linux-2.6.31.3-jz-20110420-r821.patch.gzlinux-2.6.31.3-jz

 * init version for JZ4760B on LEPUS board
 * add system build on SD card or inand for APUS<A1><A2>CETUS and LEPUS board
 * add nand_oob_218 layout mode for support 218 Bytes of oobsize.
 * change the method of make yaffs file system on LEPUS borad for JZ4760B
 * support new nand type such as K9GAG0800D and other 8k bytes  page nand
 * add otg gadget function to be removed by WIN7 or VISTA operation system support
 * add opt function for jz4760B
 * change the pll source for ohci from PLL0 to PLL1
 * add fpu support for JZ4760B

555 files changed, 180171 insertions, 15539 deletions

diff --git a/Changelog b/Changelog
index 8eb423da02c..185319cf744 100644
--- a/Changelog
+++ b/Changelog
@@ -1,3 +1,42 @@
+2011.03.11 <hpyang@ingenic.cn>
+*Note:Implement the NEW mechanism of ECC and SUPPORT 8k nand.
+Update file						Version after commit
+
+For Nand & Yaffs2
+
+linux-2.6.31.3/drivers/mtd/nand/nand_base.c
+
+linux-2.6.31.3/include/linux/mtd/mtd.h
+
+linux-2.6.31.3/include/linux/mtd/nand.h
+				
+linux-2.6.31.3/drivers/mtd/nand/nand_ids.c
+
+linux-2.6.31.3/drivers/mtd/nand/Makefile
+
+linux-2.6.31.3/drivers/mtd/nand/jz4760b_nand.c	(Add)
+	
+linux-2.6.31.3/fs/yaffs2/yaffs_fs.c
+
+linux-2.6.31.3/fs/yaffs2/yaffs_mtdif.c
+
+linux-2.6.31.3/fs/yaffs2/yaffs_mtdif2.c
+
+linux-2.6.31.3/drivers/mtd/mtdpart.c
+
+
+For VFAT
+
+linux-2.6.31.3/drivers/mtd/mtdblock-jz.c
+
+
+For Yaffs2 tool
+
+linux-2.6.31.3/fs/yaffs2/utils/Makefile
+
+linux-2.6.31.3/fs/yaffs2/utils/mkyaffs2image4760x.c (Add)
+*Note:Implement the NEW mechanism of ECC and SUPPORT 8k nand.
+
 2009.04.22
 * Which mode a partition works with, cpu mode or dma mode, could be determined by the 
   value of cpu_mode in partition_info[] in drivers/mtd/nand/jz47xx_nand.c
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 6c25c366342..e499c302c34 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -4,6 +4,8 @@ config MIPS
 	select HAVE_IDE
 	select HAVE_OPROFILE
 	select HAVE_ARCH_KGDB
+	select HAVE_KPROBES
+	select HAVE_KRETPROBES
 	# Horrible source of confusion.  Die, die, die ...
 	select EMBEDDED
 	select RTC_LIB
@@ -146,8 +148,48 @@ config JZ4760_LEPUS
 	select SYS_SUPPORTS_32BIT_KERNEL
 	select SYS_SUPPORTS_LITTLE_ENDIAN
 	select SYS_HAS_EARLY_PRINTK
+	select SYS_SUPPORTS_HIGHMEM
+	select SOC_JZ4760
+
+config JZ4760_HTB80
+        bool "SunNorth HTB80 board"
+	select DMA_NONCOHERENT
+	select SYS_HAS_CPU_MIPS32_R1
+	select SYS_SUPPORTS_32BIT_KERNEL
+	select SYS_SUPPORTS_LITTLE_ENDIAN
+	select SYS_HAS_EARLY_PRINTK
+	select SYS_SUPPORTS_HIGHMEM
 	select SOC_JZ4760
 
+config JZ4760B_CYGNUS
+        bool "Ingenic JZ4760B CYGNUS board"
+	select DMA_NONCOHERENT
+	select SYS_HAS_CPU_MIPS32_R1
+	select SYS_SUPPORTS_32BIT_KERNEL
+	select SYS_SUPPORTS_LITTLE_ENDIAN
+	select SYS_HAS_EARLY_PRINTK
+	select SOC_JZ4760B
+
+config JZ4760B_LEPUS
+	bool "Ingenic JZ4760B LEPUS board"
+	select DMA_NONCOHERENT
+	select SYS_HAS_CPU_MIPS32_R1
+	select SYS_SUPPORTS_32BIT_KERNEL
+	select SYS_SUPPORTS_LITTLE_ENDIAN
+	select SYS_HAS_EARLY_PRINTK
+	select SYS_SUPPORTS_HIGHMEM
+	select SOC_JZ4760B
+
+config JZ4770_F4770
+	bool "Ingenic JZ4770 FPGA board"
+	select DMA_NONCOHERENT
+	select SYS_HAS_CPU_MIPS32_R1
+	select SYS_SUPPORTS_32BIT_KERNEL
+	select SYS_SUPPORTS_LITTLE_ENDIAN
+	select SYS_HAS_EARLY_PRINTK
+	select SOC_JZ4770
+	select JZ_FPGA
+
 config JZ4810_F4810
 	bool "Ingenic JZ4810 FPGA board"
 	select DMA_NONCOHERENT
@@ -847,6 +889,14 @@ config SOC_JZ4760
 	bool
 	select JZSOC
 
+config SOC_JZ4760B
+	bool
+	select JZSOC
+
+config SOC_JZ4770
+	bool
+	select JZSOC
+
 config SOC_JZ4810
 	bool
 	select JZSOC
@@ -2301,9 +2351,12 @@ config ZONE_DMA32
 	bool
 
 config FORCE_MAX_ZONEORDER
-	int
+	prompt "MAX_ZONEORDER"
 	depends on JZSOC
+	int
 	default "13"
+help
+	 The max memory that can be allocated = 4KB * 2^(CONFIG_FORCE_MAX_ZONEORDER - 1)
 
 source "drivers/pcmcia/Kconfig"
 
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 5c7183d25ac..6489958ba0d 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -220,6 +220,22 @@ cflags-$(CONFIG_SOC_JZ4760)	+= -I$(srctree)/arch/mips/include/asm/mach-jz4760
 load-$(CONFIG_SOC_JZ4760)	+= 0xffffffff80010000
 
 #
+# Commond Ingenic JZ4760B series
+#
+
+core-$(CONFIG_SOC_JZ4760B)	+= arch/mips/jz4760b/
+cflags-$(CONFIG_SOC_JZ4760B)	+= -I$(srctree)/arch/mips/include/asm/mach-jz4760b
+load-$(CONFIG_SOC_JZ4760B)	+= 0xffffffff80010000
+
+#
+# Commond Ingenic JZ4770 series
+#
+
+core-$(CONFIG_SOC_JZ4770)	+= arch/mips/jz4770/
+cflags-$(CONFIG_SOC_JZ4770)	+= -I$(srctree)/arch/mips/include/asm/mach-jz4770
+load-$(CONFIG_SOC_JZ4770)	+= 0xffffffff80010000
+
+#
 # Commond Ingenic JZ4810 series
 #
 
diff --git a/arch/mips/configs/apus_defconfig b/arch/mips/configs/apus_defconfig
index 6e46ecc7c02..f325adbc0af 100644
--- a/arch/mips/configs/apus_defconfig
+++ b/arch/mips/configs/apus_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
 # Linux kernel version: 2.6.31.3
-# Fri Feb 26 12:16:04 2010
+# Fri Jan  7 14:43:41 2011
 #
 CONFIG_MIPS=y
 
@@ -19,6 +19,13 @@ CONFIG_MIPS=y
 CONFIG_JZ4750_APUS=y
 # CONFIG_JZ4750D_CETUS is not set
 # CONFIG_JZ4750L_F4750L is not set
+# CONFIG_JZ4760_F4760 is not set
+# CONFIG_JZ4760_CYGNUS is not set
+# CONFIG_JZ4760_ALTAIR is not set
+# CONFIG_JZ4760_LEPUS is not set
+# CONFIG_JZ4760B_CYGNUS is not set
+# CONFIG_JZ4760B_LEPUS is not set
+# CONFIG_JZ4810_F4810 is not set
 # CONFIG_MACH_ALCHEMY is not set
 # CONFIG_AR7 is not set
 # CONFIG_BASLER_EXCITE is not set
@@ -75,6 +82,7 @@ CONFIG_SCHED_OMIT_FRAME_POINTER=y
 CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
 CONFIG_DMA_NONCOHERENT=y
 CONFIG_DMA_NEED_PCI_MAP_STATE=y
+# CONFIG_SYS_HAS_EARLY_PRINTK is not set
 # CONFIG_NO_IOPORT is not set
 # CONFIG_CPU_BIG_ENDIAN is not set
 CONFIG_CPU_LITTLE_ENDIAN=y
@@ -237,6 +245,9 @@ CONFIG_SLUB=y
 # CONFIG_PROFILING is not set
 # CONFIG_MARKERS is not set
 CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
 
 #
 # GCOV-based kernel profiling
@@ -288,6 +299,11 @@ CONFIG_BINFMT_ELF=y
 CONFIG_TRAD_SIGNALS=y
 
 #
+# CPU Frequency scaling
+#
+# CONFIG_CPU_FREQ_JZ is not set
+
+#
 # Power management options
 #
 CONFIG_ARCH_HIBERNATION_POSSIBLE=y
@@ -462,15 +478,21 @@ CONFIG_MTD_NAND_JZ4750=y
 # CONFIG_MTD_NAND_CS3 is not set
 # CONFIG_MTD_NAND_CS4 is not set
 # CONFIG_MTD_NAND_MULTI_PLANE is not set
+CONFIG_MTD_NAND_BUS_WIDTH_8=y
+# CONFIG_MTD_NAND_BUS_WIDTH_16 is not set
 # CONFIG_MTD_HW_HM_ECC is not set
 # CONFIG_MTD_SW_HM_ECC is not set
 # CONFIG_MTD_HW_RS_ECC is not set
 CONFIG_MTD_HW_BCH_ECC=y
 # CONFIG_MTD_HW_BCH_4BIT is not set
 CONFIG_MTD_HW_BCH_8BIT=y
+# CONFIG_MTD_HW_BCH_12BIT is not set
+# CONFIG_MTD_HW_BCH_16BIT is not set
+# CONFIG_MTD_HW_BCH_20BIT is not set
+# CONFIG_MTD_HW_BCH_24BIT is not set
 CONFIG_MTD_NAND_DMA=y
 # CONFIG_MTD_NAND_DMABUF is not set
-# CONFIG_ALLOCATE_MTDBLOCK_JZ_EARLY is not set 
+# CONFIG_ALLOCATE_MTDBLOCK_JZ_EARLY is not set
 # CONFIG_MTD_MTDBLOCK_WRITE_VERIFY_ENABLE is not set
 CONFIG_MTD_OOB_COPIES=3
 CONFIG_MTD_BADBLOCK_FLAG_PAGE=127
@@ -508,6 +530,8 @@ CONFIG_BLK_DEV_RAM_SIZE=4096
 # CONFIG_ATA_OVER_ETH is not set
 # CONFIG_BLK_DEV_HD is not set
 CONFIG_MISC_DEVICES=y
+# CONFIG_JZ_I2C_SIMULATE is not set
+# CONFIG_JZ_CIM is not set
 # CONFIG_ENCLOSURE_SERVICES is not set
 # CONFIG_C2PORT is not set
 
@@ -586,6 +610,7 @@ CONFIG_PHYLIB=y
 CONFIG_NET_ETHERNET=y
 CONFIG_MII=y
 CONFIG_JZCS8900=y
+# CONFIG_JZ_AX88796C is not set
 # CONFIG_AX88796 is not set
 # CONFIG_SMC91X is not set
 # CONFIG_DM9000 is not set
@@ -719,9 +744,8 @@ CONFIG_RTC_JZ=y
 #
 CONFIG_JZCHAR=y
 # CONFIG_JZ_SIMPLE_I2C is not set
-# CONFIG_JZ_CIM is not set
+# CONFIG_JZ_GPIO_PM_KEY is not set
 # CONFIG_JZ_TPANEL_ATA2508 is not set
-# CONFIG_JZ_POWEROFF is not set
 # CONFIG_JZ_OW is not set
 CONFIG_JZ_TCSM=y
 # CONFIG_JZ_TSSI is not set
@@ -782,7 +806,7 @@ CONFIG_FB_CFB_IMAGEBLIT=y
 #
 # Frame buffer hardware drivers
 #
-# CONFIG_JZ4750_AUO_EPD_EBOOK is not set
+# CONFIG_FB_JZ475X is not set
 CONFIG_FB_JZSOC=y
 CONFIG_FB_JZ4750_LCD=y
 # CONFIG_FB_JZ4750_LCD_USE_2LAYER_FRAMEBUFFER is not set
@@ -845,7 +869,9 @@ CONFIG_SOUND_JZ_I2S=y
 # CONFIG_SOUND_JZ_PCM is not set
 # CONFIG_I2S_AK4642EN is not set
 # CONFIG_I2S_ICODEC is not set
-CONFIG_I2S_DLV=y
+CONFIG_I2S_DLV_4750=y
+# CONFIG_I2S_DLV_4760 is not set
+# CONFIG_I2S_DLV_4810 is not set
 CONFIG_HID_SUPPORT=y
 CONFIG_HID=y
 # CONFIG_HID_DEBUG is not set
@@ -922,6 +948,7 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y
 # CONFIG_USB_SL811_HCD is not set
 # CONFIG_USB_R8A66597_HCD is not set
 # CONFIG_USB_HWA_HCD is not set
+# CONFIG_USB_MUSB_HDRC is not set
 # CONFIG_USB_GADGET_MUSB_HDRC is not set
 
 #
@@ -1049,13 +1076,19 @@ CONFIG_MMC_BLOCK_BOUNCE=y
 #
 # MMC/SD/SDIO Host Controller Drivers
 #
+CONFIG_JZ_MSC=y
 CONFIG_JZ_MSC0=y
-# CONFIG_JZ4750_MSC0_BUS_1 is not set
+# CONFIG_JZ_MSC0_BUS_1 is not set
 CONFIG_JZ_MSC0_BUS_4=y
-# CONFIG_JZ4750_MSC0_BUS_8 is not set
+# CONFIG_JZ_MSC0_BUS_8 is not set
 CONFIG_JZ_MSC0_SDIO_SUPPORT=y
-# CONFIG_MSC1_JZ4750 is not set
-# CONFIG_JZ4750_BOOT_FROM_MSC0 is not set
+CONFIG_JZ_MSC1=y
+# CONFIG_JZ_MSC1_BUS_1 is not set
+CONFIG_JZ_MSC1_BUS_4=y
+# CONFIG_JZ_MSC1_BUS_8 is not set
+# CONFIG_JZ_MSC1_SDIO_SUPPORT is not set
+# CONFIG_JZ_BOOT_FROM_MSC0 is not set
+# CONFIG_JZ_FS_AT_CARD is not set
 # CONFIG_MMC_SDHCI is not set
 # CONFIG_MEMSTICK is not set
 # CONFIG_NEW_LEDS is not set
diff --git a/arch/mips/configs/cetus_defconfig b/arch/mips/configs/cetus_defconfig
index 7a7546469e4..5f0423e195d 100644
--- a/arch/mips/configs/cetus_defconfig
+++ b/arch/mips/configs/cetus_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
 # Linux kernel version: 2.6.31.3
-# Tue Oct 12 17:34:28 2010
+# Sun Mar 20 16:10:31 2011
 #
 CONFIG_MIPS=y
 
@@ -23,6 +23,10 @@ CONFIG_JZ4750D_CETUS=y
 # CONFIG_JZ4760_CYGNUS is not set
 # CONFIG_JZ4760_ALTAIR is not set
 # CONFIG_JZ4760_LEPUS is not set
+# CONFIG_JZ4760_HTB80 is not set
+# CONFIG_JZ4760B_CYGNUS is not set
+# CONFIG_JZ4760B_LEPUS is not set
+# CONFIG_JZ4770_F4770 is not set
 # CONFIG_JZ4810_F4810 is not set
 # CONFIG_MACH_ALCHEMY is not set
 # CONFIG_AR7 is not set
@@ -243,6 +247,9 @@ CONFIG_SLUB=y
 # CONFIG_PROFILING is not set
 # CONFIG_MARKERS is not set
 CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
 
 #
 # GCOV-based kernel profiling
@@ -472,7 +479,7 @@ CONFIG_MTD_NAND_JZ4750=y
 # CONFIG_MTD_NAND_CS2 is not set
 # CONFIG_MTD_NAND_CS3 is not set
 # CONFIG_MTD_NAND_CS4 is not set
-CONFIG_MTD_NAND_MULTI_PLANE=y
+# CONFIG_MTD_NAND_MULTI_PLANE is not set
 CONFIG_MTD_NAND_BUS_WIDTH_8=y
 # CONFIG_MTD_NAND_BUS_WIDTH_16 is not set
 # CONFIG_MTD_HW_HM_ECC is not set
@@ -777,6 +784,8 @@ CONFIG_JZ4750_LCD_AUO_A043FL01V2=y
 # CONFIG_JZ4750_LCD_TRULY_TFT_GG1P0319LTSW_W is not set
 # CONFIG_JZ4750_SLCD_KGM701A3_TFT_SPFD5420A is not set
 # CONFIG_JZ4750D_VGA_DISPLAY is not set
+# CONFIG_FB_JZ4760_TVE is not set
+# CONFIG_JZ4760_HDMI_DISPLAY is not set
 # CONFIG_FB_S1D13XXX is not set
 # CONFIG_FB_VIRTUAL is not set
 # CONFIG_FB_METRONOME is not set
@@ -823,6 +832,7 @@ CONFIG_SOUND_JZ_I2S=y
 # CONFIG_I2S_ICODEC is not set
 CONFIG_I2S_DLV_4750=y
 # CONFIG_I2S_DLV_4760 is not set
+# CONFIG_I2S_DLV_4810 is not set
 CONFIG_HID_SUPPORT=y
 CONFIG_HID=y
 # CONFIG_HID_DEBUG is not set
@@ -906,7 +916,7 @@ CONFIG_MMC_BLOCK_BOUNCE=y
 #
 # MMC/SD/SDIO Host Controller Drivers
 #
-# CONFIG_JZ_MSC0 is not set
+CONFIG_MMC_JZSOC=y
 # CONFIG_JZ_MSC1 is not set
 # CONFIG_MMC_SDHCI is not set
 # CONFIG_MEMSTICK is not set
diff --git a/arch/mips/configs/cygnus60b_defconfig b/arch/mips/configs/cygnus60b_defconfig
new file mode 100644
index 00000000000..5399cbb803b
--- /dev/null
+++ b/arch/mips/configs/cygnus60b_defconfig
@@ -0,0 +1,1340 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.31.3
+# Thu Mar 10 11:12:58 2011
+#
+CONFIG_MIPS=y
+
+#
+# Machine selection
+#
+# CONFIG_JZ4730_PMP is not set
+# CONFIG_JZ4740_PAVO is not set
+# CONFIG_JZ4740_LEO is not set
+# CONFIG_JZ4740_LYRA is not set
+# CONFIG_JZ4725_DIPPER is not set
+# CONFIG_JZ4720_VIRGO is not set
+# CONFIG_JZ4750_FUWA is not set
+# CONFIG_JZ4750D_FUWA1 is not set
+# CONFIG_JZ4750_APUS is not set
+# CONFIG_JZ4750D_CETUS is not set
+# CONFIG_JZ4750L_F4750L is not set
+# CONFIG_JZ4760_F4760 is not set
+# CONFIG_JZ4760_CYGNUS is not set
+# CONFIG_JZ4760_ALTAIR is not set
+# CONFIG_JZ4760_LEPUS is not set
+# CONFIG_JZ4760_HTB80 is not set
+CONFIG_JZ4760B_CYGNUS=y
+# CONFIG_JZ4760B_LEPUS is not set
+# CONFIG_JZ4770_F4770 is not set
+# CONFIG_JZ4810_F4810 is not set
+# CONFIG_MACH_ALCHEMY is not set
+# CONFIG_AR7 is not set
+# CONFIG_BASLER_EXCITE is not set
+# CONFIG_BCM47XX is not set
+# CONFIG_MIPS_COBALT is not set
+# CONFIG_MACH_DECSTATION is not set
+# CONFIG_MACH_JAZZ is not set
+# CONFIG_LASAT is not set
+# CONFIG_LEMOTE_FULONG is not set
+# CONFIG_MIPS_MALTA is not set
+# CONFIG_MIPS_SIM is not set
+# CONFIG_NEC_MARKEINS is not set
+# CONFIG_MACH_VR41XX is not set
+# CONFIG_NXP_STB220 is not set
+# CONFIG_NXP_STB225 is not set
+# CONFIG_PNX8550_JBS is not set
+# CONFIG_PNX8550_STB810 is not set
+# CONFIG_PMC_MSP is not set
+# CONFIG_PMC_YOSEMITE is not set
+# CONFIG_SGI_IP22 is not set
+# CONFIG_SGI_IP27 is not set
+# CONFIG_SGI_IP28 is not set
+# CONFIG_SGI_IP32 is not set
+# CONFIG_SIBYTE_CRHINE is not set
+# CONFIG_SIBYTE_CARMEL is not set
+# CONFIG_SIBYTE_CRHONE is not set
+# CONFIG_SIBYTE_RHONE is not set
+# CONFIG_SIBYTE_SWARM is not set
+# CONFIG_SIBYTE_LITTLESUR is not set
+# CONFIG_SIBYTE_SENTOSA is not set
+# CONFIG_SIBYTE_BIGSUR is not set
+# CONFIG_SNI_RM is not set
+# CONFIG_MACH_TX39XX is not set
+# CONFIG_MACH_TX49XX is not set
+# CONFIG_MIKROTIK_RB532 is not set
+# CONFIG_WR_PPMC is not set
+# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set
+# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set
+# CONFIG_ALCHEMY_GPIO_INDIRECT is not set
+CONFIG_SOC_JZ4760B=y
+CONFIG_JZSOC=y
+CONFIG_JZRISC=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_SUPPORTS_OPROFILE=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_SCHED_OMIT_FRAME_POINTER=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_DMA_NEED_PCI_MAP_STATE=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+# CONFIG_NO_IOPORT is not set
+# CONFIG_CPU_BIG_ENDIAN is not set
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+
+#
+# CPU selection
+#
+# CONFIG_CPU_LOONGSON2 is not set
+CONFIG_CPU_MIPS32_R1=y
+# CONFIG_CPU_MIPS32_R2 is not set
+# CONFIG_CPU_MIPS64_R1 is not set
+# CONFIG_CPU_MIPS64_R2 is not set
+# CONFIG_CPU_R3000 is not set
+# CONFIG_CPU_TX39XX is not set
+# CONFIG_CPU_VR41XX is not set
+# CONFIG_CPU_R4300 is not set
+# CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_TX49XX is not set
+# CONFIG_CPU_R5000 is not set
+# CONFIG_CPU_R5432 is not set
+# CONFIG_CPU_R5500 is not set
+# CONFIG_CPU_R6000 is not set
+# CONFIG_CPU_NEVADA is not set
+# CONFIG_CPU_R8000 is not set
+# CONFIG_CPU_R10000 is not set
+# CONFIG_CPU_RM7000 is not set
+# CONFIG_CPU_RM9000 is not set
+# CONFIG_CPU_SB1 is not set
+# CONFIG_CPU_CAVIUM_OCTEON is not set
+CONFIG_SYS_HAS_CPU_MIPS32_R1=y
+CONFIG_CPU_MIPS32=y
+CONFIG_CPU_MIPSR1=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_HARDWARE_WATCHPOINTS=y
+
+#
+# Kernel type
+#
+CONFIG_32BIT=y
+# CONFIG_64BIT is not set
+CONFIG_PAGE_SIZE_4KB=y
+# CONFIG_PAGE_SIZE_8KB is not set
+# CONFIG_PAGE_SIZE_16KB is not set
+# CONFIG_PAGE_SIZE_32KB is not set
+# CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_MIPS_MT_DISABLED=y
+# CONFIG_MIPS_MT_SMP is not set
+# CONFIG_MIPS_MT_SMTC is not set
+CONFIG_CPU_HAS_LLSC=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_HZ_48 is not set
+CONFIG_HZ_100=y
+# CONFIG_HZ_128 is not set
+# CONFIG_HZ_250 is not set
+# CONFIG_HZ_256 is not set
+# CONFIG_HZ_1000 is not set
+# CONFIG_HZ_1024 is not set
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_HZ=100
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+# CONFIG_KEXEC is not set
+CONFIG_SECCOMP=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+# CONFIG_NAMESPACES is not set
+# CONFIG_BLK_DEV_INITRD is not set
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EMBEDDED=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_PCSPKR_PLATFORM=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+
+#
+# Performance Counters
+#
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+# CONFIG_STRIP_ASM_SYMS is not set
+CONFIG_COMPAT_BRK=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_SLOW_WORK is not set
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_FREEZER=y
+
+#
+# Bus options (PCI, PCMCIA, EISA, ISA, TC)
+#
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_MMU=y
+CONFIG_FORCE_MAX_ZONEORDER=13
+# CONFIG_PCCARD is not set
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_HAVE_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+CONFIG_TRAD_SIGNALS=y
+
+#
+# CPU Frequency scaling
+#
+# CONFIG_CPU_FREQ_JZ is not set
+
+#
+# Power management options
+#
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+# CONFIG_HIBERNATION is not set
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_WIRELESS is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH=""
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_JZ4760B=y
+# CONFIG_MTD_NAND_CS2 is not set
+# CONFIG_MTD_NAND_CS3 is not set
+# CONFIG_MTD_NAND_CS4 is not set
+CONFIG_MTD_NAND_MULTI_PLANE=y
+CONFIG_MTD_NAND_BUS_WIDTH_8=y
+# CONFIG_MTD_NAND_BUS_WIDTH_16 is not set
+# CONFIG_MTD_HW_HM_ECC is not set
+# CONFIG_MTD_SW_HM_ECC is not set
+# CONFIG_MTD_HW_RS_ECC is not set
+CONFIG_MTD_HW_BCH_ECC=y
+# CONFIG_MTD_HW_BCH_4BIT is not set
+CONFIG_MTD_HW_BCH_8BIT=y
+# CONFIG_MTD_HW_BCH_12BIT is not set
+# CONFIG_MTD_HW_BCH_16BIT is not set
+# CONFIG_MTD_HW_BCH_20BIT is not set
+# CONFIG_MTD_HW_BCH_24BIT is not set
+CONFIG_MTD_NAND_DMA=y
+# CONFIG_MTD_NAND_DMABUF is not set
+# CONFIG_ALLOCATE_MTDBLOCK_JZ_EARLY is not set
+# CONFIG_MTD_MTDBLOCK_WRITE_VERIFY_ENABLE is not set
+CONFIG_MTD_OOB_COPIES=3
+CONFIG_MTD_BADBLOCK_FLAG_PAGE=127
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_HD is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_SCSI_PROC_FS is not set
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_LSI_ET1011C_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+CONFIG_JZCS8900=y
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_ETHOC is not set
+# CONFIG_DNET is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=2
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_RTC_PCF8563 is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+
+#
+# JZSOC char device support
+#
+CONFIG_JZCHAR=y
+CONFIG_JZ_TCSM=y
+# CONFIG_JZ_TSSI is not set
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+CONFIG_FB_JZSOC=y
+CONFIG_FB_JZ4760_LCD=y
+# CONFIG_FB_JZ4760_LCD_USE_2LAYER_FRAMEBUFFER is not set
+# CONFIG_FB_JZ4760_TVE is not set
+# CONFIG_JZ4760_HDMI_DISPLAY is not set
+CONFIG_JZ4760_IPU_MM=y
+# CONFIG_FB_JZ4760_SLCD is not set
+# CONFIG_JZ4760_LCD_SAMSUNG_LTP400WQF01 is not set
+CONFIG_JZ4760_LCD_SAMSUNG_LTP400WQF02=y
+# CONFIG_JZ4760_LCD_AUO_A043FL01V2 is not set
+# CONFIG_JZ4760_LCD_FOXCONN_PT035TN01 is not set
+# CONFIG_JZ4760_LCD_INNOLUX_PT035TN01_SERIAL is not set
+# CONFIG_JZ4760_LCD_TOPPOLY_TD025THEA7_RGB_DELTA is not set
+# CONFIG_JZ4760_LCD_TOPPOLY_TD043MGEB1 is not set
+# CONFIG_JZ4760_LCD_TRULY_TFTG320240DTSW_18BIT is not set
+# CONFIG_JZ4760_LCD_TRULY_TFT_GG1P0319LTSW_W is not set
+# CONFIG_JZ4760_SLCD_KGM701A3_TFT_SPFD5420A is not set
+# CONFIG_JZ4760_VGA_DISPLAY is not set
+# CONFIG_FB_JZ4760_EPD is not set
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_BROADSHEET is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_CURSOR_FLASH is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LOGO_LINUX_CLUT224=y
+CONFIG_SOUND=y
+CONFIG_SOUND_OSS_CORE=y
+# CONFIG_SND is not set
+CONFIG_SOUND_PRIME=y
+# CONFIG_SOUND_JZ_AC97 is not set
+CONFIG_SOUND_JZ_I2S=y
+# CONFIG_I2S_AK4642EN is not set
+# CONFIG_I2S_ICODEC is not set
+# CONFIG_I2S_DLV_4750 is not set
+CONFIG_I2S_DLV_4760=y
+# CONFIG_I2S_DLV_4810 is not set
+# CONFIG_HID_SUPPORT is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+# CONFIG_USB_DEVICEFS is not set
+# CONFIG_USB_DEVICE_CLASS is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+CONFIG_USB_SUSPEND=y
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_MON is not set
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+CONFIG_USB_MUSB_HDRC=y
+CONFIG_USB_MUSB_SOC=y
+
+#
+# Ingenic OTG USB support
+#
+# CONFIG_USB_MUSB_HOST is not set
+CONFIG_USB_MUSB_PERIPHERAL=y
+# CONFIG_USB_MUSB_OTG is not set
+# CONFIG_USB_MUSB_PERIPHERAL_HOTPLUG is not set
+CONFIG_USB_GADGET_MUSB_HDRC=y
+# CONFIG_MUSB_PIO_ONLY is not set
+CONFIG_USB_INVENTRA_DMA=y
+# CONFIG_USB_TI_CPPI_DMA is not set
+# CONFIG_USB_MUSB_DEBUG is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+CONFIG_USB_LIBUSUAL=y
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+CONFIG_USB_GADGET=m
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_JZ4740 is not set
+# CONFIG_USB_GADGET_JZ4750 is not set
+# CONFIG_USB_GADGET_JZ4750D is not set
+# CONFIG_USB_GADGET_JZ4750L is not set
+# CONFIG_USB_GADGET_JZ4730 is not set
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_S3C_HSOTG is not set
+# CONFIG_USB_GADGET_IMX is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_CI13XXX is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LANGWELL is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+CONFIG_USB_GADGET_DUALSPEED=y
+# CONFIG_JZ_UDC_HOTPLUG is not set
+# CONFIG_USB_ZERO is not set
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_ETH is not set
+# CONFIG_USB_GADGETFS is not set
+CONFIG_USB_FILE_STORAGE=m
+# CONFIG_USB_FILE_STORAGE_TEST is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+# CONFIG_USB_CDC_COMPOSITE is not set
+
+#
+# OTG and related infrastructure
+#
+CONFIG_USB_OTG_UTILS=y
+CONFIG_NOP_USB_XCEIV=y
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+CONFIG_MMC_JZSOC=y
+# CONFIG_JZ_MSC0 is not set
+CONFIG_JZ_MSC1=y
+# CONFIG_JZ_MSC1_BUS_1 is not set
+CONFIG_JZ_MSC1_BUS_4=y
+# CONFIG_JZ_MSC1_BUS_8 is not set
+# CONFIG_JZ_MSC1_SDIO_SUPPORT is not set
+# CONFIG_JZ_MSC2 is not set
+# CONFIG_MMC_SDHCI is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+
+#
+# TI VLYNQ
+#
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+# CONFIG_EXT2_FS_POSIX_ACL is not set
+# CONFIG_EXT2_FS_SECURITY is not set
+# CONFIG_EXT2_FS_XIP is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4_FS is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+# CONFIG_MISC_FILESYSTEMS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+CONFIG_NFS_V4=y
+# CONFIG_NFS_V4_1 is not set
+CONFIG_ROOT_NFS=y
+CONFIG_NFSD=y
+CONFIG_NFSD_V3=y
+# CONFIG_NFSD_V3_ACL is not set
+CONFIG_NFSD_V4=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_EXPORTFS=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+CONFIG_RPCSEC_GSS_KRB5=y
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="cp437"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+CONFIG_NLS_CODEPAGE_936=y
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=y
+# CONFIG_DLM is not set
+
+#
+# Yaffs2 Filesystems
+#
+CONFIG_YAFFS_FS=y
+CONFIG_YAFFS_YAFFS1=y
+# CONFIG_YAFFS_DOES_ECC is not set
+CONFIG_YAFFS_YAFFS2=y
+CONFIG_YAFFS_AUTO_YAFFS2=y
+# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
+# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
+CONFIG_YAFFS_DISABLE_CHUNK_ERASED_CHECK=y
+CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
+CONFIG_YAFFS_CHECKPOINT_RESERVED_BLOCKS=10
+
+#
+# Kernel hacking
+#
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_CMDLINE=""
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+CONFIG_CRYPTO_WORKQUEUE=y
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=y
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=y
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_ZLIB is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_HW=y
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/mips/configs/cygnus_defconfig b/arch/mips/configs/cygnus_defconfig
index 7ca7993207c..88e4ec9ddde 100644
--- a/arch/mips/configs/cygnus_defconfig
+++ b/arch/mips/configs/cygnus_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
 # Linux kernel version: 2.6.31.3
-# Wed May 19 11:25:42 2010
+# Fri Mar  4 12:18:46 2011
 #
 CONFIG_MIPS=y
 
@@ -22,6 +22,12 @@ CONFIG_MIPS=y
 # CONFIG_JZ4760_F4760 is not set
 CONFIG_JZ4760_CYGNUS=y
 # CONFIG_JZ4760_ALTAIR is not set
+# CONFIG_JZ4760_LEPUS is not set
+# CONFIG_JZ4760_HTB80 is not set
+# CONFIG_JZ4760B_CYGNUS is not set
+# CONFIG_JZ4760B_LEPUS is not set
+# CONFIG_JZ4770_F4770 is not set
+# CONFIG_JZ4810_F4810 is not set
 # CONFIG_MACH_ALCHEMY is not set
 # CONFIG_AR7 is not set
 # CONFIG_BASLER_EXCITE is not set
@@ -243,6 +249,9 @@ CONFIG_SLUB=y
 # CONFIG_PROFILING is not set
 # CONFIG_MARKERS is not set
 CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
 
 #
 # GCOV-based kernel profiling
@@ -476,7 +485,8 @@ CONFIG_MTD_HW_BCH_8BIT=y
 # CONFIG_MTD_HW_BCH_16BIT is not set
 # CONFIG_MTD_HW_BCH_20BIT is not set
 # CONFIG_MTD_HW_BCH_24BIT is not set
-# CONFIG_MTD_NAND_DMA is not set
+CONFIG_MTD_NAND_DMA=y
+# CONFIG_MTD_NAND_DMABUF is not set
 # CONFIG_ALLOCATE_MTDBLOCK_JZ_EARLY is not set
 # CONFIG_MTD_MTDBLOCK_WRITE_VERIFY_ENABLE is not set
 CONFIG_MTD_OOB_COPIES=3
@@ -587,6 +597,7 @@ CONFIG_NET_ETHERNET=y
 CONFIG_MII=y
 CONFIG_JZCS8900=y
 # CONFIG_JZ4760_ETH is not set
+# CONFIG_JZ_AX88796C is not set
 # CONFIG_AX88796 is not set
 # CONFIG_SMC91X is not set
 # CONFIG_DM9000 is not set
@@ -694,11 +705,57 @@ CONFIG_LEGACY_PTY_COUNT=2
 # CONFIG_IPMI_HANDLER is not set
 # CONFIG_HW_RANDOM is not set
 # CONFIG_RTC_PCF8563 is not set
-CONFIG_RTC_JZ=y
+# CONFIG_RTC_JZ4760 is not set
 # CONFIG_R3964 is not set
 # CONFIG_RAW_DRIVER is not set
 # CONFIG_TCG_TPM is not set
-# CONFIG_I2C is not set
+
+#
+# JZSOC char device support
+#
+# CONFIG_JZCHAR is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+# CONFIG_I2C_CHARDEV is not set
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+# CONFIG_I2C0_JZ4760 is not set
+CONFIG_I2C1_JZ4760=y
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
 # CONFIG_SPI is not set
 
 #
@@ -724,7 +781,13 @@ CONFIG_SSB_POSSIBLE=y
 # CONFIG_MFD_CORE is not set
 # CONFIG_MFD_SM501 is not set
 # CONFIG_HTC_PASIC3 is not set
+# CONFIG_TWL4030_CORE is not set
 # CONFIG_MFD_TMIO is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_AB3100_CORE is not set
 # CONFIG_REGULATOR is not set
 # CONFIG_MEDIA_SUPPORT is not set
 
@@ -822,6 +885,7 @@ CONFIG_USB_MUSB_SOC=y
 # CONFIG_USB_MUSB_HOST is not set
 CONFIG_USB_MUSB_PERIPHERAL=y
 # CONFIG_USB_MUSB_OTG is not set
+# CONFIG_USB_MUSB_PERIPHERAL_HOTPLUG is not set
 CONFIG_USB_GADGET_MUSB_HDRC=y
 # CONFIG_MUSB_PIO_ONLY is not set
 CONFIG_USB_INVENTRA_DMA=y
@@ -938,7 +1002,31 @@ CONFIG_USB_FILE_STORAGE=m
 #
 CONFIG_USB_OTG_UTILS=y
 CONFIG_NOP_USB_XCEIV=y
-# CONFIG_MMC is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+CONFIG_MMC_JZSOC=y
+# CONFIG_JZ_MSC0 is not set
+CONFIG_JZ_MSC1=y
+# CONFIG_JZ_MSC1_BUS_1 is not set
+CONFIG_JZ_MSC1_BUS_4=y
+# CONFIG_JZ_MSC1_BUS_8 is not set
+# CONFIG_JZ_MSC1_SDIO_SUPPORT is not set
+# CONFIG_JZ_MSC2 is not set
+# CONFIG_JZ_FS_AT_CARD is not set
+# CONFIG_MMC_SDHCI is not set
 # CONFIG_MEMSTICK is not set
 # CONFIG_NEW_LEDS is not set
 # CONFIG_ACCESSIBILITY is not set
@@ -1106,7 +1194,16 @@ CONFIG_NLS_UTF8=y
 #
 # Yaffs2 Filesystems
 #
-# CONFIG_YAFFS_FS is not set
+CONFIG_YAFFS_FS=y
+CONFIG_YAFFS_YAFFS1=y
+# CONFIG_YAFFS_DOES_ECC is not set
+CONFIG_YAFFS_YAFFS2=y
+CONFIG_YAFFS_AUTO_YAFFS2=y
+# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
+# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
+CONFIG_YAFFS_DISABLE_CHUNK_ERASED_CHECK=y
+CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
+CONFIG_YAFFS_CHECKPOINT_RESERVED_BLOCKS=10
 
 #
 # Kernel hacking
diff --git a/arch/mips/configs/f4770_defconfig b/arch/mips/configs/f4770_defconfig
new file mode 100644
index 00000000000..64de5fc1bd7
--- /dev/null
+++ b/arch/mips/configs/f4770_defconfig
@@ -0,0 +1,1073 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.31.3
+# Wed Feb 23 17:12:41 2011
+#
+CONFIG_MIPS=y
+
+#
+# Machine selection
+#
+# CONFIG_JZ4730_PMP is not set
+# CONFIG_JZ4740_PAVO is not set
+# CONFIG_JZ4740_LEO is not set
+# CONFIG_JZ4740_LYRA is not set
+# CONFIG_JZ4725_DIPPER is not set
+# CONFIG_JZ4720_VIRGO is not set
+# CONFIG_JZ4750_FUWA is not set
+# CONFIG_JZ4750D_FUWA1 is not set
+# CONFIG_JZ4750_APUS is not set
+# CONFIG_JZ4750D_CETUS is not set
+# CONFIG_JZ4750L_F4750L is not set
+# CONFIG_JZ4760_F4760 is not set
+# CONFIG_JZ4760_CYGNUS is not set
+# CONFIG_JZ4760_ALTAIR is not set
+# CONFIG_JZ4760_LEPUS is not set
+# CONFIG_JZ4760_HTB80 is not set
+# CONFIG_JZ4760B_CYGNUS is not set
+# CONFIG_JZ4760B_LEPUS is not set
+CONFIG_JZ4770_F4770=y
+# CONFIG_JZ4810_F4810 is not set
+# CONFIG_MACH_ALCHEMY is not set
+# CONFIG_AR7 is not set
+# CONFIG_BASLER_EXCITE is not set
+# CONFIG_BCM47XX is not set
+# CONFIG_MIPS_COBALT is not set
+# CONFIG_MACH_DECSTATION is not set
+# CONFIG_MACH_JAZZ is not set
+# CONFIG_LASAT is not set
+# CONFIG_LEMOTE_FULONG is not set
+# CONFIG_MIPS_MALTA is not set
+# CONFIG_MIPS_SIM is not set
+# CONFIG_NEC_MARKEINS is not set
+# CONFIG_MACH_VR41XX is not set
+# CONFIG_NXP_STB220 is not set
+# CONFIG_NXP_STB225 is not set
+# CONFIG_PNX8550_JBS is not set
+# CONFIG_PNX8550_STB810 is not set
+# CONFIG_PMC_MSP is not set
+# CONFIG_PMC_YOSEMITE is not set
+# CONFIG_SGI_IP22 is not set
+# CONFIG_SGI_IP27 is not set
+# CONFIG_SGI_IP28 is not set
+# CONFIG_SGI_IP32 is not set
+# CONFIG_SIBYTE_CRHINE is not set
+# CONFIG_SIBYTE_CARMEL is not set
+# CONFIG_SIBYTE_CRHONE is not set
+# CONFIG_SIBYTE_RHONE is not set
+# CONFIG_SIBYTE_SWARM is not set
+# CONFIG_SIBYTE_LITTLESUR is not set
+# CONFIG_SIBYTE_SENTOSA is not set
+# CONFIG_SIBYTE_BIGSUR is not set
+# CONFIG_SNI_RM is not set
+# CONFIG_MACH_TX39XX is not set
+# CONFIG_MACH_TX49XX is not set
+# CONFIG_MIKROTIK_RB532 is not set
+# CONFIG_WR_PPMC is not set
+# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set
+# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set
+# CONFIG_ALCHEMY_GPIO_INDIRECT is not set
+CONFIG_SOC_JZ4770=y
+CONFIG_JZ_FPGA=y
+CONFIG_JZSOC=y
+CONFIG_JZRISC=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_SUPPORTS_OPROFILE=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_SCHED_OMIT_FRAME_POINTER=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_DMA_NEED_PCI_MAP_STATE=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+# CONFIG_NO_IOPORT is not set
+# CONFIG_CPU_BIG_ENDIAN is not set
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+
+#
+# CPU selection
+#
+# CONFIG_CPU_LOONGSON2 is not set
+CONFIG_CPU_MIPS32_R1=y
+# CONFIG_CPU_MIPS32_R2 is not set
+# CONFIG_CPU_MIPS64_R1 is not set
+# CONFIG_CPU_MIPS64_R2 is not set
+# CONFIG_CPU_R3000 is not set
+# CONFIG_CPU_TX39XX is not set
+# CONFIG_CPU_VR41XX is not set
+# CONFIG_CPU_R4300 is not set
+# CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_TX49XX is not set
+# CONFIG_CPU_R5000 is not set
+# CONFIG_CPU_R5432 is not set
+# CONFIG_CPU_R5500 is not set
+# CONFIG_CPU_R6000 is not set
+# CONFIG_CPU_NEVADA is not set
+# CONFIG_CPU_R8000 is not set
+# CONFIG_CPU_R10000 is not set
+# CONFIG_CPU_RM7000 is not set
+# CONFIG_CPU_RM9000 is not set
+# CONFIG_CPU_SB1 is not set
+# CONFIG_CPU_CAVIUM_OCTEON is not set
+CONFIG_SYS_HAS_CPU_MIPS32_R1=y
+CONFIG_CPU_MIPS32=y
+CONFIG_CPU_MIPSR1=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_HARDWARE_WATCHPOINTS=y
+
+#
+# Kernel type
+#
+CONFIG_32BIT=y
+# CONFIG_64BIT is not set
+CONFIG_PAGE_SIZE_4KB=y
+# CONFIG_PAGE_SIZE_8KB is not set
+# CONFIG_PAGE_SIZE_16KB is not set
+# CONFIG_PAGE_SIZE_32KB is not set
+# CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_MIPS_MT_DISABLED=y
+# CONFIG_MIPS_MT_SMP is not set
+# CONFIG_MIPS_MT_SMTC is not set
+CONFIG_CPU_HAS_LLSC=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_HZ_48 is not set
+CONFIG_HZ_100=y
+# CONFIG_HZ_128 is not set
+# CONFIG_HZ_250 is not set
+# CONFIG_HZ_256 is not set
+# CONFIG_HZ_1000 is not set
+# CONFIG_HZ_1024 is not set
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_HZ=100
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+# CONFIG_KEXEC is not set
+CONFIG_SECCOMP=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+# CONFIG_NAMESPACES is not set
+# CONFIG_BLK_DEV_INITRD is not set
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EMBEDDED=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_PCSPKR_PLATFORM=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+
+#
+# Performance Counters
+#
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+# CONFIG_STRIP_ASM_SYMS is not set
+CONFIG_COMPAT_BRK=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_SLOW_WORK is not set
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_FREEZER=y
+
+#
+# Bus options (PCI, PCMCIA, EISA, ISA, TC)
+#
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_MMU=y
+CONFIG_FORCE_MAX_ZONEORDER=13
+# CONFIG_PCCARD is not set
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_HAVE_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+CONFIG_TRAD_SIGNALS=y
+
+#
+# CPU Frequency scaling
+#
+# CONFIG_CPU_FREQ_JZ is not set
+
+#
+# Power management options
+#
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+# CONFIG_HIBERNATION is not set
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_WIRELESS is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH=""
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_JZ4770=y
+# CONFIG_MTD_NAND_CS2 is not set
+# CONFIG_MTD_NAND_CS3 is not set
+# CONFIG_MTD_NAND_CS4 is not set
+# CONFIG_MTD_NAND_MULTI_PLANE is not set
+CONFIG_MTD_NAND_BUS_WIDTH_8=y
+# CONFIG_MTD_NAND_BUS_WIDTH_16 is not set
+# CONFIG_MTD_HW_HM_ECC is not set
+# CONFIG_MTD_SW_HM_ECC is not set
+# CONFIG_MTD_HW_RS_ECC is not set
+CONFIG_MTD_HW_BCH_ECC=y
+# CONFIG_MTD_HW_BCH_4BIT is not set
+CONFIG_MTD_HW_BCH_8BIT=y
+# CONFIG_MTD_HW_BCH_12BIT is not set
+# CONFIG_MTD_HW_BCH_16BIT is not set
+# CONFIG_MTD_HW_BCH_20BIT is not set
+# CONFIG_MTD_HW_BCH_24BIT is not set
+CONFIG_MTD_NAND_DMA=y
+# CONFIG_MTD_NAND_DMABUF is not set
+# CONFIG_ALLOCATE_MTDBLOCK_JZ_EARLY is not set
+# CONFIG_MTD_MTDBLOCK_WRITE_VERIFY_ENABLE is not set
+CONFIG_MTD_OOB_COPIES=3
+CONFIG_MTD_BADBLOCK_FLAG_PAGE=0
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_HD is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_SCSI_PROC_FS is not set
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_LSI_ET1011C_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_JZ_ETH is not set
+CONFIG_JZ4760_ETH=y
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_ETHOC is not set
+# CONFIG_DNET is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=2
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_RTC_PCF8563 is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_SOUND is not set
+# CONFIG_HID_SUPPORT is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+
+#
+# TI VLYNQ
+#
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+# CONFIG_EXT2_FS_POSIX_ACL is not set
+# CONFIG_EXT2_FS_SECURITY is not set
+# CONFIG_EXT2_FS_XIP is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4_FS is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+# CONFIG_MISC_FILESYSTEMS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+CONFIG_NFS_V4=y
+# CONFIG_NFS_V4_1 is not set
+CONFIG_ROOT_NFS=y
+CONFIG_NFSD=y
+CONFIG_NFSD_V3=y
+# CONFIG_NFSD_V3_ACL is not set
+CONFIG_NFSD_V4=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_EXPORTFS=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+CONFIG_RPCSEC_GSS_KRB5=y
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="cp437"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+CONFIG_NLS_CODEPAGE_936=y
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=y
+# CONFIG_DLM is not set
+
+#
+# Yaffs2 Filesystems
+#
+CONFIG_YAFFS_FS=y
+CONFIG_YAFFS_YAFFS1=y
+# CONFIG_YAFFS_DOES_ECC is not set
+CONFIG_YAFFS_YAFFS2=y
+CONFIG_YAFFS_AUTO_YAFFS2=y
+# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
+# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
+CONFIG_YAFFS_DISABLE_CHUNK_ERASED_CHECK=y
+CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
+CONFIG_YAFFS_CHECKPOINT_RESERVED_BLOCKS=10
+
+#
+# Kernel hacking
+#
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_CMDLINE=""
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+CONFIG_CRYPTO_WORKQUEUE=y
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=y
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=y
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_ZLIB is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_HW=y
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_GENERIC_FIND_LAST_BIT=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+# CONFIG_CRC32 is not set
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/mips/configs/f4810_defconfig b/arch/mips/configs/f4810_defconfig
index 8f83253bc76..d6a95b5a2d5 100644
--- a/arch/mips/configs/f4810_defconfig
+++ b/arch/mips/configs/f4810_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
 # Linux kernel version: 2.6.31.3
-# Sat Jun 19 16:47:21 2010
+# Fri Dec 10 15:32:55 2010
 #
 CONFIG_MIPS=y
 
@@ -22,6 +22,9 @@ CONFIG_MIPS=y
 # CONFIG_JZ4760_F4760 is not set
 # CONFIG_JZ4760_CYGNUS is not set
 # CONFIG_JZ4760_ALTAIR is not set
+# CONFIG_JZ4760_LEPUS is not set
+# CONFIG_JZ4760B_CYGNUS is not set
+# CONFIG_JZ4760B_LEPUS is not set
 CONFIG_JZ4810_F4810=y
 # CONFIG_MACH_ALCHEMY is not set
 # CONFIG_AR7 is not set
@@ -399,7 +402,109 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
 # CONFIG_FW_LOADER is not set
 # CONFIG_SYS_HYPERVISOR is not set
 # CONFIG_CONNECTOR is not set
-# CONFIG_MTD is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_JZ4810=y
+# CONFIG_MTD_NAND_CS2 is not set
+# CONFIG_MTD_NAND_CS3 is not set
+# CONFIG_MTD_NAND_CS4 is not set
+# CONFIG_MTD_NAND_MULTI_PLANE is not set
+CONFIG_MTD_NAND_BUS_WIDTH_8=y
+# CONFIG_MTD_NAND_BUS_WIDTH_16 is not set
+# CONFIG_MTD_HW_HM_ECC is not set
+# CONFIG_MTD_SW_HM_ECC is not set
+# CONFIG_MTD_HW_RS_ECC is not set
+CONFIG_MTD_HW_BCH_ECC=y
+# CONFIG_MTD_HW_BCH_4BIT is not set
+CONFIG_MTD_HW_BCH_8BIT=y
+# CONFIG_MTD_HW_BCH_12BIT is not set
+# CONFIG_MTD_HW_BCH_16BIT is not set
+# CONFIG_MTD_HW_BCH_20BIT is not set
+# CONFIG_MTD_HW_BCH_24BIT is not set
+CONFIG_MTD_NAND_DMA=y
+# CONFIG_MTD_NAND_DMABUF is not set
+# CONFIG_ALLOCATE_MTDBLOCK_JZ_EARLY is not set
+# CONFIG_MTD_MTDBLOCK_WRITE_VERIFY_ENABLE is not set
+CONFIG_MTD_OOB_COPIES=3
+CONFIG_MTD_BADBLOCK_FLAG_PAGE=0
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
 # CONFIG_PARPORT is not set
 CONFIG_BLK_DEV=y
 # CONFIG_BLK_DEV_COW_COMMON is not set
@@ -485,7 +590,6 @@ CONFIG_PHYLIB=y
 CONFIG_NET_ETHERNET=y
 CONFIG_MII=y
 # CONFIG_JZ_ETH is not set
-# CONFIG_JZCS8900 is not set
 CONFIG_JZ4760_ETH=y
 # CONFIG_AX88796 is not set
 # CONFIG_SMC91X is not set
@@ -585,7 +689,6 @@ CONFIG_LEGACY_PTY_COUNT=2
 # CONFIG_IPMI_HANDLER is not set
 # CONFIG_HW_RANDOM is not set
 # CONFIG_RTC_PCF8563 is not set
-# CONFIG_RTC_JZ is not set
 # CONFIG_R3964 is not set
 # CONFIG_RAW_DRIVER is not set
 # CONFIG_TCG_TPM is not set
@@ -808,6 +911,16 @@ CONFIG_NLS_UTF8=y
 #
 # Yaffs2 Filesystems
 #
+CONFIG_YAFFS_FS=y
+CONFIG_YAFFS_YAFFS1=y
+# CONFIG_YAFFS_DOES_ECC is not set
+CONFIG_YAFFS_YAFFS2=y
+CONFIG_YAFFS_AUTO_YAFFS2=y
+# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
+# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
+CONFIG_YAFFS_DISABLE_CHUNK_ERASED_CHECK=y
+CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
+CONFIG_YAFFS_CHECKPOINT_RESERVED_BLOCKS=10
 
 #
 # Kernel hacking
diff --git a/arch/mips/configs/htb80_defconfig b/arch/mips/configs/htb80_defconfig
new file mode 100644
index 00000000000..e277ff2b124
--- /dev/null
+++ b/arch/mips/configs/htb80_defconfig
@@ -0,0 +1,1460 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.31.3
+# Tue Feb 22 18:12:53 2011
+#
+CONFIG_MIPS=y
+
+#
+# Machine selection
+#
+# CONFIG_JZ4730_PMP is not set
+# CONFIG_JZ4740_PAVO is not set
+# CONFIG_JZ4740_LEO is not set
+# CONFIG_JZ4740_LYRA is not set
+# CONFIG_JZ4725_DIPPER is not set
+# CONFIG_JZ4720_VIRGO is not set
+# CONFIG_JZ4750_FUWA is not set
+# CONFIG_JZ4750D_FUWA1 is not set
+# CONFIG_JZ4750_APUS is not set
+# CONFIG_JZ4750D_CETUS is not set
+# CONFIG_JZ4750L_F4750L is not set
+# CONFIG_JZ4760_F4760 is not set
+# CONFIG_JZ4760_CYGNUS is not set
+# CONFIG_JZ4760_ALTAIR is not set
+# CONFIG_JZ4760_LEPUS is not set
+CONFIG_JZ4760_HTB80=y
+# CONFIG_JZ4760B_CYGNUS is not set
+# CONFIG_JZ4760B_LEPUS is not set
+# CONFIG_JZ4810_F4810 is not set
+# CONFIG_MACH_ALCHEMY is not set
+# CONFIG_AR7 is not set
+# CONFIG_BASLER_EXCITE is not set
+# CONFIG_BCM47XX is not set
+# CONFIG_MIPS_COBALT is not set
+# CONFIG_MACH_DECSTATION is not set
+# CONFIG_MACH_JAZZ is not set
+# CONFIG_LASAT is not set
+# CONFIG_LEMOTE_FULONG is not set
+# CONFIG_MIPS_MALTA is not set
+# CONFIG_MIPS_SIM is not set
+# CONFIG_NEC_MARKEINS is not set
+# CONFIG_MACH_VR41XX is not set
+# CONFIG_NXP_STB220 is not set
+# CONFIG_NXP_STB225 is not set
+# CONFIG_PNX8550_JBS is not set
+# CONFIG_PNX8550_STB810 is not set
+# CONFIG_PMC_MSP is not set
+# CONFIG_PMC_YOSEMITE is not set
+# CONFIG_SGI_IP22 is not set
+# CONFIG_SGI_IP27 is not set
+# CONFIG_SGI_IP28 is not set
+# CONFIG_SGI_IP32 is not set
+# CONFIG_SIBYTE_CRHINE is not set
+# CONFIG_SIBYTE_CARMEL is not set
+# CONFIG_SIBYTE_CRHONE is not set
+# CONFIG_SIBYTE_RHONE is not set
+# CONFIG_SIBYTE_SWARM is not set
+# CONFIG_SIBYTE_LITTLESUR is not set
+# CONFIG_SIBYTE_SENTOSA is not set
+# CONFIG_SIBYTE_BIGSUR is not set
+# CONFIG_SNI_RM is not set
+# CONFIG_MACH_TX39XX is not set
+# CONFIG_MACH_TX49XX is not set
+# CONFIG_MIKROTIK_RB532 is not set
+# CONFIG_WR_PPMC is not set
+# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set
+# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set
+# CONFIG_ALCHEMY_GPIO_INDIRECT is not set
+CONFIG_SOC_JZ4760=y
+CONFIG_JZSOC=y
+CONFIG_JZRISC=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_SUPPORTS_OPROFILE=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_SCHED_OMIT_FRAME_POINTER=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_DMA_NEED_PCI_MAP_STATE=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+# CONFIG_NO_IOPORT is not set
+# CONFIG_CPU_BIG_ENDIAN is not set
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+
+#
+# CPU selection
+#
+# CONFIG_CPU_LOONGSON2 is not set
+CONFIG_CPU_MIPS32_R1=y
+# CONFIG_CPU_MIPS32_R2 is not set
+# CONFIG_CPU_MIPS64_R1 is not set
+# CONFIG_CPU_MIPS64_R2 is not set
+# CONFIG_CPU_R3000 is not set
+# CONFIG_CPU_TX39XX is not set
+# CONFIG_CPU_VR41XX is not set
+# CONFIG_CPU_R4300 is not set
+# CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_TX49XX is not set
+# CONFIG_CPU_R5000 is not set
+# CONFIG_CPU_R5432 is not set
+# CONFIG_CPU_R5500 is not set
+# CONFIG_CPU_R6000 is not set
+# CONFIG_CPU_NEVADA is not set
+# CONFIG_CPU_R8000 is not set
+# CONFIG_CPU_R10000 is not set
+# CONFIG_CPU_RM7000 is not set
+# CONFIG_CPU_RM9000 is not set
+# CONFIG_CPU_SB1 is not set
+# CONFIG_CPU_CAVIUM_OCTEON is not set
+CONFIG_SYS_HAS_CPU_MIPS32_R1=y
+CONFIG_CPU_MIPS32=y
+CONFIG_CPU_MIPSR1=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_HARDWARE_WATCHPOINTS=y
+
+#
+# Kernel type
+#
+CONFIG_32BIT=y
+# CONFIG_64BIT is not set
+CONFIG_PAGE_SIZE_4KB=y
+# CONFIG_PAGE_SIZE_8KB is not set
+# CONFIG_PAGE_SIZE_16KB is not set
+# CONFIG_PAGE_SIZE_32KB is not set
+# CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_MIPS_MT_DISABLED=y
+# CONFIG_MIPS_MT_SMP is not set
+# CONFIG_MIPS_MT_SMTC is not set
+CONFIG_CPU_HAS_LLSC=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_HZ_48 is not set
+CONFIG_HZ_100=y
+# CONFIG_HZ_128 is not set
+# CONFIG_HZ_250 is not set
+# CONFIG_HZ_256 is not set
+# CONFIG_HZ_1000 is not set
+# CONFIG_HZ_1024 is not set
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_HZ=100
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+# CONFIG_KEXEC is not set
+CONFIG_SECCOMP=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+# CONFIG_NAMESPACES is not set
+# CONFIG_BLK_DEV_INITRD is not set
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EMBEDDED=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_PCSPKR_PLATFORM=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+
+#
+# Performance Counters
+#
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+# CONFIG_STRIP_ASM_SYMS is not set
+CONFIG_COMPAT_BRK=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_SLOW_WORK is not set
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_FREEZER=y
+
+#
+# Bus options (PCI, PCMCIA, EISA, ISA, TC)
+#
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_MMU=y
+CONFIG_FORCE_MAX_ZONEORDER=13
+# CONFIG_PCCARD is not set
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_HAVE_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+CONFIG_TRAD_SIGNALS=y
+
+#
+# CPU Frequency scaling
+#
+# CONFIG_CPU_FREQ_JZ is not set
+
+#
+# Power management options
+#
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+# CONFIG_HIBERNATION is not set
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+CONFIG_WIRELESS=y
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_OLD_REGULATORY is not set
+CONFIG_WIRELESS_EXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+# CONFIG_LIB80211 is not set
+
+#
+# CFG80211 needs to be enabled for MAC80211
+#
+CONFIG_MAC80211_DEFAULT_PS_VALUE=0
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH=""
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_JZ4760=y
+# CONFIG_MTD_NAND_CS2 is not set
+# CONFIG_MTD_NAND_CS3 is not set
+# CONFIG_MTD_NAND_CS4 is not set
+# CONFIG_MTD_NAND_MULTI_PLANE is not set
+CONFIG_MTD_NAND_BUS_WIDTH_8=y
+# CONFIG_MTD_NAND_BUS_WIDTH_16 is not set
+# CONFIG_MTD_HW_HM_ECC is not set
+# CONFIG_MTD_SW_HM_ECC is not set
+# CONFIG_MTD_HW_RS_ECC is not set
+CONFIG_MTD_HW_BCH_ECC=y
+# CONFIG_MTD_HW_BCH_4BIT is not set
+CONFIG_MTD_HW_BCH_8BIT=y
+# CONFIG_MTD_HW_BCH_12BIT is not set
+# CONFIG_MTD_HW_BCH_16BIT is not set
+# CONFIG_MTD_HW_BCH_20BIT is not set
+# CONFIG_MTD_HW_BCH_24BIT is not set
+CONFIG_MTD_NAND_DMA=y
+# CONFIG_MTD_NAND_DMABUF is not set
+# CONFIG_ALLOCATE_MTDBLOCK_JZ_EARLY is not set
+# CONFIG_MTD_MTDBLOCK_WRITE_VERIFY_ENABLE is not set
+CONFIG_MTD_OOB_COPIES=3
+CONFIG_MTD_BADBLOCK_FLAG_PAGE=127
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_HD is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_SCSI_PROC_FS is not set
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_LSI_ET1011C_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_JZCS8900 is not set
+# CONFIG_JZ4760_ETH is not set
+# CONFIG_JZ_AX88796C is not set
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_ETHOC is not set
+# CONFIG_DNET is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_TOUCHSCREEN_JZ4760 is not set
+# CONFIG_TOUCHSCREEN_AD7879_I2C is not set
+# CONFIG_TOUCHSCREEN_AD7879 is not set
+# CONFIG_TOUCHSCREEN_EETI is not set
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+# CONFIG_TOUCHSCREEN_TSC2007 is not set
+# CONFIG_TOUCHSCREEN_W90X900 is not set
+CONFIG_TOUCHSCREEN_FT5X0X=y
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=2
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_RTC_PCF8563 is not set
+CONFIG_RTC_JZ4760=y
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+
+#
+# JZSOC char device support
+#
+CONFIG_JZCHAR=y
+CONFIG_JZ_TCSM=y
+# CONFIG_JZ_TSSI is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+CONFIG_I2C0_JZ4760=y
+CONFIG_I2C1_JZ4760=y
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+# CONFIG_SPI is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_AB3100_CORE is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+CONFIG_FB_JZSOC=y
+# CONFIG_FB_JZ4760_LCD is not set
+CONFIG_FB_JZ4760_EPD=y
+# CONFIG_JZ4760_LCD_USE_FG0_ONLY is not set
+# CONFIG_JZ4760_LCD_USE_FG1_ONLY is not set
+CONFIG_JZ4760_LCD_USE_2LAYER_FG=y
+# CONFIG_JZ4760_AUO_EPD_DISPLAY is not set
+CONFIG_JZ4760_EPSON_EPD_DISPLAY=y
+# CONFIG_JZ4760_OED_EPD_DISPLAY is not set
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_BROADSHEET is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE is not set
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LOGO_LINUX_CLUT224=y
+CONFIG_SOUND=y
+CONFIG_SOUND_OSS_CORE=y
+# CONFIG_SND is not set
+CONFIG_SOUND_PRIME=y
+# CONFIG_SOUND_JZ_AC97 is not set
+CONFIG_SOUND_JZ_I2S=y
+# CONFIG_I2S_AK4642EN is not set
+# CONFIG_I2S_ICODEC is not set
+# CONFIG_I2S_DLV_4750 is not set
+CONFIG_I2S_DLV_4760=y
+# CONFIG_I2S_DLV_4810 is not set
+# CONFIG_HID_SUPPORT is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+# CONFIG_USB_DEVICEFS is not set
+# CONFIG_USB_DEVICE_CLASS is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+CONFIG_USB_SUSPEND=y
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_MON is not set
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+CONFIG_USB_MUSB_HDRC=y
+CONFIG_USB_MUSB_SOC=y
+
+#
+# Ingenic OTG USB support
+#
+# CONFIG_USB_MUSB_HOST is not set
+CONFIG_USB_MUSB_PERIPHERAL=y
+# CONFIG_USB_MUSB_OTG is not set
+# CONFIG_USB_MUSB_PERIPHERAL_HOTPLUG is not set
+CONFIG_USB_GADGET_MUSB_HDRC=y
+# CONFIG_MUSB_PIO_ONLY is not set
+CONFIG_USB_INVENTRA_DMA=y
+# CONFIG_USB_TI_CPPI_DMA is not set
+# CONFIG_USB_MUSB_DEBUG is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+CONFIG_USB_LIBUSUAL=y
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+CONFIG_USB_GADGET=m
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_JZ4740 is not set
+# CONFIG_USB_GADGET_JZ4750 is not set
+# CONFIG_USB_GADGET_JZ4750D is not set
+# CONFIG_USB_GADGET_JZ4750L is not set
+# CONFIG_USB_GADGET_JZ4730 is not set
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_S3C_HSOTG is not set
+# CONFIG_USB_GADGET_IMX is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_CI13XXX is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LANGWELL is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+CONFIG_USB_GADGET_DUALSPEED=y
+# CONFIG_JZ_UDC_HOTPLUG is not set
+# CONFIG_USB_ZERO is not set
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_ETH is not set
+# CONFIG_USB_GADGETFS is not set
+CONFIG_USB_FILE_STORAGE=m
+# CONFIG_USB_FILE_STORAGE_TEST is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+# CONFIG_USB_CDC_COMPOSITE is not set
+
+#
+# OTG and related infrastructure
+#
+CONFIG_USB_OTG_UTILS=y
+CONFIG_NOP_USB_XCEIV=y
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+CONFIG_MMC_JZSOC=y
+# CONFIG_JZ_MSC0 is not set
+CONFIG_JZ_MSC1=y
+# CONFIG_JZ_MSC1_BUS_1 is not set
+CONFIG_JZ_MSC1_BUS_4=y
+# CONFIG_JZ_MSC1_BUS_8 is not set
+# CONFIG_JZ_MSC1_SDIO_SUPPORT is not set
+CONFIG_JZ_MSC2=y
+# CONFIG_JZ_MSC2_BUS_1 is not set
+CONFIG_JZ_MSC2_BUS_4=y
+# CONFIG_JZ_MSC2_BUS_8 is not set
+CONFIG_JZ_MSC2_SDIO_SUPPORT=y
+# CONFIG_JZ_FS_AT_CARD is not set
+# CONFIG_MMC_SDHCI is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+
+#
+# SPI RTC drivers
+#
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+
+#
+# TI VLYNQ
+#
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+# CONFIG_EXT2_FS_POSIX_ACL is not set
+# CONFIG_EXT2_FS_SECURITY is not set
+# CONFIG_EXT2_FS_XIP is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4_FS is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+# CONFIG_MISC_FILESYSTEMS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+CONFIG_NFS_V4=y
+# CONFIG_NFS_V4_1 is not set
+CONFIG_ROOT_NFS=y
+CONFIG_NFSD=y
+CONFIG_NFSD_V3=y
+# CONFIG_NFSD_V3_ACL is not set
+CONFIG_NFSD_V4=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_EXPORTFS=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+CONFIG_RPCSEC_GSS_KRB5=y
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="cp437"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+CONFIG_NLS_CODEPAGE_936=y
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=y
+# CONFIG_DLM is not set
+
+#
+# Yaffs2 Filesystems
+#
+CONFIG_YAFFS_FS=y
+CONFIG_YAFFS_YAFFS1=y
+# CONFIG_YAFFS_DOES_ECC is not set
+CONFIG_YAFFS_YAFFS2=y
+CONFIG_YAFFS_AUTO_YAFFS2=y
+# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
+# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
+CONFIG_YAFFS_DISABLE_CHUNK_ERASED_CHECK=y
+CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
+CONFIG_YAFFS_CHECKPOINT_RESERVED_BLOCKS=10
+
+#
+# Kernel hacking
+#
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_CMDLINE=""
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+CONFIG_CRYPTO_WORKQUEUE=y
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=y
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=y
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_ZLIB is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_HW=y
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/mips/configs/lepus60b_defconfig b/arch/mips/configs/lepus60b_defconfig
new file mode 100644
index 00000000000..e036ef00dda
--- /dev/null
+++ b/arch/mips/configs/lepus60b_defconfig
@@ -0,0 +1,1485 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.31.3
+# Wed Apr 20 14:15:45 2011
+#
+CONFIG_MIPS=y
+
+#
+# Machine selection
+#
+# CONFIG_JZ4730_PMP is not set
+# CONFIG_JZ4740_PAVO is not set
+# CONFIG_JZ4740_LEO is not set
+# CONFIG_JZ4740_LYRA is not set
+# CONFIG_JZ4725_DIPPER is not set
+# CONFIG_JZ4720_VIRGO is not set
+# CONFIG_JZ4750_FUWA is not set
+# CONFIG_JZ4750D_FUWA1 is not set
+# CONFIG_JZ4750_APUS is not set
+# CONFIG_JZ4750D_CETUS is not set
+# CONFIG_JZ4750L_F4750L is not set
+# CONFIG_JZ4760_F4760 is not set
+# CONFIG_JZ4760_CYGNUS is not set
+# CONFIG_JZ4760_ALTAIR is not set
+# CONFIG_JZ4760_LEPUS is not set
+# CONFIG_JZ4760_HTB80 is not set
+# CONFIG_JZ4760B_CYGNUS is not set
+CONFIG_JZ4760B_LEPUS=y
+# CONFIG_JZ4770_F4770 is not set
+# CONFIG_JZ4810_F4810 is not set
+# CONFIG_MACH_ALCHEMY is not set
+# CONFIG_AR7 is not set
+# CONFIG_BASLER_EXCITE is not set
+# CONFIG_BCM47XX is not set
+# CONFIG_MIPS_COBALT is not set
+# CONFIG_MACH_DECSTATION is not set
+# CONFIG_MACH_JAZZ is not set
+# CONFIG_LASAT is not set
+# CONFIG_LEMOTE_FULONG is not set
+# CONFIG_MIPS_MALTA is not set
+# CONFIG_MIPS_SIM is not set
+# CONFIG_NEC_MARKEINS is not set
+# CONFIG_MACH_VR41XX is not set
+# CONFIG_NXP_STB220 is not set
+# CONFIG_NXP_STB225 is not set
+# CONFIG_PNX8550_JBS is not set
+# CONFIG_PNX8550_STB810 is not set
+# CONFIG_PMC_MSP is not set
+# CONFIG_PMC_YOSEMITE is not set
+# CONFIG_SGI_IP22 is not set
+# CONFIG_SGI_IP27 is not set
+# CONFIG_SGI_IP28 is not set
+# CONFIG_SGI_IP32 is not set
+# CONFIG_SIBYTE_CRHINE is not set
+# CONFIG_SIBYTE_CARMEL is not set
+# CONFIG_SIBYTE_CRHONE is not set
+# CONFIG_SIBYTE_RHONE is not set
+# CONFIG_SIBYTE_SWARM is not set
+# CONFIG_SIBYTE_LITTLESUR is not set
+# CONFIG_SIBYTE_SENTOSA is not set
+# CONFIG_SIBYTE_BIGSUR is not set
+# CONFIG_SNI_RM is not set
+# CONFIG_MACH_TX39XX is not set
+# CONFIG_MACH_TX49XX is not set
+# CONFIG_MIKROTIK_RB532 is not set
+# CONFIG_WR_PPMC is not set
+# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set
+# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set
+# CONFIG_ALCHEMY_GPIO_INDIRECT is not set
+CONFIG_SOC_JZ4760B=y
+CONFIG_JZSOC=y
+CONFIG_JZRISC=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_SUPPORTS_OPROFILE=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_SCHED_OMIT_FRAME_POINTER=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_DMA_NEED_PCI_MAP_STATE=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+# CONFIG_NO_IOPORT is not set
+# CONFIG_CPU_BIG_ENDIAN is not set
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+
+#
+# CPU selection
+#
+# CONFIG_CPU_LOONGSON2 is not set
+CONFIG_CPU_MIPS32_R1=y
+# CONFIG_CPU_MIPS32_R2 is not set
+# CONFIG_CPU_MIPS64_R1 is not set
+# CONFIG_CPU_MIPS64_R2 is not set
+# CONFIG_CPU_R3000 is not set
+# CONFIG_CPU_TX39XX is not set
+# CONFIG_CPU_VR41XX is not set
+# CONFIG_CPU_R4300 is not set
+# CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_TX49XX is not set
+# CONFIG_CPU_R5000 is not set
+# CONFIG_CPU_R5432 is not set
+# CONFIG_CPU_R5500 is not set
+# CONFIG_CPU_R6000 is not set
+# CONFIG_CPU_NEVADA is not set
+# CONFIG_CPU_R8000 is not set
+# CONFIG_CPU_R10000 is not set
+# CONFIG_CPU_RM7000 is not set
+# CONFIG_CPU_RM9000 is not set
+# CONFIG_CPU_SB1 is not set
+# CONFIG_CPU_CAVIUM_OCTEON is not set
+CONFIG_SYS_HAS_CPU_MIPS32_R1=y
+CONFIG_CPU_MIPS32=y
+CONFIG_CPU_MIPSR1=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_HARDWARE_WATCHPOINTS=y
+
+#
+# Kernel type
+#
+CONFIG_32BIT=y
+# CONFIG_64BIT is not set
+CONFIG_PAGE_SIZE_4KB=y
+# CONFIG_PAGE_SIZE_8KB is not set
+# CONFIG_PAGE_SIZE_16KB is not set
+# CONFIG_PAGE_SIZE_32KB is not set
+# CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_MIPS_MT_DISABLED=y
+# CONFIG_MIPS_MT_SMP is not set
+# CONFIG_MIPS_MT_SMTC is not set
+CONFIG_CPU_HAS_LLSC=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_IRQ_PROBE=y
+# CONFIG_HIGHMEM is not set
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_SYS_SUPPORTS_HIGHMEM=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_HZ_48 is not set
+CONFIG_HZ_100=y
+# CONFIG_HZ_128 is not set
+# CONFIG_HZ_250 is not set
+# CONFIG_HZ_256 is not set
+# CONFIG_HZ_1000 is not set
+# CONFIG_HZ_1024 is not set
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_HZ=100
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+# CONFIG_KEXEC is not set
+CONFIG_SECCOMP=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+# CONFIG_NAMESPACES is not set
+# CONFIG_BLK_DEV_INITRD is not set
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EMBEDDED=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_PCSPKR_PLATFORM=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+
+#
+# Performance Counters
+#
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+# CONFIG_STRIP_ASM_SYMS is not set
+CONFIG_COMPAT_BRK=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_SLOW_WORK is not set
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_FREEZER=y
+
+#
+# Bus options (PCI, PCMCIA, EISA, ISA, TC)
+#
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_MMU=y
+CONFIG_FORCE_MAX_ZONEORDER=14
+# CONFIG_PCCARD is not set
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_HAVE_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+CONFIG_TRAD_SIGNALS=y
+
+#
+# CPU Frequency scaling
+#
+# CONFIG_CPU_FREQ_JZ is not set
+
+#
+# Power management options
+#
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+# CONFIG_HIBERNATION is not set
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+CONFIG_WIRELESS=y
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_OLD_REGULATORY is not set
+CONFIG_WIRELESS_EXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+# CONFIG_LIB80211 is not set
+
+#
+# CFG80211 needs to be enabled for MAC80211
+#
+CONFIG_MAC80211_DEFAULT_PS_VALUE=0
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH=""
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_JZ4760B=y
+# CONFIG_MTD_NAND_CS2 is not set
+# CONFIG_MTD_NAND_CS3 is not set
+# CONFIG_MTD_NAND_CS4 is not set
+# CONFIG_MTD_NAND_CS5 is not set
+# CONFIG_MTD_NAND_CS6 is not set
+# CONFIG_MTD_NAND_MULTI_PLANE is not set
+CONFIG_MTD_NAND_BUS_WIDTH_8=y
+# CONFIG_MTD_NAND_BUS_WIDTH_16 is not set
+# CONFIG_MTD_HW_HM_ECC is not set
+# CONFIG_MTD_SW_HM_ECC is not set
+# CONFIG_MTD_HW_RS_ECC is not set
+CONFIG_MTD_HW_BCH_ECC=y
+# CONFIG_MTD_HW_BCH_4BIT is not set
+CONFIG_MTD_HW_BCH_8BIT=y
+# CONFIG_MTD_HW_BCH_12BIT is not set
+# CONFIG_MTD_HW_BCH_16BIT is not set
+# CONFIG_MTD_HW_BCH_20BIT is not set
+# CONFIG_MTD_HW_BCH_24BIT is not set
+CONFIG_MTD_NAND_DMA=y
+# CONFIG_MTD_NAND_DMABUF is not set
+# CONFIG_ALLOCATE_MTDBLOCK_JZ_EARLY is not set
+# CONFIG_MTD_MTDBLOCK_WRITE_VERIFY_ENABLE is not set
+CONFIG_MTD_OOB_COPIES=3
+CONFIG_MTD_BADBLOCK_FLAG_PAGE=127
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_HD is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_SCSI_PROC_FS is not set
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_LSI_ET1011C_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+CONFIG_JZCS8900=y
+# CONFIG_JZ_AX88796C is not set
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_ETHOC is not set
+# CONFIG_DNET is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ATH6K_LEGACY is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_TOUCHSCREEN_JZ4760B is not set
+# CONFIG_TOUCHSCREEN_AD7879_I2C is not set
+# CONFIG_TOUCHSCREEN_AD7879 is not set
+# CONFIG_TOUCHSCREEN_EETI is not set
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+# CONFIG_TOUCHSCREEN_TSC2007 is not set
+# CONFIG_TOUCHSCREEN_W90X900 is not set
+CONFIG_TOUCHSCREEN_FT5X0X=y
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=2
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_RTC_PCF8563 is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+
+#
+# JZSOC char device support
+#
+CONFIG_JZCHAR=y
+CONFIG_JZ_TCSM=y
+# CONFIG_JZ_TSSI is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+CONFIG_JZ_I2C=y
+CONFIG_JZ_I2C0=y
+CONFIG_JZ_I2C0_USE_DMA=y
+CONFIG_JZ_I2C1=y
+CONFIG_JZ_I2C1_USE_DMA=y
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+# CONFIG_SPI is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_AB3100_CORE is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+CONFIG_FB_JZSOC=y
+CONFIG_FB_JZ4760_LCD=y
+# CONFIG_FB_JZ4760_LCD_USE_2LAYER_FRAMEBUFFER is not set
+# CONFIG_FB_JZ4760_TVE is not set
+# CONFIG_JZ4760_HDMI_DISPLAY is not set
+# CONFIG_JZ4760_IPU_MM is not set
+# CONFIG_FB_JZ4760_SLCD is not set
+# CONFIG_JZ4760_LCD_SAMSUNG_LTP400WQF01 is not set
+# CONFIG_JZ4760_LCD_SAMSUNG_LTP400WQF02 is not set
+# CONFIG_JZ4760_LCD_AUO_A043FL01V2 is not set
+# CONFIG_JZ4760_LCD_FOXCONN_PT035TN01 is not set
+# CONFIG_JZ4760_LCD_INNOLUX_PT035TN01_SERIAL is not set
+# CONFIG_JZ4760_LCD_TOPPOLY_TD025THEA7_RGB_DELTA is not set
+CONFIG_JZ4760_LCD_TOPPOLY_TD043MGEB1=y
+# CONFIG_JZ4760_LCD_TRULY_TFTG320240DTSW_18BIT is not set
+# CONFIG_JZ4760_LCD_TRULY_TFT_GG1P0319LTSW_W is not set
+# CONFIG_JZ4760_SLCD_KGM701A3_TFT_SPFD5420A is not set
+# CONFIG_JZ4760_VGA_DISPLAY is not set
+# CONFIG_FB_JZ4760_EPD is not set
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_BROADSHEET is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_CURSOR_FLASH is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LOGO_LINUX_CLUT224=y
+CONFIG_SOUND=y
+CONFIG_SOUND_OSS_CORE=y
+# CONFIG_SND is not set
+CONFIG_SOUND_PRIME=y
+# CONFIG_SOUND_JZ_AC97 is not set
+CONFIG_SOUND_JZ_I2S=y
+# CONFIG_I2S_AK4642EN is not set
+# CONFIG_I2S_ICODEC is not set
+# CONFIG_I2S_DLV_4750 is not set
+CONFIG_I2S_DLV_4760=y
+# CONFIG_I2S_DLV_4810 is not set
+# CONFIG_HID_SUPPORT is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+# CONFIG_USB_DEVICEFS is not set
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+CONFIG_USB_SUSPEND=y
+CONFIG_USB_OTG=y
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+CONFIG_USB_MON=y
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+CONFIG_USB_MUSB_HDRC=y
+CONFIG_USB_MUSB_SOC=y
+
+#
+# Ingenic OTG USB support
+#
+# CONFIG_USB_MUSB_HOST is not set
+# CONFIG_USB_MUSB_PERIPHERAL is not set
+CONFIG_USB_MUSB_OTG=y
+# CONFIG_USB_MUSB_PERIPHERAL_HOTPLUG is not set
+CONFIG_USB_GADGET_MUSB_HDRC=y
+CONFIG_USB_MUSB_HDRC_HCD=y
+# CONFIG_MUSB_PIO_ONLY is not set
+CONFIG_USB_INVENTRA_DMA=y
+# CONFIG_USB_TI_CPPI_DMA is not set
+# CONFIG_USB_MUSB_DEBUG is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+CONFIG_USB_GADGET=m
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_JZ4740 is not set
+# CONFIG_USB_GADGET_JZ4750 is not set
+# CONFIG_USB_GADGET_JZ4750D is not set
+# CONFIG_USB_GADGET_JZ4750L is not set
+# CONFIG_USB_GADGET_JZ4730 is not set
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_S3C_HSOTG is not set
+# CONFIG_USB_GADGET_IMX is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_CI13XXX is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LANGWELL is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+CONFIG_USB_GADGET_DUALSPEED=y
+# CONFIG_JZ_UDC_HOTPLUG is not set
+# CONFIG_USB_ZERO is not set
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_ETH is not set
+# CONFIG_USB_GADGETFS is not set
+CONFIG_USB_FILE_STORAGE=m
+# CONFIG_USB_FILE_STORAGE_TEST is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+# CONFIG_USB_CDC_COMPOSITE is not set
+
+#
+# OTG and related infrastructure
+#
+CONFIG_USB_OTG_UTILS=y
+CONFIG_NOP_USB_XCEIV=y
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+CONFIG_MMC_JZSOC=y
+CONFIG_JZ_MSC0=y
+# CONFIG_JZ_MSC0_BUS_1 is not set
+CONFIG_JZ_MSC0_BUS_4=y
+# CONFIG_JZ_MSC0_BUS_8 is not set
+# CONFIG_JZ_MSC0_SDIO_SUPPORT is not set
+CONFIG_JZ_MSC1=y
+# CONFIG_JZ_MSC1_BUS_1 is not set
+CONFIG_JZ_MSC1_BUS_4=y
+# CONFIG_JZ_MSC1_BUS_8 is not set
+# CONFIG_JZ_MSC1_SDIO_SUPPORT is not set
+# CONFIG_JZ_MSC2 is not set
+# CONFIG_JZ_SYSTEM_AT_CARD is not set
+# CONFIG_MMC_SDHCI is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+
+#
+# SPI RTC drivers
+#
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_JZ4760B=y
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+
+#
+# TI VLYNQ
+#
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+# CONFIG_EXT2_FS_POSIX_ACL is not set
+# CONFIG_EXT2_FS_SECURITY is not set
+# CONFIG_EXT2_FS_XIP is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4_FS is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+# CONFIG_MISC_FILESYSTEMS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+CONFIG_NFS_V4=y
+# CONFIG_NFS_V4_1 is not set
+CONFIG_ROOT_NFS=y
+CONFIG_NFSD=y
+CONFIG_NFSD_V3=y
+# CONFIG_NFSD_V3_ACL is not set
+CONFIG_NFSD_V4=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_EXPORTFS=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+CONFIG_RPCSEC_GSS_KRB5=y
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="cp437"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+CONFIG_NLS_CODEPAGE_936=y
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=y
+# CONFIG_DLM is not set
+
+#
+# Yaffs2 Filesystems
+#
+CONFIG_YAFFS_FS=y
+CONFIG_YAFFS_YAFFS1=y
+# CONFIG_YAFFS_DOES_ECC is not set
+CONFIG_YAFFS_YAFFS2=y
+CONFIG_YAFFS_AUTO_YAFFS2=y
+# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
+# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
+CONFIG_YAFFS_DISABLE_CHUNK_ERASED_CHECK=y
+CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
+CONFIG_YAFFS_CHECKPOINT_RESERVED_BLOCKS=10
+
+#
+# Kernel hacking
+#
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_CMDLINE=""
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+CONFIG_CRYPTO_WORKQUEUE=y
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=y
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=y
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_ZLIB is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_HW=y
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/mips/configs/lepus_defconfig b/arch/mips/configs/lepus_defconfig
index cf147f6789c..9ad02712aab 100644
--- a/arch/mips/configs/lepus_defconfig
+++ b/arch/mips/configs/lepus_defconfig
@@ -1075,6 +1075,7 @@ CONFIG_MMC_BLOCK_BOUNCE=y
 #
 # MMC/SD/SDIO Host Controller Drivers
 #
+CONFIG_MMC_JZSOC=y
 CONFIG_JZ_MSC0=y
 # CONFIG_JZ_MSC0_BUS_1 is not set
 CONFIG_JZ_MSC0_BUS_4=y
diff --git a/arch/mips/include/asm/bootinfo.h b/arch/mips/include/asm/bootinfo.h
index 14217998dfb..258ebae01e8 100644
--- a/arch/mips/include/asm/bootinfo.h
+++ b/arch/mips/include/asm/bootinfo.h
@@ -207,7 +207,9 @@
 #define  MACH_INGENIC_JZ4750D	3	/* JZ4750D SOC		*/
 #define  MACH_INGENIC_JZ4750L	4	/* JZ4750L SOC		*/
 #define  MACH_INGENIC_JZ4760	5	/* JZ4760 SOC		*/
-#define  MACH_INGENIC_JZ4810	6	/* JZ4810 SOC		*/
+#define  MACH_INGENIC_JZ4760B	6	/* JZ4760B SOC		*/
+#define  MACH_INGENIC_JZ4770	7	/* JZ4770 SOC		*/
+#define  MACH_INGENIC_JZ4810	8	/* JZ4810 SOC		*/
 
 #define CL_SIZE			COMMAND_LINE_SIZE
 
diff --git a/arch/mips/include/asm/break.h b/arch/mips/include/asm/break.h
index 44437ed765e..9161e684cb4 100644
--- a/arch/mips/include/asm/break.h
+++ b/arch/mips/include/asm/break.h
@@ -30,6 +30,8 @@
 #define BRK_BUG		512	/* Used by BUG() */
 #define BRK_KDB		513	/* Used in KDB_ENTER() */
 #define BRK_MEMU	514	/* Used by FPU emulator */
+#define BRK_KPROBE_BP	515	/* Kprobe break */
+#define BRK_KPROBE_SSTEPBP 516	/* Kprobe single step software implementation */
 #define BRK_MULOVF	1023	/* Multiply overflow */
 
 #endif /* __ASM_BREAK_H */
diff --git a/arch/mips/include/asm/cacheflush.h b/arch/mips/include/asm/cacheflush.h
index 03b1d69b142..6cc65cbe25e 100644
--- a/arch/mips/include/asm/cacheflush.h
+++ b/arch/mips/include/asm/cacheflush.h
@@ -10,6 +10,7 @@
 #define _ASM_CACHEFLUSH_H
 
 /* Keep includes the same across arches.  */
+#include <linux/fs.h>
 #include <linux/mm.h>
 #include <asm/cpu-features.h>
 
@@ -57,10 +58,39 @@ static inline void flush_anon_page(struct vm_area_struct *vma,
 		__flush_anon_page(page, vmaddr);
 }
 
+#ifdef CONFIG_JZRISC
+extern void (*flush_insn_cache_page)(unsigned long addr);
+static inline void flush_icache_page(struct vm_area_struct *vma,
+	struct page *page)
+{
+	struct address_space *mapping = page_mapping(page);
+	unsigned long addr;
+
+	if (PageHighMem(page))
+	  return;
+
+	if (mapping && !mapping_mapped(mapping)) {
+	  return;
+	}
+
+	__flush_dcache_page(page);
+
+	/*
+	 * We could delay the flush for the !page_mapping case too.  But that
+	 * case is for exec env/arg pages and those are %99 certainly going to
+	 * get faulted into the tlb (and thus flushed) anyways.
+	 */
+
+	addr = (unsigned long) page_address(page);
+
+	flush_insn_cache_page(addr);
+}
+#else
 static inline void flush_icache_page(struct vm_area_struct *vma,
 	struct page *page)
 {
 }
+#endif
 
 extern void (*flush_icache_range)(unsigned long start, unsigned long end);
 extern void (*local_flush_icache_range)(unsigned long start, unsigned long end);
diff --git a/arch/mips/include/asm/inst.h b/arch/mips/include/asm/inst.h
index 6489f00731c..444ff71aa0e 100644
--- a/arch/mips/include/asm/inst.h
+++ b/arch/mips/include/asm/inst.h
@@ -247,6 +247,12 @@ struct ma_format {	/* FPU multipy and add format (MIPS IV) */
 	unsigned int fmt : 2;
 };
 
+struct b_format { /* BREAK and SYSCALL */
+	unsigned int opcode:6;
+	unsigned int code:20;
+	unsigned int func:6;
+};
+
 #elif defined(__MIPSEL__)
 
 struct j_format {	/* Jump format */
@@ -314,6 +320,12 @@ struct ma_format {	/* FPU multipy and add format (MIPS IV) */
 	unsigned int opcode : 6;
 };
 
+struct b_format { /* BREAK and SYSCALL */
+	unsigned int func:6;
+	unsigned int code:20;
+	unsigned int opcode:6;
+};
+
 #else /* !defined (__MIPSEB__) && !defined (__MIPSEL__) */
 #error "MIPS but neither __MIPSEL__ nor __MIPSEB__?"
 #endif
@@ -328,7 +340,8 @@ union mips_instruction {
 	struct c_format c_format;
 	struct r_format r_format;
 	struct f_format f_format;
-        struct ma_format ma_format;
+	struct ma_format ma_format;
+	struct b_format b_format;
 };
 
 /* HACHACHAHCAHC ...  */
diff --git a/arch/mips/include/asm/jzmmc/jz_mmc_host.h b/arch/mips/include/asm/jzmmc/jz_mmc_host.h
deleted file mode 100644
index a64614381de..00000000000
--- a/arch/mips/include/asm/jzmmc/jz_mmc_host.h
+++ /dev/null
@@ -1,114 +0,0 @@
-/*

- *  linux/drivers/mmc/host/jz_mmc/jz_mmc_host.h

- *

- * This program is free software; you can redistribute it and/or modify

- * it under the terms of the GNU General Public License version 2 as

- * published by the Free Software Foundation.

- *

- * Copyright (c) Ingenic Semiconductor Co., Ltd.

- */

-

-#ifndef __JZ_MMC_HOST_H__

-#define __JZ_MMC_HOST_H__

-

-#include <asm/jzmmc/jz_mmc_platform_data.h>

-#include <asm/jzsoc.h>

-

-#define USE_DMA

-#define USE_DMA_DESC

-#ifdef CONFIG_SOC_JZ4760

-#define USE_DMA_BUSRT_64

-#endif

-

-

-#define MMC_CLOCK_SLOW    400000      /* 400 kHz for initial setup */

-#define MMC_CLOCK_FAST  20000000      /* 20 MHz for maximum for normal operation */

-#define SD_CLOCK_FAST   24000000      /* 24 MHz for SD Cards */

-#define SD_CLOCK_HIGH   24000000      /* 24 MHz for SD Cards */

-#define MMC_NO_ERROR  0

-

-#define NR_SG	1

-

-#define MSC_1BIT_BUS 0

-#define MSC_4BIT_BUS 1

-#define MSC_8BIT_BUS 2

-

-#define SZ_4K                           0x00001000

-

-#ifndef USE_DMA_DESC

-typedef struct jzsoc_dma_desc {

-        volatile u32 ddadr;     /* Points to the next descriptor + flags */

-        volatile u32 dsadr;     /* DSADR value for the current transfer */

-        volatile u32 dtadr;     /* DTADR value for the current transfer */

-        volatile u32 dcmd;      /* DCMD value for the current transfer */

-} jzsoc_dma_desc;

-#endif

-

-struct jz_mmc_curr_req {

-	struct mmc_request	*mrq;

-	struct mmc_command	*cmd;

-	struct mmc_data		*data;

-	int r_type;

-};

-

-struct jz_mmc_host {

-	struct mmc_host *mmc;

-	spinlock_t lock;

-#ifdef USE_DMA

-	struct {

-		int len;

-		int dir;

-		int rxchannel;

-		int txchannel;

-	} dma;

-#ifdef USE_DMA_DESC

-	jz_dma_desc *dma_desc;

-	dma_addr_t dma_desc_phys_addr;

-#else

-	dma_addr_t sg_dma;

-	struct jzsoc_dma_desc *sg_cpu;

-#endif

-#else

-	struct {

-		int index;

-		int offset;

-		int len;

-	} pio;

-#endif

-	unsigned int clkrt;

-	unsigned int cmdat;

-	unsigned int imask;

-	unsigned int power_mode;

-	unsigned int eject;

-	unsigned int oldstat;

-	unsigned int pdev_id;

-	void __iomem *base;

-

-	struct resource *irqres;

-	struct resource *memres;

-	struct resource *dmares;

-

-	struct jz_mmc_platform_data *plat;

-	struct jz_mmc_curr_req curr;

-	int msc_ack;

-	struct delayed_work gpio_jiq_work;

-	atomic_t detect_refcnt;

-	int sleeping;

-	struct work_struct msc_jiq_work;

-	struct workqueue_struct *msc_work_queue;

-	wait_queue_head_t msc_wait_queue;

-};

-

-#if 0

-struct jz_mmc_functions {

-	void (*deinit) (struct jz_mmc_host *, struct platform_device *);

-	int (*transmit_data) (struct jz_mmc_host *);

-	void (*execute_cmd) (struct jz_mmc_host *, struct mmc_command *, unsigned int);

-	void (*set_clock) (struct jz_mmc_host *, int);

-	void (*msc_deinit) (struct jz_mmc_host *);

-	int (*gpio_deinit) (struct jz_mmc_host *, struct platform_device *);

-	void (*dma_deinit) (struct jz_mmc_host *);

-};

-#endif

-

-#endif /* __JZ_MMC_HOST_H__ */

diff --git a/arch/mips/include/asm/jzmmc/jz_mmc_platform_data.h b/arch/mips/include/asm/jzmmc/jz_mmc_platform_data.h
deleted file mode 100644
index f5b0e190ded..00000000000
--- a/arch/mips/include/asm/jzmmc/jz_mmc_platform_data.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- *  arch/mips/include/asm/mach-jz4750/jz_platform_data.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Copyright (c) Ingenic Semiconductor Co., Ltd.
- */
-
-#ifndef __JZ_PLATFORM_DATA_H__
-#define __JZ_PLATFORM_DATA_H__
-
-#include <linux/mmc/host.h>
-#include <linux/mmc/card.h>
-#include <linux/mmc/sdio_func.h>
-
-#define CARD_INSERTED 1
-#define CARD_REMOVED 0
-
-struct jz_mmc_platform_data {
-	unsigned int ocr_mask;			/* available voltages */
-	unsigned long detect_delay;		/* delay in jiffies before detecting cards after interrupt */
-	unsigned char status_irq;
-	unsigned char support_sdio;
-	unsigned char bus_width;
-	unsigned int max_bus_width;
-	unsigned int detect_pin;
-
-	unsigned char msc_irq;
-	unsigned char dma_rxid;
-	unsigned char dma_txid;
-
-	void *driver_data;
-
-	void (*init) (struct device *);
-	void (*power_on) (struct device *);
-	void (*power_off) (struct device *);
-	void (*cpm_start) (struct device *);
-	unsigned int (*status) (struct device *);
-	unsigned int (*write_protect) (struct device *);
-	void (*plug_change) (int);
-	int (*register_status_notify)(void (*callback)(int card_present, void *dev_id), void *dev_id);
-
-
-/*
-	int (*init)(struct device *, irq_handler_t , void *);
-	int (*get_ro)(struct device *);
-	void (*setpower)(struct device *, unsigned int);
-	void (*exit)(struct device *, void *);
-*/
-
-
-};
-
-#endif
diff --git a/arch/mips/include/asm/jzsoc.h b/arch/mips/include/asm/jzsoc.h
index d950ad58e7d..16032f1b415 100644
--- a/arch/mips/include/asm/jzsoc.h
+++ b/arch/mips/include/asm/jzsoc.h
@@ -43,6 +43,14 @@
 #include <asm/mach-jz4760/jz4760.h>
 #endif
 
+#ifdef CONFIG_SOC_JZ4760B
+#include <asm/mach-jz4760b/jz4760b.h>
+#endif
+
+#ifdef CONFIG_SOC_JZ4770
+#include <asm/mach-jz4770/jz4770.h>
+#endif
+
 #ifdef CONFIG_SOC_JZ4810
 #include <asm/mach-jz4810/jz4810.h>
 #endif
diff --git a/arch/mips/include/asm/kdebug.h b/arch/mips/include/asm/kdebug.h
index 5bf62aafc89..6a9af5fcb5d 100644
--- a/arch/mips/include/asm/kdebug.h
+++ b/arch/mips/include/asm/kdebug.h
@@ -8,6 +8,9 @@ enum die_val {
 	DIE_FP,
 	DIE_TRAP,
 	DIE_RI,
+	DIE_PAGE_FAULT,
+	DIE_BREAK,
+	DIE_SSTEPBP
 };
 
 #endif /* _ASM_MIPS_KDEBUG_H */
diff --git a/arch/mips/include/asm/kprobes.h b/arch/mips/include/asm/kprobes.h
new file mode 100644
index 00000000000..5beac681d85
--- /dev/null
+++ b/arch/mips/include/asm/kprobes.h
@@ -0,0 +1,99 @@
+/*
+ *  Kernel Probes (KProbes)
+ *  include/asm-mips/kprobes.h
+ *
+ *  Copyright 2006 Sony Corp.
+ *  Copyright 2010 Cavium Networks
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; version 2 of the License.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef _ASM_KPROBES_H
+#define _ASM_KPROBES_H
+
+#include <linux/ptrace.h>
+#include <linux/types.h>
+
+#include <asm/cacheflush.h>
+#include <asm/kdebug.h>
+#include <asm/inst.h>
+
+#define  __ARCH_WANT_KPROBES_INSN_SLOT
+
+struct kprobe;
+struct pt_regs;
+
+typedef union mips_instruction kprobe_opcode_t;
+
+#define MAX_INSN_SIZE 3
+
+extern void _blast_cache_range(unsigned long start, unsigned long end);
+#define flush_insn_slot(p)						\
+do {									\
+	_blast_cache_range((unsigned long)p->addr,			\
+			   (unsigned long)p->addr +			\
+			   (MAX_INSN_SIZE * sizeof(kprobe_opcode_t)));	\
+} while (0)
+
+
+/* regs_return_value() is used in test_kprobes.c */
+#ifdef CONFIG_KPROBES_SANITY_TEST
+#define regs_return_value(_regs)	((_regs)->regs[2])
+#endif
+extern const int kretprobe_blacklist_size;
+
+void arch_remove_kprobe(struct kprobe *p);
+
+/* Architecture specific copy of original instruction*/
+struct arch_specific_insn {
+	/* copy of the original instruction */
+	kprobe_opcode_t *insn;
+};
+
+struct prev_kprobe {
+	struct kprobe *kp;
+	unsigned long status;
+	unsigned long old_SR;
+	unsigned long saved_SR;
+	unsigned long saved_epc;
+};
+
+#define MAX_JPROBES_STACK_SIZE 128
+#define MAX_JPROBES_STACK_ADDR \
+	(((unsigned long)current_thread_info()) + THREAD_SIZE - 32 - sizeof(struct pt_regs))
+
+#define MIN_JPROBES_STACK_SIZE(ADDR)					\
+	((((ADDR) + MAX_JPROBES_STACK_SIZE) > MAX_JPROBES_STACK_ADDR)	\
+		? MAX_JPROBES_STACK_ADDR - (ADDR)			\
+		: MAX_JPROBES_STACK_SIZE)
+
+
+/* per-cpu kprobe control block */
+struct kprobe_ctlblk {
+	unsigned long kprobe_status;
+	unsigned long kprobe_old_SR;
+	unsigned long kprobe_saved_SR;
+	unsigned long kprobe_saved_epc;
+	unsigned long jprobe_saved_sp;
+	struct pt_regs jprobe_saved_regs;
+	u8 jprobes_stack[MAX_JPROBES_STACK_SIZE];
+	struct prev_kprobe prev_kprobe;
+};
+
+extern int kprobe_exceptions_notify(struct notifier_block *self,
+				    unsigned long val, void *data);
+extern unsigned long _mips_unwind_stack(struct task_struct *task, unsigned long *sp,
+				 unsigned long pc, unsigned long *ra);
+
+#endif				/* _ASM_KPROBES_H */
diff --git a/arch/mips/include/asm/mach-jz4750/board-apus.h b/arch/mips/include/asm/mach-jz4750/board-apus.h
index 12e45e1ded3..da82ea73563 100644
--- a/arch/mips/include/asm/mach-jz4750/board-apus.h
+++ b/arch/mips/include/asm/mach-jz4750/board-apus.h
@@ -15,13 +15,13 @@
 #ifndef __ASM_JZ4750_APUS_H__
 #define __ASM_JZ4750_APUS_H__
 
-/*====================================================================== 
+/*======================================================================
  * Frequencies of on-board oscillators
  */
 #define JZ_EXTAL		24000000  /* Main extal freq: 24 MHz */
 #define JZ_EXTAL2		32768     /* RTC extal freq: 32.768 KHz */
 
-/*====================================================================== 
+/*======================================================================
  * GPIO
  */
 #define GPIO_DISP_OFF_N         (32*4+25) /* GPE25 */
@@ -38,7 +38,7 @@
 #define GPIO_UDC_HOTPLUG	GPIO_USB_DETE
 
 
-/*====================================================================== 
+/*======================================================================
  * LCD backlight
  */
 #define LCD_PWM_CHN 4    /* pwm channel */
@@ -54,7 +54,7 @@
 static inline void __lcd_pwm_set_backlight_level(int n)
 {
 	__tcu_stop_counter(LCD_PWM_CHN);
-	
+
 	__tcu_set_pwm_output_shutdown_abrupt(LCD_PWM_CHN);
 	__tcu_disable_pwm_output(LCD_PWM_CHN);
 
@@ -73,7 +73,7 @@ static inline void __lcd_pwm_start(void)
 	__gpio_as_pwm(4);
 
 	__tcu_stop_counter(LCD_PWM_CHN);
-	
+
 	__tcu_select_extalclk(LCD_PWM_CHN);
 	__tcu_select_clk_div4(LCD_PWM_CHN);
 	__tcu_init_pwm_output_high(LCD_PWM_CHN);
@@ -146,7 +146,7 @@ do {					\
 #define ACTIVE_WAKE_UP 		1
 
 
-/*====================================================================== 
+/*======================================================================
  * MMC/SD
  */
 
@@ -206,4 +206,6 @@ do {						\
 	detected;				\
 })
 
+#define JZ_EARLY_UART_BASE UART3_BASE
+
 #endif /* __ASM_JZ4750_APUS_H__ */
diff --git a/arch/mips/include/asm/mach-jz4750/board-fuwa.h b/arch/mips/include/asm/mach-jz4750/board-fuwa.h
index 8b6a1992c9e..34df8da4b4f 100644
--- a/arch/mips/include/asm/mach-jz4750/board-fuwa.h
+++ b/arch/mips/include/asm/mach-jz4750/board-fuwa.h
@@ -17,14 +17,14 @@
 
 #define CONFIG_FPGA	 /* fuwa is an FPGA board */
 
-/*====================================================================== 
+/*======================================================================
  * Frequencies of on-board oscillators
  */
 #define JZ_EXTAL		48000000  /* Main extal freq: 12 MHz */
 #define JZ_EXTAL2		32768     /* RTC extal freq: 32.768 KHz */
 
 
-/*====================================================================== 
+/*======================================================================
  * GPIO
  */
 #define GPIO_SD_VCC_EN_N	113 /* GPD17 */
@@ -38,7 +38,7 @@
 
 #define GPIO_UDC_HOTPLUG	GPIO_USB_DETE
 
-/*====================================================================== 
+/*======================================================================
  * LCD backlight
  */
 #define GPIO_LCD_PWM   		(32*4+20) /* GPE20 */
@@ -58,7 +58,7 @@ do {					\
 	__gpio_clear_pin(GPIO_LCD_PWM);	\
 } while (0)
 
-/*====================================================================== 
+/*======================================================================
  * MMC/SD
  */
 
@@ -90,4 +90,6 @@ do {						\
 	detected;				\
 })
 
+#define JZ_EARLY_UART_BASE UART3_BASE
+
 #endif /* __ASM_JZ4750_FUWA_H__ */
diff --git a/arch/mips/include/asm/mach-jz4750/dma.h b/arch/mips/include/asm/mach-jz4750/dma.h
index fc1f2c8e92d..d4b48ffcb55 100644
--- a/arch/mips/include/asm/mach-jz4750/dma.h
+++ b/arch/mips/include/asm/mach-jz4750/dma.h
@@ -76,6 +76,8 @@ enum {
 	DMA_ID_SSI1_RX,		/* SSI1 receive-fifo-empty request */
 	DMA_ID_PCM_TX,		/* PM transmit-fifo-full request */
 	DMA_ID_PCM_RX,		/* PM receive-fifo-empty request */
+	DMA_ID_AX88796C_TX,
+	DMA_ID_AX88796C_RX,
 	DMA_ID_RAW_SET,
 	DMA_ID_MAX
 };
diff --git a/arch/mips/include/asm/mach-jz4750/jz4750.h b/arch/mips/include/asm/mach-jz4750/jz4750.h
index 4cd6698e6d3..3562302c2e9 100644
--- a/arch/mips/include/asm/mach-jz4750/jz4750.h
+++ b/arch/mips/include/asm/mach-jz4750/jz4750.h
@@ -19,6 +19,7 @@
 #include <asm/mach-jz4750/ops.h>
 #include <asm/mach-jz4750/dma.h>
 #include <asm/mach-jz4750/misc.h>
+#include <asm/mach-jz4750/platform.h>
 
 /*------------------------------------------------------------------
  * Platform definitions
@@ -43,5 +44,6 @@
 #include <asm/mach-jz4750/clock.h>
 #include <asm/mach-jz4750/serial.h>
 #include <asm/mach-jz4750/i2c.h>
+#include <asm/mach-jz4750/spi.h>
 
 #endif /* __ASM_JZ4750_H__ */
diff --git a/arch/mips/include/asm/mach-jz4750/ops.h b/arch/mips/include/asm/mach-jz4750/ops.h
index a463bbb4ca3..6efa0fa5a85 100644
--- a/arch/mips/include/asm/mach-jz4750/ops.h
+++ b/arch/mips/include/asm/mach-jz4750/ops.h
@@ -732,6 +732,20 @@ do {						\
 /* n = 0(SSI0), 1(SSI1) */
 #define __gpio_as_ssi(n)	 __gpio_as_ssi##n()
 
+#define __gpio_as_ssi0_x()			\
+do {						\
+	REG_GPIO_PXFUNS(1) = 0x1c000000;	\
+	REG_GPIO_PXSELC(1) = 0x1c000000;	\
+	REG_GPIO_PXPES(1)  = 0x1c000000;	\
+} while (0)
+
+#define __gpio_as_ssi1_x()			\
+do {						\
+	REG_GPIO_PXFUNS(3) = 0x1c000000;	\
+	REG_GPIO_PXSELC(3) = 0x1c000000;	\
+	REG_GPIO_PXPES(3)  = 0x1c000000;	\
+} while (0)
+
 /*
  * I2C_SCK, I2C_SDA
  */
@@ -1040,7 +1054,7 @@ do {						\
 #define __cpm_get_uhcdiv() \
 	((REG_CPM_UHCCDR & CPM_UHCCDR_UHCDIV_MASK) >> CPM_UHCCDR_UHCDIV_BIT)
 #define __cpm_get_ssidiv() \
-	((REG_CPM_SSICCDR & CPM_SSICDR_SSICDIV_MASK) >> CPM_SSICDR_SSIDIV_BIT)
+	((REG_CPM_SSICDR & CPM_SSICDR_SSIDIV_MASK) >> CPM_SSICDR_SSIDIV_BIT)
 #define __cpm_get_pcmdiv(v) \
 	((REG_CPM_PCMCDR & CPM_PCMCDR_PCMCD_MASK) >> CPM_PCMCDR_PCMCD_BIT)
 
@@ -2330,7 +2344,19 @@ do { 						\
 #define __ssi_receive_data(n) 		REG_SSI_DR(n)
 #define __ssi_transmit_data(n, v) 	(REG_SSI_DR(n) = (v))
 
-
+#define __ssi_set_grdiv(n,v)			(REG_SSI_GR(n) = v)
+#define __ssi_get_grdiv(n)				(REG_SSI_GR(n))
+
+#define __ssi_txfifo_half_empty_intr(n)  \
+	( REG_SSI_CR0(n) & SSI_CR0_TIE )
+#define __ssi_rxfifo_half_full_intr(n)	\
+	( REG_SSI_CR0(n) & SSI_CR0_RIE )
+	
+#define __ssi_tx_error_intr(n)		\
+	( REG_SSI_CR0(n) & SSI_CR0_TEIE )
+#define __ssi_rx_error_intr(n)		\
+	( REG_SSI_CR0(n) & SSI_CR0_REIE )	
+	
 /***************************************************************************
  * CIM
  ***************************************************************************/
diff --git a/arch/mips/include/asm/mach-jz4750/platform.h b/arch/mips/include/asm/mach-jz4750/platform.h
new file mode 100644
index 00000000000..8e8e9d44dd8
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4750/platform.h
@@ -0,0 +1,32 @@
+#ifndef __JZ4750_PLATFORM_H__
+#define __JZ4750_PLATFORM_H__
+
+/* msc */
+#define CARD_INSERTED 1
+#define CARD_REMOVED 0
+
+struct jz_mmc_platform_data {
+	unsigned int ocr_mask;			/* available voltages */
+	unsigned long detect_delay;		/* delay in jiffies before detecting cards after interrupt */
+	unsigned char status_irq;
+	unsigned char support_sdio;
+	unsigned char bus_width;
+	unsigned int max_bus_width;
+	unsigned int detect_pin;
+
+	unsigned char msc_irq;
+	unsigned char dma_rxid;
+	unsigned char dma_txid;
+
+	void *driver_data;
+
+	void (*init) (struct device *);
+	void (*power_on) (struct device *);
+	void (*power_off) (struct device *);
+	void (*cpm_start) (struct device *);
+	unsigned int (*status) (struct device *);
+	unsigned int (*write_protect) (struct device *);
+	void (*plug_change) (int);
+};
+
+#endif /* __JZ4750_PLATFORM_H__ */
diff --git a/arch/mips/include/asm/mach-jz4750/regs.h b/arch/mips/include/asm/mach-jz4750/regs.h
index e2636ac8ba3..d5b3e83708f 100644
--- a/arch/mips/include/asm/mach-jz4750/regs.h
+++ b/arch/mips/include/asm/mach-jz4750/regs.h
@@ -1578,6 +1578,10 @@
 /*************************************************************************
  * MSC
  ************************************************************************/
+#define JZ_MAX_MSC_NUM 2
+
+#define JZ_MSC_ID_INVALID(msc_id) ( ((msc_id) < 0) || ( (msc_id) > JZ_MAX_MSC_NUM ) )
+
 /* n = 0, 1 (MSC0, MSC1) */
 #define	MSC_STRPCL(n)		(MSC_BASE + (n)*0x1000 + 0x000)
 #define	MSC_STAT(n)		(MSC_BASE + (n)*0x1000 + 0x004)
diff --git a/arch/mips/include/asm/mach-jz4750/spi.h b/arch/mips/include/asm/mach-jz4750/spi.h
new file mode 100644
index 00000000000..1e329a15e3a
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4750/spi.h
@@ -0,0 +1,87 @@
+/*

+ * linux/arch/mips/include/asm/mach-jz4750/spi.h

+ *

+ * SSI controller for SPI protocol,use FIFO and DMA;

+ *

+ * Copyright (c) 2010 Ingenic Semiconductor Inc.

+ * Author: Shumb <sbhuang@ingenic.cn>

+ *

+ *  This program is free software; you can redistribute	 it and/or modify it

+ *  under  the terms of	 the GNU General  Public License as published by the

+ *  Free Software Foundation;  either version 2 of the	License, or (at your

+ *  option) any later version.

+ */

+

+#ifndef __I_SPI_H__

+#define __I_SPI_H__

+

+#define R_MODE		0x1

+#define W_MODE		0x2

+#define RW_MODE	(R_MODE | W_MODE)

+

+#define R_DMA		0x4

+#define W_DMA		0x8

+#define RW_DMA		(R_DMA |W_DMA)

+

+#define SPI_DMA_ERROR  		3

+#define SPI_CPU_ERROR		4

+

+#define JZ_SSI_MAX_FIFO_ENTRIES 	128

+#define JZ_SSI_DMA_BURST_LENGTH 	16

+

+#define FIFO_8_BIT		1

+#define FIFO_16_BIT		2

+#define FIFO_32_BIT		4

+

+

+/* the max number of spi devices */

+#define MAX_SPI_DEVICES				10

+

+#define PIN_SSI_CE0 	0

+#define PIN_SSI_CE1 	1

+

+struct jz47xx_spi_info {

+	u8	chnl;								/* the chanel of SSI controller */

+	u16	bus_num;							/* spi_master.bus_num */

+	unsigned is_pllclk:1;					/* source clock: 1---pllclk;0---exclk */

+	unsigned long		 board_size;		/* spi_master.num_chipselect */

+	struct spi_board_info	*board_info; 	/* link to spi devices info */

+	void (*set_cs)(struct jz47xx_spi_info *spi, u8 cs,unsigned int pol); /* be defined by spi devices driver user */

+	void (*pins_config)(void);				/* configure spi function pins (CLK,DR,RT) by user if need. */

+	u32		 pin_cs[MAX_SPI_DEVICES];		/* the member is pin_value according to spi_device.chip_select,

+												if uses spi controller driver "set_cs",it must be filled.*/

+};

+

+/* Chipselect "set_cs" function could be defined by user. Example as the follow ... */

+/*

+static void spi_gpio_cs(struct jz47xx_spi_info *spi, int cs, int pol);

+{

+	int pinval;

+

+	switch(cs){

+	case 0:

+		pinval = 32*1+31;

+		break;

+	case 1:

+		pinval = 32*1+30;

+		break;

+	case 2:

+		pinval = 32*1+29;

+		break;

+	default:

+		pinval = 32*1+28;

+		break;	

+	}

+	__gpio_as_output(pinval);				

+	switch (pol) {

+	case BITBANG_CS_ACTIVE:

+		__gpio_set_pin(pinval);

+		break;

+	case BITBANG_CS_INACTIVE:

+		__gpio_clear_pin(pinval);

+		break;

+	}

+

+}*/

+

+#endif

diff --git a/arch/mips/include/asm/mach-jz4750d/jz4750d.h b/arch/mips/include/asm/mach-jz4750d/jz4750d.h
index 5b842567f38..8dafdc5925c 100644
--- a/arch/mips/include/asm/mach-jz4750d/jz4750d.h
+++ b/arch/mips/include/asm/mach-jz4750d/jz4750d.h
@@ -19,6 +19,7 @@
 #include <asm/mach-jz4750d/ops.h>
 #include <asm/mach-jz4750d/dma.h>
 #include <asm/mach-jz4750d/misc.h>
+#include <asm/mach-jz4750d/platform.h>
 
 /*------------------------------------------------------------------
  * Platform definitions
diff --git a/arch/mips/include/asm/mach-jz4750d/platform.h b/arch/mips/include/asm/mach-jz4750d/platform.h
new file mode 100644
index 00000000000..6f5861af0c1
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4750d/platform.h
@@ -0,0 +1,32 @@
+#ifndef __JZ4750D_PLATFORM_H__
+#define __JZ4750D_PLATFORM_H__
+
+/* msc */
+#define CARD_INSERTED 1
+#define CARD_REMOVED 0
+
+struct jz_mmc_platform_data {
+	unsigned int ocr_mask;			/* available voltages */
+	unsigned long detect_delay;		/* delay in jiffies before detecting cards after interrupt */
+	unsigned char status_irq;
+	unsigned char support_sdio;
+	unsigned char bus_width;
+	unsigned int max_bus_width;
+	unsigned int detect_pin;
+
+	unsigned char msc_irq;
+	unsigned char dma_rxid;
+	unsigned char dma_txid;
+
+	void *driver_data;
+
+	void (*init) (struct device *);
+	void (*power_on) (struct device *);
+	void (*power_off) (struct device *);
+	void (*cpm_start) (struct device *);
+	unsigned int (*status) (struct device *);
+	unsigned int (*write_protect) (struct device *);
+	void (*plug_change) (int);
+};
+
+#endif /* __JZ4750D_PLATFORM_H__ */
diff --git a/arch/mips/include/asm/mach-jz4750d/regs.h b/arch/mips/include/asm/mach-jz4750d/regs.h
index f612aa9b208..2e020e89303 100644
--- a/arch/mips/include/asm/mach-jz4750d/regs.h
+++ b/arch/mips/include/asm/mach-jz4750d/regs.h
@@ -747,7 +747,7 @@
 #define DMAC_DCCSR_CT		(1 << 1)  /* count terminated */
 #define DMAC_DCCSR_EN		(1 << 0)  /* channel enable bit */
 
-// DMA channel command register 
+// DMA channel command register
 #define DMAC_DCMD_EACKS_LOW  	(1 << 31) /* External DACK Output Level Select, active low */
 #define DMAC_DCMD_EACKS_HIGH  	(0 << 31) /* External DACK Output Level Select, active high */
 #define DMAC_DCMD_EACKM_WRITE 	(1 << 30) /* External DACK Output Mode Select, output in write cycle */
@@ -1306,7 +1306,7 @@
 #define	REG_ICDC_RGDATA		REG32(ICDC_RGDATA)
 
 /* ICDC Clock Configure Register */
-#define	ICDC_CKCFG_CKRDY	(1 << 1) 
+#define	ICDC_CKCFG_CKRDY	(1 << 1)
 #define	ICDC_CKCFG_SELAD	(1 << 0)
 
 /* ICDC internal register access control Register */
@@ -1507,7 +1507,7 @@
   #define SSI_CR1_FMAT_MW1	  (2 << SSI_CR1_FMAT_BIT) /* National Microwire 1 format */
   #define SSI_CR1_FMAT_MW2	  (3 << SSI_CR1_FMAT_BIT) /* National Microwire 2 format */
 #define SSI_CR1_TTRG_BIT	16 /* SSI1 TX trigger */
-#define SSI_CR1_TTRG_MASK	(0xf << SSI_CR1_TTRG_BIT) 
+#define SSI_CR1_TTRG_MASK	(0xf << SSI_CR1_TTRG_BIT)
 #define SSI_CR1_MCOM_BIT	12
 #define SSI_CR1_MCOM_MASK	(0xf << SSI_CR1_MCOM_BIT)
   #define SSI_CR1_MCOM_1BIT	  (0x0 << SSI_CR1_MCOM_BIT) /* 1-bit command selected */
@@ -1574,6 +1574,9 @@
 /*************************************************************************
  * MSC
  ************************************************************************/
+#define JZ_MAX_MSC_NUM 2
+
+#define JZ_MSC_ID_INVALID(msc_id) ( ((msc_id) < 0) || ( (msc_id) > JZ_MAX_MSC_NUM ) )
 /* n = 0, 1 (MSC0, MSC1) */
 #define	MSC_STRPCL(n)		(MSC_BASE + (n)*0x1000 + 0x000)
 #define	MSC_STAT(n)		(MSC_BASE + (n)*0x1000 + 0x004)
@@ -1598,7 +1601,7 @@
 #define	REG_MSC_CLKRT(n)	REG16(MSC_CLKRT(n))
 #define	REG_MSC_CMDAT(n)	REG32(MSC_CMDAT(n))
 #define	REG_MSC_RESTO(n)	REG16(MSC_RESTO(n))
-#define	REG_MSC_RDTO(n)		REG16(MSC_RDTO(n))
+#define	REG_MSC_RDTO(n)		REG32(MSC_RDTO(n))
 #define	REG_MSC_BLKLEN(n)	REG16(MSC_BLKLEN(n))
 #define	REG_MSC_NOB(n)		REG16(MSC_NOB(n))
 #define	REG_MSC_SNOB(n)		REG16(MSC_SNOB(n))
@@ -2595,8 +2598,8 @@
 #define TVE_CTRL_EYCBCR         (1 << 25)    /* YCbCr_enable */
 #define TVE_CTRL_ECVBS          (1 << 24)    /* cvbs_enable */
 #define TVE_CTRL_DAPD3	        (1 << 23)    /* DAC 3 power down */
-#define TVE_CTRL_DAPD2	        (1 << 22)    /* DAC 2 power down */	
-#define TVE_CTRL_DAPD1	        (1 << 21)    /* DAC 1 power down */	
+#define TVE_CTRL_DAPD2	        (1 << 22)    /* DAC 2 power down */
+#define TVE_CTRL_DAPD1	        (1 << 21)    /* DAC 1 power down */
 #define TVE_CTRL_DAPD           (1 << 20)    /* power down all DACs */
 #define TVE_CTRL_YCDLY_BIT      16
 #define TVE_CTRL_YCDLY_MASK     (0x7 << TVE_CTRL_YCDLY_BIT)
@@ -3175,7 +3178,7 @@
 #define TSSI_PID6      ( TSSI_BASE + 0x38 )
 #define TSSI_PID7      ( TSSI_BASE + 0x3c )
 #define TSSI_PID_MAX   8	/* max PID: 7 */
- 
+
 #define REG_TSSI_ENA       REG8( TSSI_ENA )
 #define REG_TSSI_CFG       REG16( TSSI_CFG )
 #define REG_TSSI_CTRL      REG8( TSSI_CTRL )
@@ -3229,21 +3232,21 @@
 
 /* TSSI PID enable register */
 #define TSSI_PEN_EN00 	( 1 << 0 )      /* enable PID n */
-#define TSSI_PEN_EN10 	( 1 << 1 )      
-#define TSSI_PEN_EN20 	( 1 << 2 )      
-#define TSSI_PEN_EN30 	( 1 << 3 )      
-#define TSSI_PEN_EN40 	( 1 << 4 )      
-#define TSSI_PEN_EN50 	( 1 << 5 )      
-#define TSSI_PEN_EN60 	( 1 << 6 )      
-#define TSSI_PEN_EN70 	( 1 << 7 )      
-#define TSSI_PEN_EN01 	( 1 << 16 )      
-#define TSSI_PEN_EN11 	( 1 << 17 )      
-#define TSSI_PEN_EN21 	( 1 << 18 )     
-#define TSSI_PEN_EN31 	( 1 << 19 )      
-#define TSSI_PEN_EN41 	( 1 << 20 )     
-#define TSSI_PEN_EN51 	( 1 << 21 )      
-#define TSSI_PEN_EN61 	( 1 << 22 )     
-#define TSSI_PEN_EN71 	( 1 << 23 )      
+#define TSSI_PEN_EN10 	( 1 << 1 )
+#define TSSI_PEN_EN20 	( 1 << 2 )
+#define TSSI_PEN_EN30 	( 1 << 3 )
+#define TSSI_PEN_EN40 	( 1 << 4 )
+#define TSSI_PEN_EN50 	( 1 << 5 )
+#define TSSI_PEN_EN60 	( 1 << 6 )
+#define TSSI_PEN_EN70 	( 1 << 7 )
+#define TSSI_PEN_EN01 	( 1 << 16 )
+#define TSSI_PEN_EN11 	( 1 << 17 )
+#define TSSI_PEN_EN21 	( 1 << 18 )
+#define TSSI_PEN_EN31 	( 1 << 19 )
+#define TSSI_PEN_EN41 	( 1 << 20 )
+#define TSSI_PEN_EN51 	( 1 << 21 )
+#define TSSI_PEN_EN61 	( 1 << 22 )
+#define TSSI_PEN_EN71 	( 1 << 23 )
 #define TSSI_PEN_PID0 	( 1 << 31 ) /* PID filter enable PID0 */
 
 /* TSSI PID Filter Registers */
@@ -3258,79 +3261,79 @@
  *************************************************************************/
 
 /* IPU Control Register */
-#define REG_IPU_CTRL			(IPU_BASE + 0x0) 
+#define REG_IPU_CTRL			(IPU_BASE + 0x0)
 
 /* IPU Status Register */
-#define REG_IPU_STATUS			(IPU_BASE + 0x4) 
+#define REG_IPU_STATUS			(IPU_BASE + 0x4)
 
 /* Data Format Register */
-#define REG_IPU_D_FMT			(IPU_BASE + 0x8) 
+#define REG_IPU_D_FMT			(IPU_BASE + 0x8)
 
 /* Input Y or YUV422 Packaged Data Address Register */
-#define REG_IPU_Y_ADDR			(IPU_BASE + 0xc) 
+#define REG_IPU_Y_ADDR			(IPU_BASE + 0xc)
 
 /* Input U Data Address Register */
-#define REG_IPU_U_ADDR			(IPU_BASE + 0x10) 
+#define REG_IPU_U_ADDR			(IPU_BASE + 0x10)
 
 /* Input V Data Address Register */
-#define REG_IPU_V_ADDR			(IPU_BASE + 0x14) 
+#define REG_IPU_V_ADDR			(IPU_BASE + 0x14)
 
 /* Input Geometric Size Register */
-#define REG_IPU_IN_FM_GS		(IPU_BASE + 0x18) 
+#define REG_IPU_IN_FM_GS		(IPU_BASE + 0x18)
 
 /* Input Y Data Line Stride Register */
-#define REG_IPU_Y_STRIDE		(IPU_BASE + 0x1c) 
+#define REG_IPU_Y_STRIDE		(IPU_BASE + 0x1c)
 
 /* Input UV Data Line Stride Register */
-#define REG_IPU_UV_STRIDE		(IPU_BASE + 0x20) 
+#define REG_IPU_UV_STRIDE		(IPU_BASE + 0x20)
 
 /* Output Frame Start Address Register */
-#define REG_IPU_OUT_ADDR		(IPU_BASE + 0x24) 
+#define REG_IPU_OUT_ADDR		(IPU_BASE + 0x24)
 
 /* Output Geometric Size Register */
-#define REG_IPU_OUT_GS			(IPU_BASE + 0x28) 
+#define REG_IPU_OUT_GS			(IPU_BASE + 0x28)
 
 /* Output Data Line Stride Register */
-#define REG_IPU_OUT_STRIDE		(IPU_BASE + 0x2c) 
+#define REG_IPU_OUT_STRIDE		(IPU_BASE + 0x2c)
 
 /* Resize Coefficients Table Index Register */
-#define REG_IPU_RSZ_COEF_INDEX		(IPU_BASE + 0x30) 
+#define REG_IPU_RSZ_COEF_INDEX		(IPU_BASE + 0x30)
 
 /* CSC C0 Coefficient Register */
-#define REG_IPU_CSC_CO_COEF		(IPU_BASE + 0x34) 
+#define REG_IPU_CSC_CO_COEF		(IPU_BASE + 0x34)
 
 /* CSC C1 Coefficient Register */
-#define REG_IPU_CSC_C1_COEF		(IPU_BASE + 0x38) 
+#define REG_IPU_CSC_C1_COEF		(IPU_BASE + 0x38)
 
 /* CSC C2 Coefficient Register */
-#define REG_IPU_CSC_C2_COEF		(IPU_BASE + 0x3c) 
+#define REG_IPU_CSC_C2_COEF		(IPU_BASE + 0x3c)
 
 /* CSC C3 Coefficient Register */
-#define REG_IPU_CSC_C3_COEF		(IPU_BASE + 0x40) 
+#define REG_IPU_CSC_C3_COEF		(IPU_BASE + 0x40)
 
 /* CSC C4 Coefficient Register */
-#define REG_IPU_CSC_C4_COEF		(IPU_BASE + 0x44) 
+#define REG_IPU_CSC_C4_COEF		(IPU_BASE + 0x44)
 
 /* Horizontal Resize Coefficients Look Up Table Register group */
-#define REG_IPU_HRSZ_LUT_BASE 		(IPU_BASE + 0x48) 
+#define REG_IPU_HRSZ_LUT_BASE 		(IPU_BASE + 0x48)
 
 /* Virtical Resize Coefficients Look Up Table Register group */
-#define REG_IPU_VRSZ_LUT_BASE 		(IPU_BASE + 0x4c) 
+#define REG_IPU_VRSZ_LUT_BASE 		(IPU_BASE + 0x4c)
 
 /* CSC Offset Parameter Register */
 #define REG_IPU_CSC_OFSET_PARA		(IPU_BASE + 0x50)
 
 /* Input Y Physical Table Address Register */
-#define REG_IPU_Y_PHY_T_ADDR		(IPU_BASE + 0x54) 
+#define REG_IPU_Y_PHY_T_ADDR		(IPU_BASE + 0x54)
 
 /* Input U Physical Table Address Register */
-#define REG_IPU_U_PHY_T_ADDR		(IPU_BASE + 0x58) 
+#define REG_IPU_U_PHY_T_ADDR		(IPU_BASE + 0x58)
 
 /* Input V Physical Table Address Register */
-#define REG_IPU_V_PHY_T_ADDR		(IPU_BASE + 0x5c) 
+#define REG_IPU_V_PHY_T_ADDR		(IPU_BASE + 0x5c)
 
 /* Output Physical Table Address Register */
-#define REG_IPU_OUT_PHY_T_ADDR		(IPU_BASE + 0x60) 
+#define REG_IPU_OUT_PHY_T_ADDR		(IPU_BASE + 0x60)
 
 /* IPU Control */
 #define IPU_CTRL_DFIX_SEL			(1 << 17)
diff --git a/arch/mips/include/asm/mach-jz4760/board-altair.h b/arch/mips/include/asm/mach-jz4760/board-altair.h
index f7f5f4a00a3..c72c2321475 100644
--- a/arch/mips/include/asm/mach-jz4760/board-altair.h
+++ b/arch/mips/include/asm/mach-jz4760/board-altair.h
@@ -80,7 +80,7 @@
 #define LCD_INT			(32 * 0 + 16) /* GPA16 interrupt pin */
 #define LCD_INT_IRQ		(IRQ_GPIO_0 + LCD_INT)
 
-/* 
+/*
  * E-Compass and G-Sensor
  */
 #define COMPASS_RSTN	(32*3+5)	/* GPD5 */
@@ -105,7 +105,7 @@
 #define MSC1_HOTPLUG_PIN	GPIO_SD1_CD_N
 #define MSC1_HOTPLUG_IRQ	(IRQ_GPIO_0 + GPIO_SD1_CD_N)
 
-/*====================================================================== 
+/*======================================================================
  * Modem
  */
 #if defined(CONFIG_GSM_IW368)
@@ -213,4 +213,6 @@ do {								\
 #define ACTIVE_LOW_MSC0_CD	1 /* work when GPIO_SD1_CD_N is low */
 #define ACTIVE_LOW_MSC1_CD	0 /* work when GPIO_SD1_CD_N is low */
 
+#define JZ_EARLY_UART_BASE UART1_BASE
+
 #endif /* __ASM_JZ4760_ALTAIR_H__ */
diff --git a/arch/mips/include/asm/mach-jz4760/board-cygnus.h b/arch/mips/include/asm/mach-jz4760/board-cygnus.h
index eec766d750f..cad7318b17a 100644
--- a/arch/mips/include/asm/mach-jz4760/board-cygnus.h
+++ b/arch/mips/include/asm/mach-jz4760/board-cygnus.h
@@ -27,6 +27,12 @@
 /*======================================================================
  * SYSTEM GPIO
  */
+
+#define GPIO_I2C1_SDA           (32*1+20)       /* GPB20 */
+#define GPIO_I2C1_SCK           (32*1+21)       /* GPB21 */
+
+#define GPIO_POWER_ON           (32 * 0 + 30)  /* GPA30 */
+
 #define GPIO_DISP_OFF_N		(32 * 4 + 11) /* GPE11 */ //???
 
 #define GPIO_SD0_VCC_EN_N	(32 * 4 + 2) /* GPE02 */
@@ -99,12 +105,66 @@
 #define MSC1_HOTPLUG_PIN	GPIO_SD1_CD_N
 #define MSC1_HOTPLUG_IRQ	(IRQ_GPIO_0 + GPIO_SD1_CD_N)
 
+#define __msc0_init_io()			\
+do {						\
+	__gpio_as_output(GPIO_SD0_VCC_EN_N);	\
+	__gpio_as_input(GPIO_SD0_CD_N);		\
+} while (0)
+
+#define __msc0_enable_power()			\
+do {						\
+	__gpio_clear_pin(GPIO_SD0_VCC_EN_N);	\
+} while (0)
+
+#define __msc0_disable_power()			\
+do {						\
+	__gpio_set_pin(GPIO_SD0_VCC_EN_N);	\
+} while (0)
+
+#define __msc0_card_detected(s)			\
+({						\
+	int detected = 1;			\
+	if (__gpio_get_pin(GPIO_SD0_CD_N))	\
+		detected = 0;			\
+	detected;				\
+})
+
+#define __msc1_init_io()			\
+do {						\
+	__gpio_as_output(GPIO_SD1_VCC_EN_N);	\
+	__gpio_as_input(GPIO_SD1_CD_N);		\
+} while (0)
+
+#define __msc1_enable_power()			\
+do {						\
+	__gpio_clear_pin(GPIO_SD1_VCC_EN_N);	\
+} while (0)
+
+#define __msc1_disable_power()			\
+do {						\
+	__gpio_set_pin(GPIO_SD1_VCC_EN_N);	\
+} while (0)
+
+#define __msc1_card_detected(s)			\
+({						\
+	int detected = 1;			\
+	if (__gpio_get_pin(GPIO_SD1_CD_N))	\
+		detected = 0;			\
+	detected;				\
+})
+
+
+
 /*======================================================================
  * LCD backlight
  */
 #define LCD_PWM_CHN 4    /* pwm channel */
 #define LCD_PWM_FULL 256
 #define PWM_BACKLIGHT_CHIP	0	/*0: digital pusle; 1: PWM*/
+#define LCD_DEFAULT_BACKLIGHT           80
+#define LCD_MAX_BACKLIGHT               100
+#define LCD_MIN_BACKLIGHT               1
+
 
 #if 1
 #if PWM_BACKLIGHT_CHIP
@@ -190,4 +250,6 @@ do {								\
 #define ACTIVE_LOW_MSC0_CD	1 /* work when GPIO_SD1_CD_N is low */
 #define ACTIVE_LOW_MSC1_CD	0 /* work when GPIO_SD1_CD_N is low */
 
+#define JZ_EARLY_UART_BASE UART1_BASE
+
 #endif /* __ASM_JZ4760_CYGNUS_H__ */
diff --git a/arch/mips/include/asm/mach-jz4760/board-f4760.h b/arch/mips/include/asm/mach-jz4760/board-f4760.h
index f58e9a69af0..1e27611f4d3 100644
--- a/arch/mips/include/asm/mach-jz4760/board-f4760.h
+++ b/arch/mips/include/asm/mach-jz4760/board-f4760.h
@@ -17,14 +17,14 @@
 
 #define CONFIG_FPGA	 /* fuwa is an FPGA board */
 
-/*====================================================================== 
+/*======================================================================
  * Frequencies of on-board oscillators
  */
 #define JZ_EXTAL		24000000  /* Main extal freq: 12 MHz */
 #define JZ_EXTAL2		32768     /* RTC extal freq: 32.768 KHz */
 #define CFG_DIV		2	/* cpu/extclk; only for FPGA */
 
-/*====================================================================== 
+/*======================================================================
  * GPIO
  */
 #define GPIO_SD_VCC_EN_N	113 /* GPD17 */
@@ -38,7 +38,7 @@
 
 #define GPIO_UDC_HOTPLUG	GPIO_USB_DETE
 
-/*====================================================================== 
+/*======================================================================
  * LCD backlight
  */
 #define GPIO_LCD_PWM   		(32*4+4) /* GPE4 PWM4 */
@@ -58,7 +58,7 @@ do {					\
 	__gpio_clear_pin(GPIO_LCD_PWM);	\
 } while (0)
 
-/*====================================================================== 
+/*======================================================================
  * MMC/SD
  */
 
@@ -90,4 +90,6 @@ do {						\
 	detected;				\
 })
 
+#define JZ_EARLY_UART_BASE UART1_BASE
+
 #endif /* __ASM_JZ4760_F4760_H__ */
diff --git a/arch/mips/include/asm/mach-jz4760/board-htb80.h b/arch/mips/include/asm/mach-jz4760/board-htb80.h
new file mode 100644
index 00000000000..16aa1b0aed6
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4760/board-htb80.h
@@ -0,0 +1,283 @@
+/*
+ * linux/include/asm-mips/mach-jz4760/board-htb80.h
+ *
+ * JZ4760-based LEPUS board ver 1.0 definition.
+ *
+ * Copyright (C) 2010 Ingenic Semiconductor Inc.
+ *
+ * Author: James<ljia@ingenic.cn>
+ *		Based on board-cygnus.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_JZ4760_HTB80_H__
+#define __ASM_JZ4760_HTB80_H__
+
+/*======================================================================
+ * Frequencies of on-board oscillators
+ */
+#define JZ_EXTAL		12000000  /* Main extal freq:	12 MHz */
+#define JZ_EXTAL2		32768     /* RTC extal freq:	32.768 KHz */
+
+/*======================================================================
+ * SYSTEM GPIO
+ */
+
+/*  */
+/* TF-card on MSC1 */
+#define GPIO_SD1_VCC_EN_N	(32 * 1 + 23)  /* GPB23 */
+#define GPIO_SD1_CD_N		(32 * 1 + 22) /* GPB22 */
+#define MSC1_HOTPLUG_PIN	GPIO_SD1_CD_N
+#define ACTIVE_LOW_MSC1_CD	1
+
+/* wifi on MSC2 */
+#define	GPIO_WIFI_PWR_EN	(32 * 5 + 0) /* GPF0 */
+#define GPIO_WIFI_PDn		(32 * 5 + 3) /* GPF3 */
+#define GPIO_WIFI_WAKEUP	(32 * 5 + 2) /* GPF2 */
+#define GPIO_WIFI_MODE		(32 * 5 + 1) /* GPF1 */
+
+#define GPIO_SD2_VCC_EN_N	GPIO_WIFI_PWR_EN
+#define GPIO_SD2_CD_N		GPIO_WIFI_MODE
+#define MSC2_HOTPLUG_PIN	GPIO_SD2_CD_N
+#define ACTIVE_LOW_MSC2_CD	1
+
+#define __msc1_enable_power()				\
+	do {						\
+		__gpio_clear_pin(GPIO_SD1_VCC_EN_N);	\
+	} while (0)
+
+#define __msc1_disable_power()				\
+	do {						\
+		__gpio_set_pin(GPIO_SD1_VCC_EN_N);	\
+	} while (0)
+
+#define __msc1_enable_power()				\
+	do {						\
+		__gpio_clear_pin(GPIO_SD1_VCC_EN_N);	\
+	} while (0)
+
+#define __msc1_disable_power()				\
+	do {						\
+		__gpio_set_pin(GPIO_SD1_VCC_EN_N);	\
+	} while (0)
+
+
+
+
+
+
+
+
+#define GPIO_DISP_OFF_N		(32 * 5 + 6) /* GPF6 */ //???
+
+
+
+
+#define GPIO_USB_DETE		(32 * 4 + 19) /* GPE19 */
+
+#define GPIO_LCD_PWM		(32 * 4 + 1) /* GPE01 */
+#define GPIO_LCD_VCC_EN_N       (32 * 1 + 31) /* GPB31 */
+
+#define GPIO_BOOT_SEL0		(32 * 3 + 17) /* GPD17 */
+#define GPIO_BOOT_SEL1		(32 * 3 + 18) /* GPD18 */
+#define GPIO_BOOT_SEL2		(32 * 3 + 19) /* GPD19 */
+
+/* Ethernet: WE#, RD#, CS5# */
+#define GPIO_NET_INT		(32 * 5 + 5)  /* GPF5 */
+
+#define GPIO_GSM_RI             (32 * 3 + 8) /* GPD08, waking cpu from sleep when a call comes in. */
+#define GPIO_GSM_RI_ACK         (32 * 0 + 29) /* GPA29, notify baseband not to send data to cpu when cpu is sleeping. */
+#define GPIO_GSM_WAKE           (32 * 1 + 27) /* GPB27 */
+#define GPIO_GSM_WAKE_ACK       (32 * 1 + 30) /* GPB30 */
+
+#define GPIO_POWER_ON           (32 * 0 + 30)  /* GPA30 */
+
+/*====================================================================
+ * GPIO KEYS and ADKEYS (GPIO_WAKEUP used for end call)
+ */
+#define GPIO_HOME		(32 * 2 + 29) // SW3-GPC29
+#define GPIO_MENU		(32 * 3 + 19) // SW6-boot_sel2-GPD19
+#define GPIO_CALL		(32 * 2 + 31) // SW1-GPC31
+#define GPIO_BACK		(32 * 3 + 27) // SW4-GPD27
+#define GPIO_ENDCALL    (32 * 0 + 30) // WAKEUP-GPA30
+#define GPIO_VOLUMEDOWN (32 * 3 + 18) // SW7-boot_sel1-GPD18
+#define GPIO_VOLUMEUP   (32 * 3 + 17) // SW8-boot_sel0-GPD17
+
+#define GPIO_ADKEY_INT	(32 * 4 + 8)  // GPE8
+
+/*====================================================================
+ *  ADKEYS LEVEL
+ */
+#define DPAD_LEFT_LEVEL		186 	//0.15V, 186=0.15/3.3*4096
+#define DPAD_DOWN_LEVEL		2482    //2.0V
+#define DPAD_UP_LEVEL		1985    //1.6V
+#define DPAD_CENTER_LEVEL	1489    //1.2V
+#define DPAD_RIGHT_LEVEL	868     //0.7V
+
+
+#define GPIO_TS_I2C_INT         (32 * 1 + 20)   //GPB20
+#define GPIO_TS_I2C_IRQ         (IRQ_GPIO_0 + GPIO_TS_I2C_INT)
+
+/*======================================================================
+ * Analog input for VBAT is the battery voltage divided by CFG_PBAT_DIV.
+ */
+//#define CFG_PBAT_DIV            4
+
+/*
+ * M-T4D touchscreen
+ */
+//#define LCD_INT		(32*2+20)	/* WAIT_N GPC20 interrupt pin */
+//#define IOSWITCH	(32*5+23)	/* GPF23 */
+
+
+/*======================================================================
+ * MMC/SD
+ */
+#define MSC0_WP_PIN		GPIO_SD0_WP_N
+#define MSC0_HOTPLUG_PIN	GPIO_SD0_CD_N
+#define MSC0_HOTPLUG_IRQ	(IRQ_GPIO_0 + GPIO_SD0_CD_N)
+
+#define MSC1_WP_PIN		GPIO_SD1_WP_N
+#define MSC1_HOTPLUG_PIN	GPIO_SD1_CD_N
+#define MSC1_HOTPLUG_IRQ	(IRQ_GPIO_0 + GPIO_SD1_CD_N)
+
+/*======================================================================
+ * LCD backlight
+ */
+#define LCD_PWM_CHN 1   /* pwm channel */
+#define LCD_PWM_FULL 256
+#define PWM_BACKLIGHT_CHIP	0	/*0: digital pusle; 1: PWM*/
+#define LCD_DEFAULT_BACKLIGHT		80
+#define LCD_MAX_BACKLIGHT		100
+#define LCD_MIN_BACKLIGHT		1
+
+#if 1
+#if PWM_BACKLIGHT_CHIP
+
+#define __lcd_init_backlight(n)					\
+do {    							\
+	__lcd_set_backlight_level(n);				\
+} while (0)
+
+/* 100 level: 0,1,...,100 */
+#define __lcd_set_backlight_level(n)				\
+do {								\
+	__gpio_as_pwm(1);                               \
+	__tcu_disable_pwm_output(LCD_PWM_CHN);			\
+	__tcu_stop_counter(LCD_PWM_CHN);			\
+	__tcu_init_pwm_output_high(LCD_PWM_CHN);		\
+	__tcu_set_pwm_output_shutdown_abrupt(LCD_PWM_CHN);	\
+	__tcu_select_clk_div1(LCD_PWM_CHN);			\
+	__tcu_mask_full_match_irq(LCD_PWM_CHN);			\
+	__tcu_mask_half_match_irq(LCD_PWM_CHN);			\
+	__tcu_clear_counter_to_zero(LCD_PWM_CHN);		\
+	__tcu_set_full_data(LCD_PWM_CHN, JZ_EXTAL / 30000);	\
+	__tcu_set_half_data(LCD_PWM_CHN, JZ_EXTAL / 30000 * n / LCD_PWM_FULL); \
+	__tcu_enable_pwm_output(LCD_PWM_CHN);			\
+	__tcu_select_extalclk(LCD_PWM_CHN);			\
+	__tcu_start_counter(LCD_PWM_CHN);			\
+} while (0)
+
+#define __lcd_close_backlight()					\
+do {								\
+	__gpio_as_output(GPIO_LCD_PWM);				\
+	__gpio_clear_pin(GPIO_LCD_PWM);				\
+} while (0)
+
+#else	/* PWM_BACKLIGHT_CHIP */
+
+#define __send_low_pulse(n)					\
+do {								\
+	unsigned int i;						\
+	for (i = n; i > 0; i--)	{				\
+		__gpio_clear_pin(GPIO_LCD_PWM);			\
+		udelay(1);					\
+		__gpio_set_pin(GPIO_LCD_PWM);			\
+		udelay(3);					\
+	}							\
+} while (0)
+
+#define MAX_BRIGHTNESS_STEP	16				/* RT9365 supports 16 brightness step */
+#define CONVERT_FACTOR		(256/MAX_BRIGHTNESS_STEP)	/* System support 256 brightness step */
+
+#define __lcd_init_backlight(n)					\
+do {								\
+	unsigned int tmp = (n)/CONVERT_FACTOR + 1;		\
+	__gpio_as_output(GPIO_LCD_PWM);				\
+	__gpio_set_pin(GPIO_LCD_PWM);				\
+	udelay(30);						\
+	__send_low_pulse(MAX_BRIGHTNESS_STEP-tmp);		\
+} while (0)
+
+#define __lcd_set_backlight_level(n)					\
+do {									\
+	unsigned int last = lcd_backlight_level / CONVERT_FACTOR + 1;	\
+	unsigned int tmp = (n) / CONVERT_FACTOR + 1;			\
+	if (tmp <= last) {						\
+		__send_low_pulse(last-tmp);				\
+	} else {							\
+		__send_low_pulse(last + MAX_BRIGHTNESS_STEP - tmp);	\
+	}								\
+	udelay(30);							\
+} while (0)
+
+#define __lcd_close_backlight()					\
+do {								\
+	__gpio_as_output(GPIO_LCD_PWM); 			\
+	__gpio_clear_pin(GPIO_LCD_PWM); 			\
+} while (0)
+
+#endif	/*PWM_BACKLIGHT_CHIP*/
+#endif  // if 0
+
+/*
+ * The key interrupt pin is low voltage or fall edge acitve
+ */
+#define ACTIVE_LOW_HOME		1
+#define ACTIVE_LOW_MENU		1
+#define ACTIVE_LOW_BACK		1
+#define ACTIVE_LOW_CALL		1
+#define ACTIVE_LOW_ENDCALL  1
+#define ACTIVE_LOW_VOLUMEDOWN   1
+#define ACTIVE_LOW_VOLUMEUP     1
+#define ACTIVE_LOW_ADKEY	1
+#define ACTIVE_LOW_WAKE_UP 	1
+
+/* mplayer keys */
+#define GPIO_MP_VOLUMEUP	(32 * 2 + 29) // SW3-GPC29
+#define GPIO_MP_VOLUMEDOWN	(32 * 2 + 31) // SW1-GPC31
+#define GPIO_MP_MUTE		(32 * 3 + 19) // SW6-boot_sel2-GPD19
+#define GPIO_MP_PAUSE		(32 * 3 + 27) // SW4-GPD27
+#define GPIO_MP_PLAY		(32 * 0 + 30) // SW9-WAKEUP-GPA30
+#define GPIO_MP_REWIND		(32 * 3 + 18) // SW7-boot_sel1-GPD18
+#define GPIO_MP_FORWARD		(32 * 3 + 17) // SW8-boot_sel0-GPD17
+
+#define ACTIVE_LOW_MUTE		1
+#define ACTIVE_LOW_PUASE	1
+#define ACTIVE_LOW_PLAY		1
+#define ACTIVE_LOW_REWIND	1
+#define ACTIVE_LOW_FORWARD	1
+
+
+#define GPIO_SW3	(32 * 2 + 29) // SW3-GPC29
+#define GPIO_SW1	(32 * 2 + 31) // SW1-GPC31
+#define GPIO_SW6	(32 * 3 + 19) // SW6-boot_sel2-GPD19
+#define GPIO_SW4	(32 * 3 + 27) // SW4-GPD27
+#define GPIO_SW9	(32 * 0 + 30) // SW9-WAKEUP-GPA30
+#define GPIO_SW7	(32 * 3 + 18) // SW7-boot_sel1-GPD18
+#define GPIO_SW8	(32 * 3 + 17) // SW8-boot_sel0-GPD17
+
+#define ACTIVE_LOW_SW3		1
+#define ACTIVE_LOW_SW1		1
+#define ACTIVE_LOW_SW6		1
+#define ACTIVE_LOW_SW4		1
+#define ACTIVE_LOW_SW9		1
+#define ACTIVE_LOW_SW7   	1
+#define ACTIVE_LOW_SW8     	1
+
+#define JZ_EARLY_UART_BASE UART1_BASE
+
+#endif /* __ASM_JZ4760_HTB80_H__ */
diff --git a/arch/mips/include/asm/mach-jz4760/board-lepus.h b/arch/mips/include/asm/mach-jz4760/board-lepus.h
index ca2565605d8..bc3e41aed58 100644
--- a/arch/mips/include/asm/mach-jz4760/board-lepus.h
+++ b/arch/mips/include/asm/mach-jz4760/board-lepus.h
@@ -285,4 +285,6 @@ do {								\
 #define ACTIVE_LOW_SW7   	1
 #define ACTIVE_LOW_SW8     	1
 
+#define JZ_EARLY_UART_BASE UART1_BASE
+
 #endif /* __ASM_JZ4760_LEPUS_H__ */
diff --git a/arch/mips/include/asm/mach-jz4760/dma.h b/arch/mips/include/asm/mach-jz4760/dma.h
index 236c90fa68d..e582a7b5cd2 100644
--- a/arch/mips/include/asm/mach-jz4760/dma.h
+++ b/arch/mips/include/asm/mach-jz4760/dma.h
@@ -74,17 +74,24 @@ enum {
 	DMA_ID_SSI0_RX,		/* SSI0 receive-fifo-empty request */
 	DMA_ID_AIC_TX,		/* AIC transmit-fifo-full request */
 	DMA_ID_AIC_RX,		/* AIC receive-fifo-empty request */
-	DMA_ID_MSC0_TX,		/* MSC0 transmit-fifo-full request */
-	DMA_ID_MSC0_RX,		/* MSC0 receive-fifo-empty request */
+	DMA_ID_MSC0,
+	DMA_ID_MSC0_TX,	      /* for compitable with SD8686 */
+	DMA_ID_MSC0_RX,	      /* for compitable with SD8686 */
 	DMA_ID_TCU_OVERFLOW,	/* TCU channel n overflow interrupt */
 	DMA_ID_SADC,		/* SADC transfer request */
-	DMA_ID_MSC1_TX,		/* MSC1 transmit-fifo-full request */
-	DMA_ID_MSC1_RX,		/* MSC1 receive-fifo-empty request */
+	DMA_ID_MSC1,
+	DMA_ID_MSC1_TX,	      /* for compitable with SD8686 */
+	DMA_ID_MSC1_RX,	      /* for compitable with SD8686 */
+	DMA_ID_MSC2,
+	DMA_ID_MSC2_TX,	      /* for compitable with SD8686 */
+	DMA_ID_MSC2_RX,	      /* for compitable with SD8686 */
 	DMA_ID_SSI1_TX,		/* SSI1 transmit-fifo-full request */
 	DMA_ID_SSI1_RX,		/* SSI1 receive-fifo-empty request */
 	DMA_ID_PCM_TX,		/* PM transmit-fifo-full request */
 	DMA_ID_PCM_RX,		/* PM receive-fifo-empty request */
 	DMA_ID_RAW_SET,
+	DMA_ID_AX88796C_RX,
+	DMA_ID_AX88796C_TX,
 	DMA_ID_MAX
 };
 
diff --git a/arch/mips/include/asm/mach-jz4760/jz4760.h b/arch/mips/include/asm/mach-jz4760/jz4760.h
index 5c12b81c788..5ac79a258e0 100644
--- a/arch/mips/include/asm/mach-jz4760/jz4760.h
+++ b/arch/mips/include/asm/mach-jz4760/jz4760.h
@@ -53,6 +53,7 @@
 
 #include <asm/mach-jz4760/dma.h>
 #include <asm/mach-jz4760/misc.h>
+#include <asm/mach-jz4760/platform.h>
 
 /*------------------------------------------------------------------
  * Platform definitions
@@ -80,6 +81,11 @@
 #include <asm/mach-jz4760/board-altair.h>
 #endif
 
+#ifdef CONFIG_JZ4760_HTB80
+#include <asm/mach-jz4760/jz4760epdc.h>
+#include <asm/mach-jz4760/board-htb80.h>
+#endif
+
 /* Add other platform definition here ... */
 
 
@@ -89,5 +95,6 @@
 
 //#include <asm/mach-jz4760/clock.h>
 #include <asm/mach-jz4760/serial.h>
+#include <asm/mach-jz4760/spi.h>
 
 #endif /* __ASM_JZ4760_H__ */
diff --git a/arch/mips/include/asm/mach-jz4760/jz4760cpm.h b/arch/mips/include/asm/mach-jz4760/jz4760cpm.h
index 54b8ba2b744..f0e36149671 100644
--- a/arch/mips/include/asm/mach-jz4760/jz4760cpm.h
+++ b/arch/mips/include/asm/mach-jz4760/jz4760cpm.h
@@ -1,646 +1,675 @@
-/*

- * jz4760cpm.h

- * JZ4760 CPM register definition

- * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

- *

- * Author: whxu@ingenic.cn

- */

-

-#ifndef __JZ4760CPM_H__

-#define __JZ4760CPM_H__

-

-#ifndef JZ_EXTAL

-#define JZ_EXTAL		12000000   /* 3.6864 MHz */

-#endif

-#ifndef JZ_EXTAL2

-#define JZ_EXTAL2		32768     /* 32.768 KHz */

-#endif

-

-/*

- * Clock reset and power controller module(CPM) address definition

- */

-#define	CPM_BASE	0xb0000000

-

-

-/*

- * CPM registers offset address definition

- */

-#define CPM_CPCCR_OFFSET        (0x00)  /* rw, 32, 0x01011100 */

-#define CPM_LCR_OFFSET          (0x04)  /* rw, 32, 0x000000f8 */

-#define CPM_RSR_OFFSET          (0x08)  /* rw, 32, 0x???????? */

-#define CPM_CPPCR0_OFFSET       (0x10)  /* rw, 32, 0x28080011 */

-#define CPM_CPPSR_OFFSET        (0x14)  /* rw, 32, 0x80000000 */

-#define CPM_CLKGR0_OFFSET       (0x20)  /* rw, 32, 0x3fffffe0 */

-#define CPM_OPCR_OFFSET         (0x24)  /* rw, 32, 0x00001570 */

-#define CPM_CLKGR1_OFFSET       (0x28)  /* rw, 32, 0x0000017f */

-#define CPM_CPPCR1_OFFSET       (0x30)  /* rw, 32, 0x28080002 */

-#define CPM_CPSPR_OFFSET        (0x34)  /* rw, 32, 0x???????? */

-#define CPM_CPSPPR_OFFSET       (0x38)  /* rw, 32, 0x0000a5a5 */

-#define CPM_USBPCR_OFFSET       (0x3c)  /* rw, 32, 0x42992198 */

-#define CPM_USBRDT_OFFSET       (0x40)  /* rw, 32, 0x00000096 */

-#define CPM_USBVBFIL_OFFSET     (0x44)  /* rw, 32, 0x00000080 */

-#define CPM_USBCDR_OFFSET       (0x50)  /* rw, 32, 0x00000000 */

-#define CPM_I2SCDR_OFFSET       (0x60)  /* rw, 32, 0x00000000 */

-#define CPM_LPCDR_OFFSET        (0x64)  /* rw, 32, 0x00000000 */

-#define CPM_MSCCDR_OFFSET       (0x68)  /* rw, 32, 0x00000000 */

-#define CPM_UHCCDR_OFFSET       (0x6c)  /* rw, 32, 0x00000000 */

-#define CPM_SSICDR_OFFSET       (0x74)  /* rw, 32, 0x00000000 */

-#define CPM_CIMCDR_OFFSET       (0x7c)  /* rw, 32, 0x00000000 */

-#define CPM_GPSCDR_OFFSET       (0x80)  /* rw, 32, 0x00000000 */

-#define CPM_PCMCDR_OFFSET       (0x84)  /* rw, 32, 0x00000000 */

-#define CPM_GPUCDR_OFFSET       (0x88)  /* rw, 32, 0x00000000 */

-#define CPM_PSWC0ST_OFFSET      (0x90)  /* rw, 32, 0x00000000 */

-#define CPM_PSWC1ST_OFFSET      (0x94)  /* rw, 32, 0x00000000 */

-#define CPM_PSWC2ST_OFFSET      (0x98)  /* rw, 32, 0x00000000 */

-#define CPM_PSWC3ST_OFFSET      (0x9c)  /* rw, 32, 0x00000000 */

-

-

-/*

- * CPM registers address definition

- */

-#define CPM_CPCCR        (CPM_BASE + CPM_CPCCR_OFFSET)

-#define CPM_LCR          (CPM_BASE + CPM_LCR_OFFSET)

-#define CPM_RSR          (CPM_BASE + CPM_RSR_OFFSET)

-#define CPM_CPPCR0       (CPM_BASE + CPM_CPPCR0_OFFSET)

-#define CPM_CPPSR        (CPM_BASE + CPM_CPPSR_OFFSET)

-#define CPM_CLKGR0       (CPM_BASE + CPM_CLKGR0_OFFSET)

-#define CPM_OPCR         (CPM_BASE + CPM_OPCR_OFFSET)

-#define CPM_CLKGR1       (CPM_BASE + CPM_CLKGR1_OFFSET)

-#define CPM_CPPCR1       (CPM_BASE + CPM_CPPCR1_OFFSET)

-#define CPM_CPSPR        (CPM_BASE + CPM_CPSPR_OFFSET)

-#define CPM_CPSPPR       (CPM_BASE + CPM_CPSPPR_OFFSET)

-#define CPM_USBPCR       (CPM_BASE + CPM_USBPCR_OFFSET)

-#define CPM_USBRDT       (CPM_BASE + CPM_USBRDT_OFFSET)

-#define CPM_USBVBFIL     (CPM_BASE + CPM_USBVBFIL_OFFSET)

-#define CPM_USBCDR       (CPM_BASE + CPM_USBCDR_OFFSET)

-#define CPM_I2SCDR       (CPM_BASE + CPM_I2SCDR_OFFSET)

-#define CPM_LPCDR        (CPM_BASE + CPM_LPCDR_OFFSET)

-#define CPM_MSCCDR       (CPM_BASE + CPM_MSCCDR_OFFSET)

-#define CPM_UHCCDR       (CPM_BASE + CPM_UHCCDR_OFFSET)

-#define CPM_SSICDR       (CPM_BASE + CPM_SSICDR_OFFSET)

-#define CPM_CIMCDR       (CPM_BASE + CPM_CIMCDR_OFFSET)

-#define CPM_GPSCDR       (CPM_BASE + CPM_GPSCDR_OFFSET)

-#define CPM_PCMCDR       (CPM_BASE + CPM_PCMCDR_OFFSET)

-#define CPM_GPUCDR       (CPM_BASE + CPM_GPUCDR_OFFSET)

-#define CPM_PSWC0ST      (CPM_BASE + CPM_PSWC0ST_OFFSET)

-#define CPM_PSWC1ST      (CPM_BASE + CPM_PSWC1ST_OFFSET)

-#define CPM_PSWC2ST      (CPM_BASE + CPM_PSWC2ST_OFFSET)

-#define CPM_PSWC3ST      (CPM_BASE + CPM_PSWC3ST_OFFSET)

-

-

-/*

- * CPM registers common define

- */

-

-/* Clock control register(CPCCR) */

-#define CPCCR_ECS               BIT31

-#define CPCCR_MEM               BIT30

-#define CPCCR_CE                BIT22

-#define CPCCR_PCS               BIT21

-

-#define CPCCR_SDIV_LSB          24

-#define CPCCR_SDIV_MASK         BITS_H2L(27, CPCCR_SDIV_LSB)

-

-#define CPCCR_H2DIV_LSB         16

-#define CPCCR_H2DIV_MASK        BITS_H2L(19, CPCCR_H2DIV_LSB)

-

-#define CPCCR_MDIV_LSB          12

-#define CPCCR_MDIV_MASK         BITS_H2L(15, CPCCR_MDIV_LSB)

-

-#define CPCCR_PDIV_LSB		8

-#define CPCCR_PDIV_MASK         BITS_H2L(11, CPCCR_PDIV_LSB)

-

-#define CPCCR_HDIV_LSB		4

-#define CPCCR_HDIV_MASK         BITS_H2L(7, CPCCR_HDIV_LSB)

-

-#define CPCCR_CDIV_LSB		0

-#define CPCCR_CDIV_MASK         BITS_H2L(3, CPCCR_CDIV_LSB)

-

-/* Low power control register(LCR) */

-#define LCR_PDAHB1              BIT30

-#define LCR_VBATIR              BIT29

-#define LCR_PDGPS               BIT28

-#define LCR_PDAHB1S             BIT26

-#define LCR_PDGPSS              BIT24

-#define LCR_DOZE                BIT2

-

-#define LCR_PST_LSB             8

-#define LCR_PST_MASK            BITS_H2L(19, LCR_PST_LSB)

-

-#define LCR_DUTY_LSB            3

-#define LCR_DUTY_MASK           BITS_H2L(7, LCR_DUTY_LSB)

-

-#define LCR_LPM_LSB             0

-#define LCR_LPM_MASK            BITS_H2L(1, LCR_LPM_LSB)

-#define LCR_LPM_IDLE            (0x0 << LCR_LPM_LSB)

-#define LCR_LPM_SLEEP           (0x1 << LCR_LPM_LSB)

-

-/* Reset status register(RSR) */

-#define RSR_P0R         BIT2

-#define RSR_WR          BIT1

-#define RSR_PR          BIT0

-

-/* PLL control register 0(CPPCR0) */

-#define CPPCR0_LOCK             BIT15   /* LOCK0 bit */

-#define CPPCR0_ENLOCK           BIT14

-#define CPPCR0_PLLS             BIT10

-#define CPPCR0_PLLBP            BIT9

-#define CPPCR0_PLLEN            BIT8

-

-#define CPPCR0_PLLM_LSB         24

-#define CPPCR0_PLLM_MASK        BITS_H2L(30, CPPCR0_PLLM_LSB)

-

-#define CPPCR0_PLLN_LSB         18

-#define CPPCR0_PLLN_MASK        BITS_H2L(21, CPPCR0_PLLN_LSB)

-

-#define CPPCR0_PLLOD_LSB        16

-#define CPPCR0_PLLOD_MASK       BITS_H2L(17, CPPCR0_PLLOD_LSB)

-

-#define CPPCR0_PLLST_LSB        0

-#define CPPCR0_PLLST_MASK       BITS_H2L(7, CPPCR0_PLLST_LSB)

-

-/* PLL switch and status register(CPPSR) */

-#define CPPSR_PLLOFF            BIT31

-#define CPPSR_PLLBP             BIT30

-#define CPPSR_PLLON             BIT29

-#define CPPSR_PS                BIT28

-#define CPPSR_FS                BIT27

-#define CPPSR_CS                BIT26

-#define CPPSR_SM                BIT2

-#define CPPSR_PM                BIT1

-#define CPPSR_FM                BIT0

-

-/* Clock gate register 0(CGR0) */

-#define CLKGR0_EMC              BIT31

-#define CLKGR0_DDR              BIT30

-#define CLKGR0_IPU              BIT29

-#define CLKGR0_LCD              BIT28

-#define CLKGR0_TVE              BIT27

-#define CLKGR0_CIM              BIT26

-#define CLKGR0_MDMA             BIT25

-#define CLKGR0_UHC              BIT24

-#define CLKGR0_MAC              BIT23

-#define CLKGR0_GPS              BIT22

-#define CLKGR0_DMAC             BIT21

-#define CLKGR0_SSI2             BIT20

-#define CLKGR0_SSI1             BIT19

-#define CLKGR0_UART3            BIT18

-#define CLKGR0_UART2            BIT17

-#define CLKGR0_UART1            BIT16

-#define CLKGR0_UART0            BIT15

-#define CLKGR0_SADC             BIT14

-#define CLKGR0_KBC              BIT13

-#define CLKGR0_MSC2             BIT12

-#define CLKGR0_MSC1             BIT11

-#define CLKGR0_OWI              BIT10

-#define CLKGR0_TSSI             BIT9

-#define CLKGR0_AIC              BIT8

-#define CLKGR0_SCC              BIT7

-#define CLKGR0_I2C1             BIT6

-#define CLKGR0_I2C0             BIT5

-#define CLKGR0_SSI0             BIT4

-#define CLKGR0_MSC0             BIT3

-#define CLKGR0_OTG              BIT2

-#define CLKGR0_BCH              BIT1

-#define CLKGR0_NEMC             BIT0

-

-/* Oscillator and power control register(OPCR) */

-#define OPCR_OTGPHY_ENABLE      BIT7    /* SPENDN bit */

-#define OPCR_GPSEN              BIT6

-#define OPCR_UHCPHY_DISABLE     BIT5    /* SPENDH bit */

-#define OPCR_O1SE               BIT4

-#define OPCR_PD                 BIT3

-#define OPCR_ERCS               BIT2

-

-#define OPCR_O1ST_LSB           8

-#define OPCR_O1ST_MASK          BITS_H2L(15, OPCR_O1ST_LSB)

-

-/* Clock gate register 1(CGR1) */

-#define CLKGR1_GPU              BIT9

-#define CLKGR1_PCM              BIT8

-#define CLKGR1_AHB1             BIT7

-#define CLKGR1_CABAC            BIT6

-#define CLKGR1_SRAM             BIT5

-#define CLKGR1_DCT              BIT4

-#define CLKGR1_ME               BIT3

-#define CLKGR1_DBLK             BIT2

-#define CLKGR1_MC               BIT1

-#define CLKGR1_BDMA             BIT0

-

-/* PLL control register 1(CPPCR1) */

-#define CPPCR1_P1SCS            BIT15

-#define CPPCR1_PLL1EN           BIT7

-#define CPPCR1_PLL1S            BIT6

-#define CPPCR1_LOCK             BIT2    /* LOCK1 bit */

-#define CPPCR1_PLL1OFF          BIT1

-#define CPPCR1_PLL1ON           BIT0

-

-#define CPPCR1_PLL1M_LSB        24

-#define CPPCR1_PLL1M_MASK       BITS_H2L(30, CPPCR1_PLL1M_LSB)

-

-#define CPPCR1_PLL1N_LSB        18

-#define CPPCR1_PLL1N_MASK       BITS_H2L(21, CPPCR1_PLL1N_LSB)

-

-#define CPPCR1_PLL1OD_LSB       16

-#define CPPCR1_PLL1OD_MASK      BITS_H2L(17, CPPCR1_PLL1OD_LSB)

-

-#define CPPCR1_P1SDIV_LSB       9

-#define CPPCR1_P1SDIV_MASK      BITS_H2L(14, CPPCR1_P1SDIV_LSB)

-

-/* CPM scratch pad protected register(CPSPPR) */

-#define CPSPPR_CPSPR_WRITABLE   (0x00005a5a)

-

-/* OTG parameter control register(USBPCR) */

-#define USBPCR_USB_MODE         BIT31

-#define USBPCR_AVLD_REG         BIT30

-#define USBPCR_INCRM            BIT27   /* INCR_MASK bit */

-#define USBPCR_CLK12_EN         BIT26

-#define USBPCR_COMMONONN        BIT25

-#define USBPCR_VBUSVLDEXT       BIT24

-#define USBPCR_VBUSVLDEXTSEL    BIT23

-#define USBPCR_POR              BIT22

-#define USBPCR_SIDDQ            BIT21

-#define USBPCR_OTG_DISABLE      BIT20

-#define USBPCR_TXPREEMPHTUNE    BIT6

-

-#define USBPCR_IDPULLUP_LSB             28   /* IDPULLUP_MASK bit */

-#define USBPCR_IDPULLUP_MASK            BITS_H2L(29, USBPCR_USBPCR_IDPULLUP_LSB)

-

-#define USBPCR_COMPDISTUNE_LSB          17

-#define USBPCR_COMPDISTUNE_MASK         BITS_H2L(19, USBPCR_COMPDISTUNE_LSB)

-

-#define USBPCR_OTGTUNE_LSB              14

-#define USBPCR_OTGTUNE_MASK             BITS_H2L(16, USBPCR_OTGTUNE_LSB)

-

-#define USBPCR_SQRXTUNE_LSB             11

-#define USBPCR_SQRXTUNE_MASK            BITS_H2L(13, USBPCR_SQRXTUNE_LSB)

-

-#define USBPCR_TXFSLSTUNE_LSB           7

-#define USBPCR_TXFSLSTUNE_MASK          BITS_H2L(10, USBPCR_TXFSLSTUNE_LSB)

-

-#define USBPCR_TXRISETUNE_LSB           4

-#define USBPCR_TXRISETUNE_MASK          BITS_H2L(5, USBPCR_TXRISETUNE_LSB)

-

-#define USBPCR_TXVREFTUNE_LSB           0

-#define USBPCR_TXVREFTUNE_MASK          BITS_H2L(3, USBPCR_TXVREFTUNE_LSB)

-

-/* OTG reset detect timer register(USBRDT) */

-#define USBRDT_VBFIL_LD_EN      BIT25

-#define USBRDT_IDDIG_EN         BIT24

-#define USBRDT_IDDIG_REG        BIT23

-

-#define USBRDT_USBRDT_LSB       0

-#define USBRDT_USBRDT_MASK      BITS_H2L(22, USBRDT_USBRDT_LSB)

-

-/* OTG PHY clock divider register(USBCDR) */

-#define USBCDR_UCS              BIT31

-#define USBCDR_UPCS             BIT30

-

-#define USBCDR_OTGDIV_LSB       0       /* USBCDR bit */

-#define USBCDR_OTGDIV_MASK      BITS_H2L(5, USBCDR_OTGDIV_LSB)

-

-/* I2S device clock divider register(I2SCDR) */

-#define I2SCDR_I2CS             BIT31

-#define I2SCDR_I2PCS            BIT30

-

-#define I2SCDR_I2SDIV_LSB       0       /* I2SCDR bit */

-#define I2SCDR_I2SDIV_MASK      BITS_H2L(8, I2SCDR_I2SDIV_LSB)

-

-/* LCD pix clock divider register(LPCDR) */

-#define LPCDR_LSCS              BIT31

-#define LPCDR_LTCS              BIT30

-#define LPCDR_LPCS              BIT29

-

-#define LPCDR_PIXDIV_LSB        0       /* LPCDR bit */

-#define LPCDR_PIXDIV_MASK       BITS_H2L(10, LPCDR_PIXDIV_LSB)

-

-/* MSC clock divider register(MSCCDR) */

-#define MSCCDR_MCS              BIT31

-

-#define MSCCDR_MSCDIV_LSB       0       /* MSCCDR bit */

-#define MSCCDR_MSCDIV_MASK      BITS_H2L(5, MSCCDR_MSCDIV_LSB)

-

-/* UHC device clock divider register(UHCCDR) */

-#define UHCCDR_UHPCS            BIT31

-

-#define UHCCDR_UHCDIV_LSB       0       /* UHCCDR bit */

-#define UHCCDR_UHCDIV_MASK      BITS_H2L(3, UHCCDR_UHCDIV_LSB)

-

-/* SSI clock divider register(SSICDR) */

-#define SSICDR_SCS              BIT31

-

-#define SSICDR_SSIDIV_LSB       0       /* SSICDR bit */

-#define SSICDR_SSIDIV_MASK      BITS_H2L(5, SSICDR_SSIDIV_LSB)

-

-/* CIM mclk clock divider register(CIMCDR) */

-#define CIMCDR_CIMDIV_LSB       0       /* CIMCDR bit */

-#define CIMCDR_CIMDIV_MASK      BITS_H2L(7, CIMCDR_CIMDIV_LSB)

-

-/* GPS clock divider register(GPSCDR) */

-#define GPSCDR_GPCS             BIT31

-

-#define GPSCDR_GPSDIV_LSB       0       /* GPSCDR bit */

-#define GSPCDR_GPSDIV_MASK      BITS_H2L(3, GPSCDR_GPSDIV_LSB)

-

-/* PCM device clock divider register(PCMCDR) */

-#define PCMCDR_PCMS             BIT31

-#define PCMCDR_PCMPCS           BIT30

-

-#define PCMCDR_PCMDIV_LSB       0       /* PCMCDR bit */

-#define PCMCDR_PCMDIV_MASK      BITS_H2L(8, PCMCDR_PCMDIV_LSB)

-

-/* GPU clock divider register */

-#define GPUCDR_GPCS             BIT31

-#define GPUCDR_GPUDIV_LSB       0       /* GPUCDR bit */

-#define GPUCDR_GPUDIV_MASK      BITS_H2L(2, GPUCDR_GPUDIV_LSB)

-

-

-#ifndef __MIPS_ASSEMBLER

-

-#define REG_CPM_CPCCR           REG32(CPM_CPCCR)

-#define REG_CPM_RSR             REG32(CPM_RSR)

-#define REG_CPM_CPPCR0          REG32(CPM_CPPCR0)

-#define REG_CPM_CPPSR           REG32(CPM_CPPSR)

-#define REG_CPM_CPPCR1          REG32(CPM_CPPCR1)

-#define REG_CPM_CPSPR           REG32(CPM_CPSPR)

-#define REG_CPM_CPSPPR          REG32(CPM_CPSPPR)

-#define REG_CPM_USBPCR          REG32(CPM_USBPCR)

-#define REG_CPM_USBRDT          REG32(CPM_USBRDT)

-#define REG_CPM_USBVBFIL        REG32(CPM_USBVBFIL)

-#define REG_CPM_USBCDR          REG32(CPM_USBCDR)

-#define REG_CPM_I2SCDR          REG32(CPM_I2SCDR)

-#define REG_CPM_LPCDR           REG32(CPM_LPCDR)

-#define REG_CPM_MSCCDR          REG32(CPM_MSCCDR)

-#define REG_CPM_UHCCDR          REG32(CPM_UHCCDR)

-#define REG_CPM_SSICDR          REG32(CPM_SSICDR)

-#define REG_CPM_CIMCDR          REG32(CPM_CIMCDR)

-#define REG_CPM_GPSCDR          REG32(CPM_GPSCDR)

-#define REG_CPM_PCMCDR          REG32(CPM_PCMCDR)

-#define REG_CPM_GPUCDR          REG32(CPM_GPUCDR)

-

-#define REG_CPM_PSWC0ST         REG32(CPM_PSWC0ST)

-#define REG_CPM_PSWC1ST         REG32(CPM_PSWC1ST)

-#define REG_CPM_PSWC2ST         REG32(CPM_PSWC2ST)

-#define REG_CPM_PSWC3ST         REG32(CPM_PSWC3ST)

-

-#define REG_CPM_LCR             REG32(CPM_LCR)

-#define REG_CPM_CLKGR0          REG32(CPM_CLKGR0)

-#define REG_CPM_OPCR            REG32(CPM_OPCR)

-#define REG_CPM_CLKGR1          REG32(CPM_CLKGR1)

-#define REG_CPM_CLKGR           REG32(CPM_CLKGR0)

-

-typedef enum {

-        CGM_NEMC = 0,

-        CGM_BCH  = 1,

-        CGM_OTG  = 2,

-        CGM_MSC0 = 3,

-        CGM_SSI0 = 4,

-        CGM_I2C0 = 5,

-        CGM_I2C1 = 6,

-        CGM_SCC  = 7,

-        CGM_AIC         = 8,

-        CGM_TSSI        = 9,

-        CGM_OWI         = 10,

-        CGM_MSC1        = 11,

-        CGM_MSC2        = 12,

-        CGM_KBC         = 13,

-        CGM_SADC        = 14,

-        CGM_UART0       = 15,

-        CGM_UART1 = 16,

-        CGM_UART2 = 17,

-        CGM_UART3 = 18,

-        CGM_SSI1  = 19,

-        CGM_SSI2  = 20,

-        CGM_DMAC  = 21,

-        CGM_GPS   = 22,

-        CGM_MAC   = 23,

-        CGM_UHC         = 24,

-        CGM_MDMA        = 25,

-        CGM_CIM         = 26,

-        CGM_TVE         = 27,

-        CGM_LCD         = 28,

-        CGM_IPU         = 29,

-        CGM_DDR         = 30,

-        CGM_EMC         = 31,

-        CGM_BDMA  = 32 + 0,

-        CGM_MC    = 32 + 1,

-        CGM_DBLK  = 32 + 2,

-        CGM_ME    = 32 + 3,

-        CGM_DCT   = 32 + 4,

-        CGM_SRAM  = 32 + 5,

-        CGM_CABAC = 32 + 6,

-        CGM_AHB1  = 32 + 7,

-        CGM_PCM         = 32 + 8,

-        CGM_GPU         = 32 + 9,

-        CGM_ALL_MODULE,

-} clock_gate_module;

-

-

-#define __CGU_CLOCK_BASE__      0x1000

-

-typedef enum {

-        /* Clock source is pll0 */

-        CGU_CCLK = __CGU_CLOCK_BASE__ + 0,

-        CGU_HCLK,

-        CGU_PCLK,

-        CGU_MCLK,

-        CGU_H2CLK,

-        CGU_SCLK,

-

-        /* Clock source is exclk, pll0 or pll0/2 */

-        CGU_MSCCLK,

-        CGU_SSICLK,

-

-        /* Clock source is pll0 or pll0/2 */

-        CGU_CIMCLK,

-

-        /* Clock source is exclk, pll0, pll0/2 or pll1 */

-        CGU_TVECLK,

-

-        /* Clock source is pll0 */

-        CGU_LPCLK,

-

-        /* Clock source is exclk, exclk/2, pll0, pll0/2 or pll1 */

-        CGU_I2SCLK,

-        CGU_PCMCLK,

-        CGU_OTGCLK,

-

-        /* Clock source is pll0, pll0/2 or pll1 */

-        CGU_UHCCLK,

-        CGU_GPSCLK,

-        CGU_GPUCLK,

-

-        /* Clock source is exclk or exclk/2 */

-        CGU_UARTCLK,

-        CGU_SADCCLK,

-

-        /* Clock source is exclk */

-        CGU_TCUCLK,

-

-	/* Clock source is external rtc clock */

-	CGU_RTCCLK,

-

-        CGU_CLOCK_MAX,

-} cgu_clock;

-

-/*

- * JZ4760 clocks structure

- */

-typedef struct {

-	unsigned int cclk;	/* CPU clock				*/

-	unsigned int hclk;	/* System bus clock: AHB0,AHB1		*/

-	unsigned int h1clk;	/* For compatible, the same as h1clk	*/

-	unsigned int h2clk;	/* System bus clock: AHB2		*/

-	unsigned int pclk;	/* Peripheral bus clock			*/

-	unsigned int mclk;	/* EMC or DDR controller clock		*/

-	unsigned int sclk;	/* NEMC controller clock		*/

-	unsigned int cko;	/* SDRAM or DDR clock			*/

-	unsigned int pixclk;	/* LCD pixel clock			*/

-	unsigned int tveclk;	/* TV encoder 27M  clock		*/

-	unsigned int cimmclk;	/* Clock output from CIM module		*/

-	unsigned int cimpclk;	/* Clock input to CIM module		*/

-	unsigned int gpuclk;	/* GPU clock				*/

-	unsigned int gpsclk;	/* GPS clock				*/

-	unsigned int i2sclk;	/* I2S codec clock			*/

-	unsigned int bitclk;	/* AC97 bit clock			*/

-	unsigned int pcmclk;	/* PCM clock				*/

-	unsigned int mscclk;	/* MSC clock				*/

-	unsigned int ssiclk;	/* SSI clock				*/

-	unsigned int tssiclk;	/* TSSI clock				*/

-	unsigned int otgclk;	/* USB OTG clock			*/

-	unsigned int uhcclk;	/* USB UHCI clock			*/

-	unsigned int extalclk;	/* EXTAL clock for

-				   UART,I2C,TCU,USB2.0-PHY,AUDIO CODEC	*/

-	unsigned int rtcclk;	/* RTC clock for CPM,INTC,RTC,TCU,WDT	*/

-} jz_clocks_t;

-

-void cpm_start_clock(clock_gate_module module_name);

-void cpm_stop_clock(clock_gate_module module_name);

-

-unsigned int cpm_set_clock(cgu_clock clock_name, unsigned int clock_hz);

-unsigned int cpm_get_clock(cgu_clock clock_name);

-unsigned int cpm_get_pllout(void);

-

-void cpm_uhc_phy(unsigned int en);

-

-/**************remove me if android's kernel support these operations********start*********  */

-#define __cpm_stop_lcd()	(REG_CPM_CLKGR0 |= CLKGR0_LCD)

-#define __cpm_start_lcd()	(REG_CPM_CLKGR0 &= ~CLKGR0_LCD)

-#define __cpm_set_pixdiv(v) \

-	(REG_CPM_LPCDR = (REG_CPM_LPCDR & ~LPCDR_PIXDIV_MASK) | ((v) << (LPCDR_PIXDIV_LSB)))

-

-#define __cpm_get_pixdiv() \

-	((REG_CPM_LPCDR & LPCDR_PIXDIV_MASK) >> LPCDR_PIXDIV_LSB)

-

-#define __cpm_select_pixclk_tve()	(REG_CPM_LPCDR |= LPCDR_LTCS)

-

-static __inline__ unsigned int __cpm_get_pllout2(void)

-{

-#if defined(CONFIG_FPGA)

-	return cpm_get_pllout();

-#else

-	if (REG_CPM_CPCCR & CPCCR_PCS)

-		return cpm_get_pllout();

-	else

-		return cpm_get_pllout()/2;

-#endif

-}

-

-static __inline__ unsigned int __cpm_get_pixclk(void)

-{

-	return __cpm_get_pllout2() / (__cpm_get_pixdiv() + 1);

-}

-

-/* EXTAL clock */

-static __inline__ unsigned int __cpm_get_extalclk0(void)

-{

-	return JZ_EXTAL;

-}

-

-/* EXTAL clock for UART,I2C,SSI,SADC,USB-PHY */

-static __inline__ unsigned int __cpm_get_extalclk(void)

-{

-#if defined(CONFIG_FPGA)

-	return __cpm_get_extalclk0() / CFG_DIV;

-#else

-	if (REG_CPM_CPCCR & CPCCR_ECS)

-		return __cpm_get_extalclk0() / 2;

-	else

-		return __cpm_get_extalclk0();

-#endif

-

-}

-

-/* RTC clock for CPM,INTC,RTC,TCU,WDT */

-static __inline__ unsigned int __cpm_get_rtcclk(void)

-{

-	return JZ_EXTAL2;

-}

-

-extern jz_clocks_t jz_clocks;

-

-#define __cpm_select_i2sclk_exclk()	(REG_CPM_I2SCDR &= ~I2SCDR_I2CS)

-#define __cpm_enable_pll_change()	(REG_CPM_CPCCR |= CPCCR_CE)

-

-#define __cpm_suspend_otg_phy()		(REG_CPM_OPCR &= ~OPCR_OTGPHY_ENABLE)

-#define __cpm_enable_otg_phy()		(REG_CPM_OPCR |=  OPCR_OTGPHY_ENABLE)

-

-#define __cpm_suspend_uhc_phy()		(REG_CPM_OPCR |= OPCR_UHCPHY_DISABLE)

-#define __cpm_enable_uhc_phy()		(REG_CPM_OPCR &= ~OPCR_UHCPHY_DISABLE)

-#define __cpm_suspend_gps()        (REG_CPM_OPCR &= ~OPCR_GPSEN)

-#define __cpm_disable_osc_in_sleep()	(REG_CPM_OPCR &= ~OPCR_O1SE)

-#define __cpm_select_rtcclk_rtc()	(REG_CPM_OPCR |= OPCR_ERCS)

-

-#define __cpm_get_pllm() \

-	((REG_CPM_CPPCR0 & CPPCR0_PLLM_MASK) >> CPPCR0_PLLM_LSB)

-#define __cpm_get_plln() \

-	((REG_CPM_CPPCR0 & CPPCR0_PLLN_MASK) >> CPPCR0_PLLN_LSB)

-#define __cpm_get_pllod() \

-	((REG_CPM_CPPCR0 & CPPCR0_PLLOD_MASK) >> CPPCR0_PLLOD_LSB)

-

-#define __cpm_get_pll1m() \

-	((REG_CPM_CPPCR1 & CPPCR1_PLL1M_MASK) >> CPPCR1_PLL1M_LSB)

-#define __cpm_get_pll1n() \

-	((REG_CPM_CPPCR1 & CPPCR1_PLL1N_MASK) >> CPPCR1_PLL1N_LSB)

-#define __cpm_get_pll1od() \

-	((REG_CPM_CPPCR1 & CPPCR1_PLL1OD_MASK) >> CPPCR1_PLL1OD_LSB)

-

-#define __cpm_get_cdiv() \

-	((REG_CPM_CPCCR & CPCCR_CDIV_MASK) >> CPCCR_CDIV_LSB)

-#define __cpm_get_hdiv() \

-	((REG_CPM_CPCCR & CPCCR_HDIV_MASK) >> CPCCR_HDIV_LSB)

-#define __cpm_get_h2div() \

-	((REG_CPM_CPCCR & CPCCR_H2DIV_MASK) >> CPCCR_H2DIV_LSB)

-#define __cpm_get_otgdiv() \

-	((REG_CPM_USBCDR & USBCDR_OTGDIV_MASK) >> USBCDR_OTGDIV_LSB)

-#define __cpm_get_pdiv() \

-	((REG_CPM_CPCCR & CPCCR_PDIV_MASK) >> CPCCR_PDIV_LSB)

-#define __cpm_get_mdiv() \

-	((REG_CPM_CPCCR & CPCCR_MDIV_MASK) >> CPCCR_MDIV_LSB)

-#define __cpm_get_sdiv() \

-	((REG_CPM_CPCCR & CPCCR_SDIV_MASK) >> CPCCR_SDIV_LSB)

-#define __cpm_get_i2sdiv() \

-	((REG_CPM_I2SCDR & I2SCDR_I2SDIV_MASK) >> I2SCDR_I2SDIV_LSB)

-#define __cpm_get_pixdiv() \

-	((REG_CPM_LPCDR & LPCDR_PIXDIV_MASK) >> LPCDR_PIXDIV_LSB)

-#define __cpm_get_mscdiv() \

-	((REG_CPM_MSCCDR & MSCCDR_MSCDIV_MASK) >> MSCCDR_MSCDIV_LSB)

-

-/*

-#define __cpm_get_mscdiv(n) \

-	((REG_CPM_MSCCDR(n) & MSCCDR_MSCDIV_MASK) >> MSCCDR_MSCDIV_LSB)

-*/

-#define __cpm_get_ssidiv() \

-	((REG_CPM_SSICCDR & SSICDR_SSICDIV_MASK) >> SSICDR_SSIDIV_LSB)

-#define __cpm_get_pcmdiv() \

-	((REG_CPM_PCMCDR & PCMCDR_PCMCD_MASK) >> PCMCDR_PCMCD_LSB)

-#define __cpm_get_pll1div() \

-	((REG_CPM_CPPCR1 & CPCCR1_P1SDIV_MASK) >> CPCCR1_P1SDIV_LSB)

-

-/**************remove me if android's kernel support these operations********end*********  */

-

-extern int jz_pm_init(void);

-

-#endif /* __MIPS_ASSEMBLER */

-

-#endif /* __JZ4760CPM_H__ */

+/*
+ * jz4760cpm.h
+ * JZ4760 CPM register definition
+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.
+ *
+ * Author: whxu@ingenic.cn
+ */
+
+#ifndef __JZ4760CPM_H__
+#define __JZ4760CPM_H__
+
+#ifndef JZ_EXTAL
+#define JZ_EXTAL		12000000   /* 3.6864 MHz */
+#endif
+#ifndef JZ_EXTAL2
+#define JZ_EXTAL2		32768     /* 32.768 KHz */
+#endif
+
+/*
+ * Clock reset and power controller module(CPM) address definition
+ */
+#define	CPM_BASE	0xb0000000
+
+
+/*
+ * CPM registers offset address definition
+ */
+#define CPM_CPCCR_OFFSET        (0x00)  /* rw, 32, 0x01011100 */
+#define CPM_LCR_OFFSET          (0x04)  /* rw, 32, 0x000000f8 */
+#define CPM_RSR_OFFSET          (0x08)  /* rw, 32, 0x???????? */
+#define CPM_CPPCR0_OFFSET       (0x10)  /* rw, 32, 0x28080011 */
+#define CPM_CPPSR_OFFSET        (0x14)  /* rw, 32, 0x80000000 */
+#define CPM_CLKGR0_OFFSET       (0x20)  /* rw, 32, 0x3fffffe0 */
+#define CPM_OPCR_OFFSET         (0x24)  /* rw, 32, 0x00001570 */
+#define CPM_CLKGR1_OFFSET       (0x28)  /* rw, 32, 0x0000017f */
+#define CPM_CPPCR1_OFFSET       (0x30)  /* rw, 32, 0x28080002 */
+#define CPM_CPSPR_OFFSET        (0x34)  /* rw, 32, 0x???????? */
+#define CPM_CPSPPR_OFFSET       (0x38)  /* rw, 32, 0x0000a5a5 */
+#define CPM_USBPCR_OFFSET       (0x3c)  /* rw, 32, 0x42992198 */
+#define CPM_USBRDT_OFFSET       (0x40)  /* rw, 32, 0x00000096 */
+#define CPM_USBVBFIL_OFFSET     (0x44)  /* rw, 32, 0x00000080 */
+#define CPM_USBCDR_OFFSET       (0x50)  /* rw, 32, 0x00000000 */
+#define CPM_I2SCDR_OFFSET       (0x60)  /* rw, 32, 0x00000000 */
+#define CPM_LPCDR_OFFSET        (0x64)  /* rw, 32, 0x00000000 */
+#define CPM_MSCCDR_OFFSET       (0x68)  /* rw, 32, 0x00000000 */
+#define CPM_UHCCDR_OFFSET       (0x6c)  /* rw, 32, 0x00000000 */
+#define CPM_SSICDR_OFFSET       (0x74)  /* rw, 32, 0x00000000 */
+#define CPM_CIMCDR_OFFSET       (0x7c)  /* rw, 32, 0x00000000 */
+#define CPM_GPSCDR_OFFSET       (0x80)  /* rw, 32, 0x00000000 */
+#define CPM_PCMCDR_OFFSET       (0x84)  /* rw, 32, 0x00000000 */
+#define CPM_GPUCDR_OFFSET       (0x88)  /* rw, 32, 0x00000000 */
+#define CPM_PSWC0ST_OFFSET      (0x90)  /* rw, 32, 0x00000000 */
+#define CPM_PSWC1ST_OFFSET      (0x94)  /* rw, 32, 0x00000000 */
+#define CPM_PSWC2ST_OFFSET      (0x98)  /* rw, 32, 0x00000000 */
+#define CPM_PSWC3ST_OFFSET      (0x9c)  /* rw, 32, 0x00000000 */
+
+
+/*
+ * CPM registers address definition
+ */
+#define CPM_CPCCR        (CPM_BASE + CPM_CPCCR_OFFSET)
+#define CPM_LCR          (CPM_BASE + CPM_LCR_OFFSET)
+#define CPM_RSR          (CPM_BASE + CPM_RSR_OFFSET)
+#define CPM_CPPCR0       (CPM_BASE + CPM_CPPCR0_OFFSET)
+#define CPM_CPPSR        (CPM_BASE + CPM_CPPSR_OFFSET)
+#define CPM_CLKGR0       (CPM_BASE + CPM_CLKGR0_OFFSET)
+#define CPM_OPCR         (CPM_BASE + CPM_OPCR_OFFSET)
+#define CPM_CLKGR1       (CPM_BASE + CPM_CLKGR1_OFFSET)
+#define CPM_CPPCR1       (CPM_BASE + CPM_CPPCR1_OFFSET)
+#define CPM_CPSPR        (CPM_BASE + CPM_CPSPR_OFFSET)
+#define CPM_CPSPPR       (CPM_BASE + CPM_CPSPPR_OFFSET)
+#define CPM_USBPCR       (CPM_BASE + CPM_USBPCR_OFFSET)
+#define CPM_USBRDT       (CPM_BASE + CPM_USBRDT_OFFSET)
+#define CPM_USBVBFIL     (CPM_BASE + CPM_USBVBFIL_OFFSET)
+#define CPM_USBCDR       (CPM_BASE + CPM_USBCDR_OFFSET)
+#define CPM_I2SCDR       (CPM_BASE + CPM_I2SCDR_OFFSET)
+#define CPM_LPCDR        (CPM_BASE + CPM_LPCDR_OFFSET)
+#define CPM_MSCCDR       (CPM_BASE + CPM_MSCCDR_OFFSET)
+#define CPM_UHCCDR       (CPM_BASE + CPM_UHCCDR_OFFSET)
+#define CPM_SSICDR       (CPM_BASE + CPM_SSICDR_OFFSET)
+#define CPM_CIMCDR       (CPM_BASE + CPM_CIMCDR_OFFSET)
+#define CPM_GPSCDR       (CPM_BASE + CPM_GPSCDR_OFFSET)
+#define CPM_PCMCDR       (CPM_BASE + CPM_PCMCDR_OFFSET)
+#define CPM_GPUCDR       (CPM_BASE + CPM_GPUCDR_OFFSET)
+#define CPM_PSWC0ST      (CPM_BASE + CPM_PSWC0ST_OFFSET)
+#define CPM_PSWC1ST      (CPM_BASE + CPM_PSWC1ST_OFFSET)
+#define CPM_PSWC2ST      (CPM_BASE + CPM_PSWC2ST_OFFSET)
+#define CPM_PSWC3ST      (CPM_BASE + CPM_PSWC3ST_OFFSET)
+
+
+/*
+ * CPM registers common define
+ */
+
+/* Clock control register(CPCCR) */
+#define CPCCR_ECS               BIT31
+#define CPCCR_MEM               BIT30
+#define CPCCR_CE                BIT22
+#define CPCCR_PCS               BIT21
+
+#define CPCCR_SDIV_LSB          24
+#define CPCCR_SDIV_MASK         BITS_H2L(27, CPCCR_SDIV_LSB)
+
+#define CPCCR_H2DIV_LSB         16
+#define CPCCR_H2DIV_MASK        BITS_H2L(19, CPCCR_H2DIV_LSB)
+
+#define CPCCR_MDIV_LSB          12
+#define CPCCR_MDIV_MASK         BITS_H2L(15, CPCCR_MDIV_LSB)
+
+#define CPCCR_PDIV_LSB		8
+#define CPCCR_PDIV_MASK         BITS_H2L(11, CPCCR_PDIV_LSB)
+
+#define CPCCR_HDIV_LSB		4
+#define CPCCR_HDIV_MASK         BITS_H2L(7, CPCCR_HDIV_LSB)
+
+#define CPCCR_CDIV_LSB		0
+#define CPCCR_CDIV_MASK         BITS_H2L(3, CPCCR_CDIV_LSB)
+
+/* Low power control register(LCR) */
+#define LCR_PDAHB1              BIT30
+#define LCR_VBATIR              BIT29
+#define LCR_PDGPS               BIT28
+#define LCR_PDAHB1S             BIT26
+#define LCR_PDGPSS              BIT24
+#define LCR_DOZE                BIT2
+
+#define LCR_PST_LSB             8
+#define LCR_PST_MASK            BITS_H2L(19, LCR_PST_LSB)
+
+#define LCR_DUTY_LSB            3
+#define LCR_DUTY_MASK           BITS_H2L(7, LCR_DUTY_LSB)
+
+#define LCR_LPM_LSB             0
+#define LCR_LPM_MASK            BITS_H2L(1, LCR_LPM_LSB)
+#define LCR_LPM_IDLE            (0x0 << LCR_LPM_LSB)
+#define LCR_LPM_SLEEP           (0x1 << LCR_LPM_LSB)
+
+/* Reset status register(RSR) */
+#define RSR_P0R         BIT2
+#define RSR_WR          BIT1
+#define RSR_PR          BIT0
+
+/* PLL control register 0(CPPCR0) */
+#define CPPCR0_LOCK             BIT15   /* LOCK0 bit */
+#define CPPCR0_ENLOCK           BIT14
+#define CPPCR0_PLLS             BIT10
+#define CPPCR0_PLLBP            BIT9
+#define CPPCR0_PLLEN            BIT8
+
+#define CPPCR0_PLLM_LSB         24
+#define CPPCR0_PLLM_MASK        BITS_H2L(30, CPPCR0_PLLM_LSB)
+
+#define CPPCR0_PLLN_LSB         18
+#define CPPCR0_PLLN_MASK        BITS_H2L(21, CPPCR0_PLLN_LSB)
+
+#define CPPCR0_PLLOD_LSB        16
+#define CPPCR0_PLLOD_MASK       BITS_H2L(17, CPPCR0_PLLOD_LSB)
+
+#define CPPCR0_PLLST_LSB        0
+#define CPPCR0_PLLST_MASK       BITS_H2L(7, CPPCR0_PLLST_LSB)
+
+/* PLL switch and status register(CPPSR) */
+#define CPPSR_PLLOFF            BIT31
+#define CPPSR_PLLBP             BIT30
+#define CPPSR_PLLON             BIT29
+#define CPPSR_PS                BIT28
+#define CPPSR_FS                BIT27
+#define CPPSR_CS                BIT26
+#define CPPSR_SM                BIT2
+#define CPPSR_PM                BIT1
+#define CPPSR_FM                BIT0
+
+/* Clock gate register 0(CGR0) */
+#define CLKGR0_EMC              BIT31
+#define CLKGR0_DDR              BIT30
+#define CLKGR0_IPU              BIT29
+#define CLKGR0_LCD              BIT28
+#define CLKGR0_TVE              BIT27
+#define CLKGR0_CIM              BIT26
+#define CLKGR0_MDMA             BIT25
+#define CLKGR0_UHC              BIT24
+#define CLKGR0_MAC              BIT23
+#define CLKGR0_GPS              BIT22
+#define CLKGR0_DMAC             BIT21
+#define CLKGR0_SSI2             BIT20
+#define CLKGR0_SSI1             BIT19
+#define CLKGR0_UART3            BIT18
+#define CLKGR0_UART2            BIT17
+#define CLKGR0_UART1            BIT16
+#define CLKGR0_UART0            BIT15
+#define CLKGR0_SADC             BIT14
+#define CLKGR0_KBC              BIT13
+#define CLKGR0_MSC2             BIT12
+#define CLKGR0_MSC1             BIT11
+#define CLKGR0_OWI              BIT10
+#define CLKGR0_TSSI             BIT9
+#define CLKGR0_AIC              BIT8
+#define CLKGR0_SCC              BIT7
+#define CLKGR0_I2C1             BIT6
+#define CLKGR0_I2C0             BIT5
+#define CLKGR0_SSI0             BIT4
+#define CLKGR0_MSC0             BIT3
+#define CLKGR0_OTG              BIT2
+#define CLKGR0_BCH              BIT1
+#define CLKGR0_NEMC             BIT0
+
+/* Oscillator and power control register(OPCR) */
+#define OPCR_OTGPHY_ENABLE      BIT7    /* SPENDN bit */
+#define OPCR_GPSEN              BIT6
+#define OPCR_UHCPHY_DISABLE     BIT5    /* SPENDH bit */
+#define OPCR_O1SE               BIT4
+#define OPCR_PD                 BIT3
+#define OPCR_ERCS               BIT2
+
+#define OPCR_O1ST_LSB           8
+#define OPCR_O1ST_MASK          BITS_H2L(15, OPCR_O1ST_LSB)
+
+/* Clock gate register 1(CGR1) */
+#define CLKGR1_GPU              BIT9
+#define CLKGR1_PCM              BIT8
+#define CLKGR1_AHB1             BIT7
+#define CLKGR1_CABAC            BIT6
+#define CLKGR1_SRAM             BIT5
+#define CLKGR1_DCT              BIT4
+#define CLKGR1_ME               BIT3
+#define CLKGR1_DBLK             BIT2
+#define CLKGR1_MC               BIT1
+#define CLKGR1_BDMA             BIT0
+
+/* PLL control register 1(CPPCR1) */
+#define CPPCR1_P1SCS            BIT15
+#define CPPCR1_PLL1EN           BIT7
+#define CPPCR1_PLL1S            BIT6
+#define CPPCR1_LOCK             BIT2    /* LOCK1 bit */
+#define CPPCR1_PLL1OFF          BIT1
+#define CPPCR1_PLL1ON           BIT0
+
+#define CPPCR1_PLL1M_LSB        24
+#define CPPCR1_PLL1M_MASK       BITS_H2L(30, CPPCR1_PLL1M_LSB)
+
+#define CPPCR1_PLL1N_LSB        18
+#define CPPCR1_PLL1N_MASK       BITS_H2L(21, CPPCR1_PLL1N_LSB)
+
+#define CPPCR1_PLL1OD_LSB       16
+#define CPPCR1_PLL1OD_MASK      BITS_H2L(17, CPPCR1_PLL1OD_LSB)
+
+#define CPPCR1_P1SDIV_LSB       9
+#define CPPCR1_P1SDIV_MASK      BITS_H2L(14, CPPCR1_P1SDIV_LSB)
+
+/* CPM scratch pad protected register(CPSPPR) */
+#define CPSPPR_CPSPR_WRITABLE   (0x00005a5a)
+
+/* OTG parameter control register(USBPCR) */
+#define USBPCR_USB_MODE         BIT31
+#define USBPCR_AVLD_REG         BIT30
+#define USBPCR_INCRM            BIT27   /* INCR_MASK bit */
+#define USBPCR_CLK12_EN         BIT26
+#define USBPCR_COMMONONN        BIT25
+#define USBPCR_VBUSVLDEXT       BIT24
+#define USBPCR_VBUSVLDEXTSEL    BIT23
+#define USBPCR_POR              BIT22
+#define USBPCR_SIDDQ            BIT21
+#define USBPCR_OTG_DISABLE      BIT20
+#define USBPCR_TXPREEMPHTUNE    BIT6
+
+#define USBPCR_IDPULLUP_LSB             28   /* IDPULLUP_MASK bit */
+#define USBPCR_IDPULLUP_MASK            BITS_H2L(29, USBPCR_USBPCR_IDPULLUP_LSB)
+
+#define USBPCR_COMPDISTUNE_LSB          17
+#define USBPCR_COMPDISTUNE_MASK         BITS_H2L(19, USBPCR_COMPDISTUNE_LSB)
+
+#define USBPCR_OTGTUNE_LSB              14
+#define USBPCR_OTGTUNE_MASK             BITS_H2L(16, USBPCR_OTGTUNE_LSB)
+
+#define USBPCR_SQRXTUNE_LSB             11
+#define USBPCR_SQRXTUNE_MASK            BITS_H2L(13, USBPCR_SQRXTUNE_LSB)
+
+#define USBPCR_TXFSLSTUNE_LSB           7
+#define USBPCR_TXFSLSTUNE_MASK          BITS_H2L(10, USBPCR_TXFSLSTUNE_LSB)
+
+#define USBPCR_TXRISETUNE_LSB           4
+#define USBPCR_TXRISETUNE_MASK          BITS_H2L(5, USBPCR_TXRISETUNE_LSB)
+
+#define USBPCR_TXVREFTUNE_LSB           0
+#define USBPCR_TXVREFTUNE_MASK          BITS_H2L(3, USBPCR_TXVREFTUNE_LSB)
+
+/* OTG reset detect timer register(USBRDT) */
+#define USBRDT_VBFIL_LD_EN      BIT25
+#define USBRDT_IDDIG_EN         BIT24
+#define USBRDT_IDDIG_REG        BIT23
+
+#define USBRDT_USBRDT_LSB       0
+#define USBRDT_USBRDT_MASK      BITS_H2L(22, USBRDT_USBRDT_LSB)
+
+/* OTG PHY clock divider register(USBCDR) */
+#define USBCDR_UCS              BIT31
+#define USBCDR_UPCS             BIT30
+
+#define USBCDR_OTGDIV_LSB       0       /* USBCDR bit */
+#define USBCDR_OTGDIV_MASK      BITS_H2L(5, USBCDR_OTGDIV_LSB)
+
+/* I2S device clock divider register(I2SCDR) */
+#define I2SCDR_I2CS             BIT31
+#define I2SCDR_I2PCS            BIT30
+
+#define I2SCDR_I2SDIV_LSB       0       /* I2SCDR bit */
+#define I2SCDR_I2SDIV_MASK      BITS_H2L(8, I2SCDR_I2SDIV_LSB)
+
+/* LCD pix clock divider register(LPCDR) */
+#define LPCDR_LSCS              BIT31
+#define LPCDR_LTCS              BIT30
+#define LPCDR_LPCS              BIT29
+
+#define LPCDR_PIXDIV_LSB        0       /* LPCDR bit */
+#define LPCDR_PIXDIV_MASK       BITS_H2L(10, LPCDR_PIXDIV_LSB)
+
+/* MSC clock divider register(MSCCDR) */
+#define MSCCDR_MCS              BIT31
+
+#define MSCCDR_MSCDIV_LSB       0       /* MSCCDR bit */
+#define MSCCDR_MSCDIV_MASK      BITS_H2L(5, MSCCDR_MSCDIV_LSB)
+
+/* UHC device clock divider register(UHCCDR) */
+#define UHCCDR_UHPCS            BIT31
+
+#define UHCCDR_UHCDIV_LSB       0       /* UHCCDR bit */
+#define UHCCDR_UHCDIV_MASK      BITS_H2L(3, UHCCDR_UHCDIV_LSB)
+
+/* SSI clock divider register(SSICDR) */
+#define SSICDR_SCS              BIT31
+
+#define SSICDR_SSIDIV_LSB       0       /* SSICDR bit */
+#define SSICDR_SSIDIV_MASK      BITS_H2L(5, SSICDR_SSIDIV_LSB)
+
+/* CIM mclk clock divider register(CIMCDR) */
+#define CIMCDR_CIMDIV_LSB       0       /* CIMCDR bit */
+#define CIMCDR_CIMDIV_MASK      BITS_H2L(7, CIMCDR_CIMDIV_LSB)
+
+/* GPS clock divider register(GPSCDR) */
+#define GPSCDR_GPCS             BIT31
+
+#define GPSCDR_GPSDIV_LSB       0       /* GPSCDR bit */
+#define GSPCDR_GPSDIV_MASK      BITS_H2L(3, GPSCDR_GPSDIV_LSB)
+
+/* PCM device clock divider register(PCMCDR) */
+#define PCMCDR_PCMS             BIT31
+#define PCMCDR_PCMPCS           BIT30
+
+#define PCMCDR_PCMDIV_LSB       0       /* PCMCDR bit */
+#define PCMCDR_PCMDIV_MASK      BITS_H2L(8, PCMCDR_PCMDIV_LSB)
+
+/* GPU clock divider register */
+#define GPUCDR_GPCS             BIT31
+#define GPUCDR_GPUDIV_LSB       0       /* GPUCDR bit */
+#define GPUCDR_GPUDIV_MASK      BITS_H2L(2, GPUCDR_GPUDIV_LSB)
+
+
+#ifndef __MIPS_ASSEMBLER
+
+#define REG_CPM_CPCCR           REG32(CPM_CPCCR)
+#define REG_CPM_RSR             REG32(CPM_RSR)
+#define REG_CPM_CPPCR0          REG32(CPM_CPPCR0)
+#define REG_CPM_CPPSR           REG32(CPM_CPPSR)
+#define REG_CPM_CPPCR1          REG32(CPM_CPPCR1)
+#define REG_CPM_CPSPR           REG32(CPM_CPSPR)
+#define REG_CPM_CPSPPR          REG32(CPM_CPSPPR)
+#define REG_CPM_USBPCR          REG32(CPM_USBPCR)
+#define REG_CPM_USBRDT          REG32(CPM_USBRDT)
+#define REG_CPM_USBVBFIL        REG32(CPM_USBVBFIL)
+#define REG_CPM_USBCDR          REG32(CPM_USBCDR)
+#define REG_CPM_I2SCDR          REG32(CPM_I2SCDR)
+#define REG_CPM_LPCDR           REG32(CPM_LPCDR)
+#define REG_CPM_MSCCDR          REG32(CPM_MSCCDR)
+#define REG_CPM_UHCCDR          REG32(CPM_UHCCDR)
+#define REG_CPM_SSICDR          REG32(CPM_SSICDR)
+#define REG_CPM_CIMCDR          REG32(CPM_CIMCDR)
+#define REG_CPM_GPSCDR          REG32(CPM_GPSCDR)
+#define REG_CPM_PCMCDR          REG32(CPM_PCMCDR)
+#define REG_CPM_GPUCDR          REG32(CPM_GPUCDR)
+
+#define REG_CPM_PSWC0ST         REG32(CPM_PSWC0ST)
+#define REG_CPM_PSWC1ST         REG32(CPM_PSWC1ST)
+#define REG_CPM_PSWC2ST         REG32(CPM_PSWC2ST)
+#define REG_CPM_PSWC3ST         REG32(CPM_PSWC3ST)
+
+#define REG_CPM_LCR             REG32(CPM_LCR)
+#define REG_CPM_CLKGR0          REG32(CPM_CLKGR0)
+#define REG_CPM_OPCR            REG32(CPM_OPCR)
+#define REG_CPM_CLKGR1          REG32(CPM_CLKGR1)
+#define REG_CPM_CLKGR           REG32(CPM_CLKGR0)
+
+typedef enum {
+        CGM_NEMC = 0,
+        CGM_BCH  = 1,
+        CGM_OTG  = 2,
+        CGM_MSC0 = 3,
+        CGM_SSI0 = 4,
+        CGM_I2C0 = 5,
+        CGM_I2C1 = 6,
+        CGM_SCC  = 7,
+        CGM_AIC         = 8,
+        CGM_TSSI        = 9,
+        CGM_OWI         = 10,
+        CGM_MSC1        = 11,
+        CGM_MSC2        = 12,
+        CGM_KBC         = 13,
+        CGM_SADC        = 14,
+        CGM_UART0       = 15,
+        CGM_UART1 = 16,
+        CGM_UART2 = 17,
+        CGM_UART3 = 18,
+        CGM_SSI1  = 19,
+        CGM_SSI2  = 20,
+        CGM_DMAC  = 21,
+        CGM_GPS   = 22,
+        CGM_MAC   = 23,
+        CGM_UHC         = 24,
+        CGM_MDMA        = 25,
+        CGM_CIM         = 26,
+        CGM_TVE         = 27,
+        CGM_LCD         = 28,
+        CGM_IPU         = 29,
+        CGM_DDR         = 30,
+        CGM_EMC         = 31,
+        CGM_BDMA  = 32 + 0,
+        CGM_MC    = 32 + 1,
+        CGM_DBLK  = 32 + 2,
+        CGM_ME    = 32 + 3,
+        CGM_DCT   = 32 + 4,
+        CGM_SRAM  = 32 + 5,
+        CGM_CABAC = 32 + 6,
+        CGM_AHB1  = 32 + 7,
+        CGM_PCM         = 32 + 8,
+        CGM_GPU         = 32 + 9,
+        CGM_ALL_MODULE,
+} clock_gate_module;
+
+
+#define __CGU_CLOCK_BASE__      0x1000
+
+typedef enum {
+        /* Clock source is pll0 */
+        CGU_CCLK = __CGU_CLOCK_BASE__ + 0,
+        CGU_HCLK,
+        CGU_PCLK,
+        CGU_MCLK,
+        CGU_H2CLK,
+        CGU_SCLK,
+
+        /* Clock source is exclk, pll0 or pll0/2 */
+        CGU_MSCCLK,
+        CGU_SSICLK,
+
+        /* Clock source is pll0 or pll0/2 */
+        CGU_CIMCLK,
+
+        /* Clock source is exclk, pll0, pll0/2 or pll1 */
+        CGU_TVECLK,
+
+        /* Clock source is pll0 */
+        CGU_LPCLK,
+
+        /* Clock source is exclk, exclk/2, pll0, pll0/2 or pll1 */
+        CGU_I2SCLK,
+        CGU_PCMCLK,
+        CGU_OTGCLK,
+
+        /* Clock source is pll0, pll0/2 or pll1 */
+        CGU_UHCCLK,
+        CGU_GPSCLK,
+        CGU_GPUCLK,
+
+        /* Clock source is exclk or exclk/2 */
+        CGU_UARTCLK,
+        CGU_SADCCLK,
+
+        /* Clock source is exclk */
+        CGU_TCUCLK,
+
+	/* Clock source is external rtc clock */
+	CGU_RTCCLK,
+
+        CGU_CLOCK_MAX,
+} cgu_clock;
+
+/*
+ * JZ4760 clocks structure
+ */
+typedef struct {
+	unsigned int cclk;	/* CPU clock				*/
+	unsigned int hclk;	/* System bus clock: AHB0,AHB1		*/
+	unsigned int h1clk;	/* For compatible, the same as h1clk	*/
+	unsigned int h2clk;	/* System bus clock: AHB2		*/
+	unsigned int pclk;	/* Peripheral bus clock			*/
+	unsigned int mclk;	/* EMC or DDR controller clock		*/
+	unsigned int sclk;	/* NEMC controller clock		*/
+	unsigned int cko;	/* SDRAM or DDR clock			*/
+	unsigned int pixclk;	/* LCD pixel clock			*/
+	unsigned int tveclk;	/* TV encoder 27M  clock		*/
+	unsigned int cimmclk;	/* Clock output from CIM module		*/
+	unsigned int cimpclk;	/* Clock input to CIM module		*/
+	unsigned int gpuclk;	/* GPU clock				*/
+	unsigned int gpsclk;	/* GPS clock				*/
+	unsigned int i2sclk;	/* I2S codec clock			*/
+	unsigned int bitclk;	/* AC97 bit clock			*/
+	unsigned int pcmclk;	/* PCM clock				*/
+	unsigned int mscclk;	/* MSC clock				*/
+	unsigned int ssiclk;	/* SSI clock				*/
+	unsigned int tssiclk;	/* TSSI clock				*/
+	unsigned int otgclk;	/* USB OTG clock			*/
+	unsigned int uhcclk;	/* USB UHCI clock			*/
+	unsigned int extalclk;	/* EXTAL clock for
+				   UART,I2C,TCU,USB2.0-PHY,AUDIO CODEC	*/
+	unsigned int rtcclk;	/* RTC clock for CPM,INTC,RTC,TCU,WDT	*/
+} jz_clocks_t;
+
+void cpm_start_clock(clock_gate_module module_name);
+void cpm_stop_clock(clock_gate_module module_name);
+
+unsigned int cpm_set_clock(cgu_clock clock_name, unsigned int clock_hz);
+unsigned int cpm_get_clock(cgu_clock clock_name);
+unsigned int cpm_get_pllout(void);
+unsigned int cpm_get_pllout1(void);
+
+void cpm_uhc_phy(unsigned int en);
+
+/**************remove me if android's kernel support these operations********start*********  */
+#define __cpm_stop_lcd()	(REG_CPM_CLKGR0 |= CLKGR0_LCD)
+#define __cpm_start_lcd()	(REG_CPM_CLKGR0 &= ~CLKGR0_LCD)
+#define __cpm_stop_tve()	(REG_CPM_CLKGR0 |= CLKGR0_TVE)
+#define __cpm_start_tve()	(REG_CPM_CLKGR0 &= ~CLKGR0_TVE)
+#define __cpm_set_pixdiv(v) \
+	(REG_CPM_LPCDR = (REG_CPM_LPCDR & ~LPCDR_PIXDIV_MASK) | ((v) << (LPCDR_PIXDIV_LSB)))
+
+#define __cpm_get_pixdiv() \
+	((REG_CPM_LPCDR & LPCDR_PIXDIV_MASK) >> LPCDR_PIXDIV_LSB)
+
+#define __cpm_select_pixclk_lcd()	(REG_CPM_LPCDR &= ~LPCDR_LTCS)
+#define __cpm_select_pixclk_tve()	(REG_CPM_LPCDR |= LPCDR_LTCS)
+#define __cpm_select_pixclk_lcd()	(REG_CPM_LPCDR &= ~LPCDR_LTCS)
+
+#define __cpm_start_uart0()	(REG_CPM_CLKGR0 &= ~CLKGR0_UART0)
+#define __cpm_start_uart1()	(REG_CPM_CLKGR0 &= ~CLKGR0_UART1)
+#define __cpm_start_uart2()	(REG_CPM_CLKGR0 &= ~CLKGR0_UART2)
+#define __cpm_start_uart3()	(REG_CPM_CLKGR0 &= ~CLKGR0_UART3)
+static __inline__ unsigned int __cpm_get_pllout2(void)
+{
+#if defined(CONFIG_FPGA)
+	return cpm_get_pllout();
+#else
+	if (REG_CPM_CPCCR & CPCCR_PCS)
+		return cpm_get_pllout();
+	else
+		return cpm_get_pllout()/2;
+#endif
+}
+
+static __inline__ unsigned int __cpm_get_pixclk(void)
+{
+	return __cpm_get_pllout2() / (__cpm_get_pixdiv() + 1);
+}
+
+/* EXTAL clock */
+static __inline__ unsigned int __cpm_get_extalclk0(void)
+{
+	return JZ_EXTAL;
+}
+
+/* EXTAL clock for UART,I2C,SSI,SADC,USB-PHY */
+static __inline__ unsigned int __cpm_get_extalclk(void)
+{
+#if defined(CONFIG_FPGA)
+	return __cpm_get_extalclk0() / CFG_DIV;
+#else
+	if (REG_CPM_CPCCR & CPCCR_ECS)
+		return __cpm_get_extalclk0() / 2;
+	else
+		return __cpm_get_extalclk0();
+#endif
+
+}
+
+/* RTC clock for CPM,INTC,RTC,TCU,WDT */
+static __inline__ unsigned int __cpm_get_rtcclk(void)
+{
+	return JZ_EXTAL2;
+}
+
+extern jz_clocks_t jz_clocks;
+
+#define __cpm_select_i2sclk_exclk()	(REG_CPM_I2SCDR &= ~I2SCDR_I2CS)
+#define __cpm_enable_pll_change()	(REG_CPM_CPCCR |= CPCCR_CE)
+
+#define __cpm_suspend_otg_phy()		(REG_CPM_OPCR &= ~OPCR_OTGPHY_ENABLE)
+#define __cpm_enable_otg_phy()		(REG_CPM_OPCR |=  OPCR_OTGPHY_ENABLE)
+
+#define __cpm_suspend_uhc_phy()		(REG_CPM_OPCR |= OPCR_UHCPHY_DISABLE)
+#define __cpm_enable_uhc_phy()		(REG_CPM_OPCR &= ~OPCR_UHCPHY_DISABLE)
+#define __cpm_suspend_gps()        (REG_CPM_OPCR &= ~OPCR_GPSEN)
+#define __cpm_disable_osc_in_sleep()	(REG_CPM_OPCR &= ~OPCR_O1SE)
+#define __cpm_select_rtcclk_rtc()	(REG_CPM_OPCR |= OPCR_ERCS)
+
+#define __cpm_get_pllm() \
+	((REG_CPM_CPPCR0 & CPPCR0_PLLM_MASK) >> CPPCR0_PLLM_LSB)
+#define __cpm_get_plln() \
+	((REG_CPM_CPPCR0 & CPPCR0_PLLN_MASK) >> CPPCR0_PLLN_LSB)
+#define __cpm_get_pllod() \
+	((REG_CPM_CPPCR0 & CPPCR0_PLLOD_MASK) >> CPPCR0_PLLOD_LSB)
+
+#define __cpm_get_pll1m() \
+	((REG_CPM_CPPCR1 & CPPCR1_PLL1M_MASK) >> CPPCR1_PLL1M_LSB)
+#define __cpm_get_pll1n() \
+	((REG_CPM_CPPCR1 & CPPCR1_PLL1N_MASK) >> CPPCR1_PLL1N_LSB)
+#define __cpm_get_pll1od() \
+	((REG_CPM_CPPCR1 & CPPCR1_PLL1OD_MASK) >> CPPCR1_PLL1OD_LSB)
+
+#define __cpm_get_cdiv() \
+	((REG_CPM_CPCCR & CPCCR_CDIV_MASK) >> CPCCR_CDIV_LSB)
+#define __cpm_get_hdiv() \
+	((REG_CPM_CPCCR & CPCCR_HDIV_MASK) >> CPCCR_HDIV_LSB)
+#define __cpm_get_h2div() \
+	((REG_CPM_CPCCR & CPCCR_H2DIV_MASK) >> CPCCR_H2DIV_LSB)
+#define __cpm_get_otgdiv() \
+	((REG_CPM_USBCDR & USBCDR_OTGDIV_MASK) >> USBCDR_OTGDIV_LSB)
+#define __cpm_get_pdiv() \
+	((REG_CPM_CPCCR & CPCCR_PDIV_MASK) >> CPCCR_PDIV_LSB)
+#define __cpm_get_mdiv() \
+	((REG_CPM_CPCCR & CPCCR_MDIV_MASK) >> CPCCR_MDIV_LSB)
+#define __cpm_get_sdiv() \
+	((REG_CPM_CPCCR & CPCCR_SDIV_MASK) >> CPCCR_SDIV_LSB)
+#define __cpm_get_i2sdiv() \
+	((REG_CPM_I2SCDR & I2SCDR_I2SDIV_MASK) >> I2SCDR_I2SDIV_LSB)
+#define __cpm_get_pixdiv() \
+	((REG_CPM_LPCDR & LPCDR_PIXDIV_MASK) >> LPCDR_PIXDIV_LSB)
+#define __cpm_get_mscdiv() \
+	((REG_CPM_MSCCDR & MSCCDR_MSCDIV_MASK) >> MSCCDR_MSCDIV_LSB)
+
+/*
+#define __cpm_get_mscdiv(n) \
+	((REG_CPM_MSCCDR(n) & MSCCDR_MSCDIV_MASK) >> MSCCDR_MSCDIV_LSB)
+*/
+#define __cpm_get_ssidiv() \
+	((REG_CPM_SSICDR & SSICDR_SSIDIV_MASK) >> SSICDR_SSIDIV_LSB)
+#define __cpm_get_pcmdiv() \
+	((REG_CPM_PCMCDR & PCMCDR_PCMCD_MASK) >> PCMCDR_PCMCD_LSB)
+#define __cpm_get_pll1div() \
+	((REG_CPM_CPPCR1 & CPPCR1_P1SDIV_MASK) >> CPPCR1_P1SDIV_LSB)
+
+
+#define __cpm_set_ssidiv(v) \
+	(REG_CPM_SSICDR = (REG_CPM_SSICDR & ~SSICDR_SSIDIV_MASK) | ((v) << (SSICDR_SSIDIV_LSB)))
+
+#define __cpm_exclk_direct()		(REG_CPM_CPCCR &= ~CPM_CPCCR_ECS)
+#define __cpm_exclk_div2()          (REG_CPM_CPCCR |= CPM_CPCCR_ECS)
+#define __cpm_pllout_direct()		(REG_CPM_CPCCR |= CPM_CPCCR_PCS)
+#define __cpm_pllout_div2()			(REG_CPM_CPCCR &= ~CPM_CPCCR_PCS)
+
+#define __ssi_select_exclk()		(REG_CPM_SSICDR &= ~SSICDR_SCS)
+#define __ssi_select_pllclk()		(REG_CPM_SSICDR |= SSICDR_SCS)
+
+#define cpm_get_scrpad()	INREG32(CPM_CPSPR)
+#define cpm_set_scrpad(data)				\
+do {							\
+	OUTREG32(CPM_CPSPPR, CPSPPR_CPSPR_WRITABLE);	\
+	OUTREG32(CPM_CPSPR, data);			\
+	OUTREG32(CPM_CPSPPR, ~CPSPPR_CPSPR_WRITABLE);	\
+} while (0)
+
+/**************remove me if android's kernel support these operations********end*********  */
+
+extern int jz_pm_init(void);
+
+#endif /* __MIPS_ASSEMBLER */
+
+#endif /* __JZ4760CPM_H__ */
diff --git a/arch/mips/include/asm/mach-jz4760/jz4760gpio.h b/arch/mips/include/asm/mach-jz4760/jz4760gpio.h
index ed7a699bc1b..4f452619ca8 100644
--- a/arch/mips/include/asm/mach-jz4760/jz4760gpio.h
+++ b/arch/mips/include/asm/mach-jz4760/jz4760gpio.h
@@ -408,6 +408,18 @@ do {						\
 	REG_GPIO_PXPES(4)  = 0x3ff00000;	\

 } while (0)

 

+

+#define __gpio_as_msc0_boot()			\

+do {						\

+	REG_GPIO_PXFUNS(0) = 0x00ec0000;	\

+	REG_GPIO_PXTRGC(0) = 0x00ec0000;	\

+	REG_GPIO_PXSELS(0) = 0x00ec0000;	\

+	REG_GPIO_PXPES(0)  = 0x00ec0000;	\

+	REG_GPIO_PXFUNS(0) = 0x00100000;	\

+	REG_GPIO_PXTRGC(0) = 0x00100000;	\

+	REG_GPIO_PXSELC(0) = 0x00100000;	\

+	REG_GPIO_PXPES(0)  = 0x00100000;	\

+} while (0)

 /*

  * MSC0_CMD, MSC0_CLK, MSC0_D0 ~ MSC0_D3

  */

@@ -430,35 +442,10 @@ do {						\
 	REG_GPIO_PXPES(3)  = 0x3f00000;	\

 } while (0)

 

-#if 0

-/*

- * MSC0_CMD, MSC0_CLK, MSC0_D0 ~ MSC0_D3

- */

-#define __gpio_as_msc0_4bit()			\

-do {						\

-	REG_GPIO_PXFUNS(2) = 0x38400300;	\

-	REG_GPIO_PXTRGC(2) = 0x38400300;	\

-	REG_GPIO_PXSELS(2) = 0x30400300;	\

-	REG_GPIO_PXSELC(2) = 0x08000000;	\

-	REG_GPIO_PXPES(2)  = 0x38400300;	\

-} while (0)

-

-/*

- * MSC1_CMD, MSC1_CLK, MSC1_D0 ~ MSC1_D3

- */

-#define __gpio_as_msc1_4bit()			\

-do {						\

-	REG_GPIO_PXFUNS(1) = 0xfc000000;	\

-	REG_GPIO_PXTRGC(1) = 0xfc000000;	\

-	REG_GPIO_PXSELC(1) = 0xfc000000;	\

-	REG_GPIO_PXPES(1)  = 0xfc000000;	\

-} while (0)

-#endif

-

 /* Port B

  * MSC2_CMD, MSC2_CLK, MSC2_D0 ~ MSC2_D3

  */

-#define __gpio_as_msc2_4bit_1()			\

+#define __gpio_as_msc2_4bit()			\

 do {						\

 	REG_GPIO_PXFUNS(1) = 0xf0300000;	\

 	REG_GPIO_PXTRGC(1) = 0xf0300000;	\

@@ -508,27 +495,104 @@ do {						\
 	REG_GPIO_PXSELS(0) = 0x00100000;	\

 	REG_GPIO_PXPES(0)  = 0x00100000;	\

 } while (0)

+#define __gpio_as_ssi0()				\

+do {						\

+	REG_GPIO_PXFUNS(4) = 0x000fc000; /* SSI0: SSI0_CE0, SSI0_CE1, SSI0_CLK, SSI0_DT, SSI0_DR,SSI0_GPC*/\

+	REG_GPIO_PXTRGC(4) = 0x000fc000;	\

+	REG_GPIO_PXSELC(4) = 0x000fc000;	\

+	REG_GPIO_PXPES(4)  = 0x000fc000;	\

+} while (0)

+#define __gpio_as_ssi0_x()			\

+do {						\

+	REG_GPIO_PXFUNS(4) = 0x0002c000; /*  SSI0_CLK, SSI0_DT, SSI0_DR	*/ \

+	REG_GPIO_PXTRGC(4) = 0x0002c000;	\

+	REG_GPIO_PXSELC(4) = 0x0002c000;	\

+	REG_GPIO_PXPES(4)  = 0x0002c000;	\

+} while (0)

 

-/*

- * SSI_CE0, SSI_CE2, SSI_GPC, SSI_CLK, SSI_DT, SSI1_DR

- */

-#define __gpio_as_ssi_1()			\

+#define __gpio_as_ssi0_1()				\

 do {						\

-	REG_GPIO_PXFUNS(5) = 0x0000fc00;	\

-	REG_GPIO_PXTRGC(5) = 0x0000fc00;	\

-	REG_GPIO_PXSELC(5) = 0x0000fc00;	\

-	REG_GPIO_PXPES(5)  = 0x0000fc00;	\

+	REG_GPIO_PXFUNS(1) = 0xf0300000; /* SSI0 */	\

+	REG_GPIO_PXTRGC(1) = 0xf0300000;	\

+	REG_GPIO_PXSELS(1) = 0xf0300000;	\

+	REG_GPIO_PXPES(1)  = 0xf0300000;	\

 } while (0)

 

-/* Port B

- * SSI2_CE0, SSI2_CE2, SSI2_GPC, SSI2_CLK, SSI2_DT, SSI12_DR

- */

-#define __gpio_as_ssi2_1()			\

+#define __gpio_as_ssi0_x1()				\

+do {						\

+	REG_GPIO_PXFUNS(1) = 0x10300000; /* SSI0_CLK, SSI0_DT,SSI0_DR	*/ \

+	REG_GPIO_PXTRGS(1) = 0x10300000;	\

+	REG_GPIO_PXSELC(1) = 0x10300000;	\

+	REG_GPIO_PXPES(1)  = 0x10300000;	\

+} while (0)

+#define __gpio_as_ssi0_2()				\

+do {						\

+	REG_GPIO_PXFUNS(0) = 0x00100000; /* SSI0 */	\

+	REG_GPIO_PXTRGC(0) = 0x00100000;	\

+	REG_GPIO_PXSELS(0) = 0x00100000;	\

+	REG_GPIO_PXPES(0)  = 0x00100000;	\

+										\

+	REG_GPIO_PXFUNS(0) = 0x002c0000; /* SSI0_CE0, SSI0_CLK, SSI0_DT	*/ \

+	REG_GPIO_PXTRGS(0) = 0x002c0000;	\

+	REG_GPIO_PXSELC(0) = 0x002c0000;	\

+	REG_GPIO_PXPES(0)  = 0x002c0000;	\

+} while (0)

+#define __gpio_as_ssi0_x2()			\

+do {						\

+	REG_GPIO_PXFUNS(0) = 0x00240000; /*  SSI0_CLK, SSI0_DT	*/ \

+	REG_GPIO_PXTRGS(0) = 0x00240000;	\

+	REG_GPIO_PXSELC(0) = 0x00240000;	\

+	REG_GPIO_PXPES(0)  = 0x00240000;	\

+						\

+	REG_GPIO_PXFUNS(0) = 0x00100000; /* SSI0_DR */	\

+	REG_GPIO_PXTRGC(0) = 0x00100000;	\

+	REG_GPIO_PXSELS(0) = 0x00100000;	\

+	REG_GPIO_PXPES(0)  = 0x00100000;	\

+} while (0)

+/***************** SSI 1 ***********************/

+#define __gpio_as_ssi1()				\

+do {						\

+	REG_GPIO_PXFUNS(4) = 0x000fc000; /* SSI1: SSI1_CE0, SSI1_CE1, SSI1_CLK, SSI1_DT, SSI1_DR,SSI1_GPC*/	\

+	REG_GPIO_PXTRGC(4) = 0x000fc000;	\

+	REG_GPIO_PXSELS(4) = 0x000fc000;	\

+	REG_GPIO_PXPES(4)  = 0x000fc000;	\

+} while (0)

+#define __gpio_as_ssi1_x()			\

+do {						\

+	REG_GPIO_PXFUNS(4) = 0x0002c000; /*  SSI1_CLK, SSI1_DT, SSI1_DR	*/ \

+	REG_GPIO_PXTRGC(4) = 0x0002c000;	\

+	REG_GPIO_PXSELS(4) = 0x0002c000;	\

+	REG_GPIO_PXPES(4)  = 0x0002c000;	\

+} while (0)

+

+#define __gpio_as_ssi1_1()				\

+do {						\

+	REG_GPIO_PXFUNS(1) = 0xf0300000; /* SSI1*/\

+	REG_GPIO_PXTRGC(1) = 0xf0300000;	\

+	REG_GPIO_PXSELS(1) = 0xf0300000;	\

+	REG_GPIO_PXPES(1)  = 0xf0300000;	\

+} while (0)

+#define __gpio_as_ssi1_x1()				\

+do {						\

+	REG_GPIO_PXFUNS(1) = 0x10300000; /* SSI1_x*/\

+	REG_GPIO_PXTRGC(1) = 0x10300000;	\

+	REG_GPIO_PXSELS(1) = 0x10300000;	\

+	REG_GPIO_PXPES(1)  = 0x10300000;	\

+} while (0)

+

+#define __gpio_as_ssi1_2()				\

+do {						\

+	REG_GPIO_PXFUNS(1) = 0x000003c0; /* SSI1*/\

+	REG_GPIO_PXTRGC(1) = 0x000003c0;	\

+	REG_GPIO_PXSELS(1) = 0x000003c0;	\

+	REG_GPIO_PXPES(1)  = 0x000003c0;	\

+} while (0)

+#define __gpio_as_ssi1_x2()				\

 do {						\

-	REG_GPIO_PXFUNS(5) = 0xf0300000;	\

-	REG_GPIO_PXTRGC(5) = 0xf0300000;	\

-	REG_GPIO_PXSELS(5) = 0xf0300000;	\

-	REG_GPIO_PXPES(5)  = 0xf0300000;	\

+	REG_GPIO_PXFUNS(1) = 0x000002c0; /* SSI1_x*/\

+	REG_GPIO_PXTRGC(1) = 0x000002c0;	\

+	REG_GPIO_PXSELS(1) = 0x000002c0;	\

+	REG_GPIO_PXPES(1)  = 0x000002c0;	\

 } while (0)

 

 /*

diff --git a/arch/mips/include/asm/mach-jz4760/jz4760i2c.h b/arch/mips/include/asm/mach-jz4760/jz4760i2c.h
index 584da4c794e..b2a4ae9b1e7 100644
--- a/arch/mips/include/asm/mach-jz4760/jz4760i2c.h
+++ b/arch/mips/include/asm/mach-jz4760/jz4760i2c.h
@@ -207,6 +207,8 @@
 #define __i2c_is_enable(n)       ( REG_I2C_ENSTA(n) & I2C_ENB_I2CENB )

 #define __i2c_is_disable(n)      ( !(REG_I2C_ENSTA(n) & I2C_ENB_I2CENB) )

 

+#define __i2c_abrt_intr(n)       (REG_I2C_INTST(n) & I2C_INTST_TXABT)

+

 #define __i2c_abrt(n)            ( REG_I2C_TXABRT(n) != 0 )

 #define __i2c_master_active(n)   ( REG_I2C_STA(n) & I2C_STA_MSTACT )

 #define __i2c_abrt_7b_addr_nack(n)  ( REG_I2C_TXABRT(n) & I2C_TXABRT_ABRT_7B_ADDR_NOACK )

diff --git a/arch/mips/include/asm/mach-jz4760/jz4760lcdc.h b/arch/mips/include/asm/mach-jz4760/jz4760lcdc.h
index bd7a4ce2d54..1db58a6f61b 100644
--- a/arch/mips/include/asm/mach-jz4760/jz4760lcdc.h
+++ b/arch/mips/include/asm/mach-jz4760/jz4760lcdc.h
@@ -466,208 +466,6 @@
 #define LCD_DESSIZE_WIDTH_BIT	0  /* width of foreground 1 */

 #define LCD_DESSIZE_WIDTH_MASK	(0xffff << LCD_DESSIZE_WIDTH_BIT)

 

-

-/*************************************************************************

- * EPD

- *************************************************************************/

-#if defined(CONFIG_JZ4760_AUO_EPD_DISPLAY) 

-

-#define EPD_CTRL      (LCD_BASE + 0x200)

-#define EPD_STA       (LCD_BASE + 0x204)

-#define EPD_ISR       (LCD_BASE + 0x208)

-#define EPD_CFG0      (LCD_BASE + 0x20C)

-#define EPD_CFG1      (LCD_BASE + 0x210)

-#define EPD_PPL0      (LCD_BASE + 0x214)

-#define EPD_PLL1      (LCD_BASE + 0x218)

-#define EPD_VAT       (LCD_BASE + 0x21C)

-#define EPD_DAV       (LCD_BASE + 0x220)

-#define EPD_DAH       (LCD_BASE + 0x224)

-#define EPD_VSYNC      (LCD_BASE + 0x228)

-#define EPD_HSYNC      (LCD_BASE + 0x22C)

-#define EPD_GDCLK      (LCD_BASE + 0x230)

-#define EPD_GDOE       (LCD_BASE + 0x234)

-#define EPD_GDSP       (LCD_BASE + 0x238)

-#define EPD_SDOE       (LCD_BASE + 0x23C)

-#define EPD_SDSP       (LCD_BASE + 0x240)

-#define EPD_PMGR0       (LCD_BASE + 0x244)

-#define EPD_PWGR1       (LCD_BASE + 0x248)

-#define EPD_PWGR2       (LCD_BASE + 0x24C)

-#define EPD_PWGR3       (LCD_BASE + 0x250)

-#define EPD_PWGR4       (LCD_BASE + 0x254)

-#define EPD_VCOM0       (LCD_BASE + 0x258)

-#define EPD_VCOM1       (LCD_BASE + 0x25C)

-#define EPD_VCOM2       (LCD_BASE + 0x260)

-#define EPD_VCOM3       (LCD_BASE + 0x264)

-#define EPD_VCOM4       (LCD_BASE + 0x268)

-#define EPD_VCOM5       (LCD_BASE + 0x26C)

-#define EPD_PWDR        (LCD_BASE + 0x270)

-#define EPD_PPL0_POS    (LCD_BASE + 0x280)

-#define EPD_PPL0_SIZE   (LCD_BASE + 0x284)

-#define EPD_PPL1_POS    (LCD_BASE + 0x288)

-#define EPD_PPL1_SIZE   (LCD_BASE + 0x28C)

-#define EPD_PPL2_POS    (LCD_BASE + 0x290)

-#define EPD_PPL2_SIZE   (LCD_BASE + 0x294)

-#define EPD_PPL3_POS    (LCD_BASE + 0x298)

-#define EPD_PPL3_SIZE   (LCD_BASE + 0x29C)

-#define EPD_PPL4_POS    (LCD_BASE + 0x2A0)

-#define EPD_PPL4_SIZE   (LCD_BASE + 0x2A4)

-#define EPD_PPL5_POS    (LCD_BASE + 0x2A8)

-#define EPD_PPL5_SIZE   (LCD_BASE + 0x2AC)

-#define EPD_PPL6_POS    (LCD_BASE + 0x2B0)

-#define EPD_PPL6_SIZE   (LCD_BASE + 0x2B4)

-#define EPD_PPL7_POS    (LCD_BASE + 0x2B8)

-#define EPD_PPL7_SIZE   (LCD_BASE + 0x2C0)

-

-

-#define REG_EPD_CTRL     REG32(EPD_CTRL)    

-#define REG_EPD_STA      REG32(EPD_STA) 

-#define REG_EPD_ISR      REG32(EPD_ISR) 

-#define REG_EPD_CFG0     REG32(EPD_CFG0)

-#define REG_EPD_CFG1     REG32(EPD_CFG1)

-#define REG_EPD_PPL0     REG32(EPD_PPL0)

-#define REG_EPD_PLL1     REG32(EPD_PLL1)

-#define REG_EPD_VAT      REG32(EPD_VAT) 

-#define REG_EPD_DAV      REG32(EPD_DAV)

-#define REG_EPD_DAH      REG32(EPD_DAH)       

-#define REG_EPD_VSYNC     REG32(EPD_VSYNC)     

-#define REG_EPD_HSYNC     REG32(EPD_HSYNC)     

-#define REG_EPD_GDCLK     REG32(EPD_GDCLK)     

-#define REG_EPD_GDOE      REG32(EPD_GDOE)      

-#define REG_EPD_GDSP      REG32(EPD_GDSP)      

-#define REG_EPD_SDOE      REG32(EPD_SDOE)      

-#define REG_EPD_SDSP      REG32(EPD_SDSP)      

-#define REG_EPD_PMGR0    REG32(EPD_PMGR0)    

-#define REG_EPD_PWGR1    REG32(EPD_PWGR1)    

-#define REG_EPD_PWGR2    REG32(EPD_PWGR2)    

-#define REG_EPD_PWGR3    REG32(EPD_PWGR3)    

-#define REG_EPD_PWGR4    REG32(EPD_PWGR4)    

-#define REG_EPD_VCOM0    REG32(EPD_VCOM0)    

-#define REG_EPD_VCOM1    REG32(EPD_VCOM1)    

-#define REG_EPD_VCOM2    REG32(EPD_VCOM2)    

-#define REG_EPD_VCOM3    REG32(EPD_VCOM3)    

-#define REG_EPD_VCOM4    REG32(EPD_VCOM4)    

-#define REG_EPD_VCOM5    REG32(EPD_VCOM5)    

-#define REG_EPD_PWDR     REG32(EPD_PWDR)     

-#define REG_EPD_PPL0_POS   REG32(EPD_PPL0_POS)   

-#define REG_EPD_PPL0_SIZE  REG32(EPD_PPL0_SIZE)  

-#define REG_EPD_PPL1_POS   REG32(EPD_PPL1_POS)   

-#define REG_EPD_PPL1_SIZE  REG32(EPD_PPL1_SIZE)  

-#define REG_EPD_PPL2_POS   REG32(EPD_PPL2_POS)   

-#define REG_EPD_PPL2_SIZE  REG32(EPD_PPL2_SIZE)  

-#define REG_EPD_PPL3_POS   REG32(EPD_PPL3_POS)   

-#define REG_EPD_PPL3_SIZE  REG32(EPD_PPL3_SIZE)  

-#define REG_EPD_PPL4_POS   REG32(EPD_PPL4_POS)    

-#define REG_EPD_PPL4_SIZE  REG32(EPD_PPL4_SIZE)  

-#define REG_EPD_PPL5_POS   REG32(EPD_PPL5_POS)   

-#define REG_EPD_PPL5_SIZE  REG32(EPD_PPL5_SIZE)  

-#define REG_EPD_PPL6_POS   REG32(EPD_PPL6_POS)   

-#define REG_EPD_PPL6_SIZE  REG32(EPD_PPL6_SIZE)  

-#define REG_EPD_PPL7_POS   REG32(EPD_PPL7_POS)   

-#define REG_EPD_PPL7_SIZE  REG32(EPD_PPL7_SIZE)  

-

-#else  // for E-ink

-

-

-#define EPD_CTRL1	(LCD_BASE + 0xc0)

-#define EPD_CTRL2	(LCD_BASE + 0xc4)

-#define EPD_CTRL3	(LCD_BASE + 0xc8)

-#define EPD_CTRL4	(LCD_BASE + 0xcc)

-#define EPD_CTRL5	(LCD_BASE + 0xd0)

-#define EPD_CTRL6	(LCD_BASE + 0xd4)

-#define EPD_CTRL7	(LCD_BASE + 0xd8)

-#define EPD_CTRL8	(LCD_BASE + 0xdc)

-#define EPD_CTRL9	(LCD_BASE + 0xe0)

-#define EPD_VCOM0	(LCD_BASE + 0xf0)

-#define EPD_VCOM1	(LCD_BASE + 0xf4)

-#define EPD_VCOM2	(LCD_BASE + 0xf8)

-#define EPD_VCOM3	(LCD_BASE + 0xfc)

-

-#define REG_EPD_CTRL1	REG32(EPD_CTRL1)

-#define REG_EPD_CTRL2	REG32(EPD_CTRL2)

-#define REG_EPD_CTRL3	REG32(EPD_CTRL3)

-#define REG_EPD_CTRL4	REG32(EPD_CTRL4)

-#define REG_EPD_CTRL5	REG32(EPD_CTRL5)

-#define REG_EPD_CTRL6	REG32(EPD_CTRL6)

-#define REG_EPD_CTRL7	REG32(EPD_CTRL7)

-#define REG_EPD_CTRL8	REG32(EPD_CTRL8)

-#define REG_EPD_CTRL9	REG32(EPD_CTRL9)

-

-#define REG_EPD_VCOM0 	REG32(EPD_VCOM0)

-#define REG_EPD_VCOM1 	REG32(EPD_VCOM1)

-#define REG_EPD_VCOM2 	REG32(EPD_VCOM2)

-#define REG_EPD_VCOM3 	REG32(EPD_VCOM3)

-

-

-    

-#define EPD_CTRL1_GDCEN_BIT		16

-#define EPD_CTRL1_GDCEN_MASK		(0xfff<<EPD_CTRL1_GDCEN_BIT)

-#define EPD_CTRL1_AUO		(1<<15)

-#define EPD_CTRL1_GDOEP		(1<<14)

-#define EPD_CTRL1_GDRL		(1<<13)

-#define EPD_CTRL1_SDOREV	(1<<12)

-#define EPD_CTRL1_SDCEREV	(1<<11)

-#define EPD_CTRL1_SDSHR		(1<<10)

-#define EPD_CTRL1_PPC		(1<<9)

-#define EPD_CTRL1_PADDINGD_BIT 	1

-#define EPD_CTRL1_PADDINGD_MASK (0xff<<EPD_CTRL1_PADDINGD_BIT)

-#define EPD_CTRL1_DDREN  	(1<<0)

-

-#define EPD_CTRL2_DELAY01_BIT   20 	

-#define EPD_CTRL2_DELAY01_MASK 	(0xfff<<EPD_CTRL2_DELAY01_BIT)

-#define EPD_CTRL2_PWROFF   	(1<<19)

-#define EPD_CTRL2_PWRON    	(1<<18)

-#define EPD_CTRL2_PWRCOMP    	(1<<17)

-#define EPD_CTRL2_SDCE1_BIT    	13

-#define EPD_CTRL2_SDCE1_MASK	(0xf<<EPD_CTRL2_SDCE1_BIT)

-#define EPD_CTRL2_SDOS_BIT	4

-#define EPD_CTRL2_SDOS_MASK	(0x1f<<EPD_CTRL2_SDOS_BIT)

-#define EPD_CTRL2_SDCN_BIT	0

-#define EPD_CTRL2_SDCN_MASK	(0xf<<EPD_CTRL2_SDCN_BIT)

-

-#define EPD_CTRL3_DELAY23    	

-#define EPD_CTRL3_DELAY12    	

-#define EPD_CTRL4_PWR7P    	

-#define EPD_CTRL4_PWR6P    	

-#define EPD_CTRL4_PWR5P    		

-#define EPD_CTRL4_PWR4P    	

-#define EPD_CTRL4_PWR3P    	

-#define EPD_CTRL4_PWR2P    	

-#define EPD_CTRL4_PWR1P    			

-#define EPD_CTRL4_PWR0P    		

-#define EPD_CTRL4_PWRDNM    			

-#define EPD_CTRL4_EPDDMAM    		

-#define EPD_CTRL4_FENDM        	

-#define EPD_CTRL4_FCEM            

-#define EPD_CTRL4_PWRUPM        

-#define EPD_CTRL4_FEINTSEL        

-#define EPD_CTRL4_FCANCEL        

-#define EPD_CTRL4_FEN    	(1<<9)

-#define EPD_CTRL4_SDCEP    

-#define EPD_CTRL4_SDLEP    

-#define EPD_CTRL4_SDOEP    

-#define EPD_CTRL4_GDCP    

-#define EPD_CTRL4_GDSPP    

-

-#define EPD_CTRL5_GDCDIS    

-#define EPD_CTRL5_MAX_FRM    

-#define EPD_CTRL5_DMA_MODE    

-#define EPD_CTRL5_OBPP    

-#define EPD_CTRL5_OMODE    

-#define EPD_CTRL5_EPD_EN 

-

-#define EPD_CTRL6_GDSPDIS    

-#define EPD_CTRL6_GDSPEN    

-#define EPD_CTRL7_SDOEE    

-#define EPD_CTRL7_SDOES    

-

-#define EPD_CTRL8_DELAY45    

-#define EPD_CTRL8_DELAY34    

-

-#define EPD_CTRL9_DELAY67    

-#define EPD_CTRL9_DELAY56    

-

-#endif //End E-ink

-

 #ifndef __MIPS_ASSEMBLER

 

 /*************************************************************************

@@ -796,8 +594,8 @@
 

 #define __lcd_set_24_tftpnl()		( REG_LCD_CFG |= LCD_CFG_MODE_TFT_24BIT )

 

-/* 

- * n=1,2,4,8 for single mono-STN 

+/*

+ * n=1,2,4,8 for single mono-STN

  * n=4,8 for dual mono-STN

  */

 #define __lcd_set_panel_datawidth(n) 		\

diff --git a/arch/mips/include/asm/mach-jz4760/jz4760msc.h b/arch/mips/include/asm/mach-jz4760/jz4760msc.h
index 71b9f15d098..650d073c7a4 100644
--- a/arch/mips/include/asm/mach-jz4760/jz4760msc.h
+++ b/arch/mips/include/asm/mach-jz4760/jz4760msc.h
@@ -9,16 +9,14 @@
 #ifndef __JZ4760MSC_H__

 #define __JZ4760MSC_H__

 

+#define JZ_MAX_MSC_NUM 3

+

+#define JZ_MSC_ID_INVALID(msc_id) ( ((msc_id) < 0) || ( (msc_id) > JZ_MAX_MSC_NUM ) )

 

 #define	MSC0_BASE	0xB0021000

 #define	MSC1_BASE	0xB0022000

 #define	MSC2_BASE	0xB0023000

 

-

-/*************************************************************************

- * MSC

- ************************************************************************/

-/* n = 0, 1 (MSC0, MSC1) */

 #define	MSC_STRPCL(n)		(MSC0_BASE + (n)*0x1000 + 0x000)

 #define	MSC_STAT(n)		(MSC0_BASE + (n)*0x1000 + 0x004)

 #define	MSC_CLKRT(n)		(MSC0_BASE + (n)*0x1000 + 0x008)

@@ -66,8 +64,8 @@
 #define MSC_STRPCL_START_OP		(1 << 2)

 #define MSC_STRPCL_CLOCK_CONTROL_BIT	0

 #define MSC_STRPCL_CLOCK_CONTROL_MASK	(0x3 << MSC_STRPCL_CLOCK_CONTROL_BIT)

-  #define MSC_STRPCL_CLOCK_CONTROL_STOP	  (0x1 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Stop MMC/SD clock */

-  #define MSC_STRPCL_CLOCK_CONTROL_START  (0x2 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Start MMC/SD clock */

+#define MSC_STRPCL_CLOCK_CONTROL_STOP	  (0x1 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Stop MMC/SD clock */

+#define MSC_STRPCL_CLOCK_CONTROL_START  (0x2 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Start MMC/SD clock */

 

 /* MSC Status Register (MSC_STAT) */

 #define MSC_STAT_AUTO_CMD_DONE		(1 << 31) /*12 is internally generated by controller has finished */

@@ -85,23 +83,23 @@
 #define MSC_STAT_CRC_READ_ERROR		(1 << 4)

 #define MSC_STAT_CRC_WRITE_ERROR_BIT	2

 #define MSC_STAT_CRC_WRITE_ERROR_MASK	(0x3 << MSC_STAT_CRC_WRITE_ERROR_BIT)

-  #define MSC_STAT_CRC_WRITE_ERROR_NO		(0 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No error on transmission of data */

-  #define MSC_STAT_CRC_WRITE_ERROR		(1 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* Card observed erroneous transmission of data */

-  #define MSC_STAT_CRC_WRITE_ERROR_NOSTS	(2 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No CRC status is sent back */

+#define MSC_STAT_CRC_WRITE_ERROR_NO	(0 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No error on transmission of data */

+#define MSC_STAT_CRC_WRITE_ERROR	(1 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* Card observed erroneous transmission of data */

+#define MSC_STAT_CRC_WRITE_ERROR_NOSTS	(2 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No CRC status is sent back */

 #define MSC_STAT_TIME_OUT_RES		(1 << 1)

 #define MSC_STAT_TIME_OUT_READ		(1 << 0)

 

 /* MSC Bus Clock Control Register (MSC_CLKRT) */

 #define	MSC_CLKRT_CLK_RATE_BIT		0

 #define	MSC_CLKRT_CLK_RATE_MASK		(0x7 << MSC_CLKRT_CLK_RATE_BIT)

-  #define MSC_CLKRT_CLK_RATE_DIV_1	(0x0 << MSC_CLKRT_CLK_RATE_BIT) /* CLK_SRC */

-  #define MSC_CLKRT_CLK_RATE_DIV_2	(0x1 << MSC_CLKRT_CLK_RATE_BIT) /* 1/2 of CLK_SRC */

-  #define MSC_CLKRT_CLK_RATE_DIV_4	(0x2 << MSC_CLKRT_CLK_RATE_BIT) /* 1/4 of CLK_SRC */

-  #define MSC_CLKRT_CLK_RATE_DIV_8	(0x3 << MSC_CLKRT_CLK_RATE_BIT) /* 1/8 of CLK_SRC */

-  #define MSC_CLKRT_CLK_RATE_DIV_16	(0x4 << MSC_CLKRT_CLK_RATE_BIT) /* 1/16 of CLK_SRC */

-  #define MSC_CLKRT_CLK_RATE_DIV_32	(0x5 << MSC_CLKRT_CLK_RATE_BIT) /* 1/32 of CLK_SRC */

-  #define MSC_CLKRT_CLK_RATE_DIV_64	(0x6 << MSC_CLKRT_CLK_RATE_BIT) /* 1/64 of CLK_SRC */

-  #define MSC_CLKRT_CLK_RATE_DIV_128	(0x7 << MSC_CLKRT_CLK_RATE_BIT) /* 1/128 of CLK_SRC */

+#define MSC_CLKRT_CLK_RATE_DIV_1	(0x0 << MSC_CLKRT_CLK_RATE_BIT) /* CLK_SRC */

+#define MSC_CLKRT_CLK_RATE_DIV_2	(0x1 << MSC_CLKRT_CLK_RATE_BIT) /* 1/2 of CLK_SRC */

+#define MSC_CLKRT_CLK_RATE_DIV_4	(0x2 << MSC_CLKRT_CLK_RATE_BIT) /* 1/4 of CLK_SRC */

+#define MSC_CLKRT_CLK_RATE_DIV_8	(0x3 << MSC_CLKRT_CLK_RATE_BIT) /* 1/8 of CLK_SRC */

+#define MSC_CLKRT_CLK_RATE_DIV_16	(0x4 << MSC_CLKRT_CLK_RATE_BIT) /* 1/16 of CLK_SRC */

+#define MSC_CLKRT_CLK_RATE_DIV_32	(0x5 << MSC_CLKRT_CLK_RATE_BIT) /* 1/32 of CLK_SRC */

+#define MSC_CLKRT_CLK_RATE_DIV_64	(0x6 << MSC_CLKRT_CLK_RATE_BIT) /* 1/64 of CLK_SRC */

+#define MSC_CLKRT_CLK_RATE_DIV_128	(0x7 << MSC_CLKRT_CLK_RATE_BIT) /* 1/128 of CLK_SRC */

 

 /* MSC Command Sequence Control Register (MSC_CMDAT) */

 #define	MSC_CMDAT_CCS_EXPECTED		(1 << 31) /* interrupts are enabled in ce-ata */

@@ -109,20 +107,19 @@
 #define	MSC_CMDAT_SDIO_PRDT		(1 << 17) /* exact 2 cycle */

 #define	MSC_CMDAT_SEND_AS_STOP		(1 << 16)

 #define	MSC_CMDAT_RTRG_BIT		14

-  #define MSC_CMDAT_RTRG_EQUALT_8	(0x0 << MSC_CMDAT_RTRG_BIT)

-  #define MSC_CMDAT_RTRG_EQUALT_16	(0x1 << MSC_CMDAT_RTRG_BIT) /* reset value */

-  #define MSC_CMDAT_RTRG_EQUALT_24	(0x2 << MSC_CMDAT_RTRG_BIT)

-

+#define MSC_CMDAT_RTRG_EQUALT_8		(0x0 << MSC_CMDAT_RTRG_BIT)

+#define MSC_CMDAT_RTRG_EQUALT_16	(0x1 << MSC_CMDAT_RTRG_BIT) /* reset value */

+#define MSC_CMDAT_RTRG_EQUALT_24	(0x2 << MSC_CMDAT_RTRG_BIT)

 #define	MSC_CMDAT_TTRG_BIT		12

-  #define MSC_CMDAT_TTRG_LESS_8		(0x0 << MSC_CMDAT_TTRG_BIT)

-  #define MSC_CMDAT_TTRG_LESS_16	(0x1 << MSC_CMDAT_TTRG_BIT) /*reset value  */

-  #define MSC_CMDAT_TTRG_LESS_24	(0x2 << MSC_CMDAT_TTRG_BIT)

+#define MSC_CMDAT_TTRG_LESS_8		(0x0 << MSC_CMDAT_TTRG_BIT)

+#define MSC_CMDAT_TTRG_LESS_16		(0x1 << MSC_CMDAT_TTRG_BIT) /*reset value  */

+#define MSC_CMDAT_TTRG_LESS_24		(0x2 << MSC_CMDAT_TTRG_BIT)

 #define	MSC_CMDAT_STOP_ABORT		(1 << 11)

 #define	MSC_CMDAT_BUS_WIDTH_BIT		9

 #define	MSC_CMDAT_BUS_WIDTH_MASK	(0x3 << MSC_CMDAT_BUS_WIDTH_BIT)

-  #define MSC_CMDAT_BUS_WIDTH_1BIT	(0x0 << MSC_CMDAT_BUS_WIDTH_BIT) /* 1-bit data bus */

-  #define MSC_CMDAT_BUS_WIDTH_4BIT	(0x2 << MSC_CMDAT_BUS_WIDTH_BIT) /* 4-bit data bus */

-  #define MSC_CMDAT_BUS_WIDTH_8BIT	(0x3 << MSC_CMDAT_BUS_WIDTH_BIT) /* 8-bit data bus */

+#define MSC_CMDAT_BUS_WIDTH_1BIT	(0x0 << MSC_CMDAT_BUS_WIDTH_BIT) /* 1-bit data bus */

+#define MSC_CMDAT_BUS_WIDTH_4BIT	(0x2 << MSC_CMDAT_BUS_WIDTH_BIT) /* 4-bit data bus */

+#define MSC_CMDAT_BUS_WIDTH_8BIT	(0x3 << MSC_CMDAT_BUS_WIDTH_BIT) /* 8-bit data bus */

 #define	MSC_CMDAT_DMA_EN		(1 << 8)

 #define	MSC_CMDAT_INIT			(1 << 7)

 #define	MSC_CMDAT_BUSY			(1 << 6)

@@ -132,38 +129,45 @@
 #define	MSC_CMDAT_DATA_EN		(1 << 3)

 #define	MSC_CMDAT_RESPONSE_BIT	0

 #define	MSC_CMDAT_RESPONSE_MASK	(0x7 << MSC_CMDAT_RESPONSE_BIT)

-  #define MSC_CMDAT_RESPONSE_NONE (0x0 << MSC_CMDAT_RESPONSE_BIT) /* No response */

-  #define MSC_CMDAT_RESPONSE_R1	  (0x1 << MSC_CMDAT_RESPONSE_BIT) /* Format R1 and R1b */

-  #define MSC_CMDAT_RESPONSE_R2	  (0x2 << MSC_CMDAT_RESPONSE_BIT) /* Format R2 */

-  #define MSC_CMDAT_RESPONSE_R3	  (0x3 << MSC_CMDAT_RESPONSE_BIT) /* Format R3 */

-  #define MSC_CMDAT_RESPONSE_R4	  (0x4 << MSC_CMDAT_RESPONSE_BIT) /* Format R4 */

-  #define MSC_CMDAT_RESPONSE_R5	  (0x5 << MSC_CMDAT_RESPONSE_BIT) /* Format R5 */

-  #define MSC_CMDAT_RESPONSE_R6	  (0x6 << MSC_CMDAT_RESPONSE_BIT) /* Format R6 */

-

-#define	CMDAT_DMA_EN	(1 << 8)

-#define	CMDAT_INIT	(1 << 7)

-#define	CMDAT_BUSY	(1 << 6)

-#define	CMDAT_STREAM	(1 << 5)

-#define	CMDAT_WRITE	(1 << 4)

-#define	CMDAT_DATA_EN	(1 << 3)

+#define MSC_CMDAT_RESPONSE_NONE (0x0 << MSC_CMDAT_RESPONSE_BIT) /* No response */

+#define MSC_CMDAT_RESPONSE_R1	  (0x1 << MSC_CMDAT_RESPONSE_BIT) /* Format R1 and R1b */

+#define MSC_CMDAT_RESPONSE_R2	  (0x2 << MSC_CMDAT_RESPONSE_BIT) /* Format R2 */

+#define MSC_CMDAT_RESPONSE_R3	  (0x3 << MSC_CMDAT_RESPONSE_BIT) /* Format R3 */

+#define MSC_CMDAT_RESPONSE_R4	  (0x4 << MSC_CMDAT_RESPONSE_BIT) /* Format R4 */

+#define MSC_CMDAT_RESPONSE_R5	  (0x5 << MSC_CMDAT_RESPONSE_BIT) /* Format R5 */

+#define MSC_CMDAT_RESPONSE_R6	  (0x6 << MSC_CMDAT_RESPONSE_BIT) /* Format R6 */

 

 /* MSC Interrupts Mask Register (MSC_IMASK) */

-#define	MSC_IMASK_AUTO_CMD_DONE		(1 << 8)

-#define	MSC_IMASK_SDIO			(1 << 7)

-#define	MSC_IMASK_TXFIFO_WR_REQ		(1 << 6)

-#define	MSC_IMASK_RXFIFO_RD_REQ		(1 << 5)

-#define	MSC_IMASK_END_CMD_RES		(1 << 2)

-#define	MSC_IMASK_PRG_DONE		(1 << 1)

-#define	MSC_IMASK_DATA_TRAN_DONE	(1 << 0)

+#define	MSC_IMASK_AUTO_CMD_DONE		BIT15

+#define MSC_IMASK_DATA_FIFO_FULL	BIT14

+#define MSC_IMASK_DATA_FIFO_EMP		BIT13

+#define MSC_IMASK_CRC_RES_ERR		BIT12

+#define MSC_IMASK_CRC_READ_ERR		BIT11

+#define MSC_IMASK_CRC_WRITE_ERR		BIT10

+#define MSC_IMASK_TIMEOUT_RES		BIT9

+#define MSC_IMASK_TIMEOUT_READ		BIT8

+#define	MSC_IMASK_SDIO			BIT7

+#define	MSC_IMASK_TXFIFO_WR_REQ		BIT6

+#define	MSC_IMASK_RXFIFO_RD_REQ		BIT5

+#define	MSC_IMASK_END_CMD_RES		BIT2

+#define	MSC_IMASK_PRG_DONE		BIT1

+#define	MSC_IMASK_DATA_TRAN_DONE	BIT0

 

 /* MSC Interrupts Status Register (MSC_IREG) */

-#define	MSC_IREG_AUTO_CMD_DONE		(1 << 8)

-#define	MSC_IREG_SDIO			(1 << 7)

-#define	MSC_IREG_TXFIFO_WR_REQ		(1 << 6)

-#define	MSC_IREG_RXFIFO_RD_REQ		(1 << 5)

-#define	MSC_IREG_END_CMD_RES		(1 << 2)

-#define	MSC_IREG_PRG_DONE		(1 << 1)

-#define	MSC_IREG_DATA_TRAN_DONE		(1 << 0)

+#define	MSC_IREG_AUTO_CMD_DONE		BIT15

+#define MSC_IREG_DATA_FIFO_FULL		BIT14

+#define MSC_IREG_DATA_FIFO_EMP		BIT13

+#define MSC_IREG_CRC_RES_ERR		BIT12

+#define MSC_IREG_CRC_READ_ERR		BIT11

+#define MSC_IREG_CRC_WRITE_ERR		BIT10

+#define MSC_IREG_TIMEOUT_RES		BIT9

+#define MSC_IREG_TIMEOUT_READ		BIT8

+#define	MSC_IREG_SDIO			BIT7

+#define	MSC_IREG_TXFIFO_WR_REQ		BIT6

+#define	MSC_IREG_RXFIFO_RD_REQ		BIT5

+#define	MSC_IREG_END_CMD_RES		BIT2

+#define	MSC_IREG_PRG_DONE		BIT1

+#define	MSC_IREG_DATA_TRAN_DONE		BIT0

 

 /* MSC Low Power Mode Register (MSC_LPM) */

 #define	MSC_SET_LPM			(1 << 0)

@@ -176,7 +180,7 @@
  ***************************************************************************/

 /* n = 0, 1 (MSC0, MSC1) */

 

-#define __msc_start_op(n) \

+#define __msc_start_op(n)						\

 	( REG_MSC_STRPCL(n) = MSC_STRPCL_START_OP | MSC_STRPCL_CLOCK_CONTROL_START )

 

 #define __msc_set_resto(n, to)  	( REG_MSC_RESTO(n) = to )

@@ -190,17 +194,17 @@
 #define __msc_set_cmdat_ioabort(n) 	( REG_MSC_CMDAT(n) |= MSC_CMDAT_IO_ABORT )

 #define __msc_clear_cmdat_ioabort(n) 	( REG_MSC_CMDAT(n) &= ~MSC_CMDAT_IO_ABORT )

 

-#define __msc_set_cmdat_bus_width1(n) 			\

-do { 							\

-	REG_MSC_CMDAT(n) &= ~MSC_CMDAT_BUS_WIDTH_MASK; 	\

-	REG_MSC_CMDAT(n) |= MSC_CMDAT_BUS_WIDTH_1BIT; 	\

-} while(0)

+#define __msc_set_cmdat_bus_width1(n)				\

+	do { 							\

+		REG_MSC_CMDAT(n) &= ~MSC_CMDAT_BUS_WIDTH_MASK; 	\

+		REG_MSC_CMDAT(n) |= MSC_CMDAT_BUS_WIDTH_1BIT; 	\

+	} while(0)

 

-#define __msc_set_cmdat_bus_width4(n) 			\

-do { 							\

-	REG_MSC_CMDAT(n) &= ~MSC_CMDAT_BUS_WIDTH_MASK; 	\

-	REG_MSC_CMDAT(n) |= MSC_CMDAT_BUS_WIDTH_4BIT; 	\

-} while(0)

+#define __msc_set_cmdat_bus_width4(n)				\

+	do { 							\

+		REG_MSC_CMDAT(n) &= ~MSC_CMDAT_BUS_WIDTH_MASK; 	\

+		REG_MSC_CMDAT(n) |= MSC_CMDAT_BUS_WIDTH_4BIT; 	\

+	} while(0)

 

 #define __msc_set_cmdat_dma_en(n)       ( REG_MSC_CMDAT(n) |= MSC_CMDAT_DMA_EN )

 #define __msc_set_cmdat_init(n) 	( REG_MSC_CMDAT(n) |= MSC_CMDAT_INIT )

@@ -213,15 +217,15 @@ do { 							\
 

 /* r is MSC_CMDAT_RESPONSE_FORMAT_Rx or MSC_CMDAT_RESPONSE_FORMAT_NONE */

 #define __msc_set_cmdat_res_format(n, r)				\

-do { 								\

-	REG_MSC_CMDAT(n) &= ~MSC_CMDAT_RESPONSE_FORMAT_MASK; 	\

-	REG_MSC_CMDAT(n) |= (r); 					\

-} while(0)

+	do { 								\

+		REG_MSC_CMDAT(n) &= ~MSC_CMDAT_RESPONSE_FORMAT_MASK; 	\

+		REG_MSC_CMDAT(n) |= (r);				\

+	} while(0)

 

-#define __msc_clear_cmdat(n) \

-  REG_MSC_CMDAT(n) &= ~( MSC_CMDAT_IO_ABORT | MSC_CMDAT_DMA_EN | MSC_CMDAT_INIT| \

-  MSC_CMDAT_BUSY | MSC_CMDAT_STREAM_BLOCK | MSC_CMDAT_WRITE_READ | \

-  MSC_CMDAT_DATA_EN | MSC_CMDAT_RESPONSE_FORMAT_MASK )

+#define __msc_clear_cmdat(n)						\

+	REG_MSC_CMDAT(n) &= ~( MSC_CMDAT_IO_ABORT | MSC_CMDAT_DMA_EN | MSC_CMDAT_INIT| \

+			       MSC_CMDAT_BUSY | MSC_CMDAT_STREAM_BLOCK | MSC_CMDAT_WRITE_READ | \

+			       MSC_CMDAT_DATA_EN | MSC_CMDAT_RESPONSE_FORMAT_MASK )

 

 #define __msc_get_imask(n) 		( REG_MSC_IMASK(n) )

 #define __msc_mask_all_intrs(n) 	( REG_MSC_IMASK(n) = 0xff )

@@ -238,10 +242,10 @@ do { 								\
 #define __msc_unmask_prgdone(n) 	( REG_MSC_IMASK(n) &= ~MSC_IMASK_PRG_DONE )

 

 /* m=0,1,2,3,4,5,6,7 */

-#define __msc_set_clkrt(n, m) 	\

-do { 				\

-	REG_MSC_CLKRT(n) = m;	\

-} while(0)

+#define __msc_set_clkrt(n, m)			\

+	do {					\

+		REG_MSC_CLKRT(n) = m;		\

+	} while(0)

 

 #define __msc_get_ireg(n) 	        	( REG_MSC_IREG(n) )

 #define __msc_ireg_rd(n) 	        	( REG_MSC_IREG(n) & MSC_IREG_RXFIFO_RD_REQ )

@@ -255,8 +259,8 @@ do { 				\
 

 #define __msc_get_stat(n) 		( REG_MSC_STAT(n) )

 #define __msc_stat_not_end_cmd_res(n) 	( (REG_MSC_STAT(n) & MSC_STAT_END_CMD_RES) == 0)

-#define __msc_stat_crc_err(n) \

-  ( REG_MSC_STAT(n) & (MSC_STAT_CRC_RES_ERR | MSC_STAT_CRC_READ_ERROR | MSC_STAT_CRC_WRITE_ERROR_YES) )

+#define __msc_stat_crc_err(n)						\

+	( REG_MSC_STAT(n) & (MSC_STAT_CRC_RES_ERR | MSC_STAT_CRC_READ_ERROR | MSC_STAT_CRC_WRITE_ERROR_YES) )

 #define __msc_stat_res_crc_err(n) 	( REG_MSC_STAT(n) & MSC_STAT_CRC_RES_ERR )

 #define __msc_stat_rd_crc_err(n) 	( REG_MSC_STAT(n) & MSC_STAT_CRC_READ_ERROR )

 #define __msc_stat_wr_crc_err(n) 	( REG_MSC_STAT(n) & MSC_STAT_CRC_WRITE_ERROR_YES )

@@ -267,55 +271,55 @@ do { 				\
 #define __msc_rd_rxfifo(n)  		( REG_MSC_RXFIFO(n) )

 #define __msc_wr_txfifo(n, v)  		( REG_MSC_TXFIFO(n) = v )

 

-#define __msc_reset(n) 						\

-do { 								\

-	REG_MSC_STRPCL(n) = MSC_STRPCL_RESET;			\

- 	while (REG_MSC_STAT(n) & MSC_STAT_IS_RESETTING);		\

-} while (0)

+#define __msc_reset(n)							\

+	do { 								\

+		REG_MSC_STRPCL(n) = MSC_STRPCL_RESET;			\

+		while (REG_MSC_STAT(n) & MSC_STAT_IS_RESETTING);	\

+	} while (0)

 

-#define __msc_start_clk(n) 					\

-do { 								\

-	REG_MSC_STRPCL(n) = MSC_STRPCL_CLOCK_CONTROL_START;	\

-} while (0)

+#define __msc_start_clk(n)						\

+	do { 								\

+		REG_MSC_STRPCL(n) = MSC_STRPCL_CLOCK_CONTROL_START;	\

+	} while (0)

 

-#define __msc_stop_clk(n) 					\

-do { 								\

-	REG_MSC_STRPCL(n) = MSC_STRPCL_CLOCK_CONTROL_STOP;	\

-} while (0)

+#define __msc_stop_clk(n)						\

+	do { 								\

+		REG_MSC_STRPCL(n) = MSC_STRPCL_CLOCK_CONTROL_STOP;	\

+	} while (0)

 

 #define MMC_CLK 19169200

 #define SD_CLK  24576000

 

 /* msc_clk should little than pclk and little than clk retrieve from card */

-#define __msc_calc_clk_divisor(type,dev_clk,msc_clk,lv)		\

-do {								\

-	unsigned int rate, pclk, i;				\

-	pclk = dev_clk;						\

-	rate = type?SD_CLK:MMC_CLK;				\

-  	if (msc_clk && msc_clk < pclk)				\

-    		pclk = msc_clk;					\

-	i = 0;							\

-  	while (pclk < rate)					\

-    	{							\

-      		i ++;						\

-      		rate >>= 1;					\

-    	}							\

-  	lv = i;							\

-} while(0)

+#define __msc_calc_clk_divisor(type,dev_clk,msc_clk,lv)	\

+	do {						\

+		unsigned int rate, pclk, i;		\

+		pclk = dev_clk;				\

+		rate = type?SD_CLK:MMC_CLK;		\

+		if (msc_clk && msc_clk < pclk)		\

+			pclk = msc_clk;			\

+		i = 0;					\

+		while (pclk < rate)			\

+		{					\

+			i ++;				\

+			rate >>= 1;			\

+		}					\

+		lv = i;					\

+	} while(0)

 

 /* divide rate to little than or equal to 400kHz */

-#define __msc_calc_slow_clk_divisor(type, lv)			\

-do {								\

-	unsigned int rate, i;					\

-	rate = (type?SD_CLK:MMC_CLK)/1000/400;			\

-	i = 0;							\

-	while (rate > 0)					\

-    	{							\

-      		rate >>= 1;					\

-      		i ++;						\

-    	}							\

-  	lv = i;							\

-} while(0)

+#define __msc_calc_slow_clk_divisor(type, lv)		\

+	do {						\

+		unsigned int rate, i;			\

+		rate = (type?SD_CLK:MMC_CLK)/1000/400;	\

+		i = 0;					\

+		while (rate > 0)			\

+		{					\

+			rate >>= 1;			\

+			i ++;				\

+		}					\

+		lv = i;					\

+	} while(0)

 

 

 

diff --git a/arch/mips/include/asm/mach-jz4760/jz4760nemc.h b/arch/mips/include/asm/mach-jz4760/jz4760nemc.h
index abc0374c5d8..2d847659a29 100644
--- a/arch/mips/include/asm/mach-jz4760/jz4760nemc.h
+++ b/arch/mips/include/asm/mach-jz4760/jz4760nemc.h
@@ -12,44 +12,92 @@
 

 #define NEMC_BASE	0xB3410000

 

-/*************************************************************************

- * NEMC (External Memory Controller for NAND)

- *************************************************************************/

+#define NEMC_BCR		(NEMC_BASE + 0x0)  /* BCR */

+

+#define NEMC_SMCR1	(NEMC_BASE + 0x14)  /* Static Memory Control Register 1 */

+#define NEMC_SMCR2	(NEMC_BASE + 0x18)  /* Static Memory Control Register 2 */

+#define NEMC_SMCR3	(NEMC_BASE + 0x1c)  /* Static Memory Control Register 3 */

+#define NEMC_SMCR4	(NEMC_BASE + 0x20)  /* Static Memory Control Register 4 */

+#define NEMC_SMCR5	(NEMC_BASE + 0x24)  /* Static Memory Control Register 5 */

+#define NEMC_SMCR6	(NEMC_BASE + 0x28)  /* Static Memory Control Register 6 */

+#define NEMC_SACR1	(NEMC_BASE + 0x34)  /* Static Memory Bank 1 Addr Config Reg */

+#define NEMC_SACR2	(NEMC_BASE + 0x38)  /* Static Memory Bank 2 Addr Config Reg */

+#define NEMC_SACR3	(NEMC_BASE + 0x3c)  /* Static Memory Bank 3 Addr Config Reg */

+#define NEMC_SACR4	(NEMC_BASE + 0x40)  /* Static Memory Bank 4 Addr Config Reg */

+#define NEMC_SACR5	(NEMC_BASE + 0x44)  /* Static Memory Bank 5 Addr Config Reg */

+#define NEMC_SACR6	(NEMC_BASE + 0x48)  /* Static Memory Bank 6 Addr Config Reg */

 

 #define NEMC_NFCSR	(NEMC_BASE + 0x050) /* NAND Flash Control/Status Register */

-#define NEMC_SMCR	(NEMC_BASE + 0x14)  /* Static Memory Control Register 1 */

 

+#define REG_NEMC_BCR	REG32(NEMC_BCR)

+#define REG_NEMC_SMCR1	REG32(NEMC_SMCR1)

+#define REG_NEMC_SMCR2	REG32(NEMC_SMCR2)

+#define REG_NEMC_SMCR3	REG32(NEMC_SMCR3)

+#define REG_NEMC_SMCR4	REG32(NEMC_SMCR4)

+#define REG_NEMC_SMCR5	REG32(NEMC_SMCR5)

+#define REG_NEMC_SMCR6	REG32(NEMC_SMCR6)

+#define REG_NEMC_SACR1	REG32(NEMC_SACR1)

+#define REG_NEMC_SACR2	REG32(NEMC_SACR2)

+#define REG_NEMC_SACR3	REG32(NEMC_SACR3)

+#define REG_NEMC_SACR4	REG32(NEMC_SACR4)

+#define REG_NEMC_SACR5	REG32(NEMC_SACR5)

+#define REG_NEMC_SACR6	REG32(NEMC_SACR6)

 

-#define REG_NEMC_NFCSR	REG32(NEMC_NFCSR)

-#define REG_NEMC_SMCR1	REG32(NEMC_SMCR)

 

-// PN(bit 0):0-disable, 1-enable

-// PN(bit 1):0-no reset, 1-reset

-// (bit 2):Reserved

-// BITCNT(bit 3):0-disable, 1-enable

-// BITCNT(bit 4):0-calculate, 1's number, 1-calculate 0's number

-// BITCNT(bit 5):0-no reset, 1-reset bitcnt

-#define NEMC_PNCR 	(NEMC_BASE+0x100)

-#define NEMC_PNDR 	(NEMC_BASE+0x104)

-#define NEMC_BITCNT	(NEMC_BASE+0x108)

+#define REG_NEMC_NFCSR	REG32(NEMC_NFCSR)

 

-#define REG_NEMC_PNCR REG32(NEMC_PNCR)

-#define REG_NEMC_PNDR REG32(NEMC_PNDR)

-#define REG_NEMC_BITCNT REG32(NEMC_BITCNT)

 

-#define REG_NEMC_SMCR	REG32(NEMC_SMCR)

+/* Bus Control Register */

+#define NEMC_BCR_BT_SEL_BIT      30

+#define NEMC_BCR_BT_SEL_MASK     (0x3 << NEMC_BCR_BT_SEL_BIT)

+#define NEMC_BCR_PK_SEL          (1 << 24)

+#define NEMC_BCR_BSR_MASK          (1 << 2)  /* Nand and SDRAM Bus Share Select: 0, share; 1, unshare */

+  #define NEMC_BCR_BSR_SHARE       (0 << 2)

+  #define NEMC_BCR_BSR_UNSHARE     (1 << 2)

+#define NEMC_BCR_BRE             (1 << 1)

+#define NEMC_BCR_ENDIAN          (1 << 0)

+

+/* Static Memory Control Register */

+#define NEMC_SMCR_STRV_BIT	24

+#define NEMC_SMCR_STRV_MASK	(0x0f << NEMC_SMCR_STRV_BIT)

+#define NEMC_SMCR_TAW_BIT	20

+#define NEMC_SMCR_TAW_MASK	(0x0f << NEMC_SMCR_TAW_BIT)

+#define NEMC_SMCR_TBP_BIT	16

+#define NEMC_SMCR_TBP_MASK	(0x0f << NEMC_SMCR_TBP_BIT)

+#define NEMC_SMCR_TAH_BIT	12

+#define NEMC_SMCR_TAH_MASK	(0x07 << NEMC_SMCR_TAH_BIT)

+#define NEMC_SMCR_TAS_BIT	8

+#define NEMC_SMCR_TAS_MASK	(0x07 << NEMC_SMCR_TAS_BIT)

+#define NEMC_SMCR_BW_BIT		6

+#define NEMC_SMCR_BW_MASK	(0x03 << NEMC_SMCR_BW_BIT)

+  #define NEMC_SMCR_BW_8BIT	(0 << NEMC_SMCR_BW_BIT)

+  #define NEMC_SMCR_BW_16BIT	(1 << NEMC_SMCR_BW_BIT)

+  #define NEMC_SMCR_BW_32BIT	(2 << NEMC_SMCR_BW_BIT)

+#define NEMC_SMCR_BCM		(1 << 3)

+#define NEMC_SMCR_BL_BIT		1

+#define NEMC_SMCR_BL_MASK	(0x03 << NEMC_SMCR_BL_BIT)

+  #define NEMC_SMCR_BL_4		(0 << NEMC_SMCR_BL_BIT)

+  #define NEMC_SMCR_BL_8		(1 << NEMC_SMCR_BL_BIT)

+  #define NEMC_SMCR_BL_16	(2 << NEMC_SMCR_BL_BIT)

+  #define NEMC_SMCR_BL_32	(3 << NEMC_SMCR_BL_BIT)

+#define NEMC_SMCR_SMT		(1 << 0)

+

+/* Static Memory Bank Addr Config Reg */

+#define NEMC_SACR_BASE_BIT	8

+#define NEMC_SACR_BASE_MASK	(0xff << NEMC_SACR_BASE_BIT)

+#define NEMC_SACR_MASK_BIT	0

+#define NEMC_SACR_MASK_MASK	(0xff << NEMC_SACR_MASK_BIT)

 

 /* NAND Flash Control/Status Register */

-#define NEMC_NFCSR_NFCE4	(1 << 7) /* NAND Flash Enable */

+#define NEMC_NFCSR_NFCE4		(1 << 7) /* NAND Flash Enable */

 #define NEMC_NFCSR_NFE4		(1 << 6) /* NAND Flash FCE# Assertion Enable */

-#define NEMC_NFCSR_NFCE3	(1 << 5)

+#define NEMC_NFCSR_NFCE3		(1 << 5)

 #define NEMC_NFCSR_NFE3		(1 << 4)

-#define NEMC_NFCSR_NFCE2	(1 << 3)

+#define NEMC_NFCSR_NFCE2		(1 << 3)

 #define NEMC_NFCSR_NFE2		(1 << 2)

-#define NEMC_NFCSR_NFCE1	(1 << 1)

+#define NEMC_NFCSR_NFCE1		(1 << 1)

 #define NEMC_NFCSR_NFE1		(1 << 0)

 

-

 #ifndef __MIPS_ASSEMBLER

 

 #endif /* __MIPS_ASSEMBLER */

diff --git a/arch/mips/include/asm/mach-jz4760/jz4760ssi.h b/arch/mips/include/asm/mach-jz4760/jz4760ssi.h
index f2b027b7b92..5937dacd889 100644
--- a/arch/mips/include/asm/mach-jz4760/jz4760ssi.h
+++ b/arch/mips/include/asm/mach-jz4760/jz4760ssi.h
@@ -20,13 +20,13 @@
  * SSI (Synchronous Serial Interface)

  *************************************************************************/

 /* n = 0, 1 (SSI0, SSI1) */

-#define	SSI_DR(n)		(SSI0_BASE + 0x000 + (n)*0x2000)

-#define	SSI_CR0(n)		(SSI0_BASE + 0x004 + (n)*0x2000)

-#define	SSI_CR1(n)		(SSI0_BASE + 0x008 + (n)*0x2000)

-#define	SSI_SR(n)		(SSI0_BASE + 0x00C + (n)*0x2000)

-#define	SSI_ITR(n)		(SSI0_BASE + 0x010 + (n)*0x2000)

-#define	SSI_ICR(n)		(SSI0_BASE + 0x014 + (n)*0x2000)

-#define	SSI_GR(n)		(SSI0_BASE + 0x018 + (n)*0x2000)

+#define	SSI_DR(n)		(SSI0_BASE + 0x000 + (n)*0x1000)

+#define	SSI_CR0(n)		(SSI0_BASE + 0x004 + (n)*0x1000)

+#define	SSI_CR1(n)		(SSI0_BASE + 0x008 + (n)*0x1000)

+#define	SSI_SR(n)		(SSI0_BASE + 0x00C + (n)*0x1000)

+#define	SSI_ITR(n)		(SSI0_BASE + 0x010 + (n)*0x1000)

+#define	SSI_ICR(n)		(SSI0_BASE + 0x014 + (n)*0x1000)

+#define	SSI_GR(n)		(SSI0_BASE + 0x018 + (n)*0x1000)

 

 #define	REG_SSI_DR(n)		REG32(SSI_DR(n))

 #define	REG_SSI_CR0(n)		REG16(SSI_CR0(n))

@@ -90,7 +90,7 @@
   #define SSI_CR1_FMAT_MW1	  (2 << SSI_CR1_FMAT_BIT) /* National Microwire 1 format */

   #define SSI_CR1_FMAT_MW2	  (3 << SSI_CR1_FMAT_BIT) /* National Microwire 2 format */

 #define SSI_CR1_TTRG_BIT	16 /* SSI1 TX trigger */

-#define SSI_CR1_TTRG_MASK	(0xf << SSI_CR1_TTRG_BIT) 

+#define SSI_CR1_TTRG_MASK	(0xf << SSI_CR1_TTRG_BIT)

 #define SSI_CR1_MCOM_BIT	12

 #define SSI_CR1_MCOM_MASK	(0xf << SSI_CR1_MCOM_BIT)

   #define SSI_CR1_MCOM_1BIT	  (0x0 << SSI_CR1_MCOM_BIT) /* 1-bit command selected */

@@ -272,7 +272,7 @@ do { 						\
 /* frmhl,endian,mcom,flen,pha,pol MASK */

 #define SSICR1_MISC_MASK 					\

 	( SSI_CR1_FRMHL_MASK | SSI_CR1_LFST | SSI_CR1_MCOM_MASK	\

-	  | SSI_CR1_FLEN_MASK | SSI_CR1_PHA | SSI_CR1_POL )	

+	  | SSI_CR1_FLEN_MASK | SSI_CR1_PHA | SSI_CR1_POL )

 

 #define __ssi_spi_set_misc(n,frmhl,endian,flen,mcom,pha,pol)		\

 	do {								\

@@ -287,7 +287,7 @@ do { 						\
 #define __ssi_set_lsb(n) ( REG_SSI_CR1(n) |= SSI_CR1_LFST )

 

 #define __ssi_set_frame_length(n, m)					\

-	REG_SSI_CR1(n) = (REG_SSI_CR1(n) & ~SSI_CR1_FLEN_MASK) | (((m) - 2) << 4) 

+	REG_SSI_CR1(n) = (REG_SSI_CR1(n) & ~SSI_CR1_FLEN_MASK) | (((m) - 2) << 4)

 

 /* m = 1 - 16 */

 #define __ssi_set_microwire_command_length(n,m)				\

@@ -341,7 +341,18 @@ do { 						\
 #define __ssi_transmit_data(n, v) 	(REG_SSI_DR(n) = (v))

 

 

+#define __ssi_set_grdiv(n,v)			(REG_SSI_GR(n) = v)

+#define __ssi_get_grdiv(n)				(REG_SSI_GR(n))

 

+#define __ssi_txfifo_half_empty_intr(n)  \

+	( REG_SSI_CR0(n) & SSI_CR0_TIE )

+#define __ssi_rxfifo_half_full_intr(n)	\

+	( REG_SSI_CR0(n) & SSI_CR0_RIE )

+	

+#define __ssi_tx_error_intr(n)		\

+	( REG_SSI_CR0(n) & SSI_CR0_TEIE )

+#define __ssi_rx_error_intr(n)		\

+	( REG_SSI_CR0(n) & SSI_CR0_REIE )	

 

 

 #endif /* __MIPS_ASSEMBLER */

diff --git a/arch/mips/include/asm/mach-jz4760/platform.h b/arch/mips/include/asm/mach-jz4760/platform.h
new file mode 100644
index 00000000000..73ea5608cf7
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4760/platform.h
@@ -0,0 +1,50 @@
+#ifndef __JZ4760_PLATFORM_H__
+#define __JZ4760_PLATFORM_H__
+
+/* msc */
+#define CARD_INSERTED 1
+#define CARD_REMOVED 0
+
+#ifdef CONFIG_JZ_RECOVERY_SUPPORT
+struct mmc_partition_info {
+	char name[32];
+	unsigned int saddr;
+	unsigned int len;
+	int type;
+};
+#endif
+
+struct jz_mmc_platform_data {
+	unsigned int ocr_mask;			/* available voltages */
+	unsigned long detect_delay;		/* delay in jiffies before detecting cards after interrupt */
+	unsigned char status_irq;
+	unsigned char support_sdio;
+	unsigned char bus_width;
+	unsigned int max_bus_width;
+	unsigned int detect_pin;
+
+	unsigned char msc_irq;
+	unsigned char dma_rxid;
+	unsigned char dma_txid;
+
+	void *driver_data;
+
+	void (*init) (struct device *);
+	void (*power_on) (struct device *);
+	void (*power_off) (struct device *);
+	void (*cpm_start) (struct device *);
+	unsigned int (*status) (struct device *);
+	unsigned int (*write_protect) (struct device *);
+	void (*plug_change) (int);
+#ifdef CONFIG_JZ_RECOVERY_SUPPORT
+	struct mmc_partition_info *partitions;
+	int num_partitions;
+	
+	unsigned int permission;
+	
+#define MMC_BOOT_AREA_PROTECTED	(0x1234)	/* Can not modified the area protected */
+#define MMC_BOOT_AREA_OPENED	(0x4321)	/* Can modified the area protected */
+#endif
+};
+
+#endif /* __JZ4760_PLATFORM_H__ */
diff --git a/arch/mips/include/asm/mach-jz4760/spi.h b/arch/mips/include/asm/mach-jz4760/spi.h
new file mode 100644
index 00000000000..bbc3b96c4bd
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4760/spi.h
@@ -0,0 +1,87 @@
+/*

+ * linux/arch/mips/include/asm/mach-jz4760/spi.h

+ *

+ * SSI controller for SPI protocol,use FIFO and DMA;

+ *

+ * Copyright (c) 2010 Ingenic Semiconductor Inc.

+ * Author: Shumb <sbhuang@ingenic.cn>

+ *

+ *  This program is free software; you can redistribute	 it and/or modify it

+ *  under  the terms of	 the GNU General  Public License as published by the

+ *  Free Software Foundation;  either version 2 of the	License, or (at your

+ *  option) any later version.

+ */

+

+#ifndef __I_SPI_H__

+#define __I_SPI_H__

+

+#define R_MODE		0x1

+#define W_MODE		0x2

+#define RW_MODE	(R_MODE | W_MODE)

+

+#define R_DMA		0x4

+#define W_DMA		0x8

+#define RW_DMA		(R_DMA |W_DMA)

+

+#define SPI_DMA_ERROR  		3

+#define SPI_CPU_ERROR		4

+

+#define JZ_SSI_MAX_FIFO_ENTRIES 	128

+#define JZ_SSI_DMA_BURST_LENGTH 	16

+

+#define FIFO_8_BIT		1

+#define FIFO_16_BIT		2

+#define FIFO_32_BIT		4

+

+

+/* the max number of spi devices */

+#define MAX_SPI_DEVICES				10

+

+#define PIN_SSI_CE0 	0

+#define PIN_SSI_CE1 	1

+

+struct jz47xx_spi_info {

+	u8	chnl;								/* the chanel of SSI controller */

+	u16	bus_num;							/* spi_master.bus_num */

+	unsigned is_pllclk:1;					/* source clock: 1---pllclk;0---exclk */

+	unsigned long		 board_size;		/* spi_master.num_chipselect */

+	struct spi_board_info	*board_info; 	/* link to spi devices info */

+	void (*set_cs)(struct jz47xx_spi_info *spi, u8 cs,unsigned int pol); /* be defined by spi devices driver user */

+	void (*pins_config)(void);				/* configure spi function pins (CLK,DR,RT) by user if need. */

+	u32		 pin_cs[MAX_SPI_DEVICES];		/* the member is pin_value according to spi_device.chip_select,

+												if uses spi controller driver "set_cs",it must be filled.*/

+};

+

+/* Chipselect "set_cs" function could be defined by user. Example as the follow ... */

+/*

+static void spi_gpio_cs(struct jz47xx_spi_info *spi, int cs, int pol);

+{

+	int pinval;

+

+	switch(cs){

+	case 0:

+		pinval = 32*1+31;

+		break;

+	case 1:

+		pinval = 32*1+30;

+		break;

+	case 2:

+		pinval = 32*1+29;

+		break;

+	default:

+		pinval = 32*1+28;

+		break;	

+	}

+	__gpio_as_output(pinval);				

+	switch (pol) {

+	case BITBANG_CS_ACTIVE:

+		__gpio_set_pin(pinval);

+		break;

+	case BITBANG_CS_INACTIVE:

+		__gpio_clear_pin(pinval);

+		break;

+	}

+

+}*/

+

+#endif

diff --git a/arch/mips/include/asm/mach-jz4760b/board-altair.h b/arch/mips/include/asm/mach-jz4760b/board-altair.h
new file mode 100644
index 00000000000..0a46fda69b4
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4760b/board-altair.h
@@ -0,0 +1,216 @@
+/*
+ * linux/include/asm-mips/mach-jz4760b/board-altair.h
+ *
+ * JZ4760B-based ALTAIR board definition.
+ *
+ * Copyright (C) 2010 Ingenic Semiconductor Inc.
+ *
+ * Author: Jason<xwang@ingenic.cn>
+ *		Based on board-aquila.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_JZ4760B_ALTAIR_H__
+#define __ASM_JZ4760B_ALTAIR_H__
+
+/*======================================================================
+ * Frequencies of on-board oscillators
+ */
+#define JZ_EXTAL		12000000  /* Main extal freq:	24 MHz */
+#define JZ_EXTAL2		32768     /* RTC extal freq:	32.768 KHz */
+
+#define __GPIO(p, n) (32 * (p - 'A') + n)
+
+/*======================================================================
+ * SYSTEM GPIO
+ */
+#define GPIO_DISP_OFF_N		(32 * 3 + 17) /* GPD17 */
+
+#define GPIO_SD0_VCC_EN_N	(32 * 1 + 22) /* GPB22 */
+#define GPIO_SD0_WP_N		(32 * 1 + 23) /* GPB23 */
+#define GPIO_SD0_CD_N		(32 * 1 + 24) /* GPB24 */
+
+#define GPIO_SD1_VCC_EN_N	(32 * 1 + 2) /* GPB02 */
+#define GPIO_SD1_CD_N		(32 * 1 + 3) /* GPB03 */
+
+#define GPIO_USB_DETE		__GPIO('B', 4)
+
+#define GPIO_LCD_PWM		(32 * 4 + 1) /* GPE01 */
+
+#define GPIO_AMPEN_N		(32 * 4 + 11) /* GPE11 */
+
+#define GPIO_BOOT_SEL0		(32 * 3 + 17) /* GPD17 */
+#define GPIO_BOOT_SEL1		(32 * 3 + 18) /* GPD18 */
+#define GPIO_BOOT_SEL2		(32 * 3 + 19) /* GPD19 */
+
+#define GPIO_WM831x_DETECT      (32 * 1 + 5)  /* GPB5 */
+
+/*====================================================================
+ *  KEYPAD
+ */
+#define KEY_C0			(32 * 4 + 8) //GPE08
+#define KEY_C1                  (32 * 4 + 9) //GPE09
+#define KEY_C2                  (32 * 5 + 4) //GPF04
+#define KEY_C3                  (32 * 5 + 5) //GPF05
+#define KEY_C4                  (32 * 5 + 6) //GPF06
+
+#define KEY_R0			(32 * 5 + 7) //GPF07
+#define KEY_R1                  (32 * 5 + 8) //GPF08
+#define KEY_R2                  (32 * 5 + 9) //GPF09
+#define KEY_R3                  (32 * 5 + 10) //GPF10
+#define KEY_R4                  (32 * 5 + 11) //GPF11
+
+//keycode for android
+#define KEY_CENTER              232
+#define KEY_CALL                231
+#define KEY_POUND               228
+#define KEY_STAR                227
+
+/*======================================================================
+ * Analog input for VBAT is the battery voltage divided by CFG_PBAT_DIV.
+ */
+//#define CFG_PBAT_DIV            4
+
+/*
+ * M-T4D touchscreen
+ */
+#define LCD_INT			(32 * 0 + 16) /* GPA16 interrupt pin */
+#define LCD_INT_IRQ		(IRQ_GPIO_0 + LCD_INT)
+
+/* 
+ * E-Compass and G-Sensor
+ */
+#define COMPASS_RSTN	(32*3+5)	/* GPD5 */
+#define COMPASS_INTR	(32*3+4)	/* GPD4 */
+#define COMPASS_INT_IRQ	(IRQ_GPIO_0 + COMPASS_INTR)	/* irq number */
+
+#define SENSOR_INT1	(32*4+26)	/* GPE26 */
+#define SENSOR_INT2	(32*4+27)	/* GPE27 */
+#define SENSOR_INT1_IRQ	(IRQ_GPIO_0 + SENSOR_INT1)	/* irq number */
+
+/*
+ * Used for GPIO-based bitbanging I2C
+ */
+#define IOSWITCH_EN		(32*4+6)	/* GPE6 */
+#define CIM_I2C_SCK		(32*5+2)	/* GPF2 */
+#define CIM_I2C_SDA		(32*5+1)	/* GPF1 */
+
+
+/*======================================================================
+ * MMC/SD
+ */
+#define MSC1_HOTPLUG_PIN	GPIO_SD1_CD_N
+#define MSC1_HOTPLUG_IRQ	(IRQ_GPIO_0 + GPIO_SD1_CD_N)
+
+/*====================================================================== 
+ * Modem
+ */
+#if defined(CONFIG_GSM_IW368)
+#define GPIO_GSM_ONOFF          (32 * 1 + 25)
+#define GPIO_GSM_PWR_STATUS     (32 * 0 + 28)
+#define GPIO_GSM_RI             (32 * 3 + 8)  /* GPD08, waking cpu from sleep when a call comes in. */
+#define GPIO_GSM_RI_ACK         (32 * 0 + 29) /* GPA29, notify baseband not to send data to cpu when cpu is sleeping. */
+#define GPIO_GSM_WAKE           (32 * 1 + 27) /* GPB27 */
+#define GPIO_GSM_WAKE_ACK       (32 * 1 + 30) /* GPB30 */
+#endif
+
+#if defined(CONFIG_TDSCDMA_LC6311)
+#define GPIO_TD_POWERON        (32 * 3 + 9)
+#define GPIO_TD_RESET          (32 * 3 + 19)  /* shared with boot_sel2 */
+#endif
+
+/*======================================================================
+ * LCD backlight
+ */
+#define LCD_PWM_CHN		4	/* pwm channel */
+#define LCD_PWM_FULL		256
+#define PWM_BACKLIGHT_CHIP	0	/*0: digital pusle; 1: PWM*/
+
+#if 1 // temporarily
+#if PWM_BACKLIGHT_CHIP
+
+#define __lcd_init_backlight(n)					\
+do {								\
+} while (0)
+
+/* 100 level: 0,1,...,100 */
+#define __lcd_set_backlight_level(n)				\
+do {								\
+	__gpio_as_pwm(4);					\
+	__tcu_disable_pwm_output(LCD_PWM_CHN);			\
+	__tcu_stop_counter(LCD_PWM_CHN);			\
+	__tcu_init_pwm_output_high(LCD_PWM_CHN);		\
+	__tcu_set_pwm_output_shutdown_abrupt(LCD_PWM_CHN);	\
+	__tcu_select_clk_div1(LCD_PWM_CHN);			\
+	__tcu_mask_full_match_irq(LCD_PWM_CHN);			\
+	__tcu_mask_half_match_irq(LCD_PWM_CHN);			\
+	__tcu_set_count(LCD_PWM_CHN,0);				\
+	__tcu_set_full_data(LCD_PWM_CHN, __cpm_get_extalclk() / 30000);\
+	__tcu_set_half_data(LCD_PWM_CHN, __cpm_get_extalclk() / 30000 * n / (LCD_PWM_FULL - 1));\
+	__tcu_enable_pwm_output(LCD_PWM_CHN);			\
+	__tcu_select_extalclk(LCD_PWM_CHN);			\
+	__tcu_start_counter(LCD_PWM_CHN);			\
+} while (0)
+
+#define __lcd_close_backlight()					\
+do {								\
+	__gpio_as_output(GPIO_LCD_PWM);				\
+	__gpio_clear_pin(GPIO_LCD_PWM);				\
+} while (0)
+
+#else	/* PWM_BACKLIGHT_CHIP */
+
+#define __send_low_pulse(n)					\
+do {								\
+	unsigned int i;						\
+	for (i = n; i > 0; i--)	{				\
+		__gpio_clear_pin(GPIO_LCD_PWM);			\
+		udelay(1);					\
+		__gpio_set_pin(GPIO_LCD_PWM);			\
+		udelay(3);					\
+	}							\
+} while (0)
+
+#define MAX_BRIGHTNESS_STEP	16				/* RT9365 supports 16 brightness step */
+#define CONVERT_FACTOR		(256/MAX_BRIGHTNESS_STEP)	/* System support 256 brightness step */
+
+#define __lcd_init_backlight(n)					\
+do {								\
+	unsigned int tmp = (n)/CONVERT_FACTOR + 1;		\
+	__gpio_as_output(GPIO_LCD_PWM);				\
+	__gpio_set_pin(GPIO_LCD_PWM);				\
+	udelay(30);						\
+	__send_low_pulse(MAX_BRIGHTNESS_STEP-tmp);		\
+} while (0)
+
+#define __lcd_set_backlight_level(n)					\
+do {									\
+	unsigned int last = lcd_backlight_level / CONVERT_FACTOR + 1;	\
+	unsigned int tmp = (n) / CONVERT_FACTOR + 1;			\
+	if (tmp <= last) {						\
+		__send_low_pulse(last-tmp);				\
+	} else {							\
+		__send_low_pulse(last + MAX_BRIGHTNESS_STEP - tmp);	\
+	}								\
+	udelay(30);							\
+} while (0)
+
+#define __lcd_close_backlight()					\
+do {								\
+	__gpio_as_output(GPIO_LCD_PWM); 			\
+	__gpio_clear_pin(GPIO_LCD_PWM); 			\
+} while (0)
+
+#endif	/*PWM_BACKLIGHT_CHIP*/
+#endif  // if 0
+
+/*
+ * The key interrupt pin is low voltage or fall edge acitve
+ */
+#define ACTIVE_LOW_MSC0_CD	1 /* work when GPIO_SD1_CD_N is low */
+#define ACTIVE_LOW_MSC1_CD	0 /* work when GPIO_SD1_CD_N is low */
+
+#endif /* __ASM_JZ4760B_ALTAIR_H__ */
diff --git a/arch/mips/include/asm/mach-jz4760b/board-cygnus.h b/arch/mips/include/asm/mach-jz4760b/board-cygnus.h
new file mode 100644
index 00000000000..02d3b797863
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4760b/board-cygnus.h
@@ -0,0 +1,253 @@
+/*
+ * linux/include/asm-mips/mach-jz4760b/board-cygnus.h
+ *
+ * JZ4760B-based CYGNUS board ver 1.0 definition.
+ *
+ * Copyright (C) 2010 Ingenic Semiconductor Inc.
+ *
+ * Author: Jason<xwang@ingenic.cn>
+ *		Based on board-f4760b.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_JZ4760B_CYGNUS_H__
+#define __ASM_JZ4760B_CYGNUS_H__
+
+#define CYGNUS_CPU_V1_0          0
+
+/*======================================================================
+ * Frequencies of on-board oscillators
+ */
+#define JZ_EXTAL		12000000  /* Main extal freq:	12 MHz */
+#define JZ_EXTAL2		32768     /* RTC extal freq:	32.768 KHz */
+
+/*======================================================================
+ * SYSTEM GPIO
+ */
+
+#define GPIO_I2C1_SDA           (32*1+20)       /* GPB20 */
+#define GPIO_I2C1_SCK           (32*1+21)       /* GPB21 */
+
+#define GPIO_POWER_ON           (32 * 0 + 30)  /* GPA30 */
+#define GPIO_DISP_OFF_N		(32 * 4 + 11) /* GPE11 */ //???
+
+#define GPIO_SD0_VCC_EN_N	(32 * 4 + 2) /* GPE02 */
+#define GPIO_SD0_CD_N		(32 * 5 + 6) /* GPF06 */
+#define GPIO_SD0_WP_N		(32 * 1 + 8) /* GPB08 */
+#define GPIO_SD1_VCC_EN_N	(32 * 1 + 16) /* GPB16 */
+#define GPIO_SD1_CD_N		(32 * 1 + 15) /* GPB15 */
+#define GPIO_SD1_WP_N		(32 * 1 + 6) /* GPB06 */
+
+#define GPIO_USB_DETE		(32 * 4 + 19) /* GPE19 */
+
+#define GPIO_LCD_PWM		(32 * 4 + 1) /* GPE01 */
+//#define GPIO_LCD_VCC_EN_N       (32 * 1 + 31) /* GPB31 */
+
+#define GPIO_BOOT_SEL0		(32 * 3 + 17) /* GPD17 */
+#define GPIO_BOOT_SEL1		(32 * 3 + 18) /* GPD18 */
+#define GPIO_BOOT_SEL2		(32 * 3 + 19) /* GPD19 */
+
+/* Ethernet: WE#, RD#, CS5# */
+#define GPIO_NET_INT		(32 * 5 + 5)  /* GPF5 */
+
+#define GPIO_GSM_RI             (32 * 3 + 8) /* GPD08, waking cpu from sleep when a call comes in. */
+#define GPIO_GSM_RI_ACK         (32 * 0 + 29) /* GPA29, notify baseband not to send data to cpu when cpu is sleeping. */
+#define GPIO_GSM_WAKE           (32 * 1 + 27) /* GPB27 */
+#define GPIO_GSM_WAKE_ACK       (32 * 1 + 30) /* GPB30 */
+
+#define GPIO_WM831x_DETECT      (32 * 1 + 5)  /* GPB5 */
+
+/*====================================================================
+ *  KEYPAD
+ */
+#define KEY_C0			(32 * 4 + 8) //GPE08
+#define KEY_C1                  (32 * 4 + 9) //GPE09
+#define KEY_C2                  (32 * 5 + 4) //GPF04
+#define KEY_C3                  (32 * 5 + 5) //GPF05
+#define KEY_C4                  (32 * 5 + 6) //GPF06
+
+#define KEY_R0			(32 * 5 + 7) //GPF07
+#define KEY_R1                  (32 * 5 + 8) //GPF08
+#define KEY_R2                  (32 * 5 + 9) //GPF09
+#define KEY_R3                  (32 * 5 + 10) //GPF10
+#define KEY_R4                  (32 * 5 + 11) //GPF11
+
+//keycode for android
+#define KEY_CENTER              232
+#define KEY_CALL                231
+#define KEY_POUND               228
+#define KEY_STAR                227
+
+/*======================================================================
+ * Analog input for VBAT is the battery voltage divided by CFG_PBAT_DIV.
+ */
+//#define CFG_PBAT_DIV            4
+
+/*
+ * M-T4D touchscreen
+ */
+//#define LCD_INT		(32*2+20)	/* WAIT_N GPC20 interrupt pin */
+//#define IOSWITCH	(32*5+23)	/* GPF23 */
+
+
+/*======================================================================
+ * MMC/SD
+ */
+#define MSC0_WP_PIN		GPIO_SD0_WP_N
+#define MSC0_HOTPLUG_PIN	GPIO_SD0_CD_N
+#define MSC0_HOTPLUG_IRQ	(IRQ_GPIO_0 + GPIO_SD0_CD_N)
+
+#define MSC1_WP_PIN		GPIO_SD1_WP_N
+#define MSC1_HOTPLUG_PIN	GPIO_SD1_CD_N
+#define MSC1_HOTPLUG_IRQ	(IRQ_GPIO_0 + GPIO_SD1_CD_N)
+
+#define __msc0_init_io()			\
+do {						\
+	__gpio_as_output(GPIO_SD0_VCC_EN_N);	\
+	__gpio_as_input(GPIO_SD0_CD_N);		\
+} while (0)
+
+#define __msc0_enable_power()			\
+do {						\
+	__gpio_clear_pin(GPIO_SD0_VCC_EN_N);	\
+} while (0)
+
+#define __msc0_disable_power()			\
+do {						\
+	__gpio_set_pin(GPIO_SD0_VCC_EN_N);	\
+} while (0)
+
+#define __msc0_card_detected(s)			\
+({						\
+	int detected = 1;			\
+	if (__gpio_get_pin(GPIO_SD0_CD_N))	\
+		detected = 0;			\
+	detected;				\
+})
+
+#define __msc1_init_io()			\
+do {						\
+	__gpio_as_output(GPIO_SD1_VCC_EN_N);	\
+	__gpio_as_input(GPIO_SD1_CD_N);		\
+} while (0)
+
+#define __msc1_enable_power()			\
+do {						\
+	__gpio_clear_pin(GPIO_SD1_VCC_EN_N);	\
+} while (0)
+
+#define __msc1_disable_power()			\
+do {						\
+	__gpio_set_pin(GPIO_SD1_VCC_EN_N);	\
+} while (0)
+
+#define __msc1_card_detected(s)			\
+({						\
+	int detected = 1;			\
+	if (__gpio_get_pin(GPIO_SD1_CD_N))	\
+		detected = 0;			\
+	detected;				\
+})
+
+
+
+
+
+/*======================================================================
+ * LCD backlight
+ */
+#define LCD_PWM_CHN 4    /* pwm channel */
+#define LCD_PWM_FULL 256
+#define PWM_BACKLIGHT_CHIP	0	/*0: digital pusle; 1: PWM*/
+#define LCD_DEFAULT_BACKLIGHT		80
+#define LCD_MAX_BACKLIGHT		100
+#define LCD_MIN_BACKLIGHT		1
+
+#if 1
+#if PWM_BACKLIGHT_CHIP
+
+#define __lcd_init_backlight(n)					\
+do {								\
+} while (0)
+
+/* 100 level: 0,1,...,100 */
+#define __lcd_set_backlight_level(n)				\
+do {								\
+	__gpio_as_pwm(4);					\
+	__tcu_disable_pwm_output(LCD_PWM_CHN);			\
+	__tcu_stop_counter(LCD_PWM_CHN);			\
+	__tcu_init_pwm_output_high(LCD_PWM_CHN);		\
+	__tcu_set_pwm_output_shutdown_abrupt(LCD_PWM_CHN);	\
+	__tcu_select_clk_div1(LCD_PWM_CHN);			\
+	__tcu_mask_full_match_irq(LCD_PWM_CHN);			\
+	__tcu_mask_half_match_irq(LCD_PWM_CHN);			\
+	__tcu_set_count(LCD_PWM_CHN,0);				\
+	__tcu_set_full_data(LCD_PWM_CHN, __cpm_get_extalclk() / 30000);\
+	__tcu_set_half_data(LCD_PWM_CHN, __cpm_get_extalclk() / 30000 * n / (LCD_PWM_FULL - 1));\
+	__tcu_enable_pwm_output(LCD_PWM_CHN);			\
+	__tcu_select_extalclk(LCD_PWM_CHN);			\
+	__tcu_start_counter(LCD_PWM_CHN);			\
+} while (0)
+
+#define __lcd_close_backlight()					\
+do {								\
+	__gpio_as_output(GPIO_LCD_PWM);				\
+	__gpio_clear_pin(GPIO_LCD_PWM);				\
+} while (0)
+
+#else	/* PWM_BACKLIGHT_CHIP */
+
+#define __send_low_pulse(n)					\
+do {								\
+	unsigned int i;						\
+	for (i = n; i > 0; i--)	{				\
+		__gpio_clear_pin(GPIO_LCD_PWM);			\
+		udelay(1);					\
+		__gpio_set_pin(GPIO_LCD_PWM);			\
+		udelay(3);					\
+	}							\
+} while (0)
+
+#define MAX_BRIGHTNESS_STEP	16				/* RT9365 supports 16 brightness step */
+#define CONVERT_FACTOR		(256/MAX_BRIGHTNESS_STEP)	/* System support 256 brightness step */
+
+#define __lcd_init_backlight(n)					\
+do {								\
+	unsigned int tmp = (n)/CONVERT_FACTOR + 1;		\
+	__gpio_as_output(GPIO_LCD_PWM);				\
+	__gpio_set_pin(GPIO_LCD_PWM);				\
+	udelay(30);						\
+	__send_low_pulse(MAX_BRIGHTNESS_STEP-tmp);		\
+} while (0)
+
+#define __lcd_set_backlight_level(n)					\
+do {									\
+	unsigned int last = lcd_backlight_level / CONVERT_FACTOR + 1;	\
+	unsigned int tmp = (n) / CONVERT_FACTOR + 1;			\
+	if (tmp <= last) {						\
+		__send_low_pulse(last-tmp);				\
+	} else {							\
+		__send_low_pulse(last + MAX_BRIGHTNESS_STEP - tmp);	\
+	}								\
+	udelay(30);							\
+} while (0)
+
+#define __lcd_close_backlight()					\
+do {								\
+	__gpio_as_output(GPIO_LCD_PWM); 			\
+	__gpio_clear_pin(GPIO_LCD_PWM); 			\
+} while (0)
+
+#endif	/*PWM_BACKLIGHT_CHIP*/
+#endif  // if 0
+
+/*
+ * The key interrupt pin is low voltage or fall edge acitve
+ */
+#define ACTIVE_LOW_MSC0_CD	1 /* work when GPIO_SD1_CD_N is low */
+#define ACTIVE_LOW_MSC1_CD	0 /* work when GPIO_SD1_CD_N is low */
+
+#endif /* __ASM_JZ4760B_CYGNUS_H__ */
diff --git a/arch/mips/include/asm/mach-jz4760b/board-f4760.h b/arch/mips/include/asm/mach-jz4760b/board-f4760.h
new file mode 100644
index 00000000000..3ce71c58a70
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4760b/board-f4760.h
@@ -0,0 +1,93 @@
+/*
+ *  linux/include/asm-mips/mach-jz4760b/board-f4760b.h
+ *
+ *  JZ4760B-based F4760b board ver 1.x definition.
+ *
+ *  Copyright (C) 2008 Ingenic Semiconductor Inc.
+ *
+ *  Author: <cwjia@ingenic.cn>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_JZ4760B_F4760b_H__
+#define __ASM_JZ4760B_F4760b_H__
+
+#define CONFIG_FPGA	 /* fuwa is an FPGA board */
+
+/*====================================================================== 
+ * Frequencies of on-board oscillators
+ */
+#define JZ_EXTAL		24000000  /* Main extal freq: 12 MHz */
+#define JZ_EXTAL2		32768     /* RTC extal freq: 32.768 KHz */
+#define CFG_DIV		2	/* cpu/extclk; only for FPGA */
+
+/*====================================================================== 
+ * GPIO
+ */
+#define GPIO_SD_VCC_EN_N	113 /* GPD17 */
+#define GPIO_SD_CD_N		110 /* GPD14 */
+#define GPIO_SD_WP		112 /* GPD16 */
+#define GPIO_USB_DETE		102 /* GPD6 */
+#define GPIO_DC_DETE_N		103 /* GPD7 */
+#define GPIO_CHARG_STAT_N	111 /* GPD15 */
+#define GPIO_DISP_OFF_N		121 /* GPD25, LCD_REV */
+//#define GPIO_LED_EN       	124 /* GPD28 */
+
+#define GPIO_UDC_HOTPLUG	GPIO_USB_DETE
+
+/*====================================================================== 
+ * LCD backlight
+ */
+#define GPIO_LCD_PWM   		(32*4+4) /* GPE4 PWM4 */
+
+#define LCD_PWM_CHN 4    /* pwm channel */
+#define LCD_PWM_FULL 101
+/* 100 level: 0,1,...,100 */
+#define __lcd_set_backlight_level(n)	\
+do {					\
+	__gpio_as_output(GPIO_LCD_PWM);	\
+	__gpio_set_pin(GPIO_LCD_PWM);	\
+} while (0)
+
+#define __lcd_close_backlight()		\
+do {					\
+	__gpio_as_output(GPIO_LCD_PWM);	\
+	__gpio_clear_pin(GPIO_LCD_PWM);	\
+} while (0)
+
+/*====================================================================== 
+ * MMC/SD
+ */
+
+#define MSC_WP_PIN		GPIO_SD_WP
+#define MSC_HOTPLUG_PIN		GPIO_SD_CD_N
+#define MSC_HOTPLUG_IRQ		(IRQ_GPIO_0 + GPIO_SD_CD_N)
+
+#define __msc_init_io()				\
+do {						\
+	__gpio_as_output(GPIO_SD_VCC_EN_N);	\
+	__gpio_as_input(GPIO_SD_CD_N);		\
+} while (0)
+
+#define __msc_enable_power()			\
+do {						\
+	__gpio_clear_pin(GPIO_SD_VCC_EN_N);	\
+} while (0)
+
+#define __msc_disable_power()			\
+do {						\
+	__gpio_set_pin(GPIO_SD_VCC_EN_N);	\
+} while (0)
+
+#define __msc_card_detected(s)			\
+({						\
+	int detected = 1;			\
+	if (__gpio_get_pin(GPIO_SD_CD_N))	\
+		detected = 0;			\
+	detected;				\
+})
+
+#endif /* __ASM_JZ4760B_F4760b_H__ */
diff --git a/arch/mips/include/asm/mach-jz4760b/board-lepus.h b/arch/mips/include/asm/mach-jz4760b/board-lepus.h
new file mode 100644
index 00000000000..b3f6bdc6bfb
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4760b/board-lepus.h
@@ -0,0 +1,288 @@
+/*
+ * linux/include/asm-mips/mach-jz4760b/board-lepus.h
+ *
+ * JZ4760B-based LEPUS board ver 1.0 definition.
+ *
+ * Copyright (C) 2010 Ingenic Semiconductor Inc.
+ *
+ * Author: James<ljia@ingenic.cn>
+ *		Based on board-cygnus.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_JZ4760B_LEPUS_H__
+#define __ASM_JZ4760B_LEPUS_H__
+
+/*======================================================================
+ * Frequencies of on-board oscillators
+ */
+#define JZ_EXTAL		12000000  /* Main extal freq:	12 MHz */
+#define JZ_EXTAL2		32768     /* RTC extal freq:	32.768 KHz */
+
+/*======================================================================
+ * SYSTEM GPIO
+ */
+#define GPIO_DISP_OFF_N		(32 * 5 + 6) /* GPF6 */ //???
+
+#define GPIO_SD0_VCC_EN_N	(32 * 5 + 9)  /* GPF9 */
+#define GPIO_SD0_CD_N		(32 * 1 + 22) /* GPB22 */
+#define GPIO_SD0_WP_N		(32 * 5 + 4)  /* GPF4 */
+#define GPIO_SD1_VCC_EN_N	(32 * 4 + 9)  /* GPE9 */
+#define GPIO_SD1_CD_N		(32 * 0 + 28) /* GPA28 */
+
+#define GPIO_USB_DETE		(32 * 4 + 19) /* GPE19 */
+
+#define GPIO_LCD_PWM		(32 * 4 + 1) /* GPE01 */
+#define GPIO_LCD_VCC_EN_N       (32 * 1 + 31) /* GPB31 */
+
+#define GPIO_BOOT_SEL0		(32 * 3 + 17) /* GPD17 */
+#define GPIO_BOOT_SEL1		(32 * 3 + 18) /* GPD18 */
+#define GPIO_BOOT_SEL2		(32 * 3 + 19) /* GPD19 */
+
+/* Ethernet: WE#, RD#, CS5# */
+#define GPIO_NET_INT		(32 * 5 + 5)  /* GPF5 */
+
+#define GPIO_GSM_RI             (32 * 3 + 8) /* GPD08, waking cpu from sleep when a call comes in. */
+#define GPIO_GSM_RI_ACK         (32 * 0 + 29) /* GPA29, notify baseband not to send data to cpu when cpu is sleeping. */
+#define GPIO_GSM_WAKE           (32 * 1 + 27) /* GPB27 */
+#define GPIO_GSM_WAKE_ACK       (32 * 1 + 30) /* GPB30 */
+
+#define GPIO_POWER_ON           (32 * 0 + 30)  /* GPA30 */
+
+/*====================================================================
+ * GPIO KEYS and ADKEYS (GPIO_WAKEUP used for end call)
+ */
+#define GPIO_HOME		(32 * 2 + 29) // SW3-GPC29
+#define GPIO_MENU		(32 * 3 + 19) // SW6-boot_sel2-GPD19
+#define GPIO_CALL		(32 * 2 + 31) // SW1-GPC31
+#define GPIO_BACK		(32 * 3 + 27) // SW4-GPD27
+#define GPIO_ENDCALL    (32 * 0 + 30) // WAKEUP-GPA30
+#define GPIO_VOLUMEDOWN (32 * 3 + 18) // SW7-boot_sel1-GPD18
+#define GPIO_VOLUMEUP   (32 * 3 + 17) // SW8-boot_sel0-GPD17
+
+#define GPIO_ADKEY_INT	(32 * 4 + 8)  // GPE8
+
+/*====================================================================
+ *  ADKEYS LEVEL
+ */
+#define DPAD_LEFT_LEVEL		186 	//0.15V, 186=0.15/3.3*4096
+#define DPAD_DOWN_LEVEL		2482    //2.0V
+#define DPAD_UP_LEVEL		1985    //1.6V
+#define DPAD_CENTER_LEVEL	1489    //1.2V
+#define DPAD_RIGHT_LEVEL	868     //0.7V
+
+
+#define GPIO_TS_I2C_INT         (32 * 1 + 20)   //GPB20
+#define GPIO_TS_I2C_IRQ         (IRQ_GPIO_0 + GPIO_TS_I2C_INT)
+
+/*======================================================================
+ * Analog input for VBAT is the battery voltage divided by CFG_PBAT_DIV.
+ */
+//#define CFG_PBAT_DIV            4
+
+/*
+ * M-T4D touchscreen
+ */
+//#define LCD_INT		(32*2+20)	/* WAIT_N GPC20 interrupt pin */
+//#define IOSWITCH	(32*5+23)	/* GPF23 */
+
+
+/*======================================================================
+ * MMC/SD
+ */
+#define MSC0_WP_PIN		GPIO_SD0_WP_N
+#define MSC0_HOTPLUG_PIN	GPIO_SD0_CD_N
+#define MSC0_HOTPLUG_IRQ	(IRQ_GPIO_0 + GPIO_SD0_CD_N)
+
+#define MSC1_WP_PIN		GPIO_SD1_WP_N
+#define MSC1_HOTPLUG_PIN	GPIO_SD1_CD_N
+#define MSC1_HOTPLUG_IRQ	(IRQ_GPIO_0 + GPIO_SD1_CD_N)
+
+#define __msc0_init_io()			\
+do {						\
+	__gpio_as_output(GPIO_SD0_VCC_EN_N);	\
+	__gpio_as_input(GPIO_SD0_CD_N);		\
+} while (0)
+
+#define __msc0_enable_power()			\
+do {						\
+	__gpio_clear_pin(GPIO_SD0_VCC_EN_N);	\
+} while (0)
+
+#define __msc0_disable_power()			\
+do {						\
+	__gpio_set_pin(GPIO_SD0_VCC_EN_N);	\
+} while (0)
+
+#define __msc0_card_detected(s)			\
+({						\
+	int detected = 1;			\
+	if (__gpio_get_pin(GPIO_SD0_CD_N))	\
+		detected = 0;			\
+	detected;				\
+})
+
+#define __msc1_init_io()			\
+do {						\
+	__gpio_as_output(GPIO_SD1_VCC_EN_N);	\
+	__gpio_as_input(GPIO_SD1_CD_N);		\
+} while (0)
+
+#define __msc1_enable_power()			\
+do {						\
+	__gpio_clear_pin(GPIO_SD1_VCC_EN_N);	\
+} while (0)
+
+#define __msc1_disable_power()			\
+do {						\
+	__gpio_set_pin(GPIO_SD1_VCC_EN_N);	\
+} while (0)
+
+#define __msc1_card_detected(s)			\
+({						\
+	int detected = 1;			\
+	if (__gpio_get_pin(GPIO_SD1_CD_N))	\
+		detected = 0;			\
+	detected;				\
+})
+
+/*======================================================================
+ * LCD backlight
+ */
+#define LCD_PWM_CHN 1   /* pwm channel */
+#define LCD_PWM_FULL 256
+#define PWM_BACKLIGHT_CHIP	0	/*0: digital pusle; 1: PWM*/
+#define LCD_DEFAULT_BACKLIGHT		80
+#define LCD_MAX_BACKLIGHT		100
+#define LCD_MIN_BACKLIGHT		1
+
+#if 1
+#if PWM_BACKLIGHT_CHIP
+
+#define __lcd_init_backlight(n)					\
+do {    							\
+	__lcd_set_backlight_level(n);				\
+} while (0)
+
+/* 100 level: 0,1,...,100 */
+#define __lcd_set_backlight_level(n)				\
+do {								\
+	__gpio_as_pwm(1);                               \
+	__tcu_disable_pwm_output(LCD_PWM_CHN);			\
+	__tcu_stop_counter(LCD_PWM_CHN);			\
+	__tcu_init_pwm_output_high(LCD_PWM_CHN);		\
+	__tcu_set_pwm_output_shutdown_abrupt(LCD_PWM_CHN);	\
+	__tcu_select_clk_div1(LCD_PWM_CHN);			\
+	__tcu_mask_full_match_irq(LCD_PWM_CHN);			\
+	__tcu_mask_half_match_irq(LCD_PWM_CHN);			\
+	__tcu_clear_counter_to_zero(LCD_PWM_CHN);		\
+	__tcu_set_full_data(LCD_PWM_CHN, JZ_EXTAL / 30000);	\
+	__tcu_set_half_data(LCD_PWM_CHN, JZ_EXTAL / 30000 * n / LCD_PWM_FULL); \
+	__tcu_enable_pwm_output(LCD_PWM_CHN);			\
+	__tcu_select_extalclk(LCD_PWM_CHN);			\
+	__tcu_start_counter(LCD_PWM_CHN);			\
+} while (0)
+
+#define __lcd_close_backlight()					\
+do {								\
+	__gpio_as_output(GPIO_LCD_PWM);				\
+	__gpio_clear_pin(GPIO_LCD_PWM);				\
+} while (0)
+
+#else	/* PWM_BACKLIGHT_CHIP */
+
+#define __send_low_pulse(n)					\
+do {								\
+	unsigned int i;						\
+	for (i = n; i > 0; i--)	{				\
+		__gpio_clear_pin(GPIO_LCD_PWM);			\
+		udelay(1);					\
+		__gpio_set_pin(GPIO_LCD_PWM);			\
+		udelay(3);					\
+	}							\
+} while (0)
+
+#define MAX_BRIGHTNESS_STEP	16				/* RT9365 supports 16 brightness step */
+#define CONVERT_FACTOR		(256/MAX_BRIGHTNESS_STEP)	/* System support 256 brightness step */
+
+#define __lcd_init_backlight(n)					\
+do {								\
+	unsigned int tmp = (n)/CONVERT_FACTOR + 1;		\
+	__gpio_as_output(GPIO_LCD_PWM);				\
+	__gpio_set_pin(GPIO_LCD_PWM);				\
+	udelay(30);						\
+	__send_low_pulse(MAX_BRIGHTNESS_STEP-tmp);		\
+} while (0)
+
+#define __lcd_set_backlight_level(n)					\
+do {									\
+	unsigned int last = lcd_backlight_level / CONVERT_FACTOR + 1;	\
+	unsigned int tmp = (n) / CONVERT_FACTOR + 1;			\
+	if (tmp <= last) {						\
+		__send_low_pulse(last-tmp);				\
+	} else {							\
+		__send_low_pulse(last + MAX_BRIGHTNESS_STEP - tmp);	\
+	}								\
+	udelay(30);							\
+} while (0)
+
+#define __lcd_close_backlight()					\
+do {								\
+	__gpio_as_output(GPIO_LCD_PWM); 			\
+	__gpio_clear_pin(GPIO_LCD_PWM); 			\
+} while (0)
+
+#endif	/*PWM_BACKLIGHT_CHIP*/
+#endif  // if 0
+
+/*
+ * The key interrupt pin is low voltage or fall edge acitve
+ */
+#define ACTIVE_LOW_HOME		1
+#define ACTIVE_LOW_MENU		1
+#define ACTIVE_LOW_BACK		1
+#define ACTIVE_LOW_CALL		1
+#define ACTIVE_LOW_ENDCALL  1
+#define ACTIVE_LOW_VOLUMEDOWN   1
+#define ACTIVE_LOW_VOLUMEUP     1
+#define ACTIVE_LOW_ADKEY	1
+#define ACTIVE_LOW_WAKE_UP 	1
+#define ACTIVE_LOW_MSC0_CD	1
+#define ACTIVE_LOW_MSC1_CD	1
+
+/* mplayer keys */
+#define GPIO_MP_VOLUMEUP	(32 * 2 + 29) // SW3-GPC29
+#define GPIO_MP_VOLUMEDOWN	(32 * 2 + 31) // SW1-GPC31
+#define GPIO_MP_MUTE		(32 * 3 + 19) // SW6-boot_sel2-GPD19
+#define GPIO_MP_PAUSE		(32 * 3 + 27) // SW4-GPD27
+#define GPIO_MP_PLAY		(32 * 0 + 30) // SW9-WAKEUP-GPA30
+#define GPIO_MP_REWIND		(32 * 3 + 18) // SW7-boot_sel1-GPD18
+#define GPIO_MP_FORWARD		(32 * 3 + 17) // SW8-boot_sel0-GPD17
+
+#define ACTIVE_LOW_MUTE		1
+#define ACTIVE_LOW_PUASE	1
+#define ACTIVE_LOW_PLAY		1
+#define ACTIVE_LOW_REWIND	1
+#define ACTIVE_LOW_FORWARD	1
+
+
+#define GPIO_SW3	(32 * 2 + 29) // SW3-GPC29
+#define GPIO_SW1	(32 * 2 + 31) // SW1-GPC31
+#define GPIO_SW6	(32 * 3 + 19) // SW6-boot_sel2-GPD19
+#define GPIO_SW4	(32 * 3 + 27) // SW4-GPD27
+#define GPIO_SW9	(32 * 0 + 30) // SW9-WAKEUP-GPA30
+#define GPIO_SW7	(32 * 3 + 18) // SW7-boot_sel1-GPD18
+#define GPIO_SW8	(32 * 3 + 17) // SW8-boot_sel0-GPD17
+
+#define ACTIVE_LOW_SW3		1
+#define ACTIVE_LOW_SW1		1
+#define ACTIVE_LOW_SW6		1
+#define ACTIVE_LOW_SW4		1
+#define ACTIVE_LOW_SW9		1
+#define ACTIVE_LOW_SW7   	1
+#define ACTIVE_LOW_SW8     	1
+
+#endif /* __ASM_JZ4760B_LEPUS_H__ */
diff --git a/arch/mips/include/asm/mach-jz4760b/dma.h b/arch/mips/include/asm/mach-jz4760b/dma.h
new file mode 100644
index 00000000000..b30ce3aa46c
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4760b/dma.h
@@ -0,0 +1,338 @@
+/*
+ *  linux/include/asm-mips/mach-jz4760b/dma.h
+ *
+ *  JZ4760B DMA definition.
+ *
+ *  Copyright (C) 2008 Ingenic Semiconductor Inc.
+ *
+ *  Author: <cwjia@ingenic.cn>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_JZ4760B_DMA_H__
+#define __ASM_JZ4760B_DMA_H__
+
+#include <linux/interrupt.h>
+#include <asm/io.h>			/* need byte IO */
+#include <linux/spinlock.h>		/* And spinlocks */
+#include <linux/delay.h>
+#include <asm/system.h>
+
+/*
+ * Descriptor structure for JZ4760B DMA engine
+ * Note: this structure must always be aligned to a 16-bytes boundary.
+ */
+
+/* old descriptor 4-word */
+typedef struct {
+	volatile u32 dcmd;	/* DCMD value for the current transfer */
+	volatile u32 dsadr;	/* DSAR value for the current transfer */
+	volatile u32 dtadr;	/* DTAR value for the current transfer */
+	volatile u32 ddadr;	/* Points to the next descriptor + transfer count */
+} jz_dma_desc;
+
+/* new descriptor 8-word */
+typedef struct {
+	volatile u32 dcmd;	/* DCMD value for the current transfer */
+	volatile u32 dsadr;	/* DSAR value for the current transfer */
+	volatile u32 dtadr;	/* DTAR value for the current transfer */
+	volatile u32 ddadr;	/* Points to the next descriptor + transfer count */
+	volatile u32 dstrd;     /* DMA source and target stride address */
+	volatile u32 dreqt;     /* DMA request type for current transfer */
+	volatile u32 reserved0;	/* Reserved */
+	volatile u32 reserved1;	/* Reserved */
+} jz_dma_desc_8word;
+
+/* new descriptor 8-word */
+typedef struct {
+	volatile u32 dcmd;	/* DCMD value for the current transfer */
+	volatile u32 dsadr;	/* DSAR value for the current transfer */
+	volatile u32 dtadr;	/* DTAR value for the current transfer */
+	volatile u32 dcnt;	/* transfer count */
+	volatile u32 dstrd; /* DMA source and target stride address */
+	volatile u32 dreqt; /* DMA request type for current transfer */
+	volatile u32 dnt;	/* NAND detect timer enable(15) and value(0~5), and Tail counter(22~16)*/
+	volatile u32 ddadr;	/* Next descriptor address(31~4)  */
+} jz_bdma_desc_8word;
+
+/* DMA Device ID's follow */
+enum {
+	DMA_ID_AUTO = 0,		/* Auto-request */
+//	DMA_ID_TSSI_RX,		/* TSSI receive fifo full request */
+	DMA_ID_UART3_TX,	/* UART3 transmit-fifo-empty request */
+	DMA_ID_UART3_RX,	/* UART3 receve-fifo-full request */
+	DMA_ID_UART2_TX,	/* UART2 transmit-fifo-empty request */
+	DMA_ID_UART2_RX,	/* UART2 receve-fifo-full request */
+	DMA_ID_UART1_TX,	/* UART1 transmit-fifo-empty request */
+	DMA_ID_UART1_RX,	/* UART1 receve-fifo-full request */
+	DMA_ID_UART0_TX,	/* UART0 transmit-fifo-empty request */
+	DMA_ID_UART0_RX,	/* UART0 receve-fifo-full request */
+	DMA_ID_SSI0_TX,		/* SSI0 transmit-fifo-full request */
+	DMA_ID_SSI0_RX,		/* SSI0 receive-fifo-empty request */
+	DMA_ID_AIC_TX,		/* AIC transmit-fifo-full request */
+	DMA_ID_AIC_RX,		/* AIC receive-fifo-empty request */
+	DMA_ID_MSC0,
+	DMA_ID_MSC0_TX,	      /* for compitable with SD8686 */
+	DMA_ID_MSC0_RX,	      /* for compitable with SD8686 */
+	DMA_ID_TCU_OVERFLOW,	/* TCU channel n overflow interrupt */
+	DMA_ID_SADC,		/* SADC transfer request */
+	DMA_ID_MSC1,
+	DMA_ID_MSC1_TX,	      /* for compitable with SD8686 */
+	DMA_ID_MSC1_RX,	      /* for compitable with SD8686 */
+	DMA_ID_MSC2,
+	DMA_ID_MSC2_TX,	      /* for compitable with SD8686 */
+	DMA_ID_MSC2_RX,	      /* for compitable with SD8686 */
+	DMA_ID_SSI1_TX,		/* SSI1 transmit-fifo-full request */
+	DMA_ID_SSI1_RX,		/* SSI1 receive-fifo-empty request */
+	DMA_ID_PCM_TX,		/* PM transmit-fifo-full request */
+	DMA_ID_PCM_RX,		/* PM receive-fifo-empty request */
+	DMA_ID_RAW_SET,
+	DMA_ID_AX88796C_RX,
+	DMA_ID_AX88796C_TX,
+	DMA_ID_I2C0_RX,
+	DMA_ID_I2C0_TX,
+	DMA_ID_I2C1_RX,
+	DMA_ID_I2C1_TX,
+	DMA_ID_I2C2_RX,
+	DMA_ID_I2C2_TX,
+	DMA_ID_MAX
+};
+
+/* DMA modes, simulated by sw */
+#define DMA_MODE_READ	0x0  /* I/O to memory, no autoinit, increment, single mode */
+#define DMA_MODE_WRITE	0x1  /* memory to I/O, no autoinit, increment, single mode */
+#define DMA_AUTOINIT	0x2
+#define DMA_MODE_MASK	0x3
+
+struct jz_dma_chan {
+	int dev_id;	/* DMA ID: this channel is allocated if >=0, free otherwise */
+	unsigned int io;        /* DMA channel number */
+	const char *dev_str;    /* string describes the DMA channel */
+	int irq;                /* DMA irq number */
+	void *irq_dev;          /* DMA private device structure */
+	unsigned int fifo_addr; /* physical fifo address of the requested device */
+	unsigned int cntl;	/* DMA controll */
+	unsigned int mode;      /* DMA configuration */
+	unsigned int source;    /* DMA request source */
+};
+
+extern struct jz_dma_chan jz_dma_table[];
+
+
+#define DMA_8BIT_RX_CMD					\
+	DMAC_DCMD_DAI |					\
+	DMAC_DCMD_SWDH_8 | DMAC_DCMD_DWDH_32 |		\
+	DMAC_DCMD_DS_8BIT | DMAC_DCMD_RDIL_IGN
+
+#define DMA_8BIT_TX_CMD					\
+	DMAC_DCMD_SAI |					\
+	DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_8 |		\
+	DMAC_DCMD_DS_8BIT | DMAC_DCMD_RDIL_IGN
+
+#define DMA_16BIT_RX_CMD				\
+	DMAC_DCMD_DAI |					\
+	DMAC_DCMD_SWDH_16 | DMAC_DCMD_DWDH_32 |		\
+	DMAC_DCMD_DS_16BIT | DMAC_DCMD_RDIL_IGN
+
+#define DMA_16BIT_TX_CMD				\
+	DMAC_DCMD_SAI |					\
+	DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_16 |		\
+	DMAC_DCMD_DS_16BIT | DMAC_DCMD_RDIL_IGN
+
+#define DMA_32BIT_RX_CMD				\
+	DMAC_DCMD_DAI |					\
+	DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 |		\
+	DMAC_DCMD_DS_32BIT | DMAC_DCMD_RDIL_IGN
+
+#define DMA_32BIT_TX_CMD				\
+	DMAC_DCMD_SAI |					\
+	DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 |		\
+	DMAC_DCMD_DS_32BIT | DMAC_DCMD_RDIL_IGN
+
+#define DMA_16BYTE_RX_CMD				\
+	DMAC_DCMD_DAI |					\
+	DMAC_DCMD_SWDH_8 | DMAC_DCMD_DWDH_32 |		\
+	DMAC_DCMD_DS_16BYTE | DMAC_DCMD_RDIL_IGN
+
+#define DMA_16BYTE_TX_CMD				\
+	DMAC_DCMD_SAI |					\
+	DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_8 |		\
+	DMAC_DCMD_DS_16BYTE | DMAC_DCMD_RDIL_IGN
+
+#define DMA_32BYTE_RX_CMD				\
+	DMAC_DCMD_DAI |					\
+	DMAC_DCMD_SWDH_8 | DMAC_DCMD_DWDH_32 |		\
+	DMAC_DCMD_DS_32BYTE | DMAC_DCMD_RDIL_IGN
+
+#define DMA_32BYTE_TX_CMD				\
+	DMAC_DCMD_SAI |					\
+	DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_8 |		\
+	DMAC_DCMD_DS_32BYTE | DMAC_DCMD_RDIL_IGN
+
+#define DMA_AIC_32_32BYTE_TX_CMD		       	\
+	DMAC_DCMD_SAI |					\
+	DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 |		\
+	DMAC_DCMD_DS_32BYTE | DMAC_DCMD_RDIL_IGN
+#define DMA_AIC_32_16BYTE_TX_CMD		       	\
+	DMAC_DCMD_SAI |					\
+	DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 |		\
+	DMAC_DCMD_DS_16BYTE | DMAC_DCMD_RDIL_IGN
+
+#define DMA_AIC_32_16BYTE_RX_CMD			\
+	DMAC_DCMD_DAI |					\
+	DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 |		\
+	DMAC_DCMD_DS_16BYTE | DMAC_DCMD_RDIL_IGN
+
+#define DMA_AIC_16BIT_TX_CMD				\
+	DMAC_DCMD_SAI |					\
+	DMAC_DCMD_SWDH_16 | DMAC_DCMD_DWDH_16 |		\
+	DMAC_DCMD_DS_16BIT | DMAC_DCMD_RDIL_IGN
+
+#define DMA_AIC_16BIT_RX_CMD				\
+	DMAC_DCMD_DAI |					\
+	DMAC_DCMD_SWDH_16 | DMAC_DCMD_DWDH_16 |		\
+	DMAC_DCMD_DS_16BIT | DMAC_DCMD_RDIL_IGN
+
+#define DMA_AIC_16BYTE_RX_CMD				\
+	DMAC_DCMD_DAI |					\
+	DMAC_DCMD_SWDH_16 | DMAC_DCMD_DWDH_16 |		\
+	DMAC_DCMD_DS_16BYTE | DMAC_DCMD_RDIL_IGN
+
+#define DMA_AIC_16BYTE_TX_CMD				\
+	DMAC_DCMD_SAI |					\
+	DMAC_DCMD_SWDH_16 | DMAC_DCMD_DWDH_16 |		\
+	DMAC_DCMD_DS_16BYTE | DMAC_DCMD_RDIL_IGN
+
+#define DMA_AIC_16BYTE_TX_CMD_UC			\
+	DMAC_DCMD_SAI |					\
+	DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_16 |		\
+	DMAC_DCMD_DS_16BYTE | DMAC_DCMD_RDIL_IGN
+
+#define DMA_AIC_TX_CMD_UNPACK				\
+	DMAC_DCMD_SAI |					\
+	DMAC_DCMD_SWDH_16 | DMAC_DCMD_DWDH_16 |		\
+	DMAC_DCMD_DS_32BIT | DMAC_DCMD_RDIL_IGN
+
+#define DMA_AIC_TX_CMD_PACK				\
+	DMAC_DCMD_SAI |					\
+	DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 |		\
+	DMAC_DCMD_DS_32BIT | DMAC_DCMD_RDIL_IGN
+
+extern int jz_request_dma(int dev_id,
+			  const char *dev_str,
+			  irqreturn_t (*irqhandler)(int, void *),
+			  unsigned long irqflags,
+			  void *irq_dev_id);
+extern void jz_free_dma(unsigned int dmanr);
+
+extern int jz_dma_read_proc(char *buf, char **start, off_t fpos,
+			      int length, int *eof, void *data);
+extern void dump_jz_dma_channel(unsigned int dmanr);
+extern void dump_jz_bdma_channel(unsigned int dmanr);
+
+extern void enable_dma(unsigned int dmanr);
+extern void disable_dma(unsigned int dmanr);
+extern void set_dma_addr(unsigned int dmanr, unsigned int phyaddr);
+extern void set_dma_count(unsigned int dmanr, unsigned int bytecnt);
+extern void set_dma_mode(unsigned int dmanr, unsigned int mode);
+extern void jz_set_oss_dma(unsigned int dmanr, unsigned int mode, unsigned int audio_fmt);
+extern void jz_set_alsa_dma(unsigned int dmanr, unsigned int mode, unsigned int audio_fmt);
+extern void jz_set_dma_src_width(int dmanr, int nbit);
+extern void jz_set_dma_dest_width(int dmanr, int nbit);
+extern void jz_set_dma_block_size(int dmanr, int nbyte);
+extern unsigned int get_dma_residue(unsigned int dmanr);
+extern spinlock_t  dma_spin_lock;
+
+static __inline__ unsigned long claim_dma_lock(void)
+{
+	unsigned long flags;
+	spin_lock_irqsave(&dma_spin_lock, flags);
+	return flags;
+}
+
+static __inline__ void release_dma_lock(unsigned long flags)
+{
+	spin_unlock_irqrestore(&dma_spin_lock, flags);
+}
+
+/* Clear the 'DMA Pointer Flip Flop'.
+ * Write 0 for LSB/MSB, 1 for MSB/LSB access.
+ */
+#define clear_dma_ff(channel)
+
+static __inline__ struct jz_dma_chan *get_dma_chan(unsigned int dmanr)
+{
+	if (dmanr > MAX_DMA_NUM
+	    || jz_dma_table[dmanr].dev_id < 0)
+		return NULL;
+	return &jz_dma_table[dmanr];
+}
+
+static __inline__ int dma_halted(unsigned int dmanr)
+{
+	struct jz_dma_chan *chan = get_dma_chan(dmanr);
+	if (!chan)
+		return 1;
+	return  __dmac_channel_transmit_halt_detected(dmanr) ? 1 : 0;
+}
+
+static __inline__ unsigned int get_dma_mode(unsigned int dmanr)
+{
+	struct jz_dma_chan *chan = get_dma_chan(dmanr);
+	if (!chan)
+		return 0;
+	return chan->mode;
+}
+
+static __inline__ void clear_dma_done(unsigned int dmanr)
+{
+	struct jz_dma_chan *chan = get_dma_chan(dmanr);
+	if (!chan)
+		return;
+	REG_DMAC_DCCSR(chan->io) &= ~(DMAC_DCCSR_HLT | DMAC_DCCSR_TT | DMAC_DCCSR_AR);
+}
+
+static __inline__ void clear_dma_halt(unsigned int dmanr)
+{
+	struct jz_dma_chan *chan = get_dma_chan(dmanr);
+	if (!chan)
+		return;
+	REG_DMAC_DCCSR(chan->io) &= ~(DMAC_DCCSR_HLT);
+	REG_DMAC_DMACR((chan->io)/HALF_DMA_NUM) &= ~(DMAC_DMACR_HLT);
+}
+
+static __inline__ void clear_dma_flag(unsigned int dmanr)
+{
+	struct jz_dma_chan *chan = get_dma_chan(dmanr);
+	if (!chan)
+		return;
+	REG_DMAC_DCCSR(chan->io) &= ~(DMAC_DCCSR_HLT | DMAC_DCCSR_TT | DMAC_DCCSR_AR);
+	REG_DMAC_DMACR((chan->io)/HALF_DMA_NUM) &= ~(DMAC_DMACR_HLT | DMAC_DMACR_AR);
+}
+
+static __inline__ void set_dma_page(unsigned int dmanr, char pagenr)
+{
+}
+
+static __inline__ unsigned int get_dma_done_status(unsigned int dmanr)
+{
+	unsigned long dccsr;
+	struct jz_dma_chan *chan = get_dma_chan(dmanr);
+	if (!chan)
+		return 0;
+	dccsr = REG_DMAC_DCCSR(chan->io);
+	return dccsr & (DMAC_DCCSR_HLT | DMAC_DCCSR_TT | DMAC_DCCSR_AR);
+}
+
+static __inline__ int get_dma_done_irq(unsigned int dmanr)
+{
+	struct jz_dma_chan *chan = get_dma_chan(dmanr);
+	if (!chan)
+		return -1;
+	return chan->irq;
+}
+
+#endif  /* __ASM_JZ4760B_DMA_H__ */
diff --git a/arch/mips/include/asm/mach-jz4760b/irq.h b/arch/mips/include/asm/mach-jz4760b/irq.h
new file mode 100644
index 00000000000..0b7c1105134
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4760b/irq.h
@@ -0,0 +1,21 @@
+/*
+ *  linux/arch/mips/include/asm/mach-jz4760b/irq.h
+ *
+ *  JZ4760B IRQ definition.
+ *
+ *  Copyright (C) 2010 Ingenic Semiconductor Inc.
+ *
+ *  Author: <yliu@ingenic.cn>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_JZ4760B_IRQ_H__
+#define __ASM_JZ4760B_IRQ_H__
+
+/* we need 256 irq levels at least */
+#define NR_IRQS	256
+
+#endif
diff --git a/arch/mips/include/asm/mach-jz4760b/jz4760b.h b/arch/mips/include/asm/mach-jz4760b/jz4760b.h
new file mode 100644
index 00000000000..55072d3f650
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4760b/jz4760b.h
@@ -0,0 +1,95 @@
+/*
+ *  linux/include/asm-mips/mach-jz4760b/jz4760b.h
+ *
+ *  JZ4760B common definition.
+ *
+ *  Copyright (C) 2008 Ingenic Semiconductor Inc.
+ *
+ *  Author: <cwjia@ingenic.cn>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_JZ4760B_H__
+#define __ASM_JZ4760B_H__
+
+#include <asm/mach-jz4760b/regs.h>
+
+#include <asm/mach-jz4760b/jz4760bmisc.h>
+#include <asm/mach-jz4760b/jz4760bgpio.h>
+#include <asm/mach-jz4760b/jz4760bdmac.h>
+#include <asm/mach-jz4760b/jz4760bintc.h>
+#include <asm/mach-jz4760b/jz4760baic.h>
+#include <asm/mach-jz4760b/jz4760bbch.h>
+#include <asm/mach-jz4760b/jz4760bbdma.h>
+#include <asm/mach-jz4760b/jz4760bcim.h>
+#include <asm/mach-jz4760b/jz4760bcpm.h>
+#include <asm/mach-jz4760b/jz4760bddrc.h>
+#include <asm/mach-jz4760b/jz4760bemc.h>
+#include <asm/mach-jz4760b/jz4760bi2c.h>
+#include <asm/mach-jz4760b/jz4760bipu.h>
+#include <asm/mach-jz4760b/jz4760blcdc.h>
+#include <asm/mach-jz4760b/jz4760bmc.h>
+#include <asm/mach-jz4760b/jz4760bmdma.h>
+#include <asm/mach-jz4760b/jz4760bme.h>
+#include <asm/mach-jz4760b/jz4760bmsc.h>
+#include <asm/mach-jz4760b/jz4760bnemc.h>
+#include <asm/mach-jz4760b/jz4760botg.h>
+#include <asm/mach-jz4760b/jz4760botp.h>
+#include <asm/mach-jz4760b/jz4760bowi.h>
+#include <asm/mach-jz4760b/jz4760bpcm.h>
+#include <asm/mach-jz4760b/jz4760brtc.h>
+#include <asm/mach-jz4760b/jz4760bsadc.h>
+#include <asm/mach-jz4760b/jz4760bscc.h>
+#include <asm/mach-jz4760b/jz4760bssi.h>
+#include <asm/mach-jz4760b/jz4760btcu.h>
+#include <asm/mach-jz4760b/jz4760btssi.h>
+#include <asm/mach-jz4760b/jz4760btve.h>
+#include <asm/mach-jz4760b/jz4760buart.h>
+#include <asm/mach-jz4760b/jz4760bwdt.h>
+#include <asm/mach-jz4760b/jz4760bost.h>
+
+#include <asm/mach-jz4760b/dma.h>
+#include <asm/mach-jz4760b/misc.h>
+#include <asm/mach-jz4760b/platform.h>
+
+/*------------------------------------------------------------------
+ * Platform definitions
+ */
+
+#define JZ_SOC_NAME "JZ4760B"
+
+#ifdef CONFIG_JZ4750_FUWA
+#include <asm/mach-jz4750/board-fuwa.h>
+#endif
+
+#ifdef CONFIG_JZ4760B_F4760b
+#include <asm/mach-jz4760b/board-f4760b.h>
+#endif
+
+#ifdef CONFIG_JZ4760B_CYGNUS
+#include <asm/mach-jz4760b/board-cygnus.h>
+#endif
+
+#ifdef CONFIG_JZ4760B_LEPUS
+#include <asm/mach-jz4760b/board-lepus.h>
+#endif
+
+#ifdef CONFIG_JZ4760B_ALTAIR
+#include <asm/mach-jz4760b/board-altair.h>
+#endif
+
+/* Add other platform definition here ... */
+
+
+/*------------------------------------------------------------------
+ * Follows are related to platform definitions
+ */
+
+//#include <asm/mach-jz4760b/clock.h>
+#include <asm/mach-jz4760b/serial.h>
+#include <asm/mach-jz4760b/spi.h>
+
+#endif /* __ASM_JZ4760B_H__ */
diff --git a/arch/mips/include/asm/mach-jz4760b/jz4760baic.h b/arch/mips/include/asm/mach-jz4760b/jz4760baic.h
new file mode 100644
index 00000000000..d15e090728a
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4760b/jz4760baic.h
@@ -0,0 +1,764 @@
+/*

+ * chip-aic.h

+ * JZ4760B AIC register definition

+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

+ *

+ * Author: whxu@ingenic.cn

+ */

+

+#ifndef __CHIP_AIC_H__

+#define __CHIP_AIC_H__

+

+

+/*

+ * AC97 and I2S controller module(AIC) address definition

+ */

+#define	AIC_BASE	0xb0020000

+

+

+/*

+ * AIC registers offset address definition

+ */

+#define AIC_FR_OFFSET		(0x00)

+#define AIC_CR_OFFSET		(0x04)

+#define AIC_ACCR1_OFFSET	(0x08)

+#define AIC_ACCR2_OFFSET	(0x0c)

+#define AIC_I2SCR_OFFSET	(0x10)

+#define AIC_SR_OFFSET		(0x14)

+#define AIC_ACSR_OFFSET		(0x18)

+#define AIC_I2SSR_OFFSET	(0x1c)

+#define AIC_ACCAR_OFFSET	(0x20)

+#define AIC_ACCDR_OFFSET	(0x24)

+#define AIC_ACSAR_OFFSET	(0x28)

+#define AIC_ACSDR_OFFSET	(0x2c)

+#define AIC_I2SDIV_OFFSET	(0x30)

+#define AIC_DR_OFFSET		(0x34)

+

+#define SPDIF_ENA_OFFSET	(0x80)

+#define SPDIF_CTRL_OFFSET	(0x84)

+#define SPDIF_STATE_OFFSET	(0x88)

+#define SPDIF_CFG1_OFFSET	(0x8c)

+#define SPDIF_CFG2_OFFSET	(0x90)

+#define SPDIF_FIFO_OFFSET	(0x94)

+

+#define ICDC_RGADW_OFFSET	(0xa4)

+#define ICDC_RGDATA_OFFSET	(0xa8)

+

+

+/*

+ * AIC registers address definition

+ */

+#define AIC_FR		(AIC_BASE + AIC_FR_OFFSET)

+#define AIC_CR		(AIC_BASE + AIC_CR_OFFSET)

+#define AIC_ACCR1	(AIC_BASE + AIC_ACCR1_OFFSET)

+#define AIC_ACCR2	(AIC_BASE + AIC_ACCR2_OFFSET)

+#define AIC_I2SCR	(AIC_BASE + AIC_I2SCR_OFFSET)

+#define AIC_SR		(AIC_BASE + AIC_SR_OFFSET)

+#define AIC_ACSR	(AIC_BASE + AIC_ACSR_OFFSET)

+#define AIC_I2SSR	(AIC_BASE + AIC_I2SSR_OFFSET)

+#define AIC_ACCAR	(AIC_BASE + AIC_ACCAR_OFFSET)

+#define AIC_ACCDR	(AIC_BASE + AIC_ACCDR_OFFSET)

+#define AIC_ACSAR	(AIC_BASE + AIC_ACSAR_OFFSET)

+#define AIC_ACSDR	(AIC_BASE + AIC_ACSDR_OFFSET)

+#define AIC_I2SDIV	(AIC_BASE + AIC_I2SDIV_OFFSET)

+#define AIC_DR		(AIC_BASE + AIC_DR_OFFSET)

+

+#define SPDIF_ENA	(AIC_BASE + SPDIF_ENA_OFFSET)

+#define SPDIF_CTRL	(AIC_BASE + SPDIF_CTRL_OFFSET)

+#define SPDIF_STATE	(AIC_BASE + SPDIF_STATE_OFFSET)

+#define SPDIF_CFG1	(AIC_BASE + SPDIF_CFG1_OFFSET)

+#define SPDIF_CFG2	(AIC_BASE + SPDIF_CFG2_OFFSET)

+#define SPDIF_FIFO	(AIC_BASE + SPDIF_FIFO_OFFSET)

+

+#define ICDC_RGADW	(AIC_BASE + ICDC_RGADW_OFFSET)

+#define ICDC_RGDATA	(AIC_BASE + ICDC_RGDATA_OFFSET)

+

+

+/*

+ * AIC registers common define

+ */

+

+/* AIC controller configuration register(AICFR) */

+#define	AIC_FR_LSMP		BIT6

+#define	AIC_FR_ICDC		BIT5

+#define	AIC_FR_AUSEL		BIT4

+#define	AIC_FR_RST		BIT3

+#define	AIC_FR_BCKD		BIT2

+#define	AIC_FR_SYNCD		BIT1

+#define	AIC_FR_ENB		BIT0

+

+#define	AIC_FR_RFTH_LSB		24

+#define	AIC_FR_RFTH_MASK	BITS_H2L(27, AIC_FR_RFTH_LSB)

+

+#define	AIC_FR_TFTH_LSB		16

+#define	AIC_FR_TFTH_MASK	BITS_H2L(20, AIC_FR_TFTH_LSB)

+

+/* AIC controller common control register(AICCR) */

+#define AIC_CR_PACK16		BIT28

+#define	AIC_CR_RDMS		BIT15

+#define	AIC_CR_TDMS		BIT14

+#define	AIC_CR_M2S		BIT11

+#define	AIC_CR_ENDSW		BIT10

+#define	AIC_CR_AVSTSU		BIT9

+#define	AIC_CR_TFLUSH		BIT8

+#define	AIC_CR_RFLUSH		BIT7

+#define	AIC_CR_EROR		BIT6

+#define	AIC_CR_ETUR		BIT5

+#define	AIC_CR_ERFS		BIT4

+#define	AIC_CR_ETFS		BIT3

+#define	AIC_CR_ENLBF		BIT2

+#define	AIC_CR_ERPL		BIT1

+#define	AIC_CR_EREC		BIT0

+

+#define AIC_CR_CHANNEL_LSB	24

+#define AIC_CR_CHANNEL_MASK	BITS_H2L(26, AIC_CR_CHANNEL_LSB)

+

+#define	AIC_CR_OSS_LSB		19

+#define	AIC_CR_OSS_MASK		BITS_H2L(21, AIC_CR_OSS_LSB)

+ #define AIC_CR_OSS(n)		(((n) > 18 ? (n)/6 : (n)/9) << AIC_CR_OSS_LSB)	/* n = 8, 16, 18, 20, 24 */

+

+#define	AIC_CR_ISS_LSB		16

+#define	AIC_CR_ISS_MASK		BITS_H2L(18, AIC_CR_ISS_LSB)

+ #define AIC_CR_ISS(n)		(((n) > 18 ? (n)/6 : (n)/9) << AIC_CR_ISS_LSB)	/* n = 8, 16, 18, 20, 24 */

+

+/* AIC controller AC-link control register 1(ACCR1) */

+#define AIC_ACCR1_RS_LSB	16

+#define	AIC_ACCR1_RS_MASK	BITS_H2L(25, AIC_ACCR1_RS_LSB)

+ #define AIC_ACCR1_RS_SLOT(n)	((1 << ((n) - 3)) << AIC_ACCR1_RS_LSB)	/* n = 3 .. 12 */

+

+#define AIC_ACCR1_XS_LSB	0

+#define	AIC_ACCR1_XS_MASK	BITS_H2L(9, AIC_ACCR1_XS_LSB)

+ #define AIC_ACCR1_XS_SLOT(n)	((1 << ((n) - 3)) << AIC_ACCR1_XS_LSB)	/* n = 3 .. 12 */

+

+/* AIC controller AC-link control register 2 (ACCR2) */

+#define	AIC_ACCR2_ERSTO		BIT18

+#define	AIC_ACCR2_ESADR		BIT17

+#define	AIC_ACCR2_ECADT		BIT16

+#define	AIC_ACCR2_SO		BIT3

+#define	AIC_ACCR2_SR		BIT2

+#define	AIC_ACCR2_SS		BIT1

+#define	AIC_ACCR2_SA		BIT0

+

+/* AIC controller i2s/msb-justified control register (I2SCR) */

+#define	AIC_I2SCR_RFIRST	BIT17

+#define	AIC_I2SCR_SWLH   	BIT16

+#define	AIC_I2SCR_STPBK		BIT12

+#define AIC_I2SCR_ESCLK		BIT4

+#define	AIC_I2SCR_AMSL		BIT0

+

+/* AIC controller FIFO status register (AICSR) */

+#define	AIC_SR_ROR		BIT6

+#define	AIC_SR_TUR		BIT5

+#define	AIC_SR_RFS		BIT4

+#define	AIC_SR_TFS		BIT3

+

+#define	AIC_SR_RFL_LSB		24

+#define	AIC_SR_RFL_MASK		BITS_H2L(29, AIC_SR_RFL_LSB)

+

+#define	AIC_SR_TFL_LSB		8

+#define	AIC_SR_TFL_MASK		BITS_H2L(13, AIC_SR_TFL_LSB)

+

+/* AIC controller AC-link status register (ACSR) */

+#define	AIC_ACSR_SLTERR		BIT21

+#define	AIC_ACSR_CRDY		BIT20

+#define	AIC_ACSR_CLPM		BIT19

+#define	AIC_ACSR_RSTO		BIT18

+#define	AIC_ACSR_SADR		BIT17

+#define	AIC_ACSR_CADT		BIT16

+

+/* AIC controller I2S/MSB-justified status register (I2SSR) */

+#define	AIC_I2SSR_CHBSY		BIT5

+#define	AIC_I2SSR_TBSY		BIT4

+#define	AIC_I2SSR_RBSY		BIT3

+#define	AIC_I2SSR_BSY		BIT2

+

+/* AIC controller AC97 codec command address register (ACCAR) */

+#define	AIC_ACCAR_CAR_LSB	0

+#define	AIC_ACCAR_CAR_MASK	BITS_H2L(19, AIC_ACCAR_CAR_LSB)

+

+

+/* AIC controller AC97 codec command data register (ACCDR) */

+#define	AIC_ACCDR_CDR_LSB	0

+#define	AIC_ACCDR_CDR_MASK	BITS_H2L(19, AIC_ACCDR_CDR_LSB)

+

+/* AC97 read and write macro based on ACCAR and ACCDR */

+#define AC97_READ_CMD		BIT19

+#define AC97_WRITE_CMD		(BIT19 & ~BIT19)

+

+#define AC97_INDEX_LSB		12

+#define AC97_INDEX_MASK		BITS_H2L(18, AC97_INDEX_LSB)

+

+#define AC97_DATA_LSB		4

+#define AC97_DATA_MASK		BITS_H2L(19, AC97_DATA_LSB)

+

+/* AIC controller AC97 codec status address register (ACSAR) */

+#define	AIC_ACSAR_SAR_LSB	0

+#define	AIC_ACSAR_SAR_MASK	BITS_H2L(19, AIC_ACSAR_SAR_LSB)

+

+/* AIC controller AC97 codec status data register (ACSDR) */

+#define	AIC_ACSDR_SDR_LSB	0

+#define	AIC_ACSDR_SDR_MASK	BITS_H2L(19, AIC_ACSDR_SDR_LSB)

+

+/* AIC controller I2S/MSB-justified clock divider register (I2SDIV) */

+#define	AIC_I2SDIV_DIV_LSB	0

+#define	AIC_I2SDIV_DIV_MASK	BITS_H2L(3, AIC_I2SDIV_DIV_LSB)

+

+/* SPDIF enable register (SPDIF_ENA) */

+#define SPDIF_ENA_SPEN		BIT0

+

+/* SPDIF control register (SPDIF_CTRL) */

+#define SPDIF_CTRL_DMAEN        BIT15

+#define SPDIF_CTRL_DTYPE        BIT14

+#define SPDIF_CTRL_SIGN         BIT13

+#define SPDIF_CTRL_INVALID      BIT12

+#define SPDIF_CTRL_RST          BIT11

+#define SPDIF_CTRL_SPDIFI2S     BIT10

+#define SPDIF_CTRL_MTRIG        BIT1

+#define SPDIF_CTRL_MFFUR        BIT0

+

+/* SPDIF state register (SPDIF_STAT) */

+#define SPDIF_STAT_BUSY		BIT7

+#define SPDIF_STAT_FTRIG	BIT1

+#define SPDIF_STAT_FUR		BIT0

+

+#define SPDIF_STAT_FLVL_LSB	8

+#define SPDIF_STAT_FLVL_MASK	BITS_H2L(14, SPDIF_STAT_FLVL_LSB)

+

+/* SPDIF configure 1 register (SPDIF_CFG1) */

+#define SPDIF_CFG1_INITLVL	BIT17

+#define SPDIF_CFG1_ZROVLD	BIT16

+

+#define SPDIF_CFG1_TRIG_LSB	12

+#define SPDIF_CFG1_TRIG_MASK	BITS_H2L(13, SPDIF_CFG1_TRIG_LSB)

+#define SPDIF_CFG1_TRIG(n)	(((n) > 16 ? 3 : (n)/8) << SPDIF_CFG1_TRIG_LSB)	/* n = 4, 8, 16, 32 */

+

+#define SPDIF_CFG1_SRCNUM_LSB	8

+#define SPDIF_CFG1_SRCNUM_MASK	BITS_H2L(11, SPDIF_CFG1_SRCNUM_LSB)

+

+#define SPDIF_CFG1_CH1NUM_LSB	4

+#define SPDIF_CFG1_CH1NUM_MASK	BITS_H2L(7, SPDIF_CFG1_CH1NUM_LSB)

+

+#define SPDIF_CFG1_CH2NUM_LSB	0

+#define SPDIF_CFG1_CH2NUM_MASK	BITS_H2L(3, SPDIF_CFG1_CH2NUM_LSB)

+

+/* SPDIF configure 2 register (SPDIF_CFG2) */

+#define SPDIF_CFG2_MAXWL	BIT18

+#define SPDIF_CFG2_PRE		BIT3

+#define SPDIF_CFG2_COPYN	BIT2

+#define SPDIF_CFG2_AUDION	BIT1

+#define SPDIF_CFG2_CONPRO	BIT0

+

+#define SPDIF_CFG2_FS_LSB	26

+#define SPDIF_CFG2_FS_MASK	BITS_H2L(29, SPDIF_CFG2_FS_LSB)

+

+#define SPDIF_CFG2_ORGFRQ_LSB	22

+#define SPDIF_CFG2_ORGFRQ_MASK	BITS_H2L(25, SPDIF_CFG2_ORGFRQ_LSB)

+

+#define SPDIF_CFG2_SAMWL_LSB	19

+#define SPDIF_CFG2_SAMWL_MASK	BITS_H2L(21, SPDIF_CFG2_SAMWL_LSB)

+

+#define SPDIF_CFG2_CLKACU_LSB	16

+#define SPDIF_CFG2_CLKACU_MASK	BITS_H2L(17, SPDIF_CFG2_CLKACU_LSB)

+

+#define SPDIF_CFG2_CATCODE_LSB	8

+#define SPDIF_CFG2_CATCODE_MASK	BITS_H2L(15, SPDIF_CFG2_CATCODE_LSB)

+

+#define SPDIF_CFG2_CHMD_LSB	6

+#define SPDIF_CFG2_CHMD_MASK	BITS_H2L(7, SPDIF_CFG2_CHMD_LSB)

+

+/* ICDC internal register access control register(RGADW) */

+#define ICDC_RGADW_RGWR		BIT16

+

+#define ICDC_RGADW_RGADDR_LSB	8

+#define	ICDC_RGADW_RGADDR_MASK	BITS_H2L(14, ICDC_RGADW_RGADDR_LSB)

+

+#define ICDC_RGADW_RGDIN_LSB	0

+#define	ICDC_RGADW_RGDIN_MASK	BITS_H2L(7, ICDC_RGADW_RGDIN_LSB)

+

+/* ICDC internal register data output register (RGDATA)*/

+#define ICDC_RGDATA_IRQ		BIT8

+

+#define ICDC_RGDATA_RGDOUT_LSB	0

+#define ICDC_RGDATA_RGDOUT_MASK	BITS_H2L(7, ICDC_RGDATA_RGDOUT_LSB)

+

+

+#ifndef __MIPS_ASSEMBLER

+

+

+#define	REG_AIC_FR		REG32(AIC_FR)

+#define	REG_AIC_CR		REG32(AIC_CR)

+#define	REG_AIC_ACCR1		REG32(AIC_ACCR1)

+#define	REG_AIC_ACCR2		REG32(AIC_ACCR2)

+#define	REG_AIC_I2SCR		REG32(AIC_I2SCR)

+#define	REG_AIC_SR		REG32(AIC_SR)

+#define	REG_AIC_ACSR		REG32(AIC_ACSR)

+#define	REG_AIC_I2SSR		REG32(AIC_I2SSR)

+#define	REG_AIC_ACCAR		REG32(AIC_ACCAR)

+#define	REG_AIC_ACCDR		REG32(AIC_ACCDR)

+#define	REG_AIC_ACSAR		REG32(AIC_ACSAR)

+#define	REG_AIC_ACSDR		REG32(AIC_ACSDR)

+#define	REG_AIC_I2SDIV		REG32(AIC_I2SDIV)

+#define	REG_AIC_DR		REG32(AIC_DR)

+

+#define REG_SPDIF_ENA		REG32(SPDIF_ENA)

+#define REG_SPDIF_CTRL		REG32(SPDIF_CTRL)

+#define REG_SPDIF_STATE		REG32(SPDIF_STATE)

+#define REG_SPDIF_CFG1		REG32(SPDIF_CFG1)

+#define REG_SPDIF_CFG2		REG32(SPDIF_CFG2)

+#define REG_SPDIF_FIFO		REG32(SPDIF_FIFO)

+

+#define	REG_ICDC_RGADW		REG32(ICDC_RGADW)

+#define	REG_ICDC_RGDATA		REG32(ICDC_RGDATA)

+

+

+#define __aic_enable()		( REG_AIC_FR |= AIC_FR_ENB )

+#define __aic_disable()		( REG_AIC_FR &= ~AIC_FR_ENB )

+

+#define __aic_select_ac97()	( REG_AIC_FR &= ~AIC_FR_AUSEL )

+#define __aic_select_i2s()	( REG_AIC_FR |= AIC_FR_AUSEL )

+

+#define __aic_play_zero()	( REG_AIC_FR &= ~AIC_FR_LSMP )

+#define __aic_play_lastsample()	( REG_AIC_FR |= AIC_FR_LSMP )

+

+#define __i2s_as_master()	( REG_AIC_FR |= AIC_FR_BCKD | AIC_FR_SYNCD )

+#define __i2s_as_slave()	( REG_AIC_FR &= ~(AIC_FR_BCKD | AIC_FR_SYNCD) )

+#define __aic_reset_status()          ( REG_AIC_FR & AIC_FR_RST )

+

+#define __aic_reset()                                   \

+do {                                                    \

+        REG_AIC_FR |= AIC_FR_RST;                       \

+} while(0)

+

+

+#define __aic_set_transmit_trigger(n) 			\

+do {							\

+	REG_AIC_FR &= ~AIC_FR_TFTH_MASK;		\

+	REG_AIC_FR |= ((n) << AIC_FR_TFTH_LSB);		\

+} while(0)

+

+#define __aic_set_receive_trigger(n) 			\

+do {							\

+	REG_AIC_FR &= ~AIC_FR_RFTH_MASK;		\

+	REG_AIC_FR |= ((n) << AIC_FR_RFTH_LSB);		\

+} while(0)

+

+#define __aic_enable_oldstyle()

+#define __aic_enable_newstyle()

+#define __aic_enable_pack16()   ( REG_AIC_CR |= AIC_CR_PACK16 )

+#define __aic_enable_unpack16() ( REG_AIC_CR &= ~AIC_CR_PACK16)

+

+/* n = AIC_CR_CHANNEL_MONO,AIC_CR_CHANNEL_STEREO ... */

+#define __aic_out_channel_select(n)                    \

+do {                                                   \

+	REG_AIC_CR &= ~AIC_CR_CHANNEL_MASK;            \

+        REG_AIC_CR |= ((n) << AIC_CR_CHANNEL_LSB );			       \

+} while(0)

+

+#define __aic_enable_record()	( REG_AIC_CR |= AIC_CR_EREC )

+#define __aic_disable_record()	( REG_AIC_CR &= ~AIC_CR_EREC )

+#define __aic_enable_replay()	( REG_AIC_CR |= AIC_CR_ERPL )

+#define __aic_disable_replay()	( REG_AIC_CR &= ~AIC_CR_ERPL )

+#define __aic_enable_loopback()	( REG_AIC_CR |= AIC_CR_ENLBF )

+#define __aic_disable_loopback() ( REG_AIC_CR &= ~AIC_CR_ENLBF )

+

+#define __aic_flush_tfifo()	( REG_AIC_CR |= AIC_CR_TFLUSH )

+#define __aic_unflush_tfifo()	( REG_AIC_CR &= ~AIC_CR_TFLUSH )

+#define __aic_flush_rfifo()	( REG_AIC_CR |= AIC_CR_RFLUSH )

+#define __aic_unflush_rfifo()	( REG_AIC_CR &= ~AIC_CR_RFLUSH )

+

+#define __aic_enable_transmit_intr() \

+  ( REG_AIC_CR |= (AIC_CR_ETFS | AIC_CR_ETUR) )

+#define __aic_disable_transmit_intr() \

+  ( REG_AIC_CR &= ~(AIC_CR_ETFS | AIC_CR_ETUR) )

+#define __aic_enable_receive_intr() \

+  ( REG_AIC_CR |= (AIC_CR_ERFS | AIC_CR_EROR) )

+#define __aic_disable_receive_intr() \

+  ( REG_AIC_CR &= ~(AIC_CR_ERFS | AIC_CR_EROR) )

+

+#define __aic_enable_transmit_dma()  ( REG_AIC_CR |= AIC_CR_TDMS )

+#define __aic_disable_transmit_dma() ( REG_AIC_CR &= ~AIC_CR_TDMS )

+#define __aic_enable_receive_dma()   ( REG_AIC_CR |= AIC_CR_RDMS )

+#define __aic_disable_receive_dma()  ( REG_AIC_CR &= ~AIC_CR_RDMS )

+

+#define __aic_enable_mono2stereo()   ( REG_AIC_CR |= AIC_CR_M2S )

+#define __aic_disable_mono2stereo()  ( REG_AIC_CR &= ~AIC_CR_M2S )

+#define __aic_enable_byteswap()      ( REG_AIC_CR |= AIC_CR_ENDSW )

+#define __aic_disable_byteswap()     ( REG_AIC_CR &= ~AIC_CR_ENDSW )

+#define __aic_enable_unsignadj()     ( REG_AIC_CR |= AIC_CR_AVSTSU )

+#define __aic_disable_unsignadj()    ( REG_AIC_CR &= ~AIC_CR_AVSTSU )

+

+#define AC97_PCM_XS_L_FRONT   	AIC_ACCR1_XS_SLOT(3)

+#define AC97_PCM_XS_R_FRONT   	AIC_ACCR1_XS_SLOT(4)

+#define AC97_PCM_XS_CENTER    	AIC_ACCR1_XS_SLOT(6)

+#define AC97_PCM_XS_L_SURR    	AIC_ACCR1_XS_SLOT(7)

+#define AC97_PCM_XS_R_SURR    	AIC_ACCR1_XS_SLOT(8)

+#define AC97_PCM_XS_LFE       	AIC_ACCR1_XS_SLOT(9)

+

+#define AC97_PCM_RS_L_FRONT   	AIC_ACCR1_RS_SLOT(3)

+#define AC97_PCM_RS_R_FRONT   	AIC_ACCR1_RS_SLOT(4)

+#define AC97_PCM_RS_CENTER    	AIC_ACCR1_RS_SLOT(6)

+#define AC97_PCM_RS_L_SURR    	AIC_ACCR1_RS_SLOT(7)

+#define AC97_PCM_RS_R_SURR    	AIC_ACCR1_RS_SLOT(8)

+#define AC97_PCM_RS_LFE       	AIC_ACCR1_RS_SLOT(9)

+

+#define __ac97_set_xs_none()	( REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK )

+#define __ac97_set_xs_mono() 						\

+do {									\

+	REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK;				\

+	REG_AIC_ACCR1 |= AC97_PCM_XS_R_FRONT;				\

+} while(0)

+#define __ac97_set_xs_stereo() 						\

+do {									\

+	REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK;				\

+	REG_AIC_ACCR1 |= AC97_PCM_XS_L_FRONT | AC97_PCM_XS_R_FRONT;	\

+} while(0)

+

+/* In fact, only stereo is support now. */

+#define __ac97_set_rs_none()	( REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK )

+#define __ac97_set_rs_mono() 						\

+do {									\

+	REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK;				\

+	REG_AIC_ACCR1 |= AC97_PCM_RS_R_FRONT;				\

+} while(0)

+#define __ac97_set_rs_stereo() 						\

+do {									\

+	REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK;				\

+	REG_AIC_ACCR1 |= AC97_PCM_RS_L_FRONT | AC97_PCM_RS_R_FRONT;	\

+} while(0)

+

+#define __ac97_warm_reset_codec()		\

+ do {						\

+	REG_AIC_ACCR2 |= AIC_ACCR2_SA;		\

+	REG_AIC_ACCR2 |= AIC_ACCR2_SS;		\

+	udelay(2);				\

+	REG_AIC_ACCR2 &= ~AIC_ACCR2_SS;		\

+	REG_AIC_ACCR2 &= ~AIC_ACCR2_SA;		\

+ } while (0)

+

+#define __ac97_cold_reset_codec()		\

+ do {						\

+	REG_AIC_ACCR2 |=  AIC_ACCR2_SR;		\

+	udelay(2);				\

+	REG_AIC_ACCR2 &= ~AIC_ACCR2_SR;		\

+ } while (0)

+

+/* n=8,16,18,20 */

+#define __ac97_set_iass(n) \

+ ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_IASS_MASK) | AIC_ACCR2_IASS_##n##BIT )

+#define __ac97_set_oass(n) \

+ ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_OASS_MASK) | AIC_ACCR2_OASS_##n##BIT )

+

+/* This bit should only be set in 2 channels configuration */

+#define __i2s_send_rfirst()   ( REG_AIC_I2SCR |= AIC_I2SCR_RFIRST )  /* RL */

+#define __i2s_send_lfirst()   ( REG_AIC_I2SCR &= ~AIC_I2SCR_RFIRST ) /* LR */

+

+/* This bit should only be set in 2 channels configuration and 16bit-packed mode */

+#define __i2s_switch_lr()     ( REG_AIC_I2SCR |= AIC_I2SCR_SWLH )

+#define __i2s_unswitch_lr()   ( REG_AIC_I2SCR &= ~AIC_I2SCR_SWLH )

+

+#define __i2s_select_i2s()            ( REG_AIC_I2SCR &= ~AIC_I2SCR_AMSL )

+#define __i2s_select_msbjustified()   ( REG_AIC_I2SCR |= AIC_I2SCR_AMSL )

+

+/* n=8,16,18,20,24 */

+/*#define __i2s_set_sample_size(n) \

+ ( REG_AIC_I2SCR |= (REG_AIC_I2SCR & ~AIC_I2SCR_WL_MASK) | AIC_I2SCR_WL_##n##BIT )*/

+

+#define __i2s_out_channel_select(n) __aic_out_channel_select(n)

+

+#define __i2s_set_oss_sample_size(n) \

+ ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_OSS_MASK) | AIC_CR_OSS(n))

+#define __i2s_set_iss_sample_size(n) \

+ ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_ISS_MASK) | AIC_CR_ISS(n))

+

+#define __i2s_stop_bitclk()   ( REG_AIC_I2SCR |= AIC_I2SCR_STPBK )

+#define __i2s_start_bitclk()  ( REG_AIC_I2SCR &= ~AIC_I2SCR_STPBK )

+

+#define __aic_transmit_request()  ( REG_AIC_SR & AIC_SR_TFS )

+#define __aic_receive_request()   ( REG_AIC_SR & AIC_SR_RFS )

+#define __aic_transmit_underrun() ( REG_AIC_SR & AIC_SR_TUR )

+#define __aic_receive_overrun()   ( REG_AIC_SR & AIC_SR_ROR )

+

+#define __aic_clear_errors()      ( REG_AIC_SR &= ~(AIC_SR_TUR | AIC_SR_ROR) )

+

+#define __aic_get_transmit_resident() \

+  ( (REG_AIC_SR & AIC_SR_TFL_MASK) >> AIC_SR_TFL_LSB )

+#define __aic_get_receive_count() \

+  ( (REG_AIC_SR & AIC_SR_RFL_MASK) >> AIC_SR_RFL_LSB )

+

+#define __ac97_command_transmitted()     ( REG_AIC_ACSR & AIC_ACSR_CADT )

+#define __ac97_status_received()         ( REG_AIC_ACSR & AIC_ACSR_SADR )

+#define __ac97_status_receive_timeout()  ( REG_AIC_ACSR & AIC_ACSR_RSTO )

+#define __ac97_codec_is_low_power_mode() ( REG_AIC_ACSR & AIC_ACSR_CLPM )

+#define __ac97_codec_is_ready()          ( REG_AIC_ACSR & AIC_ACSR_CRDY )

+#define __ac97_slot_error_detected()     ( REG_AIC_ACSR & AIC_ACSR_SLTERR )

+#define __ac97_clear_slot_error()        ( REG_AIC_ACSR &= ~AIC_ACSR_SLTERR )

+

+#define __i2s_is_busy()         ( REG_AIC_I2SSR & AIC_I2SSR_BSY )

+

+#define __ac97_out_rcmd_addr(reg) 					\

+do { 									\

+    REG_AIC_ACCAR = AC97_READ_CMD | ((reg) << AC97_INDEX_LSB); 	\

+} while (0)

+

+#define __ac97_out_wcmd_addr(reg) 					\

+do { 									\

+    REG_AIC_ACCAR = AC97_WRITE_CMD | ((reg) << AC97_INDEX_LSB); 	\

+} while (0)

+

+#define __ac97_out_data(value) 						\

+do { 									\

+    REG_AIC_ACCDR = ((value) << AC97_DATA_LSB); 			\

+} while (0)

+

+#define __ac97_in_data() \

+ ( (REG_AIC_ACSDR & CODEC_REG_DATA_MASK) >> AC97_DATA_LSB )

+

+#define __ac97_in_status_addr() \

+ ( (REG_AIC_ACSAR & AC97_INDEX_MASK) >> AC97_INDEX_LSB )

+

+#define __i2s_set_sample_rate(i2sclk, sync) \

+  ( REG_AIC_I2SDIV = ((i2sclk) / (4*64)) / (sync) )

+

+#define __aic_write_tfifo(v)  ( REG_AIC_DR = (v) )

+#define __aic_read_rfifo()    ( REG_AIC_DR )

+

+#define __aic_internal_codec()  ( REG_AIC_FR |= AIC_FR_ICDC )

+#define __aic_external_codec()  ( REG_AIC_FR &= ~AIC_FR_ICDC )

+

+//

+// Define next ops for AC97 compatible

+//

+

+#define AC97_ACSR	AIC_ACSR

+

+#define __ac97_enable()		__aic_enable(); __aic_select_ac97()

+#define __ac97_disable()	__aic_disable()

+#define __ac97_reset()		__aic_reset()

+

+#define __ac97_set_transmit_trigger(n)	__aic_set_transmit_trigger(n)

+#define __ac97_set_receive_trigger(n)	__aic_set_receive_trigger(n)

+

+#define __ac97_enable_record()		__aic_enable_record()

+#define __ac97_disable_record()		__aic_disable_record()

+#define __ac97_enable_replay()		__aic_enable_replay()

+#define __ac97_disable_replay()		__aic_disable_replay()

+#define __ac97_enable_loopback()	__aic_enable_loopback()

+#define __ac97_disable_loopback()	__aic_disable_loopback()

+

+#define __ac97_enable_transmit_dma()	__aic_enable_transmit_dma()

+#define __ac97_disable_transmit_dma()	__aic_disable_transmit_dma()

+#define __ac97_enable_receive_dma()	__aic_enable_receive_dma()

+#define __ac97_disable_receive_dma()	__aic_disable_receive_dma()

+

+#define __ac97_transmit_request()	__aic_transmit_request()

+#define __ac97_receive_request()	__aic_receive_request()

+#define __ac97_transmit_underrun()	__aic_transmit_underrun()

+#define __ac97_receive_overrun()	__aic_receive_overrun()

+

+#define __ac97_clear_errors()		__aic_clear_errors()

+

+#define __ac97_get_transmit_resident()	__aic_get_transmit_resident()

+#define __ac97_get_receive_count()	__aic_get_receive_count()

+

+#define __ac97_enable_transmit_intr()	__aic_enable_transmit_intr()

+#define __ac97_disable_transmit_intr()	__aic_disable_transmit_intr()

+#define __ac97_enable_receive_intr()	__aic_enable_receive_intr()

+#define __ac97_disable_receive_intr()	__aic_disable_receive_intr()

+

+#define __ac97_write_tfifo(v)		__aic_write_tfifo(v)

+#define __ac97_read_rfifo()		__aic_read_rfifo()

+

+//

+// Define next ops for I2S compatible

+//

+

+#define I2S_ACSR	AIC_I2SSR

+

+#define __i2s_enable()		 __aic_enable(); __aic_select_i2s()

+#define __i2s_disable()		__aic_disable()

+#define __i2s_reset()		__aic_reset()

+

+#define __i2s_set_transmit_trigger(n)	__aic_set_transmit_trigger(n)

+#define __i2s_set_receive_trigger(n)	__aic_set_receive_trigger(n)

+

+#define __i2s_enable_record()		__aic_enable_record()

+#define __i2s_disable_record()		__aic_disable_record()

+#define __i2s_enable_replay()		__aic_enable_replay()

+#define __i2s_disable_replay()		__aic_disable_replay()

+#define __i2s_enable_loopback()		__aic_enable_loopback()

+#define __i2s_disable_loopback()	__aic_disable_loopback()

+

+#define __i2s_enable_transmit_dma()	__aic_enable_transmit_dma()

+#define __i2s_disable_transmit_dma()	__aic_disable_transmit_dma()

+#define __i2s_enable_receive_dma()	__aic_enable_receive_dma()

+#define __i2s_disable_receive_dma()	__aic_disable_receive_dma()

+

+#define __i2s_transmit_request()	__aic_transmit_request()

+#define __i2s_receive_request()		__aic_receive_request()

+#define __i2s_transmit_underrun()	__aic_transmit_underrun()

+#define __i2s_receive_overrun()		__aic_receive_overrun()

+

+#define __i2s_clear_errors()		__aic_clear_errors()

+

+#define __i2s_get_transmit_resident()	__aic_get_transmit_resident()

+#define __i2s_get_receive_count()	__aic_get_receive_count()

+

+#define __i2s_enable_transmit_intr()	__aic_enable_transmit_intr()

+#define __i2s_disable_transmit_intr()	__aic_disable_transmit_intr()

+#define __i2s_enable_receive_intr()	__aic_enable_receive_intr()

+#define __i2s_disable_receive_intr()	__aic_disable_receive_intr()

+

+#define __i2s_write_tfifo(v)		__aic_write_tfifo(v)

+#define __i2s_read_rfifo()		__aic_read_rfifo()

+

+#define __i2s_reset_codec()			\

+ do {						\

+ } while (0)

+

+

+/*************************************************************************

+ * SPDIF INTERFACE in AIC Controller

+ *************************************************************************/

+

+#define __spdif_enable()        ( REG_SPDIF_ENA |= SPDIF_ENA_SPEN )

+#define __spdif_disable()       ( REG_SPDIF_ENA &= ~SPDIF_ENA_SPEN )

+

+#define __spdif_enable_transmit_dma()     ( REG_SPDIF_CTRL |= SPDIF_CTRL_DMAEN )

+#define __spdif_disable_transmit_dma()    ( REG_SPDIF_CTRL &= ~SPDIF_CTRL_DMAEN )

+#define __spdif_enable_dtype()            ( REG_SPDIF_CTRL |= SPDIF_CTRL_DTYPE )

+#define __spdif_disable_dtype()           ( REG_SPDIF_CTRL &= ~SPDIF_CTRL_DTYPE )

+#define __spdif_enable_sign()             ( REG_SPDIF_CTRL |= SPDIF_CTRL_SIGN )

+#define __spdif_disable_sign()            ( REG_SPDIF_CTRL &= ~SPDIF_CTRL_SIGN )

+#define __spdif_enable_invalid()          ( REG_SPDIF_CTRL |= SPDIF_CTRL_INVALID )

+#define __spdif_disable_invalid()         ( REG_SPDIF_CTRL &= ~SPDIF_CTRL_INVALID )

+#define __spdif_enable_reset()            ( REG_SPDIF_CTRL |= SPDIF_CTRL_RST )

+#define __spdif_select_spdif()            ( REG_SPDIF_CTRL |= SPDIF_CTRL_SPDIFI2S )

+#define __spdif_select_i2s()              ( REG_SPDIF_CTRL &= ~SPDIF_CTRL_SPDIFI2S )

+#define __spdif_enable_MTRIGmask()        ( REG_SPDIF_CTRL |= SPDIF_CTRL_MTRIG )

+#define __spdif_disable_MTRIGmask()       ( REG_SPDIF_CTRL &= ~SPDIF_CTRL_MTRIG )

+#define __spdif_enable_MFFURmask()        ( REG_SPDIF_CTRL |= SPDIF_CTRL_MFFUR )

+#define __spdif_disable_MFFURmask()       ( REG_SPDIF_CTRL &= ~SPDIF_CTRL_MFFUR )

+

+#define __spdif_enable_initlvl_high()     ( REG_SPDIF_CFG1 |=  SPDIF_CFG1_INITLVL )

+#define __spdif_enable_initlvl_low()      ( REG_SPDIF_CFG1 &=  ~SPDIF_CFG1_INITLVL )

+#define __spdif_enable_zrovld_invald()    ( REG_SPDIF_CFG1 |=  SPDIF_CFG1_ZROVLD )

+#define __spdif_enable_zrovld_vald()      ( REG_SPDIF_CFG1 &=  ~SPDIF_CFG1_ZROVLD )

+

+/* 0, 1, 2, 3 */

+#define __spdif_set_transmit_trigger(n)			\

+do {							\

+	REG_SPDIF_CFG1 &= ~SPDIF_CFG1_TRIG_MASK;	\

+	REG_SPDIF_CFG1 |= SPDIF_CFG1_TRIG(n);	\

+} while(0)

+

+/* 1 ~ 15 */

+#define __spdif_set_srcnum(n)    			\

+do {							\

+	REG_SPDIF_CFG1 &= ~SPDIF_CFG1_SRCNUM_MASK;	\

+	REG_SPDIF_CFG1 |= ((n) << SPDIF_CFG1_SRCNUM_LSB);	\

+} while(0)

+

+/* 1 ~ 15 */

+#define __spdif_set_ch1num(n)    			\

+do {							\

+	REG_SPDIF_CFG1 &= ~SPDIF_CFG1_CH1NUM_MASK;	\

+	REG_SPDIF_CFG1 |= ((n) << SPDIF_CFG1_CH1NUM_LSB);	\

+} while(0)

+

+/* 1 ~ 15 */

+#define __spdif_set_ch2num(n)    			\

+do {							\

+	REG_SPDIF_CFG1 &= ~SPDIF_CFG1_CH2NUM_MASK;	\

+	REG_SPDIF_CFG1 |= ((n) << SPDIF_CFG1_CH2NUM_LSB);	\

+} while(0)

+

+/* 0x0, 0x2, 0x3, 0xa, 0xe */

+#define __spdif_set_fs(n)				\

+do {							\

+	REG_SPDIF_CFG2 &= ~SPDIF_CFG2_FS_MASK;   	\

+	REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_FS_LSB);	\

+} while(0)

+

+/* 0xd, 0xc, 0x5, 0x1 */

+#define __spdif_set_orgfrq(n)				\

+do {							\

+	REG_SPDIF_CFG2 &= ~SPDIF_CFG2_ORGFRQ_MASK;   	\

+	REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_ORGFRQ_LSB);	\

+} while(0)

+

+/* 0x1, 0x6, 0x2, 0x4, 0x5 */

+#define __spdif_set_samwl(n)				\

+do {							\

+	REG_SPDIF_CFG2 &= ~SPDIF_CFG2_SAMWL_MASK;   	\

+	REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_SAMWL_LSB);	\

+} while(0)

+

+#define __spdif_enable_samwl_24()    ( REG_SPDIF_CFG2 |= SPDIF_CFG2_MAXWL )

+#define __spdif_enable_samwl_20()    ( REG_SPDIF_CFG1 &= ~SPDIF_CFG2_MAXWL )

+

+/* 0x1, 0x1, 0x2, 0x3 */

+#define __spdif_set_clkacu(n)				\

+do {							\

+	REG_SPDIF_CFG2 &= ~SPDIF_CFG2_CLKACU_MASK;   	\

+	REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_CLKACU_LSB);	\

+} while(0)

+

+/* see IEC60958-3 */

+#define __spdif_set_catcode(n)				\

+do {							\

+	REG_SPDIF_CFG2 &= ~SPDIF_CFG2_CATCODE_MASK;   	\

+	REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_CATCODE_LSB);	\

+} while(0)

+

+/* n = 0x0, */

+#define __spdif_set_chmode(n)				\

+do {							\

+	REG_SPDIF_CFG2 &= ~SPDIF_CFG2_CHMD_MASK;   	\

+	REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_CHMD_LSB);	\

+} while(0)

+

+#define __spdif_enable_pre()       ( REG_SPDIF_CFG2 |= SPDIF_CFG2_PRE )

+#define __spdif_disable_pre()      ( REG_SPDIF_CFG2 &= ~SPDIF_CFG2_PRE )

+#define __spdif_enable_copyn()     ( REG_SPDIF_CFG2 |= SPDIF_CFG2_COPYN )

+#define __spdif_disable_copyn()    ( REG_SPDIF_CFG2 &= ~SPDIF_CFG2_COPYN )

+/* audio sample word represents linear PCM samples */

+#define __spdif_enable_audion()    ( REG_SPDIF_CFG2 &= ~SPDIF_CFG2_AUDION )

+/* udio sample word used for other purpose */

+#define __spdif_disable_audion()   ( REG_SPDIF_CFG2 |= SPDIF_CFG2_AUDION )

+#define __spdif_enable_conpro()    ( REG_SPDIF_CFG2 &= ~SPDIF_CFG2_CONPRO )

+#define __spdif_disable_conpro()   ( REG_SPDIF_CFG2 |= SPDIF_CFG2_CONPRO )

+

+/***************************************************************************

+ * ICDC

+ ***************************************************************************/

+#define __i2s_internal_codec()         __aic_internal_codec()

+#define __i2s_external_codec()         __aic_external_codec()

+

+#define __icdc_clk_ready()             ( REG_ICDC_CKCFG & ICDC_CKCFG_CKRDY )

+#define __icdc_sel_adc()               ( REG_ICDC_CKCFG |= ICDC_CKCFG_SELAD )

+#define __icdc_sel_dac()               ( REG_ICDC_CKCFG &= ~ICDC_CKCFG_SELAD )

+

+#define __icdc_set_rgwr()              ( REG_ICDC_RGADW |= ICDC_RGADW_RGWR )

+#define __icdc_clear_rgwr()            ( REG_ICDC_RGADW &= ~ICDC_RGADW_RGWR )

+#define __icdc_rgwr_ready()            ( REG_ICDC_RGADW & ICDC_RGADW_RGWR )

+

+#define __icdc_set_addr(n)				\

+do {          						\

+	REG_ICDC_RGADW &= ~ICDC_RGADW_RGADDR_MASK;	\

+	REG_ICDC_RGADW |= (n) << ICDC_RGADW_RGADDR_LSB;	\

+} while(0)

+

+#define __icdc_set_cmd(n)				\

+do {          						\

+	REG_ICDC_RGADW &= ~ICDC_RGADW_RGDIN_MASK;	\

+	REG_ICDC_RGADW |= (n) << ICDC_RGADW_RGDIN_LSB;	\

+} while(0)

+

+#define __icdc_irq_pending()            ( REG_ICDC_RGDATA & ICDC_RGDATA_IRQ )

+#define __icdc_get_value()              ( REG_ICDC_RGDATA & ICDC_RGDATA_RGDOUT_MASK )

+

+

+

+#endif /* __MIPS_ASSEMBLER */

+

+#endif /* __CHIP_AIC_H__ */

diff --git a/arch/mips/include/asm/mach-jz4760b/jz4760bbch.h b/arch/mips/include/asm/mach-jz4760b/jz4760bbch.h
new file mode 100644
index 00000000000..abc09619521
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4760b/jz4760bbch.h
@@ -0,0 +1,216 @@
+/*

+ * linux/include/asm-mips/mach-jz4760b/jz4760bbch.h

+ *

+ * JZ4760B bch register definition.

+ *

+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

+ */

+

+#ifndef __JZ4760BBCH_H__

+#define __JZ4760BBCH_H__

+

+

+#define BCH_BASE	0xB34D0000

+

+/*************************************************************************

+ * BCH

+ *************************************************************************/

+#define	BCH_CR         	(BCH_BASE + 0x00) /* BCH Control register */

+#define	BCH_CRS       	(BCH_BASE + 0x04) /* BCH Control Set register */

+#define	BCH_CRC       	(BCH_BASE + 0x08) /* BCH Control Clear register */

+#define	BCH_CNT    	(BCH_BASE + 0x0C) /* BCH ENC/DEC Count register */

+#define	BCH_DR     	(BCH_BASE + 0x10) /* BCH data register */

+#define	BCH_PAR0    	(BCH_BASE + 0x14) /* BCH Parity 0 register */

+#define	BCH_PAR1    	(BCH_BASE + 0x18) /* BCH Parity 1 register */

+#define	BCH_PAR2    	(BCH_BASE + 0x1C) /* BCH Parity 2 register */

+#define	BCH_PAR3    	(BCH_BASE + 0x20) /* BCH Parity 3 register */

+#define	BCH_PAR4    	(BCH_BASE + 0x24) /* BCH Parity 4 register */

+#define	BCH_PAR5    	(BCH_BASE + 0x28) /* BCH Parity 5 register */

+#define	BCH_PAR6    	(BCH_BASE + 0x2C) /* BCH Parity 6 register */

+#define	BCH_PAR7    	(BCH_BASE + 0x30) /* BCH Parity 7 register */

+#define	BCH_PAR8    	(BCH_BASE + 0x34) /* BCH Parity 8 register */

+#define	BCH_PAR9    	(BCH_BASE + 0x38) /* BCH Parity 9 register */

+#define	BCH_ERR0        (BCH_BASE + 0x3C) /* BCH Error Report 0 register */

+#define	BCH_ERR1        (BCH_BASE + 0x40) /* BCH Error Report 1 register */

+#define	BCH_ERR2        (BCH_BASE + 0x44) /* BCH Error Report 2 register */

+#define	BCH_ERR3        (BCH_BASE + 0x48) /* BCH Error Report 3 register */

+#define	BCH_ERR4        (BCH_BASE + 0x4C) /* BCH Error Report 4 register */

+#define	BCH_ERR5        (BCH_BASE + 0x50) /* BCH Error Report 5 register */

+#define	BCH_ERR6        (BCH_BASE + 0x54) /* BCH Error Report 6 register */

+#define	BCH_ERR7        (BCH_BASE + 0x58) /* BCH Error Report 7 register */

+#define	BCH_ERR8        (BCH_BASE + 0x5C) /* BCH Error Report 8 register */

+#define	BCH_ERR9        (BCH_BASE + 0x60) /* BCH Error Report 9 register */

+#define	BCH_ERR10       (BCH_BASE + 0x64) /* BCH Error Report 10 register */

+#define	BCH_ERR11       (BCH_BASE + 0x68) /* BCH Error Report 11 register */

+#define	BCH_INTS    	(BCH_BASE + 0x6C) /* BCH Interrupt Status register */

+#define	BCH_INTE	(BCH_BASE + 0x70) /* BCH Interrupt Enable register */

+#define	BCH_INTES       (BCH_BASE + 0x74) /* BCH Interrupt Set register */

+#define	BCH_INTEC	(BCH_BASE + 0x78) /* BCH Interrupt Clear register */

+

+#define	REG_BCH_CR      REG32(BCH_CR)

+#define	REG_BCH_CRS     REG32(BCH_CRS)

+#define	REG_BCH_CRC     REG32(BCH_CRC)

+#define	REG_BCH_CNT     REG32(BCH_CNT)

+#define	REG_BCH_DR      REG8(BCH_DR)

+#define	REG_BCH_PAR0    REG32(BCH_PAR0)

+#define	REG_BCH_PAR1    REG32(BCH_PAR1)

+#define	REG_BCH_PAR2    REG32(BCH_PAR2)

+#define	REG_BCH_PAR3    REG32(BCH_PAR3)

+#define	REG_BCH_PAR4    REG32(BCH_PAR4)

+#define	REG_BCH_PAR5    REG32(BCH_PAR5)

+#define	REG_BCH_PAR6    REG32(BCH_PAR6)

+#define	REG_BCH_PAR7    REG32(BCH_PAR7)

+#define	REG_BCH_PAR8    REG32(BCH_PAR8)

+#define	REG_BCH_PAR9    REG32(BCH_PAR9)

+#define	REG_BCH_ERR0    REG32(BCH_ERR0)

+#define	REG_BCH_ERR1    REG32(BCH_ERR1)

+#define	REG_BCH_ERR2    REG32(BCH_ERR2)

+#define	REG_BCH_ERR3    REG32(BCH_ERR3)

+#define	REG_BCH_ERR4    REG32(BCH_ERR4)

+#define	REG_BCH_ERR5    REG32(BCH_ERR5)

+#define	REG_BCH_ERR6    REG32(BCH_ERR6)

+#define	REG_BCH_ERR7    REG32(BCH_ERR7)

+#define	REG_BCH_ERR8    REG32(BCH_ERR8)

+#define	REG_BCH_ERR9    REG32(BCH_ERR9)

+#define	REG_BCH_ERR10   REG32(BCH_ERR10)

+#define	REG_BCH_ERR11   REG32(BCH_ERR11)

+#define	REG_BCH_INTS    REG32(BCH_INTS)

+#define	REG_BCH_INTE    REG32(BCH_INTE)

+#define	REG_BCH_INTEC   REG32(BCH_INTEC)

+#define	REG_BCH_INTES   REG32(BCH_INTES)

+

+/* BCH Control Register*/

+#define	BCH_CR_DMAE              (1 << 7)  /* BCH DMA Enable */

+#define	BCH_CR_BSEL_BIT          3

+#define	BCH_CR_BSEL_MASK         (0x3 << BCH_CR_BSEL_BIT)

+  #define BCH_CR_BSEL_4          (0x0 << BCH_CR_BSEL_BIT)  /* 4 Bit BCH Select */

+  #define BCH_CR_BSEL_8          (0x1 << BCH_CR_BSEL_BIT)  /* 8 Bit BCH Select */

+  #define BCH_CR_BSEL_12         (0x2 << BCH_CR_BSEL_BIT)  /* 12 Bit BCH Select */

+  #define BCH_CR_BSEL_16         (0x3 << BCH_CR_BSEL_BIT)  /* 16 Bit BCH Select */

+  #define BCH_CR_BSEL_20         (0x4 << BCH_CR_BSEL_BIT)  /* 20 Bit BCH Select */

+  #define BCH_CR_BSEL_24         (0x5 << BCH_CR_BSEL_BIT)  /* 24 Bit BCH Select */

+#define	BCH_CR_ENCE              (1 << 2)  /* BCH Encoding Select */

+#define	BCH_CR_DECE              (0 << 2)  /* BCH Decoding Select */

+#define	BCH_CR_BRST              (1 << 1)  /* BCH Reset */

+#define	BCH_CR_BCHE              (1 << 0)  /* BCH Enable */

+

+/* BCH Interrupt Status Register */

+#define	BCH_INTS_ERRC_BIT        27

+#define	BCH_INTS_ERRC_MASK       (0x1f << BCH_INTS_ERRC_BIT)

+#define	BCH_INTS_ALL0            (1 << 5)

+#define	BCH_INTS_ALLf            (1 << 4)

+#define	BCH_INTS_DECF            (1 << 3)

+#define	BCH_INTS_ENCF            (1 << 2)

+#define	BCH_INTS_UNCOR           (1 << 1)

+#define	BCH_INTS_ERR             (1 << 0)

+

+/* BCH ENC/DEC Count Register */

+#define BCH_CNT_DEC_BIT          16

+#define BCH_CNT_DEC_MASK         (0x7ff << BCH_CNT_DEC_BIT)

+#define BCH_CNT_ENC_BIT          0

+#define BCH_CNT_ENC_MASK         (0x7ff << BCH_CNT_ENC_BIT)

+

+/* BCH Error Report Register */

+#define BCH_ERR_INDEX_ODD_BIT    16

+#define BCH_ERR_INDEX_ODD_MASK   (0x1fff << BCH_ERR_INDEX_ODD_BIT)

+#define BCH_ERR_INDEX_EVEN_BIT   0

+#define BCH_ERR_INDEX_EVEN_MASK  (0x1fff << BCH_ERR_INDEX_EVEN_BIT)

+#define BCH_ERR_INDEX_MASK	 0x1fff

+

+#ifndef __MIPS_ASSEMBLER

+

+/*************************************************************************

+ * BCH

+ *************************************************************************/

+#define __ecc_encoding_4bit()						\

+do {									\

+	REG_BCH_CRS = BCH_CR_BSEL_4 | BCH_CR_ENCE | BCH_CR_BCHE;	\

+	REG_BCH_CRC = ~(BCH_CR_BSEL_4 | BCH_CR_ENCE | BCH_CR_BCHE);	\

+	REG_BCH_CRS = BCH_CR_BRST;					\

+} while(0)

+#define __ecc_decoding_4bit()						\

+do {									\

+	REG_BCH_CRS = BCH_CR_BSEL_4 | BCH_CR_DECE | BCH_CR_BCHE;	\

+	REG_BCH_CRC = ~(BCH_CR_BSEL_4 | BCH_CR_DECE | BCH_CR_BCHE);	\

+	REG_BCH_CRS = BCH_CR_BRST;					\

+} while(0)

+#define __ecc_encoding_8bit()                                           \

+do {				   		                        \

+	REG_BCH_CRS = BCH_CR_BSEL_8 | BCH_CR_ENCE | BCH_CR_BCHE;	\

+	REG_BCH_CRC = ~(BCH_CR_BSEL_8 | BCH_CR_ENCE | BCH_CR_BCHE);	\

+	REG_BCH_CRS = BCH_CR_BRST;					\

+} while(0)

+#define __ecc_decoding_8bit()						\

+do {									\

+	REG_BCH_CRS = BCH_CR_BSEL_8 | BCH_CR_DECE | BCH_CR_BCHE;	\

+	REG_BCH_CRC = ~(BCH_CR_BSEL_8 | BCH_CR_DECE | BCH_CR_BCHE);	\

+	REG_BCH_CRS = BCH_CR_BRST;					\

+} while(0)

+#define __ecc_encoding_12bit()						\

+do {									\

+	REG_BCH_CRS = BCH_CR_BSEL_12 | BCH_CR_ENCE | BCH_CR_BCHE;	\

+	REG_BCH_CRC = ~(BCH_CR_BSEL_12 | BCH_CR_ENCE | BCH_CR_BCHE);	\

+	REG_BCH_CRS = BCH_CR_BRST;					\

+} while(0)

+#define __ecc_decoding_12bit()						\

+do {									\

+	REG_BCH_CRS = BCH_CR_BSEL_12 | BCH_CR_DECE | BCH_CR_BCHE;	\

+	REG_BCH_CRC = ~(BCH_CR_BSEL_12 | BCH_CR_DECE | BCH_CR_BCHE);	\

+	REG_BCH_CRS = BCH_CR_BRST;					\

+} while(0)

+#define __ecc_encoding_16bit()						\

+do {									\

+	REG_BCH_CRS = BCH_CR_BSEL_16 | BCH_CR_ENCE | BCH_CR_BCHE;	\

+	REG_BCH_CRC = ~(BCH_CR_BSEL_16 | BCH_CR_ENCE | BCH_CR_BCHE);	\

+	REG_BCH_CRS = BCH_CR_BRST;					\

+} while(0)

+#define __ecc_decoding_16bit()						\

+do {									\

+	REG_BCH_CRS = BCH_CR_BSEL_16 | BCH_CR_DECE | BCH_CR_BCHE;	\

+	REG_BCH_CRC = ~(BCH_CR_BSEL_16 | BCH_CR_DECE | BCH_CR_BCHE);	\

+	REG_BCH_CRS = BCH_CR_BRST;					\

+} while(0)

+#define __ecc_encoding_20bit()						\

+do {									\

+	REG_BCH_CRS = BCH_CR_BSEL_20 | BCH_CR_ENCE | BCH_CR_BCHE;	\

+	REG_BCH_CRC = ~(BCH_CR_BSEL_20 | BCH_CR_ENCE | BCH_CR_BCHE);	\

+	REG_BCH_CRS = BCH_CR_BRST;					\

+} while(0)

+#define __ecc_decoding_20bit()						\

+do {									\

+	REG_BCH_CRS = BCH_CR_BSEL_20 | BCH_CR_DECE | BCH_CR_BCHE;	\

+	REG_BCH_CRC = ~(BCH_CR_BSEL_20 | BCH_CR_DECE | BCH_CR_BCHE);	\

+	REG_BCH_CRS = BCH_CR_BRST;					\

+} while(0)

+#define __ecc_encoding_24bit()						\

+do {									\

+	REG_BCH_CRS = BCH_CR_BSEL_24 | BCH_CR_ENCE | BCH_CR_BCHE;	\

+	REG_BCH_CRC = ~(BCH_CR_BSEL_24 | BCH_CR_ENCE | BCH_CR_BCHE);	\

+	REG_BCH_CRS = BCH_CR_BRST;					\

+} while(0)

+#define __ecc_decoding_24bit()						\

+do {									\

+	REG_BCH_CRS = BCH_CR_BSEL_24 | BCH_CR_DECE | BCH_CR_BCHE;	\

+	REG_BCH_CRC = ~(BCH_CR_BSEL_24 | BCH_CR_DECE | BCH_CR_BCHE);	\

+	REG_BCH_CRS = BCH_CR_BRST;					\

+} while(0)

+#define __ecc_dma_enable()        ( REG_BCH_CRS = BCH_CR_DMAE )

+#define __ecc_dma_disable()       ( REG_BCH_CRC = BCH_CR_DMAE )

+#define __ecc_disable()           ( REG_BCH_CRC = BCH_CR_BCHE )

+#define __ecc_encode_sync()       while (!(REG_BCH_INTS & BCH_INTS_ENCF))

+#define __ecc_decode_sync()       while (!(REG_BCH_INTS & BCH_INTS_DECF))

+

+#define __ecc_cnt_dec(n)                                             \

+do {						               	     \

+        REG_BCH_CNT = (n) << BCH_CNT_DEC_BIT;                        \

+} while(0)

+

+#define __ecc_cnt_enc(n)                                             \

+do {                                                                 \

+        REG_BCH_CNT = (n) << BCH_CNT_ENC_BIT;                        \

+} while(0)

+

+#endif /* __MIPS_ASSEMBLER */

+

+#endif /* __JZ4760BBCH_H__ */

+

diff --git a/arch/mips/include/asm/mach-jz4760b/jz4760bbdma.h b/arch/mips/include/asm/mach-jz4760b/jz4760bbdma.h
new file mode 100644
index 00000000000..9376649711f
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4760b/jz4760bbdma.h
@@ -0,0 +1,314 @@
+/*

+ * linux/include/asm-mips/mach-jz4760b/jz4760bbdma.h

+ *

+ * JZ4760B BDMA register definition.

+ *

+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

+ */

+

+#ifndef __JZ4760BBDMA_H__

+#define __JZ4760BBDMA_H__

+

+

+#define BDMAC_BASE  0xB3450000

+

+

+/*************************************************************************

+ * BDMAC (BCH & NAND DMA Controller)

+ *************************************************************************/

+

+/* n is the DMA channel index (0 - 2) */

+#define BDMAC_DSAR(n)		(BDMAC_BASE + (0x00 + (n) * 0x20)) /* DMA source address */

+#define BDMAC_DTAR(n)  		(BDMAC_BASE + (0x04 + (n) * 0x20)) /* DMA target address */

+#define BDMAC_DTCR(n)  		(BDMAC_BASE + (0x08 + (n) * 0x20)) /* DMA transfer count */

+#define BDMAC_DRSR(n)  		(BDMAC_BASE + (0x0c + (n) * 0x20)) /* DMA request source */

+#define BDMAC_DCCSR(n) 		(BDMAC_BASE + (0x10 + (n) * 0x20)) /* DMA control/status */

+#define BDMAC_DCMD(n)  		(BDMAC_BASE + (0x14 + (n) * 0x20)) /* DMA command */

+#define BDMAC_DDA(n)   		(BDMAC_BASE + (0x18 + (n) * 0x20)) /* DMA descriptor address */

+#define BDMAC_DSD(n)   		(BDMAC_BASE + (0x1c + (n) * 0x20)) /* DMA Stride Address */

+#define BDMAC_DNT(n)  		(BDMAC_BASE + (0xc0 + (n) * 0x04)) /* NAND Detect Timer */

+

+#define BDMAC_DMACR			(BDMAC_BASE + 0x0300) 	/* DMA control register */

+#define BDMAC_DMAIPR		(BDMAC_BASE + 0x0304) 	/* DMA interrupt pending */

+#define BDMAC_DMADBR		(BDMAC_BASE + 0x0308) 	/* DMA doorbell */

+#define BDMAC_DMADBSR		(BDMAC_BASE + 0x030C) 	/* DMA doorbell set */

+#define BDMAC_DMACKE  		(BDMAC_BASE + 0x0310)

+#define BDMAC_DMACKES  		(BDMAC_BASE + 0x0314)

+#define BDMAC_DMACKEC  		(BDMAC_BASE + 0x0318)

+

+#define REG_BDMAC_DSAR(n)	REG32(BDMAC_DSAR((n)))

+#define REG_BDMAC_DTAR(n)	REG32(BDMAC_DTAR((n)))

+#define REG_BDMAC_DTCR(n)	REG32(BDMAC_DTCR((n)))

+#define REG_BDMAC_DRSR(n)	REG32(BDMAC_DRSR((n)))

+#define REG_BDMAC_DCCSR(n)	REG32(BDMAC_DCCSR((n)))

+#define REG_BDMAC_DCMD(n)	REG32(BDMAC_DCMD((n)))

+#define REG_BDMAC_DDA(n)	REG32(BDMAC_DDA((n)))

+#define REG_BDMAC_DSD(n)    REG32(BDMAC_DSD(n))

+#define REG_BDMAC_DNT(n)	REG32(BDMAC_DNT(n))

+

+#define REG_BDMAC_DMACR		REG32(BDMAC_DMACR)

+#define REG_BDMAC_DMAIPR	REG32(BDMAC_DMAIPR)

+#define REG_BDMAC_DMADBR	REG32(BDMAC_DMADBR)

+#define REG_BDMAC_DMADBSR	REG32(BDMAC_DMADBSR)

+#define REG_BDMAC_DMACKE    REG32(BDMAC_DMACKE)

+#define REG_BDMAC_DMACKES    REG32(BDMAC_DMACKES)

+#define REG_BDMAC_DMACKEC    REG32(BDMAC_DMACKEC)

+

+// BDMA request source register

+#define BDMAC_DRSR_RS_BIT	0

+#define BDMAC_DRSR_RS_MASK	(0x3f << DMAC_DRSR_RS_BIT)

+#define BDMAC_DRSR_RS_BCH_ENC	(2 << DMAC_DRSR_RS_BIT)

+#define BDMAC_DRSR_RS_BCH_DEC	(3 << DMAC_DRSR_RS_BIT)

+#define BDMAC_DRSR_RS_NAND0	(6 << DMAC_DRSR_RS_BIT)

+#define BDMAC_DRSR_RS_NAND1	(7 << DMAC_DRSR_RS_BIT)

+#define BDMAC_DRSR_RS_AUTO	(8 << DMAC_DRSR_RS_BIT)

+#define BDMAC_DRSR_RS_EXT	(12 << DMAC_DRSR_RS_BIT)

+

+// BDMA channel control/status register

+#define BDMAC_DCCSR_NDES	(1 << 31) /* descriptor (0) or not (1) ? */

+#define BDMAC_DCCSR_DES8    	(1 << 30) /* Descriptor 8 Word */

+#define BDMAC_DCCSR_DES4    	(0 << 30) /* Descriptor 4 Word */

+#define BDMAC_DCCSR_LASTMD0    	(0 << 28) /* BCH Decoding last mode 0, there's one descriptor for decoding blcok*/

+#define BDMAC_DCCSR_LASTMD1    	(1 << 28) /* BCH Decoding last mode 1, there's two descriptor for decoding blcok*/

+#define BDMAC_DCCSR_LASTMD2    	(2 << 28) /* BCH Decoding last mode 2, there's three descriptor for decoding blcok*/

+#define BDMAC_DCCSR_FRBS(n)	((n) << 24)

+#define BDMAC_DCCSR_CDOA_BIT	16        /* copy of DMA offset address */

+  #define BDMAC_DCCSR_CDOA_MASK	(0xff << BDMACC_DCCSR_CDOA_BIT)

+#define BDMAC_DCCSR_BERR	(0x1f << 7)  /* BCH error within this transfer, Only for channel 0 */

+#define BDMAC_DCCSR_BUERR       (1 << 5)  /* BCH uncorrectable error, only for channel 0 */

+#define BDMAC_DCCSR_NSERR       (1 << 5)  /* status error, only for channel 1 */

+#define BDMAC_DCCSR_AR		(1 << 4)  /* address error */

+#define BDMAC_DCCSR_TT		(1 << 3)  /* transfer terminated */

+#define BDMAC_DCCSR_HLT		(1 << 2)  /* DMA halted */

+#define BDMAC_DCCSR_BAC		(1 << 1)  /* BCH auto correction */

+#define BDMAC_DCCSR_EN		(1 << 0)  /* channel enable bit */

+

+// BDMA channel command register

+#define BDMAC_DCMD_EACKS_LOW  	(1 << 31) /* External DACK Output Level Select, active low */

+#define BDMAC_DCMD_EACKS_HIGH  	(0 << 31) /* External DACK Output Level Select, active high */

+#define BDMAC_DCMD_EACKM_WRITE 	(1 << 30) /* External DACK Output Mode Select, output in write cycle */

+#define BDMAC_DCMD_EACKM_READ 	(0 << 30) /* External DACK Output Mode Select, output in read cycle */

+#define BDMAC_DCMD_ERDM_BIT	28        /* External DREQ Detection Mode Select */

+  #define BDMAC_DCMD_ERDM_MASK	(0x03 << BDMAC_DCMD_ERDM_BIT)

+  #define BDMAC_DCMD_ERDM_LOW	(0 << BDMAC_DCMD_ERDM_BIT)

+  #define BDMAC_DCMD_ERDM_FALL	(1 << BDMAC_DCMD_ERDM_BIT)

+  #define BDMAC_DCMD_ERDM_HIGH	(2 << BDMAC_DCMD_ERDM_BIT)

+  #define BDMAC_DCMD_ERDM_RISE	(3 << BDMAC_DCMD_ERDM_BIT)

+#define BDMAC_DCMD_BLAST	(1 << 25) /* BCH last */

+#define BDMAC_DCMD_SAI		(1 << 23) /* source address increment */

+#define BDMAC_DCMD_DAI		(1 << 22) /* dest address increment */

+#define BDMAC_DCMD_SWDH_BIT	14  /* source port width */

+  #define BDMAC_DCMD_SWDH_MASK	(0x03 << BDMAC_DCMD_SWDH_BIT)

+  #define BDMAC_DCMD_SWDH_32	(0 << BDMAC_DCMD_SWDH_BIT)

+  #define BDMAC_DCMD_SWDH_8	(1 << BDMAC_DCMD_SWDH_BIT)

+  #define BDMAC_DCMD_SWDH_16	(2 << BDMAC_DCMD_SWDH_BIT)

+#define BDMAC_DCMD_DWDH_BIT	12  /* dest port width */

+  #define BDMAC_DCMD_DWDH_MASK	(0x03 << BDMAC_DCMD_DWDH_BIT)

+  #define BDMAC_DCMD_DWDH_32	(0 << BDMAC_DCMD_DWDH_BIT)

+  #define BDMAC_DCMD_DWDH_8	(1 << BDMAC_DCMD_DWDH_BIT)

+  #define BDMAC_DCMD_DWDH_16	(2 << BDMAC_DCMD_DWDH_BIT)

+#define BDMAC_DCMD_DS_BIT	8  /* transfer data size of a data unit */

+  #define BDMAC_DCMD_DS_MASK	(0x07 << BDMAC_DCMD_DS_BIT)

+  #define BDMAC_DCMD_DS_32BIT	(0 << BDMAC_DCMD_DS_BIT)

+  #define BDMAC_DCMD_DS_8BIT	(1 << BDMAC_DCMD_DS_BIT)

+  #define BDMAC_DCMD_DS_16BIT	(2 << BDMAC_DCMD_DS_BIT)

+  #define BDMAC_DCMD_DS_16BYTE	(3 << BDMAC_DCMD_DS_BIT)

+  #define BDMAC_DCMD_DS_32BYTE	(4 << BDMAC_DCMD_DS_BIT)

+  #define BDMAC_DCMD_DS_64BYTE	(5 << BDMAC_DCMD_DS_BIT)

+#define BDMAC_DCMD_NRD   	(1 << 7)  /* NAND direct read */

+#define BDMAC_DCMD_NWR   	(1 << 6)  /* NAND direct write */

+#define BDMAC_DCMD_NAC   	(1 << 5)  /* NAND AL/CL enable */

+#define BDMAC_DCMD_STDE   	(1 << 2)  /* Stride Disable/Enable */

+#define BDMAC_DCMD_TIE		(1 << 1)  /* DMA transfer interrupt enable */

+#define BDMAC_DCMD_LINK		(1 << 0)  /* descriptor link enable */

+

+// BDMA descriptor address register

+#define BDMAC_DDA_BASE_BIT	12  /* descriptor base address */

+  #define BDMAC_DDA_BASE_MASK	(0x0fffff << BDMAC_DDA_BASE_BIT)

+#define BDMAC_DDA_OFFSET_BIT	4   /* descriptor offset address */

+  #define BDMAC_DDA_OFFSET_MASK	(0x0ff << BDMAC_DDA_OFFSET_BIT)

+

+// BDMA stride address register

+#define BDMAC_DSD_TSD_BIT	16	/* target stride address */

+  #define BDMAC_DSD_TSD_MASK	(0xffff << BDMAC_DSD_TSD_BIT)

+#define BDMAC_DSD_SSD_BIT	0	/* source stride address */

+  #define BDMAC_DSD_SSD_MASK	(0xffff << BDMAC_DSD_SSD_BIT)

+

+// BDMA NAND Detect timer register

+#define BDMAC_NDTCTIMER_EN	(1 << 15)  /* enable detect timer */

+#define BDMAC_TAILCNT_BIT	16

+

+// BDMA control register

+#define BDMAC_DMACR_PR_BIT	8	/* channel priority mode */

+  #define BDMAC_DMACR_PR_MASK	(0x03 << DMAC_DMACR_PR_BIT)

+  #define BDMAC_DMACR_PR_01_2	(0 << BDMAC_DMACR_PR_BIT)

+  #define BDMAC_DMACR_PR_12_0	(1 << BDMAC_DMACR_PR_BIT)

+  #define BDMAC_DMACR_PR_20_1	(2 << BDMAC_DMACR_PR_BIT)

+  #define BDMAC_DMACR_PR_012	(3 << BDMAC_DMACR_PR_BIT)

+#define BDMAC_DMACR_HLT		(1 << 3)  /* DMA halt flag */

+#define BDMAC_DMACR_AR		(1 << 2)  /* address error flag */

+#define BDMAC_DMACR_DMAE	(1 << 0)  /* DMA enable bit */

+

+// BDMA interrupt pending register

+#define BDMAC_DMAIPR_CIRQ2	(1 << 2)  /* irq pending status for channel 2 */

+#define BDMAC_DMAIPR_CIRQ1	(1 << 1)  /* irq pending status for channel 1 */

+#define BDMAC_DMAIPR_CIRQ0	(1 << 0)  /* irq pending status for channel 0 */

+

+// BDMA doorbell register

+#define BDMAC_DMADBR_DB2	(1 << 2)  /* doorbell for channel 2 */

+#define BDMAC_DMADBR_DB1	(1 << 1)  /* doorbell for channel 1 */

+#define BDMAC_DMADBR_DB0	(1 << 0)  /* doorbell for channel 0 */

+

+// BDMA doorbell set register

+#define BDMAC_DMADBSR_DBS2	(1 << 2)  /* enable doorbell for channel 2 */

+#define BDMAC_DMADBSR_DBS1	(1 << 1)  /* enable doorbell for channel 1 */

+#define BDMAC_DMADBSR_DBS0	(1 << 0)  /* enable doorbell for channel 0 */

+

+

+#ifndef __MIPS_ASSEMBLER

+

+

+/***************************************************************************

+ * BCH & NAND DMAC

+ ***************************************************************************/

+

+/* n is the DMA channel index (0 - 2) */

+

+#define __bdmac_test_halt_error ( REG_BDMAC_DMACR & BDMAC_DMACR_HLT )

+#define __bdmac_test_addr_error ( REG_BDMAC_DMACR & BDMAC_DMACR_AR )

+

+#define __bdmac_channel_enable_clk(n)           \

+	REG_BDMAC_DMACKES |= 1 << (n);

+

+#define __bdmac_enable_descriptor(n) \

+  ( REG_BDMAC_DCCSR((n)) &= ~BDMAC_DCCSR_NDES )

+#define __bdmac_disable_descriptor(n) \

+  ( REG_BDMAC_DCCSR((n)) |= BDMAC_DCCSR_NDES )

+

+#define __bdmac_enable_channel(n)                 \

+do {                                             \

+	REG_BDMAC_DCCSR((n)) |= BDMAC_DCCSR_EN;    \

+} while (0)

+#define __bdmac_disable_channel(n)                \

+do {                                             \

+	REG_BDMAC_DCCSR((n)) &= ~BDMAC_DCCSR_EN;   \

+} while (0)

+

+#define __bdmac_channel_enable_irq(n) \

+  ( REG_BDMAC_DCMD((n)) |= BDMAC_DCMD_TIE )

+#define __bdmac_channel_disable_irq(n) \

+  ( REG_BDMAC_DCMD((n)) &= ~BDMAC_DCMD_TIE )

+

+#define __bdmac_channel_transmit_halt_detected(n) \

+  (  REG_BDMAC_DCCSR((n)) & BDMAC_DCCSR_HLT )

+#define __bdmac_channel_transmit_end_detected(n) \

+  (  REG_BDMAC_DCCSR((n)) & BDMAC_DCCSR_TT )

+/* Nand ops status error, only for channel 1 */

+#define __bdmac_channel_status_error_detected() \

+  (  REG_BDMAC_DCCSR(1) & BDMAC_DCCSR_NSERR )

+#define __bdmac_channel_address_error_detected(n) \

+  (  REG_BDMAC_DCCSR((n)) & BDMAC_DCCSR_AR )

+#define __bdmac_channel_count_terminated_detected(n) \

+  (  REG_BDMAC_DCCSR((n)) & BDMAC_DCCSR_CT )

+#define __bdmac_channel_descriptor_invalid_detected(n) \

+  (  REG_BDMAC_DCCSR((n)) & BDMAC_DCCSR_INV )

+#define __bdmac_BCH_error_detected(n) \

+  (  REG_BDMAC_DCCSR((n)) & BDMAC_DCCSR_BERR )

+

+#define __bdmac_channel_clear_transmit_halt(n)				\

+	do {								\

+		/* clear both channel halt error and globle halt error */ \

+		REG_BDMAC_DCCSR(n) &= ~BDMAC_DCCSR_HLT;			\

+		REG_BDMAC_DMACR &= ~BDMAC_DMACR_HLT;	\

+	} while (0)

+#define __bdmac_channel_clear_transmit_end(n) \

+  (  REG_BDMAC_DCCSR(n) &= ~BDMAC_DCCSR_TT )

+#define __bdmac_channel_clear_status_error() \

+  ( REG_BDMAC_DCCSR(1) &= ~BDMAC_DCCSR_NSERR )

+#define __bdmac_channel_clear_address_error(n)				\

+	do {								\

+		REG_BDMAC_DDA(n) = 0; /* clear descriptor address register */ \

+		REG_BDMAC_DSAR(n) = 0; /* clear source address register */ \

+		REG_BDMAC_DTAR(n) = 0; /* clear target address register */ \

+		/* clear both channel addr error and globle address error */ \

+		REG_BDMAC_DCCSR(n) &= ~BDMAC_DCCSR_AR;			\

+		REG_BDMAC_DMACR &= ~BDMAC_DMACR_AR;	\

+	} while (0)

+#define __bdmac_channel_clear_count_terminated(n) \

+  (  REG_BDMAC_DCCSR((n)) &= ~BDMAC_DCCSR_CT )

+#define __bdmac_channel_clear_descriptor_invalid(n) \

+  (  REG_BDMAC_DCCSR((n)) &= ~BDMAC_DCCSR_INV )

+

+#define __bdmac_channel_set_transfer_unit_32bit(n)	\

+do {							\

+	REG_BDMAC_DCMD((n)) &= ~BDMAC_DCMD_DS_MASK;	\

+	REG_BDMAC_DCMD((n)) |= BDMAC_DCMD_DS_32BIT;	\

+} while (0)

+

+#define __bdmac_channel_set_transfer_unit_16bit(n)	\

+do {							\

+	REG_BDMAC_DCMD((n)) &= ~BDMAC_DCMD_DS_MASK;	\

+	REG_BDMAC_DCMD((n)) |= BDMAC_DCMD_DS_16BIT;	\

+} while (0)

+

+#define __bdmac_channel_set_transfer_unit_8bit(n)	\

+do {							\

+	REG_BDMAC_DCMD((n)) &= ~BDMAC_DCMD_DS_MASK;	\

+	REG_BDMAC_DCMD((n)) |= BDMAC_DCMD_DS_8BIT;	\

+} while (0)

+

+#define __bdmac_channel_set_transfer_unit_16byte(n)	\

+do {							\

+	REG_BDMAC_DCMD((n)) &= ~BDMAC_DCMD_DS_MASK;	\

+	REG_BDMAC_DCMD((n)) |= BDMAC_DCMD_DS_16BYTE;	\

+} while (0)

+

+#define __bdmac_channel_set_transfer_unit_32byte(n)	\

+do {							\

+	REG_BDMAC_DCMD((n)) &= ~BDMAC_DCMD_DS_MASK;	\

+	REG_BDMAC_DCMD((n)) |= BDMAC_DCMD_DS_32BYTE;	\

+} while (0)

+

+/* w=8,16,32 */

+#define __bdmac_channel_set_dest_port_width(n,w)		\

+do {							\

+	REG_BDMAC_DCMD((n)) &= ~BDMAC_DCMD_DWDH_MASK;	\

+	REG_BDMAC_DCMD((n)) |= BDMAC_DCMD_DWDH_##w;	\

+} while (0)

+

+/* w=8,16,32 */

+#define __bdmac_channel_set_src_port_width(n,w)		\

+do {							\

+	REG_BDMAC_DCMD((n)) &= ~BDMAC_DCMD_SWDH_MASK;	\

+	REG_BDMAC_DCMD((n)) |= BDMAC_DCMD_SWDH_##w;	\

+} while (0)

+

+#define __bdmac_channel_dest_addr_fixed(n) \

+	(REG_BDMAC_DCMD((n)) &= ~BDMAC_DCMD_DAI)

+#define __bdmac_channel_dest_addr_increment(n) \

+	(REG_BDMAC_DCMD((n)) |= BDMAC_DCMD_DAI)

+

+#define __bdmac_channel_src_addr_fixed(n) \

+	(REG_BDMAC_DCMD((n)) &= ~BDMAC_DCMD_SAI)

+#define __bdmac_channel_src_addr_increment(n) \

+	(REG_BDMAC_DCMD((n)) |= BDMAC_DCMD_SAI)

+

+#define __bdmac_channel_set_doorbell(n)	\

+	(REG_BDMAC_DMADBSR = (1 << (n)))

+

+#define __bdmac_channel_irq_detected(n)  (REG_BDMAC_DMAIPR & (1 << (n)))

+#define __bdmac_channel_ack_irq(n)       (REG_BDMAC_DMAIPR &= ~(1 <<(n)))

+

+static __inline__ int __bdmac_get_irq(void)

+{

+	int i;

+	for (i = 0; i < MAX_BDMA_NUM; i++)

+		if (__bdmac_channel_irq_detected(i))

+			return i;

+	return -1;

+}

+

+#endif /* __MIPS_ASSEMBLER */

+

+#endif /* __JZ4760BBDMA_H__ */

+

diff --git a/arch/mips/include/asm/mach-jz4760b/jz4760bcim.h b/arch/mips/include/asm/mach-jz4760b/jz4760bcim.h
new file mode 100644
index 00000000000..b5e8c7c0a63
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4760b/jz4760bcim.h
@@ -0,0 +1,417 @@
+/*

+ * linux/include/asm-mips/mach-jz4760b/jz4760bcim.h

+ *

+ * JZ4760B CIM register definition.

+ *

+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

+ */

+

+#ifndef __JZ4760BCIM_H__

+#define __JZ4760BCIM_H__

+

+

+#define	CIM_BASE	0xB3060000

+

+/*************************************************************************

+ * CIM

+ *************************************************************************/

+#define	CIM_CFG			(CIM_BASE + 0x0000)

+#define	CIM_CTRL		(CIM_BASE + 0x0004)

+#define	CIM_STATE		(CIM_BASE + 0x0008)

+#define	CIM_IID			(CIM_BASE + 0x000C)

+#define	CIM_RXFIFO		(CIM_BASE + 0x0010)

+#define	CIM_DA			(CIM_BASE + 0x0020)

+#define	CIM_FA			(CIM_BASE + 0x0024)

+#define	CIM_FID			(CIM_BASE + 0x0028)

+#define	CIM_CMD			(CIM_BASE + 0x002C)

+#define	CIM_SIZE		(CIM_BASE + 0x0030)

+#define	CIM_OFFSET		(CIM_BASE + 0x0034)

+#define CIM_YFA			(CIM_BASE + 0x0038)

+#define CIM_YCMD		(CIM_BASE + 0x003C)

+#define CIM_CBFA		(CIM_BASE + 0x0040)

+#define CIM_CBCMD		(CIM_BASE + 0x0044)

+#define CIM_CRFA		(CIM_BASE + 0x0048)

+#define CIM_CRCMD		(CIM_BASE + 0x004C)

+#define CIM_CTRL2		(CIM_BASE + 0x0050)

+#define	CIM_RAM_ADDR		(CIM_BASE + 0x1000)

+

+#define	REG_CIM_CFG		REG32(CIM_CFG)

+#define	REG_CIM_CTRL		REG32(CIM_CTRL)

+#define REG_CIM_CTRL2		REG32(CIM_CTRL2)

+#define	REG_CIM_STATE		REG32(CIM_STATE)

+#define	REG_CIM_IID		REG32(CIM_IID)

+#define	REG_CIM_RXFIFO		REG32(CIM_RXFIFO)

+#define	REG_CIM_DA		REG32(CIM_DA)

+#define	REG_CIM_FA		REG32(CIM_FA)

+#define	REG_CIM_FID		REG32(CIM_FID)

+#define	REG_CIM_CMD		REG32(CIM_CMD)

+#define	REG_CIM_SIZE		REG32(CIM_SIZE)

+#define	REG_CIM_OFFSET		REG32(CIM_OFFSET)

+#define REG_CIM_YFA		REG32(CIM_YFA)

+#define REG_CIM_YCMD		REG32(CIM_YCMD)

+#define REG_CIM_CBFA		REG32(CIM_CBFA)

+#define REG_CIM_CBCMD		REG32(CIM_CBCMD)

+#define REG_CIM_CRFA		REG32(CIM_CRFA)

+#define REG_CIM_CRCMD		REG32(CIM_CRCMD)

+

+#define CIM_CFG_RXF_TRIG_BIT	24

+#define CIM_CFG_RXF_TRIG_MASK	(0x3f << CIM_CFG_RT_TRIG_MASK)

+#define CIM_CFG_SEP		(1 << 20)

+#define	CIM_CFG_ORDER_BIT	18

+#define	CIM_CFG_ORDER_MASK	(0x3 << CIM_CFG_ORDER_BIT)

+  #define CIM_CFG_ORDER_0	  (0x0 << CIM_CFG_ORDER_BIT) 	/* Y0CbY1Cr; YCbCr */

+  #define CIM_CFG_ORDER_1	  (0x1 << CIM_CFG_ORDER_BIT)	/* Y0CrY1Cb; YCrCb */

+  #define CIM_CFG_ORDER_2	  (0x2 << CIM_CFG_ORDER_BIT)	/* CbY0CrY1; CbCrY */

+  #define CIM_CFG_ORDER_3	  (0x3 << CIM_CFG_ORDER_BIT)	/* CrY0CbY1; CrCbY */

+#define	CIM_CFG_DF_BIT		16

+#define	CIM_CFG_DF_MASK		  (0x3 << CIM_CFG_DF_BIT)

+  #define CIM_CFG_DF_YUV444	  (0x1 << CIM_CFG_DF_BIT) 	/* YCbCr444 */

+  #define CIM_CFG_DF_YUV422	  (0x2 << CIM_CFG_DF_BIT)	/* YCbCr422 */

+  #define CIM_CFG_DF_ITU656	  (0x3 << CIM_CFG_DF_BIT)	/* ITU656 YCbCr422 */

+#define	CIM_CFG_INV_DAT		(1 << 15)

+#define	CIM_CFG_VSP		(1 << 14) /* VSYNC Polarity:0-rising edge active,1-falling edge active */

+#define	CIM_CFG_HSP		(1 << 13) /* HSYNC Polarity:0-rising edge active,1-falling edge active */

+#define	CIM_CFG_PCP		(1 << 12) /* PCLK working edge: 0-rising, 1-falling */

+#define	CIM_CFG_DMA_BURST_TYPE_BIT	10

+#define	CIM_CFG_DMA_BURST_TYPE_MASK	(0x3 << CIM_CFG_DMA_BURST_TYPE_BIT)

+  #define	CIM_CFG_DMA_BURST_INCR4		(0 << CIM_CFG_DMA_BURST_TYPE_BIT)

+  #define	CIM_CFG_DMA_BURST_INCR8		(1 << CIM_CFG_DMA_BURST_TYPE_BIT)	/* Suggested */

+  #define	CIM_CFG_DMA_BURST_INCR16	(2 << CIM_CFG_DMA_BURST_TYPE_BIT)	/* Suggested High speed AHB*/

+  #define	CIM_CFG_DMA_BURST_INCR32	(3 << CIM_CFG_DMA_BURST_TYPE_BIT)	/* Suggested High speed AHB*/

+#define	CIM_CFG_DUMMY_ZERO	(1 << 9)

+#define	CIM_CFG_EXT_VSYNC	(1 << 8)	/* Only for ITU656 Progressive mode */

+#define	CIM_CFG_PACK_BIT	4

+#define	CIM_CFG_PACK_MASK	(0x7 << CIM_CFG_PACK_BIT)

+  #define CIM_CFG_PACK_0	  (0 << CIM_CFG_PACK_BIT) /* 11 22 33 44 0xY0CbY1Cr */

+  #define CIM_CFG_PACK_1	  (1 << CIM_CFG_PACK_BIT) /* 22 33 44 11 0xCbY1CrY0 */

+  #define CIM_CFG_PACK_2	  (2 << CIM_CFG_PACK_BIT) /* 33 44 11 22 0xY1CrY0Cb */

+  #define CIM_CFG_PACK_3	  (3 << CIM_CFG_PACK_BIT) /* 44 11 22 33 0xCrY0CbY1 */

+  #define CIM_CFG_PACK_4	  (4 << CIM_CFG_PACK_BIT) /* 44 33 22 11 0xCrY1CbY0 */

+  #define CIM_CFG_PACK_5	  (5 << CIM_CFG_PACK_BIT) /* 33 22 11 44 0xY1CbY0Cr */

+  #define CIM_CFG_PACK_6	  (6 << CIM_CFG_PACK_BIT) /* 22 11 44 33 0xCbY0CrY1 */

+  #define CIM_CFG_PACK_7	  (7 << CIM_CFG_PACK_BIT) /* 11 44 33 22 0xY0CrY1Cb */

+#define	CIM_CFG_BYPASS_BIT	2

+#define	CIM_CFG_BYPASS_MASK	(1 << CIM_CFG_BYPASS_BIT)

+  #define CIM_CFG_BYPASS	  (1 << CIM_CFG_BYPASS_BIT)

+#define	CIM_CFG_DSM_BIT		0

+#define	CIM_CFG_DSM_MASK	(0x3 << CIM_CFG_DSM_BIT)

+  #define CIM_CFG_DSM_CPM	  (0 << CIM_CFG_DSM_BIT) /* CCIR656 Progressive Mode */

+  #define CIM_CFG_DSM_CIM	  (1 << CIM_CFG_DSM_BIT) /* CCIR656 Interlace Mode */

+  #define CIM_CFG_DSM_GCM	  (2 << CIM_CFG_DSM_BIT) /* Gated Clock Mode */

+

+/* CIM Control Register  (CIM_CTRL) */

+#define	CIM_CTRL_EEOF_LINE_BIT	20

+#define	CIM_CTRL_EEOF_LINE_MASK	(0xfff << CIM_CTRL_EEOF_LINE_BIT)

+#define	CIM_CTRL_FRC_BIT	16

+#define	CIM_CTRL_FRC_MASK	(0xf << CIM_CTRL_FRC_BIT)

+  #define CIM_CTRL_FRC_1	  (0x0 << CIM_CTRL_FRC_BIT) /* Sample every frame */

+  #define CIM_CTRL_FRC_2	  (0x1 << CIM_CTRL_FRC_BIT) /* Sample 1/2 frame */

+  #define CIM_CTRL_FRC_3	  (0x2 << CIM_CTRL_FRC_BIT) /* Sample 1/3 frame */

+  #define CIM_CTRL_FRC_4	  (0x3 << CIM_CTRL_FRC_BIT) /* Sample 1/4 frame */

+  #define CIM_CTRL_FRC_5	  (0x4 << CIM_CTRL_FRC_BIT) /* Sample 1/5 frame */

+  #define CIM_CTRL_FRC_6	  (0x5 << CIM_CTRL_FRC_BIT) /* Sample 1/6 frame */

+  #define CIM_CTRL_FRC_7	  (0x6 << CIM_CTRL_FRC_BIT) /* Sample 1/7 frame */

+  #define CIM_CTRL_FRC_8	  (0x7 << CIM_CTRL_FRC_BIT) /* Sample 1/8 frame */

+  #define CIM_CTRL_FRC_9	  (0x8 << CIM_CTRL_FRC_BIT) /* Sample 1/9 frame */

+  #define CIM_CTRL_FRC_10	  (0x9 << CIM_CTRL_FRC_BIT) /* Sample 1/10 frame */

+  #define CIM_CTRL_FRC_11	  (0xA << CIM_CTRL_FRC_BIT) /* Sample 1/11 frame */

+  #define CIM_CTRL_FRC_12	  (0xB << CIM_CTRL_FRC_BIT) /* Sample 1/12 frame */

+  #define CIM_CTRL_FRC_13	  (0xC << CIM_CTRL_FRC_BIT) /* Sample 1/13 frame */

+  #define CIM_CTRL_FRC_14	  (0xD << CIM_CTRL_FRC_BIT) /* Sample 1/14 frame */

+  #define CIM_CTRL_FRC_15	  (0xE << CIM_CTRL_FRC_BIT) /* Sample 1/15 frame */

+  #define CIM_CTRL_FRC_16	  (0xF << CIM_CTRL_FRC_BIT) /* Sample 1/16 frame */

+

+#define	CIM_CTRL_DMA_EEOFM	(1 << 15)	/* Enable EEOF interrupt */

+#define	CIM_CTRL_WIN_EN		(1 << 14)

+#define	CIM_CTRL_VDDM		(1 << 13) /* VDD interrupt enable */

+#define	CIM_CTRL_DMA_SOFM	(1 << 12)

+#define	CIM_CTRL_DMA_EOFM	(1 << 11)

+#define	CIM_CTRL_DMA_STOPM	(1 << 10)

+#define	CIM_CTRL_RXF_TRIGM	(1 << 9)

+#define	CIM_CTRL_RXF_OFM	(1 << 8)

+#define	CIM_CTRL_DMA_SYNC	(1 << 7)	/*when change DA, do frame sync */

+#define	CIM_CTRL_RXF_TRIG_BIT	3

+#define	CIM_CTRL_RXF_TRIG_MASK	(0xf << CIM_CTRL_RXF_TRIG_BIT) /* trigger value = (n+1)*burst_type */

+

+#define	CIM_CTRL_DMA_EN		(1 << 2) /* Enable DMA */

+#define	CIM_CTRL_RXF_RST	(1 << 1) /* RxFIFO reset */

+#define	CIM_CTRL_ENA		(1 << 0) /* Enable CIM */

+

+

+/* cim control2 */

+#define CIM_CTRL2_OPG_BIT	4

+#define CIM_CTRL2_OPG_MASK	(0x3 << CIM_CTRL2_OPG_BIT)

+#define CIM_CTRL2_OPE		(1 << 2)

+#define CIM_CTRL2_EME		(1 << 1)

+#define CIM_CTRL2_APM		(1 << 0)

+

+/* CIM State Register  (CIM_STATE) */

+#define CIM_STATE_CR_RF_OF	(1 << 27)

+#define CIM_STATE_CR_RF_TRIG	(1 << 26)

+#define CIM_STATE_CR_RF_EMPTY	(1 << 25)

+

+#define CIM_STATE_CB_RF_OF	(1 << 19)

+#define CIM_STATE_CB_RF_TRIG	(1 << 18)

+#define CIM_STATE_CB_RF_EMPTY	(1 << 17)

+

+#define CIM_STATE_Y_RF_OF	(1 << 11)

+#define CIM_STATE_Y_RF_TRIG	(1 << 10)

+#define CIM_STATE_Y_RF_EMPTY	(1 << 9)

+

+#define	CIM_STATE_DMA_EEOF	(1 << 7) /* DMA Line EEOf irq */

+#define	CIM_STATE_DMA_SOF	(1 << 6) /* DMA start irq */

+#define	CIM_STATE_DMA_EOF	(1 << 5) /* DMA end irq */

+#define	CIM_STATE_DMA_STOP	(1 << 4) /* DMA stop irq */

+#define	CIM_STATE_RXF_OF	(1 << 3) /* RXFIFO over flow irq */

+#define	CIM_STATE_RXF_TRIG	(1 << 2) /* RXFIFO triger meet irq */

+#define	CIM_STATE_RXF_EMPTY	(1 << 1) /* RXFIFO empty irq */

+#define	CIM_STATE_VDD		(1 << 0) /* CIM disabled irq */

+

+/* CIM DMA Command Register (CIM_CMD) */

+

+#define	CIM_CMD_SOFINT		(1 << 31) /* enable DMA start irq */

+#define	CIM_CMD_EOFINT		(1 << 30) /* enable DMA end irq */

+#define	CIM_CMD_EEOFINT		(1 << 29) /* enable DMA EEOF irq */

+#define	CIM_CMD_STOP		(1 << 28) /* enable DMA stop irq */

+#define	CIM_CMD_OFRCV		(1 << 27) /* enable recovery when TXFiFo overflow */

+#define	CIM_CMD_LEN_BIT		0

+#define	CIM_CMD_LEN_MASK	(0xffffff << CIM_CMD_LEN_BIT)

+

+/* CIM Window-Image Size Register  (CIM_SIZE) */

+#define	CIM_SIZE_LPF_BIT	16 /* Lines per freame for csc output image */

+#define	CIM_SIZE_LPF_MASK	(0x1fff << CIM_SIZE_LPF_BIT)

+#define	CIM_SIZE_PPL_BIT	0 /* Pixels per line for csc output image, should be an even number */

+#define	CIM_SIZE_PPL_MASK	(0x1fff << CIM_SIZE_PPL_BIT)

+

+/* CIM Image Offset Register  (CIM_OFFSET) */

+#define	CIM_OFFSET_V_BIT	16 /* Vertical offset */

+#define	CIM_OFFSET_V_MASK	(0xfff << CIM_OFFSET_V_BIT)

+#define	CIM_OFFSET_H_BIT	0 /* Horizontal offset, should be an enen number */

+#define	CIM_OFFSET_H_MASK	(0xfff << CIM_OFFSET_H_BIT) /*OFFSET_H should be even number*/

+

+#ifndef __MIPS_ASSEMBLER

+

+/***************************************************************************

+ * CIM

+ ***************************************************************************/

+

+#define __cim_enable()	( REG_CIM_CTRL |= CIM_CTRL_ENA )

+#define __cim_disable()	( REG_CIM_CTRL &= ~CIM_CTRL_ENA )

+

+#define __cim_enable_sep() (REG_CIM_CFG |= CIM_CFG_SEP)

+#define __cim_disable_sep() (REG_CIM_CFG &= ~CIM_CFG_SEP)

+

+/* n = 0, 1, 2, 3 */

+#define __cim_set_input_data_stream_order(n)				\

+	do {								\

+		REG_CIM_CFG &= ~CIM_CFG_ORDER_MASK;			\

+		REG_CIM_CFG |= ((n)<<CIM_CFG_ORDER_BIT)&CIM_CFG_ORDER_MASK; \

+	} while (0)

+

+#define __cim_input_data_format_select_RGB()	\

+	do {					\

+		REG_CIM_CFG &= ~CIM_CFG_DF_MASK;	\

+		REG_CIM_CFG |= CIM_CFG_DF_RGB;	\

+	} while (0)

+

+#define __cim_input_data_format_select_YUV444()		\

+	do {						\

+		REG_CIM_CFG &= ~CIM_CFG_DF_MASK;		\

+		REG_CIM_CFG |= CIM_CFG_DF_YUV444;	\

+	} while (0)

+

+#define __cim_input_data_format_select_YUV422()		\

+	do {						\

+		REG_CIM_CFG &= ~CIM_CFG_DF_MASK;		\

+		REG_CIM_CFG |= CIM_CFG_DF_YUV422;	\

+	} while (0)

+

+#define __cim_input_data_format_select_ITU656()		\

+	do {						\

+		REG_CIM_CFG &= ~CIM_CFG_DF_MASK;		\

+		REG_CIM_CFG |= CIM_CFG_DF_ITU656;	\

+	} while (0)

+

+#define __cim_input_data_inverse()	( REG_CIM_CFG |= CIM_CFG_INV_DAT )

+#define __cim_input_data_normal()	( REG_CIM_CFG &= ~CIM_CFG_INV_DAT )

+

+#define __cim_vsync_active_low()	( REG_CIM_CFG |= CIM_CFG_VSP )

+#define __cim_vsync_active_high()	( REG_CIM_CFG &= ~CIM_CFG_VSP )

+

+#define __cim_hsync_active_low()	( REG_CIM_CFG |= CIM_CFG_HSP )

+#define __cim_hsync_active_high()	( REG_CIM_CFG &= ~CIM_CFG_HSP )

+

+#define __cim_sample_data_at_pclk_falling_edge() \

+	( REG_CIM_CFG |= CIM_CFG_PCP )

+#define __cim_sample_data_at_pclk_rising_edge() \

+	( REG_CIM_CFG &= ~CIM_CFG_PCP )

+

+#define __cim_enable_dummy_zero()	( REG_CIM_CFG |= CIM_CFG_DUMMY_ZERO )

+#define __cim_disable_dummy_zero()	( REG_CIM_CFG &= ~CIM_CFG_DUMMY_ZERO )

+

+#define __cim_select_external_vsync()	( REG_CIM_CFG |= CIM_CFG_EXT_VSYNC )

+#define __cim_select_internal_vsync()	( REG_CIM_CFG &= ~CIM_CFG_EXT_VSYNC )

+

+/* n=0-7 */

+#define __cim_set_data_packing_mode(n) 		\

+do {						\

+	REG_CIM_CFG &= ~CIM_CFG_PACK_MASK;	\

+	REG_CIM_CFG |= (CIM_CFG_PACK_##n);	\

+} while (0)

+

+#define __cim_enable_bypass_func() 	(REG_CIM_CFG |= CIM_CFG_BYPASS)

+#define __cim_disable_bypass_func() 	(REG_CIM_CFG &= ~CIM_CFG_BYPASS_MASK)

+

+#define __cim_enable_ccir656_progressive_mode()	\

+do {						\

+	REG_CIM_CFG &= ~CIM_CFG_DSM_MASK;	\

+	REG_CIM_CFG |= CIM_CFG_DSM_CPM;		\

+} while (0)

+

+#define __cim_enable_ccir656_interlace_mode()	\

+do {						\

+	REG_CIM_CFG &= ~CIM_CFG_DSM_MASK;	\

+	REG_CIM_CFG |= CIM_CFG_DSM_CIM;		\

+} while (0)

+

+#define __cim_enable_gated_clock_mode()		\

+do {						\

+	REG_CIM_CFG &= ~CIM_CFG_DSM_MASK;	\

+	REG_CIM_CFG |= CIM_CFG_DSM_GCM;		\

+} while (0)

+

+#define __cim_enable_nongated_clock_mode()	\

+do {						\

+	REG_CIM_CFG &= ~CIM_CFG_DSM_MASK;	\

+	REG_CIM_CFG |= CIM_CFG_DSM_NGCM;	\

+} while (0)

+

+/* sclk:system bus clock

+ * mclk: CIM master clock

+ */

+#define __cim_set_master_clk(sclk, mclk)			\

+do {								\

+	REG_CIM_CTRL &= ~CIM_CTRL_MCLKDIV_MASK;				\

+	REG_CIM_CTRL |= (((sclk)/(mclk) - 1) << CIM_CTRL_MCLKDIV_BIT);	\

+} while (0)

+/* n=1-16 */

+#define __cim_set_frame_rate(n) 		\

+do {						\

+	REG_CIM_CTRL &= ~CIM_CTRL_FRC_MASK; 	\

+	REG_CIM_CTRL |= CIM_CTRL_FRC_##n;	\

+} while (0)

+

+#define __cim_enable_size_func() \

+	( REG_CIM_CTRL |= CIM_CTRL_WIN_EN)

+#define __cim_disable_size_func() \

+	( REG_CIM_CTRL &= ~CIM_CTRL_WIN_EN )

+

+#define __cim_enable_vdd_intr() \

+	( REG_CIM_CTRL |= CIM_CTRL_VDDM )

+#define __cim_disable_vdd_intr() \

+	( REG_CIM_CTRL &= ~CIM_CTRL_VDDM )

+

+#define __cim_enable_sof_intr() \

+	( REG_CIM_CTRL |= CIM_CTRL_DMA_SOFM )

+#define __cim_disable_sof_intr() \

+	( REG_CIM_CTRL &= ~CIM_CTRL_DMA_SOFM )

+

+#define __cim_enable_eof_intr() \

+	( REG_CIM_CTRL |= CIM_CTRL_DMA_EOFM )

+#define __cim_disable_eof_intr() \

+	( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EOFM )

+

+#define __cim_enable_eeof_intr() \

+	( REG_CIM_CTRL |= CIM_CTRL_DMA_EEOFM )

+#define __cim_disable_eeof_intr() \

+	( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EEOFM )

+

+#define __cim_enable_stop_intr() \

+	( REG_CIM_CTRL |= CIM_CTRL_DMA_STOPM )

+#define __cim_disable_stop_intr() \

+	( REG_CIM_CTRL &= ~CIM_CTRL_DMA_STOPM )

+

+#define __cim_enable_trig_intr() \

+	( REG_CIM_CTRL |= CIM_CTRL_RXF_TRIGM )

+#define __cim_disable_trig_intr() \

+	( REG_CIM_CTRL &= ~CIM_CTRL_RXF_TRIGM )

+

+#define __cim_enable_rxfifo_overflow_intr()	\

+	( REG_CIM_CTRL |= CIM_CTRL_RXF_OFM )

+#define __cim_disable_rxfifo_overflow_intr()	\

+	( REG_CIM_CTRL &= ~CIM_CTRL_RXF_OFM )

+

+/* n=4,8,12,16,20,24,28,32 */

+#define __cim_set_rxfifo_trigger(n)				\

+	do {							\

+		REG_CIM_CTRL &= ~CIM_CTRL_RXF_TRIG_MASK; 	\

+		REG_CIM_CTRL |= CIM_CTRL_RXF_TRIG_##n;		\

+	} while (0)

+

+

+#define __cim_set_eeof_line(n)						\

+	do {								\

+		REG_CIM_CTRL &= ~CIM_CTRL_EEOF_LINE_MASK;		\

+		REG_CIM_CTRL |= ( ((n) << CIM_CTRL_EEOF_LINE_BIT) & CIM_CTRL_EEOF_LINE_MASK ); \

+	} while (0)

+

+#define __cim_enable_fast_mode() 	( REG_CIM_CTRL |= CIM_CTRL_FAST_MODE )

+#define __cim_disable_fast_mode() 	( REG_CIM_CTRL &= ~CIM_CTRL_FAST_MODE )

+#define __cim_use_normal_mode() 	__cim_disable_fast_mode()

+#define __cim_enable_dma()   ( REG_CIM_CTRL |= CIM_CTRL_DMA_EN )

+#define __cim_disable_dma()  ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EN )

+#define __cim_reset_rxfifo() ( REG_CIM_CTRL |= CIM_CTRL_RXF_RST )

+#define __cim_unreset_rxfifo() ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_RST )

+

+/* cim control2 */

+#define __cim_enable_priority_control()		( REG_CIM_CTRL2 |= CIM_CTRL2_APM)

+#define __cim_disable_priority_control()	( REG_CIM_CTRL2 &= ~CIM_CTRL2_APM)

+#define __cim_enable_auto_priority()		( REG_CIM_CTRL2 |= CIM_CTRL2_OPE)

+#define __cim_disable_auto_priority()		( REG_CIM_CTRL2 &= ~CIM_CTRL2_OPE)

+#define __cim_enable_emergency()		( REG_CIM_CTRL2 |= CIM_CTRL2_EME)

+#define __cim_disable_emergency()		( REG_CIM_CTRL2 &= ~CIM_CTRL2_EME);

+/* 0, 1, 2, 3

+ * 0: highest priority

+ * 3: lowest priority

+ * 1 maybe best for SEP=1

+ * 3 maybe best for SEP=0

+ */

+#define __cim_set_opg(n)				\

+	do {								\

+		REG_CIM_CTRL2 &= ~CIM_CTRL2_OPG_MASK;			\

+		REG_CIM_CTRL2 |= ((n) << CIM_CTRL2_OPG_BIT) & CIM_CTRL2_OPG_MASK; \

+	} while (0)

+

+#define __cim_clear_state()   	     ( REG_CIM_STATE = 0 )

+

+#define __cim_disable_done()   	     ( REG_CIM_STATE & CIM_STATE_VDD )

+#define __cim_rxfifo_empty()   	     ( REG_CIM_STATE & CIM_STATE_RXF_EMPTY )

+#define __cim_rxfifo_reach_trigger() ( REG_CIM_STATE & CIM_STATE_RXF_TRIG )

+#define __cim_rxfifo_overflow()      ( REG_CIM_STATE & CIM_STATE_RXF_OF )

+#define __cim_clear_rxfifo_overflow() ( REG_CIM_STATE &= ~CIM_STATE_RXF_OF )

+#define __cim_dma_stop()   	     ( REG_CIM_STATE & CIM_STATE_DMA_STOP )

+#define __cim_dma_eof()   	     ( REG_CIM_STATE & CIM_STATE_DMA_EOF )

+#define __cim_dma_sof()   	     ( REG_CIM_STATE & CIM_STATE_DMA_SOF )

+

+#define __cim_get_iid()   	     ( REG_CIM_IID )

+#define __cim_get_fid()   	     ( REG_CIM_FID )

+#define __cim_get_image_data()       ( REG_CIM_RXFIFO )

+#define __cim_get_dma_cmd()          ( REG_CIM_CMD )

+

+#define __cim_set_da(a)              ( REG_CIM_DA = (a) )

+

+#define __cim_set_line(a) 	( REG_CIM_SIZE = (REG_CIM_SIZE&(~CIM_SIZE_LPF_MASK))|((a)<<CIM_SIZE_LPF_BIT) )

+#define __cim_set_pixel(a) 	( REG_CIM_SIZE = (REG_CIM_SIZE&(~CIM_SIZE_PPL_MASK))|((a)<<CIM_SIZE_PPL_BIT) )

+#define __cim_get_line() 	((REG_CIM_SIZE&CIM_SIZE_LPF_MASK)>>CIM_SIZE_LPF_BIT)

+#define __cim_get_pixel() 	((REG_CIM_SIZE&CIM_SIZE_PPL_MASK)>>CIM_SIZE_PPL_BIT)

+

+#define __cim_set_v_offset(a) 	( REG_CIM_OFFSET = (REG_CIM_OFFSET&(~CIM_OFFSET_V_MASK)) | ((a)<<CIM_OFFSET_V_BIT) )

+#define __cim_set_h_offset(a) 	( REG_CIM_OFFSET = (REG_CIM_OFFSET&(~CIM_OFFSET_H_MASK)) | ((a)<<CIM_OFFSET_H_BIT) )

+#define __cim_get_v_offset() 	((REG_CIM_OFFSET&CIM_OFFSET_V_MASK)>>CIM_OFFSET_V_BIT)

+#define __cim_get_h_offset() 	((REG_CIM_OFFSET&CIM_OFFSET_H_MASK)>>CIM_OFFSET_H_BIT)

+

+

+

+#endif /* __MIPS_ASSEMBLER */

+

+#endif /* __JZ4760BCIM_H__ */

diff --git a/arch/mips/include/asm/mach-jz4760b/jz4760bcpm.h b/arch/mips/include/asm/mach-jz4760b/jz4760bcpm.h
new file mode 100644
index 00000000000..172eaa6f2cd
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4760b/jz4760bcpm.h
@@ -0,0 +1,671 @@
+/*
+ * jz4760bcpm.h
+ * JZ4760B CPM register definition
+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.
+ *
+ * Author: whxu@ingenic.cn
+ */
+
+#ifndef __JZ4760BCPM_H__
+#define __JZ4760BCPM_H__
+
+#ifndef JZ_EXTAL
+#define JZ_EXTAL		12000000   /* 3.6864 MHz */
+#endif
+#ifndef JZ_EXTAL2
+#define JZ_EXTAL2		32768     /* 32.768 KHz */
+#endif
+
+/*
+ * Clock reset and power controller module(CPM) address definition
+ */
+#define	CPM_BASE	0xb0000000
+
+
+/*
+ * CPM registers offset address definition
+ */
+#define CPM_CPCCR_OFFSET        (0x00)  /* rw, 32, 0x01011100 */
+#define CPM_LCR_OFFSET          (0x04)  /* rw, 32, 0x000000f8 */
+#define CPM_RSR_OFFSET          (0x08)  /* rw, 32, 0x???????? */
+#define CPM_CPPCR0_OFFSET       (0x10)  /* rw, 32, 0x28080011 */
+#define CPM_CPPSR_OFFSET        (0x14)  /* rw, 32, 0x80000000 */
+#define CPM_CLKGR0_OFFSET       (0x20)  /* rw, 32, 0x3fffffe0 */
+#define CPM_OPCR_OFFSET         (0x24)  /* rw, 32, 0x00001570 */
+#define CPM_CLKGR1_OFFSET       (0x28)  /* rw, 32, 0x0000017f */
+#define CPM_CPPCR1_OFFSET       (0x30)  /* rw, 32, 0x28080002 */
+#define CPM_CPSPR_OFFSET        (0x34)  /* rw, 32, 0x???????? */
+#define CPM_CPSPPR_OFFSET       (0x38)  /* rw, 32, 0x0000a5a5 */
+#define CPM_USBPCR_OFFSET       (0x3c)  /* rw, 32, 0x42992198 */
+#define CPM_USBRDT_OFFSET       (0x40)  /* rw, 32, 0x00000096 */
+#define CPM_USBVBFIL_OFFSET     (0x44)  /* rw, 32, 0x00000080 */
+#define CPM_USBCDR_OFFSET       (0x50)  /* rw, 32, 0x00000000 */
+#define CPM_I2SCDR_OFFSET       (0x60)  /* rw, 32, 0x00000000 */
+#define CPM_LPCDR_OFFSET        (0x64)  /* rw, 32, 0x00000000 */
+#define CPM_MSCCDR_OFFSET       (0x68)  /* rw, 32, 0x00000000 */
+#define CPM_UHCCDR_OFFSET       (0x6c)  /* rw, 32, 0x00000000 */
+#define CPM_SSICDR_OFFSET       (0x74)  /* rw, 32, 0x00000000 */
+#define CPM_CIMCDR_OFFSET       (0x7c)  /* rw, 32, 0x00000000 */
+#define CPM_GPSCDR_OFFSET       (0x80)  /* rw, 32, 0x00000000 */
+#define CPM_PCMCDR_OFFSET       (0x84)  /* rw, 32, 0x00000000 */
+#define CPM_GPUCDR_OFFSET       (0x88)  /* rw, 32, 0x00000000 */
+#define CPM_PSWC0ST_OFFSET      (0x90)  /* rw, 32, 0x00000000 */
+#define CPM_PSWC1ST_OFFSET      (0x94)  /* rw, 32, 0x00000000 */
+#define CPM_PSWC2ST_OFFSET      (0x98)  /* rw, 32, 0x00000000 */
+#define CPM_PSWC3ST_OFFSET      (0x9c)  /* rw, 32, 0x00000000 */
+
+
+/*
+ * CPM registers address definition
+ */
+#define CPM_CPCCR        (CPM_BASE + CPM_CPCCR_OFFSET)
+#define CPM_LCR          (CPM_BASE + CPM_LCR_OFFSET)
+#define CPM_RSR          (CPM_BASE + CPM_RSR_OFFSET)
+#define CPM_CPPCR0       (CPM_BASE + CPM_CPPCR0_OFFSET)
+#define CPM_CPPSR        (CPM_BASE + CPM_CPPSR_OFFSET)
+#define CPM_CLKGR0       (CPM_BASE + CPM_CLKGR0_OFFSET)
+#define CPM_OPCR         (CPM_BASE + CPM_OPCR_OFFSET)
+#define CPM_CLKGR1       (CPM_BASE + CPM_CLKGR1_OFFSET)
+#define CPM_CPPCR1       (CPM_BASE + CPM_CPPCR1_OFFSET)
+#define CPM_CPSPR        (CPM_BASE + CPM_CPSPR_OFFSET)
+#define CPM_CPSPPR       (CPM_BASE + CPM_CPSPPR_OFFSET)
+#define CPM_USBPCR       (CPM_BASE + CPM_USBPCR_OFFSET)
+#define CPM_USBRDT       (CPM_BASE + CPM_USBRDT_OFFSET)
+#define CPM_USBVBFIL     (CPM_BASE + CPM_USBVBFIL_OFFSET)
+#define CPM_USBCDR       (CPM_BASE + CPM_USBCDR_OFFSET)
+#define CPM_I2SCDR       (CPM_BASE + CPM_I2SCDR_OFFSET)
+#define CPM_LPCDR        (CPM_BASE + CPM_LPCDR_OFFSET)
+#define CPM_MSCCDR       (CPM_BASE + CPM_MSCCDR_OFFSET)
+#define CPM_UHCCDR       (CPM_BASE + CPM_UHCCDR_OFFSET)
+#define CPM_SSICDR       (CPM_BASE + CPM_SSICDR_OFFSET)
+#define CPM_CIMCDR       (CPM_BASE + CPM_CIMCDR_OFFSET)
+#define CPM_GPSCDR       (CPM_BASE + CPM_GPSCDR_OFFSET)
+#define CPM_PCMCDR       (CPM_BASE + CPM_PCMCDR_OFFSET)
+#define CPM_GPUCDR       (CPM_BASE + CPM_GPUCDR_OFFSET)
+#define CPM_PSWC0ST      (CPM_BASE + CPM_PSWC0ST_OFFSET)
+#define CPM_PSWC1ST      (CPM_BASE + CPM_PSWC1ST_OFFSET)
+#define CPM_PSWC2ST      (CPM_BASE + CPM_PSWC2ST_OFFSET)
+#define CPM_PSWC3ST      (CPM_BASE + CPM_PSWC3ST_OFFSET)
+
+
+/*
+ * CPM registers common define
+ */
+
+/* Clock control register(CPCCR) */
+#define CPCCR_ECS               BIT31
+#define CPCCR_MEM               BIT30
+#define CPCCR_CE                BIT22
+#define CPCCR_PCS               BIT21
+
+#define CPCCR_SDIV_LSB          24
+#define CPCCR_SDIV_MASK         BITS_H2L(27, CPCCR_SDIV_LSB)
+
+#define CPCCR_H2DIV_LSB         16
+#define CPCCR_H2DIV_MASK        BITS_H2L(19, CPCCR_H2DIV_LSB)
+
+#define CPCCR_MDIV_LSB          12
+#define CPCCR_MDIV_MASK         BITS_H2L(15, CPCCR_MDIV_LSB)
+
+#define CPCCR_PDIV_LSB		8
+#define CPCCR_PDIV_MASK         BITS_H2L(11, CPCCR_PDIV_LSB)
+
+#define CPCCR_HDIV_LSB		4
+#define CPCCR_HDIV_MASK         BITS_H2L(7, CPCCR_HDIV_LSB)
+
+#define CPCCR_CDIV_LSB		0
+#define CPCCR_CDIV_MASK         BITS_H2L(3, CPCCR_CDIV_LSB)
+
+/* Low power control register(LCR) */
+#define LCR_PDAHB1              BIT30
+#define LCR_VBATIR              BIT29
+#define LCR_PDGPS               BIT28
+#define LCR_PDAHB1S             BIT26
+#define LCR_PDGPSS              BIT24
+#define LCR_DOZE                BIT2
+
+#define LCR_PST_LSB             8
+#define LCR_PST_MASK            BITS_H2L(19, LCR_PST_LSB)
+
+#define LCR_DUTY_LSB            3
+#define LCR_DUTY_MASK           BITS_H2L(7, LCR_DUTY_LSB)
+
+#define LCR_LPM_LSB             0
+#define LCR_LPM_MASK            BITS_H2L(1, LCR_LPM_LSB)
+#define LCR_LPM_IDLE            (0x0 << LCR_LPM_LSB)
+#define LCR_LPM_SLEEP           (0x1 << LCR_LPM_LSB)
+
+/* Reset status register(RSR) */
+#define RSR_P0R         BIT2
+#define RSR_WR          BIT1
+#define RSR_PR          BIT0
+
+/* PLL control register 0(CPPCR0) */
+#define CPPCR0_LOCK             BIT15   /* LOCK0 bit */
+#define CPPCR0_ENLOCK           BIT14
+#define CPPCR0_PLLS             BIT10
+#define CPPCR0_PLLBP            BIT9
+#define CPPCR0_PLLEN            BIT8
+
+#define CPPCR0_PLLM_LSB         24
+#define CPPCR0_PLLM_MASK        BITS_H2L(30, CPPCR0_PLLM_LSB)
+
+#define CPPCR0_PLLN_LSB         18
+#define CPPCR0_PLLN_MASK        BITS_H2L(21, CPPCR0_PLLN_LSB)
+
+#define CPPCR0_PLLOD_LSB        16
+#define CPPCR0_PLLOD_MASK       BITS_H2L(17, CPPCR0_PLLOD_LSB)
+
+#define CPPCR0_PLLST_LSB        0
+#define CPPCR0_PLLST_MASK       BITS_H2L(7, CPPCR0_PLLST_LSB)
+
+/* PLL switch and status register(CPPSR) */
+#define CPPSR_PLLOFF            BIT31
+#define CPPSR_PLLBP             BIT30
+#define CPPSR_PLLON             BIT29
+#define CPPSR_PS                BIT28
+#define CPPSR_FS                BIT27
+#define CPPSR_CS                BIT26
+#define CPPSR_SM                BIT2
+#define CPPSR_PM                BIT1
+#define CPPSR_FM                BIT0
+
+/* Clock gate register 0(CGR0) */
+#define CLKGR0_EMC              BIT31
+#define CLKGR0_DDR              BIT30
+#define CLKGR0_IPU              BIT29
+#define CLKGR0_LCD              BIT28
+#define CLKGR0_TVE              BIT27
+#define CLKGR0_CIM              BIT26
+#define CLKGR0_MDMA             BIT25
+#define CLKGR0_UHC              BIT24
+#define CLKGR0_MAC              BIT23
+#define CLKGR0_GPS              BIT22
+#define CLKGR0_DMAC             BIT21
+#define CLKGR0_SSI2             BIT20
+#define CLKGR0_SSI1             BIT19
+#define CLKGR0_UART3            BIT18
+#define CLKGR0_UART2            BIT17
+#define CLKGR0_UART1            BIT16
+#define CLKGR0_UART0            BIT15
+#define CLKGR0_SADC             BIT14
+#define CLKGR0_KBC              BIT13
+#define CLKGR0_MSC2             BIT12
+#define CLKGR0_MSC1             BIT11
+#define CLKGR0_OWI              BIT10
+#define CLKGR0_TSSI             BIT9
+#define CLKGR0_AIC              BIT8
+#define CLKGR0_SCC              BIT7
+#define CLKGR0_I2C1             BIT6
+#define CLKGR0_I2C0             BIT5
+#define CLKGR0_SSI0             BIT4
+#define CLKGR0_MSC0             BIT3
+#define CLKGR0_OTG              BIT2
+#define CLKGR0_BCH              BIT1
+#define CLKGR0_NEMC             BIT0
+
+/* Oscillator and power control register(OPCR) */
+#define OPCR_OTGPHY_ENABLE      BIT7    /* SPENDN bit */
+#define OPCR_GPSEN              BIT6
+#define OPCR_UHCPHY_DISABLE     BIT5    /* SPENDH bit */
+#define OPCR_O1SE               BIT4
+#define OPCR_PD                 BIT3
+#define OPCR_ERCS               BIT2
+
+#define OPCR_O1ST_LSB           8
+#define OPCR_O1ST_MASK          BITS_H2L(15, OPCR_O1ST_LSB)
+
+/* Clock gate register 1(CGR1) */
+#define CLKGR1_AUX              BIT11
+#define CLKGR1_OSD              BIT10
+#define CLKGR1_GPU              BIT9
+#define CLKGR1_PCM              BIT8
+#define CLKGR1_AHB1             BIT7
+#define CLKGR1_CABAC            BIT6
+#define CLKGR1_SRAM             BIT5
+#define CLKGR1_DCT              BIT4
+#define CLKGR1_ME               BIT3
+#define CLKGR1_DBLK             BIT2
+#define CLKGR1_MC               BIT1
+#define CLKGR1_BDMA             BIT0
+
+/* PLL control register 1(CPPCR1) */
+#define CPPCR1_P1SCS            BIT15
+#define CPPCR1_PLL1EN           BIT7
+#define CPPCR1_PLL1S            BIT6
+#define CPPCR1_LOCK             BIT2    /* LOCK1 bit */
+#define CPPCR1_PLL1OFF          BIT1
+#define CPPCR1_PLL1ON           BIT0
+
+#define CPPCR1_PLL1M_LSB        24
+#define CPPCR1_PLL1M_MASK       BITS_H2L(30, CPPCR1_PLL1M_LSB)
+
+#define CPPCR1_PLL1N_LSB        18
+#define CPPCR1_PLL1N_MASK       BITS_H2L(21, CPPCR1_PLL1N_LSB)
+
+#define CPPCR1_PLL1OD_LSB       16
+#define CPPCR1_PLL1OD_MASK      BITS_H2L(17, CPPCR1_PLL1OD_LSB)
+
+#define CPPCR1_P1SDIV_LSB       9
+#define CPPCR1_P1SDIV_MASK      BITS_H2L(14, CPPCR1_P1SDIV_LSB)
+
+/* CPM scratch pad protected register(CPSPPR) */
+#define CPSPPR_CPSPR_WRITABLE   (0x00005a5a)
+
+/* OTG parameter control register(USBPCR) */
+#define USBPCR_USB_MODE         BIT31
+#define USBPCR_AVLD_REG         BIT30
+#define USBPCR_INCRM            BIT27   /* INCR_MASK bit */
+#define USBPCR_CLK12_EN         BIT26
+#define USBPCR_COMMONONN        BIT25
+#define USBPCR_VBUSVLDEXT       BIT24
+#define USBPCR_VBUSVLDEXTSEL    BIT23
+#define USBPCR_POR              BIT22
+#define USBPCR_SIDDQ            BIT21
+#define USBPCR_OTG_DISABLE      BIT20
+#define USBPCR_TXPREEMPHTUNE    BIT6
+
+#define USBPCR_IDPULLUP_LSB             28   /* IDPULLUP_MASK bit */
+#define USBPCR_IDPULLUP_MASK            BITS_H2L(29, USBPCR_USBPCR_IDPULLUP_LSB)
+
+#define USBPCR_COMPDISTUNE_LSB          17
+#define USBPCR_COMPDISTUNE_MASK         BITS_H2L(19, USBPCR_COMPDISTUNE_LSB)
+
+#define USBPCR_OTGTUNE_LSB              14
+#define USBPCR_OTGTUNE_MASK             BITS_H2L(16, USBPCR_OTGTUNE_LSB)
+
+#define USBPCR_SQRXTUNE_LSB             11
+#define USBPCR_SQRXTUNE_MASK            BITS_H2L(13, USBPCR_SQRXTUNE_LSB)
+
+#define USBPCR_TXFSLSTUNE_LSB           7
+#define USBPCR_TXFSLSTUNE_MASK          BITS_H2L(10, USBPCR_TXFSLSTUNE_LSB)
+
+#define USBPCR_TXRISETUNE_LSB           4
+#define USBPCR_TXRISETUNE_MASK          BITS_H2L(5, USBPCR_TXRISETUNE_LSB)
+
+#define USBPCR_TXVREFTUNE_LSB           0
+#define USBPCR_TXVREFTUNE_MASK          BITS_H2L(3, USBPCR_TXVREFTUNE_LSB)
+
+/* OTG reset detect timer register(USBRDT) */
+#define USBRDT_VBFIL_LD_EN      BIT25
+#define USBRDT_IDDIG_EN         BIT24
+#define USBRDT_IDDIG_REG        BIT23
+
+#define USBRDT_USBRDT_LSB       0
+#define USBRDT_USBRDT_MASK      BITS_H2L(22, USBRDT_USBRDT_LSB)
+
+/* OTG PHY clock divider register(USBCDR) */
+#define USBCDR_UCS              BIT31
+#define USBCDR_UPCS             BIT30
+
+#define USBCDR_OTGDIV_LSB       0       /* USBCDR bit */
+#define USBCDR_OTGDIV_MASK      BITS_H2L(5, USBCDR_OTGDIV_LSB)
+
+/* I2S device clock divider register(I2SCDR) */
+#define I2SCDR_I2CS             BIT31
+#define I2SCDR_I2PCS            BIT30
+
+#define I2SCDR_I2SDIV_LSB       0       /* I2SCDR bit */
+#define I2SCDR_I2SDIV_MASK      BITS_H2L(8, I2SCDR_I2SDIV_LSB)
+
+/* LCD pix clock divider register(LPCDR) */
+#define LPCDR_LSCS              BIT31
+#define LPCDR_LTCS              BIT30
+#define LPCDR_LPCS              BIT29
+
+#define LPCDR_PIXDIV_LSB        0       /* LPCDR bit */
+#define LPCDR_PIXDIV_MASK       BITS_H2L(10, LPCDR_PIXDIV_LSB)
+
+/* MSC clock divider register(MSCCDR) */
+#define MSCCDR_MCS              BIT31
+
+#define MSCCDR_MSCDIV_LSB       0       /* MSCCDR bit */
+#define MSCCDR_MSCDIV_MASK      BITS_H2L(5, MSCCDR_MSCDIV_LSB)
+
+/* UHC device clock divider register(UHCCDR) */
+#define UHCCDR_UHPCS            BIT31
+
+#define UHCCDR_UHCDIV_LSB       0       /* UHCCDR bit */
+#define UHCCDR_UHCDIV_MASK      BITS_H2L(3, UHCCDR_UHCDIV_LSB)
+
+/* SSI clock divider register(SSICDR) */
+#define SSICDR_SCS              BIT31
+
+#define SSICDR_SSIDIV_LSB       0       /* SSICDR bit */
+#define SSICDR_SSIDIV_MASK      BITS_H2L(5, SSICDR_SSIDIV_LSB)
+
+/* CIM mclk clock divider register(CIMCDR) */
+#define CIMCDR_CIMDIV_LSB       0       /* CIMCDR bit */
+#define CIMCDR_CIMDIV_MASK      BITS_H2L(7, CIMCDR_CIMDIV_LSB)
+
+/* GPS clock divider register(GPSCDR) */
+#define GPSCDR_GPCS             BIT31
+
+#define GPSCDR_GPSDIV_LSB       0       /* GPSCDR bit */
+#define GSPCDR_GPSDIV_MASK      BITS_H2L(3, GPSCDR_GPSDIV_LSB)
+
+/* PCM device clock divider register(PCMCDR) */
+#define PCMCDR_PCMS             BIT31
+#define PCMCDR_PCMPCS           BIT30
+
+#define PCMCDR_PCMDIV_LSB       0       /* PCMCDR bit */
+#define PCMCDR_PCMDIV_MASK      BITS_H2L(8, PCMCDR_PCMDIV_LSB)
+
+/* GPU clock divider register */
+#define GPUCDR_GPCS             BIT31
+#define GPUCDR_GPUDIV_LSB       0       /* GPUCDR bit */
+#define GPUCDR_GPUDIV_MASK      BITS_H2L(2, GPUCDR_GPUDIV_LSB)
+
+
+#ifndef __MIPS_ASSEMBLER
+
+#define REG_CPM_CPCCR           REG32(CPM_CPCCR)
+#define REG_CPM_RSR             REG32(CPM_RSR)
+#define REG_CPM_CPPCR0          REG32(CPM_CPPCR0)
+#define REG_CPM_CPPSR           REG32(CPM_CPPSR)
+#define REG_CPM_CPPCR1          REG32(CPM_CPPCR1)
+#define REG_CPM_CPSPR           REG32(CPM_CPSPR)
+#define REG_CPM_CPSPPR          REG32(CPM_CPSPPR)
+#define REG_CPM_USBPCR          REG32(CPM_USBPCR)
+#define REG_CPM_USBRDT          REG32(CPM_USBRDT)
+#define REG_CPM_USBVBFIL        REG32(CPM_USBVBFIL)
+#define REG_CPM_USBCDR          REG32(CPM_USBCDR)
+#define REG_CPM_I2SCDR          REG32(CPM_I2SCDR)
+#define REG_CPM_LPCDR           REG32(CPM_LPCDR)
+#define REG_CPM_MSCCDR          REG32(CPM_MSCCDR)
+#define REG_CPM_UHCCDR          REG32(CPM_UHCCDR)
+#define REG_CPM_SSICDR          REG32(CPM_SSICDR)
+#define REG_CPM_CIMCDR          REG32(CPM_CIMCDR)
+#define REG_CPM_GPSCDR          REG32(CPM_GPSCDR)
+#define REG_CPM_PCMCDR          REG32(CPM_PCMCDR)
+#define REG_CPM_GPUCDR          REG32(CPM_GPUCDR)
+
+#define REG_CPM_PSWC0ST         REG32(CPM_PSWC0ST)
+#define REG_CPM_PSWC1ST         REG32(CPM_PSWC1ST)
+#define REG_CPM_PSWC2ST         REG32(CPM_PSWC2ST)
+#define REG_CPM_PSWC3ST         REG32(CPM_PSWC3ST)
+
+#define REG_CPM_LCR             REG32(CPM_LCR)
+#define REG_CPM_CLKGR0          REG32(CPM_CLKGR0)
+#define REG_CPM_OPCR            REG32(CPM_OPCR)
+#define REG_CPM_CLKGR1          REG32(CPM_CLKGR1)
+#define REG_CPM_CLKGR           REG32(CPM_CLKGR0)
+
+typedef enum {
+        CGM_NEMC = 0,
+        CGM_BCH  = 1,
+        CGM_OTG  = 2,
+        CGM_MSC0 = 3,
+        CGM_SSI0 = 4,
+        CGM_I2C0 = 5,
+        CGM_I2C1 = 6,
+        CGM_SCC  = 7,
+        CGM_AIC         = 8,
+        CGM_TSSI        = 9,
+        CGM_OWI         = 10,
+        CGM_MSC1        = 11,
+        CGM_MSC2        = 12,
+        CGM_KBC         = 13,
+        CGM_SADC        = 14,
+        CGM_UART0       = 15,
+        CGM_UART1 = 16,
+        CGM_UART2 = 17,
+        CGM_UART3 = 18,
+        CGM_SSI1  = 19,
+        CGM_SSI2  = 20,
+        CGM_DMAC  = 21,
+        CGM_GPS   = 22,
+        CGM_MAC   = 23,
+        CGM_UHC         = 24,
+        CGM_MDMA        = 25,
+        CGM_CIM         = 26,
+        CGM_TVE         = 27,
+        CGM_LCD         = 28,
+        CGM_IPU         = 29,
+        CGM_DDR         = 30,
+        CGM_EMC         = 31,
+        CGM_BDMA  = 32 + 0,
+        CGM_MC    = 32 + 1,
+        CGM_DBLK  = 32 + 2,
+        CGM_ME    = 32 + 3,
+        CGM_DCT   = 32 + 4,
+        CGM_SRAM  = 32 + 5,
+        CGM_CABAC = 32 + 6,
+        CGM_AHB1  = 32 + 7,
+        CGM_PCM         = 32 + 8,
+        CGM_GPU         = 32 + 9,
+        CGM_OSD         = 32 + 10,
+        CGM_AUX         = 32 + 11,
+        CGM_ALL_MODULE,
+} clock_gate_module;
+
+
+#define __CGU_CLOCK_BASE__      0x1000
+
+typedef enum {
+        /* Clock source is pll0 */
+        CGU_CCLK = __CGU_CLOCK_BASE__ + 0,
+        CGU_HCLK,
+        CGU_PCLK,
+        CGU_MCLK,
+        CGU_H2CLK,
+        CGU_SCLK,
+
+        /* Clock source is exclk, pll0 or pll0/2 */
+        CGU_MSCCLK,
+        CGU_SSICLK,
+
+        /* Clock source is pll0 or pll0/2 */
+        CGU_CIMCLK,
+
+        /* Clock source is exclk, pll0, pll0/2 or pll1 */
+        CGU_TVECLK,
+
+        /* Clock source is pll0 */
+        CGU_LPCLK,
+
+        /* Clock source is exclk, exclk/2, pll0, pll0/2 or pll1 */
+        CGU_I2SCLK,
+        CGU_PCMCLK,
+        CGU_OTGCLK,
+
+        /* Clock source is pll0, pll0/2 or pll1 */
+        CGU_UHCCLK,
+        CGU_GPSCLK,
+        CGU_GPUCLK,
+
+        /* Clock source is exclk or exclk/2 */
+        CGU_UARTCLK,
+        CGU_SADCCLK,
+
+        /* Clock source is exclk */
+        CGU_TCUCLK,
+
+	/* Clock source is external rtc clock */
+	CGU_RTCCLK,
+
+        CGU_CLOCK_MAX,
+} cgu_clock;
+
+/*
+ * JZ4760B clocks structure
+ */
+typedef struct {
+	unsigned int cclk;	/* CPU clock				*/
+	unsigned int hclk;	/* System bus clock: AHB0,AHB1		*/
+	unsigned int h1clk;	/* For compatible, the same as h1clk	*/
+	unsigned int h2clk;	/* System bus clock: AHB2		*/
+	unsigned int pclk;	/* Peripheral bus clock			*/
+	unsigned int mclk;	/* EMC or DDR controller clock		*/
+	unsigned int sclk;	/* NEMC controller clock		*/
+	unsigned int cko;	/* SDRAM or DDR clock			*/
+	unsigned int pixclk;	/* LCD pixel clock			*/
+	unsigned int tveclk;	/* TV encoder 27M  clock		*/
+	unsigned int cimmclk;	/* Clock output from CIM module		*/
+	unsigned int cimpclk;	/* Clock input to CIM module		*/
+	unsigned int gpuclk;	/* GPU clock				*/
+	unsigned int gpsclk;	/* GPS clock				*/
+	unsigned int i2sclk;	/* I2S codec clock			*/
+	unsigned int bitclk;	/* AC97 bit clock			*/
+	unsigned int pcmclk;	/* PCM clock				*/
+	unsigned int mscclk;	/* MSC clock				*/
+	unsigned int ssiclk;	/* SSI clock				*/
+	unsigned int tssiclk;	/* TSSI clock				*/
+	unsigned int otgclk;	/* USB OTG clock			*/
+	unsigned int uhcclk;	/* USB UHCI clock			*/
+	unsigned int extalclk;	/* EXTAL clock for
+				   UART,I2C,TCU,USB2.0-PHY,AUDIO CODEC	*/
+	unsigned int rtcclk;	/* RTC clock for CPM,INTC,RTC,TCU,WDT	*/
+} jz_clocks_t;
+
+void cpm_start_clock(clock_gate_module module_name);
+void cpm_stop_clock(clock_gate_module module_name);
+
+unsigned int cpm_set_clock(cgu_clock clock_name, unsigned int clock_hz);
+unsigned int cpm_get_clock(cgu_clock clock_name);
+unsigned int cpm_get_pllout(void);
+
+void cpm_uhc_phy(unsigned int en);
+
+/**************remove me if android's kernel support these operations********start*********  */
+#define __cpm_stop_lcd()	(REG_CPM_CLKGR0 |= CLKGR0_LCD)
+#define __cpm_start_lcd()	(REG_CPM_CLKGR0 &= ~CLKGR0_LCD)
+#define __cpm_set_pixdiv(v) \
+	(REG_CPM_LPCDR = (REG_CPM_LPCDR & ~LPCDR_PIXDIV_MASK) | ((v) << (LPCDR_PIXDIV_LSB)))
+
+#define __cpm_get_pixdiv() \
+	((REG_CPM_LPCDR & LPCDR_PIXDIV_MASK) >> LPCDR_PIXDIV_LSB)
+
+#define __cpm_select_pixclk_lcd()	(REG_CPM_LPCDR &= ~LPCDR_LTCS)
+#define __cpm_select_pixclk_tve()	(REG_CPM_LPCDR |= LPCDR_LTCS)
+
+static __inline__ unsigned int __cpm_get_pllout2(void)
+{
+#if defined(CONFIG_FPGA)
+	return cpm_get_pllout();
+#else
+	if (REG_CPM_CPCCR & CPCCR_PCS)
+		return cpm_get_pllout();
+	else
+		return cpm_get_pllout()/2;
+#endif
+}
+
+static __inline__ unsigned int __cpm_get_pixclk(void)
+{
+	return __cpm_get_pllout2() / (__cpm_get_pixdiv() + 1);
+}
+
+/* EXTAL clock */
+static __inline__ unsigned int __cpm_get_extalclk0(void)
+{
+	return JZ_EXTAL;
+}
+
+/* EXTAL clock for UART,I2C,SSI,SADC,USB-PHY */
+static __inline__ unsigned int __cpm_get_extalclk(void)
+{
+#if defined(CONFIG_FPGA)
+	return __cpm_get_extalclk0() / CFG_DIV;
+#else
+	if (REG_CPM_CPCCR & CPCCR_ECS)
+		return __cpm_get_extalclk0() / 2;
+	else
+		return __cpm_get_extalclk0();
+#endif
+
+}
+
+/* RTC clock for CPM,INTC,RTC,TCU,WDT */
+static __inline__ unsigned int __cpm_get_rtcclk(void)
+{
+	return JZ_EXTAL2;
+}
+
+extern jz_clocks_t jz_clocks;
+
+#define __cpm_select_i2sclk_exclk()	(REG_CPM_I2SCDR &= ~I2SCDR_I2CS)
+#define __cpm_enable_pll_change()	(REG_CPM_CPCCR |= CPCCR_CE)
+
+#define __cpm_suspend_otg_phy()		(REG_CPM_OPCR &= ~OPCR_OTGPHY_ENABLE)
+#define __cpm_enable_otg_phy()		(REG_CPM_OPCR |=  OPCR_OTGPHY_ENABLE)
+
+#define __cpm_suspend_uhc_phy()		(REG_CPM_OPCR |= OPCR_UHCPHY_DISABLE)
+#define __cpm_enable_uhc_phy()		(REG_CPM_OPCR &= ~OPCR_UHCPHY_DISABLE)
+#define __cpm_suspend_gps()        (REG_CPM_OPCR &= ~OPCR_GPSEN)
+#define __cpm_disable_osc_in_sleep()	(REG_CPM_OPCR &= ~OPCR_O1SE)
+#define __cpm_select_rtcclk_rtc()	(REG_CPM_OPCR |= OPCR_ERCS)
+
+#define __cpm_get_pllm() \
+	((REG_CPM_CPPCR0 & CPPCR0_PLLM_MASK) >> CPPCR0_PLLM_LSB)
+#define __cpm_get_plln() \
+	((REG_CPM_CPPCR0 & CPPCR0_PLLN_MASK) >> CPPCR0_PLLN_LSB)
+#define __cpm_get_pllod() \
+	((REG_CPM_CPPCR0 & CPPCR0_PLLOD_MASK) >> CPPCR0_PLLOD_LSB)
+
+#define __cpm_get_pll1m() \
+	((REG_CPM_CPPCR1 & CPPCR1_PLL1M_MASK) >> CPPCR1_PLL1M_LSB)
+#define __cpm_get_pll1n() \
+	((REG_CPM_CPPCR1 & CPPCR1_PLL1N_MASK) >> CPPCR1_PLL1N_LSB)
+#define __cpm_get_pll1od() \
+	((REG_CPM_CPPCR1 & CPPCR1_PLL1OD_MASK) >> CPPCR1_PLL1OD_LSB)
+
+#define __cpm_get_cdiv() \
+	((REG_CPM_CPCCR & CPCCR_CDIV_MASK) >> CPCCR_CDIV_LSB)
+#define __cpm_get_hdiv() \
+	((REG_CPM_CPCCR & CPCCR_HDIV_MASK) >> CPCCR_HDIV_LSB)
+#define __cpm_get_h2div() \
+	((REG_CPM_CPCCR & CPCCR_H2DIV_MASK) >> CPCCR_H2DIV_LSB)
+#define __cpm_get_otgdiv() \
+	((REG_CPM_USBCDR & USBCDR_OTGDIV_MASK) >> USBCDR_OTGDIV_LSB)
+#define __cpm_get_pdiv() \
+	((REG_CPM_CPCCR & CPCCR_PDIV_MASK) >> CPCCR_PDIV_LSB)
+#define __cpm_get_mdiv() \
+	((REG_CPM_CPCCR & CPCCR_MDIV_MASK) >> CPCCR_MDIV_LSB)
+#define __cpm_get_sdiv() \
+	((REG_CPM_CPCCR & CPCCR_SDIV_MASK) >> CPCCR_SDIV_LSB)
+#define __cpm_get_i2sdiv() \
+	((REG_CPM_I2SCDR & I2SCDR_I2SDIV_MASK) >> I2SCDR_I2SDIV_LSB)
+#define __cpm_get_pixdiv() \
+	((REG_CPM_LPCDR & LPCDR_PIXDIV_MASK) >> LPCDR_PIXDIV_LSB)
+#define __cpm_get_mscdiv() \
+	((REG_CPM_MSCCDR & MSCCDR_MSCDIV_MASK) >> MSCCDR_MSCDIV_LSB)
+
+/*
+#define __cpm_get_mscdiv(n) \
+	((REG_CPM_MSCCDR(n) & MSCCDR_MSCDIV_MASK) >> MSCCDR_MSCDIV_LSB)
+*/
+#define __cpm_get_ssidiv() \
+	((REG_CPM_SSICDR & SSICDR_SSIDIV_MASK) >> SSICDR_SSIDIV_LSB)
+#define __cpm_get_pcmdiv() \
+	((REG_CPM_PCMCDR & PCMCDR_PCMCD_MASK) >> PCMCDR_PCMCD_LSB)
+#define __cpm_get_pll1div() \
+	((REG_CPM_CPPCR1 & CPCCR1_P1SDIV_MASK) >> CPCCR1_P1SDIV_LSB)
+
+
+#define __cpm_set_ssidiv(v) \
+	(REG_CPM_SSICDR = (REG_CPM_SSICDR & ~SSICDR_SSIDIV_MASK) | ((v) << (SSICDR_SSIDIV_LSB)))
+
+#define __cpm_exclk_direct()		(REG_CPM_CPCCR &= ~CPM_CPCCR_ECS)
+#define __cpm_exclk_div2()          (REG_CPM_CPCCR |= CPM_CPCCR_ECS)
+#define __cpm_pllout_direct()		(REG_CPM_CPCCR |= CPM_CPCCR_PCS)
+#define __cpm_pllout_div2()			(REG_CPM_CPCCR &= ~CPM_CPCCR_PCS)
+
+#define __ssi_select_exclk()		(REG_CPM_SSICDR &= ~SSICDR_SCS)
+#define __ssi_select_pllclk()		(REG_CPM_SSICDR |= SSICDR_SCS)
+
+#define cpm_get_scrpad()	INREG32(CPM_CPSPR)
+#define cpm_set_scrpad(data)				\
+do {							\
+	OUTREG32(CPM_CPSPPR, CPSPPR_CPSPR_WRITABLE);	\
+	OUTREG32(CPM_CPSPR, data);			\
+	OUTREG32(CPM_CPSPPR, ~CPSPPR_CPSPR_WRITABLE);	\
+} while (0)
+
+/**************remove me if android's kernel support these operations********end*********  */
+
+extern int jz_pm_init(void);
+
+#endif /* __MIPS_ASSEMBLER */
+
+#endif /* __JZ4760BCPM_H__ */
diff --git a/arch/mips/include/asm/mach-jz4760b/jz4760bddrc.h b/arch/mips/include/asm/mach-jz4760b/jz4760bddrc.h
new file mode 100644
index 00000000000..fad4f896472
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4760b/jz4760bddrc.h
@@ -0,0 +1,345 @@
+/*

+ * linux/include/asm-mips/mach-jz4760b/jz4760bddrc.h

+ *

+ * JZ4760B DDRC register definition.

+ *

+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

+ */

+

+#ifndef __JZ4760BDDRC_H__

+#define __JZ4760BDDRC_H__

+

+

+#define	DDRC_BASE	0xB3020000

+

+/*************************************************************************

+ * DDRC (DDR Controller)

+ *************************************************************************/

+#define DDRC_ST		(DDRC_BASE + 0x0) /* DDR Status Register */

+#define DDRC_CFG	(DDRC_BASE + 0x4) /* DDR Configure Register */

+#define DDRC_CTRL	(DDRC_BASE + 0x8) /* DDR Control Register */

+#define DDRC_LMR	(DDRC_BASE + 0xc) /* DDR Load-Mode-Register */

+#define DDRC_TIMING1	(DDRC_BASE + 0x10) /* DDR Timing Config Register 1 */

+#define DDRC_TIMING2	(DDRC_BASE + 0x14) /* DDR Timing Config Register 2 */

+#define DDRC_REFCNT	(DDRC_BASE + 0x18) /* DDR  Auto-Refresh Counter */

+#define DDRC_DQS	(DDRC_BASE + 0x1c) /* DDR DQS Delay Control Register */

+#define DDRC_DQS_ADJ	(DDRC_BASE + 0x20) /* DDR DQS Delay Adjust Register */

+#define DDRC_MMAP0	(DDRC_BASE + 0x24) /* DDR Memory Map Config Register */

+#define DDRC_MMAP1	(DDRC_BASE + 0x28) /* DDR Memory Map Config Register */

+

+/* DDRC Register */

+#define REG_DDRC_ST		REG32(DDRC_ST)

+#define REG_DDRC_CFG		REG32(DDRC_CFG)

+#define REG_DDRC_CTRL		REG32(DDRC_CTRL)

+#define REG_DDRC_LMR		REG32(DDRC_LMR)

+#define REG_DDRC_TIMING1	REG32(DDRC_TIMING1)

+#define REG_DDRC_TIMING2	REG32(DDRC_TIMING2)

+#define REG_DDRC_REFCNT		REG32(DDRC_REFCNT)

+#define REG_DDRC_DQS		REG32(DDRC_DQS)

+#define REG_DDRC_DQS_ADJ	REG32(DDRC_DQS_ADJ)

+#define REG_DDRC_MMAP0		REG32(DDRC_MMAP0)

+#define REG_DDRC_MMAP1		REG32(DDRC_MMAP1)

+

+/* DDRC Status Register */

+#define DDRC_ST_ENDIAN	(1 << 7) /* 0 Little data endian

+					    1 Big data endian */

+#define DDRC_ST_DPDN		(1 << 5) /* 0 DDR memory is NOT in deep-power-down state

+					    1 DDR memory is in deep-power-down state */

+#define DDRC_ST_PDN		(1 << 4) /* 0 DDR memory is NOT in power-down state

+					    1 DDR memory is in power-down state */

+#define DDRC_ST_AREF		(1 << 3) /* 0 DDR memory is NOT in auto-refresh state

+					    1 DDR memory is in auto-refresh state */

+#define DDRC_ST_SREF		(1 << 2) /* 0 DDR memory is NOT in self-refresh state

+					    1 DDR memory is in self-refresh state */

+#define DDRC_ST_CKE1		(1 << 1) /* 0 CKE1 Pin is low

+					    1 CKE1 Pin is high */

+#define DDRC_ST_CKE0		(1 << 0) /* 0 CKE0 Pin is low

+					    1 CKE0 Pin is high */

+

+/* DDRC Configure Register */

+#define DDRC_CFG_MSEL_BIT	16 /* Mask delay select */

+#define DDRC_CFG_MSEL_MASK	(0x3 << DDRC_CFG_MSEL_BIT)

+  #define DDRC_CFG_MSEL_0	(0 << DDRC_CFG_MSEL_BIT) /* 00 No delay */

+  #define DDRC_CFG_MSEL_1	(1 << DDRC_CFG_MSEL_BIT) /* 01 delay 1 tCK */

+  #define DDRC_CFG_MSEL_2	(2 << DDRC_CFG_MSEL_BIT) /* 10 delay 2 tCK */

+  #define DDRC_CFG_MSEL_3	(3 << DDRC_CFG_MSEL_BIT) /* 11 delay 3 tCK */

+

+#define DDRC_CFG_HL		(1 << 15) /* 0: no extra delay 1: one extra half tCK delay */

+

+#define DDRC_CFG_ROW1_BIT	27 /* Row Address width. */

+#define DDRC_CFG_COL1_BIT	25 /* Row Address width. */

+#define DDRC_CFG_BA1_BIT	(1 << 24)

+#define DDRC_CFG_IMBA_BIT	(1 << 23)

+#define DDRC_CFG_BTRUN		(1 << 21)

+

+#define DDRC_CFG_TYPE_BIT	12

+#define DDRC_CFG_TYPE_MASK	(0x7 << DDRC_CFG_TYPE_BIT)

+#define DDRC_CFG_TYPE_DDR1	(2 << DDRC_CFG_TYPE_BIT)

+#define DDRC_CFG_TYPE_MDDR	(3 << DDRC_CFG_TYPE_BIT)

+#define DDRC_CFG_TYPE_DDR2	(4 << DDRC_CFG_TYPE_BIT)

+

+#define DDRC_CFG_ROW_BIT	10 /* Row Address width. */

+#define DDRC_CFG_ROW_MASK	(0x3 << DDRC_CFG_ROW_BIT)

+  #define DDRC_CFG_ROW_13	(0 << DDRC_CFG_ROW_BIT) /* 13-bit row address is used */

+  #define DDRC_CFG_ROW_14	(1 << DDRC_CFG_ROW_BIT) /* 14-bit row address is used */

+

+#define DDRC_CFG_COL_BIT	8 /* Column Address width.

+				     Specify the Column address width of external DDR. */

+#define DDRC_CFG_COL_MASK	(0x3 << DDRC_CFG_COL_BIT)

+  #define DDRC_CFG_COL_9	(0 << DDRC_CFG_COL_BIT) /* 9-bit Column address is used */

+  #define DDRC_CFG_COL_10	(1 << DDRC_CFG_COL_BIT) /* 10-bit Column address is used */

+

+#define DDRC_CFG_CS1EN	(1 << 7) /* 0 DDR Pin CS1 un-used

+					    1 There're DDR memory connected to CS1 */

+#define DDRC_CFG_CS0EN	(1 << 6) /* 0 DDR Pin CS0 un-used

+					    1 There're DDR memory connected to CS0 */

+

+#define DDRC_CFG_TSEL_BIT	18 /* Read delay select */

+#define DDRC_CFG_TSEL_MASK	(0x3 << DDRC_CFG_TSEL_BIT)

+#define DDRC_CFG_TSEL_0	(0 << DDRC_CFG_TSEL_BIT) /* No delay */

+#define DDRC_CFG_TSEL_1	(1 << DDRC_CFG_TSEL_BIT) /* delay 1 tCK */

+#define DDRC_CFG_TSEL_2	(2 << DDRC_CFG_TSEL_BIT) /* delay 2 tCK */

+#define DDRC_CFG_TSEL_3	(3 << DDRC_CFG_TSEL_BIT) /* delay 3 tCK */

+

+#define DDRC_CFG_CL_BIT	2 /* CAS Latency */

+#define DDRC_CFG_CL_MASK	(0xf << DDRC_CFG_CL_BIT)

+#define DDRC_CFG_CL_3		(0 << DDRC_CFG_CL_BIT) /* CL = 3 tCK */

+#define DDRC_CFG_CL_4		(1 << DDRC_CFG_CL_BIT) /* CL = 4 tCK */

+#define DDRC_CFG_CL_5		(2 << DDRC_CFG_CL_BIT) /* CL = 5 tCK */

+#define DDRC_CFG_CL_6		(3 << DDRC_CFG_CL_BIT) /* CL = 6 tCK */

+

+#define DDRC_CFG_BA		(1 << 1) /* 0 4 bank device, Pin ba[1:0] valid, ba[2] un-used

+					    1 8 bank device, Pin ba[2:0] valid*/

+#define DDRC_CFG_DW		(1 << 0) /*0 External memory data width is 16-bit

+					   1 External memory data width is 32-bit */

+

+/* DDRC Control Register */

+#define DDRC_CTRL_ACTPD	(1 << 15) /* 0 Precharge all banks before entering power-down

+					     1 Do not precharge banks before entering power-down */

+#define DDRC_CTRL_PDT_BIT	12 /* Power-Down Timer */

+#define DDRC_CTRL_PDT_MASK	(0x7 << DDRC_CTRL_PDT_BIT)

+  #define DDRC_CTRL_PDT_DIS	(0 << DDRC_CTRL_PDT_BIT) /* power-down disabled */

+  #define DDRC_CTRL_PDT_8	(1 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 8 tCK idle */

+  #define DDRC_CTRL_PDT_16	(2 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 16 tCK idle */

+  #define DDRC_CTRL_PDT_32	(3 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 32 tCK idle */

+  #define DDRC_CTRL_PDT_64	(4 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 64 tCK idle */

+  #define DDRC_CTRL_PDT_128	(5 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 128 tCK idle */

+

+#define DDRC_CTRL_PRET_BIT	8 /* Precharge Timer */

+#define DDRC_CTRL_PRET_MASK	(0x7 << DDRC_CTRL_PRET_BIT) /*  */

+  #define DDRC_CTRL_PRET_DIS	(0 << DDRC_CTRL_PRET_BIT) /* PRET function Disabled */

+  #define DDRC_CTRL_PRET_8	(1 << DDRC_CTRL_PRET_BIT) /* Precharge active bank after 8 tCK idle */

+  #define DDRC_CTRL_PRET_16	(2 << DDRC_CTRL_PRET_BIT) /* Precharge active bank after 16 tCK idle */

+  #define DDRC_CTRL_PRET_32	(3 << DDRC_CTRL_PRET_BIT) /* Precharge active bank after 32 tCK idle */

+  #define DDRC_CTRL_PRET_64	(4 << DDRC_CTRL_PRET_BIT) /* Precharge active bank after 64 tCK idle */

+  #define DDRC_CTRL_PRET_128	(5 << DDRC_CTRL_PRET_BIT) /* Precharge active bank after 128 tCK idle */

+

+#define DDRC_CTRL_SR		(1 << 5) /* 1 Drive external DDR device entering self-refresh mode

+					    0 Drive external DDR device exiting self-refresh mode */

+#define DDRC_CTRL_UNALIGN	(1 << 4) /* 0 Disable unaligned transfer on AXI BUS

+					    1 Enable unaligned transfer on AXI BUS */

+#define DDRC_CTRL_ALH		(1 << 3) /* Advanced Latency Hiding:

+					    0 Disable ALH

+					    1 Enable ALH */

+#define DDRC_CTRL_RDC		(1 << 2) /* 0 dclk clock frequency is lower than 60MHz

+					    1 dclk clock frequency is higher than 60MHz */

+#define DDRC_CTRL_CKE		(1 << 1) /* 0 Not set CKE Pin High

+					    1 Set CKE Pin HIGH */

+#define DDRC_CTRL_RESET	(1 << 0) /* 0 End resetting ddrc_controller

+					    1 Resetting ddrc_controller */

+

+/* DDRC Load-Mode-Register */

+#define DDRC_LMR_DDR_ADDR_BIT	16 /* When performing a DDR command, DDRC_ADDR[13:0]

+					      corresponding to external DDR address Pin A[13:0] */

+#define DDRC_LMR_DDR_ADDR_MASK	(0xff << DDRC_LMR_DDR_ADDR_BIT)

+

+#define DDRC_LMR_BA_BIT		8 /* When performing a DDR command, BA[2:0]

+				     corresponding to external DDR address Pin BA[2:0]. */

+#define DDRC_LMR_BA_MASK	(0x7 << DDRC_LMR_BA_BIT)

+  /* For DDR2 */

+  #define DDRC_LMR_BA_MRS	(0 << DDRC_LMR_BA_BIT) /* Mode Register set */

+  #define DDRC_LMR_BA_EMRS1	(1 << DDRC_LMR_BA_BIT) /* Extended Mode Register1 set */

+  #define DDRC_LMR_BA_EMRS2	(2 << DDRC_LMR_BA_BIT) /* Extended Mode Register2 set */

+  #define DDRC_LMR_BA_EMRS3	(3 << DDRC_LMR_BA_BIT) /* Extended Mode Register3 set */

+  /* For mobile DDR */

+  #define DDRC_LMR_BA_M_MRS	(0 << DDRC_LMR_BA_BIT) /* Mode Register set */

+  #define DDRC_LMR_BA_M_EMRS	(2 << DDRC_LMR_BA_BIT) /* Extended Mode Register set */

+  #define DDRC_LMR_BA_M_SR	(1 << DDRC_LMR_BA_BIT) /* Status Register set */

+

+#define DDRC_LMR_CMD_BIT	4

+#define DDRC_LMR_CMD_MASK	(0x3 << DDRC_LMR_CMD_BIT)

+  #define DDRC_LMR_CMD_PREC	(0 << DDRC_LMR_CMD_BIT)/* Precharge one bank/All banks */

+  #define DDRC_LMR_CMD_AUREF	(1 << DDRC_LMR_CMD_BIT)/* Auto-Refresh */

+  #define DDRC_LMR_CMD_LMR	(2 << DDRC_LMR_CMD_BIT)/* Load Mode Register */

+

+#define DDRC_LMR_START		(1 << 0) /* 0 No command is performed

+						    1 On the posedge of START, perform a command

+						    defined by CMD field */

+

+/* DDRC Mode Register Set */

+#define DDR_MRS_PD_BIT		(1 << 10) /* Active power down exit time */

+#define DDR_MRS_PD_MASK		(1 << DDR_MRS_PD_BIT) 

+  #define DDR_MRS_PD_FAST_EXIT	(0 << 10)

+  #define DDR_MRS_PD_SLOW_EXIT	(1 << 10)

+#define DDR_MRS_WR_BIT		(1 << 9) /* Write Recovery for autoprecharge */

+#define DDR_MRS_WR_MASK		(7 << DDR_MRS_WR_BIT)

+#define DDR_MRS_DLL_RST		(1 << 8) /* DLL Reset */

+#define DDR_MRS_TM_BIT		7        /* Operating Mode */

+#define DDR_MRS_TM_MASK		(1 << DDR_MRS_OM_BIT) 

+  #define DDR_MRS_TM_NORMAL	(0 << DDR_MRS_OM_BIT)

+  #define DDR_MRS_TM_TEST	(1 << DDR_MRS_OM_BIT)

+#define DDR_MRS_CAS_BIT		4        /* CAS Latency */

+#define DDR_MRS_CAS_MASK	(7 << DDR_MRS_CAS_BIT)

+#define DDR_MRS_BT_BIT		3        /* Burst Type */

+#define DDR_MRS_BT_MASK		(1 << DDR_MRS_BT_BIT)

+  #define DDR_MRS_BT_SEQ	(0 << DDR_MRS_BT_BIT) /* Sequential */

+  #define DDR_MRS_BT_INT	(1 << DDR_MRS_BT_BIT) /* Interleave */

+#define DDR_MRS_BL_BIT		0        /* Burst Length */

+#define DDR_MRS_BL_MASK		(7 << DDR_MRS_BL_BIT)

+  #define DDR_MRS_BL_4		(2 << DDR_MRS_BL_BIT)

+  #define DDR_MRS_BL_8		(3 << DDR_MRS_BL_BIT)

+

+/* DDRC Extended Mode Register1 Set */

+#define DDR_EMRS1_QOFF		(1<<12) /* 0 Output buffer enabled

+					   1 Output buffer disabled */

+#define DDR_EMRS1_RDQS_EN	(1<<11) /* 0 Disable

+					   1 Enable */

+#define DDR_EMRS1_DQS_DIS	(1<<10) /* 0 Enable

+					   1 Disable */

+#define DDR_EMRS1_OCD_BIT	7 /* Additive Latency 0 -> 6 */

+#define DDR_EMRS1_OCD_MASK	(0x7 << DDR_EMRS1_OCD_BIT)

+  #define DDR_EMRS1_OCD_EXIT		(0 << DDR_EMRS1_OCD_BIT)

+  #define DDR_EMRS1_OCD_D0		(1 << DDR_EMRS1_OCD_BIT)

+  #define DDR_EMRS1_OCD_D1		(2 << DDR_EMRS1_OCD_BIT)

+  #define DDR_EMRS1_OCD_ADJ		(4 << DDR_EMRS1_OCD_BIT)

+  #define DDR_EMRS1_OCD_DFLT		(7 << DDR_EMRS1_OCD_BIT)

+#define DDR_EMRS1_AL_BIT	3 /* Additive Latency 0 -> 6 */

+#define DDR_EMRS1_AL_MASK	(7 << DDR_EMRS1_AL_BIT)

+#define DDR_EMRS1_RTT_BIT	2 /*  */

+#define DDR_EMRS1_RTT_MASK	(0x11 << DDR_EMRS1_DIC_BIT) /* Bit 6, Bit 2 */

+#define DDR_EMRS1_DIC_BIT	1        /* Output Driver Impedence Control */

+#define DDR_EMRS1_DIC_MASK	(1 << DDR_EMRS1_DIC_BIT) /* 100% */

+  #define DDR_EMRS1_DIC_NORMAL	(0 << DDR_EMRS1_DIC_BIT) /* 60% */

+  #define DDR_EMRS1_DIC_HALF	(1 << DDR_EMRS1_DIC_BIT)

+#define DDR_EMRS1_DLL_BIT	0        /* DLL Enable  */

+#define DDR_EMRS1_DLL_MASK	(1 << DDR_EMRS1_DLL_BIT)

+  #define DDR_EMRS1_DLL_EN	(0 << DDR_EMRS1_DLL_BIT)

+  #define DDR_EMRS1_DLL_DIS	(1 << DDR_EMRS1_DLL_BIT)

+

+/* Mobile SDRAM Extended Mode Register */

+#define DDR_EMRS_DS_BIT		5	/* Driver strength */

+#define DDR_EMRS_DS_MASK	(7 << DDR_EMRS_DS_BIT)

+  #define DDR_EMRS_DS_FULL	(0 << DDR_EMRS_DS_BIT)	/*Full*/

+  #define DDR_EMRS_DS_HALF	(1 << DDR_EMRS_DS_BIT)	/*1/2 Strength*/

+  #define DDR_EMRS_DS_QUTR	(2 << DDR_EMRS_DS_BIT)	/*1/4 Strength*/

+  #define DDR_EMRS_DS_OCTANT	(3 << DDR_EMRS_DS_BIT)	/*1/8 Strength*/

+  #define DDR_EMRS_DS_QUTR3	(4 << DDR_EMRS_DS_BIT)	/*3/4 Strength*/

+

+#define DDR_EMRS_PRSR_BIT	0	/* Partial Array Self Refresh */

+#define DDR_EMRS_PRSR_MASK	(7 << DDR_EMRS_PRSR_BIT)

+  #define DDR_EMRS_PRSR_ALL	(0 << DDR_EMRS_PRSR_BIT) /*All Banks*/

+  #define DDR_EMRS_PRSR_HALF_TL	(1 << DDR_EMRS_PRSR_BIT) /*Half of Total Bank*/

+  #define DDR_EMRS_PRSR_QUTR_TL	(2 << DDR_EMRS_PRSR_BIT) /*Quarter of Total Bank*/

+  #define DDR_EMRS_PRSR_HALF_B0	(5 << DDR_EMRS_PRSR_BIT) /*Half of Bank0*/

+  #define DDR_EMRS_PRSR_QUTR_B0	(6 << DDR_EMRS_PRSR_BIT) /*Quarter of Bank0*/

+

+

+/* DDRC Timing Config Register 1 */

+#define DDRC_TIMING1_TRAS_BIT 	28 /* ACTIVE to PRECHARGE command period (2 * tRAS + 1) */

+#define DDRC_TIMING1_TRAS_MASK 	(0xf << DDRC_TIMING1_TRAS_BIT)

+

+

+#define DDRC_TIMING1_TRTP_BIT		24 /* READ to PRECHARGE command period. */

+#define DDRC_TIMING1_TRTP_MASK	(0x3 << DDRC_TIMING1_TRTP_BIT)

+

+#define DDRC_TIMING1_TRP_BIT		20 /* PRECHARGE command period. */

+#define DDRC_TIMING1_TRP_MASK 	(0x7 << DDRC_TIMING1_TRP_BIT)

+

+#define DDRC_TIMING1_TRCD_BIT		16 /* ACTIVE to READ or WRITE command period. */

+#define DDRC_TIMING1_TRCD_MASK	(0x7 << DDRC_TIMING1_TRCD_BIT)

+

+#define DDRC_TIMING1_TRC_BIT 		12 /* ACTIVE to ACTIVE command period. */

+#define DDRC_TIMING1_TRC_MASK 	(0xf << DDRC_TIMING1_TRC_BIT)

+

+#define DDRC_TIMING1_TRRD_BIT		8 /* ACTIVE bank A to ACTIVE bank B command period. */

+#define DDRC_TIMING1_TRRD_MASK	(0x3 << DDRC_TIMING1_TRRD_BIT)

+#define DDRC_TIMING1_TRRD_DISABLE	(0 << DDRC_TIMING1_TRRD_BIT)

+#define DDRC_TIMING1_TRRD_2		(1 << DDRC_TIMING1_TRRD_BIT)

+#define DDRC_TIMING1_TRRD_3		(2 << DDRC_TIMING1_TRRD_BIT)

+#define DDRC_TIMING1_TRRD_4		(3 << DDRC_TIMING1_TRRD_BIT)

+

+#define DDRC_TIMING1_TWR_BIT 		4 /* WRITE Recovery Time defined by register MR of DDR2 memory */

+#define DDRC_TIMING1_TWR_MASK		(0x7 << DDRC_TIMING1_TWR_BIT)

+  #define DDRC_TIMING1_TWR_1		(0 << DDRC_TIMING1_TWR_BIT)

+  #define DDRC_TIMING1_TWR_2		(1 << DDRC_TIMING1_TWR_BIT)

+  #define DDRC_TIMING1_TWR_3		(2 << DDRC_TIMING1_TWR_BIT)

+  #define DDRC_TIMING1_TWR_4		(3 << DDRC_TIMING1_TWR_BIT)

+  #define DDRC_TIMING1_TWR_5		(4 << DDRC_TIMING1_TWR_BIT)

+  #define DDRC_TIMING1_TWR_6		(5 << DDRC_TIMING1_TWR_BIT)

+

+#define DDRC_TIMING1_TWTR_BIT		0 /* WRITE to READ command delay. */

+#define DDRC_TIMING1_TWTR_MASK	(0x3 << DDRC_TIMING1_TWTR_BIT)

+  #define DDRC_TIMING1_TWTR_1		(0 << DDRC_TIMING1_TWTR_BIT)

+  #define DDRC_TIMING1_TWTR_2		(1 << DDRC_TIMING1_TWTR_BIT)

+  #define DDRC_TIMING1_TWTR_3		(2 << DDRC_TIMING1_TWTR_BIT)

+  #define DDRC_TIMING1_TWTR_4		(3 << DDRC_TIMING1_TWTR_BIT)

+

+/* DDRC Timing Config Register 2 */

+#define DDRC_TIMING2_TRFC_BIT         12 /* AUTO-REFRESH command period. */

+#define DDRC_TIMING2_TRFC_MASK        (0xf << DDRC_TIMING2_TRFC_BIT)

+#define DDRC_TIMING2_TMINSR_BIT       8  /* Minimum Self-Refresh / Deep-Power-Down time */

+#define DDRC_TIMING2_TMINSR_MASK      (0xf << DDRC_TIMING2_TMINSR_BIT)

+#define DDRC_TIMING2_TXP_BIT          4  /* EXIT-POWER-DOWN to next valid command period. */

+#define DDRC_TIMING2_TXP_MASK         (0x7 << DDRC_TIMING2_TXP_BIT)

+#define DDRC_TIMING2_TMRD_BIT         0  /* Load-Mode-Register to next valid command period. */

+#define DDRC_TIMING2_TMRD_MASK        (0x3 << DDRC_TIMING2_TMRD_BIT)

+

+/* DDRC  Auto-Refresh Counter */

+#define DDRC_REFCNT_CON_BIT           16 /* Constant value used to compare with CNT value. */

+#define DDRC_REFCNT_CON_MASK          (0xff << DDRC_REFCNT_CON_BIT)

+#define DDRC_REFCNT_CNT_BIT           8  /* 8-bit counter */

+#define DDRC_REFCNT_CNT_MASK          (0xff << DDRC_REFCNT_CNT_BIT)

+#define DDRC_REFCNT_CLKDIV_BIT        1  /* Clock Divider for auto-refresh counter. */

+#define DDRC_REFCNT_CLKDIV_MASK       (0x7 << DDRC_REFCNT_CLKDIV_BIT)

+#define DDRC_REFCNT_REF_EN            (1 << 0) /* Enable Refresh Counter */

+

+/* DDRC DQS Delay Control Register */

+#define DDRC_DQS_ERROR                (1 << 29) /* ahb_clk Delay Detect ERROR, read-only. */

+#define DDRC_DQS_READY                (1 << 28) /* ahb_clk Delay Detect READY, read-only. */

+#define DDRC_DQS_AUTO                 (1 << 23) /* Hardware auto-detect & set delay line */

+#define DDRC_DQS_DET                  (1 << 24) /* Start delay detecting. */

+#define DDRC_DQS_CLKD_BIT             16 /* CLKD is reference value for setting WDQS and RDQS.*/

+#define DDRC_DQS_CLKD_MASK            (0x7f << DDRC_DQS_CLKD_BIT) 

+#define DDRC_DQS_WDQS_BIT             8  /* Set delay element number to write DQS delay-line. */

+#define DDRC_DQS_WDQS_MASK            (0x3f << DDRC_DQS_WDQS_BIT) 

+#define DDRC_DQS_RDQS_BIT             0  /* Set delay element number to read DQS delay-line. */

+#define DDRC_DQS_RDQS_MASK            (0x3f << DDRC_DQS_RDQS_BIT) 

+

+/* DDRC DQS Delay Adjust Register */

+#define DDRC_DQS_ADJWDQS_BIT          8 /* The adjust value for WRITE DQS delay */

+#define DDRC_DQS_ADJWDQS_MASK         (0x1f << DDRC_DQS_ADJWDQS_BIT)

+#define DDRC_DQS_ADJRDQS_BIT          0 /* The adjust value for READ DQS delay */

+#define DDRC_DQS_ADJRDQS_MASK         (0x1f << DDRC_DQS_ADJRDQS_BIT)

+

+/* DDRC Memory Map Config Register */

+#define DDRC_MMAP_BASE_BIT            8 /* base address */

+#define DDRC_MMAP_BASE_MASK           (0xff << DDRC_MMAP_BASE_BIT)

+#define DDRC_MMAP_MASK_BIT            0 /* address mask */

+#define DDRC_MMAP_MASK_MASK           (0xff << DDRC_MMAP_MASK_BIT)         

+

+#define DDRC_MMAP0_BASE		     (0x20 << DDRC_MMAP_BASE_BIT)

+#define DDRC_MMAP1_BASE_64M	(0x24 << DDRC_MMAP_BASE_BIT) /*when bank0 is 128M*/

+#define DDRC_MMAP1_BASE_128M	(0x28 << DDRC_MMAP_BASE_BIT) /*when bank0 is 128M*/

+#define DDRC_MMAP1_BASE_256M	(0x30 << DDRC_MMAP_BASE_BIT) /*when bank0 is 128M*/

+

+#define DDRC_MMAP_MASK_64_64	(0xfc << DDRC_MMAP_MASK_BIT)  /*mask for two 128M SDRAM*/

+#define DDRC_MMAP_MASK_128_128	(0xf8 << DDRC_MMAP_MASK_BIT)  /*mask for two 128M SDRAM*/

+#define DDRC_MMAP_MASK_256_256	(0xf0 << DDRC_MMAP_MASK_BIT)  /*mask for two 128M SDRAM*/

+

+

+#ifndef __MIPS_ASSEMBLER

+

+#endif /* __MIPS_ASSEMBLER */

+

+#endif /* __JZ4760BDDRC_H__ */

+

diff --git a/arch/mips/include/asm/mach-jz4760b/jz4760bdmac.h b/arch/mips/include/asm/mach-jz4760b/jz4760bdmac.h
new file mode 100644
index 00000000000..914c839217c
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4760b/jz4760bdmac.h
@@ -0,0 +1,387 @@
+/*

+ * linux/include/asm-mips/mach-jz4760b/jz4760bdmac.h

+ *

+ * JZ4760B DMAC register definition.

+ *

+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

+ */

+

+#ifndef __JZ4760BDMAC_H__

+#define __JZ4760BDMAC_H__

+

+

+#define DMAC_BASE	0xB3420000

+

+

+/*************************************************************************

+ * DMAC (DMA Controller)

+ *************************************************************************/

+

+#define MAX_DMA_NUM 	12  /* max 12 channels */

+#define MAX_MDMA_NUM    3   /* max 3  channels */

+#define MAX_BDMA_NUM	3   /* max 3  channels */

+#define HALF_DMA_NUM	6   /* the number of one dma controller's channels */

+

+/* m is the DMA controller index (0, 1), n is the DMA channel index (0 - 11) */

+

+#define DMAC_DSAR(n)  (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0x00 + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x20)) /* DMA source address */

+#define DMAC_DTAR(n)  (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0x04 + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x20)) /* DMA target address */

+#define DMAC_DTCR(n)  (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0x08 + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x20)) /* DMA transfer count */

+#define DMAC_DRSR(n)  (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0x0c + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x20)) /* DMA request source */

+#define DMAC_DCCSR(n) (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0x10 + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x20)) /* DMA control/status */

+#define DMAC_DCMD(n)  (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0x14 + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x20)) /* DMA command */

+#define DMAC_DDA(n)   (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0x18 + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x20)) /* DMA descriptor address */

+#define DMAC_DSD(n)   (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0x1c + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x04)) /* DMA Stride Address */

+

+#define DMAC_DMACR(m)	(DMAC_BASE + 0x0300 + 0x100 * (m))              /* DMA control register */

+#define DMAC_DMAIPR(m)	(DMAC_BASE + 0x0304 + 0x100 * (m))              /* DMA interrupt pending */

+#define DMAC_DMADBR(m)	(DMAC_BASE + 0x0308 + 0x100 * (m))              /* DMA doorbell */

+#define DMAC_DMADBSR(m)	(DMAC_BASE + 0x030C + 0x100 * (m))              /* DMA doorbell set */

+#define DMAC_DMACK(m)  (DMAC_BASE + 0x0310 + 0x100 * (m))

+#define DMAC_DMACKS(m)  (DMAC_BASE + 0x0314 + 0x100 * (m))

+#define DMAC_DMACKC(m)  (DMAC_BASE + 0x0318 + 0x100 * (m))

+

+#define REG_DMAC_DSAR(n)	REG32(DMAC_DSAR((n)))

+#define REG_DMAC_DTAR(n)	REG32(DMAC_DTAR((n)))

+#define REG_DMAC_DTCR(n)	REG32(DMAC_DTCR((n)))

+#define REG_DMAC_DRSR(n)	REG32(DMAC_DRSR((n)))

+#define REG_DMAC_DCCSR(n)	REG32(DMAC_DCCSR((n)))

+#define REG_DMAC_DCMD(n)	REG32(DMAC_DCMD((n)))

+#define REG_DMAC_DDA(n)		REG32(DMAC_DDA((n)))

+#define REG_DMAC_DSD(n)         REG32(DMAC_DSD(n))

+#define REG_DMAC_DMACR(m)	REG32(DMAC_DMACR(m))

+#define REG_DMAC_DMAIPR(m)	REG32(DMAC_DMAIPR(m))

+#define REG_DMAC_DMADBR(m)	REG32(DMAC_DMADBR(m))

+#define REG_DMAC_DMADBSR(m)	REG32(DMAC_DMADBSR(m))

+#define REG_DMAC_DMACK(m)      REG32(DMAC_DMACK(m))

+#define REG_DMAC_DMACKS(m)      REG32(DMAC_DMACKS(m))

+#define REG_DMAC_DMACKC(m)      REG32(DMAC_DMACKC(m))

+

+// DMA request source register

+#define DMAC_DRSR_RS_BIT	0

+#define DMAC_DRSR_RS_MASK	(0x3f << DMAC_DRSR_RS_BIT)

+/* 0~7 is reserved */

+#define DMAC_DRSR_RS_AUTO	(8 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_TSSIIN	(9 << DMAC_DRSR_RS_BIT)

+/* 10 ~ 11 is reserved */

+#define DMAC_DRSR_RS_EXTERN	(12 << DMAC_DRSR_RS_BIT)

+/* 13 is reserved */

+#define DMAC_DRSR_RS_UART3OUT	(14 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_UART3IN	(15 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_UART2OUT	(16 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_UART2IN	(17 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_UART1OUT	(18 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_UART1IN	(19 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_UART0OUT	(20 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_UART0IN	(21 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_SSI0OUT	(22 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_SSI0IN	(23 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_AICOUT	(24 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_AICIN	(25 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_MSC0OUT	(26 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_MSC0IN	(27 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_TCU	(28 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_SADC	(29 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_MSC1OUT	(30 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_MSC1IN	(31 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_SSI1OUT	(32 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_SSI1IN	(33 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_PMOUT	(34 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_PMIN	(35 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_MSC2OUT	(36 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_MSC2IN	(37 << DMAC_DRSR_RS_BIT)

+/* others are reserved */

+

+// DMA channel control/status register

+#define DMAC_DCCSR_NDES		(1 << 31) /* descriptor (0) or not (1) ? */

+#define DMAC_DCCSR_DES8    	(1 << 30) /* Descriptor 8 Word */

+#define DMAC_DCCSR_DES4    	(0 << 30) /* Descriptor 4 Word */

+/* [29:24] reserved */

+#define DMAC_DCCSR_CDOA_BIT	16        /* copy of DMA offset address */

+#define DMAC_DCCSR_CDOA_MASK	(0xff << DMAC_DCCSR_CDOA_BIT)

+/* [15:5] reserved */

+#define DMAC_DCCSR_AR		(1 << 4)  /* address error */

+#define DMAC_DCCSR_TT		(1 << 3)  /* transfer terminated */

+#define DMAC_DCCSR_HLT		(1 << 2)  /* DMA halted */

+#define DMAC_DCCSR_CT		(1 << 1)  /* count terminated */

+#define DMAC_DCCSR_EN		(1 << 0)  /* channel enable bit */

+

+// DMA channel command register

+#define DMAC_DCMD_EACKS_LOW  	(1 << 31) /* External DACK Output Level Select, active low */

+#define DMAC_DCMD_EACKS_HIGH  	(0 << 31) /* External DACK Output Level Select, active high */

+#define DMAC_DCMD_EACKM_WRITE 	(1 << 30) /* External DACK Output Mode Select, output in write cycle */

+#define DMAC_DCMD_EACKM_READ 	(0 << 30) /* External DACK Output Mode Select, output in read cycle */

+#define DMAC_DCMD_ERDM_BIT      28        /* External DREQ Detection Mode Select */

+#define DMAC_DCMD_ERDM_MASK     (0x03 << DMAC_DCMD_ERDM_BIT)

+#define DMAC_DCMD_ERDM_LOW    (0 << DMAC_DCMD_ERDM_BIT)

+#define DMAC_DCMD_ERDM_FALL   (1 << DMAC_DCMD_ERDM_BIT)

+#define DMAC_DCMD_ERDM_HIGH   (2 << DMAC_DCMD_ERDM_BIT)

+#define DMAC_DCMD_ERDM_RISE   (3 << DMAC_DCMD_ERDM_BIT)

+/* [27:24] reserved */

+#define DMAC_DCMD_SAI		(1 << 23) /* source address increment */

+#define DMAC_DCMD_DAI		(1 << 22) /* dest address increment */

+#define DMAC_DCMD_RDIL_BIT	16        /* request detection interval length */

+#define DMAC_DCMD_RDIL_MASK	(0x0f << DMAC_DCMD_RDIL_BIT)

+#define DMAC_DCMD_RDIL_IGN	(0 << DMAC_DCMD_RDIL_BIT)

+#define DMAC_DCMD_RDIL_2	(1 << DMAC_DCMD_RDIL_BIT)

+#define DMAC_DCMD_RDIL_4	(2 << DMAC_DCMD_RDIL_BIT)

+#define DMAC_DCMD_RDIL_8	(3 << DMAC_DCMD_RDIL_BIT)

+#define DMAC_DCMD_RDIL_12	(4 << DMAC_DCMD_RDIL_BIT)

+#define DMAC_DCMD_RDIL_16	(5 << DMAC_DCMD_RDIL_BIT)

+#define DMAC_DCMD_RDIL_20	(6 << DMAC_DCMD_RDIL_BIT)

+#define DMAC_DCMD_RDIL_24	(7 << DMAC_DCMD_RDIL_BIT)

+#define DMAC_DCMD_RDIL_28	(8 << DMAC_DCMD_RDIL_BIT)

+#define DMAC_DCMD_RDIL_32	(9 << DMAC_DCMD_RDIL_BIT)

+#define DMAC_DCMD_RDIL_48	(10 << DMAC_DCMD_RDIL_BIT)

+#define DMAC_DCMD_RDIL_60	(11 << DMAC_DCMD_RDIL_BIT)

+#define DMAC_DCMD_RDIL_64	(12 << DMAC_DCMD_RDIL_BIT)

+#define DMAC_DCMD_RDIL_124	(13 << DMAC_DCMD_RDIL_BIT)

+#define DMAC_DCMD_RDIL_128	(14 << DMAC_DCMD_RDIL_BIT)

+#define DMAC_DCMD_RDIL_200	(15 << DMAC_DCMD_RDIL_BIT)

+#define DMAC_DCMD_SWDH_BIT	14  /* source port width */

+#define DMAC_DCMD_SWDH_MASK	(0x03 << DMAC_DCMD_SWDH_BIT)

+#define DMAC_DCMD_SWDH_32	(0 << DMAC_DCMD_SWDH_BIT)

+#define DMAC_DCMD_SWDH_8	(1 << DMAC_DCMD_SWDH_BIT)

+#define DMAC_DCMD_SWDH_16	(2 << DMAC_DCMD_SWDH_BIT)

+#define DMAC_DCMD_DWDH_BIT	12  /* dest port width */

+#define DMAC_DCMD_DWDH_MASK	(0x03 << DMAC_DCMD_DWDH_BIT)

+#define DMAC_DCMD_DWDH_32	(0 << DMAC_DCMD_DWDH_BIT)

+#define DMAC_DCMD_DWDH_8	(1 << DMAC_DCMD_DWDH_BIT)

+#define DMAC_DCMD_DWDH_16	(2 << DMAC_DCMD_DWDH_BIT)

+/* bit11 reserved */

+#define DMAC_DCMD_DS_BIT	8  /* transfer data size of a data unit */

+#define DMAC_DCMD_DS_MASK	(0x07 << DMAC_DCMD_DS_BIT)

+#define DMAC_DCMD_DS_32BIT	(0 << DMAC_DCMD_DS_BIT)

+#define DMAC_DCMD_DS_8BIT	(1 << DMAC_DCMD_DS_BIT)

+#define DMAC_DCMD_DS_16BIT	(2 << DMAC_DCMD_DS_BIT)

+#define DMAC_DCMD_DS_16BYTE	(3 << DMAC_DCMD_DS_BIT)

+#define DMAC_DCMD_DS_32BYTE	(4 << DMAC_DCMD_DS_BIT)

+#define DMAC_DCMD_DS_64BYTE	(5 << DMAC_DCMD_DS_BIT)

+/* [7:3] reserved */

+#define DMAC_DCMD_STDE   	(1 << 2)  /* Stride Disable/Enable */

+#define DMAC_DCMD_TIE		(1 << 1)  /* DMA transfer interrupt enable */

+#define DMAC_DCMD_LINK		(1 << 0)  /* descriptor link enable */

+

+// DMA descriptor address register

+#define DMAC_DDA_BASE_BIT	12  /* descriptor base address */

+#define DMAC_DDA_BASE_MASK	(0x0fffff << DMAC_DDA_BASE_BIT)

+#define DMAC_DDA_OFFSET_BIT	4   /* descriptor offset address */

+#define DMAC_DDA_OFFSET_MASK	(0x0ff << DMAC_DDA_OFFSET_BIT)

+/* [3:0] reserved */

+

+// DMA stride address register

+#define DMAC_DSD_TSD_BIT        16  /* target stride address */

+#define DMAC_DSD_TSD_MASK      	(0xffff << DMAC_DSD_TSD_BIT)

+#define DMAC_DSD_SSD_BIT        0  /* source stride address */

+#define DMAC_DSD_SSD_MASK      	(0xffff << DMAC_DSD_SSD_BIT)

+

+// DMA control register

+#define DMAC_DMACR_FMSC		(1 << 31)  /* MSC Fast DMA mode */

+#define DMAC_DMACR_FSSI		(1 << 30)  /* SSI Fast DMA mode */

+#define DMAC_DMACR_FTSSI	(1 << 29)  /* TSSI Fast DMA mode */

+#define DMAC_DMACR_FUART	(1 << 28)  /* UART Fast DMA mode */

+#define DMAC_DMACR_FAIC		(1 << 27)  /* AIC Fast DMA mode */

+/* [26:10] reserved */

+#define DMAC_DMACR_PR_BIT	8  /* channel priority mode */

+#define DMAC_DMACR_PR_MASK	(0x03 << DMAC_DMACR_PR_BIT)

+#define DMAC_DMACR_PR_012345	(0 << DMAC_DMACR_PR_BIT)

+#define DMAC_DMACR_PR_120345	(1 << DMAC_DMACR_PR_BIT)

+#define DMAC_DMACR_PR_230145	(2 << DMAC_DMACR_PR_BIT)

+#define DMAC_DMACR_PR_340125	(3 << DMAC_DMACR_PR_BIT)

+/* [7:4] resered */

+#define DMAC_DMACR_HLT		(1 << 3)  /* DMA halt flag */

+#define DMAC_DMACR_AR		(1 << 2)  /* address error flag */

+/* bit1 reserved */

+#define DMAC_DMACR_DMAE		(1 << 0)  /* DMA enable bit */

+

+// DMA doorbell register

+#define DMAC_DMADBR_DB5		(1 << 5)  /* doorbell for channel 5 */

+#define DMAC_DMADBR_DB4		(1 << 4)  /* doorbell for channel 4 */

+#define DMAC_DMADBR_DB3		(1 << 3)  /* doorbell for channel 3 */

+#define DMAC_DMADBR_DB2		(1 << 2)  /* doorbell for channel 2 */

+#define DMAC_DMADBR_DB1		(1 << 1)  /* doorbell for channel 1 */

+#define DMAC_DMADBR_DB0		(1 << 0)  /* doorbell for channel 0 */

+

+// DMA doorbell set register

+#define DMAC_DMADBSR_DBS5	(1 << 5)  /* enable doorbell for channel 5 */

+#define DMAC_DMADBSR_DBS4	(1 << 4)  /* enable doorbell for channel 4 */

+#define DMAC_DMADBSR_DBS3	(1 << 3)  /* enable doorbell for channel 3 */

+#define DMAC_DMADBSR_DBS2	(1 << 2)  /* enable doorbell for channel 2 */

+#define DMAC_DMADBSR_DBS1	(1 << 1)  /* enable doorbell for channel 1 */

+#define DMAC_DMADBSR_DBS0	(1 << 0)  /* enable doorbell for channel 0 */

+

+// DMA interrupt pending register

+#define DMAC_DMAIPR_CIRQ5	(1 << 5)  /* irq pending status for channel 5 */

+#define DMAC_DMAIPR_CIRQ4	(1 << 4)  /* irq pending status for channel 4 */

+#define DMAC_DMAIPR_CIRQ3	(1 << 3)  /* irq pending status for channel 3 */

+#define DMAC_DMAIPR_CIRQ2	(1 << 2)  /* irq pending status for channel 2 */

+#define DMAC_DMAIPR_CIRQ1	(1 << 1)  /* irq pending status for channel 1 */

+#define DMAC_DMAIPR_CIRQ0	(1 << 0)  /* irq pending status for channel 0 */

+

+

+#ifndef __MIPS_ASSEMBLER

+

+

+/***************************************************************************

+ * DMAC

+ ***************************************************************************/

+

+/* m is the DMA controller index (0, 1), n is the DMA channel index (0 - 11) */

+

+#define __dmac_enable_module(m)						\

+	( REG_DMAC_DMACR(m) |= DMAC_DMACR_DMAE | DMAC_DMACR_PR_012345 )

+#define __dmac_disable_module(m)			\

+	( REG_DMAC_DMACR(m) &= ~DMAC_DMACR_DMAE )

+

+/* p=0,1,2,3 */

+#define __dmac_set_priority(m,p)					\

+	do {								\

+		REG_DMAC_DMACR(m) &= ~DMAC_DMACR_PR_MASK;		\

+		REG_DMAC_DMACR(m) |= ((p) << DMAC_DMACR_PR_BIT);	\

+	} while (0)

+

+#define __dmac_test_halt_error(m) ( REG_DMAC_DMACR(m) & DMAC_DMACR_HLT )

+#define __dmac_test_addr_error(m) ( REG_DMAC_DMACR(m) & DMAC_DMACR_AR )

+

+#define __dmac_channel_enable_clk(n)					\

+	REG_DMAC_DMACKS((n)/HALF_DMA_NUM) |= 1 << ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM);

+

+#define __dmac_channel_clear_clk(n)					\

+	REG_DMAC_DMACKC((n)/HALF_DMA_NUM) |= 1 << ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM);

+

+#define __dmac_enable_descriptor(n)			\

+	( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_NDES )

+#define __dmac_disable_descriptor(n)			\

+	( REG_DMAC_DCCSR((n)) |= DMAC_DCCSR_NDES )

+

+#define __dmac_enable_channel(n)			\

+	do {						\

+		REG_DMAC_DCCSR((n)) |= DMAC_DCCSR_EN;	\

+	} while (0)

+#define __dmac_disable_channel(n)			\

+	do {						\

+		REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_EN;	\

+	} while (0)

+#define __dmac_channel_enabled(n)		\

+	( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_EN )

+

+#define __dmac_channel_enable_irq(n)		\

+	( REG_DMAC_DCMD((n)) |= DMAC_DCMD_TIE )

+#define __dmac_channel_disable_irq(n)			\

+	( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_TIE )

+

+#define __dmac_channel_transmit_halt_detected(n)	\

+	(  REG_DMAC_DCCSR((n)) & DMAC_DCCSR_HLT )

+#define __dmac_channel_transmit_end_detected(n)		\

+	(  REG_DMAC_DCCSR((n)) & DMAC_DCCSR_TT )

+#define __dmac_channel_address_error_detected(n)	\

+	(  REG_DMAC_DCCSR((n)) & DMAC_DCCSR_AR )

+#define __dmac_channel_count_terminated_detected(n)	\

+	(  REG_DMAC_DCCSR((n)) & DMAC_DCCSR_CT )

+#define __dmac_channel_descriptor_invalid_detected(n)	\

+	(  REG_DMAC_DCCSR((n)) & DMAC_DCCSR_INV )

+

+#define __dmac_channel_clear_transmit_halt(n)				\

+	do {								\

+		/* clear both channel halt error and globle halt error */ \

+		REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_HLT;			\

+		REG_DMAC_DMACR(n/HALF_DMA_NUM) &= ~DMAC_DMACR_HLT;	\

+	} while (0)

+#define __dmac_channel_clear_transmit_end(n)		\

+	(  REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_TT )

+#define __dmac_channel_clear_address_error(n)				\

+	do {								\

+		REG_DMAC_DDA(n) = 0; /* clear descriptor address register */ \

+		REG_DMAC_DSAR(n) = 0; /* clear source address register */ \

+		REG_DMAC_DTAR(n) = 0; /* clear target address register */ \

+		/* clear both channel addr error and globle address error */ \

+		REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_AR;			\

+		REG_DMAC_DMACR(n/HALF_DMA_NUM) &= ~DMAC_DMACR_AR;	\

+	} while (0)

+#define __dmac_channel_clear_count_terminated(n)	\

+	(  REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_CT )

+#define __dmac_channel_clear_descriptor_invalid(n)	\

+	(  REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_INV )

+

+#define __dmac_channel_set_transfer_unit_32bit(n)		\

+	do {							\

+		REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK;	\

+		REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_32BIT;	\

+	} while (0)

+

+#define __dmac_channel_set_transfer_unit_16bit(n)		\

+	do {							\

+		REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK;	\

+		REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_16BIT;	\

+	} while (0)

+

+#define __dmac_channel_set_transfer_unit_8bit(n)		\

+	do {							\

+		REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK;	\

+		REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_8BIT;	\

+	} while (0)

+

+#define __dmac_channel_set_transfer_unit_16byte(n)		\

+	do {							\

+		REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK;	\

+		REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_16BYTE;	\

+	} while (0)

+

+#define __dmac_channel_set_transfer_unit_32byte(n)		\

+	do {							\

+		REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK;	\

+		REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_32BYTE;	\

+	} while (0)

+

+/* w=8,16,32 */

+#define __dmac_channel_set_dest_port_width(n,w)			\

+	do {							\

+		REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DWDH_MASK;	\

+		REG_DMAC_DCMD((n)) |= DMAC_DCMD_DWDH_##w;	\

+	} while (0)

+

+/* w=8,16,32 */

+#define __dmac_channel_set_src_port_width(n,w)			\

+	do {							\

+		REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_SWDH_MASK;	\

+		REG_DMAC_DCMD((n)) |= DMAC_DCMD_SWDH_##w;	\

+	} while (0)

+

+/* v=0-15 */

+#define __dmac_channel_set_rdil(n,v)				\

+	do {							\

+	REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_RDIL_MASK;		\

+	REG_DMAC_DCMD((n) |= ((v) << DMAC_DCMD_RDIL_BIT);	\

+		      } while (0)

+

+#define __dmac_channel_dest_addr_fixed(n)		\

+	(  REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DAI )

+#define __dmac_channel_dest_addr_increment(n)		\

+	(  REG_DMAC_DCMD((n)) |= DMAC_DCMD_DAI )

+

+#define __dmac_channel_src_addr_fixed(n)		\

+	(  REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_SAI )

+#define __dmac_channel_src_addr_increment(n)		\

+	(  REG_DMAC_DCMD((n)) |= DMAC_DCMD_SAI )

+

+#define __dmac_channel_set_doorbell(n)					\

+	(  REG_DMAC_DMADBSR((n)/HALF_DMA_NUM) = (1 << ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM)) )

+

+#define __dmac_channel_irq_detected(n)  ( REG_DMAC_DMAIPR((n)/HALF_DMA_NUM) & (1 << ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM)) )

+#define __dmac_channel_ack_irq(n)       ( REG_DMAC_DMAIPR((n)/HALF_DMA_NUM) &= ~(1 <<((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM)) )

+

+static __inline__ int __dmac_get_irq(void)

+{

+	int i;

+	for (i = 0; i < MAX_DMA_NUM; i++)

+		if (__dmac_channel_irq_detected(i))

+			return i;

+	return -1;

+}

+

+

+

+#endif /* __MIPS_ASSEMBLER */

+

+#endif /* __JZ4760BDMAC_H__ */

+

diff --git a/arch/mips/include/asm/mach-jz4760b/jz4760bemc.h b/arch/mips/include/asm/mach-jz4760b/jz4760bemc.h
new file mode 100644
index 00000000000..bc4b9305c3c
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4760b/jz4760bemc.h
@@ -0,0 +1,213 @@
+/*

+ * linux/include/asm-mips/mach-jz4760b/jz4760bemc.h

+ *

+ * JZ4760B EMC register definition.

+ *

+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

+ */

+

+#ifndef __JZ4760BEMC_H__

+#define __JZ4760BEMC_H__

+

+

+#define	EMC_BASE	0xB3010000

+

+

+/*************************************************************************

+ * EMC (External Memory Controller)

+ *************************************************************************/

+#define EMC_BCR    	(EMC_BASE + 0x00)  /* Bus Control Register */

+#define EMC_PMEMBS1     (EMC_BASE + 0x6004) 

+#define EMC_PMEMBS0     (EMC_BASE + 0x6008) 

+#define EMC_SMCR0	(EMC_BASE + 0x10)  /* Static Memory Control Register 0 ??? */

+#define EMC_SMCR1	(EMC_BASE + 0x14)  /* Static Memory Control Register 1 */

+#define EMC_SMCR2	(EMC_BASE + 0x18)  /* Static Memory Control Register 2 */

+#define EMC_SMCR3	(EMC_BASE + 0x1c)  /* Static Memory Control Register 3 */

+#define EMC_SMCR4	(EMC_BASE + 0x20)  /* Static Memory Control Register 4 */

+#define EMC_SMCR5	(EMC_BASE + 0x24)  /* Static Memory Control Register 5 */

+#define EMC_SMCR6	(EMC_BASE + 0x28)  /* Static Memory Control Register 6 */

+#define EMC_SACR0	(EMC_BASE + 0x30)  /* Static Memory Bank 0 Addr Config Reg */

+#define EMC_SACR1	(EMC_BASE + 0x34)  /* Static Memory Bank 1 Addr Config Reg */

+#define EMC_SACR2	(EMC_BASE + 0x38)  /* Static Memory Bank 2 Addr Config Reg */

+#define EMC_SACR3	(EMC_BASE + 0x3c)  /* Static Memory Bank 3 Addr Config Reg */

+#define EMC_SACR4	(EMC_BASE + 0x40)  /* Static Memory Bank 4 Addr Config Reg */

+

+#define EMC_NFCSR	(EMC_BASE + 0x050) /* NAND Flash Control/Status Register */

+

+#define EMC_DMCR	(EMC_BASE + 0x80)  /* DRAM Control Register */

+#define EMC_RTCSR	(EMC_BASE + 0x84)  /* Refresh Time Control/Status Register */

+#define EMC_RTCNT	(EMC_BASE + 0x88)  /* Refresh Timer Counter */

+#define EMC_RTCOR	(EMC_BASE + 0x8c)  /* Refresh Time Constant Register */

+#define EMC_DMAR0	(EMC_BASE + 0x90)  /* SDRAM Bank 0 Addr Config Register */

+#define EMC_DMAR1	(EMC_BASE + 0x94)  /* SDRAM Bank 1 Addr Config Register */

+#define EMC_SDMR0	(EMC_BASE + 0xa000) /* Mode Register of SDRAM bank 0 */

+

+#define REG_EMC_BCR 	REG32(EMC_BCR)

+#define REG_EMC_PMEMBS1 REG32(EMC_PMEMBS1)

+#define REG_EMC_PMEMBS0	REG32(EMC_PMEMBS0)

+#define REG_EMC_SMCR0	REG32(EMC_SMCR0) // ???

+#define REG_EMC_SMCR1	REG32(EMC_SMCR1)

+#define REG_EMC_SMCR2	REG32(EMC_SMCR2)

+#define REG_EMC_SMCR3	REG32(EMC_SMCR3)

+#define REG_EMC_SMCR4	REG32(EMC_SMCR4)

+#define REG_EMC_SMCR5	REG32(EMC_SMCR5)

+#define REG_EMC_SMCR6	REG32(EMC_SMCR6)

+#define REG_EMC_SACR0	REG32(EMC_SACR0)

+#define REG_EMC_SACR1	REG32(EMC_SACR1)

+#define REG_EMC_SACR2	REG32(EMC_SACR2)

+#define REG_EMC_SACR3	REG32(EMC_SACR3)

+#define REG_EMC_SACR4	REG32(EMC_SACR4)

+

+#define REG_EMC_NFCSR	REG32(EMC_NFCSR)

+

+#define REG_EMC_DMCR	REG32(EMC_DMCR)

+#define REG_EMC_RTCSR	REG16(EMC_RTCSR)

+#define REG_EMC_RTCNT	REG16(EMC_RTCNT)

+#define REG_EMC_RTCOR	REG16(EMC_RTCOR)

+#define REG_EMC_DMAR0	REG32(EMC_DMAR0)

+#define REG_EMC_DMAR1	REG32(EMC_DMAR1)

+

+/* Bus Control Register */

+#define EMC_BCR_BT_SEL_BIT      30

+#define EMC_BCR_BT_SEL_MASK     (0x3 << EMC_BCR_BT_SEL_BIT)

+#define EMC_BCR_PK_SEL          (1 << 24)

+#define EMC_BCR_BSR_MASK          (1 << 2)  /* Nand and SDRAM Bus Share Select: 0, share; 1, unshare */

+  #define EMC_BCR_BSR_SHARE       (0 << 2)

+  #define EMC_BCR_BSR_UNSHARE     (1 << 2)

+#define EMC_BCR_BRE             (1 << 1)

+#define EMC_BCR_ENDIAN          (1 << 0)

+

+/* Static Memory Control Register */

+#define EMC_SMCR_STRV_BIT	24

+#define EMC_SMCR_STRV_MASK	(0x0f << EMC_SMCR_STRV_BIT)

+#define EMC_SMCR_TAW_BIT	20

+#define EMC_SMCR_TAW_MASK	(0x0f << EMC_SMCR_TAW_BIT)

+#define EMC_SMCR_TBP_BIT	16

+#define EMC_SMCR_TBP_MASK	(0x0f << EMC_SMCR_TBP_BIT)

+#define EMC_SMCR_TAH_BIT	12

+#define EMC_SMCR_TAH_MASK	(0x07 << EMC_SMCR_TAH_BIT)

+#define EMC_SMCR_TAS_BIT	8

+#define EMC_SMCR_TAS_MASK	(0x07 << EMC_SMCR_TAS_BIT)

+#define EMC_SMCR_BW_BIT		6

+#define EMC_SMCR_BW_MASK	(0x03 << EMC_SMCR_BW_BIT)

+  #define EMC_SMCR_BW_8BIT	(0 << EMC_SMCR_BW_BIT)

+  #define EMC_SMCR_BW_16BIT	(1 << EMC_SMCR_BW_BIT)

+  #define EMC_SMCR_BW_32BIT	(2 << EMC_SMCR_BW_BIT)

+#define EMC_SMCR_BCM		(1 << 3)

+#define EMC_SMCR_BL_BIT		1

+#define EMC_SMCR_BL_MASK	(0x03 << EMC_SMCR_BL_BIT)

+  #define EMC_SMCR_BL_4		(0 << EMC_SMCR_BL_BIT)

+  #define EMC_SMCR_BL_8		(1 << EMC_SMCR_BL_BIT)

+  #define EMC_SMCR_BL_16	(2 << EMC_SMCR_BL_BIT)

+  #define EMC_SMCR_BL_32	(3 << EMC_SMCR_BL_BIT)

+#define EMC_SMCR_SMT		(1 << 0)

+

+/* Static Memory Bank Addr Config Reg */

+#define EMC_SACR_BASE_BIT	8

+#define EMC_SACR_BASE_MASK	(0xff << EMC_SACR_BASE_BIT)

+#define EMC_SACR_MASK_BIT	0

+#define EMC_SACR_MASK_MASK	(0xff << EMC_SACR_MASK_BIT)

+

+/* NAND Flash Control/Status Register */

+#define EMC_NFCSR_NFCE4		(1 << 7) /* NAND Flash Enable */

+#define EMC_NFCSR_NFE4		(1 << 6) /* NAND Flash FCE# Assertion Enable */

+#define EMC_NFCSR_NFCE3		(1 << 5)

+#define EMC_NFCSR_NFE3		(1 << 4)

+#define EMC_NFCSR_NFCE2		(1 << 3)

+#define EMC_NFCSR_NFE2		(1 << 2)

+#define EMC_NFCSR_NFCE1		(1 << 1)

+#define EMC_NFCSR_NFE1		(1 << 0)

+

+/* DRAM Control Register */

+#define EMC_DMCR_BW_BIT		31

+#define EMC_DMCR_BW		(1 << EMC_DMCR_BW_BIT)

+#define EMC_DMCR_CA_BIT		26

+#define EMC_DMCR_CA_MASK	(0x07 << EMC_DMCR_CA_BIT)

+  #define EMC_DMCR_CA_8		(0 << EMC_DMCR_CA_BIT)

+  #define EMC_DMCR_CA_9		(1 << EMC_DMCR_CA_BIT)

+  #define EMC_DMCR_CA_10	(2 << EMC_DMCR_CA_BIT)

+  #define EMC_DMCR_CA_11	(3 << EMC_DMCR_CA_BIT)

+  #define EMC_DMCR_CA_12	(4 << EMC_DMCR_CA_BIT)

+#define EMC_DMCR_RMODE		(1 << 25)

+#define EMC_DMCR_RFSH		(1 << 24)

+#define EMC_DMCR_MRSET		(1 << 23)

+#define EMC_DMCR_RA_BIT		20

+#define EMC_DMCR_RA_MASK	(0x03 << EMC_DMCR_RA_BIT)

+  #define EMC_DMCR_RA_11	(0 << EMC_DMCR_RA_BIT)

+  #define EMC_DMCR_RA_12	(1 << EMC_DMCR_RA_BIT)

+  #define EMC_DMCR_RA_13	(2 << EMC_DMCR_RA_BIT)

+#define EMC_DMCR_BA_BIT		19

+#define EMC_DMCR_BA		(1 << EMC_DMCR_BA_BIT)

+#define EMC_DMCR_PDM		(1 << 18)

+#define EMC_DMCR_EPIN		(1 << 17)

+#define EMC_DMCR_MBSEL		(1 << 16)

+#define EMC_DMCR_TRAS_BIT	13

+#define EMC_DMCR_TRAS_MASK	(0x07 << EMC_DMCR_TRAS_BIT)

+#define EMC_DMCR_RCD_BIT	11

+#define EMC_DMCR_RCD_MASK	(0x03 << EMC_DMCR_RCD_BIT)

+#define EMC_DMCR_TPC_BIT	8

+#define EMC_DMCR_TPC_MASK	(0x07 << EMC_DMCR_TPC_BIT)

+#define EMC_DMCR_TRWL_BIT	5

+#define EMC_DMCR_TRWL_MASK	(0x03 << EMC_DMCR_TRWL_BIT)

+#define EMC_DMCR_TRC_BIT	2

+#define EMC_DMCR_TRC_MASK	(0x07 << EMC_DMCR_TRC_BIT)

+#define EMC_DMCR_TCL_BIT	0

+#define EMC_DMCR_TCL_MASK	(0x03 << EMC_DMCR_TCL_BIT)

+

+/* Refresh Time Control/Status Register */

+#define EMC_RTCSR_SFR		(1 << 8)    /* self refresh flag */

+#define EMC_RTCSR_CMF		(1 << 7)

+#define EMC_RTCSR_CKS_BIT	0

+#define EMC_RTCSR_CKS_MASK	(0x07 << EMC_RTCSR_CKS_BIT)

+  #define EMC_RTCSR_CKS_DISABLE	(0 << EMC_RTCSR_CKS_BIT)

+  #define EMC_RTCSR_CKS_4	(1 << EMC_RTCSR_CKS_BIT)

+  #define EMC_RTCSR_CKS_16	(2 << EMC_RTCSR_CKS_BIT)

+  #define EMC_RTCSR_CKS_64	(3 << EMC_RTCSR_CKS_BIT)

+  #define EMC_RTCSR_CKS_256	(4 << EMC_RTCSR_CKS_BIT)

+  #define EMC_RTCSR_CKS_1024	(5 << EMC_RTCSR_CKS_BIT)

+  #define EMC_RTCSR_CKS_2048	(6 << EMC_RTCSR_CKS_BIT)

+  #define EMC_RTCSR_CKS_4096	(7 << EMC_RTCSR_CKS_BIT)

+

+/* SDRAM Bank Address Configuration Register */

+#define EMC_DMAR_BASE_BIT	8

+#define EMC_DMAR_BASE_MASK	(0xff << EMC_DMAR_BASE_BIT)

+#define EMC_DMAR_MASK_BIT	0

+#define EMC_DMAR_MASK_MASK	(0xff << EMC_DMAR_MASK_BIT)

+

+/* Mode Register of SDRAM bank 0 */

+#define EMC_SDMR_BM		(1 << 9) /* Write Burst Mode */

+#define EMC_SDMR_OM_BIT		7        /* Operating Mode */

+#define EMC_SDMR_OM_MASK	(3 << EMC_SDMR_OM_BIT)

+  #define EMC_SDMR_OM_NORMAL	(0 << EMC_SDMR_OM_BIT)

+#define EMC_SDMR_CAS_BIT	4        /* CAS Latency */

+#define EMC_SDMR_CAS_MASK	(7 << EMC_SDMR_CAS_BIT)

+  #define EMC_SDMR_CAS_1	(1 << EMC_SDMR_CAS_BIT)

+  #define EMC_SDMR_CAS_2	(2 << EMC_SDMR_CAS_BIT)

+  #define EMC_SDMR_CAS_3	(3 << EMC_SDMR_CAS_BIT)

+#define EMC_SDMR_BT_BIT		3        /* Burst Type */

+#define EMC_SDMR_BT_MASK	(1 << EMC_SDMR_BT_BIT)

+  #define EMC_SDMR_BT_SEQ	(0 << EMC_SDMR_BT_BIT) /* Sequential */

+  #define EMC_SDMR_BT_INT	(1 << EMC_SDMR_BT_BIT) /* Interleave */

+#define EMC_SDMR_BL_BIT		0        /* Burst Length */

+#define EMC_SDMR_BL_MASK	(7 << EMC_SDMR_BL_BIT)

+  #define EMC_SDMR_BL_1		(0 << EMC_SDMR_BL_BIT)

+  #define EMC_SDMR_BL_2		(1 << EMC_SDMR_BL_BIT)

+  #define EMC_SDMR_BL_4		(2 << EMC_SDMR_BL_BIT)

+  #define EMC_SDMR_BL_8		(3 << EMC_SDMR_BL_BIT)

+

+#define EMC_SDMR_CAS2_16BIT \

+  (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2)

+#define EMC_SDMR_CAS2_32BIT \

+  (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4)

+#define EMC_SDMR_CAS3_16BIT \

+  (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2)

+#define EMC_SDMR_CAS3_32BIT \

+  (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4)

+

+

+#ifndef __MIPS_ASSEMBLER

+

+#endif /* __MIPS_ASSEMBLER */

+

+#endif /* __JZ4760BEMC_H__ */

+

diff --git a/arch/mips/include/asm/mach-jz4760b/jz4760bgpio.h b/arch/mips/include/asm/mach-jz4760b/jz4760bgpio.h
new file mode 100644
index 00000000000..e9e8ca8f556
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4760b/jz4760bgpio.h
@@ -0,0 +1,1052 @@
+/*

+ * jz4760bgpio.h

+ * JZ4760B GPIO register definition

+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

+ *

+ * Author: whxu@ingenic.cn

+ */

+

+#ifndef __JZ4760BGPIO_H__

+#define __JZ4760BGPIO_H__

+

+

+/*

+ * General purpose I/O port module(GPIO) address definition

+ */

+#define	GPIO_BASE	0xb0010000

+

+/* GPIO group offset */

+#define GPIO_GOS	0x100

+

+/* Each group address */

+#define GPIO_BASEA	(GPIO_BASE + (0) * GPIO_GOS)

+#define GPIO_BASEB	(GPIO_BASE + (1) * GPIO_GOS)

+#define GPIO_BASEC	(GPIO_BASE + (2) * GPIO_GOS)

+#define GPIO_BASED	(GPIO_BASE + (3) * GPIO_GOS)

+#define GPIO_BASEE	(GPIO_BASE + (4) * GPIO_GOS)

+#define GPIO_BASEF	(GPIO_BASE + (5) * GPIO_GOS)

+

+

+/*

+ * GPIO registers offset address definition

+ */

+#define GPIO_PXPIN_OFFSET	(0x00)	/*  r, 32, 0x00000000 */

+#define GPIO_PXDAT_OFFSET	(0x10)	/*  r, 32, 0x00000000 */

+#define GPIO_PXDATS_OFFSET	(0x14)  /*  w, 32, 0x???????? */

+#define GPIO_PXDATC_OFFSET	(0x18)  /*  w, 32, 0x???????? */

+#define GPIO_PXIM_OFFSET	(0x20)  /*  r, 32, 0xffffffff */

+#define GPIO_PXIMS_OFFSET	(0x24)  /*  w, 32, 0x???????? */

+#define GPIO_PXIMC_OFFSET	(0x28)  /*  w, 32, 0x???????? */

+#define GPIO_PXPE_OFFSET	(0x30)  /*  r, 32, 0x00000000 */

+#define GPIO_PXPES_OFFSET	(0x34)  /*  w, 32, 0x???????? */

+#define GPIO_PXPEC_OFFSET	(0x38)  /*  w, 32, 0x???????? */

+#define GPIO_PXFUN_OFFSET	(0x40)  /*  r, 32, 0x00000000 */

+#define GPIO_PXFUNS_OFFSET	(0x44)  /*  w, 32, 0x???????? */

+#define GPIO_PXFUNC_OFFSET	(0x48)  /*  w, 32, 0x???????? */

+#define GPIO_PXSEL_OFFSET	(0x50)  /*  r, 32, 0x00000000 */

+#define GPIO_PXSELS_OFFSET	(0x54)  /*  w, 32, 0x???????? */

+#define GPIO_PXSELC_OFFSET	(0x58)  /*  w, 32, 0x???????? */

+#define GPIO_PXDIR_OFFSET	(0x60)  /*  r, 32, 0x00000000 */

+#define GPIO_PXDIRS_OFFSET	(0x64)  /*  w, 32, 0x???????? */

+#define GPIO_PXDIRC_OFFSET	(0x68)  /*  w, 32, 0x???????? */

+#define GPIO_PXTRG_OFFSET	(0x70)  /*  r, 32, 0x00000000 */

+#define GPIO_PXTRGS_OFFSET	(0x74)  /*  w, 32, 0x???????? */

+#define GPIO_PXTRGC_OFFSET	(0x78)  /*  w, 32, 0x???????? */

+#define GPIO_PXFLG_OFFSET	(0x80)  /*  r, 32, 0x00000000 */

+#define GPIO_PXFLGC_OFFSET	(GPIO_PXDATS_OFFSET)  /*  w, 32, 0x???????? */

+

+#define GPIO_PXDS0_OFFSET	(0xc0)

+#define GPIO_PXDS1_OFFSET	(0xd0)

+#define GPIO_PXDS2_OFFSET	(0xe0)

+#define GPIO_PXDS0S_OFFSET	(0xc4)

+#define GPIO_PXDS1S_OFFSET	(0xd4)

+#define GPIO_PXDS2S_OFFSET	(0xe4)

+#define GPIO_PXDS0C_OFFSET	(0xc8)

+#define GPIO_PXDS1C_OFFSET	(0xd8)

+#define GPIO_PXDS2C_OFFSET	(0xe8)

+#define GPIO_PXSL_OFFSET	(0xf0)

+#define GPIO_PXSLS_OFFSET	(0xf4)

+#define GPIO_PXSLC_OFFSET	(0xf8)

+

+

+/*

+ * GPIO registers address definition

+ */

+#define GPIO_PXPIN(n)	(GPIO_BASE + (n)*GPIO_GOS + GPIO_PXPIN_OFFSET)

+#define GPIO_PXDAT(n)	(GPIO_BASE + (n)*GPIO_GOS + GPIO_PXDAT_OFFSET)

+#define GPIO_PXDATS(n)	(GPIO_BASE + (n)*GPIO_GOS + GPIO_PXDATS_OFFSET)

+#define GPIO_PXDATC(n)	(GPIO_BASE + (n)*GPIO_GOS + GPIO_PXDATC_OFFSET)

+#define GPIO_PXIM(n)	(GPIO_BASE + (n)*GPIO_GOS + GPIO_PXIM_OFFSET)

+#define GPIO_PXIMS(n)	(GPIO_BASE + (n)*GPIO_GOS + GPIO_PXIMS_OFFSET)

+#define GPIO_PXIMC(n)	(GPIO_BASE + (n)*GPIO_GOS + GPIO_PXIMC_OFFSET)

+#define GPIO_PXPE(n)	(GPIO_BASE + (n)*GPIO_GOS + GPIO_PXPE_OFFSET)

+#define GPIO_PXPES(n)	(GPIO_BASE + (n)*GPIO_GOS + GPIO_PXPES_OFFSET)

+#define GPIO_PXPEC(n)	(GPIO_BASE + (n)*GPIO_GOS + GPIO_PXPEC_OFFSET)

+#define GPIO_PXFUN(n)	(GPIO_BASE + (n)*GPIO_GOS + GPIO_PXFUN_OFFSET)

+#define GPIO_PXFUNS(n)	(GPIO_BASE + (n)*GPIO_GOS + GPIO_PXFUNS_OFFSET)

+#define GPIO_PXFUNC(n)	(GPIO_BASE + (n)*GPIO_GOS + GPIO_PXFUNC_OFFSET)

+#define GPIO_PXSEL(n)	(GPIO_BASE + (n)*GPIO_GOS + GPIO_PXSEL_OFFSET)

+#define GPIO_PXSELS(n)	(GPIO_BASE + (n)*GPIO_GOS + GPIO_PXSELS_OFFSET)

+#define GPIO_PXSELC(n)	(GPIO_BASE + (n)*GPIO_GOS + GPIO_PXSELC_OFFSET)

+#define GPIO_PXDIR(n)	(GPIO_BASE + (n)*GPIO_GOS + GPIO_PXDIR_OFFSET)

+#define GPIO_PXDIRS(n)	(GPIO_BASE + (n)*GPIO_GOS + GPIO_PXDIRS_OFFSET)

+#define GPIO_PXDIRC(n)	(GPIO_BASE + (n)*GPIO_GOS + GPIO_PXDIRC_OFFSET)

+#define GPIO_PXTRG(n)	(GPIO_BASE + (n)*GPIO_GOS + GPIO_PXTRG_OFFSET)

+#define GPIO_PXTRGS(n)	(GPIO_BASE + (n)*GPIO_GOS + GPIO_PXTRGS_OFFSET)

+#define GPIO_PXTRGC(n)	(GPIO_BASE + (n)*GPIO_GOS + GPIO_PXTRGC_OFFSET)

+#define GPIO_PXFLG(n)	(GPIO_BASE + (n)*GPIO_GOS + GPIO_PXFLG_OFFSET)

+#define GPIO_PXFLGC(n)	(GPIO_BASE + (n)*GPIO_GOS + GPIO_PXFLGC_OFFSET)

+/* n (1~5) */

+#define GPIO_PXDS0(n)	(GPIO_BASE + (n)*GPIO_GOS + GPIO_PXDS0_OFFSET)

+#define GPIO_PXDS0S(n)	(GPIO_BASE + (n)*GPIO_GOS + GPIO_PXDS0S_OFFSET)

+#define GPIO_PXDS0C(n)	(GPIO_BASE + (n)*GPIO_GOS + GPIO_PXDS0C_OFFSET)

+#define GPIO_PXDS1(n)	(GPIO_BASE + (n)*GPIO_GOS + GPIO_PXDS1_OFFSET)

+#define GPIO_PXDS1S(n)	(GPIO_BASE + (n)*GPIO_GOS + GPIO_PXDS1S_OFFSET)

+#define GPIO_PXDS1C(n)	(GPIO_BASE + (n)*GPIO_GOS + GPIO_PXDS1C_OFFSET)

+#define GPIO_PXDS2(n)	(GPIO_BASE + (n)*GPIO_GOS + GPIO_PXDS2_OFFSET)

+#define GPIO_PXDS2S(n)	(GPIO_BASE + (n)*GPIO_GOS + GPIO_PXDS2S_OFFSET)

+#define GPIO_PXDS2C(n)	(GPIO_BASE + (n)*GPIO_GOS + GPIO_PXDS2C_OFFSET)

+#define GPIO_PXSL(n)	(GPIO_BASE + (n)*GPIO_GOS + GPIO_PXSL_OFFSET)

+#define GPIO_PXSLS(n)	(GPIO_BASE + (n)*GPIO_GOS + GPIO_PXSLS_OFFSET)

+#define GPIO_PXSLC(n)	(GPIO_BASE + (n)*GPIO_GOS + GPIO_PXSLC_OFFSET)

+

+

+

+/*  */

+#define GPIO_PORT_NUM   6

+#define MAX_GPIO_NUM	192

+#define GPIO_WAKEUP     (30)

+

+

+#ifndef __MIPS_ASSEMBLER

+

+//n = 0,1,2,3,4,5 (PORTA, PORTB, PORTC, PORTD, PORTE, PORTF)

+#define REG_GPIO_PXPIN(n)	REG32(GPIO_PXPIN(n))

+#define REG_GPIO_PXDAT(n)	REG32(GPIO_PXDAT(n))

+#define REG_GPIO_PXDATS(n)	REG32(GPIO_PXDATS(n))

+#define REG_GPIO_PXDATC(n)	REG32(GPIO_PXDATC(n))

+#define REG_GPIO_PXIM(n)	REG32(GPIO_PXIM(n))

+#define REG_GPIO_PXIMS(n)	REG32(GPIO_PXIMS(n))

+#define REG_GPIO_PXIMC(n)	REG32(GPIO_PXIMC(n))

+#define REG_GPIO_PXPE(n)	REG32(GPIO_PXPE(n))

+#define REG_GPIO_PXPES(n)	REG32(GPIO_PXPES(n))

+#define REG_GPIO_PXPEC(n)	REG32(GPIO_PXPEC(n))

+#define REG_GPIO_PXFUN(n)	REG32(GPIO_PXFUN(n))

+#define REG_GPIO_PXFUNS(n)	REG32(GPIO_PXFUNS(n))

+#define REG_GPIO_PXFUNC(n)	REG32(GPIO_PXFUNC(n))

+#define REG_GPIO_PXSEL(n)	REG32(GPIO_PXSEL(n))

+#define REG_GPIO_PXSELS(n)	REG32(GPIO_PXSELS(n))

+#define REG_GPIO_PXSELC(n)	REG32(GPIO_PXSELC(n))

+#define REG_GPIO_PXDIR(n)	REG32(GPIO_PXDIR(n))

+#define REG_GPIO_PXDIRS(n)	REG32(GPIO_PXDIRS(n))

+#define REG_GPIO_PXDIRC(n)	REG32(GPIO_PXDIRC(n))

+#define REG_GPIO_PXTRG(n)	REG32(GPIO_PXTRG(n))

+#define REG_GPIO_PXTRGS(n)	REG32(GPIO_PXTRGS(n))

+#define REG_GPIO_PXTRGC(n)	REG32(GPIO_PXTRGC(n))

+#define REG_GPIO_PXFLG(n)	REG32(GPIO_PXFLG(n))

+#define REG_GPIO_PXFLGC(n)	REG32(GPIO_PXFLGC(n))

+

+/* n (1~5) */

+#define REG_GPIO_PXDS0(n)	REG32(GPIO_PXDS0(n))

+#define REG_GPIO_PXDS0S(n)	REG32(GPIO_PXDS0S(n))

+#define REG_GPIO_PXDS0C(n)	REG32(GPIO_PXDS0C(n))

+#define REG_GPIO_PXDS1(n)	REG32(GPIO_PXDS1(n))

+#define REG_GPIO_PXDS1S(n)	REG32(GPIO_PXDS1S(n))

+#define REG_GPIO_PXDS1C(n)	REG32(GPIO_PXDS1C(n))

+#define REG_GPIO_PXDS2(n)	REG32(GPIO_PXDS2(n))

+#define REG_GPIO_PXDS2S(n)	REG32(GPIO_PXDS2S(n))

+#define REG_GPIO_PXDS2C(n)	REG32(GPIO_PXDS2C(n))

+#define REG_GPIO_PXSL(n)	REG32(GPIO_PXSL(n))

+#define REG_GPIO_PXSLS(n)	REG32(GPIO_PXSLS(n))

+#define REG_GPIO_PXSLC(n)	REG32(GPIO_PXSLC(n))

+

+/*----------------------------------------------------------------

+ * p is the port number (0,1,2,3,4,5)

+ * o is the pin offset (0-31) inside the port

+ * n is the absolute number of a pin (0-127), regardless of the port

+ */

+

+//----------------------------------------------------------------

+// Function Pins Mode

+

+#define __gpio_as_func0(n)			\

+do {						\

+	unsigned int p, o;			\

+	p = (n) / 32;				\

+	o = (n) % 32;				\

+	REG_GPIO_PXFUNS(p) = (1 << o);		\

+	REG_GPIO_PXTRGC(p) = (1 << o);		\

+	REG_GPIO_PXSELC(p) = (1 << o);		\

+} while (0)

+

+#define __gpio_as_func1(n)			\

+do {						\

+	unsigned int p, o;			\

+	p = (n) / 32;				\

+	o = (n) % 32;				\

+	REG_GPIO_PXFUNS(p) = (1 << o);		\

+	REG_GPIO_PXTRGC(p) = (1 << o);		\

+	REG_GPIO_PXSELS(p) = (1 << o);		\

+} while (0)

+

+#define __gpio_as_func2(n)			\

+do {						\

+	unsigned int p, o;			\

+	p = (n) / 32;				\

+	o = (n) % 32;				\

+	REG_GPIO_PXFUNS(p) = (1 << o);		\

+	REG_GPIO_PXTRGS(p) = (1 << o);		\

+	REG_GPIO_PXSELC(p) = (1 << o);		\

+} while (0)

+

+#define __gpio_as_func3(n)			\

+do {						\

+	unsigned int p, o;			\

+	p = (n) / 32;				\

+	o = (n) % 32;				\

+	REG_GPIO_PXFUNS(p) = (1 << o);		\

+	REG_GPIO_PXTRGS(p) = (1 << o);		\

+	REG_GPIO_PXSELS(p) = (1 << o);		\

+} while (0)

+

+/*

+ * UART0_TxD, UART0_RxD

+ */

+#define __gpio_as_uart0()			\

+do {						\

+	unsigned int bits = BIT3 | BIT0;	\

+	REG_GPIO_PXFUNS(5) = bits;		\

+	REG_GPIO_PXTRGC(5) = bits;		\

+	REG_GPIO_PXSELC(5) = bits;		\

+	REG_GPIO_PXPES(5)  = bits;		\

+} while (0)

+

+/*

+ * UART0_TxD, UART0_RxD, UART0_CTS, UART0_RTS

+ */

+#define __gpio_as_uart0_ctsrts()		\

+do {						\

+	unsigned int bits = BITS_H2L(3, 0);	\

+	REG_GPIO_PXFUNS(5) = bits;		\

+	REG_GPIO_PXTRGC(5) = bits;		\

+	REG_GPIO_PXSELC(5) = bits;		\

+	REG_GPIO_PXPES(5)  = bits;		\

+} while (0)

+

+/*

+ * UART1_TxD, UART1_RxD

+ */

+#define __gpio_as_uart1()			\

+do {						\

+	unsigned int bits = BIT28 | BIT26;	\

+	REG_GPIO_PXFUNS(3) = bits;		\

+	REG_GPIO_PXTRGC(3) = bits;		\

+	REG_GPIO_PXSELC(3) = bits;		\

+	REG_GPIO_PXPES(3)  = bits;		\

+} while (0)

+

+/*

+ * UART1_TxD, UART1_RxD, UART1_CTS, UART1_RTS

+ */

+#define __gpio_as_uart1_ctsrts()		\

+do {						\

+	unsigned int bits = BITS_H2L(29, 26);	\

+	REG_GPIO_PXFUNS(3) = bits;		\

+	REG_GPIO_PXTRGC(3) = bits;		\

+	REG_GPIO_PXSELC(3) = bits;		\

+	REG_GPIO_PXPES(3)  = bits;		\

+} while (0)

+

+

+/*

+ * UART2_TxD, UART2_RxD

+ */

+#define __gpio_as_uart2()			\

+do {						\

+	unsigned int bits = BIT30 | BIT28;	\

+	REG_GPIO_PXFUNS(2) = bits;		\

+	REG_GPIO_PXTRGC(2) = bits;		\

+	REG_GPIO_PXSELC(2) = bits;		\

+	REG_GPIO_PXPES(2)  = bits;		\

+} while (0)

+

+/*

+ * UART2_TxD, UART2_RxD, UART2_CTS, UART2_RTS

+ */

+#define __gpio_as_uart2_ctsrts()		\

+do {						\

+	unsigned int bits = BITS_H2L(31, 28);	\

+	REG_GPIO_PXFUNS(2) = bits;		\

+	REG_GPIO_PXTRGC(2) = bits;		\

+	REG_GPIO_PXSELC(2) = bits;		\

+	REG_GPIO_PXPES(2)  = bits;		\

+} while (0)

+

+/* WARNING: the folloing macro do NOT check */

+/*

+ * UART3_TxD, UART3_RxD

+ */

+#define __gpio_as_uart3()           \

+do {                        \

+    unsigned int rx_bit = BIT12,tx_bit= BIT5;   \

+    REG_GPIO_PXFUNS(3) = rx_bit;        \

+    REG_GPIO_PXTRGC(3) = rx_bit;        \

+    REG_GPIO_PXSELC(3) = rx_bit;        \

+    REG_GPIO_PXPES(3)  = rx_bit;        \

+    \

+    REG_GPIO_PXFUNS(4) = tx_bit;        \

+    REG_GPIO_PXTRGC(4) = tx_bit;        \

+    REG_GPIO_PXSELS(4) = tx_bit;        \

+    REG_GPIO_PXPES(4)  = tx_bit;        \

+} while (0)

+

+/*

+ * UART3_TxD, UART3_RxD, UART3_CTS, UART3_RTS

+ */

+#define __gpio_as_uart3_ctsrts()            \

+do {                        \

+    unsigned int rx_bit = BIT12,tx_bit= BIT5,   \

+                bits = BITS_H2L(9, 8); \

+    REG_GPIO_PXFUNS(3) = rx_bit;        \

+    REG_GPIO_PXTRGC(3) = rx_bit;        \

+    REG_GPIO_PXSELC(3) = rx_bit;        \

+    REG_GPIO_PXPES(3)  = rx_bit;        \

+    \

+    REG_GPIO_PXFUNS(4) = tx_bit;        \

+    REG_GPIO_PXTRGC(4) = tx_bit;        \

+    REG_GPIO_PXSELS(4) = tx_bit;        \

+    REG_GPIO_PXPES(4)  = tx_bit;        \

+    REG_GPIO_PXFUNS(4) = bits;      \

+    REG_GPIO_PXTRGC(4) = bits;      \

+    REG_GPIO_PXSELC(4) = bits;      \

+    REG_GPIO_PXPES(4)  = bits;      \

+} while (0)

+

+/*

+ * SD0 ~ SD7, CS1#, CLE, ALE, FRE#, FWE#, FRB#

+ * @n: chip select number(1 ~ 6)

+ */

+#define __gpio_as_nand_8bit(n)						\

+do {		              						\

+									\

+	REG_GPIO_PXFUNS(0) = 0x000c00ff; /* SD0 ~ SD7, CS1#, FRE#, FWE# */ \

+	REG_GPIO_PXSELC(0) = 0x000c00ff;				\

+	REG_GPIO_PXTRGC(0) = 0x000c00ff;				\

+	REG_GPIO_PXPES(0) = 0x000c00ff;					\

+	REG_GPIO_PXFUNS(1) = 0x00000003; /* CLE(SA2), ALE(SA3) */	\

+	REG_GPIO_PXSELC(1) = 0x00000003;				\

+	REG_GPIO_PXTRGC(1) = 0x00000003;				\

+	REG_GPIO_PXPES(1) = 0x00000003;					\

+									\

+	REG_GPIO_PXFUNS(0) = 0x00200000 << ((n)-1); /* CSn */		\

+	REG_GPIO_PXSELC(0) = 0x00200000 << ((n)-1);			\

+	REG_GPIO_PXPES(0) = 0x00200000 << ((n)-1);			\

+									\

+ 	REG_GPIO_PXFUNC(0) = 0x00100000; /* FRB#(input) */		\

+	REG_GPIO_PXSELC(0) = 0x00100000;				\

+	REG_GPIO_PXDIRC(0) = 0x00100000;				\

+	REG_GPIO_PXPES(0) = 0x00100000;					\

+} while (0)

+

+#define __gpio_as_nand_16bit(n)						\

+do {		              						\

+									\

+	REG_GPIO_PXFUNS(0) = 0x000cffff; /* SD0 ~ SD15, CS1#, FRE#, FWE# */ \

+	REG_GPIO_PXSELC(0) = 0x000cffff;				\

+	REG_GPIO_PXTRGC(0) = 0x000cffff;				\

+	REG_GPIO_PXPES(0) = 0x000cffff;					\

+	REG_GPIO_PXFUNS(1) = 0x00000003; /* CLE(SA2), ALE(SA3) */	\

+	REG_GPIO_PXSELC(1) = 0x00000003;				\

+	REG_GPIO_PXTRGC(1) = 0x00000003;				\

+	REG_GPIO_PXPES(1) = 0x00000003;					\

+									\

+	REG_GPIO_PXFUNS(0) = 0x00200000 << ((n)-1); /* CSn */		\

+	REG_GPIO_PXSELC(0) = 0x00200000 << ((n)-1);			\

+	REG_GPIO_PXPES(0) = 0x00200000 << ((n)-1);			\

+									\

+ 	REG_GPIO_PXFUNC(0) = 0x00100000; /* FRB#(input) */		\

+	REG_GPIO_PXSELC(0) = 0x00100000;				\

+	REG_GPIO_PXDIRC(0) = 0x00100000;				\

+	REG_GPIO_PXPES(0) = 0x00100000;					\

+} while (0)

+

+/*

+ * LCD_R3~LCD_R7, LCD_G2~LCD_G7, LCD_B3~LCD_B7,

+ * LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE

+ */

+#define __gpio_as_lcd_16bit()			\

+do {						\

+	REG_GPIO_PXFUNS(2) = 0x0f8ff3f8;	\

+	REG_GPIO_PXTRGC(2) = 0x0f8ff3f8;	\

+	REG_GPIO_PXSELC(2) = 0x0f8ff3f8;	\

+	REG_GPIO_PXPES(2) = 0x0f8ff3f8;		\

+} while (0)

+

+/*

+ * LCD_R2~LCD_R7, LCD_G2~LCD_G7, LCD_B2~LCD_B7,

+ * LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE

+ */

+#define __gpio_as_lcd_18bit()			\

+do {						\

+	REG_GPIO_PXFUNS(2) = 0x0fcff3fc;	\

+	REG_GPIO_PXTRGC(2) = 0x0fcff3fc;	\

+	REG_GPIO_PXSELC(2) = 0x0fcff3fc;	\

+	REG_GPIO_PXPES(2) = 0x0fcff3fc;		\

+} while (0)

+

+/*

+ * LCD_R0~LCD_R7, LCD_G0~LCD_G7, LCD_B0~LCD_B7,

+ * LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE

+ */

+#define __gpio_as_lcd_24bit()			\

+do {						\

+	REG_GPIO_PXFUNS(2) = 0x0fffffff;	\

+	REG_GPIO_PXTRGC(2) = 0x0fffffff;	\

+	REG_GPIO_PXSELC(2) = 0x0fffffff;	\

+	REG_GPIO_PXPES(2) = 0x0fffffff;		\

+} while (0)

+

+/*

+ *  LCD_CLS, LCD_SPL, LCD_PS, LCD_REV

+ */

+#define __gpio_as_lcd_special()			\

+do {						\

+	REG_GPIO_PXFUNS(2) = 0x0fffffff;	\

+	REG_GPIO_PXTRGC(2) = 0x0fffffff;	\

+	REG_GPIO_PXSELC(2) = 0x0feffbfc;	\

+	REG_GPIO_PXSELS(2) = 0x00100403;	\

+	REG_GPIO_PXPES(2) = 0x0fffffff;		\

+} while (0)

+

+

+#define __gpio_as_epd()				\

+do {						\

+	REG_GPIO_PXFUNS(1) = 0x00011e00;	\

+	REG_GPIO_PXTRGS(1) = 0x00011e00;	\

+	REG_GPIO_PXSELS(1) = 0x00011e00;	\

+	REG_GPIO_PXPES(1)  = 0x00011e00;	\

+} while (0)

+

+/*

+ * CIM_D0~CIM_D7, CIM_MCLK, CIM_PCLK, CIM_VSYNC, CIM_HSYNC

+ */

+#define __gpio_as_cim()				\

+do {						\

+	REG_GPIO_PXFUNS(1) = 0x0003ffc0;	\

+	REG_GPIO_PXTRGC(1) = 0x0003ffc0;	\

+	REG_GPIO_PXSELC(1) = 0x0003ffc0;	\

+	REG_GPIO_PXPES(1)  = 0x0003ffc0;	\

+} while (0)

+

+/*

+ * SDATO, SDATI, BCLK, SYNC, SCLK_RSTN(gpio sepc) or

+ * SDATA_OUT, SDATA_IN, BIT_CLK, SYNC, SCLK_RESET(aic spec)

+ */

+#define __gpio_as_aic()				\

+do {						\

+	REG_GPIO_PXFUNS(4) = 0x16c00000;	\

+	REG_GPIO_PXTRGC(4) = 0x02c00000;	\

+	REG_GPIO_PXTRGS(4) = 0x14000000;	\

+	REG_GPIO_PXSELC(4) = 0x14c00000;	\

+	REG_GPIO_PXSELS(4) = 0x02000000;	\

+	REG_GPIO_PXPES(4)  = 0x16c00000;	\

+} while (0)

+

+/*

+ * MSC0_CMD, MSC0_CLK, MSC0_D0 ~ MSC0_D7

+ */

+#define __gpio_as_msc0_boot()			\

+do {						\

+	REG_GPIO_PXFUNS(0) = 0x00ec0000;	\

+	REG_GPIO_PXTRGC(0) = 0x00ec0000;	\

+	REG_GPIO_PXSELS(0) = 0x00ec0000;	\

+	REG_GPIO_PXPES(0)  = 0x00ec0000;	\

+	REG_GPIO_PXFUNS(0) = 0x00100000;	\

+	REG_GPIO_PXTRGC(0) = 0x00100000;	\

+	REG_GPIO_PXSELC(0) = 0x00100000;	\

+	REG_GPIO_PXPES(0)  = 0x00100000;	\

+} while (0)

+

+#define __gpio_as_msc0_8bit()			\

+do {						\

+	REG_GPIO_PXFUNS(4) = 0x3ff00000;	\

+	REG_GPIO_PXTRGC(4) = 0x3ff00000;	\

+	REG_GPIO_PXSELC(4) = 0x3ff00000;	\

+	REG_GPIO_PXPES(4)  = 0x3ff00000;	\

+} while (0)

+

+/*

+ * MSC0_CMD, MSC0_CLK, MSC0_D0 ~ MSC0_D3

+ */

+#define __gpio_as_msc0_4bit()			\

+do {						\

+	REG_GPIO_PXFUNS(4) = 0x30f00000;	\

+	REG_GPIO_PXTRGC(4) = 0x30f00000;	\

+	REG_GPIO_PXSELC(4) = 0x30f00000;	\

+	REG_GPIO_PXPES(4)  = 0x30f00000;	\

+} while (0)

+

+/*

+ * MSC1_CMD, MSC1_CLK, MSC1_D0 ~ MSC1_D3

+ */

+#define __gpio_as_msc1_4bit()			\

+do {						\

+	REG_GPIO_PXFUNS(3) = 0x3f00000;	\

+	REG_GPIO_PXTRGC(3) = 0x3f00000;	\

+	REG_GPIO_PXSELC(3) = 0x3f00000;	\

+	REG_GPIO_PXPES(3)  = 0x3f00000;	\

+} while (0)

+

+/* Port B

+ * MSC2_CMD, MSC2_CLK, MSC2_D0 ~ MSC2_D3

+ */

+#define __gpio_as_msc2_4bit()			\

+do {						\

+	REG_GPIO_PXFUNS(1) = 0xf0300000;	\

+	REG_GPIO_PXTRGC(1) = 0xf0300000;	\

+	REG_GPIO_PXSELC(1) = 0xf0300000;	\

+	REG_GPIO_PXPES(1)  = 0xf0300000;	\

+} while (0)

+

+#define __gpio_as_msc 	__gpio_as_msc0_4bit /* default as msc0 4bit */

+#define __gpio_as_msc0 	__gpio_as_msc0_4bit /* msc0 default as 4bit */

+#define __gpio_as_msc1 	__gpio_as_msc1_4bit /* msc1 only support 4bit */

+

+/*

+ * TSCLK, TSSTR, TSFRM, TSFAIL, TSDI0~7

+ */

+#define __gpio_as_tssi_1()			\

+do {						\

+	REG_GPIO_PXFUNS(1) = 0x0003ffc0;	\

+	REG_GPIO_PXTRGC(1) = 0x0003ffc0;	\

+	REG_GPIO_PXSELS(1) = 0x0003ffc0;	\

+	REG_GPIO_PXPES(1)  = 0x0003ffc0;	\

+} while (0)

+

+/*

+ * TSCLK, TSSTR, TSFRM, TSFAIL, TSDI0~7

+ */

+#define __gpio_as_tssi_2()			\

+do {						\

+	REG_GPIO_PXFUNS(1) = 0xfff00000;	\

+	REG_GPIO_PXTRGC(1) = 0x0fc00000;	\

+	REG_GPIO_PXTRGS(1) = 0xf0300000;	\

+	REG_GPIO_PXSELC(1) = 0xfff00000;	\

+	REG_GPIO_PXPES(1)  = 0xfff00000;	\

+} while (0)

+

+/*

+ * SSI_CE0, SSI_CE1, SSI_GPC, SSI_CLK, SSI_DT, SSI_DR

+ */

+#define __gpio_as_ssi()				\

+do {						\

+	REG_GPIO_PXFUNS(0) = 0x002c0000; /* SSI0_CE0, SSI0_CLK, SSI0_DT	*/ \

+	REG_GPIO_PXTRGS(0) = 0x002c0000;	\

+	REG_GPIO_PXSELC(0) = 0x002c0000;	\

+	REG_GPIO_PXPES(0)  = 0x002c0000;	\

+						\

+	REG_GPIO_PXFUNS(0) = 0x00100000; /* SSI0_DR */	\

+	REG_GPIO_PXTRGC(0) = 0x00100000;	\

+	REG_GPIO_PXSELS(0) = 0x00100000;	\

+	REG_GPIO_PXPES(0)  = 0x00100000;	\

+} while (0)

+#define __gpio_as_ssi0()				\

+do {						\

+	REG_GPIO_PXFUNS(4) = 0x000fc000; /* SSI0: SSI0_CE0, SSI0_CE1, SSI0_CLK, SSI0_DT, SSI0_DR,SSI0_GPC*/\

+	REG_GPIO_PXTRGC(4) = 0x000fc000;	\

+	REG_GPIO_PXSELC(4) = 0x000fc000;	\

+	REG_GPIO_PXPES(4)  = 0x000fc000;	\

+} while (0)

+#define __gpio_as_ssi0_x()			\

+do {						\

+	REG_GPIO_PXFUNS(4) = 0x0002c000; /*  SSI0_CLK, SSI0_DT, SSI0_DR	*/ \

+	REG_GPIO_PXTRGC(4) = 0x0002c000;	\

+	REG_GPIO_PXSELC(4) = 0x0002c000;	\

+	REG_GPIO_PXPES(4)  = 0x0002c000;	\

+} while (0)

+

+#define __gpio_as_ssi0_1()				\

+do {						\

+	REG_GPIO_PXFUNS(1) = 0xf0300000; /* SSI0 */	\

+	REG_GPIO_PXTRGC(1) = 0xf0300000;	\

+	REG_GPIO_PXSELS(1) = 0xf0300000;	\

+	REG_GPIO_PXPES(1)  = 0xf0300000;	\

+} while (0)

+

+#define __gpio_as_ssi0_x1()				\

+do {						\

+	REG_GPIO_PXFUNS(1) = 0x10300000; /* SSI0_CLK, SSI0_DT,SSI0_DR	*/ \

+	REG_GPIO_PXTRGS(1) = 0x10300000;	\

+	REG_GPIO_PXSELC(1) = 0x10300000;	\

+	REG_GPIO_PXPES(1)  = 0x10300000;	\

+} while (0)

+#define __gpio_as_ssi0_2()				\

+do {						\

+	REG_GPIO_PXFUNS(0) = 0x00100000; /* SSI0 */	\

+	REG_GPIO_PXTRGC(0) = 0x00100000;	\

+	REG_GPIO_PXSELS(0) = 0x00100000;	\

+	REG_GPIO_PXPES(0)  = 0x00100000;	\

+										\

+	REG_GPIO_PXFUNS(0) = 0x002c0000; /* SSI0_CE0, SSI0_CLK, SSI0_DT	*/ \

+	REG_GPIO_PXTRGS(0) = 0x002c0000;	\

+	REG_GPIO_PXSELC(0) = 0x002c0000;	\

+	REG_GPIO_PXPES(0)  = 0x002c0000;	\

+} while (0)

+#define __gpio_as_ssi0_x2()			\

+do {						\

+	REG_GPIO_PXFUNS(0) = 0x00240000; /*  SSI0_CLK, SSI0_DT	*/ \

+	REG_GPIO_PXTRGS(0) = 0x00240000;	\

+	REG_GPIO_PXSELC(0) = 0x00240000;	\

+	REG_GPIO_PXPES(0)  = 0x00240000;	\

+						\

+	REG_GPIO_PXFUNS(0) = 0x00100000; /* SSI0_DR */	\

+	REG_GPIO_PXTRGC(0) = 0x00100000;	\

+	REG_GPIO_PXSELS(0) = 0x00100000;	\

+	REG_GPIO_PXPES(0)  = 0x00100000;	\

+} while (0)

+/***************** SSI 1 ***********************/

+#define __gpio_as_ssi1()				\

+do {						\

+	REG_GPIO_PXFUNS(4) = 0x000fc000; /* SSI1: SSI1_CE0, SSI1_CE1, SSI1_CLK, SSI1_DT, SSI1_DR,SSI1_GPC*/	\

+	REG_GPIO_PXTRGC(4) = 0x000fc000;	\

+	REG_GPIO_PXSELS(4) = 0x000fc000;	\

+	REG_GPIO_PXPES(4)  = 0x000fc000;	\

+} while (0)

+#define __gpio_as_ssi1_x()			\

+do {						\

+	REG_GPIO_PXFUNS(4) = 0x0002c000; /*  SSI1_CLK, SSI1_DT, SSI1_DR	*/ \

+	REG_GPIO_PXTRGC(4) = 0x0002c000;	\

+	REG_GPIO_PXSELS(4) = 0x0002c000;	\

+	REG_GPIO_PXPES(4)  = 0x0002c000;	\

+} while (0)

+

+#define __gpio_as_ssi1_1()				\

+do {						\

+	REG_GPIO_PXFUNS(1) = 0xf0300000; /* SSI1*/\

+	REG_GPIO_PXTRGC(1) = 0xf0300000;	\

+	REG_GPIO_PXSELS(1) = 0xf0300000;	\

+	REG_GPIO_PXPES(1)  = 0xf0300000;	\

+} while (0)

+#define __gpio_as_ssi1_x1()				\

+do {						\

+	REG_GPIO_PXFUNS(1) = 0x10300000; /* SSI1_x*/\

+	REG_GPIO_PXTRGC(1) = 0x10300000;	\

+	REG_GPIO_PXSELS(1) = 0x10300000;	\

+	REG_GPIO_PXPES(1)  = 0x10300000;	\

+} while (0)

+

+#define __gpio_as_ssi1_2()				\

+do {						\

+	REG_GPIO_PXFUNS(1) = 0x000003c0; /* SSI1*/\

+	REG_GPIO_PXTRGC(1) = 0x000003c0;	\

+	REG_GPIO_PXSELS(1) = 0x000003c0;	\

+	REG_GPIO_PXPES(1)  = 0x000003c0;	\

+} while (0)

+#define __gpio_as_ssi1_x2()				\

+do {						\

+	REG_GPIO_PXFUNS(1) = 0x000002c0; /* SSI1_x*/\

+	REG_GPIO_PXTRGC(1) = 0x000002c0;	\

+	REG_GPIO_PXSELS(1) = 0x000002c0;	\

+	REG_GPIO_PXPES(1)  = 0x000002c0;	\

+} while (0)

+

+/*

+ * I2C_SCK, I2C_SDA

+ */

+#define __gpio_as_i2c(n)		       \

+do {						\

+	REG_GPIO_PXFUNS(3+(n)) = 0xc0000000;	\

+	REG_GPIO_PXTRGC(3+(n)) = 0xc0000000;	\

+	REG_GPIO_PXSELC(3+(n)) = 0xc0000000;	\

+	REG_GPIO_PXPES(3+(n))  = 0xc0000000;	\

+} while (0)

+

+/*

+ * PWM0

+ */

+#define __gpio_as_pwm0()			\

+do {						\

+	REG_GPIO_PXFUNS(4) = 0x00100000;	\

+	REG_GPIO_PXSELC(4) = 0x00100000;	\

+	REG_GPIO_PXPES(4) = 0x00100000;		\

+} while (0)

+

+/*

+ * PWM1

+ */

+#define __gpio_as_pwm1()			\

+do {						\

+	REG_GPIO_PXFUNS(4) = 0x2;	        \

+	REG_GPIO_PXTRGC(4) = 0x2;		\

+	REG_GPIO_PXSELC(4) = 0x2;		\

+	REG_GPIO_PXPEC(4) = 0x2;		\

+} while (0)

+

+/*

+ * PWM2

+ */

+#define __gpio_as_pwm2()			\

+do {						\

+	REG_GPIO_PXFUNS(4) = 0x00400000;	\

+	REG_GPIO_PXSELC(4) = 0x00400000;	\

+	REG_GPIO_PXPES(4) = 0x00400000;		\

+} while (0)

+

+/*

+ * PWM3

+ */

+#define __gpio_as_pwm3()			\

+do {						\

+	REG_GPIO_PXFUNS(4) = 0x00800000;	\

+	REG_GPIO_PXSELC(4) = 0x00800000;	\

+	REG_GPIO_PXPES(4) = 0x00800000;		\

+} while (0)

+

+/*

+ * PWM4

+ */

+#define __gpio_as_pwm4()			\

+do {						\

+	REG_GPIO_PXFUNS(4) = 0x01000000;	\

+	REG_GPIO_PXSELC(4) = 0x01000000;	\

+	REG_GPIO_PXPES(4) = 0x01000000;		\

+} while (0)

+

+/*

+ * PWM5

+ */

+#define __gpio_as_pwm5()			\

+do {						\

+	REG_GPIO_PXFUNS(4) = 0x02000000;	\

+	REG_GPIO_PXSELC(4) = 0x02000000;	\

+	REG_GPIO_PXPES(4) = 0x02000000;		\

+} while (0)

+

+/*

+ * n = 0 ~ 5

+ */

+#define __gpio_as_pwm(n)	__gpio_as_pwm##n()

+

+/*

+ * OWI - PA29 function 1

+ */

+#define __gpio_as_owi()				\

+do {						\

+	REG_GPIO_PXFUNS(0) = 0x20000000;	\

+	REG_GPIO_PXTRGC(0) = 0x20000000;	\

+	REG_GPIO_PXSELS(0) = 0x20000000;	\

+} while (0)

+

+/*

+ * SCC - PD08 function 0

+ *       PD09 function 0

+ */

+#define __gpio_as_scc()				\

+do {						\

+	REG_GPIO_PXFUNS(3) = 0xc0000300;	\

+	REG_GPIO_PXTRGC(3) = 0xc0000300;	\

+	REG_GPIO_PXSELC(3) = 0xc0000300;	\

+} while (0)

+

+#define __gpio_as_otg_drvvbus()	\

+do {	\

+	REG_GPIO_PXDATC(4) = (1 << 10);		\

+	REG_GPIO_PXPEC(4) = (1 << 10);		\

+	REG_GPIO_PXSELC(4) = (1 << 10);		\

+	REG_GPIO_PXTRGC(4) = (1 << 10);		\

+	REG_GPIO_PXFUNS(4) = (1 << 10);		\

+} while (0)

+

+//-------------------------------------------

+// GPIO or Interrupt Mode

+

+#define __gpio_get_port(p)	(REG_GPIO_PXPIN(p))

+

+#define __gpio_port_as_output(p, o)		\

+do {						\

+    REG_GPIO_PXFUNC(p) = (1 << (o));		\

+    REG_GPIO_PXSELC(p) = (1 << (o));		\

+    REG_GPIO_PXDIRS(p) = (1 << (o));		\

+    REG_GPIO_PXPES(p) = (1 << (o));		\

+} while (0)

+

+#define __gpio_port_as_input(p, o)		\

+do {						\

+    REG_GPIO_PXFUNC(p) = (1 << (o));		\

+    REG_GPIO_PXSELC(p) = (1 << (o));		\

+    REG_GPIO_PXDIRC(p) = (1 << (o));		\

+} while (0)

+

+#define __gpio_as_output(n)			\

+do {						\

+	unsigned int p, o;			\

+	p = (n) / 32;				\

+	o = (n) % 32;				\

+	__gpio_port_as_output(p, o);		\

+} while (0)

+

+#define __gpio_as_input(n)			\

+do {						\

+	unsigned int p, o;			\

+	p = (n) / 32;				\

+	o = (n) % 32;				\

+	__gpio_port_as_input(p, o);		\

+} while (0)

+

+#define __gpio_set_pin(n)			\

+do {						\

+	unsigned int p, o;			\

+	p = (n) / 32;				\

+	o = (n) % 32;				\

+	REG_GPIO_PXDATS(p) = (1 << o);		\

+} while (0)

+

+#define __gpio_clear_pin(n)			\

+do {						\

+	unsigned int p, o;			\

+	p = (n) / 32;				\

+	o = (n) % 32;				\

+	REG_GPIO_PXDATC(p) = (1 << o);		\

+} while (0)

+

+#define __gpio_get_pin(n)			\

+({						\

+	unsigned int p, o, v;			\

+	p = (n) / 32;				\

+	o = (n) % 32;				\

+	if (__gpio_get_port(p) & (1 << o))	\

+		v = 1;				\

+	else					\

+		v = 0;				\

+	v;					\

+})

+

+#define __gpio_as_irq_high_level(n)		\

+do {						\

+	unsigned int p, o;			\

+	p = (n) / 32;				\

+	o = (n) % 32;				\

+	REG_GPIO_PXIMS(p) = (1 << o);		\

+	REG_GPIO_PXTRGC(p) = (1 << o);		\

+	REG_GPIO_PXFUNC(p) = (1 << o);		\

+	REG_GPIO_PXSELS(p) = (1 << o);		\

+	REG_GPIO_PXDIRS(p) = (1 << o);		\

+	REG_GPIO_PXFLGC(p) = (1 << o);		\

+	REG_GPIO_PXIMC(p) = (1 << o);		\

+} while (0)

+

+#define __gpio_as_irq_low_level(n)		\

+do {						\

+	unsigned int p, o;			\

+	p = (n) / 32;				\

+	o = (n) % 32;				\

+	REG_GPIO_PXIMS(p) = (1 << o);		\

+	REG_GPIO_PXTRGC(p) = (1 << o);		\

+	REG_GPIO_PXFUNC(p) = (1 << o);		\

+	REG_GPIO_PXSELS(p) = (1 << o);		\

+	REG_GPIO_PXDIRC(p) = (1 << o);		\

+	REG_GPIO_PXFLGC(p) = (1 << o);		\

+	REG_GPIO_PXIMC(p) = (1 << o);		\

+} while (0)

+

+#define __gpio_as_irq_rise_edge(n)		\

+do {						\

+	unsigned int p, o;			\

+	p = (n) / 32;				\

+	o = (n) % 32;				\

+	REG_GPIO_PXIMS(p) = (1 << o);		\

+	REG_GPIO_PXTRGS(p) = (1 << o);		\

+	REG_GPIO_PXFUNC(p) = (1 << o);		\

+	REG_GPIO_PXSELS(p) = (1 << o);		\

+	REG_GPIO_PXDIRS(p) = (1 << o);		\

+	REG_GPIO_PXFLGC(p) = (1 << o);		\

+	REG_GPIO_PXIMC(p) = (1 << o);		\

+} while (0)

+

+#define __gpio_as_irq_fall_edge(n)		\

+do {						\

+	unsigned int p, o;			\

+	p = (n) / 32;				\

+	o = (n) % 32;				\

+	REG_GPIO_PXIMS(p) = (1 << o);		\

+	REG_GPIO_PXTRGS(p) = (1 << o);		\

+	REG_GPIO_PXFUNC(p) = (1 << o);		\

+	REG_GPIO_PXSELS(p) = (1 << o);		\

+	REG_GPIO_PXDIRC(p) = (1 << o);		\

+	REG_GPIO_PXFLGC(p) = (1 << o);		\

+	REG_GPIO_PXIMC(p) = (1 << o);		\

+} while (0)

+

+#define __gpio_mask_irq(n)			\

+do {						\

+	unsigned int p, o;			\

+	p = (n) / 32;				\

+	o = (n) % 32;				\

+	REG_GPIO_PXIMS(p) = (1 << o);		\

+} while (0)

+

+#define __gpio_unmask_irq(n)			\

+do {						\

+	unsigned int p, o;			\

+	p = (n) / 32;				\

+	o = (n) % 32;				\

+	REG_GPIO_PXIMC(p) = (1 << o);		\

+} while (0)

+

+#define __gpio_ack_irq(n)			\

+do {						\

+	unsigned int p, o;			\

+	p = (n) / 32;				\

+	o = (n) % 32;				\

+	REG_GPIO_PXFLGC(p) = (1 << o);		\

+} while (0)

+

+#define __gpio_get_irq()			\

+({						\

+	unsigned int p, i, tmp, v = 0;		\

+	for (p = 3; p >= 0; p--) {		\

+		tmp = REG_GPIO_PXFLG(p);	\

+		for (i = 0; i < 32; i++)	\

+			if (tmp & (1 << i))	\

+				v = (32*p + i);	\

+	}					\

+	v;					\

+})

+

+#define __gpio_group_irq(n)			\

+({						\

+	register int tmp, i;			\

+	tmp = REG_GPIO_PXFLG(n) & (~REG_GPIO_PXIM(n));	\

+	for (i=31;i>=0;i--)			\

+		if (tmp & (1 << i))		\

+			break;			\

+	i;					\

+})

+

+#define __gpio_enable_pull(n)			\

+do {						\

+	unsigned int p, o;			\

+	p = (n) / 32;				\

+	o = (n) % 32;				\

+	REG_GPIO_PXPEC(p) = (1 << o);		\

+} while (0)

+

+#define __gpio_disable_pull(n)			\

+do {						\

+	unsigned int p, o;			\

+	p = (n) / 32;				\

+	o = (n) % 32;				\

+	REG_GPIO_PXPES(p) = (1 << o);		\

+} while (0)

+

+/* gpio driver strength function */

+#define __gpio_get_ds0(n)			\

+({						\

+	unsigned int p, o, v;			\

+	p = (n) / 32;				\

+	o = (n) % 32;				\

+	if (REG_GPIO_PXDS0(p) & (1 << o))	\

+		v = 1;				\

+	else					\

+		v = 0;				\

+	v;					\

+})

+#define __gpio_set_ds0(n)			\

+do {						\

+	unsigned int p, o;			\

+	p = (n) / 32;				\

+	o = (n) % 32;				\

+	REG_GPIO_PXDS0S(p) = (1 << o);		\

+} while (0)

+#define __gpio_clear_ds0(n)			\

+do {						\

+	unsigned int p, o;			\

+	p = (n) / 32;				\

+	o = (n) % 32;				\

+	REG_GPIO_PXDS0C(p) = (1 << o);		\

+} while (0)

+#define __gpio_get_ds1(n)			\

+({						\

+	unsigned int p, o, v;			\

+	p = (n) / 32;				\

+	o = (n) % 32;				\

+	if (REG_GPIO_PXDS1(p) & (1 << o))	\

+		v = 1;				\

+	else					\

+		v = 0;				\

+	v;					\

+})

+

+#define __gpio_set_ds1(n)			\

+do {						\

+	unsigned int p, o;			\

+	p = (n) / 32;				\

+	o = (n) % 32;				\

+	REG_GPIO_PXDS1S(p) = (1 << o);		\

+} while (0)

+#define __gpio_clear_ds1(n)			\

+do {						\

+	unsigned int p, o;			\

+	p = (n) / 32;				\

+	o = (n) % 32;				\

+	REG_GPIO_PXDS1C(p) = (1 << o);		\

+} while (0)

+#define __gpio_get_ds2(n)			\

+({						\

+	unsigned int p, o, v;			\

+	p = (n) / 32;				\

+	o = (n) % 32;				\

+	if (REG_GPIO_PXDS2(p) & (1 << o))	\

+		v = 1;				\

+	else					\

+		v = 0;				\

+	v;					\

+})

+#define __gpio_set_ds2(n)			\

+do {						\

+	unsigned int p, o;			\

+	p = (n) / 32;				\

+	o = (n) % 32;				\

+	REG_GPIO_PXDS2S(p) = (1 << o);		\

+} while (0)

+#define __gpio_clear_ds2(n)			\

+do {						\

+	unsigned int p, o;			\

+	p = (n) / 32;				\

+	o = (n) % 32;				\

+	REG_GPIO_PXDS2C(p) = (1 << o);		\

+} while (0)

+

+#define __gpio_get_slew_rate(n)			\

+({						\

+	unsigned int p, o, v;			\

+	p = (n) / 32;				\

+	o = (n) % 32;				\

+	if (REG_GPIO_PXSL(p) & (1 << o))	\

+		v = 1;				\

+	else					\

+		v = 0;				\

+	v;					\

+})

+#define __gpio_set_fast_slew_rate(n)		\

+do {						\

+	unsigned int p, o;			\

+	p = (n) / 32;				\

+	o = (n) % 32;				\

+	REG_GPIO_PXSLC(p) = (1 << o);		\

+} while (0)

+#define __gpio_set_low_slew_rate(n)		\

+do {						\

+	unsigned int p, o;			\

+	p = (n) / 32;				\

+	o = (n) % 32;				\

+	REG_GPIO_PXSLS(p) = (1 << o);		\

+} while (0)

+

+

+

+

+

+#endif /* __MIPS_ASSEMBLER */

+

+#endif /* __JZ4760BGPIO_H__ */

diff --git a/arch/mips/include/asm/mach-jz4760b/jz4760bi2c.h b/arch/mips/include/asm/mach-jz4760b/jz4760bi2c.h
new file mode 100644
index 00000000000..130367d4b64
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4760b/jz4760bi2c.h
@@ -0,0 +1,275 @@
+/*

+ * linux/include/asm-mips/mach-jz4810/jz4810i2c.h

+ *

+ * JZ4810 I2C register definition.

+ *

+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

+ */

+

+#ifndef __JZ4810I2C_H__

+#define __JZ4810I2C_H__

+

+#define JZ_I2C_NUM	3

+

+#define	I2C0_BASE	0xB0050000

+#define	I2C1_BASE	0xB0051000

+#define I2C2_BASE	0xB0055000

+

+

+/*************************************************************************

+ * I2C

+ *************************************************************************/

+#define	I2C_CTRL(n)		(I2C0_BASE + (n)*0x1000 + 0x00)

+#define	I2C_TAR(n)     		(I2C0_BASE + (n)*0x1000 + 0x04)

+#define	I2C_SAR(n)     		(I2C0_BASE + (n)*0x1000 + 0x08)

+#define	I2C_DC(n)      		(I2C0_BASE + (n)*0x1000 + 0x10)

+#define	I2C_SHCNT(n)		(I2C0_BASE + (n)*0x1000 + 0x14)

+#define	I2C_SLCNT(n)		(I2C0_BASE + (n)*0x1000 + 0x18)

+#define	I2C_FHCNT(n)		(I2C0_BASE + (n)*0x1000 + 0x1C)

+#define	I2C_FLCNT(n)		(I2C0_BASE + (n)*0x1000 + 0x20)

+#define	I2C_INTST(n)		(I2C0_BASE + (n)*0x1000 + 0x2C)

+#define	I2C_INTM(n)		(I2C0_BASE + (n)*0x1000 + 0x30)

+#define I2C_RXTL(n)		(I2C0_BASE + (n)*0x1000 + 0x38)

+#define I2C_TXTL(n)		(I2C0_BASE + (n)*0x1000 + 0x3c)

+#define	I2C_CINTR(n)		(I2C0_BASE + (n)*0x1000 + 0x40)

+#define	I2C_CRXUF(n)		(I2C0_BASE + (n)*0x1000 + 0x44)

+#define	I2C_CRXOF(n)		(I2C0_BASE + (n)*0x1000 + 0x48)

+#define	I2C_CTXOF(n)		(I2C0_BASE + (n)*0x1000 + 0x4C)

+#define	I2C_CRXREQ(n)		(I2C0_BASE + (n)*0x1000 + 0x50)

+#define	I2C_CTXABRT(n)		(I2C0_BASE + (n)*0x1000 + 0x54)

+#define	I2C_CRXDONE(n)		(I2C0_BASE + (n)*0x1000 + 0x58)

+#define	I2C_CACT(n)		(I2C0_BASE + (n)*0x1000 + 0x5C)

+#define	I2C_CSTP(n)		(I2C0_BASE + (n)*0x1000 + 0x60)

+#define	I2C_CSTT(n)		(I2C0_BASE + (n)*0x1000 + 0x64)

+#define	I2C_CGC(n)    		(I2C0_BASE + (n)*0x1000 + 0x68)

+#define	I2C_ENB(n)     		(I2C0_BASE + (n)*0x1000 + 0x6C)

+#define	I2C_STA(n)     		(I2C0_BASE + (n)*0x1000 + 0x70)

+#define I2C_TXFLR(n)		(I2C0_BASE + (n)*0x1000 + 0x74)

+#define I2C_RXFLR(n)		(I2C0_BASE + (n)*0x1000 + 0x78)

+#define	I2C_TXABRT(n)		(I2C0_BASE + (n)*0x1000 + 0x80)

+#define I2C_DMACR(n)            (I2C0_BASE + (n)*0x1000 + 0x88)

+#define I2C_DMATDLR(n)          (I2C0_BASE + (n)*0x1000 + 0x8c)

+#define I2C_DMARDLR(n)          (I2C0_BASE + (n)*0x1000 + 0x90)

+#define	I2C_SDASU(n)		(I2C0_BASE + (n)*0x1000 + 0x94)

+#define	I2C_ACKGC(n)		(I2C0_BASE + (n)*0x1000 + 0x98)

+#define	I2C_ENSTA(n)		(I2C0_BASE + (n)*0x1000 + 0x9C)

+#define I2C_SDAHD(n)		(I2C0_BASE + (n)*0x1000 + 0xD0)

+

+#define	REG_I2C_CTRL(n)		REG8(I2C_CTRL(n)) /* I2C Control Register (I2C_CTRL) */

+#define	REG_I2C_TAR(n)		REG16(I2C_TAR(n)) /* I2C target address (I2C_TAR) */

+#define REG_I2C_SAR(n)		REG16(I2C_SAR(n))

+#define REG_I2C_DC(n)		REG16(I2C_DC(n))

+#define REG_I2C_SHCNT(n)       	REG16(I2C_SHCNT(n))

+#define REG_I2C_SLCNT(n)       	REG16(I2C_SLCNT(n))

+#define REG_I2C_FHCNT(n)       	REG16(I2C_FHCNT(n))

+#define REG_I2C_FLCNT(n)       	REG16(I2C_FLCNT(n))

+#define REG_I2C_INTST(n)       	REG16(I2C_INTST(n)) /* i2c interrupt status (I2C_INTST) */

+#define REG_I2C_INTM(n)		REG16(I2C_INTM(n)) /* i2c interrupt mask status (I2C_INTM) */

+#define REG_I2C_RXTL(n)		REG8(I2C_RXTL(n))

+#define REG_I2C_TXTL(n)		REG8(I2C_TXTL(n))

+#define REG_I2C_CINTR(n)       	REG8(I2C_CINTR(n))

+#define REG_I2C_CRXUF(n)       	REG8(I2C_CRXUF(n))

+#define REG_I2C_CRXOF(n)       	REG8(I2C_CRXOF(n))

+#define REG_I2C_CTXOF(n)       	REG8(I2C_CTXOF(n))

+#define REG_I2C_CRXREQ(n)      	REG8(I2C_CRXREQ(n))

+#define REG_I2C_CTXABRT(n)     	REG8(I2C_CTXABRT(n))

+#define REG_I2C_CRXDONE(n)     	REG8(I2C_CRXDONE(n))

+#define REG_I2C_CACT(n)		REG8(I2C_CACT(n))

+#define REG_I2C_CSTP(n)		REG8(I2C_CSTP(n))

+#define REG_I2C_CSTT(n)		REG16(I2C_CSTT(n))

+#define REG_I2C_CGC(n)		REG8(I2C_CGC(n))

+#define REG_I2C_ENB(n)		REG8(I2C_ENB(n))

+#define REG_I2C_STA(n)		REG8(I2C_STA(n))

+#define REG_I2C_TXFLR(n)	REG8(I2C_TXFLR(n))

+#define REG_I2C_RXFLR(n)	REG8(I2C_RXFLR(n))

+#define REG_I2C_TXABRT(n)      	REG16(I2C_TXABRT(n))

+#define REG_I2C_DMACR(n)        REG8(I2C_DMACR(n))

+#define REG_I2C_DMATDLR(n)      REG8(I2C_DMATDLR(n))

+#define REG_I2C_DMARDLR(n)      REG8(I2C_DMARDLR(n))

+#define REG_I2C_SDASU(n)       	REG8(I2C_SDASU(n))

+#define REG_I2C_ACKGC(n)       	REG8(I2C_ACKGC(n))

+#define REG_I2C_ENSTA(n)       	REG8(I2C_ENSTA(n))

+#define REG_I2C_SDAHD(n)	REG16(I2C_SDAHD(n))

+

+/* I2C Control Register (I2C_CTRL) */

+

+#define I2C_CTRL_STPHLD		(1 << 7)

+#define I2C_CTRL_SLVDIS		(1 << 6) /* after reset slave is disabled*/

+#define I2C_CTRL_REST		(1 << 5)

+#define I2C_CTRL_MATP		(1 << 4) /* 1: 10bit address 0: 7bit addressing*/

+#define I2C_CTRL_SATP		(1 << 3) /* standard mode 100kbps */

+#define I2C_CTRL_SPDF		(2 << 1) /* fast mode 400kbps */

+#define I2C_CTRL_SPDS		(1 << 1) /* standard mode 100kbps */

+#define I2C_CTRL_MD		(1 << 0) /* master enabled*/

+

+/* I2C target address (I2C_TAR) */

+

+#define I2C_TAR_MATP		(1 << 12)

+#define I2C_TAR_SPECIAL		(1 << 11)

+#define I2C_TAR_GC_OR_START	(1 << 10)

+

+/* I2C slave address  */

+/* I2C data buffer and command (I2C_DC) */

+

+#define I2C_DC_CMD			(1 << 8) /* 1 read 0  write*/

+

+/* i2c interrupt status (I2C_INTST) */

+

+#define I2C_INTST_IGC			(1 << 11) /* */

+#define I2C_INTST_ISTT			(1 << 10)

+#define I2C_INTST_ISTP			(1 << 9)

+#define I2C_INTST_IACT			(1 << 8)

+#define I2C_INTST_RXDN			(1 << 7)

+#define I2C_INTST_TXABT			(1 << 6)

+#define I2C_INTST_RDREQ			(1 << 5)

+#define I2C_INTST_TXEMP			(1 << 4)

+#define I2C_INTST_TXOF			(1 << 3)

+#define I2C_INTST_RXFL			(1 << 2)

+#define I2C_INTST_RXOF			(1 << 1)

+#define I2C_INTST_RXUF			(1 << 0)

+

+/* i2c interrupt mask status (I2C_INTM) */

+

+#define I2C_INTM_MIGC			(1 << 11) /* */

+#define I2C_INTM_MISTT			(1 << 10)

+#define I2C_INTM_MISTP			(1 << 9)

+#define I2C_INTM_MIACT			(1 << 8)

+#define I2C_INTM_MRXDN			(1 << 7)

+#define I2C_INTM_MTXABT			(1 << 6)

+#define I2C_INTM_MRDREQ			(1 << 5)

+#define I2C_INTM_MTXEMP			(1 << 4)

+#define I2C_INTM_MTXOF			(1 << 3)

+#define I2C_INTM_MRXFL			(1 << 2)

+#define I2C_INTM_MRXOF			(1 << 1)

+#define I2C_INTM_MRXUF			(1 << 0)

+

+/* I2C Clear Combined and Individual Interrupts (I2C_CINTR) */

+

+#define I2C_CINTR_CINT

+

+/* I2C Clear TX_OVER Interrupt */

+/* I2C Clear RDREQ Interrupt */

+/* I2C Clear TX_ABRT Interrupt */

+/* I2C Clear RX_DONE Interrupt */

+/* I2C Clear ACTIVITY Interrupt */

+/* I2C Clear STOP Interrupts */

+/* I2C Clear START Interrupts */

+/* I2C Clear GEN_CALL Interrupts */

+

+/* I2C Enable (I2C_ENB) */

+

+#define I2C_ENB_I2CENB 		(1 << 0) /* Enable the i2c */

+

+/* I2C Status Register (I2C_STA) */

+

+#define I2C_STA_SLVACT		(1 << 6) /* Slave FSM is not in IDLE state */

+#define I2C_STA_MSTACT		(1 << 5) /* Master FSM is not in IDLE state */

+#define I2C_STA_RFF		(1 << 4) /* RFIFO if full */

+#define I2C_STA_RFNE		(1 << 3) /* RFIFO is not empty */

+#define I2C_STA_TFE		(1 << 2) /* TFIFO is empty */

+#define I2C_STA_TFNF		(1 << 1) /* TFIFO is not full  */

+#define I2C_STA_ACT		(1 << 0) /* I2C Activity Status */

+

+/* I2C Transmit Abort Status Register (I2C_TXABRT) */

+

+#define I2C_TXABRT_SLVRD_INTX		(1 << 15)

+#define I2C_TXABRT_SLV_ARBLOST		(1 << 14)

+#define I2C_TXABRT_SLVFLUSH_TXFIFO	(1 << 13)

+#define I2C_TXABRT_ARB_LOST		(1 << 12)

+#define I2C_TXABRT_ABRT_MASTER_DIS	(1 << 11)

+#define I2C_TXABRT_ABRT_10B_RD_NORSTRT	(1 << 10)

+#define I2C_TXABRT_SBYTE_NORSTRT	(1 << 9)

+#define I2C_TXABRT_ABRT_HS_NORSTRT	(1 << 8)

+#define I2C_TXABRT_SBYTE_ACKDET		(1 << 7)

+#define I2C_TXABRT_ABRT_HS_ACKD		(1 << 6)

+#define I2C_TXABRT_ABRT_GCALL_READ	(1 << 5)

+#define I2C_TXABRT_ABRT_GCALL_NOACK	(1 << 4)

+#define I2C_TXABRT_ABRT_XDATA_NOACK	(1 << 3)

+#define I2C_TXABRT_ABRT_10ADDR2_NOACK	(1 << 2)

+#define I2C_TXABRT_ABRT_10ADDR1_NOACK	(1 << 1)

+#define I2C_TXABRT_ABRT_7B_ADDR_NOACK	(1 << 0)

+

+/* I2C Enable Status Register (I2C_ENSTA) */

+

+#define I2C_ENSTA_SLVRDLST		(1 << 2)

+#define I2C_ENSTA_SLVDISB 		(1 << 1)

+#define I2C_ENSTA_I2CEN 		(1 << 0) /* when read as 1, i2c is deemed to be in an enabled state

+						    when read as 0, i2c is deemed completely inactive. The cpu can

+						 safely read this bit anytime .When this bit is read as 0 ,the cpu can

+						 safely read SLVRDLST and SLVDISB */

+

+#define I2C_SDASU_SETUP_TIME_BASE	0

+#define I2C_SDASU_SETUP_TIME_MASK	0xff

+

+#define I2C_SDAHD_HOLD_TIME_BASE	0

+#define I2C_SDAHD_HOLD_TIME_MASK	0xff

+#define I2C_SDAHD_HOLD_TIME_EN		(1 << 8)

+

+#ifndef __MIPS_ASSEMBLER

+

+/***************************************************************************

+ * I2C

+ ***************************************************************************/

+

+#define __i2c_enable(n)		( REG_I2C_ENB(n) = 1 )

+#define __i2c_disable(n)       	( REG_I2C_ENB(n) = 0 )

+

+#define __i2c_is_enable(n)       ( REG_I2C_ENSTA(n) & I2C_ENB_I2CENB )

+#define __i2c_is_disable(n)      ( !(REG_I2C_ENSTA(n) & I2C_ENB_I2CENB) )

+

+#define __i2c_abrt(n)            ( REG_I2C_TXABRT(n) != 0 )

+#define __i2c_master_active(n)   ( REG_I2C_STA(n) & I2C_STA_MSTACT )

+#define __i2c_abrt_7b_addr_nack(n)  ( REG_I2C_TXABRT(n) & I2C_TXABRT_ABRT_7B_ADDR_NOACK )

+#define __i2c_txfifo_is_empty(n)     ( REG_I2C_STA(n) & I2C_STA_TFE )

+#define __i2c_clear_interrupts(ret,n)    ( ret = REG_I2C_CINTR(n) )

+

+#define __i2c_dma_rd_enable(n)        SETREG8(I2C_DMACR(n),1 << 0)

+#define __i2c_dma_rd_disable(n)       CLRREG8(I2C_DMACR(n),1 << 0)

+#define __i2c_dma_td_enable(n)        SETREG8(I2C_DMACR(n),1 << 1)

+#define __i2c_dma_td_disable(n)       CLRREG8(I2C_DMACR(n),1 << 1)

+

+#define __i2c_send_stop(n)           CLRREG8(I2C_SHCNT(n), I2C_CTRL_STPHLD)

+#define __i2c_nsend_stop(n)          SETREG8(I2C_SHCNT(n), I2C_CTRL_STPHLD)

+

+#define __i2c_set_dma_td_level(n,data) OUTREG8(I2C_DMATDLR(n),data)

+#define __i2c_set_dma_rd_level(n,data) OUTREG8(I2C_DMARDLR(n),data)

+

+#define __i2c_hold_time_enable(n) SETREG16(I2C_SDAHD(n), I2C_SDAHD_HOLD_TIME_EN)

+#define __i2c_hold_time_disable(n) CLRREG16(I2C_SDAHD(n), I2C_SDAHD_HOLD_TIME_EN)

+#define __i2c_set_hold_time(n, ht)					\

+	do {								\

+		CLRREG16(I2C_SDAHD(n), I2C_SDAHD_HOLD_TIME_MASK);	\

+		SETREG16(I2C_SDAHD(n), ((ht) & I2C_SDAHD_HOLD_TIME_MASK)); \

+	} while(0)

+

+#define __i2c_set_setup_time(n, su)					\

+	do {								\

+		CLRREG16(I2C_SDASU(n), I2C_SDASU_SETUP_TIME_MASK);	\

+		SETREG16(I2C_SDASU(n), ((su) & I2C_SDASU_SETUP_TIME_MASK)); \

+	} while(0) 

+

+/* I2C standard mode high count register(I2CSHCNT) */

+#define I2CSHCNT_ADJUST(n)      (((n) - 8) < 6 ? 6 : ((n) - 8))

+

+/* I2C standard mode low count register(I2CSLCNT) */

+#define I2CSLCNT_ADJUST(n)      (((n) - 1) < 8 ? 8 : ((n) - 1))

+

+/* I2C fast mode high count register(I2CFHCNT) */

+#define I2CFHCNT_ADJUST(n)      (((n) - 8) < 6 ? 6 : ((n) - 8))

+

+/* I2C fast mode low count register(I2CFLCNT) */

+#define I2CFLCNT_ADJUST(n)      (((n) - 1) < 8 ? 8 : ((n) - 1))

+

+/*

+#define __i2c_set_clk(dev_clk, i2c_clk) \

+  ( REG_I2C_GR = (dev_clk) / (16*(i2c_clk)) - 1 )

+*/

+

+#define __i2c_read(n)		( REG_I2C_DC(n) & 0xff )

+#define __i2c_write(val,n)	( REG_I2C_DC(n) = (val) )

+

+

+#endif /* __MIPS_ASSEMBLER */

+

+#endif /* __JZ4810I2C_H__ */

+

diff --git a/arch/mips/include/asm/mach-jz4760b/jz4760bintc.h b/arch/mips/include/asm/mach-jz4760b/jz4760bintc.h
new file mode 100644
index 00000000000..6411be0ee5c
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4760b/jz4760bintc.h
@@ -0,0 +1,115 @@
+/*

+ * linux/include/asm-mips/mach-jz4760b/jz4760bintc.h

+ *

+ * JZ4760B INTC register definition.

+ *

+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

+ */

+

+#ifndef __JZ4760BINTC_H__

+#define __JZ4760BINTC_H__

+

+

+#define	INTC_BASE	0xB0001000

+

+

+/*************************************************************************

+ * INTC (Interrupt Controller)

+ *************************************************************************/

+/* n = 0 ~ 1 */

+#define INTC_ISR(n)	(INTC_BASE + 0x00 + (n) * 0x20)

+#define INTC_IMR(n)	(INTC_BASE + 0x04 + (n) * 0x20)

+#define INTC_ICMR(n)    INTC_IMR(n)

+#define INTC_IMSR(n)	(INTC_BASE + 0x08 + (n) * 0x20)

+#define INTC_ICMSR(n)   INTC_IMSR(n)

+#define INTC_IMCR(n)	(INTC_BASE + 0x0c + (n) * 0x20)

+#define INTC_ICMCR(n)	INTC_IMCR(n)

+#define INTC_IPR(n)	(INTC_BASE + 0x10 + (n) * 0x20)

+//#define INTC_ISSR	(INTC_BASE + 0x18)  /* Interrupt Controller Source Set Register */

+//#define INTC_ISCR	(INTC_BASE + 0x1c)  /* Interrupt Controller Source Clear Register */

+

+#define REG_INTC_ISR(n)		REG32(INTC_ISR(n))

+#define REG_INTC_IMR(n)		REG32(INTC_IMR(n))

+#define REG_INTC_IMSR(n)	REG32(INTC_IMSR(n))

+#define REG_INTC_IMCR(n)	REG32(INTC_IMCR(n))

+#define REG_INTC_IPR(n)		REG32(INTC_IPR(n))

+//#define REG_INTC_ISSR   REG32(INTC_ISSR)

+//#define REG_INTC_ISCR   REG32(INTC_ISCR)

+

+// 1st-level interrupts

+#define IRQ_I2C1	0

+#define IRQ_I2C0	1

+#define IRQ_UART3	2

+#define IRQ_UART2	3

+#define IRQ_UART1	4

+#define IRQ_UART0	5

+#define IRQ_SSI2   	6

+#define IRQ_SSI1   	7

+#define IRQ_SSI0   	8

+#define IRQ_TSSI	9

+#define IRQ_BDMA	10

+#define IRQ_KBC		11

+#define IRQ_GPIO5	12

+#define IRQ_GPIO4	13

+#define IRQ_GPIO3	14

+#define IRQ_GPIO2	15

+#define IRQ_GPIO1	16

+#define IRQ_GPIO0	17

+#define IRQ_SADC	18

+#define IRQ_ETH		19

+#define IRQ_UHC		20

+#define IRQ_OTG		21

+#define IRQ_MDMA	22

+#define IRQ_DMAC1	23

+#define IRQ_DMAC0	24

+#define IRQ_TCU2	25

+#define IRQ_TCU1	26

+#define IRQ_TCU0	27

+#define IRQ_GPS		28

+#define IRQ_IPU		29

+#define IRQ_CIM		30

+#define IRQ_LCD		31

+

+#define IRQ_RTC		32

+#define IRQ_OWI		33

+#define IRQ_AIC 	34

+#define IRQ_MSC2	35

+#define IRQ_MSC1	36

+#define IRQ_MSC0	37

+#define IRQ_SCC		38

+#define IRQ_BCH		39

+#define IRQ_PCM		40

+

+

+// 2nd-level interrupts

+

+#define IRQ_DMA_0	46  /* 64 ~ 75 for DMAC0 channel 0 ~ 5 & DMAC1 channel 0 ~ 5 */

+//#define IRQ_DMA_0	32  /* 64 ~ 75 for DMAC0 channel 0 ~ 5 & DMAC1 channel 0 ~ 5 */

+#define IRQ_DMA_1	(IRQ_DMA_0 + HALF_DMA_NUM)  /* 64 ~ 75 for DMAC0 channel 0 ~ 5 & DMAC1 channel 0 ~ 5 */

+#define IRQ_MDMA_0	(IRQ_DMA_0 + MAX_DMA_NUM)   /* 64 ~ 66 for MDMAC channel 0 ~ 2 */

+#define IRQ_BDMA_0  (IRQ_DMA_0 + MAX_DMA_NUM + MAX_MDMA_NUM) /* 61 ~ 63 for BDMA channel 0 ~ 2 */

+

+//#define IRQ_GPIO_0	96  /* 96 to 287 for GPIO pin 0 to 127 */

+#define IRQ_GPIO_0	64  /* 96 to 287 for GPIO pin 0 to 127 */

+

+#define NUM_INTC	41

+#define NUM_DMA         MAX_DMA_NUM	/* 12 */

+#define NUM_MDMA        MAX_MDMA_NUM	/* 3 */

+#define NUM_GPIO        MAX_GPIO_NUM	/* GPIO NUM: 192, Jz4760b real num GPIO 178 */

+

+

+#ifndef __MIPS_ASSEMBLER

+

+

+/***************************************************************************

+ * INTC

+ ***************************************************************************/

+#define __intc_unmask_irq(n)	(REG_INTC_IMCR((n)/32) = (1 << ((n)%32)))

+#define __intc_mask_irq(n)	(REG_INTC_IMSR((n)/32) = (1 << ((n)%32)))

+#define __intc_ack_irq(n)	(REG_INTC_IPR((n)/32) = (1 << ((n)%32))) /* A dummy ack, as the Pending Register is Read Only. Should we remove __intc_ack_irq() */

+

+

+#endif /* __MIPS_ASSEMBLER */

+

+#endif /* __JZ4760BINTC_H__ */

+

diff --git a/arch/mips/include/asm/mach-jz4760b/jz4760bipu.h b/arch/mips/include/asm/mach-jz4760b/jz4760bipu.h
new file mode 100644
index 00000000000..bf72354e0c7
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4760b/jz4760bipu.h
@@ -0,0 +1,328 @@
+/*

+ * linux/include/asm-mips/mach-jz4760b/jz4760bipu.h

+ *

+ * JZ4760B IPU register definition.

+ *

+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

+ */

+

+#ifndef __JZ4760BIPU_H__

+#define __JZ4760BIPU_H__

+

+

+#define	IPU_BASE	0xB3080000

+

+/*************************************************************************

+ * IPU (Image Processing Unit)

+ *************************************************************************/

+#define IPU_V_BASE		0xB3080000

+#define IPU_P_BASE		0x13080000

+

+/* Register offset */

+#define REG_CTRL		0x0  /* IPU Control Register */

+#define REG_STATUS		0x4  /* IPU Status Register */

+#define REG_D_FMT		0x8  /* Data Format Register */

+#define REG_Y_ADDR		0xc  /* Input Y or YUV422 Packaged Data Address Register */

+#define REG_U_ADDR		0x10 /* Input U Data Address Register */

+#define REG_V_ADDR		0x14 /* Input V Data Address Register */

+#define REG_IN_FM_GS		0x18 /* Input Geometric Size Register */

+#define REG_Y_STRIDE		0x1c /* Input Y Data Line Stride Register */

+#define REG_UV_STRIDE		0x20 /* Input UV Data Line Stride Register */

+#define REG_OUT_ADDR		0x24 /* Output Frame Start Address Register */

+#define REG_OUT_GS		0x28 /* Output Geometric Size Register */

+#define REG_OUT_STRIDE		0x2c /* Output Data Line Stride Register */

+#define REG_RSZ_COEF_INDEX	0x30 /* Resize Coefficients Table Index Register */

+#define REG_CSC_CO_COEF		0x34 /* CSC C0 Coefficient Register */

+#define REG_CSC_C1_COEF		0x38 /* CSC C1 Coefficient Register */

+#define REG_CSC_C2_COEF 	0x3c /* CSC C2 Coefficient Register */

+#define REG_CSC_C3_COEF 	0x40 /* CSC C3 Coefficient Register */

+#define REG_CSC_C4_COEF 	0x44 /* CSC C4 Coefficient Register */

+#define HRSZ_LUT_BASE 		0x48 /* Horizontal Resize Coefficients Look Up Table Register group */

+#define VRSZ_LUT_BASE 		0x4c /* Virtical Resize Coefficients Look Up Table Register group */

+#define REG_CSC_OFSET_PARA	0x50 /* CSC Offset Parameter Register */

+#define REG_Y_PHY_T_ADDR	0x54 /* Input Y Physical Table Address Register */

+#define REG_U_PHY_T_ADDR	0x58 /* Input U Physical Table Address Register */

+#define REG_V_PHY_T_ADDR	0x5c /* Input V Physical Table Address Register */

+#define REG_OUT_PHY_T_ADDR	0x60 /* Output Physical Table Address Register */

+

+/* REG_CTRL: IPU Control Register */

+#define IPU_CE_SFT	0x0

+#define IPU_CE_MSK	0x1

+#define IPU_RUN_SFT	0x1

+#define IPU_RUN_MSK	0x1

+#define HRSZ_EN_SFT	0x2

+#define HRSZ_EN_MSK	0x1

+#define VRSZ_EN_SFT	0x3

+#define VRSZ_EN_MSK	0x1

+#define CSC_EN_SFT	0x4

+#define CSC_EN_MSK	0x1

+#define FM_IRQ_EN_SFT	0x5

+#define FM_IRQ_EN_MSK	0x1

+#define IPU_RST_SFT	0x6

+#define IPU_RST_MSK	0x1

+#define H_SCALE_SFT	0x8

+#define H_SCALE_MSK	0x1

+#define V_SCALE_SFT	0x9

+#define V_SCALE_MSK	0x1

+#define PKG_SEL_SFT	0xA

+#define PKG_SEL_MSK	0x1

+#define LCDC_SEL_SFT	0xB

+#define LCDC_SEL_MSK	0x1

+#define SPAGE_MAP_SFT	0xC

+#define SPAGE_MAP_MSK	0x1

+#define DPAGE_SEL_SFT	0xD

+#define DPAGE_SEL_MSK	0x1

+#define DISP_SEL_SFT	0xE

+#define DISP_SEL_MSK	0x1

+#define FIELD_CONF_EN_SFT 15

+#define FIELD_CONF_EN_MSK 1

+#define FIELD_SEL_SFT	16

+#define FIELD_SEL_MSK	1

+#define DFIX_SEL_SFT	17

+#define DFIX_SEL_MSK	1

+

+/* REG_STATUS: IPU Status Register */

+#define OUT_END_SFT	0x0

+#define OUT_END_MSK	0x1

+#define FMT_ERR_SFT	0x1

+#define FMT_ERR_MSK	0x1

+#define SIZE_ERR_SFT	0x2

+#define SIZE_ERR_MSK	0x1

+

+/* D_FMT: Data Format Register */

+#define IN_FMT_SFT	0x0

+#define IN_FMT_MSK 	0x3

+#define IN_OFT_SFT 	0x2

+#define IN_OFT_MSK 	0x3

+#define YUV_PKG_OUT_SFT	0x10

+#define YUV_PKG_OUT_MSK	0x7

+#define OUT_FMT_SFT 	0x13

+#define OUT_FMT_MSK 	0x3

+#define RGB_OUT_OFT_SFT	0x15

+#define RGB_OUT_OFT_MSK	0x7

+#define RGB888_FMT_SFT	0x18

+#define RGB888_FMT_MSK	0x1

+

+/* IN_FM_GS: Input Geometric Size Register */

+#define IN_FM_H_SFT	0x0

+#define IN_FM_H_MSK	0xFFF

+#define IN_FM_W_SFT	0x10

+#define IN_FM_W_MSK	0xFFF

+

+/* Y_STRIDE: Input Y Data Line Stride Register */

+#define Y_S_SFT		0x0

+#define Y_S_MSK		0x3FFF

+

+/* UV_STRIDE: Input UV Data Line Stride Register */

+#define V_S_SFT		0x0

+#define V_S_MSK		0x1FFF

+#define U_S_SFT 	0x10

+#define U_S_MSK		0x1FFF

+

+/* OUT_GS: Output Geometric Size Register */

+#define OUT_FM_H_SFT	0x0

+#define OUT_FM_H_MSK	0x1FFF

+#define OUT_FM_W_SFT	0x10

+#define OUT_FM_W_MSK	0x7FFF

+

+/* OUT_STRIDE: Output Data Line Stride Register */

+#define OUT_S_SFT	0x0

+#define OUT_S_MSK	0xFFFF

+

+/* RSZ_COEF_INDEX: Resize Coefficients Table Index Register */

+#define VE_IDX_SFT	0x0

+#define VE_IDX_MSK	0x1F

+#define HE_IDX_SFT	0x10

+#define HE_IDX_MSK	0x1F

+

+/* CSC_CX_COEF: CSC CX Coefficient Register */

+#define CX_COEF_SFT	0x0

+#define CX_COEF_MSK	0xFFF

+

+/* HRSZ_LUT_BASE, VRSZ_LUT_BASE: Resize Coefficients Look Up Table Register group */

+#define LUT_LEN		20

+

+#define OUT_N_SFT	0x0

+#define OUT_N_MSK	0x1

+#define IN_N_SFT	0x1

+#define IN_N_MSK	0x1

+#define W_COEF_SFT	0x2

+#define W_COEF_MSK	0x3FF

+

+/* CSC_OFSET_PARA: CSC Offset Parameter Register */

+#define CHROM_OF_SFT	0x10

+#define CHROM_OF_MSK	0xFF

+#define LUMA_OF_SFT	0x00

+#define LUMA_OF_MSK	0xFF

+

+

+#ifndef __MIPS_ASSEMBLER

+

+

+#if 0

+/*************************************************************************

+ * IPU (Image Processing Unit)

+ *************************************************************************/

+#define u32 volatile unsigned long

+

+#define write_reg(reg, val)	\

+do {				\

+	*(u32 *)(reg) = (val);	\

+} while(0)

+

+#define read_reg(reg, off)	(*(u32 *)((reg)+(off)))

+

+

+#define set_ipu_fmt(rgb_888_out_fmt, rgb_out_oft, out_fmt, yuv_pkg_out, in_oft, in_fmt ) \

+({ write_reg( (IPU_V_BASE + REG_D_FMT), ((in_fmt) & IN_FMT_MSK)<<IN_FMT_SFT \

+| ((in_oft) & IN_OFT_MSK)<< IN_OFT_SFT \

+| ((out_fmt) & OUT_FMT_MSK)<<OUT_FMT_SFT \

+| ((yuv_pkg_out) & YUV_PKG_OUT_MSK ) << YUV_PKG_OUT_SFT \

+| ((rgb_888_out_fmt) & RGB888_FMT_MSK ) << RGB888_FMT_SFT \

+| ((rgb_out_oft) & RGB_OUT_OFT_MSK ) << RGB_OUT_OFT_SFT); \

+})

+#define set_y_addr(y_addr) \

+({ write_reg( (IPU_V_BASE + REG_Y_ADDR), y_addr); \

+})

+#define set_u_addr(u_addr) \

+({ write_reg( (IPU_V_BASE + REG_U_ADDR), u_addr); \

+})

+

+#define set_v_addr(v_addr) \

+({ write_reg( (IPU_V_BASE + REG_V_ADDR), v_addr); \

+})

+

+#define set_y_phy_t_addr(y_phy_t_addr) \

+({ write_reg( (IPU_V_BASE + REG_Y_PHY_T_ADDR), y_phy_t_addr); \

+})

+

+#define set_u_phy_t_addr(u_phy_t_addr) \

+({ write_reg( (IPU_V_BASE + REG_U_PHY_T_ADDR), u_phy_t_addr); \

+})

+

+#define set_v_phy_t_addr(v_phy_t_addr) \

+({ write_reg( (IPU_V_BASE + REG_V_PHY_T_ADDR), v_phy_t_addr); \

+})

+

+#define set_out_phy_t_addr(out_phy_t_addr) \

+({ write_reg( (IPU_V_BASE + REG_OUT_PHY_T_ADDR), out_phy_t_addr); \

+})

+

+#define set_inframe_gsize(width, height, y_stride, u_stride, v_stride) \

+({ write_reg( (IPU_V_BASE + REG_IN_FM_GS), ((width) & IN_FM_W_MSK)<<IN_FM_W_SFT \

+| ((height) & IN_FM_H_MSK)<<IN_FM_H_SFT); \

+ write_reg( (IPU_V_BASE + REG_Y_STRIDE), ((y_stride) & Y_S_MSK)<<Y_S_SFT); \

+ write_reg( (IPU_V_BASE + REG_UV_STRIDE), ((u_stride) & U_S_MSK)<<U_S_SFT \

+| ((v_stride) & V_S_MSK)<<V_S_SFT); \

+})

+#define set_out_addr(out_addr) \

+({ write_reg( (IPU_V_BASE + REG_OUT_ADDR), out_addr); \

+})

+#define set_outframe_gsize(width, height, o_stride) \

+({ write_reg( (IPU_V_BASE + REG_OUT_GS), ((width) & OUT_FM_W_MSK)<<OUT_FM_W_SFT \

+| ((height) & OUT_FM_H_MSK)<<OUT_FM_H_SFT); \

+ write_reg( (IPU_V_BASE + REG_OUT_STRIDE), ((o_stride) & OUT_S_MSK)<<OUT_S_SFT); \

+})

+#define set_rsz_lut_end(h_end, v_end) \

+({ write_reg( (IPU_V_BASE + REG_RSZ_COEF_INDEX), ((h_end) & HE_IDX_MSK)<<HE_IDX_SFT \

+| ((v_end) & VE_IDX_MSK)<<VE_IDX_SFT); \

+})

+#define set_csc_c0(c0_coeff) \

+({ write_reg( (IPU_V_BASE + REG_CSC_CO_COEF), ((c0_coeff) & CX_COEF_MSK)<<CX_COEF_SFT); \

+})

+#define set_csc_c1(c1_coeff) \

+({ write_reg( (IPU_V_BASE + REG_CSC_C1_COEF), ((c1_coeff) & CX_COEF_MSK)<<CX_COEF_SFT); \

+})

+#define set_csc_c2(c2_coeff) \

+({ write_reg( (IPU_V_BASE + REG_CSC_C2_COEF), ((c2_coeff) & CX_COEF_MSK)<<CX_COEF_SFT); \

+})

+#define set_csc_c3(c3_coeff) \

+({ write_reg( (IPU_V_BASE + REG_CSC_C3_COEF), ((c3_coeff) & CX_COEF_MSK)<<CX_COEF_SFT); \

+})

+#define set_csc_c4(c4_coeff) \

+({ write_reg( (IPU_V_BASE + REG_CSC_C4_COEF), ((c4_coeff) & CX_COEF_MSK)<<CX_COEF_SFT); \

+})

+#define set_hrsz_lut_coef(coef, in_n, out_n) \

+({ write_reg( (IPU_V_BASE + HRSZ_LUT_BASE ), ((coef) & W_COEF_MSK)<<W_COEF_SFT \

+| ((in_n) & IN_N_MSK)<<IN_N_SFT | ((out_n) & OUT_N_MSK)<<OUT_N_SFT); \

+})

+#define set_vrsz_lut_coef(coef, in_n, out_n) \

+({ write_reg( (IPU_V_BASE + VRSZ_LUT_BASE), ((coef) & W_COEF_MSK)<<W_COEF_SFT \

+| ((in_n) & IN_N_MSK)<<IN_N_SFT | ((out_n) & OUT_N_MSK)<<OUT_N_SFT); \

+})

+

+#define set_primary_ctrl(vrsz_en, hrsz_en,csc_en, irq_en) \

+({ write_reg( (IPU_V_BASE + REG_CTRL), ((irq_en) & FM_IRQ_EN_MSK)<<FM_IRQ_EN_SFT \

+| ((vrsz_en) & VRSZ_EN_MSK)<<VRSZ_EN_SFT \

+| ((hrsz_en) & HRSZ_EN_MSK)<<HRSZ_EN_SFT \

+| ((csc_en) & CSC_EN_MSK)<<CSC_EN_SFT \

+| (read_reg(IPU_V_BASE, REG_CTRL)) \

+& ~(CSC_EN_MSK<<CSC_EN_SFT | FM_IRQ_EN_MSK<<FM_IRQ_EN_SFT | VRSZ_EN_MSK<<VRSZ_EN_SFT | HRSZ_EN_MSK<<HRSZ_EN_SFT ) ); \

+})

+

+#define set_source_ctrl(pkg_sel, spage_sel) \

+({ write_reg( (IPU_V_BASE + REG_CTRL), ((pkg_sel) & PKG_SEL_MSK  )<< PKG_SEL_SFT \

+| ((spage_sel) & SPAGE_MAP_MSK )<< SPAGE_MAP_SFT \

+| (read_reg(IPU_V_BASE, REG_CTRL)) \

+& ~(SPAGE_MAP_MSK << SPAGE_MAP_SFT | PKG_SEL_MSK << PKG_SEL_SFT ) ) ; \

+})

+

+#define set_out_ctrl(lcdc_sel, dpage_sel, disp_sel) \

+({ write_reg( (IPU_V_BASE + REG_CTRL), ((lcdc_sel) & LCDC_SEL_MSK  )<< LCDC_SEL_SFT \

+| ((dpage_sel) & DPAGE_SEL_MSK )<< DPAGE_SEL_SFT \

+| ((disp_sel) & DISP_SEL_MSK )<< DISP_SEL_SFT \

+| (read_reg(IPU_V_BASE, REG_CTRL)) \

+& ~(LCDC_SEL_MSK<< LCDC_SEL_SFT | DPAGE_SEL_MSK << DPAGE_SEL_SFT | DISP_SEL_MSK << DISP_SEL_SFT ) ); \

+})

+

+#define set_scale_ctrl(v_scal, h_scal) \

+({ write_reg( (IPU_V_BASE + REG_CTRL), ((v_scal) & V_SCALE_MSK)<<V_SCALE_SFT \

+| ((h_scal) & H_SCALE_MSK)<<H_SCALE_SFT \

+| (read_reg(IPU_V_BASE, REG_CTRL)) & ~(V_SCALE_MSK<<V_SCALE_SFT | H_SCALE_MSK<<H_SCALE_SFT ) ); \

+})

+

+

+#define set_csc_ofset_para(chrom_oft, luma_oft) \

+({ write_reg( (IPU_V_BASE + REG_CSC_OFSET_PARA ), ((chrom_oft) & CHROM_OF_MSK ) << CHROM_OF_SFT \

+| ((luma_oft) & LUMA_OF_MSK ) << LUMA_OF_SFT ) ; \

+})

+

+#define sw_reset_ipu() \

+({ write_reg( (IPU_V_BASE + REG_CTRL), (read_reg(IPU_V_BASE, REG_CTRL)) \

+| IPU_RST_MSK<<IPU_RST_SFT); \

+})

+#define enable_ipu() \

+({ write_reg( (IPU_V_BASE + REG_CTRL), (read_reg(IPU_V_BASE, REG_CTRL)) | 0x1); \

+})

+#define disable_ipu() \

+({ write_reg( (IPU_V_BASE + REG_CTRL), (read_reg(IPU_V_BASE, REG_CTRL)) & ~0x1); \

+})

+#define run_ipu() \

+({ write_reg( (IPU_V_BASE + REG_CTRL), (read_reg(IPU_V_BASE, REG_CTRL)) | 0x2); \

+})

+#define stop_ipu() \

+({ write_reg( (IPU_V_BASE + REG_CTRL), (read_reg(IPU_V_BASE, REG_CTRL)) & ~0x2); \

+})

+

+#define polling_end_flag() \

+({ (read_reg(IPU_V_BASE, REG_STATUS)) & 0x01; \

+})

+

+#define start_vlut_coef_write() \

+({ write_reg( (IPU_V_BASE + VRSZ_LUT_BASE), ( 0x1<<12 ) ); \

+})

+

+#define start_hlut_coef_write() \

+({ write_reg( (IPU_V_BASE + HRSZ_LUT_BASE), ( 0x01<<12 ) ); \

+})

+

+#define clear_end_flag() \

+({ write_reg( (IPU_V_BASE + REG_STATUS), 0); \

+})

+#endif /* #if 0 */

+

+

+#endif /* __MIPS_ASSEMBLER */

+

+#endif /* __JZ4760BIPU_H__ */

+

diff --git a/arch/mips/include/asm/mach-jz4760b/jz4760blcdc.h b/arch/mips/include/asm/mach-jz4760b/jz4760blcdc.h
new file mode 100644
index 00000000000..f46b1e1d7f4
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4760b/jz4760blcdc.h
@@ -0,0 +1,1280 @@
+/*

+ * linux/include/asm-mips/mach-jz4760b/jz4760blcdc.h

+ *

+ * JZ4760B LCDC register definition.

+ *

+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

+ */

+

+#ifndef __JZ4760BLCDC_H__

+#define __JZ4760BLCDC_H__

+

+

+#define	LCD_BASE	0xB3050000

+#define	SLCD_BASE	0xB3050000

+

+

+/*************************************************************************

+ * SLCD (Smart LCD Controller)

+ *************************************************************************/

+

+#define SLCD_CFG	(SLCD_BASE + 0xA0)  /* SLCD Configure Register */

+#define SLCD_CTRL	(SLCD_BASE + 0xA4)  /* SLCD Control Register */

+#define SLCD_STATE	(SLCD_BASE + 0xA8)  /* SLCD Status Register */

+#define SLCD_DATA	(SLCD_BASE + 0xAC)  /* SLCD Data Register */

+

+#define REG_SLCD_CFG	REG32(SLCD_CFG)

+#define REG_SLCD_CTRL	REG8(SLCD_CTRL)

+#define REG_SLCD_STATE	REG8(SLCD_STATE)

+#define REG_SLCD_DATA	REG32(SLCD_DATA)

+

+/* SLCD Configure Register */

+#define SLCD_CFG_DWIDTH_BIT	10

+#define SLCD_CFG_DWIDTH_MASK	(0x7 << SLCD_CFG_DWIDTH_BIT)

+  #define SLCD_CFG_DWIDTH_18BIT	(0 << SLCD_CFG_DWIDTH_BIT)

+  #define SLCD_CFG_DWIDTH_16BIT	(1 << SLCD_CFG_DWIDTH_BIT)

+  #define SLCD_CFG_DWIDTH_8BIT_x3	(2 << SLCD_CFG_DWIDTH_BIT)

+  #define SLCD_CFG_DWIDTH_8BIT_x2	(3 << SLCD_CFG_DWIDTH_BIT)

+  #define SLCD_CFG_DWIDTH_8BIT_x1	(4 << SLCD_CFG_DWIDTH_BIT)

+  #define SLCD_CFG_DWIDTH_24BIT	(5 << SLCD_CFG_DWIDTH_BIT)

+  #define SLCD_CFG_DWIDTH_9BIT_x2	(7 << SLCD_CFG_DWIDTH_BIT)

+#define SLCD_CFG_CWIDTH_BIT	(8)

+#define SLCD_CFG_CWIDTH_MASK	(0x7 << SLCD_CFG_CWIDTH_BIT)

+#define SLCD_CFG_CWIDTH_16BIT	(0 << SLCD_CFG_CWIDTH_BIT)

+#define SLCD_CFG_CWIDTH_8BIT	(1 << SLCD_CFG_CWIDTH_BIT)

+#define SLCD_CFG_CWIDTH_18BIT	(2 << SLCD_CFG_CWIDTH_BIT)

+#define SLCD_CFG_CWIDTH_24BIT	(3 << SLCD_CFG_CWIDTH_BIT)

+#define SLCD_CFG_CS_ACTIVE_LOW	(0 << 4)

+#define SLCD_CFG_CS_ACTIVE_HIGH	(1 << 4)

+#define SLCD_CFG_RS_CMD_LOW	(0 << 3)

+#define SLCD_CFG_RS_CMD_HIGH	(1 << 3)

+#define SLCD_CFG_CLK_ACTIVE_FALLING	(0 << 1)

+#define SLCD_CFG_CLK_ACTIVE_RISING	(1 << 1)

+#define SLCD_CFG_TYPE_PARALLEL	(0 << 0)

+#define SLCD_CFG_TYPE_SERIAL	(1 << 0)

+

+/* SLCD Control Register */

+#define SLCD_CTRL_DMA_MODE	(1 << 2)

+#define SLCD_CTRL_DMA_START	(1 << 1)

+#define SLCD_CTRL_DMA_EN	(1 << 0)

+

+/* SLCD Status Register */

+#define SLCD_STATE_BUSY		(1 << 0)

+

+/* SLCD Data Register */

+#define SLCD_DATA_RS_DATA	(0 << 31)

+#define SLCD_DATA_RS_COMMAND	(1 << 31)

+

+/*************************************************************************

+ * LCD (LCD Controller)

+ *************************************************************************/

+#define LCD_CFG		(LCD_BASE + 0x00) /* LCD Configure Register */

+#define LCD_CTRL	(LCD_BASE + 0x30) /* LCD Control Register */

+#define LCD_STATE	(LCD_BASE + 0x34) /* LCD Status Register */

+

+#define LCD_OSDC	(LCD_BASE + 0x100) /* LCD OSD Configure Register */

+#define LCD_OSDCTRL	(LCD_BASE + 0x104) /* LCD OSD Control Register */

+#define LCD_OSDS	(LCD_BASE + 0x108) /* LCD OSD Status Register */

+#define LCD_BGC		(LCD_BASE + 0x10C) /* LCD Background Color Register */

+#define LCD_KEY0	(LCD_BASE + 0x110) /* LCD Foreground Color Key Register 0 */

+#define LCD_KEY1	(LCD_BASE + 0x114) /* LCD Foreground Color Key Register 1 */

+#define LCD_ALPHA	(LCD_BASE + 0x118) /* LCD ALPHA Register */

+#define LCD_IPUR	(LCD_BASE + 0x11C) /* LCD IPU Restart Register */

+

+#define LCD_VAT		(LCD_BASE + 0x0c) /* Virtual Area Setting Register */

+#define LCD_DAH		(LCD_BASE + 0x10) /* Display Area Horizontal Start/End Point */

+#define LCD_DAV		(LCD_BASE + 0x14) /* Display Area Vertical Start/End Point */

+#define LCD_XYP0	(LCD_BASE + 0x120) /* Foreground 0 XY Position Register */

+#define LCD_XYP1	(LCD_BASE + 0x124) /* Foreground 1 XY Position Register */

+#define LCD_XYP0_PART2	(LCD_BASE + 0x1F0) /* Foreground 0 PART2 XY Position Register */

+#define LCD_SIZE0	(LCD_BASE + 0x128) /* Foreground 0 Size Register */

+#define LCD_SIZE1	(LCD_BASE + 0x12C) /* Foreground 1 Size Register */

+#define LCD_SIZE0_PART2	(LCD_BASE + 0x1F4) /*Foreground 0 PART2 Size Register */

+#define LCD_RGBC	(LCD_BASE + 0x90) /* RGB Controll Register */

+

+#define LCD_VSYNC	(LCD_BASE + 0x04) /* Vertical Synchronize Register */

+#define LCD_HSYNC	(LCD_BASE + 0x08) /* Horizontal Synchronize Register */

+#define LCD_PS		(LCD_BASE + 0x18) /* PS Signal Setting */

+#define LCD_CLS		(LCD_BASE + 0x1c) /* CLS Signal Setting */

+#define LCD_SPL		(LCD_BASE + 0x20) /* SPL Signal Setting */

+#define LCD_REV		(LCD_BASE + 0x24) /* REV Signal Setting */

+#define LCD_IID		(LCD_BASE + 0x38) /* Interrupt ID Register */

+#define LCD_DA0		(LCD_BASE + 0x40) /* Descriptor Address Register 0 */

+#define LCD_SA0		(LCD_BASE + 0x44) /* Source Address Register 0 */

+#define LCD_FID0	(LCD_BASE + 0x48) /* Frame ID Register 0 */

+#define LCD_CMD0	(LCD_BASE + 0x4c) /* DMA Command Register 0 */

+#define LCD_OFFS0	(LCD_BASE + 0x60) /* DMA Offsize Register 0 */

+#define LCD_PW0		(LCD_BASE + 0x64) /* DMA Page Width Register 0 */

+#define LCD_CNUM0	(LCD_BASE + 0x68) /* DMA Command Counter Register 0 */

+#define LCD_DESSIZE0	(LCD_BASE + 0x6C) /* Foreground Size in Descriptor 0 Register*/

+

+#define LCD_DA0_PART2	(LCD_BASE + 0x1C0) /* Descriptor Address Register PART2 */

+#define LCD_SA0_PART2	(LCD_BASE + 0x1C4) /* Source Address Register PART2 */

+#define LCD_FID0_PART2	(LCD_BASE + 0x1C8) /* Frame ID Register PART2 */

+#define LCD_CMD0_PART2	(LCD_BASE + 0x1CC) /* DMA Command Register PART2 */

+#define LCD_OFFS0_PART2	(LCD_BASE + 0x1E0) /* DMA Offsize Register PART2 */

+#define LCD_PW0_PART2	(LCD_BASE + 0x1E4) /* DMA Command Counter Register PART2 */

+#define LCD_CNUM0_PART2	(LCD_BASE + 0x1E8) /* Foreground Size in Descriptor PART2 Register */

+#define LCD_DESSIZE0_PART2	(LCD_BASE + 0x1EC) /*  */

+#define LCD_PCFG	(LCD_BASE + 0x2C0)

+

+#define LCD_DA1		(LCD_BASE + 0x50) /* Descriptor Address Register 1 */

+#define LCD_SA1		(LCD_BASE + 0x54) /* Source Address Register 1 */

+#define LCD_FID1	(LCD_BASE + 0x58) /* Frame ID Register 1 */

+#define LCD_CMD1	(LCD_BASE + 0x5c) /* DMA Command Register 1 */

+#define LCD_OFFS1	(LCD_BASE + 0x70) /* DMA Offsize Register 1 */

+#define LCD_PW1		(LCD_BASE + 0x74) /* DMA Page Width Register 1 */

+#define LCD_CNUM1	(LCD_BASE + 0x78) /* DMA Command Counter Register 1 */

+#define LCD_DESSIZE1	(LCD_BASE + 0x7C) /* Foreground Size in Descriptor 1 Register*/

+

+#define REG_LCD_CFG	REG32(LCD_CFG)

+#define REG_LCD_CTRL	REG32(LCD_CTRL)

+#define REG_LCD_STATE	REG32(LCD_STATE)

+

+#define REG_LCD_OSDC	REG16(LCD_OSDC)

+#define REG_LCD_OSDCTRL	REG16(LCD_OSDCTRL)

+#define REG_LCD_OSDS	REG16(LCD_OSDS)

+#define REG_LCD_BGC	REG32(LCD_BGC)

+#define REG_LCD_KEY0	REG32(LCD_KEY0)

+#define REG_LCD_KEY1	REG32(LCD_KEY1)

+#define REG_LCD_ALPHA	REG8(LCD_ALPHA)

+#define REG_LCD_IPUR	REG32(LCD_IPUR)

+

+#define REG_LCD_VAT	REG32(LCD_VAT)

+#define REG_LCD_DAH	REG32(LCD_DAH)

+#define REG_LCD_DAV	REG32(LCD_DAV)

+

+#define REG_LCD_XYP0		REG32(LCD_XYP0)

+#define REG_LCD_XYP0_PART2	REG32(LCD_XYP0_PART2)

+#define REG_LCD_XYP1		REG32(LCD_XYP1)

+#define REG_LCD_SIZE0		REG32(LCD_SIZE0)

+#define REG_LCD_SIZE0_PART2	REG32(LCD_SIZE0_PART2)

+#define REG_LCD_SIZE1	REG32(LCD_SIZE1)

+

+#define REG_LCD_RGBC	REG16(LCD_RGBC)

+

+#define REG_LCD_VSYNC	REG32(LCD_VSYNC)

+#define REG_LCD_HSYNC	REG32(LCD_HSYNC)

+#define REG_LCD_PS	REG32(LCD_PS)

+#define REG_LCD_CLS	REG32(LCD_CLS)

+#define REG_LCD_SPL	REG32(LCD_SPL)

+#define REG_LCD_REV	REG32(LCD_REV)

+#define REG_LCD_IID	REG32(LCD_IID)

+#define REG_LCD_DA0	REG32(LCD_DA0)

+#define REG_LCD_SA0	REG32(LCD_SA0)

+#define REG_LCD_FID0	REG32(LCD_FID0)

+#define REG_LCD_CMD0	REG32(LCD_CMD0)

+

+#define REG_LCD_OFFS0	REG32(LCD_OFFS0)

+#define REG_LCD_PW0	REG32(LCD_PW0)

+#define REG_LCD_CNUM0	REG32(LCD_CNUM0)

+#define REG_LCD_DESSIZE0	REG32(LCD_DESSIZE0)

+

+#define REG_LCD_DA0_PART2	REG32(LCD_DA0_PART2)

+#define REG_LCD_SA0_PART2	REG32(LCD_SA0_PART2)

+#define REG_LCD_FID0_PART2	REG32(LCD_FID0_PART2)

+#define REG_LCD_CMD0_PART2	REG32(LCD_CMD0_PART2)

+#define REG_LCD_OFFS0_PART2	REG32(LCD_OFFS0_PART2)

+#define REG_LCD_PW0_PART2	REG32(LCD_PW0_PART2)

+#define REG_LCD_CNUM0_PART2	REG32(LCD_CNUM0_PART2)

+#define REG_LCD_DESSIZE0_PART2	REG32(LCD_DESSIZE0_PART2)

+#define REG_LCD_PCFG		REG32(LCD_PCFG)

+

+#define REG_LCD_DA1	REG32(LCD_DA1)

+#define REG_LCD_SA1	REG32(LCD_SA1)

+#define REG_LCD_FID1	REG32(LCD_FID1)

+#define REG_LCD_CMD1	REG32(LCD_CMD1)

+#define REG_LCD_OFFS1	REG32(LCD_OFFS1)

+#define REG_LCD_PW1	REG32(LCD_PW1)

+#define REG_LCD_CNUM1	REG32(LCD_CNUM1)

+#define REG_LCD_DESSIZE1	REG32(LCD_DESSIZE1)

+

+/* LCD Configure Register */

+#define LCD_CFG_LCDPIN_BIT	31  /* LCD pins selection */

+#define LCD_CFG_LCDPIN_MASK	(0x1 << LCD_CFG_LCDPIN_BIT)

+  #define LCD_CFG_LCDPIN_LCD	(0x0 << LCD_CFG_LCDPIN_BIT)

+  #define LCD_CFG_LCDPIN_SLCD	(0x1 << LCD_CFG_LCDPIN_BIT)

+#define LCD_CFG_TVEPEH		(1 << 30) /* TVE PAL enable extra halfline signal */

+#define LCD_CFG_FUHOLD		(1 << 29) /* hold pixel clock when outFIFO underrun */

+#define LCD_CFG_NEWDES		(1 << 28) /* use new descripter. old: 4words, new:8words */

+#define LCD_CFG_PALBP		(1 << 27) /* bypass data format and alpha blending */

+#define LCD_CFG_TVEN		(1 << 26) /* indicate the terminal is lcd or tv */

+#define LCD_CFG_RECOVER		(1 << 25) /* Auto recover when output fifo underrun */

+#define LCD_CFG_DITHER		(1 << 24) /* Dither function */

+#define LCD_CFG_PSM		(1 << 23) /* PS signal mode */

+#define LCD_CFG_CLSM		(1 << 22) /* CLS signal mode */

+#define LCD_CFG_SPLM		(1 << 21) /* SPL signal mode */

+#define LCD_CFG_REVM		(1 << 20) /* REV signal mode */

+#define LCD_CFG_HSYNM		(1 << 19) /* HSYNC signal mode */

+#define LCD_CFG_PCLKM		(1 << 18) /* PCLK signal mode */

+#define LCD_CFG_INVDAT		(1 << 17) /* Inverse output data */

+#define LCD_CFG_SYNDIR_IN	(1 << 16) /* VSYNC&HSYNC direction */

+#define LCD_CFG_PSP		(1 << 15) /* PS pin reset state */

+#define LCD_CFG_CLSP		(1 << 14) /* CLS pin reset state */

+#define LCD_CFG_SPLP		(1 << 13) /* SPL pin reset state */

+#define LCD_CFG_REVP		(1 << 12) /* REV pin reset state */

+#define LCD_CFG_HSP		(1 << 11) /* HSYNC polarity:0-active high,1-active low */

+#define LCD_CFG_PCP		(1 << 10) /* PCLK polarity:0-rising,1-falling */

+#define LCD_CFG_DEP		(1 << 9)  /* DE polarity:0-active high,1-active low */

+#define LCD_CFG_VSP		(1 << 8)  /* VSYNC polarity:0-rising,1-falling */

+#define LCD_CFG_MODE_TFT_18BIT 	(1 << 7)  /* 18bit TFT */

+#define LCD_CFG_MODE_TFT_16BIT 	(0 << 7)  /* 16bit TFT */

+#define LCD_CFG_MODE_TFT_24BIT 	(1 << 6)  /* 24bit TFT */

+#define LCD_CFG_PDW_BIT		4  /* STN pins utilization */

+#define LCD_CFG_PDW_MASK	(0x3 << LCD_DEV_PDW_BIT)

+#define LCD_CFG_PDW_1		(0 << LCD_CFG_PDW_BIT) /* LCD_D[0] */

+  #define LCD_CFG_PDW_2		(1 << LCD_CFG_PDW_BIT) /* LCD_D[0:1] */

+  #define LCD_CFG_PDW_4		(2 << LCD_CFG_PDW_BIT) /* LCD_D[0:3]/LCD_D[8:11] */

+  #define LCD_CFG_PDW_8		(3 << LCD_CFG_PDW_BIT) /* LCD_D[0:7]/LCD_D[8:15] */

+#define LCD_CFG_MODE_BIT	0  /* Display Device Mode Select */

+#define LCD_CFG_MODE_MASK	(0x0f << LCD_CFG_MODE_BIT)

+  #define LCD_CFG_MODE_GENERIC_TFT	(0 << LCD_CFG_MODE_BIT) /* 16,18 bit TFT */

+  #define LCD_CFG_MODE_SPECIAL_TFT_1	(1 << LCD_CFG_MODE_BIT)

+  #define LCD_CFG_MODE_SPECIAL_TFT_2	(2 << LCD_CFG_MODE_BIT)

+  #define LCD_CFG_MODE_SPECIAL_TFT_3	(3 << LCD_CFG_MODE_BIT)

+  #define LCD_CFG_MODE_NONINTER_CCIR656	(4 << LCD_CFG_MODE_BIT)

+  #define LCD_CFG_MODE_INTER_CCIR656	(6 << LCD_CFG_MODE_BIT)

+  #define LCD_CFG_MODE_SINGLE_CSTN	(8 << LCD_CFG_MODE_BIT)

+  #define LCD_CFG_MODE_SINGLE_MSTN	(9 << LCD_CFG_MODE_BIT)

+  #define LCD_CFG_MODE_DUAL_CSTN	(10 << LCD_CFG_MODE_BIT)

+  #define LCD_CFG_MODE_DUAL_MSTN	(11 << LCD_CFG_MODE_BIT)

+  #define LCD_CFG_MODE_SERIAL_TFT	(12 << LCD_CFG_MODE_BIT)

+  #define LCD_CFG_MODE_LCM  		(13 << LCD_CFG_MODE_BIT)

+  #define LCD_CFG_MODE_SLCD  		LCD_CFG_MODE_LCM

+

+/* LCD Control Register */

+#define LCD_CTRL_PINMD		(1 << 30) /* This register set Pin distribution in 16-bit parallel mode

+					    0: 16-bit data correspond with LCD_D[15:0]

+					    1: 16-bit data correspond with LCD_D[17:10], LCD_D[8:1] */

+#define LCD_CTRL_BST_BIT	28  /* Burst Length Selection */

+#define LCD_CTRL_BST_MASK	(0x03 << LCD_CTRL_BST_BIT)

+  #define LCD_CTRL_BST_4	(0 << LCD_CTRL_BST_BIT) /* 4-word */

+  #define LCD_CTRL_BST_8	(1 << LCD_CTRL_BST_BIT) /* 8-word */

+  #define LCD_CTRL_BST_16	(2 << LCD_CTRL_BST_BIT) /* 16-word */

+  #define LCD_CTRL_BST_32	(3 << LCD_CTRL_BST_BIT) /* 32-word */

+#define LCD_CTRL_RGB565		(0 << 27) /* RGB565 mode(foreground 0 in OSD mode) */

+#define LCD_CTRL_RGB555		(1 << 27) /* RGB555 mode(foreground 0 in OSD mode) */

+#define LCD_CTRL_OFUP		(1 << 26) /* Output FIFO underrun protection enable */

+#define LCD_CTRL_FRC_BIT	24  /* STN FRC Algorithm Selection */

+#define LCD_CTRL_FRC_MASK	(0x03 << LCD_CTRL_FRC_BIT)

+  #define LCD_CTRL_FRC_16	(0 << LCD_CTRL_FRC_BIT) /* 16 grayscale */

+  #define LCD_CTRL_FRC_4	(1 << LCD_CTRL_FRC_BIT) /* 4 grayscale */

+  #define LCD_CTRL_FRC_2	(2 << LCD_CTRL_FRC_BIT) /* 2 grayscale */

+#define LCD_CTRL_PDD_BIT	16  /* Load Palette Delay Counter */

+#define LCD_CTRL_PDD_MASK	(0xff << LCD_CTRL_PDD_BIT)

+///#define LCD_CTRL_VGA		(1 << 15) /* VGA interface enable */

+//#define LCD_CTRL_DACTE		(1 << 14) /* DAC loop back test */

+#define LCD_CTRL_EOFM		(1 << 13) /* EOF interrupt mask */

+#define LCD_CTRL_SOFM		(1 << 12) /* SOF interrupt mask */

+#define LCD_CTRL_OFUM		(1 << 11) /* Output FIFO underrun interrupt mask */

+#define LCD_CTRL_IFUM0		(1 << 10) /* Input FIFO 0 underrun interrupt mask */

+#define LCD_CTRL_IFUM1		(1 << 9)  /* Input FIFO 1 underrun interrupt mask */

+#define LCD_CTRL_LDDM		(1 << 8)  /* LCD disable done interrupt mask */

+#define LCD_CTRL_QDM		(1 << 7)  /* LCD quick disable done interrupt mask */

+#define LCD_CTRL_BEDN		(1 << 6)  /* Endian selection */

+#define LCD_CTRL_PEDN		(1 << 5)  /* Endian in byte:0-msb first, 1-lsb first */

+#define LCD_CTRL_DIS		(1 << 4)  /* Disable indicate bit */

+#define LCD_CTRL_ENA		(1 << 3)  /* LCD enable bit */

+#define LCD_CTRL_BPP_BIT	0  /* Bits Per Pixel */

+#define LCD_CTRL_BPP_MASK	(0x07 << LCD_CTRL_BPP_BIT)

+  #define LCD_CTRL_BPP_1	(0 << LCD_CTRL_BPP_BIT) /* 1 bpp */

+  #define LCD_CTRL_BPP_2	(1 << LCD_CTRL_BPP_BIT) /* 2 bpp */

+  #define LCD_CTRL_BPP_4	(2 << LCD_CTRL_BPP_BIT) /* 4 bpp */

+  #define LCD_CTRL_BPP_8	(3 << LCD_CTRL_BPP_BIT) /* 8 bpp */

+  #define LCD_CTRL_BPP_16	(4 << LCD_CTRL_BPP_BIT) /* 15/16 bpp */

+  #define LCD_CTRL_BPP_18_24	(5 << LCD_CTRL_BPP_BIT) /* 18/24/32 bpp */

+  #define LCD_CTRL_BPP_CMPS_24	(6 << LCD_CTRL_BPP_BIT) /* 24 compress bpp */

+  #define LCD_CTRL_BPP_30	(7 << LCD_CTRL_BPP_BIT) /* 30 bpp */

+

+/* LCD Status Register */

+

+#define EPD_STATE_FEND		(1<<22)

+#define EPD_STATE_PWRUP		(1<<20)

+#define EPD_STATE_PWRDN		(1<<19)

+

+#define LCD_STATE_QD		(1 << 7) /* Quick Disable Done */

+#define LCD_STATE_EOF		(1 << 5) /* EOF Flag */

+#define LCD_STATE_SOF		(1 << 4) /* SOF Flag */

+#define LCD_STATE_OFU		(1 << 3) /* Output FIFO Underrun */

+#define LCD_STATE_IFU0		(1 << 2) /* Input FIFO 0 Underrun */

+#define LCD_STATE_IFU1		(1 << 1) /* Input FIFO 1 Underrun */

+#define LCD_STATE_LDD		(1 << 0) /* LCD Disabled */

+

+/* OSD Configure Register */

+#define LCD_OSDC_SOFM1		(1 << 15) /* Start of frame interrupt mask for foreground 1 */

+#define LCD_OSDC_EOFM1		(1 << 14) /* End of frame interrupt mask for foreground 1 */

+#define LCD_OSDC_SOFM0		(1 << 11) /* Start of frame interrupt mask for foreground 0 */

+#define LCD_OSDC_EOFM0		(1 << 10) /* End of frame interrupt mask for foreground 0 */

+

+////////////////////////////////////////////////////////////

+#define LCD_OSDC_ENDM		(1 << 9) /* End of frame interrupt mask for panel. */

+#define LCD_OSDC_F0DIVMD	(1 << 8) /* Divide Foreground 0 into 2 parts.

+					  * 0: Foreground 0 only has one part. */

+#define LCD_OSDC_F0P1EN		(1 << 7) /* 1: Foreground 0 PART1 is enabled.

+					  * 0: Foreground 0 PART1 is disabled. */

+#define LCD_OSDC_F0P2MD		(1 << 6) /* 1: PART 1&2 same level and same heighth

+					  * 0: PART 1&2 have no same line */

+#define LCD_OSDC_F0P2EN		(1 << 5) /* 1: Foreground 0 PART2 is enabled.

+					  * 0: Foreground 0 PART2 is disabled.*/

+////////////////////////////////////////////////////////////

+

+#define LCD_OSDC_F1EN		(1 << 4) /* enable foreground 1 */

+#define LCD_OSDC_F0EN		(1 << 3) /* enable foreground 0 */

+#define LCD_OSDC_ALPHAEN		(1 << 2) /* enable alpha blending */

+#define LCD_OSDC_ALPHAMD		(1 << 1) /* alpha blending mode */

+#define LCD_OSDC_OSDEN		(1 << 0) /* OSD mode enable */

+

+/* OSD Controll Register */

+#define LCD_OSDCTRL_IPU		(1 << 15) /* input data from IPU */

+#define LCD_OSDCTRL_RGB565	(0 << 4) /* foreground 1, 16bpp, 0-RGB565, 1-RGB555 */

+#define LCD_OSDCTRL_RGB555	(1 << 4) /* foreground 1, 16bpp, 0-RGB565, 1-RGB555 */

+#define LCD_OSDCTRL_CHANGES	(1 << 3) /* Change size flag */

+#define LCD_OSDCTRL_OSDBPP_BIT	0 	 /* Bits Per Pixel of OSD Channel 1 */

+#define LCD_OSDCTRL_OSDBPP_MASK	(0x7<<LCD_OSDCTRL_OSDBPP_BIT) 	 /* Bits Per Pixel of OSD Channel 1's MASK */

+  #define LCD_OSDCTRL_OSDBPP_2     (1 << LCD_OSDCTRL_OSDBPP_BIT)

+  #define LCD_OSDCTRL_OSDBPP_4     (2 << LCD_OSDCTRL_OSDBPP_BIT)

+  #define LCD_OSDCTRL_OSDBPP_16	(4 << LCD_OSDCTRL_OSDBPP_BIT) /* RGB 15,16 bit*/

+  #define LCD_OSDCTRL_OSDBPP_15_16	(4 << LCD_OSDCTRL_OSDBPP_BIT) /* RGB 15,16 bit*/

+  #define LCD_OSDCTRL_OSDBPP_18_24	(5 << LCD_OSDCTRL_OSDBPP_BIT) /* RGB 18,24 bit*/

+  #define LCD_OSDCTRL_OSDBPP_CMPS_24	(6 << LCD_OSDCTRL_OSDBPP_BIT) /* RGB compress 24 bit*/

+  #define LCD_OSDCTRL_OSDBPP_30		(7 << LCD_OSDCTRL_OSDBPP_BIT) /* RGB 30 bit*/

+

+/* OSD State Register */

+#define LCD_OSDS_SOF1		(1 << 15) /* Start of frame flag for foreground 1 */

+#define LCD_OSDS_EOF1		(1 << 14) /* End of frame flag for foreground 1 */

+#define LCD_OSDS_SOF0		(1 << 11) /* Start of frame flag for foreground 0 */

+#define LCD_OSDS_EOF0		(1 << 10) /* End of frame flag for foreground 0 */

+#define LCD_OSDS_READY		(1 << 0)  /* Read for accept the change */

+

+/* Background Color Register */

+#define LCD_BGC_RED_OFFSET	(1 << 16)  /* Red color offset */

+#define LCD_BGC_RED_MASK	(0xFF<<LCD_BGC_RED_OFFSET)

+#define LCD_BGC_GREEN_OFFSET	(1 << 8)   /* Green color offset */

+#define LCD_BGC_GREEN_MASK	(0xFF<<LCD_BGC_GREEN_OFFSET)

+#define LCD_BGC_BLUE_OFFSET	(1 << 0)   /* Blue color offset */

+#define LCD_BGC_BLUE_MASK	(0xFF<<LCD_BGC_BLUE_OFFSET)

+

+/* Foreground Color Key Register 0,1(foreground 0, foreground 1) */

+#define LCD_KEY_KEYEN		(1 << 31)   /* enable color key */

+#define LCD_KEY_KEYMD		(1 << 30)   /* color key mode */

+#define LCD_KEY_RED_OFFSET	16  /* Red color offset */

+#define LCD_KEY_RED_MASK	(0xFF<<LCD_KEY_RED_OFFSET)

+#define LCD_KEY_GREEN_OFFSET	8   /* Green color offset */

+#define LCD_KEY_GREEN_MASK	(0xFF<<LCD_KEY_GREEN_OFFSET)

+#define LCD_KEY_BLUE_OFFSET	0   /* Blue color offset */

+#define LCD_KEY_BLUE_MASK	(0xFF<<LCD_KEY_BLUE_OFFSET)

+#define LCD_KEY_MASK		(LCD_KEY_RED_MASK|LCD_KEY_GREEN_MASK|LCD_KEY_BLUE_MASK)

+

+/* IPU Restart Register */

+#define LCD_IPUR_IPUREN		(1 << 31)   /* IPU restart function enable*/

+#define LCD_IPUR_IPURMASK	(0xFFFFFF)   /* IPU restart value mask*/

+

+/* RGB Control Register */

+#define LCD_RGBC_RGBDM		(1 << 15)   /* enable RGB Dummy data */

+#define LCD_RGBC_DMM		(1 << 14)   /* RGB Dummy mode */

+#define LCD_RGBC_YCC		(1 << 8)    /* RGB to YCC */

+#define LCD_RGBC_ODDRGB_BIT	4	/* odd line serial RGB data arrangement */

+#define LCD_RGBC_ODDRGB_MASK	(0x7<<LCD_RGBC_ODDRGB_BIT)

+  #define LCD_RGBC_ODD_RGB	0

+  #define LCD_RGBC_ODD_RBG	1

+  #define LCD_RGBC_ODD_GRB	2

+  #define LCD_RGBC_ODD_GBR	3

+  #define LCD_RGBC_ODD_BRG	4

+  #define LCD_RGBC_ODD_BGR	5

+#define LCD_RGBC_EVENRGB_BIT	0	/* even line serial RGB data arrangement */

+#define LCD_RGBC_EVENRGB_MASK	(0x7<<LCD_RGBC_EVENRGB_BIT)

+  #define LCD_RGBC_EVEN_RGB	0

+  #define LCD_RGBC_EVEN_RBG	1

+  #define LCD_RGBC_EVEN_GRB	2

+  #define LCD_RGBC_EVEN_GBR	3

+  #define LCD_RGBC_EVEN_BRG	4

+  #define LCD_RGBC_EVEN_BGR	5

+

+/* Vertical Synchronize Register */

+#define LCD_VSYNC_VPS_BIT	16  /* VSYNC pulse start in line clock, fixed to 0 */

+#define LCD_VSYNC_VPS_MASK	(0xffff << LCD_VSYNC_VPS_BIT)

+#define LCD_VSYNC_VPE_BIT	0   /* VSYNC pulse end in line clock */

+#define LCD_VSYNC_VPE_MASK	(0xffff << LCD_VSYNC_VPS_BIT)

+

+/* Horizontal Synchronize Register */

+#define LCD_HSYNC_HPS_BIT	16  /* HSYNC pulse start position in dot clock */

+#define LCD_HSYNC_HPS_MASK	(0xffff << LCD_HSYNC_HPS_BIT)

+#define LCD_HSYNC_HPE_BIT	0   /* HSYNC pulse end position in dot clock */

+#define LCD_HSYNC_HPE_MASK	(0xffff << LCD_HSYNC_HPE_BIT)

+

+/* Virtual Area Setting Register */

+#define LCD_VAT_HT_BIT		16  /* Horizontal Total size in dot clock */

+#define LCD_VAT_HT_MASK		(0xffff << LCD_VAT_HT_BIT)

+#define LCD_VAT_VT_BIT		0   /* Vertical Total size in dot clock */

+#define LCD_VAT_VT_MASK		(0xffff << LCD_VAT_VT_BIT)

+

+/* Display Area Horizontal Start/End Point Register */

+#define LCD_DAH_HDS_BIT		16  /* Horizontal display area start in dot clock */

+#define LCD_DAH_HDS_MASK	(0xffff << LCD_DAH_HDS_BIT)

+#define LCD_DAH_HDE_BIT		0   /* Horizontal display area end in dot clock */

+#define LCD_DAH_HDE_MASK	(0xffff << LCD_DAH_HDE_BIT)

+

+/* Display Area Vertical Start/End Point Register */

+#define LCD_DAV_VDS_BIT		16  /* Vertical display area start in line clock */

+#define LCD_DAV_VDS_MASK	(0xffff << LCD_DAV_VDS_BIT)

+#define LCD_DAV_VDE_BIT		0   /* Vertical display area end in line clock */

+#define LCD_DAV_VDE_MASK	(0xffff << LCD_DAV_VDE_BIT)

+

+/* Foreground XY Position Register */

+#define LCD_XYP_YPOS_BIT	16  /* Y position bit of foreground 0 or 1 */

+#define LCD_XYP_YPOS_MASK	(0xffff << LCD_XYP_YPOS_BIT)

+#define LCD_XYP_XPOS_BIT	0   /* X position bit of foreground 0 or 1 */

+#define LCD_XYP_XPOS_MASK	(0xffff << LCD_XYP_XPOS_BIT)

+

+/* PS Signal Setting */

+#define LCD_PS_PSS_BIT		16  /* PS signal start position in dot clock */

+#define LCD_PS_PSS_MASK		(0xffff << LCD_PS_PSS_BIT)

+#define LCD_PS_PSE_BIT		0   /* PS signal end position in dot clock */

+#define LCD_PS_PSE_MASK		(0xffff << LCD_PS_PSE_BIT)

+

+/* CLS Signal Setting */

+#define LCD_CLS_CLSS_BIT	16  /* CLS signal start position in dot clock */

+#define LCD_CLS_CLSS_MASK	(0xffff << LCD_CLS_CLSS_BIT)

+#define LCD_CLS_CLSE_BIT	0   /* CLS signal end position in dot clock */

+#define LCD_CLS_CLSE_MASK	(0xffff << LCD_CLS_CLSE_BIT)

+

+/* SPL Signal Setting */

+#define LCD_SPL_SPLS_BIT	16  /* SPL signal start position in dot clock */

+#define LCD_SPL_SPLS_MASK	(0xffff << LCD_SPL_SPLS_BIT)

+#define LCD_SPL_SPLE_BIT	0   /* SPL signal end position in dot clock */

+#define LCD_SPL_SPLE_MASK	(0xffff << LCD_SPL_SPLE_BIT)

+

+/* REV Signal Setting */

+#define LCD_REV_REVS_BIT	16  /* REV signal start position in dot clock */

+#define LCD_REV_REVS_MASK	(0xffff << LCD_REV_REVS_BIT)

+

+/* DMA Command Register */

+#define LCD_CMD_SOFINT		(1 << 31)

+#define LCD_CMD_EOFINT		(1 << 30)

+#define LCD_CMD_CMD		(1 << 29) /* indicate command in slcd mode */

+#define LCD_CMD_PAL		(1 << 28)

+#define LCD_CMD_LEN_BIT		0

+#define LCD_CMD_LEN_MASK	(0xffffff << LCD_CMD_LEN_BIT)

+

+/* DMA Offsize Register 0,1 */

+

+/* DMA Page Width Register 0,1 */

+

+/* DMA Command Counter Register 0,1 */

+

+/* Foreground 0,1 Size Register */

+#define LCD_DESSIZE_HEIGHT_BIT	16  /* height of foreground 1 */

+#define LCD_DESSIZE_HEIGHT_MASK	(0xffff << LCD_DESSIZE_HEIGHT_BIT)

+#define LCD_DESSIZE_WIDTH_BIT	0  /* width of foreground 1 */

+#define LCD_DESSIZE_WIDTH_MASK	(0xffff << LCD_DESSIZE_WIDTH_BIT)

+

+

+/*************************************************************************

+ * EPD

+ *************************************************************************/

+#if defined(CONFIG_SOC_JZ4760B) 

+

+#define EPD_CTRL      (LCD_BASE + 0x200)

+#define EPD_STA       (LCD_BASE + 0x204)

+#define EPD_ISR       (LCD_BASE + 0x208)

+#define EPD_CFG0      (LCD_BASE + 0x20C)

+#define EPD_CFG1      (LCD_BASE + 0x210)

+#define EPD_PPL0      (LCD_BASE + 0x214)

+#define EPD_PPL1      (LCD_BASE + 0x218)

+#define EPD_VAT       (LCD_BASE + 0x21C)

+#define EPD_DAV       (LCD_BASE + 0x220)

+#define EPD_DAH       (LCD_BASE + 0x224)

+#define EPD_VSYNC      (LCD_BASE + 0x228)

+#define EPD_HSYNC      (LCD_BASE + 0x22C)

+#define EPD_GDCLK      (LCD_BASE + 0x230)

+#define EPD_GDOE       (LCD_BASE + 0x234)

+#define EPD_GDSP       (LCD_BASE + 0x238)

+#define EPD_SDOE       (LCD_BASE + 0x23C)

+#define EPD_SDSP       (LCD_BASE + 0x240)

+#define EPD_PMGR0       (LCD_BASE + 0x244)

+#define EPD_PMGR1       (LCD_BASE + 0x248)

+#define EPD_PMGR2       (LCD_BASE + 0x24C)

+#define EPD_PMGR3       (LCD_BASE + 0x250)

+#define EPD_PMGR4       (LCD_BASE + 0x254)

+#define EPD_VCOM0       (LCD_BASE + 0x258)

+#define EPD_VCOM1       (LCD_BASE + 0x25C)

+#define EPD_VCOM2       (LCD_BASE + 0x260)

+#define EPD_VCOM3       (LCD_BASE + 0x264)

+#define EPD_VCOM4       (LCD_BASE + 0x268)

+#define EPD_VCOM5       (LCD_BASE + 0x26C)

+#define EPD_BORDR       (LCD_BASE + 0x270)

+#define EPD_PPL0_POS    (LCD_BASE + 0x280)

+#define EPD_PPL0_SIZE   (LCD_BASE + 0x284)

+#define EPD_PPL1_POS    (LCD_BASE + 0x288)

+#define EPD_PPL1_SIZE   (LCD_BASE + 0x28C)

+#define EPD_PPL2_POS    (LCD_BASE + 0x290)

+#define EPD_PPL2_SIZE   (LCD_BASE + 0x294)

+#define EPD_PPL3_POS    (LCD_BASE + 0x298)

+#define EPD_PPL3_SIZE   (LCD_BASE + 0x29C)

+#define EPD_PPL4_POS    (LCD_BASE + 0x2A0)

+#define EPD_PPL4_SIZE   (LCD_BASE + 0x2A4)

+#define EPD_PPL5_POS    (LCD_BASE + 0x2A8)

+#define EPD_PPL5_SIZE   (LCD_BASE + 0x2AC)

+#define EPD_PPL6_POS    (LCD_BASE + 0x2B0)

+#define EPD_PPL6_SIZE   (LCD_BASE + 0x2B4)

+#define EPD_PPL7_POS    (LCD_BASE + 0x2B8)

+#define EPD_PPL7_SIZE   (LCD_BASE + 0x2BC)

+

+#define REG_EPD_CTRL     REG32(EPD_CTRL)    

+#define REG_EPD_STA      REG32(EPD_STA) 

+#define REG_EPD_ISR      REG32(EPD_ISR) 

+#define REG_EPD_CFG0     REG32(EPD_CFG0)

+#define REG_EPD_CFG1     REG32(EPD_CFG1)

+#define REG_EPD_PPL0     REG32(EPD_PPL0)

+#define REG_EPD_PPL1     REG32(EPD_PPL1)

+#define REG_EPD_VAT      REG32(EPD_VAT) 

+#define REG_EPD_DAV      REG32(EPD_DAV)

+#define REG_EPD_DAH      REG32(EPD_DAH)       

+#define REG_EPD_VSYNC     REG32(EPD_VSYNC)     

+#define REG_EPD_HSYNC     REG32(EPD_HSYNC)     

+#define REG_EPD_GDCLK     REG32(EPD_GDCLK)     

+#define REG_EPD_GDOE      REG32(EPD_GDOE)      

+#define REG_EPD_GDSP      REG32(EPD_GDSP)      

+#define REG_EPD_SDOE      REG32(EPD_SDOE)      

+#define REG_EPD_SDSP      REG32(EPD_SDSP)      

+#define REG_EPD_PMGR0    REG32(EPD_PMGR0)    

+#define REG_EPD_PMGR1    REG32(EPD_PMGR1)    

+#define REG_EPD_PMGR2    REG32(EPD_PMGR2)    

+#define REG_EPD_PMGR3    REG32(EPD_PMGR3)    

+#define REG_EPD_PMGR4    REG32(EPD_PMGR4)    

+#define REG_EPD_VCOM0    REG32(EPD_VCOM0)    

+#define REG_EPD_VCOM1    REG32(EPD_VCOM1)    

+#define REG_EPD_VCOM2    REG32(EPD_VCOM2)    

+#define REG_EPD_VCOM3    REG32(EPD_VCOM3)    

+#define REG_EPD_VCOM4    REG32(EPD_VCOM4)    

+#define REG_EPD_VCOM5    REG32(EPD_VCOM5)    

+#define REG_EPD_BORDR    REG32(EPD_BORDR)     

+#define REG_EPD_PPL0_POS   REG32(EPD_PPL0_POS)   

+#define REG_EPD_PPL0_SIZE  REG32(EPD_PPL0_SIZE)  

+#define REG_EPD_PPL1_POS   REG32(EPD_PPL1_POS)   

+#define REG_EPD_PPL1_SIZE  REG32(EPD_PPL1_SIZE)  

+#define REG_EPD_PPL2_POS   REG32(EPD_PPL2_POS)   

+#define REG_EPD_PPL2_SIZE  REG32(EPD_PPL2_SIZE)  

+#define REG_EPD_PPL3_POS   REG32(EPD_PPL3_POS)   

+#define REG_EPD_PPL3_SIZE  REG32(EPD_PPL3_SIZE)  

+#define REG_EPD_PPL4_POS   REG32(EPD_PPL4_POS)    

+#define REG_EPD_PPL4_SIZE  REG32(EPD_PPL4_SIZE)  

+#define REG_EPD_PPL5_POS   REG32(EPD_PPL5_POS)   

+#define REG_EPD_PPL5_SIZE  REG32(EPD_PPL5_SIZE)  

+#define REG_EPD_PPL6_POS   REG32(EPD_PPL6_POS)   

+#define REG_EPD_PPL6_SIZE  REG32(EPD_PPL6_SIZE)  

+#define REG_EPD_PPL7_POS   REG32(EPD_PPL7_POS)   

+#define REG_EPD_PPL7_SIZE  REG32(EPD_PPL7_SIZE)  

+

+#define EPD_CTRL_PPL7_FRM_INTM		(1 << 31)

+#define EPD_CTRL_PPL6_FRM_INTM		(1 << 30)

+#define EPD_CTRL_PPL5_FRM_INTM		(1 << 29)

+#define EPD_CTRL_PPL4_FRM_INTM		(1 << 28)

+#define EPD_CTRL_PPL3_FRM_INTM		(1 << 27)

+#define EPD_CTRL_PPL2_FRM_INTM		(1 << 26)

+#define EPD_CTRL_PPL1_FRM_INTM		(1 << 25)

+#define EPD_CTRL_PPL0_FRM_INTM		(1 << 24)

+#define EPD_CTRL_FRM_VCOM_INTM		(1 << 22)

+#define EPD_CTRL_IMG_DONE_INTM		(1 << 21)

+#define EPD_CTRL_FRM_DONE_INTM		(1 << 20)

+#define EPD_CTRL_FRM_ABT_INTM		(1 << 19)

+#define EPD_CTRL_PWR_OFF_INTM		(1 << 18)

+#define EPD_CTRL_PWR_ON_INTM		(1 << 17)

+#define EPD_CTRL_DMA_DONE_INTM		(1 << 16)

+#define EPD_CTRL_PPL7_FRM_ENA		(1 << 15)

+#define EPD_CTRL_PPL6_FRM_ENA		(1 << 14)

+#define EPD_CTRL_PPL5_FRM_ENA		(1 << 13)

+#define EPD_CTRL_PPL4_FRM_ENA		(1 << 12)

+#define EPD_CTRL_PPL3_FRM_ENA		(1 << 11)

+#define EPD_CTRL_PPL2_FRM_ENA		(1 << 10)

+#define EPD_CTRL_PPL1_FRM_ENA		(1 << 9)

+#define EPD_CTRL_PPL0_FRM_ENA		(1 << 8)

+#define EPD_CTRL_IMG_REF_ENA		(1 << 7)

+#define EPD_CTRL_IMG_REF_ABT		(1 << 6)

+#define EPD_CTRL_PWROFF			(1 << 5)

+#define EPD_CTRL_PWRON			(1 << 4)

+#define EPD_CTRL_EPD_DMA_MODE		(1 << 1)

+#define EPD_CTRL_EPD_ENA		(1 << 0)

+

+#define EPD_ISR_PPL7_FRM_INT		(1 << 15)

+#define EPD_ISR_PPL6_FRM_INT		(1 << 14)

+#define EPD_ISR_PPL5_FRM_INT		(1 << 13)

+#define EPD_ISR_PPL4_FRM_INT		(1 << 12)

+#define EPD_ISR_PPL3_FRM_INT		(1 << 11)

+#define EPD_ISR_PPL2_FRM_INT		(1 << 10)

+#define EPD_ISR_PPL1_FRM_INT		(1 << 9)

+#define EPD_ISR_PPL0_FRM_INT		(1 << 8)

+#define EPD_ISR_FRM_VCOM_INT		(1 << 6)

+#define EPD_ISR_IMG_DONE_INT		(1 << 5)

+#define EPD_ISR_FRM_DONE_INT		(1 << 4)

+#define EPD_ISR_FRM_ABT_INT		(1 << 3)

+#define EPD_ISR_PWR_OFF_INT		(1 << 2)

+#define EPD_ISR_PWR_ON_INT		(1 << 1)

+#define EPD_ISR_DMA_DONE_INT		(1 << 0)

+

+#define EPD_CFG0_DUAL_GATE		(1 << 31)

+#define EPD_CFG0_COLOR_MODE		(1 << 30)

+#define EPD_CFG0_COLOR_FORMAT_BIT	26

+#define EPD_CFG0_COLOR_FORMAT_MASK	(0xf << EPD_CFG0_COLOR_FORMAT_BIT)

+#define EPD_CFG0_SDSP_MODE		(1 << 25)

+#define EPD_CFG0_GDCLK_MODE		(1 << 24)

+#define EPD_CFG0_GDOE_MODE_BIT		22

+#define EPD_CFG0_GDOE_MODE_MASK		(0x3 << EPD_CFG0_GDOE_MODE_BIT)

+#define EPD_CFG0_GDUD			(1 << 21)

+#define EPD_CFG0_SDRL			(1 << 20)

+#define EPD_CFG0_GDCLK_POL		(1 << 19)

+#define EPD_CFG0_GDOE_POL		(1 << 18)

+#define EPD_CFG0_GDSP_POL		(1 << 17)

+#define EPD_CFG0_SDCLK_POL		(1 << 16)

+#define EPD_CFG0_SDOE_POL		(1 << 15)

+#define EPD_CFG0_SDSP_POL		(1 << 14)

+#define EPD_CFG0_SDCE_POL		(1 << 13)

+#define EPD_CFG0_SDLE_POL		(1 << 12)

+#define EPD_CFG0_COMP_MODE		(1 << 8)

+#define EPD_CFG0_EPD_OBPP_BIT		1

+#define EPD_CFG0_EPD_OBPP_MASK		(0x7 << EPD_CFG0_EPD_OBPP_BIT)

+#define EPD_CFG0_EPD_OMODE		(1 << 0)

+

+#define EPD_CFG1_SDDO_REV		(1 << 30)

+#define EPD_CFG1_PDAT_SWAP		(1 << 29)

+#define EPD_CFG1_SDCE_REV		(1 << 28)

+#define EPD_CFG1_SDOS_BIT		16

+#define EPD_CFG1_SDOS_MASK		(0xff << EPD_CFG1_SDOS_BIT)

+#define EPD_CFG1_PADDING_DAT_BIT	8

+#define EPD_CFG1_PADDING_DAT_MASK	(0xff << EPD_CFG1_PADDING_DAT_BIT)

+#define EPD_CFG1_SDCE_STN_BIT		4

+#define EPD_CFG1_SDCE_STN_MASK		(0xf << EPD_CFG1_SDCE_STN_BIT)

+#define EPD_CFG1_SDCE_NUM_BIT		0

+#define EPD_CFG1_SDCE_NUM_MASK		(0xf << EPD_CFG1_SDCE_NUM_BIT)

+

+#define EPD_PPL0_PPL3_FRM_NUM_BIT	24

+#define EPD_PPL0_PPL3_FRM_NUM_MASK	(0xff << EPD_PPL0_PPL3_FRM_NUM_BIT)

+#define EPD_PPL0_PPL2_FRM_NUM_BIT	16

+#define EPD_PPL0_PPL2_FRM_NUM_MASK	(0xff << EPD_PPL0_PPL2_FRM_NUM_BIT)

+#define EPD_PPL0_PPL1_FRM_NUM_BIT	8

+#define EPD_PPL0_PPL1_FRM_NUM_MASK	(0xff << EPD_PPL0_PPL1_FRM_NUM_BIT)

+#define EPD_PPL0_PPL0_FRM_NUM_BIT	0

+#define EPD_PPL0_PPL0_FRM_NUM_MASK	(0xff << EPD_PPL0_PPL0_FRM_NUM_BIT)

+

+#define EPD_PPL1_PPL7_FRM_NUM_BIT	24

+#define EPD_PPL1_PPL7_FRM_NUM_MASK	(0xff << EPD_PPL1_PPL7_FRM_NUM_BIT)

+#define EPD_PPL1_PPL6_FRM_NUM_BIT	16

+#define EPD_PPL1_PPL6_FRM_NUM_MASK	(0xff << EPD_PPL1_PPL6_FRM_NUM_BIT)

+#define EPD_PPL1_PPL5_FRM_NUM_BIT	8

+#define EPD_PPL1_PPL5_FRM_NUM_MASK	(0xff << EPD_PPL1_PPL5_FRM_NUM_BIT)

+#define EPD_PPL1_PPL4_FRM_NUM_BIT	0

+#define EPD_PPL1_PPL4_FRM_NUM_MASK	(0xff << EPD_PPL1_PPL4_FRM_NUM_BIT)

+

+#define EPD_VAT_VT_BIT			16

+#define EPD_VAT_VT_MASK			(0xfff << EPD_VAT_VT_BIT)

+#define EPD_VAT_HT_BIT			0

+#define EPD_VAT_HT_MASK			(0xfff << EPD_VAT_HT_BIT)

+

+#define EPD_DAH_HDE_BIT			16

+#define EPD_DAH_HDE_MASK		(0xfff << EPD_DAH_HDE_BIT)

+#define EPD_DAH_HDS_BIT			0

+#define EPD_DAH_HDS_MASK		(0xfff << EPD_DAH_HDS_BIT)

+

+#define EPD_DAV_VDE_BIT			16

+#define EPD_DAV_VDE_MASK		(0xfff << EPD_DAV_VDE_BIT)

+#define EPD_DAV_VDS_BIT			0

+#define EPD_DAV_VDS_MASK		(0xfff << EPD_DAV_VDS_BIT)

+

+#define EPD_VSYNC_VPE_BIT		16

+#define EPD_VSYNC_VPE_MASK		(0xfff << EPD_VSYNC_VPE_BIT)

+#define EPD_VSYNC_VPS_BIT		0

+#define EPD_VSYNC_VPS_MASK		(0xfff << EPD_VSYNC_VPS_BIT)

+

+#define EPD_HSYNC_HPE_BIT		16

+#define EPD_HSYNC_HPE_MASK		(0xfff << EPD_HSYNC_HPE_BIT)

+#define EPD_HSYNC_HPS_BIT		0

+#define EPD_HSYNC_HPS_MASK		(0xfff << EPD_HSYNC_HPS_BIT)

+

+#define EPD_GDCLK_DIS_BIT		16

+#define EPD_GDCLK_DIS_MASK		(0xfff << EPD_GDCLK_DIS_BIT)

+#define EPD_GDCLK_ENA_BIT		0

+#define EPD_GDCLK_ENA_MASK		(0xfff << EPD_GDCLK_ENA_BIT)

+

+#define EPD_GDOE_DIS_BIT		16

+#define EPD_GDOE_DIS_MASK		(0xfff << EPD_GDOE_DIS_BIT)

+#define EPD_GDOE_ENA_BIT		0

+#define EPD_GDOE_ENA_MASK		(0xfff << EPD_GDOE_ENA_BIT)

+

+#define EPD_GDSP_DIS_BIT		16

+#define EPD_GDSP_DIS_MASK		(0xfff << EPD_GDSP_DIS_BIT)

+#define EPD_GDSP_ENA_BIT		0

+#define EPD_GDSP_ENA_MASK		(0xfff << EPD_GDSP_ENA_BIT)

+

+#define EPD_SDOE_DIS_BIT		16

+#define EPD_SDOE_DIS_MASK		(0xfff << EPD_SDOE_DIS_BIT)

+#define EPD_SDOE_ENA_BIT		0

+#define EPD_SDOE_ENA_MASK		(0xfff << EPD_SDOE_ENA_BIT)

+

+#define EPD_SDSP_DIS_BIT		16

+#define EPD_SDSP_DIS_MASK		(0xfff << EPD_SDSP_DIS_BIT)

+#define EPD_SDSP_ENA_BIT		0

+#define EPD_SDSP_ENA_MASK		(0xfff << EPD_SDSP_ENA_BIT)

+

+#define EPD_PMGR0_PWR_DLY12_BIT		16

+#define EPD_PMGR0_PWR_DLY12_MASK	(0xfff << EPD_PMGR0_PWR_DLY12_BIT)

+#define EPD_PMGR0_PWR_DLY01_BIT		0

+#define EPD_PMGR0_PWR_DLY01_MASK	(0xfff << EPD_PMGR0_PWR_DLY01_BIT)

+

+#define EPD_PMGR1_PWR_DLY34_BIT		16

+#define EPD_PMGR1_PWR_DLY34_MASK	(0xfff << EPD_PMGR1_PWR_DLY34_BIT)

+#define EPD_PMGR1_PWR_DLY23_BIT		0

+#define EPD_PMGR1_PWR_DLY23_MASK	(0xfff << EPD_PMGR1_PWR_DLY23_BIT)

+

+#define EPD_PMGR2_PWR_DLY56_BIT		16

+#define EPD_PMGR2_PWR_DLY56_MASK	(0xfff << EPD_PMGR2_PWR_DLY56_BIT)

+#define EPD_PMGR2_PWR_DLY45_BIT		0

+#define EPD_PMGR2_PWR_DLY45_MASK	(0xfff << EPD_PMGR2_PWR_DLY45_BIT)

+

+#define EPD_PMGR3_VCOM_IDLE_BIT		30

+#define EPD_PMGR3_VCOM_IDLE_MASK	(0x3 << EPD_PMGR3_VCOM_IDLE_BIT)

+#define EPD_PMGR3_PWRCOM_POL		(1 << 29)

+#define EPD_PMGR3_UNI_POL		(1 << 28)

+#define EPD_PMGR3_PPL7_BDR_ENA		(1 << 27)

+#define EPD_PMGR3_BDR_LEVEL		(1 << 26)

+#define EPD_PMGR3_BDR_VALUE_BIT		24

+#define EPD_PMGR3_BDR_VALUE_MASK	(0x3 << EPD_PMGR3_BDR_VALUE_BIT)

+#define EPD_PMGR3_PWR_POL_BIT		16

+#define EPD_PMGR3_PWR_POL_MASK		(0xff << EPD_PMGR3_PWR_DLY67_BIT)

+#define EPD_PMGR3_PWR_DLY67_BIT		0

+#define EPD_PMGR3_PWR_DLY67_MASK	(0xfff << EPD_PMGR3_PWR_DLY67_BIT)

+

+#define EPD_PMGR4_PWR_VAL_BIT		16

+#define EPD_PMGR4_PWR_VAL_MASK		(0xff << EPD_PMGR2_PWR_VAL_BIT)

+#define EPD_PMGR4_PWR_ENA_BIT		0

+#define EPD_PMGR4_PWR_ENA_MASK		(0xff << EPD_PMGR2_PWR_ENA_BIT)

+

+#define EPD_PPL_POS_PPL_YPOS_BIT	16

+#define EPD_PPL_POS_PPL_YPOS_MASK	(0xfff << EPD_PPL_POS_PPL_YPOS_BIT)

+#define EPD_PPL_POS_PPL_XPOS_BIT	0

+#define EPD_PPL_POS_PPL_XPOS_MASK	(0xfff << EPD_PPL_POS_PPL_XPOS_BIT)

+

+#define EPD_PPL_SIZE_PPL_HEIGHT_BIT	16

+#define EPD_PPL_SIZE_PPL_HEIGHT_MASK	(0xfff << EPD_PPL_SIZE_PPL_HEIGHT_BIT)

+#define EPD_PPL_SIZE_PPL_WIDTH_BIT	0

+#define EPD_PPL_SIZE_PPL_WIDTH_MASK	(0xfff << EPD_PPL_SIZE_PPL_WIDTH_BIT)

+

+#else  // for JZ4760

+

+#define EPD_CTRL1	(LCD_BASE + 0xc0)

+#define EPD_CTRL2	(LCD_BASE + 0xc4)

+#define EPD_CTRL3	(LCD_BASE + 0xc8)

+#define EPD_CTRL4	(LCD_BASE + 0xcc)

+#define EPD_CTRL5	(LCD_BASE + 0xd0)

+#define EPD_CTRL6	(LCD_BASE + 0xd4)

+#define EPD_CTRL7	(LCD_BASE + 0xd8)

+#define EPD_CTRL8	(LCD_BASE + 0xdc)

+#define EPD_CTRL9	(LCD_BASE + 0xe0)

+#define EPD_VCOM0	(LCD_BASE + 0xf0)

+#define EPD_VCOM1	(LCD_BASE + 0xf4)

+#define EPD_VCOM2	(LCD_BASE + 0xf8)

+#define EPD_VCOM3	(LCD_BASE + 0xfc)

+

+#define REG_EPD_CTRL1	REG32(EPD_CTRL1)

+#define REG_EPD_CTRL2	REG32(EPD_CTRL2)

+#define REG_EPD_CTRL3	REG32(EPD_CTRL3)

+#define REG_EPD_CTRL4	REG32(EPD_CTRL4)

+#define REG_EPD_CTRL5	REG32(EPD_CTRL5)

+#define REG_EPD_CTRL6	REG32(EPD_CTRL6)

+#define REG_EPD_CTRL7	REG32(EPD_CTRL7)

+#define REG_EPD_CTRL8	REG32(EPD_CTRL8)

+#define REG_EPD_CTRL9	REG32(EPD_CTRL9)

+

+#define REG_EPD_VCOM0 	REG32(EPD_VCOM0)

+#define REG_EPD_VCOM1 	REG32(EPD_VCOM1)

+#define REG_EPD_VCOM2 	REG32(EPD_VCOM2)

+#define REG_EPD_VCOM3 	REG32(EPD_VCOM3)

+

+#define EPD_CTRL1_GDCLKEN_BIT	16

+#define EPD_CTRL1_GDCLKEN_MASK	(0xfff << EPD_CTRL1_GDCLKEN_BIT)

+#define EPD_CTRL1_AUOEN		(1 << 15)

+#define EPD_CTRL1_GDOEP		(1 << 14)

+#define EPD_CTRL1_GDRL		(1 << 13)

+#define EPD_CTRL1_SDOREV	(1 << 12)

+#define EPD_CTRL1_SDCEREV	(1 << 11)

+#define EPD_CTRL1_SDSHR		(1 << 10)

+#define EPD_CTRL1_PPC		(1 << 9)

+#define EPD_CTRL1_PADDINGD_BIT	1

+#define EPD_CTRL1_PADDINGD_MASK	(0xff << EPD_CTRL1_PADDINGD_BIT)

+#define EPD_CTRL1_DDREN		(1 << 0)

+

+#define EPD_CTRL2_PWRDL01_BIT	20 	

+#define EPD_CTRL2_PWRDL01_MASK	(0xfff << EPD_CTRL2_PWRDL01_BIT)

+#define EPD_CTRL2_PWROFF	(1 << 19)

+#define EPD_CTRL2_PWRON		(1 << 18)

+#define EPD_CTRL2_PCOMP		(1 << 17)

+#define EPD_CTRL2_SDCE1_BIT	13

+#define EPD_CTRL2_SDCE1_MASK	(0xf << EPD_CTRL2_SDCE1_BIT)

+#define EPD_CTRL2_SDOS_BIT	4

+#define EPD_CTRL2_SDOS_MASK	(0x1f << EPD_CTRL2_SDOS_BIT)

+#define EPD_CTRL2_SDCN_BIT	0

+#define EPD_CTRL2_SDCN_MASK	(0xf << EPD_CTRL2_SDCN_BIT)

+

+#define EPD_CTRL3_PWRDL23_BIT	16

+#define EPD_CTRL3_PWRDL23_MASK	(0xfff << EPD_CTRL3_PWRDL23_BIT)

+#define EPD_CTRL3_PWRDL12_BIT	0

+#define EPD_CTRL3_PWRDL12_MASK	(0xfff << EPD_CTRL3_PWRDL12_BIT)

+

+#define EPD_CTRL4_PWR7P		(1 << 31)

+#define EPD_CTRL4_PWR6P		(1 << 30)

+#define EPD_CTRL4_PWR5P		(1 << 29)

+#define EPD_CTRL4_PWR4P		(1 << 28)

+#define EPD_CTRL4_PWR3P		(1 << 27)

+#define EPD_CTRL4_PWR2P		(1 << 26)

+#define EPD_CTRL4_PWR1P		(1 << 25)

+#define EPD_CTRL4_PWR0P		(1 << 24)

+#define EPD_CTRL4_PWRDNM	(1 << 16)

+#define EPD_CTRL4_DMAM		(1 << 15)

+#define EPD_CTRL4_FEM		(1 << 14)

+#define EPD_CTRL4_FCEM		(1 << 13)

+#define EPD_CTRL4_PWRUPM	(1 << 12)

+#define EPD_CTRL4_FEINTSEL	(1 << 11)

+#define EPD_CTRL4_FCANCEL	(1 << 10)

+#define EPD_CTRL4_FEN		(1 << 9)

+#define EPD_CTRL4_PADDING_SWAP

+#define EPD_CTRL4_SDCEP		(1 << 4)

+#define EPD_CTRL4_SDLEP		(1 << 3)

+#define EPD_CTRL4_SDOEP		(1 << 2)

+#define EPD_CTRL4_GDCLKP	(1 << 1)

+#define EPD_CTRL4_GDSPP		(1 << 0)

+

+#define EPD_CTRL5_GDCLKDIS_BIT	16

+#define EPD_CTRL5_GDCDLKIS_MASK	(0xfff << EPD_CTRL5_GDCLKDIS_BIT)

+#define EPD_CTRL5_MAXFRM_BIT	8

+#define EPD_CTRL5_MAXFRM_MASK	(0xff << EPD_CTRL5_MAXFRM_BIT)

+#define EPD_CTRL5_DMAMODE	(1 << 5)

+#define EPD_CTRL5_OBPP_BIT	2

+#define EPD_CTRL5_OBPP_MASK	(0x7 << EPD_CTRL5_OBPP_BIT)

+#define EPD_CTRL5_OMODE		(1 << 1)

+#define EPD_CTRL5_EPDEN		(1 << 0)

+

+#define EPD_CTRL6_GDSPDIS_BIT	16

+#define EPD_CTRL6_GDSPDIS_AMSK	(0xfff << EPD_CTRL6_GDSPDIS_BIT)

+#define EPD_CTRL6_GDSPEN_BIT	0

+#define EPD_CTRL6_GDSPEN_MASK	(0xfff << EPD_CTRL6_GDSPEN_BIT)

+

+#define EPD_CTRL7_SDOEDIS_BIT	16

+#define EPD_CTRL7_SDOEDIS_MASK	(0xfff << EPD_CTRL7_SDOEDIS_BIT)

+#define EPD_CTRL7_SDOEEN_BIT	0

+#define EPD_CTRL7_SDOEEN_MASK	(0xfff << EPD_CTRL7_SDOEEN_BIT)

+

+#define EPD_CTRL8_PWRDL45_BIT	16

+#define EPD_CTRL8_PWRDL45_MASK	(0xfff << EPD_CTRL8_PWRDL45_BIT)

+#define EPD_CTRL8_PWRDL34_BIT	0

+#define EPD_CTRL8_PWRDL34_MASK	(0xfff << EPD_CTRL8_PWRDL34_BIT)

+

+#define EPD_CTRL9_PWRDL67_BIT	16

+#define EPD_CTRL9_PWRDL67_MASK	(0xfff << EPD_CTRL9_PWRDL67_BIT)

+#define EPD_CTRL9_PWRDL56_BIT	0

+#define EPD_CTRL9_PWRDL56_MASK	(0xfff << EPD_CTRL9_PWRDL56_BIT)      

+

+#endif //End JZ4760

+

+#ifndef __MIPS_ASSEMBLER

+

+/*************************************************************************

+ * SLCD (Smart LCD Controller)

+ *************************************************************************/

+#define __slcd_set_data_18bit() \

+  ( REG_SLCD_CFG = (REG_SLCD_CFG & ~SLCD_CFG_DWIDTH_MASK) | SLCD_CFG_DWIDTH_18BIT )

+#define __slcd_set_data_16bit() \

+  ( REG_SLCD_CFG = (REG_SLCD_CFG & ~SLCD_CFG_DWIDTH_MASK) | SLCD_CFG_DWIDTH_16BIT )

+#define __slcd_set_data_8bit_x3() \

+  ( REG_SLCD_CFG = (REG_SLCD_CFG & ~SLCD_CFG_DWIDTH_MASK) | SLCD_CFG_DWIDTH_8BIT_x3 )

+#define __slcd_set_data_8bit_x2() \

+  ( REG_SLCD_CFG = (REG_SLCD_CFG & ~SLCD_CFG_DWIDTH_MASK) | SLCD_CFG_DWIDTH_8BIT_x2 )

+#define __slcd_set_data_8bit_x1() \

+  ( REG_SLCD_CFG = (REG_SLCD_CFG & ~SLCD_CFG_DWIDTH_MASK) | SLCD_CFG_DWIDTH_8BIT_x1 )

+#define __slcd_set_data_24bit() \

+  ( REG_SLCD_CFG = (REG_SLCD_CFG & ~SLCD_CFG_DWIDTH_MASK) | SLCD_CFG_DWIDTH_24BIT )

+#define __slcd_set_data_9bit_x2() \

+  ( REG_SLCD_CFG = (REG_SLCD_CFG & ~SLCD_CFG_DWIDTH_MASK) | SLCD_CFG_DWIDTH_9BIT_x2 )

+

+#define __slcd_set_cmd_16bit() \

+  ( REG_SLCD_CFG = (REG_SLCD_CFG & ~SLCD_CFG_CWIDTH_MASK) | SLCD_CFG_CWIDTH_16BIT )

+#define __slcd_set_cmd_8bit() \

+  ( REG_SLCD_CFG = (REG_SLCD_CFG & ~SLCD_CFG_CWIDTH_MASK) | SLCD_CFG_CWIDTH_8BIT )

+#define __slcd_set_cmd_18bit() \

+  ( REG_SLCD_CFG = (REG_SLCD_CFG & ~SLCD_CFG_CWIDTH_MASK) | SLCD_CFG_CWIDTH_18BIT )

+#define __slcd_set_cmd_24bit() \

+  ( REG_SLCD_CFG = (REG_SLCD_CFG & ~SLCD_CFG_CWIDTH_MASK) | SLCD_CFG_CWIDTH_24BIT )

+

+#define __slcd_set_cs_high()        ( REG_SLCD_CFG |= SLCD_CFG_CS_ACTIVE_HIGH )

+#define __slcd_set_cs_low()         ( REG_SLCD_CFG &= ~SLCD_CFG_CS_ACTIVE_HIGH )

+

+#define __slcd_set_rs_high()        ( REG_SLCD_CFG |= SLCD_CFG_RS_CMD_HIGH )

+#define __slcd_set_rs_low()         ( REG_SLCD_CFG &= ~SLCD_CFG_RS_CMD_HIGH )

+

+#define __slcd_set_clk_falling()    ( REG_SLCD_CFG &= ~SLCD_CFG_CLK_ACTIVE_RISING )

+#define __slcd_set_clk_rising()     ( REG_SLCD_CFG |= SLCD_CFG_CLK_ACTIVE_RISING )

+

+#define __slcd_set_parallel_type()  ( REG_SLCD_CFG &= ~SLCD_CFG_TYPE_SERIAL )

+#define __slcd_set_serial_type()    ( REG_SLCD_CFG |= SLCD_CFG_TYPE_SERIAL )

+

+/* SLCD Control Register */

+#define __slcd_enable_dma()         ( REG_SLCD_CTRL |= SLCD_CTRL_DMA_EN )

+#define __slcd_disable_dma()        ( REG_SLCD_CTRL &= ~SLCD_CTRL_DMA_EN )

+

+/* SLCD Status Register */

+#define __slcd_is_busy()            ( REG_SLCD_STATE & SLCD_STATE_BUSY )

+

+/* SLCD Data Register */

+#define __slcd_set_cmd_rs()         ( REG_SLCD_DATA |= SLCD_DATA_RS_COMMAND)

+#define __slcd_set_data_rs()        ( REG_SLCD_DATA &= ~SLCD_DATA_RS_COMMAND)

+

+

+/***************************************************************************

+ * LCD

+ ***************************************************************************/

+

+/***************************************************************************

+ * LCD

+ ***************************************************************************/

+#define __lcd_as_smart_lcd() 		( REG_LCD_CFG |= ( LCD_CFG_LCDPIN_SLCD | LCD_CFG_MODE_SLCD))

+#define __lcd_as_general_lcd() 		( REG_LCD_CFG &= ~( LCD_CFG_LCDPIN_SLCD | LCD_CFG_MODE_SLCD))

+

+#define __lcd_enable_tvepeh() 		( REG_LCD_CFG |= LCD_CFG_TVEPEH )

+#define __lcd_disable_tvepeh() 		( REG_LCD_CFG &= ~LCD_CFG_TVEPEH )

+

+#define __lcd_enable_fuhold() 		( REG_LCD_CFG |= LCD_CFG_FUHOLD )

+#define __lcd_disable_fuhold() 		( REG_LCD_CFG &= ~LCD_CFG_FUHOLD )

+

+#define __lcd_des_8word() 		( REG_LCD_CFG |= LCD_CFG_NEWDES )

+#define __lcd_des_4word() 		( REG_LCD_CFG &= ~LCD_CFG_NEWDES )

+

+#define __lcd_enable_bypass_pal() 	( REG_LCD_CFG |= LCD_CFG_PALBP )

+#define __lcd_disable_bypass_pal() 	( REG_LCD_CFG &= ~LCD_CFG_PALBP )

+

+#define __lcd_set_lcdpnl_term()		( REG_LCD_CFG |= LCD_CFG_TVEN )

+#define __lcd_set_tv_term()		( REG_LCD_CFG &= ~LCD_CFG_TVEN )

+

+#define __lcd_enable_auto_recover() 	( REG_LCD_CFG |= LCD_CFG_RECOVER )

+#define __lcd_disable_auto_recover() 	( REG_LCD_CFG &= ~LCD_CFG_RECOVER )

+

+#define __lcd_enable_dither() 	        ( REG_LCD_CFG |= LCD_CFG_DITHER )

+#define __lcd_disable_dither() 	        ( REG_LCD_CFG &= ~LCD_CFG_DITHER )

+

+#define __lcd_disable_ps_mode()	        ( REG_LCD_CFG |= LCD_CFG_PSM )

+#define __lcd_enable_ps_mode()	        ( REG_LCD_CFG &= ~LCD_CFG_PSM )

+

+#define __lcd_disable_cls_mode() 	( REG_LCD_CFG |= LCD_CFG_CLSM )

+#define __lcd_enable_cls_mode()	        ( REG_LCD_CFG &= ~LCD_CFG_CLSM )

+

+#define __lcd_disable_spl_mode() 	( REG_LCD_CFG |= LCD_CFG_SPLM )

+#define __lcd_enable_spl_mode()	        ( REG_LCD_CFG &= ~LCD_CFG_SPLM )

+

+#define __lcd_disable_rev_mode() 	( REG_LCD_CFG |= LCD_CFG_REVM )

+#define __lcd_enable_rev_mode()	        ( REG_LCD_CFG &= ~LCD_CFG_REVM )

+

+#define __lcd_disable_hsync_mode() 	( REG_LCD_CFG |= LCD_CFG_HSYNM )

+#define __lcd_enable_hsync_mode()	( REG_LCD_CFG &= ~LCD_CFG_HSYNM )

+

+#define __lcd_disable_pclk_mode() 	( REG_LCD_CFG |= LCD_CFG_PCLKM )

+#define __lcd_enable_pclk_mode()	( REG_LCD_CFG &= ~LCD_CFG_PCLKM )

+

+#define __lcd_normal_outdata()          ( REG_LCD_CFG &= ~LCD_CFG_INVDAT )

+#define __lcd_inverse_outdata()         ( REG_LCD_CFG |= LCD_CFG_INVDAT )

+

+#define __lcd_sync_input()              ( REG_LCD_CFG |= LCD_CFG_SYNDIR_IN )

+#define __lcd_sync_output()             ( REG_LCD_CFG &= ~LCD_CFG_SYNDIR_IN )

+

+#define __lcd_hsync_active_high()       ( REG_LCD_CFG &= ~LCD_CFG_HSP )

+#define __lcd_hsync_active_low()        ( REG_LCD_CFG |= LCD_CFG_HSP )

+

+#define __lcd_pclk_rising()             ( REG_LCD_CFG &= ~LCD_CFG_PCP )

+#define __lcd_pclk_falling()            ( REG_LCD_CFG |= LCD_CFG_PCP )

+

+#define __lcd_de_active_high()          ( REG_LCD_CFG &= ~LCD_CFG_DEP )

+#define __lcd_de_active_low()           ( REG_LCD_CFG |= LCD_CFG_DEP )

+

+#define __lcd_vsync_rising()            ( REG_LCD_CFG &= ~LCD_CFG_VSP )

+#define __lcd_vsync_falling()           ( REG_LCD_CFG |= LCD_CFG_VSP )

+

+#define __lcd_set_16_tftpnl() \

+  ( REG_LCD_CFG = (REG_LCD_CFG & ~LCD_CFG_MODE_TFT_MASK) | LCD_CFG_MODE_TFT_16BIT )

+

+#define __lcd_set_18_tftpnl() \

+  ( REG_LCD_CFG = (REG_LCD_CFG & ~LCD_CFG_MODE_TFT_MASK) | LCD_CFG_MODE_TFT_18BIT )

+

+#define __lcd_set_24_tftpnl()		( REG_LCD_CFG |= LCD_CFG_MODE_TFT_24BIT )

+

+/* 

+ * n=1,2,4,8 for single mono-STN 

+ * n=4,8 for dual mono-STN

+ */

+#define __lcd_set_panel_datawidth(n) 		\

+do { 						\

+	REG_LCD_CFG &= ~LCD_CFG_PDW_MASK; 	\

+	REG_LCD_CFG |= LCD_CFG_PDW_n##;		\

+} while (0)

+

+/* m = LCD_CFG_MODE_GENERUIC_TFT_xxx */

+#define __lcd_set_panel_mode(m) 		\

+do {						\

+	REG_LCD_CFG &= ~LCD_CFG_MODE_MASK;	\

+	REG_LCD_CFG |= (m);			\

+} while(0)

+

+/* n=4,8,16 */

+#define __lcd_set_burst_length(n) 		\

+do {						\

+	REG_LCD_CTRL &= ~LCD_CTRL_BST_MASK;	\

+	REG_LCD_CTRL |= LCD_CTRL_BST_n##;	\

+} while (0)

+

+#define __lcd_select_rgb565()		( REG_LCD_CTRL &= ~LCD_CTRL_RGB555 )

+#define __lcd_select_rgb555()		( REG_LCD_CTRL |= LCD_CTRL_RGB555 )

+

+#define __lcd_set_ofup()		( REG_LCD_CTRL |= LCD_CTRL_OFUP )

+#define __lcd_clr_ofup()		( REG_LCD_CTRL &= ~LCD_CTRL_OFUP )

+

+/* n=2,4,16 */

+#define __lcd_set_stn_frc(n) 			\

+do {						\

+	REG_LCD_CTRL &= ~LCD_CTRL_FRC_MASK;	\

+	REG_LCD_CTRL |= LCD_CTRL_FRC_n##;	\

+} while (0)

+

+#define __lcd_enable_eof_intr()		( REG_LCD_CTRL |= LCD_CTRL_EOFM )

+#define __lcd_disable_eof_intr()	( REG_LCD_CTRL &= ~LCD_CTRL_EOFM )

+

+#define __lcd_enable_sof_intr()		( REG_LCD_CTRL |= LCD_CTRL_SOFM )

+#define __lcd_disable_sof_intr()	( REG_LCD_CTRL &= ~LCD_CTRL_SOFM )

+

+#define __lcd_enable_ofu_intr()		( REG_LCD_CTRL |= LCD_CTRL_OFUM )

+#define __lcd_disable_ofu_intr()	( REG_LCD_CTRL &= ~LCD_CTRL_OFUM )

+

+#define __lcd_enable_ifu0_intr()	( REG_LCD_CTRL |= LCD_CTRL_IFUM0 )

+#define __lcd_disable_ifu0_intr()	( REG_LCD_CTRL &= ~LCD_CTRL_IFUM0 )

+

+#define __lcd_enable_ifu1_intr()	( REG_LCD_CTRL |= LCD_CTRL_IFUM1 )

+#define __lcd_disable_ifu1_intr()	( REG_LCD_CTRL &= ~LCD_CTRL_IFUM1 )

+

+#define __lcd_enable_ldd_intr()		( REG_LCD_CTRL |= LCD_CTRL_LDDM )

+#define __lcd_disable_ldd_intr()	( REG_LCD_CTRL &= ~LCD_CTRL_LDDM )

+

+#define __lcd_enable_qd_intr()		( REG_LCD_CTRL |= LCD_CTRL_QDM )

+#define __lcd_disable_qd_intr()		( REG_LCD_CTRL &= ~LCD_CTRL_QDM )

+

+#define __lcd_reverse_byte_endian()	( REG_LCD_CTRL |= LCD_CTRL_BEDN )

+#define __lcd_normal_byte_endian()	( REG_LCD_CTRL &= ~LCD_CTRL_BEDN )

+

+#define __lcd_pixel_endian_little()	( REG_LCD_CTRL |= LCD_CTRL_PEDN )

+#define __lcd_pixel_endian_big()	( REG_LCD_CTRL &= ~LCD_CTRL_PEDN )

+

+#define __lcd_set_dis()			( REG_LCD_CTRL |= LCD_CTRL_DIS )

+#define __lcd_clr_dis()			( REG_LCD_CTRL &= ~LCD_CTRL_DIS )

+

+#define __lcd_set_ena()			( REG_LCD_CTRL |= LCD_CTRL_ENA )

+#define __lcd_clr_ena()			( REG_LCD_CTRL &= ~LCD_CTRL_ENA )

+

+/* n=1,2,4,8,16 */

+#define __lcd_set_bpp(n) \

+  ( REG_LCD_CTRL = (REG_LCD_CTRL & ~LCD_CTRL_BPP_MASK) | LCD_CTRL_BPP_##n )

+

+/* LCD status register indication */

+

+#define __lcd_quick_disable_done()	( REG_LCD_STATE & LCD_STATE_QD )

+#define __lcd_disable_done()		( REG_LCD_STATE & LCD_STATE_LDD )

+#define __lcd_infifo0_underrun()	( REG_LCD_STATE & LCD_STATE_IFU0 )

+#define __lcd_infifo1_underrun()	( REG_LCD_STATE & LCD_STATE_IFU1 )

+#define __lcd_outfifo_underrun()	( REG_LCD_STATE & LCD_STATE_OFU )

+#define __lcd_start_of_frame()		( REG_LCD_STATE & LCD_STATE_SOF )

+#define __lcd_end_of_frame()		( REG_LCD_STATE & LCD_STATE_EOF )

+

+#define __lcd_clr_outfifounderrun()	( REG_LCD_STATE &= ~LCD_STATE_OFU )

+#define __lcd_clr_sof()			( REG_LCD_STATE &= ~LCD_STATE_SOF )

+#define __lcd_clr_eof()			( REG_LCD_STATE &= ~LCD_STATE_EOF )

+

+/* OSD functions */

+#define __lcd_enable_osd() 	(REG_LCD_OSDC |= LCD_OSDC_OSDEN)

+#define __lcd_enable_f0() 	(REG_LCD_OSDC |= LCD_OSDC_F0EN)

+#define __lcd_enable_f1()	(REG_LCD_OSDC |= LCD_OSDC_F1EN)

+#define __lcd_enable_alpha() 	(REG_LCD_OSDC |= LCD_OSDC_ALPHAEN)

+#define __lcd_enable_alphamd()	(REG_LCD_OSDC |= LCD_OSDC_ALPHAMD)

+

+#define __lcd_disable_osd()	(REG_LCD_OSDC &= ~LCD_OSDC_OSDEN)

+#define __lcd_disable_f0() 	(REG_LCD_OSDC &= ~LCD_OSDC_F0EN)

+#define __lcd_disable_f1() 	(REG_LCD_OSDC &= ~LCD_OSDC_F1EN)

+#define __lcd_disable_alpha()	(REG_LCD_OSDC &= ~LCD_OSDC_ALPHAEN)

+#define __lcd_disable_alphamd()	(REG_LCD_OSDC &= ~LCD_OSDC_ALPHAMD)

+

+/* OSD Controll Register */

+#define __lcd_fg1_use_ipu() 		(REG_LCD_OSDCTRL |= LCD_OSDCTRL_IPU)

+#define __lcd_fg1_use_dma_chan1() 	(REG_LCD_OSDCTRL &= ~LCD_OSDCTRL_IPU)

+#define __lcd_fg1_unuse_ipu() 		__lcd_fg1_use_dma_chan1()

+#define __lcd_osd_rgb555_mode()         ( REG_LCD_OSDCTRL |= LCD_OSDCTRL_RGB555 )

+#define __lcd_osd_rgb565_mode()         ( REG_LCD_OSDCTRL &= ~LCD_OSDCTRL_RGB555 )

+#define __lcd_osd_change_size()         ( REG_LCD_OSDCTRL |= LCD_OSDCTRL_CHANGES )

+#define __lcd_osd_bpp_15_16() \

+  ( REG_LCD_OSDCTRL = (REG_LCD_OSDCTRL & ~LCD_OSDCTRL_OSDBPP_MASK) | LCD_OSDCTRL_OSDBPP_15_16 )

+#define __lcd_osd_bpp_18_24() \

+  ( REG_LCD_OSDCTRL = (REG_LCD_OSDCTRL & ~LCD_OSDCTRL_OSDBPP_MASK) | LCD_OSDCTRL_OSDBPP_18_24 )

+

+/* OSD State Register */

+#define __lcd_start_of_fg1()		( REG_LCD_STATE & LCD_OSDS_SOF1 )

+#define __lcd_end_of_fg1()		( REG_LCD_STATE & LCD_OSDS_EOF1 )

+#define __lcd_start_of_fg0()		( REG_LCD_STATE & LCD_OSDS_SOF0 )

+#define __lcd_end_of_fg0()		( REG_LCD_STATE & LCD_OSDS_EOF0 )

+#define __lcd_change_is_rdy()		( REG_LCD_STATE & LCD_OSDS_READY )

+

+/* Foreground Color Key Register 0,1(foreground 0, foreground 1) */

+#define __lcd_enable_colorkey0()	(REG_LCD_KEY0 |= LCD_KEY_KEYEN)

+#define __lcd_enable_colorkey1()	(REG_LCD_KEY1 |= LCD_KEY_KEYEN)

+#define __lcd_enable_colorkey0_md() 	(REG_LCD_KEY0 |= LCD_KEY_KEYMD)

+#define __lcd_enable_colorkey1_md() 	(REG_LCD_KEY1 |= LCD_KEY_KEYMD)

+#define __lcd_set_colorkey0(key) 	(REG_LCD_KEY0 = (REG_LCD_KEY0&~0xFFFFFF)|(key))

+#define __lcd_set_colorkey1(key) 	(REG_LCD_KEY1 = (REG_LCD_KEY1&~0xFFFFFF)|(key))

+

+#define __lcd_disable_colorkey0() 	(REG_LCD_KEY0 &= ~LCD_KEY_KEYEN)

+#define __lcd_disable_colorkey1() 	(REG_LCD_KEY1 &= ~LCD_KEY_KEYEN)

+#define __lcd_disable_colorkey0_md() 	(REG_LCD_KEY0 &= ~LCD_KEY_KEYMD)

+#define __lcd_disable_colorkey1_md() 	(REG_LCD_KEY1 &= ~LCD_KEY_KEYMD)

+

+/* IPU Restart Register */

+#define __lcd_enable_ipu_restart() 	(REG_LCD_IPUR |= LCD_IPUR_IPUREN)

+#define __lcd_disable_ipu_restart() 	(REG_LCD_IPUR &= ~LCD_IPUR_IPUREN)

+#define __lcd_set_ipu_restart_triger(n)	(REG_LCD_IPUR = (REG_LCD_IPUR&(~0xFFFFFF))|(n))

+

+/* RGB Control Register */

+#define __lcd_enable_rgb_dummy() 	(REG_LCD_RGBC |= LCD_RGBC_RGBDM)

+#define __lcd_disable_rgb_dummy() 	(REG_LCD_RGBC &= ~LCD_RGBC_RGBDM)

+

+#define __lcd_dummy_rgb() 	(REG_LCD_RGBC |= LCD_RGBC_DMM)

+#define __lcd_rgb_dummy() 	(REG_LCD_RGBC &= ~LCD_RGBC_DMM)

+

+#define __lcd_rgb2ycc() 	(REG_LCD_RGBC |= LCD_RGBC_YCC)

+#define __lcd_notrgb2ycc() 	(REG_LCD_RGBC &= ~LCD_RGBC_YCC)

+

+#define __lcd_odd_mode_rgb() \

+  ( REG_LCD_RGBC = (REG_LCD_RGBC & ~LCD_RGBC_ODDRGB_MASK) | LCD_RGBC_ODD_RGB )

+#define __lcd_odd_mode_rbg() \

+  ( REG_LCD_RGBC = (REG_LCD_RGBC & ~LCD_RGBC_ODDRGB_MASK) | LCD_RGBC_ODD_RBG )

+#define __lcd_odd_mode_grb() \

+  ( REG_LCD_RGBC = (REG_LCD_RGBC & ~LCD_RGBC_ODDRGB_MASK) | LCD_RGBC_ODD_GRB)

+

+#define __lcd_odd_mode_gbr() \

+  ( REG_LCD_RGBC = (REG_LCD_RGBC & ~LCD_RGBC_ODDRGB_MASK) | LCD_RGBC_ODD_GBR)

+#define __lcd_odd_mode_brg() \

+  ( REG_LCD_RGBC = (REG_LCD_RGBC & ~LCD_RGBC_ODDRGB_MASK) | LCD_RGBC_ODD_BRG)

+#define __lcd_odd_mode_bgr() \

+  ( REG_LCD_RGBC = (REG_LCD_RGBC & ~LCD_RGBC_ODDRGB_MASK) | LCD_RGBC_ODD_BGR)

+

+#define __lcd_even_mode_rgb() \

+  ( REG_LCD_RGBC = (REG_LCD_RGBC & ~LCD_RGBC_EVENRGB_MASK) | LCD_RGBC_EVEN_RGB )

+#define __lcd_even_mode_rbg() \

+  ( REG_LCD_RGBC = (REG_LCD_RGBC & ~LCD_RGBC_EVENRGB_MASK) | LCD_RGBC_EVEN_RBG )

+#define __lcd_even_mode_grb() \

+  ( REG_LCD_RGBC = (REG_LCD_RGBC & ~LCD_RGBC_EVENRGB_MASK) | LCD_RGBC_EVEN_GRB)

+

+#define __lcd_even_mode_gbr() \

+  ( REG_LCD_RGBC = (REG_LCD_RGBC & ~LCD_RGBC_EVENRGB_MASK) | LCD_RGBC_EVEN_GBR)

+#define __lcd_even_mode_brg() \

+  ( REG_LCD_RGBC = (REG_LCD_RGBC & ~LCD_RGBC_EVENRGB_MASK) | LCD_RGBC_EVEN_BRG)

+#define __lcd_even_mode_bgr() \

+  ( REG_LCD_RGBC = (REG_LCD_RGBC & ~LCD_RGBC_EVENRGB_MASK) | LCD_RGBC_EVEN_BGR)

+

+/* Vertical Synchronize Register */

+#define __lcd_vsync_get_vps() \

+  ( (REG_LCD_VSYNC & LCD_VSYNC_VPS_MASK) >> LCD_VSYNC_VPS_BIT )

+

+#define __lcd_vsync_get_vpe() \

+  ( (REG_LCD_VSYNC & LCD_VSYNC_VPE_MASK) >> LCD_VSYNC_VPE_BIT )

+#define __lcd_vsync_set_vpe(n) 				\

+do {							\

+	REG_LCD_VSYNC &= ~LCD_VSYNC_VPE_MASK;		\

+	REG_LCD_VSYNC |= (n) << LCD_VSYNC_VPE_BIT;	\

+} while (0)

+

+#define __lcd_hsync_get_hps() \

+  ( (REG_LCD_HSYNC & LCD_HSYNC_HPS_MASK) >> LCD_HSYNC_HPS_BIT )

+#define __lcd_hsync_set_hps(n) 				\

+do {							\

+	REG_LCD_HSYNC &= ~LCD_HSYNC_HPS_MASK;		\

+	REG_LCD_HSYNC |= (n) << LCD_HSYNC_HPS_BIT;	\

+} while (0)

+

+#define __lcd_hsync_get_hpe() \

+  ( (REG_LCD_HSYNC & LCD_HSYNC_HPE_MASK) >> LCD_VSYNC_HPE_BIT )

+#define __lcd_hsync_set_hpe(n) 				\

+do {							\

+	REG_LCD_HSYNC &= ~LCD_HSYNC_HPE_MASK;		\

+	REG_LCD_HSYNC |= (n) << LCD_HSYNC_HPE_BIT;	\

+} while (0)

+

+#define __lcd_vat_get_ht() \

+  ( (REG_LCD_VAT & LCD_VAT_HT_MASK) >> LCD_VAT_HT_BIT )

+#define __lcd_vat_set_ht(n) 				\

+do {							\

+	REG_LCD_VAT &= ~LCD_VAT_HT_MASK;		\

+	REG_LCD_VAT |= (n) << LCD_VAT_HT_BIT;		\

+} while (0)

+

+#define __lcd_vat_get_vt() \

+  ( (REG_LCD_VAT & LCD_VAT_VT_MASK) >> LCD_VAT_VT_BIT )

+#define __lcd_vat_set_vt(n) 				\

+do {							\

+	REG_LCD_VAT &= ~LCD_VAT_VT_MASK;		\

+	REG_LCD_VAT |= (n) << LCD_VAT_VT_BIT;		\

+} while (0)

+

+#define __lcd_dah_get_hds() \

+  ( (REG_LCD_DAH & LCD_DAH_HDS_MASK) >> LCD_DAH_HDS_BIT )

+#define __lcd_dah_set_hds(n) 				\

+do {							\

+	REG_LCD_DAH &= ~LCD_DAH_HDS_MASK;		\

+	REG_LCD_DAH |= (n) << LCD_DAH_HDS_BIT;		\

+} while (0)

+

+#define __lcd_dah_get_hde() \

+  ( (REG_LCD_DAH & LCD_DAH_HDE_MASK) >> LCD_DAH_HDE_BIT )

+#define __lcd_dah_set_hde(n) 				\

+do {							\

+	REG_LCD_DAH &= ~LCD_DAH_HDE_MASK;		\

+	REG_LCD_DAH |= (n) << LCD_DAH_HDE_BIT;		\

+} while (0)

+

+#define __lcd_dav_get_vds() \

+  ( (REG_LCD_DAV & LCD_DAV_VDS_MASK) >> LCD_DAV_VDS_BIT )

+#define __lcd_dav_set_vds(n) 				\

+do {							\

+	REG_LCD_DAV &= ~LCD_DAV_VDS_MASK;		\

+	REG_LCD_DAV |= (n) << LCD_DAV_VDS_BIT;		\

+} while (0)

+

+#define __lcd_dav_get_vde() \

+  ( (REG_LCD_DAV & LCD_DAV_VDE_MASK) >> LCD_DAV_VDE_BIT )

+#define __lcd_dav_set_vde(n) 				\

+do {							\

+	REG_LCD_DAV &= ~LCD_DAV_VDE_MASK;		\

+	REG_LCD_DAV |= (n) << LCD_DAV_VDE_BIT;		\

+} while (0)

+

+/* DMA Command Register */

+#define __lcd_cmd0_set_sofint()		( REG_LCD_CMD0 |= LCD_CMD_SOFINT )

+#define __lcd_cmd0_clr_sofint()		( REG_LCD_CMD0 &= ~LCD_CMD_SOFINT )

+#define __lcd_cmd1_set_sofint()		( REG_LCD_CMD1 |= LCD_CMD_SOFINT )

+#define __lcd_cmd1_clr_sofint()		( REG_LCD_CMD1 &= ~LCD_CMD_SOFINT )

+

+#define __lcd_cmd0_set_eofint()		( REG_LCD_CMD0 |= LCD_CMD_EOFINT )

+#define __lcd_cmd0_clr_eofint()		( REG_LCD_CMD0 &= ~LCD_CMD_EOFINT )

+#define __lcd_cmd1_set_eofint()		( REG_LCD_CMD1 |= LCD_CMD_EOFINT )

+#define __lcd_cmd1_clr_eofint()		( REG_LCD_CMD1 &= ~LCD_CMD_EOFINT )

+

+#define __lcd_cmd0_set_pal()		( REG_LCD_CMD0 |= LCD_CMD_PAL )

+#define __lcd_cmd0_clr_pal()		( REG_LCD_CMD0 &= ~LCD_CMD_PAL )

+

+#define __lcd_cmd0_get_len() \

+  ( (REG_LCD_CMD0 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT )

+#define __lcd_cmd1_get_len() \

+  ( (REG_LCD_CMD1 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT )

+

+

+#endif /* __MIPS_ASSEMBLER */

+

+#endif /* __JZ4760BLCDC_H__ */

+

diff --git a/arch/mips/include/asm/mach-jz4760b/jz4760bmc.h b/arch/mips/include/asm/mach-jz4760b/jz4760bmc.h
new file mode 100644
index 00000000000..21539e4d45a
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4760b/jz4760bmc.h
@@ -0,0 +1,128 @@
+/*

+ * jz4760bmc.h

+ * JZ4760B MC register definition

+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

+ *

+ * Author: whxu@ingenic.cn

+ */

+

+#ifndef __JZ4760BMC_H__

+#define __JZ4760BMC_H__

+

+

+/*

+ * Motion compensation module(MC) address definition

+ */

+#define	MC_BASE		0xb3250000

+

+

+/*

+ * MC registers offset address definition

+ */

+#define MC_MCCR_OFFSET		(0x00)	/* rw, 32, 0x???????? */

+#define MC_MCSR_OFFSET		(0x04)	/* rw, 32, 0x???????? */

+#define MC_MCRBAR_OFFSET	(0x08)	/* rw, 32, 0x???????? */

+#define MC_MCT1LFCR_OFFSET	(0x0c)	/* rw, 32, 0x???????? */

+#define MC_MCT2LFCR_OFFSET	(0x10)	/* rw, 32, 0x???????? */

+#define MC_MCCBAR_OFFSET	(0x14)	/* rw, 32, 0x???????? */

+#define MC_MCIIR_OFFSET		(0x18)	/* rw, 32, 0x???????? */

+#define MC_MCSIR_OFFSET		(0x1c)	/* rw, 32, 0x???????? */

+#define MC_MCT1MFCR_OFFSET	(0x20)	/* rw, 32, 0x???????? */

+#define MC_MCT2MFCR_OFFSET	(0x24)	/* rw, 32, 0x???????? */

+#define MC_MCFGIR_OFFSET	(0x28)	/* rw, 32, 0x???????? */

+#define MC_MCFCIR_OFFSET	(0x2c)	/* rw, 32, 0x???????? */

+#define MC_MCRNDTR_OFFSET	(0x40)	/* rw, 32, 0x???????? */

+

+#define MC_MC2CR_OFFSET		(0x8000)	/* rw, 32, 0x???????? */

+#define MC_MC2SR_OFFSET		(0x8004)	/* rw, 32, 0x???????? */

+#define MC_MC2RBAR_OFFSET	(0x8008)	/* rw, 32, 0x???????? */

+#define MC_MC2CBAR_OFFSET	(0x800c)	/* rw, 32, 0x???????? */

+#define MC_MC2IIR_OFFSET	(0x8010)	/* rw, 32, 0x???????? */

+#define MC_MC2TFCR_OFFSET	(0x8014)	/* rw, 32, 0x???????? */

+#define MC_MC2SIR_OFFSET	(0x8018)	/* rw, 32, 0x???????? */

+#define MC_MC2FCIR_OFFSET	(0x801c)	/* rw, 32, 0x???????? */

+#define MC_MC2RNDTR_OFFSET	(0x8040)	/* rw, 32, 0x???????? */

+

+

+/*

+ * MC registers address definition

+ */

+#define MC_MCCR		(MC_BASE + MC_MCCR_OFFSET)

+#define MC_MCSR		(MC_BASE + MC_MCSR_OFFSET)

+#define MC_MCRBAR	(MC_BASE + MC_MCRBAR_OFFSET)

+#define MC_MCT1LFCR	(MC_BASE + MC_MCT1LFCR_OFFSET)

+#define MC_MCT2LFCR	(MC_BASE + MC_MCT2LFCR_OFFSET)

+#define MC_MCCBAR	(MC_BASE + MC_MCCBAR_OFFSET)

+#define MC_MCIIR	(MC_BASE + MC_MCIIR_OFFSET)

+#define MC_MCSIR	(MC_BASE + MC_MCSIR_OFFSET)

+#define MC_MCT1MFCR	(MC_BASE + MC_MCT1MFCR_OFFSET)

+#define MC_MCT2MFCR	(MC_BASE + MC_MCT2MFCR_OFFSET)

+#define MC_MCFGIR	(MC_BASE + MC_MCFGIR_OFFSET)

+#define MC_MCFCIR	(MC_BASE + MC_MCFCIR_OFFSET)

+#define MC_MCRNDTR	(MC_BASE + MC_MCRNDTR_OFFSET)

+

+#define MC_MC2CR	(MC_BASE + MC_MC2CR_OFFSET)

+#define MC_MC2SR	(MC_BASE + MC_MC2SR_OFFSET)

+#define MC_MC2RBAR	(MC_BASE + MC_MC2RBAR_OFFSET)

+#define MC_MC2CBAR	(MC_BASE + MC_MC2CBAR_OFFSET)

+#define MC_MC2IIR	(MC_BASE + MC_MC2IIR_OFFSET)

+#define MC_MC2TFCR	(MC_BASE + MC_MC2TFCR_OFFSET)

+#define MC_MC2SIR	(MC_BASE + MC_MC2SIR_OFFSET)

+#define MC_MC2FCIR	(MC_BASE + MC_MC2FCIR_OFFSET)

+#define MC_MC2RNDTR	(MC_BASE + MC_MC2RNDTR_OFFSET)

+

+

+/*

+ * MC registers common define

+ */

+

+/* MC Control Register(MCCR) */

+#define MCCR_RETE		BIT16

+#define MCCR_DIPE		BIT7

+#define MCCR_CKGEN		BIT6

+#define MCCR_FDDEN		BIT5

+#define MCCR_DINSE		BIT3

+#define MCCR_FAE		BIT2

+#define MCCR_RST		BIT1

+#define MCCR_CHEN		BIT0

+

+#define MCCR_FDDPGN_LSB		8

+#define MCCR_FDDPGN_MASK	BITS_H2L(15, MCCR_FDDPGN_LSB)

+

+/* MC Status Register(MCSR) */

+#define MCSR_DLEND		BIT1

+#define MCSR_BKLEND		BIT0

+

+

+#ifndef __MIPS_ASSEMBLER

+

+

+#define REG_MC_MCCR		REG32(REG_MC_MCCR)

+#define REG_MC_MCSR             REG32(REG_MC_MCSR)

+#define REG_MC_MCRBAR           REG32(REG_MC_MCRBAR)

+#define REG_MC_MCT1LFCR         REG32(REG_MC_MCT1LFCR)

+#define REG_MC_MCT2LFCR         REG32(REG_MC_MCT2LFCR)

+#define REG_MC_MCCBAR           REG32(REG_MC_MCCBAR)

+#define REG_MC_MCIIR            REG32(REG_MC_MCIIR)

+#define REG_MC_MCSIR            REG32(REG_MC_MCSIR)

+#define REG_MC_MCT1MFCR         REG32(REG_MC_MCT1MFCR)

+#define REG_MC_MCT2MFCR         REG32(REG_MC_MCT2MFCR)

+#define REG_MC_MCFGIR           REG32(REG_MC_MCFGIR)

+#define REG_MC_MCFCIR           REG32(REG_MC_MCFCIR)

+#define REG_MC_MCRNDTR          REG32(REG_MC_MCRNDTR)

+

+#define REG_MC_MC2CR            REG32(REG_MC_MC2CR)

+#define REG_MC_MC2SR            REG32(REG_MC_MC2SR)

+#define REG_MC_MC2RBAR          REG32(REG_MC_MC2RBAR)

+#define REG_MC_MC2CBAR          REG32(REG_MC_MC2CBAR)

+#define REG_MC_MC2IIR           REG32(REG_MC_MC2IIR)

+#define REG_MC_MC2TFCR          REG32(REG_MC_MC2TFCR)

+#define REG_MC_MC2SIR           REG32(REG_MC_MC2SIR)

+#define REG_MC_MC2FCIR          REG32(REG_MC_MC2FCIR)

+#define REG_MC_MC2RNDTR         REG32(REG_MC_MC2RNDTR)

+

+

+#endif /* __MIPS_ASSEMBLER */

+

+#endif /* __JZ4760BMC_H__ */

+

diff --git a/arch/mips/include/asm/mach-jz4760b/jz4760bmdma.h b/arch/mips/include/asm/mach-jz4760b/jz4760bmdma.h
new file mode 100644
index 00000000000..153a1619eb9
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4760b/jz4760bmdma.h
@@ -0,0 +1,209 @@
+/*

+ * linux/include/asm-mips/mach-jz4760b/jz4760bmdma.h

+ *

+ * JZ4760B MDMA register definition.

+ *

+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

+ */

+

+#ifndef __JZ4760BMDMA_H__

+#define __JZ4760BMDMA_H__

+

+

+#define	MDMAC_BASE	0xB3030000 /* Memory Copy DMAC */

+

+/*************************************************************************

+ * MDMAC (MEM Copy DMA Controller)

+ *************************************************************************/

+

+/* m is the DMA controller index (0, 1), n is the DMA channel index (0 - 11) */

+

+#define MDMAC_DSAR(n)		(MDMAC_BASE + (0x00 + (n) * 0x20)) /* DMA source address */

+#define MDMAC_DTAR(n)  		(MDMAC_BASE + (0x04 + (n) * 0x20)) /* DMA target address */

+#define MDMAC_DTCR(n)  		(MDMAC_BASE + (0x08 + (n) * 0x20)) /* DMA transfer count */

+#define MDMAC_DRSR(n)  		(MDMAC_BASE + (0x0c + (n) * 0x20)) /* DMA request source */

+#define MDMAC_DCCSR(n) 		(MDMAC_BASE + (0x10 + (n) * 0x20)) /* DMA control/status */

+#define MDMAC_DCMD(n)  		(MDMAC_BASE + (0x14 + (n) * 0x20)) /* DMA command */

+#define MDMAC_DDA(n)   		(MDMAC_BASE + (0x18 + (n) * 0x20)) /* DMA descriptor address */

+#define MDMAC_DSD(n)   		(MDMAC_BASE + (0xc0 + (n) * 0x04)) /* DMA Stride Address */

+

+#define MDMAC_DMACR		(MDMAC_BASE + 0x0300) /* DMA control register */

+#define MDMAC_DMAIPR		(MDMAC_BASE + 0x0304) /* DMA interrupt pending */

+#define MDMAC_DMADBR		(MDMAC_BASE + 0x0308) /* DMA doorbell */

+#define MDMAC_DMADBSR		(MDMAC_BASE + 0x030C) /* DMA doorbell set */

+#define MDMAC_DMACKE  		(MDMAC_BASE + 0x0310)

+

+#define REG_MDMAC_DSAR(n)	REG32(MDMAC_DSAR((n)))

+#define REG_MDMAC_DTAR(n)	REG32(MDMAC_DTAR((n)))

+#define REG_MDMAC_DTCR(n)	REG32(MDMAC_DTCR((n)))

+#define REG_MDMAC_DRSR(n)	REG32(MDMAC_DRSR((n)))

+#define REG_MDMAC_DCCSR(n)	REG32(MDMAC_DCCSR((n)))

+#define REG_MDMAC_DCMD(n)	REG32(MDMAC_DCMD((n)))

+#define REG_MDMAC_DDA(n)	REG32(MDMAC_DDA((n)))

+#define REG_MDMAC_DSD(n)        REG32(MDMAC_DSD(n))

+#define REG_MDMAC_DMACR		REG32(MDMAC_DMACR)

+#define REG_MDMAC_DMAIPR	REG32(MDMAC_DMAIPR)

+#define REG_MDMAC_DMADBR	REG32(MDMAC_DMADBR)

+#define REG_MDMAC_DMADBSR	REG32(MDMAC_DMADBSR)

+#define REG_MDMAC_DMACKE     	REG32(MDMAC_DMACKE)

+

+#ifndef __MIPS_ASSEMBLER

+

+/***************************************************************************

+ * Mem Copy DMAC

+ ***************************************************************************/

+

+/* n is the DMA channel index (0 - 11) */

+

+#define __mdmac_enable_module \

+	( REG_MDMAC_DMACR |= DMAC_MDMACR_DMAE | DMAC_MDMACR_PR_012345 )

+#define __mdmac_disable_module \

+	( REG_MDMAC_DMACR &= ~DMAC_MDMACR_DMAE )

+

+/* p=0,1,2,3 */

+#define __mdmac_set_priority(p)			\

+do {							\

+	REG_MDMAC_DMACR &= ~DMAC_DMACR_PR_MASK;	\

+	REG_MDMAC_DMACR |= ((p) << DMAC_DMACR_PR_BIT);	\

+} while (0)

+

+#define __mdmac_test_halt_error ( REG_MDMAC_DMACR & DMAC_MDMACR_HLT )

+#define __mdmac_test_addr_error ( REG_MDMAC_DMACR & DMAC_MDMACR_AR )

+

+#define __mdmac_channel_enable_clk \

+	REG_MDMAC_DMACKE |= 1 << (n);

+

+#define __mdmac_enable_descriptor(n) \

+  ( REG_MDMAC_DCCSR((n)) &= ~DMAC_DCCSR_NDES )

+#define __mdmac_disable_descriptor(n) \

+  ( REG_MDMAC_DCCSR((n)) |= DMAC_DCCSR_NDES )

+

+#define __mdmac_enable_channel(n)                 \

+do {                                             \

+	REG_MDMAC_DCCSR((n)) |= DMAC_DCCSR_EN;    \

+} while (0)

+#define __mdmac_disable_channel(n)                \

+do {                                             \

+	REG_MDMAC_DCCSR((n)) &= ~DMAC_DCCSR_EN;   \

+} while (0)

+#define __mdmac_channel_enabled(n) \

+  ( REG_MDMAC_DCCSR((n)) & DMAC_DCCSR_EN )

+

+#define __mdmac_channel_enable_irq(n) \

+  ( REG_MDMAC_DCMD((n)) |= DMAC_DCMD_TIE )

+#define __mdmac_channel_disable_irq(n) \

+  ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_TIE )

+

+#define __mdmac_channel_transmit_halt_detected(n) \

+  (  REG_MDMAC_DCCSR((n)) & DMAC_DCCSR_HLT )

+#define __mdmac_channel_transmit_end_detected(n) \

+  (  REG_MDMAC_DCCSR((n)) & DMAC_DCCSR_TT )

+#define __mdmac_channel_address_error_detected(n) \

+  (  REG_DMAC_DCCSR((n)) & DMAC_DCCSR_AR )

+#define __mdmac_channel_count_terminated_detected(n) \

+  (  REG_MDMAC_DCCSR((n)) & DMAC_DCCSR_CT )

+#define __mdmac_channel_descriptor_invalid_detected(n) \

+  (  REG_MDMAC_DCCSR((n)) & DMAC_DCCSR_INV )

+

+#define __mdmac_channel_clear_transmit_halt(n)				\

+	do {								\

+		/* clear both channel halt error and globle halt error */ \

+		REG_MDMAC_DCCSR(n) &= ~DMAC_DCCSR_HLT;			\

+		REG_MDMAC_DMACR &= ~DMAC_DMACR_HLT;	\

+	} while (0)

+#define __mdmac_channel_clear_transmit_end(n) \

+  (  REG_MDMAC_DCCSR(n) &= ~DMAC_DCCSR_TT )

+#define __mdmac_channel_clear_address_error(n)				\

+	do {								\

+		REG_MDMAC_DDA(n) = 0; /* clear descriptor address register */ \

+		REG_MDMAC_DSAR(n) = 0; /* clear source address register */ \

+		REG_MDMAC_DTAR(n) = 0; /* clear target address register */ \

+		/* clear both channel addr error and globle address error */ \

+		REG_MDMAC_DCCSR(n) &= ~DMAC_DCCSR_AR;			\

+		REG_MDMAC_DMACR &= ~DMAC_DMACR_AR;	\

+	} while (0)

+#define __mdmac_channel_clear_count_terminated(n) \

+  (  REG_MDMAC_DCCSR((n)) &= ~DMAC_DCCSR_CT )

+#define __mdmac_channel_clear_descriptor_invalid(n) \

+  (  REG_MDMAC_DCCSR((n)) &= ~DMAC_DCCSR_INV )

+

+#define __mdmac_channel_set_transfer_unit_32bit(n)	\

+do {							\

+	REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK;	\

+	REG_MDMAC_DCMD((n)) |= DMAC_DCMD_DS_32BIT;	\

+} while (0)

+

+#define __mdmac_channel_set_transfer_unit_16bit(n)	\

+do {							\

+	REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK;	\

+	REG_MDMAC_DCMD((n)) |= DMAC_DCMD_DS_16BIT;	\

+} while (0)

+

+#define __mdmac_channel_set_transfer_unit_8bit(n)	\

+do {							\

+	REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK;	\

+	REG_MDMAC_DCMD((n)) |= DMAC_DCMD_DS_8BIT;	\

+} while (0)

+

+#define __mdmac_channel_set_transfer_unit_16byte(n)	\

+do {							\

+	REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK;	\

+	REG_MDMAC_DCMD((n)) |= DMAC_DCMD_DS_16BYTE;	\

+} while (0)

+

+#define __mdmac_channel_set_transfer_unit_32byte(n)	\

+do {							\

+	REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK;	\

+	REG_MDMAC_DCMD((n)) |= DMAC_DCMD_DS_32BYTE;	\

+} while (0)

+

+/* w=8,16,32 */

+#define __mdmac_channel_set_dest_port_width(n,w)		\

+do {							\

+	REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_DWDH_MASK;	\

+	REG_MDMAC_DCMD((n)) |= DMAC_DCMD_DWDH_##w;	\

+} while (0)

+

+/* w=8,16,32 */

+#define __mdmac_channel_set_src_port_width(n,w)		\

+do {							\

+	REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_SWDH_MASK;	\

+	REG_MDMAC_DCMD((n)) |= DMAC_DCMD_SWDH_##w;	\

+} while (0)

+

+/* v=0-15 */

+#define __mdmac_channel_set_rdil(n,v)				\

+do {								\

+	REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_RDIL_MASK;		\

+	REG_MDMAC_DCMD((n) |= ((v) << DMAC_DCMD_RDIL_BIT);	\

+} while (0)

+

+#define __mdmac_channel_dest_addr_fixed(n) \

+	(REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_DAI)

+#define __mdmac_channel_dest_addr_increment(n) \

+	(REG_MDMAC_DCMD((n)) |= DMAC_DCMD_DAI)

+

+#define __mdmac_channel_src_addr_fixed(n) \

+	(REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_SAI)

+#define __mdmac_channel_src_addr_increment(n) \

+	(REG_MDMAC_DCMD((n)) |= DMAC_DCMD_SAI)

+

+#define __mdmac_channel_set_doorbell(n)	\

+	(REG_MDMAC_DMADBSR = (1 << (n)))

+

+#define __mdmac_channel_irq_detected(n)  (REG_MDMAC_DMAIPR & (1 << (n)))

+#define __mdmac_channel_ack_irq(n)       (REG_MDMAC_DMAIPR &= ~(1 <<(n)))

+

+static __inline__ int __mdmac_get_irq(void)

+{

+	int i;

+	for (i = 0; i < MAX_MDMA_NUM; i++)

+		if (__mdmac_channel_irq_detected(i))

+			return i;

+	return -1;

+}

+

+#endif /* __MIPS_ASSEMBLER */

+

+#endif /* __JZ4760BMDMA_H__ */

+

diff --git a/arch/mips/include/asm/mach-jz4760b/jz4760bme.h b/arch/mips/include/asm/mach-jz4760b/jz4760bme.h
new file mode 100644
index 00000000000..cc72dd184e6
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4760b/jz4760bme.h
@@ -0,0 +1,93 @@
+/*

+ * jz4760bme.h

+ * JZ4760B ME register definition

+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

+ *

+ * Author: whxu@ingenic.cn

+ */

+

+#ifndef __JZ4760BME_H__

+#define __JZ4760BME_H__

+

+

+/*

+ * Motion estimation module(ME) address definition

+ */

+#define	ME_BASE		0xb3260000

+

+

+/*

+ * ME registers offset address definition

+ */

+#define ME_MECR_OFFSET		(0x00)  /* rw, 32, 0x???????0 */

+#define ME_MERBAR_OFFSET	(0x04)  /* rw, 32, 0x???????? */

+#define ME_MECBAR_OFFSET	(0x08)  /* rw, 32, 0x???????? */

+#define ME_MEDAR_OFFSET		(0x0c)  /* rw, 32, 0x???????? */

+#define ME_MERFSR_OFFSET	(0x10)  /* rw, 32, 0x???????? */

+#define ME_MECFSR_OFFSET	(0x14)  /* rw, 32, 0x???????? */

+#define ME_MEDFSR_OFFSET	(0x18)  /* rw, 32, 0x???????? */

+#define ME_MESR_OFFSET		(0x1c)  /* rw, 32, 0x???????? */

+#define ME_MEMR_OFFSET		(0x20)  /* rw, 32, 0x???????? */

+#define ME_MEFR_OFFSET		(0x24)  /* rw, 32, 0x???????? */

+

+

+/*

+ * ME registers address definition

+ */

+#define ME_MECR		(ME_BASE + ME_MECR_OFFSET)

+#define ME_MERBAR	(ME_BASE + ME_MERBAR_OFFSET)

+#define ME_MECBAR       (ME_BASE + ME_MECBAR_OFFSET)

+#define ME_MEDAR        (ME_BASE + ME_MEDAR_OFFSET)

+#define ME_MERFSR       (ME_BASE + ME_MERFSR_OFFSET)

+#define ME_MECFSR       (ME_BASE + ME_MECFSR_OFFSET)

+#define ME_MEDFSR       (ME_BASE + ME_MEDFSR_OFFSET)

+#define ME_MESR         (ME_BASE + ME_MESR_OFFSET)

+#define ME_MEMR         (ME_BASE + ME_MEMR_OFFSET)

+#define ME_MEFR         (ME_BASE + ME_MEFR_OFFSET)

+

+

+/*

+ * ME registers common define

+ */

+

+/* ME control register(MECR) */

+#define MECR_FLUSH		BIT2

+#define MECR_RESET		BIT1

+#define MECR_ENABLE		BIT0

+

+/* ME settings register(MESR) */

+#define MESR_GATE_LSB		16

+#define MESR_GATE_MASK		BITS_H2L(31, MESR_GATE_LSB)

+

+#define MESR_NUM_LSB		0

+#define MESR_NUM_MASK		BITS_H2L(5, MESR_NUM_LSB)

+

+/* ME MVD register(MEMR) */

+#define MEMR_MVDY_LSB		16

+#define MESR_MVDY_MASK		BITS_H2L(31, MEMR_MVDY_LSB)

+

+#define MEMR_MVDX_LSB		0

+#define MESR_MVDX_MASK		BITS_H2L(15, MEMR_MVDX_LSB)

+

+/* ME flag register(MEFR) */

+#define MEFR_INTRA		BIT1

+#define MEFR_COMPLETED		BIT0

+

+

+#ifndef __MIPS_ASSEMBLER

+

+#define REG_ME_MECR	REG32(ME_MECR)

+#define REG_ME_MERBAR	REG32(ME_MERBAR)

+#define REG_ME_MECBAR	REG32(ME_MECBAR)

+#define REG_ME_MEDAR	REG32(ME_MEDAR)

+#define REG_ME_MERFSR	REG32(ME_MERFSR)

+#define REG_ME_MECFSR	REG32(ME_MECFSR)

+#define REG_ME_MEDFSR	REG32(ME_MEDFSR)

+#define REG_ME_MESR	REG32(ME_MESR)

+#define REG_ME_MEMR	REG32(ME_MEMR)

+#define REG_ME_MEFR	REG32(ME_MEFR)

+

+#endif /* __MIPS_ASSEMBLER */

+

+#endif /* __JZ4760BME_H__ */

+

diff --git a/arch/mips/include/asm/mach-jz4760b/jz4760bmisc.h b/arch/mips/include/asm/mach-jz4760b/jz4760bmisc.h
new file mode 100644
index 00000000000..d7c401b8f83
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4760b/jz4760bmisc.h
@@ -0,0 +1,91 @@
+/*

+ * linux/include/asm-mips/mach-jz4760b/jz4760bmisc.h

+ *

+ * JZ4760B misc definition.

+ *

+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

+ */

+

+#ifndef __JZ4760BMISC_H__

+#define __JZ4760BMISC_H__

+

+

+#if defined(__ASSEMBLY__) || defined(__LANGUAGE_ASSEMBLY)

+        #ifndef __MIPS_ASSEMBLER

+                #define __MIPS_ASSEMBLER

+        #endif

+        #define REG8(addr)	(addr)

+        #define REG16(addr)	(addr)

+        #define REG32(addr)	(addr)

+#else

+        #define REG8(addr)	*((volatile unsigned char *)(addr))

+        #define REG16(addr)	*((volatile unsigned short *)(addr))

+        #define REG32(addr)	*((volatile unsigned int *)(addr))

+

+        #define INREG8(x)               ((unsigned char)(*(volatile unsigned char *)(x)))

+        #define OUTREG8(x, y)           *(volatile unsigned char *)(x) = (y)

+        #define SETREG8(x, y)           OUTREG8(x, INREG8(x)|(y))

+        #define CLRREG8(x, y)           OUTREG8(x, INREG8(x)&~(y))

+        #define CMSREG8(x, y, m)        OUTREG8(x, (INREG8(x)&~(m))|(y))

+

+        #define INREG16(x)              ((unsigned short)(*(volatile unsigned short *)(x)))

+        #define OUTREG16(x, y)          *(volatile unsigned short *)(x) = (y)

+        #define SETREG16(x, y)          OUTREG16(x, INREG16(x)|(y))

+        #define CLRREG16(x, y)          OUTREG16(x, INREG16(x)&~(y))

+        #define CMSREG16(x, y, m)       OUTREG16(x, (INREG16(x)&~(m))|(y))

+

+        #define INREG32(x)              ((unsigned int)(*(volatile unsigned int *)(x)))

+        #define OUTREG32(x, y)          *(volatile unsigned int *)(x) = (y)

+        #define SETREG32(x, y)          OUTREG32(x, INREG32(x)|(y))

+        #define CLRREG32(x, y)          OUTREG32(x, INREG32(x)&~(y))

+        #define CMSREG32(x, y, m)       OUTREG32(x, (INREG32(x)&~(m))|(y))

+

+#endif

+

+

+/*

+ * Define the bit field macro to avoid the bit mistake

+ */

+#define BIT0            (1 << 0)

+#define BIT1            (1 << 1)

+#define BIT2            (1 << 2)

+#define BIT3            (1 << 3)

+#define BIT4            (1 << 4)

+#define BIT5            (1 << 5)

+#define BIT6            (1 << 6)

+#define BIT7            (1 << 7)

+#define BIT8            (1 << 8)

+#define BIT9            (1 << 9)

+#define BIT10           (1 << 10)

+#define BIT11           (1 << 11)

+#define BIT12 	        (1 << 12)

+#define BIT13 	        (1 << 13)

+#define BIT14 	        (1 << 14)

+#define BIT15 	        (1 << 15)

+#define BIT16 	        (1 << 16)

+#define BIT17 	        (1 << 17)

+#define BIT18 	        (1 << 18)

+#define BIT19 	        (1 << 19)

+#define BIT20 	        (1 << 20)

+#define BIT21 	        (1 << 21)

+#define BIT22 	        (1 << 22)

+#define BIT23 	        (1 << 23)

+#define BIT24 	        (1 << 24)

+#define BIT25 	        (1 << 25)

+#define BIT26 	        (1 << 26)

+#define BIT27 	        (1 << 27)

+#define BIT28 	        (1 << 28)

+#define BIT29 	        (1 << 29)

+#define BIT30 	        (1 << 30)

+#define BIT31 	        (1 << 31)

+

+

+/* Generate the bit field mask from msb to lsb */

+#define BITS_H2L(msb, lsb)  ((0xFFFFFFFF >> (32-((msb)-(lsb)+1))) << (lsb))

+

+

+/* Get the bit field value from the data which is read from the register */

+#define get_bf_value(data, lsb, mask)  (((data) & (mask)) >> (lsb))

+

+

+#endif /* __JZ4760BMISC_H__ */

diff --git a/arch/mips/include/asm/mach-jz4760b/jz4760bmsc.h b/arch/mips/include/asm/mach-jz4760b/jz4760bmsc.h
new file mode 100644
index 00000000000..4424c75fc97
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4760b/jz4760bmsc.h
@@ -0,0 +1,329 @@
+/*

+ * linux/include/asm-mips/mach-jz4760b/jz4760bmsc.h

+ *

+ * JZ4760B MSC register definition.

+ *

+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

+ */

+

+#ifndef __JZ4760BMSC_H__

+#define __JZ4760BMSC_H__

+

+#define JZ_MAX_MSC_NUM 3

+

+#define JZ_MSC_ID_INVALID(msc_id) ( ((msc_id) < 0) || ( (msc_id) > JZ_MAX_MSC_NUM ) )

+

+#define	MSC0_BASE	0xB0021000

+#define	MSC1_BASE	0xB0022000

+#define	MSC2_BASE	0xB0023000

+

+#define	MSC_STRPCL(n)		(MSC0_BASE + (n)*0x1000 + 0x000)

+#define	MSC_STAT(n)		(MSC0_BASE + (n)*0x1000 + 0x004)

+#define	MSC_CLKRT(n)		(MSC0_BASE + (n)*0x1000 + 0x008)

+#define	MSC_CMDAT(n)		(MSC0_BASE + (n)*0x1000 + 0x00C)

+#define	MSC_RESTO(n)		(MSC0_BASE + (n)*0x1000 + 0x010)

+#define	MSC_RDTO(n)		(MSC0_BASE + (n)*0x1000 + 0x014)

+#define	MSC_BLKLEN(n)		(MSC0_BASE + (n)*0x1000 + 0x018)

+#define	MSC_NOB(n)		(MSC0_BASE + (n)*0x1000 + 0x01C)

+#define	MSC_SNOB(n)		(MSC0_BASE + (n)*0x1000 + 0x020)

+#define	MSC_IMASK(n)		(MSC0_BASE + (n)*0x1000 + 0x024)

+#define	MSC_IREG(n)		(MSC0_BASE + (n)*0x1000 + 0x028)

+#define	MSC_CMD(n)		(MSC0_BASE + (n)*0x1000 + 0x02C)

+#define	MSC_ARG(n)		(MSC0_BASE + (n)*0x1000 + 0x030)

+#define	MSC_RES(n)		(MSC0_BASE + (n)*0x1000 + 0x034)

+#define	MSC_RXFIFO(n)		(MSC0_BASE + (n)*0x1000 + 0x038)

+#define	MSC_TXFIFO(n)		(MSC0_BASE + (n)*0x1000 + 0x03C)

+#define	MSC_LPM(n)		(MSC0_BASE + (n)*0x1000 + 0x040)

+

+#define	REG_MSC_STRPCL(n)	REG16(MSC_STRPCL(n))

+#define	REG_MSC_STAT(n)		REG32(MSC_STAT(n))

+#define	REG_MSC_CLKRT(n)	REG16(MSC_CLKRT(n))

+#define	REG_MSC_CMDAT(n)	REG32(MSC_CMDAT(n))

+#define	REG_MSC_RESTO(n)	REG16(MSC_RESTO(n))

+#define	REG_MSC_RDTO(n)		REG32(MSC_RDTO(n))

+#define	REG_MSC_BLKLEN(n)	REG16(MSC_BLKLEN(n))

+#define	REG_MSC_NOB(n)		REG16(MSC_NOB(n))

+#define	REG_MSC_SNOB(n)		REG16(MSC_SNOB(n))

+#define	REG_MSC_IMASK(n)	REG32(MSC_IMASK(n))

+#define	REG_MSC_IREG(n)		REG16(MSC_IREG(n))

+#define	REG_MSC_CMD(n)		REG8(MSC_CMD(n))

+#define	REG_MSC_ARG(n)		REG32(MSC_ARG(n))

+#define	REG_MSC_RES(n)		REG16(MSC_RES(n))

+#define	REG_MSC_RXFIFO(n)	REG32(MSC_RXFIFO(n))

+#define	REG_MSC_TXFIFO(n)	REG32(MSC_TXFIFO(n))

+#define	REG_MSC_LPM(n)		REG32(MSC_LPM(n))

+

+/* MSC Clock and Control Register (MSC_STRPCL) */

+#define MSC_STRPCL_SEND_CCSD		(1 << 15) /*send command completion signal disable to ceata */

+#define MSC_STRPCL_SEND_AS_CCSD		(1 << 14) /*send internally generated stop after sending ccsd */

+#define MSC_STRPCL_EXIT_MULTIPLE	(1 << 7)

+#define MSC_STRPCL_EXIT_TRANSFER	(1 << 6)

+#define MSC_STRPCL_START_READWAIT	(1 << 5)

+#define MSC_STRPCL_STOP_READWAIT	(1 << 4)

+#define MSC_STRPCL_RESET		(1 << 3)

+#define MSC_STRPCL_START_OP		(1 << 2)

+#define MSC_STRPCL_CLOCK_CONTROL_BIT	0

+#define MSC_STRPCL_CLOCK_CONTROL_MASK	(0x3 << MSC_STRPCL_CLOCK_CONTROL_BIT)

+#define MSC_STRPCL_CLOCK_CONTROL_STOP	  (0x1 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Stop MMC/SD clock */

+#define MSC_STRPCL_CLOCK_CONTROL_START  (0x2 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Start MMC/SD clock */

+

+/* MSC Status Register (MSC_STAT) */

+#define MSC_STAT_AUTO_CMD_DONE		(1 << 31) /*12 is internally generated by controller has finished */

+#define MSC_STAT_IS_RESETTING		(1 << 15)

+#define MSC_STAT_SDIO_INT_ACTIVE	(1 << 14)

+#define MSC_STAT_PRG_DONE		(1 << 13)

+#define MSC_STAT_DATA_TRAN_DONE		(1 << 12)

+#define MSC_STAT_END_CMD_RES		(1 << 11)

+#define MSC_STAT_DATA_FIFO_AFULL	(1 << 10)

+#define MSC_STAT_IS_READWAIT		(1 << 9)

+#define MSC_STAT_CLK_EN			(1 << 8)

+#define MSC_STAT_DATA_FIFO_FULL		(1 << 7)

+#define MSC_STAT_DATA_FIFO_EMPTY	(1 << 6)

+#define MSC_STAT_CRC_RES_ERR		(1 << 5)

+#define MSC_STAT_CRC_READ_ERROR		(1 << 4)

+#define MSC_STAT_CRC_WRITE_ERROR_BIT	2

+#define MSC_STAT_CRC_WRITE_ERROR_MASK	(0x3 << MSC_STAT_CRC_WRITE_ERROR_BIT)

+#define MSC_STAT_CRC_WRITE_ERROR_NO	(0 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No error on transmission of data */

+#define MSC_STAT_CRC_WRITE_ERROR	(1 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* Card observed erroneous transmission of data */

+#define MSC_STAT_CRC_WRITE_ERROR_NOSTS	(2 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No CRC status is sent back */

+#define MSC_STAT_TIME_OUT_RES		(1 << 1)

+#define MSC_STAT_TIME_OUT_READ		(1 << 0)

+

+/* MSC Bus Clock Control Register (MSC_CLKRT) */

+#define	MSC_CLKRT_CLK_RATE_BIT		0

+#define	MSC_CLKRT_CLK_RATE_MASK		(0x7 << MSC_CLKRT_CLK_RATE_BIT)

+#define MSC_CLKRT_CLK_RATE_DIV_1	(0x0 << MSC_CLKRT_CLK_RATE_BIT) /* CLK_SRC */

+#define MSC_CLKRT_CLK_RATE_DIV_2	(0x1 << MSC_CLKRT_CLK_RATE_BIT) /* 1/2 of CLK_SRC */

+#define MSC_CLKRT_CLK_RATE_DIV_4	(0x2 << MSC_CLKRT_CLK_RATE_BIT) /* 1/4 of CLK_SRC */

+#define MSC_CLKRT_CLK_RATE_DIV_8	(0x3 << MSC_CLKRT_CLK_RATE_BIT) /* 1/8 of CLK_SRC */

+#define MSC_CLKRT_CLK_RATE_DIV_16	(0x4 << MSC_CLKRT_CLK_RATE_BIT) /* 1/16 of CLK_SRC */

+#define MSC_CLKRT_CLK_RATE_DIV_32	(0x5 << MSC_CLKRT_CLK_RATE_BIT) /* 1/32 of CLK_SRC */

+#define MSC_CLKRT_CLK_RATE_DIV_64	(0x6 << MSC_CLKRT_CLK_RATE_BIT) /* 1/64 of CLK_SRC */

+#define MSC_CLKRT_CLK_RATE_DIV_128	(0x7 << MSC_CLKRT_CLK_RATE_BIT) /* 1/128 of CLK_SRC */

+

+/* MSC Command Sequence Control Register (MSC_CMDAT) */

+#define	MSC_CMDAT_CCS_EXPECTED		(1 << 31) /* interrupts are enabled in ce-ata */

+#define	MSC_CMDAT_READ_CEATA		(1 << 30)

+#define	MSC_CMDAT_SDIO_PRDT		(1 << 17) /* exact 2 cycle */

+#define	MSC_CMDAT_SEND_AS_STOP		(1 << 16)

+#define	MSC_CMDAT_RTRG_BIT		14

+#define MSC_CMDAT_RTRG_EQUALT_8		(0x0 << MSC_CMDAT_RTRG_BIT)

+#define MSC_CMDAT_RTRG_EQUALT_16	(0x1 << MSC_CMDAT_RTRG_BIT) /* reset value */

+#define MSC_CMDAT_RTRG_EQUALT_24	(0x2 << MSC_CMDAT_RTRG_BIT)

+#define	MSC_CMDAT_TTRG_BIT		12

+#define MSC_CMDAT_TTRG_LESS_8		(0x0 << MSC_CMDAT_TTRG_BIT)

+#define MSC_CMDAT_TTRG_LESS_16		(0x1 << MSC_CMDAT_TTRG_BIT) /*reset value  */

+#define MSC_CMDAT_TTRG_LESS_24		(0x2 << MSC_CMDAT_TTRG_BIT)

+#define	MSC_CMDAT_STOP_ABORT		(1 << 11)

+#define	MSC_CMDAT_BUS_WIDTH_BIT		9

+#define	MSC_CMDAT_BUS_WIDTH_MASK	(0x3 << MSC_CMDAT_BUS_WIDTH_BIT)

+#define MSC_CMDAT_BUS_WIDTH_1BIT	(0x0 << MSC_CMDAT_BUS_WIDTH_BIT) /* 1-bit data bus */

+#define MSC_CMDAT_BUS_WIDTH_4BIT	(0x2 << MSC_CMDAT_BUS_WIDTH_BIT) /* 4-bit data bus */

+#define MSC_CMDAT_BUS_WIDTH_8BIT	(0x3 << MSC_CMDAT_BUS_WIDTH_BIT) /* 8-bit data bus */

+#define	MSC_CMDAT_DMA_EN		(1 << 8)

+#define	MSC_CMDAT_INIT			(1 << 7)

+#define	MSC_CMDAT_BUSY			(1 << 6)

+#define	MSC_CMDAT_STREAM_BLOCK		(1 << 5)

+#define	MSC_CMDAT_WRITE			(1 << 4)

+#define	MSC_CMDAT_READ			(0 << 4)

+#define	MSC_CMDAT_DATA_EN		(1 << 3)

+#define	MSC_CMDAT_RESPONSE_BIT	0

+#define	MSC_CMDAT_RESPONSE_MASK	(0x7 << MSC_CMDAT_RESPONSE_BIT)

+#define MSC_CMDAT_RESPONSE_NONE (0x0 << MSC_CMDAT_RESPONSE_BIT) /* No response */

+#define MSC_CMDAT_RESPONSE_R1	  (0x1 << MSC_CMDAT_RESPONSE_BIT) /* Format R1 and R1b */

+#define MSC_CMDAT_RESPONSE_R2	  (0x2 << MSC_CMDAT_RESPONSE_BIT) /* Format R2 */

+#define MSC_CMDAT_RESPONSE_R3	  (0x3 << MSC_CMDAT_RESPONSE_BIT) /* Format R3 */

+#define MSC_CMDAT_RESPONSE_R4	  (0x4 << MSC_CMDAT_RESPONSE_BIT) /* Format R4 */

+#define MSC_CMDAT_RESPONSE_R5	  (0x5 << MSC_CMDAT_RESPONSE_BIT) /* Format R5 */

+#define MSC_CMDAT_RESPONSE_R6	  (0x6 << MSC_CMDAT_RESPONSE_BIT) /* Format R6 */

+

+/* MSC Interrupts Mask Register (MSC_IMASK) */

+#define	MSC_IMASK_AUTO_CMD_DONE		BIT15

+#define MSC_IMASK_DATA_FIFO_FULL	BIT14

+#define MSC_IMASK_DATA_FIFO_EMP		BIT13

+#define MSC_IMASK_CRC_RES_ERR		BIT12

+#define MSC_IMASK_CRC_READ_ERR		BIT11

+#define MSC_IMASK_CRC_WRITE_ERR		BIT10

+#define MSC_IMASK_TIMEOUT_RES		BIT9

+#define MSC_IMASK_TIMEOUT_READ		BIT8

+#define	MSC_IMASK_SDIO			BIT7

+#define	MSC_IMASK_TXFIFO_WR_REQ		BIT6

+#define	MSC_IMASK_RXFIFO_RD_REQ		BIT5

+#define	MSC_IMASK_END_CMD_RES		BIT2

+#define	MSC_IMASK_PRG_DONE		BIT1

+#define	MSC_IMASK_DATA_TRAN_DONE	BIT0

+

+/* MSC Interrupts Status Register (MSC_IREG) */

+#define	MSC_IREG_AUTO_CMD_DONE		BIT15

+#define MSC_IREG_DATA_FIFO_FULL		BIT14

+#define MSC_IREG_DATA_FIFO_EMP		BIT13

+#define MSC_IREG_CRC_RES_ERR		BIT12

+#define MSC_IREG_CRC_READ_ERR		BIT11

+#define MSC_IREG_CRC_WRITE_ERR		BIT10

+#define MSC_IREG_TIMEOUT_RES		BIT9

+#define MSC_IREG_TIMEOUT_READ		BIT8

+#define	MSC_IREG_SDIO			BIT7

+#define	MSC_IREG_TXFIFO_WR_REQ		BIT6

+#define	MSC_IREG_RXFIFO_RD_REQ		BIT5

+#define	MSC_IREG_END_CMD_RES		BIT2

+#define	MSC_IREG_PRG_DONE		BIT1

+#define	MSC_IREG_DATA_TRAN_DONE		BIT0

+

+/* MSC Low Power Mode Register (MSC_LPM) */

+#define	MSC_SET_LPM			(1 << 0)

+

+

+#ifndef __MIPS_ASSEMBLER

+

+/***************************************************************************

+ * MSC

+ ***************************************************************************/

+/* n = 0, 1 (MSC0, MSC1) */

+

+#define __msc_start_op(n)						\

+	( REG_MSC_STRPCL(n) = MSC_STRPCL_START_OP | MSC_STRPCL_CLOCK_CONTROL_START )

+

+#define __msc_set_resto(n, to)  	( REG_MSC_RESTO(n) = to )

+#define __msc_set_rdto(n, to)   	( REG_MSC_RDTO(n) = to )

+#define __msc_set_cmd(n, cmd)   	( REG_MSC_CMD(n) = cmd )

+#define __msc_set_arg(n, arg)   	( REG_MSC_ARG(n) = arg )

+#define __msc_set_nob(n, nob)      	( REG_MSC_NOB(n) = nob )

+#define __msc_get_nob(n)        	( REG_MSC_NOB(n) )

+#define __msc_set_blklen(n, len)        ( REG_MSC_BLKLEN(n) = len )

+#define __msc_set_cmdat(n, cmdat)   	( REG_MSC_CMDAT(n) = cmdat )

+#define __msc_set_cmdat_ioabort(n) 	( REG_MSC_CMDAT(n) |= MSC_CMDAT_IO_ABORT )

+#define __msc_clear_cmdat_ioabort(n) 	( REG_MSC_CMDAT(n) &= ~MSC_CMDAT_IO_ABORT )

+

+#define __msc_set_cmdat_bus_width1(n)				\

+	do { 							\

+		REG_MSC_CMDAT(n) &= ~MSC_CMDAT_BUS_WIDTH_MASK; 	\

+		REG_MSC_CMDAT(n) |= MSC_CMDAT_BUS_WIDTH_1BIT; 	\

+	} while(0)

+

+#define __msc_set_cmdat_bus_width4(n)				\

+	do { 							\

+		REG_MSC_CMDAT(n) &= ~MSC_CMDAT_BUS_WIDTH_MASK; 	\

+		REG_MSC_CMDAT(n) |= MSC_CMDAT_BUS_WIDTH_4BIT; 	\

+	} while(0)

+

+#define __msc_set_cmdat_dma_en(n)       ( REG_MSC_CMDAT(n) |= MSC_CMDAT_DMA_EN )

+#define __msc_set_cmdat_init(n) 	( REG_MSC_CMDAT(n) |= MSC_CMDAT_INIT )

+#define __msc_set_cmdat_busy(n) 	( REG_MSC_CMDAT(n) |= MSC_CMDAT_BUSY )

+#define __msc_set_cmdat_stream(n)       ( REG_MSC_CMDAT(n) |= MSC_CMDAT_STREAM_BLOCK )

+#define __msc_set_cmdat_block(n)        ( REG_MSC_CMDAT(n) &= ~MSC_CMDAT_STREAM_BLOCK )

+#define __msc_set_cmdat_read(n) 	( REG_MSC_CMDAT(n) &= ~MSC_CMDAT_WRITE_READ )

+#define __msc_set_cmdat_write(n)        ( REG_MSC_CMDAT(n) |= MSC_CMDAT_WRITE_READ )

+#define __msc_set_cmdat_data_en(n)      ( REG_MSC_CMDAT(n) |= MSC_CMDAT_DATA_EN )

+

+/* r is MSC_CMDAT_RESPONSE_FORMAT_Rx or MSC_CMDAT_RESPONSE_FORMAT_NONE */

+#define __msc_set_cmdat_res_format(n, r)				\

+	do { 								\

+		REG_MSC_CMDAT(n) &= ~MSC_CMDAT_RESPONSE_FORMAT_MASK; 	\

+		REG_MSC_CMDAT(n) |= (r);				\

+	} while(0)

+

+#define __msc_clear_cmdat(n)						\

+	REG_MSC_CMDAT(n) &= ~( MSC_CMDAT_IO_ABORT | MSC_CMDAT_DMA_EN | MSC_CMDAT_INIT| \

+			       MSC_CMDAT_BUSY | MSC_CMDAT_STREAM_BLOCK | MSC_CMDAT_WRITE_READ | \

+			       MSC_CMDAT_DATA_EN | MSC_CMDAT_RESPONSE_FORMAT_MASK )

+

+#define __msc_get_imask(n) 		( REG_MSC_IMASK(n) )

+#define __msc_mask_all_intrs(n) 	( REG_MSC_IMASK(n) = 0xff )

+#define __msc_unmask_all_intrs(n) 	( REG_MSC_IMASK(n) = 0x00 )

+#define __msc_mask_rd(n) 		( REG_MSC_IMASK(n) |= MSC_IMASK_RXFIFO_RD_REQ )

+#define __msc_unmask_rd(n) 		( REG_MSC_IMASK(n) &= ~MSC_IMASK_RXFIFO_RD_REQ )

+#define __msc_mask_wr(n) 		( REG_MSC_IMASK(n) |= MSC_IMASK_TXFIFO_WR_REQ )

+#define __msc_unmask_wr(n) 		( REG_MSC_IMASK(n) &= ~MSC_IMASK_TXFIFO_WR_REQ )

+#define __msc_mask_endcmdres(n) 	( REG_MSC_IMASK(n) |= MSC_IMASK_END_CMD_RES )

+#define __msc_unmask_endcmdres(n) 	( REG_MSC_IMASK(n) &= ~MSC_IMASK_END_CMD_RES )

+#define __msc_mask_datatrandone(n) 	( REG_MSC_IMASK(n) |= MSC_IMASK_DATA_TRAN_DONE )

+#define __msc_unmask_datatrandone(n) 	( REG_MSC_IMASK(n) &= ~MSC_IMASK_DATA_TRAN_DONE )

+#define __msc_mask_prgdone(n) 		( REG_MSC_IMASK(n) |= MSC_IMASK_PRG_DONE )

+#define __msc_unmask_prgdone(n) 	( REG_MSC_IMASK(n) &= ~MSC_IMASK_PRG_DONE )

+

+/* m=0,1,2,3,4,5,6,7 */

+#define __msc_set_clkrt(n, m)			\

+	do {					\

+		REG_MSC_CLKRT(n) = m;		\

+	} while(0)

+

+#define __msc_get_ireg(n) 	        	( REG_MSC_IREG(n) )

+#define __msc_ireg_rd(n) 	        	( REG_MSC_IREG(n) & MSC_IREG_RXFIFO_RD_REQ )

+#define __msc_ireg_wr(n) 	        	( REG_MSC_IREG(n) & MSC_IREG_TXFIFO_WR_REQ )

+#define __msc_ireg_end_cmd_res(n)       	( REG_MSC_IREG(n) & MSC_IREG_END_CMD_RES )

+#define __msc_ireg_data_tran_done(n)     	( REG_MSC_IREG(n) & MSC_IREG_DATA_TRAN_DONE )

+#define __msc_ireg_prg_done(n) 	        	( REG_MSC_IREG(n) & MSC_IREG_PRG_DONE )

+#define __msc_ireg_clear_end_cmd_res(n)         ( REG_MSC_IREG(n) = MSC_IREG_END_CMD_RES )

+#define __msc_ireg_clear_data_tran_done(n)      ( REG_MSC_IREG(n) = MSC_IREG_DATA_TRAN_DONE )

+#define __msc_ireg_clear_prg_done(n)     	( REG_MSC_IREG(n) = MSC_IREG_PRG_DONE )

+

+#define __msc_get_stat(n) 		( REG_MSC_STAT(n) )

+#define __msc_stat_not_end_cmd_res(n) 	( (REG_MSC_STAT(n) & MSC_STAT_END_CMD_RES) == 0)

+#define __msc_stat_crc_err(n)						\

+	( REG_MSC_STAT(n) & (MSC_STAT_CRC_RES_ERR | MSC_STAT_CRC_READ_ERROR | MSC_STAT_CRC_WRITE_ERROR_YES) )

+#define __msc_stat_res_crc_err(n) 	( REG_MSC_STAT(n) & MSC_STAT_CRC_RES_ERR )

+#define __msc_stat_rd_crc_err(n) 	( REG_MSC_STAT(n) & MSC_STAT_CRC_READ_ERROR )

+#define __msc_stat_wr_crc_err(n) 	( REG_MSC_STAT(n) & MSC_STAT_CRC_WRITE_ERROR_YES )

+#define __msc_stat_resto_err(n) 	( REG_MSC_STAT(n) & MSC_STAT_TIME_OUT_RES )

+#define __msc_stat_rdto_err(n) 		( REG_MSC_STAT(n) & MSC_STAT_TIME_OUT_READ )

+

+#define __msc_rd_resfifo(n) 		( REG_MSC_RES(n) )

+#define __msc_rd_rxfifo(n)  		( REG_MSC_RXFIFO(n) )

+#define __msc_wr_txfifo(n, v)  		( REG_MSC_TXFIFO(n) = v )

+

+#define __msc_reset(n)							\

+	do { 								\

+		REG_MSC_STRPCL(n) = MSC_STRPCL_RESET;			\

+		while (REG_MSC_STAT(n) & MSC_STAT_IS_RESETTING);	\

+	} while (0)

+

+#define __msc_start_clk(n)						\

+	do { 								\

+		REG_MSC_STRPCL(n) = MSC_STRPCL_CLOCK_CONTROL_START;	\

+	} while (0)

+

+#define __msc_stop_clk(n)						\

+	do { 								\

+		REG_MSC_STRPCL(n) = MSC_STRPCL_CLOCK_CONTROL_STOP;	\

+	} while (0)

+

+#define MMC_CLK 19169200

+#define SD_CLK  24576000

+

+/* msc_clk should little than pclk and little than clk retrieve from card */

+#define __msc_calc_clk_divisor(type,dev_clk,msc_clk,lv)	\

+	do {						\

+		unsigned int rate, pclk, i;		\

+		pclk = dev_clk;				\

+		rate = type?SD_CLK:MMC_CLK;		\

+		if (msc_clk && msc_clk < pclk)		\

+			pclk = msc_clk;			\

+		i = 0;					\

+		while (pclk < rate)			\

+		{					\

+			i ++;				\

+			rate >>= 1;			\

+		}					\

+		lv = i;					\

+	} while(0)

+

+/* divide rate to little than or equal to 400kHz */

+#define __msc_calc_slow_clk_divisor(type, lv)		\

+	do {						\

+		unsigned int rate, i;			\

+		rate = (type?SD_CLK:MMC_CLK)/1000/400;	\

+		i = 0;					\

+		while (rate > 0)			\

+		{					\

+			rate >>= 1;			\

+			i ++;				\

+		}					\

+		lv = i;					\

+	} while(0)

+

+

+

+#endif /* __MIPS_ASSEMBLER */

+

+#endif /* __JZ4760BMSC_H__ */

+

diff --git a/arch/mips/include/asm/mach-jz4760b/jz4760bnemc.h b/arch/mips/include/asm/mach-jz4760b/jz4760bnemc.h
new file mode 100644
index 00000000000..4dfe6adc491
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4760b/jz4760bnemc.h
@@ -0,0 +1,115 @@
+/*

+ * linux/include/asm-mips/mach-jz4760b/jz4760bnemc.h

+ *

+ * JZ4760B NEMC register definition.

+ *

+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

+ */

+

+#ifndef __JZ4760BNEMC_H__

+#define __JZ4760BNEMC_H__

+

+

+#define NEMC_BASE	0xB3410000

+

+/*************************************************************************

+ * NEMC (External Memory Controller for NAND)

+ *************************************************************************/

+

+#define NEMC_NFCSR	(NEMC_BASE + 0x050) /* NAND Flash Control/Status Register */

+#define NEMC_SMCR1	(NEMC_BASE + 0x14)  /* Static Memory Control Register 1 */

+#define NEMC_SMCR2	(NEMC_BASE + 0x18)

+#define NEMC_SMCR3	(NEMC_BASE + 0x1c)

+#define NEMC_SMCR4	(NEMC_BASE + 0x20)

+#define NEMC_SMCR5	(NEMC_BASE + 0x24)

+#define NEMC_SMCR6	(NEMC_BASE + 0x28)

+#define NEMC_SACR1	(NEMC_BASE + 0x34)

+#define NEMC_SACR2	(NEMC_BASE + 0x38)

+#define NEMC_SACR3	(NEMC_BASE + 0x3c)

+#define NEMC_SACR4	(NEMC_BASE + 0x40)

+#define NEMC_SACR5	(NEMC_BASE + 0x44)

+#define NEMC_SACR6	(NEMC_BASE + 0x48)

+

+#define REG_NEMC_NFCSR	REG32(NEMC_NFCSR)

+#define REG_NEMC_SMCR1	REG32(NEMC_SMCR1)

+#define REG_NEMC_SMCR2	REG32(NEMC_SMCR2)

+#define REG_NEMC_SMCR3	REG32(NEMC_SMCR3)

+#define REG_NEMC_SMCR4	REG32(NEMC_SMCR4)

+#define REG_NEMC_SMCR5	REG32(NEMC_SMCR5)

+#define REG_NEMC_SMCR6	REG32(NEMC_SMCR6)

+#define REG_NEMC_SACR1	REG32(NEMC_SACR1)

+#define REG_NEMC_SACR2	REG32(NEMC_SACR2)

+#define REG_NEMC_SACR3	REG32(NEMC_SACR3)

+#define REG_NEMC_SACR4	REG32(NEMC_SACR4)

+#define REG_NEMC_SACR5	REG32(NEMC_SACR5)

+#define REG_NEMC_SACR6	REG32(NEMC_SACR6)

+

+#define NEMC_CS1	       0xBA000000	/* read-write area in static bank 1 */

+#define NEMC_CS2	       0xB8000000	/* read-write area in static bank 2 */

+#define NEMC_CS3	       0xB7000000	/* read-write area in static bank 3 */

+#define NEMC_CS4	       0xB6000000	/* read-write area in static bank 4 */

+#define NEMC_CS5	       0xB5000000	/* read-write area in static bank 5 */

+#define NEMC_CS6	       0xB4000000	/* read-write area in static bank 6 */

+

+// PN(bit 0):0-disable, 1-enable

+// PN(bit 1):0-no reset, 1-reset

+// (bit 2):Reserved

+// BITCNT(bit 3):0-disable, 1-enable

+// BITCNT(bit 4):0-calculate, 1's number, 1-calculate 0's number

+// BITCNT(bit 5):0-no reset, 1-reset bitcnt

+#define NEMC_PNCR 	(NEMC_BASE+0x100)

+#define NEMC_PNDR 	(NEMC_BASE+0x104)

+#define NEMC_BITCNT	(NEMC_BASE+0x108)

+

+#define REG_NEMC_PNCR REG32(NEMC_PNCR)

+#define REG_NEMC_PNDR REG32(NEMC_PNDR)

+#define REG_NEMC_BITCNT REG32(NEMC_BITCNT)

+

+//#define REG_NEMC_SMCR	REG32(NEMC_SMCR)

+

+/* Static Memory Control Register */

+#define NEMC_SMCR_STRV_BIT	24

+#define NEMC_SMCR_STRV_MASK	(0x1f << NEMC_SMCR_STRV_BIT)

+#define NEMC_SMCR_TAW_BIT	20

+#define NEMC_SMCR_TAW_MASK	(0x0f << NEMC_SMCR_TAW_BIT)

+#define NEMC_SMCR_TBP_BIT	16

+#define NEMC_SMCR_TBP_MASK	(0x0f << NEMC_SMCR_TBP_BIT)

+#define NEMC_SMCR_TAH_BIT	12

+#define NEMC_SMCR_TAH_MASK	(0x0f << NEMC_SMCR_TAH_BIT)

+#define NEMC_SMCR_TAS_BIT	8

+#define NEMC_SMCR_TAS_MASK	(0x0f << NEMC_SMCR_TAS_BIT)

+#define NEMC_SMCR_BW_BIT	6

+#define NEMC_SMCR_BW_MASK	(0x03 << NEMC_SMCR_BW_BIT)

+#define NEMC_SMCR_BW_8BIT	(0 << NEMC_SMCR_BW_BIT)

+#define NEMC_SMCR_BW_16BIT	(1 << NEMC_SMCR_BW_BIT)

+#define NEMC_SMCR_BL_BIT	1

+#define NEMC_SMCR_BL_MASK	(0x03 << NEMC_SMCR_BL_BIT)

+#define NEMC_SMCR_BL_4		(0 << NEMC_SMCR_BL_BIT)

+#define NEMC_SMCR_BL_8		(1 << NEMC_SMCR_BL_BIT)

+#define NEMC_SMCR_BL_16		(2 << NEMC_SMCR_BL_BIT)

+#define NEMC_SMCR_BL_32		(3 << NEMC_SMCR_BL_BIT)

+#define NEMC_SMCR_SMT		(1 << 0)

+

+/* Static Memory Bank Addr Config Reg */

+#define NEMC_SACR_BASE_BIT	8

+#define NEMC_SACR_BASE_MASK	(0xff << NEMC_SACR_BASE_BIT)

+#define NEMC_SACR_MASK_BIT	0

+#define NEMC_SACR_MASK_MASK	(0xff << NEMC_SACR_MASK_BIT)

+

+/* NAND Flash Control/Status Register */

+#define NEMC_NFCSR_NFCE4	(1 << 7) /* NAND Flash Enable */

+#define NEMC_NFCSR_NFE4		(1 << 6) /* NAND Flash FCE# Assertion Enable */

+#define NEMC_NFCSR_NFCE3	(1 << 5)

+#define NEMC_NFCSR_NFE3		(1 << 4)

+#define NEMC_NFCSR_NFCE2	(1 << 3)

+#define NEMC_NFCSR_NFE2		(1 << 2)

+#define NEMC_NFCSR_NFCE1	(1 << 1)

+#define NEMC_NFCSR_NFE1		(1 << 0)

+

+

+#ifndef __MIPS_ASSEMBLER

+

+#endif /* __MIPS_ASSEMBLER */

+

+#endif /* __JZ4760BNEMC_H__ */

+

diff --git a/arch/mips/include/asm/mach-jz4760b/jz4760bost.h b/arch/mips/include/asm/mach-jz4760b/jz4760bost.h
new file mode 100644
index 00000000000..09803b54c15
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4760b/jz4760bost.h
@@ -0,0 +1,92 @@
+/*

+ * jz4760ost.h

+ * JZ4760 OST register definition

+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

+ *

+ * Author: whxu@ingenic.cn

+ */

+

+#ifndef __JZ4760OST_H__

+#define __JZ4760OST_H__

+

+//#define CONFIG_SOC_JZ4760B 1

+/*

+ * Operating system timer module(OST) address definition

+ */

+#define	OST_BASE	0xb0002000

+

+

+/*

+ * OST registers offset address definition

+ */

+#define OST_OSTDR_OFFSET	(0xe0)  /* rw, 32, 0x???????? */

+#if defined(CONFIG_SOC_JZ4760B)

+#define OST_OSTCNTL_OFFSET	(0xe4)

+#define OST_OSTCNTH_OFFSET	(0xe8)

+#else

+#define OST_OSTCNT_OFFSET	(0xe8)  /* rw, 32, 0x???????? */

+#endif

+#define OST_OSTCSR_OFFSET	(0xec)  /* rw, 16, 0x0000 */

+

+#if defined(CONFIG_SOC_JZ4760B)

+#define OST_OSTCNTH_BUF_OFFSET	(0xfc)

+#endif

+

+

+/*

+ * OST registers address definition

+ */

+#define OST_OSTDR	(OST_BASE + OST_OSTDR_OFFSET)

+#if defined(CONFIG_SOC_JZ4760B)

+#define OST_OSTCNTL	(OST_BASE + OST_OSTCNTL_OFFSET)

+#define OST_OSTCNTH	(OST_BASE + OST_OSTCNTH_OFFSET)

+#else

+#define OST_OSTCNT	(OST_BASE + OST_OSTCNT_OFFSET)

+#endif

+#define OST_OSTCSR	(OST_BASE + OST_OSTCSR_OFFSET)

+#if defined(CONFIG_SOC_JZ4760B)

+#define OST_OSTCNTH_BUF	(OST_BASE + OST_OSTCNTH_BUF_OFFSET)

+#endif

+

+

+/*

+ * OST registers common define

+ */

+

+/* Operating system control register(OSTCSR) */

+#define OSTCSR_CNT_MD		BIT15

+#define OSTCSR_SD		BIT9

+#define OSTCSR_EXT_EN		BIT2

+#define OSTCSR_RTC_EN		BIT1

+#define OSTCSR_PCK_EN		BIT0

+

+#define OSTCSR_PRESCALE_LSB	3

+#define OSTCSR_PRESCALE_MASK	BITS_H2L(5, OSTCSR_PRESCALE_LSB)

+#define OSTCSR_PRESCALE1	(0x0 << OSTCSR_PRESCALE_LSB)

+#define OSTCSR_PRESCALE4	(0x1 << OSTCSR_PRESCALE_LSB)

+#define OSTCSR_PRESCALE16	(0x2 << OSTCSR_PRESCALE_LSB)

+#define OSTCSR_PRESCALE64	(0x3 << OSTCSR_PRESCALE_LSB)

+#define OSTCSR_PRESCALE256	(0x4 << OSTCSR_PRESCALE_LSB)

+#define OSTCSR_PRESCALE1024	(0x5 << OSTCSR_PRESCALE_LSB)

+

+

+#ifndef __MIPS_ASSEMBLER

+

+#define REG_OST_OSTDR		REG32(OST_OSTDR)

+

+#if defined(CONFIG_SOC_JZ4760B)

+#define REG_OST_OSTCNTL		REG32(OST_OSTCNTL)

+#define REG_OST_OSTCNTH		REG32(OST_OSTCNTH)

+#else

+#define REG_OST_OSTCNT		REG32(OST_OSTCNT)

+#endif

+

+#define REG_OST_OSTCSR		REG16(OST_OSTCSR)

+

+#if defined(CONFIG_SOC_JZ4760B)

+#define REG_OST_OSTCNTH_BUF	REG32(OST_OSTCNTH_BUF)

+#endif

+

+#endif /* __MIPS_ASSEMBLER */

+

+#endif /* __JZ4760OST_H__ */

diff --git a/arch/mips/include/asm/mach-jz4760b/jz4760botg.h b/arch/mips/include/asm/mach-jz4760b/jz4760botg.h
new file mode 100644
index 00000000000..17d05cb67f0
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4760b/jz4760botg.h
@@ -0,0 +1,135 @@
+/*

+ * linux/include/asm-mips/mach-jz4760b/jz4760botg.h

+ *

+ * JZ4760B OTG register definition.

+ *

+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

+ */

+

+#ifndef __JZ4760BOTG_H__

+#define __JZ4760BOTG_H__

+

+

+#define UDC_BASE	0xB3440000

+

+/*************************************************************************

+ * USB Device

+ *************************************************************************/

+#define USB_BASE  UDC_BASE

+

+#define USB_REG_FADDR		(USB_BASE + 0x00) /* Function Address 8-bit */

+#define USB_REG_POWER		(USB_BASE + 0x01) /* Power Managemetn 8-bit */

+#define USB_REG_INTRIN		(USB_BASE + 0x02) /* Interrupt IN 16-bit */

+#define USB_REG_INTROUT		(USB_BASE + 0x04) /* Interrupt OUT 16-bit */

+#define USB_REG_INTRINE		(USB_BASE + 0x06) /* Intr IN enable 16-bit */

+#define USB_REG_INTROUTE	(USB_BASE + 0x08) /* Intr OUT enable 16-bit */

+#define USB_REG_INTRUSB		(USB_BASE + 0x0a) /* Interrupt USB 8-bit */

+#define USB_REG_INTRUSBE	(USB_BASE + 0x0b) /* Interrupt USB Enable 8-bit */

+#define USB_REG_FRAME		(USB_BASE + 0x0c) /* Frame number 16-bit */

+#define USB_REG_INDEX		(USB_BASE + 0x0e) /* Index register 8-bit */

+#define USB_REG_TESTMODE	(USB_BASE + 0x0f) /* USB test mode 8-bit */

+

+#define USB_REG_CSR0		(USB_BASE + 0x12) /* EP0 CSR 8-bit */

+#define USB_REG_INMAXP		(USB_BASE + 0x10) /* EP1-2 IN Max Pkt Size 16-bit */

+#define USB_REG_INCSR		(USB_BASE + 0x12) /* EP1-2 IN CSR LSB 8/16bit */

+#define USB_REG_INCSRH		(USB_BASE + 0x13) /* EP1-2 IN CSR MSB 8-bit */

+#define USB_REG_OUTMAXP		(USB_BASE + 0x14) /* EP1 OUT Max Pkt Size 16-bit */

+#define USB_REG_OUTCSR		(USB_BASE + 0x16) /* EP1 OUT CSR LSB 8/16bit */

+#define USB_REG_OUTCSRH		(USB_BASE + 0x17) /* EP1 OUT CSR MSB 8-bit */

+#define USB_REG_OUTCOUNT	(USB_BASE + 0x18) /* bytes in EP0/1 OUT FIFO 16-bit */

+

+#define USB_FIFO_EP0		(USB_BASE + 0x20)

+#define USB_FIFO_EP1		(USB_BASE + 0x24)

+#define USB_FIFO_EP2		(USB_BASE + 0x28)

+

+#define USB_REG_EPINFO		(USB_BASE + 0x78) /* Endpoint information */

+#define USB_REG_RAMINFO		(USB_BASE + 0x79) /* RAM information */

+

+#define USB_REG_INTR		(USB_BASE + 0x200) /* DMA pending interrupts */

+#define USB_REG_CNTL1		(USB_BASE + 0x204) /* DMA channel 1 control */

+#define USB_REG_ADDR1		(USB_BASE + 0x208) /* DMA channel 1 AHB memory addr */

+#define USB_REG_COUNT1		(USB_BASE + 0x20c) /* DMA channel 1 byte count */

+#define USB_REG_CNTL2		(USB_BASE + 0x214) /* DMA channel 2 control */

+#define USB_REG_ADDR2		(USB_BASE + 0x218) /* DMA channel 2 AHB memory addr */

+#define USB_REG_COUNT2		(USB_BASE + 0x21c) /* DMA channel 2 byte count */

+

+

+/* Power register bit masks */

+#define USB_POWER_SUSPENDM	0x01

+#define USB_POWER_RESUME	0x04

+#define USB_POWER_HSMODE	0x10

+#define USB_POWER_HSENAB	0x20

+#define USB_POWER_SOFTCONN	0x40

+

+/* Interrupt register bit masks */

+#define USB_INTR_SUSPEND	0x01

+#define USB_INTR_RESUME		0x02

+#define USB_INTR_RESET		0x04

+

+#define USB_INTR_EP0		0x0001

+#define USB_INTR_INEP1		0x0002

+#define USB_INTR_INEP2		0x0004

+#define USB_INTR_OUTEP1		0x0002

+

+/* CSR0 bit masks */

+#define USB_CSR0_OUTPKTRDY	0x01

+#define USB_CSR0_INPKTRDY	0x02

+#define USB_CSR0_SENTSTALL	0x04

+#define USB_CSR0_DATAEND	0x08

+#define USB_CSR0_SETUPEND	0x10

+#define USB_CSR0_SENDSTALL	0x20

+#define USB_CSR0_SVDOUTPKTRDY	0x40

+#define USB_CSR0_SVDSETUPEND	0x80

+

+/* Endpoint CSR register bits */

+#define USB_INCSRH_AUTOSET	0x80

+#define USB_INCSRH_ISO		0x40

+#define USB_INCSRH_MODE		0x20

+#define USB_INCSRH_DMAREQENAB	0x10

+#define USB_INCSRH_DMAREQMODE	0x04

+#define USB_INCSR_CDT		0x40

+#define USB_INCSR_SENTSTALL	0x20

+#define USB_INCSR_SENDSTALL	0x10

+#define USB_INCSR_FF		0x08

+#define USB_INCSR_UNDERRUN	0x04

+#define USB_INCSR_FFNOTEMPT	0x02

+#define USB_INCSR_INPKTRDY	0x01

+#define USB_OUTCSRH_AUTOCLR	0x80

+#define USB_OUTCSRH_ISO		0x40

+#define USB_OUTCSRH_DMAREQENAB	0x20

+#define USB_OUTCSRH_DNYT	0x10

+#define USB_OUTCSRH_DMAREQMODE	0x08

+#define USB_OUTCSR_CDT		0x80

+#define USB_OUTCSR_SENTSTALL	0x40

+#define USB_OUTCSR_SENDSTALL	0x20

+#define USB_OUTCSR_FF		0x10

+#define USB_OUTCSR_DATAERR	0x08

+#define USB_OUTCSR_OVERRUN	0x04

+#define USB_OUTCSR_FFFULL	0x02

+#define USB_OUTCSR_OUTPKTRDY	0x01

+

+/* Testmode register bits */

+#define USB_TEST_SE0NAK		0x01

+#define USB_TEST_J		0x02

+#define USB_TEST_K		0x04

+#define USB_TEST_PACKET		0x08

+

+/* DMA control bits */

+#define USB_CNTL_ENA		0x01

+#define USB_CNTL_DIR_IN		0x02

+#define USB_CNTL_MODE_1		0x04

+#define USB_CNTL_INTR_EN	0x08

+#define USB_CNTL_EP(n)		((n) << 4)

+#define USB_CNTL_BURST_0	(0 << 9)

+#define USB_CNTL_BURST_4	(1 << 9)

+#define USB_CNTL_BURST_8	(2 << 9)

+#define USB_CNTL_BURST_16	(3 << 9)

+

+

+

+#ifndef __MIPS_ASSEMBLER

+

+#endif /* __MIPS_ASSEMBLER */

+

+#endif /* __JZ4760BOTG_H__ */

+

diff --git a/arch/mips/include/asm/mach-jz4760b/jz4760botp.h b/arch/mips/include/asm/mach-jz4760b/jz4760botp.h
new file mode 100644
index 00000000000..8934a09d637
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4760b/jz4760botp.h
@@ -0,0 +1,97 @@
+/*

+ * linux/include/asm-mips/mach-jz4760b/jz4760botp.h

+ *

+ * JZ4760B OTP register definition.

+ *

+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

+ */

+

+#ifndef __JZ4760BOTP_H__

+#define __JZ4760BOTP_H__

+

+

+/*************************************************************************

+ * OTP (One Time Programmable Module)

+ *************************************************************************/

+#define OTP_ID0		(OTP_BASE + 0x00) /* ID0 Register */

+#define OTP_ID1		(OTP_BASE + 0x04) /* ID1 Register */

+#define OTP_ID2		(OTP_BASE + 0x08) /* ID2 Register */

+#define OTP_ID3		(OTP_BASE + 0x0C) /* ID3 Register */

+#define OTP_BR0		(OTP_BASE + 0x10) /* BOOTROM0 Register */

+#define OTP_BR1		(OTP_BASE + 0x14) /* BOOTROM1 Register */

+#define OTP_HW0		(OTP_BASE + 0x18) /* Chip Hardware 0 Register */

+#define OTP_HW1		(OTP_BASE + 0x1C) /* Chip Hardware 1 Register */

+

+#define REG_OTP_ID0	REG32(OTP_ID0)

+#define REG_OTP_ID1	REG32(OTP_ID1)

+#define REG_OTP_ID2	REG32(OTP_ID2)

+#define REG_OTP_ID3	REG32(OTP_ID3)

+#define REG_OTP_BR0	REG32(OTP_BR0)

+#define REG_OTP_BR1	REG32(OTP_BR1)

+#define REG_OTP_HW0	REG32(OTP_HW0)

+#define REG_OTP_HW1	REG32(OTP_HW1)

+

+/* ID0 Register */

+#define OTP_ID0_WID_BIT		24 /* Wafer ID */

+#define OTP_ID0_WID_MASK	(0xff << OTP_ID0_WID_BIT)

+#define OTP_ID0_MID_BIT		16 /* MASK ID */

+#define OTP_ID0_MID_MASK	(0xff << OTP_ID0_MID_BIT)

+#define OTP_ID0_FID_BIT		8 /* Foundary ID */

+#define OTP_ID0_FID_MASK	(0xff << OTP_ID0_FID_BIT)

+#define OTP_ID0_PID_BIT		0 /* Product ID */

+#define OTP_ID0_PID_MASK	(0xff << OTP_ID0_PID_BIT)

+

+/* ID1 Register */

+#define OTP_ID1_LID_BIT		8 /* Lot ID */

+#define OTP_ID1_LID_MASK	(0xffffff << OTP_ID1_LID_BIT)

+#define OTP_ID1_TID_BIT		0 /* Test House ID */

+#define OTP_ID1_TID_MASK	(0xff << OTP_ID1_TID_BIT)

+

+/* ID2 Register */

+#define OTP_ID2_XADR_BIT	24 /* Die X-dir Address */

+#define OTP_ID2_XADR_MASK	(0xff << OTP_ID2_XADR_BIT)

+#define OTP_ID2_YADR_BIT	16 /* Die Y-dir Address */

+#define OTP_ID2_YADR_MASK	(0xff << OTP_ID2_YADR_BIT)

+#define OTP_ID2_TDATE_BIT	0  /* Testing Date */

+#define OTP_ID2_TDATE_MASK	(0xffff << OTP_ID2_TDATE_BIT)

+

+/* ID3 Register */

+#define OTP_ID3_CID_BIT		16 /* Customer ID */

+#define OTP_ID3_CID_MASK	(0xffff << OTP_ID3_CID_BIT)

+#define OTP_ID3_CP_BIT		0 /* Chip Parameters */

+#define OTP_ID3_CP_MASK		(0xffff << OTP_ID3_CP_BIT)

+

+/* BOOTROM1 Register */

+#define OTP_BR1_UDCBOOT_BIT	0

+#define OTP_BR1_UDCBOOT_MASK	(0xff << OTP_BR1_UDCBOOT_BIT)

+  #define OTP_BR1_UDCBOOT_AUTO	(0xf0 << OTP_BR1_UDCBOOT_BIT)

+  #define OTP_BR1_UDCBOOT_24M	(0x0f << OTP_BR1_UDCBOOT_BIT) /* 24MHz OSC */

+  #define OTP_BR1_UDCBOOT_13M	(0x0c << OTP_BR1_UDCBOOT_BIT) /* 13MHz OSC */

+  #define OTP_BR1_UDCBOOT_26M	(0x03 << OTP_BR1_UDCBOOT_BIT) /* 26MHz OSC */

+  #define OTP_BR1_UDCBOOT_27M	(0x00 << OTP_BR1_UDCBOOT_BIT) /* 27MHz OSC */

+

+/* Chip Hardware 1 Register */

+#define OTP_HW1_MC_EN		(0x3 << 30) /* MC is enabled */

+#define OTP_HW1_ME_EN		(0x3 << 28)

+#define OTP_HW1_DE_EN		(0x3 << 26)

+#define OTP_HW1_IDCT_EN		(0x3 << 24)

+#define OTP_HW1_UART3_EN	(0x3 << 22)

+#define OTP_HW1_UART2_EN	(0x3 << 20)

+#define OTP_HW1_UART1_EN	(0x3 << 18)

+#define OTP_HW1_UART0_EN	(0x3 << 16)

+#define OTP_HW1_SSI1_EN		(0x3 << 14)

+#define OTP_HW1_SSI0_EN		(0x3 << 12)

+#define OTP_HW1_MSC1_EN		(0x3 << 10)

+#define OTP_HW1_MSC0_EN		(0x3 << 8)

+#define OTP_HW1_UHC_EN		(0x3 << 6)

+#define OTP_HW1_TVE_EN		(0x3 << 4)

+#define OTP_HW1_TSSI_EN		(0x3 << 2)

+#define OTP_HW1_CIM_EN		(0x3 << 0)

+

+

+#ifndef __MIPS_ASSEMBLER

+

+#endif /* __MIPS_ASSEMBLER */

+

+#endif /* __JZ4760BOTP_H__ */

+

diff --git a/arch/mips/include/asm/mach-jz4760b/jz4760bowi.h b/arch/mips/include/asm/mach-jz4760b/jz4760bowi.h
new file mode 100644
index 00000000000..4b38755f63e
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4760b/jz4760bowi.h
@@ -0,0 +1,82 @@
+/*

+ * jz4760bowi.h

+ * JZ4760B OWI register definition

+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

+ *

+ * Author: whxu@ingenic.cn

+ */

+

+#ifndef __JZ4760BOWI_H__

+#define __JZ4760BOWI_H__

+

+

+/*

+ * One wire bus interface(OWI) address definition

+ */

+#define	OWI_BASE	0xb0072000

+

+

+/*

+ * OWI registers offset address definition

+ */

+#define OWI_OWICFG_OFFSET	(0x00)	/* rw, 8, 0x00 */

+#define OWI_OWICTL_OFFSET	(0x04)	/* rw, 8, 0x00 */

+#define OWI_OWISTS_OFFSET	(0x08)	/* rw, 8, 0x00 */

+#define OWI_OWIDAT_OFFSET	(0x0c)	/* rw, 8, 0x00 */

+#define OWI_OWIDIV_OFFSET	(0x10)	/* rw, 8, 0x00 */

+

+

+/*

+ * OWI registers address definition

+ */

+#define OWI_OWICFG	(OWI_BASE + OWI_OWICFG_OFFSET)

+#define OWI_OWICTL	(OWI_BASE + OWI_OWICTL_OFFSET)

+#define OWI_OWISTS	(OWI_BASE + OWI_OWISTS_OFFSET)

+#define OWI_OWIDAT	(OWI_BASE + OWI_OWIDAT_OFFSET)

+#define OWI_OWIDIV	(OWI_BASE + OWI_OWIDIV_OFFSET)

+

+

+/*

+ * OWI registers common define

+ */

+

+/* OWI configure register(OWICFG) */

+#define OWICFG_MODE	BIT7

+#define OWICFG_RDDATA	BIT6

+#define OWICFG_WRDATA	BIT5

+#define OWICFG_RDST	BIT4

+#define OWICFG_WR1RD	BIT3

+#define OWICFG_WR0	BIT2

+#define OWICFG_RST	BIT1

+#define OWICFG_ENA	BIT0

+

+/* OWI control register(OWICTL) */

+#define OWICTL_EBYTE	BIT2

+#define OWICTL_EBIT	BIT1

+#define OWICTL_ERST	BIT0

+

+/* OWI status register(OWISTS) */

+#define OWISTS_PST		BIT7

+#define OWISTS_BYTE_RDY		BIT2

+#define OWISTS_BIT_RDY		BIT1

+#define OWISTS_PST_RDY		BIT0

+

+/* OWI clock divide register(OWIDIV) */

+#define OWIDIV_CLKDIV_LSB	0

+#define OWIDIV_CLKDIV_MASK	BITS_H2L(5, OWIDIV_CLKDIV_LSB)

+

+

+#ifndef __MIPS_ASSEMBLER

+

+/* Basic ops */

+#define REG_OWI_OWICFG  REG8(OWI_OWICFG)

+#define REG_OWI_OWICTL  REG8(OWI_OWICTL)

+#define REG_OWI_OWISTS  REG8(OWI_OWISTS)

+#define REG_OWI_OWIDAT  REG8(OWI_OWIDAT)

+#define REG_OWI_OWIDIV  REG8(OWI_OWIDIV)

+

+

+#endif /* __MIPS_ASSEMBLER */

+

+#endif /* __JZ4760BOWI_H__ */

+

diff --git a/arch/mips/include/asm/mach-jz4760b/jz4760bpcm.h b/arch/mips/include/asm/mach-jz4760b/jz4760bpcm.h
new file mode 100644
index 00000000000..a686a99c792
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4760b/jz4760bpcm.h
@@ -0,0 +1,218 @@
+/*

+ * jz4760bpcm.h

+ * JZ4760B PCM register definition

+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

+ *

+ * Author: whxu@ingenic.cn

+ */

+

+#ifndef __JZ4760BPCM_H__

+#define __JZ4760BPCM_H__

+

+

+/*

+ * Pulse-code modulation module(PCM) address definition

+ */

+#define	PCM_BASE        0xb0071000

+

+

+/*

+ * PCM registers offset address definition

+ */

+#define PCM_PCTL_OFFSET		(0x00)	/* rw, 32, 0x00000000 */

+#define PCM_PCFG_OFFSET		(0x04)  /* rw, 32, 0x00000110 */

+#define PCM_PDP_OFFSET		(0x08)  /* rw, 32, 0x00000000 */

+#define PCM_PINTC_OFFSET	(0x0c)  /* rw, 32, 0x00000000 */

+#define PCM_PINTS_OFFSET	(0x10)  /* rw, 32, 0x00000100 */

+#define PCM_PDIV_OFFSET		(0x14)  /* rw, 32, 0x00000001 */

+

+

+/*

+ * PCM registers address definition

+ */

+#define PCM_PCTL	(PCM_BASE + PCM_PCTL_OFFSET)

+#define PCM_PCFG	(PCM_BASE + PCM_PCFG_OFFSET)

+#define PCM_PDP		(PCM_BASE + PCM_PDP_OFFSET)

+#define PCM_PINTC	(PCM_BASE + PCM_PINTC_OFFSET)

+#define PCM_PINTS	(PCM_BASE + PCM_PINTS_OFFSET)

+#define PCM_PDIV	(PCM_BASE + PCM_PDIV_OFFSET)

+

+

+/*

+ * CPM registers common define

+ */

+

+/* PCM controller control register (PCTL) */

+#define PCTL_ERDMA	BIT9

+#define PCTL_ETDMA	BIT8

+#define PCTL_LSMP	BIT7

+#define PCTL_ERPL	BIT6

+#define PCTL_EREC	BIT5

+#define PCTL_FLUSH	BIT4

+#define PCTL_RST	BIT3

+#define PCTL_CLKEN	BIT1

+#define PCTL_PCMEN	BIT0

+

+/* PCM controller configure register (PCFG) */

+#define PCFG_ISS_16BIT		BIT12

+#define PCFG_OSS_16BIT		BIT11

+#define PCFG_IMSBPOS		BIT10

+#define PCFG_OMSBPOS		BIT9

+#define PCFG_MODE_SLAVE		BIT0

+

+#define PCFG_SLOT_LSB		13

+#define PCFG_SLOT_MASK		BIT_H2L(14, PCFG_SLOT_LSB)

+#define PCFG_SLOT(n)		((n) << PCFG_SLOT_LSB)

+

+#define	PCFG_RFTH_LSB		5

+#define	PCFG_RFTH_MASK		BIT_H2L(8, PCFG_RFTH_LSB)

+

+#define	PCFG_TFTH_LSB		1

+#define	PCFG_TFTH_MASK		BIT_H2L(4, PCFG_TFTH_LSB)

+

+/* PCM controller interrupt control register(PINTC) */

+#define PINTC_ETFS	BIT3

+#define PINTC_ETUR	BIT2

+#define PINTC_ERFS	BIT1

+#define PINTC_EROR	BIT0

+

+/* PCM controller interrupt status register(PINTS) */

+#define PINTS_RSTS	BIT14

+#define PINTS_TFS	BIT8

+#define PINTS_TUR	BIT7

+#define PINTS_RFS	BIT1

+#define PINTS_ROR	BIT0

+

+#define PINTS_TFL_LSB		9

+#define PINTS_TFL_MASK		BITS_H2L(13, PINTS_TFL_LSB)

+

+#define PINTS_RFL_LSB		2

+#define PINTS_RFL_MASK		BITS_H2L(6, PINTS_RFL_LSB)

+

+/* PCM controller clock division register(PDIV) */

+#define PDIV_SYNL_LSB		11

+#define PDIV_SYNL_MASK		BITS_H2L(16, PDIV_SYNL_LSB)

+

+#define PDIV_SYNDIV_LSB		6

+#define PDIV_SYNDIV_MASK	BITS_H2L(10, PDIV_SYNDIV_LSB)

+

+#define PDIV_CLKDIV_LSB		0

+#define PDIV_CLKDIV_MASK	BITS_H2L(5, PDIV_CLKDIV_LSB)

+

+

+#ifndef __MIPS_ASSEMBLER

+

+

+#define REG_PCM_PCTL		REG32(PCM_PCTL)

+#define REG_PCM_PCFG		REG32(PCM_PCFG)

+#define REG_PCM_PDP		REG32(PCM_PDP)

+#define REG_PCM_PINTC		REG32(PCM_PINTC)

+#define REG_PCM_PINTS		REG32(PCM_PINTS)

+#define REG_PCM_PDIV		REG32(PCM_PDIV)

+

+/*

+ * PCM_DIN, PCM_DOUT, PCM_CLK, PCM_SYN

+*/

+#define __gpio_as_pcm() 			\

+do {						\

+	unsigned int bits = BITS_H2L(3, 0);	\

+	REG_GPIO_PXFUNS(3) = bits;		\

+	REG_GPIO_PXSELC(3) = bits;		\

+	REG_GPIO_PXTRGC(3) = bits; 		\

+	REG_GPIO_PXPES(3)  = bits; 		\

+} while (0)

+

+#define __pcm_enable()          (REG_PCM_PCTL |= PCTL_PCMEN)

+#define __pcm_disable()         (REG_PCM_PCTL &= ~PCTL_PCMEN)

+

+#define __pcm_clk_enable()      (REG_PCM_PCTL |= PCTL_CLKEN)

+#define __pcm_clk_disable()     (REG_PCM_PCTL &= ~PCTL_CLKEN)

+

+#define __pcm_reset()           (REG_PCM_PCTL |= PCTL_RST)

+#define __pcm_flush_fifo()	(REG_PCM_PCTL |= PCTL_FLUSH)

+

+#define __pcm_enable_record()		(REG_PCM_PCTL |= PCTL_EREC)

+#define __pcm_disable_record()		(REG_PCM_PCTL &= ~PCTL_EREC)

+#define __pcm_enable_playback()		(REG_PCM_PCTL |= PCTL_ERPL)

+#define __pcm_disable_playback()	(REG_PCM_PCTL &= ~PCTL_ERPL)

+

+#define __pcm_enable_rxfifo()           __pcm_enable_record()

+#define __pcm_disable_rxfifo()          __pcm_disable_record()

+#define __pcm_enable_txfifo()           __pcm_enable_playback()

+#define __pcm_disable_txfifo()          __pcm_disable_playback()

+

+#define __pcm_last_sample()     (REG_PCM_PCTL |= PCTL_LSMP)

+#define __pcm_zero_sample()     (REG_PCM_PCTL &= ~PCTL_LSMP)

+

+#define __pcm_enable_transmit_dma()    (REG_PCM_PCTL |= PCTL_ETDMA)

+#define __pcm_disable_transmit_dma()   (REG_PCM_PCTL &= ~PCTL_ETDMA)

+#define __pcm_enable_receive_dma()     (REG_PCM_PCTL |= PCTL_ERDMA)

+#define __pcm_disable_receive_dma()    (REG_PCM_PCTL &= ~PCTL_ERDMA)

+

+#define __pcm_as_master()     (REG_PCM_PCFG &= PCFG_MODE)

+#define __pcm_as_slave()      (REG_PCM_PCFG |= ~PCFG_MODE)

+

+#define __pcm_set_transmit_trigger(n) 			\

+do {							\

+	REG_PCM_PCFG &= ~PCFG_TFTH_MASK;		\

+	REG_PCM_PCFG |= ((n) << PCFG_TFTH_BIT);		\

+} while(0)

+

+#define __pcm_set_receive_trigger(n) 			\

+do {							\

+	REG_PCM_PCFG &= ~PCFG_RFTH_MASK;		\

+	REG_PCM_PCFG |= ((n) << PCFG_RFTH_BIT);		\

+} while(0)

+

+#define __pcm_omsb_same_sync()   (REG_PCM_PCFG &= ~PCFG_OMSBPOS)

+#define __pcm_omsb_next_sync()   (REG_PCM_PCFG |= PCFG_OMSBPOS)

+

+#define __pcm_imsb_same_sync()   (REG_PCM_PCFG &= ~PCFG_IMSBPOS)

+#define __pcm_imsb_next_sync()   (REG_PCM_PCFG |= PCFG_IMSBPOS)

+

+#define __pcm_set_iss(n)	\

+(n == 16 ? REG_PCM_PCFG |= PCFG_ISS_16BIT : REG_PCM_PCFG &= ~PCFG_ISS_16BIT)

+

+#define __pcm_set_oss(n)	\

+(n == 16 ? REG_PCM_PCFG |= PCFG_OSS_16BIT : REG_PCM_PCFG &= ~PCFG_OSS_16BIT)

+

+#define __pcm_set_valid_slot(n) \

+(REG_PCM_PCFG = (REG_PCM_PCFG & ~PCFG_SLOT_MASK) | PCFG_SLOT(n))

+

+#define __pcm_write_data(v)	(REG_PCM_PDP = (v))

+#define __pcm_read_data()	(REG_PCM_PDP)

+

+#define __pcm_enable_tfs_intr()		(REG_PCM_PINTC |= PINTC_ETFS)

+#define __pcm_disable_tfs_intr()	(REG_PCM_PINTC &= ~PINTC_ETFS)

+

+#define __pcm_enable_tur_intr()		(REG_PCM_PINTC |= PINTC_ETUR)

+#define __pcm_disable_tur_intr()	(REG_PCM_PINTC &= ~PINTC_ETUR)

+

+#define __pcm_enable_rfs_intr()		(REG_PCM_PINTC |= PINTC_ERFS)

+#define __pcm_disable_rfs_intr()	(REG_PCM_PINTC &= ~PINTC_ERFS)

+

+#define __pcm_enable_ror_intr()		(REG_PCM_PINTC |= PINTC_EROR)

+#define __pcm_disable_ror_intr()	(REG_PCM_PINTC &= ~PINTC_EROR)

+

+#define __pcm_ints_valid_tx()	(((REG_PCM_PINTS & PINTS_TFL_MASK) >> PINTS_TFL_LSB))

+#define __pcm_ints_valid_rx()	(((REG_PCM_PINTS & PINTS_RFL_MASK) >> PINTS_RFL_LSB))

+

+#define __pcm_set_clk_div(n)	\

+(REG_PCM_DIV = (REG_PCM_PDIV & ~PDIV_CLKDIV_MASK) | ((n) << PDIV_CLKDIV_LSB))

+

+#define __pcm_set_clk_rate(sysclk, pcmclk) \

+__pcm_set_clk_div(((sysclk) / (pcmclk) - 1))

+

+#define __pcm_set_sync_div(n) \

+(REG_PCM_PDIV = (REG_PCM_PDIV & ~PDIV_SYNDIV_MASK) | ((n) << PDIV_SYNDIV_LSB))

+

+#define __pcm_set_sync_rate(pcmclk, sync) \

+__pcm_set_sync_div(((pcmclk) / (8 * (sync)) - 1))

+

+#define __pcm_set_sync_len(n) \

+(REG_PCM_PDIV = (REG_PCM_PDIV & ~PDIV_SYNL_MASK) | (n << PDIV_SYNL_LSB))

+

+#endif /* __MIPS_ASSEMBLER */

+

+#endif /* __JZ4760BPCM_H__ */

+

diff --git a/arch/mips/include/asm/mach-jz4760b/jz4760brtc.h b/arch/mips/include/asm/mach-jz4760b/jz4760brtc.h
new file mode 100644
index 00000000000..26ecb7079f8
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4760b/jz4760brtc.h
@@ -0,0 +1,172 @@
+/*

+ * jz4760brtc.h

+ * JZ4760B RTC register definition

+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

+ *

+ * Author: cjwang@ingenic.cn

+ */

+

+#ifndef __JZ4760BRTC_H__

+#define __JZ4760BRTC_H__

+

+

+/*

+ * Real time clock module(RTC) address definition

+ */

+#define	RTC_BASE	0xb0003000

+

+

+/*

+ * RTC registers offset address definition

+ */

+#define RTC_RTCCR_OFFSET	(0x00)	/* rw, 32, 0x00000081 */

+#define RTC_RTCSR_OFFSET	(0x04)	/* rw, 32, 0x???????? */

+#define RTC_RTCSAR_OFFSET	(0x08)	/* rw, 32, 0x???????? */

+#define RTC_RTCGR_OFFSET	(0x0c)	/* rw, 32, 0x0??????? */

+

+#define RTC_HCR_OFFSET		(0x20)  /* rw, 32, 0x00000000 */

+#define RTC_HWFCR_OFFSET	(0x24)  /* rw, 32, 0x0000???0 */

+#define RTC_HRCR_OFFSET		(0x28)  /* rw, 32, 0x00000??0 */

+#define RTC_HWCR_OFFSET		(0x2c)  /* rw, 32, 0x00000008 */

+#define RTC_HWRSR_OFFSET	(0x30)  /* rw, 32, 0x00000000 */

+#define RTC_HSPR_OFFSET		(0x34)  /* rw, 32, 0x???????? */

+#define RTC_WENR_OFFSET		(0x3c)  /* rw, 32, 0x00000000 */

+

+

+/*

+ * RTC registers address definition

+ */

+#define RTC_RTCCR	(RTC_BASE + RTC_RTCCR_OFFSET)

+#define RTC_RTCSR	(RTC_BASE + RTC_RTCSR_OFFSET)

+#define RTC_RTCSAR	(RTC_BASE + RTC_RTCSAR_OFFSET)

+#define RTC_RTCGR	(RTC_BASE + RTC_RTCGR_OFFSET)

+

+#define RTC_HCR		(RTC_BASE + RTC_HCR_OFFSET)

+#define RTC_HWFCR	(RTC_BASE + RTC_HWFCR_OFFSET)

+#define RTC_HRCR	(RTC_BASE + RTC_HRCR_OFFSET)

+#define RTC_HWCR	(RTC_BASE + RTC_HWCR_OFFSET)

+#define RTC_HWRSR	(RTC_BASE + RTC_HWRSR_OFFSET)

+#define RTC_HSPR	(RTC_BASE + RTC_HSPR_OFFSET)

+#define RTC_WENR	(RTC_BASE + RTC_WENR_OFFSET)

+

+

+/*

+ * RTC registers common define

+ */

+

+/* RTC control register(RTCCR) */

+#define RTCCR_WRDY		BIT7

+#define RTCCR_1HZ		BIT6

+#define RTCCR_1HZIE		BIT5

+#define RTCCR_AF		BIT4

+#define RTCCR_AIE		BIT3

+#define RTCCR_AE		BIT2

+#define RTCCR_SELEXC		BIT1

+#define RTCCR_RTCE		BIT0

+

+/* RTC regulator register(RTCGR) */

+#define RTCGR_LOCK		BIT31

+

+#define RTCGR_ADJC_LSB		16

+#define RTCGR_ADJC_MASK		BITS_H2L(25, RTCGR_ADJC_LSB)

+

+#define RTCGR_NC1HZ_LSB		0

+#define RTCGR_NC1HZ_MASK	BITS_H2L(15, RTCGR_NC1HZ_LSB)

+

+/* Hibernate control register(HCR) */

+#define HCR_PD			BIT0

+

+/* Hibernate wakeup filter counter register(HWFCR) */

+#define HWFCR_LSB		5

+#define HWFCR_MASK		BITS_H2L(15, HWFCR_LSB)

+#define HWFCR_WAIT_TIME(ms)	(((ms) << HWFCR_LSB) > HWFCR_MASK ? HWFCR_MASK : ((ms) << HWFCR_LSB))

+

+/* Hibernate reset counter register(HRCR) */

+#define HRCR_LSB		5

+#define HRCR_MASK		BITS_H2L(11, HRCR_LSB)

+#define HRCR_WAIT_TIME(ms)     (((ms) << HRCR_LSB) > HRCR_MASK ? HRCR_MASK : ((ms) << HRCR_LSB))

+

+/* Hibernate wakeup control register(HWCR) */

+#define HWCR_EPDET		BIT3

+#define HWCR_WKUPVL		BIT2

+#define HWCR_EALM		BIT0

+

+/* Hibernate wakeup status register(HWRSR) */

+#define HWRSR_APD		BIT8

+#define HWRSR_HR		BIT5

+#define HWRSR_PPR		BIT4

+#define HWRSR_PIN		BIT1

+#define HWRSR_ALM		BIT0

+

+/* write enable pattern register(WENR) */

+#define WENR_WEN		BIT31

+

+#define WENR_WENPAT_LSB		0

+#define WENR_WENPAT_MASK	BITS_H2L(15, WENR_WENPAT_LSB)

+#define WENR_WENPAT_WRITABLE	(0xa55a)

+

+/* Hibernate scratch pattern register(HSPR) */

+#define HSPR_RTCV               0x52544356      /* The value is 'RTCV', means rtc is valid */ 

+

+

+#ifndef __MIPS_ASSEMBLER

+

+/* Waiting for the RTC register writing finish */

+#define __wait_write_ready()						\

+do {									\

+	unsigned int timeout = 1;					\

+	while (!(rtc_read_reg(RTC_RTCCR) & RTCCR_WRDY) && timeout++);	\

+}while(0);

+

+/* Waiting for the RTC register writable */

+#define __wait_writable()						\

+do {									\

+	unsigned int timeout = 1;					\

+	__wait_write_ready();						\

+	OUTREG32(RTC_WENR, WENR_WENPAT_WRITABLE);			\

+	__wait_write_ready();						\

+	while (!(rtc_read_reg(RTC_WENR) & WENR_WEN) && timeout++);	\

+}while(0);

+

+/* Basic RTC ops */

+#define rtc_read_reg(reg)				\

+({							\

+	unsigned int data;				\

+	do {						\

+		data = INREG32(reg);			\

+	} while (INREG32(reg) != data);			\

+	data;						\

+})

+

+#define rtc_write_reg(reg, data)			\

+do {							\

+	__wait_writable();				\

+	OUTREG32(reg, data);				\

+	__wait_write_ready();				\

+}while(0);

+

+#define rtc_set_reg(reg, data)	rtc_write_reg(reg, rtc_read_reg(reg) | (data))

+#define rtc_clr_reg(reg, data)	rtc_write_reg(reg, rtc_read_reg(reg) & ~(data))

+

+typedef volatile struct

+{

+	unsigned int RTCCR;

+	unsigned int RTCSR;

+	unsigned int RTCSAR;

+	unsigned int RTCGR;

+

+	unsigned int RTCRSV[(RTC_HCR_OFFSET - RTC_RTCGR_OFFSET)/4];

+

+	unsigned int HCR;

+	unsigned int HWFCR;

+	unsigned int HRCR;

+	unsigned int HWCR;

+	unsigned int HWRSR;

+	unsigned int HSPR;

+	unsigned int WENR;

+} JZ4760B_RTC, *PJZ4760B_RTC;

+

+

+#endif /* __MIPS_ASSEMBLER */

+

+#endif /* __JZ4760BRTC_H__ */

diff --git a/arch/mips/include/asm/mach-jz4760b/jz4760bsadc.h b/arch/mips/include/asm/mach-jz4760b/jz4760bsadc.h
new file mode 100644
index 00000000000..44e769abbbb
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4760b/jz4760bsadc.h
@@ -0,0 +1,182 @@
+/*

+ * jz4760bsadc.h

+ * JZ4760B SADC register definition.

+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

+ *

+ * Author:jfli@ingenic.cn

+ */

+

+#ifndef __JZ4760BSADC_H__

+#define __JZ4760BSADC_H__

+

+

+/*

+ * SAR A/D Controller(SADC) address definition

+ */

+#define	SADC_BASE		0xb0070000

+

+

+/*

+ * SADC registers offset definition

+ */

+#define SADC_ADENA_OFFSET	(0x00)	/* rw,  8, 0x00 */

+#define SADC_ADCFG_OFFSET       (0x04)  /* rw, 32, 0x0002000c */

+#define SADC_ADCTRL_OFFSET      (0x08)  /* rw,  8, 0x3f */

+#define SADC_ADSTATE_OFFSET     (0x0c)  /* rw,  8, 0x00 */

+#define SADC_ADSAME_OFFSET    	(0x10)  /* rw, 16, 0x0000 */

+#define SADC_ADWAIT_OFFSET    	(0x14)  /* rw, 16, 0x0000 */

+#define SADC_ADTCH_OFFSET       (0x18)  /* rw, 32, 0x00000000 */

+#define SADC_ADVDAT_OFFSET      (0x1c)  /* rw, 16, 0x0000 */

+#define SADC_ADADAT_OFFSET      (0x20)  /* rw, 16, 0x0000 */

+#define SADC_ADFLT_OFFSET       (0x24)  /* rw, 16, 0x0000 */

+#define SADC_ADCLK_OFFSET       (0x28)  /* rw, 32, 0x00000000 */

+

+

+/*

+ * SADC registers address definition

+ */

+#define SADC_ADENA		(SADC_BASE + SADC_ADENA_OFFSET)	 /* ADC Enable Register */

+#define SADC_ADCFG		(SADC_BASE + SADC_ADCFG_OFFSET)	 /* ADC Configure Register */

+#define SADC_ADCTRL		(SADC_BASE + SADC_ADCTRL_OFFSET) /* ADC Control Register */

+#define SADC_ADSTATE		(SADC_BASE + SADC_ADSTATE_OFFSET)/* ADC Status Register*/

+#define SADC_ADSAME		(SADC_BASE + SADC_ADSAME_OFFSET) /* ADC Same Point Time Register */

+#define SADC_ADWAIT		(SADC_BASE + SADC_ADWAIT_OFFSET) /* ADC Wait Time Register */

+#define SADC_ADTCH		(SADC_BASE + SADC_ADTCH_OFFSET)  /* ADC Touch Screen Data Register */

+#define SADC_ADVDAT		(SADC_BASE + SADC_ADVDAT_OFFSET) /* ADC VBAT Data Register */

+#define SADC_ADADAT		(SADC_BASE + SADC_ADADAT_OFFSET) /* ADC AUX Data Register */

+#define SADC_ADFLT		(SADC_BASE + SADC_ADFLT_OFFSET)  /* ADC Filter Register */

+#define SADC_ADCLK		(SADC_BASE + SADC_ADCLK_OFFSET)  /* ADC Clock Divide Register */

+

+

+/*

+ * SADC registers common define

+ */

+

+/* ADC Enable Register (ADENA) */

+#define ADENA_POWER		BIT7

+#define ADENA_SLP_MD		BIT6

+#define ADENA_TCHEN		BIT2

+#define ADENA_VBATEN		BIT1

+#define ADENA_AUXEN		BIT0

+

+/* ADC Configure Register (ADCFG) */

+#define ADCFG_SPZZ           	BIT31

+#define ADCFG_DMA_EN		BIT15

+

+#define ADCFG_XYZ_LSB		13

+#define ADCFG_XYZ_MASK		BITS_H2L(14, ADCFG_XYZ_LSB)

+ #define ADCFG_XYZ_XYS		(0x0 << ADCFG_XYZ_LSB)

+ #define ADCFG_XYZ_XYD		(0x1 << ADCFG_XYZ_LSB)

+ #define ADCFG_XYZ_XYZ1Z2	(0x2 << ADCFG_XYZ_LSB)

+

+#define ADCFG_SNUM_LSB		10

+#define ADCFG_SNUM_MASK		BITS_H2L(12, ADCFG_SNUM_LSB)

+ #define ADCFG_SNUM(n)          (((n) <= 6 ? ((n)-1) : ((n)-2)) << ADCFG_SNUM_LSB)

+

+#define ADCFG_CMD_LSB		0

+#define ADCFG_CMD_MASK		BITS_H2L(1, ADCFG_CMD_LSB)

+ #define ADCFG_CMD_AUX(n)	((n) << ADCFG_CMD_LSB)

+

+/* ADC Control Register (ADCCTRL) */

+#define ADCTRL_SLPENDM		BIT5

+#define ADCTRL_PENDM		BIT4

+#define ADCTRL_PENUM		BIT3

+#define ADCTRL_DTCHM		BIT2

+#define ADCTRL_VRDYM		BIT1

+#define ADCTRL_ARDYM		BIT0

+#define ADCTRL_MASK_ALL         (ADCTRL_SLPENDM | ADCTRL_PENDM | ADCTRL_PENUM \

+                                | ADCTRL_DTCHM | ADCTRL_VRDYM | ADCTRL_ARDYM)

+

+/*  ADC Status Register  (ADSTATE) */

+#define ADSTATE_SLP_RDY		BIT7

+#define ADSTATE_SLPEND		BIT5

+#define ADSTATE_PEND		BIT4

+#define ADSTATE_PENU		BIT3

+#define ADSTATE_DTCH		BIT2

+#define ADSTATE_VRDY		BIT1

+#define ADSTATE_ARDY		BIT0

+

+/* ADC Same Point Time Register (ADSAME) */

+#define ADSAME_SCNT_LSB		0

+#define ADSAME_SCNT_MASK	BITS_H2L(15, ADSAME_SCNT_LSB)

+

+/* ADC Wait Pen Down Time Register (ADWAIT) */

+#define ADWAIT_WCNT_LSB		0

+#define ADWAIT_WCNT_MASK	BITS_H2L(15, ADWAIT_WCNT_LSB)

+

+/* ADC Touch Screen Data Register (ADTCH) */

+#define ADTCH_TYPE1		BIT31

+#define ADTCH_TYPE0		BIT15

+

+#define ADTCH_DATA1_LSB		16

+#define ADTCH_DATA1_MASK	BITS_H2L(27, ADTCH_DATA1_LSB)

+

+#define ADTCH_DATA0_LSB		0

+#define ADTCH_DATA0_MASK	BITS_H2L(11, ADTCH_DATA0_LSB)

+

+/* ADC VBAT Date Register (ADVDAT) */

+#define ADVDAT_VDATA_LSB	0

+#define ADVDAT_VDATA_MASK	BITS_H2L(11, ADVDAT_VDATA_LSB)

+

+/* ADC AUX Data Register (ADADAT) */

+#define ADADAT_ADATA_LSB	0

+#define ADADAT_ADATA_MASK	BITS_H2L(11, ADADAT_ADATA_LSB)

+

+/*  ADC Clock Divide Register (ADCLK) */

+#define ADCLK_CLKDIV_MS_LSB	16

+#define ADCLK_CLKDIV_MS_MASK	BITS_H2L(31, ADCLK_CLKDIV_MS_LSB)

+

+#define ADCLK_CLKDIV_US_LSB	8

+#define ADCLK_CLKDIV_US_MASK	BITS_H2L(15, ADCLK_CLKDIV_US_LSB)

+

+#define ADCLK_CLKDIV_LSB	0

+#define ADCLK_CLKDIV_MASK	BITS_H2L(7, ADCLK_CLKDIV_LSB)

+

+/* ADC Filter Register (ADFLT) */

+#define ADFLT_FLT_EN		BIT15

+

+#define ADFLT_FLT_D_LSB		0

+#define ADFLT_FLT_D_MASK	BITS_H2L(11, ADFLT_FLT_D_LSB)

+

+

+#ifndef __MIPS_ASSEMBLER

+

+#define REG_SADC_ADENA          REG8(SADC_ADENA)

+#define REG_SADC_ADCFG          REG32(SADC_ADCFG)

+#define REG_SADC_ADCTRL         REG8(SADC_ADCTRL)

+#define REG_SADC_ADSTATE        REG8(SADC_ADSTATE)

+#define REG_SADC_ADSAME         REG16(SADC_ADSAME)

+#define REG_SADC_ADWAIT         REG16(SADC_ADWAIT)

+#define REG_SADC_ADTCH          REG32(SADC_ADTCH)

+#define REG_SADC_ADVDAT         REG16(SADC_ADVDAT)

+#define REG_SADC_ADADAT         REG16(SADC_ADADAT)

+#define REG_SADC_ADFLT          REG16(SADC_ADFLT)

+#define REG_SADC_ADCLK          REG32(SADC_ADCLK)

+

+

+typedef volatile struct

+{

+        unsigned char   ADENA;

+        unsigned char   ADENARSV[3];

+        unsigned int    ADCFG;

+        unsigned char   ADCTRL;

+        unsigned char   ADCTRLRSV[3];

+        unsigned char   ADSTATE;

+        unsigned char   ADSTATERSV[3];

+        unsigned short  ADSAME;

+        unsigned short  ADSAMERSV[1];

+        unsigned short  ADWAIT;

+        unsigned short  ADWAITRSV[1];

+        unsigned int    ADTCH;

+        unsigned short  ADVDAT;

+        unsigned short  ADVDATRSV[1];

+        unsigned short  ADADAT;

+        unsigned short  ADADATRSV[1];

+        unsigned short  ADFLT;

+        unsigned short  ADFLTRSV[1];

+        unsigned int    ADCLK;

+} JZ4760B_SADC, *PJZ4760B_SADC;

+

+#endif /* __MIPS_ASSEMBLER */

+

+#endif /* __JZ4760BSADC_H__ */

diff --git a/arch/mips/include/asm/mach-jz4760b/jz4760bscc.h b/arch/mips/include/asm/mach-jz4760b/jz4760bscc.h
new file mode 100644
index 00000000000..22c70331ae1
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4760b/jz4760bscc.h
@@ -0,0 +1,191 @@
+/*

+ * linux/include/asm-mips/mach-jz4760b/jz4760bscc.h

+ *

+ * JZ4760B SCC register definition.

+ *

+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

+ */

+

+#ifndef __JZ4760BSCC_H__

+#define __JZ4760BSCC_H__

+

+

+#define	SCC_BASE	0xB0040000

+

+/*************************************************************************

+ * SCC

+ *************************************************************************/

+#define	SCC_DR			(SCC_BASE + 0x000)

+#define	SCC_FDR			(SCC_BASE + 0x004)

+#define	SCC_CR			(SCC_BASE + 0x008)

+#define	SCC_SR			(SCC_BASE + 0x00C)

+#define	SCC_TFR			(SCC_BASE + 0x010)

+#define	SCC_EGTR		(SCC_BASE + 0x014)

+#define	SCC_ECR			(SCC_BASE + 0x018)

+#define	SCC_RTOR		(SCC_BASE + 0x01C)

+

+#define REG_SCC_DR		REG8(SCC_DR)

+#define REG_SCC_FDR		REG8(SCC_FDR)

+#define REG_SCC_CR		REG32(SCC_CR)

+#define REG_SCC_SR		REG16(SCC_SR)

+#define REG_SCC_TFR		REG16(SCC_TFR)

+#define REG_SCC_EGTR		REG8(SCC_EGTR)

+#define REG_SCC_ECR		REG32(SCC_ECR)

+#define REG_SCC_RTOR		REG8(SCC_RTOR)

+

+/* SCC FIFO Data Count Register (SCC_FDR) */

+

+#define SCC_FDR_EMPTY		0x00

+#define SCC_FDR_FULL		0x10

+

+/* SCC Control Register (SCC_CR) */

+

+#define SCC_CR_SCCE		(1 << 31)

+#define SCC_CR_TRS		(1 << 30)

+#define SCC_CR_T2R		(1 << 29)

+#define SCC_CR_FDIV_BIT		24

+#define SCC_CR_FDIV_MASK	(0x3 << SCC_CR_FDIV_BIT)

+  #define SCC_CR_FDIV_1		(0 << SCC_CR_FDIV_BIT) /* SCC_CLK frequency is the same as device clock */

+  #define SCC_CR_FDIV_2		(1 << SCC_CR_FDIV_BIT) /* SCC_CLK frequency is half of device clock */

+#define SCC_CR_FLUSH		(1 << 23)

+#define SCC_CR_TRIG_BIT		16

+#define SCC_CR_TRIG_MASK	(0x3 << SCC_CR_TRIG_BIT)

+  #define SCC_CR_TRIG_1		(0 << SCC_CR_TRIG_BIT) /* Receive/Transmit-FIFO Trigger is 1 */

+  #define SCC_CR_TRIG_4		(1 << SCC_CR_TRIG_BIT) /* Receive/Transmit-FIFO Trigger is 4 */

+  #define SCC_CR_TRIG_8		(2 << SCC_CR_TRIG_BIT) /* Receive/Transmit-FIFO Trigger is 8 */

+  #define SCC_CR_TRIG_14	(3 << SCC_CR_TRIG_BIT) /* Receive/Transmit-FIFO Trigger is 14 */

+#define SCC_CR_TP		(1 << 15)

+#define SCC_CR_CONV		(1 << 14)

+#define SCC_CR_TXIE		(1 << 13)

+#define SCC_CR_RXIE		(1 << 12)

+#define SCC_CR_TENDIE		(1 << 11)

+#define SCC_CR_RTOIE		(1 << 10)

+#define SCC_CR_ECIE		(1 << 9)

+#define SCC_CR_EPIE		(1 << 8)

+#define SCC_CR_RETIE		(1 << 7)

+#define SCC_CR_EOIE		(1 << 6)

+#define SCC_CR_TSEND		(1 << 3)

+#define SCC_CR_PX_BIT		1

+#define SCC_CR_PX_MASK		(0x3 << SCC_CR_PX_BIT)

+  #define SCC_CR_PX_NOT_SUPPORT	(0 << SCC_CR_PX_BIT) /* SCC does not support clock stop */

+  #define SCC_CR_PX_STOP_LOW	(1 << SCC_CR_PX_BIT) /* SCC_CLK stops at state low */

+  #define SCC_CR_PX_STOP_HIGH	(2 << SCC_CR_PX_BIT) /* SCC_CLK stops at state high */

+#define SCC_CR_CLKSTP		(1 << 0)

+

+/* SCC Status Register (SCC_SR) */

+

+#define SCC_SR_TRANS		(1 << 15)

+#define SCC_SR_ORER		(1 << 12)

+#define SCC_SR_RTO		(1 << 11)

+#define SCC_SR_PER		(1 << 10)

+#define SCC_SR_TFTG		(1 << 9)

+#define SCC_SR_RFTG		(1 << 8)

+#define SCC_SR_TEND		(1 << 7)

+#define SCC_SR_RETR_3		(1 << 4)

+#define SCC_SR_ECNTO		(1 << 0)

+

+

+#ifndef __MIPS_ASSEMBLER

+

+/***************************************************************************

+ * SCC

+ ***************************************************************************/

+

+#define __scc_enable()			( REG_SCC_CR |= SCC_CR_SCCE )

+#define __scc_disable()			( REG_SCC_CR &= ~SCC_CR_SCCE )

+

+#define __scc_set_tx_mode()		( REG_SCC_CR |= SCC_CR_TRS )

+#define __scc_set_rx_mode()		( REG_SCC_CR &= ~SCC_CR_TRS )

+

+#define __scc_enable_t2r()		( REG_SCC_CR |= SCC_CR_T2R )

+#define __scc_disable_t2r()		( REG_SCC_CR &= ~SCC_CR_T2R )

+

+#define __scc_clk_as_devclk()			\

+do {						\

+  REG_SCC_CR &= ~SCC_CR_FDIV_MASK;		\

+  REG_SCC_CR |= SCC_CR_FDIV_1;			\

+} while (0)

+

+#define __scc_clk_as_half_devclk()		\

+do {						\

+  REG_SCC_CR &= ~SCC_CR_FDIV_MASK;		\

+  REG_SCC_CR |= SCC_CR_FDIV_2;			\

+} while (0)

+

+/* n=1,4,8,14 */

+#define __scc_set_fifo_trigger(n)		\

+do {						\

+  REG_SCC_CR &= ~SCC_CR_TRIG_MASK;		\

+  REG_SCC_CR |= SCC_CR_TRIG_##n;		\

+} while (0)

+

+#define __scc_set_protocol(p)			\

+do {						\

+	if (p)					\

+	  	REG_SCC_CR |= SCC_CR_TP;	\

+	else					\

+	 	REG_SCC_CR &= ~SCC_CR_TP;	\

+} while (0)

+

+#define __scc_flush_fifo()		( REG_SCC_CR |= SCC_CR_FLUSH )

+

+#define __scc_set_invert_mode()		( REG_SCC_CR |= SCC_CR_CONV )

+#define __scc_set_direct_mode()		( REG_SCC_CR &= ~SCC_CR_CONV )

+

+#define SCC_ERR_INTRS \

+    ( SCC_CR_ECIE | SCC_CR_EPIE | SCC_CR_RETIE | SCC_CR_EOIE )

+#define SCC_ALL_INTRS \

+    ( SCC_CR_TXIE | SCC_CR_RXIE | SCC_CR_TENDIE | SCC_CR_RTOIE | \

+      SCC_CR_ECIE | SCC_CR_EPIE | SCC_CR_RETIE | SCC_CR_EOIE )

+

+#define __scc_enable_err_intrs()	( REG_SCC_CR |= SCC_ERR_INTRS )

+#define __scc_disable_err_intrs()	( REG_SCC_CR &= ~SCC_ERR_INTRS )

+

+#define SCC_ALL_ERRORS \

+    ( SCC_SR_ORER | SCC_SR_RTO | SCC_SR_PER | SCC_SR_RETR_3 | SCC_SR_ECNTO)

+

+#define __scc_clear_errors()		( REG_SCC_SR &= ~SCC_ALL_ERRORS )

+

+#define __scc_enable_all_intrs()	( REG_SCC_CR |= SCC_ALL_INTRS )

+#define __scc_disable_all_intrs()	( REG_SCC_CR &= ~SCC_ALL_INTRS )

+

+#define __scc_enable_tx_intr()		( REG_SCC_CR |= SCC_CR_TXIE | SCC_CR_TENDIE )

+#define __scc_disable_tx_intr()		( REG_SCC_CR &= ~(SCC_CR_TXIE | SCC_CR_TENDIE) )

+

+#define __scc_enable_rx_intr()		( REG_SCC_CR |= SCC_CR_RXIE)

+#define __scc_disable_rx_intr()		( REG_SCC_CR &= ~SCC_CR_RXIE)

+

+#define __scc_set_tsend()		( REG_SCC_CR |= SCC_CR_TSEND )

+#define __scc_clear_tsend()		( REG_SCC_CR &= ~SCC_CR_TSEND )

+

+#define __scc_set_clockstop()		( REG_SCC_CR |= SCC_CR_CLKSTP )

+#define __scc_clear_clockstop()		( REG_SCC_CR &= ~SCC_CR_CLKSTP )

+

+#define __scc_clockstop_low()			\

+do {						\

+  REG_SCC_CR &= ~SCC_CR_PX_MASK;		\

+  REG_SCC_CR |= SCC_CR_PX_STOP_LOW;		\

+} while (0)

+

+#define __scc_clockstop_high()			\

+do {						\

+  REG_SCC_CR &= ~SCC_CR_PX_MASK;		\

+  REG_SCC_CR |= SCC_CR_PX_STOP_HIGH;		\

+} while (0)

+

+/* SCC status checking */

+#define __scc_check_transfer_status()		( REG_SCC_SR & SCC_SR_TRANS )

+#define __scc_check_rx_overrun_error()		( REG_SCC_SR & SCC_SR_ORER )

+#define __scc_check_rx_timeout()		( REG_SCC_SR & SCC_SR_RTO )

+#define __scc_check_parity_error()		( REG_SCC_SR & SCC_SR_PER )

+#define __scc_check_txfifo_trigger()		( REG_SCC_SR & SCC_SR_TFTG )

+#define __scc_check_rxfifo_trigger()		( REG_SCC_SR & SCC_SR_RFTG )

+#define __scc_check_tx_end()			( REG_SCC_SR & SCC_SR_TEND )

+#define __scc_check_retx_3()			( REG_SCC_SR & SCC_SR_RETR_3 )

+#define __scc_check_ecnt_overflow()		( REG_SCC_SR & SCC_SR_ECNTO )

+

+

+#endif /* __MIPS_ASSEMBLER */

+

+#endif /* __JZ4760BSCC_H__ */

+

diff --git a/arch/mips/include/asm/mach-jz4760b/jz4760bssi.h b/arch/mips/include/asm/mach-jz4760b/jz4760bssi.h
new file mode 100644
index 00000000000..2e31a8cadfc
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4760b/jz4760bssi.h
@@ -0,0 +1,361 @@
+/*

+ * linux/include/asm-mips/mach-jz4760b/jz4760bssi.h

+ *

+ * JZ4760B SSI register definition.

+ *

+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

+ */

+

+#ifndef __JZ4760BSSI_H__

+#define __JZ4760BSSI_H__

+

+

+#define	SSI0_BASE	0xB0043000

+#define	SSI1_BASE	0xB0044000

+#define	SSI2_BASE	0xB0045000

+

+

+

+/*************************************************************************

+ * SSI (Synchronous Serial Interface)

+ *************************************************************************/

+/* n = 0, 1 (SSI0, SSI1) */

+#define	SSI_DR(n)		(SSI0_BASE + 0x000 + (n)*0x1000)

+#define	SSI_CR0(n)		(SSI0_BASE + 0x004 + (n)*0x1000)

+#define	SSI_CR1(n)		(SSI0_BASE + 0x008 + (n)*0x1000)

+#define	SSI_SR(n)		(SSI0_BASE + 0x00C + (n)*0x1000)

+#define	SSI_ITR(n)		(SSI0_BASE + 0x010 + (n)*0x1000)

+#define	SSI_ICR(n)		(SSI0_BASE + 0x014 + (n)*0x1000)

+#define	SSI_GR(n)		(SSI0_BASE + 0x018 + (n)*0x1000)

+

+#define	REG_SSI_DR(n)		REG32(SSI_DR(n))

+#define	REG_SSI_CR0(n)		REG16(SSI_CR0(n))

+#define	REG_SSI_CR1(n)		REG32(SSI_CR1(n))

+#define	REG_SSI_SR(n)		REG32(SSI_SR(n))

+#define	REG_SSI_ITR(n)		REG16(SSI_ITR(n))

+#define	REG_SSI_ICR(n)		REG8(SSI_ICR(n))

+#define	REG_SSI_GR(n)		REG16(SSI_GR(n))

+

+/* SSI Data Register (SSI_DR) */

+

+#define	SSI_DR_GPC_BIT		0

+#define	SSI_DR_GPC_MASK		(0x1ff << SSI_DR_GPC_BIT)

+

+#define SSI_MAX_FIFO_ENTRIES 	128 /* 128 txfifo and 128 rxfifo */

+

+/* SSI Control Register 0 (SSI_CR0) */

+

+#define SSI_CR0_SSIE		(1 << 15)

+#define SSI_CR0_TIE		(1 << 14)

+#define SSI_CR0_RIE		(1 << 13)

+#define SSI_CR0_TEIE		(1 << 12)

+#define SSI_CR0_REIE		(1 << 11)

+#define SSI_CR0_LOOP		(1 << 10)

+#define SSI_CR0_RFINE		(1 << 9)

+#define SSI_CR0_RFINC		(1 << 8)

+#define SSI_CR0_EACLRUN		(1 << 7) /* hardware auto clear underrun when TxFifo no empty */

+#define SSI_CR0_FSEL		(1 << 6)

+#define SSI_CR0_TFLUSH		(1 << 2)

+#define SSI_CR0_RFLUSH		(1 << 1)

+#define SSI_CR0_DISREV		(1 << 0)

+

+/* SSI Control Register 1 (SSI_CR1) */

+

+#define SSI_CR1_FRMHL_BIT	30

+#define SSI_CR1_FRMHL_MASK	(0x3 << SSI_CR1_FRMHL_BIT)

+  #define SSI_CR1_FRMHL_CELOW_CE2LOW	(0 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is low valid */

+  #define SSI_CR1_FRMHL_CEHIGH_CE2LOW	(1 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is low valid */

+  #define SSI_CR1_FRMHL_CELOW_CE2HIGH	(2 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid  and SSI_CE2_ is high valid */

+  #define SSI_CR1_FRMHL_CEHIGH_CE2HIGH	(3 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is high valid */

+#define SSI_CR1_TFVCK_BIT	28

+#define SSI_CR1_TFVCK_MASK	(0x3 << SSI_CR1_TFVCK_BIT)

+  #define SSI_CR1_TFVCK_0	  (0 << SSI_CR1_TFVCK_BIT)

+  #define SSI_CR1_TFVCK_1	  (1 << SSI_CR1_TFVCK_BIT)

+  #define SSI_CR1_TFVCK_2	  (2 << SSI_CR1_TFVCK_BIT)

+  #define SSI_CR1_TFVCK_3	  (3 << SSI_CR1_TFVCK_BIT)

+#define SSI_CR1_TCKFI_BIT	26

+#define SSI_CR1_TCKFI_MASK	(0x3 << SSI_CR1_TCKFI_BIT)

+  #define SSI_CR1_TCKFI_0	  (0 << SSI_CR1_TCKFI_BIT)

+  #define SSI_CR1_TCKFI_1	  (1 << SSI_CR1_TCKFI_BIT)

+  #define SSI_CR1_TCKFI_2	  (2 << SSI_CR1_TCKFI_BIT)

+  #define SSI_CR1_TCKFI_3	  (3 << SSI_CR1_TCKFI_BIT)

+#define SSI_CR1_LFST		(1 << 25)

+#define SSI_CR1_ITFRM		(1 << 24)

+#define SSI_CR1_UNFIN		(1 << 23)

+#define SSI_CR1_MULTS		(1 << 22)

+#define SSI_CR1_FMAT_BIT	20

+#define SSI_CR1_FMAT_MASK	(0x3 << SSI_CR1_FMAT_BIT)

+  #define SSI_CR1_FMAT_SPI	  (0 << SSI_CR1_FMAT_BIT) /* Motorola¡¯s SPI format */

+  #define SSI_CR1_FMAT_SSP	  (1 << SSI_CR1_FMAT_BIT) /* TI's SSP format */

+  #define SSI_CR1_FMAT_MW1	  (2 << SSI_CR1_FMAT_BIT) /* National Microwire 1 format */

+  #define SSI_CR1_FMAT_MW2	  (3 << SSI_CR1_FMAT_BIT) /* National Microwire 2 format */

+#define SSI_CR1_TTRG_BIT	16 /* SSI1 TX trigger */

+#define SSI_CR1_TTRG_MASK	(0xf << SSI_CR1_TTRG_BIT)

+#define SSI_CR1_MCOM_BIT	12

+#define SSI_CR1_MCOM_MASK	(0xf << SSI_CR1_MCOM_BIT)

+  #define SSI_CR1_MCOM_1BIT	  (0x0 << SSI_CR1_MCOM_BIT) /* 1-bit command selected */

+  #define SSI_CR1_MCOM_2BIT	  (0x1 << SSI_CR1_MCOM_BIT) /* 2-bit command selected */

+  #define SSI_CR1_MCOM_3BIT	  (0x2 << SSI_CR1_MCOM_BIT) /* 3-bit command selected */

+  #define SSI_CR1_MCOM_4BIT	  (0x3 << SSI_CR1_MCOM_BIT) /* 4-bit command selected */

+  #define SSI_CR1_MCOM_5BIT	  (0x4 << SSI_CR1_MCOM_BIT) /* 5-bit command selected */

+  #define SSI_CR1_MCOM_6BIT	  (0x5 << SSI_CR1_MCOM_BIT) /* 6-bit command selected */

+  #define SSI_CR1_MCOM_7BIT	  (0x6 << SSI_CR1_MCOM_BIT) /* 7-bit command selected */

+  #define SSI_CR1_MCOM_8BIT	  (0x7 << SSI_CR1_MCOM_BIT) /* 8-bit command selected */

+  #define SSI_CR1_MCOM_9BIT	  (0x8 << SSI_CR1_MCOM_BIT) /* 9-bit command selected */

+  #define SSI_CR1_MCOM_10BIT	  (0x9 << SSI_CR1_MCOM_BIT) /* 10-bit command selected */

+  #define SSI_CR1_MCOM_11BIT	  (0xA << SSI_CR1_MCOM_BIT) /* 11-bit command selected */

+  #define SSI_CR1_MCOM_12BIT	  (0xB << SSI_CR1_MCOM_BIT) /* 12-bit command selected */

+  #define SSI_CR1_MCOM_13BIT	  (0xC << SSI_CR1_MCOM_BIT) /* 13-bit command selected */

+  #define SSI_CR1_MCOM_14BIT	  (0xD << SSI_CR1_MCOM_BIT) /* 14-bit command selected */

+  #define SSI_CR1_MCOM_15BIT	  (0xE << SSI_CR1_MCOM_BIT) /* 15-bit command selected */

+  #define SSI_CR1_MCOM_16BIT	  (0xF << SSI_CR1_MCOM_BIT) /* 16-bit command selected */

+#define SSI_CR1_RTRG_BIT	8 /* SSI RX trigger */

+#define SSI_CR1_RTRG_MASK	(0xf << SSI_CR1_RTRG_BIT)

+#define SSI_CR1_FLEN_BIT	4

+#define SSI_CR1_FLEN_MASK	(0xf << SSI_CR1_FLEN_BIT)

+  #define SSI_CR1_FLEN_2BIT	  (0x0 << SSI_CR1_FLEN_BIT)

+  #define SSI_CR1_FLEN_3BIT	  (0x1 << SSI_CR1_FLEN_BIT)

+  #define SSI_CR1_FLEN_4BIT	  (0x2 << SSI_CR1_FLEN_BIT)

+  #define SSI_CR1_FLEN_5BIT	  (0x3 << SSI_CR1_FLEN_BIT)

+  #define SSI_CR1_FLEN_6BIT	  (0x4 << SSI_CR1_FLEN_BIT)

+  #define SSI_CR1_FLEN_7BIT	  (0x5 << SSI_CR1_FLEN_BIT)

+  #define SSI_CR1_FLEN_8BIT	  (0x6 << SSI_CR1_FLEN_BIT)

+  #define SSI_CR1_FLEN_9BIT	  (0x7 << SSI_CR1_FLEN_BIT)

+  #define SSI_CR1_FLEN_10BIT	  (0x8 << SSI_CR1_FLEN_BIT)

+  #define SSI_CR1_FLEN_11BIT	  (0x9 << SSI_CR1_FLEN_BIT)

+  #define SSI_CR1_FLEN_12BIT	  (0xA << SSI_CR1_FLEN_BIT)

+  #define SSI_CR1_FLEN_13BIT	  (0xB << SSI_CR1_FLEN_BIT)

+  #define SSI_CR1_FLEN_14BIT	  (0xC << SSI_CR1_FLEN_BIT)

+  #define SSI_CR1_FLEN_15BIT	  (0xD << SSI_CR1_FLEN_BIT)

+  #define SSI_CR1_FLEN_16BIT	  (0xE << SSI_CR1_FLEN_BIT)

+  #define SSI_CR1_FLEN_17BIT	  (0xF << SSI_CR1_FLEN_BIT)

+#define SSI_CR1_PHA		(1 << 1)

+#define SSI_CR1_POL		(1 << 0)

+

+/* SSI Status Register (SSI_SR) */

+

+#define SSI_SR_TFIFONUM_BIT	16

+#define SSI_SR_TFIFONUM_MASK	(0xff << SSI_SR_TFIFONUM_BIT)

+#define SSI_SR_RFIFONUM_BIT	8

+#define SSI_SR_RFIFONUM_MASK	(0xff << SSI_SR_RFIFONUM_BIT)

+#define SSI_SR_END		(1 << 7)

+#define SSI_SR_BUSY		(1 << 6)

+#define SSI_SR_TFF		(1 << 5)

+#define SSI_SR_RFE		(1 << 4)

+#define SSI_SR_TFHE		(1 << 3)

+#define SSI_SR_RFHF		(1 << 2)

+#define SSI_SR_UNDR		(1 << 1)

+#define SSI_SR_OVER		(1 << 0)

+

+/* SSI Interval Time Control Register (SSI_ITR) */

+

+#define	SSI_ITR_CNTCLK		(1 << 15)

+#define SSI_ITR_IVLTM_BIT	0

+#define SSI_ITR_IVLTM_MASK	(0x7fff << SSI_ITR_IVLTM_BIT)

+

+

+#ifndef __MIPS_ASSEMBLER

+

+/***************************************************************************

+ * SSI (Synchronous Serial Interface)

+ ***************************************************************************/

+/* n = 0, 1 (SSI0, SSI1) */

+#define __ssi_enable(n) 	( REG_SSI_CR0(n) |= SSI_CR0_SSIE )

+#define __ssi_disable(n) 	( REG_SSI_CR0(n) &= ~SSI_CR0_SSIE )

+#define __ssi_select_ce(n) 	( REG_SSI_CR0(n) &= ~SSI_CR0_FSEL )

+

+#define __ssi_normal_mode(n) ( REG_SSI_ITR(n) &= ~SSI_ITR_IVLTM_MASK )

+

+#define __ssi_select_ce2(n) 		\

+do { 					\

+	REG_SSI_CR0(n) |= SSI_CR0_FSEL; 	\

+	REG_SSI_CR1(n) &= ~SSI_CR1_MULTS;	\

+} while (0)

+

+#define __ssi_select_gpc(n) 			\

+do { 						\

+	REG_SSI_CR0(n) &= ~SSI_CR0_FSEL;	\

+	REG_SSI_CR1(n) |= SSI_CR1_MULTS;	\

+} while (0)

+

+#define __ssi_underrun_auto_clear(n) 		\

+do { 						\

+	REG_SSI_CR0(n) |= SSI_CR0_EACLRUN; 	\

+} while (0)

+

+#define __ssi_underrun_clear_manually(n) 	\

+do { 						\

+	REG_SSI_CR0(n) &= ~SSI_CR0_EACLRUN; 	\

+} while (0)

+

+#define __ssi_enable_tx_intr(n)					\

+	( REG_SSI_CR0(n) |= SSI_CR0_TIE | SSI_CR0_TEIE )

+

+#define __ssi_disable_tx_intr(n)				\

+	( REG_SSI_CR0(n) &= ~(SSI_CR0_TIE | SSI_CR0_TEIE) )

+

+#define __ssi_enable_rx_intr(n)					\

+	( REG_SSI_CR0(n) |= SSI_CR0_RIE | SSI_CR0_REIE )

+

+#define __ssi_disable_rx_intr(n)				\

+	( REG_SSI_CR0(n) &= ~(SSI_CR0_RIE | SSI_CR0_REIE) )

+

+#define __ssi_enable_txfifo_half_empty_intr(n)  \

+	( REG_SSI_CR0(n) |= SSI_CR0_TIE )

+#define __ssi_disable_txfifo_half_empty_intr(n)	\

+	( REG_SSI_CR0(n) &= ~SSI_CR0_TIE )

+#define __ssi_enable_tx_error_intr(n)		\

+	( REG_SSI_CR0(n) |= SSI_CR0_TEIE )

+#define __ssi_disable_tx_error_intr(n)		\

+	( REG_SSI_CR0(n) &= ~SSI_CR0_TEIE )

+#define __ssi_enable_rxfifo_half_full_intr(n)	\

+	( REG_SSI_CR0(n) |= SSI_CR0_RIE )

+#define __ssi_disable_rxfifo_half_full_intr(n)  \

+	( REG_SSI_CR0(n) &= ~SSI_CR0_RIE )

+#define __ssi_enable_rx_error_intr(n)		\

+	( REG_SSI_CR0(n) |= SSI_CR0_REIE )

+#define __ssi_disable_rx_error_intr(n)		\

+	( REG_SSI_CR0(n) &= ~SSI_CR0_REIE )

+

+#define __ssi_enable_loopback(n)  ( REG_SSI_CR0(n) |= SSI_CR0_LOOP )

+#define __ssi_disable_loopback(n) ( REG_SSI_CR0(n) &= ~SSI_CR0_LOOP )

+

+#define __ssi_enable_receive(n)   ( REG_SSI_CR0(n) &= ~SSI_CR0_DISREV )

+#define __ssi_disable_receive(n)  ( REG_SSI_CR0(n) |= SSI_CR0_DISREV )

+

+#define __ssi_finish_receive(n)					\

+	( REG_SSI_CR0(n) |= (SSI_CR0_RFINE | SSI_CR0_RFINC) )

+

+#define __ssi_disable_recvfinish(n)				\

+	( REG_SSI_CR0(n) &= ~(SSI_CR0_RFINE | SSI_CR0_RFINC) )

+

+#define __ssi_flush_txfifo(n)   	( REG_SSI_CR0(n) |= SSI_CR0_TFLUSH )

+#define __ssi_flush_rxfifo(n)   	( REG_SSI_CR0(n) |= SSI_CR0_RFLUSH )

+

+#define __ssi_flush_fifo(n)					\

+	( REG_SSI_CR0(n) |= SSI_CR0_TFLUSH | SSI_CR0_RFLUSH )

+

+#define __ssi_finish_transmit(n) 	( REG_SSI_CR1(n) &= ~SSI_CR1_UNFIN )

+#define __ssi_wait_transmit(n) 		( REG_SSI_CR1(n) |= SSI_CR1_UNFIN )

+#define __ssi_use_busy_wait_mode(n) 	__ssi_wait_transmit(n)

+#define __ssi_unset_busy_wait_mode(n) 	__ssi_finish_transmit(n)

+

+#define __ssi_spi_format(n)						\

+	do {								\

+		REG_SSI_CR1(n) &= ~SSI_CR1_FMAT_MASK; 			\

+		REG_SSI_CR1(n) |= SSI_CR1_FMAT_SPI;			\

+		REG_SSI_CR1(n) &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK); \

+		REG_SSI_CR1(n) |= (SSI_CR1_TFVCK_1 | SSI_CR1_TCKFI_1);	\

+	} while (0)

+

+/* TI's SSP format, must clear SSI_CR1.UNFIN */

+#define __ssi_ssp_format(n)						\

+	do { 								\

+		REG_SSI_CR1(n) &= ~(SSI_CR1_FMAT_MASK | SSI_CR1_UNFIN);	\

+		REG_SSI_CR1(n) |= SSI_CR1_FMAT_SSP;			\

+	} while (0)

+

+/* National's Microwire format, must clear SSI_CR0.RFINE, and set max delay */

+#define __ssi_microwire_format(n)					\

+	do {								\

+		REG_SSI_CR1(n) &= ~SSI_CR1_FMAT_MASK; 			\

+		REG_SSI_CR1(n) |= SSI_CR1_FMAT_MW1;			\

+		REG_SSI_CR1(n) &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK); \

+		REG_SSI_CR1(n) |= (SSI_CR1_TFVCK_3 | SSI_CR1_TCKFI_3);	\

+		REG_SSI_CR0(n) &= ~SSI_CR0_RFINE;			\

+	} while (0)

+

+/* CE# level (FRMHL), CE# in interval time (ITFRM),

+   clock phase and polarity (PHA POL),

+   interval time (SSIITR), interval characters/frame (SSIICR) */

+

+/* frmhl,endian,mcom,flen,pha,pol MASK */

+#define SSICR1_MISC_MASK 					\

+	( SSI_CR1_FRMHL_MASK | SSI_CR1_LFST | SSI_CR1_MCOM_MASK	\

+	  | SSI_CR1_FLEN_MASK | SSI_CR1_PHA | SSI_CR1_POL )

+

+#define __ssi_spi_set_misc(n,frmhl,endian,flen,mcom,pha,pol)		\

+	do {								\

+		REG_SSI_CR1(n) &= ~SSICR1_MISC_MASK;			\

+		REG_SSI_CR1(n) |= ((frmhl) << 30) | ((endian) << 25) | 	\

+			(((mcom) - 1) << 12) | (((flen) - 2) << 4) | 	\

+			((pha) << 1) | (pol); 				\

+	} while(0)

+

+/* Transfer with MSB or LSB first */

+#define __ssi_set_msb(n) ( REG_SSI_CR1(n) &= ~SSI_CR1_LFST )

+#define __ssi_set_lsb(n) ( REG_SSI_CR1(n) |= SSI_CR1_LFST )

+

+#define __ssi_set_frame_length(n, m)					\

+	REG_SSI_CR1(n) = (REG_SSI_CR1(n) & ~SSI_CR1_FLEN_MASK) | (((m) - 2) << 4)

+

+/* m = 1 - 16 */

+#define __ssi_set_microwire_command_length(n,m)				\

+	( REG_SSI_CR1(n) = ((REG_SSI_CR1(n) & ~SSI_CR1_MCOM_MASK) | SSI_CR1_MCOM_##m##BIT) )

+

+/* Set the clock phase for SPI */

+#define __ssi_set_spi_clock_phase(n, m)					\

+	( REG_SSI_CR1(n) = ((REG_SSI_CR1(n) & ~SSI_CR1_PHA) | (((m)&0x1)<< 1)))

+

+/* Set the clock polarity for SPI */

+#define __ssi_set_spi_clock_polarity(n, p)				\

+	( REG_SSI_CR1(n) = ((REG_SSI_CR1(n) & ~SSI_CR1_POL) | ((p)&0x1)) )

+

+/* SSI tx trigger, m = i x 8 */

+#define __ssi_set_tx_trigger(n, m)				\

+	do {							\

+		REG_SSI_CR1(n) &= ~SSI_CR1_TTRG_MASK;		\

+		REG_SSI_CR1(n) |= ((m)/8)<<SSI_CR1_TTRG_BIT;	\

+	} while (0)

+

+/* SSI rx trigger, m = i x 8 */

+#define __ssi_set_rx_trigger(n, m)				\

+	do {							\

+		REG_SSI_CR1(n) &= ~SSI_CR1_RTRG_MASK;		\

+		REG_SSI_CR1(n) |= ((m)/8)<<SSI_CR1_RTRG_BIT;	\

+	} while (0)

+

+#define __ssi_get_txfifo_count(n)					\

+	( (REG_SSI_SR(n) & SSI_SR_TFIFONUM_MASK) >> SSI_SR_TFIFONUM_BIT )

+

+#define __ssi_get_rxfifo_count(n)					\

+	( (REG_SSI_SR(n) & SSI_SR_RFIFONUM_MASK) >> SSI_SR_RFIFONUM_BIT )

+

+#define __ssi_transfer_end(n)		( REG_SSI_SR(n) & SSI_SR_END )

+#define __ssi_is_busy(n)		( REG_SSI_SR(n) & SSI_SR_BUSY )

+

+#define __ssi_txfifo_full(n)		( REG_SSI_SR(n) & SSI_SR_TFF )

+#define __ssi_rxfifo_empty(n)		( REG_SSI_SR(n) & SSI_SR_RFE )

+#define __ssi_rxfifo_half_full(n)	( REG_SSI_SR(n) & SSI_SR_RFHF )

+#define __ssi_txfifo_half_empty(n)	( REG_SSI_SR(n) & SSI_SR_TFHE )

+#define __ssi_underrun(n)		( REG_SSI_SR(n) & SSI_SR_UNDR )

+#define __ssi_overrun(n)		( REG_SSI_SR(n) & SSI_SR_OVER )

+#define __ssi_clear_underrun(n)		( REG_SSI_SR(n) = ~SSI_SR_UNDR )

+#define __ssi_clear_overrun(n)		( REG_SSI_SR(n) = ~SSI_SR_OVER )

+#define __ssi_clear_errors(n)		( REG_SSI_SR(n) &= ~(SSI_SR_UNDR | SSI_SR_OVER) )

+

+#define __ssi_set_clk(n, dev_clk, ssi_clk)			\

+	( REG_SSI_GR(n) = (dev_clk) / (2*(ssi_clk)) - 1 )

+

+#define __ssi_receive_data(n) 		REG_SSI_DR(n)

+#define __ssi_transmit_data(n, v) 	(REG_SSI_DR(n) = (v))

+

+

+#define __ssi_set_grdiv(n,v)			(REG_SSI_GR(n) = v)

+#define __ssi_get_grdiv(n)				(REG_SSI_GR(n))

+

+#define __ssi_txfifo_half_empty_intr(n)  \

+	( REG_SSI_CR0(n) & SSI_CR0_TIE )

+#define __ssi_rxfifo_half_full_intr(n)	\

+	( REG_SSI_CR0(n) & SSI_CR0_RIE )

+	

+#define __ssi_tx_error_intr(n)		\

+	( REG_SSI_CR0(n) & SSI_CR0_TEIE )

+#define __ssi_rx_error_intr(n)		\

+	( REG_SSI_CR0(n) & SSI_CR0_REIE )	

+

+

+#endif /* __MIPS_ASSEMBLER */

+

+#endif /* __JZ4760BSSI_H__ */

+

diff --git a/arch/mips/include/asm/mach-jz4760b/jz4760btcu.h b/arch/mips/include/asm/mach-jz4760b/jz4760btcu.h
new file mode 100644
index 00000000000..c590f06625f
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4760b/jz4760btcu.h
@@ -0,0 +1,305 @@
+/*

+ * jz4760btcu.h

+ * JZ4760B TCU register definition

+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

+ *

+ * Author: fyliao@ingenic.cn

+ */

+

+#ifndef __JZ4760BTCU_H__

+#define __JZ4760BTCU_H__

+

+

+/*

+ * Timer and counter unit module(TCU) address definition

+ */

+#define	TCU_BASE		0xb0002000

+

+/* TCU group offset */

+#define TCU_GOS			0x10

+

+/* TCU total channel number */

+#define TCU_CHANNEL_NUM		8

+

+

+/*

+ * TCU registers offset definition

+ */

+#define TCU_TER_OFFSET		(0x10)  /* r, 16, 0x0000     */

+#define TCU_TESR_OFFSET		(0x14)  /* w, 16, 0x????     */

+#define TCU_TECR_OFFSET		(0x18)  /* w, 16, 0x????     */

+#define TCU_TSR_OFFSET		(0x1c)  /* r, 32, 0x00000000 */

+#define TCU_TFR_OFFSET		(0x20)  /* r, 32, 0x003F003F */

+#define TCU_TFSR_OFFSET		(0x24)  /* w, 32, 0x???????? */

+#define TCU_TFCR_OFFSET		(0x28)  /* w, 32, 0x???????? */

+#define TCU_TSSR_OFFSET		(0x2c)  /* w, 32, 0x00000000 */

+#define TCU_TMR_OFFSET		(0x30)  /* r, 32, 0x00000000 */

+#define TCU_TMSR_OFFSET		(0x34)  /* w, 32, 0x???????? */

+#define TCU_TMCR_OFFSET		(0x38)  /* w, 32, 0x???????? */

+#define TCU_TSCR_OFFSET		(0x3c)  /* w, 32, 0x0000     */

+

+#define TCU_TDFR_OFFSET		(0x40)  /* rw,16, 0x????     */

+#define TCU_TDHR_OFFSET		(0x44)  /* rw,16, 0x????     */

+#define TCU_TCNT_OFFSET		(0x48)  /* rw,16, 0x????     */

+#define TCU_TCSR_OFFSET		(0x4c)  /* rw,16, 0x0000     */

+

+#define TCU_TSTR_OFFSET		(0xf0)  /* r, 32, 0x00000000 */

+#define TCU_TSTSR_OFFSET	(0xf4)  /* w, 32, 0x???????? */

+#define TCU_TSTCR_OFFSET	(0xf8)  /* w, 32, 0x???????? */

+

+

+/*

+ * TCU registers address definition

+ */

+#define TCU_TER		(TCU_BASE + TCU_TER_OFFSET)

+#define TCU_TESR	(TCU_BASE + TCU_TESR_OFFSET)

+#define TCU_TECR	(TCU_BASE + TCU_TECR_OFFSET)

+#define TCU_TSR		(TCU_BASE + TCU_TSR_OFFSET)

+#define TCU_TFR		(TCU_BASE + TCU_TFR_OFFSET)

+#define TCU_TFSR	(TCU_BASE + TCU_TFSR_OFFSET)

+#define TCU_TFCR	(TCU_BASE + TCU_TFCR_OFFSET)

+#define TCU_TSSR	(TCU_BASE + TCU_TSSR_OFFSET)

+#define TCU_TMR		(TCU_BASE + TCU_TMR_OFFSET)

+#define TCU_TMSR	(TCU_BASE + TCU_TMSR_OFFSET)

+#define TCU_TMCR	(TCU_BASE + TCU_TMCR_OFFSET)

+#define TCU_TSCR	(TCU_BASE + TCU_TSCR_OFFSET)

+#define TCU_TSTR	(TCU_BASE + TCU_TSTR_OFFSET)

+#define TCU_TSTSR	(TCU_BASE + TCU_TSTSR_OFFSET)

+#define TCU_TSTCR	(TCU_BASE + TCU_TSTCR_OFFSET)

+

+/* n is the TCU channel index (0 - 7) */

+#define TCU_TDFR(n)	(TCU_BASE + (n) * TCU_GOS + TCU_TDFR_OFFSET)

+#define TCU_TDHR(n)	(TCU_BASE + (n) * TCU_GOS + TCU_TDHR_OFFSET)

+#define TCU_TCNT(n)	(TCU_BASE + (n) * TCU_GOS + TCU_TCNT_OFFSET)

+#define TCU_TCSR(n)	(TCU_BASE + (n) * TCU_GOS + TCU_TCSR_OFFSET)

+

+

+/*

+ * TCU registers bit field common define

+ */

+

+/* When n is NOT less than TCU_CHANNEL_NUM, change to TCU_CHANNEL_NUM - 1 */

+#define __TIMER(n)	(1 << ((n) < TCU_CHANNEL_NUM ? (n) : (TCU_CHANNEL_NUM - 1)))

+

+/* Timer counter enable register(TER) */

+#define TER_OSTEN	BIT15

+#define TER_TCEN(n)	__TIMER(n)

+

+/* Timer counter enable set register(TESR) */

+#define TESR_OST	BIT15

+#define TESR_TIMER(n)	__TIMER(n)

+

+/* Timer counter enable clear register(TECR) */

+#define TECR_OST	BIT15

+#define TECR_TIMER(n)	__TIMER(n)

+

+/* Timer stop register(TSR) */

+#define TSR_WDT_STOP		BIT16

+#define TSR_OST_STOP		BIT15

+#define TSR_TIMER_STOP(n)	__TIMER(n)

+

+/* Timer stop set register(TSSR) */

+#define TSSR_WDT		BIT16

+#define TSSR_OST		BIT15

+#define TSSR_TIMER(n)		__TIMER(n)

+

+/* Timer stop clear register(TSCR) */

+#define TSCR_WDT		BIT16

+#define TSCR_OST		BIT15

+#define TSSR_TIMER(n)		__TIMER(n)

+

+/* Timer flag register(TFR) */

+#define TFR_HFLAG(n)	(__TIMER(n) << 16)

+#define TFR_OSTFLAG	BIT15

+#define TFR_FFLAG(n)	__TIMER(n)

+

+/* Timer flag set register(TFSR) */

+#define TFSR_HFLAG(n)	(__TIMER(n) << 16)

+#define TFSR_OSTFLAG	BIT15

+#define TFSR_FFLAG(n)	__TIMER(n)

+

+/* Timer flag clear register(TFCR) */

+#define TFCR_HFLAG(n)	(__TIMER(n) << 16)

+#define TFCR_OSTFLAG	BIT15

+#define TFCR_FFLAG(n)	(__TIMER(n))

+

+/* Timer mast register(TMR) */

+#define TMR_HMASK(n)	(__TIMER(n) << 16)

+#define TMR_OSTMASK	BIT15

+#define TMR_FMASK(n)	(__TIMER(n))

+

+/* Timer mask set register(TMSR) */

+#define TMSR_HMASK(n)	(__TIMER(n) << 16)

+#define TMSR_OSTMASK	BIT15

+#define TMSR_FMASK(n)	(__TIMER(n))

+

+/* Timer mask clear register(TMCR) */

+#define TMCR_HMASK(n)	(__TIMER(n) << 16)

+#define TMCR_OSTMASK	BIT15

+#define TMCR_FMASK(n)	(__TIMER(n))

+

+/* Timer control register(TCSR) */

+#define TCSR_CLRZ		BIT10

+#define TCSR_SD_ABRUPT		BIT9

+#define TCSR_INITL_HIGH		BIT8

+#define TCSR_PWM_EN		BIT7

+#define TCSR_PWM_IN_EN		BIT6

+#define TCSR_EXT_EN		BIT2

+#define TCSR_RTC_EN		BIT1

+#define TCSR_PCK_EN		BIT0

+

+#define TCSR_PRESCALE_LSB	3

+#define TCSR_PRESCALE_MASK	BITS_H2L(5, TCSR_PRESCALE_LSB)

+#define TCSR_PRESCALE1		(0x0 << TCSR_PRESCALE_LSB)

+#define TCSR_PRESCALE4		(0x1 << TCSR_PRESCALE_LSB)

+#define TCSR_PRESCALE16		(0x2 << TCSR_PRESCALE_LSB)

+#define TCSR_PRESCALE64		(0x3 << TCSR_PRESCALE_LSB)

+#define TCSR_PRESCALE256	(0x4 << TCSR_PRESCALE_LSB)

+#define TCSR_PRESCALE1024	(0x5 << TCSR_PRESCALE_LSB)

+

+/* Timer data full register(TDFR) */

+#define TDFR_TDFR_LSB		0

+#define TDFR_TDFR_MASK		BITS_H2L(15, TDFR_TDFR_LSB)

+

+/* Timer data half register(TDHR) */

+#define TDHR_TDHR_LSB		0

+#define TDHR_TDHR_MASK		BITS_H2L(15, TDHR_TDHR_LSB)

+

+/* Timer counter register(TCNT) */

+#define TCNT_TCNT_LSB		0

+#define TCNT_TCNT_MASK		BITS_H2L(15, TCNT_TCNT_LSB)

+

+/* Timer status register(TSTR) */

+#define TSTR_REAL2	BIT18

+#define TSTR_REAL1	BIT17

+#define TSTR_BUSY2	BIT2

+#define TSTR_BUSY1	BIT1

+

+/* Timer status set register(TSTSR) */

+#define TSTSR_REALS2	BIT18

+#define TSTSR_REALS1	BIT17

+#define TSTSR_BUSYS2	BIT2

+#define TSTSR_BUSYS1	BIT1

+

+/* Timer status clear register(TSTCR) */

+#define TSTCR_REALC2	BIT18

+#define TSTCR_REALC1	BIT17

+#define TSTCR_BUSYC2	BIT2

+#define TSTCR_BUSYC1	BIT1

+

+

+#ifndef __MIPS_ASSEMBLER

+

+#define REG_TCU_TER	REG16(TCU_TER)

+#define REG_TCU_TESR	REG16(TCU_TESR)

+#define REG_TCU_TECR	REG16(TCU_TECR)

+#define REG_TCU_TSR	REG32(TCU_TSR)

+#define REG_TCU_TFR	REG32(TCU_TFR)

+#define REG_TCU_TFSR	REG32(TCU_TFSR)

+#define REG_TCU_TFCR	REG32(TCU_TFCR)

+#define REG_TCU_TSSR	REG32(TCU_TSSR)

+#define REG_TCU_TMR	REG32(TCU_TMR)

+#define REG_TCU_TMSR	REG32(TCU_TMSR)

+#define REG_TCU_TMCR	REG32(TCU_TMCR)

+#define REG_TCU_TSCR	REG32(TCU_TSCR)

+#define REG_TCU_TSTR	REG32(TCU_TSTR)

+#define REG_TCU_TSTSR	REG32(TCU_TSTSR)

+#define REG_TCU_TSTCR	REG32(TCU_TSTCR)

+

+#define REG_TCU_TDFR(n)	REG16(TCU_TDFR(n))

+#define REG_TCU_TDHR(n)	REG16(TCU_TDHR(n))

+#define REG_TCU_TCNT(n)	REG16(TCU_TCNT(n))

+#define REG_TCU_TCSR(n)	REG16(TCU_TCSR(n))

+

+

+// where 'n' is the TCU channel

+#define __tcu_select_extalclk(n) \

+	(REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCSR_EXT_EN | TCSR_RTC_EN | TCSR_PCK_EN)) | TCSR_EXT_EN)

+#define __tcu_select_rtcclk(n) \

+	(REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCSR_EXT_EN | TCSR_RTC_EN | TCSR_PCK_EN)) | TCSR_RTC_EN)

+#define __tcu_select_pclk(n) \

+	(REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCSR_EXT_EN | TCSR_RTC_EN | TCSR_PCK_EN)) | TCSR_PCK_EN)

+#define __tcu_disable_pclk(n) \

+	REG_TCU_TCSR(n) = (REG_TCU_TCSR((n)) & ~TCSR_PCK_EN);

+#define __tcu_select_clk_div1(n) \

+	(REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCSR_PRESCALE_MASK) | TCSR_PRESCALE1)

+#define __tcu_select_clk_div4(n) \

+	(REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCSR_PRESCALE_MASK) | TCSR_PRESCALE4)

+#define __tcu_select_clk_div16(n) \

+	(REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCSR_PRESCALE_MASK) | TCSR_PRESCALE16)

+#define __tcu_select_clk_div64(n) \

+	(REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCSR_PRESCALE_MASK) | TCSR_PRESCALE64)

+#define __tcu_select_clk_div256(n) \

+	(REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCSR_PRESCALE_MASK) | TCSR_PRESCALE256)

+#define __tcu_select_clk_div1024(n) \

+	(REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCSR_PRESCALE_MASK) | TCSR_PRESCALE1024)

+

+#define __tcu_enable_pwm_output(n)	(REG_TCU_TCSR((n)) |= TCSR_PWM_EN)

+#define __tcu_disable_pwm_output(n)	(REG_TCU_TCSR((n)) &= ~TCSR_PWM_EN)

+

+#define __tcu_init_pwm_output_high(n)	(REG_TCU_TCSR((n)) |= TCSR_INITL_HIGH)

+#define __tcu_init_pwm_output_low(n)	(REG_TCU_TCSR((n)) &= ~TCSR_INITL_HIGH)

+

+#define __tcu_set_pwm_output_shutdown_graceful(n)	(REG_TCU_TCSR((n)) &= ~TCSR_SD_ABRUPT)

+#define __tcu_set_pwm_output_shutdown_abrupt(n)		(REG_TCU_TCSR((n)) |= TCSR_SD_ABRUPT)

+

+#define __tcu_clear_counter_to_zero(n)	(REG_TCU_TCSR((n)) |= TCSR_CLRZ)

+

+#define __tcu_ost_enabled()		(REG_TCU_TER & TER_OSTEN)

+#define __tcu_enable_ost()		(REG_TCU_TESR = TESR_OST)

+#define __tcu_disable_ost()		(REG_TCU_TECR = TECR_OST)

+

+#define __tcu_counter_enabled(n)	(REG_TCU_TER & (1 << (n)))

+#define __tcu_start_counter(n)		(REG_TCU_TESR |= (1 << (n)))

+#define __tcu_stop_counter(n)		(REG_TCU_TECR |= (1 << (n)))

+

+#define __tcu_half_match_flag(n)	(REG_TCU_TFR & (1 << ((n) + 16)))

+#define __tcu_full_match_flag(n)	(REG_TCU_TFR & (1 << (n)))

+#define __tcu_set_half_match_flag(n)	(REG_TCU_TFSR = (1 << ((n) + 16)))

+#define __tcu_set_full_match_flag(n)	(REG_TCU_TFSR = (1 << (n)))

+#define __tcu_clear_half_match_flag(n)	(REG_TCU_TFCR = (1 << ((n) + 16)))

+#define __tcu_clear_full_match_flag(n)	(REG_TCU_TFCR = (1 << (n)))

+#define __tcu_mask_half_match_irq(n)	(REG_TCU_TMSR = (1 << ((n) + 16)))

+#define __tcu_mask_full_match_irq(n)	(REG_TCU_TMSR = (1 << (n)))

+#define __tcu_unmask_half_match_irq(n)	(REG_TCU_TMCR = (1 << ((n) + 16)))

+#define __tcu_unmask_full_match_irq(n)	(REG_TCU_TMCR = (1 << (n)))

+

+#define __tcu_ost_match_flag()		(REG_TCU_TFR & TFR_OSTFLAG)

+#define __tcu_set_ost_match_flag()	(REG_TCU_TFSR = TFSR_OSTFLAG)

+#define __tcu_clear_ost_match_flag()	(REG_TCU_TFCR = TFCR_OSTFLAG)

+#define __tcu_ost_match_irq_masked()	(REG_TCU_TMR & TMR_OSTMASK)

+#define __tcu_mask_ost_match_irq()	(REG_TCU_TMSR = TMSR_OSTMASK)

+#define __tcu_unmask_ost_match_irq()	(REG_TCU_TMCR = TMCR_OSTMASK)

+

+#define __tcu_wdt_clock_stopped()	(REG_TCU_TSR & TSR_WDT_STOP)

+#define __tcu_ost_clock_stopped()	(REG_TCU_TSR & TSR_OST_STOP)

+#define __tcu_timer_clock_stopped(n)	(REG_TCU_TSR & (1 << (n)))

+

+#define __tcu_start_wdt_clock()		(REG_TCU_TSCR = TSCR_WDT)

+#define __tcu_start_ost_clock()		(REG_TCU_TSCR = TSCR_OST)

+#define __tcu_start_timer_clock(n)	(REG_TCU_TSCR = (1 << (n)))

+

+#define __tcu_stop_wdt_clock()		(REG_TCU_TSSR = TSSR_WDT)

+#define __tcu_stop_ost_clock()		(REG_TCU_TSSR = TSSR_OST)

+#define __tcu_stop_timer_clock(n)	(REG_TCU_TSSR = (1 << (n)))

+

+#define __tcu_get_count(n)		(REG_TCU_TCNT((n)))

+#define __tcu_set_count(n,v)		(REG_TCU_TCNT((n)) = (v))

+#define __tcu_set_full_data(n,v)	(REG_TCU_TDFR((n)) = (v))

+#define __tcu_set_half_data(n,v)	(REG_TCU_TDHR((n)) = (v))

+

+/* TCU2, counter 1, 2*/

+#define __tcu_read_real_value(n)	(REG_TCU_TSTR & (1 << ((n) + 16)))

+#define __tcu_read_false_value(n)	(REG_TCU_TSTR & (1 << ((n) + 16)))

+#define __tcu_counter_busy(n)		(REG_TCU_TSTR & (1 << (n)))

+#define __tcu_counter_ready(n)		(REG_TCU_TSTR & (1 << (n)))

+

+#define __tcu_set_read_real_value(n)	(REG_TCU_TSTSR = (1 << ((n) + 16)))

+#define __tcu_set_read_false_value(n)	(REG_TCU_TSTCR = (1 << ((n) + 16)))

+#define __tcu_set_counter_busy(n)	(REG_TCU_TSTSR = (1 << (n)))

+#define __tcu_set_counter_ready(n)	(REG_TCU_TSTCR = (1 << (n)))

+

+#endif /* __MIPS_ASSEMBLER */

+

+

+#endif /* __JZ4760BTCU_H__ */

diff --git a/arch/mips/include/asm/mach-jz4760b/jz4760btssi.h b/arch/mips/include/asm/mach-jz4760b/jz4760btssi.h
new file mode 100644
index 00000000000..f748e57d525
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4760b/jz4760btssi.h
@@ -0,0 +1,105 @@
+/*

+ * jz4760btssi.h

+ * JZ4760B TSSI register definition

+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

+ *

+ * Author: whxu@ingenic.cn

+ */

+

+#ifndef __JZ4760BTSSI_H__

+#define __JZ4760BTSSI_H__

+

+

+/*

+ * TS slave interface(TSSI) address definition

+ */

+#define	TSSI_BASE	0xb0073000

+

+

+/*

+ * TS registers offset address definition

+ */

+#define TSSI_TSENA_OFFSET	(0x00)	/* rw,  8, 0x08 */

+#define TSSI_TSCFG_OFFSET	(0x04)	/* rw, 16, 0x04ff */

+#define TSSI_TSCTRL_OFFSET	(0x08)	/* rw,  8, 0x03 */

+#define TSSI_TSSTAT_OFFSET	(0x0c)	/* rw,  8, 0x00 */

+#define TSSI_TSFIFO_OFFSET	(0x10)	/* rw, 32, 0x???????? */

+#define TSSI_TSPEN_OFFSET	(0x14)	/* rw, 32, 0x00000000 */

+#define TSSI_TSNUM_OFFSET	(0x18)	/* rw,  8, 0x00 */

+#define TSSI_TSDTR_OFFSET	(0x1c)	/* rw,  8, 0x7f */

+#define TSSI_TSPID_OFFSET	(0x20)	/* rw, 32, 0x00000000 */

+

+

+/*

+ * TS registers address definition

+ */

+#define TSSI_TSENA	(TSSI_BASE + TSSI_TSENA_OFFSET)

+#define TSSI_TSCFG	(TSSI_BASE + TSSI_TSCFG_OFFSET)

+#define TSSI_TSCTRL	(TSSI_BASE + TSSI_TSCTRL_OFFSET)

+#define TSSI_TSSTAT	(TSSI_BASE + TSSI_TSSTAT_OFFSET)

+#define TSSI_TSFIFO	(TSSI_BASE + TSSI_TSFIFO_OFFSET)

+#define TSSI_TSPEN	(TSSI_BASE + TSSI_TSPEN_OFFSET)

+#define TSSI_TSNUM	(TSSI_BASE + TSSI_TSNUM_OFFSET)

+#define TSSI_TSDTR	(TSSI_BASE + TSSI_TSDTR_OFFSET)

+#define TSSI_TSPID(n)	(TSSI_BASE + TSSI_TSPID_OFFSET + (n)*4)	/* max n is 15 */

+

+

+/*

+ * TS registers common define

+ */

+

+/* TSSI enable register(TSENA) */

+#define TSENA_RESET		BIT7

+#define TSENA_FAIL		BIT4

+#define TSENA_PEN0		BIT3

+#define TSENA_PIDEN		BIT2

+#define TSENA_DMAEN		BIT1

+#define TSENA_ENA		BIT0

+

+/* TSSI configure register(TSCFG) */

+#define TSCFG_EDNWD		BIT9

+#define TSCFG_EDNBT		BIT8

+#define TSCFG_TSDI_HIGH		BIT7

+#define TSCFG_USE0		BIT6

+#define TSCFG_TSCLK		BIT5

+#define TSCFG_PARAL		BIT4

+#define TSCFG_CLKP		BIT3

+#define TSCFG_FRM_HIGH		BIT2

+#define TSCFG_STR_HIGH		BIT1

+#define TSCFG_FAIL_HIGH		BIT0

+

+#define TSCFG_TRIGV_LSB		14

+#define TSCFG_TRIGV_MASK	BIT_H2L(15, TSCFG_TRIGV_LSB)

+#define TSCFG_TRIGV(n)		(((n)/8) << TSCFG_TRIGV_LSB)	/* n = 4, 8, 16 */

+

+#define TSCFG_TRANSMD_LSB	10

+#define TSCFG_TRANSMD_MASK	BIT_H2L(11, TSCFG_TRANSMD_LSB)

+

+/* TSSI control register(TSCTRL) */

+#define TSCTRL_FDTRM		BIT2

+#define TSCTRL_FOVERUNM		BIT1

+#define TSCTRL_FTRIGM		BIT0

+

+/* TSSI state register(TSSTAT) */

+#define TSSTAT_FDTR		BIT2

+#define TSSTAT_FOVERUN		BIT1

+#define TSSTAT_FTRIG		BIT0

+

+

+#ifndef __MIPS_ASSEMBLER

+

+#define REG_TSSI_TSENA		REG8(TSSI_TSENA)

+#define REG_TSSI_TSCFG          REG16(TSSI_TSCFG)

+#define REG_TSSI_TSCTRL         REG8(TSSI_TSCTRL)

+#define REG_TSSI_TSSTAT         REG8(TSSI_TSSTAT)

+#define REG_TSSI_TSFIFO         REG32(TSSI_TSFIFO)

+#define REG_TSSI_TSPEN          REG32(TSSI_TSPEN)

+#define REG_TSSI_TSNUM          REG8(TSSI_TSNUM)

+#define REG_TSSI_TSDTR          REG8(TSSI_TSDTR)

+#define REG_TSSI_TSPID(n)       REG32(TSSI_TSPID(n))

+

+

+#endif /* __MIPS_ASSEMBLER */

+

+#endif /* __JZ4760BTSSI_H__ */

+

diff --git a/arch/mips/include/asm/mach-jz4760b/jz4760btve.h b/arch/mips/include/asm/mach-jz4760b/jz4760btve.h
new file mode 100644
index 00000000000..45784d929b9
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4760b/jz4760btve.h
@@ -0,0 +1,396 @@
+/*

+ * linux/include/asm-mips/mach-jz4760b/jz4760btve.h

+ *

+ * JZ4760B TVE register definition.

+ *

+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

+ */

+

+#ifndef __JZ4760BTVE_H__

+#define __JZ4760BTVE_H__

+

+

+#define	TVE_BASE	0xB3050100 

+

+

+

+/*************************************************************************

+ * TVE (TV Encoder Controller)

+ *************************************************************************/

+#define TVE_CTRL	(TVE_BASE + 0x40) /* TV Encoder Control register */

+#define TVE_FRCFG	(TVE_BASE + 0x44) /* Frame configure register */

+#define TVE_SLCFG1	(TVE_BASE + 0x50) /* TV signal level configure register 1 */

+#define TVE_SLCFG2	(TVE_BASE + 0x54) /* TV signal level configure register 2*/

+#define TVE_SLCFG3	(TVE_BASE + 0x58) /* TV signal level configure register 3*/

+#define TVE_LTCFG1	(TVE_BASE + 0x60) /* Line timing configure register 1 */

+#define TVE_LTCFG2	(TVE_BASE + 0x64) /* Line timing configure register 2 */

+#define TVE_CFREQ	(TVE_BASE + 0x70) /* Chrominance sub-carrier frequency configure register */

+#define TVE_CPHASE	(TVE_BASE + 0x74) /* Chrominance sub-carrier phase configure register */

+#define TVE_CBCRCFG	(TVE_BASE + 0x78) /* Chrominance filter configure register */

+#define TVE_WSSCR	(TVE_BASE + 0x80) /* Wide screen signal control register */

+#define TVE_WSSCFG1	(TVE_BASE + 0x84) /* Wide screen signal configure register 1 */

+#define TVE_WSSCFG2	(TVE_BASE + 0x88) /* Wide screen signal configure register 2 */

+#define TVE_WSSCFG3	(TVE_BASE + 0x8c) /* Wide screen signal configure register 3 */

+

+#define REG_TVE_CTRL     REG32(TVE_CTRL)

+#define REG_TVE_FRCFG    REG32(TVE_FRCFG)

+#define REG_TVE_SLCFG1   REG32(TVE_SLCFG1)

+#define REG_TVE_SLCFG2   REG32(TVE_SLCFG2)

+#define REG_TVE_SLCFG3   REG32(TVE_SLCFG3)

+#define REG_TVE_LTCFG1   REG32(TVE_LTCFG1)

+#define REG_TVE_LTCFG2   REG32(TVE_LTCFG2)

+#define REG_TVE_CFREQ    REG32(TVE_CFREQ)

+#define REG_TVE_CPHASE   REG32(TVE_CPHASE)

+#define REG_TVE_CBCRCFG	 REG32(TVE_CBCRCFG)

+#define REG_TVE_WSSCR    REG32(TVE_WSSCR)

+#define REG_TVE_WSSCFG1  REG32(TVE_WSSCFG1)

+#define REG_TVE_WSSCFG2	 REG32(TVE_WSSCFG2)

+#define REG_TVE_WSSCFG3  REG32(TVE_WSSCFG3)

+

+/* TV Encoder Control register */

+#define TVE_CTRL_EYCBCR         (1 << 25)    /* YCbCr_enable */

+#define TVE_CTRL_ECVBS          (1 << 24)    /* 1: cvbs_enable 0: s-video*/

+#define TVE_CTRL_DAPD3	        (1 << 23)    /* DAC 3 power down */

+#define TVE_CTRL_DAPD2	        (1 << 22)    /* DAC 2 power down */	

+#define TVE_CTRL_DAPD1	        (1 << 21)    /* DAC 1 power down */	

+#define TVE_CTRL_DAPD           (1 << 20)    /* power down all DACs */

+#define TVE_CTRL_YCDLY_BIT      16

+#define TVE_CTRL_YCDLY_MASK     (0x7 << TVE_CTRL_YCDLY_BIT)

+#define TVE_CTRL_CGAIN_BIT      14

+#define TVE_CTRL_CGAIN_MASK     (0x3 << TVE_CTRL_CGAIN_BIT)

+  #define TVE_CTRL_CGAIN_FULL		(0 << TVE_CTRL_CGAIN_BIT) /* gain = 1 */

+  #define TVE_CTRL_CGAIN_QUTR		(1 << TVE_CTRL_CGAIN_BIT) /* gain = 1/4 */

+  #define TVE_CTRL_CGAIN_HALF		(2 << TVE_CTRL_CGAIN_BIT) /* gain = 1/2 */

+  #define TVE_CTRL_CGAIN_THREE_QURT	(3 << TVE_CTRL_CGAIN_BIT) /* gain = 3/4 */

+#define TVE_CTRL_CBW_BIT        12

+#define TVE_CTRL_CBW_MASK       (0x3 << TVE_CTRL_CBW_BIT)

+  #define TVE_CTRL_CBW_NARROW	(0 << TVE_CTRL_CBW_BIT) /* Narrow band */

+  #define TVE_CTRL_CBW_WIDE	(1 << TVE_CTRL_CBW_BIT) /* Wide band */

+  #define TVE_CTRL_CBW_EXTRA	(2 << TVE_CTRL_CBW_BIT) /* Extra wide band */

+  #define TVE_CTRL_CBW_ULTRA	(3 << TVE_CTRL_CBW_BIT) /* Ultra wide band */

+#define TVE_CTRL_SYNCT          (1 << 9)

+#define TVE_CTRL_PAL            (1 << 8) /* 1: PAL, 0: NTSC */

+#define TVE_CTRL_FINV           (1 << 7) /* invert_top:1-invert top and bottom fields. */

+#define TVE_CTRL_ZBLACK         (1 << 6) /* bypass_yclamp:1-Black of luminance (Y) input is 0.*/

+#define TVE_CTRL_CR1ST          (1 << 5) /* uv_order:0-Cb before Cr,1-Cr before Cb */

+#define TVE_CTRL_CLBAR          (1 << 4) /* Color bar mode:0-Output input video to TV,1-Output color bar to TV */

+#define TVE_CTRL_SWRST          (1 << 0) /* Software reset:1-TVE is reset */

+

+/* Signal level configure register 1 */

+#define TVE_SLCFG1_BLACKL_BIT   0

+#define TVE_SLCFG1_BLACKL_MASK  (0x3ff << TVE_SLCFG1_BLACKL_BIT)

+#define TVE_SLCFG1_WHITEL_BIT   16

+#define TVE_SLCFG1_WHITEL_MASK  (0x3ff << TVE_SLCFG1_WHITEL_BIT)

+

+/* Signal level configure register 2 */

+#define TVE_SLCFG2_BLANKL_BIT    0

+#define TVE_SLCFG2_BLANKL_MASK   (0x3ff << TVE_SLCFG2_BLANKL_BIT)

+#define TVE_SLCFG2_VBLANKL_BIT   16

+#define TVE_SLCFG2_VBLANKL_MASK  (0x3ff << TVE_SLCFG2_VBLANKL_BIT)

+

+/* Signal level configure register 3 */

+#define TVE_SLCFG3_SYNCL_BIT   0

+#define TVE_SLCFG3_SYNCL_MASK  (0xff << TVE_SLCFG3_SYNCL_BIT)

+

+/* Line timing configure register 1 */

+#define TVE_LTCFG1_BACKP_BIT   0

+#define TVE_LTCFG1_BACKP_MASK  (0x7f << TVE_LTCFG1_BACKP_BIT)

+#define TVE_LTCFG1_HSYNCW_BIT   8

+#define TVE_LTCFG1_HSYNCW_MASK  (0x7f << TVE_LTCFG1_HSYNCW_BIT)

+#define TVE_LTCFG1_FRONTP_BIT   16

+#define TVE_LTCFG1_FRONTP_MASK  (0x1f << TVE_LTCFG1_FRONTP_BIT)

+

+/* Line timing configure register 2 */

+#define TVE_LTCFG2_BURSTW_BIT    0

+#define TVE_LTCFG2_BURSTW_MASK   (0x3f << TVE_LTCFG2_BURSTW_BIT)

+#define TVE_LTCFG2_PREBW_BIT     8

+#define TVE_LTCFG2_PREBW_MASK    (0x1f << TVE_LTCFG2_PREBW_BIT)

+#define TVE_LTCFG2_ACTLIN_BIT    16

+#define TVE_LTCFG2_ACTLIN_MASK	(0x7ff << TVE_LTCFG2_ACTLIN_BIT)

+

+/* Chrominance sub-carrier phase configure register */

+#define TVE_CPHASE_CCRSTP_BIT    0

+#define TVE_CPHASE_CCRSTP_MASK   (0x3 << TVE_CPHASE_CCRSTP_BIT)

+  #define TVE_CPHASE_CCRSTP_8	(0 << TVE_CPHASE_CCRSTP_BIT) /* Every 8 field */

+  #define TVE_CPHASE_CCRSTP_4	(1 << TVE_CPHASE_CCRSTP_BIT) /* Every 4 field */

+  #define TVE_CPHASE_CCRSTP_2	(2 << TVE_CPHASE_CCRSTP_BIT) /* Every 2 lines */

+  #define TVE_CPHASE_CCRSTP_0	(3 << TVE_CPHASE_CCRSTP_BIT) /* Never */

+#define TVE_CPHASE_ACTPH_BIT     16

+#define TVE_CPHASE_ACTPH_MASK    (0xff << TVE_CPHASE_ACTPH_BIT)

+#define TVE_CPHASE_INITPH_BIT    24

+#define TVE_CPHASE_INITPH_MASK   (0xff << TVE_CPHASE_INITPH_BIT)

+

+/* Chrominance filter configure register */

+#define TVE_CBCRCFG_CRGAIN_BIT       0

+#define TVE_CBCRCFG_CRGAIN_MASK      (0xff << TVE_CBCRCFG_CRGAIN_BIT)

+#define TVE_CBCRCFG_CBGAIN_BIT       8

+#define TVE_CBCRCFG_CBGAIN_MASK      (0xff << TVE_CBCRCFG_CBGAIN_BIT)

+#define TVE_CBCRCFG_CRBA_BIT         16

+#define TVE_CBCRCFG_CRBA_MASK        (0xff << TVE_CBCRCFG_CRBA_BIT)

+#define TVE_CBCRCFG_CBBA_BIT         24

+#define TVE_CBCRCFG_CBBA_MASK        (0xff << TVE_CBCRCFG_CBBA_BIT)

+

+/* Frame configure register */

+#define TVE_FRCFG_NLINE_BIT          0

+#define TVE_FRCFG_NLINE_MASK         (0x3ff << TVE_FRCFG_NLINE_BIT)

+#define TVE_FRCFG_L1ST_BIT           16

+#define TVE_FRCFG_L1ST_MASK          (0xff << TVE_FRCFG_L1ST_BIT)

+

+/* Wide screen signal control register */

+#define TVE_WSSCR_EWSS0_BIT	0

+#define TVE_WSSCR_EWSS1_BIT	1

+#define TVE_WSSCR_WSSTP_BIT	2

+#define TVE_WSSCR_WSSCKBP_BIT	3

+#define TVE_WSSCR_WSSEDGE_BIT	4

+#define TVE_WSSCR_WSSEDGE_MASK	(0x7 << TVE_WSSCR_WSSEDGE_BIT)

+#define TVE_WSSCR_ENCH_BIT	8

+#define TVE_WSSCR_NCHW_BIT	9

+#define TVE_WSSCR_NCHFREQ_BIT	12

+#define TVE_WSSCR_NCHFREQ_MASK	(0x7 << TVE_WSSCR_NCHFREQ_BIT)

+

+

+#ifndef __MIPS_ASSEMBLER

+

+/*************************************************************************

+ * TVE (TV Encoder Controller) ops

+ *************************************************************************/

+/* TV Encoder Control register ops */

+#define __tve_soft_reset()		(REG_TVE_CTRL |= TVE_CTRL_SWRST)

+

+#define __tve_output_colorbar()		(REG_TVE_CTRL |= TVE_CTRL_CLBAR)

+#define __tve_output_video()		(REG_TVE_CTRL &= ~TVE_CTRL_CLBAR)

+

+#define __tve_input_cr_first()		(REG_TVE_CTRL |= TVE_CTRL_CR1ST)

+#define __tve_input_cb_first()		(REG_TVE_CTRL &= ~TVE_CTRL_CR1ST)

+

+#define __tve_set_0_as_black()		(REG_TVE_CTRL |= TVE_CTRL_ZBLACK)

+#define __tve_set_16_as_black()		(REG_TVE_CTRL &= ~TVE_CTRL_ZBLACK)

+

+#define __tve_ena_invert_top_bottom()	(REG_TVE_CTRL |= TVE_CTRL_FINV)

+#define __tve_dis_invert_top_bottom()	(REG_TVE_CTRL &= ~TVE_CTRL_FINV)

+

+#define __tve_set_pal_mode()		(REG_TVE_CTRL |= TVE_CTRL_PAL)

+#define __tve_set_ntsc_mode()		(REG_TVE_CTRL &= ~TVE_CTRL_PAL)

+

+#define __tve_set_pal_dura()		(REG_TVE_CTRL |= TVE_CTRL_SYNCT)

+#define __tve_set_ntsc_dura()		(REG_TVE_CTRL &= ~TVE_CTRL_SYNCT)

+

+/* n = 0 ~ 3 */

+#define __tve_set_c_bandwidth(n) \

+do {\

+	REG_TVE_CTRL &= ~TVE_CTRL_CBW_MASK;\

+	REG_TVE_CTRL |= (n) << TVE_CTRL_CBW_BIT;	\

+}while(0)

+

+/* n = 0 ~ 3 */

+#define __tve_set_c_gain(n) \

+do {\

+	REG_TVE_CTRL &= ~TVE_CTRL_CGAIN_MASK;\

+	(REG_TVE_CTRL |= (n) << TVE_CTRL_CGAIN_BIT;	\

+}while(0)

+

+/* n = 0 ~ 7 */

+#define __tve_set_yc_delay(n)				\

+do {							\

+	REG_TVE_CTRL &= ~TVE_CTRL_YCDLY_MASK		\

+	REG_TVE_CTRL |= ((n) << TVE_CTRL_YCDLY_BIT);	\

+} while(0)

+

+#define __tve_disable_all_dacs()	(REG_TVE_CTRL |= TVE_CTRL_DAPD)

+#define __tve_disable_dac1()		(REG_TVE_CTRL |= TVE_CTRL_DAPD1)

+#define __tve_enable_dac1()		(REG_TVE_CTRL &= ~TVE_CTRL_DAPD1)

+#define __tve_disable_dac2()		(REG_TVE_CTRL |= TVE_CTRL_DAPD2)

+#define __tve_enable_dac2()		(REG_TVE_CTRL &= ~TVE_CTRL_DAPD2)

+#define __tve_disable_dac3()		(REG_TVE_CTRL |= TVE_CTRL_DAPD3)

+#define __tve_enable_dac3()		(REG_TVE_CTRL &= ~TVE_CTRL_DAPD3)

+

+#define __tve_enable_svideo_fmt()	(REG_TVE_CTRL |= TVE_CTRL_ECVBS)

+#define __tve_enable_cvbs_fmt()		(REG_TVE_CTRL &= ~TVE_CTRL_ECVBS)

+

+/* TV Encoder Frame Configure register ops */

+/* n = 0 ~ 255 */

+#define __tve_set_first_video_line(n)		\

+do {\

+		REG_TVE_FRCFG &= ~TVE_FRCFG_L1ST_MASK;\

+		REG_TVE_FRCFG |= (n) << TVE_FRCFG_L1ST_BIT;\

+} while(0)

+/* n = 0 ~ 1023 */

+#define __tve_set_line_num_per_frm(n)		\

+do {\

+		REG_TVE_FRCFG &= ~TVE_FRCFG_NLINE_MASK;\

+		REG_TVE_CFG |= (n) << TVE_FRCFG_NLINE_BIT;\

+} while(0)

+#define __tve_get_video_line_num()\

+	(((REG_TVE_FRCFG & TVE_FRCFG_NLINE_MASK) >> TVE_FRCFG_NLINE_BIT) - 1 - 2 * ((REG_TVE_FRCFG & TVE_FRCFG_L1ST_MASK) >> TVE_FRCFG_L1ST_BIT))

+

+/* TV Encoder Signal Level Configure register ops */

+/* n = 0 ~ 1023 */

+#define __tve_set_white_level(n)		\

+do {\

+		REG_TVE_SLCFG1 &= ~TVE_SLCFG1_WHITEL_MASK;\

+		REG_TVE_SLCFG1 |= (n) << TVE_SLCFG1_WHITEL_BIT;\

+} while(0)

+/* n = 0 ~ 1023 */

+#define __tve_set_black_level(n)		\

+do {\

+		REG_TVE_SLCFG1 &= ~TVE_SLCFG1_BLACKL_MASK;\

+		REG_TVE_SLCFG1 |= (n) << TVE_SLCFG1_BLACKL_BIT;\

+} while(0)

+/* n = 0 ~ 1023 */

+#define __tve_set_blank_level(n)		\

+do {\

+		REG_TVE_SLCFG2 &= ~TVE_SLCFG2_BLANKL_MASK;\

+		REG_TVE_SLCFG2 |= (n) << TVE_SLCFG2_BLANKL_BIT;\

+} while(0)

+/* n = 0 ~ 1023 */

+#define __tve_set_vbi_blank_level(n)		\

+do {\

+		REG_TVE_SLCFG2 &= ~TVE_SLCFG2_VBLANKL_MASK;\

+		REG_TVE_SLCFG2 |= (n) << TVE_SLCFG2_VBLANKL_BIT;\

+} while(0)

+/* n = 0 ~ 1023 */

+#define __tve_set_sync_level(n)		\

+do {\

+		REG_TVE_SLCFG3 &= ~TVE_SLCFG3_SYNCL_MASK;\

+		REG_TVE_SLCFG3 |= (n) << TVE_SLCFG3_SYNCL_BIT;\

+} while(0)

+

+/* TV Encoder Signal Level Configure register ops */

+/* n = 0 ~ 31 */

+#define __tve_set_front_porch(n)		\

+do {\

+		REG_TVE_LTCFG1 &= ~TVE_LTCFG1_FRONTP_MASK;\

+		REG_TVE_LTCFG1 |= (n) << TVE_LTCFG1_FRONTP_BIT;	\

+} while(0)

+/* n = 0 ~ 127 */

+#define __tve_set_hsync_width(n)		\

+do {\

+		REG_TVE_LTCFG1 &= ~TVE_LTCFG1_HSYNCW_MASK;\

+		REG_TVE_LTCFG1 |= (n) << TVE_LTCFG1_HSYNCW_BIT;	\

+} while(0)

+/* n = 0 ~ 127 */

+#define __tve_set_back_porch(n)		\

+do {\

+		REG_TVE_LTCFG1 &= ~TVE_LTCFG1_BACKP_MASK;\

+		REG_TVE_LTCFG1 |= (n) << TVE_LTCFG1_BACKP_BIT;	\

+} while(0)

+/* n = 0 ~ 2047 */

+#define __tve_set_active_linec(n)		\

+do {\

+		REG_TVE_LTCFG2 &= ~TVE_LTCFG2_ACTLIN_MASK;\

+		REG_TVE_LTCFG2 |= (n) << TVE_LTCFG2_ACTLIN_BIT;	\

+} while(0)

+/* n = 0 ~ 31 */

+#define __tve_set_breezy_way(n)		\

+do {\

+		REG_TVE_LTCFG2 &= ~TVE_LTCFG2_PREBW_MASK;\

+		REG_TVE_LTCFG2 |= (n) << TVE_LTCFG2_PREBW_BIT;	\

+} while(0)

+

+/* n = 0 ~ 127 */

+#define __tve_set_burst_width(n)		\

+do {\

+		REG_TVE_LTCFG2 &= ~TVE_LTCFG2_BURSTW_MASK;\

+		REG_TVE_LTCFG2 |= (n) << TVE_LTCFG2_BURSTW_BIT;	\

+} while(0)

+

+/* TV Encoder Chrominance filter and Modulation register ops */

+/* n = 0 ~ (2^32-1) */

+#define __tve_set_c_sub_carrier_freq(n)  REG_TVE_CFREQ = (n)

+/* n = 0 ~ 255 */

+#define __tve_set_c_sub_carrier_init_phase(n) \

+do {   \

+	REG_TVE_CPHASE &= ~TVE_CPHASE_INITPH_MASK;	\

+	REG_TVE_CPHASE |= (n) << TVE_CPHASE_INITPH_BIT;	\

+} while(0)

+/* n = 0 ~ 255 */

+#define __tve_set_c_sub_carrier_act_phase(n) \

+do {   \

+	REG_TVE_CPHASE &= ~TVE_CPHASE_ACTPH_MASK;	\

+	REG_TVE_CPHASE |= (n) << TVE_CPHASE_ACTPH_BIT;	\

+} while(0)

+/* n = 0 ~ 255 */

+#define __tve_set_c_phase_rst_period(n) \

+do {   \

+	REG_TVE_CPHASE &= ~TVE_CPHASE_CCRSTP_MASK;	\

+	REG_TVE_CPHASE |= (n) << TVE_CPHASE_CCRSTP_BIT;	\

+} while(0)

+/* n = 0 ~ 255 */

+#define __tve_set_cb_burst_amp(n) \

+do {   \

+	REG_TVE_CBCRCFG &= ~TVE_CBCRCFG_CBBA_MASK;	\

+	REG_TVE_CBCRCFG |= (n) << TVE_CBCRCFG_CBBA_BIT;	\

+} while(0)

+/* n = 0 ~ 255 */

+#define __tve_set_cr_burst_amp(n) \

+do {   \

+	REG_TVE_CBCRCFG &= ~TVE_CBCRCFG_CRBA_MASK;	\

+	REG_TVE_CBCRCFG |= (n) << TVE_CBCRCFG_CRBA_BIT;	\

+} while(0)

+/* n = 0 ~ 255 */

+#define __tve_set_cb_gain_amp(n) \

+do {   \

+	REG_TVE_CBCRCFG &= ~TVE_CBCRCFG_CBGAIN_MASK;	\

+	REG_TVE_CBCRCFG |= (n) << TVE_CBCRCFG_CBGAIN_BIT;	\

+} while(0)

+/* n = 0 ~ 255 */

+#define __tve_set_cr_gain_amp(n) \

+do {   \

+	REG_TVE_CBCRCFG &= ~TVE_CBCRCFG_CRGAIN_MASK;	\

+	REG_TVE_CBCRCFG |= (n) << TVE_CBCRCFG_CRGAIN_BIT;	\

+} while(0)

+

+/* TV Encoder Wide Screen Signal Control register ops */

+/* n = 0 ~ 7 */

+#define __tve_set_notch_freq(n) \

+do {   \

+	REG_TVE_WSSCR &= ~TVE_WSSCR_NCHFREQ_MASK;	\

+	REG_TVE_WSSCR |= (n) << TVE_WSSCR_NCHFREQ_BIT;	\

+} while(0)

+/* n = 0 ~ 7 */

+#define __tve_set_notch_width()	(REG_TVE_WSSCR |= TVE_WSSCR_NCHW_BIT)

+#define __tve_clear_notch_width()	(REG_TVE_WSSCR &= ~TVE_WSSCR_NCHW_BIT)

+#define __tve_enable_notch()		(REG_TVE_WSSCR |= TVE_WSSCR_ENCH_BIT)

+#define __tve_disable_notch()		(REG_TVE_WSSCR &= ~TVE_WSSCR_ENCH_BIT)

+/* n = 0 ~ 7 */

+#define __tve_set_wss_edge(n) \

+do {   \

+	REG_TVE_WSSCR &= ~TVE_WSSCR_WSSEDGE_MASK;	\

+	REG_TVE_WSSCR |= (n) << TVE_WSSCR_WSSEDGE_BIT;	\

+} while(0)

+#define __tve_set_wss_clkbyp()		(REG_TVE_WSSCR |= TVE_WSSCR_WSSCKBP_BIT)

+#define __tve_set_wss_type()		(REG_TVE_WSSCR |= TVE_WSSCR_WSSTP_BIT)

+#define __tve_enable_wssf1()		(REG_TVE_WSSCR |= TVE_WSSCR_EWSS1_BIT)

+#define __tve_enable_wssf0()		(REG_TVE_WSSCR |= TVE_WSSCR_EWSS0_BIT)

+

+/* TV Encoder Wide Screen Signal Configure register 1, 2 and 3 ops */

+/* n = 0 ~ 1023 */

+#define __tve_set_wss_level(n) \

+do {   \

+	REG_TVE_WSSCFG1 &= ~TVE_WSSCFG1_WSSL_MASK;	\

+	REG_TVE_WSSCFG1 |= (n) << TVE_WSSCFG1_WSSL_BIT;	\

+} while(0)

+/* n = 0 ~ 4095 */

+#define __tve_set_wss_freq(n) \

+do {   \

+	REG_TVE_WSSCFG1 &= ~TVE_WSSCFG1_WSSFREQ_MASK;	\

+	REG_TVE_WSSCFG1 |= (n) << TVE_WSSCFG1_WSSFREQ_BIT;	\

+} while(0)

+/* n = 0, 1; l = 0 ~ 255 */

+#define __tve_set_wss_line(n,v)			\

+do {   \

+	REG_TVE_WSSCFG##n &= ~TVE_WSSCFG_WSSLINE_MASK;	\

+	REG_TVE_WSSCFG##n |= (v) << TVE_WSSCFG_WSSLINE_BIT;	\

+} while(0)

+/* n = 0, 1; d = 0 ~ (2^20-1) */

+#define __tve_set_wss_data(n, v)			\

+do {   \

+	REG_TVE_WSSCFG##n &= ~TVE_WSSCFG_WSSLINE_MASK;	\

+	REG_TVE_WSSCFG##n |= (v) << TVE_WSSCFG_WSSLINE_BIT;	\

+} while(0)

+

+

+#endif /* __MIPS_ASSEMBLER */

+

+#endif /* __JZ4760BTVE_H__ */

+

diff --git a/arch/mips/include/asm/mach-jz4760b/jz4760buart.h b/arch/mips/include/asm/mach-jz4760b/jz4760buart.h
new file mode 100644
index 00000000000..7bd8887bbc3
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4760b/jz4760buart.h
@@ -0,0 +1,280 @@
+/*

+ * linux/include/asm-mips/mach-jz4760b/jz4760buart.h

+ *

+ * JZ4760B UART register definition.

+ *

+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

+ */

+

+#ifndef __JZ4760BUART_H__

+#define __JZ4760BUART_H__

+

+

+#define	UART0_BASE	0xB0030000

+#define	UART1_BASE	0xB0031000

+#define	UART2_BASE	0xB0032000

+#define	UART3_BASE	0xB0033000

+

+/*************************************************************************

+ * UART

+ *************************************************************************/

+

+#define IRDA_BASE	UART0_BASE

+#define UART_BASE	UART0_BASE

+#define UART_OFF	0x1000

+

+/* Register Offset */

+#define OFF_RDR		(0x00)	/* R  8b H'xx */

+#define OFF_TDR		(0x00)	/* W  8b H'xx */

+#define OFF_DLLR	(0x00)	/* RW 8b H'00 */

+#define OFF_DLHR	(0x04)	/* RW 8b H'00 */

+#define OFF_IER		(0x04)	/* RW 8b H'00 */

+#define OFF_ISR		(0x08)	/* R  8b H'01 */

+#define OFF_FCR		(0x08)	/* W  8b H'00 */

+#define OFF_LCR		(0x0C)	/* RW 8b H'00 */

+#define OFF_MCR		(0x10)	/* RW 8b H'00 */

+#define OFF_LSR		(0x14)	/* R  8b H'00 */

+#define OFF_MSR		(0x18)	/* R  8b H'00 */

+#define OFF_SPR		(0x1C)	/* RW 8b H'00 */

+#define OFF_SIRCR	(0x20)	/* RW 8b H'00, UART0 */

+#define OFF_UMR		(0x24)	/* RW 8b H'00, UART M Register */

+#define OFF_UACR	(0x28)	/* RW 8b H'00, UART Add Cycle Register */

+

+/* Register Address */

+#define UART0_RDR	(UART0_BASE + OFF_RDR)

+#define UART0_TDR	(UART0_BASE + OFF_TDR)

+#define UART0_DLLR	(UART0_BASE + OFF_DLLR)

+#define UART0_DLHR	(UART0_BASE + OFF_DLHR)

+#define UART0_IER	(UART0_BASE + OFF_IER)

+#define UART0_ISR	(UART0_BASE + OFF_ISR)

+#define UART0_FCR	(UART0_BASE + OFF_FCR)

+#define UART0_LCR	(UART0_BASE + OFF_LCR)

+#define UART0_MCR	(UART0_BASE + OFF_MCR)

+#define UART0_LSR	(UART0_BASE + OFF_LSR)

+#define UART0_MSR	(UART0_BASE + OFF_MSR)

+#define UART0_SPR	(UART0_BASE + OFF_SPR)

+#define UART0_SIRCR	(UART0_BASE + OFF_SIRCR)

+#define UART0_UMR	(UART0_BASE + OFF_UMR)

+#define UART0_UACR	(UART0_BASE + OFF_UACR)

+

+#define UART1_RDR	(UART1_BASE + OFF_RDR)

+#define UART1_TDR	(UART1_BASE + OFF_TDR)

+#define UART1_DLLR	(UART1_BASE + OFF_DLLR)

+#define UART1_DLHR	(UART1_BASE + OFF_DLHR)

+#define UART1_IER	(UART1_BASE + OFF_IER)

+#define UART1_ISR	(UART1_BASE + OFF_ISR)

+#define UART1_FCR	(UART1_BASE + OFF_FCR)

+#define UART1_LCR	(UART1_BASE + OFF_LCR)

+#define UART1_MCR	(UART1_BASE + OFF_MCR)

+#define UART1_LSR	(UART1_BASE + OFF_LSR)

+#define UART1_MSR	(UART1_BASE + OFF_MSR)

+#define UART1_SPR	(UART1_BASE + OFF_SPR)

+#define UART1_SIRCR	(UART1_BASE + OFF_SIRCR)

+

+#define UART2_RDR	(UART2_BASE + OFF_RDR)

+#define UART2_TDR	(UART2_BASE + OFF_TDR)

+#define UART2_DLLR	(UART2_BASE + OFF_DLLR)

+#define UART2_DLHR	(UART2_BASE + OFF_DLHR)

+#define UART2_IER	(UART2_BASE + OFF_IER)

+#define UART2_ISR	(UART2_BASE + OFF_ISR)

+#define UART2_FCR	(UART2_BASE + OFF_FCR)

+#define UART2_LCR	(UART2_BASE + OFF_LCR)

+#define UART2_MCR	(UART2_BASE + OFF_MCR)

+#define UART2_LSR	(UART2_BASE + OFF_LSR)

+#define UART2_MSR	(UART2_BASE + OFF_MSR)

+#define UART2_SPR	(UART2_BASE + OFF_SPR)

+#define UART2_SIRCR	(UART2_BASE + OFF_SIRCR)

+

+#define UART3_RDR	(UART3_BASE + OFF_RDR)

+#define UART3_TDR	(UART3_BASE + OFF_TDR)

+#define UART3_DLLR	(UART3_BASE + OFF_DLLR)

+#define UART3_DLHR	(UART3_BASE + OFF_DLHR)

+#define UART3_IER	(UART3_BASE + OFF_IER)

+#define UART3_ISR	(UART3_BASE + OFF_ISR)

+#define UART3_FCR	(UART3_BASE + OFF_FCR)

+#define UART3_LCR	(UART3_BASE + OFF_LCR)

+#define UART3_MCR	(UART3_BASE + OFF_MCR)

+#define UART3_LSR	(UART3_BASE + OFF_LSR)

+#define UART3_MSR	(UART3_BASE + OFF_MSR)

+#define UART3_SPR	(UART3_BASE + OFF_SPR)

+#define UART3_SIRCR	(UART3_BASE + OFF_SIRCR)

+

+

+/*

+ * Define macros for UARTIER

+ * UART Interrupt Enable Register

+ */

+#define UARTIER_RIE	(1 << 0)	/* 0: receive fifo full interrupt disable */

+#define UARTIER_TIE	(1 << 1)	/* 0: transmit fifo empty interrupt disable */

+#define UARTIER_RLIE	(1 << 2)	/* 0: receive line status interrupt disable */

+#define UARTIER_MIE	(1 << 3)	/* 0: modem status interrupt disable */

+#define UARTIER_RTIE	(1 << 4)	/* 0: receive timeout interrupt disable */

+

+/*

+ * Define macros for UARTISR

+ * UART Interrupt Status Register

+ */

+#define UARTISR_IP	(1 << 0)	/* 0: interrupt is pending  1: no interrupt */

+#define UARTISR_IID	(7 << 1)	/* Source of Interrupt */

+#define UARTISR_IID_MSI		(0 << 1)  /* Modem status interrupt */

+#define UARTISR_IID_THRI	(1 << 1)  /* Transmitter holding register empty */

+#define UARTISR_IID_RDI		(2 << 1)  /* Receiver data interrupt */

+#define UARTISR_IID_RLSI	(3 << 1)  /* Receiver line status interrupt */

+#define UARTISR_IID_RTO		(6 << 1)  /* Receive timeout */

+#define UARTISR_FFMS		(3 << 6)  /* FIFO mode select, set when UARTFCR.FE is set to 1 */

+#define UARTISR_FFMS_NO_FIFO	(0 << 6)

+#define UARTISR_FFMS_FIFO_MODE	(3 << 6)

+

+/*

+ * Define macros for UARTFCR

+ * UART FIFO Control Register

+ */

+#define UARTFCR_FE	(1 << 0)	/* 0: non-FIFO mode  1: FIFO mode */

+#define UARTFCR_RFLS	(1 << 1)	/* write 1 to flush receive FIFO */

+#define UARTFCR_TFLS	(1 << 2)	/* write 1 to flush transmit FIFO */

+#define UARTFCR_DMS	(1 << 3)	/* 0: disable DMA mode */

+#define UARTFCR_UUE	(1 << 4)	/* 0: disable UART */

+#define UARTFCR_RTRG	(3 << 6)	/* Receive FIFO Data Trigger */

+#define UARTFCR_RTRG_1	(0 << 6)

+#define UARTFCR_RTRG_4	(1 << 6)

+#define UARTFCR_RTRG_8	(2 << 6)

+#define UARTFCR_RTRG_15	(3 << 6)

+

+/*

+ * Define macros for UARTLCR

+ * UART Line Control Register

+ */

+#define UARTLCR_WLEN	(3 << 0)	/* word length */

+#define UARTLCR_WLEN_5	(0 << 0)

+#define UARTLCR_WLEN_6	(1 << 0)

+#define UARTLCR_WLEN_7	(2 << 0)

+#define UARTLCR_WLEN_8	(3 << 0)

+#define UARTLCR_STOP	(1 << 2)	/* 0: 1 stop bit when word length is 5,6,7,8

+					   1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */

+#define UARTLCR_STOP1	(0 << 2)

+#define UARTLCR_STOP2	(1 << 2)

+#define UARTLCR_PE	(1 << 3)	/* 0: parity disable */

+#define UARTLCR_PROE	(1 << 4)	/* 0: even parity  1: odd parity */

+#define UARTLCR_SPAR	(1 << 5)	/* 0: sticky parity disable */

+#define UARTLCR_SBRK	(1 << 6)	/* write 0 normal, write 1 send break */

+#define UARTLCR_DLAB	(1 << 7)	/* 0: access UARTRDR/TDR/IER  1: access UARTDLLR/DLHR */

+

+/*

+ * Define macros for UARTLSR

+ * UART Line Status Register

+ */

+#define UARTLSR_DR	(1 << 0)	/* 0: receive FIFO is empty  1: receive data is ready */

+#define UARTLSR_ORER	(1 << 1)	/* 0: no overrun error */

+#define UARTLSR_PER	(1 << 2)	/* 0: no parity error */

+#define UARTLSR_FER	(1 << 3)	/* 0; no framing error */

+#define UARTLSR_BRK	(1 << 4)	/* 0: no break detected  1: receive a break signal */

+#define UARTLSR_TDRQ	(1 << 5)	/* 1: transmit FIFO half "empty" */

+#define UARTLSR_TEMT	(1 << 6)	/* 1: transmit FIFO and shift registers empty */

+#define UARTLSR_RFER	(1 << 7)	/* 0: no receive error  1: receive error in FIFO mode */

+

+/*

+ * Define macros for UARTMCR

+ * UART Modem Control Register

+ */

+#define UARTMCR_RTS	(1 << 1)	/* 0: RTS_ output high, 1: RTS_ output low */

+#define UARTMCR_LOOP	(1 << 4)	/* 0: normal  1: loopback mode */

+#define UARTMCR_FCM	(1 << 6)	/* 0: software  1: hardware */

+#define UARTMCR_MCE	(1 << 7)	/* 0: modem function is disable */

+

+/*

+ * Define macros for UARTMSR

+ * UART Modem Status Register

+ */

+#define UARTMSR_CCTS	(1 << 0)        /* 1: a change on CTS_ pin */

+#define UARTMSR_CTS	(1 << 4)	/* 0: CTS_ pin is high */

+

+/*

+ * Define macros for SIRCR

+ * Slow IrDA Control Register

+ */

+#define SIRCR_TSIRE	(1 << 0)  /* 0: transmitter is in UART mode  1: SIR mode */

+#define SIRCR_RSIRE	(1 << 1)  /* 0: receiver is in UART mode  1: SIR mode */

+#define SIRCR_TPWS	(1 << 2)  /* 0: transmit 0 pulse width is 3/16 of bit length

+					   1: 0 pulse width is 1.6us for 115.2Kbps */

+#define SIRCR_TDPL	(1 << 3)  /* 0: encoder generates a positive pulse for 0 */

+#define SIRCR_RDPL	(1 << 4)  /* 0: decoder interprets positive pulse as 0 */

+

+

+#ifndef __MIPS_ASSEMBLER

+

+/***************************************************************************

+ * UART

+ ***************************************************************************/

+#define __jtag_as_uart3()			\

+do {	                    			\

+	REG_GPIO_PXSELC(0) = 0x40000000;	\

+	REG_GPIO_PXSELS(0) = 0x80000000;	\

+} while(0)

+

+#define __uart_enable(n) \

+  ( REG8(UART_BASE + UART_OFF*(n) + OFF_FCR) |= UARTFCR_UUE | UARTFCR_FE )

+#define __uart_disable(n) \

+  ( REG8(UART_BASE + UART_OFF*(n) + OFF_FCR) = ~UARTFCR_UUE )

+

+#define __uart_enable_transmit_irq(n) \

+  ( REG8(UART_BASE + UART_OFF*(n) + OFF_IER) |= UARTIER_TIE )

+#define __uart_disable_transmit_irq(n) \

+  ( REG8(UART_BASE + UART_OFF*(n) + OFF_IER) &= ~UARTIER_TIE )

+

+#define __uart_enable_receive_irq(n) \

+  ( REG8(UART_BASE + UART_OFF*(n) + OFF_IER) |= UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE )

+#define __uart_disable_receive_irq(n) \

+  ( REG8(UART_BASE + UART_OFF*(n) + OFF_IER) &= ~(UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE) )

+

+#define __uart_enable_loopback(n) \

+  ( REG8(UART_BASE + UART_OFF*(n) + OFF_MCR) |= UARTMCR_LOOP )

+#define __uart_disable_loopback(n) \

+  ( REG8(UART_BASE + UART_OFF*(n) + OFF_MCR) &= ~UARTMCR_LOOP )

+

+#define __uart_set_8n1(n) \

+  ( REG8(UART_BASE + UART_OFF*(n) + OFF_LCR) = UARTLCR_WLEN_8 )

+

+#define __uart_set_baud(n, devclk, baud)						\

+  do {											\

+	REG8(UART_BASE + UART_OFF*(n) + OFF_LCR) |= UARTLCR_DLAB;			\

+	REG8(UART_BASE + UART_OFF*(n) + OFF_DLLR) = (devclk / 16 / baud) & 0xff;	\

+	REG8(UART_BASE + UART_OFF*(n) + OFF_DLHR) = ((devclk / 16 / baud) >> 8) & 0xff;	\

+	REG8(UART_BASE + UART_OFF*(n) + OFF_LCR) &= ~UARTLCR_DLAB;			\

+  } while (0)

+

+#define __uart_parity_error(n) \

+  ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_PER) != 0 )

+

+#define __uart_clear_errors(n) \

+  ( REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) &= ~(UARTLSR_ORER | UARTLSR_BRK | UARTLSR_FER | UARTLSR_PER | UARTLSR_RFER) )

+

+#define __uart_transmit_fifo_empty(n) \

+  ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_TDRQ) != 0 )

+

+#define __uart_transmit_end(n) \

+  ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_TEMT) != 0 )

+

+#define __uart_transmit_char(n, ch) \

+  REG8(UART_BASE + UART_OFF*(n) + OFF_TDR) = (ch)

+

+#define __uart_receive_fifo_full(n) \

+  ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_DR) != 0 )

+

+#define __uart_receive_ready(n) \

+  ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_DR) != 0 )

+

+#define __uart_receive_char(n) \

+  REG8(UART_BASE + UART_OFF*(n) + OFF_RDR)

+

+#define __uart_disable_irda() \

+  ( REG8(IRDA_BASE + OFF_SIRCR) &= ~(SIRCR_TSIRE | SIRCR_RSIRE) )

+#define __uart_enable_irda() \

+  /* Tx high pulse as 0, Rx low pulse as 0 */ \

+  ( REG8(IRDA_BASE + OFF_SIRCR) = SIRCR_TSIRE | SIRCR_RSIRE | SIRCR_RXPL | SIRCR_TPWS )

+

+

+

+#endif /* __MIPS_ASSEMBLER */

+

+#endif /* __JZ4760BUART_H__ */

+

diff --git a/arch/mips/include/asm/mach-jz4760b/jz4760bwdt.h b/arch/mips/include/asm/mach-jz4760b/jz4760bwdt.h
new file mode 100644
index 00000000000..30f4e91df65
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4760b/jz4760bwdt.h
@@ -0,0 +1,70 @@
+/*

+ * jz4760bwdt.h

+ * JZ4760B WDT register definition

+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

+ *

+ * Author: whxu@ingenic.cn

+ */

+

+#ifndef __JZ4760BWDT_H__

+#define __JZ4760BWDT_H__

+

+

+/*

+ * Watchdog timer module(WDT) address definition

+ */

+#define	WDT_BASE	0xb0002000

+

+

+/*

+ * WDT registers offset address definition

+ */

+#define WDT_WDR_OFFSET		(0x00)	/* rw, 16, 0x???? */

+#define WDT_WCER_OFFSET		(0x04)	/* rw,  8, 0x00 */

+#define WDT_WCNT_OFFSET		(0x08)	/* rw, 16, 0x???? */

+#define WDT_WCSR_OFFSET		(0x0c)	/* rw, 16, 0x0000 */

+

+

+/*

+ * WDT registers address definition

+ */

+#define WDT_WDR		(WDT_BASE + WDT_WDR_OFFSET)

+#define WDT_WCER	(WDT_BASE + WDT_WCER_OFFSET)

+#define WDT_WCNT	(WDT_BASE + WDT_WCNT_OFFSET)

+#define WDT_WCSR	(WDT_BASE + WDT_WCSR_OFFSET)

+

+

+/*

+ * WDT registers common define

+ */

+

+/* Watchdog counter enable register(WCER) */

+#define WCER_TCEN	BIT0

+

+/* Watchdog control register(WCSR) */

+#define WCSR_PRESCALE_LSB	3

+#define WCSR_PRESCALE_MASK	BITS_H2L(5, WCSR_PRESCALE_LSB)

+#define WCSR_PRESCALE1		(0x0 << WCSR_PRESCALE_LSB)

+#define WCSR_PRESCALE4		(0x1 << WCSR_PRESCALE_LSB)

+#define WCSR_PRESCALE16		(0x2 << WCSR_PRESCALE_LSB)

+#define WCSR_PRESCALE64		(0x3 << WCSR_PRESCALE_LSB)

+#define WCSR_PRESCALE256	(0x4 << WCSR_PRESCALE_LSB)

+#define WCSR_PRESCALE1024	(0x5 << WCSR_PRESCALE_LSB)

+

+#define WCSR_CLKIN_LSB		0

+#define WCSR_CLKIN_MASK		BITS_H2L(2, WCSR_CLKIN_LSB)

+#define WCSR_CLKIN_PCK		(0x1 << WCSR_CLKIN_LSB)

+#define WCSR_CLKIN_RTC		(0x2 << WCSR_CLKIN_LSB)

+#define WCSR_CLKIN_EXT		(0x4 << WCSR_CLKIN_LSB)

+

+

+#ifndef __MIPS_ASSEMBLER

+

+#define REG_WDT_WDR	REG16(WDT_WDR)

+#define REG_WDT_WCER	REG8(WDT_WCER)

+#define REG_WDT_WCNT	REG16(WDT_WCNT)

+#define REG_WDT_WCSR	REG16(WDT_WCSR)

+

+#endif /* __MIPS_ASSEMBLER */

+

+#endif /* __JZ4760BWDT_H__ */

diff --git a/arch/mips/include/asm/mach-jz4760b/jz4760bxxx.h b/arch/mips/include/asm/mach-jz4760b/jz4760bxxx.h
new file mode 100644
index 00000000000..2766ebef10d
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4760b/jz4760bxxx.h
@@ -0,0 +1,18 @@
+/*

+ * linux/include/asm-mips/mach-jz4760b/jz4760bxxx.h

+ *

+ * JZ4760B XXX register definition.

+ *

+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

+ */

+

+#ifndef __JZ4760BXXX_H__

+#define __JZ4760BXXX_H__

+

+

+#ifndef __MIPS_ASSEMBLER

+

+#endif /* __MIPS_ASSEMBLER */

+

+#endif /* __JZ4760BXXX_H__ */

+

diff --git a/arch/mips/include/asm/mach-jz4760b/misc.h b/arch/mips/include/asm/mach-jz4760b/misc.h
new file mode 100644
index 00000000000..b71c61bed33
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4760b/misc.h
@@ -0,0 +1,44 @@
+/*
+ *  linux/include/asm-mips/mach-jz4760b/misc.h
+ *
+ *  Ingenic's JZ4760B common include.
+ *
+ *  Copyright (C) 2008 Ingenic Semiconductor Inc.
+ *
+ *  Author: <cwjia@ingenic.cn>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_JZ4760B_MISC_H__
+#define __ASM_JZ4760B_MISC_H__
+
+/*==========================================================
+ * I2C
+ *===========================================================*/
+
+#define I2C_EEPROM_DEV	0xA	/* b'1010 */
+#define I2C_RTC_DEV	0xD	/* b'1101 */
+#define DIMM0_SPD_ADDR	0
+#define DIMM1_SPD_ADDR	1
+#define DIMM2_SPD_ADDR	2
+#define DIMM3_SPD_ADDR	3
+#define JZ_HCI_ADDR	7
+
+#define DIMM_SPD_LEN	128
+#define JZ_HCI_LEN	512    /* 4K bits E2PROM */
+#define I2C_RTC_LEN	16
+#define HCI_MAC_OFFSET	64
+
+extern void i2c_open(void);
+extern void i2c_close(void);
+extern void i2c_setclk(unsigned int i2cclk);
+
+extern int i2c_read(unsigned char device, unsigned char *buf,
+		    unsigned char address, int count);
+extern int i2c_write(unsigned char device, unsigned char *buf,
+		     unsigned char address, int count);
+
+#endif /* __ASM_JZ4760B_MISC_H__ */
diff --git a/arch/mips/include/asm/mach-jz4760b/platform.h b/arch/mips/include/asm/mach-jz4760b/platform.h
new file mode 100644
index 00000000000..b0d985b2b1d
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4760b/platform.h
@@ -0,0 +1,50 @@
+#ifndef __JZ4760B_PLATFORM_H__
+#define __JZ4760B_PLATFORM_H__
+
+/* msc */
+#define CARD_INSERTED 1
+#define CARD_REMOVED 0
+
+#ifdef CONFIG_JZ_RECOVERY_SUPPORT
+struct mmc_partition_info {
+	char name[32];
+	unsigned int saddr;
+	unsigned int len;
+	int type;
+};
+#endif
+
+struct jz_mmc_platform_data {
+	unsigned int ocr_mask;			/* available voltages */
+	unsigned long detect_delay;		/* delay in jiffies before detecting cards after interrupt */
+	unsigned char status_irq;
+	unsigned char support_sdio;
+	unsigned char bus_width;
+	unsigned int max_bus_width;
+	unsigned int detect_pin;
+
+	unsigned char msc_irq;
+	unsigned char dma_rxid;
+	unsigned char dma_txid;
+
+	void *driver_data;
+
+	void (*init) (struct device *);
+	void (*power_on) (struct device *);
+	void (*power_off) (struct device *);
+	void (*cpm_start) (struct device *);
+	unsigned int (*status) (struct device *);
+	unsigned int (*write_protect) (struct device *);
+	void (*plug_change) (int);
+#ifdef CONFIG_JZ_RECOVERY_SUPPORT
+	struct mmc_partition_info *partitions;
+	int num_partitions;
+	
+	unsigned int permission;
+	
+#define MMC_BOOT_AREA_PROTECTED	(0x1234)	/* Can not modified the area protected */
+#define MMC_BOOT_AREA_OPENED	(0x4321)	/* Can modified the area protected */
+#endif
+};
+
+#endif /* __JZ4760B_PLATFORM_H__ */
diff --git a/arch/mips/include/asm/mach-jz4760b/regs.h b/arch/mips/include/asm/mach-jz4760b/regs.h
new file mode 100644
index 00000000000..d4220eedf31
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4760b/regs.h
@@ -0,0 +1,42 @@
+/*
+ * linux/include/asm-mips/mach-jz4760b/regs.h
+ *
+ * JZ4760B register definition.
+ *
+ * Copyright (C) 2008 Ingenic Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __JZ4760B_REGS_H__
+#define __JZ4760B_REGS_H__
+
+
+/*
+ * Define the module base addresses
+ */
+/* AHB0 BUS Devices Base */
+#define HARB0_BASE	0xB3000000
+/* AHB1 BUS Devices Base */
+#define HARB1_BASE	0xB3200000
+#define	DMAGP0_BASE	0xB3210000
+#define	DMAGP1_BASE	0xB3220000
+#define	DMAGP2_BASE	0xB3230000
+#define	DEBLK_BASE	0xB3270000
+#define	IDCT_BASE	0xB3280000
+#define	CABAC_BASE	0xB3290000
+#define	TCSM0_BASE	0xB32B0000
+#define	TCSM1_BASE	0xB32C0000
+#define	SRAM_BASE	0xB32D0000
+/* AHB2 BUS Devices Base */
+#define HARB2_BASE	0xB3400000
+#define UHC_BASE	0xB3430000
+#define GPS_BASE	0xB3480000
+#define ETHC_BASE	0xB34B0000
+/* APB BUS Devices Base */
+#define	PS2_BASE	0xB0060000
+
+
+#endif /* __JZ4760B_REGS_H__ */
diff --git a/arch/mips/include/asm/mach-jz4760b/serial.h b/arch/mips/include/asm/mach-jz4760b/serial.h
new file mode 100644
index 00000000000..1393003a1cd
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4760b/serial.h
@@ -0,0 +1,30 @@
+/*
+ *  linux/include/asm-mips/mach-jz4760b/serial.h
+ *
+ *  Ingenic's JZ4760B common include.
+ *
+ *  Copyright (C) 2008 Ingenic Semiconductor Inc.
+ *
+ *  Author: <cwjia@ingenic.cn>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_BOARD_SERIAL_H__
+#define __ASM_BOARD_SERIAL_H__
+
+#ifndef CONFIG_SERIAL_MANY_PORTS
+#undef RS_TABLE_SIZE
+#define RS_TABLE_SIZE  1
+#endif
+
+#define JZ_BASE_BAUD	(12000000/16)
+
+#define JZ_SERIAL_PORT_DEFNS \
+	{ .baud_base = JZ_BASE_BAUD, .irq = IRQ_UART0, \
+	  .flags = STD_COM_FLAGS, .iomem_base = (u8 *)UART0_BASE, \
+	  .iomem_reg_shift = 2, .io_type = SERIAL_IO_MEM },
+
+#endif /* __ASM_BORAD_SERIAL_H__ */
diff --git a/arch/mips/include/asm/mach-jz4760b/spi.h b/arch/mips/include/asm/mach-jz4760b/spi.h
new file mode 100644
index 00000000000..b86738b197b
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4760b/spi.h
@@ -0,0 +1,87 @@
+/*

+ * linux/arch/mips/include/asm/mach-jz4760b/spi.h

+ *

+ * SSI controller for SPI protocol,use FIFO and DMA;

+ *

+ * Copyright (c) 2010 Ingenic Semiconductor Inc.

+ * Author: Shumb <sbhuang@ingenic.cn>

+ *

+ *  This program is free software; you can redistribute	 it and/or modify it

+ *  under  the terms of	 the GNU General  Public License as published by the

+ *  Free Software Foundation;  either version 2 of the	License, or (at your

+ *  option) any later version.

+ */

+

+#ifndef __I_SPI_H__

+#define __I_SPI_H__

+

+#define R_MODE		0x1

+#define W_MODE		0x2

+#define RW_MODE	(R_MODE | W_MODE)

+

+#define R_DMA		0x4

+#define W_DMA		0x8

+#define RW_DMA		(R_DMA |W_DMA)

+

+#define SPI_DMA_ERROR  		3

+#define SPI_CPU_ERROR		4

+

+#define JZ_SSI_MAX_FIFO_ENTRIES 	128

+#define JZ_SSI_DMA_BURST_LENGTH 	16

+

+#define FIFO_8_BIT		1

+#define FIFO_16_BIT		2

+#define FIFO_32_BIT		4

+

+

+/* the max number of spi devices */

+#define MAX_SPI_DEVICES				10

+

+#define PIN_SSI_CE0 	0

+#define PIN_SSI_CE1 	1

+

+struct jz47xx_spi_info {

+	u8	chnl;								/* the chanel of SSI controller */

+	u16	bus_num;							/* spi_master.bus_num */

+	unsigned is_pllclk:1;					/* source clock: 1---pllclk;0---exclk */

+	unsigned long		 board_size;		/* spi_master.num_chipselect */

+	struct spi_board_info	*board_info; 	/* link to spi devices info */

+	void (*set_cs)(struct jz47xx_spi_info *spi, u8 cs,unsigned int pol); /* be defined by spi devices driver user */

+	void (*pins_config)(void);				/* configure spi function pins (CLK,DR,RT) by user if need. */

+	u32		 pin_cs[MAX_SPI_DEVICES];		/* the member is pin_value according to spi_device.chip_select,

+												if uses spi controller driver "set_cs",it must be filled.*/

+};

+

+/* Chipselect "set_cs" function could be defined by user. Example as the follow ... */

+/*

+static void spi_gpio_cs(struct jz47xx_spi_info *spi, int cs, int pol);

+{

+	int pinval;

+

+	switch(cs){

+	case 0:

+		pinval = 32*1+31;

+		break;

+	case 1:

+		pinval = 32*1+30;

+		break;

+	case 2:

+		pinval = 32*1+29;

+		break;

+	default:

+		pinval = 32*1+28;

+		break;	

+	}

+	__gpio_as_output(pinval);				

+	switch (pol) {

+	case BITBANG_CS_ACTIVE:

+		__gpio_set_pin(pinval);

+		break;

+	case BITBANG_CS_INACTIVE:

+		__gpio_clear_pin(pinval);

+		break;

+	}

+

+}*/

+

+#endif

diff --git a/arch/mips/include/asm/mach-jz4760b/war.h b/arch/mips/include/asm/mach-jz4760b/war.h
new file mode 100644
index 00000000000..ae9574f5e8d
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4760b/war.h
@@ -0,0 +1,26 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_MIPS_MACH_JZ4760B_WAR_H
+#define __ASM_MIPS_MACH_JZ4760B_WAR_H
+
+#define R4600_V1_INDEX_ICACHEOP_WAR	0
+#define R4600_V1_HIT_CACHEOP_WAR	0
+#define R4600_V2_HIT_CACHEOP_WAR	0
+#define R5432_CP0_INTERRUPT_WAR		0
+#define BCM1250_M3_WAR			0
+#define SIBYTE_1956_WAR			0
+#define MIPS4K_ICACHE_REFILL_WAR	0
+#define MIPS_CACHE_SYNC_WAR		0
+#define TX49XX_ICACHE_INDEX_INV_WAR	0
+#define RM9000_CDEX_SMP_WAR		0
+#define ICACHE_REFILLS_WORKAROUND_WAR	0
+#define R10000_LLSC_WAR			0
+#define MIPS34K_MISSED_ITLB_WAR		0
+
+#endif /* __ASM_MIPS_MACH_JZ4760B_WAR_H */
+
diff --git a/arch/mips/include/asm/mach-jz4770/board-f4770.h b/arch/mips/include/asm/mach-jz4770/board-f4770.h
new file mode 100644
index 00000000000..18be091cdfd
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4770/board-f4770.h
@@ -0,0 +1,135 @@
+/*
+ *  linux arch/mips/include/asm/mach-jz4770/board-f4770.h
+ *
+ *  JZ4770-based F4770 board ver 1.x definition.
+ *
+ *  Copyright (C) 2008 Ingenic Semiconductor Inc.
+ *
+ *  Author: <cwjia@ingenic.cn>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_JZ4770_F4770_H__
+#define __ASM_JZ4770_F4770_H__
+
+#define CONFIG_FPGA
+
+/*======================================================================
+ * Frequencies of on-board oscillators
+ */
+#define JZ_EXTAL		24000000  /* Main extal freq: 12 MHz */
+#define JZ_EXTAL2		32768     /* RTC extal freq: 32.768 KHz */
+#define CFG_DIV		        2	/* cpu/extclk; only for FPGA */
+
+/*======================================================================
+ * GPIO
+ */
+#define GPIO_SD0_VCC_EN_N	113 /* GPD17 */
+#define GPIO_SD0_CD_N		110 /* GPD14 */
+#define GPIO_SD0_WP		112 /* GPD16 */
+
+#define GPIO_USB_DETE		102 /* GPD6 */
+#define GPIO_DC_DETE_N		103 /* GPD7 */
+#define GPIO_CHARG_STAT_N	111 /* GPD15 */
+#define GPIO_DISP_OFF_N		121 /* GPD25, LCD_REV */
+//#define GPIO_LED_EN       	124 /* GPD28 */
+
+#define GPIO_UDC_HOTPLUG	GPIO_USB_DETE
+
+/*======================================================================
+ * LCD backlight
+ */
+
+#define GPIO_LCD_PWM   		(32*4+4) /* GPE4 PWM4 */
+#define LCD_PWM_CHN 4    /* pwm channel */
+#define LCD_PWM_FULL 101
+#define LCD_DEFAULT_BACKLIGHT		80
+#define LCD_MAX_BACKLIGHT		100
+#define LCD_MIN_BACKLIGHT		1
+
+/* 100 level: 0,1,...,100 */
+
+#define __lcd_set_backlight_level(n)	\
+do {					\
+	__gpio_as_output1(GPIO_LCD_PWM);	\
+} while (0)
+
+#define __lcd_close_backlight()		\
+do {					\
+	__gpio_as_output0(GPIO_LCD_PWM);	\
+} while (0)
+
+/*======================================================================
+ * MMC/SD
+ */
+
+#define MSC0_WP_PIN		GPIO_SD0_WP
+#define MSC0_HOTPLUG_PIN		GPIO_SD0_CD_N
+#define MSC0_HOTPLUG_IRQ		(IRQ_GPIO_0 + GPIO_SD0_CD_N)
+
+#if 0
+#define __msc0_init_io()				\
+do {						\
+	__gpio_as_output1(GPIO_SD0_VCC_EN_N);	\
+	__gpio_as_input(GPIO_SD0_CD_N);		\
+} while (0)
+#endif
+#define __msc0_init_io()				\
+do {						\
+	__gpio_as_input(GPIO_SD0_CD_N);		\
+} while (0)
+
+#define __msc0_enable_power()			\
+do {						\
+	__gpio_as_output0(GPIO_SD0_VCC_EN_N);	\
+} while (0)
+
+#define __msc0_disable_power()			\
+do {						\
+	__gpio_as_output1(GPIO_SD0_VCC_EN_N);	\
+} while (0)
+
+#define __msc0_card_detected(s)			\
+({						\
+	int detected = 1;			\
+	if (__gpio_get_pin(GPIO_SD0_CD_N))	\
+		detected = 0;			\
+	detected;				\
+})
+
+#if 0
+#define __msc_init_io()				\
+do {						\
+	__gpio_as_output(GPIO_SD_VCC_EN_N);	\
+	__gpio_as_input(GPIO_SD_CD_N);		\
+} while (0)
+
+#define __msc_enable_power()			\
+do {						\
+	__gpio_clear_pin(GPIO_SD_VCC_EN_N);	\
+} while (0)
+
+#define __msc_disable_power()			\
+do {						\
+	__gpio_set_pin(GPIO_SD_VCC_EN_N);	\
+} while (0)
+
+#define __msc_card_detected(s)			\
+({						\
+	int detected = 1;			\
+	if (__gpio_get_pin(GPIO_SD_CD_N))	\
+		detected = 0;			\
+	detected;				\
+})
+#endif
+#define ACTIVE_LOW_MSC0_CD	1
+#define ACTIVE_LOW_MSC1_CD	1
+
+#define JZ_BOOTUP_UART_TXD	(32 * 2 + 30)
+#define JZ_BOOTUP_UART_RXD	(32 * 2 + 28)
+#define JZ_EARLY_UART_BASE	UART2_BASE
+
+#endif /* __ASM_JZ4770_F4770_H__ */
diff --git a/arch/mips/include/asm/mach-jz4760/clock.h b/arch/mips/include/asm/mach-jz4770/clock.h
index 56cd10021fe..722e62ffe84 100644
--- a/arch/mips/include/asm/mach-jz4760/clock.h
+++ b/arch/mips/include/asm/mach-jz4770/clock.h
@@ -1,7 +1,7 @@
 /*
- *  linux/include/asm-mips/mach-jz4760/clock.h
+ *  linux/include/asm-mips/mach-jz4810/clock.h
  *
- *  JZ4760 clocks definition.
+ *  JZ4810 clocks definition.
  *
  *  Copyright (C) 2008 Ingenic Semiconductor Inc.
  *
@@ -12,18 +12,18 @@
  * published by the Free Software Foundation.
  */
 
-#ifndef __ASM_JZ4760_CLOCK_H__
-#define __ASM_JZ4760_CLOCK_H__
+#ifndef __ASM_JZ4770_CLOCK_H__
+#define __ASM_JZ4770_CLOCK_H__
 
 #ifndef JZ_EXTAL
-#define JZ_EXTAL		12000000   /* 3.6864 MHz */
+#define JZ_EXTAL		24000000   /* 3.6864 MHz */
 #endif
 #ifndef JZ_EXTAL2
 #define JZ_EXTAL2		32768     /* 32.768 KHz */
 #endif
 
 /*
- * JZ4760 clocks structure
+ * JZ4770 clocks structure
  */
 typedef struct {
 	unsigned int cclk;	/* CPU clock				*/
@@ -247,7 +247,6 @@ static inline void __cpm_select_msc_clk(int n, int sd)
 	}
 
 	REG_CPM_MSCCDR = div - 1;
-	//	REG_CPM_MSCCDR |= CPM_MSCCDR_MCS;
 	REG_CPM_CPCCR |= CPM_CPCCR_CE;
 }
 
@@ -265,4 +264,4 @@ static inline void __cpm_select_msc_clk_high(int n, int sd)
 	REG_CPM_CPCCR |= CPM_CPCCR_CE;
 }
 
-#endif /* __ASM_JZ4760_CLOCK_H__ */
+#endif /* __ASM_JZ4770_CLOCK_H__ */
diff --git a/arch/mips/include/asm/mach-jz4770/dma.h b/arch/mips/include/asm/mach-jz4770/dma.h
new file mode 100644
index 00000000000..57172b5d165
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4770/dma.h
@@ -0,0 +1,327 @@
+/*
+ *  linux/include/asm-mips/mach-jz4770/dma.h
+ *
+ *  JZ4770 DMA definition.
+ *
+ *  Copyright (C) 2008 Ingenic Semiconductor Inc.
+ *
+ *  Author: <cwjia@ingenic.cn>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_JZ4770_DMA_H__
+#define __ASM_JZ4770_DMA_H__
+
+#include <linux/interrupt.h>
+#include <asm/io.h>			/* need byte IO */
+#include <linux/spinlock.h>		/* And spinlocks */
+#include <linux/delay.h>
+#include <asm/system.h>
+
+/*
+ * Descriptor structure for JZ4770 DMA engine
+ * Note: this structure must always be aligned to a 16-bytes boundary.
+ */
+
+/* old descriptor 4-word */
+typedef struct {
+	volatile u32 dcmd;	/* DCMD value for the current transfer */
+	volatile u32 dsadr;	/* DSAR value for the current transfer */
+	volatile u32 dtadr;	/* DTAR value for the current transfer */
+	volatile u32 ddadr;	/* Points to the next descriptor + transfer count */
+} jz_dma_desc;
+
+/* new descriptor 8-word */
+typedef struct {
+	volatile u32 dcmd;	/* DCMD value for the current transfer */
+	volatile u32 dsadr;	/* DSAR value for the current transfer */
+	volatile u32 dtadr;	/* DTAR value for the current transfer */
+	volatile u32 ddadr;	/* Points to the next descriptor + transfer count */
+	volatile u32 dstrd;     /* DMA source and target stride address */
+	volatile u32 dreqt;     /* DMA request type for current transfer */
+	volatile u32 reserved0;	/* Reserved */
+	volatile u32 reserved1;	/* Reserved */
+} jz_dma_desc_8word;
+
+/* new descriptor 8-word */
+typedef struct {
+	volatile u32 dcmd;	/* DCMD value for the current transfer */
+	volatile u32 dsadr;	/* DSAR value for the current transfer */
+	volatile u32 dtadr;	/* DTAR value for the current transfer */
+	volatile u32 dcnt;	/* transfer count */
+	volatile u32 dstrd; /* DMA source and target stride address */
+	volatile u32 dreqt; /* DMA request type for current transfer */
+	volatile u32 dnt;	/* NAND detect timer enable(15) and value(0~5), and Tail counter(22~16)*/
+	volatile u32 ddadr;	/* Next descriptor address(31~4)  */
+} jz_bdma_desc_8word;
+
+/* DMA Device ID's follow */
+enum {
+	DMA_ID_AUTO = 0,		/* Auto-request */
+//	DMA_ID_TSSI_RX,		/* TSSI receive fifo full request */
+	DMA_ID_UART3_TX,	/* UART3 transmit-fifo-empty request */
+	DMA_ID_UART3_RX,	/* UART3 receve-fifo-full request */
+	DMA_ID_UART2_TX,	/* UART2 transmit-fifo-empty request */
+	DMA_ID_UART2_RX,	/* UART2 receve-fifo-full request */
+	DMA_ID_UART1_TX,	/* UART1 transmit-fifo-empty request */
+	DMA_ID_UART1_RX,	/* UART1 receve-fifo-full request */
+	DMA_ID_UART0_TX,	/* UART0 transmit-fifo-empty request */
+	DMA_ID_UART0_RX,	/* UART0 receve-fifo-full request */
+	DMA_ID_SSI0_TX,		/* SSI0 transmit-fifo-full request */
+	DMA_ID_SSI0_RX,		/* SSI0 receive-fifo-empty request */
+	DMA_ID_AIC_TX,		/* AIC transmit-fifo-full request */
+	DMA_ID_AIC_RX,		/* AIC receive-fifo-empty request */
+	DMA_ID_MSC0,
+	DMA_ID_TCU_OVERFLOW,	/* TCU channel n overflow interrupt */
+	DMA_ID_SADC,		/* SADC transfer request */
+	DMA_ID_MSC1,
+	DMA_ID_MSC2,
+	DMA_ID_SSI1_TX,		/* SSI1 transmit-fifo-full request */
+	DMA_ID_SSI1_RX,		/* SSI1 receive-fifo-empty request */
+	DMA_ID_PCM_TX,		/* PM transmit-fifo-full request */
+	DMA_ID_PCM_RX,		/* PM receive-fifo-empty request */
+	DMA_ID_RAW_SET,
+	DMA_ID_I2C0,
+	DMA_ID_I2C1,
+	DMA_ID_I2C2,
+	DMA_ID_MAX
+};
+
+/* DMA modes, simulated by sw */
+#define DMA_MODE_READ	0x0  /* I/O to memory, no autoinit, increment, single mode */
+#define DMA_MODE_WRITE	0x1  /* memory to I/O, no autoinit, increment, single mode */
+#define DMA_AUTOINIT	0x2
+#define DMA_MODE_MASK	0x3
+
+struct jz_dma_chan {
+	int dev_id;	/* DMA ID: this channel is allocated if >=0, free otherwise */
+	unsigned int io;        /* DMA channel number */
+	const char *dev_str;    /* string describes the DMA channel */
+	int irq;                /* DMA irq number */
+	void *irq_dev;          /* DMA private device structure */
+	unsigned int fifo_addr; /* physical fifo address of the requested device */
+	unsigned int cntl;	/* DMA controll */
+	unsigned int mode;      /* DMA configuration */
+	unsigned int source;    /* DMA request source */
+};
+
+extern struct jz_dma_chan jz_dma_table[];
+
+
+#define DMA_8BIT_RX_CMD					\
+	DMAC_DCMD_DAI |					\
+	DMAC_DCMD_SWDH_8 | DMAC_DCMD_DWDH_32 |		\
+	DMAC_DCMD_DS_8BIT | DMAC_DCMD_RDIL_IGN
+
+#define DMA_8BIT_TX_CMD					\
+	DMAC_DCMD_SAI |					\
+	DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_8 |		\
+	DMAC_DCMD_DS_8BIT | DMAC_DCMD_RDIL_IGN
+
+#define DMA_16BIT_RX_CMD				\
+	DMAC_DCMD_DAI |					\
+	DMAC_DCMD_SWDH_16 | DMAC_DCMD_DWDH_32 |		\
+	DMAC_DCMD_DS_16BIT | DMAC_DCMD_RDIL_IGN
+
+#define DMA_16BIT_TX_CMD				\
+	DMAC_DCMD_SAI |					\
+	DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_16 |		\
+	DMAC_DCMD_DS_16BIT | DMAC_DCMD_RDIL_IGN
+
+#define DMA_32BIT_RX_CMD				\
+	DMAC_DCMD_DAI |					\
+	DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 |		\
+	DMAC_DCMD_DS_32BIT | DMAC_DCMD_RDIL_IGN
+
+#define DMA_32BIT_TX_CMD				\
+	DMAC_DCMD_SAI |					\
+	DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 |		\
+	DMAC_DCMD_DS_32BIT | DMAC_DCMD_RDIL_IGN
+
+#define DMA_16BYTE_RX_CMD				\
+	DMAC_DCMD_DAI |					\
+	DMAC_DCMD_SWDH_8 | DMAC_DCMD_DWDH_32 |		\
+	DMAC_DCMD_DS_16BYTE | DMAC_DCMD_RDIL_IGN
+
+#define DMA_16BYTE_TX_CMD				\
+	DMAC_DCMD_SAI |					\
+	DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_8 |		\
+	DMAC_DCMD_DS_16BYTE | DMAC_DCMD_RDIL_IGN
+
+#define DMA_32BYTE_RX_CMD				\
+	DMAC_DCMD_DAI |					\
+	DMAC_DCMD_SWDH_8 | DMAC_DCMD_DWDH_32 |		\
+	DMAC_DCMD_DS_32BYTE | DMAC_DCMD_RDIL_IGN
+
+#define DMA_32BYTE_TX_CMD				\
+	DMAC_DCMD_SAI |					\
+	DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_8 |		\
+	DMAC_DCMD_DS_32BYTE | DMAC_DCMD_RDIL_IGN
+
+#define DMA_AIC_32_32BYTE_TX_CMD		       	\
+	DMAC_DCMD_SAI |					\
+	DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 |		\
+	DMAC_DCMD_DS_32BYTE | DMAC_DCMD_RDIL_IGN
+#define DMA_AIC_32_16BYTE_TX_CMD		       	\
+	DMAC_DCMD_SAI |					\
+	DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 |		\
+	DMAC_DCMD_DS_16BYTE | DMAC_DCMD_RDIL_IGN
+
+#define DMA_AIC_32_16BYTE_RX_CMD			\
+	DMAC_DCMD_DAI |					\
+	DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 |		\
+	DMAC_DCMD_DS_16BYTE | DMAC_DCMD_RDIL_IGN
+
+#define DMA_AIC_16BIT_TX_CMD				\
+	DMAC_DCMD_SAI |					\
+	DMAC_DCMD_SWDH_16 | DMAC_DCMD_DWDH_16 |		\
+	DMAC_DCMD_DS_16BIT | DMAC_DCMD_RDIL_IGN
+
+#define DMA_AIC_16BIT_RX_CMD				\
+	DMAC_DCMD_DAI |					\
+	DMAC_DCMD_SWDH_16 | DMAC_DCMD_DWDH_16 |		\
+	DMAC_DCMD_DS_16BIT | DMAC_DCMD_RDIL_IGN
+
+#define DMA_AIC_16BYTE_RX_CMD				\
+	DMAC_DCMD_DAI |					\
+	DMAC_DCMD_SWDH_16 | DMAC_DCMD_DWDH_16 |		\
+	DMAC_DCMD_DS_16BYTE | DMAC_DCMD_RDIL_IGN
+
+#define DMA_AIC_16BYTE_TX_CMD				\
+	DMAC_DCMD_SAI |					\
+	DMAC_DCMD_SWDH_16 | DMAC_DCMD_DWDH_16 |		\
+	DMAC_DCMD_DS_16BYTE | DMAC_DCMD_RDIL_IGN
+
+#define DMA_AIC_16BYTE_TX_CMD_UC			\
+	DMAC_DCMD_SAI |					\
+	DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_16 |		\
+	DMAC_DCMD_DS_16BYTE | DMAC_DCMD_RDIL_IGN
+
+#define DMA_AIC_TX_CMD_UNPACK				\
+	DMAC_DCMD_SAI |					\
+	DMAC_DCMD_SWDH_16 | DMAC_DCMD_DWDH_16 |		\
+	DMAC_DCMD_DS_32BIT | DMAC_DCMD_RDIL_IGN
+
+#define DMA_AIC_TX_CMD_PACK				\
+	DMAC_DCMD_SAI |					\
+	DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 |		\
+	DMAC_DCMD_DS_32BIT | DMAC_DCMD_RDIL_IGN
+
+extern int jz_request_dma(int dev_id,
+			  const char *dev_str,
+			  irqreturn_t (*irqhandler)(int, void *),
+			  unsigned long irqflags,
+			  void *irq_dev_id);
+extern void jz_free_dma(unsigned int dmanr);
+
+extern int jz_dma_read_proc(char *buf, char **start, off_t fpos,
+			      int length, int *eof, void *data);
+extern void dump_jz_dma_channel(unsigned int dmanr);
+extern void dump_jz_bdma_channel(unsigned int dmanr);
+
+extern void enable_dma(unsigned int dmanr);
+extern void disable_dma(unsigned int dmanr);
+extern void set_dma_addr(unsigned int dmanr, unsigned int phyaddr);
+extern void set_dma_count(unsigned int dmanr, unsigned int bytecnt);
+extern void set_dma_mode(unsigned int dmanr, unsigned int mode);
+extern void jz_set_oss_dma(unsigned int dmanr, unsigned int mode, unsigned int audio_fmt);
+extern void jz_set_alsa_dma(unsigned int dmanr, unsigned int mode, unsigned int audio_fmt);
+extern void jz_set_dma_src_width(int dmanr, int nbit);
+extern void jz_set_dma_dest_width(int dmanr, int nbit);
+extern void jz_set_dma_block_size(int dmanr, int nbyte);
+extern unsigned int get_dma_residue(unsigned int dmanr);
+extern spinlock_t  dma_spin_lock;
+
+static __inline__ unsigned long claim_dma_lock(void)
+{
+	unsigned long flags;
+	spin_lock_irqsave(&dma_spin_lock, flags);
+	return flags;
+}
+
+static __inline__ void release_dma_lock(unsigned long flags)
+{
+	spin_unlock_irqrestore(&dma_spin_lock, flags);
+}
+
+/* Clear the 'DMA Pointer Flip Flop'.
+ * Write 0 for LSB/MSB, 1 for MSB/LSB access.
+ */
+#define clear_dma_ff(channel)
+
+static __inline__ struct jz_dma_chan *get_dma_chan(unsigned int dmanr)
+{
+	if (dmanr > MAX_DMA_NUM
+	    || jz_dma_table[dmanr].dev_id < 0)
+		return NULL;
+	return &jz_dma_table[dmanr];
+}
+
+static __inline__ int dma_halted(unsigned int dmanr)
+{
+	struct jz_dma_chan *chan = get_dma_chan(dmanr);
+	if (!chan)
+		return 1;
+	return  __dmac_channel_transmit_halt_detected(dmanr) ? 1 : 0;
+}
+
+static __inline__ unsigned int get_dma_mode(unsigned int dmanr)
+{
+	struct jz_dma_chan *chan = get_dma_chan(dmanr);
+	if (!chan)
+		return 0;
+	return chan->mode;
+}
+
+static __inline__ void clear_dma_done(unsigned int dmanr)
+{
+	struct jz_dma_chan *chan = get_dma_chan(dmanr);
+	if (!chan)
+		return;
+	REG_DMAC_DCCSR(chan->io) &= ~(DMAC_DCCSR_HLT | DMAC_DCCSR_TT | DMAC_DCCSR_AR);
+}
+
+static __inline__ void clear_dma_halt(unsigned int dmanr)
+{
+	struct jz_dma_chan *chan = get_dma_chan(dmanr);
+	if (!chan)
+		return;
+	REG_DMAC_DCCSR(chan->io) &= ~(DMAC_DCCSR_HLT);
+	REG_DMAC_DMACR((chan->io)/HALF_DMA_NUM) &= ~(DMAC_DMACR_HLT);
+}
+
+static __inline__ void clear_dma_flag(unsigned int dmanr)
+{
+	struct jz_dma_chan *chan = get_dma_chan(dmanr);
+	if (!chan)
+		return;
+	REG_DMAC_DCCSR(chan->io) &= ~(DMAC_DCCSR_HLT | DMAC_DCCSR_TT | DMAC_DCCSR_AR);
+	REG_DMAC_DMACR((chan->io)/HALF_DMA_NUM) &= ~(DMAC_DMACR_HLT | DMAC_DMACR_AR);
+}
+
+static __inline__ void set_dma_page(unsigned int dmanr, char pagenr)
+{
+}
+
+static __inline__ unsigned int get_dma_done_status(unsigned int dmanr)
+{
+	unsigned long dccsr;
+	struct jz_dma_chan *chan = get_dma_chan(dmanr);
+	if (!chan)
+		return 0;
+	dccsr = REG_DMAC_DCCSR(chan->io);
+	return dccsr & (DMAC_DCCSR_HLT | DMAC_DCCSR_TT | DMAC_DCCSR_AR);
+}
+
+static __inline__ int get_dma_done_irq(unsigned int dmanr)
+{
+	struct jz_dma_chan *chan = get_dma_chan(dmanr);
+	if (!chan)
+		return -1;
+	return chan->irq;
+}
+
+#endif  /* __ASM_JZ4770_DMA_H__ */
diff --git a/arch/mips/include/asm/mach-jz4770/irq.h b/arch/mips/include/asm/mach-jz4770/irq.h
new file mode 100644
index 00000000000..6c7ab262bd3
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4770/irq.h
@@ -0,0 +1,21 @@
+/*
+ *  linux/arch/mips/include/asm/mach-jz4810/irq.h
+ *
+ *  JZ4810 IRQ definition.
+ *
+ *  Copyright (C) 2010 Ingenic Semiconductor Inc.
+ *
+ *  Author: <yliu@ingenic.cn>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_JZ4770_IRQ_H__
+#define __ASM_JZ4770_IRQ_H__
+
+/* we need 256 irq levels at least */
+#define NR_IRQS	384
+
+#endif
diff --git a/arch/mips/include/asm/mach-jz4770/jz4770.h b/arch/mips/include/asm/mach-jz4770/jz4770.h
new file mode 100644
index 00000000000..8602c6e4ea8
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4770/jz4770.h
@@ -0,0 +1,79 @@
+/*
+ *  linux/include/asm-mips/mach-jz4770/jz4770.h
+ *
+ *  JZ4770 common definition.
+ *
+ *  Copyright (C) 2008 Ingenic Semiconductor Inc.
+ *
+ *  Author: <cwjia@ingenic.cn>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_JZ4770_H__
+#define __ASM_JZ4770_H__
+
+#include <asm/mach-jz4770/regs.h>
+
+#include <asm/mach-jz4770/jz4770misc.h>
+#include <asm/mach-jz4770/jz4770gpio.h>
+#include <asm/mach-jz4770/jz4770dmac.h>
+#include <asm/mach-jz4770/jz4770intc.h>
+#include <asm/mach-jz4770/jz4770aic.h>
+#include <asm/mach-jz4770/jz4770bch.h>
+#include <asm/mach-jz4770/jz4770bdma.h>
+#include <asm/mach-jz4770/jz4770cim.h>
+#include <asm/mach-jz4770/jz4770cpm.h>
+#include <asm/mach-jz4770/jz4770ddrc.h>
+#include <asm/mach-jz4770/jz4770emc.h>
+#include <asm/mach-jz4770/jz4770i2c.h>
+#include <asm/mach-jz4770/jz4770ipu.h>
+#include <asm/mach-jz4770/jz4770lcdc.h>
+#include <asm/mach-jz4770/jz4770mc.h>
+#include <asm/mach-jz4770/jz4770mdma.h>
+#include <asm/mach-jz4770/jz4770me.h>
+#include <asm/mach-jz4770/jz4770msc.h>
+#include <asm/mach-jz4770/jz4770nemc.h>
+#include <asm/mach-jz4770/jz4770otg.h>
+#include <asm/mach-jz4770/jz4770otp.h>
+#include <asm/mach-jz4770/jz4770owi.h>
+#include <asm/mach-jz4770/jz4770ost.h>
+#include <asm/mach-jz4770/jz4770pcm.h>
+#include <asm/mach-jz4770/jz4770rtc.h>
+#include <asm/mach-jz4770/jz4770sadc.h>
+#include <asm/mach-jz4770/jz4770scc.h>
+#include <asm/mach-jz4770/jz4770ssi.h>
+#include <asm/mach-jz4770/jz4770tcu.h>
+#include <asm/mach-jz4770/jz4770tssi.h>
+#include <asm/mach-jz4770/jz4770tve.h>
+#include <asm/mach-jz4770/jz4770uart.h>
+#include <asm/mach-jz4770/jz4770wdt.h>
+#include <asm/mach-jz4770/jz4770aosd.h>
+
+#include <asm/mach-jz4770/dma.h>
+#include <asm/mach-jz4770/misc.h>
+
+/*------------------------------------------------------------------
+ * Platform definitions
+ */
+
+#define JZ_SOC_NAME "JZ4770"
+
+#ifdef CONFIG_JZ4770_F4770
+#include <asm/mach-jz4770/board-f4770.h>
+#endif
+
+
+/* Add other platform definition here ... */
+
+
+/*------------------------------------------------------------------
+ * Follows are related to platform definitions
+ */
+
+#include <asm/mach-jz4770/clock.h>
+#include <asm/mach-jz4770/serial.h>
+
+#endif /* __ASM_JZ4770_H__ */
diff --git a/arch/mips/include/asm/mach-jz4770/jz4770aic.h b/arch/mips/include/asm/mach-jz4770/jz4770aic.h
new file mode 100644
index 00000000000..3ac4832f3a6
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4770/jz4770aic.h
@@ -0,0 +1,769 @@
+/*

+ * chip-aic.h

+ * JZ4760 AIC register definition

+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

+ *

+ * Author: whxu@ingenic.cn

+ */

+

+#ifndef __CHIP_AIC_H__

+#define __CHIP_AIC_H__

+

+

+/*

+ * AC97 and I2S controller module(AIC) address definition

+ */

+#define	AIC_BASE	0xb0020000

+//#define	AIC_BASE	0xb0024000

+

+

+/*

+ * AIC registers offset address definition

+ */

+#define AIC_FR_OFFSET		(0x00)

+#define AIC_CR_OFFSET		(0x04)

+#define AIC_ACCR1_OFFSET	(0x08)

+#define AIC_ACCR2_OFFSET	(0x0c)

+#define AIC_I2SCR_OFFSET	(0x10)

+#define AIC_SR_OFFSET		(0x14)

+#define AIC_ACSR_OFFSET		(0x18)

+#define AIC_I2SSR_OFFSET	(0x1c)

+#define AIC_ACCAR_OFFSET	(0x20)

+#define AIC_ACCDR_OFFSET	(0x24)

+#define AIC_ACSAR_OFFSET	(0x28)

+#define AIC_ACSDR_OFFSET	(0x2c)

+#define AIC_I2SDIV_OFFSET	(0x30)

+#define AIC_DR_OFFSET		(0x34)

+

+#define SPDIF_ENA_OFFSET	(0x80)

+#define SPDIF_CTRL_OFFSET	(0x84)

+#define SPDIF_STATE_OFFSET	(0x88)

+#define SPDIF_CFG1_OFFSET	(0x8c)

+#define SPDIF_CFG2_OFFSET	(0x90)

+#define SPDIF_FIFO_OFFSET	(0x94)

+

+#define ICDC_RGADW_OFFSET	(0xa4)

+#define ICDC_RGDATA_OFFSET	(0xa8)

+

+

+/*

+ * AIC registers address definition

+ */

+#define AIC_FR		(AIC_BASE + AIC_FR_OFFSET)

+#define AIC0_FR		(0xb0020000 + AIC_FR_OFFSET)

+#define AIC_CR		(AIC_BASE + AIC_CR_OFFSET)

+#define AIC_ACCR1	(AIC_BASE + AIC_ACCR1_OFFSET)

+#define AIC_ACCR2	(AIC_BASE + AIC_ACCR2_OFFSET)

+#define AIC_I2SCR	(AIC_BASE + AIC_I2SCR_OFFSET)

+#define AIC_SR		(AIC_BASE + AIC_SR_OFFSET)

+#define AIC_ACSR	(AIC_BASE + AIC_ACSR_OFFSET)

+#define AIC_I2SSR	(AIC_BASE + AIC_I2SSR_OFFSET)

+#define AIC_ACCAR	(AIC_BASE + AIC_ACCAR_OFFSET)

+#define AIC_ACCDR	(AIC_BASE + AIC_ACCDR_OFFSET)

+#define AIC_ACSAR	(AIC_BASE + AIC_ACSAR_OFFSET)

+#define AIC_ACSDR	(AIC_BASE + AIC_ACSDR_OFFSET)

+#define AIC_I2SDIV	(AIC_BASE + AIC_I2SDIV_OFFSET)

+#define AIC_DR		(AIC_BASE + AIC_DR_OFFSET)

+

+#define SPDIF_ENA	(AIC_BASE + SPDIF_ENA_OFFSET)

+#define SPDIF_CTRL	(AIC_BASE + SPDIF_CTRL_OFFSET)

+#define SPDIF_STATE	(AIC_BASE + SPDIF_STATE_OFFSET)

+#define SPDIF_CFG1	(AIC_BASE + SPDIF_CFG1_OFFSET)

+#define SPDIF_CFG2	(AIC_BASE + SPDIF_CFG2_OFFSET)

+#define SPDIF_FIFO	(AIC_BASE + SPDIF_FIFO_OFFSET)

+

+#define ICDC_RGADW	(0xb0020000 + ICDC_RGADW_OFFSET)

+#define ICDC_RGDATA	(0xb0020000 + ICDC_RGDATA_OFFSET)

+

+

+/*

+ * AIC registers common define

+ */

+

+/* AIC controller configuration register(AICFR) */

+#define	AIC_FR_LSMP		BIT6

+#define	AIC_FR_ICDC		BIT5

+#define	AIC_FR_AUSEL		BIT4

+#define	AIC_FR_RST		BIT3

+#define	AIC_FR_BCKD		BIT2

+#define	AIC_FR_SYNCD		BIT1

+#define	AIC_FR_ENB		BIT0

+

+#define	AIC_FR_RFTH_LSB		24

+#define	AIC_FR_RFTH_MASK	BITS_H2L(27, AIC_FR_RFTH_LSB)

+

+#define	AIC_FR_TFTH_LSB		16

+#define	AIC_FR_TFTH_MASK	BITS_H2L(20, AIC_FR_TFTH_LSB)

+

+/* AIC controller common control register(AICCR) */

+#define AIC_CR_PACK16		BIT28

+#define	AIC_CR_RDMS		BIT15

+#define	AIC_CR_TDMS		BIT14

+#define	AIC_CR_M2S		BIT11

+#define	AIC_CR_ENDSW		BIT10

+#define	AIC_CR_AVSTSU		BIT9

+#define	AIC_CR_TFLUSH		BIT8

+#define	AIC_CR_RFLUSH		BIT7

+#define	AIC_CR_EROR		BIT6

+#define	AIC_CR_ETUR		BIT5

+#define	AIC_CR_ERFS		BIT4

+#define	AIC_CR_ETFS		BIT3

+#define	AIC_CR_ENLBF		BIT2

+#define	AIC_CR_ERPL		BIT1

+#define	AIC_CR_EREC		BIT0

+

+#define AIC_CR_CHANNEL_LSB	24

+#define AIC_CR_CHANNEL_MASK	BITS_H2L(26, AIC_CR_CHANNEL_LSB)

+

+#define	AIC_CR_OSS_LSB		19

+#define	AIC_CR_OSS_MASK		BITS_H2L(21, AIC_CR_OSS_LSB)

+ #define AIC_CR_OSS(n)		(((n) > 18 ? (n)/6 : (n)/9) << AIC_CR_OSS_LSB)	/* n = 8, 16, 18, 20, 24 */

+

+#define	AIC_CR_ISS_LSB		16

+#define	AIC_CR_ISS_MASK		BITS_H2L(18, AIC_CR_ISS_LSB)

+ #define AIC_CR_ISS(n)		(((n) > 18 ? (n)/6 : (n)/9) << AIC_CR_ISS_LSB)	/* n = 8, 16, 18, 20, 24 */

+

+/* AIC controller AC-link control register 1(ACCR1) */

+#define AIC_ACCR1_RS_LSB	16

+#define	AIC_ACCR1_RS_MASK	BITS_H2L(25, AIC_ACCR1_RS_LSB)

+ #define AIC_ACCR1_RS_SLOT(n)	((1 << ((n) - 3)) << AIC_ACCR1_RS_LSB)	/* n = 3 .. 12 */

+

+#define AIC_ACCR1_XS_LSB	0

+#define	AIC_ACCR1_XS_MASK	BITS_H2L(9, AIC_ACCR1_XS_LSB)

+ #define AIC_ACCR1_XS_SLOT(n)	((1 << ((n) - 3)) << AIC_ACCR1_XS_LSB)	/* n = 3 .. 12 */

+

+/* AIC controller AC-link control register 2 (ACCR2) */

+#define	AIC_ACCR2_ERSTO		BIT18

+#define	AIC_ACCR2_ESADR		BIT17

+#define	AIC_ACCR2_ECADT		BIT16

+#define	AIC_ACCR2_SO		BIT3

+#define	AIC_ACCR2_SR		BIT2

+#define	AIC_ACCR2_SS		BIT1

+#define	AIC_ACCR2_SA		BIT0

+

+/* AIC controller i2s/msb-justified control register (I2SCR) */

+#define	AIC_I2SCR_RFIRST	BIT17

+#define	AIC_I2SCR_SWLH   	BIT16

+#define	AIC_I2SCR_STPBK		BIT12

+#define AIC_I2SCR_ESCLK		BIT4

+#define	AIC_I2SCR_AMSL		BIT0

+

+/* AIC controller FIFO status register (AICSR) */

+#define	AIC_SR_ROR		BIT6

+#define	AIC_SR_TUR		BIT5

+#define	AIC_SR_RFS		BIT4

+#define	AIC_SR_TFS		BIT3

+

+#define	AIC_SR_RFL_LSB		24

+#define	AIC_SR_RFL_MASK		BITS_H2L(29, AIC_SR_RFL_LSB)

+

+#define	AIC_SR_TFL_LSB		8

+#define	AIC_SR_TFL_MASK		BITS_H2L(13, AIC_SR_TFL_LSB)

+

+/* AIC controller AC-link status register (ACSR) */

+#define	AIC_ACSR_SLTERR		BIT21

+#define	AIC_ACSR_CRDY		BIT20

+#define	AIC_ACSR_CLPM		BIT19

+#define	AIC_ACSR_RSTO		BIT18

+#define	AIC_ACSR_SADR		BIT17

+#define	AIC_ACSR_CADT		BIT16

+

+/* AIC controller I2S/MSB-justified status register (I2SSR) */

+#define	AIC_I2SSR_CHBSY		BIT5

+#define	AIC_I2SSR_TBSY		BIT4

+#define	AIC_I2SSR_RBSY		BIT3

+#define	AIC_I2SSR_BSY		BIT2

+

+/* AIC controller AC97 codec command address register (ACCAR) */

+#define	AIC_ACCAR_CAR_LSB	0

+#define	AIC_ACCAR_CAR_MASK	BITS_H2L(19, AIC_ACCAR_CAR_LSB)

+

+

+/* AIC controller AC97 codec command data register (ACCDR) */

+#define	AIC_ACCDR_CDR_LSB	0

+#define	AIC_ACCDR_CDR_MASK	BITS_H2L(19, AIC_ACCDR_CDR_LSB)

+

+/* AC97 read and write macro based on ACCAR and ACCDR */

+#define AC97_READ_CMD		BIT19

+#define AC97_WRITE_CMD		(BIT19 & ~BIT19)

+

+#define AC97_INDEX_LSB		12

+#define AC97_INDEX_MASK		BITS_H2L(18, AC97_INDEX_LSB)

+

+#define AC97_DATA_LSB		4

+#define AC97_DATA_MASK		BITS_H2L(19, AC97_DATA_LSB)

+

+/* AIC controller AC97 codec status address register (ACSAR) */

+#define	AIC_ACSAR_SAR_LSB	0

+#define	AIC_ACSAR_SAR_MASK	BITS_H2L(19, AIC_ACSAR_SAR_LSB)

+

+/* AIC controller AC97 codec status data register (ACSDR) */

+#define	AIC_ACSDR_SDR_LSB	0

+#define	AIC_ACSDR_SDR_MASK	BITS_H2L(19, AIC_ACSDR_SDR_LSB)

+

+/* AIC controller I2S/MSB-justified clock divider register (I2SDIV) */

+#define	AIC_I2SDIV_DIV_LSB	0

+#define	AIC_I2SDIV_DIV_MASK	BITS_H2L(3, AIC_I2SDIV_DIV_LSB)

+

+/* SPDIF enable register (SPDIF_ENA) */

+#define SPDIF_ENA_SPEN		BIT0

+

+/* SPDIF control register (SPDIF_CTRL) */

+#define SPDIF_CTRL_DMAEN        BIT15

+#define SPDIF_CTRL_DTYPE        BIT14

+#define SPDIF_CTRL_SIGN         BIT13

+#define SPDIF_CTRL_INVALID      BIT12

+#define SPDIF_CTRL_RST          BIT11

+#define SPDIF_CTRL_SPDIFI2S     BIT10

+#define SPDIF_CTRL_MTRIG        BIT1

+#define SPDIF_CTRL_MFFUR        BIT0

+

+/* SPDIF state register (SPDIF_STAT) */

+#define SPDIF_STAT_BUSY		BIT7

+#define SPDIF_STAT_FTRIG	BIT1

+#define SPDIF_STAT_FUR		BIT0

+

+#define SPDIF_STAT_FLVL_LSB	8

+#define SPDIF_STAT_FLVL_MASK	BITS_H2L(14, SPDIF_STAT_FLVL_LSB)

+

+/* SPDIF configure 1 register (SPDIF_CFG1) */

+#define SPDIF_CFG1_INITLVL	BIT17

+#define SPDIF_CFG1_ZROVLD	BIT16

+

+#define SPDIF_CFG1_TRIG_LSB	12

+#define SPDIF_CFG1_TRIG_MASK	BITS_H2L(13, SPDIF_CFG1_TRIG_LSB)

+#define SPDIF_CFG1_TRIG(n)	(((n) > 16 ? 3 : (n)/8) << SPDIF_CFG1_TRIG_LSB)	/* n = 4, 8, 16, 32 */

+

+#define SPDIF_CFG1_SRCNUM_LSB	8

+#define SPDIF_CFG1_SRCNUM_MASK	BITS_H2L(11, SPDIF_CFG1_SRCNUM_LSB)

+

+#define SPDIF_CFG1_CH1NUM_LSB	4

+#define SPDIF_CFG1_CH1NUM_MASK	BITS_H2L(7, SPDIF_CFG1_CH1NUM_LSB)

+

+#define SPDIF_CFG1_CH2NUM_LSB	0

+#define SPDIF_CFG1_CH2NUM_MASK	BITS_H2L(3, SPDIF_CFG1_CH2NUM_LSB)

+

+/* SPDIF configure 2 register (SPDIF_CFG2) */

+#define SPDIF_CFG2_MAXWL	BIT18

+#define SPDIF_CFG2_PRE		BIT3

+#define SPDIF_CFG2_COPYN	BIT2

+#define SPDIF_CFG2_AUDION	BIT1

+#define SPDIF_CFG2_CONPRO	BIT0

+

+#define SPDIF_CFG2_FS_LSB	26

+#define SPDIF_CFG2_FS_MASK	BITS_H2L(29, SPDIF_CFG2_FS_LSB)

+

+#define SPDIF_CFG2_ORGFRQ_LSB	22

+#define SPDIF_CFG2_ORGFRQ_MASK	BITS_H2L(25, SPDIF_CFG2_ORGFRQ_LSB)

+

+#define SPDIF_CFG2_SAMWL_LSB	19

+#define SPDIF_CFG2_SAMWL_MASK	BITS_H2L(21, SPDIF_CFG2_SAMWL_LSB)

+

+#define SPDIF_CFG2_CLKACU_LSB	16

+#define SPDIF_CFG2_CLKACU_MASK	BITS_H2L(17, SPDIF_CFG2_CLKACU_LSB)

+

+#define SPDIF_CFG2_CATCODE_LSB	8

+#define SPDIF_CFG2_CATCODE_MASK	BITS_H2L(15, SPDIF_CFG2_CATCODE_LSB)

+

+#define SPDIF_CFG2_CHMD_LSB	6

+#define SPDIF_CFG2_CHMD_MASK	BITS_H2L(7, SPDIF_CFG2_CHMD_LSB)

+

+/* ICDC internal register access control register(RGADW) */

+#define ICDC_RGADW_RGWR		BIT16

+

+#define ICDC_RGADW_RGADDR_LSB	8

+#define	ICDC_RGADW_RGADDR_MASK	BITS_H2L(14, ICDC_RGADW_RGADDR_LSB)

+

+#define ICDC_RGADW_RGDIN_LSB	0

+#define	ICDC_RGADW_RGDIN_MASK	BITS_H2L(7, ICDC_RGADW_RGDIN_LSB)

+

+/* ICDC internal register data output register (RGDATA)*/

+#define ICDC_RGDATA_IRQ		BIT8

+

+#define ICDC_RGDATA_RGDOUT_LSB	0

+#define ICDC_RGDATA_RGDOUT_MASK	BITS_H2L(7, ICDC_RGDATA_RGDOUT_LSB)

+

+

+#ifndef __MIPS_ASSEMBLER

+

+

+#define	REG_AIC_FR		REG32(AIC_FR)

+#define	REG_AIC0_FR		REG32(AIC0_FR)

+#define	REG_AIC_CR		REG32(AIC_CR)

+#define	REG_AIC_ACCR1		REG32(AIC_ACCR1)

+#define	REG_AIC_ACCR2		REG32(AIC_ACCR2)

+#define	REG_AIC_I2SCR		REG32(AIC_I2SCR)

+#define	REG_AIC_SR		REG32(AIC_SR)

+#define	REG_AIC_ACSR		REG32(AIC_ACSR)

+#define	REG_AIC_I2SSR		REG32(AIC_I2SSR)

+#define	REG_AIC_ACCAR		REG32(AIC_ACCAR)

+#define	REG_AIC_ACCDR		REG32(AIC_ACCDR)

+#define	REG_AIC_ACSAR		REG32(AIC_ACSAR)

+#define	REG_AIC_ACSDR		REG32(AIC_ACSDR)

+#define	REG_AIC_I2SDIV		REG32(AIC_I2SDIV)

+#define	REG_AIC_DR		REG32(AIC_DR)

+

+#define REG_SPDIF_ENA		REG32(SPDIF_ENA)

+#define REG_SPDIF_CTRL		REG32(SPDIF_CTRL)

+#define REG_SPDIF_STATE		REG32(SPDIF_STATE)

+#define REG_SPDIF_CFG1		REG32(SPDIF_CFG1)

+#define REG_SPDIF_CFG2		REG32(SPDIF_CFG2)

+#define REG_SPDIF_FIFO		REG32(SPDIF_FIFO)

+

+#define	REG_ICDC_RGADW		REG32(ICDC_RGADW)

+#define	REG_ICDC_RGDATA		REG32(ICDC_RGDATA)

+

+

+#define __aic_enable()		( REG_AIC_FR |= AIC_FR_ENB )

+#define __aic_disable()		( REG_AIC_FR &= ~AIC_FR_ENB )

+

+#define __aic_select_ac97()	( REG_AIC_FR &= ~AIC_FR_AUSEL )

+#define __aic_select_i2s()	( REG_AIC_FR |= AIC_FR_AUSEL )

+

+#define __aic_play_zero()	( REG_AIC_FR &= ~AIC_FR_LSMP )

+#define __aic_play_lastsample()	( REG_AIC_FR |= AIC_FR_LSMP )

+

+#define __i2s_as_master()	( REG_AIC_FR |= AIC_FR_BCKD | AIC_FR_SYNCD )

+#define __i2s_as_slave()	( REG_AIC_FR &= ~(AIC_FR_BCKD | AIC_FR_SYNCD) )

+#define __aic_reset_status()          ( REG_AIC_FR & AIC_FR_RST )

+

+#define __aic_reset()                                   \

+do {                                                    \

+        REG_AIC_FR |= AIC_FR_RST;                       \

+} while(0)

+

+

+#define __aic_set_transmit_trigger(n) 			\

+do {							\

+	REG_AIC_FR &= ~AIC_FR_TFTH_MASK;		\

+	REG_AIC_FR |= ((n) << AIC_FR_TFTH_LSB);		\

+} while(0)

+

+#define __aic_set_receive_trigger(n) 			\

+do {							\

+	REG_AIC_FR &= ~AIC_FR_RFTH_MASK;		\

+	REG_AIC_FR |= ((n) << AIC_FR_RFTH_LSB);		\

+} while(0)

+

+#define __aic_enable_oldstyle()

+#define __aic_enable_newstyle()

+#define __aic_enable_pack16()   ( REG_AIC_CR |= AIC_CR_PACK16 )

+#define __aic_enable_unpack16() ( REG_AIC_CR &= ~AIC_CR_PACK16)

+

+/* n = AIC_CR_CHANNEL_MONO,AIC_CR_CHANNEL_STEREO ... */

+#define __aic_out_channel_select(n)                    \

+do {                                                   \

+	REG_AIC_CR &= ~AIC_CR_CHANNEL_MASK;            \

+        REG_AIC_CR |= ((n) << AIC_CR_CHANNEL_LSB );			       \

+} while(0)

+

+#define __aic_enable_record()	( REG_AIC_CR |= AIC_CR_EREC )

+#define __aic_disable_record()	( REG_AIC_CR &= ~AIC_CR_EREC )

+#define __aic_enable_replay()	( REG_AIC_CR |= AIC_CR_ERPL )

+#define __aic_disable_replay()	( REG_AIC_CR &= ~AIC_CR_ERPL )

+#define __aic_enable_loopback()	( REG_AIC_CR |= AIC_CR_ENLBF )

+#define __aic_disable_loopback() ( REG_AIC_CR &= ~AIC_CR_ENLBF )

+

+#define __aic_flush_tfifo()	( REG_AIC_CR |= AIC_CR_TFLUSH )

+#define __aic_unflush_tfifo()	( REG_AIC_CR &= ~AIC_CR_TFLUSH )

+#define __aic_flush_rfifo()	( REG_AIC_CR |= AIC_CR_RFLUSH )

+#define __aic_unflush_rfifo()	( REG_AIC_CR &= ~AIC_CR_RFLUSH )

+

+#define __aic_enable_transmit_intr() \

+  ( REG_AIC_CR |= (AIC_CR_ETFS | AIC_CR_ETUR) )

+#define __aic_disable_transmit_intr() \

+  ( REG_AIC_CR &= ~(AIC_CR_ETFS | AIC_CR_ETUR) )

+#define __aic_enable_receive_intr() \

+  ( REG_AIC_CR |= (AIC_CR_ERFS | AIC_CR_EROR) )

+#define __aic_disable_receive_intr() \

+  ( REG_AIC_CR &= ~(AIC_CR_ERFS | AIC_CR_EROR) )

+

+#define __aic_enable_transmit_dma()  ( REG_AIC_CR |= AIC_CR_TDMS )

+#define __aic_disable_transmit_dma() ( REG_AIC_CR &= ~AIC_CR_TDMS )

+#define __aic_enable_receive_dma()   ( REG_AIC_CR |= AIC_CR_RDMS )

+#define __aic_disable_receive_dma()  ( REG_AIC_CR &= ~AIC_CR_RDMS )

+

+#define __aic_enable_mono2stereo()   ( REG_AIC_CR |= AIC_CR_M2S )

+#define __aic_disable_mono2stereo()  ( REG_AIC_CR &= ~AIC_CR_M2S )

+#define __aic_enable_byteswap()      ( REG_AIC_CR |= AIC_CR_ENDSW )

+#define __aic_disable_byteswap()     ( REG_AIC_CR &= ~AIC_CR_ENDSW )

+#define __aic_enable_unsignadj()     ( REG_AIC_CR |= AIC_CR_AVSTSU )

+#define __aic_disable_unsignadj()    ( REG_AIC_CR &= ~AIC_CR_AVSTSU )

+

+#define AC97_PCM_XS_L_FRONT   	AIC_ACCR1_XS_SLOT(3)

+#define AC97_PCM_XS_R_FRONT   	AIC_ACCR1_XS_SLOT(4)

+#define AC97_PCM_XS_CENTER    	AIC_ACCR1_XS_SLOT(6)

+#define AC97_PCM_XS_L_SURR    	AIC_ACCR1_XS_SLOT(7)

+#define AC97_PCM_XS_R_SURR    	AIC_ACCR1_XS_SLOT(8)

+#define AC97_PCM_XS_LFE       	AIC_ACCR1_XS_SLOT(9)

+

+#define AC97_PCM_RS_L_FRONT   	AIC_ACCR1_RS_SLOT(3)

+#define AC97_PCM_RS_R_FRONT   	AIC_ACCR1_RS_SLOT(4)

+#define AC97_PCM_RS_CENTER    	AIC_ACCR1_RS_SLOT(6)

+#define AC97_PCM_RS_L_SURR    	AIC_ACCR1_RS_SLOT(7)

+#define AC97_PCM_RS_R_SURR    	AIC_ACCR1_RS_SLOT(8)

+#define AC97_PCM_RS_LFE       	AIC_ACCR1_RS_SLOT(9)

+

+#define __ac97_set_xs_none()	( REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK )

+#define __ac97_set_xs_mono() 						\

+do {									\

+	REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK;				\

+	REG_AIC_ACCR1 |= AC97_PCM_XS_R_FRONT;				\

+} while(0)

+#define __ac97_set_xs_stereo() 						\

+do {									\

+	REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK;				\

+	REG_AIC_ACCR1 |= AC97_PCM_XS_L_FRONT | AC97_PCM_XS_R_FRONT;	\

+} while(0)

+

+/* In fact, only stereo is support now. */

+#define __ac97_set_rs_none()	( REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK )

+#define __ac97_set_rs_mono() 						\

+do {									\

+	REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK;				\

+	REG_AIC_ACCR1 |= AC97_PCM_RS_R_FRONT;				\

+} while(0)

+#define __ac97_set_rs_stereo() 						\

+do {									\

+	REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK;				\

+	REG_AIC_ACCR1 |= AC97_PCM_RS_L_FRONT | AC97_PCM_RS_R_FRONT;	\

+} while(0)

+

+#define __ac97_warm_reset_codec()		\

+ do {						\

+	REG_AIC_ACCR2 |= AIC_ACCR2_SA;		\

+	REG_AIC_ACCR2 |= AIC_ACCR2_SS;		\

+	udelay(2);				\

+	REG_AIC_ACCR2 &= ~AIC_ACCR2_SS;		\

+	REG_AIC_ACCR2 &= ~AIC_ACCR2_SA;		\

+ } while (0)

+

+#define __ac97_cold_reset_codec()		\

+ do {						\

+	REG_AIC_ACCR2 |=  AIC_ACCR2_SR;		\

+	udelay(2);				\

+	REG_AIC_ACCR2 &= ~AIC_ACCR2_SR;		\

+ } while (0)

+

+/* n=8,16,18,20 */

+#define __ac97_set_iass(n) \

+ ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_IASS_MASK) | AIC_ACCR2_IASS_##n##BIT )

+#define __ac97_set_oass(n) \

+ ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_OASS_MASK) | AIC_ACCR2_OASS_##n##BIT )

+

+/* This bit should only be set in 2 channels configuration */

+#define __i2s_send_rfirst()   ( REG_AIC_I2SCR |= AIC_I2SCR_RFIRST )  /* RL */

+#define __i2s_send_lfirst()   ( REG_AIC_I2SCR &= ~AIC_I2SCR_RFIRST ) /* LR */

+

+/* This bit should only be set in 2 channels configuration and 16bit-packed mode */

+#define __i2s_switch_lr()     ( REG_AIC_I2SCR |= AIC_I2SCR_SWLH )

+#define __i2s_unswitch_lr()   ( REG_AIC_I2SCR &= ~AIC_I2SCR_SWLH )

+

+#define __i2s_select_i2s()            ( REG_AIC_I2SCR &= ~AIC_I2SCR_AMSL )

+#define __i2s_select_msbjustified()   ( REG_AIC_I2SCR |= AIC_I2SCR_AMSL )

+

+/* n=8,16,18,20,24 */

+/*#define __i2s_set_sample_size(n) \

+ ( REG_AIC_I2SCR |= (REG_AIC_I2SCR & ~AIC_I2SCR_WL_MASK) | AIC_I2SCR_WL_##n##BIT )*/

+

+#define __i2s_out_channel_select(n) __aic_out_channel_select(n)

+

+#define __i2s_set_oss_sample_size(n) \

+ ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_OSS_MASK) | AIC_CR_OSS(n))

+#define __i2s_set_iss_sample_size(n) \

+ ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_ISS_MASK) | AIC_CR_ISS(n))

+

+#define __i2s_stop_bitclk()   ( REG_AIC_I2SCR |= AIC_I2SCR_STPBK )

+#define __i2s_start_bitclk()  ( REG_AIC_I2SCR &= ~AIC_I2SCR_STPBK )

+

+#define __aic_transmit_request()  ( REG_AIC_SR & AIC_SR_TFS )

+#define __aic_receive_request()   ( REG_AIC_SR & AIC_SR_RFS )

+#define __aic_transmit_underrun() ( REG_AIC_SR & AIC_SR_TUR )

+#define __aic_receive_overrun()   ( REG_AIC_SR & AIC_SR_ROR )

+

+#define __aic_clear_errors()      ( REG_AIC_SR &= ~(AIC_SR_TUR | AIC_SR_ROR) )

+

+#define __aic_get_transmit_resident() \

+  ( (REG_AIC_SR & AIC_SR_TFL_MASK) >> AIC_SR_TFL_LSB )

+#define __aic_get_receive_count() \

+  ( (REG_AIC_SR & AIC_SR_RFL_MASK) >> AIC_SR_RFL_LSB )

+

+#define __ac97_command_transmitted()     ( REG_AIC_ACSR & AIC_ACSR_CADT )

+#define __ac97_status_received()         ( REG_AIC_ACSR & AIC_ACSR_SADR )

+#define __ac97_status_receive_timeout()  ( REG_AIC_ACSR & AIC_ACSR_RSTO )

+#define __ac97_codec_is_low_power_mode() ( REG_AIC_ACSR & AIC_ACSR_CLPM )

+#define __ac97_codec_is_ready()          ( REG_AIC_ACSR & AIC_ACSR_CRDY )

+#define __ac97_slot_error_detected()     ( REG_AIC_ACSR & AIC_ACSR_SLTERR )

+#define __ac97_clear_slot_error()        ( REG_AIC_ACSR &= ~AIC_ACSR_SLTERR )

+

+#define __i2s_is_busy()         ( REG_AIC_I2SSR & AIC_I2SSR_BSY )

+

+#define __ac97_out_rcmd_addr(reg) 					\

+do { 									\

+    REG_AIC_ACCAR = AC97_READ_CMD | ((reg) << AC97_INDEX_LSB); 	\

+} while (0)

+

+#define __ac97_out_wcmd_addr(reg) 					\

+do { 									\

+    REG_AIC_ACCAR = AC97_WRITE_CMD | ((reg) << AC97_INDEX_LSB); 	\

+} while (0)

+

+#define __ac97_out_data(value) 						\

+do { 									\

+    REG_AIC_ACCDR = ((value) << AC97_DATA_LSB); 			\

+} while (0)

+

+#define __ac97_in_data() \

+ ( (REG_AIC_ACSDR & CODEC_REG_DATA_MASK) >> AC97_DATA_LSB )

+

+#define __ac97_in_status_addr() \

+ ( (REG_AIC_ACSAR & AC97_INDEX_MASK) >> AC97_INDEX_LSB )

+

+#define __i2s_set_sample_rate(i2sclk, sync) \

+  ( REG_AIC_I2SDIV = ((i2sclk) / (4*64)) / (sync) )

+

+#define __aic_write_tfifo(v)  ( REG_AIC_DR = (v) )

+#define __aic_read_rfifo()    ( REG_AIC_DR )

+

+#define __aic_internal_codec()  ( REG_AIC_FR |= AIC_FR_ICDC )

+#define __aic_external_codec()  ( REG_AIC_FR &= ~AIC_FR_ICDC )

+#define __aic0_internal_codec()  ( REG_AIC0_FR |= AIC_FR_ICDC )

+#define __aic0_external_codec()  ( REG_AIC0_FR &= ~AIC_FR_ICDC )

+

+//

+// Define next ops for AC97 compatible

+//

+

+#define AC97_ACSR	AIC_ACSR

+

+#define __ac97_enable()		__aic_enable(); __aic_select_ac97()

+#define __ac97_disable()	__aic_disable()

+#define __ac97_reset()		__aic_reset()

+

+#define __ac97_set_transmit_trigger(n)	__aic_set_transmit_trigger(n)

+#define __ac97_set_receive_trigger(n)	__aic_set_receive_trigger(n)

+

+#define __ac97_enable_record()		__aic_enable_record()

+#define __ac97_disable_record()		__aic_disable_record()

+#define __ac97_enable_replay()		__aic_enable_replay()

+#define __ac97_disable_replay()		__aic_disable_replay()

+#define __ac97_enable_loopback()	__aic_enable_loopback()

+#define __ac97_disable_loopback()	__aic_disable_loopback()

+

+#define __ac97_enable_transmit_dma()	__aic_enable_transmit_dma()

+#define __ac97_disable_transmit_dma()	__aic_disable_transmit_dma()

+#define __ac97_enable_receive_dma()	__aic_enable_receive_dma()

+#define __ac97_disable_receive_dma()	__aic_disable_receive_dma()

+

+#define __ac97_transmit_request()	__aic_transmit_request()

+#define __ac97_receive_request()	__aic_receive_request()

+#define __ac97_transmit_underrun()	__aic_transmit_underrun()

+#define __ac97_receive_overrun()	__aic_receive_overrun()

+

+#define __ac97_clear_errors()		__aic_clear_errors()

+

+#define __ac97_get_transmit_resident()	__aic_get_transmit_resident()

+#define __ac97_get_receive_count()	__aic_get_receive_count()

+

+#define __ac97_enable_transmit_intr()	__aic_enable_transmit_intr()

+#define __ac97_disable_transmit_intr()	__aic_disable_transmit_intr()

+#define __ac97_enable_receive_intr()	__aic_enable_receive_intr()

+#define __ac97_disable_receive_intr()	__aic_disable_receive_intr()

+

+#define __ac97_write_tfifo(v)		__aic_write_tfifo(v)

+#define __ac97_read_rfifo()		__aic_read_rfifo()

+

+//

+// Define next ops for I2S compatible

+//

+

+#define I2S_ACSR	AIC_I2SSR

+

+#define __i2s_enable()		 __aic_enable(); __aic_select_i2s()

+#define __i2s_disable()		__aic_disable()

+#define __i2s_reset()		__aic_reset()

+

+#define __i2s_set_transmit_trigger(n)	__aic_set_transmit_trigger(n)

+#define __i2s_set_receive_trigger(n)	__aic_set_receive_trigger(n)

+

+#define __i2s_enable_record()		__aic_enable_record()

+#define __i2s_disable_record()		__aic_disable_record()

+#define __i2s_enable_replay()		__aic_enable_replay()

+#define __i2s_disable_replay()		__aic_disable_replay()

+#define __i2s_enable_loopback()		__aic_enable_loopback()

+#define __i2s_disable_loopback()	__aic_disable_loopback()

+

+#define __i2s_enable_transmit_dma()	__aic_enable_transmit_dma()

+#define __i2s_disable_transmit_dma()	__aic_disable_transmit_dma()

+#define __i2s_enable_receive_dma()	__aic_enable_receive_dma()

+#define __i2s_disable_receive_dma()	__aic_disable_receive_dma()

+

+#define __i2s_transmit_request()	__aic_transmit_request()

+#define __i2s_receive_request()		__aic_receive_request()

+#define __i2s_transmit_underrun()	__aic_transmit_underrun()

+#define __i2s_receive_overrun()		__aic_receive_overrun()

+

+#define __i2s_clear_errors()		__aic_clear_errors()

+

+#define __i2s_get_transmit_resident()	__aic_get_transmit_resident()

+#define __i2s_get_receive_count()	__aic_get_receive_count()

+

+#define __i2s_enable_transmit_intr()	__aic_enable_transmit_intr()

+#define __i2s_disable_transmit_intr()	__aic_disable_transmit_intr()

+#define __i2s_enable_receive_intr()	__aic_enable_receive_intr()

+#define __i2s_disable_receive_intr()	__aic_disable_receive_intr()

+

+#define __i2s_write_tfifo(v)		__aic_write_tfifo(v)

+#define __i2s_read_rfifo()		__aic_read_rfifo()

+

+#define __i2s_reset_codec()			\

+ do {						\

+ } while (0)

+

+

+/*************************************************************************

+ * SPDIF INTERFACE in AIC Controller

+ *************************************************************************/

+

+#define __spdif_enable()        ( REG_SPDIF_ENA |= SPDIF_ENA_SPEN )

+#define __spdif_disable()       ( REG_SPDIF_ENA &= ~SPDIF_ENA_SPEN )

+

+#define __spdif_enable_transmit_dma()     ( REG_SPDIF_CTRL |= SPDIF_CTRL_DMAEN )

+#define __spdif_disable_transmit_dma()    ( REG_SPDIF_CTRL &= ~SPDIF_CTRL_DMAEN )

+#define __spdif_enable_dtype()            ( REG_SPDIF_CTRL |= SPDIF_CTRL_DTYPE )

+#define __spdif_disable_dtype()           ( REG_SPDIF_CTRL &= ~SPDIF_CTRL_DTYPE )

+#define __spdif_enable_sign()             ( REG_SPDIF_CTRL |= SPDIF_CTRL_SIGN )

+#define __spdif_disable_sign()            ( REG_SPDIF_CTRL &= ~SPDIF_CTRL_SIGN )

+#define __spdif_enable_invalid()          ( REG_SPDIF_CTRL |= SPDIF_CTRL_INVALID )

+#define __spdif_disable_invalid()         ( REG_SPDIF_CTRL &= ~SPDIF_CTRL_INVALID )

+#define __spdif_enable_reset()            ( REG_SPDIF_CTRL |= SPDIF_CTRL_RST )

+#define __spdif_select_spdif()            ( REG_SPDIF_CTRL |= SPDIF_CTRL_SPDIFI2S )

+#define __spdif_select_i2s()              ( REG_SPDIF_CTRL &= ~SPDIF_CTRL_SPDIFI2S )

+#define __spdif_enable_MTRIGmask()        ( REG_SPDIF_CTRL |= SPDIF_CTRL_MTRIG )

+#define __spdif_disable_MTRIGmask()       ( REG_SPDIF_CTRL &= ~SPDIF_CTRL_MTRIG )

+#define __spdif_enable_MFFURmask()        ( REG_SPDIF_CTRL |= SPDIF_CTRL_MFFUR )

+#define __spdif_disable_MFFURmask()       ( REG_SPDIF_CTRL &= ~SPDIF_CTRL_MFFUR )

+

+#define __spdif_enable_initlvl_high()     ( REG_SPDIF_CFG1 |=  SPDIF_CFG1_INITLVL )

+#define __spdif_enable_initlvl_low()      ( REG_SPDIF_CFG1 &=  ~SPDIF_CFG1_INITLVL )

+#define __spdif_enable_zrovld_invald()    ( REG_SPDIF_CFG1 |=  SPDIF_CFG1_ZROVLD )

+#define __spdif_enable_zrovld_vald()      ( REG_SPDIF_CFG1 &=  ~SPDIF_CFG1_ZROVLD )

+

+/* 0, 1, 2, 3 */

+#define __spdif_set_transmit_trigger(n)			\

+do {							\

+	REG_SPDIF_CFG1 &= ~SPDIF_CFG1_TRIG_MASK;	\

+	REG_SPDIF_CFG1 |= SPDIF_CFG1_TRIG(n);	\

+} while(0)

+

+/* 1 ~ 15 */

+#define __spdif_set_srcnum(n)    			\

+do {							\

+	REG_SPDIF_CFG1 &= ~SPDIF_CFG1_SRCNUM_MASK;	\

+	REG_SPDIF_CFG1 |= ((n) << SPDIF_CFG1_SRCNUM_LSB);	\

+} while(0)

+

+/* 1 ~ 15 */

+#define __spdif_set_ch1num(n)    			\

+do {							\

+	REG_SPDIF_CFG1 &= ~SPDIF_CFG1_CH1NUM_MASK;	\

+	REG_SPDIF_CFG1 |= ((n) << SPDIF_CFG1_CH1NUM_LSB);	\

+} while(0)

+

+/* 1 ~ 15 */

+#define __spdif_set_ch2num(n)    			\

+do {							\

+	REG_SPDIF_CFG1 &= ~SPDIF_CFG1_CH2NUM_MASK;	\

+	REG_SPDIF_CFG1 |= ((n) << SPDIF_CFG1_CH2NUM_LSB);	\

+} while(0)

+

+/* 0x0, 0x2, 0x3, 0xa, 0xe */

+#define __spdif_set_fs(n)				\

+do {							\

+	REG_SPDIF_CFG2 &= ~SPDIF_CFG2_FS_MASK;   	\

+	REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_FS_LSB);	\

+} while(0)

+

+/* 0xd, 0xc, 0x5, 0x1 */

+#define __spdif_set_orgfrq(n)				\

+do {							\

+	REG_SPDIF_CFG2 &= ~SPDIF_CFG2_ORGFRQ_MASK;   	\

+	REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_ORGFRQ_LSB);	\

+} while(0)

+

+/* 0x1, 0x6, 0x2, 0x4, 0x5 */

+#define __spdif_set_samwl(n)				\

+do {							\

+	REG_SPDIF_CFG2 &= ~SPDIF_CFG2_SAMWL_MASK;   	\

+	REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_SAMWL_LSB);	\

+} while(0)

+

+#define __spdif_enable_samwl_24()    ( REG_SPDIF_CFG2 |= SPDIF_CFG2_MAXWL )

+#define __spdif_enable_samwl_20()    ( REG_SPDIF_CFG1 &= ~SPDIF_CFG2_MAXWL )

+

+/* 0x1, 0x1, 0x2, 0x3 */

+#define __spdif_set_clkacu(n)				\

+do {							\

+	REG_SPDIF_CFG2 &= ~SPDIF_CFG2_CLKACU_MASK;   	\

+	REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_CLKACU_LSB);	\

+} while(0)

+

+/* see IEC60958-3 */

+#define __spdif_set_catcode(n)				\

+do {							\

+	REG_SPDIF_CFG2 &= ~SPDIF_CFG2_CATCODE_MASK;   	\

+	REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_CATCODE_LSB);	\

+} while(0)

+

+/* n = 0x0, */

+#define __spdif_set_chmode(n)				\

+do {							\

+	REG_SPDIF_CFG2 &= ~SPDIF_CFG2_CHMD_MASK;   	\

+	REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_CHMD_LSB);	\

+} while(0)

+

+#define __spdif_enable_pre()       ( REG_SPDIF_CFG2 |= SPDIF_CFG2_PRE )

+#define __spdif_disable_pre()      ( REG_SPDIF_CFG2 &= ~SPDIF_CFG2_PRE )

+#define __spdif_enable_copyn()     ( REG_SPDIF_CFG2 |= SPDIF_CFG2_COPYN )

+#define __spdif_disable_copyn()    ( REG_SPDIF_CFG2 &= ~SPDIF_CFG2_COPYN )

+/* audio sample word represents linear PCM samples */

+#define __spdif_enable_audion()    ( REG_SPDIF_CFG2 &= ~SPDIF_CFG2_AUDION )

+/* udio sample word used for other purpose */

+#define __spdif_disable_audion()   ( REG_SPDIF_CFG2 |= SPDIF_CFG2_AUDION )

+#define __spdif_enable_conpro()    ( REG_SPDIF_CFG2 &= ~SPDIF_CFG2_CONPRO )

+#define __spdif_disable_conpro()   ( REG_SPDIF_CFG2 |= SPDIF_CFG2_CONPRO )

+

+/***************************************************************************

+ * ICDC

+ ***************************************************************************/

+#define __i2s_internal_codec()         __aic_internal_codec()

+#define __i2s_external_codec()         __aic_external_codec()

+

+#define __icdc_clk_ready()             ( REG_ICDC_CKCFG & ICDC_CKCFG_CKRDY )

+#define __icdc_sel_adc()               ( REG_ICDC_CKCFG |= ICDC_CKCFG_SELAD )

+#define __icdc_sel_dac()               ( REG_ICDC_CKCFG &= ~ICDC_CKCFG_SELAD )

+

+#define __icdc_set_rgwr()              ( REG_ICDC_RGADW |= ICDC_RGADW_RGWR )

+#define __icdc_clear_rgwr()            ( REG_ICDC_RGADW &= ~ICDC_RGADW_RGWR )

+#define __icdc_rgwr_ready()            ( REG_ICDC_RGADW & ICDC_RGADW_RGWR )

+

+#define __icdc_set_addr(n)				\

+do {          						\

+	REG_ICDC_RGADW &= ~ICDC_RGADW_RGADDR_MASK;	\

+	REG_ICDC_RGADW |= (n) << ICDC_RGADW_RGADDR_LSB;	\

+} while(0)

+

+#define __icdc_set_cmd(n)				\

+do {          						\

+	REG_ICDC_RGADW &= ~ICDC_RGADW_RGDIN_MASK;	\

+	REG_ICDC_RGADW |= (n) << ICDC_RGADW_RGDIN_LSB;	\

+} while(0)

+

+#define __icdc_irq_pending()            ( REG_ICDC_RGDATA & ICDC_RGDATA_IRQ )

+#define __icdc_get_value()              ( REG_ICDC_RGDATA & ICDC_RGDATA_RGDOUT_MASK )

+

+

+

+#endif /* __MIPS_ASSEMBLER */

+

+#endif /* __CHIP_AIC_H__ */

diff --git a/arch/mips/include/asm/mach-jz4770/jz4770aosd.h b/arch/mips/include/asm/mach-jz4770/jz4770aosd.h
new file mode 100644
index 00000000000..b6af248616d
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4770/jz4770aosd.h
@@ -0,0 +1,107 @@
+/*

+ * linux/include/asm-mips/mach-jz4770/jz4770aosd.h

+ *

+ * JZ4770 ALPHA OSD register definition.

+ *

+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

+ */

+

+#ifndef __JZ4770AOSD_H__

+#define __JZ4770AOSD_H__

+

+#define AOSD_BASE        0xB3070000

+

+/*************************************************************************

+ * OSD (On Screen Display)

+ *************************************************************************/

+#define AOSD_ADDR0             (AOSD_BASE + 0x00)

+#define AOSD_ADDR1             (AOSD_BASE + 0x04)

+#define AOSD_ADDR2             (AOSD_BASE + 0x08)

+#define AOSD_ADDR3             (AOSD_BASE + 0x0C)

+#define AOSD_WADDR             (AOSD_BASE + 0x10)

+#define AOSD_ADDRLEN           (AOSD_BASE + 0x14)

+#define AOSD_ALPHA_VALUE       (AOSD_BASE + 0x18)

+#define AOSD_CTRL              (AOSD_BASE + 0x1C)

+#define AOSD_INT               (AOSD_BASE + 0x20)

+#define AOSD_CLK_GATE          (AOSD_BASE + 0x48)

+

+#define REG_AOSD_ADDR0         REG32(AOSD_ADDR0)

+#define REG_AOSD_ADDR1         REG32(AOSD_ADDR1)

+#define REG_AOSD_ADDR2         REG32(AOSD_ADDR2)

+#define REG_AOSD_ADDR3         REG32(AOSD_ADDR3)

+#define REG_AOSD_WADDR         REG32(AOSD_WADDR)

+#define REG_AOSD_ADDRLEN       REG32(AOSD_ADDRLEN)

+#define REG_AOSD_ALPHA_VALUE   REG32(AOSD_ALPHA_VALUE)

+#define REG_AOSD_CTRL          REG32(AOSD_CTRL)

+#define REG_AOSD_INT           REG32(AOSD_INT)

+#define REG_AOSD_CLK_GATE      REG32(AOSD_CLK_GATE)

+

+#define AOSD_CTRL_FRMLV_MASK        (0x3 << 18)

+#define AOSD_CTRL_FRMLV_2        (0x1 << 18)

+#define AOSD_CTRL_FRMLV_3        (0x2 << 18)

+#define AOSD_CTRL_FRMLV_4        (0x3 << 18)

+

+#define AOSD_CTRL_FRM_END        (1 << 17)

+#define AOSD_CTRL_ALPHA_START    (1 << 16)

+#define AOSD_CTRL_INT_MAKS            (1 << 15)

+#define AOSD_CTRL_CHANNEL_LEVEL_BIT    7

+#define AOSD_CTRL_CHANNEL_LEVEL_MASK   (0xff <<  AOSD_CTRL_CHANNEL_LEVEL_BIT)

+#define AOSD_CTRL_ALPHA_MODE_BIT       3

+#define AOSD_CTRL_ALPHA_MODE_MASK      (0xf << AOSD_CTRL_ALPHA_MODE_BIT)

+#define AOSD_CTRL_ALPHA_PIXEL_MODE     0

+#define AOSD_CTRL_ALPHA_FRAME_MODE     1

+

+#define AOSD_CTRL_FORMAT_MODE_BIT     1

+#define AOSD_CTRL_FORMAT_MODE_MASK     (0x3 << 1)

+#define AOSD_CTRL_RGB565_FORMAT_MODE   (0 << AOSD_CTRL_FORMAT_MODE_BIT)

+#define AOSD_CTRL_RGB555_FORMAT_MODE   (1 << AOSD_CTRL_FORMAT_MODE_BIT)

+#define AOSD_CTRL_RGB8888_FORMAT_MODE  (2 << AOSD_CTRL_FORMAT_MODE_BIT)

+

+#define AOSD_ALPHA_ENABLE        (1 << 0)

+

+#define AOSD_INT_COMPRESS_END   (1 << 1)

+#define AOSD_INT_AOSD_END        (1 << 0)

+

+#define AOSD_CLK_GATE_EN         (1 << 0)

+

+#define __osd_enable_alpha() 	(REG_AOSD_CTRL |= AOSD_ALPHA_ENABLE)

+#define __osd_alpha_start()     (REG_AOSD_CTRL |= AOSD_CTRL_ALPHA_START) 

+/*************************************************************************

+ * COMPRESS

+ *************************************************************************/

+

+#define COMPRESS_SCR_ADDR      (AOSD_BASE + 0x00)

+#define COMPRESS_DES_ADDR      (AOSD_BASE + 0x10)

+#define COMPRESS_OFFSIZE       (AOSD_BASE + 0x34)

+#define COMPRESS_FRAME_SIZE       (AOSD_BASE + 0x38)

+#define COMPRESS_CTRL       (AOSD_BASE + 0x3C)

+#define COMPRESS_RATIO      (AOSD_BASE + 0x40)

+#define COMPRESS_OFFSET     (AOSD_BASE + 0x44)

+#define COMPRESS_RESULT     (AOSD_BASE + 0x4C)

+ 

+#define REG_COMPRESS_SCR_ADDR      REG32(COMPRESS_SCR_ADDR)

+#define REG_COMPRESS_DES_ADDR      REG32(COMPRESS_DES_ADDR)

+#define REG_COMPRESS_OFFSIZE       REG32(COMPRESS_OFFSIZE)

+#define REG_COMPRESS_FRAME_SIZE       REG32(COMPRESS_FRAME_SIZE)

+#define REG_COMPRESS_CTRL       REG32(COMPRESS_CTRL)

+#define REG_COMPRESS_RATIO      REG32(COMPRESS_RATIO)

+#define REG_COMPRESS_OFFSET     REG32(COMPRESS_OFFSET)

+#define REG_COMPRESS_RESULT     REG32(COMPRESS_RESULT)

+

+#define COMPRESS_CTRL_WITHOUT_ALPHA     (1 << 4)

+#define COMPRESS_CTRL_WITH_ALPHA     (0 << 4)

+#define COMPRESS_CTRL_COMP_START   (1 << 3)

+#define COMPRESS_CTRL_COMP_END     (1 << 2)

+#define COMPRESS_CTRL_INT_MASK     (1 << 1)

+#define COMPRESS_CTRL_COMP_ENABLE  (1 << 0)

+

+#define COMPRESS_RATIO_FRM_BYPASS   (1 << 31)

+#define COMPRESS_BYPASS_ROW         (1 << 12)

+#define COMPRESS_ROW_QUARTER        (1 << 0)

+

+#define __compress_enable()       (REG_COMPRESS_CTRL |= COMPRESS_INT_AOSD_END)      

+#define __compress_start()        (REG_COMPRESS_CTRL |= COMPRESS_CTRL_COMP_START)      

+#define __compress_with_alpha()   (REG_COMPRESS_CTRL |= COMPRESS_CTRL_ALPHA_EN)      

+

+#endif /* __JZ4770AOSD_H__ */

+

diff --git a/arch/mips/include/asm/mach-jz4770/jz4770bch.h b/arch/mips/include/asm/mach-jz4770/jz4770bch.h
new file mode 100644
index 00000000000..8350509f11e
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4770/jz4770bch.h
@@ -0,0 +1,216 @@
+/*

+ * linux/include/asm-mips/mach-jz4770/jz4770bch.h

+ *

+ * JZ4770 bch register definition.

+ *

+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

+ */

+

+#ifndef __JZ4770BCH_H__

+#define __JZ4770BCH_H__

+

+

+#define BCH_BASE	0xB34D0000

+

+/*************************************************************************

+ * BCH

+ *************************************************************************/

+#define	BCH_CR         	(BCH_BASE + 0x00) /* BCH Control register */

+#define	BCH_CRS       	(BCH_BASE + 0x04) /* BCH Control Set register */

+#define	BCH_CRC       	(BCH_BASE + 0x08) /* BCH Control Clear register */

+#define	BCH_CNT    	(BCH_BASE + 0x0C) /* BCH ENC/DEC Count register */

+#define	BCH_DR     	(BCH_BASE + 0x10) /* BCH data register */

+#define	BCH_PAR0    	(BCH_BASE + 0x14) /* BCH Parity 0 register */

+#define	BCH_PAR1    	(BCH_BASE + 0x18) /* BCH Parity 1 register */

+#define	BCH_PAR2    	(BCH_BASE + 0x1C) /* BCH Parity 2 register */

+#define	BCH_PAR3    	(BCH_BASE + 0x20) /* BCH Parity 3 register */

+#define	BCH_PAR4    	(BCH_BASE + 0x24) /* BCH Parity 4 register */

+#define	BCH_PAR5    	(BCH_BASE + 0x28) /* BCH Parity 5 register */

+#define	BCH_PAR6    	(BCH_BASE + 0x2C) /* BCH Parity 6 register */

+#define	BCH_PAR7    	(BCH_BASE + 0x30) /* BCH Parity 7 register */

+#define	BCH_PAR8    	(BCH_BASE + 0x34) /* BCH Parity 8 register */

+#define	BCH_PAR9    	(BCH_BASE + 0x38) /* BCH Parity 9 register */

+#define	BCH_ERR0        (BCH_BASE + 0x3C) /* BCH Error Report 0 register */

+#define	BCH_ERR1        (BCH_BASE + 0x40) /* BCH Error Report 1 register */

+#define	BCH_ERR2        (BCH_BASE + 0x44) /* BCH Error Report 2 register */

+#define	BCH_ERR3        (BCH_BASE + 0x48) /* BCH Error Report 3 register */

+#define	BCH_ERR4        (BCH_BASE + 0x4C) /* BCH Error Report 4 register */

+#define	BCH_ERR5        (BCH_BASE + 0x50) /* BCH Error Report 5 register */

+#define	BCH_ERR6        (BCH_BASE + 0x54) /* BCH Error Report 6 register */

+#define	BCH_ERR7        (BCH_BASE + 0x58) /* BCH Error Report 7 register */

+#define	BCH_ERR8        (BCH_BASE + 0x5C) /* BCH Error Report 8 register */

+#define	BCH_ERR9        (BCH_BASE + 0x60) /* BCH Error Report 9 register */

+#define	BCH_ERR10       (BCH_BASE + 0x64) /* BCH Error Report 10 register */

+#define	BCH_ERR11       (BCH_BASE + 0x68) /* BCH Error Report 11 register */

+#define	BCH_INTS    	(BCH_BASE + 0x6C) /* BCH Interrupt Status register */

+#define	BCH_INTE	(BCH_BASE + 0x70) /* BCH Interrupt Enable register */

+#define	BCH_INTES       (BCH_BASE + 0x74) /* BCH Interrupt Set register */

+#define	BCH_INTEC	(BCH_BASE + 0x78) /* BCH Interrupt Clear register */

+

+#define	REG_BCH_CR      REG32(BCH_CR)

+#define	REG_BCH_CRS     REG32(BCH_CRS)

+#define	REG_BCH_CRC     REG32(BCH_CRC)

+#define	REG_BCH_CNT     REG32(BCH_CNT)

+#define	REG_BCH_DR      REG8(BCH_DR)

+#define	REG_BCH_PAR0    REG32(BCH_PAR0)

+#define	REG_BCH_PAR1    REG32(BCH_PAR1)

+#define	REG_BCH_PAR2    REG32(BCH_PAR2)

+#define	REG_BCH_PAR3    REG32(BCH_PAR3)

+#define	REG_BCH_PAR4    REG32(BCH_PAR4)

+#define	REG_BCH_PAR5    REG32(BCH_PAR5)

+#define	REG_BCH_PAR6    REG32(BCH_PAR6)

+#define	REG_BCH_PAR7    REG32(BCH_PAR7)

+#define	REG_BCH_PAR8    REG32(BCH_PAR8)

+#define	REG_BCH_PAR9    REG32(BCH_PAR9)

+#define	REG_BCH_ERR0    REG32(BCH_ERR0)

+#define	REG_BCH_ERR1    REG32(BCH_ERR1)

+#define	REG_BCH_ERR2    REG32(BCH_ERR2)

+#define	REG_BCH_ERR3    REG32(BCH_ERR3)

+#define	REG_BCH_ERR4    REG32(BCH_ERR4)

+#define	REG_BCH_ERR5    REG32(BCH_ERR5)

+#define	REG_BCH_ERR6    REG32(BCH_ERR6)

+#define	REG_BCH_ERR7    REG32(BCH_ERR7)

+#define	REG_BCH_ERR8    REG32(BCH_ERR8)

+#define	REG_BCH_ERR9    REG32(BCH_ERR9)

+#define	REG_BCH_ERR10   REG32(BCH_ERR10)

+#define	REG_BCH_ERR11   REG32(BCH_ERR11)

+#define	REG_BCH_INTS    REG32(BCH_INTS)

+#define	REG_BCH_INTE    REG32(BCH_INTE)

+#define	REG_BCH_INTEC   REG32(BCH_INTEC)

+#define	REG_BCH_INTES   REG32(BCH_INTES)

+

+/* BCH Control Register*/

+#define	BCH_CR_DMAE              (1 << 7)  /* BCH DMA Enable */

+#define	BCH_CR_BSEL_BIT          3

+#define	BCH_CR_BSEL_MASK         (0x3 << BCH_CR_BSEL_BIT)

+  #define BCH_CR_BSEL_4          (0x0 << BCH_CR_BSEL_BIT)  /* 4 Bit BCH Select */

+  #define BCH_CR_BSEL_8          (0x1 << BCH_CR_BSEL_BIT)  /* 8 Bit BCH Select */

+  #define BCH_CR_BSEL_12         (0x2 << BCH_CR_BSEL_BIT)  /* 12 Bit BCH Select */

+  #define BCH_CR_BSEL_16         (0x3 << BCH_CR_BSEL_BIT)  /* 16 Bit BCH Select */

+  #define BCH_CR_BSEL_20         (0x4 << BCH_CR_BSEL_BIT)  /* 20 Bit BCH Select */

+  #define BCH_CR_BSEL_24         (0x5 << BCH_CR_BSEL_BIT)  /* 24 Bit BCH Select */

+#define	BCH_CR_ENCE              (1 << 2)  /* BCH Encoding Select */

+#define	BCH_CR_DECE              (0 << 2)  /* BCH Decoding Select */

+#define	BCH_CR_BRST              (1 << 1)  /* BCH Reset */

+#define	BCH_CR_BCHE              (1 << 0)  /* BCH Enable */

+

+/* BCH Interrupt Status Register */

+#define	BCH_INTS_ERRC_BIT        27

+#define	BCH_INTS_ERRC_MASK       (0x1f << BCH_INTS_ERRC_BIT)

+#define	BCH_INTS_ALL0            (1 << 5)

+#define	BCH_INTS_ALLf            (1 << 4)

+#define	BCH_INTS_DECF            (1 << 3)

+#define	BCH_INTS_ENCF            (1 << 2)

+#define	BCH_INTS_UNCOR           (1 << 1)

+#define	BCH_INTS_ERR             (1 << 0)

+

+/* BCH ENC/DEC Count Register */

+#define BCH_CNT_DEC_BIT          16

+#define BCH_CNT_DEC_MASK         (0x7ff << BCH_CNT_DEC_BIT)

+#define BCH_CNT_ENC_BIT          0

+#define BCH_CNT_ENC_MASK         (0x7ff << BCH_CNT_ENC_BIT)

+

+/* BCH Error Report Register */

+#define BCH_ERR_INDEX_ODD_BIT    16

+#define BCH_ERR_INDEX_ODD_MASK   (0x1fff << BCH_ERR_INDEX_ODD_BIT)

+#define BCH_ERR_INDEX_EVEN_BIT   0

+#define BCH_ERR_INDEX_EVEN_MASK  (0x1fff << BCH_ERR_INDEX_EVEN_BIT)

+#define BCH_ERR_INDEX_MASK	 0x1fff

+

+#ifndef __MIPS_ASSEMBLER

+

+/*************************************************************************

+ * BCH

+ *************************************************************************/

+#define __ecc_encoding_4bit()						\

+do {									\

+	REG_BCH_CRS = BCH_CR_BSEL_4 | BCH_CR_ENCE | BCH_CR_BCHE;	\

+	REG_BCH_CRC = ~(BCH_CR_BSEL_4 | BCH_CR_ENCE | BCH_CR_BCHE);	\

+	REG_BCH_CRS = BCH_CR_BRST;					\

+} while(0)

+#define __ecc_decoding_4bit()						\

+do {									\

+	REG_BCH_CRS = BCH_CR_BSEL_4 | BCH_CR_DECE | BCH_CR_BCHE;	\

+	REG_BCH_CRC = ~(BCH_CR_BSEL_4 | BCH_CR_DECE | BCH_CR_BCHE);	\

+	REG_BCH_CRS = BCH_CR_BRST;					\

+} while(0)

+#define __ecc_encoding_8bit()                                           \

+do {				   		                        \

+	REG_BCH_CRS = BCH_CR_BSEL_8 | BCH_CR_ENCE | BCH_CR_BCHE;	\

+	REG_BCH_CRC = ~(BCH_CR_BSEL_8 | BCH_CR_ENCE | BCH_CR_BCHE);	\

+	REG_BCH_CRS = BCH_CR_BRST;					\

+} while(0)

+#define __ecc_decoding_8bit()						\

+do {									\

+	REG_BCH_CRS = BCH_CR_BSEL_8 | BCH_CR_DECE | BCH_CR_BCHE;	\

+	REG_BCH_CRC = ~(BCH_CR_BSEL_8 | BCH_CR_DECE | BCH_CR_BCHE);	\

+	REG_BCH_CRS = BCH_CR_BRST;					\

+} while(0)

+#define __ecc_encoding_12bit()						\

+do {									\

+	REG_BCH_CRS = BCH_CR_BSEL_12 | BCH_CR_ENCE | BCH_CR_BCHE;	\

+	REG_BCH_CRC = ~(BCH_CR_BSEL_12 | BCH_CR_ENCE | BCH_CR_BCHE);	\

+	REG_BCH_CRS = BCH_CR_BRST;					\

+} while(0)

+#define __ecc_decoding_12bit()						\

+do {									\

+	REG_BCH_CRS = BCH_CR_BSEL_12 | BCH_CR_DECE | BCH_CR_BCHE;	\

+	REG_BCH_CRC = ~(BCH_CR_BSEL_12 | BCH_CR_DECE | BCH_CR_BCHE);	\

+	REG_BCH_CRS = BCH_CR_BRST;					\

+} while(0)

+#define __ecc_encoding_16bit()						\

+do {									\

+	REG_BCH_CRS = BCH_CR_BSEL_16 | BCH_CR_ENCE | BCH_CR_BCHE;	\

+	REG_BCH_CRC = ~(BCH_CR_BSEL_16 | BCH_CR_ENCE | BCH_CR_BCHE);	\

+	REG_BCH_CRS = BCH_CR_BRST;					\

+} while(0)

+#define __ecc_decoding_16bit()						\

+do {									\

+	REG_BCH_CRS = BCH_CR_BSEL_16 | BCH_CR_DECE | BCH_CR_BCHE;	\

+	REG_BCH_CRC = ~(BCH_CR_BSEL_16 | BCH_CR_DECE | BCH_CR_BCHE);	\

+	REG_BCH_CRS = BCH_CR_BRST;					\

+} while(0)

+#define __ecc_encoding_20bit()						\

+do {									\

+	REG_BCH_CRS = BCH_CR_BSEL_20 | BCH_CR_ENCE | BCH_CR_BCHE;	\

+	REG_BCH_CRC = ~(BCH_CR_BSEL_20 | BCH_CR_ENCE | BCH_CR_BCHE);	\

+	REG_BCH_CRS = BCH_CR_BRST;					\

+} while(0)

+#define __ecc_decoding_20bit()						\

+do {									\

+	REG_BCH_CRS = BCH_CR_BSEL_20 | BCH_CR_DECE | BCH_CR_BCHE;	\

+	REG_BCH_CRC = ~(BCH_CR_BSEL_20 | BCH_CR_DECE | BCH_CR_BCHE);	\

+	REG_BCH_CRS = BCH_CR_BRST;					\

+} while(0)

+#define __ecc_encoding_24bit()						\

+do {									\

+	REG_BCH_CRS = BCH_CR_BSEL_24 | BCH_CR_ENCE | BCH_CR_BCHE;	\

+	REG_BCH_CRC = ~(BCH_CR_BSEL_24 | BCH_CR_ENCE | BCH_CR_BCHE);	\

+	REG_BCH_CRS = BCH_CR_BRST;					\

+} while(0)

+#define __ecc_decoding_24bit()						\

+do {									\

+	REG_BCH_CRS = BCH_CR_BSEL_24 | BCH_CR_DECE | BCH_CR_BCHE;	\

+	REG_BCH_CRC = ~(BCH_CR_BSEL_24 | BCH_CR_DECE | BCH_CR_BCHE);	\

+	REG_BCH_CRS = BCH_CR_BRST;					\

+} while(0)

+#define __ecc_dma_enable()        ( REG_BCH_CRS = BCH_CR_DMAE )

+#define __ecc_dma_disable()       ( REG_BCH_CRC = BCH_CR_DMAE )

+#define __ecc_disable()           ( REG_BCH_CRC = BCH_CR_BCHE )

+#define __ecc_encode_sync()       while (!(REG_BCH_INTS & BCH_INTS_ENCF))

+#define __ecc_decode_sync()       while (!(REG_BCH_INTS & BCH_INTS_DECF))

+

+#define __ecc_cnt_dec(n)                                             \

+do {						               	     \

+        REG_BCH_CNT = (n) << BCH_CNT_DEC_BIT;                        \

+} while(0)

+

+#define __ecc_cnt_enc(n)                                             \

+do {                                                                 \

+        REG_BCH_CNT = (n) << BCH_CNT_ENC_BIT;                        \

+} while(0)

+

+#endif /* __MIPS_ASSEMBLER */

+

+#endif /* __JZ4770BCH_H__ */

+

diff --git a/arch/mips/include/asm/mach-jz4770/jz4770bdma.h b/arch/mips/include/asm/mach-jz4770/jz4770bdma.h
new file mode 100644
index 00000000000..d59ba4a63fc
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4770/jz4770bdma.h
@@ -0,0 +1,322 @@
+/*

+ * linux/include/asm-mips/mach-jz4770/jz4770bdma.h

+ *

+ * JZ4770 BDMA register definition.

+ *

+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

+ */

+

+#ifndef __JZ4770BDMA_H__

+#define __JZ4770BDMA_H__

+

+

+#define BDMAC_BASE  0xB3450000

+

+

+/*************************************************************************

+ * BDMAC (BCH & NAND DMA Controller)

+ *************************************************************************/

+

+/* n is the DMA channel index (0 - 2) */

+#define BDMAC_DSAR(n)		(BDMAC_BASE + (0x00 + (n) * 0x20)) /* DMA source address */

+#define BDMAC_DTAR(n)  		(BDMAC_BASE + (0x04 + (n) * 0x20)) /* DMA target address */

+#define BDMAC_DTCR(n)  		(BDMAC_BASE + (0x08 + (n) * 0x20)) /* DMA transfer count */

+#define BDMAC_DRSR(n)  		(BDMAC_BASE + (0x0c + (n) * 0x20)) /* DMA request source */

+#define BDMAC_DCCSR(n) 		(BDMAC_BASE + (0x10 + (n) * 0x20)) /* DMA control/status */

+#define BDMAC_DCMD(n)  		(BDMAC_BASE + (0x14 + (n) * 0x20)) /* DMA command */

+#define BDMAC_DDA(n)   		(BDMAC_BASE + (0x18 + (n) * 0x20)) /* DMA descriptor address */

+#define BDMAC_DSD(n)   		(BDMAC_BASE + (0x1c + (n) * 0x20)) /* DMA Stride Address */

+#define BDMAC_DNT(n)  		(BDMAC_BASE + (0xc0 + (n) * 0x04)) /* NAND Detect Timer */

+

+#define BDMAC_DMACR		(BDMAC_BASE + 0x0300) 	/* DMA control register */

+#define BDMAC_DMAIPR		(BDMAC_BASE + 0x0304) 	/* DMA interrupt pending */

+#define BDMAC_DMADBR		(BDMAC_BASE + 0x0308) 	/* DMA doorbell */

+#define BDMAC_DMADBSR		(BDMAC_BASE + 0x030C) 	/* DMA doorbell set */

+#define BDMAC_DMACKE  		(BDMAC_BASE + 0x0310)

+#define BDMAC_DMACKES  		(BDMAC_BASE + 0x0314)

+#define BDMAC_DMACKEC  		(BDMAC_BASE + 0x0318)

+

+#define REG_BDMAC_DSAR(n)	REG32(BDMAC_DSAR((n)))

+#define REG_BDMAC_DTAR(n)	REG32(BDMAC_DTAR((n)))

+#define REG_BDMAC_DTCR(n)	REG32(BDMAC_DTCR((n)))

+#define REG_BDMAC_DRSR(n)	REG32(BDMAC_DRSR((n)))

+#define REG_BDMAC_DCCSR(n)	REG32(BDMAC_DCCSR((n)))

+#define REG_BDMAC_DCMD(n)	REG32(BDMAC_DCMD((n)))

+#define REG_BDMAC_DDA(n)	REG32(BDMAC_DDA((n)))

+#define REG_BDMAC_DSD(n)    REG32(BDMAC_DSD(n))

+#define REG_BDMAC_DNT(n)	REG32(BDMAC_DNT(n))

+

+#define REG_BDMAC_DMACR		REG32(BDMAC_DMACR)

+#define REG_BDMAC_DMAIPR	REG32(BDMAC_DMAIPR)

+#define REG_BDMAC_DMADBR	REG32(BDMAC_DMADBR)

+#define REG_BDMAC_DMADBSR	REG32(BDMAC_DMADBSR)

+#define REG_BDMAC_DMACKE    REG32(BDMAC_DMACKE)

+#define REG_BDMAC_DMACKES    REG32(BDMAC_DMACKES)

+#define REG_BDMAC_DMACKEC    REG32(BDMAC_DMACKEC)

+

+//BDMA nand detect timer register

+#define BDMAC_DNTR_DNTE          (1 << 15)  /* Nand request 0 detect timer enable */

+#define BDMAC_DNTR_DNT(n)        ((n) << 0) /* Nand request 0 detect timer value */

+#define BDMAC_DNTR_DNTE1          (1 << 31)  /* Nand request 1 detect timer enable */

+#define BDMAC_DNTR_DNT1(n)        ((n) << 23) /* Nand request 1 detect timer value */

+

+

+// BDMA request source register

+#define BDMAC_DRSR_RS_BIT	0

+#define BDMAC_DRSR_RS_MASK	(0x3f << DMAC_DRSR_RS_BIT)

+#define BDMAC_DRSR_RS_BCH_ENC	(2 << DMAC_DRSR_RS_BIT)

+#define BDMAC_DRSR_RS_BCH_DEC	(3 << DMAC_DRSR_RS_BIT)

+#define BDMAC_DRSR_RS_NAND0	(6 << DMAC_DRSR_RS_BIT)

+#define BDMAC_DRSR_RS_NAND1	(7 << DMAC_DRSR_RS_BIT)

+#define BDMAC_DRSR_RS_AUTO	(8 << DMAC_DRSR_RS_BIT)

+#define BDMAC_DRSR_RS_EXT	(12 << DMAC_DRSR_RS_BIT)

+

+// BDMA channel control/status register

+#define BDMAC_DCCSR_NDES	(1 << 31) /* descriptor (0) or not (1) ? */

+#define BDMAC_DCCSR_DES8    	(1 << 30) /* Descriptor 8 Word */

+#define BDMAC_DCCSR_DES4    	(0 << 30) /* Descriptor 4 Word */

+#define BDMAC_DCCSR_LASTMD0    	(0 << 28) /* BCH Decoding last mode 0, there's one descriptor for decoding blcok*/

+#define BDMAC_DCCSR_LASTMD1    	(1 << 28) /* BCH Decoding last mode 1, there's two descriptor for decoding blcok*/

+#define BDMAC_DCCSR_LASTMD2    	(2 << 28) /* BCH Decoding last mode 2, there's three descriptor for decoding blcok*/

+#define BDMAC_DCCSR_FRBS(n)	((n) << 24)

+#define BDMAC_DCCSR_CDOA_BIT	16        /* copy of DMA offset address */

+#define BDMAC_DCCSR_CDOA_MASK	(0xff << BDMACC_DCCSR_CDOA_BIT)

+#define BDMAC_DCCSR_BERR	(0x1f << 7)  /* BCH error within this transfer, Only for channel 0 */

+#define BDMAC_DCCSR_BUERR       (1 << 5)  /* BCH uncorrectable error, only for channel 0 */

+#define BDMAC_DCCSR_NSERR       (1 << 5)  /* status error, only for channel 1 */

+#define BDMAC_DCCSR_AR		(1 << 4)  /* address error */

+#define BDMAC_DCCSR_TT		(1 << 3)  /* transfer terminated */

+#define BDMAC_DCCSR_HLT		(1 << 2)  /* DMA halted */

+#define BDMAC_DCCSR_BAC		(1 << 1)  /* BCH auto correction */

+#define BDMAC_DCCSR_EN		(1 << 0)  /* channel enable bit */

+

+// BDMA channel command register

+#define BDMAC_DCMD_EACKS_LOW  	(1 << 31) /* External DACK Output Level Select, active low */

+#define BDMAC_DCMD_EACKS_HIGH  	(0 << 31) /* External DACK Output Level Select, active high */

+#define BDMAC_DCMD_EACKM_WRITE 	(1 << 30) /* External DACK Output Mode Select, output in write cycle */

+#define BDMAC_DCMD_EACKM_READ 	(0 << 30) /* External DACK Output Mode Select, output in read cycle */

+#define BDMAC_DCMD_ERDM_BIT	28        /* External DREQ Detection Mode Select */

+  #define BDMAC_DCMD_ERDM_MASK	(0x03 << BDMAC_DCMD_ERDM_BIT)

+  #define BDMAC_DCMD_ERDM_LOW	(0 << BDMAC_DCMD_ERDM_BIT)

+  #define BDMAC_DCMD_ERDM_FALL	(1 << BDMAC_DCMD_ERDM_BIT)

+  #define BDMAC_DCMD_ERDM_HIGH	(2 << BDMAC_DCMD_ERDM_BIT)

+  #define BDMAC_DCMD_ERDM_RISE	(3 << BDMAC_DCMD_ERDM_BIT)

+#define BDMAC_DCMD_BLAST	(1 << 25) /* BCH last */

+#define BDMAC_DCMD_SAI		(1 << 23) /* source address increment */

+#define BDMAC_DCMD_DAI		(1 << 22) /* dest address increment */

+#define BDMAC_DCMD_SWDH_BIT	14  /* source port width */

+  #define BDMAC_DCMD_SWDH_MASK	(0x03 << BDMAC_DCMD_SWDH_BIT)

+  #define BDMAC_DCMD_SWDH_32	(0 << BDMAC_DCMD_SWDH_BIT)

+  #define BDMAC_DCMD_SWDH_8	(1 << BDMAC_DCMD_SWDH_BIT)

+  #define BDMAC_DCMD_SWDH_16	(2 << BDMAC_DCMD_SWDH_BIT)

+#define BDMAC_DCMD_DWDH_BIT	12  /* dest port width */

+  #define BDMAC_DCMD_DWDH_MASK	(0x03 << BDMAC_DCMD_DWDH_BIT)

+  #define BDMAC_DCMD_DWDH_32	(0 << BDMAC_DCMD_DWDH_BIT)

+  #define BDMAC_DCMD_DWDH_8	(1 << BDMAC_DCMD_DWDH_BIT)

+  #define BDMAC_DCMD_DWDH_16	(2 << BDMAC_DCMD_DWDH_BIT)

+#define BDMAC_DCMD_DS_BIT	8  /* transfer data size of a data unit */

+  #define BDMAC_DCMD_DS_MASK	(0x07 << BDMAC_DCMD_DS_BIT)

+  #define BDMAC_DCMD_DS_32BIT	(0 << BDMAC_DCMD_DS_BIT)

+  #define BDMAC_DCMD_DS_8BIT	(1 << BDMAC_DCMD_DS_BIT)

+  #define BDMAC_DCMD_DS_16BIT	(2 << BDMAC_DCMD_DS_BIT)

+  #define BDMAC_DCMD_DS_16BYTE	(3 << BDMAC_DCMD_DS_BIT)

+  #define BDMAC_DCMD_DS_32BYTE	(4 << BDMAC_DCMD_DS_BIT)

+  #define BDMAC_DCMD_DS_64BYTE	(5 << BDMAC_DCMD_DS_BIT)

+#define BDMAC_DCMD_NRD   	(1 << 7)  /* NAND direct read */

+#define BDMAC_DCMD_NWR   	(1 << 6)  /* NAND direct write */

+#define BDMAC_DCMD_NAC   	(1 << 5)  /* NAND AL/CL enable */

+#define BDMAC_DCMD_NSTA		(1 << 4)  /* Nand Status Transfer Enable */

+#define BDMAC_DCMD_STDE   	(1 << 2)  /* Stride Disable/Enable */

+#define BDMAC_DCMD_TIE		(1 << 1)  /* DMA transfer interrupt enable */

+#define BDMAC_DCMD_LINK		(1 << 0)  /* descriptor link enable */

+

+// BDMA descriptor address register

+#define BDMAC_DDA_BASE_BIT	12  /* descriptor base address */

+  #define BDMAC_DDA_BASE_MASK	(0x0fffff << BDMAC_DDA_BASE_BIT)

+#define BDMAC_DDA_OFFSET_BIT	4   /* descriptor offset address */

+  #define BDMAC_DDA_OFFSET_MASK	(0x0ff << BDMAC_DDA_OFFSET_BIT)

+

+// BDMA stride address register

+#define BDMAC_DSD_TSD_BIT	16	/* target stride address */

+  #define BDMAC_DSD_TSD_MASK	(0xffff << BDMAC_DSD_TSD_BIT)

+#define BDMAC_DSD_SSD_BIT	0	/* source stride address */

+  #define BDMAC_DSD_SSD_MASK	(0xffff << BDMAC_DSD_SSD_BIT)

+

+// BDMA NAND Detect timer register

+#define BDMAC_NDTCTIMER_EN	(1 << 15)  /* enable detect timer */

+#define BDMAC_TAILCNT_BIT	16

+

+// BDMA control register

+#define BDMAC_DMACR_PR_BIT	8	/* channel priority mode */

+  #define BDMAC_DMACR_PR_MASK	(0x03 << DMAC_DMACR_PR_BIT)

+  #define BDMAC_DMACR_PR_01_2	(0 << BDMAC_DMACR_PR_BIT)

+  #define BDMAC_DMACR_PR_12_0	(1 << BDMAC_DMACR_PR_BIT)

+  #define BDMAC_DMACR_PR_20_1	(2 << BDMAC_DMACR_PR_BIT)

+  #define BDMAC_DMACR_PR_012	(3 << BDMAC_DMACR_PR_BIT)

+#define BDMAC_DMACR_HLT		(1 << 3)  /* DMA halt flag */

+#define BDMAC_DMACR_AR		(1 << 2)  /* address error flag */

+#define BDMAC_DMACR_DMAE	(1 << 0)  /* DMA enable bit */

+

+// BDMA interrupt pending register

+#define BDMAC_DMAIPR_CIRQ2	(1 << 2)  /* irq pending status for channel 2 */

+#define BDMAC_DMAIPR_CIRQ1	(1 << 1)  /* irq pending status for channel 1 */

+#define BDMAC_DMAIPR_CIRQ0	(1 << 0)  /* irq pending status for channel 0 */

+

+// BDMA doorbell register

+#define BDMAC_DMADBR_DB2	(1 << 2)  /* doorbell for channel 2 */

+#define BDMAC_DMADBR_DB1	(1 << 1)  /* doorbell for channel 1 */

+#define BDMAC_DMADBR_DB0	(1 << 0)  /* doorbell for channel 0 */

+

+// BDMA doorbell set register

+#define BDMAC_DMADBSR_DBS2	(1 << 2)  /* enable doorbell for channel 2 */

+#define BDMAC_DMADBSR_DBS1	(1 << 1)  /* enable doorbell for channel 1 */

+#define BDMAC_DMADBSR_DBS0	(1 << 0)  /* enable doorbell for channel 0 */

+

+

+#ifndef __MIPS_ASSEMBLER

+

+

+/***************************************************************************

+ * BCH & NAND DMAC

+ ***************************************************************************/

+

+/* n is the DMA channel index (0 - 2) */

+

+#define __bdmac_test_halt_error ( REG_BDMAC_DMACR & BDMAC_DMACR_HLT )

+#define __bdmac_test_addr_error ( REG_BDMAC_DMACR & BDMAC_DMACR_AR )

+

+#define __bdmac_channel_enable_clk(n)           \

+	REG_BDMAC_DMACKE |= 1 << (n);

+

+#define __bdmac_enable_descriptor(n) \

+  ( REG_BDMAC_DCCSR((n)) &= ~BDMAC_DCCSR_NDES )

+#define __bdmac_disable_descriptor(n) \

+  ( REG_BDMAC_DCCSR((n)) |= BDMAC_DCCSR_NDES )

+

+#define __bdmac_enable_channel(n)                 \

+do {                                             \

+	REG_BDMAC_DCCSR((n)) |= BDMAC_DCCSR_EN;    \

+} while (0)

+#define __bdmac_disable_channel(n)                \

+do {                                             \

+	REG_BDMAC_DCCSR((n)) &= ~BDMAC_DCCSR_EN;   \

+} while (0)

+

+#define __bdmac_channel_enable_irq(n) \

+  ( REG_BDMAC_DCMD((n)) |= BDMAC_DCMD_TIE )

+#define __bdmac_channel_disable_irq(n) \

+  ( REG_BDMAC_DCMD((n)) &= ~BDMAC_DCMD_TIE )

+

+#define __bdmac_channel_transmit_halt_detected(n) \

+  (  REG_BDMAC_DCCSR((n)) & BDMAC_DCCSR_HLT )

+#define __bdmac_channel_transmit_end_detected(n) \

+  (  REG_BDMAC_DCCSR((n)) & BDMAC_DCCSR_TT )

+/* Nand ops status error, only for channel 1 */

+#define __bdmac_channel_status_error_detected() \

+  (  REG_BDMAC_DCCSR(1) & BDMAC_DCCSR_NSERR )

+#define __bdmac_channel_address_error_detected(n)	\

+  (  REG_BDMAC_DCCSR((n)) & BDMAC_DCCSR_AR )

+#define __bdmac_channel_count_terminated_detected(n) \

+  (  REG_BDMAC_DCCSR((n)) & BDMAC_DCCSR_CT )

+#define __bdmac_channel_descriptor_invalid_detected(n) \

+  (  REG_BDMAC_DCCSR((n)) & BDMAC_DCCSR_INV )

+#define __bdmac_BCH_error_detected(n) \

+  (  REG_BDMAC_DCCSR((n)) & BDMAC_DCCSR_BERR )

+

+#define __bdmac_channel_clear_transmit_halt(n)				\

+	do {								\

+		/* clear both channel halt error and globle halt error */ \

+		REG_BDMAC_DCCSR(n) &= ~BDMAC_DCCSR_HLT;			\

+		REG_BDMAC_DMACR &= ~BDMAC_DMACR_HLT;	\

+	} while (0)

+#define __bdmac_channel_clear_transmit_end(n) \

+  (  REG_BDMAC_DCCSR(n) &= ~BDMAC_DCCSR_TT )

+#define __bdmac_channel_clear_status_error() \

+  ( REG_BDMAC_DCCSR(1) &= ~BDMAC_DCCSR_NSERR )

+#define __bdmac_channel_clear_address_error(n)				\

+	do {								\

+		REG_BDMAC_DDA(n) = 0; /* clear descriptor address register */ \

+		REG_BDMAC_DSAR(n) = 0; /* clear source address register */ \

+		REG_BDMAC_DTAR(n) = 0; /* clear target address register */ \

+		/* clear both channel addr error and globle address error */ \

+		REG_BDMAC_DCCSR(n) &= ~BDMAC_DCCSR_AR;			\

+		REG_BDMAC_DMACR &= ~BDMAC_DMACR_AR;	\

+	} while (0)

+#define __bdmac_channel_clear_count_terminated(n) \

+  (  REG_BDMAC_DCCSR((n)) &= ~BDMAC_DCCSR_CT )

+#define __bdmac_channel_clear_descriptor_invalid(n) \

+  (  REG_BDMAC_DCCSR((n)) &= ~BDMAC_DCCSR_INV )

+

+#define __bdmac_channel_set_transfer_unit_32bit(n)	\

+do {							\

+	REG_BDMAC_DCMD((n)) &= ~BDMAC_DCMD_DS_MASK;	\

+	REG_BDMAC_DCMD((n)) |= BDMAC_DCMD_DS_32BIT;	\

+} while (0)

+

+#define __bdmac_channel_set_transfer_unit_16bit(n)	\

+do {							\

+	REG_BDMAC_DCMD((n)) &= ~BDMAC_DCMD_DS_MASK;	\

+	REG_BDMAC_DCMD((n)) |= BDMAC_DCMD_DS_16BIT;	\

+} while (0)

+

+#define __bdmac_channel_set_transfer_unit_8bit(n)	\

+do {							\

+	REG_BDMAC_DCMD((n)) &= ~BDMAC_DCMD_DS_MASK;	\

+	REG_BDMAC_DCMD((n)) |= BDMAC_DCMD_DS_8BIT;	\

+} while (0)

+

+#define __bdmac_channel_set_transfer_unit_16byte(n)	\

+do {							\

+	REG_BDMAC_DCMD((n)) &= ~BDMAC_DCMD_DS_MASK;	\

+	REG_BDMAC_DCMD((n)) |= BDMAC_DCMD_DS_16BYTE;	\

+} while (0)

+

+#define __bdmac_channel_set_transfer_unit_32byte(n)	\

+do {							\

+	REG_BDMAC_DCMD((n)) &= ~BDMAC_DCMD_DS_MASK;	\

+	REG_BDMAC_DCMD((n)) |= BDMAC_DCMD_DS_32BYTE;	\

+} while (0)

+

+/* w=8,16,32 */

+#define __bdmac_channel_set_dest_port_width(n,w)		\

+do {							\

+	REG_BDMAC_DCMD((n)) &= ~BDMAC_DCMD_DWDH_MASK;	\

+	REG_BDMAC_DCMD((n)) |= BDMAC_DCMD_DWDH_##w;	\

+} while (0)

+

+/* w=8,16,32 */

+#define __bdmac_channel_set_src_port_width(n,w)		\

+do {							\

+	REG_BDMAC_DCMD((n)) &= ~BDMAC_DCMD_SWDH_MASK;	\

+	REG_BDMAC_DCMD((n)) |= BDMAC_DCMD_SWDH_##w;	\

+} while (0)

+

+#define __bdmac_channel_dest_addr_fixed(n) \

+	(REG_BDMAC_DCMD((n)) &= ~BDMAC_DCMD_DAI)

+#define __bdmac_channel_dest_addr_increment(n) \

+	(REG_BDMAC_DCMD((n)) |= BDMAC_DCMD_DAI)

+

+#define __bdmac_channel_src_addr_fixed(n) \

+	(REG_BDMAC_DCMD((n)) &= ~BDMAC_DCMD_SAI)

+#define __bdmac_channel_src_addr_increment(n) \

+	(REG_BDMAC_DCMD((n)) |= BDMAC_DCMD_SAI)

+

+#define __bdmac_channel_set_doorbell(n)	\

+	(REG_BDMAC_DMADBSR = (1 << (n)))

+

+#define __bdmac_channel_irq_detected(n)  (REG_BDMAC_DMAIPR & (1 << (n)))

+#define __bdmac_channel_ack_irq(n)       (REG_BDMAC_DMAIPR &= ~(1 <<(n)))

+

+static __inline__ int __bdmac_get_irq(void)

+{

+	int i;

+	for (i = 0; i < MAX_BDMA_NUM; i++)

+		if (__bdmac_channel_irq_detected(i))

+			return i;

+	return -1;

+}

+

+#endif /* __MIPS_ASSEMBLER */

+

+#endif /* __JZ4770BDMA_H__ */

+

diff --git a/arch/mips/include/asm/mach-jz4770/jz4770cim.h b/arch/mips/include/asm/mach-jz4770/jz4770cim.h
new file mode 100644
index 00000000000..0c84dd24f46
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4770/jz4770cim.h
@@ -0,0 +1,417 @@
+/*

+ * linux/include/asm-mips/mach-jz4770/jz4770cim.h

+ *

+ * JZ4770 CIM register definition.

+ *

+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

+ */

+

+#ifndef __JZ4770CIM_H__

+#define __JZ4770CIM_H__

+

+

+#define	CIM_BASE	0xB3060000

+

+/*************************************************************************

+ * CIM

+ *************************************************************************/

+#define	CIM_CFG			(CIM_BASE + 0x0000)

+#define	CIM_CTRL		(CIM_BASE + 0x0004)

+#define	CIM_STATE		(CIM_BASE + 0x0008)

+#define	CIM_IID			(CIM_BASE + 0x000C)

+#define	CIM_RXFIFO		(CIM_BASE + 0x0010)

+#define	CIM_DA			(CIM_BASE + 0x0020)

+#define	CIM_FA			(CIM_BASE + 0x0024)

+#define	CIM_FID			(CIM_BASE + 0x0028)

+#define	CIM_CMD			(CIM_BASE + 0x002C)

+#define	CIM_SIZE		(CIM_BASE + 0x0030)

+#define	CIM_OFFSET		(CIM_BASE + 0x0034)

+#define CIM_YFA			(CIM_BASE + 0x0038)

+#define CIM_YCMD		(CIM_BASE + 0x003C)

+#define CIM_CBFA		(CIM_BASE + 0x0040)

+#define CIM_CBCMD		(CIM_BASE + 0x0044)

+#define CIM_CRFA		(CIM_BASE + 0x0048)

+#define CIM_CRCMD		(CIM_BASE + 0x004C)

+#define CIM_CTRL2		(CIM_BASE + 0x0050)

+#define	CIM_RAM_ADDR		(CIM_BASE + 0x1000)

+

+#define	REG_CIM_CFG		REG32(CIM_CFG)

+#define	REG_CIM_CTRL		REG32(CIM_CTRL)

+#define REG_CIM_CTRL2		REG32(CIM_CTRL2)

+#define	REG_CIM_STATE		REG32(CIM_STATE)

+#define	REG_CIM_IID		REG32(CIM_IID)

+#define	REG_CIM_RXFIFO		REG32(CIM_RXFIFO)

+#define	REG_CIM_DA		REG32(CIM_DA)

+#define	REG_CIM_FA		REG32(CIM_FA)

+#define	REG_CIM_FID		REG32(CIM_FID)

+#define	REG_CIM_CMD		REG32(CIM_CMD)

+#define	REG_CIM_SIZE		REG32(CIM_SIZE)

+#define	REG_CIM_OFFSET		REG32(CIM_OFFSET)

+#define REG_CIM_YFA		REG32(CIM_YFA)

+#define REG_CIM_YCMD		REG32(CIM_YCMD)

+#define REG_CIM_CBFA		REG32(CIM_CBFA)

+#define REG_CIM_CBCMD		REG32(CIM_CBCMD)

+#define REG_CIM_CRFA		REG32(CIM_CRFA)

+#define REG_CIM_CRCMD		REG32(CIM_CRCMD)

+

+#define CIM_CFG_RXF_TRIG_BIT	24

+#define CIM_CFG_RXF_TRIG_MASK	(0x3f << CIM_CFG_RT_TRIG_MASK)

+#define CIM_CFG_SEP		(1 << 20)

+#define	CIM_CFG_ORDER_BIT	18

+#define	CIM_CFG_ORDER_MASK	(0x3 << CIM_CFG_ORDER_BIT)

+  #define CIM_CFG_ORDER_0	  (0x0 << CIM_CFG_ORDER_BIT) 	/* Y0CbY1Cr; YCbCr */

+  #define CIM_CFG_ORDER_1	  (0x1 << CIM_CFG_ORDER_BIT)	/* Y0CrY1Cb; YCrCb */

+  #define CIM_CFG_ORDER_2	  (0x2 << CIM_CFG_ORDER_BIT)	/* CbY0CrY1; CbCrY */

+  #define CIM_CFG_ORDER_3	  (0x3 << CIM_CFG_ORDER_BIT)	/* CrY0CbY1; CrCbY */

+#define	CIM_CFG_DF_BIT		16

+#define	CIM_CFG_DF_MASK		  (0x3 << CIM_CFG_DF_BIT)

+  #define CIM_CFG_DF_YUV444	  (0x1 << CIM_CFG_DF_BIT) 	/* YCbCr444 */

+  #define CIM_CFG_DF_YUV422	  (0x2 << CIM_CFG_DF_BIT)	/* YCbCr422 */

+  #define CIM_CFG_DF_ITU656	  (0x3 << CIM_CFG_DF_BIT)	/* ITU656 YCbCr422 */

+#define	CIM_CFG_INV_DAT		(1 << 15)

+#define	CIM_CFG_VSP		(1 << 14) /* VSYNC Polarity:0-rising edge active,1-falling edge active */

+#define	CIM_CFG_HSP		(1 << 13) /* HSYNC Polarity:0-rising edge active,1-falling edge active */

+#define	CIM_CFG_PCP		(1 << 12) /* PCLK working edge: 0-rising, 1-falling */

+#define	CIM_CFG_DMA_BURST_TYPE_BIT	10

+#define	CIM_CFG_DMA_BURST_TYPE_MASK	(0x3 << CIM_CFG_DMA_BURST_TYPE_BIT)

+  #define	CIM_CFG_DMA_BURST_INCR4		(0 << CIM_CFG_DMA_BURST_TYPE_BIT)

+  #define	CIM_CFG_DMA_BURST_INCR8		(1 << CIM_CFG_DMA_BURST_TYPE_BIT)	/* Suggested */

+  #define	CIM_CFG_DMA_BURST_INCR16	(2 << CIM_CFG_DMA_BURST_TYPE_BIT)	/* Suggested High speed AHB*/

+  #define	CIM_CFG_DMA_BURST_INCR32	(3 << CIM_CFG_DMA_BURST_TYPE_BIT)	/* Suggested High speed AHB*/

+#define	CIM_CFG_DUMMY_ZERO	(1 << 9)

+#define	CIM_CFG_EXT_VSYNC	(1 << 8)	/* Only for ITU656 Progressive mode */

+#define	CIM_CFG_PACK_BIT	4

+#define	CIM_CFG_PACK_MASK	(0x7 << CIM_CFG_PACK_BIT)

+  #define CIM_CFG_PACK_0	  (0 << CIM_CFG_PACK_BIT) /* 11 22 33 44 0xY0CbY1Cr */

+  #define CIM_CFG_PACK_1	  (1 << CIM_CFG_PACK_BIT) /* 22 33 44 11 0xCbY1CrY0 */

+  #define CIM_CFG_PACK_2	  (2 << CIM_CFG_PACK_BIT) /* 33 44 11 22 0xY1CrY0Cb */

+  #define CIM_CFG_PACK_3	  (3 << CIM_CFG_PACK_BIT) /* 44 11 22 33 0xCrY0CbY1 */

+  #define CIM_CFG_PACK_4	  (4 << CIM_CFG_PACK_BIT) /* 44 33 22 11 0xCrY1CbY0 */

+  #define CIM_CFG_PACK_5	  (5 << CIM_CFG_PACK_BIT) /* 33 22 11 44 0xY1CbY0Cr */

+  #define CIM_CFG_PACK_6	  (6 << CIM_CFG_PACK_BIT) /* 22 11 44 33 0xCbY0CrY1 */

+  #define CIM_CFG_PACK_7	  (7 << CIM_CFG_PACK_BIT) /* 11 44 33 22 0xY0CrY1Cb */

+#define	CIM_CFG_BYPASS_BIT	2

+#define	CIM_CFG_BYPASS_MASK	(1 << CIM_CFG_BYPASS_BIT)

+  #define CIM_CFG_BYPASS	  (1 << CIM_CFG_BYPASS_BIT)

+#define	CIM_CFG_DSM_BIT		0

+#define	CIM_CFG_DSM_MASK	(0x3 << CIM_CFG_DSM_BIT)

+  #define CIM_CFG_DSM_CPM	  (0 << CIM_CFG_DSM_BIT) /* CCIR656 Progressive Mode */

+  #define CIM_CFG_DSM_CIM	  (1 << CIM_CFG_DSM_BIT) /* CCIR656 Interlace Mode */

+  #define CIM_CFG_DSM_GCM	  (2 << CIM_CFG_DSM_BIT) /* Gated Clock Mode */

+

+/* CIM Control Register  (CIM_CTRL) */

+#define	CIM_CTRL_EEOF_LINE_BIT	20

+#define	CIM_CTRL_EEOF_LINE_MASK	(0xfff << CIM_CTRL_EEOF_LINE_BIT)

+#define	CIM_CTRL_FRC_BIT	16

+#define	CIM_CTRL_FRC_MASK	(0xf << CIM_CTRL_FRC_BIT)

+  #define CIM_CTRL_FRC_1	  (0x0 << CIM_CTRL_FRC_BIT) /* Sample every frame */

+  #define CIM_CTRL_FRC_2	  (0x1 << CIM_CTRL_FRC_BIT) /* Sample 1/2 frame */

+  #define CIM_CTRL_FRC_3	  (0x2 << CIM_CTRL_FRC_BIT) /* Sample 1/3 frame */

+  #define CIM_CTRL_FRC_4	  (0x3 << CIM_CTRL_FRC_BIT) /* Sample 1/4 frame */

+  #define CIM_CTRL_FRC_5	  (0x4 << CIM_CTRL_FRC_BIT) /* Sample 1/5 frame */

+  #define CIM_CTRL_FRC_6	  (0x5 << CIM_CTRL_FRC_BIT) /* Sample 1/6 frame */

+  #define CIM_CTRL_FRC_7	  (0x6 << CIM_CTRL_FRC_BIT) /* Sample 1/7 frame */

+  #define CIM_CTRL_FRC_8	  (0x7 << CIM_CTRL_FRC_BIT) /* Sample 1/8 frame */

+  #define CIM_CTRL_FRC_9	  (0x8 << CIM_CTRL_FRC_BIT) /* Sample 1/9 frame */

+  #define CIM_CTRL_FRC_10	  (0x9 << CIM_CTRL_FRC_BIT) /* Sample 1/10 frame */

+  #define CIM_CTRL_FRC_11	  (0xA << CIM_CTRL_FRC_BIT) /* Sample 1/11 frame */

+  #define CIM_CTRL_FRC_12	  (0xB << CIM_CTRL_FRC_BIT) /* Sample 1/12 frame */

+  #define CIM_CTRL_FRC_13	  (0xC << CIM_CTRL_FRC_BIT) /* Sample 1/13 frame */

+  #define CIM_CTRL_FRC_14	  (0xD << CIM_CTRL_FRC_BIT) /* Sample 1/14 frame */

+  #define CIM_CTRL_FRC_15	  (0xE << CIM_CTRL_FRC_BIT) /* Sample 1/15 frame */

+  #define CIM_CTRL_FRC_16	  (0xF << CIM_CTRL_FRC_BIT) /* Sample 1/16 frame */

+

+#define	CIM_CTRL_DMA_EEOFM	(1 << 15)	/* Enable EEOF interrupt */

+#define	CIM_CTRL_WIN_EN		(1 << 14)

+#define	CIM_CTRL_VDDM		(1 << 13) /* VDD interrupt enable */

+#define	CIM_CTRL_DMA_SOFM	(1 << 12)

+#define	CIM_CTRL_DMA_EOFM	(1 << 11)

+#define	CIM_CTRL_DMA_STOPM	(1 << 10)

+#define	CIM_CTRL_RXF_TRIGM	(1 << 9)

+#define	CIM_CTRL_RXF_OFM	(1 << 8)

+#define	CIM_CTRL_DMA_SYNC	(1 << 7)	/*when change DA, do frame sync */

+#define	CIM_CTRL_RXF_TRIG_BIT	3

+#define	CIM_CTRL_RXF_TRIG_MASK	(0xf << CIM_CTRL_RXF_TRIG_BIT) /* trigger value = (n+1)*burst_type */

+

+#define	CIM_CTRL_DMA_EN		(1 << 2) /* Enable DMA */

+#define	CIM_CTRL_RXF_RST	(1 << 1) /* RxFIFO reset */

+#define	CIM_CTRL_ENA		(1 << 0) /* Enable CIM */

+

+

+/* cim control2 */

+#define CIM_CTRL2_OPG_BIT	4

+#define CIM_CTRL2_OPG_MASK	(0x3 << CIM_CTRL2_OPG_BIT)

+#define CIM_CTRL2_OPE		(1 << 2)

+#define CIM_CTRL2_EME		(1 << 1)

+#define CIM_CTRL2_APM		(1 << 0)

+

+/* CIM State Register  (CIM_STATE) */

+#define CIM_STATE_CR_RF_OF	(1 << 27)

+#define CIM_STATE_CR_RF_TRIG	(1 << 26)

+#define CIM_STATE_CR_RF_EMPTY	(1 << 25)

+

+#define CIM_STATE_CB_RF_OF	(1 << 19)

+#define CIM_STATE_CB_RF_TRIG	(1 << 18)

+#define CIM_STATE_CB_RF_EMPTY	(1 << 17)

+

+#define CIM_STATE_Y_RF_OF	(1 << 11)

+#define CIM_STATE_Y_RF_TRIG	(1 << 10)

+#define CIM_STATE_Y_RF_EMPTY	(1 << 9)

+

+#define	CIM_STATE_DMA_EEOF	(1 << 7) /* DMA Line EEOf irq */

+#define	CIM_STATE_DMA_SOF	(1 << 6) /* DMA start irq */

+#define	CIM_STATE_DMA_EOF	(1 << 5) /* DMA end irq */

+#define	CIM_STATE_DMA_STOP	(1 << 4) /* DMA stop irq */

+#define	CIM_STATE_RXF_OF	(1 << 3) /* RXFIFO over flow irq */

+#define	CIM_STATE_RXF_TRIG	(1 << 2) /* RXFIFO triger meet irq */

+#define	CIM_STATE_RXF_EMPTY	(1 << 1) /* RXFIFO empty irq */

+#define	CIM_STATE_VDD		(1 << 0) /* CIM disabled irq */

+

+/* CIM DMA Command Register (CIM_CMD) */

+

+#define	CIM_CMD_SOFINT		(1 << 31) /* enable DMA start irq */

+#define	CIM_CMD_EOFINT		(1 << 30) /* enable DMA end irq */

+#define	CIM_CMD_EEOFINT		(1 << 29) /* enable DMA EEOF irq */

+#define	CIM_CMD_STOP		(1 << 28) /* enable DMA stop irq */

+#define	CIM_CMD_OFRCV		(1 << 27) /* enable recovery when TXFiFo overflow */

+#define	CIM_CMD_LEN_BIT		0

+#define	CIM_CMD_LEN_MASK	(0xffffff << CIM_CMD_LEN_BIT)

+

+/* CIM Window-Image Size Register  (CIM_SIZE) */

+#define	CIM_SIZE_LPF_BIT	16 /* Lines per freame for csc output image */

+#define	CIM_SIZE_LPF_MASK	(0x1fff << CIM_SIZE_LPF_BIT)

+#define	CIM_SIZE_PPL_BIT	0 /* Pixels per line for csc output image, should be an even number */

+#define	CIM_SIZE_PPL_MASK	(0x1fff << CIM_SIZE_PPL_BIT)

+

+/* CIM Image Offset Register  (CIM_OFFSET) */

+#define	CIM_OFFSET_V_BIT	16 /* Vertical offset */

+#define	CIM_OFFSET_V_MASK	(0xfff << CIM_OFFSET_V_BIT)

+#define	CIM_OFFSET_H_BIT	0 /* Horizontal offset, should be an enen number */

+#define	CIM_OFFSET_H_MASK	(0xfff << CIM_OFFSET_H_BIT) /*OFFSET_H should be even number*/

+

+#ifndef __MIPS_ASSEMBLER

+

+/***************************************************************************

+ * CIM

+ ***************************************************************************/

+

+#define __cim_enable()	( REG_CIM_CTRL |= CIM_CTRL_ENA )

+#define __cim_disable()	( REG_CIM_CTRL &= ~CIM_CTRL_ENA )

+

+#define __cim_enable_sep() (REG_CIM_CFG |= CIM_CFG_SEP)

+#define __cim_disable_sep() (REG_CIM_CFG &= ~CIM_CFG_SEP)

+

+/* n = 0, 1, 2, 3 */

+#define __cim_set_input_data_stream_order(n)				\

+	do {								\

+		REG_CIM_CFG &= ~CIM_CFG_ORDER_MASK;			\

+		REG_CIM_CFG |= ((n)<<CIM_CFG_ORDER_BIT)&CIM_CFG_ORDER_MASK; \

+	} while (0)

+

+#define __cim_input_data_format_select_RGB()	\

+	do {					\

+		REG_CIM_CFG &= ~CIM_CFG_DF_MASK;	\

+		REG_CIM_CFG |= CIM_CFG_DF_RGB;	\

+	} while (0)

+

+#define __cim_input_data_format_select_YUV444()		\

+	do {						\

+		REG_CIM_CFG &= ~CIM_CFG_DF_MASK;		\

+		REG_CIM_CFG |= CIM_CFG_DF_YUV444;	\

+	} while (0)

+

+#define __cim_input_data_format_select_YUV422()		\

+	do {						\

+		REG_CIM_CFG &= ~CIM_CFG_DF_MASK;		\

+		REG_CIM_CFG |= CIM_CFG_DF_YUV422;	\

+	} while (0)

+

+#define __cim_input_data_format_select_ITU656()		\

+	do {						\

+		REG_CIM_CFG &= ~CIM_CFG_DF_MASK;		\

+		REG_CIM_CFG |= CIM_CFG_DF_ITU656;	\

+	} while (0)

+

+#define __cim_input_data_inverse()	( REG_CIM_CFG |= CIM_CFG_INV_DAT )

+#define __cim_input_data_normal()	( REG_CIM_CFG &= ~CIM_CFG_INV_DAT )

+

+#define __cim_vsync_active_low()	( REG_CIM_CFG |= CIM_CFG_VSP )

+#define __cim_vsync_active_high()	( REG_CIM_CFG &= ~CIM_CFG_VSP )

+

+#define __cim_hsync_active_low()	( REG_CIM_CFG |= CIM_CFG_HSP )

+#define __cim_hsync_active_high()	( REG_CIM_CFG &= ~CIM_CFG_HSP )

+

+#define __cim_sample_data_at_pclk_falling_edge() \

+	( REG_CIM_CFG |= CIM_CFG_PCP )

+#define __cim_sample_data_at_pclk_rising_edge() \

+	( REG_CIM_CFG &= ~CIM_CFG_PCP )

+

+#define __cim_enable_dummy_zero()	( REG_CIM_CFG |= CIM_CFG_DUMMY_ZERO )

+#define __cim_disable_dummy_zero()	( REG_CIM_CFG &= ~CIM_CFG_DUMMY_ZERO )

+

+#define __cim_select_external_vsync()	( REG_CIM_CFG |= CIM_CFG_EXT_VSYNC )

+#define __cim_select_internal_vsync()	( REG_CIM_CFG &= ~CIM_CFG_EXT_VSYNC )

+

+/* n=0-7 */

+#define __cim_set_data_packing_mode(n) 		\

+do {						\

+	REG_CIM_CFG &= ~CIM_CFG_PACK_MASK;	\

+	REG_CIM_CFG |= (CIM_CFG_PACK_##n);	\

+} while (0)

+

+#define __cim_enable_bypass_func() 	(REG_CIM_CFG |= CIM_CFG_BYPASS)

+#define __cim_disable_bypass_func() 	(REG_CIM_CFG &= ~CIM_CFG_BYPASS_MASK)

+

+#define __cim_enable_ccir656_progressive_mode()	\

+do {						\

+	REG_CIM_CFG &= ~CIM_CFG_DSM_MASK;	\

+	REG_CIM_CFG |= CIM_CFG_DSM_CPM;		\

+} while (0)

+

+#define __cim_enable_ccir656_interlace_mode()	\

+do {						\

+	REG_CIM_CFG &= ~CIM_CFG_DSM_MASK;	\

+	REG_CIM_CFG |= CIM_CFG_DSM_CIM;		\

+} while (0)

+

+#define __cim_enable_gated_clock_mode()		\

+do {						\

+	REG_CIM_CFG &= ~CIM_CFG_DSM_MASK;	\

+	REG_CIM_CFG |= CIM_CFG_DSM_GCM;		\

+} while (0)

+

+#define __cim_enable_nongated_clock_mode()	\

+do {						\

+	REG_CIM_CFG &= ~CIM_CFG_DSM_MASK;	\

+	REG_CIM_CFG |= CIM_CFG_DSM_NGCM;	\

+} while (0)

+

+/* sclk:system bus clock

+ * mclk: CIM master clock

+ */

+#define __cim_set_master_clk(sclk, mclk)			\

+do {								\

+	REG_CIM_CTRL &= ~CIM_CTRL_MCLKDIV_MASK;				\

+	REG_CIM_CTRL |= (((sclk)/(mclk) - 1) << CIM_CTRL_MCLKDIV_BIT);	\

+} while (0)

+/* n=1-16 */

+#define __cim_set_frame_rate(n) 		\

+do {						\

+	REG_CIM_CTRL &= ~CIM_CTRL_FRC_MASK; 	\

+	REG_CIM_CTRL |= CIM_CTRL_FRC_##n;	\

+} while (0)

+

+#define __cim_enable_size_func() \

+	( REG_CIM_CTRL |= CIM_CTRL_WIN_EN)

+#define __cim_disable_size_func() \

+	( REG_CIM_CTRL &= ~CIM_CTRL_WIN_EN )

+

+#define __cim_enable_vdd_intr() \

+	( REG_CIM_CTRL |= CIM_CTRL_VDDM )

+#define __cim_disable_vdd_intr() \

+	( REG_CIM_CTRL &= ~CIM_CTRL_VDDM )

+

+#define __cim_enable_sof_intr() \

+	( REG_CIM_CTRL |= CIM_CTRL_DMA_SOFM )

+#define __cim_disable_sof_intr() \

+	( REG_CIM_CTRL &= ~CIM_CTRL_DMA_SOFM )

+

+#define __cim_enable_eof_intr() \

+	( REG_CIM_CTRL |= CIM_CTRL_DMA_EOFM )

+#define __cim_disable_eof_intr() \

+	( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EOFM )

+

+#define __cim_enable_eeof_intr() \

+	( REG_CIM_CTRL |= CIM_CTRL_DMA_EEOFM )

+#define __cim_disable_eeof_intr() \

+	( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EEOFM )

+

+#define __cim_enable_stop_intr() \

+	( REG_CIM_CTRL |= CIM_CTRL_DMA_STOPM )

+#define __cim_disable_stop_intr() \

+	( REG_CIM_CTRL &= ~CIM_CTRL_DMA_STOPM )

+

+#define __cim_enable_trig_intr() \

+	( REG_CIM_CTRL |= CIM_CTRL_RXF_TRIGM )

+#define __cim_disable_trig_intr() \

+	( REG_CIM_CTRL &= ~CIM_CTRL_RXF_TRIGM )

+

+#define __cim_enable_rxfifo_overflow_intr()	\

+	( REG_CIM_CTRL |= CIM_CTRL_RXF_OFM )

+#define __cim_disable_rxfifo_overflow_intr()	\

+	( REG_CIM_CTRL &= ~CIM_CTRL_RXF_OFM )

+

+/* n=4,8,12,16,20,24,28,32 */

+#define __cim_set_rxfifo_trigger(n)				\

+	do {							\

+		REG_CIM_CTRL &= ~CIM_CTRL_RXF_TRIG_MASK; 	\

+		REG_CIM_CTRL |= CIM_CTRL_RXF_TRIG_##n;		\

+	} while (0)

+

+

+#define __cim_set_eeof_line(n)						\

+	do {								\

+		REG_CIM_CTRL &= ~CIM_CTRL_EEOF_LINE_MASK;		\

+		REG_CIM_CTRL |= ( ((n) << CIM_CTRL_EEOF_LINE_BIT) & CIM_CTRL_EEOF_LINE_MASK ); \

+	} while (0)

+

+#define __cim_enable_fast_mode() 	( REG_CIM_CTRL |= CIM_CTRL_FAST_MODE )

+#define __cim_disable_fast_mode() 	( REG_CIM_CTRL &= ~CIM_CTRL_FAST_MODE )

+#define __cim_use_normal_mode() 	__cim_disable_fast_mode()

+#define __cim_enable_dma()   ( REG_CIM_CTRL |= CIM_CTRL_DMA_EN )

+#define __cim_disable_dma()  ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EN )

+#define __cim_reset_rxfifo() ( REG_CIM_CTRL |= CIM_CTRL_RXF_RST )

+#define __cim_unreset_rxfifo() ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_RST )

+

+/* cim control2 */

+#define __cim_enable_priority_control()		( REG_CIM_CTRL2 |= CIM_CTRL2_APM)

+#define __cim_disable_priority_control()	( REG_CIM_CTRL2 &= ~CIM_CTRL2_APM)

+#define __cim_enable_auto_priority()		( REG_CIM_CTRL2 |= CIM_CTRL2_OPE)

+#define __cim_disable_auto_priority()		( REG_CIM_CTRL2 &= ~CIM_CTRL2_OPE)

+#define __cim_enable_emergency()		( REG_CIM_CTRL2 |= CIM_CTRL2_EME)

+#define __cim_disable_emergency()		( REG_CIM_CTRL2 &= ~CIM_CTRL2_EME);

+/* 0, 1, 2, 3

+ * 0: highest priority

+ * 3: lowest priority

+ * 1 maybe best for SEP=1

+ * 3 maybe best for SEP=0

+ */

+#define __cim_set_opg(n)				\

+	do {								\

+		REG_CIM_CTRL2 &= ~CIM_CTRL2_OPG_MASK;			\

+		REG_CIM_CTRL2 |= ((n) << CIM_CTRL2_OPG_BIT) & CIM_CTRL2_OPG_MASK; \

+	} while (0)

+

+#define __cim_clear_state()   	     ( REG_CIM_STATE = 0 )

+

+#define __cim_disable_done()   	     ( REG_CIM_STATE & CIM_STATE_VDD )

+#define __cim_rxfifo_empty()   	     ( REG_CIM_STATE & CIM_STATE_RXF_EMPTY )

+#define __cim_rxfifo_reach_trigger() ( REG_CIM_STATE & CIM_STATE_RXF_TRIG )

+#define __cim_rxfifo_overflow()      ( REG_CIM_STATE & CIM_STATE_RXF_OF )

+#define __cim_clear_rxfifo_overflow() ( REG_CIM_STATE &= ~CIM_STATE_RXF_OF )

+#define __cim_dma_stop()   	     ( REG_CIM_STATE & CIM_STATE_DMA_STOP )

+#define __cim_dma_eof()   	     ( REG_CIM_STATE & CIM_STATE_DMA_EOF )

+#define __cim_dma_sof()   	     ( REG_CIM_STATE & CIM_STATE_DMA_SOF )

+

+#define __cim_get_iid()   	     ( REG_CIM_IID )

+#define __cim_get_fid()   	     ( REG_CIM_FID )

+#define __cim_get_image_data()       ( REG_CIM_RXFIFO )

+#define __cim_get_dma_cmd()          ( REG_CIM_CMD )

+

+#define __cim_set_da(a)              ( REG_CIM_DA = (a) )

+

+#define __cim_set_line(a) 	( REG_CIM_SIZE = (REG_CIM_SIZE&(~CIM_SIZE_LPF_MASK))|((a)<<CIM_SIZE_LPF_BIT) )

+#define __cim_set_pixel(a) 	( REG_CIM_SIZE = (REG_CIM_SIZE&(~CIM_SIZE_PPL_MASK))|((a)<<CIM_SIZE_PPL_BIT) )

+#define __cim_get_line() 	((REG_CIM_SIZE&CIM_SIZE_LPF_MASK)>>CIM_SIZE_LPF_BIT)

+#define __cim_get_pixel() 	((REG_CIM_SIZE&CIM_SIZE_PPL_MASK)>>CIM_SIZE_PPL_BIT)

+

+#define __cim_set_v_offset(a) 	( REG_CIM_OFFSET = (REG_CIM_OFFSET&(~CIM_OFFSET_V_MASK)) | ((a)<<CIM_OFFSET_V_BIT) )

+#define __cim_set_h_offset(a) 	( REG_CIM_OFFSET = (REG_CIM_OFFSET&(~CIM_OFFSET_H_MASK)) | ((a)<<CIM_OFFSET_H_BIT) )

+#define __cim_get_v_offset() 	((REG_CIM_OFFSET&CIM_OFFSET_V_MASK)>>CIM_OFFSET_V_BIT)

+#define __cim_get_h_offset() 	((REG_CIM_OFFSET&CIM_OFFSET_H_MASK)>>CIM_OFFSET_H_BIT)

+

+

+

+#endif /* __MIPS_ASSEMBLER */

+

+#endif /* __JZ4770CIM_H__ */

diff --git a/arch/mips/include/asm/mach-jz4770/jz4770cpm.h b/arch/mips/include/asm/mach-jz4770/jz4770cpm.h
new file mode 100644
index 00000000000..2a0092c6b79
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4770/jz4770cpm.h
@@ -0,0 +1,665 @@
+/*

+ * linux/include/asm-mips/mach-jz4770/jz4770cpm.h

+ *

+ * JZ4770 CPM register definition.

+ *

+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

+ */

+

+#ifndef __JZ4770CPM_H__

+#define __JZ4770CPM_H__

+

+

+#define	CPM_BASE	0xB0000000

+

+

+/*************************************************************************

+ * CPM (Clock reset and Power control Management)

+ *************************************************************************/

+#define CPM_CPCCR		(CPM_BASE + 0x00) /* Clock control register		*/

+#define CPM_RSR                 (CPM_BASE + 0x08)

+#define CPM_CPPCR		(CPM_BASE + 0x10) /* PLL control register 0		*/

+#define CPM_CPPSR		(CPM_BASE + 0x14) /* PLL switch and status Register	*/

+#define CPM_CPPCR1		(CPM_BASE + 0x30) /* PLL control register 1		*/

+#define CPM_CPSPR		(CPM_BASE + 0x34) /* CPM scratch pad register		*/

+#define CPM_CPSPPR		(CPM_BASE + 0x38) /* CPM scratch protected register	*/

+#define CPM_USBPCR		(CPM_BASE + 0x3c) /* USB parameter control register	*/

+#define CPM_USBRDT		(CPM_BASE + 0x40) /* USB reset detect timer register	*/

+#define CPM_USBVBFIL		(CPM_BASE + 0x44) /* USB jitter filter register		*/

+#define CPM_USBCDR		(CPM_BASE + 0x50) /* USB OTG PHY clock divider register	*/

+#define CPM_I2SCDR		(CPM_BASE + 0x60) /* I2S device clock divider register	*/

+#define CPM_LPCDR		(CPM_BASE + 0x64) /* LCD pix clock divider register	*/

+#define CPM_MSCCDR		(CPM_BASE + 0x68) /* MSC clock divider register		*/

+#define CPM_UHCCDR		(CPM_BASE + 0x6C) /* UHC 48M clock divider register	*/

+#define CPM_SSICDR		(CPM_BASE + 0x74) /* SSI clock divider register		*/

+#define CPM_CIMCDR		(CPM_BASE + 0x7c) /* CIM MCLK clock divider register	*/

+#define CPM_GPSCDR		(CPM_BASE + 0x80) /* GPS clock divider register		*/

+#define CPM_PCMCDR		(CPM_BASE + 0x84) /* PCM device clock divider register	*/

+#define CPM_GPUCDR		(CPM_BASE + 0x88) /* GPU clock divider register		*/

+

+#define CPM_PSWC0ST             (CPM_BASE + 0x90)

+#define CPM_PSWC1ST             (CPM_BASE + 0x94)

+#define CPM_PSWC2ST             (CPM_BASE + 0x98)

+#define CPM_PSWC3ST             (CPM_BASE + 0x9c)

+

+#define CPM_LCR			(CPM_BASE + 0x04)

+#define CPM_CLKGR0		(CPM_BASE + 0x20)

+#define CPM_OPCR		(CPM_BASE + 0x24)

+#define CPM_CLKGR1		(CPM_BASE + 0x28)

+

+#define REG_CPM_CPCCR		REG32(CPM_CPCCR)

+#define REG_CPM_RSR             REG32(CPM_RSR)

+#define REG_CPM_CPPCR		REG32(CPM_CPPCR)

+#define REG_CPM_CPPSR		REG32(CPM_CPPSR)

+#define REG_CPM_CPPCR1		REG32(CPM_CPPCR1)

+#define REG_CPM_CPSPR		REG32(CPM_CPSPR)

+#define REG_CPM_CPSPPR		REG32(CPM_CPSPPR)

+#define REG_CPM_USBPCR		REG32(CPM_USBPCR)

+#define REG_CPM_USBRDT		REG32(CPM_USBRDT)

+#define REG_CPM_USBVBFIL	REG32(CPM_USBVBFIL)

+#define REG_CPM_USBCDR		REG32(CPM_USBCDR)

+#define REG_CPM_I2SCDR		REG32(CPM_I2SCDR)

+#define REG_CPM_LPCDR		REG32(CPM_LPCDR)

+#define REG_CPM_MSCCDR		REG32(CPM_MSCCDR)

+#define REG_CPM_UHCCDR		REG32(CPM_UHCCDR)

+#define REG_CPM_SSICDR		REG32(CPM_SSICDR)

+#define REG_CPM_CIMCDR		REG32(CPM_CIMCDR)

+#define REG_CPM_GPSCDR		REG32(CPM_GPSCDR)

+#define REG_CPM_PCMCDR		REG32(CPM_PCMCDR)

+#define REG_CPM_GPUCDR		REG32(CPM_GPUCDR)

+

+#define REG_CPM_PSWC0ST		REG32(CPM_PSWC0ST)

+#define REG_CPM_PSWC1ST		REG32(CPM_PSWC1ST)

+#define REG_CPM_PSWC2ST		REG32(CPM_PSWC2ST)

+#define REG_CPM_PSWC3ST		REG32(CPM_PSWC3ST)

+

+#define REG_CPM_LCR		REG32(CPM_LCR)

+#define REG_CPM_CLKGR0		REG32(CPM_CLKGR0)

+#define REG_CPM_OPCR		REG32(CPM_OPCR)

+#define REG_CPM_CLKGR1		REG32(CPM_CLKGR1)

+#define REG_CPM_CLKGR		REG32(CPM_CLKGR0)

+

+#ifndef __MIPS_ASSEMBLER

+

+typedef enum {

+        CGM_NEMC = 0,

+        CGM_BCH  = 1,

+        CGM_OTG  = 2,

+        CGM_MSC0 = 3,

+        CGM_SSI0 = 4,

+        CGM_I2C0 = 5,

+        CGM_I2C1 = 6,

+        CGM_SCC  = 7,

+        CGM_AIC         = 8,

+        CGM_TSSI        = 9,

+        CGM_OWI         = 10,

+        CGM_MSC1        = 11,

+        CGM_MSC2        = 12,

+        CGM_KBC         = 13,

+        CGM_SADC        = 14,

+        CGM_UART0       = 15,

+        CGM_UART1 = 16,

+        CGM_UART2 = 17,

+        CGM_UART3 = 18,

+        CGM_SSI1  = 19,

+        CGM_SSI2  = 20,

+        CGM_DMAC  = 21,

+        CGM_GPS   = 22,

+        CGM_MAC   = 23,

+        CGM_UHC         = 24,

+        CGM_MDMA        = 25,

+        CGM_CIM         = 26,

+        CGM_TVE         = 27,

+        CGM_LCD         = 28,

+        CGM_IPU         = 29,

+        CGM_DDR         = 30,

+        CGM_EMC         = 31,

+        CGM_BDMA  = 32 + 0,

+        CGM_MC    = 32 + 1,

+        CGM_DBLK  = 32 + 2,

+        CGM_ME    = 32 + 3,

+        CGM_DCT   = 32 + 4,

+        CGM_SRAM  = 32 + 5,

+        CGM_CABAC = 32 + 6,

+        CGM_AHB1  = 32 + 7,

+        CGM_PCM         = 32 + 8,

+        CGM_GPU         = 32 + 9,

+        CGM_ALL_MODULE,

+} clock_gate_module;

+

+

+#define __CGU_CLOCK_BASE__      0x1000

+

+typedef enum {

+        /* Clock source is pll0 */

+        CGU_CCLK = __CGU_CLOCK_BASE__ + 0,

+        CGU_HCLK,

+        CGU_PCLK,

+        CGU_MCLK,

+        CGU_H2CLK,

+        CGU_SCLK,

+

+        /* Clock source is exclk, pll0 or pll0/2 */

+        CGU_MSCCLK,

+        CGU_SSICLK,

+

+        /* Clock source is pll0 or pll0/2 */

+        CGU_CIMCLK,

+

+        /* Clock source is exclk, pll0, pll0/2 or pll1 */

+        CGU_TVECLK,

+

+        /* Clock source is pll0 */

+        CGU_LPCLK,

+

+        /* Clock source is exclk, exclk/2, pll0, pll0/2 or pll1 */

+        CGU_I2SCLK,

+        CGU_PCMCLK,

+        CGU_OTGCLK,

+

+        /* Clock source is pll0, pll0/2 or pll1 */

+        CGU_UHCCLK,

+        CGU_GPSCLK,

+        CGU_GPUCLK,

+

+        /* Clock source is exclk or exclk/2 */

+        CGU_UARTCLK,

+        CGU_SADCCLK,

+

+        /* Clock source is exclk */

+        CGU_TCUCLK,

+

+	/* Clock source is external rtc clock */

+	CGU_RTCCLK,

+

+        CGU_CLOCK_MAX,

+} cgu_clock;

+#endif

+

+

+/* Clock control register */

+#define CPM_CPCCR_ECS			(1 << 31)

+#define CPM_CPCCR_MEM			(1 << 30)

+#define CPM_CPCCR_SDIV_BIT		24

+#define CPM_CPCCR_SDIV_MASK		(0x0f << CPM_CPCCR_SDIV_BIT)

+#define CPM_CPCCR_CE			(1 << 22)

+#define CPM_CPCCR_PCS			(1 << 21)

+#define CPM_CPCCR_H2DIV_BIT		16

+#define CPM_CPCCR_H2DIV_MASK		(0x0f << CPM_CPCCR_H2DIV_BIT)

+#define CPM_CPCCR_MDIV_BIT		12

+#define CPM_CPCCR_MDIV_MASK		(0x0f << CPM_CPCCR_MDIV_BIT)

+#define CPM_CPCCR_PDIV_BIT		8

+#define CPM_CPCCR_PDIV_MASK		(0x0f << CPM_CPCCR_PDIV_BIT)

+#define CPM_CPCCR_HDIV_BIT		4

+#define CPM_CPCCR_HDIV_MASK		(0x0f << CPM_CPCCR_HDIV_BIT)

+#define CPM_CPCCR_CDIV_BIT		0

+#define CPM_CPCCR_CDIV_MASK		(0x0f << CPM_CPCCR_CDIV_BIT)

+

+/*Reset status register*/

+#define CPM_RSR_P0R		(1 << 2)

+#define CPM_RSR_WR		(1 << 1)

+#define CPM_RSR_PR		(1 << 0)

+

+/* PLL control register 0 */

+#define CPM_CPPCR_PLLM_BIT		24

+#define CPM_CPPCR_PLLM_MASK		(0x7f << CPM_CPPCR_PLLM_BIT)

+#define CPM_CPPCR_PLLN_BIT		18

+#define CPM_CPPCR_PLLN_MASK		(0x0f << CPM_CPPCR_PLLN_BIT)

+#define CPM_CPPCR_PLLOD_BIT		16

+#define CPM_CPPCR_PLLOD_MASK		(0x03 << CPM_CPPCR_PLLOD_BIT)

+#define CPM_CPPCR_LOCK0			(1 << 15)

+#define CPM_CPPCR_ENLOCK		(1 << 14)

+#define CPM_CPPCR_PLLS			(1 << 10)

+#define CPM_CPPCR_PLLBP			(1 << 9)

+#define CPM_CPPCR_PLLEN			(1 << 8)

+#define CPM_CPPCR_PLLST_BIT		0

+#define CPM_CPPCR_PLLST_MASK		(0xff << CPM_CPPCR_PLLST_BIT)

+

+/* PLL control register 1 */

+#define CPM_CPPCR1_PLL1M_BIT		24

+#define CPM_CPCCR1_PLL1M_MASK		(0x7f << CPM_CPPCR1_PLL1M_BIT)

+#define CPM_CPCCR1_PLL1N_BIT		18

+#define CPM_CPCCR1_PLL1N_MASK		(0x0f << CPM_CPCCR1_PLL1N_BIT)

+#define CPM_CPCCR1_PLL1OD_BIT		16

+#define CPM_CPCCR1_PLL1OD_MASK		(0x03 << CPM_CPCCR1_PLL1OD_BIT)

+#define CPM_CPCCR1_P1SCS		(1 << 15)

+#define CPM_CPCCR1_P1SDIV_BIT		9

+#define CPM_CPCCR1_P1SDIV_MASK		(0x3f << CPM_CPCCR1_P1SDIV_BIT)

+#define CPM_CPCCR1_PLL1EN		(1 << 7)

+#define CPM_CPCCR1_PLL1S		(1 << 6)

+#define CPM_CPCCR1_LOCK1		(1 << 2)

+#define CPM_CPCCR1_PLL1OFF		(1 << 1)

+#define CPM_CPCCR1_PLL1ON		(1 << 0)

+

+/* PLL switch and status Register */

+#define CPM_CPPSR_PLLOFF		(1 << 31)

+#define CPM_CPPSR_PLLBP			(1 << 30)

+#define CPM_CPPSR_PLLON			(1 << 29)

+#define CPM_CPPSR_PS			(1 << 28)

+#define CPM_CPPSR_FS			(1 << 27)

+#define CPM_CPPSR_CS			(1 << 26)

+#define CPM_CPPSR_SM			(1 << 02)

+#define CPM_CPPSR_PM			(1 << 01)

+#define CPM_CPPSR_FM			(1 << 00)

+

+/* CPM scratch protected register */

+#define CPM_CPSPPR_BIT			0

+#define CPM_CPSPPR_MASK			(0xffff << CPM_CPSPPR_BIT)

+

+/* USB parameter control register */

+#define CPM_USBPCR_USB_MODE		(1 << 31)

+#define CPM_USBPCR_AVLD_REG		(1 << 30)

+#define CPM_USBPCR_IDPULLUP_MASK_BIT	28

+#define CPM_USBPCR_IDPULLUP_MASK_MASK	(0x02 << IDPULLUP_MASK_BIT)

+#define CPM_USBPCR_INCR_MASK		(1 << 27)

+#define CPM_USBPCR_CLK12_EN		(1 << 26)

+#define CPM_USBPCR_COMMONONN		(1 << 25)

+#define CPM_USBPCR_VBUSVLDEXT		(1 << 24)

+#define CPM_USBPCR_VBUSVLDEXTSEL	(1 << 23)

+#define CPM_USBPCR_POR			(1 << 22)

+#define CPM_USBPCR_SIDDQ		(1 << 21)

+#define CPM_USBPCR_OTG_DISABLE		(1 << 20)

+#define CPM_USBPCR_COMPDISTUNE_BIT	17

+#define CPM_USBPCR_COMPDISTUNE_MASK	(0x07 << COMPDISTUNE_BIT)

+#define CPM_USBPCR_OTGTUNE_BIT		14

+#define CPM_USBPCR_OTGTUNE_MASK		(0x07 << OTGTUNE_BIT)

+#define CPM_USBPCR_SQRXTUNE_BIT		11

+#define CPM_USBPCR_SQRXTUNE_MASK	(0x7x << SQRXTUNE_BIT)

+#define CPM_USBPCR_TXFSLSTUNE_BIT	7

+#define CPM_USBPCR_TXFSLSTUNE_MASK	(0x0f << TXFSLSTUNE_BIT)

+#define CPM_USBPCR_TXPREEMPHTUNE	(1 << 6)

+#define CPM_USBPCR_TXRISETUNE_BIT	4

+#define CPM_USBPCR_TXRISETUNE_MASK	(0x03 << TXRISETUNE_BIT)

+#define CPM_USBPCR_TXVREFTUNE_BIT	0

+#define CPM_USBPCR_TXVREFTUNE_MASK	(0x0f << TXVREFTUNE_BIT)

+

+/* USB reset detect timer register */

+#define CPM_USBRDT_VBFIL_LD_EN		(1 << 25)

+#define CPM_USBRDT_IDDIG_EN		(1 << 24)

+#define CPM_USBRDT_IDDIG_REG		(1 << 23)

+#define CPM_USBRDT_USBRDT_BIT		0

+#define CPM_USBRDT_USBRDT_MASK		(0x7fffff << CPM_USBRDT_USBRDT_BIT)

+

+/* USB OTG PHY clock divider register */

+#define CPM_USBCDR_UCS			(1 << 31)

+#define CPM_USBCDR_UPCS			(1 << 30)

+#define CPM_USBCDR_OTGDIV_BIT		0

+#define CPM_USBCDR_OTGDIV_MASK		(0x3f << CPM_USBCDR_OTGDIV_BIT)

+

+/* I2S device clock divider register */

+#define CPM_I2SCDR_I2CS			(1 << 31)

+#define CPM_I2SCDR_I2PCS		(1 << 30)

+#define CPM_I2SCDR_I2SDIV_BIT		0

+#define CPM_I2SCDR_I2SDIV_MASK		(0x1f << CPM_I2SCDR_I2SDIV_BIT)

+

+/* LCD pix clock divider register */

+#define CPM_LPCDR_LSCS			(1 << 31)

+#define CPM_LPCDR_LTCS			(1 << 30)

+#define CPM_LPCDR_LPCS			(1 << 29)

+#define CPM_LPCDR_PIXDIV_BIT		0

+#define CPM_LPCDR_PIXDIV_MASK		(0x7ff << CPM_LPCDR_PIXDIV_BIT)

+

+/* MSC clock divider register */

+#define CPM_MSCCDR_MCS			(1 << 31)

+#define CPM_MSCCDR_MSCDIV_BIT		0

+#define CPM_MSCCDR_MSCDIV_MASK		(0x1f << CPM_MSCCDR_MSCDIV_BIT)

+

+/* UHC 48M clock divider register */

+#define CPM_UHCCDR_UHPCS		(1 << 31)

+#define CPM_UHCCDR_UHCDIV_BIT		0

+#define CPM_UHCCDR_UHCDIV_MASK		(0x0f << CPM_UHCCDR_UHCDIV_BIT)

+

+/* SSI clock divider register */

+#define CPM_SSICDR_SCS			(1 << 31)

+#define CPM_SSICDR_SSIDIV_BIT		0

+#define CPM_SSICDR_SSIDIV_MASK		(0x0f << CPM_SSICDR_SSIDIV_BIT)

+

+/* CIM MCLK clock divider register */

+#define CPM_CIMCDR_CIMDIV_BIT		0

+#define CPM_CIMCDR_CIMDIV_MASK		(0xff << CPM_CIMCDR_CIMDIV_BIT)

+

+/* GPS clock divider register */

+#define CPM_GPSCDR_GPCS			(1 << 31)

+#define CPM_GPSCDR_GPSDIV_BIT		0

+#define CPM_GSPCDR_GPSDIV_MASK		(0x0f << CPM_GPSCDR_GPSDIV_BIT)

+

+/* PCM device clock divider register */

+#define CPM_PCMCDR_PCMS			(1 << 31)

+#define CPM_PCMCDR_PCMPCS		(1 << 30)

+#define CPM_PCMCDR_PCMDIV_BIT		0

+#define CPM_PCMCDR_PCMDIV_MASK		(0x1ff << CPM_PCMCDR_PCMDIV_BIT)

+

+/* GPU clock divider register */

+#define CPM_GPUCDR_GPCS			(1 << 31)

+#define CPM_GPUCDR_GPUDIV_BIT		0

+#define CPM_GPUCDR_GPUDIV_MASK		(0x07 << CPM_GPUCDR_GPUDIV_BIT)

+

+/* Low power control register*/

+#define CPM_LCR_PDAHB1			(1 << 30)

+#define CPM_LCR_VBATIR			(1 << 29)

+#define CPM_LCR_PDGPS			(1 << 28)

+#define CPM_LCR_PDAHB1S			(1 << 26)

+#define CPM_LCR_PDGPSS			(1 << 24)

+#define CPM_LCR_PTS_BIT			8

+#define CPM_LCR_PTS_MASK		(0xfff << CPM_LCR_PTS_BIT)

+#define CPM_LCR_DOZE_DUTY_BIT		3

+#define CPM_LCR_DOZE_DUTY_MASK		(0x1f << CPM_LCR_DOZE_DUTY_BIT)

+#define CPM_LCR_DOZE_ON			(1 << 2)

+#define CPM_LCR_LPM_BIT			0

+#define CPM_LCR_LPM_MASK		(0x3 << CPM_LCR_LPM_BIT)

+  #define CPM_LCR_LPM_IDLE		(0x0 << CPM_LCR_LPM_BIT)

+  #define CPM_LCR_LPM_SLEEP		(0x1 << CPM_LCR_LPM_BIT)

+

+/* Clock gate register 0 */

+#define CPM_CLKGR0_EMC			(1 << 31)

+#define CPM_CLKGR0_DDR			(1 << 30)

+#define CPM_CLKGR0_IPU			(1 << 29)

+#define CPM_CLKGR0_LCD			(1 << 28)

+#define CPM_CLKGR0_TVE			(1 << 27)

+#define CPM_CLKGR0_CIM			(1 << 26)

+#define CPM_CLKGR0_MDMA			(1 << 25)

+#define CPM_CLKGR0_UHC			(1 << 24)

+#define CPM_CLKGR0_MAC			(1 << 23)

+#define CPM_CLKGR0_GPS			(1 << 22)

+#define CPM_CLKGR0_DMAC			(1 << 21)

+#define CPM_CLKGR0_SSI2			(1 << 20)

+#define CPM_CLKGR0_SSI1			(1 << 19)

+#define CPM_CLKGR0_UART3		(1 << 18)

+#define CPM_CLKGR0_UART2		(1 << 17)

+#define CPM_CLKGR0_UART1		(1 << 16)

+#define CPM_CLKGR0_UART0		(1 << 15)

+#define CPM_CLKGR0_SADC			(1 << 14)

+#define CPM_CLKGR0_KBC			(1 << 13)

+#define CPM_CLKGR0_MSC2			(1 << 12)

+#define CPM_CLKGR0_MSC1			(1 << 11)

+#define CPM_CLKGR0_OWI			(1 << 10)

+#define CPM_CLKGR0_TSSI			(1 << 9)

+#define CPM_CLKGR0_AIC			(1 << 8)

+#define CPM_CLKGR0_SCC			(1 << 7)

+#define CPM_CLKGR0_I2C1			(1 << 6)

+#define CPM_CLKGR0_I2C0			(1 << 5)

+#define CPM_CLKGR0_SSI0			(1 << 4)

+#define CPM_CLKGR0_MSC0			(1 << 3)

+#define CPM_CLKGR0_OTG			(1 << 2)

+#define CPM_CLKGR0_BCH			(1 << 1)

+#define CPM_CLKGR0_NEMC			(1 << 0)

+

+/* Oscillator and Power Control Register */

+#define CPM_OPCR_O1ST_BIT		8

+#define CPM_OPCR_O1ST_MASK		(0xff << CPM_OPCR_O1ST_BIT)

+#define CPM_OPCR_UDCPHY_ENABLE		(1 << 7)

+#define CPM_OPCR_GPSEN			(1 << 6)

+#define CPM_OPCR_UHCPHY_DISABLE		(1 << 5)

+#define CPM_OPCR_OSC_ENABLE		(1 << 4)

+#define CPM_OPCR_PD			(1 << 3)

+#define CPM_OPCR_ERCS           	(1 << 2) /* EXCLK/512 clock and RTCLK clock selection */

+

+/* Clock gate register 1 */

+#define CPM_CLKGR1_GPU			(1 << 9)

+#define CPM_CLKGR1_PCM			(1 << 8)

+#define CPM_CLKGR1_AHB1			(1 << 7)

+#define CPM_CLKGR1_CABAC		(1 << 6)

+#define CPM_CLKGR1_SRAM			(1 << 5)

+#define CPM_CLKGR1_DCT			(1 << 4)

+#define CPM_CLKGR1_ME			(1 << 3)

+#define CPM_CLKGR1_DBLK			(1 << 2)

+#define CPM_CLKGR1_MC			(1 << 1)

+#define CPM_CLKGR1_BDMA			(1 << 0)

+

+

+#ifndef __MIPS_ASSEMBLER

+

+#define __cpm_get_pllm() \

+	((REG_CPM_CPPCR & CPM_CPPCR_PLLM_MASK) >> CPM_CPPCR_PLLM_BIT)

+#define __cpm_get_plln() \

+	((REG_CPM_CPPCR & CPM_CPPCR_PLLN_MASK) >> CPM_CPPCR_PLLN_BIT)

+#define __cpm_get_pllod() \

+	((REG_CPM_CPPCR & CPM_CPPCR_PLLOD_MASK) >> CPM_CPPCR_PLLOD_BIT)

+

+#define __cpm_get_pll1m() \

+	((REG_CPM_CPPCR1 & CPM_CPPCR1_PLL1M_MASK) >> CPM_CPPCR1_PLL1M_BIT)

+#define __cpm_get_pll1n() \

+	((REG_CPM_CPPCR1 & CPM_CPPCR1_PLL1N_MASK) >> CPM_CPPCR1_PLL1N_BIT)

+#define __cpm_get_pll1od() \

+	((REG_CPM_CPPCR1 & CPM_CPPCR1_PLL1OD_MASK) >> CPM_CPPCR1_PLL1OD_BIT)

+

+#define __cpm_get_cdiv() \

+	((REG_CPM_CPCCR & CPM_CPCCR_CDIV_MASK) >> CPM_CPCCR_CDIV_BIT)

+#define __cpm_get_hdiv() \

+	((REG_CPM_CPCCR & CPM_CPCCR_HDIV_MASK) >> CPM_CPCCR_HDIV_BIT)

+#define __cpm_get_h2div() \

+	((REG_CPM_CPCCR & CPM_CPCCR_H2DIV_MASK) >> CPM_CPCCR_H2DIV_BIT)

+#define __cpm_get_otgdiv() \

+	((REG_CPM_USBCDR & CPM_USBCDR_OTGDIV_MASK) >> CPM_USBCDR_OTGDIV_BIT)

+#define __cpm_get_pdiv() \

+	((REG_CPM_CPCCR & CPM_CPCCR_PDIV_MASK) >> CPM_CPCCR_PDIV_BIT)

+#define __cpm_get_mdiv() \

+	((REG_CPM_CPCCR & CPM_CPCCR_MDIV_MASK) >> CPM_CPCCR_MDIV_BIT)

+#define __cpm_get_sdiv() \

+	((REG_CPM_CPCCR & CPM_CPCCR_SDIV_MASK) >> CPM_CPCCR_SDIV_BIT)

+#define __cpm_get_i2sdiv() \

+	((REG_CPM_I2SCDR & CPM_I2SCDR_I2SDIV_MASK) >> CPM_I2SCDR_I2SDIV_BIT)

+#define __cpm_get_pixdiv() \

+	((REG_CPM_LPCDR & CPM_LPCDR_PIXDIV_MASK) >> CPM_LPCDR_PIXDIV_BIT)

+#define __cpm_get_mscdiv() \

+	((REG_CPM_MSCCDR & CPM_MSCCDR_MSCDIV_MASK) >> CPM_MSCCDR_MSCDIV_BIT)

+

+/*

+#define __cpm_get_mscdiv(n) \

+	((REG_CPM_MSCCDR(n) & CPM_MSCCDR_MSCDIV_MASK) >> CPM_MSCCDR_MSCDIV_BIT)

+*/

+#define __cpm_get_ssidiv() \

+	((REG_CPM_SSICCDR & CPM_SSICDR_SSICDIV_MASK) >> CPM_SSICDR_SSIDIV_BIT)

+#define __cpm_get_pcmdiv() \

+	((REG_CPM_PCMCDR & CPM_PCMCDR_PCMCD_MASK) >> CPM_PCMCDR_PCMCD_BIT)

+#define __cpm_get_pll1div() \

+	((REG_CPM_CPPCR1 & CPM_CPCCR1_P1SDIV_MASK) >> CPM_CPCCR1_P1SDIV_BIT)

+

+#define __cpm_set_cdiv(v) \

+	(REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_CDIV_MASK) | ((v) << (CPM_CPCCR_CDIV_BIT)))

+#define __cpm_set_hdiv(v) \

+	(REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_HDIV_MASK) | ((v) << (CPM_CPCCR_HDIV_BIT)))

+#define __cpm_set_pdiv(v) \

+	(REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_PDIV_MASK) | ((v) << (CPM_CPCCR_PDIV_BIT)))

+#define __cpm_set_mdiv(v) \

+	(REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_MDIV_MASK) | ((v) << (CPM_CPCCR_MDIV_BIT)))

+#define __cpm_set_h1div(v) \

+	(REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_H1DIV_MASK) | ((v) << (CPM_CPCCR_H1DIV_BIT)))

+#define __cpm_set_udiv(v) \

+	(REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_UDIV_MASK) | ((v) << (CPM_CPCCR_UDIV_BIT)))

+#define __cpm_set_i2sdiv(v) \

+	(REG_CPM_I2SCDR = (REG_CPM_I2SCDR & ~CPM_I2SCDR_I2SDIV_MASK) | ((v) << (CPM_I2SCDR_I2SDIV_BIT)))

+#define __cpm_set_pixdiv(v) \

+	(REG_CPM_LPCDR = (REG_CPM_LPCDR & ~CPM_LPCDR_PIXDIV_MASK) | ((v) << (CPM_LPCDR_PIXDIV_BIT)))

+#define __cpm_set_mscdiv(v) \

+	(REG_CPM_MSCCDR = (REG_CPM_MSCCDR & ~CPM_MSCCDR_MSCDIV_MASK) | ((v) << (CPM_MSCCDR_MSCDIV_BIT)))

+#define __cpm_set_ssidiv(v) \

+	(REG_CPM_SSICDR = (REG_CPM_SSICDR & ~CPM_SSICDR_SSIDIV_MASK) | ((v) << (CPM_SSICDR_SSIDIV_BIT)))

+#define __cpm_set_pcmdiv(v) \

+	(REG_CPM_PCMCDR = (REG_CPM_PCMCDR & ~CPM_PCMCDR_PCMDIV_MASK) | ((v) << (CPM_PCMCDR_PCMDIV_BIT)))

+#define __cpm_set_pll1div(v) \

+	(REG_CPM_CPPCR1 = (REG_CPM_CPPCR1 & ~CPM_CPCCR1_P1SDIV_MASK) | ((v) << (CPM_CPCCR1_P1SDIV_BIT)))

+

+#define __cpm_select_i2sclk_pll1() 	(REG_CPM_I2SCDR |= CPM_I2SCDR_I2PCS)

+#define __cpm_select_i2sclk_pll0()	(REG_CPM_I2SCDR &= ~CPM_I2SCDR_I2PCS)

+#define __cpm_select_otgclk_pll1() 	(REG_CPM_USBCDR |= CPM_USBCDR_UPCS)

+#define __cpm_select_otgclk_pll0()	(REG_CPM_USBCDR &= ~CPM_USBCDR_UPCS)

+#define __cpm_select_lcdpclk_pll1() 	(REG_CPM_LPCDR |= CPM_LPCDR_LPCS)

+#define __cpm_select_lcdpclk_pll0()	(REG_CPM_LPCDR &= ~CPM_LPCDR_LPCS)

+#define __cpm_select_uhcclk_pll1() 	(REG_CPM_UHCCDR |= CPM_UHCCDR_UHPCS)

+#define __cpm_select_uhcclk_pll0()	(REG_CPM_UHCCDR &= ~CPM_UHCCDR_UHPCS)

+#define __cpm_select_gpsclk_pll1() 	(REG_CPM_GPSCDR |= CPM_GPSCDR_GPCS)

+#define __cpm_select_gpsclk_pll0()	(REG_CPM_GPSCDR &= ~CPM_GPSCDR_GPCS)

+#define __cpm_select_pcmclk_pll1() 	(REG_CPM_PCMCDR |= CPM_PCMCDR_PCMPCS)

+#define __cpm_select_pcmclk_pll0()	(REG_CPM_PCMCDR &= ~CPM_PCMCDR_PCMPCS)

+#define __cpm_select_gpuclk_pll1() 	(REG_CPM_GPUCDR |= CPM_GPUCDR_GPCS)

+#define __cpm_select_gpuclk_pll0()	(REG_CPM_GPUCDR &= ~CPM_GPUCDR_GPCS)

+#define __cpm_select_clk_pll1() 	(REG_CPM_CDR |= CPM_CDR_PCS)

+#define __cpm_select_clk_pll0()	(REG_CPM_CDR &= ~CPM_CDR_PCS)

+

+

+#define __cpm_select_pcmclk_pll() 	(REG_CPM_PCMCDR |= CPM_PCMCDR_PCMS)

+#define __cpm_select_pcmclk_exclk() 	(REG_CPM_PCMCDR &= ~CPM_PCMCDR_PCMS)

+#define __cpm_select_pixclk_ext()	(REG_CPM_LPCDR |= CPM_LPCDR_LPCS)

+#define __cpm_select_pixclk_pll()	(REG_CPM_LPCDR &= ~CPM_LPCDR_LPCS)

+#define __cpm_select_tveclk_exclk()	(REG_CPM_LPCDR |= CPM_CPCCR_LSCS)

+#define __cpm_select_tveclk_pll()	(REG_CPM_LPCDR &= ~CPM_LPCDR_LSCS)

+#define __cpm_select_pixclk_lcd()	(REG_CPM_LPCDR &= ~CPM_LPCDR_LTCS)

+#define __cpm_select_pixclk_tve()	(REG_CPM_LPCDR |= CPM_LPCDR_LTCS)

+#define __cpm_select_i2sclk_exclk()	(REG_CPM_I2SCDR &= ~CPM_I2SCDR_I2CS)

+#define __cpm_select_i2sclk_pll()	(REG_CPM_I2SCDR |= CPM_I2SCDR_I2CS)

+//#define __cpm_select_usbclk_exclk()	(REG_CPM_CPCCR &= ~CPM_CPCCR_UCS)

+//#define __cpm_select_usbclk_pll()	(REG_CPM_CPCCR |= CPM_CPCCR_UCS)

+

+#define __cpm_enable_cko()

+#define __cpm_exclk_direct()		(REG_CPM_CPCCR &= ~CPM_CPCCR_ECS)

+#define __cpm_exclk_div2()             	(REG_CPM_CPCCR |= CPM_CPCCR_ECS)

+#define __cpm_enable_pll_change()	(REG_CPM_CPCCR |= CPM_CPCCR_CE)

+

+#define __cpm_pllout_div2()		(REG_CPM_CPCCR &= ~CPM_CPCCR_PCS)

+#define __cpm_pll_enable()		(REG_CPM_CPPCR |= CPM_CPPCR_PLLEN)

+

+#define __cpm_pll1_enable()		(REG_CPM_CPPCR1 |= CPM_CPPCR1_PLL1EN)

+

+#define __cpm_pll_is_off()		(REG_CPM_CPPSR & CPM_CPPSR_PLLOFF)

+#define __cpm_pll_is_on()		(REG_CPM_CPPSR & CPM_CPPSR_PLLON)

+#define __cpm_pll_bypass()		(REG_CPM_CPPSR |= CPM_CPPSR_PLLBP)

+

+#define __cpm_get_cclk_doze_duty() \

+	((REG_CPM_LCR & CPM_LCR_DOZE_DUTY_MASK) >> CPM_LCR_DOZE_DUTY_BIT)

+#define __cpm_set_cclk_doze_duty(v) \

+	(REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_DOZE_DUTY_MASK) | ((v) << (CPM_LCR_DOZE_DUTY_BIT)))

+

+#define __cpm_doze_mode()		(REG_CPM_LCR |= CPM_LCR_DOZE_ON)

+#define __cpm_idle_mode() \

+	(REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_LPM_MASK) | CPM_LCR_LPM_IDLE)

+#define __cpm_sleep_mode() \

+	(REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_LPM_MASK) | CPM_LCR_LPM_SLEEP)

+

+#define __cpm_stop_all() 	\

+	do {\

+		(REG_CPM_CLKGR0 = 0xffffffff);\

+		(REG_CPM_CLKGR1 = 0x3ff);\

+	}while(0)

+#define __cpm_stop_emc()	(REG_CPM_CLKGR0 |= CPM_CLKGR0_EMC)

+#define __cpm_stop_ddr()	(REG_CPM_CLKGR0 |= CPM_CLKGR0_DDR)

+#define __cpm_stop_ipu()	(REG_CPM_CLKGR0 |= CPM_CLKGR0_IPU)

+#define __cpm_stop_lcd()	(REG_CPM_CLKGR0 |= CPM_CLKGR0_LCD)

+#define __cpm_stop_tve()	(REG_CPM_CLKGR0 |= CPM_CLKGR0_TVE)

+#define __cpm_stop_Cim()	(REG_CPM_CLKGR0 |= CPM_CLKGR0_CIM)

+#define __cpm_stop_mdma()	(REG_CPM_CLKGR0 |= CPM_CLKGR0_MDMA)

+#define __cpm_stop_uhc()	(REG_CPM_CLKGR0 |= CPM_CLKGR0_UHC)

+#define __cpm_stop_mac()	(REG_CPM_CLKGR0 |= CPM_CLKGR0_MAC)

+#define __cpm_stop_gps()	(REG_CPM_CLKGR0 |= CPM_CLKGR0_GPS)

+#define __cpm_stop_dmac()	(REG_CPM_CLKGR0 |= CPM_CLKGR0_DMAC)

+#define __cpm_stop_ssi2()	(REG_CPM_CLKGR0 |= CPM_CLKGR0_SSI2)

+#define __cpm_stop_ssi1()	(REG_CPM_CLKGR0 |= CPM_CLKGR0_SSI1)

+#define __cpm_stop_uart3()	(REG_CPM_CLKGR0 |= CPM_CLKGR0_UART3)

+#define __cpm_stop_uart2()	(REG_CPM_CLKGR0 |= CPM_CLKGR0_UART2)

+#define __cpm_stop_uart1()	(REG_CPM_CLKGR0 |= CPM_CLKGR0_UART1)

+#define __cpm_stop_uart0()	(REG_CPM_CLKGR0 |= CPM_CLKGR0_UART0)

+#define __cpm_stop_sadc()	(REG_CPM_CLKGR0 |= CPM_CLKGR0_SADC)

+#define __cpm_stop_kbc()	(REG_CPM_CLKGR0 |= CPM_CLKGR0_KBC)

+#define __cpm_stop_msc2()	(REG_CPM_CLKGR0 |= CPM_CLKGR0_MSC2)

+#define __cpm_stop_msc1()	(REG_CPM_CLKGR0 |= CPM_CLKGR0_MSC1)

+#define __cpm_stop_owi()	(REG_CPM_CLKGR0 |= CPM_CLKGR0_OWI)

+#define __cpm_stop_tssi()	(REG_CPM_CLKGR0 |= CPM_CLKGR0_TSSI)

+#define __cpm_stop_aic()	(REG_CPM_CLKGR0 |= CPM_CLKGR0_AIC)

+#define __cpm_stop_scc()	(REG_CPM_CLKGR0 |= CPM_CLKGR0_SCC)

+#define __cpm_stop_i2c0()	(REG_CPM_CLKGR0 |= CPM_CLKGR0_I2C1)

+#define __cpm_stop_i2c1()	(REG_CPM_CLKGR0 |= CPM_CLKGR0_I2C0)

+#define __cpm_stop_ssi0()	(REG_CPM_CLKGR0 |= CPM_CLKGR0_SSI0)

+#define __cpm_stop_msc0()	(REG_CPM_CLKGR0 |= CPM_CLKGR0_MSC0)

+#define __cpm_stop_otg()	(REG_CPM_CLKGR0 |= CPM_CLKGR0_OTG)

+#define __cpm_stop_bch()	(REG_CPM_CLKGR0 |= CPM_CLKGR0_BCH)

+#define __cpm_stop_nemc()	(REG_CPM_CLKGR0 |= CPM_CLKGR0_NEMC)

+#define __cpm_stop_gpu()	(REG_CPM_CLKGR1 |= CPM_CLKGR0_GPU)

+#define __cpm_stop_pcm()	(REG_CPM_CLKGR1 |= CPM_CLKGR0_PCM)

+#define __cpm_stop_ahb1()	(REG_CPM_CLKGR1 |= CPM_CLKGR0_AHB1)

+#define __cpm_stop_cabac()	(REG_CPM_CLKGR1 |= CPM_CLKGR0_CABAC)

+#define __cpm_stop_sram()	(REG_CPM_CLKGR1 |= CPM_CLKGR0_SRAM)

+#define __cpm_stop_dct()	(REG_CPM_CLKGR1 |= CPM_CLKGR0_DCT)

+#define __cpm_stop_me()		(REG_CPM_CLKGR1 |= CPM_CLKGR0_ME)

+#define __cpm_stop_dblk()	(REG_CPM_CLKGR1 |= CPM_CLKGR0_DBLK)

+#define __cpm_stop_mc()		(REG_CPM_CLKGR1 |= CPM_CLKGR0_MC)

+#define __cpm_stop_bdma()	(REG_CPM_CLKGR1 |= CPM_CLKGR1_BDMA)

+

+#define __cpm_start_all() 	\

+	do {\

+		REG_CPM_CLKGR0 = 0x0;\

+		REG_CPM_CLKGR1 = 0x0;\

+	} while(0)

+#define __cpm_start_emc()	(REG_CPM_CLKGR0 &= ~CPM_CLKGR0_EMC)

+#define __cpm_start_ddr()	(REG_CPM_CLKGR0 &= ~CPM_CLKGR0_DDR)

+#define __cpm_start_ipu()	(REG_CPM_CLKGR0 &= ~CPM_CLKGR0_IPU)

+#define __cpm_start_lcd()	(REG_CPM_CLKGR0 &= ~CPM_CLKGR0_LCD)

+#define __cpm_start_tve()	(REG_CPM_CLKGR0 &= ~CPM_CLKGR0_TVE)

+#define __cpm_start_Cim()	(REG_CPM_CLKGR0 &= ~CPM_CLKGR0_CIM)

+#define __cpm_start_mdma()	(REG_CPM_CLKGR0 &= ~CPM_CLKGR0_MDMA)

+#define __cpm_start_uhc()	(REG_CPM_CLKGR0 &= ~CPM_CLKGR0_UHC)

+#define __cpm_start_mac()	(REG_CPM_CLKGR0 &= ~CPM_CLKGR0_MAC)

+#define __cpm_start_gps()	(REG_CPM_CLKGR0 &= ~CPM_CLKGR0_GPS)

+#define __cpm_start_dmac()	(REG_CPM_CLKGR0 &= ~CPM_CLKGR0_DMAC)

+#define __cpm_start_ssi2()	(REG_CPM_CLKGR0 &= ~CPM_CLKGR0_SSI2)

+#define __cpm_start_ssi1()	(REG_CPM_CLKGR0 &= ~CPM_CLKGR0_SSI1)

+#define __cpm_start_uart3()	(REG_CPM_CLKGR0 &= ~CPM_CLKGR0_UART3)

+#define __cpm_start_uart2()	(REG_CPM_CLKGR0 &= ~CPM_CLKGR0_UART2)

+#define __cpm_start_uart1()	(REG_CPM_CLKGR0 &= ~CPM_CLKGR0_UART1)

+#define __cpm_start_uart0()	(REG_CPM_CLKGR0 &= ~CPM_CLKGR0_UART0)

+#define __cpm_start_sadc()	(REG_CPM_CLKGR0 &= ~CPM_CLKGR0_SADC)

+#define __cpm_start_kbc()	(REG_CPM_CLKGR0 &= ~CPM_CLKGR0_KBC)

+#define __cpm_start_msc2()	(REG_CPM_CLKGR0 &= ~CPM_CLKGR0_MSC2)

+#define __cpm_start_msc1()	(REG_CPM_CLKGR0 &= ~CPM_CLKGR0_MSC1)

+#define __cpm_start_owi()	(REG_CPM_CLKGR0 &= ~CPM_CLKGR0_OWI)

+#define __cpm_start_tssi()	(REG_CPM_CLKGR0 &= ~CPM_CLKGR0_TSSI)

+#define __cpm_start_aic()	(REG_CPM_CLKGR0 &= ~CPM_CLKGR0_AIC)

+#define __cpm_start_scc()	(REG_CPM_CLKGR0 &= ~CPM_CLKGR0_SCC)

+#define __cpm_start_i2c0()	(REG_CPM_CLKGR0 &= ~CPM_CLKGR0_I2C1)

+#define __cpm_start_i2c1()	(REG_CPM_CLKGR0 &= ~CPM_CLKGR0_I2C0)

+#define __cpm_start_ssi0()	(REG_CPM_CLKGR0 &= ~CPM_CLKGR0_SSI0)

+#define __cpm_start_msc0()	(REG_CPM_CLKGR0 &= ~CPM_CLKGR0_MSC0)

+#define __cpm_start_otg()	(REG_CPM_CLKGR0 &= ~CPM_CLKGR0_OTG)

+#define __cpm_start_bch()	(REG_CPM_CLKGR0 &= ~CPM_CLKGR0_BCH)

+#define __cpm_start_nemc()	(REG_CPM_CLKGR0 &= ~CPM_CLKGR0_NEMC)

+#define __cpm_start_gpu()	(REG_CPM_CLKGR1 &= ~CPM_CLKGR1_GPU)

+#define __cpm_start_pcm()	(REG_CPM_CLKGR1 &= ~CPM_CLKGR1_PCM)

+#define __cpm_start_ahb1()	(REG_CPM_CLKGR1 &= ~CPM_CLKGR1_AHB1)

+#define __cpm_start_cabac()	(REG_CPM_CLKGR1 &= ~CPM_CLKGR1_CABAC)

+#define __cpm_start_sram()	(REG_CPM_CLKGR1 &= ~CPM_CLKGR1_SRAM)

+#define __cpm_start_dct()	(REG_CPM_CLKGR1 &= ~CPM_CLKGR1_DCT)

+#define __cpm_start_me()		(REG_CPM_CLKGR1 &= ~CPM_CLKGR0_ME)

+#define __cpm_start_dblk()	(REG_CPM_CLKGR1 &= ~CPM_CLKGR0_DBLK)

+#define __cpm_start_mc()		(REG_CPM_CLKGR1 &= ~CPM_CLKGR0_MC)

+#define __cpm_start_bdma()	(REG_CPM_CLKGR1 &= ~CPM_CLKGR1_BDMA)

+

+#define __cpm_get_o1st() \

+	((REG_CPM_OPCR & CPM_OPCR_O1ST_MASK) >> CPM_OPCR_O1ST_BIT)

+#define __cpm_set_o1st(v) \

+	(REG_CPM_OPCR = (REG_CPM_OPCR & ~CPM_OPCR_O1ST_MASK) | ((v) << (CPM_OPCR_O1ST_BIT)))

+

+#define __cpm_suspend_otg_phy()		(REG_CPM_OPCR &= ~CPM_OPCR_UDCPHY_ENABLE)

+#define __cpm_enable_otg_phy()		(REG_CPM_OPCR |= CPM_OPCR_UDCPHY_ENABLE)

+

+#define __cpm_suspend_uhc_phy()		(REG_CPM_OPCR |= CPM_OPCR_UHCPHY_DISABLE)

+#define __cpm_enable_uhc_phy()		(REG_CPM_OPCR &= ~CPM_OPCR_UHCPHY_DISABLE)

+

+#define __cpm_suspend_uhcphy()  (REG_CPM_OPCR |= CPM_OPCR_UHCPHY_DISABLE)

+#define __cpm_suspend_gps()        (REG_CPM_OPCR &= ~CPM_OPCR_GPSEN)

+#define __cpm_suspend_udcphy()	(REG_CPM_OPCR &= ~CPM_OPCR_UDCPHY_ENABLE)

+#define __cpm_disable_osc_in_sleep()	(REG_CPM_OPCR &= ~CPM_OPCR_OSC_ENABLE)

+#define __cpm_enable_osc_in_sleep()	(REG_CPM_OPCR |= CPM_OPCR_OSC_ENABLE)

+#define __cpm_select_rtcclk_rtc()	(REG_CPM_OPCR |= CPM_OPCR_ERCS)

+#define __cpm_select_rtcclk_exclk()	(REG_CPM_OPCR &= ~CPM_OPCR_ERCS)

+

+void cpm_start_clock(clock_gate_module module_name);

+void cpm_stop_clock(clock_gate_module module_name);

+unsigned int cpm_set_clock(cgu_clock clock_name, unsigned int clock_hz);

+unsigned int cpm_get_clock(cgu_clock clock_name);

+unsigned int cpm_get_pllout(void);

+

+extern int jz_pm_init(void);

+

+#endif /* __MIPS_ASSEMBLER */

+

+#endif /* __JZ4770CPM_H__ */

+

diff --git a/arch/mips/include/asm/mach-jz4770/jz4770dbg.h b/arch/mips/include/asm/mach-jz4770/jz4770dbg.h
new file mode 100644
index 00000000000..b8d9ac44fb6
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4770/jz4770dbg.h
@@ -0,0 +1,30 @@
+#include <asm/mach-jz4770/regs.h>
+#include <asm/mach-jz4770/jz4770misc.h>
+#include <asm/mach-jz4770/jz4770gpio.h>
+#include <asm/mach-jz4770/jz4770uart.h>
+
+static void dserial_putc (const char c)
+{
+	volatile u8 *uart_lsr = (volatile u8 *)(UART2_BASE + OFF_LSR);
+	volatile u8 *uart_tdr = (volatile u8 *)(UART2_BASE + OFF_TDR);
+
+	if (c == '\n') dserial_putc ('\r');
+
+	/* Wait for fifo to shift out some bytes */
+	while ( !((*uart_lsr & (UART_LSR_TDRQ | UART_LSR_TEMT)) == 0x60) );
+
+	*uart_tdr = (u8)c;
+}
+
+static void dserial_puts (const char *s)
+{
+	while (*s) {
+		dserial_putc (*s++);
+	}
+}
+
+main()
+{
+	dserial_puts("\n");
+	return 0;
+}
diff --git a/arch/mips/include/asm/mach-jz4770/jz4770ddrc.h b/arch/mips/include/asm/mach-jz4770/jz4770ddrc.h
new file mode 100644
index 00000000000..5349da6afb1
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4770/jz4770ddrc.h
@@ -0,0 +1,345 @@
+/*

+ * linux/include/asm-mips/mach-jz4770/jz4770ddrc.h

+ *

+ * JZ4770 DDRC register definition.

+ *

+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

+ */

+

+#ifndef __JZ4770DDRC_H__

+#define __JZ4770DDRC_H__

+

+

+#define	DDRC_BASE	0xB3020000

+

+/*************************************************************************

+ * DDRC (DDR Controller)

+ *************************************************************************/

+#define DDRC_ST		(DDRC_BASE + 0x0) /* DDR Status Register */

+#define DDRC_CFG	(DDRC_BASE + 0x4) /* DDR Configure Register */

+#define DDRC_CTRL	(DDRC_BASE + 0x8) /* DDR Control Register */

+#define DDRC_LMR	(DDRC_BASE + 0xc) /* DDR Load-Mode-Register */

+#define DDRC_TIMING1	(DDRC_BASE + 0x10) /* DDR Timing Config Register 1 */

+#define DDRC_TIMING2	(DDRC_BASE + 0x14) /* DDR Timing Config Register 2 */

+#define DDRC_REFCNT	(DDRC_BASE + 0x18) /* DDR  Auto-Refresh Counter */

+#define DDRC_DQS	(DDRC_BASE + 0x1c) /* DDR DQS Delay Control Register */

+#define DDRC_DQS_ADJ	(DDRC_BASE + 0x20) /* DDR DQS Delay Adjust Register */

+#define DDRC_MMAP0	(DDRC_BASE + 0x24) /* DDR Memory Map Config Register */

+#define DDRC_MMAP1	(DDRC_BASE + 0x28) /* DDR Memory Map Config Register */

+

+/* DDRC Register */

+#define REG_DDRC_ST		REG32(DDRC_ST)

+#define REG_DDRC_CFG		REG32(DDRC_CFG)

+#define REG_DDRC_CTRL		REG32(DDRC_CTRL)

+#define REG_DDRC_LMR		REG32(DDRC_LMR)

+#define REG_DDRC_TIMING1	REG32(DDRC_TIMING1)

+#define REG_DDRC_TIMING2	REG32(DDRC_TIMING2)

+#define REG_DDRC_REFCNT		REG32(DDRC_REFCNT)

+#define REG_DDRC_DQS		REG32(DDRC_DQS)

+#define REG_DDRC_DQS_ADJ	REG32(DDRC_DQS_ADJ)

+#define REG_DDRC_MMAP0		REG32(DDRC_MMAP0)

+#define REG_DDRC_MMAP1		REG32(DDRC_MMAP1)

+

+/* DDRC Status Register */

+#define DDRC_ST_ENDIAN	(1 << 7) /* 0 Little data endian

+					    1 Big data endian */

+#define DDRC_ST_DPDN		(1 << 5) /* 0 DDR memory is NOT in deep-power-down state

+					    1 DDR memory is in deep-power-down state */

+#define DDRC_ST_PDN		(1 << 4) /* 0 DDR memory is NOT in power-down state

+					    1 DDR memory is in power-down state */

+#define DDRC_ST_AREF		(1 << 3) /* 0 DDR memory is NOT in auto-refresh state

+					    1 DDR memory is in auto-refresh state */

+#define DDRC_ST_SREF		(1 << 2) /* 0 DDR memory is NOT in self-refresh state

+					    1 DDR memory is in self-refresh state */

+#define DDRC_ST_CKE1		(1 << 1) /* 0 CKE1 Pin is low

+					    1 CKE1 Pin is high */

+#define DDRC_ST_CKE0		(1 << 0) /* 0 CKE0 Pin is low

+					    1 CKE0 Pin is high */

+

+/* DDRC Configure Register */

+#define DDRC_CFG_MSEL_BIT	16 /* Mask delay select */

+#define DDRC_CFG_MSEL_MASK	(0x3 << DDRC_CFG_MSEL_BIT)

+  #define DDRC_CFG_MSEL_0	(0 << DDRC_CFG_MSEL_BIT) /* 00 No delay */

+  #define DDRC_CFG_MSEL_1	(1 << DDRC_CFG_MSEL_BIT) /* 01 delay 1 tCK */

+  #define DDRC_CFG_MSEL_2	(2 << DDRC_CFG_MSEL_BIT) /* 10 delay 2 tCK */

+  #define DDRC_CFG_MSEL_3	(3 << DDRC_CFG_MSEL_BIT) /* 11 delay 3 tCK */

+

+#define DDRC_CFG_HL		(1 << 15) /* 0: no extra delay 1: one extra half tCK delay */

+

+#define DDRC_CFG_ROW1_BIT	27 /* Row Address width. */

+#define DDRC_CFG_COL1_BIT	25 /* Row Address width. */

+#define DDRC_CFG_BA1_BIT	(1 << 24)

+#define DDRC_CFG_IMBA_BIT	(1 << 23)

+#define DDRC_CFG_BTRUN		(1 << 21)

+

+#define DDRC_CFG_TYPE_BIT	12

+#define DDRC_CFG_TYPE_MASK	(0x7 << DDRC_CFG_TYPE_BIT)

+#define DDRC_CFG_TYPE_DDR1	(2 << DDRC_CFG_TYPE_BIT)

+#define DDRC_CFG_TYPE_MDDR	(3 << DDRC_CFG_TYPE_BIT)

+#define DDRC_CFG_TYPE_DDR2	(4 << DDRC_CFG_TYPE_BIT)

+

+#define DDRC_CFG_ROW_BIT	10 /* Row Address width. */

+#define DDRC_CFG_ROW_MASK	(0x3 << DDRC_CFG_ROW_BIT)

+  #define DDRC_CFG_ROW_13	(0 << DDRC_CFG_ROW_BIT) /* 13-bit row address is used */

+  #define DDRC_CFG_ROW_14	(1 << DDRC_CFG_ROW_BIT) /* 14-bit row address is used */

+

+#define DDRC_CFG_COL_BIT	8 /* Column Address width.

+				     Specify the Column address width of external DDR. */

+#define DDRC_CFG_COL_MASK	(0x3 << DDRC_CFG_COL_BIT)

+  #define DDRC_CFG_COL_9	(0 << DDRC_CFG_COL_BIT) /* 9-bit Column address is used */

+  #define DDRC_CFG_COL_10	(1 << DDRC_CFG_COL_BIT) /* 10-bit Column address is used */

+

+#define DDRC_CFG_CS1EN	(1 << 7) /* 0 DDR Pin CS1 un-used

+					    1 There're DDR memory connected to CS1 */

+#define DDRC_CFG_CS0EN	(1 << 6) /* 0 DDR Pin CS0 un-used

+					    1 There're DDR memory connected to CS0 */

+

+#define DDRC_CFG_TSEL_BIT	18 /* Read delay select */

+#define DDRC_CFG_TSEL_MASK	(0x3 << DDRC_CFG_TSEL_BIT)

+#define DDRC_CFG_TSEL_0	(0 << DDRC_CFG_TSEL_BIT) /* No delay */

+#define DDRC_CFG_TSEL_1	(1 << DDRC_CFG_TSEL_BIT) /* delay 1 tCK */

+#define DDRC_CFG_TSEL_2	(2 << DDRC_CFG_TSEL_BIT) /* delay 2 tCK */

+#define DDRC_CFG_TSEL_3	(3 << DDRC_CFG_TSEL_BIT) /* delay 3 tCK */

+

+#define DDRC_CFG_CL_BIT	2 /* CAS Latency */

+#define DDRC_CFG_CL_MASK	(0xf << DDRC_CFG_CL_BIT)

+#define DDRC_CFG_CL_3		(0 << DDRC_CFG_CL_BIT) /* CL = 3 tCK */

+#define DDRC_CFG_CL_4		(1 << DDRC_CFG_CL_BIT) /* CL = 4 tCK */

+#define DDRC_CFG_CL_5		(2 << DDRC_CFG_CL_BIT) /* CL = 5 tCK */

+#define DDRC_CFG_CL_6		(3 << DDRC_CFG_CL_BIT) /* CL = 6 tCK */

+

+#define DDRC_CFG_BA		(1 << 1) /* 0 4 bank device, Pin ba[1:0] valid, ba[2] un-used

+					    1 8 bank device, Pin ba[2:0] valid*/

+#define DDRC_CFG_DW		(1 << 0) /*0 External memory data width is 16-bit

+					   1 External memory data width is 32-bit */

+

+/* DDRC Control Register */

+#define DDRC_CTRL_ACTPD	(1 << 15) /* 0 Precharge all banks before entering power-down

+					     1 Do not precharge banks before entering power-down */

+#define DDRC_CTRL_PDT_BIT	12 /* Power-Down Timer */

+#define DDRC_CTRL_PDT_MASK	(0x7 << DDRC_CTRL_PDT_BIT)

+  #define DDRC_CTRL_PDT_DIS	(0 << DDRC_CTRL_PDT_BIT) /* power-down disabled */

+  #define DDRC_CTRL_PDT_8	(1 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 8 tCK idle */

+  #define DDRC_CTRL_PDT_16	(2 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 16 tCK idle */

+  #define DDRC_CTRL_PDT_32	(3 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 32 tCK idle */

+  #define DDRC_CTRL_PDT_64	(4 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 64 tCK idle */

+  #define DDRC_CTRL_PDT_128	(5 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 128 tCK idle */

+

+#define DDRC_CTRL_PRET_BIT	8 /* Precharge Timer */

+#define DDRC_CTRL_PRET_MASK	(0x7 << DDRC_CTRL_PRET_BIT) /*  */

+  #define DDRC_CTRL_PRET_DIS	(0 << DDRC_CTRL_PRET_BIT) /* PRET function Disabled */

+  #define DDRC_CTRL_PRET_8	(1 << DDRC_CTRL_PRET_BIT) /* Precharge active bank after 8 tCK idle */

+  #define DDRC_CTRL_PRET_16	(2 << DDRC_CTRL_PRET_BIT) /* Precharge active bank after 16 tCK idle */

+  #define DDRC_CTRL_PRET_32	(3 << DDRC_CTRL_PRET_BIT) /* Precharge active bank after 32 tCK idle */

+  #define DDRC_CTRL_PRET_64	(4 << DDRC_CTRL_PRET_BIT) /* Precharge active bank after 64 tCK idle */

+  #define DDRC_CTRL_PRET_128	(5 << DDRC_CTRL_PRET_BIT) /* Precharge active bank after 128 tCK idle */

+

+#define DDRC_CTRL_SR		(1 << 5) /* 1 Drive external DDR device entering self-refresh mode

+					    0 Drive external DDR device exiting self-refresh mode */

+#define DDRC_CTRL_UNALIGN	(1 << 4) /* 0 Disable unaligned transfer on AXI BUS

+					    1 Enable unaligned transfer on AXI BUS */

+#define DDRC_CTRL_ALH		(1 << 3) /* Advanced Latency Hiding:

+					    0 Disable ALH

+					    1 Enable ALH */

+#define DDRC_CTRL_RDC		(1 << 2) /* 0 dclk clock frequency is lower than 60MHz

+					    1 dclk clock frequency is higher than 60MHz */

+#define DDRC_CTRL_CKE		(1 << 1) /* 0 Not set CKE Pin High

+					    1 Set CKE Pin HIGH */

+#define DDRC_CTRL_RESET	(1 << 0) /* 0 End resetting ddrc_controller

+					    1 Resetting ddrc_controller */

+

+/* DDRC Load-Mode-Register */

+#define DDRC_LMR_DDR_ADDR_BIT	16 /* When performing a DDR command, DDRC_ADDR[13:0]

+					      corresponding to external DDR address Pin A[13:0] */

+#define DDRC_LMR_DDR_ADDR_MASK	(0xff << DDRC_LMR_DDR_ADDR_BIT)

+

+#define DDRC_LMR_BA_BIT		8 /* When performing a DDR command, BA[2:0]

+				     corresponding to external DDR address Pin BA[2:0]. */

+#define DDRC_LMR_BA_MASK	(0x7 << DDRC_LMR_BA_BIT)

+  /* For DDR2 */

+  #define DDRC_LMR_BA_MRS	(0 << DDRC_LMR_BA_BIT) /* Mode Register set */

+  #define DDRC_LMR_BA_EMRS1	(1 << DDRC_LMR_BA_BIT) /* Extended Mode Register1 set */

+  #define DDRC_LMR_BA_EMRS2	(2 << DDRC_LMR_BA_BIT) /* Extended Mode Register2 set */

+  #define DDRC_LMR_BA_EMRS3	(3 << DDRC_LMR_BA_BIT) /* Extended Mode Register3 set */

+  /* For mobile DDR */

+  #define DDRC_LMR_BA_M_MRS	(0 << DDRC_LMR_BA_BIT) /* Mode Register set */

+  #define DDRC_LMR_BA_M_EMRS	(2 << DDRC_LMR_BA_BIT) /* Extended Mode Register set */

+  #define DDRC_LMR_BA_M_SR	(1 << DDRC_LMR_BA_BIT) /* Status Register set */

+

+#define DDRC_LMR_CMD_BIT	4

+#define DDRC_LMR_CMD_MASK	(0x3 << DDRC_LMR_CMD_BIT)

+  #define DDRC_LMR_CMD_PREC	(0 << DDRC_LMR_CMD_BIT)/* Precharge one bank/All banks */

+  #define DDRC_LMR_CMD_AUREF	(1 << DDRC_LMR_CMD_BIT)/* Auto-Refresh */

+  #define DDRC_LMR_CMD_LMR	(2 << DDRC_LMR_CMD_BIT)/* Load Mode Register */

+

+#define DDRC_LMR_START		(1 << 0) /* 0 No command is performed

+						    1 On the posedge of START, perform a command

+						    defined by CMD field */

+

+/* DDRC Mode Register Set */

+#define DDR_MRS_PD_BIT		(1 << 10) /* Active power down exit time */

+#define DDR_MRS_PD_MASK		(1 << DDR_MRS_PD_BIT) 

+  #define DDR_MRS_PD_FAST_EXIT	(0 << 10)

+  #define DDR_MRS_PD_SLOW_EXIT	(1 << 10)

+#define DDR_MRS_WR_BIT		(1 << 9) /* Write Recovery for autoprecharge */

+#define DDR_MRS_WR_MASK		(7 << DDR_MRS_WR_BIT)

+#define DDR_MRS_DLL_RST		(1 << 8) /* DLL Reset */

+#define DDR_MRS_TM_BIT		7        /* Operating Mode */

+#define DDR_MRS_TM_MASK		(1 << DDR_MRS_OM_BIT) 

+  #define DDR_MRS_TM_NORMAL	(0 << DDR_MRS_OM_BIT)

+  #define DDR_MRS_TM_TEST	(1 << DDR_MRS_OM_BIT)

+#define DDR_MRS_CAS_BIT		4        /* CAS Latency */

+#define DDR_MRS_CAS_MASK	(7 << DDR_MRS_CAS_BIT)

+#define DDR_MRS_BT_BIT		3        /* Burst Type */

+#define DDR_MRS_BT_MASK		(1 << DDR_MRS_BT_BIT)

+  #define DDR_MRS_BT_SEQ	(0 << DDR_MRS_BT_BIT) /* Sequential */

+  #define DDR_MRS_BT_INT	(1 << DDR_MRS_BT_BIT) /* Interleave */

+#define DDR_MRS_BL_BIT		0        /* Burst Length */

+#define DDR_MRS_BL_MASK		(7 << DDR_MRS_BL_BIT)

+  #define DDR_MRS_BL_4		(2 << DDR_MRS_BL_BIT)

+  #define DDR_MRS_BL_8		(3 << DDR_MRS_BL_BIT)

+

+/* DDRC Extended Mode Register1 Set */

+#define DDR_EMRS1_QOFF		(1<<12) /* 0 Output buffer enabled

+					   1 Output buffer disabled */

+#define DDR_EMRS1_RDQS_EN	(1<<11) /* 0 Disable

+					   1 Enable */

+#define DDR_EMRS1_DQS_DIS	(1<<10) /* 0 Enable

+					   1 Disable */

+#define DDR_EMRS1_OCD_BIT	7 /* Additive Latency 0 -> 6 */

+#define DDR_EMRS1_OCD_MASK	(0x7 << DDR_EMRS1_OCD_BIT)

+  #define DDR_EMRS1_OCD_EXIT		(0 << DDR_EMRS1_OCD_BIT)

+  #define DDR_EMRS1_OCD_D0		(1 << DDR_EMRS1_OCD_BIT)

+  #define DDR_EMRS1_OCD_D1		(2 << DDR_EMRS1_OCD_BIT)

+  #define DDR_EMRS1_OCD_ADJ		(4 << DDR_EMRS1_OCD_BIT)

+  #define DDR_EMRS1_OCD_DFLT		(7 << DDR_EMRS1_OCD_BIT)

+#define DDR_EMRS1_AL_BIT	3 /* Additive Latency 0 -> 6 */

+#define DDR_EMRS1_AL_MASK	(7 << DDR_EMRS1_AL_BIT)

+#define DDR_EMRS1_RTT_BIT	2 /*  */

+#define DDR_EMRS1_RTT_MASK	(0x11 << DDR_EMRS1_DIC_BIT) /* Bit 6, Bit 2 */

+#define DDR_EMRS1_DIC_BIT	1        /* Output Driver Impedence Control */

+#define DDR_EMRS1_DIC_MASK	(1 << DDR_EMRS1_DIC_BIT) /* 100% */

+  #define DDR_EMRS1_DIC_NORMAL	(0 << DDR_EMRS1_DIC_BIT) /* 60% */

+  #define DDR_EMRS1_DIC_HALF	(1 << DDR_EMRS1_DIC_BIT)

+#define DDR_EMRS1_DLL_BIT	0        /* DLL Enable  */

+#define DDR_EMRS1_DLL_MASK	(1 << DDR_EMRS1_DLL_BIT)

+  #define DDR_EMRS1_DLL_EN	(0 << DDR_EMRS1_DLL_BIT)

+  #define DDR_EMRS1_DLL_DIS	(1 << DDR_EMRS1_DLL_BIT)

+

+/* Mobile SDRAM Extended Mode Register */

+#define DDR_EMRS_DS_BIT		5	/* Driver strength */

+#define DDR_EMRS_DS_MASK	(7 << DDR_EMRS_DS_BIT)

+  #define DDR_EMRS_DS_FULL	(0 << DDR_EMRS_DS_BIT)	/*Full*/

+  #define DDR_EMRS_DS_HALF	(1 << DDR_EMRS_DS_BIT)	/*1/2 Strength*/

+  #define DDR_EMRS_DS_QUTR	(2 << DDR_EMRS_DS_BIT)	/*1/4 Strength*/

+  #define DDR_EMRS_DS_OCTANT	(3 << DDR_EMRS_DS_BIT)	/*1/8 Strength*/

+  #define DDR_EMRS_DS_QUTR3	(4 << DDR_EMRS_DS_BIT)	/*3/4 Strength*/

+

+#define DDR_EMRS_PRSR_BIT	0	/* Partial Array Self Refresh */

+#define DDR_EMRS_PRSR_MASK	(7 << DDR_EMRS_PRSR_BIT)

+  #define DDR_EMRS_PRSR_ALL	(0 << DDR_EMRS_PRSR_BIT) /*All Banks*/

+  #define DDR_EMRS_PRSR_HALF_TL	(1 << DDR_EMRS_PRSR_BIT) /*Half of Total Bank*/

+  #define DDR_EMRS_PRSR_QUTR_TL	(2 << DDR_EMRS_PRSR_BIT) /*Quarter of Total Bank*/

+  #define DDR_EMRS_PRSR_HALF_B0	(5 << DDR_EMRS_PRSR_BIT) /*Half of Bank0*/

+  #define DDR_EMRS_PRSR_QUTR_B0	(6 << DDR_EMRS_PRSR_BIT) /*Quarter of Bank0*/

+

+

+/* DDRC Timing Config Register 1 */

+#define DDRC_TIMING1_TRAS_BIT 	28 /* ACTIVE to PRECHARGE command period (2 * tRAS + 1) */

+#define DDRC_TIMING1_TRAS_MASK 	(0xf << DDRC_TIMING1_TRAS_BIT)

+

+

+#define DDRC_TIMING1_TRTP_BIT		24 /* READ to PRECHARGE command period. */

+#define DDRC_TIMING1_TRTP_MASK	(0x3 << DDRC_TIMING1_TRTP_BIT)

+

+#define DDRC_TIMING1_TRP_BIT		20 /* PRECHARGE command period. */

+#define DDRC_TIMING1_TRP_MASK 	(0x7 << DDRC_TIMING1_TRP_BIT)

+

+#define DDRC_TIMING1_TRCD_BIT		16 /* ACTIVE to READ or WRITE command period. */

+#define DDRC_TIMING1_TRCD_MASK	(0x7 << DDRC_TIMING1_TRCD_BIT)

+

+#define DDRC_TIMING1_TRC_BIT 		12 /* ACTIVE to ACTIVE command period. */

+#define DDRC_TIMING1_TRC_MASK 	(0xf << DDRC_TIMING1_TRC_BIT)

+

+#define DDRC_TIMING1_TRRD_BIT		8 /* ACTIVE bank A to ACTIVE bank B command period. */

+#define DDRC_TIMING1_TRRD_MASK	(0x3 << DDRC_TIMING1_TRRD_BIT)

+#define DDRC_TIMING1_TRRD_DISABLE	(0 << DDRC_TIMING1_TRRD_BIT)

+#define DDRC_TIMING1_TRRD_2		(1 << DDRC_TIMING1_TRRD_BIT)

+#define DDRC_TIMING1_TRRD_3		(2 << DDRC_TIMING1_TRRD_BIT)

+#define DDRC_TIMING1_TRRD_4		(3 << DDRC_TIMING1_TRRD_BIT)

+

+#define DDRC_TIMING1_TWR_BIT 		4 /* WRITE Recovery Time defined by register MR of DDR2 memory */

+#define DDRC_TIMING1_TWR_MASK		(0x7 << DDRC_TIMING1_TWR_BIT)

+  #define DDRC_TIMING1_TWR_1		(0 << DDRC_TIMING1_TWR_BIT)

+  #define DDRC_TIMING1_TWR_2		(1 << DDRC_TIMING1_TWR_BIT)

+  #define DDRC_TIMING1_TWR_3		(2 << DDRC_TIMING1_TWR_BIT)

+  #define DDRC_TIMING1_TWR_4		(3 << DDRC_TIMING1_TWR_BIT)

+  #define DDRC_TIMING1_TWR_5		(4 << DDRC_TIMING1_TWR_BIT)

+  #define DDRC_TIMING1_TWR_6		(5 << DDRC_TIMING1_TWR_BIT)

+

+#define DDRC_TIMING1_TWTR_BIT		0 /* WRITE to READ command delay. */

+#define DDRC_TIMING1_TWTR_MASK	(0x3 << DDRC_TIMING1_TWTR_BIT)

+  #define DDRC_TIMING1_TWTR_1		(0 << DDRC_TIMING1_TWTR_BIT)

+  #define DDRC_TIMING1_TWTR_2		(1 << DDRC_TIMING1_TWTR_BIT)

+  #define DDRC_TIMING1_TWTR_3		(2 << DDRC_TIMING1_TWTR_BIT)

+  #define DDRC_TIMING1_TWTR_4		(3 << DDRC_TIMING1_TWTR_BIT)

+

+/* DDRC Timing Config Register 2 */

+#define DDRC_TIMING2_TRFC_BIT         12 /* AUTO-REFRESH command period. */

+#define DDRC_TIMING2_TRFC_MASK        (0xf << DDRC_TIMING2_TRFC_BIT)

+#define DDRC_TIMING2_TMINSR_BIT       8  /* Minimum Self-Refresh / Deep-Power-Down time */

+#define DDRC_TIMING2_TMINSR_MASK      (0xf << DDRC_TIMING2_TMINSR_BIT)

+#define DDRC_TIMING2_TXP_BIT          4  /* EXIT-POWER-DOWN to next valid command period. */

+#define DDRC_TIMING2_TXP_MASK         (0x7 << DDRC_TIMING2_TXP_BIT)

+#define DDRC_TIMING2_TMRD_BIT         0  /* Load-Mode-Register to next valid command period. */

+#define DDRC_TIMING2_TMRD_MASK        (0x3 << DDRC_TIMING2_TMRD_BIT)

+

+/* DDRC  Auto-Refresh Counter */

+#define DDRC_REFCNT_CON_BIT           16 /* Constant value used to compare with CNT value. */

+#define DDRC_REFCNT_CON_MASK          (0xff << DDRC_REFCNT_CON_BIT)

+#define DDRC_REFCNT_CNT_BIT           8  /* 8-bit counter */

+#define DDRC_REFCNT_CNT_MASK          (0xff << DDRC_REFCNT_CNT_BIT)

+#define DDRC_REFCNT_CLKDIV_BIT        1  /* Clock Divider for auto-refresh counter. */

+#define DDRC_REFCNT_CLKDIV_MASK       (0x7 << DDRC_REFCNT_CLKDIV_BIT)

+#define DDRC_REFCNT_REF_EN            (1 << 0) /* Enable Refresh Counter */

+

+/* DDRC DQS Delay Control Register */

+#define DDRC_DQS_ERROR                (1 << 29) /* ahb_clk Delay Detect ERROR, read-only. */

+#define DDRC_DQS_READY                (1 << 28) /* ahb_clk Delay Detect READY, read-only. */

+#define DDRC_DQS_AUTO                 (1 << 23) /* Hardware auto-detect & set delay line */

+#define DDRC_DQS_DET                  (1 << 24) /* Start delay detecting. */

+#define DDRC_DQS_CLKD_BIT             16 /* CLKD is reference value for setting WDQS and RDQS.*/

+#define DDRC_DQS_CLKD_MASK            (0x7f << DDRC_DQS_CLKD_BIT) 

+#define DDRC_DQS_WDQS_BIT             8  /* Set delay element number to write DQS delay-line. */

+#define DDRC_DQS_WDQS_MASK            (0x3f << DDRC_DQS_WDQS_BIT) 

+#define DDRC_DQS_RDQS_BIT             0  /* Set delay element number to read DQS delay-line. */

+#define DDRC_DQS_RDQS_MASK            (0x3f << DDRC_DQS_RDQS_BIT) 

+

+/* DDRC DQS Delay Adjust Register */

+#define DDRC_DQS_ADJWDQS_BIT          8 /* The adjust value for WRITE DQS delay */

+#define DDRC_DQS_ADJWDQS_MASK         (0x1f << DDRC_DQS_ADJWDQS_BIT)

+#define DDRC_DQS_ADJRDQS_BIT          0 /* The adjust value for READ DQS delay */

+#define DDRC_DQS_ADJRDQS_MASK         (0x1f << DDRC_DQS_ADJRDQS_BIT)

+

+/* DDRC Memory Map Config Register */

+#define DDRC_MMAP_BASE_BIT            8 /* base address */

+#define DDRC_MMAP_BASE_MASK           (0xff << DDRC_MMAP_BASE_BIT)

+#define DDRC_MMAP_MASK_BIT            0 /* address mask */

+#define DDRC_MMAP_MASK_MASK           (0xff << DDRC_MMAP_MASK_BIT)         

+

+#define DDRC_MMAP0_BASE		     (0x20 << DDRC_MMAP_BASE_BIT)

+#define DDRC_MMAP1_BASE_64M	(0x24 << DDRC_MMAP_BASE_BIT) /*when bank0 is 128M*/

+#define DDRC_MMAP1_BASE_128M	(0x28 << DDRC_MMAP_BASE_BIT) /*when bank0 is 128M*/

+#define DDRC_MMAP1_BASE_256M	(0x30 << DDRC_MMAP_BASE_BIT) /*when bank0 is 128M*/

+

+#define DDRC_MMAP_MASK_64_64	(0xfc << DDRC_MMAP_MASK_BIT)  /*mask for two 128M SDRAM*/

+#define DDRC_MMAP_MASK_128_128	(0xf8 << DDRC_MMAP_MASK_BIT)  /*mask for two 128M SDRAM*/

+#define DDRC_MMAP_MASK_256_256	(0xf0 << DDRC_MMAP_MASK_BIT)  /*mask for two 128M SDRAM*/

+

+

+#ifndef __MIPS_ASSEMBLER

+

+#endif /* __MIPS_ASSEMBLER */

+

+#endif /* __JZ4770DDRC_H__ */

+

diff --git a/arch/mips/include/asm/mach-jz4770/jz4770dmac.h b/arch/mips/include/asm/mach-jz4770/jz4770dmac.h
new file mode 100644
index 00000000000..00444e229b1
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4770/jz4770dmac.h
@@ -0,0 +1,380 @@
+/*

+ * linux/include/asm-mips/mach-jz4770/jz4770dmac.h

+ *

+ * JZ4770 DMAC register definition.

+ *

+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

+ */

+

+#ifndef __JZ4770DMAC_H__

+#define __JZ4770DMAC_H__

+

+

+#define DMAC_BASE	0xB3420000

+

+

+/*************************************************************************

+ * DMAC (DMA Controller)

+ *************************************************************************/

+

+#define MAX_DMA_NUM 	12  /* max 12 channels */

+#define MAX_MDMA_NUM    3   /* max 3  channels */

+#define MAX_BDMA_NUM	3   /* max 3  channels */

+#define HALF_DMA_NUM	6   /* the number of one dma controller's channels */

+

+/* m is the DMA controller index (0, 1), n is the DMA channel index (0 - 11) */

+

+#define DMAC_DSAR(n)  (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0x00 + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x20)) /* DMA source address */

+#define DMAC_DTAR(n)  (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0x04 + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x20)) /* DMA target address */

+#define DMAC_DTCR(n)  (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0x08 + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x20)) /* DMA transfer count */

+#define DMAC_DRSR(n)  (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0x0c + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x20)) /* DMA request source */

+#define DMAC_DCCSR(n) (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0x10 + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x20)) /* DMA control/status */

+#define DMAC_DCMD(n)  (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0x14 + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x20)) /* DMA command */

+#define DMAC_DDA(n)   (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0x18 + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x20)) /* DMA descriptor address */

+#define DMAC_DSD(n)   (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0x1c + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x04)) /* DMA Stride Address */

+

+#define DMAC_DMACR(m)	(DMAC_BASE + 0x0300 + 0x100 * (m))              /* DMA control register */

+#define DMAC_DMAIPR(m)	(DMAC_BASE + 0x0304 + 0x100 * (m))              /* DMA interrupt pending */

+#define DMAC_DMADBR(m)	(DMAC_BASE + 0x0308 + 0x100 * (m))              /* DMA doorbell */

+#define DMAC_DMADBSR(m)	(DMAC_BASE + 0x030C + 0x100 * (m))              /* DMA doorbell set */

+#define DMAC_DMACKE(m)  (DMAC_BASE + 0x0310 + 0x100 * (m))

+

+#define REG_DMAC_DSAR(n)	REG32(DMAC_DSAR((n)))

+#define REG_DMAC_DTAR(n)	REG32(DMAC_DTAR((n)))

+#define REG_DMAC_DTCR(n)	REG32(DMAC_DTCR((n)))

+#define REG_DMAC_DRSR(n)	REG32(DMAC_DRSR((n)))

+#define REG_DMAC_DCCSR(n)	REG32(DMAC_DCCSR((n)))

+#define REG_DMAC_DCMD(n)	REG32(DMAC_DCMD((n)))

+#define REG_DMAC_DDA(n)		REG32(DMAC_DDA((n)))

+#define REG_DMAC_DSD(n)         REG32(DMAC_DSD(n))

+#define REG_DMAC_DMACR(m)	REG32(DMAC_DMACR(m))

+#define REG_DMAC_DMAIPR(m)	REG32(DMAC_DMAIPR(m))

+#define REG_DMAC_DMADBR(m)	REG32(DMAC_DMADBR(m))

+#define REG_DMAC_DMADBSR(m)	REG32(DMAC_DMADBSR(m))

+#define REG_DMAC_DMACKE(m)      REG32(DMAC_DMACKE(m))

+

+// DMA request source register

+#define DMAC_DRSR_RS_BIT	0

+#define DMAC_DRSR_RS_MASK	(0x3f << DMAC_DRSR_RS_BIT)

+/* 0~7 is reserved */

+#define DMAC_DRSR_RS_AUTO	(8 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_TSSIIN	(9 << DMAC_DRSR_RS_BIT)

+/* 10 ~ 11 is reserved */

+#define DMAC_DRSR_RS_EXTERN	(12 << DMAC_DRSR_RS_BIT)

+/* 13 is reserved */

+#define DMAC_DRSR_RS_UART3OUT	(14 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_UART3IN	(15 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_UART2OUT	(16 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_UART2IN	(17 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_UART1OUT	(18 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_UART1IN	(19 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_UART0OUT	(20 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_UART0IN	(21 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_SSI0OUT	(22 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_SSI0IN	(23 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_AICOUT	(24 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_AICIN	(25 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_MSC0OUT	(26 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_MSC0IN	(27 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_TCU	(28 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_SADC	(29 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_MSC1OUT	(30 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_MSC1IN	(31 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_SSI1OUT	(32 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_SSI1IN	(33 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_PMOUT	(34 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_PMIN	(35 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_MSC2OUT	(36 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_MSC2IN	(37 << DMAC_DRSR_RS_BIT)

+/* others are reserved */

+

+// DMA channel control/status register

+#define DMAC_DCCSR_NDES		(1 << 31) /* descriptor (0) or not (1) ? */

+#define DMAC_DCCSR_DES8    	(1 << 30) /* Descriptor 8 Word */

+#define DMAC_DCCSR_DES4    	(0 << 30) /* Descriptor 4 Word */

+/* [29:24] reserved */

+#define DMAC_DCCSR_CDOA_BIT	16        /* copy of DMA offset address */

+#define DMAC_DCCSR_CDOA_MASK	(0xff << DMAC_DCCSR_CDOA_BIT)

+/* [15:5] reserved */

+#define DMAC_DCCSR_AR		(1 << 4)  /* address error */

+#define DMAC_DCCSR_TT		(1 << 3)  /* transfer terminated */

+#define DMAC_DCCSR_HLT		(1 << 2)  /* DMA halted */

+#define DMAC_DCCSR_CT		(1 << 1)  /* count terminated */

+#define DMAC_DCCSR_EN		(1 << 0)  /* channel enable bit */

+

+// DMA channel command register

+#define DMAC_DCMD_EACKS_LOW  	(1 << 31) /* External DACK Output Level Select, active low */

+#define DMAC_DCMD_EACKS_HIGH  	(0 << 31) /* External DACK Output Level Select, active high */

+#define DMAC_DCMD_EACKM_WRITE 	(1 << 30) /* External DACK Output Mode Select, output in write cycle */

+#define DMAC_DCMD_EACKM_READ 	(0 << 30) /* External DACK Output Mode Select, output in read cycle */

+#define DMAC_DCMD_ERDM_BIT      28        /* External DREQ Detection Mode Select */

+#define DMAC_DCMD_ERDM_MASK     (0x03 << DMAC_DCMD_ERDM_BIT)

+#define DMAC_DCMD_ERDM_LOW    (0 << DMAC_DCMD_ERDM_BIT)

+#define DMAC_DCMD_ERDM_FALL   (1 << DMAC_DCMD_ERDM_BIT)

+#define DMAC_DCMD_ERDM_HIGH   (2 << DMAC_DCMD_ERDM_BIT)

+#define DMAC_DCMD_ERDM_RISE   (3 << DMAC_DCMD_ERDM_BIT)

+/* [27:24] reserved */

+#define DMAC_DCMD_SAI		(1 << 23) /* source address increment */

+#define DMAC_DCMD_DAI		(1 << 22) /* dest address increment */

+#define DMAC_DCMD_RDIL_BIT	16        /* request detection interval length */

+#define DMAC_DCMD_RDIL_MASK	(0x0f << DMAC_DCMD_RDIL_BIT)

+#define DMAC_DCMD_RDIL_IGN	(0 << DMAC_DCMD_RDIL_BIT)

+#define DMAC_DCMD_RDIL_2	(1 << DMAC_DCMD_RDIL_BIT)

+#define DMAC_DCMD_RDIL_4	(2 << DMAC_DCMD_RDIL_BIT)

+#define DMAC_DCMD_RDIL_8	(3 << DMAC_DCMD_RDIL_BIT)

+#define DMAC_DCMD_RDIL_12	(4 << DMAC_DCMD_RDIL_BIT)

+#define DMAC_DCMD_RDIL_16	(5 << DMAC_DCMD_RDIL_BIT)

+#define DMAC_DCMD_RDIL_20	(6 << DMAC_DCMD_RDIL_BIT)

+#define DMAC_DCMD_RDIL_24	(7 << DMAC_DCMD_RDIL_BIT)

+#define DMAC_DCMD_RDIL_28	(8 << DMAC_DCMD_RDIL_BIT)

+#define DMAC_DCMD_RDIL_32	(9 << DMAC_DCMD_RDIL_BIT)

+#define DMAC_DCMD_RDIL_48	(10 << DMAC_DCMD_RDIL_BIT)

+#define DMAC_DCMD_RDIL_60	(11 << DMAC_DCMD_RDIL_BIT)

+#define DMAC_DCMD_RDIL_64	(12 << DMAC_DCMD_RDIL_BIT)

+#define DMAC_DCMD_RDIL_124	(13 << DMAC_DCMD_RDIL_BIT)

+#define DMAC_DCMD_RDIL_128	(14 << DMAC_DCMD_RDIL_BIT)

+#define DMAC_DCMD_RDIL_200	(15 << DMAC_DCMD_RDIL_BIT)

+#define DMAC_DCMD_SWDH_BIT	14  /* source port width */

+#define DMAC_DCMD_SWDH_MASK	(0x03 << DMAC_DCMD_SWDH_BIT)

+#define DMAC_DCMD_SWDH_32	(0 << DMAC_DCMD_SWDH_BIT)

+#define DMAC_DCMD_SWDH_8	(1 << DMAC_DCMD_SWDH_BIT)

+#define DMAC_DCMD_SWDH_16	(2 << DMAC_DCMD_SWDH_BIT)

+#define DMAC_DCMD_DWDH_BIT	12  /* dest port width */

+#define DMAC_DCMD_DWDH_MASK	(0x03 << DMAC_DCMD_DWDH_BIT)

+#define DMAC_DCMD_DWDH_32	(0 << DMAC_DCMD_DWDH_BIT)

+#define DMAC_DCMD_DWDH_8	(1 << DMAC_DCMD_DWDH_BIT)

+#define DMAC_DCMD_DWDH_16	(2 << DMAC_DCMD_DWDH_BIT)

+/* bit11 reserved */

+#define DMAC_DCMD_DS_BIT	8  /* transfer data size of a data unit */

+#define DMAC_DCMD_DS_MASK	(0x07 << DMAC_DCMD_DS_BIT)

+#define DMAC_DCMD_DS_32BIT	(0 << DMAC_DCMD_DS_BIT)

+#define DMAC_DCMD_DS_8BIT	(1 << DMAC_DCMD_DS_BIT)

+#define DMAC_DCMD_DS_16BIT	(2 << DMAC_DCMD_DS_BIT)

+#define DMAC_DCMD_DS_16BYTE	(3 << DMAC_DCMD_DS_BIT)

+#define DMAC_DCMD_DS_32BYTE	(4 << DMAC_DCMD_DS_BIT)

+#define DMAC_DCMD_DS_64BYTE	(5 << DMAC_DCMD_DS_BIT)

+/* [7:3] reserved */

+#define DMAC_DCMD_STDE   	(1 << 2)  /* Stride Disable/Enable */

+#define DMAC_DCMD_TIE		(1 << 1)  /* DMA transfer interrupt enable */

+#define DMAC_DCMD_LINK		(1 << 0)  /* descriptor link enable */

+

+// DMA descriptor address register

+#define DMAC_DDA_BASE_BIT	12  /* descriptor base address */

+#define DMAC_DDA_BASE_MASK	(0x0fffff << DMAC_DDA_BASE_BIT)

+#define DMAC_DDA_OFFSET_BIT	4   /* descriptor offset address */

+#define DMAC_DDA_OFFSET_MASK	(0x0ff << DMAC_DDA_OFFSET_BIT)

+/* [3:0] reserved */

+

+// DMA stride address register

+#define DMAC_DSD_TSD_BIT        16  /* target stride address */

+#define DMAC_DSD_TSD_MASK      	(0xffff << DMAC_DSD_TSD_BIT)

+#define DMAC_DSD_SSD_BIT        0  /* source stride address */

+#define DMAC_DSD_SSD_MASK      	(0xffff << DMAC_DSD_SSD_BIT)

+

+// DMA control register

+#define DMAC_DMACR_FMSC		(1 << 31)  /* MSC Fast DMA mode */

+#define DMAC_DMACR_FSSI		(1 << 30)  /* SSI Fast DMA mode */

+#define DMAC_DMACR_FTSSI	(1 << 29)  /* TSSI Fast DMA mode */

+#define DMAC_DMACR_FUART	(1 << 28)  /* UART Fast DMA mode */

+#define DMAC_DMACR_FAIC		(1 << 27)  /* AIC Fast DMA mode */

+/* [26:10] reserved */

+#define DMAC_DMACR_PR_BIT	8  /* channel priority mode */

+#define DMAC_DMACR_PR_MASK	(0x03 << DMAC_DMACR_PR_BIT)

+#define DMAC_DMACR_PR_012345	(0 << DMAC_DMACR_PR_BIT)

+#define DMAC_DMACR_PR_120345	(1 << DMAC_DMACR_PR_BIT)

+#define DMAC_DMACR_PR_230145	(2 << DMAC_DMACR_PR_BIT)

+#define DMAC_DMACR_PR_340125	(3 << DMAC_DMACR_PR_BIT)

+/* [7:4] resered */

+#define DMAC_DMACR_HLT		(1 << 3)  /* DMA halt flag */

+#define DMAC_DMACR_AR		(1 << 2)  /* address error flag */

+/* bit1 reserved */

+#define DMAC_DMACR_DMAE		(1 << 0)  /* DMA enable bit */

+

+// DMA doorbell register

+#define DMAC_DMADBR_DB5		(1 << 5)  /* doorbell for channel 5 */

+#define DMAC_DMADBR_DB4		(1 << 4)  /* doorbell for channel 4 */

+#define DMAC_DMADBR_DB3		(1 << 3)  /* doorbell for channel 3 */

+#define DMAC_DMADBR_DB2		(1 << 2)  /* doorbell for channel 2 */

+#define DMAC_DMADBR_DB1		(1 << 1)  /* doorbell for channel 1 */

+#define DMAC_DMADBR_DB0		(1 << 0)  /* doorbell for channel 0 */

+

+// DMA doorbell set register

+#define DMAC_DMADBSR_DBS5	(1 << 5)  /* enable doorbell for channel 5 */

+#define DMAC_DMADBSR_DBS4	(1 << 4)  /* enable doorbell for channel 4 */

+#define DMAC_DMADBSR_DBS3	(1 << 3)  /* enable doorbell for channel 3 */

+#define DMAC_DMADBSR_DBS2	(1 << 2)  /* enable doorbell for channel 2 */

+#define DMAC_DMADBSR_DBS1	(1 << 1)  /* enable doorbell for channel 1 */

+#define DMAC_DMADBSR_DBS0	(1 << 0)  /* enable doorbell for channel 0 */

+

+// DMA interrupt pending register

+#define DMAC_DMAIPR_CIRQ5	(1 << 5)  /* irq pending status for channel 5 */

+#define DMAC_DMAIPR_CIRQ4	(1 << 4)  /* irq pending status for channel 4 */

+#define DMAC_DMAIPR_CIRQ3	(1 << 3)  /* irq pending status for channel 3 */

+#define DMAC_DMAIPR_CIRQ2	(1 << 2)  /* irq pending status for channel 2 */

+#define DMAC_DMAIPR_CIRQ1	(1 << 1)  /* irq pending status for channel 1 */

+#define DMAC_DMAIPR_CIRQ0	(1 << 0)  /* irq pending status for channel 0 */

+

+

+#ifndef __MIPS_ASSEMBLER

+

+

+/***************************************************************************

+ * DMAC

+ ***************************************************************************/

+

+/* m is the DMA controller index (0, 1), n is the DMA channel index (0 - 11) */

+

+#define __dmac_enable_module(m)						\

+	( REG_DMAC_DMACR(m) |= DMAC_DMACR_DMAE | DMAC_DMACR_PR_012345 )

+#define __dmac_disable_module(m)			\

+	( REG_DMAC_DMACR(m) &= ~DMAC_DMACR_DMAE )

+

+/* p=0,1,2,3 */

+#define __dmac_set_priority(m,p)					\

+	do {								\

+		REG_DMAC_DMACR(m) &= ~DMAC_DMACR_PR_MASK;		\

+		REG_DMAC_DMACR(m) |= ((p) << DMAC_DMACR_PR_BIT);	\

+	} while (0)

+

+#define __dmac_test_halt_error(m) ( REG_DMAC_DMACR(m) & DMAC_DMACR_HLT )

+#define __dmac_test_addr_error(m) ( REG_DMAC_DMACR(m) & DMAC_DMACR_AR )

+

+#define __dmac_channel_enable_clk(n)					\

+	REG_DMAC_DMACKE((n)/HALF_DMA_NUM) |= 1 << ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM);

+

+#define __dmac_enable_descriptor(n)			\

+	( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_NDES )

+#define __dmac_disable_descriptor(n)			\

+	( REG_DMAC_DCCSR((n)) |= DMAC_DCCSR_NDES )

+

+#define __dmac_enable_channel(n)			\

+	do {						\

+		REG_DMAC_DCCSR((n)) |= DMAC_DCCSR_EN;	\

+	} while (0)

+#define __dmac_disable_channel(n)			\

+	do {						\

+		REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_EN;	\

+	} while (0)

+#define __dmac_channel_enabled(n)		\

+	( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_EN )

+

+#define __dmac_channel_enable_irq(n)		\

+	( REG_DMAC_DCMD((n)) |= DMAC_DCMD_TIE )

+#define __dmac_channel_disable_irq(n)			\

+	( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_TIE )

+

+#define __dmac_channel_transmit_halt_detected(n)	\

+	(  REG_DMAC_DCCSR((n)) & DMAC_DCCSR_HLT )

+#define __dmac_channel_transmit_end_detected(n)		\

+	(  REG_DMAC_DCCSR((n)) & DMAC_DCCSR_TT )

+#define __dmac_channel_address_error_detected(n)	\

+	(  REG_DMAC_DCCSR((n)) & DMAC_DCCSR_AR )

+#define __dmac_channel_count_terminated_detected(n)	\

+	(  REG_DMAC_DCCSR((n)) & DMAC_DCCSR_CT )

+#define __dmac_channel_descriptor_invalid_detected(n)	\

+	(  REG_DMAC_DCCSR((n)) & DMAC_DCCSR_INV )

+

+#define __dmac_channel_clear_transmit_halt(n)				\

+	do {								\

+		/* clear both channel halt error and globle halt error */ \

+		REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_HLT;			\

+		REG_DMAC_DMACR(n/HALF_DMA_NUM) &= ~DMAC_DMACR_HLT;	\

+	} while (0)

+#define __dmac_channel_clear_transmit_end(n)		\

+	(  REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_TT )

+#define __dmac_channel_clear_address_error(n)				\

+	do {								\

+		REG_DMAC_DDA(n) = 0; /* clear descriptor address register */ \

+		REG_DMAC_DSAR(n) = 0; /* clear source address register */ \

+		REG_DMAC_DTAR(n) = 0; /* clear target address register */ \

+		/* clear both channel addr error and globle address error */ \

+		REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_AR;			\

+		REG_DMAC_DMACR(n/HALF_DMA_NUM) &= ~DMAC_DMACR_AR;	\

+	} while (0)

+#define __dmac_channel_clear_count_terminated(n)	\

+	(  REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_CT )

+#define __dmac_channel_clear_descriptor_invalid(n)	\

+	(  REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_INV )

+

+#define __dmac_channel_set_transfer_unit_32bit(n)		\

+	do {							\

+		REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK;	\

+		REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_32BIT;	\

+	} while (0)

+

+#define __dmac_channel_set_transfer_unit_16bit(n)		\

+	do {							\

+		REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK;	\

+		REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_16BIT;	\

+	} while (0)

+

+#define __dmac_channel_set_transfer_unit_8bit(n)		\

+	do {							\

+		REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK;	\

+		REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_8BIT;	\

+	} while (0)

+

+#define __dmac_channel_set_transfer_unit_16byte(n)		\

+	do {							\

+		REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK;	\

+		REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_16BYTE;	\

+	} while (0)

+

+#define __dmac_channel_set_transfer_unit_32byte(n)		\

+	do {							\

+		REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK;	\

+		REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_32BYTE;	\

+	} while (0)

+

+/* w=8,16,32 */

+#define __dmac_channel_set_dest_port_width(n,w)			\

+	do {							\

+		REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DWDH_MASK;	\

+		REG_DMAC_DCMD((n)) |= DMAC_DCMD_DWDH_##w;	\

+	} while (0)

+

+/* w=8,16,32 */

+#define __dmac_channel_set_src_port_width(n,w)			\

+	do {							\

+		REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_SWDH_MASK;	\

+		REG_DMAC_DCMD((n)) |= DMAC_DCMD_SWDH_##w;	\

+	} while (0)

+

+/* v=0-15 */

+#define __dmac_channel_set_rdil(n,v)				\

+	do {							\

+	REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_RDIL_MASK;		\

+	REG_DMAC_DCMD((n) |= ((v) << DMAC_DCMD_RDIL_BIT);	\

+		      } while (0)

+

+#define __dmac_channel_dest_addr_fixed(n)		\

+	(  REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DAI )

+#define __dmac_channel_dest_addr_increment(n)		\

+	(  REG_DMAC_DCMD((n)) |= DMAC_DCMD_DAI )

+

+#define __dmac_channel_src_addr_fixed(n)		\

+	(  REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_SAI )

+#define __dmac_channel_src_addr_increment(n)		\

+	(  REG_DMAC_DCMD((n)) |= DMAC_DCMD_SAI )

+

+#define __dmac_channel_set_doorbell(n)					\

+	(  REG_DMAC_DMADBSR((n)/HALF_DMA_NUM) = (1 << ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM)) )

+

+#define __dmac_channel_irq_detected(n)  ( REG_DMAC_DMAIPR((n)/HALF_DMA_NUM) & (1 << ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM)) )

+#define __dmac_channel_ack_irq(n)       ( REG_DMAC_DMAIPR((n)/HALF_DMA_NUM) &= ~(1 <<((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM)) )

+

+static __inline__ int __dmac_get_irq(void)

+{

+	int i;

+	for (i = 0; i < MAX_DMA_NUM; i++)

+		if (__dmac_channel_irq_detected(i))

+			return i;

+	return -1;

+}

+

+

+

+#endif /* __MIPS_ASSEMBLER */

+

+#endif /* __JZ4770DMAC_H__ */

+

diff --git a/arch/mips/include/asm/mach-jz4770/jz4770emc.h b/arch/mips/include/asm/mach-jz4770/jz4770emc.h
new file mode 100644
index 00000000000..29cd387feca
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4770/jz4770emc.h
@@ -0,0 +1,213 @@
+/*

+ * linux/include/asm-mips/mach-jz4770/jz4770emc.h

+ *

+ * JZ4770 EMC register definition.

+ *

+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

+ */

+

+#ifndef __JZ4770EMC_H__

+#define __JZ4770EMC_H__

+

+

+#define	EMC_BASE	0xB3010000

+

+

+/*************************************************************************

+ * EMC (External Memory Controller)

+ *************************************************************************/

+#define EMC_BCR    	(EMC_BASE + 0x00)  /* Bus Control Register */

+#define EMC_PMEMBS1     (EMC_BASE + 0x6004) 

+#define EMC_PMEMBS0     (EMC_BASE + 0x6008) 

+#define EMC_SMCR0	(EMC_BASE + 0x10)  /* Static Memory Control Register 0 ??? */

+#define EMC_SMCR1	(EMC_BASE + 0x14)  /* Static Memory Control Register 1 */

+#define EMC_SMCR2	(EMC_BASE + 0x18)  /* Static Memory Control Register 2 */

+#define EMC_SMCR3	(EMC_BASE + 0x1c)  /* Static Memory Control Register 3 */

+#define EMC_SMCR4	(EMC_BASE + 0x20)  /* Static Memory Control Register 4 */

+#define EMC_SMCR5	(EMC_BASE + 0x24)  /* Static Memory Control Register 5 */

+#define EMC_SMCR6	(EMC_BASE + 0x28)  /* Static Memory Control Register 6 */

+#define EMC_SACR0	(EMC_BASE + 0x30)  /* Static Memory Bank 0 Addr Config Reg */

+#define EMC_SACR1	(EMC_BASE + 0x34)  /* Static Memory Bank 1 Addr Config Reg */

+#define EMC_SACR2	(EMC_BASE + 0x38)  /* Static Memory Bank 2 Addr Config Reg */

+#define EMC_SACR3	(EMC_BASE + 0x3c)  /* Static Memory Bank 3 Addr Config Reg */

+#define EMC_SACR4	(EMC_BASE + 0x40)  /* Static Memory Bank 4 Addr Config Reg */

+

+#define EMC_NFCSR	(EMC_BASE + 0x050) /* NAND Flash Control/Status Register */

+

+#define EMC_DMCR	(EMC_BASE + 0x80)  /* DRAM Control Register */

+#define EMC_RTCSR	(EMC_BASE + 0x84)  /* Refresh Time Control/Status Register */

+#define EMC_RTCNT	(EMC_BASE + 0x88)  /* Refresh Timer Counter */

+#define EMC_RTCOR	(EMC_BASE + 0x8c)  /* Refresh Time Constant Register */

+#define EMC_DMAR0	(EMC_BASE + 0x90)  /* SDRAM Bank 0 Addr Config Register */

+#define EMC_DMAR1	(EMC_BASE + 0x94)  /* SDRAM Bank 1 Addr Config Register */

+#define EMC_SDMR0	(EMC_BASE + 0xa000) /* Mode Register of SDRAM bank 0 */

+

+#define REG_EMC_BCR 	REG32(EMC_BCR)

+#define REG_EMC_PMEMBS1 REG32(EMC_PMEMBS1)

+#define REG_EMC_PMEMBS0	REG32(EMC_PMEMBS0)

+#define REG_EMC_SMCR0	REG32(EMC_SMCR0) // ???

+#define REG_EMC_SMCR1	REG32(EMC_SMCR1)

+#define REG_EMC_SMCR2	REG32(EMC_SMCR2)

+#define REG_EMC_SMCR3	REG32(EMC_SMCR3)

+#define REG_EMC_SMCR4	REG32(EMC_SMCR4)

+#define REG_EMC_SMCR5	REG32(EMC_SMCR5)

+#define REG_EMC_SMCR6	REG32(EMC_SMCR6)

+#define REG_EMC_SACR0	REG32(EMC_SACR0)

+#define REG_EMC_SACR1	REG32(EMC_SACR1)

+#define REG_EMC_SACR2	REG32(EMC_SACR2)

+#define REG_EMC_SACR3	REG32(EMC_SACR3)

+#define REG_EMC_SACR4	REG32(EMC_SACR4)

+

+#define REG_EMC_NFCSR	REG32(EMC_NFCSR)

+

+#define REG_EMC_DMCR	REG32(EMC_DMCR)

+#define REG_EMC_RTCSR	REG16(EMC_RTCSR)

+#define REG_EMC_RTCNT	REG16(EMC_RTCNT)

+#define REG_EMC_RTCOR	REG16(EMC_RTCOR)

+#define REG_EMC_DMAR0	REG32(EMC_DMAR0)

+#define REG_EMC_DMAR1	REG32(EMC_DMAR1)

+

+/* Bus Control Register */

+#define EMC_BCR_BT_SEL_BIT      30

+#define EMC_BCR_BT_SEL_MASK     (0x3 << EMC_BCR_BT_SEL_BIT)

+#define EMC_BCR_PK_SEL          (1 << 24)

+#define EMC_BCR_BSR_MASK          (1 << 2)  /* Nand and SDRAM Bus Share Select: 0, share; 1, unshare */

+  #define EMC_BCR_BSR_SHARE       (0 << 2)

+  #define EMC_BCR_BSR_UNSHARE     (1 << 2)

+#define EMC_BCR_BRE             (1 << 1)

+#define EMC_BCR_ENDIAN          (1 << 0)

+

+/* Static Memory Control Register */

+#define EMC_SMCR_STRV_BIT	24

+#define EMC_SMCR_STRV_MASK	(0x0f << EMC_SMCR_STRV_BIT)

+#define EMC_SMCR_TAW_BIT	20

+#define EMC_SMCR_TAW_MASK	(0x0f << EMC_SMCR_TAW_BIT)

+#define EMC_SMCR_TBP_BIT	16

+#define EMC_SMCR_TBP_MASK	(0x0f << EMC_SMCR_TBP_BIT)

+#define EMC_SMCR_TAH_BIT	12

+#define EMC_SMCR_TAH_MASK	(0x07 << EMC_SMCR_TAH_BIT)

+#define EMC_SMCR_TAS_BIT	8

+#define EMC_SMCR_TAS_MASK	(0x07 << EMC_SMCR_TAS_BIT)

+#define EMC_SMCR_BW_BIT		6

+#define EMC_SMCR_BW_MASK	(0x03 << EMC_SMCR_BW_BIT)

+  #define EMC_SMCR_BW_8BIT	(0 << EMC_SMCR_BW_BIT)

+  #define EMC_SMCR_BW_16BIT	(1 << EMC_SMCR_BW_BIT)

+  #define EMC_SMCR_BW_32BIT	(2 << EMC_SMCR_BW_BIT)

+#define EMC_SMCR_BCM		(1 << 3)

+#define EMC_SMCR_BL_BIT		1

+#define EMC_SMCR_BL_MASK	(0x03 << EMC_SMCR_BL_BIT)

+  #define EMC_SMCR_BL_4		(0 << EMC_SMCR_BL_BIT)

+  #define EMC_SMCR_BL_8		(1 << EMC_SMCR_BL_BIT)

+  #define EMC_SMCR_BL_16	(2 << EMC_SMCR_BL_BIT)

+  #define EMC_SMCR_BL_32	(3 << EMC_SMCR_BL_BIT)

+#define EMC_SMCR_SMT		(1 << 0)

+

+/* Static Memory Bank Addr Config Reg */

+#define EMC_SACR_BASE_BIT	8

+#define EMC_SACR_BASE_MASK	(0xff << EMC_SACR_BASE_BIT)

+#define EMC_SACR_MASK_BIT	0

+#define EMC_SACR_MASK_MASK	(0xff << EMC_SACR_MASK_BIT)

+

+/* NAND Flash Control/Status Register */

+#define EMC_NFCSR_NFCE4		(1 << 7) /* NAND Flash Enable */

+#define EMC_NFCSR_NFE4		(1 << 6) /* NAND Flash FCE# Assertion Enable */

+#define EMC_NFCSR_NFCE3		(1 << 5)

+#define EMC_NFCSR_NFE3		(1 << 4)

+#define EMC_NFCSR_NFCE2		(1 << 3)

+#define EMC_NFCSR_NFE2		(1 << 2)

+#define EMC_NFCSR_NFCE1		(1 << 1)

+#define EMC_NFCSR_NFE1		(1 << 0)

+

+/* DRAM Control Register */

+#define EMC_DMCR_BW_BIT		31

+#define EMC_DMCR_BW		(1 << EMC_DMCR_BW_BIT)

+#define EMC_DMCR_CA_BIT		26

+#define EMC_DMCR_CA_MASK	(0x07 << EMC_DMCR_CA_BIT)

+  #define EMC_DMCR_CA_8		(0 << EMC_DMCR_CA_BIT)

+  #define EMC_DMCR_CA_9		(1 << EMC_DMCR_CA_BIT)

+  #define EMC_DMCR_CA_10	(2 << EMC_DMCR_CA_BIT)

+  #define EMC_DMCR_CA_11	(3 << EMC_DMCR_CA_BIT)

+  #define EMC_DMCR_CA_12	(4 << EMC_DMCR_CA_BIT)

+#define EMC_DMCR_RMODE		(1 << 25)

+#define EMC_DMCR_RFSH		(1 << 24)

+#define EMC_DMCR_MRSET		(1 << 23)

+#define EMC_DMCR_RA_BIT		20

+#define EMC_DMCR_RA_MASK	(0x03 << EMC_DMCR_RA_BIT)

+  #define EMC_DMCR_RA_11	(0 << EMC_DMCR_RA_BIT)

+  #define EMC_DMCR_RA_12	(1 << EMC_DMCR_RA_BIT)

+  #define EMC_DMCR_RA_13	(2 << EMC_DMCR_RA_BIT)

+#define EMC_DMCR_BA_BIT		19

+#define EMC_DMCR_BA		(1 << EMC_DMCR_BA_BIT)

+#define EMC_DMCR_PDM		(1 << 18)

+#define EMC_DMCR_EPIN		(1 << 17)

+#define EMC_DMCR_MBSEL		(1 << 16)

+#define EMC_DMCR_TRAS_BIT	13

+#define EMC_DMCR_TRAS_MASK	(0x07 << EMC_DMCR_TRAS_BIT)

+#define EMC_DMCR_RCD_BIT	11

+#define EMC_DMCR_RCD_MASK	(0x03 << EMC_DMCR_RCD_BIT)

+#define EMC_DMCR_TPC_BIT	8

+#define EMC_DMCR_TPC_MASK	(0x07 << EMC_DMCR_TPC_BIT)

+#define EMC_DMCR_TRWL_BIT	5

+#define EMC_DMCR_TRWL_MASK	(0x03 << EMC_DMCR_TRWL_BIT)

+#define EMC_DMCR_TRC_BIT	2

+#define EMC_DMCR_TRC_MASK	(0x07 << EMC_DMCR_TRC_BIT)

+#define EMC_DMCR_TCL_BIT	0

+#define EMC_DMCR_TCL_MASK	(0x03 << EMC_DMCR_TCL_BIT)

+

+/* Refresh Time Control/Status Register */

+#define EMC_RTCSR_SFR		(1 << 8)    /* self refresh flag */

+#define EMC_RTCSR_CMF		(1 << 7)

+#define EMC_RTCSR_CKS_BIT	0

+#define EMC_RTCSR_CKS_MASK	(0x07 << EMC_RTCSR_CKS_BIT)

+  #define EMC_RTCSR_CKS_DISABLE	(0 << EMC_RTCSR_CKS_BIT)

+  #define EMC_RTCSR_CKS_4	(1 << EMC_RTCSR_CKS_BIT)

+  #define EMC_RTCSR_CKS_16	(2 << EMC_RTCSR_CKS_BIT)

+  #define EMC_RTCSR_CKS_64	(3 << EMC_RTCSR_CKS_BIT)

+  #define EMC_RTCSR_CKS_256	(4 << EMC_RTCSR_CKS_BIT)

+  #define EMC_RTCSR_CKS_1024	(5 << EMC_RTCSR_CKS_BIT)

+  #define EMC_RTCSR_CKS_2048	(6 << EMC_RTCSR_CKS_BIT)

+  #define EMC_RTCSR_CKS_4096	(7 << EMC_RTCSR_CKS_BIT)

+

+/* SDRAM Bank Address Configuration Register */

+#define EMC_DMAR_BASE_BIT	8

+#define EMC_DMAR_BASE_MASK	(0xff << EMC_DMAR_BASE_BIT)

+#define EMC_DMAR_MASK_BIT	0

+#define EMC_DMAR_MASK_MASK	(0xff << EMC_DMAR_MASK_BIT)

+

+/* Mode Register of SDRAM bank 0 */

+#define EMC_SDMR_BM		(1 << 9) /* Write Burst Mode */

+#define EMC_SDMR_OM_BIT		7        /* Operating Mode */

+#define EMC_SDMR_OM_MASK	(3 << EMC_SDMR_OM_BIT)

+  #define EMC_SDMR_OM_NORMAL	(0 << EMC_SDMR_OM_BIT)

+#define EMC_SDMR_CAS_BIT	4        /* CAS Latency */

+#define EMC_SDMR_CAS_MASK	(7 << EMC_SDMR_CAS_BIT)

+  #define EMC_SDMR_CAS_1	(1 << EMC_SDMR_CAS_BIT)

+  #define EMC_SDMR_CAS_2	(2 << EMC_SDMR_CAS_BIT)

+  #define EMC_SDMR_CAS_3	(3 << EMC_SDMR_CAS_BIT)

+#define EMC_SDMR_BT_BIT		3        /* Burst Type */

+#define EMC_SDMR_BT_MASK	(1 << EMC_SDMR_BT_BIT)

+  #define EMC_SDMR_BT_SEQ	(0 << EMC_SDMR_BT_BIT) /* Sequential */

+  #define EMC_SDMR_BT_INT	(1 << EMC_SDMR_BT_BIT) /* Interleave */

+#define EMC_SDMR_BL_BIT		0        /* Burst Length */

+#define EMC_SDMR_BL_MASK	(7 << EMC_SDMR_BL_BIT)

+  #define EMC_SDMR_BL_1		(0 << EMC_SDMR_BL_BIT)

+  #define EMC_SDMR_BL_2		(1 << EMC_SDMR_BL_BIT)

+  #define EMC_SDMR_BL_4		(2 << EMC_SDMR_BL_BIT)

+  #define EMC_SDMR_BL_8		(3 << EMC_SDMR_BL_BIT)

+

+#define EMC_SDMR_CAS2_16BIT \

+  (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2)

+#define EMC_SDMR_CAS2_32BIT \

+  (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4)

+#define EMC_SDMR_CAS3_16BIT \

+  (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2)

+#define EMC_SDMR_CAS3_32BIT \

+  (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4)

+

+

+#ifndef __MIPS_ASSEMBLER

+

+#endif /* __MIPS_ASSEMBLER */

+

+#endif /* __JZ4770EMC_H__ */

+

diff --git a/arch/mips/include/asm/mach-jz4770/jz4770gpio.h b/arch/mips/include/asm/mach-jz4770/jz4770gpio.h
new file mode 100644
index 00000000000..625d923c6c7
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4770/jz4770gpio.h
@@ -0,0 +1,1141 @@
+/*

+ * linux/include/asm-mips/mach-jz4770/jz4770gpio.h

+ *

+ * JZ4770 GPIO register definition.

+ *

+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

+ */

+

+#ifndef __JZ4770GPIO_H__

+#define __JZ4770GPIO_H__

+

+/***************************************************************************

+ * GPIO

+ ***************************************************************************/

+

+//------------------------------------------------------

+// GPIO Pins Description

+//

+// PORT 0:

+//

+// PIN/BIT N	FUNC0		FUNC1		FUNC2         NOTE

+//	0	SD0		-		-

+//	1	SD1		-		-

+//	2	SD2		-		-

+//	3	SD3		-		-

+//	4	SD4		-		-

+//	5	SD5		-		-

+//	6	SD6		-		-

+//	7	SD7		-		-

+//	8	SD8		-		-

+//	9	SD9		-		-

+//	10	SD10		-		-

+//	11	SD11		-		-

+//	12	SD12		-		-

+//	13	SD13		-		-

+//	14	SD14		-		-

+//	15	SD15		-		-

+//      16      RD_             -		-

+//      17      WE_             -		-

+//      18      FRE_            MSC0_CLK        SSI0_CLK

+//      19      FWE_            MSC0_CMD        SSI0_CE0_

+//      20      MSC0_D0         SSI0_DR		-	       1

+//      21      CS1_            MSC0_D1         SSI0_DT

+//      22      CS2_            MSC0_D2		-

+//      23      CS3_		-		-

+//      24      CS4_ 		-		-

+//      25      CS5_		-		-

+//      26      CS6_		-		-

+//      27      WAIT_		-		-

+//      28      DREQ0		-		-

+//      29      DACK0           OWI		-

+//      30	-		-		-	     6

+//      31	-		-		-	     7

+

+//Note1. PA20: GPIO group A bit 20. If NAND flash is used, this pin must be used as NAND FRB. (NAND flash ready/busy)

+//Note6. PA30: GPIO group A bit 30 can only be used as input and interrupt, no pull-up and pull-down.

+//Note7. PA31: GPIO group A bit 31. No corresponding pin exists for this GPIO. It is only used to select the function between UART and JTAG, which share the same set of pins, by using register PASEL [31]

+//       When PASEL [31]=0, select JTAG function.

+//       When PASEL [31]=1, select UART function

+

+//------------------------------------------------------

+// PORT 1:

+//

+// PIN/BIT N	FUNC0		FUNC1	       FUNC2         NOTE

+//	0	SA0		-              -

+//	1	SA1		-              -

+//	2	SA2		-              -             CL

+//	3	SA3		-              -             AL

+//	4	SA4		-              -

+//	5	SA5		-              -

+//	6	CIM_PCLK 	TSCLK	       -

+//	7	CIM_HSYN  	TSFRM          -

+//	8	CIM_VSYN 	TSSTR          -

+//	9	CIM_MCLK 	TSFAIL         -

+//	10	CIM_D0 	 	TSDI0          -

+//	11	CIM_D1 	 	TSDI1          -

+//	12	CIM_D2 	 	TSDI2          -

+//	13	CIM_D3 		TSDI3          -

+//	14	CIM_D4 		TSDI4          -

+//	15	CIM_D5		TSDI5          -

+//	16 	CIM_D6 		TSDI6          -

+//	17 	CIM_D7 		TSDI7          -

+//	18	-               -	       -

+//	19	-               -	       -

+//	20 	MSC2_D0 	SSI2_DR        TSDI0

+//	21 	MSC2_D1 	SSI2_DT        TSDI1

+//	22 	TSDI2		-              -

+//	23 	TSDI3		-              -

+//	24 	TSDI4		-              -

+//	25 	TSDI5		-              -

+//	26 	TSDI6		-              -

+//	27 	TSDI7		-              -

+//	28 	MSC2_CLK        SSI2_CLK       TSCLK

+//	29 	MSC2_CMD        SSI2_CE0_      TSSTR

+//	30 	MSC2_D2         SSI2_GPC       TSFAIL

+//	31 	MSC2_D3         SSI2_CE1_      TSFRM

+

+//------------------------------------------------------

+// PORT 2:

+// PIN/BIT N	FUNC0		FUNC1		FUNC2 		FUNC3		NOTE

+//	0	LCD_B0 (O)	LCD_REV (O)	-               -

+//	1	LCD_B1 (O)	LCD_PS (O)	-               -

+//	2	LCD_B2 (O)	-               -	        -

+//	3	LCD_B3 (O)	-               -	        -

+//	4	LCD_B4 (O)	-               -	        -

+//	5	LCD_B5 (O)	-               -	        -

+//	6	LCD_B6 (O)	-               -	        -

+//	7	LCD_B7 (O)	-               -	        -

+//	8	LCD_PCLK (O)	-               -	        -

+//	9	LCD_DE (O)	-               -	        -

+//	10	LCD_G0 (O)	LCD_SPL (O)	-               -

+//	11	LCD_G1 (O)	-               -	        -

+//	12	LCD_G2 (O)	-               -	        -

+//	13	LCD_G3 (O)	-               -	        -

+//	14	LCD_G4 (O)	-               -	        -

+//	15	LCD_G5 (O)	-               -	        -

+//	16	LCD_G6 (O)	-               -	        -

+//	17	LCD_G7 (O)	-               -	        -

+//	18	LCD_HSYN (IO)	-               -	        -

+//	19	LCD_VSYN (IO)	-               -	        -

+//	20	LCD_R0 (O)	LCD_CLS (O)	-               -

+//	21	LCD_R1 (O)	-               -	        -

+//	22	LCD_R2 (O)	-               -	        -

+//	23	LCD_R3 (O)	-               -	        -

+//	24	LCD_R4 (O)	-               -	        -

+//	25	LCD_R5 (O)	-               -	        -

+//	26	LCD_R6 (O)	-               -	        -

+//	27	LCD_R7 (O)	-               -	        -

+//	28	UART2_RxD (I)	-               -	        -

+//	29	UART2_CTS_ (I)	-               -	        -

+//	30	UART2_TxD (O)	-               -	        -

+//	31	UART2_RTS_ (O)	-               -	        -

+

+//------------------------------------------------------

+// PORT 3:

+//

+// PIN/BIT N	FUNC0		FUNC1		FUNC2 		FUNC3		NOTE

+//	0 	MII_TXD0 	-     		-  		-

+//	1 	MII_TXD1	-     		-  		-

+//	2 	MII_TXD2	-     		-  		-

+//	3 	MII_TXD3	- 		-  		-

+//	4 	MII_TXEN	-		-		-

+//	5  MII_TXCLK(RMII_CLK)	-		-  		-

+//	6 	MII_COL   	-		-  		-

+//	7 	MII_RXER	-		-  		-

+//	8 	MII_RXDV	-		-  		-

+//	9 	MII_RXCLK	-		-		-

+//	10 	MII_RXD0	-		-  		-

+//	11 	MII_RXD1	-		-  		-

+//	12 	MII_RXD2	-		-  		-

+//	13 	MII_RXD3	-		-  		-

+//	14 	MII_CRS		-		-  		-

+//	15 	MII_MDC		-		-  		-

+//	16 	MII_MDIO	-		-  		-

+//	17 	BOOT_SEL0	-		-  		-		Note2,5

+//	18 	BOOT_SEL1	-		-  		- 		Note3,5

+//	19 	BOOT_SEL2	-		-  		- 		Note4,5

+//	20 	MSC1_D0 	SSI1_DR 	-  		-

+//	21	MSC1_D1 	SSI1_DT 	-  		-

+//	22 	MSC1_D2  	SSI1_GPC 	-  		-

+//	23 	MSC1_D3  	SSI1_CE1_ 	-  		-

+//	24 	MSC1_CLK  	SSI1_CLK 	-  		-

+//	25 	MSC1_CMD  	SSI1_CE0_ 	-  		-

+//	26 	UART1_RxD 	-		-  		-

+//	27 	UART1_CTS_ 	-		-  		-

+//	28 	UART1_TxD 	-		-  		-

+//	29 	UART1_RTS_ 	-		-  		-

+//	30 	I2C0_SDA 	-		-  		-

+//	31 	I2C0_SCK 	-		-  		-

+//

+// Note2. PD17: GPIO group D bit 17 is used as BOOT_SEL0 input during boot.

+// Note3. PD18: GPIO group D bit 18 is used as BOOT_SEL1 input during boot.

+// Note4. PD19: GPIO group D bit 19 is used as BOOT_SEL2 input during boot.

+// Note5. BOOT_SEL2, BOOT_SEL1, BOOT_SEL0 are used to select boot source and function during the processor boot.

+//

+//------------------------------------------------------

+// PORT 4:

+//

+// PIN/BIT N	FUNC0		FUNC1	       FUNC2         FUNC3         NOTE

+//	0  	PWM0		- 		- 		-

+//	1  	PWM1		- 		- 		-

+//	2  	PWM2 		SYNC 		- 		-

+//	3  	PWM3 		UART3_RxD 	BCLK 		-

+//	4  	PWM4 		- 		- 		-

+//	5  	PWM5 		UART3_TxD 	SCLK_RSTN 	-

+//	6  	SDATI		- 		- 		-

+//	7  	SDATO 		- 		- 		-

+//	8  	UART3_CTS_ 	- 		- 		-

+//	9  	UART3_RTS_ 	- 		- 		-

+//	10  	- 		- 		- 		-

+//	11  	SDATO1 		- 		- 		-

+//	12  	SDATO2 		- 		- 		-

+//	13  	SDATO3 		-		-		-

+//	14  	SSI0_DR 	SSI1_DR 	SSI2_DR 	-

+//	15  	SSI0_CLK 	SI1_CLK 	SSI2_CLK 	-

+//	16  	SSI0_CE0_ 	SI1_CE0_ 	SSI2_CE0_ 	-

+//	17  	SSI0_DT 	SSI1_DT 	SSI2_DT 	-

+//	18  	SSI0_CE1_ 	SSI1_CE1_ 	SSI2_CE1_ 	-

+//	19  	SSI0_GPC 	SSI1_GPC 	SSI2_GPC 	-

+//	20  	MSC0_D0 	MSC1_D0 	MSC2_D0 	-

+//	21  	MSC0_D1 	MSC1_D1 	MSC2_D1 	-

+//	22  	MSC0_D2 	MSC1_D2 	MSC2_D2 	-

+//	23  	MSC0_D3 	MSC1_D3 	MSC2_D3 	-

+//	24  	MSC0_CLK 	MSC1_CLK 	MSC2_CLK 	-

+//	25  	MSC0_CMD 	MSC1_CMD 	MSC2_CMD 	-

+//	26  	MSC0_D4 	MSC0_D4 	MSC0_D4 	PS2_MCLK

+//	27  	MSC0_D5 	MSC0_D5 	MSC0_D5 	PS2_MDATA

+//	28  	MSC0_D6 	MSC0_D6 	MSC0_D6 	PS2_KCLK

+//	29  	MSC0_D7 	MSC0_D7 	MSC0_D7 	PS2_KDATA

+//	30  	I2C1_SDA 	SCC_DATA 	- 		-

+//	31  	I2C1_SCK 	SCC_CLK 	- 		-

+//

+//------------------------------------------------------

+// PORT 5:

+//

+// PIN/BIT N	FUNC0		FUNC1		FUNC2		FUNC3		NOTE

+//	0   	UART0_RxD 	GPS_CLK 	- 		-

+//	1   	UART0_CTS_ 	GPS_MAG 	- 		-

+//	2   	UART0_TxD 	GPS_SIG 	- 		-

+//	3   	UART0_RTS_ 	- 		-		-

+//

+//////////////////////////////////////////////////////////

+

+

+

+#define	GPIO_BASE	0xB0010000

+

+

+/*************************************************************************

+ * GPIO (General-Purpose I/O Ports)

+ *************************************************************************/

+#define GPIO_BASEA GPIO_BASE +(0)*0x100

+#define GPIO_BASEB GPIO_BASE +(1)*0x100

+#define GPIO_BASEC GPIO_BASE +(2)*0x100

+#define GPIO_BASED GPIO_BASE +(3)*0x100

+#define GPIO_BASEE GPIO_BASE +(4)*0x100

+#define GPIO_BASEF GPIO_BASE +(5)*0x100

+

+#define MAX_GPIO_NUM	192

+#define GPIO_WAKEUP     (30)

+

+//n = 0,1,2,3,4,5 (PORTA, PORTB, PORTC, PORTD, PORTE, PORTF)

+#define GPIO_PXPIN(n)	(GPIO_BASE + (0x00 + (n)*0x100)) /* PIN Level Register */

+#define GPIO_PXINT(n)	(GPIO_BASE + (0x10 + (n)*0x100)) /* Port Interrupt Register */

+#define GPIO_PXINTS(n)	(GPIO_BASE + (0x14 + (n)*0x100)) /* Port Interrupt Set Register */

+#define GPIO_PXINTC(n)	(GPIO_BASE + (0x18 + (n)*0x100)) /* Port Interrupt Clear Register */

+

+//#define GPIO_PXMASK(n)	(GPIO_BASE + (0x20 + (n)*0x100)) /* Interrupt Mask Register */

+//#define GPIO_PXMASKS(n)	(GPIO_BASE + (0x24 + (n)*0x100)) /* Interrupt Mask Set Reg */

+//#define GPIO_PXMASKC(n)	(GPIO_BASE + (0x28 + (n)*0x100)) /* Interrupt Mask Clear Reg */

+#define GPIO_PXMASK(n)	(GPIO_BASE + (0x20 + (n)*0x100)) /* Port Interrupt Mask Register */

+#define GPIO_PXMASKS(n)	(GPIO_BASE + (0x24 + (n)*0x100)) /* Port Interrupt Mask Set Reg */

+#define GPIO_PXMASKC(n)	(GPIO_BASE + (0x28 + (n)*0x100)) /* Port Interrupt Mask Clear Reg */

+

+#define GPIO_PXPAT1(n)	(GPIO_BASE + (0x30 + (n)*0x100)) /* Port Pattern 1 Register */

+#define GPIO_PXPAT1S(n)	(GPIO_BASE + (0x34 + (n)*0x100)) /* Port Pattern 1 Set Reg. */

+#define GPIO_PXPAT1C(n)	(GPIO_BASE + (0x38 + (n)*0x100)) /* Port Pattern 1 Clear Reg. */

+#define GPIO_PXPAT0(n)	(GPIO_BASE + (0x40 + (n)*0x100)) /* Port Pattern 0 Register */

+#define GPIO_PXPAT0S(n)	(GPIO_BASE + (0x44 + (n)*0x100)) /* Port Pattern 0 Set Register */

+#define GPIO_PXPAT0C(n)	(GPIO_BASE + (0x48 + (n)*0x100)) /* Port Pattern 0 Clear Register */

+#define GPIO_PXFLG(n)	(GPIO_BASE + (0x50 + (n)*0x100)) /* Port Flag Register */

+#define GPIO_PXFLGC(n)	(GPIO_BASE + (0x58 + (n)*0x100)) /* Port Flag clear Register */

+#define GPIO_PXOEN(n)	(GPIO_BASE + (0x60 + (n)*0x100)) /* Port Output Disable Register */

+#define GPIO_PXOENS(n)	(GPIO_BASE + (0x64 + (n)*0x100)) /* Port Output Disable Set Register */

+#define GPIO_PXOENC(n)	(GPIO_BASE + (0x68 + (n)*0x100)) /* Port Output Disable Clear Register */

+#define GPIO_PXPEN(n)	(GPIO_BASE + (0x70 + (n)*0x100)) /* Port Pull Disable Register */

+#define GPIO_PXPENS(n)	(GPIO_BASE + (0x74 + (n)*0x100)) /* Port Pull Disable Set Register */

+#define GPIO_PXPENC(n)	(GPIO_BASE + (0x78 + (n)*0x100)) /* Port Pull Disable Clear Register */

+#define GPIO_PXDS(n)	(GPIO_BASE + (0x80 + (n)*0x100)) /* Port Drive Strength Register */

+#define GPIO_PXDSS(n)	(GPIO_BASE + (0x84 + (n)*0x100)) /* Port Drive Strength set Register */

+#define GPIO_PXDSC(n)	(GPIO_BASE + (0x88 + (n)*0x100)) /* Port Drive Strength clear Register */

+

+#define REG_GPIO_PXPIN(n)	REG32(GPIO_PXPIN((n)))  /* PIN level */

+#define REG_GPIO_PXINT(n)	REG32(GPIO_PXINT((n)))  /* 1: interrupt pending */

+#define REG_GPIO_PXINTS(n)	REG32(GPIO_PXINTS((n)))

+#define REG_GPIO_PXINTC(n)	REG32(GPIO_PXINTC((n)))

+

+#define REG_GPIO_PXMASK(n)	REG32(GPIO_PXMASK((n)))   /* 1: mask pin interrupt */

+#define REG_GPIO_PXMASKS(n)	REG32(GPIO_PXMASKS((n)))

+#define REG_GPIO_PXMASKC(n)	REG32(GPIO_PXMASKC((n)))

+#define REG_GPIO_PXMASK(n)	REG32(GPIO_PXMASK((n)))   /* 1: mask pin interrupt */

+#define REG_GPIO_PXMASKS(n)	REG32(GPIO_PXMASKS((n)))

+#define REG_GPIO_PXMASKC(n)	REG32(GPIO_PXMASKC((n)))

+#define REG_GPIO_PXPAT1(n)	REG32(GPIO_PXPAT1((n)))   /* 1: disable pull up/down */

+#define REG_GPIO_PXPAT1S(n)	REG32(GPIO_PXPAT1S((n)))

+#define REG_GPIO_PXPAT1C(n)	REG32(GPIO_PXPAT1C((n)))

+#define REG_GPIO_PXPAT0(n)	REG32(GPIO_PXPAT0((n)))  /* 0:GPIO/INTR, 1:FUNC */

+#define REG_GPIO_PXPAT0S(n)	REG32(GPIO_PXPAT0S((n)))

+#define REG_GPIO_PXPAT0C(n)	REG32(GPIO_PXPAT0C((n)))

+#define REG_GPIO_PXFLG(n)	REG32(GPIO_PXFLG((n))) /* 0:GPIO/Fun0,1:intr/fun1*/

+#define REG_GPIO_PXFLGC(n)	REG32(GPIO_PXFLGC((n)))

+#define REG_GPIO_PXOEN(n)	REG32(GPIO_PXOEN((n)))

+#define REG_GPIO_PXOENS(n)	REG32(GPIO_PXOENS((n))) /* 0:input/low-level-trig/falling-edge-trig, 1:output/high-level-trig/rising-edge-trig */

+#define REG_GPIO_PXOENC(n)	REG32(GPIO_PXOENC((n)))

+#define REG_GPIO_PXPEN(n)	REG32(GPIO_PXPEN((n)))

+#define REG_GPIO_PXPENS(n)	REG32(GPIO_PXPENS((n))) /* 0:Level-trigger/Fun0, 1:Edge-trigger/Fun1 */

+#define REG_GPIO_PXPENC(n)	REG32(GPIO_PXPENC((n)))

+#define REG_GPIO_PXDS(n)	REG32(GPIO_PXDS((n)))

+#define REG_GPIO_PXDSS(n)	REG32(GPIO_PXDSS((n))) /* interrupt flag */

+#define REG_GPIO_PXDSC(n)	REG32(GPIO_PXDSC((n))) /* interrupt flag */

+

+#ifndef __MIPS_ASSEMBLER

+

+/*----------------------------------------------------------------

+ * p is the port number (0,1,2,3,4,5)

+ * o is the pin offset (0-31) inside the port

+ * n is the absolute number of a pin (0-127), regardless of the port

+ */

+

+//----------------------------------------------------------------

+// Function Pins Mode

+#define __gpio_as_func0(n)			\

+do {						\

+	unsigned int p, o;			\

+	p = (n) / 32;				\

+	o = (n) % 32;				\

+	REG_GPIO_PXINTC(p) = (1 << o);		\

+	REG_GPIO_PXMASKC(p) = (1 << o);		\

+	REG_GPIO_PXPAT1C(p) = (1 << o);		\

+	REG_GPIO_PXPAT0C(p) = (1 << o);		\

+} while (0)

+

+#define __gpio_as_func1(n)			\

+do {						\

+	unsigned int p, o;			\

+	p = (n) / 32;				\

+	o = (n) % 32;				\

+	REG_GPIO_PXINTC(p) = (1 << o);		\

+	REG_GPIO_PXMASKC(p) = (1 << o);		\

+	REG_GPIO_PXPAT1C(p) = (1 << o);		\

+	REG_GPIO_PXPAT0S(p) = (1 << o);		\

+} while (0)

+

+#define __gpio_as_func2(n)			\

+do {						\

+	unsigned int p, o;			\

+	p = (n) / 32;				\

+	o = (n) % 32;				\

+	REG_GPIO_PXINTC(p) = (1 << o);		\

+	REG_GPIO_PXMASKC(p) = (1 << o);		\

+	REG_GPIO_PXPAT1S(p) = (1 << o);		\

+	REG_GPIO_PXPAT0C(p) = (1 << o);		\

+} while (0)

+

+#define __gpio_as_func3(n)			\

+do {						\

+	unsigned int p, o;			\

+	p = (n) / 32;				\

+	o = (n) % 32;				\

+	REG_GPIO_PXINTC(p) = (1 << o);		\

+	REG_GPIO_PXMASKC(p) = (1 << o);		\

+	REG_GPIO_PXPAT1S(p) = (1 << o);		\

+	REG_GPIO_PXPAT0S(p) = (1 << o);		\

+} while (0)

+

+#if 0

+/*

+ * MII_TXD0- D3 MII_TXEN MII_TXCLK MII_COL

+ * MII_RXER MII_RXDV MII_RXCLK MII_RXD0 - D3

+ * MII_CRS MII_MDC MII_MDIO

+ */

+#define __gpio_as_eth()				\

+do {						\

+	REG_GPIO_PXINTC(1) =  0x00000010;	\

+	REG_GPIO_PXMASKC(1) = 0x00000010;	\

+	REG_GPIO_PXPAT1S(1) = 0x00000010;	\

+	REG_GPIO_PXPAT0C(1) = 0x00000010;	\

+	REG_GPIO_PXINTC(3) =  0x3c000000;	\

+	REG_GPIO_PXMASKC(3) = 0x3c000000;	\

+	REG_GPIO_PXPAT1C(3) = 0x3c000000;	\

+	REG_GPIO_PXPAT0S(3) = 0x3c000000;	\

+	REG_GPIO_PXINTC(5) =  0x0000fff0;	\

+	REG_GPIO_PXMASKC(5) = 0x0000fff0;	\

+	REG_GPIO_PXPAT1C(5) = 0x0000fff0;	\

+	REG_GPIO_PXPAT0C(5) = 0x0000fff0;	\

+} while (0)

+#endif

+

+#define __gpio_as_eth()				\

+do {						\

+	REG_GPIO_PXINTC(1) =  0x00000010;	\

+	REG_GPIO_PXMASKC(1) = 0x00000010;	\

+	REG_GPIO_PXPAT1S(1) = 0x00000010;	\

+	REG_GPIO_PXPAT0C(1) = 0x00000010;	\

+	REG_GPIO_PXINTC(3) =  0x3c000000;	\

+	REG_GPIO_PXMASKC(3) = 0x3c000000;	\

+	REG_GPIO_PXPAT1C(3) = 0x3c000000;	\

+	REG_GPIO_PXPAT0S(3) = 0x3c000000;	\

+	REG_GPIO_PXINTC(5) =  0x0000fff0;	\

+	REG_GPIO_PXMASKC(5) = 0x0000fff0;	\

+	REG_GPIO_PXPAT1C(5) = 0x0000fff0;	\

+	REG_GPIO_PXPAT0C(5) = 0x0000fff0;	\

+} while (0)

+

+

+/*

+ * UART0_TxD, UART0_RxD

+ */

+#define __gpio_as_uart0()			\

+do {						\

+	REG_GPIO_PXINTC(5) = 0x00000009;	\

+	REG_GPIO_PXMASKC(5) = 0x00000009;	\

+	REG_GPIO_PXPAT1C(5) = 0x00000009;	\

+	REG_GPIO_PXPAT0C(5) = 0x00000009;	\

+} while (0)

+

+

+/*

+ * UART0_TxD, UART0_RxD, UART0_CTS, UART0_RTS

+ */

+#define __gpio_as_uart0_ctsrts()		\

+do {						\

+	REG_GPIO_PXFUN1S(5) = 0x0000000f;	\

+	REG_GPIO_PXTRGC(5) = 0x0000000f;	\

+	REG_GPIO_PXSELC(5) = 0x0000000f;	\

+	REG_GPIO_PXPES(5) = 0x0000000f;		\

+} while (0)

+/*

+ * GPS_CLK GPS_MAG GPS_SIG

+ */

+#define __gpio_as_gps()			\

+do {						\

+	REG_GPIO_PXFUNS(5) = 0x00000007;	\

+	REG_GPIO_PXTRGC(5) = 0x00000007;	\

+	REG_GPIO_PXSELS(5) = 0x00000007;	\

+	REG_GPIO_PXPES(5) = 0x00000007;		\

+} while (0)

+

+/*

+ * UART1_TxD, UART1_RxD

+ */

+#define __gpio_as_uart1()			\

+do {						\

+	REG_GPIO_PXFUNS(3) = 0x14000000;	\

+	REG_GPIO_PXTRGC(3) = 0x14000000;	\

+	REG_GPIO_PXSELC(3) = 0x14000000;	\

+	REG_GPIO_PXPES(3)  = 0x14000000;	\

+} while (0)

+

+/*

+ * UART1_TxD, UART1_RxD, UART1_CTS, UART1_RTS

+ */

+#define __gpio_as_uart1_ctsrts()		\

+do {						\

+	REG_GPIO_PXFUNS(3) = 0x3c000000;	\

+	REG_GPIO_PXTRGC(3) = 0x3c000000;	\

+	REG_GPIO_PXSELC(3) = 0x3c000000;	\

+	REG_GPIO_PXPES(3)  = 0x3c000000;	\

+} while (0)

+

+/*

+ * UART2_TxD, UART2_RxD

+ */

+#define __gpio_as_uart2()			\

+do {						\

+	REG_GPIO_PXINTC(2) = 0x50000000;	\

+	REG_GPIO_PXMASKC(2) = 0x50000000;	\

+	REG_GPIO_PXPAT1C(2) = 0x50000000;	\

+	REG_GPIO_PXPAT0C(2)  = 0x50000000;	\

+} while (0)

+

+/*

+ * UART2_TxD, UART2_RxD, UART2_CTS, UART2_RTS

+ */

+#define __gpio_as_uart2_ctsrts()		\

+do {						\

+	REG_GPIO_PXFUNS(2) = 0xf0000000;	\

+	REG_GPIO_PXTRGC(2) = 0xf0000000;	\

+	REG_GPIO_PXSELC(2) = 0xf0000000;	\

+	REG_GPIO_PXPES(2)  = 0xf0000000;	\

+} while (0)

+

+/*

+ * UART3_TxD, UART3_RxD

+ */

+#define __gpio_as_uart3()			\

+do {						\

+	REG_GPIO_PXFUNS(4) = 0x00000028;	\

+	REG_GPIO_PXTRGC(4) = 0x00000028;	\

+	REG_GPIO_PXSELS(4) = 0x00000028;	\

+	REG_GPIO_PXPES(4)  = 0x00000028;	\

+} while (0)

+

+/*

+ * UART3_TxD, UART3_RxD, UART3_CTS, UART3_RTS

+ */

+#define __gpio_as_uart3_ctsrts()		\

+do {						\

+	REG_GPIO_PXFUNS(4) = 0x00000028;	\

+	REG_GPIO_PXTRGC(4) = 0x00000028;	\

+	REG_GPIO_PXSELS(4) = 0x00000028;	\

+	REG_GPIO_PXFUNS(4) = 0x00000300;	\

+	REG_GPIO_PXTRGC(4) = 0x00000300;	\

+	REG_GPIO_PXSELC(4) = 0x00000300;	\

+	REG_GPIO_PXPES(4)  = 0x00000328;	\

+}

+

+#define __gpio_as_uart4()			\

+do {						\

+	REG_GPIO_PXINTC(2)  = 0x00100400;	\

+	REG_GPIO_PXMASKC(2) = 0x00100400;	\

+	REG_GPIO_PXPAT1C(2) = 0x00100400;	\

+	REG_GPIO_PXPAT0C(2) = 0x00100400;	\

+} while (0)

+/*

+ * SD0 ~ SD7, CS1#, CLE, ALE, FRE#, FWE#, FRB#

+ * @n: chip select number(1 ~ 6)

+ */

+#define __gpio_as_nand_8bit(n)						\

+do {		              						\

+									\

+	REG_GPIO_PXINTC(0) = 0x000c00ff; /* SD0 ~ SD7, CS1#, FRE#, FWE# */ \

+	REG_GPIO_PXMASKC(0) = 0x000c00ff;				\

+	REG_GPIO_PXPAT1C(0) = 0x000c00ff;				\

+	REG_GPIO_PXPAT0C(0) = 0x000c00ff;				\

+	REG_GPIO_PXPENS(0) = 0x000c00ff;				\

+									\

+	REG_GPIO_PXINTC(1) = 0x00000003; /* CLE(SA2), ALE(SA3) */	\

+	REG_GPIO_PXMASKC(1) = 0x00000003;				\

+	REG_GPIO_PXPAT1C(1) = 0x00000003;				\

+	REG_GPIO_PXPAT0C(1) = 0x00000003;				\

+	REG_GPIO_PXPENS(1) = 0x00000003;				\

+									\

+	REG_GPIO_PXINTC(0) = 0x00200000 << ((n)-1); /* CSn */		\

+	REG_GPIO_PXMASKC(0) = 0x00200000 << ((n)-1);			\

+	REG_GPIO_PXPAT1C(0) = 0x00200000 << ((n)-1);			\

+	REG_GPIO_PXPAT0C(0) = 0x00200000 << ((n)-1);			\

+	REG_GPIO_PXPENS(0) = 0x00200000 << ((n)-1);			\

+									\

+	REG_GPIO_PXINTC(0) = 0x00100000; /* FRB#(input) */		\

+	REG_GPIO_PXMASKS(0) = 0x00100000;				\

+	REG_GPIO_PXPAT1S(0) = 0x00100000;				\

+	REG_GPIO_PXPENS(0) = 0x00100000;				\

+} while (0)

+

+#define __gpio_as_nand_16bit(n)						\

+do {		              						\

+									\

+	REG_GPIO_PXINTC(0) = 0x000cffff; /* SD0 ~ SD15, CS1#, FRE#, FWE# */ \

+	REG_GPIO_PXMASKC(0) = 0x000cffff;				\

+	REG_GPIO_PXPAT1C(0) = 0x000cffff;				\

+	REG_GPIO_PXPAT0C(0) = 0x000cffff;				\

+	REG_GPIO_PXPENS(0) = 0x000cffff;				\

+									\

+	REG_GPIO_PXINTC(1) = 0x00000003; /* CLE(SA2), ALE(SA3) */	\

+	REG_GPIO_PXMASKC(1) = 0x00000003;				\

+	REG_GPIO_PXPAT1C(1) = 0x00000003;				\

+	REG_GPIO_PXPAT0C(1) = 0x00000003;				\

+	REG_GPIO_PXPENS(1) = 0x00000003;				\

+									\

+	REG_GPIO_PXINTC(0) = 0x00200000 << ((n)-1); /* CSn */		\

+	REG_GPIO_PXMASKC(0) = 0x00200000 << ((n)-1);			\

+	REG_GPIO_PXPAT1C(0) = 0x00200000 << ((n)-1);			\

+	REG_GPIO_PXPAT0C(0) = 0x00200000 << ((n)-1);			\

+	REG_GPIO_PXPENS(0) = 0x00200000 << ((n)-1);			\

+									\

+	REG_GPIO_PXINTC(0) = 0x00100000; /* FRB#(input) */		\

+	REG_GPIO_PXMASKS(0) = 0x00100000;				\

+	REG_GPIO_PXPAT1S(0) = 0x00100000;				\

+	REG_GPIO_PXPENS(0) = 0x00100000;					\

+} while (0)

+

+/*

+ * CS4#, RD#, WR#, WAIT#, A0 ~ A22, D0 ~ D7

+ * @n: chip select number(1 ~ 4)

+ */

+#define __gpio_as_nor_8bit(n)						\

+do {								        \

+	/* 32/16-bit data bus */					\

+	REG_GPIO_PXFUNS(0) = 0x000000ff;				\

+	REG_GPIO_PXSELC(0) = 0x000000ff;				\

+	REG_GPIO_PXPES(0) = 0x000000ff;					\

+									\

+	REG_GPIO_PXFUNS(2) = 0x00200000 << ((n)-1); /* CSn */		\

+	REG_GPIO_PXSELC(2) = 0x00200000 << ((n)-1);			\

+	REG_GPIO_PXPES(2) = 0x00200000 << ((n)-1);			\

+									\

+	REG_GPIO_PXFUNS(1) = 0x0000ffff; /* A0~A15 */			\

+	REG_GPIO_PXSELC(1) = 0x0000ffff;				\

+	REG_GPIO_PXPES(1) = 0x0000ffff;					\

+	REG_GPIO_PXFUNS(2) = 0x06110007; /* RD#, WR#, WAIT#, A20~A22 */	\

+	REG_GPIO_PXSELC(2) = 0x06110007;				\

+	REG_GPIO_PXPES(2) = 0x06110007;					\

+	REG_GPIO_PXFUNS(2) = 0x000e0000; /* A17~A19 */	        	\

+	REG_GPIO_PXSELS(2) = 0x000e0000;				\

+	REG_GPIO_PXPES(2) = 0x000e0000;					\

+} while (0)

+

+/*

+ * CS4#, RD#, WR#, WAIT#, A0 ~ A22, D0 ~ D15

+ * @n: chip select number(1 ~ 4)

+ */

+#define __gpio_as_nor_16bit(n)						\

+do {	               							\

+	/* 32/16-bit data normal order */				\

+	REG_GPIO_PXFUNS(0) = 0x0000ffff;				\

+	REG_GPIO_PXSELC(0) = 0x0000ffff;				\

+	REG_GPIO_PXPES(0) = 0x0000ffff;					\

+									\

+	REG_GPIO_PXFUNS(2) = 0x00200000 << ((n)-1); /* CSn */		\

+	REG_GPIO_PXSELC(2) = 0x00200000 << ((n)-1);			\

+	REG_GPIO_PXPES(2) = 0x00200000 << ((n)-1);			\

+									\

+	REG_GPIO_PXFUNS(1) = 0x0000ffff; /* A0~A15 */			\

+	REG_GPIO_PXSELC(1) = 0x0000ffff;				\

+	REG_GPIO_PXPES(1) = 0x0000ffff;					\

+	REG_GPIO_PXFUNS(2) = 0x06110007; /* RD#, WR#, WAIT#, A20~A22 */	\

+	REG_GPIO_PXSELC(2) = 0x06110007;				\

+	REG_GPIO_PXPES(2) = 0x06110007;					\

+	REG_GPIO_PXFUNS(2) = 0x000e0000; /* A17~A19 */	        	\

+	REG_GPIO_PXSELS(2) = 0x000e0000;				\

+	REG_GPIO_PXPES(2) = 0x000e0000;					\

+} while (0)

+

+/*

+ * LCD_D0~LCD_D7, LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE

+ */

+#define __gpio_as_lcd_8bit()			\

+do {						\

+	REG_GPIO_PXINTC(2) = 0x000c03ff;	\

+	REG_GPIO_PXMASKC(2)  = 0x000c03ff;		\

+	REG_GPIO_PXPAT0C(2) = 0x000c03ff;	\

+	REG_GPIO_PXPAT1C(2) = 0x000c03ff;		\

+} while (0)

+

+/*

+ * LCD_R3~LCD_R7, LCD_G2~LCD_G7, LCD_B3~LCD_B7,

+ * LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE

+ */

+#define __gpio_as_lcd_16bit()			\

+do {						\

+	REG_GPIO_PXINTC(2) = 0x0f8ff3f8;	\

+	REG_GPIO_PXMASKC(2) = 0x0f8ff3f8;	\

+	REG_GPIO_PXPAT0C(2) = 0x0f8ff3f8;	\

+	REG_GPIO_PXPAT1C(2) = 0x0f8ff3f8;		\

+} while (0)

+

+/*

+ * LCD_R2~LCD_R7, LCD_G2~LCD_G7, LCD_B2~LCD_B7,

+ * LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE

+ */

+#define __gpio_as_lcd_18bit()			\

+do {						\

+	REG_GPIO_PXINTC(2) = 0x0fcff3fc;	\

+	REG_GPIO_PXMASKC(2) = 0x0fcff3fc;	\

+	REG_GPIO_PXPAT0C(2) = 0x0fcff3fc;	\

+	REG_GPIO_PXPAT1C(2) = 0x0fcff3fc;		\

+} while (0)

+

+/*

+ * LCD_R0~LCD_R7, LCD_G0~LCD_G7, LCD_B0~LCD_B7,

+ * LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE

+ */

+#define __gpio_as_lcd_24bit()			\

+do {						\

+	REG_GPIO_PXINTC(2) = 0x0fffffff;	\

+	REG_GPIO_PXMASKC(2)  = 0x0fffffff;	\

+	REG_GPIO_PXPAT0C(2) = 0x0fffffff;	\

+	REG_GPIO_PXPAT1C(2) = 0x0fffffff;		\

+} while (0)

+

+/*

+ *  LCD_CLS, LCD_SPL, LCD_PS, LCD_REV

+ */

+#define __gpio_as_lcd_special()			\

+do {						\

+	REG_GPIO_PXINTC(2) = 0x0fffffff;	\

+	REG_GPIO_PXMASKC(2) = 0x0fffffff;	\

+	REG_GPIO_PXPAT0C(2) = 0x0feffbfc;	\

+	REG_GPIO_PXPAT0S(2) = 0x00100403;	\

+	REG_GPIO_PXPAT1C(2) = 0x0fffffff;		\

+} while (0)

+

+/*

+ * CIM_D0~CIM_D7, CIM_MCLK, CIM_PCLK, CIM_VSYNC, CIM_HSYNC

+ */

+#define __gpio_as_cim()					\

+	do {						\

+		REG_GPIO_PXINTC(1) = 0x0003ffc0;	\

+		REG_GPIO_PXMASKC(1) = 0x0003ffc0;		\

+		REG_GPIO_PXPAT1C(1) = 0x0003ffc0;	\

+		REG_GPIO_PXPAT0C(1) = 0x0003ffc0;	\

+	} while (0)

+

+/*

+ * SDATO, SDATI, BCLK, SYNC, SCLK_RSTN(gpio sepc) or

+ * SDATA_OUT, SDATA_IN, BIT_CLK, SYNC, SCLK_RESET(aic spec)

+ */

+#define __gpio_as_aic()				\

+do {						\

+	REG_GPIO_PXFUNS(4) = 0x16c00000;	\

+	REG_GPIO_PXTRGC(4) = 0x02c00000;	\

+	REG_GPIO_PXTRGS(4) = 0x14000000;	\

+	REG_GPIO_PXSELC(4) = 0x14c00000;	\

+	REG_GPIO_PXSELS(4) = 0x02000000;	\

+	REG_GPIO_PXPES(4)  = 0x16c00000;	\

+} while (0)

+

+/*

+ * PCM_DIN, PCM_DOUT, PCM_CLK, PCM_SYN

+*/

+#define __gpio_as_pcm() 			\

+do {						\

+	REG_GPIO_PXFUNS(3) = 0x0000000f;	\

+	REG_GPIO_PXSELC(3) = 0x0000000f;	\

+	REG_GPIO_PXTRGC(3) = 0x0000000f; 	\

+} while (0)

+

+/*

+ * MSC0_CMD, MSC0_CLK, MSC0_D0 ~ MSC0_D7

+ */

+#define __gpio_as_msc0_8bit()			\

+do {						\

+	REG_GPIO_PXINTC(4) = 0x3ff00000;	\

+	REG_GPIO_PXMASKC(4)  = 0x3ff00000;	\

+	REG_GPIO_PXPAT0C(4) = 0x3ff00000;	\

+	REG_GPIO_PXPAT1C(4) = 0x3ff00000;	\

+} while (0)

+

+#define __gpio_as_msc1_8bit()			\

+do {						\

+	REG_GPIO_PXINTC(4) = 0x3ff00000;	\

+	REG_GPIO_PXMASKC(4)  = 0x3ff00000;	\

+	REG_GPIO_PXPAT0S(4) = 0x3ff00000;	\

+	REG_GPIO_PXPAT1C(4) = 0x3ff00000;	\

+} while (0)

+

+#define __gpio_as_msc2_8bit()			\

+do {						\

+	REG_GPIO_PXINTC(4) = 0x3ff00000;	\

+	REG_GPIO_PXMASKC(4)  = 0x3ff00000;	\

+	REG_GPIO_PXPAT0C(4) = 0x3ff00000;	\

+	REG_GPIO_PXPAT1S(4) = 0x3ff00000;	\

+} while (0)

+

+#if 0

+/*

+ * MSC0_CMD, MSC0_CLK, MSC0_D0 ~ MSC0_D3

+ */

+#define __gpio_as_msc0_4bit()			\

+do {						\

+	REG_GPIO_PXINTC(4) = 0x30f00000;	\

+	REG_GPIO_PXMASKC(4)  = 0x30f00000;	\

+	REG_GPIO_PXPAT0C(4) = 0x30f00000;	\

+	REG_GPIO_PXPAT1C(4) = 0x30f00000;	\

+} while (0)

+

+/*

+ * MSC1_CMD, MSC1_CLK, MSC1_D0 ~ MSC1_D3

+ */

+#define __gpio_as_msc1_4bit()			\

+do {						\

+	REG_GPIO_PXINTC(3) = 0x3f00000;	\

+	REG_GPIO_PXMASKC(3) = 0x3f00000;	\

+	REG_GPIO_PXPAT0C(3) = 0x3f00000;	\

+	REG_GPIO_PXPAT1C(3)  = 0x3f00000;	\

+} while (0)

+

+

+/* Port B

+ * MSC2_CMD, MSC2_CLK, MSC2_D0 ~ MSC2_D3

+ */

+#define __gpio_as_msc2_4bit_1()			\

+do {						\

+	REG_GPIO_PXINTC(1) = 0xf0300000;	\

+	REG_GPIO_PXMASKC(1) = 0xf0300000;	\

+	REG_GPIO_PXPAT0C(1) = 0xf0300000;	\

+	REG_GPIO_PXPAT1C(1)  = 0xf0300000;	\

+} while (0)

+#endif

+

+#define __gpio_as_msc 	__gpio_as_msc0_4bit /* default as msc0 4bit */

+#define __gpio_as_msc0 	__gpio_as_msc0_4bit /* msc0 default as 4bit */

+#define __gpio_as_msc1 	__gpio_as_msc1_4bit /* msc1 only support 4bit */

+

+/*

+ * TSCLK, TSSTR, TSFRM, TSFAIL, TSDI0~7

+ */

+#define __gpio_as_tssi()                        \

+do {                                            \

+        REG_GPIO_PXINTC(1) = 0xf0300000;        \

+        REG_GPIO_PXMASKC(1)  = 0xf0300000;                \

+        REG_GPIO_PXPAT0S(1) = 0xf0300000;       \

+        REG_GPIO_PXPAT1S(1) = 0xf0300000;               \

+                                                        \

+        REG_GPIO_PXINTC(1) = 0x0fc00000;        \

+        REG_GPIO_PXMASKC(1)  = 0x0fc00000;                \

+        REG_GPIO_PXPAT0C(1) = 0x0fc00000;       \

+        REG_GPIO_PXPAT1C(1) = 0x0fc00000;               \

+} while (0)

+

+

+/*

+ * SSI_CE0, SSI_CE1, SSI_GPC, SSI_CLK, SSI_DT, SSI_DR

+ */

+#define __gpio_as_ssi()				\

+do {						\

+	REG_GPIO_PXFUNS(0) = 0x002c0000; /* SSI0_CE0, SSI0_CLK, SSI0_DT	*/ \

+	REG_GPIO_PXTRGS(0) = 0x002c0000;	\

+	REG_GPIO_PXSELC(0) = 0x002c0000;	\

+	REG_GPIO_PXPES(0)  = 0x002c0000;	\

+						\

+	REG_GPIO_PXFUNS(0) = 0x00100000; /* SSI0_DR */	\

+	REG_GPIO_PXTRGC(0) = 0x00100000;	\

+	REG_GPIO_PXSELS(0) = 0x00100000;	\

+	REG_GPIO_PXPES(0)  = 0x00100000;	\

+} while (0)

+

+/*

+ * SSI_CE0, SSI_CE2, SSI_GPC, SSI_CLK, SSI_DT, SSI1_DR

+ */

+#define __gpio_as_ssi_1()			\

+do {						\

+	REG_GPIO_PXFUNS(5) = 0x0000fc00;	\

+	REG_GPIO_PXTRGC(5) = 0x0000fc00;	\

+	REG_GPIO_PXSELC(5) = 0x0000fc00;	\

+	REG_GPIO_PXPES(5)  = 0x0000fc00;	\

+} while (0)

+

+/* Port B

+ * SSI2_CE0, SSI2_CE2, SSI2_GPC, SSI2_CLK, SSI2_DT, SSI12_DR

+ */

+#define __gpio_as_ssi2_1()			\

+do {						\

+	REG_GPIO_PXFUNS(5) = 0xf0300000;	\

+	REG_GPIO_PXTRGC(5) = 0xf0300000;	\

+	REG_GPIO_PXSELS(5) = 0xf0300000;	\

+	REG_GPIO_PXPES(5)  = 0xf0300000;	\

+} while (0)

+

+

+/*

+ * I2C_SCK, I2C_SDA

+ */

+#define __gpio_as_i2c(n)				\

+	do {						\

+		REG_GPIO_PXINTC(3 + (n)) = 0xC0000000;	\

+		REG_GPIO_PXMASKC(3 + (n)) = 0xC0000000;	\

+		REG_GPIO_PXPAT1C(3 + (n)) = 0xC0000000;	\

+		REG_GPIO_PXPAT0C(3 + (n)) = 0xC0000000;	\

+	} while (0)

+

+#define __gpio_as_i2c2()				\

+	do {						\

+		REG_GPIO_PXINTC(5) = 0x00030000;	\

+		REG_GPIO_PXMASKC(5) = 0x00030000;	\

+		REG_GPIO_PXPAT1S(5) = 0x00030000;	\

+		REG_GPIO_PXPAT0C(5) = 0x00030000;	\

+	} while(0)

+/*

+ * PWM0

+ */

+#define __gpio_as_pwm0()			\

+do {						\

+	REG_GPIO_PXFUNS(4) = 0x00100000;	\

+	REG_GPIO_PXSELC(4) = 0x00100000;	\

+	REG_GPIO_PXPES(4) = 0x00100000;		\

+} while (0)

+

+/*

+ * PWM1

+ */

+#define __gpio_as_pwm1()			\

+do {						\

+	REG_GPIO_PXFUNS(5) = 0x00000800;	\

+	REG_GPIO_PXSELC(5) = 0x00000800;	\

+	REG_GPIO_PXPES(5) = 0x00000800;		\

+} while (0)

+

+/*

+ * PWM2

+ */

+#define __gpio_as_pwm2()			\

+do {						\

+	REG_GPIO_PXFUNS(4) = 0x00400000;	\

+	REG_GPIO_PXSELC(4) = 0x00400000;	\

+	REG_GPIO_PXPES(4) = 0x00400000;		\

+} while (0)

+

+/*

+ * PWM3

+ */

+#define __gpio_as_pwm3()			\

+do {						\

+	REG_GPIO_PXFUNS(4) = 0x00800000;	\

+	REG_GPIO_PXSELC(4) = 0x00800000;	\

+	REG_GPIO_PXPES(4) = 0x00800000;		\

+} while (0)

+

+/*

+ * PWM4

+ */

+#define __gpio_as_pwm4()			\

+do {						\

+	REG_GPIO_PXFUNS(4) = 0x01000000;	\

+	REG_GPIO_PXSELC(4) = 0x01000000;	\

+	REG_GPIO_PXPES(4) = 0x01000000;		\

+} while (0)

+

+/*

+ * PWM5

+ */

+#define __gpio_as_pwm5()			\

+do {						\

+	REG_GPIO_PXFUNS(4) = 0x02000000;	\

+	REG_GPIO_PXSELC(4) = 0x02000000;	\

+	REG_GPIO_PXPES(4) = 0x02000000;		\

+} while (0)

+

+/*

+ * n = 0 ~ 5

+ */

+#define __gpio_as_pwm(n)	__gpio_as_pwm##n()

+

+/*

+ * OWI - PA29 function 1

+ */

+#define __gpio_as_owi()				\

+do {						\

+	REG_GPIO_PXFUNS(0) = 0x20000000;	\

+	REG_GPIO_PXTRGC(0) = 0x20000000;	\

+	REG_GPIO_PXSELS(0) = 0x20000000;	\

+} while (0)

+

+/*

+ * SCC - PD08 function 0

+ *       PD09 function 0

+ */

+#define __gpio_as_scc()				\

+do {						\

+	REG_GPIO_PXFUNS(3) = 0xc0000300;	\

+	REG_GPIO_PXTRGC(3) = 0xc0000300;	\

+	REG_GPIO_PXSELC(3) = 0xc0000300;	\

+} while (0)

+

+#define __gpio_as_otg_drvvbus()	\

+do {	\

+	REG_GPIO_PXDATC(4) = (1 << 10);		\

+	REG_GPIO_PXPEC(4) = (1 << 10);		\

+	REG_GPIO_PXSELC(4) = (1 << 10);		\

+	REG_GPIO_PXTRGC(4) = (1 << 10);		\

+	REG_GPIO_PXFUNS(4) = (1 << 10);		\

+} while (0)

+

+//-------------------------------------------

+// GPIO or Interrupt Mode

+

+#define __gpio_get_port(p)	(REG_GPIO_PXPIN(p))

+#define __gpio_port_as_output0(p, o)		\

+do {						\

+    REG_GPIO_PXINTC(p) = (1 << (o));		\

+    REG_GPIO_PXMASKS(p) = (1 << (o));		\

+    REG_GPIO_PXPAT1C(p) = (1 << (o));		\

+    REG_GPIO_PXPAT0C(p) = (1 << (o));		\

+} while (0)

+

+#define __gpio_port_as_output1(p, o)		\

+do {						\

+    REG_GPIO_PXINTC(p) = (1 << (o));		\

+    REG_GPIO_PXMASKS(p) = (1 << (o));		\

+    REG_GPIO_PXPAT1C(p) = (1 << (o));		\

+    REG_GPIO_PXPAT0S(p) = (1 << (o));		\

+} while (0)

+

+#define __gpio_port_as_input(p, o)		\

+do {						\

+    REG_GPIO_PXINTC(p) = (1 << (o));		\

+    REG_GPIO_PXMASKS(p) = (1 << (o));		\

+    REG_GPIO_PXPAT1S(p) = (1 << (o));		\

+    REG_GPIO_PXPAT0C(p) = (1 << (o));		\

+} while (0)

+

+#define __gpio_as_output0(n)			\

+do {						\

+	unsigned int p, o;			\

+	p = (n) / 32;				\

+	o = (n) % 32;				\

+	__gpio_port_as_output0(p, o);		\

+} while (0)

+

+#define __gpio_as_output1(n)			\

+do {						\

+	unsigned int p, o;			\

+	p = (n) / 32;				\

+	o = (n) % 32;				\

+	__gpio_port_as_output1(p, o);		\

+} while (0)

+

+#define __gpio_as_input(n)			\

+do {						\

+	unsigned int p, o;			\

+	p = (n) / 32;				\

+	o = (n) % 32;				\

+	__gpio_port_as_input(p, o);		\

+} while (0)

+

+#define __gpio_set_pin(n)			\

+do {						\

+	unsigned int p, o;			\

+	p = (n) / 32;				\

+	o = (n) % 32;				\

+	REG_GPIO_PXDATS(p) = (1 << o);		\

+} while (0)

+

+#define __gpio_clear_pin(n)			\

+do {						\

+	unsigned int p, o;			\

+	p = (n) / 32;				\

+	o = (n) % 32;				\

+	REG_GPIO_PXDATC(p) = (1 << o);		\

+} while (0)

+

+#define __gpio_get_pin(n)			\

+({						\

+	unsigned int p, o, v;			\

+	p = (n) / 32;				\

+	o = (n) % 32;				\

+	if (__gpio_get_port(p) & (1 << o))	\

+		v = 1;				\

+	else					\

+		v = 0;				\

+	v;					\

+})

+

+#define __gpio_as_irq_high_level(n)		\

+do {						\

+	unsigned int p, o;			\

+	p = (n) / 32;				\

+	o = (n) % 32;				\

+	REG_GPIO_PXMASKS(p) = (1 << o);		\

+	REG_GPIO_PXTRGC(p) = (1 << o);		\

+	REG_GPIO_PXFUNC(p) = (1 << o);		\

+	REG_GPIO_PXSELS(p) = (1 << o);		\

+	REG_GPIO_PXDIRS(p) = (1 << o);		\

+	REG_GPIO_PXFLGC(p) = (1 << o);		\

+	REG_GPIO_PXMASKC(p) = (1 << o);		\

+} while (0)

+

+#define __gpio_as_irq_low_level(n)		\

+	do {					\

+		unsigned int p, o;		\

+		p = (n) / 32;			\

+		o = (n) % 32;			\

+		REG_GPIO_PXINTS(p) = (1 << o);	\

+		REG_GPIO_PXMASKC(p) = (1 << o);	\

+		REG_GPIO_PXPAT1C(p) = (1 << o);	\

+		REG_GPIO_PXPAT0C(p) = (1 << o);	\

+	} while (0)

+

+#define __gpio_as_irq_rise_edge(n)		\

+do {						\

+	unsigned int p, o;			\

+	p = (n) / 32;				\

+	o = (n) % 32;				\

+	REG_GPIO_PXMASKS(p) = (1 << o);		\

+	REG_GPIO_PXTRGS(p) = (1 << o);		\

+	REG_GPIO_PXFUNC(p) = (1 << o);		\

+	REG_GPIO_PXSELS(p) = (1 << o);		\

+	REG_GPIO_PXDIRS(p) = (1 << o);		\

+	REG_GPIO_PXFLGC(p) = (1 << o);		\

+	REG_GPIO_PXMASKC(p) = (1 << o);		\

+} while (0)

+

+#define __gpio_as_irq_fall_edge(n)		\

+do {						\

+	unsigned int p, o;			\

+	p = (n) / 32;				\

+	o = (n) % 32;				\

+	REG_GPIO_PXINTS(p) = (1 << o);  \

+        REG_GPIO_PXMASKC(p) = (1 << o);   \

+        REG_GPIO_PXPAT1S(p) = (1 << o); \

+        REG_GPIO_PXPAT0C(p) = (1 << o); \

+} while (0)

+

+#define __gpio_mask_irq(n)			\

+do {						\

+	unsigned int p, o;			\

+	p = (n) / 32;				\

+	o = (n) % 32;				\

+	REG_GPIO_PXMASKS(p) = (1 << o);		\

+} while (0)

+

+#define __gpio_unmask_irq(n)			\

+do {						\

+	unsigned int p, o;			\

+	p = (n) / 32;				\

+	o = (n) % 32;				\

+	REG_GPIO_PXMASKC(p) = (1 << o);		\

+} while (0)

+

+#define __gpio_ack_irq(n)			\

+do {						\

+	unsigned int p, o;			\

+	p = (n) / 32;				\

+	o = (n) % 32;				\

+	REG_GPIO_PXFLGC(p) = (1 << o);		\

+} while (0)

+

+#define __gpio_get_irq()			\

+({						\

+	unsigned int p, i, tmp, v = 0;		\

+	for (p = 3; p >= 0; p--) {		\

+		tmp = REG_GPIO_PXFLG(p);	\

+		for (i = 0; i < 32; i++)	\

+			if (tmp & (1 << i))	\

+				v = (32*p + i);	\

+	}					\

+	v;					\

+})

+

+#define __gpio_group_irq(n)			\

+({						\

+	register int tmp, i;			\

+	tmp = REG_GPIO_PXFLG((n));		\

+	for (i=31;i>=0;i--)			\

+		if (tmp & (1 << i))		\

+			break;			\

+	i;					\

+})

+

+#define __gpio_enable_pull(n)			\

+do {						\

+	unsigned int p, o;			\

+	p = (n) / 32;				\

+	o = (n) % 32;				\

+	REG_GPIO_PXPEC(p) = (1 << o);		\

+} while (0)

+

+#define __gpio_disable_pull(n)			\

+do {						\

+	unsigned int p, o;			\

+	p = (n) / 32;				\

+	o = (n) % 32;				\

+	REG_GPIO_PXPES(p) = (1 << o);		\

+} while (0)

+

+

+#endif /* __MIPS_ASSEMBLER */

+

+#endif /* __JZ4770GPIO_H__ */

+

diff --git a/arch/mips/include/asm/mach-jz4770/jz4770i2c.h b/arch/mips/include/asm/mach-jz4770/jz4770i2c.h
new file mode 100644
index 00000000000..36b035acc7e
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4770/jz4770i2c.h
@@ -0,0 +1,275 @@
+/*

+ * linux/include/asm-mips/mach-jz4770/jz4770i2c.h

+ *

+ * JZ4770 I2C register definition.

+ *

+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

+ */

+

+#ifndef __JZ4770I2C_H__

+#define __JZ4770I2C_H__

+

+#define JZ_I2C_NUM	3

+

+#define	I2C0_BASE	0xB0050000

+#define	I2C1_BASE	0xB0051000

+#define I2C2_BASE	0xB0055000

+

+

+/*************************************************************************

+ * I2C

+ *************************************************************************/

+#define	I2C_CTRL(n)		(I2C0_BASE + (n)*0x1000 + 0x00)

+#define	I2C_TAR(n)     		(I2C0_BASE + (n)*0x1000 + 0x04)

+#define	I2C_SAR(n)     		(I2C0_BASE + (n)*0x1000 + 0x08)

+#define	I2C_DC(n)      		(I2C0_BASE + (n)*0x1000 + 0x10)

+#define	I2C_SHCNT(n)		(I2C0_BASE + (n)*0x1000 + 0x14)

+#define	I2C_SLCNT(n)		(I2C0_BASE + (n)*0x1000 + 0x18)

+#define	I2C_FHCNT(n)		(I2C0_BASE + (n)*0x1000 + 0x1C)

+#define	I2C_FLCNT(n)		(I2C0_BASE + (n)*0x1000 + 0x20)

+#define	I2C_INTST(n)		(I2C0_BASE + (n)*0x1000 + 0x2C)

+#define	I2C_INTM(n)		(I2C0_BASE + (n)*0x1000 + 0x30)

+#define I2C_RXTL(n)		(I2C0_BASE + (n)*0x1000 + 0x38)

+#define I2C_TXTL(n)		(I2C0_BASE + (n)*0x1000 + 0x3c)

+#define	I2C_CINTR(n)		(I2C0_BASE + (n)*0x1000 + 0x40)

+#define	I2C_CRXUF(n)		(I2C0_BASE + (n)*0x1000 + 0x44)

+#define	I2C_CRXOF(n)		(I2C0_BASE + (n)*0x1000 + 0x48)

+#define	I2C_CTXOF(n)		(I2C0_BASE + (n)*0x1000 + 0x4C)

+#define	I2C_CRXREQ(n)		(I2C0_BASE + (n)*0x1000 + 0x50)

+#define	I2C_CTXABRT(n)		(I2C0_BASE + (n)*0x1000 + 0x54)

+#define	I2C_CRXDONE(n)		(I2C0_BASE + (n)*0x1000 + 0x58)

+#define	I2C_CACT(n)		(I2C0_BASE + (n)*0x1000 + 0x5C)

+#define	I2C_CSTP(n)		(I2C0_BASE + (n)*0x1000 + 0x60)

+#define	I2C_CSTT(n)		(I2C0_BASE + (n)*0x1000 + 0x64)

+#define	I2C_CGC(n)    		(I2C0_BASE + (n)*0x1000 + 0x68)

+#define	I2C_ENB(n)     		(I2C0_BASE + (n)*0x1000 + 0x6C)

+#define	I2C_STA(n)     		(I2C0_BASE + (n)*0x1000 + 0x70)

+#define I2C_TXFLR(n)		(I2C0_BASE + (n)*0x1000 + 0x74)

+#define I2C_RXFLR(n)		(I2C0_BASE + (n)*0x1000 + 0x78)

+#define	I2C_TXABRT(n)		(I2C0_BASE + (n)*0x1000 + 0x80)

+#define I2C_DMACR(n)            (I2C0_BASE + (n)*0x1000 + 0x88)

+#define I2C_DMATDLR(n)          (I2C0_BASE + (n)*0x1000 + 0x8c)

+#define I2C_DMARDLR(n)          (I2C0_BASE + (n)*0x1000 + 0x90)

+#define	I2C_SDASU(n)		(I2C0_BASE + (n)*0x1000 + 0x94)

+#define	I2C_ACKGC(n)		(I2C0_BASE + (n)*0x1000 + 0x98)

+#define	I2C_ENSTA(n)		(I2C0_BASE + (n)*0x1000 + 0x9C)

+#define I2C_SDAHD(n)		(I2C0_BASE + (n)*0x1000 + 0xD0)

+

+#define	REG_I2C_CTRL(n)		REG8(I2C_CTRL(n)) /* I2C Control Register (I2C_CTRL) */

+#define	REG_I2C_TAR(n)		REG16(I2C_TAR(n)) /* I2C target address (I2C_TAR) */

+#define REG_I2C_SAR(n)		REG16(I2C_SAR(n))

+#define REG_I2C_DC(n)		REG16(I2C_DC(n))

+#define REG_I2C_SHCNT(n)       	REG16(I2C_SHCNT(n))

+#define REG_I2C_SLCNT(n)       	REG16(I2C_SLCNT(n))

+#define REG_I2C_FHCNT(n)       	REG16(I2C_FHCNT(n))

+#define REG_I2C_FLCNT(n)       	REG16(I2C_FLCNT(n))

+#define REG_I2C_INTST(n)       	REG16(I2C_INTST(n)) /* i2c interrupt status (I2C_INTST) */

+#define REG_I2C_INTM(n)		REG16(I2C_INTM(n)) /* i2c interrupt mask status (I2C_INTM) */

+#define REG_I2C_RXTL(n)		REG8(I2C_RXTL(n))

+#define REG_I2C_TXTL(n)		REG8(I2C_TXTL(n))

+#define REG_I2C_CINTR(n)       	REG8(I2C_CINTR(n))

+#define REG_I2C_CRXUF(n)       	REG8(I2C_CRXUF(n))

+#define REG_I2C_CRXOF(n)       	REG8(I2C_CRXOF(n))

+#define REG_I2C_CTXOF(n)       	REG8(I2C_CTXOF(n))

+#define REG_I2C_CRXREQ(n)      	REG8(I2C_CRXREQ(n))

+#define REG_I2C_CTXABRT(n)     	REG8(I2C_CTXABRT(n))

+#define REG_I2C_CRXDONE(n)     	REG8(I2C_CRXDONE(n))

+#define REG_I2C_CACT(n)		REG8(I2C_CACT(n))

+#define REG_I2C_CSTP(n)		REG8(I2C_CSTP(n))

+#define REG_I2C_CSTT(n)		REG16(I2C_CSTT(n))

+#define REG_I2C_CGC(n)		REG8(I2C_CGC(n))

+#define REG_I2C_ENB(n)		REG8(I2C_ENB(n))

+#define REG_I2C_STA(n)		REG8(I2C_STA(n))

+#define REG_I2C_TXFLR(n)	REG8(I2C_TXFLR(n))

+#define REG_I2C_RXFLR(n)	REG8(I2C_RXFLR(n))

+#define REG_I2C_TXABRT(n)      	REG16(I2C_TXABRT(n))

+#define REG_I2C_DMACR(n)        REG8(I2C_DMACR(n))

+#define REG_I2C_DMATDLR(n)      REG8(I2C_DMATDLR(n))

+#define REG_I2C_DMARDLR(n)      REG8(I2C_DMARDLR(n))

+#define REG_I2C_SDASU(n)       	REG8(I2C_SDASU(n))

+#define REG_I2C_ACKGC(n)       	REG8(I2C_ACKGC(n))

+#define REG_I2C_ENSTA(n)       	REG8(I2C_ENSTA(n))

+#define REG_I2C_SDAHD(n)	REG16(I2C_SDAHD(n))

+

+/* I2C Control Register (I2C_CTRL) */

+

+#define I2C_CTRL_STPHLD		(1 << 7)

+#define I2C_CTRL_SLVDIS		(1 << 6) /* after reset slave is disabled*/

+#define I2C_CTRL_REST		(1 << 5)

+#define I2C_CTRL_MATP		(1 << 4) /* 1: 10bit address 0: 7bit addressing*/

+#define I2C_CTRL_SATP		(1 << 3) /* standard mode 100kbps */

+#define I2C_CTRL_SPDF		(2 << 1) /* fast mode 400kbps */

+#define I2C_CTRL_SPDS		(1 << 1) /* standard mode 100kbps */

+#define I2C_CTRL_MD		(1 << 0) /* master enabled*/

+

+/* I2C target address (I2C_TAR) */

+

+#define I2C_TAR_MATP		(1 << 12)

+#define I2C_TAR_SPECIAL		(1 << 11)

+#define I2C_TAR_GC_OR_START	(1 << 10)

+

+/* I2C slave address  */

+/* I2C data buffer and command (I2C_DC) */

+

+#define I2C_DC_CMD			(1 << 8) /* 1 read 0  write*/

+

+/* i2c interrupt status (I2C_INTST) */

+

+#define I2C_INTST_IGC			(1 << 11) /* */

+#define I2C_INTST_ISTT			(1 << 10)

+#define I2C_INTST_ISTP			(1 << 9)

+#define I2C_INTST_IACT			(1 << 8)

+#define I2C_INTST_RXDN			(1 << 7)

+#define I2C_INTST_TXABT			(1 << 6)

+#define I2C_INTST_RDREQ			(1 << 5)

+#define I2C_INTST_TXEMP			(1 << 4)

+#define I2C_INTST_TXOF			(1 << 3)

+#define I2C_INTST_RXFL			(1 << 2)

+#define I2C_INTST_RXOF			(1 << 1)

+#define I2C_INTST_RXUF			(1 << 0)

+

+/* i2c interrupt mask status (I2C_INTM) */

+

+#define I2C_INTM_MIGC			(1 << 11) /* */

+#define I2C_INTM_MISTT			(1 << 10)

+#define I2C_INTM_MISTP			(1 << 9)

+#define I2C_INTM_MIACT			(1 << 8)

+#define I2C_INTM_MRXDN			(1 << 7)

+#define I2C_INTM_MTXABT			(1 << 6)

+#define I2C_INTM_MRDREQ			(1 << 5)

+#define I2C_INTM_MTXEMP			(1 << 4)

+#define I2C_INTM_MTXOF			(1 << 3)

+#define I2C_INTM_MRXFL			(1 << 2)

+#define I2C_INTM_MRXOF			(1 << 1)

+#define I2C_INTM_MRXUF			(1 << 0)

+

+/* I2C Clear Combined and Individual Interrupts (I2C_CINTR) */

+

+#define I2C_CINTR_CINT

+

+/* I2C Clear TX_OVER Interrupt */

+/* I2C Clear RDREQ Interrupt */

+/* I2C Clear TX_ABRT Interrupt */

+/* I2C Clear RX_DONE Interrupt */

+/* I2C Clear ACTIVITY Interrupt */

+/* I2C Clear STOP Interrupts */

+/* I2C Clear START Interrupts */

+/* I2C Clear GEN_CALL Interrupts */

+

+/* I2C Enable (I2C_ENB) */

+

+#define I2C_ENB_I2CENB 		(1 << 0) /* Enable the i2c */

+

+/* I2C Status Register (I2C_STA) */

+

+#define I2C_STA_SLVACT		(1 << 6) /* Slave FSM is not in IDLE state */

+#define I2C_STA_MSTACT		(1 << 5) /* Master FSM is not in IDLE state */

+#define I2C_STA_RFF		(1 << 4) /* RFIFO if full */

+#define I2C_STA_RFNE		(1 << 3) /* RFIFO is not empty */

+#define I2C_STA_TFE		(1 << 2) /* TFIFO is empty */

+#define I2C_STA_TFNF		(1 << 1) /* TFIFO is not full  */

+#define I2C_STA_ACT		(1 << 0) /* I2C Activity Status */

+

+/* I2C Transmit Abort Status Register (I2C_TXABRT) */

+

+#define I2C_TXABRT_SLVRD_INTX		(1 << 15)

+#define I2C_TXABRT_SLV_ARBLOST		(1 << 14)

+#define I2C_TXABRT_SLVFLUSH_TXFIFO	(1 << 13)

+#define I2C_TXABRT_ARB_LOST		(1 << 12)

+#define I2C_TXABRT_ABRT_MASTER_DIS	(1 << 11)

+#define I2C_TXABRT_ABRT_10B_RD_NORSTRT	(1 << 10)

+#define I2C_TXABRT_SBYTE_NORSTRT	(1 << 9)

+#define I2C_TXABRT_ABRT_HS_NORSTRT	(1 << 8)

+#define I2C_TXABRT_SBYTE_ACKDET		(1 << 7)

+#define I2C_TXABRT_ABRT_HS_ACKD		(1 << 6)

+#define I2C_TXABRT_ABRT_GCALL_READ	(1 << 5)

+#define I2C_TXABRT_ABRT_GCALL_NOACK	(1 << 4)

+#define I2C_TXABRT_ABRT_XDATA_NOACK	(1 << 3)

+#define I2C_TXABRT_ABRT_10ADDR2_NOACK	(1 << 2)

+#define I2C_TXABRT_ABRT_10ADDR1_NOACK	(1 << 1)

+#define I2C_TXABRT_ABRT_7B_ADDR_NOACK	(1 << 0)

+

+/* I2C Enable Status Register (I2C_ENSTA) */

+

+#define I2C_ENSTA_SLVRDLST		(1 << 2)

+#define I2C_ENSTA_SLVDISB 		(1 << 1)

+#define I2C_ENSTA_I2CEN 		(1 << 0) /* when read as 1, i2c is deemed to be in an enabled state

+						    when read as 0, i2c is deemed completely inactive. The cpu can

+						 safely read this bit anytime .When this bit is read as 0 ,the cpu can

+						 safely read SLVRDLST and SLVDISB */

+

+#define I2C_SDASU_SETUP_TIME_BASE	0

+#define I2C_SDASU_SETUP_TIME_MASK	0xff

+

+#define I2C_SDAHD_HOLD_TIME_BASE	0

+#define I2C_SDAHD_HOLD_TIME_MASK	0xff

+#define I2C_SDAHD_HOLD_TIME_EN		(1 << 8)

+

+#ifndef __MIPS_ASSEMBLER

+

+/***************************************************************************

+ * I2C

+ ***************************************************************************/

+

+#define __i2c_enable(n)		( REG_I2C_ENB(n) = 1 )

+#define __i2c_disable(n)       	( REG_I2C_ENB(n) = 0 )

+

+#define __i2c_is_enable(n)       ( REG_I2C_ENSTA(n) & I2C_ENB_I2CENB )

+#define __i2c_is_disable(n)      ( !(REG_I2C_ENSTA(n) & I2C_ENB_I2CENB) )

+

+#define __i2c_abrt(n)            ( REG_I2C_TXABRT(n) != 0 )

+#define __i2c_master_active(n)   ( REG_I2C_STA(n) & I2C_STA_MSTACT )

+#define __i2c_abrt_7b_addr_nack(n)  ( REG_I2C_TXABRT(n) & I2C_TXABRT_ABRT_7B_ADDR_NOACK )

+#define __i2c_txfifo_is_empty(n)     ( REG_I2C_STA(n) & I2C_STA_TFE )

+#define __i2c_clear_interrupts(ret,n)    ( ret = REG_I2C_CINTR(n) )

+

+#define __i2c_dma_rd_enable(n)        SETREG8(I2C_DMACR(n),1 << 0)

+#define __i2c_dma_rd_disable(n)       CLRREG8(I2C_DMACR(n),1 << 0)

+#define __i2c_dma_td_enable(n)        SETREG8(I2C_DMACR(n),1 << 1)

+#define __i2c_dma_td_disable(n)       CLRREG8(I2C_DMACR(n),1 << 1)

+

+#define __i2c_send_stop(n)           CLRREG8(I2C_SHCNT(n), I2C_CTRL_STPHLD)

+#define __i2c_nsend_stop(n)          SETREG8(I2C_SHCNT(n), I2C_CTRL_STPHLD)

+

+#define __i2c_set_dma_td_level(n,data) OUTREG8(I2C_DMATDLR(n),data)

+#define __i2c_set_dma_rd_level(n,data) OUTREG8(I2C_DMARDLR(n),data)

+

+#define __i2c_hold_time_enable(n) SETREG16(I2C_SDAHD(n), I2C_SDAHD_HOLD_TIME_EN)

+#define __i2c_hold_time_disable(n) CLRREG16(I2C_SDAHD(n), I2C_SDAHD_HOLD_TIME_EN)

+#define __i2c_set_hold_time(n, ht)					\

+	do {								\

+		CLRREG16(I2C_SDAHD(n), I2C_SDAHD_HOLD_TIME_MASK);	\

+		SETREG16(I2C_SDAHD(n), ((ht) & I2C_SDAHD_HOLD_TIME_MASK)); \

+	} while(0)

+

+#define __i2c_set_setup_time(n, su)					\

+	do {								\

+		CLRREG16(I2C_SDASU(n), I2C_SDASU_SETUP_TIME_MASK);	\

+		SETREG16(I2C_SDASU(n), ((su) & I2C_SDASU_SETUP_TIME_MASK)); \

+	} while(0) 

+

+/* I2C standard mode high count register(I2CSHCNT) */

+#define I2CSHCNT_ADJUST(n)      (((n) - 8) < 6 ? 6 : ((n) - 8))

+

+/* I2C standard mode low count register(I2CSLCNT) */

+#define I2CSLCNT_ADJUST(n)      (((n) - 1) < 8 ? 8 : ((n) - 1))

+

+/* I2C fast mode high count register(I2CFHCNT) */

+#define I2CFHCNT_ADJUST(n)      (((n) - 8) < 6 ? 6 : ((n) - 8))

+

+/* I2C fast mode low count register(I2CFLCNT) */

+#define I2CFLCNT_ADJUST(n)      (((n) - 1) < 8 ? 8 : ((n) - 1))

+

+/*

+#define __i2c_set_clk(dev_clk, i2c_clk) \

+  ( REG_I2C_GR = (dev_clk) / (16*(i2c_clk)) - 1 )

+*/

+

+#define __i2c_read(n)		( REG_I2C_DC(n) & 0xff )

+#define __i2c_write(val,n)	( REG_I2C_DC(n) = (val) )

+

+

+#endif /* __MIPS_ASSEMBLER */

+

+#endif /* __JZ4770I2C_H__ */

+

diff --git a/arch/mips/include/asm/mach-jz4770/jz4770intc.h b/arch/mips/include/asm/mach-jz4770/jz4770intc.h
new file mode 100644
index 00000000000..4063a192dcb
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4770/jz4770intc.h
@@ -0,0 +1,116 @@
+/*

+ * linux/include/asm-mips/mach-jz4770/jz4770intc.h

+ *

+ * JZ4770 INTC register definition.

+ *

+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

+ */

+

+#ifndef __JZ4770INTC_H__

+#define __JZ4770INTC_H__

+

+

+#define	INTC_BASE	0xB0001000

+

+

+/*************************************************************************

+ * INTC (Interrupt Controller)

+ *************************************************************************/

+/* n = 0 ~ 1 */

+#define INTC_ISR(n)	(INTC_BASE + 0x00 + (n) * 0x20)

+#define INTC_IMR(n)	(INTC_BASE + 0x04 + (n) * 0x20)

+#define INTC_IMSR(n)	(INTC_BASE + 0x08 + (n) * 0x20)

+#define INTC_IMCR(n)	(INTC_BASE + 0x0c + (n) * 0x20)

+#define INTC_IPR(n)	(INTC_BASE + 0x10 + (n) * 0x20)

+//#define INTC_ISSR	(INTC_BASE + 0x18)  /* Interrupt Controller Source Set Register */

+//#define INTC_ISCR	(INTC_BASE + 0x1c)  /* Interrupt Controller Source Clear Register */

+

+#define REG_INTC_ISR(n)		REG32(INTC_ISR(n))

+#define REG_INTC_IMR(n)		REG32(INTC_IMR(n))

+#define REG_INTC_IMSR(n)	REG32(INTC_IMSR(n))

+#define REG_INTC_IMCR(n)	REG32(INTC_IMCR(n))

+#define REG_INTC_IPR(n)		REG32(INTC_IPR(n))

+//#define REG_INTC_ISSR   REG32(INTC_ISSR)

+//#define REG_INTC_ISCR   REG32(INTC_ISCR)

+

+// 1st-level interrupts

+#define IRQ_I2C1	0

+#define IRQ_I2C0	1

+#define IRQ_UART3	2

+#define IRQ_UART2	3

+#define IRQ_UART1	4

+#define IRQ_UART0	5

+#define IRQ_GPU		6

+#define IRQ_SSI1   	7

+#define IRQ_SSI0   	8

+#define IRQ_TSSI	9

+#define IRQ_BDMA	10

+#define IRQ_KBC		11

+#define IRQ_GPIO5	12

+#define IRQ_GPIO4	13

+#define IRQ_GPIO3	14

+#define IRQ_GPIO2	15

+#define IRQ_GPIO1	16

+#define IRQ_GPIO0	17

+#define IRQ_SADC	18

+#define IRQ_ETH		19

+#define IRQ_UHC		20

+#define IRQ_OTG		21

+//#define IRQ_MDMA	22

+#define IRQ_I2C2	22

+#define IRQ_DMAC1	23

+#define IRQ_DMAC0	24

+#define IRQ_TCU2	25

+#define IRQ_TCU1	26

+#define IRQ_TCU0	27

+#define IRQ_GPS		28

+#define IRQ_IPU		29

+#define IRQ_CIM		30

+#define IRQ_LCD		31

+

+#define IRQ_RTC		32

+#define IRQ_OWI		33

+#define IRQ_AIC 	34

+#define IRQ_MSC2	35

+#define IRQ_MSC1	36

+#define IRQ_MSC0	37

+#define IRQ_SCC		38

+#define IRQ_BCH		39

+#define IRQ_PCM0	40

+#define IRQ_PCM1	41

+#define IRQ_UART4	42

+#define IRQ_AOSD        43

+#define IRQ_HARB2	44

+#define IRQ_I2S2	45

+#define IRQ_CPM		47

+

+// 2nd-level interrupts

+

+#define IRQ_DMA_0	64    /* 64,65,66,67,68,69 */

+#define IRQ_DMA_1	(IRQ_DMA_0 + HALF_DMA_NUM) /* 70,71,72,73,74,75 */

+#define IRQ_MDMA_0	(IRQ_DMA_0 + MAX_DMA_NUM)   /* 76,77,78 */

+#define IRQ_BDMA_0  	(IRQ_MDMA_0 + MAX_MDMA_NUM) /* 79,80,81 */

+

+#define IRQ_GPIO_0	(IRQ_BDMA_0 + MAX_BDMA_NUM)

+

+#define NUM_INTC	48

+#define NUM_DMA         MAX_DMA_NUM	/* 12 */

+#define NUM_MDMA        MAX_MDMA_NUM	/* 3 */

+#define NUM_GPIO        MAX_GPIO_NUM	/* GPIO NUM: 192, Jz4770 real num GPIO 178 */

+

+

+#ifndef __MIPS_ASSEMBLER

+

+

+/***************************************************************************

+ * INTC

+ ***************************************************************************/

+#define __intc_unmask_irq(n)	(REG_INTC_IMCR((n)/32) = (1 << ((n)%32)))

+#define __intc_mask_irq(n)	(REG_INTC_IMSR((n)/32) = (1 << ((n)%32)))

+#define __intc_ack_irq(n)	(REG_INTC_IPR((n)/32) = (1 << ((n)%32))) /* A dummy ack, as the Pending Register is Read Only. Should we remove __intc_ack_irq() */

+

+

+#endif /* __MIPS_ASSEMBLER */

+

+#endif /* __JZ4770INTC_H__ */

+

diff --git a/arch/mips/include/asm/mach-jz4770/jz4770ipu.h b/arch/mips/include/asm/mach-jz4770/jz4770ipu.h
new file mode 100644
index 00000000000..d29f7f7e708
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4770/jz4770ipu.h
@@ -0,0 +1,328 @@
+/*

+ * linux/include/asm-mips/mach-jz4770/jz4770ipu.h

+ *

+ * JZ4770 IPU register definition.

+ *

+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

+ */

+

+#ifndef __JZ4770IPU_H__

+#define __JZ4770IPU_H__

+

+

+#define	IPU_BASE	0xB3080000

+

+/*************************************************************************

+ * IPU (Image Processing Unit)

+ *************************************************************************/

+#define IPU_V_BASE		0xB3080000

+#define IPU_P_BASE		0x13080000

+

+/* Register offset */

+#define REG_CTRL		0x0  /* IPU Control Register */

+#define REG_STATUS		0x4  /* IPU Status Register */

+#define REG_D_FMT		0x8  /* Data Format Register */

+#define REG_Y_ADDR		0xc  /* Input Y or YUV422 Packaged Data Address Register */

+#define REG_U_ADDR		0x10 /* Input U Data Address Register */

+#define REG_V_ADDR		0x14 /* Input V Data Address Register */

+#define REG_IN_FM_GS		0x18 /* Input Geometric Size Register */

+#define REG_Y_STRIDE		0x1c /* Input Y Data Line Stride Register */

+#define REG_UV_STRIDE		0x20 /* Input UV Data Line Stride Register */

+#define REG_OUT_ADDR		0x24 /* Output Frame Start Address Register */

+#define REG_OUT_GS		0x28 /* Output Geometric Size Register */

+#define REG_OUT_STRIDE		0x2c /* Output Data Line Stride Register */

+#define REG_RSZ_COEF_INDEX	0x30 /* Resize Coefficients Table Index Register */

+#define REG_CSC_CO_COEF		0x34 /* CSC C0 Coefficient Register */

+#define REG_CSC_C1_COEF		0x38 /* CSC C1 Coefficient Register */

+#define REG_CSC_C2_COEF 	0x3c /* CSC C2 Coefficient Register */

+#define REG_CSC_C3_COEF 	0x40 /* CSC C3 Coefficient Register */

+#define REG_CSC_C4_COEF 	0x44 /* CSC C4 Coefficient Register */

+#define HRSZ_LUT_BASE 		0x48 /* Horizontal Resize Coefficients Look Up Table Register group */

+#define VRSZ_LUT_BASE 		0x4c /* Virtical Resize Coefficients Look Up Table Register group */

+#define REG_CSC_OFSET_PARA	0x50 /* CSC Offset Parameter Register */

+#define REG_Y_PHY_T_ADDR	0x54 /* Input Y Physical Table Address Register */

+#define REG_U_PHY_T_ADDR	0x58 /* Input U Physical Table Address Register */

+#define REG_V_PHY_T_ADDR	0x5c /* Input V Physical Table Address Register */

+#define REG_OUT_PHY_T_ADDR	0x60 /* Output Physical Table Address Register */

+

+/* REG_CTRL: IPU Control Register */

+#define IPU_CE_SFT	0x0

+#define IPU_CE_MSK	0x1

+#define IPU_RUN_SFT	0x1

+#define IPU_RUN_MSK	0x1

+#define HRSZ_EN_SFT	0x2

+#define HRSZ_EN_MSK	0x1

+#define VRSZ_EN_SFT	0x3

+#define VRSZ_EN_MSK	0x1

+#define CSC_EN_SFT	0x4

+#define CSC_EN_MSK	0x1

+#define FM_IRQ_EN_SFT	0x5

+#define FM_IRQ_EN_MSK	0x1

+#define IPU_RST_SFT	0x6

+#define IPU_RST_MSK	0x1

+#define H_SCALE_SFT	0x8

+#define H_SCALE_MSK	0x1

+#define V_SCALE_SFT	0x9

+#define V_SCALE_MSK	0x1

+#define PKG_SEL_SFT	0xA

+#define PKG_SEL_MSK	0x1

+#define LCDC_SEL_SFT	0xB

+#define LCDC_SEL_MSK	0x1

+#define SPAGE_MAP_SFT	0xC

+#define SPAGE_MAP_MSK	0x1

+#define DPAGE_SEL_SFT	0xD

+#define DPAGE_SEL_MSK	0x1

+#define DISP_SEL_SFT	0xE

+#define DISP_SEL_MSK	0x1

+#define FIELD_CONF_EN_SFT 15

+#define FIELD_CONF_EN_MSK 1

+#define FIELD_SEL_SFT	16

+#define FIELD_SEL_MSK	1

+#define DFIX_SEL_SFT	17

+#define DFIX_SEL_MSK	1

+

+/* REG_STATUS: IPU Status Register */

+#define OUT_END_SFT	0x0

+#define OUT_END_MSK	0x1

+#define FMT_ERR_SFT	0x1

+#define FMT_ERR_MSK	0x1

+#define SIZE_ERR_SFT	0x2

+#define SIZE_ERR_MSK	0x1

+

+/* D_FMT: Data Format Register */

+#define IN_FMT_SFT	0x0

+#define IN_FMT_MSK 	0x3

+#define IN_OFT_SFT 	0x2

+#define IN_OFT_MSK 	0x3

+#define YUV_PKG_OUT_SFT	0x10

+#define YUV_PKG_OUT_MSK	0x7

+#define OUT_FMT_SFT 	0x13

+#define OUT_FMT_MSK 	0x3

+#define RGB_OUT_OFT_SFT	0x15

+#define RGB_OUT_OFT_MSK	0x7

+#define RGB888_FMT_SFT	0x18

+#define RGB888_FMT_MSK	0x1

+

+/* IN_FM_GS: Input Geometric Size Register */

+#define IN_FM_H_SFT	0x0

+#define IN_FM_H_MSK	0xFFF

+#define IN_FM_W_SFT	0x10

+#define IN_FM_W_MSK	0xFFF

+

+/* Y_STRIDE: Input Y Data Line Stride Register */

+#define Y_S_SFT		0x0

+#define Y_S_MSK		0x3FFF

+

+/* UV_STRIDE: Input UV Data Line Stride Register */

+#define V_S_SFT		0x0

+#define V_S_MSK		0x1FFF

+#define U_S_SFT 	0x10

+#define U_S_MSK		0x1FFF

+

+/* OUT_GS: Output Geometric Size Register */

+#define OUT_FM_H_SFT	0x0

+#define OUT_FM_H_MSK	0x1FFF

+#define OUT_FM_W_SFT	0x10

+#define OUT_FM_W_MSK	0x7FFF

+

+/* OUT_STRIDE: Output Data Line Stride Register */

+#define OUT_S_SFT	0x0

+#define OUT_S_MSK	0xFFFF

+

+/* RSZ_COEF_INDEX: Resize Coefficients Table Index Register */

+#define VE_IDX_SFT	0x0

+#define VE_IDX_MSK	0x1F

+#define HE_IDX_SFT	0x10

+#define HE_IDX_MSK	0x1F

+

+/* CSC_CX_COEF: CSC CX Coefficient Register */

+#define CX_COEF_SFT	0x0

+#define CX_COEF_MSK	0xFFF

+

+/* HRSZ_LUT_BASE, VRSZ_LUT_BASE: Resize Coefficients Look Up Table Register group */

+#define LUT_LEN		20

+

+#define OUT_N_SFT	0x0

+#define OUT_N_MSK	0x1

+#define IN_N_SFT	0x1

+#define IN_N_MSK	0x1

+#define W_COEF_SFT	0x2

+#define W_COEF_MSK	0x3FF

+

+/* CSC_OFSET_PARA: CSC Offset Parameter Register */

+#define CHROM_OF_SFT	0x10

+#define CHROM_OF_MSK	0xFF

+#define LUMA_OF_SFT	0x00

+#define LUMA_OF_MSK	0xFF

+

+

+#ifndef __MIPS_ASSEMBLER

+

+

+#if 0

+/*************************************************************************

+ * IPU (Image Processing Unit)

+ *************************************************************************/

+#define u32 volatile unsigned long

+

+#define write_reg(reg, val)	\

+do {				\

+	*(u32 *)(reg) = (val);	\

+} while(0)

+

+#define read_reg(reg, off)	(*(u32 *)((reg)+(off)))

+

+

+#define set_ipu_fmt(rgb_888_out_fmt, rgb_out_oft, out_fmt, yuv_pkg_out, in_oft, in_fmt ) \

+({ write_reg( (IPU_V_BASE + REG_D_FMT), ((in_fmt) & IN_FMT_MSK)<<IN_FMT_SFT \

+| ((in_oft) & IN_OFT_MSK)<< IN_OFT_SFT \

+| ((out_fmt) & OUT_FMT_MSK)<<OUT_FMT_SFT \

+| ((yuv_pkg_out) & YUV_PKG_OUT_MSK ) << YUV_PKG_OUT_SFT \

+| ((rgb_888_out_fmt) & RGB888_FMT_MSK ) << RGB888_FMT_SFT \

+| ((rgb_out_oft) & RGB_OUT_OFT_MSK ) << RGB_OUT_OFT_SFT); \

+})

+#define set_y_addr(y_addr) \

+({ write_reg( (IPU_V_BASE + REG_Y_ADDR), y_addr); \

+})

+#define set_u_addr(u_addr) \

+({ write_reg( (IPU_V_BASE + REG_U_ADDR), u_addr); \

+})

+

+#define set_v_addr(v_addr) \

+({ write_reg( (IPU_V_BASE + REG_V_ADDR), v_addr); \

+})

+

+#define set_y_phy_t_addr(y_phy_t_addr) \

+({ write_reg( (IPU_V_BASE + REG_Y_PHY_T_ADDR), y_phy_t_addr); \

+})

+

+#define set_u_phy_t_addr(u_phy_t_addr) \

+({ write_reg( (IPU_V_BASE + REG_U_PHY_T_ADDR), u_phy_t_addr); \

+})

+

+#define set_v_phy_t_addr(v_phy_t_addr) \

+({ write_reg( (IPU_V_BASE + REG_V_PHY_T_ADDR), v_phy_t_addr); \

+})

+

+#define set_out_phy_t_addr(out_phy_t_addr) \

+({ write_reg( (IPU_V_BASE + REG_OUT_PHY_T_ADDR), out_phy_t_addr); \

+})

+

+#define set_inframe_gsize(width, height, y_stride, u_stride, v_stride) \

+({ write_reg( (IPU_V_BASE + REG_IN_FM_GS), ((width) & IN_FM_W_MSK)<<IN_FM_W_SFT \

+| ((height) & IN_FM_H_MSK)<<IN_FM_H_SFT); \

+ write_reg( (IPU_V_BASE + REG_Y_STRIDE), ((y_stride) & Y_S_MSK)<<Y_S_SFT); \

+ write_reg( (IPU_V_BASE + REG_UV_STRIDE), ((u_stride) & U_S_MSK)<<U_S_SFT \

+| ((v_stride) & V_S_MSK)<<V_S_SFT); \

+})

+#define set_out_addr(out_addr) \

+({ write_reg( (IPU_V_BASE + REG_OUT_ADDR), out_addr); \

+})

+#define set_outframe_gsize(width, height, o_stride) \

+({ write_reg( (IPU_V_BASE + REG_OUT_GS), ((width) & OUT_FM_W_MSK)<<OUT_FM_W_SFT \

+| ((height) & OUT_FM_H_MSK)<<OUT_FM_H_SFT); \

+ write_reg( (IPU_V_BASE + REG_OUT_STRIDE), ((o_stride) & OUT_S_MSK)<<OUT_S_SFT); \

+})

+#define set_rsz_lut_end(h_end, v_end) \

+({ write_reg( (IPU_V_BASE + REG_RSZ_COEF_INDEX), ((h_end) & HE_IDX_MSK)<<HE_IDX_SFT \

+| ((v_end) & VE_IDX_MSK)<<VE_IDX_SFT); \

+})

+#define set_csc_c0(c0_coeff) \

+({ write_reg( (IPU_V_BASE + REG_CSC_CO_COEF), ((c0_coeff) & CX_COEF_MSK)<<CX_COEF_SFT); \

+})

+#define set_csc_c1(c1_coeff) \

+({ write_reg( (IPU_V_BASE + REG_CSC_C1_COEF), ((c1_coeff) & CX_COEF_MSK)<<CX_COEF_SFT); \

+})

+#define set_csc_c2(c2_coeff) \

+({ write_reg( (IPU_V_BASE + REG_CSC_C2_COEF), ((c2_coeff) & CX_COEF_MSK)<<CX_COEF_SFT); \

+})

+#define set_csc_c3(c3_coeff) \

+({ write_reg( (IPU_V_BASE + REG_CSC_C3_COEF), ((c3_coeff) & CX_COEF_MSK)<<CX_COEF_SFT); \

+})

+#define set_csc_c4(c4_coeff) \

+({ write_reg( (IPU_V_BASE + REG_CSC_C4_COEF), ((c4_coeff) & CX_COEF_MSK)<<CX_COEF_SFT); \

+})

+#define set_hrsz_lut_coef(coef, in_n, out_n) \

+({ write_reg( (IPU_V_BASE + HRSZ_LUT_BASE ), ((coef) & W_COEF_MSK)<<W_COEF_SFT \

+| ((in_n) & IN_N_MSK)<<IN_N_SFT | ((out_n) & OUT_N_MSK)<<OUT_N_SFT); \

+})

+#define set_vrsz_lut_coef(coef, in_n, out_n) \

+({ write_reg( (IPU_V_BASE + VRSZ_LUT_BASE), ((coef) & W_COEF_MSK)<<W_COEF_SFT \

+| ((in_n) & IN_N_MSK)<<IN_N_SFT | ((out_n) & OUT_N_MSK)<<OUT_N_SFT); \

+})

+

+#define set_primary_ctrl(vrsz_en, hrsz_en,csc_en, irq_en) \

+({ write_reg( (IPU_V_BASE + REG_CTRL), ((irq_en) & FM_IRQ_EN_MSK)<<FM_IRQ_EN_SFT \

+| ((vrsz_en) & VRSZ_EN_MSK)<<VRSZ_EN_SFT \

+| ((hrsz_en) & HRSZ_EN_MSK)<<HRSZ_EN_SFT \

+| ((csc_en) & CSC_EN_MSK)<<CSC_EN_SFT \

+| (read_reg(IPU_V_BASE, REG_CTRL)) \

+& ~(CSC_EN_MSK<<CSC_EN_SFT | FM_IRQ_EN_MSK<<FM_IRQ_EN_SFT | VRSZ_EN_MSK<<VRSZ_EN_SFT | HRSZ_EN_MSK<<HRSZ_EN_SFT ) ); \

+})

+

+#define set_source_ctrl(pkg_sel, spage_sel) \

+({ write_reg( (IPU_V_BASE + REG_CTRL), ((pkg_sel) & PKG_SEL_MSK  )<< PKG_SEL_SFT \

+| ((spage_sel) & SPAGE_MAP_MSK )<< SPAGE_MAP_SFT \

+| (read_reg(IPU_V_BASE, REG_CTRL)) \

+& ~(SPAGE_MAP_MSK << SPAGE_MAP_SFT | PKG_SEL_MSK << PKG_SEL_SFT ) ) ; \

+})

+

+#define set_out_ctrl(lcdc_sel, dpage_sel, disp_sel) \

+({ write_reg( (IPU_V_BASE + REG_CTRL), ((lcdc_sel) & LCDC_SEL_MSK  )<< LCDC_SEL_SFT \

+| ((dpage_sel) & DPAGE_SEL_MSK )<< DPAGE_SEL_SFT \

+| ((disp_sel) & DISP_SEL_MSK )<< DISP_SEL_SFT \

+| (read_reg(IPU_V_BASE, REG_CTRL)) \

+& ~(LCDC_SEL_MSK<< LCDC_SEL_SFT | DPAGE_SEL_MSK << DPAGE_SEL_SFT | DISP_SEL_MSK << DISP_SEL_SFT ) ); \

+})

+

+#define set_scale_ctrl(v_scal, h_scal) \

+({ write_reg( (IPU_V_BASE + REG_CTRL), ((v_scal) & V_SCALE_MSK)<<V_SCALE_SFT \

+| ((h_scal) & H_SCALE_MSK)<<H_SCALE_SFT \

+| (read_reg(IPU_V_BASE, REG_CTRL)) & ~(V_SCALE_MSK<<V_SCALE_SFT | H_SCALE_MSK<<H_SCALE_SFT ) ); \

+})

+

+

+#define set_csc_ofset_para(chrom_oft, luma_oft) \

+({ write_reg( (IPU_V_BASE + REG_CSC_OFSET_PARA ), ((chrom_oft) & CHROM_OF_MSK ) << CHROM_OF_SFT \

+| ((luma_oft) & LUMA_OF_MSK ) << LUMA_OF_SFT ) ; \

+})

+

+#define sw_reset_ipu() \

+({ write_reg( (IPU_V_BASE + REG_CTRL), (read_reg(IPU_V_BASE, REG_CTRL)) \

+| IPU_RST_MSK<<IPU_RST_SFT); \

+})

+#define enable_ipu() \

+({ write_reg( (IPU_V_BASE + REG_CTRL), (read_reg(IPU_V_BASE, REG_CTRL)) | 0x1); \

+})

+#define disable_ipu() \

+({ write_reg( (IPU_V_BASE + REG_CTRL), (read_reg(IPU_V_BASE, REG_CTRL)) & ~0x1); \

+})

+#define run_ipu() \

+({ write_reg( (IPU_V_BASE + REG_CTRL), (read_reg(IPU_V_BASE, REG_CTRL)) | 0x2); \

+})

+#define stop_ipu() \

+({ write_reg( (IPU_V_BASE + REG_CTRL), (read_reg(IPU_V_BASE, REG_CTRL)) & ~0x2); \

+})

+

+#define polling_end_flag() \

+({ (read_reg(IPU_V_BASE, REG_STATUS)) & 0x01; \

+})

+

+#define start_vlut_coef_write() \

+({ write_reg( (IPU_V_BASE + VRSZ_LUT_BASE), ( 0x1<<12 ) ); \

+})

+

+#define start_hlut_coef_write() \

+({ write_reg( (IPU_V_BASE + HRSZ_LUT_BASE), ( 0x01<<12 ) ); \

+})

+

+#define clear_end_flag() \

+({ write_reg( (IPU_V_BASE + REG_STATUS), 0); \

+})

+#endif /* #if 0 */

+

+

+#endif /* __MIPS_ASSEMBLER */

+

+#endif /* __JZ4770IPU_H__ */

+

diff --git a/arch/mips/include/asm/mach-jz4770/jz4770lcdc.h b/arch/mips/include/asm/mach-jz4770/jz4770lcdc.h
new file mode 100644
index 00000000000..5991dbc682e
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4770/jz4770lcdc.h
@@ -0,0 +1,874 @@
+/*

+ * linux/include/asm-mips/mach-jz4770/jz4770lcdc.h

+ *

+ * JZ4770 LCDC register definition.

+ *

+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

+ */

+

+#ifndef __JZ4770LCDC_H__

+#define __JZ4770LCDC_H__

+

+

+#define	LCD_BASE	0xB3050000

+#define	SLCD_BASE	0xB3050000

+

+

+/*************************************************************************

+ * SLCD (Smart LCD Controller)

+ *************************************************************************/

+

+#define SLCD_CFG	(SLCD_BASE + 0xA0)  /* SLCD Configure Register */

+#define SLCD_CTRL	(SLCD_BASE + 0xA4)  /* SLCD Control Register */

+#define SLCD_STATE	(SLCD_BASE + 0xA8)  /* SLCD Status Register */

+#define SLCD_DATA	(SLCD_BASE + 0xAC)  /* SLCD Data Register */

+

+#define REG_SLCD_CFG	REG32(SLCD_CFG)

+#define REG_SLCD_CTRL	REG8(SLCD_CTRL)

+#define REG_SLCD_STATE	REG8(SLCD_STATE)

+#define REG_SLCD_DATA	REG32(SLCD_DATA)

+

+/* SLCD Configure Register */

+#define SLCD_CFG_DWIDTH_BIT	10

+#define SLCD_CFG_DWIDTH_MASK	(0x7 << SLCD_CFG_DWIDTH_BIT)

+  #define SLCD_CFG_DWIDTH_18BIT	(0 << SLCD_CFG_DWIDTH_BIT)

+  #define SLCD_CFG_DWIDTH_16BIT	(1 << SLCD_CFG_DWIDTH_BIT)

+  #define SLCD_CFG_DWIDTH_8BIT_x3	(2 << SLCD_CFG_DWIDTH_BIT)

+  #define SLCD_CFG_DWIDTH_8BIT_x2	(3 << SLCD_CFG_DWIDTH_BIT)

+  #define SLCD_CFG_DWIDTH_8BIT_x1	(4 << SLCD_CFG_DWIDTH_BIT)

+  #define SLCD_CFG_DWIDTH_24BIT	(5 << SLCD_CFG_DWIDTH_BIT)

+  #define SLCD_CFG_DWIDTH_9BIT_x2	(7 << SLCD_CFG_DWIDTH_BIT)

+#define SLCD_CFG_CWIDTH_BIT	(8)

+#define SLCD_CFG_CWIDTH_MASK	(0x7 << SLCD_CFG_CWIDTH_BIT)

+#define SLCD_CFG_CWIDTH_16BIT	(0 << SLCD_CFG_CWIDTH_BIT)

+#define SLCD_CFG_CWIDTH_8BIT	(1 << SLCD_CFG_CWIDTH_BIT)

+#define SLCD_CFG_CWIDTH_18BIT	(2 << SLCD_CFG_CWIDTH_BIT)

+#define SLCD_CFG_CWIDTH_24BIT	(3 << SLCD_CFG_CWIDTH_BIT)

+#define SLCD_CFG_CS_ACTIVE_LOW	(0 << 4)

+#define SLCD_CFG_CS_ACTIVE_HIGH	(1 << 4)

+#define SLCD_CFG_RS_CMD_LOW	(0 << 3)

+#define SLCD_CFG_RS_CMD_HIGH	(1 << 3)

+#define SLCD_CFG_CLK_ACTIVE_FALLING	(0 << 1)

+#define SLCD_CFG_CLK_ACTIVE_RISING	(1 << 1)

+#define SLCD_CFG_TYPE_PARALLEL	(0 << 0)

+#define SLCD_CFG_TYPE_SERIAL	(1 << 0)

+

+/* SLCD Control Register */

+#define SLCD_CTRL_DMA_MODE	(1 << 2)

+#define SLCD_CTRL_DMA_START	(1 << 1)

+#define SLCD_CTRL_DMA_EN	(1 << 0)

+

+/* SLCD Status Register */

+#define SLCD_STATE_BUSY		(1 << 0)

+

+/* SLCD Data Register */

+#define SLCD_DATA_RS_DATA	(0 << 31)

+#define SLCD_DATA_RS_COMMAND	(1 << 31)

+

+/*************************************************************************

+ * LCD (LCD Controller)

+ *************************************************************************/

+#define LCD_CFG		(LCD_BASE + 0x00) /* LCD Configure Register */

+#define LCD_CTRL	(LCD_BASE + 0x30) /* LCD Control Register */

+#define LCD_STATE	(LCD_BASE + 0x34) /* LCD Status Register */

+

+#define LCD_OSDC	(LCD_BASE + 0x100) /* LCD OSD Configure Register */

+#define LCD_OSDCTRL	(LCD_BASE + 0x104) /* LCD OSD Control Register */

+#define LCD_OSDS	(LCD_BASE + 0x108) /* LCD OSD Status Register */

+#define LCD_BGC		(LCD_BASE + 0x10C) /* LCD Background Color Register */

+#define LCD_KEY0	(LCD_BASE + 0x110) /* LCD Foreground Color Key Register 0 */

+#define LCD_KEY1	(LCD_BASE + 0x114) /* LCD Foreground Color Key Register 1 */

+#define LCD_ALPHA	(LCD_BASE + 0x118) /* LCD ALPHA Register */

+#define LCD_IPUR	(LCD_BASE + 0x11C) /* LCD IPU Restart Register */

+

+#define LCD_VAT		(LCD_BASE + 0x0c) /* Virtual Area Setting Register */

+#define LCD_DAH		(LCD_BASE + 0x10) /* Display Area Horizontal Start/End Point */

+#define LCD_DAV		(LCD_BASE + 0x14) /* Display Area Vertical Start/End Point */

+#define LCD_XYP0	(LCD_BASE + 0x120) /* Foreground 0 XY Position Register */

+#define LCD_XYP1	(LCD_BASE + 0x124) /* Foreground 1 XY Position Register */

+#define LCD_XYP0_PART2	(LCD_BASE + 0x1F0) /* Foreground 0 PART2 XY Position Register */

+#define LCD_SIZE0	(LCD_BASE + 0x128) /* Foreground 0 Size Register */

+#define LCD_SIZE1	(LCD_BASE + 0x12C) /* Foreground 1 Size Register */

+#define LCD_SIZE0_PART2	(LCD_BASE + 0x1F4) /*Foreground 0 PART2 Size Register */

+#define LCD_RGBC	(LCD_BASE + 0x90) /* RGB Controll Register */

+

+#define LCD_VSYNC	(LCD_BASE + 0x04) /* Vertical Synchronize Register */

+#define LCD_HSYNC	(LCD_BASE + 0x08) /* Horizontal Synchronize Register */

+#define LCD_PS		(LCD_BASE + 0x18) /* PS Signal Setting */

+#define LCD_CLS		(LCD_BASE + 0x1c) /* CLS Signal Setting */

+#define LCD_SPL		(LCD_BASE + 0x20) /* SPL Signal Setting */

+#define LCD_REV		(LCD_BASE + 0x24) /* REV Signal Setting */

+#define LCD_IID		(LCD_BASE + 0x38) /* Interrupt ID Register */

+#define LCD_DA0		(LCD_BASE + 0x40) /* Descriptor Address Register 0 */

+#define LCD_SA0		(LCD_BASE + 0x44) /* Source Address Register 0 */

+#define LCD_FID0	(LCD_BASE + 0x48) /* Frame ID Register 0 */

+#define LCD_CMD0	(LCD_BASE + 0x4c) /* DMA Command Register 0 */

+#define LCD_OFFS0	(LCD_BASE + 0x60) /* DMA Offsize Register 0 */

+#define LCD_PW0		(LCD_BASE + 0x64) /* DMA Page Width Register 0 */

+#define LCD_CNUM0	(LCD_BASE + 0x68) /* DMA Command Counter Register 0 */

+#define LCD_DESSIZE0	(LCD_BASE + 0x6C) /* Foreground Size in Descriptor 0 Register*/

+

+#define LCD_DA0_PART2	(LCD_BASE + 0x1C0) /* Descriptor Address Register PART2 */

+#define LCD_SA0_PART2	(LCD_BASE + 0x1C4) /* Source Address Register PART2 */

+#define LCD_FID0_PART2	(LCD_BASE + 0x1C8) /* Frame ID Register PART2 */

+#define LCD_CMD0_PART2	(LCD_BASE + 0x1CC) /* DMA Command Register PART2 */

+#define LCD_OFFS0_PART2	(LCD_BASE + 0x1E0) /* DMA Offsize Register PART2 */

+#define LCD_PW0_PART2	(LCD_BASE + 0x1E4) /* DMA Command Counter Register PART2 */

+#define LCD_CNUM0_PART2	(LCD_BASE + 0x1E8) /* Foreground Size in Descriptor PART2 Register */

+#define LCD_DESSIZE0_PART2	(LCD_BASE + 0x1EC) /*  */

+

+#define LCD_DA1		(LCD_BASE + 0x50) /* Descriptor Address Register 1 */

+#define LCD_SA1		(LCD_BASE + 0x54) /* Source Address Register 1 */

+#define LCD_FID1	(LCD_BASE + 0x58) /* Frame ID Register 1 */

+#define LCD_CMD1	(LCD_BASE + 0x5c) /* DMA Command Register 1 */

+#define LCD_OFFS1	(LCD_BASE + 0x70) /* DMA Offsize Register 1 */

+#define LCD_PW1		(LCD_BASE + 0x74) /* DMA Page Width Register 1 */

+#define LCD_CNUM1	(LCD_BASE + 0x78) /* DMA Command Counter Register 1 */

+#define LCD_DESSIZE1	(LCD_BASE + 0x7C) /* Foreground Size in Descriptor 1 Register*/

+#define LCD_PCFG        (LCD_BASE + 0xB0)

+

+#define REG_LCD_CFG	REG32(LCD_CFG)

+#define REG_LCD_CTRL	REG32(LCD_CTRL)

+#define REG_LCD_STATE	REG32(LCD_STATE)

+

+#define REG_LCD_OSDC	REG16(LCD_OSDC)

+#define REG_LCD_OSDCTRL	REG16(LCD_OSDCTRL)

+#define REG_LCD_OSDS	REG16(LCD_OSDS)

+#define REG_LCD_BGC	REG32(LCD_BGC)

+#define REG_LCD_KEY0	REG32(LCD_KEY0)

+#define REG_LCD_KEY1	REG32(LCD_KEY1)

+#define REG_LCD_ALPHA	REG8(LCD_ALPHA)

+#define REG_LCD_IPUR	REG32(LCD_IPUR)

+

+#define REG_LCD_VAT	REG32(LCD_VAT)

+#define REG_LCD_DAH	REG32(LCD_DAH)

+#define REG_LCD_DAV	REG32(LCD_DAV)

+

+#define REG_LCD_XYP0		REG32(LCD_XYP0)

+#define REG_LCD_XYP0_PART2	REG32(LCD_XYP0_PART2)

+#define REG_LCD_XYP1		REG32(LCD_XYP1)

+#define REG_LCD_SIZE0		REG32(LCD_SIZE0)

+#define REG_LCD_SIZE0_PART2	REG32(LCD_SIZE0_PART2)

+#define REG_LCD_SIZE1	REG32(LCD_SIZE1)

+

+#define REG_LCD_RGBC	REG16(LCD_RGBC)

+

+#define REG_LCD_VSYNC	REG32(LCD_VSYNC)

+#define REG_LCD_HSYNC	REG32(LCD_HSYNC)

+#define REG_LCD_PS	REG32(LCD_PS)

+#define REG_LCD_CLS	REG32(LCD_CLS)

+#define REG_LCD_SPL	REG32(LCD_SPL)

+#define REG_LCD_REV	REG32(LCD_REV)

+#define REG_LCD_IID	REG32(LCD_IID)

+#define REG_LCD_DA0	REG32(LCD_DA0)

+#define REG_LCD_SA0	REG32(LCD_SA0)

+#define REG_LCD_FID0	REG32(LCD_FID0)

+#define REG_LCD_CMD0	REG32(LCD_CMD0)

+

+#define REG_LCD_OFFS0	REG32(LCD_OFFS0)

+#define REG_LCD_PW0	REG32(LCD_PW0)

+#define REG_LCD_CNUM0	REG32(LCD_CNUM0)

+#define REG_LCD_DESSIZE0	REG32(LCD_DESSIZE0)

+

+#define REG_LCD_DA0_PART2	REG32(LCD_DA0_PART2)

+#define REG_LCD_SA0_PART2	REG32(LCD_SA0_PART2)

+#define REG_LCD_FID0_PART2	REG32(LCD_FID0_PART2)

+#define REG_LCD_CMD0_PART2	REG32(LCD_CMD0_PART2)

+#define REG_LCD_OFFS0_PART2	REG32(LCD_OFFS0_PART2)

+#define REG_LCD_PW0_PART2	REG32(LCD_PW0_PART2)

+#define REG_LCD_CNUM0_PART2	REG32(LCD_CNUM0_PART2)

+#define REG_LCD_DESSIZE0_PART2	REG32(LCD_DESSIZE0_PART2)

+

+#define REG_LCD_DA1	REG32(LCD_DA1)

+#define REG_LCD_SA1	REG32(LCD_SA1)

+#define REG_LCD_FID1	REG32(LCD_FID1)

+#define REG_LCD_CMD1	REG32(LCD_CMD1)

+#define REG_LCD_OFFS1	REG32(LCD_OFFS1)

+#define REG_LCD_PW1	REG32(LCD_PW1)

+#define REG_LCD_CNUM1	REG32(LCD_CNUM1)

+#define REG_LCD_DESSIZE1	REG32(LCD_DESSIZE1)

+#define REG_LCD_PCFG            REG32(LCD_PCFG)

+

+/* LCD Configure Register */

+#define LCD_CFG_LCDPIN_BIT	31  /* LCD pins selection */

+#define LCD_CFG_LCDPIN_MASK	(0x1 << LCD_CFG_LCDPIN_BIT)

+  #define LCD_CFG_LCDPIN_LCD	(0x0 << LCD_CFG_LCDPIN_BIT)

+  #define LCD_CFG_LCDPIN_SLCD	(0x1 << LCD_CFG_LCDPIN_BIT)

+#define LCD_CFG_TVEPEH		(1 << 30) /* TVE PAL enable extra halfline signal */

+//#define LCD_CFG_FUHOLD	(1 << 29) /* hold pixel clock when outFIFO underrun *//*keep this bit to 0*/

+#define LCD_CFG_NEWDES		(1 << 28) /* use new descripter. old: 4words, new:8words */

+#define LCD_CFG_PALBP		(1 << 27) /* bypass data format and alpha blending */

+#define LCD_CFG_TVEN		(1 << 26) /* indicate the terminal is lcd or tv */

+#define LCD_CFG_RECOVER		(1 << 25) /* Auto recover when output fifo underrun */

+#define LCD_CFG_DITHER		(1 << 24) /* Dither function */

+#define LCD_CFG_PSM		(1 << 23) /* PS signal mode */

+#define LCD_CFG_CLSM		(1 << 22) /* CLS signal mode */

+#define LCD_CFG_SPLM		(1 << 21) /* SPL signal mode */

+#define LCD_CFG_REVM		(1 << 20) /* REV signal mode */

+#define LCD_CFG_HSYNM		(1 << 19) /* HSYNC signal mode */

+#define LCD_CFG_PCLKM		(1 << 18) /* PCLK signal mode */

+#define LCD_CFG_INVDAT		(1 << 17) /* Inverse output data */

+#define LCD_CFG_SYNDIR_IN	(1 << 16) /* VSYNC&HSYNC direction */

+#define LCD_CFG_PSP		(1 << 15) /* PS pin reset state */

+#define LCD_CFG_CLSP		(1 << 14) /* CLS pin reset state */

+#define LCD_CFG_SPLP		(1 << 13) /* SPL pin reset state */

+#define LCD_CFG_REVP		(1 << 12) /* REV pin reset state */

+#define LCD_CFG_HSP		(1 << 11) /* HSYNC polarity:0-active high,1-active low */

+#define LCD_CFG_PCP		(1 << 10) /* PCLK polarity:0-rising,1-falling */

+#define LCD_CFG_DEP		(1 << 9)  /* DE polarity:0-active high,1-active low */

+#define LCD_CFG_VSP		(1 << 8)  /* VSYNC polarity:0-rising,1-falling */

+#define LCD_CFG_MODE_TFT_18BIT 	(1 << 7)  /* 18bit TFT */

+#define LCD_CFG_MODE_TFT_16BIT 	(0 << 7)  /* 16bit TFT */

+#define LCD_CFG_MODE_TFT_24BIT 	(1 << 6)  /* 24bit TFT */

+#define LCD_CFG_PDW_BIT		4  /* STN pins utilization */

+#define LCD_CFG_PDW_MASK	(0x3 << LCD_DEV_PDW_BIT)

+#define LCD_CFG_PDW_1		(0 << LCD_CFG_PDW_BIT) /* LCD_D[0] */

+  #define LCD_CFG_PDW_2		(1 << LCD_CFG_PDW_BIT) /* LCD_D[0:1] */

+  #define LCD_CFG_PDW_4		(2 << LCD_CFG_PDW_BIT) /* LCD_D[0:3]/LCD_D[8:11] */

+  #define LCD_CFG_PDW_8		(3 << LCD_CFG_PDW_BIT) /* LCD_D[0:7]/LCD_D[8:15] */

+#define LCD_CFG_MODE_BIT	0  /* Display Device Mode Select */

+#define LCD_CFG_MODE_MASK	(0x0f << LCD_CFG_MODE_BIT)

+  #define LCD_CFG_MODE_GENERIC_TFT	(0 << LCD_CFG_MODE_BIT) /* 16,18 bit TFT */

+  #define LCD_CFG_MODE_SPECIAL_TFT_1	(1 << LCD_CFG_MODE_BIT)

+  #define LCD_CFG_MODE_SPECIAL_TFT_2	(2 << LCD_CFG_MODE_BIT)

+  #define LCD_CFG_MODE_SPECIAL_TFT_3	(3 << LCD_CFG_MODE_BIT)

+  #define LCD_CFG_MODE_NONINTER_CCIR656	(4 << LCD_CFG_MODE_BIT)

+  #define LCD_CFG_MODE_INTER_CCIR656	(6 << LCD_CFG_MODE_BIT)

+  #define LCD_CFG_MODE_SINGLE_CSTN	(8 << LCD_CFG_MODE_BIT)

+  #define LCD_CFG_MODE_SINGLE_MSTN	(9 << LCD_CFG_MODE_BIT)

+  #define LCD_CFG_MODE_DUAL_CSTN	(10 << LCD_CFG_MODE_BIT)

+  #define LCD_CFG_MODE_DUAL_MSTN	(11 << LCD_CFG_MODE_BIT)

+  #define LCD_CFG_MODE_SERIAL_TFT	(12 << LCD_CFG_MODE_BIT)

+  #define LCD_CFG_MODE_LCM  		(13 << LCD_CFG_MODE_BIT)

+  #define LCD_CFG_MODE_SLCD  		LCD_CFG_MODE_LCM

+

+/* LCD Control Register */

+#define LCD_CTRL_PINMD		(1 << 30) /* This register set Pin distribution in 16-bit parallel mode

+					    0: 16-bit data correspond with LCD_D[15:0]

+					    1: 16-bit data correspond with LCD_D[17:10], LCD_D[8:1] */

+#define LCD_CTRL_BST_BIT	28  /* Burst Length Selection */

+#define LCD_CTRL_BST_MASK	(0x07 << LCD_CTRL_BST_BIT)

+  #define LCD_CTRL_BST_4	(0 << LCD_CTRL_BST_BIT) /* 4-word */

+  #define LCD_CTRL_BST_8	(1 << LCD_CTRL_BST_BIT) /* 8-word */

+  #define LCD_CTRL_BST_16	(2 << LCD_CTRL_BST_BIT) /* 16-word */

+  #define LCD_CTRL_BST_32	(3 << LCD_CTRL_BST_BIT) /* 32-word */

+#define LCD_CTRL_BST_16_CTN     (5 << LCD_CTRL_BST_BIT)

+#define LCD_CTRL_BST_64         (4 << LCD_CTRL_BST_BIT)

+#define LCD_CTRL_RGB565		(0 << 27) /* RGB565 mode(foreground 0 in OSD mode) */

+#define LCD_CTRL_RGB555		(1 << 27) /* RGB555 mode(foreground 0 in OSD mode) */

+#define LCD_CTRL_OFUP		(1 << 26) /* Output FIFO underrun protection enable */

+#define LCD_CTRL_FRC_BIT	24  /* STN FRC Algorithm Selection */

+#define LCD_CTRL_FRC_MASK	(0x03 << LCD_CTRL_FRC_BIT)

+  #define LCD_CTRL_FRC_16	(0 << LCD_CTRL_FRC_BIT) /* 16 grayscale */

+  #define LCD_CTRL_FRC_4	(1 << LCD_CTRL_FRC_BIT) /* 4 grayscale */

+  #define LCD_CTRL_FRC_2	(2 << LCD_CTRL_FRC_BIT) /* 2 grayscale */

+#define LCD_CTRL_PDD_BIT	16  /* Load Palette Delay Counter */

+#define LCD_CTRL_PDD_MASK	(0xff << LCD_CTRL_PDD_BIT)

+//#define LCD_CTRL_VGA		(1 << 15) /* VGA interface enable *//*keep this bit to 0*/

+#define LCD_CTRL_DACTE		(1 << 14) /* DAC loop back test */

+#define LCD_CTRL_EOFM		(1 << 13) /* EOF interrupt mask */

+#define LCD_CTRL_SOFM		(1 << 12) /* SOF interrupt mask */

+#define LCD_CTRL_OFUM		(1 << 11) /* Output FIFO underrun interrupt mask */

+#define LCD_CTRL_IFUM0		(1 << 10) /* Input FIFO 0 underrun interrupt mask */

+#define LCD_CTRL_IFUM1		(1 << 9)  /* Input FIFO 1 underrun interrupt mask */

+#define LCD_CTRL_LDDM		(1 << 8)  /* LCD disable done interrupt mask */

+#define LCD_CTRL_QDM		(1 << 7)  /* LCD quick disable done interrupt mask */

+#define LCD_CTRL_BEDN		(1 << 6)  /* Endian selection */

+#define LCD_CTRL_PEDN		(1 << 5)  /* Endian in byte:0-msb first, 1-lsb first */

+#define LCD_CTRL_DIS		(1 << 4)  /* Disable indicate bit */

+#define LCD_CTRL_ENA		(1 << 3)  /* LCD enable bit */

+#define LCD_CTRL_BPP_BIT	0  /* Bits Per Pixel */

+#define LCD_CTRL_BPP_MASK	(0x07 << LCD_CTRL_BPP_BIT)

+  #define LCD_CTRL_BPP_1	(0 << LCD_CTRL_BPP_BIT) /* 1 bpp */

+  #define LCD_CTRL_BPP_2	(1 << LCD_CTRL_BPP_BIT) /* 2 bpp */

+  #define LCD_CTRL_BPP_4	(2 << LCD_CTRL_BPP_BIT) /* 4 bpp */

+  #define LCD_CTRL_BPP_8	(3 << LCD_CTRL_BPP_BIT) /* 8 bpp */

+  #define LCD_CTRL_BPP_16	(4 << LCD_CTRL_BPP_BIT) /* 15/16 bpp */

+  #define LCD_CTRL_BPP_18_24	(5 << LCD_CTRL_BPP_BIT) /* 18/24/32 bpp */

+  #define LCD_CTRL_BPP_CMPS_24	(6 << LCD_CTRL_BPP_BIT) /* 24 compress bpp */

+  #define LCD_CTRL_BPP_30	(7 << LCD_CTRL_BPP_BIT) /* 30 bpp */

+

+/* LCD Status Register */

+#define LCD_STATE_QD		(1 << 7) /* Quick Disable Done */

+#define LCD_STATE_EOF		(1 << 5) /* EOF Flag */

+#define LCD_STATE_SOF		(1 << 4) /* SOF Flag */

+#define LCD_STATE_OFU		(1 << 3) /* Output FIFO Underrun */

+#define LCD_STATE_IFU0		(1 << 2) /* Input FIFO 0 Underrun */

+#define LCD_STATE_IFU1		(1 << 1) /* Input FIFO 1 Underrun */

+#define LCD_STATE_LDD		(1 << 0) /* LCD Disabled */

+

+/* OSD Configure Register */

+#define LCD_OSDC_SOFM1		(1 << 15) /* Start of frame interrupt mask for foreground 1 */

+#define LCD_OSDC_EOFM1		(1 << 14) /* End of frame interrupt mask for foreground 1 */

+#define LCD_OSDC_SOFM0		(1 << 11) /* Start of frame interrupt mask for foreground 0 */

+#define LCD_OSDC_EOFM0		(1 << 10) /* End of frame interrupt mask for foreground 0 */

+

+////////////////////////////////////////////////////////////

+#if 0//These bits always read 0, and written are ignored.

+#define LCD_OSDC_ENDM		(1 << 9) /* End of frame interrupt mask for panel. */

+#define LCD_OSDC_F0DIVMD	(1 << 8) /* Divide Foreground 0 into 2 parts.

+					  * 0: Foreground 0 only has one part. */

+#define LCD_OSDC_F0P1EN		(1 << 7) /* 1: Foreground 0 PART1 is enabled.

+					  * 0: Foreground 0 PART1 is disabled. */

+#define LCD_OSDC_F0P2MD		(1 << 6) /* 1: PART 1&2 same level and same heighth

+					  * 0: PART 1&2 have no same line */

+#define LCD_OSDC_F0P2EN		(1 << 5) /* 1: Foreground 0 PART2 is enabled.

+					  * 0: Foreground 0 PART2 is disabled.*/

+#endif

+////////////////////////////////////////////////////////////

+

+#define LCD_OSDC_F1EN		(1 << 4) /* enable foreground 1 */

+#define LCD_OSDC_F0EN		(1 << 3) /* enable foreground 0 */

+#define LCD_OSDC_ALPHAEN		(1 << 2) /* enable alpha blending */

+#define LCD_OSDC_ALPHAMD		(1 << 1) /* alpha blending mode */

+#define LCD_OSDC_OSDEN		(1 << 0) /* OSD mode enable */

+

+/* OSD Controll Register */

+#define LCD_OSDCTRL_IPU		(1 << 15) /* input data from IPU */

+#define LCD_OSDCTRL_RGB565	(0 << 4) /* foreground 1, 16bpp, 0-RGB565, 1-RGB555 */

+#define LCD_OSDCTRL_RGB555	(1 << 4) /* foreground 1, 16bpp, 0-RGB565, 1-RGB555 */

+#define LCD_OSDCTRL_CHANGES	(1 << 3) /* Change size flag */

+#define LCD_OSDCTRL_OSDBPP_BIT	0 	 /* Bits Per Pixel of OSD Channel 1 */

+#define LCD_OSDCTRL_OSDBPP_MASK	(0x7<<LCD_OSDCTRL_OSDBPP_BIT) 	 /* Bits Per Pixel of OSD Channel 1's MASK */

+  #define LCD_OSDCTRL_OSDBPP_16	(4 << LCD_OSDCTRL_OSDBPP_BIT) /* RGB 15,16 bit*/

+  #define LCD_OSDCTRL_OSDBPP_15_16	(4 << LCD_OSDCTRL_OSDBPP_BIT) /* RGB 15,16 bit*/

+  #define LCD_OSDCTRL_OSDBPP_18_24	(5 << LCD_OSDCTRL_OSDBPP_BIT) /* RGB 18,24 bit*/

+  #define LCD_OSDCTRL_OSDBPP_CMPS_24	(6 << LCD_OSDCTRL_OSDBPP_BIT) /* RGB compress 24 bit*/

+  #define LCD_OSDCTRL_OSDBPP_30		(7 << LCD_OSDCTRL_OSDBPP_BIT) /* RGB 30 bit*/

+

+/* OSD State Register */

+#define LCD_OSDS_SOF1		(1 << 15) /* Start of frame flag for foreground 1 */

+#define LCD_OSDS_EOF1		(1 << 14) /* End of frame flag for foreground 1 */

+#define LCD_OSDS_SOF0		(1 << 11) /* Start of frame flag for foreground 0 */

+#define LCD_OSDS_EOF0		(1 << 10) /* End of frame flag for foreground 0 */

+#define LCD_OSDS_READY		(1 << 0)  /* Read for accept the change */

+

+/* Background Color Register */

+#define LCD_BGC_RED_OFFSET	(1 << 16)  /* Red color offset */

+#define LCD_BGC_RED_MASK	(0xFF<<LCD_BGC_RED_OFFSET)

+#define LCD_BGC_GREEN_OFFSET	(1 << 8)   /* Green color offset */

+#define LCD_BGC_GREEN_MASK	(0xFF<<LCD_BGC_GREEN_OFFSET)

+#define LCD_BGC_BLUE_OFFSET	(1 << 0)   /* Blue color offset */

+#define LCD_BGC_BLUE_MASK	(0xFF<<LCD_BGC_BLUE_OFFSET)

+

+/* Foreground Color Key Register 0,1(foreground 0, foreground 1) */

+#define LCD_KEY_KEYEN		(1 << 31)   /* enable color key */

+#define LCD_KEY_KEYMD		(1 << 30)   /* color key mode */

+#define LCD_KEY_RED_OFFSET	16  /* Red color offset */

+#define LCD_KEY_RED_MASK	(0xFF<<LCD_KEY_RED_OFFSET)

+#define LCD_KEY_GREEN_OFFSET	8   /* Green color offset */

+#define LCD_KEY_GREEN_MASK	(0xFF<<LCD_KEY_GREEN_OFFSET)

+#define LCD_KEY_BLUE_OFFSET	0   /* Blue color offset */

+#define LCD_KEY_BLUE_MASK	(0xFF<<LCD_KEY_BLUE_OFFSET)

+#define LCD_KEY_MASK		(LCD_KEY_RED_MASK|LCD_KEY_GREEN_MASK|LCD_KEY_BLUE_MASK)

+

+/* IPU Restart Register */

+#define LCD_IPUR_IPUREN		(1 << 31)   /* IPU restart function enable*/

+#define LCD_IPUR_IPURMASK	(0xFFFFFF)   /* IPU restart value mask*/

+

+/* RGB Control Register */

+#define LCD_RGBC_RGBDM		(1 << 15)   /* enable RGB Dummy data */

+#define LCD_RGBC_DMM		(1 << 14)   /* RGB Dummy mode */

+#define LCD_RGBC_YCC		(1 << 8)    /* RGB to YCC */

+#define LCD_RGBC_ODDRGB_BIT	4	/* odd line serial RGB data arrangement */

+#define LCD_RGBC_ODDRGB_MASK	(0x7<<LCD_RGBC_ODDRGB_BIT)

+  #define LCD_RGBC_ODD_RGB	0

+  #define LCD_RGBC_ODD_RBG	1

+  #define LCD_RGBC_ODD_GRB	2

+  #define LCD_RGBC_ODD_GBR	3

+  #define LCD_RGBC_ODD_BRG	4

+  #define LCD_RGBC_ODD_BGR	5

+#define LCD_RGBC_EVENRGB_BIT	0	/* even line serial RGB data arrangement */

+#define LCD_RGBC_EVENRGB_MASK	(0x7<<LCD_RGBC_EVENRGB_BIT)

+  #define LCD_RGBC_EVEN_RGB	0

+  #define LCD_RGBC_EVEN_RBG	1

+  #define LCD_RGBC_EVEN_GRB	2

+  #define LCD_RGBC_EVEN_GBR	3

+  #define LCD_RGBC_EVEN_BRG	4

+  #define LCD_RGBC_EVEN_BGR	5

+

+/* Vertical Synchronize Register */

+#define LCD_VSYNC_VPS_BIT	16  /* VSYNC pulse start in line clock, fixed to 0 */

+#define LCD_VSYNC_VPS_MASK	(0xffff << LCD_VSYNC_VPS_BIT)

+#define LCD_VSYNC_VPE_BIT	0   /* VSYNC pulse end in line clock */

+#define LCD_VSYNC_VPE_MASK	(0xffff << LCD_VSYNC_VPS_BIT)

+

+/* Horizontal Synchronize Register */

+#define LCD_HSYNC_HPS_BIT	16  /* HSYNC pulse start position in dot clock */

+#define LCD_HSYNC_HPS_MASK	(0xffff << LCD_HSYNC_HPS_BIT)

+#define LCD_HSYNC_HPE_BIT	0   /* HSYNC pulse end position in dot clock */

+#define LCD_HSYNC_HPE_MASK	(0xffff << LCD_HSYNC_HPE_BIT)

+

+/* Virtual Area Setting Register */

+#define LCD_VAT_HT_BIT		16  /* Horizontal Total size in dot clock */

+#define LCD_VAT_HT_MASK		(0xffff << LCD_VAT_HT_BIT)

+#define LCD_VAT_VT_BIT		0   /* Vertical Total size in dot clock */

+#define LCD_VAT_VT_MASK		(0xffff << LCD_VAT_VT_BIT)

+

+/* Display Area Horizontal Start/End Point Register */

+#define LCD_DAH_HDS_BIT		16  /* Horizontal display area start in dot clock */

+#define LCD_DAH_HDS_MASK	(0xffff << LCD_DAH_HDS_BIT)

+#define LCD_DAH_HDE_BIT		0   /* Horizontal display area end in dot clock */

+#define LCD_DAH_HDE_MASK	(0xffff << LCD_DAH_HDE_BIT)

+

+/* Display Area Vertical Start/End Point Register */

+#define LCD_DAV_VDS_BIT		16  /* Vertical display area start in line clock */

+#define LCD_DAV_VDS_MASK	(0xffff << LCD_DAV_VDS_BIT)

+#define LCD_DAV_VDE_BIT		0   /* Vertical display area end in line clock */

+#define LCD_DAV_VDE_MASK	(0xffff << LCD_DAV_VDE_BIT)

+

+/* Foreground XY Position Register */

+#define LCD_XYP_YPOS_BIT	16  /* Y position bit of foreground 0 or 1 */

+#define LCD_XYP_YPOS_MASK	(0xffff << LCD_XYP_YPOS_BIT)

+#define LCD_XYP_XPOS_BIT	0   /* X position bit of foreground 0 or 1 */

+#define LCD_XYP_XPOS_MASK	(0xffff << LCD_XYP_XPOS_BIT)

+

+/* PS Signal Setting */

+#define LCD_PS_PSS_BIT		16  /* PS signal start position in dot clock */

+#define LCD_PS_PSS_MASK		(0xffff << LCD_PS_PSS_BIT)

+#define LCD_PS_PSE_BIT		0   /* PS signal end position in dot clock */

+#define LCD_PS_PSE_MASK		(0xffff << LCD_PS_PSE_BIT)

+

+/* CLS Signal Setting */

+#define LCD_CLS_CLSS_BIT	16  /* CLS signal start position in dot clock */

+#define LCD_CLS_CLSS_MASK	(0xffff << LCD_CLS_CLSS_BIT)

+#define LCD_CLS_CLSE_BIT	0   /* CLS signal end position in dot clock */

+#define LCD_CLS_CLSE_MASK	(0xffff << LCD_CLS_CLSE_BIT)

+

+/* SPL Signal Setting */

+#define LCD_SPL_SPLS_BIT	16  /* SPL signal start position in dot clock */

+#define LCD_SPL_SPLS_MASK	(0xffff << LCD_SPL_SPLS_BIT)

+#define LCD_SPL_SPLE_BIT	0   /* SPL signal end position in dot clock */

+#define LCD_SPL_SPLE_MASK	(0xffff << LCD_SPL_SPLE_BIT)

+

+/* REV Signal Setting */

+#define LCD_REV_REVS_BIT	16  /* REV signal start position in dot clock */

+#define LCD_REV_REVS_MASK	(0xffff << LCD_REV_REVS_BIT)

+

+/* DMA Command Register */

+#define LCD_CMD_SOFINT		(1 << 31)

+#define LCD_CMD_EOFINT		(1 << 30)

+#define LCD_CMD_CMD		(1 << 29) /* indicate command in slcd mode */

+#define LCD_CMD_PAL		(1 << 28)

+#define LCD_CMD_UNCOMPRESS_EN   (1 << 27)

+#define LCD_CMD_UNCOMPRESS_WITHOUT_ALPHA      (1 << 26)

+#define LCD_CMD_LEN_BIT		0

+#define LCD_CMD_LEN_MASK	(0xffffff << LCD_CMD_LEN_BIT)

+

+/* DMA Offsize Register 0,1 */

+

+/* DMA Page Width Register 0,1 */

+

+/* DMA Command Counter Register 0,1 */

+

+/* Foreground 0,1 Size Register */

+#define LCD_DESSIZE_HEIGHT_BIT	16  /* height of foreground 1 */

+#define LCD_DESSIZE_HEIGHT_MASK	(0xffff << LCD_DESSIZE_HEIGHT_BIT)

+#define LCD_DESSIZE_WIDTH_BIT	0  /* width of foreground 1 */

+#define LCD_DESSIZE_WIDTH_MASK	(0xffff << LCD_DESSIZE_WIDTH_BIT)

+

+

+#ifndef __MIPS_ASSEMBLER

+

+/*************************************************************************

+ * SLCD (Smart LCD Controller)

+ *************************************************************************/

+#define __slcd_set_data_18bit() \

+  ( REG_SLCD_CFG = (REG_SLCD_CFG & ~SLCD_CFG_DWIDTH_MASK) | SLCD_CFG_DWIDTH_18BIT )

+#define __slcd_set_data_16bit() \

+  ( REG_SLCD_CFG = (REG_SLCD_CFG & ~SLCD_CFG_DWIDTH_MASK) | SLCD_CFG_DWIDTH_16BIT )

+#define __slcd_set_data_8bit_x3() \

+  ( REG_SLCD_CFG = (REG_SLCD_CFG & ~SLCD_CFG_DWIDTH_MASK) | SLCD_CFG_DWIDTH_8BIT_x3 )

+#define __slcd_set_data_8bit_x2() \

+  ( REG_SLCD_CFG = (REG_SLCD_CFG & ~SLCD_CFG_DWIDTH_MASK) | SLCD_CFG_DWIDTH_8BIT_x2 )

+#define __slcd_set_data_8bit_x1() \

+  ( REG_SLCD_CFG = (REG_SLCD_CFG & ~SLCD_CFG_DWIDTH_MASK) | SLCD_CFG_DWIDTH_8BIT_x1 )

+#define __slcd_set_data_24bit() \

+  ( REG_SLCD_CFG = (REG_SLCD_CFG & ~SLCD_CFG_DWIDTH_MASK) | SLCD_CFG_DWIDTH_24BIT )

+#define __slcd_set_data_9bit_x2() \

+  ( REG_SLCD_CFG = (REG_SLCD_CFG & ~SLCD_CFG_DWIDTH_MASK) | SLCD_CFG_DWIDTH_9BIT_x2 )

+

+#define __slcd_set_cmd_16bit() \

+  ( REG_SLCD_CFG = (REG_SLCD_CFG & ~SLCD_CFG_CWIDTH_MASK) | SLCD_CFG_CWIDTH_16BIT )

+#define __slcd_set_cmd_8bit() \

+  ( REG_SLCD_CFG = (REG_SLCD_CFG & ~SLCD_CFG_CWIDTH_MASK) | SLCD_CFG_CWIDTH_8BIT )

+#define __slcd_set_cmd_18bit() \

+  ( REG_SLCD_CFG = (REG_SLCD_CFG & ~SLCD_CFG_CWIDTH_MASK) | SLCD_CFG_CWIDTH_18BIT )

+#define __slcd_set_cmd_24bit() \

+  ( REG_SLCD_CFG = (REG_SLCD_CFG & ~SLCD_CFG_CWIDTH_MASK) | SLCD_CFG_CWIDTH_24BIT )

+

+#define __slcd_set_cs_high()        ( REG_SLCD_CFG |= SLCD_CFG_CS_ACTIVE_HIGH )

+#define __slcd_set_cs_low()         ( REG_SLCD_CFG &= ~SLCD_CFG_CS_ACTIVE_HIGH )

+

+#define __slcd_set_rs_high()        ( REG_SLCD_CFG |= SLCD_CFG_RS_CMD_HIGH )

+#define __slcd_set_rs_low()         ( REG_SLCD_CFG &= ~SLCD_CFG_RS_CMD_HIGH )

+

+#define __slcd_set_clk_falling()    ( REG_SLCD_CFG &= ~SLCD_CFG_CLK_ACTIVE_RISING )

+#define __slcd_set_clk_rising()     ( REG_SLCD_CFG |= SLCD_CFG_CLK_ACTIVE_RISING )

+

+#define __slcd_set_parallel_type()  ( REG_SLCD_CFG &= ~SLCD_CFG_TYPE_SERIAL )

+#define __slcd_set_serial_type()    ( REG_SLCD_CFG |= SLCD_CFG_TYPE_SERIAL )

+

+/* SLCD Control Register */

+#define __slcd_enable_dma()         ( REG_SLCD_CTRL |= SLCD_CTRL_DMA_EN )

+#define __slcd_disable_dma()        ( REG_SLCD_CTRL &= ~SLCD_CTRL_DMA_EN )

+

+/* SLCD Status Register */

+#define __slcd_is_busy()            ( REG_SLCD_STATE & SLCD_STATE_BUSY )

+

+/* SLCD Data Register */

+#define __slcd_set_cmd_rs()         ( REG_SLCD_DATA |= SLCD_DATA_RS_COMMAND)

+#define __slcd_set_data_rs()        ( REG_SLCD_DATA &= ~SLCD_DATA_RS_COMMAND)

+

+

+/***************************************************************************

+ * LCD

+ ***************************************************************************/

+

+/***************************************************************************

+ * LCD

+ ***************************************************************************/

+#define __lcd_as_smart_lcd() 		( REG_LCD_CFG |= ( LCD_CFG_LCDPIN_SLCD | LCD_CFG_MODE_SLCD))

+#define __lcd_as_general_lcd() 		( REG_LCD_CFG &= ~( LCD_CFG_LCDPIN_SLCD | LCD_CFG_MODE_SLCD))

+

+#define __lcd_enable_tvepeh() 		( REG_LCD_CFG |= LCD_CFG_TVEPEH )

+#define __lcd_disable_tvepeh() 		( REG_LCD_CFG &= ~LCD_CFG_TVEPEH )

+

+#define __lcd_enable_fuhold() 		( REG_LCD_CFG |= LCD_CFG_FUHOLD )

+#define __lcd_disable_fuhold() 		( REG_LCD_CFG &= ~LCD_CFG_FUHOLD )

+

+#define __lcd_des_8word() 		( REG_LCD_CFG |= LCD_CFG_NEWDES )

+#define __lcd_des_4word() 		( REG_LCD_CFG &= ~LCD_CFG_NEWDES )

+

+#define __lcd_enable_bypass_pal() 	( REG_LCD_CFG |= LCD_CFG_PALBP )

+#define __lcd_disable_bypass_pal() 	( REG_LCD_CFG &= ~LCD_CFG_PALBP )

+

+#define __lcd_set_lcdpnl_term()		( REG_LCD_CFG |= LCD_CFG_TVEN )

+#define __lcd_set_tv_term()		( REG_LCD_CFG &= ~LCD_CFG_TVEN )

+

+#define __lcd_enable_auto_recover() 	( REG_LCD_CFG |= LCD_CFG_RECOVER )

+#define __lcd_disable_auto_recover() 	( REG_LCD_CFG &= ~LCD_CFG_RECOVER )

+

+#define __lcd_enable_dither() 	        ( REG_LCD_CFG |= LCD_CFG_DITHER )

+#define __lcd_disable_dither() 	        ( REG_LCD_CFG &= ~LCD_CFG_DITHER )

+

+#define __lcd_disable_ps_mode()	        ( REG_LCD_CFG |= LCD_CFG_PSM )

+#define __lcd_enable_ps_mode()	        ( REG_LCD_CFG &= ~LCD_CFG_PSM )

+

+#define __lcd_disable_cls_mode() 	( REG_LCD_CFG |= LCD_CFG_CLSM )

+#define __lcd_enable_cls_mode()	        ( REG_LCD_CFG &= ~LCD_CFG_CLSM )

+

+#define __lcd_disable_spl_mode() 	( REG_LCD_CFG |= LCD_CFG_SPLM )

+#define __lcd_enable_spl_mode()	        ( REG_LCD_CFG &= ~LCD_CFG_SPLM )

+

+#define __lcd_disable_rev_mode() 	( REG_LCD_CFG |= LCD_CFG_REVM )

+#define __lcd_enable_rev_mode()	        ( REG_LCD_CFG &= ~LCD_CFG_REVM )

+

+#define __lcd_disable_hsync_mode() 	( REG_LCD_CFG |= LCD_CFG_HSYNM )

+#define __lcd_enable_hsync_mode()	( REG_LCD_CFG &= ~LCD_CFG_HSYNM )

+

+#define __lcd_disable_pclk_mode() 	( REG_LCD_CFG |= LCD_CFG_PCLKM )

+#define __lcd_enable_pclk_mode()	( REG_LCD_CFG &= ~LCD_CFG_PCLKM )

+

+#define __lcd_normal_outdata()          ( REG_LCD_CFG &= ~LCD_CFG_INVDAT )

+#define __lcd_inverse_outdata()         ( REG_LCD_CFG |= LCD_CFG_INVDAT )

+

+#define __lcd_sync_input()              ( REG_LCD_CFG |= LCD_CFG_SYNDIR_IN )

+#define __lcd_sync_output()             ( REG_LCD_CFG &= ~LCD_CFG_SYNDIR_IN )

+

+#define __lcd_hsync_active_high()       ( REG_LCD_CFG &= ~LCD_CFG_HSP )

+#define __lcd_hsync_active_low()        ( REG_LCD_CFG |= LCD_CFG_HSP )

+

+#define __lcd_pclk_rising()             ( REG_LCD_CFG &= ~LCD_CFG_PCP )

+#define __lcd_pclk_falling()            ( REG_LCD_CFG |= LCD_CFG_PCP )

+

+#define __lcd_de_active_high()          ( REG_LCD_CFG &= ~LCD_CFG_DEP )

+#define __lcd_de_active_low()           ( REG_LCD_CFG |= LCD_CFG_DEP )

+

+#define __lcd_vsync_rising()            ( REG_LCD_CFG &= ~LCD_CFG_VSP )

+#define __lcd_vsync_falling()           ( REG_LCD_CFG |= LCD_CFG_VSP )

+

+#define __lcd_set_16_tftpnl() \

+  ( REG_LCD_CFG = (REG_LCD_CFG & ~LCD_CFG_MODE_TFT_MASK) | LCD_CFG_MODE_TFT_16BIT )

+

+#define __lcd_set_18_tftpnl() \

+  ( REG_LCD_CFG = (REG_LCD_CFG & ~LCD_CFG_MODE_TFT_MASK) | LCD_CFG_MODE_TFT_18BIT )

+

+#define __lcd_set_24_tftpnl()		( REG_LCD_CFG |= LCD_CFG_MODE_TFT_24BIT )

+

+/* 

+ * n=1,2,4,8 for single mono-STN 

+ * n=4,8 for dual mono-STN

+ */

+#define __lcd_set_panel_datawidth(n) 		\

+do { 						\

+	REG_LCD_CFG &= ~LCD_CFG_PDW_MASK; 	\

+	REG_LCD_CFG |= LCD_CFG_PDW_n##;		\

+} while (0)

+

+/* m = LCD_CFG_MODE_GENERUIC_TFT_xxx */

+#define __lcd_set_panel_mode(m) 		\

+do {						\

+	REG_LCD_CFG &= ~LCD_CFG_MODE_MASK;	\

+	REG_LCD_CFG |= (m);			\

+} while(0)

+

+/* n=4,8,16 */

+#define __lcd_set_burst_length(n) 		\

+do {						\

+	REG_LCD_CTRL &= ~LCD_CTRL_BST_MASK;	\

+	REG_LCD_CTRL |= LCD_CTRL_BST_n##;	\

+} while (0)

+

+#define __lcd_select_rgb565()		( REG_LCD_CTRL &= ~LCD_CTRL_RGB555 )

+#define __lcd_select_rgb555()		( REG_LCD_CTRL |= LCD_CTRL_RGB555 )

+

+#define __lcd_set_ofup()		( REG_LCD_CTRL |= LCD_CTRL_OFUP )

+#define __lcd_clr_ofup()		( REG_LCD_CTRL &= ~LCD_CTRL_OFUP )

+

+/* n=2,4,16 */

+#define __lcd_set_stn_frc(n) 			\

+do {						\

+	REG_LCD_CTRL &= ~LCD_CTRL_FRC_MASK;	\

+	REG_LCD_CTRL |= LCD_CTRL_FRC_n##;	\

+} while (0)

+

+#define __lcd_enable_eof_intr()		( REG_LCD_CTRL |= LCD_CTRL_EOFM )

+#define __lcd_disable_eof_intr()	( REG_LCD_CTRL &= ~LCD_CTRL_EOFM )

+

+#define __lcd_enable_sof_intr()		( REG_LCD_CTRL |= LCD_CTRL_SOFM )

+#define __lcd_disable_sof_intr()	( REG_LCD_CTRL &= ~LCD_CTRL_SOFM )

+

+#define __lcd_enable_ofu_intr()		( REG_LCD_CTRL |= LCD_CTRL_OFUM )

+#define __lcd_disable_ofu_intr()	( REG_LCD_CTRL &= ~LCD_CTRL_OFUM )

+

+#define __lcd_enable_ifu0_intr()	( REG_LCD_CTRL |= LCD_CTRL_IFUM0 )

+#define __lcd_disable_ifu0_intr()	( REG_LCD_CTRL &= ~LCD_CTRL_IFUM0 )

+

+#define __lcd_enable_ifu1_intr()	( REG_LCD_CTRL |= LCD_CTRL_IFUM1 )

+#define __lcd_disable_ifu1_intr()	( REG_LCD_CTRL &= ~LCD_CTRL_IFUM1 )

+

+#define __lcd_enable_ldd_intr()		( REG_LCD_CTRL |= LCD_CTRL_LDDM )

+#define __lcd_disable_ldd_intr()	( REG_LCD_CTRL &= ~LCD_CTRL_LDDM )

+

+#define __lcd_enable_qd_intr()		( REG_LCD_CTRL |= LCD_CTRL_QDM )

+#define __lcd_disable_qd_intr()		( REG_LCD_CTRL &= ~LCD_CTRL_QDM )

+

+#define __lcd_reverse_byte_endian()	( REG_LCD_CTRL |= LCD_CTRL_BEDN )

+#define __lcd_normal_byte_endian()	( REG_LCD_CTRL &= ~LCD_CTRL_BEDN )

+

+#define __lcd_pixel_endian_little()	( REG_LCD_CTRL |= LCD_CTRL_PEDN )

+#define __lcd_pixel_endian_big()	( REG_LCD_CTRL &= ~LCD_CTRL_PEDN )

+

+#define __lcd_set_dis()			( REG_LCD_CTRL |= LCD_CTRL_DIS )

+#define __lcd_clr_dis()			( REG_LCD_CTRL &= ~LCD_CTRL_DIS )

+

+#define __lcd_set_ena()			( REG_LCD_CTRL |= LCD_CTRL_ENA )

+#define __lcd_clr_ena()			( REG_LCD_CTRL &= ~LCD_CTRL_ENA )

+

+/* n=1,2,4,8,16 */

+#define __lcd_set_bpp(n) \

+  ( REG_LCD_CTRL = (REG_LCD_CTRL & ~LCD_CTRL_BPP_MASK) | LCD_CTRL_BPP_##n )

+

+/* LCD status register indication */

+

+#define __lcd_quick_disable_done()	( REG_LCD_STATE & LCD_STATE_QD )

+#define __lcd_disable_done()		( REG_LCD_STATE & LCD_STATE_LDD )

+#define __lcd_infifo0_underrun()	( REG_LCD_STATE & LCD_STATE_IFU0 )

+#define __lcd_infifo1_underrun()	( REG_LCD_STATE & LCD_STATE_IFU1 )

+#define __lcd_outfifo_underrun()	( REG_LCD_STATE & LCD_STATE_OFU )

+#define __lcd_start_of_frame()		( REG_LCD_STATE & LCD_STATE_SOF )

+#define __lcd_end_of_frame()		( REG_LCD_STATE & LCD_STATE_EOF )

+

+#define __lcd_clr_outfifounderrun()	( REG_LCD_STATE &= ~LCD_STATE_OFU )

+#define __lcd_clr_sof()			( REG_LCD_STATE &= ~LCD_STATE_SOF )

+#define __lcd_clr_eof()			( REG_LCD_STATE &= ~LCD_STATE_EOF )

+

+/* OSD functions */

+#define __lcd_enable_osd() 	(REG_LCD_OSDC |= LCD_OSDC_OSDEN)

+#define __lcd_enable_f0() 	(REG_LCD_OSDC |= LCD_OSDC_F0EN)

+#define __lcd_enable_f1()	(REG_LCD_OSDC |= LCD_OSDC_F1EN)

+#define __lcd_enable_alpha() 	(REG_LCD_OSDC |= LCD_OSDC_ALPHAEN)

+#define __lcd_enable_alphamd()	(REG_LCD_OSDC |= LCD_OSDC_ALPHAMD)

+

+#define __lcd_disable_osd()	(REG_LCD_OSDC &= ~LCD_OSDC_OSDEN)

+#define __lcd_disable_f0() 	(REG_LCD_OSDC &= ~LCD_OSDC_F0EN)

+#define __lcd_disable_f1() 	(REG_LCD_OSDC &= ~LCD_OSDC_F1EN)

+#define __lcd_disable_alpha()	(REG_LCD_OSDC &= ~LCD_OSDC_ALPHAEN)

+#define __lcd_disable_alphamd()	(REG_LCD_OSDC &= ~LCD_OSDC_ALPHAMD)

+

+/* OSD Controll Register */

+#define __lcd_fg1_use_ipu() 		(REG_LCD_OSDCTRL |= LCD_OSDCTRL_IPU)

+#define __lcd_fg1_use_dma_chan1() 	(REG_LCD_OSDCTRL &= ~LCD_OSDCTRL_IPU)

+#define __lcd_fg1_unuse_ipu() 		__lcd_fg1_use_dma_chan1()

+#define __lcd_osd_rgb555_mode()         ( REG_LCD_OSDCTRL |= LCD_OSDCTRL_RGB555 )

+#define __lcd_osd_rgb565_mode()         ( REG_LCD_OSDCTRL &= ~LCD_OSDCTRL_RGB555 )

+#define __lcd_osd_change_size()         ( REG_LCD_OSDCTRL |= LCD_OSDCTRL_CHANGES )

+#define __lcd_osd_bpp_15_16() \

+  ( REG_LCD_OSDCTRL = (REG_LCD_OSDCTRL & ~LCD_OSDCTRL_OSDBPP_MASK) | LCD_OSDCTRL_OSDBPP_15_16 )

+#define __lcd_osd_bpp_18_24() \

+  ( REG_LCD_OSDCTRL = (REG_LCD_OSDCTRL & ~LCD_OSDCTRL_OSDBPP_MASK) | LCD_OSDCTRL_OSDBPP_18_24 )

+

+/* OSD State Register */

+#define __lcd_start_of_fg1()		( REG_LCD_STATE & LCD_OSDS_SOF1 )

+#define __lcd_end_of_fg1()		( REG_LCD_STATE & LCD_OSDS_EOF1 )

+#define __lcd_start_of_fg0()		( REG_LCD_STATE & LCD_OSDS_SOF0 )

+#define __lcd_end_of_fg0()		( REG_LCD_STATE & LCD_OSDS_EOF0 )

+#define __lcd_change_is_rdy()		( REG_LCD_STATE & LCD_OSDS_READY )

+

+/* Foreground Color Key Register 0,1(foreground 0, foreground 1) */

+#define __lcd_enable_colorkey0()	(REG_LCD_KEY0 |= LCD_KEY_KEYEN)

+#define __lcd_enable_colorkey1()	(REG_LCD_KEY1 |= LCD_KEY_KEYEN)

+#define __lcd_enable_colorkey0_md() 	(REG_LCD_KEY0 |= LCD_KEY_KEYMD)

+#define __lcd_enable_colorkey1_md() 	(REG_LCD_KEY1 |= LCD_KEY_KEYMD)

+#define __lcd_set_colorkey0(key) 	(REG_LCD_KEY0 = (REG_LCD_KEY0&~0xFFFFFF)|(key))

+#define __lcd_set_colorkey1(key) 	(REG_LCD_KEY1 = (REG_LCD_KEY1&~0xFFFFFF)|(key))

+

+#define __lcd_disable_colorkey0() 	(REG_LCD_KEY0 &= ~LCD_KEY_KEYEN)

+#define __lcd_disable_colorkey1() 	(REG_LCD_KEY1 &= ~LCD_KEY_KEYEN)

+#define __lcd_disable_colorkey0_md() 	(REG_LCD_KEY0 &= ~LCD_KEY_KEYMD)

+#define __lcd_disable_colorkey1_md() 	(REG_LCD_KEY1 &= ~LCD_KEY_KEYMD)

+

+/* IPU Restart Register */

+#define __lcd_enable_ipu_restart() 	(REG_LCD_IPUR |= LCD_IPUR_IPUREN)

+#define __lcd_disable_ipu_restart() 	(REG_LCD_IPUR &= ~LCD_IPUR_IPUREN)

+#define __lcd_set_ipu_restart_triger(n)	(REG_LCD_IPUR = (REG_LCD_IPUR&(~0xFFFFFF))|(n))

+

+/* RGB Control Register */

+#define __lcd_enable_rgb_dummy() 	(REG_LCD_RGBC |= LCD_RGBC_RGBDM)

+#define __lcd_disable_rgb_dummy() 	(REG_LCD_RGBC &= ~LCD_RGBC_RGBDM)

+

+#define __lcd_dummy_rgb() 	(REG_LCD_RGBC |= LCD_RGBC_DMM)

+#define __lcd_rgb_dummy() 	(REG_LCD_RGBC &= ~LCD_RGBC_DMM)

+

+#define __lcd_rgb2ycc() 	(REG_LCD_RGBC |= LCD_RGBC_YCC)

+#define __lcd_notrgb2ycc() 	(REG_LCD_RGBC &= ~LCD_RGBC_YCC)

+

+#define __lcd_odd_mode_rgb() \

+  ( REG_LCD_RGBC = (REG_LCD_RGBC & ~LCD_RGBC_ODDRGB_MASK) | LCD_RGBC_ODD_RGB )

+#define __lcd_odd_mode_rbg() \

+  ( REG_LCD_RGBC = (REG_LCD_RGBC & ~LCD_RGBC_ODDRGB_MASK) | LCD_RGBC_ODD_RBG )

+#define __lcd_odd_mode_grb() \

+  ( REG_LCD_RGBC = (REG_LCD_RGBC & ~LCD_RGBC_ODDRGB_MASK) | LCD_RGBC_ODD_GRB)

+

+#define __lcd_odd_mode_gbr() \

+  ( REG_LCD_RGBC = (REG_LCD_RGBC & ~LCD_RGBC_ODDRGB_MASK) | LCD_RGBC_ODD_GBR)

+#define __lcd_odd_mode_brg() \

+  ( REG_LCD_RGBC = (REG_LCD_RGBC & ~LCD_RGBC_ODDRGB_MASK) | LCD_RGBC_ODD_BRG)

+#define __lcd_odd_mode_bgr() \

+  ( REG_LCD_RGBC = (REG_LCD_RGBC & ~LCD_RGBC_ODDRGB_MASK) | LCD_RGBC_ODD_BGR)

+

+#define __lcd_even_mode_rgb() \

+  ( REG_LCD_RGBC = (REG_LCD_RGBC & ~LCD_RGBC_EVENRGB_MASK) | LCD_RGBC_EVEN_RGB )

+#define __lcd_even_mode_rbg() \

+  ( REG_LCD_RGBC = (REG_LCD_RGBC & ~LCD_RGBC_EVENRGB_MASK) | LCD_RGBC_EVEN_RBG )

+#define __lcd_even_mode_grb() \

+  ( REG_LCD_RGBC = (REG_LCD_RGBC & ~LCD_RGBC_EVENRGB_MASK) | LCD_RGBC_EVEN_GRB)

+

+#define __lcd_even_mode_gbr() \

+  ( REG_LCD_RGBC = (REG_LCD_RGBC & ~LCD_RGBC_EVENRGB_MASK) | LCD_RGBC_EVEN_GBR)

+#define __lcd_even_mode_brg() \

+  ( REG_LCD_RGBC = (REG_LCD_RGBC & ~LCD_RGBC_EVENRGB_MASK) | LCD_RGBC_EVEN_BRG)

+#define __lcd_even_mode_bgr() \

+  ( REG_LCD_RGBC = (REG_LCD_RGBC & ~LCD_RGBC_EVENRGB_MASK) | LCD_RGBC_EVEN_BGR)

+

+/* Vertical Synchronize Register */

+#define __lcd_vsync_get_vps() \

+  ( (REG_LCD_VSYNC & LCD_VSYNC_VPS_MASK) >> LCD_VSYNC_VPS_BIT )

+

+#define __lcd_vsync_get_vpe() \

+  ( (REG_LCD_VSYNC & LCD_VSYNC_VPE_MASK) >> LCD_VSYNC_VPE_BIT )

+#define __lcd_vsync_set_vpe(n) 				\

+do {							\

+	REG_LCD_VSYNC &= ~LCD_VSYNC_VPE_MASK;		\

+	REG_LCD_VSYNC |= (n) << LCD_VSYNC_VPE_BIT;	\

+} while (0)

+

+#define __lcd_hsync_get_hps() \

+  ( (REG_LCD_HSYNC & LCD_HSYNC_HPS_MASK) >> LCD_HSYNC_HPS_BIT )

+#define __lcd_hsync_set_hps(n) 				\

+do {							\

+	REG_LCD_HSYNC &= ~LCD_HSYNC_HPS_MASK;		\

+	REG_LCD_HSYNC |= (n) << LCD_HSYNC_HPS_BIT;	\

+} while (0)

+

+#define __lcd_hsync_get_hpe() \

+  ( (REG_LCD_HSYNC & LCD_HSYNC_HPE_MASK) >> LCD_VSYNC_HPE_BIT )

+#define __lcd_hsync_set_hpe(n) 				\

+do {							\

+	REG_LCD_HSYNC &= ~LCD_HSYNC_HPE_MASK;		\

+	REG_LCD_HSYNC |= (n) << LCD_HSYNC_HPE_BIT;	\

+} while (0)

+

+#define __lcd_vat_get_ht() \

+  ( (REG_LCD_VAT & LCD_VAT_HT_MASK) >> LCD_VAT_HT_BIT )

+#define __lcd_vat_set_ht(n) 				\

+do {							\

+	REG_LCD_VAT &= ~LCD_VAT_HT_MASK;		\

+	REG_LCD_VAT |= (n) << LCD_VAT_HT_BIT;		\

+} while (0)

+

+#define __lcd_vat_get_vt() \

+  ( (REG_LCD_VAT & LCD_VAT_VT_MASK) >> LCD_VAT_VT_BIT )

+#define __lcd_vat_set_vt(n) 				\

+do {							\

+	REG_LCD_VAT &= ~LCD_VAT_VT_MASK;		\

+	REG_LCD_VAT |= (n) << LCD_VAT_VT_BIT;		\

+} while (0)

+

+#define __lcd_dah_get_hds() \

+  ( (REG_LCD_DAH & LCD_DAH_HDS_MASK) >> LCD_DAH_HDS_BIT )

+#define __lcd_dah_set_hds(n) 				\

+do {							\

+	REG_LCD_DAH &= ~LCD_DAH_HDS_MASK;		\

+	REG_LCD_DAH |= (n) << LCD_DAH_HDS_BIT;		\

+} while (0)

+

+#define __lcd_dah_get_hde() \

+  ( (REG_LCD_DAH & LCD_DAH_HDE_MASK) >> LCD_DAH_HDE_BIT )

+#define __lcd_dah_set_hde(n) 				\

+do {							\

+	REG_LCD_DAH &= ~LCD_DAH_HDE_MASK;		\

+	REG_LCD_DAH |= (n) << LCD_DAH_HDE_BIT;		\

+} while (0)

+

+#define __lcd_dav_get_vds() \

+  ( (REG_LCD_DAV & LCD_DAV_VDS_MASK) >> LCD_DAV_VDS_BIT )

+#define __lcd_dav_set_vds(n) 				\

+do {							\

+	REG_LCD_DAV &= ~LCD_DAV_VDS_MASK;		\

+	REG_LCD_DAV |= (n) << LCD_DAV_VDS_BIT;		\

+} while (0)

+

+#define __lcd_dav_get_vde() \

+  ( (REG_LCD_DAV & LCD_DAV_VDE_MASK) >> LCD_DAV_VDE_BIT )

+#define __lcd_dav_set_vde(n) 				\

+do {							\

+	REG_LCD_DAV &= ~LCD_DAV_VDE_MASK;		\

+	REG_LCD_DAV |= (n) << LCD_DAV_VDE_BIT;		\

+} while (0)

+

+/* DMA Command Register */

+#define __lcd_cmd0_set_sofint()		( REG_LCD_CMD0 |= LCD_CMD_SOFINT )

+#define __lcd_cmd0_clr_sofint()		( REG_LCD_CMD0 &= ~LCD_CMD_SOFINT )

+#define __lcd_cmd1_set_sofint()		( REG_LCD_CMD1 |= LCD_CMD_SOFINT )

+#define __lcd_cmd1_clr_sofint()		( REG_LCD_CMD1 &= ~LCD_CMD_SOFINT )

+

+#define __lcd_cmd0_set_eofint()		( REG_LCD_CMD0 |= LCD_CMD_EOFINT )

+#define __lcd_cmd0_clr_eofint()		( REG_LCD_CMD0 &= ~LCD_CMD_EOFINT )

+#define __lcd_cmd1_set_eofint()		( REG_LCD_CMD1 |= LCD_CMD_EOFINT )

+#define __lcd_cmd1_clr_eofint()		( REG_LCD_CMD1 &= ~LCD_CMD_EOFINT )

+

+#define __lcd_cmd0_set_pal()		( REG_LCD_CMD0 |= LCD_CMD_PAL )

+#define __lcd_cmd0_clr_pal()		( REG_LCD_CMD0 &= ~LCD_CMD_PAL )

+

+#define __lcd_cmd0_get_len() \

+  ( (REG_LCD_CMD0 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT )

+#define __lcd_cmd1_get_len() \

+  ( (REG_LCD_CMD1 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT )

+

+

+#endif /* __MIPS_ASSEMBLER */

+

+#endif /* __JZ4770LCDC_H__ */

+

diff --git a/arch/mips/include/asm/mach-jz4770/jz4770mc.h b/arch/mips/include/asm/mach-jz4770/jz4770mc.h
new file mode 100644
index 00000000000..6a2d1496f19
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4770/jz4770mc.h
@@ -0,0 +1,135 @@
+/*

+ * linux/include/asm-mips/mach-jz4810/jz4810mc.h

+ *

+ * JZ4810 MC register definition.

+ *

+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

+ */

+

+#ifndef __JZ4770MC_H__

+#define __JZ4770MC_H__

+

+

+#define	MC_BASE		0xB3250000

+

+/*************************************************************************

+ * MC (Motion Compensation)

+ *************************************************************************/

+#define MC_CTRL		(MC_BASE + 0x00) /* MC Control Register */

+#define MC_STAT		(MC_BASE + 0x04) /* MC Status Register */

+#define MC_REF_ADDR	(MC_BASE + 0x08) /* MC Reference Block Address Register */

+#define MC_REF2_ADDR	(MC_BASE + 0x0C) /* MC 2nd Reference Block Address Register */

+#define MC_CURR_ADDR	(MC_BASE + 0x10) /* MC Current Block Address Register */

+#define MC_REF_STRD	(MC_BASE + 0x14) /* MC Reference Frame Stride Register */

+#define MC_CURR_STRD	(MC_BASE + 0x18) /* MC Current Frame Stride Register */

+#define MC_ITP_INFO	(MC_BASE + 0x1C) /* MC Block Interpolation Information Register */

+#define MC_TAP_COEF1	(MC_BASE + 0x20) /* MC TAP Filter Coefficient 1 Register */

+#define MC_TAP_COEF2	(MC_BASE + 0x24) /* MC TAP Filter Coefficient 2 Register */

+

+#define REG_MC_CTRL		REG32(MC_CTRL)

+#define REG_MC_STAT		REG32(MC_STAT)

+#define REG_MC_REF_ADDR		REG32(MC_REF_ADDR)

+#define REG_MC_REF2_ADDR	REG32(MC_REF2_ADDR)

+#define REG_MC_CURR_ADDR	REG32(MC_CURR_ADDR)

+#define REG_MC_REF_STRD		REG32(MC_REF_STRD)

+#define REG_MC_CURR_STRD	REG32(MC_CURR_STRD)

+#define REG_MC_ITP_INFO		REG32(MC_ITP_INFO)

+#define REG_MC_TAP_COEF1	REG32(MC_TAP_COEF1)

+#define REG_MC_TAP_COEF2	REG32(MC_TAP_COEF2)

+

+/* MC Control Register */

+#define MC_CTRL_CACHECLR	(1 << 2) /* MC Cache clear */

+#define MC_CTRL_RESET		(1 << 1) /* MC Reset */

+#define MC_CTRL_ENABLE		(1 << 0) /* MC enable */

+

+/* MC Status Register */

+#define MC_STAT_OUT_END		(1 << 0) /* Output DMA termination flag */

+

+/* MC Reference Frame Stride Register, unit: byte */

+#define MC_REF_STRD_BIT		16

+#define MC_REF_STRD_MASK	(0xfff << MC_REF_STRD_BIT)

+#define MC_REF_STRD2_BIT	0

+#define MC_REF_STRD2_MASK	(0xfff << MC_REF_STRD2_BIT)

+

+/* MC Current Frame Stride Register, unit: byte */

+#define MC_CURR_STRD_BIT	0

+#define MC_CURR_STRD_MASK	(0xfff << MC_CURR_STRD_BIT)

+

+/* MC Block Interpolation Information Register */

+#define MC_ITP_INFO_RND1_BIT	24  /* Rounding data during interpolation */

+#define MC_ITP_INFO_RND1_MASK	(0xff << MC_ITP_INFO_RND1_BIT)

+#define MC_ITP_INFO_RND0_BIT	16  /* Rounding data during interpolation */

+#define MC_ITP_INFO_RND0_MASK	(0xff << MC_ITP_INFO_RND0_BIT)

+#define MC_ITP_INFO_AVG		(1 << 12)  /* 0: output interpolated data directly; 1: doing average operation with 2nd source data after interpolating and output */

+#define MC_ITP_INFO_FMT_BIT	8  /* Indicate current interpolation's type */

+#define MC_ITP_INFO_RMT_MASK	(0xf << MC_ITP_INFO_RMT_BIT)

+  #define MC_ITP_INFO_FMT_MPEG_HPEL  (0x0 << MC_ITP_INFO_RMT_BIT) /* MPEG Half-pixel interpolation */

+  #define MC_ITP_INFO_FMT_MPEG_QPEL  (0x1 << MC_ITP_INFO_RMT_BIT) /* MPEG 8-tap Quarter-pixel interpolation */

+  #define MC_ITP_INFO_FMT_H264_QPEL  (0x2 << MC_ITP_INFO_RMT_BIT) /* H264 6-tap Quarter-pixel interpolation */

+  #define MC_ITP_INFO_FMT_H264_EPEL  (0x3 << MC_ITP_INFO_RMT_BIT) /* H264 2-tap Eight-pixel interpolation */

+  #define MC_ITP_INFO_FMT_H264_WPDT  (0x4 << MC_ITP_INFO_RMT_BIT) /* H264 Weighted-prediction */

+  #define MC_ITP_INFO_FMT_WMV2_QPEL  (0x5 << MC_ITP_INFO_RMT_BIT) /* WMV2 4-tap Quarter-pixel interpolation */

+  #define MC_ITP_INFO_FMT_VC1_QPEL   (0x6 << MC_ITP_INFO_RMT_BIT) /* VC1 4-tap Quarter-pixel interpolation */

+  #define MC_ITP_INFO_FMT_RV8_TPEL   (0x7 << MC_ITP_INFO_RMT_BIT) /* RV8 4-tap Third-pixel interpolation */

+  #define MC_ITP_INFO_FMT_RV8_CHROM  (0x8 << MC_ITP_INFO_RMT_BIT) /* RV8 2-tap Third-pixel interpolation */

+  #define MC_ITP_INFO_FMT_RV9_QPEL   (0x9 << MC_ITP_INFO_RMT_BIT) /* RV9 6-tap Quarter-pixel interpolation */

+  #define MC_ITP_INFO_FMT_RV9_CHROM  (0xa << MC_ITP_INFO_RMT_BIT) /* RV9 2-tap Quarter-pixel interpolation */

+#define MC_ITP_INFO_BLK_W_BIT	6  /* Indicate reference block's width, unit: pixel */

+#define MC_ITP_INFO_BLK_W_MASK	(0x3 << MC_ITP_INFO_BLK_W_BIT)

+  #define MC_ITP_INFO_BLK_W_2	(0x0 << MC_ITP_INFO_BLK_W_BIT)

+  #define MC_ITP_INFO_BLK_W_4	(0x1 << MC_ITP_INFO_BLK_W_BIT)

+  #define MC_ITP_INFO_BLK_W_8	(0x2 << MC_ITP_INFO_BLK_W_BIT)

+  #define MC_ITP_INFO_BLK_W_16	(0x3 << MC_ITP_INFO_BLK_W_BIT)

+#define MC_ITP_INFO_BLK_H_BIT	4  /* Indicate reference block's height, unit: pixel */

+#define MC_ITP_INFO_BLK_H_MASK	(0x3 << MC_ITP_INFO_BLK_H_BIT)

+  #define MC_ITP_INFO_BLK_H_2	(0x0 << MC_ITP_INFO_BLK_H_BIT)

+  #define MC_ITP_INFO_BLK_H_4	(0x1 << MC_ITP_INFO_BLK_H_BIT)

+  #define MC_ITP_INFO_BLK_H_8	(0x2 << MC_ITP_INFO_BLK_H_BIT)

+  #define MC_ITP_INFO_BLK_H_16	(0x3 << MC_ITP_INFO_BLK_H_BIT)

+#define MC_ITP_INFO_ITP_CASE_BIT	0  /* Indicate interpolation final destination pixel position */

+#define MC_ITP_INFO_ITP_CASE_MASK	(0xf << MC_ITP_INFO_ITP_CASE_BIT)

+  #define MC_ITP_INFO_ITP_CASE_H0V0	(0x0 << MC_ITP_INFO_ITP_CASE_BIT)

+  #define MC_ITP_INFO_ITP_CASE_H1V0	(0x1 << MC_ITP_INFO_ITP_CASE_BIT)

+  #define MC_ITP_INFO_ITP_CASE_H2V0	(0x2 << MC_ITP_INFO_ITP_CASE_BIT)

+  #define MC_ITP_INFO_ITP_CASE_H3V0	(0x3 << MC_ITP_INFO_ITP_CASE_BIT)

+  #define MC_ITP_INFO_ITP_CASE_H0V1	(0x4 << MC_ITP_INFO_ITP_CASE_BIT)

+  #define MC_ITP_INFO_ITP_CASE_H1V1	(0x5 << MC_ITP_INFO_ITP_CASE_BIT)

+  #define MC_ITP_INFO_ITP_CASE_H2V1	(0x6 << MC_ITP_INFO_ITP_CASE_BIT)

+  #define MC_ITP_INFO_ITP_CASE_H3V1	(0x7 << MC_ITP_INFO_ITP_CASE_BIT)

+  #define MC_ITP_INFO_ITP_CASE_H0V2	(0x8 << MC_ITP_INFO_ITP_CASE_BIT)

+  #define MC_ITP_INFO_ITP_CASE_H1V2	(0x9 << MC_ITP_INFO_ITP_CASE_BIT)

+  #define MC_ITP_INFO_ITP_CASE_H2V2	(0xa << MC_ITP_INFO_ITP_CASE_BIT)

+  #define MC_ITP_INFO_ITP_CASE_H3V2	(0xb << MC_ITP_INFO_ITP_CASE_BIT)

+  #define MC_ITP_INFO_ITP_CASE_H0V3	(0xc << MC_ITP_INFO_ITP_CASE_BIT)

+  #define MC_ITP_INFO_ITP_CASE_H1V3	(0xd << MC_ITP_INFO_ITP_CASE_BIT)

+  #define MC_ITP_INFO_ITP_CASE_H2V3	(0xe << MC_ITP_INFO_ITP_CASE_BIT)

+  #define MC_ITP_INFO_ITP_CASE_H3V3	(0xf << MC_ITP_INFO_ITP_CASE_BIT)

+

+/* MC TAP Filter Coefficient 1 Register */

+#define MC_TAP_COEF1_TAP_COEF4_BIT	24

+#define MC_TAP_COEF1_TAP_COEF4_MASK	(0xff << MC_TAP_COEF1_TAP_COEF4_BIT)

+#define MC_TAP_COEF1_TAP_COEF3_BIT	16

+#define MC_TAP_COEF1_TAP_COEF3_MASK	(0xff << MC_TAP_COEF1_TAP_COEF3_BIT)

+#define MC_TAP_COEF1_TAP_COEF2_BIT	8

+#define MC_TAP_COEF1_TAP_COEF2_MASK	(0xff << MC_TAP_COEF1_TAP_COEF2_BIT)

+#define MC_TAP_COEF1_TAP_COEF1_BIT	0

+#define MC_TAP_COEF1_TAP_COEF1_MASK	(0xff << MC_TAP_COEF1_TAP_COEF1_BIT)

+

+/* MC TAP Filter Coefficient 2 Register */

+#define MC_TAP_COEF2_TAP_COEF8_BIT	24

+#define MC_TAP_COEF2_TAP_COEF8_MASK	(0xff << MC_TAP_COEF2_TAP_COEF8_BIT)

+#define MC_TAP_COEF2_TAP_COEF7_BIT	16

+#define MC_TAP_COEF2_TAP_COEF7_MASK	(0xff << MC_TAP_COEF2_TAP_COEF7_BIT)

+#define MC_TAP_COEF2_TAP_COEF6_BIT	8

+#define MC_TAP_COEF2_TAP_COEF6_MASK	(0xff << MC_TAP_COEF2_TAP_COEF6_BIT)

+#define MC_TAP_COEF2_TAP_COEF5_BIT	0

+#define MC_TAP_COEF2_TAP_COEF5_MASK	(0xff << MC_TAP_COEF2_TAP_COEF5_BIT)

+

+

+

+#ifndef __MIPS_ASSEMBLER

+

+#endif /* __MIPS_ASSEMBLER */

+

+#endif /* __JZ4770MC_H__ */

+

diff --git a/arch/mips/include/asm/mach-jz4770/jz4770mdma.h b/arch/mips/include/asm/mach-jz4770/jz4770mdma.h
new file mode 100644
index 00000000000..ae16f25ccd8
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4770/jz4770mdma.h
@@ -0,0 +1,209 @@
+/*

+ * linux/include/asm-mips/mach-jz4770/jz4770mdma.h

+ *

+ * JZ4770 MDMA register definition.

+ *

+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

+ */

+

+#ifndef __JZ4770MDMA_H__

+#define __JZ4770MDMA_H__

+

+

+#define	MDMAC_BASE	0xB3420000 //0xB3030000 /* Memory Copy DMAC */

+

+/*************************************************************************

+ * MDMAC (MEM Copy DMA Controller)

+ *************************************************************************/

+

+/* m is the DMA controller index (0, 1), n is the DMA channel index (0 - 11) */

+

+#define MDMAC_DSAR(n)		(MDMAC_BASE + (0x00 + (n) * 0x20)) /* DMA source address */

+#define MDMAC_DTAR(n)  		(MDMAC_BASE + (0x04 + (n) * 0x20)) /* DMA target address */

+#define MDMAC_DTCR(n)  		(MDMAC_BASE + (0x08 + (n) * 0x20)) /* DMA transfer count */

+#define MDMAC_DRSR(n)  		(MDMAC_BASE + (0x0c + (n) * 0x20)) /* DMA request source */

+#define MDMAC_DCCSR(n) 		(MDMAC_BASE + (0x10 + (n) * 0x20)) /* DMA control/status */

+#define MDMAC_DCMD(n)  		(MDMAC_BASE + (0x14 + (n) * 0x20)) /* DMA command */

+#define MDMAC_DDA(n)   		(MDMAC_BASE + (0x18 + (n) * 0x20)) /* DMA descriptor address */

+#define MDMAC_DSD(n)   		(MDMAC_BASE + (0xc0 + (n) * 0x04)) /* DMA Stride Address */

+

+#define MDMAC_DMACR		(MDMAC_BASE + 0x0300) /* DMA control register */

+#define MDMAC_DMAIPR		(MDMAC_BASE + 0x0304) /* DMA interrupt pending */

+#define MDMAC_DMADBR		(MDMAC_BASE + 0x0308) /* DMA doorbell */

+#define MDMAC_DMADBSR		(MDMAC_BASE + 0x030C) /* DMA doorbell set */

+#define MDMAC_DMACKE  		(MDMAC_BASE + 0x0310)

+

+#define REG_MDMAC_DSAR(n)	REG32(MDMAC_DSAR((n)))

+#define REG_MDMAC_DTAR(n)	REG32(MDMAC_DTAR((n)))

+#define REG_MDMAC_DTCR(n)	REG32(MDMAC_DTCR((n)))

+#define REG_MDMAC_DRSR(n)	REG32(MDMAC_DRSR((n)))

+#define REG_MDMAC_DCCSR(n)	REG32(MDMAC_DCCSR((n)))

+#define REG_MDMAC_DCMD(n)	REG32(MDMAC_DCMD((n)))

+#define REG_MDMAC_DDA(n)	REG32(MDMAC_DDA((n)))

+#define REG_MDMAC_DSD(n)        REG32(MDMAC_DSD(n))

+#define REG_MDMAC_DMACR		REG32(MDMAC_DMACR)

+#define REG_MDMAC_DMAIPR	REG32(MDMAC_DMAIPR)

+#define REG_MDMAC_DMADBR	REG32(MDMAC_DMADBR)

+#define REG_MDMAC_DMADBSR	REG32(MDMAC_DMADBSR)

+#define REG_MDMAC_DMACKE     	REG32(MDMAC_DMACKE)

+

+#ifndef __MIPS_ASSEMBLER

+

+/***************************************************************************

+ * Mem Copy DMAC

+ ***************************************************************************/

+

+/* n is the DMA channel index (0 - 11) */

+

+#define __mdmac_enable_module \

+	( REG_MDMAC_DMACR |= DMAC_MDMACR_DMAE | DMAC_MDMACR_PR_012345 )

+#define __mdmac_disable_module \

+	( REG_MDMAC_DMACR &= ~DMAC_MDMACR_DMAE )

+

+/* p=0,1,2,3 */

+#define __mdmac_set_priority(p)			\

+do {							\

+	REG_MDMAC_DMACR &= ~DMAC_DMACR_PR_MASK;	\

+	REG_MDMAC_DMACR |= ((p) << DMAC_DMACR_PR_BIT);	\

+} while (0)

+

+#define __mdmac_test_halt_error ( REG_MDMAC_DMACR & DMAC_MDMACR_HLT )

+#define __mdmac_test_addr_error ( REG_MDMAC_DMACR & DMAC_MDMACR_AR )

+

+#define __mdmac_channel_enable_clk \

+	REG_MDMAC_DMACKE |= 1 << (n);

+

+#define __mdmac_enable_descriptor(n) \

+  ( REG_MDMAC_DCCSR((n)) &= ~DMAC_DCCSR_NDES )

+#define __mdmac_disable_descriptor(n) \

+  ( REG_MDMAC_DCCSR((n)) |= DMAC_DCCSR_NDES )

+

+#define __mdmac_enable_channel(n)                 \

+do {                                             \

+	REG_MDMAC_DCCSR((n)) |= DMAC_DCCSR_EN;    \

+} while (0)

+#define __mdmac_disable_channel(n)                \

+do {                                             \

+	REG_MDMAC_DCCSR((n)) &= ~DMAC_DCCSR_EN;   \

+} while (0)

+#define __mdmac_channel_enabled(n) \

+  ( REG_MDMAC_DCCSR((n)) & DMAC_DCCSR_EN )

+

+#define __mdmac_channel_enable_irq(n) \

+  ( REG_MDMAC_DCMD((n)) |= DMAC_DCMD_TIE )

+#define __mdmac_channel_disable_irq(n) \

+  ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_TIE )

+

+#define __mdmac_channel_transmit_halt_detected(n) \

+  (  REG_MDMAC_DCCSR((n)) & DMAC_DCCSR_HLT )

+#define __mdmac_channel_transmit_end_detected(n) \

+  (  REG_MDMAC_DCCSR((n)) & DMAC_DCCSR_TT )

+#define __mdmac_channel_address_error_detected(n) \

+  (  REG_DMAC_DCCSR((n)) & DMAC_DCCSR_AR )

+#define __mdmac_channel_count_terminated_detected(n) \

+  (  REG_MDMAC_DCCSR((n)) & DMAC_DCCSR_CT )

+#define __mdmac_channel_descriptor_invalid_detected(n) \

+  (  REG_MDMAC_DCCSR((n)) & DMAC_DCCSR_INV )

+

+#define __mdmac_channel_clear_transmit_halt(n)				\

+	do {								\

+		/* clear both channel halt error and globle halt error */ \

+		REG_MDMAC_DCCSR(n) &= ~DMAC_DCCSR_HLT;			\

+		REG_MDMAC_DMACR &= ~DMAC_DMACR_HLT;	\

+	} while (0)

+#define __mdmac_channel_clear_transmit_end(n) \

+  (  REG_MDMAC_DCCSR(n) &= ~DMAC_DCCSR_TT )

+#define __mdmac_channel_clear_address_error(n)				\

+	do {								\

+		REG_MDMAC_DDA(n) = 0; /* clear descriptor address register */ \

+		REG_MDMAC_DSAR(n) = 0; /* clear source address register */ \

+		REG_MDMAC_DTAR(n) = 0; /* clear target address register */ \

+		/* clear both channel addr error and globle address error */ \

+		REG_MDMAC_DCCSR(n) &= ~DMAC_DCCSR_AR;			\

+		REG_MDMAC_DMACR &= ~DMAC_DMACR_AR;	\

+	} while (0)

+#define __mdmac_channel_clear_count_terminated(n) \

+  (  REG_MDMAC_DCCSR((n)) &= ~DMAC_DCCSR_CT )

+#define __mdmac_channel_clear_descriptor_invalid(n) \

+  (  REG_MDMAC_DCCSR((n)) &= ~DMAC_DCCSR_INV )

+

+#define __mdmac_channel_set_transfer_unit_32bit(n)	\

+do {							\

+	REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK;	\

+	REG_MDMAC_DCMD((n)) |= DMAC_DCMD_DS_32BIT;	\

+} while (0)

+

+#define __mdmac_channel_set_transfer_unit_16bit(n)	\

+do {							\

+	REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK;	\

+	REG_MDMAC_DCMD((n)) |= DMAC_DCMD_DS_16BIT;	\

+} while (0)

+

+#define __mdmac_channel_set_transfer_unit_8bit(n)	\

+do {							\

+	REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK;	\

+	REG_MDMAC_DCMD((n)) |= DMAC_DCMD_DS_8BIT;	\

+} while (0)

+

+#define __mdmac_channel_set_transfer_unit_16byte(n)	\

+do {							\

+	REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK;	\

+	REG_MDMAC_DCMD((n)) |= DMAC_DCMD_DS_16BYTE;	\

+} while (0)

+

+#define __mdmac_channel_set_transfer_unit_32byte(n)	\

+do {							\

+	REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK;	\

+	REG_MDMAC_DCMD((n)) |= DMAC_DCMD_DS_32BYTE;	\

+} while (0)

+

+/* w=8,16,32 */

+#define __mdmac_channel_set_dest_port_width(n,w)		\

+do {							\

+	REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_DWDH_MASK;	\

+	REG_MDMAC_DCMD((n)) |= DMAC_DCMD_DWDH_##w;	\

+} while (0)

+

+/* w=8,16,32 */

+#define __mdmac_channel_set_src_port_width(n,w)		\

+do {							\

+	REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_SWDH_MASK;	\

+	REG_MDMAC_DCMD((n)) |= DMAC_DCMD_SWDH_##w;	\

+} while (0)

+

+/* v=0-15 */

+#define __mdmac_channel_set_rdil(n,v)				\

+do {								\

+	REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_RDIL_MASK;		\

+	REG_MDMAC_DCMD((n) |= ((v) << DMAC_DCMD_RDIL_BIT);	\

+} while (0)

+

+#define __mdmac_channel_dest_addr_fixed(n) \

+	(REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_DAI)

+#define __mdmac_channel_dest_addr_increment(n) \

+	(REG_MDMAC_DCMD((n)) |= DMAC_DCMD_DAI)

+

+#define __mdmac_channel_src_addr_fixed(n) \

+	(REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_SAI)

+#define __mdmac_channel_src_addr_increment(n) \

+	(REG_MDMAC_DCMD((n)) |= DMAC_DCMD_SAI)

+

+#define __mdmac_channel_set_doorbell(n)	\

+	(REG_MDMAC_DMADBSR = (1 << (n)))

+

+#define __mdmac_channel_irq_detected(n)  (REG_MDMAC_DMAIPR & (1 << (n)))

+#define __mdmac_channel_ack_irq(n)       (REG_MDMAC_DMAIPR &= ~(1 <<(n)))

+

+static __inline__ int __mdmac_get_irq(void)

+{

+	int i;

+	for (i = 0; i < MAX_MDMA_NUM; i++)

+		if (__mdmac_channel_irq_detected(i))

+			return i;

+	return -1;

+}

+

+#endif /* __MIPS_ASSEMBLER */

+

+#endif /* __JZ4770MDMA_H__ */

+

diff --git a/arch/mips/include/asm/mach-jz4770/jz4770me.h b/arch/mips/include/asm/mach-jz4770/jz4770me.h
new file mode 100644
index 00000000000..2b5a327d6f6
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4770/jz4770me.h
@@ -0,0 +1,69 @@
+/*

+ * linux/include/asm-mips/mach-jz4810/jz4810ME.h

+ *

+ * JZ4810 ME register definition.

+ *

+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

+ */

+

+#ifndef __JZ4770ME_H__

+#define __JZ4770ME_H__

+

+

+#define	ME_BASE		0xB3260000

+

+/*************************************************************************

+ * ME (Motion Estimation)

+ *************************************************************************/

+#define ME_CTRL		(ME_BASE + 0x00) /* ME Control Register */

+#define ME_REF_ADDR	(ME_BASE + 0x04) /* ME Reference Block Address Register */

+#define ME_CURR_ADDR	(ME_BASE + 0x08) /* ME Current Block Address Register */

+#define ME_DIFF_ADDR	(ME_BASE + 0x0C) /* ME Difference Address Register */

+#define ME_REF_STRD	(ME_BASE + 0x10) /* ME Reference Frame Stride Register */

+#define ME_CURR_STRD	(ME_BASE + 0x14) /* ME Current Frame Stride Register */

+#define ME_DIFF_STRD	(ME_BASE + 0x18) /* ME Difference Frame Stride Register */

+#define ME_SETTINGS	(ME_BASE + 0x1C) /* ME Settings Register */

+#define ME_MVD		(ME_BASE + 0x20) /* ME Motion Vector Difference Register */

+#define ME_FLAG		(ME_BASE + 0x24) /* ME Flag Register */

+

+#define REG_ME_CTRL		REG32(ME_CTRL)

+#define REG_ME_REF_ADDR		REG32(ME_REF_ADDR)

+#define REG_ME_CURR_ADDR	REG32(ME_CURR_ADDR)

+#define REG_ME_DIFF_ADDR	REG32(ME_DIFF_ADDR)

+#define REG_ME_REF_STRD		REG32(ME_REF_STRD)

+#define REG_ME_CURR_STRD	REG32(ME_CURR_STRD)

+#define REG_ME_DIFF_STRD	REG32(ME_DIFF_STRD)

+#define REG_ME_SETTINGS		REG32(ME_SETTINGS)

+#define REG_ME_MVD		REG32(ME_MVD)

+#define REG_ME_FLAG		REG32(ME_FLAG)

+

+

+/* ME Control Register */

+#define ME_CTRL_FLUSH		(1 << 2) /* ME cache clear */

+#define ME_CTRL_RESET		(1 << 1) /* ME reset */

+#define ME_CTRL_ENABLE		(1 << 0) /* ME enable */

+

+/* ME Settings Register */

+#define ME_SETTINGS_SAD_GATE_BIT	16 /* The max SAD value which can be accepted */

+#define ME_SETTINGS_SAD_GATE_MASK	(0xffff << ME_SETTINGS_SAD_GATE_BIT)

+#define ME_SETTINGS_STEP_NUM_BIT	0  /* The max step number the search process can not exceed */

+#define ME_SETTINGS_STEP_NUM_MASK	(0x3f << ME_SETTINGS_STEP_NUM_BIT)

+

+/* ME Motion Vector Difference Register */

+#define ME_MVD_MVDY_BIT		16 /* The MVD value of coordinate-Y */

+#define ME_MVD_MVDY_MASK	(0xffff << ME_MVD_MVDY_BIT)

+#define ME_MVD_MVDX_BIT		0  /* The MVD value of coordinate-X */

+#define ME_MVD_MVDX_MASK	(0xffff << ME_MVD_MVDX_BIT)

+

+/* ME Flag Register */

+#define ME_FLAG_INTRA		(1 << 1) /* Indicate the current MB will be predicted in intra mode */

+#define ME_FLAG_COMPLETED	(1 << 0) /* The ME of the current part of the MB is completed */

+

+

+

+#ifndef __MIPS_ASSEMBLER

+

+#endif /* __MIPS_ASSEMBLER */

+

+#endif /* __JZ4770ME_H__ */

+

diff --git a/arch/mips/include/asm/mach-jz4770/jz4770misc.h b/arch/mips/include/asm/mach-jz4770/jz4770misc.h
new file mode 100644
index 00000000000..e744ea0fd7c
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4770/jz4770misc.h
@@ -0,0 +1,91 @@
+/*

+ * linux/include/asm-mips/mach-jz4760/jz4760misc.h

+ *

+ * JZ4760 misc definition.

+ *

+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

+ */

+

+#ifndef __JZ4760MISC_H__

+#define __JZ4760MISC_H__

+

+

+#if defined(__ASSEMBLY__) || defined(__LANGUAGE_ASSEMBLY)

+        #ifndef __MIPS_ASSEMBLER

+                #define __MIPS_ASSEMBLER

+        #endif

+        #define REG8(addr)	(addr)

+        #define REG16(addr)	(addr)

+        #define REG32(addr)	(addr)

+#else

+        #define REG8(addr)	*((volatile unsigned char *)(addr))

+        #define REG16(addr)	*((volatile unsigned short *)(addr))

+        #define REG32(addr)	*((volatile unsigned int *)(addr))

+

+        #define INREG8(x)               ((unsigned char)(*(volatile unsigned char *)(x)))

+        #define OUTREG8(x, y)           *(volatile unsigned char *)(x) = (y)

+        #define SETREG8(x, y)           OUTREG8(x, INREG8(x)|(y))

+        #define CLRREG8(x, y)           OUTREG8(x, INREG8(x)&~(y))

+        #define CMSREG8(x, y, m)        OUTREG8(x, (INREG8(x)&~(m))|(y))

+

+        #define INREG16(x)              ((unsigned short)(*(volatile unsigned short *)(x)))

+        #define OUTREG16(x, y)          *(volatile unsigned short *)(x) = (y)

+        #define SETREG16(x, y)          OUTREG16(x, INREG16(x)|(y))

+        #define CLRREG16(x, y)          OUTREG16(x, INREG16(x)&~(y))

+        #define CMSREG16(x, y, m)       OUTREG16(x, (INREG16(x)&~(m))|(y))

+

+        #define INREG32(x)              ((unsigned int)(*(volatile unsigned int *)(x)))

+        #define OUTREG32(x, y)          *(volatile unsigned int *)(x) = (y)

+        #define SETREG32(x, y)          OUTREG32(x, INREG32(x)|(y))

+        #define CLRREG32(x, y)          OUTREG32(x, INREG32(x)&~(y))

+        #define CMSREG32(x, y, m)       OUTREG32(x, (INREG32(x)&~(m))|(y))

+

+#endif

+

+

+/*

+ * Define the bit field macro to avoid the bit mistake

+ */

+#define BIT0            (1 << 0)

+#define BIT1            (1 << 1)

+#define BIT2            (1 << 2)

+#define BIT3            (1 << 3)

+#define BIT4            (1 << 4)

+#define BIT5            (1 << 5)

+#define BIT6            (1 << 6)

+#define BIT7            (1 << 7)

+#define BIT8            (1 << 8)

+#define BIT9            (1 << 9)

+#define BIT10           (1 << 10)

+#define BIT11           (1 << 11)

+#define BIT12 	        (1 << 12)

+#define BIT13 	        (1 << 13)

+#define BIT14 	        (1 << 14)

+#define BIT15 	        (1 << 15)

+#define BIT16 	        (1 << 16)

+#define BIT17 	        (1 << 17)

+#define BIT18 	        (1 << 18)

+#define BIT19 	        (1 << 19)

+#define BIT20 	        (1 << 20)

+#define BIT21 	        (1 << 21)

+#define BIT22 	        (1 << 22)

+#define BIT23 	        (1 << 23)

+#define BIT24 	        (1 << 24)

+#define BIT25 	        (1 << 25)

+#define BIT26 	        (1 << 26)

+#define BIT27 	        (1 << 27)

+#define BIT28 	        (1 << 28)

+#define BIT29 	        (1 << 29)

+#define BIT30 	        (1 << 30)

+#define BIT31 	        (1 << 31)

+

+

+/* Generate the bit field mask from msb to lsb */

+#define BITS_H2L(msb, lsb)  ((0xFFFFFFFF >> (32-((msb)-(lsb)+1))) << (lsb))

+

+

+/* Get the bit field value from the data which is read from the register */

+#define get_bf_value(data, lsb, mask)  (((data) & (mask)) >> (lsb))

+

+

+#endif /* __JZ4760MISC_H__ */

diff --git a/arch/mips/include/asm/mach-jz4770/jz4770msc.h b/arch/mips/include/asm/mach-jz4770/jz4770msc.h
new file mode 100644
index 00000000000..23f07f75407
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4770/jz4770msc.h
@@ -0,0 +1,325 @@
+/*

+ * linux/include/asm-mips/mach-jz4810/jz4810msc.h

+ *

+ * JZ4810 MSC register definition.

+ *

+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

+ */

+

+#ifndef __JZ4770MSC_H__

+#define __JZ4770MSC_H__

+

+

+#define	MSC0_BASE	0xB0021000

+#define	MSC1_BASE	0xB0022000

+#define	MSC2_BASE	0xB0023000

+

+

+/*************************************************************************

+ * MSC

+ ************************************************************************/

+/* n = 0, 1 (MSC0, MSC1) */

+#define	MSC_STRPCL(n)		(MSC0_BASE + (n)*0x1000 + 0x000)

+#define	MSC_STAT(n)		(MSC0_BASE + (n)*0x1000 + 0x004)

+#define	MSC_CLKRT(n)		(MSC0_BASE + (n)*0x1000 + 0x008)

+#define	MSC_CMDAT(n)		(MSC0_BASE + (n)*0x1000 + 0x00C)

+#define	MSC_RESTO(n)		(MSC0_BASE + (n)*0x1000 + 0x010)

+#define	MSC_RDTO(n)		(MSC0_BASE + (n)*0x1000 + 0x014)

+#define	MSC_BLKLEN(n)		(MSC0_BASE + (n)*0x1000 + 0x018)

+#define	MSC_NOB(n)		(MSC0_BASE + (n)*0x1000 + 0x01C)

+#define	MSC_SNOB(n)		(MSC0_BASE + (n)*0x1000 + 0x020)

+#define	MSC_IMASK(n)		(MSC0_BASE + (n)*0x1000 + 0x024)

+#define	MSC_IREG(n)		(MSC0_BASE + (n)*0x1000 + 0x028)

+#define	MSC_CMD(n)		(MSC0_BASE + (n)*0x1000 + 0x02C)

+#define	MSC_ARG(n)		(MSC0_BASE + (n)*0x1000 + 0x030)

+#define	MSC_RES(n)		(MSC0_BASE + (n)*0x1000 + 0x034)

+#define	MSC_RXFIFO(n)		(MSC0_BASE + (n)*0x1000 + 0x038)

+#define	MSC_TXFIFO(n)		(MSC0_BASE + (n)*0x1000 + 0x03C)

+#define	MSC_LPM(n)		(MSC0_BASE + (n)*0x1000 + 0x040)

+

+#define	REG_MSC_STRPCL(n)	REG16(MSC_STRPCL(n))

+#define	REG_MSC_STAT(n)		REG32(MSC_STAT(n))

+#define	REG_MSC_CLKRT(n)	REG16(MSC_CLKRT(n))

+#define	REG_MSC_CMDAT(n)	REG32(MSC_CMDAT(n))

+#define	REG_MSC_RESTO(n)	REG16(MSC_RESTO(n))

+#define	REG_MSC_RDTO(n)		REG16(MSC_RDTO(n))

+#define	REG_MSC_BLKLEN(n)	REG16(MSC_BLKLEN(n))

+#define	REG_MSC_NOB(n)		REG16(MSC_NOB(n))

+#define	REG_MSC_SNOB(n)		REG16(MSC_SNOB(n))

+#define	REG_MSC_IMASK(n)	REG32(MSC_IMASK(n))

+#define	REG_MSC_IREG(n)		REG16(MSC_IREG(n))

+#define	REG_MSC_CMD(n)		REG8(MSC_CMD(n))

+#define	REG_MSC_ARG(n)		REG32(MSC_ARG(n))

+#define	REG_MSC_RES(n)		REG16(MSC_RES(n))

+#define	REG_MSC_RXFIFO(n)	REG32(MSC_RXFIFO(n))

+#define	REG_MSC_TXFIFO(n)	REG32(MSC_TXFIFO(n))

+#define	REG_MSC_LPM(n)		REG32(MSC_LPM(n))

+

+/* MSC Clock and Control Register (MSC_STRPCL) */

+#define MSC_STRPCL_SEND_CCSD		(1 << 15) /*send command completion signal disable to ceata */

+#define MSC_STRPCL_SEND_AS_CCSD		(1 << 14) /*send internally generated stop after sending ccsd */

+#define MSC_STRPCL_EXIT_MULTIPLE	(1 << 7)

+#define MSC_STRPCL_EXIT_TRANSFER	(1 << 6)

+#define MSC_STRPCL_START_READWAIT	(1 << 5)

+#define MSC_STRPCL_STOP_READWAIT	(1 << 4)

+#define MSC_STRPCL_RESET		(1 << 3)

+#define MSC_STRPCL_START_OP		(1 << 2)

+#define MSC_STRPCL_CLOCK_CONTROL_BIT	0

+#define MSC_STRPCL_CLOCK_CONTROL_MASK	(0x3 << MSC_STRPCL_CLOCK_CONTROL_BIT)

+  #define MSC_STRPCL_CLOCK_CONTROL_STOP	  (0x1 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Stop MMC/SD clock */

+  #define MSC_STRPCL_CLOCK_CONTROL_START  (0x2 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Start MMC/SD clock */

+

+/* MSC Status Register (MSC_STAT) */

+#define MSC_STAT_AUTO_CMD_DONE		(1 << 31) /*12 is internally generated by controller has finished */

+#define MSC_STAT_IS_RESETTING		(1 << 15)

+#define MSC_STAT_SDIO_INT_ACTIVE	(1 << 14)

+#define MSC_STAT_PRG_DONE		(1 << 13)

+#define MSC_STAT_DATA_TRAN_DONE		(1 << 12)

+#define MSC_STAT_END_CMD_RES		(1 << 11)

+#define MSC_STAT_DATA_FIFO_AFULL	(1 << 10)

+#define MSC_STAT_IS_READWAIT		(1 << 9)

+#define MSC_STAT_CLK_EN			(1 << 8)

+#define MSC_STAT_DATA_FIFO_FULL		(1 << 7)

+#define MSC_STAT_DATA_FIFO_EMPTY	(1 << 6)

+#define MSC_STAT_CRC_RES_ERR		(1 << 5)

+#define MSC_STAT_CRC_READ_ERROR		(1 << 4)

+#define MSC_STAT_CRC_WRITE_ERROR_BIT	2

+#define MSC_STAT_CRC_WRITE_ERROR_MASK	(0x3 << MSC_STAT_CRC_WRITE_ERROR_BIT)

+  #define MSC_STAT_CRC_WRITE_ERROR_NO		(0 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No error on transmission of data */

+  #define MSC_STAT_CRC_WRITE_ERROR		(1 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* Card observed erroneous transmission of data */

+  #define MSC_STAT_CRC_WRITE_ERROR_NOSTS	(2 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No CRC status is sent back */

+#define MSC_STAT_TIME_OUT_RES		(1 << 1)

+#define MSC_STAT_TIME_OUT_READ		(1 << 0)

+

+/* MSC Bus Clock Control Register (MSC_CLKRT) */

+#define	MSC_CLKRT_CLK_RATE_BIT		0

+#define	MSC_CLKRT_CLK_RATE_MASK		(0x7 << MSC_CLKRT_CLK_RATE_BIT)

+  #define MSC_CLKRT_CLK_RATE_DIV_1	(0x0 << MSC_CLKRT_CLK_RATE_BIT) /* CLK_SRC */

+  #define MSC_CLKRT_CLK_RATE_DIV_2	(0x1 << MSC_CLKRT_CLK_RATE_BIT) /* 1/2 of CLK_SRC */

+  #define MSC_CLKRT_CLK_RATE_DIV_4	(0x2 << MSC_CLKRT_CLK_RATE_BIT) /* 1/4 of CLK_SRC */

+  #define MSC_CLKRT_CLK_RATE_DIV_8	(0x3 << MSC_CLKRT_CLK_RATE_BIT) /* 1/8 of CLK_SRC */

+  #define MSC_CLKRT_CLK_RATE_DIV_16	(0x4 << MSC_CLKRT_CLK_RATE_BIT) /* 1/16 of CLK_SRC */

+  #define MSC_CLKRT_CLK_RATE_DIV_32	(0x5 << MSC_CLKRT_CLK_RATE_BIT) /* 1/32 of CLK_SRC */

+  #define MSC_CLKRT_CLK_RATE_DIV_64	(0x6 << MSC_CLKRT_CLK_RATE_BIT) /* 1/64 of CLK_SRC */

+  #define MSC_CLKRT_CLK_RATE_DIV_128	(0x7 << MSC_CLKRT_CLK_RATE_BIT) /* 1/128 of CLK_SRC */

+

+/* MSC Command Sequence Control Register (MSC_CMDAT) */

+#define	MSC_CMDAT_CCS_EXPECTED		(1 << 31) /* interrupts are enabled in ce-ata */

+#define	MSC_CMDAT_READ_CEATA		(1 << 30)

+#define	MSC_CMDAT_SDIO_PRDT		(1 << 17) /* exact 2 cycle */

+#define	MSC_CMDAT_SEND_AS_STOP		(1 << 16)

+#define	MSC_CMDAT_RTRG_BIT		14

+  #define MSC_CMDAT_RTRG_EQUALT_8	(0x0 << MSC_CMDAT_RTRG_BIT)

+  #define MSC_CMDAT_RTRG_EQUALT_16	(0x1 << MSC_CMDAT_RTRG_BIT) /* reset value */

+  #define MSC_CMDAT_RTRG_EQUALT_24	(0x2 << MSC_CMDAT_RTRG_BIT)

+

+#define	MSC_CMDAT_TTRG_BIT		12

+  #define MSC_CMDAT_TTRG_LESS_8		(0x0 << MSC_CMDAT_TTRG_BIT)

+  #define MSC_CMDAT_TTRG_LESS_16	(0x1 << MSC_CMDAT_TTRG_BIT) /*reset value  */

+  #define MSC_CMDAT_TTRG_LESS_24	(0x2 << MSC_CMDAT_TTRG_BIT)

+#define	MSC_CMDAT_STOP_ABORT		(1 << 11)

+#define	MSC_CMDAT_BUS_WIDTH_BIT		9

+#define	MSC_CMDAT_BUS_WIDTH_MASK	(0x3 << MSC_CMDAT_BUS_WIDTH_BIT)

+  #define MSC_CMDAT_BUS_WIDTH_1BIT	(0x0 << MSC_CMDAT_BUS_WIDTH_BIT) /* 1-bit data bus */

+  #define MSC_CMDAT_BUS_WIDTH_4BIT	(0x2 << MSC_CMDAT_BUS_WIDTH_BIT) /* 4-bit data bus */

+  #define MSC_CMDAT_BUS_WIDTH_8BIT	(0x3 << MSC_CMDAT_BUS_WIDTH_BIT) /* 8-bit data bus */

+#define	MSC_CMDAT_DMA_EN		(1 << 8)

+#define	MSC_CMDAT_INIT			(1 << 7)

+#define	MSC_CMDAT_BUSY			(1 << 6)

+#define	MSC_CMDAT_STREAM_BLOCK		(1 << 5)

+#define	MSC_CMDAT_WRITE			(1 << 4)

+#define	MSC_CMDAT_READ			(0 << 4)

+#define	MSC_CMDAT_DATA_EN		(1 << 3)

+#define	MSC_CMDAT_RESPONSE_BIT	0

+#define	MSC_CMDAT_RESPONSE_MASK	(0x7 << MSC_CMDAT_RESPONSE_BIT)

+  #define MSC_CMDAT_RESPONSE_NONE (0x0 << MSC_CMDAT_RESPONSE_BIT) /* No response */

+  #define MSC_CMDAT_RESPONSE_R1	  (0x1 << MSC_CMDAT_RESPONSE_BIT) /* Format R1 and R1b */

+  #define MSC_CMDAT_RESPONSE_R2	  (0x2 << MSC_CMDAT_RESPONSE_BIT) /* Format R2 */

+  #define MSC_CMDAT_RESPONSE_R3	  (0x3 << MSC_CMDAT_RESPONSE_BIT) /* Format R3 */

+  #define MSC_CMDAT_RESPONSE_R4	  (0x4 << MSC_CMDAT_RESPONSE_BIT) /* Format R4 */

+  #define MSC_CMDAT_RESPONSE_R5	  (0x5 << MSC_CMDAT_RESPONSE_BIT) /* Format R5 */

+  #define MSC_CMDAT_RESPONSE_R6	  (0x6 << MSC_CMDAT_RESPONSE_BIT) /* Format R6 */

+

+#define	CMDAT_DMA_EN	(1 << 8)

+#define	CMDAT_INIT	(1 << 7)

+#define	CMDAT_BUSY	(1 << 6)

+#define	CMDAT_STREAM	(1 << 5)

+#define	CMDAT_WRITE	(1 << 4)

+#define	CMDAT_DATA_EN	(1 << 3)

+

+/* MSC Interrupts Mask Register (MSC_IMASK) */

+#define	MSC_IMASK_AUTO_CMD_DONE		(1 << 8)

+#define	MSC_IMASK_SDIO			(1 << 7)

+#define	MSC_IMASK_TXFIFO_WR_REQ		(1 << 6)

+#define	MSC_IMASK_RXFIFO_RD_REQ		(1 << 5)

+#define	MSC_IMASK_END_CMD_RES		(1 << 2)

+#define	MSC_IMASK_PRG_DONE		(1 << 1)

+#define	MSC_IMASK_DATA_TRAN_DONE	(1 << 0)

+

+/* MSC Interrupts Status Register (MSC_IREG) */

+#define	MSC_IREG_AUTO_CMD_DONE		(1 << 8)

+#define	MSC_IREG_SDIO			(1 << 7)

+#define	MSC_IREG_TXFIFO_WR_REQ		(1 << 6)

+#define	MSC_IREG_RXFIFO_RD_REQ		(1 << 5)

+#define	MSC_IREG_END_CMD_RES		(1 << 2)

+#define	MSC_IREG_PRG_DONE		(1 << 1)

+#define	MSC_IREG_DATA_TRAN_DONE		(1 << 0)

+

+/* MSC Low Power Mode Register (MSC_LPM) */

+#define	MSC_SET_LPM			(1 << 0)

+

+

+#ifndef __MIPS_ASSEMBLER

+

+/***************************************************************************

+ * MSC

+ ***************************************************************************/

+/* n = 0, 1 (MSC0, MSC1) */

+

+#define __msc_start_op(n) \

+	( REG_MSC_STRPCL(n) = MSC_STRPCL_START_OP | MSC_STRPCL_CLOCK_CONTROL_START )

+

+#define __msc_set_resto(n, to)  	( REG_MSC_RESTO(n) = to )

+#define __msc_set_rdto(n, to)   	( REG_MSC_RDTO(n) = to )

+#define __msc_set_cmd(n, cmd)   	( REG_MSC_CMD(n) = cmd )

+#define __msc_set_arg(n, arg)   	( REG_MSC_ARG(n) = arg )

+#define __msc_set_nob(n, nob)      	( REG_MSC_NOB(n) = nob )

+#define __msc_get_nob(n)        	( REG_MSC_NOB(n) )

+#define __msc_set_blklen(n, len)        ( REG_MSC_BLKLEN(n) = len )

+#define __msc_set_cmdat(n, cmdat)   	( REG_MSC_CMDAT(n) = cmdat )

+#define __msc_set_cmdat_ioabort(n) 	( REG_MSC_CMDAT(n) |= MSC_CMDAT_IO_ABORT )

+#define __msc_clear_cmdat_ioabort(n) 	( REG_MSC_CMDAT(n) &= ~MSC_CMDAT_IO_ABORT )

+

+#define __msc_set_cmdat_bus_width1(n) 			\

+do { 							\

+	REG_MSC_CMDAT(n) &= ~MSC_CMDAT_BUS_WIDTH_MASK; 	\

+	REG_MSC_CMDAT(n) |= MSC_CMDAT_BUS_WIDTH_1BIT; 	\

+} while(0)

+

+#define __msc_set_cmdat_bus_width4(n) 			\

+do { 							\

+	REG_MSC_CMDAT(n) &= ~MSC_CMDAT_BUS_WIDTH_MASK; 	\

+	REG_MSC_CMDAT(n) |= MSC_CMDAT_BUS_WIDTH_4BIT; 	\

+} while(0)

+

+#define __msc_set_cmdat_dma_en(n)       ( REG_MSC_CMDAT(n) |= MSC_CMDAT_DMA_EN )

+#define __msc_set_cmdat_init(n) 	( REG_MSC_CMDAT(n) |= MSC_CMDAT_INIT )

+#define __msc_set_cmdat_busy(n) 	( REG_MSC_CMDAT(n) |= MSC_CMDAT_BUSY )

+#define __msc_set_cmdat_stream(n)       ( REG_MSC_CMDAT(n) |= MSC_CMDAT_STREAM_BLOCK )

+#define __msc_set_cmdat_block(n)        ( REG_MSC_CMDAT(n) &= ~MSC_CMDAT_STREAM_BLOCK )

+#define __msc_set_cmdat_read(n) 	( REG_MSC_CMDAT(n) &= ~MSC_CMDAT_WRITE_READ )

+#define __msc_set_cmdat_write(n)        ( REG_MSC_CMDAT(n) |= MSC_CMDAT_WRITE_READ )

+#define __msc_set_cmdat_data_en(n)      ( REG_MSC_CMDAT(n) |= MSC_CMDAT_DATA_EN )

+

+/* r is MSC_CMDAT_RESPONSE_FORMAT_Rx or MSC_CMDAT_RESPONSE_FORMAT_NONE */

+#define __msc_set_cmdat_res_format(n, r)				\

+do { 								\

+	REG_MSC_CMDAT(n) &= ~MSC_CMDAT_RESPONSE_FORMAT_MASK; 	\

+	REG_MSC_CMDAT(n) |= (r); 					\

+} while(0)

+

+#define __msc_clear_cmdat(n) \

+  REG_MSC_CMDAT(n) &= ~( MSC_CMDAT_IO_ABORT | MSC_CMDAT_DMA_EN | MSC_CMDAT_INIT| \

+  MSC_CMDAT_BUSY | MSC_CMDAT_STREAM_BLOCK | MSC_CMDAT_WRITE_READ | \

+  MSC_CMDAT_DATA_EN | MSC_CMDAT_RESPONSE_FORMAT_MASK )

+

+#define __msc_get_imask(n) 		( REG_MSC_IMASK(n) )

+#define __msc_mask_all_intrs(n) 	( REG_MSC_IMASK(n) = 0xff )

+#define __msc_unmask_all_intrs(n) 	( REG_MSC_IMASK(n) = 0x00 )

+#define __msc_mask_rd(n) 		( REG_MSC_IMASK(n) |= MSC_IMASK_RXFIFO_RD_REQ )

+#define __msc_unmask_rd(n) 		( REG_MSC_IMASK(n) &= ~MSC_IMASK_RXFIFO_RD_REQ )

+#define __msc_mask_wr(n) 		( REG_MSC_IMASK(n) |= MSC_IMASK_TXFIFO_WR_REQ )

+#define __msc_unmask_wr(n) 		( REG_MSC_IMASK(n) &= ~MSC_IMASK_TXFIFO_WR_REQ )

+#define __msc_mask_endcmdres(n) 	( REG_MSC_IMASK(n) |= MSC_IMASK_END_CMD_RES )

+#define __msc_unmask_endcmdres(n) 	( REG_MSC_IMASK(n) &= ~MSC_IMASK_END_CMD_RES )

+#define __msc_mask_datatrandone(n) 	( REG_MSC_IMASK(n) |= MSC_IMASK_DATA_TRAN_DONE )

+#define __msc_unmask_datatrandone(n) 	( REG_MSC_IMASK(n) &= ~MSC_IMASK_DATA_TRAN_DONE )

+#define __msc_mask_prgdone(n) 		( REG_MSC_IMASK(n) |= MSC_IMASK_PRG_DONE )

+#define __msc_unmask_prgdone(n) 	( REG_MSC_IMASK(n) &= ~MSC_IMASK_PRG_DONE )

+

+/* m=0,1,2,3,4,5,6,7 */

+#define __msc_set_clkrt(n, m) 	\

+do { 				\

+	REG_MSC_CLKRT(n) = m;	\

+} while(0)

+

+#define __msc_get_ireg(n) 	        	( REG_MSC_IREG(n) )

+#define __msc_ireg_rd(n) 	        	( REG_MSC_IREG(n) & MSC_IREG_RXFIFO_RD_REQ )

+#define __msc_ireg_wr(n) 	        	( REG_MSC_IREG(n) & MSC_IREG_TXFIFO_WR_REQ )

+#define __msc_ireg_end_cmd_res(n)       	( REG_MSC_IREG(n) & MSC_IREG_END_CMD_RES )

+#define __msc_ireg_data_tran_done(n)     	( REG_MSC_IREG(n) & MSC_IREG_DATA_TRAN_DONE )

+#define __msc_ireg_prg_done(n) 	        	( REG_MSC_IREG(n) & MSC_IREG_PRG_DONE )

+#define __msc_ireg_clear_end_cmd_res(n)         ( REG_MSC_IREG(n) = MSC_IREG_END_CMD_RES )

+#define __msc_ireg_clear_data_tran_done(n)      ( REG_MSC_IREG(n) = MSC_IREG_DATA_TRAN_DONE )

+#define __msc_ireg_clear_prg_done(n)     	( REG_MSC_IREG(n) = MSC_IREG_PRG_DONE )

+

+#define __msc_get_stat(n) 		( REG_MSC_STAT(n) )

+#define __msc_stat_not_end_cmd_res(n) 	( (REG_MSC_STAT(n) & MSC_STAT_END_CMD_RES) == 0)

+#define __msc_stat_crc_err(n) \

+  ( REG_MSC_STAT(n) & (MSC_STAT_CRC_RES_ERR | MSC_STAT_CRC_READ_ERROR | MSC_STAT_CRC_WRITE_ERROR_YES) )

+#define __msc_stat_res_crc_err(n) 	( REG_MSC_STAT(n) & MSC_STAT_CRC_RES_ERR )

+#define __msc_stat_rd_crc_err(n) 	( REG_MSC_STAT(n) & MSC_STAT_CRC_READ_ERROR )

+#define __msc_stat_wr_crc_err(n) 	( REG_MSC_STAT(n) & MSC_STAT_CRC_WRITE_ERROR_YES )

+#define __msc_stat_resto_err(n) 	( REG_MSC_STAT(n) & MSC_STAT_TIME_OUT_RES )

+#define __msc_stat_rdto_err(n) 		( REG_MSC_STAT(n) & MSC_STAT_TIME_OUT_READ )

+

+#define __msc_rd_resfifo(n) 		( REG_MSC_RES(n) )

+#define __msc_rd_rxfifo(n)  		( REG_MSC_RXFIFO(n) )

+#define __msc_wr_txfifo(n, v)  		( REG_MSC_TXFIFO(n) = v )

+

+#define __msc_reset(n) 						\

+do { 								\

+	REG_MSC_STRPCL(n) = MSC_STRPCL_RESET;			\

+ 	while (REG_MSC_STAT(n) & MSC_STAT_IS_RESETTING);		\

+} while (0)

+

+#define __msc_start_clk(n) 					\

+do { 								\

+	REG_MSC_STRPCL(n) = MSC_STRPCL_CLOCK_CONTROL_START;	\

+} while (0)

+

+#define __msc_stop_clk(n) 					\

+do { 								\

+	REG_MSC_STRPCL(n) = MSC_STRPCL_CLOCK_CONTROL_STOP;	\

+} while (0)

+

+#define MMC_CLK 19169200

+#define SD_CLK  24576000

+

+/* msc_clk should little than pclk and little than clk retrieve from card */

+#define __msc_calc_clk_divisor(type,dev_clk,msc_clk,lv)		\

+do {								\

+	unsigned int rate, pclk, i;				\

+	pclk = dev_clk;						\

+	rate = type?SD_CLK:MMC_CLK;				\

+  	if (msc_clk && msc_clk < pclk)				\

+    		pclk = msc_clk;					\

+	i = 0;							\

+  	while (pclk < rate)					\

+    	{							\

+      		i ++;						\

+      		rate >>= 1;					\

+    	}							\

+  	lv = i;							\

+} while(0)

+

+/* divide rate to little than or equal to 400kHz */

+#define __msc_calc_slow_clk_divisor(type, lv)			\

+do {								\

+	unsigned int rate, i;					\

+	rate = (type?SD_CLK:MMC_CLK)/1000/400;			\

+	i = 0;							\

+	while (rate > 0)					\

+    	{							\

+      		rate >>= 1;					\

+      		i ++;						\

+    	}							\

+  	lv = i;							\

+} while(0)

+

+

+

+#endif /* __MIPS_ASSEMBLER */

+

+#endif /* __JZ4770MSC_H__ */

+

diff --git a/arch/mips/include/asm/mach-jz4770/jz4770nemc.h b/arch/mips/include/asm/mach-jz4770/jz4770nemc.h
new file mode 100644
index 00000000000..6f764b6bc38
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4770/jz4770nemc.h
@@ -0,0 +1,86 @@
+/*

+ * linux/include/asm-mips/mach-jz4810/jz4810nemc.h

+ *

+ * JZ4810 NEMC register definition.

+ *

+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

+ */

+

+#ifndef __JZ4770NEMC_H__

+#define __JZ4770NEMC_H__

+

+

+#define NEMC_BASE	0xB3410000

+

+/*************************************************************************

+ * NEMC (External Memory Controller for NAND)

+ *************************************************************************/

+

+#define NEMC_NFCSR	(NEMC_BASE + 0x050) /* NAND Flash Control/Status Register */

+#define NEMC_SMCR1	(NEMC_BASE + 0x14)  /* Static Memory Control Register 1 */

+#define NEMC_SMCR2	(NEMC_BASE + 0x18)

+#define NEMC_SMCR3	(NEMC_BASE + 0x1c)

+#define NEMC_SMCR4	(NEMC_BASE + 0x20)

+#define NEMC_SMCR5	(NEMC_BASE + 0x24)

+#define NEMC_SMCR6	(NEMC_BASE + 0x28)

+#define NEMC_SACR1	(NEMC_BASE + 0x34)

+#define NEMC_SACR2	(NEMC_BASE + 0x38)

+#define NEMC_SACR3	(NEMC_BASE + 0x3c)

+#define NEMC_SACR4	(NEMC_BASE + 0x40)

+#define NEMC_SACR5	(NEMC_BASE + 0x44)

+#define NEMC_SACR6	(NEMC_BASE + 0x48)

+

+#define REG_NEMC_NFCSR	REG32(NEMC_NFCSR)

+#define REG_NEMC_SMCR1	REG32(NEMC_SMCR1)

+#define REG_NEMC_SMCR2	REG32(NEMC_SMCR2)

+#define REG_NEMC_SMCR3	REG32(NEMC_SMCR3)

+#define REG_NEMC_SMCR4	REG32(NEMC_SMCR4)

+#define REG_NEMC_SMCR5	REG32(NEMC_SMCR5)

+#define REG_NEMC_SMCR6	REG32(NEMC_SMCR6)

+#define REG_NEMC_SACR1	REG32(NEMC_SACR1)

+#define REG_NEMC_SACR2	REG32(NEMC_SACR2)

+#define REG_NEMC_SACR3	REG32(NEMC_SACR3)

+#define REG_NEMC_SACR4	REG32(NEMC_SACR4)

+#define REG_NEMC_SACR5	REG32(NEMC_SACR5)

+#define REG_NEMC_SACR6	REG32(NEMC_SACR6)

+

+#define NEMC_CS1	       0xBA000000	/* read-write area in static bank 1 */

+#define NEMC_CS2	       0xB8000000	/* read-write area in static bank 2 */

+#define NEMC_CS3	       0xB7000000	/* read-write area in static bank 3 */

+#define NEMC_CS4	       0xB6000000	/* read-write area in static bank 4 */

+#define NEMC_CS5	       0xB5000000	/* read-write area in static bank 5 */

+#define NEMC_CS6	       0xB4000000	/* read-write area in static bank 6 */

+

+// PN(bit 0):0-disable, 1-enable

+// PN(bit 1):0-no reset, 1-reset

+// (bit 2):Reserved

+// BITCNT(bit 3):0-disable, 1-enable

+// BITCNT(bit 4):0-calculate, 1's number, 1-calculate 0's number

+// BITCNT(bit 5):0-no reset, 1-reset bitcnt

+#define NEMC_PNCR 	(NEMC_BASE+0x100)

+#define NEMC_PNDR 	(NEMC_BASE+0x104)

+#define NEMC_BITCNT	(NEMC_BASE+0x108)

+

+#define REG_NEMC_PNCR REG32(NEMC_PNCR)

+#define REG_NEMC_PNDR REG32(NEMC_PNDR)

+#define REG_NEMC_BITCNT REG32(NEMC_BITCNT)

+

+//#define REG_NEMC_SMCR	REG32(NEMC_SMCR)

+

+/* NAND Flash Control/Status Register */

+#define NEMC_NFCSR_NFCE4	(1 << 7) /* NAND Flash Enable */

+#define NEMC_NFCSR_NFE4		(1 << 6) /* NAND Flash FCE# Assertion Enable */

+#define NEMC_NFCSR_NFCE3	(1 << 5)

+#define NEMC_NFCSR_NFE3		(1 << 4)

+#define NEMC_NFCSR_NFCE2	(1 << 3)

+#define NEMC_NFCSR_NFE2		(1 << 2)

+#define NEMC_NFCSR_NFCE1	(1 << 1)

+#define NEMC_NFCSR_NFE1		(1 << 0)

+

+

+#ifndef __MIPS_ASSEMBLER

+

+#endif /* __MIPS_ASSEMBLER */

+

+#endif /* __JZ4770NEMC_H__ */

+

diff --git a/arch/mips/include/asm/mach-jz4770/jz4770ost.h b/arch/mips/include/asm/mach-jz4770/jz4770ost.h
new file mode 100644
index 00000000000..37b9c9f564a
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4770/jz4770ost.h
@@ -0,0 +1,73 @@
+/*

+ * jz4760ost.h

+ * JZ4760 OST register definition

+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

+ *

+ * Author: whxu@ingenic.cn

+ */

+

+#ifndef __JZ4770OST_H__

+#define __JZ4770OST_H__

+

+//#define CONFIG_SOC_JZ4770 1

+/*

+ * Operating system timer module(OST) address definition

+ */

+

+/*

+ * OST registers offset address definition

+ */

+#define OST_OSTDR_OFFSET	(0xe0)  /* rw, 32, 0x???????? */

+#define OST_OSTCNTL_OFFSET	(0xe4)

+#define OST_OSTCNTH_OFFSET	(0xe8)

+#define OST_OSTCSR_OFFSET	(0xec)  /* rw, 16, 0x0000 */

+

+#define OST_OSTCNTH_BUF_OFFSET	(0xfc)

+

+

+/*

+ * OST registers address definition

+ */

+#define OST_OSTDR	(OST_BASE + OST_OSTDR_OFFSET)

+#define OST_OSTCNTL	(OST_BASE + OST_OSTCNTL_OFFSET)

+#define OST_OSTCNTH	(OST_BASE + OST_OSTCNTH_OFFSET)

+#define OST_OSTCSR	(OST_BASE + OST_OSTCSR_OFFSET)

+

+#define OST_OSTCNTH_BUF	(OST_BASE + OST_OSTCNTH_BUF_OFFSET)

+

+

+/*

+ * OST registers common define

+ */

+

+/* Operating system control register(OSTCSR) */

+#define OSTCSR_CNT_MD		BIT15

+#define OSTCSR_SD		BIT9

+#define OSTCSR_EXT_EN		BIT2

+#define OSTCSR_RTC_EN		BIT1

+#define OSTCSR_PCK_EN		BIT0

+

+#define OSTCSR_PRESCALE_LSB	3

+#define OSTCSR_PRESCALE_MASK	BITS_H2L(5, OSTCSR_PRESCALE_LSB)

+#define OSTCSR_PRESCALE1	(0x0 << OSTCSR_PRESCALE_LSB)

+#define OSTCSR_PRESCALE4	(0x1 << OSTCSR_PRESCALE_LSB)

+#define OSTCSR_PRESCALE16	(0x2 << OSTCSR_PRESCALE_LSB)

+#define OSTCSR_PRESCALE64	(0x3 << OSTCSR_PRESCALE_LSB)

+#define OSTCSR_PRESCALE256	(0x4 << OSTCSR_PRESCALE_LSB)

+#define OSTCSR_PRESCALE1024	(0x5 << OSTCSR_PRESCALE_LSB)

+

+

+#ifndef __MIPS_ASSEMBLER

+

+#define REG_OST_OSTDR		REG32(OST_OSTDR)

+

+#define REG_OST_OSTCNTL		REG32(OST_OSTCNTL)

+#define REG_OST_OSTCNTH		REG32(OST_OSTCNTH)

+

+#define REG_OST_OSTCSR		REG16(OST_OSTCSR)

+

+#define REG_OST_OSTCNTH_BUF	REG32(OST_OSTCNTH_BUF)

+

+#endif /* __MIPS_ASSEMBLER */

+

+#endif /* __JZ4770OST_H__ */

diff --git a/arch/mips/include/asm/mach-jz4770/jz4770otg.h b/arch/mips/include/asm/mach-jz4770/jz4770otg.h
new file mode 100644
index 00000000000..2be2c86becf
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4770/jz4770otg.h
@@ -0,0 +1,135 @@
+/*

+ * linux/include/asm-mips/mach-jz4810/jz4810otg.h

+ *

+ * JZ4810 OTG register definition.

+ *

+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

+ */

+

+#ifndef __JZ4770OTG_H__

+#define __JZ4770OTG_H__

+

+

+#define UDC_BASE	0xB3440000

+

+/*************************************************************************

+ * USB Device

+ *************************************************************************/

+#define USB_BASE  UDC_BASE

+

+#define USB_REG_FADDR		(USB_BASE + 0x00) /* Function Address 8-bit */

+#define USB_REG_POWER		(USB_BASE + 0x01) /* Power Managemetn 8-bit */

+#define USB_REG_INTRIN		(USB_BASE + 0x02) /* Interrupt IN 16-bit */

+#define USB_REG_INTROUT		(USB_BASE + 0x04) /* Interrupt OUT 16-bit */

+#define USB_REG_INTRINE		(USB_BASE + 0x06) /* Intr IN enable 16-bit */

+#define USB_REG_INTROUTE	(USB_BASE + 0x08) /* Intr OUT enable 16-bit */

+#define USB_REG_INTRUSB		(USB_BASE + 0x0a) /* Interrupt USB 8-bit */

+#define USB_REG_INTRUSBE	(USB_BASE + 0x0b) /* Interrupt USB Enable 8-bit */

+#define USB_REG_FRAME		(USB_BASE + 0x0c) /* Frame number 16-bit */

+#define USB_REG_INDEX		(USB_BASE + 0x0e) /* Index register 8-bit */

+#define USB_REG_TESTMODE	(USB_BASE + 0x0f) /* USB test mode 8-bit */

+

+#define USB_REG_CSR0		(USB_BASE + 0x12) /* EP0 CSR 8-bit */

+#define USB_REG_INMAXP		(USB_BASE + 0x10) /* EP1-2 IN Max Pkt Size 16-bit */

+#define USB_REG_INCSR		(USB_BASE + 0x12) /* EP1-2 IN CSR LSB 8/16bit */

+#define USB_REG_INCSRH		(USB_BASE + 0x13) /* EP1-2 IN CSR MSB 8-bit */

+#define USB_REG_OUTMAXP		(USB_BASE + 0x14) /* EP1 OUT Max Pkt Size 16-bit */

+#define USB_REG_OUTCSR		(USB_BASE + 0x16) /* EP1 OUT CSR LSB 8/16bit */

+#define USB_REG_OUTCSRH		(USB_BASE + 0x17) /* EP1 OUT CSR MSB 8-bit */

+#define USB_REG_OUTCOUNT	(USB_BASE + 0x18) /* bytes in EP0/1 OUT FIFO 16-bit */

+

+#define USB_FIFO_EP0		(USB_BASE + 0x20)

+#define USB_FIFO_EP1		(USB_BASE + 0x24)

+#define USB_FIFO_EP2		(USB_BASE + 0x28)

+

+#define USB_REG_EPINFO		(USB_BASE + 0x78) /* Endpoint information */

+#define USB_REG_RAMINFO		(USB_BASE + 0x79) /* RAM information */

+

+#define USB_REG_INTR		(USB_BASE + 0x200) /* DMA pending interrupts */

+#define USB_REG_CNTL1		(USB_BASE + 0x204) /* DMA channel 1 control */

+#define USB_REG_ADDR1		(USB_BASE + 0x208) /* DMA channel 1 AHB memory addr */

+#define USB_REG_COUNT1		(USB_BASE + 0x20c) /* DMA channel 1 byte count */

+#define USB_REG_CNTL2		(USB_BASE + 0x214) /* DMA channel 2 control */

+#define USB_REG_ADDR2		(USB_BASE + 0x218) /* DMA channel 2 AHB memory addr */

+#define USB_REG_COUNT2		(USB_BASE + 0x21c) /* DMA channel 2 byte count */

+

+

+/* Power register bit masks */

+#define USB_POWER_SUSPENDM	0x01

+#define USB_POWER_RESUME	0x04

+#define USB_POWER_HSMODE	0x10

+#define USB_POWER_HSENAB	0x20

+#define USB_POWER_SOFTCONN	0x40

+

+/* Interrupt register bit masks */

+#define USB_INTR_SUSPEND	0x01

+#define USB_INTR_RESUME		0x02

+#define USB_INTR_RESET		0x04

+

+#define USB_INTR_EP0		0x0001

+#define USB_INTR_INEP1		0x0002

+#define USB_INTR_INEP2		0x0004

+#define USB_INTR_OUTEP1		0x0002

+

+/* CSR0 bit masks */

+#define USB_CSR0_OUTPKTRDY	0x01

+#define USB_CSR0_INPKTRDY	0x02

+#define USB_CSR0_SENTSTALL	0x04

+#define USB_CSR0_DATAEND	0x08

+#define USB_CSR0_SETUPEND	0x10

+#define USB_CSR0_SENDSTALL	0x20

+#define USB_CSR0_SVDOUTPKTRDY	0x40

+#define USB_CSR0_SVDSETUPEND	0x80

+

+/* Endpoint CSR register bits */

+#define USB_INCSRH_AUTOSET	0x80

+#define USB_INCSRH_ISO		0x40

+#define USB_INCSRH_MODE		0x20

+#define USB_INCSRH_DMAREQENAB	0x10

+#define USB_INCSRH_DMAREQMODE	0x04

+#define USB_INCSR_CDT		0x40

+#define USB_INCSR_SENTSTALL	0x20

+#define USB_INCSR_SENDSTALL	0x10

+#define USB_INCSR_FF		0x08

+#define USB_INCSR_UNDERRUN	0x04

+#define USB_INCSR_FFNOTEMPT	0x02

+#define USB_INCSR_INPKTRDY	0x01

+#define USB_OUTCSRH_AUTOCLR	0x80

+#define USB_OUTCSRH_ISO		0x40

+#define USB_OUTCSRH_DMAREQENAB	0x20

+#define USB_OUTCSRH_DNYT	0x10

+#define USB_OUTCSRH_DMAREQMODE	0x08

+#define USB_OUTCSR_CDT		0x80

+#define USB_OUTCSR_SENTSTALL	0x40

+#define USB_OUTCSR_SENDSTALL	0x20

+#define USB_OUTCSR_FF		0x10

+#define USB_OUTCSR_DATAERR	0x08

+#define USB_OUTCSR_OVERRUN	0x04

+#define USB_OUTCSR_FFFULL	0x02

+#define USB_OUTCSR_OUTPKTRDY	0x01

+

+/* Testmode register bits */

+#define USB_TEST_SE0NAK		0x01

+#define USB_TEST_J		0x02

+#define USB_TEST_K		0x04

+#define USB_TEST_PACKET		0x08

+

+/* DMA control bits */

+#define USB_CNTL_ENA		0x01

+#define USB_CNTL_DIR_IN		0x02

+#define USB_CNTL_MODE_1		0x04

+#define USB_CNTL_INTR_EN	0x08

+#define USB_CNTL_EP(n)		((n) << 4)

+#define USB_CNTL_BURST_0	(0 << 9)

+#define USB_CNTL_BURST_4	(1 << 9)

+#define USB_CNTL_BURST_8	(2 << 9)

+#define USB_CNTL_BURST_16	(3 << 9)

+

+

+

+#ifndef __MIPS_ASSEMBLER

+

+#endif /* __MIPS_ASSEMBLER */

+

+#endif /* __JZ4770OTG_H__ */

+

diff --git a/arch/mips/include/asm/mach-jz4770/jz4770otp.h b/arch/mips/include/asm/mach-jz4770/jz4770otp.h
new file mode 100644
index 00000000000..33451966fa0
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4770/jz4770otp.h
@@ -0,0 +1,97 @@
+/*

+ * linux/include/asm-mips/mach-jz4810/jz4810otp.h

+ *

+ * JZ4810 OTP register definition.

+ *

+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

+ */

+

+#ifndef __JZ4770OTP_H__

+#define __JZ4770OTP_H__

+

+

+/*************************************************************************

+ * OTP (One Time Programmable Module)

+ *************************************************************************/

+#define OTP_ID0		(OTP_BASE + 0x00) /* ID0 Register */

+#define OTP_ID1		(OTP_BASE + 0x04) /* ID1 Register */

+#define OTP_ID2		(OTP_BASE + 0x08) /* ID2 Register */

+#define OTP_ID3		(OTP_BASE + 0x0C) /* ID3 Register */

+#define OTP_BR0		(OTP_BASE + 0x10) /* BOOTROM0 Register */

+#define OTP_BR1		(OTP_BASE + 0x14) /* BOOTROM1 Register */

+#define OTP_HW0		(OTP_BASE + 0x18) /* Chip Hardware 0 Register */

+#define OTP_HW1		(OTP_BASE + 0x1C) /* Chip Hardware 1 Register */

+

+#define REG_OTP_ID0	REG32(OTP_ID0)

+#define REG_OTP_ID1	REG32(OTP_ID1)

+#define REG_OTP_ID2	REG32(OTP_ID2)

+#define REG_OTP_ID3	REG32(OTP_ID3)

+#define REG_OTP_BR0	REG32(OTP_BR0)

+#define REG_OTP_BR1	REG32(OTP_BR1)

+#define REG_OTP_HW0	REG32(OTP_HW0)

+#define REG_OTP_HW1	REG32(OTP_HW1)

+

+/* ID0 Register */

+#define OTP_ID0_WID_BIT		24 /* Wafer ID */

+#define OTP_ID0_WID_MASK	(0xff << OTP_ID0_WID_BIT)

+#define OTP_ID0_MID_BIT		16 /* MASK ID */

+#define OTP_ID0_MID_MASK	(0xff << OTP_ID0_MID_BIT)

+#define OTP_ID0_FID_BIT		8 /* Foundary ID */

+#define OTP_ID0_FID_MASK	(0xff << OTP_ID0_FID_BIT)

+#define OTP_ID0_PID_BIT		0 /* Product ID */

+#define OTP_ID0_PID_MASK	(0xff << OTP_ID0_PID_BIT)

+

+/* ID1 Register */

+#define OTP_ID1_LID_BIT		8 /* Lot ID */

+#define OTP_ID1_LID_MASK	(0xffffff << OTP_ID1_LID_BIT)

+#define OTP_ID1_TID_BIT		0 /* Test House ID */

+#define OTP_ID1_TID_MASK	(0xff << OTP_ID1_TID_BIT)

+

+/* ID2 Register */

+#define OTP_ID2_XADR_BIT	24 /* Die X-dir Address */

+#define OTP_ID2_XADR_MASK	(0xff << OTP_ID2_XADR_BIT)

+#define OTP_ID2_YADR_BIT	16 /* Die Y-dir Address */

+#define OTP_ID2_YADR_MASK	(0xff << OTP_ID2_YADR_BIT)

+#define OTP_ID2_TDATE_BIT	0  /* Testing Date */

+#define OTP_ID2_TDATE_MASK	(0xffff << OTP_ID2_TDATE_BIT)

+

+/* ID3 Register */

+#define OTP_ID3_CID_BIT		16 /* Customer ID */

+#define OTP_ID3_CID_MASK	(0xffff << OTP_ID3_CID_BIT)

+#define OTP_ID3_CP_BIT		0 /* Chip Parameters */

+#define OTP_ID3_CP_MASK		(0xffff << OTP_ID3_CP_BIT)

+

+/* BOOTROM1 Register */

+#define OTP_BR1_UDCBOOT_BIT	0

+#define OTP_BR1_UDCBOOT_MASK	(0xff << OTP_BR1_UDCBOOT_BIT)

+  #define OTP_BR1_UDCBOOT_AUTO	(0xf0 << OTP_BR1_UDCBOOT_BIT)

+  #define OTP_BR1_UDCBOOT_24M	(0x0f << OTP_BR1_UDCBOOT_BIT) /* 24MHz OSC */

+  #define OTP_BR1_UDCBOOT_13M	(0x0c << OTP_BR1_UDCBOOT_BIT) /* 13MHz OSC */

+  #define OTP_BR1_UDCBOOT_26M	(0x03 << OTP_BR1_UDCBOOT_BIT) /* 26MHz OSC */

+  #define OTP_BR1_UDCBOOT_27M	(0x00 << OTP_BR1_UDCBOOT_BIT) /* 27MHz OSC */

+

+/* Chip Hardware 1 Register */

+#define OTP_HW1_MC_EN		(0x3 << 30) /* MC is enabled */

+#define OTP_HW1_ME_EN		(0x3 << 28)

+#define OTP_HW1_DE_EN		(0x3 << 26)

+#define OTP_HW1_IDCT_EN		(0x3 << 24)

+#define OTP_HW1_UART3_EN	(0x3 << 22)

+#define OTP_HW1_UART2_EN	(0x3 << 20)

+#define OTP_HW1_UART1_EN	(0x3 << 18)

+#define OTP_HW1_UART0_EN	(0x3 << 16)

+#define OTP_HW1_SSI1_EN		(0x3 << 14)

+#define OTP_HW1_SSI0_EN		(0x3 << 12)

+#define OTP_HW1_MSC1_EN		(0x3 << 10)

+#define OTP_HW1_MSC0_EN		(0x3 << 8)

+#define OTP_HW1_UHC_EN		(0x3 << 6)

+#define OTP_HW1_TVE_EN		(0x3 << 4)

+#define OTP_HW1_TSSI_EN		(0x3 << 2)

+#define OTP_HW1_CIM_EN		(0x3 << 0)

+

+

+#ifndef __MIPS_ASSEMBLER

+

+#endif /* __MIPS_ASSEMBLER */

+

+#endif /* __JZ4770OTP_H__ */

+

diff --git a/arch/mips/include/asm/mach-jz4770/jz4770owi.h b/arch/mips/include/asm/mach-jz4770/jz4770owi.h
new file mode 100644
index 00000000000..56685d204e0
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4770/jz4770owi.h
@@ -0,0 +1,120 @@
+/*

+ * linux/include/asm-mips/mach-jz4810/jz4810owi.h

+ *

+ * JZ4810 OWI register definition.

+ *

+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

+ */

+

+#ifndef __JZ4770OWI_H__

+#define __JZ4770OWI_H__

+

+

+#define	OWI_BASE	0xB0072000

+

+/*************************************************************************

+ * OWI (One-wire Bus Controller )

+ *************************************************************************/

+#define OWI_CFG (OWI_BASE + 0x00) /* OWI Configure Register */

+#define OWI_CTL (OWI_BASE + 0x04) /* OWI Control Register */

+#define OWI_STS (OWI_BASE + 0x08) /* OWI Status Register */

+#define OWI_DAT (OWI_BASE + 0x0c) /* OWI Data Register */

+#define OWI_DIV (OWI_BASE + 0x10) /* OWI Clock Divide Register */

+

+#define REG_OWI_CFG  REG8(OWI_CFG)

+#define REG_OWI_CTL  REG8(OWI_CTL)

+#define REG_OWI_STS  REG8(OWI_STS)

+#define REG_OWI_DAT  REG8(OWI_DAT)

+#define REG_OWI_DIV  REG8(OWI_DIV)

+

+/* OWI Configure Register */

+#define OWI_CFG_MODE      (1 << 7) /*  0: Regular speed mode  1: Overdrive  speed mode */

+#define OWI_CFG_RDDATA    (1 << 6) /* 1: receive data from one-wire bus and stored in OWDAT*/

+#define OWI_CFG_WRDATA    (1 << 5) /* 1: transmit the data in OWDAT */

+#define OWI_CFG_RDST      (1 << 4) /* 1: was sampled during a read */

+#define OWI_CFG_WR1RD     (1 << 3) /* 1: generate write 1 sequence on line */

+#define OWI_CFG_WR0       (1 << 2) /* 1: generate write 0 sequence on line */

+#define OWI_CFG_RST       (1 << 1) /* 1: generate reset pulse and sample slaves presence pulse*/

+#define OWI_CFG_ENA       (1 << 0) /* 1: enable the OWI operation */

+

+/* OWI Control Register */

+#define OWI_CTL_EBYTE     (1 << 2) /* enable byte write/read interrupt */

+#define OWI_CTL_EBIT      (1 << 1) /* enable bit write/read interrupt */

+#define OWI_CTL_ERST      (1 << 0) /* enable reset sequence finished interrupt */

+

+/* OWI Status Register */

+#define OWI_STS_PST       (1 << 7) /* 1: one-wire bus has device on it */

+#define OWI_STS_BYTE_RDY  (1 << 2) /* 1: have received or transmitted a data */

+#define OWI_STS_BIT_RDY   (1 << 1) /* 1: have received or transmitted a bit */

+#define OWI_STS_PST_RDY   (1 << 0) /* 1: have finished a reset pulse */

+

+/* OWI Clock Divide Register */

+#define OWI_DIV_CLKDIV_BIT  5

+

+

+#ifndef __MIPS_ASSEMBLER

+

+/***************************************************************************

+ * OWI (one-wire bus)  ops

+ ***************************************************************************/

+

+/* OW control register ops */

+#define __owi_enable_all_interrupts()      ( REG_OWI_CTL = (OWI_CTL_EBYTE | OWI_CTL_EBIT | OWI_CTL_ERST) )

+#define __owi_disable_all_interrupts()     ( REG_OWI_CTL = 0 )

+

+#define __owi_enable_byte_interrupt()      ( REG_OWI_CTL |= OWI_CTL_EBYTE )

+#define __owi_disable_byte_interrupt()     ( REG_OWI_CTL &= ~OWI_CTL_EBYTE )

+#define __owi_enable_bit_interrupt()       ( REG_OWI_CTL |= OWI_CTL_EBIT )

+#define __owi_disable_bit_interrupt()      ( REG_OWI_CTL &= ~OWI_CTL_EBIT )

+#define __owi_enable_rst_interrupt()       ( REG_OWI_CTL |= OWI_CTL_ERST ) 

+#define __owi_disable_rst_interrupt()      ( REG_OWI_CTL &=~OWI_CTL_ERST )

+

+/* OW configure register ops */

+#define __owi_select_regular_mode()        ( REG_OWI_CFG &= ~OWI_CFG_MODE )

+#define __owi_select_overdrive_mode()      ( REG_OWI_CFG |= OWI_CFG_MODE )

+

+#define __owi_set_rddata()  ( REG_OWI_CFG |= OWI_CFG_RDDATA )

+#define __owi_clr_rddata()  ( REG_OWI_CFG &= ~OWI_CFG_RDDATA )

+#define __owi_get_rddata()  ( REG_OWI_CFG & OWI_CFG_RDDATA )

+

+#define __owi_set_wrdata()  ( REG_OWI_CFG |= OWI_CFG_WRDATA )

+#define __owi_clr_wrdata()  ( REG_OWI_CFG &= ~OWI_CFG_WRDATA )

+#define __owi_get_wrdata()  ( REG_OWI_CFG & OWI_CFG_WRDATA )

+

+#define __owi_get_rdst()    ( REG_OWI_CFG & OWI_CFG_RDST )

+

+#define __owi_set_wr1rd()   ( REG_OWI_CFG |= OWI_CFG_WR1RD )

+#define __owi_clr_wr1rd()   ( REG_OWI_CFG &= ~OWI_CFG_WR1RD )

+#define __owi_get_wr1rd()   ( REG_OWI_CFG & OWI_CFG_WR1RD )

+

+#define __owi_set_wr0()     ( REG_OWI_CFG |= OWI_CFG_WR0 )

+#define __owi_clr_wr0()     ( REG_OWI_CFG &= ~OWI_CFG_WR0 )

+#define __owi_get_wr0()     ( REG_OWI_CFG & OWI_CFG_WR0 )

+

+#define __owi_set_rst()     ( REG_OWI_CFG |= OWI_CFG_RST )

+#define __owi_clr_rst()     ( REG_OWI_CFG &= ~OWI_CFG_RST )

+#define __owi_get_rst()     ( REG_OWI_CFG & OWI_CFG_RST )

+

+#define __owi_enable_ow_ops()  ( REG_OWI_CFG |= OWI_CFG_ENA )

+#define __owi_disable_ow_ops() ( REG_OWI_CFG &= ~OWI_CFG_ENA )

+#define __owi_get_enable()     ( REG_OWI_CFG & OWI_CFG_ENA )

+

+#define __owi_wait_ops_rdy()                \

+	do {				    \

+		while(__owi_get_enable());  \

+		udelay(1);		    \

+	} while(0);

+

+/* OW status register ops */

+#define __owi_clr_sts()           ( REG_OWI_STS = 0 )

+#define __owi_get_sts_pst()       ( REG_OWI_STS & OWI_STS_PST )

+#define __owi_get_sts_byte_rdy()  ( REG_OWI_STS & OWI_STS_BYTE_RDY )

+#define __owi_get_sts_bit_rdy()   ( REG_OWI_STS & OWI_STS_BIT_RDY )

+#define __owi_get_sts_pst_rdy()   ( REG_OWI_STS & OWI_STS_PST_RDY )

+

+

+

+#endif /* __MIPS_ASSEMBLER */

+

+#endif /* __JZ4770OWI_H__ */

+

diff --git a/arch/mips/include/asm/mach-jz4770/jz4770pcm.h b/arch/mips/include/asm/mach-jz4770/jz4770pcm.h
new file mode 100644
index 00000000000..6a1f7937ff2
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4770/jz4770pcm.h
@@ -0,0 +1,202 @@
+/*

+ * linux/include/asm-mips/mach-jz4810/jz4810pcm.h

+ *

+ * JZ4810 PCM register definition.

+ *

+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

+ */

+

+#ifndef __JZ4770PCM_H__

+#define __JZ4770PCM_H__

+

+

+#define	PCM_BASE        0xB0071000

+

+/*************************************************************************

+ * PCM Controller

+ *************************************************************************/

+

+#define PCM_CTL                 (PCM_BASE + 0x000)

+#define PCM_CFG                 (PCM_BASE + 0x004)

+#define PCM_DP                  (PCM_BASE + 0x008)

+#define PCM_INTC                (PCM_BASE + 0x00c)

+#define PCM_INTS                (PCM_BASE + 0x010)

+#define PCM_DIV                 (PCM_BASE + 0x014)

+

+#define REG_PCM_CTL             REG32(PCM_CTL)

+#define REG_PCM_CFG             REG32(PCM_CFG)

+#define REG_PCM_DP              REG32(PCM_DP)

+#define REG_PCM_INTC            REG32(PCM_INTC)

+#define REG_PCM_INTS            REG32(PCM_INTS)

+#define REG_PCM_DIV             REG32(PCM_DIV)

+

+/* PCM Controller control Register (PCM_CTL) */

+

+#define PCM_CTL_ERDMA		(1 << 9)  /* Enable Receive DMA */

+#define PCM_CTL_ETDMA           (1 << 8)  /* Enable Transmit DMA */

+#define PCM_CTL_LSMP		(1 << 7)  /* Play Zero sample or last sample */

+#define PCM_CTL_ERPL            (1 << 6)  /* Enable Playing Back Function */

+#define PCM_CTL_EREC            (1 << 5)  /* Enable Recording Function */

+#define PCM_CTL_FLUSH           (1 << 4)  /* FIFO flush */

+#define PCM_CTL_RST             (1 << 3)  /* Reset PCM */

+#define PCM_CTL_CLKEN           (1 << 1)  /* Enable the clock division logic */

+#define PCM_CTL_PCMEN           (1 << 0)  /* Enable PCM module */

+

+/* PCM Controller configure Register (PCM_CFG) */

+

+#define PCM_CFG_SLOT_BIT        13

+#define PCM_CFG_SLOT_MASK       (0x3 << PCM_CFG_SLOT_BIT)

+  #define PCM_CFG_SLOT_0	  (0 << PCM_CFG_SLOT_BIT) /* Slot is 0 */

+  #define PCM_CFG_SLOT_1	  (1 << PCM_CFG_SLOT_BIT) /* Slot is 1 */

+  #define PCM_CFG_SLOT_2	  (2 << PCM_CFG_SLOT_BIT) /* Slot is 2 */

+  #define PCM_CFG_SLOT_3	  (3 << PCM_CFG_SLOT_BIT) /* Slot is 3 */

+#define PCM_CFG_ISS_BIT         12

+#define PCM_CFG_ISS_MASK        (0x1 << PCM_CFG_ISS_BIT)

+  #define PCM_CFG_ISS_8           (0 << PCM_CFG_ISS_BIT)

+  #define PCM_CFG_ISS_16          (1 << PCM_CFG_ISS_BIT)

+#define PCM_CFG_OSS_BIT         11

+#define PCM_CFG_OSS_MASK        (0x1 << PCM_CFG_OSS_BIT)

+  #define PCM_CFG_OSS_8           (0 << PCM_CFG_OSS_BIT)

+  #define PCM_CFG_OSS_16          (1 << PCM_CFG_OSS_BIT)

+#define PCM_CFG_IMSBPOS         (1 << 10)

+#define PCM_CFG_OMSBPOS         (1 << 9)

+#define	PCM_CFG_RFTH_BIT	5        /* Receive FIFO Threshold */

+#define	PCM_CFG_RFTH_MASK	(0xf << PCM_CFG_RFTH_BIT)

+#define	PCM_CFG_TFTH_BIT	1         /* Transmit FIFO Threshold */

+#define	PCM_CFG_TFTH_MASK	(0xf << PCM_CFG_TFTH_BIT)

+#define PCM_CFG_MODE            (0x0 << 0)

+

+/* PCM Controller interrupt control Register (PCM_INTC) */

+

+#define PCM_INTC_ETFS           (1 << 3)

+#define PCM_INTC_ETUR           (1 << 2)

+#define PCM_INTC_ERFS           (1 << 1)

+#define PCM_INTC_EROR           (1 << 0)

+

+/* PCM Controller interrupt status Register (PCM_INTS) */

+

+#define PCM_INTS_RSTS		(1 << 14) /* Reset or flush has not complete */

+#define PCM_INTS_TFL_BIT        9

+#define PCM_INTS_TFL_MASK       (0x1f << PCM_INTS_TFL_BIT)

+#define PCM_INTS_TFS		(1 << 8) /* Tranmit FIFO Service Request */

+#define PCM_INTS_TUR		(1 << 7) /* Transmit FIFO Under Run */

+#define PCM_INTS_RFL_BIT        2

+#define PCM_INTS_RFL_MASK       (0x1f << PCM_INTS_RFL_BIT)

+#define PCM_INTS_RFS		(1 << 1) /* Receive FIFO Service Request */

+#define PCM_INTS_ROR		(1 << 0) /* Receive FIFO Over Run */

+

+/* PCM Controller clock division Register (PCM_DIV) */

+#define PCM_DIV_SYNL_BIT        11

+#define PCM_DIV_SYNL_MASK       (0x3f << PCM_DIV_SYNL_BIT)

+#define PCM_DIV_SYNDIV_BIT      6

+#define PCM_DIV_SYNDIV_MASK     (0x1f << PCM_DIV_SYNDIV_BIT)

+#define PCM_DIV_CLKDIV_BIT      0

+#define PCM_DIV_CLKDIV_MASK     (0x3f << PCM_DIV_CLKDIV_BIT)

+

+

+#ifndef __MIPS_ASSEMBLER

+

+/*************************************************************************

+ * PCM Controller operation

+ *************************************************************************/

+

+#define __pcm_enable()          ( REG_PCM_CTL |= PCM_CTL_PCMEN )

+#define __pcm_disable()         ( REG_PCM_CTL &= ~PCM_CTL_PCMEN )

+

+#define __pcm_clk_enable()      ( REG_PCM_CTL |= PCM_CTL_CLKEN )

+#define __pcm_clk_disable()     ( REG_PCM_CTL &= ~PCM_CTL_CLKEN )

+

+#define __pcm_reset()           ( REG_PCM_CTL |= PCM_CTL_RST )

+#define __pcm_flush_fifo()	( REG_PCM_CTL |= PCM_CTL_FLUSH )

+

+#define __pcm_enable_record()		( REG_PCM_CTL |= PCM_CTL_EREC )

+#define __pcm_disable_record()		( REG_PCM_CTL &= ~PCM_CTL_EREC )

+#define __pcm_enable_playback()		( REG_PCM_CTL |= PCM_CTL_ERPL )

+#define __pcm_disable_playback()	( REG_PCM_CTL &= ~PCM_CTL_ERPL )

+

+#define __pcm_enable_rxfifo()           __pcm_enable_record()

+#define __pcm_disable_rxfifo()          __pcm_disable_record()

+#define __pcm_enable_txfifo()           __pcm_enable_playback()

+#define __pcm_disable_txfifo()          __pcm_disable_playback()

+

+#define __pcm_last_sample()     ( REG_PCM_CTL |= PCM_CTL_LSMP )

+#define __pcm_zero_sample()     ( REG_PCM_CTL &= ~PCM_CTL_LSMP )

+

+#define __pcm_enable_transmit_dma()    ( REG_PCM_CTL |= PCM_CTL_ETDMA )

+#define __pcm_disable_transmit_dma()   ( REG_PCM_CTL &= ~PCM_CTL_ETDMA )

+#define __pcm_enable_receive_dma()     ( REG_PCM_CTL |= PCM_CTL_ERDMA )

+#define __pcm_disable_receive_dma()    ( REG_PCM_CTL &= ~PCM_CTL_ERDMA )

+

+#define __pcm_as_master()     ( REG_PCM_CFG &= PCM_CFG_MODE )

+#define __pcm_as_slave()      ( REG_PCM_CFG |= ~PCM_CFG_MODE )

+

+#define __pcm_set_transmit_trigger(n) 			\

+do {							\

+	REG_PCM_CFG &= ~PCM_CFG_TFTH_MASK;		\

+	REG_PCM_CFG |= ((n) << PCM_CFG_TFTH_BIT);	\

+} while(0)

+

+#define __pcm_set_receive_trigger(n) 			\

+do {							\

+	REG_PCM_CFG &= ~PCM_CFG_RFTH_MASK;		\

+	REG_PCM_CFG |= ((n) << PCM_CFG_RFTH_BIT);	\

+} while(0)

+

+#define __pcm_omsb_same_sync()   ( REG_PCM_CFG &= ~PCM_CFG_OMSBPOS )

+#define __pcm_omsb_next_sync()   ( REG_PCM_CFG |= PCM_CFG_OMSBPOS )

+

+#define __pcm_imsb_same_sync()   ( REG_PCM_CFG &= ~PCM_CFG_IMSBPOS )

+#define __pcm_imsb_next_sync()   ( REG_PCM_CFG |= PCM_CFG_IMSBPOS )

+

+/* set input sample size 8 or 16*/

+#define __pcm_set_iss(n) \

+( REG_PCM_CFG = (REG_PCM_CFG & ~PCM_CFG_ISS_MASK) | PCM_CFG_ISS_##n )

+/* set output sample size 8 or 16*/

+#define __pcm_set_oss(n) \

+( REG_PCM_CFG = (REG_PCM_CFG & ~PCM_CFG_OSS_MASK) | PCM_CFG_OSS_##n )

+

+#define __pcm_set_valid_slot(n) \

+( REG_PCM_CFG = (REG_PCM_CFG & ~PCM_CFG_SLOT_MASK) | PCM_CFG_SLOT_##n )

+

+#define __pcm_write_data(v)           ( REG_PCM_DP = (v) )

+#define __pcm_read_data()             ( REG_PCM_DP )

+

+#define __pcm_enable_tfs_intr()       ( REG_PCM_INTC |= PCM_INTC_ETFS )

+#define __pcm_disable_tfs_intr()      ( REG_PCM_INTC &= ~PCM_INTC_ETFS )

+

+#define __pcm_enable_tur_intr()       ( REG_PCM_INTC |= PCM_INTC_ETUR )

+#define __pcm_disable_tur_intr()      ( REG_PCM_INTC &= ~PCM_INTC_ETUR )

+

+#define __pcm_enable_rfs_intr()       ( REG_PCM_INTC |= PCM_INTC_ERFS )

+#define __pcm_disable_rfs_intr()      ( REG_PCM_INTC &= ~PCM_INTC_ERFS )

+

+#define __pcm_enable_ror_intr()       ( REG_PCM_INTC |= PCM_INTC_EROR )

+#define __pcm_disable_ror_intr()      ( REG_PCM_INTC &= ~PCM_INTC_EROR )

+

+#define __pcm_ints_valid_tx() \

+( ((REG_PCM_INTS & PCM_INTS_TFL_MASK) >> PCM_INTS_TFL_BIT) )

+#define __pcm_ints_valid_rx() \

+( ((REG_PCM_INTS & PCM_INTS_RFL_MASK) >> PCM_INTS_RFL_BIT) )

+

+#define __pcm_set_clk_div(n) \

+( REG_PCM_DIV = (REG_PCM_DIV & ~PCM_DIV_CLKDIV_MASK) | ((n) << PCM_DIV_CLKDIV_BIT) )

+

+/* sysclk(cpm_pcm_sysclk) Hz is created by cpm logic, and pcmclk Hz is the pcm in/out clock wanted */

+#define __pcm_set_clk_rate(sysclk, pcmclk) \

+__pcm_set_clk_div(((sysclk) / (pcmclk) - 1)) 

+

+#define __pcm_set_sync_div(n) \

+( REG_PCM_DIV = (REG_PCM_DIV & ~PCM_DIV_SYNDIV_MASK) | ((n) << PCM_DIV_SYNDIV_BIT) )

+

+/* pcmclk is source clock Hz, and sync is the frame sync clock Hz wanted */

+#define __pcm_set_sync_rate(pcmclk, sync) \

+__pcm_set_sync_div(((pcmclk) / (8 * (sync)) - 1))

+

+ /* set sync length in pcmclk n = 0 ... 63 */

+#define __pcm_set_sync_len(n) \

+( REG_PCM_DIV = (REG_PCM_DIV & ~PCM_DIV_SYNL_MASK) | (n << PCM_DIV_SYNL_BIT) )

+

+#endif /* __MIPS_ASSEMBLER */

+

+#endif /* __JZ4770PCM_H__ */

+

diff --git a/arch/mips/include/asm/mach-jz4770/jz4770rtc.h b/arch/mips/include/asm/mach-jz4770/jz4770rtc.h
new file mode 100644
index 00000000000..95851373b6b
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4770/jz4770rtc.h
@@ -0,0 +1,141 @@
+/*

+ * linux/include/asm-mips/mach-jz4810/jz4810rtc.h

+ *

+ * JZ4810 RTC register definition.

+ *

+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

+ */

+

+#ifndef __JZ4770RTC_H__

+#define __JZ4770RTC_H__

+

+

+#define	RTC_BASE	0xB0003000

+

+/*************************************************************************

+ * RTC

+ *************************************************************************/

+#define RTC_RCR		(RTC_BASE + 0x00) /* RTC Control Register */

+#define RTC_RSR		(RTC_BASE + 0x04) /* RTC Second Register */

+#define RTC_RSAR	(RTC_BASE + 0x08) /* RTC Second Alarm Register */

+#define RTC_RGR		(RTC_BASE + 0x0c) /* RTC Regulator Register */

+

+#define RTC_HCR		(RTC_BASE + 0x20) /* Hibernate Control Register */

+#define RTC_HWFCR	(RTC_BASE + 0x24) /* Hibernate Wakeup Filter Counter Reg */

+#define RTC_HRCR	(RTC_BASE + 0x28) /* Hibernate Reset Counter Register */

+#define RTC_HWCR	(RTC_BASE + 0x2c) /* Hibernate Wakeup Control Register */

+#define RTC_HWRSR	(RTC_BASE + 0x30) /* Hibernate Wakeup Status Register */

+#define RTC_HSPR	(RTC_BASE + 0x34) /* Hibernate Scratch Pattern Register */

+

+#define REG_RTC_RCR	REG32(RTC_RCR)

+#define REG_RTC_RSR	REG32(RTC_RSR)

+#define REG_RTC_RSAR	REG32(RTC_RSAR)

+#define REG_RTC_RGR	REG32(RTC_RGR)

+#define REG_RTC_HCR	REG32(RTC_HCR)

+#define REG_RTC_HWFCR	REG32(RTC_HWFCR)

+#define REG_RTC_HRCR	REG32(RTC_HRCR)

+#define REG_RTC_HWCR	REG32(RTC_HWCR)

+#define REG_RTC_HWRSR	REG32(RTC_HWRSR)

+#define REG_RTC_HSPR	REG32(RTC_HSPR)

+

+/* RTC Control Register */

+#define RTC_RCR_WRDY_BIT 7

+#define RTC_RCR_WRDY	(1 << 7)  /* Write Ready Flag */

+#define RTC_RCR_1HZ_BIT	6

+#define RTC_RCR_1HZ	(1 << RTC_RCR_1HZ_BIT)  /* 1Hz Flag */

+#define RTC_RCR_1HZIE	(1 << 5)  /* 1Hz Interrupt Enable */

+#define RTC_RCR_AF_BIT	4

+#define RTC_RCR_AF	(1 << RTC_RCR_AF_BIT)  /* Alarm Flag */

+#define RTC_RCR_AIE	(1 << 3)  /* Alarm Interrupt Enable */

+#define RTC_RCR_AE	(1 << 2)  /* Alarm Enable */

+#define RTC_RCR_RTCE	(1 << 0)  /* RTC Enable */

+

+/* RTC Regulator Register */

+#define RTC_RGR_LOCK		(1 << 31) /* Lock Bit */

+#define RTC_RGR_ADJC_BIT	16

+#define RTC_RGR_ADJC_MASK	(0x3ff << RTC_RGR_ADJC_BIT)

+#define RTC_RGR_NC1HZ_BIT	0

+#define RTC_RGR_NC1HZ_MASK	(0xffff << RTC_RGR_NC1HZ_BIT)

+

+/* Hibernate Control Register */

+#define RTC_HCR_PD		(1 << 0)  /* Power Down */

+

+/* Hibernate Wakeup Filter Counter Register */

+#define RTC_HWFCR_BIT		5

+#define RTC_HWFCR_MASK		(0x7ff << RTC_HWFCR_BIT)

+

+/* Hibernate Reset Counter Register */

+#define RTC_HRCR_BIT		5

+#define RTC_HRCR_MASK		(0x7f << RTC_HRCR_BIT)

+

+/* Hibernate Wakeup Control Register */

+#define RTC_HWCR_EALM		(1 << 0)  /* RTC alarm wakeup enable */

+

+/* Hibernate Wakeup Status Register */

+#define RTC_HWRSR_HR		(1 << 5)  /* Hibernate reset */

+#define RTC_HWRSR_PPR		(1 << 4)  /* PPR reset */

+#define RTC_HWRSR_PIN		(1 << 1)  /* Wakeup pin status bit */

+#define RTC_HWRSR_ALM		(1 << 0)  /* RTC alarm status bit */

+

+

+#ifndef __MIPS_ASSEMBLER

+

+/***************************************************************************

+ * RTC ops

+ ***************************************************************************/

+

+#define __rtc_write_ready()  ( (REG_RTC_RCR & RTC_RCR_WRDY) >> RTC_RCR_WRDY_BIT )

+#define __rtc_enabled()        ( REG_RTC_RCR |= RTC_RCR_RTCE )

+#define __rtc_disabled()         ( REG_RTC_RCR &= ~RTC_RCR_RTCE )

+#define __rtc_enable_alarm()         ( REG_RTC_RCR |= RTC_RCR_AE )

+#define __rtc_disable_alarm()         ( REG_RTC_RCR &= ~RTC_RCR_AE )

+#define __rtc_enable_alarm_irq()         ( REG_RTC_RCR |= RTC_RCR_AIE )

+#define __rtc_disable_alarm_irq()         ( REG_RTC_RCR &= ~RTC_RCR_AIE )

+#define __rtc_enable_1Hz_irq()         ( REG_RTC_RCR |= RTC_RCR_1HZIE )

+#define __rtc_disable_1Hz_irq()         ( REG_RTC_RCR &= ~RTC_RCR_1HZIE )

+

+#define __rtc_get_1Hz_flag()           ( (REG_RTC_RCR >> RTC_RCR_1HZ_BIT) & 0x1 )

+#define __rtc_clear_1Hz_flag()           ( REG_RTC_RCR &= ~RTC_RCR_1HZ )

+#define __rtc_get_alarm_flag()           ( (REG_RTC_RCR >> RTC_RCR_AF_BIT) & 0x1 )

+#define __rtc_clear_alarm_flag()           ( REG_RTC_RCR &= ~RTC_RCR_AF )

+

+#define __rtc_get_second()   ( REG_RTC_RSR )

+#define __rtc_set_second(v)   ( REG_RTC_RSR = v )

+

+#define __rtc_get_alarm_second()   ( REG_RTC_RSAR )

+#define __rtc_set_alarm_second(v)   ( REG_RTC_RSAR = v )

+

+#define __rtc_RGR_is_locked()       ( (REG_RTC_RGR >> RTC_RGR_LOCK) )

+#define __rtc_lock_RGR()       ( REG_RTC_RGR |= RTC_RGR_LOCK )

+#define __rtc_unlock_RGR()       ( REG_RTC_RGR &= ~RTC_RGR_LOCK )

+#define __rtc_get_adjc_val()       ( (REG_RTC_RGR & RTC_RGR_ADJC_MASK) >> RTC_RGR_ADJC_BIT )

+#define __rtc_set_adjc_val(v)      \

+       ( REG_RTC_RGR = ( (REG_RTC_RGR & ~RTC_RGR_ADJC_MASK) | (v << RTC_RGR_ADJC_BIT) ))

+#define __rtc_get_nc1Hz_val()       ( (REG_RTC_RGR & RTC_RGR_NC1HZ_MASK) >> RTC_RGR_NC1HZ_BIT )

+#define __rtc_set_nc1Hz_val(v)      \

+       ( REG_RTC_RGR = ( (REG_RTC_RGR & ~RTC_RGR_NC1HZ_MASK) | (v << RTC_RGR_NC1HZ_BIT) ))

+

+#define __rtc_power_down()            ( REG_RTC_HCR |= RTC_HCR_PD )

+

+#define __rtc_get_hwfcr_val()         ( REG_RTC_HWFCR & RTC_HWFCR_MASK )

+#define __rtc_set_hwfcr_val(v)         ( REG_RTC_HWFCR = (v) & RTC_HWFCR_MASK )

+#define __rtc_get_hrcr_val()         ( REG_RTC_HRCR & RTC_HRCR_MASK )

+#define __rtc_set_hrcr_val(v)         ( REG_RTC_HRCR = (v) & RTC_HRCR_MASK )

+

+#define __rtc_enable_alarm_wakeup()        ( REG_RTC_HWCR |= RTC_HWCR_EALM )

+#define __rtc_disable_alarm_wakeup()        ( REG_RTC_HWCR &= ~RTC_HWCR_EALM )

+

+#define __rtc_status_hib_reset_occur()        ( (REG_RTC_HWRSR >> RTC_HWRSR_HR) & 0x1 )

+#define __rtc_status_ppr_reset_occur()        ( (REG_RTC_HWRSR >> RTC_HWRSR_PPR) & 0x1 )

+#define __rtc_status_wakeup_pin_waken_up()    ( (REG_RTC_HWRSR >> RTC_HWRSR_PIN) & 0x1 )

+#define __rtc_status_alarm_waken_up()        ( (REG_RTC_HWRSR >> RTC_HWRSR_ALM) & 0x1 )

+#define __rtc_clear_hib_stat_all()               ( REG_RTC_HWRSR = 0 )

+

+#define __rtc_get_scratch_pattern() 		(REG_RTC_HSPR)

+#define __rtc_set_scratch_pattern(n) 		(REG_RTC_HSPR = n )

+

+

+#endif /* __MIPS_ASSEMBLER */

+

+#endif /* __JZ4770RTC_H__ */

+

diff --git a/arch/mips/include/asm/mach-jz4770/jz4770sadc.h b/arch/mips/include/asm/mach-jz4770/jz4770sadc.h
new file mode 100644
index 00000000000..4d4686a0ff5
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4770/jz4770sadc.h
@@ -0,0 +1,116 @@
+/*

+ * linux/include/asm-mips/mach-jz4810/jz4810sadc.h

+ *

+ * JZ4810 SADC register definition.

+ *

+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

+ */

+

+#ifndef __JZ4770SADC_H__

+#define __JZ4770SADC_H__

+

+

+#define	SADC_BASE	0xB0070000

+

+/*************************************************************************

+ * SADC (Smart A/D Controller)

+ *************************************************************************/

+

+#define SADC_ENA	(SADC_BASE + 0x00)  /* ADC Enable Register */

+#define SADC_CFG	(SADC_BASE + 0x04)  /* ADC Configure Register */

+#define SADC_CTRL	(SADC_BASE + 0x08)  /* ADC Control Register */

+#define SADC_STATE	(SADC_BASE + 0x0C)  /* ADC Status Register*/

+#define SADC_SAMETIME	(SADC_BASE + 0x10)  /* ADC Same Point Time Register */

+#define SADC_WAITTIME	(SADC_BASE + 0x14)  /* ADC Wait Time Register */

+#define SADC_TSDAT	(SADC_BASE + 0x18)  /* ADC Touch Screen Data Register */

+#define SADC_BATDAT	(SADC_BASE + 0x1C)  /* ADC VBAT Data Register */

+#define SADC_SADDAT	(SADC_BASE + 0x20)  /* ADC AUX Data Register */

+#define SADC_ADCLK	(SADC_BASE + 0x28)  /* ADC Clock Divide Register */

+#define SADC_FLT	(SADC_BASE + 0x24)  /* ADC Filter Register */

+

+#define REG_SADC_ENA		REG8(SADC_ENA)

+#define REG_SADC_CFG		REG32(SADC_CFG)

+#define REG_SADC_CTRL		REG8(SADC_CTRL)

+#define REG_SADC_STATE		REG8(SADC_STATE)

+#define REG_SADC_SAMETIME	REG16(SADC_SAMETIME)

+#define REG_SADC_WAITTIME	REG16(SADC_WAITTIME)

+#define REG_SADC_TSDAT		REG32(SADC_TSDAT)

+#define REG_SADC_BATDAT		REG16(SADC_BATDAT)

+#define REG_SADC_SADDAT		REG16(SADC_SADDAT)

+#define REG_SADC_ADCLK		REG32(SADC_ADCLK)

+#define REG_SADC_FLT		REG16(SADC_FLT)

+   #define SADC_FLT_ENA		(1 << 15)

+

+/* ADENA: ADC Enable Register */

+#define SADC_ENA_POWER		(1 << 7)  /* SADC Power control bit */

+#define SADC_ENA_SLP_MD		(1 << 6)  /* SLEEP mode control */

+#define SADC_ENA_TSEN		(1 << 2)  /* Touch Screen Enable */

+#define SADC_ENA_PBATEN		(1 << 1)  /* PBAT Enable */

+#define SADC_ENA_SADCINEN	(1 << 0)  /* AUX n Enable */

+

+/* ADC Configure Register */

+#define SADC_CFG_SPZZ           (1 << 30)

+#define SADC_CFG_TS_DMA		(1 << 15)  /* Touch Screen DMA Enable */

+#define SADC_CFG_XYZ_BIT	13  /* XYZ selection */

+#define SADC_CFG_XYZ_MASK	(0x3 << SADC_CFG_XYZ_BIT)

+  #define SADC_CFG_XY		(0 << SADC_CFG_XYZ_BIT)

+  #define SADC_CFG_XYZ		(1 << SADC_CFG_XYZ_BIT)

+  #define SADC_CFG_XYZ1Z2	(2 << SADC_CFG_XYZ_BIT)

+#define SADC_CFG_SNUM_BIT	10  /* Sample Number */

+#define SADC_CFG_SNUM(x)	(((x) - 1) << SADC_CFG_SNUM_BIT)

+#define SADC_CFG_SNUM_MASK	(0x7 << SADC_CFG_SNUM_BIT)

+  #define SADC_CFG_SNUM_1	(0x0 << SADC_CFG_SNUM_BIT)

+  #define SADC_CFG_SNUM_2	(0x1 << SADC_CFG_SNUM_BIT)

+  #define SADC_CFG_SNUM_3	(0x2 << SADC_CFG_SNUM_BIT)

+  #define SADC_CFG_SNUM_4	(0x3 << SADC_CFG_SNUM_BIT)

+  #define SADC_CFG_SNUM_5	(0x4 << SADC_CFG_SNUM_BIT)

+  #define SADC_CFG_SNUM_6	(0x5 << SADC_CFG_SNUM_BIT)

+  #define SADC_CFG_SNUM_8	(0x6 << SADC_CFG_SNUM_BIT)

+  #define SADC_CFG_SNUM_9	(0x7 << SADC_CFG_SNUM_BIT)

+#define SADC_CFG_CMD_BIT	0  /* ADC Command */

+#define SADC_CFG_CMD_MASK	(0x3 << SADC_CFG_CMD_BIT)

+  #define SADC_CFG_CMD_AUX0	(0x0 << SADC_CFG_CMD_BIT) /* AUX voltage */

+  #define SADC_CFG_CMD_AUX1	(0x1 << SADC_CFG_CMD_BIT) /* AUX1 voltage */

+  #define SADC_CFG_CMD_AUX2	(0x2 << SADC_CFG_CMD_BIT) /* AUX2 voltage */

+  #define SADC_CFG_CMD_RESERVED	(0x3 << SADC_CFG_CMD_BIT) /* Reserved */

+

+/* ADCCTRL: ADC Control Register */

+#define SADC_CTRL_SLPENDM	(1 << 5)  /* Sleep Interrupt Mask */

+#define SADC_CTRL_PENDM		(1 << 4)  /* Pen Down Interrupt Mask */

+#define SADC_CTRL_PENUM		(1 << 3)  /* Pen Up Interrupt Mask */

+#define SADC_CTRL_TSRDYM	(1 << 2)  /* Touch Screen Data Ready Interrupt Mask */

+#define SADC_CTRL_PBATRDYM	(1 << 1)  /* VBAT Data Ready Interrupt Mask */

+#define SADC_CTRL_SRDYM		(1 << 0)  /* AUX Data Ready Interrupt Mask */

+

+/* ADSTATE: ADC Status Register */

+#define SADC_STATE_SLP_RDY	(1 << 7)  /* Sleep state bit */

+#define SADC_STATE_SLEEPND	(1 << 5)  /* Pen Down Interrupt Flag */

+#define SADC_STATE_PEND		(1 << 4)  /* Pen Down Interrupt Flag */

+#define SADC_STATE_PENU		(1 << 3)  /* Pen Up Interrupt Flag */

+#define SADC_STATE_TSRDY	(1 << 2)  /* Touch Screen Data Ready Interrupt Flag */

+#define SADC_STATE_PBATRDY		(1 << 1)  /* VBAT Data Ready Interrupt Flag */

+#define SADC_STATE_SRDY		(1 << 0)  /* AUX Data Ready Interrupt Flag */

+

+/* ADTCH: ADC Touch Screen Data Register */

+#define SADC_TSDAT_TYPE1	(1 << 31)

+#define SADC_TSDAT_DATA1_BIT	16

+#define SADC_TSDAT_DATA1_MASK	(0xfff << SADC_TSDAT_DATA1_BIT)

+#define SADC_TSDAT_TYPE0	(1 << 15)

+#define SADC_TSDAT_DATA0_BIT	0

+#define SADC_TSDAT_DATA0_MASK	(0xfff << SADC_TSDAT_DATA0_BIT)

+

+/* ADCLK: ADC Clock Divide Register */

+#define SADC_ADCLK_CLKDIV_MS	16

+#define SADC_ADCLK_CLKDIV_MS_MASK	(0xffff << SADC_ADCLK_CLKDIV_MS)

+#define SADC_ADCLK_CLKDIV_US	8

+#define SADC_ADCLK_CLKDIV_US_MASK	(0xff << SADC_ADCLK_CLKDIV_US)

+#define SADC_ADCLK_CLKDIV_BIT		0

+#define SADC_ADCLK_CLKDIV_MASK		(0xff << SADC_ADCLK_CLKDIV_BIT)

+

+

+#ifndef __MIPS_ASSEMBLER

+

+#endif /* __MIPS_ASSEMBLER */

+

+#endif /* __JZ4770SADC_H__ */

+

diff --git a/arch/mips/include/asm/mach-jz4770/jz4770scc.h b/arch/mips/include/asm/mach-jz4770/jz4770scc.h
new file mode 100644
index 00000000000..9216fb919fc
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4770/jz4770scc.h
@@ -0,0 +1,191 @@
+/*

+ * linux/include/asm-mips/mach-jz4810/jz4810scc.h

+ *

+ * JZ4810 SCC register definition.

+ *

+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

+ */

+

+#ifndef __JZ4770SCC_H__

+#define __JZ4770SCC_H__

+

+

+#define	SCC_BASE	0xB0040000

+

+/*************************************************************************

+ * SCC

+ *************************************************************************/

+#define	SCC_DR			(SCC_BASE + 0x000)

+#define	SCC_FDR			(SCC_BASE + 0x004)

+#define	SCC_CR			(SCC_BASE + 0x008)

+#define	SCC_SR			(SCC_BASE + 0x00C)

+#define	SCC_TFR			(SCC_BASE + 0x010)

+#define	SCC_EGTR		(SCC_BASE + 0x014)

+#define	SCC_ECR			(SCC_BASE + 0x018)

+#define	SCC_RTOR		(SCC_BASE + 0x01C)

+

+#define REG_SCC_DR		REG8(SCC_DR)

+#define REG_SCC_FDR		REG8(SCC_FDR)

+#define REG_SCC_CR		REG32(SCC_CR)

+#define REG_SCC_SR		REG16(SCC_SR)

+#define REG_SCC_TFR		REG16(SCC_TFR)

+#define REG_SCC_EGTR		REG8(SCC_EGTR)

+#define REG_SCC_ECR		REG32(SCC_ECR)

+#define REG_SCC_RTOR		REG8(SCC_RTOR)

+

+/* SCC FIFO Data Count Register (SCC_FDR) */

+

+#define SCC_FDR_EMPTY		0x00

+#define SCC_FDR_FULL		0x10

+

+/* SCC Control Register (SCC_CR) */

+

+#define SCC_CR_SCCE		(1 << 31)

+#define SCC_CR_TRS		(1 << 30)

+#define SCC_CR_T2R		(1 << 29)

+#define SCC_CR_FDIV_BIT		24

+#define SCC_CR_FDIV_MASK	(0x3 << SCC_CR_FDIV_BIT)

+  #define SCC_CR_FDIV_1		(0 << SCC_CR_FDIV_BIT) /* SCC_CLK frequency is the same as device clock */

+  #define SCC_CR_FDIV_2		(1 << SCC_CR_FDIV_BIT) /* SCC_CLK frequency is half of device clock */

+#define SCC_CR_FLUSH		(1 << 23)

+#define SCC_CR_TRIG_BIT		16

+#define SCC_CR_TRIG_MASK	(0x3 << SCC_CR_TRIG_BIT)

+  #define SCC_CR_TRIG_1		(0 << SCC_CR_TRIG_BIT) /* Receive/Transmit-FIFO Trigger is 1 */

+  #define SCC_CR_TRIG_4		(1 << SCC_CR_TRIG_BIT) /* Receive/Transmit-FIFO Trigger is 4 */

+  #define SCC_CR_TRIG_8		(2 << SCC_CR_TRIG_BIT) /* Receive/Transmit-FIFO Trigger is 8 */

+  #define SCC_CR_TRIG_14	(3 << SCC_CR_TRIG_BIT) /* Receive/Transmit-FIFO Trigger is 14 */

+#define SCC_CR_TP		(1 << 15)

+#define SCC_CR_CONV		(1 << 14)

+#define SCC_CR_TXIE		(1 << 13)

+#define SCC_CR_RXIE		(1 << 12)

+#define SCC_CR_TENDIE		(1 << 11)

+#define SCC_CR_RTOIE		(1 << 10)

+#define SCC_CR_ECIE		(1 << 9)

+#define SCC_CR_EPIE		(1 << 8)

+#define SCC_CR_RETIE		(1 << 7)

+#define SCC_CR_EOIE		(1 << 6)

+#define SCC_CR_TSEND		(1 << 3)

+#define SCC_CR_PX_BIT		1

+#define SCC_CR_PX_MASK		(0x3 << SCC_CR_PX_BIT)

+  #define SCC_CR_PX_NOT_SUPPORT	(0 << SCC_CR_PX_BIT) /* SCC does not support clock stop */

+  #define SCC_CR_PX_STOP_LOW	(1 << SCC_CR_PX_BIT) /* SCC_CLK stops at state low */

+  #define SCC_CR_PX_STOP_HIGH	(2 << SCC_CR_PX_BIT) /* SCC_CLK stops at state high */

+#define SCC_CR_CLKSTP		(1 << 0)

+

+/* SCC Status Register (SCC_SR) */

+

+#define SCC_SR_TRANS		(1 << 15)

+#define SCC_SR_ORER		(1 << 12)

+#define SCC_SR_RTO		(1 << 11)

+#define SCC_SR_PER		(1 << 10)

+#define SCC_SR_TFTG		(1 << 9)

+#define SCC_SR_RFTG		(1 << 8)

+#define SCC_SR_TEND		(1 << 7)

+#define SCC_SR_RETR_3		(1 << 4)

+#define SCC_SR_ECNTO		(1 << 0)

+

+

+#ifndef __MIPS_ASSEMBLER

+

+/***************************************************************************

+ * SCC

+ ***************************************************************************/

+

+#define __scc_enable()			( REG_SCC_CR |= SCC_CR_SCCE )

+#define __scc_disable()			( REG_SCC_CR &= ~SCC_CR_SCCE )

+

+#define __scc_set_tx_mode()		( REG_SCC_CR |= SCC_CR_TRS )

+#define __scc_set_rx_mode()		( REG_SCC_CR &= ~SCC_CR_TRS )

+

+#define __scc_enable_t2r()		( REG_SCC_CR |= SCC_CR_T2R )

+#define __scc_disable_t2r()		( REG_SCC_CR &= ~SCC_CR_T2R )

+

+#define __scc_clk_as_devclk()			\

+do {						\

+  REG_SCC_CR &= ~SCC_CR_FDIV_MASK;		\

+  REG_SCC_CR |= SCC_CR_FDIV_1;			\

+} while (0)

+

+#define __scc_clk_as_half_devclk()		\

+do {						\

+  REG_SCC_CR &= ~SCC_CR_FDIV_MASK;		\

+  REG_SCC_CR |= SCC_CR_FDIV_2;			\

+} while (0)

+

+/* n=1,4,8,14 */

+#define __scc_set_fifo_trigger(n)		\

+do {						\

+  REG_SCC_CR &= ~SCC_CR_TRIG_MASK;		\

+  REG_SCC_CR |= SCC_CR_TRIG_##n;		\

+} while (0)

+

+#define __scc_set_protocol(p)			\

+do {						\

+	if (p)					\

+	  	REG_SCC_CR |= SCC_CR_TP;	\

+	else					\

+	 	REG_SCC_CR &= ~SCC_CR_TP;	\

+} while (0)

+

+#define __scc_flush_fifo()		( REG_SCC_CR |= SCC_CR_FLUSH )

+

+#define __scc_set_invert_mode()		( REG_SCC_CR |= SCC_CR_CONV )

+#define __scc_set_direct_mode()		( REG_SCC_CR &= ~SCC_CR_CONV )

+

+#define SCC_ERR_INTRS \

+    ( SCC_CR_ECIE | SCC_CR_EPIE | SCC_CR_RETIE | SCC_CR_EOIE )

+#define SCC_ALL_INTRS \

+    ( SCC_CR_TXIE | SCC_CR_RXIE | SCC_CR_TENDIE | SCC_CR_RTOIE | \

+      SCC_CR_ECIE | SCC_CR_EPIE | SCC_CR_RETIE | SCC_CR_EOIE )

+

+#define __scc_enable_err_intrs()	( REG_SCC_CR |= SCC_ERR_INTRS )

+#define __scc_disable_err_intrs()	( REG_SCC_CR &= ~SCC_ERR_INTRS )

+

+#define SCC_ALL_ERRORS \

+    ( SCC_SR_ORER | SCC_SR_RTO | SCC_SR_PER | SCC_SR_RETR_3 | SCC_SR_ECNTO)

+

+#define __scc_clear_errors()		( REG_SCC_SR &= ~SCC_ALL_ERRORS )

+

+#define __scc_enable_all_intrs()	( REG_SCC_CR |= SCC_ALL_INTRS )

+#define __scc_disable_all_intrs()	( REG_SCC_CR &= ~SCC_ALL_INTRS )

+

+#define __scc_enable_tx_intr()		( REG_SCC_CR |= SCC_CR_TXIE | SCC_CR_TENDIE )

+#define __scc_disable_tx_intr()		( REG_SCC_CR &= ~(SCC_CR_TXIE | SCC_CR_TENDIE) )

+

+#define __scc_enable_rx_intr()		( REG_SCC_CR |= SCC_CR_RXIE)

+#define __scc_disable_rx_intr()		( REG_SCC_CR &= ~SCC_CR_RXIE)

+

+#define __scc_set_tsend()		( REG_SCC_CR |= SCC_CR_TSEND )

+#define __scc_clear_tsend()		( REG_SCC_CR &= ~SCC_CR_TSEND )

+

+#define __scc_set_clockstop()		( REG_SCC_CR |= SCC_CR_CLKSTP )

+#define __scc_clear_clockstop()		( REG_SCC_CR &= ~SCC_CR_CLKSTP )

+

+#define __scc_clockstop_low()			\

+do {						\

+  REG_SCC_CR &= ~SCC_CR_PX_MASK;		\

+  REG_SCC_CR |= SCC_CR_PX_STOP_LOW;		\

+} while (0)

+

+#define __scc_clockstop_high()			\

+do {						\

+  REG_SCC_CR &= ~SCC_CR_PX_MASK;		\

+  REG_SCC_CR |= SCC_CR_PX_STOP_HIGH;		\

+} while (0)

+

+/* SCC status checking */

+#define __scc_check_transfer_status()		( REG_SCC_SR & SCC_SR_TRANS )

+#define __scc_check_rx_overrun_error()		( REG_SCC_SR & SCC_SR_ORER )

+#define __scc_check_rx_timeout()		( REG_SCC_SR & SCC_SR_RTO )

+#define __scc_check_parity_error()		( REG_SCC_SR & SCC_SR_PER )

+#define __scc_check_txfifo_trigger()		( REG_SCC_SR & SCC_SR_TFTG )

+#define __scc_check_rxfifo_trigger()		( REG_SCC_SR & SCC_SR_RFTG )

+#define __scc_check_tx_end()			( REG_SCC_SR & SCC_SR_TEND )

+#define __scc_check_retx_3()			( REG_SCC_SR & SCC_SR_RETR_3 )

+#define __scc_check_ecnt_overflow()		( REG_SCC_SR & SCC_SR_ECNTO )

+

+

+#endif /* __MIPS_ASSEMBLER */

+

+#endif /* __JZ4770SCC_H__ */

+

diff --git a/arch/mips/include/asm/mach-jz4770/jz4770ssi.h b/arch/mips/include/asm/mach-jz4770/jz4770ssi.h
new file mode 100644
index 00000000000..ffab5a369e9
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4770/jz4770ssi.h
@@ -0,0 +1,350 @@
+/*

+ * linux/include/asm-mips/mach-jz4810/jz4810ssi.h

+ *

+ * JZ4810 SSI register definition.

+ *

+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

+ */

+

+#ifndef __JZ4770SSI_H__

+#define __JZ4770SSI_H__

+

+

+#define	SSI0_BASE	0xB0043000

+#define	SSI1_BASE	0xB0044000

+#define	SSI2_BASE	0xB0045000

+

+

+

+/*************************************************************************

+ * SSI (Synchronous Serial Interface)

+ *************************************************************************/

+/* n = 0, 1 (SSI0, SSI1) */

+#define	SSI_DR(n)		(SSI0_BASE + 0x000 + (n)*0x2000)

+#define	SSI_CR0(n)		(SSI0_BASE + 0x004 + (n)*0x2000)

+#define	SSI_CR1(n)		(SSI0_BASE + 0x008 + (n)*0x2000)

+#define	SSI_SR(n)		(SSI0_BASE + 0x00C + (n)*0x2000)

+#define	SSI_ITR(n)		(SSI0_BASE + 0x010 + (n)*0x2000)

+#define	SSI_ICR(n)		(SSI0_BASE + 0x014 + (n)*0x2000)

+#define	SSI_GR(n)		(SSI0_BASE + 0x018 + (n)*0x2000)

+

+#define	REG_SSI_DR(n)		REG32(SSI_DR(n))

+#define	REG_SSI_CR0(n)		REG16(SSI_CR0(n))

+#define	REG_SSI_CR1(n)		REG32(SSI_CR1(n))

+#define	REG_SSI_SR(n)		REG32(SSI_SR(n))

+#define	REG_SSI_ITR(n)		REG16(SSI_ITR(n))

+#define	REG_SSI_ICR(n)		REG8(SSI_ICR(n))

+#define	REG_SSI_GR(n)		REG16(SSI_GR(n))

+

+/* SSI Data Register (SSI_DR) */

+

+#define	SSI_DR_GPC_BIT		0

+#define	SSI_DR_GPC_MASK		(0x1ff << SSI_DR_GPC_BIT)

+

+#define SSI_MAX_FIFO_ENTRIES 	128 /* 128 txfifo and 128 rxfifo */

+

+/* SSI Control Register 0 (SSI_CR0) */

+

+#define SSI_CR0_SSIE		(1 << 15)

+#define SSI_CR0_TIE		(1 << 14)

+#define SSI_CR0_RIE		(1 << 13)

+#define SSI_CR0_TEIE		(1 << 12)

+#define SSI_CR0_REIE		(1 << 11)

+#define SSI_CR0_LOOP		(1 << 10)

+#define SSI_CR0_RFINE		(1 << 9)

+#define SSI_CR0_RFINC		(1 << 8)

+#define SSI_CR0_EACLRUN		(1 << 7) /* hardware auto clear underrun when TxFifo no empty */

+#define SSI_CR0_FSEL		(1 << 6)

+#define SSI_CR0_TFLUSH		(1 << 2)

+#define SSI_CR0_RFLUSH		(1 << 1)

+#define SSI_CR0_DISREV		(1 << 0)

+

+/* SSI Control Register 1 (SSI_CR1) */

+

+#define SSI_CR1_FRMHL_BIT	30

+#define SSI_CR1_FRMHL_MASK	(0x3 << SSI_CR1_FRMHL_BIT)

+  #define SSI_CR1_FRMHL_CELOW_CE2LOW	(0 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is low valid */

+  #define SSI_CR1_FRMHL_CEHIGH_CE2LOW	(1 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is low valid */

+  #define SSI_CR1_FRMHL_CELOW_CE2HIGH	(2 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid  and SSI_CE2_ is high valid */

+  #define SSI_CR1_FRMHL_CEHIGH_CE2HIGH	(3 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is high valid */

+#define SSI_CR1_TFVCK_BIT	28

+#define SSI_CR1_TFVCK_MASK	(0x3 << SSI_CR1_TFVCK_BIT)

+  #define SSI_CR1_TFVCK_0	  (0 << SSI_CR1_TFVCK_BIT)

+  #define SSI_CR1_TFVCK_1	  (1 << SSI_CR1_TFVCK_BIT)

+  #define SSI_CR1_TFVCK_2	  (2 << SSI_CR1_TFVCK_BIT)

+  #define SSI_CR1_TFVCK_3	  (3 << SSI_CR1_TFVCK_BIT)

+#define SSI_CR1_TCKFI_BIT	26

+#define SSI_CR1_TCKFI_MASK	(0x3 << SSI_CR1_TCKFI_BIT)

+  #define SSI_CR1_TCKFI_0	  (0 << SSI_CR1_TCKFI_BIT)

+  #define SSI_CR1_TCKFI_1	  (1 << SSI_CR1_TCKFI_BIT)

+  #define SSI_CR1_TCKFI_2	  (2 << SSI_CR1_TCKFI_BIT)

+  #define SSI_CR1_TCKFI_3	  (3 << SSI_CR1_TCKFI_BIT)

+#define SSI_CR1_LFST		(1 << 25)

+#define SSI_CR1_ITFRM		(1 << 24)

+#define SSI_CR1_UNFIN		(1 << 23)

+#define SSI_CR1_MULTS		(1 << 22)

+#define SSI_CR1_FMAT_BIT	20

+#define SSI_CR1_FMAT_MASK	(0x3 << SSI_CR1_FMAT_BIT)

+  #define SSI_CR1_FMAT_SPI	  (0 << SSI_CR1_FMAT_BIT) /* Motorola¡¯s SPI format */

+  #define SSI_CR1_FMAT_SSP	  (1 << SSI_CR1_FMAT_BIT) /* TI's SSP format */

+  #define SSI_CR1_FMAT_MW1	  (2 << SSI_CR1_FMAT_BIT) /* National Microwire 1 format */

+  #define SSI_CR1_FMAT_MW2	  (3 << SSI_CR1_FMAT_BIT) /* National Microwire 2 format */

+#define SSI_CR1_TTRG_BIT	16 /* SSI1 TX trigger */

+#define SSI_CR1_TTRG_MASK	(0xf << SSI_CR1_TTRG_BIT) 

+#define SSI_CR1_MCOM_BIT	12

+#define SSI_CR1_MCOM_MASK	(0xf << SSI_CR1_MCOM_BIT)

+  #define SSI_CR1_MCOM_1BIT	  (0x0 << SSI_CR1_MCOM_BIT) /* 1-bit command selected */

+  #define SSI_CR1_MCOM_2BIT	  (0x1 << SSI_CR1_MCOM_BIT) /* 2-bit command selected */

+  #define SSI_CR1_MCOM_3BIT	  (0x2 << SSI_CR1_MCOM_BIT) /* 3-bit command selected */

+  #define SSI_CR1_MCOM_4BIT	  (0x3 << SSI_CR1_MCOM_BIT) /* 4-bit command selected */

+  #define SSI_CR1_MCOM_5BIT	  (0x4 << SSI_CR1_MCOM_BIT) /* 5-bit command selected */

+  #define SSI_CR1_MCOM_6BIT	  (0x5 << SSI_CR1_MCOM_BIT) /* 6-bit command selected */

+  #define SSI_CR1_MCOM_7BIT	  (0x6 << SSI_CR1_MCOM_BIT) /* 7-bit command selected */

+  #define SSI_CR1_MCOM_8BIT	  (0x7 << SSI_CR1_MCOM_BIT) /* 8-bit command selected */

+  #define SSI_CR1_MCOM_9BIT	  (0x8 << SSI_CR1_MCOM_BIT) /* 9-bit command selected */

+  #define SSI_CR1_MCOM_10BIT	  (0x9 << SSI_CR1_MCOM_BIT) /* 10-bit command selected */

+  #define SSI_CR1_MCOM_11BIT	  (0xA << SSI_CR1_MCOM_BIT) /* 11-bit command selected */

+  #define SSI_CR1_MCOM_12BIT	  (0xB << SSI_CR1_MCOM_BIT) /* 12-bit command selected */

+  #define SSI_CR1_MCOM_13BIT	  (0xC << SSI_CR1_MCOM_BIT) /* 13-bit command selected */

+  #define SSI_CR1_MCOM_14BIT	  (0xD << SSI_CR1_MCOM_BIT) /* 14-bit command selected */

+  #define SSI_CR1_MCOM_15BIT	  (0xE << SSI_CR1_MCOM_BIT) /* 15-bit command selected */

+  #define SSI_CR1_MCOM_16BIT	  (0xF << SSI_CR1_MCOM_BIT) /* 16-bit command selected */

+#define SSI_CR1_RTRG_BIT	8 /* SSI RX trigger */

+#define SSI_CR1_RTRG_MASK	(0xf << SSI_CR1_RTRG_BIT)

+#define SSI_CR1_FLEN_BIT	4

+#define SSI_CR1_FLEN_MASK	(0xf << SSI_CR1_FLEN_BIT)

+  #define SSI_CR1_FLEN_2BIT	  (0x0 << SSI_CR1_FLEN_BIT)

+  #define SSI_CR1_FLEN_3BIT	  (0x1 << SSI_CR1_FLEN_BIT)

+  #define SSI_CR1_FLEN_4BIT	  (0x2 << SSI_CR1_FLEN_BIT)

+  #define SSI_CR1_FLEN_5BIT	  (0x3 << SSI_CR1_FLEN_BIT)

+  #define SSI_CR1_FLEN_6BIT	  (0x4 << SSI_CR1_FLEN_BIT)

+  #define SSI_CR1_FLEN_7BIT	  (0x5 << SSI_CR1_FLEN_BIT)

+  #define SSI_CR1_FLEN_8BIT	  (0x6 << SSI_CR1_FLEN_BIT)

+  #define SSI_CR1_FLEN_9BIT	  (0x7 << SSI_CR1_FLEN_BIT)

+  #define SSI_CR1_FLEN_10BIT	  (0x8 << SSI_CR1_FLEN_BIT)

+  #define SSI_CR1_FLEN_11BIT	  (0x9 << SSI_CR1_FLEN_BIT)

+  #define SSI_CR1_FLEN_12BIT	  (0xA << SSI_CR1_FLEN_BIT)

+  #define SSI_CR1_FLEN_13BIT	  (0xB << SSI_CR1_FLEN_BIT)

+  #define SSI_CR1_FLEN_14BIT	  (0xC << SSI_CR1_FLEN_BIT)

+  #define SSI_CR1_FLEN_15BIT	  (0xD << SSI_CR1_FLEN_BIT)

+  #define SSI_CR1_FLEN_16BIT	  (0xE << SSI_CR1_FLEN_BIT)

+  #define SSI_CR1_FLEN_17BIT	  (0xF << SSI_CR1_FLEN_BIT)

+#define SSI_CR1_PHA		(1 << 1)

+#define SSI_CR1_POL		(1 << 0)

+

+/* SSI Status Register (SSI_SR) */

+

+#define SSI_SR_TFIFONUM_BIT	16

+#define SSI_SR_TFIFONUM_MASK	(0xff << SSI_SR_TFIFONUM_BIT)

+#define SSI_SR_RFIFONUM_BIT	8

+#define SSI_SR_RFIFONUM_MASK	(0xff << SSI_SR_RFIFONUM_BIT)

+#define SSI_SR_END		(1 << 7)

+#define SSI_SR_BUSY		(1 << 6)

+#define SSI_SR_TFF		(1 << 5)

+#define SSI_SR_RFE		(1 << 4)

+#define SSI_SR_TFHE		(1 << 3)

+#define SSI_SR_RFHF		(1 << 2)

+#define SSI_SR_UNDR		(1 << 1)

+#define SSI_SR_OVER		(1 << 0)

+

+/* SSI Interval Time Control Register (SSI_ITR) */

+

+#define	SSI_ITR_CNTCLK		(1 << 15)

+#define SSI_ITR_IVLTM_BIT	0

+#define SSI_ITR_IVLTM_MASK	(0x7fff << SSI_ITR_IVLTM_BIT)

+

+

+#ifndef __MIPS_ASSEMBLER

+

+/***************************************************************************

+ * SSI (Synchronous Serial Interface)

+ ***************************************************************************/

+/* n = 0, 1 (SSI0, SSI1) */

+#define __ssi_enable(n) 	( REG_SSI_CR0(n) |= SSI_CR0_SSIE )

+#define __ssi_disable(n) 	( REG_SSI_CR0(n) &= ~SSI_CR0_SSIE )

+#define __ssi_select_ce(n) 	( REG_SSI_CR0(n) &= ~SSI_CR0_FSEL )

+

+#define __ssi_normal_mode(n) ( REG_SSI_ITR(n) &= ~SSI_ITR_IVLTM_MASK )

+

+#define __ssi_select_ce2(n) 		\

+do { 					\

+	REG_SSI_CR0(n) |= SSI_CR0_FSEL; 	\

+	REG_SSI_CR1(n) &= ~SSI_CR1_MULTS;	\

+} while (0)

+

+#define __ssi_select_gpc(n) 			\

+do { 						\

+	REG_SSI_CR0(n) &= ~SSI_CR0_FSEL;	\

+	REG_SSI_CR1(n) |= SSI_CR1_MULTS;	\

+} while (0)

+

+#define __ssi_underrun_auto_clear(n) 		\

+do { 						\

+	REG_SSI_CR0(n) |= SSI_CR0_EACLRUN; 	\

+} while (0)

+

+#define __ssi_underrun_clear_manually(n) 	\

+do { 						\

+	REG_SSI_CR0(n) &= ~SSI_CR0_EACLRUN; 	\

+} while (0)

+

+#define __ssi_enable_tx_intr(n)					\

+	( REG_SSI_CR0(n) |= SSI_CR0_TIE | SSI_CR0_TEIE )

+

+#define __ssi_disable_tx_intr(n)				\

+	( REG_SSI_CR0(n) &= ~(SSI_CR0_TIE | SSI_CR0_TEIE) )

+

+#define __ssi_enable_rx_intr(n)					\

+	( REG_SSI_CR0(n) |= SSI_CR0_RIE | SSI_CR0_REIE )

+

+#define __ssi_disable_rx_intr(n)				\

+	( REG_SSI_CR0(n) &= ~(SSI_CR0_RIE | SSI_CR0_REIE) )

+

+#define __ssi_enable_txfifo_half_empty_intr(n)  \

+	( REG_SSI_CR0(n) |= SSI_CR0_TIE )

+#define __ssi_disable_txfifo_half_empty_intr(n)	\

+	( REG_SSI_CR0(n) &= ~SSI_CR0_TIE )

+#define __ssi_enable_tx_error_intr(n)		\

+	( REG_SSI_CR0(n) |= SSI_CR0_TEIE )

+#define __ssi_disable_tx_error_intr(n)		\

+	( REG_SSI_CR0(n) &= ~SSI_CR0_TEIE )

+#define __ssi_enable_rxfifo_half_full_intr(n)	\

+	( REG_SSI_CR0(n) |= SSI_CR0_RIE )

+#define __ssi_disable_rxfifo_half_full_intr(n)  \

+	( REG_SSI_CR0(n) &= ~SSI_CR0_RIE )

+#define __ssi_enable_rx_error_intr(n)		\

+	( REG_SSI_CR0(n) |= SSI_CR0_REIE )

+#define __ssi_disable_rx_error_intr(n)		\

+	( REG_SSI_CR0(n) &= ~SSI_CR0_REIE )

+

+#define __ssi_enable_loopback(n)  ( REG_SSI_CR0(n) |= SSI_CR0_LOOP )

+#define __ssi_disable_loopback(n) ( REG_SSI_CR0(n) &= ~SSI_CR0_LOOP )

+

+#define __ssi_enable_receive(n)   ( REG_SSI_CR0(n) &= ~SSI_CR0_DISREV )

+#define __ssi_disable_receive(n)  ( REG_SSI_CR0(n) |= SSI_CR0_DISREV )

+

+#define __ssi_finish_receive(n)					\

+	( REG_SSI_CR0(n) |= (SSI_CR0_RFINE | SSI_CR0_RFINC) )

+

+#define __ssi_disable_recvfinish(n)				\

+	( REG_SSI_CR0(n) &= ~(SSI_CR0_RFINE | SSI_CR0_RFINC) )

+

+#define __ssi_flush_txfifo(n)   	( REG_SSI_CR0(n) |= SSI_CR0_TFLUSH )

+#define __ssi_flush_rxfifo(n)   	( REG_SSI_CR0(n) |= SSI_CR0_RFLUSH )

+

+#define __ssi_flush_fifo(n)					\

+	( REG_SSI_CR0(n) |= SSI_CR0_TFLUSH | SSI_CR0_RFLUSH )

+

+#define __ssi_finish_transmit(n) 	( REG_SSI_CR1(n) &= ~SSI_CR1_UNFIN )

+#define __ssi_wait_transmit(n) 		( REG_SSI_CR1(n) |= SSI_CR1_UNFIN )

+#define __ssi_use_busy_wait_mode(n) 	__ssi_wait_transmit(n)

+#define __ssi_unset_busy_wait_mode(n) 	__ssi_finish_transmit(n)

+

+#define __ssi_spi_format(n)						\

+	do {								\

+		REG_SSI_CR1(n) &= ~SSI_CR1_FMAT_MASK; 			\

+		REG_SSI_CR1(n) |= SSI_CR1_FMAT_SPI;			\

+		REG_SSI_CR1(n) &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK); \

+		REG_SSI_CR1(n) |= (SSI_CR1_TFVCK_1 | SSI_CR1_TCKFI_1);	\

+	} while (0)

+

+/* TI's SSP format, must clear SSI_CR1.UNFIN */

+#define __ssi_ssp_format(n)						\

+	do { 								\

+		REG_SSI_CR1(n) &= ~(SSI_CR1_FMAT_MASK | SSI_CR1_UNFIN);	\

+		REG_SSI_CR1(n) |= SSI_CR1_FMAT_SSP;			\

+	} while (0)

+

+/* National's Microwire format, must clear SSI_CR0.RFINE, and set max delay */

+#define __ssi_microwire_format(n)					\

+	do {								\

+		REG_SSI_CR1(n) &= ~SSI_CR1_FMAT_MASK; 			\

+		REG_SSI_CR1(n) |= SSI_CR1_FMAT_MW1;			\

+		REG_SSI_CR1(n) &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK); \

+		REG_SSI_CR1(n) |= (SSI_CR1_TFVCK_3 | SSI_CR1_TCKFI_3);	\

+		REG_SSI_CR0(n) &= ~SSI_CR0_RFINE;			\

+	} while (0)

+

+/* CE# level (FRMHL), CE# in interval time (ITFRM),

+   clock phase and polarity (PHA POL),

+   interval time (SSIITR), interval characters/frame (SSIICR) */

+

+/* frmhl,endian,mcom,flen,pha,pol MASK */

+#define SSICR1_MISC_MASK 					\

+	( SSI_CR1_FRMHL_MASK | SSI_CR1_LFST | SSI_CR1_MCOM_MASK	\

+	  | SSI_CR1_FLEN_MASK | SSI_CR1_PHA | SSI_CR1_POL )	

+

+#define __ssi_spi_set_misc(n,frmhl,endian,flen,mcom,pha,pol)		\

+	do {								\

+		REG_SSI_CR1(n) &= ~SSICR1_MISC_MASK;			\

+		REG_SSI_CR1(n) |= ((frmhl) << 30) | ((endian) << 25) | 	\

+			(((mcom) - 1) << 12) | (((flen) - 2) << 4) | 	\

+			((pha) << 1) | (pol); 				\

+	} while(0)

+

+/* Transfer with MSB or LSB first */

+#define __ssi_set_msb(n) ( REG_SSI_CR1(n) &= ~SSI_CR1_LFST )

+#define __ssi_set_lsb(n) ( REG_SSI_CR1(n) |= SSI_CR1_LFST )

+

+#define __ssi_set_frame_length(n, m)					\

+	REG_SSI_CR1(n) = (REG_SSI_CR1(n) & ~SSI_CR1_FLEN_MASK) | (((m) - 2) << 4) 

+

+/* m = 1 - 16 */

+#define __ssi_set_microwire_command_length(n,m)				\

+	( REG_SSI_CR1(n) = ((REG_SSI_CR1(n) & ~SSI_CR1_MCOM_MASK) | SSI_CR1_MCOM_##m##BIT) )

+

+/* Set the clock phase for SPI */

+#define __ssi_set_spi_clock_phase(n, m)					\

+	( REG_SSI_CR1(n) = ((REG_SSI_CR1(n) & ~SSI_CR1_PHA) | (((m)&0x1)<< 1)))

+

+/* Set the clock polarity for SPI */

+#define __ssi_set_spi_clock_polarity(n, p)				\

+	( REG_SSI_CR1(n) = ((REG_SSI_CR1(n) & ~SSI_CR1_POL) | ((p)&0x1)) )

+

+/* SSI tx trigger, m = i x 8 */

+#define __ssi_set_tx_trigger(n, m)				\

+	do {							\

+		REG_SSI_CR1(n) &= ~SSI_CR1_TTRG_MASK;		\

+		REG_SSI_CR1(n) |= ((m)/8)<<SSI_CR1_TTRG_BIT;	\

+	} while (0)

+

+/* SSI rx trigger, m = i x 8 */

+#define __ssi_set_rx_trigger(n, m)				\

+	do {							\

+		REG_SSI_CR1(n) &= ~SSI_CR1_RTRG_MASK;		\

+		REG_SSI_CR1(n) |= ((m)/8)<<SSI_CR1_RTRG_BIT;	\

+	} while (0)

+

+#define __ssi_get_txfifo_count(n)					\

+	( (REG_SSI_SR(n) & SSI_SR_TFIFONUM_MASK) >> SSI_SR_TFIFONUM_BIT )

+

+#define __ssi_get_rxfifo_count(n)					\

+	( (REG_SSI_SR(n) & SSI_SR_RFIFONUM_MASK) >> SSI_SR_RFIFONUM_BIT )

+

+#define __ssi_transfer_end(n)		( REG_SSI_SR(n) & SSI_SR_END )

+#define __ssi_is_busy(n)		( REG_SSI_SR(n) & SSI_SR_BUSY )

+

+#define __ssi_txfifo_full(n)		( REG_SSI_SR(n) & SSI_SR_TFF )

+#define __ssi_rxfifo_empty(n)		( REG_SSI_SR(n) & SSI_SR_RFE )

+#define __ssi_rxfifo_half_full(n)	( REG_SSI_SR(n) & SSI_SR_RFHF )

+#define __ssi_txfifo_half_empty(n)	( REG_SSI_SR(n) & SSI_SR_TFHE )

+#define __ssi_underrun(n)		( REG_SSI_SR(n) & SSI_SR_UNDR )

+#define __ssi_overrun(n)		( REG_SSI_SR(n) & SSI_SR_OVER )

+#define __ssi_clear_underrun(n)		( REG_SSI_SR(n) = ~SSI_SR_UNDR )

+#define __ssi_clear_overrun(n)		( REG_SSI_SR(n) = ~SSI_SR_OVER )

+#define __ssi_clear_errors(n)		( REG_SSI_SR(n) &= ~(SSI_SR_UNDR | SSI_SR_OVER) )

+

+#define __ssi_set_clk(n, dev_clk, ssi_clk)			\

+	( REG_SSI_GR(n) = (dev_clk) / (2*(ssi_clk)) - 1 )

+

+#define __ssi_receive_data(n) 		REG_SSI_DR(n)

+#define __ssi_transmit_data(n, v) 	(REG_SSI_DR(n) = (v))

+

+

+

+

+

+#endif /* __MIPS_ASSEMBLER */

+

+#endif /* __JZ4770SSI_H__ */

+

diff --git a/arch/mips/include/asm/mach-jz4770/jz4770tcu.h b/arch/mips/include/asm/mach-jz4770/jz4770tcu.h
new file mode 100644
index 00000000000..2930a1941f7
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4770/jz4770tcu.h
@@ -0,0 +1,427 @@
+/*

+ * linux/include/asm-mips/mach-jz4810/jz4810tcu.h

+ *

+ * JZ4810 tcu register definition.

+ *

+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

+ */

+

+#ifndef __JZ4770TCU_H__

+#define __JZ4770TCU_H__

+

+

+#define	TCU_BASE	0xB0002000

+

+

+/*************************************************************************

+ * TCU (Timer Counter Unit)

+ *************************************************************************/

+#define TCU_TSTR	(TCU_BASE + 0xF0) /* Timer Status Register,Only Used In Tcu2 Mode */

+#define TCU_TSTSR	(TCU_BASE + 0xF4) /* Timer Status Set Register */

+#define TCU_TSTCR	(TCU_BASE + 0xF8) /* Timer Status Clear Register */

+#define TCU_TSR		(TCU_BASE + 0x1C) /* Timer Stop Register */

+#define TCU_TSSR	(TCU_BASE + 0x2C) /* Timer Stop Set Register */

+#define TCU_TSCR	(TCU_BASE + 0x3C) /* Timer Stop Clear Register */

+#define TCU_TER		(TCU_BASE + 0x10) /* Timer Counter Enable Register */

+#define TCU_TESR	(TCU_BASE + 0x14) /* Timer Counter Enable Set Register */

+#define TCU_TECR	(TCU_BASE + 0x18) /* Timer Counter Enable Clear Register */

+#define TCU_TFR		(TCU_BASE + 0x20) /* Timer Flag Register */

+#define TCU_TFSR	(TCU_BASE + 0x24) /* Timer Flag Set Register */

+#define TCU_TFCR	(TCU_BASE + 0x28) /* Timer Flag Clear Register */

+#define TCU_TMR		(TCU_BASE + 0x30) /* Timer Mask Register */

+#define TCU_TMSR	(TCU_BASE + 0x34) /* Timer Mask Set Register */

+#define TCU_TMCR	(TCU_BASE + 0x38) /* Timer Mask Clear Register */

+

+#define TCU_TDFR0	(TCU_BASE + 0x40) /* Timer Data Full Register */

+#define TCU_TDHR0	(TCU_BASE + 0x44) /* Timer Data Half Register */

+#define TCU_TCNT0	(TCU_BASE + 0x48) /* Timer Counter Register */

+#define TCU_TCSR0	(TCU_BASE + 0x4C) /* Timer Control Register */

+#define TCU_TDFR1	(TCU_BASE + 0x50)

+#define TCU_TDHR1	(TCU_BASE + 0x54)

+#define TCU_TCNT1	(TCU_BASE + 0x58)

+#define TCU_TCSR1	(TCU_BASE + 0x5C)

+#define TCU_TDFR2	(TCU_BASE + 0x60)

+#define TCU_TDHR2	(TCU_BASE + 0x64)

+#define TCU_TCNT2	(TCU_BASE + 0x68)

+#define TCU_TCSR2	(TCU_BASE + 0x6C)

+#define TCU_TDFR3	(TCU_BASE + 0x70)

+#define TCU_TDHR3	(TCU_BASE + 0x74)

+#define TCU_TCNT3	(TCU_BASE + 0x78)

+#define TCU_TCSR3	(TCU_BASE + 0x7C)

+#define TCU_TDFR4	(TCU_BASE + 0x80)

+#define TCU_TDHR4	(TCU_BASE + 0x84)

+#define TCU_TCNT4	(TCU_BASE + 0x88)

+#define TCU_TCSR4	(TCU_BASE + 0x8C)

+#define TCU_TDFR5	(TCU_BASE + 0x90)

+#define TCU_TDHR5	(TCU_BASE + 0x94)

+#define TCU_TCNT5	(TCU_BASE + 0x98)

+#define TCU_TCSR5	(TCU_BASE + 0x9C)

+

+#define REG_TCU_TSTR	REG32(TCU_TSTR)

+#define REG_TCU_TSTSR	REG32(TCU_TSTSR)

+#define REG_TCU_TSTCR	REG32(TCU_TSTCR)

+#define REG_TCU_TSR	REG32(TCU_TSR)

+#define REG_TCU_TSSR	REG32(TCU_TSSR)

+#define REG_TCU_TSCR	REG32(TCU_TSCR)

+#define REG_TCU_TER	REG16(TCU_TER)

+#define REG_TCU_TESR	REG32(TCU_TESR)

+#define REG_TCU_TECR	REG32(TCU_TECR)

+#define REG_TCU_TFR	REG32(TCU_TFR)

+#define REG_TCU_TFSR	REG32(TCU_TFSR)

+#define REG_TCU_TFCR	REG32(TCU_TFCR)

+#define REG_TCU_TMR	REG32(TCU_TMR)

+#define REG_TCU_TMSR	REG32(TCU_TMSR)

+#define REG_TCU_TMCR	REG32(TCU_TMCR)

+#define REG_TCU_TDFR0	REG16(TCU_TDFR0)

+#define REG_TCU_TDHR0	REG16(TCU_TDHR0)

+#define REG_TCU_TCNT0	REG16(TCU_TCNT0)

+#define REG_TCU_TCSR0	REG16(TCU_TCSR0)

+#define REG_TCU_TDFR1	REG16(TCU_TDFR1)

+#define REG_TCU_TDHR1	REG16(TCU_TDHR1)

+#define REG_TCU_TCNT1	REG16(TCU_TCNT1)

+#define REG_TCU_TCSR1	REG16(TCU_TCSR1)

+#define REG_TCU_TDFR2	REG16(TCU_TDFR2)

+#define REG_TCU_TDHR2	REG16(TCU_TDHR2)

+#define REG_TCU_TCNT2	REG16(TCU_TCNT2)

+#define REG_TCU_TCSR2	REG16(TCU_TCSR2)

+#define REG_TCU_TDFR3	REG16(TCU_TDFR3)

+#define REG_TCU_TDHR3	REG16(TCU_TDHR3)

+#define REG_TCU_TCNT3	REG16(TCU_TCNT3)

+#define REG_TCU_TCSR3	REG16(TCU_TCSR3)

+#define REG_TCU_TDFR4	REG16(TCU_TDFR4)

+#define REG_TCU_TDHR4	REG16(TCU_TDHR4)

+#define REG_TCU_TCNT4	REG16(TCU_TCNT4)

+#define REG_TCU_TCSR4	REG16(TCU_TCSR4)

+

+// n = 0,1,2,3,4,5

+#define TCU_TDFR(n)	(TCU_BASE + (0x40 + (n)*0x10)) /* Timer Data Full Reg */

+#define TCU_TDHR(n)	(TCU_BASE + (0x44 + (n)*0x10)) /* Timer Data Half Reg */

+#define TCU_TCNT(n)	(TCU_BASE + (0x48 + (n)*0x10)) /* Timer Counter Reg */

+#define TCU_TCSR(n)	(TCU_BASE + (0x4C + (n)*0x10)) /* Timer Control Reg */

+#define TCU_OSTDR	(TCU_BASE + 0xe0) /* Operating System Timer Data Reg */

+#define TCU_OSTCNT	(TCU_BASE + 0xe4) /* Operating System Timer Counter Reg */

+#define TCU_OSTCSR	(TCU_BASE + 0xeC) /* Operating System Timer Control Reg */

+

+#define REG_TCU_TDFR(n)	REG16(TCU_TDFR((n)))

+#define REG_TCU_TDHR(n)	REG16(TCU_TDHR((n)))

+#define REG_TCU_TCNT(n)	REG16(TCU_TCNT((n)))

+#define REG_TCU_TCSR(n)	REG16(TCU_TCSR((n)))

+#define REG_TCU_OSTDR   REG32(TCU_OSTDR)

+#define REG_TCU_OSTCNT  REG32(TCU_OSTCNT)

+#define REG_TCU_OSTCSR  REG32(TCU_OSTCSR)

+

+// Register definitions

+#define TCU_TSTR_REAL2		(1 << 18) /* only used in TCU2 mode */

+#define TCU_TSTR_REAL1		(1 << 17) /* only used in TCU2 mode */

+#define TCU_TSTR_BUSY2		(1 << 2)  /* only used in TCU2 mode */

+#define TCU_TSTR_BUSY1		(1 << 1)  /* only used in TCU2 mode */

+

+#define TCU_TSTSR_REAL2		(1 << 18)

+#define TCU_TSTSR_REAL1		(1 << 17)

+#define TCU_TSTSR_BUSY2		(1 << 2)

+#define TCU_TSTSR_BUSY1		(1 << 1)

+

+#define TCU_TSTCR_REAL2		(1 << 18)

+#define TCU_TSTCR_REAL1		(1 << 17)

+#define TCU_TSTCR_BUSY2		(1 << 2)

+#define TCU_TSTCR_BUSY1		(1 << 1)

+

+#define TCU_TSR_WDTS		(1 << 16) /*the clock supplies to wdt is stopped */

+#define TCU_TSR_OSTS		(1 << 15) /*the clock supplies to osts is stopped */

+#define TCU_TSR_STOP5		(1 << 5)  /*the clock supplies to timer5 is stopped */

+#define TCU_TSR_STOP4		(1 << 4)  /*the clock supplies to timer4 is stopped */

+#define TCU_TSR_STOP3		(1 << 3)  /*the clock supplies to timer3 is stopped */

+#define TCU_TSR_STOP2		(1 << 2)  /*the clock supplies to timer2 is stopped */

+#define TCU_TSR_STOP1		(1 << 1)  /*the clock supplies to timer1 is stopped */

+#define TCU_TSR_STOP0		(1 << 0)  /*the clock supplies to timer0 is stopped */

+

+#define TCU_TSSR_WDTSS		(1 << 16)

+#define TCU_TSSR_OSTSS		(1 << 15)

+#define TCU_TSSR_STPS5		(1 << 5)

+#define TCU_TSSR_STPS4		(1 << 4)

+#define TCU_TSSR_STPS3		(1 << 3)

+#define TCU_TSSR_STPS2		(1 << 2)

+#define TCU_TSSR_STPS1		(1 << 1)

+#define TCU_TSSR_STPS0		(1 << 0)

+

+#define TCU_TSCR_WDTSC		(1 << 16)

+#define TCU_TSCR_OSTSC		(1 << 15)

+#define TCU_TSCR_STPC5		(1 << 5)

+#define TCU_TSCR_STPC4		(1 << 4)

+#define TCU_TSCR_STPC3		(1 << 3)

+#define TCU_TSCR_STPC2		(1 << 2)

+#define TCU_TSCR_STPC1		(1 << 1)

+#define TCU_TSCR_STPC0		(1 << 0)

+

+#define TCU_TER_OSTEN		(1 << 15) /* enable the counter in ost */

+#define TCU_TER_TCEN5		(1 << 5)  /* enable the counter in timer5 */

+#define TCU_TER_TCEN4		(1 << 4)

+#define TCU_TER_TCEN3		(1 << 3)

+#define TCU_TER_TCEN2		(1 << 2)

+#define TCU_TER_TCEN1		(1 << 1)

+#define TCU_TER_TCEN0		(1 << 0)

+

+#define TCU_TESR_OSTST		(1 << 15)

+#define TCU_TESR_TCST5		(1 << 5)

+#define TCU_TESR_TCST4		(1 << 4)

+#define TCU_TESR_TCST3		(1 << 3)

+#define TCU_TESR_TCST2		(1 << 2)

+#define TCU_TESR_TCST1		(1 << 1)

+#define TCU_TESR_TCST0		(1 << 0)

+

+#define TCU_TECR_OSTCL		(1 << 15)

+#define TCU_TECR_TCCL5		(1 << 5)

+#define TCU_TECR_TCCL4		(1 << 4)

+#define TCU_TECR_TCCL3		(1 << 3)

+#define TCU_TECR_TCCL2		(1 << 2)

+#define TCU_TECR_TCCL1		(1 << 1)

+#define TCU_TECR_TCCL0		(1 << 0)

+

+#define TCU_TFR_HFLAG5		(1 << 21) /* half comparison match flag */

+#define TCU_TFR_HFLAG4		(1 << 20)

+#define TCU_TFR_HFLAG3		(1 << 19)

+#define TCU_TFR_HFLAG2		(1 << 18)

+#define TCU_TFR_HFLAG1		(1 << 17)

+#define TCU_TFR_HFLAG0		(1 << 16)

+#define TCU_TFR_OSTFLAG		(1 << 15) /* ost comparison match flag */

+#define TCU_TFR_FFLAG5		(1 << 5)  /* full comparison match flag */

+#define TCU_TFR_FFLAG4		(1 << 4)

+#define TCU_TFR_FFLAG3		(1 << 3)

+#define TCU_TFR_FFLAG2		(1 << 2)

+#define TCU_TFR_FFLAG1		(1 << 1)

+#define TCU_TFR_FFLAG0		(1 << 0)

+

+#define TCU_TFSR_HFST5		(1 << 21)

+#define TCU_TFSR_HFST4		(1 << 20)

+#define TCU_TFSR_HFST3		(1 << 19)

+#define TCU_TFSR_HFST2		(1 << 18)

+#define TCU_TFSR_HFST1		(1 << 17)

+#define TCU_TFSR_HFST0		(1 << 16)

+#define TCU_TFSR_OSTFST		(1 << 15)

+#define TCU_TFSR_FFST5		(1 << 5)

+#define TCU_TFSR_FFST4		(1 << 4)

+#define TCU_TFSR_FFST3		(1 << 3)

+#define TCU_TFSR_FFST2		(1 << 2)

+#define TCU_TFSR_FFST1		(1 << 1)

+#define TCU_TFSR_FFST0		(1 << 0)

+

+#define TCU_TFCR_HFCL5		(1 << 21)

+#define TCU_TFCR_HFCL4		(1 << 20)

+#define TCU_TFCR_HFCL3		(1 << 19)

+#define TCU_TFCR_HFCL2		(1 << 18)

+#define TCU_TFCR_HFCL1		(1 << 17)

+#define TCU_TFCR_HFCL0		(1 << 16)

+#define TCU_TFCR_OSTFCL		(1 << 15)

+#define TCU_TFCR_FFCL5		(1 << 5)

+#define TCU_TFCR_FFCL4		(1 << 4)

+#define TCU_TFCR_FFCL3		(1 << 3)

+#define TCU_TFCR_FFCL2		(1 << 2)

+#define TCU_TFCR_FFCL1		(1 << 1)

+#define TCU_TFCR_FFCL0		(1 << 0)

+

+#define TCU_TMR_HMASK5		(1 << 21) /* half comparison match interrupt mask */

+#define TCU_TMR_HMASK4		(1 << 20)

+#define TCU_TMR_HMASK3		(1 << 19)

+#define TCU_TMR_HMASK2		(1 << 18)

+#define TCU_TMR_HMASK1		(1 << 17)

+#define TCU_TMR_HMASK0		(1 << 16)

+#define TCU_TMR_OSTMASK		(1 << 15) /* ost comparison match interrupt mask */

+#define TCU_TMR_FMASK5		(1 << 5)  /* full comparison match interrupt mask */

+#define TCU_TMR_FMASK4		(1 << 4)

+#define TCU_TMR_FMASK3		(1 << 3)

+#define TCU_TMR_FMASK2		(1 << 2)

+#define TCU_TMR_FMASK1		(1 << 1)

+#define TCU_TMR_FMASK0		(1 << 0)

+

+#define TCU_TMSR_HMST5		(1 << 21)

+#define TCU_TMSR_HMST4		(1 << 20)

+#define TCU_TMSR_HMST3		(1 << 19)

+#define TCU_TMSR_HMST2		(1 << 18)

+#define TCU_TMSR_HMST1		(1 << 17)

+#define TCU_TMSR_HMST0		(1 << 16)

+#define TCU_TMSR_OSTMST		(1 << 15)

+#define TCU_TMSR_FMST5		(1 << 5)

+#define TCU_TMSR_FMST4		(1 << 4)

+#define TCU_TMSR_FMST3		(1 << 3)

+#define TCU_TMSR_FMST2		(1 << 2)

+#define TCU_TMSR_FMST1		(1 << 1)

+#define TCU_TMSR_FMST0		(1 << 0)

+

+#define TCU_TMCR_HMCL5		(1 << 21)

+#define TCU_TMCR_HMCL4		(1 << 20)

+#define TCU_TMCR_HMCL3		(1 << 19)

+#define TCU_TMCR_HMCL2		(1 << 18)

+#define TCU_TMCR_HMCL1		(1 << 17)

+#define TCU_TMCR_HMCL0		(1 << 16)

+#define TCU_TMCR_OSTMCL		(1 << 15)

+#define TCU_TMCR_FMCL5		(1 << 5)

+#define TCU_TMCR_FMCL4		(1 << 4)

+#define TCU_TMCR_FMCL3		(1 << 3)

+#define TCU_TMCR_FMCL2		(1 << 2)

+#define TCU_TMCR_FMCL1		(1 << 1)

+#define TCU_TMCR_FMCL0		(1 << 0)

+

+#define TCU_TCSR_CNT_CLRZ	(1 << 10) /* clear counter to 0, only used in TCU2 mode */

+#define TCU_TCSR_PWM_SD		(1 << 9)  /* shut down the pwm output only used in TCU1 mode */

+#define TCU_TCSR_PWM_INITL_HIGH	(1 << 8)  /* selects an initial output level for pwm output */

+#define TCU_TCSR_PWM_EN		(1 << 7)  /* pwm pin output enable */

+#define TCU_TCSR_PRESCALE_BIT	3         /* select the tcnt count clock frequency*/

+#define TCU_TCSR_PRESCALE_MASK	(0x7 << TCU_TCSR_PRESCALE_BIT)

+  #define TCU_TCSR_PRESCALE1	(0x0 << TCU_TCSR_PRESCALE_BIT)

+  #define TCU_TCSR_PRESCALE4	(0x1 << TCU_TCSR_PRESCALE_BIT)

+  #define TCU_TCSR_PRESCALE16	(0x2 << TCU_TCSR_PRESCALE_BIT)

+  #define TCU_TCSR_PRESCALE64	(0x3 << TCU_TCSR_PRESCALE_BIT)

+  #define TCU_TCSR_PRESCALE256	(0x4 << TCU_TCSR_PRESCALE_BIT)

+  #define TCU_TCSR_PRESCALE1024	(0x5 << TCU_TCSR_PRESCALE_BIT)

+#define TCU_TCSR_EXT_EN		(1 << 2)  /* select extal as the timer clock input */

+#define TCU_TCSR_RTC_EN		(1 << 1)  /* select rtcclk as the timer clock input */

+#define TCU_TCSR_PCK_EN		(1 << 0)  /* select pclk as the timer clock input */

+

+#define TCU_TSTR_REAL2		(1 << 18) /* the value read from counter 2 is a real value */

+#define TCU_TSTR_REAL1		(1 << 17)

+#define TCU_TSTR_BUSY2		(1 << 2)  /* the counter 2 is busy now */

+#define TCU_TSTR_BUSY1		(1 << 1)

+

+#define TCU_TSTSR_REALS2	(1 << 18)

+#define TCU_TSTSR_REALS1	(1 << 17)

+#define TCU_TSTSR_BUSYS2	(1 << 2)

+#define TCU_TSTSR_BUSYS1	(1 << 1)

+

+#define TCU_TSTCR_REALC2	(1 << 18)

+#define TCU_TSTCR_REALC1	(1 << 17)

+#define TCU_TSTCR_BUSYC2	(1 << 2)

+#define TCU_TSTCR_BUSYC1	(1 << 1)

+

+#define TCU_OSTCR_CNT_MD		(1 << 15) /* when the value counter is equal to compare value,the counter is go on increasing till overflow,and then icrease from 0 */

+#define TCU_OSTCR_PWM_SD		(1 << 9) /* shut down the pwm output, only used in TCU1 mode */

+#define TCU_OSTCSR_PRESCALE_BIT		3

+#define TCU_OSTCSR_PRESCALE_MASK	(0x7 << TCU_OSTCSR_PRESCALE_BIT)

+  #define TCU_OSTCSR_PRESCALE1		(0x0 << TCU_OSTCSR_PRESCALE_BIT)

+  #define TCU_OSTCSR_PRESCALE4		(0x1 << TCU_OSTCSR_PRESCALE_BIT)

+  #define TCU_OSTCSR_PRESCALE16		(0x2 << TCU_OSTCSR_PRESCALE_BIT)

+  #define TCU_OSTCSR_PRESCALE64		(0x3 << TCU_OSTCSR_PRESCALE_BIT)

+  #define TCU_OSTCSR_PRESCALE256	(0x4 << TCU_OSTCSR_PRESCALE_BIT)

+  #define TCU_OSTCSR_PRESCALE1024	(0x5 << TCU_OSTCSR_PRESCALE_BIT)

+#define TCU_OSTCSR_EXT_EN		(1 << 2) /* select extal as the timer clock input */

+#define TCU_OSTCSR_RTC_EN		(1 << 1) /* select rtcclk as the timer clock input */

+#define TCU_OSTCSR_PCK_EN		(1 << 0) /* select pclk as the timer clock input */

+

+

+#ifndef __MIPS_ASSEMBLER

+

+/***************************************************************************

+ * TCU

+ ***************************************************************************/

+// where 'n' is the TCU channel

+#define __tcu_select_extalclk(n) \

+	(REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_EXT_EN)

+#define __tcu_select_rtcclk(n) \

+	(REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_RTC_EN)

+#define __tcu_select_pclk(n) \

+	(REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_PCK_EN)

+#define __tcu_disable_pclk(n) \

+	REG_TCU_TCSR(n) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PCK_EN);

+#define __tcu_select_clk_div1(n) \

+	(REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE1)

+#define __tcu_select_clk_div4(n) \

+	(REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE4)

+#define __tcu_select_clk_div16(n) \

+	(REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE16)

+#define __tcu_select_clk_div64(n) \

+	(REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE64)

+#define __tcu_select_clk_div256(n) \

+	(REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE256)

+#define __tcu_select_clk_div1024(n) \

+	(REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE1024)

+

+#define __tcu_enable_pwm_output(n)	(REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_EN)

+#define __tcu_disable_pwm_output(n)	(REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_EN)

+

+#define __tcu_init_pwm_output_high(n)	(REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_INITL_HIGH)

+#define __tcu_init_pwm_output_low(n)	(REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_INITL_HIGH)

+

+#define __tcu_set_pwm_output_shutdown_graceful(n)	(REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_SD)

+#define __tcu_set_pwm_output_shutdown_abrupt(n)		(REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_SD)

+

+#define __tcu_clear_counter_to_zero(n)	(REG_TCU_TCSR((n)) |= TCU_TCSR_CNT_CLRZ)

+

+#define __tcu_ost_enabled()		(REG_TCU_TER & TCU_TER_OSTEN)

+#define __tcu_enable_ost()		(REG_TCU_TESR = TCU_TESR_OSTST)

+#define __tcu_disable_ost()		(REG_TCU_TECR = TCU_TECR_OSTCL)

+

+#define __tcu_counter_enabled(n)	(REG_TCU_TER & (1 << (n)))

+#define __tcu_start_counter(n)		(REG_TCU_TESR |= (1 << (n)))

+#define __tcu_stop_counter(n)		(REG_TCU_TECR |= (1 << (n)))

+

+#define __tcu_half_match_flag(n)	(REG_TCU_TFR & (1 << ((n) + 16)))

+#define __tcu_full_match_flag(n)	(REG_TCU_TFR & (1 << (n)))

+#define __tcu_set_half_match_flag(n)	(REG_TCU_TFSR = (1 << ((n) + 16)))

+#define __tcu_set_full_match_flag(n)	(REG_TCU_TFSR = (1 << (n)))

+#define __tcu_clear_half_match_flag(n)	(REG_TCU_TFCR = (1 << ((n) + 16)))

+#define __tcu_clear_full_match_flag(n)	(REG_TCU_TFCR = (1 << (n)))

+#define __tcu_mask_half_match_irq(n)	(REG_TCU_TMSR = (1 << ((n) + 16)))

+#define __tcu_mask_full_match_irq(n)	(REG_TCU_TMSR = (1 << (n)))

+#define __tcu_unmask_half_match_irq(n)	(REG_TCU_TMCR = (1 << ((n) + 16)))

+#define __tcu_unmask_full_match_irq(n)	(REG_TCU_TMCR = (1 << (n)))

+

+#define __tcu_ost_match_flag()		(REG_TCU_TFR & TCU_TFR_OSTFLAG)

+#define __tcu_set_ost_match_flag()	(REG_TCU_TFSR = TCU_TFSR_OSTFST)

+#define __tcu_clear_ost_match_flag()	(REG_TCU_TFCR = TCU_TFCR_OSTFCL)

+#define __tcu_ost_match_irq_masked()	(REG_TCU_TMR & TCU_TMR_OSTMASK)

+#define __tcu_mask_ost_match_irq()	(REG_TCU_TMSR = TCU_TMSR_OSTMST)

+#define __tcu_unmask_ost_match_irq()	(REG_TCU_TMCR = TCU_TMCR_OSTMCL)

+

+#define __tcu_wdt_clock_stopped()	(REG_TCU_TSR & TCU_TSSR_WDTSC)

+#define __tcu_ost_clock_stopped()	(REG_TCU_TSR & TCU_TSR_OST)

+#define __tcu_timer_clock_stopped(n)	(REG_TCU_TSR & (1 << (n)))

+

+#define __tcu_start_wdt_clock()		(REG_TCU_TSCR = TCU_TSSR_WDTSC)

+#define __tcu_start_ost_clock()		(REG_TCU_TSCR = TCU_TSCR_OSTSC)

+#define __tcu_start_timer_clock(n)	(REG_TCU_TSCR = (1 << (n)))

+

+#define __tcu_stop_wdt_clock()		(REG_TCU_TSSR = TCU_TSSR_WDTSC)

+#define __tcu_stop_ost_clock()		(REG_TCU_TSSR = TCU_TSSR_OSTSS)

+#define __tcu_stop_timer_clock(n)	(REG_TCU_TSSR = (1 << (n)))

+

+#define __tcu_get_count(n)		(REG_TCU_TCNT((n)))

+#define __tcu_set_count(n,v)		(REG_TCU_TCNT((n)) = (v))

+#define __tcu_set_full_data(n,v)	(REG_TCU_TDFR((n)) = (v))

+#define __tcu_set_half_data(n,v)	(REG_TCU_TDHR((n)) = (v))

+

+/* TCU2, counter 1, 2*/

+#define __tcu_read_real_value(n)	(REG_TCU_TSTR & (1 << ((n) + 16)))

+#define __tcu_read_false_value(n)	(REG_TCU_TSTR & (1 << ((n) + 16)))

+#define __tcu_counter_busy(n)		(REG_TCU_TSTR & (1 << (n)))

+#define __tcu_counter_ready(n)		(REG_TCU_TSTR & (1 << (n)))

+

+#define __tcu_set_read_real_value(n)	(REG_TCU_TSTSR = (1 << ((n) + 16)))

+#define __tcu_set_read_false_value(n)	(REG_TCU_TSTCR = (1 << ((n) + 16)))

+#define __tcu_set_counter_busy(n)	(REG_TCU_TSTSR = (1 << (n)))

+#define __tcu_set_counter_ready(n)	(REG_TCU_TSTCR = (1 << (n)))

+

+/* ost counter */

+#define __ostcu_set_pwm_output_shutdown_graceful()	(REG_TCU_OSTCSR &= ~TCU_TCSR_PWM_SD)

+#define __ostcu_set_ost_output_shutdown_abrupt()	(REG_TCU_OSTCSR |= TCU_TCSR_PWM_SD)

+#define __ostcu_select_clk_div1() \

+	(REG_TCU_OSTCSR = (REG_TCU_OSTCSR & ~TCU_OSTCSR_PRESCALE_MASK) | TCU_OSTCSR_PRESCALE1)

+#define __ostcu_select_clk_div4() \

+	(REG_TCU_OSTCSR = (REG_TCU_OSTCSR & ~TCU_OSTCSR_PRESCALE_MASK) | TCU_OSTCSR_PRESCALE4)

+#define __ostcu_select_clk_div16() \

+	(REG_TCU_OSTCSR = (REG_TCU_OSTCSR & ~TCU_OSTCSR_PRESCALE_MASK) | TCU_OSTCSR_PRESCALE16)

+#define __ostcu_select_clk_div64() \

+	(REG_TCU_OSTCSR = (REG_TCU_OSTCSR & ~TCU_OSTCSR_PRESCALE_MASK) | TCU_OSTCSR_PRESCALE64)

+#define __ostcu_select_clk_div256() \

+	(REG_TCU_OSTCSR = (REG_TCU_OSTCSR & ~TCU_OSTCSR_PRESCALE_MASK) | TCU_OSTCSR_PRESCALE256)

+#define __ostcu_select_clk_div1024() \

+	(REG_TCU_OSTCSR = (REG_TCU_OSTCSR & ~TCU_OSTCSR_PRESCALE_MASK) | TCU_OSTCSR_PRESCALE1024)

+#define __ostcu_select_rtcclk() \

+	(REG_TCU_OSTCSR = (REG_TCU_OSTCSR & ~(TCU_OSTCSR_EXT_EN | TCU_OSTCSR_RTC_EN | TCU_OSTCSR_PCK_EN)) | TCU_OSTCSR_RTC_EN)

+#define __ostcu_select_extalclk() \

+	(REG_TCU_OSTCSR = (REG_TCU_OSTCSR & ~(TCU_OSTCSR_EXT_EN | TCU_OSTCSR_RTC_EN | TCU_OSTCSR_PCK_EN)) | TCU_OSTCSR_EXT_EN)

+#define __ostcu_select_pclk() \

+	(REG_TCU_OSTCSR = (REG_TCU_OSTCSR & ~(TCU_OSTCSR_EXT_EN | TCU_OSTCSR_RTC_EN | TCU_OSTCSR_PCK_EN)) | TCU_OSTCSR_PCK_EN)

+

+#endif /* __MIPS_ASSEMBLER */

+

+#endif /* __JZ4770TCU_H__ */

+

diff --git a/arch/mips/include/asm/mach-jz4770/jz4770tssi.h b/arch/mips/include/asm/mach-jz4770/jz4770tssi.h
new file mode 100644
index 00000000000..b24e24663a0
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4770/jz4770tssi.h
@@ -0,0 +1,342 @@
+/*

+ * linux/include/asm-mips/mach-jz4810/jz4810tssi.h

+ *

+ * JZ4810 TSSI register definition.

+ *

+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

+ */

+

+#ifndef __JZ4770TSSI_H__

+#define __JZ4770TSSI_H__

+

+

+#define	TSSI0_BASE	0xB34E0000

+

+/*************************************************************************

+ * TSSI MPEG 2-TS slave interface

+ *************************************************************************/

+#define TSSI_ENA       ( TSSI0_BASE + 0x00 )   /* TSSI enable register */

+#define TSSI_CFG       ( TSSI0_BASE + 0x04 )   /* TSSI configure register */

+#define TSSI_CTRL      ( TSSI0_BASE + 0x08 )   /* TSSI control register */

+#define TSSI_STAT      ( TSSI0_BASE + 0x0c )   /* TSSI state register */

+#define TSSI_FIFO      ( TSSI0_BASE + 0x10 )   /* TSSI FIFO register */

+#define TSSI_PEN       ( TSSI0_BASE + 0x14 )   /* TSSI PID enable register */

+#define TSSI_NUM       ( TSSI0_BASE + 0x18 )

+#define TSSI_DTR       ( TSSI0_BASE + 0x1c )

+#define TSSI_PID(n)    ( TSSI0_BASE + 0x20 + 4*(n) )   /* TSSI PID filter register */

+#define TSSI_PID0      ( TSSI0_BASE + 0x20 )

+#define TSSI_PID1      ( TSSI0_BASE + 0x24 )

+#define TSSI_PID2      ( TSSI0_BASE + 0x28 )

+#define TSSI_PID3      ( TSSI0_BASE + 0x2c )

+#define TSSI_PID4      ( TSSI0_BASE + 0x30 )

+#define TSSI_PID5      ( TSSI0_BASE + 0x34 )

+#define TSSI_PID6      ( TSSI0_BASE + 0x38 )

+#define TSSI_PID7      ( TSSI0_BASE + 0x3c )

+#define TSSI_PID8      ( TSSI0_BASE + 0x40 )

+#define TSSI_PID9      ( TSSI0_BASE + 0x44 )

+#define TSSI_PID10     ( TSSI0_BASE + 0x48 )

+#define TSSI_PID11     ( TSSI0_BASE + 0x4c )

+#define TSSI_PID12     ( TSSI0_BASE + 0x50 )

+#define TSSI_PID13     ( TSSI0_BASE + 0x54 )

+#define TSSI_PID14     ( TSSI0_BASE + 0x58 )

+#define TSSI_PID15     ( TSSI0_BASE + 0x5c )

+#define TSSI_PID_MAX   16	/* max PID: 15 */

+

+#define TSSI_DDA	( TSSI0_BASE + 0x60 )

+#define TSSI_DTA	( TSSI0_BASE + 0x64 )

+#define TSSI_DID	( TSSI0_BASE + 0x68 )

+#define TSSI_DCMD	( TSSI0_BASE + 0x6c )

+#define TSSI_DST	( TSSI0_BASE + 0x70 )

+#define TSSI_TC		( TSSI0_BASE + 0x74 )

+ 

+#define REG_TSSI_ENA       REG8( TSSI_ENA )

+#define REG_TSSI_CFG       REG32( TSSI_CFG )

+#define REG_TSSI_CTRL      REG8( TSSI_CTRL )

+#define REG_TSSI_STAT      REG8( TSSI_STAT )

+#define REG_TSSI_FIFO      REG32( TSSI_FIFO )

+#define REG_TSSI_PEN       REG32( TSSI_PEN )

+#define REG_TSSI_NUM       REG32( TSSI_NUM )

+#define REG_TSSI_DTR       REG32( TSSI_DTR )

+#define REG_TSSI_PID(n)    REG32( TSSI_PID(n) )

+#define REG_TSSI_PID0      REG32( TSSI_PID0 )

+#define REG_TSSI_PID1      REG32( TSSI_PID1 )

+#define REG_TSSI_PID2      REG32( TSSI_PID2 )

+#define REG_TSSI_PID3      REG32( TSSI_PID3 )

+#define REG_TSSI_PID4      REG32( TSSI_PID4 )

+#define REG_TSSI_PID5      REG32( TSSI_PID5 )

+#define REG_TSSI_PID6      REG32( TSSI_PID6 )

+#define REG_TSSI_PID7      REG32( TSSI_PID7 )

+#define REG_TSSI_PID8      REG32( TSSI_PID8 )

+#define REG_TSSI_PID9      REG32( TSSI_PID9 )

+#define REG_TSSI_PID10     REG32( TSSI_PID10 )

+#define REG_TSSI_PID11     REG32( TSSI_PID11 )

+#define REG_TSSI_PID12     REG32( TSSI_PID12 )

+#define REG_TSSI_PID13     REG32( TSSI_PID13 )

+#define REG_TSSI_PID14     REG32( TSSI_PID14 )

+#define REG_TSSI_PID15     REG32( TSSI_PID15 )

+

+#define REG_TSSI_DDA	REG32( TSSI_DDA )

+#define REG_TSSI_DTA	REG32( TSSI_DTA )

+#define REG_TSSI_DID	REG32( TSSI_DID )

+#define REG_TSSI_DCMD	REG32( TSSI_DCMD )

+#define REG_TSSI_DST	REG32( TSSI_DST )

+#define REG_TSSI_TC	REG32( TSSI_TC )

+

+/* TSSI enable register */

+#define TSSI_ENA_SFT_RST 	( 1 << 7 )      /* soft reset bit */

+#define TSSI_ENA_PID_EN 	( 1 << 2 )      /* soft filtering function enable bit */

+#define TSSI_ENA_FAIL		( 1 << 4 )	/* fail signal bit */

+#define TSSI_ENA_PEN_0		( 1 << 3 )	/* PID filter enable bit for PID */

+#define TSSI_ENA_DMA_EN 	( 1 << 1 )      /* DMA enable bit */

+#define TSSI_ENA_ENA 		( 1 << 0 )      /* TSSI enable bit */

+

+/* TSSI configure register */

+#define TSSI_CFG_TRIG_BIT 	14 /* fifo trig number */

+#define TSSI_CFG_TRIG_MASK 	( 0x7 << TSSI_CFG_TRIG_BIT)

+#define TSSI_CFG_TRIG_4 	( 0 << TSSI_CFG_TRIG_BIT)

+#define TSSI_CFG_TRIG_8 	( 1 << TSSI_CFG_TRIG_BIT)

+#define TSSI_CFG_TRIG_16 	( 2 << TSSI_CFG_TRIG_BIT)

+#define TSSI_CFG_TRIG_32 	( 3 << TSSI_CFG_TRIG_BIT)

+#define TSSI_CFG_TRIG_48 	( 4 << TSSI_CFG_TRIG_BIT)

+#define TSSI_CFG_TRIG_64 	( 5 << TSSI_CFG_TRIG_BIT)

+#define TSSI_CFG_TRIG_80 	( 6 << TSSI_CFG_TRIG_BIT)

+#define TSSI_CFG_TRIG_96 	( 7 << TSSI_CFG_TRIG_BIT)

+

+/* mode of adding data 0 select bit */

+#define TSSI_CFG_TRANS_MD_BIT	10

+#define TSSI_CFG_TRANS_MD_MASK	( 0x7 << TSSI_CFG_TRANS_MD_BIT)	

+#define TSSI_CFG_TRANS_MD_0	(0 << TSSI_CFG_TRANS_MD_BIT)

+#define TSSI_CFG_TRANS_MD_1	(1 << TSSI_CFG_TRANS_MD_BIT)

+#define TSSI_CFG_TRANS_MD_2	(2 << TSSI_CFG_TRANS_MD_BIT)

+

+#define TSSI_CFG_END_WD 	( 1 << 9 )      /* order of data in word */

+#define TSSI_CFG_END_BT 	( 1 << 8 )      /* order of data in byte */

+

+#define TSSI_CFG_TSDI_H 	( 1 << 7 )      /* data pin polarity */

+#define TSSI_CFG_USE_0 		( 1 << 6 )      /* serial mode data pin select */

+#define TSSI_CFG_USE_TSDI0 	( 1 << 6 )      /* TSDI0 as serial mode data pin */

+#define TSSI_CFG_USE_TSDI7 	( 0 << 6 )      /* TSDI7 as serial mode data pin */

+#define TSSI_CFG_TSCLK_CH 	( 1 << 5 )      /* clk channel select */

+#define TSSI_CFG_PARAL 		( 1 << 4 )      /* mode select */

+#define TSSI_CFG_PARAL_MODE 	( 1 << 4 )      /* parallel select */

+#define TSSI_CFG_SERIAL_MODE 	( 0 << 4 )      /* serial select */

+#define TSSI_CFG_TSCLK_P 	( 1 << 3 )      /* clk edge select */

+#define TSSI_CFG_TSFRM_H 	( 1 << 2 )      /* TSFRM polarity select */

+#define TSSI_CFG_TSSTR_H 	( 1 << 1 )      /* TSSTR polarity select */

+#define TSSI_CFG_TSFAIL_H 	( 1 << 0 )      /* TSFAIL polarity select */

+

+/* TSSI control register */

+#define TSSI_CTRL_DTRM		( 1 << 2 ) 	/* FIFO data trigger interrupt mask bit */

+#define TSSI_CTRL_OVRNM 	( 1 << 1 )      /* FIFO overrun interrupt mask bit */

+#define TSSI_CTRL_TRIGM 	( 1 << 0 )      /* FIFO trigger interrupt mask bit */

+

+/* TSSI state register */

+#define TSSI_STAT_DTR		( 1 << 2 )	/* FIFO data trigger interrupt flag bit */

+#define TSSI_STAT_OVRN 		( 1 << 1 )      /* FIFO overrun interrupt flag bit */

+#define TSSI_STAT_TRIG 		( 1 << 0 )      /* FIFO trigger interrupt flag bit */

+

+/* TSSI PID enable register */

+#define TSSI_PEN_EN00 	( 1 << 0 )      /* enable PID n */

+#define TSSI_PEN_EN10 	( 1 << 1 )      

+#define TSSI_PEN_EN20 	( 1 << 2 )      

+#define TSSI_PEN_EN30 	( 1 << 3 )      

+#define TSSI_PEN_EN40 	( 1 << 4 )      

+#define TSSI_PEN_EN50 	( 1 << 5 )      

+#define TSSI_PEN_EN60 	( 1 << 6 )      

+#define TSSI_PEN_EN70 	( 1 << 7 )      

+#define TSSI_PEN_EN80 	( 1 << 8 )      

+#define TSSI_PEN_EN90 	( 1 << 9 )      

+#define TSSI_PEN_EN100 	( 1 << 10 )      

+#define TSSI_PEN_EN110 	( 1 << 11 )      

+#define TSSI_PEN_EN120 	( 1 << 12 )      

+#define TSSI_PEN_EN130 	( 1 << 13 )      

+#define TSSI_PEN_EN140 	( 1 << 14 )      

+#define TSSI_PEN_EN150 	( 1 << 15 )      

+#define TSSI_PEN_EN01 	( 1 << 16 )      

+#define TSSI_PEN_EN11 	( 1 << 17 )      

+#define TSSI_PEN_EN21 	( 1 << 18 )     

+#define TSSI_PEN_EN31 	( 1 << 19 )      

+#define TSSI_PEN_EN41 	( 1 << 20 )     

+#define TSSI_PEN_EN51 	( 1 << 21 )      

+#define TSSI_PEN_EN61 	( 1 << 22 )     

+#define TSSI_PEN_EN71 	( 1 << 23 )      

+#define TSSI_PEN_EN81 	( 1 << 24 )      

+#define TSSI_PEN_EN91 	( 1 << 25 )      

+#define TSSI_PEN_EN101 	( 1 << 26 )      

+#define TSSI_PEN_EN111 	( 1 << 27 )      

+#define TSSI_PEN_EN121 	( 1 << 28 )      

+#define TSSI_PEN_EN131 	( 1 << 29 )      

+#define TSSI_PEN_EN141 	( 1 << 30 )      

+#define TSSI_PEN_EN151 	( 1 << 31 )      

+//#define TSSI_PEN_PID0 	( 1 << 31 ) /* PID filter enable PID0 */

+

+/* TSSI Data Number Registers */

+#define TSSI_DNUM_BIT	0

+#define TSSI_DNUM_MASK	(0x7f << TSSI_DNUM_BIT)

+

+/* TSSI Data Trigger Register */

+#define TSSI_DTRG_BIT 	0

+#define TSSI_DTRG_MASK	(0x7f << TSSI_DTRG_BIT)

+

+

+/* TSSI PID Filter Registers */

+#define TSSI_PID_PID1_BIT 	16

+#define TSSI_PID_PID1_MASK 	(0x1fff<<TSSI_PID_PID1_BIT)

+#define TSSI_PID_PID0_BIT 	0

+#define TSSI_PID_PID0_MASK 	(0x1fff<<TSSI_PID_PID0_BIT)

+

+/* TSSI DMA Identifier Registers */

+#define TSSI_DMA_ID_BIT		0

+#define TSSI_DMA_ID_MASK	(0xffff << TSSI_DMA_ID_BIT)

+

+/* TSSI DMA Command Registers */

+#define TSSI_DCMD_TLEN_BIT	8

+#define TSSI_DCMD_TLEN_MASK	(0xff << TSSI_DCMD_TLEN_BIT)

+#define TSSI_DCMD_TEFE		(1 << 4)

+#define TSSI_DCMD_TSZ_BIT	2

+#define TSSI_DCMD_TSZ_MASK	(0x3 << TSSI_DCMD_TSZ_BIT)

+#define TSSI_DCMD_TSZ_4		(0 << TSSI_DCMD_TSZ_BIT)

+#define TSSI_DCMD_TSZ_8		(1 << TSSI_DCMD_TSZ_BIT)

+#define TSSI_DCMD_TSZ_16	(2 << TSSI_DCMD_TSZ_BIT)

+#define TSSI_DCMD_TSZ_32	(3 << TSSI_DCMD_TSZ_BIT)

+#define TSSI_DCMD_TEIE		(1 << 1)

+#define TSSI_DCMD_LINK		(1 << 0)

+

+/* TSSI DMA Status Registers */

+#define TSSI_DST_DID_BIT	16

+#define TSSI_DST_DID_MASK	(0xffff << TSSI_DST_DID_BIT)

+#define TSSI_DST_TEND		(1 << 0)

+

+/* TSSI Transfer Control Registers */

+#define TSSI_TC_OP_BIT		4

+#define TSSI_TC_OP_MASK		(0x3 << TSSI_TC_OP_BIT)

+//////////////////#define TSSI_TC_OP_0		( 

+#define TSSI_TC_OPE		(1 << 2)

+#define TSSI_TC_EME		(1 << 1)

+#define TSSI_TC_APM		(1 << 0)

+#ifndef __MIPS_ASSEMBLER

+

+/*************************************************************************

+ * TSSI MPEG 2-TS slave interface operation

+ *************************************************************************/

+#define __tssi_enable()                       ( REG_TSSI_ENA |= TSSI_ENA_ENA )

+#define __tssi_disable()                      ( REG_TSSI_ENA &= ~TSSI_ENA_ENA )

+#define __tssi_soft_reset()                   ( REG_TSSI_ENA |= TSSI_ENA_SFT_RST )

+#define __tssi_filter_enable_pid0()	      ( REG_TSSI_ENA |= TSSI_ENA_PEN_0 )

+#define __tssi_filter_disable_pid0()	      ( REG_TSSI_ENA &= ~TSSI_ENA_PEN_0 )

+#define __tssi_dma_enable()                   ( REG_TSSI_ENA |= TSSI_ENA_DMA_EN )

+#define __tssi_dma_disable()                  ( REG_TSSI_ENA &= ~TSSI_ENA_DMA_EN )

+#define __tssi_filter_enable()                ( REG_TSSI_ENA |= TSSI_ENA_PID_EN )

+#define __tssi_filter_disable()               ( REG_TSSI_ENA &= ~TSSI_ENA_PID_EN )

+

+/* n = 4, 8, 16 */

+#define __tssi_set_tigger_num(n)			\

+	do {						\

+		REG_TSSI_CFG &= ~TSSI_CFG_TRIG_MASK;	\

+		REG_TSSI_CFG |= TSSI_CFG_TRIG_##n;	\

+	} while (0)

+

+#define __tssi_set_wd_1()                     ( REG_TSSI_CFG |= TSSI_CFG_END_WD )

+#define __tssi_set_wd_0()                     ( REG_TSSI_CFG &= ~TSSI_CFG_END_WD )

+

+#define __tssi_set_bt_1()                     ( REG_TSSI_CFG |= TSSI_CFG_END_BD )

+#define __tssi_set_bt_0()                     ( REG_TSSI_CFG &= ~TSSI_CFG_END_BD )

+

+#define __tssi_set_data_pola_high()           ( REG_TSSI_CFG |= TSSI_CFG_TSDI_H )

+#define __tssi_set_data_pola_low()            ( REG_TSSI_CFG &= ~TSSI_CFG_TSDI_H )

+

+#define __tssi_set_data_use_data0()           ( REG_TSSI_CFG |= TSSI_CFG_USE_0 )

+#define __tssi_set_data_use_data7()           ( REG_TSSI_CFG &= ~TSSI_CFG_USE_0 )

+

+#define __tssi_select_clk_fast()              ( REG_TSSI_CFG &= ~TSSI_CFG_TSCLK_CH )

+#define __tssi_select_clk_slow()              ( REG_TSSI_CFG |= TSSI_CFG_TSCLK_CH )

+

+#define __tssi_select_serail_mode()           ( REG_TSSI_CFG &= ~TSSI_CFG_PARAL )

+#define __tssi_select_paral_mode()            ( REG_TSSI_CFG |= TSSI_CFG_PARAL )

+

+#define __tssi_select_clk_nega_edge()         ( REG_TSSI_CFG &= ~TSSI_CFG_TSCLK_P )

+#define __tssi_select_clk_posi_edge()         ( REG_TSSI_CFG |= TSSI_CFG_TSCLK_P )

+

+#define __tssi_select_frm_act_high()          ( REG_TSSI_CFG |= TSSI_CFG_TSFRM_H )

+#define __tssi_select_frm_act_low()           ( REG_TSSI_CFG &= ~TSSI_CFG_TSFRM_H )

+

+#define __tssi_select_str_act_high()          ( REG_TSSI_CFG |= TSSI_CFG_TSSTR_H )

+#define __tssi_select_str_act_low()           ( REG_TSSI_CFG &= ~TSSI_CFG_TSSTR_H )

+

+#define __tssi_select_fail_act_high()         ( REG_TSSI_CFG |= TSSI_CFG_TSFAIL_H )

+#define __tssi_select_fail_act_low()          ( REG_TSSI_CFG &= ~TSSI_CFG_TSFAIL_H )

+

+#define __tssi_enable_data_trigger_irq()      (REG_TSSI_CTRL &= ~TSSI_CTRL_DTRM)

+#define __tssi_disable_data_trigger_irq()     (REG_TSSI_CTRL |= TSSI_CTRL_DTRM)

+

+#define __tssi_enable_ovrn_irq()              ( REG_TSSI_CTRL &= ~TSSI_CTRL_OVRNM )

+#define __tssi_disable_ovrn_irq()             ( REG_TSSI_CTRL |= TSSI_CTRL_OVRNM )

+

+#define __tssi_enable_trig_irq()              ( REG_TSSI_CTRL &= ~TSSI_CTRL_TRIGM )

+#define __tssi_disable_trig_irq()             ( REG_TSSI_CTRL |= TSSI_CTRL_TRIGM ) 

+

+#define __tssi_enable_ctrl_irq()	      ( REG_TSSI_CTRL = 0)

+#define __tssi_disable_ctrl_irq()	      ( REG_TSSI_CTRL = 7)

+

+#define __tssi_state_is_dtr()		      ( REG_TSSI_STAT & TSSI_STAT_DTR )

+#define __tssi_state_is_overrun()             ( REG_TSSI_STAT & TSSI_STAT_OVRN )

+#define __tssi_state_trigger_meet()           ( REG_TSSI_STAT & TSSI_STAT_TRIG )

+#define __tssi_clear_state()                  ( REG_TSSI_STAT = 0 ) /* write 0??? */

+#define __tssi_state_clear_overrun()          ( REG_TSSI_STAT = TSSI_STAT_OVRN )   //??????? xyma

+

+#define __tssi_clear_desc_end_flag()	      ( REG_TSSI_DST &= ~TSSI_DST_TEND )

+

+

+//#define __tssi_enable_filte_pid0()            ( REG_TSSI_PEN |= TSSI_PEN_PID0 )

+//#define __tssi_disable_filte_pid0()           ( REG_TSSI_PEN &= ~TSSI_PEN_PID0 )

+

+/* m = 0, ..., 31 */

+////////////////???????????????????????????????????????????????????????????

+

+#define __tssi_enable_pid_filter(m)				\

+	do {							\

+		int n = (m);					\

+		if ( n>=0 && n <(TSSI_PID_MAX*2) ) {		\

+			REG_TSSI_PEN |= ( 1 << n );		\

+		}						\

+	} while (0)

+

+/* m = 0, ..., 31 */

+#define __tssi_disable_pid_filter(m)				       \

+	do {							       \

+		int n = (m);					       \

+		if ( n>=0 && n <(TSSI_PID_MAX*2) ) {		       \

+			REG_TSSI_PEN &= ~( 1 << n );		       \

+		}						       \

+	} while (0)

+

+/* n = 0, ..., 15 */

+#define __tssi_set_pid0(n, pid0)					\

+	do {								\

+		REG_TSSI_PID(n) &= ~TSSI_PID_PID0_MASK;			\

+		REG_TSSI_PID(n) |= ((pid0)<<TSSI_PID_PID0_BIT)&TSSI_PID_PID0_MASK; \

+	}while (0)

+/* n = 0, ..., 15 */

+#define __tssi_set_pid1(n, pid1)					\

+	do {								\

+		REG_TSSI_PID(n) &= ~TSSI_PID_PID1_MASK;			\

+		REG_TSSI_PID(n) |= ((pid1)<<TSSI_PID_PID1_BIT)&TSSI_PID_PID1_MASK; \

+	}while (0)

+

+/* n = 0, ..., 15 */

+#define __tssi_set_pid(n, pid)						\

+	do {								\

+		if ( n>=0 && n < TSSI_PID_MAX*2) {			\

+			if ( n < TSSI_PID_MAX )				\

+				__tssi_set_pid0(n, pid);		\

+			else						\

+				__tssi_set_pid1(n-TSSI_PID_MAX, pid);	\

+		}							\

+	}while (0)

+

+

+

+#endif /* __MIPS_ASSEMBLER */

+

+#endif /* __JZ4770TSSI_H__ */

+

diff --git a/arch/mips/include/asm/mach-jz4770/jz4770tve.h b/arch/mips/include/asm/mach-jz4770/jz4770tve.h
new file mode 100644
index 00000000000..f71009098f5
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4770/jz4770tve.h
@@ -0,0 +1,396 @@
+ /*

+ * linux/include/asm-mips/mach-jz4810/jz4810tve.h

+ *

+ * JZ4810 TVE register definition.

+ *

+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

+ */

+

+#ifndef __JZ4770TVE_H__

+#define __JZ4770TVE_H__

+

+

+#define	TVE_BASE	0xB3050100 

+

+

+

+/*************************************************************************

+ * TVE (TV Encoder Controller)

+ *************************************************************************/

+#define TVE_CTRL	(TVE_BASE + 0x40) /* TV Encoder Control register */

+#define TVE_FRCFG	(TVE_BASE + 0x44) /* Frame configure register */

+#define TVE_SLCFG1	(TVE_BASE + 0x50) /* TV signal level configure register 1 */

+#define TVE_SLCFG2	(TVE_BASE + 0x54) /* TV signal level configure register 2*/

+#define TVE_SLCFG3	(TVE_BASE + 0x58) /* TV signal level configure register 3*/

+#define TVE_LTCFG1	(TVE_BASE + 0x60) /* Line timing configure register 1 */

+#define TVE_LTCFG2	(TVE_BASE + 0x64) /* Line timing configure register 2 */

+#define TVE_CFREQ	(TVE_BASE + 0x70) /* Chrominance sub-carrier frequency configure register */

+#define TVE_CPHASE	(TVE_BASE + 0x74) /* Chrominance sub-carrier phase configure register */

+#define TVE_CBCRCFG	(TVE_BASE + 0x78) /* Chrominance filter configure register */

+#define TVE_WSSCR	(TVE_BASE + 0x80) /* Wide screen signal control register */

+#define TVE_WSSCFG1	(TVE_BASE + 0x84) /* Wide screen signal configure register 1 */

+#define TVE_WSSCFG2	(TVE_BASE + 0x88) /* Wide screen signal configure register 2 */

+#define TVE_WSSCFG3	(TVE_BASE + 0x8c) /* Wide screen signal configure register 3 */

+

+#define REG_TVE_CTRL     REG32(TVE_CTRL)

+#define REG_TVE_FRCFG    REG32(TVE_FRCFG)

+#define REG_TVE_SLCFG1   REG32(TVE_SLCFG1)

+#define REG_TVE_SLCFG2   REG32(TVE_SLCFG2)

+#define REG_TVE_SLCFG3   REG32(TVE_SLCFG3)

+#define REG_TVE_LTCFG1   REG32(TVE_LTCFG1)

+#define REG_TVE_LTCFG2   REG32(TVE_LTCFG2)

+#define REG_TVE_CFREQ    REG32(TVE_CFREQ)

+#define REG_TVE_CPHASE   REG32(TVE_CPHASE)

+#define REG_TVE_CBCRCFG	 REG32(TVE_CBCRCFG)

+#define REG_TVE_WSSCR    REG32(TVE_WSSCR)

+#define REG_TVE_WSSCFG1  REG32(TVE_WSSCFG1)

+#define REG_TVE_WSSCFG2	 REG32(TVE_WSSCFG2)

+#define REG_TVE_WSSCFG3  REG32(TVE_WSSCFG3)

+

+/* TV Encoder Control register */

+#define TVE_CTRL_EYCBCR         (1 << 25)    /* YCbCr_enable */

+#define TVE_CTRL_ECVBS          (1 << 24)    /* 1: cvbs_enable 0: s-video*/

+#define TVE_CTRL_DAPD3	        (1 << 23)    /* DAC 3 power down */

+#define TVE_CTRL_DAPD2	        (1 << 22)    /* DAC 2 power down */	

+#define TVE_CTRL_DAPD1	        (1 << 21)    /* DAC 1 power down */	

+#define TVE_CTRL_DAPD           (1 << 20)    /* power down all DACs */

+#define TVE_CTRL_YCDLY_BIT      16

+#define TVE_CTRL_YCDLY_MASK     (0x7 << TVE_CTRL_YCDLY_BIT)

+#define TVE_CTRL_CGAIN_BIT      14

+#define TVE_CTRL_CGAIN_MASK     (0x3 << TVE_CTRL_CGAIN_BIT)

+  #define TVE_CTRL_CGAIN_FULL		(0 << TVE_CTRL_CGAIN_BIT) /* gain = 1 */

+  #define TVE_CTRL_CGAIN_QUTR		(1 << TVE_CTRL_CGAIN_BIT) /* gain = 1/4 */

+  #define TVE_CTRL_CGAIN_HALF		(2 << TVE_CTRL_CGAIN_BIT) /* gain = 1/2 */

+  #define TVE_CTRL_CGAIN_THREE_QURT	(3 << TVE_CTRL_CGAIN_BIT) /* gain = 3/4 */

+#define TVE_CTRL_CBW_BIT        12

+#define TVE_CTRL_CBW_MASK       (0x3 << TVE_CTRL_CBW_BIT)

+  #define TVE_CTRL_CBW_NARROW	(0 << TVE_CTRL_CBW_BIT) /* Narrow band */

+  #define TVE_CTRL_CBW_WIDE	(1 << TVE_CTRL_CBW_BIT) /* Wide band */

+  #define TVE_CTRL_CBW_EXTRA	(2 << TVE_CTRL_CBW_BIT) /* Extra wide band */

+  #define TVE_CTRL_CBW_ULTRA	(3 << TVE_CTRL_CBW_BIT) /* Ultra wide band */

+#define TVE_CTRL_SYNCT          (1 << 9)

+#define TVE_CTRL_PAL            (1 << 8) /* 1: PAL, 0: NTSC */

+#define TVE_CTRL_FINV           (1 << 7) /* invert_top:1-invert top and bottom fields. */

+#define TVE_CTRL_ZBLACK         (1 << 6) /* bypass_yclamp:1-Black of luminance (Y) input is 0.*/

+#define TVE_CTRL_CR1ST          (1 << 5) /* uv_order:0-Cb before Cr,1-Cr before Cb */

+#define TVE_CTRL_CLBAR          (1 << 4) /* Color bar mode:0-Output input video to TV,1-Output color bar to TV */

+#define TVE_CTRL_SWRST          (1 << 0) /* Software reset:1-TVE is reset */

+

+/* Signal level configure register 1 */

+#define TVE_SLCFG1_BLACKL_BIT   0

+#define TVE_SLCFG1_BLACKL_MASK  (0x3ff << TVE_SLCFG1_BLACKL_BIT)

+#define TVE_SLCFG1_WHITEL_BIT   16

+#define TVE_SLCFG1_WHITEL_MASK  (0x3ff << TVE_SLCFG1_WHITEL_BIT)

+

+/* Signal level configure register 2 */

+#define TVE_SLCFG2_BLANKL_BIT    0

+#define TVE_SLCFG2_BLANKL_MASK   (0x3ff << TVE_SLCFG2_BLANKL_BIT)

+#define TVE_SLCFG2_VBLANKL_BIT   16

+#define TVE_SLCFG2_VBLANKL_MASK  (0x3ff << TVE_SLCFG2_VBLANKL_BIT)

+

+/* Signal level configure register 3 */

+#define TVE_SLCFG3_SYNCL_BIT   0

+#define TVE_SLCFG3_SYNCL_MASK  (0xff << TVE_SLCFG3_SYNCL_BIT)

+

+/* Line timing configure register 1 */

+#define TVE_LTCFG1_BACKP_BIT   0

+#define TVE_LTCFG1_BACKP_MASK  (0x7f << TVE_LTCFG1_BACKP_BIT)

+#define TVE_LTCFG1_HSYNCW_BIT   8

+#define TVE_LTCFG1_HSYNCW_MASK  (0x7f << TVE_LTCFG1_HSYNCW_BIT)

+#define TVE_LTCFG1_FRONTP_BIT   16

+#define TVE_LTCFG1_FRONTP_MASK  (0x1f << TVE_LTCFG1_FRONTP_BIT)

+

+/* Line timing configure register 2 */

+#define TVE_LTCFG2_BURSTW_BIT    0

+#define TVE_LTCFG2_BURSTW_MASK   (0x3f << TVE_LTCFG2_BURSTW_BIT)

+#define TVE_LTCFG2_PREBW_BIT     8

+#define TVE_LTCFG2_PREBW_MASK    (0x1f << TVE_LTCFG2_PREBW_BIT)

+#define TVE_LTCFG2_ACTLIN_BIT    16

+#define TVE_LTCFG2_ACTLIN_MASK	(0x7ff << TVE_LTCFG2_ACTLIN_BIT)

+

+/* Chrominance sub-carrier phase configure register */

+#define TVE_CPHASE_CCRSTP_BIT    0

+#define TVE_CPHASE_CCRSTP_MASK   (0x3 << TVE_CPHASE_CCRSTP_BIT)

+  #define TVE_CPHASE_CCRSTP_8	(0 << TVE_CPHASE_CCRSTP_BIT) /* Every 8 field */

+  #define TVE_CPHASE_CCRSTP_4	(1 << TVE_CPHASE_CCRSTP_BIT) /* Every 4 field */

+  #define TVE_CPHASE_CCRSTP_2	(2 << TVE_CPHASE_CCRSTP_BIT) /* Every 2 lines */

+  #define TVE_CPHASE_CCRSTP_0	(3 << TVE_CPHASE_CCRSTP_BIT) /* Never */

+#define TVE_CPHASE_ACTPH_BIT     16

+#define TVE_CPHASE_ACTPH_MASK    (0xff << TVE_CPHASE_ACTPH_BIT)

+#define TVE_CPHASE_INITPH_BIT    24

+#define TVE_CPHASE_INITPH_MASK   (0xff << TVE_CPHASE_INITPH_BIT)

+

+/* Chrominance filter configure register */

+#define TVE_CBCRCFG_CRGAIN_BIT       0

+#define TVE_CBCRCFG_CRGAIN_MASK      (0xff << TVE_CBCRCFG_CRGAIN_BIT)

+#define TVE_CBCRCFG_CBGAIN_BIT       8

+#define TVE_CBCRCFG_CBGAIN_MASK      (0xff << TVE_CBCRCFG_CBGAIN_BIT)

+#define TVE_CBCRCFG_CRBA_BIT         16

+#define TVE_CBCRCFG_CRBA_MASK        (0xff << TVE_CBCRCFG_CRBA_BIT)

+#define TVE_CBCRCFG_CBBA_BIT         24

+#define TVE_CBCRCFG_CBBA_MASK        (0xff << TVE_CBCRCFG_CBBA_BIT)

+

+/* Frame configure register */

+#define TVE_FRCFG_NLINE_BIT          0

+#define TVE_FRCFG_NLINE_MASK         (0x3ff << TVE_FRCFG_NLINE_BIT)

+#define TVE_FRCFG_L1ST_BIT           16

+#define TVE_FRCFG_L1ST_MASK          (0xff << TVE_FRCFG_L1ST_BIT)

+

+/* Wide screen signal control register */

+#define TVE_WSSCR_EWSS0_BIT	0

+#define TVE_WSSCR_EWSS1_BIT	1

+#define TVE_WSSCR_WSSTP_BIT	2

+#define TVE_WSSCR_WSSCKBP_BIT	3

+#define TVE_WSSCR_WSSEDGE_BIT	4

+#define TVE_WSSCR_WSSEDGE_MASK	(0x7 << TVE_WSSCR_WSSEDGE_BIT)

+#define TVE_WSSCR_ENCH_BIT	8

+#define TVE_WSSCR_NCHW_BIT	9

+#define TVE_WSSCR_NCHFREQ_BIT	12

+#define TVE_WSSCR_NCHFREQ_MASK	(0x7 << TVE_WSSCR_NCHFREQ_BIT)

+

+

+#ifndef __MIPS_ASSEMBLER

+

+/*************************************************************************

+ * TVE (TV Encoder Controller) ops

+ *************************************************************************/

+/* TV Encoder Control register ops */

+#define __tve_soft_reset()		(REG_TVE_CTRL |= TVE_CTRL_SWRST)

+

+#define __tve_output_colorbar()		(REG_TVE_CTRL |= TVE_CTRL_CLBAR)

+#define __tve_output_video()		(REG_TVE_CTRL &= ~TVE_CTRL_CLBAR)

+

+#define __tve_input_cr_first()		(REG_TVE_CTRL |= TVE_CTRL_CR1ST)

+#define __tve_input_cb_first()		(REG_TVE_CTRL &= ~TVE_CTRL_CR1ST)

+

+#define __tve_set_0_as_black()		(REG_TVE_CTRL |= TVE_CTRL_ZBLACK)

+#define __tve_set_16_as_black()		(REG_TVE_CTRL &= ~TVE_CTRL_ZBLACK)

+

+#define __tve_ena_invert_top_bottom()	(REG_TVE_CTRL |= TVE_CTRL_FINV)

+#define __tve_dis_invert_top_bottom()	(REG_TVE_CTRL &= ~TVE_CTRL_FINV)

+

+#define __tve_set_pal_mode()		(REG_TVE_CTRL |= TVE_CTRL_PAL)

+#define __tve_set_ntsc_mode()		(REG_TVE_CTRL &= ~TVE_CTRL_PAL)

+

+#define __tve_set_pal_dura()		(REG_TVE_CTRL |= TVE_CTRL_SYNCT)

+#define __tve_set_ntsc_dura()		(REG_TVE_CTRL &= ~TVE_CTRL_SYNCT)

+

+/* n = 0 ~ 3 */

+#define __tve_set_c_bandwidth(n) \

+do {\

+	REG_TVE_CTRL &= ~TVE_CTRL_CBW_MASK;\

+	REG_TVE_CTRL |= (n) << TVE_CTRL_CBW_BIT;	\

+}while(0)

+

+/* n = 0 ~ 3 */

+#define __tve_set_c_gain(n) \

+do {\

+	REG_TVE_CTRL &= ~TVE_CTRL_CGAIN_MASK;\

+	(REG_TVE_CTRL |= (n) << TVE_CTRL_CGAIN_BIT;	\

+}while(0)

+

+/* n = 0 ~ 7 */

+#define __tve_set_yc_delay(n)				\

+do {							\

+	REG_TVE_CTRL &= ~TVE_CTRL_YCDLY_MASK		\

+	REG_TVE_CTRL |= ((n) << TVE_CTRL_YCDLY_BIT);	\

+} while(0)

+

+#define __tve_disable_all_dacs()	(REG_TVE_CTRL |= TVE_CTRL_DAPD)

+#define __tve_disable_dac1()		(REG_TVE_CTRL |= TVE_CTRL_DAPD1)

+#define __tve_enable_dac1()		(REG_TVE_CTRL &= ~TVE_CTRL_DAPD1)

+#define __tve_disable_dac2()		(REG_TVE_CTRL |= TVE_CTRL_DAPD2)

+#define __tve_enable_dac2()		(REG_TVE_CTRL &= ~TVE_CTRL_DAPD2)

+#define __tve_disable_dac3()		(REG_TVE_CTRL |= TVE_CTRL_DAPD3)

+#define __tve_enable_dac3()		(REG_TVE_CTRL &= ~TVE_CTRL_DAPD3)

+

+#define __tve_enable_svideo_fmt()	(REG_TVE_CTRL |= TVE_CTRL_ECVBS)

+#define __tve_enable_cvbs_fmt()		(REG_TVE_CTRL &= ~TVE_CTRL_ECVBS)

+

+/* TV Encoder Frame Configure register ops */

+/* n = 0 ~ 255 */

+#define __tve_set_first_video_line(n)		\

+do {\

+		REG_TVE_FRCFG &= ~TVE_FRCFG_L1ST_MASK;\

+		REG_TVE_FRCFG |= (n) << TVE_FRCFG_L1ST_BIT;\

+} while(0)

+/* n = 0 ~ 1023 */

+#define __tve_set_line_num_per_frm(n)		\

+do {\

+		REG_TVE_FRCFG &= ~TVE_FRCFG_NLINE_MASK;\

+		REG_TVE_CFG |= (n) << TVE_FRCFG_NLINE_BIT;\

+} while(0)

+#define __tve_get_video_line_num()\

+	(((REG_TVE_FRCFG & TVE_FRCFG_NLINE_MASK) >> TVE_FRCFG_NLINE_BIT) - 1 - 2 * ((REG_TVE_FRCFG & TVE_FRCFG_L1ST_MASK) >> TVE_FRCFG_L1ST_BIT))

+

+/* TV Encoder Signal Level Configure register ops */

+/* n = 0 ~ 1023 */

+#define __tve_set_white_level(n)		\

+do {\

+		REG_TVE_SLCFG1 &= ~TVE_SLCFG1_WHITEL_MASK;\

+		REG_TVE_SLCFG1 |= (n) << TVE_SLCFG1_WHITEL_BIT;\

+} while(0)

+/* n = 0 ~ 1023 */

+#define __tve_set_black_level(n)		\

+do {\

+		REG_TVE_SLCFG1 &= ~TVE_SLCFG1_BLACKL_MASK;\

+		REG_TVE_SLCFG1 |= (n) << TVE_SLCFG1_BLACKL_BIT;\

+} while(0)

+/* n = 0 ~ 1023 */

+#define __tve_set_blank_level(n)		\

+do {\

+		REG_TVE_SLCFG2 &= ~TVE_SLCFG2_BLANKL_MASK;\

+		REG_TVE_SLCFG2 |= (n) << TVE_SLCFG2_BLANKL_BIT;\

+} while(0)

+/* n = 0 ~ 1023 */

+#define __tve_set_vbi_blank_level(n)		\

+do {\

+		REG_TVE_SLCFG2 &= ~TVE_SLCFG2_VBLANKL_MASK;\

+		REG_TVE_SLCFG2 |= (n) << TVE_SLCFG2_VBLANKL_BIT;\

+} while(0)

+/* n = 0 ~ 1023 */

+#define __tve_set_sync_level(n)		\

+do {\

+		REG_TVE_SLCFG3 &= ~TVE_SLCFG3_SYNCL_MASK;\

+		REG_TVE_SLCFG3 |= (n) << TVE_SLCFG3_SYNCL_BIT;\

+} while(0)

+

+/* TV Encoder Signal Level Configure register ops */

+/* n = 0 ~ 31 */

+#define __tve_set_front_porch(n)		\

+do {\

+		REG_TVE_LTCFG1 &= ~TVE_LTCFG1_FRONTP_MASK;\

+		REG_TVE_LTCFG1 |= (n) << TVE_LTCFG1_FRONTP_BIT;	\

+} while(0)

+/* n = 0 ~ 127 */

+#define __tve_set_hsync_width(n)		\

+do {\

+		REG_TVE_LTCFG1 &= ~TVE_LTCFG1_HSYNCW_MASK;\

+		REG_TVE_LTCFG1 |= (n) << TVE_LTCFG1_HSYNCW_BIT;	\

+} while(0)

+/* n = 0 ~ 127 */

+#define __tve_set_back_porch(n)		\

+do {\

+		REG_TVE_LTCFG1 &= ~TVE_LTCFG1_BACKP_MASK;\

+		REG_TVE_LTCFG1 |= (n) << TVE_LTCFG1_BACKP_BIT;	\

+} while(0)

+/* n = 0 ~ 2047 */

+#define __tve_set_active_linec(n)		\

+do {\

+		REG_TVE_LTCFG2 &= ~TVE_LTCFG2_ACTLIN_MASK;\

+		REG_TVE_LTCFG2 |= (n) << TVE_LTCFG2_ACTLIN_BIT;	\

+} while(0)

+/* n = 0 ~ 31 */

+#define __tve_set_breezy_way(n)		\

+do {\

+		REG_TVE_LTCFG2 &= ~TVE_LTCFG2_PREBW_MASK;\

+		REG_TVE_LTCFG2 |= (n) << TVE_LTCFG2_PREBW_BIT;	\

+} while(0)

+

+/* n = 0 ~ 127 */

+#define __tve_set_burst_width(n)		\

+do {\

+		REG_TVE_LTCFG2 &= ~TVE_LTCFG2_BURSTW_MASK;\

+		REG_TVE_LTCFG2 |= (n) << TVE_LTCFG2_BURSTW_BIT;	\

+} while(0)

+

+/* TV Encoder Chrominance filter and Modulation register ops */

+/* n = 0 ~ (2^32-1) */

+#define __tve_set_c_sub_carrier_freq(n)  REG_TVE_CFREQ = (n)

+/* n = 0 ~ 255 */

+#define __tve_set_c_sub_carrier_init_phase(n) \

+do {   \

+	REG_TVE_CPHASE &= ~TVE_CPHASE_INITPH_MASK;	\

+	REG_TVE_CPHASE |= (n) << TVE_CPHASE_INITPH_BIT;	\

+} while(0)

+/* n = 0 ~ 255 */

+#define __tve_set_c_sub_carrier_act_phase(n) \

+do {   \

+	REG_TVE_CPHASE &= ~TVE_CPHASE_ACTPH_MASK;	\

+	REG_TVE_CPHASE |= (n) << TVE_CPHASE_ACTPH_BIT;	\

+} while(0)

+/* n = 0 ~ 255 */

+#define __tve_set_c_phase_rst_period(n) \

+do {   \

+	REG_TVE_CPHASE &= ~TVE_CPHASE_CCRSTP_MASK;	\

+	REG_TVE_CPHASE |= (n) << TVE_CPHASE_CCRSTP_BIT;	\

+} while(0)

+/* n = 0 ~ 255 */

+#define __tve_set_cb_burst_amp(n) \

+do {   \

+	REG_TVE_CBCRCFG &= ~TVE_CBCRCFG_CBBA_MASK;	\

+	REG_TVE_CBCRCFG |= (n) << TVE_CBCRCFG_CBBA_BIT;	\

+} while(0)

+/* n = 0 ~ 255 */

+#define __tve_set_cr_burst_amp(n) \

+do {   \

+	REG_TVE_CBCRCFG &= ~TVE_CBCRCFG_CRBA_MASK;	\

+	REG_TVE_CBCRCFG |= (n) << TVE_CBCRCFG_CRBA_BIT;	\

+} while(0)

+/* n = 0 ~ 255 */

+#define __tve_set_cb_gain_amp(n) \

+do {   \

+	REG_TVE_CBCRCFG &= ~TVE_CBCRCFG_CBGAIN_MASK;	\

+	REG_TVE_CBCRCFG |= (n) << TVE_CBCRCFG_CBGAIN_BIT;	\

+} while(0)

+/* n = 0 ~ 255 */

+#define __tve_set_cr_gain_amp(n) \

+do {   \

+	REG_TVE_CBCRCFG &= ~TVE_CBCRCFG_CRGAIN_MASK;	\

+	REG_TVE_CBCRCFG |= (n) << TVE_CBCRCFG_CRGAIN_BIT;	\

+} while(0)

+

+/* TV Encoder Wide Screen Signal Control register ops */

+/* n = 0 ~ 7 */

+#define __tve_set_notch_freq(n) \

+do {   \

+	REG_TVE_WSSCR &= ~TVE_WSSCR_NCHFREQ_MASK;	\

+	REG_TVE_WSSCR |= (n) << TVE_WSSCR_NCHFREQ_BIT;	\

+} while(0)

+/* n = 0 ~ 7 */

+#define __tve_set_notch_width()	(REG_TVE_WSSCR |= TVE_WSSCR_NCHW_BIT)

+#define __tve_clear_notch_width()	(REG_TVE_WSSCR &= ~TVE_WSSCR_NCHW_BIT)

+#define __tve_enable_notch()		(REG_TVE_WSSCR |= TVE_WSSCR_ENCH_BIT)

+#define __tve_disable_notch()		(REG_TVE_WSSCR &= ~TVE_WSSCR_ENCH_BIT)

+/* n = 0 ~ 7 */

+#define __tve_set_wss_edge(n) \

+do {   \

+	REG_TVE_WSSCR &= ~TVE_WSSCR_WSSEDGE_MASK;	\

+	REG_TVE_WSSCR |= (n) << TVE_WSSCR_WSSEDGE_BIT;	\

+} while(0)

+#define __tve_set_wss_clkbyp()		(REG_TVE_WSSCR |= TVE_WSSCR_WSSCKBP_BIT)

+#define __tve_set_wss_type()		(REG_TVE_WSSCR |= TVE_WSSCR_WSSTP_BIT)

+#define __tve_enable_wssf1()		(REG_TVE_WSSCR |= TVE_WSSCR_EWSS1_BIT)

+#define __tve_enable_wssf0()		(REG_TVE_WSSCR |= TVE_WSSCR_EWSS0_BIT)

+

+/* TV Encoder Wide Screen Signal Configure register 1, 2 and 3 ops */

+/* n = 0 ~ 1023 */

+#define __tve_set_wss_level(n) \

+do {   \

+	REG_TVE_WSSCFG1 &= ~TVE_WSSCFG1_WSSL_MASK;	\

+	REG_TVE_WSSCFG1 |= (n) << TVE_WSSCFG1_WSSL_BIT;	\

+} while(0)

+/* n = 0 ~ 4095 */

+#define __tve_set_wss_freq(n) \

+do {   \

+	REG_TVE_WSSCFG1 &= ~TVE_WSSCFG1_WSSFREQ_MASK;	\

+	REG_TVE_WSSCFG1 |= (n) << TVE_WSSCFG1_WSSFREQ_BIT;	\

+} while(0)

+/* n = 0, 1; l = 0 ~ 255 */

+#define __tve_set_wss_line(n,v)			\

+do {   \

+	REG_TVE_WSSCFG##n &= ~TVE_WSSCFG_WSSLINE_MASK;	\

+	REG_TVE_WSSCFG##n |= (v) << TVE_WSSCFG_WSSLINE_BIT;	\

+} while(0)

+/* n = 0, 1; d = 0 ~ (2^20-1) */

+#define __tve_set_wss_data(n, v)			\

+do {   \

+	REG_TVE_WSSCFG##n &= ~TVE_WSSCFG_WSSLINE_MASK;	\

+	REG_TVE_WSSCFG##n |= (v) << TVE_WSSCFG_WSSLINE_BIT;	\

+} while(0)

+

+

+#endif /* __MIPS_ASSEMBLER */

+

+#endif /* __JZ4770TVE_H__ */

+

diff --git a/arch/mips/include/asm/mach-jz4770/jz4770uart.h b/arch/mips/include/asm/mach-jz4770/jz4770uart.h
new file mode 100644
index 00000000000..51c9bb6f717
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4770/jz4770uart.h
@@ -0,0 +1,293 @@
+/*

+ * linux/include/asm-mips/mach-jz4810/jz4810uart.h

+ *

+ * JZ4810 UART register definition.

+ *

+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

+ */

+

+#ifndef __JZ4770UART_H__

+#define __JZ4770UART_H__

+

+

+#define	UART0_BASE	0xB0030000

+#define	UART1_BASE	0xB0031000

+#define	UART2_BASE	0xB0032000

+#define	UART3_BASE	0xB0033000

+

+/*************************************************************************

+ * UART

+ *************************************************************************/

+

+#define IRDA_BASE	UART0_BASE

+#define UART_BASE	UART0_BASE

+#define UART_OFF	0x1000

+

+/* Register Offset */

+#define OFF_RDR		(0x00)	/* R  8b H'xx */

+#define OFF_TDR		(0x00)	/* W  8b H'xx */

+#define OFF_DLLR	(0x00)	/* RW 8b H'00 */

+#define OFF_DLHR	(0x04)	/* RW 8b H'00 */

+#define OFF_IER		(0x04)	/* RW 8b H'00 */

+#define OFF_ISR		(0x08)	/* R  8b H'01 */

+#define OFF_FCR		(0x08)	/* W  8b H'00 */

+#define OFF_LCR		(0x0C)	/* RW 8b H'00 */

+#define OFF_MCR		(0x10)	/* RW 8b H'00 */

+#define OFF_LSR		(0x14)	/* R  8b H'00 */

+#define OFF_MSR		(0x18)	/* R  8b H'00 */

+#define OFF_SPR		(0x1C)	/* RW 8b H'00 */

+#define OFF_SIRCR	(0x20)	/* RW 8b H'00, UART0 */

+#define OFF_UMR		(0x24)	/* RW 8b H'00, UART M Register */

+#define OFF_UACR	(0x28)	/* RW 8b H'00, UART Add Cycle Register */

+

+/* Register Address */

+#define UART0_RDR	(UART0_BASE + OFF_RDR)

+#define UART0_TDR	(UART0_BASE + OFF_TDR)

+#define UART0_DLLR	(UART0_BASE + OFF_DLLR)

+#define UART0_DLHR	(UART0_BASE + OFF_DLHR)

+#define UART0_IER	(UART0_BASE + OFF_IER)

+#define UART0_ISR	(UART0_BASE + OFF_ISR)

+#define UART0_FCR	(UART0_BASE + OFF_FCR)

+#define UART0_LCR	(UART0_BASE + OFF_LCR)

+#define UART0_MCR	(UART0_BASE + OFF_MCR)

+#define UART0_LSR	(UART0_BASE + OFF_LSR)

+#define UART0_MSR	(UART0_BASE + OFF_MSR)

+#define UART0_SPR	(UART0_BASE + OFF_SPR)

+#define UART0_SIRCR	(UART0_BASE + OFF_SIRCR)

+#define UART0_UMR	(UART0_BASE + OFF_UMR)

+#define UART0_UACR	(UART0_BASE + OFF_UACR)

+

+#define UART1_RDR	(UART1_BASE + OFF_RDR)

+#define UART1_TDR	(UART1_BASE + OFF_TDR)

+#define UART1_DLLR	(UART1_BASE + OFF_DLLR)

+#define UART1_DLHR	(UART1_BASE + OFF_DLHR)

+#define UART1_IER	(UART1_BASE + OFF_IER)

+#define UART1_ISR	(UART1_BASE + OFF_ISR)

+#define UART1_FCR	(UART1_BASE + OFF_FCR)

+#define UART1_LCR	(UART1_BASE + OFF_LCR)

+#define UART1_MCR	(UART1_BASE + OFF_MCR)

+#define UART1_LSR	(UART1_BASE + OFF_LSR)

+#define UART1_MSR	(UART1_BASE + OFF_MSR)

+#define UART1_SPR	(UART1_BASE + OFF_SPR)

+#define UART1_SIRCR	(UART1_BASE + OFF_SIRCR)

+

+#define UART2_RDR	(UART2_BASE + OFF_RDR)

+#define UART2_TDR	(UART2_BASE + OFF_TDR)

+#define UART2_DLLR	(UART2_BASE + OFF_DLLR)

+#define UART2_DLHR	(UART2_BASE + OFF_DLHR)

+#define UART2_IER	(UART2_BASE + OFF_IER)

+#define UART2_ISR	(UART2_BASE + OFF_ISR)

+#define UART2_FCR	(UART2_BASE + OFF_FCR)

+#define UART2_LCR	(UART2_BASE + OFF_LCR)

+#define UART2_MCR	(UART2_BASE + OFF_MCR)

+#define UART2_LSR	(UART2_BASE + OFF_LSR)

+#define UART2_MSR	(UART2_BASE + OFF_MSR)

+#define UART2_SPR	(UART2_BASE + OFF_SPR)

+#define UART2_SIRCR	(UART2_BASE + OFF_SIRCR)

+

+#define UART3_RDR	(UART3_BASE + OFF_RDR)

+#define UART3_TDR	(UART3_BASE + OFF_TDR)

+#define UART3_DLLR	(UART3_BASE + OFF_DLLR)

+#define UART3_DLHR	(UART3_BASE + OFF_DLHR)

+#define UART3_IER	(UART3_BASE + OFF_IER)

+#define UART3_ISR	(UART3_BASE + OFF_ISR)

+#define UART3_FCR	(UART3_BASE + OFF_FCR)

+#define UART3_LCR	(UART3_BASE + OFF_LCR)

+#define UART3_MCR	(UART3_BASE + OFF_MCR)

+#define UART3_LSR	(UART3_BASE + OFF_LSR)

+#define UART3_MSR	(UART3_BASE + OFF_MSR)

+#define UART3_SPR	(UART3_BASE + OFF_SPR)

+#define UART3_SIRCR	(UART3_BASE + OFF_SIRCR)

+

+

+/*

+ * Define macros for UARTIER

+ * UART Interrupt Enable Register

+ */

+#define UARTIER_RIE	(1 << 0)	/* 0: receive fifo full interrupt disable */

+#define UARTIER_TIE	(1 << 1)	/* 0: transmit fifo empty interrupt disable */

+#define UARTIER_RLIE	(1 << 2)	/* 0: receive line status interrupt disable */

+#define UARTIER_MIE	(1 << 3)	/* 0: modem status interrupt disable */

+#define UARTIER_RTIE	(1 << 4)	/* 0: receive timeout interrupt disable */

+

+/*

+ * Define macros for UARTISR

+ * UART Interrupt Status Register

+ */

+#define UARTISR_IP	(1 << 0)	/* 0: interrupt is pending  1: no interrupt */

+#define UARTISR_IID	(7 << 1)	/* Source of Interrupt */

+#define UARTISR_IID_MSI		(0 << 1)  /* Modem status interrupt */

+#define UARTISR_IID_THRI	(1 << 1)  /* Transmitter holding register empty */

+#define UARTISR_IID_RDI		(2 << 1)  /* Receiver data interrupt */

+#define UARTISR_IID_RLSI	(3 << 1)  /* Receiver line status interrupt */

+#define UARTISR_IID_RTO		(6 << 1)  /* Receive timeout */

+#define UARTISR_FFMS		(3 << 6)  /* FIFO mode select, set when UARTFCR.FE is set to 1 */

+#define UARTISR_FFMS_NO_FIFO	(0 << 6)

+#define UARTISR_FFMS_FIFO_MODE	(3 << 6)

+

+/*

+ * Define macros for UARTFCR

+ * UART FIFO Control Register

+ */

+#define UARTFCR_FE	(1 << 0)	/* 0: non-FIFO mode  1: FIFO mode */

+#define UARTFCR_RFLS	(1 << 1)	/* write 1 to flush receive FIFO */

+#define UARTFCR_TFLS	(1 << 2)	/* write 1 to flush transmit FIFO */

+#define UARTFCR_DMS	(1 << 3)	/* 0: disable DMA mode */

+#define UARTFCR_UUE	(1 << 4)	/* 0: disable UART */

+#define UARTFCR_RTRG	(3 << 6)	/* Receive FIFO Data Trigger */

+#define UARTFCR_RTRG_1	(0 << 6)

+#define UARTFCR_RTRG_4	(1 << 6)

+#define UARTFCR_RTRG_8	(2 << 6)

+#define UARTFCR_RTRG_15	(3 << 6)

+

+/*

+ * Define macros for UARTLCR

+ * UART Line Control Register

+ */

+#define UARTLCR_WLEN	(3 << 0)	/* word length */

+#define UARTLCR_WLEN_5	(0 << 0)

+#define UARTLCR_WLEN_6	(1 << 0)

+#define UARTLCR_WLEN_7	(2 << 0)

+#define UARTLCR_WLEN_8	(3 << 0)

+#define UARTLCR_STOP	(1 << 2)	/* 0: 1 stop bit when word length is 5,6,7,8

+					   1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */

+#define UARTLCR_STOP1	(0 << 2)

+#define UARTLCR_STOP2	(1 << 2)

+#define UARTLCR_PE	(1 << 3)	/* 0: parity disable */

+#define UARTLCR_PROE	(1 << 4)	/* 0: even parity  1: odd parity */

+#define UARTLCR_SPAR	(1 << 5)	/* 0: sticky parity disable */

+#define UARTLCR_SBRK	(1 << 6)	/* write 0 normal, write 1 send break */

+#define UARTLCR_DLAB	(1 << 7)	/* 0: access UARTRDR/TDR/IER  1: access UARTDLLR/DLHR */

+

+/*

+ * Define macros for UARTLSR

+ * UART Line Status Register

+ */

+#define UARTLSR_DR	(1 << 0)	/* 0: receive FIFO is empty  1: receive data is ready */

+#define UARTLSR_ORER	(1 << 1)	/* 0: no overrun error */

+#define UARTLSR_PER	(1 << 2)	/* 0: no parity error */

+#define UARTLSR_FER	(1 << 3)	/* 0; no framing error */

+#define UARTLSR_BRK	(1 << 4)	/* 0: no break detected  1: receive a break signal */

+#define UARTLSR_TDRQ	(1 << 5)	/* 1: transmit FIFO half "empty" */

+#define UARTLSR_TEMT	(1 << 6)	/* 1: transmit FIFO and shift registers empty */

+#define UARTLSR_RFER	(1 << 7)	/* 0: no receive error  1: receive error in FIFO mode */

+

+/*

+ * Define macros for UARTMCR

+ * UART Modem Control Register

+ */

+#define UARTMCR_RTS	(1 << 1)	/* 0: RTS_ output high, 1: RTS_ output low */

+#define UARTMCR_LOOP	(1 << 4)	/* 0: normal  1: loopback mode */

+#define UARTMCR_FCM	(1 << 6)	/* 0: software  1: hardware */

+#define UARTMCR_MCE	(1 << 7)	/* 0: modem function is disable */

+

+/*

+ * Define macros for UARTMSR

+ * UART Modem Status Register

+ */

+#define UARTMSR_CCTS	(1 << 0)        /* 1: a change on CTS_ pin */

+#define UARTMSR_CTS	(1 << 4)	/* 0: CTS_ pin is high */

+

+/*

+ * Define macros for SIRCR

+ * Slow IrDA Control Register

+ */

+#define SIRCR_TSIRE	(1 << 0)  /* 0: transmitter is in UART mode  1: SIR mode */

+#define SIRCR_RSIRE	(1 << 1)  /* 0: receiver is in UART mode  1: SIR mode */

+#define SIRCR_TPWS	(1 << 2)  /* 0: transmit 0 pulse width is 3/16 of bit length

+					   1: 0 pulse width is 1.6us for 115.2Kbps */

+#define SIRCR_TDPL	(1 << 3)  /* 0: encoder generates a positive pulse for 0 */

+#define SIRCR_RDPL	(1 << 4)  /* 0: decoder interprets positive pulse as 0 */

+

+/*

+ * Define macros for UART_LSR

+ * UART Line Status Register

+ */

+#define UART_LSR_DR	(1 << 0)	/* 0: receive FIFO is empty  1: receive data is ready */

+#define UART_LSR_ORER	(1 << 1)	/* 0: no overrun error */

+#define UART_LSR_PER	(1 << 2)	/* 0: no parity error */

+#define UART_LSR_FER	(1 << 3)	/* 0; no framing error */

+#define UART_LSR_BRK	(1 << 4)	/* 0: no break detected  1: receive a break signal */

+#define UART_LSR_TDRQ	(1 << 5)	/* 1: transmit FIFO half "empty" */

+#define UART_LSR_TEMT	(1 << 6)	/* 1: transmit FIFO and shift registers empty */

+#define UART_LSR_RFER	(1 << 7)	/* 0: no receive error  1: receive error in FIFO mode */

+

+

+#ifndef __MIPS_ASSEMBLER

+

+/***************************************************************************

+ * UART

+ ***************************************************************************/

+#define __jtag_as_uart3()			\

+do {	                    			\

+	REG_GPIO_PXSELC(0) = 0x40000000;	\

+	REG_GPIO_PXSELS(0) = 0x80000000;	\

+} while(0)

+

+#define __uart_enable(n) \

+  ( REG8(UART_BASE + UART_OFF*(n) + OFF_FCR) |= UARTFCR_UUE | UARTFCR_FE )

+#define __uart_disable(n) \

+  ( REG8(UART_BASE + UART_OFF*(n) + OFF_FCR) = ~UARTFCR_UUE )

+

+#define __uart_enable_transmit_irq(n) \

+  ( REG8(UART_BASE + UART_OFF*(n) + OFF_IER) |= UARTIER_TIE )

+#define __uart_disable_transmit_irq(n) \

+  ( REG8(UART_BASE + UART_OFF*(n) + OFF_IER) &= ~UARTIER_TIE )

+

+#define __uart_enable_receive_irq(n) \

+  ( REG8(UART_BASE + UART_OFF*(n) + OFF_IER) |= UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE )

+#define __uart_disable_receive_irq(n) \

+  ( REG8(UART_BASE + UART_OFF*(n) + OFF_IER) &= ~(UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE) )

+

+#define __uart_enable_loopback(n) \

+  ( REG8(UART_BASE + UART_OFF*(n) + OFF_MCR) |= UARTMCR_LOOP )

+#define __uart_disable_loopback(n) \

+  ( REG8(UART_BASE + UART_OFF*(n) + OFF_MCR) &= ~UARTMCR_LOOP )

+

+#define __uart_set_8n1(n) \

+  ( REG8(UART_BASE + UART_OFF*(n) + OFF_LCR) = UARTLCR_WLEN_8 )

+

+#define __uart_set_baud(n, devclk, baud)						\

+  do {											\

+	REG8(UART_BASE + UART_OFF*(n) + OFF_LCR) |= UARTLCR_DLAB;			\

+	REG8(UART_BASE + UART_OFF*(n) + OFF_DLLR) = (devclk / 16 / baud) & 0xff;	\

+	REG8(UART_BASE + UART_OFF*(n) + OFF_DLHR) = ((devclk / 16 / baud) >> 8) & 0xff;	\

+	REG8(UART_BASE + UART_OFF*(n) + OFF_LCR) &= ~UARTLCR_DLAB;			\

+  } while (0)

+

+#define __uart_parity_error(n) \

+  ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_PER) != 0 )

+

+#define __uart_clear_errors(n) \

+  ( REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) &= ~(UARTLSR_ORER | UARTLSR_BRK | UARTLSR_FER | UARTLSR_PER | UARTLSR_RFER) )

+

+#define __uart_transmit_fifo_empty(n) \

+  ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_TDRQ) != 0 )

+

+#define __uart_transmit_end(n) \

+  ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_TEMT) != 0 )

+

+#define __uart_transmit_char(n, ch) \

+  REG8(UART_BASE + UART_OFF*(n) + OFF_TDR) = (ch)

+

+#define __uart_receive_fifo_full(n) \

+  ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_DR) != 0 )

+

+#define __uart_receive_ready(n) \

+  ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_DR) != 0 )

+

+#define __uart_receive_char(n) \

+  REG8(UART_BASE + UART_OFF*(n) + OFF_RDR)

+

+#define __uart_disable_irda() \

+  ( REG8(IRDA_BASE + OFF_SIRCR) &= ~(SIRCR_TSIRE | SIRCR_RSIRE) )

+#define __uart_enable_irda() \

+  /* Tx high pulse as 0, Rx low pulse as 0 */ \

+  ( REG8(IRDA_BASE + OFF_SIRCR) = SIRCR_TSIRE | SIRCR_RSIRE | SIRCR_RXPL | SIRCR_TPWS )

+

+

+

+#endif /* __MIPS_ASSEMBLER */

+

+#endif /* __JZ4770UART_H__ */

+

diff --git a/arch/mips/include/asm/mach-jz4770/jz4770wdt.h b/arch/mips/include/asm/mach-jz4770/jz4770wdt.h
new file mode 100644
index 00000000000..74f0b3e3f69
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4770/jz4770wdt.h
@@ -0,0 +1,80 @@
+/*

+ * linux/include/asm-mips/mach-jz4810/jz4810wdt.h

+ *

+ * JZ4810 WDT register definition.

+ *

+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

+ */

+

+#ifndef __JZ4770WDT_H__

+#define __JZ4770WDT_H__

+

+

+#define	WDT_BASE	0xB0002000

+/*************************************************************************

+ * WDT (WatchDog Timer)

+ *************************************************************************/

+#define WDT_TDR		(WDT_BASE + 0x00)

+#define WDT_TCER	(WDT_BASE + 0x04)

+#define WDT_TCNT	(WDT_BASE + 0x08)

+#define WDT_TCSR	(WDT_BASE + 0x0C)

+

+#define REG_WDT_TDR	REG16(WDT_TDR)

+#define REG_WDT_TCER	REG8(WDT_TCER)

+#define REG_WDT_TCNT	REG16(WDT_TCNT)

+#define REG_WDT_TCSR	REG16(WDT_TCSR)

+

+// Register definition

+#define WDT_TCSR_PRESCALE_BIT	3

+#define WDT_TCSR_PRESCALE_MASK	(0x7 << WDT_TCSR_PRESCALE_BIT)

+  #define WDT_TCSR_PRESCALE1	(0x0 << WDT_TCSR_PRESCALE_BIT)

+  #define WDT_TCSR_PRESCALE4	(0x1 << WDT_TCSR_PRESCALE_BIT)

+  #define WDT_TCSR_PRESCALE16	(0x2 << WDT_TCSR_PRESCALE_BIT)

+  #define WDT_TCSR_PRESCALE64	(0x3 << WDT_TCSR_PRESCALE_BIT)

+  #define WDT_TCSR_PRESCALE256	(0x4 << WDT_TCSR_PRESCALE_BIT)

+  #define WDT_TCSR_PRESCALE1024	(0x5 << WDT_TCSR_PRESCALE_BIT)

+#define WDT_TCSR_EXT_EN		(1 << 2)

+#define WDT_TCSR_RTC_EN		(1 << 1)

+#define WDT_TCSR_PCK_EN		(1 << 0)

+

+#define WDT_TCER_TCEN		(1 << 0)

+

+

+#ifndef __MIPS_ASSEMBLER

+

+

+/***************************************************************************

+ * WDT

+ ***************************************************************************/

+#define __wdt_start()			( REG_WDT_TCER |= WDT_TCER_TCEN )

+#define __wdt_stop()			( REG_WDT_TCER &= ~WDT_TCER_TCEN )

+#define __wdt_set_count(v)		( REG_WDT_TCNT = (v) )

+#define __wdt_set_data(v)		( REG_WDT_TDR = (v) )

+

+#define __wdt_select_extalclk() \

+	(REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_EXT_EN)

+#define __wdt_select_rtcclk() \

+	(REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_RTC_EN)

+#define __wdt_select_pclk() \

+	(REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_PCK_EN)

+

+#define __wdt_select_clk_div1() \

+	(REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE1)

+#define __wdt_select_clk_div4() \

+	(REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE4)

+#define __wdt_select_clk_div16() \

+	(REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE16)

+#define __wdt_select_clk_div64() \

+	(REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE64)

+#define __wdt_select_clk_div256() \

+	(REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE256)

+#define __wdt_select_clk_div1024() \

+	(REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE1024)

+

+

+

+#endif /* __MIPS_ASSEMBLER */

+

+#endif /* __JZ4770WDT_H__ */

+

+

diff --git a/arch/mips/include/asm/mach-jz4770/jz4770xxx.h b/arch/mips/include/asm/mach-jz4770/jz4770xxx.h
new file mode 100644
index 00000000000..c976595109d
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4770/jz4770xxx.h
@@ -0,0 +1,18 @@
+/*

+ * linux/include/asm-mips/mach-jz4770/jz4770xxx.h

+ *

+ * JZ4770 XXX register definition.

+ *

+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

+ */

+

+#ifndef __JZ4770XXX_H__

+#define __JZ4770XXX_H__

+

+

+#ifndef __MIPS_ASSEMBLER

+

+#endif /* __MIPS_ASSEMBLER */

+

+#endif /* __JZ4770XXX_H__ */

+

diff --git a/arch/mips/include/asm/mach-jz4770/misc.h b/arch/mips/include/asm/mach-jz4770/misc.h
new file mode 100644
index 00000000000..f1287302566
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4770/misc.h
@@ -0,0 +1,44 @@
+/*
+ *  linux/include/asm-mips/mach-jz4770/misc.h
+ *
+ *  Ingenic's JZ4770 common include.
+ *
+ *  Copyright (C) 2008 Ingenic Semiconductor Inc.
+ *
+ *  Author: <cwjia@ingenic.cn>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_JZ4770_MISC_H__
+#define __ASM_JZ4770_MISC_H__
+
+/*==========================================================
+ * I2C
+ *===========================================================*/
+
+#define I2C_EEPROM_DEV	0xA	/* b'1010 */
+#define I2C_RTC_DEV	0xD	/* b'1101 */
+#define DIMM0_SPD_ADDR	0
+#define DIMM1_SPD_ADDR	1
+#define DIMM2_SPD_ADDR	2
+#define DIMM3_SPD_ADDR	3
+#define JZ_HCI_ADDR	7
+
+#define DIMM_SPD_LEN	128
+#define JZ_HCI_LEN	512    /* 4K bits E2PROM */
+#define I2C_RTC_LEN	16
+#define HCI_MAC_OFFSET	64
+
+extern void i2c_open(void);
+extern void i2c_close(void);
+extern void i2c_setclk(unsigned int i2cclk);
+
+extern int i2c_read(unsigned char device, unsigned char *buf,
+		    unsigned char address, int count);
+extern int i2c_write(unsigned char device, unsigned char *buf,
+		     unsigned char address, int count);
+
+#endif /* __ASM_JZ4770_MISC_H__ */
diff --git a/arch/mips/include/asm/mach-jz4770/regs.h b/arch/mips/include/asm/mach-jz4770/regs.h
new file mode 100644
index 00000000000..24d1e9422ef
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4770/regs.h
@@ -0,0 +1,43 @@
+/*
+ * linux/include/asm-mips/mach-jz4810/regs.h
+ *
+ * JZ4810 register definition.
+ *
+ * Copyright (C) 2008 Ingenic Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __JZ4770_REGS_H__
+#define __JZ4770_REGS_H__
+
+
+/*
+ * Define the module base addresses
+ */
+/* AHB0 BUS Devices Base */
+#define HARB0_BASE	0xB3000000
+/* AHB1 BUS Devices Base */
+#define HARB1_BASE	0xB3200000
+#define	DMAGP0_BASE	0xB3210000
+#define	DMAGP1_BASE	0xB3220000
+#define	DMAGP2_BASE	0xB3230000
+#define	DEBLK_BASE	0xB3270000
+#define	IDCT_BASE	0xB3280000
+#define	CABAC_BASE	0xB3290000
+#define	TCSM0_BASE	0xB32B0000
+#define	TCSM1_BASE	0xB32C0000
+#define	SRAM_BASE	0xB32D0000
+/* AHB2 BUS Devices Base */
+#define HARB2_BASE	0xB3400000
+#define UHC_BASE	0xB3430000
+#define GPS_BASE	0xB3480000
+#define ETHC_BASE	0xB34B0000
+/* APB BUS Devices Base */
+#define	OST_BASE	0xB0002000
+#define	PS2_BASE	0xB0060000
+
+
+#endif /* __JZ4770_REGS_H__ */
diff --git a/arch/mips/include/asm/mach-jz4770/serial.h b/arch/mips/include/asm/mach-jz4770/serial.h
new file mode 100644
index 00000000000..ced1867f3b2
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4770/serial.h
@@ -0,0 +1,30 @@
+/*
+ *  linux/include/asm-mips/mach-jz4810/serial.h
+ *
+ *  Ingenic's JZ4810 common include.
+ *
+ *  Copyright (C) 2008 Ingenic Semiconductor Inc.
+ *
+ *  Author: <cwjia@ingenic.cn>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_BOARD_SERIAL_H__
+#define __ASM_BOARD_SERIAL_H__
+
+#ifndef CONFIG_SERIAL_MANY_PORTS
+#undef RS_TABLE_SIZE
+#define RS_TABLE_SIZE  1
+#endif
+
+#define JZ_BASE_BAUD	(33000000/16)
+
+#define JZ_SERIAL_PORT_DEFNS \
+	{ .baud_base = JZ_BASE_BAUD, .irq = IRQ_UART2, \
+	  .flags = STD_COM_FLAGS, .iomem_base = (u8 *)UART2_BASE, \
+	  .iomem_reg_shift = 2, .io_type = SERIAL_IO_MEM },
+
+#endif /* __ASM_BORAD_SERIAL_H__ */
diff --git a/arch/mips/include/asm/mach-jz4770/war.h b/arch/mips/include/asm/mach-jz4770/war.h
new file mode 100644
index 00000000000..ea9445b4ebb
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4770/war.h
@@ -0,0 +1,26 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_MIPS_MACH_JZ4770_WAR_H
+#define __ASM_MIPS_MACH_JZ4770_WAR_H
+
+#define R4600_V1_INDEX_ICACHEOP_WAR	0
+#define R4600_V1_HIT_CACHEOP_WAR	0
+#define R4600_V2_HIT_CACHEOP_WAR	0
+#define R5432_CP0_INTERRUPT_WAR		0
+#define BCM1250_M3_WAR			0
+#define SIBYTE_1956_WAR			0
+#define MIPS4K_ICACHE_REFILL_WAR	0
+#define MIPS_CACHE_SYNC_WAR		0
+#define TX49XX_ICACHE_INDEX_INV_WAR	0
+#define RM9000_CDEX_SMP_WAR		0
+#define ICACHE_REFILLS_WORKAROUND_WAR	0
+#define R10000_LLSC_WAR			0
+#define MIPS34K_MISSED_ITLB_WAR		0
+
+#endif /* __ASM_MIPS_MACH_JZ4770_WAR_H */
+
diff --git a/arch/mips/include/asm/mach-jz4810/board-f4810.h b/arch/mips/include/asm/mach-jz4810/board-f4810.h
index 88f25d3d4f9..f340848130f 100644
--- a/arch/mips/include/asm/mach-jz4810/board-f4810.h
+++ b/arch/mips/include/asm/mach-jz4810/board-f4810.h
@@ -17,19 +17,20 @@
 
 #define CONFIG_FPGA
 
-/*====================================================================== 
+/*======================================================================
  * Frequencies of on-board oscillators
  */
-#define JZ_EXTAL		33000000  /* Main extal freq: 12 MHz */
+#define JZ_EXTAL		24000000  /* Main extal freq: 12 MHz */
 #define JZ_EXTAL2		32768     /* RTC extal freq: 32.768 KHz */
-#define CFG_DIV		2	/* cpu/extclk; only for FPGA */
+#define CFG_DIV		        2	/* cpu/extclk; only for FPGA */
 
-/*====================================================================== 
+/*======================================================================
  * GPIO
  */
-#define GPIO_SD_VCC_EN_N	113 /* GPD17 */
-#define GPIO_SD_CD_N		110 /* GPD14 */
-#define GPIO_SD_WP		112 /* GPD16 */
+#define GPIO_SD0_VCC_EN_N	113 /* GPD17 */
+#define GPIO_SD0_CD_N		110 /* GPD14 */
+#define GPIO_SD0_WP		112 /* GPD16 */
+
 #define GPIO_USB_DETE		102 /* GPD6 */
 #define GPIO_DC_DETE_N		103 /* GPD7 */
 #define GPIO_CHARG_STAT_N	111 /* GPD15 */
@@ -38,34 +39,68 @@
 
 #define GPIO_UDC_HOTPLUG	GPIO_USB_DETE
 
-/*====================================================================== 
+/*======================================================================
  * LCD backlight
  */
-#define GPIO_LCD_PWM   		(32*4+4) /* GPE4 PWM4 */
 
+#define GPIO_LCD_PWM   		(32*4+4) /* GPE4 PWM4 */
 #define LCD_PWM_CHN 4    /* pwm channel */
 #define LCD_PWM_FULL 101
+#define LCD_DEFAULT_BACKLIGHT		80
+#define LCD_MAX_BACKLIGHT		100
+#define LCD_MIN_BACKLIGHT		1
+
 /* 100 level: 0,1,...,100 */
+
 #define __lcd_set_backlight_level(n)	\
 do {					\
-	__gpio_as_output(GPIO_LCD_PWM);	\
-	__gpio_set_pin(GPIO_LCD_PWM);	\
+	__gpio_as_output1(GPIO_LCD_PWM);	\
 } while (0)
 
 #define __lcd_close_backlight()		\
 do {					\
-	__gpio_as_output(GPIO_LCD_PWM);	\
-	__gpio_clear_pin(GPIO_LCD_PWM);	\
+	__gpio_as_output0(GPIO_LCD_PWM);	\
 } while (0)
 
-/*====================================================================== 
+/*======================================================================
  * MMC/SD
  */
 
-#define MSC_WP_PIN		GPIO_SD_WP
-#define MSC_HOTPLUG_PIN		GPIO_SD_CD_N
-#define MSC_HOTPLUG_IRQ		(IRQ_GPIO_0 + GPIO_SD_CD_N)
+#define MSC0_WP_PIN		GPIO_SD0_WP
+#define MSC0_HOTPLUG_PIN		GPIO_SD0_CD_N
+#define MSC0_HOTPLUG_IRQ		(IRQ_GPIO_0 + GPIO_SD0_CD_N)
+
+#if 0
+#define __msc0_init_io()				\
+do {						\
+	__gpio_as_output1(GPIO_SD0_VCC_EN_N);	\
+	__gpio_as_input(GPIO_SD0_CD_N);		\
+} while (0)
+#endif
+#define __msc0_init_io()				\
+do {						\
+	__gpio_as_input(GPIO_SD0_CD_N);		\
+} while (0)
 
+#define __msc0_enable_power()			\
+do {						\
+	__gpio_as_output0(GPIO_SD0_VCC_EN_N);	\
+} while (0)
+
+#define __msc0_disable_power()			\
+do {						\
+	__gpio_as_output1(GPIO_SD0_VCC_EN_N);	\
+} while (0)
+
+#define __msc0_card_detected(s)			\
+({						\
+	int detected = 1;			\
+	if (__gpio_get_pin(GPIO_SD0_CD_N))	\
+		detected = 0;			\
+	detected;				\
+})
+
+#if 0
 #define __msc_init_io()				\
 do {						\
 	__gpio_as_output(GPIO_SD_VCC_EN_N);	\
@@ -89,5 +124,12 @@ do {						\
 		detected = 0;			\
 	detected;				\
 })
+#endif
+#define ACTIVE_LOW_MSC0_CD	1
+#define ACTIVE_LOW_MSC1_CD	1
+
+#define JZ_BOOTUP_UART_TXD	(32 * 2 + 30)
+#define JZ_BOOTUP_UART_RXD	(32 * 2 + 28)
+#define JZ_EARLY_UART_BASE	UART2_BASE
 
 #endif /* __ASM_JZ4810_F4810_H__ */
diff --git a/arch/mips/include/asm/mach-jz4810/clock.h b/arch/mips/include/asm/mach-jz4810/clock.h
index 383b0fcc700..c9d09075e91 100644
--- a/arch/mips/include/asm/mach-jz4810/clock.h
+++ b/arch/mips/include/asm/mach-jz4810/clock.h
@@ -16,7 +16,7 @@
 #define __ASM_JZ4810_CLOCK_H__
 
 #ifndef JZ_EXTAL
-#define JZ_EXTAL		33000000   /* 3.6864 MHz */
+#define JZ_EXTAL		24000000   /* 3.6864 MHz */
 #endif
 #ifndef JZ_EXTAL2
 #define JZ_EXTAL2		32768     /* 32.768 KHz */
diff --git a/arch/mips/include/asm/mach-jz4810/dma.h b/arch/mips/include/asm/mach-jz4810/dma.h
index 042aa2c7acc..6ef25464def 100644
--- a/arch/mips/include/asm/mach-jz4810/dma.h
+++ b/arch/mips/include/asm/mach-jz4810/dma.h
@@ -60,11 +60,7 @@ typedef struct {
 
 /* DMA Device ID's follow */
 enum {
-	DMA_ID_EXT = 0,		/* External request with DREQn */
-	DMA_ID_NAND,		/* NAND DMA request */
-	DMA_ID_BCH_ENC,		/* BCH Encoding DMA request */
-	DMA_ID_BCH_DEC,		/* BCH Decoding DMA request */
-	DMA_ID_AUTO,		/* Auto-request */
+	DMA_ID_AUTO = 0,		/* Auto-request */
 //	DMA_ID_TSSI_RX,		/* TSSI receive fifo full request */
 	DMA_ID_UART3_TX,	/* UART3 transmit-fifo-empty request */
 	DMA_ID_UART3_RX,	/* UART3 receve-fifo-full request */
@@ -78,17 +74,19 @@ enum {
 	DMA_ID_SSI0_RX,		/* SSI0 receive-fifo-empty request */
 	DMA_ID_AIC_TX,		/* AIC transmit-fifo-full request */
 	DMA_ID_AIC_RX,		/* AIC receive-fifo-empty request */
-	DMA_ID_MSC0_TX,		/* MSC0 transmit-fifo-full request */
-	DMA_ID_MSC0_RX,		/* MSC0 receive-fifo-empty request */
+	DMA_ID_MSC0,
 	DMA_ID_TCU_OVERFLOW,	/* TCU channel n overflow interrupt */
 	DMA_ID_SADC,		/* SADC transfer request */
-	DMA_ID_MSC1_TX,		/* MSC1 transmit-fifo-full request */
-	DMA_ID_MSC1_RX,		/* MSC1 receive-fifo-empty request */
+	DMA_ID_MSC1,
+	DMA_ID_MSC2,
 	DMA_ID_SSI1_TX,		/* SSI1 transmit-fifo-full request */
 	DMA_ID_SSI1_RX,		/* SSI1 receive-fifo-empty request */
 	DMA_ID_PCM_TX,		/* PM transmit-fifo-full request */
 	DMA_ID_PCM_RX,		/* PM receive-fifo-empty request */
 	DMA_ID_RAW_SET,
+	DMA_ID_I2C0,
+	DMA_ID_I2C1,
+	DMA_ID_I2C2,
 	DMA_ID_MAX
 };
 
@@ -99,7 +97,7 @@ enum {
 #define DMA_MODE_MASK	0x3
 
 struct jz_dma_chan {
-	int dev_id;	/* DMA ID: this channel is allocated if >=0, free otherwise */ 
+	int dev_id;	/* DMA ID: this channel is allocated if >=0, free otherwise */
 	unsigned int io;        /* DMA channel number */
 	const char *dev_str;    /* string describes the DMA channel */
 	int irq;                /* DMA irq number */
diff --git a/arch/mips/include/asm/mach-jz4810/irq.h b/arch/mips/include/asm/mach-jz4810/irq.h
index e0194e3a075..a1525fc5622 100644
--- a/arch/mips/include/asm/mach-jz4810/irq.h
+++ b/arch/mips/include/asm/mach-jz4810/irq.h
@@ -16,6 +16,6 @@
 #define __ASM_JZ4810_IRQ_H__
 
 /* we need 256 irq levels at least */
-#define NR_IRQS	256
+#define NR_IRQS	384
 
 #endif
diff --git a/arch/mips/include/asm/mach-jz4810/jz4810.h b/arch/mips/include/asm/mach-jz4810/jz4810.h
index a7154ad02c9..9c6db5d284b 100644
--- a/arch/mips/include/asm/mach-jz4810/jz4810.h
+++ b/arch/mips/include/asm/mach-jz4810/jz4810.h
@@ -39,6 +39,7 @@
 #include <asm/mach-jz4810/jz4810otg.h>
 #include <asm/mach-jz4810/jz4810otp.h>
 #include <asm/mach-jz4810/jz4810owi.h>
+#include <asm/mach-jz4810/jz4810ost.h>
 #include <asm/mach-jz4810/jz4810pcm.h>
 #include <asm/mach-jz4810/jz4810rtc.h>
 #include <asm/mach-jz4810/jz4810sadc.h>
@@ -49,6 +50,7 @@
 #include <asm/mach-jz4810/jz4810tve.h>
 #include <asm/mach-jz4810/jz4810uart.h>
 #include <asm/mach-jz4810/jz4810wdt.h>
+#include <asm/mach-jz4810/jz4810aosd.h>
 
 #include <asm/mach-jz4810/dma.h>
 #include <asm/mach-jz4810/misc.h>
diff --git a/arch/mips/include/asm/mach-jz4810/jz4810aic.h b/arch/mips/include/asm/mach-jz4810/jz4810aic.h
index f5699a1a0b8..3ac4832f3a6 100644
--- a/arch/mips/include/asm/mach-jz4810/jz4810aic.h
+++ b/arch/mips/include/asm/mach-jz4810/jz4810aic.h
@@ -1,360 +1,318 @@
 /*

- * linux/include/asm-mips/mach-jz4810/jz4810aic.h

- *

- * JZ4810 AIC register definition.

- *

+ * chip-aic.h

+ * JZ4760 AIC register definition

  * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

+ *

+ * Author: whxu@ingenic.cn

  */

 

-#ifndef __JZ4810AIC_H__

-#define __JZ4810AIC_H__

-

+#ifndef __CHIP_AIC_H__

+#define __CHIP_AIC_H__

 

-#define	AIC_BASE	0xB0020000

-#define	ICDC_BASE	0xB0020000

-

-

-/*************************************************************************

- * AIC (AC97/I2S Controller)

- *************************************************************************/

-#define	AIC_FR			(AIC_BASE + 0x000)

-#define	AIC_CR			(AIC_BASE + 0x004)

-#define	AIC_ACCR1		(AIC_BASE + 0x008)

-#define	AIC_ACCR2		(AIC_BASE + 0x00C)

-#define	AIC_I2SCR		(AIC_BASE + 0x010)

-#define	AIC_SR			(AIC_BASE + 0x014)

-#define	AIC_ACSR		(AIC_BASE + 0x018)

-#define	AIC_I2SSR		(AIC_BASE + 0x01C)

-#define	AIC_ACCAR		(AIC_BASE + 0x020)

-#define	AIC_ACCDR		(AIC_BASE + 0x024)

-#define	AIC_ACSAR		(AIC_BASE + 0x028)

-#define	AIC_ACSDR		(AIC_BASE + 0x02C)

-#define	AIC_I2SDIV		(AIC_BASE + 0x030)

-#define	AIC_DR			(AIC_BASE + 0x034)

 

-#define	REG_AIC_FR		REG32(AIC_FR)

-#define	REG_AIC_CR		REG32(AIC_CR)

-#define	REG_AIC_ACCR1		REG32(AIC_ACCR1)

-#define	REG_AIC_ACCR2		REG32(AIC_ACCR2)

-#define	REG_AIC_I2SCR		REG32(AIC_I2SCR)

-#define	REG_AIC_SR		REG32(AIC_SR)

-#define	REG_AIC_ACSR		REG32(AIC_ACSR)

-#define	REG_AIC_I2SSR		REG32(AIC_I2SSR)

-#define	REG_AIC_ACCAR		REG32(AIC_ACCAR)

-#define	REG_AIC_ACCDR		REG32(AIC_ACCDR)

-#define	REG_AIC_ACSAR		REG32(AIC_ACSAR)

-#define	REG_AIC_ACSDR		REG32(AIC_ACSDR)

-#define	REG_AIC_I2SDIV		REG32(AIC_I2SDIV)

-#define	REG_AIC_DR		REG32(AIC_DR)

+/*

+ * AC97 and I2S controller module(AIC) address definition

+ */

+#define	AIC_BASE	0xb0020000

+//#define	AIC_BASE	0xb0024000

 

-/* AIC Controller Configuration Register (AIC_FR) */

-

-#define	AIC_FR_RFTH_BIT		24        /* Receive FIFO Threshold */

-#define	AIC_FR_RFTH_MASK	(0xf << AIC_FR_RFTH_BIT)

-#define	AIC_FR_TFTH_BIT		16         /* Transmit FIFO Threshold */

-#define	AIC_FR_TFTH_MASK	(0x1f << AIC_FR_TFTH_BIT)

-#define	AIC_FR_LSMP		(1 << 6)  /* Play Zero sample or last sample */

-#define	AIC_FR_ICDC		(1 << 5)  /* External(0) or Internal CODEC(1) */

-#define	AIC_FR_AUSEL		(1 << 4)  /* AC97(0) or I2S/MSB-justified(1) */

-#define	AIC_FR_RST		(1 << 3)  /* AIC registers reset */

-#define	AIC_FR_BCKD		(1 << 2)  /* I2S BIT_CLK direction, 0:input,1:output */

-#define	AIC_FR_SYNCD		(1 << 1)  /* I2S SYNC direction, 0:input,1:output */

-#define	AIC_FR_ENB		(1 << 0)  /* AIC enable bit */

-

-/* AIC Controller Common Control Register (AIC_CR) */

-

-#define AIC_CR_EN2OLD           (1 << 29)  /* Enable old style */

-#define AIC_CR_PACK16           (1 << 28)  /* Output Sample data 16bit packed mode select */

-#define AIC_CR_CHANNEL_BIT      24  /* Output Channel Number Select */

-#define AIC_CR_CHANNEL_MASK     (0x7 << AIC_CR_CHANNEL_BIT)

-  #define AIC_CR_CHANNEL_MONO   (0x0 << AIC_CR_CHANNEL_BIT)

-  #define AIC_CR_CHANNEL_STEREO (0x1 << AIC_CR_CHANNEL_BIT)

-  #define AIC_CR_CHANNEL_4CHNL  (0x3 << AIC_CR_CHANNEL_BIT)

-  #define AIC_CR_CHANNEL_6CHNL  (0x5 << AIC_CR_CHANNEL_BIT)

-  #define AIC_CR_CHANNEL_8CHNL  (0x7 << AIC_CR_CHANNEL_BIT)

-

-#define	AIC_CR_OSS_BIT		19  /* Output Sample Size from memory (AIC V2 only) */

-#define	AIC_CR_OSS_MASK		(0x7 << AIC_CR_OSS_BIT)

-  #define AIC_CR_OSS_8BIT	(0x0 << AIC_CR_OSS_BIT)

-  #define AIC_CR_OSS_16BIT	(0x1 << AIC_CR_OSS_BIT)

-  #define AIC_CR_OSS_18BIT	(0x2 << AIC_CR_OSS_BIT)

-  #define AIC_CR_OSS_20BIT	(0x3 << AIC_CR_OSS_BIT)

-  #define AIC_CR_OSS_24BIT	(0x4 << AIC_CR_OSS_BIT)

-#define	AIC_CR_ISS_BIT		16  /* Input Sample Size from memory (AIC V2 only) */

-#define	AIC_CR_ISS_MASK		(0x7 << AIC_CR_ISS_BIT)

-  #define AIC_CR_ISS_8BIT	(0x0 << AIC_CR_ISS_BIT)

-  #define AIC_CR_ISS_16BIT	(0x1 << AIC_CR_ISS_BIT)

-  #define AIC_CR_ISS_18BIT	(0x2 << AIC_CR_ISS_BIT)

-  #define AIC_CR_ISS_20BIT	(0x3 << AIC_CR_ISS_BIT)

-  #define AIC_CR_ISS_24BIT	(0x4 << AIC_CR_ISS_BIT)

-#define	AIC_CR_RDMS		(1 << 15)  /* Receive DMA enable */

-#define	AIC_CR_TDMS		(1 << 14)  /* Transmit DMA enable */

-#define	AIC_CR_M2S		(1 << 11)  /* Mono to Stereo enable */

-#define	AIC_CR_ENDSW		(1 << 10)  /* Endian switch enable */

-#define	AIC_CR_AVSTSU		(1 << 9)   /* Signed <-> Unsigned toggle enable */

-#define	AIC_CR_TFLUSH		(1 << 8)   /* Flush TFIFO */

-#define	AIC_CR_RFLUSH		(1 << 7)   /* Flush RFIFO */

-#define	AIC_CR_EROR		(1 << 6)   /* Enable ROR interrupt */

-#define	AIC_CR_ETUR		(1 << 5)   /* Enable TUR interrupt */

-#define	AIC_CR_ERFS		(1 << 4)   /* Enable RFS interrupt */

-#define	AIC_CR_ETFS		(1 << 3)   /* Enable TFS interrupt */

-#define	AIC_CR_ENLBF		(1 << 2)   /* Enable Loopback Function */

-#define	AIC_CR_ERPL		(1 << 1)   /* Enable Playback Function */

-#define	AIC_CR_EREC		(1 << 0)   /* Enable Record Function */

-

-/* AIC Controller AC-link Control Register 1 (AIC_ACCR1) */

-

-#define	AIC_ACCR1_RS_BIT	16          /* Receive Valid Slots */

-#define	AIC_ACCR1_RS_MASK	(0x3ff << AIC_ACCR1_RS_BIT)

-  #define AIC_ACCR1_RS_SLOT12	  (1 << 25) /* Slot 12 valid bit */

-  #define AIC_ACCR1_RS_SLOT11	  (1 << 24) /* Slot 11 valid bit */

-  #define AIC_ACCR1_RS_SLOT10	  (1 << 23) /* Slot 10 valid bit */

-  #define AIC_ACCR1_RS_SLOT9	  (1 << 22) /* Slot 9 valid bit, LFE */

-  #define AIC_ACCR1_RS_SLOT8	  (1 << 21) /* Slot 8 valid bit, Surround Right */

-  #define AIC_ACCR1_RS_SLOT7	  (1 << 20) /* Slot 7 valid bit, Surround Left */

-  #define AIC_ACCR1_RS_SLOT6	  (1 << 19) /* Slot 6 valid bit, PCM Center */

-  #define AIC_ACCR1_RS_SLOT5	  (1 << 18) /* Slot 5 valid bit */

-  #define AIC_ACCR1_RS_SLOT4	  (1 << 17) /* Slot 4 valid bit, PCM Right */

-  #define AIC_ACCR1_RS_SLOT3	  (1 << 16) /* Slot 3 valid bit, PCM Left */

-#define	AIC_ACCR1_XS_BIT	0          /* Transmit Valid Slots */

-#define	AIC_ACCR1_XS_MASK	(0x3ff << AIC_ACCR1_XS_BIT)

-  #define AIC_ACCR1_XS_SLOT12	  (1 << 9) /* Slot 12 valid bit */

-  #define AIC_ACCR1_XS_SLOT11	  (1 << 8) /* Slot 11 valid bit */

-  #define AIC_ACCR1_XS_SLOT10	  (1 << 7) /* Slot 10 valid bit */

-  #define AIC_ACCR1_XS_SLOT9	  (1 << 6) /* Slot 9 valid bit, LFE */

-  #define AIC_ACCR1_XS_SLOT8	  (1 << 5) /* Slot 8 valid bit, Surround Right */

-  #define AIC_ACCR1_XS_SLOT7	  (1 << 4) /* Slot 7 valid bit, Surround Left */

-  #define AIC_ACCR1_XS_SLOT6	  (1 << 3) /* Slot 6 valid bit, PCM Center */

-  #define AIC_ACCR1_XS_SLOT5	  (1 << 2) /* Slot 5 valid bit */

-  #define AIC_ACCR1_XS_SLOT4	  (1 << 1) /* Slot 4 valid bit, PCM Right */

-  #define AIC_ACCR1_XS_SLOT3	  (1 << 0) /* Slot 3 valid bit, PCM Left */

-

-/* AIC Controller AC-link Control Register 2 (AIC_ACCR2) */

-

-#define	AIC_ACCR2_ERSTO		(1 << 18) /* Enable RSTO interrupt */

-#define	AIC_ACCR2_ESADR		(1 << 17) /* Enable SADR interrupt */

-#define	AIC_ACCR2_ECADT		(1 << 16) /* Enable CADT interrupt */

-#define	AIC_ACCR2_OASS_BIT	8  /* Output Sample Size for AC-link */

-#define	AIC_ACCR2_OASS_MASK	(0x3 << AIC_ACCR2_OASS_BIT)

-  #define AIC_ACCR2_OASS_20BIT	  (0 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 20-bit */

-  #define AIC_ACCR2_OASS_18BIT	  (1 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 18-bit */

-  #define AIC_ACCR2_OASS_16BIT	  (2 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 16-bit */

-  #define AIC_ACCR2_OASS_8BIT	  (3 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 8-bit */

-#define	AIC_ACCR2_IASS_BIT	6  /* Output Sample Size for AC-link */

-#define	AIC_ACCR2_IASS_MASK	(0x3 << AIC_ACCR2_IASS_BIT)

-  #define AIC_ACCR2_IASS_20BIT	  (0 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 20-bit */

-  #define AIC_ACCR2_IASS_18BIT	  (1 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 18-bit */

-  #define AIC_ACCR2_IASS_16BIT	  (2 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 16-bit */

-  #define AIC_ACCR2_IASS_8BIT	  (3 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 8-bit */

-#define	AIC_ACCR2_SO		(1 << 3)  /* SDATA_OUT output value */

-#define	AIC_ACCR2_SR		(1 << 2)  /* RESET# pin level */

-#define	AIC_ACCR2_SS		(1 << 1)  /* SYNC pin level */

-#define	AIC_ACCR2_SA		(1 << 0)  /* SYNC and SDATA_OUT alternation */

-

-/* AIC Controller I2S/MSB-justified Control Register (AIC_I2SCR) */

-

-#define	AIC_I2SCR_RFIRST	(1 << 17) /* Send R channel first in stereo mode */

-#define	AIC_I2SCR_SWLH   	(1 << 16) /* Switch LR channel in 16bit-packed stereo mode */ 

-#define	AIC_I2SCR_STPBK		(1 << 12) /* Stop BIT_CLK for I2S/MSB-justified */

-#define	AIC_I2SCR_WL_BIT	1  /* Input/Output Sample Size for I2S/MSB-justified */

-#define	AIC_I2SCR_WL_MASK	(0x7 << AIC_I2SCR_WL_BIT)

-  #define AIC_I2SCR_WL_24BIT	  (0 << AIC_I2SCR_WL_BIT) /* Word Length is 24 bit */

-  #define AIC_I2SCR_WL_20BIT	  (1 << AIC_I2SCR_WL_BIT) /* Word Length is 20 bit */

-  #define AIC_I2SCR_WL_18BIT	  (2 << AIC_I2SCR_WL_BIT) /* Word Length is 18 bit */

-  #define AIC_I2SCR_WL_16BIT	  (3 << AIC_I2SCR_WL_BIT) /* Word Length is 16 bit */

-  #define AIC_I2SCR_WL_8BIT	  (4 << AIC_I2SCR_WL_BIT) /* Word Length is 8 bit */

-

-#define AIC_I2SCR_ESCLK		(1 << 4)

-

-#define	AIC_I2SCR_AMSL		(1 << 0) /* 0:I2S, 1:MSB-justified */

-

-/* AIC Controller FIFO Status Register (AIC_SR) */

-

-#define	AIC_SR_RFL_BIT		24  /* Receive FIFO Level */

-#define	AIC_SR_RFL_MASK		(0x3f << AIC_SR_RFL_BIT)

-#define	AIC_SR_TFL_BIT		8   /* Transmit FIFO level */

-#define	AIC_SR_TFL_MASK		(0x3f << AIC_SR_TFL_BIT)

-#define	AIC_SR_ROR		(1 << 6) /* Receive FIFO Overrun */

-#define	AIC_SR_TUR		(1 << 5) /* Transmit FIFO Underrun */

-#define	AIC_SR_RFS		(1 << 4) /* Receive FIFO Service Request */

-#define	AIC_SR_TFS		(1 << 3) /* Transmit FIFO Service Request */

-

-/* AIC Controller AC-link Status Register (AIC_ACSR) */

-

-#define	AIC_ACSR_SLTERR		(1 << 21) /* Slot Error Flag */

-#define	AIC_ACSR_CRDY		(1 << 20) /* External CODEC Ready Flag */

-#define	AIC_ACSR_CLPM		(1 << 19) /* External CODEC low power mode flag */

-#define	AIC_ACSR_RSTO		(1 << 18) /* External CODEC regs read status timeout */

-#define	AIC_ACSR_SADR		(1 << 17) /* External CODEC regs status addr and data received */

-#define	AIC_ACSR_CADT		(1 << 16) /* Command Address and Data Transmitted */

-

-/* AIC Controller I2S/MSB-justified Status Register (AIC_I2SSR) */

-

-#define	AIC_I2SSR_BSY		(1 << 2)  /* AIC Busy in I2S/MSB-justified format */

-

-/* AIC Controller AC97 codec Command Address Register (AIC_ACCAR) */

-

-#define	AIC_ACCAR_CAR_BIT	0

-#define	AIC_ACCAR_CAR_MASK	(0xfffff << AIC_ACCAR_CAR_BIT)

-

-/* AIC Controller AC97 codec Command Data Register (AIC_ACCDR) */

-

-#define	AIC_ACCDR_CDR_BIT	0

-#define	AIC_ACCDR_CDR_MASK	(0xfffff << AIC_ACCDR_CDR_BIT)

-

-/* AIC Controller AC97 codec Status Address Register (AIC_ACSAR) */

-

-#define	AIC_ACSAR_SAR_BIT	0

-#define	AIC_ACSAR_SAR_MASK	(0xfffff << AIC_ACSAR_SAR_BIT)

-

-/* AIC Controller AC97 codec Status Data Register (AIC_ACSDR) */

-

-#define	AIC_ACSDR_SDR_BIT	0

-#define	AIC_ACSDR_SDR_MASK	(0xfffff << AIC_ACSDR_SDR_BIT)

-

-/* AIC Controller I2S/MSB-justified Clock Divider Register (AIC_I2SDIV) */

-

-#define	AIC_I2SDIV_DIV_BIT	0

-#define	AIC_I2SDIV_DIV_MASK	(0x7f << AIC_I2SDIV_DIV_BIT)

-  #define AIC_I2SDIV_BITCLK_3072KHZ	(0x0C << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 3.072MHz */

-  #define AIC_I2SDIV_BITCLK_2836KHZ	(0x0D << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 2.836MHz */

-  #define AIC_I2SDIV_BITCLK_1418KHZ	(0x1A << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 1.418MHz */

-  #define AIC_I2SDIV_BITCLK_1024KHZ	(0x24 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 1.024MHz */

-  #define AIC_I2SDIV_BITCLK_7089KHZ	(0x34 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 708.92KHz */

-  #define AIC_I2SDIV_BITCLK_512KHZ	(0x48 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 512.00KHz */

 

+/*

+ * AIC registers offset address definition

+ */

+#define AIC_FR_OFFSET		(0x00)

+#define AIC_CR_OFFSET		(0x04)

+#define AIC_ACCR1_OFFSET	(0x08)

+#define AIC_ACCR2_OFFSET	(0x0c)

+#define AIC_I2SCR_OFFSET	(0x10)

+#define AIC_SR_OFFSET		(0x14)

+#define AIC_ACSR_OFFSET		(0x18)

+#define AIC_I2SSR_OFFSET	(0x1c)

+#define AIC_ACCAR_OFFSET	(0x20)

+#define AIC_ACCDR_OFFSET	(0x24)

+#define AIC_ACSAR_OFFSET	(0x28)

+#define AIC_ACSDR_OFFSET	(0x2c)

+#define AIC_I2SDIV_OFFSET	(0x30)

+#define AIC_DR_OFFSET		(0x34)

+

+#define SPDIF_ENA_OFFSET	(0x80)

+#define SPDIF_CTRL_OFFSET	(0x84)

+#define SPDIF_STATE_OFFSET	(0x88)

+#define SPDIF_CFG1_OFFSET	(0x8c)

+#define SPDIF_CFG2_OFFSET	(0x90)

+#define SPDIF_FIFO_OFFSET	(0x94)

+

+#define ICDC_RGADW_OFFSET	(0xa4)

+#define ICDC_RGDATA_OFFSET	(0xa8)

 

 

-/*************************************************************************

- * ICDC (Internal CODEC)

- *************************************************************************/

+/*

+ * AIC registers address definition

+ */

+#define AIC_FR		(AIC_BASE + AIC_FR_OFFSET)

+#define AIC0_FR		(0xb0020000 + AIC_FR_OFFSET)

+#define AIC_CR		(AIC_BASE + AIC_CR_OFFSET)

+#define AIC_ACCR1	(AIC_BASE + AIC_ACCR1_OFFSET)

+#define AIC_ACCR2	(AIC_BASE + AIC_ACCR2_OFFSET)

+#define AIC_I2SCR	(AIC_BASE + AIC_I2SCR_OFFSET)

+#define AIC_SR		(AIC_BASE + AIC_SR_OFFSET)

+#define AIC_ACSR	(AIC_BASE + AIC_ACSR_OFFSET)

+#define AIC_I2SSR	(AIC_BASE + AIC_I2SSR_OFFSET)

+#define AIC_ACCAR	(AIC_BASE + AIC_ACCAR_OFFSET)

+#define AIC_ACCDR	(AIC_BASE + AIC_ACCDR_OFFSET)

+#define AIC_ACSAR	(AIC_BASE + AIC_ACSAR_OFFSET)

+#define AIC_ACSDR	(AIC_BASE + AIC_ACSDR_OFFSET)

+#define AIC_I2SDIV	(AIC_BASE + AIC_I2SDIV_OFFSET)

+#define AIC_DR		(AIC_BASE + AIC_DR_OFFSET)

+

+#define SPDIF_ENA	(AIC_BASE + SPDIF_ENA_OFFSET)

+#define SPDIF_CTRL	(AIC_BASE + SPDIF_CTRL_OFFSET)

+#define SPDIF_STATE	(AIC_BASE + SPDIF_STATE_OFFSET)

+#define SPDIF_CFG1	(AIC_BASE + SPDIF_CFG1_OFFSET)

+#define SPDIF_CFG2	(AIC_BASE + SPDIF_CFG2_OFFSET)

+#define SPDIF_FIFO	(AIC_BASE + SPDIF_FIFO_OFFSET)

+

+#define ICDC_RGADW	(0xb0020000 + ICDC_RGADW_OFFSET)

+#define ICDC_RGDATA	(0xb0020000 + ICDC_RGDATA_OFFSET)

 

-#define	ICDC_CKCFG	  (ICDC_BASE + 0x00a0)  /* Clock Configure Register */

-#define	ICDC_RGADW	  (ICDC_BASE + 0x00a4)  /* internal register access control */

-#define	ICDC_RGDATA	  (ICDC_BASE + 0x00a8)  /* internal register data output */

 

-#define	REG_ICDC_CKCFG		REG32(ICDC_CKCFG)

-#define	REG_ICDC_RGADW		REG32(ICDC_RGADW)

-#define	REG_ICDC_RGDATA		REG32(ICDC_RGDATA)

+/*

+ * AIC registers common define

+ */

 

-/* ICDC Clock Configure Register */

-#define	ICDC_CKCFG_CKRDY	(1 << 1) 

-#define	ICDC_CKCFG_SELAD	(1 << 0)

+/* AIC controller configuration register(AICFR) */

+#define	AIC_FR_LSMP		BIT6

+#define	AIC_FR_ICDC		BIT5

+#define	AIC_FR_AUSEL		BIT4

+#define	AIC_FR_RST		BIT3

+#define	AIC_FR_BCKD		BIT2

+#define	AIC_FR_SYNCD		BIT1

+#define	AIC_FR_ENB		BIT0

+

+#define	AIC_FR_RFTH_LSB		24

+#define	AIC_FR_RFTH_MASK	BITS_H2L(27, AIC_FR_RFTH_LSB)

+

+#define	AIC_FR_TFTH_LSB		16

+#define	AIC_FR_TFTH_MASK	BITS_H2L(20, AIC_FR_TFTH_LSB)

+

+/* AIC controller common control register(AICCR) */

+#define AIC_CR_PACK16		BIT28

+#define	AIC_CR_RDMS		BIT15

+#define	AIC_CR_TDMS		BIT14

+#define	AIC_CR_M2S		BIT11

+#define	AIC_CR_ENDSW		BIT10

+#define	AIC_CR_AVSTSU		BIT9

+#define	AIC_CR_TFLUSH		BIT8

+#define	AIC_CR_RFLUSH		BIT7

+#define	AIC_CR_EROR		BIT6

+#define	AIC_CR_ETUR		BIT5

+#define	AIC_CR_ERFS		BIT4

+#define	AIC_CR_ETFS		BIT3

+#define	AIC_CR_ENLBF		BIT2

+#define	AIC_CR_ERPL		BIT1

+#define	AIC_CR_EREC		BIT0

+

+#define AIC_CR_CHANNEL_LSB	24

+#define AIC_CR_CHANNEL_MASK	BITS_H2L(26, AIC_CR_CHANNEL_LSB)

+

+#define	AIC_CR_OSS_LSB		19

+#define	AIC_CR_OSS_MASK		BITS_H2L(21, AIC_CR_OSS_LSB)

+ #define AIC_CR_OSS(n)		(((n) > 18 ? (n)/6 : (n)/9) << AIC_CR_OSS_LSB)	/* n = 8, 16, 18, 20, 24 */

+

+#define	AIC_CR_ISS_LSB		16

+#define	AIC_CR_ISS_MASK		BITS_H2L(18, AIC_CR_ISS_LSB)

+ #define AIC_CR_ISS(n)		(((n) > 18 ? (n)/6 : (n)/9) << AIC_CR_ISS_LSB)	/* n = 8, 16, 18, 20, 24 */

+

+/* AIC controller AC-link control register 1(ACCR1) */

+#define AIC_ACCR1_RS_LSB	16

+#define	AIC_ACCR1_RS_MASK	BITS_H2L(25, AIC_ACCR1_RS_LSB)

+ #define AIC_ACCR1_RS_SLOT(n)	((1 << ((n) - 3)) << AIC_ACCR1_RS_LSB)	/* n = 3 .. 12 */

+

+#define AIC_ACCR1_XS_LSB	0

+#define	AIC_ACCR1_XS_MASK	BITS_H2L(9, AIC_ACCR1_XS_LSB)

+ #define AIC_ACCR1_XS_SLOT(n)	((1 << ((n) - 3)) << AIC_ACCR1_XS_LSB)	/* n = 3 .. 12 */

+

+/* AIC controller AC-link control register 2 (ACCR2) */

+#define	AIC_ACCR2_ERSTO		BIT18

+#define	AIC_ACCR2_ESADR		BIT17

+#define	AIC_ACCR2_ECADT		BIT16

+#define	AIC_ACCR2_SO		BIT3

+#define	AIC_ACCR2_SR		BIT2

+#define	AIC_ACCR2_SS		BIT1

+#define	AIC_ACCR2_SA		BIT0

+

+/* AIC controller i2s/msb-justified control register (I2SCR) */

+#define	AIC_I2SCR_RFIRST	BIT17

+#define	AIC_I2SCR_SWLH   	BIT16

+#define	AIC_I2SCR_STPBK		BIT12

+#define AIC_I2SCR_ESCLK		BIT4

+#define	AIC_I2SCR_AMSL		BIT0

+

+/* AIC controller FIFO status register (AICSR) */

+#define	AIC_SR_ROR		BIT6

+#define	AIC_SR_TUR		BIT5

+#define	AIC_SR_RFS		BIT4

+#define	AIC_SR_TFS		BIT3

+

+#define	AIC_SR_RFL_LSB		24

+#define	AIC_SR_RFL_MASK		BITS_H2L(29, AIC_SR_RFL_LSB)

+

+#define	AIC_SR_TFL_LSB		8

+#define	AIC_SR_TFL_MASK		BITS_H2L(13, AIC_SR_TFL_LSB)

+

+/* AIC controller AC-link status register (ACSR) */

+#define	AIC_ACSR_SLTERR		BIT21

+#define	AIC_ACSR_CRDY		BIT20

+#define	AIC_ACSR_CLPM		BIT19

+#define	AIC_ACSR_RSTO		BIT18

+#define	AIC_ACSR_SADR		BIT17

+#define	AIC_ACSR_CADT		BIT16

+

+/* AIC controller I2S/MSB-justified status register (I2SSR) */

+#define	AIC_I2SSR_CHBSY		BIT5

+#define	AIC_I2SSR_TBSY		BIT4

+#define	AIC_I2SSR_RBSY		BIT3

+#define	AIC_I2SSR_BSY		BIT2

+

+/* AIC controller AC97 codec command address register (ACCAR) */

+#define	AIC_ACCAR_CAR_LSB	0

+#define	AIC_ACCAR_CAR_MASK	BITS_H2L(19, AIC_ACCAR_CAR_LSB)

+

+

+/* AIC controller AC97 codec command data register (ACCDR) */

+#define	AIC_ACCDR_CDR_LSB	0

+#define	AIC_ACCDR_CDR_MASK	BITS_H2L(19, AIC_ACCDR_CDR_LSB)

+

+/* AC97 read and write macro based on ACCAR and ACCDR */

+#define AC97_READ_CMD		BIT19

+#define AC97_WRITE_CMD		(BIT19 & ~BIT19)

+

+#define AC97_INDEX_LSB		12

+#define AC97_INDEX_MASK		BITS_H2L(18, AC97_INDEX_LSB)

+

+#define AC97_DATA_LSB		4

+#define AC97_DATA_MASK		BITS_H2L(19, AC97_DATA_LSB)

+

+/* AIC controller AC97 codec status address register (ACSAR) */

+#define	AIC_ACSAR_SAR_LSB	0

+#define	AIC_ACSAR_SAR_MASK	BITS_H2L(19, AIC_ACSAR_SAR_LSB)

+

+/* AIC controller AC97 codec status data register (ACSDR) */

+#define	AIC_ACSDR_SDR_LSB	0

+#define	AIC_ACSDR_SDR_MASK	BITS_H2L(19, AIC_ACSDR_SDR_LSB)

+

+/* AIC controller I2S/MSB-justified clock divider register (I2SDIV) */

+#define	AIC_I2SDIV_DIV_LSB	0

+#define	AIC_I2SDIV_DIV_MASK	BITS_H2L(3, AIC_I2SDIV_DIV_LSB)

+

+/* SPDIF enable register (SPDIF_ENA) */

+#define SPDIF_ENA_SPEN		BIT0

 

-/* ICDC internal register access control Register */

-#define ICDC_RGADW_RGWR         (1 << 16)

-#define ICDC_RGADW_RGADDR_BIT   8

-#define	ICDC_RGADW_RGADDR_MASK	(0x7f << ICDC_RGADW_RGADDR_BIT)

-#define ICDC_RGADW_RGDIN_BIT    0

-#define	ICDC_RGADW_RGDIN_MASK	(0xff << ICDC_RGADW_RGDIN_BIT)

+/* SPDIF control register (SPDIF_CTRL) */

+#define SPDIF_CTRL_DMAEN        BIT15

+#define SPDIF_CTRL_DTYPE        BIT14

+#define SPDIF_CTRL_SIGN         BIT13

+#define SPDIF_CTRL_INVALID      BIT12

+#define SPDIF_CTRL_RST          BIT11

+#define SPDIF_CTRL_SPDIFI2S     BIT10

+#define SPDIF_CTRL_MTRIG        BIT1

+#define SPDIF_CTRL_MFFUR        BIT0

 

-/* ICDC internal register data output Register */

-#define ICDC_RGDATA_IRQ         (1 << 8)

-#define ICDC_RGDATA_RGDOUT_BIT  0

-#define ICDC_RGDATA_RGDOUT_MASK (0xff << ICDC_RGDATA_RGDOUT_BIT)

+/* SPDIF state register (SPDIF_STAT) */

+#define SPDIF_STAT_BUSY		BIT7

+#define SPDIF_STAT_FTRIG	BIT1

+#define SPDIF_STAT_FUR		BIT0

 

-/*************************************************************************

- * SPDIF INTERFACE in AIC Controller

- *************************************************************************/

+#define SPDIF_STAT_FLVL_LSB	8

+#define SPDIF_STAT_FLVL_MASK	BITS_H2L(14, SPDIF_STAT_FLVL_LSB)

 

-#define SPDIF_ENA               (AIC_BASE + 0x080) 

-#define SPDIF_CTRL              (AIC_BASE + 0x084)

-#define SPDIF_STATE             (AIC_BASE + 0x088)

-#define SPDIF_CFG1              (AIC_BASE + 0x08c)

-#define SPDIF_CFG2              (AIC_BASE + 0x090)

-#define SPDIF_FIFO              (AIC_BASE + 0x094)

+/* SPDIF configure 1 register (SPDIF_CFG1) */

+#define SPDIF_CFG1_INITLVL	BIT17

+#define SPDIF_CFG1_ZROVLD	BIT16

 

-#define REG_SPDIF_ENA           REG32(SPDIF_ENA) 

-#define REG_SPDIF_CTRL          REG32(SPDIF_CTRL)

-#define REG_SPDIF_STATE         REG32(SPDIF_STATE)

-#define REG_SPDIF_CFG1          REG32(SPDIF_CFG1)

-#define REG_SPDIF_CFG2          REG32(SPDIF_CFG2)

-#define REG_SPDIF_FIFO          REG32(SPDIF_FIFO)

+#define SPDIF_CFG1_TRIG_LSB	12

+#define SPDIF_CFG1_TRIG_MASK	BITS_H2L(13, SPDIF_CFG1_TRIG_LSB)

+#define SPDIF_CFG1_TRIG(n)	(((n) > 16 ? 3 : (n)/8) << SPDIF_CFG1_TRIG_LSB)	/* n = 4, 8, 16, 32 */

 

-/* SPDIF Enable Register (SPDIF_ENA) */

+#define SPDIF_CFG1_SRCNUM_LSB	8

+#define SPDIF_CFG1_SRCNUM_MASK	BITS_H2L(11, SPDIF_CFG1_SRCNUM_LSB)

 

-#define SPDIF_ENA_SPEN		(1 << 0)  /* Enable or disable the SPDIF transmitter */

+#define SPDIF_CFG1_CH1NUM_LSB	4

+#define SPDIF_CFG1_CH1NUM_MASK	BITS_H2L(7, SPDIF_CFG1_CH1NUM_LSB)

 

-/* SPDIF Control Register (SPDIF_CTRL) */

+#define SPDIF_CFG1_CH2NUM_LSB	0

+#define SPDIF_CFG1_CH2NUM_MASK	BITS_H2L(3, SPDIF_CFG1_CH2NUM_LSB)

 

-#define SPDIF_CTRL_DMAEN        (1 << 15)

-#define SPDIF_CTRL_DTYPE        (1 << 14)

-#define SPDIF_CTRL_SIGN         (1 << 13)

-#define SPDIF_CTRL_INVALID      (1 << 12)

-#define SPDIF_CTRL_RST          (1 << 11)

-#define SPDIF_CTRL_SPDIFI2S     (1 << 10)

-#define SPDIF_CTRL_MTRIG        (1 << 1)

-#define SPDIF_CTRL_MFFUR        (1 << 0)

+/* SPDIF configure 2 register (SPDIF_CFG2) */

+#define SPDIF_CFG2_MAXWL	BIT18

+#define SPDIF_CFG2_PRE		BIT3

+#define SPDIF_CFG2_COPYN	BIT2

+#define SPDIF_CFG2_AUDION	BIT1

+#define SPDIF_CFG2_CONPRO	BIT0

 

-/* SPDIF Configure 1 Register (SPDIF_CFG1) */

+#define SPDIF_CFG2_FS_LSB	26

+#define SPDIF_CFG2_FS_MASK	BITS_H2L(29, SPDIF_CFG2_FS_LSB)

 

-#define SPDIF_CFG1_INITLVL      (1 << 17)

-#define SPDIF_CFG1_ZROVLD       (1 << 16)

+#define SPDIF_CFG2_ORGFRQ_LSB	22

+#define SPDIF_CFG2_ORGFRQ_MASK	BITS_H2L(25, SPDIF_CFG2_ORGFRQ_LSB)

 

-#define SPDIF_CFG1_TRIG_BIT     12

-#define SPDIF_CFG1_TRIG_MASK    (0x3 << SPDIF_CFG1_TRIG_BIT)

-  #define SPDIF_CFG1_TRIG_4     (0x0 << SPDIF_CFG1_TRIG_BIT)

-  #define SPDIF_CFG1_TRIG_8     (0x1 << SPDIF_CFG1_TRIG_BIT)

-  #define SPDIF_CFG1_TRIG_16    (0x2 << SPDIF_CFG1_TRIG_BIT)

-  #define SPDIF_CFG1_TRIG_32    (0x3 << SPDIF_CFG1_TRIG_BIT)

+#define SPDIF_CFG2_SAMWL_LSB	19

+#define SPDIF_CFG2_SAMWL_MASK	BITS_H2L(21, SPDIF_CFG2_SAMWL_LSB)

 

-#define SPDIF_CFG1_SRCNUM_BIT     8

-#define SPDIF_CFG1_SRCNUM_MASK    (0xf << SPDIF_CFG1_SRCNUM_BIT)

+#define SPDIF_CFG2_CLKACU_LSB	16

+#define SPDIF_CFG2_CLKACU_MASK	BITS_H2L(17, SPDIF_CFG2_CLKACU_LSB)

 

-#define SPDIF_CFG1_CH1NUM_BIT     4

-#define SPDIF_CFG1_CH1NUM_MASK    (0xf << SPDIF_CFG1_CH1NUM_BIT)

+#define SPDIF_CFG2_CATCODE_LSB	8

+#define SPDIF_CFG2_CATCODE_MASK	BITS_H2L(15, SPDIF_CFG2_CATCODE_LSB)

 

-#define SPDIF_CFG1_CH2NUM_BIT     0

-#define SPDIF_CFG1_CH2NUM_MASK    (0xf << SPDIF_CFG1_CH2NUM_BIT)

+#define SPDIF_CFG2_CHMD_LSB	6

+#define SPDIF_CFG2_CHMD_MASK	BITS_H2L(7, SPDIF_CFG2_CHMD_LSB)

 

-/* SPDIF Configure 2 Register (SPDIF_CFG2) */

+/* ICDC internal register access control register(RGADW) */

+#define ICDC_RGADW_RGWR		BIT16

 

-#define SPDIF_CFG2_FS_BIT       26

-#define SPDIF_CFG2_FS_MASK      (0xf << SPDIF_CFG2_FS_BIT)

-  #define SPDIF_CFG2_FS_44K     (0x0 << SPDIF_CFG2_FS_BIT) /* 44.1kHz */

-  #define SPDIF_CFG2_FS_48K     (0x2 << SPDIF_CFG2_FS_BIT)

-  #define SPDIF_CFG2_FS_32K     (0x3 << SPDIF_CFG2_FS_BIT)

-  #define SPDIF_CFG2_FS_96K     (0xa << SPDIF_CFG2_FS_BIT)

-  #define SPDIF_CFG2_FS_192K    (0xe << SPDIF_CFG2_FS_BIT)

+#define ICDC_RGADW_RGADDR_LSB	8

+#define	ICDC_RGADW_RGADDR_MASK	BITS_H2L(14, ICDC_RGADW_RGADDR_LSB)

 

-#define SPDIF_CFG2_ORGFRQ_BIT   22

-#define SPDIF_CFG2_ORGFRQ_MASK  (0xf << SPDIF_CFG2_ORGFRQ_BIT)

-  #define SPDIF_CFG2_ORGFRQ_44K     (0xf << SPDIF_CFG2_ORGFRQ_BIT) /* 44.1kHz */

-  #define SPDIF_CFG2_ORGFRQ_48K     (0xd << SPDIF_CFG2_ORGFRQ_BIT)

-  #define SPDIF_CFG2_ORGFRQ_32K     (0xc << SPDIF_CFG2_ORGFRQ_BIT)

-  #define SPDIF_CFG2_ORGFRQ_96K     (0x5 << SPDIF_CFG2_ORGFRQ_BIT)

-  #define SPDIF_CFG2_ORGFRQ_192K    (0x1 << SPDIF_CFG2_ORGFRQ_BIT)

+#define ICDC_RGADW_RGDIN_LSB	0

+#define	ICDC_RGADW_RGDIN_MASK	BITS_H2L(7, ICDC_RGADW_RGDIN_LSB)

 

-#define SPDIF_CFG2_SAMWL_BIT    19

-#define SPDIF_CFG2_SAMWL_MASK  (0x7 << SPDIF_CFG2_SAMWL_BIT)

+/* ICDC internal register data output register (RGDATA)*/

+#define ICDC_RGDATA_IRQ		BIT8

 

-#define SPDIF_CFG2_MAXWL        (1 << 18)

+#define ICDC_RGDATA_RGDOUT_LSB	0

+#define ICDC_RGDATA_RGDOUT_MASK	BITS_H2L(7, ICDC_RGDATA_RGDOUT_LSB)

 

-#define SPDIF_CFG2_CLKACU_BIT   16

-#define SPDIF_CFG2_CLKACU_MASK  (0x3 << SPDIF_CFG2_CLKACU_BIT)

-  #define SPDIF_CFG2_CLKACU_LVL2     (0x0 << SPDIF_CFG2_CLKACU_BIT)

-  #define SPDIF_CFG2_CLKACU_LVL1     (0x1 << SPDIF_CFG2_CLKACU_BIT)

-  #define SPDIF_CFG2_CLKACU_LVL3     (0x2 << SPDIF_CFG2_CLKACU_BIT)

-  #define SPDIF_CFG2_CLKACU_NOTMAT   (0x3 << SPDIF_CFG2_CLKACU_BIT)

 

-#define SPDIF_CFG2_CATCODE_BIT   8

-#define SPDIF_CFG2_CATCODE_MASK  (0xff << SPDIF_CFG2_CATCODE_BIT)

+#ifndef __MIPS_ASSEMBLER

 

-#define SPDIF_CFG2_CHMD_BIT   6

-#define SPDIF_CFG2_CHMD_MASK  (0x3 << SPDIF_CFG2_CHMD_BIT)

-  #define SPDIF_CFG2_CHMD_MOD0     (0x0 << SPDIF_CFG2_CHMD_BIT)

 

-#define SPDIF_CFG2_PRE        (1 << 3)

-#define SPDIF_CFG2_COPYN      (1 << 2)

-#define SPDIF_CFG2_AUDION     (1 << 1)

-#define SPDIF_CFG2_CONPRO     (1 << 0)

+#define	REG_AIC_FR		REG32(AIC_FR)

+#define	REG_AIC0_FR		REG32(AIC0_FR)

+#define	REG_AIC_CR		REG32(AIC_CR)

+#define	REG_AIC_ACCR1		REG32(AIC_ACCR1)

+#define	REG_AIC_ACCR2		REG32(AIC_ACCR2)

+#define	REG_AIC_I2SCR		REG32(AIC_I2SCR)

+#define	REG_AIC_SR		REG32(AIC_SR)

+#define	REG_AIC_ACSR		REG32(AIC_ACSR)

+#define	REG_AIC_I2SSR		REG32(AIC_I2SSR)

+#define	REG_AIC_ACCAR		REG32(AIC_ACCAR)

+#define	REG_AIC_ACCDR		REG32(AIC_ACCDR)

+#define	REG_AIC_ACSAR		REG32(AIC_ACSAR)

+#define	REG_AIC_ACSDR		REG32(AIC_ACSDR)

+#define	REG_AIC_I2SDIV		REG32(AIC_I2SDIV)

+#define	REG_AIC_DR		REG32(AIC_DR)

 

+#define REG_SPDIF_ENA		REG32(SPDIF_ENA)

+#define REG_SPDIF_CTRL		REG32(SPDIF_CTRL)

+#define REG_SPDIF_STATE		REG32(SPDIF_STATE)

+#define REG_SPDIF_CFG1		REG32(SPDIF_CFG1)

+#define REG_SPDIF_CFG2		REG32(SPDIF_CFG2)

+#define REG_SPDIF_FIFO		REG32(SPDIF_FIFO)

 

-#ifndef __MIPS_ASSEMBLER

+#define	REG_ICDC_RGADW		REG32(ICDC_RGADW)

+#define	REG_ICDC_RGDATA		REG32(ICDC_RGDATA)

 

-/***************************************************************************

- * AIC (AC'97 & I2S Controller)

- ***************************************************************************/

 

 #define __aic_enable()		( REG_AIC_FR |= AIC_FR_ENB )

 #define __aic_disable()		( REG_AIC_FR &= ~AIC_FR_ENB )

@@ -378,25 +336,25 @@ do {                                                    \
 #define __aic_set_transmit_trigger(n) 			\

 do {							\

 	REG_AIC_FR &= ~AIC_FR_TFTH_MASK;		\

-	REG_AIC_FR |= ((n) << AIC_FR_TFTH_BIT);		\

+	REG_AIC_FR |= ((n) << AIC_FR_TFTH_LSB);		\

 } while(0)

 

 #define __aic_set_receive_trigger(n) 			\

 do {							\

 	REG_AIC_FR &= ~AIC_FR_RFTH_MASK;		\

-	REG_AIC_FR |= ((n) << AIC_FR_RFTH_BIT);		\

+	REG_AIC_FR |= ((n) << AIC_FR_RFTH_LSB);		\

 } while(0)

 

-#define __aic_enable_oldstyle() ( REG_AIC_CR |= AIC_CR_EN2OLD )

-#define __aic_enable_newstyle() ( REG_AIC_CR &= ~AIC_CR_EN2OLD )

+#define __aic_enable_oldstyle()

+#define __aic_enable_newstyle()

 #define __aic_enable_pack16()   ( REG_AIC_CR |= AIC_CR_PACK16 )

-#define __aic_enable_unpack16() ( REG_AIC_CR &= ~AIC_CR_PACK16) 

+#define __aic_enable_unpack16() ( REG_AIC_CR &= ~AIC_CR_PACK16)

 

 /* n = AIC_CR_CHANNEL_MONO,AIC_CR_CHANNEL_STEREO ... */

 #define __aic_out_channel_select(n)                    \

 do {                                                   \

 	REG_AIC_CR &= ~AIC_CR_CHANNEL_MASK;            \

-        REG_AIC_CR |= ((n) << AIC_CR_CHANNEL_BIT );			       \

+        REG_AIC_CR |= ((n) << AIC_CR_CHANNEL_LSB );			       \

 } while(0)

 

 #define __aic_enable_record()	( REG_AIC_CR |= AIC_CR_EREC )

@@ -432,19 +390,19 @@ do {                                                   \
 #define __aic_enable_unsignadj()     ( REG_AIC_CR |= AIC_CR_AVSTSU )

 #define __aic_disable_unsignadj()    ( REG_AIC_CR &= ~AIC_CR_AVSTSU )

 

-#define AC97_PCM_XS_L_FRONT   	AIC_ACCR1_XS_SLOT3

-#define AC97_PCM_XS_R_FRONT   	AIC_ACCR1_XS_SLOT4

-#define AC97_PCM_XS_CENTER    	AIC_ACCR1_XS_SLOT6

-#define AC97_PCM_XS_L_SURR    	AIC_ACCR1_XS_SLOT7

-#define AC97_PCM_XS_R_SURR    	AIC_ACCR1_XS_SLOT8

-#define AC97_PCM_XS_LFE       	AIC_ACCR1_XS_SLOT9

+#define AC97_PCM_XS_L_FRONT   	AIC_ACCR1_XS_SLOT(3)

+#define AC97_PCM_XS_R_FRONT   	AIC_ACCR1_XS_SLOT(4)

+#define AC97_PCM_XS_CENTER    	AIC_ACCR1_XS_SLOT(6)

+#define AC97_PCM_XS_L_SURR    	AIC_ACCR1_XS_SLOT(7)

+#define AC97_PCM_XS_R_SURR    	AIC_ACCR1_XS_SLOT(8)

+#define AC97_PCM_XS_LFE       	AIC_ACCR1_XS_SLOT(9)

 

-#define AC97_PCM_RS_L_FRONT   	AIC_ACCR1_RS_SLOT3

-#define AC97_PCM_RS_R_FRONT   	AIC_ACCR1_RS_SLOT4

-#define AC97_PCM_RS_CENTER    	AIC_ACCR1_RS_SLOT6

-#define AC97_PCM_RS_L_SURR    	AIC_ACCR1_RS_SLOT7

-#define AC97_PCM_RS_R_SURR    	AIC_ACCR1_RS_SLOT8

-#define AC97_PCM_RS_LFE       	AIC_ACCR1_RS_SLOT9

+#define AC97_PCM_RS_L_FRONT   	AIC_ACCR1_RS_SLOT(3)

+#define AC97_PCM_RS_R_FRONT   	AIC_ACCR1_RS_SLOT(4)

+#define AC97_PCM_RS_CENTER    	AIC_ACCR1_RS_SLOT(6)

+#define AC97_PCM_RS_L_SURR    	AIC_ACCR1_RS_SLOT(7)

+#define AC97_PCM_RS_R_SURR    	AIC_ACCR1_RS_SLOT(8)

+#define AC97_PCM_RS_LFE       	AIC_ACCR1_RS_SLOT(9)

 

 #define __ac97_set_xs_none()	( REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK )

 #define __ac97_set_xs_mono() 						\

@@ -458,7 +416,7 @@ do {									\
 	REG_AIC_ACCR1 |= AC97_PCM_XS_L_FRONT | AC97_PCM_XS_R_FRONT;	\

 } while(0)

 

-/* In fact, only stereo is support now. */ 

+/* In fact, only stereo is support now. */

 #define __ac97_set_rs_none()	( REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK )

 #define __ac97_set_rs_mono() 						\

 do {									\

@@ -511,9 +469,9 @@ do {									\
 #define __i2s_out_channel_select(n) __aic_out_channel_select(n)

 

 #define __i2s_set_oss_sample_size(n) \

- ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_OSS_MASK) | AIC_CR_OSS_##n##BIT )

+ ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_OSS_MASK) | AIC_CR_OSS(n))

 #define __i2s_set_iss_sample_size(n) \

- ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_ISS_MASK) | AIC_CR_ISS_##n##BIT )

+ ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_ISS_MASK) | AIC_CR_ISS(n))

 

 #define __i2s_stop_bitclk()   ( REG_AIC_I2SCR |= AIC_I2SCR_STPBK )

 #define __i2s_start_bitclk()  ( REG_AIC_I2SCR &= ~AIC_I2SCR_STPBK )

@@ -526,9 +484,9 @@ do {									\
 #define __aic_clear_errors()      ( REG_AIC_SR &= ~(AIC_SR_TUR | AIC_SR_ROR) )

 

 #define __aic_get_transmit_resident() \

-  ( (REG_AIC_SR & AIC_SR_TFL_MASK) >> AIC_SR_TFL_BIT )

+  ( (REG_AIC_SR & AIC_SR_TFL_MASK) >> AIC_SR_TFL_LSB )

 #define __aic_get_receive_count() \

-  ( (REG_AIC_SR & AIC_SR_RFL_MASK) >> AIC_SR_RFL_BIT )

+  ( (REG_AIC_SR & AIC_SR_RFL_MASK) >> AIC_SR_RFL_LSB )

 

 #define __ac97_command_transmitted()     ( REG_AIC_ACSR & AIC_ACSR_CADT )

 #define __ac97_status_received()         ( REG_AIC_ACSR & AIC_ACSR_SADR )

@@ -540,33 +498,26 @@ do {									\
 

 #define __i2s_is_busy()         ( REG_AIC_I2SSR & AIC_I2SSR_BSY )

 

-#define CODEC_READ_CMD	        (1 << 19)

-#define CODEC_WRITE_CMD	        (0 << 19)

-#define CODEC_REG_INDEX_BIT     12

-#define CODEC_REG_INDEX_MASK	(0x7f << CODEC_REG_INDEX_BIT)	/* 18:12 */

-#define CODEC_REG_DATA_BIT      4

-#define CODEC_REG_DATA_MASK	(0x0ffff << 4)	/* 19:4 */

-

 #define __ac97_out_rcmd_addr(reg) 					\

 do { 									\

-    REG_AIC_ACCAR = CODEC_READ_CMD | ((reg) << CODEC_REG_INDEX_BIT); 	\

+    REG_AIC_ACCAR = AC97_READ_CMD | ((reg) << AC97_INDEX_LSB); 	\

 } while (0)

 

 #define __ac97_out_wcmd_addr(reg) 					\

 do { 									\

-    REG_AIC_ACCAR = CODEC_WRITE_CMD | ((reg) << CODEC_REG_INDEX_BIT); 	\

+    REG_AIC_ACCAR = AC97_WRITE_CMD | ((reg) << AC97_INDEX_LSB); 	\

 } while (0)

 

 #define __ac97_out_data(value) 						\

 do { 									\

-    REG_AIC_ACCDR = ((value) << CODEC_REG_DATA_BIT); 			\

+    REG_AIC_ACCDR = ((value) << AC97_DATA_LSB); 			\

 } while (0)

 

 #define __ac97_in_data() \

- ( (REG_AIC_ACSDR & CODEC_REG_DATA_MASK) >> CODEC_REG_DATA_BIT )

+ ( (REG_AIC_ACSDR & CODEC_REG_DATA_MASK) >> AC97_DATA_LSB )

 

 #define __ac97_in_status_addr() \

- ( (REG_AIC_ACSAR & CODEC_REG_INDEX_MASK) >> CODEC_REG_INDEX_BIT )

+ ( (REG_AIC_ACSAR & AC97_INDEX_MASK) >> AC97_INDEX_LSB )

 

 #define __i2s_set_sample_rate(i2sclk, sync) \

   ( REG_AIC_I2SDIV = ((i2sclk) / (4*64)) / (sync) )

@@ -574,8 +525,10 @@ do { 									\
 #define __aic_write_tfifo(v)  ( REG_AIC_DR = (v) )

 #define __aic_read_rfifo()    ( REG_AIC_DR )

 

-#define __aic_internal_codec()  ( REG_AIC_FR |= AIC_FR_ICDC ) 

+#define __aic_internal_codec()  ( REG_AIC_FR |= AIC_FR_ICDC )

 #define __aic_external_codec()  ( REG_AIC_FR &= ~AIC_FR_ICDC )

+#define __aic0_internal_codec()  ( REG_AIC0_FR |= AIC_FR_ICDC )

+#define __aic0_external_codec()  ( REG_AIC0_FR &= ~AIC_FR_ICDC )

 

 //

 // Define next ops for AC97 compatible

@@ -700,49 +653,49 @@ do { 									\
 #define __spdif_set_transmit_trigger(n)			\

 do {							\

 	REG_SPDIF_CFG1 &= ~SPDIF_CFG1_TRIG_MASK;	\

-	REG_SPDIF_CFG1 |= ((n) << SPDIF_CFG1_TRIG_BIT );	\

+	REG_SPDIF_CFG1 |= SPDIF_CFG1_TRIG(n);	\

 } while(0)

 

 /* 1 ~ 15 */

 #define __spdif_set_srcnum(n)    			\

 do {							\

 	REG_SPDIF_CFG1 &= ~SPDIF_CFG1_SRCNUM_MASK;	\

-	REG_SPDIF_CFG1 |= ((n) << SPDIF_CFG1_SRCNUM_BIT);	\

+	REG_SPDIF_CFG1 |= ((n) << SPDIF_CFG1_SRCNUM_LSB);	\

 } while(0)

 

 /* 1 ~ 15 */

 #define __spdif_set_ch1num(n)    			\

 do {							\

 	REG_SPDIF_CFG1 &= ~SPDIF_CFG1_CH1NUM_MASK;	\

-	REG_SPDIF_CFG1 |= ((n) << SPDIF_CFG1_CH1NUM_BIT);	\

+	REG_SPDIF_CFG1 |= ((n) << SPDIF_CFG1_CH1NUM_LSB);	\

 } while(0)

 

 /* 1 ~ 15 */

 #define __spdif_set_ch2num(n)    			\

 do {							\

 	REG_SPDIF_CFG1 &= ~SPDIF_CFG1_CH2NUM_MASK;	\

-	REG_SPDIF_CFG1 |= ((n) << SPDIF_CFG1_CH2NUM_BIT);	\

+	REG_SPDIF_CFG1 |= ((n) << SPDIF_CFG1_CH2NUM_LSB);	\

 } while(0)

 

 /* 0x0, 0x2, 0x3, 0xa, 0xe */

 #define __spdif_set_fs(n)				\

 do {							\

 	REG_SPDIF_CFG2 &= ~SPDIF_CFG2_FS_MASK;   	\

-	REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_FS_BIT);	\

+	REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_FS_LSB);	\

 } while(0)

 

 /* 0xd, 0xc, 0x5, 0x1 */

 #define __spdif_set_orgfrq(n)				\

 do {							\

 	REG_SPDIF_CFG2 &= ~SPDIF_CFG2_ORGFRQ_MASK;   	\

-	REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_ORGFRQ_BIT);	\

+	REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_ORGFRQ_LSB);	\

 } while(0)

 

 /* 0x1, 0x6, 0x2, 0x4, 0x5 */

 #define __spdif_set_samwl(n)				\

 do {							\

 	REG_SPDIF_CFG2 &= ~SPDIF_CFG2_SAMWL_MASK;   	\

-	REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_SAMWL_BIT);	\

+	REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_SAMWL_LSB);	\

 } while(0)

 

 #define __spdif_enable_samwl_24()    ( REG_SPDIF_CFG2 |= SPDIF_CFG2_MAXWL )

@@ -752,21 +705,21 @@ do {							\
 #define __spdif_set_clkacu(n)				\

 do {							\

 	REG_SPDIF_CFG2 &= ~SPDIF_CFG2_CLKACU_MASK;   	\

-	REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_CLKACU_BIT);	\

+	REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_CLKACU_LSB);	\

 } while(0)

 

 /* see IEC60958-3 */

 #define __spdif_set_catcode(n)				\

 do {							\

 	REG_SPDIF_CFG2 &= ~SPDIF_CFG2_CATCODE_MASK;   	\

-	REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_CATCODE_BIT);	\

+	REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_CATCODE_LSB);	\

 } while(0)

 

 /* n = 0x0, */

 #define __spdif_set_chmode(n)				\

 do {							\

 	REG_SPDIF_CFG2 &= ~SPDIF_CFG2_CHMD_MASK;   	\

-	REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_CHMD_BIT);	\

+	REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_CHMD_LSB);	\

 } while(0)

 

 #define __spdif_enable_pre()       ( REG_SPDIF_CFG2 |= SPDIF_CFG2_PRE )

@@ -797,13 +750,13 @@ do {							\
 #define __icdc_set_addr(n)				\

 do {          						\

 	REG_ICDC_RGADW &= ~ICDC_RGADW_RGADDR_MASK;	\

-	REG_ICDC_RGADW |= (n) << ICDC_RGADW_RGADDR_BIT;	\

+	REG_ICDC_RGADW |= (n) << ICDC_RGADW_RGADDR_LSB;	\

 } while(0)

 

 #define __icdc_set_cmd(n)				\

 do {          						\

 	REG_ICDC_RGADW &= ~ICDC_RGADW_RGDIN_MASK;	\

-	REG_ICDC_RGADW |= (n) << ICDC_RGADW_RGDIN_BIT;	\

+	REG_ICDC_RGADW |= (n) << ICDC_RGADW_RGDIN_LSB;	\

 } while(0)

 

 #define __icdc_irq_pending()            ( REG_ICDC_RGDATA & ICDC_RGDATA_IRQ )

@@ -813,5 +766,4 @@ do {          						\
 

 #endif /* __MIPS_ASSEMBLER */

 

-#endif /* __JZ4810AIC_H__ */

-

+#endif /* __CHIP_AIC_H__ */

diff --git a/arch/mips/include/asm/mach-jz4810/jz4810aosd.h b/arch/mips/include/asm/mach-jz4810/jz4810aosd.h
new file mode 100644
index 00000000000..899c2aac734
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4810/jz4810aosd.h
@@ -0,0 +1,107 @@
+/*

+ * linux/include/asm-mips/mach-jz4810/jz4810aosd.h

+ *

+ * JZ4810 ALPHA OSD register definition.

+ *

+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

+ */

+

+#ifndef __JZ4810AOSD_H__

+#define __JZ4810AOSD_H__

+

+#define AOSD_BASE        0xB3070000

+

+/*************************************************************************

+ * OSD (On Screen Display)

+ *************************************************************************/

+#define AOSD_ADDR0             (AOSD_BASE + 0x00)

+#define AOSD_ADDR1             (AOSD_BASE + 0x04)

+#define AOSD_ADDR2             (AOSD_BASE + 0x08)

+#define AOSD_ADDR3             (AOSD_BASE + 0x0C)

+#define AOSD_WADDR             (AOSD_BASE + 0x10)

+#define AOSD_ADDRLEN           (AOSD_BASE + 0x14)

+#define AOSD_ALPHA_VALUE       (AOSD_BASE + 0x18)

+#define AOSD_CTRL              (AOSD_BASE + 0x1C)

+#define AOSD_INT               (AOSD_BASE + 0x20)

+#define AOSD_CLK_GATE          (AOSD_BASE + 0x48)

+

+#define REG_AOSD_ADDR0         REG32(AOSD_ADDR0)

+#define REG_AOSD_ADDR1         REG32(AOSD_ADDR1)

+#define REG_AOSD_ADDR2         REG32(AOSD_ADDR2)

+#define REG_AOSD_ADDR3         REG32(AOSD_ADDR3)

+#define REG_AOSD_WADDR         REG32(AOSD_WADDR)

+#define REG_AOSD_ADDRLEN       REG32(AOSD_ADDRLEN)

+#define REG_AOSD_ALPHA_VALUE   REG32(AOSD_ALPHA_VALUE)

+#define REG_AOSD_CTRL          REG32(AOSD_CTRL)

+#define REG_AOSD_INT           REG32(AOSD_INT)

+#define REG_AOSD_CLK_GATE      REG32(AOSD_CLK_GATE)

+

+#define AOSD_CTRL_FRMLV_MASK        (0x3 << 18)

+#define AOSD_CTRL_FRMLV_2        (0x1 << 18)

+#define AOSD_CTRL_FRMLV_3        (0x2 << 18)

+#define AOSD_CTRL_FRMLV_4        (0x3 << 18)

+

+#define AOSD_CTRL_FRM_END        (1 << 17)

+#define AOSD_CTRL_ALPHA_START    (1 << 16)

+#define AOSD_CTRL_INT_MAKS            (1 << 15)

+#define AOSD_CTRL_CHANNEL_LEVEL_BIT    7

+#define AOSD_CTRL_CHANNEL_LEVEL_MASK   (0xff <<  AOSD_CTRL_CHANNEL_LEVEL_BIT)

+#define AOSD_CTRL_ALPHA_MODE_BIT       3

+#define AOSD_CTRL_ALPHA_MODE_MASK      (0xf << AOSD_CTRL_ALPHA_MODE_BIT)

+#define AOSD_CTRL_ALPHA_PIXEL_MODE     0

+#define AOSD_CTRL_ALPHA_FRAME_MODE     1

+

+#define AOSD_CTRL_FORMAT_MODE_BIT     1

+#define AOSD_CTRL_FORMAT_MODE_MASK     (0x3 << 1)

+#define AOSD_CTRL_RGB565_FORMAT_MODE   (0 << AOSD_CTRL_FORMAT_MODE_BIT)

+#define AOSD_CTRL_RGB555_FORMAT_MODE   (1 << AOSD_CTRL_FORMAT_MODE_BIT)

+#define AOSD_CTRL_RGB8888_FORMAT_MODE  (2 << AOSD_CTRL_FORMAT_MODE_BIT)

+

+#define AOSD_ALPHA_ENABLE        (1 << 0)

+

+#define AOSD_INT_COMPRESS_END   (1 << 1)

+#define AOSD_INT_AOSD_END        (1 << 0)

+

+#define AOSD_CLK_GATE_EN         (1 << 0)

+

+#define __osd_enable_alpha() 	(REG_AOSD_CTRL |= AOSD_ALPHA_ENABLE)

+#define __osd_alpha_start()     (REG_AOSD_CTRL |= AOSD_CTRL_ALPHA_START) 

+/*************************************************************************

+ * COMPRESS

+ *************************************************************************/

+

+#define COMPRESS_SCR_ADDR      (AOSD_BASE + 0x00)

+#define COMPRESS_DES_ADDR      (AOSD_BASE + 0x10)

+#define COMPRESS_OFFSIZE       (AOSD_BASE + 0x34)

+#define COMPRESS_FRAME_SIZE       (AOSD_BASE + 0x38)

+#define COMPRESS_CTRL       (AOSD_BASE + 0x3C)

+#define COMPRESS_RATIO      (AOSD_BASE + 0x40)

+#define COMPRESS_OFFSET     (AOSD_BASE + 0x44)

+#define COMPRESS_RESULT     (AOSD_BASE + 0x4C)

+ 

+#define REG_COMPRESS_SCR_ADDR      REG32(COMPRESS_SCR_ADDR)

+#define REG_COMPRESS_DES_ADDR      REG32(COMPRESS_DES_ADDR)

+#define REG_COMPRESS_OFFSIZE       REG32(COMPRESS_OFFSIZE)

+#define REG_COMPRESS_FRAME_SIZE       REG32(COMPRESS_FRAME_SIZE)

+#define REG_COMPRESS_CTRL       REG32(COMPRESS_CTRL)

+#define REG_COMPRESS_RATIO      REG32(COMPRESS_RATIO)

+#define REG_COMPRESS_OFFSET     REG32(COMPRESS_OFFSET)

+#define REG_COMPRESS_RESULT     REG32(COMPRESS_RESULT)

+

+#define COMPRESS_CTRL_WITHOUT_ALPHA     (1 << 4)

+#define COMPRESS_CTRL_WITH_ALPHA     (0 << 4)

+#define COMPRESS_CTRL_COMP_START   (1 << 3)

+#define COMPRESS_CTRL_COMP_END     (1 << 2)

+#define COMPRESS_CTRL_INT_MASK     (1 << 1)

+#define COMPRESS_CTRL_COMP_ENABLE  (1 << 0)

+

+#define COMPRESS_RATIO_FRM_BYPASS   (1 << 31)

+#define COMPRESS_BYPASS_ROW         (1 << 12)

+#define COMPRESS_ROW_QUARTER        (1 << 0)

+

+#define __compress_enable()       (REG_COMPRESS_CTRL |= COMPRESS_INT_AOSD_END)      

+#define __compress_start()        (REG_COMPRESS_CTRL |= COMPRESS_CTRL_COMP_START)      

+#define __compress_with_alpha()   (REG_COMPRESS_CTRL |= COMPRESS_CTRL_ALPHA_EN)      

+

+#endif /* __JZ4810AOSD_H__ */

+

diff --git a/arch/mips/include/asm/mach-jz4810/jz4810bch.h b/arch/mips/include/asm/mach-jz4810/jz4810bch.h
index 426c41ac23f..e2d5315984d 100644
--- a/arch/mips/include/asm/mach-jz4810/jz4810bch.h
+++ b/arch/mips/include/asm/mach-jz4810/jz4810bch.h
@@ -43,9 +43,9 @@
 #define	BCH_ERR10       (BCH_BASE + 0x64) /* BCH Error Report 10 register */

 #define	BCH_ERR11       (BCH_BASE + 0x68) /* BCH Error Report 11 register */

 #define	BCH_INTS    	(BCH_BASE + 0x6C) /* BCH Interrupt Status register */

-#define	BCH_INTES       (BCH_BASE + 0x70) /* BCH Interrupt Enable register */

-#define	BCH_INTEC       (BCH_BASE + 0x74) /* BCH Interrupt Set register */

-#define	BCH_INTE       	(BCH_BASE + 0x78) /* BCH Interrupt Clear register */

+#define	BCH_INTE	(BCH_BASE + 0x70) /* BCH Interrupt Enable register */

+#define	BCH_INTES       (BCH_BASE + 0x74) /* BCH Interrupt Set register */

+#define	BCH_INTEC	(BCH_BASE + 0x78) /* BCH Interrupt Clear register */

 

 #define	REG_BCH_CR      REG32(BCH_CR)

 #define	REG_BCH_CRS     REG32(BCH_CRS)

@@ -111,76 +111,88 @@
 #define BCH_CNT_ENC_MASK         (0x7ff << BCH_CNT_ENC_BIT)

 

 /* BCH Error Report Register */

-#define BCH_ERR_INDEX_ODD_BIT    0

+#define BCH_ERR_INDEX_ODD_BIT    16

 #define BCH_ERR_INDEX_ODD_MASK   (0x1fff << BCH_ERR_INDEX_ODD_BIT)

-#define BCH_ERR_INDEX_EVEN_BIT   16

+#define BCH_ERR_INDEX_EVEN_BIT   0

 #define BCH_ERR_INDEX_EVEN_MASK  (0x1fff << BCH_ERR_INDEX_EVEN_BIT)

-

+#define BCH_ERR_INDEX_MASK	 0x1fff

 

 #ifndef __MIPS_ASSEMBLER

 

 /*************************************************************************

  * BCH

  *************************************************************************/

-#define __ecc_encoding_4bit()                                   \

-do {				   		        	\

-	REG_BCH_CRS = BCH_CR_BSEL_4 | BCH_CR_ENCE | BCH_CR_BRST | BCH_CR_BCHE;  \

-	REG_BCH_CRC = ~(BCH_CR_BSEL_4 | BCH_CR_ENCE | BCH_CR_BRST | BCH_CR_BCHE); \

+#define __ecc_encoding_4bit()						\

+do {									\

+	REG_BCH_CRS = BCH_CR_BSEL_4 | BCH_CR_ENCE | BCH_CR_BCHE;	\

+	REG_BCH_CRC = ~(BCH_CR_BSEL_4 | BCH_CR_ENCE | BCH_CR_BCHE);	\

+	REG_BCH_CRS = BCH_CR_BRST;					\

 } while(0)

-#define __ecc_decoding_4bit()                           \

-do {                                                    \

-	REG_BCH_CRS = BCH_CR_BSEL_4 | BCH_CR_DECE | BCH_CR_BRST | BCH_CR_BCHE;	\

-	REG_BCH_CRC = ~(BCH_CR_BSEL_4 | BCH_CR_DECE | BCH_CR_BRST | BCH_CR_BCHE); \

+#define __ecc_decoding_4bit()						\

+do {									\

+	REG_BCH_CRS = BCH_CR_BSEL_4 | BCH_CR_DECE | BCH_CR_BCHE;	\

+	REG_BCH_CRC = ~(BCH_CR_BSEL_4 | BCH_CR_DECE | BCH_CR_BCHE);	\

+	REG_BCH_CRS = BCH_CR_BRST;					\

 } while(0)

-#define __ecc_encoding_8bit()                                                   \

-do {				   		                        	\

-	REG_BCH_CRS = BCH_CR_BSEL_8 | BCH_CR_ENCE | BCH_CR_BRST | BCH_CR_BCHE;   \

-	REG_BCH_CRC = ~(BCH_CR_BSEL_8 | BCH_CR_ENCE | BCH_CR_BRST | BCH_CR_BCHE); \

+#define __ecc_encoding_8bit()                                           \

+do {				   		                        \

+	REG_BCH_CRS = BCH_CR_BSEL_8 | BCH_CR_ENCE | BCH_CR_BCHE;	\

+	REG_BCH_CRC = ~(BCH_CR_BSEL_8 | BCH_CR_ENCE | BCH_CR_BCHE);	\

+	REG_BCH_CRS = BCH_CR_BRST;					\

 } while(0)

-#define __ecc_decoding_8bit()                                        \

-do {                                                                 \

-	REG_BCH_CRS = BCH_CR_BSEL_8 | BCH_CR_DECE | BCH_CR_BRST | BCH_CR_BCHE;	     \

-	REG_BCH_CRC = ~(BCH_CR_BSEL_8 | BCH_CR_DECE | BCH_CR_BRST | BCH_CR_BCHE); \

+#define __ecc_decoding_8bit()						\

+do {									\

+	REG_BCH_CRS = BCH_CR_BSEL_8 | BCH_CR_DECE | BCH_CR_BCHE;	\

+	REG_BCH_CRC = ~(BCH_CR_BSEL_8 | BCH_CR_DECE | BCH_CR_BCHE);	\

+	REG_BCH_CRS = BCH_CR_BRST;					\

 } while(0)

-#define __ecc_encoding_12bit()                                        \

-do {                                                                 \

-	REG_BCH_CRS = BCH_CR_BSEL_12 | BCH_CR_ENCE | BCH_CR_BRST | BCH_CR_BCHE;	     \

-	REG_BCH_CRC = ~(BCH_CR_BSEL_12 | BCH_CR_ENCE | BCH_CR_BRST | BCH_CR_BCHE); \

+#define __ecc_encoding_12bit()						\

+do {									\

+	REG_BCH_CRS = BCH_CR_BSEL_12 | BCH_CR_ENCE | BCH_CR_BCHE;	\

+	REG_BCH_CRC = ~(BCH_CR_BSEL_12 | BCH_CR_ENCE | BCH_CR_BCHE);	\

+	REG_BCH_CRS = BCH_CR_BRST;					\

 } while(0)

-#define __ecc_decoding_12bit()                                        \

-do {                                                                 \

-	REG_BCH_CRS = BCH_CR_BSEL_12 | BCH_CR_DECE | BCH_CR_BRST | BCH_CR_BCHE;	     \

-	REG_BCH_CRC = ~(BCH_CR_BSEL_12 | BCH_CR_DECE | BCH_CR_BRST | BCH_CR_BCHE); \

+#define __ecc_decoding_12bit()						\

+do {									\

+	REG_BCH_CRS = BCH_CR_BSEL_12 | BCH_CR_DECE | BCH_CR_BCHE;	\

+	REG_BCH_CRC = ~(BCH_CR_BSEL_12 | BCH_CR_DECE | BCH_CR_BCHE);	\

+	REG_BCH_CRS = BCH_CR_BRST;					\

 } while(0)

-#define __ecc_encoding_16bit()                                        \

-do {                                                                 \

-	REG_BCH_CRS = BCH_CR_BSEL_16 | BCH_CR_ENCE | BCH_CR_BRST | BCH_CR_BCHE;	     \

-	REG_BCH_CRC = ~(BCH_CR_BSEL_16 | BCH_CR_ENCE | BCH_CR_BRST | BCH_CR_BCHE); \

+#define __ecc_encoding_16bit()						\

+do {									\

+	REG_BCH_CRS = BCH_CR_BSEL_16 | BCH_CR_ENCE | BCH_CR_BCHE;	\

+	REG_BCH_CRC = ~(BCH_CR_BSEL_16 | BCH_CR_ENCE | BCH_CR_BCHE);	\

+	REG_BCH_CRS = BCH_CR_BRST;					\

 } while(0)

-#define __ecc_decoding_16bit()                                        \

-do {                                                                 \

-	REG_BCH_CRS = BCH_CR_BSEL_16 | BCH_CR_DECE | BCH_CR_BRST | BCH_CR_BCHE;	     \

-	REG_BCH_CRC = ~(BCH_CR_BSEL_16 | BCH_CR_DECE | BCH_CR_BRST | BCH_CR_BCHE); \

+#define __ecc_decoding_16bit()						\

+do {									\

+	REG_BCH_CRS = BCH_CR_BSEL_16 | BCH_CR_DECE | BCH_CR_BCHE;	\

+	REG_BCH_CRC = ~(BCH_CR_BSEL_16 | BCH_CR_DECE | BCH_CR_BCHE);	\

+	REG_BCH_CRS = BCH_CR_BRST;					\

 } while(0)

-#define __ecc_encoding_20bit()                                        \

-do {                                                                 \

-	REG_BCH_CRS = BCH_CR_BSEL_20 | BCH_CR_ENCE | BCH_CR_BRST | BCH_CR_BCHE;	     \

-	REG_BCH_CRC = ~(BCH_CR_BSEL_20 | BCH_CR_ENCE | BCH_CR_BRST | BCH_CR_BCHE); \

+#define __ecc_encoding_20bit()						\

+do {									\

+	REG_BCH_CRS = BCH_CR_BSEL_20 | BCH_CR_ENCE | BCH_CR_BCHE;	\

+	REG_BCH_CRC = ~(BCH_CR_BSEL_20 | BCH_CR_ENCE | BCH_CR_BCHE);	\

+	REG_BCH_CRS = BCH_CR_BRST;					\

 } while(0)

-#define __ecc_decoding_20bit()                                        \

-do {                                                                 \

-	REG_BCH_CRS = BCH_CR_BSEL_20 | BCH_CR_DECE | BCH_CR_BRST | BCH_CR_BCHE;	     \

-	REG_BCH_CRC = ~(BCH_CR_BSEL_20 | BCH_CR_DECE | BCH_CR_BRST | BCH_CR_BCHE); \

+#define __ecc_decoding_20bit()						\

+do {									\

+	REG_BCH_CRS = BCH_CR_BSEL_20 | BCH_CR_DECE | BCH_CR_BCHE;	\

+	REG_BCH_CRC = ~(BCH_CR_BSEL_20 | BCH_CR_DECE | BCH_CR_BCHE);	\

+	REG_BCH_CRS = BCH_CR_BRST;					\

 } while(0)

-#define __ecc_encoding_24bit()                                        \

-do {                                                                 \

-	REG_BCH_CRS = BCH_CR_BSEL_24 | BCH_CR_ENCE | BCH_CR_BRST | BCH_CR_BCHE;	     \

-	REG_BCH_CRC = ~(BCH_CR_BSEL_24 | BCH_CR_ENCE | BCH_CR_BRST | BCH_CR_BCHE); \

+#define __ecc_encoding_24bit()						\

+do {									\

+	REG_BCH_CRS = BCH_CR_BSEL_24 | BCH_CR_ENCE | BCH_CR_BCHE;	\

+	REG_BCH_CRC = ~(BCH_CR_BSEL_24 | BCH_CR_ENCE | BCH_CR_BCHE);	\

+	REG_BCH_CRS = BCH_CR_BRST;					\

 } while(0)

-#define __ecc_decoding_24bit()                                        \

-do {                                                                 \

-	REG_BCH_CRS = BCH_CR_BSEL_24 | BCH_CR_DECE | BCH_CR_BRST | BCH_CR_BCHE;	     \

-	REG_BCH_CRC = ~(BCH_CR_BSEL_24 | BCH_CR_DECE | BCH_CR_BRST | BCH_CR_BCHE); \

+#define __ecc_decoding_24bit()						\

+do {									\

+	REG_BCH_CRS = BCH_CR_BSEL_24 | BCH_CR_DECE | BCH_CR_BCHE;	\

+	REG_BCH_CRC = ~(BCH_CR_BSEL_24 | BCH_CR_DECE | BCH_CR_BCHE);	\

+	REG_BCH_CRS = BCH_CR_BRST;					\

 } while(0)

 #define __ecc_dma_enable()        ( REG_BCH_CRS = BCH_CR_DMAE )

 #define __ecc_dma_disable()       ( REG_BCH_CRC = BCH_CR_DMAE )

@@ -190,17 +202,14 @@ do {                                                                 \
 

 #define __ecc_cnt_dec(n)                                             \

 do {						               	     \

-        REG_BCH_CNT &= ~BCH_CNT_DEC_MASK;			      \

-        REG_BCH_CNT |= (n) << BCH_CNT_DEC_BIT;                        \

+        REG_BCH_CNT = (n) << BCH_CNT_DEC_BIT;                        \

 } while(0)

+

 #define __ecc_cnt_enc(n)                                             \

 do {                                                                 \

-        REG_BCH_CNT &= ~BCH_CNT_ENC_MASK;			      \

-        REG_BCH_CNT |= (n) << BCH_CNT_ENC_BIT;                        \

+        REG_BCH_CNT = (n) << BCH_CNT_ENC_BIT;                        \

 } while(0)

 

-

-

 #endif /* __MIPS_ASSEMBLER */

 

 #endif /* __JZ4810BCH_H__ */

diff --git a/arch/mips/include/asm/mach-jz4810/jz4810bdma.h b/arch/mips/include/asm/mach-jz4810/jz4810bdma.h
index fa9e558b2a3..19f96b26b34 100644
--- a/arch/mips/include/asm/mach-jz4810/jz4810bdma.h
+++ b/arch/mips/include/asm/mach-jz4810/jz4810bdma.h
@@ -28,11 +28,13 @@
 #define BDMAC_DSD(n)   		(BDMAC_BASE + (0x1c + (n) * 0x20)) /* DMA Stride Address */

 #define BDMAC_DNT(n)  		(BDMAC_BASE + (0xc0 + (n) * 0x04)) /* NAND Detect Timer */

 

-#define BDMAC_DMACR			(BDMAC_BASE + 0x0300) 	/* DMA control register */

+#define BDMAC_DMACR		(BDMAC_BASE + 0x0300) 	/* DMA control register */

 #define BDMAC_DMAIPR		(BDMAC_BASE + 0x0304) 	/* DMA interrupt pending */

 #define BDMAC_DMADBR		(BDMAC_BASE + 0x0308) 	/* DMA doorbell */

 #define BDMAC_DMADBSR		(BDMAC_BASE + 0x030C) 	/* DMA doorbell set */

 #define BDMAC_DMACKE  		(BDMAC_BASE + 0x0310)

+#define BDMAC_DMACKES  		(BDMAC_BASE + 0x0314)

+#define BDMAC_DMACKEC  		(BDMAC_BASE + 0x0318)

 

 #define REG_BDMAC_DSAR(n)	REG32(BDMAC_DSAR((n)))

 #define REG_BDMAC_DTAR(n)	REG32(BDMAC_DTAR((n)))

@@ -49,26 +51,43 @@
 #define REG_BDMAC_DMADBR	REG32(BDMAC_DMADBR)

 #define REG_BDMAC_DMADBSR	REG32(BDMAC_DMADBSR)

 #define REG_BDMAC_DMACKE    REG32(BDMAC_DMACKE)

+#define REG_BDMAC_DMACKES    REG32(BDMAC_DMACKES)

+#define REG_BDMAC_DMACKEC    REG32(BDMAC_DMACKEC)

+

+//BDMA nand detect timer register

+#define BDMAC_DNTR_DNTE          (1 << 15)  /* Nand request 0 detect timer enable */

+#define BDMAC_DNTR_DNT(n)        ((n) << 0) /* Nand request 0 detect timer value */

+#define BDMAC_DNTR_DNTE1          (1 << 31)  /* Nand request 1 detect timer enable */

+#define BDMAC_DNTR_DNT1(n)        ((n) << 23) /* Nand request 1 detect timer value */

+

 

 // BDMA request source register

 #define BDMAC_DRSR_RS_BIT	0

-  #define BDMAC_DRSR_RS_MASK	(0x3f << DMAC_DRSR_RS_BIT)

-  #define BDMAC_DRSR_RS_NAND	(1 << DMAC_DRSR_RS_BIT)

-  #define BDMAC_DRSR_RS_BCH_ENC	(2 << DMAC_DRSR_RS_BIT)

-  #define BDMAC_DRSR_RS_BCH_DEC	(3 << DMAC_DRSR_RS_BIT)

-  #define BDMAC_DRSR_RS_AUTO	(8 << DMAC_DRSR_RS_BIT)

-  #define BDMAC_DRSR_RS_EXT	(12 << DMAC_DRSR_RS_BIT)

+#define BDMAC_DRSR_RS_MASK	(0x3f << DMAC_DRSR_RS_BIT)

+#define BDMAC_DRSR_RS_BCH_ENC	(2 << DMAC_DRSR_RS_BIT)

+#define BDMAC_DRSR_RS_BCH_DEC	(3 << DMAC_DRSR_RS_BIT)

+#define BDMAC_DRSR_RS_NAND0	(6 << DMAC_DRSR_RS_BIT)

+#define BDMAC_DRSR_RS_NAND1	(7 << DMAC_DRSR_RS_BIT)

+#define BDMAC_DRSR_RS_AUTO	(8 << DMAC_DRSR_RS_BIT)

+#define BDMAC_DRSR_RS_EXT	(12 << DMAC_DRSR_RS_BIT)

 

 // BDMA channel control/status register

 #define BDMAC_DCCSR_NDES	(1 << 31) /* descriptor (0) or not (1) ? */

 #define BDMAC_DCCSR_DES8    	(1 << 30) /* Descriptor 8 Word */

 #define BDMAC_DCCSR_DES4    	(0 << 30) /* Descriptor 4 Word */

+#define BDMAC_DCCSR_LASTMD0    	(0 << 28) /* BCH Decoding last mode 0, there's one descriptor for decoding blcok*/

+#define BDMAC_DCCSR_LASTMD1    	(1 << 28) /* BCH Decoding last mode 1, there's two descriptor for decoding blcok*/

+#define BDMAC_DCCSR_LASTMD2    	(2 << 28) /* BCH Decoding last mode 2, there's three descriptor for decoding blcok*/

+#define BDMAC_DCCSR_FRBS(n)	((n) << 24)

 #define BDMAC_DCCSR_CDOA_BIT	16        /* copy of DMA offset address */

-  #define BDMAC_DCCSR_CDOA_MASK	(0xff << BDMACC_DCCSR_CDOA_BIT)

-#define BDMAC_DCCSR_BERR	(1 << 7)  /* BCH error within this transfer, Only for channel 0 */

+#define BDMAC_DCCSR_CDOA_MASK	(0xff << BDMACC_DCCSR_CDOA_BIT)

+#define BDMAC_DCCSR_BERR	(0x1f << 7)  /* BCH error within this transfer, Only for channel 0 */

+#define BDMAC_DCCSR_BUERR       (1 << 5)  /* BCH uncorrectable error, only for channel 0 */

+#define BDMAC_DCCSR_NSERR       (1 << 5)  /* status error, only for channel 1 */

 #define BDMAC_DCCSR_AR		(1 << 4)  /* address error */

 #define BDMAC_DCCSR_TT		(1 << 3)  /* transfer terminated */

 #define BDMAC_DCCSR_HLT		(1 << 2)  /* DMA halted */

+#define BDMAC_DCCSR_BAC		(1 << 1)  /* BCH auto correction */

 #define BDMAC_DCCSR_EN		(1 << 0)  /* channel enable bit */

 

 // BDMA channel command register

@@ -106,6 +125,7 @@
 #define BDMAC_DCMD_NRD   	(1 << 7)  /* NAND direct read */

 #define BDMAC_DCMD_NWR   	(1 << 6)  /* NAND direct write */

 #define BDMAC_DCMD_NAC   	(1 << 5)  /* NAND AL/CL enable */

+#define BDMAC_DCMD_NSTA		(1 << 4)  /* Nand Status Transfer Enable */

 #define BDMAC_DCMD_STDE   	(1 << 2)  /* Stride Disable/Enable */

 #define BDMAC_DCMD_TIE		(1 << 1)  /* DMA transfer interrupt enable */

 #define BDMAC_DCMD_LINK		(1 << 0)  /* descriptor link enable */

@@ -191,7 +211,10 @@ do {                                             \
   (  REG_BDMAC_DCCSR((n)) & BDMAC_DCCSR_HLT )

 #define __bdmac_channel_transmit_end_detected(n) \

   (  REG_BDMAC_DCCSR((n)) & BDMAC_DCCSR_TT )

-#define __bdmac_channel_address_error_detected(n) \

+/* Nand ops status error, only for channel 1 */

+#define __bdmac_channel_status_error_detected() \

+  (  REG_BDMAC_DCCSR(1) & BDMAC_DCCSR_NSERR )

+#define __bdmac_channel_address_error_detected(n)	\

   (  REG_BDMAC_DCCSR((n)) & BDMAC_DCCSR_AR )

 #define __bdmac_channel_count_terminated_detected(n) \

   (  REG_BDMAC_DCCSR((n)) & BDMAC_DCCSR_CT )

@@ -208,6 +231,8 @@ do {                                             \
 	} while (0)

 #define __bdmac_channel_clear_transmit_end(n) \

   (  REG_BDMAC_DCCSR(n) &= ~BDMAC_DCCSR_TT )

+#define __bdmac_channel_clear_status_error() \

+  ( REG_BDMAC_DCCSR(1) &= ~BDMAC_DCCSR_NSERR )

 #define __bdmac_channel_clear_address_error(n)				\

 	do {								\

 		REG_BDMAC_DDA(n) = 0; /* clear descriptor address register */ \

diff --git a/arch/mips/include/asm/mach-jz4810/jz4810cim.h b/arch/mips/include/asm/mach-jz4810/jz4810cim.h
index 47279adfd87..38b49d48098 100644
--- a/arch/mips/include/asm/mach-jz4810/jz4810cim.h
+++ b/arch/mips/include/asm/mach-jz4810/jz4810cim.h
@@ -1,13 +1,13 @@
 /*

- * linux/include/asm-mips/mach-jz4810/jz4810cim.h

+ * linux/include/asm-mips/mach-jz4760/jz4760cim.h

  *

- * JZ4810 CIM register definition.

+ * JZ4760 CIM register definition.

  *

  * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

  */

 

-#ifndef __JZ4810CIM_H__

-#define __JZ4810CIM_H__

+#ifndef __JZ4760CIM_H__

+#define __JZ4760CIM_H__

 

 

 #define	CIM_BASE	0xB3060000

@@ -26,10 +26,18 @@
 #define	CIM_CMD			(CIM_BASE + 0x002C)

 #define	CIM_SIZE		(CIM_BASE + 0x0030)

 #define	CIM_OFFSET		(CIM_BASE + 0x0034)

+#define CIM_YFA			(CIM_BASE + 0x0038)

+#define CIM_YCMD		(CIM_BASE + 0x003C)

+#define CIM_CBFA		(CIM_BASE + 0x0040)

+#define CIM_CBCMD		(CIM_BASE + 0x0044)

+#define CIM_CRFA		(CIM_BASE + 0x0048)

+#define CIM_CRCMD		(CIM_BASE + 0x004C)

+#define CIM_CTRL2		(CIM_BASE + 0x0050)

 #define	CIM_RAM_ADDR		(CIM_BASE + 0x1000)

 

 #define	REG_CIM_CFG		REG32(CIM_CFG)

 #define	REG_CIM_CTRL		REG32(CIM_CTRL)

+#define REG_CIM_CTRL2		REG32(CIM_CTRL2)

 #define	REG_CIM_STATE		REG32(CIM_STATE)

 #define	REG_CIM_IID		REG32(CIM_IID)

 #define	REG_CIM_RXFIFO		REG32(CIM_RXFIFO)

@@ -39,7 +47,16 @@
 #define	REG_CIM_CMD		REG32(CIM_CMD)

 #define	REG_CIM_SIZE		REG32(CIM_SIZE)

 #define	REG_CIM_OFFSET		REG32(CIM_OFFSET)

-

+#define REG_CIM_YFA		REG32(CIM_YFA)

+#define REG_CIM_YCMD		REG32(CIM_YCMD)

+#define REG_CIM_CBFA		REG32(CIM_CBFA)

+#define REG_CIM_CBCMD		REG32(CIM_CBCMD)

+#define REG_CIM_CRFA		REG32(CIM_CRFA)

+#define REG_CIM_CRCMD		REG32(CIM_CRCMD)

+

+#define CIM_CFG_RXF_TRIG_BIT	24

+#define CIM_CFG_RXF_TRIG_MASK	(0x3f << CIM_CFG_RT_TRIG_MASK)

+#define CIM_CFG_SEP		(1 << 20)

 #define	CIM_CFG_ORDER_BIT	18

 #define	CIM_CFG_ORDER_MASK	(0x3 << CIM_CFG_ORDER_BIT)

   #define CIM_CFG_ORDER_0	  (0x0 << CIM_CFG_ORDER_BIT) 	/* Y0CbY1Cr; YCbCr */

@@ -60,6 +77,7 @@
   #define	CIM_CFG_DMA_BURST_INCR4		(0 << CIM_CFG_DMA_BURST_TYPE_BIT)

   #define	CIM_CFG_DMA_BURST_INCR8		(1 << CIM_CFG_DMA_BURST_TYPE_BIT)	/* Suggested */

   #define	CIM_CFG_DMA_BURST_INCR16	(2 << CIM_CFG_DMA_BURST_TYPE_BIT)	/* Suggested High speed AHB*/

+  #define	CIM_CFG_DMA_BURST_INCR32	(3 << CIM_CFG_DMA_BURST_TYPE_BIT)	/* Suggested High speed AHB*/

 #define	CIM_CFG_DUMMY_ZERO	(1 << 9)

 #define	CIM_CFG_EXT_VSYNC	(1 << 8)	/* Only for ITU656 Progressive mode */

 #define	CIM_CFG_PACK_BIT	4

@@ -103,7 +121,7 @@
   #define CIM_CTRL_FRC_15	  (0xE << CIM_CTRL_FRC_BIT) /* Sample 1/15 frame */

   #define CIM_CTRL_FRC_16	  (0xF << CIM_CTRL_FRC_BIT) /* Sample 1/16 frame */

 

-#define	CIM_CTRL_DMA_EEOF	(1 << 15)	/* Enable EEOF interrupt */

+#define	CIM_CTRL_DMA_EEOFM	(1 << 15)	/* Enable EEOF interrupt */

 #define	CIM_CTRL_WIN_EN		(1 << 14)

 #define	CIM_CTRL_VDDM		(1 << 13) /* VDD interrupt enable */

 #define	CIM_CTRL_DMA_SOFM	(1 << 12)

@@ -119,7 +137,27 @@
 #define	CIM_CTRL_RXF_RST	(1 << 1) /* RxFIFO reset */

 #define	CIM_CTRL_ENA		(1 << 0) /* Enable CIM */

 

+

+/* cim control2 */

+#define CIM_CTRL2_OPG_BIT	4

+#define CIM_CTRL2_OPG_MASK	(0x3 << CIM_CTRL2_OPG_BIT)

+#define CIM_CTRL2_OPE		(1 << 2)

+#define CIM_CTRL2_EME		(1 << 1)

+#define CIM_CTRL2_APM		(1 << 0)

+

 /* CIM State Register  (CIM_STATE) */

+#define CIM_STATE_CR_RF_OF	(1 << 27)

+#define CIM_STATE_CR_RF_TRIG	(1 << 26)

+#define CIM_STATE_CR_RF_EMPTY	(1 << 25)

+

+#define CIM_STATE_CB_RF_OF	(1 << 19)

+#define CIM_STATE_CB_RF_TRIG	(1 << 18)

+#define CIM_STATE_CB_RF_EMPTY	(1 << 17)

+

+#define CIM_STATE_Y_RF_OF	(1 << 11)

+#define CIM_STATE_Y_RF_TRIG	(1 << 10)

+#define CIM_STATE_Y_RF_EMPTY	(1 << 9)

+

 #define	CIM_STATE_DMA_EEOF	(1 << 7) /* DMA Line EEOf irq */

 #define	CIM_STATE_DMA_SOF	(1 << 6) /* DMA start irq */

 #define	CIM_STATE_DMA_EOF	(1 << 5) /* DMA end irq */

@@ -151,7 +189,6 @@
 #define	CIM_OFFSET_H_BIT	0 /* Horizontal offset, should be an enen number */

 #define	CIM_OFFSET_H_MASK	(0xfff << CIM_OFFSET_H_BIT) /*OFFSET_H should be even number*/

 

-

 #ifndef __MIPS_ASSEMBLER

 

 /***************************************************************************

@@ -161,6 +198,9 @@
 #define __cim_enable()	( REG_CIM_CTRL |= CIM_CTRL_ENA )

 #define __cim_disable()	( REG_CIM_CTRL &= ~CIM_CTRL_ENA )

 

+#define __cim_enable_sep() (REG_CIM_CFG |= CIM_CFG_SEP)

+#define __cim_disable_sep() (REG_CIM_CFG &= ~CIM_CFG_SEP)

+

 /* n = 0, 1, 2, 3 */

 #define __cim_set_input_data_stream_order(n)				\

 	do {								\

@@ -262,9 +302,9 @@ do {						\
 } while (0)

 

 #define __cim_enable_size_func() \

-	( REG_CIM_CTRL |= CIM_CTRL_SIZEEN )

+	( REG_CIM_CTRL |= CIM_CTRL_WIN_EN)

 #define __cim_disable_size_func() \

-	( REG_CIM_CTRL &= ~CIM_CTRL_SIZEEN_MASK )

+	( REG_CIM_CTRL &= ~CIM_CTRL_WIN_EN )

 

 #define __cim_enable_vdd_intr() \

 	( REG_CIM_CTRL |= CIM_CTRL_VDDM )

@@ -302,11 +342,19 @@ do {						\
 	( REG_CIM_CTRL &= ~CIM_CTRL_RXF_OFM )

 

 /* n=4,8,12,16,20,24,28,32 */

-#define __cim_set_rxfifo_trigger(n) 		\

-do {						\

-	REG_CIM_CTRL &= ~CIM_CTRL_RXF_TRIG_MASK; 	\

-	REG_CIM_CTRL |= CIM_CTRL_RXF_TRIG_##n;		\

-} while (0)

+#define __cim_set_rxfifo_trigger(n)				\

+	do {							\

+		REG_CIM_CTRL &= ~CIM_CTRL_RXF_TRIG_MASK; 	\

+		REG_CIM_CTRL |= CIM_CTRL_RXF_TRIG_##n;		\

+	} while (0)

+

+

+#define __cim_set_eeof_line(n)						\

+	do {								\

+		REG_CIM_CTRL &= ~CIM_CTRL_EEOF_LINE_MASK;		\

+		REG_CIM_CTRL |= ( ((n) << CIM_CTRL_EEOF_LINE_BIT) & CIM_CTRL_EEOF_LINE_MASK ); \

+	} while (0)

+

 #define __cim_enable_fast_mode() 	( REG_CIM_CTRL |= CIM_CTRL_FAST_MODE )

 #define __cim_disable_fast_mode() 	( REG_CIM_CTRL &= ~CIM_CTRL_FAST_MODE )

 #define __cim_use_normal_mode() 	__cim_disable_fast_mode()

@@ -315,6 +363,25 @@ do {						\
 #define __cim_reset_rxfifo() ( REG_CIM_CTRL |= CIM_CTRL_RXF_RST )

 #define __cim_unreset_rxfifo() ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_RST )

 

+/* cim control2 */

+#define __cim_enable_priority_control()		( REG_CIM_CTRL2 |= CIM_CTRL2_APM)

+#define __cim_disable_priority_control()	( REG_CIM_CTRL2 &= ~CIM_CTRL2_APM)

+#define __cim_enable_auto_priority()		( REG_CIM_CTRL2 |= CIM_CTRL2_OPE)

+#define __cim_disable_auto_priority()		( REG_CIM_CTRL2 &= ~CIM_CTRL2_OPE)

+#define __cim_enable_emergency()		( REG_CIM_CTRL2 |= CIM_CTRL2_EME)

+#define __cim_disable_emergency()		( REG_CIM_CTRL2 &= ~CIM_CTRL2_EME);

+/* 0, 1, 2, 3

+ * 0: highest priority

+ * 3: lowest priority

+ * 1 maybe best for SEP=1

+ * 3 maybe best for SEP=0

+ */

+#define __cim_set_opg(n)				\

+	do {								\

+		REG_CIM_CTRL2 &= ~CIM_CTRL2_OPG_MASK;			\

+		REG_CIM_CTRL2 |= ((n) << CIM_CTRL2_OPG_BIT) & CIM_CTRL2_OPG_MASK; \

+	} while (0)

+

 #define __cim_clear_state()   	     ( REG_CIM_STATE = 0 )

 

 #define __cim_disable_done()   	     ( REG_CIM_STATE & CIM_STATE_VDD )

@@ -347,5 +414,4 @@ do {						\
 

 #endif /* __MIPS_ASSEMBLER */

 

-#endif /* __JZ4810CIM_H__ */

-

+#endif /* __JZ4760CIM_H__ */

diff --git a/arch/mips/include/asm/mach-jz4810/jz4810cpm.h b/arch/mips/include/asm/mach-jz4810/jz4810cpm.h
index 0dd45aba6d0..102af860f82 100644
--- a/arch/mips/include/asm/mach-jz4810/jz4810cpm.h
+++ b/arch/mips/include/asm/mach-jz4810/jz4810cpm.h
@@ -79,6 +79,104 @@
 #define REG_CPM_CLKGR1		REG32(CPM_CLKGR1)

 #define REG_CPM_CLKGR		REG32(CPM_CLKGR0)

 

+#ifndef __MIPS_ASSEMBLER

+

+typedef enum {

+        CGM_NEMC = 0,

+        CGM_BCH  = 1,

+        CGM_OTG  = 2,

+        CGM_MSC0 = 3,

+        CGM_SSI0 = 4,

+        CGM_I2C0 = 5,

+        CGM_I2C1 = 6,

+        CGM_SCC  = 7,

+        CGM_AIC         = 8,

+        CGM_TSSI        = 9,

+        CGM_OWI         = 10,

+        CGM_MSC1        = 11,

+        CGM_MSC2        = 12,

+        CGM_KBC         = 13,

+        CGM_SADC        = 14,

+        CGM_UART0       = 15,

+        CGM_UART1 = 16,

+        CGM_UART2 = 17,

+        CGM_UART3 = 18,

+        CGM_SSI1  = 19,

+        CGM_SSI2  = 20,

+        CGM_DMAC  = 21,

+        CGM_GPS   = 22,

+        CGM_MAC   = 23,

+        CGM_UHC         = 24,

+        CGM_MDMA        = 25,

+        CGM_CIM         = 26,

+        CGM_TVE         = 27,

+        CGM_LCD         = 28,

+        CGM_IPU         = 29,

+        CGM_DDR         = 30,

+        CGM_EMC         = 31,

+        CGM_BDMA  = 32 + 0,

+        CGM_MC    = 32 + 1,

+        CGM_DBLK  = 32 + 2,

+        CGM_ME    = 32 + 3,

+        CGM_DCT   = 32 + 4,

+        CGM_SRAM  = 32 + 5,

+        CGM_CABAC = 32 + 6,

+        CGM_AHB1  = 32 + 7,

+        CGM_PCM         = 32 + 8,

+        CGM_GPU         = 32 + 9,

+        CGM_ALL_MODULE,

+} clock_gate_module;

+

+

+#define __CGU_CLOCK_BASE__      0x1000

+

+typedef enum {

+        /* Clock source is pll0 */

+        CGU_CCLK = __CGU_CLOCK_BASE__ + 0,

+        CGU_HCLK,

+        CGU_PCLK,

+        CGU_MCLK,

+        CGU_H2CLK,

+        CGU_SCLK,

+

+        /* Clock source is exclk, pll0 or pll0/2 */

+        CGU_MSCCLK,

+        CGU_SSICLK,

+

+        /* Clock source is pll0 or pll0/2 */

+        CGU_CIMCLK,

+

+        /* Clock source is exclk, pll0, pll0/2 or pll1 */

+        CGU_TVECLK,

+

+        /* Clock source is pll0 */

+        CGU_LPCLK,

+

+        /* Clock source is exclk, exclk/2, pll0, pll0/2 or pll1 */

+        CGU_I2SCLK,

+        CGU_PCMCLK,

+        CGU_OTGCLK,

+

+        /* Clock source is pll0, pll0/2 or pll1 */

+        CGU_UHCCLK,

+        CGU_GPSCLK,

+        CGU_GPUCLK,

+

+        /* Clock source is exclk or exclk/2 */

+        CGU_UARTCLK,

+        CGU_SADCCLK,

+

+        /* Clock source is exclk */

+        CGU_TCUCLK,

+

+	/* Clock source is external rtc clock */

+	CGU_RTCCLK,

+

+        CGU_CLOCK_MAX,

+} cgu_clock;

+#endif

+

+

 /* Clock control register */

 #define CPM_CPCCR_ECS			(1 << 31)

 #define CPM_CPCCR_MEM			(1 << 30)

@@ -163,16 +261,16 @@
 #define CPM_USBPCR_OTG_DISABLE		(1 << 20)

 #define CPM_USBPCR_COMPDISTUNE_BIT	17

 #define CPM_USBPCR_COMPDISTUNE_MASK	(0x07 << COMPDISTUNE_BIT)

-#define CPM_USBPCR_OTGTUNE_BIT		14  

+#define CPM_USBPCR_OTGTUNE_BIT		14

 #define CPM_USBPCR_OTGTUNE_MASK		(0x07 << OTGTUNE_BIT)

-#define CPM_USBPCR_SQRXTUNE_BIT		11  

+#define CPM_USBPCR_SQRXTUNE_BIT		11

 #define CPM_USBPCR_SQRXTUNE_MASK	(0x7x << SQRXTUNE_BIT)

-#define CPM_USBPCR_TXFSLSTUNE_BIT	7  

+#define CPM_USBPCR_TXFSLSTUNE_BIT	7

 #define CPM_USBPCR_TXFSLSTUNE_MASK	(0x0f << TXFSLSTUNE_BIT)

 #define CPM_USBPCR_TXPREEMPHTUNE	(1 << 6)

 #define CPM_USBPCR_TXRISETUNE_BIT	4

 #define CPM_USBPCR_TXRISETUNE_MASK	(0x03 << TXRISETUNE_BIT)

-#define CPM_USBPCR_TXVREFTUNE_BIT	0  

+#define CPM_USBPCR_TXVREFTUNE_BIT	0

 #define CPM_USBPCR_TXVREFTUNE_MASK	(0x0f << TXVREFTUNE_BIT)

 

 /* USB reset detect timer register */

@@ -484,7 +582,7 @@
 #define __cpm_stop_me()		(REG_CPM_CLKGR1 |= CPM_CLKGR0_ME)

 #define __cpm_stop_dblk()	(REG_CPM_CLKGR1 |= CPM_CLKGR0_DBLK)

 #define __cpm_stop_mc()		(REG_CPM_CLKGR1 |= CPM_CLKGR0_MC)

-#define __cpm_stop_bdma()	(REG_CPM_CLKGR1 |= CPM_CLKGR0_BDMA)

+#define __cpm_stop_bdma()	(REG_CPM_CLKGR1 |= CPM_CLKGR1_BDMA)

 

 #define __cpm_start_all() 	\

 	do {\

@@ -532,7 +630,7 @@
 #define __cpm_start_me()		(REG_CPM_CLKGR1 &= ~CPM_CLKGR0_ME)

 #define __cpm_start_dblk()	(REG_CPM_CLKGR1 &= ~CPM_CLKGR0_DBLK)

 #define __cpm_start_mc()		(REG_CPM_CLKGR1 &= ~CPM_CLKGR0_MC)

-#define __cpm_start_bdma()	(REG_CPM_CLKGR1 &= ~CPM_CLKGR0_BDMA)

+#define __cpm_start_bdma()	(REG_CPM_CLKGR1 &= ~CPM_CLKGR1_BDMA)

 

 #define __cpm_get_o1st() \

 	((REG_CPM_OPCR & CPM_OPCR_O1ST_MASK) >> CPM_OPCR_O1ST_BIT)

@@ -546,13 +644,21 @@
 #define __cpm_enable_uhc_phy()		(REG_CPM_OPCR &= ~CPM_OPCR_UHCPHY_DISABLE)

 

 #define __cpm_suspend_uhcphy()  (REG_CPM_OPCR |= CPM_OPCR_UHCPHY_DISABLE)

-#define __cpm_suspend_gps()        (REG_CPM_OPCR &= ~CPM_OPCR_GPSEN)              

+#define __cpm_suspend_gps()        (REG_CPM_OPCR &= ~CPM_OPCR_GPSEN)

 #define __cpm_suspend_udcphy()	(REG_CPM_OPCR &= ~CPM_OPCR_UDCPHY_ENABLE)

 #define __cpm_disable_osc_in_sleep()	(REG_CPM_OPCR &= ~CPM_OPCR_OSC_ENABLE)

 #define __cpm_enable_osc_in_sleep()	(REG_CPM_OPCR |= CPM_OPCR_OSC_ENABLE)

 #define __cpm_select_rtcclk_rtc()	(REG_CPM_OPCR |= CPM_OPCR_ERCS)

 #define __cpm_select_rtcclk_exclk()	(REG_CPM_OPCR &= ~CPM_OPCR_ERCS)

 

+void cpm_start_clock(clock_gate_module module_name);

+void cpm_stop_clock(clock_gate_module module_name);

+unsigned int cpm_set_clock(cgu_clock clock_name, unsigned int clock_hz);

+unsigned int cpm_get_clock(cgu_clock clock_name);

+unsigned int cpm_get_pllout(void);

+

+extern int jz_pm_init(void);

+

 #endif /* __MIPS_ASSEMBLER */

 

 #endif /* __JZ4810CPM_H__ */

diff --git a/arch/mips/include/asm/mach-jz4810/jz4810dmac.h b/arch/mips/include/asm/mach-jz4810/jz4810dmac.h
index ebde999c268..7bda37b0a4d 100644
--- a/arch/mips/include/asm/mach-jz4810/jz4810dmac.h
+++ b/arch/mips/include/asm/mach-jz4810/jz4810dmac.h
@@ -31,7 +31,7 @@
 #define DMAC_DCCSR(n) (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0x10 + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x20)) /* DMA control/status */

 #define DMAC_DCMD(n)  (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0x14 + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x20)) /* DMA command */

 #define DMAC_DDA(n)   (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0x18 + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x20)) /* DMA descriptor address */

-#define DMAC_DSD(n)   (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0xc0 + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x04)) /* DMA Stride Address */

+#define DMAC_DSD(n)   (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0x1c + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x04)) /* DMA Stride Address */

 

 #define DMAC_DMACR(m)	(DMAC_BASE + 0x0300 + 0x100 * (m))              /* DMA control register */

 #define DMAC_DMAIPR(m)	(DMAC_BASE + 0x0304 + 0x100 * (m))              /* DMA interrupt pending */

@@ -56,102 +56,105 @@
 // DMA request source register

 #define DMAC_DRSR_RS_BIT	0

 #define DMAC_DRSR_RS_MASK	(0x3f << DMAC_DRSR_RS_BIT)

-  #define DMAC_DRSR_RS_EXT	(0 << DMAC_DRSR_RS_BIT)

-  #define DMAC_DRSR_RS_NAND	(1 << DMAC_DRSR_RS_BIT)

-  #define DMAC_DRSR_RS_BCH_ENC	(2 << DMAC_DRSR_RS_BIT)

-  #define DMAC_DRSR_RS_BCH_DEC	(3 << DMAC_DRSR_RS_BIT)

-  #define DMAC_DRSR_RS_AUTO	(8 << DMAC_DRSR_RS_BIT)

-  #define DMAC_DRSR_RS_TSSIIN	(9 << DMAC_DRSR_RS_BIT)

-  #define DMAC_DRSR_RS_UART3OUT	(14 << DMAC_DRSR_RS_BIT)

-  #define DMAC_DRSR_RS_UART3IN	(15 << DMAC_DRSR_RS_BIT)

-  #define DMAC_DRSR_RS_UART2OUT	(16 << DMAC_DRSR_RS_BIT)

-  #define DMAC_DRSR_RS_UART2IN	(17 << DMAC_DRSR_RS_BIT)

-  #define DMAC_DRSR_RS_UART1OUT	(18 << DMAC_DRSR_RS_BIT)

-  #define DMAC_DRSR_RS_UART1IN	(19 << DMAC_DRSR_RS_BIT)

-  #define DMAC_DRSR_RS_UART0OUT	(20 << DMAC_DRSR_RS_BIT)

-  #define DMAC_DRSR_RS_UART0IN	(21 << DMAC_DRSR_RS_BIT)

-  #define DMAC_DRSR_RS_SSI0OUT	(22 << DMAC_DRSR_RS_BIT)

-  #define DMAC_DRSR_RS_SSI0IN	(23 << DMAC_DRSR_RS_BIT)

-  #define DMAC_DRSR_RS_AICOUT	(24 << DMAC_DRSR_RS_BIT)

-  #define DMAC_DRSR_RS_AICIN	(25 << DMAC_DRSR_RS_BIT)

-  #define DMAC_DRSR_RS_MSC0OUT	(26 << DMAC_DRSR_RS_BIT)

-  #define DMAC_DRSR_RS_MSC0IN	(27 << DMAC_DRSR_RS_BIT)

-  #define DMAC_DRSR_RS_TCU	(28 << DMAC_DRSR_RS_BIT)

-  #define DMAC_DRSR_RS_SADC	(29 << DMAC_DRSR_RS_BIT)

-  #define DMAC_DRSR_RS_MSC1OUT	(30 << DMAC_DRSR_RS_BIT)

-  #define DMAC_DRSR_RS_MSC1IN	(31 << DMAC_DRSR_RS_BIT)

-  #define DMAC_DRSR_RS_SSI1OUT	(32 << DMAC_DRSR_RS_BIT)

-  #define DMAC_DRSR_RS_SSI1IN	(33 << DMAC_DRSR_RS_BIT)

-  #define DMAC_DRSR_RS_PMOUT	(34 << DMAC_DRSR_RS_BIT)

-  #define DMAC_DRSR_RS_PMIN	(35 << DMAC_DRSR_RS_BIT)

+/* 0~7 is reserved */

+#define DMAC_DRSR_RS_AUTO	(8 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_TSSIIN	(9 << DMAC_DRSR_RS_BIT)

+/* 10 ~ 11 is reserved */

+#define DMAC_DRSR_RS_EXTERN	(12 << DMAC_DRSR_RS_BIT)

+/* 13 is reserved */

+#define DMAC_DRSR_RS_UART3OUT	(14 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_UART3IN	(15 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_UART2OUT	(16 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_UART2IN	(17 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_UART1OUT	(18 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_UART1IN	(19 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_UART0OUT	(20 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_UART0IN	(21 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_SSI0OUT	(22 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_SSI0IN	(23 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_AICOUT	(24 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_AICIN	(25 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_MSC0OUT	(26 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_MSC0IN	(27 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_TCU	(28 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_SADC	(29 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_MSC1OUT	(30 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_MSC1IN	(31 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_SSI1OUT	(32 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_SSI1IN	(33 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_PMOUT	(34 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_PMIN	(35 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_MSC2OUT	(36 << DMAC_DRSR_RS_BIT)

+#define DMAC_DRSR_RS_MSC2IN	(37 << DMAC_DRSR_RS_BIT)

+/* others are reserved */

 

 // DMA channel control/status register

 #define DMAC_DCCSR_NDES		(1 << 31) /* descriptor (0) or not (1) ? */

 #define DMAC_DCCSR_DES8    	(1 << 30) /* Descriptor 8 Word */

 #define DMAC_DCCSR_DES4    	(0 << 30) /* Descriptor 4 Word */

+/* [29:24] reserved */

 #define DMAC_DCCSR_CDOA_BIT	16        /* copy of DMA offset address */

 #define DMAC_DCCSR_CDOA_MASK	(0xff << DMAC_DCCSR_CDOA_BIT)

-#define DMAC_DCCSR_BERR		(1 << 7)  /* BCH error within this transfer, Only for channel 0 */

-#define DMAC_DCCSR_INV		(1 << 6)  /* descriptor invalid */

+/* [15:5] reserved */

 #define DMAC_DCCSR_AR		(1 << 4)  /* address error */

 #define DMAC_DCCSR_TT		(1 << 3)  /* transfer terminated */

 #define DMAC_DCCSR_HLT		(1 << 2)  /* DMA halted */

 #define DMAC_DCCSR_CT		(1 << 1)  /* count terminated */

 #define DMAC_DCCSR_EN		(1 << 0)  /* channel enable bit */

 

-// DMA channel command register 

+// DMA channel command register

 #define DMAC_DCMD_EACKS_LOW  	(1 << 31) /* External DACK Output Level Select, active low */

 #define DMAC_DCMD_EACKS_HIGH  	(0 << 31) /* External DACK Output Level Select, active high */

 #define DMAC_DCMD_EACKM_WRITE 	(1 << 30) /* External DACK Output Mode Select, output in write cycle */

 #define DMAC_DCMD_EACKM_READ 	(0 << 30) /* External DACK Output Mode Select, output in read cycle */

 #define DMAC_DCMD_ERDM_BIT      28        /* External DREQ Detection Mode Select */

 #define DMAC_DCMD_ERDM_MASK     (0x03 << DMAC_DCMD_ERDM_BIT)

-  #define DMAC_DCMD_ERDM_LOW    (0 << DMAC_DCMD_ERDM_BIT)

-  #define DMAC_DCMD_ERDM_FALL   (1 << DMAC_DCMD_ERDM_BIT)

-  #define DMAC_DCMD_ERDM_HIGH   (2 << DMAC_DCMD_ERDM_BIT)

-  #define DMAC_DCMD_ERDM_RISE   (3 << DMAC_DCMD_ERDM_BIT)

-#define DMAC_DCMD_BLAST		(1 << 25) /* BCH last */

+#define DMAC_DCMD_ERDM_LOW    (0 << DMAC_DCMD_ERDM_BIT)

+#define DMAC_DCMD_ERDM_FALL   (1 << DMAC_DCMD_ERDM_BIT)

+#define DMAC_DCMD_ERDM_HIGH   (2 << DMAC_DCMD_ERDM_BIT)

+#define DMAC_DCMD_ERDM_RISE   (3 << DMAC_DCMD_ERDM_BIT)

+/* [27:24] reserved */

 #define DMAC_DCMD_SAI		(1 << 23) /* source address increment */

 #define DMAC_DCMD_DAI		(1 << 22) /* dest address increment */

 #define DMAC_DCMD_RDIL_BIT	16        /* request detection interval length */

 #define DMAC_DCMD_RDIL_MASK	(0x0f << DMAC_DCMD_RDIL_BIT)

-  #define DMAC_DCMD_RDIL_IGN	(0 << DMAC_DCMD_RDIL_BIT)

-  #define DMAC_DCMD_RDIL_2	(1 << DMAC_DCMD_RDIL_BIT)

-  #define DMAC_DCMD_RDIL_4	(2 << DMAC_DCMD_RDIL_BIT)

-  #define DMAC_DCMD_RDIL_8	(3 << DMAC_DCMD_RDIL_BIT)

-  #define DMAC_DCMD_RDIL_12	(4 << DMAC_DCMD_RDIL_BIT)

-  #define DMAC_DCMD_RDIL_16	(5 << DMAC_DCMD_RDIL_BIT)

-  #define DMAC_DCMD_RDIL_20	(6 << DMAC_DCMD_RDIL_BIT)

-  #define DMAC_DCMD_RDIL_24	(7 << DMAC_DCMD_RDIL_BIT)

-  #define DMAC_DCMD_RDIL_28	(8 << DMAC_DCMD_RDIL_BIT)

-  #define DMAC_DCMD_RDIL_32	(9 << DMAC_DCMD_RDIL_BIT)

-  #define DMAC_DCMD_RDIL_48	(10 << DMAC_DCMD_RDIL_BIT)

-  #define DMAC_DCMD_RDIL_60	(11 << DMAC_DCMD_RDIL_BIT)

-  #define DMAC_DCMD_RDIL_64	(12 << DMAC_DCMD_RDIL_BIT)

-  #define DMAC_DCMD_RDIL_124	(13 << DMAC_DCMD_RDIL_BIT)

-  #define DMAC_DCMD_RDIL_128	(14 << DMAC_DCMD_RDIL_BIT)

-  #define DMAC_DCMD_RDIL_200	(15 << DMAC_DCMD_RDIL_BIT)

+#define DMAC_DCMD_RDIL_IGN	(0 << DMAC_DCMD_RDIL_BIT)

+#define DMAC_DCMD_RDIL_2	(1 << DMAC_DCMD_RDIL_BIT)

+#define DMAC_DCMD_RDIL_4	(2 << DMAC_DCMD_RDIL_BIT)

+#define DMAC_DCMD_RDIL_8	(3 << DMAC_DCMD_RDIL_BIT)

+#define DMAC_DCMD_RDIL_12	(4 << DMAC_DCMD_RDIL_BIT)

+#define DMAC_DCMD_RDIL_16	(5 << DMAC_DCMD_RDIL_BIT)

+#define DMAC_DCMD_RDIL_20	(6 << DMAC_DCMD_RDIL_BIT)

+#define DMAC_DCMD_RDIL_24	(7 << DMAC_DCMD_RDIL_BIT)

+#define DMAC_DCMD_RDIL_28	(8 << DMAC_DCMD_RDIL_BIT)

+#define DMAC_DCMD_RDIL_32	(9 << DMAC_DCMD_RDIL_BIT)

+#define DMAC_DCMD_RDIL_48	(10 << DMAC_DCMD_RDIL_BIT)

+#define DMAC_DCMD_RDIL_60	(11 << DMAC_DCMD_RDIL_BIT)

+#define DMAC_DCMD_RDIL_64	(12 << DMAC_DCMD_RDIL_BIT)

+#define DMAC_DCMD_RDIL_124	(13 << DMAC_DCMD_RDIL_BIT)

+#define DMAC_DCMD_RDIL_128	(14 << DMAC_DCMD_RDIL_BIT)

+#define DMAC_DCMD_RDIL_200	(15 << DMAC_DCMD_RDIL_BIT)

 #define DMAC_DCMD_SWDH_BIT	14  /* source port width */

 #define DMAC_DCMD_SWDH_MASK	(0x03 << DMAC_DCMD_SWDH_BIT)

-  #define DMAC_DCMD_SWDH_32	(0 << DMAC_DCMD_SWDH_BIT)

-  #define DMAC_DCMD_SWDH_8	(1 << DMAC_DCMD_SWDH_BIT)

-  #define DMAC_DCMD_SWDH_16	(2 << DMAC_DCMD_SWDH_BIT)

+#define DMAC_DCMD_SWDH_32	(0 << DMAC_DCMD_SWDH_BIT)

+#define DMAC_DCMD_SWDH_8	(1 << DMAC_DCMD_SWDH_BIT)

+#define DMAC_DCMD_SWDH_16	(2 << DMAC_DCMD_SWDH_BIT)

 #define DMAC_DCMD_DWDH_BIT	12  /* dest port width */

 #define DMAC_DCMD_DWDH_MASK	(0x03 << DMAC_DCMD_DWDH_BIT)

-  #define DMAC_DCMD_DWDH_32	(0 << DMAC_DCMD_DWDH_BIT)

-  #define DMAC_DCMD_DWDH_8	(1 << DMAC_DCMD_DWDH_BIT)

-  #define DMAC_DCMD_DWDH_16	(2 << DMAC_DCMD_DWDH_BIT)

+#define DMAC_DCMD_DWDH_32	(0 << DMAC_DCMD_DWDH_BIT)

+#define DMAC_DCMD_DWDH_8	(1 << DMAC_DCMD_DWDH_BIT)

+#define DMAC_DCMD_DWDH_16	(2 << DMAC_DCMD_DWDH_BIT)

+/* bit11 reserved */

 #define DMAC_DCMD_DS_BIT	8  /* transfer data size of a data unit */

 #define DMAC_DCMD_DS_MASK	(0x07 << DMAC_DCMD_DS_BIT)

-  #define DMAC_DCMD_DS_32BIT	(0 << DMAC_DCMD_DS_BIT)

-  #define DMAC_DCMD_DS_8BIT	(1 << DMAC_DCMD_DS_BIT)

-  #define DMAC_DCMD_DS_16BIT	(2 << DMAC_DCMD_DS_BIT)

-  #define DMAC_DCMD_DS_16BYTE	(3 << DMAC_DCMD_DS_BIT)

-  #define DMAC_DCMD_DS_32BYTE	(4 << DMAC_DCMD_DS_BIT)

-#define DMAC_DCMD_STDE   	(1 << 5)  /* Stride Disable/Enable */

-#define DMAC_DCMD_DES_V		(1 << 4)  /* descriptor valid flag */

-#define DMAC_DCMD_DES_VM	(1 << 3)  /* descriptor valid mask: 1:support V-bit */

-#define DMAC_DCMD_DES_VIE	(1 << 2)  /* DMA valid error interrupt enable */

+#define DMAC_DCMD_DS_32BIT	(0 << DMAC_DCMD_DS_BIT)

+#define DMAC_DCMD_DS_8BIT	(1 << DMAC_DCMD_DS_BIT)

+#define DMAC_DCMD_DS_16BIT	(2 << DMAC_DCMD_DS_BIT)

+#define DMAC_DCMD_DS_16BYTE	(3 << DMAC_DCMD_DS_BIT)

+#define DMAC_DCMD_DS_32BYTE	(4 << DMAC_DCMD_DS_BIT)

+#define DMAC_DCMD_DS_64BYTE	(5 << DMAC_DCMD_DS_BIT)

+/* [7:3] reserved */

+#define DMAC_DCMD_STDE   	(1 << 2)  /* Stride Disable/Enable */

 #define DMAC_DCMD_TIE		(1 << 1)  /* DMA transfer interrupt enable */

 #define DMAC_DCMD_LINK		(1 << 0)  /* descriptor link enable */

 

@@ -160,6 +163,7 @@
 #define DMAC_DDA_BASE_MASK	(0x0fffff << DMAC_DDA_BASE_BIT)

 #define DMAC_DDA_OFFSET_BIT	4   /* descriptor offset address */

 #define DMAC_DDA_OFFSET_MASK	(0x0ff << DMAC_DDA_OFFSET_BIT)

+/* [3:0] reserved */

 

 // DMA stride address register

 #define DMAC_DSD_TSD_BIT        16  /* target stride address */

@@ -173,14 +177,17 @@
 #define DMAC_DMACR_FTSSI	(1 << 29)  /* TSSI Fast DMA mode */

 #define DMAC_DMACR_FUART	(1 << 28)  /* UART Fast DMA mode */

 #define DMAC_DMACR_FAIC		(1 << 27)  /* AIC Fast DMA mode */

+/* [26:10] reserved */

 #define DMAC_DMACR_PR_BIT	8  /* channel priority mode */

 #define DMAC_DMACR_PR_MASK	(0x03 << DMAC_DMACR_PR_BIT)

-  #define DMAC_DMACR_PR_012345	(0 << DMAC_DMACR_PR_BIT)

-  #define DMAC_DMACR_PR_120345	(1 << DMAC_DMACR_PR_BIT)

-  #define DMAC_DMACR_PR_230145	(2 << DMAC_DMACR_PR_BIT)

-  #define DMAC_DMACR_PR_340125	(3 << DMAC_DMACR_PR_BIT)

+#define DMAC_DMACR_PR_012345	(0 << DMAC_DMACR_PR_BIT)

+#define DMAC_DMACR_PR_120345	(1 << DMAC_DMACR_PR_BIT)

+#define DMAC_DMACR_PR_230145	(2 << DMAC_DMACR_PR_BIT)

+#define DMAC_DMACR_PR_340125	(3 << DMAC_DMACR_PR_BIT)

+/* [7:4] resered */

 #define DMAC_DMACR_HLT		(1 << 3)  /* DMA halt flag */

 #define DMAC_DMACR_AR		(1 << 2)  /* address error flag */

+/* bit1 reserved */

 #define DMAC_DMACR_DMAE		(1 << 0)  /* DMA enable bit */

 

 // DMA doorbell register

@@ -217,55 +224,55 @@
 

 /* m is the DMA controller index (0, 1), n is the DMA channel index (0 - 11) */

 

-#define __dmac_enable_module(m) \

+#define __dmac_enable_module(m)						\

 	( REG_DMAC_DMACR(m) |= DMAC_DMACR_DMAE | DMAC_DMACR_PR_012345 )

-#define __dmac_disable_module(m) \

+#define __dmac_disable_module(m)			\

 	( REG_DMAC_DMACR(m) &= ~DMAC_DMACR_DMAE )

 

 /* p=0,1,2,3 */

-#define __dmac_set_priority(m,p)			\

-do {							\

-	REG_DMAC_DMACR(m) &= ~DMAC_DMACR_PR_MASK;	\

-	REG_DMAC_DMACR(m) |= ((p) << DMAC_DMACR_PR_BIT);	\

-} while (0)

+#define __dmac_set_priority(m,p)					\

+	do {								\

+		REG_DMAC_DMACR(m) &= ~DMAC_DMACR_PR_MASK;		\

+		REG_DMAC_DMACR(m) |= ((p) << DMAC_DMACR_PR_BIT);	\

+	} while (0)

 

 #define __dmac_test_halt_error(m) ( REG_DMAC_DMACR(m) & DMAC_DMACR_HLT )

 #define __dmac_test_addr_error(m) ( REG_DMAC_DMACR(m) & DMAC_DMACR_AR )

 

-#define __dmac_channel_enable_clk(n) \

+#define __dmac_channel_enable_clk(n)					\

 	REG_DMAC_DMACKE((n)/HALF_DMA_NUM) |= 1 << ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM);

 

-#define __dmac_enable_descriptor(n) \

-  ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_NDES )

-#define __dmac_disable_descriptor(n) \

-  ( REG_DMAC_DCCSR((n)) |= DMAC_DCCSR_NDES )

-

-#define __dmac_enable_channel(n)                 \

-do {                                             \

-	REG_DMAC_DCCSR((n)) |= DMAC_DCCSR_EN;    \

-} while (0)

-#define __dmac_disable_channel(n)                \

-do {                                             \

-	REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_EN;   \

-} while (0)

-#define __dmac_channel_enabled(n) \

-  ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_EN )

-

-#define __dmac_channel_enable_irq(n) \

-  ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_TIE )

-#define __dmac_channel_disable_irq(n) \

-  ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_TIE )

-

-#define __dmac_channel_transmit_halt_detected(n) \

-  (  REG_DMAC_DCCSR((n)) & DMAC_DCCSR_HLT )

-#define __dmac_channel_transmit_end_detected(n) \

-  (  REG_DMAC_DCCSR((n)) & DMAC_DCCSR_TT )

-#define __dmac_channel_address_error_detected(n) \

-  (  REG_DMAC_DCCSR((n)) & DMAC_DCCSR_AR )

-#define __dmac_channel_count_terminated_detected(n) \

-  (  REG_DMAC_DCCSR((n)) & DMAC_DCCSR_CT )

-#define __dmac_channel_descriptor_invalid_detected(n) \

-  (  REG_DMAC_DCCSR((n)) & DMAC_DCCSR_INV )

+#define __dmac_enable_descriptor(n)			\

+	( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_NDES )

+#define __dmac_disable_descriptor(n)			\

+	( REG_DMAC_DCCSR((n)) |= DMAC_DCCSR_NDES )

+

+#define __dmac_enable_channel(n)			\

+	do {						\

+		REG_DMAC_DCCSR((n)) |= DMAC_DCCSR_EN;	\

+	} while (0)

+#define __dmac_disable_channel(n)			\

+	do {						\

+		REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_EN;	\

+	} while (0)

+#define __dmac_channel_enabled(n)		\

+	( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_EN )

+

+#define __dmac_channel_enable_irq(n)		\

+	( REG_DMAC_DCMD((n)) |= DMAC_DCMD_TIE )

+#define __dmac_channel_disable_irq(n)			\

+	( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_TIE )

+

+#define __dmac_channel_transmit_halt_detected(n)	\

+	(  REG_DMAC_DCCSR((n)) & DMAC_DCCSR_HLT )

+#define __dmac_channel_transmit_end_detected(n)		\

+	(  REG_DMAC_DCCSR((n)) & DMAC_DCCSR_TT )

+#define __dmac_channel_address_error_detected(n)	\

+	(  REG_DMAC_DCCSR((n)) & DMAC_DCCSR_AR )

+#define __dmac_channel_count_terminated_detected(n)	\

+	(  REG_DMAC_DCCSR((n)) & DMAC_DCCSR_CT )

+#define __dmac_channel_descriptor_invalid_detected(n)	\

+	(  REG_DMAC_DCCSR((n)) & DMAC_DCCSR_INV )

 

 #define __dmac_channel_clear_transmit_halt(n)				\

 	do {								\

@@ -273,8 +280,8 @@ do {                                             \
 		REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_HLT;			\

 		REG_DMAC_DMACR(n/HALF_DMA_NUM) &= ~DMAC_DMACR_HLT;	\

 	} while (0)

-#define __dmac_channel_clear_transmit_end(n) \

-  (  REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_TT )

+#define __dmac_channel_clear_transmit_end(n)		\

+	(  REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_TT )

 #define __dmac_channel_clear_address_error(n)				\

 	do {								\

 		REG_DMAC_DDA(n) = 0; /* clear descriptor address register */ \

@@ -284,73 +291,73 @@ do {                                             \
 		REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_AR;			\

 		REG_DMAC_DMACR(n/HALF_DMA_NUM) &= ~DMAC_DMACR_AR;	\

 	} while (0)

-#define __dmac_channel_clear_count_terminated(n) \

-  (  REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_CT )

-#define __dmac_channel_clear_descriptor_invalid(n) \

-  (  REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_INV )

-

-#define __dmac_channel_set_transfer_unit_32bit(n)	\

-do {							\

-	REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK;	\

-	REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_32BIT;	\

-} while (0)

-

-#define __dmac_channel_set_transfer_unit_16bit(n)	\

-do {							\

-	REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK;	\

-	REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_16BIT;	\

-} while (0)

-

-#define __dmac_channel_set_transfer_unit_8bit(n)	\

-do {							\

-	REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK;	\

-	REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_8BIT;	\

-} while (0)

-

-#define __dmac_channel_set_transfer_unit_16byte(n)	\

-do {							\

-	REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK;	\

-	REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_16BYTE;	\

-} while (0)

-

-#define __dmac_channel_set_transfer_unit_32byte(n)	\

-do {							\

-	REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK;	\

-	REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_32BYTE;	\

-} while (0)

+#define __dmac_channel_clear_count_terminated(n)	\

+	(  REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_CT )

+#define __dmac_channel_clear_descriptor_invalid(n)	\

+	(  REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_INV )

+

+#define __dmac_channel_set_transfer_unit_32bit(n)		\

+	do {							\

+		REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK;	\

+		REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_32BIT;	\

+	} while (0)

+

+#define __dmac_channel_set_transfer_unit_16bit(n)		\

+	do {							\

+		REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK;	\

+		REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_16BIT;	\

+	} while (0)

+

+#define __dmac_channel_set_transfer_unit_8bit(n)		\

+	do {							\

+		REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK;	\

+		REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_8BIT;	\

+	} while (0)

+

+#define __dmac_channel_set_transfer_unit_16byte(n)		\

+	do {							\

+		REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK;	\

+		REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_16BYTE;	\

+	} while (0)

+

+#define __dmac_channel_set_transfer_unit_32byte(n)		\

+	do {							\

+		REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK;	\

+		REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_32BYTE;	\

+	} while (0)

 

 /* w=8,16,32 */

-#define __dmac_channel_set_dest_port_width(n,w)		\

-do {							\

-	REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DWDH_MASK;	\

-	REG_DMAC_DCMD((n)) |= DMAC_DCMD_DWDH_##w;	\

-} while (0)

+#define __dmac_channel_set_dest_port_width(n,w)			\

+	do {							\

+		REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DWDH_MASK;	\

+		REG_DMAC_DCMD((n)) |= DMAC_DCMD_DWDH_##w;	\

+	} while (0)

 

 /* w=8,16,32 */

-#define __dmac_channel_set_src_port_width(n,w)		\

-do {							\

-	REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_SWDH_MASK;	\

-	REG_DMAC_DCMD((n)) |= DMAC_DCMD_SWDH_##w;	\

-} while (0)

+#define __dmac_channel_set_src_port_width(n,w)			\

+	do {							\

+		REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_SWDH_MASK;	\

+		REG_DMAC_DCMD((n)) |= DMAC_DCMD_SWDH_##w;	\

+	} while (0)

 

 /* v=0-15 */

 #define __dmac_channel_set_rdil(n,v)				\

-do {								\

+	do {							\

 	REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_RDIL_MASK;		\

 	REG_DMAC_DCMD((n) |= ((v) << DMAC_DCMD_RDIL_BIT);	\

-} while (0)

+		      } while (0)

 

-#define __dmac_channel_dest_addr_fixed(n) \

-  (  REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DAI )

-#define __dmac_channel_dest_addr_increment(n) \

-  (  REG_DMAC_DCMD((n)) |= DMAC_DCMD_DAI )

+#define __dmac_channel_dest_addr_fixed(n)		\

+	(  REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DAI )

+#define __dmac_channel_dest_addr_increment(n)		\

+	(  REG_DMAC_DCMD((n)) |= DMAC_DCMD_DAI )

 

-#define __dmac_channel_src_addr_fixed(n) \

-  (  REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_SAI )

-#define __dmac_channel_src_addr_increment(n) \

-  (  REG_DMAC_DCMD((n)) |= DMAC_DCMD_SAI )

+#define __dmac_channel_src_addr_fixed(n)		\

+	(  REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_SAI )

+#define __dmac_channel_src_addr_increment(n)		\

+	(  REG_DMAC_DCMD((n)) |= DMAC_DCMD_SAI )

 

-#define __dmac_channel_set_doorbell(n)	\

+#define __dmac_channel_set_doorbell(n)					\

 	(  REG_DMAC_DMADBSR((n)/HALF_DMA_NUM) = (1 << ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM)) )

 

 #define __dmac_channel_irq_detected(n)  ( REG_DMAC_DMAIPR((n)/HALF_DMA_NUM) & (1 << ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM)) )

diff --git a/arch/mips/include/asm/mach-jz4810/jz4810gpio.h b/arch/mips/include/asm/mach-jz4810/jz4810gpio.h
index 062e1783e00..48372b2281b 100644
--- a/arch/mips/include/asm/mach-jz4810/jz4810gpio.h
+++ b/arch/mips/include/asm/mach-jz4810/jz4810gpio.h
@@ -68,7 +68,7 @@
 //	3	SA3		-              -             AL

 //	4	SA4		-              -

 //	5	SA5		-              -

-//	6	CIM_PCLK 	TSCLK	       -             

+//	6	CIM_PCLK 	TSCLK	       -

 //	7	CIM_HSYN  	TSFRM          -

 //	8	CIM_VSYN 	TSSTR          -

 //	9	CIM_MCLK 	TSFAIL         -

@@ -80,8 +80,8 @@
 //	15	CIM_D5		TSDI5          -

 //	16 	CIM_D6 		TSDI6          -

 //	17 	CIM_D7 		TSDI7          -

-//	18	-               -	       - 

-//	19	-               -	       - 

+//	18	-               -	       -

+//	19	-               -	       -

 //	20 	MSC2_D0 	SSI2_DR        TSDI0

 //	21 	MSC2_D1 	SSI2_DT        TSDI1

 //	22 	TSDI2		-              -

@@ -98,44 +98,44 @@
 //------------------------------------------------------

 // PORT 2:

 // PIN/BIT N	FUNC0		FUNC1		FUNC2 		FUNC3		NOTE

-//	0	LCD_B0 (O)	LCD_REV (O)	-               -	         

-//	1	LCD_B1 (O)	LCD_PS (O)	-               -	         

-//	2	LCD_B2 (O)	-               -	        - 

-//	3	LCD_B3 (O)	-               -	        - 

-//	4	LCD_B4 (O)	-               -	        - 

-//	5	LCD_B5 (O)	-               -	        - 

-//	6	LCD_B6 (O)	-               -	        - 

-//	7	LCD_B7 (O)	-               -	        - 

-//	8	LCD_PCLK (O)	-               -	        - 

-//	9	LCD_DE (O)	-               -	        - 

-//	10	LCD_G0 (O)	LCD_SPL (O)	-               -	         

-//	11	LCD_G1 (O)	-               -	        - 

-//	12	LCD_G2 (O)	-               -	        - 

-//	13	LCD_G3 (O)	-               -	        - 

-//	14	LCD_G4 (O)	-               -	        - 

-//	15	LCD_G5 (O)	-               -	        - 

-//	16	LCD_G6 (O)	-               -	        - 

-//	17	LCD_G7 (O)	-               -	        - 

-//	18	LCD_HSYN (IO)	-               -	        - 

-//	19	LCD_VSYN (IO)	-               -	        - 

-//	20	LCD_R0 (O)	LCD_CLS (O)	-               -	         

-//	21	LCD_R1 (O)	-               -	        - 

-//	22	LCD_R2 (O)	-               -	        - 

-//	23	LCD_R3 (O)	-               -	        - 

-//	24	LCD_R4 (O)	-               -	        - 

-//	25	LCD_R5 (O)	-               -	        - 

-//	26	LCD_R6 (O)	-               -	        - 

-//	27	LCD_R7 (O)	-               -	        - 

-//	28	UART2_RxD (I)	-               -	        - 

-//	29	UART2_CTS_ (I)	-               -	        - 

-//	30	UART2_TxD (O)	-               -	        - 

-//	31	UART2_RTS_ (O)	-               -	        - 

+//	0	LCD_B0 (O)	LCD_REV (O)	-               -

+//	1	LCD_B1 (O)	LCD_PS (O)	-               -

+//	2	LCD_B2 (O)	-               -	        -

+//	3	LCD_B3 (O)	-               -	        -

+//	4	LCD_B4 (O)	-               -	        -

+//	5	LCD_B5 (O)	-               -	        -

+//	6	LCD_B6 (O)	-               -	        -

+//	7	LCD_B7 (O)	-               -	        -

+//	8	LCD_PCLK (O)	-               -	        -

+//	9	LCD_DE (O)	-               -	        -

+//	10	LCD_G0 (O)	LCD_SPL (O)	-               -

+//	11	LCD_G1 (O)	-               -	        -

+//	12	LCD_G2 (O)	-               -	        -

+//	13	LCD_G3 (O)	-               -	        -

+//	14	LCD_G4 (O)	-               -	        -

+//	15	LCD_G5 (O)	-               -	        -

+//	16	LCD_G6 (O)	-               -	        -

+//	17	LCD_G7 (O)	-               -	        -

+//	18	LCD_HSYN (IO)	-               -	        -

+//	19	LCD_VSYN (IO)	-               -	        -

+//	20	LCD_R0 (O)	LCD_CLS (O)	-               -

+//	21	LCD_R1 (O)	-               -	        -

+//	22	LCD_R2 (O)	-               -	        -

+//	23	LCD_R3 (O)	-               -	        -

+//	24	LCD_R4 (O)	-               -	        -

+//	25	LCD_R5 (O)	-               -	        -

+//	26	LCD_R6 (O)	-               -	        -

+//	27	LCD_R7 (O)	-               -	        -

+//	28	UART2_RxD (I)	-               -	        -

+//	29	UART2_CTS_ (I)	-               -	        -

+//	30	UART2_TxD (O)	-               -	        -

+//	31	UART2_RTS_ (O)	-               -	        -

 

 //------------------------------------------------------

 // PORT 3:

 //

 // PIN/BIT N	FUNC0		FUNC1		FUNC2 		FUNC3		NOTE

-//	0 	MII_TXD0 	-     		-  		-		

+//	0 	MII_TXD0 	-     		-  		-

 //	1 	MII_TXD1	-     		-  		-

 //	2 	MII_TXD2	-     		-  		-

 //	3 	MII_TXD3	- 		-  		-

@@ -167,12 +167,12 @@
 //	29 	UART1_RTS_ 	-		-  		-

 //	30 	I2C0_SDA 	-		-  		-

 //	31 	I2C0_SCK 	-		-  		-

-//	

+//

 // Note2. PD17: GPIO group D bit 17 is used as BOOT_SEL0 input during boot.

 // Note3. PD18: GPIO group D bit 18 is used as BOOT_SEL1 input during boot.

 // Note4. PD19: GPIO group D bit 19 is used as BOOT_SEL2 input during boot.

 // Note5. BOOT_SEL2, BOOT_SEL1, BOOT_SEL0 are used to select boot source and function during the processor boot.

-//	

+//

 //------------------------------------------------------

 // PORT 4:

 //

@@ -182,7 +182,7 @@
 //	2  	PWM2 		SYNC 		- 		-

 //	3  	PWM3 		UART3_RxD 	BCLK 		-

 //	4  	PWM4 		- 		- 		-

-//	5  	PWM5 		UART3_TxD 	SCLK_RSTN 	-	

+//	5  	PWM5 		UART3_TxD 	SCLK_RSTN 	-

 //	6  	SDATI		- 		- 		-

 //	7  	SDATO 		- 		- 		-

 //	8  	UART3_CTS_ 	- 		- 		-

@@ -203,10 +203,10 @@
 //	23  	MSC0_D3 	MSC1_D3 	MSC2_D3 	-

 //	24  	MSC0_CLK 	MSC1_CLK 	MSC2_CLK 	-

 //	25  	MSC0_CMD 	MSC1_CMD 	MSC2_CMD 	-

-//	26  	MSC0_D4 	MSC0_D4 	MSC0_D4 	PS2_MCLK 

-//	27  	MSC0_D5 	MSC0_D5 	MSC0_D5 	PS2_MDATA 

-//	28  	MSC0_D6 	MSC0_D6 	MSC0_D6 	PS2_KCLK 

-//	29  	MSC0_D7 	MSC0_D7 	MSC0_D7 	PS2_KDATA 

+//	26  	MSC0_D4 	MSC0_D4 	MSC0_D4 	PS2_MCLK

+//	27  	MSC0_D5 	MSC0_D5 	MSC0_D5 	PS2_MDATA

+//	28  	MSC0_D6 	MSC0_D6 	MSC0_D6 	PS2_KCLK

+//	29  	MSC0_D7 	MSC0_D7 	MSC0_D7 	PS2_KDATA

 //	30  	I2C1_SDA 	SCC_DATA 	- 		-

 //	31  	I2C1_SCK 	SCC_CLK 	- 		-

 //

@@ -245,12 +245,12 @@
 #define GPIO_PXINTS(n)	(GPIO_BASE + (0x14 + (n)*0x100)) /* Port Interrupt Set Register */

 #define GPIO_PXINTC(n)	(GPIO_BASE + (0x18 + (n)*0x100)) /* Port Interrupt Clear Register */

 

-#define GPIO_PXIM(n)	(GPIO_BASE + (0x20 + (n)*0x100)) /* Interrupt Mask Register */

-#define GPIO_PXIMS(n)	(GPIO_BASE + (0x24 + (n)*0x100)) /* Interrupt Mask Set Reg */

-#define GPIO_PXIMC(n)	(GPIO_BASE + (0x28 + (n)*0x100)) /* Interrupt Mask Clear Reg */

-//#define GPIO_PXMASK(n)	(GPIO_BASE + (0x20 + (n)*0x100)) /* Port Interrupt Mask Register */

-//#define GPIO_PXMASKS(n)	(GPIO_BASE + (0x24 + (n)*0x100)) /* Port Interrupt Mask Set Reg */

-//#define GPIO_PXMASKC(n)	(GPIO_BASE + (0x28 + (n)*0x100)) /* Port Interrupt Mask Clear Reg */

+//#define GPIO_PXMASK(n)	(GPIO_BASE + (0x20 + (n)*0x100)) /* Interrupt Mask Register */

+//#define GPIO_PXMASKS(n)	(GPIO_BASE + (0x24 + (n)*0x100)) /* Interrupt Mask Set Reg */

+//#define GPIO_PXMASKC(n)	(GPIO_BASE + (0x28 + (n)*0x100)) /* Interrupt Mask Clear Reg */

+#define GPIO_PXMASK(n)	(GPIO_BASE + (0x20 + (n)*0x100)) /* Port Interrupt Mask Register */

+#define GPIO_PXMASKS(n)	(GPIO_BASE + (0x24 + (n)*0x100)) /* Port Interrupt Mask Set Reg */

+#define GPIO_PXMASKC(n)	(GPIO_BASE + (0x28 + (n)*0x100)) /* Port Interrupt Mask Clear Reg */

 

 #define GPIO_PXPAT1(n)	(GPIO_BASE + (0x30 + (n)*0x100)) /* Port Pattern 1 Register */

 #define GPIO_PXPAT1S(n)	(GPIO_BASE + (0x34 + (n)*0x100)) /* Port Pattern 1 Set Reg. */

@@ -259,7 +259,7 @@
 #define GPIO_PXPAT0S(n)	(GPIO_BASE + (0x44 + (n)*0x100)) /* Port Pattern 0 Set Register */

 #define GPIO_PXPAT0C(n)	(GPIO_BASE + (0x48 + (n)*0x100)) /* Port Pattern 0 Clear Register */

 #define GPIO_PXFLG(n)	(GPIO_BASE + (0x50 + (n)*0x100)) /* Port Flag Register */

-#define GPIO_PXFLGC(n)	(GPIO_BASE + (0x54 + (n)*0x100)) /* Port Flag clear Register */

+#define GPIO_PXFLGC(n)	(GPIO_BASE + (0x58 + (n)*0x100)) /* Port Flag clear Register */

 #define GPIO_PXOEN(n)	(GPIO_BASE + (0x60 + (n)*0x100)) /* Port Output Disable Register */

 #define GPIO_PXOENS(n)	(GPIO_BASE + (0x64 + (n)*0x100)) /* Port Output Disable Set Register */

 #define GPIO_PXOENC(n)	(GPIO_BASE + (0x68 + (n)*0x100)) /* Port Output Disable Clear Register */

@@ -275,12 +275,12 @@
 #define REG_GPIO_PXINTS(n)	REG32(GPIO_PXINTS((n)))

 #define REG_GPIO_PXINTC(n)	REG32(GPIO_PXINTC((n)))

 

-#define REG_GPIO_PXIM(n)	REG32(GPIO_PXIM((n)))   /* 1: mask pin interrupt */

-#define REG_GPIO_PXIMS(n)	REG32(GPIO_PXIMS((n)))

-#define REG_GPIO_PXIMC(n)	REG32(GPIO_PXIMC((n)))

-//#define REG_GPIO_PXMASK(n)	REG32(GPIO_PXMASK((n)))   /* 1: mask pin interrupt */

-//#define REG_GPIO_PXMASKS(n)	REG32(GPIO_PXMASKS((n)))

-//#define REG_GPIO_PXMASKC(n)	REG32(GPIO_PXMASKC((n)))

+#define REG_GPIO_PXMASK(n)	REG32(GPIO_PXMASK((n)))   /* 1: mask pin interrupt */

+#define REG_GPIO_PXMASKS(n)	REG32(GPIO_PXMASKS((n)))

+#define REG_GPIO_PXMASKC(n)	REG32(GPIO_PXMASKC((n)))

+#define REG_GPIO_PXMASK(n)	REG32(GPIO_PXMASK((n)))   /* 1: mask pin interrupt */

+#define REG_GPIO_PXMASKS(n)	REG32(GPIO_PXMASKS((n)))

+#define REG_GPIO_PXMASKC(n)	REG32(GPIO_PXMASKC((n)))

 #define REG_GPIO_PXPAT1(n)	REG32(GPIO_PXPAT1((n)))   /* 1: disable pull up/down */

 #define REG_GPIO_PXPAT1S(n)	REG32(GPIO_PXPAT1S((n)))

 #define REG_GPIO_PXPAT1C(n)	REG32(GPIO_PXPAT1C((n)))

@@ -355,9 +355,9 @@ do {						\
 

 #if 0

 /*

- * MII_TXD0- D3 MII_TXEN MII_TXCLK MII_COL 

+ * MII_TXD0- D3 MII_TXEN MII_TXCLK MII_COL

  * MII_RXER MII_RXDV MII_RXCLK MII_RXD0 - D3

- * MII_CRS MII_MDC MII_MDIO 

+ * MII_CRS MII_MDC MII_MDIO

  */

 #define __gpio_as_eth()				\

 do {						\

@@ -379,15 +379,15 @@ do {						\
 #define __gpio_as_eth()				\

 do {						\

 	REG_GPIO_PXINTC(1) =  0x00000010;	\

-	REG_GPIO_PXIMC(1) = 0x00000010;	\

+	REG_GPIO_PXMASKC(1) = 0x00000010;	\

 	REG_GPIO_PXPAT1S(1) = 0x00000010;	\

 	REG_GPIO_PXPAT0C(1) = 0x00000010;	\

 	REG_GPIO_PXINTC(3) =  0x3c000000;	\

-	REG_GPIO_PXIMC(3) = 0x3c000000;	\

+	REG_GPIO_PXMASKC(3) = 0x3c000000;	\

 	REG_GPIO_PXPAT1C(3) = 0x3c000000;	\

 	REG_GPIO_PXPAT0S(3) = 0x3c000000;	\

 	REG_GPIO_PXINTC(5) =  0x0000fff0;	\

-	REG_GPIO_PXIMC(5) = 0x0000fff0;	\

+	REG_GPIO_PXMASKC(5) = 0x0000fff0;	\

 	REG_GPIO_PXPAT1C(5) = 0x0000fff0;	\

 	REG_GPIO_PXPAT0C(5) = 0x0000fff0;	\

 } while (0)

@@ -398,10 +398,10 @@ do {						\
  */

 #define __gpio_as_uart0()			\

 do {						\

-	REG_GPIO_PXINTC(5) = 0x00000005;	\

-	REG_GPIO_PXMASKC(5) = 0x00000005;	\

-	REG_GPIO_PXPAT1C(5) = 0x00000005;	\

-	REG_GPIO_PXPAT0C(5) = 0x00000005;	\

+	REG_GPIO_PXINTC(5) = 0x00000009;	\

+	REG_GPIO_PXMASKC(5) = 0x00000009;	\

+	REG_GPIO_PXPAT1C(5) = 0x00000009;	\

+	REG_GPIO_PXPAT0C(5) = 0x00000009;	\

 } while (0)

 

 

@@ -410,7 +410,7 @@ do {						\
  */

 #define __gpio_as_uart0_ctsrts()		\

 do {						\

-	REG_GPIO_PXFUNS(5) = 0x0000000f;	\

+	REG_GPIO_PXFUN1S(5) = 0x0000000f;	\

 	REG_GPIO_PXTRGC(5) = 0x0000000f;	\

 	REG_GPIO_PXSELC(5) = 0x0000000f;	\

 	REG_GPIO_PXPES(5) = 0x0000000f;		\

@@ -495,6 +495,13 @@ do {						\
 	REG_GPIO_PXPES(4)  = 0x00000328;	\

 }

 

+#define __gpio_as_uart4()			\

+do {						\

+	REG_GPIO_PXINTC(2)  = 0x00100400;	\

+	REG_GPIO_PXMASKC(2) = 0x00100400;	\

+	REG_GPIO_PXPAT1C(2) = 0x00100400;	\

+	REG_GPIO_PXPAT0C(2) = 0x00100400;	\

+} while (0)

 /*

  * SD0 ~ SD7, CS1#, CLE, ALE, FRE#, FWE#, FRB#

  * @n: chip select number(1 ~ 6)

@@ -502,45 +509,55 @@ do {						\
 #define __gpio_as_nand_8bit(n)						\

 do {		              						\

 									\

-	REG_GPIO_PXFUNS(0) = 0x000c00ff; /* SD0 ~ SD7, CS1#, FRE#, FWE# */ \

-	REG_GPIO_PXSELC(0) = 0x000c00ff;				\

-	REG_GPIO_PXTRGC(0) = 0x000c00ff;				\

-	REG_GPIO_PXPES(0) = 0x000c00ff;					\

-	REG_GPIO_PXFUNS(1) = 0x00000003; /* CLE(SA2), ALE(SA3) */	\

-	REG_GPIO_PXSELC(1) = 0x00000003;				\

-	REG_GPIO_PXTRGC(1) = 0x00000003;				\

-	REG_GPIO_PXPES(1) = 0x00000003;					\

+	REG_GPIO_PXINTC(0) = 0x000c00ff; /* SD0 ~ SD7, CS1#, FRE#, FWE# */ \

+	REG_GPIO_PXMASKC(0) = 0x000c00ff;				\

+	REG_GPIO_PXPAT1C(0) = 0x000c00ff;				\

+	REG_GPIO_PXPAT0C(0) = 0x000c00ff;				\

+	REG_GPIO_PXPENS(0) = 0x000c00ff;				\

 									\

-	REG_GPIO_PXFUNS(0) = 0x00200000 << ((n)-1); /* CSn */		\

-	REG_GPIO_PXSELC(0) = 0x00200000 << ((n)-1);			\

-	REG_GPIO_PXPES(0) = 0x00200000 << ((n)-1);			\

+	REG_GPIO_PXINTC(1) = 0x00000003; /* CLE(SA2), ALE(SA3) */	\

+	REG_GPIO_PXMASKC(1) = 0x00000003;				\

+	REG_GPIO_PXPAT1C(1) = 0x00000003;				\

+	REG_GPIO_PXPAT0C(1) = 0x00000003;				\

+	REG_GPIO_PXPENS(1) = 0x00000003;				\

 									\

- 	REG_GPIO_PXFUNC(0) = 0x00100000; /* FRB#(input) */		\

-	REG_GPIO_PXSELC(0) = 0x00100000;				\

-	REG_GPIO_PXDIRC(0) = 0x00100000;				\

-	REG_GPIO_PXPES(0) = 0x00100000;					\

+	REG_GPIO_PXINTC(0) = 0x00200000 << ((n)-1); /* CSn */		\

+	REG_GPIO_PXMASKC(0) = 0x00200000 << ((n)-1);			\

+	REG_GPIO_PXPAT1C(0) = 0x00200000 << ((n)-1);			\

+	REG_GPIO_PXPAT0C(0) = 0x00200000 << ((n)-1);			\

+	REG_GPIO_PXPENS(0) = 0x00200000 << ((n)-1);			\

+									\

+	REG_GPIO_PXINTC(0) = 0x00100000; /* FRB#(input) */		\

+	REG_GPIO_PXMASKS(0) = 0x00100000;				\

+	REG_GPIO_PXPAT1S(0) = 0x00100000;				\

+	REG_GPIO_PXPENS(0) = 0x00100000;				\

 } while (0)

 

 #define __gpio_as_nand_16bit(n)						\

 do {		              						\

 									\

-	REG_GPIO_PXFUNS(0) = 0x000cffff; /* SD0 ~ SD15, CS1#, FRE#, FWE# */ \

-	REG_GPIO_PXSELC(0) = 0x000cffff;				\

-	REG_GPIO_PXTRGC(0) = 0x000cffff;				\

-	REG_GPIO_PXPES(0) = 0x000cffff;					\

-	REG_GPIO_PXFUNS(1) = 0x00000003; /* CLE(SA2), ALE(SA3) */	\

-	REG_GPIO_PXSELC(1) = 0x00000003;				\

-	REG_GPIO_PXTRGC(1) = 0x00000003;				\

-	REG_GPIO_PXPES(1) = 0x00000003;					\

+	REG_GPIO_PXINTC(0) = 0x000cffff; /* SD0 ~ SD15, CS1#, FRE#, FWE# */ \

+	REG_GPIO_PXMASKC(0) = 0x000cffff;				\

+	REG_GPIO_PXPAT1C(0) = 0x000cffff;				\

+	REG_GPIO_PXPAT0C(0) = 0x000cffff;				\

+	REG_GPIO_PXPENS(0) = 0x000cffff;				\

+									\

+	REG_GPIO_PXINTC(1) = 0x00000003; /* CLE(SA2), ALE(SA3) */	\

+	REG_GPIO_PXMASKC(1) = 0x00000003;				\

+	REG_GPIO_PXPAT1C(1) = 0x00000003;				\

+	REG_GPIO_PXPAT0C(1) = 0x00000003;				\

+	REG_GPIO_PXPENS(1) = 0x00000003;				\

 									\

-	REG_GPIO_PXFUNS(0) = 0x00200000 << ((n)-1); /* CSn */		\

-	REG_GPIO_PXSELC(0) = 0x00200000 << ((n)-1);			\

-	REG_GPIO_PXPES(0) = 0x00200000 << ((n)-1);			\

+	REG_GPIO_PXINTC(0) = 0x00200000 << ((n)-1); /* CSn */		\

+	REG_GPIO_PXMASKC(0) = 0x00200000 << ((n)-1);			\

+	REG_GPIO_PXPAT1C(0) = 0x00200000 << ((n)-1);			\

+	REG_GPIO_PXPAT0C(0) = 0x00200000 << ((n)-1);			\

+	REG_GPIO_PXPENS(0) = 0x00200000 << ((n)-1);			\

 									\

- 	REG_GPIO_PXFUNC(0) = 0x00100000; /* FRB#(input) */		\

-	REG_GPIO_PXSELC(0) = 0x00100000;				\

-	REG_GPIO_PXDIRC(0) = 0x00100000;				\

-	REG_GPIO_PXPES(0) = 0x00100000;					\

+	REG_GPIO_PXINTC(0) = 0x00100000; /* FRB#(input) */		\

+	REG_GPIO_PXMASKS(0) = 0x00100000;				\

+	REG_GPIO_PXPAT1S(0) = 0x00100000;				\

+	REG_GPIO_PXPENS(0) = 0x00100000;					\

 } while (0)

 

 /*

@@ -600,10 +617,10 @@ do {	               							\
  */

 #define __gpio_as_lcd_8bit()			\

 do {						\

-	REG_GPIO_PXFUNS(2) = 0x000c03ff;	\

-	REG_GPIO_PXTRGC(2) = 0x000c03ff;	\

-	REG_GPIO_PXSELC(2) = 0x000c03ff;	\

-	REG_GPIO_PXPES(2) = 0x000c03ff;		\

+	REG_GPIO_PXINTC(2) = 0x000c03ff;	\

+	REG_GPIO_PXMASKC(2)  = 0x000c03ff;		\

+	REG_GPIO_PXPAT0C(2) = 0x000c03ff;	\

+	REG_GPIO_PXPAT1C(2) = 0x000c03ff;		\

 } while (0)

 

 /*

@@ -612,10 +629,10 @@ do {						\
  */

 #define __gpio_as_lcd_16bit()			\

 do {						\

-	REG_GPIO_PXFUNS(2) = 0x0f8ff3f8;	\

-	REG_GPIO_PXTRGC(2) = 0x0f8ff3f8;	\

-	REG_GPIO_PXSELC(2) = 0x0f8ff3f8;	\

-	REG_GPIO_PXPES(2) = 0x0f8ff3f8;		\

+	REG_GPIO_PXINTC(2) = 0x0f8ff3f8;	\

+	REG_GPIO_PXMASKC(2) = 0x0f8ff3f8;	\

+	REG_GPIO_PXPAT0C(2) = 0x0f8ff3f8;	\

+	REG_GPIO_PXPAT1C(2) = 0x0f8ff3f8;		\

 } while (0)

 

 /*

@@ -624,10 +641,10 @@ do {						\
  */

 #define __gpio_as_lcd_18bit()			\

 do {						\

-	REG_GPIO_PXFUNS(2) = 0x0fcff3fc;	\

-	REG_GPIO_PXTRGC(2) = 0x0fcff3fc;	\

-	REG_GPIO_PXSELC(2) = 0x0fcff3fc;	\

-	REG_GPIO_PXPES(2) = 0x0fcff3fc;		\

+	REG_GPIO_PXINTC(2) = 0x0fcff3fc;	\

+	REG_GPIO_PXMASKC(2) = 0x0fcff3fc;	\

+	REG_GPIO_PXPAT0C(2) = 0x0fcff3fc;	\

+	REG_GPIO_PXPAT1C(2) = 0x0fcff3fc;		\

 } while (0)

 

 /*

@@ -636,10 +653,10 @@ do {						\
  */

 #define __gpio_as_lcd_24bit()			\

 do {						\

-	REG_GPIO_PXFUNS(2) = 0x0fffffff;	\

-	REG_GPIO_PXTRGC(2) = 0x0fffffff;	\

-	REG_GPIO_PXSELC(2) = 0x0fffffff;	\

-	REG_GPIO_PXPES(2) = 0x0fffffff;		\

+	REG_GPIO_PXINTC(2) = 0x0fffffff;	\

+	REG_GPIO_PXMASKC(2)  = 0x0fffffff;	\

+	REG_GPIO_PXPAT0C(2) = 0x0fffffff;	\

+	REG_GPIO_PXPAT1C(2) = 0x0fffffff;		\

 } while (0)

 

 /*

@@ -647,25 +664,25 @@ do {						\
  */

 #define __gpio_as_lcd_special()			\

 do {						\

-	REG_GPIO_PXFUNS(2) = 0x0fffffff;	\

-	REG_GPIO_PXTRGC(2) = 0x0fffffff;	\

-	REG_GPIO_PXSELC(2) = 0x0feffbfc;	\

-	REG_GPIO_PXSELS(2) = 0x00100403;	\

-	REG_GPIO_PXPES(2) = 0x0fffffff;		\

+	REG_GPIO_PXINTC(2) = 0x0fffffff;	\

+	REG_GPIO_PXMASKC(2) = 0x0fffffff;	\

+	REG_GPIO_PXPAT0C(2) = 0x0feffbfc;	\

+	REG_GPIO_PXPAT0S(2) = 0x00100403;	\

+	REG_GPIO_PXPAT1C(2) = 0x0fffffff;		\

 } while (0)

 

 /*

  * CIM_D0~CIM_D7, CIM_MCLK, CIM_PCLK, CIM_VSYNC, CIM_HSYNC

  */

-#define __gpio_as_cim()				\

-do {						\

-	REG_GPIO_PXFUNS(1) = 0x0003ffc0;	\

-	REG_GPIO_PXTRGC(1) = 0x0003ffc0;	\

-	REG_GPIO_PXSELC(1) = 0x0003ffc0;	\

-	REG_GPIO_PXPES(1)  = 0x0003ffc0;	\

-} while (0)

+#define __gpio_as_cim()					\

+	do {						\

+		REG_GPIO_PXINTC(1) = 0x0003ffc0;	\

+		REG_GPIO_PXMASKC(1) = 0x0003ffc0;		\

+		REG_GPIO_PXPAT1C(1) = 0x0003ffc0;	\

+		REG_GPIO_PXPAT0C(1) = 0x0003ffc0;	\

+	} while (0)

 

-/* 

+/*

  * SDATO, SDATI, BCLK, SYNC, SCLK_RSTN(gpio sepc) or

  * SDATA_OUT, SDATA_IN, BIT_CLK, SYNC, SCLK_RESET(aic spec)

  */

@@ -694,32 +711,26 @@ do {						\
  */

 #define __gpio_as_msc0_8bit()			\

 do {						\

-	REG_GPIO_PXFUNS(4) = 0x3ff00000;	\

-	REG_GPIO_PXTRGC(4) = 0x3ff00000;	\

-	REG_GPIO_PXSELC(4) = 0x3ff00000;	\

-	REG_GPIO_PXPES(4)  = 0x3ff00000;	\

+	REG_GPIO_PXINTC(4) = 0x3ff00000;	\

+	REG_GPIO_PXMASKC(4)  = 0x3ff00000;	\

+	REG_GPIO_PXPAT0C(4) = 0x3ff00000;	\

+	REG_GPIO_PXPAT1C(4) = 0x3ff00000;	\

 } while (0)

 

-/*

- * MSC0_CMD, MSC0_CLK, MSC0_D0 ~ MSC0_D3

- */

-#define __gpio_as_msc0_4bit()			\

+#define __gpio_as_msc1_8bit()			\

 do {						\

-	REG_GPIO_PXFUNS(4) = 0x30f00000;	\

-	REG_GPIO_PXTRGC(4) = 0x30f00000;	\

-	REG_GPIO_PXSELC(4) = 0x30f00000;	\

-	REG_GPIO_PXPES(4)  = 0x30f00000;	\

+	REG_GPIO_PXINTC(4) = 0x3ff00000;	\

+	REG_GPIO_PXMASKC(4)  = 0x3ff00000;	\

+	REG_GPIO_PXPAT0S(4) = 0x3ff00000;	\

+	REG_GPIO_PXPAT1C(4) = 0x3ff00000;	\

 } while (0)

 

-/*

- * MSC1_CMD, MSC1_CLK, MSC1_D0 ~ MSC1_D3

- */

-#define __gpio_as_msc1_4bit()			\

+#define __gpio_as_msc2_8bit()			\

 do {						\

-	REG_GPIO_PXFUNS(3) = 0x3f00000;	\

-	REG_GPIO_PXTRGC(3) = 0x3f00000;	\

-	REG_GPIO_PXSELC(3) = 0x3f00000;	\

-	REG_GPIO_PXPES(3)  = 0x3f00000;	\

+	REG_GPIO_PXINTC(4) = 0x3ff00000;	\

+	REG_GPIO_PXMASKC(4)  = 0x3ff00000;	\

+	REG_GPIO_PXPAT0C(4) = 0x3ff00000;	\

+	REG_GPIO_PXPAT1S(4) = 0x3ff00000;	\

 } while (0)

 

 #if 0

@@ -728,11 +739,10 @@ do {						\
  */

 #define __gpio_as_msc0_4bit()			\

 do {						\

-	REG_GPIO_PXFUNS(2) = 0x38400300;	\

-	REG_GPIO_PXTRGC(2) = 0x38400300;	\

-	REG_GPIO_PXSELS(2) = 0x30400300;	\

-	REG_GPIO_PXSELC(2) = 0x08000000;	\

-	REG_GPIO_PXPES(2)  = 0x38400300;	\

+	REG_GPIO_PXINTC(4) = 0x30f00000;	\

+	REG_GPIO_PXMASKC(4)  = 0x30f00000;	\

+	REG_GPIO_PXPAT0C(4) = 0x30f00000;	\

+	REG_GPIO_PXPAT1C(4) = 0x30f00000;	\

 } while (0)

 

 /*

@@ -740,23 +750,24 @@ do {						\
  */

 #define __gpio_as_msc1_4bit()			\

 do {						\

-	REG_GPIO_PXFUNS(1) = 0xfc000000;	\

-	REG_GPIO_PXTRGC(1) = 0xfc000000;	\

-	REG_GPIO_PXSELC(1) = 0xfc000000;	\

-	REG_GPIO_PXPES(1)  = 0xfc000000;	\

+	REG_GPIO_PXINTC(3) = 0x3f00000;	\

+	REG_GPIO_PXMASKC(3) = 0x3f00000;	\

+	REG_GPIO_PXPAT0C(3) = 0x3f00000;	\

+	REG_GPIO_PXPAT1C(3)  = 0x3f00000;	\

 } while (0)

-#endif

+

 

 /* Port B

  * MSC2_CMD, MSC2_CLK, MSC2_D0 ~ MSC2_D3

  */

 #define __gpio_as_msc2_4bit_1()			\

 do {						\

-	REG_GPIO_PXFUNS(1) = 0xf0300000;	\

-	REG_GPIO_PXTRGC(1) = 0xf0300000;	\

-	REG_GPIO_PXSELC(1) = 0xf0300000;	\

-	REG_GPIO_PXPES(1)  = 0xf0300000;	\

+	REG_GPIO_PXINTC(1) = 0xf0300000;	\

+	REG_GPIO_PXMASKC(1) = 0xf0300000;	\

+	REG_GPIO_PXPAT0C(1) = 0xf0300000;	\

+	REG_GPIO_PXPAT1C(1)  = 0xf0300000;	\

 } while (0)

+#endif

 

 #define __gpio_as_msc 	__gpio_as_msc0_4bit /* default as msc0 4bit */

 #define __gpio_as_msc0 	__gpio_as_msc0_4bit /* msc0 default as 4bit */

@@ -765,25 +776,19 @@ do {						\
 /*

  * TSCLK, TSSTR, TSFRM, TSFAIL, TSDI0~7

  */

-#define __gpio_as_tssi_1()			\

-do {						\

-	REG_GPIO_PXFUNS(1) = 0x0003ffc0;	\

-	REG_GPIO_PXTRGC(1) = 0x0003ffc0;	\

-	REG_GPIO_PXSELS(1) = 0x0003ffc0;	\

-	REG_GPIO_PXPES(1)  = 0x0003ffc0;	\

+#define __gpio_as_tssi()                        \

+do {                                            \

+        REG_GPIO_PXINTC(1) = 0xf0300000;        \

+        REG_GPIO_PXMASKC(1)  = 0xf0300000;                \

+        REG_GPIO_PXPAT0S(1) = 0xf0300000;       \

+        REG_GPIO_PXPAT1S(1) = 0xf0300000;               \

+                                                        \

+        REG_GPIO_PXINTC(1) = 0x0fc00000;        \

+        REG_GPIO_PXMASKC(1)  = 0x0fc00000;                \

+        REG_GPIO_PXPAT0C(1) = 0x0fc00000;       \

+        REG_GPIO_PXPAT1C(1) = 0x0fc00000;               \

 } while (0)

 

-/*

- * TSCLK, TSSTR, TSFRM, TSFAIL, TSDI0~7

- */

-#define __gpio_as_tssi_2()			\

-do {						\

-	REG_GPIO_PXFUNS(1) = 0xfff00000;	\

-	REG_GPIO_PXTRGC(1) = 0x0fc00000;	\

-	REG_GPIO_PXTRGS(1) = 0xf0300000;	\

-	REG_GPIO_PXSELC(1) = 0xfff00000;	\

-	REG_GPIO_PXPES(1)  = 0xfff00000;	\

-} while (0)

 

 /*

  * SSI_CE0, SSI_CE1, SSI_GPC, SSI_CLK, SSI_DT, SSI_DR

@@ -823,17 +828,25 @@ do {						\
 	REG_GPIO_PXPES(5)  = 0xf0300000;	\

 } while (0)

 

+

 /*

  * I2C_SCK, I2C_SDA

  */

-#define __gpio_as_i2c(n)		       \

-do {						\

-	REG_GPIO_PXFUNS(3+(n)) = 0xc0000000;	\

-	REG_GPIO_PXTRGC(3+(n)) = 0xc0000000;	\

-	REG_GPIO_PXSELC(3+(n)) = 0xc0000000;	\

-	REG_GPIO_PXPES(3+(n))  = 0xc0000000;	\

-} while (0)

-

+#define __gpio_as_i2c(n)				\

+	do {						\

+		REG_GPIO_PXINTC(3 + (n)) = 0xC0000000;	\

+		REG_GPIO_PXMASKC(3 + (n)) = 0xC0000000;	\

+		REG_GPIO_PXPAT1C(3 + (n)) = 0xC0000000;	\

+		REG_GPIO_PXPAT0C(3 + (n)) = 0xC0000000;	\

+	} while (0)

+

+#define __gpio_as_i2c2()				\

+	do {						\

+		REG_GPIO_PXINTC(5) = 0x00030000;	\

+		REG_GPIO_PXMASKC(5) = 0x00030000;	\

+		REG_GPIO_PXPAT1S(5) = 0x00030000;	\

+		REG_GPIO_PXPAT0C(5) = 0x00030000;	\

+	} while(0)

 /*

  * PWM0

  */

@@ -936,7 +949,7 @@ do {	\
 #define __gpio_port_as_output0(p, o)		\

 do {						\

     REG_GPIO_PXINTC(p) = (1 << (o));		\

-    REG_GPIO_PXIMS(p) = (1 << (o));		\

+    REG_GPIO_PXMASKS(p) = (1 << (o));		\

     REG_GPIO_PXPAT1C(p) = (1 << (o));		\

     REG_GPIO_PXPAT0C(p) = (1 << (o));		\

 } while (0)

@@ -944,7 +957,7 @@ do {						\
 #define __gpio_port_as_output1(p, o)		\

 do {						\

     REG_GPIO_PXINTC(p) = (1 << (o));		\

-    REG_GPIO_PXINTS(p) = (1 << (o));		\

+    REG_GPIO_PXMASKS(p) = (1 << (o));		\

     REG_GPIO_PXPAT1C(p) = (1 << (o));		\

     REG_GPIO_PXPAT0S(p) = (1 << (o));		\

 } while (0)

@@ -1014,41 +1027,38 @@ do {						\
 	unsigned int p, o;			\

 	p = (n) / 32;				\

 	o = (n) % 32;				\

-	REG_GPIO_PXIMS(p) = (1 << o);		\

+	REG_GPIO_PXMASKS(p) = (1 << o);		\

 	REG_GPIO_PXTRGC(p) = (1 << o);		\

 	REG_GPIO_PXFUNC(p) = (1 << o);		\

 	REG_GPIO_PXSELS(p) = (1 << o);		\

 	REG_GPIO_PXDIRS(p) = (1 << o);		\

 	REG_GPIO_PXFLGC(p) = (1 << o);		\

-	REG_GPIO_PXIMC(p) = (1 << o);		\

+	REG_GPIO_PXMASKC(p) = (1 << o);		\

 } while (0)

 

 #define __gpio_as_irq_low_level(n)		\

-do {						\

-	unsigned int p, o;			\

-	p = (n) / 32;				\

-	o = (n) % 32;				\

-	REG_GPIO_PXIMS(p) = (1 << o);		\

-	REG_GPIO_PXTRGC(p) = (1 << o);		\

-	REG_GPIO_PXFUNC(p) = (1 << o);		\

-	REG_GPIO_PXSELS(p) = (1 << o);		\

-	REG_GPIO_PXDIRC(p) = (1 << o);		\

-	REG_GPIO_PXFLGC(p) = (1 << o);		\

-	REG_GPIO_PXIMC(p) = (1 << o);		\

-} while (0)

+	do {					\

+		unsigned int p, o;		\

+		p = (n) / 32;			\

+		o = (n) % 32;			\

+		REG_GPIO_PXINTS(p) = (1 << o);	\

+		REG_GPIO_PXMASKC(p) = (1 << o);	\

+		REG_GPIO_PXPAT1C(p) = (1 << o);	\

+		REG_GPIO_PXPAT0C(p) = (1 << o);	\

+	} while (0)

 

 #define __gpio_as_irq_rise_edge(n)		\

 do {						\

 	unsigned int p, o;			\

 	p = (n) / 32;				\

 	o = (n) % 32;				\

-	REG_GPIO_PXIMS(p) = (1 << o);		\

+	REG_GPIO_PXMASKS(p) = (1 << o);		\

 	REG_GPIO_PXTRGS(p) = (1 << o);		\

 	REG_GPIO_PXFUNC(p) = (1 << o);		\

 	REG_GPIO_PXSELS(p) = (1 << o);		\

 	REG_GPIO_PXDIRS(p) = (1 << o);		\

 	REG_GPIO_PXFLGC(p) = (1 << o);		\

-	REG_GPIO_PXIMC(p) = (1 << o);		\

+	REG_GPIO_PXMASKC(p) = (1 << o);		\

 } while (0)

 

 #define __gpio_as_irq_fall_edge(n)		\

@@ -1056,13 +1066,10 @@ do {						\
 	unsigned int p, o;			\

 	p = (n) / 32;				\

 	o = (n) % 32;				\

-	REG_GPIO_PXIMS(p) = (1 << o);		\

-	REG_GPIO_PXTRGS(p) = (1 << o);		\

-	REG_GPIO_PXFUNC(p) = (1 << o);		\

-	REG_GPIO_PXSELS(p) = (1 << o);		\

-	REG_GPIO_PXDIRC(p) = (1 << o);		\

-	REG_GPIO_PXFLGC(p) = (1 << o);		\

-	REG_GPIO_PXIMC(p) = (1 << o);		\

+	REG_GPIO_PXINTS(p) = (1 << o);  \

+        REG_GPIO_PXMASKC(p) = (1 << o);   \

+        REG_GPIO_PXPAT1S(p) = (1 << o); \

+        REG_GPIO_PXPAT0C(p) = (1 << o); \

 } while (0)

 

 #define __gpio_mask_irq(n)			\

@@ -1070,7 +1077,7 @@ do {						\
 	unsigned int p, o;			\

 	p = (n) / 32;				\

 	o = (n) % 32;				\

-	REG_GPIO_PXIMS(p) = (1 << o);		\

+	REG_GPIO_PXMASKS(p) = (1 << o);		\

 } while (0)

 

 #define __gpio_unmask_irq(n)			\

@@ -1078,7 +1085,7 @@ do {						\
 	unsigned int p, o;			\

 	p = (n) / 32;				\

 	o = (n) % 32;				\

-	REG_GPIO_PXIMC(p) = (1 << o);		\

+	REG_GPIO_PXMASKC(p) = (1 << o);		\

 } while (0)

 

 #define __gpio_ack_irq(n)			\

diff --git a/arch/mips/include/asm/mach-jz4810/jz4810i2c.h b/arch/mips/include/asm/mach-jz4810/jz4810i2c.h
index 90f86b175d1..130367d4b64 100644
--- a/arch/mips/include/asm/mach-jz4810/jz4810i2c.h
+++ b/arch/mips/include/asm/mach-jz4810/jz4810i2c.h
@@ -9,9 +9,11 @@
 #ifndef __JZ4810I2C_H__

 #define __JZ4810I2C_H__

 

+#define JZ_I2C_NUM	3

 

 #define	I2C0_BASE	0xB0050000

 #define	I2C1_BASE	0xB0051000

+#define I2C2_BASE	0xB0055000

 

 

 /*************************************************************************

@@ -42,10 +44,16 @@
 #define	I2C_CGC(n)    		(I2C0_BASE + (n)*0x1000 + 0x68)

 #define	I2C_ENB(n)     		(I2C0_BASE + (n)*0x1000 + 0x6C)

 #define	I2C_STA(n)     		(I2C0_BASE + (n)*0x1000 + 0x70)

+#define I2C_TXFLR(n)		(I2C0_BASE + (n)*0x1000 + 0x74)

+#define I2C_RXFLR(n)		(I2C0_BASE + (n)*0x1000 + 0x78)

 #define	I2C_TXABRT(n)		(I2C0_BASE + (n)*0x1000 + 0x80)

+#define I2C_DMACR(n)            (I2C0_BASE + (n)*0x1000 + 0x88)

+#define I2C_DMATDLR(n)          (I2C0_BASE + (n)*0x1000 + 0x8c)

+#define I2C_DMARDLR(n)          (I2C0_BASE + (n)*0x1000 + 0x90)

 #define	I2C_SDASU(n)		(I2C0_BASE + (n)*0x1000 + 0x94)

 #define	I2C_ACKGC(n)		(I2C0_BASE + (n)*0x1000 + 0x98)

 #define	I2C_ENSTA(n)		(I2C0_BASE + (n)*0x1000 + 0x9C)

+#define I2C_SDAHD(n)		(I2C0_BASE + (n)*0x1000 + 0xD0)

 

 #define	REG_I2C_CTRL(n)		REG8(I2C_CTRL(n)) /* I2C Control Register (I2C_CTRL) */

 #define	REG_I2C_TAR(n)		REG16(I2C_TAR(n)) /* I2C target address (I2C_TAR) */

@@ -72,15 +80,22 @@
 #define REG_I2C_CGC(n)		REG8(I2C_CGC(n))

 #define REG_I2C_ENB(n)		REG8(I2C_ENB(n))

 #define REG_I2C_STA(n)		REG8(I2C_STA(n))

+#define REG_I2C_TXFLR(n)	REG8(I2C_TXFLR(n))

+#define REG_I2C_RXFLR(n)	REG8(I2C_RXFLR(n))

 #define REG_I2C_TXABRT(n)      	REG16(I2C_TXABRT(n))

+#define REG_I2C_DMACR(n)        REG8(I2C_DMACR(n))

+#define REG_I2C_DMATDLR(n)      REG8(I2C_DMATDLR(n))

+#define REG_I2C_DMARDLR(n)      REG8(I2C_DMARDLR(n))

 #define REG_I2C_SDASU(n)       	REG8(I2C_SDASU(n))

 #define REG_I2C_ACKGC(n)       	REG8(I2C_ACKGC(n))

 #define REG_I2C_ENSTA(n)       	REG8(I2C_ENSTA(n))

+#define REG_I2C_SDAHD(n)	REG16(I2C_SDAHD(n))

 

 /* I2C Control Register (I2C_CTRL) */

 

+#define I2C_CTRL_STPHLD		(1 << 7)

 #define I2C_CTRL_SLVDIS		(1 << 6) /* after reset slave is disabled*/

-#define I2C_CTRL_REST		(1 << 5)	

+#define I2C_CTRL_REST		(1 << 5)

 #define I2C_CTRL_MATP		(1 << 4) /* 1: 10bit address 0: 7bit addressing*/

 #define I2C_CTRL_SATP		(1 << 3) /* standard mode 100kbps */

 #define I2C_CTRL_SPDF		(2 << 1) /* fast mode 400kbps */

@@ -105,7 +120,7 @@
 #define I2C_INTST_ISTP			(1 << 9)

 #define I2C_INTST_IACT			(1 << 8)

 #define I2C_INTST_RXDN			(1 << 7)

-#define I2C_INTST_TXABT			(1 << 6) 

+#define I2C_INTST_TXABT			(1 << 6)

 #define I2C_INTST_RDREQ			(1 << 5)

 #define I2C_INTST_TXEMP			(1 << 4)

 #define I2C_INTST_TXOF			(1 << 3)

@@ -143,7 +158,7 @@
 

 /* I2C Enable (I2C_ENB) */

 

-#define I2C_ENB_I2CENB 		(1 << 0) /* Enable the i2c */	

+#define I2C_ENB_I2CENB 		(1 << 0) /* Enable the i2c */

 

 /* I2C Status Register (I2C_STA) */

 

@@ -179,10 +194,16 @@
 #define I2C_ENSTA_SLVRDLST		(1 << 2)

 #define I2C_ENSTA_SLVDISB 		(1 << 1)

 #define I2C_ENSTA_I2CEN 		(1 << 0) /* when read as 1, i2c is deemed to be in an enabled state

-						    when read as 0, i2c is deemed completely inactive. The cpu can 

-						 safely read this bit anytime .When this bit is read as 0 ,the cpu can 

+						    when read as 0, i2c is deemed completely inactive. The cpu can

+						 safely read this bit anytime .When this bit is read as 0 ,the cpu can

 						 safely read SLVRDLST and SLVDISB */

 

+#define I2C_SDASU_SETUP_TIME_BASE	0

+#define I2C_SDASU_SETUP_TIME_MASK	0xff

+

+#define I2C_SDAHD_HOLD_TIME_BASE	0

+#define I2C_SDAHD_HOLD_TIME_MASK	0xff

+#define I2C_SDAHD_HOLD_TIME_EN		(1 << 8)

 

 #ifndef __MIPS_ASSEMBLER

 

@@ -194,7 +215,7 @@
 #define __i2c_disable(n)       	( REG_I2C_ENB(n) = 0 )

 

 #define __i2c_is_enable(n)       ( REG_I2C_ENSTA(n) & I2C_ENB_I2CENB )

-#define __i2c_is_disable(n)      ( ~(REG_I2C_ENSTA(n) & I2C_ENB_I2CENB) )

+#define __i2c_is_disable(n)      ( !(REG_I2C_ENSTA(n) & I2C_ENB_I2CENB) )

 

 #define __i2c_abrt(n)            ( REG_I2C_TXABRT(n) != 0 )

 #define __i2c_master_active(n)   ( REG_I2C_STA(n) & I2C_STA_MSTACT )

@@ -202,6 +223,43 @@
 #define __i2c_txfifo_is_empty(n)     ( REG_I2C_STA(n) & I2C_STA_TFE )

 #define __i2c_clear_interrupts(ret,n)    ( ret = REG_I2C_CINTR(n) )

 

+#define __i2c_dma_rd_enable(n)        SETREG8(I2C_DMACR(n),1 << 0)

+#define __i2c_dma_rd_disable(n)       CLRREG8(I2C_DMACR(n),1 << 0)

+#define __i2c_dma_td_enable(n)        SETREG8(I2C_DMACR(n),1 << 1)

+#define __i2c_dma_td_disable(n)       CLRREG8(I2C_DMACR(n),1 << 1)

+

+#define __i2c_send_stop(n)           CLRREG8(I2C_SHCNT(n), I2C_CTRL_STPHLD)

+#define __i2c_nsend_stop(n)          SETREG8(I2C_SHCNT(n), I2C_CTRL_STPHLD)

+

+#define __i2c_set_dma_td_level(n,data) OUTREG8(I2C_DMATDLR(n),data)

+#define __i2c_set_dma_rd_level(n,data) OUTREG8(I2C_DMARDLR(n),data)

+

+#define __i2c_hold_time_enable(n) SETREG16(I2C_SDAHD(n), I2C_SDAHD_HOLD_TIME_EN)

+#define __i2c_hold_time_disable(n) CLRREG16(I2C_SDAHD(n), I2C_SDAHD_HOLD_TIME_EN)

+#define __i2c_set_hold_time(n, ht)					\

+	do {								\

+		CLRREG16(I2C_SDAHD(n), I2C_SDAHD_HOLD_TIME_MASK);	\

+		SETREG16(I2C_SDAHD(n), ((ht) & I2C_SDAHD_HOLD_TIME_MASK)); \

+	} while(0)

+

+#define __i2c_set_setup_time(n, su)					\

+	do {								\

+		CLRREG16(I2C_SDASU(n), I2C_SDASU_SETUP_TIME_MASK);	\

+		SETREG16(I2C_SDASU(n), ((su) & I2C_SDASU_SETUP_TIME_MASK)); \

+	} while(0) 

+

+/* I2C standard mode high count register(I2CSHCNT) */

+#define I2CSHCNT_ADJUST(n)      (((n) - 8) < 6 ? 6 : ((n) - 8))

+

+/* I2C standard mode low count register(I2CSLCNT) */

+#define I2CSLCNT_ADJUST(n)      (((n) - 1) < 8 ? 8 : ((n) - 1))

+

+/* I2C fast mode high count register(I2CFHCNT) */

+#define I2CFHCNT_ADJUST(n)      (((n) - 8) < 6 ? 6 : ((n) - 8))

+

+/* I2C fast mode low count register(I2CFLCNT) */

+#define I2CFLCNT_ADJUST(n)      (((n) - 1) < 8 ? 8 : ((n) - 1))

+

 /*

 #define __i2c_set_clk(dev_clk, i2c_clk) \

   ( REG_I2C_GR = (dev_clk) / (16*(i2c_clk)) - 1 )

diff --git a/arch/mips/include/asm/mach-jz4810/jz4810intc.h b/arch/mips/include/asm/mach-jz4810/jz4810intc.h
index c45950d3810..5fe66c6501a 100644
--- a/arch/mips/include/asm/mach-jz4810/jz4810intc.h
+++ b/arch/mips/include/asm/mach-jz4810/jz4810intc.h
@@ -40,7 +40,7 @@
 #define IRQ_UART2	3

 #define IRQ_UART1	4

 #define IRQ_UART0	5

-#define IRQ_SSI2   	6

+#define IRQ_GPU		6

 #define IRQ_SSI1   	7

 #define IRQ_SSI0   	8

 #define IRQ_TSSI	9

@@ -56,7 +56,8 @@
 #define IRQ_ETH		19

 #define IRQ_UHC		20

 #define IRQ_OTG		21

-#define IRQ_MDMA	22

+//#define IRQ_MDMA	22

+#define IRQ_I2C2	22

 #define IRQ_DMAC1	23

 #define IRQ_DMAC0	24

 #define IRQ_TCU2	25

@@ -75,21 +76,24 @@
 #define IRQ_MSC0	37

 #define IRQ_SCC		38

 #define IRQ_BCH		39

-#define IRQ_PCM		40

-

+#define IRQ_PCM0	40

+#define IRQ_PCM1	41

+#define IRQ_UART4	42

+#define IRQ_AOSD        43

+#define IRQ_HARB2	44

+#define IRQ_I2S2	45

+#define IRQ_CPM		47

 

 // 2nd-level interrupts

 

-#define IRQ_DMA_0	46  /* 64 ~ 75 for DMAC0 channel 0 ~ 5 & DMAC1 channel 0 ~ 5 */

-//#define IRQ_DMA_0	32  /* 64 ~ 75 for DMAC0 channel 0 ~ 5 & DMAC1 channel 0 ~ 5 */

-#define IRQ_DMA_1	(IRQ_DMA_0 + HALF_DMA_NUM)  /* 64 ~ 75 for DMAC0 channel 0 ~ 5 & DMAC1 channel 0 ~ 5 */

-#define IRQ_MDMA_0	(IRQ_DMA_0 + MAX_DMA_NUM)   /* 64 ~ 66 for MDMAC channel 0 ~ 2 */

-#define IRQ_BDMA_0  (IRQ_DMA_0 + MAX_DMA_NUM + MAX_MDMA_NUM) /* 61 ~ 63 for BDMA channel 0 ~ 2 */

+#define IRQ_DMA_0	64    /* 64,65,66,67,68,69 */

+#define IRQ_DMA_1	(IRQ_DMA_0 + HALF_DMA_NUM) /* 70,71,72,73,74,75 */

+#define IRQ_MDMA_0	(IRQ_DMA_0 + MAX_DMA_NUM)   /* 76,77,78 */

+#define IRQ_BDMA_0  	(IRQ_MDMA_0 + MAX_MDMA_NUM) /* 79,80,81 */

 

-//#define IRQ_GPIO_0	96  /* 96 to 287 for GPIO pin 0 to 127 */

-#define IRQ_GPIO_0	64  /* 96 to 287 for GPIO pin 0 to 127 */

+#define IRQ_GPIO_0	(IRQ_BDMA_0 + MAX_BDMA_NUM)

 

-#define NUM_INTC	41

+#define NUM_INTC	48

 #define NUM_DMA         MAX_DMA_NUM	/* 12 */

 #define NUM_MDMA        MAX_MDMA_NUM	/* 3 */

 #define NUM_GPIO        MAX_GPIO_NUM	/* GPIO NUM: 192, Jz4810 real num GPIO 178 */

diff --git a/arch/mips/include/asm/mach-jz4810/jz4810lcdc.h b/arch/mips/include/asm/mach-jz4810/jz4810lcdc.h
index 147d5b49441..47af2e8d04e 100644
--- a/arch/mips/include/asm/mach-jz4810/jz4810lcdc.h
+++ b/arch/mips/include/asm/mach-jz4810/jz4810lcdc.h
@@ -125,6 +125,7 @@
 #define LCD_PW1		(LCD_BASE + 0x74) /* DMA Page Width Register 1 */

 #define LCD_CNUM1	(LCD_BASE + 0x78) /* DMA Command Counter Register 1 */

 #define LCD_DESSIZE1	(LCD_BASE + 0x7C) /* Foreground Size in Descriptor 1 Register*/

+#define LCD_PCFG        (LCD_BASE + 0xB0)

 

 #define REG_LCD_CFG	REG32(LCD_CFG)

 #define REG_LCD_CTRL	REG32(LCD_CTRL)

@@ -186,6 +187,7 @@
 #define REG_LCD_PW1	REG32(LCD_PW1)

 #define REG_LCD_CNUM1	REG32(LCD_CNUM1)

 #define REG_LCD_DESSIZE1	REG32(LCD_DESSIZE1)

+#define REG_LCD_PCFG            REG32(LCD_PCFG)

 

 /* LCD Configure Register */

 #define LCD_CFG_LCDPIN_BIT	31  /* LCD pins selection */

@@ -193,7 +195,7 @@
   #define LCD_CFG_LCDPIN_LCD	(0x0 << LCD_CFG_LCDPIN_BIT)

   #define LCD_CFG_LCDPIN_SLCD	(0x1 << LCD_CFG_LCDPIN_BIT)

 #define LCD_CFG_TVEPEH		(1 << 30) /* TVE PAL enable extra halfline signal */

-#define LCD_CFG_FUHOLD		(1 << 29) /* hold pixel clock when outFIFO underrun */

+//#define LCD_CFG_FUHOLD	(1 << 29) /* hold pixel clock when outFIFO underrun *//*keep this bit to 0*/

 #define LCD_CFG_NEWDES		(1 << 28) /* use new descripter. old: 4words, new:8words */

 #define LCD_CFG_PALBP		(1 << 27) /* bypass data format and alpha blending */

 #define LCD_CFG_TVEN		(1 << 26) /* indicate the terminal is lcd or tv */

@@ -245,11 +247,13 @@
 					    0: 16-bit data correspond with LCD_D[15:0]

 					    1: 16-bit data correspond with LCD_D[17:10], LCD_D[8:1] */

 #define LCD_CTRL_BST_BIT	28  /* Burst Length Selection */

-#define LCD_CTRL_BST_MASK	(0x03 << LCD_CTRL_BST_BIT)

+#define LCD_CTRL_BST_MASK	(0x07 << LCD_CTRL_BST_BIT)

   #define LCD_CTRL_BST_4	(0 << LCD_CTRL_BST_BIT) /* 4-word */

   #define LCD_CTRL_BST_8	(1 << LCD_CTRL_BST_BIT) /* 8-word */

   #define LCD_CTRL_BST_16	(2 << LCD_CTRL_BST_BIT) /* 16-word */

   #define LCD_CTRL_BST_32	(3 << LCD_CTRL_BST_BIT) /* 32-word */

+#define LCD_CTRL_BST_16_CTN     (5 << LCD_CTRL_BST_BIT)

+#define LCD_CTRL_BST_64         (4 << LCD_CTRL_BST_BIT)

 #define LCD_CTRL_RGB565		(0 << 27) /* RGB565 mode(foreground 0 in OSD mode) */

 #define LCD_CTRL_RGB555		(1 << 27) /* RGB555 mode(foreground 0 in OSD mode) */

 #define LCD_CTRL_OFUP		(1 << 26) /* Output FIFO underrun protection enable */

@@ -260,8 +264,8 @@
   #define LCD_CTRL_FRC_2	(2 << LCD_CTRL_FRC_BIT) /* 2 grayscale */

 #define LCD_CTRL_PDD_BIT	16  /* Load Palette Delay Counter */

 #define LCD_CTRL_PDD_MASK	(0xff << LCD_CTRL_PDD_BIT)

-///#define LCD_CTRL_VGA		(1 << 15) /* VGA interface enable */

-//#define LCD_CTRL_DACTE		(1 << 14) /* DAC loop back test */

+//#define LCD_CTRL_VGA		(1 << 15) /* VGA interface enable *//*keep this bit to 0*/

+#define LCD_CTRL_DACTE		(1 << 14) /* DAC loop back test */

 #define LCD_CTRL_EOFM		(1 << 13) /* EOF interrupt mask */

 #define LCD_CTRL_SOFM		(1 << 12) /* SOF interrupt mask */

 #define LCD_CTRL_OFUM		(1 << 11) /* Output FIFO underrun interrupt mask */

@@ -300,6 +304,7 @@
 #define LCD_OSDC_EOFM0		(1 << 10) /* End of frame interrupt mask for foreground 0 */

 

 ////////////////////////////////////////////////////////////

+#if 0//These bits always read 0, and written are ignored.

 #define LCD_OSDC_ENDM		(1 << 9) /* End of frame interrupt mask for panel. */

 #define LCD_OSDC_F0DIVMD	(1 << 8) /* Divide Foreground 0 into 2 parts.

 					  * 0: Foreground 0 only has one part. */

@@ -309,6 +314,7 @@
 					  * 0: PART 1&2 have no same line */

 #define LCD_OSDC_F0P2EN		(1 << 5) /* 1: Foreground 0 PART2 is enabled.

 					  * 0: Foreground 0 PART2 is disabled.*/

+#endif

 ////////////////////////////////////////////////////////////

 

 #define LCD_OSDC_F1EN		(1 << 4) /* enable foreground 1 */

@@ -444,6 +450,8 @@
 #define LCD_CMD_EOFINT		(1 << 30)

 #define LCD_CMD_CMD		(1 << 29) /* indicate command in slcd mode */

 #define LCD_CMD_PAL		(1 << 28)

+#define LCD_CMD_UNCOMPRESS_EN   (1 << 27)

+#define LCD_CMD_UNCOMPRESS_WITHOUT_ALPHA      (1 << 26)

 #define LCD_CMD_LEN_BIT		0

 #define LCD_CMD_LEN_MASK	(0xffffff << LCD_CMD_LEN_BIT)

 

diff --git a/arch/mips/include/asm/mach-jz4810/jz4810mdma.h b/arch/mips/include/asm/mach-jz4810/jz4810mdma.h
index b61ffdb4d50..20084d19682 100644
--- a/arch/mips/include/asm/mach-jz4810/jz4810mdma.h
+++ b/arch/mips/include/asm/mach-jz4810/jz4810mdma.h
@@ -10,7 +10,7 @@
 #define __JZ4810MDMA_H__

 

 

-#define	MDMAC_BASE	0xB3030000 /* Memory Copy DMAC */

+#define	MDMAC_BASE	0xB3420000 //0xB3030000 /* Memory Copy DMAC */

 

 /*************************************************************************

  * MDMAC (MEM Copy DMA Controller)

diff --git a/arch/mips/include/asm/mach-jz4810/jz4810misc.h b/arch/mips/include/asm/mach-jz4810/jz4810misc.h
index e6176f01ff3..e744ea0fd7c 100644
--- a/arch/mips/include/asm/mach-jz4810/jz4810misc.h
+++ b/arch/mips/include/asm/mach-jz4810/jz4810misc.h
@@ -1,13 +1,13 @@
 /*

- * linux/include/asm-mips/mach-jz4810/jz4810misc.h

+ * linux/include/asm-mips/mach-jz4760/jz4760misc.h

  *

- * JZ4810 misc definition.

+ * JZ4760 misc definition.

  *

  * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

  */

 

-#ifndef __JZ4810MISC_H__

-#define __JZ4810MISC_H__

+#ifndef __JZ4760MISC_H__

+#define __JZ4760MISC_H__

 

 

 #if defined(__ASSEMBLY__) || defined(__LANGUAGE_ASSEMBLY)

@@ -21,8 +21,71 @@
         #define REG8(addr)	*((volatile unsigned char *)(addr))

         #define REG16(addr)	*((volatile unsigned short *)(addr))

         #define REG32(addr)	*((volatile unsigned int *)(addr))

+

+        #define INREG8(x)               ((unsigned char)(*(volatile unsigned char *)(x)))

+        #define OUTREG8(x, y)           *(volatile unsigned char *)(x) = (y)

+        #define SETREG8(x, y)           OUTREG8(x, INREG8(x)|(y))

+        #define CLRREG8(x, y)           OUTREG8(x, INREG8(x)&~(y))

+        #define CMSREG8(x, y, m)        OUTREG8(x, (INREG8(x)&~(m))|(y))

+

+        #define INREG16(x)              ((unsigned short)(*(volatile unsigned short *)(x)))

+        #define OUTREG16(x, y)          *(volatile unsigned short *)(x) = (y)

+        #define SETREG16(x, y)          OUTREG16(x, INREG16(x)|(y))

+        #define CLRREG16(x, y)          OUTREG16(x, INREG16(x)&~(y))

+        #define CMSREG16(x, y, m)       OUTREG16(x, (INREG16(x)&~(m))|(y))

+

+        #define INREG32(x)              ((unsigned int)(*(volatile unsigned int *)(x)))

+        #define OUTREG32(x, y)          *(volatile unsigned int *)(x) = (y)

+        #define SETREG32(x, y)          OUTREG32(x, INREG32(x)|(y))

+        #define CLRREG32(x, y)          OUTREG32(x, INREG32(x)&~(y))

+        #define CMSREG32(x, y, m)       OUTREG32(x, (INREG32(x)&~(m))|(y))

+

 #endif

 

 

-#endif /* __JZ4810MISC_H__ */

+/*

+ * Define the bit field macro to avoid the bit mistake

+ */

+#define BIT0            (1 << 0)

+#define BIT1            (1 << 1)

+#define BIT2            (1 << 2)

+#define BIT3            (1 << 3)

+#define BIT4            (1 << 4)

+#define BIT5            (1 << 5)

+#define BIT6            (1 << 6)

+#define BIT7            (1 << 7)

+#define BIT8            (1 << 8)

+#define BIT9            (1 << 9)

+#define BIT10           (1 << 10)

+#define BIT11           (1 << 11)

+#define BIT12 	        (1 << 12)

+#define BIT13 	        (1 << 13)

+#define BIT14 	        (1 << 14)

+#define BIT15 	        (1 << 15)

+#define BIT16 	        (1 << 16)

+#define BIT17 	        (1 << 17)

+#define BIT18 	        (1 << 18)

+#define BIT19 	        (1 << 19)

+#define BIT20 	        (1 << 20)

+#define BIT21 	        (1 << 21)

+#define BIT22 	        (1 << 22)

+#define BIT23 	        (1 << 23)

+#define BIT24 	        (1 << 24)

+#define BIT25 	        (1 << 25)

+#define BIT26 	        (1 << 26)

+#define BIT27 	        (1 << 27)

+#define BIT28 	        (1 << 28)

+#define BIT29 	        (1 << 29)

+#define BIT30 	        (1 << 30)

+#define BIT31 	        (1 << 31)

+

+

+/* Generate the bit field mask from msb to lsb */

+#define BITS_H2L(msb, lsb)  ((0xFFFFFFFF >> (32-((msb)-(lsb)+1))) << (lsb))

+

+

+/* Get the bit field value from the data which is read from the register */

+#define get_bf_value(data, lsb, mask)  (((data) & (mask)) >> (lsb))

+

 

+#endif /* __JZ4760MISC_H__ */

diff --git a/arch/mips/include/asm/mach-jz4810/jz4810nemc.h b/arch/mips/include/asm/mach-jz4810/jz4810nemc.h
index e33f8b989c7..58a1966d653 100644
--- a/arch/mips/include/asm/mach-jz4810/jz4810nemc.h
+++ b/arch/mips/include/asm/mach-jz4810/jz4810nemc.h
@@ -17,11 +17,39 @@
  *************************************************************************/

 

 #define NEMC_NFCSR	(NEMC_BASE + 0x050) /* NAND Flash Control/Status Register */

-#define NEMC_SMCR	(NEMC_BASE + 0x14)  /* Static Memory Control Register 1 */

-

+#define NEMC_SMCR1	(NEMC_BASE + 0x14)  /* Static Memory Control Register 1 */

+#define NEMC_SMCR2	(NEMC_BASE + 0x18)

+#define NEMC_SMCR3	(NEMC_BASE + 0x1c)

+#define NEMC_SMCR4	(NEMC_BASE + 0x20)

+#define NEMC_SMCR5	(NEMC_BASE + 0x24)

+#define NEMC_SMCR6	(NEMC_BASE + 0x28)

+#define NEMC_SACR1	(NEMC_BASE + 0x34)

+#define NEMC_SACR2	(NEMC_BASE + 0x38)

+#define NEMC_SACR3	(NEMC_BASE + 0x3c)

+#define NEMC_SACR4	(NEMC_BASE + 0x40)

+#define NEMC_SACR5	(NEMC_BASE + 0x44)

+#define NEMC_SACR6	(NEMC_BASE + 0x48)

 

 #define REG_NEMC_NFCSR	REG32(NEMC_NFCSR)

-#define REG_NEMC_SMCR1	REG32(NEMC_SMCR)

+#define REG_NEMC_SMCR1	REG32(NEMC_SMCR1)

+#define REG_NEMC_SMCR2	REG32(NEMC_SMCR2)

+#define REG_NEMC_SMCR3	REG32(NEMC_SMCR3)

+#define REG_NEMC_SMCR4	REG32(NEMC_SMCR4)

+#define REG_NEMC_SMCR5	REG32(NEMC_SMCR5)

+#define REG_NEMC_SMCR6	REG32(NEMC_SMCR6)

+#define REG_NEMC_SACR1	REG32(NEMC_SACR1)

+#define REG_NEMC_SACR2	REG32(NEMC_SACR2)

+#define REG_NEMC_SACR3	REG32(NEMC_SACR3)

+#define REG_NEMC_SACR4	REG32(NEMC_SACR4)

+#define REG_NEMC_SACR5	REG32(NEMC_SACR5)

+#define REG_NEMC_SACR6	REG32(NEMC_SACR6)

+

+#define NEMC_CS1	       0xBA000000	/* read-write area in static bank 1 */

+#define NEMC_CS2	       0xB8000000	/* read-write area in static bank 2 */

+#define NEMC_CS3	       0xB7000000	/* read-write area in static bank 3 */

+#define NEMC_CS4	       0xB6000000	/* read-write area in static bank 4 */

+#define NEMC_CS5	       0xB5000000	/* read-write area in static bank 5 */

+#define NEMC_CS6	       0xB4000000	/* read-write area in static bank 6 */

 

 // PN(bit 0):0-disable, 1-enable

 // PN(bit 1):0-no reset, 1-reset

@@ -37,7 +65,7 @@
 #define REG_NEMC_PNDR REG32(NEMC_PNDR)

 #define REG_NEMC_BITCNT REG32(NEMC_BITCNT)

 

-#define REG_NEMC_SMCR	REG32(NEMC_SMCR)

+//#define REG_NEMC_SMCR	REG32(NEMC_SMCR)

 

 /* NAND Flash Control/Status Register */

 #define NEMC_NFCSR_NFCE4	(1 << 7) /* NAND Flash Enable */

diff --git a/arch/mips/include/asm/mach-jz4810/jz4810ost.h b/arch/mips/include/asm/mach-jz4810/jz4810ost.h
new file mode 100644
index 00000000000..544d4f54760
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4810/jz4810ost.h
@@ -0,0 +1,73 @@
+/*

+ * jz4760ost.h

+ * JZ4760 OST register definition

+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.

+ *

+ * Author: whxu@ingenic.cn

+ */

+

+#ifndef __JZ4810OST_H__

+#define __JZ4810OST_H__

+

+//#define CONFIG_SOC_JZ4810 1

+/*

+ * Operating system timer module(OST) address definition

+ */

+

+/*

+ * OST registers offset address definition

+ */

+#define OST_OSTDR_OFFSET	(0xe0)  /* rw, 32, 0x???????? */

+#define OST_OSTCNTL_OFFSET	(0xe4)

+#define OST_OSTCNTH_OFFSET	(0xe8)

+#define OST_OSTCSR_OFFSET	(0xec)  /* rw, 16, 0x0000 */

+

+#define OST_OSTCNTH_BUF_OFFSET	(0xfc)

+

+

+/*

+ * OST registers address definition

+ */

+#define OST_OSTDR	(OST_BASE + OST_OSTDR_OFFSET)

+#define OST_OSTCNTL	(OST_BASE + OST_OSTCNTL_OFFSET)

+#define OST_OSTCNTH	(OST_BASE + OST_OSTCNTH_OFFSET)

+#define OST_OSTCSR	(OST_BASE + OST_OSTCSR_OFFSET)

+

+#define OST_OSTCNTH_BUF	(OST_BASE + OST_OSTCNTH_BUF_OFFSET)

+

+

+/*

+ * OST registers common define

+ */

+

+/* Operating system control register(OSTCSR) */

+#define OSTCSR_CNT_MD		BIT15

+#define OSTCSR_SD		BIT9

+#define OSTCSR_EXT_EN		BIT2

+#define OSTCSR_RTC_EN		BIT1

+#define OSTCSR_PCK_EN		BIT0

+

+#define OSTCSR_PRESCALE_LSB	3

+#define OSTCSR_PRESCALE_MASK	BITS_H2L(5, OSTCSR_PRESCALE_LSB)

+#define OSTCSR_PRESCALE1	(0x0 << OSTCSR_PRESCALE_LSB)

+#define OSTCSR_PRESCALE4	(0x1 << OSTCSR_PRESCALE_LSB)

+#define OSTCSR_PRESCALE16	(0x2 << OSTCSR_PRESCALE_LSB)

+#define OSTCSR_PRESCALE64	(0x3 << OSTCSR_PRESCALE_LSB)

+#define OSTCSR_PRESCALE256	(0x4 << OSTCSR_PRESCALE_LSB)

+#define OSTCSR_PRESCALE1024	(0x5 << OSTCSR_PRESCALE_LSB)

+

+

+#ifndef __MIPS_ASSEMBLER

+

+#define REG_OST_OSTDR		REG32(OST_OSTDR)

+

+#define REG_OST_OSTCNTL		REG32(OST_OSTCNTL)

+#define REG_OST_OSTCNTH		REG32(OST_OSTCNTH)

+

+#define REG_OST_OSTCSR		REG16(OST_OSTCSR)

+

+#define REG_OST_OSTCNTH_BUF	REG32(OST_OSTCNTH_BUF)

+

+#endif /* __MIPS_ASSEMBLER */

+

+#endif /* __JZ4810OST_H__ */

diff --git a/arch/mips/include/asm/mach-jz4810/jz4810tcu.h b/arch/mips/include/asm/mach-jz4810/jz4810tcu.h
index 92ca9eb1dcf..ca2bd10e386 100644
--- a/arch/mips/include/asm/mach-jz4810/jz4810tcu.h
+++ b/arch/mips/include/asm/mach-jz4810/jz4810tcu.h
@@ -99,7 +99,7 @@
 #define TCU_TCNT(n)	(TCU_BASE + (0x48 + (n)*0x10)) /* Timer Counter Reg */

 #define TCU_TCSR(n)	(TCU_BASE + (0x4C + (n)*0x10)) /* Timer Control Reg */

 #define TCU_OSTDR	(TCU_BASE + 0xe0) /* Operating System Timer Data Reg */

-#define TCU_OSTCNT	(TCU_BASE + 0xe8) /* Operating System Timer Counter Reg */

+#define TCU_OSTCNT	(TCU_BASE + 0xe4) /* Operating System Timer Counter Reg */

 #define TCU_OSTCSR	(TCU_BASE + 0xeC) /* Operating System Timer Control Reg */

 

 #define REG_TCU_TDFR(n)	REG16(TCU_TDFR((n)))

diff --git a/arch/mips/include/asm/mach-jz4810/jz4810tssi.h b/arch/mips/include/asm/mach-jz4810/jz4810tssi.h
index 997fcf923ce..f60c62c6b2b 100644
--- a/arch/mips/include/asm/mach-jz4810/jz4810tssi.h
+++ b/arch/mips/include/asm/mach-jz4810/jz4810tssi.h
@@ -10,7 +10,7 @@
 #define __JZ4810TSSI_H__

 

 

-#define	TSSI0_BASE	0xB0073000

+#define	TSSI0_BASE	0xB34E0000

 

 /*************************************************************************

  * TSSI MPEG 2-TS slave interface

@@ -21,6 +21,8 @@
 #define TSSI_STAT      ( TSSI0_BASE + 0x0c )   /* TSSI state register */

 #define TSSI_FIFO      ( TSSI0_BASE + 0x10 )   /* TSSI FIFO register */

 #define TSSI_PEN       ( TSSI0_BASE + 0x14 )   /* TSSI PID enable register */

+#define TSSI_NUM       ( TSSI0_BASE + 0x18 )

+#define TSSI_DTR       ( TSSI0_BASE + 0x1c )

 #define TSSI_PID(n)    ( TSSI0_BASE + 0x20 + 4*(n) )   /* TSSI PID filter register */

 #define TSSI_PID0      ( TSSI0_BASE + 0x20 )

 #define TSSI_PID1      ( TSSI0_BASE + 0x24 )

@@ -30,14 +32,31 @@
 #define TSSI_PID5      ( TSSI0_BASE + 0x34 )

 #define TSSI_PID6      ( TSSI0_BASE + 0x38 )

 #define TSSI_PID7      ( TSSI0_BASE + 0x3c )

-#define TSSI_PID_MAX   8	/* max PID: 7 */

+#define TSSI_PID8      ( TSSI0_BASE + 0x40 )

+#define TSSI_PID9      ( TSSI0_BASE + 0x44 )

+#define TSSI_PID10     ( TSSI0_BASE + 0x48 )

+#define TSSI_PID11     ( TSSI0_BASE + 0x4c )

+#define TSSI_PID12     ( TSSI0_BASE + 0x50 )

+#define TSSI_PID13     ( TSSI0_BASE + 0x54 )

+#define TSSI_PID14     ( TSSI0_BASE + 0x58 )

+#define TSSI_PID15     ( TSSI0_BASE + 0x5c )

+#define TSSI_PID_MAX   16	/* max PID: 15 */

+

+#define TSSI_DDA	( TSSI0_BASE + 0x60 )

+#define TSSI_DTA	( TSSI0_BASE + 0x64 )

+#define TSSI_DID	( TSSI0_BASE + 0x68 )

+#define TSSI_DCMD	( TSSI0_BASE + 0x6c )

+#define TSSI_DST	( TSSI0_BASE + 0x70 )

+#define TSSI_TC		( TSSI0_BASE + 0x74 )

  

 #define REG_TSSI_ENA       REG8( TSSI_ENA )

-#define REG_TSSI_CFG       REG16( TSSI_CFG )

+#define REG_TSSI_CFG       REG32( TSSI_CFG )

 #define REG_TSSI_CTRL      REG8( TSSI_CTRL )

 #define REG_TSSI_STAT      REG8( TSSI_STAT )

 #define REG_TSSI_FIFO      REG32( TSSI_FIFO )

 #define REG_TSSI_PEN       REG32( TSSI_PEN )

+#define REG_TSSI_NUM       REG32( TSSI_NUM )

+#define REG_TSSI_DTR       REG32( TSSI_DTR )

 #define REG_TSSI_PID(n)    REG32( TSSI_PID(n) )

 #define REG_TSSI_PID0      REG32( TSSI_PID0 )

 #define REG_TSSI_PID1      REG32( TSSI_PID1 )

@@ -47,25 +66,56 @@
 #define REG_TSSI_PID5      REG32( TSSI_PID5 )

 #define REG_TSSI_PID6      REG32( TSSI_PID6 )

 #define REG_TSSI_PID7      REG32( TSSI_PID7 )

+#define REG_TSSI_PID8      REG32( TSSI_PID8 )

+#define REG_TSSI_PID9      REG32( TSSI_PID9 )

+#define REG_TSSI_PID10     REG32( TSSI_PID10 )

+#define REG_TSSI_PID11     REG32( TSSI_PID11 )

+#define REG_TSSI_PID12     REG32( TSSI_PID12 )

+#define REG_TSSI_PID13     REG32( TSSI_PID13 )

+#define REG_TSSI_PID14     REG32( TSSI_PID14 )

+#define REG_TSSI_PID15     REG32( TSSI_PID15 )

+

+#define REG_TSSI_DDA	REG32( TSSI_DDA )

+#define REG_TSSI_DTA	REG32( TSSI_DTA )

+#define REG_TSSI_DID	REG32( TSSI_DID )

+#define REG_TSSI_DCMD	REG32( TSSI_DCMD )

+#define REG_TSSI_DST	REG32( TSSI_DST )

+#define REG_TSSI_TC	REG32( TSSI_TC )

 

 /* TSSI enable register */

 #define TSSI_ENA_SFT_RST 	( 1 << 7 )      /* soft reset bit */

 #define TSSI_ENA_PID_EN 	( 1 << 2 )      /* soft filtering function enable bit */

+#define TSSI_ENA_FAIL		( 1 << 4 )	/* fail signal bit */

+#define TSSI_ENA_PEN_0		( 1 << 3 )	/* PID filter enable bit for PID */

 #define TSSI_ENA_DMA_EN 	( 1 << 1 )      /* DMA enable bit */

 #define TSSI_ENA_ENA 		( 1 << 0 )      /* TSSI enable bit */

 

 /* TSSI configure register */

 #define TSSI_CFG_TRIG_BIT 	14 /* fifo trig number */

-#define TSSI_CFG_TRIG_MASK 	( 0x3 << TSSI_CFG_TRIG_BIT)

+#define TSSI_CFG_TRIG_MASK 	( 0x7 << TSSI_CFG_TRIG_BIT)

 #define TSSI_CFG_TRIG_4 	( 0 << TSSI_CFG_TRIG_BIT)

 #define TSSI_CFG_TRIG_8 	( 1 << TSSI_CFG_TRIG_BIT)

 #define TSSI_CFG_TRIG_16 	( 2 << TSSI_CFG_TRIG_BIT)

+#define TSSI_CFG_TRIG_32 	( 3 << TSSI_CFG_TRIG_BIT)

+#define TSSI_CFG_TRIG_48 	( 4 << TSSI_CFG_TRIG_BIT)

+#define TSSI_CFG_TRIG_64 	( 5 << TSSI_CFG_TRIG_BIT)

+#define TSSI_CFG_TRIG_80 	( 6 << TSSI_CFG_TRIG_BIT)

+#define TSSI_CFG_TRIG_96 	( 7 << TSSI_CFG_TRIG_BIT)

+

+/* mode of adding data 0 select bit */

+#define TSSI_CFG_TRANS_MD_BIT	10

+#define TSSI_CFG_TRANS_MD_MASK	( 0x7 << TSSI_CFG_TRANS_MD_BIT)	

+#define TSSI_CFG_TRANS_MD_0	(0 << TSSI_CFG_TRANS_MD_BIT)

+#define TSSI_CFG_TRANS_MD_1	(1 << TSSI_CFG_TRANS_MD_BIT)

+#define TSSI_CFG_TRANS_MD_2	(2 << TSSI_CFG_TRANS_MD_BIT)

+

 #define TSSI_CFG_END_WD 	( 1 << 9 )      /* order of data in word */

 #define TSSI_CFG_END_BT 	( 1 << 8 )      /* order of data in byte */

+

 #define TSSI_CFG_TSDI_H 	( 1 << 7 )      /* data pin polarity */

 #define TSSI_CFG_USE_0 		( 1 << 6 )      /* serial mode data pin select */

-#define TSSI_CFG_USE_TSDI0 	( 0 << 6 )      /* TSDI0 as serial mode data pin */

-#define TSSI_CFG_USE_TSDI7 	( 1 << 6 )      /* TSDI7 as serial mode data pin */

+#define TSSI_CFG_USE_TSDI0 	( 1 << 6 )      /* TSDI0 as serial mode data pin */

+#define TSSI_CFG_USE_TSDI7 	( 0 << 6 )      /* TSDI7 as serial mode data pin */

 #define TSSI_CFG_TSCLK_CH 	( 1 << 5 )      /* clk channel select */

 #define TSSI_CFG_PARAL 		( 1 << 4 )      /* mode select */

 #define TSSI_CFG_PARAL_MODE 	( 1 << 4 )      /* parallel select */

@@ -76,10 +126,12 @@
 #define TSSI_CFG_TSFAIL_H 	( 1 << 0 )      /* TSFAIL polarity select */

 

 /* TSSI control register */

+#define TSSI_CTRL_DTRM		( 1 << 2 ) 	/* FIFO data trigger interrupt mask bit */

 #define TSSI_CTRL_OVRNM 	( 1 << 1 )      /* FIFO overrun interrupt mask bit */

 #define TSSI_CTRL_TRIGM 	( 1 << 0 )      /* FIFO trigger interrupt mask bit */

 

 /* TSSI state register */

+#define TSSI_STAT_DTR		( 1 << 2 )	/* FIFO data trigger interrupt flag bit */

 #define TSSI_STAT_OVRN 		( 1 << 1 )      /* FIFO overrun interrupt flag bit */

 #define TSSI_STAT_TRIG 		( 1 << 0 )      /* FIFO trigger interrupt flag bit */

 

@@ -92,6 +144,14 @@
 #define TSSI_PEN_EN50 	( 1 << 5 )      

 #define TSSI_PEN_EN60 	( 1 << 6 )      

 #define TSSI_PEN_EN70 	( 1 << 7 )      

+#define TSSI_PEN_EN80 	( 1 << 8 )      

+#define TSSI_PEN_EN90 	( 1 << 9 )      

+#define TSSI_PEN_EN100 	( 1 << 10 )      

+#define TSSI_PEN_EN110 	( 1 << 11 )      

+#define TSSI_PEN_EN120 	( 1 << 12 )      

+#define TSSI_PEN_EN130 	( 1 << 13 )      

+#define TSSI_PEN_EN140 	( 1 << 14 )      

+#define TSSI_PEN_EN150 	( 1 << 15 )      

 #define TSSI_PEN_EN01 	( 1 << 16 )      

 #define TSSI_PEN_EN11 	( 1 << 17 )      

 #define TSSI_PEN_EN21 	( 1 << 18 )     

@@ -100,15 +160,60 @@
 #define TSSI_PEN_EN51 	( 1 << 21 )      

 #define TSSI_PEN_EN61 	( 1 << 22 )     

 #define TSSI_PEN_EN71 	( 1 << 23 )      

-#define TSSI_PEN_PID0 	( 1 << 31 ) /* PID filter enable PID0 */

+#define TSSI_PEN_EN81 	( 1 << 24 )      

+#define TSSI_PEN_EN91 	( 1 << 25 )      

+#define TSSI_PEN_EN101 	( 1 << 26 )      

+#define TSSI_PEN_EN111 	( 1 << 27 )      

+#define TSSI_PEN_EN121 	( 1 << 28 )      

+#define TSSI_PEN_EN131 	( 1 << 29 )      

+#define TSSI_PEN_EN141 	( 1 << 30 )      

+#define TSSI_PEN_EN151 	( 1 << 31 )      

+//#define TSSI_PEN_PID0 	( 1 << 31 ) /* PID filter enable PID0 */

+

+/* TSSI Data Number Registers */

+#define TSSI_DNUM_BIT	0

+#define TSSI_DNUM_MASK	(0x7f << TSSI_DNUM_BIT)

+

+/* TSSI Data Trigger Register */

+#define TSSI_DTRG_BIT 	0

+#define TSSI_DTRG_MASK	(0x7f << TSSI_DTRG_BIT)

+

 

 /* TSSI PID Filter Registers */

 #define TSSI_PID_PID1_BIT 	16

-#define TSSI_PID_PID1_MASK 	(0x1FFF<<TSSI_PID_PID1_BIT)

+#define TSSI_PID_PID1_MASK 	(0x1fff<<TSSI_PID_PID1_BIT)

 #define TSSI_PID_PID0_BIT 	0

-#define TSSI_PID_PID0_MASK 	(0x1FFF<<TSSI_PID_PID0_BIT)

-

-

+#define TSSI_PID_PID0_MASK 	(0x1fff<<TSSI_PID_PID0_BIT)

+

+/* TSSI DMA Identifier Registers */

+#define TSSI_DMA_ID_BIT		0

+#define TSSI_DMA_ID_MASK	(0xffff << TSSI_DMA_ID_BIT)

+

+/* TSSI DMA Command Registers */

+#define TSSI_DCMD_TLEN_BIT	8

+#define TSSI_DCMD_TLEN_MASK	(0xff << TSSI_DCMD_TLEN_BIT)

+#define TSSI_DCMD_TEFE		(1 << 4)

+#define TSSI_DCMD_TSZ_BIT	2

+#define TSSI_DCMD_TSZ_MASK	(0x3 << TSSI_DCMD_TSZ_BIT)

+#define TSSI_DCMD_TSZ_4		(0 << TSSI_DCMD_TSZ_BIT)

+#define TSSI_DCMD_TSZ_8		(1 << TSSI_DCMD_TSZ_BIT)

+#define TSSI_DCMD_TSZ_16	(2 << TSSI_DCMD_TSZ_BIT)

+#define TSSI_DCMD_TSZ_32	(3 << TSSI_DCMD_TSZ_BIT)

+#define TSSI_DCMD_TEIE		(1 << 1)

+#define TSSI_DCMD_LINK		(1 << 0)

+

+/* TSSI DMA Status Registers */

+#define TSSI_DST_DID_BIT	16

+#define TSSI_DST_DID_MASK	(0xffff << TSSI_DST_DID_BIT)

+#define TSSI_DST_TEND		(1 << 0)

+

+/* TSSI Transfer Control Registers */

+#define TSSI_TC_OP_BIT		4

+#define TSSI_TC_OP_MASK		(0x3 << TSSI_TC_OP_BIT)

+//////////////////#define TSSI_TC_OP_0		( 

+#define TSSI_TC_OPE		(1 << 2)

+#define TSSI_TC_EME		(1 << 1)

+#define TSSI_TC_APM		(1 << 0)

 #ifndef __MIPS_ASSEMBLER

 

 /*************************************************************************

@@ -117,6 +222,8 @@
 #define __tssi_enable()                       ( REG_TSSI_ENA |= TSSI_ENA_ENA )

 #define __tssi_disable()                      ( REG_TSSI_ENA &= ~TSSI_ENA_ENA )

 #define __tssi_soft_reset()                   ( REG_TSSI_ENA |= TSSI_ENA_SFT_RST )

+#define __tssi_filter_enable_pid0()	      ( REG_TSSI_ENA |= TSSI_ENA_PEN_0 )

+#define __tssi_filter_disable_pid0()	      ( REG_TSSI_ENA &= ~TSSI_ENA_PEN_0 )

 #define __tssi_dma_enable()                   ( REG_TSSI_ENA |= TSSI_ENA_DMA_EN )

 #define __tssi_dma_disable()                  ( REG_TSSI_ENA &= ~TSSI_ENA_DMA_EN )

 #define __tssi_filter_enable()                ( REG_TSSI_ENA |= TSSI_ENA_PID_EN )

@@ -159,47 +266,57 @@
 #define __tssi_select_fail_act_high()         ( REG_TSSI_CFG |= TSSI_CFG_TSFAIL_H )

 #define __tssi_select_fail_act_low()          ( REG_TSSI_CFG &= ~TSSI_CFG_TSFAIL_H )

 

+#define __tssi_enable_data_trigger_irq()      (REG_TSSI_CTRL &= ~TSSI_CTRL_DTRM)

+#define __tssi_disable_data_trigger_irq()     (REG_TSSI_CTRL |= TSSI_CTRL_DTRM)

+

 #define __tssi_enable_ovrn_irq()              ( REG_TSSI_CTRL &= ~TSSI_CTRL_OVRNM )

 #define __tssi_disable_ovrn_irq()             ( REG_TSSI_CTRL |= TSSI_CTRL_OVRNM )

 

 #define __tssi_enable_trig_irq()              ( REG_TSSI_CTRL &= ~TSSI_CTRL_TRIGM )

 #define __tssi_disable_trig_irq()             ( REG_TSSI_CTRL |= TSSI_CTRL_TRIGM ) 

 

+#define __tssi_enable_ctrl_irq()	      ( REG_TSSI_CTRL = 0)

+#define __tssi_disable_ctrl_irq()	      ( REG_TSSI_CTRL = 7)

+

+#define __tssi_state_is_dtr()		      ( REG_TSSI_STAT & TSSI_STAT_DTR )

 #define __tssi_state_is_overrun()             ( REG_TSSI_STAT & TSSI_STAT_OVRN )

 #define __tssi_state_trigger_meet()           ( REG_TSSI_STAT & TSSI_STAT_TRIG )

 #define __tssi_clear_state()                  ( REG_TSSI_STAT = 0 ) /* write 0??? */

-#define __tssi_state_clear_overrun()          ( REG_TSSI_STAT = TSSI_STAT_OVRN )

+#define __tssi_state_clear_overrun()          ( REG_TSSI_STAT = TSSI_STAT_OVRN )   //??????? xyma

+

+#define __tssi_clear_desc_end_flag()	      ( REG_TSSI_DST &= ~TSSI_DST_TEND )

+

 

-#define __tssi_enable_filte_pid0()            ( REG_TSSI_PEN |= TSSI_PEN_PID0 )

-#define __tssi_disable_filte_pid0()           ( REG_TSSI_PEN &= ~TSSI_PEN_PID0 )

+//#define __tssi_enable_filte_pid0()            ( REG_TSSI_PEN |= TSSI_PEN_PID0 )

+//#define __tssi_disable_filte_pid0()           ( REG_TSSI_PEN &= ~TSSI_PEN_PID0 )

+

+/* m = 0, ..., 31 */

+////////////////???????????????????????????????????????????????????????????

 

-/* m = 0, ..., 15 */

 #define __tssi_enable_pid_filter(m)				\

 	do {							\

 		int n = (m);					\

 		if ( n>=0 && n <(TSSI_PID_MAX*2) ) {		\

-			if ( n >= TSSI_PID_MAX ) n += 8;	\

 			REG_TSSI_PEN |= ( 1 << n );		\

 		}						\

 	} while (0)

 

-/* m = 0, ..., 15 */

+/* m = 0, ..., 31 */

 #define __tssi_disable_pid_filter(m)				       \

 	do {							       \

 		int n = (m);					       \

 		if ( n>=0 && n <(TSSI_PID_MAX*2) ) {		       \

-			if ( n >= TSSI_PID_MAX ) n += 8;	       \

 			REG_TSSI_PEN &= ~( 1 << n );		       \

 		}						       \

 	} while (0)

 

-/* n = 0, ..., 7 */

+/* n = 0, ..., 15 */

 #define __tssi_set_pid0(n, pid0)					\

 	do {								\

 		REG_TSSI_PID(n) &= ~TSSI_PID_PID0_MASK;			\

 		REG_TSSI_PID(n) |= ((pid0)<<TSSI_PID_PID0_BIT)&TSSI_PID_PID0_MASK; \

 	}while (0)

-/* n = 0, ..., 7 */

+/* n = 0, ..., 15 */

 #define __tssi_set_pid1(n, pid1)					\

 	do {								\

 		REG_TSSI_PID(n) &= ~TSSI_PID_PID1_MASK;			\

diff --git a/arch/mips/include/asm/sstep.h b/arch/mips/include/asm/sstep.h
new file mode 100644
index 00000000000..f344e5da07a
--- /dev/null
+++ b/arch/mips/include/asm/sstep.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2010 zhiping zhong <zpzhong@ingenic.cn>, JZ
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#ifndef SSTEP_H
+#define SSTEP_H
+struct pt_regs;
+
+/*
+ * Only "eret" cann't single be execute?
+ */
+#define IS_SYNC(instr)  	(((instr) & 0xfc00003f) == 0x0f)
+#define IS_ERET(instr)  	( (instr) == 0x42000018)
+
+/* Emulate instructions that cause a transfer of control. */
+extern int emulate_step(struct pt_regs *regs, unsigned int instr);
+extern int test_step(unsigned int instr);
+extern int insn_is_jmpbra(unsigned int instr);
+
+
+#define __TEST_EMULATE_STEP
+
+#ifdef __TEST_EMULATE_STEP
+extern int test_emulate_step(void);
+#else
+static inline int test_emulate_step(void) {
+	return 0;
+}
+#endif
+
+#endif
diff --git a/arch/mips/jz4750/board-apus.c b/arch/mips/jz4750/board-apus.c
index 884c8152102..08561b80c6b 100644
--- a/arch/mips/jz4750/board-apus.c
+++ b/arch/mips/jz4750/board-apus.c
@@ -17,6 +17,7 @@
 #include <linux/mm.h>
 #include <linux/console.h>
 #include <linux/delay.h>
+#include <linux/mmc/host.h>
 
 #include <asm/cpu.h>
 #include <asm/bootinfo.h>
@@ -25,7 +26,7 @@
 
 #include <asm/jzsoc.h>
 #include <linux/i2c.h>
-#include <asm/jzmmc/jz_mmc_platform_data.h>
+#include <linux/spi/spi.h>
 
 void __init board_msc_init(void);
 
@@ -71,6 +72,9 @@ static void apus_sd_cpm_start(struct device *dev)
 
 static unsigned int apus_sd_status(struct device *dev)
 {
+#if defined(CONFIG_JZ_SYSTEM_AT_CARD)
+	return 1;
+#endif
 	unsigned int status;
 
 	status = (unsigned int) __gpio_get_pin(GPIO_SD0_CD_N);
@@ -97,6 +101,10 @@ static void apus_sd_plug_change(int state)
 
 static unsigned int apus_sd_get_wp(struct device *dev)
 {
+#if defined(CONFIG_JZ_SYSTEM_AT_CARD)
+	return 0;
+#endif
+
 	unsigned int status;
 
 	status = (unsigned int) __gpio_get_pin(GPIO_SD0_WP);
@@ -110,8 +118,13 @@ struct jz_mmc_platform_data apus_sd_data = {
 	.support_sdio   = 1,
 #endif
 	.ocr_mask	= MMC_VDD_32_33 | MMC_VDD_33_34,
+#if defined(CONFIG_SYSTEM_AT_CARD)
+	.status_irq	= 0,
+	.detect_pin     = 0,
+#else
 	.status_irq	= MSC0_HOTPLUG_IRQ,
 	.detect_pin     = GPIO_SD0_CD_N,
+#endif
 	.init           = apus_sd_gpio_init,
 	.power_on       = apus_sd_power_on,
 	.power_off      = apus_sd_power_off,
@@ -119,7 +132,14 @@ struct jz_mmc_platform_data apus_sd_data = {
 	.status		= apus_sd_status,
 	.plug_change	= apus_sd_plug_change,
 	.write_protect  = apus_sd_get_wp,
-	.max_bus_width  = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | MMC_CAP_4_BIT_DATA,
+	.max_bus_width  = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED
+#ifdef CONFIG_JZ_MSC0_BUS_4
+	| MMC_CAP_4_BIT_DATA
+#endif
+#ifdef CONFIG_JZ_MSC0_BUS_8
+	| MMC_CAP_8_BIT_DATA
+#endif
+	,
 #ifdef CONFIG_JZ_MSC0_BUS_1
 	.bus_width      = 1,
 #elif defined  CONFIG_JZ_MSC0_BUS_4
@@ -192,7 +212,11 @@ struct jz_mmc_platform_data apus_tf_data = {
 	.cpm_start	= apus_tf_cpm_start,
 	.status		= apus_tf_status,
 	.plug_change	= apus_tf_plug_change,
-	.max_bus_width  = MMC_CAP_SD_HIGHSPEED | MMC_CAP_4_BIT_DATA,
+	.max_bus_width  = MMC_CAP_SD_HIGHSPEED
+#ifdef CONFIG_JZ_MSC1_BUS_4
+	| MMC_CAP_4_BIT_DATA
+#endif
+	,
 #ifdef CONFIG_JZ_MSC1_BUS_1
 	.bus_width      = 1,
 #else
@@ -218,6 +242,33 @@ void __init board_i2c_init(void) {
 	i2c_register_board_info(0, lepus_i2c0_devs, ARRAY_SIZE(lepus_i2c0_devs));
 }
 
+/* SPI devices */
+struct spi_board_info jz4750_spi0_board_info[]  = {
+	[0] = {
+		.modalias       = "spidev0",
+		.bus_num        = 0,
+		.chip_select    = 0,
+		.max_speed_hz   = 120000,
+	},
+	[1] = {
+		.modalias       = "spitest",
+		.bus_num        = 0,
+		.chip_select    = 1,
+		.max_speed_hz   = 2500000,
+	},
+};
+struct spi_board_info jz4750_spi1_board_info[]  = {
+	[0] = {
+		.modalias       = "spidev1",
+		.bus_num        = 1,
+		.chip_select    = 0,
+		.max_speed_hz   = 12000000,
+	},
+};
+void __init board_spi_init(void){
+	spi_register_board_info(jz4750_spi0_board_info,ARRAY_SIZE(jz4750_spi0_board_info));
+	spi_register_board_info(jz4750_spi1_board_info,ARRAY_SIZE(jz4750_spi1_board_info));
+}
 static void __init board_cpm_setup(void)
 {
 	/* Stop unused module clocks here.
diff --git a/arch/mips/jz4750/dma.c b/arch/mips/jz4750/dma.c
index 2508111b44e..70acdefe44c 100644
--- a/arch/mips/jz4750/dma.c
+++ b/arch/mips/jz4750/dma.c
@@ -95,6 +95,8 @@ static const struct {
 	{CPHYSADDR(SSI_DR(1)), DMA_32BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_SSI1IN},
 	{CPHYSADDR(PCM_DP), DMA_16BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_PMOUT},
 	{CPHYSADDR(PCM_DP), DMA_16BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_PMIN},
+	[DMA_ID_AX88796C_TX] = {0, 0, 0},
+	[DMA_ID_AX88796C_RX] = {0, 0, 0},
 	{},
 };
 
diff --git a/arch/mips/jz4750/platform.c b/arch/mips/jz4750/platform.c
index acf09c8406f..a9849cc670b 100644
--- a/arch/mips/jz4750/platform.c
+++ b/arch/mips/jz4750/platform.c
@@ -16,8 +16,7 @@
 
 #include <asm/jzsoc.h>
 #include <../sound/oss/jz_audio.h>
-
-#include <asm/jzmmc/jz_mmc_platform_data.h>
+#include <linux/spi/spi.h>
 
 extern void __init board_msc_init(void);
 
@@ -123,7 +122,7 @@ static struct resource jz_mmc_resources[] = {
 static u64 jz_mmc_dmamask =  ~(u32)0;
 
 static struct platform_device jz_mmc_device = {
-	.name = "jz-mmc",
+	.name = "jz-msc",
 	.id = 0,
 	.dev = {
 		.dma_mask               = &jz_mmc_dmamask,
@@ -155,7 +154,7 @@ static struct resource jz_msc0_resources[] = {
 static u64 jz_msc0_dmamask =  ~(u32)0;
 
 static struct platform_device jz_msc0_device = {
-	.name = "jz-msc0",
+	.name = "jz-msc",
 	.id = 0,
 	.dev = {
 		.dma_mask               = &jz_msc0_dmamask,
@@ -188,7 +187,7 @@ static struct resource jz_msc1_resources[] = {
 static u64 jz_msc1_dmamask =  ~(u32)0;
 
 static struct platform_device jz_msc1_device = {
-	.name = "jz-msc1",
+	.name = "jz-msc",
 	.id = 1,
 	.dev = {
 		.dma_mask               = &jz_msc1_dmamask,
@@ -247,29 +246,153 @@ static struct platform_device jz_i2c_device = {
 	.resource       = jz_i2c_resources,
 };
 
+
+/** AX88796C controller **/
+static struct resource ax88796c_resources[] = {
+	[0] = {
+		.start          = CPHYSADDR(0xac000000),
+		.end            = CPHYSADDR(0xac000000) + 0x6800 - 1,
+		.flags          = IORESOURCE_MEM,
+	},
+	[1] = {
+		.start          = 118,
+		.end            = 118,
+		.flags          = IORESOURCE_IRQ,
+	}
+};
+
+static u64 ax88796c_dmamask =  ~(u32)0;
+
+static struct platform_device ax88796c_dev = {
+	.name = "ax88796c",
+	.id = 0,
+	.dev = {
+		.dma_mask               = &ax88796c_dmamask,
+		.coherent_dma_mask      = 0xffffffff,
+	},
+	.num_resources  = ARRAY_SIZE(ax88796c_resources),
+	.resource       = ax88796c_resources,
+};
+
 //////////////////////////////////////////////////////////
-#define SND(num, desc) { .name = desc, .id = num } 
-static struct snd_endpoint snd_endpoints_list[] = { 
- SND(0, "HANDSET"), 
- SND(1, "SPEAKER"), 
- SND(2, "HEADSET"), 
- 
-}; 
-#undef SND 
-   
-static struct jz_snd_endpoints vogue_snd_endpoints = { 
-      .endpoints = snd_endpoints_list, 
-      .num = ARRAY_SIZE(snd_endpoints_list), 
-}; 
-
-static struct platform_device vogue_snd_device = { 
-    .name = "mixer", 
-    .id = -1, 
-    .dev = { 
-      .platform_data = &vogue_snd_endpoints, 
-    }, 
-}; 
+#define SND(num, desc) { .name = desc, .id = num }
+static struct snd_endpoint snd_endpoints_list[] = {
+ SND(0, "HANDSET"),
+ SND(1, "SPEAKER"),
+ SND(2, "HEADSET"),
+
+};
+#undef SND
+
+static struct jz_snd_endpoints vogue_snd_endpoints = {
+      .endpoints = snd_endpoints_list,
+      .num = ARRAY_SIZE(snd_endpoints_list),
+};
+
+static struct platform_device vogue_snd_device = {
+    .name = "mixer",
+    .id = -1,
+    .dev = {
+      .platform_data = &vogue_snd_endpoints,
+    },
+};
 ///////////////////////////////////////////////////////////
+/* SSI controller --- SPI (0) */
+#ifndef CONFIG_JZ_SPI_BOARD_INFO_REGISTER
+#define __jz_spi0_board_info 	NULL
+#define __jz_spi1_board_info 	NULL
+#else
+extern struct spi_board_info jz4750_spi0_board_info[];
+extern struct spi_board_info jz4750_spi1_board_info[];
+#define __jz_spi0_board_info 	&jz4750_spi0_board_info[0]
+#define __jz_spi1_board_info 	&jz4750_spi1_board_info[0]
+#endif
+
+struct jz47xx_spi_info spi0_info_cfg = {
+	.chnl = 0,
+	.bus_num = 0,
+	.board_size = 2,				/* spiÉ豸ÊýÄ¿*/
+#ifdef CONFIG_JZ_SPI_BOARD_INFO_REGISTER
+	.board_info = __jz_spi0_board_info,
+#else
+	.board_info = NULL,
+#endif
+//	.set_cs = spi_gpio_cs,
+	.set_cs = NULL,
+	.pin_cs ={
+		PIN_SSI_CE0,
+		32*2+31,				/*apus: GPC31 --- SW6 --- BOOT_SEL1 (dummy, example) */
+//		32*4+16,				/*lepus: TP56 */
+	},
+};
+static struct resource jz_spi0_resource[] = {
+	[0] = {
+		.start          = CPHYSADDR(SSI_BASE),
+		.end            = CPHYSADDR(SSI_BASE) + 0x2000 - 1,
+		.flags 			= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start = IRQ_SSI0,
+		.end   = IRQ_SSI0,
+		.flags = IORESOURCE_IRQ,
+	}
+};
+static u64 jz_spi0_dmamask =  ~(u32)0;
+
+struct platform_device jz_spi0_device = {
+	.name		  = "jz47xx-spi0",
+	.id		  = 0,
+	.num_resources	  = ARRAY_SIZE(jz_spi0_resource),
+	.resource	  = jz_spi0_resource,
+        .dev              = {
+                .dma_mask = &jz_spi0_dmamask,
+                .coherent_dma_mask = 0xffffffffUL,
+                .platform_data = & spi0_info_cfg,
+        }
+};
+
+/* SSI controller --- SPI (1) */
+struct jz47xx_spi_info spi1_info_cfg = {
+	.chnl = 1,
+	.bus_num = 1,
+	.board_size = 1,
+#ifdef CONFIG_JZ_SPI_BOARD_INFO_REGISTER
+	.board_info = __jz_spi1_board_info,
+#else
+	.board_info = NULL,
+#endif
+//	.set_cs = spi_gpio_cs,
+	.set_cs = NULL,
+	.pins_config = NULL,
+	.pin_cs ={
+		PIN_SSI_CE0,
+	},
+};
+static struct resource jz_spi1_resource[] = {
+	[0] = {
+		.start          = CPHYSADDR(SSI_BASE) + 0x2000,
+		.end            = CPHYSADDR(SSI_BASE) + 0x4000 - 1,
+		.flags 			= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start = IRQ_SSI1,
+		.end   = IRQ_SSI1,
+		.flags = IORESOURCE_IRQ,
+	}
+};
+static u64 jz_spi1_dmamask =  ~(u32)0;
+
+struct platform_device jz_spi1_device = {
+	.name		  = "jz47xx-spi1",
+	.id		  = 1,
+	.num_resources	  = ARRAY_SIZE(jz_spi1_resource),
+	.resource	  = jz_spi1_resource,
+        .dev              = {
+                .dma_mask = &jz_spi1_dmamask,
+                .coherent_dma_mask = 0xffffffffUL,
+                .platform_data = & spi1_info_cfg,
+        }
+};
 
 /* All */
 static struct platform_device *jz_platform_devices[] __initdata = {
@@ -279,13 +402,21 @@ static struct platform_device *jz_platform_devices[] __initdata = {
 	//	&jz_mmc_device,
 	&jz_i2c_device,
 	&vogue_snd_device,
+	&ax88796c_dev,
+	&jz_spi0_device,
+	&jz_spi1_device,
 };
 
 extern void __init board_i2c_init(void);
+extern void __init board_spi_init(void);
 static int __init jz_platform_init(void)
 {
 	board_i2c_init();
 	board_msc_init();
+#ifndef CONFIG_JZ_SPI_BOARD_INFO_REGISTER
+	board_spi_init();
+#endif
+
 	return platform_add_devices(jz_platform_devices, ARRAY_SIZE(jz_platform_devices));
 }
 
diff --git a/arch/mips/jz4750/prom.c b/arch/mips/jz4750/prom.c
index d04bb3e52a3..ade199d93c3 100644
--- a/arch/mips/jz4750/prom.c
+++ b/arch/mips/jz4750/prom.c
@@ -179,8 +179,11 @@ void __init prom_init(void)
 /* used by early printk */
 void prom_putchar(char c)
 {
-	volatile u8 *uart_lsr = (volatile u8 *)(UART0_BASE + OFF_LSR);
-	volatile u8 *uart_tdr = (volatile u8 *)(UART0_BASE + OFF_TDR);
+#ifndef JZ_EARLY_UART_BASE
+#error "please define JZ_EARLY_UART_BASE for your board!"
+#endif
+	volatile u8 *uart_lsr = (volatile u8 *)(JZ_EARLY_UART_BASE + OFF_LSR);
+	volatile u8 *uart_tdr = (volatile u8 *)(JZ_EARLY_UART_BASE + OFF_TDR);
 
 	/* Wait for fifo to shift out some bytes */
 	while ( !((*uart_lsr & (UARTLSR_TDRQ | UARTLSR_TEMT)) == 0x60) );
diff --git a/arch/mips/jz4750d/board-cetus.c b/arch/mips/jz4750d/board-cetus.c
index d154cc61fb1..afbc5f465a6 100644
--- a/arch/mips/jz4750d/board-cetus.c
+++ b/arch/mips/jz4750d/board-cetus.c
@@ -17,6 +17,7 @@
 #include <linux/mm.h>
 #include <linux/console.h>
 #include <linux/delay.h>
+#include <linux/mmc/host.h>
 
 #include <asm/cpu.h>
 #include <asm/bootinfo.h>
@@ -24,7 +25,6 @@
 #include <asm/reboot.h>
 
 #include <asm/jzsoc.h>
-#include <asm/jzmmc/jz_mmc_platform_data.h>
 
 void __init board_msc_init(void);
 
@@ -76,6 +76,9 @@ static void cetus_sd_cpm_start(struct device *dev)
 
 static unsigned int cetus_sd_status(struct device *dev)
 {
+#if defined(CONFIG_JZ_SYSTEM_AT_CARD)
+	return 1;
+#endif
 	unsigned int status;
 
 	status = (unsigned int) __gpio_get_pin(GPIO_SD0_CD_N);
@@ -102,6 +105,9 @@ static void cetus_sd_plug_change(int state)
 
 static unsigned int cetus_sd_get_wp(struct device *dev)
 {
+#if defined(CONFIG_JZ_SYSTEM_AT_CARD)
+	return 0;
+#endif
 	unsigned int status;
 
 	status = (unsigned int) __gpio_get_pin(GPIO_SD0_WP);
@@ -115,8 +121,13 @@ struct jz_mmc_platform_data cetus_sd_data = {
 	.support_sdio   = 1,
 #endif
 	.ocr_mask	= MMC_VDD_32_33 | MMC_VDD_33_34,
+#if defined(CONFIG_SYSTEM_AT_CARD)
+	.status_irq	= 0,
+	.detect_pin     = 0,
+#else
 	.status_irq	= MSC0_HOTPLUG_IRQ,
 	.detect_pin     = GPIO_SD0_CD_N,
+#endif
 	.init           = cetus_sd_gpio_init,
 	.power_on       = cetus_sd_power_on,
 	.power_off      = cetus_sd_power_off,
diff --git a/arch/mips/jz4750d/platform.c b/arch/mips/jz4750d/platform.c
index cf119330c0d..716fc34a16f 100644
--- a/arch/mips/jz4750d/platform.c
+++ b/arch/mips/jz4750d/platform.c
@@ -17,8 +17,6 @@
 #include <asm/jzsoc.h>
 #include <../sound/oss/jz_audio.h>
 
-#include <asm/jzmmc/jz_mmc_platform_data.h>
-
 extern void __init board_msc_init(void);
 
 int __init jz_add_msc_devices(unsigned int controller, struct jz_mmc_platform_data *plat);
@@ -158,7 +156,7 @@ static struct resource jz_msc0_resources[] = {
 static u64 jz_msc0_dmamask =  ~(u32)0;
 
 static struct platform_device jz_msc0_device = {
-	.name = "jz-msc0",
+	.name = "jz-msc",
 	.id = 0,
 	.dev = {
 		.dma_mask               = &jz_msc0_dmamask,
@@ -191,7 +189,7 @@ static struct resource jz_msc1_resources[] = {
 static u64 jz_msc1_dmamask =  ~(u32)0;
 
 static struct platform_device jz_msc1_device = {
-	.name = "jz-msc1",
+	.name = "jz-msc",
 	.id = 1,
 	.dev = {
 		.dma_mask               = &jz_msc1_dmamask,
@@ -250,27 +248,27 @@ static struct platform_device jz_i2c_device = {
 };
 
 //////////////////////////////////////////////////////////
-#define SND(num, desc) { .name = desc, .id = num } 
-static struct snd_endpoint snd_endpoints_list[] = { 
- SND(0, "HANDSET"), 
- SND(1, "SPEAKER"), 
- SND(2, "HEADSET"), 
- 
-}; 
-#undef SND 
-   
-static struct jz_snd_endpoints vogue_snd_endpoints = { 
-      .endpoints = snd_endpoints_list, 
-      .num = ARRAY_SIZE(snd_endpoints_list), 
-}; 
-
-static struct platform_device vogue_snd_device = { 
-    .name = "mixer", 
-    .id = -1, 
-    .dev = { 
-      .platform_data = &vogue_snd_endpoints, 
-    }, 
-}; 
+#define SND(num, desc) { .name = desc, .id = num }
+static struct snd_endpoint snd_endpoints_list[] = {
+ SND(0, "HANDSET"),
+ SND(1, "SPEAKER"),
+ SND(2, "HEADSET"),
+
+};
+#undef SND
+
+static struct jz_snd_endpoints vogue_snd_endpoints = {
+      .endpoints = snd_endpoints_list,
+      .num = ARRAY_SIZE(snd_endpoints_list),
+};
+
+static struct platform_device vogue_snd_device = {
+    .name = "mixer",
+    .id = -1,
+    .dev = {
+      .platform_data = &vogue_snd_endpoints,
+    },
+};
 ///////////////////////////////////////////////////////////
 
 /* All */
diff --git a/arch/mips/jz4760/Makefile b/arch/mips/jz4760/Makefile
index a03e184c0dd..d369d31b67d 100644
--- a/arch/mips/jz4760/Makefile
+++ b/arch/mips/jz4760/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_PROC_FS)		+= proc.o
 obj-$(CONFIG_JZ4760_ALTAIR)	+= board-altair.o
 obj-$(CONFIG_JZ4760_CYGNUS)	+= board-cygnus.o
 obj-$(CONFIG_JZ4760_LEPUS)	+= board-lepus.o
+obj-$(CONFIG_JZ4760_HTB80)	+= board-htb80.o
 
 obj-$(CONFIG_JZ4760_F4760)	+= board-f4760.o
 obj-$(CONFIG_SOC_JZ4760)        += fpu.o
diff --git a/arch/mips/jz4760/board-cygnus.c b/arch/mips/jz4760/board-cygnus.c
index 9624b211c25..fe8728f6125 100644
--- a/arch/mips/jz4760/board-cygnus.c
+++ b/arch/mips/jz4760/board-cygnus.c
@@ -14,9 +14,12 @@
 #include <linux/init.h>
 #include <linux/sched.h>
 #include <linux/ioport.h>
-//#include <linux/mm.h>
+#include <linux/mmc/host.h>
 #include <linux/console.h>
 #include <linux/delay.h>
+#include <linux/i2c.h>
+#include <linux/i2c-gpio.h>
+#include <linux/platform_device.h>
 
 #include <asm/cpu.h>
 #include <asm/bootinfo.h>
@@ -26,7 +29,7 @@
 #include <asm/jzsoc.h>
 
 extern void (*jz_timer_callback)(void);
-//extern int __init jz_add_msc_devices(unsigned int controller, struct jz_mmc_platform_data *plat);
+extern int __init jz_add_msc_devices(unsigned int controller, struct jz_mmc_platform_data *plat);
 
 void __init board_msc_init(void);
 
@@ -162,23 +165,6 @@ void jz_board_do_sleep(unsigned long *ptr)
          * system to avoid chip select crashing with sdram when resuming from sleep mode.
          */
 
-#if defined(CONFIG_JZ4760_APUS)
-        /* GPB25/CS1_N is used as chip select for nand flash, shouldn't be change. */
-
-        /* GPB26/CS2_N is connected to nand flash, needn't be changed. */
-
-        /* GPB28/CS3_N is used as cs8900's chip select, shouldn't be changed. */
-
-	/* GPB27/CS4_N is used as NOR's chip select, shouldn't be changed. */
-#endif
-
- 	/*
-         * Enable pull for NC pins here according to your system
-	 */
-
-#if defined(CONFIG_JZ4760_APUS)
-#endif
-
 	/*
          * If you must set some GPIOs as output to high level or low level,
          * you can set them here, using:
@@ -186,11 +172,6 @@ void jz_board_do_sleep(unsigned long *ptr)
          * __gpio_set_pin(n); or  __gpio_clear_pin(n);
 	 */
 
-#if defined(CONFIG_JZ4760_APUS)
-	/* GPC7 which is used as AMPEN_N should be set to high to disable audio amplifier */
-	__gpio_as_output(32*2+7);
-	__gpio_set_pin(32*2+7);
-#endif
 
 #ifdef DEBUG
         /* Keep uart function for printing debug message */
@@ -302,8 +283,8 @@ static unsigned int cygnus_sd_8bit_get_wp(struct device *dev)
 	status = (unsigned int) __gpio_get_pin(GPIO_SD0_WP_N);
 	return (status);
 }
-
 /*
+
 struct jz_mmc_platform_data cygnus_sd_8bit_data = {
 #ifndef CONFIG_JZ_MSC0_SDIO_SUPPORT
 	.support_sdio   = 0,
@@ -330,11 +311,11 @@ struct jz_mmc_platform_data cygnus_sd_8bit_data = {
 };
 */
 
-/*
 static void cygnus_sd_4bit_gpio_init(struct device *dev)
 {
 	__gpio_as_msc1_4bit();
 	__gpio_as_output(GPIO_SD1_VCC_EN_N);
+	__gpio_set_pin(GPIO_SD1_VCC_EN_N); /* poweroff */
 	__gpio_as_input(GPIO_SD1_CD_N);
 }
 
@@ -348,20 +329,24 @@ static void cygnus_sd_4bit_power_off(struct device *dev)
 	__msc1_disable_power();
 }
 
+static void lepus_tf_cpm_start(struct device *dev)
+{
+	cpm_start_clock(CGM_MSC1);
+}
 static unsigned int cygnus_sd_4bit_status(struct device *dev)
 {
 	unsigned int status;
 
 	status = (unsigned int) __gpio_get_pin(GPIO_SD1_CD_N);
-	return (status);
+	return (!status);
 }
 
 static void cygnus_sd_4bit_plug_change(int state)
 {
 	if(state == CARD_INSERTED)
-		__gpio_as_irq_low_level(MSC1_HOTPLUG_PIN);
-	else
 		__gpio_as_irq_high_level(MSC1_HOTPLUG_PIN);
+	else
+		__gpio_as_irq_low_level(MSC1_HOTPLUG_PIN);
 }
 
 static unsigned int cygnus_sd_4bit_get_wp(struct device *dev)
@@ -384,6 +369,7 @@ struct jz_mmc_platform_data cygnus_sd_4bit_data = {
 	.init           = cygnus_sd_4bit_gpio_init,
 	.power_on       = cygnus_sd_4bit_power_on,
 	.power_off      = cygnus_sd_4bit_power_off,
+	.cpm_start	= lepus_tf_cpm_start,
 	.status		= cygnus_sd_4bit_status,
 	.plug_change	= cygnus_sd_4bit_plug_change,
 	.write_protect  = cygnus_sd_4bit_get_wp,
@@ -398,14 +384,13 @@ struct jz_mmc_platform_data cygnus_sd_4bit_data = {
 void __init board_msc_init(void)
 {
 #ifdef CONFIG_JZ_MSC0
-	jz_add_msc_devices(0, &cygnus_sd_8bit_data);
+//	jz_add_msc_devices(0, &cygnus_sd_8bit_data);
 #endif
 
 #ifdef CONFIG_JZ_MSC1
 	jz_add_msc_devices(1, &cygnus_sd_4bit_data);
 #endif
 }
-*/
 
 static void f4760_timer_callback(void)
 {
@@ -449,3 +434,89 @@ const char *get_board_type(void)
 {
 	return "Cygnus";
 }
+#if defined(CONFIG_I2C_GPIO)
+static struct i2c_board_info cygnus_gpio_i2c_devs[] __initdata = {
+        {
+                I2C_BOARD_INFO("jz_edid", 0xa0 >> 1),
+        },
+        {
+                I2C_BOARD_INFO("jz_hdcp_rx", 0x74 >> 1),
+        },
+        {
+                I2C_BOARD_INFO("jz_hey", 0xa8 >> 1),
+        },
+#if 0
+        {
+                I2C_BOARD_INFO("jz_edid_segment_ptr", 0x60 >> 1),
+        },
+        {
+                I2C_BOARD_INFO("jz_hdcp_rx_bksv", 0x00 >> 1),
+        },
+        {
+                I2C_BOARD_INFO("jz_hdcp_rx_ri", 0x08 >> 1),
+        },
+        {
+                I2C_BOARD_INFO("jz_hdcp_rx_aksv", 0x10 >> 1),
+        },
+        {
+                I2C_BOARD_INFO("jz_hdcp_rx_ainfo", 0x15 >> 1),
+        },
+        {
+                I2C_BOARD_INFO("jz_hdcp_rx_an", 0x18 >> 1),
+        },
+        {
+                I2C_BOARD_INFO("jz_hdcp_rx_sha1_hash", 0x20 >> 1),
+        },
+        {
+                I2C_BOARD_INFO("jz_hdcp_rx_bcaps", 0x40 >> 1),
+        },
+        {
+                I2C_BOARD_INFO("jz_hdcp_rx_bstatus", 0x41 >> 1),
+        },
+        {
+                I2C_BOARD_INFO("jz_hdcp_rx_ksv_fifo", 0x43 >> 1),
+        },
+#endif
+};
+
+static struct i2c_gpio_platform_data cygnus_i2c_gpio_data = {
+        .sda_pin        = GPIO_I2C1_SDA,
+        .scl_pin        = GPIO_I2C1_SCK,
+};
+
+static struct platform_device cygnus_i2c_gpio_device = {
+        .name   = "i2c-gpio",
+        .id     = 2,
+        .dev    = {
+                .platform_data = &cygnus_i2c_gpio_data,
+        },
+};
+
+
+static struct platform_device *cygnus_platform_devices[] __initdata = {
+//#if defined(CONFIG_I2C_GPIO)
+        &cygnus_i2c_gpio_device,
+//#endif
+};
+#endif
+
+static struct i2c_board_info ep932_i2c_devs[] __initdata = {
+        {
+                I2C_BOARD_INFO("jz_ep932", 0x38),
+               // .irq = GPIO_WM831x_DETECT + IRQ_GPIO_0,
+               // .platform_data = &wm831x_platform_data,
+        },
+};
+
+
+
+void __init board_i2c_init(void) {
+	i2c_register_board_info(1, ep932_i2c_devs, ARRAY_SIZE(ep932_i2c_devs));
+#if defined(CONFIG_I2C_GPIO)
+        i2c_register_board_info(2, cygnus_gpio_i2c_devs, ARRAY_SIZE(cygnus_gpio_i2c_devs));
+        platform_add_devices(cygnus_platform_devices, ARRAY_SIZE(cygnus_platform_devices));
+#endif
+
+
+}
+
diff --git a/arch/mips/jz4760/board-htb80.c b/arch/mips/jz4760/board-htb80.c
new file mode 100644
index 00000000000..8e00a05c6b5
--- /dev/null
+++ b/arch/mips/jz4760/board-htb80.c
@@ -0,0 +1,539 @@
+/*
+ * linux/arch/mips/jz4760/board-cygnus.c
+ *
+ * JZ4760 Cygnus board setup routines.
+ *
+ * Copyright (c) 2006-2010  Ingenic Semiconductor Inc.
+ * Author: <jlwei@ingenic.cn>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/ioport.h>
+#include <linux/console.h>
+#include <linux/delay.h>
+
+#include <asm/cpu.h>
+#include <asm/bootinfo.h>
+#include <asm/mipsregs.h>
+#include <asm/reboot.h>
+
+#include <asm/jzsoc.h>
+#include <linux/i2c.h>
+#include <linux/mmc/host.h>
+#include <linux/ft5x0x_ts.h>
+#include <linux/spi/spi.h>
+extern void (*jz_timer_callback)(void);
+extern int __init jz_add_msc_devices(unsigned int controller, struct jz_mmc_platform_data *plat);
+
+#undef DEBUG
+//#define DEBUG
+#ifdef DEBUG
+#define dprintk(x...)	printk(x)
+#else
+#define dprintk(x...)
+#endif
+
+/*
+ *  config_gpio_on_sleep config all gpio pins when sleep.
+ */
+struct gpio_sleep_status {
+	unsigned int input;
+	unsigned int input_pull;
+	unsigned int input_no_pull;
+	unsigned int output;
+	unsigned int output_high;
+	unsigned int output_low;
+	unsigned int no_operation;
+};
+
+void config_gpio_on_sleep(void)
+{
+	int i = 0;
+	struct gpio_sleep_status gpio_sleep_st[] = {
+		/* GPA */
+		{
+			.input_pull = BIT31 | BIT27 |
+			BITS_H2L(29,28) | /* NC pin */
+			BITS_H2L(19,0), /* NAND: SD0~SD15 */
+
+			.output_high = BIT21 | BIT22 | BIT23 | BIT24 | BIT25 | BIT26, /* NAND: CS1~CS6 */
+			.output_low = 0x0,
+			.no_operation = 0x0,
+		},
+
+		/* GPB */
+		{
+			.input_pull = BIT30 | BIT27 | BIT26 | BIT25 | BITS_H2L(24,22) | BIT20 |
+			BITS_H2L(19,0), /* SA0~SA5 */
+
+			.output_high = BIT29,
+			.output_low = BIT31 | BIT28 | BIT21,
+			.no_operation = 0x0,
+		},
+
+		/* GPC */
+		{
+			.input_pull = BITS_H2L(31,28),
+			.output_high = 0x0,
+			.output_low = BITS_H2L(27,0),
+			.no_operation = 0x0,
+		},
+
+		/* GPD */
+		{
+			.input_pull = BITS_H2L(29,26) | BITS_H2L(19,14) | BITS_H2L(13,12) || BITS_H2L(10,0) | BIT11,  // bit11 temporary input_pull
+			.output_high = 0x0,
+			.output_low =  BITS_H2L(25,20), // | BIT11,
+			.no_operation = 0x0,
+		},
+
+		/* GPE */
+		{
+			.input_pull = BITS_H2L(18,11) | BITS_H2L(8,3) | BIT0,
+			.output_high = BIT9,
+			.output_low = BITS_H2L(29,20) | BIT10 | BIT1 | BIT2,
+			.no_operation = 0x0,
+		},
+
+		/* GPF */
+		{
+			.input_pull = BIT11 | BITS_H2L(8,4) | BITS_H2L(2,0),
+			.output_high = BIT9,
+			.output_low = BIT3,
+			.no_operation = 0x0,
+		},
+	};
+
+	for (i = 0; i < 6; i++) {
+		gpio_sleep_st[i].input_pull &= ~gpio_sleep_st[i].no_operation;
+		gpio_sleep_st[i].output_high &= ~gpio_sleep_st[i].no_operation;
+		gpio_sleep_st[i].output_low &= ~gpio_sleep_st[i].no_operation;
+		gpio_sleep_st[i].input_no_pull = 0xffffffff &
+			~(gpio_sleep_st[i].input_pull |
+			  gpio_sleep_st[i].output_high |
+			  gpio_sleep_st[i].output_low) &
+			~gpio_sleep_st[i].no_operation;
+
+		gpio_sleep_st[i].input = gpio_sleep_st[i].input_pull | gpio_sleep_st[i].input_no_pull;
+		gpio_sleep_st[i].output = gpio_sleep_st[i].output_high | gpio_sleep_st[i].output_low;
+
+		/* all as gpio, except interrupt pins(see @wakeup_key_setup()) */
+		REG_GPIO_PXFUNC(i) =  0xffffffff;
+		REG_GPIO_PXSELC(i) =  0xffffffff;
+		/* input */
+		REG_GPIO_PXDIRC(i) =  gpio_sleep_st[i].input;
+		/* pull */
+		REG_GPIO_PXPEC(i) = gpio_sleep_st[i].input_pull;
+		/* no_pull */
+		REG_GPIO_PXPES(i) =  gpio_sleep_st[i].input_no_pull;
+
+		/* output */
+		REG_GPIO_PXDIRS(i) =  gpio_sleep_st[i].output;
+		REG_GPIO_PXPES(i)  = gpio_sleep_st[i].output; /* disable pull */
+		/* high */
+		REG_GPIO_PXDATS(i) = gpio_sleep_st[i].output_high;
+		/* low */
+		REG_GPIO_PXDATC(i) = gpio_sleep_st[i].output_low;
+	}
+}
+
+struct wakeup_key_s {
+	int gpio;       /* gpio pin number */
+	int active_low; /* the key interrupt pin is low voltage
+                           or fall edge acitve */
+};
+
+/* add wakeup keys here */
+static struct wakeup_key_s wakeup_key[] = {
+	{
+		.gpio = GPIO_POWER_ON,
+		.active_low = ACTIVE_LOW_WAKE_UP,
+	},
+	{
+		.gpio = MSC1_HOTPLUG_PIN,
+		.active_low = ACTIVE_LOW_MSC1_CD,
+	},
+};
+
+static void wakeup_key_setup(void)
+{
+	int i;
+	int num = sizeof(wakeup_key) / sizeof(wakeup_key[0]);
+
+	for(i = 0; i < num; i++) {
+		if(wakeup_key[i].active_low)
+			__gpio_as_irq_fall_edge(wakeup_key[i].gpio);
+		else
+			__gpio_as_irq_rise_edge(wakeup_key[i].gpio);
+
+		__gpio_ack_irq(wakeup_key[i].gpio);
+		__gpio_unmask_irq(wakeup_key[i].gpio);
+		__intc_unmask_irq(IRQ_GPIO0 - (wakeup_key[i].gpio/32));  /* unmask IRQ_GPIOn */
+	}
+}
+
+
+/* NOTES:
+ * 1: Pins that are floated (NC) should be set as input and pull-enable.
+ * 2: Pins that are pull-up or pull-down by outside should be set as input
+ *    and pull-disable.
+ * 3: Pins that are connected to a chip except sdram and nand flash
+ *    should be set as input and pull-disable, too.
+ */
+void jz_board_do_sleep(unsigned long *ptr)
+{
+	unsigned char i;
+
+        /* Print messages of GPIO registers for debug */
+	for(i=0;i<GPIO_PORT_NUM;i++) {
+		dprintk("run dat:%x pin:%x fun:%x sel:%x dir:%x pull:%x msk:%x trg:%x\n",        \
+			REG_GPIO_PXDAT(i),REG_GPIO_PXPIN(i),REG_GPIO_PXFUN(i),REG_GPIO_PXSEL(i), \
+			REG_GPIO_PXDIR(i),REG_GPIO_PXPE(i),REG_GPIO_PXIM(i),REG_GPIO_PXTRG(i));
+	}
+
+        /* Save GPIO registers */
+	for(i = 1; i < GPIO_PORT_NUM; i++) {
+		*ptr++ = REG_GPIO_PXFUN(i);
+		*ptr++ = REG_GPIO_PXSEL(i);
+		*ptr++ = REG_GPIO_PXDIR(i);
+		*ptr++ = REG_GPIO_PXPE(i);
+		*ptr++ = REG_GPIO_PXIM(i);
+		*ptr++ = REG_GPIO_PXDAT(i);
+		*ptr++ = REG_GPIO_PXTRG(i);
+	}
+
+        /*
+         * Set all pins to pull-disable, and set all pins as input except
+         * sdram and the pins which can be used as CS1_N to CS4_N for chip select.
+         */
+	config_gpio_on_sleep();
+
+        /*
+	 * Set proper status for GPC21 to GPC24 which can be used as CS1_N to CS4_N.
+	 * Keep the pins' function used for chip select(CS) here according to your
+         * system to avoid chip select crashing with sdram when resuming from sleep mode.
+         */
+
+	/*
+         * If you must set some GPIOs as output to high level or low level,
+         * you can set them here, using:
+         * __gpio_as_output(n);
+         * __gpio_set_pin(n); or  __gpio_clear_pin(n);
+	 */
+
+#if 0
+        /* Keep uart function for printing debug message */
+	__gpio_as_uart0();
+	__gpio_as_uart1();
+	__gpio_as_uart2();
+	__gpio_as_uart3();
+
+        /* Print messages of GPIO registers for debug */
+	for(i=0;i<GPIO_PORT_NUM;i++) {
+		printk("GP%d: data:0x%08x pin:0x%08x fun:0x%08x sel:0x%08x dir:0x%08x pull:0x%08x msk:0x%08x trg:0x%08x\n",
+		       i, REG_GPIO_PXDAT(i),REG_GPIO_PXPIN(i),REG_GPIO_PXFUN(i),REG_GPIO_PXSEL(i),
+		       REG_GPIO_PXDIR(i),REG_GPIO_PXPE(i),REG_GPIO_PXIM(i),REG_GPIO_PXTRG(i));
+	}
+#endif
+	wakeup_key_setup();
+}
+
+void jz_board_do_resume(unsigned long *ptr)
+{
+	unsigned char i;
+
+	/* Restore GPIO registers */
+	for(i = 1; i < GPIO_PORT_NUM; i++) {
+		 REG_GPIO_PXFUNS(i) = *ptr;
+		 REG_GPIO_PXFUNC(i) = ~(*ptr++);
+
+		 REG_GPIO_PXSELS(i) = *ptr;
+		 REG_GPIO_PXSELC(i) = ~(*ptr++);
+
+		 REG_GPIO_PXDIRS(i) = *ptr;
+		 REG_GPIO_PXDIRC(i) = ~(*ptr++);
+
+		 REG_GPIO_PXPES(i) = *ptr;
+		 REG_GPIO_PXPEC(i) = ~(*ptr++);
+
+		 REG_GPIO_PXIMS(i)=*ptr;
+		 REG_GPIO_PXIMC(i)=~(*ptr++);
+
+		 REG_GPIO_PXDATS(i)=*ptr;
+		 REG_GPIO_PXDATC(i)=~(*ptr++);
+
+		 REG_GPIO_PXTRGS(i)=*ptr;
+		 REG_GPIO_PXTRGC(i)=~(*ptr++);
+	}
+
+        /* Print messages of GPIO registers for debug */
+	for(i=0;i<GPIO_PORT_NUM;i++) {
+		dprintk("resume dat:%x pin:%x fun:%x sel:%x dir:%x pull:%x msk:%x trg:%x\n",     \
+			REG_GPIO_PXDAT(i),REG_GPIO_PXPIN(i),REG_GPIO_PXFUN(i),REG_GPIO_PXSEL(i), \
+			REG_GPIO_PXDIR(i),REG_GPIO_PXPE(i),REG_GPIO_PXIM(i),REG_GPIO_PXTRG(i));
+	}
+}
+
+static void htb80_tf_gpio_init(struct device *dev)
+{
+	__gpio_as_msc1_4bit();
+	__gpio_as_output(GPIO_SD1_VCC_EN_N);
+	__gpio_set_pin(GPIO_SD1_VCC_EN_N); /* poweroff */
+	__gpio_as_input(GPIO_SD1_CD_N);
+}
+
+static void htb80_tf_power_on(struct device *dev)
+{
+	__gpio_clear_pin(GPIO_SD1_VCC_EN_N);
+}
+
+static void htb80_tf_power_off(struct device *dev)
+{
+	__gpio_set_pin(GPIO_SD1_VCC_EN_N);
+}
+
+static void htb80_tf_cpm_start(struct device *dev)
+{
+	cpm_start_clock(CGM_MSC1);
+}
+
+static unsigned int htb80_tf_status(struct device *dev)
+{
+	unsigned int status = 0;
+	status = (unsigned int) __gpio_get_pin(GPIO_SD1_CD_N);
+#if ACTIVE_LOW_MSC1_CD
+	return !status;
+#else
+	return status;
+#endif
+}
+
+static void htb80_tf_plug_change(int state)
+{
+	if(state == CARD_INSERTED) /* wait for remove */
+#if ACTIVE_LOW_MSC1_CD
+		__gpio_as_irq_high_level(MSC1_HOTPLUG_PIN);
+#else
+		__gpio_as_irq_low_level(MSC1_HOTPLUG_PIN);
+#endif
+	else		      /* wait for insert */
+#if ACTIVE_LOW_MSC1_CD
+		__gpio_as_irq_low_level(MSC1_HOTPLUG_PIN);
+#else
+		__gpio_as_irq_high_level(MSC1_HOTPLUG_PIN);
+#endif
+}
+
+struct jz_mmc_platform_data htb80_tf_data = {
+#ifndef CONFIG_JZ_MSC1_SDIO_SUPPORT
+	.support_sdio   = 0,
+#else
+	.support_sdio   = 1,
+#endif
+	.ocr_mask	= MMC_VDD_32_33 | MMC_VDD_33_34,
+	.status_irq	= IRQ_GPIO_0 + GPIO_SD1_CD_N,
+	.detect_pin     = GPIO_SD1_CD_N,
+	.init           = htb80_tf_gpio_init,
+	.power_on       = htb80_tf_power_on,
+	.power_off      = htb80_tf_power_off,
+	.cpm_start	= htb80_tf_cpm_start,
+	.status		= htb80_tf_status,
+	.plug_change	= htb80_tf_plug_change,
+	.max_bus_width  = MMC_CAP_SD_HIGHSPEED
+#ifdef CONFIG_JZ_MSC1_BUS_4
+	| MMC_CAP_4_BIT_DATA
+#endif
+	,
+
+#ifdef CONFIG_JZ_MSC1_BUS_1
+	.bus_width      = 1,
+#else
+	.bus_width      = 4,
+#endif
+};
+
+static void htb80_wifi_gpio_init(struct device *dev)
+{
+	__gpio_as_msc2_4bit();
+	__gpio_as_output(GPIO_SD2_VCC_EN_N);
+	__gpio_set_pin(GPIO_SD2_VCC_EN_N);
+	__gpio_as_input(GPIO_SD2_CD_N);
+
+	__gpio_as_output(GPIO_WIFI_PDn);
+	__gpio_clear_pin(GPIO_WIFI_PDn); /* default to poweroff the wifi */
+}
+
+static void htb80_wifi_power_on(struct device *dev)
+{
+	__gpio_clear_pin(GPIO_SD2_VCC_EN_N);
+	msleep(10);
+	__gpio_set_pin(GPIO_WIFI_PDn);
+}
+
+static void htb80_wifi_power_off(struct device *dev)
+{
+	__gpio_clear_pin(GPIO_WIFI_PDn);
+	msleep(10);
+	__gpio_set_pin(GPIO_SD2_VCC_EN_N);
+}
+
+static void htb80_wifi_cpm_start(struct device *dev)
+{
+	cpm_start_clock(CGM_MSC2);
+}
+
+static unsigned int htb80_wifi_status(struct device *dev)
+{
+	unsigned int status = 0;
+	status = (unsigned int) __gpio_get_pin(GPIO_SD2_CD_N);
+#if ACTIVE_LOW_MSC2_CD
+	return !status;
+#else
+	return status;
+#endif
+}
+
+static void htb80_wifi_plug_change(int state)
+{
+	if(state == CARD_INSERTED) /* wait for remove */
+#if ACTIVE_LOW_MSC2_CD
+		__gpio_as_irq_high_level(MSC2_HOTPLUG_PIN);
+#else
+	__gpio_as_irq_low_level(MSC2_HOTPLUG_PIN);
+#endif
+	else		      /* wait for insert */
+#if ACTIVE_LOW_MSC2_CD
+		__gpio_as_irq_low_level(MSC2_HOTPLUG_PIN);
+#else
+	__gpio_as_irq_high_level(MSC2_HOTPLUG_PIN);
+#endif
+}
+
+struct jz_mmc_platform_data htb80_wifi_data = {
+#ifndef CONFIG_JZ_MSC2_SDIO_SUPPORT
+	.support_sdio   = 0,
+#else
+	.support_sdio   = 1,
+#endif
+	.ocr_mask	= MMC_VDD_32_33 | MMC_VDD_33_34,
+	.status_irq	= IRQ_GPIO_0 + GPIO_SD2_CD_N,
+	.detect_pin     = GPIO_SD2_CD_N,
+	.init           = htb80_wifi_gpio_init,
+	.power_on       = htb80_wifi_power_on,
+	.power_off      = htb80_wifi_power_off,
+	.cpm_start	= htb80_wifi_cpm_start,
+	.status		= htb80_wifi_status,
+	.plug_change	= htb80_wifi_plug_change,
+	.max_bus_width  = MMC_CAP_SD_HIGHSPEED | MMC_CAP_4_BIT_DATA,
+#ifdef CONFIG_JZ_MSC2_BUS_1
+	.bus_width      = 1,
+#else
+	.bus_width      = 4,
+#endif
+};
+
+void __init board_msc_init(void)
+{
+	jz_add_msc_devices(1, &htb80_tf_data);
+	jz_add_msc_devices(2, &htb80_wifi_data);
+}
+
+static void f4760_timer_callback(void)
+{
+	static unsigned long count = 0;
+
+	if ((++count) % 50 == 0) {
+//		dancing();
+		count = 0;
+	}
+}
+
+static void __init board_cpm_setup(void)
+{
+	/* Stop unused module clocks here.
+	 * We have started all module clocks at arch/mips/jz4760/setup.c.
+	 */
+}
+
+static void __init board_gpio_setup(void)
+{
+	/*
+	 * Initialize SDRAM pins
+	 */
+}
+
+static struct ft5x0x_ts_platform_data ft5x0x_ts_pdata = {
+	        .intr = GPIO_TS_I2C_INT,
+};
+static struct i2c_board_info htb80_i2c0_devs[] __initdata = {
+	{
+		I2C_BOARD_INFO("cm3511", 0x30),
+	},
+	{
+		I2C_BOARD_INFO("ov3640", 0x3c),
+	},
+	{
+		I2C_BOARD_INFO("ov7690", 0x21),
+	},
+	{
+	        I2C_BOARD_INFO(FT5X0X_NAME, 0x38),
+	       .irq = GPIO_TS_I2C_IRQ,
+	       .platform_data = &ft5x0x_ts_pdata,
+	},
+	{
+	},
+};
+/* SPI devices */
+struct spi_board_info jz4760_spi0_board_info[]  = {
+	[0] = {
+		.modalias       = "spidev0",
+		.bus_num        = 0,
+		.chip_select    = 0,
+		.max_speed_hz   = 120000,
+/*		.platform_data	= &spitest,*/
+	},
+	[1] = {
+		.modalias       = "spitest",
+		.bus_num        = 0,
+		.chip_select    = 1,
+		.max_speed_hz   = 2500000,
+/*		.platform_data	= */
+	},
+};
+struct spi_board_info jz4760_spi1_board_info[]  = {
+	[0] = {
+		.modalias       = "spidev1",
+		.bus_num        = 1,
+		.chip_select    = 0,
+		.max_speed_hz   = 12000000,
+	},
+};
+
+void __init board_i2c_init(void) {
+	i2c_register_board_info(0, htb80_i2c0_devs, ARRAY_SIZE(htb80_i2c0_devs));
+}
+void __init board_spi_init(void){
+	spi_register_board_info(jz4760_spi0_board_info,ARRAY_SIZE(jz4760_spi0_board_info));
+	spi_register_board_info(jz4760_spi1_board_info,ARRAY_SIZE(jz4760_spi1_board_info));
+}
+void __init jz_board_setup(void)
+{
+	printk("JZ4760 HTB80 board setup\n");
+	board_cpm_setup();
+	board_gpio_setup();
+
+	jz_timer_callback = f4760_timer_callback;
+}
+
+/**
+ * Called by arch/mips/kernel/proc.c when 'cat /proc/cpuinfo'.
+  */
+const char *get_board_type(void)
+{
+	return "HTB80";
+}
diff --git a/arch/mips/jz4760/board-lepus.c b/arch/mips/jz4760/board-lepus.c
index d3b43c8d0a3..709934b9f01 100644
--- a/arch/mips/jz4760/board-lepus.c
+++ b/arch/mips/jz4760/board-lepus.c
@@ -24,8 +24,9 @@
 
 #include <asm/jzsoc.h>
 #include <linux/i2c.h>
-#include <asm/jzmmc/jz_mmc_platform_data.h>
+#include <linux/mmc/host.h>
 #include <linux/ft5x0x_ts.h>
+#include <linux/spi/spi.h>
 extern void (*jz_timer_callback)(void);
 extern int __init jz_add_msc_devices(unsigned int controller, struct jz_mmc_platform_data *plat);
 
@@ -38,28 +39,116 @@ extern int __init jz_add_msc_devices(unsigned int controller, struct jz_mmc_plat
 #endif
 
 /*
- * __gpio_as_sleep set all pins to pull-disable, and set all pins as input
- * except sdram and the pins which can be used as CS1_N to CS4_N for chip select.
+ *  config_gpio_on_sleep config all gpio pins when sleep.
  */
-#define __gpio_as_sleep()	              \
-do {	                                      \
-	REG_GPIO_PXFUNC(1) = ~0x03ff7fff;     \
-	REG_GPIO_PXSELC(1) = ~0x03ff7fff;     \
-	REG_GPIO_PXDIRC(1) = ~0x03ff7fff;     \
-	REG_GPIO_PXPES(1)  =  0xffffffff;     \
-	REG_GPIO_PXFUNC(2) = ~0x01e00000;     \
-	REG_GPIO_PXSELC(2) = ~0x01e00000;     \
-	REG_GPIO_PXDIRC(2) = ~0x01e00000;     \
-	REG_GPIO_PXPES(2)  =  0xffffffff;     \
-	REG_GPIO_PXFUNC(4) =  0xffffffff;     \
-	REG_GPIO_PXSELC(4) =  0xffffffff;     \
-	REG_GPIO_PXDIRC(4) =  0xffffffff;     \
-	REG_GPIO_PXPES(4)  =  0xffffffff;     \
-	REG_GPIO_PXFUNC(5) =  0xffffffff;     \
-	REG_GPIO_PXSELC(5) =  0xffffffff;     \
-	REG_GPIO_PXDIRC(5) =  0xffffffff;     \
-	REG_GPIO_PXPES(5)  =  0xffffffff;     \
-} while (0)
+struct gpio_sleep_status {
+	unsigned int input;
+	unsigned int input_pull;
+	unsigned int input_no_pull;
+	unsigned int output;
+	unsigned int output_high;
+	unsigned int output_low;
+	unsigned int no_operation;
+};
+
+void config_gpio_on_sleep(void)
+{
+	int i = 0;
+	struct gpio_sleep_status gpio_sleep_st[] = {
+		/* GPA */
+		{
+			.input_pull = BIT31 | BIT27 |
+			BITS_H2L(29,28) | /* NC pin */
+			BITS_H2L(19,0), /* NAND: SD0~SD15 */
+
+			.output_high = BIT21 | BIT22 | BIT23 | BIT24 | BIT25 | BIT26, /* NAND: CS1~CS6 */
+			.output_low = 0x0,
+#ifndef CONFIG_JZ_SYSTEM_AT_CARD
+			.no_operation = 0x0,
+#else
+			.no_operation = BITS_H2L(23, 18),
+#endif
+		},
+
+		/* GPB */
+		{
+			.input_pull = BIT30 | BIT27 | BIT26 | BIT25 | BITS_H2L(24,22) | BIT20 |
+			BITS_H2L(19,0), /* SA0~SA5 */
+
+			.output_high = BIT29,
+			.output_low = BIT31 | BIT28 | BIT21,
+#ifndef CONFIG_JZ_SYSTEM_AT_CARD
+			.no_operation = 0x0,
+#else
+			.no_operation = BIT0,
+#endif
+		},
+
+		/* GPC */
+		{
+			.input_pull = BITS_H2L(31,28),
+			.output_high = 0x0,
+			.output_low = BITS_H2L(27,0),
+			.no_operation = 0x0,
+		},
+
+		/* GPD */
+		{
+			.input_pull = BITS_H2L(29,26) | BITS_H2L(19,14) | BITS_H2L(13,12) || BITS_H2L(10,0) | BIT11,  // bit11 temporary input_pull
+			.output_high = 0x0,
+			.output_low =  BITS_H2L(25,20), // | BIT11,
+			.no_operation = 0x0,
+		},
+
+		/* GPE */
+		{
+			.input_pull = BITS_H2L(18,11) | BITS_H2L(8,3) | BIT0,
+			.output_high = BIT9,
+			.output_low = BITS_H2L(29,20) | BIT10 | BIT1 | BIT2,
+			.no_operation = 0x0,
+		},
+
+		/* GPF */
+		{
+			.input_pull = BIT11 | BITS_H2L(8,4) | BITS_H2L(2,0),
+			.output_high = BIT9,
+			.output_low = BIT3,
+			.no_operation = 0x0,
+		},
+	};
+
+	for (i = 0; i < 6; i++) {
+		gpio_sleep_st[i].input_pull &= ~gpio_sleep_st[i].no_operation;
+		gpio_sleep_st[i].output_high &= ~gpio_sleep_st[i].no_operation;
+		gpio_sleep_st[i].output_low &= ~gpio_sleep_st[i].no_operation;
+		gpio_sleep_st[i].input_no_pull = 0xffffffff &
+			~(gpio_sleep_st[i].input_pull |
+			  gpio_sleep_st[i].output_high |
+			  gpio_sleep_st[i].output_low) &
+			~gpio_sleep_st[i].no_operation;
+
+		gpio_sleep_st[i].input = gpio_sleep_st[i].input_pull | gpio_sleep_st[i].input_no_pull;
+		gpio_sleep_st[i].output = gpio_sleep_st[i].output_high | gpio_sleep_st[i].output_low;
+
+		/* all as gpio, except interrupt pins(see @wakeup_key_setup()) */
+		REG_GPIO_PXFUNC(i) =  (0xffffffff & ~gpio_sleep_st[i].no_operation);
+		REG_GPIO_PXSELC(i) =  (0xffffffff & ~gpio_sleep_st[i].no_operation);
+		/* input */
+		REG_GPIO_PXDIRC(i) =  gpio_sleep_st[i].input;
+		/* pull */
+		REG_GPIO_PXPEC(i) = gpio_sleep_st[i].input_pull;
+		/* no_pull */
+		REG_GPIO_PXPES(i) =  gpio_sleep_st[i].input_no_pull;
+
+		/* output */
+		REG_GPIO_PXDIRS(i) =  gpio_sleep_st[i].output;
+		REG_GPIO_PXPES(i)  = gpio_sleep_st[i].output; /* disable pull */
+		/* high */
+		REG_GPIO_PXDATS(i) = gpio_sleep_st[i].output_high;
+		/* low */
+		REG_GPIO_PXDATC(i) = gpio_sleep_st[i].output_low;
+	}
+}
 
 struct wakeup_key_s {
 	int gpio;       /* gpio pin number */
@@ -73,10 +162,12 @@ static struct wakeup_key_s wakeup_key[] = {
 		.gpio = GPIO_POWER_ON,
 		.active_low = ACTIVE_LOW_WAKE_UP,
 	},
+#ifndef CONFIG_JZ_SYSTEM_AT_CARD
 	{
 		.gpio = MSC0_HOTPLUG_PIN,
 		.active_low = ACTIVE_LOW_MSC0_CD,
 	},
+#endif
 	{
 		.gpio = MSC1_HOTPLUG_PIN,
 		.active_low = ACTIVE_LOW_MSC1_CD,
@@ -134,7 +225,7 @@ void jz_board_do_sleep(unsigned long *ptr)
          * Set all pins to pull-disable, and set all pins as input except
          * sdram and the pins which can be used as CS1_N to CS4_N for chip select.
          */
-//        __gpio_as_sleep();
+	config_gpio_on_sleep();
 
         /*
 	 * Set proper status for GPC21 to GPC24 which can be used as CS1_N to CS4_N.
@@ -149,7 +240,10 @@ void jz_board_do_sleep(unsigned long *ptr)
          * __gpio_set_pin(n); or  __gpio_clear_pin(n);
 	 */
 
-#ifdef DEBUG
+	if (!console_suspend_enabled)
+		__gpio_as_uart1();
+
+#if 0
         /* Keep uart function for printing debug message */
 	__gpio_as_uart0();
 	__gpio_as_uart1();
@@ -158,9 +252,9 @@ void jz_board_do_sleep(unsigned long *ptr)
 
         /* Print messages of GPIO registers for debug */
 	for(i=0;i<GPIO_PORT_NUM;i++) {
-		dprintk("sleep dat:%x pin:%x fun:%x sel:%x dir:%x pull:%x msk:%x trg:%x\n",      \
-			REG_GPIO_PXDAT(i),REG_GPIO_PXPIN(i),REG_GPIO_PXFUN(i),REG_GPIO_PXSEL(i), \
-			REG_GPIO_PXDIR(i),REG_GPIO_PXPE(i),REG_GPIO_PXIM(i),REG_GPIO_PXTRG(i));
+		printk("GP%d: data:0x%08x pin:0x%08x fun:0x%08x sel:0x%08x dir:0x%08x pull:0x%08x msk:0x%08x trg:0x%08x\n",
+		       i, REG_GPIO_PXDAT(i),REG_GPIO_PXPIN(i),REG_GPIO_PXFUN(i),REG_GPIO_PXSEL(i),
+		       REG_GPIO_PXDIR(i),REG_GPIO_PXPE(i),REG_GPIO_PXIM(i),REG_GPIO_PXTRG(i));
 	}
 #endif
 	wakeup_key_setup();
@@ -204,8 +298,13 @@ void jz_board_do_resume(unsigned long *ptr)
 
 static void lepus_sd_gpio_init(struct device *dev)
 {
+#if defined (CONFIG_JZ_SYSTEM_AT_CARD)
+	__gpio_as_msc0_boot();
+#else
 	__gpio_as_msc0_8bit();
+#endif
 	__gpio_as_output(GPIO_SD0_VCC_EN_N);
+	__gpio_set_pin(GPIO_SD0_VCC_EN_N); /* poweroff */
 	__gpio_as_input(GPIO_SD0_CD_N);
 }
 
@@ -226,6 +325,9 @@ static void lepus_sd_cpm_start(struct device *dev)
 
 static unsigned int lepus_sd_status(struct device *dev)
 {
+#if defined(CONFIG_JZ_SYSTEM_AT_CARD)
+	return 1;
+#else
 	unsigned int status;
 
 	status = (unsigned int) __gpio_get_pin(GPIO_SD0_CD_N);
@@ -234,42 +336,54 @@ static unsigned int lepus_sd_status(struct device *dev)
 #else
 	return status;
 #endif
+#endif
 }
 
-#if 0
-static void lepus_sd_plug_change(int state)
-{
-	if(state == CARD_INSERTED)
-		__gpio_as_irq_high_level(MSC0_HOTPLUG_PIN); /* wait remove */
-	else
-		__gpio_as_irq_low_level(MSC0_HOTPLUG_PIN); /* wait insert */
-}
-#else
 static void lepus_sd_plug_change(int state)
 {
 	if(state == CARD_INSERTED) /* wait for remove */
 #if ACTIVE_LOW_MSC0_CD
-		__gpio_as_irq_rise_edge(MSC0_HOTPLUG_PIN);
+		__gpio_as_irq_high_level(MSC0_HOTPLUG_PIN);
 #else
-		__gpio_as_irq_fall_edge(MSC0_HOTPLUG_PIN);
+		__gpio_as_irq_low_level(MSC0_HOTPLUG_PIN);
 #endif
 	else		      /* wait for insert */
 #if ACTIVE_LOW_MSC0_CD
-		__gpio_as_irq_fall_edge(MSC0_HOTPLUG_PIN);
+		__gpio_as_irq_low_level(MSC0_HOTPLUG_PIN);
 #else
-		__gpio_as_irq_rise_edge(MSC0_HOTPLUG_PIN);
+		__gpio_as_irq_high_level(MSC0_HOTPLUG_PIN);
 #endif
 }
-#endif
 
 static unsigned int lepus_sd_get_wp(struct device *dev)
 {
+#if defined(CONFIG_JZ_SYSTEM_AT_CARD)
+	return 0;
+#else
+	int i = 0;
 	unsigned int status;
 
-	status = (unsigned int) __gpio_get_pin(MSC0_WP_PIN);
+	for (i = 0; i < 5; i++) {
+		status = (unsigned int) __gpio_get_pin(MSC0_WP_PIN);
+		schedule_timeout(HZ/100); /* 10ms */
+	}
 	return (status);
+#endif
 }
-
+#if defined(CONFIG_JZ_RECOVERY_SUPPORT) && defined(CONFIG_JZ_SYSTEM_AT_CARD)
+struct mmc_partition_info lepus_partitions[] = {
+	[0] = {"mbr",0,512,0},//0 - 512
+	[1] = {"uboot",512,3*1024*1024-512,0}, // 512 - 2.5MB
+	[2] = {"misc",0x3000000,0x1000000,0},//3MB - 1MB
+	[3] = {"kernel",0x400000,0x400000,0},//4MB - 4MB
+	[4] = {"recovery",0x800000,0x400000,0},//8MB -4MB
+
+	[5] = {"rootfs",12*1024*1024,256*1024*1024,1}, //12MB - 256MB
+	[6] = {"data",268*1024*1024,500*1024*1024,1},//268MB - 500MB
+	[7] = {"cache",768*1024*1024,32*1024*1024,1},//768MB - 32MB
+	[8] = {"test_0",0x0,0xffffffff,0},
+};
+#endif
 struct jz_mmc_platform_data lepus_sd_data = {
 #ifndef CONFIG_JZ_MSC0_SDIO_SUPPORT
 	.support_sdio   = 0,
@@ -277,8 +391,13 @@ struct jz_mmc_platform_data lepus_sd_data = {
 	.support_sdio   = 1,
 #endif
 	.ocr_mask	= MMC_VDD_32_33 | MMC_VDD_33_34,
+#if defined(CONFIG_JZ_SYSTEM_AT_CARD)
+	.status_irq	= 0,
+	.detect_pin     = 0,
+#else
 	.status_irq	= MSC0_HOTPLUG_IRQ,
 	.detect_pin     = GPIO_SD0_CD_N,
+#endif
 	.init           = lepus_sd_gpio_init,
 	.power_on       = lepus_sd_power_on,
 	.power_off      = lepus_sd_power_off,
@@ -286,7 +405,15 @@ struct jz_mmc_platform_data lepus_sd_data = {
 	.status		= lepus_sd_status,
 	.plug_change	= lepus_sd_plug_change,
 	.write_protect  = lepus_sd_get_wp,
-	.max_bus_width  = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | MMC_CAP_4_BIT_DATA,
+	.max_bus_width  = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED
+#ifdef CONFIG_JZ_MSC0_BUS_4
+	| MMC_CAP_4_BIT_DATA
+#endif
+#ifdef CONFIG_JZ_MSC0_BUS_8
+	| MMC_CAP_8_BIT_DATA
+#endif
+	,
+
 #ifdef CONFIG_JZ_MSC0_BUS_1
 	.bus_width      = 1,
 #elif defined  CONFIG_JZ_MSC0_BUS_4
@@ -294,12 +421,17 @@ struct jz_mmc_platform_data lepus_sd_data = {
 #else
 	.bus_width      = 8,
 #endif
+#if defined(CONFIG_JZ_RECOVERY_SUPPORT) && defined(CONFIG_JZ_SYSTEM_AT_CARD)
+	.partitions = lepus_partitions,
+	.num_partitions = ARRAY_SIZE(lepus_partitions),
+#endif
 };
 
 static void lepus_tf_gpio_init(struct device *dev)
 {
 	__gpio_as_msc1_4bit();
 	__gpio_as_output(GPIO_SD1_VCC_EN_N);
+	__gpio_set_pin(GPIO_SD1_VCC_EN_N); /* poweroff */
 	__gpio_as_input(GPIO_SD1_CD_N);
 }
 
@@ -329,31 +461,21 @@ static unsigned int lepus_tf_status(struct device *dev)
 #endif
 }
 
-#if 0
-static void lepus_tf_plug_change(int state)
-{
-	if(state == CARD_INSERTED)
-		__gpio_as_irq_low_level(MSC1_HOTPLUG_PIN);
-	else
-		__gpio_as_irq_high_level(MSC1_HOTPLUG_PIN);
-}
-#else
 static void lepus_tf_plug_change(int state)
 {
 	if(state == CARD_INSERTED) /* wait for remove */
 #if ACTIVE_LOW_MSC1_CD
-		__gpio_as_irq_rise_edge(MSC1_HOTPLUG_PIN);
+		__gpio_as_irq_high_level(MSC1_HOTPLUG_PIN);
 #else
-		__gpio_as_irq_fall_edge(MSC1_HOTPLUG_PIN);
+		__gpio_as_irq_low_level(MSC1_HOTPLUG_PIN);
 #endif
 	else		      /* wait for insert */
 #if ACTIVE_LOW_MSC1_CD
-		__gpio_as_irq_fall_edge(MSC1_HOTPLUG_PIN);
+		__gpio_as_irq_low_level(MSC1_HOTPLUG_PIN);
 #else
-		__gpio_as_irq_rise_edge(MSC1_HOTPLUG_PIN);
+		__gpio_as_irq_high_level(MSC1_HOTPLUG_PIN);
 #endif
 }
-#endif
 
 struct jz_mmc_platform_data lepus_tf_data = {
 #ifndef CONFIG_JZ_MSC1_SDIO_SUPPORT
@@ -370,7 +492,12 @@ struct jz_mmc_platform_data lepus_tf_data = {
 	.cpm_start	= lepus_tf_cpm_start,
 	.status		= lepus_tf_status,
 	.plug_change	= lepus_tf_plug_change,
-	.max_bus_width  = MMC_CAP_SD_HIGHSPEED | MMC_CAP_4_BIT_DATA,
+	.max_bus_width  = MMC_CAP_SD_HIGHSPEED
+#ifdef CONFIG_JZ_MSC1_BUS_4
+	| MMC_CAP_4_BIT_DATA
+#endif
+	,
+
 #ifdef CONFIG_JZ_MSC1_BUS_1
 	.bus_width      = 1,
 #else
@@ -378,17 +505,68 @@ struct jz_mmc_platform_data lepus_tf_data = {
 #endif
 };
 
-void __init board_msc_init(void)
+static void lepus_msc2_gpio_init(struct device *dev)
 {
-#ifdef CONFIG_JZ_MSC0
-	printk("add msc0......\n");
-	jz_add_msc_devices(0, &lepus_sd_data);
+	return;
+}
+
+static void lepus_msc2_power_on(struct device *dev)
+{
+	return;
+}
+
+static void lepus_msc2_power_off(struct device *dev)
+{
+	return;
+}
+
+static void lepus_msc2_cpm_start(struct device *dev)
+{
+	cpm_start_clock(CGM_MSC2);
+}
+
+static unsigned int lepus_msc2_status(struct device *dev)
+{
+	return 0;	      /* default: no card */
+}
+
+static void lepus_msc2_plug_change(int state)
+{
+	return;
+}
+
+struct jz_mmc_platform_data lepus_msc2_data = {
+#ifndef CONFIG_JZ_MSC2_SDIO_SUPPORT
+	.support_sdio   = 0,
+#else
+	.support_sdio   = 1,
+#endif
+	.ocr_mask	= MMC_VDD_32_33 | MMC_VDD_33_34,
+	.status_irq	= 0, //MSC1_HOTPLUG_IRQ,
+	.detect_pin     = 0, //GPIO_SD1_CD_N,
+	.init           = lepus_msc2_gpio_init,
+	.power_on       = lepus_msc2_power_on,
+	.power_off      = lepus_msc2_power_off,
+	.cpm_start	= lepus_msc2_cpm_start,
+	.status		= lepus_msc2_status,
+	.plug_change	= lepus_msc2_plug_change,
+	.max_bus_width  = MMC_CAP_SD_HIGHSPEED
+#ifdef CONFIG_JZ_MSC2_BUS_4
+	| MMC_CAP_4_BIT_DATA
+#endif
+	,
+#ifdef CONFIG_JZ_MSC2_BUS_1
+	.bus_width      = 1,
+#else
+	.bus_width      = 4,
 #endif
+};
 
-#ifdef CONFIG_JZ_MSC1
-	printk("add msc1......\n");
+void __init board_msc_init(void)
+{
+	jz_add_msc_devices(0, &lepus_sd_data);
 	jz_add_msc_devices(1, &lepus_tf_data);
-#endif
+	jz_add_msc_devices(2, &lepus_msc2_data);
 }
 
 static void f4760_timer_callback(void)
@@ -429,18 +607,69 @@ static struct i2c_board_info lepus_i2c0_devs[] __initdata = {
 		I2C_BOARD_INFO("ov7690", 0x21),
 	},
 	{
-	        I2C_BOARD_INFO(FT5X0X_NAME, 0x38),
+	        I2C_BOARD_INFO(FT5X0X_NAME, 0x36),
 	       .irq = GPIO_TS_I2C_IRQ,
 	       .platform_data = &ft5x0x_ts_pdata,
 	},
 	{
 	},
 };
+/* SPI devices */
+struct spi_board_info jz4760_spi0_board_info[]  = {
+	[0] = {
+		.modalias       = "spidev0",
+		.bus_num        = 0,
+		.chip_select    = 0,
+		.max_speed_hz   = 120000,
+/*		.platform_data	= &spitest,*/
+	},
+	[1] = {
+		.modalias       = "spitest",
+		.bus_num        = 0,
+		.chip_select    = 1,
+		.max_speed_hz   = 2500000,
+/*		.platform_data	= */
+	},
+};
+struct spi_board_info jz4760_spi1_board_info[]  = {
+	[0] = {
+		.modalias       = "spidev1",
+		.bus_num        = 1,
+		.chip_select    = 0,
+		.max_speed_hz   = 12000000,
+	},
+};
+
+#ifdef CONFIG_JZ4760_HDMI_DISPLAY
+static struct i2c_board_info ep932_i2c_devs[] __initdata = {
+        {
+                I2C_BOARD_INFO("jz_ep932", 0x38),
+        },
+        {
+                I2C_BOARD_INFO("jz_edid", 0xa0 >> 1),
+        },
+        #if 0
+        {
+                I2C_BOARD_INFO("jz_hdcp_rx", 0x74 >> 1),
+        },
+        {
+                I2C_BOARD_INFO("jz_hey", 0xa8 >> 1),
+        },
+        #endif
+};
+#endif
+
 
 void __init board_i2c_init(void) {
 	i2c_register_board_info(0, lepus_i2c0_devs, ARRAY_SIZE(lepus_i2c0_devs));
+	#ifdef CONFIG_JZ4760_HDMI_DISPLAY
+  i2c_register_board_info(0, ep932_i2c_devs, ARRAY_SIZE(ep932_i2c_devs));
+#endif
+}
+void __init board_spi_init(void){
+	spi_register_board_info(jz4760_spi0_board_info,ARRAY_SIZE(jz4760_spi0_board_info));
+	spi_register_board_info(jz4760_spi1_board_info,ARRAY_SIZE(jz4760_spi1_board_info));
 }
-
 void __init jz_board_setup(void)
 {
 	printk("JZ4760 Lepus board setup\n");
diff --git a/arch/mips/jz4760/cpm.c b/arch/mips/jz4760/cpm.c
index 901041e6fdc..1ea62822ff4 100644
--- a/arch/mips/jz4760/cpm.c
+++ b/arch/mips/jz4760/cpm.c
@@ -9,6 +9,7 @@
  */
 
 #include <asm/jzsoc.h>
+#include <linux/module.h>
 
 
 #ifndef JZ_EXTAL
@@ -70,6 +71,7 @@ unsigned int cpm_get_pllout(void)
 
         return pllout;
 }
+EXPORT_SYMBOL(cpm_get_pllout);
 
 /*
  * Get the PLL2 clock
@@ -105,6 +107,7 @@ unsigned int cpm_get_pllout1(void)
 
         return pll_out;
 }
+EXPORT_SYMBOL(cpm_get_pllout1);
 
 /*
  * Start the module clock
@@ -134,6 +137,7 @@ void cpm_start_clock(clock_gate_module module_name)
                         break;
        }
 }
+EXPORT_SYMBOL(cpm_start_clock);
 
 /*
  * Stop the module clock
@@ -165,6 +169,7 @@ void cpm_stop_clock(clock_gate_module module_name)
                         break;
         }
 }
+EXPORT_SYMBOL(cpm_stop_clock);
 
 /*
  * Get the clock, assigned by the clock_name, and the return value unit is Hz
@@ -393,6 +398,7 @@ unsigned int cpm_get_clock(cgu_clock clock_name)
 
         return clock_hz;
 }
+EXPORT_SYMBOL(cpm_get_clock);
 
 /*
  * Check div value whether valid, if invalid, return the max valid value
@@ -494,9 +500,9 @@ unsigned int cpm_set_clock(cgu_clock clock_name, unsigned int clock_hz)
 		break;
 
 	case CGU_UHCCLK:
-		div = nearbyint(pllclk , clock_hz) - 1;
+		div = nearbyint(pllclk1 , clock_hz) - 1;
 		div = __check_div(div, UHCCDR_UHCDIV_LSB, UHCCDR_UHCDIV_MASK);
-		OUTREG32(CPM_UHCCDR, div);
+		OUTREG32(CPM_UHCCDR, div | UHCCDR_UHPCS);
 		break;
 
         default:
@@ -510,6 +516,7 @@ unsigned int cpm_set_clock(cgu_clock clock_name, unsigned int clock_hz)
 
         return actual_clock;
 }
+EXPORT_SYMBOL(cpm_set_clock);
 
  /*
   * Control UHC phy, if en is NON-ZERO, enable the UHC phy, otherwise disable
diff --git a/arch/mips/jz4760/dma.c b/arch/mips/jz4760/dma.c
index c411363c60b..cdbc44f9a73 100644
--- a/arch/mips/jz4760/dma.c
+++ b/arch/mips/jz4760/dma.c
@@ -47,7 +47,7 @@
  */
 
 struct jz_dma_chan jz_dma_table[MAX_DMA_NUM] = {
-	{ dev_id: -1, },	/* DMAC0 channel 0, reserved for BCH */
+	{ dev_id: DMA_ID_MSC0, },	/* DMAC0 channel 0, reserved for MSC0 */
 	{ dev_id: -1, },		/* DMAC0 channel 1 */
 	{ dev_id: -1, },		/* DMAC0 channel 2 */
 	{ dev_id: -1, },		/* DMAC0 channel 3 */
@@ -57,8 +57,7 @@ struct jz_dma_chan jz_dma_table[MAX_DMA_NUM] = {
 	/* To avoid bug, reserved channel 6 & 7 for AIC_TX & AIC_RX */
 	{ dev_id: DMA_ID_AIC_TX, },	/* DMAC1 channel 0 */
 	{ dev_id: DMA_ID_AIC_RX, },	/* DMAC1 channel 1 */
-
-	{ dev_id: -1, },		/* DMAC1 channel 2 */
+	{ dev_id: DMA_ID_MSC1, },	/* DMAC1 channel 2, reserved for MSC1 */
 	{ dev_id: -1, },		/* DMAC1 channel 3 */
 	{ dev_id: -1, },		/* DMAC0 channel 4 */
 	{ dev_id: 0, },			/* DMAC0 channel 5 --- unavailable */
@@ -70,37 +69,46 @@ static const struct {
 	unsigned int dma_mode;
 	unsigned int dma_source;
 } dma_dev_table[DMA_ID_MAX] = {
-	{0, DMA_AUTOINIT, DMAC_DRSR_RS_AUTO},
+	[DMA_ID_AUTO] = {0, DMA_AUTOINIT, DMAC_DRSR_RS_AUTO},
 //	{CPHYSADDR(TSSI_FIFO), DMA_32BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_TSSIIN},
-	{CPHYSADDR(UART3_TDR), DMA_8BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_UART3OUT},
-	{CPHYSADDR(UART3_RDR), DMA_8BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_UART3IN},
-	{CPHYSADDR(UART2_TDR), DMA_8BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_UART2OUT},
-	{CPHYSADDR(UART2_RDR), DMA_8BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_UART2IN},
-	{CPHYSADDR(UART1_TDR), DMA_8BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_UART1OUT},
-	{CPHYSADDR(UART1_RDR), DMA_8BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_UART1IN},
-	{CPHYSADDR(UART0_TDR), DMA_8BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_UART0OUT},
-	{CPHYSADDR(UART0_RDR), DMA_8BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_UART0IN},
-	{CPHYSADDR(SSI_DR(0)), DMA_32BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_SSI0OUT},
-	{CPHYSADDR(SSI_DR(0)), DMA_32BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_SSI0IN},
+	[DMA_ID_UART3_TX] = {CPHYSADDR(UART3_TDR), DMA_8BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_UART3OUT},
+	[DMA_ID_UART3_RX] = {CPHYSADDR(UART3_RDR), DMA_8BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_UART3IN},
+	[DMA_ID_UART2_TX] = {CPHYSADDR(UART2_TDR), DMA_8BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_UART2OUT},
+	[DMA_ID_UART2_RX] = {CPHYSADDR(UART2_RDR), DMA_8BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_UART2IN},
+	[DMA_ID_UART1_TX] = {CPHYSADDR(UART1_TDR), DMA_8BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_UART1OUT},
+	[DMA_ID_UART1_RX] = {CPHYSADDR(UART1_RDR), DMA_8BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_UART1IN},
+	[DMA_ID_UART0_TX] = {CPHYSADDR(UART0_TDR), DMA_8BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_UART0OUT},
+	[DMA_ID_UART0_RX] = {CPHYSADDR(UART0_RDR), DMA_8BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_UART0IN},
+	[DMA_ID_SSI0_TX] = {CPHYSADDR(SSI_DR(0)), DMA_32BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_SSI0OUT},
+	[DMA_ID_SSI0_RX] = {CPHYSADDR(SSI_DR(0)), DMA_32BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_SSI0IN},
 
 	/*spdif used */
 	//{CPHYSADDR(SPDIF_FIFO), DMA_16BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_AICOUT},
 	/*aic unpack used*/
-	{CPHYSADDR(AIC_DR), DMA_AIC_TX_CMD_UNPACK | DMA_MODE_WRITE, DMAC_DRSR_RS_AICOUT},
+	[DMA_ID_AIC_TX] = {CPHYSADDR(AIC_DR), DMA_AIC_TX_CMD_UNPACK | DMA_MODE_WRITE, DMAC_DRSR_RS_AICOUT},
 	/*aic pack used*/
 	//{CPHYSADDR(AIC_DR), DMA_AIC_TX_CMD_PACK | DMA_MODE_WRITE, DMAC_DRSR_RS_AICOUT},
-	{CPHYSADDR(AIC_DR), DMA_32BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_AICIN},
-	{CPHYSADDR(MSC_TXFIFO(0)), DMA_32BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_MSC0OUT},
-	{CPHYSADDR(MSC_RXFIFO(0)), DMA_32BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_MSC0IN},
-	{0, DMA_AUTOINIT, DMAC_DRSR_RS_TCU},
-	{CPHYSADDR(SADC_ADTCH), DMA_32BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_SADC},/* Touch Screen Data Register */
-	{CPHYSADDR(MSC_TXFIFO(1)), DMA_32BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_MSC1OUT}, /* SSC1 TX */
-	{CPHYSADDR(MSC_RXFIFO(1)), DMA_32BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_MSC1IN},	/* SSC1 RX */
-	{CPHYSADDR(SSI_DR(1)), DMA_32BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_SSI1OUT},
-	{CPHYSADDR(SSI_DR(1)), DMA_32BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_SSI1IN},
-	{CPHYSADDR(PCM_PDP), DMA_16BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_PMOUT},
-	{CPHYSADDR(PCM_PDP), DMA_16BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_PMIN},
-	{},
+	[DMA_ID_AIC_RX] = {CPHYSADDR(AIC_DR), DMA_32BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_AICIN},
+	[DMA_ID_MSC0] = {0, 0, 0},
+	/* Just for compitable with SD8686 msc driver */
+	[DMA_ID_MSC0_TX] = {CPHYSADDR(MSC_TXFIFO(0)), DMA_32BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_MSC0OUT},
+	[DMA_ID_MSC0_RX] = {CPHYSADDR(MSC_RXFIFO(0)), DMA_32BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_MSC0IN},
+	[DMA_ID_TCU_OVERFLOW] = {0, DMA_AUTOINIT, DMAC_DRSR_RS_TCU},
+	[DMA_ID_SADC] = {CPHYSADDR(SADC_ADTCH), DMA_32BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_SADC},/* Touch Screen Data Register */
+	[DMA_ID_MSC1] = {0, 0, 0},
+	/* Just for compitable with SD8686 msc driver */
+	[DMA_ID_MSC1_TX] = {CPHYSADDR(MSC_TXFIFO(1)), DMA_32BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_MSC1OUT},
+	[DMA_ID_MSC1_RX] = {CPHYSADDR(MSC_RXFIFO(1)), DMA_32BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_MSC1IN},
+	[DMA_ID_MSC2] = {0, 0, 0},
+	/* Just for compitable with SD8686 msc driver */
+	[DMA_ID_MSC2_TX] = {CPHYSADDR(MSC_TXFIFO(2)), DMA_32BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_MSC2OUT},
+	[DMA_ID_MSC2_RX] = {CPHYSADDR(MSC_RXFIFO(2)), DMA_32BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_MSC2IN},
+	[DMA_ID_SSI1_TX] = {CPHYSADDR(SSI_DR(1)), DMA_32BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_SSI1OUT},
+	[DMA_ID_SSI1_RX] = {CPHYSADDR(SSI_DR(1)), DMA_32BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_SSI1IN},
+	[DMA_ID_PCM_TX] = {CPHYSADDR(PCM_PDP), DMA_16BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_PMOUT},
+	[DMA_ID_PCM_RX] = {CPHYSADDR(PCM_PDP), DMA_16BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_PMIN},
+	[DMA_ID_AX88796C_RX] = { 0, 0, 0 },
+	[DMA_ID_AX88796C_TX] = { 0, 0, 0 },
 };
 
 
@@ -201,9 +209,16 @@ int jz_request_dma(int dev_id, const char *dev_str,
 	if (dev_id < 0 || dev_id >= DMA_ID_MAX)
 		return -EINVAL;
 
- 	for (i = 0; i < MAX_DMA_NUM; i++) {
-		if (jz_dma_table[i].dev_id < 0)
-			break;
+	for (i = 0; i < MAX_DMA_NUM; i++) {
+		    if (jz_dma_table[i].dev_id == dev_id)
+			    break;
+	}
+
+	if (i == MAX_DMA_NUM) {
+		for (i = 0; i < MAX_DMA_NUM; i++) {
+			if (jz_dma_table[i].dev_id < 0)
+				break;
+		}
 	}
 	if (i == MAX_DMA_NUM)  /* no free channel */
 		return -ENODEV;
@@ -233,10 +248,17 @@ int jz_request_dma(int dev_id, const char *dev_str,
 	chan->mode = dma_dev_table[dev_id].dma_mode;
 	chan->source = dma_dev_table[dev_id].dma_source;
 
-	if (i < HALF_DMA_NUM)
-		REG_DMAC_DMACKE(0) = 1 << i;
-	else
-		REG_DMAC_DMACKE(1) = 1 << (i - HALF_DMA_NUM);
+	if (i < HALF_DMA_NUM) {
+		if (i == 0)
+			REG_DMAC_DMACKE(0) = 0x2;
+		else
+			REG_DMAC_DMACKE(0) = 1 << i;
+	} else {
+		if (i == HALF_DMA_NUM)
+			REG_DMAC_DMACKE(1) = 0x2;
+		else
+			REG_DMAC_DMACKE(1) = 1 << (i - HALF_DMA_NUM);
+	}
 
 	return i;
 }
@@ -827,6 +849,15 @@ void dma_desc_test(void)
 	jz_free_dma(dma_chan);
 }
 
+/*
+ * channel 0: read
+ * channel 1: write
+ * read and write are simutanously
+ */
+void dma_two_desc_test(void) {
+
+}
+
 #endif
 
 //EXPORT_SYMBOL_NOVERS(jz_dma_table);
diff --git a/arch/mips/jz4760/irq.c b/arch/mips/jz4760/irq.c
index 68db2a6a612..42a31113166 100644
--- a/arch/mips/jz4760/irq.c
+++ b/arch/mips/jz4760/irq.c
@@ -173,13 +173,17 @@ static void enable_dma_irq(unsigned int irq)
 
 static void disable_dma_irq(unsigned int irq)
 {
-	__dmac_channel_disable_irq(irq - IRQ_DMA_0);
+	int chan = irq - IRQ_DMA_0;
+	__dmac_disable_channel(chan);
+	__dmac_channel_disable_irq(chan);
 }
 
 static void mask_and_ack_dma_irq(unsigned int irq)
 {
 	unsigned int intc_irq;
 
+	disable_dma_irq(irq);
+
 	if ( irq < (IRQ_DMA_0 + HALF_DMA_NUM) ) 	/* DMAC Group 0 irq */
 		intc_irq = IRQ_DMAC0;
 	else if ( irq < (IRQ_DMA_0 + MAX_DMA_NUM) ) 	/* DMAC Group 1 irq */
@@ -189,8 +193,8 @@ static void mask_and_ack_dma_irq(unsigned int irq)
 		return ;
 	}
 	__intc_ack_irq(intc_irq);
-	__dmac_channel_ack_irq(irq-IRQ_DMA_0); /* needed?? add 20080506, Wolfgang */
-	__dmac_channel_disable_irq(irq - IRQ_DMA_0);
+	//__dmac_channel_ack_irq(irq-IRQ_DMA_0); /* needed?? add 20080506, Wolfgang */
+	//__dmac_channel_disable_irq(irq - IRQ_DMA_0);
 }
 
 static void end_dma_irq(unsigned int irq)
@@ -434,13 +438,22 @@ static int plat_real_irq(int irq)
 #endif
 	case IRQ_DMAC0:
 	case IRQ_DMAC1:
-		irq = __dmac_get_irq() + IRQ_DMA_0;
+		irq = __dmac_get_irq();
+		if (irq < 0)
+			return irq;
+		irq += IRQ_DMA_0;
 		break;
 	case IRQ_MDMA:
-		irq = __mdmac_get_irq() + IRQ_MDMA_0;
+		irq = __mdmac_get_irq();
+		if (irq < 0)
+			return irq;
+		irq += IRQ_MDMA_0;
 		break;
 	case IRQ_BDMA:
-		irq = __bdmac_get_irq() + IRQ_BDMA_0;
+		irq = __bdmac_get_irq();
+		if (irq < 0)
+			return irq;
+		irq += IRQ_BDMA_0;
 		break;
 	}
 
@@ -494,14 +507,15 @@ asmlinkage void plat_irq_dispatch(void)
 	if ((irq >= IRQ_GPIO5) && (irq <= IRQ_GPIO0)) {
 		group = IRQ_GPIO0 - irq;
 		irq = __gpio_group_irq(group);
-		if (irq < 0) {
-			return;
-		}
-
-		irq += IRQ_GPIO_0 + 32 * group;
+		if (irq >= 0)
+			irq += IRQ_GPIO_0 + 32 * group;
 	} else {
 		irq = plat_real_irq(irq);
 	}
 
+	/* WARN((irq < 0), "irq raised, but no irq pending\n"); */
+	if (irq < 0)
+		return;
+
 	do_IRQ(irq);
 }
diff --git a/arch/mips/jz4760/platform.c b/arch/mips/jz4760/platform.c
index 80f045e2d8f..ea9787bf3cf 100644
--- a/arch/mips/jz4760/platform.c
+++ b/arch/mips/jz4760/platform.c
@@ -20,8 +20,7 @@
 
 #include <asm/jzsoc.h>
 #include <linux/usb/musb.h>
-#include <../sound/oss/jz_audio.h>
-#include <asm/jzmmc/jz_mmc_platform_data.h>
+#include <linux/spi/spi.h>
 
 extern void __init board_msc_init(void);
 
@@ -92,7 +91,7 @@ static struct musb_hdrc_config jz_usb_otg_config = {
 	.soft_con	= 1,
 	.dma		= 1,
 /* Max EPs scanned. Driver will decide which EP can be used automatically. */
-	.num_eps	= 16,
+	.num_eps	= 6,
 };
 
 static struct musb_hdrc_platform_data jz_usb_otg_platform_data = {
@@ -133,106 +132,84 @@ static struct platform_device jz_usb_otg_device = {
 	.resource	= jz_usb_otg_resources,
 };
 
-/** MMC/SD controller MSC0**/
-static struct resource jz_msc0_resources[] = {
-	{
-		.start          = CPHYSADDR(MSC0_BASE),
-		.end            = CPHYSADDR(MSC0_BASE) + 0x1000 - 1,
-		.flags          = IORESOURCE_MEM,
-	},
-	{
-		.start          = IRQ_MSC0,
-		.end            = IRQ_MSC0,
-		.flags          = IORESOURCE_IRQ,
-	},
-	{
-		.start          = DMA_ID_MSC0_RX,
-		.end            = DMA_ID_MSC0_TX,
-		.flags          = IORESOURCE_DMA,
-	},
-};
-
-static u64 jz_msc0_dmamask =  ~(u32)0;
-
-static struct platform_device jz_msc0_device = {
-	.name = "jz-msc0",
-	.id = 0,
-	.dev = {
-		.dma_mask               = &jz_msc0_dmamask,
-		.coherent_dma_mask      = 0xffffffff,
-	},
-	.num_resources  = ARRAY_SIZE(jz_msc0_resources),
-	.resource       = jz_msc0_resources,
-};
-
-/** MMC/SD controller MSC1**/
-static struct resource jz_msc1_resources[] = {
-	{
-		.start          = CPHYSADDR(MSC1_BASE),
-		.end            = CPHYSADDR(MSC1_BASE) + 0x1000 - 1,
-		.flags          = IORESOURCE_MEM,
-	},
-	{
-		.start          = IRQ_MSC1,
-		.end            = IRQ_MSC1,
-		.flags          = IORESOURCE_IRQ,
-	},
-	{
-		.start          = DMA_ID_MSC1_RX,
-		.end            = DMA_ID_MSC1_TX,
-		.flags          = IORESOURCE_DMA,
-	},
-
-};
-
-static u64 jz_msc1_dmamask =  ~(u32)0;
-
-static struct platform_device jz_msc1_device = {
-	.name = "jz-msc1",
-	.id = 1,
-	.dev = {
-		.dma_mask               = &jz_msc1_dmamask,
-		.coherent_dma_mask      = 0xffffffff,
-	},
-	.num_resources  = ARRAY_SIZE(jz_msc1_resources),
-	.resource       = jz_msc1_resources,
-};
+/** MMC/SD/SDIO controllers**/
+#define __BUILD_JZ_MSC_PLATFORM_DEV(msc_id)				\
+	static struct resource jz_msc##msc_id##_resources[] = {		\
+		{							\
+			.start          = CPHYSADDR(MSC##msc_id##_BASE), \
+			.end            = CPHYSADDR(MSC##msc_id##_BASE) + 0x1000 - 1, \
+			.flags          = IORESOURCE_MEM,		\
+		},							\
+		{							\
+			.start          = IRQ_MSC##msc_id,		\
+			.end            = IRQ_MSC##msc_id,		\
+			.flags          = IORESOURCE_IRQ,		\
+		},							\
+		{							\
+			.start          = DMA_ID_MSC##msc_id,	\
+			.end            = DMA_ID_MSC##msc_id,	\
+			.flags          = IORESOURCE_DMA,		\
+		},							\
+	};								\
+									\
+	static u64 jz_msc##msc_id##_dmamask =  ~(u32)0;			\
+									\
+	static struct platform_device jz_msc##msc_id##_device = {	\
+		.name = "jz-msc",					\
+		.id = msc_id,						\
+		.dev = {						\
+			.dma_mask               = &jz_msc##msc_id##_dmamask, \
+			.coherent_dma_mask      = 0xffffffff,		\
+		},							\
+		.num_resources  = ARRAY_SIZE(jz_msc##msc_id##_resources), \
+		.resource       = jz_msc##msc_id##_resources,		\
+	};
+
+#ifdef CONFIG_JZ_MSC0
+__BUILD_JZ_MSC_PLATFORM_DEV(0)
+#endif
+#ifdef CONFIG_JZ_MSC1
+__BUILD_JZ_MSC_PLATFORM_DEV(1)
+#endif
+#ifdef CONFIG_JZ_MSC2
+__BUILD_JZ_MSC_PLATFORM_DEV(2)
+#endif
 
 static struct platform_device *jz_msc_devices[] __initdata = {
+#ifdef CONFIG_JZ_MSC0
 	&jz_msc0_device,
+#else
+	NULL,
+#endif
+#ifdef CONFIG_JZ_MSC1
 	&jz_msc1_device,
+#else
+	NULL,
+#endif
+#ifdef CONFIG_JZ_MSC2
+	&jz_msc2_device,
+#else
+	NULL,
+#endif
 };
 
-int __init jz_add_msc_devices(unsigned int controller, struct jz_mmc_platform_data *plat)
+int __init jz_add_msc_devices(unsigned int id, struct jz_mmc_platform_data *plat)
 {
 	struct platform_device	*pdev;
 
-	if (controller < 0 || controller > 1)
+	if (JZ_MSC_ID_INVALID(id))
 		return -EINVAL;
 
-	pdev = jz_msc_devices[controller];
+	pdev = jz_msc_devices[id];
+	if (NULL == pdev) {
+		return -EINVAL;
+	}
 
 	pdev->dev.platform_data = plat;
 
 	return platform_device_register(pdev);
 }
 
-
-/* + Sound device */
-
-#define SND(num, desc) { .name = desc, .id = num }
-static struct snd_endpoint snd_endpoints_list[] = {
-	SND(0, "HANDSET"),
-	SND(1, "SPEAKER"),
-	SND(2, "HEADSET"),
-};
-#undef SND
-
-static struct jz_snd_endpoints vogue_snd_endpoints = {
-	.endpoints = snd_endpoints_list,
-	.num = ARRAY_SIZE(snd_endpoints_list),
-};
-
 static struct platform_device vogue_snd_device = {
 	.name = "mixer",
 	.id = -1,
@@ -241,8 +218,6 @@ static struct platform_device vogue_snd_device = {
 	},
 };
 
-/* - Sound device */
-
 static struct resource jz_i2c0_resources[] = {
 	[0] = {
 		.start          = CPHYSADDR(I2C0_BASE),
@@ -297,6 +272,131 @@ static struct platform_device rtc_device = {
 	.name		= "jz4760-rtc",
 	.id		= -1,
 };
+///////////////////////////////////
+/* SSI controller --- SPI (0) */
+#ifndef CONFIG_JZ_SPI_BOARD_INFO_REGISTER
+#define __jz_spi0_board_info 	NULL
+#define __jz_spi1_board_info 	NULL
+#else
+extern struct spi_board_info jz4760_spi0_board_info[];
+extern struct spi_board_info jz4760_spi1_board_info[];
+#define __jz_spi0_board_info 	&jz4760_spi0_board_info[0]
+#define __jz_spi1_board_info 	&jz4760_spi1_board_info[0]
+#endif
+
+/** AX88796C controller **/
+static struct resource ax88796c_resources[] = {
+	[0] = {
+		.start          = CPHYSADDR(0xb4000000),
+		.end            = CPHYSADDR(0xb4000000) + 0x6800 - 1,
+		.flags          = IORESOURCE_MEM,
+	},
+	[1] = {
+		.start          = GPIO_NET_INT + IRQ_GPIO_0,
+		.end            = GPIO_NET_INT + IRQ_GPIO_0,
+		.flags          = IORESOURCE_IRQ,
+	}
+};
+
+static u64 ax88796c_dmamask =  ~(u32)0;
+
+static struct platform_device ax88796c_dev = {
+	.name = "ax88796c",
+	.id = 0,
+	.dev = {
+		.dma_mask               = &ax88796c_dmamask,
+		.coherent_dma_mask      = 0xffffffff,
+	},
+	.num_resources  = ARRAY_SIZE(ax88796c_resources),
+	.resource       = ax88796c_resources,
+};
+
+struct jz47xx_spi_info spi0_info_cfg = {
+	.chnl = 0,
+	.bus_num = 0,
+	.is_pllclk = 1,
+	.board_size = 2,				/* spi¨¦¨¨¡À?¨ºy??*/
+#ifdef CONFIG_JZ_SPI_BOARD_INFO_REGISTER
+	.board_info = __jz_spi0_board_info,
+#else
+	.board_info = NULL,
+#endif
+//	.set_cs = spi_gpio_cs,
+	.set_cs = NULL,
+	.pin_cs ={
+		PIN_SSI_CE0,
+//		32*2+31,				/*apus: GPC31 --- SW6 --- BOOT_SEL1 (dummy, example) */
+		32*4+16,				/*lepus: TP56 */
+	},
+};
+static struct resource jz_spi0_resource[] = {
+	[0] = {
+		.start          = CPHYSADDR(SSI0_BASE),
+		.end            = CPHYSADDR(SSI0_BASE) + 0x2000 - 1,
+		.flags 			= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start = IRQ_SSI0,
+		.end   = IRQ_SSI0,
+		.flags = IORESOURCE_IRQ,
+	}
+};
+static u64 jz_spi0_dmamask =  ~(u32)0;
+
+struct platform_device jz_spi0_device = {
+	.name		  = "jz47xx-spi0",
+	.id		  = 0,
+	.num_resources	  = ARRAY_SIZE(jz_spi0_resource),
+	.resource	  = jz_spi0_resource,
+        .dev              = {
+                .dma_mask = &jz_spi0_dmamask,
+                .coherent_dma_mask = 0xffffffffUL,
+                .platform_data = & spi0_info_cfg,
+        }
+};
+
+/* SSI controller --- SPI (1) */
+struct jz47xx_spi_info spi1_info_cfg = {
+	.chnl = 1,
+	.bus_num = 1,
+	.board_size = 1,
+#ifdef CONFIG_JZ_SPI_BOARD_INFO_REGISTER
+	.board_info = __jz_spi1_board_info,
+#else
+	.board_info = NULL,
+#endif
+//	.set_cs = spi_gpio_cs,
+	.set_cs = NULL,
+	.pins_config = NULL,
+	.pin_cs ={
+		PIN_SSI_CE0,
+	},
+};
+static struct resource jz_spi1_resource[] = {
+	[0] = {
+		.start          = CPHYSADDR(SSI1_BASE) + 0x2000,
+		.end            = CPHYSADDR(SSI1_BASE) + 0x4000 - 1,
+		.flags 			= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start = IRQ_SSI1,
+		.end   = IRQ_SSI1,
+		.flags = IORESOURCE_IRQ,
+	}
+};
+static u64 jz_spi1_dmamask =  ~(u32)0;
+
+struct platform_device jz_spi1_device = {
+	.name		  = "jz47xx-spi1",
+	.id		  = 1,
+	.num_resources	  = ARRAY_SIZE(jz_spi1_resource),
+	.resource	  = jz_spi1_resource,
+        .dev              = {
+                .dma_mask = &jz_spi1_dmamask,
+                .coherent_dma_mask = 0xffffffffUL,
+                .platform_data = & spi1_info_cfg,
+        }
+};
 
 /* All */
 static struct platform_device *jz_platform_devices[] __initdata = {
@@ -310,14 +410,21 @@ static struct platform_device *jz_platform_devices[] __initdata = {
 	// &jz_msc0_device,
 	// &jz_msc1_device,
 	&rtc_device,
+	&jz_spi0_device,
+	&jz_spi1_device,
+	&ax88796c_dev,
 };
 
 extern void __init board_i2c_init(void);
+extern void __init board_spi_init(void);
 static int __init jz_platform_init(void)
 {
 	int ret = 0;
 
 	board_i2c_init();
+#ifndef CONFIG_JZ_SPI_BOARD_INFO_REGISTER
+	board_spi_init();
+#endif
 
 	ret = platform_add_devices(jz_platform_devices, ARRAY_SIZE(jz_platform_devices));
 #ifdef CONFIG_ANDROID_PMEM
@@ -330,3 +437,4 @@ static int __init jz_platform_init(void)
 }
 
 arch_initcall(jz_platform_init);
+
diff --git a/arch/mips/jz4760/pm.c b/arch/mips/jz4760/pm.c
index 34334f9b382..d8024e1968a 100644
--- a/arch/mips/jz4760/pm.c
+++ b/arch/mips/jz4760/pm.c
@@ -31,7 +31,11 @@
 #include <asm/cacheops.h>
 #include <asm/jzsoc.h>
 
+#ifndef CONFIG_JZ_SYSTEM_AT_CARD
 #define CONFIG_PM_POWERDOWN_P0 y
+#else
+#undef CONFIG_PM_POWERDOWN_P0
+#endif
 #define JZ_PM_SIMULATE_BATTERY y
 
 #ifdef JZ_PM_SIMULATE_BATTERY
@@ -177,9 +181,9 @@ static int jz_pm_do_sleep(void)
 	unsigned long sleep_gpio_save[7*(GPIO_PORT_NUM-1)];
 	unsigned long cpuflags;
 
+#if defined(CONFIG_RTC_JZ4760) && defined(CONFIG_BATTERY_JZ)
 	jz_save_alarm();
 
-#if defined(CONFIG_RTC_JZ4760) && defined(CONFIG_BATTERY_JZ)
  __jz_pm_do_sleep_start:
 #endif
  	/* set SLEEP mode */
@@ -336,7 +340,9 @@ static int jz_pm_do_sleep(void)
 	}
 #endif
 
+#if defined(CONFIG_RTC_JZ4760) && defined(CONFIG_BATTERY_JZ)
 	jz_restore_alarm();
+#endif
 
 	return 0;
 }
diff --git a/arch/mips/jz4760/proc.c b/arch/mips/jz4760/proc.c
index 34c56f12b22..adf121a6d1f 100644
--- a/arch/mips/jz4760/proc.c
+++ b/arch/mips/jz4760/proc.c
@@ -192,6 +192,7 @@ static int cgm_read_proc (char *page, char **start, off_t off,
 			div[__cpm_get_pdiv()]
 		);
 	len += sprintf (page+len, "PLL Freq        : %3d.%02d MHz\n", TO_MHZ(cpm_get_pllout()));
+	len += sprintf (page+len, "PLL1 Freq	   : %3d.%02d MHZ\n", TO_MHZ(cpm_get_pllout1()));
 	len += sprintf (page+len, "CCLK            : %3d.%02d MHz\n", TO_MHZ(cpm_get_clock(CGU_CCLK)));
 	len += sprintf (page+len, "HCLK            : %3d.%02d MHz\n", TO_MHZ(cpm_get_clock(CGU_HCLK)));
 	len += sprintf (page+len, "MCLK            : %3d.%02d MHz\n", TO_MHZ(cpm_get_clock(CGU_MCLK)));
@@ -1006,7 +1007,7 @@ static int imem1_write_proc(struct file *file, const char *buffer, unsigned long
 	} else if ((val >= 0) && (val <= IMEM1_MAX_ORDER)) {
 		/* allocate 2^val pages */
 		imem1_alloc(val);
-	} else {			
+	} else {
 		/* free buffer which phys_addr is val */
 		imem_free(val);
 	}
@@ -1028,6 +1029,46 @@ static int fpu_write_proc(struct file *file, const char *buffer, unsigned long c
 	return count;
 }
 
+static int idle_write_proc(struct file *file, const char *buffer, unsigned long count, void *data)
+{
+	unsigned long icmr0 = INREG32(INTC_ICMR(0));
+	unsigned long icmr1 = INREG32(INTC_ICMR(1));
+	unsigned long cpuflags;
+
+	printk("===>enter idle\n");
+	local_irq_save(cpuflags);
+
+	/* Mask all interrupts*/
+	OUTREG32(INTC_ICMSR(0), 0xffffffff);
+	OUTREG32(INTC_ICMSR(1), 0x7ff);
+
+	CMSREG32(CPM_LCR, LCR_LPM_IDLE, LCR_LPM_MASK);
+	__gpio_as_irq_fall_edge(GPIO_POWER_ON);
+	__gpio_ack_irq(GPIO_POWER_ON);
+	__gpio_unmask_irq(GPIO_POWER_ON);
+	__intc_unmask_irq(IRQ_GPIO0 - (GPIO_POWER_ON/32));
+
+	__asm__(".set\tmips3\n\t"
+		"sync\n\t"
+		"wait\n\t"
+		"nop\n\t"
+		"nop\n\t"
+		"nop\n\t"
+		"nop\n\t"
+		".set\tmips0");
+
+	printk("===>leave idle\n");
+
+	OUTREG32(INTC_ICMR(0), icmr0);
+	OUTREG32(INTC_ICMR(1), icmr1);
+
+	local_irq_restore(cpuflags);
+	CLRREG32(CPM_RSR, RSR_PR | RSR_WR | RSR_P0R);
+
+	return count;
+}
+
+
 /*
  * /proc/jz/xxx entry
  *
@@ -1149,7 +1190,7 @@ static int __init jz_proc_init(void)
 
                 printk("Total %dMB memory1 at 0x%x was reserved for IPU\n",
                        (unsigned int)((1 << IMEM1_MAX_ORDER) * PAGE_SIZE)/1000000, jz_imem1_base);
-        } 
+        }
         else
            printk("NOT enough memory for imem1\n");
 
@@ -1163,6 +1204,13 @@ static int __init jz_proc_init(void)
 		res->data = NULL;
 	}
 
+	res = create_proc_entry("idle", 0644, proc_jz_root);
+	if (res) {
+		res->read_proc = NULL;
+		res->write_proc = idle_write_proc;
+		res->data = NULL;
+	}
+
 	return 0;
 }
 
diff --git a/arch/mips/jz4760/prom.c b/arch/mips/jz4760/prom.c
index f30a77b8c77..f7935462b7d 100644
--- a/arch/mips/jz4760/prom.c
+++ b/arch/mips/jz4760/prom.c
@@ -179,8 +179,11 @@ void __init prom_init(void)
 /* used by early printk */
 void prom_putchar(char c)
 {
-	volatile u8 *uart_lsr = (volatile u8 *)(UART1_BASE + OFF_LSR);
-	volatile u8 *uart_tdr = (volatile u8 *)(UART1_BASE + OFF_TDR);
+#ifndef JZ_EARLY_UART_BASE
+#error "please define JZ_EARLY_UART_BASE for your board!"
+#endif
+	volatile u8 *uart_lsr = (volatile u8 *)(JZ_EARLY_UART_BASE + OFF_LSR);
+	volatile u8 *uart_tdr = (volatile u8 *)(JZ_EARLY_UART_BASE + OFF_TDR);
 
 	/* Wait for fifo to shift out some bytes */
 	while ( !((*uart_lsr & (UARTLSR_TDRQ | UARTLSR_TEMT)) == 0x60) );
diff --git a/arch/mips/jz4760/reset.c b/arch/mips/jz4760/reset.c
index b2bc72e7cac..a4523eff3e4 100644
--- a/arch/mips/jz4760/reset.c
+++ b/arch/mips/jz4760/reset.c
@@ -19,10 +19,19 @@
 #include <asm/system.h>
 #include <asm/jzsoc.h>
 
+#define RECOVERY_SIGNATURE	0x52454359	/* means "RECOVERY" */
 void jz_restart(char *command)
 {
 #if 1
 	printk("Restarting after 4ms\n");
+#if defined(CONFIG_JZ_RECOVERY_SUPPORT)
+	if ((command != NULL) && !strcmp(command, "recovery")) {
+		printk("After restart will goto REVCOVERY mode!");
+		cpm_set_scrpad(RECOVERY_SIGNATURE);
+	} else {
+		cpm_set_scrpad(0);
+	}
+#endif
 
 	REG_WDT_WCSR = WCSR_PRESCALE4 | WCSR_CLKIN_EXT;
 	REG_WDT_WCNT = 0;
diff --git a/arch/mips/jz4760/time.c b/arch/mips/jz4760/time.c
index 86ff7af848d..6688363eec8 100644
--- a/arch/mips/jz4760/time.c
+++ b/arch/mips/jz4760/time.c
@@ -1,8 +1,8 @@
 /*
  * linux/arch/mips/jz4760/time.c
- * 
+ *
  * Setting up the clock on the JZ4760 boards.
- * 
+ *
  * Copyright (C) 2008 Ingenic Semiconductor Inc.
  * Author: <jlwei@ingenic.cn>
  *
@@ -68,7 +68,7 @@ union clycle_type
 	unsigned int cycle32[2];
 };
 
-cycle_t jz_get_cycles(void)
+cycle_t jz_get_cycles(struct clocksource *unused)
 {
 	/* convert jiffes to jz timer cycles */
 	unsigned int ostcount;
@@ -76,13 +76,13 @@ cycle_t jz_get_cycles(void)
 	unsigned int current_cycle;
 	unsigned int flag;
 	union clycle_type old_cycle;
-	
+
 	local_irq_save(cpuflags);
 	current_cycle = current_cycle_high;
 	ostcount = REG_OST_OSTCNT;
 	flag = (REG_TCU_TFR & TFCR_OSTFLAG) ? 1: 0;
 	if(flag)
-		ostcount = REG_OST_OSTCNT;	  
+		ostcount = REG_OST_OSTCNT;
 	local_irq_restore(cpuflags);
 
 	old_cycle.cycle32[0] = ostcount;
@@ -195,8 +195,8 @@ static void __init jz_timer_setup(void)
 	__tcu_stop_counter(JZ_TIMER_TCU_CH);
 //	__cpm_start_tcu();
 	latch = (JZ_TIMER_CLOCK + (HZ>>1)) / HZ;
-	
-	REG_TCU_TMSR = ((1 << JZ_TIMER_TCU_CH) | (1 << (JZ_TIMER_TCU_CH + 16))); 
+
+	REG_TCU_TMSR = ((1 << JZ_TIMER_TCU_CH) | (1 << (JZ_TIMER_TCU_CH + 16)));
 
 	REG_TCU_TCSR(JZ_TIMER_TCU_CH) = TCSR_PRESCALE16 | TCSR_EXT_EN;
 	REG_TCU_TDFR(JZ_TIMER_TCU_CH) = latch - 1;
diff --git a/arch/mips/jz4760b/Makefile b/arch/mips/jz4760b/Makefile
new file mode 100644
index 00000000000..0a0b8f4050c
--- /dev/null
+++ b/arch/mips/jz4760b/Makefile
@@ -0,0 +1,32 @@
+#
+# Makefile for the Ingenic JZ4760.
+#
+
+# Object file lists.
+
+obj-y += prom.o irq.o time.o reset.o setup.o dma.o \
+	platform.o cpm.o proc.o #i2c.o
+
+obj-$(CONFIG_PROC_FS)		+= proc.o
+
+# board specific support
+obj-$(CONFIG_JZ4760_ALTAIR)	+= board-altair.o
+obj-$(CONFIG_JZ4760_CYGNUS)	+= board-cygnus.o
+obj-$(CONFIG_JZ4760B_CYGNUS)	+= board-cygnus.o
+obj-$(CONFIG_JZ4760_LEPUS)	+= board-lepus.o
+obj-$(CONFIG_JZ4760B_LEPUS)	+= board-lepus.o
+
+obj-$(CONFIG_JZ4760_F4760)	+= board-f4760.o
+obj-$(CONFIG_SOC_JZ4760B)        += fpu.o
+
+# PM support
+
+obj-$(CONFIG_PM)         += pm.o sleep.o
+
+# CPU Frequency scaling support
+
+obj-$(CONFIG_CPU_FREQ_JZ)       += cpufreq.o
+
+#obj-$(CONFIG_JZ4760_ALTAIR)	+= gpiolib.o
+#obj-$(CONFIG_JZ4760B_CYGNUS)	+= gpiolib.o
+
diff --git a/arch/mips/jz4760b/board-altair.c b/arch/mips/jz4760b/board-altair.c
new file mode 100644
index 00000000000..8c94310cf28
--- /dev/null
+++ b/arch/mips/jz4760b/board-altair.c
@@ -0,0 +1,557 @@
+/*
+ * linux/arch/mips/jz4760b/board-altair.c
+ *
+ * JZ4760B Altair board setup routines.
+ *
+ * Copyright (c) 2006-2010  Ingenic Semiconductor Inc.
+ *
+ * Author: Jason<xwang@ingenic>
+ *		Based on board-cygnus.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/ioport.h>
+#include <linux/mm.h>
+#include <linux/console.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/device.h>
+#include <linux/i2c.h>
+#include <linux/i2c-gpio.h>
+
+#include <asm/cpu.h>
+#include <asm/bootinfo.h>
+#include <asm/mipsregs.h>
+#include <asm/reboot.h>
+
+/*
+#include <linux/mfd/wm831x/core.h>
+#include <linux/mfd/wm831x/auxadc.h>
+#include <linux/mfd/wm831x/pdata.h>
+#include <linux/mfd/wm831x/irq.h>
+#include <linux/mfd/wm831x/watchdog.h>
+#include <linux/mfd/wm831x/status.h>
+*/
+#include <linux/regulator/machine.h>
+#include <linux/regulator/driver.h>
+//#include <linux/timed_gpio.h>
+
+#include <asm/jzsoc.h>
+//#include <asm/jzmmc/jz_mmc_platform_data.h>
+
+#define WM831X_LDO_MAX_NAME 6
+
+void __init board_msc_init(void);
+
+//extern int jz_add_msc_devices(unsigned int controller, struct jz_mmc_platform_data *plat);
+extern void (*jz_timer_callback)(void);
+
+#if 0
+static void dancing(void)
+{
+	static unsigned char slash[] = "\\|/-";
+//	static volatile unsigned char *p = (unsigned char *)0xb6000058;
+	static volatile unsigned char *p = (unsigned char *)0xb6000016;
+	static unsigned int count = 0;
+	*p = slash[count++];
+	count &= 3;
+}
+#endif
+
+/* MSC SETUP */
+/*
+static void altair_sdio_gpio_init(struct device *dev)
+{
+	__gpio_as_msc0_4bit();
+
+	// BT/WLAN reset
+	__gpio_as_output(17); //GPA17
+	__gpio_clear_pin(17);
+	mdelay(10);
+	__gpio_as_input(17);
+}
+
+static void altair_sdio_power_on(struct device *dev)
+{
+	__msc0_enable_power();
+}
+
+static void altair_sdio_power_off(struct device *dev)
+{
+	__msc0_disable_power();
+}
+
+static unsigned int altair_sdio_status(struct device *dev)
+{
+	unsigned int status;
+
+	// WIFI virtual 'card detect' status
+	status = 1;
+	return (status);
+}
+
+static struct jz_mmc_platform_data altair_sdio_data = {
+	.support_sdio   = 1,
+	.ocr_mask	= MMC_VDD_32_33 | MMC_VDD_33_34,
+	.init           = altair_sdio_gpio_init,
+	.power_on       = altair_sdio_power_on,
+	.power_off      = altair_sdio_power_off,
+	.status		= altair_sdio_status,
+	.max_bus_width  = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | MMC_CAP_8_BIT_DATA,
+#ifdef CONFIG_JZ_MSC0_BUS_1
+	.bus_width      = 1,
+#elif defined  CONFIG_JZ_MSC0_BUS_4
+	.bus_width      = 4,
+#else
+	.bus_width      = 8,
+#endif
+};
+
+static void altair_tf_gpio_init(struct device *dev)
+{
+	__gpio_as_msc1_4bit();
+	__gpio_as_output(GPIO_SD1_VCC_EN_N);
+}
+
+static void altair_tf_power_on(struct device *dev)
+{
+	__msc1_enable_power();
+}
+
+static void altair_tf_power_off(struct device *dev)
+{
+	__msc1_disable_power();
+}
+
+static unsigned int altair_tf_status(struct device *dev)
+{
+	unsigned int status;
+
+	status = (unsigned int) __gpio_get_pin(GPIO_SD1_CD_N);
+	return (status);
+}
+
+static void altair_tf_plug_change(int state)
+{
+	if(state == CARD_INSERTED)
+		__gpio_as_irq_low_level(MSC1_HOTPLUG_PIN);
+	else
+		__gpio_as_irq_high_level(MSC1_HOTPLUG_PIN);
+}
+
+static struct jz_mmc_platform_data altair_tf_data = {
+#ifndef CONFIG_JZ_MSC1_SDIO_SUPPORT
+	.support_sdio   = 0,
+#else
+	.support_sdio   = 1,
+#endif
+	.ocr_mask	= MMC_VDD_32_33 | MMC_VDD_33_34,
+	.status_irq	= MSC1_HOTPLUG_IRQ,
+	.detect_pin     = GPIO_SD1_CD_N,
+	.init           = altair_tf_gpio_init,
+	.power_on       = altair_tf_power_on,
+	.power_off      = altair_tf_power_off,
+	.status		= altair_tf_status,
+	.plug_change	= altair_tf_plug_change,
+	.max_bus_width  = MMC_CAP_SD_HIGHSPEED | MMC_CAP_4_BIT_DATA,
+#ifdef CONFIG_JZ_MSC1_BUS_1
+	.bus_width      = 1,
+#else
+	.bus_width      = 4,
+#endif
+};
+
+void __init board_msc_init(void)
+{
+#ifdef CONFIG_JZ_MSC0
+	jz_add_msc_devices(0, &altair_sdio_data);
+#endif
+
+#ifdef CONFIG_JZ_MSC1
+	jz_add_msc_devices(1, &altair_tf_data);
+#endif
+}
+
+*/
+
+static void f4760b_timer_callback(void)
+{
+	static unsigned long count = 0;
+
+	if ((++count) % 50 == 0) {
+//		dancing();
+		count = 0;
+	}
+}
+
+static void __init board_cpm_setup(void)
+{
+	/* Stop unused module clocks here.
+	 * We have started all module clocks at arch/mips/jz4760b/setup.c.
+	 */
+}
+
+static void __init board_gpio_setup(void)
+{
+        __jtag_as_uart3(); /* for GSM modem IW368 */
+}
+
+void __init jz_board_setup(void)
+{
+	printk("JZ4760B Altair board setup\n");
+//	jz_restart(NULL);
+	board_cpm_setup();
+	board_gpio_setup();
+
+	jz_timer_callback = f4760b_timer_callback;
+}
+
+/**
+ * Called by arch/mips/kernel/proc.c when 'cat /proc/cpuinfo'.
+ * Android requires the 'Hardware:' field in cpuinfo to setup the init.%hardware%.rc.
+ */
+const char *get_board_type(void)
+{
+	return "Altair";
+}
+
+/*****
+ * Wm831x init
+ *****/
+
+/*
+struct wm831x_ldo {
+	char name[WM831X_LDO_MAX_NAME];
+	struct regulator_desc desc;
+	int base;
+	struct wm831x *wm831x;
+	struct regulator_dev *regulator;
+};
+
+static int wm8310_pre_init(struct wm831x *wm831x){
+	//close all wm831x regulator .
+	int ret;
+
+	ret = wm831x_set_bits(wm831x,WM831X_LDO_ENABLE,0x7ff,0);
+	if (ret != 0)
+		dev_err(wm831x->dev, "Failed to close all ldo: %d\n",ret);
+
+	return 0;
+}
+
+static int wm8310_post_init(struct wm831x *wm831x){
+
+	int ret;
+
+	ret = wm831x_reg_unlock(wm831x);
+	if (ret != 0) {
+		dev_err(wm831x->dev, "Failed to unlock registers: %d\n", ret);
+		return -1;
+	}
+
+	// close wm831x watchdog
+	ret = wm831x_set_bits(wm831x,WM831X_WATCHDOG,WM831X_WDOG_ENA,0);
+	if (ret != 0)
+		dev_err(wm831x->dev, "Failed to close watchdog: %d\n",ret);
+
+	// set ON pin timeout period and set secondary action as irq
+
+	ret = wm831x_set_bits(wm831x,WM831X_ON_PIN_CONTROL,
+			      WM831X_ON_PIN_SECACT_MASK  |
+			      WM831X_ON_PIN_PRIMACT_MASK |
+			      WM831X_ON_PIN_TO_MASK,
+			      WM831X_ON_PIN_AS_IRQ );
+	if (ret != 0)
+		dev_err(wm831x->dev, "Failed to set ON pin timeout period: %d\n",ret);
+
+	wm831x_reg_lock(wm831x);
+	//set wm831x LED1 as a flag of charge status
+	ret = wm831x_set_bits(wm831x,WM831X_STATUS_LED_1,WM831X_LED1_MASK,
+			      WM831X_LED1_CHARGE_STATE);
+	if (ret != 0)
+		dev_err(wm831x->dev, "Failed to set status of charge on led1: %d\n",ret);
+
+	return 0;
+}
+
+struct wm831x_backlight_pdata wm8310_backlight = {
+
+	.isink     = 1,
+	.max_uA   = 3000,
+};
+static struct wm831x_battery_pdata wm8310_battery_data={
+
+	.enable        = 1,
+	.fast_enable   = 1,
+	.off_mask      = 0,
+	.trickle_ilim  = 50,
+	.vsel          = 4200,
+	.eoc_iterm     = 50,
+	.fast_ilim     = 400,
+	.timeout       = 300,
+};
+
+struct wm831x_status_pdata wm8310_led_status[] = {
+	{
+		.default_src = WM831X_STATUS_CHARGER,
+		.name        = "wm831x-status",
+	},
+};
+
+static struct regulator_init_data wm8310_dcdc[]={
+	{
+		.constraints = {
+			.name    = "wm831x-dcdc1",
+//			.boot_on = 0,
+		},
+	},
+	{
+		.constraints = {
+			.name    = "wm831x-dcdc2",
+//			.boot_on = 1,
+		},
+
+	},
+       	{
+		.constraints = {
+			.name    = "wm831x-dcdc3",
+//			.boot_on = 1,
+		},
+	},
+	{
+		.constraints = {
+			.name    = "wm831x-dcdc4",
+//			.boot_on = 1,
+		},
+	},
+};
+
+static int wm8310_ldo1_init( void *driver_data )
+{
+	return 0;
+}
+struct wm831x_ldo ldo1_driver_data = {
+	.base = WM831X_LDO1_CONTROL,
+};
+
+static struct regulator_init_data wm8310_ldo[]={
+	{
+		.constraints = {
+			.name     = "wm831x-ldo1",
+			.apply_uV = 1,
+			.min_uV   = 3300000,
+			.max_uV   = 3300000,
+			.boot_on  = 0,
+		},
+		.regulator_init  = &wm8310_ldo1_init,
+	},
+	{
+		.constraints = {
+			.name = "wm831x-ldo2",
+			.apply_uV = 1,
+			.min_uV   = 1500000,
+			.max_uV   = 1500000,
+			.boot_on = 0,
+		},
+
+	},
+       	{
+		.constraints = {
+			.name    = "wm831x-ldo3",
+			.apply_uV = 1,
+			.min_uV   = 3300000,
+			.max_uV   = 3300000,
+			.boot_on = 1,
+		},
+	},
+	{
+		.constraints = {
+			.name = "wm831x-ldo4",
+			.apply_uV = 1,
+			.min_uV   = 3300000,
+			.max_uV   = 3300000,
+			.boot_on = 0,
+		},
+
+	},
+	{
+		.constraints = {
+			.name    = "wm831x-ldo5",
+			.apply_uV = 1,
+			.min_uV   = 3300000,
+			.max_uV   = 3300000,
+			.boot_on = 0,
+		},
+	},
+	{
+		.constraints = {
+			.name = "wm831x-ldo6",
+			.apply_uV = 1,
+			.min_uV   = 3300000,
+			.max_uV   = 3300000,
+			.boot_on = 0,
+		},
+
+	},
+       	{
+		.constraints = {
+			.name    = "wm831x-ldo7",
+			.apply_uV = 1,
+			.min_uV   = 1200000,
+			.max_uV   = 1200000,
+			.boot_on = 0,
+		},
+	},
+	{
+		.constraints = {
+			.name = "wm831x-ldo8",
+			.apply_uV = 1,
+			.min_uV   = 1800000,
+			.max_uV   = 1800000,
+			.boot_on = 0,
+		},
+
+	},
+		{
+		.constraints = {
+			.name    = "wm831x-ldo9",
+			.apply_uV = 1,
+			.min_uV   = 2800000,
+			.max_uV   = 2800000,
+			.boot_on = 0,
+		},
+	},
+	{
+		.constraints = {
+			.name = "wm831x-ldo10",
+			.apply_uV = 1,
+			.min_uV   = 2800000,
+			.max_uV   = 2800000,
+			.boot_on = 0,
+		},
+
+	},
+	{
+		.constraints = {
+			.name = "wm831x-ldo11",
+			.boot_on = 0,
+		},
+
+	},
+
+};
+
+static struct wm831x_pdata wm831x_platform_data = {
+	.pre_init  = &wm8310_pre_init,
+	.post_init = &wm8310_post_init,
+	.backlight = &wm8310_backlight,
+	.battery   = &wm8310_battery_data,
+	.dcdc      = { wm8310_dcdc, wm8310_dcdc+1, wm8310_dcdc+2, wm8310_dcdc+3 },
+	.ldo       = {
+			wm8310_ldo,  wm8310_ldo+1,wm8310_ldo+2,wm8310_ldo+3,
+			wm8310_ldo+4,wm8310_ldo+5,wm8310_ldo+6,wm8310_ldo+7,
+			wm8310_ldo+8,wm8310_ldo+9,wm8310_ldo+10
+	},
+};
+
+static struct i2c_board_info wm831x_i2c_devs[] __initdata = {
+	{
+		I2C_BOARD_INFO("wm8310", 0x34),
+		.irq = GPIO_WM831x_DETECT + IRQ_GPIO_0,
+		.platform_data = &wm831x_platform_data,
+	},
+};
+*/
+
+static struct i2c_board_info altair_i2c0_devs[] __initdata = {
+	{
+		I2C_BOARD_INFO("ov3640", 0x3c),
+	},
+	{
+	},
+};
+
+static struct i2c_board_info altair_i2c1_devs[] __initdata = {
+	{
+		I2C_BOARD_INFO("jz_mt4d_ts", 0x40),
+		.irq = LCD_INT_IRQ,
+	},
+	{
+	},
+};
+
+static struct i2c_board_info altair_gpio_i2c_devs[] __initdata = {
+#if 0
+	{
+		I2C_BOARD_INFO("jz_mt4d_ts", 0x40),
+		.irq = LCD_INT_IRQ,
+	},
+#endif
+	{
+	},
+};
+
+static struct i2c_gpio_platform_data altair_i2c_gpio_data = {
+	.sda_pin	= CIM_I2C_SDA,
+	.scl_pin	= CIM_I2C_SCK,
+};
+
+static struct platform_device altair_i2c_gpio_device = {
+	.name	= "i2c-gpio",
+	.id	= 2,
+	.dev	= {
+		.platform_data = &altair_i2c_gpio_data,
+	},
+};
+
+/*
+struct timed_gpio vibrator_timed_gpio = {
+		.name         = "vibrator",
+//		.gpio         = GPIO_VIBRATOR_EN_N,
+		.active_low   = 1,
+		.max_timeout  = 15000,
+};
+
+static struct timed_gpio_platform_data vibrator_platform_data = {
+	.num_gpios    = 1,
+	.gpios        = &vibrator_timed_gpio,
+};
+
+static struct platform_device altair_timed_gpio_device = {
+	.name = TIMED_GPIO_NAME,
+	.id = 0,
+	.dev = {
+		.platform_data          = &vibrator_platform_data,
+	},
+
+};
+
+static struct platform_device *altair_platform_devices[] __initdata = {
+	&altair_timed_gpio_device,
+	&altair_i2c_gpio_device,
+};
+*/
+
+static int __init altair_board_init( void )
+{
+//	i2c_register_board_info(1, wm831x_i2c_devs, ARRAY_SIZE(wm831x_i2c_devs));
+	i2c_register_board_info(0, altair_i2c0_devs, ARRAY_SIZE(altair_i2c0_devs));
+	i2c_register_board_info(1, altair_i2c1_devs, ARRAY_SIZE(altair_i2c1_devs));
+	i2c_register_board_info(2, altair_gpio_i2c_devs, ARRAY_SIZE(altair_gpio_i2c_devs));
+//	platform_add_devices(altair_platform_devices, ARRAY_SIZE(altair_platform_devices));
+
+	/*
+	 * for gpio-based bitbanging i2c bus
+	 */
+	__gpio_as_output(IOSWITCH_EN);
+	__gpio_clear_pin(IOSWITCH_EN);
+
+	return 0;
+}
+
+arch_initcall(altair_board_init);
diff --git a/arch/mips/jz4760b/board-cygnus.c b/arch/mips/jz4760b/board-cygnus.c
new file mode 100644
index 00000000000..fe8728f6125
--- /dev/null
+++ b/arch/mips/jz4760b/board-cygnus.c
@@ -0,0 +1,522 @@
+/*
+ * linux/arch/mips/jz4760/board-cygnus.c
+ *
+ * JZ4760 Cygnus board setup routines.
+ *
+ * Copyright (c) 2006-2010  Ingenic Semiconductor Inc.
+ * Author: <jlwei@ingenic.cn>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/ioport.h>
+#include <linux/mmc/host.h>
+#include <linux/console.h>
+#include <linux/delay.h>
+#include <linux/i2c.h>
+#include <linux/i2c-gpio.h>
+#include <linux/platform_device.h>
+
+#include <asm/cpu.h>
+#include <asm/bootinfo.h>
+#include <asm/mipsregs.h>
+#include <asm/reboot.h>
+
+#include <asm/jzsoc.h>
+
+extern void (*jz_timer_callback)(void);
+extern int __init jz_add_msc_devices(unsigned int controller, struct jz_mmc_platform_data *plat);
+
+void __init board_msc_init(void);
+
+#undef DEBUG
+//#define DEBUG
+#ifdef DEBUG
+#define dprintk(x...)	printk(x)
+#else
+#define dprintk(x...)
+#endif
+
+/*
+ * __gpio_as_sleep set all pins to pull-disable, and set all pins as input
+ * except sdram and the pins which can be used as CS1_N to CS4_N for chip select.
+ */
+#define __gpio_as_sleep()	              \
+do {	                                      \
+	REG_GPIO_PXFUNC(1) = ~0x03ff7fff;     \
+	REG_GPIO_PXSELC(1) = ~0x03ff7fff;     \
+	REG_GPIO_PXDIRC(1) = ~0x03ff7fff;     \
+	REG_GPIO_PXPES(1)  =  0xffffffff;     \
+	REG_GPIO_PXFUNC(2) = ~0x01e00000;     \
+	REG_GPIO_PXSELC(2) = ~0x01e00000;     \
+	REG_GPIO_PXDIRC(2) = ~0x01e00000;     \
+	REG_GPIO_PXPES(2)  =  0xffffffff;     \
+	REG_GPIO_PXFUNC(3) =  0xffffffff;     \
+	REG_GPIO_PXSELC(3) =  0xffffffff;     \
+	REG_GPIO_PXDIRC(3) =  0xffffffff;     \
+	REG_GPIO_PXPES(3)  =  0xffffffff;     \
+	REG_GPIO_PXFUNC(4) =  0xffffffff;     \
+	REG_GPIO_PXSELC(4) =  0xffffffff;     \
+	REG_GPIO_PXDIRC(4) =  0xffffffff;     \
+	REG_GPIO_PXPES(4)  =  0xffffffff;     \
+	REG_GPIO_PXFUNC(5) =  0xffffffff;     \
+	REG_GPIO_PXSELC(5) =  0xffffffff;     \
+	REG_GPIO_PXDIRC(5) =  0xffffffff;     \
+	REG_GPIO_PXPES(5)  =  0xffffffff;     \
+} while (0)
+
+struct wakeup_key_s {
+	int gpio;       /* gpio pin number */
+	int active_low; /* the key interrupt pin is low voltage
+                           or fall edge acitve */
+};
+
+/* add wakeup keys here */
+static struct wakeup_key_s wakeup_key[] = {
+    {
+		.gpio = KEY_C0,
+		.active_low = 1,
+	},
+	{
+		.gpio = KEY_C1,
+		.active_low = 1,
+	},
+    {
+		.gpio = KEY_C2,
+		.active_low = 1,
+	},
+	{
+		.gpio = KEY_C3,
+		.active_low = 1,
+	},
+	{
+		.gpio = KEY_C4,
+		.active_low = 1,
+	},
+#if defined(CONFIG_GSM_IW368)
+	{
+		.gpio = GPIO_GSM_RI,
+		.active_low = 1,
+	},
+#endif
+};
+
+static void wakeup_key_setup(void)
+{
+	int i;
+	int num = sizeof(wakeup_key) / sizeof(wakeup_key[0]);
+
+	for(i = 0; i < num; i++) {
+#if 1
+		if(wakeup_key[i].active_low)
+			__gpio_as_irq_fall_edge(wakeup_key[i].gpio);
+		else
+			__gpio_as_irq_rise_edge(wakeup_key[i].gpio);
+#endif
+		__gpio_ack_irq(wakeup_key[i].gpio);
+		__gpio_unmask_irq(wakeup_key[i].gpio);
+		__intc_unmask_irq(IRQ_GPIO0 - (wakeup_key[i].gpio/32));  /* unmask IRQ_GPIOn */
+	}
+}
+
+
+/* NOTES:
+ * 1: Pins that are floated (NC) should be set as input and pull-enable.
+ * 2: Pins that are pull-up or pull-down by outside should be set as input
+ *    and pull-disable.
+ * 3: Pins that are connected to a chip except sdram and nand flash
+ *    should be set as input and pull-disable, too.
+ */
+void jz_board_do_sleep(unsigned long *ptr)
+{
+	unsigned char i;
+
+        /* Print messages of GPIO registers for debug */
+	for(i=0;i<GPIO_PORT_NUM;i++) {
+		dprintk("run dat:%x pin:%x fun:%x sel:%x dir:%x pull:%x msk:%x trg:%x\n",        \
+			REG_GPIO_PXDAT(i),REG_GPIO_PXPIN(i),REG_GPIO_PXFUN(i),REG_GPIO_PXSEL(i), \
+			REG_GPIO_PXDIR(i),REG_GPIO_PXPE(i),REG_GPIO_PXIM(i),REG_GPIO_PXTRG(i));
+	}
+
+        /* Save GPIO registers */
+	for(i = 1; i < GPIO_PORT_NUM; i++) {
+		*ptr++ = REG_GPIO_PXFUN(i);
+		*ptr++ = REG_GPIO_PXSEL(i);
+		*ptr++ = REG_GPIO_PXDIR(i);
+		*ptr++ = REG_GPIO_PXPE(i);
+		*ptr++ = REG_GPIO_PXIM(i);
+		*ptr++ = REG_GPIO_PXDAT(i);
+		*ptr++ = REG_GPIO_PXTRG(i);
+	}
+
+        /*
+         * Set all pins to pull-disable, and set all pins as input except
+         * sdram and the pins which can be used as CS1_N to CS4_N for chip select.
+         */
+	//       __gpio_as_sleep();
+
+        /*
+	 * Set proper status for GPC21 to GPC24 which can be used as CS1_N to CS4_N.
+	 * Keep the pins' function used for chip select(CS) here according to your
+         * system to avoid chip select crashing with sdram when resuming from sleep mode.
+         */
+
+	/*
+         * If you must set some GPIOs as output to high level or low level,
+         * you can set them here, using:
+         * __gpio_as_output(n);
+         * __gpio_set_pin(n); or  __gpio_clear_pin(n);
+	 */
+
+
+#ifdef DEBUG
+        /* Keep uart function for printing debug message */
+	__gpio_as_uart0();
+	__gpio_as_uart1();
+	__gpio_as_uart2();
+	__gpio_as_uart3();
+
+        /* Print messages of GPIO registers for debug */
+	for(i=0;i<GPIO_PORT_NUM;i++) {
+		dprintk("sleep dat:%x pin:%x fun:%x sel:%x dir:%x pull:%x msk:%x trg:%x\n",      \
+			REG_GPIO_PXDAT(i),REG_GPIO_PXPIN(i),REG_GPIO_PXFUN(i),REG_GPIO_PXSEL(i), \
+			REG_GPIO_PXDIR(i),REG_GPIO_PXPE(i),REG_GPIO_PXIM(i),REG_GPIO_PXTRG(i));
+	}
+#endif
+	wakeup_key_setup();
+}
+
+void jz_board_do_resume(unsigned long *ptr)
+{
+	unsigned char i;
+
+	/* Restore GPIO registers */
+	for(i = 1; i < GPIO_PORT_NUM; i++) {
+		 REG_GPIO_PXFUNS(i) = *ptr;
+		 REG_GPIO_PXFUNC(i) = ~(*ptr++);
+
+		 REG_GPIO_PXSELS(i) = *ptr;
+		 REG_GPIO_PXSELC(i) = ~(*ptr++);
+
+		 REG_GPIO_PXDIRS(i) = *ptr;
+		 REG_GPIO_PXDIRC(i) = ~(*ptr++);
+
+		 REG_GPIO_PXPES(i) = *ptr;
+		 REG_GPIO_PXPEC(i) = ~(*ptr++);
+
+		 REG_GPIO_PXIMS(i)=*ptr;
+		 REG_GPIO_PXIMC(i)=~(*ptr++);
+
+		 REG_GPIO_PXDATS(i)=*ptr;
+		 REG_GPIO_PXDATC(i)=~(*ptr++);
+
+		 REG_GPIO_PXTRGS(i)=*ptr;
+		 REG_GPIO_PXTRGC(i)=~(*ptr++);
+	}
+
+        /* Print messages of GPIO registers for debug */
+	for(i=0;i<GPIO_PORT_NUM;i++) {
+		dprintk("resume dat:%x pin:%x fun:%x sel:%x dir:%x pull:%x msk:%x trg:%x\n",     \
+			REG_GPIO_PXDAT(i),REG_GPIO_PXPIN(i),REG_GPIO_PXFUN(i),REG_GPIO_PXSEL(i), \
+			REG_GPIO_PXDIR(i),REG_GPIO_PXPE(i),REG_GPIO_PXIM(i),REG_GPIO_PXTRG(i));
+	}
+}
+
+#if 0
+static void dancing(void)
+{
+	static unsigned char slash[] = "\\|/-";
+//	static volatile unsigned char *p = (unsigned char *)0xb6000058;
+	static volatile unsigned char *p = (unsigned char *)0xb6000016;
+	static unsigned int count = 0;
+	*p = slash[count++];
+	count &= 3;
+}
+#endif
+
+/* MSC SETUP */
+static void cygnus_sd_8bit_gpio_init(struct device *dev)
+{
+	__gpio_as_msc0_8bit();
+	__gpio_as_output(GPIO_SD0_VCC_EN_N);
+	__gpio_as_input(GPIO_SD0_CD_N);
+}
+
+static void cygnus_sd_8bit_power_on(struct device *dev)
+{
+	__gpio_clear_pin(GPIO_SD0_VCC_EN_N);
+}
+
+static void cygnus_sd_8bit_power_off(struct device *dev)
+{
+	__gpio_set_pin(GPIO_SD0_VCC_EN_N);
+}
+
+/*
+static unsigned int cygnus_sd_8bit_status(struct device *dev)
+{
+	unsigned int status;
+
+	status = (unsigned int) __gpio_get_pin(GPIO_SD0_CD_N);
+	return (!status);
+}
+*/
+
+/*
+static void cygnus_sd_8bit_plug_change(int state)
+{
+	if(state == CARD_INSERTED)
+		__gpio_as_irq_high_level(MSC0_HOTPLUG_PIN);
+	else
+		__gpio_as_irq_low_level(MSC0_HOTPLUG_PIN);
+}
+*/
+
+static unsigned int cygnus_sd_8bit_get_wp(struct device *dev)
+{
+	unsigned int status;
+
+	status = (unsigned int) __gpio_get_pin(GPIO_SD0_WP_N);
+	return (status);
+}
+/*
+
+struct jz_mmc_platform_data cygnus_sd_8bit_data = {
+#ifndef CONFIG_JZ_MSC0_SDIO_SUPPORT
+	.support_sdio   = 0,
+#else
+	.support_sdio   = 1,
+#endif
+	.ocr_mask	= MMC_VDD_32_33 | MMC_VDD_33_34,
+	.status_irq	= MSC0_HOTPLUG_IRQ,
+	.detect_pin     = GPIO_SD0_CD_N,
+	.init           = cygnus_sd_8bit_gpio_init,
+	.power_on       = cygnus_sd_8bit_power_on,
+	.power_off      = cygnus_sd_8bit_power_off,
+	.status		= cygnus_sd_8bit_status,
+	.plug_change	= cygnus_sd_8bit_plug_change,
+	.write_protect  = cygnus_sd_8bit_get_wp,
+	.max_bus_width  = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | MMC_CAP_8_BIT_DATA,
+#ifdef CONFIG_JZ_MSC0_BUS_1
+	.bus_width      = 1,
+#elif defined  CONFIG_JZ_MSC0_BUS_4
+	.bus_width      = 4,
+#else
+	.bus_width      = 8,
+#endif
+};
+*/
+
+static void cygnus_sd_4bit_gpio_init(struct device *dev)
+{
+	__gpio_as_msc1_4bit();
+	__gpio_as_output(GPIO_SD1_VCC_EN_N);
+	__gpio_set_pin(GPIO_SD1_VCC_EN_N); /* poweroff */
+	__gpio_as_input(GPIO_SD1_CD_N);
+}
+
+static void cygnus_sd_4bit_power_on(struct device *dev)
+{
+	__msc1_enable_power();
+}
+
+static void cygnus_sd_4bit_power_off(struct device *dev)
+{
+	__msc1_disable_power();
+}
+
+static void lepus_tf_cpm_start(struct device *dev)
+{
+	cpm_start_clock(CGM_MSC1);
+}
+static unsigned int cygnus_sd_4bit_status(struct device *dev)
+{
+	unsigned int status;
+
+	status = (unsigned int) __gpio_get_pin(GPIO_SD1_CD_N);
+	return (!status);
+}
+
+static void cygnus_sd_4bit_plug_change(int state)
+{
+	if(state == CARD_INSERTED)
+		__gpio_as_irq_high_level(MSC1_HOTPLUG_PIN);
+	else
+		__gpio_as_irq_low_level(MSC1_HOTPLUG_PIN);
+}
+
+static unsigned int cygnus_sd_4bit_get_wp(struct device *dev)
+{
+	unsigned int status;
+
+	status = (unsigned int) __gpio_get_pin(GPIO_SD1_WP_N);
+	return (status);
+}
+
+struct jz_mmc_platform_data cygnus_sd_4bit_data = {
+#ifndef CONFIG_JZ_MSC1_SDIO_SUPPORT
+	.support_sdio   = 0,
+#else
+	.support_sdio   = 1,
+#endif
+	.ocr_mask	= MMC_VDD_32_33 | MMC_VDD_33_34,
+	.status_irq	= MSC1_HOTPLUG_IRQ,
+	.detect_pin     = GPIO_SD1_CD_N,
+	.init           = cygnus_sd_4bit_gpio_init,
+	.power_on       = cygnus_sd_4bit_power_on,
+	.power_off      = cygnus_sd_4bit_power_off,
+	.cpm_start	= lepus_tf_cpm_start,
+	.status		= cygnus_sd_4bit_status,
+	.plug_change	= cygnus_sd_4bit_plug_change,
+	.write_protect  = cygnus_sd_4bit_get_wp,
+	.max_bus_width  = MMC_CAP_SD_HIGHSPEED | MMC_CAP_4_BIT_DATA,
+#ifdef CONFIG_JZ_MSC1_BUS_1
+	.bus_width      = 1,
+#else
+	.bus_width      = 4,
+#endif
+};
+
+void __init board_msc_init(void)
+{
+#ifdef CONFIG_JZ_MSC0
+//	jz_add_msc_devices(0, &cygnus_sd_8bit_data);
+#endif
+
+#ifdef CONFIG_JZ_MSC1
+	jz_add_msc_devices(1, &cygnus_sd_4bit_data);
+#endif
+}
+
+static void f4760_timer_callback(void)
+{
+	static unsigned long count = 0;
+
+	if ((++count) % 50 == 0) {
+//		dancing();
+		count = 0;
+	}
+}
+
+static void __init board_cpm_setup(void)
+{
+	/* Stop unused module clocks here.
+	 * We have started all module clocks at arch/mips/jz4760/setup.c.
+	 */
+}
+
+static void __init board_gpio_setup(void)
+{
+	/*
+	 * Initialize SDRAM pins
+	 */
+}
+
+void __init jz_board_setup(void)
+{
+	printk("JZ4760 Cygnus board setup\n");
+//	jz_restart(NULL);
+	board_cpm_setup();
+	board_gpio_setup();
+
+	jz_timer_callback = f4760_timer_callback;
+}
+
+/**
+ * Called by arch/mips/kernel/proc.c when 'cat /proc/cpuinfo'.
+ * Android requires the 'Hardware:' field in cpuinfo to setup the init.%hardware%.rc.
+ */
+const char *get_board_type(void)
+{
+	return "Cygnus";
+}
+#if defined(CONFIG_I2C_GPIO)
+static struct i2c_board_info cygnus_gpio_i2c_devs[] __initdata = {
+        {
+                I2C_BOARD_INFO("jz_edid", 0xa0 >> 1),
+        },
+        {
+                I2C_BOARD_INFO("jz_hdcp_rx", 0x74 >> 1),
+        },
+        {
+                I2C_BOARD_INFO("jz_hey", 0xa8 >> 1),
+        },
+#if 0
+        {
+                I2C_BOARD_INFO("jz_edid_segment_ptr", 0x60 >> 1),
+        },
+        {
+                I2C_BOARD_INFO("jz_hdcp_rx_bksv", 0x00 >> 1),
+        },
+        {
+                I2C_BOARD_INFO("jz_hdcp_rx_ri", 0x08 >> 1),
+        },
+        {
+                I2C_BOARD_INFO("jz_hdcp_rx_aksv", 0x10 >> 1),
+        },
+        {
+                I2C_BOARD_INFO("jz_hdcp_rx_ainfo", 0x15 >> 1),
+        },
+        {
+                I2C_BOARD_INFO("jz_hdcp_rx_an", 0x18 >> 1),
+        },
+        {
+                I2C_BOARD_INFO("jz_hdcp_rx_sha1_hash", 0x20 >> 1),
+        },
+        {
+                I2C_BOARD_INFO("jz_hdcp_rx_bcaps", 0x40 >> 1),
+        },
+        {
+                I2C_BOARD_INFO("jz_hdcp_rx_bstatus", 0x41 >> 1),
+        },
+        {
+                I2C_BOARD_INFO("jz_hdcp_rx_ksv_fifo", 0x43 >> 1),
+        },
+#endif
+};
+
+static struct i2c_gpio_platform_data cygnus_i2c_gpio_data = {
+        .sda_pin        = GPIO_I2C1_SDA,
+        .scl_pin        = GPIO_I2C1_SCK,
+};
+
+static struct platform_device cygnus_i2c_gpio_device = {
+        .name   = "i2c-gpio",
+        .id     = 2,
+        .dev    = {
+                .platform_data = &cygnus_i2c_gpio_data,
+        },
+};
+
+
+static struct platform_device *cygnus_platform_devices[] __initdata = {
+//#if defined(CONFIG_I2C_GPIO)
+        &cygnus_i2c_gpio_device,
+//#endif
+};
+#endif
+
+static struct i2c_board_info ep932_i2c_devs[] __initdata = {
+        {
+                I2C_BOARD_INFO("jz_ep932", 0x38),
+               // .irq = GPIO_WM831x_DETECT + IRQ_GPIO_0,
+               // .platform_data = &wm831x_platform_data,
+        },
+};
+
+
+
+void __init board_i2c_init(void) {
+	i2c_register_board_info(1, ep932_i2c_devs, ARRAY_SIZE(ep932_i2c_devs));
+#if defined(CONFIG_I2C_GPIO)
+        i2c_register_board_info(2, cygnus_gpio_i2c_devs, ARRAY_SIZE(cygnus_gpio_i2c_devs));
+        platform_add_devices(cygnus_platform_devices, ARRAY_SIZE(cygnus_platform_devices));
+#endif
+
+
+}
+
diff --git a/arch/mips/jz4760b/board-f4760.c b/arch/mips/jz4760b/board-f4760.c
new file mode 100644
index 00000000000..21d0eff96e3
--- /dev/null
+++ b/arch/mips/jz4760b/board-f4760.c
@@ -0,0 +1,352 @@
+/*
+ * linux/arch/mips/jz4760b/board-f4760b.c
+ *
+ * JZ4760B F4760b board setup routines.
+ *
+ * Copyright (c) 2006-2008  Ingenic Semiconductor Inc.
+ * Author: <jlwei@ingenic.cn>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/ioport.h>
+#include <linux/mm.h>
+#include <linux/console.h>
+#include <linux/delay.h>
+#include <linux/i2c.h>
+
+#include <asm/cpu.h>
+#include <asm/bootinfo.h>
+#include <asm/mipsregs.h>
+#include <asm/reboot.h>
+
+#include <asm/jzsoc.h>
+
+/*
+#include <linux/mfd/wm831x/core.h>
+#include <linux/mfd/wm831x/auxadc.h>
+#include <linux/mfd/wm831x/pdata.h>
+#include <linux/mfd/wm831x/irq.h>
+#include <linux/mfd/wm831x/watchdog.h>
+#include <linux/mfd/wm831x/status.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/driver.h>
+*/
+
+#define WM831X_LDO_MAX_NAME 6
+
+extern void (*jz_timer_callback)(void);
+
+static void dancing(void)
+{
+	static unsigned char slash[] = "\\|/-";
+//	static volatile unsigned char *p = (unsigned char *)0xb6000058;
+	static volatile unsigned char *p = (unsigned char *)0xb6000016;
+	static unsigned int count = 0;
+	*p = slash[count++];
+	count &= 3;
+}
+
+static void f4760b_timer_callback(void)
+{
+	static unsigned long count = 0;
+
+	if ((++count) % 50 == 0) {
+		dancing();
+		count = 0;
+	}
+}
+
+static void __init board_cpm_setup(void)
+{
+	/* Stop unused module clocks here.
+	 * We have started all module clocks at arch/mips/jz4760b/setup.c.
+	 */
+}
+
+static void __init board_gpio_setup(void)
+{
+	/*
+	 * Initialize SDRAM pins
+	 */
+}
+
+void __init jz_board_setup(void)
+{
+	printk("JZ4760B F4760b board setup\n");
+//	jz_restart(NULL);
+	board_cpm_setup();
+	board_gpio_setup();
+
+	jz_timer_callback = f4760b_timer_callback;
+}
+
+/**
+ * Called by arch/mips/kernel/proc.c when 'cat /proc/cpuinfo'.
+ * Android requires the 'Hardware:' field in cpuinfo to setup the init.%hardware%.rc.
+ */
+const char *get_board_type(void)
+{
+	return "f4760b";
+}
+
+/*****
+ * Wm831x init
+ *****/
+#if 0
+struct wm831x_ldo {
+	char name[WM831X_LDO_MAX_NAME];
+	struct regulator_desc desc;
+	int base;
+	struct wm831x *wm831x;
+	struct regulator_dev *regulator;
+};
+
+static int wm8310_pre_init(struct wm831x *wm831x){
+
+	int ret;
+
+        /* close all wm831x regulators . */
+	ret = wm831x_set_bits(wm831x,WM831X_LDO_ENABLE,0x7ff,0);
+	if (ret != 0)
+		dev_err(wm831x->dev, "Failed to close all ldo: %d\n",ret);
+	
+	return 0;
+}
+
+static int wm8310_post_init(struct wm831x *wm831x){
+	
+	int ret;
+
+	ret = wm831x_reg_unlock(wm831x);
+	if (ret != 0) {
+		dev_err(wm831x->dev, "Failed to unlock registers: %d\n", ret);
+		return -1;
+	}
+	
+	// close wm831x watchdog
+	ret = wm831x_set_bits(wm831x,WM831X_WATCHDOG,WM831X_WDOG_ENA,0);
+	if (ret != 0)
+		dev_err(wm831x->dev, "Failed to close watchdog: %d\n",ret);
+	
+	// set ON pin timeout period and set secondary action as irq
+
+	ret = wm831x_set_bits(wm831x,WM831X_ON_PIN_CONTROL,
+			      WM831X_ON_PIN_SECACT_MASK  | 
+			      WM831X_ON_PIN_PRIMACT_MASK |
+			      WM831X_ON_PIN_TO_MASK,
+			      WM831X_ON_PIN_AS_IRQ );
+	if (ret != 0)
+		dev_err(wm831x->dev, "Failed to set ON pin timeout period: %d\n",ret);
+
+	wm831x_reg_lock(wm831x);
+	//set wm831x LED1 as a flag of charge status
+	ret = wm831x_set_bits(wm831x,WM831X_STATUS_LED_1,WM831X_LED1_MASK,
+			      WM831X_LED1_CHARGE_STATE);
+	if (ret != 0)
+		dev_err(wm831x->dev, "Failed to set status of charge on led1: %d\n",ret);
+
+	return 0;
+}
+
+struct wm831x_backlight_pdata wm8310_backlight = {
+
+	.isink     = 1,
+	.max_uA   = 3000,
+};
+static struct wm831x_battery_pdata wm8310_battery_data={
+
+	.enable        = 1,
+	.fast_enable   = 1,
+	.off_mask      = 0,
+	.trickle_ilim  = 50,         /** Trickle charge current limit, in mA */
+	.vsel          = 4200,       /** Target voltage, in mV */
+	.eoc_iterm     = 50,         /** End of trickle charge current, in mA */
+	.fast_ilim     = 400,        /** Fast charge current limit, in mA */
+	.timeout       = 300,        /** Charge cycle timeout, in minutes */
+};
+
+struct wm831x_status_pdata wm8310_led_status[] = {
+	{
+		.default_src = WM831X_STATUS_CHARGER,
+		.name        = "wm831x-status",
+	},
+};
+
+static struct regulator_init_data wm8310_dcdc[]={
+	{
+		.constraints = {
+			.name    = "wm831x-dcdc1",
+//			.boot_on = 0,
+		},
+	},
+	{
+		.constraints = {
+			.name    = "wm831x-dcdc2",
+//			.boot_on = 1,
+		},
+	 
+	},
+       	{
+		.constraints = {
+			.name    = "wm831x-dcdc3",
+//			.boot_on = 1,
+		},
+	},
+	{
+		.constraints = {
+			.name    = "wm831x-dcdc4",
+//			.boot_on = 1,
+		},
+	},
+};
+
+static int wm8310_ldo1_init( void *driver_data )
+{	
+	return 0;
+}
+struct wm831x_ldo ldo1_driver_data = {
+	.base = WM831X_LDO1_CONTROL,
+};
+
+static struct regulator_init_data wm8310_ldo[]={
+	{
+		.constraints = {
+			.name     = "wm831x-ldo1",
+			.apply_uV = 1,
+			.min_uV   = 3300000,
+			.max_uV   = 3300000,
+			.boot_on  = 0,
+		},
+		.regulator_init  = &wm8310_ldo1_init,
+	},
+	{
+		.constraints = {
+			.name = "wm831x-ldo2",
+			.apply_uV = 1,
+			.min_uV   = 1200000,
+			.max_uV   = 1200000,
+			.boot_on = 0,
+		},
+	 
+	},
+       	{
+		.constraints = {
+			.name    = "wm831x-ldo3",
+			.apply_uV = 1,
+			.min_uV   = 3300000,
+			.max_uV   = 3300000,
+			.boot_on = 0,
+		},
+	},
+	{
+		.constraints = {
+			.name = "wm831x-ldo4",
+			.apply_uV = 1,
+			.min_uV   = 3300000,
+			.max_uV   = 3300000,
+			.boot_on = 0,
+		},
+	 
+	},
+	{
+		.constraints = {
+			.name    = "wm831x-ldo5",
+			.apply_uV = 1,
+			.min_uV   = 3300000,
+			.max_uV   = 3300000,
+			.boot_on = 0,
+		},
+	},
+	{
+		.constraints = {
+			.name = "wm831x-ldo6",
+			.apply_uV = 1,
+			.min_uV   = 3300000,
+			.max_uV   = 3300000,
+			.boot_on = 0,
+		},
+	 
+	},
+       	{
+		.constraints = {
+			.name    = "wm831x-ldo7",
+			.apply_uV = 1,
+			.min_uV   = 1200000,
+			.max_uV   = 1200000,
+			.boot_on = 0,
+		},
+	},
+	{
+		.constraints = {
+			.name = "wm831x-ldo8",
+			.apply_uV = 1,
+			.min_uV   = 1800000,
+			.max_uV   = 1800000,
+			.boot_on = 0,
+		},
+	 
+	},
+		{
+		.constraints = {
+			.name    = "wm831x-ldo9",
+			.apply_uV = 1,
+			.min_uV   = 1800000,
+			.max_uV   = 1800000,
+			.boot_on = 0,
+		},
+	},
+	{
+		.constraints = {
+			.name = "wm831x-ldo10",
+			.apply_uV = 1,
+			.min_uV   = 2800000,
+			.max_uV   = 2800000,
+			.boot_on = 0,
+		},
+	 
+	},
+	{
+		.constraints = {
+			.name = "wm831x-ldo11",
+			.boot_on = 0,
+		},
+	 
+	},
+
+};
+
+static struct wm831x_pdata wm831x_platform_data = {
+	.pre_init  = &wm8310_pre_init,
+	.post_init = &wm8310_post_init,
+	.backlight = &wm8310_backlight,
+	.battery   = &wm8310_battery_data,
+	.dcdc      = { wm8310_dcdc, wm8310_dcdc+1, wm8310_dcdc+2, wm8310_dcdc+3 },
+	.ldo       = { 
+			wm8310_ldo,  wm8310_ldo+1,wm8310_ldo+2,wm8310_ldo+3,
+			wm8310_ldo+4,wm8310_ldo+5,wm8310_ldo+6,wm8310_ldo+7,
+			wm8310_ldo+8,wm8310_ldo+9,wm8310_ldo+10
+	},
+};
+
+static struct i2c_board_info wm831x_i2c_devs[] __initdata = {
+	{
+		I2C_BOARD_INFO("wm8310", 0x34),
+//		.irq = GPIO_WM831x_IRQ,
+		.platform_data = &wm831x_platform_data, 
+	}, 
+};
+
+static int __init wm831x_platform_init( void )
+{
+	i2c_register_board_info(0,wm831x_i2c_devs,ARRAY_SIZE(wm831x_i2c_devs));
+//	platform_add_devices(aquila_platform_devices, ARRAY_SIZE(aquila_platform_devices));
+	return 0;
+}
+
+arch_initcall(wm831x_platform_init);
+#endif
diff --git a/arch/mips/jz4760b/board-lepus.c b/arch/mips/jz4760b/board-lepus.c
new file mode 100644
index 00000000000..d3c24f43b7f
--- /dev/null
+++ b/arch/mips/jz4760b/board-lepus.c
@@ -0,0 +1,661 @@
+/*
+ * linux/arch/mips/jz4760b/board-cygnus.c
+ *
+ * JZ4760B Cygnus board setup routines.
+ *
+ * Copyright (c) 2006-2010  Ingenic Semiconductor Inc.
+ * Author: <jlwei@ingenic.cn>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/ioport.h>
+#include <linux/console.h>
+#include <linux/delay.h>
+
+#include <asm/cpu.h>
+#include <asm/bootinfo.h>
+#include <asm/mipsregs.h>
+#include <asm/reboot.h>
+
+#include <asm/jzsoc.h>
+#include <linux/i2c.h>
+#include <linux/mmc/host.h>
+#include <linux/ft5x0x_ts.h>
+#include <linux/spi/spi.h>
+extern void (*jz_timer_callback)(void);
+extern int __init jz_add_msc_devices(unsigned int controller, struct jz_mmc_platform_data *plat);
+
+#undef DEBUG
+//#define DEBUG
+#ifdef DEBUG
+#define dprintk(x...)	printk(x)
+#else
+#define dprintk(x...)
+#endif
+
+/*
+ *  config_gpio_on_sleep config all gpio pins when sleep.
+ */
+struct gpio_sleep_status {
+	unsigned int input;
+	unsigned int input_pull;
+	unsigned int input_no_pull;
+	unsigned int output;
+	unsigned int output_high;
+	unsigned int output_low;
+	unsigned int no_operation;
+};
+
+void config_gpio_on_sleep(void)
+{
+	int i = 0;
+	struct gpio_sleep_status gpio_sleep_st[] = {
+		/* GPA */
+		{
+			.input_pull = BIT31 | BIT27 |
+			BITS_H2L(29,28) | /* NC pin */
+			BITS_H2L(19,0), /* NAND: SD0~SD15 */
+
+			.output_high = BIT21 | BIT22 | BIT23 | BIT24 | BIT25 | BIT26, /* NAND: CS1~CS6 */
+			.output_low = 0x0,
+#ifndef CONFIG_JZ_SYSTEM_AT_CARD
+			.no_operation = 0x0,
+#else
+			.no_operation = BITS_H2L(23, 18),
+#endif
+		},
+
+		/* GPB */
+		{
+			.input_pull = BIT30 | BIT27 | BIT26 | BIT25 | BITS_H2L(24,22) | BIT20 |
+			BITS_H2L(19,0), /* SA0~SA5 */
+
+			.output_high = BIT29,
+			.output_low = BIT31 | BIT28 | BIT21,
+#ifndef CONFIG_JZ_SYSTEM_AT_CARD
+			.no_operation = 0x0,
+#else
+			.no_operation = BIT0,
+#endif
+		},
+
+		/* GPC */
+		{
+			.input_pull = BITS_H2L(31,28),
+			.output_high = 0x0,
+			.output_low = BITS_H2L(27,0),
+			.no_operation = 0x0,
+		},
+
+		/* GPD */
+		{
+			.input_pull = BITS_H2L(29,26) | BITS_H2L(19,14) | BITS_H2L(13,12) || BITS_H2L(10,0) | BIT11,  // bit11 temporary input_pull
+			.output_high = 0x0,
+			.output_low =  BITS_H2L(25,20), // | BIT11,
+			.no_operation = 0x0,
+		},
+
+		/* GPE */
+		{
+			.input_pull = BITS_H2L(18,11) | BITS_H2L(8,3) | BIT0,
+			.output_high = BIT9,
+			.output_low = BITS_H2L(29,20) | BIT10 | BIT1 | BIT2,
+			.no_operation = 0x0,
+		},
+
+		/* GPF */
+		{
+			.input_pull = BIT11 | BITS_H2L(8,4) | BITS_H2L(2,0),
+			.output_high = BIT9,
+			.output_low = BIT3,
+			.no_operation = 0x0,
+		},
+	};
+
+	for (i = 0; i < 6; i++) {
+		gpio_sleep_st[i].input_pull &= ~gpio_sleep_st[i].no_operation;
+		gpio_sleep_st[i].output_high &= ~gpio_sleep_st[i].no_operation;
+		gpio_sleep_st[i].output_low &= ~gpio_sleep_st[i].no_operation;
+		gpio_sleep_st[i].input_no_pull = 0xffffffff &
+			~(gpio_sleep_st[i].input_pull |
+			  gpio_sleep_st[i].output_high |
+			  gpio_sleep_st[i].output_low) &
+			~gpio_sleep_st[i].no_operation;
+
+		gpio_sleep_st[i].input = gpio_sleep_st[i].input_pull | gpio_sleep_st[i].input_no_pull;
+		gpio_sleep_st[i].output = gpio_sleep_st[i].output_high | gpio_sleep_st[i].output_low;
+
+		/* all as gpio, except interrupt pins(see @wakeup_key_setup()) */
+		REG_GPIO_PXFUNC(i) =  (0xffffffff & ~gpio_sleep_st[i].no_operation);
+		REG_GPIO_PXSELC(i) =  (0xffffffff & ~gpio_sleep_st[i].no_operation);
+		/* input */
+		REG_GPIO_PXDIRC(i) =  gpio_sleep_st[i].input;
+		/* pull */
+		REG_GPIO_PXPEC(i) = gpio_sleep_st[i].input_pull;
+		/* no_pull */
+		REG_GPIO_PXPES(i) =  gpio_sleep_st[i].input_no_pull;
+
+		/* output */
+		REG_GPIO_PXDIRS(i) =  gpio_sleep_st[i].output;
+		REG_GPIO_PXPES(i)  = gpio_sleep_st[i].output; /* disable pull */
+		/* high */
+		REG_GPIO_PXDATS(i) = gpio_sleep_st[i].output_high;
+		/* low */
+		REG_GPIO_PXDATC(i) = gpio_sleep_st[i].output_low;
+	}
+}
+
+struct wakeup_key_s {
+	int gpio;       /* gpio pin number */
+	int active_low; /* the key interrupt pin is low voltage
+                           or fall edge acitve */
+};
+
+/* add wakeup keys here */
+static struct wakeup_key_s wakeup_key[] = {
+	{
+		.gpio = GPIO_POWER_ON,
+		.active_low = ACTIVE_LOW_WAKE_UP,
+	},
+#ifndef CONFIG_JZ_SYSTEM_AT_CARD
+	{
+		.gpio = MSC0_HOTPLUG_PIN,
+		.active_low = ACTIVE_LOW_MSC0_CD,
+	},
+#endif
+	{
+		.gpio = MSC1_HOTPLUG_PIN,
+		.active_low = ACTIVE_LOW_MSC1_CD,
+	},
+};
+
+static void wakeup_key_setup(void)
+{
+	int i;
+	int num = sizeof(wakeup_key) / sizeof(wakeup_key[0]);
+
+	for(i = 0; i < num; i++) {
+		if(wakeup_key[i].active_low)
+			__gpio_as_irq_fall_edge(wakeup_key[i].gpio);
+		else
+			__gpio_as_irq_rise_edge(wakeup_key[i].gpio);
+
+		__gpio_ack_irq(wakeup_key[i].gpio);
+		__gpio_unmask_irq(wakeup_key[i].gpio);
+		__intc_unmask_irq(IRQ_GPIO0 - (wakeup_key[i].gpio/32));  /* unmask IRQ_GPIOn */
+	}
+}
+
+
+/* NOTES:
+ * 1: Pins that are floated (NC) should be set as input and pull-enable.
+ * 2: Pins that are pull-up or pull-down by outside should be set as input
+ *    and pull-disable.
+ * 3: Pins that are connected to a chip except sdram and nand flash
+ *    should be set as input and pull-disable, too.
+ */
+void jz_board_do_sleep(unsigned long *ptr)
+{
+	unsigned char i;
+
+        /* Print messages of GPIO registers for debug */
+	for(i=0;i<GPIO_PORT_NUM;i++) {
+		dprintk("run dat:%x pin:%x fun:%x sel:%x dir:%x pull:%x msk:%x trg:%x\n",        \
+			REG_GPIO_PXDAT(i),REG_GPIO_PXPIN(i),REG_GPIO_PXFUN(i),REG_GPIO_PXSEL(i), \
+			REG_GPIO_PXDIR(i),REG_GPIO_PXPE(i),REG_GPIO_PXIM(i),REG_GPIO_PXTRG(i));
+	}
+
+        /* Save GPIO registers */
+	for(i = 1; i < GPIO_PORT_NUM; i++) {
+		*ptr++ = REG_GPIO_PXFUN(i);
+		*ptr++ = REG_GPIO_PXSEL(i);
+		*ptr++ = REG_GPIO_PXDIR(i);
+		*ptr++ = REG_GPIO_PXPE(i);
+		*ptr++ = REG_GPIO_PXIM(i);
+		*ptr++ = REG_GPIO_PXDAT(i);
+		*ptr++ = REG_GPIO_PXTRG(i);
+	}
+
+        /*
+         * Set all pins to pull-disable, and set all pins as input except
+         * sdram and the pins which can be used as CS1_N to CS4_N for chip select.
+         */
+	config_gpio_on_sleep();
+
+        /*
+	 * Set proper status for GPC21 to GPC24 which can be used as CS1_N to CS4_N.
+	 * Keep the pins' function used for chip select(CS) here according to your
+         * system to avoid chip select crashing with sdram when resuming from sleep mode.
+         */
+
+	/*
+         * If you must set some GPIOs as output to high level or low level,
+         * you can set them here, using:
+         * __gpio_as_output(n);
+         * __gpio_set_pin(n); or  __gpio_clear_pin(n);
+	 */
+
+	if (!console_suspend_enabled)
+		__gpio_as_uart1();
+
+#if 0
+        /* Keep uart function for printing debug message */
+	__gpio_as_uart0();
+	__gpio_as_uart1();
+	__gpio_as_uart2();
+	__gpio_as_uart3();
+
+        /* Print messages of GPIO registers for debug */
+	for(i=0;i<GPIO_PORT_NUM;i++) {
+		printk("GP%d: data:0x%08x pin:0x%08x fun:0x%08x sel:0x%08x dir:0x%08x pull:0x%08x msk:0x%08x trg:0x%08x\n",
+		       i, REG_GPIO_PXDAT(i),REG_GPIO_PXPIN(i),REG_GPIO_PXFUN(i),REG_GPIO_PXSEL(i),
+		       REG_GPIO_PXDIR(i),REG_GPIO_PXPE(i),REG_GPIO_PXIM(i),REG_GPIO_PXTRG(i));
+	}
+#endif
+	wakeup_key_setup();
+}
+
+void jz_board_do_resume(unsigned long *ptr)
+{
+	unsigned char i;
+
+	/* Restore GPIO registers */
+	for(i = 1; i < GPIO_PORT_NUM; i++) {
+		 REG_GPIO_PXFUNS(i) = *ptr;
+		 REG_GPIO_PXFUNC(i) = ~(*ptr++);
+
+		 REG_GPIO_PXSELS(i) = *ptr;
+		 REG_GPIO_PXSELC(i) = ~(*ptr++);
+
+		 REG_GPIO_PXDIRS(i) = *ptr;
+		 REG_GPIO_PXDIRC(i) = ~(*ptr++);
+
+		 REG_GPIO_PXPES(i) = *ptr;
+		 REG_GPIO_PXPEC(i) = ~(*ptr++);
+
+		 REG_GPIO_PXIMS(i)=*ptr;
+		 REG_GPIO_PXIMC(i)=~(*ptr++);
+
+		 REG_GPIO_PXDATS(i)=*ptr;
+		 REG_GPIO_PXDATC(i)=~(*ptr++);
+
+		 REG_GPIO_PXTRGS(i)=*ptr;
+		 REG_GPIO_PXTRGC(i)=~(*ptr++);
+	}
+
+        /* Print messages of GPIO registers for debug */
+	for(i=0;i<GPIO_PORT_NUM;i++) {
+		dprintk("resume dat:%x pin:%x fun:%x sel:%x dir:%x pull:%x msk:%x trg:%x\n",     \
+			REG_GPIO_PXDAT(i),REG_GPIO_PXPIN(i),REG_GPIO_PXFUN(i),REG_GPIO_PXSEL(i), \
+			REG_GPIO_PXDIR(i),REG_GPIO_PXPE(i),REG_GPIO_PXIM(i),REG_GPIO_PXTRG(i));
+	}
+}
+
+static void lepus_sd_gpio_init(struct device *dev)
+{
+#if defined (CONFIG_JZ_SYSTEM_AT_CARD)
+	__gpio_as_msc0_boot();
+#else
+	__gpio_as_msc0_8bit();
+#endif
+	__gpio_as_output(GPIO_SD0_VCC_EN_N);
+	__gpio_set_pin(GPIO_SD0_VCC_EN_N); /* poweroff */
+	__gpio_as_input(GPIO_SD0_CD_N);
+}
+
+static void lepus_sd_power_on(struct device *dev)
+{
+	__msc0_enable_power();
+}
+
+static void lepus_sd_power_off(struct device *dev)
+{
+	__msc0_disable_power();
+}
+
+static void lepus_sd_cpm_start(struct device *dev)
+{
+	cpm_start_clock(CGM_MSC0);
+}
+
+static unsigned int lepus_sd_status(struct device *dev)
+{
+#if defined(CONFIG_JZ_SYSTEM_AT_CARD)
+	return 1;
+#else
+	unsigned int status;
+
+	status = (unsigned int) __gpio_get_pin(GPIO_SD0_CD_N);
+#if ACTIVE_LOW_MSC0_CD
+	return !status;
+#else
+	return status;
+#endif
+#endif
+}
+
+static void lepus_sd_plug_change(int state)
+{
+	if(state == CARD_INSERTED) /* wait for remove */
+#if ACTIVE_LOW_MSC0_CD
+		__gpio_as_irq_high_level(MSC0_HOTPLUG_PIN);
+#else
+		__gpio_as_irq_low_level(MSC0_HOTPLUG_PIN);
+#endif
+	else		      /* wait for insert */
+#if ACTIVE_LOW_MSC0_CD
+		__gpio_as_irq_low_level(MSC0_HOTPLUG_PIN);
+#else
+		__gpio_as_irq_high_level(MSC0_HOTPLUG_PIN);
+#endif
+}
+
+static unsigned int lepus_sd_get_wp(struct device *dev)
+{
+#if defined(CONFIG_JZ_SYSTEM_AT_CARD)
+	return 0;
+#else
+	int i = 0;
+	unsigned int status;
+
+	status = (unsigned int) __gpio_get_pin(MSC0_WP_PIN);
+	return (status);
+#endif
+}
+#if defined(CONFIG_JZ_RECOVERY_SUPPORT) && defined(CONFIG_JZ_SYSTEM_AT_CARD)
+struct mmc_partition_info lepus_partitions[] = {
+	[0] = {"mbr",0,512,0},//0 - 512
+	[1] = {"uboot",512,3*1024*1024-512,0}, // 512 - 2.5MB
+	[2] = {"misc",0x3000000,0x1000000,0},//3MB - 1MB
+	[3] = {"kernel",0x400000,0x400000,0},//4MB - 4MB
+	[4] = {"recovery",0x800000,0x400000,0},//8MB -4MB
+
+	[5] = {"rootfs",12*1024*1024,256*1024*1024,1}, //12MB - 256MB
+	[6] = {"data",268*1024*1024,500*1024*1024,1},//268MB - 500MB
+	[7] = {"cache",768*1024*1024,32*1024*1024,1},//768MB - 32MB
+	[8] = {"test_0",0x0,0xffffffff,0},
+};
+#endif
+struct jz_mmc_platform_data lepus_sd_data = {
+#ifndef CONFIG_JZ_MSC0_SDIO_SUPPORT
+	.support_sdio   = 0,
+#else
+	.support_sdio   = 1,
+#endif
+	.ocr_mask	= MMC_VDD_32_33 | MMC_VDD_33_34,
+#if defined(CONFIG_JZ_SYSTEM_AT_CARD)
+	.status_irq	= 0,
+	.detect_pin     = 0,
+#else
+	.status_irq	= MSC0_HOTPLUG_IRQ,
+	.detect_pin     = GPIO_SD0_CD_N,
+#endif
+	.init           = lepus_sd_gpio_init,
+	.power_on       = lepus_sd_power_on,
+	.power_off      = lepus_sd_power_off,
+	.cpm_start	= lepus_sd_cpm_start,
+	.status		= lepus_sd_status,
+	.plug_change	= lepus_sd_plug_change,
+	.write_protect  = lepus_sd_get_wp,
+	.max_bus_width  = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED
+#ifdef CONFIG_JZ_MSC0_BUS_4
+	| MMC_CAP_4_BIT_DATA
+#endif
+#ifdef CONFIG_JZ_MSC0_BUS_8
+	| MMC_CAP_8_BIT_DATA
+#endif
+	,
+
+#ifdef CONFIG_JZ_MSC0_BUS_1
+	.bus_width      = 1,
+#elif defined  CONFIG_JZ_MSC0_BUS_4
+	.bus_width      = 4,
+#else
+	.bus_width      = 8,
+#endif
+#if defined(CONFIG_JZ_RECOVERY_SUPPORT) && defined(CONFIG_JZ_SYSTEM_AT_CARD)
+	.partitions = lepus_partitions,
+	.num_partitions = ARRAY_SIZE(lepus_partitions),
+#endif
+};
+
+static void lepus_tf_gpio_init(struct device *dev)
+{
+	__gpio_as_msc1_4bit();
+	__gpio_as_output(GPIO_SD1_VCC_EN_N);
+	__gpio_set_pin(GPIO_SD1_VCC_EN_N); /* poweroff */
+	__gpio_as_input(GPIO_SD1_CD_N);
+}
+
+static void lepus_tf_power_on(struct device *dev)
+{
+	__msc1_enable_power();
+}
+
+static void lepus_tf_power_off(struct device *dev)
+{
+	__msc1_disable_power();
+}
+
+static void lepus_tf_cpm_start(struct device *dev)
+{
+	cpm_start_clock(CGM_MSC1);
+}
+
+static unsigned int lepus_tf_status(struct device *dev)
+{
+	unsigned int status = 0;
+	status = (unsigned int) __gpio_get_pin(GPIO_SD1_CD_N);
+#if ACTIVE_LOW_MSC1_CD
+	return !status;
+#else
+	return status;
+#endif
+}
+
+static void lepus_tf_plug_change(int state)
+{
+	if(state == CARD_INSERTED) /* wait for remove */
+#if ACTIVE_LOW_MSC1_CD
+		__gpio_as_irq_high_level(MSC1_HOTPLUG_PIN);
+#else
+		__gpio_as_irq_low_level(MSC1_HOTPLUG_PIN);
+#endif
+	else		      /* wait for insert */
+#if ACTIVE_LOW_MSC1_CD
+		__gpio_as_irq_low_level(MSC1_HOTPLUG_PIN);
+#else
+		__gpio_as_irq_high_level(MSC1_HOTPLUG_PIN);
+#endif
+}
+
+struct jz_mmc_platform_data lepus_tf_data = {
+#ifndef CONFIG_JZ_MSC1_SDIO_SUPPORT
+	.support_sdio   = 0,
+#else
+	.support_sdio   = 1,
+#endif
+	.ocr_mask	= MMC_VDD_32_33 | MMC_VDD_33_34,
+	.status_irq	= MSC1_HOTPLUG_IRQ,
+	.detect_pin     = GPIO_SD1_CD_N,
+	.init           = lepus_tf_gpio_init,
+	.power_on       = lepus_tf_power_on,
+	.power_off      = lepus_tf_power_off,
+	.cpm_start	= lepus_tf_cpm_start,
+	.status		= lepus_tf_status,
+	.plug_change	= lepus_tf_plug_change,
+	.max_bus_width  = MMC_CAP_SD_HIGHSPEED
+#ifdef CONFIG_JZ_MSC1_BUS_4
+	| MMC_CAP_4_BIT_DATA
+#endif
+	,
+#ifdef CONFIG_JZ_MSC1_BUS_1
+	.bus_width      = 1,
+#else
+	.bus_width      = 4,
+#endif
+};
+
+static void lepus_msc2_gpio_init(struct device *dev)
+{
+	return;
+}
+
+static void lepus_msc2_power_on(struct device *dev)
+{
+	return;
+}
+
+static void lepus_msc2_power_off(struct device *dev)
+{
+	return;
+}
+
+static void lepus_msc2_cpm_start(struct device *dev)
+{
+	cpm_start_clock(CGM_MSC2);
+}
+
+static unsigned int lepus_msc2_status(struct device *dev)
+{
+	return 0;	      /* default: no card */
+}
+
+static void lepus_msc2_plug_change(int state)
+{
+	return;
+}
+
+struct jz_mmc_platform_data lepus_msc2_data = {
+#ifndef CONFIG_JZ_MSC2_SDIO_SUPPORT
+	.support_sdio   = 0,
+#else
+	.support_sdio   = 1,
+#endif
+	.ocr_mask	= MMC_VDD_32_33 | MMC_VDD_33_34,
+	.status_irq	= 0, //MSC1_HOTPLUG_IRQ,
+	.detect_pin     = 0, //GPIO_SD1_CD_N,
+	.init           = lepus_msc2_gpio_init,
+	.power_on       = lepus_msc2_power_on,
+	.power_off      = lepus_msc2_power_off,
+	.cpm_start	= lepus_msc2_cpm_start,
+	.status		= lepus_msc2_status,
+	.plug_change	= lepus_msc2_plug_change,
+	.max_bus_width  = MMC_CAP_SD_HIGHSPEED
+#ifdef CONFIG_JZ_MSC2_BUS_4
+	| MMC_CAP_4_BIT_DATA
+#endif
+	,
+#ifdef CONFIG_JZ_MSC2_BUS_1
+	.bus_width      = 1,
+#else
+	.bus_width      = 4,
+#endif
+};
+
+void __init board_msc_init(void)
+{
+	jz_add_msc_devices(0, &lepus_sd_data);
+	jz_add_msc_devices(1, &lepus_tf_data);
+	jz_add_msc_devices(2, &lepus_msc2_data);
+}
+
+static void f4760b_timer_callback(void)
+{
+	static unsigned long count = 0;
+
+	if ((++count) % 50 == 0) {
+//		dancing();
+		count = 0;
+	}
+}
+
+static void __init board_cpm_setup(void)
+{
+	/* Stop unused module clocks here.
+	 * We have started all module clocks at arch/mips/jz4760b/setup.c.
+	 */
+}
+
+static void __init board_gpio_setup(void)
+{
+	/*
+	 * Initialize SDRAM pins
+	 */
+}
+
+static struct ft5x0x_ts_platform_data ft5x0x_ts_pdata = {
+	        .intr = GPIO_TS_I2C_INT,
+};
+static struct i2c_board_info lepus_i2c0_devs[] __initdata = {
+	{
+		I2C_BOARD_INFO("cm3511", 0x30),
+	},
+	{
+		I2C_BOARD_INFO("ov3640", 0x3c),
+	},
+	{
+		I2C_BOARD_INFO("ov7690", 0x21),
+	},
+	{
+	        I2C_BOARD_INFO(FT5X0X_NAME, 0x38),
+	       .irq = GPIO_TS_I2C_IRQ,
+	       .platform_data = &ft5x0x_ts_pdata,
+	},
+	{
+	},
+};
+/* SPI devices */
+struct spi_board_info jz4760b_spi0_board_info[]  = {
+	[0] = {
+		.modalias       = "spidev0",
+		.bus_num        = 0,
+		.chip_select    = 0,
+		.max_speed_hz   = 120000,
+/*		.platform_data	= &spitest,*/
+	},
+	[1] = {
+		.modalias       = "spitest",
+		.bus_num        = 0,
+		.chip_select    = 1,
+		.max_speed_hz   = 2500000,
+/*		.platform_data	= */
+	},
+};
+struct spi_board_info jz4760b_spi1_board_info[]  = {
+	[0] = {
+		.modalias       = "spidev1",
+		.bus_num        = 1,
+		.chip_select    = 0,
+		.max_speed_hz   = 12000000,
+	},
+};
+
+void __init board_i2c_init(void) {
+	i2c_register_board_info(0, lepus_i2c0_devs, ARRAY_SIZE(lepus_i2c0_devs));
+}
+void __init board_spi_init(void){
+	spi_register_board_info(jz4760b_spi0_board_info,ARRAY_SIZE(jz4760b_spi0_board_info));
+	spi_register_board_info(jz4760b_spi1_board_info,ARRAY_SIZE(jz4760b_spi1_board_info));
+}
+void __init jz_board_setup(void)
+{
+	printk("JZ4760B Lepus board setup\n");
+	board_cpm_setup();
+	board_gpio_setup();
+
+	jz_timer_callback = f4760b_timer_callback;
+}
+
+/**
+ * Called by arch/mips/kernel/proc.c when 'cat /proc/cpuinfo'.
+  */
+const char *get_board_type(void)
+{
+	return "Lepus";
+}
diff --git a/arch/mips/jz4760b/cpm.c b/arch/mips/jz4760b/cpm.c
new file mode 100644
index 00000000000..e39db4be839
--- /dev/null
+++ b/arch/mips/jz4760b/cpm.c
@@ -0,0 +1,531 @@
+/*
+ * linux/arch/mips/jz4760b/cpm.c
+ *
+ * jz4760b on-chip modules.
+ *
+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.
+ *
+ * Author: <whxu@ingenic.cn>
+ */
+
+#include <asm/jzsoc.h>
+#include <linux/module.h>
+
+
+#ifndef JZ_EXTAL
+#define JZ_EXTAL        (12 * 1000000)  /* 12MHz */
+#endif
+
+
+static unsigned int __get_clock_div(unsigned int val);
+
+/*
+ * Get clock div, such as CDIV, HDIV, PDIV, MDIV, H2DIV, SDIV.
+ * Convert the value read from register to the division ratio
+ */
+static unsigned int __get_clock_div(unsigned int val)
+{
+        unsigned int index;
+        unsigned int div[] = {1, 2, 3, 4, 6, 8};
+
+        if (val < (sizeof(div)/div[0]))
+                index = val;
+        else {
+                printk("WARNING: Invalid clock value %d!\n", val);
+                index = 0;
+        }
+
+        return div[index];
+}
+
+/*
+ * Get the external clock
+ */
+static unsigned int get_external_clock(void)
+{
+        return JZ_EXTAL;
+}
+
+/*
+ * Get the PLL clock
+ */
+unsigned int cpm_get_pllout(void)
+{
+        unsigned int exclk = get_external_clock();
+        unsigned int pll_stat, pll_ctrl, pllout;
+        unsigned int m, n, od, no;
+
+        pll_stat = INREG32(CPM_CPPSR);
+        if ((pll_stat & CPPSR_PLLBP) || (pll_stat & CPPSR_PLLOFF)) {
+                pllout = exclk;
+                return pllout;
+        }
+
+        pll_ctrl = INREG32(CPM_CPPCR0);
+        m = ((pll_ctrl & CPPCR0_PLLM_MASK) >> CPPCR0_PLLM_LSB) * 2;
+        n = (pll_ctrl & CPPCR0_PLLN_MASK) >> CPPCR0_PLLN_LSB;
+
+        od = (pll_ctrl & CPPCR0_PLLOD_MASK) >> CPPCR0_PLLOD_LSB;
+        no = 1 << od;
+        pllout = (exclk / (n * no)) * m;
+
+        return pllout;
+}
+EXPORT_SYMBOL(cpm_get_pllout);
+
+/*
+ * Get the PLL2 clock
+ */
+unsigned int cpm_get_pllout1(void)
+{
+        unsigned int clock_in, pll_ctrl, pll_out;
+        unsigned int m, n, od, no, val, div;
+
+        pll_ctrl = INREG32(CPM_CPPCR1);
+
+        if ( !(pll_ctrl & CPPCR1_PLL1ON)) {					/* pll1 off */
+            return 0;
+        }
+
+        if (pll_ctrl & CPPCR1_P1SCS) {
+                val = get_bf_value(pll_ctrl, CPPCR1_P1SDIV_LSB, CPPCR1_P1SDIV_MASK);
+                div = val + 1;
+                clock_in = cpm_get_pllout() / div;
+        } else
+                clock_in = get_external_clock();
+
+        if (pll_ctrl & CPPCR1_PLL1S) {
+                m = ((pll_ctrl & CPPCR1_PLL1M_MASK) >> CPPCR1_PLL1M_LSB) * 2;
+                n = (pll_ctrl & CPPCR1_PLL1N_MASK) >> CPPCR1_PLL1N_LSB;
+
+                od = (pll_ctrl & CPPCR1_PLL1OD_MASK) >> CPPCR1_PLL1OD_LSB;
+                no = 1 << od;
+                pll_out = (clock_in / (n * no)) * m;
+        } else {
+                pll_out = clock_in;
+        }
+
+        return pll_out;
+}
+EXPORT_SYMBOL(cpm_get_pllout1);
+
+/*
+ * Start the module clock
+ */
+void cpm_start_clock(clock_gate_module module_name)
+{
+        unsigned int cgr_index, module_index;
+
+	if (module_name == CGM_ALL_MODULE) {
+	        OUTREG32(CPM_CLKGR0, 0x0);
+	        OUTREG32(CPM_CLKGR1, 0x0);
+		return;
+	}
+
+        cgr_index = module_name / 32;
+        module_index = module_name % 32;
+        switch (cgr_index) {
+                case 0:
+                        CLRREG32(CPM_CLKGR0, 1 << module_index);
+                        break;
+                case 1:
+                        CLRREG32(CPM_CLKGR1, 1 << module_index);
+                        break;
+                default:
+                        printk("WARNING: can NOT start the %d's clock\n",
+                                        module_name);
+                        break;
+       }
+}
+EXPORT_SYMBOL(cpm_start_clock);
+
+/*
+ * Stop the module clock
+ */
+void cpm_stop_clock(clock_gate_module module_name)
+{
+        unsigned int cgr_index, module_index;
+
+        if (module_name == CGM_ALL_MODULE) {
+	        OUTREG32(CPM_CLKGR0, 0xffffffff);
+	        OUTREG32(CPM_CLKGR1, 0x3ff);
+		return;
+        }
+
+        cgr_index = module_name / 32;
+        module_index = module_name % 32;
+        switch (cgr_index) {
+                case 0:
+                        SETREG32(CPM_CLKGR0, 1 << module_index);
+                        break;
+
+                case 1:
+                        SETREG32(CPM_CLKGR1, 1 << module_index);
+                        break;
+
+                default:
+                        printk("WARNING: can NOT stop the %d's clock\n",
+                                        module_name);
+                        break;
+        }
+}
+EXPORT_SYMBOL(cpm_stop_clock);
+
+/*
+ * Get the clock, assigned by the clock_name, and the return value unit is Hz
+ */
+unsigned int cpm_get_clock(cgu_clock clock_name)
+{
+        unsigned int exclk = get_external_clock();
+        unsigned int pllclk = cpm_get_pllout();
+        unsigned int clock_ctrl = INREG32(CPM_CPCCR);
+        unsigned int clock_hz = exclk;
+        unsigned int val, tmp, div;
+
+        switch (clock_name) {
+        case CGU_CCLK:
+                val = get_bf_value(clock_ctrl, CPCCR_CDIV_LSB, CPCCR_CDIV_MASK);
+                div = __get_clock_div(val);
+                clock_hz = pllclk / div;
+
+                break;
+
+        case CGU_HCLK:
+                val = get_bf_value(clock_ctrl, CPCCR_HDIV_LSB, CPCCR_HDIV_MASK);
+                div = __get_clock_div(val);
+                clock_hz = pllclk / div;
+
+                break;
+
+        case CGU_PCLK:
+                val = get_bf_value(clock_ctrl, CPCCR_PDIV_LSB, CPCCR_PDIV_MASK);
+                div = __get_clock_div(val);
+                clock_hz = pllclk / div;
+
+                break;
+
+        case CGU_MCLK:
+                val = get_bf_value(clock_ctrl, CPCCR_MDIV_LSB, CPCCR_MDIV_MASK);
+                div = __get_clock_div(val);
+                clock_hz = pllclk / div;
+
+                break;
+
+        case CGU_H2CLK:
+                val = get_bf_value(clock_ctrl, CPCCR_H2DIV_LSB, CPCCR_H2DIV_MASK);
+                div = __get_clock_div(val);
+                clock_hz = pllclk / div;
+
+                break;
+
+        case CGU_SCLK:
+                val = get_bf_value(clock_ctrl, CPCCR_SDIV_LSB, CPCCR_SDIV_MASK);
+                div = __get_clock_div(val);
+                clock_hz = pllclk / div;
+
+                break;
+
+        case CGU_MSCCLK:
+                tmp = INREG32(CPM_MSCCDR);
+                val = get_bf_value(tmp, MSCCDR_MSCDIV_LSB, MSCCDR_MSCDIV_MASK);
+                div = val + 1;
+                if (tmp & MSCCDR_MCS) {
+                        if (clock_ctrl & CPCCR_PCS)
+                                clock_hz = pllclk / div;
+                        else
+                                clock_hz = (pllclk / 2) / div;
+                } else {
+                        clock_hz = exclk;
+                }
+
+                break;
+
+        case CGU_SSICLK:
+                tmp = INREG32(CPM_SSICDR);
+                val = get_bf_value(tmp, SSICDR_SSIDIV_LSB, SSICDR_SSIDIV_MASK);
+                div = val + 1;
+                if (tmp & SSICDR_SCS) {
+                        if (clock_ctrl & CPCCR_PCS)
+                                clock_hz = pllclk / div;
+                        else
+                                clock_hz = (pllclk / 2) / div;
+                } else {
+                        clock_hz = exclk;
+                }
+
+                break;
+
+        case CGU_CIMCLK:
+                tmp = INREG32(CPM_CIMCDR);
+                val = get_bf_value(tmp, CIMCDR_CIMDIV_LSB, CIMCDR_CIMDIV_MASK);
+                div = val + 1;
+                if (clock_ctrl & CPCCR_PCS)
+                        clock_hz = pllclk / div;
+                else
+                        clock_hz = (pllclk / 2) / div;
+
+                break;
+
+        case CGU_LPCLK:
+	case CGU_TVECLK:
+                tmp = INREG32(CPM_LPCDR);
+                val = get_bf_value(tmp, LPCDR_PIXDIV_LSB, LPCDR_PIXDIV_MASK);
+                div = val + 1;
+                if (tmp & LPCDR_LTCS) {
+                        if (tmp & LPCDR_LSCS)
+				clock_hz = exclk;
+			else {
+				if (tmp & LPCDR_LPCS)
+					clock_hz = cpm_get_pllout1() / div;
+				else
+					clock_hz = pllclk / div;
+			}
+                } else {
+                        if (tmp & LPCDR_LPCS)
+                                clock_hz = cpm_get_pllout1() / div;
+                        else
+                                clock_hz = pllclk / div;
+                }
+
+                break;
+
+        case CGU_I2SCLK:
+                tmp = INREG32(CPM_I2SCDR);
+                val = get_bf_value(tmp, CIMCDR_CIMDIV_LSB, CIMCDR_CIMDIV_MASK);
+                div = val + 1;
+                if (tmp & I2SCDR_I2CS) {
+                        if (tmp & I2SCDR_I2PCS)
+                                clock_hz = cpm_get_pllout1() / div;
+                        else
+                                clock_hz = pllclk / div;
+                } else {
+                        if (clock_ctrl & CPCCR_ECS)
+                                clock_hz = exclk / 2;
+                        else
+                                clock_hz = exclk;
+                }
+
+                break;
+
+        case CGU_PCMCLK:
+                tmp = INREG32(CPM_PCMCDR);
+                val = get_bf_value(tmp, PCMCDR_PCMDIV_LSB, PCMCDR_PCMDIV_MASK);
+                div = val + 1;
+                if (tmp & PCMCDR_PCMS) {
+                        if (tmp & PCMCDR_PCMPCS)
+                                clock_hz = cpm_get_pllout1() / div;
+                        else
+                                clock_hz = pllclk / div;
+                } else {
+                        if (clock_ctrl & CPCCR_ECS)
+                                clock_hz = exclk / 2;
+                        else
+                                clock_hz = exclk;
+                }
+
+                break;
+
+        case CGU_OTGCLK:
+                tmp = INREG32(CPM_USBCDR);
+                val = get_bf_value(tmp, USBCDR_OTGDIV_LSB, USBCDR_OTGDIV_MASK);
+                div = val + 1;
+                if (tmp & USBCDR_UCS) {
+                        if (tmp & USBCDR_UPCS)
+                                clock_hz = cpm_get_pllout1() / div;
+                        else
+                                clock_hz = pllclk / div;
+                } else {
+                        if (clock_ctrl & CPCCR_ECS)
+                                clock_hz = exclk / 2;
+                        else
+                                clock_hz = exclk;
+                }
+
+                break;
+
+        case CGU_UHCCLK:
+                tmp = INREG32(CPM_UHCCDR);
+                val = get_bf_value(tmp, UHCCDR_UHCDIV_LSB, UHCCDR_UHCDIV_MASK);
+                div = val + 1;
+                if (tmp & UHCCDR_UHPCS)
+                        clock_hz = cpm_get_pllout1() / div;
+                else
+                        clock_hz = pllclk / div;
+
+                break;
+
+        case CGU_GPSCLK:
+                tmp = INREG32(CPM_GPSCDR);
+                val = get_bf_value(tmp, GPSCDR_GPSDIV_LSB, GSPCDR_GPSDIV_MASK);
+                div = val + 1;
+                if (tmp & GPSCDR_GPCS)
+                        clock_hz = cpm_get_pllout1() / div;
+                else
+                        clock_hz = pllclk / div;
+
+                break;
+
+        case CGU_GPUCLK:
+                tmp = INREG32(CPM_GPUCDR);
+                val = get_bf_value(tmp, GPUCDR_GPUDIV_LSB, GPUCDR_GPUDIV_MASK);
+                div = val + 1;
+                if (tmp & GPUCDR_GPCS)
+                        clock_hz = cpm_get_pllout1() / div;
+                else
+                        clock_hz = pllclk / div;
+
+                break;
+
+        case CGU_UARTCLK:
+        case CGU_SADCCLK:
+                if (clock_ctrl & CPCCR_ECS)
+                        clock_hz = exclk / 2;
+                else
+                        clock_hz = exclk;
+
+                break;
+
+        case CGU_TCUCLK:
+                clock_hz = exclk;
+
+                break;
+
+        default:
+                printk("WARNING: can NOT get clock %d!\n", clock_name);
+                clock_hz = exclk;
+                break;
+        }
+
+        return clock_hz;
+}
+EXPORT_SYMBOL(cpm_get_clock);
+
+/*
+ * Check div value whether valid, if invalid, return the max valid value
+ */
+static unsigned int __check_div(unsigned int div, unsigned int lsb, unsigned int mask)
+{
+	if ((div << lsb) > mask) {
+		printk("WARNING: Invalid div %d larger than %d\n", div, mask >> lsb);
+		return mask >> lsb;
+	} else
+		return div;
+}
+
+/*
+ * Set the clock, assigned by the clock_name, and the return value unit is Hz,
+ * which means the actual clock
+ */
+#define ceil(v,div) ({ unsigned int val = 0; if(v % div ) val = v /div + 1; else val = v /div; val;})
+#define nearbyint(v,div) ({unsigned int val = 0; if((v % div) * 2 >= div)  val = v / div + 1;else val = v / div; val;})
+unsigned int cpm_set_clock(cgu_clock clock_name, unsigned int clock_hz)
+{
+        unsigned int actual_clock = 0;
+        unsigned int exclk = get_external_clock();
+        unsigned int pllclk = cpm_get_pllout();
+	unsigned int pllclk1 = cpm_get_pllout1();
+        unsigned int div;
+
+        if (!clock_hz)
+                return actual_clock;
+
+        switch (clock_name) {
+        case CGU_MSCCLK:
+                if (clock_hz == exclk) {
+			/* Select external clock as input*/
+                        CLRREG32(CPM_MSCCDR, MSCCDR_MCS);
+                } else {
+			div = ceil(pllclk , clock_hz) - 1;
+			div = __check_div(div, MSCCDR_MSCDIV_LSB, MSCCDR_MSCDIV_MASK);
+                        OUTREG32(CPM_MSCCDR, MSCCDR_MCS | div);
+                }
+
+		break;
+
+	case CGU_TVECLK:
+		if (clock_hz == exclk) {
+			/* Select external clock as input */
+			SETREG32(CPM_LPCDR, LPCDR_LSCS | LPCDR_LTCS);
+		} else {
+			div = nearbyint(pllclk1 , clock_hz) - 1;
+			div = __check_div(div, LPCDR_PIXDIV_LSB, LPCDR_PIXDIV_MASK);
+			/* Select pll1 clock as input */
+			OUTREG32(CPM_LPCDR, LPCDR_LTCS | LPCDR_LPCS | div);
+		}
+		break;
+
+	case CGU_LPCLK:
+		div = nearbyint(pllclk , clock_hz) - 1;
+		div = __check_div(div, LPCDR_PIXDIV_LSB, LPCDR_PIXDIV_MASK);
+		/* Select pll0 clock as input */
+		OUTREG32(CPM_LPCDR, div);
+		break;
+
+	case CGU_I2SCLK:
+		if (clock_hz == exclk) {
+			CLRREG32(CPM_CPCCR, CPCCR_ECS);
+			OUTREG32(CPM_I2SCDR, 0);
+		} else if (clock_hz == exclk/2) {
+			SETREG32(CPM_CPCCR, CPCCR_ECS);
+			OUTREG32(CPM_I2SCDR, 0);
+		} else {
+			div = nearbyint(pllclk , clock_hz) - 1;
+			div = __check_div(div, I2SCDR_I2SDIV_LSB, I2SCDR_I2SDIV_MASK);
+			OUTREG32(CPM_I2SCDR, I2SCDR_I2CS | div);
+		}
+		break;
+
+	case CGU_OTGCLK:
+		if (clock_hz == exclk) {
+			CLRREG32(CPM_CPCCR, CPCCR_ECS);
+			OUTREG32(CPM_USBCDR, 0);
+		} else if (clock_hz == exclk/2) {
+			SETREG32(CPM_CPCCR, CPCCR_ECS);
+			OUTREG32(CPM_USBCDR, 0);
+		} else {
+			div = nearbyint(pllclk , clock_hz) - 1;
+			div = __check_div(div, USBCDR_OTGDIV_LSB, USBCDR_OTGDIV_MASK);
+			OUTREG32(CPM_USBCDR, USBCDR_UCS | div);
+		}
+		break;
+
+	case CGU_RTCCLK:
+		SETREG32(CPM_OPCR, OPCR_ERCS);
+		break;
+
+	case CGU_CIMCLK:
+		div = ceil(pllclk , clock_hz) - 1;
+		div = __check_div(div, CIMCDR_CIMDIV_LSB, CIMCDR_CIMDIV_MASK);
+		OUTREG32(CPM_CIMCDR, div);
+		break;
+
+	case CGU_UHCCLK:
+		div = nearbyint(pllclk1 , clock_hz) - 1;
+		div = __check_div(div, UHCCDR_UHCDIV_LSB, UHCCDR_UHCDIV_MASK);
+		OUTREG32(CPM_UHCCDR, div | UHCCDR_UHPCS);
+		break;
+
+        default:
+                printk("WARNING: can NOT set clock %d!\n", clock_name);
+                break;
+        }
+
+        SETREG32(CPM_CPCCR, CPCCR_CE);
+        /* Get the actual clock */
+        actual_clock = cpm_get_clock(clock_name);
+
+        return actual_clock;
+}
+EXPORT_SYMBOL(cpm_set_clock);
+
+ /*
+  * Control UHC phy, if en is NON-ZERO, enable the UHC phy, otherwise disable
+  */
+void cpm_uhc_phy(unsigned int en)
+{
+	if (en)
+		CLRREG32(CPM_OPCR, OPCR_UHCPHY_DISABLE);
+	else
+		SETREG32(CPM_OPCR, OPCR_UHCPHY_DISABLE);
+}
+
diff --git a/arch/mips/jz4760b/cpufreq.c b/arch/mips/jz4760b/cpufreq.c
new file mode 100644
index 00000000000..432c1264e47
--- /dev/null
+++ b/arch/mips/jz4760b/cpufreq.c
@@ -0,0 +1,598 @@
+/*
+ * linux/arch/mips/jz4760b/cpufreq.c
+ *
+ * cpufreq driver for JZ4760B 
+ *
+ * Copyright (c) 2006-2008  Ingenic Semiconductor Inc.
+ * Author: <lhhuang@ingenic.cn>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+
+#include <linux/cpufreq.h>
+
+#include <asm/jzsoc.h>
+#include <asm/processor.h>
+
+#define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, \
+						"cpufreq-jz4760b", msg)
+
+#undef CHANGE_PLL
+
+#define PLL_UNCHANGED 0
+#define PLL_GOES_UP   1
+#define PLL_GOES_DOWN 2
+
+#define PLL_WAIT_500NS (500*(__cpm_get_cclk()/1000000000))
+
+/* Saved the boot-time parameters */
+static struct {
+	/* SDRAM parameters */
+	unsigned int mclk;  /* memory clock, KHz */
+	unsigned int tras;  /* RAS pulse width, cycles of mclk */
+	unsigned int rcd;   /* RAS to CAS Delay, cycles of mclk */
+	unsigned int tpc;   /* RAS Precharge time, cycles of mclk */
+	unsigned int trwl;  /* Write Precharge Time, cycles of mclk */
+	unsigned int trc;   /* RAS Cycle Time, cycles of mclk */
+	unsigned int rtcor; /* Refresh Time Constant */
+	unsigned int sdram_initialized;
+
+	/* LCD parameters */
+	unsigned int lcdpix_clk; /* LCD Pixel clock, Hz */
+	unsigned int lcd_clks_initialized;
+} boot_config;
+
+struct jz4760b_freq_percpu_info {
+	struct cpufreq_frequency_table table[7];
+};
+
+static struct jz4760b_freq_percpu_info jz4760b_freq_table;
+
+/*
+ * This contains the registers value for an operating point.
+ * If only part of a register needs to change then there is
+ * a mask value for that register.
+ * When going to a new operating point the current register
+ * value is ANDed with the ~mask and ORed with the new value.
+ */
+struct dpm_regs {
+	u32 cpccr;        /* Clock Freq Control Register */
+	u32 cpccr_mask;   /* Clock Freq Control Register mask */
+	u32 cppcr;        /* PLL1 Control Register */
+	u32 cppcr_mask;   /* PLL1 Control Register mask */
+	u32 pll_up_flag;  /* New PLL freq is higher than current or not */
+};
+
+extern jz_clocks_t jz_clocks;
+
+static void jz_update_clocks(void)
+{
+	/* Next clocks must be updated if we have changed 
+	 * the PLL or divisors.
+	 */
+	jz_clocks.cclk = __cpm_get_cclk();
+	jz_clocks.hclk = __cpm_get_hclk();
+	jz_clocks.mclk = __cpm_get_mclk();
+	jz_clocks.pclk = __cpm_get_pclk();
+	jz_clocks.pixclk = __cpm_get_pixclk();
+	jz_clocks.i2sclk = __cpm_get_i2sclk();
+	jz_clocks.usbclk = __cpm_get_usbclk();
+	jz_clocks.mscclk = __cpm_get_mscclk(0);
+}
+
+static void
+jz_init_boot_config(void)
+{
+	if (!boot_config.lcd_clks_initialized) {
+		/* the first time to scale pll */
+		boot_config.lcdpix_clk = __cpm_get_pixclk();
+		boot_config.lcd_clks_initialized = 1;
+	}
+
+	if (!boot_config.sdram_initialized) {
+		/* the first time to scale frequencies */
+		unsigned int dmcr, rtcor;
+		unsigned int tras, rcd, tpc, trwl, trc;
+		
+		dmcr = REG_EMC_DMCR;
+		rtcor = REG_EMC_RTCOR;
+
+		tras = (dmcr >> 13) & 0x7;
+		rcd = (dmcr >> 11) & 0x3;
+		tpc = (dmcr >> 8) & 0x7;
+		trwl = (dmcr >> 5) & 0x3;
+		trc = (dmcr >> 2) & 0x7;
+
+		boot_config.mclk = __cpm_get_mclk() / 1000;
+		boot_config.tras = tras + 4;
+		boot_config.rcd = rcd + 1;
+		boot_config.tpc = tpc + 1;
+		boot_config.trwl = trwl + 1;
+		boot_config.trc = trc * 2 + 1;
+		boot_config.rtcor = rtcor;
+
+		boot_config.sdram_initialized = 1;
+	}
+}
+
+static void jz_update_dram_rtcor(unsigned int new_mclk)
+{
+	unsigned int rtcor;
+	
+	new_mclk /= 1000;
+	rtcor = boot_config.rtcor * new_mclk / boot_config.mclk;
+	rtcor--;
+
+	if (rtcor < 1) rtcor = 1;
+	if (rtcor > 255) rtcor = 255;
+
+	REG_EMC_RTCOR = rtcor;
+	REG_EMC_RTCNT = rtcor;
+}
+
+static void jz_update_dram_dmcr(unsigned int new_mclk)
+{
+	unsigned int dmcr;
+	unsigned int tras, rcd, tpc, trwl, trc;
+	unsigned int valid_time, new_time; /* ns */
+
+	new_mclk /= 1000;
+	tras = boot_config.tras * new_mclk / boot_config.mclk;
+	rcd = boot_config.rcd * new_mclk / boot_config.mclk;
+	tpc = boot_config.tpc * new_mclk / boot_config.mclk;
+	trwl = boot_config.trwl * new_mclk / boot_config.mclk;
+	trc = boot_config.trc * new_mclk / boot_config.mclk;
+
+	/* Validation checking */
+	valid_time = (boot_config.tras * 1000000) / boot_config.mclk;
+	new_time = (tras * 1000000) / new_mclk;
+	if (new_time < valid_time) tras += 1;
+
+	valid_time = (boot_config.rcd * 1000000) / boot_config.mclk;
+	new_time = (rcd * 1000000) / new_mclk;
+	if (new_time < valid_time) rcd += 1;
+
+	valid_time = (boot_config.tpc * 1000000) / boot_config.mclk;
+	new_time = (tpc * 1000000) / new_mclk;
+	if (new_time < valid_time) tpc += 1;
+
+	valid_time = (boot_config.trwl * 1000000) / boot_config.mclk;
+	new_time = (trwl * 1000000) / new_mclk;
+	if (new_time < valid_time) trwl += 1;
+
+	valid_time = (boot_config.trc * 1000000) / boot_config.mclk;
+	new_time = (trc * 1000000) / new_mclk;
+	if (new_time < valid_time) trc += 2;
+
+	tras = (tras < 4) ? 4: tras;
+	tras = (tras > 11) ? 11: tras;
+	tras -= 4;
+
+	rcd = (rcd < 1) ? 1: rcd;
+	rcd = (rcd > 4) ? 4: rcd;
+	rcd -= 1;
+
+	tpc = (tpc < 1) ? 1: tpc;
+	tpc = (tpc > 8) ? 8: tpc;
+	tpc -= 1;
+
+	trwl = (trwl < 1) ? 1: trwl;
+	trwl = (trwl > 4) ? 4: trwl;
+	trwl -= 1;
+
+	trc = (trc < 1) ? 1: trc;
+	trc = (trc > 15) ? 15: trc;
+	trc /= 2;	
+
+	dmcr = REG_EMC_DMCR;
+	
+	dmcr &= ~(EMC_DMCR_TRAS_MASK | EMC_DMCR_RCD_MASK | EMC_DMCR_TPC_MASK | EMC_DMCR_TRWL_MASK | EMC_DMCR_TRC_MASK);
+	dmcr |= ((tras << EMC_DMCR_TRAS_BIT) | (rcd << EMC_DMCR_RCD_BIT) | (tpc << EMC_DMCR_TPC_BIT) | (trwl << EMC_DMCR_TRWL_BIT) | (trc << EMC_DMCR_TRC_BIT));
+
+	REG_EMC_DMCR = dmcr;
+}
+
+static void jz_update_dram_prev(unsigned int cur_mclk, unsigned int new_mclk)
+{	
+	/* No risk, no fun: run with interrupts on! */
+	if (new_mclk > cur_mclk) {
+		/* We're going FASTER, so first update TRAS, RCD, TPC, TRWL
+		 * and TRC of DMCR before changing the frequency.
+		 */
+		jz_update_dram_dmcr(new_mclk);
+	} else {
+		/* We're going SLOWER: first update RTCOR value
+		 * before changing the frequency.
+		 */
+		jz_update_dram_rtcor(new_mclk);
+	}
+}
+
+static void jz_update_dram_post(unsigned int cur_mclk, unsigned int new_mclk)
+{	
+	/* No risk, no fun: run with interrupts on! */
+	if (new_mclk > cur_mclk) {
+		/* We're going FASTER, so update RTCOR
+		 * after changing the frequency 
+		 */
+		jz_update_dram_rtcor(new_mclk);
+	} else {
+		/* We're going SLOWER: so update TRAS, RCD, TPC, TRWL
+		 * and TRC of DMCR after changing the frequency.
+		 */
+		jz_update_dram_dmcr(new_mclk);
+	}
+}
+
+static void jz_scale_divisors(struct dpm_regs *regs)
+{
+	unsigned int cpccr;
+	unsigned int cur_mclk, new_mclk;
+	int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
+	unsigned int tmp = 0, wait = PLL_WAIT_500NS; 
+
+	cpccr = REG_CPM_CPCCR;
+	cpccr &= ~((unsigned long)regs->cpccr_mask);
+	cpccr |= regs->cpccr;
+	cpccr |= CPM_CPCCR_CE;       /* update immediately */
+
+	cur_mclk = __cpm_get_mclk();
+	new_mclk = __cpm_get_pllout() / div[(cpccr & CPM_CPCCR_MDIV_MASK) >> CPM_CPCCR_MDIV_BIT];
+
+	/* Update some DRAM parameters before changing frequency */
+	jz_update_dram_prev(cur_mclk, new_mclk);
+
+	/* update register to change the clocks.
+	 * align this code to a cache line.
+	 */
+	__asm__ __volatile__(
+		".set noreorder\n\t"
+		".align 5\n"
+		"sw %1,0(%0)\n\t"
+		"li %3,0\n\t"
+		"1:\n\t"
+		"bne %3,%2,1b\n\t"
+		"addi %3, 1\n\t"
+		"nop\n\t"
+		"nop\n\t"
+		"nop\n\t"
+		"nop\n\t"
+		".set reorder\n\t"
+		:
+		: "r" (CPM_CPCCR), "r" (cpccr), "r" (wait), "r" (tmp));
+
+	/* Update some other DRAM parameters after changing frequency */
+	jz_update_dram_post(cur_mclk, new_mclk);
+}
+
+#ifdef CHANGE_PLL
+/* Maintain the LCD clock and pixel clock */
+static void jz_scale_lcd_divisors(struct dpm_regs *regs)
+{	
+	unsigned int new_pll, new_lcd_div, new_lcdpix_div;
+	unsigned int cpccr;
+	unsigned int tmp = 0, wait = PLL_WAIT_500NS; 
+
+	if (!boot_config.lcd_clks_initialized) return;
+
+	new_pll = __cpm_get_pllout();
+	new_lcd_div = new_pll / boot_config.lcd_clk;
+	new_lcdpix_div = new_pll / boot_config.lcdpix_clk;
+
+	if (new_lcd_div < 1)
+		new_lcd_div = 1;
+	if (new_lcd_div > 16)
+		new_lcd_div = 16;
+
+	if (new_lcdpix_div < 1)
+		new_lcdpix_div = 1;
+	if (new_lcdpix_div > 512)
+		new_lcdpix_div = 512;
+
+//	REG_CPM_CPCCR2 = new_lcdpix_div - 1;
+
+	cpccr = REG_CPM_CPCCR;
+	cpccr &= ~CPM_CPCCR_LDIV_MASK;
+	cpccr |= ((new_lcd_div - 1) << CPM_CPCCR_LDIV_BIT);
+	cpccr |= CPM_CPCCR_CE;       /* update immediately */
+
+	/* update register to change the clocks.
+	 * align this code to a cache line.
+	 */
+	__asm__ __volatile__(
+		".set noreorder\n\t"
+		".align 5\n"
+		"sw %1,0(%0)\n\t"
+		"li %3,0\n\t"
+		"1:\n\t"
+		"bne %3,%2,1b\n\t"
+		"addi %3, 1\n\t"
+		"nop\n\t"
+		"nop\n\t"
+		"nop\n\t"
+		"nop\n\t"
+		".set reorder\n\t"
+		:
+		: "r" (CPM_CPCCR), "r" (cpccr), "r" (wait), "r" (tmp));
+}
+
+static void jz_scale_pll(struct dpm_regs *regs)
+{
+	unsigned int cppcr;
+	unsigned int cur_mclk, new_mclk, new_pll;
+	int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
+	int od[] = {1, 2, 2, 4};
+
+	cppcr = REG_CPM_CPPCR;
+	cppcr &= ~(regs->cppcr_mask | CPM_CPPCR_PLLS | CPM_CPPCR_PLLEN | CPM_CPPCR_PLLST_MASK);
+	regs->cppcr &= ~CPM_CPPCR_PLLEN;
+	cppcr |= (regs->cppcr | 0xff);
+
+	/* Update some DRAM parameters before changing frequency */
+	new_pll = JZ_EXTAL * ((cppcr>>23)+2) / ((((cppcr>>18)&0x1f)+2) * od[(cppcr>>16)&0x03]);
+	cur_mclk = __cpm_get_mclk();
+	new_mclk = new_pll / div[(REG_CPM_CPCCR>>16) & 0xf];
+
+	/*
+	 * Update some SDRAM parameters
+	 */
+	jz_update_dram_prev(cur_mclk, new_mclk);
+
+	/* 
+	 * Update PLL, align code to cache line.
+	 */
+	cppcr |= CPM_CPPCR_PLLEN;
+	__asm__ __volatile__(
+		".set noreorder\n\t"
+		".align 5\n"
+		"sw %1,0(%0)\n\t"
+		"nop\n\t"
+		"nop\n\t"
+		"nop\n\t"
+		"nop\n\t"
+		"nop\n\t"
+		"nop\n\t"
+		"nop\n\t"
+		".set reorder\n\t"
+		:
+		: "r" (CPM_CPPCR), "r" (cppcr));
+
+	/* Update some other DRAM parameters after changing frequency */
+	jz_update_dram_post(cur_mclk, new_mclk);
+}
+#endif
+
+static void jz4760b_transition(struct dpm_regs *regs)
+{
+	/*
+	 * Get and save some boot-time conditions.
+	 */
+	jz_init_boot_config();
+
+#ifdef CHANGE_PLL
+	/* 
+	 * Disable LCD before scaling pll.
+	 * LCD and LCD pixel clocks should not be changed even if the PLL 
+	 * output frequency has been changed.
+	 */
+	REG_LCD_CTRL &= ~LCD_CTRL_ENA;
+
+	/*
+	 * Stop module clocks before scaling PLL
+	 */
+	__cpm_stop_eth();
+	__cpm_stop_aic(1);
+	__cpm_stop_aic(2);
+#endif
+
+	/* ... add more as necessary */
+
+	if (regs->pll_up_flag == PLL_GOES_UP) {
+		/* the pll frequency is going up, so change dividors first */
+		jz_scale_divisors(regs);
+#ifdef CHANGE_PLL
+		jz_scale_pll(regs);
+#endif
+	}
+	else if (regs->pll_up_flag == PLL_GOES_DOWN) {
+		/* the pll frequency is going down, so change pll first */
+#ifdef CHANGE_PLL
+		jz_scale_pll(regs);
+#endif
+		jz_scale_divisors(regs);
+	}
+	else {
+		/* the pll frequency is unchanged, so change divisors only */
+		jz_scale_divisors(regs);
+	}
+
+#ifdef CHANGE_PLL
+	/*
+	 * Restart module clocks before scaling PLL
+	 */
+	__cpm_start_eth();
+	__cpm_start_aic(1);
+	__cpm_start_aic(2);
+
+	/* ... add more as necessary */
+
+	/* Scale the LCD divisors after scaling pll */
+	if (regs->pll_up_flag != PLL_UNCHANGED) {
+		jz_scale_lcd_divisors(regs);
+	}
+
+	/* Enable LCD controller */
+	REG_LCD_CTRL &= ~LCD_CTRL_DIS;
+	REG_LCD_CTRL |= LCD_CTRL_ENA;
+#endif
+
+	/* Update system clocks */
+	jz_update_clocks();
+}
+
+extern unsigned int idle_times;
+static unsigned int jz4760b_freq_get(unsigned int cpu)
+{
+	return  (__cpm_get_cclk() / 1000);
+}
+
+static unsigned int index_to_divisor(unsigned int index, struct dpm_regs *regs)
+{
+	int n2FR[33] = {
+		0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0,
+		7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0,
+		9
+	};
+	int div[4] = {1, 2, 2, 2}; /* divisors of I:S:P:M */
+	unsigned int div_of_cclk, new_freq, i;
+
+	regs->pll_up_flag = PLL_UNCHANGED;
+	regs->cpccr_mask = CPM_CPCCR_CDIV_MASK | CPM_CPCCR_HDIV_MASK | CPM_CPCCR_PDIV_MASK | CPM_CPCCR_MDIV_MASK;
+
+	new_freq = jz4760b_freq_table.table[index].frequency;
+
+	do {
+		div_of_cclk = __cpm_get_pllout() / (1000 * new_freq);
+	} while (div_of_cclk==0);
+
+	if(div_of_cclk == 1 || div_of_cclk == 2 || div_of_cclk == 4) {
+		for(i = 1; i<4; i++) {
+			div[i] = 3;
+		}
+	} else {
+		for(i = 1; i<4; i++) {
+			div[i] = 2;
+		}
+	}
+
+	for(i = 0; i<4; i++) {
+		div[i] *= div_of_cclk;
+	}
+
+	dprintk("divisors of I:S:P:M = %d:%d:%d:%d\n", div[0], div[1], div[2], div[3]);
+
+	regs->cpccr = 
+		(n2FR[div[0]] << CPM_CPCCR_CDIV_BIT) | 
+		(n2FR[div[1]] << CPM_CPCCR_HDIV_BIT) | 
+		(n2FR[div[2]] << CPM_CPCCR_PDIV_BIT) |
+		(n2FR[div[3]] << CPM_CPCCR_MDIV_BIT);
+
+	return  div_of_cclk;
+}
+
+static void jz4760b_set_cpu_divider_index(unsigned int cpu, unsigned int index)
+{
+	unsigned long divisor, old_divisor;
+	struct cpufreq_freqs freqs;
+	struct dpm_regs regs;
+
+	old_divisor = __cpm_get_pllout() /  __cpm_get_cclk();
+	divisor = index_to_divisor(index, &regs);
+
+	freqs.old = __cpm_get_cclk() / 1000;
+	freqs.new =  __cpm_get_pllout() / (1000 * divisor);
+	freqs.cpu = cpu;
+
+	cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
+
+	if (old_divisor != divisor)
+		jz4760b_transition(&regs);
+
+	cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
+}
+
+static int jz4760b_freq_target(struct cpufreq_policy *policy,
+			  unsigned int target_freq,
+			  unsigned int relation)
+{
+	unsigned int new_index = 0;
+
+	if (cpufreq_frequency_table_target(policy,
+					   &jz4760b_freq_table.table[0],
+					   target_freq, relation, &new_index))
+		return -EINVAL;
+
+	jz4760b_set_cpu_divider_index(policy->cpu, new_index);
+
+	dprintk("new frequency is %d KHz (REG_CPM_CPCCR:0x%x)\n", __cpm_get_cclk() / 1000, REG_CPM_CPCCR);
+
+	return 0;
+}
+
+static int jz4760b_freq_verify(struct cpufreq_policy *policy)
+{
+	return cpufreq_frequency_table_verify(policy,
+					      &jz4760b_freq_table.table[0]);
+}
+
+static int __init jz4760b_cpufreq_driver_init(struct cpufreq_policy *policy)
+{
+
+	struct cpufreq_frequency_table *table =	&jz4760b_freq_table.table[0];
+	unsigned int MAX_FREQ;
+
+	dprintk(KERN_INFO "Jz4760b cpufreq driver\n");
+
+	if (policy->cpu != 0)
+		return -EINVAL;
+
+	policy->cur = MAX_FREQ = __cpm_get_cclk() / 1000; /* in kHz. Current and max frequency is determined by u-boot */
+	policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
+
+	policy->cpuinfo.min_freq = MAX_FREQ/8;
+	policy->cpuinfo.max_freq = MAX_FREQ;
+	policy->cpuinfo.transition_latency = 100000; /* in 10^(-9) s = nanoseconds */
+
+	table[0].index = 0;
+	table[0].frequency = MAX_FREQ/8;
+	table[1].index = 1;
+	table[1].frequency = MAX_FREQ/6;
+	table[2].index = 2;
+	table[2].frequency = MAX_FREQ/4;
+	table[3].index = 3;
+	table[3].frequency = MAX_FREQ/3;
+	table[4].index = 4;
+	table[4].frequency = MAX_FREQ/2;
+	table[5].index = 5;
+	table[5].frequency = MAX_FREQ;
+	table[6].index = 6;
+	table[6].frequency = CPUFREQ_TABLE_END;
+
+#ifdef CONFIG_CPU_FREQ_STAT_DETAILS
+	cpufreq_frequency_table_get_attr(table, policy->cpu); /* for showing /sys/devices/system/cpu/cpuX/cpufreq/stats/ */
+#endif
+
+	return  cpufreq_frequency_table_cpuinfo(policy, table);
+}
+
+static struct cpufreq_driver cpufreq_jz4760b_driver = {
+//	.flags		= CPUFREQ_STICKY,
+	.init		= jz4760b_cpufreq_driver_init,
+	.verify		= jz4760b_freq_verify,
+	.target		= jz4760b_freq_target,
+	.get		= jz4760b_freq_get,
+	.name		= "jz4760b",
+};
+
+static int __init jz4760b_cpufreq_init(void)
+{
+	return cpufreq_register_driver(&cpufreq_jz4760b_driver);
+}
+
+static void __exit jz4760b_cpufreq_exit(void)
+{
+	cpufreq_unregister_driver(&cpufreq_jz4760b_driver);
+}
+
+module_init(jz4760b_cpufreq_init);
+module_exit(jz4760b_cpufreq_exit);
+
+MODULE_AUTHOR("Regen <lhhuang@ingenic.cn>");
+MODULE_DESCRIPTION("cpufreq driver for Jz4760b");
+MODULE_LICENSE("GPL");
diff --git a/arch/mips/jz4760b/dma.c b/arch/mips/jz4760b/dma.c
new file mode 100644
index 00000000000..03c1ee1b0c0
--- /dev/null
+++ b/arch/mips/jz4760b/dma.c
@@ -0,0 +1,879 @@
+/*
+ * linux/arch/mips/jz4760b/dma.c
+ *
+ * Support functions for the JZ4760B internal DMA channels.
+ * No-descriptor transfer only.
+ * Descriptor transfer should also call jz_request_dma() to get a free
+ * channel and call jz_free_dma() to free the channel. And driver should
+ * build the DMA descriptor and setup the DMA channel by itself.
+ *
+ * Copyright (C) 2006 - 2008 Ingenic Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/sched.h>
+#include <linux/spinlock.h>
+#include <linux/string.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/soundcard.h>
+
+#include <asm/system.h>
+#include <asm/addrspace.h>
+#include <asm/jzsoc.h>
+
+/*
+ * A note on resource allocation:
+ *
+ * All drivers needing DMA channels, should allocate and release them
+ * through the public routines `jz_request_dma()' and `jz_free_dma()'.
+ *
+ * In order to avoid problems, all processes should allocate resources in
+ * the same sequence and release them in the reverse order.
+ *
+ * So, when allocating DMAs and IRQs, first allocate the DMA, then the IRQ.
+ * When releasing them, first release the IRQ, then release the DMA. The
+ * main reason for this order is that, if you are requesting the DMA buffer
+ * done interrupt, you won't know the irq number until the DMA channel is
+ * returned from jz_request_dma().
+ */
+
+struct jz_dma_chan jz_dma_table[MAX_DMA_NUM] = {
+	{ dev_id: DMA_ID_MSC0, },	/* DMAC0 channel 0, reserved for MSC0 */
+	{ dev_id: -1, },		/* DMAC0 channel 1 */
+	{ dev_id: -1, },		/* DMAC0 channel 2 */
+	{ dev_id: -1, },		/* DMAC0 channel 3 */
+	{ dev_id: -1, },		/* DMAC0 channel 4 */
+	{ dev_id: 0, },			/* DMAC0 channel 5 --- unavailable */
+
+	/* To avoid bug, reserved channel 6 & 7 for AIC_TX & AIC_RX */
+	{ dev_id: DMA_ID_AIC_TX, },	/* DMAC1 channel 0 */
+	{ dev_id: DMA_ID_AIC_RX, },	/* DMAC1 channel 1 */
+	{ dev_id: DMA_ID_MSC1, },	/* DMAC1 channel 2, reserved for MSC1 */
+	{ dev_id: -1, },		/* DMAC1 channel 3 */
+	{ dev_id: -1, },		/* DMAC0 channel 4 */
+	{ dev_id: 0, },			/* DMAC0 channel 5 --- unavailable */
+};
+
+// Device FIFO addresses and default DMA modes
+static const struct {
+	unsigned int fifo_addr;
+	unsigned int dma_mode;
+	unsigned int dma_source;
+} dma_dev_table[DMA_ID_MAX] = {
+	[DMA_ID_AUTO] = {0, DMA_AUTOINIT, DMAC_DRSR_RS_AUTO},
+//	{CPHYSADDR(TSSI_FIFO), DMA_32BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_TSSIIN},
+	[DMA_ID_UART3_TX] = {CPHYSADDR(UART3_TDR), DMA_8BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_UART3OUT},
+	[DMA_ID_UART3_RX] = {CPHYSADDR(UART3_RDR), DMA_8BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_UART3IN},
+	[DMA_ID_UART2_TX] = {CPHYSADDR(UART2_TDR), DMA_8BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_UART2OUT},
+	[DMA_ID_UART2_RX] = {CPHYSADDR(UART2_RDR), DMA_8BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_UART2IN},
+	[DMA_ID_UART1_TX] = {CPHYSADDR(UART1_TDR), DMA_8BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_UART1OUT},
+	[DMA_ID_UART1_RX] = {CPHYSADDR(UART1_RDR), DMA_8BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_UART1IN},
+	[DMA_ID_UART0_TX] = {CPHYSADDR(UART0_TDR), DMA_8BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_UART0OUT},
+	[DMA_ID_UART0_RX] = {CPHYSADDR(UART0_RDR), DMA_8BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_UART0IN},
+	[DMA_ID_SSI0_TX] = {CPHYSADDR(SSI_DR(0)), DMA_32BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_SSI0OUT},
+	[DMA_ID_SSI0_RX] = {CPHYSADDR(SSI_DR(0)), DMA_32BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_SSI0IN},
+
+	/*spdif used */
+	//{CPHYSADDR(SPDIF_FIFO), DMA_16BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_AICOUT},
+	/*aic unpack used*/
+	[DMA_ID_AIC_TX] = {CPHYSADDR(AIC_DR), DMA_AIC_TX_CMD_UNPACK | DMA_MODE_WRITE, DMAC_DRSR_RS_AICOUT},
+	/*aic pack used*/
+	//{CPHYSADDR(AIC_DR), DMA_AIC_TX_CMD_PACK | DMA_MODE_WRITE, DMAC_DRSR_RS_AICOUT},
+	[DMA_ID_AIC_RX] = {CPHYSADDR(AIC_DR), DMA_32BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_AICIN},
+	[DMA_ID_MSC0] = {0, 0, 0},
+	/* Just for compitable with SD8686 msc driver */
+	[DMA_ID_MSC0_TX] = {CPHYSADDR(MSC_TXFIFO(0)), DMA_32BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_MSC0OUT},
+	[DMA_ID_MSC0_RX] = {CPHYSADDR(MSC_RXFIFO(0)), DMA_32BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_MSC0IN},
+	[DMA_ID_TCU_OVERFLOW] = {0, DMA_AUTOINIT, DMAC_DRSR_RS_TCU},
+	[DMA_ID_SADC] = {CPHYSADDR(SADC_ADTCH), DMA_32BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_SADC},/* Touch Screen Data Register */
+	[DMA_ID_MSC1] = {0, 0, 0},
+	/* Just for compitable with SD8686 msc driver */
+	[DMA_ID_MSC1_TX] = {CPHYSADDR(MSC_TXFIFO(1)), DMA_32BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_MSC1OUT},
+	[DMA_ID_MSC1_RX] = {CPHYSADDR(MSC_RXFIFO(1)), DMA_32BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_MSC1IN},
+	[DMA_ID_MSC2] = {0, 0, 0},
+	/* Just for compitable with SD8686 msc driver */
+	[DMA_ID_MSC2_TX] = {CPHYSADDR(MSC_TXFIFO(2)), DMA_32BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_MSC2OUT},
+	[DMA_ID_MSC2_RX] = {CPHYSADDR(MSC_RXFIFO(2)), DMA_32BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_MSC2IN},
+	[DMA_ID_SSI1_TX] = {CPHYSADDR(SSI_DR(1)), DMA_32BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_SSI1OUT},
+	[DMA_ID_SSI1_RX] = {CPHYSADDR(SSI_DR(1)), DMA_32BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_SSI1IN},
+	[DMA_ID_PCM_TX] = {CPHYSADDR(PCM_PDP), DMA_16BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_PMOUT},
+	[DMA_ID_PCM_RX] = {CPHYSADDR(PCM_PDP), DMA_16BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_PMIN},
+	[DMA_ID_AX88796C_RX] = { 0, 0, 0 },
+	[DMA_ID_AX88796C_TX] = { 0, 0, 0 },
+	[DMA_ID_I2C0_RX] = { 0, 0, 0 },
+	[DMA_ID_I2C1_RX] = { 0, 0, 0 },
+	[DMA_ID_I2C2_RX] = { 0, 0, 0 },
+	[DMA_ID_I2C0_TX] = { 0, 0, 0 },
+	[DMA_ID_I2C1_TX] = { 0, 0, 0 },
+	[DMA_ID_I2C2_TX] = { 0, 0, 0 },
+};
+
+
+int jz_dma_read_proc(char *buf, char **start, off_t fpos,
+			 int length, int *eof, void *data)
+{
+	int i, len = 0;
+	struct jz_dma_chan *chan;
+
+	for (i = 0; i < MAX_DMA_NUM; i++) {
+		if ((chan = get_dma_chan(i)) != NULL) {
+			len += sprintf(buf + len, "%2d: %s\n",
+				       i, chan->dev_str);
+		}
+	}
+
+	if (fpos >= len) {
+		*start = buf;
+		*eof = 1;
+		return 0;
+	}
+	*start = buf + fpos;
+	if ((len -= fpos) > length)
+		return length;
+	*eof = 1;
+	return len;
+}
+
+
+void dump_jz_dma_channel(unsigned int dmanr)
+{
+	struct jz_dma_chan *chan;
+
+	if (dmanr > MAX_DMA_NUM)
+		return;
+	chan = &jz_dma_table[dmanr];
+
+	printk("DMA%d Registers:\n", dmanr);
+	printk("  DMACR  = 0x%08x\n", REG_DMAC_DMACR(chan->io/HALF_DMA_NUM));
+	printk("  DSAR   = 0x%08x\n", REG_DMAC_DSAR(dmanr));
+	printk("  DTAR   = 0x%08x\n", REG_DMAC_DTAR(dmanr));
+	printk("  DTCR   = 0x%08x\n", REG_DMAC_DTCR(dmanr));
+	printk("  DRSR   = 0x%08x\n", REG_DMAC_DRSR(dmanr));
+	printk("  DCCSR  = 0x%08x\n", REG_DMAC_DCCSR(dmanr));
+	printk("  DCMD  = 0x%08x\n", REG_DMAC_DCMD(dmanr));
+	printk("  DDA  = 0x%08x\n", REG_DMAC_DDA(dmanr));
+	printk("  DMADBR = 0x%08x\n", REG_DMAC_DMADBR(chan->io/HALF_DMA_NUM));
+}
+
+void dump_jz_bdma_channel(unsigned int dmanr)
+{
+	printk("\n----------chan%d----------------\n",dmanr);
+	printk("DSA: %x\n",REG_BDMAC_DSAR(dmanr));
+	printk("DTA: %x\n",REG_BDMAC_DTAR(dmanr));
+	printk("DTC: %x\n",REG_BDMAC_DTCR(dmanr));
+	printk("DRT: %x\n",REG_BDMAC_DRSR(dmanr));
+	printk("DCS: %x\n",REG_BDMAC_DCCSR(dmanr));
+	printk("DCM: %x\n",REG_BDMAC_DCMD(dmanr));
+	printk("DDA: %x\n",REG_BDMAC_DDA(dmanr));
+	printk("DSD: %x\n",REG_BDMAC_DSD(dmanr));
+	printk("DNT: %x\n",REG_BDMAC_DNT(dmanr));
+	printk("DMAC: %x\n",REG_BDMAC_DMACR);
+	printk("DIRQP: %x\n",REG_BDMAC_DMAIPR);
+	printk("DDR: %x\n",REG_BDMAC_DMADBR);
+	printk("DDRS: %x\n",REG_BDMAC_DMADBSR);
+	printk("DCKE: %x\n",REG_BDMAC_DMACKE);
+	printk("-------------------------\n");
+}
+
+
+/**
+ * jz_request_dma - dynamically allcate an idle DMA channel to return
+ * @dev_id: the specified dma device id or DMA_ID_RAW_SET
+ * @dev_str: the specified dma device string name
+ * @irqhandler: the irq handler, or NULL
+ * @irqflags: the irq handler flags
+ * @irq_dev_id: the irq handler device id for shared irq
+ *
+ * Finds a free channel, and binds the requested device to it.
+ * Returns the allocated channel number, or negative on error.
+ * Requests the DMA done IRQ if irqhandler != NULL.
+ *
+*/
+/*int jz_request_dma(int dev_id, const char *dev_str,
+		   void (*irqhandler)(int, void *, struct pt_regs *),
+		   unsigned long irqflags,
+		   void *irq_dev_id)
+*/
+
+int jz_request_dma(int dev_id, const char *dev_str,
+		   irqreturn_t (*irqhandler)(int, void *),
+		   unsigned long irqflags,
+		   void *irq_dev_id)
+{
+	struct jz_dma_chan *chan;
+	int i, ret;
+
+	if (dev_id < 0 || dev_id >= DMA_ID_MAX)
+		return -EINVAL;
+
+	for (i = 0; i < MAX_DMA_NUM; i++) {
+		    if (jz_dma_table[i].dev_id == dev_id)
+			    break;
+	}
+
+	if (i == MAX_DMA_NUM) {
+		for (i = 0; i < MAX_DMA_NUM; i++) {
+			if (jz_dma_table[i].dev_id < 0)
+				break;
+		}
+	}
+	if (i == MAX_DMA_NUM)  /* no free channel */
+		return -ENODEV;
+
+	/* we got a free channel */
+	chan = &jz_dma_table[i];
+
+	if (irqhandler) {
+		chan->irq = IRQ_DMA_0 + i;	// allocate irq number
+		chan->irq_dev = irq_dev_id;
+		if ((ret = request_irq(chan->irq, irqhandler, irqflags,
+				       dev_str, chan->irq_dev))) {
+			chan->irq = -1;
+			chan->irq_dev = NULL;
+			return ret;
+		}
+	} else {
+		chan->irq = -1;
+		chan->irq_dev = NULL;
+	}
+
+	// fill it in
+	chan->io = i;
+	chan->dev_id = dev_id;
+	chan->dev_str = dev_str;
+	chan->fifo_addr = dma_dev_table[dev_id].fifo_addr;
+	chan->mode = dma_dev_table[dev_id].dma_mode;
+	chan->source = dma_dev_table[dev_id].dma_source;
+
+	if (i < HALF_DMA_NUM) {
+		REG_DMAC_DMACKS(0) = 1 << i;
+	} else {
+		REG_DMAC_DMACKS(1) = 1 << (i - HALF_DMA_NUM);
+	}
+
+	return i;
+}
+
+void jz_free_dma(unsigned int dmanr)
+{
+	struct jz_dma_chan *chan = get_dma_chan(dmanr);
+
+	if (!chan) {
+		printk("Trying to free DMA%d\n", dmanr);
+		return;
+	}
+
+	disable_dma(dmanr);
+	if (chan->irq)
+		free_irq(chan->irq, chan->irq_dev);
+
+	chan->irq = -1;
+	chan->irq_dev = NULL;
+	chan->dev_id = -1;
+}
+
+void jz_set_dma_dest_width(int dmanr, int nbit)
+{
+	struct jz_dma_chan *chan = get_dma_chan(dmanr);
+
+	if (!chan)
+	       	return;
+
+	chan->mode &= ~DMAC_DCMD_DWDH_MASK;
+	switch (nbit) {
+	case 8:
+		chan->mode |= DMAC_DCMD_DWDH_8;
+		break;
+	case 16:
+		chan->mode |= DMAC_DCMD_DWDH_16;
+		break;
+	case 32:
+		chan->mode |= DMAC_DCMD_DWDH_32;
+		break;
+	}
+}
+
+void jz_set_dma_src_width(int dmanr, int nbit)
+{
+	struct jz_dma_chan *chan = get_dma_chan(dmanr);
+
+	if (!chan)
+	       	return;
+
+	chan->mode &= ~DMAC_DCMD_SWDH_MASK;
+	switch (nbit) {
+	case 8:
+		chan->mode |= DMAC_DCMD_SWDH_8;
+		break;
+	case 16:
+		chan->mode |= DMAC_DCMD_SWDH_16;
+		break;
+	case 32:
+		chan->mode |= DMAC_DCMD_SWDH_32;
+		break;
+	}
+}
+
+void jz_set_dma_block_size(int dmanr, int nbyte)
+{
+	struct jz_dma_chan *chan = get_dma_chan(dmanr);
+
+	if (!chan)
+		return;
+
+	chan->mode &= ~DMAC_DCMD_DS_MASK;
+	switch (nbyte) {
+	case 1:
+		chan->mode |= DMAC_DCMD_DS_8BIT;
+		break;
+	case 2:
+		chan->mode |= DMAC_DCMD_DS_16BIT;
+		break;
+	case 4:
+		chan->mode |= DMAC_DCMD_DS_32BIT;
+		break;
+	case 16:
+		chan->mode |= DMAC_DCMD_DS_16BYTE;
+		break;
+	case 32:
+		chan->mode |= DMAC_DCMD_DS_32BYTE;
+		break;
+	}
+}
+
+unsigned int jz_get_dma_command(int dmanr)
+{
+	struct jz_dma_chan *chan = get_dma_chan(dmanr);
+	return chan->mode;
+}
+
+/**
+ * jz_set_dma_mode - do the raw settings for the specified DMA channel
+ * @dmanr: the specified DMA channel
+ * @mode: dma operate mode, DMA_MODE_READ or DMA_MODE_WRITE
+ * @dma_mode: dma raw mode
+ * @dma_source: dma raw request source
+ * @fifo_addr: dma raw device fifo address
+ *
+ * Ensure call jz_request_dma(DMA_ID_RAW_SET, ...) first, then call
+ * jz_set_dma_mode() rather than set_dma_mode() if you work with
+ * and external request dma device.
+ *
+ * NOTE: Don not dynamically allocate dma channel if one external request
+ *       dma device will occupy this channel.
+*/
+int jz_set_dma_mode(unsigned int dmanr, unsigned int mode,
+		    unsigned int dma_mode, unsigned int dma_source,
+		    unsigned int fifo_addr)
+{
+	int dev_id, i;
+	struct jz_dma_chan *chan;
+
+	if (dmanr > MAX_DMA_NUM)
+		return -ENODEV;
+	for (i = 0; i < MAX_DMA_NUM; i++) {
+		if (jz_dma_table[i].dev_id < 0)
+			break;
+	}
+	if (i == MAX_DMA_NUM)
+		return -ENODEV;
+
+	chan = &jz_dma_table[dmanr];
+	dev_id = chan->dev_id;
+	if (dev_id > 0) {
+		printk(KERN_DEBUG "%s sets the allocated DMA channel %d!\n",
+		       __FUNCTION__, dmanr);
+		return -ENODEV;
+	}
+
+	/* clone it from the dynamically allocated. */
+	if (i != dmanr) {
+		chan->irq = jz_dma_table[i].irq;
+		chan->irq_dev = jz_dma_table[i].irq_dev;
+		chan->dev_str = jz_dma_table[i].dev_str;
+		jz_dma_table[i].irq = 0;
+		jz_dma_table[i].irq_dev = NULL;
+		jz_dma_table[i].dev_id = -1;
+	}
+	chan->dev_id = DMA_ID_RAW_SET;
+	chan->io = dmanr;
+	chan->fifo_addr = fifo_addr;
+	chan->mode = dma_mode;
+	chan->source = dma_source;
+
+	set_dma_mode(dmanr, dma_mode);
+
+	return dmanr;
+}
+
+void enable_dma(unsigned int dmanr)
+{
+	struct jz_dma_chan *chan = get_dma_chan(dmanr);
+
+	if (!chan)
+		return;
+
+	REG_DMAC_DCCSR(dmanr) &= ~(DMAC_DCCSR_HLT | DMAC_DCCSR_TT | DMAC_DCCSR_AR);
+	REG_DMAC_DCCSR(dmanr) |= DMAC_DCCSR_NDES; /* No-descriptor transfer */
+	__dmac_enable_channel(dmanr);
+	if (chan->irq)
+		__dmac_channel_enable_irq(dmanr);
+}
+
+#define DMA_DISABLE_POLL 0x10000
+
+void disable_dma(unsigned int dmanr)
+{
+	int i;
+	struct jz_dma_chan *chan = get_dma_chan(dmanr);
+
+	if (!chan)
+		return;
+
+	if (!__dmac_channel_enabled(dmanr))
+		return;
+
+	for (i = 0; i < DMA_DISABLE_POLL; i++)
+		if (__dmac_channel_transmit_end_detected(dmanr))
+			break;
+#if 0
+	if (i == DMA_DISABLE_POLL)
+		printk(KERN_INFO "disable_dma: poll expired!\n");
+#endif
+
+	__dmac_disable_channel(dmanr);
+	if (chan->irq)
+		__dmac_channel_disable_irq(dmanr);
+}
+
+/* Note: DMA_MODE_MASK is simulated by sw */
+void set_dma_mode(unsigned int dmanr, unsigned int mode)
+{
+	struct jz_dma_chan *chan = get_dma_chan(dmanr);
+
+	if (!chan)
+		return;
+
+	chan->mode |= mode & ~(DMAC_DCMD_SAI | DMAC_DCMD_DAI);
+	mode &= DMA_MODE_MASK;
+	if (mode == DMA_MODE_READ) {
+		chan->mode |= DMAC_DCMD_DAI;
+		chan->mode &= ~DMAC_DCMD_SAI;
+	} else if (mode == DMA_MODE_WRITE) {
+		chan->mode |= DMAC_DCMD_SAI;
+		chan->mode &= ~DMAC_DCMD_DAI;
+	} else {
+		printk(KERN_DEBUG "set_dma_mode() just supports DMA_MODE_READ or DMA_MODE_WRITE!\n");
+	}
+	REG_DMAC_DCMD(chan->io) = chan->mode & ~DMA_MODE_MASK;
+	REG_DMAC_DRSR(chan->io) = chan->source;
+}
+
+void set_dma_addr(unsigned int dmanr, unsigned int phyaddr)
+{
+	unsigned int mode;
+	struct jz_dma_chan *chan = get_dma_chan(dmanr);
+
+	if (!chan)
+		return;
+
+	mode = chan->mode & DMA_MODE_MASK;
+	if (mode == DMA_MODE_READ) {
+		REG_DMAC_DSAR(chan->io) = chan->fifo_addr;
+		REG_DMAC_DTAR(chan->io) = phyaddr;
+	} else if (mode == DMA_MODE_WRITE) {
+		REG_DMAC_DSAR(chan->io) = phyaddr;
+		REG_DMAC_DTAR(chan->io) = chan->fifo_addr;
+	} else
+		printk(KERN_DEBUG "Driver should call set_dma_mode() ahead set_dma_addr()!\n");
+}
+
+void set_dma_count(unsigned int dmanr, unsigned int bytecnt)
+{
+	struct jz_dma_chan *chan = get_dma_chan(dmanr);
+	int dma_ds[] = {4, 1, 2, 16, 32};
+	unsigned int ds;
+
+	if (!chan)
+	       	return;
+
+       	ds = (chan->mode & DMAC_DCMD_DS_MASK) >> DMAC_DCMD_DS_BIT;
+	REG_DMAC_DTCR(chan->io) = bytecnt / dma_ds[ds]; // transfer count
+}
+
+unsigned int get_dma_residue(unsigned int dmanr)
+{
+	unsigned int count, ds;
+	int dma_ds[] = {4, 1, 2, 16, 32};
+	struct jz_dma_chan *chan = get_dma_chan(dmanr);
+	if (!chan)
+		return 0;
+
+	ds = (chan->mode & DMAC_DCMD_DS_MASK) >> DMAC_DCMD_DS_BIT;
+	count = REG_DMAC_DTCR(chan->io);
+	count = count * dma_ds[ds];
+
+	return count;
+}
+
+void jz_set_oss_dma(unsigned int dmanr, unsigned int mode, unsigned int audio_fmt)
+{
+	struct jz_dma_chan *chan = get_dma_chan(dmanr);
+
+	if (!chan)
+		return;
+
+	switch (audio_fmt) {
+	case AFMT_U8:
+		/* burst mode : 32BIT */
+		break;
+	case AFMT_S16_LE:
+		/* burst mode : 16BYTE */
+		if (mode == DMA_MODE_READ) {
+			chan->mode = DMA_AIC_32_16BYTE_RX_CMD | DMA_MODE_READ;
+			chan->mode |= mode & ~(DMAC_DCMD_SAI | DMAC_DCMD_DAI);
+			mode &= DMA_MODE_MASK;
+			chan->mode |= DMAC_DCMD_DAI;
+			chan->mode &= ~DMAC_DCMD_SAI;
+		} else if (mode == DMA_MODE_WRITE) {
+			chan->mode = DMA_AIC_32_16BYTE_TX_CMD | DMA_MODE_WRITE;
+			//chan->mode = DMA_AIC_16BYTE_TX_CMD | DMA_MODE_WRITE;
+			chan->mode |= mode & ~(DMAC_DCMD_SAI | DMAC_DCMD_DAI);
+			mode &= DMA_MODE_MASK;
+			chan->mode |= DMAC_DCMD_SAI;
+			chan->mode &= ~DMAC_DCMD_DAI;
+		} else
+			printk("oss_dma_burst_mode() just supports DMA_MODE_READ or DMA_MODE_WRITE!\n");
+
+		REG_DMAC_DCMD(chan->io) = chan->mode & ~DMA_MODE_MASK;
+		REG_DMAC_DRSR(chan->io) = chan->source;
+		break;
+	}
+}
+
+void jz_set_alsa_dma(unsigned int dmanr, unsigned int mode, unsigned int audio_fmt)
+{
+	struct jz_dma_chan *chan = get_dma_chan(dmanr);
+
+	if (!chan)
+		return;
+
+	switch (audio_fmt) {
+	case 8:
+		/* SNDRV_PCM_FORMAT_S8 burst mode : 32BIT */
+		break;
+	case 16:
+		/* SNDRV_PCM_FORMAT_S16_LE burst mode : 16BYTE */
+		if (mode == DMA_MODE_READ) {
+			chan->mode = DMA_AIC_16BYTE_RX_CMD | DMA_MODE_READ;
+			chan->mode |= mode & ~(DMAC_DCMD_SAI | DMAC_DCMD_DAI);
+			mode &= DMA_MODE_MASK;
+			chan->mode |= DMAC_DCMD_DAI;
+			chan->mode &= ~DMAC_DCMD_SAI;
+		} else if (mode == DMA_MODE_WRITE) {
+			chan->mode = DMA_AIC_16BYTE_TX_CMD | DMA_MODE_WRITE;
+			chan->mode |= mode & ~(DMAC_DCMD_SAI | DMAC_DCMD_DAI);
+			mode &= DMA_MODE_MASK;
+			chan->mode |= DMAC_DCMD_SAI;
+			chan->mode &= ~DMAC_DCMD_DAI;
+		} else
+			printk("alsa_dma_burst_mode() just supports DMA_MODE_READ or DMA_MODE_WRITE!\n");
+
+		REG_DMAC_DCMD(chan->io) = chan->mode & ~DMA_MODE_MASK;
+		REG_DMAC_DRSR(chan->io) = chan->source;
+		break;
+	}
+}
+
+//#define JZ4760B_DMAC_TEST_ENABLE
+#undef JZ4760B_DMAC_TEST_ENABLE
+
+#ifdef JZ4760B_DMAC_TEST_ENABLE
+
+/*
+ * DMA test: external address <--> external address
+ */
+#define TEST_DMA_SIZE  16*1024
+
+static jz_dma_desc *dma_desc;
+
+static int dma_chan;
+static dma_addr_t dma_desc_phys_addr;
+static unsigned int dma_src_addr, dma_src_phys_addr, dma_dst_addr, dma_dst_phys_addr;
+
+static int dma_check_result(void *src, void *dst, int size)
+{
+	unsigned int addr1, addr2, i, err = 0;
+
+	addr1 = (unsigned int)src;
+	addr2 = (unsigned int)dst;
+
+	for (i = 0; i < size; i += 4) {
+		if (*(volatile unsigned int *)addr1 != *(volatile unsigned int *)addr2) {
+			err++;
+			printk("wrong data at 0x%08x: src 0x%08x  dst 0x%08x\n", addr2, *(volatile unsigned int *)addr1, *(volatile unsigned int *)addr2);
+		}
+		addr1 += 4;
+		addr2 += 4;
+	}
+	printk("check DMA result err=%d\n", err);
+	return err;
+}
+
+static irqreturn_t jz4760b_dma_irq(int irq, void *dev_id)
+{
+	printk("jz4760b_dma_irq %d\n", irq);
+
+
+	if (__dmac_channel_transmit_halt_detected(dma_chan)) {
+		printk("DMA HALT\n");
+		REG_DMAC_DCCSR(dma_chan) &= ~DMAC_DCCSR_EN;  /* disable DMA */
+		__dmac_channel_clear_transmit_halt(dma_chan);
+	}
+
+	if (__dmac_channel_address_error_detected(dma_chan)) {
+		printk("DMA ADDR ERROR\n");
+		REG_DMAC_DCCSR(dma_chan) &= ~DMAC_DCCSR_EN;  /* disable DMA */
+		REG_DMAC_DSAR(dma_chan) = 0; /* clear source address register */
+		REG_DMAC_DTAR(dma_chan) = 0; /* clear target address register */
+		__dmac_channel_clear_address_error(dma_chan);
+	}
+
+	if (__dmac_channel_descriptor_invalid_detected(dma_chan)) {
+		REG_DMAC_DCCSR(dma_chan) &= ~DMAC_DCCSR_EN;  /* disable DMA */
+		printk("DMA DESC INVALID\n");
+		__dmac_channel_clear_descriptor_invalid(dma_chan);
+	}
+
+	if (__dmac_channel_count_terminated_detected(dma_chan)) {
+		printk("DMA CT\n");
+		__dmac_channel_clear_count_terminated(dma_chan);
+	}
+
+	if (__dmac_channel_transmit_end_detected(dma_chan)) {
+		REG_DMAC_DCCSR(dma_chan) &= ~DMAC_DCCSR_EN;  /* disable DMA */
+		printk("DMA TT\n");
+		__dmac_channel_clear_transmit_end(dma_chan);
+		dump_jz_dma_channel(dma_chan);
+		dma_check_result((void *)dma_src_addr, (void *)dma_dst_addr, TEST_DMA_SIZE);
+	}
+
+	return IRQ_HANDLED;
+}
+
+void dma_nodesc_test(void)
+{
+	unsigned int addr, i;
+
+	printk("dma_nodesc_test\n");
+
+	/* Request DMA channel and setup irq handler */
+	dma_chan = jz_request_dma(DMA_ID_AUTO, "auto", jz4760b_dma_irq,
+				  IRQF_DISABLED, NULL);
+	if (dma_chan < 0) {
+		printk("Setup irq failed\n");
+		return;
+	}
+
+	printk("Requested DMA channel = %d\n", dma_chan);
+
+	/* Allocate DMA buffers */
+	dma_src_addr = __get_free_pages(GFP_KERNEL, 2); /* 16KB */
+	dma_dst_addr = __get_free_pages(GFP_KERNEL, 2); /* 16KB */
+
+	dma_src_phys_addr = CPHYSADDR(dma_src_addr);
+	dma_dst_phys_addr = CPHYSADDR(dma_dst_addr);
+
+	printk("Buffer addresses: 0x%08x 0x%08x 0x%08x 0x%08x\n",
+	       dma_src_addr, dma_src_phys_addr, dma_dst_addr, dma_dst_phys_addr);
+
+	/* Prepare data for source buffer */
+	addr = (unsigned int)dma_src_addr;
+	for (i = 0; i < TEST_DMA_SIZE; i += 4) {
+		*(volatile unsigned int *)addr = addr;
+		addr += 4;
+	}
+	dma_cache_wback((unsigned long)dma_src_addr, TEST_DMA_SIZE);
+
+	/* Init target buffer */
+	memset((void *)dma_dst_addr, 0, TEST_DMA_SIZE);
+	dma_cache_wback((unsigned long)dma_dst_addr, TEST_DMA_SIZE);
+
+	/* Init DMA module */
+	printk("Starting DMA\n");
+	REG_DMAC_DMACR(dma_chan/HALF_DMA_NUM) = 0;
+	REG_DMAC_DCCSR(dma_chan) = 0;
+	REG_DMAC_DRSR(dma_chan) = DMAC_DRSR_RS_AUTO;
+	REG_DMAC_DSAR(dma_chan) = dma_src_phys_addr;
+	REG_DMAC_DTAR(dma_chan) = dma_dst_phys_addr;
+	REG_DMAC_DTCR(dma_chan) = 512;
+	REG_DMAC_DCMD(dma_chan) = DMAC_DCMD_SAI | DMAC_DCMD_DAI | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 | DMAC_DCMD_DS_32BYTE | DMAC_DCMD_TIE;
+	REG_DMAC_DCCSR(dma_chan) = DMAC_DCCSR_NDES | DMAC_DCCSR_EN;
+	REG_DMAC_DMACR(dma_chan/HALF_DMA_NUM) = DMAC_DMACR_DMAE; /* global DMA enable bit */
+
+	/* wait a long time, ensure transfer end */
+	printk("wait 3s...\n");
+	mdelay(3000);		/* wait 3s */
+
+	REG_DMAC_DCCSR(dma_chan) &= ~DMAC_DCCSR_EN;  /* disable DMA */
+	/* free buffers */
+	printk("free DMA buffers\n");
+	free_pages(dma_src_addr, 2);
+	free_pages(dma_dst_addr, 2);
+
+	if (dma_desc)
+		free_pages((unsigned int)dma_desc, 0);
+
+	/* free dma */
+	jz_free_dma(dma_chan);
+}
+
+void dma_desc_test(void)
+{
+	unsigned int next, addr, i;
+	static jz_dma_desc *desc;
+
+	printk("dma_desc_test\n");
+
+	/* Request DMA channel and setup irq handler */
+	dma_chan = jz_request_dma(DMA_ID_AUTO, "auto", jz4760b_dma_irq,
+				  IRQF_DISABLED, NULL);
+	if (dma_chan < 0) {
+		printk("Setup irq failed\n");
+		return;
+	}
+
+	printk("Requested DMA channel = %d\n", dma_chan);
+
+	/* Allocate DMA buffers */
+	dma_src_addr = __get_free_pages(GFP_KERNEL, 2); /* 16KB */
+	dma_dst_addr = __get_free_pages(GFP_KERNEL, 2); /* 16KB */
+
+	dma_src_phys_addr = CPHYSADDR(dma_src_addr);
+	dma_dst_phys_addr = CPHYSADDR(dma_dst_addr);
+
+	printk("Buffer addresses: 0x%08x 0x%08x 0x%08x 0x%08x\n",
+	       dma_src_addr, dma_src_phys_addr, dma_dst_addr, dma_dst_phys_addr);
+
+	/* Prepare data for source buffer */
+	addr = (unsigned int)dma_src_addr;
+	for (i = 0; i < TEST_DMA_SIZE; i += 4) {
+		*(volatile unsigned int *)addr = addr;
+		addr += 4;
+	}
+	dma_cache_wback((unsigned long)dma_src_addr, TEST_DMA_SIZE);
+
+	/* Init target buffer */
+	memset((void *)dma_dst_addr, 0, TEST_DMA_SIZE);
+	dma_cache_wback((unsigned long)dma_dst_addr, TEST_DMA_SIZE);
+
+	/* Allocate DMA descriptors */
+	dma_desc = (jz_dma_desc *)__get_free_pages(GFP_KERNEL, 0);
+	dma_desc_phys_addr = CPHYSADDR((unsigned long)dma_desc);
+
+	printk("DMA descriptor address: 0x%08x  0x%08x\n", (u32)dma_desc, dma_desc_phys_addr);
+
+	/* Setup DMA descriptors */
+	desc = dma_desc;
+	next = (dma_desc_phys_addr + (sizeof(jz_dma_desc))) >> 4;
+
+	desc->dcmd = DMAC_DCMD_SAI | DMAC_DCMD_DAI | DMAC_DCMD_RDIL_IGN | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 | DMAC_DCMD_DS_32BYTE | DMAC_DCMD_DES_V | DMAC_DCMD_DES_VM | DMAC_DCMD_DES_VIE | DMAC_DCMD_TIE | DMAC_DCMD_LINK;
+	desc->dsadr = dma_src_phys_addr;    /* DMA source address */
+	desc->dtadr = dma_dst_phys_addr;    /* DMA target address */
+	desc->ddadr = (next << 24) + 128;    /* size: 128*32 bytes = 4096 bytes */
+
+	desc++;
+	next = (dma_desc_phys_addr + 2*(sizeof(jz_dma_desc))) >> 4;
+
+	desc->dcmd = DMAC_DCMD_SAI | DMAC_DCMD_DAI | DMAC_DCMD_RDIL_IGN | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 | DMAC_DCMD_DS_16BYTE | DMAC_DCMD_DES_V | DMAC_DCMD_DES_VM | DMAC_DCMD_DES_VIE | DMAC_DCMD_TIE | DMAC_DCMD_LINK;
+	desc->dsadr = dma_src_phys_addr + 4096;	/* DMA source address */
+	desc->dtadr = dma_dst_phys_addr + 4096;	/* DMA target address */
+	desc->ddadr = (next << 24) + 256;    /* size: 256*16 bytes = 4096 bytes */
+
+	desc++;
+	next = (dma_desc_phys_addr + 3*(sizeof(jz_dma_desc))) >> 4;
+
+	desc->dcmd = DMAC_DCMD_SAI | DMAC_DCMD_DAI | DMAC_DCMD_RDIL_IGN | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 | DMAC_DCMD_DS_16BYTE | DMAC_DCMD_DES_V | DMAC_DCMD_DES_VM | DMAC_DCMD_DES_VIE | DMAC_DCMD_TIE | DMAC_DCMD_LINK;
+	desc->dsadr = dma_src_phys_addr + 8192;	/* DMA source address */
+	desc->dtadr = dma_dst_phys_addr + 8192;	/* DMA target address */
+	desc->ddadr = (next << 24) + 256;    /* size: 256*16 bytes = 4096 bytes */
+
+	desc++;
+	next = (dma_desc_phys_addr + 4*(sizeof(jz_dma_desc))) >> 4;
+
+	desc->dcmd = DMAC_DCMD_SAI | DMAC_DCMD_DAI | DMAC_DCMD_RDIL_IGN | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 | DMAC_DCMD_DS_32BIT | DMAC_DCMD_DES_V | DMAC_DCMD_DES_VM | DMAC_DCMD_DES_VIE | DMAC_DCMD_TIE;
+	desc->dsadr = dma_src_phys_addr + 12*1024;	/* DMA source address */
+	desc->dtadr = dma_dst_phys_addr + 12*1024;	/* DMA target address */
+	desc->ddadr = (next << 24) + 1024;    /* size: 1024*4 bytes = 4096 bytes */
+
+	dma_cache_wback((unsigned long)dma_desc, 4*(sizeof(jz_dma_desc)));
+
+	/* Setup DMA descriptor address */
+	REG_DMAC_DDA(dma_chan) = dma_desc_phys_addr;
+
+	/* Setup request source */
+	REG_DMAC_DRSR(dma_chan) = DMAC_DRSR_RS_AUTO;
+
+	/* Setup DMA channel control/status register */
+	REG_DMAC_DCCSR(dma_chan) = DMAC_DCCSR_EN;	/* descriptor transfer, clear status, start channel */
+
+	/* Enable DMA */
+	REG_DMAC_DMACR(dma_chan/HALF_DMA_NUM) = DMAC_DMACR_DMAE;
+
+	/* DMA doorbell set -- start DMA now ... */
+	REG_DMAC_DMADBSR(dma_chan/HALF_DMA_NUM) = 1 << dma_chan;
+
+	/* wait a long time, ensure transfer end */
+	printk("wait 3s...\n");
+	mdelay(3000);		/* wait 3s */
+
+	REG_DMAC_DCCSR(dma_chan) &= ~DMAC_DCCSR_EN;  /* disable DMA */
+	/* free buffers */
+	printk("free DMA buffers\n");
+	free_pages(dma_src_addr, 2);
+	free_pages(dma_dst_addr, 2);
+
+	if (dma_desc)
+		free_pages((unsigned int)dma_desc, 0);
+
+	/* free dma */
+	jz_free_dma(dma_chan);
+}
+
+/*
+ * channel 0: read
+ * channel 1: write
+ * read and write are simutanously
+ */
+void dma_two_desc_test(void) {
+
+}
+
+#endif
+
+//EXPORT_SYMBOL_NOVERS(jz_dma_table);
+EXPORT_SYMBOL(jz_dma_table);
+EXPORT_SYMBOL(jz_request_dma);
+EXPORT_SYMBOL(jz_free_dma);
+EXPORT_SYMBOL(jz_set_dma_src_width);
+EXPORT_SYMBOL(jz_set_dma_dest_width);
+EXPORT_SYMBOL(jz_set_dma_block_size);
+EXPORT_SYMBOL(jz_set_dma_mode);
+EXPORT_SYMBOL(set_dma_mode);
+EXPORT_SYMBOL(jz_set_oss_dma);
+EXPORT_SYMBOL(jz_set_alsa_dma);
+EXPORT_SYMBOL(set_dma_addr);
+EXPORT_SYMBOL(set_dma_count);
+EXPORT_SYMBOL(get_dma_residue);
+EXPORT_SYMBOL(enable_dma);
+EXPORT_SYMBOL(disable_dma);
+EXPORT_SYMBOL(dump_jz_dma_channel);
diff --git a/arch/mips/jz4760b/fpu.c b/arch/mips/jz4760b/fpu.c
new file mode 100644
index 00000000000..a3bec625a4a
--- /dev/null
+++ b/arch/mips/jz4760b/fpu.c
@@ -0,0 +1,143 @@
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/ioport.h>
+#include <linux/mm.h>
+#include <linux/console.h>
+#include <linux/delay.h>
+
+#include <asm/cpu.h>
+#include <asm/bootinfo.h>
+#include <asm/mipsregs.h>
+#include <asm/reboot.h>
+
+#include <asm/asm.h>
+#include <asm/errno.h>
+#include <asm/fpregdef.h>
+#include <asm/mipsregs.h>
+#include <asm/asm-offsets.h>
+#include <asm/regdef.h>
+
+#include <asm/jzsoc.h>
+
+void jz4760b_fpu_dump(void)
+{
+	unsigned int fgpr[32];
+	unsigned int fscr, fir, i;
+
+	for (i = 0; i < 32; i ++)
+		fgpr[i] = 0xdeadbeef;
+
+	__asm__ __volatile__(
+		"swc1 $f0, 0(%0)\n\t"
+		"swc1 $f1, 4(%0)\n\t"
+		"swc1 $f2, 8(%0)\n\t"
+		"swc1 $f3, 12(%0)\n\t"
+		"swc1 $f4, 16(%0)\n\t"
+		"swc1 $f4, 20(%0)\n\t"
+		"swc1 $f6, 24(%0)\n\t"
+		"swc1 $f6, 28(%0)\n\t"
+		"swc1 $f8, 32(%0)\n\t"
+		"swc1 $f9, 36(%0)\n\t"
+		"swc1 $f10, 40(%0)\n\t"
+		"swc1 $f11, 44(%0)\n\t"
+		"swc1 $f12, 48(%0)\n\t"
+		"swc1 $f13, 52(%0)\n\t"
+		"swc1 $f14, 56(%0)\n\t"
+		"swc1 $f15, 60(%0)\n\t"
+		"swc1 $f16, 64(%0)\n\t"
+		"swc1 $f17, 68(%0)\n\t"
+		"swc1 $f18, 72(%0)\n\t"
+		"swc1 $f19, 76(%0)\n\t"
+		"swc1 $f20, 80(%0)\n\t"
+		"swc1 $f21, 84(%0)\n\t"
+		"swc1 $f22, 88(%0)\n\t"
+		"swc1 $f23, 92(%0)\n\t"
+		"swc1 $f24, 96(%0)\n\t"
+		"swc1 $f25, 100(%0)\n\t"
+		"swc1 $f26, 104(%0)\n\t"
+		"swc1 $f27, 108(%0)\n\t"
+		"swc1 $f28, 112(%0)\n\t"
+		"swc1 $f29, 116(%0)\n\t"
+		"swc1 $f30, 120(%0)\n\t"
+		"swc1 $f31, 124(%0)\n\t"
+		:
+		:"r"(fgpr)
+	);
+
+	/* Get FPU control and status register */
+	__asm__ __volatile__(
+		"cfc1	%0, $31 \n\t"
+		:"=r"(fscr)
+		:
+	);
+
+	/* Get FPU implementation and revision register */
+	__asm__ __volatile__(
+		"cfc1	%0, $0 \n\t"
+		:"=r"(fir)
+		:
+	);
+
+	printk("Dump of FPU: \n");
+
+	for (i = 0; i < 32; i += 4)
+		printk("%08x %08x %08x %08x \n",
+		       fgpr[i],fgpr[i+1],fgpr[i+2],fgpr[i+3]);
+	printk("FPU control and status register          = %08x \n",fscr);
+	printk("FPU implementation and revision register = %08x \n",fir);
+
+	fscr |= 0x11;
+
+	__asm__ __volatile__(
+		"ctc1	%0, $31 \n\t"
+		:
+		:"r"(fscr)
+	);
+	__asm__ __volatile__(
+		"cfc1	%0, $31 \n\t"
+		:"=r"(fscr)
+		:
+	);
+	printk("FPU control and status register          = %08x \n",fscr);
+}
+
+void jz4760b_fpu_init(unsigned int round)
+{
+	unsigned int tmp;
+
+	__asm__ __volatile__(
+		"cfc1	%0, $31 \n\t"
+		:"=r"(tmp)
+		:
+	);
+
+//	printk("original jz4760b FCSR value: %8x\n",tmp);
+
+	tmp = 0x0;
+	/* Jz4760b FPU init */
+	/* disable any exception */
+	tmp |= (0x0 << 7);
+	/* Set ronud mode */
+	tmp &= ~0x3;
+	tmp |= (round & 0x3);
+
+//	printk("plan to set jz4760b FPU FCSR to %08x \n",tmp);
+	__asm__ __volatile__(
+		"ctc1	%0, $28 \n\t"
+		:
+		:"r"(tmp)
+	);
+
+	__asm__ __volatile__(
+		"cfc1	%0, $31 \n\t"
+		:"=r"(tmp)
+		:
+	);
+
+//	printk("jz4760b FCSR value after setting: %8x\n",tmp);
+
+}
+
+EXPORT_SYMBOL(jz4760b_fpu_init);
diff --git a/arch/mips/jz4760b/gpiolib.c b/arch/mips/jz4760b/gpiolib.c
new file mode 100644
index 00000000000..ba3dc3d1e80
--- /dev/null
+++ b/arch/mips/jz4760b/gpiolib.c
@@ -0,0 +1,208 @@
+
+/* arch/mips/jz4760b/gpiolib.c
+ *
+ *	hlguo <hlguo@ingenic.cn>
+ *
+ * jz4760b GPIOlib support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+*/
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+
+#include <asm/irq.h>
+#include <asm/io.h>
+#include <asm/jzsoc.h>
+#include <asm/gpio.h>
+
+#include <linux/gpio.h>
+
+struct jz4760b_gpio_chip {
+	struct gpio_chip	chip;
+	void __iomem		*base;
+};
+
+static inline struct jz4760b_gpio_chip *to_jz4760b_chip(struct gpio_chip *gpc)
+{
+	return container_of(gpc, struct jz4760b_gpio_chip, chip);
+}
+
+static void jz4760b_gpiolib_set(struct gpio_chip *chip,
+				unsigned offset, int value)
+{
+       	unsigned long flags;
+	unsigned int n = 0;
+
+	n = chip->base + offset;	
+	local_irq_save(flags);
+	if (value)
+		__gpio_set_pin(n);
+	else
+		__gpio_clear_pin(n);
+	local_irq_restore(flags);	
+}
+
+static int jz4760b_gpiolib_get(struct gpio_chip *chip, unsigned offset)
+{
+       	unsigned long flags;
+	unsigned int n = 0;
+	int state = -1;
+
+	n = chip->base + offset;
+	local_irq_save(flags);
+	state = __gpio_get_pin(n);
+	local_irq_restore(flags);
+	return state;
+	
+}
+
+static int jz4760b_gpiolib_input(struct gpio_chip *chip, unsigned offset)
+{
+       	unsigned long flags;
+	unsigned int n = 0;
+
+	n = chip->base + offset;
+	local_irq_save(flags);
+	__gpio_as_input(n);	
+	local_irq_restore(flags);
+	return 0;
+}
+
+static int jz4760b_gpiolib_output(struct gpio_chip *chip,
+					unsigned offset, int value)
+{
+	unsigned long flags;
+	unsigned int n = 0;
+
+	n = chip->base + offset;	
+	local_irq_save(flags);
+	__gpio_as_output(n);
+	if (value)
+		__gpio_set_pin(n);
+	else
+		__gpio_clear_pin(n);
+	local_irq_restore(flags);
+	return 0;
+}
+
+static int jz4760b_gpio_request(struct gpio_chip *chip, unsigned offset)
+{
+	return 0;
+}
+
+static void jz4760b_gpio_free(struct gpio_chip *chip, unsigned offset)
+{
+	return;
+}
+
+static struct jz4760b_gpio_chip jz4760b_gpios[] = {
+	[0] = {
+		.base	= (unsigned *)GPIO_BASEA,
+		.chip	= {
+			.base			= 0*32,
+			.owner			= THIS_MODULE,
+			.label			= "GPIOA",
+			.ngpio			= 32,
+			.direction_input	= jz4760b_gpiolib_input,
+			.direction_output	= jz4760b_gpiolib_output,
+			.set			= jz4760b_gpiolib_set,
+			.get			= jz4760b_gpiolib_get,
+			.request		= jz4760b_gpio_request,
+			.free			= jz4760b_gpio_free,
+		},
+	},
+	[1] = {
+		.base	= (unsigned *)GPIO_BASEB,
+		.chip	= {
+			.base			= 1*32,
+			.owner			= THIS_MODULE,
+			.label			= "GPIOB",
+		       	.ngpio			= 32,
+			.direction_input	= jz4760b_gpiolib_input,
+			.direction_output	= jz4760b_gpiolib_output,
+			.set			= jz4760b_gpiolib_set,
+			.get			= jz4760b_gpiolib_get,
+			.request		= jz4760b_gpio_request,
+			.free			= jz4760b_gpio_free,
+		},
+	},
+	[2] = {
+		.base	= (unsigned *)GPIO_BASEC,
+		.chip	= {
+			.base			= 2*32,
+			.owner			= THIS_MODULE,
+			.label			= "GPIOC",
+		       	.ngpio			= 32,
+			.direction_input	= jz4760b_gpiolib_input,
+			.direction_output	= jz4760b_gpiolib_output,
+			.set			= jz4760b_gpiolib_set,
+			.get			= jz4760b_gpiolib_get,
+			.request		= jz4760b_gpio_request,
+			.free			= jz4760b_gpio_free,
+		},
+	},
+	[3] = {
+		.base	= (unsigned *)GPIO_BASED,
+		.chip	= {
+			.base			= 3*32,
+			.owner			= THIS_MODULE,
+			.label			= "GPIOD",
+		       	.ngpio			= 32,
+			.direction_input	= jz4760b_gpiolib_input,
+			.direction_output	= jz4760b_gpiolib_output,
+			.set			= jz4760b_gpiolib_set,
+			.get			= jz4760b_gpiolib_get,
+			.request		= jz4760b_gpio_request,
+			.free			= jz4760b_gpio_free,
+		},
+	},
+	[4] = {
+		.base	= (unsigned *)GPIO_BASEE,
+		.chip	= {
+			.base			= 4*32,
+			.label			= "GPIOE",
+			.owner			= THIS_MODULE,
+		       	.ngpio			= 32,
+			.direction_input	= jz4760b_gpiolib_input,
+			.direction_output	= jz4760b_gpiolib_output,
+			.set			= jz4760b_gpiolib_set,
+			.get			= jz4760b_gpiolib_get,
+			.request		= jz4760b_gpio_request,
+			.free			= jz4760b_gpio_free,
+		},
+	},
+	[5] = {
+		.base	= (unsigned *)GPIO_BASEF,
+		.chip	= {
+			.base			= 5*32,
+			.owner			= THIS_MODULE,
+			.label			= "GPIOF",
+		       	.ngpio			= 32,
+			.direction_input	= jz4760b_gpiolib_input,
+			.direction_output	= jz4760b_gpiolib_output,
+			.set			= jz4760b_gpiolib_set,
+			.get			= jz4760b_gpiolib_get,
+			.request		= jz4760b_gpio_request,
+			.free			= jz4760b_gpio_free,
+		},
+	},
+};
+
+static __init int jz4760b_gpiolib_init(void)
+{
+	struct jz4760b_gpio_chip *chip = jz4760b_gpios;
+	int gpn;
+
+	for (gpn = 0; gpn < ARRAY_SIZE(jz4760b_gpios); gpn++, chip++)
+		gpiochip_add(&chip->chip);
+
+	return 0;
+}
+
+arch_initcall(jz4760b_gpiolib_init);
diff --git a/arch/mips/jz4760b/i2c.c b/arch/mips/jz4760b/i2c.c
new file mode 100644
index 00000000000..e7575a7150e
--- /dev/null
+++ b/arch/mips/jz4760b/i2c.c
@@ -0,0 +1,273 @@
+/*
+ * linux/arch/mips/jz4760b/i2c.c
+ * 
+ * Jz4760b I2C routines.
+ * 
+ * Copyright (C) 2005,2006 Ingenic Semiconductor Inc.
+ * Author: <lhhuang@ingenic.cn>
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ */
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/delay.h>
+#include <asm/uaccess.h>
+#include <asm/addrspace.h>
+
+#include <asm/jzsoc.h>
+
+/* I2C protocol */
+#define I2C_READ	1
+#define I2C_WRITE	0
+
+#define TIMEOUT         1000
+
+/*
+ * I2C bus protocol basic routines
+ */
+static int i2c_put_data(unsigned char data)
+{
+	unsigned int timeout = TIMEOUT*10;
+
+	__i2c_write(data);
+	__i2c_set_drf();
+	while (__i2c_check_drf() != 0);
+	while (!__i2c_transmit_ended());
+	while (!__i2c_received_ack() && timeout)
+		timeout--;
+
+	if (timeout)
+		return 0;
+	else
+		return -ETIMEDOUT;
+}
+
+#ifdef CONFIG_JZ_TPANEL_ATA2508
+static int i2c_put_data_nack(unsigned char data)
+{
+	unsigned int timeout = TIMEOUT*10;
+
+	__i2c_write(data);
+	__i2c_set_drf();
+	while (__i2c_check_drf() != 0);
+	while (!__i2c_transmit_ended());
+	while (timeout--);
+		return 0;
+}
+#endif
+
+static int i2c_get_data(unsigned char *data, int ack)
+{
+	int timeout = TIMEOUT*10;
+
+	if (!ack)
+		__i2c_send_nack();
+	else
+		__i2c_send_ack();
+
+	while (__i2c_check_drf() == 0 && timeout)
+		timeout--;
+
+	if (timeout) {
+		if (!ack)
+			__i2c_send_stop();
+		*data = __i2c_read();
+		__i2c_clear_drf();
+		return 0;
+	} else
+		return -ETIMEDOUT;
+}
+
+/*
+ * I2C interface
+ */
+void i2c_open(void)
+{
+	__i2c_set_clk(jz_clocks.extalclk, 10000); /* default 10 KHz */
+	__i2c_enable();
+}
+
+void i2c_close(void)
+{
+	udelay(300); /* wait for STOP goes over. */
+	__i2c_disable();
+}
+
+void i2c_setclk(unsigned int i2cclk)
+{
+	__i2c_set_clk(jz_clocks.extalclk, i2cclk);
+}
+
+int i2c_lseek(unsigned char device, unsigned char offset)
+{
+	__i2c_send_nack();	/* Master does not send ACK, slave sends it */
+	__i2c_send_start();
+	if (i2c_put_data( (device << 1) | I2C_WRITE ) < 0)
+		goto device_err;
+	if (i2c_put_data(offset) < 0)
+		goto address_err;
+	return 0;
+ device_err:
+	printk(KERN_DEBUG "No I2C device (0x%02x) installed.\n", device);
+	__i2c_send_stop();
+	return -ENODEV;
+ address_err:
+	printk(KERN_DEBUG "No I2C device (0x%02x) response.\n", device);
+	__i2c_send_stop();
+	return -EREMOTEIO;
+}
+
+int i2c_read(unsigned char device, unsigned char *buf,
+	       unsigned char address, int count)
+{
+	int cnt = count;
+	int timeout = 5;
+
+L_try_again:
+
+	if (timeout < 0)
+		goto L_timeout;
+
+	__i2c_send_nack();	/* Master does not send ACK, slave sends it */
+	__i2c_send_start();
+	if (i2c_put_data( (device << 1) | I2C_WRITE ) < 0)
+		goto device_werr;
+	if (i2c_put_data(address) < 0)
+		goto address_err;
+
+	__i2c_send_start();
+	if (i2c_put_data( (device << 1) | I2C_READ ) < 0)
+		goto device_rerr;
+	__i2c_send_ack();	/* Master sends ACK for continue reading */
+	while (cnt) {
+		if (cnt == 1) {
+			if (i2c_get_data(buf, 0) < 0)
+				break;
+		} else {
+			if (i2c_get_data(buf, 1) < 0)
+				break;
+		}
+		cnt--;
+		buf++;
+	}
+
+	__i2c_send_stop();
+	return count - cnt;
+ device_rerr:
+ device_werr:
+ address_err:
+	timeout --;
+	__i2c_send_stop();
+	goto L_try_again;
+
+L_timeout:
+	__i2c_send_stop();
+	printk("Read I2C device 0x%2x failed.\n", device);
+	return -ENODEV;
+}
+
+int i2c_write(unsigned char device, unsigned char *buf,
+		unsigned char address, int count)
+{
+	int cnt = count;
+	int cnt_in_pg;
+	int timeout = 5;
+	unsigned char *tmpbuf;
+	unsigned char tmpaddr;
+
+	__i2c_send_nack();	/* Master does not send ACK, slave sends it */
+
+ W_try_again:
+	if (timeout < 0)
+		goto W_timeout;
+
+	cnt = count;
+	tmpbuf = (unsigned char *)buf;
+	tmpaddr = address;
+
+ start_write_page:
+	cnt_in_pg = 0;
+	__i2c_send_start();
+	if (i2c_put_data( (device << 1) | I2C_WRITE ) < 0)
+		goto device_err;
+#ifdef CONFIG_JZ_TPANEL_ATA2508
+	if (address == 0xff) {
+		if (i2c_put_data_nack(tmpaddr) < 0)
+			goto address_err;
+		while (cnt) {
+			if (++cnt_in_pg > 8) {
+				__i2c_send_stop();
+				mdelay(1);
+				tmpaddr += 8;
+				goto start_write_page;
+			}
+			if (i2c_put_data_nack(*tmpbuf) < 0)
+				break;
+			cnt--;
+			tmpbuf++;
+		}
+	}
+	else {
+
+		if (i2c_put_data(tmpaddr) < 0)
+			goto address_err;
+		while (cnt) {
+			if (++cnt_in_pg > 8) {
+				__i2c_send_stop();
+				mdelay(1);
+				tmpaddr += 8;
+				goto start_write_page;
+			}
+			if (i2c_put_data(*tmpbuf) < 0)
+				break;
+			cnt--;
+			tmpbuf++;
+		}
+	}
+#else
+	if (i2c_put_data(tmpaddr) < 0)
+		goto address_err;
+	while (cnt) {
+		if (++cnt_in_pg > 8) {
+			__i2c_send_stop();
+			mdelay(1);
+			tmpaddr += 8;
+			goto start_write_page;
+		}
+		if (i2c_put_data(*tmpbuf) < 0)
+			break;
+		cnt--;
+		tmpbuf++;
+	}
+#endif
+	__i2c_send_stop();
+	return count - cnt;
+ device_err:
+ address_err:
+	timeout--;
+	__i2c_send_stop();
+	goto W_try_again;
+
+ W_timeout:
+	printk(KERN_DEBUG "Write I2C device 0x%2x failed.\n", device);
+	__i2c_send_stop();
+	return -ENODEV;
+}
+
+EXPORT_SYMBOL(i2c_open);
+EXPORT_SYMBOL(i2c_close);
+EXPORT_SYMBOL(i2c_setclk);
+EXPORT_SYMBOL(i2c_read);
+EXPORT_SYMBOL(i2c_write);
diff --git a/arch/mips/jz4760b/i2c_intr_debug.c b/arch/mips/jz4760b/i2c_intr_debug.c
new file mode 100644
index 00000000000..2130c47a355
--- /dev/null
+++ b/arch/mips/jz4760b/i2c_intr_debug.c
@@ -0,0 +1,254 @@
+/*
+ * linux/arch/mips/jz4760b/i2c.c
+ * 
+ * Jz4810 I2C routines.
+ * 
+ * Copyright (C) 2005,2006 Ingenic Semiconductor Inc.
+ * Author: <cwjia@ingenic.cn>
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ */
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/delay.h>
+#include <asm/uaccess.h>
+#include <asm/addrspace.h>
+
+#include <asm/jzsoc.h>
+
+/* I2C protocol */
+#define I2C_READ	1
+#define I2C_WRITE	0
+
+#define TIMEOUT         1000
+
+static volatile int w_tfep = 0;
+static volatile int w_rfne = 0;
+static	unsigned char *tmpbuf;
+static	unsigned char tmpaddr;
+static int cnt;
+
+/*
+ * I2C_SCK, I2C_SDA
+ */
+#define __gpio_as_i2c()				\
+do {						\
+	REG_GPIO_PXFUNS(2) = 0x00000c00;	\
+	REG_GPIO_PXTRGC(2) = 0x00000c00;	\
+	REG_GPIO_PXSELS(2)  = 0x00000c00;	\
+} while (0)
+
+/*
+ * I2C interface
+ */
+
+static int i2c_disable()
+{
+	int timeout = 0xfffff, i = 100;
+	
+	REG_I2C_ENB = 0; /*disable i2c*/
+	while((REG_I2C_ENSTA & 0x1) && (timeout > 0)) {
+		udelay(1);
+		timeout --;
+	}
+	if(timeout)
+		return 0;
+	else
+		return 1;
+}
+
+static irqreturn_t jz_i2chander(int irq, void *devid)
+{
+	if (REG_I2C_INTST & I2C_INTST_RXFL) {
+		w_rfne  = 1;
+		REG_I2C_INTM = 0;
+		return IRQ_HANDLED;
+	}
+	REG_I2C_INTM = 0;
+	w_tfep = 1;	
+	return IRQ_HANDLED;
+}
+
+void i2c_open()
+{
+	__gpio_as_i2c();
+	REG_I2C_RXTL = 0;
+	request_irq(IRQ_I2C,jz_i2chander,IRQF_DISABLED,0,0);
+}
+
+void i2c_close(void)
+{
+}
+
+void i2c_setclk(unsigned int i2cclk)
+{
+
+}
+
+static void i2c_init_as_master(unsigned char address)
+{
+	if(i2c_disable())
+		printk("i2c_disable error\n");
+//	REG_I2C_CTRL = 0x43;
+	REG_I2C_CTRL = 0x45;
+	REG_I2C_TAR = address; /* slave id needed write only once */
+	REG_I2C_INTM = 0x10;
+	REG_I2C_FHCNT =49;
+	REG_I2C_FLCNT =62;
+	REG_I2C_RXTL = 0;
+//	REG_I2C_SHCNT =0xc80; // 6k
+//	REG_I2C_SLCNT =0xeb0; // 6k
+//	REG_I2C_SHCNT =0x640; // 12k
+//	REG_I2C_SLCNT =0x758; // 12k
+//	REG_I2C_SHCNT =0x320; //26k
+//	REG_I2C_SLCNT =0x3ac; //26k
+//	REG_I2C_SHCNT =0x12c; //71k
+//	REG_I2C_SLCNT =0x160; //71k
+//	REG_I2C_SHCNT =0xc8;
+//	REG_I2C_SLCNT =0xe8;
+	REG_I2C_ENB = 1; /*enable i2c*/
+}
+
+
+int i2c_read(unsigned char device, unsigned char *buf,
+	       unsigned char address, int count)
+{
+	int cnt = count;
+	volatile int tmp;
+	int timeout = 0xffff;
+
+	i2c_init_as_master(device);
+
+	address = address & 0xff;
+       
+	while(!w_tfep)
+		;
+	w_tfep = 0;
+
+	REG_I2C_DC = (I2C_WRITE << 8) | address; 
+
+	while(cnt) {
+		timeout = 0xffff;
+
+	REG_I2C_INTM = 0x10;
+
+	while(!w_tfep)
+		;
+	w_tfep = 0;		
+	REG_I2C_DC = (I2C_READ << 8); 
+	REG_I2C_INTM = 0x4;
+	while(!w_rfne) 
+		;
+	
+	w_rfne = 0;		
+	
+	*buf = REG_I2C_DC & 0xff;
+	
+	cnt--;
+	buf++;
+	}
+	return count - cnt;
+}
+
+int i2c_write(unsigned char device, unsigned char *buf,
+		unsigned char address, int count)
+{
+	int cnt_in_pg;
+	cnt = count;
+	int timeout = 0xffff;
+
+	tmpbuf = (unsigned char *)buf;
+	tmpaddr = address;
+
+rewrite:
+	i2c_init_as_master(device);
+
+start_write_page:
+	cnt_in_pg = 0;
+
+	while(!w_tfep)
+		;
+	w_tfep = 0;
+	
+	REG_I2C_DC = (I2C_WRITE << 8) | tmpaddr;   
+
+	if ((REG_I2C_TXABRT & I2C_TXABRT_ABRT_7B_ADDR_NOACK) || ( REG_I2C_STA & I2C_STA_TFE)) {
+		mdelay(3);
+		int a = REG_I2C_CINTR;
+		goto rewrite;
+	}
+	REG_I2C_INTM = 0x10;
+	
+	while(cnt) {
+		
+		if (++cnt_in_pg > 16) { //8 or 16 
+			mdelay(3);
+			tmpaddr += 16;
+			goto start_write_page;
+		}
+
+		while(!w_tfep)
+			;
+		if ((REG_I2C_TXABRT & I2C_TXABRT_ABRT_7B_ADDR_NOACK)) {
+			mdelay(3);
+			tmpbuf = (unsigned char *)buf;
+			cnt = 16;  
+			int a = REG_I2C_CINTR;
+			goto rewrite;
+		}
+
+		if(REG_I2C_TXABRT != 0)
+			printk("\n\nREG_I2C_TXABRT==0x%x\n",REG_I2C_TXABRT);
+
+		REG_I2C_DC = (I2C_WRITE << 8) | *tmpbuf;
+		REG_I2C_INTM = 0x10;
+
+		w_tfep = 0;
+		cnt--;
+		tmpbuf++;
+
+		if ((REG_I2C_TXABRT & I2C_TXABRT_ABRT_7B_ADDR_NOACK) || ( REG_I2C_STA & I2C_STA_TFE)) {
+			mdelay(3);
+			tmpbuf = (unsigned char *)buf;
+			cnt = 16;  
+			int a = REG_I2C_CINTR;
+			goto rewrite;
+		}
+	}
+
+	timeout = 0xffff;
+	while(((REG_I2C_STA & I2C_STA_MSTACT)) && --timeout)
+		;
+	if (!(timeout)) 
+		printk("***timeout*****************\n");
+	mdelay(2);
+	udelay(450);
+
+	if (REG_I2C_TXABRT & I2C_TXABRT_ABRT_7B_ADDR_NOACK) {
+		mdelay(3);
+		tmpbuf = (unsigned char *)buf;
+		cnt = 16;  
+		int a = REG_I2C_CINTR;
+		goto rewrite;
+	}
+
+	return count - cnt;
+}
+
+EXPORT_SYMBOL(i2c_open);
+EXPORT_SYMBOL(i2c_close);
+EXPORT_SYMBOL(i2c_setclk);
+EXPORT_SYMBOL(i2c_read);
+EXPORT_SYMBOL(i2c_write);
diff --git a/arch/mips/jz4760b/i2c_pio_debug.c b/arch/mips/jz4760b/i2c_pio_debug.c
new file mode 100644
index 00000000000..429d9c6c2c8
--- /dev/null
+++ b/arch/mips/jz4760b/i2c_pio_debug.c
@@ -0,0 +1,255 @@
+/*
+ * linux/arch/mips/jz4810/i2c.c
+ * 
+ * Jz4810 I2C routines.
+ * 
+ * Copyright (C) 2005,2006 Ingenic Semiconductor Inc.
+ * Author: <cwjia@ingenic.cn>
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ */
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/delay.h>
+#include <asm/uaccess.h>
+#include <asm/addrspace.h>
+
+#include <asm/jzsoc.h>
+
+/* I2C protocol */
+#define I2C_READ	1
+#define I2C_WRITE	0
+
+#define TIMEOUT         1000
+
+/*
+ * I2C_SCK, I2C_SDA
+ */
+#define __gpio_as_i2c()				\
+do {						\
+	REG_GPIO_PXFUNS(2) = 0x00000c00;	\
+	REG_GPIO_PXTRGC(2) = 0x00000c00;	\
+	REG_GPIO_PXSELS(2)  = 0x00000c00;	\
+} while (0)
+
+/*
+ * I2C interface
+ */
+
+static int i2c_disable()
+{
+	int timeout = 0xfffff, i = 100;
+	
+	REG_I2C_ENB = 0; /*disable i2c*/
+	while((REG_I2C_ENSTA & 0x1) && (timeout > 0)) {
+		udelay(1);
+		timeout --;
+	}
+	if(timeout)
+		return 0;
+	else
+		return 1;
+}
+void i2c_open()
+{
+	__gpio_as_i2c();
+}
+
+void i2c_close(void)
+{
+}
+
+void i2c_setclk(unsigned int i2cclk)
+{
+
+}
+
+static void i2c_init_as_master(unsigned char address)
+{
+//	__gpio_as_i2c();
+	if(i2c_disable())
+		printk("i2c not disable\n");
+//	REG_I2C_CTRL = 0x43;
+	REG_I2C_CTRL = 0x45;
+	REG_I2C_TAR = address; /* slave id needed write only once */
+	REG_I2C_INTM = 0;
+	REG_I2C_FHCNT =49;
+	REG_I2C_FLCNT =62;
+//	REG_I2C_SHCNT =0xc80; // 6k
+//	REG_I2C_SLCNT =0xeb0; // 6k
+//	REG_I2C_SHCNT =0x640; // 12k
+//	REG_I2C_SLCNT =0x758; // 12k
+//	REG_I2C_SHCNT =0x320; //26k
+//	REG_I2C_SLCNT =0x3ac; //26k
+//	REG_I2C_SHCNT =0x12c; //71k
+//	REG_I2C_SLCNT =0x160; //71k
+//	REG_I2C_SHCNT =0xc8;
+//	REG_I2C_SLCNT =0xe8;
+	REG_I2C_ENB = 1; /*enable i2c*/
+}
+
+
+/* now for fpga test , count == 1 */
+int i2c_read(unsigned char device, unsigned char *buf,
+	       unsigned char address, int count)
+{
+	int cnt = count;
+	volatile int tmp;
+	int timeout = 0xffff;
+
+	i2c_init_as_master(device);
+
+	address = address & 0xff;
+	
+	while((!(REG_I2C_STA & I2C_STA_TFNF)) && --timeout)
+		;	
+	if (!(timeout)) 
+		printk("***timeout*****************\n");
+	
+	REG_I2C_DC = (I2C_WRITE << 8) | address; 
+
+	while(cnt) {
+		timeout = 0xffff;
+		while((!(REG_I2C_STA & I2C_STA_TFNF)) && --timeout)
+			;	
+		if (!(timeout)) 
+			printk("***timeout*****************\n");
+		
+		REG_I2C_DC = (I2C_READ << 8); 
+#if 1		
+		while((!(REG_I2C_STA & I2C_STA_RFNE)) && timeout) {
+			timeout--;
+		}
+#endif			
+		if (!(timeout)) 
+			printk("***timeout*****************\n");
+
+		*buf = REG_I2C_DC & 0xff;
+
+		cnt--;
+		buf++;
+	}
+	return count - cnt;
+}
+
+int i2c_write(unsigned char device, unsigned char *buf,
+		unsigned char address, int count)
+{
+	int cnt_in_pg,cnt = count;
+	unsigned char *tmpbuf;
+	unsigned char tmpaddr;
+	int timeout = 0xffff;
+	int rw = 0;
+
+
+	tmpbuf = (unsigned char *)buf;
+	tmpaddr = address;
+rewrite:
+	i2c_init_as_master(device);
+
+start_write_page:
+	cnt_in_pg = 0;
+	while((!(REG_I2C_STA & I2C_STA_TFNF)) && --timeout)
+		;	
+	if (!(timeout)) 
+		printk("00***timeout*****************\n");
+
+		REG_I2C_DC = (I2C_WRITE << 8) | tmpaddr;
+#if 1
+
+		if ((REG_I2C_TXABRT & I2C_TXABRT_ABRT_7B_ADDR_NOACK) || ( REG_I2C_STA & I2C_STA_TFE)) {
+			mdelay(3);
+			int a = REG_I2C_CINTR;
+			goto rewrite;
+		}
+#endif
+	while(cnt) {
+
+		timeout = 0xfffff;
+#if 1
+		if ((REG_I2C_TXABRT & I2C_TXABRT_ABRT_7B_ADDR_NOACK) || ( REG_I2C_STA & I2C_STA_TFE)) {
+			mdelay(3);
+			rw = 1;
+			tmpbuf = (unsigned char *)buf;
+			cnt = 16;  
+			int a = REG_I2C_CINTR;
+			goto rewrite;
+		}
+#endif
+
+		if (++cnt_in_pg > 16) { //8 or 16 
+			mdelay(3);
+			tmpaddr += 16;
+			goto start_write_page;
+		}
+
+
+		while((!(REG_I2C_STA & I2C_STA_TFNF)) && timeout)
+			;		
+
+		if ((REG_I2C_TXABRT & I2C_TXABRT_ABRT_7B_ADDR_NOACK) || ( REG_I2C_STA & I2C_STA_TFE)) {
+			mdelay(3);
+			rw = 1;
+			tmpbuf = (unsigned char *)buf;
+			cnt = 16;  
+			int a = REG_I2C_CINTR;
+			goto rewrite;
+		}
+
+		if(REG_I2C_TXABRT != 0)
+			printk("\n\nREG_I2C_TXABRT==0x%x\n",REG_I2C_TXABRT);
+		
+		REG_I2C_DC = (I2C_WRITE << 8) | *tmpbuf;
+
+		rw = 0;
+		cnt--;
+		tmpbuf++;
+#if 1
+		if ((REG_I2C_TXABRT & I2C_TXABRT_ABRT_7B_ADDR_NOACK) || ( REG_I2C_STA & I2C_STA_TFE)) {
+			mdelay(3);
+			rw = 1;
+			tmpbuf = (unsigned char *)buf;
+			cnt = 16;  
+			int a = REG_I2C_CINTR;
+			goto rewrite;
+		}
+#endif
+	}
+
+	timeout = 0xffff;
+	while(((REG_I2C_STA & I2C_STA_MSTACT)) && --timeout)
+		;
+	if (!(timeout)) 
+		printk("22***timeout*****************\n");
+
+	mdelay(2);
+	udelay(450);
+
+	if (REG_I2C_TXABRT & I2C_TXABRT_ABRT_7B_ADDR_NOACK) {
+		mdelay(3);
+		rw = 1;
+		tmpbuf = (unsigned char *)buf;
+		cnt = 16;  
+		int a = REG_I2C_CINTR;
+		goto rewrite;
+	}
+	return count - cnt;
+}
+
+EXPORT_SYMBOL(i2c_open);
+EXPORT_SYMBOL(i2c_close);
+EXPORT_SYMBOL(i2c_setclk);
+EXPORT_SYMBOL(i2c_read);
+EXPORT_SYMBOL(i2c_write);
diff --git a/arch/mips/jz4760b/irq.c b/arch/mips/jz4760b/irq.c
new file mode 100644
index 00000000000..d1f058ebe56
--- /dev/null
+++ b/arch/mips/jz4760b/irq.c
@@ -0,0 +1,509 @@
+/*
+ * linux/arch/mips/jz4760b/irq.c
+ *
+ * JZ4760B interrupt routines.
+ *
+ * Copyright (c) 2006-2007  Ingenic Semiconductor Inc.
+ * Author: <lhhuang@ingenic.cn>
+ *
+ *  This program is free software; you can redistribute	 it and/or modify it
+ *  under  the terms of	 the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the	License, or (at your
+ *  option) any later version.
+ */
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/kernel_stat.h>
+#include <linux/module.h>
+#include <linux/signal.h>
+#include <linux/sched.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/timex.h>
+#include <linux/slab.h>
+#include <linux/random.h>
+#include <linux/delay.h>
+#include <linux/bitops.h>
+
+#include <asm/bootinfo.h>
+#include <asm/io.h>
+#include <asm/mipsregs.h>
+#include <asm/system.h>
+#include <asm/jzsoc.h>
+
+/*
+ * INTC irq type
+ */
+
+static void enable_intc_irq(unsigned int irq)
+{
+	__intc_unmask_irq(irq);
+}
+
+static void disable_intc_irq(unsigned int irq)
+{
+	__intc_mask_irq(irq);
+}
+
+static void mask_and_ack_intc_irq(unsigned int irq)
+{
+	__intc_mask_irq(irq);
+	__intc_ack_irq(irq);
+}
+
+static void end_intc_irq(unsigned int irq)
+{
+	if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) {
+		enable_intc_irq(irq);
+	}
+}
+
+static unsigned int startup_intc_irq(unsigned int irq)
+{
+	enable_intc_irq(irq);
+	return 0;
+}
+
+static void shutdown_intc_irq(unsigned int irq)
+{
+	disable_intc_irq(irq);
+}
+
+static struct irq_chip intc_irq_type = {
+	.typename = "INTC",
+	.startup = startup_intc_irq,
+	.shutdown = shutdown_intc_irq,
+	.unmask = enable_intc_irq,
+	.mask = disable_intc_irq,
+	.ack = mask_and_ack_intc_irq,
+	.end = end_intc_irq,
+};
+
+/*
+ * GPIO irq type
+ */
+
+static void enable_gpio_irq(unsigned int irq)
+{
+	unsigned int intc_irq;
+
+	if (irq < (IRQ_GPIO_0 + 32)) {
+		intc_irq = IRQ_GPIO0;
+	}
+	else if (irq < (IRQ_GPIO_0 + 64)) {
+		intc_irq = IRQ_GPIO1;
+	}
+	else if (irq < (IRQ_GPIO_0 + 96)) {
+		intc_irq = IRQ_GPIO2;
+	}
+	else if (irq < (IRQ_GPIO_0 + 128)) {
+		intc_irq = IRQ_GPIO3;
+	}
+	else if (irq < (IRQ_GPIO_0 + 160)) {
+		intc_irq = IRQ_GPIO4;
+	}
+	else {
+		intc_irq = IRQ_GPIO5;
+	}
+
+	enable_intc_irq(intc_irq);
+	__gpio_unmask_irq(irq - IRQ_GPIO_0);
+}
+
+static void disable_gpio_irq(unsigned int irq)
+{
+	__gpio_mask_irq(irq - IRQ_GPIO_0);
+}
+
+static void mask_and_ack_gpio_irq(unsigned int irq)
+{
+	__gpio_mask_irq(irq - IRQ_GPIO_0);
+	__gpio_ack_irq(irq - IRQ_GPIO_0);
+}
+
+static void end_gpio_irq(unsigned int irq)
+{
+	if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) {
+		enable_gpio_irq(irq);
+	}
+}
+
+static unsigned int startup_gpio_irq(unsigned int irq)
+{
+	enable_gpio_irq(irq);
+	return 0;
+}
+
+static void shutdown_gpio_irq(unsigned int irq)
+{
+	disable_gpio_irq(irq);
+}
+
+static struct irq_chip gpio_irq_type = {
+	.typename = "GPIO",
+	.startup = startup_gpio_irq,
+	.shutdown = shutdown_gpio_irq,
+	.unmask = enable_gpio_irq,
+	.mask = disable_gpio_irq,
+	.ack = mask_and_ack_gpio_irq,
+	.end = end_gpio_irq,
+};
+
+/*
+ * DMA irq type
+ */
+
+static void enable_dma_irq(unsigned int irq)
+{
+	unsigned int intc_irq;
+
+	if ( irq < (IRQ_DMA_0 + HALF_DMA_NUM) ) 	/* DMAC Group 0 irq */
+		intc_irq = IRQ_DMAC0;
+	else if ( irq < (IRQ_DMA_0 + MAX_DMA_NUM) ) 	/* DMAC Group 1 irq */
+		intc_irq = IRQ_DMAC1;
+	else {
+		printk("%s, unexpected dma irq #%d\n", __FILE__, irq);
+		return;
+	}
+	__intc_unmask_irq(intc_irq);
+	__dmac_channel_enable_irq(irq - IRQ_DMA_0);
+}
+
+static void disable_dma_irq(unsigned int irq)
+{
+	int chan = irq - IRQ_DMA_0;
+	__dmac_disable_channel(chan);
+	__dmac_channel_disable_irq(chan);
+}
+
+static void mask_and_ack_dma_irq(unsigned int irq)
+{
+	unsigned int intc_irq;
+
+	disable_dma_irq(irq);
+
+	if ( irq < (IRQ_DMA_0 + HALF_DMA_NUM) ) 	/* DMAC Group 0 irq */
+		intc_irq = IRQ_DMAC0;
+	else if ( irq < (IRQ_DMA_0 + MAX_DMA_NUM) ) 	/* DMAC Group 1 irq */
+		intc_irq = IRQ_DMAC1;
+	else {
+		printk("%s, unexpected dma irq #%d\n", __FILE__, irq);
+		return ;
+	}
+	__intc_ack_irq(intc_irq);
+}
+
+static void end_dma_irq(unsigned int irq)
+{
+	if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) {
+		enable_dma_irq(irq);
+	}
+}
+
+static unsigned int startup_dma_irq(unsigned int irq)
+{
+	enable_dma_irq(irq);
+	return 0;
+}
+
+static void shutdown_dma_irq(unsigned int irq)
+{
+	disable_dma_irq(irq);
+}
+
+static struct irq_chip dma_irq_type = {
+	.typename = "DMA",
+	.startup = startup_dma_irq,
+	.shutdown = shutdown_dma_irq,
+	.unmask = enable_dma_irq,
+	.mask = disable_dma_irq,
+	.ack = mask_and_ack_dma_irq,
+	.end = end_dma_irq,
+};
+
+/*
+ * MDMA irq type
+ */
+
+static void enable_mdma_irq(unsigned int irq)
+{
+	unsigned int intc_irq;
+
+	if (irq < IRQ_MDMA_0 + MAX_MDMA_NUM) 	/* DMAC Group 0 irq */
+		intc_irq = IRQ_MDMA;
+	else {
+		printk("%s, unexpected mdma irq #%d\n", __FILE__, irq);
+		return;
+	}
+	__intc_unmask_irq(intc_irq);
+	__mdmac_channel_enable_irq(irq - IRQ_DMA_0);
+}
+
+static void disable_mdma_irq(unsigned int irq)
+{
+	__mdmac_channel_disable_irq(irq - IRQ_DMA_0);
+}
+
+static void mask_and_ack_mdma_irq(unsigned int irq)
+{
+	unsigned int intc_irq;
+
+	if ( irq < IRQ_MDMA_0 + MAX_MDMA_NUM ) 	/* DMAC Group 0 irq */
+		intc_irq = IRQ_MDMA;
+	else {
+		printk("%s, unexpected mdma irq #%d\n", __FILE__, irq);
+		return ;
+	}
+	__intc_ack_irq(intc_irq);
+	__mdmac_channel_ack_irq(irq-IRQ_MDMA_0); /* needed?? add 20080506, Wolfgang */
+	__mdmac_channel_disable_irq(irq - IRQ_MDMA_0);
+}
+
+static void end_mdma_irq(unsigned int irq)
+{
+	if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) {
+		enable_mdma_irq(irq);
+	}
+}
+
+static unsigned int startup_mdma_irq(unsigned int irq)
+{
+	enable_mdma_irq(irq);
+	return 0;
+}
+
+static void shutdown_mdma_irq(unsigned int irq)
+{
+	disable_mdma_irq(irq);
+}
+
+static struct irq_chip mdma_irq_type = {
+	.typename = "MDMA",
+	.startup = startup_mdma_irq,
+	.shutdown = shutdown_mdma_irq,
+	.unmask = enable_mdma_irq,
+	.mask = disable_mdma_irq,
+	.ack = mask_and_ack_mdma_irq,
+	.end = end_mdma_irq,
+};
+
+//----------------------------------------------------------------------
+
+/*
+ * BDMA irq type
+ */
+
+static void enable_bdma_irq(unsigned int irq)
+{
+	unsigned int intc_irq;
+
+	if (irq < IRQ_BDMA_0 + MAX_BDMA_NUM)
+		intc_irq = IRQ_BDMA;
+	else {
+		printk("%s, unexpected bdma irq #%d\n", __FILE__, irq);
+		return;
+	}
+	__intc_unmask_irq(intc_irq);
+	__bdmac_channel_enable_irq(irq - IRQ_DMA_0);
+}
+
+static void disable_bdma_irq(unsigned int irq)
+{
+	__bdmac_channel_disable_irq(irq - IRQ_DMA_0);
+}
+
+static void mask_and_ack_bdma_irq(unsigned int irq)
+{
+	unsigned int intc_irq;
+
+	if ( irq < IRQ_BDMA_0 + MAX_BDMA_NUM ) 	/* DMAC Group 0 irq */
+		intc_irq = IRQ_BDMA;
+	else {
+		printk("%s, unexpected bdma irq #%d\n", __FILE__, irq);
+		return ;
+	}
+	__intc_ack_irq(intc_irq);
+	__bdmac_channel_ack_irq(irq - IRQ_BDMA_0);
+	__bdmac_channel_disable_irq(irq - IRQ_BDMA_0);
+}
+
+static void end_bdma_irq(unsigned int irq)
+{
+	if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) {
+		enable_bdma_irq(irq);
+	}
+}
+
+static unsigned int startup_bdma_irq(unsigned int irq)
+{
+	enable_bdma_irq(irq);
+	return 0;
+}
+
+static void shutdown_bdma_irq(unsigned int irq)
+{
+	disable_bdma_irq(irq);
+}
+
+static struct irq_chip bdma_irq_type = {
+	.typename = "BDMA",
+	.startup = startup_bdma_irq,
+	.shutdown = shutdown_bdma_irq,
+	.unmask = enable_bdma_irq,
+	.mask = disable_bdma_irq,
+	.ack = mask_and_ack_bdma_irq,
+	.end = end_bdma_irq,
+};
+
+//----------------------------------------------------------------------
+void plat_bad_irq(unsigned int irq)
+{
+        printk("INTC Registers:\n");
+	printk("REG_INTC_ICMR0=0x%08x, REG_INTC_ICMR1=0x%08x\n", REG_INTC_IMR(0), REG_INTC_IMR(1));
+	printk("REG_INTC_ICPR0=0x%08x, REG_INTC_ICPR1=0x%08x\n", REG_INTC_IPR(0), REG_INTC_IPR(1));
+}
+
+extern void (*ack_bad_irq_callback)(unsigned int irq);
+void __init arch_init_irq(void)
+{
+	int i;
+
+	clear_c0_status(0xff04); /* clear ERL */
+	set_c0_status(0x0400);   /* set IP2 */
+
+	ack_bad_irq_callback = plat_bad_irq;
+
+	/* Set up INTC irq
+	 */
+	for (i = 0; i < NUM_INTC; i++) {
+		disable_intc_irq(i);
+		set_irq_chip_and_handler(i, &intc_irq_type, handle_level_irq);
+	}
+
+	/* Set up DMAC irq
+	 */
+	for (i = 0; i < NUM_DMA; i++) {
+		disable_dma_irq(IRQ_DMA_0 + i);
+		set_irq_chip_and_handler(IRQ_DMA_0 + i, &dma_irq_type, handle_level_irq);
+	}
+
+	/* Set up MDMAC irq
+	 */
+	for (i = 0; i < NUM_MDMA; i++) {
+		disable_mdma_irq(IRQ_MDMA_0 + i);
+		set_irq_chip_and_handler(IRQ_MDMA_0 + i, &mdma_irq_type, handle_level_irq);
+	}
+
+	/* Set up BDMA irq
+	 */
+	for (i = 0; i < MAX_BDMA_NUM; i++) {
+		disable_bdma_irq(IRQ_BDMA_0 + i);
+		set_irq_chip_and_handler(IRQ_BDMA_0 + i, &bdma_irq_type, handle_level_irq);
+	}
+
+	/* Set up GPIO irq
+	 */
+	for (i = 0; i < NUM_GPIO; i++) {
+		disable_gpio_irq(IRQ_GPIO_0 + i);
+		set_irq_chip_and_handler(IRQ_GPIO_0 + i, &gpio_irq_type, handle_level_irq);
+	}
+}
+
+static int plat_real_irq(int irq)
+{
+	switch (irq) {
+#if 0
+	case IRQ_GPIO0:
+		irq = __gpio_group_irq(0) + IRQ_GPIO_0;
+		break;
+	case IRQ_GPIO1:
+		irq = __gpio_group_irq(1) + IRQ_GPIO_0 + 32;
+		break;
+	case IRQ_GPIO2:
+		irq = __gpio_group_irq(2) + IRQ_GPIO_0 + 64;
+		break;
+	case IRQ_GPIO3:
+		irq = __gpio_group_irq(3) + IRQ_GPIO_0 + 96;
+		break;
+	case IRQ_GPIO4:
+		irq = __gpio_group_irq(4) + IRQ_GPIO_0 + 128;
+		break;
+	case IRQ_GPIO5:
+		irq = __gpio_group_irq(5) + IRQ_GPIO_0 + 160;
+		break;
+#endif
+	case IRQ_DMAC0:
+	case IRQ_DMAC1:
+		irq = __dmac_get_irq() + IRQ_DMA_0;
+		break;
+	case IRQ_MDMA:
+		irq = __mdmac_get_irq() + IRQ_MDMA_0;
+		break;
+	case IRQ_BDMA:
+		irq = __bdmac_get_irq() + IRQ_BDMA_0;
+		break;
+	}
+
+	return irq;
+}
+
+asmlinkage void plat_irq_dispatch(void)
+{
+	int irq = 0, group;
+
+	unsigned long intc_ipr0 = 0, intc_ipr1 = 0;
+
+	intc_ipr0 = REG_INTC_IPR(0);
+	intc_ipr1 = REG_INTC_IPR(1);
+
+
+	if (!(intc_ipr0 || intc_ipr1))	return;
+#if 0
+	if (intc_ipr0) {
+		irq = ffs(intc_ipr0) - 1;
+		intc_ipr0 &= ~(1<<irq);
+	} else {
+		irq = ffs(intc_ipr1) - 1;
+		intc_ipr1 &= ~(1<<irq);
+		irq += 32;
+	}
+#endif
+#if 1
+	if (!(intc_ipr0 & 3)) {
+		if (intc_ipr0) {
+			irq = fls(intc_ipr0) - 1;
+			intc_ipr0 &= ~(1<<irq);
+		} else {
+			irq = fls(intc_ipr1) - 1;
+			intc_ipr1 &= ~(1<<irq);
+			irq += 32;
+		}
+	} else  {
+		if (intc_ipr0 & 2) {
+
+			irq = 1;
+			intc_ipr0 &= ~(1<<irq);
+		} else {
+
+			irq = 0;
+			intc_ipr0 &= ~(1<<irq);
+		}
+	}
+#endif
+
+	if ((irq >= IRQ_GPIO5) && (irq <= IRQ_GPIO0)) {
+		group = IRQ_GPIO0 - irq;
+		irq = __gpio_group_irq(group);
+		if (irq < 0) {
+			return;
+		}
+
+		irq += IRQ_GPIO_0 + 32 * group;
+	} else {
+		irq = plat_real_irq(irq);
+	}
+
+	do_IRQ(irq);
+}
diff --git a/arch/mips/jz4760b/platform.c b/arch/mips/jz4760b/platform.c
new file mode 100644
index 00000000000..dcd55cfbdc7
--- /dev/null
+++ b/arch/mips/jz4760b/platform.c
@@ -0,0 +1,461 @@
+/*
+ * Platform device support for Jz4760b SoC.
+ *
+ * Copyright 2007, <yliu@ingenic.cn>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/resource.h>
+
+#ifdef CONFIG_ANDROID_PMEM
+#include <linux/android_pmem.h>
+#endif
+
+#include <asm/jzsoc.h>
+#include <linux/usb/musb.h>
+#include <../sound/oss/jz_audio.h>
+#include <linux/spi/spi.h>
+
+extern void __init board_msc_init(void);
+
+/* OHCI (USB full speed host controller) */
+static struct resource jz_usb_ohci_resources[] = {
+	[0] = {
+		.start		= CPHYSADDR(UHC_BASE), // phys addr for ioremap
+		.end		= CPHYSADDR(UHC_BASE) + 0x10000 - 1,
+		.flags		= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start		= IRQ_UHC,
+		.end		= IRQ_UHC,
+		.flags		= IORESOURCE_IRQ,
+	},
+};
+
+/* The dmamask must be set for OHCI to work */
+static u64 ohci_dmamask = ~(u32)0;
+
+static struct platform_device jz_usb_ohci_device = {
+	.name		= "jz-ohci",
+	.id		= 0,
+	.dev = {
+		.dma_mask		= &ohci_dmamask,
+		.coherent_dma_mask	= 0xffffffff,
+	},
+	.num_resources	= ARRAY_SIZE(jz_usb_ohci_resources),
+	.resource	= jz_usb_ohci_resources,
+};
+
+/*** LCD controller ***/
+static struct resource jz_lcd_resources[] = {
+	[0] = {
+		.start          = CPHYSADDR(LCD_BASE),
+		.end            = CPHYSADDR(LCD_BASE) + 0x10000 - 1,
+		.flags          = IORESOURCE_MEM,
+	},
+	[1] = {
+		.start          = IRQ_LCD,
+		.end            = IRQ_LCD,
+		.flags          = IORESOURCE_IRQ,
+	}
+};
+
+static u64 jz_lcd_dmamask = ~(u32)0;
+
+static struct platform_device jz_lcd_device = {
+	.name           = "jz-lcd",
+	.id             = 0,
+	.dev = {
+		.dma_mask               = &jz_lcd_dmamask,
+		.coherent_dma_mask      = 0xffffffff,
+	},
+	.num_resources  = ARRAY_SIZE(jz_lcd_resources),
+	.resource       = jz_lcd_resources,
+};
+
+/* USB OTG Controller */
+static struct platform_device jz_usb_otg_xceiv_device = {
+	.name	= "nop_usb_xceiv",
+	.id	= 0,
+};
+
+static struct musb_hdrc_config jz_usb_otg_config = {
+	.multipoint	= 1,
+	.dyn_fifo	= 0,
+	.soft_con	= 1,
+	.dma		= 1,
+/* Max EPs scanned. Driver will decide which EP can be used automatically. */
+	.num_eps	= 6,
+};
+
+static struct musb_hdrc_platform_data jz_usb_otg_platform_data = {
+#if defined(CONFIG_USB_MUSB_OTG)
+	.mode           = MUSB_OTG,
+#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
+	.mode           = MUSB_HOST,
+#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
+	.mode           = MUSB_PERIPHERAL,
+#endif
+	.config		= &jz_usb_otg_config,
+};
+
+static struct resource jz_usb_otg_resources[] = {
+	[0] = {
+		.start		= CPHYSADDR(UDC_BASE),
+		.end		= CPHYSADDR(UDC_BASE) + 0x10000 - 1,
+		.flags		= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start		= IRQ_OTG,
+		.end		= IRQ_OTG,
+		.flags		= IORESOURCE_IRQ,
+	},
+};
+
+static u64  usb_otg_dmamask = ~(u32)0;
+
+static struct platform_device jz_usb_otg_device = {
+	.name	= "musb_hdrc",
+	.id	= 0,
+	.dev = {
+		.dma_mask		= &usb_otg_dmamask,
+		.coherent_dma_mask	= 0xffffffff,
+		.platform_data		= &jz_usb_otg_platform_data,
+	},
+	.num_resources	= ARRAY_SIZE(jz_usb_otg_resources),
+	.resource	= jz_usb_otg_resources,
+};
+
+/** MMC/SD/SDIO controllers**/
+#define __BUILD_JZ_MSC_PLATFORM_DEV(msc_id)				\
+	static struct resource jz_msc##msc_id##_resources[] = {		\
+		{							\
+			.start          = CPHYSADDR(MSC##msc_id##_BASE), \
+			.end            = CPHYSADDR(MSC##msc_id##_BASE) + 0x1000 - 1, \
+			.flags          = IORESOURCE_MEM,		\
+		},							\
+		{							\
+			.start          = IRQ_MSC##msc_id,		\
+			.end            = IRQ_MSC##msc_id,		\
+			.flags          = IORESOURCE_IRQ,		\
+		},							\
+		{							\
+			.start          = DMA_ID_MSC##msc_id,	\
+			.end            = DMA_ID_MSC##msc_id,	\
+			.flags          = IORESOURCE_DMA,		\
+		},							\
+	};								\
+									\
+	static u64 jz_msc##msc_id##_dmamask =  ~(u32)0;			\
+									\
+	static struct platform_device jz_msc##msc_id##_device = {	\
+		.name = "jz-msc",					\
+		.id = msc_id,						\
+		.dev = {						\
+			.dma_mask               = &jz_msc##msc_id##_dmamask, \
+			.coherent_dma_mask      = 0xffffffff,		\
+		},							\
+		.num_resources  = ARRAY_SIZE(jz_msc##msc_id##_resources), \
+		.resource       = jz_msc##msc_id##_resources,		\
+	};
+
+#ifdef CONFIG_JZ_MSC0
+__BUILD_JZ_MSC_PLATFORM_DEV(0)
+#endif
+#ifdef CONFIG_JZ_MSC1
+__BUILD_JZ_MSC_PLATFORM_DEV(1)
+#endif
+#ifdef CONFIG_JZ_MSC2
+__BUILD_JZ_MSC_PLATFORM_DEV(2)
+#endif
+
+static struct platform_device *jz_msc_devices[] __initdata = {
+#ifdef CONFIG_JZ_MSC0
+	&jz_msc0_device,
+#else
+	NULL,
+#endif
+#ifdef CONFIG_JZ_MSC1
+	&jz_msc1_device,
+#else
+	NULL,
+#endif
+#ifdef CONFIG_JZ_MSC2
+	&jz_msc2_device,
+#else
+	NULL,
+#endif
+};
+
+int __init jz_add_msc_devices(unsigned int id, struct jz_mmc_platform_data *plat)
+{
+	struct platform_device	*pdev;
+
+	if (JZ_MSC_ID_INVALID(id))
+		return -EINVAL;
+
+	pdev = jz_msc_devices[id];
+	if (NULL == pdev) {
+		return -EINVAL;
+	}
+
+	pdev->dev.platform_data = plat;
+
+	return platform_device_register(pdev);
+}
+
+
+/* + Sound device */
+#define SND(num, desc) { .name = desc, .id = num }
+static struct snd_endpoint snd_endpoints_list[] = {
+	SND(0, "HANDSET"),
+	SND(1, "SPEAKER"),
+	SND(2, "HEADSET"),
+};
+#undef SND
+
+static struct jz_snd_endpoints vogue_snd_endpoints = {
+	.endpoints = snd_endpoints_list,
+	.num = ARRAY_SIZE(snd_endpoints_list),
+};
+
+static struct platform_device vogue_snd_device = {
+	.name = "mixer",
+	.id = -1,
+	.dev = {
+		.platform_data = &vogue_snd_device,
+	},
+};
+
+static struct resource jz_i2c0_resources[] = {
+	[0] = {
+		.start          = CPHYSADDR(I2C0_BASE),
+		.end            = CPHYSADDR(I2C0_BASE) + 0x1000 - 1,
+		.flags          = IORESOURCE_MEM,
+	},
+	[1] = {
+		.start          = IRQ_I2C0,
+		.end            = IRQ_I2C0,
+		.flags          = IORESOURCE_IRQ,
+	},
+};
+
+static struct resource jz_i2c1_resources[] = {
+	[0] = {
+		.start          = CPHYSADDR(I2C1_BASE),
+		.end            = CPHYSADDR(I2C1_BASE) + 0x1000 - 1,
+		.flags          = IORESOURCE_MEM,
+	},
+	[1] = {
+		.start          = IRQ_I2C1,
+		.end            = IRQ_I2C1,
+		.flags          = IORESOURCE_IRQ,
+	},
+};
+
+static u64 jz_i2c_dmamask =  ~(u32)0;
+
+static struct platform_device jz_i2c0_device = {
+	.name = "jz_i2c0",
+	.id = 0,
+	.dev = {
+		.dma_mask               = &jz_i2c_dmamask,
+		.coherent_dma_mask      = 0xffffffff,
+	},
+	.num_resources  = ARRAY_SIZE(jz_i2c0_resources),
+	.resource       = jz_i2c0_resources,
+};
+
+static struct platform_device jz_i2c1_device = {
+	.name = "jz_i2c1",
+	.id = 1,
+	.dev = {
+		.dma_mask               = &jz_i2c_dmamask,
+		.coherent_dma_mask      = 0xffffffff,
+	},
+	.num_resources  = ARRAY_SIZE(jz_i2c1_resources),
+	.resource       = jz_i2c1_resources,
+};
+
+static struct platform_device rtc_device = {
+	.name		= "jz4760b-rtc",
+	.id		= -1,
+};
+///////////////////////////////////
+/* SSI controller --- SPI (0) */
+#ifndef CONFIG_JZ_SPI_BOARD_INFO_REGISTER
+#define __jz_spi0_board_info 	NULL
+#define __jz_spi1_board_info 	NULL
+#else
+extern struct spi_board_info jz4760b_spi0_board_info[];
+extern struct spi_board_info jz4760b_spi1_board_info[];
+#define __jz_spi0_board_info 	&jz4760b_spi0_board_info[0]
+#define __jz_spi1_board_info 	&jz4760b_spi1_board_info[0]
+#endif
+
+#ifdef CONFIG_JZ_AX88796C
+/** AX88796C controller **/
+static struct resource ax88796c_resources[] = {
+	[0] = {
+		.start          = CPHYSADDR(0xb4000000),
+		.end            = CPHYSADDR(0xb4000000) + 0x6800 - 1,
+		.flags          = IORESOURCE_MEM,
+	},
+	[1] = {
+		.start          = GPIO_NET_INT + IRQ_GPIO_0,
+		.end            = GPIO_NET_INT + IRQ_GPIO_0,
+		.flags          = IORESOURCE_IRQ,
+	}
+};
+
+static u64 ax88796c_dmamask =  ~(u32)0;
+
+static struct platform_device ax88796c_dev = {
+	.name = "ax88796c",
+	.id = 0,
+	.dev = {
+		.dma_mask               = &ax88796c_dmamask,
+		.coherent_dma_mask      = 0xffffffff,
+	},
+	.num_resources  = ARRAY_SIZE(ax88796c_resources),
+	.resource       = ax88796c_resources,
+};
+#endif /* CONFIG_JZ_AX88796C */
+
+struct jz47xx_spi_info spi0_info_cfg = {
+	.chnl = 0,
+	.bus_num = 0,
+	.is_pllclk = 1,
+	.board_size = 2,				/* spi¨¦¨¨¡À?¨ºy??*/
+#ifdef CONFIG_JZ_SPI_BOARD_INFO_REGISTER
+	.board_info = __jz_spi0_board_info,
+#else
+	.board_info = NULL,
+#endif
+//	.set_cs = spi_gpio_cs,
+	.set_cs = NULL,
+	.pin_cs ={
+		PIN_SSI_CE0,
+//		32*2+31,				/*apus: GPC31 --- SW6 --- BOOT_SEL1 (dummy, example) */
+		32*4+16,				/*lepus: TP56 */
+	},
+};
+
+static struct resource jz_spi0_resource[] = {
+	[0] = {
+		.start          = CPHYSADDR(SSI0_BASE),
+		.end            = CPHYSADDR(SSI0_BASE) + 0x2000 - 1,
+		.flags 			= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start = IRQ_SSI0,
+		.end   = IRQ_SSI0,
+		.flags = IORESOURCE_IRQ,
+	}
+};
+static u64 jz_spi0_dmamask =  ~(u32)0;
+
+struct platform_device jz_spi0_device = {
+	.name		  = "jz47xx-spi0",
+	.id		  = 0,
+	.num_resources	  = ARRAY_SIZE(jz_spi0_resource),
+	.resource	  = jz_spi0_resource,
+        .dev              = {
+                .dma_mask = &jz_spi0_dmamask,
+                .coherent_dma_mask = 0xffffffffUL,
+                .platform_data = & spi0_info_cfg,
+        }
+};
+
+/* SSI controller --- SPI (1) */
+struct jz47xx_spi_info spi1_info_cfg = {
+	.chnl = 1,
+	.bus_num = 1,
+	.board_size = 1,
+#ifdef CONFIG_JZ_SPI_BOARD_INFO_REGISTER
+	.board_info = __jz_spi1_board_info,
+#else
+	.board_info = NULL,
+#endif
+//	.set_cs = spi_gpio_cs,
+	.set_cs = NULL,
+	.pins_config = NULL,
+	.pin_cs ={
+		PIN_SSI_CE0,
+	},
+};
+static struct resource jz_spi1_resource[] = {
+	[0] = {
+		.start          = CPHYSADDR(SSI1_BASE) + 0x2000,
+		.end            = CPHYSADDR(SSI1_BASE) + 0x4000 - 1,
+		.flags 			= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start = IRQ_SSI1,
+		.end   = IRQ_SSI1,
+		.flags = IORESOURCE_IRQ,
+	}
+};
+static u64 jz_spi1_dmamask =  ~(u32)0;
+
+struct platform_device jz_spi1_device = {
+	.name		  = "jz47xx-spi1",
+	.id		  = 1,
+	.num_resources	  = ARRAY_SIZE(jz_spi1_resource),
+	.resource	  = jz_spi1_resource,
+        .dev              = {
+                .dma_mask = &jz_spi1_dmamask,
+                .coherent_dma_mask = 0xffffffffUL,
+                .platform_data = & spi1_info_cfg,
+        }
+};
+
+/* All */
+static struct platform_device *jz_platform_devices[] __initdata = {
+	&jz_usb_ohci_device,
+	&jz_usb_otg_xceiv_device,
+	&jz_usb_otg_device,
+	&jz_lcd_device,
+	&vogue_snd_device,
+	&jz_i2c0_device,
+	&jz_i2c1_device,
+	// &jz_msc0_device,
+	// &jz_msc1_device,
+	&rtc_device,
+//	&jz_spi0_device,
+//	&jz_spi1_device,
+#ifdef CONFIG_JZ_AX88796C
+	&ax88796c_dev,
+#endif
+};
+
+extern void __init board_i2c_init(void);
+extern void __init board_spi_init(void);
+static int __init jz_platform_init(void)
+{
+	int ret = 0;
+
+	board_i2c_init();
+#ifndef CONFIG_JZ_SPI_BOARD_INFO_REGISTER
+	board_spi_init();
+#endif
+
+	ret = platform_add_devices(jz_platform_devices, ARRAY_SIZE(jz_platform_devices));
+#ifdef CONFIG_ANDROID_PMEM
+	platform_pmem_device_setup();
+#endif
+
+	printk("jz_platform_init\n");
+	board_msc_init();
+	return ret;
+}
+
+arch_initcall(jz_platform_init);
+
diff --git a/arch/mips/jz4760b/pm.c b/arch/mips/jz4760b/pm.c
new file mode 100644
index 00000000000..637b38b1d92
--- /dev/null
+++ b/arch/mips/jz4760b/pm.c
@@ -0,0 +1,426 @@
+/*
+ * linux/arch/mips/jz4760b/pm.c
+ *
+ * JZ4760B Power Management Routines
+ *
+ * Copyright (C) 2006 - 2010 Ingenic Semiconductor Inc.
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/pm.h>
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/suspend.h>
+#include <linux/proc_fs.h>
+#include <linux/sysctl.h>
+
+#include <asm/cacheops.h>
+#include <asm/jzsoc.h>
+
+#ifndef CONFIG_JZ_SYSTEM_AT_CARD
+#define CONFIG_PM_POWERDOWN_P0 y
+#else
+#undef CONFIG_PM_POWERDOWN_P0
+#endif
+#define JZ_PM_SIMULATE_BATTERY y
+
+#ifdef JZ_PM_SIMULATE_BATTERY
+#define CONFIG_BATTERY_JZ
+#define JZ_PM_BATTERY_SIMED
+#endif
+
+#if defined(CONFIG_RTC_DRV_JZ4760B) && defined(CONFIG_BATTERY_JZ)
+//extern unsigned long jz_read_bat(void);
+//extern int g_jz_battery_min_voltage;
+static unsigned int usr_alarm_data = 0;
+static int alarm_state = 0;
+#endif
+
+#undef DEBUG
+//#define DEBUG
+#ifdef DEBUG
+#define dprintk(x...)	printk(x)
+#else
+#define dprintk(x...)
+#endif
+
+extern void jz_board_do_sleep(unsigned long *ptr);
+extern void jz_board_do_resume(unsigned long *ptr);
+#if defined(CONFIG_PM_POWERDOWN_P0)
+extern void jz_cpu_sleep(void);
+extern void jz_cpu_resume(void);
+#endif
+#if defined(CONFIG_INPUT_WM831X_ON)
+extern void wm8310_power_off(void);
+#endif
+int jz_pm_do_hibernate(void)
+{
+	printk("Put CPU into hibernate mode.\n");
+#if defined(CONFIG_INPUT_WM831X_ON)
+	printk("The power will be off.\n");
+	wm8310_power_off();
+	while(1);
+#else
+
+	/* Mask all interrupts */
+	OUTREG32(INTC_ICMSR(0), 0xffffffff);
+	OUTREG32(INTC_ICMSR(1), 0x7ff);
+
+	/*
+	 * RTC Wakeup or 1Hz interrupt can be enabled or disabled
+	 * through  RTC driver's ioctl (linux/driver/char/rtc_jz.c).
+	 */
+
+	/* Set minimum wakeup_n pin low-level assertion time for wakeup: 100ms */
+	rtc_write_reg(RTC_HWFCR, HWFCR_WAIT_TIME(100));
+
+	/* Set reset pin low-level assertion time after wakeup: must  > 60ms */
+	rtc_write_reg(RTC_HRCR, HRCR_WAIT_TIME(60));
+
+	/* Scratch pad register to be reserved */
+	rtc_write_reg(RTC_HSPR, HSPR_RTCV);
+
+	/* clear wakeup status register */
+	rtc_write_reg(RTC_HWRSR, 0x0);
+
+	/* set wake up valid level as low  and disable rtc alarm wake up.*/
+        rtc_write_reg(RTC_HWCR,0x8);
+
+	/* Put CPU to hibernate mode */
+	rtc_write_reg(RTC_HCR, HCR_PD);
+
+	while (1) {
+		printk("We should NOT come here, please check the jz4760brtc.h!!!\n");
+	};
+#endif
+
+	/* We can't get here */
+	return 0;
+}
+
+
+#if defined(CONFIG_RTC_DRV_JZ4760B) && defined(CONFIG_BATTERY_JZ)
+static int alarm_remain = 0;
+//#define ALARM_TIME (3 * 60)
+#define ALARM_TIME (10 * 60)
+static inline void jz_save_alarm(void) {
+	uint32_t rtc_rtcsr = 0,rtc_rtcsar = 0;
+
+	rtc_rtcsar = rtc_read_reg(RTC_RTCSAR); /* second alarm register */
+	rtc_rtcsr = rtc_read_reg(RTC_RTCSR); /* second register */
+
+	alarm_remain = rtc_rtcsar - rtc_rtcsr;
+}
+
+static inline void jz_restore_alarm(void) {
+	if (alarm_remain > 0) {
+		rtc_write_reg(RTC_RTCSAR, rtc_read_reg(RTC_RTCSR) + alarm_remain);
+		rtc_set_reg(RTC_RTCCR,0x3<<2); /* alarm enable, alarm interrupt enable */
+	}
+}
+
+static void jz_set_alarm(void)
+{
+	uint32_t rtc_rtcsr = 0,rtc_rtcsar = 0;
+
+	rtc_rtcsar = rtc_read_reg(RTC_RTCSAR); /* second alarm register */
+	rtc_rtcsr = rtc_read_reg(RTC_RTCSR); /* second register */
+#if 0
+	if(rtc_rtcsar <= rtc_rtcsr) {
+#endif
+		printk("1\n");
+		rtc_write_reg(RTC_RTCSAR,rtc_rtcsr + ALARM_TIME);
+		rtc_set_reg(RTC_RTCCR,0x3<<2); /* alarm enable, alarm interrupt enable */
+//		alarm_state = 1;	       /* alarm on */
+#if 0
+	} else if(rtc_rtcsar > rtc_rtcsr + ALARM_TIME) {
+		printk("2\n");
+		usr_alarm_data = rtc_rtcsar;
+		rtc_write_reg(RTC_RTCSAR,rtc_rtcsr + ALARM_TIME);
+		rtc_set_reg(RTC_RTCCR,0x3<<2);
+		alarm_state = 1;
+	} else {	      /* ??? I have some questions here, when the cpu is sleeping, the time freezes, doesn't it?
+				 consider sleep->wakeup->sleep   --- by Lutts */
+		printk("3\n");
+		usr_alarm_data = 0;
+		rtc_set_reg(RTC_RTCCR,0x3<<2);
+		alarm_state = 0;
+	}
+#endif
+
+	rtc_rtcsar = rtc_read_reg(RTC_RTCSAR); /* second alarm register */
+	rtc_rtcsr = rtc_read_reg(RTC_RTCSR); /* second register */
+
+	printk("rtc_rtcsar = %u rtc_rtcsr = %u alarm_state = %d\n", rtc_rtcsar, rtc_rtcsr, alarm_state);
+}
+#undef ALARM_TIME
+#endif
+
+static int jz_pm_do_sleep(void)
+{
+	unsigned long nfcsr = REG_NEMC_NFCSR;
+	unsigned long opcr = INREG32(CPM_OPCR);
+	unsigned long icmr0 = INREG32(INTC_ICMR(0));
+	unsigned long icmr1 = INREG32(INTC_ICMR(1));
+	unsigned long sadc = INREG8(SADC_ADENA);
+	unsigned long sleep_gpio_save[7*(GPIO_PORT_NUM-1)];
+	unsigned long cpuflags;
+
+#if defined(CONFIG_RTC_DRV_JZ4760B) && defined(CONFIG_BATTERY_JZ)
+	jz_save_alarm();
+
+ __jz_pm_do_sleep_start:
+#endif
+ 	/* set SLEEP mode */
+	CMSREG32(CPM_LCR, LCR_LPM_SLEEP, LCR_LPM_MASK);
+
+	/* Save CPU irqs */
+	local_irq_save(cpuflags);
+
+        /* Disable nand flash */
+	REG_NEMC_NFCSR = ~0xff;
+
+        /* stop sadc */
+	SETREG8(SADC_ADENA,ADENA_POWER);
+	while ((INREG8(SADC_ADENA) & ADENA_POWER) != ADENA_POWER) {
+		dprintk("INREG8(SADC_ADENA) = 0x%x\n",INREG8(SADC_ADENA));
+		udelay(100);
+	}
+
+        /* stop uhc */
+	SETREG32(CPM_OPCR, OPCR_UHCPHY_DISABLE);
+
+	/* stop otg and gps */
+	CLRREG32(CPM_OPCR, OPCR_OTGPHY_ENABLE | OPCR_GPSEN);
+
+	/*power down gps and ahb1*/
+	//SETREG32(CPM_LCR, LCR_PDAHB1 | LCR_PDGPS);
+
+	//while(!(REG_CPM_LCR && LCR_PDAHB1S)) ;
+	//while(!(REG_CPM_LCR && LCR_PDGPSS)) ;
+
+	/* Mask all interrupts except rtc*/
+	OUTREG32(INTC_ICMSR(0), 0xffffffff);
+	OUTREG32(INTC_ICMSR(1), 0x7ff);
+
+#if defined(CONFIG_RTC_DRV_JZ4760B)
+	OUTREG32(INTC_ICMCR(1), 0x1);
+	jz_set_alarm();
+	__intc_ack_irq(IRQ_RTC);
+	__intc_unmask_irq(IRQ_RTC);
+	rtc_clr_reg(RTC_RTCCR,RTCCR_AF);
+#else
+	/* mask rtc interrupts */
+	OUTREG32(INTC_ICMSR(1), 0x1);
+#endif
+
+	/* Sleep on-board modules */
+	jz_board_do_sleep(sleep_gpio_save);
+
+	printk("control = 0x%08x icmr0 = 0x%08x icmr1 = 0x%08x\n",
+	       INREG32(RTC_RTCCR), INREG32(INTC_ICMR(0)), INREG32(INTC_ICMR(1)));
+
+#if 1
+	/* WAKEUP key */
+	__gpio_as_irq_fall_edge(GPIO_POWER_ON);
+	__gpio_unmask_irq(GPIO_POWER_ON);
+      	__intc_unmask_irq(IRQ_GPIO0 - (GPIO_POWER_ON/32));  /* unmask IRQ_GPIOn depends on GPIO_WAKEUP */
+#endif
+
+	/* disable externel clock Oscillator in sleep mode */
+	CLRREG32(CPM_OPCR, OPCR_O1SE);
+
+	/* select 32K crystal as RTC clock in sleep mode */
+	SETREG32(CPM_OPCR, OPCR_ERCS);
+
+#if 0 /*for cpu 336M 1:2:4*/
+	OUTREG32(CPM_PSWC0ST, 0);
+	OUTREG32(CPM_PSWC1ST, 6);
+	OUTREG32(CPM_PSWC2ST, 8);
+	OUTREG32(CPM_PSWC3ST, 0);
+#endif
+
+#if 1 /*for cpu 533M 1:2:4*/
+	OUTREG32(CPM_PSWC0ST, 0);
+	OUTREG32(CPM_PSWC1ST, 8);
+	OUTREG32(CPM_PSWC2ST, 11);
+	OUTREG32(CPM_PSWC3ST, 0);
+#endif
+
+#if defined(CONFIG_PM_POWERDOWN_P0)
+	printk("Shutdown P0\n");
+
+	/* power down the p0 */
+	SETREG32(CPM_OPCR, OPCR_PD);
+
+      	/* Clear previous reset status */
+	CLRREG32(CPM_RSR, RSR_PR | RSR_WR | RSR_P0R);
+
+       	/* Set resume return address */
+	OUTREG32(CPM_CPSPPR, 0x00005a5a);
+	udelay(1);
+	OUTREG32(CPM_CPSPR, virt_to_phys(jz_cpu_resume));
+
+	rtc_clr_reg(RTC_RTCCR,RTCCR_AF);
+
+	/* *** go zzz *** */
+	jz_cpu_sleep();
+#else
+	__asm__(".set\tmips3\n\t"
+		"sync\n\t"
+		"wait\n\t"
+		"nop\n\t"
+		"nop\n\t"
+		"nop\n\t"
+		"nop\n\t"
+		".set\tmips0");
+#endif
+
+
+	/*if power down p0 ,return from sleep.S*/
+
+	/* Restore to IDLE mode */
+	CMSREG32(CPM_LCR, LCR_LPM_IDLE, LCR_LPM_MASK);
+
+	/* Restore nand flash control register, it must be restored,
+	   because it will be clear to 0 in bootrom. */
+	REG_NEMC_NFCSR = nfcsr;
+
+
+	/* Restore interrupts FIXME:*/
+	OUTREG32(INTC_ICMR(0), icmr0);
+	OUTREG32(INTC_ICMR(1), icmr1);
+
+	/* Restore sadc */
+	OUTREG8(SADC_ADENA, sadc);
+
+	/* Resume on-board modules */
+	jz_board_do_resume(sleep_gpio_save);
+
+	/* Restore Oscillator and Power Control Register */
+	OUTREG32(CPM_OPCR, opcr);
+
+	/* Restore CPU interrupt flags */
+	local_irq_restore(cpuflags);
+
+	CLRREG32(CPM_RSR, RSR_PR | RSR_WR | RSR_P0R);
+
+	printk("===>Leave CPU Sleep\n");
+#if  defined(CONFIG_RTC_DRV_JZ4760B) && defined(CONFIG_BATTERY_JZ)
+	if((INREG32(RTC_RTCCR) & RTCCR_AF)) {
+		rtc_clr_reg(RTC_RTCCR,RTCCR_AF | RTCCR_AE | RTCCR_AIE);
+		if(!usr_alarm_data) /* restore usrs alarm state */
+			rtc_write_reg(RTC_RTCSAR,usr_alarm_data);
+#if 0
+		if(g_jz_battery_min_voltage > jz_read_bat()) /* Just for example, add your Battery check here */
+			pm_power_off();
+		else
+#endif
+			goto __jz_pm_do_sleep_start;
+	}
+#endif
+
+#if defined(CONFIG_RTC_DRV_JZ4760B) && defined(CONFIG_BATTERY_JZ)
+	jz_restore_alarm();
+#endif
+
+	return 0;
+}
+
+#define K0BASE  KSEG0
+void jz_flush_cache_all(void)
+{
+	unsigned long addr;
+
+	/* Clear CP0 TagLo */
+	asm volatile ("mtc0 $0, $28\n\t"::);
+
+	for (addr = K0BASE; addr < (K0BASE + 0x4000); addr += 32) {
+		asm volatile (
+			".set mips3\n\t"
+			" cache %0, 0(%1)\n\t"
+			".set mips2\n\t"
+			:
+			: "I" (Index_Writeback_Inv_D), "r"(addr));
+
+		asm volatile (
+			".set mips3\n\t"
+			" cache %0, 0(%1)\n\t"
+			".set mips2\n\t"
+			:
+			: "I" (Index_Store_Tag_I), "r"(addr));
+	}
+
+	asm volatile ("sync\n\t"::);
+
+	/* invalidate BTB */
+	asm volatile (
+		".set mips32\n\t"
+		" mfc0 %0, $16, 7\n\t"
+		" nop\n\t"
+		" ori $0, 2\n\t"
+		" mtc0 %0, $16, 7\n\t"
+		" nop\n\t"
+		".set mips2\n\t"
+		:
+		: "r"(addr));
+}
+
+void jz_pm_hibernate(void)
+{
+	jz_pm_do_hibernate();
+}
+
+int jz_pm_sleep(void)
+{
+	return jz_pm_do_sleep();
+}
+
+static int jz4760b_pm_valid(suspend_state_t state)
+{
+	return state == PM_SUSPEND_MEM;
+}
+
+/*
+ * Jz CPU enter save power mode
+ */
+static int jz4760b_pm_enter(suspend_state_t state)
+{
+	jz_pm_do_sleep();
+	return 0;
+}
+
+static struct platform_suspend_ops jz4760b_pm_ops = {
+	.valid		= jz4760b_pm_valid,
+	.enter		= jz4760b_pm_enter,
+};
+
+/*
+ * Initialize power interface
+ */
+int __init jz_pm_init(void)
+{
+	printk("Power Management for JZ\n");
+
+	suspend_set_ops(&jz4760b_pm_ops);
+	return 0;
+}
+
+#ifdef JZ_PM_BATTERY_SIMED
+#undef CONFIG_BATTERY_JZ
+#endif
+
diff --git a/arch/mips/jz4760b/proc.c b/arch/mips/jz4760b/proc.c
new file mode 100644
index 00000000000..12b772e1d06
--- /dev/null
+++ b/arch/mips/jz4760b/proc.c
@@ -0,0 +1,1261 @@
+/*
+ * linux/arch/mips/jz4760b/proc.c
+ *
+ * /proc/jz/ procfs for jz4760b on-chip modules.
+ *
+ * Copyright (C) 2006 Ingenic Semiconductor Inc.
+ * Author: <jlwei@ingenic.cn>
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/sysctl.h>
+#include <linux/proc_fs.h>
+#include <linux/page-flags.h>
+#include <asm/uaccess.h>
+#include <asm/pgtable.h>
+#include <asm/jzsoc.h>
+
+
+//#define DEBUG 1
+#undef DEBUG
+
+extern void jz4760b_fpu_init(unsigned int round);
+
+struct proc_dir_entry *proc_jz_root;
+
+/*
+ * DDRC Modules
+ */
+static int ddrc_read_proc (char *page, char **start, off_t off,
+			  int count, int *eof, void *data)
+{
+	int len = 0;
+
+	len += sprintf (page+len, "REG_DDRC_ST      0x%08x\n", REG_DDRC_ST);
+	len += sprintf (page+len, "REG_DDRC_CFG     0x%08x\n", REG_DDRC_CFG);
+	len += sprintf (page+len, "REG_DDRC_CTRL    0x%08x\n", REG_DDRC_CTRL);
+	len += sprintf (page+len, "REG_DDRC_LMR     0x%08x\n", REG_DDRC_LMR);
+	len += sprintf (page+len, "REG_DDRC_TIMING1 0x%08x\n", REG_DDRC_TIMING1);
+	len += sprintf (page+len, "REG_DDRC_TIMING2 0x%08x\n", REG_DDRC_TIMING2);
+	len += sprintf (page+len, "REG_DDRC_REFCNT  0x%08x\n", REG_DDRC_REFCNT);
+	len += sprintf (page+len, "REG_DDRC_DQS     0x%08x\n", REG_DDRC_DQS);
+	len += sprintf (page+len, "REG_DDRC_DQS_ADJ 0x%08x\n", REG_DDRC_DQS_ADJ);
+	len += sprintf (page+len, "REG_DDRC_MMAP0   0x%08x\n", REG_DDRC_MMAP0);
+	len += sprintf (page+len, "REG_DDRC_MMAP1   0x%08x\n", REG_DDRC_MMAP1);
+
+	return len;
+}
+
+/*
+ * Power Manager Module
+ */
+static int pmc_read_proc (char *page, char **start, off_t off,
+			  int count, int *eof, void *data)
+{
+	int len = 0;
+	unsigned long lcr = REG_CPM_LCR;
+//	unsigned long clkgr = REG_CPM_CLKGR;
+
+	len += sprintf (page+len, "Low Power Mode : %s\n",
+			((lcr & LCR_LPM_MASK) == (LCR_LPM_IDLE)) ?
+			"IDLE" : (((lcr & LCR_LPM_MASK) == (LCR_LPM_SLEEP)) ?
+				  "SLEEP" : "HIBERNATE"));
+	len += sprintf (page+len, "Doze Mode      : %s\n",
+			(lcr & LCR_DOZE) ? "on" : "off");
+	if (lcr & LCR_DOZE)
+		len += sprintf (page+len, "     duty      : %d\n", (int)((lcr & LCR_DUTY_MASK) >> LCR_DUTY_LSB));
+
+/*
+	len += sprintf (page+len, "AUX_CPU        : %s\n",
+			(clkgr & CPM_CLKGR_AUX_CPU) ? "stopped" : "running");
+	len += sprintf (page+len, "AHB1           : %s\n",
+			(clkgr & CPM_CLKGR_AHB1) ? "stopped" : "running");
+	len += sprintf (page+len, "IDCT           : %s\n",
+			(clkgr & CPM_CLKGR_IDCT) ? "stopped" : "running");
+	len += sprintf (page+len, "DB             : %s\n",
+			(clkgr & CPM_CLKGR_DB) ? "stopped" : "running");
+	len += sprintf (page+len, "ME             : %s\n",
+			(clkgr & CPM_CLKGR_ME) ? "stopped" : "running");
+	len += sprintf (page+len, "MC             : %s\n",
+			(clkgr & CPM_CLKGR_MC) ? "stopped" : "running");
+	len += sprintf (page+len, "TVE            : %s\n",
+			(clkgr & CPM_CLKGR_TVE) ? "stopped" : "running");
+	len += sprintf (page+len, "TSSI           : %s\n",
+			(clkgr & CPM_CLKGR_TSSI) ? "stopped" : "running");
+	len += sprintf (page+len, "IPU            : %s\n",
+			(clkgr & CPM_CLKGR_IPU) ? "stopped" : "running");
+	len += sprintf (page+len, "DMAC           : %s\n",
+			(clkgr & CPM_CLKGR_DMAC) ? "stopped" : "running");
+	len += sprintf (page+len, "UDC            : %s\n",
+			(clkgr & CPM_CLKGR_UDC) ? "stopped" : "running");
+	len += sprintf (page+len, "LCD            : %s\n",
+			(clkgr & CPM_CLKGR_LCD) ? "stopped" : "running");
+	len += sprintf (page+len, "CIM            : %s\n",
+			(clkgr & CPM_CLKGR_CIM) ? "stopped" : "running");
+	len += sprintf (page+len, "SADC           : %s\n",
+			(clkgr & CPM_CLKGR_SADC) ? "stopped" : "running");
+	len += sprintf (page+len, "MSC0           : %s\n",
+			(clkgr & CPM_CLKGR_MSC0) ? "stopped" : "running");
+	len += sprintf (page+len, "MSC1           : %s\n",
+			(clkgr & CPM_CLKGR_MSC1) ? "stopped" : "running");
+	len += sprintf (page+len, "SSI           : %s\n",
+			(clkgr & CPM_CLKGR_SSI) ? "stopped" : "running");
+	len += sprintf (page+len, "I2C            : %s\n",
+			(clkgr & CPM_CLKGR_I2C) ? "stopped" : "running");
+	len += sprintf (page+len, "RTC            : %s\n",
+			(clkgr & CPM_CLKGR_RTC) ? "stopped" : "running");
+	len += sprintf (page+len, "TCU            : %s\n",
+			(clkgr & CPM_CLKGR_TCU) ? "stopped" : "running");
+	len += sprintf (page+len, "UART1          : %s\n",
+			(clkgr & CPM_CLKGR_UART1) ? "stopped" : "running");
+	len += sprintf (page+len, "UART0          : %s\n",
+			(clkgr & CPM_CLKGR_UART0) ? "stopped" : "running");
+*/
+	return len;
+}
+
+static int pmc_write_proc(struct file *file, const char *buffer, unsigned long count, void *data)
+{
+	REG_CPM_CLKGR = simple_strtoul(buffer, 0, 16);
+	return count;
+}
+
+/*
+ * Clock Generation Module
+ */
+#define TO_MHZ(x) (x/1000000),(x%1000000)/10000
+#define TO_KHZ(x) (x/1000),(x%1000)/10
+
+static int cgm_read_proc (char *page, char **start, off_t off,
+			  int count, int *eof, void *data)
+{
+	int len = 0;
+	unsigned int cppcr = REG_CPM_CPPCR0;  /* PLL Control Register */
+	unsigned int cpccr = REG_CPM_CPCCR;  /* Clock Control Register */
+	unsigned int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
+	unsigned int od[4] = {1, 2, 2, 4};
+
+	len += sprintf (page+len, "CPPCR          : 0x%08x\n", cppcr);
+	len += sprintf (page+len, "CPCCR          : 0x%08x\n", cpccr);
+	len += sprintf (page+len, "PLL            : %s\n",
+			(cppcr & CPPCR0_PLLEN) ? "ON" : "OFF");
+
+	len += sprintf (page+len, "m:n:o          : %d:%d:%d\n",
+			__cpm_get_pllm() + 2,
+			__cpm_get_plln() + 2,
+			od[__cpm_get_pllod()]
+		);
+	len += sprintf (page+len, "C:H:M:P        : %d:%d:%d:%d\n",
+			div[__cpm_get_cdiv()],
+			div[__cpm_get_hdiv()],
+			div[__cpm_get_mdiv()],
+			div[__cpm_get_pdiv()]
+		);
+	len += sprintf (page+len, "PLL Freq        : %3d.%02d MHz\n", TO_MHZ(cpm_get_pllout()));
+	len += sprintf (page+len, "CCLK            : %3d.%02d MHz\n", TO_MHZ(cpm_get_clock(CGU_CCLK)));
+	len += sprintf (page+len, "HCLK            : %3d.%02d MHz\n", TO_MHZ(cpm_get_clock(CGU_HCLK)));
+	len += sprintf (page+len, "MCLK            : %3d.%02d MHz\n", TO_MHZ(cpm_get_clock(CGU_MCLK)));
+	len += sprintf (page+len, "PCLK            : %3d.%02d MHz\n", TO_MHZ(cpm_get_clock(CGU_PCLK)));
+	len += sprintf (page+len, "H2CLK           : %3d.%02d MHz\n", TO_MHZ(cpm_get_clock(CGU_H2CLK)));
+	len += sprintf (page+len, "PIXCLK          : %3d.%02d KHz\n", TO_KHZ(cpm_get_clock(CGU_TVECLK)));
+	len += sprintf (page+len, "I2SCLK          : %3d.%02d MHz\n", TO_MHZ(cpm_get_clock(CGU_I2SCLK)));
+	len += sprintf (page+len, "USBCLK          : %3d.%02d MHz\n", TO_MHZ(cpm_get_clock(CGU_OTGCLK)));
+	len += sprintf (page+len, "MSC0CLK         : %3d.%02d MHz\n", TO_MHZ(cpm_get_clock(CGU_MSCCLK)));
+	len += sprintf (page+len, "MSC1CLK         : %3d.%02d MHz\n", TO_MHZ(cpm_get_clock(CGU_MSCCLK)));
+	// len += sprintf (page+len, "EXTALCLK0       : %3d.%02d MHz\n", TO_MHZ(cpm_get_clock(CGU_EXTCLK)));
+	// len += sprintf (page+len, "EXTALCLK(by CPM): %3d.%02d MHz\n", TO_MHZ(get_external_clock()));
+	// len += sprintf (page+len, "RTCCLK          : %3d.%02d MHz\n", TO_MHZ(cpm_get_clock(CGU_RTCCLK)));
+	return len;
+}
+
+static int cgm_write_proc(struct file *file, const char *buffer, unsigned long count, void *data)
+{
+	REG_CPM_CPCCR = simple_strtoul(buffer, 0, 16);
+	return count;
+}
+
+
+/* USAGE:
+ * echo n  > /proc/jz/ipu 	// n = [1,...,9], alloc mem, 2^n pages.
+ * echo FF > /proc/jz/ipu 	// 255, free all buffer
+ * echo xxxx > /proc/jz/ipu 	// free buffer which addr is xxxx
+ * echo llll > /proc/jz/ipu 	// add_wired_entry(l,l,l,l)
+ * echo 0  > /proc/jz/ipu 	// debug, print ipu_buf
+ * od -X /proc/jz/ipu 		// read mem addr
+ */
+
+typedef struct _ipu_buf {
+	unsigned int addr;	/* phys addr */
+	unsigned int page_shift;
+} ipu_buf_t;
+
+#define IPU_BUF_MAX 		4 	/* 4 buffers */
+
+static struct _ipu_buf ipu_buf[IPU_BUF_MAX];
+static int ipu_buf_cnt = 0;
+static unsigned char g_asid=0;
+
+extern void local_flush_tlb_all(void);
+
+/* CP0 hazard avoidance. */
+#define BARRIER __asm__ __volatile__(".set noreorder\n\t" \
+				     "nop; nop; nop; nop; nop; nop;\n\t" \
+				     ".set reorder\n\t")
+void show_tlb(void)
+{
+#define ASID_MASK 0xFF
+
+        unsigned long flags;
+        unsigned int old_ctx;
+	unsigned int entry;
+	unsigned int entrylo0, entrylo1, entryhi;
+	unsigned int pagemask;
+
+	local_irq_save(flags);
+
+	/* Save old context */
+	old_ctx = (read_c0_entryhi() & 0xff);
+
+	printk("TLB content:\n");
+	entry = 0;
+	while(entry < 32) {
+		write_c0_index(entry);
+		BARRIER;
+		tlb_read();
+		BARRIER;
+		entryhi = read_c0_entryhi();
+		entrylo0 = read_c0_entrylo0();
+		entrylo1 = read_c0_entrylo1();
+		pagemask = read_c0_pagemask();
+		printk("%02d: ASID=%02d%s VA=0x%08x ", entry, entryhi & ASID_MASK, (entrylo0 & entrylo1 & 1) ? "(G)" : "   ", entryhi & ~ASID_MASK);
+		printk("PA0=0x%08x C0=%x %s%s%s\n", (entrylo0>>6)<<12, (entrylo0>>3) & 7, (entrylo0 & 4) ? "Dirty " : "", (entrylo0 & 2) ? "Valid " : "Invalid ", (entrylo0 & 1) ? "Global" : "");
+		printk("\t\t\t     PA1=0x%08x C1=%x %s%s%s\n", (entrylo1>>6)<<12, (entrylo1>>3) & 7, (entrylo1 & 4) ? "Dirty " : "", (entrylo1 & 2) ? "Valid " : "Invalid ", (entrylo1 & 1) ? "Global" : "");
+
+		printk("\t\tpagemask=0x%08x", pagemask);
+		printk("\tentryhi=0x%08x\n", entryhi);
+		printk("\t\tentrylo0=0x%08x", entrylo0);
+		printk("\tentrylo1=0x%08x\n", entrylo1);
+
+		entry++;
+	}
+	BARRIER;
+	write_c0_entryhi(old_ctx);
+
+	local_irq_restore(flags);
+}
+
+static void ipu_add_wired_entry(unsigned long pid,
+				unsigned long entrylo0, unsigned long entrylo1,
+				unsigned long entryhi, unsigned long pagemask)
+{
+	unsigned long flags;
+	unsigned long wired;
+	unsigned long old_pagemask;
+	unsigned long old_ctx;
+	struct task_struct *g, *p;
+
+	/* We will lock an 4MB page size entry to map the 4MB reserved IPU memory */
+	wired = read_c0_wired();
+	if (wired) return;
+
+	do_each_thread(g, p) {
+		if (p->pid == pid )
+			g_asid = p->mm->context[0];
+	} while_each_thread(g, p);
+
+
+	local_irq_save(flags);
+
+	entrylo0 = entrylo0 >> 6;   /* PFN */
+	entrylo0 |= 0x6 | (0 << 3); /* Write-through cacheable, dirty, valid */
+
+	/* Save old context and create impossible VPN2 value */
+	old_ctx = read_c0_entryhi() & 0xff;
+	old_pagemask = read_c0_pagemask();
+	wired = read_c0_wired();
+	write_c0_wired(wired + 1);
+	write_c0_index(wired);
+	BARRIER;
+	entryhi &= ~0xff;	/* new add, 20070906 */
+	entryhi |= g_asid;	/* new add, 20070906 */
+//	entryhi |= old_ctx;	/* new add, 20070906 */
+	write_c0_pagemask(pagemask);
+	write_c0_entryhi(entryhi);
+	write_c0_entrylo0(entrylo0);
+	write_c0_entrylo1(entrylo1);
+	BARRIER;
+	tlb_write_indexed();
+	BARRIER;
+
+	write_c0_entryhi(old_ctx);
+	BARRIER;
+	write_c0_pagemask(old_pagemask);
+	local_flush_tlb_all();
+	local_irq_restore(flags);
+#if defined(DEBUG)
+	printk("\nold_ctx=%03d\n", old_ctx);
+
+	show_tlb();
+#endif
+}
+
+static void ipu_del_wired_entry( void )
+{
+	unsigned long flags;
+	unsigned long wired;
+
+	local_irq_save(flags);
+	wired = read_c0_wired();
+	if ( wired > 0 ) {
+		write_c0_wired(wired - 1);
+	}
+	local_irq_restore(flags);
+}
+
+static inline void ipu_buf_get( unsigned int page_shift )
+{
+	unsigned char * virt_addr;
+	int i;
+	for ( i=0; i< IPU_BUF_MAX; ++i ) {
+		if ( ipu_buf[i].addr == 0 ) {
+			break;
+		}
+	}
+
+	if ( (ipu_buf_cnt = i) == IPU_BUF_MAX ) {
+		printk("Error, no free ipu buffer.\n");
+		return ;
+	}
+
+	virt_addr =  (unsigned char *)__get_free_pages(GFP_KERNEL, page_shift);
+
+	if ( virt_addr ) {
+		ipu_buf[ipu_buf_cnt].addr = (unsigned int)virt_to_phys((void *)virt_addr);
+		ipu_buf[ipu_buf_cnt].page_shift = page_shift;
+
+		for (i = 0; i < (1<<page_shift); i++) {
+			SetPageReserved(virt_to_page(virt_addr));
+			virt_addr += PAGE_SIZE;
+		}
+	}
+	else {
+		printk("get memory Failed.\n");
+	}
+}
+
+static inline void ipu_buf_free( unsigned int phys_addr )
+{
+	unsigned char * virt_addr, *addr;
+	int cnt, i;
+
+	if ( phys_addr == 0 )
+		return ;
+
+	for ( cnt=0; cnt<IPU_BUF_MAX; ++cnt )
+		if ( phys_addr == ipu_buf[cnt].addr )
+			break;
+
+	if ( cnt == IPU_BUF_MAX ) {	/* addr not in the ipu buffers */
+		printk("Invalid addr:0x%08x\n", (unsigned int)phys_addr);
+	}
+
+	virt_addr = (unsigned char *)phys_to_virt(ipu_buf[cnt].addr);
+	addr = virt_addr;
+	for (i = 0; i < (1<<ipu_buf[cnt].page_shift); i++) {
+		ClearPageReserved(virt_to_page(addr));
+		addr += PAGE_SIZE;
+	}
+
+	if ( cnt == 0 )
+		ipu_del_wired_entry();
+
+	free_pages((unsigned long )virt_addr, ipu_buf[cnt].page_shift);
+
+	ipu_buf[cnt].addr = 0;
+	ipu_buf[cnt].page_shift = 0;
+}
+
+static int ipu_read_proc (char *page, char **start, off_t off,
+			  int count, int *eof, void *data)
+{
+	int len = 0;
+
+	/* read as binary */
+	unsigned int * pint;
+	pint = (unsigned int *) (page+len);
+
+	if ( ipu_buf_cnt >= IPU_BUF_MAX ) {	/* failed alloc mem, rturn 0 */
+		printk("no free buffer.\n");
+		*pint = 0;
+	}
+	else
+		*pint = (unsigned int )ipu_buf[ipu_buf_cnt].addr; /* phys addr */
+	len += sizeof(unsigned int);
+
+#if defined(DEBUG)
+		show_tlb();
+#endif
+	return len;
+
+}
+
+static int ipu_write_proc(struct file *file, const char *buffer, unsigned long count, void *data)
+{
+	unsigned int val ;
+	int cnt,i;
+	char buf[12];
+	unsigned long pid, entrylo0, entrylo1, entryhi, pagemask;
+#if defined(DEBUG)
+	printk("ipu write count=%u\n", count);
+#endif
+	if (count == (8*5+1)) {
+		for (i=0;i<12;i++) buf[i]=0;
+		strncpy(buf, buffer+8*0, 8);
+		pid = simple_strtoul(buf, 0, 16);
+		for (i=0;i<12;i++) buf[i]=0;
+		strncpy(buf, buffer+8*1, 8);
+		entrylo0 = simple_strtoul(buf, 0, 16);
+		for (i=0;i<12;i++) buf[i]=0;
+		strncpy(buf, buffer+8*2, 8);
+		entrylo1 = simple_strtoul(buf, 0, 16);
+		for (i=0;i<12;i++) buf[i]=0;
+		strncpy(buf, buffer+8*3, 8);
+		entryhi = simple_strtoul(buf, 0, 16);
+		for (i=0;i<12;i++) buf[i]=0;
+		strncpy(buf, buffer+8*4, 8);
+		pagemask = simple_strtoul(buf, 0, 16);
+
+#if defined(DEBUG)
+		printk("pid=0x%08x, entrylo0=0x%08x, entrylo1=0x%08x, entryhi=0x%08x, pagemask=0x%08x\n",
+		       pid, entrylo0, entrylo1, entryhi, pagemask);
+#endif
+		ipu_add_wired_entry( pid, entrylo0, entrylo1, entryhi, pagemask);
+		return 41;
+	}
+	else if ( count <= 8+1 ) {
+		for (i=0;i<12;i++) buf[i]=0;
+		strncpy(buf, buffer, 8);
+		val = simple_strtoul(buf, 0, 16);
+	} else if (count == 44) {
+		for (i = 0; i < 12; i++)
+			buf[i] = 0;
+		strncpy(buf, buffer, 10);
+		pid = simple_strtoul(buf, 0, 16);
+		for (i = 0; i < 12; i++)
+			buf[i] = 0;
+		strncpy(buf, buffer + 11, 10);
+		entryhi = simple_strtoul(buf, 0, 16);//vaddr
+		for (i = 0; i < 12; i++)
+			buf[i] = 0;
+		strncpy(buf, buffer + 22, 10);
+		entrylo0 = simple_strtoul(buf, 0, 16);//paddr
+		for (i = 0; i < 12; i++)
+			buf[i] = 0;
+		strncpy(buf, buffer + 33, 10);
+		pagemask = simple_strtoul(buf, 0, 16);
+		pagemask = 0x3ff << 13; /* Fixed to 4MB page size */
+		ipu_add_wired_entry(pid, entrylo0, 0, entryhi, pagemask);
+		return 44;
+	} else {
+		printk("ipu write count error, count=%d\n.", (unsigned int)count);
+		return -1;
+	}
+
+	/* val: 1-9, page_shift,  val>= 10: ipu_buf.addr */
+	if ( val == 0 ) {	/* debug, print ipu_buf info */
+		for ( cnt=0; cnt<IPU_BUF_MAX; ++cnt)
+			printk("ipu_buf[%d]: addr=0x%08x, page_shift=%d\n",
+			       cnt, ipu_buf[cnt].addr, ipu_buf[cnt].page_shift );
+#if defined(DEBUG)
+		show_tlb();
+#endif
+	}
+	else if ( 0< val && val < 10 ) {
+		ipu_buf_get(val);
+	}
+	else if ( val == 0xff ) { /* 255: free all ipu_buf */
+		for ( cnt=0; cnt<IPU_BUF_MAX; ++cnt ) {
+			ipu_buf_free(ipu_buf[cnt].addr);
+		}
+	}
+	else {
+		ipu_buf_free(val);
+	}
+
+	return count;
+}
+
+/*
+ * UDC hotplug
+ */
+#ifdef CONFIG_JZ_UDC_HOTPLUG
+extern int jz_udc_active;	/* defined in drivers/char/jzchar/jz_udc_hotplug.c */
+#endif
+
+#ifndef GPIO_UDC_HOTPLUG
+#define GPIO_UDC_HOTPLUG 86
+#endif
+
+static int udc_read_proc(char *page, char **start, off_t off,
+			 int count, int *eof, void *data)
+{
+        int len = 0;
+
+	if (__gpio_get_pin(GPIO_UDC_HOTPLUG)) {
+
+#ifdef CONFIG_JZ_UDC_HOTPLUG
+
+		/* Cable has connected, wait for disconnection. */
+		__gpio_as_irq_fall_edge(GPIO_UDC_HOTPLUG);
+
+		if (jz_udc_active)
+			len += sprintf (page+len, "CONNECT_CABLE\n");
+		else
+			len += sprintf (page+len, "CONNECT_POWER\n");
+#else
+		len += sprintf (page+len, "CONNECT\n");
+#endif
+	}
+	else {
+
+#ifdef CONFIG_JZ_UDC_HOTPLUG
+		/* Cable has disconnected, wait for connection. */
+		__gpio_as_irq_rise_edge(GPIO_UDC_HOTPLUG);
+#endif
+
+		len += sprintf (page+len, "REMOVE\n");
+	}
+
+        return len;
+}
+
+/*
+ * MMC/SD hotplug
+ */
+
+#ifndef MSC_HOTPLUG_PIN
+#define MSC_HOTPLUG_PIN 90
+#endif
+
+static int mmc_read_proc (char *page, char **start, off_t off,
+                          int count, int *eof, void *data)
+{
+        int len = 0;
+
+        if (__gpio_get_pin(MSC_HOTPLUG_PIN))
+                len += sprintf (page+len, "REMOVE\n");
+        else
+                len += sprintf (page+len, "INSERT\n");
+
+        return len;
+}
+
+#ifndef CONFIG_ANDROID_PMEM	/* /dev/pmem instead /proc/jz/imem on android platform */
+
+/***********************************************************************
+ * IPU memory management (used by mplayer and other apps)
+ *
+ * We reserved 16MB memory for IPU
+ * The memory base address is jz_ipu_framebuf
+ */
+
+/* Usage:
+ *
+ * echo n  > /proc/jz/imem 		// n = [0,...,10], allocate memory, 2^n pages
+ * echo xxxxxxxx > /proc/jz/imem	// free buffer which addr is xxxxxxxx
+ * echo FF > /proc/jz/ipu 		// FF, free all buffers
+ * od -X /proc/jz/imem 			// return the allocated buffer address and the max order of free buffer
+ */
+
+//#define DEBUG_IMEM 1
+
+#define IMEM_MAX_ORDER 13		/* max 2^13 * 4096 = 32MB */
+
+static unsigned int jz_imem_base;	/* physical base address of ipu memory */
+
+static unsigned int allocated_phys_addr = 0;
+
+/*
+ * Allocated buffer list
+ */
+typedef struct imem_list {
+	unsigned int phys_start;	/* physical start addr */
+	unsigned int phys_end;		/* physical end addr */
+	struct imem_list *next;
+} imem_list_t;
+
+static struct imem_list *imem_list_head = NULL; /* up sorted by phys_start */
+
+#define IMEM1_MAX_ORDER 12              /* max 2^12 * 4096 = 16MB */
+static unsigned int jz_imem1_base;      /* physical base address of ipu memory */
+static unsigned int allocated_phys_addr1 = 0;
+static struct imem_list *imem1_list_head = NULL; /* up sorted by phys_start */
+
+
+#ifdef DEBUG_IMEM
+static void dump_imem_list(void)
+{
+	struct imem_list *imem;
+
+	printk("*** dump_imem_list 0x%x ***\n", (u32)imem_list_head);
+	imem = imem_list_head;
+	while (imem) {
+		printk("imem=0x%x phys_start=0x%x phys_end=0x%x next=0x%x\n", (u32)imem, imem->phys_start, imem->phys_end, (u32)imem->next);
+		imem = imem->next;
+	}
+
+        printk("*** dump_imem_list 0x%x ***\n", (u32)imem1_list_head);
+        imem = imem1_list_head;
+        while (imem) {
+                printk("imem=0x%x phys_start=0x%x phys_end=0x%x next=0x%x\n", (u32)imem, imem->phys_start, imem->phys_end, (u32)imem->next);
+                imem = imem->next;
+        }
+}
+#endif
+
+/* allocate 2^order pages inside the 16MB memory */
+static int imem_alloc(unsigned int order)
+{
+	int alloc_ok = 0;
+	unsigned int start, end;
+	unsigned int size = (1 << order) * PAGE_SIZE;
+	struct imem_list *imem, *imemn, *imemp;
+
+	allocated_phys_addr = 0;
+
+	start = jz_imem_base;
+	end = start + (1 << IMEM_MAX_ORDER) * PAGE_SIZE;
+
+	imem = imem_list_head;
+	while (imem) {
+		if ((imem->phys_start - start) >= size) {
+			/* we got a valid address range */
+			alloc_ok = 1;
+			break;
+		}
+
+		start = imem->phys_end + 1;
+		imem = imem->next;
+	}
+
+	if (!alloc_ok) {
+		if ((end - start) >= size)
+			alloc_ok = 1;
+	}
+
+	if (alloc_ok) {
+		end = start + size - 1;
+		allocated_phys_addr = start;
+
+		/* add to imem_list, up sorted by phys_start */
+		imemn = kmalloc(sizeof(struct imem_list), GFP_KERNEL);
+		if (!imemn) {
+			return -ENOMEM;
+		}
+		imemn->phys_start = start;
+		imemn->phys_end = end;
+		imemn->next = NULL;
+
+		if (!imem_list_head)
+			imem_list_head = imemn;
+		else {
+			imem = imemp = imem_list_head;
+			while (imem) {
+				if (start < imem->phys_start) {
+					break;
+				}
+
+				imemp = imem;
+				imem = imem->next;
+			}
+
+			if (imem == imem_list_head) {
+				imem_list_head = imemn;
+				imemn->next = imem;
+			}
+			else {
+				imemn->next = imemp->next;
+				imemp->next = imemn;
+			}
+		}
+	}
+
+#ifdef DEBUG_IMEM
+	dump_imem_list();
+#endif
+	return 0;
+}
+
+/* allocate 2^order pages inside the 8MB memory */
+static int imem1_alloc(unsigned int order)
+{
+	int alloc_ok = 0;
+	unsigned int start, end;
+	unsigned int size = (1 << order) * PAGE_SIZE;
+	struct imem_list *imem, *imemn, *imemp;
+
+	allocated_phys_addr1 = 0;
+
+	start = jz_imem1_base;
+	end = start + (1 << IMEM1_MAX_ORDER) * PAGE_SIZE;
+
+	imem = imem1_list_head;
+	while (imem) {
+		if ((imem->phys_start - start) >= size) {
+			/* we got a valid address range */
+			alloc_ok = 1;
+			break;
+		}
+
+		start = imem->phys_end + 1;
+		imem = imem->next;
+	}
+
+	if (!alloc_ok) {
+		if ((end - start) >= size)
+			alloc_ok = 1;
+	}
+
+	if (alloc_ok) {
+		end = start + size - 1;
+		allocated_phys_addr1 = start;
+
+		/* add to imem_list, up sorted by phys_start */
+		imemn = kmalloc(sizeof(struct imem_list), GFP_KERNEL);
+		if (!imemn) {
+			return -ENOMEM;
+		}
+		imemn->phys_start = start;
+		imemn->phys_end = end;
+		imemn->next = NULL;
+
+		if (!imem1_list_head)
+			imem1_list_head = imemn;
+		else {
+			imem = imemp = imem1_list_head;
+			while (imem) {
+				if (start < imem->phys_start) {
+					break;
+				}
+
+				imemp = imem;
+				imem = imem->next;
+			}
+
+			if (imem == imem1_list_head) {
+				imem1_list_head = imemn;
+				imemn->next = imem;
+			}
+			else {
+				imemn->next = imemp->next;
+				imemp->next = imemn;
+			}
+		}
+	}
+
+#ifdef DEBUG_IMEM
+	dump_imem_list();
+#endif
+	return 0;
+}
+
+static void imem_free(unsigned int phys_addr)
+{
+	struct imem_list *imem, *imemp;
+
+	imem = imemp = imem_list_head;
+	while (imem) {
+		if (phys_addr == imem->phys_start) {
+			if (imem == imem_list_head) {
+				imem_list_head = imem->next;
+			}
+			else {
+				imemp->next = imem->next;
+			}
+
+			kfree(imem);
+			break;
+		}
+
+		imemp = imem;
+		imem = imem->next;
+	}
+
+        imem = imemp = imem1_list_head;
+        while (imem) {
+                if (phys_addr == imem->phys_start) {
+                        if (imem == imem1_list_head) {
+                                imem1_list_head = imem->next;
+                        }
+                        else {
+                                imemp->next = imem->next;
+                        }
+
+                        kfree(imem);
+                        break;
+                }
+
+                imemp = imem;
+                imem = imem->next;
+        }
+
+#ifdef DEBUG_IMEM
+	dump_imem_list();
+#endif
+}
+
+static void imem_free_all(void)
+{
+	struct imem_list *imem;
+
+	imem = imem_list_head;
+	while (imem) {
+		kfree(imem);
+		imem = imem->next;
+	}
+
+	imem_list_head = NULL;
+
+	allocated_phys_addr = 0;
+
+        imem = imem1_list_head;
+        while (imem) {
+                kfree(imem);
+                imem = imem->next;
+        }
+
+        imem1_list_head = NULL;
+
+        allocated_phys_addr1 = 0;
+
+#ifdef DEBUG_IMEM
+	dump_imem_list();
+#endif
+}
+
+/*
+ * Return the allocated buffer address and the max order of free buffer
+ */
+static int imem_read_proc(char *page, char **start, off_t off,
+			  int count, int *eof, void *data)
+{
+	int len = 0;
+	unsigned int start_addr, end_addr, max_order, max_size;
+	struct imem_list *imem;
+
+	unsigned int *tmp = (unsigned int *)(page + len);
+
+	start_addr = jz_imem_base;
+	end_addr = start_addr + (1 << IMEM_MAX_ORDER) * PAGE_SIZE;
+
+	if (!imem_list_head)
+		max_size = end_addr - start_addr;
+	else {
+		max_size = 0;
+		imem = imem_list_head;
+		while (imem) {
+			if (max_size < (imem->phys_start - start_addr))
+				max_size = imem->phys_start - start_addr;
+
+			start_addr = imem->phys_end + 1;
+			imem = imem->next;
+		}
+
+		if (max_size < (end_addr - start_addr))
+			max_size = end_addr - start_addr;
+	}
+
+	if (max_size > 0) {
+		max_order = get_order(max_size);
+		if (((1 << max_order) * PAGE_SIZE) > max_size)
+		    max_order--;
+	}
+	else {
+		max_order = 0xffffffff;	/* No any free buffer */
+	}
+
+	*tmp++ = allocated_phys_addr;	/* address allocated by 'echo n > /proc/jz/imem' */
+	*tmp = max_order;		/* max order of current free buffers */
+
+	len += 2 * sizeof(unsigned int);
+
+	return len;
+}
+
+static int div_write_proc(struct file *file, const char *buffer, unsigned long count, void *data)
+{
+#define Index_Writeback_Inv_D_PRIV	0x1c
+
+#define CPM_CPCCR_PCS                   (0x01 << 21)
+#define CPM_CPPCR_PLLS                  (1 << 10)
+
+
+#define CPM_CPCCR_SDIV_BIT              24
+#define CPM_CPCCR_H2DIV_BIT             16
+#define CPM_CPCCR_MDIV_BIT              12
+#define CPM_CPCCR_PDIV_BIT              8
+#define CPM_CPCCR_HDIV_BIT              4
+#define CPM_CPCCR_CDIV_BIT              0
+
+
+	unsigned int val;
+	unsigned long addr;
+	unsigned long cpuflags;
+	unsigned int cnt = 20;
+	int div[6] = {1, 2, 4, 4, 4, 4};
+	val = simple_strtoul(buffer, 0, 16);
+        register u32 cpccr = REG_CPM_CPCCR;
+
+        int n2FR[9] = {
+                0, 0, 1, 2, 3, 0, 4, 0, 5
+        };
+
+	if (val == 2) {
+		div[0] = 2;
+	}
+
+        cpccr &= ~(0xfffff | 0xf << 24);
+	cpccr =  CPM_CPCCR_PCS |
+		(n2FR[div[0]] << CPM_CPCCR_CDIV_BIT) |
+		(n2FR[div[1]] << CPM_CPCCR_HDIV_BIT) |
+		(n2FR[div[2]] << CPM_CPCCR_H2DIV_BIT) |
+		(n2FR[div[3]] << CPM_CPCCR_PDIV_BIT) |
+		(n2FR[div[4]] << CPM_CPCCR_MDIV_BIT) |
+		(n2FR[div[5]] << CPM_CPCCR_SDIV_BIT);
+
+	cpccr &= ~CPCCR_CE;
+
+	local_irq_save(cpuflags);
+
+	__asm__(".set noreorder");
+
+	addr = &&L1;
+//	__asm__("la %0, %1\n":"=r"(addr): "X"(&&L1));
+
+
+	asm volatile (
+                        ".set mips32\n\t"
+                        " cache %0, 0(%1)\n\t"
+                        ".set mips32\n\t"
+                        :
+                        : "I" (Index_Writeback_Inv_D_PRIV), "r"(addr));
+	
+	addr += 32;
+	asm volatile (
+                        ".set mips32\n\t"
+                        " cache %0, 0(%1)\n\t"
+                        ".set mips32\n\t"
+                        :
+                        : "I" (Index_Writeback_Inv_D_PRIV), "r"(addr));
+	
+	addr += 32;
+	asm volatile (
+                        ".set mips32\n\t"
+                        " cache %0, 0(%1)\n\t"
+                        ".set mips32\n\t"
+                        :
+                        : "I" (Index_Writeback_Inv_D_PRIV), "r"(addr));
+
+	addr += 32;
+	asm volatile (
+                        ".set mips32\n\t"
+                        " cache %0, 0(%1)\n\t"
+                        ".set mips32\n\t"
+                        :
+                        : "I" (Index_Writeback_Inv_D_PRIV), "r"(addr));
+	addr += 32;
+	asm volatile (
+                        ".set mips32\n\t"
+                        " cache %0, 0(%1)\n\t"
+                        ".set mips32\n\t"
+                        :
+                        : "I" (Index_Writeback_Inv_D_PRIV), "r"(addr));
+L1:
+	__asm__(".set\tmips3\n\t"
+                "sync\n\t"
+                "nop\n\t"
+                "nop\n\t"
+                "nop\n\t"
+                "nop\n\t"
+                ".set\tmips32");
+
+	REG_CPM_CPCCR &= ~CPCCR_CE;
+	REG_CPM_CPCCR = cpccr;
+	REG_CPM_CPPSR &= ~CPPSR_FS;
+	REG_CPM_CPPSR |= 1;
+	REG_CPM_CPCCR |= CPCCR_CE;
+	
+	do {
+		if (addr & 1)
+			goto L1;
+	} while(--cnt);
+
+	__asm__(".set\tmips3\n\t"
+                "nop\n\t"
+                "nop\n\t"
+                "nop\n\t"
+                "nop\n\t"
+                ".set\tmips32");
+	__asm__(".set reorder");
+
+	local_irq_restore(cpuflags);
+}
+static int imem_write_proc(struct file *file, const char *buffer, unsigned long count, void *data)
+{
+	unsigned int val;
+
+	val = simple_strtoul(buffer, 0, 16);
+
+	if (val == 0xff) {
+		/* free all memory */
+		imem_free_all();
+	}
+	else if ((val >= 0) && (val <= IMEM_MAX_ORDER)) {
+		/* allocate 2^val pages */
+		imem_alloc(val);
+	}
+	else {
+		/* free buffer which phys_addr is val */
+		imem_free(val);
+	}
+
+	return count;
+}
+
+/*
+ * Return the allocated buffer address and the max order of free buffer
+ */
+static int imem1_read_proc(char *page, char **start, off_t off,
+			  int count, int *eof, void *data)
+{
+	int len = 0;
+	unsigned int start_addr, end_addr, max_order, max_size;
+	struct imem_list *imem;
+
+	unsigned int *tmp = (unsigned int *)(page + len);
+
+	start_addr = jz_imem1_base;
+	end_addr = start_addr + (1 << IMEM1_MAX_ORDER) * PAGE_SIZE;
+
+	if (!imem1_list_head)
+		max_size = end_addr - start_addr;
+	else {
+		max_size = 0;
+		imem = imem1_list_head;
+		while (imem) {
+			if (max_size < (imem->phys_start - start_addr))
+				max_size = imem->phys_start - start_addr;
+
+			start_addr = imem->phys_end + 1;
+			imem = imem->next;
+		}
+
+		if (max_size < (end_addr - start_addr))
+			max_size = end_addr - start_addr;
+	}
+
+	if (max_size > 0) {
+		max_order = get_order(max_size);
+		if (((1 << max_order) * PAGE_SIZE) > max_size)
+		    max_order--;
+	}
+	else {
+		max_order = 0xffffffff;	/* No any free buffer */
+	}
+
+	*tmp++ = allocated_phys_addr1;	/* address allocated by 'echo n > /proc/jz/imem' */
+	*tmp = max_order;		/* max order of current free buffers */
+
+	len += 2 * sizeof(unsigned int);
+
+	return len;
+}
+
+static int imem1_write_proc(struct file *file, const char *buffer, unsigned long count, void *data)
+{
+	unsigned int val;
+
+	val = simple_strtoul(buffer, 0, 16);
+
+	if (val == 0xff) {
+		/* free all memory */
+		imem_free_all();
+		ipu_del_wired_entry();
+	} else if ((val >= 0) && (val <= IMEM1_MAX_ORDER)) {
+		/* allocate 2^val pages */
+		imem1_alloc(val);
+	} else {			
+		/* free buffer which phys_addr is val */
+		imem_free(val);
+	}
+
+	return count;
+}
+
+#endif	/* #ifndef CONFIG_ANDROID_PMEM */
+
+static int fpu_write_proc(struct file *file, const char *buffer, unsigned long count, void *data)
+{
+	printk("user set rounding mode to %x \n",(unsigned int)buffer);
+
+	if ((unsigned int)buffer > 4) {
+		printk("roundind mode error!\n");
+	}
+
+	jz4760b_fpu_init((unsigned int)buffer);
+	return count;
+}
+
+/*
+ * /proc/jz/xxx entry
+ *
+ */
+static int __init jz_proc_init(void)
+{
+	struct proc_dir_entry *res;
+#ifndef CONFIG_ANDROID_PMEM
+	unsigned int virt_addr, i;
+#endif
+
+	proc_jz_root = proc_mkdir("jz", 0);
+
+	/* Power Management Controller */
+	res = create_proc_entry("pmc", 0644, proc_jz_root);
+	if (res) {
+		res->read_proc = pmc_read_proc;
+		res->write_proc = pmc_write_proc;
+		res->data = NULL;
+	}
+
+	/* Clock Generation Module */
+	res = create_proc_entry("cgm", 0644, proc_jz_root);
+	if (res) {
+		res->read_proc = cgm_read_proc;
+		res->write_proc = cgm_write_proc;
+		res->data = NULL;
+	}
+
+	/* Image process unit */
+	res = create_proc_entry("ipu", 0644, proc_jz_root);
+	if (res) {
+		res->read_proc = ipu_read_proc;
+		res->write_proc = ipu_write_proc;
+		res->data = NULL;
+	}
+
+	res = create_proc_entry("div", 0644, proc_jz_root);
+	if (res) {
+		res->write_proc = div_write_proc;
+		res->data = NULL;
+	}
+
+	/* udc hotplug */
+	res = create_proc_entry("udc", 0644, proc_jz_root);
+	if (res) {
+		res->read_proc = udc_read_proc;
+		res->write_proc = NULL;
+		res->data = NULL;
+	}
+
+	/* mmc hotplug */
+	res = create_proc_entry("mmc", 0644, proc_jz_root);
+	if (res) {
+		res->read_proc = mmc_read_proc;
+		res->write_proc = NULL;
+		res->data = NULL;
+	}
+
+        /* DDR Controller */
+	res = create_proc_entry("ddrc", 0644, proc_jz_root);
+	if (res) {
+		res->read_proc = ddrc_read_proc;
+		res->write_proc = NULL;
+		res->data = NULL;
+	}
+
+#ifndef CONFIG_ANDROID_PMEM
+	/*
+	 * Reserve a 16MB memory for IPU on JZ4760B.
+	 */
+	jz_imem_base = (unsigned int)__get_free_pages(GFP_KERNEL, IMEM_MAX_ORDER);
+	if (jz_imem_base) {
+		/* imem (IPU memory management) */
+		res = create_proc_entry("imem", 0644, proc_jz_root);
+		if (res) {
+			res->read_proc = imem_read_proc;
+			res->write_proc = imem_write_proc;
+			res->data = NULL;
+		}
+
+		/* Set page reserved */
+		virt_addr = jz_imem_base;
+		for (i = 0; i < (1 << IMEM_MAX_ORDER); i++) {
+			SetPageReserved(virt_to_page((void *)virt_addr));
+			virt_addr += PAGE_SIZE;
+		}
+
+		/* Convert to physical address */
+		jz_imem_base = virt_to_phys((void *)jz_imem_base);
+
+		printk("Total %dMB memory at 0x%x was reserved for IPU\n",
+		       (unsigned int)((1 << IMEM_MAX_ORDER) * PAGE_SIZE)/1000000, jz_imem_base);
+	}
+        else
+           printk("NOT enough memory for imem\n");
+
+        jz_imem1_base = (unsigned int)__get_free_pages(GFP_KERNEL, IMEM1_MAX_ORDER);
+        if (jz_imem1_base) {
+                /* imem (IPU memory management) */
+                res = create_proc_entry("imem1", 0644, proc_jz_root);
+                if (res) {
+                        res->read_proc = imem1_read_proc;
+                        res->write_proc = imem1_write_proc;
+                        res->data = NULL;
+                }
+
+                /* Set page reserved */
+                virt_addr = jz_imem1_base;
+                for (i = 0; i < (1 << IMEM1_MAX_ORDER); i++) {
+                        SetPageReserved(virt_to_page((void *)virt_addr));
+                        virt_addr += PAGE_SIZE;
+                }
+
+                /* Convert to physical address */
+                jz_imem1_base = virt_to_phys((void *)jz_imem1_base);
+
+                printk("Total %dMB memory1 at 0x%x was reserved for IPU\n",
+                       (unsigned int)((1 << IMEM1_MAX_ORDER) * PAGE_SIZE)/1000000, jz_imem1_base);
+        } 
+        else
+           printk("NOT enough memory for imem1\n");
+
+#endif	/* #ifdef CONFIG_ANDROID_PMEM */
+
+	/* fpu */
+	res = create_proc_entry("fpu", 0644, proc_jz_root);
+	if (res) {
+		res->read_proc = NULL;
+		res->write_proc = fpu_write_proc;
+		res->data = NULL;
+	}
+
+	return 0;
+}
+
+__initcall(jz_proc_init);
diff --git a/arch/mips/jz4760b/prom.c b/arch/mips/jz4760b/prom.c
new file mode 100644
index 00000000000..be60cc1019b
--- /dev/null
+++ b/arch/mips/jz4760b/prom.c
@@ -0,0 +1,198 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ *    PROM library initialisation code, supports YAMON and U-Boot.
+ *
+ * Copyright 2000, 2001, 2006 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc.
+ *         	ppopov@mvista.com or source@mvista.com
+ *
+ * This file was derived from Carsten Langgaard's
+ * arch/mips/mips-boards/xx files.
+ *
+ * Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/string.h>
+
+#include <asm/bootinfo.h>
+#include <asm/jzsoc.h>
+
+/* #define DEBUG_CMDLINE */
+
+int prom_argc;
+char **prom_argv, **prom_envp;
+
+char * prom_getcmdline(void)
+{
+	return &(arcs_cmdline[0]);
+}
+
+void  prom_init_cmdline(void)
+{
+	char *cp;
+	int actr;
+
+	actr = 1; /* Always ignore argv[0] */
+
+	cp = &(arcs_cmdline[0]);
+	while(actr < prom_argc) {
+	        strcpy(cp, prom_argv[actr]);
+		cp += strlen(prom_argv[actr]);
+		*cp++ = ' ';
+		actr++;
+	}
+	if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */
+		--cp;
+	if (prom_argc > 1)
+		*cp = '\0';
+
+}
+
+
+char *prom_getenv(char *envname)
+{
+#if 0
+	/*
+	 * Return a pointer to the given environment variable.
+	 * YAMON uses "name", "value" pairs, while U-Boot uses "name=value".
+	 */
+
+	char **env = prom_envp;
+	int i = strlen(envname);
+	int yamon = (*env && strchr(*env, '=') == NULL);
+
+	while (*env) {
+		if (yamon) {
+			if (strcmp(envname, *env++) == 0)
+				return *env;
+		} else {
+			if (strncmp(envname, *env, i) == 0 && (*env)[i] == '=')
+				return *env + i + 1;
+		}
+		env++;
+	}
+#endif
+	return NULL;
+}
+
+inline unsigned char str2hexnum(unsigned char c)
+{
+	if(c >= '0' && c <= '9')
+		return c - '0';
+	if(c >= 'a' && c <= 'f')
+		return c - 'a' + 10;
+	if(c >= 'A' && c <= 'F')
+		return c - 'A' + 10;
+	return 0; /* foo */
+}
+
+inline void str2eaddr(unsigned char *ea, unsigned char *str)
+{
+	int i;
+
+	for(i = 0; i < 6; i++) {
+		unsigned char num;
+
+		if((*str == '.') || (*str == ':'))
+			str++;
+		num = str2hexnum(*str++) << 4;
+		num |= (str2hexnum(*str++));
+		ea[i] = num;
+	}
+}
+
+int get_ethernet_addr(char *ethernet_addr)
+{
+        char *ethaddr_str;
+
+        ethaddr_str = prom_getenv("ethaddr");
+	if (!ethaddr_str) {
+	        printk("ethaddr not set in boot prom\n");
+		return -1;
+	}
+	str2eaddr(ethernet_addr, ethaddr_str);
+
+#if 0
+	{
+		int i;
+
+	printk("get_ethernet_addr: ");
+	for (i=0; i<5; i++)
+		printk("%02x:", (unsigned char)*(ethernet_addr+i));
+	printk("%02x\n", *(ethernet_addr+i));
+	}
+#endif
+
+	return 0;
+}
+
+void __init prom_free_prom_memory(void)
+{
+}
+
+void __init prom_init(void)
+{
+	unsigned char *memsize_str;
+	unsigned long memsize;
+
+	prom_argc = (int) fw_arg0;
+	prom_argv = (char **) fw_arg1;
+	prom_envp = (char **) fw_arg2;
+
+	mips_machtype = MACH_INGENIC_JZ4760B;
+
+	prom_init_cmdline();
+	memsize_str = prom_getenv("memsize");
+	if (!memsize_str) {
+		memsize = 0x04000000;
+	} else {
+		memsize = simple_strtol(memsize_str, NULL, 0);
+	}
+	add_memory_region(0, memsize, BOOT_MEM_RAM);
+}
+
+/* used by early printk */
+void prom_putchar(char c)
+{
+	volatile u8 *uart_lsr = (volatile u8 *)(UART1_BASE + OFF_LSR);
+	volatile u8 *uart_tdr = (volatile u8 *)(UART1_BASE + OFF_TDR);
+
+	/* Wait for fifo to shift out some bytes */
+	while ( !((*uart_lsr & (UARTLSR_TDRQ | UARTLSR_TEMT)) == 0x60) );
+
+	*uart_tdr = (u8)c;
+}
+
+const char *get_system_type(void)
+{
+	return "JZ4760B";
+}
+
+EXPORT_SYMBOL(prom_getcmdline);
+EXPORT_SYMBOL(get_ethernet_addr);
+EXPORT_SYMBOL(str2eaddr);
diff --git a/arch/mips/jz4760b/reset.c b/arch/mips/jz4760b/reset.c
new file mode 100644
index 00000000000..bcdf3c63e37
--- /dev/null
+++ b/arch/mips/jz4760b/reset.c
@@ -0,0 +1,80 @@
+/*
+ * linux/arch/mips/jz4760b/reset.c
+ *
+ * JZ4760B reset routines.
+ *
+ * Copyright (c) 2006-2007  Ingenic Semiconductor Inc.
+ * Author: <yliu@ingenic.cn>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <asm/io.h>
+#include <asm/pgtable.h>
+#include <asm/processor.h>
+#include <asm/reboot.h>
+#include <asm/system.h>
+#include <asm/jzsoc.h>
+
+#define RECOVERY_SIGNATURE	0x52454359	/* means "RECOVERY" */
+void jz_restart(char *command)
+{
+#if 1
+	printk("Restarting after 4ms\n");
+#if defined(CONFIG_JZ_RECOVERY_SUPPORT)
+	if ((command != NULL) && !strcmp(command, "recovery")) {
+		printk("After restart will goto REVCOVERY mode!");
+		cpm_set_scrpad(RECOVERY_SIGNATURE);
+	} else {
+		cpm_set_scrpad(0);
+	}
+#endif
+
+	REG_WDT_WCSR = WCSR_PRESCALE4 | WCSR_CLKIN_EXT;
+	REG_WDT_WCNT = 0;
+	REG_WDT_WDR = JZ_EXTAL / 1000;   /* reset after 4ms */
+	REG_TCU_TSCR = TSCR_WDT; /* enable wdt clock */
+	REG_WDT_WCER = WCER_TCEN;  /* wdt start */
+#else
+	printk("Restarting after 1s\n");
+	/* clear wakeup status register */
+	rtc_write_reg(RTC_HWRSR, 0x0);
+
+	/* Scratch pad register to be reserved */
+	rtc_write_reg(RTC_HSPR, HSPR_RTCV);
+
+	/* RTC Alarm Wakeup Enable */
+	rtc_set_reg(RTC_HWCR, HWCR_EALM);
+
+	/* Set reset pin low-level assertion time after wakeup: must  > 60ms */
+	rtc_write_reg(RTC_HRCR, HRCR_WAIT_TIME(60));
+
+	/* Set minimum wakeup_n pin low-level assertion time for wakeup: 100ms */
+	rtc_write_reg(RTC_HWFCR, HWFCR_WAIT_TIME(100));
+
+	rtc_write_reg(RTC_RTCSAR, rtc_read_reg(RTC_RTCSR) + 1);
+	rtc_set_reg(RTC_RTCCR, RTCCR_AIE | RTCCR_AE | RTCCR_RTCE); /* alarm enable, alarm interrupt enable */
+
+	/* Put CPU to hibernate mode */
+	rtc_write_reg(RTC_HCR, HCR_PD);
+#endif
+	while (1);
+}
+
+void jz_halt(void)
+{
+	printk(KERN_NOTICE "\n** You can safely turn off the power\n");
+
+	while (1)
+		__asm__(".set\tmips3\n\t"
+	                "wait\n\t"
+			".set\tmips0");
+}
+
+void jz_power_off(void)
+{
+	jz_halt();
+}
diff --git a/arch/mips/jz4760b/setup.c b/arch/mips/jz4760b/setup.c
new file mode 100644
index 00000000000..55b4698c316
--- /dev/null
+++ b/arch/mips/jz4760b/setup.c
@@ -0,0 +1,212 @@
+/*
+ * linux/arch/mips/jz4760b/common/setup.c
+ *
+ * JZ4760B common setup routines.
+ *
+ * Copyright (C) 2006 Ingenic Semiconductor Inc.
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ */
+#include <linux/init.h>
+#include <linux/string.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/ioport.h>
+#include <linux/tty.h>
+#include <linux/serial.h>
+#include <linux/serial_core.h>
+#include <linux/serial_8250.h>
+
+#include <asm/cpu.h>
+#include <asm/bootinfo.h>
+#include <asm/irq.h>
+#include <asm/mipsregs.h>
+#include <asm/reboot.h>
+#include <asm/pgtable.h>
+#include <asm/time.h>
+#include <asm/jzsoc.h>
+
+#ifdef CONFIG_PM
+#include <asm/suspend.h>
+#endif
+
+#ifdef CONFIG_PC_KEYB
+#include <asm/keyboard.h>
+#endif
+
+jz_clocks_t jz_clocks;
+
+extern char * __init prom_getcmdline(void);
+extern void __init jz_board_setup(void);
+extern void jz_restart(char *);
+extern void jz_halt(void);
+extern void jz_power_off(void);
+extern void jz_time_init(void);
+extern void jz_pm_hibernate(void);
+
+static void __init sysclocks_setup(void)
+{
+#ifndef CONFIG_MIPS_JZ_EMURUS /* FPGA */
+
+	jz_clocks.cclk = cpm_get_clock(CGU_CCLK);
+	jz_clocks.hclk = cpm_get_clock(CGU_HCLK);
+	jz_clocks.pclk = cpm_get_clock(CGU_PCLK);
+	jz_clocks.mclk = cpm_get_clock(CGU_MCLK);
+	jz_clocks.h1clk = cpm_get_clock(CGU_H2CLK);
+	jz_clocks.pixclk = cpm_get_clock(CGU_LPCLK);
+	jz_clocks.i2sclk = cpm_get_clock(CGU_I2SCLK);
+	jz_clocks.otgclk = cpm_get_clock(CGU_OTGCLK);
+	jz_clocks.mscclk = cpm_get_clock(CGU_MSCCLK);
+	jz_clocks.extalclk = __cpm_get_extalclk();
+	jz_clocks.rtcclk = __cpm_get_rtcclk();
+
+#else
+
+#define FPGACLK 8000000
+
+	jz_clocks.cclk = FPGACLK;
+	jz_clocks.hclk = FPGACLK;
+	jz_clocks.pclk = FPGACLK;
+	jz_clocks.mclk = FPGACLK;
+	jz_clocks.h1clk = FPGACLK;
+	jz_clocks.pixclk = FPGACLK;
+	jz_clocks.i2sclk = FPGACLK;
+	jz_clocks.usbclk = FPGACLK;
+	jz_clocks.mscclk = FPGACLK;
+	jz_clocks.extalclk = FPGACLK;
+	jz_clocks.rtcclk = FPGACLK;
+#endif
+
+	printk("CPU clock: %dMHz, System clock: %dMHz, Peripheral clock: %dMHz, Memory clock: %dMHz\n",
+	       (jz_clocks.cclk + 500000) / 1000000,
+	       (jz_clocks.hclk + 500000) / 1000000,
+	       (jz_clocks.pclk + 500000) / 1000000,
+	       (jz_clocks.mclk + 500000) / 1000000);
+}
+
+static void __init soc_cpm_setup(void)
+{
+	/* Start all module clocks
+	 * cpm_start_clock(CGM_ALL_MODULE);
+	 */
+
+	/* Enable device DMA */
+	cpm_start_clock(CGM_DMAC);
+
+	/* CPU enters IDLE mode when executing 'wait' instruction */
+	CMSREG32(CPM_LCR, LCR_LPM_IDLE, LCR_LPM_MASK);
+
+	/* Setup system clocks */
+	sysclocks_setup();
+}
+
+static void __init soc_harb_setup(void)
+{
+//	__harb_set_priority(0x00);  /* CIM>LCD>DMA>ETH>PCI>USB>CBB */
+//	__harb_set_priority(0x03);  /* LCD>CIM>DMA>ETH>PCI>USB>CBB */
+//	__harb_set_priority(0x0a);  /* ETH>LCD>CIM>DMA>PCI>USB>CBB */
+}
+
+static void __init soc_dmac_setup(void)
+{
+	__dmac_enable_module(0);
+	__dmac_enable_module(1);
+}
+
+static void __init jz_soc_setup(void)
+{
+	soc_cpm_setup();
+	soc_harb_setup();
+	soc_dmac_setup();
+}
+
+static void __init jz_serial_setup(void)
+{
+#ifdef CONFIG_SERIAL_8250
+	struct uart_port s;
+	REG8(UART0_FCR) |= UARTFCR_UUE; /* enable UART module */
+	memset(&s, 0, sizeof(s));
+	s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
+	s.iotype = SERIAL_IO_MEM;
+	s.regshift = 2;
+	s.uartclk = jz_clocks.extalclk ;
+
+	s.line = 0;
+	s.membase = (u8 *)UART0_BASE;
+	s.irq = IRQ_UART0;
+	if (early_serial_setup(&s) != 0) {
+		printk(KERN_ERR "Serial ttyS0 setup failed!\n");
+	}
+
+	s.line = 1;
+	s.membase = (u8 *)UART1_BASE;
+	s.irq = IRQ_UART1;
+	if (early_serial_setup(&s) != 0) {
+		printk(KERN_ERR "Serial ttyS1 setup failed!\n");
+	}
+
+	s.line = 2;
+	s.membase = (u8 *)UART2_BASE;
+	s.irq = IRQ_UART2;
+
+	if (early_serial_setup(&s) != 0) {
+		printk(KERN_ERR "Serial ttyS2 setup failed!\n");
+	}
+
+	s.line = 3;
+	s.membase = (u8 *)UART3_BASE;
+	s.irq = IRQ_UART3;
+	if (early_serial_setup(&s) != 0) {
+		printk(KERN_ERR "Serial ttyS3 setup failed!\n");
+	}
+
+#endif
+}
+
+void __init plat_mem_setup(void)
+{
+	char *argptr;
+
+	argptr = prom_getcmdline();
+
+	__asm__ (
+		"li    $2, 0xa9000000 \n\t"
+		"mtc0  $2, $5, 4      \n\t"
+		"nop                  \n\t"
+		::"r"(2));
+
+	/* IO/MEM resources. Which will be the addtion value in `inX' and
+	 * `outX' macros defined in asm/io.h */
+	set_io_port_base(0);
+	ioport_resource.start	= 0x00000000;
+	ioport_resource.end	= 0xffffffff;
+	iomem_resource.start	= 0x00000000;
+	iomem_resource.end	= 0xffffffff;
+
+	_machine_restart = jz_restart;
+	_machine_halt = jz_halt;
+	pm_power_off = jz_pm_hibernate;
+
+	jz_soc_setup();
+	jz_serial_setup();
+	jz_board_setup();
+
+#ifdef CONFIG_PM
+	jz_pm_init();
+#endif
+
+}
+
diff --git a/arch/mips/jz4760b/sleep.S b/arch/mips/jz4760b/sleep.S
new file mode 100644
index 00000000000..b62fbfdec37
--- /dev/null
+++ b/arch/mips/jz4760b/sleep.S
@@ -0,0 +1,342 @@
+/*
+ * linux/arch/mips/jz4760/sleep.S
+ *
+ * jz4760 Assembler Sleep/WakeUp Management Routines
+ *
+ * Copyright (C) 2005 - 2010 Ingenic Semiconductor
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#define __MIPS_ASSEMBLER
+
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+#include <asm/cacheops.h>
+#include <asm/mach-jz4760/jz4760misc.h>
+#include <asm/mach-jz4760/jz4760cpm.h>
+#include <asm/mach-jz4760/jz4760emc.h>
+#include <asm/mach-jz4760/jz4760gpio.h>
+
+#define K0BASE 0x80000000
+#define CFG_DCACHE_SIZE  16384
+#define CFG_ICACHE_SIZE  16384
+#define CFG_CACHELINE_SIZE	32
+/**********************************************************/
+	.data
+	.align	4
+
+reg_save:
+	.space	70*4
+/*********************************************************/
+	.text
+	.set	noreorder
+	.set	noat
+	.extern jz_flush_cache_all
+
+/*
+ * jz_cpu_sleep()
+ *
+ * Forces CPU into sleep mode,and we will power down p0 in this mode!
+ */
+
+	.globl	jz_cpu_sleep
+jz_cpu_sleep:
+
+	/* save hi, lo and general registers except k0($26) and k1($27) (total 32) */
+	la	k0,	reg_save
+	mfhi	k1
+	sw	$0,	0(k0)
+	sw	$1,  	4(k0)
+	sw	k1,	120(k0)
+	mflo	k1
+	sw	$2,	8(k0)
+	sw	$3,  	12(k0)
+	sw	k1,	124(k0)
+	sw	$4,  	16(k0)
+	sw	$5,  	20(k0)
+	sw	$6,  	24(k0)
+	sw	$7,  	28(k0)
+	sw	$8,  	32(k0)
+	sw	$9,  	36(k0)
+	sw	$10, 	40(k0)
+	sw	$11, 	44(k0)
+	sw	$12, 	48(k0)
+	sw	$13, 	52(k0)
+	sw	$14, 	56(k0)
+	sw	$15, 	60(k0)
+	sw	$16, 	64(k0)
+	sw	$17, 	68(k0)
+	sw	$18, 	72(k0)
+	sw	$19, 	76(k0)
+	sw	$20, 	80(k0)
+	sw	$21, 	84(k0)
+	sw	$22, 	88(k0)
+	sw	$23, 	92(k0)
+	sw	$24, 	96(k0)
+	sw	$25, 	100(k0)
+	sw	$28, 	104(k0)
+	sw	$29, 	108(k0)		/* saved sp */
+	sw	$30, 	112(k0)
+	sw	$31, 	116(k0)		/* saved ra */
+
+	/* save CP0 registers total 31*/
+	mfc0	$1, $0
+	mfc0	$2, $1
+	mfc0	$3, $2
+	mfc0	$4, $3
+	mfc0	$5, $4
+	mfc0	$6, $5
+	mfc0	$7, $6
+	mfc0	$8, $8
+	mfc0	$9, $10
+	mfc0	$10,$12
+	mfc0	$11, $12,1
+	mfc0	$12, $13
+	mfc0	$13, $14
+	mfc0	$14, $15
+	mfc0	$15, $15,1
+	mfc0	$16, $16
+	mfc0	$17, $16,1
+	mfc0	$18, $16,2
+	mfc0	$19, $16,3
+	mfc0	$20, $16, 7
+	mfc0	$21, $17
+
+	sw	$1,  128(k0)
+	sw	$2,  132(k0)
+	sw	$3,  136(k0)
+	sw	$4,  140(k0)
+	sw	$5,  144(k0)
+	sw	$6,  148(k0)
+	sw	$7,  152(k0)
+	sw	$8,  156(k0)
+	sw	$9,  160(k0)
+	sw	$10, 164(k0)
+	sw	$11, 168(k0)
+	sw	$12, 172(k0)
+	sw	$13, 176(k0)
+	sw	$14, 180(k0)
+	sw	$15, 184(k0)
+	sw	$16, 188(k0)
+	sw	$17, 192(k0)
+	sw	$18, 196(k0)
+	sw	$19, 200(k0)
+	sw	$20, 204(k0)
+	sw	$21, 208(k0)
+
+	mfc0	$1, $18
+	mfc0	$2, $19
+	mfc0	$3, $23
+	mfc0	$4, $24
+	mfc0	$5, $26
+	mfc0	$6, $28
+	mfc0	$7, $28,1
+	mfc0	$8, $30
+	mfc0	$9, $31
+	mfc0	$10,$5,4      /*save big page mode register*/
+
+	sw	$1,  212(k0)
+	sw	$2,  216(k0)
+	sw	$3,  220(k0)
+	sw	$4,  224(k0)
+	sw	$5,  228(k0)
+	sw	$6,  232(k0)
+	sw	$7,  236(k0)
+	sw	$8,  240(k0)
+	sw	$9,  244(k0)
+	sw	$10, 248(k0)
+
+	/* preserve virtual address of stack */
+	la	k0, sleep_save_sp
+	sw	sp, 0(k0)
+
+	/* flush caches and write buffers */
+	jal	jz_flush_cache_all
+	nop
+
+	la	k0, 0xB3020050
+	li	k1, 0xff00ff00
+	nop
+	sw	k1, 0(k0)
+	nop
+
+	/* la	k0, 0xB3020054 */
+	/* li	k1, 0xff000000 */
+	/* nop */
+	/* sw	k1, 0(k0) */
+	/*nop *
+
+	/* enter sleep mode */
+	.set mips3
+	sync
+	wait
+	nop
+	nop
+	nop
+	nop
+	.set mips0
+	nop
+9:	j 9b
+	nop
+	nop
+
+/*
+ * jz_cpu_resume()
+ *
+ * entry point from bootloader into kernel during resume
+ */
+
+	.align 5
+	.globl	jz_cpu_resume
+jz_cpu_resume:
+
+	/* Init caches */
+	.set	mips32
+	mtc0	zero, CP0_TAGLO
+
+	li	t0, K0BASE
+	ori	t1, t0, CFG_DCACHE_SIZE
+1:
+	cache	Index_Store_Tag_D, 0(t0)
+	bne	t0, t1, 1b
+	addiu	t0, t0, CFG_CACHELINE_SIZE
+
+	li	t0, K0BASE
+	ori	t1, t0, CFG_ICACHE_SIZE
+2:
+	cache	Index_Store_Tag_I, 0(t0)
+	bne	t0, t1, 2b
+	addiu	t0, t0, CFG_CACHELINE_SIZE
+
+	/* Invalidate BTB */
+	mfc0	t0, CP0_CONFIG, 7
+	nop
+	ori	t0, 2
+	mtc0	t0, CP0_CONFIG, 7
+	nop
+
+
+	/* restore saved sp */
+	la	t0, sleep_save_sp
+	lw	sp, 0(t0)
+
+	/* restore CP0 registers(total 26) */
+	la	k0,	reg_save
+
+	lw	$1,  128(k0)
+	lw	$2,  132(k0)
+	lw	$3,  136(k0)
+	lw	$4,  140(k0)
+	lw	$5,  144(k0)
+	lw	$6,  148(k0)
+	lw	$7,  152(k0)
+	lw	$8,  156(k0)
+	lw	$9,  160(k0)
+	lw	$10, 164(k0)
+	lw	$11, 168(k0)
+	lw	$12, 172(k0)
+	lw	$13, 176(k0)
+	lw	$14, 180(k0)
+	lw	$15, 184(k0)
+	lw	$16, 188(k0)
+	lw	$17, 192(k0)
+	lw	$18, 196(k0)
+	lw	$19, 200(k0)
+	lw	$20, 204(k0)
+	lw	$21, 208(k0)
+
+	mtc0	$1, $0
+	mtc0	$2, $1
+	mtc0	$3, $2
+	mtc0	$4, $3
+	mtc0	$5, $4
+	mtc0	$6, $5
+	mtc0	$7, $6
+	mtc0	$8, $8
+	mtc0	$9, $10
+	mtc0	$10,$12
+	mtc0	$11, $12,1
+	mtc0	$12, $13
+	mtc0	$13, $14
+	mtc0	$14, $15
+	mtc0	$15, $15,1
+	mtc0	$16, $16
+	mtc0	$17, $16,1
+	mtc0	$18, $16,2
+	mtc0	$19, $16,3
+	mtc0	$20, $16,7
+	mtc0	$21, $17
+
+
+	lw	$1,  212(k0)
+	lw	$2,  216(k0)
+	lw	$3,  220(k0)
+	lw	$4,  224(k0)
+	lw	$5,  228(k0)
+	lw	$6,  232(k0)
+	lw	$7,  236(k0)
+	lw	$8,  240(k0)
+	lw	$9,  244(k0)
+	lw	$10, 248(k0)
+
+	mtc0	$1, $18
+	mtc0	$2, $19
+	mtc0	$3, $23
+	mtc0	$4, $24
+	mtc0	$5, $26
+	mtc0	$6, $28
+	mtc0	$7, $28,1
+	mtc0	$8, $30
+	mtc0	$9, $31
+	mtc0	$10,$5,4  /*restore big page register*/
+
+	/*Restore cpu registers*/
+	lw	k1,	120(k0)		/* hi */
+	lw	$0,	0(k0)
+	lw	$1,  	4(k0)
+	mthi	k1
+	lw	k1,	124(k0)		/* lo */
+	lw	$2,	8(k0)
+	lw	$3,  	12(k0)
+	mtlo	k1
+	lw	$4,  	16(k0)
+	lw	$5,  	20(k0)
+	lw	$6,  	24(k0)
+	lw	$7,  	28(k0)
+	lw	$8,  	32(k0)
+	lw	$9,  	36(k0)
+	lw	$10, 	40(k0)
+	lw	$11, 	44(k0)
+	lw	$12, 	48(k0)
+	lw	$13, 	52(k0)
+	lw	$14, 	56(k0)
+	lw	$15, 	60(k0)
+	lw	$16, 	64(k0)
+	lw	$17, 	68(k0)
+	lw	$18, 	72(k0)
+	lw	$19, 	76(k0)
+	lw	$20, 	80(k0)
+	lw	$21, 	84(k0)
+	lw	$22, 	88(k0)
+	lw	$23, 	92(k0)
+	lw	$24, 	96(k0)
+	lw	$25, 	100(k0)
+	lw	$28, 	104(k0)
+	lw	$29, 	108(k0)		/* restore sp */
+	lw	$30, 	112(k0)
+	lw	$31, 	116(k0)		/* restore ra */
+
+	/* return to caller */
+	jr	ra
+	nop
+	nop
+	nop
+
+sleep_save_sp:
+	.word	0			/* preserve sp here */
+
+	.set	reorder
diff --git a/arch/mips/jz4760b/time.c b/arch/mips/jz4760b/time.c
new file mode 100644
index 00000000000..4f633fc6d8c
--- /dev/null
+++ b/arch/mips/jz4760b/time.c
@@ -0,0 +1,241 @@
+/*
+ * linux/arch/mips/jz4760/time.c
+ *
+ * Setting up the clock on the JZ4760 boards.
+ *
+ * Copyright (C) 2008 Ingenic Semiconductor Inc.
+ * Author: <jlwei@ingenic.cn>
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ */
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/time.h>
+#include <linux/clockchips.h>
+
+#include <asm/time.h>
+#include <asm/jzsoc.h>
+
+/* This is for machines which generate the exact clock. */
+
+
+#define JZ_TIMER_TCU_CH  5
+#define JZ_TIMER_IRQ  IRQ_TCU1
+
+#define JZ_TIMER_CLOCK (JZ_EXTAL>>4) /* Jz timer clock frequency */
+
+static struct clocksource clocksource_jz; /* Jz clock source */
+static struct clock_event_device jz_clockevent_device; /* Jz clock event */
+
+void (*jz_timer_callback)(void);
+
+static irqreturn_t jz_timer_interrupt(int irq, void *dev_id)
+{
+	struct clock_event_device *cd = dev_id;
+
+	__tcu_clear_full_match_flag(JZ_TIMER_TCU_CH);
+
+	if (jz_timer_callback)
+		jz_timer_callback();
+
+	cd->event_handler(cd);
+
+	return IRQ_HANDLED;
+}
+
+static struct irqaction jz_irqaction = {
+	.handler	= jz_timer_interrupt,
+	.flags		= IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER,
+	.name		= "jz-timerirq",
+};
+
+union clycle_type
+{
+	cycle_t cycle64;
+	unsigned int cycle32[2];
+};
+
+#if defined(CONFIG_SOC_JZ4760B)
+cycle_t jz_get_cycles(void)
+{
+	/* convert jiffes to jz timer cycles */
+	unsigned long cpuflags;
+	union clycle_type old_cycle;
+
+	local_irq_save(cpuflags);
+	old_cycle.cycle32[0] = REG_OST_OSTCNTL;
+	old_cycle.cycle32[1] = REG_OST_OSTCNTH_BUF;
+	local_irq_restore(cpuflags);
+
+	return (old_cycle.cycle64);
+}
+#else
+static unsigned int current_cycle_high = 0;
+cycle_t jz_get_cycles(void)
+{
+	/* convert jiffes to jz timer cycles */
+	unsigned int ostcount;
+        unsigned long cpuflags;
+        unsigned int current_cycle;
+        unsigned int flag;
+        union clycle_type old_cycle;
+
+        local_irq_save(cpuflags);
+        current_cycle = current_cycle_high;
+        ostcount = REG_OST_OSTCNT;
+        flag = (REG_TCU_TFR & TFCR_OSTFLAG) ? 1: 0;
+        if(flag)
+                ostcount = REG_OST_OSTCNT;
+        local_irq_restore(cpuflags);
+
+        old_cycle.cycle32[0] = ostcount;
+        old_cycle.cycle32[1] = current_cycle + flag;
+
+        return (old_cycle.cycle64);
+}
+
+static irqreturn_t jzclock_handler(int irq, void *dev_id)
+{
+	REG_TCU_TFCR = TFCR_OSTFLAG; /* ACK timer */
+	//	current_cycle_high++;
+
+	return IRQ_HANDLED;
+}
+
+static struct irqaction jz_clockaction = {
+	.handler	= jzclock_handler,
+	.flags		= IRQF_DISABLED  | IRQF_TIMER,
+	.name		= "jz-clockcycle",
+};
+#endif	/* !CONFIG_SOC_JZ4760B */
+
+static struct clocksource clocksource_jz = {
+	.name 		= "jz_clocksource",
+	.rating		= 300,
+	.read		= jz_get_cycles,
+	.mask		= 0xFFFFFFFF,
+	.shift 		= 10,
+	.flags		= CLOCK_SOURCE_WATCHDOG,
+};
+
+static int __init jz_clocksource_init(void)
+{
+	unsigned int latch;
+
+	/* Init timer */
+	latch = (JZ_TIMER_CLOCK + (HZ>>1)) / HZ;
+
+	clocksource_jz.mult = clocksource_hz2mult(JZ_TIMER_CLOCK, clocksource_jz.shift);
+	clocksource_register(&clocksource_jz);
+
+	//---------------------init sys clock -----------------
+	REG_OST_OSTCSR = OSTCSR_PRESCALE16 | OSTCSR_EXT_EN;
+	REG_OST_OSTDR = 0xffffffff;
+#if defined(CONFIG_SOC_JZ4760B)
+	REG_OST_OSTCNTL = 0;
+	REG_OST_OSTCNTH = 0;
+#else
+	REG_OST_OSTCNT = 0;
+	jz_clockaction.dev_id = &clocksource_jz;
+
+	setup_irq(IRQ_TCU0, &jz_clockaction);
+#endif
+
+
+	REG_TCU_TMCR = TMCR_OSTMASK; /* unmask match irq */
+	REG_TCU_TSCR = TSCR_OST;  /* enable timer clock */
+	REG_TCU_TESR = TESR_OST;  /* start counting up */
+
+	//---------------------endif init sys clock -----------------
+
+	return 0;
+}
+
+static int jz_set_next_event(unsigned long evt,
+				  struct clock_event_device *unused)
+{
+	return 0;
+}
+
+static void jz_set_mode(enum clock_event_mode mode,
+			struct clock_event_device *evt)
+{
+	switch (mode) {
+	case CLOCK_EVT_MODE_PERIODIC:
+                break;
+        case CLOCK_EVT_MODE_ONESHOT:
+        case CLOCK_EVT_MODE_UNUSED:
+        case CLOCK_EVT_MODE_SHUTDOWN:
+                break;
+        case CLOCK_EVT_MODE_RESUME:
+                break;
+        }
+}
+
+static struct clock_event_device jz_clockevent_device = {
+	.name		= "jz-clockenvent",
+	.features	= CLOCK_EVT_FEAT_PERIODIC,
+//	.features	= CLOCK_EVT_FEAT_ONESHOT, /* Jz4740 not support dynamic clock now */
+
+	/* .mult, .shift, .max_delta_ns and .min_delta_ns left uninitialized */
+	.mult		= 1,
+	.rating		= 300,
+	.irq		= JZ_TIMER_IRQ,
+	.set_mode	= jz_set_mode,
+	.set_next_event	= jz_set_next_event,
+};
+
+static void __init jz_clockevent_init(void)
+{
+	struct clock_event_device *cd = &jz_clockevent_device;
+	unsigned int cpu = smp_processor_id();
+
+	cd->cpumask = cpumask_of(cpu);
+	clockevents_register_device(cd);
+}
+
+static void __init jz_timer_setup(void)
+{
+  	unsigned int latch;
+
+	jz_clocksource_init();	/* init jz clock source */
+	jz_clockevent_init();	/* init jz clock event */
+
+	//---------------------init sys tick -----------------
+	/* Init timer */
+	__tcu_stop_counter(JZ_TIMER_TCU_CH);
+//	__cpm_start_tcu();
+	latch = (JZ_TIMER_CLOCK + (HZ>>1)) / HZ;
+
+	REG_TCU_TMSR = ((1 << JZ_TIMER_TCU_CH) | (1 << (JZ_TIMER_TCU_CH + 16)));
+
+	REG_TCU_TCSR(JZ_TIMER_TCU_CH) = TCSR_PRESCALE16 | TCSR_EXT_EN;
+	REG_TCU_TDFR(JZ_TIMER_TCU_CH) = latch - 1;
+	REG_TCU_TDHR(JZ_TIMER_TCU_CH) = latch + 1;
+	REG_TCU_TCNT(JZ_TIMER_TCU_CH) = 0;
+	/*
+	 * Make irqs happen for the system timer
+	 */
+	jz_irqaction.dev_id = &jz_clockevent_device;
+	setup_irq(JZ_TIMER_IRQ, &jz_irqaction);
+	__tcu_clear_full_match_flag(JZ_TIMER_TCU_CH);
+	__tcu_unmask_full_match_irq(JZ_TIMER_TCU_CH);
+	__tcu_start_counter(JZ_TIMER_TCU_CH);}
+
+
+void __init plat_time_init(void)
+{
+	jz_timer_setup();
+}
diff --git a/arch/mips/jz4770/Makefile b/arch/mips/jz4770/Makefile
new file mode 100644
index 00000000000..cc38cab2d8a
--- /dev/null
+++ b/arch/mips/jz4770/Makefile
@@ -0,0 +1,25 @@
+#
+# Makefile for the Ingenic JZ4770.
+#
+
+# Object file lists.
+
+obj-y += prom.o irq.o time.o reset.o setup.o dma.o \
+	platform.o cpm_fake.o #i2c.o
+
+obj-$(CONFIG_PROC_FS)		+= proc.o
+
+# board specific support
+obj-$(CONFIG_JZ4770_F4770)	+= board-f4770.o
+obj-$(CONFIG_SOC_JZ4770)        += fpu.o
+
+# PM support
+
+obj-$(CONFIG_PM)         += pm.o sleep.o
+
+# CPU Frequency scaling support
+
+obj-$(CONFIG_CPU_FREQ_JZ)       += cpufreq.o
+
+#obj-$(CONFIG_JZ4760_ALTAIR)	+= gpiolib.o
+
diff --git a/arch/mips/jz4770/board-f4770.c b/arch/mips/jz4770/board-f4770.c
new file mode 100644
index 00000000000..b1fe497ac4e
--- /dev/null
+++ b/arch/mips/jz4770/board-f4770.c
@@ -0,0 +1,108 @@
+/*
+ * linux/arch/mips/jz4760/board-f4760.c
+ *
+ * JZ4770 F4770 board setup routines.
+ *
+ * Copyright (c) 2006-2008  Ingenic Semiconductor Inc.
+ * Author: <jlwei@ingenic.cn>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/ioport.h>
+#include <linux/mm.h>
+#include <linux/console.h>
+#include <linux/delay.h>
+#include <linux/i2c.h>
+
+#include <asm/cpu.h>
+#include <asm/bootinfo.h>
+#include <asm/mipsregs.h>
+#include <asm/reboot.h>
+
+#include <asm/jzsoc.h>
+
+
+#define WM831X_LDO_MAX_NAME 6
+
+extern void (*jz_timer_callback)(void);
+
+static void dancing(void)
+{
+	static unsigned char slash[] = "\\|/-";
+//	static volatile unsigned char *p = (unsigned char *)0xb6000058;
+	static volatile unsigned char *p = (unsigned char *)0xb6000016;
+	static unsigned int count = 0;
+	*p = slash[count++];
+	count &= 3;
+}
+
+static void f4770_timer_callback(void)
+{
+	static unsigned long count = 0;
+
+	if ((++count) % 50 == 0) {
+		dancing();
+		count = 0;
+	}
+}
+
+static void __init board_cpm_setup(void)
+{
+	/* Stop unused module clocks here.
+	 * We have started all module clocks at arch/mips/jz4760/setup.c.
+	 */
+}
+
+static void __init board_gpio_setup(void)
+{
+	/*
+	 * Initialize SDRAM pins
+	 */
+}
+
+static struct i2c_board_info falcon_i2c0_devs[] __initdata = {
+        {
+                I2C_BOARD_INFO("cm3511", 0x30),
+        },
+        {
+                I2C_BOARD_INFO("ov3640", 0x3c),
+        },
+        {
+                I2C_BOARD_INFO("ov7690", 0x21),
+        },
+        {
+        },
+};
+
+void __init board_i2c_init(void) {
+        i2c_register_board_info(0, falcon_i2c0_devs, ARRAY_SIZE(falcon_i2c0_devs));
+}
+
+void __init jz_board_setup(void)
+{
+
+	printk("JZ4770 F4770 board setup\n");
+//	jz_restart(NULL);
+	board_cpm_setup();
+	board_gpio_setup();
+
+	jz_timer_callback = f4770_timer_callback;
+}
+
+/**
+ * Called by arch/mips/kernel/proc.c when 'cat /proc/cpuinfo'.
+ * Android requires the 'Hardware:' field in cpuinfo to setup the init.%hardware%.rc.
+ */
+const char *get_board_type(void)
+{
+	return "f4770";
+}
+
+/*****
+ * Wm831x init
+ *****/
diff --git a/arch/mips/jz4770/cpm_fake.c b/arch/mips/jz4770/cpm_fake.c
new file mode 100644
index 00000000000..ac18c1d8ae3
--- /dev/null
+++ b/arch/mips/jz4770/cpm_fake.c
@@ -0,0 +1,127 @@
+/*
+ * linux/arch/mips/jz4760/cpm_fake.c
+ *
+ * jz4760 on-chip modules.
+ *
+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.
+ *
+ * Author: <whxu@ingenic.cn>
+ */
+
+#include <asm/jzsoc.h>
+
+
+#ifndef JZ_EXTAL
+#define JZ_EXTAL        (12 * 1000000)  /* 12MHz */
+#endif
+
+
+/*
+ * Get the external clock
+ */
+static unsigned int get_external_clock(void)
+{
+        return JZ_EXTAL;
+}
+
+/*
+ * Get the PLL clock
+ */
+unsigned int cpm_get_pllout(void)
+{
+        return get_external_clock() * CFG_DIV;
+}
+
+/*
+ * Get the PLL2 clock
+ */
+unsigned int cpm_get_pllout1(void)
+{
+        return get_external_clock();
+}
+
+/*
+ * Start the module clock
+ */
+void cpm_start_clock(clock_gate_module module_name)
+{
+
+}
+
+/*
+ * Stop the module clock
+ */
+void cpm_stop_clock(clock_gate_module module_name)
+{
+
+}
+
+/*
+ * Get the clock, assigned by the clock_name, and the return value unit is Hz
+ */
+unsigned int cpm_get_clock(cgu_clock clock_name)
+{
+        unsigned int clock_hz;
+
+        switch (clock_name) {
+        case CGU_CCLK:
+                clock_hz = cpm_get_pllout();
+
+                break;
+
+        case CGU_HCLK:
+                clock_hz = get_external_clock();
+
+                break;
+
+        case CGU_PCLK:
+                clock_hz = get_external_clock() / CFG_DIV;
+
+                break;
+
+        case CGU_MCLK:
+                clock_hz = get_external_clock() / CFG_DIV;
+
+                break;
+
+        case CGU_H2CLK:
+                clock_hz = get_external_clock();
+
+                break;
+
+        case CGU_SCLK:
+        case CGU_MSCCLK:
+        case CGU_SSICLK:
+        case CGU_CIMCLK:
+        case CGU_LPCLK:
+	case CGU_TVECLK:
+        case CGU_I2SCLK:
+        case CGU_PCMCLK:
+        case CGU_OTGCLK:
+        case CGU_UHCCLK:
+        case CGU_GPSCLK:
+        case CGU_GPUCLK:
+        case CGU_UARTCLK:
+        case CGU_SADCCLK:
+        case CGU_TCUCLK:
+                clock_hz = get_external_clock() / CFG_DIV;
+
+                break;
+
+        default:
+                printk("WARNING: can NOT get clock %d!\n", clock_name);
+                clock_hz = get_external_clock();
+                break;
+        }
+
+        return clock_hz;
+}
+
+/*
+ * Set the clock, assigned by the clock_name, and the return value unit is Hz,
+ * which means the actual clock
+ */
+unsigned int cpm_set_clock(cgu_clock clock_name, unsigned int clock_hz)
+{
+        return 0;
+}
diff --git a/arch/mips/jz4770/cpufreq.c b/arch/mips/jz4770/cpufreq.c
new file mode 100644
index 00000000000..7c0c90d21ee
--- /dev/null
+++ b/arch/mips/jz4770/cpufreq.c
@@ -0,0 +1,598 @@
+/*
+ * linux/arch/mips/jz4770/cpufreq.c
+ *
+ * cpufreq driver for JZ4770 
+ *
+ * Copyright (c) 2006-2008  Ingenic Semiconductor Inc.
+ * Author: <lhhuang@ingenic.cn>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+
+#include <linux/cpufreq.h>
+
+#include <asm/jzsoc.h>
+#include <asm/processor.h>
+
+#define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, \
+						"cpufreq-jz4770", msg)
+
+#undef CHANGE_PLL
+
+#define PLL_UNCHANGED 0
+#define PLL_GOES_UP   1
+#define PLL_GOES_DOWN 2
+
+#define PLL_WAIT_500NS (500*(__cpm_get_cclk()/1000000000))
+
+/* Saved the boot-time parameters */
+static struct {
+	/* SDRAM parameters */
+	unsigned int mclk;  /* memory clock, KHz */
+	unsigned int tras;  /* RAS pulse width, cycles of mclk */
+	unsigned int rcd;   /* RAS to CAS Delay, cycles of mclk */
+	unsigned int tpc;   /* RAS Precharge time, cycles of mclk */
+	unsigned int trwl;  /* Write Precharge Time, cycles of mclk */
+	unsigned int trc;   /* RAS Cycle Time, cycles of mclk */
+	unsigned int rtcor; /* Refresh Time Constant */
+	unsigned int sdram_initialized;
+
+	/* LCD parameters */
+	unsigned int lcdpix_clk; /* LCD Pixel clock, Hz */
+	unsigned int lcd_clks_initialized;
+} boot_config;
+
+struct jz4770_freq_percpu_info {
+	struct cpufreq_frequency_table table[7];
+};
+
+static struct jz4770_freq_percpu_info jz4770_freq_table;
+
+/*
+ * This contains the registers value for an operating point.
+ * If only part of a register needs to change then there is
+ * a mask value for that register.
+ * When going to a new operating point the current register
+ * value is ANDed with the ~mask and ORed with the new value.
+ */
+struct dpm_regs {
+	u32 cpccr;        /* Clock Freq Control Register */
+	u32 cpccr_mask;   /* Clock Freq Control Register mask */
+	u32 cppcr;        /* PLL1 Control Register */
+	u32 cppcr_mask;   /* PLL1 Control Register mask */
+	u32 pll_up_flag;  /* New PLL freq is higher than current or not */
+};
+
+extern jz_clocks_t jz_clocks;
+
+static void jz_update_clocks(void)
+{
+	/* Next clocks must be updated if we have changed 
+	 * the PLL or divisors.
+	 */
+	jz_clocks.cclk = __cpm_get_cclk();
+	jz_clocks.hclk = __cpm_get_hclk();
+	jz_clocks.mclk = __cpm_get_mclk();
+	jz_clocks.pclk = __cpm_get_pclk();
+	jz_clocks.pixclk = __cpm_get_pixclk();
+	jz_clocks.i2sclk = __cpm_get_i2sclk();
+	jz_clocks.usbclk = __cpm_get_usbclk();
+	jz_clocks.mscclk = __cpm_get_mscclk(0);
+}
+
+static void
+jz_init_boot_config(void)
+{
+	if (!boot_config.lcd_clks_initialized) {
+		/* the first time to scale pll */
+		boot_config.lcdpix_clk = __cpm_get_pixclk();
+		boot_config.lcd_clks_initialized = 1;
+	}
+
+	if (!boot_config.sdram_initialized) {
+		/* the first time to scale frequencies */
+		unsigned int dmcr, rtcor;
+		unsigned int tras, rcd, tpc, trwl, trc;
+		
+		dmcr = REG_EMC_DMCR;
+		rtcor = REG_EMC_RTCOR;
+
+		tras = (dmcr >> 13) & 0x7;
+		rcd = (dmcr >> 11) & 0x3;
+		tpc = (dmcr >> 8) & 0x7;
+		trwl = (dmcr >> 5) & 0x3;
+		trc = (dmcr >> 2) & 0x7;
+
+		boot_config.mclk = __cpm_get_mclk() / 1000;
+		boot_config.tras = tras + 4;
+		boot_config.rcd = rcd + 1;
+		boot_config.tpc = tpc + 1;
+		boot_config.trwl = trwl + 1;
+		boot_config.trc = trc * 2 + 1;
+		boot_config.rtcor = rtcor;
+
+		boot_config.sdram_initialized = 1;
+	}
+}
+
+static void jz_update_dram_rtcor(unsigned int new_mclk)
+{
+	unsigned int rtcor;
+	
+	new_mclk /= 1000;
+	rtcor = boot_config.rtcor * new_mclk / boot_config.mclk;
+	rtcor--;
+
+	if (rtcor < 1) rtcor = 1;
+	if (rtcor > 255) rtcor = 255;
+
+	REG_EMC_RTCOR = rtcor;
+	REG_EMC_RTCNT = rtcor;
+}
+
+static void jz_update_dram_dmcr(unsigned int new_mclk)
+{
+	unsigned int dmcr;
+	unsigned int tras, rcd, tpc, trwl, trc;
+	unsigned int valid_time, new_time; /* ns */
+
+	new_mclk /= 1000;
+	tras = boot_config.tras * new_mclk / boot_config.mclk;
+	rcd = boot_config.rcd * new_mclk / boot_config.mclk;
+	tpc = boot_config.tpc * new_mclk / boot_config.mclk;
+	trwl = boot_config.trwl * new_mclk / boot_config.mclk;
+	trc = boot_config.trc * new_mclk / boot_config.mclk;
+
+	/* Validation checking */
+	valid_time = (boot_config.tras * 1000000) / boot_config.mclk;
+	new_time = (tras * 1000000) / new_mclk;
+	if (new_time < valid_time) tras += 1;
+
+	valid_time = (boot_config.rcd * 1000000) / boot_config.mclk;
+	new_time = (rcd * 1000000) / new_mclk;
+	if (new_time < valid_time) rcd += 1;
+
+	valid_time = (boot_config.tpc * 1000000) / boot_config.mclk;
+	new_time = (tpc * 1000000) / new_mclk;
+	if (new_time < valid_time) tpc += 1;
+
+	valid_time = (boot_config.trwl * 1000000) / boot_config.mclk;
+	new_time = (trwl * 1000000) / new_mclk;
+	if (new_time < valid_time) trwl += 1;
+
+	valid_time = (boot_config.trc * 1000000) / boot_config.mclk;
+	new_time = (trc * 1000000) / new_mclk;
+	if (new_time < valid_time) trc += 2;
+
+	tras = (tras < 4) ? 4: tras;
+	tras = (tras > 11) ? 11: tras;
+	tras -= 4;
+
+	rcd = (rcd < 1) ? 1: rcd;
+	rcd = (rcd > 4) ? 4: rcd;
+	rcd -= 1;
+
+	tpc = (tpc < 1) ? 1: tpc;
+	tpc = (tpc > 8) ? 8: tpc;
+	tpc -= 1;
+
+	trwl = (trwl < 1) ? 1: trwl;
+	trwl = (trwl > 4) ? 4: trwl;
+	trwl -= 1;
+
+	trc = (trc < 1) ? 1: trc;
+	trc = (trc > 15) ? 15: trc;
+	trc /= 2;	
+
+	dmcr = REG_EMC_DMCR;
+	
+	dmcr &= ~(EMC_DMCR_TRAS_MASK | EMC_DMCR_RCD_MASK | EMC_DMCR_TPC_MASK | EMC_DMCR_TRWL_MASK | EMC_DMCR_TRC_MASK);
+	dmcr |= ((tras << EMC_DMCR_TRAS_BIT) | (rcd << EMC_DMCR_RCD_BIT) | (tpc << EMC_DMCR_TPC_BIT) | (trwl << EMC_DMCR_TRWL_BIT) | (trc << EMC_DMCR_TRC_BIT));
+
+	REG_EMC_DMCR = dmcr;
+}
+
+static void jz_update_dram_prev(unsigned int cur_mclk, unsigned int new_mclk)
+{	
+	/* No risk, no fun: run with interrupts on! */
+	if (new_mclk > cur_mclk) {
+		/* We're going FASTER, so first update TRAS, RCD, TPC, TRWL
+		 * and TRC of DMCR before changing the frequency.
+		 */
+		jz_update_dram_dmcr(new_mclk);
+	} else {
+		/* We're going SLOWER: first update RTCOR value
+		 * before changing the frequency.
+		 */
+		jz_update_dram_rtcor(new_mclk);
+	}
+}
+
+static void jz_update_dram_post(unsigned int cur_mclk, unsigned int new_mclk)
+{	
+	/* No risk, no fun: run with interrupts on! */
+	if (new_mclk > cur_mclk) {
+		/* We're going FASTER, so update RTCOR
+		 * after changing the frequency 
+		 */
+		jz_update_dram_rtcor(new_mclk);
+	} else {
+		/* We're going SLOWER: so update TRAS, RCD, TPC, TRWL
+		 * and TRC of DMCR after changing the frequency.
+		 */
+		jz_update_dram_dmcr(new_mclk);
+	}
+}
+
+static void jz_scale_divisors(struct dpm_regs *regs)
+{
+	unsigned int cpccr;
+	unsigned int cur_mclk, new_mclk;
+	int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
+	unsigned int tmp = 0, wait = PLL_WAIT_500NS; 
+
+	cpccr = REG_CPM_CPCCR;
+	cpccr &= ~((unsigned long)regs->cpccr_mask);
+	cpccr |= regs->cpccr;
+	cpccr |= CPM_CPCCR_CE;       /* update immediately */
+
+	cur_mclk = __cpm_get_mclk();
+	new_mclk = __cpm_get_pllout() / div[(cpccr & CPM_CPCCR_MDIV_MASK) >> CPM_CPCCR_MDIV_BIT];
+
+	/* Update some DRAM parameters before changing frequency */
+	jz_update_dram_prev(cur_mclk, new_mclk);
+
+	/* update register to change the clocks.
+	 * align this code to a cache line.
+	 */
+	__asm__ __volatile__(
+		".set noreorder\n\t"
+		".align 5\n"
+		"sw %1,0(%0)\n\t"
+		"li %3,0\n\t"
+		"1:\n\t"
+		"bne %3,%2,1b\n\t"
+		"addi %3, 1\n\t"
+		"nop\n\t"
+		"nop\n\t"
+		"nop\n\t"
+		"nop\n\t"
+		".set reorder\n\t"
+		:
+		: "r" (CPM_CPCCR), "r" (cpccr), "r" (wait), "r" (tmp));
+
+	/* Update some other DRAM parameters after changing frequency */
+	jz_update_dram_post(cur_mclk, new_mclk);
+}
+
+#ifdef CHANGE_PLL
+/* Maintain the LCD clock and pixel clock */
+static void jz_scale_lcd_divisors(struct dpm_regs *regs)
+{	
+	unsigned int new_pll, new_lcd_div, new_lcdpix_div;
+	unsigned int cpccr;
+	unsigned int tmp = 0, wait = PLL_WAIT_500NS; 
+
+	if (!boot_config.lcd_clks_initialized) return;
+
+	new_pll = __cpm_get_pllout();
+	new_lcd_div = new_pll / boot_config.lcd_clk;
+	new_lcdpix_div = new_pll / boot_config.lcdpix_clk;
+
+	if (new_lcd_div < 1)
+		new_lcd_div = 1;
+	if (new_lcd_div > 16)
+		new_lcd_div = 16;
+
+	if (new_lcdpix_div < 1)
+		new_lcdpix_div = 1;
+	if (new_lcdpix_div > 512)
+		new_lcdpix_div = 512;
+
+//	REG_CPM_CPCCR2 = new_lcdpix_div - 1;
+
+	cpccr = REG_CPM_CPCCR;
+	cpccr &= ~CPM_CPCCR_LDIV_MASK;
+	cpccr |= ((new_lcd_div - 1) << CPM_CPCCR_LDIV_BIT);
+	cpccr |= CPM_CPCCR_CE;       /* update immediately */
+
+	/* update register to change the clocks.
+	 * align this code to a cache line.
+	 */
+	__asm__ __volatile__(
+		".set noreorder\n\t"
+		".align 5\n"
+		"sw %1,0(%0)\n\t"
+		"li %3,0\n\t"
+		"1:\n\t"
+		"bne %3,%2,1b\n\t"
+		"addi %3, 1\n\t"
+		"nop\n\t"
+		"nop\n\t"
+		"nop\n\t"
+		"nop\n\t"
+		".set reorder\n\t"
+		:
+		: "r" (CPM_CPCCR), "r" (cpccr), "r" (wait), "r" (tmp));
+}
+
+static void jz_scale_pll(struct dpm_regs *regs)
+{
+	unsigned int cppcr;
+	unsigned int cur_mclk, new_mclk, new_pll;
+	int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
+	int od[] = {1, 2, 2, 4};
+
+	cppcr = REG_CPM_CPPCR;
+	cppcr &= ~(regs->cppcr_mask | CPM_CPPCR_PLLS | CPM_CPPCR_PLLEN | CPM_CPPCR_PLLST_MASK);
+	regs->cppcr &= ~CPM_CPPCR_PLLEN;
+	cppcr |= (regs->cppcr | 0xff);
+
+	/* Update some DRAM parameters before changing frequency */
+	new_pll = JZ_EXTAL * ((cppcr>>23)+2) / ((((cppcr>>18)&0x1f)+2) * od[(cppcr>>16)&0x03]);
+	cur_mclk = __cpm_get_mclk();
+	new_mclk = new_pll / div[(REG_CPM_CPCCR>>16) & 0xf];
+
+	/*
+	 * Update some SDRAM parameters
+	 */
+	jz_update_dram_prev(cur_mclk, new_mclk);
+
+	/* 
+	 * Update PLL, align code to cache line.
+	 */
+	cppcr |= CPM_CPPCR_PLLEN;
+	__asm__ __volatile__(
+		".set noreorder\n\t"
+		".align 5\n"
+		"sw %1,0(%0)\n\t"
+		"nop\n\t"
+		"nop\n\t"
+		"nop\n\t"
+		"nop\n\t"
+		"nop\n\t"
+		"nop\n\t"
+		"nop\n\t"
+		".set reorder\n\t"
+		:
+		: "r" (CPM_CPPCR), "r" (cppcr));
+
+	/* Update some other DRAM parameters after changing frequency */
+	jz_update_dram_post(cur_mclk, new_mclk);
+}
+#endif
+
+static void jz4770_transition(struct dpm_regs *regs)
+{
+	/*
+	 * Get and save some boot-time conditions.
+	 */
+	jz_init_boot_config();
+
+#ifdef CHANGE_PLL
+	/* 
+	 * Disable LCD before scaling pll.
+	 * LCD and LCD pixel clocks should not be changed even if the PLL 
+	 * output frequency has been changed.
+	 */
+	REG_LCD_CTRL &= ~LCD_CTRL_ENA;
+
+	/*
+	 * Stop module clocks before scaling PLL
+	 */
+	__cpm_stop_eth();
+	__cpm_stop_aic(1);
+	__cpm_stop_aic(2);
+#endif
+
+	/* ... add more as necessary */
+
+	if (regs->pll_up_flag == PLL_GOES_UP) {
+		/* the pll frequency is going up, so change dividors first */
+		jz_scale_divisors(regs);
+#ifdef CHANGE_PLL
+		jz_scale_pll(regs);
+#endif
+	}
+	else if (regs->pll_up_flag == PLL_GOES_DOWN) {
+		/* the pll frequency is going down, so change pll first */
+#ifdef CHANGE_PLL
+		jz_scale_pll(regs);
+#endif
+		jz_scale_divisors(regs);
+	}
+	else {
+		/* the pll frequency is unchanged, so change divisors only */
+		jz_scale_divisors(regs);
+	}
+
+#ifdef CHANGE_PLL
+	/*
+	 * Restart module clocks before scaling PLL
+	 */
+	__cpm_start_eth();
+	__cpm_start_aic(1);
+	__cpm_start_aic(2);
+
+	/* ... add more as necessary */
+
+	/* Scale the LCD divisors after scaling pll */
+	if (regs->pll_up_flag != PLL_UNCHANGED) {
+		jz_scale_lcd_divisors(regs);
+	}
+
+	/* Enable LCD controller */
+	REG_LCD_CTRL &= ~LCD_CTRL_DIS;
+	REG_LCD_CTRL |= LCD_CTRL_ENA;
+#endif
+
+	/* Update system clocks */
+	jz_update_clocks();
+}
+
+extern unsigned int idle_times;
+static unsigned int jz4770_freq_get(unsigned int cpu)
+{
+	return  (__cpm_get_cclk() / 1000);
+}
+
+static unsigned int index_to_divisor(unsigned int index, struct dpm_regs *regs)
+{
+	int n2FR[33] = {
+		0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0,
+		7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0,
+		9
+	};
+	int div[4] = {1, 2, 2, 2}; /* divisors of I:S:P:M */
+	unsigned int div_of_cclk, new_freq, i;
+
+	regs->pll_up_flag = PLL_UNCHANGED;
+	regs->cpccr_mask = CPM_CPCCR_CDIV_MASK | CPM_CPCCR_HDIV_MASK | CPM_CPCCR_PDIV_MASK | CPM_CPCCR_MDIV_MASK;
+
+	new_freq = jz4770_freq_table.table[index].frequency;
+
+	do {
+		div_of_cclk = __cpm_get_pllout() / (1000 * new_freq);
+	} while (div_of_cclk==0);
+
+	if(div_of_cclk == 1 || div_of_cclk == 2 || div_of_cclk == 4) {
+		for(i = 1; i<4; i++) {
+			div[i] = 3;
+		}
+	} else {
+		for(i = 1; i<4; i++) {
+			div[i] = 2;
+		}
+	}
+
+	for(i = 0; i<4; i++) {
+		div[i] *= div_of_cclk;
+	}
+
+	dprintk("divisors of I:S:P:M = %d:%d:%d:%d\n", div[0], div[1], div[2], div[3]);
+
+	regs->cpccr = 
+		(n2FR[div[0]] << CPM_CPCCR_CDIV_BIT) | 
+		(n2FR[div[1]] << CPM_CPCCR_HDIV_BIT) | 
+		(n2FR[div[2]] << CPM_CPCCR_PDIV_BIT) |
+		(n2FR[div[3]] << CPM_CPCCR_MDIV_BIT);
+
+	return  div_of_cclk;
+}
+
+static void jz4770_set_cpu_divider_index(unsigned int cpu, unsigned int index)
+{
+	unsigned long divisor, old_divisor;
+	struct cpufreq_freqs freqs;
+	struct dpm_regs regs;
+
+	old_divisor = __cpm_get_pllout() /  __cpm_get_cclk();
+	divisor = index_to_divisor(index, &regs);
+
+	freqs.old = __cpm_get_cclk() / 1000;
+	freqs.new =  __cpm_get_pllout() / (1000 * divisor);
+	freqs.cpu = cpu;
+
+	cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
+
+	if (old_divisor != divisor)
+		jz4770_transition(&regs);
+
+	cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
+}
+
+static int jz4770_freq_target(struct cpufreq_policy *policy,
+			  unsigned int target_freq,
+			  unsigned int relation)
+{
+	unsigned int new_index = 0;
+
+	if (cpufreq_frequency_table_target(policy,
+					   &jz4770_freq_table.table[0],
+					   target_freq, relation, &new_index))
+		return -EINVAL;
+
+	jz4770_set_cpu_divider_index(policy->cpu, new_index);
+
+	dprintk("new frequency is %d KHz (REG_CPM_CPCCR:0x%x)\n", __cpm_get_cclk() / 1000, REG_CPM_CPCCR);
+
+	return 0;
+}
+
+static int jz4770_freq_verify(struct cpufreq_policy *policy)
+{
+	return cpufreq_frequency_table_verify(policy,
+					      &jz4770_freq_table.table[0]);
+}
+
+static int __init jz4770_cpufreq_driver_init(struct cpufreq_policy *policy)
+{
+
+	struct cpufreq_frequency_table *table =	&jz4770_freq_table.table[0];
+	unsigned int MAX_FREQ;
+
+	dprintk(KERN_INFO "Jz4770 cpufreq driver\n");
+
+	if (policy->cpu != 0)
+		return -EINVAL;
+
+	policy->cur = MAX_FREQ = __cpm_get_cclk() / 1000; /* in kHz. Current and max frequency is determined by u-boot */
+	policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
+
+	policy->cpuinfo.min_freq = MAX_FREQ/8;
+	policy->cpuinfo.max_freq = MAX_FREQ;
+	policy->cpuinfo.transition_latency = 100000; /* in 10^(-9) s = nanoseconds */
+
+	table[0].index = 0;
+	table[0].frequency = MAX_FREQ/8;
+	table[1].index = 1;
+	table[1].frequency = MAX_FREQ/6;
+	table[2].index = 2;
+	table[2].frequency = MAX_FREQ/4;
+	table[3].index = 3;
+	table[3].frequency = MAX_FREQ/3;
+	table[4].index = 4;
+	table[4].frequency = MAX_FREQ/2;
+	table[5].index = 5;
+	table[5].frequency = MAX_FREQ;
+	table[6].index = 6;
+	table[6].frequency = CPUFREQ_TABLE_END;
+
+#ifdef CONFIG_CPU_FREQ_STAT_DETAILS
+	cpufreq_frequency_table_get_attr(table, policy->cpu); /* for showing /sys/devices/system/cpu/cpuX/cpufreq/stats/ */
+#endif
+
+	return  cpufreq_frequency_table_cpuinfo(policy, table);
+}
+
+static struct cpufreq_driver cpufreq_jz4770_driver = {
+//	.flags		= CPUFREQ_STICKY,
+	.init		= jz4770_cpufreq_driver_init,
+	.verify		= jz4770_freq_verify,
+	.target		= jz4770_freq_target,
+	.get		= jz4770_freq_get,
+	.name		= "jz4770",
+};
+
+static int __init jz4770_cpufreq_init(void)
+{
+	return cpufreq_register_driver(&cpufreq_jz4770_driver);
+}
+
+static void __exit jz4770_cpufreq_exit(void)
+{
+	cpufreq_unregister_driver(&cpufreq_jz4770_driver);
+}
+
+module_init(jz4770_cpufreq_init);
+module_exit(jz4770_cpufreq_exit);
+
+MODULE_AUTHOR("Regen <lhhuang@ingenic.cn>");
+MODULE_DESCRIPTION("cpufreq driver for Jz4770");
+MODULE_LICENSE("GPL");
diff --git a/arch/mips/jz4770/dma.c b/arch/mips/jz4770/dma.c
new file mode 100644
index 00000000000..36211df119a
--- /dev/null
+++ b/arch/mips/jz4770/dma.c
@@ -0,0 +1,862 @@
+/*
+ * linux/arch/mips/jz4760/dma.c
+ *
+ * Support functions for the JZ4760 internal DMA channels.
+ * No-descriptor transfer only.
+ * Descriptor transfer should also call jz_request_dma() to get a free
+ * channel and call jz_free_dma() to free the channel. And driver should
+ * build the DMA descriptor and setup the DMA channel by itself.
+ *
+ * Copyright (C) 2006 - 2008 Ingenic Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/sched.h>
+#include <linux/spinlock.h>
+#include <linux/string.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/soundcard.h>
+
+#include <asm/system.h>
+#include <asm/addrspace.h>
+#include <asm/jzsoc.h>
+
+/*
+ * A note on resource allocation:
+ *
+ * All drivers needing DMA channels, should allocate and release them
+ * through the public routines `jz_request_dma()' and `jz_free_dma()'.
+ *
+ * In order to avoid problems, all processes should allocate resources in
+ * the same sequence and release them in the reverse order.
+ *
+ * So, when allocating DMAs and IRQs, first allocate the DMA, then the IRQ.
+ * When releasing them, first release the IRQ, then release the DMA. The
+ * main reason for this order is that, if you are requesting the DMA buffer
+ * done interrupt, you won't know the irq number until the DMA channel is
+ * returned from jz_request_dma().
+ */
+
+struct jz_dma_chan jz_dma_table[MAX_DMA_NUM] = {
+	{ dev_id: DMA_ID_MSC0, },	/* DMAC0 channel 0, reserved for MSC0 */
+	{ dev_id: -1, },		/* DMAC0 channel 1 */
+	{ dev_id: -1, },		/* DMAC0 channel 2 */
+	{ dev_id: -1, },		/* DMAC0 channel 3 */
+	{ dev_id: -1, },		/* DMAC0 channel 4 */
+	{ dev_id: -1, },			/* DMAC0 channel 5 --- unavailable */
+
+	/* To avoid bug, reserved channel 6 & 7 for AIC_TX & AIC_RX */
+	{ dev_id: DMA_ID_AIC_TX, },	/* DMAC1 channel 0 */
+	{ dev_id: DMA_ID_AIC_RX, },	/* DMAC1 channel 1 */
+	{ dev_id: DMA_ID_MSC1, },	/* DMAC1 channel 2, reserved for MSC1 */
+	{ dev_id: -1, },		/* DMAC1 channel 3 */
+	{ dev_id: -1, },		/* DMAC0 channel 4 */
+	{ dev_id: -1, },			/* DMAC0 channel 5 --- unavailable */
+};
+
+// Device FIFO addresses and default DMA modes
+static const struct {
+	unsigned int fifo_addr;
+	unsigned int dma_mode;
+	unsigned int dma_source;
+} dma_dev_table[DMA_ID_MAX] = {
+	[DMA_ID_AUTO] = {0, DMA_AUTOINIT, DMAC_DRSR_RS_AUTO},
+//	{CPHYSADDR(TSSI_FIFO), DMA_32BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_TSSIIN},
+	[DMA_ID_UART3_TX] = {CPHYSADDR(UART3_TDR), DMA_8BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_UART3OUT},
+	[DMA_ID_UART3_RX] = {CPHYSADDR(UART3_RDR), DMA_8BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_UART3IN},
+	[DMA_ID_UART2_TX] = {CPHYSADDR(UART2_TDR), DMA_8BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_UART2OUT},
+	[DMA_ID_UART2_RX] = {CPHYSADDR(UART2_RDR), DMA_8BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_UART2IN},
+	[DMA_ID_UART1_TX] = {CPHYSADDR(UART1_TDR), DMA_8BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_UART1OUT},
+	[DMA_ID_UART1_RX] = {CPHYSADDR(UART1_RDR), DMA_8BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_UART1IN},
+	[DMA_ID_UART0_TX] = {CPHYSADDR(UART0_TDR), DMA_8BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_UART0OUT},
+	[DMA_ID_UART0_RX] = {CPHYSADDR(UART0_RDR), DMA_8BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_UART0IN},
+	[DMA_ID_SSI0_TX] = {CPHYSADDR(SSI_DR(0)), DMA_32BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_SSI0OUT},
+	[DMA_ID_SSI0_RX] = {CPHYSADDR(SSI_DR(0)), DMA_32BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_SSI0IN},
+	[DMA_ID_AIC_TX] = {CPHYSADDR(AIC_DR), DMA_AIC_TX_CMD_UNPACK | DMA_MODE_WRITE, DMAC_DRSR_RS_AICOUT},
+	[DMA_ID_AIC_RX] = {CPHYSADDR(AIC_DR), DMA_32BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_AICIN},
+	[DMA_ID_MSC0] = {0, 0, 0},
+	[DMA_ID_TCU_OVERFLOW] = {0, DMA_AUTOINIT, DMAC_DRSR_RS_TCU},
+	//[DMA_ID_SADC] = {CPHYSADDR(SADC_ADTCH), DMA_32BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_SADC},/* Touch Screen Data Register */
+	[DMA_ID_SADC] = { 0, 0, 0 },
+	[DMA_ID_MSC1] = {0, 0, 0},
+	[DMA_ID_MSC2] = {0, 0, 0},
+	[DMA_ID_SSI1_TX] = {CPHYSADDR(SSI_DR(1)), DMA_32BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_SSI1OUT},
+	[DMA_ID_SSI1_RX] = {CPHYSADDR(SSI_DR(1)), DMA_32BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_SSI1IN},
+	//[DMA_ID_PCM_TX] = {CPHYSADDR(PCM_PDP), DMA_16BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_PMOUT},
+	//[DMA_ID_PCM_RX] = {CPHYSADDR(PCM_PDP), DMA_16BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_PMIN},
+	[DMA_ID_PCM_TX] = { 0, 0, 0 },
+	[DMA_ID_PCM_RX] = { 0, 0, 0},
+	[DMA_ID_I2C0] = { 0, 0, 0 },
+	[DMA_ID_I2C1] = { 0, 0, 0 },
+	[DMA_ID_I2C2] = { 0, 0, 0 },
+	{},
+};
+
+
+int jz_dma_read_proc(char *buf, char **start, off_t fpos,
+			 int length, int *eof, void *data)
+{
+	int i, len = 0;
+	struct jz_dma_chan *chan;
+
+	for (i = 0; i < MAX_DMA_NUM; i++) {
+		if ((chan = get_dma_chan(i)) != NULL) {
+			len += sprintf(buf + len, "%2d: %s\n",
+				       i, chan->dev_str);
+		}
+	}
+
+	if (fpos >= len) {
+		*start = buf;
+		*eof = 1;
+		return 0;
+	}
+	*start = buf + fpos;
+	if ((len -= fpos) > length)
+		return length;
+	*eof = 1;
+	return len;
+}
+
+
+void dump_jz_dma_channel(unsigned int dmanr)
+{
+	struct jz_dma_chan *chan;
+
+	if (dmanr > MAX_DMA_NUM)
+		return;
+	chan = &jz_dma_table[dmanr];
+
+	printk("DMA%d Registers:\n", dmanr);
+	printk("  DMACR  = 0x%08x\n", REG_DMAC_DMACR(chan->io/HALF_DMA_NUM));
+	printk("  DSAR   = 0x%08x\n", REG_DMAC_DSAR(dmanr));
+	printk("  DTAR   = 0x%08x\n", REG_DMAC_DTAR(dmanr));
+	printk("  DTCR   = 0x%08x\n", REG_DMAC_DTCR(dmanr));
+	printk("  DRSR   = 0x%08x\n", REG_DMAC_DRSR(dmanr));
+	printk("  DCCSR  = 0x%08x\n", REG_DMAC_DCCSR(dmanr));
+	printk("  DCMD  = 0x%08x\n", REG_DMAC_DCMD(dmanr));
+	printk("  DDA  = 0x%08x\n", REG_DMAC_DDA(dmanr));
+	printk("  DMADBR = 0x%08x\n", REG_DMAC_DMADBR(chan->io/HALF_DMA_NUM));
+}
+
+void dump_jz_bdma_channel(unsigned int dmanr)
+{
+	printk("\n----------chan%d----------------\n",dmanr);
+	printk("DSA: %x\n",REG_BDMAC_DSAR(dmanr));
+	printk("DTA: %x\n",REG_BDMAC_DTAR(dmanr));
+	printk("DTC: %x\n",REG_BDMAC_DTCR(dmanr));
+	printk("DRT: %x\n",REG_BDMAC_DRSR(dmanr));
+	printk("DCS: %x\n",REG_BDMAC_DCCSR(dmanr));
+	printk("DCM: %x\n",REG_BDMAC_DCMD(dmanr));
+	printk("DDA: %x\n",REG_BDMAC_DDA(dmanr));
+	printk("DSD: %x\n",REG_BDMAC_DSD(dmanr));
+	printk("DNT: %x\n",REG_BDMAC_DNT(dmanr));
+	printk("DMAC: %x\n",REG_BDMAC_DMACR);
+	printk("DIRQP: %x\n",REG_BDMAC_DMAIPR);
+	printk("DDR: %x\n",REG_BDMAC_DMADBR);
+	printk("DDRS: %x\n",REG_BDMAC_DMADBSR);
+	printk("DCKE: %x\n",REG_BDMAC_DMACKE);
+	printk("-------------------------\n");
+}
+
+
+/**
+ * jz_request_dma - dynamically allcate an idle DMA channel to return
+ * @dev_id: the specified dma device id or DMA_ID_RAW_SET
+ * @dev_str: the specified dma device string name
+ * @irqhandler: the irq handler, or NULL
+ * @irqflags: the irq handler flags
+ * @irq_dev_id: the irq handler device id for shared irq
+ *
+ * Finds a free channel, and binds the requested device to it.
+ * Returns the allocated channel number, or negative on error.
+ * Requests the DMA done IRQ if irqhandler != NULL.
+ *
+*/
+/*int jz_request_dma(int dev_id, const char *dev_str,
+		   void (*irqhandler)(int, void *, struct pt_regs *),
+		   unsigned long irqflags,
+		   void *irq_dev_id)
+*/
+
+int jz_request_dma(int dev_id, const char *dev_str,
+		   irqreturn_t (*irqhandler)(int, void *),
+		   unsigned long irqflags,
+		   void *irq_dev_id)
+{
+	struct jz_dma_chan *chan;
+	int i, ret;
+
+	if (dev_id < 0 || dev_id >= DMA_ID_MAX)
+		return -EINVAL;
+
+	for (i = 0; i < MAX_DMA_NUM; i++) {
+		    if (jz_dma_table[i].dev_id == dev_id)
+			    break;
+	}
+
+	if (i == MAX_DMA_NUM) {
+		for (i = 0; i < MAX_DMA_NUM; i++) {
+			if (jz_dma_table[i].dev_id < 0)
+				break;
+		}
+	}
+	if (i == MAX_DMA_NUM)  /* no free channel */
+		return -ENODEV;
+
+	/* we got a free channel */
+	chan = &jz_dma_table[i];
+
+	if (irqhandler) {
+		chan->irq = IRQ_DMA_0 + i;	// allocate irq number
+		chan->irq_dev = irq_dev_id;
+		if ((ret = request_irq(chan->irq, irqhandler, irqflags,
+				       dev_str, chan->irq_dev))) {
+			chan->irq = -1;
+			chan->irq_dev = NULL;
+			return ret;
+		}
+	} else {
+		chan->irq = -1;
+		chan->irq_dev = NULL;
+	}
+
+	// fill it in
+	chan->io = i;
+	chan->dev_id = dev_id;
+	chan->dev_str = dev_str;
+	chan->fifo_addr = dma_dev_table[dev_id].fifo_addr;
+	chan->mode = dma_dev_table[dev_id].dma_mode;
+	chan->source = dma_dev_table[dev_id].dma_source;
+
+	if (i < HALF_DMA_NUM)
+		REG_DMAC_DMACKE(0) = 1 << i;
+	else
+		REG_DMAC_DMACKE(1) = 1 << (i - HALF_DMA_NUM);
+
+	return i;
+}
+
+void jz_free_dma(unsigned int dmanr)
+{
+	struct jz_dma_chan *chan = get_dma_chan(dmanr);
+
+	if (!chan) {
+		printk("Trying to free DMA%d\n", dmanr);
+		return;
+	}
+
+	disable_dma(dmanr);
+	if (chan->irq)
+		free_irq(chan->irq, chan->irq_dev);
+
+	chan->irq = -1;
+	chan->irq_dev = NULL;
+	chan->dev_id = -1;
+}
+
+void jz_set_dma_dest_width(int dmanr, int nbit)
+{
+	struct jz_dma_chan *chan = get_dma_chan(dmanr);
+
+	if (!chan)
+	       	return;
+
+	chan->mode &= ~DMAC_DCMD_DWDH_MASK;
+	switch (nbit) {
+	case 8:
+		chan->mode |= DMAC_DCMD_DWDH_8;
+		break;
+	case 16:
+		chan->mode |= DMAC_DCMD_DWDH_16;
+		break;
+	case 32:
+		chan->mode |= DMAC_DCMD_DWDH_32;
+		break;
+	}
+}
+
+void jz_set_dma_src_width(int dmanr, int nbit)
+{
+	struct jz_dma_chan *chan = get_dma_chan(dmanr);
+
+	if (!chan)
+	       	return;
+
+	chan->mode &= ~DMAC_DCMD_SWDH_MASK;
+	switch (nbit) {
+	case 8:
+		chan->mode |= DMAC_DCMD_SWDH_8;
+		break;
+	case 16:
+		chan->mode |= DMAC_DCMD_SWDH_16;
+		break;
+	case 32:
+		chan->mode |= DMAC_DCMD_SWDH_32;
+		break;
+	}
+}
+
+void jz_set_dma_block_size(int dmanr, int nbyte)
+{
+	struct jz_dma_chan *chan = get_dma_chan(dmanr);
+
+	if (!chan)
+		return;
+
+	chan->mode &= ~DMAC_DCMD_DS_MASK;
+	switch (nbyte) {
+	case 1:
+		chan->mode |= DMAC_DCMD_DS_8BIT;
+		break;
+	case 2:
+		chan->mode |= DMAC_DCMD_DS_16BIT;
+		break;
+	case 4:
+		chan->mode |= DMAC_DCMD_DS_32BIT;
+		break;
+	case 16:
+		chan->mode |= DMAC_DCMD_DS_16BYTE;
+		break;
+	case 32:
+		chan->mode |= DMAC_DCMD_DS_32BYTE;
+		break;
+	}
+}
+
+unsigned int jz_get_dma_command(int dmanr)
+{
+	struct jz_dma_chan *chan = get_dma_chan(dmanr);
+	return chan->mode;
+}
+
+/**
+ * jz_set_dma_mode - do the raw settings for the specified DMA channel
+ * @dmanr: the specified DMA channel
+ * @mode: dma operate mode, DMA_MODE_READ or DMA_MODE_WRITE
+ * @dma_mode: dma raw mode
+ * @dma_source: dma raw request source
+ * @fifo_addr: dma raw device fifo address
+ *
+ * Ensure call jz_request_dma(DMA_ID_RAW_SET, ...) first, then call
+ * jz_set_dma_mode() rather than set_dma_mode() if you work with
+ * and external request dma device.
+ *
+ * NOTE: Don not dynamically allocate dma channel if one external request
+ *       dma device will occupy this channel.
+*/
+int jz_set_dma_mode(unsigned int dmanr, unsigned int mode,
+		    unsigned int dma_mode, unsigned int dma_source,
+		    unsigned int fifo_addr)
+{
+	int dev_id, i;
+	struct jz_dma_chan *chan;
+
+	if (dmanr > MAX_DMA_NUM)
+		return -ENODEV;
+	for (i = 0; i < MAX_DMA_NUM; i++) {
+		if (jz_dma_table[i].dev_id < 0)
+			break;
+	}
+	if (i == MAX_DMA_NUM)
+		return -ENODEV;
+
+	chan = &jz_dma_table[dmanr];
+	dev_id = chan->dev_id;
+	if (dev_id > 0) {
+		printk(KERN_DEBUG "%s sets the allocated DMA channel %d!\n",
+		       __FUNCTION__, dmanr);
+		return -ENODEV;
+	}
+
+	/* clone it from the dynamically allocated. */
+	if (i != dmanr) {
+		chan->irq = jz_dma_table[i].irq;
+		chan->irq_dev = jz_dma_table[i].irq_dev;
+		chan->dev_str = jz_dma_table[i].dev_str;
+		jz_dma_table[i].irq = 0;
+		jz_dma_table[i].irq_dev = NULL;
+		jz_dma_table[i].dev_id = -1;
+	}
+	chan->dev_id = DMA_ID_RAW_SET;
+	chan->io = dmanr;
+	chan->fifo_addr = fifo_addr;
+	chan->mode = dma_mode;
+	chan->source = dma_source;
+
+	set_dma_mode(dmanr, dma_mode);
+
+	return dmanr;
+}
+
+void enable_dma(unsigned int dmanr)
+{
+	struct jz_dma_chan *chan = get_dma_chan(dmanr);
+
+	if (!chan)
+		return;
+
+	REG_DMAC_DCCSR(dmanr) &= ~(DMAC_DCCSR_HLT | DMAC_DCCSR_TT | DMAC_DCCSR_AR);
+	REG_DMAC_DCCSR(dmanr) |= DMAC_DCCSR_NDES; /* No-descriptor transfer */
+	__dmac_enable_channel(dmanr);
+	if (chan->irq)
+		__dmac_channel_enable_irq(dmanr);
+}
+
+#define DMA_DISABLE_POLL 0x10000
+
+void disable_dma(unsigned int dmanr)
+{
+	int i;
+	struct jz_dma_chan *chan = get_dma_chan(dmanr);
+
+	if (!chan)
+		return;
+
+	if (!__dmac_channel_enabled(dmanr))
+		return;
+
+	for (i = 0; i < DMA_DISABLE_POLL; i++)
+		if (__dmac_channel_transmit_end_detected(dmanr))
+			break;
+#if 0
+	if (i == DMA_DISABLE_POLL)
+		printk(KERN_INFO "disable_dma: poll expired!\n");
+#endif
+
+	__dmac_disable_channel(dmanr);
+	if (chan->irq)
+		__dmac_channel_disable_irq(dmanr);
+}
+
+/* Note: DMA_MODE_MASK is simulated by sw */
+void set_dma_mode(unsigned int dmanr, unsigned int mode)
+{
+	struct jz_dma_chan *chan = get_dma_chan(dmanr);
+
+	if (!chan)
+		return;
+
+	chan->mode |= mode & ~(DMAC_DCMD_SAI | DMAC_DCMD_DAI);
+	mode &= DMA_MODE_MASK;
+	if (mode == DMA_MODE_READ) {
+		chan->mode |= DMAC_DCMD_DAI;
+		chan->mode &= ~DMAC_DCMD_SAI;
+	} else if (mode == DMA_MODE_WRITE) {
+		chan->mode |= DMAC_DCMD_SAI;
+		chan->mode &= ~DMAC_DCMD_DAI;
+	} else {
+		printk(KERN_DEBUG "set_dma_mode() just supports DMA_MODE_READ or DMA_MODE_WRITE!\n");
+	}
+	REG_DMAC_DCMD(chan->io) = chan->mode & ~DMA_MODE_MASK;
+	REG_DMAC_DRSR(chan->io) = chan->source;
+}
+
+void set_dma_addr(unsigned int dmanr, unsigned int phyaddr)
+{
+	unsigned int mode;
+	struct jz_dma_chan *chan = get_dma_chan(dmanr);
+
+	if (!chan)
+		return;
+
+	mode = chan->mode & DMA_MODE_MASK;
+	if (mode == DMA_MODE_READ) {
+		REG_DMAC_DSAR(chan->io) = chan->fifo_addr;
+		REG_DMAC_DTAR(chan->io) = phyaddr;
+	} else if (mode == DMA_MODE_WRITE) {
+		REG_DMAC_DSAR(chan->io) = phyaddr;
+		REG_DMAC_DTAR(chan->io) = chan->fifo_addr;
+	} else
+		printk(KERN_DEBUG "Driver should call set_dma_mode() ahead set_dma_addr()!\n");
+}
+
+void set_dma_count(unsigned int dmanr, unsigned int bytecnt)
+{
+	struct jz_dma_chan *chan = get_dma_chan(dmanr);
+	int dma_ds[] = {4, 1, 2, 16, 32};
+	unsigned int ds;
+
+	if (!chan)
+	       	return;
+
+       	ds = (chan->mode & DMAC_DCMD_DS_MASK) >> DMAC_DCMD_DS_BIT;
+	REG_DMAC_DTCR(chan->io) = bytecnt / dma_ds[ds]; // transfer count
+}
+
+unsigned int get_dma_residue(unsigned int dmanr)
+{
+	unsigned int count, ds;
+	int dma_ds[] = {4, 1, 2, 16, 32};
+	struct jz_dma_chan *chan = get_dma_chan(dmanr);
+	if (!chan)
+		return 0;
+
+	ds = (chan->mode & DMAC_DCMD_DS_MASK) >> DMAC_DCMD_DS_BIT;
+	count = REG_DMAC_DTCR(chan->io);
+	count = count * dma_ds[ds];
+
+	return count;
+}
+
+void jz_set_oss_dma(unsigned int dmanr, unsigned int mode, unsigned int audio_fmt)
+{
+	struct jz_dma_chan *chan = get_dma_chan(dmanr);
+
+	if (!chan)
+		return;
+
+	switch (audio_fmt) {
+	case AFMT_U8:
+		/* burst mode : 32BIT */
+		break;
+	case AFMT_S16_LE:
+		/* burst mode : 16BYTE */
+		if (mode == DMA_MODE_READ) {
+			chan->mode = DMA_AIC_32_16BYTE_RX_CMD | DMA_MODE_READ;
+			chan->mode |= mode & ~(DMAC_DCMD_SAI | DMAC_DCMD_DAI);
+			mode &= DMA_MODE_MASK;
+			chan->mode |= DMAC_DCMD_DAI;
+			chan->mode &= ~DMAC_DCMD_SAI;
+		} else if (mode == DMA_MODE_WRITE) {
+			chan->mode = DMA_AIC_32_16BYTE_TX_CMD | DMA_MODE_WRITE;
+			//chan->mode = DMA_AIC_16BYTE_TX_CMD | DMA_MODE_WRITE;
+			chan->mode |= mode & ~(DMAC_DCMD_SAI | DMAC_DCMD_DAI);
+			mode &= DMA_MODE_MASK;
+			chan->mode |= DMAC_DCMD_SAI;
+			chan->mode &= ~DMAC_DCMD_DAI;
+		} else
+			printk("oss_dma_burst_mode() just supports DMA_MODE_READ or DMA_MODE_WRITE!\n");
+
+		REG_DMAC_DCMD(chan->io) = chan->mode & ~DMA_MODE_MASK;
+		REG_DMAC_DRSR(chan->io) = chan->source;
+		break;
+	}
+}
+
+void jz_set_alsa_dma(unsigned int dmanr, unsigned int mode, unsigned int audio_fmt)
+{
+	struct jz_dma_chan *chan = get_dma_chan(dmanr);
+
+	if (!chan)
+		return;
+
+	switch (audio_fmt) {
+	case 8:
+		/* SNDRV_PCM_FORMAT_S8 burst mode : 32BIT */
+		break;
+	case 16:
+		/* SNDRV_PCM_FORMAT_S16_LE burst mode : 16BYTE */
+		if (mode == DMA_MODE_READ) {
+			chan->mode = DMA_AIC_16BYTE_RX_CMD | DMA_MODE_READ;
+			chan->mode |= mode & ~(DMAC_DCMD_SAI | DMAC_DCMD_DAI);
+			mode &= DMA_MODE_MASK;
+			chan->mode |= DMAC_DCMD_DAI;
+			chan->mode &= ~DMAC_DCMD_SAI;
+		} else if (mode == DMA_MODE_WRITE) {
+			chan->mode = DMA_AIC_16BYTE_TX_CMD | DMA_MODE_WRITE;
+			chan->mode |= mode & ~(DMAC_DCMD_SAI | DMAC_DCMD_DAI);
+			mode &= DMA_MODE_MASK;
+			chan->mode |= DMAC_DCMD_SAI;
+			chan->mode &= ~DMAC_DCMD_DAI;
+		} else
+			printk("alsa_dma_burst_mode() just supports DMA_MODE_READ or DMA_MODE_WRITE!\n");
+
+		REG_DMAC_DCMD(chan->io) = chan->mode & ~DMA_MODE_MASK;
+		REG_DMAC_DRSR(chan->io) = chan->source;
+		break;
+	}
+}
+
+//#define JZ4760_DMAC_TEST_ENABLE
+#undef JZ4760_DMAC_TEST_ENABLE
+
+#ifdef JZ4760_DMAC_TEST_ENABLE
+
+/*
+ * DMA test: external address <--> external address
+ */
+#define TEST_DMA_SIZE  16*1024
+
+static jz_dma_desc *dma_desc;
+
+static int dma_chan;
+static dma_addr_t dma_desc_phys_addr;
+static unsigned int dma_src_addr, dma_src_phys_addr, dma_dst_addr, dma_dst_phys_addr;
+
+static int dma_check_result(void *src, void *dst, int size)
+{
+	unsigned int addr1, addr2, i, err = 0;
+
+	addr1 = (unsigned int)src;
+	addr2 = (unsigned int)dst;
+
+	for (i = 0; i < size; i += 4) {
+		if (*(volatile unsigned int *)addr1 != *(volatile unsigned int *)addr2) {
+			err++;
+			printk("wrong data at 0x%08x: src 0x%08x  dst 0x%08x\n", addr2, *(volatile unsigned int *)addr1, *(volatile unsigned int *)addr2);
+		}
+		addr1 += 4;
+		addr2 += 4;
+	}
+	printk("check DMA result err=%d\n", err);
+	return err;
+}
+
+static irqreturn_t jz4760_dma_irq(int irq, void *dev_id)
+{
+	printk("jz4760_dma_irq %d\n", irq);
+
+
+	if (__dmac_channel_transmit_halt_detected(dma_chan)) {
+		printk("DMA HALT\n");
+		REG_DMAC_DCCSR(dma_chan) &= ~DMAC_DCCSR_EN;  /* disable DMA */
+		__dmac_channel_clear_transmit_halt(dma_chan);
+	}
+
+	if (__dmac_channel_address_error_detected(dma_chan)) {
+		printk("DMA ADDR ERROR\n");
+		REG_DMAC_DCCSR(dma_chan) &= ~DMAC_DCCSR_EN;  /* disable DMA */
+		REG_DMAC_DSAR(dma_chan) = 0; /* clear source address register */
+		REG_DMAC_DTAR(dma_chan) = 0; /* clear target address register */
+		__dmac_channel_clear_address_error(dma_chan);
+	}
+
+	if (__dmac_channel_descriptor_invalid_detected(dma_chan)) {
+		REG_DMAC_DCCSR(dma_chan) &= ~DMAC_DCCSR_EN;  /* disable DMA */
+		printk("DMA DESC INVALID\n");
+		__dmac_channel_clear_descriptor_invalid(dma_chan);
+	}
+
+	if (__dmac_channel_count_terminated_detected(dma_chan)) {
+		printk("DMA CT\n");
+		__dmac_channel_clear_count_terminated(dma_chan);
+	}
+
+	if (__dmac_channel_transmit_end_detected(dma_chan)) {
+		REG_DMAC_DCCSR(dma_chan) &= ~DMAC_DCCSR_EN;  /* disable DMA */
+		printk("DMA TT\n");
+		__dmac_channel_clear_transmit_end(dma_chan);
+		dump_jz_dma_channel(dma_chan);
+		dma_check_result((void *)dma_src_addr, (void *)dma_dst_addr, TEST_DMA_SIZE);
+	}
+
+	return IRQ_HANDLED;
+}
+
+void dma_nodesc_test(void)
+{
+	unsigned int addr, i;
+
+	printk("dma_nodesc_test\n");
+
+	/* Request DMA channel and setup irq handler */
+	dma_chan = jz_request_dma(DMA_ID_AUTO, "auto", jz4760_dma_irq,
+				  IRQF_DISABLED, NULL);
+	if (dma_chan < 0) {
+		printk("Setup irq failed\n");
+		return;
+	}
+
+	printk("Requested DMA channel = %d\n", dma_chan);
+
+	/* Allocate DMA buffers */
+	dma_src_addr = __get_free_pages(GFP_KERNEL, 2); /* 16KB */
+	dma_dst_addr = __get_free_pages(GFP_KERNEL, 2); /* 16KB */
+
+	dma_src_phys_addr = CPHYSADDR(dma_src_addr);
+	dma_dst_phys_addr = CPHYSADDR(dma_dst_addr);
+
+	printk("Buffer addresses: 0x%08x 0x%08x 0x%08x 0x%08x\n",
+	       dma_src_addr, dma_src_phys_addr, dma_dst_addr, dma_dst_phys_addr);
+
+	/* Prepare data for source buffer */
+	addr = (unsigned int)dma_src_addr;
+	for (i = 0; i < TEST_DMA_SIZE; i += 4) {
+		*(volatile unsigned int *)addr = addr;
+		addr += 4;
+	}
+	dma_cache_wback((unsigned long)dma_src_addr, TEST_DMA_SIZE);
+
+	/* Init target buffer */
+	memset((void *)dma_dst_addr, 0, TEST_DMA_SIZE);
+	dma_cache_wback((unsigned long)dma_dst_addr, TEST_DMA_SIZE);
+
+	/* Init DMA module */
+	printk("Starting DMA\n");
+	REG_DMAC_DMACR(dma_chan/HALF_DMA_NUM) = 0;
+	REG_DMAC_DCCSR(dma_chan) = 0;
+	REG_DMAC_DRSR(dma_chan) = DMAC_DRSR_RS_AUTO;
+	REG_DMAC_DSAR(dma_chan) = dma_src_phys_addr;
+	REG_DMAC_DTAR(dma_chan) = dma_dst_phys_addr;
+	REG_DMAC_DTCR(dma_chan) = 512;
+	REG_DMAC_DCMD(dma_chan) = DMAC_DCMD_SAI | DMAC_DCMD_DAI | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 | DMAC_DCMD_DS_32BYTE | DMAC_DCMD_TIE;
+	REG_DMAC_DCCSR(dma_chan) = DMAC_DCCSR_NDES | DMAC_DCCSR_EN;
+	REG_DMAC_DMACR(dma_chan/HALF_DMA_NUM) = DMAC_DMACR_DMAE; /* global DMA enable bit */
+
+	/* wait a long time, ensure transfer end */
+	printk("wait 3s...\n");
+	mdelay(3000);		/* wait 3s */
+
+	REG_DMAC_DCCSR(dma_chan) &= ~DMAC_DCCSR_EN;  /* disable DMA */
+	/* free buffers */
+	printk("free DMA buffers\n");
+	free_pages(dma_src_addr, 2);
+	free_pages(dma_dst_addr, 2);
+
+	if (dma_desc)
+		free_pages((unsigned int)dma_desc, 0);
+
+	/* free dma */
+	jz_free_dma(dma_chan);
+}
+
+void dma_desc_test(void)
+{
+	unsigned int next, addr, i;
+	static jz_dma_desc *desc;
+
+	printk("dma_desc_test\n");
+
+	/* Request DMA channel and setup irq handler */
+	dma_chan = jz_request_dma(DMA_ID_AUTO, "auto", jz4760_dma_irq,
+				  IRQF_DISABLED, NULL);
+	if (dma_chan < 0) {
+		printk("Setup irq failed\n");
+		return;
+	}
+
+	printk("Requested DMA channel = %d\n", dma_chan);
+
+	/* Allocate DMA buffers */
+	dma_src_addr = __get_free_pages(GFP_KERNEL, 2); /* 16KB */
+	dma_dst_addr = __get_free_pages(GFP_KERNEL, 2); /* 16KB */
+
+	dma_src_phys_addr = CPHYSADDR(dma_src_addr);
+	dma_dst_phys_addr = CPHYSADDR(dma_dst_addr);
+
+	printk("Buffer addresses: 0x%08x 0x%08x 0x%08x 0x%08x\n",
+	       dma_src_addr, dma_src_phys_addr, dma_dst_addr, dma_dst_phys_addr);
+
+	/* Prepare data for source buffer */
+	addr = (unsigned int)dma_src_addr;
+	for (i = 0; i < TEST_DMA_SIZE; i += 4) {
+		*(volatile unsigned int *)addr = addr;
+		addr += 4;
+	}
+	dma_cache_wback((unsigned long)dma_src_addr, TEST_DMA_SIZE);
+
+	/* Init target buffer */
+	memset((void *)dma_dst_addr, 0, TEST_DMA_SIZE);
+	dma_cache_wback((unsigned long)dma_dst_addr, TEST_DMA_SIZE);
+
+	/* Allocate DMA descriptors */
+	dma_desc = (jz_dma_desc *)__get_free_pages(GFP_KERNEL, 0);
+	dma_desc_phys_addr = CPHYSADDR((unsigned long)dma_desc);
+
+	printk("DMA descriptor address: 0x%08x  0x%08x\n", (u32)dma_desc, dma_desc_phys_addr);
+
+	/* Setup DMA descriptors */
+	desc = dma_desc;
+	next = (dma_desc_phys_addr + (sizeof(jz_dma_desc))) >> 4;
+
+	desc->dcmd = DMAC_DCMD_SAI | DMAC_DCMD_DAI | DMAC_DCMD_RDIL_IGN | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 | DMAC_DCMD_DS_32BYTE | DMAC_DCMD_DES_V | DMAC_DCMD_DES_VM | DMAC_DCMD_DES_VIE | DMAC_DCMD_TIE | DMAC_DCMD_LINK;
+	desc->dsadr = dma_src_phys_addr;    /* DMA source address */
+	desc->dtadr = dma_dst_phys_addr;    /* DMA target address */
+	desc->ddadr = (next << 24) + 128;    /* size: 128*32 bytes = 4096 bytes */
+
+	desc++;
+	next = (dma_desc_phys_addr + 2*(sizeof(jz_dma_desc))) >> 4;
+
+	desc->dcmd = DMAC_DCMD_SAI | DMAC_DCMD_DAI | DMAC_DCMD_RDIL_IGN | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 | DMAC_DCMD_DS_16BYTE | DMAC_DCMD_DES_V | DMAC_DCMD_DES_VM | DMAC_DCMD_DES_VIE | DMAC_DCMD_TIE | DMAC_DCMD_LINK;
+	desc->dsadr = dma_src_phys_addr + 4096;	/* DMA source address */
+	desc->dtadr = dma_dst_phys_addr + 4096;	/* DMA target address */
+	desc->ddadr = (next << 24) + 256;    /* size: 256*16 bytes = 4096 bytes */
+
+	desc++;
+	next = (dma_desc_phys_addr + 3*(sizeof(jz_dma_desc))) >> 4;
+
+	desc->dcmd = DMAC_DCMD_SAI | DMAC_DCMD_DAI | DMAC_DCMD_RDIL_IGN | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 | DMAC_DCMD_DS_16BYTE | DMAC_DCMD_DES_V | DMAC_DCMD_DES_VM | DMAC_DCMD_DES_VIE | DMAC_DCMD_TIE | DMAC_DCMD_LINK;
+	desc->dsadr = dma_src_phys_addr + 8192;	/* DMA source address */
+	desc->dtadr = dma_dst_phys_addr + 8192;	/* DMA target address */
+	desc->ddadr = (next << 24) + 256;    /* size: 256*16 bytes = 4096 bytes */
+
+	desc++;
+	next = (dma_desc_phys_addr + 4*(sizeof(jz_dma_desc))) >> 4;
+
+	desc->dcmd = DMAC_DCMD_SAI | DMAC_DCMD_DAI | DMAC_DCMD_RDIL_IGN | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 | DMAC_DCMD_DS_32BIT | DMAC_DCMD_DES_V | DMAC_DCMD_DES_VM | DMAC_DCMD_DES_VIE | DMAC_DCMD_TIE;
+	desc->dsadr = dma_src_phys_addr + 12*1024;	/* DMA source address */
+	desc->dtadr = dma_dst_phys_addr + 12*1024;	/* DMA target address */
+	desc->ddadr = (next << 24) + 1024;    /* size: 1024*4 bytes = 4096 bytes */
+
+	dma_cache_wback((unsigned long)dma_desc, 4*(sizeof(jz_dma_desc)));
+
+	/* Setup DMA descriptor address */
+	REG_DMAC_DDA(dma_chan) = dma_desc_phys_addr;
+
+	/* Setup request source */
+	REG_DMAC_DRSR(dma_chan) = DMAC_DRSR_RS_AUTO;
+
+	/* Setup DMA channel control/status register */
+	REG_DMAC_DCCSR(dma_chan) = DMAC_DCCSR_EN;	/* descriptor transfer, clear status, start channel */
+
+	/* Enable DMA */
+	REG_DMAC_DMACR(dma_chan/HALF_DMA_NUM) = DMAC_DMACR_DMAE;
+
+	/* DMA doorbell set -- start DMA now ... */
+	REG_DMAC_DMADBSR(dma_chan/HALF_DMA_NUM) = 1 << dma_chan;
+
+	/* wait a long time, ensure transfer end */
+	printk("wait 3s...\n");
+	mdelay(3000);		/* wait 3s */
+
+	REG_DMAC_DCCSR(dma_chan) &= ~DMAC_DCCSR_EN;  /* disable DMA */
+	/* free buffers */
+	printk("free DMA buffers\n");
+	free_pages(dma_src_addr, 2);
+	free_pages(dma_dst_addr, 2);
+
+	if (dma_desc)
+		free_pages((unsigned int)dma_desc, 0);
+
+	/* free dma */
+	jz_free_dma(dma_chan);
+}
+
+/*
+ * channel 0: read
+ * channel 1: write
+ * read and write are simutanously
+ */
+void dma_two_desc_test(void) {
+
+}
+
+#endif
+
+//EXPORT_SYMBOL_NOVERS(jz_dma_table);
+EXPORT_SYMBOL(jz_dma_table);
+EXPORT_SYMBOL(jz_request_dma);
+EXPORT_SYMBOL(jz_free_dma);
+EXPORT_SYMBOL(jz_set_dma_src_width);
+EXPORT_SYMBOL(jz_set_dma_dest_width);
+EXPORT_SYMBOL(jz_set_dma_block_size);
+EXPORT_SYMBOL(jz_set_dma_mode);
+EXPORT_SYMBOL(set_dma_mode);
+EXPORT_SYMBOL(jz_set_oss_dma);
+EXPORT_SYMBOL(jz_set_alsa_dma);
+EXPORT_SYMBOL(set_dma_addr);
+EXPORT_SYMBOL(set_dma_count);
+EXPORT_SYMBOL(get_dma_residue);
+EXPORT_SYMBOL(enable_dma);
+EXPORT_SYMBOL(disable_dma);
+EXPORT_SYMBOL(dump_jz_dma_channel);
diff --git a/arch/mips/jz4770/fpu.c b/arch/mips/jz4770/fpu.c
new file mode 100644
index 00000000000..53f7b549473
--- /dev/null
+++ b/arch/mips/jz4770/fpu.c
@@ -0,0 +1,143 @@
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/ioport.h>
+#include <linux/mm.h>
+#include <linux/console.h>
+#include <linux/delay.h>
+
+#include <asm/cpu.h>
+#include <asm/bootinfo.h>
+#include <asm/mipsregs.h>
+#include <asm/reboot.h>
+
+#include <asm/asm.h>
+#include <asm/errno.h>
+#include <asm/fpregdef.h>
+#include <asm/mipsregs.h>
+#include <asm/asm-offsets.h>
+#include <asm/regdef.h>
+
+#include <asm/jzsoc.h>
+
+void jz4770_fpu_dump(void)
+{
+	unsigned int fgpr[32];
+	unsigned int fscr, fir, i;
+
+	for (i = 0; i < 32; i ++)
+		fgpr[i] = 0xdeadbeef;
+
+	__asm__ __volatile__(
+		"swc1 $f0, 0(%0)\n\t"
+		"swc1 $f1, 4(%0)\n\t"
+		"swc1 $f2, 8(%0)\n\t"
+		"swc1 $f3, 12(%0)\n\t"
+		"swc1 $f4, 16(%0)\n\t"
+		"swc1 $f4, 20(%0)\n\t"
+		"swc1 $f6, 24(%0)\n\t"
+		"swc1 $f6, 28(%0)\n\t"
+		"swc1 $f8, 32(%0)\n\t"
+		"swc1 $f9, 36(%0)\n\t"
+		"swc1 $f10, 40(%0)\n\t"
+		"swc1 $f11, 44(%0)\n\t"
+		"swc1 $f12, 48(%0)\n\t"
+		"swc1 $f13, 52(%0)\n\t"
+		"swc1 $f14, 56(%0)\n\t"
+		"swc1 $f15, 60(%0)\n\t"
+		"swc1 $f16, 64(%0)\n\t"
+		"swc1 $f17, 68(%0)\n\t"
+		"swc1 $f18, 72(%0)\n\t"
+		"swc1 $f19, 76(%0)\n\t"
+		"swc1 $f20, 80(%0)\n\t"
+		"swc1 $f21, 84(%0)\n\t"
+		"swc1 $f22, 88(%0)\n\t"
+		"swc1 $f23, 92(%0)\n\t"
+		"swc1 $f24, 96(%0)\n\t"
+		"swc1 $f25, 100(%0)\n\t"
+		"swc1 $f26, 104(%0)\n\t"
+		"swc1 $f27, 108(%0)\n\t"
+		"swc1 $f28, 112(%0)\n\t"
+		"swc1 $f29, 116(%0)\n\t"
+		"swc1 $f30, 120(%0)\n\t"
+		"swc1 $f31, 124(%0)\n\t"
+		:
+		:"r"(fgpr)
+	);
+
+	/* Get FPU control and status register */
+	__asm__ __volatile__(
+		"cfc1	%0, $31 \n\t"
+		:"=r"(fscr)
+		:
+	);
+
+	/* Get FPU implementation and revision register */
+	__asm__ __volatile__(
+		"cfc1	%0, $0 \n\t"
+		:"=r"(fir)
+		:
+	);
+
+	printk("Dump of FPU: \n");
+
+	for (i = 0; i < 32; i += 4)
+		printk("%08x %08x %08x %08x \n",
+		       fgpr[i],fgpr[i+1],fgpr[i+2],fgpr[i+3]);
+	printk("FPU control and status register          = %08x \n",fscr);
+	printk("FPU implementation and revision register = %08x \n",fir);
+
+	fscr |= 0x11;
+
+	__asm__ __volatile__(
+		"ctc1	%0, $31 \n\t"
+		:
+		:"r"(fscr)
+	);
+	__asm__ __volatile__(
+		"cfc1	%0, $31 \n\t"
+		:"=r"(fscr)
+		:
+	);
+	printk("FPU control and status register          = %08x \n",fscr);
+}
+
+void jz4770_fpu_init(unsigned int round)
+{
+	unsigned int tmp;
+
+	__asm__ __volatile__(
+		"cfc1	%0, $31 \n\t"
+		:"=r"(tmp)
+		:
+	);
+
+//	printk("original jz4770 FCSR value: %8x\n",tmp);
+
+	tmp = 0x0;
+	/* Jz4770 FPU init */
+	/* disable any exception */
+	tmp |= (0x0 << 7);
+	/* Set ronud mode */
+	tmp &= ~0x3;
+	tmp |= (round & 0x3);
+
+//	printk("plan to set jz4770 FPU FCSR to %08x \n",tmp);
+	__asm__ __volatile__(
+		"ctc1	%0, $28 \n\t"
+		:
+		:"r"(tmp)
+	);
+
+	__asm__ __volatile__(
+		"cfc1	%0, $31 \n\t"
+		:"=r"(tmp)
+		:
+	);
+
+//	printk("jz4770 FCSR value after setting: %8x\n",tmp);
+
+}
+
+EXPORT_SYMBOL(jz4770_fpu_init);
diff --git a/arch/mips/jz4770/gpiolib.c b/arch/mips/jz4770/gpiolib.c
new file mode 100644
index 00000000000..9d3e4c026b3
--- /dev/null
+++ b/arch/mips/jz4770/gpiolib.c
@@ -0,0 +1,205 @@
+
+/* arch/mips/jz4770/gpiolib.c
+ *
+ *	hlguo <hlguo@ingenic.cn>
+ *
+ * jz4770 GPIOlib support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+*/
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+
+#include <asm/irq.h>
+#include <asm/io.h>
+#include <asm/jzsoc.h>
+#include <asm/gpio.h>
+
+//#include <linux/gpio.h>
+
+struct jz4770_gpio_chip {
+	struct gpio_chip	chip;
+	void __iomem		*base;
+};
+
+static inline struct jz4770_gpio_chip *to_jz4770_chip(struct gpio_chip *gpc)
+{
+	return container_of(gpc, struct jz4770_gpio_chip, chip);
+}
+
+static void jz4770_gpiolib_set(struct gpio_chip *chip,
+				unsigned offset, int value)
+{
+       	unsigned long flags;
+	unsigned int n = 0;
+
+	n = chip->base +offset;	
+	local_irq_save(flags);
+	__gpio_set_pin(n);	
+	local_irq_restore(flags);	
+}
+
+static int jz4770_gpiolib_get(struct gpio_chip *chip, unsigned offset)
+{
+       	unsigned long flags;
+	unsigned int n = 0;
+	int state = -1;
+
+	n = chip->base +offset;
+	local_irq_save(flags);
+	state = __gpio_get_pin(n);
+	local_irq_restore(flags);
+	return state;
+	
+}
+
+static int jz4770_gpiolib_input(struct gpio_chip *chip, unsigned offset)
+{
+       	unsigned long flags;
+	unsigned int n = 0;
+
+	n = chip->base +offset;	
+	local_irq_save(flags);
+	__gpio_as_input(n);	
+	local_irq_restore(flags);
+	return 0;
+}
+
+static int jz4770_gpiolib_output(struct gpio_chip *chip,
+					unsigned offset, int value)
+{
+	unsigned long flags;
+	unsigned int n = 0;
+
+	n = chip->base +offset;	
+	local_irq_save(flags);
+	__gpio_as_output(n);
+	if( value )
+		__gpio_set_pin(n);
+	else
+		__gpio_clear_pin(n);
+	local_irq_restore(flags);
+	return 0;
+}
+
+static int jz4770_gpio_request(struct gpio_chip *chip, const char *label)
+{
+	return 0;
+}
+
+static void jz4770_gpio_free(struct gpio_chip *chip, unsigned offset)
+{
+	return;
+}
+
+static struct jz4770_gpio_chip jz4770_gpios[] = {
+	[0] = {
+		.base	= (unsigned *)GPIO_BASEA,
+		.chip	= {
+			.base			= 0*32,
+			.owner			= THIS_MODULE,
+			.label			= "GPIOA",
+			.ngpio			= 32,
+			.direction_input	= jz4770_gpiolib_input,
+			.direction_output	= jz4770_gpiolib_output,
+			.set			= jz4770_gpiolib_set,
+			.get			= jz4770_gpiolib_get,
+			.request		= jz4770_gpio_request,
+			.free			= jz4770_gpio_free,
+		},
+	},
+	[1] = {
+		.base	= (unsigned *)GPIO_BASEB,
+		.chip	= {
+			.base			= 1*32,
+			.owner			= THIS_MODULE,
+			.label			= "GPIOB",
+		       	.ngpio			= 32,
+			.direction_input	= jz4770_gpiolib_input,
+			.direction_output	= jz4770_gpiolib_output,
+			.set			= jz4770_gpiolib_set,
+			.get			= jz4770_gpiolib_get,
+			.request		= jz4770_gpio_request,
+			.free			= jz4770_gpio_free,
+		},
+	},
+	[2] = {
+		.base	= (unsigned *)GPIO_BASEC,
+		.chip	= {
+			.base			= 2*32,
+			.owner			= THIS_MODULE,
+			.label			= "GPIOC",
+		       	.ngpio			= 32,
+			.direction_input	= jz4770_gpiolib_input,
+			.direction_output	= jz4770_gpiolib_output,
+			.set			= jz4770_gpiolib_set,
+			.get			= jz4770_gpiolib_get,
+			.request		= jz4770_gpio_request,
+			.free			= jz4770_gpio_free,
+		},
+	},
+	[3] = {
+		.base	= (unsigned *)GPIO_BASED,
+		.chip	= {
+			.base			= 3*32,
+			.owner			= THIS_MODULE,
+			.label			= "GPIOD",
+		       	.ngpio			= 32,
+			.direction_input	= jz4770_gpiolib_input,
+			.direction_output	= jz4770_gpiolib_output,
+			.set			= jz4770_gpiolib_set,
+			.get			= jz4770_gpiolib_get,
+			.request		= jz4770_gpio_request,
+			.free			= jz4770_gpio_free,
+		},
+	},
+	[4] = {
+		.base	= (unsigned *)GPIO_BASEE,
+		.chip	= {
+			.base			= 4*32,
+			.label			= "GPIOE",
+			.owner			= THIS_MODULE,
+		       	.ngpio			= 32,
+			.direction_input	= jz4770_gpiolib_input,
+			.direction_output	= jz4770_gpiolib_output,
+			.set			= jz4770_gpiolib_set,
+			.get			= jz4770_gpiolib_get,
+			.request		= jz4770_gpio_request,
+			.free			= jz4770_gpio_free,
+		},
+	},
+	[5] = {
+		.base	= (unsigned *)GPIO_BASEF,
+		.chip	= {
+			.base			= 5*32,
+			.owner			= THIS_MODULE,
+			.label			= "GPIOF",
+		       	.ngpio			= 32,
+			.direction_input	= jz4770_gpiolib_input,
+			.direction_output	= jz4770_gpiolib_output,
+			.set			= jz4770_gpiolib_set,
+			.get			= jz4770_gpiolib_get,
+			.request		= jz4770_gpio_request,
+			.free			= jz4770_gpio_free,
+		},
+	},
+};
+
+static __init int jz4770_gpiolib_init(void)
+{
+	struct jz4770_gpio_chip *chip = jz4770_gpios;
+	int gpn;
+
+	for (gpn = 0; gpn < ARRAY_SIZE(jz4770_gpios); gpn++, chip++)
+		gpiochip_add(&chip->chip);
+
+	return 0;
+}
+
+arch_initcall(jz4770_gpiolib_init);
diff --git a/arch/mips/jz4770/i2c.c b/arch/mips/jz4770/i2c.c
new file mode 100644
index 00000000000..946265d4785
--- /dev/null
+++ b/arch/mips/jz4770/i2c.c
@@ -0,0 +1,255 @@
+/*
+ * linux/arch/mips/jz4770/i2c.c
+ * 
+ * Jz4770 I2C routines.
+ * 
+ * Copyright (C) 2005,2006 Ingenic Semiconductor Inc.
+ * Author: <cwjia@ingenic.cn>
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ */
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/delay.h>
+#include <asm/uaccess.h>
+#include <asm/addrspace.h>
+
+#include <asm/jzsoc.h>
+
+/* I2C protocol */
+#define I2C_READ	1
+#define I2C_WRITE	0
+
+#define TIMEOUT         1000
+
+/*
+ * I2C_SCK, I2C_SDA
+ */
+#define __gpio_as_i2c()				\
+do {						\
+	REG_GPIO_PXFUNS(2) = 0x00000c00;	\
+	REG_GPIO_PXTRGC(2) = 0x00000c00;	\
+	REG_GPIO_PXSELS(2)  = 0x00000c00;	\
+} while (0)
+
+/*
+ * I2C interface
+ */
+
+static int i2c_disable()
+{
+	int timeout = 0xfffff, i = 100;
+	
+	REG_I2C_ENB = 0; /*disable i2c*/
+	while((REG_I2C_ENSTA & 0x1) && (timeout > 0)) {
+		udelay(1);
+		timeout --;
+	}
+	if(timeout)
+		return 0;
+	else
+		return 1;
+}
+void i2c_open()
+{
+	__gpio_as_i2c();
+}
+
+void i2c_close(void)
+{
+}
+
+void i2c_setclk(unsigned int i2cclk)
+{
+
+}
+
+static void i2c_init_as_master(unsigned char address)
+{
+//	__gpio_as_i2c();
+	if(i2c_disable())
+		printk("i2c not disable\n");
+//	REG_I2C_CTRL = 0x43;
+	REG_I2C_CTRL = 0x45;
+	REG_I2C_TAR = address; /* slave id needed write only once */
+	REG_I2C_INTM = 0;
+	REG_I2C_FHCNT =49;
+	REG_I2C_FLCNT =62;
+//	REG_I2C_SHCNT =0xc80; // 6k
+//	REG_I2C_SLCNT =0xeb0; // 6k
+//	REG_I2C_SHCNT =0x640; // 12k
+//	REG_I2C_SLCNT =0x758; // 12k
+//	REG_I2C_SHCNT =0x320; //26k
+//	REG_I2C_SLCNT =0x3ac; //26k
+//	REG_I2C_SHCNT =0x12c; //71k
+//	REG_I2C_SLCNT =0x160; //71k
+//	REG_I2C_SHCNT =0xc8;
+//	REG_I2C_SLCNT =0xe8;
+	REG_I2C_ENB = 1; /*enable i2c*/
+}
+
+
+/* now for fpga test , count == 1 */
+int i2c_read(unsigned char device, unsigned char *buf,
+	       unsigned char address, int count)
+{
+	int cnt = count;
+	volatile int tmp;
+	int timeout = 0xffff;
+
+	i2c_init_as_master(device);
+
+	address = address & 0xff;
+	
+	while((!(REG_I2C_STA & I2C_STA_TFNF)) && --timeout)
+		;	
+	if (!(timeout)) 
+		printk("***timeout*****************\n");
+	
+	REG_I2C_DC = (I2C_WRITE << 8) | address; 
+
+	while(cnt) {
+		timeout = 0xffff;
+		while((!(REG_I2C_STA & I2C_STA_TFNF)) && --timeout)
+			;	
+		if (!(timeout)) 
+			printk("***timeout*****************\n");
+		
+		REG_I2C_DC = (I2C_READ << 8); 
+#if 1		
+		while((!(REG_I2C_STA & I2C_STA_RFNE)) && timeout) {
+			timeout--;
+		}
+#endif			
+		if (!(timeout)) 
+			printk("***timeout*****************\n");
+
+		*buf = REG_I2C_DC & 0xff;
+
+		cnt--;
+		buf++;
+	}
+	return count - cnt;
+}
+
+int i2c_write(unsigned char device, unsigned char *buf,
+		unsigned char address, int count)
+{
+	int cnt_in_pg,cnt = count;
+	unsigned char *tmpbuf;
+	unsigned char tmpaddr;
+	int timeout = 0xffff;
+	int rw = 0;
+
+
+	tmpbuf = (unsigned char *)buf;
+	tmpaddr = address;
+rewrite:
+	i2c_init_as_master(device);
+
+start_write_page:
+	cnt_in_pg = 0;
+	while((!(REG_I2C_STA & I2C_STA_TFNF)) && --timeout)
+		;	
+	if (!(timeout)) 
+		printk("00***timeout*****************\n");
+
+		REG_I2C_DC = (I2C_WRITE << 8) | tmpaddr;
+#if 1
+
+		if ((REG_I2C_TXABRT & I2C_TXABRT_ABRT_7B_ADDR_NOACK) || ( REG_I2C_STA & I2C_STA_TFE)) {
+			mdelay(3);
+			int a = REG_I2C_CINTR;
+			goto rewrite;
+		}
+#endif
+	while(cnt) {
+
+		timeout = 0xfffff;
+#if 1
+		if ((REG_I2C_TXABRT & I2C_TXABRT_ABRT_7B_ADDR_NOACK) || ( REG_I2C_STA & I2C_STA_TFE)) {
+			mdelay(3);
+			rw = 1;
+			tmpbuf = (unsigned char *)buf;
+			cnt = 16;  
+			int a = REG_I2C_CINTR;
+			goto rewrite;
+		}
+#endif
+
+		if (++cnt_in_pg > 16) { //8 or 16 
+			mdelay(3);
+			tmpaddr += 16;
+			goto start_write_page;
+		}
+
+
+		while((!(REG_I2C_STA & I2C_STA_TFNF)) && timeout)
+			;		
+
+		if ((REG_I2C_TXABRT & I2C_TXABRT_ABRT_7B_ADDR_NOACK) || ( REG_I2C_STA & I2C_STA_TFE)) {
+			mdelay(3);
+			rw = 1;
+			tmpbuf = (unsigned char *)buf;
+			cnt = 16;  
+			int a = REG_I2C_CINTR;
+			goto rewrite;
+		}
+
+		if(REG_I2C_TXABRT != 0)
+			printk("\n\nREG_I2C_TXABRT==0x%x\n",REG_I2C_TXABRT);
+		
+		REG_I2C_DC = (I2C_WRITE << 8) | *tmpbuf;
+
+		rw = 0;
+		cnt--;
+		tmpbuf++;
+#if 1
+		if ((REG_I2C_TXABRT & I2C_TXABRT_ABRT_7B_ADDR_NOACK) || ( REG_I2C_STA & I2C_STA_TFE)) {
+			mdelay(3);
+			rw = 1;
+			tmpbuf = (unsigned char *)buf;
+			cnt = 16;  
+			int a = REG_I2C_CINTR;
+			goto rewrite;
+		}
+#endif
+	}
+
+	timeout = 0xffff;
+	while(((REG_I2C_STA & I2C_STA_MSTACT)) && --timeout)
+		;
+	if (!(timeout)) 
+		printk("22***timeout*****************\n");
+
+	mdelay(2);
+	udelay(450);
+
+	if (REG_I2C_TXABRT & I2C_TXABRT_ABRT_7B_ADDR_NOACK) {
+		mdelay(3);
+		rw = 1;
+		tmpbuf = (unsigned char *)buf;
+		cnt = 16;  
+		int a = REG_I2C_CINTR;
+		goto rewrite;
+	}
+	return count - cnt;
+}
+
+EXPORT_SYMBOL(i2c_open);
+EXPORT_SYMBOL(i2c_close);
+EXPORT_SYMBOL(i2c_setclk);
+EXPORT_SYMBOL(i2c_read);
+EXPORT_SYMBOL(i2c_write);
diff --git a/arch/mips/jz4770/i2c_intr_debug.c b/arch/mips/jz4770/i2c_intr_debug.c
new file mode 100644
index 00000000000..e24c694371f
--- /dev/null
+++ b/arch/mips/jz4770/i2c_intr_debug.c
@@ -0,0 +1,254 @@
+/*
+ * linux/arch/mips/jz4770/i2c.c
+ * 
+ * Jz4770 I2C routines.
+ * 
+ * Copyright (C) 2005,2006 Ingenic Semiconductor Inc.
+ * Author: <cwjia@ingenic.cn>
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ */
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/delay.h>
+#include <asm/uaccess.h>
+#include <asm/addrspace.h>
+
+#include <asm/jzsoc.h>
+
+/* I2C protocol */
+#define I2C_READ	1
+#define I2C_WRITE	0
+
+#define TIMEOUT         1000
+
+static volatile int w_tfep = 0;
+static volatile int w_rfne = 0;
+static	unsigned char *tmpbuf;
+static	unsigned char tmpaddr;
+static int cnt;
+
+/*
+ * I2C_SCK, I2C_SDA
+ */
+#define __gpio_as_i2c()				\
+do {						\
+	REG_GPIO_PXFUNS(2) = 0x00000c00;	\
+	REG_GPIO_PXTRGC(2) = 0x00000c00;	\
+	REG_GPIO_PXSELS(2)  = 0x00000c00;	\
+} while (0)
+
+/*
+ * I2C interface
+ */
+
+static int i2c_disable()
+{
+	int timeout = 0xfffff, i = 100;
+	
+	REG_I2C_ENB = 0; /*disable i2c*/
+	while((REG_I2C_ENSTA & 0x1) && (timeout > 0)) {
+		udelay(1);
+		timeout --;
+	}
+	if(timeout)
+		return 0;
+	else
+		return 1;
+}
+
+static irqreturn_t jz_i2chander(int irq, void *devid)
+{
+	if (REG_I2C_INTST & I2C_INTST_RXFL) {
+		w_rfne  = 1;
+		REG_I2C_INTM = 0;
+		return IRQ_HANDLED;
+	}
+	REG_I2C_INTM = 0;
+	w_tfep = 1;	
+	return IRQ_HANDLED;
+}
+
+void i2c_open()
+{
+	__gpio_as_i2c();
+	REG_I2C_RXTL = 0;
+	request_irq(IRQ_I2C,jz_i2chander,IRQF_DISABLED,0,0);
+}
+
+void i2c_close(void)
+{
+}
+
+void i2c_setclk(unsigned int i2cclk)
+{
+
+}
+
+static void i2c_init_as_master(unsigned char address)
+{
+	if(i2c_disable())
+		printk("i2c_disable error\n");
+//	REG_I2C_CTRL = 0x43;
+	REG_I2C_CTRL = 0x45;
+	REG_I2C_TAR = address; /* slave id needed write only once */
+	REG_I2C_INTM = 0x10;
+	REG_I2C_FHCNT =49;
+	REG_I2C_FLCNT =62;
+	REG_I2C_RXTL = 0;
+//	REG_I2C_SHCNT =0xc80; // 6k
+//	REG_I2C_SLCNT =0xeb0; // 6k
+//	REG_I2C_SHCNT =0x640; // 12k
+//	REG_I2C_SLCNT =0x758; // 12k
+//	REG_I2C_SHCNT =0x320; //26k
+//	REG_I2C_SLCNT =0x3ac; //26k
+//	REG_I2C_SHCNT =0x12c; //71k
+//	REG_I2C_SLCNT =0x160; //71k
+//	REG_I2C_SHCNT =0xc8;
+//	REG_I2C_SLCNT =0xe8;
+	REG_I2C_ENB = 1; /*enable i2c*/
+}
+
+
+int i2c_read(unsigned char device, unsigned char *buf,
+	       unsigned char address, int count)
+{
+	int cnt = count;
+	volatile int tmp;
+	int timeout = 0xffff;
+
+	i2c_init_as_master(device);
+
+	address = address & 0xff;
+       
+	while(!w_tfep)
+		;
+	w_tfep = 0;
+
+	REG_I2C_DC = (I2C_WRITE << 8) | address; 
+
+	while(cnt) {
+		timeout = 0xffff;
+
+	REG_I2C_INTM = 0x10;
+
+	while(!w_tfep)
+		;
+	w_tfep = 0;		
+	REG_I2C_DC = (I2C_READ << 8); 
+	REG_I2C_INTM = 0x4;
+	while(!w_rfne) 
+		;
+	
+	w_rfne = 0;		
+	
+	*buf = REG_I2C_DC & 0xff;
+	
+	cnt--;
+	buf++;
+	}
+	return count - cnt;
+}
+
+int i2c_write(unsigned char device, unsigned char *buf,
+		unsigned char address, int count)
+{
+	int cnt_in_pg;
+	cnt = count;
+	int timeout = 0xffff;
+
+	tmpbuf = (unsigned char *)buf;
+	tmpaddr = address;
+
+rewrite:
+	i2c_init_as_master(device);
+
+start_write_page:
+	cnt_in_pg = 0;
+
+	while(!w_tfep)
+		;
+	w_tfep = 0;
+	
+	REG_I2C_DC = (I2C_WRITE << 8) | tmpaddr;   
+
+	if ((REG_I2C_TXABRT & I2C_TXABRT_ABRT_7B_ADDR_NOACK) || ( REG_I2C_STA & I2C_STA_TFE)) {
+		mdelay(3);
+		int a = REG_I2C_CINTR;
+		goto rewrite;
+	}
+	REG_I2C_INTM = 0x10;
+	
+	while(cnt) {
+		
+		if (++cnt_in_pg > 16) { //8 or 16 
+			mdelay(3);
+			tmpaddr += 16;
+			goto start_write_page;
+		}
+
+		while(!w_tfep)
+			;
+		if ((REG_I2C_TXABRT & I2C_TXABRT_ABRT_7B_ADDR_NOACK)) {
+			mdelay(3);
+			tmpbuf = (unsigned char *)buf;
+			cnt = 16;  
+			int a = REG_I2C_CINTR;
+			goto rewrite;
+		}
+
+		if(REG_I2C_TXABRT != 0)
+			printk("\n\nREG_I2C_TXABRT==0x%x\n",REG_I2C_TXABRT);
+
+		REG_I2C_DC = (I2C_WRITE << 8) | *tmpbuf;
+		REG_I2C_INTM = 0x10;
+
+		w_tfep = 0;
+		cnt--;
+		tmpbuf++;
+
+		if ((REG_I2C_TXABRT & I2C_TXABRT_ABRT_7B_ADDR_NOACK) || ( REG_I2C_STA & I2C_STA_TFE)) {
+			mdelay(3);
+			tmpbuf = (unsigned char *)buf;
+			cnt = 16;  
+			int a = REG_I2C_CINTR;
+			goto rewrite;
+		}
+	}
+
+	timeout = 0xffff;
+	while(((REG_I2C_STA & I2C_STA_MSTACT)) && --timeout)
+		;
+	if (!(timeout)) 
+		printk("***timeout*****************\n");
+	mdelay(2);
+	udelay(450);
+
+	if (REG_I2C_TXABRT & I2C_TXABRT_ABRT_7B_ADDR_NOACK) {
+		mdelay(3);
+		tmpbuf = (unsigned char *)buf;
+		cnt = 16;  
+		int a = REG_I2C_CINTR;
+		goto rewrite;
+	}
+
+	return count - cnt;
+}
+
+EXPORT_SYMBOL(i2c_open);
+EXPORT_SYMBOL(i2c_close);
+EXPORT_SYMBOL(i2c_setclk);
+EXPORT_SYMBOL(i2c_read);
+EXPORT_SYMBOL(i2c_write);
diff --git a/arch/mips/jz4770/irq.c b/arch/mips/jz4770/irq.c
new file mode 100644
index 00000000000..0e2d4148bd5
--- /dev/null
+++ b/arch/mips/jz4770/irq.c
@@ -0,0 +1,488 @@
+/*
+ * linux/arch/mips/jz4770/irq.c
+ *
+ * JZ4770 interrupt routines.
+ *
+ * Copyright (c) 2006-2007  Ingenic Semiconductor Inc.
+ * Author: <lhhuang@ingenic.cn>
+ *
+ *  This program is free software; you can redistribute	 it and/or modify it
+ *  under  the terms of	 the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the	License, or (at your
+ *  option) any later version.
+ */
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/kernel_stat.h>
+#include <linux/module.h>
+#include <linux/signal.h>
+#include <linux/sched.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/timex.h>
+#include <linux/slab.h>
+#include <linux/random.h>
+#include <linux/delay.h>
+#include <linux/bitops.h>
+
+#include <asm/bootinfo.h>
+#include <asm/io.h>
+#include <asm/mipsregs.h>
+#include <asm/system.h>
+#include <asm/jzsoc.h>
+
+/*
+ * INTC irq type
+ */
+
+static void enable_intc_irq(unsigned int irq)
+{
+	__intc_unmask_irq(irq);
+}
+
+static void disable_intc_irq(unsigned int irq)
+{
+	__intc_mask_irq(irq);
+}
+
+static void mask_and_ack_intc_irq(unsigned int irq)
+{
+	__intc_mask_irq(irq);
+	__intc_ack_irq(irq);
+}
+
+static void end_intc_irq(unsigned int irq)
+{
+	if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) {
+		enable_intc_irq(irq);
+	}
+}
+
+static unsigned int startup_intc_irq(unsigned int irq)
+{
+	enable_intc_irq(irq);
+	return 0;
+}
+
+static void shutdown_intc_irq(unsigned int irq)
+{
+	disable_intc_irq(irq);
+}
+
+static struct irq_chip intc_irq_type = {
+	.typename = "INTC",
+	.startup = startup_intc_irq,
+	.shutdown = shutdown_intc_irq,
+	.unmask = enable_intc_irq,
+	.mask = disable_intc_irq,
+	.ack = mask_and_ack_intc_irq,
+	.end = end_intc_irq,
+};
+
+/*
+ * GPIO irq type
+ */
+
+static void enable_gpio_irq(unsigned int irq)
+{
+	unsigned int intc_irq;
+
+	if (irq < (IRQ_GPIO_0 + 32)) {
+		intc_irq = IRQ_GPIO0;
+	}
+	else if (irq < (IRQ_GPIO_0 + 64)) {
+		intc_irq = IRQ_GPIO1;
+	}
+	else if (irq < (IRQ_GPIO_0 + 96)) {
+		intc_irq = IRQ_GPIO2;
+	}
+	else if (irq < (IRQ_GPIO_0 + 128)) {
+		intc_irq = IRQ_GPIO3;
+	}
+	else if (irq < (IRQ_GPIO_0 + 160)) {
+		intc_irq = IRQ_GPIO4;
+	}
+	else {
+		intc_irq = IRQ_GPIO5;
+	}
+
+	enable_intc_irq(intc_irq);
+	__gpio_unmask_irq(irq - IRQ_GPIO_0);
+}
+
+static void disable_gpio_irq(unsigned int irq)
+{
+	__gpio_mask_irq(irq - IRQ_GPIO_0);
+}
+
+static void mask_and_ack_gpio_irq(unsigned int irq)
+{
+	__gpio_mask_irq(irq - IRQ_GPIO_0);
+	__gpio_ack_irq(irq - IRQ_GPIO_0);
+}
+
+static void end_gpio_irq(unsigned int irq)
+{
+	if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) {
+		enable_gpio_irq(irq);
+	}
+}
+
+static unsigned int startup_gpio_irq(unsigned int irq)
+{
+	enable_gpio_irq(irq);
+	return 0;
+}
+
+static void shutdown_gpio_irq(unsigned int irq)
+{
+	disable_gpio_irq(irq);
+}
+
+static struct irq_chip gpio_irq_type = {
+	.typename = "GPIO",
+	.startup = startup_gpio_irq,
+	.shutdown = shutdown_gpio_irq,
+	.unmask = enable_gpio_irq,
+	.mask = disable_gpio_irq,
+	.ack = mask_and_ack_gpio_irq,
+	.end = end_gpio_irq,
+};
+
+/*
+ * DMA irq type
+ */
+static void enable_dma_irq(unsigned int irq)
+{
+	unsigned int intc_irq;
+
+	if ( irq < (IRQ_DMA_0 + HALF_DMA_NUM) ) 	/* DMAC Group 0 irq */
+		intc_irq = IRQ_DMAC0;
+	else if ( irq < (IRQ_DMA_0 + MAX_DMA_NUM) ) 	/* DMAC Group 1 irq */
+		intc_irq = IRQ_DMAC1;
+	else {
+		printk("%s, unexpected dma irq #%d\n", __FILE__, irq);
+		return;
+	}
+	__intc_unmask_irq(intc_irq);
+	__dmac_channel_enable_irq(irq - IRQ_DMA_0);
+}
+
+static void disable_dma_irq(unsigned int irq)
+{
+	int chan = irq - IRQ_DMA_0;
+	__dmac_disable_channel(chan);
+	__dmac_channel_disable_irq(chan);
+}
+
+static void mask_and_ack_dma_irq(unsigned int irq)
+{
+	unsigned int intc_irq;
+
+	disable_dma_irq(irq);
+
+	if ( irq < (IRQ_DMA_0 + HALF_DMA_NUM) ) 	/* DMAC Group 0 irq */
+		intc_irq = IRQ_DMAC0;
+	else if ( irq < (IRQ_DMA_0 + MAX_DMA_NUM) ) 	/* DMAC Group 1 irq */
+		intc_irq = IRQ_DMAC1;
+	else {
+		printk("%s, unexpected dma irq #%d\n", __FILE__, irq);
+		return ;
+	}
+	__intc_ack_irq(intc_irq);
+	//__dmac_channel_ack_irq(irq-IRQ_DMA_0); /* needed?? add 20080506, Wolfgang */
+	//__dmac_channel_disable_irq(irq - IRQ_DMA_0);
+}
+
+static void end_dma_irq(unsigned int irq)
+{
+	if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) {
+		enable_dma_irq(irq);
+	}
+}
+
+static unsigned int startup_dma_irq(unsigned int irq)
+{
+	enable_dma_irq(irq);
+	return 0;
+}
+
+static void shutdown_dma_irq(unsigned int irq)
+{
+	disable_dma_irq(irq);
+}
+
+static struct irq_chip dma_irq_type = {
+	.typename = "DMA",
+	.startup = startup_dma_irq,
+	.shutdown = shutdown_dma_irq,
+	.unmask = enable_dma_irq,
+	.mask = disable_dma_irq,
+	.ack = mask_and_ack_dma_irq,
+	.end = end_dma_irq,
+};
+
+#if 0
+/*
+ * MDMA irq type
+ */
+
+static void enable_mdma_irq(unsigned int irq)
+{
+	unsigned int intc_irq;
+
+	if (irq < IRQ_MDMA_0 + MAX_MDMA_NUM) 	/* DMAC Group 0 irq */
+		intc_irq = IRQ_MDMA;
+	else {
+		printk("%s, unexpected mdma irq #%d\n", __FILE__, irq);
+		return;
+	}
+	__intc_unmask_irq(intc_irq);
+	__mdmac_channel_enable_irq(irq - IRQ_DMA_0);
+}
+
+static void disable_mdma_irq(unsigned int irq)
+{
+	__mdmac_channel_disable_irq(irq - IRQ_DMA_0);
+}
+
+static void mask_and_ack_mdma_irq(unsigned int irq)
+{
+	unsigned int intc_irq;
+
+	if ( irq < IRQ_MDMA_0 + MAX_MDMA_NUM ) 	/* DMAC Group 0 irq */
+		intc_irq = IRQ_MDMA;
+	else {
+		printk("%s, unexpected mdma irq #%d\n", __FILE__, irq);
+		return ;
+	}
+	__intc_ack_irq(intc_irq);
+	__mdmac_channel_ack_irq(irq-IRQ_MDMA_0); /* needed?? add 20080506, Wolfgang */
+	__mdmac_channel_disable_irq(irq - IRQ_MDMA_0);
+}
+
+static void end_mdma_irq(unsigned int irq)
+{
+	if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) {
+		enable_mdma_irq(irq);
+	}
+}
+
+static unsigned int startup_mdma_irq(unsigned int irq)
+{
+	enable_mdma_irq(irq);
+	return 0;
+}
+
+static void shutdown_mdma_irq(unsigned int irq)
+{
+	disable_mdma_irq(irq);
+}
+
+static struct irq_chip mdma_irq_type = {
+	.typename = "MDMA",
+	.startup = startup_mdma_irq,
+	.shutdown = shutdown_mdma_irq,
+	.unmask = enable_mdma_irq,
+	.mask = disable_mdma_irq,
+	.ack = mask_and_ack_mdma_irq,
+	.end = end_mdma_irq,
+};
+#endif
+
+//----------------------------------------------------------------------
+
+/*
+ * BDMA irq type
+ */
+
+static void enable_bdma_irq(unsigned int irq)
+{
+	unsigned int intc_irq;
+
+	if (irq < IRQ_BDMA_0 + MAX_BDMA_NUM)
+		intc_irq = IRQ_BDMA;
+	else {
+		printk("%s, unexpected bdma irq #%d\n", __FILE__, irq);
+		return;
+	}
+	__intc_unmask_irq(intc_irq);
+	__bdmac_channel_enable_irq(irq - IRQ_DMA_0);
+}
+
+static void disable_bdma_irq(unsigned int irq)
+{
+	__bdmac_channel_disable_irq(irq - IRQ_DMA_0);
+}
+
+static void mask_and_ack_bdma_irq(unsigned int irq)
+{
+	unsigned int intc_irq;
+
+	if ( irq < IRQ_BDMA_0 + MAX_BDMA_NUM ) 	/* DMAC Group 0 irq */
+		intc_irq = IRQ_BDMA;
+	else {
+		printk("%s, unexpected bdma irq #%d\n", __FILE__, irq);
+		return ;
+	}
+	__intc_ack_irq(intc_irq);
+	__bdmac_channel_ack_irq(irq - IRQ_BDMA_0);
+	__bdmac_channel_disable_irq(irq - IRQ_BDMA_0);
+}
+
+static void end_bdma_irq(unsigned int irq)
+{
+	if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) {
+		enable_bdma_irq(irq);
+	}
+}
+
+static unsigned int startup_bdma_irq(unsigned int irq)
+{
+	enable_bdma_irq(irq);
+	return 0;
+}
+
+static void shutdown_bdma_irq(unsigned int irq)
+{
+	disable_bdma_irq(irq);
+}
+
+static struct irq_chip bdma_irq_type = {
+	.typename = "BDMA",
+	.startup = startup_bdma_irq,
+	.shutdown = shutdown_bdma_irq,
+	.unmask = enable_bdma_irq,
+	.mask = disable_bdma_irq,
+	.ack = mask_and_ack_bdma_irq,
+	.end = end_bdma_irq,
+};
+
+//----------------------------------------------------------------------
+
+void __init arch_init_irq(void)
+{
+	int i;
+
+	clear_c0_status(0xff04); /* clear ERL */
+	set_c0_status(0x0400);   /* set IP2 */
+
+	/* Set up INTC irq
+	 */
+	for (i = 0; i < NUM_INTC; i++) {
+		disable_intc_irq(i);
+		set_irq_chip_and_handler(i, &intc_irq_type, handle_level_irq);
+	}
+
+	/* Set up DMAC irq
+	 */
+	for (i = 0; i < NUM_DMA; i++) {
+		disable_dma_irq(IRQ_DMA_0 + i);
+		set_irq_chip_and_handler(IRQ_DMA_0 + i, &dma_irq_type, handle_level_irq);
+	}
+
+#if 0
+	/* Set up MDMAC irq
+	 */
+	for (i = 0; i < NUM_MDMA; i++) {
+		disable_mdma_irq(IRQ_MDMA_0 + i);
+		set_irq_chip_and_handler(IRQ_MDMA_0 + i, &mdma_irq_type, handle_level_irq);
+	}
+#endif
+
+	/* Set up BDMA irq
+	 */
+	for (i = 0; i < MAX_BDMA_NUM; i++) {
+		disable_bdma_irq(IRQ_BDMA_0 + i);
+		set_irq_chip_and_handler(IRQ_BDMA_0 + i, &bdma_irq_type, handle_level_irq);
+	}
+
+	/* Set up GPIO irq
+	 */
+#ifndef JZ_BOOTUP_UART_TXD
+#error "JZ_BOOTUP_UART_TXD is not set, please define it int your board header file!"
+#endif
+#ifndef JZ_BOOTUP_UART_RXD
+#error "JZ_BOOTUP_UART_RXD is not set, please define it int your board header file!"
+#endif
+	for (i = 0; i < NUM_GPIO; i++) {
+		if (unlikely(i == JZ_BOOTUP_UART_TXD))
+			continue;
+		if (unlikely(i == JZ_BOOTUP_UART_RXD))
+			continue;
+		disable_gpio_irq(IRQ_GPIO_0 + i);
+		set_irq_chip_and_handler(IRQ_GPIO_0 + i, &gpio_irq_type, handle_level_irq);
+	}
+}
+
+static int plat_real_irq(int irq)
+{
+	int group = 0;
+
+	if ((irq >= IRQ_GPIO5) && (irq <= IRQ_GPIO0)) {
+		group = IRQ_GPIO0 - irq;
+		irq = __gpio_group_irq(group);
+		if (irq >= 0)
+			irq += IRQ_GPIO_0 + 32 * group;
+	} else {
+		switch (irq) {
+		case IRQ_DMAC0:
+		case IRQ_DMAC1:
+			irq = __dmac_get_irq();
+			if (irq < 0) {
+				printk("REG_DMAC_DMAIPR(0) = 0x%08x\n", REG_DMAC_DMAIPR(0));
+				printk("REG_DMAC_DMAIPR(1) = 0x%08x\n", REG_DMAC_DMAIPR(1));
+				return irq;
+			}
+			irq += IRQ_DMA_0;
+			break;
+#if 0
+		case IRQ_MDMA:
+			irq = __mdmac_get_irq();
+			if (irq < 0)
+				return irq;
+			irq += IRQ_MDMA_0;
+			break;
+#endif
+		case IRQ_BDMA:
+			irq = __bdmac_get_irq();
+			if (irq < 0)
+				return irq;
+
+			irq += IRQ_BDMA_0;
+			break;
+		}
+	}
+
+	return irq;
+}
+
+asmlinkage void plat_irq_dispatch(void)
+{
+	int irq = 0;
+
+	unsigned long intc_ipr0 = 0, intc_ipr1 = 0;
+
+	intc_ipr0 = REG_INTC_IPR(0);
+	intc_ipr1 = REG_INTC_IPR(1);
+
+	if (!(intc_ipr0 || intc_ipr1))	return;
+
+	if (intc_ipr0) {
+		irq = ffs(intc_ipr0) - 1;
+		intc_ipr0 &= ~(1<<irq);
+	} else {
+		irq = ffs(intc_ipr1) - 1;
+		intc_ipr1 &= ~(1<<irq);
+		irq += 32;
+	}
+
+	irq = plat_real_irq(irq);
+	WARN((irq < 0), "irq raised, but no irq pending!\n");
+	if (irq < 0)
+		return;
+
+	do_IRQ(irq);
+}
diff --git a/arch/mips/jz4770/platform.c b/arch/mips/jz4770/platform.c
new file mode 100644
index 00000000000..ba5bfdbd4e7
--- /dev/null
+++ b/arch/mips/jz4770/platform.c
@@ -0,0 +1,430 @@
+/*
+ * Platform device support for Jz4770 SoC.
+ *
+ * Copyright 2007, <yliu@ingenic.cn>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/resource.h>
+
+#ifdef CONFIG_ANDROID_PMEM
+#include <linux/android_pmem.h>
+#endif
+
+#include <asm/jzsoc.h>
+
+#include <linux/usb/musb.h>
+
+extern void __init board_msc_init(void);
+extern void __init board_i2c_init(void);
+
+
+/* OHCI (USB full speed host controller) */
+static struct resource jz_usb_ohci_resources[] = {
+	[0] = {
+		.start		= CPHYSADDR(UHC_BASE), // phys addr for ioremap
+		.end		= CPHYSADDR(UHC_BASE) + 0x10000 - 1,
+		.flags		= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start		= IRQ_UHC,
+		.end		= IRQ_UHC,
+		.flags		= IORESOURCE_IRQ,
+	},
+};
+
+/* The dmamask must be set for OHCI to work */
+static u64 ohci_dmamask = ~(u32)0;
+
+static struct platform_device jz_usb_ohci_device = {
+	.name		= "jz-ohci",
+	.id		= 0,
+	.dev = {
+		.dma_mask		= &ohci_dmamask,
+		.coherent_dma_mask	= 0xffffffff,
+	},
+	.num_resources	= ARRAY_SIZE(jz_usb_ohci_resources),
+	.resource	= jz_usb_ohci_resources,
+};
+
+/*** LCD controller ***/
+static struct resource jz_lcd_resources[] = {
+	[0] = {
+		.start          = CPHYSADDR(LCD_BASE),
+		.end            = CPHYSADDR(LCD_BASE) + 0x10000 - 1,
+		.flags          = IORESOURCE_MEM,
+	},
+	[1] = {
+		.start          = IRQ_LCD,
+		.end            = IRQ_LCD,
+		.flags          = IORESOURCE_IRQ,
+	}
+};
+
+static u64 jz_lcd_dmamask = ~(u32)0;
+
+static struct platform_device jz_lcd_device = {
+	.name           = "jz-lcd",
+	.id             = 0,
+	.dev = {
+		.dma_mask               = &jz_lcd_dmamask,
+		.coherent_dma_mask      = 0xffffffff,
+	},
+	.num_resources  = ARRAY_SIZE(jz_lcd_resources),
+	.resource       = jz_lcd_resources,
+};
+
+/* USB OTG Controller */
+static struct platform_device jz_usb_otg_xceiv_device = {
+	.name	= "nop_usb_xceiv",
+	.id	= 0,
+};
+
+static struct musb_hdrc_config jz_usb_otg_config = {
+	.multipoint	= 1,
+	.dyn_fifo	= 0,
+	.soft_con	= 1,
+	.dma		= 1,
+/* Max EPs scanned. Driver will decide which EP can be used automatically. */
+	.num_eps	= 16,
+};
+
+static struct musb_hdrc_platform_data jz_usb_otg_platform_data = {
+#if defined(CONFIG_USB_MUSB_OTG)
+	.mode           = MUSB_OTG,
+#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
+	.mode           = MUSB_HOST,
+#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
+	.mode           = MUSB_PERIPHERAL,
+#endif
+	.config		= &jz_usb_otg_config,
+};
+
+static struct resource jz_usb_otg_resources[] = {
+	[0] = {
+		.start		= CPHYSADDR(UDC_BASE),
+		.end		= CPHYSADDR(UDC_BASE) + 0x10000 - 1,
+		.flags		= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start		= IRQ_OTG,
+		.end		= IRQ_OTG,
+		.flags		= IORESOURCE_IRQ,
+	},
+};
+
+static u64  usb_otg_dmamask = ~(u32)0;
+
+static struct platform_device jz_usb_otg_device = {
+	.name	= "musb_hdrc",
+	.id	= 0,
+	.dev = {
+		.dma_mask		= &usb_otg_dmamask,
+		.coherent_dma_mask	= 0xffffffff,
+		.platform_data		= &jz_usb_otg_platform_data,
+	},
+	.num_resources	= ARRAY_SIZE(jz_usb_otg_resources),
+	.resource	= jz_usb_otg_resources,
+};
+
+#if 0
+/** MMC/SD controller MSC0**/
+static struct resource jz_msc0_resources[] = {
+	{
+		.start          = CPHYSADDR(MSC0_BASE),
+		.end            = CPHYSADDR(MSC0_BASE) + 0x1000 - 1,
+		.flags          = IORESOURCE_MEM,
+	},
+	{
+		.start          = IRQ_MSC0,
+		.end            = IRQ_MSC0,
+		.flags          = IORESOURCE_IRQ,
+	},
+	{
+		.start          = DMA_ID_MSC0_RX,
+		.end            = DMA_ID_MSC0_TX,
+		.flags          = IORESOURCE_DMA,
+	},
+};
+
+static u64 jz_msc0_dmamask =  ~(u32)0;
+
+static struct platform_device jz_msc0_device = {
+	.name = "jz-msc",
+	.id = 0,
+	.dev = {
+		.dma_mask               = &jz_msc0_dmamask,
+		.coherent_dma_mask      = 0xffffffff,
+	},
+	.num_resources  = ARRAY_SIZE(jz_msc0_resources),
+	.resource       = jz_msc0_resources,
+};
+
+/** MMC/SD controller MSC1**/
+static struct resource jz_msc1_resources[] = {
+	{
+		.start          = CPHYSADDR(MSC1_BASE),
+		.end            = CPHYSADDR(MSC1_BASE) + 0x1000 - 1,
+		.flags          = IORESOURCE_MEM,
+	},
+	{
+		.start          = IRQ_MSC1,
+		.end            = IRQ_MSC1,
+		.flags          = IORESOURCE_IRQ,
+	},
+	{
+		.start          = DMA_ID_MSC1_RX,
+		.end            = DMA_ID_MSC1_TX,
+		.flags          = IORESOURCE_DMA,
+	},
+
+};
+
+static u64 jz_msc1_dmamask =  ~(u32)0;
+
+static struct platform_device jz_msc1_device = {
+	.name = "jz-msc",
+	.id = 1,
+	.dev = {
+		.dma_mask               = &jz_msc1_dmamask,
+		.coherent_dma_mask      = 0xffffffff,
+	},
+	.num_resources  = ARRAY_SIZE(jz_msc1_resources),
+	.resource       = jz_msc1_resources,
+};
+
+static struct platform_device *jz_msc_devices[] __initdata = {
+	&jz_msc0_device,
+	&jz_msc1_device,
+};
+#endif
+
+/*
+int __init jz_add_msc_devices(unsigned int controller, struct jz_mmc_platform_data *plat)
+{
+	struct platform_device	*pdev;
+
+	if (controller < 0 || controller > 1)
+		return -EINVAL;
+
+	pdev = jz_msc_devices[controller];
+
+	pdev->dev.platform_data = plat;
+
+	return platform_device_register(pdev);
+}
+*/
+
+/* + Sound device */
+/*
+#define SND(num, desc) { .name = desc, .id = num }
+static struct snd_endpoint snd_endpoints_list[] = {
+	SND(0, "HANDSET"),
+	SND(1, "SPEAKER"),
+	SND(2, "HEADSET"),
+};
+#undef SND
+*/
+
+/*
+static struct msm_snd_endpoints jz_snd_endpoints = {
+	.endpoints = snd_endpoints_list,
+	.num = ARRAY_SIZE(snd_endpoints_list),
+};
+*/
+
+static struct platform_device jz_snd_device = {
+	.name = "mixer",
+	.id = -1,
+	.dev = {
+		.platform_data = &jz_snd_device,
+	},
+};
+/* - Sound device */
+
+static struct resource jz_i2c0_resources[] = {
+	[0] = {
+		.start          = CPHYSADDR(I2C0_BASE),
+		.end            = CPHYSADDR(I2C0_BASE) + 0x1000 - 1,
+		.flags          = IORESOURCE_MEM,
+	},
+	[1] = {
+                .start          = IRQ_I2C0,
+                .end            = IRQ_I2C0,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static struct resource jz_i2c1_resources[] = {
+	[0] = {
+		.start          = CPHYSADDR(I2C1_BASE),
+		.end            = CPHYSADDR(I2C1_BASE) + 0x1000 - 1,
+		.flags          = IORESOURCE_MEM,
+	},
+  	[1] = {
+                .start          = IRQ_I2C1,
+                .end            = IRQ_I2C1,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static struct resource jz_i2c2_resources[] = {
+	[0] = {
+		.start          = CPHYSADDR(I2C2_BASE),
+		.end            = CPHYSADDR(I2C2_BASE) + 0x1000 - 1,
+		.flags          = IORESOURCE_MEM,
+	},
+  	[1] = {
+                .start          = IRQ_I2C2,
+                .end            = IRQ_I2C2,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static u64 jz_i2c_dmamask =  ~(u32)0;
+
+static struct platform_device jz_i2c0_device = {
+	.name = "jz_i2c0",
+	.id = 0,
+	.dev = {
+		.dma_mask               = &jz_i2c_dmamask,
+		.coherent_dma_mask      = 0xffffffff,
+	},
+	.num_resources  = ARRAY_SIZE(jz_i2c0_resources),
+	.resource       = jz_i2c0_resources,
+};
+
+static struct platform_device jz_i2c1_device = {
+	.name = "jz_i2c1",
+	.id = 1,
+	.dev = {
+		.dma_mask               = &jz_i2c_dmamask,
+		.coherent_dma_mask      = 0xffffffff,
+	},
+	.num_resources  = ARRAY_SIZE(jz_i2c1_resources),
+	.resource       = jz_i2c1_resources,
+};
+static struct platform_device jz_i2c2_device = {
+	.name = "jz_i2c2",
+	.id = 5,
+	.dev = {
+		.dma_mask               = &jz_i2c_dmamask,
+		.coherent_dma_mask      = 0xffffffff,
+	},
+	.num_resources  = ARRAY_SIZE(jz_i2c2_resources),
+	.resource       = jz_i2c2_resources,
+};
+
+/*AOSD*/
+static struct resource jz_aosd_resources[] = {
+	[0] = {
+		.start          = CPHYSADDR(AOSD_BASE),
+		.end            = CPHYSADDR(AOSD_BASE) + 0x1000 - 1,
+		.flags          = IORESOURCE_MEM,
+	},
+	[1] = {
+		.start          = IRQ_AOSD,
+		.end            = IRQ_AOSD,
+		.flags          = IORESOURCE_IRQ,
+	},
+};
+
+static u64 jz_aosd_dmamask =  ~(u32)0;
+
+static struct platform_device jz_aosd_device = {
+	.name = "jz-aosd",
+	.id = 0,
+	.dev = {
+		.dma_mask               = &jz_aosd_dmamask,
+		.coherent_dma_mask      = 0xffffffff,
+	},
+	.num_resources  = ARRAY_SIZE(jz_aosd_resources),
+	.resource       = jz_aosd_resources,
+};
+
+/* All */
+static struct platform_device *jz_platform_devices[] __initdata = {
+	&jz_usb_ohci_device,
+	&jz_usb_otg_xceiv_device,
+	&jz_usb_otg_device,
+	&jz_lcd_device,
+	&jz_aosd_device,
+	&jz_snd_device,
+	&jz_i2c0_device,
+	&jz_i2c1_device,
+	&jz_i2c2_device,
+};
+
+#ifdef CONFIG_ANDROID_PMEM
+/* ================================================================== */
+/* pmem  */
+#if 0
+static struct android_pmem_platform_data pmem_pdata = {
+	.name = "pmem",
+	.no_allocator = 1,
+	.cached = 1,
+	.start = 0x07800000, 	/* Low 512M mem */
+//	.start = 0x2F800000, 	/* upper 512M mem */
+	.size = 0x1000000,	/* pmem size 16M */
+};
+#else
+/*  [VIVANTE] PMEM devices. */
+static struct android_pmem_platform_data pmem_pdata = {
+	.name = "pmem",
+	.no_allocator = 1,
+	.cached = 1,
+};
+
+static struct android_pmem_platform_data pmem_adsp_pdata = {
+	.name = "pmem_adsp",
+	.no_allocator = 0,
+	.cached = 1,
+};
+
+#endif
+
+static struct platform_device pmem_device = {
+	.name = "android_pmem",
+	.id = 0,
+	.dev = { .platform_data = &pmem_pdata },
+};
+
+static struct platform_device pmem_adsp_device = {
+	.name = "android_pmem",
+	.id = 1,
+	.dev = { .platform_data = &pmem_adsp_pdata },
+};
+
+
+static void platform_pmem_device_setup(void)
+{
+//	platform_device_register(&pmem_device);
+	platform_device_register(&pmem_adsp_device);
+}
+
+#endif	/* #ifdef CONFIG_ANDROID_PMEM */
+
+
+static int __init jz_platform_init(void)
+{
+	int ret = 0;
+
+	board_i2c_init();
+	ret = platform_add_devices(jz_platform_devices, ARRAY_SIZE(jz_platform_devices));
+#ifdef CONFIG_ANDROID_PMEM
+	platform_pmem_device_setup();
+#endif
+
+	printk("jz_platform_init\n");
+//	board_msc_init();
+	return ret;
+}
+
+arch_initcall(jz_platform_init);
diff --git a/arch/mips/jz4770/pm.c b/arch/mips/jz4770/pm.c
new file mode 100644
index 00000000000..30bbadf8950
--- /dev/null
+++ b/arch/mips/jz4770/pm.c
@@ -0,0 +1,534 @@
+/*
+ * linux/arch/mips/jz4770/common/pm.c
+ *
+ * JZ4770 Power Management Routines
+ *
+ * Copyright (C) 2006 Ingenic Semiconductor Inc.
+ * Author: <jlwei@ingenic.cn>
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/pm.h>
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/suspend.h>
+#include <linux/proc_fs.h>
+#include <linux/sysctl.h>
+
+#include <asm/cacheops.h>
+#include <asm/jzsoc.h>
+
+#undef DEBUG
+//#define DEBUG
+#ifdef DEBUG
+#define dprintk(x...)	printk(x)
+#else
+#define dprintk(x...)
+#endif
+
+#define GPIO_PORT_NUM   6
+
+extern void jz_cpu_sleep(void);
+extern void jz_cpu_resume(void);
+
+/*
+ * __gpio_as_sleep set all pins to pull-disable, and set all pins as input
+ * except sdram and the pins which can be used as CS1_N to CS4_N for chip select.
+ */
+#define __gpio_as_sleep()	              \
+do {	                                      \
+	REG_GPIO_PXFUNC(1) = ~0x03ff7fff;     \
+	REG_GPIO_PXSELC(1) = ~0x03ff7fff;     \
+	REG_GPIO_PXDIRC(1) = ~0x03ff7fff;     \
+	REG_GPIO_PXPES(1)  =  0xffffffff;     \
+	REG_GPIO_PXFUNC(2) = ~0x01e00000;     \
+	REG_GPIO_PXSELC(2) = ~0x01e00000;     \
+	REG_GPIO_PXDIRC(2) = ~0x01e00000;     \
+	REG_GPIO_PXPES(2)  =  0xffffffff;     \
+	REG_GPIO_PXFUNC(3) =  0xffffffff;     \
+	REG_GPIO_PXSELC(3) =  0xffffffff;     \
+	REG_GPIO_PXDIRC(3) =  0xffffffff;     \
+	REG_GPIO_PXPES(3)  =  0xffffffff;     \
+	REG_GPIO_PXFUNC(4) =  0xffffffff;     \
+	REG_GPIO_PXSELC(4) =  0xffffffff;     \
+	REG_GPIO_PXDIRC(4) =  0xffffffff;     \
+	REG_GPIO_PXPES(4)  =  0xffffffff;     \
+	REG_GPIO_PXFUNC(5) =  0xffffffff;     \
+	REG_GPIO_PXSELC(5) =  0xffffffff;     \
+	REG_GPIO_PXDIRC(5) =  0xffffffff;     \
+	REG_GPIO_PXPES(5)  =  0xffffffff;     \
+} while (0)
+
+
+static int jz_pm_do_hibernate(void)
+{
+	printk("Put CPU into hibernate mode.\n");
+
+	/* Mask all interrupts */
+	REG_INTC_IMSR(0) = 0xffffffff;
+	REG_INTC_IMSR(1) = 0xffffffff;
+
+	/*
+	 * RTC Wakeup or 1Hz interrupt can be enabled or disabled
+	 * through  RTC driver's ioctl (linux/driver/char/rtc_jz.c).
+	 */
+#if 0
+	/* Set minimum wakeup_n pin low-level assertion time for wakeup: 100ms */
+	while (!(REG_RTC_RCR & RTC_RCR_WRDY));
+	REG_RTC_HWFCR = (100 << RTC_HWFCR_BIT);
+
+	/* Set reset pin low-level assertion time after wakeup: must  > 60ms */
+	while (!(REG_RTC_RCR & RTC_RCR_WRDY));
+	REG_RTC_HRCR = (60 << RTC_HRCR_BIT); /* 60 ms */
+
+	/* Scratch pad register to be reserved */
+	while (!(REG_RTC_RCR & RTC_RCR_WRDY));
+	REG_RTC_HSPR = 0x12345678;
+
+	/* clear wakeup status register */
+	while (!(REG_RTC_RCR & RTC_RCR_WRDY));
+	REG_RTC_HWRSR = 0x0;
+
+	/* Put CPU to power down mode */
+	while (!(REG_RTC_RCR & RTC_RCR_WRDY));
+	REG_RTC_HCR = RTC_HCR_PD;
+
+	while (!(REG_RTC_RCR & RTC_RCR_WRDY));
+	while(1);
+#endif
+
+	/* We can't get here */
+	return 0;
+}
+
+/* NOTES:
+ * 1: Pins that are floated (NC) should be set as input and pull-enable.
+ * 2: Pins that are pull-up or pull-down by outside should be set as input
+ *    and pull-disable.
+ * 3: Pins that are connected to a chip except sdram and nand flash
+ *    should be set as input and pull-disable, too.
+ */
+static void jz_board_do_sleep(unsigned long *ptr)
+{
+#if 0
+	unsigned char i;
+
+        /* Print messages of GPIO registers for debug */
+	for(i=0;i<GPIO_PORT_NUM;i++) {
+		dprintk("run dat:%x pin:%x fun:%x sel:%x dir:%x pull:%x msk:%x trg:%x\n",        \
+			REG_GPIO_PXDAT(i),REG_GPIO_PXPIN(i),REG_GPIO_PXFUN(i),REG_GPIO_PXSEL(i), \
+			REG_GPIO_PXDIR(i),REG_GPIO_PXPE(i),REG_GPIO_PXIM(i),REG_GPIO_PXTRG(i));
+	}
+
+        /* Save GPIO registers */
+	for(i = 1; i < GPIO_PORT_NUM; i++) {
+		*ptr++ = REG_GPIO_PXFUN(i);
+		*ptr++ = REG_GPIO_PXSEL(i);
+		*ptr++ = REG_GPIO_PXDIR(i);
+		*ptr++ = REG_GPIO_PXPE(i);
+		*ptr++ = REG_GPIO_PXIM(i);
+		*ptr++ = REG_GPIO_PXDAT(i);
+		*ptr++ = REG_GPIO_PXTRG(i);
+	}
+
+        /*
+         * Set all pins to pull-disable, and set all pins as input except
+         * sdram and the pins which can be used as CS1_N to CS4_N for chip select.
+         */
+        __gpio_as_sleep();
+
+        /*
+	 * Set proper status for GPC21 to GPC24 which can be used as CS1_N to CS4_N.
+	 * Keep the pins' function used for chip select(CS) here according to your
+         * system to avoid chip select crashing with sdram when resuming from sleep mode.
+         */
+
+#if defined(CONFIG_JZ4810_APUS)
+        /* GPB25/CS1_N is used as chip select for nand flash, shouldn't be change. */
+
+        /* GPB26/CS2_N is connected to nand flash, needn't be changed. */
+
+        /* GPB28/CS3_N is used as cs8900's chip select, shouldn't be changed. */
+
+	/* GPB27/CS4_N is used as NOR's chip select, shouldn't be changed. */
+#endif
+
+ 	/*
+         * Enable pull for NC pins here according to your system
+	 */
+
+#if defined(CONFIG_JZ4810_APUS)
+#endif
+
+	/*
+         * If you must set some GPIOs as output to high level or low level,
+         * you can set them here, using:
+         * __gpio_as_output(n);
+         * __gpio_set_pin(n); or  __gpio_clear_pin(n);
+	 */
+
+#if defined(CONFIG_JZ4810_APUS)
+	/* GPC7 which is used as AMPEN_N should be set to high to disable audio amplifier */
+	__gpio_as_output(32*2+7);
+	__gpio_set_pin(32*2+7);
+#endif
+
+#ifdef DEBUG
+        /* Keep uart function for printing debug message */
+	__gpio_as_uart0();
+	__gpio_as_uart1();
+	__gpio_as_uart2();
+	__gpio_as_uart3();
+
+        /* Print messages of GPIO registers for debug */
+	for(i=0;i<GPIO_PORT_NUM;i++) {
+		dprintk("sleep dat:%x pin:%x fun:%x sel:%x dir:%x pull:%x msk:%x trg:%x\n",      \
+			REG_GPIO_PXDAT(i),REG_GPIO_PXPIN(i),REG_GPIO_PXFUN(i),REG_GPIO_PXSEL(i), \
+			REG_GPIO_PXDIR(i),REG_GPIO_PXPE(i),REG_GPIO_PXIM(i),REG_GPIO_PXTRG(i));
+	}
+#endif
+#endif
+}
+
+static void jz_board_do_resume(unsigned long *ptr)
+{
+#if 0
+	unsigned char i;
+
+	/* Restore GPIO registers */
+	for(i = 1; i < GPIO_PORT_NUM; i++) {
+		 REG_GPIO_PXFUNS(i) = *ptr;
+		 REG_GPIO_PXFUNC(i) = ~(*ptr++);
+
+		 REG_GPIO_PXSELS(i) = *ptr;
+		 REG_GPIO_PXSELC(i) = ~(*ptr++);
+
+		 REG_GPIO_PXDIRS(i) = *ptr;
+		 REG_GPIO_PXDIRC(i) = ~(*ptr++);
+
+		 REG_GPIO_PXPES(i) = *ptr;
+		 REG_GPIO_PXPEC(i) = ~(*ptr++);
+
+		 REG_GPIO_PXIMS(i)=*ptr;
+		 REG_GPIO_PXIMC(i)=~(*ptr++);
+
+		 REG_GPIO_PXDATS(i)=*ptr;
+		 REG_GPIO_PXDATC(i)=~(*ptr++);
+
+		 REG_GPIO_PXTRGS(i)=*ptr;
+		 REG_GPIO_PXTRGC(i)=~(*ptr++);
+	}
+
+        /* Print messages of GPIO registers for debug */
+	for(i=0;i<GPIO_PORT_NUM;i++) {
+		dprintk("resume dat:%x pin:%x fun:%x sel:%x dir:%x pull:%x msk:%x trg:%x\n",     \
+			REG_GPIO_PXDAT(i),REG_GPIO_PXPIN(i),REG_GPIO_PXFUN(i),REG_GPIO_PXSEL(i), \
+			REG_GPIO_PXDIR(i),REG_GPIO_PXPE(i),REG_GPIO_PXIM(i),REG_GPIO_PXTRG(i));
+	}
+#endif
+}
+
+static int jz_pm_do_sleep(void)
+{
+#if 1
+	unsigned long delta;
+	unsigned long imr0 = REG_INTC_IMR(0);
+	unsigned long imr1 = REG_INTC_IMR(1);
+	unsigned long opcr = REG_CPM_OPCR;
+#if 0
+	unsigned long nfcsr = REG_EMC_NFCSR;
+
+	unsigned long sadc = REG_SADC_ENA;
+	unsigned long pmembs0 = REG_EMC_PMEMBS0;
+	unsigned long sleep_gpio_save[7*(GPIO_PORT_NUM-1)];
+#endif
+	unsigned long cpuflags;
+
+	printk("Put CPU into sleep mode.\n");
+
+	CMSREG32(CPM_LCR, CPM_LCR_LPM_SLEEP, CPM_LCR_LPM_MASK);
+
+	/* Preserve current time */
+	delta = xtime.tv_sec - REG_RTC_RSR;
+
+	/* Save CPU irqs */
+	local_irq_save(cpuflags);
+
+        /* Disable nand flash */
+	//REG_EMC_NFCSR = ~0xff;
+
+	/*pull up enable pin of DQS */
+	//REG_EMC_PMEMBS0 |= (0xff << 8);
+
+        /* stop sadc */
+	//REG_SADC_ENA &= ~0x7;
+	//while((REG_SADC_ENA & 0x7) != 0);
+ 	//udelay(100);
+
+        /*stop udc and usb*/
+	//__cpm_suspend_uhc_phy();
+	//__cpm_suspend_otg_phy();
+
+	/*stop gps*/
+	//__cpm_suspend_gps();
+
+	/* Mask all interrupts */
+	REG_INTC_IMSR(0) = 0xffffffff;
+	REG_INTC_IMSR(1) = 0xffffffff;
+
+	/* Sleep on-board modules */
+	//jz_board_do_sleep(sleep_gpio_save);
+
+#if 0
+	/* Just allow following interrupts to wakeup the system.
+	 * Note: modify this according to your system.
+	 */
+
+	/* enable RTC alarm */
+	__intc_unmask_irq(IRQ_RTC);
+
+        /* make system wake up after n seconds by RTC alarm */
+	unsigned int v, n;
+	n = 5;
+	while (!__rtc_write_ready());
+	__rtc_enable_alarm();
+	while (!__rtc_write_ready());
+	__rtc_enable_alarm_irq();
+ 	while (!__rtc_write_ready());
+ 	v = __rtc_get_second();
+ 	while (!__rtc_write_ready());
+ 	__rtc_set_alarm_second(v+n);
+
+
+#endif
+	/* WAKEUP key */
+	/* PD17: boot_sel[0] */
+	__gpio_as_irq_fall_edge(32 * 3 + 17);
+	__gpio_ack_irq(32 * 3 + 17);
+	__gpio_unmask_irq(32 * 3 + 17);
+	__intc_unmask_irq(IRQ_GPIO0 - ((32 * 3 + 17)/32));  /* unmask IRQ_GPIOn depends on GPIO_WAKEUP */
+
+	REG_GPIO_PXFLGC(3) = 0xffffffff;
+	printk("===>int = 0x%08x\n", REG_GPIO_PXINT(3));
+        printk("===>mask = 0x%08x\n", REG_GPIO_PXMASK(3));
+        printk("===>pat1 = 0x%08x\n", REG_GPIO_PXPAT1(3));
+        printk("===>pat0 = 0x%08x\n", REG_GPIO_PXPAT0(3));
+        printk("===>flag = 0x%08x\n", REG_GPIO_PXFLG(3));
+
+	printk("gpio_level = %d IPR0 = 0x%08x IPR1 = 0x%08x\n",
+		__gpio_get_pin(32 * 3 + 17), REG_INTC_IPR(0), REG_INTC_IPR(1));
+
+	printk("===>enter sleeping ......\n");
+#if 0
+	printk("Shutdown P0 ......\n");
+	/*power down the p0*/
+	REG_CPM_OPCR |= CPM_OPCR_PD;
+
+	/* disable externel clock Oscillator in sleep mode */
+	__cpm_disable_osc_in_sleep();
+	/* select 32K crystal as RTC clock in sleep mode */
+	__cpm_select_rtcclk_rtc();
+
+       	/* Clear previous reset status */
+	REG_CPM_RSR &= ~(CPM_RSR_PR | CPM_RSR_WR | CPM_RSR_P0R);
+
+       	/* Set resume return address */
+	REG_CPM_CPPSR = virt_to_phys(jz_cpu_resume);
+
+	/* *** go zzz *** */
+	jz_cpu_sleep();
+
+#else
+
+	__asm__(".set\tmips3\n\t"
+		"sync\n\t"
+		"wait\n\t"
+		"nop\n\t"
+		"nop\n\t"
+		"nop\n\t"
+		"nop\n\t"
+		".set\tmips0");
+#endif
+
+	/*if power down p0 ,return from sleep.S*/
+	printk("gpio_level = %d IPR0 = 0x%08x IPR1 = 0x%08x\n",
+		__gpio_get_pin(32 * 3 + 17), REG_INTC_IPR(0), REG_INTC_IPR(1));
+	__gpio_ack_irq(32 * 3 + 17);
+
+	/* Restore to IDLE mode */
+	CMSREG32(CPM_LCR, CPM_LCR_LPM_IDLE, CPM_LCR_LPM_MASK);
+
+        /* Restore nand flash control register */
+	//REG_EMC_NFCSR = nfcsr;
+
+	/*Restore pmembs0*/
+	//REG_EMC_PMEMBS0 = pmembs0;
+
+	/* Restore interrupts */
+	REG_INTC_IMSR(0) = imr0;
+	REG_INTC_IMSR(1) = imr1;
+
+	REG_INTC_IMCR(0) = ~imr0;
+	REG_INTC_IMCR(1) = ~imr1;
+
+	/* Restore sadc */
+	//REG_SADC_ENA = sadc;
+
+	/* Resume on-board modules */
+	//jz_board_do_resume(sleep_gpio_save);
+
+	/* Restore Oscillator and Power Control Register */
+	REG_CPM_OPCR = opcr;
+
+	/* Restore CPU interrupt flags */
+	local_irq_restore(cpuflags);
+
+	/* Restore current time */
+	xtime.tv_sec = REG_RTC_RSR + delta;
+
+	printk("Resume CPU from sleep mode.\n");
+#endif
+	return 0;
+}
+
+#define K0BASE  KSEG0
+void jz_flush_cache_all(void)
+{
+	unsigned long addr;
+
+	/* Clear CP0 TagLo */
+	asm volatile ("mtc0 $0, $28\n\t"::);
+
+	for (addr = K0BASE; addr < (K0BASE + 0x4000); addr += 32) {
+		asm volatile (
+			".set mips3\n\t"
+			" cache %0, 0(%1)\n\t"
+			".set mips2\n\t"
+			:
+			: "I" (Index_Writeback_Inv_D), "r"(addr));
+
+		asm volatile (
+			".set mips3\n\t"
+			" cache %0, 0(%1)\n\t"
+			".set mips2\n\t"
+			:
+			: "I" (Index_Store_Tag_I), "r"(addr));
+	}
+
+	asm volatile ("sync\n\t"::);
+
+	/* invalidate BTB */
+	asm volatile (
+		".set mips32\n\t"
+		" mfc0 %0, $16, 7\n\t"
+		" nop\n\t"
+		" ori $0, 2\n\t"
+		" mtc0 %0, $16, 7\n\t"
+		" nop\n\t"
+		".set mips2\n\t"
+		:
+		: "r"(addr));
+}
+
+#if 0
+#ifndef CONFIG_JZ_POWEROFF
+static irqreturn_t pm_irq_handler (int irq, void *dev_id)
+{
+	return IRQ_HANDLED;
+}
+#endif
+
+/* Put CPU to SLEEP mode */
+int jz_pm_sleep(void)
+{
+	int retval;
+
+#ifndef CONFIG_JZ_POWEROFF
+	if ((retval = request_irq (IRQ_GPIO_0 + GPIO_WAKEUP, pm_irq_handler, IRQF_DISABLED,
+				   "PM", NULL))) {
+		printk ("PM could not get IRQ for GPIO_WAKEUP\n");
+		return retval;
+	}
+#endif
+
+	retval = jz_pm_do_sleep();
+
+#ifndef CONFIG_JZ_POWEROFF
+	free_irq (IRQ_GPIO_0 + GPIO_WAKEUP, NULL);
+#endif
+
+	return retval;
+}
+#endif
+
+/* Put CPU to HIBERNATE mode
+ *----------------------------------------------------------------------------
+ * Power Management sleep sysctl interface
+ *
+ * Write "mem" to /sys/power/state invokes this function
+ * which initiates a poweroff.
+ */
+void jz_pm_hibernate(void)
+{
+	jz_pm_do_hibernate();
+}
+
+/* Put CPU to SLEEP mode
+ *----------------------------------------------------------------------------
+ * Power Management sleep sysctl interface
+ *
+ * Write "standby" to /sys/power/state invokes this function
+ * which initiates a sleep.
+ */
+
+int jz_pm_sleep(void)
+{
+	return jz_pm_do_sleep();
+}
+
+/*
+ * valid states, only support standby(sleep) and mem(hibernate)
+ */
+static int jz4770_pm_valid(suspend_state_t state)
+{
+	return state == PM_SUSPEND_MEM;
+}
+
+/*
+ * Jz CPU enter save power mode
+ */
+static int jz4770_pm_enter(suspend_state_t state)
+{
+	return jz_pm_do_sleep();
+}
+
+static struct platform_suspend_ops jz4770_pm_ops = {
+	.valid		= jz4770_pm_valid,
+	.enter		= jz4770_pm_enter,
+};
+
+/*
+ * Initialize power interface
+ */
+int __init jz_pm_init(void)
+{
+	printk("Power Management for JZ\n");
+
+	suspend_set_ops(&jz4770_pm_ops);
+	return 0;
+}
+
diff --git a/arch/mips/jz4770/proc.c b/arch/mips/jz4770/proc.c
new file mode 100644
index 00000000000..74b6c534d7e
--- /dev/null
+++ b/arch/mips/jz4770/proc.c
@@ -0,0 +1,916 @@
+/*
+ * linux/arch/mips/jz4770/proc.c
+ * 
+ * /proc/jz/ procfs for jz4770 on-chip modules.
+ * 
+ * Copyright (C) 2006 Ingenic Semiconductor Inc.
+ * Author: <jlwei@ingenic.cn>
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/sysctl.h>
+#include <linux/proc_fs.h>
+#include <linux/page-flags.h>
+#include <asm/uaccess.h>
+#include <asm/pgtable.h>
+#include <asm/jzsoc.h>
+
+//#define DEBUG 1
+#undef DEBUG
+
+extern void jz4770_fpu_init(unsigned int round);
+
+struct proc_dir_entry *proc_jz_root;
+
+
+/*
+ * EMC Modules
+ */
+static int emc_read_proc (char *page, char **start, off_t off,
+			  int count, int *eof, void *data)
+{
+	int len = 0;
+
+	len += sprintf (page+len, "SMCR(0-5): 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", REG_EMC_SMCR0, REG_EMC_SMCR1, REG_EMC_SMCR2, REG_EMC_SMCR3, REG_EMC_SMCR4);
+	len += sprintf (page+len, "SACR(0-5): 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", REG_EMC_SACR0, REG_EMC_SACR1, REG_EMC_SACR2, REG_EMC_SACR3, REG_EMC_SACR4);
+	len += sprintf (page+len, "DMCR:      0x%08x\n", REG_EMC_DMCR);
+	len += sprintf (page+len, "RTCSR:     0x%04x\n", REG_EMC_RTCSR);
+	len += sprintf (page+len, "RTCOR:     0x%04x\n", REG_EMC_RTCOR);
+	return len;
+}
+
+/* 
+ * Power Manager Module
+ */
+static int pmc_read_proc (char *page, char **start, off_t off,
+			  int count, int *eof, void *data)
+{
+	int len = 0;
+	unsigned long lcr = REG_CPM_LCR;
+//	unsigned long clkgr = REG_CPM_CLKGR;
+
+	len += sprintf (page+len, "Low Power Mode : %s\n", 
+			((lcr & CPM_LCR_LPM_MASK) == (CPM_LCR_LPM_IDLE)) ?
+			"IDLE" : (((lcr & CPM_LCR_LPM_MASK) == (CPM_LCR_LPM_SLEEP)) ? 
+				  "SLEEP" : "HIBERNATE"));
+	len += sprintf (page+len, "Doze Mode      : %s\n", 
+			(lcr & CPM_LCR_DOZE_ON) ? "on" : "off");
+	if (lcr & CPM_LCR_DOZE_ON)
+		len += sprintf (page+len, "     duty      : %d\n", (int)((lcr & CPM_LCR_DOZE_DUTY_MASK) >> CPM_LCR_DOZE_DUTY_BIT));
+
+/*
+	len += sprintf (page+len, "AUX_CPU        : %s\n",
+			(clkgr & CPM_CLKGR_AUX_CPU) ? "stopped" : "running");
+	len += sprintf (page+len, "AHB1           : %s\n",
+			(clkgr & CPM_CLKGR_AHB1) ? "stopped" : "running");
+	len += sprintf (page+len, "IDCT           : %s\n",
+			(clkgr & CPM_CLKGR_IDCT) ? "stopped" : "running");
+	len += sprintf (page+len, "DB             : %s\n",
+			(clkgr & CPM_CLKGR_DB) ? "stopped" : "running");
+	len += sprintf (page+len, "ME             : %s\n",
+			(clkgr & CPM_CLKGR_ME) ? "stopped" : "running");
+	len += sprintf (page+len, "MC             : %s\n",
+			(clkgr & CPM_CLKGR_MC) ? "stopped" : "running");
+	len += sprintf (page+len, "TVE            : %s\n",
+			(clkgr & CPM_CLKGR_TVE) ? "stopped" : "running");
+	len += sprintf (page+len, "TSSI           : %s\n",
+			(clkgr & CPM_CLKGR_TSSI) ? "stopped" : "running");
+	len += sprintf (page+len, "IPU            : %s\n",
+			(clkgr & CPM_CLKGR_IPU) ? "stopped" : "running");
+	len += sprintf (page+len, "DMAC           : %s\n",
+			(clkgr & CPM_CLKGR_DMAC) ? "stopped" : "running");
+	len += sprintf (page+len, "UDC            : %s\n",
+			(clkgr & CPM_CLKGR_UDC) ? "stopped" : "running");
+	len += sprintf (page+len, "LCD            : %s\n",
+			(clkgr & CPM_CLKGR_LCD) ? "stopped" : "running");
+	len += sprintf (page+len, "CIM            : %s\n",
+			(clkgr & CPM_CLKGR_CIM) ? "stopped" : "running");
+	len += sprintf (page+len, "SADC           : %s\n",
+			(clkgr & CPM_CLKGR_SADC) ? "stopped" : "running");
+	len += sprintf (page+len, "MSC0           : %s\n",
+			(clkgr & CPM_CLKGR_MSC0) ? "stopped" : "running");
+	len += sprintf (page+len, "MSC1           : %s\n",
+			(clkgr & CPM_CLKGR_MSC1) ? "stopped" : "running");
+	len += sprintf (page+len, "SSI           : %s\n",
+			(clkgr & CPM_CLKGR_SSI) ? "stopped" : "running");
+	len += sprintf (page+len, "I2C            : %s\n",
+			(clkgr & CPM_CLKGR_I2C) ? "stopped" : "running");
+	len += sprintf (page+len, "RTC            : %s\n",
+			(clkgr & CPM_CLKGR_RTC) ? "stopped" : "running");
+	len += sprintf (page+len, "TCU            : %s\n",
+			(clkgr & CPM_CLKGR_TCU) ? "stopped" : "running");
+	len += sprintf (page+len, "UART1          : %s\n",
+			(clkgr & CPM_CLKGR_UART1) ? "stopped" : "running");
+	len += sprintf (page+len, "UART0          : %s\n",
+			(clkgr & CPM_CLKGR_UART0) ? "stopped" : "running");
+*/
+	return len;
+}
+
+static int pmc_write_proc(struct file *file, const char *buffer, unsigned long count, void *data)
+{
+	REG_CPM_CLKGR = simple_strtoul(buffer, 0, 16);
+	return count;
+}
+
+/*
+ * Clock Generation Module
+ */
+#define TO_MHZ(x) (x/1000000),(x%1000000)/10000
+#define TO_KHZ(x) (x/1000),(x%1000)/10
+
+static int cgm_read_proc (char *page, char **start, off_t off,
+			  int count, int *eof, void *data)
+{
+	int len = 0;
+	unsigned int cppcr = REG_CPM_CPPCR;  /* PLL Control Register */
+	unsigned int cpccr = REG_CPM_CPCCR;  /* Clock Control Register */
+	unsigned int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
+	unsigned int od[4] = {1, 2, 2, 4};
+
+	len += sprintf (page+len, "CPPCR          : 0x%08x\n", cppcr);
+	len += sprintf (page+len, "CPCCR          : 0x%08x\n", cpccr);
+	len += sprintf (page+len, "PLL            : %s\n", 
+			(cppcr & CPM_CPPCR_PLLEN) ? "ON" : "OFF");
+	len += sprintf (page+len, "m:n:o          : %d:%d:%d\n",
+			__cpm_get_pllm() + 2,
+			__cpm_get_plln() + 2,
+			od[__cpm_get_pllod()]
+		);
+	len += sprintf (page+len, "C:H:M:P        : %d:%d:%d:%d\n", 
+			div[__cpm_get_cdiv()],
+			div[__cpm_get_hdiv()],
+			div[__cpm_get_mdiv()],
+			div[__cpm_get_pdiv()]
+		);
+	len += sprintf (page+len, "PLL Freq        : %3d.%02d MHz\n", TO_MHZ(__cpm_get_pllout()));
+	len += sprintf (page+len, "CCLK            : %3d.%02d MHz\n", TO_MHZ(__cpm_get_cclk()));
+	len += sprintf (page+len, "HCLK            : %3d.%02d MHz\n", TO_MHZ(__cpm_get_hclk()));
+	len += sprintf (page+len, "MCLK            : %3d.%02d MHz\n", TO_MHZ(__cpm_get_mclk()));
+	len += sprintf (page+len, "PCLK            : %3d.%02d MHz\n", TO_MHZ(__cpm_get_pclk()));
+	len += sprintf (page+len, "H2CLK           : %3d.%02d MHz\n", TO_MHZ(__cpm_get_h2clk()));
+	len += sprintf (page+len, "PIXCLK          : %3d.%02d KHz\n", TO_KHZ(__cpm_get_pixclk()));
+	len += sprintf (page+len, "I2SCLK          : %3d.%02d MHz\n", TO_MHZ(__cpm_get_i2sclk()));
+	len += sprintf (page+len, "USBCLK          : %3d.%02d MHz\n", TO_MHZ(__cpm_get_otgclk()));
+	len += sprintf (page+len, "MSC0CLK         : %3d.%02d MHz\n", TO_MHZ(__cpm_get_mscclk(0)));
+	len += sprintf (page+len, "MSC1CLK         : %3d.%02d MHz\n", TO_MHZ(__cpm_get_mscclk(1)));
+	len += sprintf (page+len, "EXTALCLK0       : %3d.%02d MHz\n", TO_MHZ(__cpm_get_extalclk0()));
+	len += sprintf (page+len, "EXTALCLK(by CPM): %3d.%02d MHz\n", TO_MHZ(__cpm_get_extalclk()));
+	len += sprintf (page+len, "RTCCLK          : %3d.%02d MHz\n", TO_MHZ(__cpm_get_rtcclk()));
+
+	return len;
+}
+
+static int cgm_write_proc(struct file *file, const char *buffer, unsigned long count, void *data)
+{
+	REG_CPM_CPCCR = simple_strtoul(buffer, 0, 16);
+	return count;
+}
+
+
+/* USAGE:  
+ * echo n  > /proc/jz/ipu 	// n = [1,...,9], alloc mem, 2^n pages.
+ * echo FF > /proc/jz/ipu 	// 255, free all buffer
+ * echo xxxx > /proc/jz/ipu 	// free buffer which addr is xxxx
+ * echo llll > /proc/jz/ipu 	// add_wired_entry(l,l,l,l)
+ * echo 0  > /proc/jz/ipu 	// debug, print ipu_buf 
+ * od -X /proc/jz/ipu 		// read mem addr
+ */
+
+typedef struct _ipu_buf {
+	unsigned int addr;	/* phys addr */
+	unsigned int page_shift;
+} ipu_buf_t;
+
+#define IPU_BUF_MAX 		4 	/* 4 buffers */
+
+static struct _ipu_buf ipu_buf[IPU_BUF_MAX];
+static int ipu_buf_cnt = 0;
+static unsigned char g_asid=0;
+
+extern void local_flush_tlb_all(void);
+
+/* CP0 hazard avoidance. */
+#define BARRIER __asm__ __volatile__(".set noreorder\n\t" \
+				     "nop; nop; nop; nop; nop; nop;\n\t" \
+				     ".set reorder\n\t")
+void show_tlb(void)
+{
+#define ASID_MASK 0xFF
+
+        unsigned long flags;
+        unsigned int old_ctx;
+	unsigned int entry;
+	unsigned int entrylo0, entrylo1, entryhi;
+	unsigned int pagemask;
+
+	local_irq_save(flags);
+
+	/* Save old context */
+	old_ctx = (read_c0_entryhi() & 0xff);
+
+	printk("TLB content:\n");
+	entry = 0;
+	while(entry < 32) {
+		write_c0_index(entry);
+		BARRIER;
+		tlb_read();
+		BARRIER;
+		entryhi = read_c0_entryhi();
+		entrylo0 = read_c0_entrylo0();
+		entrylo1 = read_c0_entrylo1();
+		pagemask = read_c0_pagemask();
+		printk("%02d: ASID=%02d%s VA=0x%08x ", entry, entryhi & ASID_MASK, (entrylo0 & entrylo1 & 1) ? "(G)" : "   ", entryhi & ~ASID_MASK);
+		printk("PA0=0x%08x C0=%x %s%s%s\n", (entrylo0>>6)<<12, (entrylo0>>3) & 7, (entrylo0 & 4) ? "Dirty " : "", (entrylo0 & 2) ? "Valid " : "Invalid ", (entrylo0 & 1) ? "Global" : "");
+		printk("\t\t\t     PA1=0x%08x C1=%x %s%s%s\n", (entrylo1>>6)<<12, (entrylo1>>3) & 7, (entrylo1 & 4) ? "Dirty " : "", (entrylo1 & 2) ? "Valid " : "Invalid ", (entrylo1 & 1) ? "Global" : "");
+
+		printk("\t\tpagemask=0x%08x", pagemask);
+		printk("\tentryhi=0x%08x\n", entryhi);
+		printk("\t\tentrylo0=0x%08x", entrylo0);
+		printk("\tentrylo1=0x%08x\n", entrylo1);
+
+		entry++;
+	}
+	BARRIER;
+	write_c0_entryhi(old_ctx);
+
+	local_irq_restore(flags);
+}
+
+static void ipu_add_wired_entry(unsigned long pid,
+				unsigned long entrylo0, unsigned long entrylo1,
+				unsigned long entryhi, unsigned long pagemask)
+{
+	unsigned long flags;
+	unsigned long wired;
+	unsigned long old_pagemask;
+	unsigned long old_ctx;
+	struct task_struct *g, *p;
+
+	/* We will lock an 4MB page size entry to map the 4MB reserved IPU memory */
+	wired = read_c0_wired();
+	if (wired) return;
+
+	do_each_thread(g, p) {
+		if (p->pid == pid )
+			g_asid = p->mm->context[0];
+	} while_each_thread(g, p);
+	
+
+	local_irq_save(flags);
+
+	entrylo0 = entrylo0 >> 6;   /* PFN */
+	entrylo0 |= 0x6 | (0 << 3); /* Write-through cacheable, dirty, valid */
+
+	/* Save old context and create impossible VPN2 value */
+	old_ctx = read_c0_entryhi() & 0xff;
+	old_pagemask = read_c0_pagemask();
+	wired = read_c0_wired();
+	write_c0_wired(wired + 1);
+	write_c0_index(wired);
+	BARRIER;
+	entryhi &= ~0xff;	/* new add, 20070906 */
+	entryhi |= g_asid;	/* new add, 20070906 */
+//	entryhi |= old_ctx;	/* new add, 20070906 */
+	write_c0_pagemask(pagemask);
+	write_c0_entryhi(entryhi);
+	write_c0_entrylo0(entrylo0);
+	write_c0_entrylo1(entrylo1);
+	BARRIER;
+	tlb_write_indexed();
+	BARRIER;
+
+	write_c0_entryhi(old_ctx);
+	BARRIER;
+	write_c0_pagemask(old_pagemask);
+	local_flush_tlb_all();
+	local_irq_restore(flags);
+#if defined(DEBUG)
+	printk("\nold_ctx=%03d\n", old_ctx);
+
+	show_tlb();
+#endif
+}
+
+static void ipu_del_wired_entry( void )
+{
+	unsigned long flags;	
+	unsigned long wired;	
+
+	local_irq_save(flags);
+	wired = read_c0_wired();
+	if ( wired > 0 ) {
+		write_c0_wired(wired - 1);
+	}
+	local_irq_restore(flags);
+}
+
+static inline void ipu_buf_get( unsigned int page_shift )
+{
+	unsigned char * virt_addr;
+	int i;
+	for ( i=0; i< IPU_BUF_MAX; ++i ) {
+		if ( ipu_buf[i].addr == 0 ) {
+			break;
+		}
+	}
+
+	if ( (ipu_buf_cnt = i) == IPU_BUF_MAX ) {
+		printk("Error, no free ipu buffer.\n");
+		return ;
+	}
+
+	virt_addr =  (unsigned char *)__get_free_pages(GFP_KERNEL, page_shift);
+
+	if ( virt_addr ) {
+		ipu_buf[ipu_buf_cnt].addr = (unsigned int)virt_to_phys((void *)virt_addr);
+		ipu_buf[ipu_buf_cnt].page_shift = page_shift;
+
+		for (i = 0; i < (1<<page_shift); i++) {
+			SetPageReserved(virt_to_page(virt_addr));
+			virt_addr += PAGE_SIZE;
+		}
+	}
+	else {
+		printk("get memory Failed.\n");
+	}
+}
+
+static inline void ipu_buf_free( unsigned int phys_addr )
+{
+	unsigned char * virt_addr, *addr;
+	int cnt, i;
+
+	if ( phys_addr == 0 ) 
+		return ;
+
+	for ( cnt=0; cnt<IPU_BUF_MAX; ++cnt ) 
+		if ( phys_addr == ipu_buf[cnt].addr ) 
+			break;
+
+	if ( cnt == IPU_BUF_MAX ) {	/* addr not in the ipu buffers */
+		printk("Invalid addr:0x%08x\n", (unsigned int)phys_addr);
+	}
+
+	virt_addr = (unsigned char *)phys_to_virt(ipu_buf[cnt].addr);
+	addr = virt_addr;
+	for (i = 0; i < (1<<ipu_buf[cnt].page_shift); i++) {
+		ClearPageReserved(virt_to_page(addr));
+		addr += PAGE_SIZE;
+	}
+
+	if ( cnt == 0 )
+		ipu_del_wired_entry();
+
+	free_pages((unsigned long )virt_addr, ipu_buf[cnt].page_shift);
+
+	ipu_buf[cnt].addr = 0;
+	ipu_buf[cnt].page_shift = 0;
+}
+
+static int ipu_read_proc (char *page, char **start, off_t off,
+			  int count, int *eof, void *data)
+{
+	int len = 0;
+
+	/* read as binary */
+	unsigned int * pint;
+	pint = (unsigned int *) (page+len);
+
+	if ( ipu_buf_cnt >= IPU_BUF_MAX ) {	/* failed alloc mem, rturn 0 */
+		printk("no free buffer.\n");
+		*pint = 0;
+	}
+	else 
+		*pint = (unsigned int )ipu_buf[ipu_buf_cnt].addr; /* phys addr */
+	len += sizeof(unsigned int);
+
+#if defined(DEBUG)
+		show_tlb();
+#endif
+	return len;
+
+}
+
+static int ipu_write_proc(struct file *file, const char *buffer, unsigned long count, void *data)
+{
+	unsigned int val ;
+	int cnt,i;
+	char buf[12];
+	unsigned long pid, entrylo0, entrylo1, entryhi, pagemask;
+#if defined(DEBUG)
+	printk("ipu write count=%u\n", count);
+#endif
+	if (count == (8*5+1)) {
+		for (i=0;i<12;i++) buf[i]=0;
+		strncpy(buf, buffer+8*0, 8);
+		pid = simple_strtoul(buf, 0, 16);
+		for (i=0;i<12;i++) buf[i]=0;
+		strncpy(buf, buffer+8*1, 8);
+		entrylo0 = simple_strtoul(buf, 0, 16);
+		for (i=0;i<12;i++) buf[i]=0;
+		strncpy(buf, buffer+8*2, 8);
+		entrylo1 = simple_strtoul(buf, 0, 16);
+		for (i=0;i<12;i++) buf[i]=0;
+		strncpy(buf, buffer+8*3, 8);
+		entryhi = simple_strtoul(buf, 0, 16);
+		for (i=0;i<12;i++) buf[i]=0;
+		strncpy(buf, buffer+8*4, 8);
+		pagemask = simple_strtoul(buf, 0, 16);
+		
+#if defined(DEBUG)		
+		printk("pid=0x%08x, entrylo0=0x%08x, entrylo1=0x%08x, entryhi=0x%08x, pagemask=0x%08x\n", 
+		       pid, entrylo0, entrylo1, entryhi, pagemask);
+#endif		
+		ipu_add_wired_entry( pid, entrylo0, entrylo1, entryhi, pagemask);
+		return 41;
+	}
+	else if ( count <= 8+1 ) {
+		for (i=0;i<12;i++) buf[i]=0;
+		strncpy(buf, buffer, 8);
+		val = simple_strtoul(buf, 0, 16);
+	} else if (count == 44) {
+		for (i = 0; i < 12; i++) 
+			buf[i] = 0;
+		strncpy(buf, buffer, 10);
+		pid = simple_strtoul(buf, 0, 16);
+		for (i = 0; i < 12; i++) 
+			buf[i] = 0;
+		strncpy(buf, buffer + 11, 10);
+		entryhi = simple_strtoul(buf, 0, 16);//vaddr
+		for (i = 0; i < 12; i++) 
+			buf[i] = 0;
+		strncpy(buf, buffer + 22, 10);
+		entrylo0 = simple_strtoul(buf, 0, 16);//paddr
+		for (i = 0; i < 12; i++) 
+			buf[i] = 0;
+		strncpy(buf, buffer + 33, 10);
+		pagemask = simple_strtoul(buf, 0, 16);
+		pagemask = 0x3ff << 13; /* Fixed to 4MB page size */
+		ipu_add_wired_entry(pid, entrylo0, 0, entryhi, pagemask);
+		return 44;
+	} else {
+		printk("ipu write count error, count=%d\n.", (unsigned int)count);
+		return -1;
+	}
+
+	/* val: 1-9, page_shift,  val>= 10: ipu_buf.addr */
+	if ( val == 0 ) {	/* debug, print ipu_buf info */
+		for ( cnt=0; cnt<IPU_BUF_MAX; ++cnt) 
+			printk("ipu_buf[%d]: addr=0x%08x, page_shift=%d\n", 
+			       cnt, ipu_buf[cnt].addr, ipu_buf[cnt].page_shift );
+#if defined(DEBUG)
+		show_tlb();
+#endif
+	}
+	else if ( 0< val && val < 10 ) {
+		ipu_buf_get(val);
+	}
+	else if ( val == 0xff ) { /* 255: free all ipu_buf */
+		for ( cnt=0; cnt<IPU_BUF_MAX; ++cnt ) {
+			ipu_buf_free(ipu_buf[cnt].addr);
+		}
+	}
+	else {			
+		ipu_buf_free(val);
+	}
+
+	return count;
+}
+
+/*
+ * UDC hotplug
+ */
+#ifdef CONFIG_JZ_UDC_HOTPLUG
+extern int jz_udc_active;	/* defined in drivers/char/jzchar/jz_udc_hotplug.c */
+#endif
+
+#ifndef GPIO_UDC_HOTPLUG
+#define GPIO_UDC_HOTPLUG 86
+#endif
+
+static int udc_read_proc(char *page, char **start, off_t off,
+			 int count, int *eof, void *data)
+{
+        int len = 0;
+
+	if (__gpio_get_pin(GPIO_UDC_HOTPLUG)) {
+
+#ifdef CONFIG_JZ_UDC_HOTPLUG
+
+		/* Cable has connected, wait for disconnection. */
+		__gpio_as_irq_fall_edge(GPIO_UDC_HOTPLUG);
+
+		if (jz_udc_active)
+			len += sprintf (page+len, "CONNECT_CABLE\n");
+		else
+			len += sprintf (page+len, "CONNECT_POWER\n");
+#else
+		len += sprintf (page+len, "CONNECT\n");
+#endif
+	}
+	else {
+
+#ifdef CONFIG_JZ_UDC_HOTPLUG
+		/* Cable has disconnected, wait for connection. */
+		__gpio_as_irq_rise_edge(GPIO_UDC_HOTPLUG);
+#endif
+
+		len += sprintf (page+len, "REMOVE\n");
+	}
+                                                                                                               
+        return len;
+}
+
+/*
+ * MMC/SD hotplug
+ */
+
+#ifndef MSC_HOTPLUG_PIN
+#define MSC_HOTPLUG_PIN 90
+#endif
+
+static int mmc_read_proc (char *page, char **start, off_t off,
+                          int count, int *eof, void *data)
+{
+        int len = 0;
+
+        if (__gpio_get_pin(MSC_HOTPLUG_PIN))
+                len += sprintf (page+len, "REMOVE\n");
+        else
+                len += sprintf (page+len, "INSERT\n");
+
+        return len;
+}
+
+#ifndef CONFIG_ANDROID_PMEM	/* /dev/pmem instead /proc/jz/imem on android platform */
+
+/***********************************************************************
+ * IPU memory management (used by mplayer and other apps)
+ *
+ * We reserved 4MB memory for IPU
+ * The memory base address is jz_ipu_framebuf
+ */
+
+/* Usage:
+ *
+ * echo n  > /proc/jz/imem 		// n = [0,...,10], allocate memory, 2^n pages
+ * echo xxxxxxxx > /proc/jz/imem	// free buffer which addr is xxxxxxxx
+ * echo FF > /proc/jz/ipu 		// FF, free all buffers
+ * od -X /proc/jz/imem 			// return the allocated buffer address and the max order of free buffer
+ */
+
+//#define DEBUG_IMEM 1
+
+#define IMEM_MAX_ORDER 10		/* max 2^10 * 4096 = 4MB */
+
+static unsigned int jz_imem_base;	/* physical base address of ipu memory */
+
+static unsigned int allocated_phys_addr = 0;
+
+/* 
+ * Allocated buffer list
+ */
+typedef struct imem_list {
+	unsigned int phys_start;	/* physical start addr */
+	unsigned int phys_end;		/* physical end addr */
+	struct imem_list *next;
+} imem_list_t;
+
+static struct imem_list *imem_list_head = NULL; /* up sorted by phys_start */
+
+#ifdef DEBUG_IMEM
+static void dump_imem_list(void)
+{
+	struct imem_list *imem;
+
+	printk("*** dump_imem_list 0x%x ***\n", (u32)imem_list_head);
+	imem = imem_list_head;
+	while (imem) {
+		printk("imem=0x%x phys_start=0x%x phys_end=0x%x next=0x%x\n", (u32)imem, imem->phys_start, imem->phys_end, (u32)imem->next);
+		imem = imem->next;
+	}
+}
+#endif
+
+/* allocate 2^order pages inside the 4MB memory */
+static int imem_alloc(unsigned int order)
+{
+	int alloc_ok = 0;
+	unsigned int start, end;
+	unsigned int size = (1 << order) * PAGE_SIZE;
+	struct imem_list *imem, *imemn, *imemp;
+
+	allocated_phys_addr = 0;
+
+	start = jz_imem_base;
+	end = start + (1 << IMEM_MAX_ORDER) * PAGE_SIZE;
+
+	imem = imem_list_head;
+	while (imem) {
+		if ((imem->phys_start - start) >= size) {
+			/* we got a valid address range */
+			alloc_ok = 1;
+			break;
+		}
+
+		start = imem->phys_end + 1;
+		imem = imem->next;
+	}
+
+	if (!alloc_ok) {
+		if ((end - start) >= size)
+			alloc_ok = 1;
+	}
+
+	if (alloc_ok) {
+		end = start + size - 1;
+		allocated_phys_addr = start;
+
+		/* add to imem_list, up sorted by phys_start */
+		imemn = kmalloc(sizeof(struct imem_list), GFP_KERNEL);
+		if (!imemn) {
+			return -ENOMEM;
+		}
+		imemn->phys_start = start;
+		imemn->phys_end = end;
+		imemn->next = NULL;
+
+		if (!imem_list_head)
+			imem_list_head = imemn;
+		else {
+			imem = imemp = imem_list_head;
+			while (imem) {
+				if (start < imem->phys_start) {
+					break;
+				}
+
+				imemp = imem;
+				imem = imem->next;
+			}
+
+			if (imem == imem_list_head) {
+				imem_list_head = imemn;
+				imemn->next = imem;
+			}
+			else {
+				imemn->next = imemp->next;
+				imemp->next = imemn;
+			}
+		}
+	}
+
+#ifdef DEBUG_IMEM
+	dump_imem_list();
+#endif
+	return 0;
+}
+
+static void imem_free(unsigned int phys_addr)
+{
+	struct imem_list *imem, *imemp;
+
+	imem = imemp = imem_list_head;
+	while (imem) {
+		if (phys_addr == imem->phys_start) {
+			if (imem == imem_list_head) {
+				imem_list_head = imem->next;
+			}
+			else {
+				imemp->next = imem->next;
+			}
+
+			kfree(imem);
+			break;
+		}
+
+		imemp = imem;
+		imem = imem->next;
+	}
+
+#ifdef DEBUG_IMEM
+	dump_imem_list();
+#endif
+}
+
+static void imem_free_all(void)
+{
+	struct imem_list *imem;
+
+	imem = imem_list_head;
+	while (imem) {
+		kfree(imem);
+		imem = imem->next;
+	}
+
+	imem_list_head = NULL;
+
+	allocated_phys_addr = 0;
+
+#ifdef DEBUG_IMEM
+	dump_imem_list();
+#endif
+}
+
+/*
+ * Return the allocated buffer address and the max order of free buffer
+ */
+static int imem_read_proc(char *page, char **start, off_t off,
+			  int count, int *eof, void *data)
+{
+	int len = 0;
+	unsigned int start_addr, end_addr, max_order, max_size;
+	struct imem_list *imem;
+
+	unsigned int *tmp = (unsigned int *)(page + len);
+
+	start_addr = jz_imem_base;
+	end_addr = start_addr + (1 << IMEM_MAX_ORDER) * PAGE_SIZE;
+
+	if (!imem_list_head)
+		max_size = end_addr - start_addr;
+	else {
+		max_size = 0;
+		imem = imem_list_head;
+		while (imem) {
+			if (max_size < (imem->phys_start - start_addr))
+				max_size = imem->phys_start - start_addr;
+
+			start_addr = imem->phys_end + 1;
+			imem = imem->next;
+		}
+
+		if (max_size < (end_addr - start_addr))
+			max_size = end_addr - start_addr;
+	}
+
+	if (max_size > 0) {
+		max_order = get_order(max_size);
+		if (((1 << max_order) * PAGE_SIZE) > max_size)
+		    max_order--;
+	}
+	else {
+		max_order = 0xffffffff;	/* No any free buffer */
+	}
+
+	*tmp++ = allocated_phys_addr;	/* address allocated by 'echo n > /proc/jz/imem' */
+	*tmp = max_order;		/* max order of current free buffers */
+
+	len += 2 * sizeof(unsigned int);
+
+	return len;
+}
+
+static int imem_write_proc(struct file *file, const char *buffer, unsigned long count, void *data)
+{
+	unsigned int val;
+
+	val = simple_strtoul(buffer, 0, 16);
+
+	if (val == 0xff) {
+		/* free all memory */
+		imem_free_all();
+	}
+	else if ((val >= 0) && (val <= IMEM_MAX_ORDER)) {
+		/* allocate 2^val pages */
+		imem_alloc(val);
+	}
+	else {			
+		/* free buffer which phys_addr is val */
+		imem_free(val);
+	}
+
+	return count;
+}
+#endif	/* #ifndef CONFIG_ANDROID_PMEM */
+
+static int fpu_write_proc(struct file *file, const char *buffer, unsigned long count, void *data)
+{
+	printk("user set rounding mode to %x \n",(unsigned int)buffer);
+
+	if ((unsigned int)buffer > 4) {
+		printk("roundind mode error!\n");
+	}
+
+	jz4770_fpu_init((unsigned int)buffer);
+	return count;
+}
+
+/*
+ * /proc/jz/xxx entry
+ *
+ */
+static int __init jz_proc_init(void)
+{
+	struct proc_dir_entry *res;
+#ifndef CONFIG_ANDROID_PMEM
+	unsigned int virt_addr, i;
+#endif
+
+	proc_jz_root = proc_mkdir("jz", 0);
+
+	/* External Memory Controller */
+	res = create_proc_entry("emc", 0644, proc_jz_root);
+	if (res) {
+		res->read_proc = emc_read_proc;
+		res->write_proc = NULL;
+		res->data = NULL;
+	}
+
+	/* Power Management Controller */
+	res = create_proc_entry("pmc", 0644, proc_jz_root);
+	if (res) {
+		res->read_proc = pmc_read_proc;
+		res->write_proc = pmc_write_proc;
+		res->data = NULL;
+	}
+
+	/* Clock Generation Module */
+	res = create_proc_entry("cgm", 0644, proc_jz_root);
+	if (res) {
+		res->read_proc = cgm_read_proc;
+		res->write_proc = cgm_write_proc;
+		res->data = NULL;
+	}
+
+	/* Image process unit */
+	res = create_proc_entry("ipu", 0644, proc_jz_root);
+	if (res) {
+		res->read_proc = ipu_read_proc;
+		res->write_proc = ipu_write_proc;
+		res->data = NULL;
+	}
+
+	/* udc hotplug */
+	res = create_proc_entry("udc", 0644, proc_jz_root);
+	if (res) {
+		res->read_proc = udc_read_proc;
+		res->write_proc = NULL;
+		res->data = NULL;
+	}
+
+	/* mmc hotplug */
+	res = create_proc_entry("mmc", 0644, proc_jz_root);
+	if (res) {
+		res->read_proc = mmc_read_proc;
+		res->write_proc = NULL;
+		res->data = NULL;
+	}
+
+#ifndef CONFIG_ANDROID_PMEM
+	/*
+	 * Reserve a 4MB memory for IPU on JZ4770.
+	 */
+	jz_imem_base = (unsigned int)__get_free_pages(GFP_KERNEL, IMEM_MAX_ORDER);
+	if (jz_imem_base) {
+		/* imem (IPU memory management) */
+		res = create_proc_entry("imem", 0644, proc_jz_root);
+		if (res) {
+			res->read_proc = imem_read_proc;
+			res->write_proc = imem_write_proc;
+			res->data = NULL;
+		}
+
+		/* Set page reserved */
+		virt_addr = jz_imem_base;
+		for (i = 0; i < (1 << IMEM_MAX_ORDER); i++) {
+			SetPageReserved(virt_to_page((void *)virt_addr));
+			virt_addr += PAGE_SIZE;
+		}
+
+		/* Convert to physical address */
+		jz_imem_base = virt_to_phys((void *)jz_imem_base);
+
+		printk("Total %dMB memory at 0x%x was reserved for IPU\n", 
+		       (unsigned int)((1 << IMEM_MAX_ORDER) * PAGE_SIZE)/1000000, jz_imem_base);
+	}
+#endif	/* #ifdef CONFIG_ANDROID_PMEM */
+
+	/* fpu */
+	res = create_proc_entry("fpu", 0644, proc_jz_root);
+	if (res) {
+		res->read_proc = NULL;
+		res->write_proc = fpu_write_proc;
+		res->data = NULL;
+	}
+
+	return 0;
+}
+
+__initcall(jz_proc_init);
diff --git a/arch/mips/jz4770/prom.c b/arch/mips/jz4770/prom.c
new file mode 100644
index 00000000000..f37afc1957f
--- /dev/null
+++ b/arch/mips/jz4770/prom.c
@@ -0,0 +1,198 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ *    PROM library initialisation code, supports YAMON and U-Boot.
+ *
+ * Copyright 2000, 2001, 2006 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc.
+ *         	ppopov@mvista.com or source@mvista.com
+ *
+ * This file was derived from Carsten Langgaard's
+ * arch/mips/mips-boards/xx files.
+ *
+ * Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/string.h>
+
+#include <asm/bootinfo.h>
+#include <asm/jzsoc.h>
+
+/* #define DEBUG_CMDLINE */
+
+int prom_argc;
+char **prom_argv, **prom_envp;
+
+char * prom_getcmdline(void)
+{
+	return &(arcs_cmdline[0]);
+}
+
+void  prom_init_cmdline(void)
+{
+	char *cp;
+	int actr;
+
+	actr = 1; /* Always ignore argv[0] */
+
+	cp = &(arcs_cmdline[0]);
+	while(actr < prom_argc) {
+	        strcpy(cp, prom_argv[actr]);
+		cp += strlen(prom_argv[actr]);
+		*cp++ = ' ';
+		actr++;
+	}
+	if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */
+		--cp;
+	if (prom_argc > 1)
+		*cp = '\0';
+
+}
+
+
+char *prom_getenv(char *envname)
+{
+#if 0
+	/*
+	 * Return a pointer to the given environment variable.
+	 * YAMON uses "name", "value" pairs, while U-Boot uses "name=value".
+	 */
+
+	char **env = prom_envp;
+	int i = strlen(envname);
+	int yamon = (*env && strchr(*env, '=') == NULL);
+
+	while (*env) {
+		if (yamon) {
+			if (strcmp(envname, *env++) == 0)
+				return *env;
+		} else {
+			if (strncmp(envname, *env, i) == 0 && (*env)[i] == '=')
+				return *env + i + 1;
+		}
+		env++;
+	}
+#endif
+	return NULL;
+}
+
+inline unsigned char str2hexnum(unsigned char c)
+{
+	if(c >= '0' && c <= '9')
+		return c - '0';
+	if(c >= 'a' && c <= 'f')
+		return c - 'a' + 10;
+	if(c >= 'A' && c <= 'F')
+		return c - 'A' + 10;
+	return 0; /* foo */
+}
+
+inline void str2eaddr(unsigned char *ea, unsigned char *str)
+{
+	int i;
+
+	for(i = 0; i < 6; i++) {
+		unsigned char num;
+
+		if((*str == '.') || (*str == ':'))
+			str++;
+		num = str2hexnum(*str++) << 4;
+		num |= (str2hexnum(*str++));
+		ea[i] = num;
+	}
+}
+
+int get_ethernet_addr(char *ethernet_addr)
+{
+        char *ethaddr_str;
+
+        ethaddr_str = prom_getenv("ethaddr");
+	if (!ethaddr_str) {
+	        printk("ethaddr not set in boot prom\n");
+		return -1;
+	}
+	str2eaddr(ethernet_addr, ethaddr_str);
+
+#if 0
+	{
+		int i;
+
+	printk("get_ethernet_addr: ");
+	for (i=0; i<5; i++)
+		printk("%02x:", (unsigned char)*(ethernet_addr+i));
+	printk("%02x\n", *(ethernet_addr+i));
+	}
+#endif
+
+	return 0;
+}
+
+void __init prom_free_prom_memory(void)
+{
+}
+
+void __init prom_init(void)
+{
+	unsigned char *memsize_str;
+	unsigned long memsize;
+
+	prom_argc = (int) fw_arg0;
+	prom_argv = (char **) fw_arg1;
+	prom_envp = (char **) fw_arg2;
+
+	mips_machtype = MACH_INGENIC_JZ4770;
+
+	prom_init_cmdline();
+	memsize_str = prom_getenv("memsize");
+	if (!memsize_str) {
+		memsize = 0x04000000;
+	} else {
+		memsize = simple_strtol(memsize_str, NULL, 0);
+	}
+	add_memory_region(0, memsize, BOOT_MEM_RAM);
+}
+
+/* used by early printk */
+void prom_putchar(char c)
+{
+	volatile u8 *uart_lsr = (volatile u8 *)(UART2_BASE + OFF_LSR);
+	volatile u8 *uart_tdr = (volatile u8 *)(UART2_BASE + OFF_TDR);
+
+	/* Wait for fifo to shift out some bytes */
+	while ( !((*uart_lsr & (UARTLSR_TDRQ | UARTLSR_TEMT)) == 0x60) );
+
+	*uart_tdr = (u8)c;
+}
+
+const char *get_system_type(void)
+{
+	return "JZ4770";
+}
+
+EXPORT_SYMBOL(prom_getcmdline);
+EXPORT_SYMBOL(get_ethernet_addr);
+EXPORT_SYMBOL(str2eaddr);
diff --git a/arch/mips/jz4770/reset.c b/arch/mips/jz4770/reset.c
new file mode 100644
index 00000000000..43e1898dee8
--- /dev/null
+++ b/arch/mips/jz4770/reset.c
@@ -0,0 +1,46 @@
+/*
+ * linux/arch/mips/jz4770/reset.c
+ *
+ * JZ4770 reset routines.
+ *
+ * Copyright (c) 2006-2007  Ingenic Semiconductor Inc.
+ * Author: <yliu@ingenic.cn>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <asm/io.h>
+#include <asm/pgtable.h>
+#include <asm/processor.h>
+#include <asm/reboot.h>
+#include <asm/system.h>
+#include <asm/jzsoc.h>
+
+void jz_restart(char *command)
+{
+	printk("Restarting after 4 ms\n");
+	REG_WDT_TCSR = WDT_TCSR_PRESCALE4 | WDT_TCSR_EXT_EN;
+	REG_WDT_TCNT = 0;
+	REG_WDT_TDR = JZ_EXTAL/1000;   /* reset after 4ms */
+	REG_TCU_TSCR = TCU_TSCR_WDTSC; /* enable wdt clock */
+	REG_WDT_TCER = WDT_TCER_TCEN;  /* wdt start */
+	while (1);
+}
+
+void jz_halt(void)
+{
+	printk(KERN_NOTICE "\n** You can safely turn off the power\n");
+
+	while (1)
+		__asm__(".set\tmips3\n\t"
+	                "wait\n\t"
+			".set\tmips0");
+}
+
+void jz_power_off(void)
+{
+	jz_halt();
+}
diff --git a/arch/mips/jz4770/setup.c b/arch/mips/jz4770/setup.c
new file mode 100644
index 00000000000..e3b7d3e0fc2
--- /dev/null
+++ b/arch/mips/jz4770/setup.c
@@ -0,0 +1,320 @@
+/*
+ * linux/arch/mips/jz4770/common/setup.c
+ * 
+ * JZ4770 common setup routines.
+ * 
+ * Copyright (C) 2006 Ingenic Semiconductor Inc.
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ */
+#include <linux/init.h>
+#include <linux/string.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/ioport.h>
+#include <linux/tty.h>
+#include <linux/serial.h>
+#include <linux/serial_core.h>
+#include <linux/serial_8250.h>
+
+#include <asm/cpu.h>
+#include <asm/bootinfo.h>
+#include <asm/irq.h>
+#include <asm/mipsregs.h>
+#include <asm/reboot.h>
+#include <asm/pgtable.h>
+#include <asm/time.h>
+#include <asm/jzsoc.h>
+
+#ifdef CONFIG_PC_KEYB
+#include <asm/keyboard.h>
+#endif
+
+jz_clocks_t jz_clocks;
+
+extern char * __init prom_getcmdline(void);
+extern void __init jz_board_setup(void);
+extern void jz_restart(char *);
+extern void jz_halt(void);
+extern void jz_power_off(void);
+extern void jz_time_init(void);
+
+#if 1
+static void serial_putc (const char c)
+{
+	volatile u8 *uart_lsr = (volatile u8 *)(UART2_BASE + OFF_LSR);
+	volatile u8 *uart_tdr = (volatile u8 *)(UART2_BASE + OFF_TDR);
+
+	if (c == '\n') serial_putc ('\r');
+
+	/* Wait for fifo to shift out some bytes */
+	while ( !((*uart_lsr & (UART_LSR_TDRQ | UART_LSR_TEMT)) == 0x60) );
+
+	*uart_tdr = (u8)c;
+}
+
+static void serial_puts (const char *s)
+{
+	while (*s) {
+		serial_putc (*s++);
+	}
+}
+#endif
+
+static void __init sysclocks_setup(void)
+{
+#ifndef CONFIG_MIPS_JZ_EMURUS /* FPGA */
+	jz_clocks.cclk = __cpm_get_cclk();
+	jz_clocks.hclk = __cpm_get_h0clk();
+	jz_clocks.pclk = __cpm_get_pclk();
+	jz_clocks.mclk = __cpm_get_mclk();
+	jz_clocks.h1clk = __cpm_get_h1clk();
+	jz_clocks.pixclk = __cpm_get_pixclk();
+	jz_clocks.i2sclk = __cpm_get_i2sclk();
+	jz_clocks.otgclk = __cpm_get_otgclk();
+	jz_clocks.mscclk = __cpm_get_mscclk(0);
+	jz_clocks.extalclk = __cpm_get_extalclk();
+	jz_clocks.rtcclk = __cpm_get_rtcclk();
+#else
+
+#define FPGACLK 8000000
+
+	jz_clocks.cclk = FPGACLK;
+	jz_clocks.hclk = FPGACLK;
+	jz_clocks.pclk = FPGACLK;
+	jz_clocks.mclk = FPGACLK;
+	jz_clocks.h1clk = FPGACLK;
+	jz_clocks.pixclk = FPGACLK;
+	jz_clocks.i2sclk = FPGACLK;
+	jz_clocks.usbclk = FPGACLK;
+	jz_clocks.mscclk = FPGACLK;
+	jz_clocks.extalclk = FPGACLK;
+	jz_clocks.rtcclk = FPGACLK;
+#endif
+
+	printk("CPU clock: %dMHz, System clock: %dMHz, Peripheral clock: %dMHz, Memory clock: %dMHz\n",
+	       (jz_clocks.cclk + 500000) / 1000000,
+	       (jz_clocks.hclk + 500000) / 1000000,
+	       (jz_clocks.pclk + 500000) / 1000000,
+	       (jz_clocks.mclk + 500000) / 1000000);
+}
+
+static void __init soc_cpm_setup(void)
+{
+	/* Start all module clocks
+	 */
+	__cpm_start_all();
+
+	/* Enable CKO to external memory */
+	__cpm_enable_cko();
+
+	/* CPU enters IDLE mode when executing 'wait' instruction */
+	__cpm_idle_mode();
+
+	/* Setup system clocks */
+	sysclocks_setup();
+}
+
+static void __init soc_harb_setup(void)
+{
+//	__harb_set_priority(0x00);  /* CIM>LCD>DMA>ETH>PCI>USB>CBB */
+//	__harb_set_priority(0x03);  /* LCD>CIM>DMA>ETH>PCI>USB>CBB */
+//	__harb_set_priority(0x0a);  /* ETH>LCD>CIM>DMA>PCI>USB>CBB */
+}
+
+static void __init soc_emc_setup(void)
+{
+	__cpm_start_emc();
+	int haili = 10000;
+	while(haili --);
+
+//	REG_EMC_PMEMBS1  = 0;
+//	REG_EMC_PMEMBS0  = 0;
+
+	REG_EMC_PMEMBS1 = 0xff000000;
+	REG_EMC_PMEMBS0 = 0xff000000;
+}
+
+static void __init soc_dmac_setup(void)
+{
+	__dmac_enable_module(0);
+	__dmac_enable_module(1);
+}
+
+static void __init jz_soc_setup(void)
+{
+//	soc_cpm_setup();
+//	soc_harb_setup();
+//	soc_emc_setup();
+	soc_dmac_setup();
+}
+
+static void __init jz_serial_setup(void)
+{
+#ifdef CONFIG_SERIAL_8250
+	struct uart_port s;
+
+	REG8(UART0_FCR) |= UARTFCR_UUE; /* enable UART module */
+	memset(&s, 0, sizeof(s));
+	s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
+	s.iotype = SERIAL_IO_MEM;
+	s.regshift = 2;
+	s.uartclk = 12000000;
+//	s.uartclk = jz_clocks.extalclk ;
+
+	s.line = 0;
+	s.membase = (u8 *)UART0_BASE;
+	s.irq = IRQ_UART0;
+	if (early_serial_setup(&s) != 0) {
+		printk(KERN_ERR "Serial ttyS0 setup failed!\n");
+	}
+
+	s.line = 1;
+	s.membase = (u8 *)UART1_BASE;
+	s.irq = IRQ_UART1;
+	if (early_serial_setup(&s) != 0) {
+		printk(KERN_ERR "Serial ttyS1 setup failed!\n");
+	}
+	s.line = 2;
+	s.membase = (u8 *)UART2_BASE;
+	s.irq = IRQ_UART2;
+
+	if (early_serial_setup(&s) != 0) {
+		printk(KERN_ERR "Serial ttyS2 setup failed!\n");
+	}
+
+	s.line = 3;
+	s.membase = (u8 *)UART3_BASE;
+	s.irq = IRQ_UART3;
+	if (early_serial_setup(&s) != 0) {
+		printk(KERN_ERR "Serial ttyS3 setup failed!\n");
+	}
+#endif
+}
+
+void __init jz_test_setup(void)
+{
+	int volatile x = 1000;
+	int i;
+
+	printk(":111%s:%d\n",__FUNCTION__,__LINE__);
+
+	printk("kernel test cs1");
+#if 1
+//	for (i = 0; i < 1000; i++) { 
+	while(1) {
+		__gpio_as_output0(21);
+
+		x = 10000;
+		while(x--)
+			;
+		__gpio_as_output1(21);
+	}
+#endif
+	printk("kernel test cs1 ok");
+
+#if 0
+
+	REG_CPM_CPCCR |= CPM_CPCCR_CE; 
+	REG_CPM_LPCDR = 7;
+	REG_CPM_UHCCDR = 7;
+	REG_CPM_GPSCDR = 2;
+	REG_CPM_GPUCDR = 1;
+
+
+	REG_CPM_PSWC0ST = 0;
+	REG_CPM_PSWC1ST = 8;
+	REG_CPM_PSWC2ST = 10;
+	REG_CPM_PSWC3ST = 0;
+
+	REG_CPM_OPCR &= ~CPM_OPCR_UHCPHY_DISABLE;
+	REG_CPM_OPCR |= CPM_OPCR_UDCPHY_ENABLE;
+#endif
+
+#if 0
+	/*stop some clk*/
+	__cpm_stop_ipu();
+	__cpm_stop_lcd();
+	__cpm_stop_tve();
+	__cpm_stop_Cim();
+	__cpm_stop_mdma();
+	__cpm_stop_uhc();
+	__cpm_stop_gps();
+	__cpm_stop_ssi2();
+	__cpm_stop_ssi1();
+
+	__cpm_stop_uart3();
+	__cpm_stop_uart2();
+	__cpm_stop_uart0();
+
+	__cpm_stop_sadc();
+	REG_CPM_CLKGR0 |= (0xfff < 2);
+	REG_CPM_CLKGR1 = 0xffffffff;
+	__cpm_stop_bch();
+	__cpm_stop_dmac();
+	printk("some clk have been stop!\n");
+
+#endif
+#if 0
+	__cpm_start_emc();
+	printk("\n-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=\nREG_CPM_CLKGR0=0x%x\n",REG_CPM_CLKGR0);
+	int haili = 10000;
+	while(haili --);
+	printk("===================\n");
+	REG_EMC_PMEMBS1  = 0;
+	REG_EMC_PMEMBS0  = 0;
+
+	REG_EMC_PMEMBS1 |= (0xff << 24);
+	REG_EMC_PMEMBS0 |= (0xff << 24);
+	REG_EMC_PMEMBS0 |= (0xff << 8);
+
+	printk("---------------PMEMBS1=0x%x,PMEMBS0=0x%x\n",REG_EMC_PMEMBS1,REG_EMC_PMEMBS0);
+#endif
+}
+
+void __init plat_mem_setup(void)
+{
+	char *argptr;
+
+	argptr = prom_getcmdline();
+
+	__asm__ (
+		"li    $2, 0xa9000000 \n\t"
+		"mtc0  $2, $5, 4      \n\t"
+		"nop                  \n\t"
+		::"r"(2));
+
+	/* IO/MEM resources. Which will be the addtion value in `inX' and
+	 * `outX' macros defined in asm/io.h */
+	set_io_port_base(0);
+	ioport_resource.start	= 0x00000000;
+	ioport_resource.end	= 0xffffffff;
+	iomem_resource.start	= 0x00000000;
+	iomem_resource.end	= 0xffffffff;
+
+	_machine_restart = jz_restart;
+	_machine_halt = jz_halt;
+	pm_power_off = jz_power_off;
+
+	jz_soc_setup();
+	jz_serial_setup();
+	jz_board_setup();
+
+#ifdef CONFIG_PM
+        jz_pm_init();
+#endif
+}
+
diff --git a/arch/mips/jz4770/sleep.S b/arch/mips/jz4770/sleep.S
new file mode 100644
index 00000000000..11c30446f1a
--- /dev/null
+++ b/arch/mips/jz4770/sleep.S
@@ -0,0 +1,311 @@
+/*
+ * linux/arch/mips/jz4770/sleep.S
+ *
+ * jz4770 Assembler Sleep/WakeUp Management Routines
+ *
+ * Copyright (C) 2005 Ingenic Semiconductor
+ * Author: <jlwei@ingenic.cn>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#define __MIPS_ASSEMBLER
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+#include <asm/mach-jz4770/jz4770cpm.h>
+#inclede <asm/mach-jz4770/jz4770emc.h>
+	.text
+	.set	noreorder
+	.set	noat
+
+	.extern jz_flush_cache_all
+
+/*
+ * jz_cpu_sleep()
+ *
+ * Forces CPU into sleep mode,and we will power down p0 in this mode!
+ */
+
+	.globl	jz_cpu_sleep
+jz_cpu_sleep:
+
+	/* save hi, lo and general registers except k0($26) and k1($27) (total 32) */
+	move	k0, sp
+	addiu	k0, k0, -(32*4)
+	mfhi	k1
+	sw	$0,  0(k0)
+	sw	$1,  4(k0)
+	sw	k1,  120(k0)		/* hi */
+	mflo	k1
+	sw	$2,  8(k0)
+	sw	$3,  12(k0)
+	sw	k1,  124(k0)		/* lo */
+	sw	$4,  16(k0)
+	sw	$5,  20(k0)
+	sw	$6,  24(k0)
+	sw	$7,  28(k0)
+	sw	$8,  32(k0)
+	sw	$9,  36(k0)
+	sw	$10, 40(k0)
+	sw	$11, 44(k0)
+	sw	$12, 48(k0)
+	sw	$13, 52(k0)
+	sw	$14, 56(k0)
+	sw	$15, 60(k0)
+	sw	$16, 64(k0)
+	sw	$17, 68(k0)
+	sw	$18, 72(k0)
+	sw	$19, 76(k0)
+	sw	$20, 80(k0)
+	sw	$21, 84(k0)
+	sw	$22, 88(k0)
+	sw	$23, 92(k0)
+	sw	$24, 96(k0)
+	sw	$25, 100(k0)
+	sw	$28, 104(k0)
+	sw	$29, 108(k0)		/* saved sp */
+	sw	$30, 112(k0)
+	sw	$31, 116(k0)		/* saved ra */
+	move	sp, k0
+
+	/* save CP0 registers and sp (total 26) */
+	move	k0, sp
+	addiu	k0, k0, -(26*4)
+
+	mfc0	$1, CP0_INDEX
+	mfc0	$2, CP0_RANDOM
+	mfc0	$3, CP0_ENTRYLO0
+	mfc0	$4, CP0_ENTRYLO1
+	mfc0	$5, CP0_CONTEXT
+	mfc0	$6, CP0_PAGEMASK
+	mfc0	$7, CP0_WIRED
+	mfc0	$8, CP0_BADVADDR
+	mfc0	$9, CP0_ENTRYHI
+	mfc0	$10, CP0_STATUS
+/*	mfc0	$11, $12, 1*/		/* IntCtl */
+	mfc0	$12, CP0_CAUSE
+	mfc0	$13, CP0_EPC
+/*	mfc0	$14, $15, 1*/		/* EBase */
+	mfc0	$15, CP0_CONFIG
+/*	mfc0	$16, CP0_CONFIG, 7*/	/* Config 7 */
+	mfc0	$17, CP0_LLADDR
+	mfc0	$18, CP0_WATCHLO
+	mfc0	$19, CP0_WATCHHI
+	mfc0	$20, CP0_DEBUG
+	mfc0	$21, CP0_DEPC
+	mfc0	$22, CP0_ECC
+	mfc0	$23, CP0_TAGLO
+	mfc0	$24, CP0_ERROREPC
+	mfc0	$25, CP0_DESAVE
+
+	sw	$1,  0(k0)
+	sw	$2,  4(k0)
+	sw	$3,  8(k0)
+	sw	$4,  12(k0)
+	sw	$5,  16(k0)
+	sw	$6,  20(k0)
+	sw	$7,  24(k0)
+	sw	$8,  28(k0)
+	sw	$9,  32(k0)
+	sw	$10, 36(k0)
+	sw	$11, 40(k0)
+	sw	$12, 44(k0)
+	sw	$13, 48(k0)
+	sw	$14, 52(k0)
+	sw	$15, 56(k0)
+	sw	$16, 60(k0)
+	sw	$17, 64(k0)
+	sw	$18, 68(k0)
+	sw	$19, 72(k0)
+	sw	$20, 76(k0)
+	sw	$21, 80(k0)
+	sw	$22, 84(k0)
+	sw	$23, 88(k0)
+	sw	$24, 92(k0)
+	sw	$25, 96(k0)
+	sw	$29, 100(k0)	/* saved sp */
+	move	sp, k0
+
+	/* preserve virtual address of stack */
+	la	k0, sleep_save_sp
+	sw	sp, 0(k0)
+
+	/* flush caches and write buffers */
+	jal	jz_flush_cache_all
+	nop
+#if 0
+	/* set new sdram refresh constant */
+	li	t0, 1
+	la	t1, EMC_RTCOR
+	sh	t0, 0(t1)
+
+
+
+	/* disable PLL */
+	la	t0, CPM_PLCR1
+	sw	$0, 0(t0)
+#endif
+	/* put CPU to sleep mode */
+	la	t0, CPM_LCR
+	lw	t1, 0(t0)
+	li	t2, ~CPM_LCR_LPM_MASK
+	and	t1, t2
+	ori	t1, CPM_LCR_LPM_SLEEP
+
+	.align	5
+	/* align execution to a cache line */
+	j	1f
+
+	.align	5
+1:
+	/* all needed values are now in registers.
+	 * These last instructions should be in cache
+	 */
+	nop
+	nop
+
+	/* set sleep mode */
+	sw	t1, 0(t0)
+	nop
+
+	/* enter sleep mode */
+	.set	mips3
+	wait
+	nop
+	.set	mips0
+
+2:	j	2b		/* loop waiting for suspended */
+	nop
+
+/*
+ * jz_cpu_resume()
+ *
+ * entry point from bootloader into kernel during resume
+ */
+
+	.align 5
+	.globl	jz_cpu_resume
+jz_cpu_resume:
+#if 0   /*60 no have */
+
+	/* clear SCR.HGP */
+	la	t0, CPM_SCR
+	lw	t1, 0(t0)
+	li	t2, ~CPM_SCR_HGP
+	and	t1, t2
+	sw	t1, 0(t0)
+#endif
+	/* restore LCR.LPM to IDLE mode */
+	la	t0, CPM_LCR
+	lw	t1, 0(t0)
+	li	t2, ~CPM_LCR_LPM_MASK
+	and	t1, t2
+	ori	t1, CPM_LCR_LPM_IDLE
+	sw	t1, 0(t0)
+
+	/* restore saved sp */
+	la	t0, sleep_save_sp
+	lw	sp, 0(t0)
+
+	/* restore CP0 registers */
+	move	k0, sp
+	lw	$1,  0(k0)
+	lw	$2,  4(k0)
+	lw	$3,  8(k0)
+	lw	$4,  12(k0)
+	lw	$5,  16(k0)
+	lw	$6,  20(k0)
+	lw	$7,  24(k0)
+	lw	$8,  28(k0)
+	lw	$9,  32(k0)
+	lw	$10, 36(k0)
+	lw	$11, 40(k0)
+	lw	$12, 44(k0)
+	lw	$13, 48(k0)
+	lw	$14, 52(k0)
+	lw	$15, 56(k0)
+	lw	$16, 60(k0)
+	lw	$17, 64(k0)
+	lw	$18, 68(k0)
+	lw	$19, 72(k0)
+	lw	$20, 76(k0)
+	lw	$21, 80(k0)
+	lw	$22, 84(k0)
+	lw	$23, 88(k0)
+	lw	$24, 92(k0)
+	lw	$25, 96(k0)
+	lw	$29, 100(k0)	/* saved sp */
+
+	mtc0	$1, CP0_INDEX
+	mtc0	$2, CP0_RANDOM
+	mtc0	$3, CP0_ENTRYLO0
+	mtc0	$4, CP0_ENTRYLO1
+	mtc0	$5, CP0_CONTEXT
+	mtc0	$6, CP0_PAGEMASK
+	mtc0	$7, CP0_WIRED
+	mtc0	$8, CP0_BADVADDR
+	mtc0	$9, CP0_ENTRYHI
+	mtc0	$10, CP0_STATUS
+/*	mtc0	$11, $12, 1*/		/* IntCtl */
+	mtc0	$12, CP0_CAUSE
+	mtc0	$13, CP0_EPC
+/*	mtc0	$14, $15, 1*/		/* EBase */
+	mtc0	$15, CP0_CONFIG
+/*	mtc0	$16, CP0_CONFIG, 7*/	/* Config 7 */
+	mtc0	$17, CP0_LLADDR
+	mtc0	$18, CP0_WATCHLO
+	mtc0	$19, CP0_WATCHHI
+	mtc0	$20, CP0_DEBUG
+	mtc0	$21, CP0_DEPC
+	mtc0	$22, CP0_ECC
+	mtc0	$23, CP0_TAGLO
+	mtc0	$24, CP0_ERROREPC
+	mtc0	$25, CP0_DESAVE
+
+	/* restore general registers */
+	move	k0, sp
+	lw	k1,  120(k0)		/* hi */
+	lw	$0,  0(k0)
+	lw	$1,  4(k0)
+	mthi	k1
+	lw	k1,  124(k0)		/* lo */
+	lw	$2,  8(k0)
+	lw	$3,  12(k0)
+	mtlo	k1
+	lw	$4,  16(k0)
+	lw	$5,  20(k0)
+	lw	$6,  24(k0)
+	lw	$7,  28(k0)
+	lw	$8,  32(k0)
+	lw	$9,  36(k0)
+	lw	$10, 40(k0)
+	lw	$11, 44(k0)
+	lw	$12, 48(k0)
+	lw	$13, 52(k0)
+	lw	$14, 56(k0)
+	lw	$15, 60(k0)
+	lw	$16, 64(k0)
+	lw	$17, 68(k0)
+	lw	$18, 72(k0)
+	lw	$19, 76(k0)
+	lw	$20, 80(k0)
+	lw	$21, 84(k0)
+	lw	$22, 88(k0)
+	lw	$23, 92(k0)
+	lw	$24, 96(k0)
+	lw	$25, 100(k0)
+	lw	$28, 104(k0)
+	lw	$29, 108(k0)		/* saved sp */
+	lw	$30, 112(k0)
+	lw	$31, 116(k0)		/* saved ra */
+
+	/* return to caller */
+	jr	ra
+	nop
+
+sleep_save_sp:
+	.word	0			/* preserve sp here */
+
+	.set	reorder
diff --git a/arch/mips/jz4770/time.c b/arch/mips/jz4770/time.c
new file mode 100644
index 00000000000..0f1a466837f
--- /dev/null
+++ b/arch/mips/jz4770/time.c
@@ -0,0 +1,195 @@
+/*
+ * linux/arch/mips/jz4760/time.c
+ *
+ * Setting up the clock on the JZ4760 boards.
+ *
+ * Copyright (C) 2008 Ingenic Semiconductor Inc.
+ * Author: <jlwei@ingenic.cn>
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ */
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/time.h>
+#include <linux/clockchips.h>
+
+#include <asm/time.h>
+#include <asm/jzsoc.h>
+
+/* This is for machines which generate the exact clock. */
+
+
+#define JZ_TIMER_TCU_CH  5
+#define JZ_TIMER_IRQ  IRQ_TCU1
+
+#define JZ_TIMER_CLOCK (JZ_EXTAL>>4) /* Jz timer clock frequency */
+
+static struct clocksource clocksource_jz; /* Jz clock source */
+static struct clock_event_device jz_clockevent_device; /* Jz clock event */
+
+void (*jz_timer_callback)(void);
+
+static irqreturn_t jz_timer_interrupt(int irq, void *dev_id)
+{
+	struct clock_event_device *cd = dev_id;
+
+	__tcu_clear_full_match_flag(JZ_TIMER_TCU_CH);
+
+	if (jz_timer_callback)
+		jz_timer_callback();
+
+	cd->event_handler(cd);
+
+	return IRQ_HANDLED;
+}
+
+static struct irqaction jz_irqaction = {
+	.handler	= jz_timer_interrupt,
+	.flags		= IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER,
+	.name		= "jz-timerirq",
+};
+
+union clycle_type
+{
+	cycle_t cycle64;
+	unsigned int cycle32[2];
+};
+
+
+cycle_t jz_get_cycles(void)
+{
+	/* convert jiffes to jz timer cycles */
+	unsigned long cpuflags;
+	union clycle_type old_cycle;
+
+	local_irq_save(cpuflags);
+	old_cycle.cycle32[0] = REG_OST_OSTCNTL;
+	old_cycle.cycle32[1] = REG_OST_OSTCNTH_BUF;
+	local_irq_restore(cpuflags);
+
+	return (old_cycle.cycle64);
+}
+
+static struct clocksource clocksource_jz = {
+	.name 		= "jz_clocksource",
+	.rating		= 300,
+	.read		= jz_get_cycles,
+	.mask		= 0xFFFFFFFF,
+	.shift 		= 10,
+	.flags		= CLOCK_SOURCE_WATCHDOG,
+};
+
+static int __init jz_clocksource_init(void)
+{
+	unsigned int latch;
+
+	/* Init timer */
+	latch = (JZ_TIMER_CLOCK + (HZ>>1)) / HZ;
+
+	clocksource_jz.mult = clocksource_hz2mult(JZ_TIMER_CLOCK, clocksource_jz.shift);
+	clocksource_register(&clocksource_jz);
+
+	//---------------------init sys clock -----------------
+	REG_OST_OSTCSR = OSTCSR_PRESCALE16 | OSTCSR_EXT_EN;
+	REG_OST_OSTDR = 0xffffffff;
+
+	REG_OST_OSTCNTL = 0;
+	REG_OST_OSTCNTH = 0;
+
+	REG_TCU_TMCR = TCU_TMCR_OSTMCL; /* unmask match irq */
+	REG_TCU_TSCR = TCU_TSCR_OSTSC;  /* enable timer clock */
+	REG_TCU_TESR = TCU_TESR_OSTST;  /* start counting up */
+
+	//---------------------endif init sys clock -----------------
+
+	return 0;
+}
+
+static int jz_set_next_event(unsigned long evt,
+				  struct clock_event_device *unused)
+{
+	return 0;
+}
+
+static void jz_set_mode(enum clock_event_mode mode,
+			struct clock_event_device *evt)
+{
+	switch (mode) {
+	case CLOCK_EVT_MODE_PERIODIC:
+                break;
+        case CLOCK_EVT_MODE_ONESHOT:
+        case CLOCK_EVT_MODE_UNUSED:
+        case CLOCK_EVT_MODE_SHUTDOWN:
+                break;
+        case CLOCK_EVT_MODE_RESUME:
+                break;
+        }
+}
+
+static struct clock_event_device jz_clockevent_device = {
+	.name		= "jz-clockenvent",
+	.features	= CLOCK_EVT_FEAT_PERIODIC,
+//	.features	= CLOCK_EVT_FEAT_ONESHOT, /* Jz4740 not support dynamic clock now */
+
+	/* .mult, .shift, .max_delta_ns and .min_delta_ns left uninitialized */
+	.mult		= 1,
+	.rating		= 300,
+	.irq		= JZ_TIMER_IRQ,
+	.set_mode	= jz_set_mode,
+	.set_next_event	= jz_set_next_event,
+};
+
+static void __init jz_clockevent_init(void)
+{
+	struct clock_event_device *cd = &jz_clockevent_device;
+	unsigned int cpu = smp_processor_id();
+
+	cd->cpumask = cpumask_of(cpu);
+	clockevents_register_device(cd);
+}
+
+static void __init jz_timer_setup(void)
+{
+  	unsigned int latch;
+
+	jz_clocksource_init();	/* init jz clock source */
+	jz_clockevent_init();	/* init jz clock event */
+
+	//---------------------init sys tick -----------------
+	/* Init timer */
+	__tcu_stop_counter(JZ_TIMER_TCU_CH);
+//	__cpm_start_tcu();
+	latch = (JZ_TIMER_CLOCK + (HZ>>1)) / HZ;
+
+	REG_TCU_TMSR = ((1 << JZ_TIMER_TCU_CH) | (1 << (JZ_TIMER_TCU_CH + 16)));
+
+	REG_TCU_TCSR(JZ_TIMER_TCU_CH) = OSTCSR_PRESCALE16 | OSTCSR_EXT_EN;
+	REG_TCU_TDFR(JZ_TIMER_TCU_CH) = latch - 1;
+	REG_TCU_TDHR(JZ_TIMER_TCU_CH) = latch + 1;
+	REG_TCU_TCNT(JZ_TIMER_TCU_CH) = 0;
+	/*
+	 * Make irqs happen for the system timer
+	 */
+	jz_irqaction.dev_id = &jz_clockevent_device;
+	setup_irq(JZ_TIMER_IRQ, &jz_irqaction);
+	__tcu_clear_full_match_flag(JZ_TIMER_TCU_CH);
+	__tcu_unmask_full_match_irq(JZ_TIMER_TCU_CH);
+	__tcu_start_counter(JZ_TIMER_TCU_CH);}
+
+
+void __init plat_time_init(void)
+{
+	jz_timer_setup();
+}
diff --git a/arch/mips/jz4810/Makefile b/arch/mips/jz4810/Makefile
index e189f5d52e4..19c3c2aef95 100644
--- a/arch/mips/jz4810/Makefile
+++ b/arch/mips/jz4810/Makefile
@@ -5,7 +5,7 @@
 # Object file lists.
 
 obj-y += prom.o irq.o time.o reset.o setup.o dma.o \
-	platform.o #i2c.o
+	platform.o cpm_fake.o #i2c.o
 
 obj-$(CONFIG_PROC_FS)		+= proc.o
 
diff --git a/arch/mips/jz4810/board-f4810.c b/arch/mips/jz4810/board-f4810.c
index 676cde06021..0e563e7482f 100644
--- a/arch/mips/jz4810/board-f4810.c
+++ b/arch/mips/jz4810/board-f4810.c
@@ -65,6 +65,24 @@ static void __init board_gpio_setup(void)
 	 */
 }
 
+static struct i2c_board_info falcon_i2c0_devs[] __initdata = {
+        {
+                I2C_BOARD_INFO("cm3511", 0x30),
+        },
+        {
+                I2C_BOARD_INFO("ov3640", 0x3c),
+        },
+        {
+                I2C_BOARD_INFO("ov7690", 0x21),
+        },
+        {
+        },
+};
+
+void __init board_i2c_init(void) {
+        i2c_register_board_info(0, falcon_i2c0_devs, ARRAY_SIZE(falcon_i2c0_devs));
+}
+
 void __init jz_board_setup(void)
 {
 
diff --git a/arch/mips/jz4810/cpm_fake.c b/arch/mips/jz4810/cpm_fake.c
new file mode 100644
index 00000000000..ac18c1d8ae3
--- /dev/null
+++ b/arch/mips/jz4810/cpm_fake.c
@@ -0,0 +1,127 @@
+/*
+ * linux/arch/mips/jz4760/cpm_fake.c
+ *
+ * jz4760 on-chip modules.
+ *
+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.
+ *
+ * Author: <whxu@ingenic.cn>
+ */
+
+#include <asm/jzsoc.h>
+
+
+#ifndef JZ_EXTAL
+#define JZ_EXTAL        (12 * 1000000)  /* 12MHz */
+#endif
+
+
+/*
+ * Get the external clock
+ */
+static unsigned int get_external_clock(void)
+{
+        return JZ_EXTAL;
+}
+
+/*
+ * Get the PLL clock
+ */
+unsigned int cpm_get_pllout(void)
+{
+        return get_external_clock() * CFG_DIV;
+}
+
+/*
+ * Get the PLL2 clock
+ */
+unsigned int cpm_get_pllout1(void)
+{
+        return get_external_clock();
+}
+
+/*
+ * Start the module clock
+ */
+void cpm_start_clock(clock_gate_module module_name)
+{
+
+}
+
+/*
+ * Stop the module clock
+ */
+void cpm_stop_clock(clock_gate_module module_name)
+{
+
+}
+
+/*
+ * Get the clock, assigned by the clock_name, and the return value unit is Hz
+ */
+unsigned int cpm_get_clock(cgu_clock clock_name)
+{
+        unsigned int clock_hz;
+
+        switch (clock_name) {
+        case CGU_CCLK:
+                clock_hz = cpm_get_pllout();
+
+                break;
+
+        case CGU_HCLK:
+                clock_hz = get_external_clock();
+
+                break;
+
+        case CGU_PCLK:
+                clock_hz = get_external_clock() / CFG_DIV;
+
+                break;
+
+        case CGU_MCLK:
+                clock_hz = get_external_clock() / CFG_DIV;
+
+                break;
+
+        case CGU_H2CLK:
+                clock_hz = get_external_clock();
+
+                break;
+
+        case CGU_SCLK:
+        case CGU_MSCCLK:
+        case CGU_SSICLK:
+        case CGU_CIMCLK:
+        case CGU_LPCLK:
+	case CGU_TVECLK:
+        case CGU_I2SCLK:
+        case CGU_PCMCLK:
+        case CGU_OTGCLK:
+        case CGU_UHCCLK:
+        case CGU_GPSCLK:
+        case CGU_GPUCLK:
+        case CGU_UARTCLK:
+        case CGU_SADCCLK:
+        case CGU_TCUCLK:
+                clock_hz = get_external_clock() / CFG_DIV;
+
+                break;
+
+        default:
+                printk("WARNING: can NOT get clock %d!\n", clock_name);
+                clock_hz = get_external_clock();
+                break;
+        }
+
+        return clock_hz;
+}
+
+/*
+ * Set the clock, assigned by the clock_name, and the return value unit is Hz,
+ * which means the actual clock
+ */
+unsigned int cpm_set_clock(cgu_clock clock_name, unsigned int clock_hz)
+{
+        return 0;
+}
diff --git a/arch/mips/jz4810/dma.c b/arch/mips/jz4810/dma.c
index d6e4dd281b2..36211df119a 100644
--- a/arch/mips/jz4810/dma.c
+++ b/arch/mips/jz4810/dma.c
@@ -1,9 +1,9 @@
 /*
- * linux/arch/mips/jz4810/dma.c
+ * linux/arch/mips/jz4760/dma.c
  *
- * Support functions for the JZ4810 internal DMA channels.
+ * Support functions for the JZ4760 internal DMA channels.
  * No-descriptor transfer only.
- * Descriptor transfer should also call jz_request_dma() to get a free 
+ * Descriptor transfer should also call jz_request_dma() to get a free
  * channel and call jz_free_dma() to free the channel. And driver should
  * build the DMA descriptor and setup the DMA channel by itself.
  *
@@ -47,14 +47,20 @@
  */
 
 struct jz_dma_chan jz_dma_table[MAX_DMA_NUM] = {
-	{dev_id:DMA_ID_BCH_ENC,}, /* DMAC0 channel 0, reserved for BCH */
-	{dev_id:-1,},		/* DMAC0 channel 1 */
-	{dev_id:-1,},		/* DMAC0 channel 2 */
-	{dev_id:-1,},		/* DMAC0 channel 3 */
-	{dev_id:-1,},		/* DMAC1 channel 0 */
-	{dev_id:-1,},		/* DMAC1 channel 1 */
-	{dev_id:-1,},		/* DMAC1 channel 2 */
-	{dev_id:-1,},		/* DMAC1 channel 3 */
+	{ dev_id: DMA_ID_MSC0, },	/* DMAC0 channel 0, reserved for MSC0 */
+	{ dev_id: -1, },		/* DMAC0 channel 1 */
+	{ dev_id: -1, },		/* DMAC0 channel 2 */
+	{ dev_id: -1, },		/* DMAC0 channel 3 */
+	{ dev_id: -1, },		/* DMAC0 channel 4 */
+	{ dev_id: -1, },			/* DMAC0 channel 5 --- unavailable */
+
+	/* To avoid bug, reserved channel 6 & 7 for AIC_TX & AIC_RX */
+	{ dev_id: DMA_ID_AIC_TX, },	/* DMAC1 channel 0 */
+	{ dev_id: DMA_ID_AIC_RX, },	/* DMAC1 channel 1 */
+	{ dev_id: DMA_ID_MSC1, },	/* DMAC1 channel 2, reserved for MSC1 */
+	{ dev_id: -1, },		/* DMAC1 channel 3 */
+	{ dev_id: -1, },		/* DMAC0 channel 4 */
+	{ dev_id: -1, },			/* DMAC0 channel 5 --- unavailable */
 };
 
 // Device FIFO addresses and default DMA modes
@@ -63,40 +69,35 @@ static const struct {
 	unsigned int dma_mode;
 	unsigned int dma_source;
 } dma_dev_table[DMA_ID_MAX] = {
-	{0, DMA_AUTOINIT, DMAC_DRSR_RS_EXT}, /* External request with DREQn */
-	{0x18000000, DMA_AUTOINIT, DMAC_DRSR_RS_NAND}, /* NAND request */
-	{CPHYSADDR(BCH_DR), DMA_8BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_BCH_ENC},
-	{CPHYSADDR(BCH_DR), DMA_8BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_BCH_DEC},
-	{0, DMA_AUTOINIT, DMAC_DRSR_RS_AUTO},
+	[DMA_ID_AUTO] = {0, DMA_AUTOINIT, DMAC_DRSR_RS_AUTO},
 //	{CPHYSADDR(TSSI_FIFO), DMA_32BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_TSSIIN},
-	{CPHYSADDR(UART3_TDR), DMA_8BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_UART3OUT},
-	{CPHYSADDR(UART3_RDR), DMA_8BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_UART3IN},
-	{CPHYSADDR(UART2_TDR), DMA_8BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_UART2OUT},
-	{CPHYSADDR(UART2_RDR), DMA_8BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_UART2IN},
-	{CPHYSADDR(UART1_TDR), DMA_8BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_UART1OUT},
-	{CPHYSADDR(UART1_RDR), DMA_8BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_UART1IN},
-	{CPHYSADDR(UART0_TDR), DMA_8BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_UART0OUT},
-	{CPHYSADDR(UART0_RDR), DMA_8BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_UART0IN},
-	{CPHYSADDR(SSI_DR(0)), DMA_32BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_SSI0OUT},
-	{CPHYSADDR(SSI_DR(0)), DMA_32BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_SSI0IN},
-	
-	/*spdif used */
-	//{CPHYSADDR(SPDIF_FIFO), DMA_16BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_AICOUT},
-	/*aic unpack used*/
-	{CPHYSADDR(AIC_DR), DMA_AIC_TX_CMD_UNPACK | DMA_MODE_WRITE, DMAC_DRSR_RS_AICOUT},
-	/*aic pack used*/
-	//{CPHYSADDR(AIC_DR), DMA_AIC_TX_CMD_PACK | DMA_MODE_WRITE, DMAC_DRSR_RS_AICOUT},
-	{CPHYSADDR(AIC_DR), DMA_32BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_AICIN},
-	{CPHYSADDR(MSC_TXFIFO(0)), DMA_32BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_MSC0OUT},
-	{CPHYSADDR(MSC_RXFIFO(0)), DMA_32BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_MSC0IN},
-	{0, DMA_AUTOINIT, DMAC_DRSR_RS_TCU},
-	{SADC_TSDAT, DMA_32BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_SADC},/* Touch Screen Data Register */
-	{CPHYSADDR(MSC_TXFIFO(1)), DMA_32BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_MSC1OUT}, /* SSC1 TX */
-	{CPHYSADDR(MSC_RXFIFO(1)), DMA_32BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_MSC1IN},	/* SSC1 RX */
-	{CPHYSADDR(SSI_DR(1)), DMA_32BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_SSI1OUT},
-	{CPHYSADDR(SSI_DR(1)), DMA_32BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_SSI1IN},
-	{CPHYSADDR(PCM_DP), DMA_16BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_PMOUT},
-	{CPHYSADDR(PCM_DP), DMA_16BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_PMIN},
+	[DMA_ID_UART3_TX] = {CPHYSADDR(UART3_TDR), DMA_8BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_UART3OUT},
+	[DMA_ID_UART3_RX] = {CPHYSADDR(UART3_RDR), DMA_8BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_UART3IN},
+	[DMA_ID_UART2_TX] = {CPHYSADDR(UART2_TDR), DMA_8BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_UART2OUT},
+	[DMA_ID_UART2_RX] = {CPHYSADDR(UART2_RDR), DMA_8BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_UART2IN},
+	[DMA_ID_UART1_TX] = {CPHYSADDR(UART1_TDR), DMA_8BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_UART1OUT},
+	[DMA_ID_UART1_RX] = {CPHYSADDR(UART1_RDR), DMA_8BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_UART1IN},
+	[DMA_ID_UART0_TX] = {CPHYSADDR(UART0_TDR), DMA_8BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_UART0OUT},
+	[DMA_ID_UART0_RX] = {CPHYSADDR(UART0_RDR), DMA_8BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_UART0IN},
+	[DMA_ID_SSI0_TX] = {CPHYSADDR(SSI_DR(0)), DMA_32BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_SSI0OUT},
+	[DMA_ID_SSI0_RX] = {CPHYSADDR(SSI_DR(0)), DMA_32BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_SSI0IN},
+	[DMA_ID_AIC_TX] = {CPHYSADDR(AIC_DR), DMA_AIC_TX_CMD_UNPACK | DMA_MODE_WRITE, DMAC_DRSR_RS_AICOUT},
+	[DMA_ID_AIC_RX] = {CPHYSADDR(AIC_DR), DMA_32BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_AICIN},
+	[DMA_ID_MSC0] = {0, 0, 0},
+	[DMA_ID_TCU_OVERFLOW] = {0, DMA_AUTOINIT, DMAC_DRSR_RS_TCU},
+	//[DMA_ID_SADC] = {CPHYSADDR(SADC_ADTCH), DMA_32BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_SADC},/* Touch Screen Data Register */
+	[DMA_ID_SADC] = { 0, 0, 0 },
+	[DMA_ID_MSC1] = {0, 0, 0},
+	[DMA_ID_MSC2] = {0, 0, 0},
+	[DMA_ID_SSI1_TX] = {CPHYSADDR(SSI_DR(1)), DMA_32BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_SSI1OUT},
+	[DMA_ID_SSI1_RX] = {CPHYSADDR(SSI_DR(1)), DMA_32BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_SSI1IN},
+	//[DMA_ID_PCM_TX] = {CPHYSADDR(PCM_PDP), DMA_16BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_PMOUT},
+	//[DMA_ID_PCM_RX] = {CPHYSADDR(PCM_PDP), DMA_16BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_PMIN},
+	[DMA_ID_PCM_TX] = { 0, 0, 0 },
+	[DMA_ID_PCM_RX] = { 0, 0, 0},
+	[DMA_ID_I2C0] = { 0, 0, 0 },
+	[DMA_ID_I2C1] = { 0, 0, 0 },
+	[DMA_ID_I2C2] = { 0, 0, 0 },
 	{},
 };
 
@@ -198,9 +199,16 @@ int jz_request_dma(int dev_id, const char *dev_str,
 	if (dev_id < 0 || dev_id >= DMA_ID_MAX)
 		return -EINVAL;
 
- 	for (i = 0; i < MAX_DMA_NUM; i++) {
-		if (jz_dma_table[i].dev_id < 0)
-			break;
+	for (i = 0; i < MAX_DMA_NUM; i++) {
+		    if (jz_dma_table[i].dev_id == dev_id)
+			    break;
+	}
+
+	if (i == MAX_DMA_NUM) {
+		for (i = 0; i < MAX_DMA_NUM; i++) {
+			if (jz_dma_table[i].dev_id < 0)
+				break;
+		}
 	}
 	if (i == MAX_DMA_NUM)  /* no free channel */
 		return -ENODEV;
@@ -528,7 +536,7 @@ void jz_set_oss_dma(unsigned int dmanr, unsigned int mode, unsigned int audio_fm
 			chan->mode &= ~DMAC_DCMD_DAI;
 		} else
 			printk("oss_dma_burst_mode() just supports DMA_MODE_READ or DMA_MODE_WRITE!\n");
-		
+
 		REG_DMAC_DCMD(chan->io) = chan->mode & ~DMA_MODE_MASK;
 		REG_DMAC_DRSR(chan->io) = chan->source;
 		break;
@@ -562,17 +570,17 @@ void jz_set_alsa_dma(unsigned int dmanr, unsigned int mode, unsigned int audio_f
 			chan->mode &= ~DMAC_DCMD_DAI;
 		} else
 			printk("alsa_dma_burst_mode() just supports DMA_MODE_READ or DMA_MODE_WRITE!\n");
-		
+
 		REG_DMAC_DCMD(chan->io) = chan->mode & ~DMA_MODE_MASK;
 		REG_DMAC_DRSR(chan->io) = chan->source;
 		break;
 	}
 }
 
-//#define JZ4810_DMAC_TEST_ENABLE
-#undef JZ4810_DMAC_TEST_ENABLE
+//#define JZ4760_DMAC_TEST_ENABLE
+#undef JZ4760_DMAC_TEST_ENABLE
 
-#ifdef JZ4810_DMAC_TEST_ENABLE
+#ifdef JZ4760_DMAC_TEST_ENABLE
 
 /*
  * DMA test: external address <--> external address
@@ -604,9 +612,9 @@ static int dma_check_result(void *src, void *dst, int size)
 	return err;
 }
 
-static irqreturn_t jz4810_dma_irq(int irq, void *dev_id)
+static irqreturn_t jz4760_dma_irq(int irq, void *dev_id)
 {
-	printk("jz4810_dma_irq %d\n", irq);
+	printk("jz4760_dma_irq %d\n", irq);
 
 
 	if (__dmac_channel_transmit_halt_detected(dma_chan)) {
@@ -652,7 +660,7 @@ void dma_nodesc_test(void)
 	printk("dma_nodesc_test\n");
 
 	/* Request DMA channel and setup irq handler */
-	dma_chan = jz_request_dma(DMA_ID_AUTO, "auto", jz4810_dma_irq,
+	dma_chan = jz_request_dma(DMA_ID_AUTO, "auto", jz4760_dma_irq,
 				  IRQF_DISABLED, NULL);
 	if (dma_chan < 0) {
 		printk("Setup irq failed\n");
@@ -695,8 +703,6 @@ void dma_nodesc_test(void)
 	REG_DMAC_DCCSR(dma_chan) = DMAC_DCCSR_NDES | DMAC_DCCSR_EN;
 	REG_DMAC_DMACR(dma_chan/HALF_DMA_NUM) = DMAC_DMACR_DMAE; /* global DMA enable bit */
 
-	printk("DMA started. IMR=%08x\n", REG_INTC_IMR);
-
 	/* wait a long time, ensure transfer end */
 	printk("wait 3s...\n");
 	mdelay(3000);		/* wait 3s */
@@ -722,7 +728,7 @@ void dma_desc_test(void)
 	printk("dma_desc_test\n");
 
 	/* Request DMA channel and setup irq handler */
-	dma_chan = jz_request_dma(DMA_ID_AUTO, "auto", jz4810_dma_irq,
+	dma_chan = jz_request_dma(DMA_ID_AUTO, "auto", jz4760_dma_irq,
 				  IRQF_DISABLED, NULL);
 	if (dma_chan < 0) {
 		printk("Setup irq failed\n");
@@ -783,7 +789,7 @@ void dma_desc_test(void)
 	desc->dsadr = dma_src_phys_addr + 8192;	/* DMA source address */
 	desc->dtadr = dma_dst_phys_addr + 8192;	/* DMA target address */
 	desc->ddadr = (next << 24) + 256;    /* size: 256*16 bytes = 4096 bytes */
-	
+
 	desc++;
 	next = (dma_desc_phys_addr + 4*(sizeof(jz_dma_desc))) >> 4;
 
@@ -809,7 +815,6 @@ void dma_desc_test(void)
 	/* DMA doorbell set -- start DMA now ... */
 	REG_DMAC_DMADBSR(dma_chan/HALF_DMA_NUM) = 1 << dma_chan;
 
-	printk("DMA started. IMR=%08x\n", REG_INTC_IMR);
 	/* wait a long time, ensure transfer end */
 	printk("wait 3s...\n");
 	mdelay(3000);		/* wait 3s */
@@ -827,6 +832,15 @@ void dma_desc_test(void)
 	jz_free_dma(dma_chan);
 }
 
+/*
+ * channel 0: read
+ * channel 1: write
+ * read and write are simutanously
+ */
+void dma_two_desc_test(void) {
+
+}
+
 #endif
 
 //EXPORT_SYMBOL_NOVERS(jz_dma_table);
diff --git a/arch/mips/jz4810/irq.c b/arch/mips/jz4810/irq.c
index dd83b7a153f..a96a2cc27e2 100644
--- a/arch/mips/jz4810/irq.c
+++ b/arch/mips/jz4810/irq.c
@@ -154,7 +154,6 @@ static struct irq_chip gpio_irq_type = {
 /*
  * DMA irq type
  */
-
 static void enable_dma_irq(unsigned int irq)
 {
 	unsigned int intc_irq;
@@ -173,13 +172,17 @@ static void enable_dma_irq(unsigned int irq)
 
 static void disable_dma_irq(unsigned int irq)
 {
-	__dmac_channel_disable_irq(irq - IRQ_DMA_0);
+	int chan = irq - IRQ_DMA_0;
+	__dmac_disable_channel(chan);
+	__dmac_channel_disable_irq(chan);
 }
 
 static void mask_and_ack_dma_irq(unsigned int irq)
 {
 	unsigned int intc_irq;
 
+	disable_dma_irq(irq);
+
 	if ( irq < (IRQ_DMA_0 + HALF_DMA_NUM) ) 	/* DMAC Group 0 irq */
 		intc_irq = IRQ_DMAC0;
 	else if ( irq < (IRQ_DMA_0 + MAX_DMA_NUM) ) 	/* DMAC Group 1 irq */
@@ -189,8 +192,8 @@ static void mask_and_ack_dma_irq(unsigned int irq)
 		return ;
 	}
 	__intc_ack_irq(intc_irq);
-	__dmac_channel_ack_irq(irq-IRQ_DMA_0); /* needed?? add 20080506, Wolfgang */
-	__dmac_channel_disable_irq(irq - IRQ_DMA_0);
+	//__dmac_channel_ack_irq(irq-IRQ_DMA_0); /* needed?? add 20080506, Wolfgang */
+	//__dmac_channel_disable_irq(irq - IRQ_DMA_0);
 }
 
 static void end_dma_irq(unsigned int irq)
@@ -221,6 +224,7 @@ static struct irq_chip dma_irq_type = {
 	.end = end_dma_irq,
 };
 
+#if 0
 /*
  * MDMA irq type
  */
@@ -286,6 +290,7 @@ static struct irq_chip mdma_irq_type = {
 	.ack = mask_and_ack_mdma_irq,
 	.end = end_mdma_irq,
 };
+#endif
 
 //----------------------------------------------------------------------
 
@@ -378,63 +383,77 @@ void __init arch_init_irq(void)
 		set_irq_chip_and_handler(IRQ_DMA_0 + i, &dma_irq_type, handle_level_irq);
 	}
 
+#if 0
 	/* Set up MDMAC irq
 	 */
 	for (i = 0; i < NUM_MDMA; i++) {
 		disable_mdma_irq(IRQ_MDMA_0 + i);
 		set_irq_chip_and_handler(IRQ_MDMA_0 + i, &mdma_irq_type, handle_level_irq);
 	}
+#endif
 
 	/* Set up BDMA irq
 	 */
 	for (i = 0; i < MAX_BDMA_NUM; i++) {
 		disable_bdma_irq(IRQ_BDMA_0 + i);
-		set_irq_chip_and_handler(IRQ_MDMA_0 + i, &bdma_irq_type, handle_level_irq);
+		set_irq_chip_and_handler(IRQ_BDMA_0 + i, &bdma_irq_type, handle_level_irq);
 	}
 
 	/* Set up GPIO irq
 	 */
-#if 1
-//	for (i = 0; i < NUM_GPIO; i++) {
-	for (i = 0; i < 90; i++) {
+#ifndef JZ_BOOTUP_UART_TXD
+#error "JZ_BOOTUP_UART_TXD is not set, please define it int your board header file!"
+#endif
+#ifndef JZ_BOOTUP_UART_RXD
+#error "JZ_BOOTUP_UART_RXD is not set, please define it int your board header file!"
+#endif
+	for (i = 0; i < NUM_GPIO; i++) {
+		if (unlikely(i == JZ_BOOTUP_UART_TXD))
+			continue;
+		if (unlikely(i == JZ_BOOTUP_UART_RXD))
+			continue;
 		disable_gpio_irq(IRQ_GPIO_0 + i);
 		set_irq_chip_and_handler(IRQ_GPIO_0 + i, &gpio_irq_type, handle_level_irq);
 	}
-#endif
-
 }
 
 static int plat_real_irq(int irq)
 {
-	switch (irq) {
-	case IRQ_GPIO0:
-		irq = __gpio_group_irq(0) + IRQ_GPIO_0;
-		break;
-	case IRQ_GPIO1:
-		irq = __gpio_group_irq(1) + IRQ_GPIO_0 + 32;
-		break;
-	case IRQ_GPIO2:
-		irq = __gpio_group_irq(2) + IRQ_GPIO_0 + 64;
-		break;
-	case IRQ_GPIO3:
-		irq = __gpio_group_irq(3) + IRQ_GPIO_0 + 96;
-		break;
-	case IRQ_GPIO4:
-		irq = __gpio_group_irq(4) + IRQ_GPIO_0 + 128;
-		break;
-	case IRQ_GPIO5:
-		irq = __gpio_group_irq(5) + IRQ_GPIO_0 + 160;
-		break;
-	case IRQ_DMAC0:
-	case IRQ_DMAC1:
-		irq = __dmac_get_irq() + IRQ_DMA_0;
-		break;
-	case IRQ_MDMA:
-		irq = __mdmac_get_irq() + IRQ_MDMA_0;
-		break;
-	case IRQ_BDMA:
-		irq = __bdmac_get_irq() + IRQ_BDMA_0;
-		break;
+	int group = 0;
+
+	if ((irq >= IRQ_GPIO5) && (irq <= IRQ_GPIO0)) {
+		group = IRQ_GPIO0 - irq;
+		irq = __gpio_group_irq(group);
+		if (irq >= 0)
+			irq += IRQ_GPIO_0 + 32 * group;
+	} else {
+		switch (irq) {
+		case IRQ_DMAC0:
+		case IRQ_DMAC1:
+			irq = __dmac_get_irq();
+			if (irq < 0) {
+				printk("REG_DMAC_DMAIPR(0) = 0x%08x\n", REG_DMAC_DMAIPR(0));
+				printk("REG_DMAC_DMAIPR(1) = 0x%08x\n", REG_DMAC_DMAIPR(1));
+				return irq;
+			}
+			irq += IRQ_DMA_0;
+			break;
+#if 0
+		case IRQ_MDMA:
+			irq = __mdmac_get_irq();
+			if (irq < 0)
+				return irq;
+			irq += IRQ_MDMA_0;
+			break;
+#endif
+		case IRQ_BDMA:
+			irq = __bdmac_get_irq();
+			if (irq < 0)
+				return irq;
+
+			irq += IRQ_BDMA_0;
+			break;
+		}
 	}
 
 	return irq;
@@ -444,10 +463,10 @@ asmlinkage void plat_irq_dispatch(void)
 {
 	int irq = 0;
 
-	static unsigned long intc_ipr0 = 0, intc_ipr1 = 0;
+	unsigned long intc_ipr0 = 0, intc_ipr1 = 0;
 
-	intc_ipr0 |= REG_INTC_IPR(0);
-	intc_ipr1 |= REG_INTC_IPR(1);
+	intc_ipr0 = REG_INTC_IPR(0);
+	intc_ipr1 = REG_INTC_IPR(1);
 
 	if (!(intc_ipr0 || intc_ipr1))	return;
 
@@ -461,5 +480,9 @@ asmlinkage void plat_irq_dispatch(void)
 	}
 
 	irq = plat_real_irq(irq);
+	WARN((irq < 0), "irq raised, but no irq pending!\n");
+	if (irq < 0)
+		return;
+
 	do_IRQ(irq);
 }
diff --git a/arch/mips/jz4810/platform.c b/arch/mips/jz4810/platform.c
index fccb72b91c3..0cfe1785948 100644
--- a/arch/mips/jz4810/platform.c
+++ b/arch/mips/jz4810/platform.c
@@ -23,6 +23,7 @@
 #include <linux/usb/musb.h>
 
 extern void __init board_msc_init(void);
+extern void __init board_i2c_init(void);
 
 
 /* OHCI (USB full speed host controller) */
@@ -133,6 +134,7 @@ static struct platform_device jz_usb_otg_device = {
 	.resource	= jz_usb_otg_resources,
 };
 
+#if 0
 /** MMC/SD controller MSC0**/
 static struct resource jz_msc0_resources[] = {
 	{
@@ -202,6 +204,7 @@ static struct platform_device *jz_msc_devices[] __initdata = {
 	&jz_msc0_device,
 	&jz_msc1_device,
 };
+#endif
 
 /*
 int __init jz_add_msc_devices(unsigned int controller, struct jz_mmc_platform_data *plat)
@@ -237,15 +240,13 @@ static struct msm_snd_endpoints jz_snd_endpoints = {
 };
 */
 
-/*
 static struct platform_device jz_snd_device = {
 	.name = "mixer",
 	.id = -1,
 	.dev = {
-		.platform_data = &jz_snd_endpoints,
+		.platform_data = &jz_snd_device,
 	},
 };
-*/
 /* - Sound device */
 
 static struct resource jz_i2c0_resources[] = {
@@ -254,6 +255,11 @@ static struct resource jz_i2c0_resources[] = {
 		.end            = CPHYSADDR(I2C0_BASE) + 0x1000 - 1,
 		.flags          = IORESOURCE_MEM,
 	},
+	[1] = {
+                .start          = IRQ_I2C0,
+                .end            = IRQ_I2C0,
+                .flags          = IORESOURCE_IRQ,
+        },
 };
 
 static struct resource jz_i2c1_resources[] = {
@@ -262,6 +268,24 @@ static struct resource jz_i2c1_resources[] = {
 		.end            = CPHYSADDR(I2C1_BASE) + 0x1000 - 1,
 		.flags          = IORESOURCE_MEM,
 	},
+  	[1] = {
+                .start          = IRQ_I2C1,
+                .end            = IRQ_I2C1,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static struct resource jz_i2c2_resources[] = {
+	[0] = {
+		.start          = CPHYSADDR(I2C2_BASE),
+		.end            = CPHYSADDR(I2C2_BASE) + 0x1000 - 1,
+		.flags          = IORESOURCE_MEM,
+	},
+  	[1] = {
+                .start          = IRQ_I2C2,
+                .end            = IRQ_I2C2,
+                .flags          = IORESOURCE_IRQ,
+        },
 };
 
 static u64 jz_i2c_dmamask =  ~(u32)0;
@@ -287,6 +311,43 @@ static struct platform_device jz_i2c1_device = {
 	.num_resources  = ARRAY_SIZE(jz_i2c1_resources),
 	.resource       = jz_i2c1_resources,
 };
+static struct platform_device jz_i2c2_device = {
+	.name = "jz_i2c2",
+	.id = 5,
+	.dev = {
+		.dma_mask               = &jz_i2c_dmamask,
+		.coherent_dma_mask      = 0xffffffff,
+	},
+	.num_resources  = ARRAY_SIZE(jz_i2c2_resources),
+	.resource       = jz_i2c2_resources,
+};
+
+/*AOSD*/
+static struct resource jz_aosd_resources[] = {
+	[0] = {
+		.start          = CPHYSADDR(AOSD_BASE),
+		.end            = CPHYSADDR(AOSD_BASE) + 0x1000 - 1,
+		.flags          = IORESOURCE_MEM,
+	},
+	[1] = {
+		.start          = IRQ_AOSD,
+		.end            = IRQ_AOSD,
+		.flags          = IORESOURCE_IRQ,
+	},
+};
+
+static u64 jz_aosd_dmamask =  ~(u32)0;
+
+static struct platform_device jz_aosd_device = {
+	.name = "jz-aosd",
+	.id = 0,
+	.dev = {
+		.dma_mask               = &jz_aosd_dmamask,
+		.coherent_dma_mask      = 0xffffffff,
+	},
+	.num_resources  = ARRAY_SIZE(jz_aosd_resources),
+	.resource       = jz_aosd_resources,
+};
 
 /* All */
 static struct platform_device *jz_platform_devices[] __initdata = {
@@ -294,9 +355,11 @@ static struct platform_device *jz_platform_devices[] __initdata = {
 	&jz_usb_otg_xceiv_device,
 	&jz_usb_otg_device,
 	&jz_lcd_device,
-//	&jz_snd_device,
+	&jz_aosd_device,
+	&jz_snd_device,
 	&jz_i2c0_device,
 	&jz_i2c1_device,
+	&jz_i2c2_device,
 };
 
 #ifdef CONFIG_ANDROID_PMEM
@@ -351,7 +414,10 @@ static void platform_pmem_device_setup(void)
 
 static int __init jz_platform_init(void)
 {
-	int ret = platform_add_devices(jz_platform_devices, ARRAY_SIZE(jz_platform_devices));
+	int ret = 0;
+
+	board_i2c_init();
+	ret = platform_add_devices(jz_platform_devices, ARRAY_SIZE(jz_platform_devices));
 #ifdef CONFIG_ANDROID_PMEM
 	platform_pmem_device_setup();
 #endif
diff --git a/arch/mips/jz4810/pm.c b/arch/mips/jz4810/pm.c
index c0ce01f3086..b77ecc7761c 100644
--- a/arch/mips/jz4810/pm.c
+++ b/arch/mips/jz4810/pm.c
@@ -1,15 +1,15 @@
 /*
  * linux/arch/mips/jz4810/common/pm.c
- * 
+ *
  * JZ4810 Power Management Routines
- * 
+ *
  * Copyright (C) 2006 Ingenic Semiconductor Inc.
  * Author: <jlwei@ingenic.cn>
  *
  *  This program is free software; you can distribute it and/or modify it
  *  under the terms of the GNU General Public License (Version 2) as
  *  published by the Free Software Foundation.
- * 
+ *
  *  This program is distributed in the hope it will be useful, but WITHOUT
  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
@@ -18,7 +18,7 @@
  *  You should have received a copy of the GNU General Public License along
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- * 
+ *
  */
 
 #include <linux/init.h>
@@ -26,14 +26,14 @@
 #include <linux/sched.h>
 #include <linux/interrupt.h>
 #include <linux/suspend.h>
-#include <linux/proc_fs.h> 
+#include <linux/proc_fs.h>
 #include <linux/sysctl.h>
 
 #include <asm/cacheops.h>
 #include <asm/jzsoc.h>
 
 #undef DEBUG
-//#define DEBUG 
+//#define DEBUG
 #ifdef DEBUG
 #define dprintk(x...)	printk(x)
 #else
@@ -45,9 +45,9 @@
 extern void jz_cpu_sleep(void);
 extern void jz_cpu_resume(void);
 
-/* 
+/*
  * __gpio_as_sleep set all pins to pull-disable, and set all pins as input
- * except sdram and the pins which can be used as CS1_N to CS4_N for chip select. 
+ * except sdram and the pins which can be used as CS1_N to CS4_N for chip select.
  */
 #define __gpio_as_sleep()	              \
 do {	                                      \
@@ -82,8 +82,8 @@ static int jz_pm_do_hibernate(void)
 	REG_INTC_IMSR(0) = 0xffffffff;
 	REG_INTC_IMSR(1) = 0xffffffff;
 
-	/* 
-	 * RTC Wakeup or 1Hz interrupt can be enabled or disabled 
+	/*
+	 * RTC Wakeup or 1Hz interrupt can be enabled or disabled
 	 * through  RTC driver's ioctl (linux/driver/char/rtc_jz.c).
 	 */
 #if 0
@@ -117,16 +117,16 @@ static int jz_pm_do_hibernate(void)
 
 /* NOTES:
  * 1: Pins that are floated (NC) should be set as input and pull-enable.
- * 2: Pins that are pull-up or pull-down by outside should be set as input 
+ * 2: Pins that are pull-up or pull-down by outside should be set as input
  *    and pull-disable.
- * 3: Pins that are connected to a chip except sdram and nand flash 
+ * 3: Pins that are connected to a chip except sdram and nand flash
  *    should be set as input and pull-disable, too.
  */
 static void jz_board_do_sleep(unsigned long *ptr)
 {
 #if 0
 	unsigned char i;
-        
+
         /* Print messages of GPIO registers for debug */
 	for(i=0;i<GPIO_PORT_NUM;i++) {
 		dprintk("run dat:%x pin:%x fun:%x sel:%x dir:%x pull:%x msk:%x trg:%x\n",        \
@@ -146,36 +146,36 @@ static void jz_board_do_sleep(unsigned long *ptr)
 	}
 
         /*
-         * Set all pins to pull-disable, and set all pins as input except 
-         * sdram and the pins which can be used as CS1_N to CS4_N for chip select. 
+         * Set all pins to pull-disable, and set all pins as input except
+         * sdram and the pins which can be used as CS1_N to CS4_N for chip select.
          */
         __gpio_as_sleep();
 
         /*
 	 * Set proper status for GPC21 to GPC24 which can be used as CS1_N to CS4_N.
-	 * Keep the pins' function used for chip select(CS) here according to your   
+	 * Keep the pins' function used for chip select(CS) here according to your
          * system to avoid chip select crashing with sdram when resuming from sleep mode.
          */
 
 #if defined(CONFIG_JZ4810_APUS)
-        /* GPB25/CS1_N is used as chip select for nand flash, shouldn't be change. */ 
+        /* GPB25/CS1_N is used as chip select for nand flash, shouldn't be change. */
 
         /* GPB26/CS2_N is connected to nand flash, needn't be changed. */
 
         /* GPB28/CS3_N is used as cs8900's chip select, shouldn't be changed. */
- 
-	/* GPB27/CS4_N is used as NOR's chip select, shouldn't be changed. */ 
+
+	/* GPB27/CS4_N is used as NOR's chip select, shouldn't be changed. */
 #endif
 
- 	/* 
-         * Enable pull for NC pins here according to your system 
+ 	/*
+         * Enable pull for NC pins here according to your system
 	 */
 
 #if defined(CONFIG_JZ4810_APUS)
 #endif
 
-	/* 
-         * If you must set some GPIOs as output to high level or low level,  
+	/*
+         * If you must set some GPIOs as output to high level or low level,
          * you can set them here, using:
          * __gpio_as_output(n);
          * __gpio_set_pin(n); or  __gpio_clear_pin(n);
@@ -225,10 +225,10 @@ static void jz_board_do_resume(unsigned long *ptr)
 
 		 REG_GPIO_PXIMS(i)=*ptr;
 		 REG_GPIO_PXIMC(i)=~(*ptr++);
-	
+
 		 REG_GPIO_PXDATS(i)=*ptr;
 		 REG_GPIO_PXDATC(i)=~(*ptr++);
-	
+
 		 REG_GPIO_PXTRGS(i)=*ptr;
 		 REG_GPIO_PXTRGC(i)=~(*ptr++);
 	}
@@ -243,25 +243,25 @@ static void jz_board_do_resume(unsigned long *ptr)
 }
 
 static int jz_pm_do_sleep(void)
-{ 
-#if 0
+{
+#if 1
 	unsigned long delta;
-	unsigned long nfcsr = REG_EMC_NFCSR;
-	unsigned long opcr = REG_CPM_OPCR;
 	unsigned long imr0 = REG_INTC_IMR(0);
 	unsigned long imr1 = REG_INTC_IMR(1);
+	unsigned long opcr = REG_CPM_OPCR;
+#if 0
+	unsigned long nfcsr = REG_EMC_NFCSR;
+
 	unsigned long sadc = REG_SADC_ENA;
 	unsigned long pmembs0 = REG_EMC_PMEMBS0;
 	unsigned long sleep_gpio_save[7*(GPIO_PORT_NUM-1)];
+#endif
 	unsigned long cpuflags;
 
 	printk("Put CPU into sleep mode.\n");
-#if 0	
- 	/* Enter SLEEP mode */
-	lcr &= ~CPM_LCR_LPM_MASK;
-	lcr |= CPM_LCR_LPM_SLEEP;
-	REG_CPM_LCR = lcr;
-#endif
+
+	CMSREG32(CPM_LCR, CPM_LCR_LPM_SLEEP, CPM_LCR_LPM_MASK);
+
 	/* Preserve current time */
 	delta = xtime.tv_sec - REG_RTC_RSR;
 
@@ -269,29 +269,29 @@ static int jz_pm_do_sleep(void)
 	local_irq_save(cpuflags);
 
         /* Disable nand flash */
-	REG_EMC_NFCSR = ~0xff;
+	//REG_EMC_NFCSR = ~0xff;
 
 	/*pull up enable pin of DQS */
-	REG_EMC_PMEMBS0 |= (0xff << 8);
+	//REG_EMC_PMEMBS0 |= (0xff << 8);
 
         /* stop sadc */
-	REG_SADC_ENA &= ~0x7;
-	while((REG_SADC_ENA & 0x7) != 0);
- 	udelay(100);
+	//REG_SADC_ENA &= ~0x7;
+	//while((REG_SADC_ENA & 0x7) != 0);
+ 	//udelay(100);
 
         /*stop udc and usb*/
-	__cpm_suspend_uhc_phy();
-	__cpm_suspend_otg_phy();
+	//__cpm_suspend_uhc_phy();
+	//__cpm_suspend_otg_phy();
 
 	/*stop gps*/
-	__cpm_suspend_gps();
+	//__cpm_suspend_gps();
 
 	/* Mask all interrupts */
 	REG_INTC_IMSR(0) = 0xffffffff;
 	REG_INTC_IMSR(1) = 0xffffffff;
 
 	/* Sleep on-board modules */
-	jz_board_do_sleep(sleep_gpio_save);
+	//jz_board_do_sleep(sleep_gpio_save);
 
 #if 0
 	/* Just allow following interrupts to wakeup the system.
@@ -316,10 +316,25 @@ static int jz_pm_do_sleep(void)
 
 #endif
 	/* WAKEUP key */
-	__gpio_as_irq_rise_edge(GPIO_WAKEUP);
-	__gpio_unmask_irq(GPIO_WAKEUP);
-	__intc_unmask_irq(IRQ_GPIO0 - (GPIO_WAKEUP/32));  /* unmask IRQ_GPIOn depends on GPIO_WAKEUP */
-
+	/* PD17: boot_sel[0] */
+	__gpio_as_irq_fall_edge(32 * 3 + 17);
+	__gpio_ack_irq(32 * 3 + 17);
+	__gpio_unmask_irq(32 * 3 + 17);
+	__intc_unmask_irq(IRQ_GPIO0 - ((32 * 3 + 17)/32));  /* unmask IRQ_GPIOn depends on GPIO_WAKEUP */
+
+	REG_GPIO_PXFLGC(3) = 0xffffffff;
+	printk("===>int = 0x%08x\n", REG_GPIO_PXINT(3));
+        printk("===>mask = 0x%08x\n", REG_GPIO_PXMASK(3));
+        printk("===>pat1 = 0x%08x\n", REG_GPIO_PXPAT1(3));
+        printk("===>pat0 = 0x%08x\n", REG_GPIO_PXPAT0(3));
+        printk("===>flag = 0x%08x\n", REG_GPIO_PXFLG(3));
+
+	printk("gpio_level = %d IPR0 = 0x%08x IPR1 = 0x%08x\n",
+		__gpio_get_pin(32 * 3 + 17), REG_INTC_IPR(0), REG_INTC_IPR(1));
+
+	printk("===>enter sleeping ......\n");
+#if 0
+	printk("Shutdown P0 ......\n");
 	/*power down the p0*/
 	REG_CPM_OPCR |= CPM_OPCR_PD;
 
@@ -336,8 +351,9 @@ static int jz_pm_do_sleep(void)
 
 	/* *** go zzz *** */
 	jz_cpu_sleep();
-	
-#if 0
+
+#else
+
 	__asm__(".set\tmips3\n\t"
 		"sync\n\t"
 		"wait\n\t"
@@ -346,21 +362,21 @@ static int jz_pm_do_sleep(void)
 		"nop\n\t"
 		"nop\n\t"
 		".set\tmips0");
-
-	/* Restore to IDLE mode */
-	lcr = REG_CPM_LCR;
-	lcr &= ~CPM_LCR_LPM_MASK;
-	lcr |= CPM_LCR_LPM_IDLE;
-	REG_CPM_LCR = lcr;
 #endif
 
-	/*return from sleep.S*/
+	/*if power down p0 ,return from sleep.S*/
+	printk("gpio_level = %d IPR0 = 0x%08x IPR1 = 0x%08x\n",
+		__gpio_get_pin(32 * 3 + 17), REG_INTC_IPR(0), REG_INTC_IPR(1));
+	__gpio_ack_irq(32 * 3 + 17);
+
+	/* Restore to IDLE mode */
+	CMSREG32(CPM_LCR, CPM_LCR_LPM_IDLE, CPM_LCR_LPM_MASK);
 
         /* Restore nand flash control register */
-	REG_EMC_NFCSR = nfcsr;
+	//REG_EMC_NFCSR = nfcsr;
 
 	/*Restore pmembs0*/
-	REG_EMC_PMEMBS0 = pmembs0;
+	//REG_EMC_PMEMBS0 = pmembs0;
 
 	/* Restore interrupts */
 	REG_INTC_IMSR(0) = imr0;
@@ -368,12 +384,12 @@ static int jz_pm_do_sleep(void)
 
 	REG_INTC_IMCR(0) = ~imr0;
 	REG_INTC_IMCR(1) = ~imr1;
-	
+
 	/* Restore sadc */
-	REG_SADC_ENA = sadc;
-	
+	//REG_SADC_ENA = sadc;
+
 	/* Resume on-board modules */
-	jz_board_do_resume(sleep_gpio_save);
+	//jz_board_do_resume(sleep_gpio_save);
 
 	/* Restore Oscillator and Power Control Register */
 	REG_CPM_OPCR = opcr;
@@ -459,11 +475,11 @@ int jz_pm_sleep(void)
 }
 #endif
 
-/* Put CPU to HIBERNATE mode 
+/* Put CPU to HIBERNATE mode
  *----------------------------------------------------------------------------
  * Power Management sleep sysctl interface
  *
- * Write "mem" to /sys/power/state invokes this function 
+ * Write "mem" to /sys/power/state invokes this function
  * which initiates a poweroff.
  */
 void jz_pm_hibernate(void)
@@ -475,11 +491,11 @@ void jz_pm_hibernate(void)
  *----------------------------------------------------------------------------
  * Power Management sleep sysctl interface
  *
- * Write "standby" to /sys/power/state invokes this function 
+ * Write "standby" to /sys/power/state invokes this function
  * which initiates a sleep.
  */
 
-int jz_pm_sleep(void) 
+int jz_pm_sleep(void)
 {
 	return jz_pm_do_sleep();
 }
diff --git a/arch/mips/jz4810/setup.c b/arch/mips/jz4810/setup.c
index 5a097f578d0..3df87e87e4a 100644
--- a/arch/mips/jz4810/setup.c
+++ b/arch/mips/jz4810/setup.c
@@ -156,8 +156,8 @@ static void __init soc_dmac_setup(void)
 
 static void __init jz_soc_setup(void)
 {
-	soc_cpm_setup();
-	soc_harb_setup();
+//	soc_cpm_setup();
+//	soc_harb_setup();
 //	soc_emc_setup();
 	soc_dmac_setup();
 }
@@ -172,7 +172,8 @@ static void __init jz_serial_setup(void)
 	s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
 	s.iotype = SERIAL_IO_MEM;
 	s.regshift = 2;
-	s.uartclk = jz_clocks.extalclk ;
+	s.uartclk = 12000000;
+//	s.uartclk = jz_clocks.extalclk ;
 
 	s.line = 0;
 	s.membase = (u8 *)UART0_BASE;
@@ -288,22 +289,16 @@ void __init plat_mem_setup(void)
 {
 	char *argptr;
 
-	serial_puts("jz plat_mem_setup \n");
 	argptr = prom_getcmdline();
-	serial_puts("jz plat_mem_setup 002\n");
 
-#if 1
 	__asm__ (
 		"li    $2, 0xa9000000 \n\t"
 		"mtc0  $2, $5, 4      \n\t"
 		"nop                  \n\t"
 		::"r"(2));
-#endif
 
 	/* IO/MEM resources. Which will be the addtion value in `inX' and
 	 * `outX' macros defined in asm/io.h */
-	serial_puts("jz plat_mem_setup 003\n");
-
 	set_io_port_base(0);
 	ioport_resource.start	= 0x00000000;
 	ioport_resource.end	= 0xffffffff;
@@ -313,14 +308,13 @@ void __init plat_mem_setup(void)
 	_machine_restart = jz_restart;
 	_machine_halt = jz_halt;
 	pm_power_off = jz_power_off;
-	serial_puts("jz plat_mem_setup 004\n");
 
 	jz_soc_setup();
-
-	serial_puts("jz plat_mem_setup 005\n");
 	jz_serial_setup();
-	serial_puts("jz plat_mem_setup 006\n");
 	jz_board_setup();
-	serial_puts("jz plat_mem_setup 007\n");
+
+#ifdef CONFIG_PM
+        jz_pm_init();
+#endif
 }
 
diff --git a/arch/mips/jz4810/sleep.S b/arch/mips/jz4810/sleep.S
index 39639c2645e..062df5900be 100644
--- a/arch/mips/jz4810/sleep.S
+++ b/arch/mips/jz4810/sleep.S
@@ -11,11 +11,11 @@
  * the Free Software Foundation; either version 2 of the License, or
  * (at your option) any later version.
  */
-
+#define __MIPS_ASSEMBLER
 #include <asm/regdef.h>
 #include <asm/mipsregs.h>
 #include <asm/mach-jz4810/jz4810cpm.h>
-#inclede <asm/mach-jz4810/jz4810emc.h>	
+#inclede <asm/mach-jz4810/jz4810emc.h>
 	.text
 	.set	noreorder
 	.set	noat
@@ -140,9 +140,9 @@ jz_cpu_sleep:
 	li	t0, 1
 	la	t1, EMC_RTCOR
 	sh	t0, 0(t1)
-	
 
-	
+
+
 	/* disable PLL */
 	la	t0, CPM_PLCR1
 	sw	$0, 0(t0)
@@ -171,9 +171,9 @@ jz_cpu_sleep:
 	nop
 
 	/* enter sleep mode */
-	.set	mips3	
+	.set	mips3
 	wait
-	nop	
+	nop
 	.set	mips0
 
 2:	j	2b		/* loop waiting for suspended */
@@ -189,7 +189,7 @@ jz_cpu_sleep:
 	.globl	jz_cpu_resume
 jz_cpu_resume:
 #if 0   /*60 no have */
-	
+
 	/* clear SCR.HGP */
 	la	t0, CPM_SCR
 	lw	t1, 0(t0)
diff --git a/arch/mips/jz4810/time.c b/arch/mips/jz4810/time.c
index 04037264f71..0f1a466837f 100644
--- a/arch/mips/jz4810/time.c
+++ b/arch/mips/jz4810/time.c
@@ -1,8 +1,8 @@
 /*
- * linux/arch/mips/jz4810/time.c
- * 
- * Setting up the clock on the JZ4810 boards.
- * 
+ * linux/arch/mips/jz4760/time.c
+ *
+ * Setting up the clock on the JZ4760 boards.
+ *
  * Copyright (C) 2008 Ingenic Semiconductor Inc.
  * Author: <jlwei@ingenic.cn>
  *
@@ -30,6 +30,7 @@
 
 /* This is for machines which generate the exact clock. */
 
+
 #define JZ_TIMER_TCU_CH  5
 #define JZ_TIMER_IRQ  IRQ_TCU1
 
@@ -60,35 +61,25 @@ static struct irqaction jz_irqaction = {
 	.name		= "jz-timerirq",
 };
 
-static unsigned int current_cycle_high = 0;
-
 union clycle_type
 {
 	cycle_t cycle64;
 	unsigned int cycle32[2];
 };
 
+
 cycle_t jz_get_cycles(void)
 {
 	/* convert jiffes to jz timer cycles */
-	unsigned int ostcount;
 	unsigned long cpuflags;
-	unsigned int current_cycle;
-	unsigned int flag;
 	union clycle_type old_cycle;
+
 	local_irq_save(cpuflags);
-	current_cycle = current_cycle_high;
-	ostcount = REG_TCU_OSTCNT;
-	flag = (REG_TCU_TFR & TCU_TFCR_OSTFCL) ? 1: 0;
-	if(flag)
-		ostcount = REG_TCU_OSTCNT;	  
+	old_cycle.cycle32[0] = REG_OST_OSTCNTL;
+	old_cycle.cycle32[1] = REG_OST_OSTCNTH_BUF;
 	local_irq_restore(cpuflags);
 
-	old_cycle.cycle32[0] = ostcount;
-	old_cycle.cycle32[1] = current_cycle + flag;
-
 	return (old_cycle.cycle64);
-
 }
 
 static struct clocksource clocksource_jz = {
@@ -100,18 +91,6 @@ static struct clocksource clocksource_jz = {
 	.flags		= CLOCK_SOURCE_WATCHDOG,
 };
 
-static irqreturn_t jzclock_handler(int irq, void *dev_id)
-{
-	REG_TCU_TFCR = TCU_TFCR_OSTFCL; /* ACK timer */
-	current_cycle_high++;
-	return IRQ_HANDLED;
-}
-
-static struct irqaction jz_clockaction = {
-	.handler	= jzclock_handler,
-	.flags		= IRQF_DISABLED  | IRQF_TIMER,
-	.name		= "jz-clockcycle",
-};
 static int __init jz_clocksource_init(void)
 {
 	unsigned int latch;
@@ -123,15 +102,12 @@ static int __init jz_clocksource_init(void)
 	clocksource_register(&clocksource_jz);
 
 	//---------------------init sys clock -----------------
-	
-	REG_TCU_OSTCSR = TCU_OSTCSR_PRESCALE16 | TCU_OSTCSR_EXT_EN;
+	REG_OST_OSTCSR = OSTCSR_PRESCALE16 | OSTCSR_EXT_EN;
+	REG_OST_OSTDR = 0xffffffff;
 
-	REG_TCU_OSTCNT = 0;
-	REG_TCU_OSTDR = 0xffffffff;
-	
-	jz_clockaction.dev_id = &clocksource_jz;
+	REG_OST_OSTCNTL = 0;
+	REG_OST_OSTCNTH = 0;
 
-	setup_irq(IRQ_TCU0, &jz_clockaction);
 	REG_TCU_TMCR = TCU_TMCR_OSTMCL; /* unmask match irq */
 	REG_TCU_TSCR = TCU_TSCR_OSTSC;  /* enable timer clock */
 	REG_TCU_TESR = TCU_TESR_OSTST;  /* start counting up */
@@ -165,7 +141,7 @@ static void jz_set_mode(enum clock_event_mode mode,
 static struct clock_event_device jz_clockevent_device = {
 	.name		= "jz-clockenvent",
 	.features	= CLOCK_EVT_FEAT_PERIODIC,
-//	.features	= CLOCK_EVT_FEAT_ONESHOT, /* Jz47XX not support dynamic clock now */
+//	.features	= CLOCK_EVT_FEAT_ONESHOT, /* Jz4740 not support dynamic clock now */
 
 	/* .mult, .shift, .max_delta_ns and .min_delta_ns left uninitialized */
 	.mult		= 1,
@@ -196,10 +172,10 @@ static void __init jz_timer_setup(void)
 	__tcu_stop_counter(JZ_TIMER_TCU_CH);
 //	__cpm_start_tcu();
 	latch = (JZ_TIMER_CLOCK + (HZ>>1)) / HZ;
-	
-	REG_TCU_TMSR = ((1 << JZ_TIMER_TCU_CH) | (1 << (JZ_TIMER_TCU_CH + 16))); 
 
-	REG_TCU_TCSR(JZ_TIMER_TCU_CH) = TCU_TCSR_PRESCALE16 | TCU_TCSR_EXT_EN;
+	REG_TCU_TMSR = ((1 << JZ_TIMER_TCU_CH) | (1 << (JZ_TIMER_TCU_CH + 16)));
+
+	REG_TCU_TCSR(JZ_TIMER_TCU_CH) = OSTCSR_PRESCALE16 | OSTCSR_EXT_EN;
 	REG_TCU_TDFR(JZ_TIMER_TCU_CH) = latch - 1;
 	REG_TCU_TDHR(JZ_TIMER_TCU_CH) = latch + 1;
 	REG_TCU_TCNT(JZ_TIMER_TCU_CH) = 0;
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index e9612215992..607a35f808c 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -75,6 +75,7 @@ obj-$(CONFIG_MIPS32_N32)	+= binfmt_elfn32.o scall64-n32.o signal_n32.o
 obj-$(CONFIG_MIPS32_O32)	+= binfmt_elfo32.o scall64-o32.o
 
 obj-$(CONFIG_KGDB)		+= kgdb.o
+obj-$(CONFIG_KPROBES)		+= kprobes.o
 obj-$(CONFIG_PROC_FS)		+= proc.o
 
 obj-$(CONFIG_64BIT)		+= cpu-bugs64.o
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 0c9d2ff6d79..e5dfbf368e5 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -280,12 +280,12 @@ static inline unsigned long cpu_get_fpu_id(void)
  */
 static inline int __cpu_has_fpu(void)
 {
-	return 0;
-#ifndef CONFIG_SOC_JZ4760
-	return 0; // need fix !!!
-//	return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
-#else
+#if defined(CONFIG_SOC_JZ4760) || defined(CONFIG_SOC_JZ4760B)
+	/* (cpu_get_fpu_id() & 0xff00) no use again in jz4760B */
+	/* so we have to force it to 1 */
 	return 1;
+#else
+	return ((cpu_get_fpu_id() & 0xff00) == 0x0100);
 #endif
 }
 
@@ -967,6 +967,7 @@ __cpuinit void cpu_probe(void)
 		break;
  	case PRID_COMP_INGENIC:
  	case 0xd80000: // used on fpga
+	case 0xd90000: //falcon	
 		cpu_probe_ingenic(c, cpu);
 		break;
 	}
diff --git a/arch/mips/kernel/kprobes.c b/arch/mips/kernel/kprobes.c
new file mode 100644
index 00000000000..695da7805ff
--- /dev/null
+++ b/arch/mips/kernel/kprobes.c
@@ -0,0 +1,569 @@
+/*
+ *  Kernel Probes (KProbes)
+ *  arch/mips/kernel/kprobes.c
+ *
+ *  Copyright 2006 Sony Corp.
+ *  Copyright 2010 Cavium Networks
+ *
+ *  Some portions copied from the powerpc version.
+ *
+ *   Copyright (C) IBM Corporation, 2002, 2004
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; version 2 of the License.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/kprobes.h>
+#include <linux/preempt.h>
+#include <linux/kdebug.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+
+#include <asm/r4kcache.h>
+#include <asm/ptrace.h>
+#include <asm/break.h>
+#include <asm/inst.h>
+#include <asm/sstep.h>
+
+static const union mips_instruction breakpoint_insn = {
+	.b_format = {
+		.opcode = spec_op,
+		.code = BRK_KPROBE_BP,
+		.func = break_op
+	}
+};
+
+static const union mips_instruction breakpoint2_insn = {
+	.b_format = {
+		.opcode = spec_op,
+		.code = BRK_KPROBE_SSTEPBP,
+		.func = break_op
+	}
+};
+
+DEFINE_PER_CPU(struct kprobe *, current_kprobe);
+DEFINE_PER_CPU(struct kprobe_ctlblk, kprobe_ctlblk);
+
+struct kretprobe_blackpoint kretprobe_blacklist[] = {
+	{"add_partial", }, /* unknown reason, preempt error */
+			      
+	{NULL, NULL}	/* Terminator */
+};
+const int kretprobe_blacklist_size = ARRAY_SIZE(kretprobe_blacklist);
+
+void __kprobes _blast_cache_range(unsigned long start, unsigned long end)
+{
+	unsigned long lsize = cpu_dcache_line_size();
+	unsigned long addr = start & ~(lsize - 1);
+	unsigned long aend = (end - 1) & ~(lsize - 1);
+
+	for (; addr <= aend; addr += lsize) {
+		protected_cache_op(Hit_Writeback_Inv_D, addr);
+		protected_cache_op(Hit_Invalidate_I, addr);
+	}
+	SYNC_WB();
+}
+
+#define IS_BREAK(instr)		(((instr) & 0xfc00003f) == 0x0000000d)
+int __kprobes arch_prepare_kprobe(struct kprobe *p)
+{
+	int ret = 0;
+	kprobe_opcode_t insn = *p->addr;
+	int insn_step = test_step(insn.word);
+
+	if ((unsigned long)p->addr & 0x03) {
+		pr_notice("Cann't register kprobe at an unaligned address\n");
+		ret = -EINVAL;
+	} else if (IS_BREAK(insn.word) || IS_ERET(insn.word)) {
+		pr_notice("Cann't register a kprobe on break or eret\n");
+		ret = -EINVAL;
+	} else if (insn_step <0) {
+		printk("Register a kprobe on instruction cann't emulate."
+			"%08x@%p\n",insn.word,p->addr);
+		ret = -EINVAL;
+	} else 	if(insn_step >0) {
+	        //printk("Register a kprobe on jmp/bra %08x@%p\n",insn,p->addr);
+		//ret = -EINVAL;
+	} else 	{
+		kprobe_opcode_t insnp = *(p->addr - 1);
+		//if(insn_is_likely(insn)) {
+		if(0) {
+			pr_notice("Cannot register a kprobe on likely\n");
+			ret = -EINVAL;
+		}
+		if(insn_is_jmpbra(insnp.word)) {
+			pr_notice("Cannot register a kprobe in dalyslot\n");
+			ret = -EINVAL;
+		}
+	}
+	
+
+	/* insn must be on a special executable page on mips. */
+	if (!ret) {
+		p->ainsn.insn = get_insn_slot();
+		if (!p->ainsn.insn) ret = -ENOMEM;
+	}
+
+	if (!ret) {
+		memcpy(p->ainsn.insn, p->addr,
+		       2 * sizeof(kprobe_opcode_t));
+		/* 
+		 * one instruction followed with break SSTEP,
+		 * so to simulate single step
+		 */
+		if(insn_step == 0) {
+			p->ainsn.insn[1] = breakpoint2_insn;
+		} else {
+			/* WARNING("kprobe on jmp/bra\n"); */
+			p->ainsn.insn[2] = breakpoint2_insn;
+		}
+		p->opcode = *p->addr;
+		_blast_cache_range((unsigned long)p->ainsn.insn,
+			(unsigned long)p->ainsn.insn + 3*sizeof(kprobe_opcode_t));
+	}
+
+	return ret;
+}
+
+void __kprobes arch_arm_kprobe(struct kprobe *p)
+{
+	*p->addr = breakpoint_insn;
+	flush_insn_slot(p);
+}
+
+void __kprobes arch_disarm_kprobe(struct kprobe *p)
+{
+	*p->addr = p->opcode;
+	flush_insn_slot(p);
+}
+
+void __kprobes arch_remove_kprobe(struct kprobe *p)
+{
+	free_insn_slot(p->ainsn.insn, 0);
+}
+
+static void save_previous_kprobe(struct kprobe_ctlblk *kcb)
+{
+	kcb->prev_kprobe.kp = kprobe_running();
+	kcb->prev_kprobe.status = kcb->kprobe_status;
+	kcb->prev_kprobe.old_SR = kcb->kprobe_old_SR;
+	kcb->prev_kprobe.saved_SR = kcb->kprobe_saved_SR;
+	kcb->prev_kprobe.saved_epc = kcb->kprobe_saved_epc;
+}
+
+static void restore_previous_kprobe(struct kprobe_ctlblk *kcb)
+{
+	__get_cpu_var(current_kprobe) = kcb->prev_kprobe.kp;
+	kcb->kprobe_status = kcb->prev_kprobe.status;
+	kcb->kprobe_old_SR = kcb->prev_kprobe.old_SR;
+	kcb->kprobe_saved_SR = kcb->prev_kprobe.saved_SR;
+	kcb->kprobe_saved_epc = kcb->prev_kprobe.saved_epc;
+}
+
+static void set_current_kprobe(struct kprobe *p, struct pt_regs *regs,
+			       struct kprobe_ctlblk *kcb)
+{
+	__get_cpu_var(current_kprobe) = p;
+	kcb->kprobe_saved_SR = kcb->kprobe_old_SR = (regs->cp0_status & ST0_IE);
+	kcb->kprobe_saved_epc = regs->cp0_epc;
+}
+
+static void prepare_singlestep(struct kprobe *p, struct pt_regs *regs)
+{
+	struct kprobe_ctlblk *kcb = get_kprobe_ctlblk();
+	kprobe_opcode_t insn = p->ainsn.insn[0];
+	int ret = emulate_step(regs, insn.word);
+
+	if(ret != 0) {
+		if(ret == 1) /* bra/jmp instruction jumped */
+			kcb->kprobe_saved_epc = regs->cp0_epc;
+		else
+			kcb->kprobe_saved_epc += 4;
+		regs->cp0_epc = (unsigned long)(&p->ainsn.insn[1]);
+	} else {
+		regs->cp0_epc = (unsigned long)(&p->ainsn.insn[0]);
+	}
+	regs->cp0_status &= ~ST0_IE;
+}
+
+static int __kprobes kprobe_handler(struct pt_regs *regs)
+{
+	struct kprobe *p;
+	int ret = 0;
+	kprobe_opcode_t *addr;
+	struct kprobe_ctlblk *kcb;
+
+	addr = (kprobe_opcode_t *) regs->cp0_epc;
+
+	/*
+	 * We don't want to be preempted for the entire
+	 * duration of kprobe processing
+	 */
+	preempt_disable();
+	kcb = get_kprobe_ctlblk();
+
+	/* Check we're not actually recursing */
+	if (kprobe_running()) {
+		p = get_kprobe(addr);
+		if (p) {
+			if (kcb->kprobe_status == KPROBE_HIT_SS &&
+			    p->ainsn.insn->word == breakpoint_insn.word) {
+				regs->cp0_status &= ~ST0_IE;
+				regs->cp0_status |= kcb->kprobe_saved_SR;
+				goto no_kprobe;
+			}
+			/*
+			 * We have reentered the kprobe_handler(), since
+			 * another probe was hit while within the handler.
+			 * We here save the original kprobes variables and
+			 * just single step on the instruction of the new probe
+			 * without calling any user handlers.
+			 */
+			save_previous_kprobe(kcb);
+			set_current_kprobe(p, regs, kcb);
+			kprobes_inc_nmissed_count(p);
+			prepare_singlestep(p, regs);
+			kcb->kprobe_status = KPROBE_REENTER;
+			return 1;
+		} else {
+			if (addr->word != breakpoint_insn.word) {
+				/*
+				 * The breakpoint instruction was removed by
+				 * another cpu right after we hit, no further
+				 * handling of this interrupt is appropriate
+				 */
+				ret = 1;
+				goto no_kprobe;
+			}
+			p = __get_cpu_var(current_kprobe);
+			if (p->break_handler && p->break_handler(p, regs))
+				goto ss_probe;
+		}
+		goto no_kprobe;
+	}
+
+	p = get_kprobe(addr);
+	if (!p) {
+		if (addr->word != breakpoint_insn.word) {
+			/*
+			 * The breakpoint instruction was removed right
+			 * after we hit it.  Another cpu has removed
+			 * either a probepoint or a debugger breakpoint
+			 * at this address.  In either case, no further
+			 * handling of this interrupt is appropriate.
+			 */
+			ret = 1;
+		}
+		/* Not one of ours: let kernel handle it */
+		goto no_kprobe;
+	}
+
+	set_current_kprobe(p, regs, kcb);
+	kcb->kprobe_status = KPROBE_HIT_ACTIVE;
+
+	if (p->pre_handler && p->pre_handler(p, regs)) {
+		/* handler has already set things up, so skip ss setup */
+		return 1;
+	}
+
+ss_probe:
+	prepare_singlestep(p, regs);
+	kcb->kprobe_status = KPROBE_HIT_SS;
+	return 1;
+
+no_kprobe:
+	preempt_enable_no_resched();
+	return ret;
+
+}
+
+/*
+ * Called after single-stepping.  p->addr is the address of the
+ * instruction whose first byte has been replaced by the "break 0"
+ * instruction.  To avoid the SMP problems that can occur when we
+ * temporarily put back the original opcode to single-step, we
+ * single-stepped a copy of the instruction.  The address of this
+ * copy is p->ainsn.insn.
+ *
+ * This function prepares to return from the post-single-step
+ * breakpoint trap.
+ */
+static void __kprobes resume_execution(struct kprobe *p,
+				       struct pt_regs *regs,
+				       struct kprobe_ctlblk *kcb)
+{
+	unsigned long orig_epc = kcb->kprobe_saved_epc;
+	int is_jmp = p->ainsn.insn[1].word != breakpoint2_insn.word;
+	if(is_jmp)
+		regs->cp0_epc = orig_epc;
+	else
+		regs->cp0_epc = orig_epc + 4;
+}
+
+static inline int post_kprobe_handler(struct pt_regs *regs)
+{
+	struct kprobe *cur = kprobe_running();
+	struct kprobe_ctlblk *kcb = get_kprobe_ctlblk();
+
+	if (!cur)
+		return 0;
+
+	if ((kcb->kprobe_status != KPROBE_REENTER) && cur->post_handler) {
+		kcb->kprobe_status = KPROBE_HIT_SSDONE;
+		cur->post_handler(cur, regs, 0);
+	}
+
+	resume_execution(cur, regs, kcb);
+
+	regs->cp0_status |= kcb->kprobe_saved_SR;
+
+	/* Restore back the original saved kprobes variables and continue. */
+	if (kcb->kprobe_status == KPROBE_REENTER) {
+		restore_previous_kprobe(kcb);
+		goto out;
+	}
+	reset_current_kprobe();
+out:
+	preempt_enable_no_resched();
+
+	return 1;
+}
+
+static inline int kprobe_fault_handler(struct pt_regs *regs, int trapnr)
+{
+	struct kprobe *cur = kprobe_running();
+	struct kprobe_ctlblk *kcb = get_kprobe_ctlblk();
+
+	if (cur->fault_handler && cur->fault_handler(cur, regs, trapnr))
+		return 1;
+
+	if (kcb->kprobe_status & KPROBE_HIT_SS) {
+		resume_execution(cur, regs, kcb);
+		regs->cp0_status |= kcb->kprobe_old_SR;
+
+		reset_current_kprobe();
+		preempt_enable_no_resched();
+	}
+	return 0;
+}
+
+/*
+ * Wrapper routine for handling exceptions.
+ */
+int __kprobes kprobe_exceptions_notify(struct notifier_block *self,
+				       unsigned long val, void *data)
+{
+
+	struct die_args *args = (struct die_args *)data;
+	int ret = NOTIFY_DONE;
+
+	switch (val) {
+	case DIE_BREAK:
+		if (kprobe_handler(args->regs))
+			ret = NOTIFY_STOP;
+		break;
+	case DIE_SSTEPBP:
+		if (post_kprobe_handler(args->regs))
+			ret = NOTIFY_STOP;
+		break;
+
+	case DIE_PAGE_FAULT:
+		/* kprobe_running() needs smp_processor_id() */
+		preempt_disable();
+
+		if (kprobe_running()
+		    && kprobe_fault_handler(args->regs, args->trapnr))
+			ret = NOTIFY_STOP;
+		preempt_enable();
+		break;
+	default:
+		break;
+	}
+	return ret;
+}
+
+int __kprobes setjmp_pre_handler(struct kprobe *p, struct pt_regs *regs)
+{
+	struct jprobe *jp = container_of(p, struct jprobe, kp);
+	struct kprobe_ctlblk *kcb = get_kprobe_ctlblk();
+
+	kcb->jprobe_saved_regs = *regs;
+	kcb->jprobe_saved_sp = regs->regs[29];
+
+	memcpy(kcb->jprobes_stack, (void *)kcb->jprobe_saved_sp,
+	       MIN_JPROBES_STACK_SIZE(kcb->jprobe_saved_sp));
+
+	regs->cp0_epc = (unsigned long)(jp->entry);
+
+	return 1;
+}
+
+/* Defined in the inline asm below. */
+void jprobe_return_end(void);
+
+void __kprobes jprobe_return(void)
+{
+	/* Assembler quirk necessitates this '0,code' business.  */
+	asm volatile(
+		"break 0,%0\n\t"
+		".globl jprobe_return_end\n"
+		"jprobe_return_end:\n"
+		: : "n" (BRK_KPROBE_BP) : "memory");
+}
+
+int __kprobes longjmp_break_handler(struct kprobe *p, struct pt_regs *regs)
+{
+	struct kprobe_ctlblk *kcb = get_kprobe_ctlblk();
+
+	if (regs->cp0_epc >= (unsigned long)jprobe_return &&
+	    regs->cp0_epc <= (unsigned long)jprobe_return_end) {
+		*regs = kcb->jprobe_saved_regs;
+		memcpy((void *)kcb->jprobe_saved_sp, kcb->jprobes_stack,
+		       MIN_JPROBES_STACK_SIZE(kcb->jprobe_saved_sp));
+		preempt_enable_no_resched();
+
+		return 1;
+	}
+	return 0;
+}
+
+/*
+ * Function return probe trampoline:
+ *	- init_kprobes() establishes a probepoint here
+ *	- When the probed function returns, this probe causes the
+ *	  handlers to fire
+ */
+static void __used kretprobe_trampoline_holder(void)
+{
+	asm volatile(
+		".set push\n\t"
+		/* Keep the assembler from reordering and placing JR here. */
+		".set noreorder\n\t"
+		"nop\n\t"
+		".global kretprobe_trampoline\n"
+		"kretprobe_trampoline:\n\t"
+		"nop\n\t"
+		".set pop"
+		: : : "memory");
+}
+
+void kretprobe_trampoline(void);
+
+void __kprobes arch_prepare_kretprobe(struct kretprobe_instance *ri,
+				      struct pt_regs *regs)
+{
+	ri->ret_addr = (kprobe_opcode_t *) regs->regs[31];
+
+	/* Replace the return addr with trampoline addr */
+	regs->regs[31] = (unsigned long)kretprobe_trampoline;
+}
+
+/*
+ * Called when the probe at kretprobe trampoline is hit
+ */
+static int __kprobes trampoline_probe_handler(struct kprobe *p,
+						struct pt_regs *regs)
+{
+	struct kretprobe_instance *ri = NULL;
+	struct hlist_head *head, empty_rp;
+	struct hlist_node *node, *tmp;
+	unsigned long flags, orig_ret_address = 0;
+	unsigned long trampoline_address = (unsigned long)kretprobe_trampoline;
+
+	INIT_HLIST_HEAD(&empty_rp);
+	kretprobe_hash_lock(current, &head, &flags);
+
+	/*
+	 * It is possible to have multiple instances associated with a given
+	 * task either because an multiple functions in the call path
+	 * have a return probe installed on them, and/or more than one return
+	 * return probe was registered for a target function.
+	 *
+	 * We can handle this because:
+	 *     - instances are always inserted at the head of the list
+	 *     - when multiple return probes are registered for the same
+	 *       function, the first instance's ret_addr will point to the
+	 *       real return address, and all the rest will point to
+	 *       kretprobe_trampoline
+	 */
+	hlist_for_each_entry_safe(ri, node, tmp, head, hlist) {
+		if (ri->task != current)
+			/* another task is sharing our hash bucket */
+			continue;
+
+		if (ri->rp && ri->rp->handler)
+			ri->rp->handler(ri, regs);
+
+		orig_ret_address = (unsigned long)ri->ret_addr;
+		recycle_rp_inst(ri, &empty_rp);
+
+		if (orig_ret_address != trampoline_address)
+			/*
+			 * This is the real return address. Any other
+			 * instances associated with this task are for
+			 * other calls deeper on the call stack
+			 */
+			break;
+	}
+
+	kretprobe_assert(ri, orig_ret_address, trampoline_address);
+	instruction_pointer(regs) = orig_ret_address;
+
+	reset_current_kprobe();
+	kretprobe_hash_unlock(current, &flags);
+	preempt_enable_no_resched();
+
+	hlist_for_each_entry_safe(ri, node, tmp, &empty_rp, hlist) {
+		hlist_del(&ri->hlist);
+		kfree(ri);
+	}
+	/*
+	 * By returning a non-zero value, we are telling
+	 * kprobe_handler() that we don't want the post_handler
+	 * to run (and have re-enabled preemption)
+	 */
+	return 1;
+}
+
+int __kprobes arch_trampoline_kprobe(struct kprobe *p)
+{
+	if (p->addr == (kprobe_opcode_t *)kretprobe_trampoline)
+		return 1;
+
+	return 0;
+}
+
+static struct kprobe trampoline_p = {
+	.addr = (kprobe_opcode_t *)kretprobe_trampoline,
+	.pre_handler = trampoline_probe_handler
+};
+
+int __init arch_init_kprobes(void)
+{
+	return register_kprobe(&trampoline_p);
+}
+
+
+
+/*
+ * Used for Systemtap mips support. stack-mips.c
+ */
+#include <asm/stacktrace.h>
+unsigned long _mips_unwind_stack(struct task_struct *task, unsigned long *sp,
+			   unsigned long pc, unsigned long *ra)
+{
+	if(!task) task = current;
+	if(!task) BUG();
+	return unwind_stack(task,sp,pc,ra);
+}
+EXPORT_SYMBOL(_mips_unwind_stack);
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 08f1edf355e..443e1a219df 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -713,7 +713,8 @@ static void do_trap_or_bp(struct pt_regs *regs, unsigned int code,
 	switch (code) {
 	case BRK_OVERFLOW:
 	case BRK_DIVZERO:
-		scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
+		scnprintf(b, sizeof(b), "%s(%d) instruction in kernel code"
+			  , str, code);
 		die_if_kernel(b, regs);
 		if (code == BRK_DIVZERO)
 			info.si_code = FPE_INTDIV;
@@ -744,7 +745,8 @@ static void do_trap_or_bp(struct pt_regs *regs, unsigned int code,
 		force_sig(SIGTRAP, current);
 		break;
 	default:
-		scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
+		scnprintf(b, sizeof(b), "%s(%d) instruction in kernel code"
+			  , str, code);
 		die_if_kernel(b, regs);
 		force_sig(SIGTRAP, current);
 	}
@@ -767,6 +769,26 @@ asmlinkage void do_bp(struct pt_regs *regs)
 	if (bcode >= (1 << 10))
 		bcode >>= 10;
 
+	/*
+	 * notify the kprobe handlers, if instruction is likely to
+	 * pertain to them.
+	 */
+#define regs_to_trapnr(regs) ((regs->cp0_cause >> 2) & 0x1f)
+	switch (bcode) {
+	case BRK_KPROBE_BP:
+		if (notify_die(DIE_BREAK, "debug", regs, bcode, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
+			return;
+		else
+			break;
+	case BRK_KPROBE_SSTEPBP:
+		if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
+			return;
+		else
+			break;
+	default:
+		break;
+	}
+
 	do_trap_or_bp(regs, bcode, "Break");
 	return;
 
diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile
index 2adead5a8a3..0324948d3e7 100644
--- a/arch/mips/lib/Makefile
+++ b/arch/mips/lib/Makefile
@@ -29,5 +29,6 @@ obj-$(CONFIG_CPU_TX49XX)	+= dump_tlb.o
 obj-$(CONFIG_CPU_VR41XX)	+= dump_tlb.o
 obj-$(CONFIG_CPU_CAVIUM_OCTEON)	+= dump_tlb.o
 
+obj-$(CONFIG_KPROBES)	+= sstep.o
 # libgcc-style stuff needed in the kernel
 obj-y += ashldi3.o ashrdi3.o cmpdi2.o lshrdi3.o ucmpdi2.o
diff --git a/arch/mips/lib/sstep.c b/arch/mips/lib/sstep.c
new file mode 100644
index 00000000000..622a25cad34
--- /dev/null
+++ b/arch/mips/lib/sstep.c
@@ -0,0 +1,414 @@
+/*
+ * Single-step support.
+ *
+ * Copyright (C) 2010 zhiping zhong <zpzhong@ingenic.cn>, JZ
+ * Base on a copy of powerpc/lib/sstep.c 
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include <linux/kernel.h>
+#include <linux/kprobes.h>
+#include <linux/ptrace.h>
+#include <asm/inst.h>
+#include <asm/sstep.h>
+#include <asm/processor.h>
+
+extern char system_call_common[];
+
+
+/*
+ * Emulate instructions that cause a transfer of control.
+ * Returns -1 if the instruction is one that should not be stepped,
+ * returns 0 if the step was not emulated, and need to single stepped,
+ * returns 1 if the step was emulated, and need delayslot single stepped,
+ * returns 2 if do not need to execute delayslot instruction,
+ * such as a likely instruction but no branch.
+ * such as break, eret and all cp0/float instructions.
+ * Here only jmp/branch instruction was emulated.
+ */
+int __kprobes emulate_step(struct pt_regs *regs, unsigned int instr)
+{
+	unsigned int opcode, rs, rt, fun;
+	unsigned long int imm;
+	long int *gpr = (long int *)regs->regs;
+	unsigned long *ugpr = regs->regs;
+	union mips_instruction inst;
+
+	int branch = 0, likely = 0;
+	inst.word = instr;
+	opcode = inst.r_format.opcode;
+	rs  = inst.r_format.rs;
+	rt  = inst.r_format.rt;
+	switch (opcode) {
+	case 0:
+		fun = inst.r_format.func;
+		/*
+		 * jr rs , but mips16e instruction
+		 * (jr.hb rs) not support 
+		 */
+		if(fun == 8) {
+			if(inst.r_format.re == 16)
+				return -1;
+			regs->cp0_epc = ugpr[rs];
+			return 1;
+		}
+		/*
+		 * jalr rs , but mips16e instruction
+		 * (jalr.hb rs) not support 
+		 */
+		if(fun == 9) {
+			int rd = inst.r_format.rd;
+			if(inst.r_format.re == 16)
+				return -1;
+			ugpr[rd] = regs->cp0_epc + 8;
+			regs->cp0_epc = ugpr[rs];
+			return 1;
+		}
+		/* syscall, break, sdbbp not support */
+		if(fun > 11 && fun < 16)
+			return -1;
+		break;
+	case 1:	/* b */
+		fun = (instr >> 16) & 0x1f;
+		switch(fun) {
+		case 0: /* bltz */
+			if(gpr[rs] < 0) branch = 1;
+			goto normal;
+		case 1: /* bgez */
+			if(gpr[rs] >= 0) branch = 1;
+			goto normal;
+		case 2: /* bltzl */
+			if(gpr[rs] < 0) branch = 1;
+			goto likely;
+		case 3: /* bgezl */
+			if(gpr[rs] >= 0) branch = 1;
+			goto likely;
+		case 16: /* bltzal */
+			if(gpr[rs] < 0) branch = 1;
+			goto link;
+		case 17: /* bgezal */
+			if(gpr[rs] >= 0) branch = 1;
+			goto link;
+		case 18: /* bltzall */
+			if(gpr[rs] < 0) branch = 1;
+			goto likely_link;
+		case 19: /* bgezall */
+			if(gpr[rs] >= 0) branch = 1;
+			goto likely_link;
+		default: /* trap inst*/ 
+			if(fun == 31) return -1; /* synci */
+			return 0;
+		}
+	case 3: /* jal */
+		regs->regs[31] = regs->cp0_epc + 8;
+	case 2: /* j */
+		imm = (instr << 2) & 0x0ffffffc;
+		regs->cp0_epc &= 0xf0000000;
+		regs->cp0_epc |= imm;
+		return 1;
+	case 4: /* beq */
+		if(gpr[rs] == gpr[rt]) branch = 1;
+		goto normal;
+	case 5: /* bne */
+		if(gpr[rs] != gpr[rt]) branch = 1;
+		goto normal;
+	case 6: /* blez */
+		if(gpr[rs] <= 0) branch = 1;
+		goto normal;
+	case 7: /* bgtz */
+		if(gpr[rs] >  0) branch = 1;
+		goto normal;
+	case 16: /* cp0 inst only support mfc0/mtc0 */
+		if(rs == 0 || rs == 4)
+			return 0;
+	case 17: /* float inst not support */
+		return -1;
+		
+	case 20: /* beql */
+		if(gpr[rs] == gpr[rt]) branch = 1;
+		goto likely;
+	case 21: /* bnel */
+		if(gpr[rs] != gpr[rt]) branch = 1;
+		goto likely;
+	case 22: /* blezl */
+		if(gpr[rs] <= 0) branch = 1;
+		goto likely;
+	case 23: /* bgtzl */
+		if(gpr[rs] >  0) branch = 1;
+		goto likely;
+	case 29: /* jalx */
+		return -1;
+	default:
+		return 0;
+	}
+	return 0;
+
+likely:
+	likely = 1;
+	goto normal;
+likely_link:
+	likely = 1;
+link:
+	if(branch)
+		regs->regs[31] = regs->cp0_epc + 8;
+normal:
+	if(branch) {
+		long int offset = (long int)((short)(instr & 0xffff));
+		offset <<= 2;
+		regs->cp0_epc += offset + 4;
+		likely = 0;
+	} else {
+		regs->cp0_epc += 4;
+		/* if likely and not branch, invalid delayslot */
+		if (likely) regs->cp0_epc += 4;
+	}
+	
+	/* emulate delayslot if branch */
+	return 2 - branch;
+}
+
+int __kprobes test_step(unsigned int instr)
+{
+	struct pt_regs regs; 
+	return emulate_step(&regs , instr);
+}
+
+/*
+ * jmp instruction return 1, branch instruction return 2
+ * other branch instruction return 3, not jmp/branch return 0
+ */
+int __kprobes insn_is_jmpbra(unsigned int instr)
+{
+	unsigned int opcode, rs, rt, fun;
+
+	int type = 0;
+	opcode = instr >> 26;
+	rs  = (instr >> 21) & 0x1f;
+	rt  = (instr >> 16) & 0x1f;
+	switch (opcode) {
+	case 0:
+		fun = instr & 0x3f;
+		if(fun == 9 || fun == 8)
+			type = 1;
+		break;
+	case 1:	/* b */
+		fun = (instr >> 16) & 0x1f;
+		switch(fun) {
+		case 0: /* bltz */
+		case 1: /* bgez */
+		case 2: /* bltzl */
+		case 3: /* bgezl */
+		case 16: /* bltzal */
+		case 17: /* bgezal */
+		case 18: /* bltzall */
+		case 19: /* bgezall */
+			type = 2;
+			break;
+		default: /* trap inst*/ 
+			break;
+		}
+	case 3: /* jal */
+	case 2: /* j */
+		type = 1;
+	case 4: /* beq */
+	case 5: /* bne */
+	case 6: /* blez */
+	case 7: /* bgtz */
+		type = 2;
+		break;
+	case 16: /* cp0 inst */
+		fun = (instr >> 16) & 0x1f;
+		if(fun == 8)  /* bc0f/t[l] */
+			type = 3;
+		break;
+	case 17: /* float inst */
+		fun = (instr >> 16) & 0x1f;
+		/* bc1f/t[l] bc1any2/4 f/t*/
+		if(fun == 8 || fun == 9 || fun == 10)  
+			type = 3;
+		break;
+	case 18: /* cp2 inst */
+		fun = (instr >> 16) & 0x1f;
+		if(fun == 8)  /* bc2f/t[l] */
+			type = 3;
+		break;
+		
+	case 20: /* beql */
+	case 21: /* bnel */
+	case 22: /* blezl */
+	case 23: /* bgtzl */
+		type = 2;
+		break;
+	default:
+		break;
+	}
+	return type;
+
+}
+
+#ifdef __TEST_EMULATE_STEP
+enum {
+	ltz = 8 + 1,
+	lez = 8 + 3,
+	eqz = 8 + 2,
+	gez = 8 + 6,
+	gtz = 8 + 4,
+	eq = 2,
+	ne = 5,
+	any = 7,
+};
+struct test_st {
+	int cmp_type;
+	unsigned int inst;
+	int link, likely;
+	char *name;
+};
+#define B1(x) ((1<<26) | ((x)<<16))
+#define B2(x) ( (x)<<26 )
+struct test_st __initdata testb[] = {
+	{ ltz, B1(0), 0, 0, "bltz"}, /* bltz */
+	{ gez, B1(1), 0, 0, "bgez"}, /* bgez */
+	{ ltz, B1(2), 0, 1, "bltzl"}, /* bltzl */
+	{ gez, B1(3), 0, 1, "bgezl"}, /* bgezl */
+
+	{ ltz, B1(16), 1, 0, "bltzal"}, /* bltzal */
+	{ gez, B1(17), 1, 0, "bgezal"}, /* bgezal */
+	{ ltz, B1(18), 1, 1, "bltzall"}, /* bltzall */
+	{ gez, B1(19), 1, 1, "bgezall"}, /* bgezall */
+
+	{ eq,  B2(4), 0, 0, "beq"}, /* beq */
+	{ ne,  B2(5), 0, 0, "bne"}, /* bne */
+	{ lez, B2(6), 0, 0, "blez"}, /* blez */
+	{ gtz, B2(7), 0, 0, "bgtz"}, /* bgtz */
+
+	{ eq,  B2(20), 0, 1, "beql"}, /* beql */
+	{ ne,  B2(21), 0, 1, "bnel"}, /* bnel */
+	{ lez, B2(22), 0, 1, "blezl"}, /* blezl */
+	{ gtz, B2(23), 0, 1, "bgtzl"}, /* bgtzl */
+
+	{ 0, 0, 0, 0 }
+};
+#define J1(x) (x)
+#define J2(x) ( (x) << 26 )
+struct test_st __initdata testj[] = {
+	{ any,  J1(8), 0, 0, "jr"}, /* jr */
+	{ any,  J1(9), 1, 0, "jalr"}, /* jalr */
+	{ any,  J2(2), 0, 0, "j"}, /* j */
+	{ any,  J2(3), 1, 0, "jal"}, /* jal */
+
+	{ 0, 0, 0, 0 }
+};
+static inline int __init judge_cmp(int cmp_type,int vs,int vt)
+{
+	int cmp = 0;
+	cmp += vs <  vt ? 1: 0;
+	cmp += vs == vt ? 2: 0;
+	cmp += vs >  vt ? 4: 0;
+	return (cmp_type & 7) & cmp;
+}
+
+#define EPC (0x80001000)
+int __init test_emulate_step(void)
+{
+	struct test_st *ptest = &testb[0];
+	struct pt_regs regs; 
+	union mips_instruction inst;
+	int vals[3] = { -1, 0, 1};
+	int rs = 5, rt = 7;
+	int i, ret, jmp;
+	
+again:
+	inst.word = ptest->inst;
+	for(i=0;i<3;i++) {
+		int vrs,vrt;
+		vrs = vals[i];
+		vrt = 0;
+		regs.regs[0] = 0;
+		regs.regs[31] = 0;
+		regs.regs[rs] = (unsigned int)vrs;
+		regs.regs[rt] = (unsigned int)vrt;
+		regs.cp0_epc = EPC;
+
+		if(inst.i_format.opcode != 1)
+			inst.i_format.rt = rt;
+		inst.i_format.rs = rs;
+		inst.i_format.simmediate = vals[i];
+		
+		ret = emulate_step(&regs,inst.word);
+		jmp = judge_cmp(ptest->cmp_type,vrs,vrt);
+	
+		if((jmp && ret != 1) || (!jmp && ret != 2)) {
+			printk("[SSTEP]" "ret(%d) jmp(%d) err at %s %d\n"
+			       ,ret,jmp,ptest->name,i);
+			return -1;
+		}
+		if(jmp) {
+			if(regs.cp0_epc != EPC +4 +vals[i]*4) {
+				printk("[SSTEP]" "epc jmp err at %s %d\n"
+				       ,ptest->name,i);
+				return -1;
+			}
+		} else {
+			int off = ptest->likely? 8: 4;
+			if(regs.cp0_epc != EPC + off) {
+				printk("[SSTEP]" "epc nojmp err at %s %d\n"
+				       ,ptest->name,i);
+				return -1;
+			}
+		}
+		if((( ptest->link &&  jmp) && regs.regs[31] != EPC+8) || 
+		   ((!ptest->link || !jmp) && regs.regs[31] != 0) )
+		{
+			printk("[SSTEP]" "ra link err at %s %d\n"
+			       ,ptest->name,i);
+			return -1;
+		}
+
+	}
+	ptest ++;
+	if(ptest->inst != 0)
+		goto again;
+
+#define TARGET (0x80020004)
+	ptest = &testj[0];
+	do {
+		inst.word = ptest->inst;
+		regs.regs[0] = 0;
+		regs.regs[31] = 0;
+		regs.cp0_epc = EPC;
+		if(inst.j_format.opcode == 0) {
+			inst.r_format.rs = rs;
+			regs.regs[rs] = TARGET;
+			if(inst.r_format.func == 9)
+				inst.r_format.rd = 31;
+		} else {
+			inst.j_format.target = (TARGET & 0x03ffffff)>>2;
+		}
+		
+		ret = emulate_step(&regs, inst.word);
+		
+		if(ret != 1) {
+			printk("[SSTEP]" "ret err at %s\n",ptest->name);
+			return -1;
+		}
+		if(regs.cp0_epc != TARGET) {
+			printk("[SSTEP]" "epc jmp err at %s\n",ptest->name);
+			return -1;
+		}
+		if((ptest->link && regs.regs[31] != EPC+8) || 
+		   (!ptest->link && regs.regs[31] != 0) )
+		{
+			printk("[SSTEP]" "ra link err at %s\n",ptest->name);
+			return -1;
+		}
+		ptest ++;
+	} while(ptest->inst != 0);
+	
+	printk("[SSTEP]emulate_step() test passed.\n");
+	return 0;
+}
+
+#endif
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 433f4a688d2..9f297302345 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -551,6 +551,22 @@ static void r4k_flush_data_cache_page(unsigned long addr)
 			        1);
 }
 
+void (*flush_insn_cache_page)(unsigned long addr);
+
+static inline void local_r4k_flush_insn_cache_page(void * addr)
+{
+	r4k_blast_icache_page((unsigned long) addr);
+}
+
+static void r4k_flush_insn_cache_page(unsigned long addr)
+{
+	if (in_atomic())
+		local_r4k_flush_insn_cache_page((void *)addr);
+	else
+		r4k_on_each_cpu(local_r4k_flush_insn_cache_page, (void *) addr,
+			        1);
+}
+
 struct flush_icache_range_args {
 	unsigned long start;
 	unsigned long end;
@@ -1438,6 +1454,7 @@ void __cpuinit r4k_cache_init(void)
 	flush_data_cache_page	= r4k_flush_data_cache_page;
 	flush_icache_range	= r4k_flush_icache_range;
 	local_flush_icache_range	= local_r4k_flush_icache_range;
+	flush_insn_cache_page	= r4k_flush_insn_cache_page;
 
 #if defined(CONFIG_DMA_NONCOHERENT)
 	if (coherentio) {
diff --git a/arch/mips/mm/fault.c b/arch/mips/mm/fault.c
index f956ecbb813..81d5c263fbe 100644
--- a/arch/mips/mm/fault.c
+++ b/arch/mips/mm/fault.c
@@ -18,6 +18,7 @@
 #include <linux/smp.h>
 #include <linux/vt_kern.h>		/* For unblank_screen() */
 #include <linux/module.h>
+#include <linux/kprobes.h>
 
 #include <asm/branch.h>
 #include <asm/mmu_context.h>
@@ -25,13 +26,15 @@
 #include <asm/uaccess.h>
 #include <asm/ptrace.h>
 #include <asm/highmem.h>		/* For VMALLOC_END */
+#include <linux/kdebug.h>
+
 
 /*
  * This routine handles page faults.  It determines the address,
  * and the problem, and then passes it off to one of the appropriate
  * routines.
  */
-asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long write,
+asmlinkage void __kprobes do_page_fault(struct pt_regs *regs, unsigned long write,
 			      unsigned long address)
 {
 	struct vm_area_struct * vma = NULL;
@@ -47,6 +50,17 @@ asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long write,
 	       field, regs->cp0_epc);
 #endif
 
+#ifdef CONFIG_KPROBES
+	/*
+	 * This is to notify the fault handler of the kprobes.  The
+	 * exception code is redundant as it is also carried in REGS,
+	 * but we pass it anyhow.
+	 */
+	if (notify_die(DIE_PAGE_FAULT, "page fault", regs, -1,
+		       (regs->cp0_cause >> 2) & 0x1f, SIGSEGV) == NOTIFY_STOP)
+		return;
+#endif
+
 	info.si_code = SEGV_MAPERR;
 
 	/*
diff --git a/drivers/char/jzchar/Kconfig b/drivers/char/jzchar/Kconfig
index fbcecdb9cf9..2435008b4c5 100644
--- a/drivers/char/jzchar/Kconfig
+++ b/drivers/char/jzchar/Kconfig
@@ -3,11 +3,11 @@
 #
 
 menu "JZSOC char device support"
-	depends on SOC_JZ4740 || SOC_JZ4730 || SOC_JZ4750 || SOC_JZ4750D || SOC_JZ4760
+	depends on SOC_JZ4740 || SOC_JZ4730 || SOC_JZ4750 || SOC_JZ4750D || SOC_JZ4760 || SOC_JZ4760B || SOC_JZ4810
 
 config JZCHAR
 	tristate 'JzSOC char device support'
-	depends on SOC_JZ4740 || SOC_JZ4730 || SOC_JZ4750 || SOC_JZ4750D || SOC_JZ4760
+	depends on SOC_JZ4740 || SOC_JZ4730 || SOC_JZ4750 || SOC_JZ4750D || SOC_JZ4760 || SOC_JZ4760B || SOC_JZ4810 
 
 config JZ_SIMPLE_I2C
 	tristate 'Ingenic Simple I2C Userspace Driver'
@@ -54,11 +54,11 @@ config JZ_OW
 
 config JZ_TCSM
 	tristate 'JZ TCSM support' 
-	depends on JZCHAR && (SOC_JZ4750 || SOC_JZ4750D || SOC_JZ4760)
+	depends on JZCHAR && (SOC_JZ4750 || SOC_JZ4750D || SOC_JZ4760 || SOC_JZ4760B || SOC_JZ4810)
 
 config JZ_TSSI
 	tristate 'JZ MPEG2-TS interface support' 
-	depends on JZCHAR && (SOC_JZ4750 || SOC_JZ4750D)
+	depends on JZCHAR && (SOC_JZ4750 || SOC_JZ4750D || SOC_JZ4760 || SOC_JZ4760B || SOC_JZ4810)
 
 endmenu
 
diff --git a/drivers/char/jzchar/jz_tssi.c b/drivers/char/jzchar/jz_tssi.c
index 24f72dcbbe0..1f467943f05 100644
--- a/drivers/char/jzchar/jz_tssi.c
+++ b/drivers/char/jzchar/jz_tssi.c
@@ -14,6 +14,7 @@
 #include <linux/init.h>
 #include <linux/fs.h>
 #include <linux/miscdevice.h>
+#include <linux/wait.h>
 #include <linux/delay.h>
 #include <linux/poll.h>
 #include <linux/string.h>
@@ -30,16 +31,16 @@ MODULE_AUTHOR("Lucifer Liu <yliu@ingenic.cn>");
 MODULE_DESCRIPTION("Ingenic MPEG2-TS interface Driver");
 MODULE_LICENSE("GPL");
 
-#define TSSI_NAME "JZ MPEG2-TS SI"
+#define TSSI_NAME "tssi"
 #define TSSI_MINOR 204         /* MAJOR: 10, MINOR: 16 */
 #define TSSI_IRQ   IRQ_TSSI
 #define PFX        TSSI_NAME
-#define RING_BUF_NUM  100
+#define RING_BUF_NUM 4
+#define OUT_BUF_LEN	10	/* 4M */
+#define IN_BUF_LEN	9	/* 2^9*4K=2M */
 
-#define USE_DMA
-#define TRIG_PIN    ( 32 * 2 + 15 )
-#define DMA_ID_TSSI 5
 //#define JZ_TSSI_DEBUG
+#define DEBUG 0
 
 #ifdef JZ_TSSISI_DEBUG
 #define dbg(format, arg...) printk(KERN_DEBUG PFX ": " format "\n" , ## arg)
@@ -51,154 +52,73 @@ MODULE_LICENSE("GPL");
 #define warn(format, arg...) printk(KERN_WARNING PFX ": " format "\n" , ## arg)
 
 static struct jz_tssi_t jz_tssi_g;
-static struct jz_tssi_buf_ring_t jz_tssi_ring_g;
-static int tssi_dma_reinit(int dma_chan, unsigned char *dma_buf, int size);
+static struct jz_tssi_buf_ring jz_tssi_ring_g;
+static struct jz_tssi_desc_t g_tssi_desc0;
+static struct jz_tssi_desc_t g_tssi_desc1;
+static unsigned char *in_buf0, *in_buf1;
+static unsigned char *out_buf;
 
-static void print_reg( void )
+static void dump_tssi_regs( void )
 {
-	printk("REG_TSSI_ENA   %8x \n ",    REG8( TSSI_ENA ));
-	printk("REG_TSSI_CFG   %8x \n ",    REG16( TSSI_CFG ));
-	printk("REG_TSSI_CTRL  %8x \n ",    REG8( TSSI_CTRL ));
-	printk("REG_TSSI_STAT  %8x \n ",    REG8( TSSI_STAT ));
-	printk("REG_TSSI_FIFO  %8x \n ",    REG32( TSSI_FIFO ));
-	printk("REG_TSSI_PEN   %8x \n ",    REG32( TSSI_PEN ));
-	printk("REG_TSSI_PID0  %8x \n ",    REG32( TSSI_PID0 ));
-	printk("REG_TSSI_PID1  %8x \n ",    REG32( TSSI_PID1 ));
-	printk("REG_TSSI_PID2  %8x \n ",    REG32( TSSI_PID2 ));
-	printk("REG_TSSI_PID3  %8x \n ",    REG32( TSSI_PID3 ));
-	printk("REG_TSSI_PID4  %8x \n ",    REG32( TSSI_PID4 ));
-	printk("REG_TSSI_PID5  %8x \n ",    REG32( TSSI_PID5 ));
-	printk("REG_TSSI_PID6  %8x \n ",    REG32( TSSI_PID6 ));
-	printk("REG_TSSI_PID7  %8x \n ",    REG32( TSSI_PID7 ));
+        printk("REG_TSSI_ENA   %8x \n", REG_TSSI_ENA);
+        printk("REG_TSSI_NUM   %8x \n", REG_TSSI_NUM);
+        printk("REG_TSSI_DTR   %8x \n", REG_TSSI_DTR);
+        printk("REG_TSSI_CFG   %8x \n", REG_TSSI_CFG);
+        printk("REG_TSSI_CTRL  %8x \n", REG_TSSI_CTRL);
+        printk("REG_TSSI_STAT  %8x \n", REG_TSSI_STAT);
+        printk("REG_TSSI_FIFO  %8x \n", REG_TSSI_FIFO);
+        printk("REG_TSSI_PEN   %8x \n", REG_TSSI_PEN);
+        printk("REG_TSSI_PID0  %8x \n", REG_TSSI_PID0);
+        printk("REG_TSSI_PID1  %8x \n", REG_TSSI_PID1);
+        printk("REG_TSSI_PID2  %8x \n", REG_TSSI_PID2);
+        printk("REG_TSSI_PID3  %8x \n", REG_TSSI_PID3);
+        printk("REG_TSSI_PID4  %8x \n", REG_TSSI_PID4);
+        printk("REG_TSSI_PID5  %8x \n", REG_TSSI_PID5);
+        printk("REG_TSSI_PID6  %8x \n", REG_TSSI_PID6);
+        printk("REG_TSSI_PID7  %8x \n", REG_TSSI_PID7);
 }
 
-void dump_dma_channel(unsigned int dmanr)
+static void tssi_free_buf(struct jz_tssi_buf_ring * ring)
 {
-	printk("DMA%d Registers:\n", dmanr);
-	printk("  DMACR  = 0x%8x\n", REG_DMAC_DMACR(0));
-	printk("  DSAR   = 0x%8x\n", REG_DMAC_DSAR(dmanr));
-	printk("  DTAR   = 0x%8x\n", REG_DMAC_DTAR(dmanr));
-	printk("  DTCR   = 0x%8x\n", REG_DMAC_DTCR(dmanr));
-	printk("  DRSR   = 0x%8x\n", REG_DMAC_DRSR(dmanr));
-	printk("  DCCSR  = 0x%8x\n", REG_DMAC_DCCSR(dmanr));
-	printk("  DCMD  = 0x%8x\n", REG_DMAC_DCMD(dmanr));
-	printk("  DDA  = 0x%8x\n", REG_DMAC_DDA(dmanr));
-	printk("  DMADBR = 0x%8x\n", REG_DMAC_DMADBR(1));
-}
-
-static int tssi_buf_init( struct jz_tssi_buf_ring_t * ring ) 	
-{
-	int i;
-	struct jz_tssi_buf * bp,* ap, *cp;
-
-	ap = cp = bp = (struct jz_tssi_buf *)kmalloc( sizeof( struct jz_tssi_buf ) ,GFP_KERNEL );  //the first
-	if ( !bp ) { 
-		printk("Can not malloc buffer! \n");
-		return -1;
-	}
-
-	for ( i = 0; i < RING_BUF_NUM; i ++ ) {
-		bp = ap;
-		bp->buf = (unsigned int *) kmalloc(MPEG2_TS_PACHAGE_SIZE / 4 * sizeof(unsigned int) ,GFP_KERNEL);
-		if ( !bp->buf ) {        
-			printk("Can not malloc buffer! \n");
-			return -1;
-		}
-		bp->index = i;
-		bp->pos = 0;
-		ap = (struct jz_tssi_buf *)kmalloc( sizeof( struct jz_tssi_buf ) ,GFP_KERNEL );
-		if ( !ap ) { 
-			printk("Can not malloc buffer! \n");
-			return -1;
-		}
-
-		bp->next = ap;      //point to next !
-	}
-
-	bp->next = cp;                  //point loop to first!
-	ring->front = cp;
-	ring->rear  = cp;
-	ring->fu_num = 0;
-	kfree(ap);
-	return 0;
-}
-
-static void tssi_free_buf( struct jz_tssi_buf_ring_t * ring )
-{
-	int i;
-	struct jz_tssi_buf * ap;
-	for ( i = 0; i < RING_BUF_NUM; i ++ ) 
-	{
+        int i;
+        struct jz_tssi_buf * ap;
+        for ( i = 0; i < RING_BUF_NUM; i++) {
 		ap = ring->front;
-		ring->front = ring->front->next;
-		kfree( ap );
-	}
+                ring->front = ring->front->next;
+                kfree(ap);
+        }
 }
 
-#if 0
-static void tssi_read_fifo(void *dev_id)
-{
-	struct jz_tssi_t* tssi = ( struct jz_tssi_t* )dev_id;
-	struct jz_tssi_buf_ring_t * ring = tssi->cur_buf;
-	struct jz_tssi_buf *buf = ring->rear;
-	int i;
-#if 0
-	if ( ring->fu_num > RING_BUF_NUM )
-	{
-		printk("Ring buffer full ! %d \n",ring->fu_num);
-		return;
-	}
-#endif
-	
-	for ( i = 0; i < 8 ; i ++ )
-	{
-		ring->front->buf[ring->front->pos++] = REG_TSSI_FIFO;
-	}
-
-	if ( ring->front->pos >= MPEG2_TS_PACHAGE_SIZE ) 
-	{
-		ring->fu_num ++;
-		ring->front = ring->front->next;
-		ring->front->pos = 0;
-	}
-}
-#endif
-
 static void tssi_config_filting( void )
 {
-	__tssi_soft_reset();
 	__gpio_as_tssi();
-	__tssi_disable_ovrn_irq();         //use dma ,no need irq
-	__tssi_disable_trig_irq();
-	__tssi_set_tigger_num( 8 );        //trig is 4 word!
-//	__tssi_filter_enable();
-	__tssi_clear_state();
-	__tssi_filter_disable();
-	__tssi_state_clear_overrun();
-//	__tssi_clear_trig_irq_flag();
-#ifdef USE_DMA
+	__tssi_disable_ctrl_irq();
 	__tssi_dma_enable();
-#else
-	__tssi_dma_disable();
-#endif
-
-	__tssi_enable_ovrn_irq();
-//	__tssi_enable_trig_irq();
-
-	//set config
-//	__tssi_set_bt_1();
+	__tssi_set_tigger_num(96);        //trig is 4 word!
+	__tssi_filter_disable_pid0();
+	__tssi_filter_enable();
+//	__tssi_filter_disable();
 	__tssi_set_wd_1();
-	__tssi_set_data_use_data7();
 	__tssi_set_data_pola_high();
-//	__tssi_select_serail_mode();
 	__tssi_select_paral_mode();
-	__tssi_select_clk_fast();
+//	__tssi_select_clk_fast();
+	__tssi_select_clk_slow(); 
+	REG_TSSI_CTRL = 7;
+
+#if 1
+/* no add data 0 */
+	REG_TSSI_CFG &= ~(1 << 10);
+	REG_TSSI_CFG |= (2 << 10);
+#endif
+
+
+
+
 	__tssi_select_clk_posi_edge();
 	__tssi_select_frm_act_high();
 	__tssi_select_str_act_high();
 	__tssi_select_fail_act_high();
 //	__tssi_select_fail_act_low();
-	__tssi_disable_filte_pid0();     //we disable pid0 filter for ever!
 }
 
 static void tssi_add_pid(int pid_num, int pid)
@@ -219,121 +139,127 @@ static void tssi_add_pid(int pid_num, int pid)
 	}
 }
 
-static irqreturn_t tssi_dma_irq(int irq, void * dev_id)
+static irqreturn_t tssi_interrupt(int irq, void * dev_id)
 {
+	unsigned char *tmp;
+	int num = REG_TSSI_NUM;
+	int did = (REG_TSSI_DST & TSSI_DST_DID_MASK) >> TSSI_DST_DID_BIT;
+	
+
 	struct jz_tssi_t *tssi = (struct jz_tssi_t *)dev_id;
-	struct jz_tssi_buf_ring_t *buf = tssi->cur_buf;
+	struct jz_tssi_buf_ring *cur_buf = tssi->cur_buf;
+	struct jz_tssi_desc_t *tssi_desc0 = &g_tssi_desc0;
+	struct jz_tssi_desc_t *tssi_desc1 = &g_tssi_desc1;
+
+	__intc_mask_irq(TSSI_IRQ);
 
-	REG_DMAC_DCCSR(tssi->dma_chan) &= ~DMAC_DCCSR_EN;  /* disable DMA */
+	__tssi_clear_desc_end_flag();
 
-	if (__dmac_channel_transmit_end_detected(tssi->dma_chan)) {
-		__dmac_channel_clear_transmit_end(tssi->dma_chan);
-		if ( buf->fu_num < RING_BUF_NUM )
-		{
-			buf->front = buf->front->next;
-			REG_DMAC_DSAR(tssi->dma_chan) = CPHYSADDR(TSSI_FIFO);
-			REG_DMAC_DTAR(tssi->dma_chan) = CPHYSADDR((unsigned int)buf->front->buf);
-			REG_DMAC_DTCR(tssi->dma_chan) = MPEG2_TS_PACHAGE_SIZE / 32;
-			REG_DMAC_DCCSR(tssi->dma_chan) = DMAC_DCCSR_NDES | DMAC_DCCSR_EN;
-			buf->fu_num ++;
-		}
+	if (REG_TSSI_STAT & TSSI_STAT_OVRN) {
+		printk("tssi over run occur! %x, num = %d\n",REG8( TSSI_STAT ), num);
 		__tssi_clear_state();
 	}
 
-	if (__dmac_channel_transmit_halt_detected(tssi->dma_chan)) {
-		printk("DMA HALT\n");
-		__dmac_channel_clear_transmit_halt(tssi->dma_chan);
-	}
+#if 1
+	/* exchange the in_buf0/1 <=> cur_buf->front->buf */
+	if (did == 0) {
+		tmp = cur_buf->front->buf;
+		cur_buf->front->buf = in_buf0;
+		in_buf0 = tmp;	
+		tssi_desc0->dst_addr = (unsigned int)virt_to_phys((void *)in_buf0);
+		dma_cache_wback((unsigned int)(&tssi_desc0), sizeof(struct jz_tssi_desc_t));
+		
+	} else if (did == 1) {
+		tmp = cur_buf->front->buf;
+		cur_buf->front->buf = in_buf1;
+		in_buf1 = tmp;	
+		tssi_desc1->dst_addr = (unsigned int)virt_to_phys((void *)in_buf1);
+		dma_cache_wback((unsigned int)(&tssi_desc1), sizeof(struct jz_tssi_desc_t));
+	} else {
+		printk("DMA Transfer fault, no souch did value: %d\n", did);
+		__intc_ack_irq(TSSI_IRQ);
+		__intc_unmask_irq(TSSI_IRQ);
 
-	if (__dmac_channel_address_error_detected(tssi->dma_chan)) {
-		printk("DMA ADDR ERROR\n");
-		__dmac_channel_clear_address_error(tssi->dma_chan);
+		return IRQ_HANDLED;
 	}
+#endif
 
-	if (__dmac_channel_descriptor_invalid_detected(tssi->dma_chan)) {
-		printk("DMA DESC INVALID\n");
-		__dmac_channel_clear_descriptor_invalid(tssi->dma_chan);
-	}
+	cur_buf->front = cur_buf->front->next;
+	cur_buf->fu_num += 1;
 
-	if (__dmac_channel_count_terminated_detected(tssi->dma_chan)) {
-		printk("DMA CT\n");
-		__dmac_channel_clear_count_terminated(tssi->dma_chan);
-	}
+	printk("num = %d, did = %d\n", cur_buf->fu_num, did);
 
-	return IRQ_HANDLED;
-}
+	if (cur_buf->fu_num == 1)
+		wake_up(&tssi->wait);
 
-static irqreturn_t tssi_interrupt(int irq, void * dev_id)
-{
-	__intc_mask_irq(TSSI_IRQ);
-#if 1
-	if ( REG_TSSI_STAT & TSSI_STAT_OVRN )
-	{
-		printk("tssi over run occur! %x\n",REG8( TSSI_STAT ));
-		__tssi_clear_state();
-		printk("clear ! %x\n",REG8( TSSI_STAT ));
+/* used for test */
+#if DEBUG
+/* it will be over run the buf */
+	if (cur_buf->fu_num == 5) {
+		__tssi_dma_enable();
+		__tssi_disable();
+		__intc_ack_irq(TSSI_IRQ);
+		__intc_unmask_irq(TSSI_IRQ);
+		return IRQ_HANDLED;
 	}
 #endif
-	if ( REG_TSSI_STAT & TSSI_STAT_TRIG )
-	{
-		printk("tssi trig irq occur! \n");
-		tssi_read_fifo( dev_id );
-	}
 
 	__intc_ack_irq(TSSI_IRQ);
 	__intc_unmask_irq(TSSI_IRQ);
+
 	return IRQ_HANDLED;
 }
-
-static ssize_t jz_read(struct file * filp, char * buffer, size_t count, loff_t * ppos)
+static ssize_t jz_read(struct file *filp, char *buffer, size_t count, loff_t *ppos)
 {
 	jz_char_dev_t *adev = (jz_char_dev_t *)filp->private_data;
-	struct jz_tssi_t* tssi = (struct jz_tssi_t*)adev->private;
-	struct jz_tssi_buf_ring_t* ring = tssi->cur_buf;
-
+        struct jz_tssi_t* tssi = (struct jz_tssi_t*)adev->private;
+        struct jz_tssi_buf_ring* ring = tssi->cur_buf;
 	int i;
+	unsigned long flags;
 
-	count /= MPEG2_TS_PACHAGE_SIZE;
+	count /= MPEG2_PACKET_SIZE;
 
-	if ( count > ring->fu_num )
-		count = ring->fu_num;
+	wait_event_interruptible(tssi->wait, ring->fu_num != 0);
 
-	for ( i = 0; i < count; i ++ )
-	{
-		memcpy( buffer + ( i * MPEG2_TS_PACHAGE_SIZE),
-			ring->rear->buf, MPEG2_TS_PACHAGE_SIZE );
-		ring->rear->pos = 0;
+	spin_lock_irqsave(&tssi->lock, flags);
+	if (count > ring->fu_num) {
+		count = ring->fu_num;
+	}
+	spin_unlock_irqrestore(&tssi->lock, flags);
+
+	for (i = 0; i < count; i++) {
+#if DEBUG
+	int j;
+		copy_to_user(buffer+i*MPEG2_PACKET_SIZE, in_buf0, MPEG2_PACKET_SIZE);
+		for (j = 0; j < MPEG2_PACKET_SIZE; j++) {
+			if (j % 192 == 0) {
+				printk("\n\n");
+			}
+		//	printk(" %02x ", ring->rear->buf[j]);
+			printk("%02x ", in_buf0[j]);
+		}
+#endif
+		copy_to_user(buffer+i*MPEG2_PACKET_SIZE, ring->rear->buf, MPEG2_PACKET_SIZE);
 		ring->rear = ring->rear->next;
+		ring->rear->pos = 0;
 	}
+
+	spin_lock_irqsave(&tssi->lock, flags);
 	ring->fu_num -= count;
-	return count * MPEG2_TS_PACHAGE_SIZE;
-}
+	spin_unlock_irqrestore(&tssi->lock, flags);
+	
 
-static int tssi_dma_reinit(int dma_chan, unsigned char *dma_buf, int size)
-{
-	static unsigned int dma_src_phys_addr, dma_dst_phys_addr;
-	REG_DMAC_DMACKE(0) = 0xff;
-	dma_src_phys_addr = CPHYSADDR(TSSI_FIFO);
-	dma_dst_phys_addr = CPHYSADDR((unsigned int)dma_buf);
-	REG_DMAC_DMACR(dma_chan/HALF_DMA_NUM) = 0;
-	REG_DMAC_DCCSR(dma_chan) = 0;
-	REG_DMAC_DRSR(dma_chan) = DMAC_DRSR_RS_TSSIIN;
-	REG_DMAC_DSAR(dma_chan) = dma_src_phys_addr;
-	REG_DMAC_DTAR(dma_chan) = dma_dst_phys_addr;
-	REG_DMAC_DTCR(dma_chan) = size / 32;                 
-	REG_DMAC_DCMD(dma_chan) = DMAC_DCMD_DAI | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 | DMAC_DCMD_DS_32BYTE | DMAC_DCMD_TIE;
-	REG_DMAC_DCCSR(dma_chan) = DMAC_DCCSR_NDES | DMAC_DCCSR_EN;
-	REG_DMAC_DMACR(dma_chan/HALF_DMA_NUM) = DMAC_DMACR_DMAE; /* global DMA enable bit */
-	return 0;
+	return count*MPEG2_PACKET_SIZE;
 }
 
 static int jz_open(struct inode * inode, struct file * filp)
 {
 	try_module_get(THIS_MODULE);
 
-	__tssi_soft_reset();
 	__intc_mask_irq(TSSI_IRQ);
 	tssi_config_filting();
+	__tssi_soft_reset();
+	__tssi_clear_state();
 
 	return 0;
 }
@@ -353,14 +279,19 @@ static int jz_ioctl(struct inode *inode, struct file *file, unsigned int cmd, un
 	switch (cmd)
 	{
 	case IOCTL_TSSI_ENABLE :
+		__tssi_disable();
+		__tssi_soft_reset();
+		__tssi_clear_state();
+		dump_tssi_regs();
 		__intc_ack_irq(TSSI_IRQ);
 		__intc_unmask_irq(TSSI_IRQ);
 		__tssi_enable();
-		print_reg();
 
         	break;
 	case IOCTL_TSSI_DISABLE :
 		__tssi_disable();
+		__tssi_soft_reset();
+		__tssi_clear_state();
 
         	break;
 	case IOCTL_TSSI_SOFTRESET :
@@ -374,7 +305,7 @@ static int jz_ioctl(struct inode *inode, struct file *file, unsigned int cmd, un
 		__tssi_filter_disable();
         	break;
 	case IOCTL_TSSI_ADDPID :           //add one pid to filter
-		if ( tssi->pid_num < 15 )
+		if ( tssi->pid_num < 31 )
 		{
 			tssi_add_pid(tssi->pid_num, arg);
 			tssi->pid_num ++ ;
@@ -394,10 +325,8 @@ static int jz_ioctl(struct inode *inode, struct file *file, unsigned int cmd, un
 		break;
 
 	case IOCTL_TSSI_INIT_DMA:
-  		tssi_dma_reinit(tssi->dma_chan, tssi->cur_buf->front->buf, MPEG2_TS_PACHAGE_SIZE);
 		break;
 	case IOCTL_TSSI_DISABLE_DMA:
-		REG_DMAC_DCCSR(tssi->dma_chan) &= ~DMAC_DCCSR_EN;  /* disable DMA */
 		break;
 	}
 
@@ -405,51 +334,134 @@ static int jz_ioctl(struct inode *inode, struct file *file, unsigned int cmd, un
 }
 
 static struct file_operations tssi_fops = {
-	owner:          THIS_MODULE,
-	read:           jz_read,
-	poll:           NULL,
-	fasync:         NULL,
-	ioctl:          jz_ioctl,
-	open:		jz_open,
-	release:	jz_release,
+	.owner	= THIS_MODULE,
+	.read	= jz_read,
+	.poll	= NULL,
+	.fasync	= NULL,
+	.ioctl	= jz_ioctl,
+	.open	= jz_open,
+//	.mmap	= jz_mmap,
+	.release= jz_release,
 };
 
+static void tssi_dma_desc_init(void)
+{
+	struct jz_tssi_desc_t *tssi_desc0 = &g_tssi_desc0;
+	struct jz_tssi_desc_t *tssi_desc1 = &g_tssi_desc1;
+	
+	tssi_desc0->next_desc = (unsigned int)virt_to_phys((void *)tssi_desc1);
+	tssi_desc0->dst_addr = (unsigned int)virt_to_phys((void *)in_buf0);
+	tssi_desc0->did = 0;
+
+	 /* TLEN:1Mbytes TEFE:1 TSZ:32 TEIE:1 LINK:0 */
+	tssi_desc0->cmd = ((MPEG2_PACKET_SIZE/4) << TSSI_DCMD_TLEN_BIT) | TSSI_DCMD_TEFE | TSSI_DCMD_TSZ_32 |
+		  TSSI_DCMD_TEIE | TSSI_DCMD_LINK;
+
+
+	tssi_desc1->next_desc = (unsigned int)virt_to_phys((void *)tssi_desc0);
+	tssi_desc1->dst_addr = (unsigned int)virt_to_phys((void *)in_buf1);
+	tssi_desc1->did = 1;
+
+	 /* TLEN:1Mbytes TEFE:1 TSZ:32 TEIE:1 LINK:1 */
+	tssi_desc1->cmd = ((MPEG2_PACKET_SIZE/4) << TSSI_DCMD_TLEN_BIT) | TSSI_DCMD_TEFE | TSSI_DCMD_TSZ_32 |
+			  TSSI_DCMD_TEIE | TSSI_DCMD_LINK;
+
+	REG_TSSI_DDA = (unsigned int)virt_to_phys((void*)tssi_desc0);
+	dma_cache_wback((unsigned int)(&tssi_desc0), sizeof(struct jz_tssi_desc_t));
+	dma_cache_wback((unsigned int)(&tssi_desc1), sizeof(struct jz_tssi_desc_t));
+	
+}
+static int tssi_buf_init(struct jz_tssi_buf_ring * ring)
+{
+	int i;
+	struct jz_tssi_buf *ap, *bp, *cp;
+
+	/* used for dma desc0 and desc1 transfer buf total 2M=2^9*4K */
+	in_buf0 = (unsigned char*)__get_free_pages(GFP_KERNEL, IN_BUF_LEN);
+	if (!in_buf0) {
+		printk("Alloc in_buf memory failed.\n");
+		return -ENOMEM;
+	}
+
+	in_buf1 = in_buf0 + (PAGE_SIZE << (IN_BUF_LEN - 1));
+	memset(in_buf0, 0, PAGE_SIZE << IN_BUF_LEN);
+
+	/* used for save the data for the user space */
+	out_buf = (unsigned char*)__get_free_pages(GFP_KERNEL, OUT_BUF_LEN);
+	if (!out_buf) {
+		printk("Alloc out_buf memory failed.\n");
+		return -ENOMEM;
+	}
+	memset(out_buf, 0, PAGE_SIZE << OUT_BUF_LEN);
+	
+	ap = bp = cp = (struct jz_tssi_buf*)kmalloc(sizeof(struct jz_tssi_buf), GFP_KERNEL);
+	if (!ap) {
+		printk("Alloc tssi buf memory failed.\n");
+		return -ENOMEM;
+	}
+	
+	for (i = 0; i < RING_BUF_NUM; i++) {
+		bp = ap;
+		ap->buf = out_buf + i * (PAGE_SIZE << (OUT_BUF_LEN -2));
+
+		ap = (struct jz_tssi_buf*)kmalloc(sizeof(struct jz_tssi_buf), GFP_KERNEL);
+		if (!ap) {
+			printk("Alloc the %dth buf ring failed.\n", i);
+			return -ENOMEM;
+		}
+
+		bp->pos = 0;
+		bp->next = ap;
+	}
+
+	bp->next = cp;
+	ring->front = cp;
+	ring->rear = cp;
+	ring->fu_num = 0;
+	kfree(ap);	
+
+	return 0;
+}
+
 static int __init jztssi_init_module(void)
 {
 	int retval;
 	struct jz_tssi_t *tssi = &jz_tssi_g;
 
-	__cpm_start_tssi();
-	__cpm_start_dmac();
-	tssi_buf_init( &jz_tssi_ring_g );
+//	cpm_start_clock(CGM_TSSI);
+
+	retval = tssi_buf_init(&jz_tssi_ring_g);
+	if (retval) {
+		printk("tssi buf init failed.\n");
+		return -1;
+	}
+	
 	tssi->cur_buf = &jz_tssi_ring_g;
 	tssi->pid_num = 0;
-	retval = request_irq(TSSI_IRQ, tssi_interrupt, IRQF_DISABLED, TSSI_NAME, &jz_tssi_g);
 
+	tssi_dma_desc_init();
+
+	spin_lock_init(&tssi->lock);
+	init_waitqueue_head(&tssi->wait);
+
+	retval = request_irq(TSSI_IRQ, tssi_interrupt, IRQF_DISABLED, TSSI_NAME, (void*)&jz_tssi_g);
 	if (retval) {
 		printk("unable to get IRQ %d",TSSI_IRQ);
 		return retval;
 	}
 
-	tssi->dma_chan = jz_request_dma(DMA_ID_TSSI, "tssi", tssi_dma_irq,
-				  IRQF_DISABLED, &jz_tssi_g);
-	if ( tssi->dma_chan < 0 )
-	{
-		printk("MPEG2-TS request irq fail! \n");
-		return -1;
-	}
-
-	jz_register_chrdev(TSSI_MINOR, TSSI_NAME, &tssi_fops, &jz_tssi_g);	
+	jz_register_chrdev(TSSI_MINOR, TSSI_NAME, &tssi_fops, (void *)&jz_tssi_g);	
 
-	printk(JZ_SOC_NAME": MPEG2-TS interface driver registered %x %d\n",&jz_tssi_g,tssi->dma_chan);
+	printk(JZ_SOC_NAME": MPEG2-TS interface driver registered %x\n",(unsigned int)&jz_tssi_g);
 	return 0;
 }
 
 static void jztssi_cleanup_module(void)
 {
 	free_irq(TSSI_IRQ,0);
-	jz_free_dma(jz_tssi_g.dma_chan);
-	tssi_free_buf( &jz_tssi_ring_g );
+	tssi_free_buf(&jz_tssi_ring_g);
+	kfree(in_buf0);
+	kfree(out_buf);
 	jz_unregister_chrdev(TSSI_MINOR, TSSI_NAME);
 }
 
diff --git a/drivers/char/jzchar/jz_tssi.h b/drivers/char/jzchar/jz_tssi.h
index 7ac424d6fce..9c4842c5342 100644
--- a/drivers/char/jzchar/jz_tssi.h
+++ b/drivers/char/jzchar/jz_tssi.h
@@ -30,47 +30,36 @@
 #endif
 
 #define MAX_PID_NUM                     15
-#define MPEG2_TS_PACHAGE_SIZE           19200
+//#define MPEG2_PACKET_SIZE          (1024 * 960) /* bytes */
+#define MPEG2_PACKET_SIZE          (1024 * 940) /* bytes */
 
-struct jz_tssi_cfg_t
+struct jz_tssi_desc_t
 {
-	unsigned char wordorder;
-	unsigned char byteorder;
-	unsigned char dataploa;
-	unsigned char use0;
-	unsigned char clkch;
-	unsigned char mode;
-	unsigned char clkpola;
-	unsigned char frmpola;
-	unsigned char strpola;
-	unsigned char failpola;
-	unsigned char trignum;
-
-	unsigned short pid;
-	unsigned char pid_index;          //0 to 15
+	unsigned int next_desc;
+	unsigned int dst_addr;
+	unsigned int did;
+	unsigned int cmd;
 };
 
-struct jz_tssi_buf
-{
-	unsigned int *buf;
-	unsigned int   pos;
-	unsigned int   index;
+struct jz_tssi_buf {
+	unsigned char *buf;
 	struct jz_tssi_buf *next;
+	int pos;
 };
 
-struct jz_tssi_buf_ring_t
-{
-	struct jz_tssi_buf	*front;
-	struct jz_tssi_buf	*rear;
-	unsigned int  fu_num;
+struct jz_tssi_buf_ring {
+	struct jz_tssi_buf *front;
+	struct jz_tssi_buf *rear;
+	unsigned int fu_num;
 };
 
 struct jz_tssi_t
 {
-	struct jz_tssi_cfg_t cur_config;
-	struct jz_tssi_buf_ring_t *cur_buf;
-	struct semaphore	tssi_sem;
-	int dma_chan, pid_num;
+	struct jz_tssi_desc_t tssi_desc;
+	struct jz_tssi_buf_ring *cur_buf;
+	spinlock_t lock;
+	wait_queue_head_t wait;
+	int pid_num;
 };
 
 #endif /* __JZ_TSSI_H__ */
diff --git a/drivers/char/jzchar/tcsm.c b/drivers/char/jzchar/tcsm.c
index a64972cd63f..ea63054ce74 100644
--- a/drivers/char/jzchar/tcsm.c
+++ b/drivers/char/jzchar/tcsm.c
@@ -61,6 +61,17 @@ static struct file_operations tcsm_fops =
 static int tcsm_open(struct inode *inode, struct file *filp)
 {
   struct pt_regs *info = task_pt_regs(current);
+
+#ifdef CONFIG_SOC_JZ4760B
+  REG_CPM_CLKGR1 &= ~(CLKGR1_AUX | CLKGR1_OSD );
+#endif
+
+#if defined(CONFIG_SOC_JZ4760) || defined(CONFIG_SOC_JZ4760B)
+  REG_CPM_CLKGR1 &= ~ (CLKGR1_AHB1 | CLKGR1_CABAC | CLKGR1_SRAM | CLKGR1_DCT | CLKGR1_DBLK | CLKGR1_MC | CLKGR1_ME);
+  REG_CPM_LCR &= ~(1 << 30);
+  while(REG_CPM_LCR & LCR_PDAHB1S);
+  REG_CPM_CLKGR1 |= (CLKGR1_ME);
+#endif
  
   info->cp0_status &= ~0x10;// clear UM bit
   info->cp0_status |= 0x08000000; // set RP bit   a tricky
@@ -72,6 +83,15 @@ static int tcsm_release(struct inode *inode, struct file *filp)
 {
   struct pt_regs *info = task_pt_regs(current);
 
+#ifdef CONFIG_SOC_JZ4760B
+  REG_CPM_CLKGR1 |= (CLKGR1_AUX | CLKGR1_OSD);
+#endif
+
+#if defined(CONFIG_SOC_JZ4760) || defined(CONFIG_SOC_JZ4760B)
+  REG_CPM_CLKGR1 |= (CLKGR1_AHB1 | CLKGR1_CABAC | CLKGR1_SRAM | CLKGR1_DCT | CLKGR1_DBLK | CLKGR1_MC | CLKGR1_ME);
+  REG_CPM_LCR |= (1 << 30);
+#endif
+
   info->cp0_status |= 0x10;// set UM bit
   info->cp0_status &= ~0x08000000; // clear RP bit  a tricky
  
diff --git a/drivers/char/rtc_jz.c b/drivers/char/rtc_jz.c
index afa17ddd089..60f74790c4b 100644
--- a/drivers/char/rtc_jz.c
+++ b/drivers/char/rtc_jz.c
@@ -465,9 +465,124 @@ static struct miscdevice rtc_dev=
 	&rtc_fops
 };
 
+/* The divider is decided by the RTC clock frequency. */
+#define RTC_FREQ_DIVIDER	(32768 - 1)
+#define ms2clycle(x)  (((x) * RTC_FREQ_DIVIDER) / 1000)
+
+#define RTC_CFG (((unsigned int)('R') << 24) | ((unsigned int)('T') << 16) | ((unsigned int)('C') << 8))
+#define CAL_RTC_CFG(x)				\
+  ({						\
+    unsigned int x1,x2,x3;			\
+    x1 = ((x) >> 24) & 0xff;			\
+    x2 = ((x) >> 16) & 0xff;			\
+    x3 = ((x) >> 8) & 0xff;			\
+  ((x & (~0xff)) | (x1 + x2 + x3));		\
+  })
+#define SET_RTC_REG(reg,x)				\
+  do{							\
+    unsigned int rcr;					\
+    do{							\
+      rcr = reg;					\
+    }while(rcr != reg);					\
+    rcr |= (x);						\
+    while ( !__rtc_write_ready());			\
+    reg = rcr;						\
+  }while(0);
+
+#define CLR_RTC_REG(reg,x)				\
+  do{							\
+    unsigned int rcr;					\
+    do{							\
+      rcr = reg;					\
+    }while(rcr != reg);					\
+    rcr &= ~(x);					\
+    while ( !__rtc_write_ready());			\
+    reg = rcr;						\
+  }while(0);
+
+#define OUT_RTC_REG(reg,x)				\
+  do{							\
+    while ( !__rtc_write_ready());			\
+    reg = x;						\
+  }while(0);
+
+#define IN_RTC_REG(reg)					\
+  ({							\
+    unsigned int dat;					\
+    do{							\
+      dat = reg;					\
+    }while(reg != dat);					\
+    dat;						\
+  })
+
+
+ /* Default time for the first-time power on */
+static struct rtc_time default_tm = {
+	.tm_year = (2009 - 1900), // year 2009
+	.tm_mon = (10 - 1),       // month 10
+	.tm_mday = 1,             // day 1
+	.tm_hour = 12,
+	.tm_min = 0,
+	.tm_sec = 0
+}; 
+static void rtc_first_power_on()
+{
+	unsigned int rcr,cfc,hspr,rgr_1hz;
+	/*
+	 * When we are powered on for the first time, init the rtc and reset time.
+	 *
+	 * For other situations, we remain the rtc status unchanged.
+	 */
+	 
+	__cpm_select_rtcclk_rtc();
+
+	//unsigned int ppr = IN_RTC_REG(REG_RTC_HWRSR);   
+	cfc = 0x12345678;//CAL_RTC_CFG(RTC_CFG);
+	hspr = IN_RTC_REG(REG_RTC_HSPR);
+	rgr_1hz  = IN_RTC_REG(REG_RTC_RGR) & RTC_RGR_NC1HZ_MASK;
+	
+	if((hspr != cfc) || (rgr_1hz != RTC_FREQ_DIVIDER))
+	{
+	//if ((ppr >> RTC_HWRSR_PPR) & 0x1) {
+		/* We are powered on for the first time !!! */
+
+		printk("jz4750-rtc: rtc status reset by power-on\n");
+
+		/* init rtc status */
+		
+		rcr = IN_RTC_REG(REG_RTC_RCR);
+		rcr &= ~(RTC_RCR_1HZ | RTC_RCR_1HZIE | RTC_RCR_AF | RTC_RCR_AE | RTC_RCR_AIE);
+		
+
+		/* Set 32768 rtc clocks per seconds */
+		OUT_RTC_REG(REG_RTC_RGR,RTC_FREQ_DIVIDER);
+
+		/* Set minimum wakeup_n pin low-level assertion time for wakeup: 100ms */
+
+		OUT_RTC_REG(REG_RTC_HWFCR,ms2clycle(100) << RTC_HWFCR_BIT);
+
+		//REG_RTC_HWFCR = (100 << RTC_HWFCR_BIT);
+		//while ( !__rtc_write_ready());
+	
+		/* Set reset pin low-level assertion time after wakeup: must  > 60ms */
+		//REG_RTC_HRCR = (60 << RTC_HRCR_BIT);
+		//while ( !__rtc_write_ready());
+
+		OUT_RTC_REG(REG_RTC_HRCR,ms2clycle(60) <<  RTC_HRCR_BIT);
+                /* Reset to the default time */
+		set_rtc_time( &default_tm);
+		/* start rtc */
+		rcr |= RTC_RCR_RTCE;
+		OUT_RTC_REG(REG_RTC_RCR,rcr);
+		OUT_RTC_REG(REG_RTC_HSPR,cfc);
+		/* select external 32K crystal as RTC clock */
+	}
+}
 int __init Jz_rtc_init(void)
 {
 
+	printk("jz4750-rtc: Jz_rtc_init\n");
+	rtc_first_power_on();
 	INIT_WORK(&rtc_alarm_task, rtc_alarm_task_handler);
 
 	/* Enabled rtc function, enable rtc alarm function */
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 918fc832349..f476337c5c3 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -8,22 +8,62 @@ comment "PC SMBus host controller drivers"
 
 config I2C_JZ47XX
 	tristate "JZ47XX I2C Interface support"
-	depends on SOC_JZ4730 || SOC_JZ4740  || SOC_JZ4750 || SOC_JZ4760
+	depends on SOC_JZ4730 || SOC_JZ4740  || SOC_JZ4750
 	help
-	  If you have devices in the Ingenic JZ4730/JZ4740/JZ4750/jJZ4760 I2C bus, say yes to
+	  If you have devices in the Ingenic JZ4730/JZ4740/JZ4750 I2C bus, say yes to
 	  this option. This driver can also be built as a module.  If so, the
 	  module will be called i2c-jz47xx.
 
+config JZ_I2C
+	tristate "JZ I2C controller support"
+	depends on SOC_JZ4760B || SOC_JZ4810
+	help
+	  atomatically selected by CONFIG_JZ_I2C0, CONFIG_JZ_I2C1, CONFIG_JZ_I2C2
+
+config JZ_I2C0
+	tristate "JZ I2C controller 0 support"
+	depends on JZ_I2C
+	default y
+	help
+	  say yes to use JZ I2C controller 0. This driver can also be built as a module
+
+config JZ_I2C0_USE_DMA
+	bool "DMA support for I2C controller 0"
+	depends on JZ_I2C0
+	default y
+
+config JZ_I2C1
+	tristate "JZ I2C controller 1 support"
+	depends on JZ_I2C
+	help
+	  say yes to use JZ I2C controller 1. This driver can also be built as a module
+
+config JZ_I2C1_USE_DMA
+	bool "DMA support for I2C controller 1"
+	depends on JZ_I2C1
+	default y
+
+config JZ_I2C2
+	tristate "JZ I2C controller 2 support"
+	depends on JZ_I2C && SOC_JZ4810
+	help
+	  say yes to use JZ I2C controller 2. This driver can also be built as a module
+	
+config JZ_I2C2_USE_DMA
+	bool "DMA support for I2C controller 2"
+	depends on JZ_I2C2
+	default y
+
 config I2C0_JZ4760
 	tristate "JZ4760 I2C controler 0 Interface support"
-	depends on JZSOC
+	depends on SOC_JZ4760
 	help
 	  If you have devices in the Ingenic JZ4760 I2C controler 0 bus, say yes to
 	  this option. This driver can also be built as a module.
 
 config I2C1_JZ4760
 	tristate "JZ4760 I2C  controler 1 Interface support"
-	depends on JZSOC
+	depends on SOC_JZ4760
 	help
 	  If you have devices in the Ingenic JZ4760 I2C controler 1 bus, say yes to
 	  this option. This driver can also be built as a module.
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 61260779319..ddd39538ea1 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -7,6 +7,7 @@
 obj-$(CONFIG_I2C_JZ47XX)	+= i2c-jz47xx.o
 obj-$(CONFIG_I2C0_JZ4760)	+= i2c-jz4760.o
 obj-$(CONFIG_I2C1_JZ4760)	+= i2c-jz4760.o
+obj-$(CONFIG_JZ_I2C)		+= i2c-jz4810.o
 obj-$(CONFIG_I2C_ALI1535)	+= i2c-ali1535.o
 obj-$(CONFIG_I2C_ALI1563)	+= i2c-ali1563.o
 obj-$(CONFIG_I2C_ALI15X3)	+= i2c-ali15x3.o
diff --git a/drivers/i2c/busses/i2c-jz4760.c b/drivers/i2c/busses/i2c-jz4760.c
index a7ae6e3b8fb..e6dd378cffd 100644
--- a/drivers/i2c/busses/i2c-jz4760.c
+++ b/drivers/i2c/busses/i2c-jz4760.c
@@ -36,33 +36,33 @@
 #define TIMEOUT         0xffff
 
 //#undef DEBUG
-#define DEBUG
+#define DEBUG 
 #ifdef DEBUG
 #define dprintk(x...)	printk(x)
 #else
 #define dprintk(x...) do{}while(0)
 #endif
 
+#define __para_printk()\
+do {\
+dprintk("cmd_flag=%d,cmd_cnt=%d,r_cnt=%d length=%d",cmd_flag[I2C_ID],cmd_cnt[I2C_ID],r_cnt[I2C_ID],length);\
+} while(0)
+
 #define __reg_printk()							\
 do {								        \
-dprintk("  cmd_flag=%d,cmd_cnt=%d,r_cnt=%d length=%d",cmd_flag[I2C_ID],cmd_cnt[I2C_ID],r_cnt[I2C_ID],length); \
 dprintk("  REG_I2C_STA(%d)=0x%x",I2C_ID,REG_I2C_STA(I2C_ID));		\
 dprintk("  REG_I2C_TXTL(%d)=0x%x",I2C_ID,REG_I2C_TXTL(I2C_ID));		\
 dprintk("  REG_I2C_INTST(%d)=0x%x",I2C_ID,REG_I2C_INTST(I2C_ID));	\
 dprintk("  REG_I2C_TXABRT(%d)=0x%x\n",I2C_ID,REG_I2C_TXABRT(I2C_ID));	\
 dprintk("------------------%s:%d\n",__FUNCTION__,__LINE__);				\
 } while(0)
-/* The value of the most significant byte of sub_addr
- * indicate the length of sub address:
- * zero:1 byte, non-zero:2 bytes
- */
 
 struct i2c_speed {
 	unsigned int speed;
 	unsigned char slave_addr;
 };
 static  struct i2c_speed jz4760_i2c_speed[I2C_CLIENT_NUM];
-static unsigned char current_device;
+static unsigned char current_device[2]={0x0,0x0};
 static int client_cnt = 0;
 static int i2c_ctrl_rest[2]  = {0,0};
 struct jz_i2c {
@@ -90,14 +90,14 @@ void i2c_jz_setclk(struct i2c_client *client,unsigned long i2cclk)
 		jz4760_i2c_speed[client_cnt].speed      = 400;
 	}
 
-	//printk("Device 0x%2x with i2c speed:%dK\n",jz4760_i2c_speed[client_cnt].slave_addr,
-	//       jz4760_i2c_speed[client_cnt].speed );
+	printk("Device 0x%2x with i2c speed:%dK\n",jz4760_i2c_speed[client_cnt].slave_addr,
+	       jz4760_i2c_speed[client_cnt].speed );
 
 	client_cnt++;
 }
 EXPORT_SYMBOL_GPL(i2c_jz_setclk);
 
-/*
+/* 
  *jz_i2c_irq
 */
 static unsigned char *msg_buf0,*msg_buf1;
@@ -111,18 +111,19 @@ static irqreturn_t jz_i2c_irq(int irqno, void *dev_id)
 	int I2C_ID = i2c->id;
 	int flags = i2c->msg->flags;
 	int timeout = TIMEOUT;
-
-	if (__i2c_abrt_7b_addr_nack(I2C_ID)) {
-		int ret;
+	
+	if (__i2c_abrt(I2C_ID) || __i2c_abrt_intr(I2C_ID)) {
 		cmd_flag[I2C_ID] = -1;
-		__i2c_clear_interrupts(ret,I2C_ID);
+		//printk("*****jz4760 i2c abort.\n");
+		//__reg_printk();
+		//__i2c_clear_interrupts(ret,I2C_ID);
 		REG_I2C_INTM(I2C_ID) = 0x0;
 		return IRQ_HANDLED;
 	}
 	/* first byte,when length > 1 */
-	if (cmd_flag[I2C_ID] == 0 && cmd_cnt[I2C_ID] > 1) {
+	if (cmd_flag[I2C_ID] == 0 && cmd_cnt[I2C_ID] > 1) { 
 		cmd_flag[I2C_ID] = 1;
-		if (flags & I2C_M_RD) {
+		if (flags & I2C_M_RD) {			
 			REG_I2C_DC(I2C_ID) = I2C_READ << 8;
 		} else {
 			if (I2C_ID == 0) {
@@ -174,14 +175,14 @@ static irqreturn_t jz_i2c_irq(int irqno, void *dev_id)
 			}
 		}
 	}
-
+	
 	return IRQ_HANDLED;
 }
 
 static int i2c_disable(int I2C_ID)
 {
 	int timeout = TIMEOUT;
-
+	
 	__i2c_disable(I2C_ID);
 	while(__i2c_is_enable(I2C_ID) && (timeout > 0)) {
 		udelay(1);
@@ -196,7 +197,7 @@ static int i2c_disable(int I2C_ID)
 static int i2c_enable(int I2C_ID)
 {
 	int timeout = TIMEOUT;
-
+	
 	__i2c_enable(I2C_ID);
 	while(__i2c_is_disable(I2C_ID) && (timeout > 0)) {
 		mdelay(1);
@@ -208,35 +209,6 @@ static int i2c_enable(int I2C_ID)
 		return 1;
 }
 #endif
-#if 0
-static int i2c_set_F_clk(int i2c_clk, int I2C_ID)
-{
-	int dev_clk = __cpm_get_pclk();
-	int count = 0;
-
-	REG_I2C_CTRL(I2C_ID) = 0x45 | i2c_ctrl_rest[I2C_ID];       /* high speed mode*/
-	if (i2c_clk < 100 || i2c_clk > 400)
-		goto Set_fclk_err;
-
-	count = dev_clk/(i2c_clk*1000) - 23;
-
-	if (count < 0)
-		goto Set_fclk_err;
-	if (count%2 == 0) {
-		REG_I2C_FHCNT(I2C_ID) = count/2 + 6;
-		REG_I2C_FLCNT(I2C_ID) = count/2 + 8;
-	} else {
-		REG_I2C_FHCNT(I2C_ID) = count/2 + 6;
-		REG_I2C_FLCNT(I2C_ID) = count/2 + 8 + 1;
-	}
-	return 0;
-
-Set_fclk_err:
-
-	printk("i2c set fclk faild,dev_clk=%d.\n",dev_clk);
-	return -1;
-}
-#endif
 
 static int i2c_set_clk(int i2c_clk, int I2C_ID)
 {
@@ -244,7 +216,7 @@ static int i2c_set_clk(int i2c_clk, int I2C_ID)
 	int cnt_high = 0;	/* HIGH period count of the SCL clock */
 	int cnt_low = 0;	/* LOW period count of the SCL clock */
 	int cnt_period = 0;	/* period count of the SCL clock */
-
+	
 	if (i2c_clk <= 0 || i2c_clk > 400)
 		goto Set_clk_err;
 
@@ -272,14 +244,13 @@ static int i2c_set_clk(int i2c_clk, int I2C_ID)
 	return 0;
 
 Set_clk_err:
-
+	
 	printk("i2c set sclk faild,i2c_clk=%d KHz,dev_clk=%dKHz.\n", i2c_clk, dev_clk_khz);
 	return -1;
 }
 
 static void i2c_set_target(unsigned char address,int I2C_ID)
-{
-
+{	
 	while (!__i2c_txfifo_is_empty(I2C_ID) || __i2c_master_active(I2C_ID));
 	REG_I2C_TAR(I2C_ID) = address;  /* slave id needed write only once */
 }
@@ -293,13 +264,10 @@ static void i2c_init_as_master(int I2C_ID,unsigned char device)
 	for (i = 0; i < I2C_CLIENT_NUM; i++) {
 		if(device == jz4760_i2c_speed[i].slave_addr) {
 			i2c_set_clk(jz4760_i2c_speed[i].speed,I2C_ID);
-			/* printk("-----Device 0x%2x with i2c speed:%dK\n",jz4760_i2c_speed[i].slave_addr,
-			   jz4760_i2c_speed[i].speed ); */
 			break;
 		}
 	}
 	if (i == I2C_CLIENT_NUM) {
-		/* printk("+++++++++++++++++++++++++++++++i2c speed 100K.\n"); */
 		i2c_set_clk(100,I2C_ID);
 	}
 	REG_I2C_INTM(I2C_ID) = 0x0; /*mask all interrupt*/
@@ -307,48 +275,75 @@ static void i2c_init_as_master(int I2C_ID,unsigned char device)
 	REG_I2C_ENB(I2C_ID) = 1;   /*enable i2c*/
 }
 
-static int xfer_read(unsigned char device, unsigned char *buf,
-		     int length, struct jz_i2c *i2c)
+static DEFINE_SPINLOCK(i2c_read_lock);
+static int xfer_read_nostart(struct i2c_msg *msg1, struct i2c_msg *msg2, struct jz_i2c *i2c)
 {
-	int timeout,timeout_1,r_i = 0;
+	unsigned char *subaddr = msg1->buf;
+	unsigned char device = msg2->addr;
+	//unsigned char *buf   = msg2->buf;
+	//int length           = msg2->len;
+	int timeout,timeout_1,ret = 0;
 	int I2C_ID = i2c->id;
+	unsigned long irqflag;
+	
+	/*add for 0v2655 virtual I2C ID on 2010.6.5 and for hi704 on 2010.8.3*/
+	if (device == 0xaa || device == 0xbb)
+		device =0x30;
+	if(device == 0xcc)
+		device =0x21;
 
 #if defined(CONFIG_TOUCHSCREEN_JZ_MT4D)
 	if ((device == 0x40) && __gpio_get_pin(GPIO_ATTN)) {
 		return -87;
 	}
 #endif
-
 	i2c_set_target(device,I2C_ID);
 	cmd_flag[I2C_ID] = 0;
-	REG_I2C_INTM(I2C_ID) = 0x10;
+#if 1
+	REG_I2C_INTM(I2C_ID) = 0x40;
+	if (msg1->len == 1) {
+		REG_I2C_DC(I2C_ID) = (I2C_WRITE << 8) | *subaddr;
+	} else if (msg1->len == 2) {
+		spin_lock_irqsave(&i2c_read_lock, irqflag);
+		REG_I2C_DC(I2C_ID) = (I2C_WRITE << 8) | *subaddr++;
+		REG_I2C_DC(I2C_ID) = (I2C_WRITE << 8) | *subaddr;
+		spin_unlock_irqrestore(&i2c_read_lock, irqflag);
+	} else {
+		printk("your device subaddres is not support.\n");
+		return -7;
+	}
+#endif
+
+	REG_I2C_INTM(I2C_ID) = 0x50;
 	timeout = TIMEOUT;
 	while (cmd_flag[I2C_ID] != 2 && --timeout) {
 		if (cmd_flag[I2C_ID] == -1) {
-			r_i = 1;
+			ret = 1; /*device nack.*/
 			goto R_dev_err;
 		}
 		udelay(1);
 	}
 	if (!timeout) {
-		r_i = 4;
+		ret = 2; /*wait interrupt timeout.*/
 	      	goto R_timeout;
 	}
 
-       	timeout = TIMEOUT;
-	while (r_cnt[I2C_ID] && --timeout) {
-	        timeout_1 = TIMEOUT;
-		while ((!(REG_I2C_STA(I2C_ID) & I2C_STA_RFNE)) && (--timeout_1)) {
-			if ((cmd_flag[I2C_ID] == -1) ||
+	timeout_1 = TIMEOUT;
+	while (r_cnt[I2C_ID] && --timeout_1) {
+		timeout = TIMEOUT;
+		while ((!(REG_I2C_STA(I2C_ID) & I2C_STA_RFNE)) && (--timeout)) {
+			if ((cmd_flag[I2C_ID] == -1) || 
 			    (REG_I2C_INTST(I2C_ID) & I2C_INTST_TXABT) ||
 			    REG_I2C_TXABRT(I2C_ID)) {
-				int ret;
-				r_i = 2;
-				__reg_printk();
-				__i2c_clear_interrupts(ret,I2C_ID);
+				ret = 3; /*i2c abort or nack.*/
 				goto R_dev_err;
 			}
 		}
+		if (!timeout){
+			ret = 4;
+			goto R_timeout;
+		}
+
 		if (I2C_ID == 0) {
 			*msg_buf0++ = REG_I2C_DC(I2C_ID) & 0xff;
 		} else {
@@ -356,12 +351,16 @@ static int xfer_read(unsigned char device, unsigned char *buf,
 		}
 		r_cnt[I2C_ID]--;
 	}
+	if (!timeout_1) {
+		ret = 6; /*can not run here.*/
+		goto R_timeout;
+	}
 
 	timeout = TIMEOUT;
 	while ((REG_I2C_STA(I2C_ID) & I2C_STA_MSTACT) && --timeout)
 		udelay(10);
 	if (!timeout){
-      		r_i = 3;
+      		ret = 5; /*wait master inactive timeout.*/
 	      	goto R_timeout;
       	}
 
@@ -370,136 +369,281 @@ static int xfer_read(unsigned char device, unsigned char *buf,
 R_dev_err:
 R_timeout:
 
+	//__reg_printk();
+	__i2c_clear_interrupts(ret,I2C_ID);
 	i2c_init_as_master(I2C_ID,device);
-	if (r_i == 1) {
-		printk("Read i2c device 0x%2x failed in r_i = %d :device no ack.\n",device,r_i);
-	} else if (r_i == 2) {
-		printk("Read i2c device 0x%2x failed in r_i = %d :i2c abort.\n",device,r_i);
-	} else if (r_i == 3) {
-		printk("Read i2c device 0x%2x failed in r_i = %d :waite master inactive timeout.\n",device,r_i);
-	} else {
-		printk("Read i2c device 0x%2x failed in r_i = %d.\n",device,r_i);
+	//dprintk("Read i2c device:0x%2x failed, ret = %d.",device, ret);
+	return -ret;
+}
+
+static int xfer_read(unsigned char device, unsigned char *buf, 
+		     int length, struct jz_i2c *i2c)
+{
+	int timeout,timeout_1,ret = 0;
+	int I2C_ID = i2c->id;
+	
+	/*add for 0v2655 virtual I2C ID on 2010.6.5 and for hi704 on 2010.8.3*/
+	if (device == 0xaa || device == 0xbb)
+		device =0x30;
+	if(device == 0xcc)
+	  device =0x21;
+
+#if defined(CONFIG_TOUCHSCREEN_JZ_MT4D)
+	if ((device == 0x40) && __gpio_get_pin(GPIO_ATTN)) {
+		return -87;
+	}
+#endif
+	i2c_set_target(device,I2C_ID);
+	cmd_flag[I2C_ID] = 0;
+	REG_I2C_INTM(I2C_ID) = 0x50;
+	timeout = TIMEOUT;
+	while (cmd_flag[I2C_ID] != 2 && --timeout) {
+		if (cmd_flag[I2C_ID] == -1) {
+			ret = 1; /*device nack.*/
+			goto R_dev_err;
+		}
+		udelay(1);
+	}
+	if (!timeout) {
+		ret = 2; /*wait interrupt timeout.*/
+	      	goto R_timeout;
+	}
+
+	timeout_1 = TIMEOUT;
+	while (r_cnt[I2C_ID] && --timeout_1) {
+		timeout = TIMEOUT;
+		while ((!(REG_I2C_STA(I2C_ID) & I2C_STA_RFNE)) && (--timeout)) {
+			if ((cmd_flag[I2C_ID] == -1) || 
+			    (REG_I2C_INTST(I2C_ID) & I2C_INTST_TXABT) ||
+			    REG_I2C_TXABRT(I2C_ID)) {
+				ret = 3; /*i2c abort or nack.*/
+				goto R_dev_err;
+			}
+		}
+		if (!timeout){
+			ret = 4;
+			goto R_timeout;
+		}
+
+		if (I2C_ID == 0) {
+			*msg_buf0++ = REG_I2C_DC(I2C_ID) & 0xff;
+		} else {
+			*msg_buf1++ = REG_I2C_DC(I2C_ID) & 0xff;
+		}
+		r_cnt[I2C_ID]--;
+	}
+	if (!timeout_1) {
+		ret = 6; /*can not run here.*/
+		goto R_timeout;
 	}
-	return -ETIMEDOUT;
+
+	timeout = TIMEOUT;
+	while ((REG_I2C_STA(I2C_ID) & I2C_STA_MSTACT) && --timeout)
+		udelay(10);
+	if (!timeout){
+      		ret = 5; /*wait master inactive timeout.*/
+	      	goto R_timeout;
+      	}
+
+	return 0;
+
+R_dev_err:
+R_timeout:
+
+	//__reg_printk();
+	__i2c_clear_interrupts(ret,I2C_ID);
+	i2c_init_as_master(I2C_ID,device);
+	//dprintk("Read i2c device:0x%2x failed, ret = %d.",device, ret);
+	return -ret;
 }
 
 static int xfer_write(unsigned char device, unsigned char *buf,
 		      int length, struct jz_i2c *i2c)
 {
-	int timeout,w_i = 0;
+	int timeout,ret = 0;
 	int I2C_ID = i2c->id;
 
+	/*add for 0v2655 virtual I2C ID on 2010.6.5 and for hi704 on 2010.8.3*/
+	if (device == 0xaa||device == 0xbb)
+		device =0x30;
+	if(device == 0xcc)
+	  device = 0x21;
+
 	i2c_set_target(device,I2C_ID);
 	cmd_flag[I2C_ID] = 0;
-	REG_I2C_INTM(I2C_ID) = 0x10;
+	REG_I2C_INTM(I2C_ID) = 0x50;
 
 	timeout = TIMEOUT;
-	while ((cmd_flag[I2C_ID] != 2) && (timeout--)) {
+	while ((cmd_flag[I2C_ID] != 2) && (--timeout)) {
 		if (cmd_flag[I2C_ID] == -1){
-			w_i = 1;
+			ret = 51; /*device no ack*/
 			goto W_dev_err;
 		}
 		udelay(1);
 	}
 
+       	if (!timeout){
+       		ret = 55; /*wait interrupt timeout.*/
+       		goto W_timeout;
+       	}
+
 	timeout = TIMEOUT;
 	while((!(REG_I2C_STA(I2C_ID) & I2C_STA_TFE)) && --timeout){
 		udelay(10);
 	}
        	if (!timeout){
-       		w_i = 2;
+       		ret = 52; /*wait TF buf empty timeout.*/
        		goto W_timeout;
        	}
 
 	timeout = TIMEOUT;
 	while (__i2c_master_active(I2C_ID) && --timeout);
 	if (!timeout){
-		w_i = 3;
+		ret = 53; /*wait master incative timeout.*/
 		goto W_timeout;
 	}
 
-	if ((length == 1)&&
-	    ((cmd_flag[I2C_ID] == -1) ||
+	if (((cmd_flag[I2C_ID] == -1) || 
 	    (REG_I2C_INTST(I2C_ID) & I2C_INTST_TXABT) ||
 	     REG_I2C_TXABRT(I2C_ID))) {
 		int ret;
-		w_i = 5;
-		__reg_printk();
-		__i2c_clear_interrupts(ret,I2C_ID);
+		ret = 54; /*device nack or Transmite abort.*/
 		goto W_dev_err;
 	}
-
 	return 0;
-
+	
 W_dev_err:
 W_timeout:
-
+	//__reg_printk();
+	__i2c_clear_interrupts(ret,I2C_ID);
 	i2c_init_as_master(I2C_ID,device);
-	if (w_i == 1) {
-		printk("Write i2c device 0x%2x failed in w_i=%d:device no ack.\n",device,w_i);
-	} else if (w_i == 2) {
-		printk("Write i2c device 0x%2x failed in w_i=%d:waite TF buff empty timeout.\n",device,w_i);
-	} else if (w_i == 3) {
-		printk("Write i2c device 0x%2x failed in w_i=%d:waite master inactive timeout.\n",device,w_i);
-	} else if (w_i == 5) {
-		printk("Write i2c device 0x%2x failed in w_i=%d:device no ack or abort.\n",device,w_i);
-	} else  {
-		printk("Write i2c device 0x%2x failed in w_i=%d.\n",device,w_i);
-	}
-
-	return -ETIMEDOUT;
+	//dprintk("Write i2c device:0x%2x failed, ret = %d.",device, ret);
+
+	return -ret;
 }
 
-static int i2c_jz_xfer(struct i2c_adapter *adap, struct i2c_msg *pmsg, int num)
+static int i2c_jz_xfer(struct i2c_adapter *adap, struct i2c_msg *spmsg, int num)
 {
-	int ret, i;
+	int ret = 0, i = 0;
+	int retry = adap->retries;
+	struct i2c_msg *pmsg = spmsg;
 	struct jz_i2c *i2c = adap->algo_data;
 
-	dev_dbg(&adap->dev, "jz4760_xfer: processing %d messages:\n", num);
-	for (i = 0; i < num; i++) {
-		dev_dbg(&adap->dev, " #%d: %sing %d byte%s %s 0x%02x\n", i,
-			pmsg->flags & I2C_M_RD ? "read" : "writ",
-			pmsg->len, pmsg->len > 1 ? "s" : "",
-			pmsg->flags & I2C_M_RD ? "from" : "to",	pmsg->addr);
-
-		if (num != 1) {
-			if (i == (num -1))
-				i2c_ctrl_rest[i2c->id] = 0;
-			else
-				i2c_ctrl_rest[i2c->id] = I2C_CTRL_REST;
+	if (spmsg->addr != current_device[i2c->id]) {
+		current_device[i2c->id] = spmsg->addr;
+		if(spmsg->flags & I2C_M_NOSTART)
+			i2c_ctrl_rest[i2c->id] = I2C_CTRL_REST;
+		else
+			i2c_ctrl_rest[i2c->id] = 0x0;
+		i2c_init_as_master(i2c->id,spmsg->addr);
+	}
 
-			i2c_init_as_master(i2c->id,pmsg->addr);
-		} else {
-			if (pmsg->addr != current_device) {
-				current_device = pmsg->addr;
-				i2c_init_as_master(i2c->id,pmsg->addr);
+    if ((num > 2) || (num < 1)) {
+        printk("error massage num,num need is 1 or 2.\n");
+        return -100;
+    }
+
+	if ((spmsg->flags & I2C_M_NOSTART) && (num == 2)) {
+
+		while (retry--) {
+			pmsg = spmsg;
+			pmsg++;	
+			if (pmsg->len && pmsg->buf) {	/* sanity check */
+				i2c->msg = pmsg;
+				if (i2c->id == 0) {
+					msg_buf0 = pmsg->buf;
+				} else {
+					msg_buf1 = pmsg->buf;
+				}
+				cmd_cnt[i2c->id] = pmsg->len;
+				r_cnt[i2c->id] = pmsg->len;
+
+				ret = xfer_read_nostart(spmsg, pmsg, i2c);
+				if (ret) {
+					udelay(100);
+					continue;
+				} else {
+					return num;
+				}
 			}
 		}
 
-		if (pmsg->len && pmsg->buf) {	/* sanity check */
-			i2c->msg = pmsg;
-			if (i2c->id == 0) {
-				msg_buf0 = pmsg->buf;
-			} else {
-				msg_buf1 = pmsg->buf;
+		if (ret) {
+			if ((ret == -1) || (ret == -2 ) || (ret == -3)){
+				printk("Nostart read i2c device 0x%2x, nack or abort, ret=%d\n",\
+						current_device[i2c->id],ret);
+			} else if (ret == -4) {
+				printk("Nostart read i2c device 0x%2x, wait device date timeout,ret=%d\n",
+						current_device[i2c->id],ret);
+			} else if (ret == -5){
+				printk("Nostart read i2c device 0x%2x, wait mst inactive timeout,ret=%d\n",
+						current_device[i2c->id],ret);
+			} else if (ret == -6) {
+				printk("Nostart read i2c device 0x%2x, can not get here,check your driver,ret=%d\n",
+						current_device[i2c->id],ret);
 			}
-			cmd_cnt[i2c->id] = pmsg->len;
-			r_cnt[i2c->id] = pmsg->len;
+			return ret;
+		}
+	}
 
-			if (pmsg->flags & I2C_M_RD){
-				ret = xfer_read(pmsg->addr, pmsg->buf, pmsg->len,i2c);
-			} else {
-				ret = xfer_write(pmsg->addr, pmsg->buf, pmsg->len,i2c);
+	while (retry--) {
+		pmsg = spmsg;
+		for (i = 0; i < num; i++) {
+			if (pmsg->len && pmsg->buf) {	/* sanity check */
+				i2c->msg = pmsg;
+				if (i2c->id == 0) {
+					msg_buf0 = pmsg->buf;
+				} else {
+					msg_buf1 = pmsg->buf;
+				}
+				cmd_cnt[i2c->id] = pmsg->len;
+				r_cnt[i2c->id] = pmsg->len;
+
+				if (pmsg->flags & I2C_M_RD){
+					ret = xfer_read(pmsg->addr, pmsg->buf, pmsg->len,i2c);
+				} else {
+					ret = xfer_write(pmsg->addr, pmsg->buf, pmsg->len,i2c);
+				}
+				if (ret)
+					break;
 			}
-			if (ret)
-				return ret;
-			/* Wait until transfer is finished */
+			pmsg++;		/* next message */
 		}
-		dev_dbg(&adap->dev, "transfer complete\n");
-		pmsg++;		/* next message */
+
+		if (!ret && (i == num))
+			return i;
+		else
+			udelay(100);
 	}
 
-	return i;
+	if (ret) {
+		if ((ret == -1) || (ret == -2 ) || (ret == -3)){
+			printk("Read i2c device 0x%2x, nack or abort, ret=%d\n",\
+					current_device[i2c->id],ret);
+		} else if((ret == -51) || (ret == -54) || (ret == -55)){
+			printk("Write i2c device 0x%2x, nack or abort, ret=%d\n",\
+					current_device[i2c->id],ret);
+		} else if (ret == -4) {
+			printk("Read i2c device 0x%2x, wait device date timeout,ret=%d\n",
+					current_device[i2c->id],ret);
+		} else if (ret == -5){
+			printk("Read i2c device 0x%2x, wait mst inactive timeout,ret=%d\n",
+					current_device[i2c->id],ret);
+		} else if (ret == -53) {
+			printk("Write i2c device 0x%2x, wait mst inactive timeout,ret=%d\n",
+					current_device[i2c->id],ret);
+		} else if (ret == -6) {
+			printk("Write i2c device 0x%2x, can not get here,check your driver,ret=%d\n",
+					current_device[i2c->id],ret);
+		} else{
+			printk("Write i2c device 0x%2x, wait TF empty timeout,ret=%d\n",
+					current_device[i2c->id],ret);
+		}
+		return ret;
+
+	} else {
+		return i;
+	}
 }
 
 static u32 i2c_jz_functionality(struct i2c_adapter *adap)
@@ -525,20 +669,22 @@ static int i2c_jz_probe(struct platform_device *pdev)
 		goto emalloc;
 	}
 
-	cpm_start_clock(CGM_I2C0);
-	cpm_start_clock(CGM_I2C1);
-
 	i2c->id            = pdev->id;
 	i2c->adap.owner   = THIS_MODULE;
 	i2c->adap.algo    = &i2c_jz_algorithm;
-	i2c->adap.retries = 5;
+	i2c->adap.retries = 6;
 	spin_lock_init(&i2c->lock);
 	init_waitqueue_head(&i2c->wait);
 	sprintf(i2c->adap.name, "jz_i2c-i2c.%u", pdev->id);
 	i2c->adap.algo_data = i2c;
 	i2c->adap.dev.parent = &pdev->dev;
+	if (i2c->id == 0)
+		cpm_start_clock(CGM_I2C0);
+	else
+		cpm_start_clock(CGM_I2C1);
 
 	__gpio_as_i2c(i2c->id);
+
 	i2c_init_as_master(i2c->id,0xff);
 
 	if (plat) {
@@ -553,7 +699,7 @@ static int i2c_jz_probe(struct platform_device *pdev)
 		dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq);
 		goto emalloc;
 	}
-
+	
 	/*
 	 * If "dev->id" is negative we consider it as zero.
 	 * The reason to do so is to avoid sysfs names that only make
diff --git a/drivers/i2c/busses/i2c-jz4810.c b/drivers/i2c/busses/i2c-jz4810.c
new file mode 100644
index 00000000000..eb89b0ddc88
--- /dev/null
+++ b/drivers/i2c/busses/i2c-jz4810.c
@@ -0,0 +1,1175 @@
+
+/*
+ * I2C adapter for the INGENIC I2C bus access.
+ *
+ * Copyright (C) 2006 - 2009 Ingenic Semiconductor Inc.
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/i2c.h>
+#include <linux/i2c-id.h>
+#include <linux/init.h>
+#include <linux/time.h>
+#include <linux/sched.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/kthread.h>
+
+#include <asm/irq.h>
+#include <asm/io.h>
+#include <linux/module.h>
+#include <asm/addrspace.h>
+
+#include <asm/jzsoc.h>
+#include "i2c-jz4810.h"
+
+/* unit: us */
+#define JZ_I2C0_BYTE_DELAY 50000
+#define JZ_I2C1_BYTE_DELAY 100
+#define JZ_I2C2_BYTE_DELAY 100
+
+/* I2C protocol */
+#define I2C_READ_CMD	(1 << 8)
+#define I2C_WRITE_CMD	(0 << 8)
+#define TIMEOUT         0xffff
+#define I2C_CLIENT_NUM  20
+
+//#define DEBUG
+#ifdef DEBUG
+#define dprintk(x...)	printk(x)
+#else
+#define dprintk(x...) do{}while(0)
+#endif
+
+#define DANGERS_WAIT_ON(cond)						\
+	do {								\
+		unsigned long m_start_time = jiffies;			\
+									\
+		while (cond) {						\
+			if (time_after(jiffies, m_start_time + HZ)) {	\
+				printk("WARNING: %s:%d condition never becomes to zero\n", __func__, __LINE__); \
+				m_start_time = jiffies;			\
+			}						\
+		}							\
+	} while(0)
+
+
+struct jz_i2c_dma_info {
+	int chan;
+	volatile atomic_t is_waiting;
+	struct completion comp;
+	int i2c_id;
+	int dma_id;
+	unsigned int dma_req;
+	char name[12];
+	int use_dma;
+};
+
+static struct jz_i2c_dma_info rx_dma_info[6] = {
+	{
+		.chan = -1,
+		.i2c_id = 0,
+		.dma_id = DMA_ID_I2C0_RX,
+		.dma_req = 0x29,
+		.name = "i2c0 read",
+#ifdef CONFIG_JZ_I2C0_USE_DMA
+		.use_dma = 1,
+#else
+		.use_dma = 0,
+#endif
+	},
+	{
+		.chan = -1,
+		.i2c_id = 1,
+		.dma_id = DMA_ID_I2C1_RX,
+		.dma_req = 0x2b,
+		.name = "i2c1 read",
+#ifdef CONFIG_JZ_I2C1_USE_DMA
+		.use_dma = 1,
+#else
+		.use_dma = 0,
+#endif
+	},
+	{  },
+	{  },
+	{  },
+	{
+		.chan = -1,
+		.i2c_id = 5,
+		.dma_id = DMA_ID_I2C2_RX,
+		.dma_req = 0x3b,
+		.name = "i2c2 read",
+#ifdef CONFIG_JZ_I2C2_USE_DMA
+		.use_dma = 1,
+#else
+		.use_dma = 0,
+#endif
+	}
+
+};
+
+static struct jz_i2c_dma_info tx_dma_info[6] = {
+	{
+		.chan = -1,
+		.i2c_id = 0,
+		.dma_id = DMA_ID_I2C0_TX,
+		.dma_req = 0x28,
+		.name = "i2c0 write",
+	},
+	{
+		.chan = -1,
+		.i2c_id = 1,
+		.dma_id = DMA_ID_I2C1_TX,
+		.dma_req = 0x2a,
+		.name = "i2c1 write",
+	},
+	{  },
+	{  },
+	{  },
+	{
+		.chan = -1,
+		.i2c_id = 5,
+		.dma_id = DMA_ID_I2C2_TX,
+		.dma_req = 0x3a,
+		.name = "i2c2 write",
+	}
+};
+
+struct jz_i2c {
+	int                     id;
+	unsigned int            irq;
+	struct i2c_adapter	adap;
+	int (*write)(unsigned char device, unsigned char *buf,
+		     int length, struct jz_i2c *i2c, int restart);
+	int (*read)(unsigned char device, unsigned char *buf,
+		    int length, struct jz_i2c *i2c, int restart);
+	int (*read_offset)(unsigned char device,
+			   unsigned char *offset, int off_len,
+			   unsigned char *buf, int read_len,
+			   struct jz_i2c *i2c);
+	int		byte_delay; /* unit: us */
+};
+
+#define PRINT_REG_WITH_ID(reg_name, id) \
+  printk("" #reg_name "(%d) = 0x%08x\n", id, reg_name(id))
+
+#ifdef DEBUG
+static void jz_dump_i2c_regs(int i2c_id, int line) {
+        printk("***** i2c%d regs, line = %d *****\n", i2c_id, line);
+        PRINT_REG_WITH_ID(REG_I2C_CTRL, i2c_id);
+        PRINT_REG_WITH_ID(REG_I2C_TAR, i2c_id);
+        PRINT_REG_WITH_ID(REG_I2C_SAR, i2c_id);
+        PRINT_REG_WITH_ID(REG_I2C_DC, i2c_id);
+        PRINT_REG_WITH_ID(REG_I2C_SHCNT, i2c_id);
+        PRINT_REG_WITH_ID(REG_I2C_SLCNT, i2c_id);
+        PRINT_REG_WITH_ID(REG_I2C_FHCNT, i2c_id);
+        PRINT_REG_WITH_ID(REG_I2C_FLCNT, i2c_id);
+        PRINT_REG_WITH_ID(REG_I2C_INTST, i2c_id);
+        PRINT_REG_WITH_ID(REG_I2C_INTM, i2c_id);
+        PRINT_REG_WITH_ID(REG_I2C_RXTL, i2c_id);
+        PRINT_REG_WITH_ID(REG_I2C_TXTL, i2c_id);
+        PRINT_REG_WITH_ID(REG_I2C_CINTR, i2c_id);
+        PRINT_REG_WITH_ID(REG_I2C_CRXUF, i2c_id);
+        PRINT_REG_WITH_ID(REG_I2C_CRXOF, i2c_id);
+        PRINT_REG_WITH_ID(REG_I2C_CTXOF, i2c_id);
+        PRINT_REG_WITH_ID(REG_I2C_CRXREQ, i2c_id);
+        PRINT_REG_WITH_ID(REG_I2C_CTXABRT, i2c_id);
+        PRINT_REG_WITH_ID(REG_I2C_CRXDONE, i2c_id);
+        PRINT_REG_WITH_ID(REG_I2C_CACT, i2c_id);
+        PRINT_REG_WITH_ID(REG_I2C_CSTP, i2c_id);
+        PRINT_REG_WITH_ID(REG_I2C_CSTT, i2c_id);
+        PRINT_REG_WITH_ID(REG_I2C_CGC, i2c_id);
+        PRINT_REG_WITH_ID(REG_I2C_ENB, i2c_id);
+        PRINT_REG_WITH_ID(REG_I2C_STA, i2c_id);
+        PRINT_REG_WITH_ID(REG_I2C_TXFLR, i2c_id);
+        PRINT_REG_WITH_ID(REG_I2C_RXFLR, i2c_id);
+        PRINT_REG_WITH_ID(REG_I2C_TXABRT, i2c_id);
+        PRINT_REG_WITH_ID(REG_I2C_DMACR, i2c_id);
+        PRINT_REG_WITH_ID(REG_I2C_DMATDLR, i2c_id);
+        PRINT_REG_WITH_ID(REG_I2C_DMARDLR, i2c_id);
+        PRINT_REG_WITH_ID(REG_I2C_SDASU, i2c_id);
+        PRINT_REG_WITH_ID(REG_I2C_ACKGC, i2c_id);
+        PRINT_REG_WITH_ID(REG_I2C_ENSTA, i2c_id);
+        PRINT_REG_WITH_ID(REG_I2C_SDAHD, i2c_id);
+}
+#else  /* !DEBUG */
+static void jz_dump_i2c_regs(int i2c_id, int line) {
+}
+#endif	/* DEBUG */
+
+static irqreturn_t jz_i2c_irq(int irqno, void *dev_id)
+{
+	volatile int ret;
+	__i2c_clear_interrupts(ret,5);
+
+	return IRQ_HANDLED;
+}
+
+struct i2c_speed {
+	unsigned int speed;
+	unsigned char slave_addr;
+};
+static  struct i2c_speed jz4760_i2c_speed[I2C_CLIENT_NUM];
+static unsigned char current_device[6] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+static int client_cnt = 0;
+static int i2c_ctrl_rest[6]  = {0,0,0,0,0,0};
+
+void i2c_jz_setclk(struct i2c_client *client,unsigned long i2cclk)
+{
+	if (i2cclk > 0 && i2cclk <= 400000) {
+		jz4760_i2c_speed[client_cnt].slave_addr = client->addr;
+		jz4760_i2c_speed[client_cnt].speed      = i2cclk/1000;
+	} else if (i2cclk <= 0) {
+		jz4760_i2c_speed[client_cnt].slave_addr = client->addr;
+		jz4760_i2c_speed[client_cnt].speed      = 100;
+	} else {
+		jz4760_i2c_speed[client_cnt].slave_addr = client->addr;
+		jz4760_i2c_speed[client_cnt].speed      = 400;
+	}
+
+	client_cnt++;
+}
+EXPORT_SYMBOL_GPL(i2c_jz_setclk);
+
+static int i2c_disable(int i2c_id)
+{
+	int timeout = TIMEOUT;
+
+	__i2c_disable(i2c_id);
+	while(__i2c_is_enable(i2c_id) && (timeout > 0)) {
+		udelay(1);
+		timeout--;
+	}
+	if(timeout)
+		return 0;
+	else
+		return 1;
+}
+
+static int i2c_set_clk(int i2c_clk, int i2c_id)
+{
+	int dev_clk_khz = cpm_get_clock(CGU_PCLK) / 1000;
+        int cnt_high = 0;       /* HIGH period count of the SCL clock */
+        int cnt_low = 0;        /* LOW period count of the SCL clock */
+        int cnt_period = 0;     /* period count of the SCL clock */
+
+        if (i2c_clk <= 0 || i2c_clk > 400)
+                goto Set_clk_err;
+
+        /* 1 I2C cycle equals to cnt_period PCLK(i2c_clk) */
+        cnt_period = dev_clk_khz / i2c_clk;
+        if (i2c_clk <= 100) {
+                /* i2c standard mode, the min LOW and HIGH period are 4700 ns and 4000 ns */
+                cnt_high = (cnt_period * 4000) / (4700 + 4000);
+        } else {
+                /* i2c fast mode, the min LOW and HIGH period are 1300 ns and 600 ns */
+                cnt_high = (cnt_period * 600) / (1300 + 600);
+        }
+
+        cnt_low = cnt_period - cnt_high;
+
+	//printk("dev_clk = %d, i2c_clk = %d cnt_period = %d, cnt_high = %d, cnt_low = %d, \n", dev_clk_khz, i2c_clk, cnt_period, cnt_high, cnt_low);
+
+        if (i2c_clk <= 100) {
+                REG_I2C_CTRL(i2c_id) = 0x43 | i2c_ctrl_rest[i2c_id];      /* standard speed mode*/
+                REG_I2C_SHCNT(i2c_id) = I2CSHCNT_ADJUST(cnt_high);
+                REG_I2C_SLCNT(i2c_id) = I2CSLCNT_ADJUST(cnt_low);
+        } else {
+                REG_I2C_CTRL(i2c_id) = 0x45 | i2c_ctrl_rest[i2c_id];       /* high speed mode*/
+                REG_I2C_FHCNT(i2c_id) = I2CFLCNT_ADJUST(cnt_high);
+                REG_I2C_FLCNT(i2c_id) = I2CFLCNT_ADJUST(cnt_low);
+        }
+#ifdef CONFIG_SOC_JZ4810
+	//__i2c_hold_time_enable(i2c_id);
+        //__i2c_hold_time_disable(i2c_id);
+	/*
+	 * a i2c device must internally provide a hold time at least 300ns
+	 * tHD:DAT
+	 *	Standard Mode: min=300ns, max=3450ns
+	 *	Fast Mode: min=0ns, max=900ns
+	 * tSU:DAT
+	 *	Standard Mode: min=250ns, max=infinite
+	 *	Fast Mode: min=100(250ns is recommanded), max=infinite
+	 *
+	 * 1i2c_clk = 10^6 / dev_clk_khz
+	 * on FPGA, dev_clk_khz = 12000, so 1i2c_clk = 1000/12 = 83ns
+	 *
+	 */
+	__i2c_set_setup_time(i2c_id, 4);
+        //__i2c_set_hold_time(i2c_id, 10);
+#endif
+
+	//printk("tSU:DAT = %d tHD:DAT = %d\n",
+	//	REG_I2C_SDASU(i2c_id) & 0xff, REG_I2C_SDAHD(i2c_id) & 0xff);
+	return 0;
+
+Set_clk_err:
+	printk("i2c set sclk faild,i2c_clk=%d KHz,dev_clk=%dKHz.\n", i2c_clk, dev_clk_khz);
+	return -1;
+}
+
+static void i2c_set_target(unsigned char address,int i2c_id)
+{
+	while (!__i2c_txfifo_is_empty(i2c_id) || __i2c_master_active(i2c_id));
+	REG_I2C_TAR(i2c_id) = address;  /* slave id needed write only once */
+}
+
+static void i2c_init_as_master(int i2c_id,unsigned char device)
+{
+
+	int i;
+
+	if(i2c_disable(i2c_id))
+		printk("i2c not disable\n");
+
+	for (i = 0; i < I2C_CLIENT_NUM; i++) {
+		if(device == jz4760_i2c_speed[i].slave_addr) {
+			i2c_set_clk(jz4760_i2c_speed[i].speed,i2c_id);
+			break;
+		}
+	}
+	if (i == I2C_CLIENT_NUM)
+		i2c_set_clk(100,i2c_id);
+	REG_I2C_INTM(i2c_id) = 0x2; /*mask all interrupt*/
+	REG_I2C_TXTL(i2c_id) = 0x15;
+	REG_I2C_RXTL(i2c_id) = 0;
+	REG_I2C_ENB(i2c_id) = 1;   /*enable i2c*/
+}
+
+static irqreturn_t jz_i2c_dma_callback(int irq, void *devid)
+{
+	struct jz_i2c_dma_info *dma_info = (struct jz_i2c_dma_info *)devid;
+	int chan = dma_info->chan;
+
+	disable_dma(chan);
+	if (__dmac_channel_address_error_detected(chan)) {
+		printk("%s: DMAC address error.\n",
+		       __FUNCTION__);
+		__dmac_channel_clear_address_error(chan);
+	}
+	if (__dmac_channel_transmit_end_detected(chan)) {
+		__dmac_channel_clear_transmit_end(chan);
+	}
+
+	if (atomic_read(&dma_info->is_waiting)) {
+		//complete(&(dma_info->comp));
+		atomic_set(&dma_info->is_waiting, 0);
+		wmb();
+	}
+
+	return IRQ_HANDLED;
+}
+
+static void jz_i2c_dma_init_as_write(unsigned short *buf,int length, int bus_id, int need_wait)
+{
+	struct jz_i2c_dma_info *dma_info = tx_dma_info + bus_id;
+
+	__i2c_set_dma_td_level(bus_id, 8); // half FIFO depth, 16/2
+	__i2c_dma_td_enable(bus_id);
+	SETREG8(I2C_CTRL(bus_id),I2C_CTRL_STPHLD);
+
+	dma_cache_wback((unsigned long)buf, length * 2);
+
+	if (need_wait)
+		atomic_set(&dma_info->is_waiting, 1);
+	else
+		atomic_set(&dma_info->is_waiting, 0);
+
+	init_completion(&dma_info->comp);
+
+	/* Init DMA module */
+	REG_DMAC_DMACR(dma_info->chan/HALF_DMA_NUM) = 0;
+	REG_DMAC_DCCSR(dma_info->chan) = 0;
+	REG_DMAC_DRSR(dma_info->chan) = dma_info->dma_req;
+	REG_DMAC_DSAR(dma_info->chan) = CPHYSADDR(buf);
+	REG_DMAC_DTAR(dma_info->chan) = CPHYSADDR(I2C_DC(bus_id));
+	REG_DMAC_DTCR(dma_info->chan) = length;
+	REG_DMAC_DCMD(dma_info->chan) = DMAC_DCMD_SAI | DMAC_DCMD_SWDH_16 | DMAC_DCMD_DWDH_16 | DMAC_DCMD_DS_16BIT | DMAC_DCMD_TIE;
+	REG_DMAC_DCCSR(dma_info->chan) = DMAC_DCCSR_NDES | DMAC_DCCSR_EN;
+	REG_DMAC_DMACR(dma_info->chan/HALF_DMA_NUM) = DMAC_DMACR_DMAE; /* global DMA enable bit */
+
+	if (need_wait) {
+		//wait_for_completion(&dma_info->comp);
+		DANGERS_WAIT_ON(atomic_read(&dma_info->is_waiting));
+		__i2c_dma_td_disable(dma_info->i2c_id);
+	}
+}
+
+static void jz_i2c_dma_init_as_read(unsigned char *buf,int length, int bus_id, int need_wait)
+{
+	struct jz_i2c_dma_info *dma_info = rx_dma_info + bus_id;
+
+	__i2c_set_dma_rd_level(bus_id, 0);
+	__i2c_dma_rd_enable(bus_id);
+
+	memset((void *)buf, 0, length * sizeof(unsigned char));
+	dma_cache_wback_inv((unsigned long)buf, length * sizeof(unsigned char));
+
+	if (need_wait)
+		atomic_set(&dma_info->is_waiting, 1);
+	else
+		atomic_set(&dma_info->is_waiting, 0);
+	init_completion(&dma_info->comp);
+
+	/* Init DMA module */
+	REG_DMAC_DMACR(dma_info->chan/HALF_DMA_NUM) = 0;
+	REG_DMAC_DCCSR(dma_info->chan) = 0;
+	REG_DMAC_DRSR(dma_info->chan) = dma_info->dma_req;
+	REG_DMAC_DSAR(dma_info->chan) = CPHYSADDR(I2C_DC(bus_id));
+	REG_DMAC_DTAR(dma_info->chan) = CPHYSADDR(buf);
+	REG_DMAC_DTCR(dma_info->chan) = length;
+	REG_DMAC_DCMD(dma_info->chan) = DMAC_DCMD_DAI | DMAC_DCMD_SWDH_8 | DMAC_DCMD_DWDH_8 | DMAC_DCMD_DS_8BIT | DMAC_DCMD_TIE;
+	REG_DMAC_DCCSR(dma_info->chan) = DMAC_DCCSR_NDES | DMAC_DCCSR_EN;
+	REG_DMAC_DMACR(dma_info->chan/HALF_DMA_NUM) = DMAC_DMACR_DMAE; /* global DMA enable bit */
+
+	if (need_wait) {
+		//wait_for_completion(&(dma_info->comp));
+		DANGERS_WAIT_ON(atomic_read(&dma_info->is_waiting));
+		__i2c_dma_rd_disable(bus_id);
+	}
+}
+
+static int xfer_read(unsigned char device, unsigned char *buf,
+		     int length, struct jz_i2c *i2c, int restart)
+{
+	int timeout,r_i = 0;
+	int i2c_id = i2c->id;
+	int i;
+	unsigned short *rbuf;
+
+	rbuf = (unsigned short *)kzalloc(sizeof(unsigned short) * length,GFP_KERNEL);
+	for (i = 0; i < length; i++)
+		rbuf[i] = I2C_READ_CMD;
+
+	if (!restart)
+		i2c_set_target(device,i2c_id);
+
+	/* must start read dma first */
+	memset((void *)buf, 0, length * sizeof(unsigned char));
+	jz_i2c_dma_init_as_read(buf,length,i2c_id, 0);
+
+	atomic_set(&rx_dma_info[i2c_id].is_waiting, 1);
+	jz_i2c_dma_init_as_write(rbuf,length,i2c_id, 0);
+	/* must clear STPHLD here! , but we can NOT support more than 2 i2c_msg if we do this */
+	CLRREG8(I2C_CTRL(i2c_id),I2C_CTRL_STPHLD);
+
+	//wait_for_completion(&(rx_dma_info[i2c_id].comp));
+	DANGERS_WAIT_ON(atomic_read(&rx_dma_info[i2c_id].is_waiting));
+	__i2c_dma_rd_disable(i2c_id);
+	__i2c_dma_td_disable(i2c_id);
+
+	timeout = TIMEOUT;
+	while ((REG_I2C_STA(i2c_id) & I2C_STA_MSTACT) && timeout) {
+		timeout --;
+		udelay(10);
+	}
+	if (!timeout){
+		r_i = 3;
+		goto err_timeout;
+	}
+
+	kfree(rbuf);
+	return 0;
+
+err_timeout:
+	i2c_init_as_master(i2c_id,device);
+	if (r_i == 1) {
+		printk("Read i2c device 0x%2x failed in r_i = %d :device no ack.\n",device,r_i);
+	} else if (r_i == 2) {
+		printk("Read i2c device 0x%2x failed in r_i = %d :i2c abort.\n",device,r_i);
+	} else if (r_i == 3) {
+		printk("Read i2c device 0x%2x failed in r_i = %d :waite master inactive timeout.\n",device,r_i);
+	} else {
+		printk("Read i2c device 0x%2x failed in r_i = %d.\n",device,r_i);
+	}
+
+	kfree(rbuf);
+	return -ETIMEDOUT;
+}
+
+
+static int xfer_write(unsigned char device, unsigned char *buf,
+		      int length, struct jz_i2c *i2c, int restart)
+{
+	int timeout,w_i = 0;
+	int i2c_id = i2c->id;
+	int i = 0;
+	unsigned short *wbuf;
+
+	wbuf = (unsigned short *)kzalloc(sizeof(unsigned short) * length,GFP_KERNEL);
+	for (i = 0; i < length; i++)
+		wbuf[i] = I2C_WRITE_CMD | buf[i];
+
+	i2c_set_target(device,i2c_id);
+
+	jz_i2c_dma_init_as_write(wbuf,length,i2c_id, 1);
+	if (!restart)
+		CLRREG8(I2C_CTRL(i2c_id),I2C_CTRL_STPHLD);
+
+	timeout = TIMEOUT;
+	while((!(REG_I2C_STA(i2c_id) & I2C_STA_TFE)) && timeout){
+		timeout --;
+		udelay(10);
+	}
+	if (!timeout){
+		w_i = 2;
+		goto W_timeout;
+	}
+
+	if (!restart) {
+		timeout = TIMEOUT;
+		while (__i2c_master_active(i2c_id) && timeout)
+			timeout--;
+		if (!timeout){
+			w_i = 3;
+			goto W_timeout;
+		}
+	}
+#if 1
+	udelay(500);	      /* the TXABRT bit seems not immediatly seted when error happen */
+	if ((REG_I2C_INTST(i2c_id) & I2C_INTST_TXABT) ||
+	    REG_I2C_TXABRT(i2c_id)) {
+		volatile int ret;
+		w_i = 5;
+		__i2c_clear_interrupts(ret,i2c_id);
+		goto W_dev_err;
+	}
+#endif
+
+	kfree(wbuf);
+	return 0;
+
+W_dev_err:
+W_timeout:
+	jz_dump_i2c_regs(i2c_id, __LINE__);
+	i2c_init_as_master(i2c_id,device);
+	if (w_i == 1) {
+		printk("Write i2c device 0x%2x failed in w_i=%d:device no ack.\n",device,w_i);
+	} else if (w_i == 2) {
+		printk("Write i2c device 0x%2x failed in w_i=%d:waite TF buff empty timeout.\n",device,w_i);
+	} else if (w_i == 3) {
+		printk("Write i2c device 0x%2x failed in w_i=%d:waite master inactive timeout.\n",device,w_i);
+	} else if (w_i == 5) {
+		printk("Write i2c device 0x%2x failed in w_i=%d:device no ack or abort.\n",device,w_i);
+	} else  {
+		printk("Write i2c device 0x%2x failed in w_i=%d.\n",device,w_i);
+	}
+
+	kfree(wbuf);
+	return -ETIMEDOUT;
+}
+
+static int xfer_read_pio(unsigned char device, unsigned char *buf,
+			 int length, struct jz_i2c *i2c, int restart)
+{
+	int timeout,r_i = 0;
+	int i2c_id = i2c->id;
+	int cnt;
+
+	if (length  > 16)     /* FIFO depth is 16 */
+		return -1;
+
+	/* set target address */
+	i2c_set_target(device,i2c_id);
+
+	SETREG8(I2C_CTRL(i2c_id), I2C_CTRL_STPHLD);
+	for (cnt = 0; cnt < length; cnt++) {
+		if (i2c->byte_delay > 1000)
+			mdelay(i2c->byte_delay / 1000);
+		else
+			udelay(i2c->byte_delay);
+		__i2c_write(I2C_READ_CMD, i2c_id);
+	}
+	udelay(100);
+	CLRREG8(I2C_CTRL(i2c_id),I2C_CTRL_STPHLD);
+
+	memset((void *)buf, 0, length * sizeof(unsigned char));
+	for (cnt = 0; cnt < length; cnt++) {
+		while (!(REG_I2C_STA(i2c_id) & I2C_STA_RFNE)) {
+			if ((REG_I2C_INTST(i2c_id) & I2C_INTST_TXABT) ||
+			    REG_I2C_TXABRT(i2c_id)) {
+				int ret;
+				r_i = 2;
+				jz_dump_i2c_regs(i2c_id, __LINE__);
+				__i2c_clear_interrupts(ret,i2c_id);
+				goto R_dev_err;
+			}
+			udelay(10);
+		}
+		buf[cnt] = __i2c_read(i2c_id);
+	}
+
+	timeout = TIMEOUT;
+	while ((REG_I2C_STA(i2c_id) & I2C_STA_MSTACT) && --timeout)
+		udelay(10);
+	if (!timeout){
+		r_i = 3;
+		goto R_timeout;
+	}
+
+	return 0;
+
+ R_dev_err:
+ R_timeout:
+
+	i2c_init_as_master(i2c_id,device);
+	if (r_i == 1) {
+		printk("Read i2c device 0x%2x failed in r_i = %d :device no ack.\n",device,r_i);
+	} else if (r_i == 2) {
+		printk("Read i2c device 0x%2x failed in r_i = %d :i2c abort.\n",device,r_i);
+	} else if (r_i == 3) {
+		printk("Read i2c device 0x%2x failed in r_i = %d :waite master inactive timeout.\n",device,r_i);
+	} else {
+		printk("Read i2c device 0x%2x failed in r_i = %d.\n",device,r_i);
+	}
+
+	return -ETIMEDOUT;
+}
+
+static int xfer_read_offset_pio(unsigned char device,
+				unsigned char *offset, int off_len,
+				unsigned char *buf, int read_len,
+				struct jz_i2c *i2c)
+{
+	int timeout;
+	int i2c_id = i2c->id;
+	int i;
+	unsigned short wbuf[32];
+	int total_len = off_len + read_len;
+
+	if (read_len  > 16)     /* FIFO depth is 16 */
+		return -EINVAL;
+
+	if (total_len > 32)
+		return -EINVAL;
+
+	for (i = 0; i < off_len; i++) {
+		wbuf[i] = I2C_WRITE_CMD | *offset;
+		offset++;
+	}
+	for (i = 0; i < read_len; i++)
+		wbuf[i + off_len] = I2C_READ_CMD;
+
+	/* set target address */
+	i2c_set_target(device,i2c_id);
+
+	SETREG8(I2C_CTRL(i2c_id), I2C_CTRL_STPHLD);
+	for (i = 0; i < total_len; i++) {
+		if (i2c->byte_delay > 1000)
+			mdelay(i2c->byte_delay / 1000);
+		else
+			udelay(i2c->byte_delay);
+		__i2c_write(wbuf[i], i2c_id);
+	}
+	udelay(100);
+	CLRREG8(I2C_CTRL(i2c_id),I2C_CTRL_STPHLD);
+	timeout = TIMEOUT;
+	while((!(REG_I2C_STA(i2c_id) & I2C_STA_TFE)) && --timeout){
+		udelay(10);
+	}
+	if (!timeout){
+		printk("%s:%d: wait tx fifi empty timedout! dev_addr = 0x%02x\n",
+		       __func__, __LINE__, device);
+		goto out;
+	}
+
+	if ((REG_I2C_INTST(i2c_id) & I2C_INTST_TXABT) ||
+	    REG_I2C_TXABRT(i2c_id)) {
+		int ret;
+		printk("%s:%d: TX abart, dev(0x%02x0 no ack!\n",
+		       __func__, __LINE__, device);
+		jz_dump_i2c_regs(i2c_id, __LINE__);
+		__i2c_clear_interrupts(ret,i2c_id);
+		goto out;
+	}
+
+	memset((void *)buf, 0, read_len * sizeof(unsigned char));
+	for (i = 0; i < read_len; i++) {
+		while (!(REG_I2C_STA(i2c_id) & I2C_STA_RFNE)) {
+			if ((REG_I2C_INTST(i2c_id) & I2C_INTST_TXABT) ||
+			    REG_I2C_TXABRT(i2c_id)) {
+				int ret;
+				jz_dump_i2c_regs(i2c_id, __LINE__);
+				__i2c_clear_interrupts(ret,i2c_id);
+				printk("%s:%d: i2c transfer aborted, dev_addr = 0x%02x, intr = 0x%08x.\n",
+				       __func__, __LINE__, device, ret);
+				goto out;
+
+			}
+			udelay(10);
+		}
+		buf[i] = __i2c_read(i2c_id);
+	}
+
+	timeout = TIMEOUT;
+	while ((REG_I2C_STA(i2c_id) & I2C_STA_MSTACT) && --timeout)
+		udelay(10);
+	if (!timeout){
+		printk("%s:%d: waite master inactive timeout, dev_addr = 0x%02x\n",
+		       __func__, __LINE__, device);
+		goto out;
+	}
+
+	return 0;
+
+ out:
+	i2c_init_as_master(i2c_id,device);
+	return -ECANCELED;
+}
+
+static int xfer_write_pio(unsigned char device, unsigned char *buf,
+			  int length, struct jz_i2c *i2c, int restart)
+{
+	int timeout,w_i = 0;
+	int i2c_id = i2c->id;
+	unsigned short wdata;
+	int i = 0;
+
+	i2c_set_target(device,i2c_id);
+
+	SETREG8(I2C_CTRL(i2c_id), I2C_CTRL_STPHLD);
+	for (i = 0; i < length; i++) {
+		wdata = I2C_WRITE_CMD | *buf++;
+		__i2c_write(wdata, i2c_id);
+	}
+	CLRREG8(I2C_CTRL(i2c_id), I2C_CTRL_STPHLD);
+
+	timeout = TIMEOUT;
+	while((!(REG_I2C_STA(i2c_id) & I2C_STA_TFE)) && --timeout){
+		udelay(10);
+	}
+	if (!timeout){
+		w_i = 2;
+		goto W_timeout;
+	}
+
+	timeout = TIMEOUT;
+	while (__i2c_master_active(i2c_id) && --timeout);
+	if (!timeout){
+		w_i = 3;
+		goto W_timeout;
+	}
+
+	if ((REG_I2C_INTST(i2c_id) & I2C_INTST_TXABT) ||
+	    REG_I2C_TXABRT(i2c_id)) {
+		int ret;
+		w_i = 5;
+		jz_dump_i2c_regs(i2c_id, __LINE__);
+		__i2c_clear_interrupts(ret,i2c_id);
+		goto W_dev_err;
+	}
+
+	return 0;
+
+ W_dev_err:
+ W_timeout:
+	i2c_init_as_master(i2c_id,device);
+	if (w_i == 1) {
+		printk("Write i2c device 0x%2x failed in w_i=%d:device no ack.\n",device,w_i);
+	} else if (w_i == 2) {
+		printk("Write i2c device 0x%2x failed in w_i=%d:waite TF buff empty timeout.\n",device,w_i);
+	} else if (w_i == 3) {
+		printk("Write i2c device 0x%2x failed in w_i=%d:waite master inactive timeout.\n",device,w_i);
+	} else if (w_i == 5) {
+		printk("Write i2c device 0x%2x failed in w_i=%d:device no ack or abort.\n",device,w_i);
+	} else  {
+		printk("Write i2c device 0x%2x failed in w_i=%d.\n",device,w_i);
+	}
+
+	return -ETIMEDOUT;
+}
+
+static int i2c_jz_xfer(struct i2c_adapter *adap, struct i2c_msg *pmsg, int num)
+{
+	int ret, i;
+	struct jz_i2c *i2c = adap->algo_data;
+
+	BUG_ON(in_irq());     /* we can not run in hardirq */
+
+	if (num > 2)	      /* sorry, our driver currently can not support more than two message
+			       * if you have such requirements, contact Ingenic for support
+			       */
+		return -EINVAL;
+
+	if (num > 1) {
+		i2c_ctrl_rest[i2c->id] = I2C_CTRL_REST;
+		current_device[i2c->id] = pmsg->addr;
+		i2c_init_as_master(i2c->id,pmsg->addr);
+	} else {
+		if (pmsg->addr != current_device[i2c->id]) {
+			i2c_ctrl_rest[i2c->id] = 0;
+			current_device[i2c->id] = pmsg->addr;
+			i2c_init_as_master(i2c->id,pmsg->addr);
+		}
+	}
+
+	if ((num > 1) &&
+	    i2c->read_offset &&
+	    ((pmsg[0].flags & I2C_M_RD) == 0) &&
+	    (pmsg[1].flags & I2C_M_RD)) {
+		ret = i2c->read_offset(pmsg[0].addr,
+					pmsg[0].buf, pmsg[0].len,
+					pmsg[1].buf, pmsg[1].len,
+					i2c);
+
+		if (ret)
+			return ret;
+		else
+			return num;
+	}
+
+	for (i = 0; i < num; i++) {
+		if (likely(pmsg->len && pmsg->buf)) {	/* sanity check */
+			if (pmsg->flags & I2C_M_RD){
+				ret = i2c->read(pmsg->addr, pmsg->buf, pmsg->len, i2c, (num > 1));
+			} else {
+				ret = i2c->write(pmsg->addr, pmsg->buf, pmsg->len, i2c, (num > 1));
+			}
+			if (ret)
+				return ret;
+		}
+		pmsg++;		/* next message */
+	}
+
+	return i;
+}
+
+//#define I2C_TEST
+#ifdef I2C_TEST
+
+#define EEPROM_PAGE_SIZE 16
+#include <linux/random.h>
+
+static inline unsigned int new_rand(void)
+{
+	return get_random_int();
+}
+
+static int i2c_write_test(struct jz_i2c *i2c, unsigned char dev_addr,
+			  unsigned char start_addr, int len) {
+	struct i2c_msg msg;
+	unsigned char *buf = NULL;
+	int j = 0;
+	int ret = 0;
+
+	printk("write 0x%02x at 0x%02x, len = %d......\n", dev_addr, start_addr, len);
+	buf = (unsigned char *)kmalloc(len + 1, GFP_KERNEL);
+	if (!buf) {
+		printk("malloc buf failed\n");
+		return -ENOMEM;
+	}
+
+	buf[0] = start_addr;
+	for (j = 0; j < len; j++)
+		buf[j + 1] = new_rand() & 0xff;
+
+	msg.addr = dev_addr;
+	msg.buf = buf;
+	msg.len = len + 1;
+	msg.flags = 0;
+
+	printk("write data:\n");
+	for (j = 0; j < len; j++) {
+		printk("0x%02x ", buf[j + 1]);
+		if ((j != 0) && (j % 8 == 7))
+			printk("\n");
+	}
+	printk("\n");
+
+	ret = i2c_transfer(&i2c->adap, &msg, 1);
+	if ( ret != 1)
+		printk("write failed!, ret = %d\n", ret);
+
+	kfree(buf);
+	return ret;
+}
+
+static int i2c_read_test(struct jz_i2c *i2c, unsigned char dev_addr,
+			 unsigned char start_addr, int len) {
+	unsigned char msg1[4] = { 0 };
+	unsigned char *msg2 = NULL;
+	int j = 0;
+	int ret = 0;
+	struct i2c_msg msgs[2];
+
+	printk("read 0x%02x at 0x%02x, len = %d......\n", dev_addr, start_addr, len);
+	msg2 = (unsigned char *)kmalloc(len, GFP_KERNEL);
+	if (!msg2) {
+		printk("malloc msg2 failed!\n");
+		return -ENOMEM;
+	}
+
+
+	msg1[0] = start_addr;
+	msgs[0].addr = dev_addr;
+	msgs[0].buf = msg1;
+	msgs[0].len = 1;
+	msgs[0].flags = 0;
+
+	memset(msg2, 0, len);
+	msgs[1].addr = dev_addr;
+	msgs[1].buf = msg2;
+	msgs[1].len = len;
+	msgs[1].flags = I2C_M_RD;
+
+	ret = i2c_transfer(&i2c->adap, msgs, 2);
+
+	printk("ret = %d data: \n", ret);
+	if (ret == 2) {
+		for (j = 0; j < len; j++) {
+			printk("0x%02x ", msg2[j]);
+			if ((j != 0) && (j % 8 == 7))
+				printk("\n");
+		}
+
+		printk("\n");
+	}
+
+	kfree(msg2);
+	return ret;
+}
+
+static struct timer_list i2c_test_timer[6];
+
+static void i2c_test_func(unsigned long data) {
+	struct jz_i2c *i2c = (struct jz_i2c *)data;
+
+	i2c_write_test(i2c, 0x50, 0, EEPROM_PAGE_SIZE);
+	i2c_read_test(i2c, 0x50, 0, EEPROM_PAGE_SIZE);
+
+	i2c_test_timer[i2c->id].expires = jiffies + HZ;
+	add_timer(&i2c_test_timer[i2c->id]);
+}
+
+static int i2c_test(void *data) {
+	struct jz_i2c *i2c = (struct jz_i2c *)data;
+
+	printk("====start test on i2c%d=====\n", i2c->id);
+
+	init_timer(&i2c_test_timer[i2c->id]);
+	i2c_test_timer[i2c->id].function = i2c_test_func;
+	i2c_test_timer[i2c->id].expires = jiffies + HZ;
+	i2c_test_timer[i2c->id].data = (unsigned long)i2c;
+
+	add_timer(&i2c_test_timer[i2c->id]);
+
+	return 0;
+}
+#else
+#define i2c_test(i) do {  } while(0)
+
+#endif
+
+static u32 i2c_jz_functionality(struct i2c_adapter *adap)
+{
+	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
+}
+
+static const struct i2c_algorithm i2c_jz_algorithm = {
+	.master_xfer	= i2c_jz_xfer,
+	.functionality	= i2c_jz_functionality,
+};
+
+static int i2c_jz_probe(struct platform_device *pdev)
+{
+	struct jz_i2c *i2c;
+	struct i2c_jz_platform_data *plat = pdev->dev.platform_data;
+	struct jz_i2c_dma_info *tx_dma = tx_dma_info + pdev->id;
+	struct jz_i2c_dma_info *rx_dma = rx_dma_info + pdev->id;
+	int ret;
+
+	pdev->id = pdev->id >=0 ? pdev->id : 0;
+
+	if (rx_dma->use_dma) {
+		tx_dma->chan = jz_request_dma(tx_dma->dma_id, tx_dma->name,
+					      jz_i2c_dma_callback, IRQF_DISABLED, tx_dma);
+		printk("i2c%d: tx chan = %d\n", pdev->id, tx_dma->chan);
+		if (tx_dma->chan < 0) {
+			printk("i2c%d: request TX dma failed\n", pdev->id);
+			return -ENODEV;
+		}
+
+		rx_dma->chan = jz_request_dma(rx_dma->dma_id, rx_dma->name,
+					      jz_i2c_dma_callback, IRQF_DISABLED, rx_dma);
+		printk("i2c%d: rx chan = %d\n", pdev->id, rx_dma->chan);
+		if (rx_dma->chan < 0) {
+			printk("i2c%d: request RX dma failed\n", pdev->id);
+			return -ENODEV;
+		}
+	}
+
+	i2c = kzalloc(sizeof(struct jz_i2c), GFP_KERNEL);
+	if (!i2c) {
+		printk("i2c%d: alloc jz_i2c failed!\n", pdev->id);
+		ret = -ENOMEM;
+		goto emalloc;
+	}
+
+	switch(pdev->id) {
+	case 0:
+		cpm_start_clock(CGM_I2C0);
+		i2c->byte_delay = JZ_I2C0_BYTE_DELAY > 100? JZ_I2C0_BYTE_DELAY : 100;
+		break;
+	case 1:
+		cpm_start_clock(CGM_I2C1);
+		i2c->byte_delay = JZ_I2C1_BYTE_DELAY > 100? JZ_I2C1_BYTE_DELAY : 100;
+		break;
+	case 5:
+#ifdef CONFIG_SOC_JZ4810
+		cpm_start_clock(CGM_I2C2);
+		i2c->byte_delay = JZ_I2C2_BYTE_DELAY > 100? JZ_I2C2_BYTE_DELAY : 100;
+#endif
+		break;
+	default:
+		;
+	}
+
+	if (rx_dma->use_dma) {
+		i2c->write = xfer_write;
+		i2c->read = xfer_read;
+		i2c->read_offset = NULL;
+	} else {
+		i2c->write = xfer_write_pio;
+		i2c->read = xfer_read_pio;
+		i2c->read_offset = xfer_read_offset_pio;
+	}
+
+	i2c->id            = pdev->id;
+	i2c->adap.owner   = THIS_MODULE;
+	i2c->adap.algo    = &i2c_jz_algorithm;
+	i2c->adap.retries = 5;
+	sprintf(i2c->adap.name, "jz_i2c-i2c.%u", pdev->id);
+	i2c->adap.algo_data = i2c;
+	i2c->adap.dev.parent = &pdev->dev;
+
+#ifdef CONFIG_SOC_JZ4810
+	if (i2c->id == 5)
+		__gpio_as_i2c2();
+	else
+#endif
+		__gpio_as_i2c(i2c->id);
+	i2c_init_as_master(i2c->id,0xff);
+
+	if (plat)
+		i2c->adap.class = plat->class;
+
+	i2c->irq = platform_get_irq(pdev, 0);
+	ret = request_irq(i2c->irq, jz_i2c_irq, IRQF_DISABLED,
+			  dev_name(&pdev->dev), i2c);
+	if (ret != 0) {
+		dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq);
+		goto irq_err;
+	}
+
+	i2c->adap.nr = pdev->id;
+	if (i2c->adap.nr == 5)
+		i2c->adap.nr = 2;
+
+	ret = i2c_add_numbered_adapter(&i2c->adap);
+	if (ret < 0) {
+		printk(KERN_INFO "i2c%d: Failed to add bus\n", pdev->id);
+		goto eadapt;
+	}
+
+	platform_set_drvdata(pdev, i2c);
+	dev_info(&pdev->dev, "JZ4760 i2c bus driver.\n");
+
+	//if (i2c->id == 1)
+		i2c_test((void*)i2c);
+	return 0;
+
+ eadapt:
+	free_irq(i2c->irq, i2c);
+ emalloc:
+	jz_free_dma(tx_dma->chan);
+	jz_free_dma(rx_dma->chan);
+ irq_err:
+	kfree(i2c);
+	return ret;
+}
+
+static int i2c_jz_remove(struct platform_device *pdev)
+{
+	struct jz_i2c *i2c = platform_get_drvdata(pdev);
+	struct i2c_adapter *adapter = &i2c->adap;
+	int rc;
+
+	rc = i2c_del_adapter(adapter);
+	platform_set_drvdata(pdev, NULL);
+	if (rx_dma_info[i2c->id].chan >= 0)
+		jz_free_dma(rx_dma_info[i2c->id].chan);
+	if (tx_dma_info[i2c->id].chan >= 0)
+		jz_free_dma(tx_dma_info[i2c->id].chan);
+	return rc;
+}
+
+#ifdef  CONFIG_JZ_I2C0
+static struct platform_driver i2c_0_jz_driver = {
+	.probe		= i2c_jz_probe,
+	.remove		= i2c_jz_remove,
+	.driver		= {
+		.name	= "jz_i2c0",
+	},
+};
+#endif
+
+#ifdef  CONFIG_JZ_I2C1
+static struct platform_driver i2c_1_jz_driver = {
+	.probe		= i2c_jz_probe,
+	.remove		= i2c_jz_remove,
+	.driver		= {
+		.name	= "jz_i2c1",
+	},
+};
+#endif
+#ifdef  CONFIG_JZ_I2C2
+static struct platform_driver i2c_2_jz_driver = {
+	.probe		= i2c_jz_probe,
+	.remove		= i2c_jz_remove,
+	.driver		= {
+		.name	= "jz_i2c2",
+	},
+};
+#endif
+
+static int __init i2c_adap_jz_init(void)
+{
+	int ret = 0;
+
+#ifdef  CONFIG_JZ_I2C0
+	ret = platform_driver_register(&i2c_0_jz_driver);
+#endif
+
+#ifdef  CONFIG_JZ_I2C1
+	ret = platform_driver_register(&i2c_1_jz_driver);
+#endif
+#ifdef  CONFIG_JZ_I2C2
+	ret = platform_driver_register(&i2c_2_jz_driver);
+#endif
+	return ret;
+}
+
+static void __exit i2c_adap_jz_exit(void)
+{
+#ifdef  CONFIG_JZ_I2C0
+	platform_driver_unregister(&i2c_0_jz_driver);
+#endif
+
+#ifdef  CONFIG_JZ_I2C1
+	platform_driver_unregister(&i2c_1_jz_driver);
+#endif
+#ifdef  CONFIG_JZ_I2C2
+	platform_driver_unregister(&i2c_2_jz_driver);
+#endif
+}
+
+MODULE_LICENSE("GPL");
+subsys_initcall(i2c_adap_jz_init);
+module_exit(i2c_adap_jz_exit);
diff --git a/drivers/i2c/busses/i2c-jz4810.h b/drivers/i2c/busses/i2c-jz4810.h
new file mode 100644
index 00000000000..eb8611067f9
--- /dev/null
+++ b/drivers/i2c/busses/i2c-jz4810.h
@@ -0,0 +1,20 @@
+/*
+ *  i2c_jz47xx.h
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+#ifndef _I2C_JZ_H_
+#define _I2C_JZ_H_
+
+struct i2c_slave_client;
+
+struct i2c_jz_platform_data {
+	unsigned int		slave_addr;
+	struct i2c_slave_client	*slave;
+	unsigned int		class;
+};
+
+extern void jz_set_i2c_info(struct i2c_jz_platform_data *info);
+#endif
diff --git a/drivers/i2c/i2c-dev.c b/drivers/i2c/i2c-dev.c
index 654820d51b6..0734511ee3a 100644
--- a/drivers/i2c/i2c-dev.c
+++ b/drivers/i2c/i2c-dev.c
@@ -443,7 +443,7 @@ static long i2cdev_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
 	case I2C_SET_CLOCK:
 #if defined(CONFIG_SOC_JZ4750)
  		arg = *(unsigned long *)arg;		
-		i2c_jz_setclk(arg);
+		i2c_jz_setclk(NULL, arg);
 #endif
 		break;
 
diff --git a/drivers/input/keyboard/jz_gpio_keypad.c b/drivers/input/keyboard/jz_gpio_keypad.c
index 10e223dc9e8..77c87e14b00 100644
--- a/drivers/input/keyboard/jz_gpio_keypad.c
+++ b/drivers/input/keyboard/jz_gpio_keypad.c
@@ -54,11 +54,71 @@
 #define KEY_NUM		ARRAY_SIZE(board_buttons)
 
 //#define KEY_FOR_MPLAYER
-#define KEY_FOR_CUR_TEST
+//#define KEY_FOR_CUR_TEST
+#define KEY_FOR_RECOVERY
 /*
  * GPIO Buttons,
  * .code conforms with android/build/target/board/<boardname>/<boardname>-keypad.kl
  */
+#ifdef KEY_FOR_RECOVERY
+ static struct gpio_keys_button board_buttons[] = {
+#ifdef GPIO_CALL
+	{
+		.gpio		= GPIO_CALL,
+		.code   	= KEY_SEND,
+		.desc		= "call key",
+		.active_low	= ACTIVE_LOW_CALL,
+	},
+#endif
+#ifdef GPIO_HOME
+	{
+		.gpio		= GPIO_HOME,
+		.code   	= KEY_HOME,
+		.desc		= "home key",
+		.active_low	= ACTIVE_LOW_HOME,
+	},
+#endif
+#ifdef GPIO_BACK
+	{
+		.gpio		= GPIO_BACK,
+		.code   	= KEY_BACK,
+		.desc		= "back key",
+		.active_low	= ACTIVE_LOW_BACK,
+	},
+#endif
+#ifdef GPIO_MENU
+	{
+		.gpio		= GPIO_MENU,
+		.code   	= KEY_MENU,
+		.desc		= "menu key",
+		.active_low	= ACTIVE_LOW_MENU,
+	},
+#endif
+#ifdef GPIO_ENDCALL
+	{
+		.gpio		= GPIO_ENDCALL,
+		.code   	= KEY_END,
+		.desc		= "end call key",
+		.active_low	= ACTIVE_LOW_ENDCALL,
+	},
+#endif
+#ifdef GPIO_VOLUMEDOWN
+	{
+		.gpio		= GPIO_VOLUMEDOWN,
+		.code   	= KEY_VOLUMEDOWN,
+		.desc		= "volum down key",
+		.active_low	= ACTIVE_LOW_VOLUMEDOWN,
+	},
+	{
+		.gpio		= GPIO_VOLUMEUP,
+		.code   	= KEY_VOLUMEUP,
+		.desc		= "volum up key",
+		.active_low	= ACTIVE_LOW_VOLUMEUP,
+	},
+#endif
+};
+#endif
+
 #ifdef KEY_FOR_MPLAYER
 static struct gpio_keys_button board_buttons[] = {
 	{
@@ -132,6 +192,12 @@ static struct gpio_keys_button board_buttons[] = {
 		.desc		= "hibernation",
 		.active_low	= ACTIVE_LOW_SW8,
 	},
+	{
+		.gpio		= GPIO_SW6,
+		.code   	= KEY_F5,
+		.desc		= "idle",
+		.active_low	= ACTIVE_LOW_SW6,
+	},
 };
 #endif	/* KEY_FOR_CUR_TEST */
 
diff --git a/drivers/input/touchscreen/Kconfig b/drivers/input/touchscreen/Kconfig
index a2f99312b36..62b450c3061 100644
--- a/drivers/input/touchscreen/Kconfig
+++ b/drivers/input/touchscreen/Kconfig
@@ -43,7 +43,7 @@ config TOUCHSCREEN_JZ
 
 config JZ_ADKEY
 	bool "JZ ADKEY"
-	depends on TOUCHSCREEN_JZ || TOUCHSCREEN_JZ4760
+	depends on TOUCHSCREEN_JZ || TOUCHSCREEN_JZ4760 || TOUCHSCREEN_JZ4760B
 	help
           The AD value of the key is get by JZ SAR A/D controller when any ad key
           is pressed down.
@@ -54,6 +54,12 @@ config TOUCHSCREEN_JZ4760
 	help
 	choose the jz4760 touchscreen
 
+config TOUCHSCREEN_JZ4760B
+	tristate "JZ4760B TOUCHSREEN"
+	depends on SOC_JZ4760B
+	help
+	choose the jz4760B touchscreen
+
 config TOUCHSCREEN_AD7877
 	tristate "AD7877 based touchscreens"
 	depends on SPI_MASTER
diff --git a/drivers/input/touchscreen/Makefile b/drivers/input/touchscreen/Makefile
index c9806d37582..3967eabfc32 100644
--- a/drivers/input/touchscreen/Makefile
+++ b/drivers/input/touchscreen/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_TOUCHSCREEN_FUJITSU)	+= fujitsu_ts.o
 obj-$(CONFIG_TOUCHSCREEN_INEXIO)	+= inexio.o
 obj-$(CONFIG_TOUCHSCREEN_JZ)		+= jz_ts.o
 obj-$(CONFIG_TOUCHSCREEN_JZ4760)	+= jz4760_ts.o
+obj-$(CONFIG_TOUCHSCREEN_JZ4760B)	+= jz4760b_ts.o
 obj-$(CONFIG_TOUCHSCREEN_MIGOR)		+= migor_ts.o
 obj-$(CONFIG_TOUCHSCREEN_MTOUCH)	+= mtouch.o
 obj-$(CONFIG_TOUCHSCREEN_MK712)		+= mk712.o
diff --git a/drivers/input/touchscreen/ft5x0x_ts.c b/drivers/input/touchscreen/ft5x0x_ts.c
index 46c44e9339b..08ada869a60 100644
--- a/drivers/input/touchscreen/ft5x0x_ts.c
+++ b/drivers/input/touchscreen/ft5x0x_ts.c
@@ -293,6 +293,8 @@ static int ft5x0x_ts_resume(struct i2c_client *client)
 #define ft5x0x_ts_resume NULL
 #endif  //CONFIG_PM
 
+extern void i2c_jz_setclk(struct i2c_client *client,unsigned long i2cclk);
+
 static int
 ft5x0x_ts_probe(struct i2c_client *client, const struct i2c_device_id *id)
 {
diff --git a/drivers/input/touchscreen/jz4760b_ts.c b/drivers/input/touchscreen/jz4760b_ts.c
new file mode 100644
index 00000000000..1a51db1748c
--- /dev/null
+++ b/drivers/input/touchscreen/jz4760b_ts.c
@@ -0,0 +1,815 @@
+/*
+ * JZ Touch Screen Driver
+ *
+ * Copyright (c) 2005 - 2009  Ingenic Semiconductor Inc.
+ *
+ * Author: Jason <xwang@ingenic.cn> 20090219
+ *         Regen <lhhuang@ingenic.cn> 20090324 add adkey
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/err.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/input.h>
+#include <linux/slab.h>
+#include <linux/interrupt.h>
+#include <linux/clk.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/kthread.h>
+#include <linux/freezer.h>
+
+#include <asm/irq.h>
+#include <asm/gpio.h>
+#include <asm/jzsoc.h>
+
+#undef DEBUG
+//#define DEBUG
+
+#ifdef DEBUG
+#define dprintk(msg...)	printk("jz-sadc: " msg)
+#else
+#define dprintk(msg...)
+#endif
+
+#define TS_NAME "jz-ts"
+
+#define KEY_AUX_INDEX       1
+#define KEY_SCAN_INTERVAL   5
+#define TS_SCAN_INTERVAL	0
+
+/* from qwerty.kl of android */
+#define  DPAD_CENTER            28
+#define  DPAD_DOWN              108
+#define  DPAD_UP                103
+#define  DPAD_LEFT              105
+#define  DPAD_RIGHT             106
+
+/* TS event status */
+#define PENUP			0x00
+#define PENDOWN			0x01
+
+/* Sample times in one sample process	*/
+//#define SAMPLE_TIMES		3
+
+#define SAMPLE_TIMES		5
+#define DROP_SAMPLE_TIMES   1  /* min drop 1 sample */
+#define CAL_SAMPLE_TIMES (SAMPLE_TIMES - DROP_SAMPLE_TIMES)
+#define VIRTUAL_SAMPLE      3 /* min >= 2 */
+/* Min pressure value. If less than it, filt the point.
+ * Mask it if it is not useful for you
+ */
+//#define MIN_PRESSURE		0x100
+
+/* Max delta x distance between current point and last point.	*/
+#define MAX_DELTA_X_OF_2_POINTS	200
+/* Max delta x distance between current point and last point.	*/
+#define MAX_DELTA_Y_OF_2_POINTS	120
+
+/* Max delta between points in one sample process
+ * Verify method :
+ * 	(diff value / min value) * 100 <= MAX_DELTA_OF_SAMPLING
+ */
+#define MAX_DELTA_OF_SAMPLING	20
+
+
+#define TS_ABS(x)       ((x) > 0 ? (x): -(x))
+#define DIFF(a,b)		(((a)>(b))?((a)-(b)):((b)-(a)))
+#define MIN(a,b)		(((a)<(b))?(a):(b))
+
+
+/************************************************************************/
+/*	SAR ADC OPS							*/
+/************************************************************************/
+
+typedef struct datasource {
+	u16 xbuf;
+	u16 ybuf;
+	u16 zbuf;
+	u16 reserve;
+}datasource_t;
+struct ts_event {
+	u16 status;
+	u16 x;
+	u16 y;
+	u16 pressure;
+	u16 pad;
+};
+#define TOUCH_TYPE 1
+
+//sadc touch fifo size 2 * 32bit
+#define FIFO_MAX_SIZE 2
+
+/*
+ * TS deriver
+ */
+struct jz_ts_t {
+	int touch_cal_count;
+
+	unsigned int ts_fifo[FIFO_MAX_SIZE][CAL_SAMPLE_TIMES];
+	datasource_t data_s;
+	struct ts_event event;
+	int event_valid;
+
+	int cal_type; /* current calibrate type */
+	//struct timer_list acq_timer;	// Timer for triggering acquisitions
+#ifdef CONFIG_JZ_ADKEY
+	struct timer_list key_timer;	// for adkey
+	int active_low;		// for adkey's interrupt pin
+#endif
+	wait_queue_head_t wait;		// read wait queue
+	spinlock_t lock;
+
+	/* Following 4 members use to pass arguments from u-boot to tell us the ts data.
+	 * But in Android we do not use them.
+	 */
+	/*
+	   int minx, miny, maxx, maxy;
+	   */
+	int first_read;
+
+	char	phys[32];
+	struct input_dev *input_dev; /* for touch screen */
+	struct input_dev *input_dev1; /* for adkey */
+};
+
+static struct jz_ts_t *jz_ts;
+
+/*
+ * TS Event type
+ */
+
+#ifdef CONFIG_JZ_ADKEY
+struct ad_keys_button {
+	int code;		/* input event code */
+	int val;                /* the ad value of the key */
+	int fuzz;               /* the error(+-fuzz) allowed of the ad value of the key */
+};
+static struct ad_keys_button ad_buttons[] = {
+	{
+		.code = DPAD_LEFT,
+		.val = DPAD_LEFT_LEVEL,
+		.fuzz = 40,
+	},
+	{
+		.code = DPAD_DOWN,
+		.val = DPAD_DOWN_LEVEL,
+		.fuzz = 40,
+	},
+	{
+		.code = DPAD_UP,
+		.val = DPAD_UP_LEVEL,
+		.fuzz = 40,
+	},
+	{
+		.code = DPAD_CENTER,
+		.val = DPAD_CENTER_LEVEL,
+		.fuzz = 40,
+	},
+	{
+		.code = DPAD_RIGHT,
+		.val = DPAD_RIGHT_LEVEL,
+		.fuzz = 40,
+	},
+};
+#define KEY_NUM (sizeof(ad_buttons) / sizeof(struct ad_keys_button))
+#endif
+
+static DECLARE_WAIT_QUEUE_HEAD (sadc_wait_queue);
+
+extern unsigned int (*codec_read_battery)(void);
+#if 0
+static void reg_debug(void)
+{
+	printk("\t####CTRL####################################################\n");
+	printk("\tPEND %s,   ", REG_SADC_CTRL & SADC_CTRL_PENDM ? "masked" : "enabled");
+	printk("PENU %s,   ", REG_SADC_CTRL & SADC_CTRL_PENUM ? "masked" : "enabled");
+	printk("TSRDY %s\n", REG_SADC_CTRL & SADC_CTRL_TSRDYM ? "masked" : "enabled");
+	printk("\t----STATE---------------------------------------------------\n");
+	printk("\tIRQ actived: %s,   %s,   %s\n",
+			REG_SADC_STATE & SADC_STATE_PEND ? "pen down" : "        ",
+			REG_SADC_STATE & SADC_STATE_PENU ? "pen up  " : "        ",
+			REG_SADC_STATE & SADC_STATE_TSRDY ? "sample  " : "        ");
+	printk("\t############################################################\n");
+}
+#endif
+/*
+ * set adc clock to 24MHz/div. A/D works at freq between 500KHz to 8MHz.
+ */
+static void sadc_init_clock(int div)
+{
+	cpm_start_clock(CGM_SADC);
+
+	div = 120 - 1;	/* working at 100 KHz */
+	CMSREG32(SADC_ADCLK, div, ADCLK_CLKDIV_MASK);
+}
+
+static inline void sadc_start_aux(void)
+{
+	SETREG8(SADC_ADENA, ADENA_AUXEN);
+}
+
+static inline void sadc_start_pbat(void)
+{
+	SETREG8(SADC_ADENA, ADENA_VBATEN);      /* Enable pbat adc */
+}
+
+static inline void ts_enable_pendown_irq(void)
+{
+	CLRREG8(SADC_ADCTRL, ADCTRL_PENDM);
+}
+
+static inline void ts_enable_penup_irq(void)
+{
+	CLRREG8(SADC_ADCTRL, ADCTRL_PENUM);
+}
+
+static inline void ts_disable_pendown_irq(void)
+{
+	SETREG8(SADC_ADCTRL, ADCTRL_PENDM);
+}
+
+static inline void ts_disable_penup_irq(void)
+{
+	SETREG8(SADC_ADCTRL, ADCTRL_PENUM);
+}
+
+static inline void sadc_enable_ts(void)
+{
+	SETREG8(SADC_ADENA, ADENA_TCHEN);
+}
+
+static inline void sadc_disable_ts(void)
+{
+	CLRREG8(SADC_ADENA, ADENA_TCHEN);
+}
+
+static inline void sadc_start_ts(void)
+{
+        unsigned int tmp;
+
+        OUTREG16(SADC_ADSAME, 1);       /* about 0.02 ms,you can change it */
+        OUTREG16(SADC_ADWAIT, 500);     /* about 3.33 ms,you can change it */
+
+        /* set ts mode and sample times */
+        tmp = ADCFG_SPZZ | ADCFG_XYZ_XYZ1Z2 | ADCFG_SNUM(SAMPLE_TIMES);
+        OUTREG32(SADC_ADCFG, tmp);
+
+        /* mask all the intr except PEN-DOWN */
+        tmp = ADCTRL_SLPENDM | ADCTRL_PENUM | ADCTRL_DTCHM | ADCTRL_VRDYM | ADCTRL_ARDYM;
+        OUTREG8(SADC_ADCTRL, tmp);
+
+        /* clear all the intr status if needed*/
+        OUTREG8(SADC_ADSTATE, INREG8(SADC_ADSTATE));
+
+        sadc_enable_ts();
+}
+
+/**
+ * Read the battery voltage
+ */
+unsigned int jz_read_battery(void)
+{
+	unsigned int timeout = 0x3fff;
+	u16 pbat;
+
+	sadc_start_pbat();
+	udelay(300);
+
+	while(!(INREG8(SADC_ADSTATE) & ADSTATE_VRDY) && --timeout);
+
+    if (!timeout)
+        printk(KERN_ERR "Reading battery timeout!");
+
+	pbat = INREG16(SADC_ADVDAT) & ADVDAT_VDATA_MASK;
+
+	OUTREG8(SADC_ADSTATE, ADSTATE_VRDY);
+	CLRREG8(SADC_ADENA, ADENA_VBATEN); // hardware may not shut down really
+
+	return pbat;
+}
+
+/**
+ * Read the aux voltage
+ */
+unsigned short jz_read_aux(int index)
+{
+	unsigned int timeout = 0x3ff;
+	u16 val;
+
+	CMSREG32(SADC_ADCFG, index, ADCFG_CMD_MASK);
+	sadc_start_aux();
+	udelay(300);
+
+	while(!(INREG8(SADC_ADSTATE) & ADSTATE_ARDY) && --timeout);
+
+    if (!timeout)
+        printk(KERN_ERR "Reading aux timeout!");
+
+	val = INREG16(SADC_ADADAT) & ADADAT_ADATA_MASK;
+
+	OUTREG8(SADC_ADSTATE, ADSTATE_ARDY);
+	CLRREG8(SADC_ADENA, ADENA_AUXEN); // hardware may not shut down really
+
+	dprintk("read aux val=%d\n", val);    
+ 	return val;
+}
+
+static inline void ts_data_ready(void)
+{
+	SETREG8(SADC_ADCTRL, ADCTRL_DTCHM);
+}
+
+#ifdef CONFIG_JZ_ADKEY
+
+static unsigned int key_scan(int ad_val)
+{
+	int i;
+
+	for(i = 0; i<KEY_NUM; i++) {
+		if((ad_buttons[i].val + ad_buttons[i].fuzz >= ad_val) &&
+				(ad_val >=ad_buttons[i].val - ad_buttons[i].fuzz)) {
+			return ad_buttons[i].code;
+		}
+	}
+	return -1;
+}
+
+static void key_timer_callback(unsigned long data)
+{
+	struct jz_ts_t *ts = (struct jz_ts_t *)data;
+	int state;
+	int active_low = ts->active_low;
+	int ad_val, code;
+	static int old_code;
+
+	state = __gpio_get_pin(GPIO_ADKEY_INT);
+	ad_val = jz_read_aux(KEY_AUX_INDEX);
+
+	if (active_low) {
+		if (state == 0) {
+			/* press down */
+			code = key_scan(ad_val);
+			old_code = code;
+			input_report_key(ts->input_dev1, code, 1);
+			dprintk("code=%d\n",code);
+			//input_sync(ts->input_dev1);
+			mod_timer(&ts->key_timer, jiffies + KEY_SCAN_INTERVAL);
+		} else {
+			/* up */
+			input_report_key(ts->input_dev1, old_code, 0);
+			//input_sync(ts->input_dev1);
+			//udelay(1000);
+			__gpio_as_irq_fall_edge(GPIO_ADKEY_INT);
+		}
+	} else {
+		if (state == 1) {
+			/* press down */
+			code = key_scan(ad_val);
+			old_code = code;
+			input_report_key(ts->input_dev1, code, 1);
+			//input_sync(ts->input_dev1);
+			mod_timer(&ts->key_timer, jiffies + KEY_SCAN_INTERVAL);
+		} else {
+			/* up */
+			input_report_key(ts->input_dev1, old_code, 0);
+			//input_sync(ts->input_dev1);
+			//udelay(1000);
+			__gpio_as_irq_rise_edge(GPIO_ADKEY_INT);
+		}
+	}
+}
+
+static irqreturn_t key_interrupt(int irq, void * dev_id)
+{
+	struct jz_ts_t *ts = dev_id;
+
+
+	__gpio_as_input(GPIO_ADKEY_INT);
+
+	if (!timer_pending(&ts->key_timer))
+        mod_timer(&ts->key_timer, jiffies + KEY_SCAN_INTERVAL);
+	return IRQ_HANDLED;
+}
+#endif
+
+/************************************************************************/
+/*	Touch Screen module						*/
+/************************************************************************/
+
+#define TSMAXX		3920
+#define TSMAXY		3700
+#define TSMAXZ		(1024) /* measure data */
+
+#define TSMINX		150
+#define TSMINY		270
+#define TSMINZ		0
+
+
+#define SCREEN_MAXX	1023
+#define SCREEN_MAXY	1023
+#define PRESS_MAXZ      256
+
+static unsigned long transform_to_screen_x(struct jz_ts_t *ts, unsigned long x )
+{
+	/* Now we don't need u-boot to tell us the ts data.	*/
+	/*
+	   if (ts->minx)
+	   {
+	   if (x < ts->minx) x = ts->minx;
+	   if (x > ts->maxx) x = ts->maxx;
+
+	   return (x - ts->minx) * SCREEN_MAXX / (ts->maxx - ts->minx);
+	   }
+	   else
+	   {
+	   */
+	if (x < TSMINX) x = TSMINX;
+	if (x > TSMAXX) x = TSMAXX;
+
+	return (x - TSMINX) * SCREEN_MAXX / (TSMAXX - TSMINX);
+	/*
+	   }
+	   */
+}
+
+static unsigned long transform_to_screen_y(struct jz_ts_t *ts, unsigned long y)
+{
+	/* Now we don't need u-boot to tell us the ts data.	*/
+	/*
+	   if (ts->miny)
+	   {
+	   if (y < ts->miny) y = ts->miny;
+	   if (y > ts->maxy) y = ts->maxy;
+
+	   return (ts->maxy - y) * SCREEN_MAXY / (ts->maxy - ts->miny);
+	   }
+	   else
+	   {
+	   */
+	if (y < TSMINY) y = TSMINY;
+	if (y > TSMAXY) y = TSMAXY;
+
+	return (TSMAXY - y) * SCREEN_MAXY / (TSMAXY - TSMINY);
+	/*
+	   }
+	   */
+}
+static unsigned long transform_to_screen_z(struct jz_ts_t *ts, unsigned long z){
+	if(z < TSMINZ) z = TSMINZ;
+	if (z > TSMAXY) z = TSMAXY;
+	return (TSMAXZ - z) * PRESS_MAXZ / (TSMAXZ - TSMINZ);
+}
+/* R plane calibrate,please look up spec 11th page*/
+
+#define Yr_PLANE  480
+#define Xr_PLANE  800
+
+#define Touch_Formula_One(z1,z2,ref,r) ({	\
+		int z;					\
+		if((z1) > 0){				\
+		z = ((ref) * (z2)) / (z1);		\
+		if((z2) > (z1)) z = (z * r - (ref) * r) / (4096);	\
+		else z = 0;				\
+		}else					\
+		z = 4095;				\
+		z;					\
+		})
+
+
+static int ts_data_filter(struct jz_ts_t *ts){
+	int i,xt = 0,yt = 0,zt1 = 0,zt2 = 0,zt3 = 0,zt4 = 0,t1_count = 0,t2_count = 0,z;
+
+	datasource_t *ds = &ts->data_s;
+	int t,xmin = 0x0fff,ymin = 0x0fff,xmax = 0,ymax = 0;//,z1min = 0xfff,z1max = 0,z2min = 0xfff,z2max = 0;
+
+	/* fifo high 16 bit = y,fifo low 16 bit = x */
+
+	for(i = 0;i < CAL_SAMPLE_TIMES;i++){
+
+		t = (ts->ts_fifo[0][i] & 0x0fff);
+#if (CAL_SAMPLE_TIMES >= 3)
+		if(t > xmax) xmax = t;
+		if(t < xmin) xmin = t;
+#endif
+		xt += t;
+		t = (ts->ts_fifo[0][i] >> 16) & 0x0fff;
+#if (CAL_SAMPLE_TIMES >= 3)
+		if(t > ymax) ymax = t;
+		if(t < ymin) ymin = t;
+#endif
+
+		yt += t;
+		if(ts->ts_fifo[1][i] & 0x8000)
+		{
+			t = (ts->ts_fifo[1][i] & 0x0fff);
+			zt1 += t;
+
+			t = (ts->ts_fifo[1][i] >> 16) & 0x0fff;
+			zt2 += t;
+
+			t1_count++;
+		}else
+		{
+			t = (ts->ts_fifo[1][i] & 0x0fff);
+			zt3 += t;
+
+			t = (ts->ts_fifo[1][i] >> 16) & 0x0fff;
+			zt4 += t;
+
+			t2_count++;
+		}
+	}
+#if (CAL_SAMPLE_TIMES >= 3)
+	xt = xt - xmin - xmax;
+	yt = yt - ymin - ymax;
+#endif
+
+	xt /= (CAL_SAMPLE_TIMES - 2);
+	yt /= (CAL_SAMPLE_TIMES - 2);
+	if(t1_count > 0)
+	{
+		zt1 /= t1_count;
+		zt2 /= t1_count;
+		zt1 = Touch_Formula_One(zt1,zt2,xt,Xr_PLANE);
+	}
+	if(t2_count)
+	{
+		zt3 /= t2_count;
+		zt4 /= t2_count;
+		zt3 = Touch_Formula_One(zt3,zt4,yt,Yr_PLANE);
+	}
+	if((t1_count) && (t2_count))
+		z = (zt1 + zt3) / 2;
+	else if(t1_count)
+		z = zt1;
+	else if(t2_count)
+		z = zt3;
+	else
+		z = 0;
+
+	ds->xbuf = xt;
+	ds->ybuf = yt;
+	ds->zbuf = z;
+	return 1;
+
+}
+static void ts_transform_data(struct jz_ts_t *ts){
+	struct ts_event *event = &ts->event;
+	event->x = transform_to_screen_x(ts,ts->data_s.xbuf);
+	event->y = transform_to_screen_y(ts,ts->data_s.ybuf);
+	event->pressure = transform_to_screen_z(ts,ts->data_s.zbuf);
+	if(event->pressure == 0) event->pressure = 1;
+}
+static void handle_ts_event(struct jz_ts_t *ts){
+	struct ts_event *event = &ts->event;
+	input_report_abs(ts->input_dev, ABS_X, event->x);
+	input_report_abs(ts->input_dev, ABS_Y, event->y);
+	input_report_abs(ts->input_dev, ABS_PRESSURE, event->pressure);
+
+	/* Android need it ... */
+	input_report_key(ts->input_dev, BTN_TOUCH, 1);
+	input_sync(ts->input_dev);
+
+	//printk("event->x = %d,event->y = %d event->pressure = %d\n",event->x,event->y,event->pressure);
+}
+
+static void handle_touch(struct jz_ts_t *ts, unsigned int *data, int size){
+	/* drop no touch calibrate points */
+	if(ts->cal_type & (~TOUCH_TYPE))
+		ts->cal_type |= ~TOUCH_TYPE;
+	if(ts->event_valid){
+		handle_ts_event(ts);
+		ts->event_valid = 0;
+	}
+
+	if(ts->touch_cal_count >= DROP_SAMPLE_TIMES)
+	{
+		if(ts->touch_cal_count < SAMPLE_TIMES){
+			ts->ts_fifo[0][ts->touch_cal_count - DROP_SAMPLE_TIMES] = data[0];
+			ts->ts_fifo[1][ts->touch_cal_count - DROP_SAMPLE_TIMES] = data[1];
+		}else
+		{
+			/* drop sample*/
+			if(ts->cal_type & TOUCH_TYPE){
+				if(ts_data_filter(ts)){
+					ts->event_valid = 1;
+					ts_transform_data(ts);
+				}
+
+			}
+			ts->touch_cal_count = 0;
+		}
+	}
+	ts->touch_cal_count++;
+}
+
+static irqreturn_t sadc_interrupt(int irq, void * dev_id)
+{
+        unsigned char tmp;
+	struct jz_ts_t *ts = dev_id;
+	unsigned int state;
+	unsigned int fifo[FIFO_MAX_SIZE];
+	static int pen_is_down = 0;
+
+	spin_lock_irq(&ts->lock);
+
+	state = INREG8(SADC_ADSTATE) & (~INREG8(SADC_ADCTRL));
+	/* first handle pen up interrupt */
+	if(state & ADSTATE_PENU){
+		/* REG_SADC_CTRL used in pendown & penup mutex */
+
+		/*  mask pen up and wait pen down */
+		tmp = INREG8(SADC_ADCTRL);
+		tmp = (tmp | ADCTRL_PENUM) & ~ADCTRL_PENDM;
+		OUTREG8(SADC_ADCTRL, tmp);
+
+		if(pen_is_down == 1)
+		{
+		        SETREG8(SADC_ADCTRL, ADCTRL_DTCHM);
+			{
+				input_report_abs(ts->input_dev, ABS_PRESSURE, 0);
+				/* Android need it ... */
+				input_report_key(ts->input_dev, BTN_TOUCH, 0);
+				input_sync(ts->input_dev);
+				ts->cal_type &= ~TOUCH_TYPE;
+				ts->event_valid = 0;
+			}
+
+		}
+		pen_is_down = 0;
+	}else if(state & ADSTATE_PEND){
+		/* REG_SADC_CTRL used in pendown & penup mutex */
+		tmp = INREG8(SADC_ADCTRL);
+		tmp = (tmp | ADCTRL_PENDM) & ~(ADCTRL_PENUM | ADCTRL_DTCHM);
+		OUTREG8(SADC_ADCTRL, tmp);
+
+		if(pen_is_down == 0){
+			/*  mask pen down and wait pen up */
+			pen_is_down = 1;
+			ts->event_valid = 0;
+			ts->cal_type |= TOUCH_TYPE;
+			ts->touch_cal_count = 0;
+		}
+		state |= ADSTATE_PENU;
+		state |= ADSTATE_SLPEND;
+	}else if(state & ADSTATE_DTCH){
+
+		fifo[0] = INREG32(SADC_ADTCH);
+		fifo[1] = INREG32(SADC_ADTCH);
+
+		/* alone here clear state */
+		OUTREG8(SADC_ADSTATE, ADSTATE_DTCH);
+
+		if(pen_is_down)
+			handle_touch(ts,fifo,2);
+
+	}else if(state & ADSTATE_SLPEND){
+		SETREG8(SADC_ADCTRL, ADSTATE_SLPEND);
+
+	}
+	//when data count not is set_count penup is not clear;
+	if(!(state & ADSTATE_DTCH))
+		OUTREG8(SADC_ADSTATE, state);
+
+	spin_unlock_irq(&ts->lock);
+
+	return IRQ_HANDLED;
+}
+
+static int __init jz_ts_init(void)
+{
+	struct input_dev	*input_dev;
+	struct jz_ts_t		*ts;
+	int	error;
+
+	ts = jz_ts = kzalloc(sizeof(struct jz_ts_t), GFP_KERNEL);
+	input_dev = input_allocate_device();
+	if (!ts || !input_dev)
+		return -ENOMEM;
+
+	input_dev->name = "touchscreen"; /* Android will load /system/usr/keychars/qwerty.kcm.bin by default */
+	input_dev->phys = ts->phys;
+
+	/*
+old:
+input_dev->evbit[0] = BIT(EV_KEY) | BIT(EV_ABS);
+input_dev->keybit[BIT_WORD(BTN_TOUCH)] = BIT_MASK(BTN_TOUCH);
+*/
+
+	/* For Android */
+	set_bit(EV_ABS, input_dev->evbit);
+	set_bit(ABS_X, input_dev->absbit);
+	set_bit(ABS_Y, input_dev->absbit);
+	set_bit(ABS_PRESSURE, input_dev->absbit);
+	set_bit(EV_KEY, input_dev->evbit);
+	set_bit(BTN_TOUCH, input_dev->keybit);
+
+	input_set_abs_params(input_dev, ABS_X, 0, SCREEN_MAXX + 1, 0, 0);
+	input_set_abs_params(input_dev, ABS_Y, 0, SCREEN_MAXY + 1, 0, 0);
+	input_set_abs_params(input_dev, ABS_PRESSURE, 0, PRESS_MAXZ + 1, 0, 0);
+	input_set_drvdata(input_dev, ts);
+	error = input_register_device(input_dev);
+
+	strcpy(ts->phys, "input/ts0");
+	spin_lock_init(&ts->lock);
+
+	ts->input_dev = input_dev;
+
+#ifdef CONFIG_JZ_ADKEY
+	ts->input_dev1 = input_allocate_device();
+	if (!ts->input_dev1)
+		return -ENOMEM;
+
+    ts->input_dev1->name = "adkey";
+	set_bit(EV_KEY, ts->input_dev1->evbit);
+	set_bit(DPAD_CENTER, ts->input_dev1->keybit);
+	set_bit(DPAD_DOWN, ts->input_dev1->keybit);
+	set_bit(DPAD_UP, ts->input_dev1->keybit);
+	set_bit(DPAD_LEFT, ts->input_dev1->keybit);
+	set_bit(DPAD_RIGHT, ts->input_dev1->keybit);
+	error = input_register_device(ts->input_dev1);
+#endif
+
+	if (error) {
+		printk("Input device register failed !\n");
+		goto err_free_dev;
+	}
+
+	sadc_init_clock(6);
+
+#if defined(CONFIG_SOC_JZ4760B)
+	CLRREG8(SADC_ADENA, ADENA_POWER);
+	CLRREG32(CPM_LCR, LCR_VBATIR);
+	mdelay(50);
+#endif
+
+	OUTREG8(SADC_ADCTRL, ADCTRL_MASK_ALL);
+
+	error = request_irq(IRQ_SADC, sadc_interrupt, IRQF_DISABLED, TS_NAME, ts);
+	if (error) {
+		pr_err("unable to get PenDown IRQ %d", IRQ_SADC);
+		goto err_free_irq;
+	}
+	ts->cal_type = 0;
+
+#ifdef CONFIG_JZ_ADKEY
+	// Init key acquisition timer function
+	init_timer(&ts->key_timer);
+	ts->key_timer.function = key_timer_callback;
+	ts->key_timer.data = (unsigned long)ts;
+	ts->active_low = ACTIVE_LOW_ADKEY;
+
+	error = request_irq(IRQ_GPIO_0 + GPIO_ADKEY_INT, key_interrupt, IRQF_DISABLED, "jz-adkey", ts);
+	if (error) {
+		pr_err("unable to get AD KEY IRQ %d", IRQ_GPIO_0 + GPIO_ADKEY_INT);
+		goto err_free_irq;
+	}
+
+	__gpio_disable_pull(GPIO_ADKEY_INT);
+
+	if(ts->active_low)
+		__gpio_as_irq_fall_edge(GPIO_ADKEY_INT);
+	else
+		__gpio_as_irq_rise_edge(GPIO_ADKEY_INT);
+
+#endif
+	sadc_start_ts();
+
+	printk("input: JZ Touch Screen registered.\n");
+
+	return 0;
+
+err_free_irq:
+	free_irq(IRQ_SADC, ts);
+#ifdef CONFIG_JZ_ADKEY
+	free_irq(IRQ_GPIO_0 + GPIO_ADKEY_INT, ts);
+#endif
+err_free_dev:
+	input_free_device(ts->input_dev);
+	kfree(ts);
+	return 0;
+}
+
+static void __exit jz_ts_exit(void)
+{
+	ts_disable_pendown_irq();
+	ts_disable_penup_irq();
+	sadc_disable_ts();
+	free_irq(IRQ_SADC, jz_ts);
+	input_unregister_device(jz_ts->input_dev);
+
+}
+
+module_init(jz_ts_init);
+module_exit(jz_ts_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("JZ TouchScreen Driver");
+MODULE_AUTHOR("Jason <xwang@ingenic.com>");
diff --git a/drivers/media/video/Kconfig b/drivers/media/video/Kconfig
index 93a74b9292f..59ba542ca58 100644
--- a/drivers/media/video/Kconfig
+++ b/drivers/media/video/Kconfig
@@ -625,11 +625,6 @@ config VIDEO_JZ4740_CIM
 	depends on VIDEO_V4L2 && FB_JZSOC && SOC_JZ4740
 	select VIDEO_JZ_SENSOR
 
-config VIDEO_JZ4750_CIM
-	tristate 'JzSOC Camera Interface Module (CIM) support'
-	depends on VIDEO_V4L2 && FB_JZSOC && (SOC_JZ4750 || SOC_JZ4750D)
-	select VIDEO_JZ_SENSOR
-
 config VIDEO_JZ_SENSOR
 	tristate "Jz generic camera sensor driver"
 
diff --git a/drivers/media/video/Makefile b/drivers/media/video/Makefile
index 77a294482e8..eab0d9bd91e 100644
--- a/drivers/media/video/Makefile
+++ b/drivers/media/video/Makefile
@@ -82,7 +82,6 @@ obj-$(CONFIG_SOC_CAMERA_TW9910)		+= tw9910.o
 
 obj-$(CONFIG_VIDEO_JZ4730_CIM) += jz4730_cim.o
 obj-$(CONFIG_VIDEO_JZ4740_CIM) += jz4740_cim.o
-obj-$(CONFIG_VIDEO_JZ4750_CIM) += jz4750_cim.o
 obj-$(CONFIG_VIDEO_JZ_SENSOR) += jz_sensor.o
 
 obj-$(CONFIG_VIDEO_BT848) += bt8xx/
diff --git a/drivers/media/video/jz4750_cim.c b/drivers/media/video/jz4750_cim.c
deleted file mode 100644
index 7edf285b0ca..00000000000
--- a/drivers/media/video/jz4750_cim.c
+++ /dev/null
@@ -1,734 +0,0 @@
-/*
- * linux/drivers/char/jzchar/cim.c
- *
- * Camera Interface Module (CIM) driver for JzSOC
- * This driver is independent of the camera sensor
- *
- * Copyright (C) 2005  JunZheng semiconductor
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- * for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software Foundation,
- * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-//#include <linux/config.h>
-#include <linux/module.h>
-#include <linux/errno.h>
-#include <linux/sched.h>
-#include <linux/interrupt.h>
-#include <linux/major.h>
-#include <linux/string.h>
-#include <linux/fcntl.h>
-#include <linux/mm.h>
-#include <linux/slab.h>
-#include <linux/init.h>
-#include <linux/delay.h>
-#include <linux/fs.h>
-#include <linux/spinlock.h>
-
-#include <asm/irq.h>
-#include <asm/pgtable.h>
-#include <asm/uaccess.h>
-#include <asm/jzsoc.h>
-#include <asm/cacheflush.h>
-
-#include <linux/videodev.h>
-#include <media/v4l2-common.h>
-#include <linux/video_decoder.h>
-
-#include "jz4750_cim.h"
-
-#define CIM_NAME        "cim"
-
-MODULE_AUTHOR("Jianli Wei<jlwei@ingenic.cn>");
-MODULE_DESCRIPTION("JzSOC Camera Interface Module driver");
-MODULE_LICENSE("GPL");
-
-#if defined(CONFIG_SOC_JZ4750D)
-//#define USE_CIM_OFRCV 1 /* Test overflow recovery */
-#define USE_CIM_DMA_SYNC 1 //set da every time
-#endif
-
-//#define CIM_DEBUG
-#undef CIM_DEBUG
-#ifdef CIM_DEBUG
-#define dprintk(x...)	printk(x)
-#else
-#define dprintk(x...)
-#endif
-/*
- * Define the Max Image Size
- */
-#define MAX_IMAGE_WIDTH  2048
-#define MAX_IMAGE_HEIGHT 2048
-#define MAX_IMAGE_BPP    16
-#define MAX_FRAME_SIZE   (MAX_IMAGE_WIDTH * MAX_IMAGE_HEIGHT * MAX_IMAGE_BPP / 8)
-#define	CIM_RAM_ADDR		(CIM_BASE + 0x1000)
-
-typedef struct
-{
-	u32 width;
-	u32 height;
-	u32 bpp;
-} img_param_t;
-
-typedef struct
-{
-	u32 cfg;
-	u32 ctrl;
-	u32 mclk;
-	u32 size;
-	u32 offs;
-} cim_config_t;
-
-/*
- * IOCTL_XXX commands
- */
-#define IOCTL_SET_IMG_PARAM	0	// arg type: img_param_t *
-#define IOCTL_CIM_CONFIG	1	// arg type: cim_config_t *
-#define IOCTL_STOP_CIM		2       // arg type: void
-#define IOCTL_GET_IMG_PARAM	3	// arg type: img_param_t *
-#define IOCTL_GET_CIM_CONFIG	4	// arg type: cim_config_t *
-#define IOCTL_TEST_CIM_RAM	5	// no arg type *
-#define IOCTL_START_CIM		6       // arg type: void
-
-/*
- * CIM DMA descriptor
- */
-struct cim_desc {
-	u32 nextdesc;   /* Physical address of next desc */
-	u32 framebuf;   /* Physical address of frame buffer */
-	u32 frameid;    /* Frame ID */ 
-	u32 dmacmd;     /* DMA command */
-	u32 pagenum;
-};
-
-/*
- * CIM device structure
- */
-struct cim_device {
-	struct video_device *jz_cim;
-	unsigned char *framebuf;
-	unsigned int frame_size;
-	unsigned int page_order;
-	wait_queue_head_t wait_queue;
-	struct cim_desc *frame_desc __attribute__ ((aligned (16)));
-};
-
-/* global*/
-static struct cim_device *cim_dev;
-static int start_init = 1;
-static int irq_sleep;
-/*==========================================================================
- * CIM init routines
- *========================================================================*/
-
-static void cim_image_area(img_param_t *c) {
-	/*set the image data area start 0, 0, lines_per_frame and pixels_per_line*/
-	REG_CIM_SIZE = 0;
-	REG_CIM_OFFSET = 0;
-#if defined(CONFIG_SOC_JZ4750D)
-	if (REG_CIM_CTRL & CIM_CTRL_WIN_EN) {
-		REG_CIM_SIZE =  (c->height << CIM_SIZE_LPF_BIT) | (c->width << CIM_SIZE_PPL_BIT);
-//		REG_CIM_OFFSET = (0 << CIM_OFFSET_V_BIT) | (0 << CIM_OFFSET_H_BIT);
-//		REG_CIM_OFFSET = (100 << CIM_OFFSET_V_BIT) | (50 << CIM_OFFSET_H_BIT);
-		REG_CIM_OFFSET = (200 << CIM_OFFSET_V_BIT) | (300 << CIM_OFFSET_H_BIT);
-	}
-#endif
-}
-
-
-static void cim_config(cim_config_t *c)
-{
-	REG_CIM_CFG = c->cfg;
-	REG_CIM_CTRL = c->ctrl;
-	REG_CIM_SIZE = c->size;
-	REG_CIM_OFFSET = c->offs;
-
-	dprintk("REG_CIM_SIZE = 0x%08x\n", REG_CIM_SIZE);
-	dprintk("REG_CIM_OFFSET = 0x%08x\n", REG_CIM_OFFSET);
-	/* Set the master clock output */
-	/* If use pll clock, enable it */
-//	__cim_set_master_clk(__cpm_get_hclk(), c->mclk);
-
-	/* Enable sof, eof and stop interrupts*/
-
-//	__cim_enable_sof_intr();
-	__cim_enable_eof_intr();
-#if defined(USE_CIM_EEOFINT)
-	__cim_enable_eeof_intr();
-#endif
-//	__cim_enable_stop_intr();
-//	__cim_enable_trig_intr();
-//	__cim_enable_rxfifo_overflow_intr();
-//	__cim_enable_vdd_intr();
-//	printk("hclk=%d, mclk = %d\n", __cpm_get_hclk(),c->mclk);
-	dprintk("REG_CIM_CTRL = 0x%08x\n", REG_CIM_CTRL);
-}
-
-/*==========================================================================
- * CIM start/stop operations
- *========================================================================*/
-static int cim_start_dma(char *ubuf)
-{
-
-	struct cim_desc *jz_frame_desc;
-	int cim_frame_size = 0;
-	dprintk("==========start_init = %d\n", start_init);
-	__cim_disable();
-	__cim_set_da(virt_to_phys(cim_dev->frame_desc));
-	__cim_clear_state();	// clear state register
-	__cim_reset_rxfifo();	// resetting rxfifo
-	__cim_unreset_rxfifo();
-	__cim_enable_dma();	// enable dma
-	__cim_enable();
-	interruptible_sleep_on(&cim_dev->wait_queue);
-
-#if 1
-	dprintk("interruptible_sleep_on\n");
-	dprintk("REG_CIM_DA = 0x%08x\n", REG_CIM_DA);
-	dprintk("REG_CIM_FA = 0x%08x\n", REG_CIM_FA);
-	dprintk("REG_CIM_FID = 0x%08x\n", REG_CIM_FID);
-	dprintk("REG_CIM_CMD = 0x%08x\n", REG_CIM_CMD);
-	dprintk("REG_CIM_CFG = 0x%08x\n", REG_CIM_CFG);
-	dprintk("REG_CIM_STATE = 0x%08x\n", REG_CIM_STATE);
-	dprintk("REG_CIM_CTRL = 0x%08x\n", REG_CIM_CTRL);
-	dprintk("REG_CIM_SIZE = 0x%08x\n", REG_CIM_SIZE);
-	dprintk("REG_CIM_OFFSET = 0x%08x\n", REG_CIM_OFFSET);
-	dprintk("REG_CIM_CMD_3 = %x\n", REG_CIM_CMD);
-	dprintk("REG_CIM_FA = %x\n", REG_CIM_FA);
-#endif
-	/* copy frame data to user buffer */
-#if 0
-	jz_frame_desc = cim_dev->frame_desc;
-
-	while (jz_frame_desc != NULL)
-	{
-		dprintk("ubuf = %x, framebuf = %x,frame_size= %d\n", (u32)ubuf,(u32) jz_frame_desc->framebuf, jz_frame_desc->dmacmd & 0xffffff);
-		memcpy(ubuf, phys_to_virt(jz_frame_desc->framebuf), ((jz_frame_desc->dmacmd & CIM_CMD_LEN_MASK) * 4));
-		ubuf += (jz_frame_desc->dmacmd & CIM_CMD_LEN_MASK) * 4;
-		cim_frame_size += (jz_frame_desc->dmacmd & CIM_CMD_LEN_MASK) * 4;
-		jz_frame_desc = (struct cim_desc *)phys_to_virt(jz_frame_desc->nextdesc);
-	}
-#endif
-	dprintk("---------**********-----\n");
-	return cim_dev->frame_size;
-}
-static void cim_stop(void)
-{
-	__cim_disable();
-	__cim_clear_state();
-}
-
-/*==========================================================================
- * Framebuffer allocation and destroy
- *========================================================================*/
-static void cim_fb_destroy(void)
-{
-	int pages;
-	struct cim_desc *jz_frame_desc, *p_desc;
-	__cim_disable_dma();
-	__cim_disable();
-
-	dprintk("cim_dev->frame_desc = %x\n", (u32)cim_dev->frame_desc);
-	if (cim_dev->frame_desc == NULL) {
-		printk("Original memory is NULL\n");
-		return;
-	}
-	jz_frame_desc = cim_dev->frame_desc;
-//	while (jz_frame_desc != NULL) {
-//	while (jz_frame_desc != cim_dev->frame_desc) {
-		dprintk("framebuf = %x,thisdesc = %x,frame_size= %d\n", (u32) jz_frame_desc->framebuf, (unsigned int)jz_frame_desc, (jz_frame_desc->dmacmd & 0xffffff) * 4);
-		p_desc = (struct cim_desc *)phys_to_virt(jz_frame_desc->nextdesc);
-		pages = jz_frame_desc->pagenum;
-		dprintk("page_order = %d\n", pages);
-		free_pages((unsigned long)phys_to_virt(jz_frame_desc->framebuf), pages);
-		kfree(jz_frame_desc);
-		jz_frame_desc = p_desc;
-//	}
-	cim_dev->frame_desc = NULL;
-	start_init = 1;
-}
-
-static struct cim_desc *get_desc_list(int page_order)
-{
-	int num, page_nums = 0;
-	unsigned char *p_buf;
-	struct cim_desc *desc_list_head __attribute__ ((aligned (16)));
-	struct cim_desc *desc_list_tail __attribute__ ((aligned (16)));
-	struct cim_desc *p_desc;
-//	num = page_order - 1;
-	num = page_order;
-	desc_list_head = desc_list_tail = NULL;
-
-	while(page_nums < (1 << page_order)) {
-		p_desc = (struct cim_desc *)kmalloc(sizeof(struct cim_desc), GFP_KERNEL);
-		if (NULL == p_desc)
-			return NULL;
-		//return -ENOMEM;
-	cim_realloc_pages:
-		p_buf = (unsigned char *)__get_free_pages(GFP_KERNEL, num);
-		if ( !(p_buf) && num != 0) {
-			num --;
-			goto cim_realloc_pages;
-		}
-		else if ( !(p_buf) && num == 0)	{
-			printk("No memory can be alloc!\n");
-			//return -ENOMEM;
-			return NULL;
-		}
-		else {
-			if (desc_list_head == NULL) {
-				dprintk("Page_list_head\n");
-				desc_list_head = p_desc;
-			}
-			
-			else
-				desc_list_tail->nextdesc = virt_to_phys(p_desc);
-
-			desc_list_tail = p_desc;
-			desc_list_tail->framebuf = virt_to_phys(p_buf);
-			dprintk("framebuf addr is 0x%08x\n", (u32)desc_list_tail->framebuf);
-			dprintk("frame_desc addr is 0x%08x\n",(u32)virt_to_phys(desc_list_tail));
-
-			desc_list_tail->frameid = 0x52052018;
-			desc_list_tail->pagenum = num;
-			if ((page_nums + (1<< num)) < (1 << page_order)) {
-				desc_list_tail->dmacmd = ((1 << num) * 4096) >> 2 ;
-			}
-			else
-				desc_list_tail->dmacmd = 
-					(cim_dev->frame_size - page_nums * 4096) >> 2 ;
-			dprintk("the desc_list_tail->dmacmd is 0x%08x\n", desc_list_tail->dmacmd);
-			page_nums += (1 << num);
-			dprintk("the pages_num is %d\n", page_nums);
-			dma_cache_wback((unsigned long)(desc_list_tail), 16);
-		}
-	}
-
-//	desc_list_tail->nextdesc = virt_to_phys(NULL);
-	desc_list_tail->nextdesc = virt_to_phys(desc_list_head);
-	desc_list_tail->dmacmd |= CIM_CMD_EOFINT;
-#if defined(CONFIG_SOC_JZ4750D)
-#if defined(USE_CIM_OFRCV)
-	desc_list_tail->dmacmd |= (CIM_CMD_EOFINT | CIM_CMD_OFRCV);
-#endif
-#if defined(USE_CIM_DMA_SYNC) /* wake ervry time */
-	desc_list_tail->nextdesc = virt_to_phys(NULL);
-	desc_list_tail->dmacmd |= (CIM_CMD_STOP | CIM_CMD_EOFINT | CIM_CMD_OFRCV);
-#endif
-#if defined(USE_CIM_EEOFINT)
-//	desc_list_tail->dmacmd |= CIM_CMD_EEOFINT;
-	desc_list_tail->dmacmd |= (CIM_CMD_STOP | CIM_CMD_EOFINT | CIM_CMD_EEOFINT);
-#endif
-#endif
-	/* stop after capturing a frame */
-//	desc_list_tail->dmacmd |= (CIM_CMD_STOP | CIM_CMD_EOFINT | CIM_CMD_SOFINT);
-
-
-
-
-	dma_cache_wback((unsigned long)(desc_list_tail), 16);
-	dprintk("the desc_list_tail->dmacmd is 0x%08x\n", desc_list_tail->dmacmd);
- 
-	return desc_list_head;
-}
-
-static int cim_fb_alloc(int img_width, int img_height, int img_bpp)
-{
-	if ((REG_CIM_CFG & (CIM_CFG_DF_MASK | CIM_CFG_BYPASS_MASK)) == 0)
-		cim_dev->frame_size = img_width * (img_height-1) * (img_bpp/8);
-	else
-		cim_dev->frame_size = img_width * img_height * (img_bpp/8);
-
-	cim_dev->page_order = get_order(cim_dev->frame_size);
-	dprintk("cim_dev->page_order=%d\n", cim_dev->page_order);
-	/* frame buffer ?? need large mem ??*/
-	cim_dev->frame_desc = get_desc_list(cim_dev->page_order);
-	if (cim_dev->frame_desc == NULL)
-		return -ENOMEM;
-	dma_cache_wback((unsigned long)(cim_dev->frame_desc), 16);
-	return 0;
-}
-
-/*==========================================================================
- * File operations
- *========================================================================*/
-
-static int cim_open(struct inode *inode, struct file *filp);
-static int cim_release(struct inode *inode, struct file *filp);
-static ssize_t cim_read(struct file *filp, char *buf, size_t size, loff_t *l);
-static ssize_t cim_write(struct file *filp, const char *buf, size_t size, loff_t *l);
-static int cim_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg);
-static int cim_mmap(struct file *file, struct vm_area_struct *vma);
-
-static struct file_operations cim_fops = 
-{
-	open:		cim_open,
-	release:	cim_release,
-	read:		cim_read,
-	write:		cim_write,
-	ioctl:		cim_ioctl,
-	compat_ioctl:	v4l_compat_ioctl32,
-	mmap:		cim_mmap
-};
-
-static struct video_device jz_v4l_device = {
-	.name		= "jz cim",
-	//.type		= VID_TYPE_CAPTURE | VID_TYPE_SUBCAPTURE |
-	//	VID_TYPE_CLIPPING | VID_TYPE_SCALES, VID_TYPE_OVERLAY
-	.fops		= &cim_fops,
-	.minor		= -1,
-	.owner		= THIS_MODULE,
-	.release 	= video_device_release,
-};
-
-static int cim_open(struct inode *inode, struct file *filp)
-{
-	
- 	try_module_get(THIS_MODULE);
-	return 0;
-}
-
-static int cim_release(struct inode *inode, struct file *filp)
-{
-	dprintk("%s, %s, %d\n", __FILE__, __FUNCTION__, __LINE__);
-	cim_fb_destroy();
-	cim_stop();
-
- 	module_put(THIS_MODULE);
-	return 0;
-}
-
-static ssize_t cim_read(struct file *filp, char *buf, size_t size, loff_t *l)
-{
-	printk("============cim error: write is not implemented\n");
-	if (size < cim_dev->frame_size)
-		return -EINVAL;
-	return cim_start_dma(buf);
-}
-
-static ssize_t cim_write(struct file *filp, const char *buf, size_t size, loff_t *l)
-{
-	printk("cim error: write is not implemented\n");
-	return -1;
-}
-
-static int cim_ioctl(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg)
-{
-	void __user *argp = (void __user *)arg;
-	switch (cmd) {
-	case IOCTL_GET_IMG_PARAM:
-	{
-		unsigned int i;
-		i = cim_dev->frame_desc->framebuf;
-//		printk("cim_dev->frame_desc->framebuf = 0x%08x\n", cim_dev->frame_desc->framebuf);
-		dprintk("&&cim_dev->frame_desc->framebuf = 0x%08x\n", i);
-
-		return copy_to_user(argp, &i, sizeof(unsigned int)) ? -EFAULT : 0;
-	}
-	case IOCTL_STOP_CIM:
-	{
-		__cim_disable_dma();	// enable dma
-		__cim_disable();
-
-//		cim_fb_destroy();
-		return 0;
-	}
-	case IOCTL_START_CIM:
-	{
-		__cim_set_da(virt_to_phys(cim_dev->frame_desc));
-		__cim_clear_state();	// clear state register
-		__cim_reset_rxfifo();	// resetting rxfifo
-		__cim_unreset_rxfifo();
-		__cim_enable_dma();	// enable dma
-		__cim_enable();
-		return 0;
-	}
-	case IOCTL_SET_IMG_PARAM:
-	{
-		img_param_t i;
-		int img_width, img_height, img_bpp;
-		if (copy_from_user((void *)&i, (void *)arg, sizeof(img_param_t)))
-			return -EFAULT;
-		img_width = i.width;
-		img_height = i.height;
-		img_bpp = i.bpp;
-		printk("ALLOC =========\n");
-		if ((img_width * img_height * img_bpp/8) > MAX_FRAME_SIZE){
-			printk("ERROR! Image is too large!\n");
-			return -EINVAL;
-		}
- 		/* allocate frame buffers */
-		if (cim_dev->frame_desc == NULL){
-			if (cim_fb_alloc(img_width, img_height, img_bpp) < 0){
-				printk("ERROR! Init & alloc cim fail!\n");
-				return -ENOMEM;
-			}
-		}
-		else
-			if ((img_width * img_height * img_bpp/8) > cim_dev->frame_size){
-				/* realloc the buffer */
-	dprintk("%s, %s, %d\n", __FILE__, __FUNCTION__, __LINE__);
-				cim_fb_destroy();
-				if (cim_fb_alloc(img_width, img_height, img_bpp) < 0){
-					printk("ERRROR! Init & alloc cim fail!\n");
-					return -ENOMEM;
-				}
-			}
-		break;
-	}
-	case IOCTL_CIM_CONFIG:
-	{
-		cim_config_t c;
-
-		if (copy_from_user((void *)&c, (void *)arg, sizeof(cim_config_t)))
-			return -EFAULT;
-		cim_config(&c);
-
-		break;
-	}
-	case IOCTL_TEST_CIM_RAM:
-	{
-		
-		int i;
-		volatile unsigned int *ptr;
-		ptr = (volatile unsigned int *)(CIM_RAM_ADDR);
-		dprintk("RAM test!\n");
-		dprintk("CIM_RAM_ADDR = 0x%08x\n", CIM_RAM_ADDR);
-		for (i = 0; i < 1024; ptr++, i++)
-			*ptr = i;
-		ptr = (volatile unsigned int *)(CIM_RAM_ADDR);
-		dma_cache_wback((unsigned long)CIM_RAM_ADDR,0xffc);
-
-		for (i = 0; i < 1024; i++) {
-			if (i != *ptr)
-				dprintk("*ptr!=i, *ptr=%d, i=%d\n", *ptr, i);
-			if (i%32 == 0) {
-				if (i%128 == 0)
-					dprintk("\n");
-				dprintk("*ptr=%04d, i=%04d | ", *ptr, i);
-			}
-			ptr++;
-		}
-		dprintk("\n");
-		break;
-	}
-	default:
-		printk("Not supported command: 0x%x\n", cmd);
-		return -EINVAL;
-		break;
-	}
-	return 0;
-}
-
-/* Use mmap /dev/fb can only get a non-cacheable Virtual Address. */
-static int cim_mmap(struct file *file, struct vm_area_struct *vma)
-{
-	unsigned long start;
-	unsigned long off;
-	u32 len;
-
-	dprintk("%s, %s, %d\n", __FILE__, __FUNCTION__, __LINE__);
-	off = vma->vm_pgoff << PAGE_SHIFT;
-
-	/* frame buffer memory */
-	start = cim_dev->frame_desc->framebuf;
-	len = PAGE_ALIGN((start & ~PAGE_MASK) + (cim_dev->frame_desc->dmacmd & CIM_CMD_LEN_MASK)*4);
-	start &= PAGE_MASK;
-	printk("vma->vm_end = 0x%08lx,\nvma->vm_start = 0x%08lx,\noff = 0x%08lx,\n len = 0x%08x\n\n", vma->vm_end, vma->vm_start, off, len);
-	if ((vma->vm_end - vma->vm_start + off) > len) {
-		printk("Error: vma is larger than memory length\n");
-		return -EINVAL;
-	}
-	off += start;
-
-	vma->vm_pgoff = off >> PAGE_SHIFT;
-	vma->vm_flags |= VM_IO;
-	vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);	/* Uncacheable */
-
-#if  defined(CONFIG_MIPS32)
- 	pgprot_val(vma->vm_page_prot) &= ~_CACHE_MASK;
- 	pgprot_val(vma->vm_page_prot) |= _CACHE_UNCACHED;		/* Uncacheable */
-#endif
-
-	if (io_remap_pfn_range(vma, vma->vm_start, off >> PAGE_SHIFT,
-			       vma->vm_end - vma->vm_start,
-			       vma->vm_page_prot)) {
-		return -EAGAIN;
-	}
-	return 0;
-}
-/*==========================================================================
- * Interrupt handler
- *========================================================================*/
-
-static irqreturn_t cim_irq_handler(int irq, void *dev_id)
-{
-	u32 state = REG_CIM_STATE;
-	dprintk("REG_CIM_STATE = %x\n", REG_CIM_STATE);
-	dprintk("IRQ:REG_CIM_CTRL = %x\n", REG_CIM_CTRL);
-
-#if 0 //sof
-	/* recommed don't open it */
-	if ((REG_CIM_CTRL & CIM_CTRL_DMA_SOFM) && (state & CIM_STATE_DMA_SOF)) {
-		dprintk("SOF interrupt!\n");
-		REG_CIM_STATE &= ~CIM_STATE_DMA_SOF;
-	}
-#endif
-#if 0 //eeof
-	if ((REG_CIM_CTRL & CIM_CTRL_DMA_EEOFM) && (state & CIM_STATE_DMA_EEOF)) {
-		dprintk("EEOF interrupt!\n");
-		__cim_disable_dma();
-		__cim_disable();
-		wake_up_interruptible(&cim_dev->wait_queue);
-		REG_CIM_STATE &= ~CIM_STATE_DMA_EEOF;
-	}
-#endif
-
-#if 1 //eof
-	if ((REG_CIM_CTRL & CIM_CTRL_DMA_EOFM) && (state & CIM_STATE_DMA_EOF)) {
-//	if (state & CIM_STATE_DMA_EOF) {
-		dprintk("EOF interrupt!\n");
-
-#if defined(USE_CIM_DMA_SYNC) /* wake ervry time */
-//		__cim_disable_dma();
-//		__cim_disable();
-		wake_up_interruptible(&cim_dev->wait_queue);
-#else
-//		if(irq_sleep == 1)
-		wake_up_interruptible(&cim_dev->wait_queue);
-#endif
-		REG_CIM_STATE &= ~CIM_STATE_DMA_EOF;
-		return IRQ_HANDLED;
-	}
-#endif
-#if 0 //overflow
-	if (state & CIM_STATE_RXF_OF) {
-		printk("OverFlow interrupt!\n");
-		REG_CIM_STATE &= ~CIM_STATE_RXF_OF;
-//		dprintk("REG_CIM_STATE = %x\n", REG_CIM_STATE);
-		return IRQ_HANDLED;
-	}
-#endif
-#if 1 // stop
-	if ((REG_CIM_CTRL & CIM_CTRL_DMA_STOPM) && (state & CIM_STATE_DMA_STOP)) {
-		// Got a frame, wake up wait routine
-//#if defined(USE_CIM_DMA_SYNC) /* wake ervry time */
-		__cim_disable_dma();
-//		__cim_disable();
-
-		dprintk("Stop interrupt!\n");
-//		wake_up_interruptible(&cim_dev->wait_queue);
-		REG_CIM_STATE &= ~CIM_STATE_DMA_STOP;
-	}
-#endif
-
-#if 0 //trig
-	if ((REG_CIM_CTRL & CIM_CTRL_RXF_TRIGM) && (state & CIM_STATE_RXF_TRIG)) {
-		REG_CIM_STATE &= ~CIM_STATE_RXF_TRIG;
-		dprintk("Trig interrupt!\n");
-	}
-#endif
-
-#if 0 //vdd
-	/* only happen disable cim during DMA transfer*/
-	if ((REG_CIM_CTRL & CIM_CTRL_VDDM) && (state & CIM_STATE_VDD)) {
-		dprintk(">>CIM Disable Done Interrupt!\n");
-		REG_CIM_STATE &= ~CIM_STATE_VDD;
-	}
-#endif
-	/* clear status flags*/
-	dprintk("before clear REG_CIM_STATE = %x\n", REG_CIM_STATE);
-//	REG_CIM_STATE = 0;
-
- 	return IRQ_HANDLED;
-}
-
-/*Camera gpio init, different operationg according sensor*/
-static void camera_gpio_init(void) {
-
-	__gpio_as_cim();
-	__gpio_as_i2c();
-	__sensor_gpio_init();
-}
-
-static int v4l_device_init(void)
-{
-	camera_gpio_init();
-	cim_dev = kzalloc(sizeof(struct cim_device), GFP_KERNEL);
-	if (!cim_dev) return -ENOMEM;
-	cim_dev->jz_cim = video_device_alloc();
-	if (!cim_dev->jz_cim) {
-		return -ENOMEM;
-	}
-	memcpy(cim_dev->jz_cim, &jz_v4l_device, sizeof(struct video_device));
-	cim_dev->frame_desc = NULL;
-	cim_dev->frame_size = 0;
-	cim_dev->page_order = 0;
-	return 0;
-}
-/*==========================================================================
- * Module init and exit
- *========================================================================*/
-
-static int __init jz4750_cim_init(void)
-{
-	struct cim_device *dev;
-	int ret;
-	/* allocate device */
-	ret = v4l_device_init();
-	if (ret)
-		return ret;
-	/* record device */
-	dev = cim_dev;
-	init_waitqueue_head(&dev->wait_queue);
-
-	ret = video_register_device(dev->jz_cim, VFL_TYPE_GRABBER, -1);
-	if (ret < 0) {
-		printk(KERN_ERR "CIM Video4Linux-device "
-		       "registration failed\n");
-		return -EINVAL;
-	}
-
-	if (ret < 0) {
-	dprintk("%s, %s, %d\n", __FILE__, __FUNCTION__, __LINE__);
-		cim_fb_destroy();
-		kfree(dev);
-		return ret;
-	}
-
-	if ((ret = request_irq(IRQ_CIM, cim_irq_handler, IRQF_DISABLED, 
-			       CIM_NAME, dev))) {
-		printk(KERN_ERR "request_irq return error, ret=%d\n", ret);
-	dprintk("%s, %s, %d\n", __FILE__, __FUNCTION__, __LINE__);
-		cim_fb_destroy();
-		kfree(dev);
-		printk(KERN_ERR "CIM could not get IRQ\n");
-		return ret;
-	}
-
-	printk("JzSOC Camera Interface Module (CIM) driver registered\n");
-
-	return 0;
-}
-
-static void __exit jz4750_cim_exit(void)
-{
-	free_irq(IRQ_CIM, cim_dev);
-	kfree(cim_dev);
-	video_unregister_device(cim_dev->jz_cim);
-}
-
-module_init(jz4750_cim_init);
-module_exit(jz4750_cim_exit);
diff --git a/drivers/media/video/jz4750_cim.h b/drivers/media/video/jz4750_cim.h
deleted file mode 100644
index 7e73c7cc291..00000000000
--- a/drivers/media/video/jz4750_cim.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * linux/drivers/media/video/jz4750_cim.h -- Ingenic Jz4750 On-Chip CIM driver
- *
- * Copyright (C) 2005-2008, Ingenic Semiconductor Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef __JZ4750_CIM_H__
-#define __JZ4750_CIM_H__
-
-/* gpio init */
-#if defined(CONFIG_JZ4750_APUS) || defined(CONFIG_JZ4750D_FUWA1) /* board pavo */
-#define GPIO_CAMERA_RST 	(32*4+8) /* CIM_MCLK as reset */
-#else
-#error "driver/video/Jzlcd.h, please define SPI pins on your board."
-#endif
-
-#define CONFIG_OV9650    1
-
-#if defined(CONFIG_OV9650) || defined(CONFIG_OV2640)
-#if defined(CONFIG_JZ4750_APUS) /* board pavo */
-#define __sensor_gpio_init()	\
-do {\
-	__gpio_as_output(GPIO_CAMERA_RST);	\
-	__gpio_set_pin(GPIO_CAMERA_RST); \
-	mdelay(50); \
-	__gpio_clear_pin(GPIO_CAMERA_RST);\
-} while(0)
-
-#elif defined(CONFIG_JZ4750D_FUWA1) /* board pavo */
-#define __sensor_gpio_init()	\
-do {\
-	__gpio_as_output(GPIO_CAMERA_RST);	\
-	__gpio_set_pin(GPIO_CAMERA_RST); \
-	mdelay(50); \
-	__gpio_clear_pin(GPIO_CAMERA_RST);\
-} while(0)
-#endif
-#endif
-
-#ifndef __sensor_gpio_init
-#define __sensor_gpio_init()
-#endif
-#endif /* __JZ4750_CIM_H__ */
-
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 9a3fec42c9d..7b2782a7426 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -18,6 +18,9 @@ config JZ_I2C_SIMULATE
 
 config JZ_CIM
 	bool "JZ CIM for Camera driver"
+config JZ_OPT
+	bool "JZ OPT driver for JZ4760B"
+	depends on  SOC_JZ4760B
 
 config OV3640
 	bool "OmniVision OV3640 sensor support (3.1 MegaPixel)"
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index e396e909316..08ada2fd53b 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -24,4 +24,5 @@ obj-y				+= eeprom/
 obj-y				+= cb710/
 
 obj-$(CONFIG_JZ_CIM)            += jz_cim/
+obj-$(CONFIG_JZ_OPT)		+= opt_test.o
 obj-$(CONFIG_JZ_I2C_SIMULATE)   += i2c_simulate.o
diff --git a/drivers/misc/jz_cim/Makefile b/drivers/misc/jz_cim/Makefile
index aaf359091fb..74c35cb5b1f 100644
--- a/drivers/misc/jz_cim/Makefile
+++ b/drivers/misc/jz_cim/Makefile
@@ -10,7 +10,9 @@ obj-$(CONFIG_JZ4750_AQUILA)	+= jz_cim_board_aquila.o
 obj-$(CONFIG_JZ4760_ALTAIR)	+= jz_cim_board_altair.o
 obj-$(CONFIG_JZ4760_PT701)	+= jz_cim_board_pt701.o
 obj-$(CONFIG_JZ4760_LEPUS)	+= jz_cim_board_lepus.o
+obj-$(CONFIG_JZ4760B_LEPUS)	+= jz_cim_board_lepus.o
 obj-$(CONFIG_JZ4760_F4760)	+= jz_cim_board_f4760.o
+obj-$(CONFIG_JZ4810_F4810)	+= jz_cim_board_f4810.o
 
 obj-$(CONFIG_OV7690)		+= camera_source/ov7690/
 obj-$(CONFIG_OV3640)		+= camera_source/ov3640/
diff --git a/drivers/misc/jz_cim/camera_source/isp/tran_data b/drivers/misc/jz_cim/camera_source/isp/tran_data
deleted file mode 100644
index da5b31121df..00000000000
--- a/drivers/misc/jz_cim/camera_source/isp/tran_data
+++ /dev/null
diff --git a/drivers/misc/jz_cim/camera_source/ov3640/ov3640_camera.c b/drivers/misc/jz_cim/camera_source/ov3640/ov3640_camera.c
index 6fb474f6037..480e716c880 100644
--- a/drivers/misc/jz_cim/camera_source/ov3640/ov3640_camera.c
+++ b/drivers/misc/jz_cim/camera_source/ov3640/ov3640_camera.c
@@ -28,9 +28,9 @@ struct camera_sensor_desc ov3640_sensor_desc;
 #define GPIO_CAMERA_RST         (32*4+8) /* MCLK as reset */
 #elif defined(CONFIG_JZ4760_ALTAIR)
 #define GPIO_CAMERA_RST         (32*4+13) /*GPE13*/
-#elif defined(CONFIG_JZ4760_LEPUS)
+#elif defined(CONFIG_JZ4760_LEPUS) || defined(CONFIG_JZ4760B_LEPUS)
 #define GPIO_CAMERA_RST         (32*1 + 26) /* GPB26 */
-#elif defined(CONFIG_JZ4760_F4760) /* JZ4760 FPGA */
+#elif defined(CONFIG_JZ4760_F4760) || defined(CONFIG_JZ4810_F4810)/* JZ4760 FPGA */
 #define GPIO_CAMERA_RST         (32*1+9) /* CIM_MCLK as reset */
 #else
 #error "ov3640/ov3640_camera.c , please define camera for your board."
@@ -45,7 +45,7 @@ void ov3640_power_down(void)
 #elif defined(CONFIG_JZ4760_ALTAIR)
 	__gpio_as_output(0*32+27);                                    /* GPA27 */
 	__gpio_set_pin(0*32+27);
-#elif defined(CONFIG_JZ4760_LEPUS)
+#elif defined(CONFIG_JZ4760_LEPUS) || defined(CONFIG_JZ4760B_LEPUS)
 	__gpio_as_output(32 * 1 + 27); /* GPB27 */
 	__gpio_set_pin(32 * 1 + 27);
 #endif
@@ -61,7 +61,7 @@ void ov3640_power_up(void)
 #elif defined(CONFIG_JZ4760_ALTAIR)
 	__gpio_as_output(0*32+27);
 	__gpio_clear_pin(0*32+27);
-#elif defined(CONFIG_JZ4760_LEPUS)
+#elif defined(CONFIG_JZ4760_LEPUS) || defined(CONFIG_JZ4760B_LEPUS)
 	__gpio_as_output(32 * 1 + 27); /* GPB27 */
 	__gpio_clear_pin(32 * 1 + 27);
 #endif
@@ -90,12 +90,18 @@ void ov3640_reset(void)
 	__gpio_set_pin(2*32+31);
 #else
 	dprintk("=======%s:%d\n", __FUNCTION__, __LINE__);
-	__gpio_as_output(GPIO_CAMERA_RST);
+#ifdef CONFIG_JZ4810_F4810
+	__gpio_as_output0(GPIO_CAMERA_RST);
+	mdelay(50);
+	__gpio_as_output1(GPIO_CAMERA_RST);
+	mdelay(50);
+#else
 	__gpio_clear_pin(GPIO_CAMERA_RST);
 	mdelay(50);
 	__gpio_set_pin(GPIO_CAMERA_RST);
 	mdelay(50);
 #endif
+#endif
 }
 
 int ov3640_set_balance(balance_flag_t balance_flag,int arg)
@@ -517,10 +523,12 @@ int ov3640_set_resolution(int width,int height,int bpp,pixel_format_flag_t fmt,c
 
 static int ov3640_probe(struct i2c_client *client, const struct i2c_device_id *id)
 {
-	printk("=====>enter ov3640 probe\n");
 	ov3640_sensor_desc.client = client;
+#ifndef CONFIG_JZ4810_F4810
 	sensor_set_i2c_speed(client,400000);// set ov3640 i2c speed : 400khz
-	//sensor_set_i2c_speed(client,5000);// F4760: set ov3640 i2c speed : 5khz
+#else
+	sensor_set_i2c_speed(client,5000);// F4760: set ov3640 i2c speed : 5khz
+#endif
 	camera_sensor_register(&ov3640_sensor_desc);
 
 	return 0;
@@ -538,7 +546,7 @@ struct camera_sensor_ops ov3640_sensor_ops = {
 
 
 struct resolution_info ov3640_resolution_table[] = {
-	//	{2048,1536,16,PIXEL_FORMAT_YUV422I},
+	//{2048,1536,16,PIXEL_FORMAT_YUV422I},
 	{1600,1200,16,PIXEL_FORMAT_YUV422I},
 	{1280,1024,16,PIXEL_FORMAT_YUV422I},
 	{1024,768,16,PIXEL_FORMAT_YUV422I},
@@ -590,7 +598,7 @@ struct camera_sensor_desc ov3640_sensor_desc = {
 			|CIM_CFG_PACK_2			/* pack mode : 3 2 1 4*/
 			|CIM_CFG_BYPASS			/* Bypass Mode */
 			//|CIM_CFG_VSP             	/* VSYNC Polarity:1-falling edge active */
-			|CIM_CFG_PCP             	/* PCLK working edge:1-falling */
+			//|CIM_CFG_PCP             	/* PCLK working edge:1-falling */
 			|CIM_CFG_DSM_GCM,		/* Gated Clock Mode */
 	},
 
@@ -626,7 +634,6 @@ static struct i2c_driver ov3640_driver = {
 
 static int __init ov3640_register(void)
 {
-	printk("=====>enter ov3640 register......\n");
 	return i2c_add_driver(&ov3640_driver);
 }
 
diff --git a/drivers/misc/jz_cim/camera_source/ov3640/ov3640_set.c b/drivers/misc/jz_cim/camera_source/ov3640/ov3640_set.c
index 3a490921db7..191757574e8 100644
--- a/drivers/misc/jz_cim/camera_source/ov3640/ov3640_set.c
+++ b/drivers/misc/jz_cim/camera_source/ov3640/ov3640_set.c
@@ -214,7 +214,11 @@ void init_set(struct i2c_client *client)
 	sensor_write_reg16(client,0x304c,0x85);

 	sensor_write_reg16(client,0x300e,0x39);

 	sensor_write_reg16(client,0x300f,0xa1);//12.5fps -> 25fps

-	sensor_write_reg16(client,0x3011,0x00); /* default 0x00, change ov3640 PCLK DIV here --- by Lutts*/

+#ifdef CONFIG_JZ4810_F4810

+	sensor_write_reg16(client,0x3011,0x5); /* default 0x00, change ov3640 PCLK DIV here --- by Lutts*/

+#else

+	sensor_write_reg16(client,0x3011,0x0); /* default 0x00, change ov3640 PCLK DIV here --- by Lutts*/

+#endif

 	sensor_write_reg16(client,0x3010,0x81);

 	sensor_write_reg16(client,0x302e,0xA0);

 	sensor_write_reg16(client,0x302d,0x00);

@@ -259,8 +263,11 @@ void capture_reg_set(struct i2c_client *client)
 	sensor_write_reg16(client,0x3010,0x20);

 	sensor_write_reg16(client,0x304c,0x81);

 	sensor_write_reg16(client,0x3366,0x10);

-	sensor_write_reg16(client,0x3011,0x00); /* default 0x00, change ov3640 PCLK DIV here --- by lutts */

-

+#ifdef CONFIG_JZ4810_F4810

+	sensor_write_reg16(client,0x3011,0x5); /* default 0x00, change ov3640 PCLK DIV here --- by lutts */

+#else

+	sensor_write_reg16(client,0x3011,0x0); /* default 0x00, change ov3640 PCLK DIV here --- by lutts */

+#endif

 	sensor_write_reg16(client,0x3f00,0x02);//disable overlay

 }

 

@@ -306,7 +313,11 @@ void preview_set(struct i2c_client *client)
 	sensor_write_reg16(client,0x300e,0x39);

 	sensor_write_reg16(client,0x300f,0xa1);//12.5fps -> 25fps

 	sensor_write_reg16(client,0x3010,0x81);

-	sensor_write_reg16(client,0x3011,0x00); /* default: 0x00, change ov3640 PCLK here --- by Lutts */

+#ifdef CONFIG_JZ4810_F4810

+	sensor_write_reg16(client,0x3011,0x5); /* default: 0x00, change ov3640 PCLK here --- by Lutts */

+#else

+	sensor_write_reg16(client,0x3011,0x0); /* default: 0x00, change ov3640 PCLK here --- by Lutts */

+#endif

 	sensor_write_reg16(client,0x302e,0xa0);

 	sensor_write_reg16(client,0x302d,0x00);

 	sensor_write_reg16(client,0x3071,0x82);

@@ -347,7 +358,7 @@ void preview_set(struct i2c_client *client)
 

 	/* slcao */

 	/* HSYNC mode */

-#if 0

+#ifdef CONFIG_JZ4810_F4810

 	value = sensor_read_reg16(client, 0x3646);

 	value |= 0x40;

 

diff --git a/drivers/misc/jz_cim/jz_cim_core.c b/drivers/misc/jz_cim/jz_cim_core.c
index 3f7ed7cd8cf..54a2cfd061d 100644
--- a/drivers/misc/jz_cim/jz_cim_core.c
+++ b/drivers/misc/jz_cim/jz_cim_core.c
@@ -46,7 +46,12 @@ MODULE_AUTHOR("Lutts Cao<slcao@ingenic.cn>");
 MODULE_DESCRIPTION("Ingenic Camera interface driver");
 MODULE_LICENSE("GPL");
 
-//#define CONFIG_TEST_JZ4760E y
+#define CIM_MINOR             234
+
+//#define CONFIG_SOC_JZ4760B y
+#ifdef CONFIG_JZ4810_F4810
+#define CONFIG_SOC_JZ4760B y
+#endif
 
 //#define CIM_INTR_SOF_EN
 #define CIM_INTR_EOF_EN
@@ -68,7 +73,7 @@ MODULE_LICENSE("GPL");
 #undef CIM_DEBUG
 
 #ifdef CIM_DEBUG
-#if defined(CONFIG_TEST_JZ4760E)
+#if defined(CONFIG_SOC_JZ4760B)
 #define dprintk(x...)	do{printk("CIM(test jz4760e)---\t");printk(x);}while(0)
 #else
 #define dprintk(x...)	do{printk("CIM---\t");printk(x);}while(0)
@@ -96,7 +101,7 @@ enum {TRUE=1,FALSE=0};
 
 struct cim_desc {
 	u32 nextdesc;   // Physical address of next desc
-#if defined(CONFIG_TEST_JZ4760E)
+#if defined(CONFIG_SOC_JZ4760B)
 	u32 frameid;    // Frame ID
 	u32 framebuf;   // Physical address of frame buffer, when SEP=1, it's y framebuffer
 #else
@@ -271,7 +276,7 @@ static void cim_print_regs(void)
 {
 	printk("REG_CIM_CFG \t= \t0x%08x\n", REG_CIM_CFG);
 	printk("REG_CIM_CTRL \t= \t0x%08x\n", REG_CIM_CTRL);
-#ifdef CONFIG_TEST_JZ4760E
+#ifdef CONFIG_SOC_JZ4760B
 	printk("REG_CIM_CTRL2 \t= \t0x%08x\n", REG_CIM_CTRL2);
 #endif
 	printk("REG_CIM_STATE \t= \t0x%08x\n", REG_CIM_STATE);
@@ -282,7 +287,7 @@ static void cim_print_regs(void)
 	printk("REG_CIM_CMD \t= \t0x%08x\n", REG_CIM_CMD);
 	printk("REG_CIM_SIZE \t= \t0x%08x\n", REG_CIM_SIZE);
 	printk("REG_CIM_OFFSET \t= \t0x%08x\n", REG_CIM_OFFSET);
-#ifdef CONFIG_TEST_JZ4760E
+#ifdef CONFIG_SOC_JZ4760B
 	printk("REG_CIM_YFA \t= \t%#08x\n", REG_CIM_YFA);
 	printk("REG_CIM_YCMD \t= \t%#08x\n", REG_CIM_YCMD);
 	printk("REG_CIM_CBFA \t= \t%#08x\n", REG_CIM_CBFA);
@@ -528,7 +533,7 @@ static void cim_config(cim_config_t *c)
 	REG_CIM_SIZE = c->size;
 	REG_CIM_OFFSET = c->offs;
 
-#if defined(CONFIG_TEST_JZ4760E)
+#if defined(CONFIG_SOC_JZ4760B)
 		__cim_input_data_format_select_YUV422();
 		//__cim_input_data_format_select_YUV444();
 		__cim_set_input_data_stream_order(0); /* YCbCr or Y0CbY1Cr */
@@ -538,9 +543,9 @@ static void cim_config(cim_config_t *c)
 
 		//__cim_set_data_packing_mode(0); /* 0x11 22 33 44 or 0x Y0 Cb Y1 Cr */
 		//__cim_set_data_packing_mode(1); /* 0x 22 33 44 11 or 0x Cb Y1 Cr Y0 */
-		//__cim_set_data_packing_mode(2); /* 0x 33 44 11 22 or 0x Y1 Cr Y0 Cb */
+		__cim_set_data_packing_mode(2); /* 0x 33 44 11 22 or 0x Y1 Cr Y0 Cb */
 		//__cim_set_data_packing_mode(3); /* 0x 44 11 22 33 or 0x Cr Y0 Cb Y1 */
-		__cim_set_data_packing_mode(4); /* 0x 44 33 22 11 or 0x Cr Y1 Cb Y0 */
+		//__cim_set_data_packing_mode(4); /* 0x 44 33 22 11 or 0x Cr Y1 Cb Y0 */
 		//__cim_set_data_packing_mode(5); /* 0x 33 22 11 44 or 0x Y1 Cb Y0 Cr */
 		//__cim_set_data_packing_mode(6); /* 0x 22 11 44 33 or 0x Cb Y0 Cr Y1 */
 		//__cim_set_data_packing_mode(7); /* 0x 11 44 33 22 or 0x Y0 Cr Y1 Cb */
@@ -637,7 +642,7 @@ static void cim_init_config(struct camera_sensor_desc *desc)
 
 	jz_cim->cim_cfg.cfg = cur_desc->cfg_info.configure_register;
 	jz_cim->cim_cfg.cfg &=~CIM_CFG_DMA_BURST_TYPE_MASK;
-#if defined(CONFIG_TEST_JZ4760E)
+#if defined(CONFIG_SOC_JZ4760B)
 	jz_cim->cim_cfg.cfg |= CIM_CFG_DMA_BURST_INCR32  | (0<<CIM_CFG_RXF_TRIG_BIT);// (n+1)*burst = 2*16 = 32 <64
 	jz_cim->cim_cfg.ctrl =  CIM_CTRL_DMA_SYNC | CIM_CTRL_FRC_1;
 #elif defined(CONFIG_SOC_JZ4760)
@@ -892,7 +897,7 @@ static irqreturn_t cim_irq_handler(int irq, void *dev_id)
        	{
 		if(likely(snapshot_flag != 1))
 	       	{
-			spin_lock_irqsave(fresh_lock,flags);
+			spin_lock_irqsave(&fresh_lock,flags);
 			jz_cim->preview_timeout_state = 1;
 
 			iprintk("__cim_get_iid() = %d\n", __cim_get_iid());
@@ -902,7 +907,7 @@ static irqreturn_t cim_irq_handler(int irq, void *dev_id)
 				fresh_id = SWAP_BUF-1;
 
 
-			spin_unlock_irqrestore(fresh_lock,flags);
+			spin_unlock_irqrestore(&fresh_lock,flags);
 
 			if(waitqueue_active(&jz_cim->preview_wait_queue))
 				wake_up_interruptible(&jz_cim->preview_wait_queue);
@@ -938,7 +943,7 @@ static irqreturn_t cim_irq_handler(int irq, void *dev_id)
 
 	state = state_back;
 	if ( (state & CIM_STATE_RXF_OF)
-#if defined(CONFIG_TEST_JZ4760E)
+#if defined(CONFIG_SOC_JZ4760B)
 	     || (state & CIM_STATE_Y_RF_OF) ||
 	     (state & CIM_STATE_CB_RF_OF) ||
 	     (state & CIM_STATE_CR_RF_OF)
@@ -948,7 +953,7 @@ static irqreturn_t cim_irq_handler(int irq, void *dev_id)
 		if (state & CIM_STATE_RXF_OF)
 			printk("OverFlow interrupt!\n");
 
-#if defined(CONFIG_TEST_JZ4760E)
+#if defined(CONFIG_SOC_JZ4760B)
 		if (state & CIM_STATE_Y_RF_OF)
 			printk("Y overflow interrupt!!!\n");
 
@@ -1082,7 +1087,7 @@ static unsigned int cim_get_preview_buf(int is_pbuf)
 
 	//cim_print_regs();
 
-/******/spin_lock_irqsave(fresh_lock,flags);/*********************************************************/
+/******/spin_lock_irqsave(&fresh_lock,flags);/*********************************************************/
 
 	iprintk("===>fresh_buf = %d fresh_id = %d\n", fresh_buf, fresh_id);
 	tmp_addr=frame_desc[fresh_id].framebuf;
@@ -1103,7 +1108,7 @@ static unsigned int cim_get_preview_buf(int is_pbuf)
 	jz_cim->preview_timeout_state = 0;
 	fresh_id = -1;
 
-/******/spin_unlock_irqrestore(fresh_lock,flags);/*******************************************************/
+/******/spin_unlock_irqrestore(&fresh_lock,flags);/*******************************************************/
 
 
 	if(likely(is_pbuf == 1))
diff --git a/drivers/misc/jz_cim/jz_sensor.c b/drivers/misc/jz_cim/jz_sensor.c
index f7faa8a3bac..d4da80f8c9d 100644
--- a/drivers/misc/jz_cim/jz_sensor.c
+++ b/drivers/misc/jz_cim/jz_sensor.c
@@ -18,10 +18,11 @@
 
 static inline int sensor_i2c_master_recv(struct i2c_client *client, char *buf ,int count);
 static inline int sensor_i2c_master_send(struct i2c_client *client,const char *buf ,int count);
+extern void i2c_jz_setclk(struct i2c_client *client,unsigned long i2cclk);
 
 void sensor_set_i2c_speed(struct i2c_client *client,unsigned long speed)
 {
-#if defined(CONFIG_SOC_JZ4760) || defined(CONFIG_JZ4760_F4760)
+#if defined(CONFIG_SOC_JZ4760) || defined(CONFIG_JZ4760_F4760) || defined(CONFIG_JZ4810_F4810)
 	i2c_jz_setclk(client,speed);
 #endif
 	//printk("set sensor i2c write read speed = %d hz\n",speed);
diff --git a/drivers/misc/opt_test.c b/drivers/misc/opt_test.c
new file mode 100644
index 00000000000..b5bf37f1d21
--- /dev/null
+++ b/drivers/misc/opt_test.c
@@ -0,0 +1,185 @@
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/kernel.h>
+#include <linux/fs.h>
+#include <linux/miscdevice.h>
+
+#include <asm/jzsoc.h>
+#include <asm/uaccess.h>
+
+#define OPTR_BASE 0xB34100E0
+#define REG_OPTR	REG32(OPTR_BASE)
+
+#define OPT_WRITE_PROTECT       1
+#define OPT_READ                2
+#define OPT_WRITE               3
+#define OPT_DUMP_REGS           4
+
+#define __opt_wait_write()			\
+	do {					\
+		while (REG_OPTR&(0x1 << 1));	\
+	} while(0)
+
+#define __opt_wait_read()			\
+	do {					\
+		while (REG_OPTR&(0x1 << 0));	\
+	} while(0)
+
+
+static char driver_name[] = "opt_test";
+
+struct opt_args {
+	char mode;		/* 0->read 1->write */
+	char section;		/* 128 bit has 8 sections */	
+	unsigned short data;	/* data to read or write */
+};
+
+
+static int opt_write_protect(void)
+{
+	unsigned tmp = ((0x7 << 2) | (0x1 << 31) | (0x2));	
+	tmp &= ~(0x1 << 5);
+	REG_OPTR = tmp;
+	__opt_wait_write();
+
+	return 0;
+}
+
+/* before you write check the APB clock musb be 100Mhz*/
+static int opt_test_write(char mode, char bit, unsigned short *data)
+
+{	unsigned short val;
+	unsigned int tmp = 0;
+
+	if (mode == 1) {
+		printk("you can't write chip space.\n");
+		return 0;
+	}
+	val = *data;
+	
+	tmp |= (bit << 2); /* write section */
+	tmp &= ~(0x1 << 5); /* write user area */
+	
+	tmp |= (val << 16);
+	
+	REG_OPTR = ((0x1 << 1) | tmp); /* write enable */
+	__opt_wait_write();
+
+	return 0;
+}
+
+static int opt_test_read(char mode, char bit, unsigned short *data)
+{
+	unsigned short val;
+	unsigned int tmp = 0;
+
+
+	tmp |= (bit << 2); /* read section*/
+	/* read user space */
+	if (mode == 0) {
+		tmp &= ~(0x1 << 5); /* read user area */
+	} else { 	
+		tmp |= (0x1 << 5);  /* read chip serial No */
+	}
+
+	REG_OPTR = ((0x1 << 0) | tmp); /* READ enable */
+	__opt_wait_read();
+
+	val = (REG_OPTR & 0xffff0000) >> 16;
+
+	if (data)
+		*data = val;
+	
+	return val;
+}
+
+static void opt_dump_regs(void)
+{
+	int i;
+	for (i = 0; i < 8; i++)
+		printk("USER section (%d) DATA: 0x%04x\n", i, opt_test_read(0, i, 0));
+	for (i = 0; i < 8; i++)
+		printk("CHIP section (%d) DATA: 0x%04x\n", i, opt_test_read(1, i, 0));
+}
+
+static int opt_open(struct inode *inode, struct file *file)
+{
+	return 0;
+}
+static int opt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
+{
+	int rv = 0;
+	struct opt_args my_args;
+
+	rv = copy_from_user(&my_args, (struct opt_args *)arg, sizeof(struct opt_args));
+	if (rv) {
+		printk("copy from user space failed.\n");
+		rv = -EFAULT;
+		return rv;
+	}
+	
+	switch(cmd) {
+	case OPT_WRITE_PROTECT:
+		opt_write_protect();
+		break;
+	case OPT_READ:
+		opt_test_read(my_args.mode, my_args.section, &my_args.data);
+		rv = copy_to_user((struct opt_args *)arg, &my_args, sizeof(struct opt_args));
+		if (rv) {
+			printk("copy to user space failed.\n");
+			return -EFAULT;
+		}
+		break;
+	case OPT_WRITE:
+		opt_test_write(my_args.mode, my_args.section, &(my_args.data));
+		break;
+
+	case OPT_DUMP_REGS:
+		opt_dump_regs();
+		break;
+
+	default:
+		printk("unknown command.\n");
+		break;
+	}
+
+	return rv;
+}
+
+static struct file_operations opt_fops = {
+	.owner	=	THIS_MODULE,
+	.open	=	opt_open,
+	.ioctl	=	opt_ioctl,
+};
+
+static struct miscdevice misc_opt = {
+	.minor	=	MISC_DYNAMIC_MINOR,
+	.name	= 	(char *)driver_name,
+	.fops	=	&opt_fops,
+};
+
+static int __init opt_test_init(void)
+{
+	int rv;
+
+	rv = misc_register(&misc_opt);
+	if (rv < 0) {
+		printk("register misc device opt failed.\n");
+		return rv;
+	}
+
+	printk("register misc device opt successed.\n");
+
+	return 0;
+}
+static void __exit opt_test_exit(void)
+{
+	misc_deregister(&misc_opt);
+	printk("deregister misc device opt.\n");
+}
+
+module_init(opt_test_init);
+module_exit(opt_test_exit);
+
+MODULE_LICENSE("Dual BSD/GPL");
diff --git a/drivers/mmc/card/block.c b/drivers/mmc/card/block.c
index 75d090cf88f..446cad8e17c 100644
--- a/drivers/mmc/card/block.c
+++ b/drivers/mmc/card/block.c
@@ -250,12 +250,25 @@ static int mmc_blk_issue_rq(struct mmc_queue *mq, struct request *req)
 		memset(&brq, 0, sizeof(struct mmc_blk_request));
 		brq.mrq.cmd = &brq.cmd;
 		brq.mrq.data = &brq.data;
+		brq.cmd.arg = blk_rq_pos(req);
+
+#if 0
+		if(!strcmp(mmc_hostname(card->host) ,"mmc0")){
+#if defined(CONFIG_JZ_BOOT_FROM_MSC0)
+			brq.cmd.arg = blk_rq_pos(req) + 16384;			
+#else
+			brq.cmd.arg = blk_rq_pos(req);
+#endif   
+		}
+		else
+			brq.cmd.arg = blk_rq_pos(req);
 
 #if defined( CONFIG_JZ_BOOT_FROM_MSC0)
 		brq.cmd.arg = blk_rq_pos(req) + 16384;
 #else
 		brq.cmd.arg = blk_rq_pos(req);
 #endif
+#endif
 		if (!mmc_card_blockaddr(card))
 			brq.cmd.arg <<= 9;
 		brq.cmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_R1 | MMC_CMD_ADTC;
@@ -393,6 +406,7 @@ static int mmc_blk_issue_rq(struct mmc_queue *mq, struct request *req)
 				 * so make sure to check both the busy
 				 * indication and the card state.
 				 */
+
 			} while (!(cmd.resp[0] & R1_READY_FOR_DATA) ||
 				(R1_CURRENT_STATE(cmd.resp[0]) == 7));
 
diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c
index d84c880fac8..656a8a499d2 100644
--- a/drivers/mmc/core/core.c
+++ b/drivers/mmc/core/core.c
@@ -866,8 +866,6 @@ void mmc_rescan(struct work_struct *work)
 		host->bus_ops->detect(host);
 
 	mmc_bus_put(host);
-
-
 	mmc_bus_get(host);
 
 	/* if there still is a card present, stop here */
@@ -935,7 +933,11 @@ out:
 void mmc_start_host(struct mmc_host *host)
 {
 	mmc_power_off(host);
+#if defined(CONFIG_JZ_SYSTEM_AT_CARD)
+	mmc_rescan(&host->detect.work);
+#else
 	mmc_detect_change(host, 0);
+#endif
 }
 
 void mmc_stop_host(struct mmc_host *host)
diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c
index 1e19f986d7d..855c0ad4bbe 100644
--- a/drivers/mmc/core/mmc.c
+++ b/drivers/mmc/core/mmc.c
@@ -121,7 +121,7 @@ static int mmc_decode_csd(struct mmc_card *card)
 	 * v1.2 has extra information in bits 15, 11 and 10.
 	 */
 	csd_struct = UNSTUFF_BITS(resp, 126, 2);
-	if (csd_struct != 1 && csd_struct != 2) {
+	if (csd_struct != 1 && csd_struct != 2 && csd_struct != 3) {
 		printk(KERN_ERR "%s: unrecognised CSD structure version %d\n",
 			mmc_hostname(card->host), csd_struct);
 		return -EINVAL;
@@ -141,13 +141,19 @@ static int mmc_decode_csd(struct mmc_card *card)
 	e = UNSTUFF_BITS(resp, 47, 3);
 	m = UNSTUFF_BITS(resp, 62, 12);
 
+#if 0
+	if(!strcmp(mmc_hostname(card->host) ,"mmc0")){
 #if defined(CONFIG_JZ_BOOT_FROM_MSC0)
-	csd->capacity	  = (1 + m) << (e + 2);
-	csd->capacity	  -= 16384;
+		csd->capacity	  = (1 + m) << (e + 2);
+		csd->capacity	  -= 16384;
 #else
-	csd->capacity	  = (1 + m) << (e + 2);
+		csd->capacity	  = (1 + m) << (e + 2);			
+#endif			
+	}
+	else
+		csd->capacity	  = (1 + m) << (e + 2);			
 #endif
-
+	csd->capacity	  = (1 + m) << (e + 2);			
 	csd->read_blkbits = UNSTUFF_BITS(resp, 80, 4);
 	csd->read_partial = UNSTUFF_BITS(resp, 79, 1);
 	csd->write_misalign = UNSTUFF_BITS(resp, 78, 1);
@@ -214,7 +220,7 @@ static int mmc_read_ext_csd(struct mmc_card *card)
 	}
 
 	ext_csd_struct = ext_csd[EXT_CSD_REV];
-	if (ext_csd_struct > 3) {
+	if (ext_csd_struct > 5) {
 		printk(KERN_ERR "%s: unrecognised EXT_CSD structure "
 			"version %d\n", mmc_hostname(card->host),
 			ext_csd_struct);
diff --git a/drivers/mmc/core/sd.c b/drivers/mmc/core/sd.c
index c68e7e5e39f..b0f14135d8b 100644
--- a/drivers/mmc/core/sd.c
+++ b/drivers/mmc/core/sd.c
@@ -110,13 +110,19 @@ static int mmc_decode_csd(struct mmc_card *card)
 		e = UNSTUFF_BITS(resp, 47, 3);
 		m = UNSTUFF_BITS(resp, 62, 12);
 
+#if 0
+		if(!strcmp(mmc_hostname(card->host) ,"mmc0")){
 #if defined(CONFIG_JZ_BOOT_FROM_MSC0)
-		csd->capacity	  = (1 + m) << (e + 2);
-		csd->capacity	  -= 16384;
+			csd->capacity	  = (1 + m) << (e + 2);
+			csd->capacity	  -= 16384;
 #else
-		csd->capacity	  = (1 + m) << (e + 2);
+			csd->capacity	  = (1 + m) << (e + 2);			
+#endif			
+		}
+		else
+			csd->capacity	  = (1 + m) << (e + 2);			
 #endif
-
+		csd->capacity	  = (1 + m) << (e + 2);			
 		csd->read_blkbits = UNSTUFF_BITS(resp, 80, 4);
 		csd->read_partial = UNSTUFF_BITS(resp, 79, 1);
 		csd->write_misalign = UNSTUFF_BITS(resp, 78, 1);
@@ -629,6 +635,8 @@ static void mmc_sd_resume(struct mmc_host *host)
 static const struct mmc_bus_ops mmc_sd_ops = {
 	.remove = mmc_sd_remove,
 	.detect = mmc_sd_detect,
+//	.sysfs_add = mmc_sd_sysfs_add,
+//	.sysfs_remove = mmc_sd_sysfs_remove,
 	.suspend = mmc_sd_suspend,
 	.resume = mmc_sd_resume,
 };
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 0d4e673cfd0..69dae6c9e92 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -32,10 +32,17 @@ config JZ_MMC_BUS_4
 
 endchoice
 
+config MMC_JZSOC
+	tristate "Ingenic MMC/SD/SDIO controller support"
+	depends on SOC_JZ4750 || SOC_JZ4750D || SOC_JZ4760 || SOC_JZ4760B
+	default y
+	help
+	  this selects Ingenic MMC/SD/SDIO controller support, it was automatically selected
+
 
 config JZ_MSC0
 	tristate "JZ SOC Multimedia/SD/SDIO host controller 0 support"
-	depends on SOC_JZ4750 || SOC_JZ4750D || SOC_JZ4760
+	depends on SOC_JZ4750 || SOC_JZ4760 || SOC_JZ4760B || (SOC_JZ4750D && (!MTD_NAND))
 	help
 	  this selects the Ingenic Multimedia/SD/SDIO host controller 0.
 	  If you have a Ingenic platform with a Multimedia Card slot,
@@ -72,6 +79,7 @@ endchoice
 config JZ_MSC0_SDIO_SUPPORT
 	bool "SDIO support for Multimedia/SD/SDIO controller 0"
 	depends on JZ_MSC0
+	depends on !JZ_SYSTEM_AT_CARD
 	help
 	  SDIO support for MSC0.
 
@@ -79,7 +87,7 @@ config JZ_MSC0_SDIO_SUPPORT
 
 config JZ_MSC1
 	tristate "JZ SOC Multimedia/SD/SDIO host controller 1 support"
-	depends on SOC_JZ4750 || SOC_JZ4750D || SOC_JZ4760
+	depends on MMC_JZSOC
 	help
 	  this selects the Ingenic Multimedia/SD/SDIO host controller 1.
 	  If you have a Ingenic platform with a Multimedia Card slot,
@@ -123,7 +131,7 @@ config JZ_MSC1_SDIO_SUPPORT
 
 config JZ_MSC2
 	tristate "JZ SOC Multimedia/SD/SDIO host controller 2 support"
-	depends on SOC_JZ4760
+	depends on MMC_JZSOC && (SOC_JZ4760 || SOC_JZ4760B)
 	help
 	  this selects the Ingenic Multimedia/SD/SDIO host controller 2.
 	  If you have a Ingenic platform with a Multimedia Card slot,
@@ -165,15 +173,23 @@ config JZ_MSC2_SDIO_SUPPORT
 
 	  If unsure,say N.
 
-config JZ_BOOT_FROM_MSC0
-	tristate "Boot from Ingenic Multimedia/SD/SDIO Card Interface 0 support"
-	depends on SOC_JZ4750 || SOC_JZ4750D || SOC_JZ4760
-	depends on JZ_MSC0
+config JZ_SYSTEM_AT_CARD
+	bool "System at MMC/SD  support"
+	depends on SOC_JZ4750 || SOC_JZ4750D || SOC_JZ4760 || SOC_JZ4760B
+	depends on JZ_MSC0 
 	help
-	  This selects boot from the Multimedia/SD/SDIO Card.
+	  This selects uboot kernel fs at the Multimedia/SD/SDIO Card.
 
 	  If unsure,say N.
 
+config JZ_RECOVERY_SUPPORT
+    tristate "Ingenic Liunx Recovery tool support for card system"
+    depends on SOC_JZ4750D || SOC_JZ4760 || SOC_JZ4760B
+    depends on JZ_SYSTEM_AT_CARD
+    default n
+    help
+      This selects Ingenic Liunx Recovery tool support.
+      
 config MMC_ARMMMCI
 	tristate "ARM AMBA Multimedia Card Interface support"
 	depends on ARM_AMBA
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index bbaeeb2fc70..9a1ac87987e 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -7,8 +7,7 @@ ifeq ($(CONFIG_MMC_DEBUG),y)
 endif
 
 obj-$(CONFIG_MMC_JZ)		+= jz_mmc.o
-obj-$(CONFIG_JZ_MSC0)       += jzmmc/
-obj-$(CONFIG_JZ_MSC1)       += jzmmc/
+obj-$(CONFIG_MMC_JZSOC)       += jzmmc/
 
 obj-$(CONFIG_MMC_ARMMMCI)	+= mmci.o
 obj-$(CONFIG_MMC_PXA)		+= pxamci.o
diff --git a/drivers/mmc/host/jzmmc/Makefile b/drivers/mmc/host/jzmmc/Makefile
index e6247deb7c3..dbc06a6258b 100644
--- a/drivers/mmc/host/jzmmc/Makefile
+++ b/drivers/mmc/host/jzmmc/Makefile
@@ -2,5 +2,9 @@
 # Makefile for MMC/SD host controller drivers
 #
 
-obj-$(CONFIG_JZ_MSC0)	+= controller/ jz_mmc_main.o
-obj-$(CONFIG_JZ_MSC1)	+= controller/ jz_mmc_main.o
+obj-$(CONFIG_MMC_JZSOC) += jz_mmc_main.o \
+			jz_mmc_controller.o \
+			jz_mmc_msc.o \
+			jz_mmc_dma.o \
+			jz_mmc_pio.o \
+			jz_mmc_gpio.o
diff --git a/drivers/mmc/host/jzmmc/controller/Makefile b/drivers/mmc/host/jzmmc/controller/Makefile
deleted file mode 100644
index fbeb4e61d5d..00000000000
--- a/drivers/mmc/host/jzmmc/controller/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-#
-# Makefile for MMC/SD host controller drivers
-#
-
-obj-$(CONFIG_JZ_MSC0)	+= msc/ dma/ gpio/ jz_mmc_controller.o
-obj-$(CONFIG_JZ_MSC1)	+= msc/ dma/ gpio/ jz_mmc_controller.o
diff --git a/drivers/mmc/host/jzmmc/controller/dma/Makefile b/drivers/mmc/host/jzmmc/controller/dma/Makefile
deleted file mode 100644
index 322b1b32804..00000000000
--- a/drivers/mmc/host/jzmmc/controller/dma/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-#
-# Makefile for MMC/SD host controller drivers
-#
-
-obj-$(CONFIG_JZ_MSC0)	+= jz_mmc_dma.o
-obj-$(CONFIG_JZ_MSC1)	+= jz_mmc_dma.o
diff --git a/drivers/mmc/host/jzmmc/controller/dma/jz_mmc_dma.c b/drivers/mmc/host/jzmmc/controller/dma/jz_mmc_dma.c
deleted file mode 100644
index e343d024604..00000000000
--- a/drivers/mmc/host/jzmmc/controller/dma/jz_mmc_dma.c
+++ /dev/null
@@ -1,347 +0,0 @@
-/*

- *  linux/drivers/mmc/host/jz_mmc/dma/jz_mmc_dma.c

- *

- * This program is free software; you can redistribute it and/or modify

- * it under the terms of the GNU General Public License version 2 as

- * published by the Free Software Foundation.

- *

- * Copyright (c) Ingenic Semiconductor Co., Ltd.

- */

-

-

-#include <asm/jzsoc.h>

-#include <asm/jzmmc/jz_mmc_dma.h>

-#include <linux/scatterlist.h>

-

-#ifdef USE_DMA_DESC

-static inline int best_burst_size(unsigned int dma_len) {

-#ifdef USE_DMA_BUSRT_64

-	if (dma_len % 64 == 0)

-		return 64;

-#endif

-

-	if (dma_len % 32 == 0)

-		return 32;

-

-	if (dma_len % 16 == 0)

-		return 16;

-

-#ifdef USE_DMA_BUSRT_64

-	if (dma_len > 64)

-		return 64;

-#endif

-

-	if (dma_len > 32)

-		return 32;

-

-	if (dma_len > 16)

-		return 16;

-

-	return 4;

-}

-

-static void sg_to_desc(struct scatterlist *sgentry, struct jz_mmc_host *host, int *desc_pos /* IN OUT */, int mode) {

-	jz_dma_desc *desc;

-	int pos = *desc_pos;

-	unsigned int ds = 32; /* ehh, 32byte is the best */

-	unsigned int next;

-	dma_addr_t dma_addr;

-	unsigned int dma_len;

-	unsigned int head_unalign_size = 0; /* ds = 4byte */

-	unsigned int aligned_size = 0;

-	unsigned int tail_unalign_size = 0; /* ds = 4byte */

-

-	dma_addr = sg_dma_address(sgentry);

-	dma_len = sg_dma_len(sgentry);

-

-	BUG_ON(dma_len % 4); /* we do NOT support transfer size < 4byte */

-

-	ds = best_burst_size(dma_len);

-	head_unalign_size = dma_addr & (ds - 1);

-	tail_unalign_size = (dma_addr + dma_len) & (ds - 1);

-	aligned_size = dma_len - head_unalign_size - tail_unalign_size;

-

-	BUG_ON(head_unalign_size % 4);

-	BUG_ON(tail_unalign_size % 4);

-

-	if (head_unalign_size) {

-		desc = host->dma_desc + pos;

-		next = (host->dma_desc_phys_addr + (pos + 1) * (sizeof(jz_dma_desc))) >> 4;

-		desc->dcmd = DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 | DMAC_DCMD_DS_32BIT | DMAC_DCMD_RDIL_IGN |

-#ifndef CONFIG_SOC_JZ4760

-			DMAC_DCMD_DES_V | DMAC_DCMD_DES_VM | DMAC_DCMD_DES_VIE |

-#endif

-			DMAC_DCMD_LINK;

-		if (DMA_MODE_WRITE == mode) {

-			desc->dcmd |= DMAC_DCMD_SAI;

-			desc->dsadr = (unsigned int)dma_addr;      /* DMA source address */

-			desc->dtadr = CPHYSADDR(MSC_TXFIFO(host->pdev_id));      /* DMA target address */

-		} else {

-			desc->dcmd |= DMAC_DCMD_DAI;

-			desc->dsadr = CPHYSADDR(MSC_RXFIFO(host->pdev_id));

-			desc->dtadr = (unsigned int)dma_addr;

-		}

-		desc->ddadr = (next << 24) | (head_unalign_size >> 2) ;

-

-		pos ++;

-	}

-

-	if (aligned_size) {

-		desc = host->dma_desc + pos;

-		next = (host->dma_desc_phys_addr + (pos + 1) * (sizeof(jz_dma_desc))) >> 4;

-

-		desc->dcmd = DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 | DMAC_DCMD_RDIL_IGN |

-#ifndef CONFIG_SOC_JZ4760

-			DMAC_DCMD_DES_V | DMAC_DCMD_DES_VM | DMAC_DCMD_DES_VIE |

-#endif

-			 DMAC_DCMD_LINK;

-		switch (ds) {

-#ifdef USE_DMA_BUSRT_64

-		case 64:

-			desc->dcmd |= DMAC_DCMD_DS_64BYTE;

-			break;

-#endif

-

-		case 32:

-			desc->dcmd |= DMAC_DCMD_DS_32BYTE;

-			break;

-

-		case 16:

-			desc->dcmd |= DMAC_DCMD_DS_16BYTE;

-			break;

-

-		case 4:

-			desc->dcmd |= DMAC_DCMD_DS_32BIT;

-			break;

-

-		default:

-			;

-		}

-

-		if (DMA_MODE_WRITE == mode) {

-			desc->dcmd |= DMAC_DCMD_SAI;

-			desc->dsadr = (unsigned int)(dma_addr + head_unalign_size);      /* DMA source address */

-			desc->dtadr = CPHYSADDR(MSC_TXFIFO(host->pdev_id));      /* DMA target address */

-		} else {

-			desc->dcmd |= DMAC_DCMD_DAI;

-			desc->dsadr = CPHYSADDR(MSC_RXFIFO(host->pdev_id));

-			desc->dtadr = (unsigned int)(dma_addr + head_unalign_size);;

-		}

-		desc->ddadr = (next << 24) | (aligned_size  / ds) ;

-

-		pos ++;

-	}

-

-

-	if (tail_unalign_size) {

-		desc = host->dma_desc + pos;

-		next = (host->dma_desc_phys_addr + (pos + 1) * (sizeof(jz_dma_desc))) >> 4;

-

-		desc->dcmd = DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 | DMAC_DCMD_DS_32BIT |   DMAC_DCMD_RDIL_IGN |

-#ifndef CONFIG_SOC_JZ4760

-			DMAC_DCMD_DES_V | DMAC_DCMD_DES_VM | DMAC_DCMD_DES_VIE |

-#endif

-			DMAC_DCMD_LINK;

-		if (DMA_MODE_WRITE == mode) {

-			desc->dcmd |= DMAC_DCMD_SAI;

-			desc->dsadr = (unsigned int)(dma_addr + head_unalign_size + aligned_size);      /* DMA source address */

-			desc->dtadr = CPHYSADDR(MSC_TXFIFO(host->pdev_id));      /* DMA target address */

-		} else {

-			desc->dcmd |= DMAC_DCMD_DAI;

-			desc->dsadr = CPHYSADDR(MSC_RXFIFO(host->pdev_id));

-			desc->dtadr = (unsigned int)(dma_addr + head_unalign_size + aligned_size);;

-		}

-		desc->ddadr = (next << 24) | (tail_unalign_size >> 2) ;

-

-		pos ++;

-

-	}

-

-	*desc_pos = pos;

-}

-

-void jz_mmc_start_scatter_dma(int chan, struct jz_mmc_host *host,

-			      struct scatterlist *sg, unsigned int sg_len, int mode) {

-	int i = 0;

-	int desc_pos = 0;

-	struct mmc_data *data = host->curr.data;

-	struct scatterlist *sgentry;

-	jz_dma_desc *desc;

-	unsigned int next;

-	unsigned long flags;

-

-	memset(host->dma_desc, 0, PAGE_SIZE);

-

-	desc = host->dma_desc;

-	next = (host->dma_desc_phys_addr + (sizeof(jz_dma_desc))) >> 4;

-

-	desc_pos = 0;

-	flags = claim_dma_lock();

-	for_each_sg(data->sg, sgentry, host->dma.len, i) {

-		sg_to_desc(sgentry, host, &desc_pos, mode);

-	}

-

-	desc = host->dma_desc + (desc_pos - 1);

-	desc->dcmd |= DMAC_DCMD_TIE;

-	desc->dcmd &= ~DMAC_DCMD_LINK;

-	desc->ddadr &= ~0xff000000;

-

-	dma_cache_wback_inv((unsigned long)desc, desc_pos * (sizeof(jz_dma_desc)));

-

-        /* Setup DMA descriptor address */

-	REG_DMAC_DDA(chan) = host->dma_desc_phys_addr;

-

-	/* Setup request source */

-	if (DMA_MODE_WRITE == mode) {

-		if(host->pdev_id == 0)

-			REG_DMAC_DRSR(chan) = DMAC_DRSR_RS_MSC0OUT;

-		else if(host->pdev_id == 1)

-			REG_DMAC_DRSR(chan) = DMAC_DRSR_RS_MSC1OUT;

-		else

-#ifdef  DMAC_DRSR_RS_MSC2OUT

-			REG_DMAC_DRSR(chan) = DMAC_DRSR_RS_MSC2OUT;

-#else

-		;

-#endif

-	} else {

-		if(host->pdev_id == 0)

-			REG_DMAC_DRSR(chan) = DMAC_DRSR_RS_MSC0IN;

-		else if(host->pdev_id == 1)

-			REG_DMAC_DRSR(chan) = DMAC_DRSR_RS_MSC1IN;

-		else

-#ifdef  DMAC_DRSR_RS_MSC2IN

-			REG_DMAC_DRSR(chan) = DMAC_DRSR_RS_MSC2IN;

-#else

-		;

-#endif

-	}

-

-	/* Setup DMA channel control/status register */

-	REG_DMAC_DCCSR(chan) = DMAC_DCCSR_EN;	/* descriptor transfer, clear status, start channel */

-

-	/* Enable DMA */

-	REG_DMAC_DMACR(chan / HALF_DMA_NUM) = DMAC_DMACR_DMAE;

-

-	/* DMA doorbell set -- start DMA now ... */

-	REG_DMAC_DMADBSR(chan / HALF_DMA_NUM) = 1 << (chan - (chan / HALF_DMA_NUM) * HALF_DMA_NUM) ;

-

-	release_dma_lock(flags);

-

-}

-#else

-void jz_mmc_start_dma(int chan, unsigned long phyaddr, int count, int mode, int ds)

-{

-	unsigned long flags;

-

-	flags = claim_dma_lock();

-	disable_dma(chan);

-	clear_dma_ff(chan);

-	jz_set_dma_src_width(chan, 32);

-	jz_set_dma_dest_width(chan, 32);

-	jz_set_dma_block_size(chan, ds);

-	set_dma_mode(chan, mode);

-	set_dma_addr(chan, phyaddr);

-	set_dma_count(chan, (count + ds - 1));

-	enable_dma(chan);

-	release_dma_lock(flags);

-}

-#endif

-

-static irqreturn_t jz_mmc_dma_rx_callback(int irq, void *devid)

-{

-	struct jz_mmc_host *host = devid;

-	int chan = host->dma.rxchannel;

-

-	disable_dma(chan);

-	if (__dmac_channel_address_error_detected(chan)) {

-		printk("%s: DMAC address error.\n",

-		       __FUNCTION__);

-		__dmac_channel_clear_address_error(chan);

-	}

-	if (__dmac_channel_transmit_end_detected(chan)) {

-		__dmac_channel_clear_transmit_end(chan);

-	}

-

-	return IRQ_HANDLED;

-}

-

-static irqreturn_t jz_mmc_dma_tx_callback(int irq, void *devid)

-{

-	struct jz_mmc_host *host = devid;

-	unsigned int chan = host->dma.txchannel;

-

-	disable_dma(chan);

-	if (__dmac_channel_address_error_detected(chan)) {

-		printk("%s: DMAC address error.\n",

-		       __FUNCTION__);

-		__dmac_channel_clear_address_error(chan);

-	}

-	if (__dmac_channel_transmit_end_detected(chan)) {

-		__dmac_channel_clear_transmit_end(chan);

-	}

-

-	return IRQ_HANDLED;

-}

-

-static int jz_mmc_init_dma(struct jz_mmc_host *host)

-{

-	host->dma.rxchannel = -1;

-	host->dma.txchannel = -1;

-

-	if (!host->dmares)

-		return -ENODEV;

-

-	host->dma.rxchannel = jz_request_dma(host->dmares->start, "dma-rx", jz_mmc_dma_rx_callback,

-			       0, host);

-	if (host->dma.rxchannel < 0) {

-		printk(KERN_ERR "jz_request_dma failed for MMC Rx\n");

-		goto err1;

-	}

-

-	if (host->dma.rxchannel < 6)

-		REG_DMAC_DMACR(0) |= DMAC_DMACR_FMSC;

-	else

-		REG_DMAC_DMACR(1) |= DMAC_DMACR_FMSC;

-

-	/* Request MMC Tx DMA channel */

-	host->dma.txchannel = jz_request_dma(host->dmares->end, "dma-tx", jz_mmc_dma_tx_callback,

-			       0, host);

-	if (host->dma.txchannel < 0) {

-		printk(KERN_ERR "jz_request_dma failed for MMC Tx\n");

-		goto err2;

-	}

-

-	if (host->dma.txchannel < 6)

-		REG_DMAC_DMACR(0) |= DMAC_DMACR_FMSC;

-	else

-		REG_DMAC_DMACR(1) |= DMAC_DMACR_FMSC;

-

-#ifdef USE_DMA_DESC

-	host->dma_desc = (jz_dma_desc *)__get_free_pages(GFP_KERNEL, 0); /* 4096 / 4 = 1024 descriptor max */

-	host->dma_desc_phys_addr = CPHYSADDR((unsigned long)host->dma_desc);

-#endif

-

-	return 0;

-

-err2:

-	jz_free_dma(host->dma.rxchannel);

-err1:

-	return -ENODEV;

-}

-

-static void jz_mmc_deinit_dma(struct jz_mmc_host *host)

-{

-	jz_free_dma(host->dma.rxchannel);

-	jz_free_dma(host->dma.txchannel);

-}

-

-int jz_mmc_dma_register(struct jz_mmc_dma *dma)

-{

-	if(dma == NULL)

-		return -ENOMEM;

-

-	dma->init = jz_mmc_init_dma;

-	dma->deinit = jz_mmc_deinit_dma;

-

-	return 0;

-}

diff --git a/drivers/mmc/host/jzmmc/controller/gpio/Makefile b/drivers/mmc/host/jzmmc/controller/gpio/Makefile
deleted file mode 100644
index 469757cc539..00000000000
--- a/drivers/mmc/host/jzmmc/controller/gpio/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-#
-# Makefile for MMC/SD host controller drivers
-#
-
-obj-$(CONFIG_JZ_MSC0)	+= jz_mmc_gpio.o
-obj-$(CONFIG_JZ_MSC1)	+= jz_mmc_gpio.o
diff --git a/drivers/mmc/host/jzmmc/controller/msc/Makefile b/drivers/mmc/host/jzmmc/controller/msc/Makefile
deleted file mode 100644
index 2538c469be5..00000000000
--- a/drivers/mmc/host/jzmmc/controller/msc/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-#
-# Makefile for MMC/SD host controller drivers
-#
-
-obj-$(CONFIG_JZ_MSC0)	+= jz_mmc_msc.o
-obj-$(CONFIG_JZ_MSC1)	+= jz_mmc_msc.o
diff --git a/drivers/mmc/host/jzmmc/controller/msc/jz_mmc_msc.c b/drivers/mmc/host/jzmmc/controller/msc/jz_mmc_msc.c
deleted file mode 100644
index 1e94aea4ebe..00000000000
--- a/drivers/mmc/host/jzmmc/controller/msc/jz_mmc_msc.c
+++ /dev/null
@@ -1,799 +0,0 @@
-/*

- *  linux/drivers/mmc/host/jz_mmc/msc/jz_mmc_msc.c

- *

- * This program is free software; you can redistribute it and/or modify

- * it under the terms of the GNU General Public License version 2 as

- * published by the Free Software Foundation.

- *

- * Copyright (c) Ingenic Semiconductor Co., Ltd.

- */

-

-#include <linux/dma-mapping.h>

-#include <linux/semaphore.h>

-#include <linux/kthread.h>

-#include <linux/mmc/mmc.h>

-#include <linux/mmc/sd.h>

-#include <linux/mmc/sdio.h>

-#include <linux/scatterlist.h>

-

-#include <asm/jzsoc.h>

-#include <asm/jzmmc/jz_mmc_msc.h>

-

-#define MSC_STAT_ERR_BITS 0x3f

-

-#if 1

-

-static int jzmmc_trace_level = 0;

-static int jzmmc_trace_cmd_code = -1;

-static int jzmmc_trace_data_len = -1;

-module_param(jzmmc_trace_level, int, 0644);

-module_param(jzmmc_trace_cmd_code, int, 0644);

-module_param(jzmmc_trace_data_len, int, 0644);

-

-#define TRACE_CMD_REQ()							\

-	({								\

-		if (jzmmc_trace_level & 0x1)				\

-			if ( (jzmmc_trace_cmd_code == -1) || (jzmmc_trace_cmd_code == cmd->opcode) ) \

-				printk("%s:     execute_cmd: opcode = %d cmdat = %#0x arg = %#0x data_flags = %#0x\n", \

-				       mmc_hostname(host->mmc), cmd->opcode, cmdat, cmdarg, \

-				       host->curr.data ? host->curr.data->flags : 0); \

-	})

-

-#define TRACE_CMD_RES()							\

-	({								\

-		if (jzmmc_trace_level & 0x1)				\

-			if ( (jzmmc_trace_cmd_code == -1) || (jzmmc_trace_cmd_code == cmd->opcode) ) \

-				printk("%s:     cmd done: r_type = %d resp[0] = %#0x err = %d state = %#0x\n", \

-				       mmc_hostname(host->mmc), host->curr.r_type, cmd->resp[0], cmd->error, \

-				       REG_MSC_STAT(host->pdev_id));	\

-	})

-

-#define TRACE_DATA_REQ()						\

-	({								\

-		if ( (jzmmc_trace_level & 0x2) && host->curr.data ) {	\

-			if ((jzmmc_trace_data_len == -1) ||		\

-			    (jzmmc_trace_data_len == host->curr.data->blksz * host->curr.data->blocks) ) \

-				printk("%s:     blksz %d blocks %d flags %08x "	\

-				       "tsac %d ms nsac %d\n",		\

-				       mmc_hostname(host->mmc), host->curr.data->blksz, \

-				       host->curr.data->blocks, host->curr.data->flags, \

-				       host->curr.data->timeout_ns / 1000000, \

-				       host->curr.data->timeout_clks); \

-		}							\

-	})

-

-#define TRACE_DATA_DONE()						\

-	({								\

-		if (jzmmc_trace_level & 0x2)				\

-			if ((jzmmc_trace_data_len == -1) ||		\

-			    (jzmmc_trace_data_len == data->blksz * data->blocks) ) \

-				printk("%s:     stat = 0x%08x error = %d bytes_xfered = %d stop = %p\n", \

-				       mmc_hostname(host->mmc), stat, data->error, \

-				       data->bytes_xfered, host->curr.mrq->stop); \

-	})

-#else

-#define TRACE_CMD_REQ() do {  } while(0)

-#define TRACE_CMD_RES() do {  } while(0)

-#define TRACE_DATA_REQ() do {  } while(0)

-#define TRACE_DATA_DONE() do {  } while(0)

-#endif

-

-//#define DEBUG 1

-

-#ifdef DEBUG

-static void jz_mmc_dump_register(int msc_id) {

-	printk("***** mmc%d registers *****\n",msc_id);

-	printk("\tREG_MSC_STRPCL(%d) = 0x%08x\n", msc_id, REG_MSC_STRPCL(msc_id));

-	printk("\tREG_MSC_STAT(%d) = 0x%08x\n", msc_id, REG_MSC_STAT(msc_id));

-	printk("\tREG_MSC_CLKRT(%d) = 0x%08x\n", msc_id, REG_MSC_CLKRT(msc_id));

-	printk("\tREG_MSC_CMDAT(%d) = 0x%08x\n", msc_id, REG_MSC_CMDAT(msc_id));

-	printk("\tREG_MSC_RESTO(%d) = 0x%08x\n", msc_id, REG_MSC_RESTO(msc_id));

-	printk("\tREG_MSC_RDTO(%d) = 0x%08x\n", msc_id, REG_MSC_RDTO(msc_id));

-	printk("\tREG_MSC_BLKLEN(%d) = 0x%08x\n", msc_id, REG_MSC_BLKLEN(msc_id));

-	printk("\tREG_MSC_NOB(%d) = 0x%08x\n", msc_id, REG_MSC_NOB(msc_id));

-	printk("\tREG_MSC_SNOB(%d) = 0x%08x\n", msc_id, REG_MSC_SNOB(msc_id));

-	printk("\tREG_MSC_IMASK(%d) = 0x%08x\n", msc_id, REG_MSC_IMASK(msc_id));

-	printk("\tREG_MSC_IREG(%d) = 0x%08x\n", msc_id, REG_MSC_IREG(msc_id));

-	printk("\tREG_MSC_CMD(%d) = 0x%08x\n", msc_id, REG_MSC_CMD(msc_id));

-	printk("\tREG_MSC_ARG(%d) = 0x%08x\n", msc_id, REG_MSC_ARG(msc_id));

-	printk("\tREG_MSC_RES(%d) = 0x%08x\n", msc_id, REG_MSC_RES(msc_id));

-	printk("\tREG_MSC_RXFIFO(%d) = 0x%08x\n", msc_id, REG_MSC_RXFIFO(msc_id));

-	printk("\tREG_MSC_TXFIFO(%d) = 0x%08x\n", msc_id, REG_MSC_TXFIFO(msc_id));

-	printk("\tREG_MSC_LPM(%d) = 0x%08x\n", msc_id, REG_MSC_LPM(msc_id));

-}

-

-static struct timer_list debug_timer;

-#define DEBUG_INTERVAL HZ/2

-

-static void debug_func(unsigned long arg) {

-	int msc_id = (int)arg;

-	jz_mmc_dump_register(msc_id);

-

-	debug_timer.expires += DEBUG_INTERVAL;

-

-	add_timer(&debug_timer);

-}

-

-static void start_debug_timer(int msc_id) {

-	static int dbg_tm_need_init = 1;

-

-	if (dbg_tm_need_init) {

-		dbg_tm_need_init = 0;

-		init_timer(&debug_timer);

-		debug_timer.function = debug_func;

-	}

-

-	debug_timer.expires = jiffies + DEBUG_INTERVAL;

-	debug_timer.data = (unsigned long)msc_id;

-

-	add_timer(&debug_timer);

-}

-

-static void stop_debug_timer(int msc_id __attribute((unused))) {

-	del_timer_sync(&debug_timer);

-}

-

-#endif

-

-void jz_mmc_set_clock(struct jz_mmc_host *host, int rate);

-static int jz_mmc_data_done(struct jz_mmc_host *host);

-

-static void msc_irq_mask_all(int msc_id)

-{

-	REG_MSC_IMASK(msc_id) = 0xffff;

-	REG_MSC_IREG(msc_id) = 0xffff;

-}

-

-static void jz_mmc_reset(struct jz_mmc_host *host)

-{

-	REG_MSC_STRPCL(host->pdev_id) = MSC_STRPCL_RESET;

- 	while (REG_MSC_STAT(host->pdev_id) & MSC_STAT_IS_RESETTING);

-}

-

-static inline int msc_calc_clkrt(int is_low, u32 rate)

-{

-	u32 clkrt;

-	u32 clk_src = is_low ? 24000000 : 48000000;

-

-	clkrt = 0;

-	while (rate < clk_src) {

-		clkrt++;

-		clk_src >>= 1;

-	}

-	return clkrt;

-}

-

-void jz_mmc_set_clock(struct jz_mmc_host *host, int rate)

-{

-	int clkrt;

-

-	/* __cpm_select_msc_clk_high will select 48M clock for MMC/SD card

-	 * perhaps this will made some card with bad quality init fail,or

-	 * bad stabilization.

-	*/

-

-	// Cause there is only ONE devider in CPM, the clock must only <= 24MHz

-#if !defined(CONFIG_SOC_JZ4750) && !defined(CONFIG_SOC_JZ4750D)

-#if 0

-	if (rate > SD_CLOCK_FAST) {

-		cpm_set_clock(CGU_MSCCLK, 48 * 1000 * 1000);

-		clkrt = msc_calc_clkrt(0, rate);

-	} else {

-		cpm_set_clock(CGU_MSCCLK, 24 * 1000 * 1000);

-		clkrt = msc_calc_clkrt(1, rate);

-	}

-#else

-	if (rate > SD_CLOCK_FAST) {

-		rate = SD_CLOCK_FAST;

-		cpm_set_clock(CGU_MSCCLK, 24 * 1000 * 1000);

-		clkrt = msc_calc_clkrt(1, rate);

-	} else {

-		cpm_set_clock(CGU_MSCCLK, 24 * 1000 * 1000);

-		clkrt = msc_calc_clkrt(1, rate);

-	}

-#endif

-	REG_MSC_CLKRT(host->pdev_id) = clkrt;

-#else

-		/* __cpm_select_msc_clk_high will select 48M clock for MMC/SD card

-	 * perhaps this will made some card with bad quality init fail,or

-	 * bad stabilization.

-	*/

-	if (rate > SD_CLOCK_FAST) {

-		rate = SD_CLOCK_FAST;

-		__cpm_select_msc_clk_high(host->pdev_id,1);	/* select clock source from CPM */

-

-		//		__cpm_select_msc_clk(host->pdev_id,1);	/* select clock source from CPM */

-		clkrt = msc_calc_clkrt(0, rate);

-	} else {

-		__cpm_select_msc_clk(host->pdev_id,1);	/* select clock source from CPM */

-		clkrt = msc_calc_clkrt(1, rate);

-	}

-

-	// printk("clock rate = %d\n", __cpm_get_mscclk(0));

-	REG_MSC_CLKRT(host->pdev_id) = clkrt;

-#endif

-}

-

-static void jz_mmc_enable_irq(struct jz_mmc_host *host, unsigned int mask)

-{

-	unsigned long flags;

-

-	spin_lock_irqsave(&host->lock, flags);

-	host->imask &= ~mask;

-	REG_MSC_IMASK(host->pdev_id) = host->imask;

-	spin_unlock_irqrestore(&host->lock, flags);

-}

-

-static void jz_mmc_disable_irq(struct jz_mmc_host *host, unsigned int mask)

-{

-	unsigned long flags;

-

-	spin_lock_irqsave(&host->lock, flags);

-	host->imask |= mask;

-	REG_MSC_IMASK(host->pdev_id) = host->imask;

-	spin_unlock_irqrestore(&host->lock, flags);

-}

-

-static void jz_mmc_finish_request(struct jz_mmc_host *host, struct mmc_request *mrq)

-{

-	host->curr.mrq = NULL;

-	host->curr.cmd = NULL;

-	host->curr.data = NULL;

-	mmc_request_done(host->mmc, mrq);

-}

-

-static int jz_mmc_cmd_done(struct jz_mmc_host *host, unsigned int stat)

-{

-	struct mmc_command *cmd = host->curr.cmd;

-	int i, temp[16] = {0};

-	unsigned char *buf;

-	unsigned int data, v, w1, w2;

-

-	if (!cmd)

-		return 0;

-

-	host->curr.cmd = NULL;

-	buf = (u8 *) temp;

-	switch (host->curr.r_type) {

-	case 1:

-	{

-		/*

-		 * Did I mention this is Sick.  We always need to

-		 * discard the upper 8 bits of the first 16-bit word.

-		 */

-

-		data = REG_MSC_RES(host->pdev_id);

-		buf[0] = (data >> 8) & 0xff;

-		buf[1] = data & 0xff;

-

-		data = REG_MSC_RES(host->pdev_id);

-		buf[2] = (data >> 8) & 0xff;

-		buf[3] = data & 0xff;

-

-		data = REG_MSC_RES(host->pdev_id);

-		buf[4] = data & 0xff;

-

-		cmd->resp[0] =

-			buf[1] << 24 | buf[2] << 16 | buf[3] << 8 |

-			buf[4];

-

-		// printk("opcode = %d, cmd->resp = 0x%08x\n", cmd->opcode, cmd->resp[0]);

-		break;

-	}

-	case 2:

-	{

-		data = REG_MSC_RES(host->pdev_id);

-		v = data & 0xffff;

-		for (i = 0; i < 4; i++) {

-			data = REG_MSC_RES(host->pdev_id);

-			w1 = data & 0xffff;

-			data = REG_MSC_RES(host->pdev_id);

-			w2 = data & 0xffff;

-			cmd->resp[i] = v << 24 | w1 << 8 | w2 >> 8;

-			v = w2;

-		}

-		break;

-	}

-	case 0:

-		break;

-	}

-	if (stat & MSC_STAT_TIME_OUT_RES) {

-		/* :-( our customer do not want to see SO MANY timeouts :-(

-		   so only CMD5 can return timeout error!!! */

-

-		/*

-		 * Note: we can not return timeout when CMD SD_SWITCH or MMC_SWITCH

-		 * because we declared that out host->caps support MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA and MMC_CAP_MMC_HIGHSPEED

-		 * if in the future some error occured because of this, we must add some code to remember

-		 * which mode(SDIO/SD/MMC)  the MSC is in

-		 */

-		switch(cmd->opcode) {

-		case SD_IO_SEND_OP_COND:

-			//case SD_SWITCH:

-			//case MMC_SWITCH:

-		case SD_SEND_IF_COND:

-		case MMC_APP_CMD:

-			cmd->error = -ETIMEDOUT;

-			break;

-		default:

-			printk("jz-msc%d: ignored MSC_STAT_TIME_OUT_RES, cmd=%d\n", host->pdev_id, cmd->opcode);

-		}

-	} else if (stat & MSC_STAT_CRC_RES_ERR && cmd->flags & MMC_RSP_CRC) {

-		printk("jz-msc%d: MSC_STAT_CRC, cmd=%d\n", host->pdev_id, cmd->opcode);

-		if (cmd->opcode == MMC_ALL_SEND_CID ||

-		    cmd->opcode == MMC_SEND_CSD ||

-		    cmd->opcode == MMC_SEND_CID) {

-			/* a bogus CRC error can appear if the msb of

-			   the 15 byte response is a one */

-			if ((cmd->resp[0] & 0x80000000) == 0)

-				cmd->error = -EILSEQ;

-		}

-	}

-

-	TRACE_CMD_RES();

-

-	if (host->curr.data && cmd->error == 0){

-		jz_mmc_enable_irq(host, MSC_IMASK_DATA_TRAN_DONE);

-	} else {

-		jz_mmc_finish_request(host, host->curr.mrq);

-	}

-

-	return 1;

-}

-

-#ifdef USE_DMA

-void jz_mmc_data_start(struct jz_mmc_host *host)

-{

-	struct mmc_data *data = host->curr.data;

-	unsigned int nob = data->blocks;

-	unsigned int block_size = data->blksz;

-	int channel;

-	int mode;

-#ifndef USE_DMA_DESC

-	int i;

-	int j = 0;

-	int ds = 4;

-	struct scatterlist *sgentry;

-#endif

-

-

-	if (data->flags & MMC_DATA_WRITE) {

-		channel = host->dma.txchannel;

-		mode = DMA_MODE_WRITE;

-		host->dma.dir = DMA_TO_DEVICE;

-	} else {

-		channel = host->dma.rxchannel;

-		mode = DMA_MODE_READ;

-		host->dma.dir = DMA_FROM_DEVICE;

-	}

-

-	if (data->flags & MMC_DATA_STREAM)

-		nob = 0xffff;

-

-	REG_MSC_NOB(host->pdev_id) = nob;

-	REG_MSC_BLKLEN(host->pdev_id) = block_size;

-

-	host->dma.len =

-	    dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,

-		       host->dma.dir);

-

-#ifdef USE_DMA_DESC

-	jz_mmc_start_scatter_dma(channel, host, data->sg, host->dma.len, mode);

-#ifdef DEBUG

-	start_debug_timer(host->pdev_id);

-#endif

-#else

-	j = 0;

-	for_each_sg(data->sg, sgentry, host->dma.len, i) {

-		host->sg_cpu[j].dtadr = sg_dma_address(sgentry);

-		host->sg_cpu[j].dcmd = sg_dma_len(sgentry);

-		dma_cache_wback_inv((unsigned long)CKSEG0ADDR(sg_dma_address(sgentry) + data->sg->offset),

-				    host->sg_cpu[j].dcmd);

-

-		if ((likely(host->sg_cpu[j].dcmd % 32 == 0)))

-			ds = 32; /* 32 byte */

-		else if (host->sg_cpu[j].dcmd % 16 == 0)

-			ds = 16; /* 16 byte */

-		else

-			ds = 4; /* default to 4 byte */

-

-

-		/* FIXME: bug here!!!!! wait for current dma done, then next sg */

-		jz_mmc_start_dma(channel, host->sg_cpu[j].dtadr,

-				 host->sg_cpu[j].dcmd, mode, ds);

-

-		j++;

-

-	}

-#endif

-}

-#else

-

-static void jz_mmc_receive_pio(struct jz_mmc_host *host)

-{

-	struct mmc_data *data = host->curr.data;

-	int sg_len = 0, max = 0, count = 0;

-	unsigned int *buf = 0;

-	struct scatterlist *sg;

-	unsigned int nob;

-

-	nob = data->blocks;

-

-	REG_MSC_NOB(host->pdev_id) = nob;

-	REG_MSC_BLKLEN(host->pdev_id) = data->blksz;

-

-	max = host->pio.len;

-	if (host->pio.index < host->dma.len) {

-		sg = &data->sg[host->pio.index];

-		buf = sg_virt(sg) + host->pio.offset;

-

-		/* This is the space left inside the buffer */

-		sg_len = sg_dma_len(&data->sg[host->pio.index]) - host->pio.offset;

-		/* Check to if we need less then the size of the sg_buffer */

-		if (sg_len < max) max = sg_len;

-	}

-

-	max = max / 4;

-	for(count = 0; count < max; count++) {

-		while (REG_MSC_STAT(host->pdev_id) & MSC_STAT_DATA_FIFO_EMPTY)

-			;

-		*buf++ = REG_MSC_RXFIFO(host->pdev_id);

-	}

-	host->pio.len -= count;

-	host->pio.offset += count;

-

-	if (sg_len && count == sg_len) {

-		host->pio.index++;

-		host->pio.offset = 0;

-	}

-}

-

-static void jz_mmc_send_pio(struct jz_mmc_host *host)

-{

-	int sg_len, max, count = 0;

-	unsigned int *wbuf = 0;

-	unsigned int nob;

-	struct mmc_data *data = host->curr.data;

-	struct scatterlist *sg;

-

-	nob = data->blocks;

-

-	REG_MSC_NOB(host->pdev_id) = nob;

-	REG_MSC_BLKLEN(host->pdev_id) = data->blksz;

-

-	/* This is the pointer to the data buffer */

-	sg = &data->sg[host->pio.index];

-	wbuf = sg_virt(sg) + host->pio.offset;

-

-	/* This is the space left inside the buffer */

-	sg_len = data->sg[host->pio.index].length - host->pio.offset;

-

-	/* Check to if we need less then the size of the sg_buffer */

-	max = (sg_len > host->pio.len) ? host->pio.len : sg_len;

-	max = max / 4;

-	for(count = 0; count < max; count++) {

-		while (REG_MSC_STAT(host->pdev_id) & MSC_STAT_DATA_FIFO_FULL)

-				;

-		REG_MSC_TXFIFO(host->pdev_id) = *wbuf++;

-	}

-

-	host->pio.len -= count;

-	host->pio.offset += count;

-

-	if (count == sg_len) {

-		host->pio.index++;

-		host->pio.offset = 0;

-	}

-}

-

-#endif

-

-static void jz_mmc_execute_cmd(struct jz_mmc_host *host, struct mmc_command *cmd, unsigned int cmdat)

-{

-	u32 timeout = 0x7fffff;

-	unsigned int stat;

-	unsigned int stat_err_bits = 0;

-	u32 cmdarg = 0;

-	int err = 0;

-

-	WARN_ON(host->curr.cmd != NULL);

-	host->curr.cmd = cmd;

-

-	/* mask interrupts */

-	REG_MSC_IMASK(host->pdev_id) = 0xffff;

-

-	/* clear status */

-	REG_MSC_IREG(host->pdev_id) = 0xffff;

-

-	if (cmd->flags & MMC_RSP_BUSY)

-		cmdat |= MSC_CMDAT_BUSY;

-

-	switch (RSP_TYPE(mmc_resp_type(cmd))) {

-	case RSP_TYPE(MMC_RSP_R1):	// r1, r1b, r5, r6, r7

-		cmdat |= MSC_CMDAT_RESPONSE_R1;

-		host->curr.r_type = 1;

-		break;

-	case RSP_TYPE(MMC_RSP_R3):	// r3, r4

-		cmdat |= MSC_CMDAT_RESPONSE_R3;

-		host->curr.r_type = 1;

-		break;

-	case RSP_TYPE(MMC_RSP_R2):	// r2

-		cmdat |= MSC_CMDAT_RESPONSE_R2;

-		host->curr.r_type = 2;

-		break;

-	default:

-		break;

-	}

-

-	REG_MSC_CMD(host->pdev_id) = cmd->opcode;

-

-	cmdarg = cmd->arg;

-

-	/* Set argument */

-	if(host->plat->bus_width == 1) {

-		if (cmd->opcode == 6) {

-			/* set  1 bit sd card bus*/

-			if (cmd->arg == 2) {

-				cmdarg = 0;

-				REG_MSC_ARG(host->pdev_id) = 0;

-			}

-

-			/* set  1 bit mmc card bus*/

-			if (cmd->arg == 0x3b70101) {

-				cmdarg = 0x3b70001;

-				REG_MSC_ARG(host->pdev_id) = 0x3b70001;

-			}

-		} else

-			REG_MSC_ARG(host->pdev_id) = cmd->arg;

-	} else if(host->plat->bus_width == 8) {

-		if (cmd->opcode == 6) {

-			/* set  8 bit mmc card bus*/

-			if (cmd->arg == 0x3b70101) {

-				cmdarg = 0x3b70201;

-				REG_MSC_ARG(host->pdev_id) = 0x3b70201;

-			} else

-				REG_MSC_ARG(host->pdev_id) = cmd->arg;

-		} else

-			REG_MSC_ARG(host->pdev_id) = cmd->arg;

-	} else

-		REG_MSC_ARG(host->pdev_id) = cmd->arg;

-

-	/* Set command */

-#ifdef USE_DMA_BUSRT_64

-	cmdat |= MSC_CMDAT_RTRG_EQUALT_16;

-#endif

-	REG_MSC_CMDAT(host->pdev_id) = cmdat;

-

-	TRACE_CMD_REQ();

-

-	/* Send command */

-	REG_MSC_STRPCL(host->pdev_id) = MSC_STRPCL_START_OP;

-

-	while (timeout-- && !((stat = REG_MSC_STAT(host->pdev_id)) & MSC_STAT_END_CMD_RES))

-		;

-

-	stat_err_bits = stat & MSC_STAT_ERR_BITS;

-

-	if (timeout == 0)

-		printk("wait END_CMD_RES failed!!!\n");

-

-

-	REG_MSC_IREG(host->pdev_id) = MSC_IREG_END_CMD_RES;	/* clear irq flag */

-

-	if (cmd->flags & MMC_RSP_BUSY) {

-		timeout = 0x7fffff;

-		while (timeout-- && !(REG_MSC_IREG(host->pdev_id) & MSC_IREG_PRG_DONE))

-			;

-		REG_MSC_IREG(host->pdev_id) = MSC_IREG_PRG_DONE;	/* clear status */

-	} else {

-		switch(cmd->opcode) { /* R1b cmds need wait PROG_DONE */

-		case 7:

-		case 12:

-		case 28:

-		case 29:

-		case 38:

-			timeout = 0x7fffff;

-			while (timeout-- && !(REG_MSC_IREG(host->pdev_id) & MSC_IREG_PRG_DONE))

-				;

-			REG_MSC_IREG(host->pdev_id) = MSC_IREG_PRG_DONE;	/* clear status */

-			break;

-		default:

-			/* do nothing */

-			break;

-		}

-	}

-

-	if (SD_IO_SEND_OP_COND == cmd->opcode) {

-		if(host->plat->support_sdio == 0) {

-			cmd->error = -ETIMEDOUT;

-			jz_mmc_finish_request(host, host->curr.mrq);

-			return;

-		}

-	}

-

-	TRACE_DATA_REQ();

-#ifndef USE_DMA

-	if (host->curr.data) {

-		if (host->curr.data->flags & MMC_DATA_READ)

-			jz_mmc_receive_pio(host);

-		else

-			jz_mmc_send_pio(host);

-	}

-#endif

-	jz_mmc_cmd_done(host, stat);

-

-#ifdef USE_DMA

-	if (host->curr.data) {

-		if(host->curr.data->flags & MMC_DATA_WRITE)

-			jz_mmc_data_start(host);

-

-		/* in case that the controller never raise interrupt(May be there are some problem, isn't it?), we must finish the request here!!! */

-		err = wait_event_interruptible_timeout(host->msc_wait_queue, ((host->msc_ack) | host->eject), 2 * HZ);

-		if(err == -ERESTARTSYS) {

-			printk("err == -ERESTARTSYS\n");

-			host->curr.mrq->cmd->error = -ENOMEDIUM;

-			jz_mmc_finish_request(host, host->curr.mrq);

-		}

-	}

-#else

-#if 0

-	if (host->curr.data) {

-		if (host->curr.data->flags & MMC_DATA_READ)

-			jz_mmc_receive_pio(host);

-		else

-			jz_mmc_send_pio(host);

-	}

-#endif

-#endif

-

-}

-

-static int jz_mmc_data_done(struct jz_mmc_host *host)

-{

-	struct mmc_data *data = host->curr.data;

-	int stat = 0;

-	unsigned int stat_err_bits = 0;

-	u32 timeout = 0x7fffff;

-

-	if (!data)

-		return 0;

-

-#ifdef DEBUG

-	stop_debug_timer(host->pdev_id);

-#endif

-

-	stat = REG_MSC_STAT(host->pdev_id);

-	stat_err_bits = stat & MSC_STAT_ERR_BITS;

-

-	REG_MSC_IREG(host->pdev_id) = MSC_IREG_DATA_TRAN_DONE;	/* clear status */

-

-	if (host->curr.mrq && (host->curr.mrq->data->flags & MMC_DATA_WRITE)) {

-

-		while (timeout-- && !(REG_MSC_IREG(host->pdev_id) & MSC_IREG_PRG_DONE))

-			;

-		if (timeout == 0)

-			printk("PRG_DONE not done!!!\n");

-		REG_MSC_IREG(host->pdev_id) = MSC_IREG_PRG_DONE;	/* clear status */

-	}

-

-	dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma.len,

-		     host->dma.dir);

-

-	stat = REG_MSC_STAT(host->pdev_id);

-	stat |= stat_err_bits;

-

-	if (stat & MSC_STAT_TIME_OUT_READ) {

-		printk("MMC/SD/SDIO timeout, MMC_STAT 0x%x opcode = %d data flags = 0x%0x blocks = %d blksz = %d\n",

-		       stat,

-		       host->curr.mrq? host->curr.mrq->cmd->opcode : -1,

-		       data->flags,

-		       data->blocks,

-		       data->blksz);

-		data->error = -ETIMEDOUT;

-	} else if (stat & (MSC_STAT_CRC_READ_ERROR | MSC_STAT_CRC_WRITE_ERROR)) {

-		printk("jz-msc%d: MMC/SD/SDIO CRC error, MMC_STAT 0x%x, cmd=%d\n",

-		       host->pdev_id, stat,

-		       host->curr.mrq? host->curr.mrq->cmd->opcode : -1);

-		//data->error = -EILSEQ;

-	}

-	/*

-	 * There appears to be a hardware design bug here.  There seems to

-	 * be no way to find out how much data was transferred to the card.

-	 * This means that if there was an error on any block, we mark all

-	 * data blocks as being in error.

-	 */

-	if (data->error == 0)

-		data->bytes_xfered = data->blocks * data->blksz;

-	else

-		data->bytes_xfered = 0;

-

-	TRACE_DATA_DONE();

-

-	// jz_mmc_disable_irq(host, MSC_IMASK_DATA_TRAN_DONE);

-

-	host->curr.data = NULL;

-	if (host->curr.mrq->stop) {

-		jz_mmc_execute_cmd(host, host->curr.mrq->stop, 0);

-	} else {

-		jz_mmc_finish_request(host, host->curr.mrq);

-	}

-

-	return 1;

-}

-

-static void jiq_msc_irq(struct work_struct *ptr)

-{

-	struct jz_mmc_host *host = container_of(ptr, struct jz_mmc_host, msc_jiq_work);

-

-	jz_mmc_data_done(host);

-

-	host->msc_ack = 1;

-	wake_up_interruptible(&host->msc_wait_queue);

-}

-

-

-static irqreturn_t jz_mmc_irq(int irq, void *devid)

-{

-	struct jz_mmc_host *host = devid;

-	unsigned int ireg = 0;

-	int handled = 0;

-

-	ireg = REG_MSC_IREG(host->pdev_id);

-

-	if (ireg) {

-		if (ireg & MSC_IREG_DATA_TRAN_DONE) {

-			jz_mmc_disable_irq(host, MSC_IMASK_DATA_TRAN_DONE);

-			//schedule_work( &(((struct jz_mmc_host *) devid)->msc_jiq_work) );

-			queue_work(host->msc_work_queue, &(((struct jz_mmc_host *) devid)->msc_jiq_work));

-			handled = 1;

-		}

-	}

-

-	return IRQ_RETVAL(handled);

-}

-

-static int jz_mmc_msc_init(struct jz_mmc_host *host)

-{

-	int ret = 0;

-

-	jz_mmc_reset(host);

-	// __msc_start_clk(host->pdev_id);

-	REG_MSC_LPM(host->pdev_id) = 0x1;	// Low power mode

-	REG_MSC_RDTO(host->pdev_id) = 0xffffffff;

-

-	host->msc_ack = 0;

-	init_waitqueue_head(&host->msc_wait_queue);

-

-	msc_irq_mask_all(host->pdev_id);

-

-	ret = request_irq(host->irqres->start, jz_mmc_irq, 0, "jz-msc (msc)", host);

-	if (ret) {

-		printk(KERN_ERR "MMC/SD: can't request MMC/SD IRQ\n");

-		return ret;

-	}

-

-	host->msc_work_queue = create_rt_workqueue("mscworkqueue");

-

-	INIT_WORK(&host->msc_jiq_work, jiq_msc_irq);

-

-	return 0;

-}

-

-static void jz_mmc_msc_deinit(struct jz_mmc_host *host)

-{

-	free_irq(host->irqres->start, &host);

-	destroy_workqueue(host->msc_work_queue);

-}

-

-int jz_mmc_msc_register(struct jz_mmc_msc *msc)

-{

-	if(msc == NULL)

-		return -ENOMEM;

-

-	msc->init = jz_mmc_msc_init;

-	msc->deinit = jz_mmc_msc_deinit;

-	msc->set_clock = jz_mmc_set_clock;

-	msc->execute_cmd = jz_mmc_execute_cmd;

-

-	return 0;

-}

diff --git a/arch/mips/include/asm/jzmmc/jz_mmc_controller.h b/drivers/mmc/host/jzmmc/include/jz_mmc_controller.h
index b45d9286633..19eba315dd1 100644
--- a/arch/mips/include/asm/jzmmc/jz_mmc_controller.h
+++ b/drivers/mmc/host/jzmmc/include/jz_mmc_controller.h
@@ -1,42 +1,42 @@
-/*

- *  drivers/mmc/host/jz_mmc_controller.h

- *

- * This program is free software; you can redistribute it and/or modify

- * it under the terms of the GNU General Public License version 2 as

- * published by the Free Software Foundation.

- *

- * Copyright (c) Ingenic Semiconductor Co., Ltd.

- */

-

-#ifndef __JZ_MMC_CONTROLLER_H__

-#define __JZ_MMC_CONTROLLER_H__

-

-#include <asm/jzmmc/jz_mmc_host.h>

-#include <asm/jzmmc/jz_mmc_gpio.h>

-#include <asm/jzmmc/jz_mmc_msc.h>

-#include <asm/jzmmc/jz_mmc_dma.h>

-

-struct jz_mmc_functions {

-	void (*deinit) (struct jz_mmc_host *, struct platform_device *);

-	int (*transmit_data) (struct jz_mmc_host *);

-	void (*execute_cmd) (struct jz_mmc_host *, struct mmc_command *, unsigned int);

-	void (*set_clock) (struct jz_mmc_host *, int);

-	void (*msc_deinit) (struct jz_mmc_host *);

-	void (*gpio_deinit) (struct jz_mmc_host *, struct platform_device *);

-	void (*dma_deinit) (struct jz_mmc_host *);

-};

-

-struct jz_mmc_controller {

-

-	struct jz_mmc_msc msc;		// msc

-	struct jz_mmc_dma dma;		// dma

-	struct jz_mmc_gpio gpio;	// gpio

-

-	int (*init) (struct jz_mmc_controller *, struct jz_mmc_host *,

-				struct platform_device *);

-	struct jz_mmc_functions functions;

-};

-

-int controller_register(struct jz_mmc_controller *, struct jz_mmc_host *);

-

-#endif /* __JZ_MMC_CONTROLLER_H__ */

+/*
+ *  drivers/mmc/host/jz_mmc_controller.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Copyright (c) Ingenic Semiconductor Co., Ltd.
+ */
+
+#ifndef __JZ_MMC_CONTROLLER_H__
+#define __JZ_MMC_CONTROLLER_H__
+
+#include "jz_mmc_host.h"
+#include "jz_mmc_gpio.h"
+#include "jz_mmc_msc.h"
+#include "jz_mmc_dma.h"
+
+struct jz_mmc_functions {
+	void (*deinit) (struct jz_mmc_host *, struct platform_device *);
+	int (*transmit_data) (struct jz_mmc_host *);
+	void (*execute_cmd) (struct jz_mmc_host *);
+	void (*set_clock) (struct jz_mmc_host *, int);
+	void (*msc_deinit) (struct jz_mmc_host *);
+	void (*gpio_deinit) (struct jz_mmc_host *, struct platform_device *);
+	void (*dma_deinit) (struct jz_mmc_host *);
+};
+
+struct jz_mmc_controller {
+
+	struct jz_mmc_msc msc;		// msc
+	struct jz_mmc_dma dma;		// dma
+	struct jz_mmc_gpio gpio;	// gpio
+
+	int (*init) (struct jz_mmc_controller *, struct jz_mmc_host *,
+				struct platform_device *);
+	struct jz_mmc_functions functions;
+};
+
+int controller_register(struct jz_mmc_controller *, struct jz_mmc_host *);
+
+#endif /* __JZ_MMC_CONTROLLER_H__ */
diff --git a/arch/mips/include/asm/jzmmc/jz_mmc_dma.h b/drivers/mmc/host/jzmmc/include/jz_mmc_dma.h
index a40025d3145..431d94e7785 100644
--- a/arch/mips/include/asm/jzmmc/jz_mmc_dma.h
+++ b/drivers/mmc/host/jzmmc/include/jz_mmc_dma.h
@@ -1,29 +1,31 @@
-/*

- *  linux/drivers/mmc/host/jz_mmc/dma/jz_mmc_dma.h

- *

- * This program is free software; you can redistribute it and/or modify

- * it under the terms of the GNU General Public License version 2 as

- * published by the Free Software Foundation.

- *

- * Copyright (c) Ingenic Semiconductor Co., Ltd.

- */

-

-#ifndef __JZ_MMC_DMA_H__

-#define __JZ_MMC_DMA_H__

-

-#include <asm/jzmmc/jz_mmc_host.h>

-

-struct jz_mmc_dma {

-

-	int (*init) (struct jz_mmc_host *);

-	void (*deinit) (struct jz_mmc_host *);

-};

-

-int jz_mmc_dma_register(struct jz_mmc_dma *dma);

-

-void jz_mmc_start_dma(int chan, unsigned long phyaddr, int count, int mode, int ds);

-

-void jz_mmc_start_scatter_dma(int chan, struct jz_mmc_host *host,

-			      struct scatterlist *sg, unsigned int sg_len, int mode);

-

-#endif /* __JZ_MMC_DMA_H__ */

+/*
+ *  linux/drivers/mmc/host/jz_mmc/dma/jz_mmc_dma.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Copyright (c) Ingenic Semiconductor Co., Ltd.
+ */
+
+#ifndef __JZ_MMC_DMA_H__
+#define __JZ_MMC_DMA_H__
+
+#include "jz_mmc_host.h"
+
+struct jz_mmc_dma {
+
+	int (*init) (struct jz_mmc_host *);
+	void (*deinit) (struct jz_mmc_host *);
+};
+
+int jz_mmc_dma_register(struct jz_mmc_dma *dma);
+
+void jz_mmc_start_dma(struct jz_mmc_host *host);
+void jz_mmc_stop_dma(struct jz_mmc_host *host);
+
+void jz_mmc_start_normal_dma(struct jz_mmc_host *host, unsigned long phyaddr, int count, int mode, int ds);
+void jz_mmc_start_scatter_dma(int chan, struct jz_mmc_host *host,
+			      struct scatterlist *sg, unsigned int sg_len, int mode);
+
+#endif /* __JZ_MMC_DMA_H__ */
diff --git a/arch/mips/include/asm/jzmmc/jz_mmc_gpio.h b/drivers/mmc/host/jzmmc/include/jz_mmc_gpio.h
index 2814a58a080..faeefd5175c 100644
--- a/arch/mips/include/asm/jzmmc/jz_mmc_gpio.h
+++ b/drivers/mmc/host/jzmmc/include/jz_mmc_gpio.h
@@ -1,33 +1,33 @@
-/*

- *  linux/drivers/mmc/host/jz_mmc/gpio/jz_mmc_gpio.h

- *

- * This program is free software; you can redistribute it and/or modify

- * it under the terms of the GNU General Public License version 2 as

- * published by the Free Software Foundation.

- *

- * Copyright (c) Ingenic Semiconductor Co., Ltd.

- */

-

-#ifndef __JZ_MMC_GPIO_H__

-#define __JZ_MMC_GPIO_H__

-

-#include <asm/jzmmc/jz_mmc_host.h>

-#include <linux/platform_device.h>

-

-#ifndef __JZ_MMC_HOST_H__

-#error "!!!!!!!!!!!!!"

-#endif

-

-//struct jz_mmc_host test;

-//int t = test.dma.len;

-

-struct jz_mmc_gpio {

-

-	int (*init) (struct jz_mmc_host *, struct platform_device *);

-	void (*deinit) (struct jz_mmc_host *, struct platform_device *);

-};

-

-int jz_mmc_gpio_register(struct jz_mmc_gpio *);

-

-#endif /* __JZ_MMC_GPIO_H__ */

-

+/*
+ *  linux/drivers/mmc/host/jz_mmc/gpio/jz_mmc_gpio.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Copyright (c) Ingenic Semiconductor Co., Ltd.
+ */
+
+#ifndef __JZ_MMC_GPIO_H__
+#define __JZ_MMC_GPIO_H__
+
+#include "jz_mmc_host.h"
+#include <linux/platform_device.h>
+
+#ifndef __JZ_MMC_HOST_H__
+#error "!!!!!!!!!!!!!"
+#endif
+
+//struct jz_mmc_host test;
+//int t = test.dma.len;
+
+struct jz_mmc_gpio {
+
+	int (*init) (struct jz_mmc_host *, struct platform_device *);
+	void (*deinit) (struct jz_mmc_host *, struct platform_device *);
+};
+
+int jz_mmc_gpio_register(struct jz_mmc_gpio *);
+
+#endif /* __JZ_MMC_GPIO_H__ */
+
diff --git a/drivers/mmc/host/jzmmc/include/jz_mmc_host.h b/drivers/mmc/host/jzmmc/include/jz_mmc_host.h
new file mode 100644
index 00000000000..7cc500ad003
--- /dev/null
+++ b/drivers/mmc/host/jzmmc/include/jz_mmc_host.h
@@ -0,0 +1,107 @@
+/*
+ *  linux/drivers/mmc/host/jz_mmc/jz_mmc_host.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Copyright (c) Ingenic Semiconductor Co., Ltd.
+ */
+
+#ifndef __JZ_MMC_HOST_H__
+#define __JZ_MMC_HOST_H__
+
+#include <linux/semaphore.h>
+#include <asm/jzsoc.h>
+#include <linux/device.h>
+
+#define JZ_MSC_USE_DMA 1
+//#define JZ_MSC_USE_PIO 1
+
+#define USE_DMA_DESC
+//#define USE_DMA_UNCACHE
+//#define MSC_DEBUG_DMA
+
+#ifdef CONFIG_SOC_JZ4760
+
+#define JZ_MSC_DMA_DESC jz_dma_desc_8word
+#define USE_DMA_BUSRT_64
+
+#else
+
+#define JZ_MSC_DMA_DESC jz_dma_desc_8word
+
+#endif
+
+#define MMC_CLOCK_SLOW    400000      /* 400 kHz for initial setup */
+#define MMC_CLOCK_FAST  20000000      /* 20 MHz for maximum for normal operation */
+#define SD_CLOCK_FAST   24000000      /* 24 MHz for SD Cards */
+#define SD_CLOCK_HIGH   24000000      /* 24 MHz for SD Cards */
+#define MMC_NO_ERROR  0
+
+#define NR_SG	1
+
+#define MSC_1BIT_BUS 0
+#define MSC_4BIT_BUS 1
+#define MSC_8BIT_BUS 2
+
+#define SZ_4K                           0x00001000
+
+struct jz_mmc_host {
+	struct mmc_host *mmc;
+	struct semaphore mutex;
+
+	/* host resources */
+	//void __iomem *base;
+	unsigned int pdev_id;
+	int irq;
+	int dma_id;
+	struct jz_mmc_platform_data *plat;
+
+	/* mmc request related */
+	unsigned int cmdat;
+	struct mmc_request *curr_mrq;
+	int curr_res_type;
+
+	/* data transter related */
+	struct {
+		int len;
+		int dir;
+		int channel;
+	} dma;
+#ifdef USE_DMA_DESC
+#ifdef MSC_DEBUG_DMA
+	int num_desc;
+	int last_direction;
+#endif
+	JZ_MSC_DMA_DESC *dma_desc;
+#endif
+	wait_queue_head_t data_wait_queue;
+	volatile int data_ack;
+	volatile int data_err;
+
+#ifdef JZ_MSC_USE_PIO
+	volatile int transfer_end;
+#endif
+#if 0
+	wait_queue_head_t status_check_queue;
+	struct timer_list status_check_timer;
+	u32 status;
+	u32 st_mask;
+	int st_check_timeout;
+	int st_check_interval;
+	int en_usr_intr;
+#endif
+
+	/* card detect related */
+	volatile unsigned int eject;
+	volatile unsigned int oldstat;
+	struct delayed_work gpio_jiq_work;
+	atomic_t detect_refcnt;
+	struct timer_list timer;
+	volatile int sleeping;
+};
+
+void jz_mmc_finish_request(struct jz_mmc_host *host, struct mmc_request *mrq);
+
+#endif /* __JZ_MMC_HOST_H__ */
diff --git a/arch/mips/include/asm/jzmmc/jz_mmc_msc.h b/drivers/mmc/host/jzmmc/include/jz_mmc_msc.h
index 69db5ea8adf..4911e090dd4 100644
--- a/arch/mips/include/asm/jzmmc/jz_mmc_msc.h
+++ b/drivers/mmc/host/jzmmc/include/jz_mmc_msc.h
@@ -1,33 +1,32 @@
-/*

- *  linux/drivers/mmc/host/jz_mmc/msc/jz_mmc_msc.c

- *

- * This program is free software; you can redistribute it and/or modify

- * it under the terms of the GNU General Public License version 2 as

- * published by the Free Software Foundation.

- *

- * Copyright (c) Ingenic Semiconductor Co., Ltd.

- */

-

-#ifndef __JZ_MMC_MSC_H__

-#define __JZ_MMC_MSC_H__

-

-#include <asm/jzmmc/jz_mmc_host.h>

-#include <asm/jzmmc/jz_mmc_dma.h>

-

-#define RSP_TYPE(x)	((x) & ~(MMC_RSP_BUSY|MMC_RSP_OPCODE))

-

-struct jz_mmc_msc {

-

-	int (*init) (struct jz_mmc_host *);

-	void (*deinit) (struct jz_mmc_host *);

-	void (*set_clock) (struct jz_mmc_host *, int);

-	void (*execute_cmd) (struct jz_mmc_host *, struct mmc_command *, unsigned int);

-};

-

-int jz_mmc_msc_register(struct jz_mmc_msc *msc);

-

-#ifdef USE_DMA

-void jz_mmc_data_start(struct jz_mmc_host *host);

-#endif

-

-#endif /* __JZ_MMC_MSC_H__ */

+/*
+ *  linux/drivers/mmc/host/jz_mmc/msc/jz_mmc_msc.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Copyright (c) Ingenic Semiconductor Co., Ltd.
+ */
+
+#ifndef __JZ_MMC_MSC_H__
+#define __JZ_MMC_MSC_H__
+
+#include "jz_mmc_host.h"
+#include "jz_mmc_dma.h"
+
+#define RSP_TYPE(x)	((x) & ~(MMC_RSP_BUSY|MMC_RSP_OPCODE))
+
+struct jz_mmc_msc {
+
+	int (*init) (struct jz_mmc_host *);
+	void (*deinit) (struct jz_mmc_host *);
+	void (*set_clock) (struct jz_mmc_host *, int);
+	void (*execute_cmd) (struct jz_mmc_host *);
+};
+
+int jz_mmc_msc_register(struct jz_mmc_msc *msc);
+
+void jz_mmc_data_start(struct jz_mmc_host *host);
+
+void jz_mmc_reset(struct jz_mmc_host *host);
+#endif /* __JZ_MMC_MSC_H__ */
diff --git a/drivers/mmc/host/jzmmc/include/jz_mmc_pio.h b/drivers/mmc/host/jzmmc/include/jz_mmc_pio.h
new file mode 100644
index 00000000000..ee8a3029608
--- /dev/null
+++ b/drivers/mmc/host/jzmmc/include/jz_mmc_pio.h
@@ -0,0 +1,7 @@
+#ifndef __JZ_MMC_PIO_H__
+#define __JZ_MMC_PIO_H__
+
+extern void jz_mmc_stop_pio(struct jz_mmc_host *host);
+extern void jz_mmc_start_pio(struct jz_mmc_host *host);
+
+#endif /* __JZ_MMC_PIO_H__ */
diff --git a/drivers/mmc/host/jzmmc/controller/jz_mmc_controller.c b/drivers/mmc/host/jzmmc/jz_mmc_controller.c
index cb79f8954ee..c43d43a01ac 100644
--- a/drivers/mmc/host/jzmmc/controller/jz_mmc_controller.c
+++ b/drivers/mmc/host/jzmmc/jz_mmc_controller.c
@@ -1,126 +1,91 @@
-/*

- *  linux/drivers/mmc/host/jz_mmc/controller/jz_mmc_controller.c

- *

- * This program is free software; you can redistribute it and/or modify

- * it under the terms of the GNU General Public License version 2 as

- * published by the Free Software Foundation.

- *

- * Copyright (c) Ingenic Semiconductor Co., Ltd.

- */

-

-#include <linux/dma-mapping.h>

-#include <linux/mmc/mmc.h>

-#include <linux/mmc/sdio.h>

-#include <linux/scatterlist.h>

-

-#include <asm/jzsoc.h>

-#include <asm/jzmmc/jz_mmc_msc.h>

-#include <asm/jzmmc/jz_mmc_controller.h>

-

-

-#ifdef USE_DMA

-

-static int data_transmit_dma(struct jz_mmc_host *host)

-{

-	jz_mmc_data_start(host);

-

-	return 0;

-}

-

-#else

-

-static int jz_mmc_prepare_data(struct jz_mmc_host *host)

-{

-	struct mmc_data *data = host->curr.data;

-	int datalen = data->blocks * data->blksz;

-

-	host->dma.dir = DMA_BIDIRECTIONAL;

-	host->dma.len = dma_map_sg(mmc_dev(host->mmc), data->sg,

-				   data->sg_len, host->dma.dir);

-

-	if (host->dma.len == 0)

-		return -ETIMEDOUT;

-

-	host->pio.index = 0;

-	host->pio.offset = 0;

-	host->pio.len = datalen;

-	return 0;

-}

-

-static int data_transmit_cpu(struct jz_mmc_host *host)

-{

-	jz_mmc_prepare_data(host);

-

-	return 0;

-}

-#endif

-

-static int controller_init(struct jz_mmc_controller *controller, struct jz_mmc_host *host,

-				struct platform_device *pdev)

-{

-	int ret = 0;

-

-	ret = controller->msc.init(host);

-	if(ret) {

-		return ret;

-	}

-

-	ret = controller->gpio.init(host, pdev);

-	if(ret) {

-		goto gpio_failed;

-	}

-

-	ret = controller->dma.init(host);

-	if(ret) {

-		goto dma_failed;

-	}

-

-	return 0;

-

-dma_failed:

-	controller->gpio.deinit(host, pdev);

-gpio_failed:

-	controller->msc.deinit(host);

-	return ret;

-}

-

-static void controller_deinit(struct jz_mmc_host *host, struct platform_device *pdev)

-{

-	struct jz_mmc_functions *functions = host->plat->driver_data;

-

-	functions->gpio_deinit(host, pdev);

-	functions->msc_deinit(host);

-	functions->dma_deinit(host);

-}

-

-int controller_register(struct jz_mmc_controller *controller, struct jz_mmc_host *host)

-{

-	if(controller == NULL)

-		return -ENOMEM;

-

-	jz_mmc_gpio_register(&(controller->gpio));

-	jz_mmc_msc_register(&(controller->msc));

-	jz_mmc_dma_register(&(controller->dma));

-

-	controller->init = controller_init;

-	controller->functions.deinit = controller_deinit;

-#ifdef USE_DMA

-	controller->functions.transmit_data = data_transmit_dma;

-#else

-	controller->functions.transmit_data = data_transmit_cpu;

-#endif

-

-	controller->functions.execute_cmd = controller->msc.execute_cmd;

-	controller->functions.set_clock = controller->msc.set_clock;

-	controller->functions.msc_deinit = controller->msc.deinit;

-	controller->functions.gpio_deinit = controller->gpio.deinit;

-	controller->functions.dma_deinit = controller->dma.deinit;

-

-	host->plat->driver_data = &(controller->functions);

-

-	// struct jz_mmc_functions *functions = host->plat->driver_data;

-

-//	printk("%s: host->plat->driver_data->set_clock = %x\n", __FUNCTION__, functions->set_clock);

-

-	return 0;

-}

+/*
+ *  linux/drivers/mmc/host/jz_mmc/controller/jz_mmc_controller.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Copyright (c) Ingenic Semiconductor Co., Ltd.
+ */
+
+#include <linux/dma-mapping.h>
+#include <linux/mmc/mmc.h>
+#include <linux/mmc/sdio.h>
+#include <linux/scatterlist.h>
+
+#include <asm/jzsoc.h>
+#include "include/jz_mmc_msc.h"
+#include "include/jz_mmc_controller.h"
+
+
+static int data_transmit_dma(struct jz_mmc_host *host)
+{
+	jz_mmc_data_start(host);
+
+	return 0;
+}
+
+static int controller_init(struct jz_mmc_controller *controller, struct jz_mmc_host *host,
+				struct platform_device *pdev)
+{
+	int ret = 0;
+
+	ret = controller->msc.init(host);
+	if(ret) {
+		return ret;
+	}
+
+	ret = controller->gpio.init(host, pdev);
+	if(ret) {
+		goto gpio_failed;
+	}
+
+	ret = controller->dma.init(host);
+	if(ret) {
+		goto dma_failed;
+	}
+
+	return 0;
+
+dma_failed:
+	controller->gpio.deinit(host, pdev);
+gpio_failed:
+	controller->msc.deinit(host);
+	return ret;
+}
+
+static void controller_deinit(struct jz_mmc_host *host, struct platform_device *pdev)
+{
+	struct jz_mmc_functions *functions = host->plat->driver_data;
+
+	functions->gpio_deinit(host, pdev);
+	functions->msc_deinit(host);
+	functions->dma_deinit(host);
+}
+
+int controller_register(struct jz_mmc_controller *controller, struct jz_mmc_host *host)
+{
+	if(controller == NULL)
+		return -ENOMEM;
+
+	jz_mmc_gpio_register(&(controller->gpio));
+	jz_mmc_msc_register(&(controller->msc));
+	jz_mmc_dma_register(&(controller->dma));
+
+	controller->init = controller_init;
+	controller->functions.deinit = controller_deinit;
+	controller->functions.transmit_data = data_transmit_dma;
+	controller->functions.execute_cmd = controller->msc.execute_cmd;
+	controller->functions.set_clock = controller->msc.set_clock;
+	controller->functions.msc_deinit = controller->msc.deinit;
+	controller->functions.gpio_deinit = controller->gpio.deinit;
+	controller->functions.dma_deinit = controller->dma.deinit;
+
+	host->plat->driver_data = &(controller->functions);
+
+	// struct jz_mmc_functions *functions = host->plat->driver_data;
+
+//	printk("%s: host->plat->driver_data->set_clock = %x\n", __FUNCTION__, functions->set_clock);
+
+	return 0;
+}
diff --git a/drivers/mmc/host/jzmmc/jz_mmc_dma.c b/drivers/mmc/host/jzmmc/jz_mmc_dma.c
new file mode 100644
index 00000000000..853023ab4dd
--- /dev/null
+++ b/drivers/mmc/host/jzmmc/jz_mmc_dma.c
@@ -0,0 +1,548 @@
+/*
+ *  linux/drivers/mmc/host/jz_mmc/dma/jz_mmc_dma.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Copyright (c) Ingenic Semiconductor Co., Ltd.
+ */
+
+
+#include <linux/dma-mapping.h>
+#include <linux/scatterlist.h>
+#include <linux/mmc/core.h>
+#include <linux/mmc/host.h>
+#include <asm/jzsoc.h>
+#include "include/jz_mmc_dma.h"
+#include "include/jz_mmc_host.h"
+
+void jz_mmc_stop_dma(struct jz_mmc_host *host)
+{
+	u32 old_counter = REG_DMAC_DTCR(host->dma.channel);
+	u32 cur_counter;
+
+	//WARN(1, "mmc%d called %s\n", host->pdev_id, __FUNCTION__);
+	/* wait for the counter not change */
+	while (1) {		     /* wait forever, even when the card is removed */
+		schedule_timeout(3); /* 30ms */
+		cur_counter = REG_DMAC_DTCR(host->dma.channel);
+		if (cur_counter == old_counter)
+			break;
+		old_counter = cur_counter;
+	}
+
+	// Stop all
+	REG_DMAC_DCCSR(host->dma.channel) = 0;
+
+	// Clear all
+	REG_DMAC_DCMD(host->dma.channel) = 0;
+	REG_DMAC_DSAR(host->dma.channel) = 0;
+	REG_DMAC_DTAR(host->dma.channel) = 0;
+	REG_DMAC_DTCR(host->dma.channel) = 0;
+	REG_DMAC_DRSR(host->dma.channel) = 0;
+	REG_DMAC_DDA(host->dma.channel) = 0;
+}
+
+static inline int best_burst_size(unsigned int dma_len) {
+#ifdef USE_DMA_BUSRT_64
+	if (dma_len % 64 == 0)
+		return 64;
+#endif
+
+	if (dma_len % 32 == 0)
+		return 32;
+
+	if (dma_len % 16 == 0)
+		return 16;
+
+#ifdef USE_DMA_BUSRT_64
+	if (dma_len > 64)
+		return 64;
+#endif
+
+	if (dma_len > 32)
+		return 32;
+
+	if (dma_len > 16)
+		return 16;
+
+	return 4;
+}
+
+#ifndef DMAC_DRSR_RS_MSC2OUT
+#define DMAC_DRSR_RS_MSC2OUT 0
+#endif
+
+#ifndef DMAC_DRSR_RS_MSC2IN
+#define DMAC_DRSR_RS_MSC2IN 0
+#endif
+
+#define MSC_SET_OUT_REQ_SRC(ctrler_id, dst)				\
+	do {								\
+		switch((ctrler_id)) {					\
+		case 0:							\
+			(dst) = DMAC_DRSR_RS_MSC0OUT;			\
+			break;						\
+		case 1:							\
+			(dst) = DMAC_DRSR_RS_MSC1OUT;			\
+			break;						\
+		case 2:							\
+			(dst) = DMAC_DRSR_RS_MSC2OUT;			\
+			break;						\
+		default:						\
+			BUG();						\
+		}							\
+	} while(0)
+
+
+#define MSC_SET_IN_REQ_SRC(ctrler_id, dst)				\
+	do {								\
+		switch((ctrler_id)) {					\
+		case 0:							\
+			(dst) = DMAC_DRSR_RS_MSC0IN;			\
+			break;						\
+		case 1:							\
+			(dst) = DMAC_DRSR_RS_MSC1IN;			\
+			break;						\
+		case 2:							\
+			(dst) = DMAC_DRSR_RS_MSC2IN;			\
+			break;						\
+		default:						\
+			BUG();						\
+		}							\
+	} while (0)
+
+#ifdef USE_DMA_DESC
+static void sg_to_desc(struct scatterlist *sgentry, JZ_MSC_DMA_DESC *first_desc,
+		       int *desc_pos /* IN OUT */, int mode, int ctrl_id,
+		       struct jz_mmc_host *host) {
+	JZ_MSC_DMA_DESC *desc = NULL;
+	int pos = *desc_pos;
+	unsigned int ds = 32; /* ehh, 32byte is the best */
+	unsigned int next;
+	dma_addr_t dma_addr;
+	unsigned int dma_len;
+	unsigned int head_unalign_size = 0; /* ds = 4byte */
+	unsigned int aligned_size = 0;
+	unsigned int tail_unalign_size = 0; /* ds = 4byte */
+	dma_addr_t best_dma_addr = 0;
+	dma_addr_t last_best_dma_addr = 0;
+	dma_addr_t dma_desc_phys_addr = CPHYSADDR((unsigned long)first_desc);
+
+	dma_addr = sg_dma_address(sgentry);
+	dma_len = sg_dma_len(sgentry);
+
+	BUG_ON(dma_addr % 4);
+	BUG_ON(dma_len % 4); /* we do NOT support transfer size < 4byte */
+
+	ds = best_burst_size(dma_len);
+	best_dma_addr = (dma_addr + ds - 1) & ~(ds - 1);
+	last_best_dma_addr = (dma_addr + dma_len) & ~(ds - 1);
+
+	head_unalign_size = best_dma_addr - dma_addr;
+	tail_unalign_size = dma_addr + dma_len - last_best_dma_addr;
+	aligned_size = dma_len - head_unalign_size - tail_unalign_size;
+
+#if 0
+	/* just for test */
+	if (aligned_size > 2 * ds) {
+		aligned_size -= 2 * ds;
+		head_unalign_size += ds;
+		best_dma_addr += ds;
+
+		tail_unalign_size += ds;
+		last_best_dma_addr -= ds;
+	} else if (aligned_size > ds) {
+		aligned_size -= ds;
+		head_unalign_size += ds;
+		best_dma_addr += ds;
+	}
+#endif
+
+	BUG_ON(head_unalign_size % 4);
+	BUG_ON(tail_unalign_size % 4);
+
+	if (head_unalign_size) {
+		desc = first_desc + pos;
+		next = (dma_desc_phys_addr + (pos + 1) * (sizeof(JZ_MSC_DMA_DESC))) >> 4;
+		desc->dcmd = DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 | DMAC_DCMD_DS_32BIT | DMAC_DCMD_RDIL_IGN | DMAC_DCMD_LINK;
+		if (DMA_MODE_WRITE == mode) {
+			desc->dcmd |= DMAC_DCMD_SAI;
+			desc->dsadr = (unsigned int)dma_addr;      /* DMA source address */
+			desc->dtadr = CPHYSADDR(MSC_TXFIFO(ctrl_id));      /* DMA target address */
+			MSC_SET_OUT_REQ_SRC(ctrl_id, desc->dreqt);
+		} else {
+			desc->dcmd |= DMAC_DCMD_DAI;
+			desc->dsadr = CPHYSADDR(MSC_RXFIFO(ctrl_id));
+			desc->dtadr = (unsigned int)dma_addr;
+			MSC_SET_IN_REQ_SRC(ctrl_id, desc->dreqt);
+		}
+		desc->ddadr = (next << 24) | (head_unalign_size >> 2) ;
+
+		pos ++;
+	}
+
+	if (aligned_size) {
+		desc = first_desc + pos;
+		next = (dma_desc_phys_addr + (pos + 1) * (sizeof(JZ_MSC_DMA_DESC))) >> 4;
+
+		desc->dcmd = DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 | DMAC_DCMD_RDIL_IGN | DMAC_DCMD_LINK;
+		switch (ds) {
+#ifdef USE_DMA_BUSRT_64
+		case 64:
+			desc->dcmd |= DMAC_DCMD_DS_64BYTE;
+			break;
+#endif
+
+		case 32:
+			desc->dcmd |= DMAC_DCMD_DS_32BYTE;
+			break;
+
+		case 16:
+			desc->dcmd |= DMAC_DCMD_DS_16BYTE;
+			break;
+
+		case 4:
+			desc->dcmd |= DMAC_DCMD_DS_32BIT;
+			break;
+
+		default:
+			;
+		}
+
+		if (DMA_MODE_WRITE == mode) {
+			desc->dcmd |= DMAC_DCMD_SAI;
+			desc->dsadr = (unsigned int)best_dma_addr;      /* DMA source address */
+			desc->dtadr = CPHYSADDR(MSC_TXFIFO(ctrl_id));      /* DMA target address */
+			MSC_SET_OUT_REQ_SRC(ctrl_id, desc->dreqt);
+		} else {
+			desc->dcmd |= DMAC_DCMD_DAI;
+			desc->dsadr = CPHYSADDR(MSC_RXFIFO(ctrl_id));
+			desc->dtadr = (unsigned int)best_dma_addr;
+			MSC_SET_IN_REQ_SRC(ctrl_id, desc->dreqt);
+		}
+		desc->ddadr = (next << 24) | (aligned_size  / ds) ;
+
+		pos ++;
+	}
+
+
+	if (tail_unalign_size) {
+		desc = first_desc + pos;
+		next = (dma_desc_phys_addr + (pos + 1) * (sizeof(JZ_MSC_DMA_DESC))) >> 4;
+
+		desc->dcmd = DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 | DMAC_DCMD_DS_32BIT |   DMAC_DCMD_RDIL_IGN | DMAC_DCMD_LINK;
+		if (DMA_MODE_WRITE == mode) {
+			desc->dcmd |= DMAC_DCMD_SAI;
+			desc->dsadr = (unsigned int)last_best_dma_addr;      /* DMA source address */
+			desc->dtadr = CPHYSADDR(MSC_TXFIFO(ctrl_id));      /* DMA target address */
+			MSC_SET_OUT_REQ_SRC(ctrl_id, desc->dreqt);
+		} else {
+			desc->dcmd |= DMAC_DCMD_DAI;
+			desc->dsadr = CPHYSADDR(MSC_RXFIFO(ctrl_id));
+			desc->dtadr = (unsigned int)last_best_dma_addr;
+			MSC_SET_IN_REQ_SRC(ctrl_id, desc->dreqt);
+		}
+		desc->ddadr = (next << 24) | (tail_unalign_size >> 2) ;
+
+		pos ++;
+
+	}
+
+	*desc_pos = pos;
+}
+
+#ifdef MSC_DEBUG_DMA
+#define JZ_MSC_RECORD_DESC_NUM(num)	host->num_desc = (num)
+#else
+#define JZ_MSC_RECORD_DESC_NUM(num)	do {  } while(0)
+#endif
+
+void jz_mmc_start_scatter_dma(int chan, struct jz_mmc_host *host,
+			      struct scatterlist *sg, unsigned int sg_len, int mode) {
+	int i = 0;
+	int desc_pos = 0;
+	dma_addr_t dma_desc_phy_addr = 0;
+	struct mmc_data *data = host->curr_mrq->data;
+	struct scatterlist *sgentry;
+	JZ_MSC_DMA_DESC *desc;
+	JZ_MSC_DMA_DESC *desc_first;
+	unsigned long flags;
+	unsigned long start_time = jiffies;
+
+	while (REG_DMAC_DMACR(chan / HALF_DMA_NUM) & (DMAC_DMACR_HLT | DMAC_DMACR_AR)) {
+		if (jiffies - start_time > 10) { /* 100ms */
+			printk("DMAC unavailable! REG_DMAC_DMACR(%d) = 0x%08x\n", chan / HALF_DMA_NUM, REG_DMAC_DMACR(chan / HALF_DMA_NUM));
+			jz_mmc_stop_dma(host);
+			break;
+		}
+	}
+
+	start_time = jiffies;
+	while (REG_DMAC_DCCSR(chan) & (DMAC_DCCSR_HLT | DMAC_DCCSR_TT | DMAC_DCCSR_AR)) {
+		if (jiffies - start_time > 10) { /* 100ms */
+			printk("DMA channel %d unavailable! REG_DMAC_DCCSR(%d) = 0x%08x\n", chan, chan, REG_DMAC_DCCSR(chan));
+			jz_mmc_stop_dma(host);
+			break;
+		}
+	}
+
+	REG_DMAC_DCCSR(chan) |= DMAC_DCCSR_DES8;
+	REG_DMAC_DCCSR(chan) &= ~DMAC_DCCSR_NDES;
+
+	/* Setup request source */
+	if (DMA_MODE_WRITE == mode) {
+		MSC_SET_OUT_REQ_SRC(host->pdev_id, REG_DMAC_DRSR(chan));
+	} else {
+		MSC_SET_IN_REQ_SRC(host->pdev_id, REG_DMAC_DRSR(chan));
+	}
+
+#ifdef MSC_DEBUG_DMA
+	if (DMA_MODE_WRITE == mode) {
+		host->last_direction = 1;
+	} else {
+		host->last_direction = 0;
+	}
+#endif
+
+	desc = host->dma_desc;
+	JZ_MSC_RECORD_DESC_NUM(desc_pos);
+	desc_first = desc;
+
+	dma_desc_phy_addr  = CPHYSADDR((unsigned long)desc);
+
+	memset(desc, 0, PAGE_SIZE);
+
+	desc_pos = 0;
+	flags = claim_dma_lock();
+	for_each_sg(data->sg, sgentry, host->dma.len, i) {
+		sg_to_desc(sgentry, desc, &desc_pos, mode, host->pdev_id, host);
+	}
+
+	desc = desc + (desc_pos - 1);
+	desc->dcmd |= DMAC_DCMD_TIE;
+	desc->dcmd &= ~DMAC_DCMD_LINK;
+	desc->ddadr &= ~0xff000000;
+
+	dma_cache_wback_inv((unsigned long)desc_first, PAGE_SIZE);
+
+        /* Setup DMA descriptor address */
+	REG_DMAC_DDA(chan) = dma_desc_phy_addr;
+
+	/* DMA doorbell set -- start DMA now ... */
+	REG_DMAC_DMADBSR(chan / HALF_DMA_NUM) = 1 << (chan - (chan / HALF_DMA_NUM) * HALF_DMA_NUM) ;
+
+	/* Enable DMA */
+	REG_DMAC_DMACR(chan / HALF_DMA_NUM) |= DMAC_DMACR_DMAE;
+
+	REG_DMAC_DCCSR(chan) |= DMAC_DCCSR_EN;
+
+	release_dma_lock(flags);
+
+}
+#else
+void jz_mmc_start_normal_dma(struct jz_mmc_host *host, unsigned long phyaddr, int count, int mode, int ds)
+{
+	unsigned long flags;
+	unsigned long start_time = jiffies;
+	int chan = host->dma.channel;
+	u32 dma_cmd = 0;
+	u32 src_addr = 0;
+	u32 dst_addr = 0;
+	u32 req_src = 0;
+
+	while (REG_DMAC_DMACR(chan / HALF_DMA_NUM) & (DMAC_DMACR_HLT | DMAC_DMACR_AR)) {
+		if (jiffies - start_time > 10) { /* 100ms */
+			printk("DMAC unavailable! REG_DMAC_DMACR(%d) = 0x%08x\n", chan / HALF_DMA_NUM, REG_DMAC_DMACR(chan / HALF_DMA_NUM));
+			jz_mmc_stop_dma(host);
+			break;
+		}
+	}
+
+	start_time = jiffies;
+	while (REG_DMAC_DCCSR(chan) & (DMAC_DCCSR_HLT | DMAC_DCCSR_TT | DMAC_DCCSR_AR)) {
+		if (jiffies - start_time > 10) { /* 100ms */
+			printk("DMA channel %d unavailable! REG_DMAC_DCCSR(%d) = 0x%08x\n", chan, chan, REG_DMAC_DCCSR(chan));
+			jz_mmc_stop_dma(host);
+			break;
+		}
+	}
+
+	flags = claim_dma_lock();
+	dma_cmd = DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 | DMAC_DCMD_RDIL_IGN | DMAC_DCMD_TIE;
+	switch (ds) {
+#ifdef USE_DMA_BUSRT_64
+	case 64:
+		dma_cmd |= DMAC_DCMD_DS_64BYTE;
+		break;
+#endif
+
+	case 32:
+		dma_cmd |= DMAC_DCMD_DS_32BYTE;
+		break;
+
+	case 16:
+		dma_cmd |= DMAC_DCMD_DS_16BYTE;
+		break;
+
+	case 4:
+		dma_cmd |= DMAC_DCMD_DS_32BIT;
+		break;
+
+	default:
+		;
+	}
+	if (DMA_MODE_WRITE == mode) {
+		dma_cmd |= DMAC_DCMD_SAI;
+		src_addr = (unsigned int)phyaddr;      /* DMA source address */
+		dst_addr = CPHYSADDR(MSC_TXFIFO(host->pdev_id));      /* DMA target address */
+		MSC_SET_OUT_REQ_SRC(host->pdev_id, req_src);
+	} else {
+		dma_cmd |= DMAC_DCMD_DAI;
+		src_addr = CPHYSADDR(MSC_RXFIFO(host->pdev_id));
+		dst_addr = (unsigned int)phyaddr;
+		MSC_SET_IN_REQ_SRC(host->pdev_id, req_src);
+	}
+
+	REG_DMAC_DCCSR(chan) |= DMAC_DCCSR_NDES; /* No-descriptor transfer */
+	REG_DMAC_DSAR(chan) = src_addr;
+	REG_DMAC_DTAR(chan) = dst_addr;
+	REG_DMAC_DTCR(chan) = (count + ds - 1) / ds;
+	REG_DMAC_DCMD(chan) = dma_cmd;
+	REG_DMAC_DRSR(chan) = req_src;
+
+	REG_DMAC_DMACR(chan / HALF_DMA_NUM) |= DMAC_DMACR_DMAE;
+	REG_DMAC_DCCSR(chan) |= DMAC_DCCSR_EN;
+
+	release_dma_lock(flags);
+}
+#endif
+
+void jz_mmc_start_dma(struct jz_mmc_host *host) {
+	struct mmc_data *data = host->curr_mrq->data;
+	int mode;
+#ifndef USE_DMA_DESC
+	int i;
+	int ds = 4;
+	struct scatterlist *sgentry;
+#endif
+
+	if (data->flags & MMC_DATA_WRITE) {
+		mode = DMA_MODE_WRITE;
+		host->dma.dir = DMA_TO_DEVICE;
+	} else {
+		mode = DMA_MODE_READ;
+		host->dma.dir = DMA_FROM_DEVICE;
+	}
+
+	host->dma.len =
+	    dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
+		       host->dma.dir);
+
+#ifdef USE_DMA_DESC
+	jz_mmc_start_scatter_dma(host->dma.channel, host, data->sg, host->dma.len, mode);
+#else
+	j = 0;
+	for_each_sg(data->sg, sgentry, host->dma.len, i) {
+		dma_cache_wback_inv((unsigned long)CKSEG0ADDR(sg_dma_address(sgentry) + data->sg->offset),
+				    sg_dma_len(sgentry));
+
+		if ((likely(sg_dma_len(sgentry) % 32 == 0)))
+			ds = 32; /* 32 byte */
+		else if (sg_dma_len(sgentry) % 16 == 0)
+			ds = 16; /* 16 byte */
+		else
+			ds = 4; /* default to 4 byte */
+
+		/*
+		 * FIXME: bug here!!!!! if NR_SG > 1(current NR_SG==1),
+		 * must wait for current dma done, then next sg
+		 */
+		jz_mmc_start_normal_dma(host, sg_dma_address(sgentry),
+				 sg_dma_len(sgentry), mode, ds);
+	}
+#endif
+}
+
+static irqreturn_t jz_mmc_dma_callback(int irq, void *devid)
+{
+	struct jz_mmc_host *host = devid;
+	int chan = host->dma.channel;
+
+	disable_dma(chan);
+
+	host->data_err = 0;
+	if (__dmac_channel_address_error_detected(chan)) {
+		printk("%s: DMAC address error.\n",
+		       __FUNCTION__);
+		__dmac_channel_clear_address_error(chan);
+		host->data_err = 1;
+		wmb();
+	}
+
+	if (__dmac_channel_transmit_halt_detected(chan)) {
+		printk("%s: DMA chan%d Halted.\n", __func__, chan);
+		__dmac_channel_clear_transmit_halt(chan);
+		host->data_err = 1;
+		wmb();
+	}
+	if (__dmac_channel_transmit_end_detected(chan)) {
+		__dmac_channel_clear_transmit_end(chan);
+	}
+
+	if (host->dma.dir == DMA_FROM_DEVICE) {
+		host->data_ack = 1;
+		wmb();
+		wake_up_interruptible(&host->data_wait_queue);
+	}
+
+	return IRQ_HANDLED;
+}
+
+static char *msc_dma_name[] = {
+	"msc0_dma",
+	"msc1_dma",
+	"msc2_dma",
+};
+
+static int jz_mmc_init_dma(struct jz_mmc_host *host)
+{
+	if (host->dma_id < 0)
+		return 0;     /* not use dma */
+
+	host->dma.channel = jz_request_dma(host->dma_id,
+					   msc_dma_name[host->pdev_id],
+					   jz_mmc_dma_callback,
+					   0, host);
+	if (host->dma.channel < 0) {
+		printk(KERN_ERR "jz_request_dma failed for MMC Rx\n");
+		goto err_out;
+	}
+
+	REG_DMAC_DMACR(host->dma.channel / HALF_DMA_NUM) |= DMAC_DMACR_FMSC;
+
+#ifdef USE_DMA_DESC
+	host->dma_desc = (JZ_MSC_DMA_DESC *)__get_free_pages(GFP_KERNEL, 0);
+#endif
+
+	return 0;
+err_out:
+	return -ENODEV;
+}
+
+static void jz_mmc_deinit_dma(struct jz_mmc_host *host)
+{
+	jz_free_dma(host->dma.channel);
+}
+
+int jz_mmc_dma_register(struct jz_mmc_dma *dma)
+{
+	if(dma == NULL)
+		return -ENOMEM;
+
+	dma->init = jz_mmc_init_dma;
+	dma->deinit = jz_mmc_deinit_dma;
+
+	return 0;
+}
diff --git a/drivers/mmc/host/jzmmc/controller/gpio/jz_mmc_gpio.c b/drivers/mmc/host/jzmmc/jz_mmc_gpio.c
index f7a2c5077a2..4aa9028f16f 100644
--- a/drivers/mmc/host/jzmmc/controller/gpio/jz_mmc_gpio.c
+++ b/drivers/mmc/host/jzmmc/jz_mmc_gpio.c
@@ -1,176 +1,213 @@
-/*

- *  linux/drivers/mmc/host/jz_mmc/gpio/jz_mmc_gpio.c

- *

- * This program is free software; you can redistribute it and/or modify

- * it under the terms of the GNU General Public License version 2 as

- * published by the Free Software Foundation.

- *

- * Copyright (c) Ingenic Semiconductor Co., Ltd.

- */

-

-#include <asm/jzmmc/jz_mmc_gpio.h>

-

-#define	TRY_TIME	10

-#define	RETRY_TIME	50

-

-static void jiq_de_quiver(struct work_struct *ptr){

-	struct jz_mmc_host *host = container_of(ptr, struct jz_mmc_host, gpio_jiq_work);

-	unsigned int time_to_try, i, tmp, counter = 0, result = 1;

-

-	if (unlikely(!host->plat->status)) { /* NEVER */

-		mmc_detect_change(host->mmc, 0);

-		atomic_inc(&host->detect_refcnt);

-		return;

-	}

-

-	for (time_to_try = 0; time_to_try < RETRY_TIME; time_to_try++) {

-		for (i = 0; i < TRY_TIME; i++) {

-			tmp = (!host->plat->status(mmc_dev(host->mmc))); // tmp = 1 means slot is empty

-			result &= tmp;

-			if( !tmp )

-				counter++;

-			schedule_timeout((10*HZ)/1000);

-		}

-

-		if ( !result ) {

-			// The card is there

-			if (counter == TRY_TIME) {

-				printk("Stable the card is there\n");

-				host->eject = 0;

-				/* wait for card removal */

-				host->plat->plug_change(CARD_INSERTED);

-				enable_irq(host->plat->status_irq);

-

-				goto stable;

-			}

-			/* try again, goto for */

-			counter = 0;

-			result = 1;

-		} else {

-			printk("Stable the slot is empty\n");

-			host->eject = 1;

-			/* wait for card insertion */

-			host->plat->plug_change(CARD_REMOVED);

-			enable_irq(host->plat->status_irq);

-			goto stable;

-		}

-	}

-

-stable:

-	/* oldstat: 1 -- eject, 0 -- inserted */

-	/* eject: 1 -- eject, 0 -- inserted */

-

-	if ( (0 == host->oldstat) && (0 == host->eject) && host->sleeping) {

-		mmc_resume_host(host->mmc);

-	}

-

-	if ( (0== host->oldstat) && (1 == host->eject) ) {

-		if (host->sleeping) {

-			mmc_resume_host(host->mmc);

-		} else {

-			mmc_detect_change(host->mmc, 50);

-		}

-

-		wake_up_interruptible(&host->msc_wait_queue);

-	}

-

-	if ( (1 == host->oldstat) && (0 == host->eject) ) {

-		mmc_detect_change(host->mmc, 50);

-	}

-

-	host->sleeping = 0;

-	host->oldstat = host->eject;

-

-	atomic_inc(&host->detect_refcnt);

-}

-

-int jz_mmc_detect(struct jz_mmc_host *host, int from_resuming) {

-	int ret = 0;

-

-	disable_irq_nosync(host->plat->status_irq);

-

-	if (!atomic_dec_and_test(&host->detect_refcnt)) {

-		atomic_inc(&host->detect_refcnt);

-		return 0;

-	}

-

-	printk("jz-msc%d: detect card......\n", host->pdev_id);

-

-	if (from_resuming)

-		schedule_timeout(HZ / 2); /* 500ms, wait for MMC Block module resuming*/

-

-	ret = schedule_delayed_work( &(host->gpio_jiq_work), HZ / 100); /* 10ms, a little time */

-

-	return ret;

-}

-

-static irqreturn_t jz_mmc_detect_irq(int irq, void *devid)

-{

-	printk("enter jz_mmc_detect_irq ......\n");

-	jz_mmc_detect((struct jz_mmc_host *) devid, 0);

-

-	return IRQ_HANDLED;

-}

-

-static int jz_mmc_gpio_init(struct jz_mmc_host *host, struct platform_device *pdev)

-{

-	int ret = 0;

-

-	/*

-	 * Setup card detect change

-	 */

-	if (host->plat->status_irq) {

-		ret = request_irq(host->plat->status_irq,

-				  jz_mmc_detect_irq,

-				  0,

-				  "jz-msc (gpio)",

-				  host);

-		if (ret) {

-			printk(KERN_ERR "Unable to get slot IRQ %d (%d)\n",

-			       host->plat->status_irq, ret);

-			return ret;

-		}

-

-		device_init_wakeup(&pdev->dev, 1);

-

-		INIT_DELAYED_WORK(&(host->gpio_jiq_work), jiq_de_quiver);

-

-		atomic_set(&host->detect_refcnt, 1);

-		host->sleeping = 0;

-

-		// Check if there were any card present

-		if (host->plat->status) {

-			host->eject = !(host->plat->status(mmc_dev(host->mmc)));

-			host->oldstat = host->eject;

-

-			if(host->eject) {

-				host->plat->plug_change(CARD_REMOVED);

-			} else {

-				host->plat->plug_change(CARD_INSERTED);

-			}

-		}

-	} else

-		printk(KERN_ERR "%s: No card detect facilities available\n",

-		       mmc_hostname(host->mmc));

-

-	return 0;

-}

-

-static void jz_mmc_gpio_deinit(struct jz_mmc_host *host, struct platform_device *pdev)

-{

-	if(host->plat->status_irq) {

-		free_irq(host->plat->status_irq, &host);

-		device_init_wakeup(&pdev->dev, 0);

-	}

-}

-

-int jz_mmc_gpio_register(struct jz_mmc_gpio *gpio)

-{

-	if(gpio == NULL)

-		return -ENOMEM;

-

-	gpio->init = jz_mmc_gpio_init;

-	gpio->deinit = jz_mmc_gpio_deinit;

-

-	return 0;

-}

+/*
+ *  linux/drivers/mmc/host/jz_mmc/gpio/jz_mmc_gpio.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Copyright (c) Ingenic Semiconductor Co., Ltd.
+ */
+
+#include <linux/mmc/host.h>
+#include "include/jz_mmc_gpio.h"
+#include "include/jz_mmc_msc.h"
+
+#define	TRY_TIME	10
+#define	RETRY_TIME	50
+
+#define DETECT_CHANGE_DELAY 50
+
+static void jz_mmc_enable_detect(unsigned long arg) {
+	struct jz_mmc_host *host = (struct jz_mmc_host *)arg;
+
+	atomic_inc(&host->detect_refcnt);
+
+	if (host->eject) {
+		/* wait for card insertion */
+		host->plat->plug_change(CARD_REMOVED);
+	} else {
+		/* wait for card removal */
+		host->plat->plug_change(CARD_INSERTED);
+	}
+	enable_irq(host->plat->status_irq);
+}
+
+static void jz_mmc_enable_card_detect(struct jz_mmc_host *host) {
+	host->timer.expires = jiffies + DETECT_CHANGE_DELAY * 2;
+	host->timer.data = (unsigned long)host;
+	host->timer.function = jz_mmc_enable_detect;
+	add_timer(&host->timer);
+}
+
+static void jiq_de_quiver(struct work_struct *ptr){
+	struct jz_mmc_host *host = container_of((struct delayed_work *)ptr,
+						struct jz_mmc_host, gpio_jiq_work);
+	unsigned int time_to_try, i, tmp, counter = 0, result = 1;
+
+	if (unlikely(!host->plat->status)) { /* NEVER */
+		mmc_detect_change(host->mmc, 0);
+		jz_mmc_enable_card_detect(host);
+		return;
+	}
+
+	for (time_to_try = 0; time_to_try < RETRY_TIME; time_to_try++) {
+		for (i = 0; i < TRY_TIME; i++) {
+			tmp = (!host->plat->status(mmc_dev(host->mmc))); // tmp = 1 means slot is empty
+			result &= tmp;
+			if( !tmp )
+				counter++;
+			schedule_timeout((10*HZ)/1000);
+		}
+
+		if ( !result ) {
+			// The card is there
+			if (counter == TRY_TIME) {
+				host->eject = 0;
+				printk("Card Insert\n");
+				goto stable;
+			}
+			/* try again, goto for */
+			counter = 0;
+			result = 1;
+		} else {
+			host->eject = 1;
+			printk("Card Eject\n");
+			goto stable;
+		}
+	}
+
+stable:
+	/* oldstat: 1 -- eject, 0 -- inserted */
+	/* eject: 1 -- eject, 0 -- inserted */
+
+	if ( (0 == host->oldstat) && (0 == host->eject) && host->sleeping) {
+		mmc_resume_host(host->mmc);
+	}
+
+	if ( (0== host->oldstat) && (1 == host->eject) ) {
+		if (host->sleeping) {
+			mmc_resume_host(host->mmc);
+		} else {
+			mmc_detect_change(host->mmc, 50);
+				if (REG_MSC_STAT(host->pdev_id) & MSC_STAT_CLK_EN){
+					printk(" ====> Clock is on\n");
+					jz_mmc_reset(host);
+				}
+
+
+		}
+
+		wake_up_interruptible(&host->data_wait_queue);
+	}
+
+	if ( (1 == host->oldstat) && (0 == host->eject) ) {
+		mmc_detect_change(host->mmc, 50);
+	}
+
+	host->sleeping = 0;
+	host->oldstat = host->eject;
+	jz_mmc_enable_card_detect(host);
+}
+
+int jz_mmc_detect(struct jz_mmc_host *host, int from_resuming) {
+	int ret = 0;
+
+	if (!atomic_dec_and_test(&host->detect_refcnt)) {
+		atomic_inc(&host->detect_refcnt);
+		return 0;
+	}
+
+	disable_irq_nosync(host->plat->status_irq);
+
+	if (from_resuming)
+		schedule_timeout(HZ / 2); /* 500ms, wait for MMC Block module resuming*/
+
+	ret = schedule_delayed_work( &(host->gpio_jiq_work), HZ / 100); /* 10ms, a little time */
+
+	return ret;
+}
+
+#if 0
+extern int wait_cmd_done;
+extern void jz_mmc_dump_regs(int msc_id, int line);
+volatile int error_may_happen = 0;
+#endif
+
+static irqreturn_t jz_mmc_detect_irq(int irq, void *devid)
+{
+#if 0
+	printk("===>enter %s\n", __func__);
+	if (wait_cmd_done) {
+		printk("============================>CAUTION: error may happen!\n");
+		//jz_mmc_dump_regs(1, __LINE__);
+		error_may_happen = 1;
+	}
+#endif
+	jz_mmc_detect((struct jz_mmc_host *) devid, 0);
+
+	return IRQ_HANDLED;
+}
+
+static int jz_mmc_gpio_init(struct jz_mmc_host *host, struct platform_device *pdev)
+{
+	int ret = 0;
+
+	/*
+	 * Setup card detect change
+	 */
+	if (host->plat->status_irq) {
+		ret = request_irq(host->plat->status_irq,
+				  jz_mmc_detect_irq,
+				  0,
+				  "jz-msc (gpio)",
+				  host);
+		if (ret) {
+			printk(KERN_ERR "Unable to get slot IRQ %d (%d)\n",
+			       host->plat->status_irq, ret);
+			return ret;
+		}
+
+		device_init_wakeup(&pdev->dev, 1);
+
+		INIT_DELAYED_WORK(&(host->gpio_jiq_work), jiq_de_quiver);
+		init_timer(&host->timer);
+
+		atomic_set(&host->detect_refcnt, 1);
+		host->sleeping = 0;
+
+		// Check if there were any card present
+		if (host->plat->status) {
+			host->eject = !(host->plat->status(mmc_dev(host->mmc)));
+			host->oldstat = host->eject;
+
+			if(host->eject) {
+				host->plat->plug_change(CARD_REMOVED);
+			} else {
+				host->plat->plug_change(CARD_INSERTED);
+			}
+		}
+	} else
+		printk(KERN_ERR "%s: No card detect facilities available\n",
+		       mmc_hostname(host->mmc));
+
+	return 0;
+}
+
+static void jz_mmc_gpio_deinit(struct jz_mmc_host *host, struct platform_device *pdev)
+{
+	if(host->plat->status_irq) {
+		free_irq(host->plat->status_irq, host);
+		device_init_wakeup(&pdev->dev, 0);
+	}
+}
+
+int jz_mmc_gpio_register(struct jz_mmc_gpio *gpio)
+{
+	if(gpio == NULL)
+		return -ENOMEM;
+
+	gpio->init = jz_mmc_gpio_init;
+	gpio->deinit = jz_mmc_gpio_deinit;
+
+	return 0;
+}
diff --git a/drivers/mmc/host/jzmmc/jz_mmc_main.c b/drivers/mmc/host/jzmmc/jz_mmc_main.c
index ad994921245..eaa6ebcaab4 100644
--- a/drivers/mmc/host/jzmmc/jz_mmc_main.c
+++ b/drivers/mmc/host/jzmmc/jz_mmc_main.c
@@ -1,393 +1,522 @@
-/*

- *  linux/drivers/mmc/host/jz_mmc/jz_mmc_main.c - JZ SD/MMC driver

- *

- * This program is free software; you can redistribute it and/or modify

- * it under the terms of the GNU General Public License version 2 as

- * published by the Free Software Foundation.

- *

- * Copyright (c) Ingenic Semiconductor Co., Ltd.

- */

-

-#include <linux/module.h>

-#include <linux/init.h>

-#include <linux/ioport.h>

-#include <linux/platform_device.h>

-#include <linux/delay.h>

-#include <linux/interrupt.h>

-#include <linux/dma-mapping.h>

-#include <linux/mmc/host.h>

-#include <linux/mmc/mmc.h>

-#include <linux/mmc/sd.h>

-#include <linux/mmc/sdio.h>

-#include <linux/mm.h>

-#include <linux/signal.h>

-#include <linux/pm.h>

-#include <linux/scatterlist.h>

-#include <asm/io.h>

-#include <asm/scatterlist.h>

-#include <asm/jzsoc.h>

-#include <asm/jzmmc/jz_mmc_host.h>

-#include <asm/jzmmc/jz_mmc_controller.h>

-

-#define NUMBER_OF_CTRL 2

-

-struct jz_mmc_controller controller[NUMBER_OF_CTRL];

-

-static void jz_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)

-{

-	struct jz_mmc_host *host = mmc_priv(mmc);

-	unsigned int cmdat;

-	struct jz_mmc_functions *functions = host->plat->driver_data;

-

-	cmdat = host->cmdat;

-	host->cmdat &= ~MSC_CMDAT_INIT;

-	host->cmdat &= ~MSC_CMDAT_STREAM_BLOCK;

-

-	if (host->eject) {

-		if (mrq->data && !(mrq->data->flags & MMC_DATA_READ)) {

-			mrq->cmd->error = 0;

-			mrq->data->bytes_xfered = mrq->data->blksz *

-						  mrq->data->blocks;

-		} else

-			mrq->cmd->error = -ENOMEDIUM;

-

-		mmc_request_done(mmc, mrq);

-		return;

-	}

-

-	if (host->curr.mrq || host->curr.data || host->curr.cmd) {

-		printk("warning, another request is processing!!!!\n");

-	}

-	host->curr.mrq = mrq;

-	host->curr.data = mrq->data;

-	host->curr.cmd = NULL;

-

-	if(mrq->data) {

-		cmdat &= ~MSC_CMDAT_BUSY;

-

-		if ((mrq->cmd->opcode == 51) | (mrq->cmd->opcode == 8) | (mrq->cmd->opcode == 6)) {

-			cmdat &= ~MSC_CMDAT_BUS_WIDTH_MASK;

-			cmdat |= MSC_CMDAT_BUS_WIDTH_1BIT | MSC_CMDAT_DATA_EN;

-		} else

-			cmdat |= MSC_CMDAT_DATA_EN;

-#ifdef USE_DMA

-		cmdat |= MSC_CMDAT_DMA_EN;

-#endif

-

-		if (mrq->data->flags & MMC_DATA_WRITE)

-			cmdat |= MSC_CMDAT_WRITE;

-

-		if (mrq->data->flags & MMC_DATA_STREAM)

-			cmdat |= MSC_CMDAT_STREAM_BLOCK;

-

-		if (mrq->data->flags & MMC_DATA_READ)

-			functions->transmit_data(host);

-	}

-

-	functions->execute_cmd(host, mrq->cmd, cmdat);

-}

-

-static int jz_mmc_get_ro(struct mmc_host *mmc)

-{

-	struct jz_mmc_host *host = mmc_priv(mmc);

-

-	if(host->plat->write_protect != NULL)

-		return host->plat->write_protect(mmc_dev(host->mmc));

-	else

-		return 0;

-}

-

-static int jz_mmc_get_cd(struct mmc_host *mmc)

-{

-	struct jz_mmc_host *host = mmc_priv(mmc);

-

-	if(host->plat->status != NULL) {

-		return host->plat->status(mmc_dev(host->mmc));

-	}

-	else

-		return 1;

-}

-

-/* set clock and power */

-static void jz_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)

-{

-	struct jz_mmc_host *host = mmc_priv(mmc);

-	struct jz_mmc_functions *functions = host->plat->driver_data;

-	//void *dev;

-

-	if(!functions) {

-//		printk("%s: functions is NULL!\n", __FUNCTION__);

-		while(1);

-	}

-

-	if (ios->clock) {

-		functions->set_clock(host, ios->clock);

-	}

-

-	switch(ios->power_mode) {

-	case MMC_POWER_ON:

-		host->plat->power_on(NULL);

-		host->cmdat |= CMDAT_INIT;

-		break;

-	case MMC_POWER_OFF:

-		host->plat->power_off(NULL);

-		break;

-	default:

-		break;

-	}

-

-	if (ios->bus_width == MMC_BUS_WIDTH_4) {

-

-		host->cmdat &= ~MSC_CMDAT_BUS_WIDTH_MASK;

-

-		if(host->plat->bus_width == 4)

-			host->cmdat |= MSC_CMDAT_BUS_WIDTH_4BIT;

-		else

-			host->cmdat |= host->plat->bus_width;

-	} else if (ios->bus_width == MMC_BUS_WIDTH_8) {

-

-		host->cmdat &= ~MSC_CMDAT_BUS_WIDTH_MASK;

-

-		if(host->plat->bus_width == 8)

-			host->cmdat |= MSC_CMDAT_BUS_WIDTH_8BIT;

-//		else

-//			host->cmdat |= host->plat->bus_width;

-	} else {

-		/* 1 bit bus*/

-		host->cmdat &= ~MSC_CMDAT_BUS_WIDTH_8BIT;

-	}

-}

-

-static const struct mmc_host_ops jz_mmc_ops = {

-	.request = jz_mmc_request,

-	.get_ro = jz_mmc_get_ro,

-	.set_ios = jz_mmc_set_ios,

-	.get_cd = jz_mmc_get_cd,

-};

-

-static int jz_mmc_probe(struct platform_device *pdev)

-{

-	struct jz_mmc_platform_data *plat = pdev->dev.platform_data;

-	struct mmc_host *mmc;

-	struct jz_mmc_host *host = NULL;

-//	struct jz_mmc_controller controller;

-	struct jz_mmc_functions *functions;

-

-	struct resource *irqres = NULL;

-	struct resource *memres = NULL;

-	struct resource *dmares = NULL;

-	int i;

-#ifndef USE_DMA_DESC

-	int ret = 0;

-#endif

-

-	if (pdev == NULL) {

-		printk(KERN_ERR "%s: pdev is NULL\n", __func__);

-		return -EINVAL;

-	}

-	if (!plat) {

-		printk(KERN_ERR "%s: Platform data not available\n", __func__);

-		return -EINVAL;

-	}

-

-

-

-	if (pdev->id < 0 || pdev->id > 1)

-		return -EINVAL;

-

-	plat->cpm_start(&pdev->dev);

-

-	// IORESOURCE_DMA is NOT required

-	if (pdev->resource == NULL || pdev->num_resources < 2) {

-		printk(KERN_ERR "%s: Invalid resource\n", __func__);

-		return -ENXIO;

-	}

-	for (i = 0; i < pdev->num_resources; i++) {

-		if (pdev->resource[i].flags & IORESOURCE_MEM)

-			memres = &pdev->resource[i];

-		if (pdev->resource[i].flags & IORESOURCE_IRQ)

-			irqres = &pdev->resource[i];

-		if (pdev->resource[i].flags & IORESOURCE_DMA)

-			dmares = &pdev->resource[i];

-	}

-	if (!irqres || !memres) {

-		printk(KERN_ERR "%s: Invalid resource\n", __func__);

-		return -ENXIO;

-	}

-	/*

-	 * Setup our host structure

-	 */

-	mmc = mmc_alloc_host(sizeof(struct jz_mmc_host), &pdev->dev);

-	if (!mmc) {

-		return -ENOMEM;

-	}

-	host = mmc_priv(mmc);

-	host->pdev_id = pdev->id;

-	host->plat = plat;

-	host->mmc = mmc;

-	// base address of MSC controller

-	host->base = ioremap(memres->start, PAGE_SIZE);

-	if (!host->base) {

-		return -ENOMEM;

-	}

-	// back up these info. for future using

-	host->irqres = irqres;

-	host->memres = memres;

-	host->dmares = dmares;

-	host->imask = 0xffff;

-#ifndef USE_DMA_DESC

-	host->sg_cpu =

-		dma_alloc_coherent(&pdev->dev, PAGE_SIZE, &host->sg_dma,

-				   GFP_KERNEL);

-

-	if (!host->sg_cpu) {

-		ret = -ENOMEM;

-		goto out;

-	}

-#endif

-	spin_lock_init(&host->lock);

-

-	/*

-	 * Setup MMC host structure

-	 */

-	mmc->ops = &jz_mmc_ops;

-	mmc->f_min = MMC_CLOCK_SLOW;

-	mmc->f_max = SD_CLOCK_HIGH;

-	mmc->ocr_avail = plat->ocr_mask;

-	mmc->caps |= host->plat->max_bus_width;

-	mmc->max_phys_segs = NR_SG;

-	mmc->max_blk_size = 4095;

-	mmc->max_blk_count = 65535;

-

-	mmc->max_req_size = PAGE_SIZE * 16;

-	mmc->max_seg_size = mmc->max_req_size;

-	plat->init(&pdev->dev);

-	plat->power_on(&pdev->dev);

-	/*

-	 * Initialize controller and register some functions

-	 * From here, we can do everything!

-	 */

-	controller_register(&controller[host->pdev_id], host);

-	functions = host->plat->driver_data;

-

-	if(controller[host->pdev_id].init(&controller[host->pdev_id], host, pdev))

-		goto out;

-

-//	printk("%s: functions->set_clock = %x  jz_mmc_set_clock = %x\n", __FUNCTION__, functions->set_clock, jz_mmc_set_clock);

-	mmc_set_drvdata(pdev, mmc);

-	mmc_add_host(mmc);

-

-	printk("JZ %s driver registered\n", pdev->name);

-

-	return 0;

-

-out:

-#ifndef USE_DMA_DESC

-	if (host->sg_cpu)

-		dma_free_coherent(&pdev->dev, PAGE_SIZE,

-				  host->sg_cpu, host->sg_dma);

-#endif

-	return -1;

-}

-

-static int jz_mmc_remove(struct platform_device *pdev)

-{

-	struct mmc_host *mmc = platform_get_drvdata(pdev);

-	struct jz_mmc_platform_data *plat = pdev->dev.platform_data;

-

-	platform_set_drvdata(pdev, NULL);

-

-	if (mmc) {

-		struct jz_mmc_host *host = mmc_priv(mmc);

-		struct jz_mmc_functions *functions = host->plat->driver_data;

-

-		plat->power_off(&pdev->dev);

-

-		functions->deinit(host, pdev);

-

-		mmc_remove_host(mmc);

-		mmc_free_host(mmc);

-	}

-	return 0;

-}

-

-#ifdef CONFIG_PM

-static int jz_mmc_suspend(struct platform_device *dev, pm_message_t state)

-{

-	struct mmc_host *mmc = platform_get_drvdata(dev);

-	struct jz_mmc_host *host = mmc_priv(mmc);

-	int ret = 0;

-

-	host->sleeping = 1;

-

-	printk("enter jz_mmc_suspend......\n");

-	if (mmc) {

-		if (mmc->card && mmc->card->type != MMC_TYPE_SDIO) {

-			ret = mmc_suspend_host(mmc, state);

-		}

-

-	}

-	printk("leave jz_mmc_suspend......\n");

-	return ret;

-}

-

-extern int jz_mmc_detect(struct jz_mmc_host *host, int from_resuming);

-static int jz_mmc_resume(struct platform_device *dev)

-{

-	struct mmc_host *mmc = platform_get_drvdata(dev);

-	struct jz_mmc_host *host = mmc_priv(mmc);

-

-	printk("enter jz_mmc_resume......\n");

-	if (mmc) {

-		if ( (mmc->card == NULL) || (mmc->card->type != MMC_TYPE_SDIO) )

-			jz_mmc_detect(host, 1);

-	}

-

-	return 0;

-}

-#else

-#define jz_mmc_suspend      NULL

-#define jz_mmc_resume       NULL

-#endif

-

-static struct platform_driver jz_mmc0_driver = {

-	.probe = jz_mmc_probe,

-	.remove = jz_mmc_remove,

-	.suspend = jz_mmc_suspend,

-	.resume = jz_mmc_resume,

-	.driver = {

-		   .name = "jz-msc0",

-		   },

-};

-

-static struct platform_driver jz_mmc1_driver = {

-	.probe = jz_mmc_probe,

-	.remove = jz_mmc_remove,

-	.suspend = jz_mmc_suspend,

-	.resume = jz_mmc_resume,

-	.driver = {

-		   .name = "jz-msc1",

-		   },

-};

-

-static int __init jz_mmc_init(void)

-{

-	int ret = 0;

-	printk("here!!!!!jz_mmc_init......\n");

-	ret = platform_driver_register(&jz_mmc0_driver);

-	ret = platform_driver_register(&jz_mmc1_driver);

-

-	return ret;

-}

-

-static void __exit jz_mmc_exit(void)

-{

-	platform_driver_unregister(&jz_mmc1_driver);

-	platform_driver_unregister(&jz_mmc0_driver);

-}

-

-module_init(jz_mmc_init);

-module_exit(jz_mmc_exit);

-

-MODULE_DESCRIPTION("JZ47XX SD/Multimedia Card Interface Driver");

-MODULE_LICENSE("GPL");

+/*
+ *  linux/drivers/mmc/host/jz_mmc/jz_mmc_main.c - JZ SD/MMC driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Copyright (c) Ingenic Semiconductor Co., Ltd.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/dma-mapping.h>
+#include <linux/mmc/host.h>
+#include <linux/mmc/mmc.h>
+#include <linux/mmc/sd.h>
+#include <linux/mmc/sdio.h>
+#include <linux/mmc/card.h>
+#include <linux/mm.h>
+#include <linux/signal.h>
+#include <linux/pm.h>
+#include <linux/scatterlist.h>
+#include <asm/io.h>
+#include <asm/scatterlist.h>
+#include <asm/jzsoc.h>
+#include "include/jz_mmc_host.h"
+#include "include/jz_mmc_controller.h"
+
+/* for Atheros wifi */
+int is_virt_addr_valid(unsigned char *buffer) {
+	return virt_addr_valid(buffer);
+}
+EXPORT_SYMBOL(is_virt_addr_valid);
+
+struct jz_mmc_controller controller[JZ_MAX_MSC_NUM];
+int is_permission = 0;
+
+int jz_mmc_get_permission(struct mmc_host *mmc, struct mmc_request *mrq){
+	int sector,up_limit,down_limit;
+
+	if (!mmc_card_blockaddr(mmc->card)){
+		up_limit = 16384 << 9 ;
+		down_limit = 512;
+	}
+	else{
+		up_limit = 16384 ;
+		down_limit = 1;
+	}
+	sector = mrq->cmd->arg;
+
+	if(sector>down_limit && sector<up_limit){
+
+		return is_permission;
+	}else{
+		return 1;
+	}
+}
+
+/* add partitions info for recovery */
+#ifdef CONFIG_JZ_RECOVERY_SUPPORT
+static ssize_t jz_mmc_partitions_show(struct device *dev,struct device_attribute *attr, char *buf)
+{
+	int i;
+	struct jz_mmc_platform_data *pdata = dev->platform_data;
+	ssize_t count = 0;
+
+	if(pdata->num_partitions == 0) {
+		count = sprintf(buf, "null\n");
+		return count;
+	}
+
+	for(i=0;i<pdata->num_partitions;i++)
+		count += sprintf(buf+count, "%s %x %x %d\n",
+				pdata->partitions[i].name,
+				pdata->partitions[i].saddr,
+				pdata->partitions[i].len,
+				pdata->partitions[i].type);
+
+	return count;
+}
+
+
+static ssize_t jz_mmc_permission_set(struct device *dev, struct device_attribute *attr,
+			  const char *buf, size_t count)
+{
+	struct jz_mmc_platform_data *pdata = dev->platform_data;
+
+	if (buf == NULL)
+		return count;
+
+	if (strcmp(buf, "RECOVERY_MODE") == 0) {
+		printk("host->permission: MMC_BOOT_AREA_PROTECTED->MMC_BOOT_AREA_OPENED\n");
+		pdata->permission = MMC_BOOT_AREA_OPENED;
+	} else {
+		printk("host->permission: MMC_BOOT_AREA_OPENED->MMC_BOOT_AREA_PROTECTED\n");
+		pdata->permission = MMC_BOOT_AREA_PROTECTED;
+	}
+
+	return count;
+}
+
+static DEVICE_ATTR(partitions, S_IRUSR | S_IRGRP | S_IROTH, jz_mmc_partitions_show, NULL);
+static DEVICE_ATTR(recovery_permission, S_IWUSR, NULL, jz_mmc_permission_set);
+
+static struct attribute *jz_mmc_attributes[] = {
+	&dev_attr_partitions.attr,
+	&dev_attr_recovery_permission.attr,
+	NULL
+};
+
+static const struct attribute_group jz_mmc_attr_group = {
+	.attrs = jz_mmc_attributes,
+};
+#endif
+
+void jz_mmc_finish_request(struct jz_mmc_host *host, struct mmc_request *mrq)
+{
+	host->curr_mrq = NULL;
+	up(&host->mutex);
+	mmc_request_done(host->mmc, mrq);
+}
+
+static void jz_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
+{
+	struct jz_mmc_host *host = mmc_priv(mmc);
+	struct jz_mmc_functions *functions = host->plat->driver_data;
+
+	down(&host->mutex);
+
+	if (SD_IO_SEND_OP_COND == mrq->cmd->opcode) {
+		if(host->plat->support_sdio == 0) {
+			mrq->cmd->error = -ETIMEDOUT;
+			jz_mmc_finish_request(host, mrq);
+			return;
+		}
+	}
+
+	if (host->eject) {
+		if (mrq->data && !(mrq->data->flags & MMC_DATA_READ)) {
+			mrq->cmd->error = -EIO;
+			mrq->data->bytes_xfered = 0;
+		} else
+			mrq->cmd->error = -ENOMEDIUM;
+		up(&host->mutex);
+		mmc_request_done(mmc, mrq);
+		return;
+	}
+
+#if defined(CONFIG_JZ_SYSTEM_AT_CARD)
+	if(host->pdev_id == 0 ){
+		if (mrq->data && (mrq->data->flags & MMC_DATA_WRITE)){
+			if(!jz_mmc_get_permission(mmc, mrq) && mrq->cmd->opcode != 6) {
+				mrq->cmd->error = -EIO;
+				mrq->data->bytes_xfered = 0;
+
+					up(&host->mutex);
+					mmc_request_done(mmc, mrq);
+					return;
+			}
+		}
+	}
+#endif
+
+	BUG_ON (host->curr_mrq);
+	host->curr_mrq = mrq;
+	functions->execute_cmd(host);
+	jz_mmc_finish_request(host, mrq);
+}
+
+static int jz_mmc_get_ro(struct mmc_host *mmc)
+{
+	struct jz_mmc_host *host = mmc_priv(mmc);
+
+	if(host->plat->write_protect != NULL)
+		return host->plat->write_protect(mmc_dev(host->mmc));
+	else
+		return 0;
+}
+
+static int jz_mmc_get_cd(struct mmc_host *mmc)
+{
+	struct jz_mmc_host *host = mmc_priv(mmc);
+
+	if(host->plat->status != NULL) {
+		return host->plat->status(mmc_dev(host->mmc));
+	}
+	else
+		return 1;
+}
+
+/* set clock and power */
+static void jz_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
+{
+	struct jz_mmc_host *host = mmc_priv(mmc);
+	struct jz_mmc_functions *functions = host->plat->driver_data;
+	//void *dev;
+
+	if(!functions) {
+//		printk("%s: functions is NULL!\n", __FUNCTION__);
+		while(1);
+	}
+
+	if (ios->clock) {
+		functions->set_clock(host, ios->clock);
+	}
+
+	switch(ios->power_mode) {
+	case MMC_POWER_ON:
+		host->plat->power_on(NULL);
+		host->cmdat |= MSC_CMDAT_INIT;
+		break;
+	case MMC_POWER_OFF:
+		host->plat->power_off(NULL);
+		break;
+	default:
+		break;
+	}
+
+	if (ios->bus_width == MMC_BUS_WIDTH_4) {
+
+		host->cmdat &= ~MSC_CMDAT_BUS_WIDTH_MASK;
+
+		if(host->plat->bus_width == 4)
+			host->cmdat |= MSC_CMDAT_BUS_WIDTH_4BIT;
+		else
+			host->cmdat |= host->plat->bus_width;
+	} else if (ios->bus_width == MMC_BUS_WIDTH_8) {
+
+		host->cmdat &= ~MSC_CMDAT_BUS_WIDTH_MASK;
+
+		if(host->plat->bus_width == 8)
+			host->cmdat |= MSC_CMDAT_BUS_WIDTH_8BIT;
+//		else
+//			host->cmdat |= host->plat->bus_width;
+	} else {
+		/* 1 bit bus*/
+		host->cmdat &= ~MSC_CMDAT_BUS_WIDTH_8BIT;
+	}
+}
+
+static const struct mmc_host_ops jz_mmc_ops = {
+	.request = jz_mmc_request,
+	.get_ro = jz_mmc_get_ro,
+	.set_ios = jz_mmc_set_ios,
+	.get_cd = jz_mmc_get_cd,
+};
+
+#ifdef MSC_DEBUG_DMA
+static struct jz_mmc_host *msc_hosts[JZ_MAX_MSC_NUM] = { NULL, NULL, NULL };
+
+static void dump_host_info(struct jz_mmc_host *host) {
+	int i = 0;
+	JZ_MSC_DMA_DESC *desc = NULL;
+
+	printk("*** msc%d host info ***\n", host->pdev_id);
+	dump_jz_dma_channel(host->dma.channel);
+	printk("*** last running descriptors = %d direction = %d ***\n", host->num_desc, host->last_direction);
+	desc = host->dma_desc;
+	for (i = 0; i < host->num_desc; i++) {
+		printk("desc address = %p\n", desc + i);
+		printk("dcmd = 0x%08x\n", desc[i].dcmd);
+		printk("dsadr = 0x%08x\n", desc[i].dsadr);
+		printk("dtadr = 0x%08x\n", desc[i].dtadr);
+		printk("ddadr = 0x%08x\n", desc[i].ddadr);
+		printk("dstrd = 0x%08x\n", desc[i].dstrd);
+		printk("dreqt = 0x%08x\n", desc[i].dreqt);
+		printk("resv0 = 0x%08x\n", desc[i].reserved0);
+		printk("resv1 = 0x%08x\n", desc[i].reserved1);
+		printk("==========\n");
+	}
+
+	printk("curr tx_ack = %d\n", host->tx_ack);
+	printk("curr rx_ack = %d\n", host->rx_ack);
+}
+
+void msc_dump_host_info(void) {
+	int i = 0;
+
+	for (i = 0; i < JZ_MAX_MSC_NUM; i++) {
+		if (msc_hosts[i] != NULL) {
+			dump_host_info(msc_hosts[0]);
+		}
+	}
+}
+EXPORT_SYMBOL(msc_dump_host_info);
+#endif	/* MSC_DEBUG_DMA */
+
+#if defined(CONFIG_JZ_RECOVERY_SUPPORT) || defined(CONFIG_JZ_SYSTEM_AT_CARD)
+static ssize_t mmc_permission_show(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	return sprintf(buf, "%d\n", is_permission);
+}
+
+static ssize_t mmc_permission_store(struct device *dev,
+	struct device_attribute *attr, const char *buf, size_t count)
+{
+	int permis;
+
+	permis = simple_strtol(buf, NULL, 10);
+	is_permission = permis;
+	printk("%d\n",is_permission);
+	return count;
+}
+
+static DEVICE_ATTR(permission, S_IWUSR | S_IRUGO, mmc_permission_show, mmc_permission_store);
+#endif
+
+static int jz_mmc_probe(struct platform_device *pdev)
+{
+	struct jz_mmc_platform_data *plat = pdev->dev.platform_data;
+	struct mmc_host *mmc;
+	struct jz_mmc_host *host = NULL;
+	struct jz_mmc_functions *functions;
+
+	struct resource *irqres = NULL;
+	struct resource *memres = NULL;
+	struct resource *dmares = NULL;
+	int i;
+
+	if (pdev == NULL) {
+		printk(KERN_ERR "%s: pdev is NULL\n", __func__);
+		return -EINVAL;
+	}
+	if (!plat) {
+		printk(KERN_ERR "%s: Platform data not available\n", __func__);
+		return -EINVAL;
+	}
+
+	if (JZ_MSC_ID_INVALID(pdev->id))
+		return -EINVAL;
+
+	plat->cpm_start(&pdev->dev);
+
+	if (pdev->resource == NULL || pdev->num_resources < 2) {
+		printk(KERN_ERR "%s: Invalid resource\n", __func__);
+		return -ENXIO;
+	}
+	for (i = 0; i < pdev->num_resources; i++) {
+		if (pdev->resource[i].flags & IORESOURCE_MEM)
+			memres = &pdev->resource[i];
+		if (pdev->resource[i].flags & IORESOURCE_IRQ)
+			irqres = &pdev->resource[i];
+		if (pdev->resource[i].flags & IORESOURCE_DMA)
+			dmares = &pdev->resource[i];
+	}
+	if (!irqres || !memres) {
+		printk(KERN_ERR "%s: Invalid resource\n", __func__);
+		return -ENXIO;
+	}
+	/*
+	 * Setup our host structure
+	 */
+	mmc = mmc_alloc_host(sizeof(struct jz_mmc_host), &pdev->dev);
+	if (!mmc) {
+		return -ENOMEM;
+	}
+	host = mmc_priv(mmc);
+	host->pdev_id = pdev->id;
+	host->plat = plat;
+	host->mmc = mmc;
+#if 0			      /* Lutts */
+	// base address of MSC controller
+	host->base = ioremap(memres->start, PAGE_SIZE);
+	if (!host->base) {
+		return -ENOMEM;
+	}
+#endif
+	host->irq = irqres->start;
+	if (dmares)
+		host->dma_id = dmares->start;
+	else
+		host->dma_id = -1;
+	//spin_lock_init(&host->lock);
+	init_MUTEX(&host->mutex);
+
+	/*
+	 * Setup MMC host structure
+	 */
+	mmc->ops = &jz_mmc_ops;
+	mmc->f_min = MMC_CLOCK_SLOW;
+	mmc->f_max = SD_CLOCK_HIGH;
+	mmc->ocr_avail = plat->ocr_mask;
+	mmc->caps |= host->plat->max_bus_width;
+	mmc->max_phys_segs = NR_SG;
+	mmc->max_blk_size = 4095;
+	mmc->max_blk_count = 65535;
+
+	mmc->max_req_size = PAGE_SIZE * 16;
+	mmc->max_seg_size = mmc->max_req_size;
+	plat->init(&pdev->dev);
+	plat->power_on(&pdev->dev);
+	/*
+	 * Initialize controller and register some functions
+	 * From here, we can do everything!
+	 */
+	controller_register(&controller[host->pdev_id], host);
+	functions = host->plat->driver_data;
+	if(controller[host->pdev_id].init(&controller[host->pdev_id], host, pdev))
+		goto out;
+	mmc_set_drvdata(pdev, mmc);
+	mmc_add_host(mmc);
+#ifdef MSC_DEBUG_DMA
+	msc_hosts[host->pdev_id] = host;
+#endif
+
+	if(host->pdev_id == 0){
+#if defined(CONFIG_JZ_SYSTEM_AT_CARD)
+		if(device_create_file(&pdev->dev, &dev_attr_permission))
+			printk("MSC0: device_create_file for attr_permission failed!\n");;
+#endif
+	}
+#ifdef CONFIG_JZ_RECOVERY_SUPPORT
+	sysfs_create_group(&pdev->dev.kobj, &jz_mmc_attr_group);
+#endif
+	printk("JZ %s driver registered\n", mmc_hostname(host->mmc));
+
+	return 0;
+
+out:
+	return -1;
+}
+
+static int jz_mmc_remove(struct platform_device *pdev)
+{
+	struct mmc_host *mmc = platform_get_drvdata(pdev);
+	struct jz_mmc_platform_data *plat = pdev->dev.platform_data;
+
+	platform_set_drvdata(pdev, NULL);
+
+	if (mmc) {
+		struct jz_mmc_host *host = mmc_priv(mmc);
+		struct jz_mmc_functions *functions = host->plat->driver_data;
+
+		plat->power_off(&pdev->dev);
+
+		functions->deinit(host, pdev);
+
+		mmc_remove_host(mmc);
+		mmc_free_host(mmc);
+	}
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int jz_mmc_suspend(struct platform_device *dev, pm_message_t state)
+{
+	struct mmc_host *mmc = platform_get_drvdata(dev);
+	struct jz_mmc_host *host = mmc_priv(mmc);
+	int ret = 0;
+
+#ifdef CONFIG_JZ_SYSTEM_AT_CARD
+	if (host->pdev_id == 0)
+		return 0;
+#endif
+
+	host->sleeping = 1;
+
+	if (mmc) {
+		if (mmc->card && mmc->card->type != MMC_TYPE_SDIO) {
+			ret = mmc_suspend_host(mmc, state);
+		}
+
+	}
+	return ret;
+}
+
+extern int jz_mmc_detect(struct jz_mmc_host *host, int from_resuming);
+static int jz_mmc_resume(struct platform_device *dev)
+{
+	struct mmc_host *mmc = platform_get_drvdata(dev);
+	struct jz_mmc_host *host = mmc_priv(mmc);
+
+#ifdef CONFIG_JZ_SYSTEM_AT_CARD
+	if (host->pdev_id == 0)
+		return 0;
+#endif
+
+	if (mmc) {
+		if ( (mmc->card == NULL) || (mmc->card->type != MMC_TYPE_SDIO) )
+			jz_mmc_detect(host, 1);
+	}
+
+	return 0;
+}
+#else
+#define jz_mmc_suspend      NULL
+#define jz_mmc_resume       NULL
+#endif
+
+static struct platform_driver jz_msc_driver = {
+	.probe = jz_mmc_probe,
+	.remove = jz_mmc_remove,
+	.suspend = jz_mmc_suspend,
+	.resume = jz_mmc_resume,
+	.driver = {
+		   .name = "jz-msc",
+		   },
+};
+
+static int __init jz_mmc_init(void)
+{
+	int ret = 0;
+
+	ret = platform_driver_register(&jz_msc_driver);
+	return ret;
+}
+
+static void __exit jz_mmc_exit(void)
+{
+	platform_driver_unregister(&jz_msc_driver);
+}
+
+subsys_initcall(jz_mmc_init);
+module_exit(jz_mmc_exit);
+
+MODULE_DESCRIPTION("JZ47XX SD/Multimedia Card Interface Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/mmc/host/jzmmc/jz_mmc_msc.c b/drivers/mmc/host/jzmmc/jz_mmc_msc.c
new file mode 100644
index 00000000000..40200d3ad2e
--- /dev/null
+++ b/drivers/mmc/host/jzmmc/jz_mmc_msc.c
@@ -0,0 +1,838 @@
+/*
+ *  linux/drivers/mmc/host/jz_mmc/msc/jz_mmc_msc.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Copyright (c) Ingenic Semiconductor Co., Ltd.
+ */
+
+#include <linux/dma-mapping.h>
+#include <linux/semaphore.h>
+#include <linux/kthread.h>
+#include <linux/mmc/mmc.h>
+#include <linux/mmc/sd.h>
+#include <linux/mmc/sdio.h>
+#include <linux/mmc/host.h>
+#include <linux/scatterlist.h>
+
+#include <asm/jzsoc.h>
+#include "include/jz_mmc_msc.h"
+#include "include/jz_mmc_pio.h"
+
+#define MSC_STAT_ERR_BITS 0x3f
+#define WAITMASK							\
+	(MSC_STAT_CRC_RES_ERR |						\
+	 MSC_STAT_CRC_READ_ERROR | MSC_STAT_CRC_WRITE_ERROR_MASK |	\
+	 MSC_STAT_TIME_OUT_RES | MSC_STAT_TIME_OUT_READ)
+
+#if 1
+
+static int jzmmc_trace_level = 0;
+static int jzmmc_trace_cmd_code = -1;
+static int jzmmc_trace_data_len = -1;
+module_param(jzmmc_trace_level, int, 0644);
+module_param(jzmmc_trace_cmd_code, int, 0644);
+module_param(jzmmc_trace_data_len, int, 0644);
+
+#define TRACE_CMD_REQ()							\
+	({								\
+		if (jzmmc_trace_level & 0x1)				\
+			if ( (jzmmc_trace_cmd_code == -1) || (jzmmc_trace_cmd_code == cmd->opcode) ) \
+				printk("%s:     execute_cmd: opcode = %d cmdat = %#0x arg = %#0x data_flags = %#0x\n", \
+				       mmc_hostname(host->mmc), cmd->opcode, REG_MSC_CMDAT(host->pdev_id), REG_MSC_ARG(host->pdev_id), \
+				       host->curr_mrq->data ? host->curr_mrq->data->flags : 0); \
+	})
+
+#define TRACE_CMD_RES()							\
+	({								\
+		if (jzmmc_trace_level & 0x1)				\
+			if ( (jzmmc_trace_cmd_code == -1) || (jzmmc_trace_cmd_code == cmd->opcode) ) \
+				printk("%s:     cmd done: curr_res_type = %d resp[0] = %#0x err = %d state = %#0x\n", \
+				       mmc_hostname(host->mmc), host->curr_res_type, cmd->resp[0], cmd->error, \
+				       REG_MSC_STAT(host->pdev_id));	\
+	})
+
+#define TRACE_DATA_REQ()						\
+	({								\
+		if ( (jzmmc_trace_level & 0x2) && host->curr_mrq->data ) {	\
+			if ((jzmmc_trace_data_len == -1) ||		\
+			    (jzmmc_trace_data_len == host->curr_mrq->data->blksz * host->curr_mrq->data->blocks) ) \
+				printk("%s:     blksz %d blocks %d flags %08x "	\
+				       "tsac %d ms nsac %d\n",		\
+				       mmc_hostname(host->mmc), host->curr_mrq->data->blksz, \
+				       host->curr_mrq->data->blocks, host->curr_mrq->data->flags, \
+				       host->curr_mrq->data->timeout_ns / 1000000, \
+				       host->curr_mrq->data->timeout_clks); \
+		}							\
+	})
+
+#define TRACE_DATA_DONE()						\
+	({								\
+		if (jzmmc_trace_level & 0x2)				\
+			if ((jzmmc_trace_data_len == -1) ||		\
+			    (jzmmc_trace_data_len == data->blksz * data->blocks) ) \
+				printk("%s:     stat = 0x%08x error = %d bytes_xfered = %d stop = %p\n", \
+				       mmc_hostname(host->mmc), stat, data->error, \
+				       data->bytes_xfered, host->curr_mrq->stop); \
+	})
+
+#define JZ_MMC_P_REG_BY_ID(reg_name, id) \
+  printk("" #reg_name "(%d) = 0x%08x\n", id, reg_name(id))
+
+void jz_mmc_dump_regs(int msc_id, int line) {
+        printk("***** msc%d regs, line = %d *****\n", msc_id, line);
+
+	JZ_MMC_P_REG_BY_ID(REG_MSC_STRPCL, msc_id);
+	JZ_MMC_P_REG_BY_ID(REG_MSC_STAT, msc_id);
+	JZ_MMC_P_REG_BY_ID(REG_MSC_CLKRT, msc_id);
+	JZ_MMC_P_REG_BY_ID(REG_MSC_CMDAT, msc_id);
+	JZ_MMC_P_REG_BY_ID(REG_MSC_RESTO, msc_id);
+	JZ_MMC_P_REG_BY_ID(REG_MSC_RDTO, msc_id);
+	JZ_MMC_P_REG_BY_ID(REG_MSC_BLKLEN, msc_id);
+	JZ_MMC_P_REG_BY_ID(REG_MSC_NOB, msc_id);
+	JZ_MMC_P_REG_BY_ID(REG_MSC_SNOB, msc_id);
+	JZ_MMC_P_REG_BY_ID(REG_MSC_IMASK, msc_id);
+	JZ_MMC_P_REG_BY_ID(REG_MSC_IREG, msc_id);
+	JZ_MMC_P_REG_BY_ID(REG_MSC_CMD, msc_id);
+	JZ_MMC_P_REG_BY_ID(REG_MSC_ARG, msc_id);
+	//JZ_MMC_P_REG_BY_ID(REG_MSC_RES, msc_id);
+	//JZ_MMC_P_REG_BY_ID(REG_MSC_RXFIFO, msc_id);
+	//JZ_MMC_P_REG_BY_ID(REG_MSC_TXFIFO, msc_id);
+	JZ_MMC_P_REG_BY_ID(REG_MSC_LPM, msc_id);
+}
+EXPORT_SYMBOL(jz_mmc_dump_regs);
+
+#else
+#define TRACE_CMD_REQ() do {  } while(0)
+#define TRACE_CMD_RES() do {  } while(0)
+#define TRACE_DATA_REQ() do {  } while(0)
+#define TRACE_DATA_DONE() do {  } while(0)
+#define jz_mmc_dump_regs(__mid, __ln) do {  } while(0)
+#endif
+
+void jz_mmc_set_clock(struct jz_mmc_host *host, int rate);
+static int jz_mmc_data_done(struct jz_mmc_host *host);
+
+static void msc_irq_mask_all(int msc_id)
+{
+	REG_MSC_IMASK(msc_id) = 0xffff;
+	REG_MSC_IREG(msc_id) = 0xffff;
+}
+
+void jz_mmc_reset(struct jz_mmc_host *host)
+{
+	u32 clkrt = REG_MSC_CLKRT(host->pdev_id);
+
+//	while (REG_MSC_STAT(host->pdev_id) & MSC_STAT_CLK_EN);        //lltang del
+
+	REG_MSC_STRPCL(host->pdev_id) = MSC_STRPCL_RESET;
+ 	while (REG_MSC_STAT(host->pdev_id) & MSC_STAT_IS_RESETTING);
+	// __msc_start_clk(host->pdev_id);
+	REG_MSC_LPM(host->pdev_id) = 0x1;	// Low power mode
+	msc_irq_mask_all(host->pdev_id);
+
+	REG_MSC_RDTO(host->pdev_id) = 0xffffffff;
+	REG_MSC_RESTO(host->pdev_id) = 0xff;
+
+	REG_MSC_CLKRT(host->pdev_id) = clkrt;
+}
+
+static inline int msc_calc_clkrt(int is_low, u32 rate)
+{
+	u32 clkrt;
+	u32 clk_src = is_low ? 24000000 : 48000000;
+
+	clkrt = 0;
+	while (rate < clk_src) {
+		clkrt++;
+		clk_src >>= 1;
+	}
+	return clkrt;
+}
+
+void jz_mmc_set_clock(struct jz_mmc_host *host, int rate)
+{
+	int clkrt;
+
+	/* __cpm_select_msc_clk_high will select 48M clock for MMC/SD card
+	 * perhaps this will made some card with bad quality init fail,or
+	 * bad stabilization.
+	*/
+
+	// Cause there is only ONE devider in CPM, the clock must only <= 24MHz
+#if !defined(CONFIG_SOC_JZ4750) && !defined(CONFIG_SOC_JZ4750D)
+#if 0
+	if (rate > SD_CLOCK_FAST) {
+		cpm_set_clock(CGU_MSCCLK, 48 * 1000 * 1000);
+		clkrt = msc_calc_clkrt(0, rate);
+	} else {
+		cpm_set_clock(CGU_MSCCLK, 24 * 1000 * 1000);
+		clkrt = msc_calc_clkrt(1, rate);
+	}
+#else
+	if (rate > SD_CLOCK_FAST) {
+		rate = SD_CLOCK_FAST;
+		cpm_set_clock(CGU_MSCCLK, 24 * 1000 * 1000);
+		clkrt = msc_calc_clkrt(1, rate);
+	} else {
+		cpm_set_clock(CGU_MSCCLK, 24 * 1000 * 1000);
+		clkrt = msc_calc_clkrt(1, rate);
+	}
+#endif
+	REG_MSC_CLKRT(host->pdev_id) = clkrt;
+#else
+		/* __cpm_select_msc_clk_high will select 48M clock for MMC/SD card
+	 * perhaps this will made some card with bad quality init fail,or
+	 * bad stabilization.
+	*/
+	if (rate > SD_CLOCK_FAST) {
+		rate = SD_CLOCK_FAST;
+		__cpm_select_msc_clk_high(host->pdev_id,1);	/* select clock source from CPM */
+
+		//		__cpm_select_msc_clk(host->pdev_id,1);	/* select clock source from CPM */
+		clkrt = msc_calc_clkrt(0, rate);
+	} else {
+		__cpm_select_msc_clk(host->pdev_id,1);	/* select clock source from CPM */
+		clkrt = msc_calc_clkrt(1, rate);
+	}
+
+	// printk("clock rate = %d\n", __cpm_get_mscclk(0));
+	REG_MSC_CLKRT(host->pdev_id) = clkrt;
+#endif
+}
+
+static void jz_mmc_enable_irq(struct jz_mmc_host *host, unsigned int mask)
+{
+	REG_MSC_IMASK(host->pdev_id) &= ~mask;
+}
+
+static void jz_mmc_disable_irq(struct jz_mmc_host *host, unsigned int mask)
+{
+	REG_MSC_IMASK(host->pdev_id) |= mask;
+}
+
+static int jz_mmc_parse_cmd_response(struct jz_mmc_host *host, unsigned int stat)
+{
+	struct mmc_command *cmd = host->curr_mrq->cmd;
+	int i, temp[16] = {0};
+	unsigned char *buf;
+	unsigned int res, v, w1, w2;
+
+	if (!cmd)
+		return -EINVAL;
+
+	/* NOTE: we must flush the FIFO,  despite of fail or success*/
+	buf = (u8 *) temp;
+	switch (host->curr_res_type) {
+	case 1:
+		{
+			/*
+			 * Did I mention this is Sick.  We always need to
+			 * discard the upper 8 bits of the first 16-bit word.
+			 */
+
+			res = REG_MSC_RES(host->pdev_id);
+			buf[0] = (res >> 8) & 0xff;
+			buf[1] = res & 0xff;
+
+			res = REG_MSC_RES(host->pdev_id);
+			buf[2] = (res >> 8) & 0xff;
+			buf[3] = res & 0xff;
+
+			res = REG_MSC_RES(host->pdev_id);
+			buf[4] = res & 0xff;
+
+			cmd->resp[0] =
+				buf[1] << 24 | buf[2] << 16 | buf[3] << 8 |
+				buf[4];
+
+			// printk("opcode = %d, cmd->resp = 0x%08x\n", cmd->opcode, cmd->resp[0]);
+			break;
+		}
+	case 2:
+		{
+			res = REG_MSC_RES(host->pdev_id);
+			v = res & 0xffff;
+			for (i = 0; i < 4; i++) {
+				res = REG_MSC_RES(host->pdev_id);
+				w1 = res & 0xffff;
+				res = REG_MSC_RES(host->pdev_id);
+				w2 = res & 0xffff;
+				cmd->resp[i] = v << 24 | w1 << 8 | w2 >> 8;
+				v = w2;
+			}
+			break;
+		}
+	case 0:
+		break;
+	}
+
+	if (stat & MSC_STAT_TIME_OUT_RES) {
+		/* :-( our customer do not want to see SO MANY timeouts :-(
+		   so only CMD5 can return timeout error!!! */
+
+		/*
+		 * Note: we can not return timeout when CMD SD_SWITCH or MMC_SWITCH
+		 * because we declared that out host->caps support MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA and MMC_CAP_MMC_HIGHSPEED
+		 * if in the future some error occured because of this, we must add some code to remember
+		 * which mode(SDIO/SD/MMC)  the MSC is in
+		 */
+		switch(cmd->opcode) {
+		case SD_IO_SEND_OP_COND:
+			//case SD_SWITCH:
+			//case MMC_SWITCH:
+		case SD_SEND_IF_COND:
+		case MMC_APP_CMD:
+			cmd->error = -ETIMEDOUT;
+			break;
+		default:
+			/* silly, isn't it??? */
+			printk("jz-msc%d: ignored MSC_STAT_TIME_OUT_RES, cmd=%d\n", host->pdev_id, cmd->opcode);
+		}
+	} else if (stat & MSC_STAT_CRC_RES_ERR && cmd->flags & MMC_RSP_CRC) {
+		printk("jz-msc%d: MSC_STAT_CRC, cmd=%d\n", host->pdev_id, cmd->opcode);
+		if (cmd->opcode == MMC_ALL_SEND_CID ||
+		    cmd->opcode == MMC_SEND_CSD ||
+		    cmd->opcode == MMC_SEND_CID) {
+			/* a bogus CRC error can appear if the msb of
+			   the 15 byte response is a one */
+			if ((cmd->resp[0] & 0x80000000) == 0)
+				cmd->error = -EILSEQ;
+		}
+	}
+
+	TRACE_CMD_RES();
+
+	return cmd->error;
+}
+
+extern void jz_mmc_start_pio(struct jz_mmc_host *host);
+
+void jz_mmc_data_start(struct jz_mmc_host *host)
+{
+	struct mmc_data *data = host->curr_mrq->data;
+	unsigned int nob = data->blocks;
+	unsigned int block_size = data->blksz;
+
+	/* NOTE: this flag is never test! */
+	if (data->flags & MMC_DATA_STREAM)
+		nob = 0xffff;
+
+	REG_MSC_NOB(host->pdev_id) = nob;
+	REG_MSC_BLKLEN(host->pdev_id) = block_size;
+
+#ifdef JZ_MSC_USE_PIO
+	jz_mmc_start_pio(host);
+#endif
+#ifdef JZ_MSC_USE_DMA
+	jz_mmc_start_dma(host);
+#endif
+}
+
+volatile u32 junk = 0;
+EXPORT_SYMBOL(junk);
+
+void jz_mmc_data_stop(struct jz_mmc_host *host) {
+	int junked = 1;
+
+#ifdef JZ_MSC_USE_PIO
+	jz_mmc_stop_pio(host);
+#endif
+#ifdef JZ_MSC_USE_DMA
+	jz_mmc_stop_dma(host);
+#endif
+
+	/* What if the data not arrived imediately? our while exits, but data remain in fifo! */
+	while (!(REG_MSC_STAT(host->pdev_id) & MSC_STAT_DATA_FIFO_EMPTY)) {
+		if (junked)
+			jz_mmc_dump_regs(host->pdev_id, __LINE__);
+		junked = 0;
+		junk = REG_MSC_RXFIFO(host->pdev_id);
+		printk("warning: fifo not empty when dma stopped!!! junk = 0x%08x\n", junk);
+	}
+}
+
+static int need_wait_prog_done(struct mmc_command *cmd) {
+	if (cmd->flags & MMC_RSP_BUSY) {
+		return 1;
+	} else {
+		switch(cmd->opcode) { /* R1b cmds need wait PROG_DONE */
+		case 12:
+		case 28:
+		case 29:
+		case 38:
+			return 1;
+			break;
+		default:
+			/* do nothing */
+			break;
+		}
+	}
+
+	return 0;
+}
+
+static void jz_mmc_set_cmdat(struct jz_mmc_host *host) {
+	struct mmc_request *mrq = host->curr_mrq;
+	struct mmc_command *cmd = mrq->cmd;
+	u32 cmdat;
+
+	cmdat = host->cmdat;
+	rmb();
+	host->cmdat &= ~MSC_CMDAT_INIT;
+
+	if(mrq->data) {
+		cmdat &= ~MSC_CMDAT_BUSY;
+
+		if ((cmd->opcode == 51) | (cmd->opcode == 8)) {
+			cmdat &= ~MSC_CMDAT_BUS_WIDTH_MASK;
+			cmdat |= MSC_CMDAT_BUS_WIDTH_1BIT | MSC_CMDAT_DATA_EN;
+		} else
+			cmdat |= MSC_CMDAT_DATA_EN;
+
+		cmdat |= MSC_CMDAT_DMA_EN;
+
+		if (mrq->data->flags & MMC_DATA_WRITE)
+			cmdat |= MSC_CMDAT_WRITE;
+
+		if (mrq->data->flags & MMC_DATA_STREAM)
+			cmdat |= MSC_CMDAT_STREAM_BLOCK;
+	}
+
+	if (cmd->flags & MMC_RSP_BUSY)
+		cmdat |= MSC_CMDAT_BUSY;
+
+	switch (RSP_TYPE(mmc_resp_type(cmd))) {
+	case RSP_TYPE(MMC_RSP_R1):	// r1, r1b, r5, r6, r7
+		cmdat |= MSC_CMDAT_RESPONSE_R1;
+		host->curr_res_type = 1;
+		break;
+	case RSP_TYPE(MMC_RSP_R3):	// r3, r4
+		cmdat |= MSC_CMDAT_RESPONSE_R3;
+		host->curr_res_type = 1;
+		break;
+	case RSP_TYPE(MMC_RSP_R2):	// r2
+		cmdat |= MSC_CMDAT_RESPONSE_R2;
+		host->curr_res_type = 2;
+		break;
+	default:
+		break;
+	}
+
+	// Multi-read || Multi-write
+	//if(cmd->opcode == MMC_READ_MULTIPLE_BLOCK || cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK)
+	if (host->curr_mrq->stop)
+		cmdat |= MSC_CMDAT_SEND_AS_STOP;
+
+#ifdef USE_DMA_BUSRT_64
+	cmdat |= MSC_CMDAT_RTRG_EQUALT_16 | MSC_CMDAT_TTRG_LESS_16;
+#endif
+	REG_MSC_CMDAT(host->pdev_id) = cmdat;
+}
+
+static void jz_mmc_set_cmdarg(struct jz_mmc_host *host) {
+	struct mmc_command *cmd = host->curr_mrq->cmd;
+
+	if(host->plat->bus_width == 1) {
+		if (cmd->opcode == 6) {
+			/* set  1 bit sd card bus*/
+			if (cmd->arg == 2) {
+				REG_MSC_ARG(host->pdev_id) = 0;
+			}
+
+			/* set  1 bit mmc card bus*/
+			if (cmd->arg == 0x3b70101) {
+				REG_MSC_ARG(host->pdev_id) = 0x3b70001;
+			}
+		} else
+			REG_MSC_ARG(host->pdev_id) = cmd->arg;
+	} else if(host->plat->bus_width == 8) {
+		if (cmd->opcode == 6) {
+			/* set  8 bit mmc card bus*/
+			if (cmd->arg == 0x3b70101) {
+				REG_MSC_ARG(host->pdev_id) = 0x3b70201;
+			} else
+				REG_MSC_ARG(host->pdev_id) = cmd->arg;
+		} else
+			REG_MSC_ARG(host->pdev_id) = cmd->arg;
+	} else
+		REG_MSC_ARG(host->pdev_id) = cmd->arg;
+}
+
+#if 0
+static void jz_mmc_status_checker(unsigned long arg) {
+	struct jz_mmc_host *host = (struct jz_mmc_host *)arg;
+
+	host->status = REG_MSC_STAT(host->pdev_id);
+	if ((host->status & host->st_mask) || (host->eject)) {
+		if (host->en_usr_intr)
+			wake_up_interruptible(&host->status_check_queue);
+		else
+			wake_up(&host->status_check_queue);
+	} else if ((host->st_check_timeout < 0) ||
+		 (host->st_check_timeout > host->st_check_interval)) {
+		if (host->st_check_timeout < 0)
+			host->st_check_timeout -= host->st_check_interval;
+		host->status_check_timer.expires = jiffies + host->st_check_interval;
+		host->status_check_timer.data = (unsigned long)host;
+
+
+		add_timer(&host->status_check_timer);
+	} else {
+		host->st_check_timeout = 0;
+		wake_up_interruptible(&host->status_check_queue);
+	}
+}
+
+
+/**
+  * timeout: -1 for wait forever until contition meet, otherwise the timeout value in jiffies
+  * en_usr_intr: if allow user interrupt
+  * Warning: if timeout == 0 && en_usr_intr == 0, this will wait forever if the condition never meet
+ **/
+static u32 jz_mmc_wait_status(struct jz_mmc_host *host, u32 st_mask,
+			      int timeout, int interval, int en_usr_intr) {
+	int ret = 0;
+
+	init_timer(&host->status_check_timer);
+	host->status_check_timer.expires = jiffies + interval;
+	host->status_check_timer.data = (unsigned long)host;
+	host->status = 0;
+	host->st_mask = st_mask;
+	host->st_check_timeout = timeout;
+	host->st_check_interval = interval;
+	host->en_usr_intr = en_usr_intr;
+
+	add_timer(&host->status_check_timer);
+
+	if (en_usr_intr)
+		ret = wait_event_interruptible(host->status_check_queue,
+					       (host->status & st_mask) ||
+					       (host->st_check_timeout == 0) ||
+					       (host->eject));
+	else
+		wait_event(host->status_check_queue,
+			   (host->status & st_mask) ||
+			   (host->st_check_timeout == 0) ||
+			   (host->eject));
+
+	/* in case when the condition is meet before wait_event, the timer must del right away */
+	del_timer_sync(&host->status_check_timer);
+	return ret;
+}
+#endif
+
+//int wait_cmd_done = 0;
+//extern volatile int error_may_happen;
+
+static u32 jz_mmc_wait_cmd_done(struct jz_mmc_host *host) {
+	u32 timeout = 0x7fffff;
+	struct mmc_command *cmd = host->curr_mrq->cmd;
+	int cmd_succ = 0;
+	u32 stat = 0;
+
+#if 0
+	/* this may slow down the card response from the usrs' view, but more friendly to other kernel parts */
+	jz_mmc_wait_status(host, MSC_STAT_END_CMD_RES | MSC_STAT_TIME_OUT_RES | MSC_STAT_CRC_RES_ERR,
+			   -1, 1, 0); /* interval: 1jiffie = 10ms */
+#else
+	//wait_cmd_done = 1;
+	while (!(REG_MSC_STAT(host->pdev_id) & (MSC_STAT_END_CMD_RES | MSC_STAT_TIME_OUT_RES | MSC_STAT_CRC_RES_ERR)) &&
+	       (host->eject == 0)) {
+#if 0
+		if (error_may_happen)
+			jz_mmc_dump_regs(host->pdev_id, __LINE__);
+#endif
+	}
+	//error_may_happen = 0;
+	//wait_cmd_done = 0;
+#endif
+
+	if (REG_MSC_STAT(host->pdev_id) & MSC_STAT_TIME_OUT_RES)
+		cmd->error = -ETIMEDOUT;
+	if (host->eject) {
+		/* wait response timeout */
+		//printk("===>eject!!! state = 0x%08x\n", REG_MSC_STAT(host->pdev_id));
+		//while (!(REG_MSC_STAT(host->pdev_id) & (MSC_STAT_END_CMD_RES | MSC_STAT_TIME_OUT_RES | MSC_STAT_CRC_RES_ERR)));
+		cmd->error = -ENOMEDIUM;
+	}
+
+	/* Check for status, avoid be cleaned by following command*/
+	stat = REG_MSC_STAT(host->pdev_id);
+	if ((stat & MSC_STAT_END_CMD_RES) &&
+	    !(stat & (MSC_STAT_TIME_OUT_RES | MSC_STAT_CRC_RES_ERR)))
+		cmd_succ = 1;
+
+	REG_MSC_IREG(host->pdev_id) = MSC_IREG_END_CMD_RES;	/* clear irq flag */
+
+	if (cmd_succ && need_wait_prog_done(cmd)) {
+		timeout = 0x7fffff;
+		while (--timeout && !(REG_MSC_IREG(host->pdev_id) & MSC_IREG_PRG_DONE) && (host->eject == 0))
+			;
+
+		stat |= (REG_MSC_STAT(host->pdev_id) & MSC_STAT_ERR_BITS);
+		REG_MSC_IREG(host->pdev_id) = MSC_IREG_PRG_DONE;	/* clear status */
+		if ((timeout == 0) || (host->eject)) {
+			cmd->error = -ETIMEDOUT;
+			printk("JZ-MSC%d: wait prog_done error when execute_cmd!, state = 0x%08x\n", host->pdev_id, stat);
+		}
+	}
+
+	return stat;
+}
+
+static void jz_mmc_send_stop_cmd(struct jz_mmc_host *host) {
+	struct mmc_command *stop_cmd = host->curr_mrq->stop;
+
+	REG_MSC_CMD(host->pdev_id) = stop_cmd->opcode;
+	REG_MSC_ARG(host->pdev_id) = stop_cmd->arg;
+
+	REG_MSC_CMDAT(host->pdev_id) = MSC_CMDAT_BUSY | MSC_CMDAT_RESPONSE_R1;
+
+	REG_MSC_RESTO(host->pdev_id) = 0xff;
+
+	REG_MSC_STRPCL(host->pdev_id) |= MSC_STRPCL_START_OP;
+
+	/* Becarefull, maybe endless */
+	while(!(REG_MSC_STAT(host->pdev_id) & (MSC_STAT_PRG_DONE | MSC_STAT_ERR_BITS)) &&
+	      !host->eject) ;
+
+	if (REG_MSC_STAT(host->pdev_id) | MSC_STAT_ERR_BITS)
+		stop_cmd->error = -ETIMEDOUT;
+
+	REG_MSC_IREG(host->pdev_id) = MSC_IREG_PRG_DONE;
+}
+
+static int jz_mmc_data_done(struct jz_mmc_host *host)
+{
+	struct mmc_data *data = host->curr_mrq->data;
+	int stat = 0;
+	u32 timeout = 0x7fffff;
+
+	if (!data)
+		return -EINVAL;
+
+	stat = REG_MSC_STAT(host->pdev_id);
+	REG_MSC_IREG(host->pdev_id) = MSC_IREG_DATA_TRAN_DONE;	/* clear status */
+
+	if (host->curr_mrq && (host->curr_mrq->data->flags & MMC_DATA_WRITE)) {
+		while (--timeout && !(REG_MSC_IREG(host->pdev_id) & MSC_IREG_PRG_DONE))
+			;
+		if (timeout == 0) {
+			/* FIXME: aha, we never see this situation happen, what can we do if it happened???
+			 * block.c will send cmd13??? */
+			//host->curr.mrq->cmd->error = -ETIMEDOUT;
+			printk(KERN_ERR"PRG_DONE not done!!!\n");
+		}
+		stat |= REG_MSC_STAT(host->pdev_id);
+		REG_MSC_IREG(host->pdev_id) = MSC_IREG_PRG_DONE;	/* clear status */
+	}
+
+	dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma.len,
+		     host->dma.dir);
+
+	if (stat & MSC_STAT_TIME_OUT_READ) {
+		printk("MMC/SD/SDIO timeout, MMC_STAT 0x%x opcode = %d data flags = 0x%0x blocks = %d blksz = %d\n",
+		       stat,
+		       host->curr_mrq? host->curr_mrq->cmd->opcode : -1,
+		       data->flags,
+		       data->blocks,
+		       data->blksz);
+		data->error = -ETIMEDOUT;
+	} else if (stat & (MSC_STAT_CRC_READ_ERROR | MSC_STAT_CRC_WRITE_ERROR)) {
+		printk("jz-msc%d: MMC/SD/SDIO CRC error, MMC_STAT 0x%x, cmd=%d\n",
+		       host->pdev_id, stat,
+		       host->curr_mrq? host->curr_mrq->cmd->opcode : -1);
+		data->error = -EILSEQ;
+	}
+	/*
+	 * There appears to be a hardware design bug here.  There seems to
+	 * be no way to find out how much data was transferred to the card.
+	 * This means that if there was an error on any block, we mark all
+	 * data blocks as being in error.
+	 */
+	if (data->error == 0)
+		data->bytes_xfered = data->blocks * data->blksz;
+	else
+		data->bytes_xfered = 0;
+
+	TRACE_DATA_DONE();
+
+	// jz_mmc_disable_irq(host, MSC_IMASK_DATA_TRAN_DONE);
+	if (host->curr_mrq->stop) {
+		if ((!(REG_MSC_STAT(host->pdev_id) & MSC_STAT_AUTO_CMD_DONE)) && data->error)
+			jz_mmc_send_stop_cmd(host);
+		else
+			while(!(REG_MSC_STAT(host->pdev_id) & (MSC_STAT_AUTO_CMD_DONE | MSC_STAT_ERR_BITS)) &&
+			      !host->eject) ;
+
+		REG_MSC_CMDAT(host->pdev_id) &= ~(MSC_CMDAT_SEND_AS_STOP);
+	}
+
+	if (host->data_err) {
+		data->bytes_xfered = 0;
+		host->data_err = 0;
+	}
+
+	return 0;
+}
+
+static void jz_mmc_execute_cmd(struct jz_mmc_host *host)
+{
+	struct mmc_request *mrq = host->curr_mrq;
+	struct mmc_data *data = mrq->data;
+	struct mmc_command *cmd = mrq->cmd;
+	unsigned int stat;
+	int err = 0;
+
+	/* mask interrupts */
+	REG_MSC_IMASK(host->pdev_id) = 0xffff;
+	/* clear status */
+	REG_MSC_IREG(host->pdev_id) = 0xffff;
+
+	jz_mmc_set_cmdat(host);
+	REG_MSC_CMD(host->pdev_id) = cmd->opcode;
+	jz_mmc_set_cmdarg(host);
+
+	/* reset NOB and BLKLEN */
+	//REG_MSC_NOB(host->pdev_id) = 0;
+	//REG_MSC_BLKLEN(host->pdev_id) = 0;
+
+	TRACE_CMD_REQ();
+
+	if(data && (data->flags & MMC_DATA_READ))
+		jz_mmc_data_start(host);
+
+	REG_MSC_RESTO(host->pdev_id) = 0xff;
+	/* Send command */
+	REG_MSC_STRPCL(host->pdev_id) = MSC_STRPCL_START_OP;
+	stat = jz_mmc_wait_cmd_done(host);
+	if (cmd->error)
+		goto cmd_err;
+
+	TRACE_DATA_REQ();
+
+	if (jz_mmc_parse_cmd_response(host, stat))
+		goto cmd_err;
+
+	if (host->curr_mrq->data) {
+		int acked = 0;
+		if(host->curr_mrq->data->flags & MMC_DATA_WRITE) {
+			jz_mmc_enable_irq(host, MSC_IMASK_DATA_TRAN_DONE);
+			jz_mmc_data_start(host);
+		}
+
+		err = wait_event_interruptible_timeout(host->data_wait_queue,
+						       ((host->data_ack) || (host->eject)
+							|| (REG_MSC_STAT(host->pdev_id) & WAITMASK)),
+						       6 * HZ);
+		acked = host->data_ack;
+		host->data_ack = 0;
+
+		if (acked)
+			jz_mmc_data_done(host);
+		else {
+			if (err == -ERESTARTSYS) /* user cancelled */
+				cmd->error = -ECANCELED;
+			else if (!err) {
+				printk("Timeout while IRQ_dma, opcode = %d\n", cmd->opcode);
+				printk("REG_MSC_STAT(host->pdev_id) = %x\n", REG_MSC_STAT(host->pdev_id));
+				jz_mmc_dump_regs(host->pdev_id, __LINE__);
+				cmd->error = -ETIMEDOUT;
+			}
+			goto data_wait_err;
+		}
+
+	}
+	return;
+
+ cmd_err:
+#if 0
+	if (host->eject)
+		printk("WARNNING: media eject when sending cmd, opcode = %d\n", cmd->opcode);
+#endif
+ data_wait_err:
+	if (host->curr_mrq->data){
+		host->curr_mrq->data->bytes_xfered = 0;
+
+#if 0
+		if (host->eject)
+			printk("WARNNING: media eject when transfering data, opcode = %d err = %d\n", cmd->opcode, err);
+#endif
+	}
+
+	if (host->eject)
+		cmd->error = -ENOMEDIUM;
+
+	if (host->curr_mrq->data)
+		jz_mmc_data_stop(host);
+}
+
+static irqreturn_t jz_mmc_irq(int irq, void *devid)
+{
+	struct jz_mmc_host *host = devid;
+	unsigned int ireg = 0;
+
+	ireg = REG_MSC_IREG(host->pdev_id);
+	if (ireg) {
+		if (ireg & MSC_IREG_DATA_TRAN_DONE) {
+			jz_mmc_disable_irq(host, MSC_IMASK_DATA_TRAN_DONE);
+			BUG_ON(host->data_ack);
+			host->data_ack = 1;
+			wmb();
+			wake_up_interruptible(&host->data_wait_queue);
+		}
+	}
+
+
+	return IRQ_HANDLED;
+}
+
+static char *msc_trans_irq_name[] = {
+	"msc_trans_0",
+	"msc_trans_1",
+	"msc_trans_2",
+};
+
+static int jz_mmc_msc_init(struct jz_mmc_host *host)
+{
+	int ret = 0;
+
+	jz_mmc_reset(host);
+
+	host->data_ack = 0;
+	init_waitqueue_head(&host->data_wait_queue);
+#if 0
+	init_waitqueue_head(&host->status_check_queue);
+	init_timer(&host->status_check_timer);
+	host->status_check_timer.function = jz_mmc_status_checker;
+#endif
+
+	ret = request_irq(host->irq, jz_mmc_irq, 0, msc_trans_irq_name[host->pdev_id], host);
+	if (ret) {
+		printk(KERN_ERR "MMC/SD: can't request MMC/SD IRQ\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static void jz_mmc_msc_deinit(struct jz_mmc_host *host)
+{
+	free_irq(host->irq, &host);
+}
+
+int jz_mmc_msc_register(struct jz_mmc_msc *msc)
+{
+	if(msc == NULL)
+		return -ENOMEM;
+
+	msc->init = jz_mmc_msc_init;
+	msc->deinit = jz_mmc_msc_deinit;
+	msc->set_clock = jz_mmc_set_clock;
+	msc->execute_cmd = jz_mmc_execute_cmd;
+
+	return 0;
+}
diff --git a/drivers/mmc/host/jzmmc/jz_mmc_pio.c b/drivers/mmc/host/jzmmc/jz_mmc_pio.c
new file mode 100644
index 00000000000..c63f000a925
--- /dev/null
+++ b/drivers/mmc/host/jzmmc/jz_mmc_pio.c
@@ -0,0 +1,100 @@
+#include <linux/mmc/core.h>
+#include <linux/mmc/host.h>
+#include <linux/scatterlist.h>
+#include <linux/kthread.h>
+#include <asm/jzsoc.h>
+#include "include/jz_mmc_dma.h"
+#include "include/jz_mmc_host.h"
+
+#ifdef JZ_MSC_USE_PIO
+
+static int jz_mmc_pio_read(struct jz_mmc_host *host, unsigned int *buf, int len) {
+	int i = 0;
+
+	for (i = 0; i < len; i++) {
+		while ((REG_MSC_STAT(host->pdev_id) & (MSC_STAT_DATA_FIFO_EMPTY | MSC_STAT_TIME_OUT_READ)) &&
+		       !host->eject)
+			;
+		if (host->eject)
+			return -ENOMEDIUM;
+
+		if (REG_MSC_STAT(host->pdev_id) & MSC_STAT_TIME_OUT_READ)
+			return -ETIMEDOUT;
+
+		*buf = REG_MSC_RXFIFO(host->pdev_id);
+		buf++;
+	}
+
+	return 0;
+}
+
+static int jz_mmc_pio_write(struct jz_mmc_host *host, unsigned int *buf, int len) {
+	int i = 0;
+
+	for (i = 0; i < len; i++) {
+		while ((REG_MSC_STAT(host->pdev_id) & MSC_STAT_DATA_FIFO_FULL) && !host->eject)
+			;
+		if (host->eject)
+			return -ENOMEDIUM;
+
+		REG_MSC_TXFIFO(host->pdev_id) = *buf;
+		buf++;
+	}
+
+	return 0;
+}
+
+void jz_mmc_stop_pio(struct jz_mmc_host *host) {
+	while(!host->transfer_end);
+}
+
+static int jz_mmc_data_transfer(void *arg) {
+	struct jz_mmc_host *host = (struct jz_mmc_host *)arg;
+	struct mmc_data *data = host->curr_mrq->data;
+	int is_write = data->flags & MMC_DATA_WRITE;
+	int i = 0;
+	int ret = 0;
+	struct scatterlist *sgentry = NULL;
+	unsigned int *buf = NULL;
+	int len = 0;
+
+	for_each_sg(data->sg, sgentry, data->sg_len, i) {
+		buf = sg_virt(sgentry);
+		len = sg_dma_len(sgentry) >> 2; /* divide by 4 */
+
+		if (is_write)
+			ret = jz_mmc_pio_write(host, buf, len);
+		else
+			ret = jz_mmc_pio_read(host, buf, len);
+		if (ret) {
+			data->error = ret;
+			break;
+		}
+	}
+
+	if (is_write) {
+		if (ret) {
+			host->data_ack = 0;
+			wake_up_interruptible(&host->data_wait_queue);
+		}
+		/* else, DATA_TRANS_DONE interrupt will raise */
+	} else {
+		if (!ret)
+			host->data_ack = 1;
+		else
+			host->data_ack = 0;
+		wake_up_interruptible(&host->data_wait_queue);
+	}
+
+	host->transfer_end = 1;
+
+	return 0;
+}
+
+void jz_mmc_start_pio(struct jz_mmc_host *host) {
+	REG_MSC_CMDAT(host->pdev_id) &= ~MSC_CMDAT_DMA_EN;
+	host->transfer_end = 0;
+	kthread_run(jz_mmc_data_transfer, (void *)host, "msc pio transfer");
+}
+
+#endif /* JZ_MSC_USE_PIO */
diff --git a/drivers/mtd/mtd-utils/nandwrite.c b/drivers/mtd/mtd-utils/nandwrite.c
index 75edfe30ab5..7e9966b2628 100644
--- a/drivers/mtd/mtd-utils/nandwrite.c
+++ b/drivers/mtd/mtd-utils/nandwrite.c
@@ -251,7 +251,11 @@ int main(int argc, char **argv)
 	if (!(meminfo.oobsize == 16 && meminfo.writesize == 512) &&
 			!(meminfo.oobsize == 8 && meminfo.writesize == 256) &&
 			!(meminfo.oobsize == 64 && meminfo.writesize == 2048) &&
-			!(meminfo.oobsize == 128 && meminfo.writesize == 4096)) {
+			!(meminfo.oobsize == 128 && meminfo.writesize == 4096) &&
+			!(meminfo.oobsize == 218 && meminfo.writesize == 4096) &&
+			!(meminfo.oobsize == 256 && meminfo.writesize == 8192) &&
+			!(meminfo.oobsize == 436 && meminfo.writesize == 8192) &&
+			!(meminfo.oobsize == 640 && meminfo.writesize == 8192)) {
 		fprintf(stderr, "Unknown flash (not normal NAND)\n");
 		close(fd);
 		exit(1);
diff --git a/drivers/mtd/mtd-utils/nandwrite_mlc.c b/drivers/mtd/mtd-utils/nandwrite_mlc.c
index 52f5b18e02b..cd85a5eba7c 100644
--- a/drivers/mtd/mtd-utils/nandwrite_mlc.c
+++ b/drivers/mtd/mtd-utils/nandwrite_mlc.c
@@ -248,7 +248,10 @@ int main(int argc, char **argv)
 			!(meminfo.oobsize == 8 && meminfo.writesize == 256) &&
 			!(meminfo.oobsize == 64 && meminfo.writesize == 2048) &&
 			!(meminfo.oobsize == 128 && meminfo.writesize == 4096) &&
-			!(meminfo.oobsize == 256 && meminfo.writesize == 8192)) {
+			!(meminfo.oobsize == 218 && meminfo.writesize == 4096) &&
+			!(meminfo.oobsize == 256 && meminfo.writesize == 8192) &&
+			!(meminfo.oobsize == 436 && meminfo.writesize == 8192) &&
+			!(meminfo.oobsize == 640 && meminfo.writesize == 8192)) {
 		fprintf(stderr, "Unknown flash (not normal NAND)\n");
 		close(fd);
 		exit(1);
diff --git a/drivers/mtd/mtdblock-jz.c b/drivers/mtd/mtdblock-jz.c
index 7ab8e306453..e70fb64698a 100644
--- a/drivers/mtd/mtdblock-jz.c
+++ b/drivers/mtd/mtdblock-jz.c
@@ -139,7 +139,6 @@ static int mtdblock_move_to_another_block(struct mtdblk_dev *mtdblk, int old_phy
 	unsigned short ppb = (1 << (this->phys_erase_shift - this->page_shift) );
 	int new_phys_block, phys_block, i , ret, readfail=0;
 
-//	tmp_block_cache = kmalloc(mtdblk->mtd->erasesize, GFP_KERNEL);
 	tmp_block_cache = mtdblk->block_cache_data;
 
 	if(!tmp_block_cache)
@@ -149,7 +148,11 @@ static int mtdblock_move_to_another_block(struct mtdblk_dev *mtdblk, int old_phy
 	pos = (unsigned long long)old_phys_block<<this->phys_erase_shift;
 	memset(&oobops, 0, sizeof(oobops));
 	oobops.mode = MTD_OOB_AUTO;
+#if !defined(CONFIG_SOC_JZ4760B)
 	oobops.len = mtd->writesize;
+#else
+	oobops.len = mtd->validsize;
+#endif
 	oobops.ooboffs = 2;
 	oobops.ooblen = sizeof(fsoobbuf);
 	oobops.oobbuf = (unsigned char *)&fsoobbuf;
@@ -208,7 +211,6 @@ static int mtdblock_move_to_another_block(struct mtdblk_dev *mtdblk, int old_phy
 		}
 		pos += mtd->writesize;
 	}
-//	kfree(tmp_block_cache);
 	new_phys_block = phys_block;
 	return new_phys_block;
 }
@@ -242,7 +244,6 @@ static int mtdblock_find_free_block (struct mtdblk_dev *mtdblk, int *free_phys_b
 	}
 
 	*free_phys_block = phys_block;
-	//dprintk("find free phys block: %d,free blocks: %d\n", phys_block,zone->free_phys_block);
 
 	memset(&oobops, 0, sizeof(oobops));
 	oobops.mode = MTD_OOB_AUTO;
@@ -315,7 +316,6 @@ static int mtdblock_block_lookup_unmap_entry (struct mtdblk_dev *mtdblk, int vir
 	int phys_block;
 
 	if (zone_ptr->block_lookup[virt_block] & MTDBLOCK_BIT_VALID_ENTRY) {
-		//dprintk("unmap %d -> %d\n", virt_block, zone_ptr->block_lookup[virt_block] & MTDBLOCK_BIT_BLOCK_ADDR);
 		zone_ptr->block_lookup[virt_block] &= ~MTDBLOCK_BIT_VALID_ENTRY;
 		phys_block = zone_ptr->block_lookup[virt_block] & MTDBLOCK_BIT_BLOCK_ADDR;
 		zone_ptr->block_info[phys_block].tag |= MTDBLOCK_BIT_FREE_BLOCK;
@@ -339,7 +339,6 @@ static int mtdblock_address_translate (struct mtdblk_dev *mtdblk, int virt_block
 		return -EINVAL;
 
 	*phys_block = entry & MTDBLOCK_BIT_BLOCK_ADDR;
-	//dprintk("found valid block mapping virt_block: %d -> phys_block: %d\n", virt_block, *phys_block);
 	return 0;
 }
 
@@ -348,7 +347,11 @@ static void mtdblock_init_block_cache(struct mtdblk_dev *mtdblk)
 {
 	struct nand_chip *this = mtdblk->mtd->priv;
 	unsigned short ppb = (1 << (this->phys_erase_shift - this->page_shift));
+#if !defined(CONFIG_SOC_JZ4760B)
 	unsigned short spp = mtdblk->mtd->writesize >> 9 ;  //spp : sectors per page
+#else
+	unsigned short spp = mtdblk->mtd->validsize>> 9 ;  //spp : sectors per page
+#endif
 
 	mtdblk->block_cache_state = STATE_UNUSED;
 	memset(mtdblk->page_state, 0, ppb);
@@ -363,8 +366,11 @@ static void mtdblock_setup_block_cache ( struct mtdblk_dev *mtdblk, int virt_blo
 {
 	struct nand_chip *this = mtdblk->mtd->priv;
 	unsigned short ppb = (1 << (this->phys_erase_shift - this->page_shift));
+#if !defined(CONFIG_SOC_JZ4760B)
 	unsigned short spp = mtdblk->mtd->writesize >> 9 ;  //spp : sectors per page
-
+#else
+	unsigned short spp = mtdblk->mtd->validsize>> 9 ;  //spp : sectors per page
+#endif
 	mtdblk->old_phys_block = old_phys_block;
 	mtdblk->new_phys_block = new_phys_block;
 	mtdblk->virt_block = virt_block;
@@ -388,13 +394,16 @@ static int mtdblock_fill_block_cache(struct mtdblk_dev *mtdblk)
 	unsigned long phys_page;
 	unsigned long long pos;
 	unsigned short ppb = (1 << (this->phys_erase_shift - this->page_shift));
+#if !defined(CONFIG_SOC_JZ4760B)
 	unsigned short sectors_per_page = mtd->writesize >> 9;
+#else
+	unsigned short sectors_per_page = mtd->validsize >> 9;
+#endif
 	unsigned char *page_buf = mtdblk->g_page_buf;
 	static int fill_block1 = 0;
 	static int fill_block2 = 0;
 
 	if (mtdblk->old_phys_block == mtdblk->new_phys_block){
-		//dprintk("Needn't read from new block %d to fill cache.\n",mtdblk->new_phys_block);
 		return 0;
 	}
 
@@ -403,8 +412,11 @@ static int mtdblock_fill_block_cache(struct mtdblk_dev *mtdblk)
 
 	memset(&oobops, 0, sizeof(oobops));
 	oobops.mode = MTD_OOB_AUTO;
+#if !defined(CONFIG_SOC_JZ4760B)
 	oobops.len = mtd->writesize;
-
+#else
+	oobops.len = mtd->validsize;
+#endif
 	phys_block = mtdblk->old_phys_block;
 	for (page = 0; page < ppb; page++) {
 		if ( ! mtdblk->page_state[page]) {
@@ -504,7 +516,11 @@ static int mtdblock_program_block(struct mtdblk_dev *mtdblk, int phys_block)
 	dprintk("W %d-%d\n", mtdblk->virt_block,phys_block);
 	memset(&oobops, 0, sizeof(oobops));
 	oobops.mode = MTD_OOB_AUTO;
+#if !defined(CONFIG_SOC_JZ4760B)
 	oobops.len = mtd->writesize;
+#else
+	oobops.len = mtd->validsize;
+#endif
 	oobops.ooblen = sizeof(fsoobbuf);
 	oobops.ooboffs = 2;
 	oobops.oobbuf = (unsigned char *)&fsoobbuf;
@@ -546,7 +562,11 @@ int mtdblock_flush_cache (struct mtdblk_dev *mtdblk)
 
 	memset(&oobops, 0, sizeof(oobops));
 	oobops.mode = MTD_OOB_AUTO;
+#if !defined(CONFIG_SOC_JZ4760B)
 	oobops.len = mtd->writesize;
+#else
+	oobops.len = mtd->validsize;
+#endif
 	oobops.ooblen = sizeof(fsoobbuf);
 	oobops.ooboffs = 2 ;
 	oobops.oobbuf = (unsigned char *)&fsoobbuf;
@@ -706,15 +726,17 @@ static int do_cached_write (struct mtdblk_dev *mtdblk, unsigned long sector,
 	unsigned long virt_page;
 	int virt_block, old_phys_block, new_phys_block, page_offset;
 	int page_num_in_block;
+#if !defined(CONFIG_SOC_JZ4760B)
 	unsigned short sectors_per_page = mtd->writesize >> 9;
-
+#else
+	unsigned short sectors_per_page = mtd->validsize>> 9;
+#endif
 	virt_page = sector / sectors_per_page;
 	page_offset = sector % sectors_per_page;
 	virt_block = virt_page / ppb;
 	page_num_in_block = virt_page % ppb;
 
 	if (mtdblock_address_translate(mtdblk, virt_block, &old_phys_block) < 0) {
-		//dprintk("virtual block 0x%x not mapped\n",virt_block);
 
 		mutex_lock(&mtdblk->cache_mutex);
 		mtdblock_flush_cache(mtdblk);
@@ -743,10 +765,8 @@ static int do_cached_write (struct mtdblk_dev *mtdblk, unsigned long sector,
 						  old_phys_block);
 				mtdblock_block_lookup_map_entry(mtdblk, virt_block, new_phys_block);
 			} else {
-				//dprintk("cache hit: 0x%x\n", virt_page);
 			}
 		} else {
-			//dprintk("in else:with existing mapping: 0x%x -> 0x%x\n", virt_block, old_phys_block);
 
 			if (mtdblock_find_free_block(mtdblk, &new_phys_block)) {
 				printk("%s ERROR: can't find_free_block!!", __FILE__);
@@ -778,7 +798,11 @@ static int do_cached_read (struct mtdblk_dev *mtdblk, unsigned long sector,
 	int ret, virt_block, phys_block, page_offset;
 	unsigned long virt_page, phys_page, page_num_in_block;
 	unsigned long long pos;
+#if !defined(CONFIG_SOC_JZ4760B)
 	unsigned short sectors_per_page = mtd->writesize >> 9;
+#else
+	unsigned short sectors_per_page = mtd->validsize >> 9;
+#endif
 	int readfail=0;
 
 	virt_page = sector / sectors_per_page;
@@ -792,7 +816,11 @@ static int do_cached_read (struct mtdblk_dev *mtdblk, unsigned long sector,
 		else {
 			memset(&oobops, 0, sizeof(oobops));
 			oobops.mode = MTD_OOB_AUTO;
+#if !defined(CONFIG_SOC_JZ4760B)
 			oobops.len = mtd->writesize;
+#else
+			oobops.len = mtd->validsize;
+#endif
 			oobops.datbuf = mtdblk->page_cache_data;
 
 			phys_page = (mtdblk->old_phys_block * ppb) + (virt_page % ppb);
@@ -838,7 +866,11 @@ read_retry:
 			} else {
 				memset(&oobops, 0, sizeof(oobops));
 				oobops.mode = MTD_OOB_AUTO;
+#if !defined(CONFIG_SOC_JZ4760B)
 				oobops.len = mtd->writesize;
+#else
+				oobops.len = mtd->validsize;
+#endif
 				oobops.datbuf = mtdblk->page_cache_data;
 
 				phys_page = (phys_block * ppb) + (virt_page % ppb);
@@ -965,7 +997,11 @@ static int mtdblock_init_mtdblk(int dev, struct mtd_info *mtd)
 	mtdblk->mtd = mtd;
 	mutex_init(&mtdblk->cache_mutex);
 	ppb = (1 << (this->phys_erase_shift - this->page_shift));
+#if !defined(CONFIG_SOC_JZ4760B)
 	spp = mtdblk->mtd->writesize >> 9 ;  //spp : sectors per page
+#else
+	spp = mtdblk->mtd->validsize>> 9 ;  //spp : sectors per page
+#endif
 
 	if (!jz_mtdblock_cache || !jz_mtdblock_cache[dev]) {
 		if ((mtd->flags) & MTD_NAND_CPU_MODE) {
@@ -985,8 +1021,13 @@ static int mtdblock_init_mtdblk(int dev, struct mtd_info *mtd)
 
 	mtdblk->page_state = kmalloc(ppb, GFP_KERNEL);
 	mtdblk->page_offset_state = kmalloc(ppb*spp, GFP_KERNEL);
+#if !defined(CONFIG_SOC_JZ4760B)
 	mtdblk->page_cache_data = kmalloc(mtdblk->mtd->writesize, GFP_KERNEL);
 	mtdblk->g_page_buf = kmalloc(mtdblk->mtd->writesize, GFP_KERNEL);
+#else
+	mtdblk->page_cache_data = kmalloc(mtdblk->mtd->validsize, GFP_KERNEL);
+	mtdblk->g_page_buf = kmalloc(mtdblk->mtd->validsize, GFP_KERNEL);
+#endif
 
 	if(!mtdblk->page_state ||
 	   !mtdblk->page_offset_state ||
@@ -1105,14 +1146,6 @@ static int mtdblock_open(struct mtd_blktrans_dev *mbd)
 		if (!mtd_blk[i])
 			return 0;
 	}
-#if 0
-	if (mtd->flags & MTD_MTDBLOCK_JZ_INVALID) {
-		dprintk(" mtdblock%d doesn't work over mtdblock-jz.\n",dev);
-		return 0;
-	}
-#endif
-
-	//dprintk(" mtdblock%d works over mtdblock-jz.\n",dev);
 
 	if (mtdblks[dev]) {
 		mtdblks[dev]->count++;
diff --git a/drivers/mtd/mtdpart.c b/drivers/mtd/mtdpart.c
index 5275911d4e9..afb36736c3c 100644
--- a/drivers/mtd/mtdpart.c
+++ b/drivers/mtd/mtdpart.c
@@ -354,6 +354,8 @@ static struct mtd_part *add_one_partition(struct mtd_info *master,
 	slave->mtd.size = part->size;
 	slave->mtd.writesize = master->writesize;
 	slave->mtd.oobsize = master->oobsize;
+	slave->mtd.validsize = master->validsize;
+	slave->mtd.freesize = master->freesize;
 	slave->mtd.oobavail = master->oobavail;
 	slave->mtd.subpage_sft = master->subpage_sft;
 
@@ -528,6 +530,7 @@ int add_mtd_partitions(struct mtd_info *master,
 		       int nbparts)
 {
 	struct mtd_part *slave;
+	struct mtd_partition *temp_part;
 	uint64_t cur_offset = 0;
 	int i;
 
@@ -537,7 +540,8 @@ int add_mtd_partitions(struct mtd_info *master,
 		slave = add_one_partition(master, parts + i, i, cur_offset);
 		if (!slave)
 			return -ENOMEM;
-		cur_offset = slave->offset + slave->mtd.size;
+		temp_part = parts + i + 1;
+		cur_offset = temp_part->offset;
 	}
 
 	return 0;
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 93dc054a508..e7e0d1025a2 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -35,24 +35,52 @@ config MTD_NAND_JZ4760
         help
         Support NAND Flash device on Jz4760 board
 
+config MTD_NAND_JZ4760B
+        tristate "Support NAND Flash device on Jz4760B board"
+        depends on SOC_JZ4760B
+        help
+        Support NAND Flash device on Jz4760B board
+
+config MTD_NAND_JZ4770
+        tristate "Support NAND Flash device on Jz4770 board"
+        depends on SOC_JZ4770
+        help
+        Support NAND Flash device on Jz4770 board
+
+config MTD_NAND_JZ4810
+        tristate "Support NAND Flash device on Jz4810 board"
+        depends on SOC_JZ4810
+        help
+        Support NAND Flash device on Jz4810 board
+
 
 config MTD_NAND_CS2
-	depends on MTD_NAND_JZ4740 || MTD_NAND_JZ4750 || MTD_NAND_JZ4760
+	depends on MTD_NAND_JZ4740 || MTD_NAND_JZ4750 || MTD_NAND_JZ4760 || MTD_NAND_JZ4760B || MTD_NAND_JZ4770 || MTD_NAND_JZ4810
 	bool 'Use NAND on CS2_N of JZSOC'
 	default n
 
 config MTD_NAND_CS3
-	depends on MTD_NAND_JZ4740 || MTD_NAND_JZ4750 || MTD_NAND_JZ4760
+	depends on MTD_NAND_JZ4740 || MTD_NAND_JZ4750 || MTD_NAND_JZ4760 || MTD_NAND_JZ4760B || MTD_NAND_JZ4770 || MTD_NAND_JZ4810
 	bool 'Use NAND on CS3_N of JZSOC'
 	default n
 
 config MTD_NAND_CS4
-	depends on MTD_NAND_JZ4740 || MTD_NAND_JZ4750 || MTD_NAND_JZ4760
+	depends on MTD_NAND_JZ4740 || MTD_NAND_JZ4750 || MTD_NAND_JZ4760 || MTD_NAND_JZ4760B || MTD_NAND_JZ4770 || MTD_NAND_JZ4810
 	bool 'Use NAND on CS4_N of JZSOC'
 	default n
 
+config MTD_NAND_CS5
+	depends on MTD_NAND_JZ4760B
+	bool 'Use NAND on CS5_N of JZSOC'
+	default n
+
+config MTD_NAND_CS6
+	depends on MTD_NAND_JZ4760B
+	bool 'Use NAND on CS6_N of JZSOC'
+	default n
+
 config MTD_NAND_MULTI_PLANE
-	depends on MTD_NAND_JZ4730 || MTD_NAND_JZ4740 || MTD_NAND_JZ4750 || MTD_NAND_JZ4760
+	depends on MTD_NAND_JZ4730 || MTD_NAND_JZ4740 || MTD_NAND_JZ4750 || MTD_NAND_JZ4760 || MTD_NAND_JZ4760B || MTD_NAND_JZ4770 || MTD_NAND_JZ4810
 	bool 'Use multiple planes if the NAND supports'
 	default y
 	help
@@ -74,15 +102,15 @@ config  MTD_NAND_BUS_WIDTH_16
 endchoice
 
 
-if     MTD_NAND_JZ4740 || MTD_NAND_JZ4730 || MTD_NAND_JZ4750 || MTD_NAND_JZ4760
+if     MTD_NAND_JZ4740 || MTD_NAND_JZ4730 || MTD_NAND_JZ4750 || MTD_NAND_JZ4760 || MTD_NAND_JZ4760B || MTD_NAND_JZ4770 || MTD_NAND_JZ4810
 choice
 	prompt "ECC type"
 	default CONFIG_MTD_SW_HM_ECC
-	
+
 config 	MTD_HW_HM_ECC
 	depends on MTD_NAND_JZ4740 || MTD_NAND_JZ4730
 	bool 'Select hardware HM ECC'
-	 
+
 config  MTD_SW_HM_ECC
 	bool 'Select software HM ECC'
 
@@ -95,8 +123,17 @@ config  MTD_HW_BCH_ECC
 	bool 'Select hardware BCH ECC'
 
 config  MTD_HW_BCH_ECC
-	depends on MTD_NAND_JZ4760
+	depends on MTD_NAND_JZ4760 || MTD_NAND_JZ4760B
+	bool 'Select hardware BCH ECC'
+
+config  MTD_HW_BCH_ECC
+	depends on MTD_NAND_JZ4770
 	bool 'Select hardware BCH ECC'
+
+config  MTD_HW_BCH_ECC
+	depends on MTD_NAND_JZ4810
+	bool 'Select hardware BCH ECC'
+
 endchoice
 
 choice
@@ -110,7 +147,7 @@ config  MTD_HW_BCH_4BIT
 config  MTD_HW_BCH_8BIT
         bool '8 bit'
 
-if     MTD_NAND_JZ4760
+if     MTD_NAND_JZ4760 || MTD_NAND_JZ4760B || MTD_NAND_JZ4770 || MTD_NAND_JZ4810
 config  MTD_HW_BCH_12BIT
         bool '12 bit'
 
@@ -130,16 +167,16 @@ config 	MTD_NAND_DMA
 	depends on MTD_HW_BCH_ECC || MTD_HW_RS_ECC
 	bool 'Use DMA mode'
 	help
-	  This enables using DMA for reading and writing NAND flash, if not selected, 
+	  This enables using DMA for reading and writing NAND flash, if not selected,
           then CPU mode is used. DMA is only used for two planes for jz4740.
 
 config  MTD_NAND_DMABUF
 	depends on MTD_NAND_DMA && MTD_HW_BCH_ECC
 	bool 'use DMA buffer in NAND driver'
 	help
-          It's better to say NO. If saying yes, DMA buffers will be allocated for 
-          NAND reading and writing in NAND driver instead of upper layer. It's 
-          slower. Just usable on CS1_N now. By saying NO, upper buffers will be 
+          It's better to say NO. If saying yes, DMA buffers will be allocated for
+          NAND reading and writing in NAND driver instead of upper layer. It's
+          slower. Just usable on CS1_N now. By saying NO, upper buffers will be
           used as DMA buffer. It's faster, but kmalloc instead of vmalloc is required.
 endif
 
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 7cb1f0bc7ae..f5045a85909 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -44,5 +44,8 @@ obj-$(CONFIG_MTD_NAND_JZ4730)		+= jz4730_nand.o
 obj-$(CONFIG_MTD_NAND_JZ4740)		+= jz4740_nand.o
 obj-$(CONFIG_MTD_NAND_JZ4750)		+= jz4750_nand.o
 obj-$(CONFIG_MTD_NAND_JZ4760)		+= jz4760_nand.o
+obj-$(CONFIG_MTD_NAND_JZ4760B)		+= jz4760b_nand.o
+obj-$(CONFIG_MTD_NAND_JZ4770)		+= jz4770_nand.o
+obj-$(CONFIG_MTD_NAND_JZ4810)		+= jz4810_nand.o
 
 nand-objs := nand_base.o nand_bbt.o
diff --git a/drivers/mtd/nand/jz4750_nand.c b/drivers/mtd/nand/jz4750_nand.c
index e40dcd40156..fedc828aa91 100644
--- a/drivers/mtd/nand/jz4750_nand.c
+++ b/drivers/mtd/nand/jz4750_nand.c
@@ -1439,8 +1439,11 @@ static int jz4750_nand_dma_init(struct mtd_info *mtd)
 	desc = dma_desc_nand_prog;

 	next = (CPHYSADDR((u32)dma_desc_nand_prog) + sizeof(jz_dma_desc_8word)) >> 4;

 	desc->dcmd =

-	    DMAC_DCMD_SAI | DMAC_DCMD_DAI | DMAC_DCMD_RDIL_IGN | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_8 |

-	    DMAC_DCMD_DS_NAND | DMAC_DCMD_LINK;

+	    DMAC_DCMD_SAI | DMAC_DCMD_RDIL_IGN | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_8 |

+	    DMAC_DCMD_DS_NAND | DMAC_DCMD_LINK;	//for unshare mode, no DMAC_DCMD_DAI

+	if (is_share_mode()) {

+		desc->dcmd |= DMAC_DCMD_DAI;

+	}

 #if defined(CONFIG_MTD_NAND_DMABUF)

 	desc->dsadr = CPHYSADDR((u32)prog_buf);	/* DMA source address */

 #endif

@@ -1453,8 +1456,11 @@ static int jz4750_nand_dma_init(struct mtd_info *mtd)
 	desc++;

 	next = (CPHYSADDR((u32)dma_desc_nand_cmd_pgprog)) >> 4;

 	desc->dcmd =

-	    DMAC_DCMD_SAI | DMAC_DCMD_DAI | DMAC_DCMD_RDIL_IGN | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_8 |

+	    DMAC_DCMD_SAI | DMAC_DCMD_RDIL_IGN | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_8 |

 	    DMAC_DCMD_DS_NAND | DMAC_DCMD_LINK;

+	if (is_share_mode()) {

+		desc->dcmd |= DMAC_DCMD_DAI;

+	}

 #if defined(CONFIG_MTD_NAND_DMABUF)

 	desc->dsadr = CPHYSADDR((u32)oobbuf);                	/* DMA source address */

 #endif

@@ -1507,8 +1513,11 @@ static int jz4750_nand_dma_init(struct mtd_info *mtd)
 	desc = dma_desc_nand_read;

 	next = (CPHYSADDR((u32)dma_desc_nand_read) + sizeof(jz_dma_desc_8word)) >> 4;

 	desc->dcmd =

-	    DMAC_DCMD_SAI | DMAC_DCMD_DAI | DMAC_DCMD_RDIL_IGN | DMAC_DCMD_SWDH_8 | DMAC_DCMD_DWDH_32 |

-	    DMAC_DCMD_DS_NAND | DMAC_DCMD_LINK;

+	    DMAC_DCMD_DAI | DMAC_DCMD_RDIL_IGN | DMAC_DCMD_SWDH_8 | DMAC_DCMD_DWDH_32 |

+	    DMAC_DCMD_DS_NAND | DMAC_DCMD_LINK;		//for unshare mode, no DMAC_DCMD_SAI

+	if (is_share_mode()) {

+		desc->dcmd |= DMAC_DCMD_SAI;

+	}

 	desc->dsadr = CPHYSADDR((u32)(chip->IO_ADDR_R));	/* DMA source address */

 #if defined(CONFIG_MTD_NAND_DMABUF)

 	desc->dtadr = CPHYSADDR((u32)read_buf);	/* DMA target address */

@@ -1521,8 +1530,11 @@ static int jz4750_nand_dma_init(struct mtd_info *mtd)
 	desc++;

 	next = (CPHYSADDR((u32)dma_desc_bch_ddr)) >> 4;

 	desc->dcmd =

-	    DMAC_DCMD_SAI | DMAC_DCMD_DAI | DMAC_DCMD_RDIL_IGN | DMAC_DCMD_SWDH_8 | DMAC_DCMD_DWDH_32 |

+	    DMAC_DCMD_DAI | DMAC_DCMD_RDIL_IGN | DMAC_DCMD_SWDH_8 | DMAC_DCMD_DWDH_32 |

 	    DMAC_DCMD_DS_NAND | DMAC_DCMD_LINK;

+	if (is_share_mode()) {

+		desc->dcmd |= DMAC_DCMD_SAI;

+	}

 	desc->dsadr = CPHYSADDR((u32)(chip->IO_ADDR_R));	/* DMA source address */

 #if defined(CONFIG_MTD_NAND_DMABUF)

 	desc->dtadr = CPHYSADDR((u32)oobbuf);	/* DMA target address */

diff --git a/drivers/mtd/nand/jz4760_nand.c b/drivers/mtd/nand/jz4760_nand.c
index c894254bc91..bf04fc86d70 100644
--- a/drivers/mtd/nand/jz4760_nand.c
+++ b/drivers/mtd/nand/jz4760_nand.c
@@ -90,9 +90,9 @@
 #endif

 

 #define NAND_DATA_PORT1	       0xBA000000	/* read-write area in static bank 1 */

-#define NAND_DATA_PORT2	       0xB4000000	/* read-write area in static bank 2 */

-#define NAND_DATA_PORT3	       0xAC000000	/* read-write area in static bank 3 */

-#define NAND_DATA_PORT4	       0xA8000000	/* read-write area in static bank 4 */

+#define NAND_DATA_PORT2	       0xB8000000	/* read-write area in static bank 2 */

+#define NAND_DATA_PORT3	       0xB7000000	/* read-write area in static bank 3 */

+#define NAND_DATA_PORT4	       0xB6000000	/* read-write area in static bank 4 */

 

 #define NAND_ADDR_OFFSET       0x00800000      /* address port offset for unshare mode */

 #define NAND_CMD_OFFSET        0x00400000      /* command port offset for unshare mode */

@@ -148,7 +148,7 @@ extern char all_use_planes;
 /*

  * Define partitions for flash devices

  */

-#if defined(CONFIG_JZ4760_CYGNUS) || defined(CONFIG_JZ4760_LEPUS)

+#if defined(CONFIG_JZ4760_CYGNUS) || defined(CONFIG_JZ4760_LEPUS) || defined(CONFIG_JZ4760B_CYGNUS) || defined(CONFIG_JZ4760B_LEPUS) || defined(CONFIG_JZ4760_HTB80)

 static struct mtd_partition partition_info[] = {

 	{name:"NAND BOOT partition",

 	 offset:0 * 0x100000LL,

@@ -191,7 +191,7 @@ static int partition_reserved_badblocks[] = {
 };				/* reserved blocks of mtd5 */

 #endif				/* CONFIG_JZ4760_CYGNUS || CONFIG_JZ4760_LEPUS */

 

-#if defined(CONFIG_JZ4760_ALTAIR)

+#if defined(CONFIG_JZ4760_ALTAIR) || defined(CONFIG_JZ4760B_ALTAIR)

 

 /* Reserve 32MB for bootloader, splash1, splash2 and radiofw */

 #define MISC_OFFSET		(32  * 0x100000LL)

@@ -499,7 +499,11 @@ static int jzsoc_nand_bch_correct_data(struct mtd_info *mtd, u_char * dat, u_cha
 						* (i+1) the error bit index.

 						* errs[i>>1] >> (((i + 1) % 2) << 4) means when error

 						* bit index is even, errs[i>>1] >> 16*/

+#if defined(CONFIG_MTD_NAND_JZ4760B)

+						bch_correct(mtd, dat, ((errs[i>>1] >> ((i % 2) << 4))) & BCH_ERR_INDEX_MASK);

+#else

 						bch_correct(mtd, dat, ((errs[i>>1] >> (((i + 1) % 2) << 4))) & BCH_ERR_INDEX_MASK);

+#endif

 					}

 				}

 			}

@@ -1011,8 +1015,12 @@ static int nand_read_page_hwecc_bch0(struct mtd_info *mtd, struct nand_chip *chi
 #if USE_PN

 	REG_BDMAC_DRSR(nand_dma_chan) = BDMAC_DRSR_RS_AUTO;

 #else

+#if defined(CONFIG_MTD_NAND_JZ4760B)

+	REG_BDMAC_DRSR(nand_dma_chan) = BDMAC_DRSR_RS_NAND0;

+#else

 	REG_BDMAC_DRSR(nand_dma_chan) = BDMAC_DRSR_RS_NAND;

 #endif

+#endif

 	REG_BDMAC_DRSR(bch_dma_chan) = BDMAC_DRSR_RS_BCH_DEC;

 

 	/* Enable DMA */

@@ -1315,17 +1323,6 @@ static irqreturn_t nand_dma_irq(int irq, void *dev_id)
 		printk("DMA address error!\n");

 	}

 

-#if 0

-

-	while (!__bdmac_channel_transmit_end_detected(dma_chan));

-

-	if (__bdmac_channel_count_terminated_detected(dma_chan)) {

-		dprintk("DMA CT\n");

-		__bdmac_channel_clear_count_terminated(dma_chan);

-		wakeup = 0;

-	}

-#endif

-

 	if (__bdmac_channel_transmit_end_detected(dma_chan)) {

 		dprintk("DMA TT\n");

 		REG_BDMAC_DCCSR(dma_chan) &= ~BDMAC_DCCSR_EN;	/* disable DMA */

@@ -1620,7 +1617,11 @@ static int jz4760_nand_dma_init(struct mtd_info *mtd)
 	desc->dtadr = CPHYSADDR((u32)dummy);        	/* DMA target address, the content is useless */

 	desc->dcnt = 1;             	/* size: 1 word */

 	desc->dnt = 1;

+#if defined(CONFIG_MTD_NAND_JZ4760B)

+	desc->dreqt = BDMAC_DRSR_RS_NAND0;

+#else

 	desc->dreqt = BDMAC_DRSR_RS_NAND;

+#endif

 	dprintk("1cmd:%x sadr:%x tadr:%x dadr:%x\n", desc->dcmd, desc->dsadr, desc->dtadr, desc->ddadr);

 

 	/* eccsteps*2 + 2 + 2 + 2:

@@ -1665,7 +1666,11 @@ static int jz4760_nand_dma_init(struct mtd_info *mtd)
 	desc->dtadr = CPHYSADDR((u32)read_buf);	/* DMA target address */

 #endif

 	desc->dcnt = pagesize / DIV_DS_NAND;	/* size: eccsize bytes */

+#if defined(CONFIG_MTD_NAND_JZ4760B)

+	desc->dreqt = BDMAC_DRSR_RS_NAND0;

+#else

 	desc->dreqt = BDMAC_DRSR_RS_NAND;

+#endif

 	desc->ddadr = next;

 	dprintk("cmd:%x sadr:%x tadr:%x dadr:%x\n", desc->dcmd, desc->dsadr, desc->dtadr, desc->ddadr);

 

diff --git a/drivers/mtd/nand/jz4760b_nand.c b/drivers/mtd/nand/jz4760b_nand.c
new file mode 100644
index 00000000000..261c5ac8814
--- /dev/null
+++ b/drivers/mtd/nand/jz4760b_nand.c
@@ -0,0 +1,2173 @@
+/*
+ * linux/drivers/mtd/nand/jz4760_nand.c
+ *
+ * JZ4760 NAND driver
+ *
+ * Copyright (c) 2005 - 2007 Ingenic Semiconductor Inc.
+ * Author: <lhhuang@ingenic.cn>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+*/
+
+/*
+	NOTE: The OOB size is align with 4 bytes now. 
+	      If your nand's OOB size not align with 4,and all of the data in OOB area is valid,
+	      please FIXUP the value of desc->dcnt when init the write/read dma descs, in jz4760_nand_dma_init func.
+	<hpyang@ingenic.cn> 2011/04/02
+*/
+
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/nand_ecc.h>
+#include <linux/mtd/partitions.h>
+
+#include <asm/io.h>
+#include <asm/jzsoc.h>
+
+#define BDMAC_DCMD_DS_NAND		BDMAC_DCMD_DS_64BYTE
+#define DIV_DS_NAND				64
+
+#define BDMAC_DCMD_DS_BCH		BDMAC_DCMD_DS_64BYTE
+#define DIV_DS_BCH           	64
+
+#ifdef CONFIG_MTD_NAND_BUS_WIDTH_16
+#define BDMAC_DCMD_DWDH_XX	BDMAC_DCMD_DWDH_16
+#else
+#define BDMAC_DCMD_DWDH_XX	BDMAC_DCMD_DWDH_8
+#endif
+
+#define USE_DIRECT	1
+#define	USE_PN		0
+#define	USE_COUNTER	0
+#define	COUNT_0		0	/* 1:count the number of 1; 0:count the number of 0 */
+#define PN_ENABLE			(1 | PN_RESET)
+#define PN_DISABLE			0
+#define PN_RESET			(1 << 1)
+#define COUNTER_ENABLE  	((1 << 3) | COUNTER_RESET)
+#define COUNTER_DISABLE 	(0 << 3)
+#define COUNTER_RESET   	(1 << 5)
+#define COUNT_FOR_1			(0 << 4)
+#define COUNT_FOR_0			(1 << 4)
+
+#define DMA_DESC_FLUSH_SIZE	2048		// Make sure all the dma desc buffer we used be flushed.
+
+#define DEBUG1    0
+
+#if DEBUG1
+#define	dprintk(n,x...) printk(n,##x)
+#else
+#define	dprintk(n,x...)
+#endif
+
+#if defined(CONFIG_MTD_HW_BCH_24BIT)
+#define __ECC_ENCODING __ecc_encoding_24bit
+#define __ECC_DECODING __ecc_decoding_24bit
+#define ERRS_SIZE       13	/* 13 words */
+#define PAR_SIZE       	78	/* 24-bit */
+#elif defined(CONFIG_MTD_HW_BCH_20BIT)
+#define __ECC_ENCODING __ecc_encoding_20bit
+#define __ECC_DECODING __ecc_decoding_20bit
+#define ERRS_SIZE       11	/* 11 words */
+#define PAR_SIZE       	65	/* 20-bit */
+#elif defined(CONFIG_MTD_HW_BCH_16BIT)
+#define __ECC_ENCODING __ecc_encoding_16bit
+#define __ECC_DECODING __ecc_decoding_16bit
+#define ERRS_SIZE       9	/* 9 words */
+#define PAR_SIZE       	52	/* 16-bit */
+#elif defined(CONFIG_MTD_HW_BCH_12BIT)
+#define __ECC_ENCODING __ecc_encoding_12bit
+#define __ECC_DECODING __ecc_decoding_12bit
+#define ERRS_SIZE       7	/* 7 words */
+#define PAR_SIZE       	39	/* 12-bit */
+#elif defined(CONFIG_MTD_HW_BCH_8BIT)
+#define __ECC_ENCODING __ecc_encoding_8bit
+#define __ECC_DECODING __ecc_decoding_8bit
+#define ERRS_SIZE       5	/* 5 words */
+#define PAR_SIZE       	26	/* 8-bit */
+#else
+#define __ECC_ENCODING __ecc_encoding_4bit
+#define __ECC_DECODING __ecc_decoding_4bit
+#define ERRS_SIZE       3	/* 3 words */
+#define PAR_SIZE       	13	/* 4-bit */
+#endif
+
+#define NAND_DATA_PORT1	       0xBA000000	/* read-write area in static bank 1 */
+#define NAND_DATA_PORT2	       0xB4000000	/* read-write area in static bank 2 */
+#define NAND_DATA_PORT3	       0xAC000000	/* read-write area in static bank 3 */
+#define NAND_DATA_PORT4	       0xA8000000	/* read-write area in static bank 4 */
+
+#define NAND_ADDR_OFFSET       0x00800000      /* address port offset for unshare mode */
+#define NAND_CMD_OFFSET        0x00400000      /* command port offset for unshare mode */
+
+#if defined(CONFIG_MTD_NAND_DMA)
+#define  USE_IRQ      1
+enum {
+	NAND_NONE,
+	NAND_PROG,
+	NAND_READ
+};
+static volatile u8 nand_status;
+static volatile int dma_ack = 0;
+static volatile int dma_ack1 = 0;
+static char nand_dma_chan = 1;	/* fixed to channel 1 */
+static char bch_dma_chan = 0;	/* fixed to channel 0 */
+static u32 *errs;
+static u32 oob_bch_errs[NAND_MAX_ERRSIZE];
+static jz_bdma_desc_8word *dma_desc_enc, *dma_desc_enc1, *dma_desc_dec, *dma_desc_dec1,
+			  *dma_desc_nand_prog, *dma_desc_nand_read;
+#if USE_PN
+static jz_bdma_desc_8word *dma_desc_pPN, *dma_desc_rPN;
+#endif
+static u32 *pval_nand_ddr;
+static u32 *pval_nand_cmd_pgprog; /* for sending 0x11 or 0x10 when programing*/
+#if defined(CONFIG_MTD_NAND_DMABUF)
+u8 *prog_buf, *read_buf;
+#endif
+#if USE_PN
+static u32 *pn_buf;
+#endif
+DECLARE_WAIT_QUEUE_HEAD(nand_prog_wait_queue);
+DECLARE_WAIT_QUEUE_HEAD(nand_read_wait_queue);
+#endif		/* CONFIG_MTD_NAND_DMA */
+
+struct buf_be_corrected {
+	u8 *data;
+	u8 *oob;
+};
+
+static u32 addr_offset;
+static u32 cmd_offset;
+
+extern int global_page; /* for two-plane operations */
+extern int global_mafid; /* ID of manufacture */
+
+/*
+ * MTD structure for JzSOC board
+ */
+static struct mtd_info *jz_mtd = NULL;
+extern struct mtd_info *jz_mtd1;
+extern char all_use_planes;
+
+/*
+ * Define partitions for flash devices
+ */
+#if defined(CONFIG_JZ4760_CYGNUS) || defined(CONFIG_JZ4760_LEPUS) || defined(CONFIG_JZ4760B_CYGNUS) || defined(CONFIG_JZ4760B_LEPUS) || defined(CONFIG_JZ4760_HTB80)
+static struct mtd_partition partition_info[] = {
+	{name:"NAND BOOT partition",
+	 offset:0 * 0x100000LL,
+         real_size:4 * 0x100000LL,
+         use_planes: 0},
+	{name:"NAND KERNEL partition",
+	 offset:4 * 0x100000LL,
+         real_size:4 * 0x100000LL,
+	 use_planes: 0},
+	{name:"NAND ROOTFS partition",
+	 offset:8 * 0x100000LL,
+	 real_size:504 * 0x100000LL,
+	 use_planes: 0},
+	{name:"NAND DATA partition",
+	 offset:512 * 0x100000LL,
+         real_size:512 * 0x100000LL,
+         use_planes: 1},
+	{name:"NAND VFAT partition",
+	 offset:1024 * 0x100000LL,
+         real_size:1024 * 0x100000LL,
+         use_planes: 1},
+};
+
+/* Define max reserved bad blocks for each partition.
+ * This is used by the mtdblock-jz.c NAND FTL driver only.
+ *
+ * The NAND FTL driver reserves some good blocks which can't be
+ * seen by the upper layer. When the bad block number of a partition
+ * exceeds the max reserved blocks, then there is no more reserved
+ * good blocks to be used by the NAND FTL driver when another bad
+ * block generated.
+ */
+static int partition_reserved_badblocks[] = {
+	2,			/* reserved blocks of mtd0 */
+	2,			/* reserved blocks of mtd1 */
+	10,			/* reserved blocks of mtd2 */
+	10,			/* reserved blocks of mtd3 */
+	20,			/* reserved blocks of mtd4 */
+	20
+};				/* reserved blocks of mtd5 */
+#endif				/* CONFIG_JZ4760_CYGNUS || CONFIG_JZ4760_LEPUS */
+
+#if defined(CONFIG_JZ4760_ALTAIR) || defined(CONFIG_JZ4760B_ALTAIR)
+
+/* Reserve 32MB for bootloader, splash1, splash2 and radiofw */
+#define MISC_OFFSET		(32  * 0x100000LL)
+
+#define MISC_SIZE		(  1 * 0x100000LL)
+#define RECOVERY_SIZE		(  5 * 0x100000LL)
+#define BOOT_SIZE		(  4 * 0x100000LL)
+#define SYSTEM_SIZE		(90 * 0x100000LL)
+#define USERDATA_SIZE		(90 * 0x100000LL)
+#define CACHE_SIZE		(32 * 0x100000LL)
+#define STORAGE_SIZE		(MTDPART_SIZ_FULL)
+
+static struct mtd_partition partition_info[] = {
+
+	/* Android partitions:
+	 *
+	 * misc@mtd0 :      raw
+	 * recovery@mtd1:   raw
+	 * boot@mtd2:       raw
+	 * system@mtd3:     yaffs2
+	 * userdata@mtd4:   yaffs2
+	 * cache@mtd5:      yaffs2
+	 * storage@mtd6:    vfat
+	 */
+	{name:       "misc",
+offset:     MISC_OFFSET,
+	    real_size:       MISC_SIZE,
+	    use_planes: 0},
+	{name:       "recovery",
+offset:     (MISC_OFFSET+MISC_SIZE),
+	    real_size:       RECOVERY_SIZE,
+	    use_planes: 0},
+	{name:       "boot",
+offset:     (MISC_OFFSET+MISC_SIZE+RECOVERY_SIZE),
+	    real_size:       BOOT_SIZE,
+	    use_planes: 0},
+	{name:       "system",
+offset:     (MISC_OFFSET+MISC_SIZE+RECOVERY_SIZE+BOOT_SIZE),
+	    real_size:       SYSTEM_SIZE,
+	    use_planes: 0},
+	{name:       "userdata",
+offset:     (MISC_OFFSET+MISC_SIZE+RECOVERY_SIZE+BOOT_SIZE+SYSTEM_SIZE),
+	    real_size:       USERDATA_SIZE,
+	    use_planes: 0},
+	{name:       "cache",
+offset:     (MISC_OFFSET+MISC_SIZE+RECOVERY_SIZE+BOOT_SIZE+SYSTEM_SIZE+USERDATA_SIZE),
+	    real_size:       CACHE_SIZE,
+	    use_planes: 0},
+	{name:       "storage",
+offset:     (MISC_OFFSET+MISC_SIZE+RECOVERY_SIZE+BOOT_SIZE+SYSTEM_SIZE+USERDATA_SIZE+CACHE_SIZE),
+	    real_size:       STORAGE_SIZE,
+	    use_planes: 0}
+};
+
+/* Define max reserved bad blocks for each partition.
+ * This is used by the mtdblock-jz.c NAND FTL driver only.
+ *
+ * The NAND FTL driver reserves some good blocks which can't be
+ * seen by the upper layer. When the bad block number of a partition
+ * exceeds the max reserved blocks, then there is no more reserved
+ * good blocks to be used by the NAND FTL driver when another bad
+ * block generated.
+ */
+static int partition_reserved_badblocks[] = {
+	10,			/* reserved blocks of mtd0 */
+	10,			/* reserved blocks of mtd1 */
+	10,			/* reserved blocks of mtd2 */
+	10,			/* reserved blocks of mtd3 */
+	10,			/* reserved blocks of mtd4 */
+	10,			/* reserved blocks of mtd5 */
+	12			/* reserved blocks of mtd6 */
+};
+#endif	                        /* CONFIG_JZ4760_ALTAIR */
+
+/*-------------------------------------------------------------------------
+ * Following three functions are exported and used by the mtdblock-jz.c
+ * NAND FTL driver only.
+ */
+
+extern void buffer_dump(uint8_t *buffer, int length, const char *comment, char *file, char *function, int line);
+
+static void calc_partition_size(struct mtd_info *mtd)
+{
+	int total_partitions,count;
+	struct nand_chip *this = mtd->priv;
+	total_partitions = sizeof(partition_info) / sizeof(struct mtd_partition);
+	for(count = 0; count < total_partitions; count++){
+		if(partition_info[count].real_size > 0x800000LL){
+			partition_info[count].size = partition_info[count].real_size -   \
+						     (partition_info[count].real_size >> this->page_shift) * mtd->freesize;
+			if(mtd_mod_by_eb(partition_info[count].size, mtd)){
+				partition_info[count].size -= mtd_mod_by_eb(partition_info[count].size, mtd); 
+			}
+		}else{
+			partition_info[count].size = partition_info[count].real_size;
+		}
+	}
+}
+
+unsigned short get_mtdblock_write_verify_enable(void)
+{
+#ifdef CONFIG_MTD_MTDBLOCK_WRITE_VERIFY_ENABLE
+	return 1;
+#endif
+	return 0;
+}
+
+EXPORT_SYMBOL(get_mtdblock_write_verify_enable);
+
+unsigned short get_mtdblock_oob_copies(void)
+{
+	return CONFIG_MTD_OOB_COPIES;
+}
+
+EXPORT_SYMBOL(get_mtdblock_oob_copies);
+
+int *get_jz_badblock_table(void)
+{
+	return partition_reserved_badblocks;
+}
+
+EXPORT_SYMBOL(get_jz_badblock_table);
+
+/*-------------------------------------------------------------------------*/
+
+static void jz_hwcontrol(struct mtd_info *mtd, int dat, u32 ctrl)
+{
+	struct nand_chip *this = (struct nand_chip *)(mtd->priv);
+	u32 nandaddr = (u32)this->IO_ADDR_W;
+	extern u8 nand_nce;  /* defined in nand_base.c, indicates which chip select is used for current nand chip */
+
+	if (ctrl & NAND_CTRL_CHANGE) {
+		if (ctrl & NAND_NCE) {
+			switch (nand_nce) {
+				case NAND_NCE1:
+					this->IO_ADDR_W = this->IO_ADDR_R = (void __iomem *)NAND_DATA_PORT1;
+					REG_NEMC_NFCSR = NEMC_NFCSR_NFCE1 | NEMC_NFCSR_NFE1;
+					break;
+				case NAND_NCE2:
+					this->IO_ADDR_W = this->IO_ADDR_R = (void __iomem *)NAND_DATA_PORT2;
+					REG_NEMC_NFCSR = NEMC_NFCSR_NFCE2 | NEMC_NFCSR_NFE2;
+					break;
+				case NAND_NCE3:
+					this->IO_ADDR_W = this->IO_ADDR_R = (void __iomem *)NAND_DATA_PORT3;
+					REG_NEMC_NFCSR = NEMC_NFCSR_NFCE3 | NEMC_NFCSR_NFE3;
+					break;
+				case NAND_NCE4:
+					this->IO_ADDR_W = this->IO_ADDR_R = (void __iomem *)NAND_DATA_PORT4;
+					REG_NEMC_NFCSR = NEMC_NFCSR_NFCE4 | NEMC_NFCSR_NFE4;
+					break;
+				default:
+					printk("error: no nand_nce 0x%x\n",nand_nce);
+					break;
+			}
+		} else {
+
+			REG_NEMC_NFCSR = 0;
+		}
+
+		if (ctrl & NAND_ALE)
+			nandaddr = (u32)((u32)(this->IO_ADDR_W) | addr_offset);
+		else
+			nandaddr = (u32)((u32)(this->IO_ADDR_W) & ~addr_offset);
+		if (ctrl & NAND_CLE)
+			nandaddr = (u32)(nandaddr | cmd_offset);
+		else
+			nandaddr = (u32)(nandaddr & ~cmd_offset);
+	}
+
+	this->IO_ADDR_W = (void __iomem *)nandaddr;
+	if (dat != NAND_CMD_NONE) {
+		writeb(dat, this->IO_ADDR_W);
+		/* printk("write cmd:0x%x to 0x%x\n",dat,(u32)this->IO_ADDR_W); */
+	}
+}
+
+static int jz_device_ready(struct mtd_info *mtd)
+{
+	int ready, wait = 10;
+	while (wait--);
+	ready = ((REG_GPIO_PXPIN(0) & 0x00100000) ? 1 : 0);
+	return ready;
+}
+
+/*
+ * NEMC setup
+ */
+static void jz_device_setup(void)
+{
+	// PORT 0:
+	// PORT 1:
+	// PORT 2:
+	// PIN/BIT N		FUNC0		FUNC1
+	//	21		CS1#		-
+	//	22		CS2#		-
+	//	23		CS3#		-
+	//	24		CS4#		-
+	//	25		CS5#		-
+	//	26		CS6#		-
+#define GPIO_CS2_N (32*0+22)
+#define GPIO_CS3_N (32*0+23)
+#define GPIO_CS4_N (32*0+24)
+#define GPIO_CS5_N (32*0+25)
+#define GPIO_CS6_N (32*0+26)
+
+#ifdef CONFIG_MTD_NAND_BUS_WIDTH_16
+#define SMCR_VAL   0x11444440
+	//#define SMCR_VAL   0x0fff7740  //slowest
+	__gpio_as_nand_16bit(1);
+#else
+#define SMCR_VAL   0x11444400
+	//#define SMCR_VAL   0x0fff7700  //slowest
+	__gpio_as_nand_8bit(1);
+#endif
+
+	/* Read/Write timings */
+	REG_NEMC_SMCR1 = SMCR_VAL;
+
+#if defined(CONFIG_MTD_NAND_CS2)
+	__gpio_as_func0(GPIO_CS2_N);
+
+	/* Read/Write timings */
+	REG_NEMC_SMCR2 = SMCR_VAL;
+#endif
+
+#if defined(CONFIG_MTD_NAND_CS3)
+	__gpio_as_func0(GPIO_CS3_N);
+
+	/* Read/Write timings */
+	REG_NEMC_SMCR3 = SMCR_VAL;
+#endif
+
+#if defined(CONFIG_MTD_NAND_CS4)
+	__gpio_as_func0(GPIO_CS4_N);
+
+	/* Read/Write timings */
+	REG_NEMC_SMCR4 = SMCR_VAL;
+#endif
+
+#if defined(CONFIG_MTD_NAND_CS5)
+	__gpio_as_func0(GPIO_CS5_N);
+
+	/* Read/Write timings */
+	REG_NEMC_SMCR5 = SMCR_VAL;
+#endif
+
+#if defined(CONFIG_MTD_NAND_CS6)
+	__gpio_as_func0(GPIO_CS6_N);
+
+	/* Read/Write timings */
+	REG_NEMC_SMCR6 = SMCR_VAL;
+#endif
+}
+
+#ifdef CONFIG_MTD_HW_BCH_ECC
+
+static void jzsoc_nand_enable_bch_hwecc(struct mtd_info *mtd, int mode)
+{
+	struct nand_chip *this = (struct nand_chip *)(mtd->priv);
+	int eccsize = this->ecc.size;
+
+	REG_BCH_INTS = 0xffffffff;
+	if (mode == NAND_ECC_READ) {
+		__ECC_DECODING();
+		__ecc_cnt_dec(eccsize * 2 + PAR_SIZE);
+#if defined(CONFIG_MTD_NAND_DMA)
+		__ecc_dma_enable();
+#endif
+	}
+
+	if (mode == NAND_ECC_WRITE) {
+		__ECC_ENCODING();
+		__ecc_cnt_enc(eccsize * 2);
+#if defined(CONFIG_MTD_NAND_DMA)
+		__ecc_dma_enable();
+#endif
+	}
+}
+
+/**
+ * bch_correct
+ * @dat:        data to be corrected
+ * @idx:        the index of error bit in an eccsize
+ */
+static void bch_correct(struct mtd_info *mtd, u8 * dat, int idx)
+{
+	struct nand_chip *this = (struct nand_chip *)(mtd->priv);
+	int eccsize = this->ecc.size;
+	int i, bit;		/* the 'bit' of i byte is error */
+
+	i = (idx - 1) >> 3;
+	bit = (idx - 1) & 0x7;
+
+	dprintk("error:i=%d, bit=%d\n",i,bit);
+	if (i < eccsize) {
+		((struct buf_be_corrected *)dat)->data[i] ^= (1 << bit);
+	}
+}
+
+#if defined(CONFIG_MTD_NAND_DMA)
+
+/**
+ * jzsoc_nand_bch_correct_data
+ * @mtd:	mtd info structure
+ * @dat:        data to be corrected
+ * @errs0:      pointer to the dma target buffer of bch decoding which stores BHINTS and
+ *              BHERR0~3(8-bit BCH) or BHERR0~1(4-bit BCH)
+ * @calc_ecc:   no used
+ */
+static int jzsoc_nand_bch_correct_data(struct mtd_info *mtd, u_char * dat, u_char * errs0, u_char * calc_ecc)
+{
+	u32 stat, i;
+	u32 *errs = (u32 *)errs0;
+	int ret = 0;
+
+	if (REG_BDMAC_DCCSR(0) & BDMAC_DCCSR_BERR) {
+		stat = errs[0];
+		dprintk("stat=%x err0:%x err1:%x \n", stat, errs[1], errs[2]);
+
+		if (stat & BCH_INTS_ERR) {
+			if (stat & BCH_INTS_UNCOR) {
+				printk("NAND: Uncorrectable ECC error\n");
+				return -1;
+			} else {
+				u32 errcnt = (stat & BCH_INTS_ERRC_MASK) >> BCH_INTS_ERRC_BIT;
+				if(errcnt > 24)
+					printk("NAND:err count[%d] is too big\n",errcnt);
+				else
+				{
+					/*begin at the second DWORD*/
+					errs = (u32 *)&errs0[4];
+					for(i = 0;i < errcnt;i++)
+					{
+						/* errs[i>>1] get the error report regester value,
+						 * (i+1) the error bit index.
+						 * errs[i>>1] >> (((i + 1) % 2) << 4) means when error
+						 * bit index is even, errs[i>>1] >> 16*/
+						bch_correct(mtd, dat, ((errs[i>>1] >> ((i % 2) << 4))) & BCH_ERR_INDEX_MASK);
+					}
+				}
+			}
+		}
+	}
+
+	return ret;
+}
+
+#else				/* cpu mode */
+
+/**
+ * jzsoc_nand_bch_correct_data
+ * @mtd:	mtd info structure
+ * @dat:        data to be corrected
+ * @read_ecc:   pointer to ecc buffer calculated when nand writing
+ * @calc_ecc:   no used
+ */
+static int jzsoc_nand_bch_correct_data(struct mtd_info *mtd, u_char * dat, u_char * read_ecc, u_char * calc_ecc)
+{
+	struct nand_chip *this = (struct nand_chip *)(mtd->priv);
+	int eccsize = this->ecc.size;
+	int eccbytes = this->ecc.bytes;
+	int ecc_pos = this->ecc.layout->eccpos[0];
+	short k;
+	u32 stat;
+	int ret = 0;
+
+	/* Write data to REG_BCH_DR */
+	for (k = 0; k < eccsize; k++) {
+		REG_BCH_DR = ((struct buf_be_corrected *)dat)->data[k];
+	}
+
+	/* Write parities to REG_BCH_DR */
+	for (k = 0; k < eccbytes; k++) {
+		REG_BCH_DR = read_ecc[k];
+	}
+
+	/* Wait for completion */
+	__ecc_decode_sync();
+	__ecc_disable();
+
+	/* Check decoding */
+	stat = REG_BCH_INTS;
+
+	if (stat & BCH_INTS_ERR) {
+		/* Error occurred */
+		if (stat & BCH_INTS_UNCOR) {
+			printk("NAND: Uncorrectable ECC error--\n");
+			return -1;
+		} else {
+			u32 errcnt = (stat & BCH_INTS_ERRC_MASK) >> BCH_INTS_ERRC_BIT;
+			switch (errcnt) {
+				case 24:
+					bch_correct(mtd, dat, (REG_BCH_ERR11 & BCH_ERR_INDEX_ODD_MASK) >> BCH_ERR_INDEX_ODD_BIT);
+					/* FALL-THROUGH */
+				case 23:
+					bch_correct(mtd, dat, (REG_BCH_ERR11 & BCH_ERR_INDEX_EVEN_MASK) >> BCH_ERR_INDEX_EVEN_BIT);
+					/* FALL-THROUGH */
+				case 22:
+					bch_correct(mtd, dat, (REG_BCH_ERR10 & BCH_ERR_INDEX_ODD_MASK) >> BCH_ERR_INDEX_ODD_BIT);
+					/* FALL-THROUGH */
+				case 21:
+					bch_correct(mtd, dat, (REG_BCH_ERR10 & BCH_ERR_INDEX_EVEN_MASK) >> BCH_ERR_INDEX_EVEN_BIT);
+					/* FALL-THROUGH */
+				case 20:
+					bch_correct(mtd, dat, (REG_BCH_ERR9 & BCH_ERR_INDEX_ODD_MASK) >> BCH_ERR_INDEX_ODD_BIT);
+					/* FALL-THROUGH */
+				case 19:
+					bch_correct(mtd, dat, (REG_BCH_ERR9 & BCH_ERR_INDEX_EVEN_MASK) >> BCH_ERR_INDEX_EVEN_BIT);
+					/* FALL-THROUGH */
+				case 18:
+					bch_correct(mtd, dat, (REG_BCH_ERR8 & BCH_ERR_INDEX_ODD_MASK) >> BCH_ERR_INDEX_ODD_BIT);
+					/* FALL-THROUGH */
+				case 17:
+					bch_correct(mtd, dat, (REG_BCH_ERR8 & BCH_ERR_INDEX_EVEN_MASK) >> BCH_ERR_INDEX_EVEN_BIT);
+					/* FALL-THROUGH */
+				case 16:
+					bch_correct(mtd, dat, (REG_BCH_ERR7 & BCH_ERR_INDEX_ODD_MASK) >> BCH_ERR_INDEX_ODD_BIT);
+					/* FALL-THROUGH */
+				case 15:
+					bch_correct(mtd, dat, (REG_BCH_ERR7 & BCH_ERR_INDEX_EVEN_MASK) >> BCH_ERR_INDEX_EVEN_BIT);
+					/* FALL-THROUGH */
+				case 14:
+					bch_correct(mtd, dat, (REG_BCH_ERR6 & BCH_ERR_INDEX_ODD_MASK) >> BCH_ERR_INDEX_ODD_BIT);
+					/* FALL-THROUGH */
+				case 13:
+					bch_correct(mtd, dat, (REG_BCH_ERR6 & BCH_ERR_INDEX_EVEN_MASK) >> BCH_ERR_INDEX_EVEN_BIT);
+					/* FALL-THROUGH */
+				case 12:
+					bch_correct(mtd, dat, (REG_BCH_ERR5 & BCH_ERR_INDEX_ODD_MASK) >> BCH_ERR_INDEX_ODD_BIT);
+					/* FALL-THROUGH */
+				case 11:
+					bch_correct(mtd, dat, (REG_BCH_ERR5 & BCH_ERR_INDEX_EVEN_MASK) >> BCH_ERR_INDEX_EVEN_BIT);
+					/* FALL-THROUGH */
+				case 10:
+					bch_correct(mtd, dat, (REG_BCH_ERR4 & BCH_ERR_INDEX_ODD_MASK) >> BCH_ERR_INDEX_ODD_BIT);
+					/* FALL-THROUGH */
+				case 9:
+					bch_correct(mtd, dat, (REG_BCH_ERR4 & BCH_ERR_INDEX_EVEN_MASK) >> BCH_ERR_INDEX_EVEN_BIT);
+					/* FALL-THROUGH */
+				case 8:
+					bch_correct(mtd, dat, (REG_BCH_ERR3 & BCH_ERR_INDEX_ODD_MASK) >> BCH_ERR_INDEX_ODD_BIT);
+					/* FALL-THROUGH */
+				case 7:
+					bch_correct(mtd, dat, (REG_BCH_ERR3 & BCH_ERR_INDEX_EVEN_MASK) >> BCH_ERR_INDEX_EVEN_BIT);
+					/* FALL-THROUGH */
+				case 6:
+					bch_correct(mtd, dat, (REG_BCH_ERR2 & BCH_ERR_INDEX_ODD_MASK) >> BCH_ERR_INDEX_ODD_BIT);
+					/* FALL-THROUGH */
+				case 5:
+					bch_correct(mtd, dat, (REG_BCH_ERR2 & BCH_ERR_INDEX_EVEN_MASK) >> BCH_ERR_INDEX_EVEN_BIT);
+					/* FALL-THROUGH */
+				case 4:
+					bch_correct(mtd, dat, (REG_BCH_ERR1 & BCH_ERR_INDEX_ODD_MASK) >> BCH_ERR_INDEX_ODD_BIT);
+					/* FALL-THROUGH */
+				case 3:
+					bch_correct(mtd, dat, (REG_BCH_ERR1 & BCH_ERR_INDEX_EVEN_MASK) >> BCH_ERR_INDEX_EVEN_BIT);
+					/* FALL-THROUGH */
+				case 2:
+					bch_correct(mtd, dat, (REG_BCH_ERR0 & BCH_ERR_INDEX_ODD_MASK) >> BCH_ERR_INDEX_ODD_BIT);
+					/* FALL-THROUGH */
+				case 1:
+					bch_correct(mtd, dat, (REG_BCH_ERR0 & BCH_ERR_INDEX_EVEN_MASK) >> BCH_ERR_INDEX_EVEN_BIT);
+					return 0;
+				default:
+					break;
+			}
+		}
+	}
+
+	return ret;
+}
+
+#endif				/* CONFIG_MTD_NAND_DMA */
+
+static int jzsoc_nand_calculate_bch_ecc(struct mtd_info *mtd, const u_char * dat, u_char * ecc_code)
+{
+	struct nand_chip *this = (struct nand_chip *)(mtd->priv);
+	int eccsize = this->ecc.size;
+	int eccbytes = this->ecc.bytes;
+	volatile u8 *paraddr = (volatile u8 *)BCH_PAR0;
+	short i;
+
+	/* Write data to REG_BCH_DR */
+	for (i = 0; i < eccsize; i++) {
+		REG_BCH_DR = ((struct buf_be_corrected *)dat)->data[i];
+	}
+	__ecc_encode_sync();
+	__ecc_disable();
+
+	for (i = 0; i < eccbytes; i++) {
+		ecc_code[i] = *paraddr++;
+	}
+
+	return 0;
+}
+
+// extern int nand_sw_bch_ops(struct mtd_info *mtd, u8 *oobdata, int ops);
+
+#if defined(CONFIG_MTD_NAND_DMA)
+
+static void nand_oob_hwecc_bchenc(struct mtd_info *mtd, struct nand_chip *chip)
+{
+	u8 *oobbuf = chip->oob_poi;
+	int ecc_pos = chip->ecc.layout->eccpos[0];
+	int err;
+
+	__bdmac_channel_enable_clk(bch_dma_chan);
+
+	dma_cache_wback_inv((u32)oobbuf, mtd->oobsize);
+
+	REG_BDMAC_DCCSR(bch_dma_chan) = 0;
+
+	REG_BDMAC_DRSR(bch_dma_chan) = BDMAC_DRSR_RS_BCH_ENC;
+
+	REG_BDMAC_DSAR(bch_dma_chan) = CPHYSADDR((u32)(chip->oob_poi));
+	REG_BDMAC_DTAR(bch_dma_chan) = CPHYSADDR((u32)(chip->oob_poi)) + ecc_pos;
+	REG_BDMAC_DTCR(bch_dma_chan) = ecc_pos / 4;
+	REG_BDMAC_DCMD(bch_dma_chan) = BDMAC_DCMD_BLAST | BDMAC_DCMD_SAI | BDMAC_DCMD_DAI | BDMAC_DCMD_SWDH_32 |
+		BDMAC_DCMD_DWDH_8 | BDMAC_DCMD_DS_32BIT | BDMAC_DCMD_TIE;
+
+	dprintk("ch0:orgcnt:%d sa:%x da:%x cmd:%x stat:%x\n",REG_BDMAC_DTCR(bch_dma_chan),REG_BDMAC_DSAR(bch_dma_chan), \
+			REG_BDMAC_DTAR(bch_dma_chan),REG_BDMAC_DCMD(bch_dma_chan),REG_BDMAC_DCCSR(bch_dma_chan));
+
+	/* Setup DMA channel control/status register */
+	REG_BDMAC_DCCSR(bch_dma_chan) |= BDMAC_DCCSR_NDES | BDMAC_DCCSR_EN;
+
+	/* Enable DMA */
+	REG_BDMAC_DMACR |= BDMAC_DMACR_DMAE;
+
+	/* Enable BCH encoding */
+	REG_BCH_INTS = 0xffffffff;
+	__ECC_ENCODING();
+	__ecc_cnt_enc(ecc_pos * 2);
+	__ecc_dma_enable();
+
+#if USE_IRQ
+		dprintk("BCH before wake up\n");
+		do {
+			err = wait_event_interruptible_timeout(nand_prog_wait_queue, dma_ack, 3 * HZ);
+		}while(err == -ERESTARTSYS);
+		dprintk("BCH after wake up\n");
+		if (!err) {
+			printk("*** NAND WRITE, Warning, wait event 3s timeout!\n");
+			dump_jz_bdma_channel(0);
+			dump_jz_bdma_channel(nand_dma_chan);
+			printk("REG_BCH_CR=%x REG_BCH_CNT=0x%x REG_BCH_INTS=%x\n", REG_BCH_CR, REG_BCH_CNT, REG_BCH_INTS);
+		}
+		dprintk("timeout remain = %d\n", err);
+#else
+	timeout = 100000;
+	while ((!__bdmac_channel_transmit_end_detected(bch_dma_chan)) && (timeout--));
+	while(!chip->dev_ready(mtd));
+	if (timeout <= 0)
+		printk("not use irq, prog timeout!\n");
+#endif
+	dprintk("ch0:newcnt:%d sa:%x da:%x cmd:%x stat:%x\n",REG_BDMAC_DTCR(bch_dma_chan),REG_BDMAC_DSAR(bch_dma_chan), \
+			REG_BDMAC_DTAR(bch_dma_chan),REG_BDMAC_DCMD(bch_dma_chan),REG_BDMAC_DCCSR(bch_dma_chan));
+}
+
+/**
+ * nand_write_page_hwecc_bch - [REPLACABLE] hardware ecc based page write function
+ * @mtd:	mtd info structure
+ * @chip:	nand chip info structure
+ * @buf:	data buffer
+ */
+static void nand_write_page_hwecc_bch0(struct mtd_info *mtd, struct nand_chip *chip, const uint8_t * buf, u8 cmd_pgprog)
+{
+	int eccsize = chip->ecc.size;
+	int eccsteps = chip->ecc.steps / chip->planenum;
+	int eccbytes = chip->ecc.bytes;
+	int ecc_pos = chip->ecc.layout->eccpos[0];
+	int freesize = mtd->freesize / chip->planenum;
+	int oobsize = mtd->oobsize / chip->planenum;
+	int i, err, timeout;
+	const u8 *databuf;
+	u8 *oobbuf;
+	jz_bdma_desc_8word *desc;
+
+	nand_oob_hwecc_bchenc(mtd, chip);
+
+	databuf = buf;
+	oobbuf = chip->oob_poi;
+	memset(oobbuf + oobsize, 0xff, mtd->freesize);
+
+	/* descriptors for encoding data blocks */
+	desc = dma_desc_enc1;
+	for (i = 0; i < eccsteps; i++) {
+		desc->dsadr = CPHYSADDR((u32)databuf) + i * eccsize;	/* DMA source address */
+		desc->dtadr = CPHYSADDR((u32)oobbuf) + ecc_pos + (i + 1) * eccbytes;	/* DMA target address */
+		desc++;
+	}
+
+	/* descriptor for nand programing data block */
+	desc = dma_desc_nand_prog;
+	desc->dsadr = CPHYSADDR((u32)databuf);	/* DMA source address */
+	desc->dtadr = CPHYSADDR((u32)chip->IO_ADDR_W);  /* It will be changed when using multiply chip select */
+
+	if (freesize != 0) {
+		/* descriptor for nand programing free block */
+		desc++;
+		desc->dsadr = CPHYSADDR((u32)oobbuf) + oobsize;
+		desc->dtadr = CPHYSADDR((u32)chip->IO_ADDR_W);
+
+	}
+
+	/* descriptor for nand programing oob block */
+	desc++;
+	desc->dsadr = CPHYSADDR((u32)oobbuf);	/* DMA source address */
+	desc->dtadr = CPHYSADDR((u32)chip->IO_ADDR_W);  /* It will be changed when using multiply chip select */
+
+	/* descriptor for __nand_cmd(CMD_PGPROG) */
+	desc++;
+	*pval_nand_cmd_pgprog = cmd_pgprog | 0x40000000;
+	desc->dsadr = CPHYSADDR((u32)pval_nand_cmd_pgprog);
+	desc->dtadr = CPHYSADDR((u32)chip->IO_ADDR_R);	/* DMA target address: cmdport */
+	if (cmd_pgprog == 0x10)
+		desc->dcmd |= BDMAC_DCMD_LINK;  /* __nand_sync() by a DMA descriptor */
+	else if (cmd_pgprog == 0x11)
+		desc->dcmd &= ~BDMAC_DCMD_LINK; /* __nand_sync() by polling */
+
+	dma_cache_wback_inv((u32)dma_desc_enc, DMA_DESC_FLUSH_SIZE);
+
+	dma_cache_wback_inv((u32)databuf, mtd->validsize);
+	dma_cache_wback_inv((u32)oobbuf, oobsize + mtd->freesize);
+	/* 4*6: pval_nand_ddr, pval_nand_dcs, pval_bch_ddr, pval_bch_dcs, dummy, pval_nand_cmd_pgprog */
+	dma_cache_wback_inv((u32)pval_nand_ddr, 4 * 8); /* 8 words, a cache line */
+
+	REG_BDMAC_DCCSR(bch_dma_chan) = 0;
+	REG_BDMAC_DCCSR(nand_dma_chan) = 0;
+
+	/* Setup DMA descriptor address */
+	REG_BDMAC_DDA(bch_dma_chan) = CPHYSADDR((u32)dma_desc_enc1);
+#if USE_PN
+	REG_BDMAC_DDA(nand_dma_chan) = CPHYSADDR((u32)dma_desc_pPN);
+#else
+	REG_BDMAC_DDA(nand_dma_chan) = CPHYSADDR((u32)dma_desc_nand_prog);
+#endif
+
+	/* Setup request source */
+	REG_BDMAC_DRSR(bch_dma_chan) = BDMAC_DRSR_RS_BCH_ENC;
+	REG_BDMAC_DRSR(nand_dma_chan) = BDMAC_DRSR_RS_AUTO;
+
+	/* Setup DMA channel control/status register */
+	REG_BDMAC_DCCSR(bch_dma_chan) = BDMAC_DCCSR_DES8 | BDMAC_DCCSR_EN;	/* descriptor transfer, clear status, start channel */
+	/* Enable DMA */
+	REG_BDMAC_DMACR |= BDMAC_DMACR_DMAE;
+
+	/* Enable BCH encoding */
+	chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
+
+	dma_ack1 = 0;
+	nand_status = NAND_PROG;
+
+	/* DMA doorbell set -- start DMA now ... */
+	__bdmac_channel_set_doorbell(bch_dma_chan);
+
+#if USE_IRQ
+	if (cmd_pgprog == 0x10) {
+		dprintk("nand prog before wake up\n");
+		do {
+			dprintk("enter...\n");
+			err = wait_event_interruptible_timeout(nand_prog_wait_queue, dma_ack1, 3 * HZ);
+			dprintk("exit.\n");
+		}while(err == -ERESTARTSYS);
+
+		nand_status = NAND_NONE;
+		dprintk("nand prog after wake up\n");
+		if (!err) {
+			printk("*** NAND WRITE, Warning, wait event 3s timeout!\n");
+			dump_jz_bdma_channel(0);
+			dump_jz_bdma_channel(nand_dma_chan);
+			printk("REG_BCH_CR=%x REG_BCH_CNT=0x%x REG_BCH_INTS=%x\n", REG_BCH_CR, REG_BCH_CNT, REG_BCH_INTS);
+		}
+		dprintk("timeout remain = %d\n", err);
+	} else if (cmd_pgprog == 0x11) {
+		timeout = 100000;
+		while ((!__bdmac_channel_transmit_end_detected(nand_dma_chan)) && (timeout--));
+		if (timeout <= 0)
+			printk("two-plane prog 0x11 timeout!\n");
+	}
+#else
+	timeout = 100000;
+	while ((!__bdmac_channel_transmit_end_detected(nand_dma_chan)) && (timeout--));
+	while(!chip->dev_ready(mtd));
+	if (timeout <= 0)
+		printk("not use irq, prog timeout!\n");
+#endif
+
+}
+
+static void nand_write_page_hwecc_bch(struct mtd_info *mtd, struct nand_chip *chip, const uint8_t * buf)
+{
+	nand_write_page_hwecc_bch0(mtd, chip, buf, 0x10);
+}
+
+static void nand_write_page_hwecc_bch_planes(struct mtd_info *mtd, struct nand_chip *chip, const uint8_t * buf)
+{
+	int page;
+	int pagesize = mtd->writesize >> 1;
+	int ppb = mtd->erasesize / mtd->writesize;
+
+	page = (global_page / ppb) * ppb + global_page; /* = global_page%ppb + (global_page/ppb)*ppb*2 */
+
+	/* send cmd 0x80, the MSB should be valid if realplane is 4 */
+	if (chip->realplanenum == 2)
+	{
+		if(global_mafid == 0x2c)
+			chip->cmdfunc(mtd, 0x80, 0x00, page);
+		else
+			chip->cmdfunc(mtd, 0x80, 0x00, 0x00);
+	}
+	else
+		chip->cmdfunc(mtd, 0x80, 0x00, page & (1 << (chip->chip_shift - chip->page_shift)));
+
+	nand_write_page_hwecc_bch0(mtd, chip, buf, 0x11);
+	chip->cmdfunc(mtd, 0x81, 0x00, page + ppb);
+	nand_write_page_hwecc_bch0(mtd, chip, buf + pagesize, 0x10);
+}
+
+static int nand_write_oob_hwecc_bch(struct mtd_info *mtd, struct nand_chip *chip, int page)
+{
+	int status = 0;
+	int ecc_pos = chip->ecc.layout->eccpos[0];
+	int err;
+
+	chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
+
+	nand_oob_hwecc_bchenc(mtd, chip);
+
+	__bdmac_channel_enable_clk(nand_dma_chan);
+
+	REG_BDMAC_DCCSR(nand_dma_chan) = 0;
+
+	REG_BDMAC_DRSR(nand_dma_chan) = BDMAC_DRSR_RS_AUTO;
+
+	REG_BDMAC_DSAR(nand_dma_chan) = CPHYSADDR((u32)(chip->oob_poi));
+	REG_BDMAC_DTAR(nand_dma_chan) = CPHYSADDR((u32)(chip->IO_ADDR_W));
+	REG_BDMAC_DTCR(nand_dma_chan) = ecc_pos + chip->ecc.bytes;
+	REG_BDMAC_DCMD(nand_dma_chan) = BDMAC_DCMD_SAI | BDMAC_DCMD_DAI | BDMAC_DCMD_SWDH_8 |
+		BDMAC_DCMD_DWDH_8 | BDMAC_DCMD_DS_8BIT | BDMAC_DCMD_TIE;
+
+	/* Enable DMA */
+	REG_BDMAC_DMACR |= BDMAC_DMACR_DMAE;
+
+	REG_BDMAC_DCCSR(nand_dma_chan) |= BDMAC_DCCSR_NDES | BDMAC_DCCSR_EN;
+
+	dma_ack1 = 0;
+	nand_status = NAND_PROG;
+
+#if USE_IRQ
+		dprintk("nand prog before wake up\n");
+		do {
+			err = wait_event_interruptible_timeout(nand_prog_wait_queue, dma_ack1, 3 * HZ);
+		}while(err == -ERESTARTSYS);
+		nand_status = NAND_NONE;
+		dprintk("nand prog after wake up\n");
+		if (!err) {
+			printk("*** NAND WRITE, Warning, wait event 3s timeout!\n");
+			dump_jz_bdma_channel(0);
+			dump_jz_bdma_channel(nand_dma_chan);
+			printk("REG_BCH_CR=%x REG_BCH_CNT=0x%x REG_BCH_INTS=%x\n", REG_BCH_CR, REG_BCH_CNT, REG_BCH_INTS);
+		}
+		dprintk("timeout remain = %d\n", err);
+#else
+	timeout = 100000;
+	while ((!__bdmac_channel_transmit_end_detected(nand_dma_chan)) && (timeout--));
+	while(!chip->dev_ready(mtd));
+	if (timeout <= 0)
+		printk("not use irq, prog timeout!\n");
+#endif
+
+	/* Send command to program the OOB data */
+	chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
+
+	status = chip->waitfunc(mtd, chip);
+
+	return status & NAND_STATUS_FAIL ? -EIO : 0;
+}
+
+#else	/* nand write in cpu mode */
+
+static void nand_write_page_hwecc_bch(struct mtd_info *mtd, struct nand_chip *chip,
+		const uint8_t *buf)
+{
+	int i, eccsize = chip->ecc.size;
+	int eccbytes = chip->ecc.bytes;
+	int eccsteps = chip->ecc.steps / chip->planenum;
+	int oob_per_eccsize = chip->ecc.layout->eccpos[0] / eccsteps;
+	int oobsize = mtd->oobsize / chip->planenum;
+	int ecctotal = chip->ecc.total / chip->planenum;
+	uint8_t *p = (uint8_t *)buf;
+	uint8_t *ecc_calc = chip->buffers->ecccalc;
+	uint32_t *eccpos = chip->ecc.layout->eccpos;
+	static struct buf_be_corrected buf_calc0;
+	struct buf_be_corrected *buf_calc = &buf_calc0;
+
+	for (i = 0; i < eccsteps; i++, p += eccsize) {
+		buf_calc->data = (u8 *)buf + eccsize * i;
+		buf_calc->oob = chip->oob_poi + oob_per_eccsize * i;
+		chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
+		chip->ecc.calculate(mtd, (u8 *)buf_calc, &ecc_calc[eccbytes*i]);
+		chip->write_buf(mtd, p, eccsize);
+	}
+
+	for (i = 0; i < ecctotal; i++)
+		chip->oob_poi[eccpos[i]] = ecc_calc[i];
+
+	chip->write_buf(mtd, chip->oob_poi, oobsize);
+}
+
+/* nand write using two-plane mode */
+static void nand_write_page_hwecc_bch_planes(struct mtd_info *mtd, struct nand_chip *chip,
+		const uint8_t *buf)
+{
+	int pagesize = mtd->writesize >> 1;
+	int ppb = mtd->erasesize / mtd->writesize;
+	int page;
+
+	page = (global_page / ppb) * ppb + global_page; /* = global_page%ppb + (global_page/ppb)*ppb*2 */
+
+	/* send cmd 0x80, the MSB should be valid if realplane is 4 */
+	if (chip->realplanenum == 2)
+	{
+		if(global_mafid == 0x2c)
+			chip->cmdfunc(mtd, 0x80, 0x00, page);
+		else
+			chip->cmdfunc(mtd, 0x80, 0x00, 0x00);
+	}
+	else
+		chip->cmdfunc(mtd, 0x80, 0x00, page & (1 << (chip->chip_shift - chip->page_shift)));
+
+	nand_write_page_hwecc_bch(mtd, chip, buf);
+
+	chip->cmdfunc(mtd, 0x11, -1, -1); /* send cmd 0x11 */
+	ndelay(100);
+	while(!chip->dev_ready(mtd));
+
+	chip->cmdfunc(mtd, 0x81, 0x00, page + ppb); /* send cmd 0x81 */
+	nand_write_page_hwecc_bch(mtd, chip, buf + pagesize);
+}
+#endif				/* CONFIG_MTD_NAND_DMA */
+
+/**
+ * nand_read_page_hwecc_bch - [REPLACABLE] hardware ecc based page read function
+ * @mtd:	mtd info structure
+ * @chip:	nand chip info structure
+ * @buf:	buffer to store read data
+ *
+ * Not for syndrome calculating ecc controllers which need a special oob layout
+ */
+#if defined(CONFIG_MTD_NAND_DMA)
+static int nand_read_page_hwecc_bch0(struct mtd_info *mtd, struct nand_chip *chip, uint8_t * buf, u32 page)
+{
+	int i, eccsize = chip->ecc.size;
+	int eccsteps = chip->ecc.steps / chip->planenum;
+	int eccbytes = chip->ecc.bytes;
+	int ecc_pos = chip->ecc.layout->eccpos[0];
+	int pagesize = mtd->writesize / chip->planenum;
+	int freesize = mtd->freesize / chip->planenum;
+	int oobsize = mtd->oobsize / chip->planenum;
+	u8 *databuf, *oobbuf;
+	jz_bdma_desc_8word *desc;
+	int err;
+	u32 addrport, cmdport;
+	static struct buf_be_corrected buf_correct0;
+
+	addrport = (u32)(chip->IO_ADDR_R) | addr_offset;
+	cmdport = (u32)(chip->IO_ADDR_R) | cmd_offset;
+
+	databuf = buf;
+	oobbuf = chip->oob_poi;
+
+	dprintk("page:%d eccbytes:%d\n",page,eccbytes);
+
+	/* descriptor for nand reading data block */
+	desc = dma_desc_nand_read;
+	desc->dsadr = CPHYSADDR((u32)chip->IO_ADDR_R); /* It will be changed when using multiply chip select */
+	desc->dtadr = CPHYSADDR((u32)databuf);	/* DMA target address */
+	dprintk("desc_nand_read:desc:%x cmd:%x sadr:%x tadr:%x dadr:%x dcnt:%d\n", (u32)desc, desc->dcmd, desc->dsadr, desc->dtadr,
+				desc->ddadr,desc->dcnt);
+
+	if (freesize != 0) {
+		/* descriptor for nand reading FREE(use for oob) block */
+		desc++;
+		desc->dsadr = CPHYSADDR((u32)chip->IO_ADDR_R);
+		desc->dtadr = CPHYSADDR((u32)oobbuf) + oobsize;
+		dprintk("desc_free_read:desc:%x cmd:%x sadr:%x tadr:%x dadr:%x dcnt:%d\n", (u32)desc, desc->dcmd, desc->dsadr, desc->dtadr,
+					desc->ddadr,desc->dcnt);
+	}
+
+	/* descriptor for nand reading oob block */
+	desc++;
+	desc->dsadr = CPHYSADDR((u32)chip->IO_ADDR_R); /* It will be changed when using multiply chip select */
+	desc->dtadr = CPHYSADDR((u32)oobbuf);	/* DMA target address */
+	dprintk("desc_oob_read:desc:%x cmd:%x sadr:%x tadr:%x dadr:%x dcnt:%d\n", (u32)desc, desc->dcmd, desc->dsadr, desc->dtadr,
+				desc->ddadr,desc->dcnt);
+
+	/* descriptors for data to be written to bch */
+	desc = dma_desc_dec;
+	for (i = 0; i < eccsteps; i++) {
+		desc->dsadr = CPHYSADDR((u32)databuf) + i * eccsize;	/* DMA source address */
+		dprintk("dma_desc_dec:desc:%x cmd:%x sadr:%x tadr:%x dadr:%x dcnt:%d\n", (u32)desc, desc->dcmd, desc->dsadr, desc->dtadr,
+					desc->ddadr,desc->dcnt);
+		desc++;
+	}
+
+	/* descriptors for parities to be written to bch */
+	desc = dma_desc_dec1;
+	for (i = 0; i < eccsteps; i++) {
+		desc->dsadr = CPHYSADDR((u32)oobbuf) + ecc_pos + (i + 1) * eccbytes;	/* DMA source address */
+		dprintk("dma_desc_dec1:desc:%x cmd:%x sadr:%x tadr:%x dadr:%x dcnt:%d\n", (u32)desc, desc->dcmd, desc->dsadr, desc->dtadr,
+					desc->ddadr,desc->dcnt);
+		desc++;
+	}
+
+	dma_cache_wback_inv((u32)dma_desc_nand_read, DMA_DESC_FLUSH_SIZE);
+
+	memset(errs, 0, eccsteps * ERRS_SIZE * 4);
+	dma_cache_inv((u32)databuf, mtd->validsize);	// databuf should be invalidated.
+	dma_cache_inv((u32)oobbuf, oobsize + freesize);	// oobbuf should be invalidated too
+	dma_cache_wback_inv((u32)errs, eccsteps * ERRS_SIZE * 4);
+
+	REG_BDMAC_DCCSR(bch_dma_chan) = 0;
+	REG_BDMAC_DCCSR(nand_dma_chan) = 0;
+
+	/* Setup DMA descriptor address */
+#if USE_PN
+	REG_BDMAC_DDA(nand_dma_chan) = CPHYSADDR((u32)dma_desc_rPN);
+#else
+	REG_BDMAC_DDA(nand_dma_chan) = CPHYSADDR((u32)dma_desc_nand_read);
+#endif
+	REG_BDMAC_DDA(bch_dma_chan) = CPHYSADDR((u32)dma_desc_dec);
+
+	/* Setup request source */
+#if USE_PN
+	REG_BDMAC_DRSR(nand_dma_chan) = BDMAC_DRSR_RS_AUTO;
+#else
+	REG_BDMAC_DRSR(nand_dma_chan) = BDMAC_DRSR_RS_NAND0;
+#endif
+	REG_BDMAC_DRSR(bch_dma_chan) = BDMAC_DRSR_RS_BCH_DEC;
+
+	/* Enable DMA */
+	REG_BDMAC_DMACR |= BDMAC_DMACR_DMAE;
+
+	/* Enable BCH decoding */
+	chip->ecc.hwctl(mtd, NAND_ECC_READ);
+
+	dma_ack = 0;
+	nand_status = NAND_READ;
+	/* DMA doorbell set -- start nand DMA now ... */
+	__bdmac_channel_set_doorbell(nand_dma_chan);
+
+	/* Setup DMA channel control/status register */
+	REG_BDMAC_DCCSR(nand_dma_chan) = BDMAC_DCCSR_DES8 | BDMAC_DCCSR_EN;
+
+#define __nand_cmd(n)		(REG8(cmdport) = (n))
+#define __nand_addr(n)		(REG8(addrport) = (n))
+
+	__nand_cmd(NAND_CMD_READ0);
+
+	__nand_addr(0);
+	if (pagesize != 512)
+		__nand_addr(0);
+
+	__nand_addr(page & 0xff);
+	__nand_addr((page >> 8) & 0xff);
+
+	/* One more address cycle for the devices whose number of page address bits > 16  */
+	if (((chip->chipsize >> chip->page_shift) >> 16) > 0)
+		__nand_addr((page >> 16) & 0xff);
+
+	if (pagesize != 512)
+		__nand_cmd(NAND_CMD_READSTART);
+
+#if USE_IRQ
+	do {
+		err = wait_event_interruptible_timeout(nand_read_wait_queue, dma_ack, 3 * HZ);
+	}while(err == -ERESTARTSYS);
+	nand_status = NAND_NONE;
+
+	if (!err) {
+		printk("*** NAND READ, Warning, wait event 3s timeout!\n");
+		dump_jz_bdma_channel(0);
+		dump_jz_bdma_channel(nand_dma_chan);
+		printk("REG_BCH_CR=%x REG_BCH_CNT=0x%x REG_BCH_INTS=%x\n", REG_BCH_CR, REG_BCH_CNT, REG_BCH_INTS);
+	}
+		dprintk("timeout remain = %d\n", err);
+#else
+	int timeout;
+	timeout = 100000;
+	while ((!__bdmac_channel_transmit_end_detected(bch_dma_chan)) && (timeout--));
+	if (timeout <= 0) {
+		printk("not use irq, NAND READ timeout!\n");
+	}
+#endif
+
+	for (i = 0; i < eccsteps; i++) {
+		int stat;
+		struct buf_be_corrected *buf_correct = &buf_correct0;
+
+		buf_correct->data = databuf + eccsize * i;
+
+		stat = chip->ecc.correct(mtd, (u8 *)buf_correct, (u8 *)&errs[i * ERRS_SIZE], NULL);
+		if (stat < 0)
+		{
+			printk("ecc Uncorrectable:global_page = %d,chip->planenum = %d\n",global_page,chip->planenum);
+			mtd->ecc_stats.failed++;
+		}
+		else
+			mtd->ecc_stats.corrected += stat;
+	}
+
+	return 0;
+}
+
+static int nand_read_page_hwecc_bch(struct mtd_info *mtd, struct nand_chip *chip, uint8_t * buf)
+{
+	u32 page = global_page;
+	nand_read_page_hwecc_bch0(mtd, chip, buf, page);
+	return 0;
+}
+
+static int nand_read_page_hwecc_bch_planes(struct mtd_info *mtd, struct nand_chip *chip, uint8_t * buf)
+{
+	u32 page;
+	int pagesize = mtd->writesize >> 1;
+	int ppb = mtd->erasesize / mtd->writesize;
+
+	page = (global_page / ppb) * ppb + global_page; /* = global_page%ppb + (global_page/ppb)*ppb*2 */
+
+	/* read 1st page */
+	nand_read_page_hwecc_bch0(mtd, chip, buf, page);
+
+	/* read 2nd page */
+	nand_read_page_hwecc_bch0(mtd, chip, buf + pagesize, page + ppb);
+	return 0;
+}
+
+static int nand_read_oob_hwecc_bch(struct mtd_info *mtd, struct nand_chip *chip, int page, int sndcmd)
+{
+	int pagesize = mtd->writesize / chip->planenum;
+	int ecc_pos = chip->ecc.layout->eccpos[0];
+	int eccbytes = chip->ecc.bytes;
+	u32 addrport, cmdport;
+	int timeout;
+	int stat;
+	struct buf_be_corrected buf_correct;
+
+	if (sndcmd) {
+		chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
+		sndcmd = 0;
+	}
+
+	memset(chip->oob_poi,0x00,mtd->oobsize);
+	memset(oob_bch_errs, 0, ERRS_SIZE * 4);
+	dma_cache_wback_inv((u32)chip->oob_poi,mtd->oobsize);
+	dma_cache_wback_inv((u32)oob_bch_errs, ERRS_SIZE * 4);
+
+	__bdmac_channel_enable_clk(nand_dma_chan);
+	__bdmac_channel_enable_clk(bch_dma_chan);
+
+	REG_BDMAC_DCCSR(nand_dma_chan) = 0;
+	REG_BDMAC_DCCSR(bch_dma_chan) = 0;
+
+	REG_BDMAC_DRSR(nand_dma_chan) = BDMAC_DRSR_RS_NAND0;
+
+	REG_BDMAC_DRSR(bch_dma_chan) = BDMAC_DRSR_RS_BCH_DEC;
+
+	REG_BDMAC_DSAR(nand_dma_chan) = CPHYSADDR((u32)(chip->IO_ADDR_R));
+	REG_BDMAC_DTAR(nand_dma_chan) = CPHYSADDR((u32)(chip->oob_poi));
+	REG_BDMAC_DTCR(nand_dma_chan) = mtd->oobsize / 4;
+	REG_BDMAC_DCMD(nand_dma_chan) = BDMAC_DCMD_SAI | BDMAC_DCMD_DAI | BDMAC_DCMD_SWDH_32 |
+		BDMAC_DCMD_DWDH_32 | BDMAC_DCMD_DS_32BIT;
+
+	REG_BDMAC_DSAR(bch_dma_chan) = CPHYSADDR((u32)(chip->oob_poi));
+	REG_BDMAC_DTAR(bch_dma_chan) = CPHYSADDR((u32)oob_bch_errs);
+	REG_BDMAC_DTCR(bch_dma_chan) = ecc_pos + eccbytes;
+	REG_BDMAC_DCMD(bch_dma_chan) = BDMAC_DCMD_BLAST | BDMAC_DCMD_SAI | BDMAC_DCMD_DAI | BDMAC_DCMD_SWDH_8 |
+		BDMAC_DCMD_DWDH_32 | BDMAC_DCMD_DS_8BIT;
+
+	dma_ack1 = 0;
+	nand_status = NAND_READ;
+
+	/* Enable DMA */
+	REG_BDMAC_DMACR |= BDMAC_DMACR_DMAE;
+
+	/* Setup DMA channel control/status register */
+	REG_BDMAC_DCCSR(nand_dma_chan) |= BDMAC_DCCSR_NDES | BDMAC_DCCSR_EN;
+
+	/* Enable BCH decoding */
+	REG_BCH_INTS = 0xffffffff;
+	__ECC_DECODING();
+	__ecc_cnt_dec(ecc_pos * 2 + PAR_SIZE);
+	__ecc_dma_enable();
+	REG_BDMAC_DCCSR(bch_dma_chan) |= BDMAC_DCCSR_NDES | BDMAC_DCCSR_EN;
+
+
+	addrport = (u32)(chip->IO_ADDR_R) | addr_offset;
+	cmdport = (u32)(chip->IO_ADDR_R) | cmd_offset;
+
+#define __nand_cmd(n)		(REG8(cmdport) = (n))
+#define __nand_addr(n)		(REG8(addrport) = (n))
+
+	__nand_cmd(NAND_CMD_READ0);
+
+	__nand_addr(mtd->writesize & 0xff);
+	if (pagesize != 512)
+		__nand_addr((mtd->writesize >> 8) & 0xff);
+
+	__nand_addr(page & 0xff);
+	__nand_addr((page >> 8) & 0xff);
+
+	/* One more address cycle for the devices whose number of page address bits > 16  */
+	if (((chip->chipsize >> chip->page_shift) >> 16) > 0)
+		__nand_addr((page >> 16) & 0xff);
+
+	if (pagesize != 512){
+		chip->cmdfunc(mtd,NAND_CMD_READSTART,pagesize,page);
+	}
+#if !USE_IRQ
+	do {
+		err = wait_event_interruptible_timeout(nand_read_wait_queue, dma_ack1, 3 * HZ);
+	}while(err == -ERESTARTSYS);
+	nand_status = NAND_NONE;
+
+	if (!err) {
+		printk("*** NAND READ, Warning, wait event 3s timeout!\n");
+		dump_jz_bdma_channel(bch_dma_chan);
+		dump_jz_bdma_channel(nand_dma_chan);
+		printk("REG_BCH_CR=%x REG_BCH_CNT=0x%x REG_BCH_INTS=%x\n", REG_BCH_CR, REG_BCH_CNT, REG_BCH_INTS);
+	}
+	dprintk("timeout remain = %d\n", err);
+#else
+	timeout = 100000;
+	while ((!__bdmac_channel_transmit_end_detected(nand_dma_chan)) && (timeout--));
+	if (timeout <= 0) {
+		printk("not use irq, NAND READ timeout!\n");
+	}
+	REG_BDMAC_DCCSR(bch_dma_chan) |= BDMAC_DCCSR_NDES | BDMAC_DCCSR_EN;
+	timeout = 100000;
+	while ((!__bdmac_channel_transmit_end_detected(bch_dma_chan)) && (timeout--));
+	if (timeout <= 0) {
+		printk("not use irq, BCH decode timeout!\n");
+	}
+#endif
+
+#if !USE_IRQ
+	do {
+		err = wait_event_interruptible_timeout(nand_read_wait_queue, dma_ack, 3 * HZ);
+	}while(err == -ERESTARTSYS);
+
+	if (!err) {
+		printk("*** BCH decoding, Warning, wait event 3s timeout!\n");
+		dump_jz_bdma_channel(bch_dma_chan);
+		dump_jz_bdma_channel(nand_dma_chan);
+		printk("REG_BCH_CR=%x REG_BCH_CNT=0x%x REG_BCH_INTS=%x\n", REG_BCH_CR, REG_BCH_CNT, REG_BCH_INTS);
+	}
+	dprintk("timeout remain = %d\n", err);
+#else
+	timeout = 100000;
+	while ((!__bdmac_channel_transmit_end_detected(bch_dma_chan)) && (timeout--));
+	if (timeout <= 0) {
+		printk("not use irq, BCH decoding timeout!\n");
+	}
+#endif
+
+	buf_correct.data = chip->oob_poi;
+
+	stat = chip->ecc.correct(mtd, (u8 *)&buf_correct, (u8 *)&oob_bch_errs[0], NULL);
+	if (stat < 0)
+	{
+		printk("ecc Uncorrectable:global_page = %d,chip->planenum = %d\n",global_page,chip->planenum);
+		mtd->ecc_stats.failed++;
+	}
+	else
+		mtd->ecc_stats.corrected += stat;
+
+	return sndcmd;
+}
+
+#else	/* nand read in cpu mode */
+
+static int nand_read_page_hwecc_bch(struct mtd_info *mtd, struct nand_chip *chip, uint8_t * buf)
+{
+	int i,j, eccsize = chip->ecc.size;
+	int eccbytes = chip->ecc.bytes;
+	int eccsteps = chip->ecc.steps / chip->planenum;
+	int ecc_pos = chip->ecc.layout->eccpos[0];
+	uint8_t *ecc_calc = chip->buffers->ecccalc;
+	uint8_t *ecc_code = chip->buffers->ecccode;
+	uint32_t *eccpos = chip->ecc.layout->eccpos;
+	int pagesize = mtd->writesize / chip->planenum;
+	int oobsize = mtd->oobsize / chip->planenum;
+	int ecctotal = chip->ecc.total / chip->planenum;
+	static struct buf_be_corrected buf_correct0;
+	int data_per_page = mtd->validsize;	
+
+	dprintk("\nchip->planenum:%d eccsteps:%d eccsize:%d eccbytes:%d ecc_pos:%d pagesize:%d oobsize:%d \
+			ecctotal:%d data_per_page:%d\n",chip->planenum,eccsteps,eccsize,eccbytes,ecc_pos,pagesize,oobsize, \
+			ecctotal,data_per_page);
+
+	chip->read_buf(mtd, buf, pagesize);
+	chip->read_buf(mtd, chip->oob_poi, oobsize);
+
+	if (ecctotal <= oobsize - ecc_pos) {
+		for (i = 0; i < ecctotal; i++) {
+			ecc_code[i] = chip->oob_poi[eccpos[i]];
+		}
+	} else {
+		for (i = 0; i < oobsize - ecc_pos; i++) {
+			ecc_code[i] = chip->oob_poi[ecc_pos + i];
+		}
+		for (j = 0; j < ecctotal - oobsize + ecc_pos; j++) {
+			ecc_code[i + j] = buf[data_per_page + j];
+		}
+	}
+
+	for (i = 0; i < eccsteps; i++) {
+		int stat;
+		struct buf_be_corrected *buf_correct = &buf_correct0;
+
+		buf_correct->data = buf + eccsize * i;
+
+		chip->ecc.hwctl(mtd, NAND_ECC_READ);
+		stat = chip->ecc.correct(mtd, (u8 *)buf_correct, &ecc_code[eccbytes * i], &ecc_calc[eccbytes * i]);
+		if (stat < 0)
+		{
+			printk("ecc Uncorrectable:global_page = %d,chip->planenum = %d\n",global_page,chip->planenum);
+			mtd->ecc_stats.failed++;
+		}
+		else
+			mtd->ecc_stats.corrected += stat;
+	}
+
+	return 0;
+}
+
+static int nand_read_page_hwecc_bch_planes(struct mtd_info *mtd, struct nand_chip *chip, uint8_t * buf)
+{
+	int pagesize = mtd->writesize >> 1;
+	int ppb = mtd->erasesize / mtd->writesize;
+	uint32_t page;
+
+	page = (global_page / ppb) * ppb + global_page; /* = global_page%ppb + (global_page/ppb)*ppb*2 */
+
+	/* Read first page */
+	chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
+	nand_read_page_hwecc_bch(mtd, chip, buf);
+
+	/* Read 2nd page */
+	chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page + ppb);
+	nand_read_page_hwecc_bch(mtd, chip, buf+pagesize);
+	return 0;
+}
+#endif				/* CONFIG_MTD_NAND_DMA */
+
+#endif				/* CONFIG_MTD_HW_BCH_ECC */
+
+/* read oob using two-plane mode */
+static int nand_read_oob_std_planes(struct mtd_info *mtd, struct nand_chip *chip,
+		int global_page, int sndcmd)
+{
+	int page;
+	int oobsize = mtd->oobsize >> 1;
+	int ppb = mtd->erasesize / mtd->writesize;
+
+	page = (global_page / ppb) * ppb + global_page; /* = global_page%ppb + (global_page/ppb)*ppb*2 */
+
+	/* Read first page OOB */
+	if (sndcmd) {
+		chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
+	}
+	chip->read_buf(mtd, chip->oob_poi, oobsize);
+
+	/* Read second page OOB */
+	page += ppb;
+	if (sndcmd) {
+		chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
+		sndcmd = 0;
+	}
+	chip->read_buf(mtd, chip->oob_poi+oobsize, oobsize);
+
+	return 0;
+}
+
+/* write oob using two-plane mode */
+static int nand_write_oob_std_planes(struct mtd_info *mtd, struct nand_chip *chip,
+		int global_page)
+{
+	int status = 0, page;
+	const uint8_t *buf = chip->oob_poi;
+	int pagesize = mtd->writesize >> 1;
+	int oobsize = mtd->oobsize >> 1;
+	int ppb = mtd->erasesize / mtd->writesize;
+
+	page = (global_page / ppb) * ppb + global_page; /* = global_page%ppb + (global_page/ppb)*ppb*2 */
+
+	/* send cmd 0x80, the MSB should be valid if realplane is 4 */
+	if (chip->realplanenum == 2)
+	{
+		if(global_mafid == 0x2c)
+			chip->cmdfunc(mtd, 0x80, pagesize, page);
+		else
+			chip->cmdfunc(mtd, 0x80, pagesize, 0x00);
+	}
+	else
+		chip->cmdfunc(mtd, 0x80, pagesize, page & (1 << (chip->chip_shift - chip->page_shift)));
+
+	chip->write_buf(mtd, buf, oobsize);
+	/* Send first command to program the OOB data */
+	chip->cmdfunc(mtd, 0x11, -1, -1);
+	ndelay(100);
+	status = chip->waitfunc(mtd, chip);
+
+	page += ppb;
+	buf += oobsize;
+	chip->cmdfunc(mtd, 0x81, pagesize, page);
+	chip->write_buf(mtd, buf, oobsize);
+	/* Send command to program the OOB data */
+	chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
+	/* Wait long R/B */
+	ndelay(100);
+	status = chip->waitfunc(mtd, chip);
+
+	return status & NAND_STATUS_FAIL ? -EIO : 0;
+}
+
+/* nand erase using two-plane mode */
+static void single_erase_cmd_planes(struct mtd_info *mtd, int global_page)
+{
+	struct nand_chip *chip = mtd->priv;
+	int page, ppb = mtd->erasesize / mtd->writesize;
+
+	page = (global_page / ppb) * ppb + global_page; /* = global_page%ppb + (global_page/ppb)*ppb*2 */
+
+	/* send cmd 0x60, the MSB should be valid if realplane is 4 */
+	if (chip->realplanenum == 2)
+	{
+		if(global_mafid == 0x2c)
+			chip->cmdfunc(mtd, 0x60, -1, page);
+		else
+			chip->cmdfunc(mtd, 0x60, -1, 0x00);
+	}
+	else
+		chip->cmdfunc(mtd, 0x60, -1, page & (1 << (chip->chip_shift - chip->page_shift)));
+
+	page += ppb;
+	chip->cmdfunc(mtd, 0x60, -1, page & (~(ppb-1))); /* send cmd 0x60 */
+
+	chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1); /* send cmd 0xd0 */
+	/* Do not need wait R/B or check status */
+}
+
+#if defined(CONFIG_MTD_NAND_DMA)
+
+#if USE_IRQ
+static irqreturn_t nand_dma_irq(int irq, void *dev_id)
+{
+	u8 dma_chan;
+	volatile int wakeup = 0;
+
+	dma_chan = irq - IRQ_BDMA_0;
+
+	dprintk("jz4760_dma_irq %d, channel %d\n", irq, dma_chan);
+
+	if (__bdmac_channel_transmit_halt_detected(dma_chan)) {
+		__bdmac_channel_clear_transmit_halt(dma_chan);
+		wakeup = 1;
+		printk("DMA HALT\n");
+	}
+
+	if (__bdmac_channel_address_error_detected(dma_chan)) {
+
+		REG_BDMAC_DCCSR(dma_chan) &= ~BDMAC_DCCSR_EN;	/* disable DMA */
+		__bdmac_channel_clear_address_error(dma_chan);
+
+		REG_BDMAC_DSAR(dma_chan) = 0;	/* reset source address register */
+		REG_BDMAC_DTAR(dma_chan) = 0;	/* reset destination address register */
+
+		/* clear address error in BDMACR */
+		REG_BDMAC_DMACR &= ~(1 << 2);
+		wakeup = 1;
+		printk("DMA address error!\n");
+	}
+
+	if (__bdmac_channel_transmit_end_detected(dma_chan)) {
+		dprintk("DMA TT\n");
+		REG_BDMAC_DCCSR(dma_chan) &= ~BDMAC_DCCSR_EN;	/* disable DMA */
+		__bdmac_channel_clear_transmit_end(dma_chan);
+		wakeup = 1;
+	}
+
+	if (wakeup) {
+		dprintk("ack %d irq , wake up dma_chan %d nand_status %d\n", dma_ack, dma_chan, nand_status);
+		/* wakeup wait event */
+		if ((dma_chan == nand_dma_chan) && (nand_status == NAND_PROG)) {
+			dprintk("nand prog dma irq, wake up----\n");
+			dma_ack1 = 1;
+			wake_up_interruptible(&nand_prog_wait_queue);
+		}
+
+		if ((dma_chan == bch_dma_chan) && (nand_status == NAND_READ)) {
+			dprintk("nand read irq, wake up----\n");
+			dma_ack = 1;
+			wake_up_interruptible(&nand_read_wait_queue);
+		}
+		wakeup = 0;
+	}
+
+	return IRQ_HANDLED;
+}
+#endif				/* USE_IRQ */
+
+static int jz4760_nand_dma_init(struct mtd_info *mtd)
+{
+	struct nand_chip *chip = mtd->priv;
+	int eccsize = chip->ecc.size;
+	int eccsteps = chip->ecc.steps / chip->planenum;
+	int eccbytes = chip->ecc.bytes;
+	int ecc_pos = chip->ecc.layout->eccpos[0];
+	int oobsize = mtd->oobsize / chip->planenum;
+	int i, err;
+	jz_bdma_desc_8word *desc, *dma_desc_bch_ddr, *dma_desc_nand_ddr, *dma_desc_nand_cmd_pgprog;
+	u32  *pval_nand_dcs, *pval_bch_ddr, *pval_bch_dcs, *dummy;
+	u32 next;
+
+	dprintk("eccsize:%d eccsteps:%d eccbytes:%d ecc_pos:%d pagesize:%d oobsize:%d\n",eccsize,eccsteps,eccbytes,ecc_pos,pagesize,oobsize);
+
+#if USE_IRQ
+	if ((err = request_irq(IRQ_BDMA_0 + nand_dma_chan, nand_dma_irq, IRQF_DISABLED, "nand_dma", NULL))) {
+		printk("can't reqeust DMA nand channel.\n");
+		return 0;
+	}
+
+	if ((err = request_irq(IRQ_BDMA_0 + bch_dma_chan, nand_dma_irq, IRQF_DISABLED, "bch_dma", NULL))) {
+		printk("bch_dma irq request err\n");
+		return 0;
+	}
+#endif
+
+	__bdmac_channel_enable_clk(nand_dma_chan);
+	__bdmac_channel_enable_clk(bch_dma_chan);
+
+	/* space for the error reports of bch decoding((4 * ERRS_SIZE * eccsteps) bytes), and the space for the value
+	 * of ddr and dcs of channel 0 and channel 1.  (4 * (2 + 2) bytes) */
+	errs = (u32 *)kmalloc(4 * (2 + 2 + ERRS_SIZE * eccsteps), GFP_KERNEL);
+	if (!errs)
+		return -ENOMEM;
+
+	pval_nand_ddr = errs + ERRS_SIZE * eccsteps;
+	pval_nand_dcs = pval_nand_ddr + 1;
+	pval_bch_ddr = pval_nand_dcs + 1;
+	pval_bch_dcs = pval_bch_ddr + 1;
+	/* space for nand prog waiting target, the content is useless */
+	dummy = pval_bch_dcs + 1;
+	/* space to store CMD_PGPROG(0x10) or 0x11 */
+	pval_nand_cmd_pgprog = (u32 *)(dummy + 1);
+
+	/* desc can't across 4KB boundary, as desc base address is fixed */
+	/* space of descriptors for nand reading data and oob blocks */
+	dma_desc_nand_read = (jz_bdma_desc_8word *) __get_free_page(GFP_KERNEL);
+	if (!dma_desc_nand_read)
+		return -ENOMEM;
+
+	memset(dma_desc_nand_read, 0 ,4096);
+
+	/* space of descriptors for bch decoding */
+	dma_desc_dec = dma_desc_nand_read + 3;		// for data 512 bytes.
+	dma_desc_dec1 = dma_desc_dec + eccsteps;	// for ecc 39 bytes of 24bits.
+
+	/* space of descriptors for notifying bch channel */
+	dma_desc_bch_ddr = dma_desc_dec1 + eccsteps;
+
+	/* space of descriptors for bch encoding */
+	dma_desc_enc = dma_desc_bch_ddr + 2;
+	dma_desc_enc1 = dma_desc_enc + 1;
+
+	/* space of descriptors for nand programing data oob and free blocks */
+	dma_desc_nand_prog = dma_desc_enc1 + eccsteps;
+
+	/* space of descriptors for nand prog waiting, including pgprog and sync */
+	dma_desc_nand_cmd_pgprog = dma_desc_nand_prog + 3;
+
+	/* space of descriptors for notifying nand channel, including ddr and dcsr */
+	dma_desc_nand_ddr = dma_desc_nand_cmd_pgprog + 2;
+
+	/*************************************
+	 * Setup of nand programing descriptors
+	 *************************************/
+
+	/* set descriptor for encoding oob blocks */
+	desc = dma_desc_enc;
+	next = CPHYSADDR((u32)dma_desc_enc) + sizeof(jz_bdma_desc_8word);
+	desc->dcmd =
+		BDMAC_DCMD_BLAST | BDMAC_DCMD_SAI | BDMAC_DCMD_DAI | BDMAC_DCMD_SWDH_8 |
+		BDMAC_DCMD_DWDH_8 | BDMAC_DCMD_DS_8BIT | BDMAC_DCMD_LINK;
+	desc->dcnt = ecc_pos;	/* size: 7 bytes -> 2 words */
+	desc->dreqt = BDMAC_DRSR_RS_BCH_ENC;
+	desc->ddadr = next;
+	dprintk("cmd:%x sadr:%x tadr:%x dadr:%x dcnt\n", desc->dcmd, desc->dsadr, desc->dtadr, desc->ddadr,desc->dcnt);
+	desc++;
+
+	/* set descriptor for encoding data blocks */
+	desc = dma_desc_enc1;
+	for (i = 0; i < eccsteps; i++) {
+		next = CPHYSADDR((u32)dma_desc_enc1) + (i + 1) * (sizeof(jz_bdma_desc_8word));
+		desc->dcmd =
+			BDMAC_DCMD_BLAST | BDMAC_DCMD_SAI | BDMAC_DCMD_DAI | BDMAC_DCMD_SWDH_32 | BDMAC_DCMD_DWDH_8 |
+			BDMAC_DCMD_DS_BCH | BDMAC_DCMD_LINK;
+		desc->dcnt = eccsize / DIV_DS_BCH;	/* size: eccsize bytes */
+		desc->dreqt = BDMAC_DRSR_RS_BCH_ENC;
+		desc->ddadr = next;
+		dprintk("cmd:%x sadr:%x tadr:%x dadr:%x dcnt:%d\n", desc->dcmd, desc->dsadr, desc->dtadr, desc->ddadr, desc->dcnt);
+		desc++;
+	}
+
+	next = CPHYSADDR((u32)dma_desc_nand_ddr);
+	desc--;
+	desc->ddadr = next;
+
+	/* set the descriptor to set door bell of nand_dma_chan for programing nand */
+	desc = dma_desc_nand_ddr;
+	*pval_nand_ddr = 1 << nand_dma_chan;
+	next = CPHYSADDR((u32)dma_desc_nand_ddr) + sizeof(jz_bdma_desc_8word);
+	desc->dcmd = BDMAC_DCMD_SWDH_32 | BDMAC_DCMD_DWDH_32 | BDMAC_DCMD_DS_32BIT | BDMAC_DCMD_LINK;
+	desc->dsadr = CPHYSADDR((u32)pval_nand_ddr);	/* DMA source address */
+	desc->dtadr = CPHYSADDR(BDMAC_DMADBSR);	/* nand_dma_chan's descriptor addres register */
+	desc->dcnt = 1;	/* size: 1 word */
+	desc->dreqt = BDMAC_DRSR_RS_AUTO;
+	desc->ddadr = next;
+	dprintk("*pval_nand_ddr=0x%x\n", *pval_nand_ddr);
+
+	/* set the descriptor to write dccsr of nand_dma_chan for programing nand, dccsr should be set at last */
+	desc++;
+	*pval_nand_dcs = BDMAC_DCCSR_DES8 | BDMAC_DCCSR_EN;	/* set value for writing ddr to enable channel nand_dma_chan */
+	desc->dcmd = BDMAC_DCMD_SWDH_32 | BDMAC_DCMD_DWDH_32 | BDMAC_DCMD_DS_32BIT;
+	desc->dsadr = CPHYSADDR((u32)pval_nand_dcs);	/* DMA source address */
+	desc->dtadr = CPHYSADDR(BDMAC_DCCSR(nand_dma_chan));	/* address of dma door bell set register */
+	desc->dcnt = 1;	/* size: 1 word */
+	desc->dreqt = BDMAC_DRSR_RS_AUTO;
+	dprintk("*pval_nand_dcs=0x%x\n", *pval_nand_dcs);
+
+	/* set descriptor for nand programing data block */
+	desc = dma_desc_nand_prog;
+	next = CPHYSADDR((u32)dma_desc_nand_prog) + sizeof(jz_bdma_desc_8word);
+	desc->dcmd =
+		BDMAC_DCMD_SAI | BDMAC_DCMD_DAI | BDMAC_DCMD_SWDH_32 | BDMAC_DCMD_DWDH_32 |
+		BDMAC_DCMD_DS_NAND | BDMAC_DCMD_LINK;
+#if USE_DIRECT
+	desc->dcmd |= BDMAC_DCMD_NWR;
+#endif
+	desc->dtadr = CPHYSADDR((u32)(chip->IO_ADDR_W)); /* DMA target address */
+	desc->dcnt = mtd->validsize / DIV_DS_NAND;	/* size: eccsize bytes */
+	desc->dreqt = BDMAC_DRSR_RS_AUTO;
+	desc->ddadr = next;
+	dprintk("cmd:%x sadr:%x tadr:%x dadr:%x dcnt:%d\n", desc->dcmd, desc->dsadr, desc->dtadr, desc->ddadr, desc->dcnt);
+
+	if (mtd->freesize != 0) {
+		/* set descriptor for nand programing free block */
+		desc++;
+		next = CPHYSADDR((u32)dma_desc_nand_prog) + 2 * sizeof(jz_bdma_desc_8word);
+		desc->dcmd = BDMAC_DCMD_SAI | BDMAC_DCMD_DAI | BDMAC_DCMD_SWDH_32 | BDMAC_DCMD_DWDH_32 |
+			BDMAC_DCMD_DS_NAND | BDMAC_DCMD_LINK;
+		#if USE_DIRECT
+			desc->dcmd |= BDMAC_DCMD_NWR;
+		#endif
+		desc->dtadr = CPHYSADDR((u32)(chip->IO_ADDR_W));
+		desc->dcnt = mtd->freesize / DIV_DS_NAND;
+		desc->dreqt = BDMAC_DRSR_RS_AUTO;
+		desc->ddadr = next;
+		dprintk("cmd:%x sadr:%x tadr:%x dadr:%x dcnt:%d\n", desc->dcmd, desc->dsadr, desc->dtadr, desc->ddadr, desc->dcnt);
+	}
+
+	/* set descriptor for nand programing oob block */
+	desc++;
+	next = CPHYSADDR((u32)dma_desc_nand_cmd_pgprog);
+	desc->dcmd =
+		BDMAC_DCMD_SAI | BDMAC_DCMD_DAI | BDMAC_DCMD_SWDH_32 | BDMAC_DCMD_DWDH_32 |
+		BDMAC_DCMD_DS_32BIT | BDMAC_DCMD_LINK;
+#if USE_DIRECT
+	desc->dcmd |= BDMAC_DCMD_NWR;
+#endif
+	desc->dtadr = CPHYSADDR((u32)(chip->IO_ADDR_W));	/* DMA target address: dataport */
+	desc->dcnt = oobsize / 4;            	/* size: eccsize bytes */
+	desc->dreqt = BDMAC_DRSR_RS_AUTO;
+	desc->ddadr = next;
+	dprintk("cmd:%x sadr:%x tadr:%x dadr:%x dcnt:%d\n", desc->dcmd, desc->dsadr, desc->dtadr, desc->ddadr, desc->dcnt);
+
+	/* set descriptor for __nand_cmd(CMD_PGPROG) */
+	desc = dma_desc_nand_cmd_pgprog;
+	*pval_nand_cmd_pgprog = NAND_CMD_PAGEPROG | 0x40000000;
+	next = CPHYSADDR((u32)dma_desc_nand_cmd_pgprog) + sizeof(jz_bdma_desc_8word);
+	desc->dcmd =
+		BDMAC_DCMD_NAC | BDMAC_DCMD_SWDH_32 | BDMAC_DCMD_DWDH_XX | BDMAC_DCMD_DS_32BIT | BDMAC_DCMD_LINK;
+	desc->dsadr = CPHYSADDR((u32)pval_nand_cmd_pgprog);	        /* DMA source address */
+	desc->dtadr = CPHYSADDR((u32)chip->IO_ADDR_R);	/* DMA target address: cmdport */
+	desc->dcnt = 1;	                        /* size: 1 byte */
+	desc->dnt = 0;
+	desc->dreqt = BDMAC_DRSR_RS_AUTO;
+	desc->ddadr = next;
+	dprintk("cmd:%x sadr:%x tadr:%x dadr:%x dcnt:%d\n", desc->dcmd, desc->dsadr, desc->dtadr, desc->ddadr, desc->dcnt);
+
+	/* set descriptor for __nand_sync() */
+	desc++;
+#if USE_IRQ
+	desc->dcmd =
+		BDMAC_DCMD_SWDH_32 | BDMAC_DCMD_DWDH_32 | BDMAC_DCMD_DS_32BIT | BDMAC_DCMD_TIE;
+#else
+	desc->dcmd =
+		BDMAC_DCMD_SWDH_32 | BDMAC_DCMD_DWDH_32 | BDMAC_DCMD_DS_32BIT;
+#endif
+	desc->dsadr = CPHYSADDR((u32)pval_nand_ddr);	/* DMA source address */
+	desc->dtadr = CPHYSADDR((u32)dummy);        	/* DMA target address, the content is useless */
+	desc->dcnt = 1;             	/* size: 1 word */
+	desc->dnt = 1;
+	desc->dreqt = BDMAC_DRSR_RS_NAND0;
+	dprintk("cmd:%x sadr:%x tadr:%x dadr:%x dcnt:%d\n", desc->dcmd, desc->dsadr, desc->dtadr, desc->ddadr, desc->dcnt);
+
+	/* 1 + eccsteps + 3 + 2 + 2:
+	   dma_desc_enc + dma_desc_enc1 + dma_desc_nand_prog(oob/free) + dma_desc_nand_ddr(csr)
+	   + dma_desc_nand_cmd_pgprog(sync) */
+
+	dma_cache_wback_inv((u32)dma_desc_enc, DMA_DESC_FLUSH_SIZE);
+
+	/* 4*6: pval_nand_ddr, pval_nand_dcs, pval_bch_ddr, pval_bch_dcs, dummy, pval_nand_cmd_pgprog */
+	dma_cache_wback_inv((u32)pval_nand_ddr, 4 * 8); /* 8 words, a cache line */
+
+	/*************************************
+	 * Setup of nand reading descriptors
+	 *************************************/
+
+
+	/* set descriptor for nand reading data block */
+	desc = dma_desc_nand_read;
+	next = CPHYSADDR((u32)dma_desc_nand_read) + sizeof(jz_bdma_desc_8word);
+	desc->dcmd =
+		BDMAC_DCMD_SAI | BDMAC_DCMD_DAI | BDMAC_DCMD_SWDH_32 | BDMAC_DCMD_DWDH_32 |
+		BDMAC_DCMD_DS_NAND | BDMAC_DCMD_LINK;
+#if USE_DIRECT
+	desc->dcmd |= BDMAC_DCMD_NRD;
+#endif
+	desc->dsadr = CPHYSADDR((u32)(chip->IO_ADDR_R));	/* DMA source address */
+	desc->dcnt = mtd->validsize / DIV_DS_NAND;	/* size: eccsize bytes */
+	desc->dreqt = BDMAC_DRSR_RS_NAND0;
+	desc->ddadr = next;
+	dprintk("cmd:%x sadr:%x tadr:%x dadr:%x\n", desc->dcmd, desc->dsadr, desc->dtadr, desc->ddadr);
+
+	if (mtd->freesize != 0) {
+		/* set descriptor for nand reading FREE(use as oob) block */
+		desc++;
+		next = CPHYSADDR((u32)dma_desc_nand_read) + sizeof(jz_bdma_desc_8word) * 2;
+		desc->dcmd =
+			BDMAC_DCMD_SAI | BDMAC_DCMD_DAI | BDMAC_DCMD_SWDH_32 | BDMAC_DCMD_DWDH_32 |
+			BDMAC_DCMD_DS_NAND | BDMAC_DCMD_LINK;
+		#if USE_DIRECT
+			desc->dcmd |= BDMAC_DCMD_NRD;
+		#endif
+		desc->dsadr = CPHYSADDR((u32)(chip->IO_ADDR_R));	/* DMA source address */
+		desc->dcnt = mtd->freesize / DIV_DS_NAND;	/* size: eccsize bytes */
+		desc->dreqt = BDMAC_DRSR_RS_NAND0;
+		desc->ddadr = next;
+		dprintk("cmd:%x sadr:%x tadr:%x dadr:%x\n", desc->dcmd, desc->dsadr, desc->dtadr, desc->ddadr);
+	}
+
+	/* set descriptor for nand reading oob block */
+	desc++;
+	next = CPHYSADDR((u32)dma_desc_bch_ddr);
+	desc->dcmd =
+		BDMAC_DCMD_SAI | BDMAC_DCMD_DAI | BDMAC_DCMD_SWDH_32 | BDMAC_DCMD_DWDH_32 |
+		BDMAC_DCMD_DS_32BIT | BDMAC_DCMD_LINK;
+#if USE_DIRECT
+	desc->dcmd |= BDMAC_DCMD_NRD;
+#endif
+	desc->dsadr = CPHYSADDR((u32)(chip->IO_ADDR_R));	/* DMA source address */
+	//	desc->dcnt = oobsize / DIV_DS_NAND;	/* size: eccsize bytes */
+	desc->dcnt = oobsize / 4;	/* size: eccsize bytes */
+	desc->dreqt = BDMAC_DRSR_RS_AUTO;
+	desc->ddadr = next;
+	dprintk("cmd:%x sadr:%x tadr:%x dadr:%x\n", desc->dcmd, desc->dsadr, desc->dtadr, desc->ddadr);
+
+	/* set the descriptor to set door bell for bch */
+	desc = dma_desc_bch_ddr;
+	*pval_bch_ddr = BDMAC_DMADBSR_DBS0;	// set value for writing ddr to enable channel 0
+	next = CPHYSADDR((u32)dma_desc_bch_ddr) + sizeof(jz_bdma_desc_8word);
+	desc->dcmd = BDMAC_DCMD_SWDH_32 | BDMAC_DCMD_DWDH_32 | BDMAC_DCMD_DS_32BIT | BDMAC_DCMD_LINK;
+	desc->dsadr = CPHYSADDR((u32)pval_bch_ddr);	/* DMA source address */
+	desc->dtadr = CPHYSADDR(BDMAC_DMADBSR);	/* channel 0's descriptor addres register */
+	desc->dcnt = 1;	/* size: 1 word */
+	desc->dreqt = BDMAC_DRSR_RS_AUTO;
+	desc->ddadr = next;
+
+	/* set descriptor for writing dcsr */
+	desc++;
+	*pval_bch_dcs = BDMAC_DCCSR_DES8 | BDMAC_DCCSR_EN;	// set value for writing ddr to enable channel 0
+	desc->dcmd = BDMAC_DCMD_SWDH_32 | BDMAC_DCMD_DWDH_32 | BDMAC_DCMD_DS_32BIT;
+	desc->dsadr = CPHYSADDR((u32)pval_bch_dcs);	/* DMA source address */
+	desc->dtadr = CPHYSADDR(BDMAC_DCCSR(bch_dma_chan));
+	desc->dcnt = 1;	/* size: 1 word */
+	desc->dreqt = BDMAC_DRSR_RS_AUTO;
+
+	/* Ch0 ... */
+	/* descriptors for data to be written to bch */
+	desc = dma_desc_dec;
+	for (i = 0; i < eccsteps; i++) {
+		next = CPHYSADDR((u32)dma_desc_dec1 + i * (sizeof(jz_bdma_desc_8word)));
+
+		desc->dcmd =
+			BDMAC_DCMD_SAI | BDMAC_DCMD_DAI | BDMAC_DCMD_SWDH_32 | BDMAC_DCMD_DWDH_32 |
+			BDMAC_DCMD_DS_BCH | BDMAC_DCMD_LINK;
+		desc->dtadr = CPHYSADDR((u32)errs) + i * 4 * ERRS_SIZE;	/* DMA target address */
+		desc->dcnt = eccsize / DIV_DS_BCH;	/* size: eccsize bytes */
+		desc->dreqt = BDMAC_DRSR_RS_BCH_DEC;
+		desc->ddadr = next;
+		dprintk("desc:%x cmd:%x sadr:%x tadr:%x dadr:%x\n", (u32)desc, desc->dcmd, desc->dsadr, desc->dtadr,
+				desc->ddadr);
+		desc++;
+	}
+
+	/* descriptors for parities to be written to bch */
+	desc = dma_desc_dec1;
+	for (i = 0; i < eccsteps; i++) {
+		next = CPHYSADDR((u32)dma_desc_dec) + (i + 1) * (sizeof(jz_bdma_desc_8word));
+
+		desc->dcmd =
+			BDMAC_DCMD_BLAST | BDMAC_DCMD_SAI | BDMAC_DCMD_DAI | BDMAC_DCMD_SWDH_8 |
+			BDMAC_DCMD_DWDH_8 | BDMAC_DCMD_DS_8BIT | BDMAC_DCMD_LINK;
+		desc->dtadr = CPHYSADDR((u32)errs) + i * 4 * ERRS_SIZE;	/* DMA target address */
+		desc->dcnt = eccbytes;	/* size: eccbytes bytes */
+		desc->dreqt = BDMAC_DRSR_RS_BCH_DEC;
+		desc->ddadr = next;
+		dprintk("desc:%x cmd:%x sadr:%x tadr:%x dadr:%x\n", (u32)desc, desc->dcmd, desc->dsadr, desc->dtadr,
+				desc->ddadr);
+		desc++;
+	}
+	desc--;
+	desc->dcmd &= ~BDMAC_DCMD_LINK;
+#if USE_IRQ
+	desc->dcmd |= BDMAC_DCMD_TIE;
+#endif
+
+	dma_cache_wback_inv((u32)dma_desc_nand_read, DMA_DESC_FLUSH_SIZE);
+
+	dma_cache_wback_inv((u32)pval_bch_ddr, 4 * 2); /* two words */
+
+	return 0;
+}
+
+#endif				/* CONFIG_MTD_NAND_DMA */
+
+/*
+ * Main initialization routine
+ */
+int __init jznand_init(void)
+{
+	struct nand_chip *this;
+	int nr_partitions, ret, i;
+
+	printk(KERN_INFO "JZ NAND init");
+#if defined(CONFIG_MTD_NAND_DMA)
+#if defined(CONFIG_MTD_NAND_DMABUF)
+	printk(KERN_INFO " DMA mode, using DMA buffer in NAND driver.\n");
+#else
+	printk(KERN_INFO " DMA mode, using DMA buffer in upper layer.\n");
+#endif
+#else
+	printk(KERN_INFO " CPU mode.\n");
+#endif
+
+	cpm_start_clock(CGM_BDMA);
+
+	/* Allocate memory for MTD device structure and private data */
+	jz_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL);
+	if (!jz_mtd) {
+		printk("Unable to allocate JzSOC NAND MTD device structure.\n");
+		return -ENOMEM;
+	}
+
+	/* Allocate memory for NAND when using only one plane */
+	jz_mtd1 = kmalloc(sizeof(struct mtd_info) + sizeof (struct nand_chip), GFP_KERNEL);
+	if (!jz_mtd1) {
+		printk ("Unable to allocate JzSOC NAND MTD device structure 1.\n");
+		kfree(jz_mtd);
+		return -ENOMEM;
+	}
+
+	/* Get pointer to private data */
+	this = (struct nand_chip *)(&jz_mtd[1]);
+
+	/* Initialize structures */
+	memset((char *)jz_mtd, 0, sizeof(struct mtd_info));
+	memset((char *)this, 0, sizeof(struct nand_chip));
+
+#ifdef CONFIG_MTD_NAND_BUS_WIDTH_16
+	this->options |= NAND_BUSWIDTH_16;
+#endif
+
+	/* Link the private data with the MTD structure */
+	jz_mtd->priv = this;
+
+
+	addr_offset = NAND_ADDR_OFFSET;
+	cmd_offset = NAND_CMD_OFFSET;
+
+	/* Set & initialize NAND Flash controller */
+	jz_device_setup();
+
+	/* Set address of NAND IO lines to static bank1 by default */
+	this->IO_ADDR_R = (void __iomem *)NAND_DATA_PORT1;
+	this->IO_ADDR_W = (void __iomem *)NAND_DATA_PORT1;
+	this->cmd_ctrl = jz_hwcontrol;
+	this->dev_ready = jz_device_ready;
+
+#ifdef CONFIG_MTD_HW_BCH_ECC
+	this->ecc.calculate = jzsoc_nand_calculate_bch_ecc;
+	this->ecc.correct = jzsoc_nand_bch_correct_data;
+	this->ecc.hwctl = jzsoc_nand_enable_bch_hwecc;
+	this->ecc.mode = NAND_ECC_HW;
+	this->ecc.size = 512;
+	this->ecc.read_page = nand_read_page_hwecc_bch;
+	this->ecc.write_page = nand_write_page_hwecc_bch;
+
+	this->ecc.read_oob = nand_read_oob_hwecc_bch;
+	this->ecc.write_oob = nand_write_oob_hwecc_bch;
+
+#if defined(CONFIG_MTD_HW_BCH_24BIT)
+	this->ecc.bytes = 39;
+#elif defined(CONFIG_MTD_HW_BCH_20BIT)
+	this->ecc.bytes = 33;
+#elif defined(CONFIG_MTD_HW_BCH_16BIT)
+	this->ecc.bytes = 26;
+#elif defined(CONFIG_MTD_HW_BCH_12BIT)
+	this->ecc.bytes = 20;
+#elif defined(CONFIG_MTD_HW_BCH_8BIT)
+	this->ecc.bytes = 13;
+#else
+	this->ecc.bytes = 7;
+#endif
+#endif
+
+#ifdef  CONFIG_MTD_SW_HM_ECC
+	this->ecc.mode = NAND_ECC_SOFT;
+#endif
+	/* 20 us command delay time */
+	this->chip_delay = 20;
+	/* Scan to find existance of the device */
+	ret = nand_scan_ident(jz_mtd, NAND_MAX_CHIPS);
+
+	if (!ret) {
+		if (this->planenum == 2) {
+			/* reset nand functions */
+			this->erase_cmd = single_erase_cmd_planes;
+			this->ecc.read_page = nand_read_page_hwecc_bch_planes;
+			this->ecc.write_page = nand_write_page_hwecc_bch_planes;
+			this->ecc.read_oob = nand_read_oob_std_planes;
+			this->ecc.write_oob = nand_write_oob_std_planes;
+
+			printk(KERN_INFO "Nand using two-plane mode, "
+					"and resized to writesize:%d oobsize:%d blocksize:0x%x \n",
+					jz_mtd->writesize, jz_mtd->oobsize, jz_mtd->erasesize);
+		}
+	}
+
+	/* Determine whether all the partitions will use multiple planes if supported */
+	nr_partitions = sizeof(partition_info) / sizeof(struct mtd_partition);
+	all_use_planes = 1;
+	for (i = 0; i < nr_partitions; i++) {
+		all_use_planes &= partition_info[i].use_planes;
+	}
+
+	if (!ret)
+		ret = nand_scan_tail(jz_mtd);
+
+	if (ret){
+		kfree (jz_mtd1);
+		kfree (jz_mtd);
+		return -ENXIO;
+	}
+
+#if defined(CONFIG_MTD_NAND_DMA)
+	jz4760_nand_dma_init(jz_mtd);
+#endif
+
+	((struct nand_chip *) (&jz_mtd1[1]))->ecc.read_page = nand_read_page_hwecc_bch;
+	((struct nand_chip *) (&jz_mtd1[1]))->ecc.write_page = nand_write_page_hwecc_bch;
+
+	/* Register the partitions */
+	printk (KERN_NOTICE "Creating %d MTD partitions on \"%s\":\n", nr_partitions, jz_mtd->name);
+
+	calc_partition_size(jz_mtd);
+
+	if ((this->planenum == 2) && !all_use_planes) {
+		for (i = 0; i < nr_partitions; i++) {
+			if (partition_info[i].use_planes)
+				add_mtd_partitions(jz_mtd, &partition_info[i], 1);
+			else
+				add_mtd_partitions(jz_mtd1, &partition_info[i], 1);
+		}
+	} else {
+		kfree(jz_mtd1);
+		add_mtd_partitions(jz_mtd, partition_info, nr_partitions);
+	}
+	return 0;
+}
+
+module_init(jznand_init);
+
+/*
+ * Clean up routine
+ */
+#ifdef MODULE
+
+#if defined(CONFIG_MTD_NAND_DMA)
+static int jz4760_nand_dma_exit(struct mtd_info *mtd)
+{
+	int pagesize = mtd->writesize / chip->planenum;
+
+#if USE_IRQ
+	free_irq(IRQ_BDMA_0 + nand_dma_chan, NULL);
+	free_irq(IRQ_BDMA_0 + bch_dma_chan, NULL);
+#endif
+
+	/* space for the error reports of bch decoding((4 * 5 * eccsteps) bytes),
+	 * and the space for the value of ddr and dcs of channel 0 and channel
+	 * nand_dma_chan (4 * (2 + 2) bytes) */
+	kfree(errs);
+
+	/* space for dma_desc_nand_read contains dma_desc_nand_prog,
+	 * dma_desc_enc and dma_desc_dec */
+	free_page((u32)dma_desc_nand_read);
+
+#if defined(CONFIG_MTD_NAND_DMABUF)
+	if (pagesize < 4096) {
+		free_page((u32)prog_buf);
+	} else {
+		free_pages((u32)prog_buf, 1);
+	}
+#endif
+
+#if USE_PN
+	free_page((u32)dma_desc_pPN);
+	free_page((u32)dma_desc_rPN);
+	kfree(pn_buf);
+#endif
+
+	return 0;
+}
+#endif
+
+static void __exit jznand_cleanup(void)
+{
+#if defined(CONFIG_MTD_NAND_DMA)
+	jz4760_nand_dma_exit(jz_mtd);
+#endif
+
+	/* Unregister partitions */
+	del_mtd_partitions(jz_mtd);
+
+	/* Unregister the device */
+	del_mtd_device(jz_mtd);
+
+	/* Free the MTD device structure */
+	if ((this->planenum == 2) && !all_use_planes)
+		kfree (jz_mtd1);
+	kfree(jz_mtd);
+}
+
+module_exit(jznand_cleanup);
+#endif
diff --git a/drivers/mtd/nand/jz4770_nand.c b/drivers/mtd/nand/jz4770_nand.c
new file mode 100644
index 00000000000..9a0c74bf418
--- /dev/null
+++ b/drivers/mtd/nand/jz4770_nand.c
@@ -0,0 +1,2021 @@
+/*

+ * linux/drivers/mtd/nand/jz4770_nand.c

+ *

+ * JZ4770 NAND driver

+ *

+ * Copyright (c) 2005 - 2007 Ingenic Semiconductor Inc.

+ * Author: <lhhuang@ingenic.cn>

+ *

+ * This program is free software; you can redistribute it and/or modify

+ * it under the terms of the GNU General Public License as published by

+ * the Free Software Foundation; either version 2 of the License, or

+ * (at your option) any later version.

+ */

+

+#include <linux/slab.h>

+#include <linux/module.h>

+#include <linux/delay.h>

+#include <linux/init.h>

+

+#include <linux/mtd/mtd.h>

+#include <linux/mtd/nand.h>

+#include <linux/mtd/nand_ecc.h>

+#include <linux/mtd/partitions.h>

+

+#include <asm/io.h>

+#include <asm/jzsoc.h>

+

+#define BDMAC_DCMD_DS_NAND		BDMAC_DCMD_DS_64BYTE

+#define DIV_DS_NAND				64

+

+#define BDMAC_DCMD_DS_BCH		BDMAC_DCMD_DS_64BYTE

+#define DIV_DS_BCH           	64

+

+#ifdef CONFIG_MTD_NAND_BUS_WIDTH_16

+#define BDMAC_DCMD_DWDH_XX	BDMAC_DCMD_DWDH_16

+#else

+#define BDMAC_DCMD_DWDH_XX	BDMAC_DCMD_DWDH_8

+#endif

+

+#define USE_DIRECT	1

+#define	USE_PN		0

+#define	USE_COUNTER	0

+#define	COUNT_0		0	/* 1:count the number of 1; 0:count the number of 0 */

+#define PN_ENABLE			(1 | PN_RESET)

+#define PN_DISABLE			0

+#define PN_RESET			(1 << 1)

+#define COUNTER_ENABLE  	((1 << 3) | COUNTER_RESET)

+#define COUNTER_DISABLE 	(0 << 3)

+#define COUNTER_RESET   	(1 << 5)

+#define COUNT_FOR_1			(0 << 4)

+#define COUNT_FOR_0			(1 << 4)

+

+#define DEBUG1        0

+#if DEBUG1

+#define	dprintk(n,x...) printk(n,##x)

+#else

+#define	dprintk(n,x...)

+#endif

+

+#if defined(CONFIG_MTD_HW_BCH_24BIT)

+#define __ECC_ENCODING __ecc_encoding_24bit

+#define __ECC_DECODING __ecc_decoding_24bit

+#define ERRS_SIZE       13	/* 13 words */

+#define PAR_SIZE       	78	/* 24-bit */

+#elif defined(CONFIG_MTD_HW_BCH_20BIT)

+#define __ECC_ENCODING __ecc_encoding_20bit

+#define __ECC_DECODING __ecc_decoding_20bit

+#define ERRS_SIZE       11	/* 11 words */

+#define PAR_SIZE       	65	/* 20-bit */

+#elif defined(CONFIG_MTD_HW_BCH_16BIT)

+#define __ECC_ENCODING __ecc_encoding_16bit

+#define __ECC_DECODING __ecc_decoding_16bit

+#define ERRS_SIZE       9	/* 9 words */

+#define PAR_SIZE       	52	/* 16-bit */

+#elif defined(CONFIG_MTD_HW_BCH_12BIT)

+#define __ECC_ENCODING __ecc_encoding_12bit

+#define __ECC_DECODING __ecc_decoding_12bit

+#define ERRS_SIZE       7	/* 7 words */

+#define PAR_SIZE       	39	/* 12-bit */

+#elif defined(CONFIG_MTD_HW_BCH_8BIT)

+#define __ECC_ENCODING __ecc_encoding_8bit

+#define __ECC_DECODING __ecc_decoding_8bit

+#define ERRS_SIZE       5	/* 5 words */

+#define PAR_SIZE       	26	/* 8-bit */

+#else

+#define __ECC_ENCODING __ecc_encoding_4bit

+#define __ECC_DECODING __ecc_decoding_4bit

+#define ERRS_SIZE       3	/* 3 words */

+#define PAR_SIZE       	13	/* 4-bit */

+#endif

+

+#define NAND_DATA_PORT1	       0xBA000000	/* read-write area in static bank 1 */

+#define NAND_DATA_PORT2	       0xB8000000	/* read-write area in static bank 2 */

+#define NAND_DATA_PORT3	       0xB7000000	/* read-write area in static bank 3 */

+#define NAND_DATA_PORT4	       0xB6000000	/* read-write area in static bank 4 */

+

+#define NAND_ADDR_OFFSET       0x00800000      /* address port offset for unshare mode */

+#define NAND_CMD_OFFSET        0x00400000      /* command port offset for unshare mode */

+

+#if defined(CONFIG_MTD_NAND_DMA)

+#define  USE_IRQ      1

+enum {

+	NAND_NONE,

+	NAND_PROG,

+	NAND_READ

+};

+static volatile u8 nand_status;

+static volatile int dma_ack = 0;

+static volatile int dma_ack1 = 0;

+static char nand_dma_chan = 1;	/* fixed to channel 1 */

+static char bch_dma_chan = 0;	/* fixed to channel 0 */

+static u32 *errs;

+static jz_bdma_desc_8word *dma_desc_enc, *dma_desc_enc1, *dma_desc_dec, *dma_desc_dec1, *dma_desc_dec2,

+	*dma_desc_nand_prog, *dma_desc_nand_read;

+#if USE_PN

+static jz_bdma_desc_8word *dma_desc_pPN, *dma_desc_rPN;

+#endif

+static u32 *pval_nand_ddr;

+static u32 *pval_nand_cmd_pgprog; /* for sending 0x11 or 0x10 when programing*/

+#if defined(CONFIG_MTD_NAND_DMABUF)

+u8 *prog_buf, *read_buf;

+#endif

+#if USE_PN

+static u32 *pn_buf;

+#endif

+DECLARE_WAIT_QUEUE_HEAD(nand_prog_wait_queue);

+DECLARE_WAIT_QUEUE_HEAD(nand_read_wait_queue);

+#endif		/* CONFIG_MTD_NAND_DMA */

+

+struct buf_be_corrected {

+	u8 *data;

+	u8 *oob;

+};

+

+static u32 addr_offset;

+static u32 cmd_offset;

+

+extern int global_page; /* for two-plane operations */

+extern int global_mafid; /* ID of manufacture */

+

+/*

+ * MTD structure for JzSOC board

+ */

+static struct mtd_info *jz_mtd = NULL;

+extern struct mtd_info *jz_mtd1;

+extern char all_use_planes;

+

+/*

+ * Define partitions for flash devices

+ */

+#if defined(CONFIG_JZ4760_CYGNUS) || defined(CONFIG_JZ4760_LEPUS) || defined(CONFIG_JZ4770_F4770)

+static struct mtd_partition partition_info[] = {

+	{name:"NAND BOOT partition",

+	 offset:0 * 0x100000LL,

+	 size:4 * 0x100000LL,

+	 use_planes: 0},

+	{name:"NAND KERNEL partition",

+	 offset:4 * 0x100000LL,

+	 size:4 * 0x100000LL,

+	 use_planes: 0},

+	{name:"NAND ROOTFS partition",

+	 offset:8 * 0x100000LL,

+	 size:504 * 0x100000LL,

+	 use_planes: 0},

+	{name:"NAND DATA partition",

+	 offset:512 * 0x100000LL,

+	 size:512 * 0x100000LL,

+	 use_planes: 1},

+	{name:"NAND VFAT partition",

+	 offset:1024 * 0x100000LL,

+	 size:1024 * 0x100000LL,

+	 use_planes: 1},

+};

+

+/* Define max reserved bad blocks for each partition.

+ * This is used by the mtdblock-jz.c NAND FTL driver only.

+ *

+ * The NAND FTL driver reserves some good blocks which can't be

+ * seen by the upper layer. When the bad block number of a partition

+ * exceeds the max reserved blocks, then there is no more reserved

+ * good blocks to be used by the NAND FTL driver when another bad

+ * block generated.

+ */

+static int partition_reserved_badblocks[] = {

+	2,			/* reserved blocks of mtd0 */

+	2,			/* reserved blocks of mtd1 */

+	10,			/* reserved blocks of mtd2 */

+	10,			/* reserved blocks of mtd3 */

+	20,			/* reserved blocks of mtd4 */

+	20

+};				/* reserved blocks of mtd5 */

+#endif				/* CONFIG_JZ4760_CYGNUS || CONFIG_JZ4760_LEPUS */

+

+#if defined(CONFIG_JZ4760_ALTAIR)

+

+/* Reserve 32MB for bootloader, splash1, splash2 and radiofw */

+#define MISC_OFFSET		(32  * 0x100000LL)

+

+#define MISC_SIZE		(  1 * 0x100000LL)

+#define RECOVERY_SIZE		(  5 * 0x100000LL)

+#define BOOT_SIZE		(  4 * 0x100000LL)

+#define SYSTEM_SIZE		(90 * 0x100000LL)

+#define USERDATA_SIZE		(90 * 0x100000LL)

+#define CACHE_SIZE		(32 * 0x100000LL)

+#define STORAGE_SIZE		(MTDPART_SIZ_FULL)

+

+static struct mtd_partition partition_info[] = {

+

+	/* Android partitions:

+	 *

+	 * misc@mtd0 :      raw

+	 * recovery@mtd1:   raw

+	 * boot@mtd2:       raw

+	 * system@mtd3:     yaffs2

+	 * userdata@mtd4:   yaffs2

+	 * cache@mtd5:      yaffs2

+	 * storage@mtd6:    vfat

+	 */

+	{name:       "misc",

+	 offset:     MISC_OFFSET,

+	 size:       MISC_SIZE,

+	 use_planes: 0},

+	{name:       "recovery",

+	 offset:     (MISC_OFFSET+MISC_SIZE),

+	 size:       RECOVERY_SIZE,

+	 use_planes: 0},

+	{name:       "boot",

+	 offset:     (MISC_OFFSET+MISC_SIZE+RECOVERY_SIZE),

+	 size:       BOOT_SIZE,

+	 use_planes: 0},

+	{name:       "system",

+	 offset:     (MISC_OFFSET+MISC_SIZE+RECOVERY_SIZE+BOOT_SIZE),

+	 size:       SYSTEM_SIZE,

+	 use_planes: 0},

+	{name:       "userdata",

+	 offset:     (MISC_OFFSET+MISC_SIZE+RECOVERY_SIZE+BOOT_SIZE+SYSTEM_SIZE),

+	 size:       USERDATA_SIZE,

+	 use_planes: 0},

+	{name:       "cache",

+	 offset:     (MISC_OFFSET+MISC_SIZE+RECOVERY_SIZE+BOOT_SIZE+SYSTEM_SIZE+USERDATA_SIZE),

+	 size:       CACHE_SIZE,

+	 use_planes: 0},

+	{name:       "storage",

+	 offset:     (MISC_OFFSET+MISC_SIZE+RECOVERY_SIZE+BOOT_SIZE+SYSTEM_SIZE+USERDATA_SIZE+CACHE_SIZE),

+	 size:       STORAGE_SIZE,

+	 use_planes: 0}

+};

+

+/* Define max reserved bad blocks for each partition.

+ * This is used by the mtdblock-jz.c NAND FTL driver only.

+ *

+ * The NAND FTL driver reserves some good blocks which can't be

+ * seen by the upper layer. When the bad block number of a partition

+ * exceeds the max reserved blocks, then there is no more reserved

+ * good blocks to be used by the NAND FTL driver when another bad

+ * block generated.

+ */

+static int partition_reserved_badblocks[] = {

+	10,			/* reserved blocks of mtd0 */

+	10,			/* reserved blocks of mtd1 */

+	10,			/* reserved blocks of mtd2 */

+	10,			/* reserved blocks of mtd3 */

+	10,			/* reserved blocks of mtd4 */

+	10,			/* reserved blocks of mtd5 */

+	12			/* reserved blocks of mtd6 */

+};

+#endif	                        /* CONFIG_JZ4760_ALTAIR */

+

+/*-------------------------------------------------------------------------

+ * Following three functions are exported and used by the mtdblock-jz.c

+ * NAND FTL driver only.

+ */

+

+unsigned short get_mtdblock_write_verify_enable(void)

+{

+#ifdef CONFIG_MTD_MTDBLOCK_WRITE_VERIFY_ENABLE

+	return 1;

+#endif

+	return 0;

+}

+

+EXPORT_SYMBOL(get_mtdblock_write_verify_enable);

+

+unsigned short get_mtdblock_oob_copies(void)

+{

+	return CONFIG_MTD_OOB_COPIES;

+}

+

+EXPORT_SYMBOL(get_mtdblock_oob_copies);

+

+int *get_jz_badblock_table(void)

+{

+	return partition_reserved_badblocks;

+}

+

+EXPORT_SYMBOL(get_jz_badblock_table);

+

+/*-------------------------------------------------------------------------*/

+

+static void jz_hwcontrol(struct mtd_info *mtd, int dat, u32 ctrl)

+{

+	struct nand_chip *this = (struct nand_chip *)(mtd->priv);

+	u32 nandaddr = (u32)this->IO_ADDR_W;

+	extern u8 nand_nce;  /* defined in nand_base.c, indicates which chip select is used for current nand chip */

+

+	if (ctrl & NAND_CTRL_CHANGE) {

+		if (ctrl & NAND_NCE) {

+			switch (nand_nce) {

+			case NAND_NCE1:

+				this->IO_ADDR_W = this->IO_ADDR_R = (void __iomem *)NAND_DATA_PORT1;

+				REG_NEMC_NFCSR = NEMC_NFCSR_NFCE1 | NEMC_NFCSR_NFE1;

+				break;

+			case NAND_NCE2:

+				this->IO_ADDR_W = this->IO_ADDR_R = (void __iomem *)NAND_DATA_PORT2;

+				REG_NEMC_NFCSR = NEMC_NFCSR_NFCE2 | NEMC_NFCSR_NFE2;

+				break;

+			case NAND_NCE3:

+				this->IO_ADDR_W = this->IO_ADDR_R = (void __iomem *)NAND_DATA_PORT3;

+				REG_NEMC_NFCSR = NEMC_NFCSR_NFCE3 | NEMC_NFCSR_NFE3;

+				break;

+			case NAND_NCE4:

+				this->IO_ADDR_W = this->IO_ADDR_R = (void __iomem *)NAND_DATA_PORT4;

+				REG_NEMC_NFCSR = NEMC_NFCSR_NFCE4 | NEMC_NFCSR_NFE4;

+				break;

+			default:

+				printk("error: no nand_nce 0x%x\n",nand_nce);

+				break;

+			}

+		} else {

+

+		  REG_NEMC_NFCSR = 0;

+		}

+

+		if (ctrl & NAND_ALE)

+			nandaddr = (u32)((u32)(this->IO_ADDR_W) | addr_offset);

+		else

+			nandaddr = (u32)((u32)(this->IO_ADDR_W) & ~addr_offset);

+		if (ctrl & NAND_CLE)

+			nandaddr = (u32)(nandaddr | cmd_offset);

+		else

+			nandaddr = (u32)(nandaddr & ~cmd_offset);

+	}

+

+	this->IO_ADDR_W = (void __iomem *)nandaddr;

+	if (dat != NAND_CMD_NONE) {

+		writeb(dat, this->IO_ADDR_W);

+		/* printk("write cmd:0x%x to 0x%x\n",dat,(u32)this->IO_ADDR_W); */

+	}

+}

+

+static int jz_device_ready(struct mtd_info *mtd)

+{

+	int ready, wait = 10;

+	while (wait--);

+	ready = ((REG_GPIO_PXPIN(0) & 0x00100000) ? 1 : 0);

+	return ready;

+}

+

+/*

+ * NEMC setup

+ */

+static void jz_device_setup(void)

+{

+// PORT 0:

+// PORT 1:

+// PORT 2:

+// PIN/BIT N		FUNC0		FUNC1

+//	21		CS1#		-

+//	22		CS2#		-

+//	23		CS3#		-

+//	24		CS4#		-

+#define GPIO_CS2_N (32*0+22)

+#define GPIO_CS3_N (32*0+23)

+#define GPIO_CS4_N (32*0+24)

+

+#ifdef CONFIG_MTD_NAND_BUS_WIDTH_16

+#define SMCR_VAL   0x0d444440

+//#define SMCR_VAL   0x0fff7740  //slowest

+	__gpio_as_nand_16bit(1);

+#else

+#define SMCR_VAL   0x0d444400

+//#define SMCR_VAL   0x0fff7700  //slowest

+	__gpio_as_nand_8bit(1);

+#endif

+

+	/* Read/Write timings */

+	REG_NEMC_SMCR1 = SMCR_VAL;

+

+#if defined(CONFIG_MTD_NAND_CS2)

+	__gpio_as_func0(GPIO_CS2_N);

+

+	/* Read/Write timings */

+	REG_NEMC_SMCR2 = SMCR_VAL;

+#endif

+

+#if defined(CONFIG_MTD_NAND_CS3)

+	__gpio_as_func0(GPIO_CS3_N);

+

+	/* Read/Write timings */

+	REG_NEMC_SMCR3 = SMCR_VAL;

+#endif

+

+#if defined(CONFIG_MTD_NAND_CS4)

+	__gpio_as_func0(GPIO_CS4_N);

+

+	/* Read/Write timings */

+	REG_NEMC_SMCR4 = SMCR_VAL;

+#endif

+}

+

+#ifdef CONFIG_MTD_HW_BCH_ECC

+

+static void jzsoc_nand_enable_bch_hwecc(struct mtd_info *mtd, int mode)

+{

+	struct nand_chip *this = (struct nand_chip *)(mtd->priv);

+	int eccsize = this->ecc.size;

+	int eccsteps = this->ecc.steps / this->planenum;

+	int oob_per_eccsize = this->ecc.layout->eccpos[0] / eccsteps;

+

+	REG_BCH_INTS = 0xffffffff;

+	if (mode == NAND_ECC_READ) {

+		__ECC_DECODING();

+		__ecc_cnt_dec((eccsize + oob_per_eccsize) * 2 + PAR_SIZE);

+#if defined(CONFIG_MTD_NAND_DMA)

+		__ecc_dma_enable();

+#endif

+	}

+

+	if (mode == NAND_ECC_WRITE) {

+		__ECC_ENCODING();

+		__ecc_cnt_enc((eccsize + oob_per_eccsize) * 2);

+#if defined(CONFIG_MTD_NAND_DMA)

+		__ecc_dma_enable();

+#endif

+	}

+}

+

+/**

+ * bch_correct

+ * @dat:        data to be corrected

+ * @idx:        the index of error bit in an eccsize

+ */

+static void bch_correct(struct mtd_info *mtd, u8 * dat, int idx)

+{

+	struct nand_chip *this = (struct nand_chip *)(mtd->priv);

+	int eccsize = this->ecc.size;

+	int eccsteps = this->ecc.steps / this->planenum;

+	int ecc_pos = this->ecc.layout->eccpos[0];

+	int oob_per_eccsize = ecc_pos / eccsteps;

+	int i, bit;		/* the 'bit' of i byte is error */

+

+	i = (idx - 1) >> 3;

+	bit = (idx - 1) & 0x7;

+

+	dprintk("error:i=%d, bit=%d\n",i,bit);

+

+	if (i < eccsize){

+		((struct buf_be_corrected *)dat)->data[i] ^= (1 << bit);

+	} else if (i < eccsize + oob_per_eccsize) {

+		((struct buf_be_corrected *)dat)->oob[i-eccsize] ^= (1 << bit);

+	}

+}

+

+#if defined(CONFIG_MTD_NAND_DMA)

+

+/**

+ * jzsoc_nand_bch_correct_data

+ * @mtd:	mtd info structure

+ * @dat:        data to be corrected

+ * @errs0:      pointer to the dma target buffer of bch decoding which stores BHINTS and

+ *              BHERR0~3(8-bit BCH) or BHERR0~1(4-bit BCH)

+ * @calc_ecc:   no used

+ */

+static int jzsoc_nand_bch_correct_data(struct mtd_info *mtd, u_char * dat, u_char * errs0, u_char * calc_ecc)

+{

+	u32 stat, i;

+	u32 *errs = (u32 *)errs0;

+	int ret = 0;

+

+	if (REG_BDMAC_DCCSR(0) & BDMAC_DCCSR_BERR) {

+		stat = errs[0];

+		dprintk("stat=%x err0:%x err1:%x \n", stat, errs[1], errs[2]);

+

+		if (stat & BCH_INTS_ERR) {

+			if (stat & BCH_INTS_UNCOR) {

+				printk("NAND: Uncorrectable ECC error\n");

+				return -1;

+			} else {

+				u32 errcnt = (stat & BCH_INTS_ERRC_MASK) >> BCH_INTS_ERRC_BIT;

+				if(errcnt > 24)

+				  printk("NAND:err count[%d] is too big\n",errcnt);

+				else

+				{

+					/*begin at the second DWORD*/

+					errs = (u32 *)&errs0[4];

+					for(i = 0;i < errcnt;i++)

+					{

+						/* errs[i>>1] get the error report regester value,

+						* (i+1) the error bit index.

+						* errs[i>>1] >> (((i + 1) % 2) << 4) means when error

+						* bit index is even, errs[i>>1] >> 16*/

+						bch_correct(mtd, dat, ((errs[i>>1] >> ((i % 2) << 4))) & BCH_ERR_INDEX_MASK);

+					}

+				}

+			}

+		}

+	}

+

+	return ret;

+}

+

+#else				/* cpu mode */

+

+/**

+ * jzsoc_nand_bch_correct_data

+ * @mtd:	mtd info structure

+ * @dat:        data to be corrected

+ * @read_ecc:   pointer to ecc buffer calculated when nand writing

+ * @calc_ecc:   no used

+ */

+static int jzsoc_nand_bch_correct_data(struct mtd_info *mtd, u_char * dat, u_char * read_ecc, u_char * calc_ecc)

+{

+	struct nand_chip *this = (struct nand_chip *)(mtd->priv);

+	int eccsize = this->ecc.size;

+	int eccbytes = this->ecc.bytes;

+	int eccsteps = this->ecc.steps / this->planenum;

+	int ecc_pos = this->ecc.layout->eccpos[0];

+	int oob_per_eccsize = ecc_pos / eccsteps;

+	short k;

+	u32 stat;

+	int ret = 0;

+

+	/* Write data to REG_BCH_DR */

+	for (k = 0; k < eccsize; k++) {

+		REG_BCH_DR = ((struct buf_be_corrected *)dat)->data[k];

+	}

+	/* Write oob to REG_BCH_DR */

+	for (k = 0; k < oob_per_eccsize; k++) {

+		REG_BCH_DR = ((struct buf_be_corrected *)dat)->oob[k];

+	}

+	/* Write parities to REG_BCH_DR */

+	for (k = 0; k < eccbytes; k++) {

+		REG_BCH_DR = read_ecc[k];

+	}

+

+	/* Wait for completion */

+	__ecc_decode_sync();

+	__ecc_disable();

+

+	/* Check decoding */

+	stat = REG_BCH_INTS;

+

+	if (stat & BCH_INTS_ERR) {

+		/* Error occurred */

+		if (stat & BCH_INTS_UNCOR) {

+			printk("NAND: Uncorrectable ECC error--\n");

+			return -1;

+		} else {

+			u32 errcnt = (stat & BCH_INTS_ERRC_MASK) >> BCH_INTS_ERRC_BIT;

+			switch (errcnt) {

+			case 24:

+				bch_correct(mtd, dat, (REG_BCH_ERR11 & BCH_ERR_INDEX_ODD_MASK) >> BCH_ERR_INDEX_ODD_BIT);

+				/* FALL-THROUGH */

+			case 23:

+				bch_correct(mtd, dat, (REG_BCH_ERR11 & BCH_ERR_INDEX_EVEN_MASK) >> BCH_ERR_INDEX_EVEN_BIT);

+				/* FALL-THROUGH */

+			case 22:

+				bch_correct(mtd, dat, (REG_BCH_ERR10 & BCH_ERR_INDEX_ODD_MASK) >> BCH_ERR_INDEX_ODD_BIT);

+				/* FALL-THROUGH */

+			case 21:

+				bch_correct(mtd, dat, (REG_BCH_ERR10 & BCH_ERR_INDEX_EVEN_MASK) >> BCH_ERR_INDEX_EVEN_BIT);

+				/* FALL-THROUGH */

+			case 20:

+				bch_correct(mtd, dat, (REG_BCH_ERR9 & BCH_ERR_INDEX_ODD_MASK) >> BCH_ERR_INDEX_ODD_BIT);

+				/* FALL-THROUGH */

+			case 19:

+				bch_correct(mtd, dat, (REG_BCH_ERR9 & BCH_ERR_INDEX_EVEN_MASK) >> BCH_ERR_INDEX_EVEN_BIT);

+				/* FALL-THROUGH */

+			case 18:

+				bch_correct(mtd, dat, (REG_BCH_ERR8 & BCH_ERR_INDEX_ODD_MASK) >> BCH_ERR_INDEX_ODD_BIT);

+				/* FALL-THROUGH */

+			case 17:

+				bch_correct(mtd, dat, (REG_BCH_ERR8 & BCH_ERR_INDEX_EVEN_MASK) >> BCH_ERR_INDEX_EVEN_BIT);

+				/* FALL-THROUGH */

+			case 16:

+				bch_correct(mtd, dat, (REG_BCH_ERR7 & BCH_ERR_INDEX_ODD_MASK) >> BCH_ERR_INDEX_ODD_BIT);

+				/* FALL-THROUGH */

+			case 15:

+				bch_correct(mtd, dat, (REG_BCH_ERR7 & BCH_ERR_INDEX_EVEN_MASK) >> BCH_ERR_INDEX_EVEN_BIT);

+				/* FALL-THROUGH */

+			case 14:

+				bch_correct(mtd, dat, (REG_BCH_ERR6 & BCH_ERR_INDEX_ODD_MASK) >> BCH_ERR_INDEX_ODD_BIT);

+				/* FALL-THROUGH */

+			case 13:

+				bch_correct(mtd, dat, (REG_BCH_ERR6 & BCH_ERR_INDEX_EVEN_MASK) >> BCH_ERR_INDEX_EVEN_BIT);

+				/* FALL-THROUGH */

+			case 12:

+				bch_correct(mtd, dat, (REG_BCH_ERR5 & BCH_ERR_INDEX_ODD_MASK) >> BCH_ERR_INDEX_ODD_BIT);

+				/* FALL-THROUGH */

+			case 11:

+				bch_correct(mtd, dat, (REG_BCH_ERR5 & BCH_ERR_INDEX_EVEN_MASK) >> BCH_ERR_INDEX_EVEN_BIT);

+				/* FALL-THROUGH */

+			case 10:

+				bch_correct(mtd, dat, (REG_BCH_ERR4 & BCH_ERR_INDEX_ODD_MASK) >> BCH_ERR_INDEX_ODD_BIT);

+				/* FALL-THROUGH */

+			case 9:

+				bch_correct(mtd, dat, (REG_BCH_ERR4 & BCH_ERR_INDEX_EVEN_MASK) >> BCH_ERR_INDEX_EVEN_BIT);

+				/* FALL-THROUGH */

+			case 8:

+				bch_correct(mtd, dat, (REG_BCH_ERR3 & BCH_ERR_INDEX_ODD_MASK) >> BCH_ERR_INDEX_ODD_BIT);

+				/* FALL-THROUGH */

+			case 7:

+				bch_correct(mtd, dat, (REG_BCH_ERR3 & BCH_ERR_INDEX_EVEN_MASK) >> BCH_ERR_INDEX_EVEN_BIT);

+				/* FALL-THROUGH */

+			case 6:

+				bch_correct(mtd, dat, (REG_BCH_ERR2 & BCH_ERR_INDEX_ODD_MASK) >> BCH_ERR_INDEX_ODD_BIT);

+				/* FALL-THROUGH */

+			case 5:

+				bch_correct(mtd, dat, (REG_BCH_ERR2 & BCH_ERR_INDEX_EVEN_MASK) >> BCH_ERR_INDEX_EVEN_BIT);

+				/* FALL-THROUGH */

+			case 4:

+				bch_correct(mtd, dat, (REG_BCH_ERR1 & BCH_ERR_INDEX_ODD_MASK) >> BCH_ERR_INDEX_ODD_BIT);

+				/* FALL-THROUGH */

+			case 3:

+				bch_correct(mtd, dat, (REG_BCH_ERR1 & BCH_ERR_INDEX_EVEN_MASK) >> BCH_ERR_INDEX_EVEN_BIT);

+				/* FALL-THROUGH */

+			case 2:

+				bch_correct(mtd, dat, (REG_BCH_ERR0 & BCH_ERR_INDEX_ODD_MASK) >> BCH_ERR_INDEX_ODD_BIT);

+				/* FALL-THROUGH */

+			case 1:

+				bch_correct(mtd, dat, (REG_BCH_ERR0 & BCH_ERR_INDEX_EVEN_MASK) >> BCH_ERR_INDEX_EVEN_BIT);

+				return 0;

+			default:

+				break;

+			}

+		}

+	}

+

+	return ret;

+}

+#endif				/* CONFIG_MTD_NAND_DMA */

+

+static int jzsoc_nand_calculate_bch_ecc(struct mtd_info *mtd, const u_char * dat, u_char * ecc_code)

+{

+	struct nand_chip *this = (struct nand_chip *)(mtd->priv);

+	int eccsize = this->ecc.size;

+	int eccbytes = this->ecc.bytes;

+	int eccsteps = this->ecc.steps / this->planenum;

+	int ecc_pos = this->ecc.layout->eccpos[0];

+	int oob_per_eccsize = ecc_pos / eccsteps;

+	volatile u8 *paraddr = (volatile u8 *)BCH_PAR0;

+	short i;

+

+	/* Write data to REG_BCH_DR */

+	for (i = 0; i < eccsize; i++) {

+		REG_BCH_DR = ((struct buf_be_corrected *)dat)->data[i];

+	}

+	/* Write oob to REG_BCH_DR */

+	for (i = 0; i < oob_per_eccsize; i++) {

+		REG_BCH_DR = ((struct buf_be_corrected *)dat)->oob[i];

+	}

+	__ecc_encode_sync();

+	__ecc_disable();

+

+	for (i = 0; i < eccbytes; i++) {

+		ecc_code[i] = *paraddr++;

+	}

+

+	return 0;

+}

+

+extern int nand_sw_bch_ops(struct mtd_info *mtd, u8 *oobdata, int ops);

+

+#if defined(CONFIG_MTD_NAND_DMA)

+

+/**

+ * nand_write_page_hwecc_bch - [REPLACABLE] hardware ecc based page write function

+ * @mtd:	mtd info structure

+ * @chip:	nand chip info structure

+ * @buf:	data buffer

+ */

+static void nand_write_page_hwecc_bch0(struct mtd_info *mtd, struct nand_chip *chip, const uint8_t * buf, u8 cmd_pgprog)

+{

+	int eccsize = chip->ecc.size;

+	int eccsteps = chip->ecc.steps / chip->planenum;

+	int eccbytes = chip->ecc.bytes;

+	int ecc_pos = chip->ecc.layout->eccpos[0];

+	int oob_per_eccsize = ecc_pos / eccsteps;

+	int pagesize = mtd->writesize / chip->planenum;

+	int oobsize = mtd->oobsize / chip->planenum;

+	int i, err, timeout;

+	const u8 *databuf;

+	u8 *oobbuf;

+	jz_bdma_desc_8word *desc;

+

+	nand_sw_bch_ops(mtd, (u8 *)chip->oob_poi, 1);

+

+#if defined(CONFIG_MTD_NAND_DMABUF)

+	memcpy(prog_buf, buf, pagesize);

+	memcpy(prog_buf + pagesize, chip->oob_poi, oobsize);

+	dma_cache_wback_inv((u32)prog_buf, pagesize + oobsize);

+#else

+	databuf = buf;

+	oobbuf = chip->oob_poi;

+

+	/* descriptors for encoding data blocks */

+	desc = dma_desc_enc;

+	for (i = 0; i < eccsteps; i++) {

+		desc->dsadr = CPHYSADDR((u32)databuf) + i * eccsize;	/* DMA source address */

+		desc->dtadr = CPHYSADDR((u32)oobbuf) + ecc_pos + i * eccbytes;	/* DMA target address */

+		dprintk("dma_desc_enc:desc:%x cmd:%x sadr:%x tadr:%x dadr:%x\n", (u32)desc, desc->dcmd, desc->dsadr, desc->dtadr,

+			desc->ddadr);

+		desc++;

+	}

+

+	/* descriptors for encoding oob blocks */

+	desc = dma_desc_enc1;

+	for (i = 0; i < eccsteps; i++) {

+		desc->dsadr = CPHYSADDR((u32)oobbuf) + oob_per_eccsize * i;	/* DMA source address, 28/4 = 7bytes */

+		desc->dtadr = CPHYSADDR((u32)oobbuf) + ecc_pos + i * eccbytes;	/* DMA target address */

+		dprintk("dma_desc_enc1:desc:%x cmd:%x sadr:%x tadr:%x dadr:%x\n", (u32)desc, desc->dcmd, desc->dsadr, desc->dtadr,

+			desc->ddadr);

+		desc++;

+	}

+

+	/* descriptor for nand programing data block */

+	desc = dma_desc_nand_prog;

+	desc->dsadr = CPHYSADDR((u32)databuf);	/* DMA source address */

+	desc->dtadr = CPHYSADDR((u32)chip->IO_ADDR_W);  /* It will be changed when using multiply chip select */

+	dprintk("dma_desc_nand_prog:desc:%x cmd:%x sadr:%x tadr:%x dadr:%x\n", (u32)desc, desc->dcmd, desc->dsadr, desc->dtadr,

+	       desc->ddadr);

+

+	/* descriptor for nand programing oob block */

+	desc++;

+	desc->dsadr = CPHYSADDR((u32)oobbuf);	/* DMA source address */

+	desc->dtadr = CPHYSADDR((u32)chip->IO_ADDR_W);  /* It will be changed when using multiply chip select */

+	dprintk("dma_desc_oob_prog:desc:%x cmd:%x sadr:%x tadr:%x dadr:%x\n", (u32)desc, desc->dcmd, desc->dsadr, desc->dtadr,

+	       desc->ddadr);

+

+	/* descriptor for __nand_cmd(CMD_PGPROG) */

+	desc++;

+	*pval_nand_cmd_pgprog = cmd_pgprog | 0x40000000;

+	desc->dsadr = CPHYSADDR((u32)pval_nand_cmd_pgprog);

+	desc->dtadr = CPHYSADDR((u32)chip->IO_ADDR_R);	/* DMA target address: cmdport */

+	if (cmd_pgprog == 0x10)

+		desc->dcmd |= BDMAC_DCMD_LINK;  /* __nand_sync() by a DMA descriptor */

+	else if (cmd_pgprog == 0x11)

+		desc->dcmd &= ~BDMAC_DCMD_LINK; /* __nand_sync() by polling */

+

+	dma_cache_wback_inv((u32)dma_desc_enc, (eccsteps * 2 + 2 + 4) * (sizeof(jz_bdma_desc_8word)));

+	dma_cache_wback_inv((u32)databuf, pagesize);

+	dma_cache_wback_inv((u32)oobbuf, oobsize);

+	/* 4*6: pval_nand_ddr, pval_nand_dcs, pval_bch_ddr, pval_bch_dcs, dummy, pval_nand_cmd_pgprog */

+	dma_cache_wback_inv((u32)pval_nand_ddr, 4 * 8); /* 8 words, a cache line */

+#endif

+

+	REG_BDMAC_DCCSR(bch_dma_chan) = 0;

+	REG_BDMAC_DCCSR(nand_dma_chan) = 0;

+

+	/* Setup DMA descriptor address */

+	REG_BDMAC_DDA(bch_dma_chan) = CPHYSADDR((u32)dma_desc_enc);

+#if USE_PN

+	REG_BDMAC_DDA(nand_dma_chan) = CPHYSADDR((u32)dma_desc_pPN);

+#else

+	REG_BDMAC_DDA(nand_dma_chan) = CPHYSADDR((u32)dma_desc_nand_prog);

+#endif

+

+	/* Setup request source */

+	REG_BDMAC_DRSR(bch_dma_chan) = BDMAC_DRSR_RS_BCH_ENC;

+	REG_BDMAC_DRSR(nand_dma_chan) = BDMAC_DRSR_RS_AUTO;

+

+	/* Setup DMA channel control/status register */

+	REG_BDMAC_DCCSR(bch_dma_chan) = BDMAC_DCCSR_DES8 | BDMAC_DCCSR_EN;	/* descriptor transfer, clear status, start channel */

+	/* Enable DMA */

+	REG_BDMAC_DMACR |= BDMAC_DMACR_DMAE;

+

+	/* Enable BCH encoding */

+	chip->ecc.hwctl(mtd, NAND_ECC_WRITE);

+

+	dma_ack1 = 0;

+	nand_status = NAND_PROG;

+

+	/* DMA doorbell set -- start DMA now ... */

+	__bdmac_channel_set_doorbell(bch_dma_chan);

+

+#if USE_IRQ

+	if (cmd_pgprog == 0x10) {

+		dprintk("nand prog before wake up\n");

+		do {

+			err = wait_event_interruptible_timeout(nand_prog_wait_queue, dma_ack1, 3 * HZ);

+		}while(err == -ERESTARTSYS);

+

+		nand_status = NAND_NONE;

+		dprintk("nand prog after wake up\n");

+		if (!err) {

+			printk("*** NAND WRITE, Warning, wait event 3s timeout!\n");

+			dump_jz_bdma_channel(0);

+			dump_jz_bdma_channel(nand_dma_chan);

+			printk("REG_BCH_CR=%x REG_BCH_CNT=0x%x REG_BCH_INTS=%x\n", REG_BCH_CR, REG_BCH_CNT, REG_BCH_INTS);

+		}

+		dprintk("timeout remain = %d\n", err);

+	} else if (cmd_pgprog == 0x11) {

+		timeout = 100000;

+		while ((!__bdmac_channel_transmit_end_detected(nand_dma_chan)) && (timeout--));

+		if (timeout <= 0)

+			printk("two-plane prog 0x11 timeout!\n");

+	}

+#else

+	timeout = 100000;

+	while ((!__bdmac_channel_transmit_end_detected(nand_dma_chan)) && (timeout--));

+	while(!chip->dev_ready(mtd));

+	if (timeout <= 0)

+		printk("not use irq, prog timeout!\n");

+#endif

+}

+

+static void nand_write_page_hwecc_bch(struct mtd_info *mtd, struct nand_chip *chip, const uint8_t * buf)

+{

+	nand_write_page_hwecc_bch0(mtd, chip, buf, 0x10);

+}

+

+static void nand_write_page_hwecc_bch_planes(struct mtd_info *mtd, struct nand_chip *chip, const uint8_t * buf)

+{

+	int page;

+	int pagesize = mtd->writesize >> 1;

+	int ppb = mtd->erasesize / mtd->writesize;

+

+	page = (global_page / ppb) * ppb + global_page; /* = global_page%ppb + (global_page/ppb)*ppb*2 */

+

+	/* send cmd 0x80, the MSB should be valid if realplane is 4 */

+	if (chip->realplanenum == 2)

+	{

+		if(global_mafid == 0x2c)

+			chip->cmdfunc(mtd, 0x80, 0x00, page);

+		else

+			chip->cmdfunc(mtd, 0x80, 0x00, 0x00);

+	}

+	else

+		chip->cmdfunc(mtd, 0x80, 0x00, page & (1 << (chip->chip_shift - chip->page_shift)));

+

+	nand_write_page_hwecc_bch0(mtd, chip, buf, 0x11);

+	chip->cmdfunc(mtd, 0x81, 0x00, page + ppb);

+	nand_write_page_hwecc_bch0(mtd, chip, buf + pagesize, 0x10);

+}

+

+#else	/* nand write in cpu mode */

+

+static void nand_write_page_hwecc_bch(struct mtd_info *mtd, struct nand_chip *chip,

+				  const uint8_t *buf)

+{

+	int i, eccsize = chip->ecc.size;

+	int eccbytes = chip->ecc.bytes;

+	int eccsteps = chip->ecc.steps / chip->planenum;

+	int oob_per_eccsize = chip->ecc.layout->eccpos[0] / eccsteps;

+	int oobsize = mtd->oobsize / chip->planenum;

+	int ecctotal = chip->ecc.total / chip->planenum;

+        uint8_t *p = (uint8_t *)buf;

+	uint8_t *ecc_calc = chip->buffers->ecccalc;

+	uint32_t *eccpos = chip->ecc.layout->eccpos;

+	static struct buf_be_corrected buf_calc0;

+	struct buf_be_corrected *buf_calc = &buf_calc0;

+

+	nand_sw_bch_ops(mtd, (u8 *)chip->oob_poi, 1);

+

+	for (i = 0; i < eccsteps; i++, p += eccsize) {

+		buf_calc->data = (u8 *)buf + eccsize * i;

+		buf_calc->oob = chip->oob_poi + oob_per_eccsize * i;

+		chip->ecc.hwctl(mtd, NAND_ECC_WRITE);

+		chip->ecc.calculate(mtd, (u8 *)buf_calc, &ecc_calc[eccbytes*i]);

+		chip->write_buf(mtd, p, eccsize);

+	}

+

+	for (i = 0; i < ecctotal; i++)

+		chip->oob_poi[eccpos[i]] = ecc_calc[i];

+

+	chip->write_buf(mtd, chip->oob_poi, oobsize);

+}

+

+/* nand write using two-plane mode */

+static void nand_write_page_hwecc_bch_planes(struct mtd_info *mtd, struct nand_chip *chip,

+					     const uint8_t *buf)

+{

+	int pagesize = mtd->writesize >> 1;

+	int ppb = mtd->erasesize / mtd->writesize;

+	int page;

+

+	page = (global_page / ppb) * ppb + global_page; /* = global_page%ppb + (global_page/ppb)*ppb*2 */

+

+	/* send cmd 0x80, the MSB should be valid if realplane is 4 */

+	if (chip->realplanenum == 2)

+	{

+		if(global_mafid == 0x2c)

+			chip->cmdfunc(mtd, 0x80, 0x00, page);

+		else

+			chip->cmdfunc(mtd, 0x80, 0x00, 0x00);

+	}

+	else

+		chip->cmdfunc(mtd, 0x80, 0x00, page & (1 << (chip->chip_shift - chip->page_shift)));

+

+	nand_write_page_hwecc_bch(mtd, chip, buf);

+

+	chip->cmdfunc(mtd, 0x11, -1, -1); /* send cmd 0x11 */

+	ndelay(100);

+	while(!chip->dev_ready(mtd));

+

+	chip->cmdfunc(mtd, 0x81, 0x00, page + ppb); /* send cmd 0x81 */

+	nand_write_page_hwecc_bch(mtd, chip, buf + pagesize);

+}

+#endif				/* CONFIG_MTD_NAND_DMA */

+

+/**

+ * nand_read_page_hwecc_bch - [REPLACABLE] hardware ecc based page read function

+ * @mtd:	mtd info structure

+ * @chip:	nand chip info structure

+ * @buf:	buffer to store read data

+ *

+ * Not for syndrome calculating ecc controllers which need a special oob layout

+ */

+#if defined(CONFIG_MTD_NAND_DMA)

+static int nand_read_page_hwecc_bch0(struct mtd_info *mtd, struct nand_chip *chip, uint8_t * buf, u32 page)

+{

+	int i, eccsize = chip->ecc.size;

+	int eccsteps = chip->ecc.steps / chip->planenum;

+	int eccbytes = chip->ecc.bytes;

+	int ecc_pos = chip->ecc.layout->eccpos[0];

+	int oob_per_eccsize = ecc_pos / eccsteps;

+	int pagesize = mtd->writesize / chip->planenum;

+	int oobsize = mtd->oobsize / chip->planenum;

+	u8 *databuf, *oobbuf;

+	jz_bdma_desc_8word *desc;

+	int err;

+	u32 addrport, cmdport;

+	static struct buf_be_corrected buf_correct0;

+

+	addrport = (u32)(chip->IO_ADDR_R) | addr_offset;

+ 	cmdport = (u32)(chip->IO_ADDR_R) | cmd_offset;

+

+#if defined(CONFIG_MTD_NAND_DMABUF)

+	databuf = read_buf;

+	oobbuf = read_buf + pagesize;

+

+	dma_cache_inv((u32)read_buf, pagesize + oobsize);	// databuf should be invalidated.

+	memset(errs, 0, eccsteps * ERRS_SIZE * 4);

+	dma_cache_wback_inv((u32)errs, eccsteps * ERRS_SIZE * 4);

+#else

+

+	databuf = buf;

+	oobbuf = chip->oob_poi;

+

+	/* descriptor for nand reading data block */

+	desc = dma_desc_nand_read;

+	desc->dsadr = CPHYSADDR((u32)chip->IO_ADDR_R); /* It will be changed when using multiply chip select */

+	desc->dtadr = CPHYSADDR((u32)databuf);	/* DMA target address */

+

+	dprintk("desc_nand_read:desc:%x cmd:%x sadr:%x tadr:%x dadr:%x\n", (u32)desc, desc->dcmd, desc->dsadr, desc->dtadr,

+	       desc->ddadr);

+

+	/* descriptor for nand reading oob block */

+	desc++;

+	desc->dsadr = CPHYSADDR((u32)chip->IO_ADDR_R); /* It will be changed when using multiply chip select */

+	desc->dtadr = CPHYSADDR((u32)oobbuf);	/* DMA target address */

+	dprintk("desc_oob_read:desc:%x cmd:%x sadr:%x tadr:%x dadr:%x\n", (u32)desc, desc->dcmd, desc->dsadr, desc->dtadr,

+	       desc->ddadr);

+

+	/* descriptors for data to be written to bch */

+	desc = dma_desc_dec;

+	for (i = 0; i < eccsteps; i++) {

+		desc->dsadr = CPHYSADDR((u32)databuf) + i * eccsize;	/* DMA source address */

+		dprintk("dma_desc_dec:desc:%x cmd:%x sadr:%x tadr:%x dadr:%x\n", (u32)desc, desc->dcmd, desc->dsadr, desc->dtadr,

+			desc->ddadr);

+		desc++;

+	}

+

+	/* descriptors for oob to be written to bch */

+	desc = dma_desc_dec1;

+	for (i = 0; i < eccsteps; i++) {

+		desc->dsadr = CPHYSADDR((u32)oobbuf) + oob_per_eccsize * i;	/* DMA source address */

+		dprintk("dma_desc_dec1:desc:%x cmd:%x sadr:%x tadr:%x dadr:%x\n", (u32)desc, desc->dcmd, desc->dsadr, desc->dtadr,

+			desc->ddadr);

+		desc++;

+	}

+

+	/* descriptors for parities to be written to bch */

+	desc = dma_desc_dec2;

+	for (i = 0; i < eccsteps; i++) {

+		desc->dsadr = CPHYSADDR((u32)oobbuf) + ecc_pos + i * eccbytes;	/* DMA source address */

+		dprintk("dma_desc_dec2:desc:%x cmd:%x sadr:%x tadr:%x dadr:%x\n", (u32)desc, desc->dcmd, desc->dsadr, desc->dtadr,

+			desc->ddadr);

+		desc++;

+	}

+

+	dma_cache_wback_inv((u32)dma_desc_nand_read, (2 + eccsteps * 3) * (sizeof(jz_bdma_desc_8word)));

+

+	memset(errs, 0, eccsteps * ERRS_SIZE * 4);

+	dma_cache_inv((u32)databuf, pagesize);	// databuf should be invalidated.

+	dma_cache_inv((u32)oobbuf, oobsize);	// oobbuf should be invalidated too

+	dma_cache_wback_inv((u32)errs, eccsteps * ERRS_SIZE * 4);

+#endif

+	REG_BDMAC_DCCSR(bch_dma_chan) = 0;

+	REG_BDMAC_DCCSR(nand_dma_chan) = 0;

+

+	/* Setup DMA descriptor address */

+#if USE_PN

+	REG_BDMAC_DDA(nand_dma_chan) = CPHYSADDR((u32)dma_desc_rPN);

+#else

+	REG_BDMAC_DDA(nand_dma_chan) = CPHYSADDR((u32)dma_desc_nand_read);

+#endif

+	REG_BDMAC_DDA(bch_dma_chan) = CPHYSADDR((u32)dma_desc_dec);

+

+	/* Setup request source */

+#if USE_PN

+	REG_BDMAC_DRSR(nand_dma_chan) = BDMAC_DRSR_RS_AUTO;

+#else

+	REG_BDMAC_DRSR(nand_dma_chan) = BDMAC_DRSR_RS_NAND0;

+#endif

+	REG_BDMAC_DRSR(bch_dma_chan) = BDMAC_DRSR_RS_BCH_DEC;

+

+	/* Enable DMA */

+	REG_BDMAC_DMACR |= BDMAC_DMACR_DMAE;

+

+	/* Enable BCH decoding */

+	chip->ecc.hwctl(mtd, NAND_ECC_READ);

+

+	dma_ack = 0;

+	nand_status = NAND_READ;

+	/* DMA doorbell set -- start nand DMA now ... */

+	__bdmac_channel_set_doorbell(nand_dma_chan);

+

+	/* Setup DMA channel control/status register */

+	REG_BDMAC_DCCSR(nand_dma_chan) = BDMAC_DCCSR_DES8 | BDMAC_DCCSR_EN;

+

+#define __nand_cmd(n)		(REG8(cmdport) = (n))

+#define __nand_addr(n)		(REG8(addrport) = (n))

+

+	__nand_cmd(NAND_CMD_READ0);

+

+	__nand_addr(0);

+	if (pagesize != 512)

+		__nand_addr(0);

+

+	__nand_addr(page & 0xff);

+	__nand_addr((page >> 8) & 0xff);

+

+	/* One more address cycle for the devices whose number of page address bits > 16  */

+	if (((chip->chipsize >> chip->page_shift) >> 16) > 0)

+		__nand_addr((page >> 16) & 0xff);

+

+	if (pagesize != 512)

+		__nand_cmd(NAND_CMD_READSTART);

+

+#if USE_IRQ

+	do {

+		err = wait_event_interruptible_timeout(nand_read_wait_queue, dma_ack, 3 * HZ);

+	}while(err == -ERESTARTSYS);

+	nand_status = NAND_NONE;

+

+	if (!err) {

+		printk("*** NAND READ, Warning, wait event 3s timeout!\n");

+		dump_jz_bdma_channel(0);

+		dump_jz_bdma_channel(nand_dma_chan);

+		printk("REG_BCH_CR=%x REG_BCH_CNT=0x%x REG_BCH_INTS=%x\n", REG_BCH_CR, REG_BCH_CNT, REG_BCH_INTS);

+	}

+	dprintk("timeout remain = %d\n", err);

+#else

+	int timeout;

+	timeout = 100000;

+	while ((!__bdmac_channel_transmit_end_detected(bch_dma_chan)) && (timeout--));

+	if (timeout <= 0) {

+		printk("not use irq, NAND READ timeout!\n");

+	}

+#endif

+

+	for (i = 0; i < eccsteps; i++) {

+		int stat;

+		struct buf_be_corrected *buf_correct = &buf_correct0;

+

+		buf_correct->data = databuf + eccsize * i;

+		buf_correct->oob = oobbuf + oob_per_eccsize * i;

+

+		stat = chip->ecc.correct(mtd, (u8 *)buf_correct, (u8 *)&errs[i * ERRS_SIZE], NULL);

+		if (stat < 0)

+		{

+			printk("ecc Uncorrectable:global_page = %d,chip->planenum = %d\n",global_page,chip->planenum);

+			mtd->ecc_stats.failed++;

+		}

+		else

+			mtd->ecc_stats.corrected += stat;

+	}

+

+#if defined(CONFIG_MTD_NAND_DMABUF)

+	memcpy(buf, read_buf, pagesize);

+	memcpy(chip->oob_poi, read_buf + pagesize, oobsize);

+#endif

+	return 0;

+}

+

+static int nand_read_page_hwecc_bch(struct mtd_info *mtd, struct nand_chip *chip, uint8_t * buf)

+{

+	u32 page = global_page;

+

+	nand_read_page_hwecc_bch0(mtd, chip, buf, page);

+	return 0;

+}

+

+static int nand_read_page_hwecc_bch_planes(struct mtd_info *mtd, struct nand_chip *chip, uint8_t * buf)

+{

+	u32 page;

+	int pagesize = mtd->writesize >> 1;

+	int ppb = mtd->erasesize / mtd->writesize;

+

+	page = (global_page / ppb) * ppb + global_page; /* = global_page%ppb + (global_page/ppb)*ppb*2 */

+

+        /* read 1st page */

+	nand_read_page_hwecc_bch0(mtd, chip, buf, page);

+

+        /* read 2nd page */

+	nand_read_page_hwecc_bch0(mtd, chip, buf + pagesize, page + ppb);

+	return 0;

+}

+

+#else	/* nand read in cpu mode */

+

+static int nand_read_page_hwecc_bch(struct mtd_info *mtd, struct nand_chip *chip, uint8_t * buf)

+{

+	int i, eccsize = chip->ecc.size;

+	int eccbytes = chip->ecc.bytes;

+	int eccsteps = chip->ecc.steps / chip->planenum;

+	int ecc_pos = chip->ecc.layout->eccpos[0];

+	int oob_per_eccsize = ecc_pos / eccsteps;

+	uint8_t *ecc_calc = chip->buffers->ecccalc;

+	uint8_t *ecc_code = chip->buffers->ecccode;

+	uint32_t *eccpos = chip->ecc.layout->eccpos;

+	int pagesize = mtd->writesize / chip->planenum;

+	int oobsize = mtd->oobsize / chip->planenum;

+	int ecctotal = chip->ecc.total / chip->planenum;

+	static struct buf_be_corrected buf_correct0;

+

+	chip->read_buf(mtd, buf, pagesize);

+	chip->read_buf(mtd, chip->oob_poi, oobsize);

+

+	for (i = 0; i < ecctotal; i++) {

+		ecc_code[i] = chip->oob_poi[eccpos[i]];

+	}

+

+	for (i = 0; i < eccsteps; i++) {

+		int stat;

+		struct buf_be_corrected *buf_correct = &buf_correct0;

+

+		buf_correct->data = buf + eccsize * i;

+		buf_correct->oob = chip->oob_poi + oob_per_eccsize * i;

+

+		chip->ecc.hwctl(mtd, NAND_ECC_READ);

+		stat = chip->ecc.correct(mtd, (u8 *)buf_correct, &ecc_code[eccbytes*i], &ecc_calc[eccbytes*i]);

+		if (stat < 0)

+		{

+			printk("ecc Uncorrectable:global_page = %d,chip->planenum = %d\n",global_page,chip->planenum);

+			mtd->ecc_stats.failed++;

+		}

+		else

+			mtd->ecc_stats.corrected += stat;

+	}

+

+	return 0;

+}

+

+static int nand_read_page_hwecc_bch_planes(struct mtd_info *mtd, struct nand_chip *chip, uint8_t * buf)

+{

+	int pagesize = mtd->writesize >> 1;

+	int ppb = mtd->erasesize / mtd->writesize;

+	uint32_t page;

+

+	page = (global_page / ppb) * ppb + global_page; /* = global_page%ppb + (global_page/ppb)*ppb*2 */

+

+	/* Read first page */

+	chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);

+	nand_read_page_hwecc_bch(mtd, chip, buf);

+

+	/* Read 2nd page */

+	chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page + ppb);

+	nand_read_page_hwecc_bch(mtd, chip, buf+pagesize);

+	return 0;

+}

+#endif				/* CONFIG_MTD_NAND_DMA */

+

+#endif				/* CONFIG_MTD_HW_BCH_ECC */

+

+/* read oob using two-plane mode */

+static int nand_read_oob_std_planes(struct mtd_info *mtd, struct nand_chip *chip,

+				    int global_page, int sndcmd)

+{

+	int page;

+	int oobsize = mtd->oobsize >> 1;

+	int ppb = mtd->erasesize / mtd->writesize;

+

+	page = (global_page / ppb) * ppb + global_page; /* = global_page%ppb + (global_page/ppb)*ppb*2 */

+

+	/* Read first page OOB */

+	if (sndcmd) {

+		chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);

+	}

+	chip->read_buf(mtd, chip->oob_poi, oobsize);

+	nand_sw_bch_ops(mtd, (u8 *)chip->oob_poi, 0);

+

+	/* Read second page OOB */

+	page += ppb;

+	if (sndcmd) {

+		chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);

+		sndcmd = 0;

+	}

+	chip->read_buf(mtd, chip->oob_poi+oobsize, oobsize);

+	nand_sw_bch_ops(mtd, (u8 *)chip->oob_poi + oobsize, 0);

+

+	return 0;

+}

+

+/* write oob using two-plane mode */

+static int nand_write_oob_std_planes(struct mtd_info *mtd, struct nand_chip *chip,

+				     int global_page)

+{

+	int status = 0, page;

+	const uint8_t *buf = chip->oob_poi;

+	int pagesize = mtd->writesize >> 1;

+	int oobsize = mtd->oobsize >> 1;

+	int ppb = mtd->erasesize / mtd->writesize;

+

+	page = (global_page / ppb) * ppb + global_page; /* = global_page%ppb + (global_page/ppb)*ppb*2 */

+

+	/* send cmd 0x80, the MSB should be valid if realplane is 4 */

+	if (chip->realplanenum == 2)

+	{

+		if(global_mafid == 0x2c)

+			chip->cmdfunc(mtd, 0x80, pagesize, page);

+		else

+			chip->cmdfunc(mtd, 0x80, pagesize, 0x00);

+	}

+	else

+		chip->cmdfunc(mtd, 0x80, pagesize, page & (1 << (chip->chip_shift - chip->page_shift)));

+

+	nand_sw_bch_ops(mtd, (u8 *)buf, 1);

+	chip->write_buf(mtd, buf, oobsize);

+	/* Send first command to program the OOB data */

+	chip->cmdfunc(mtd, 0x11, -1, -1);

+	ndelay(100);

+	status = chip->waitfunc(mtd, chip);

+

+	page += ppb;

+	buf += oobsize;

+	chip->cmdfunc(mtd, 0x81, pagesize, page);

+	nand_sw_bch_ops(mtd, (u8 *)buf, 1);

+	chip->write_buf(mtd, buf, oobsize);

+	/* Send command to program the OOB data */

+	chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);

+	/* Wait long R/B */

+	ndelay(100);

+	status = chip->waitfunc(mtd, chip);

+

+	return status & NAND_STATUS_FAIL ? -EIO : 0;

+}

+

+/* nand erase using two-plane mode */

+static void single_erase_cmd_planes(struct mtd_info *mtd, int global_page)

+{

+	struct nand_chip *chip = mtd->priv;

+	int page, ppb = mtd->erasesize / mtd->writesize;

+

+	page = (global_page / ppb) * ppb + global_page; /* = global_page%ppb + (global_page/ppb)*ppb*2 */

+

+	/* send cmd 0x60, the MSB should be valid if realplane is 4 */

+	if (chip->realplanenum == 2)

+	{

+		if(global_mafid == 0x2c)

+			chip->cmdfunc(mtd, 0x60, -1, page);

+		else

+			chip->cmdfunc(mtd, 0x60, -1, 0x00);

+	}

+	else

+		chip->cmdfunc(mtd, 0x60, -1, page & (1 << (chip->chip_shift - chip->page_shift)));

+

+	page += ppb;

+	chip->cmdfunc(mtd, 0x60, -1, page & (~(ppb-1))); /* send cmd 0x60 */

+

+	chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1); /* send cmd 0xd0 */

+	/* Do not need wait R/B or check status */

+}

+

+#if defined(CONFIG_MTD_NAND_DMA)

+

+#if USE_IRQ

+static irqreturn_t nand_dma_irq(int irq, void *dev_id)

+{

+	u8 dma_chan;

+	volatile int wakeup = 0;

+

+	dma_chan = irq - IRQ_BDMA_0;

+

+	dprintk("jz4770_dma_irq %d, channel %d\n", irq, dma_chan);

+

+	if (__bdmac_channel_transmit_halt_detected(dma_chan)) {

+		__bdmac_channel_clear_transmit_halt(dma_chan);

+		wakeup = 1;

+		printk("DMA HALT\n");

+	}

+

+	if (__bdmac_channel_address_error_detected(dma_chan)) {

+

+		REG_BDMAC_DCCSR(dma_chan) &= ~BDMAC_DCCSR_EN;	/* disable DMA */

+		__bdmac_channel_clear_address_error(dma_chan);

+

+		REG_BDMAC_DSAR(dma_chan) = 0;	/* reset source address register */

+		REG_BDMAC_DTAR(dma_chan) = 0;	/* reset destination address register */

+

+		/* clear address error in BDMACR */

+		REG_BDMAC_DMACR &= ~(1 << 2);

+		wakeup = 1;

+		printk("DMA address error!\n");

+	}

+

+#if 0

+

+	while (!__bdmac_channel_transmit_end_detected(dma_chan));

+

+	if (__bdmac_channel_count_terminated_detected(dma_chan)) {

+		dprintk("DMA CT\n");

+		__bdmac_channel_clear_count_terminated(dma_chan);

+		wakeup = 0;

+	}

+#endif

+

+	if (__bdmac_channel_transmit_end_detected(dma_chan)) {

+		dprintk("DMA TT\n");

+		REG_BDMAC_DCCSR(dma_chan) &= ~BDMAC_DCCSR_EN;	/* disable DMA */

+		__bdmac_channel_clear_transmit_end(dma_chan);

+		wakeup = 1;

+	}

+

+	if (wakeup) {

+		dprintk("ack %d irq , wake up dma_chan %d nand_status %d\n", dma_ack, dma_chan, nand_status);

+		/* wakeup wait event */

+		if ((dma_chan == nand_dma_chan) && (nand_status == NAND_PROG)) {

+			dprintk("nand prog dma irq, wake up----\n");

+			dma_ack1 = 1;

+			wake_up_interruptible(&nand_prog_wait_queue);

+		}

+

+		if ((dma_chan == bch_dma_chan) && (nand_status == NAND_READ)) {

+			dprintk("nand read irq, wake up----\n");

+			dma_ack = 1;

+			wake_up_interruptible(&nand_read_wait_queue);

+		}

+		wakeup = 0;

+	}

+

+	return IRQ_HANDLED;

+}

+#endif				/* USE_IRQ */

+

+static int jz4770_nand_dma_init(struct mtd_info *mtd)

+{

+	struct nand_chip *chip = mtd->priv;

+	int eccsize = chip->ecc.size;

+	int eccsteps = chip->ecc.steps / chip->planenum;

+	int eccbytes = chip->ecc.bytes;

+	int ecc_pos = chip->ecc.layout->eccpos[0];

+	int oob_per_eccsize = ecc_pos / eccsteps;

+	int pagesize = mtd->writesize / chip->planenum;

+	int oobsize = mtd->oobsize / chip->planenum;

+	int i, err;

+	jz_bdma_desc_8word *desc, *dma_desc_bch_ddr, *dma_desc_nand_ddr, *dma_desc_nand_cmd_pgprog;

+	u32  *pval_nand_dcs, *pval_bch_ddr, *pval_bch_dcs, *dummy;

+	u32 next;

+#if defined(CONFIG_MTD_NAND_DMABUF)

+	u8 *oobbuf;

+#endif

+

+#if USE_IRQ

+	if ((err = request_irq(IRQ_BDMA_0 + nand_dma_chan, nand_dma_irq, IRQF_DISABLED, "nand_dma", NULL))) {

+		printk("can't reqeust DMA nand channel.\n");

+		return 0;

+	}

+

+	if ((err = request_irq(IRQ_BDMA_0 + bch_dma_chan, nand_dma_irq, IRQF_DISABLED, "bch_dma", NULL))) {

+		printk("bch_dma irq request err\n");

+		return 0;

+	}

+#endif

+

+#if USE_PN

+	dma_desc_pPN = (jz_bdma_desc_8word *)__get_free_page(GFP_KERNEL);

+	dma_desc_rPN = (jz_bdma_desc_8word *)__get_free_page(GFP_KERNEL);

+	pn_buf = kmalloc(2 * sizeof(unsigned int), GFP_KERNEL);

+

+	memset(dma_desc_pPN, 0, 4096);

+	memset(dma_desc_rPN, 0, 4096);

+	memset(pn_buf, 0, 2 * sizeof(unsigned int));

+

+	#if USE_COUNTER

+		*pn_buf = PN_ENABLE | COUNTER_ENABLE;

+		#if COUNT_0

+		    *pn_buf |= COUNT_FOR_0;

+		#endif

+	#else

+		*pn_buf = PN_ENABLE;

+	#endif

+

+	*(pn_buf + 1) = PN_DISABLE;

+	dma_cache_wback_inv((unsigned int)pn_buf, 2 * sizeof(unsigned int));

+#endif	/* USE_PN */

+

+	__bdmac_channel_enable_clk(nand_dma_chan);

+	__bdmac_channel_enable_clk(bch_dma_chan);

+

+#if defined(CONFIG_MTD_NAND_DMABUF)

+	if (pagesize < 4096) {

+		read_buf = prog_buf = (u8 *) __get_free_page(GFP_KERNEL);

+	} else {

+		read_buf = prog_buf = (u8 *) __get_free_pages(GFP_KERNEL, 1);

+	}

+	if (!read_buf)

+		return -ENOMEM;

+#endif

+	/* space for the error reports of bch decoding((4 * ERRS_SIZE * eccsteps) bytes), and the space for the value

+     * of ddr and dcs of channel 0 and channel nand_dma_chan (4 * (2 + 2) bytes) */

+	errs = (u32 *)kmalloc(4 * (2 + 2 + ERRS_SIZE * eccsteps), GFP_KERNEL);

+	if (!errs)

+		return -ENOMEM;

+

+	pval_nand_ddr = errs + ERRS_SIZE * eccsteps;

+	pval_nand_dcs = pval_nand_ddr + 1;

+	pval_bch_ddr = pval_nand_dcs + 1;

+	pval_bch_dcs = pval_bch_ddr + 1;

+    /* space for nand prog waiting target, the content is useless */

+	dummy = pval_bch_dcs + 1;

+    /* space to store CMD_PGPROG(0x10) or 0x11 */

+	pval_nand_cmd_pgprog = (u32 *)(dummy + 1);

+

+	/* desc can't across 4KB boundary, as desc base address is fixed */

+	/* space of descriptors for nand reading data and oob blocks */

+	dma_desc_nand_read = (jz_bdma_desc_8word *) __get_free_page(GFP_KERNEL);

+	if (!dma_desc_nand_read)

+		return -ENOMEM;

+	memset(dma_desc_nand_read, 0 ,4096);

+

+	/* space of descriptors for bch decoding */

+	dma_desc_dec = dma_desc_nand_read + 2;

+	dma_desc_dec1 = dma_desc_dec + eccsteps;

+	dma_desc_dec2 = dma_desc_dec + eccsteps * 2;

+

+	/* space of descriptors for notifying bch channel */

+	dma_desc_bch_ddr = dma_desc_dec2 + eccsteps;

+

+	/* space of descriptors for bch encoding */

+	dma_desc_enc = dma_desc_bch_ddr + 2;

+	dma_desc_enc1 = dma_desc_enc + eccsteps;

+

+	/* space of descriptors for nand programing data and oob blocks */

+	dma_desc_nand_prog = dma_desc_enc1 + eccsteps;

+

+        /* space of descriptors for nand prog waiting, including pgprog and sync */

+	dma_desc_nand_cmd_pgprog = dma_desc_nand_prog + 2;

+

+	/* space of descriptors for notifying nand channel, including ddr and dcsr */

+	dma_desc_nand_ddr = dma_desc_nand_cmd_pgprog + 2;

+

+/*************************************

+ * Setup of nand programing descriptors

+ *************************************/

+#if defined(CONFIG_MTD_NAND_DMABUF)

+	oobbuf = prog_buf + pagesize;

+#endif

+	/* set descriptor for encoding data blocks */

+	desc = dma_desc_enc;

+	for (i = 0; i < eccsteps; i++) {

+		next = CPHYSADDR((u32)dma_desc_enc1) + i * (sizeof(jz_bdma_desc_8word));

+

+		desc->dcmd =

+		    BDMAC_DCMD_SAI | BDMAC_DCMD_DAI | BDMAC_DCMD_SWDH_32 | BDMAC_DCMD_DWDH_8 |

+		    BDMAC_DCMD_DS_BCH | BDMAC_DCMD_LINK;

+#if defined(CONFIG_MTD_NAND_DMABUF)

+		desc->dsadr = CPHYSADDR((u32)prog_buf) + i * eccsize;	/* DMA source address */

+		desc->dtadr = CPHYSADDR((u32)oobbuf) + ecc_pos + i * eccbytes;	/* DMA target address */

+#endif

+		desc->dcnt = eccsize / DIV_DS_BCH;	/* size: eccsize bytes */

+		desc->dreqt = BDMAC_DRSR_RS_BCH_ENC;

+		desc->ddadr = next;

+		dprintk("cmd:%x sadr:%x tadr:%x dadr:%x\n", desc->dcmd, desc->dsadr, desc->dtadr, desc->ddadr);

+		desc++;

+	}

+

+	/* set descriptor for encoding oob blocks */

+	desc = dma_desc_enc1;

+	for (i = 0; i < eccsteps; i++) {

+		next = CPHYSADDR((u32)dma_desc_enc) + (i + 1) * (sizeof(jz_bdma_desc_8word));

+

+		desc->dcmd =

+		    BDMAC_DCMD_BLAST | BDMAC_DCMD_SAI | BDMAC_DCMD_DAI | BDMAC_DCMD_SWDH_8 |

+		    BDMAC_DCMD_DWDH_8 | BDMAC_DCMD_DS_8BIT | BDMAC_DCMD_LINK;

+#if defined(CONFIG_MTD_NAND_DMABUF)

+		desc->dsadr = CPHYSADDR((u32)oobbuf) + oob_per_eccsize * i;	/* DMA source address, 28/4 = 7bytes */

+		desc->dtadr = CPHYSADDR((u32)oobbuf) + ecc_pos + i * eccbytes;	/* DMA target address */

+#endif

+		desc->dcnt = oob_per_eccsize;	/* size: 7 bytes -> 2 words */

+		desc->dreqt = BDMAC_DRSR_RS_BCH_ENC;

+		desc->ddadr = next;

+		dprintk("cmd:%x sadr:%x tadr:%x dadr:%x\n", desc->dcmd, desc->dsadr, desc->dtadr, desc->ddadr);

+		desc++;

+	}

+

+	next = CPHYSADDR((u32)dma_desc_nand_ddr);

+	desc--;

+	desc->ddadr = next;

+

+	/* set the descriptor to set door bell of nand_dma_chan for programing nand */

+	desc = dma_desc_nand_ddr;

+	*pval_nand_ddr = 1 << nand_dma_chan;

+	next = CPHYSADDR((u32)dma_desc_nand_ddr) + sizeof(jz_bdma_desc_8word);

+	desc->dcmd = BDMAC_DCMD_SWDH_32 | BDMAC_DCMD_DWDH_32 | BDMAC_DCMD_DS_32BIT | BDMAC_DCMD_LINK;

+	desc->dsadr = CPHYSADDR((u32)pval_nand_ddr);	/* DMA source address */

+	desc->dtadr = CPHYSADDR(BDMAC_DMADBSR);	/* nand_dma_chan's descriptor addres register */

+	desc->dcnt = 1;	/* size: 1 word */

+	desc->dreqt = BDMAC_DRSR_RS_AUTO;

+	desc->ddadr = next;

+	dprintk("*pval_nand_ddr=0x%x\n", *pval_nand_ddr);

+

+	/* set the descriptor to write dccsr of nand_dma_chan for programing nand, dccsr should be set at last */

+	desc++;

+	*pval_nand_dcs = BDMAC_DCCSR_DES8 | BDMAC_DCCSR_EN;	/* set value for writing ddr to enable channel nand_dma_chan */

+	desc->dcmd = BDMAC_DCMD_SWDH_32 | BDMAC_DCMD_DWDH_32 | BDMAC_DCMD_DS_32BIT;

+	desc->dsadr = CPHYSADDR((u32)pval_nand_dcs);	/* DMA source address */

+	desc->dtadr = CPHYSADDR(BDMAC_DCCSR(nand_dma_chan));	/* address of dma door bell set register */

+	desc->dcnt = 1;	/* size: 1 word */

+	desc->dreqt = BDMAC_DRSR_RS_AUTO;

+	dprintk("*pval_nand_dcs=0x%x\n", *pval_nand_dcs);

+

+#if USE_PN

+	desc = dma_desc_pPN;

+	next = CPHYSADDR((u32)dma_desc_nand_prog);

+	desc->dcmd = BDMAC_DCMD_SWDH_32 | BDMAC_DCMD_DWDH_32 | BDMAC_DCMD_DS_32BIT | BDMAC_DCMD_LINK;

+	desc->dsadr = CPHYSADDR((unsigned int)pn_buf);    /* DMA source address */

+	desc->dtadr = CPHYSADDR(NEMC_PNCR); /* DMA target address */

+	desc->dcnt = 1;   /* size: 6 words */

+	desc->dreqt = BDMAC_DRSR_RS_AUTO;

+	desc->ddadr = next;

+#endif

+

+	/* set descriptor for nand programing data block */

+	desc = dma_desc_nand_prog;

+	next = CPHYSADDR((u32)dma_desc_nand_prog) + sizeof(jz_bdma_desc_8word);

+	desc->dcmd =

+	    BDMAC_DCMD_SAI | BDMAC_DCMD_DAI | BDMAC_DCMD_SWDH_32 | BDMAC_DCMD_DWDH_32 |

+	    BDMAC_DCMD_DS_NAND | BDMAC_DCMD_LINK;

+#if USE_DIRECT

+	desc->dcmd |= BDMAC_DCMD_NWR;

+#endif

+#if defined(CONFIG_MTD_NAND_DMABUF)

+	desc->dsadr = CPHYSADDR((u32)prog_buf);	/* DMA source address */

+#endif

+	desc->dtadr = CPHYSADDR((u32)(chip->IO_ADDR_W)); /* DMA target address */

+	desc->dcnt = pagesize / DIV_DS_NAND;	/* size: eccsize bytes */

+	desc->dreqt = BDMAC_DRSR_RS_AUTO;

+	desc->ddadr = next;

+	dprintk("cmd:%x sadr:%x tadr:%x dadr:%x\n", desc->dcmd, desc->dsadr, desc->dtadr, desc->ddadr);

+

+	/* set descriptor for nand programing oob block */

+	desc++;

+#if USE_PN

+	next = CPHYSADDR((unsigned long)dma_desc_pPN + sizeof(jz_bdma_desc_8word));

+#else

+	next = CPHYSADDR((u32)dma_desc_nand_cmd_pgprog);

+#endif

+	desc->dcmd =

+	    BDMAC_DCMD_SAI | BDMAC_DCMD_DAI | BDMAC_DCMD_SWDH_32 | BDMAC_DCMD_DWDH_32 |

+	    BDMAC_DCMD_DS_NAND | BDMAC_DCMD_LINK;

+#if USE_DIRECT

+	desc->dcmd |= BDMAC_DCMD_NWR;

+#endif

+#if defined(CONFIG_MTD_NAND_DMABUF)

+	desc->dsadr = CPHYSADDR((u32)oobbuf);                	/* DMA source address */

+#endif

+	desc->dtadr = CPHYSADDR((u32)(chip->IO_ADDR_W));	/* DMA target address: dataport */

+	desc->dcnt = oobsize / DIV_DS_NAND;            	/* size: eccsize bytes */

+	desc->dreqt = BDMAC_DRSR_RS_AUTO;

+	desc->ddadr = next;

+	dprintk("cmd:%x sadr:%x tadr:%x dadr:%x\n", desc->dcmd, desc->dsadr, desc->dtadr, desc->ddadr);

+

+#if USE_PN

+	desc = dma_desc_pPN + 1;

+	next = CPHYSADDR((u32)dma_desc_nand_cmd_pgprog);

+	desc->dcmd = BDMAC_DCMD_SWDH_32 | BDMAC_DCMD_DWDH_32 | BDMAC_DCMD_DS_32BIT | BDMAC_DCMD_LINK;

+	desc->dsadr = CPHYSADDR((unsigned int)pn_buf) + 4;    /* DMA source address */

+	desc->dtadr = CPHYSADDR(NEMC_PNCR); /* DMA target address */

+	desc->dcnt = 1;   /* size: 6 words */

+	desc->dreqt = BDMAC_DRSR_RS_AUTO;

+	desc->ddadr = next;

+#endif

+

+	/* set descriptor for __nand_cmd(CMD_PGPROG) */

+	desc = dma_desc_nand_cmd_pgprog;

+	*pval_nand_cmd_pgprog = NAND_CMD_PAGEPROG | 0x40000000;

+	next = CPHYSADDR((u32)dma_desc_nand_cmd_pgprog) + sizeof(jz_bdma_desc_8word);

+	desc->dcmd =

+	    BDMAC_DCMD_NAC | BDMAC_DCMD_SWDH_32 | BDMAC_DCMD_DWDH_XX | BDMAC_DCMD_DS_32BIT | BDMAC_DCMD_LINK;

+	desc->dsadr = CPHYSADDR((u32)pval_nand_cmd_pgprog);	        /* DMA source address */

+	desc->dtadr = CPHYSADDR((u32)chip->IO_ADDR_R);	/* DMA target address: cmdport */

+	desc->dcnt = 1;	                        /* size: 1 byte */

+	desc->dnt = 0;

+	desc->dreqt = BDMAC_DRSR_RS_AUTO;

+	desc->ddadr = next;

+	dprintk("cmd:%x sadr:%x tadr:%x dadr:%x\n", desc->dcmd, desc->dsadr, desc->dtadr, desc->ddadr);

+

+	/* set descriptor for __nand_sync() */

+	desc++;

+#if USE_IRQ

+	desc->dcmd =

+		BDMAC_DCMD_SWDH_32 | BDMAC_DCMD_DWDH_32 | BDMAC_DCMD_DS_32BIT | BDMAC_DCMD_TIE;

+#else

+	desc->dcmd =

+		BDMAC_DCMD_SWDH_32 | BDMAC_DCMD_DWDH_32 | BDMAC_DCMD_DS_32BIT;

+#endif

+	desc->dsadr = CPHYSADDR((u32)pval_nand_ddr);	/* DMA source address */

+	desc->dtadr = CPHYSADDR((u32)dummy);        	/* DMA target address, the content is useless */

+	desc->dcnt = 1;             	/* size: 1 word */

+	desc->dnt = 1;

+	desc->dreqt = BDMAC_DRSR_RS_NAND0;

+	dprintk("1cmd:%x sadr:%x tadr:%x dadr:%x\n", desc->dcmd, desc->dsadr, desc->dtadr, desc->ddadr);

+

+	/* eccsteps*2 + 2 + 2 + 2:

+		dma_desc_enc + dma_desc_enc1 + dma_desc_nand_prog(oob) + dma_desc_nand_ddr(csr)

+		+ dma_desc_nand_cmd_pgprog(sync) */

+	dma_cache_wback_inv((u32)dma_desc_enc, (eccsteps * 2 + 2 + 2 + 2) * (sizeof(jz_bdma_desc_8word)));

+	/* 4*6: pval_nand_ddr, pval_nand_dcs, pval_bch_ddr, pval_bch_dcs, dummy, pval_nand_cmd_pgprog */

+	dma_cache_wback_inv((u32)pval_nand_ddr, 4 * 8); /* 8 words, a cache line */

+#if USE_PN

+	dma_cache_wback_inv((unsigned long)dma_desc_pPN, 2*(sizeof(jz_bdma_desc_8word)));

+#endif

+

+/*************************************

+ * Setup of nand reading descriptors

+ *************************************/

+#if defined(CONFIG_MTD_NAND_DMABUF)

+	oobbuf = read_buf + pagesize;

+#endif

+

+#if USE_PN

+	desc = dma_desc_rPN;

+	next = CPHYSADDR((u32)dma_desc_nand_read);

+	desc->dcmd = BDMAC_DCMD_SWDH_32 | BDMAC_DCMD_DWDH_32 | BDMAC_DCMD_DS_32BIT | BDMAC_DCMD_LINK;

+	desc->dsadr = CPHYSADDR((u32)pn_buf);    /* DMA source address */

+	desc->dtadr = CPHYSADDR(NEMC_PNCR); /* DMA target address */

+	desc->dcnt = 1;   /* size: 6 words */

+	desc->dreqt = BDMAC_DRSR_RS_AUTO;

+	desc->ddadr = next;

+#endif

+

+	/* set descriptor for nand reading data block */

+	desc = dma_desc_nand_read;

+	next = CPHYSADDR((u32)dma_desc_nand_read) + sizeof(jz_bdma_desc_8word);

+	desc->dcmd =

+	    BDMAC_DCMD_SAI | BDMAC_DCMD_DAI | BDMAC_DCMD_SWDH_32 | BDMAC_DCMD_DWDH_32 |

+	    BDMAC_DCMD_DS_NAND | BDMAC_DCMD_LINK;

+#if USE_DIRECT

+	desc->dcmd |= BDMAC_DCMD_NRD;

+#endif

+	desc->dsadr = CPHYSADDR((u32)(chip->IO_ADDR_R));	/* DMA source address */

+#if defined(CONFIG_MTD_NAND_DMABUF)

+	desc->dtadr = CPHYSADDR((u32)read_buf);	/* DMA target address */

+#endif

+	desc->dcnt = pagesize / DIV_DS_NAND;	/* size: eccsize bytes */

+	desc->dreqt = BDMAC_DRSR_RS_NAND0;

+	desc->ddadr = next;

+	dprintk("cmd:%x sadr:%x tadr:%x dadr:%x\n", desc->dcmd, desc->dsadr, desc->dtadr, desc->ddadr);

+

+	/* set descriptor for nand reading oob block */

+	desc++;

+#if USE_PN

+	next = CPHYSADDR((u32)dma_desc_rPN + sizeof(jz_bdma_desc_8word));

+#else

+	next = CPHYSADDR((u32)dma_desc_bch_ddr);

+#endif

+	desc->dcmd =

+	    BDMAC_DCMD_SAI | BDMAC_DCMD_DAI | BDMAC_DCMD_SWDH_32 | BDMAC_DCMD_DWDH_32 |

+	    BDMAC_DCMD_DS_NAND | BDMAC_DCMD_LINK;

+#if USE_DIRECT

+	desc->dcmd |= BDMAC_DCMD_NRD;

+#endif

+	desc->dsadr = CPHYSADDR((u32)(chip->IO_ADDR_R));	/* DMA source address */

+#if defined(CONFIG_MTD_NAND_DMABUF)

+	desc->dtadr = CPHYSADDR((u32)oobbuf);	/* DMA target address */

+#endif

+	desc->dcnt = oobsize / DIV_DS_NAND;	/* size: eccsize bytes */

+	desc->dreqt = BDMAC_DRSR_RS_AUTO;

+	desc->ddadr = next;

+	dprintk("cmd:%x sadr:%x tadr:%x dadr:%x\n", desc->dcmd, desc->dsadr, desc->dtadr, desc->ddadr);

+

+#if USE_PN

+	desc = dma_desc_rPN + 1;

+	next = CPHYSADDR((u32)dma_desc_bch_ddr);

+	desc->dcmd = BDMAC_DCMD_SWDH_32 | BDMAC_DCMD_DWDH_32 | BDMAC_DCMD_DS_32BIT | BDMAC_DCMD_LINK;

+	desc->dsadr = CPHYSADDR((u32)pn_buf) + 4;    /* DMA source address */

+	desc->dtadr = CPHYSADDR(NEMC_PNCR); /* DMA target address */

+	desc->dcnt = 1;   /* size: 6 words */

+	desc->dreqt = BDMAC_DRSR_RS_AUTO;

+	desc->ddadr = next;

+#endif

+

+	/* set the descriptor to set door bell for bch */

+	desc = dma_desc_bch_ddr;

+	*pval_bch_ddr = BDMAC_DMADBSR_DBS0;	// set value for writing ddr to enable channel 0

+	next = CPHYSADDR((u32)dma_desc_bch_ddr) + sizeof(jz_bdma_desc_8word);

+	desc->dcmd = BDMAC_DCMD_SWDH_32 | BDMAC_DCMD_DWDH_32 | BDMAC_DCMD_DS_32BIT | BDMAC_DCMD_LINK;

+	desc->dsadr = CPHYSADDR((u32)pval_bch_ddr);	/* DMA source address */

+	desc->dtadr = CPHYSADDR(BDMAC_DMADBSR);	/* channel 1's descriptor addres register */

+	desc->dcnt = 1;	/* size: 1 word */

+	desc->dreqt = BDMAC_DRSR_RS_AUTO;

+	desc->ddadr = next;

+

+	/* set descriptor for writing dcsr */

+	desc++;

+	*pval_bch_dcs = BDMAC_DCCSR_DES8 | BDMAC_DCCSR_EN;	// set value for writing ddr to enable channel 1

+	desc->dcmd = BDMAC_DCMD_SWDH_32 | BDMAC_DCMD_DWDH_32 | BDMAC_DCMD_DS_32BIT;

+	desc->dsadr = CPHYSADDR((u32)pval_bch_dcs);	/* DMA source address */

+	desc->dtadr = CPHYSADDR(BDMAC_DCCSR(bch_dma_chan));	/* address of dma door bell set register */

+	desc->dcnt = 1;	/* size: 1 word */

+	desc->dreqt = BDMAC_DRSR_RS_AUTO;

+

+	/* descriptors for data to be written to bch */

+	desc = dma_desc_dec;

+	for (i = 0; i < eccsteps; i++) {

+		next = CPHYSADDR((u32)dma_desc_dec1 + i * (sizeof(jz_bdma_desc_8word)));

+

+		desc->dcmd =

+		    BDMAC_DCMD_SAI | BDMAC_DCMD_DAI | BDMAC_DCMD_SWDH_32 | BDMAC_DCMD_DWDH_32 |

+		    BDMAC_DCMD_DS_BCH | BDMAC_DCMD_LINK;

+#if defined(CONFIG_MTD_NAND_DMABUF)

+		desc->dsadr = CPHYSADDR((u32)read_buf) + i * eccsize;	/* DMA source address */

+#endif

+		desc->dtadr = CPHYSADDR((u32)errs) + i * 4 * ERRS_SIZE;	/* DMA target address */

+		desc->dcnt = eccsize / DIV_DS_BCH;	/* size: eccsize bytes */

+		desc->dreqt = BDMAC_DRSR_RS_BCH_DEC;

+		desc->ddadr = next;

+		dprintk("desc:%x cmd:%x sadr:%x tadr:%x dadr:%x\n", (u32)desc, desc->dcmd, desc->dsadr, desc->dtadr,

+			desc->ddadr);

+		desc++;

+	}

+

+	/* descriptors for oob to be written to bch */

+	desc = dma_desc_dec1;

+	for (i = 0; i < eccsteps; i++) {

+		next = CPHYSADDR((u32)dma_desc_dec2 + i * (sizeof(jz_bdma_desc_8word)));

+

+		desc->dcmd =

+		    BDMAC_DCMD_SAI | BDMAC_DCMD_DAI | BDMAC_DCMD_SWDH_8 | BDMAC_DCMD_DWDH_32 |

+		    BDMAC_DCMD_DS_8BIT | BDMAC_DCMD_LINK;

+#if defined(CONFIG_MTD_NAND_DMABUF)

+		desc->dsadr = CPHYSADDR((u32)oobbuf) + oob_per_eccsize * i;	/* DMA source address */

+#endif

+		desc->dtadr = CPHYSADDR((u32)errs) + i * 4 * ERRS_SIZE;	/* DMA target address */

+		desc->dcnt = oob_per_eccsize;	/* size: 7 bytes */

+		desc->dreqt = BDMAC_DRSR_RS_BCH_DEC;

+		desc->ddadr = next;

+		dprintk("desc:%x cmd:%x sadr:%x tadr:%x dadr:%x\n", (u32)desc, desc->dcmd, desc->dsadr, desc->dtadr,

+			desc->ddadr);

+		desc++;

+	}

+

+	/* descriptors for parities to be written to bch */

+	desc = dma_desc_dec2;

+	for (i = 0; i < eccsteps; i++) {

+		next = CPHYSADDR((u32)dma_desc_dec) + (i + 1) * (sizeof(jz_bdma_desc_8word));

+

+		desc->dcmd =

+		    BDMAC_DCMD_BLAST | BDMAC_DCMD_SAI | BDMAC_DCMD_DAI | BDMAC_DCMD_SWDH_8 |

+		    BDMAC_DCMD_DWDH_32 | BDMAC_DCMD_DS_32BIT | BDMAC_DCMD_LINK;

+#if defined(CONFIG_MTD_NAND_DMABUF)

+		desc->dsadr = CPHYSADDR((u32)oobbuf) + ecc_pos + i * eccbytes;	/* DMA source address */

+#endif

+		desc->dtadr = CPHYSADDR((u32)errs) + i * 4 * ERRS_SIZE;	/* DMA target address */

+		desc->dcnt = (eccbytes + 3) / 4;	/* size: eccbytes bytes */

+		desc->dreqt = BDMAC_DRSR_RS_BCH_DEC;

+		desc->ddadr = next;

+		dprintk("desc:%x cmd:%x sadr:%x tadr:%x dadr:%x\n", (u32)desc, desc->dcmd, desc->dsadr, desc->dtadr,

+			desc->ddadr);

+		desc++;

+	}

+	desc--;

+	desc->dcmd &= ~BDMAC_DCMD_LINK;

+#if USE_IRQ

+	desc->dcmd |= BDMAC_DCMD_TIE;

+#endif

+

+	dma_cache_wback_inv((u32)dma_desc_nand_read, (2 + 2 + eccsteps * 3) * (sizeof(jz_bdma_desc_8word)));

+	dma_cache_wback_inv((u32)pval_bch_ddr, 4 * 2); /* two words */

+#if USE_PN

+	dma_cache_wback_inv((unsigned long)dma_desc_rPN, 2*(sizeof(jz_bdma_desc_8word)));

+#endif

+

+	return 0;

+}

+

+#endif				/* CONFIG_MTD_NAND_DMA */

+/*

+ * Main initialization routine

+ */

+int __init jznand_init(void)

+{

+	struct nand_chip *this;

+	int nr_partitions, ret, i;

+

+	printk(KERN_INFO "JZ NAND init");

+#if defined(CONFIG_MTD_NAND_DMA)

+#if defined(CONFIG_MTD_NAND_DMABUF)

+	printk(KERN_INFO " DMA mode, using DMA buffer in NAND driver.\n");

+#else

+	printk(KERN_INFO " DMA mode, using DMA buffer in upper layer.\n");

+#endif

+#else

+	printk(KERN_INFO " CPU mode.\n");

+#endif

+

+#if 1

+	REG_GPIO_PXINTC(0) = 0x00430000; /* nor cs2 rd we function0 */

+	REG_GPIO_PXMASKC(0) = 0x00430000;

+	REG_GPIO_PXPAT1C(0) = 0x00430000;

+	REG_GPIO_PXPAT0C(0) = 0x00430000;

+#endif

+

+	__cpm_start_bdma();

+	/* start bdma channel 0 & 1 */

+	REG_BDMAC_DMACKES = 0x3;

+

+	/* Allocate memory for MTD device structure and private data */

+	jz_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL);

+	if (!jz_mtd) {

+		printk("Unable to allocate JzSOC NAND MTD device structure.\n");

+		return -ENOMEM;

+	}

+

+	/* Allocate memory for NAND when using only one plane */

+	jz_mtd1 = kmalloc(sizeof(struct mtd_info) + sizeof (struct nand_chip), GFP_KERNEL);

+	if (!jz_mtd1) {

+		printk ("Unable to allocate JzSOC NAND MTD device structure 1.\n");

+		kfree(jz_mtd);

+		return -ENOMEM;

+	}

+

+	/* Get pointer to private data */

+	this = (struct nand_chip *)(&jz_mtd[1]);

+

+	/* Initialize structures */

+	memset((char *)jz_mtd, 0, sizeof(struct mtd_info));

+	memset((char *)this, 0, sizeof(struct nand_chip));

+

+#ifdef CONFIG_MTD_NAND_BUS_WIDTH_16

+	this->options |= NAND_BUSWIDTH_16;

+#endif

+

+	/* Link the private data with the MTD structure */

+	jz_mtd->priv = this;

+

+

+	addr_offset = NAND_ADDR_OFFSET;

+	cmd_offset = NAND_CMD_OFFSET;

+

+	/* Set & initialize NAND Flash controller */

+	jz_device_setup();

+

+	/* Set address of NAND IO lines to static bank1 by default */

+	this->IO_ADDR_R = (void __iomem *)NAND_DATA_PORT1;

+	this->IO_ADDR_W = (void __iomem *)NAND_DATA_PORT1;

+	this->cmd_ctrl = jz_hwcontrol;

+	this->dev_ready = jz_device_ready;

+

+#ifdef CONFIG_MTD_HW_BCH_ECC

+	this->ecc.calculate = jzsoc_nand_calculate_bch_ecc;

+	this->ecc.correct = jzsoc_nand_bch_correct_data;

+	this->ecc.hwctl = jzsoc_nand_enable_bch_hwecc;

+	this->ecc.mode = NAND_ECC_HW;

+	this->ecc.size = 512;

+	this->ecc.read_page = nand_read_page_hwecc_bch;

+	this->ecc.write_page = nand_write_page_hwecc_bch;

+#if defined(CONFIG_MTD_HW_BCH_24BIT)

+	this->ecc.bytes = 39;

+#elif defined(CONFIG_MTD_HW_BCH_20BIT)

+	this->ecc.bytes = 33;

+#elif defined(CONFIG_MTD_HW_BCH_16BIT)

+	this->ecc.bytes = 26;

+#elif defined(CONFIG_MTD_HW_BCH_12BIT)

+	this->ecc.bytes = 20;

+#elif defined(CONFIG_MTD_HW_BCH_8BIT)

+	this->ecc.bytes = 13;

+#else

+	this->ecc.bytes = 7;

+#endif

+#endif

+

+#ifdef  CONFIG_MTD_SW_HM_ECC

+	this->ecc.mode = NAND_ECC_SOFT;

+#endif

+	/* 20 us command delay time */

+	this->chip_delay = 20;

+	/* Scan to find existance of the device */

+	ret = nand_scan_ident(jz_mtd, NAND_MAX_CHIPS);

+

+	if (!ret) {

+		if (this->planenum == 2) {

+			/* reset nand functions */

+			this->erase_cmd = single_erase_cmd_planes;

+			this->ecc.read_page = nand_read_page_hwecc_bch_planes;

+			this->ecc.write_page = nand_write_page_hwecc_bch_planes;

+			this->ecc.read_oob = nand_read_oob_std_planes;

+			this->ecc.write_oob = nand_write_oob_std_planes;

+

+			printk(KERN_INFO "Nand using two-plane mode, "

+			       "and resized to writesize:%d oobsize:%d blocksize:0x%x \n",

+			       jz_mtd->writesize, jz_mtd->oobsize, jz_mtd->erasesize);

+		}

+	}

+

+	/* Determine whether all the partitions will use multiple planes if supported */

+	nr_partitions = sizeof(partition_info) / sizeof(struct mtd_partition);

+	all_use_planes = 1;

+	for (i = 0; i < nr_partitions; i++) {

+		all_use_planes &= partition_info[i].use_planes;

+	}

+

+	if (!ret)

+		ret = nand_scan_tail(jz_mtd);

+

+	if (ret){

+		kfree (jz_mtd1);

+		kfree (jz_mtd);

+		return -ENXIO;

+	}

+

+#if defined(CONFIG_MTD_NAND_DMA)

+	jz4770_nand_dma_init(jz_mtd);

+#endif

+

+ 	((struct nand_chip *) (&jz_mtd1[1]))->ecc.read_page = nand_read_page_hwecc_bch;

+ 	((struct nand_chip *) (&jz_mtd1[1]))->ecc.write_page = nand_write_page_hwecc_bch;

+

+	/* Register the partitions */

+	printk (KERN_NOTICE "Creating %d MTD partitions on \"%s\":\n", nr_partitions, jz_mtd->name);

+

+	if ((this->planenum == 2) && !all_use_planes) {

+		for (i = 0; i < nr_partitions; i++) {

+			if (partition_info[i].use_planes)

+				add_mtd_partitions(jz_mtd, &partition_info[i], 1);

+			else

+				add_mtd_partitions(jz_mtd1, &partition_info[i], 1);

+		}

+	} else {

+		kfree(jz_mtd1);

+		add_mtd_partitions(jz_mtd, partition_info, nr_partitions);

+	}

+	return 0;

+}

+

+module_init(jznand_init);

+

+/*

+ * Clean up routine

+ */

+#ifdef MODULE

+

+#if defined(CONFIG_MTD_NAND_DMA)

+static int jz4770_nand_dma_exit(struct mtd_info *mtd)

+{

+	int pagesize = mtd->writesize / chip->planenum;

+

+#if USE_IRQ

+	free_irq(IRQ_BDMA_0 + nand_dma_chan, NULL);

+	free_irq(IRQ_BDMA_0 + bch_dma_chan, NULL);

+#endif

+

+	/* space for the error reports of bch decoding((4 * 5 * eccsteps) bytes),

+     * and the space for the value of ddr and dcs of channel 0 and channel

+     * nand_dma_chan (4 * (2 + 2) bytes) */

+	kfree(errs);

+

+	/* space for dma_desc_nand_read contains dma_desc_nand_prog,

+	 * dma_desc_enc and dma_desc_dec */

+	free_page((u32)dma_desc_nand_read);

+

+#if defined(CONFIG_MTD_NAND_DMABUF)

+	if (pagesize < 4096) {

+		free_page((u32)prog_buf);

+	} else {

+		free_pages((u32)prog_buf, 1);

+	}

+#endif

+

+#if USE_PN

+	free_page((u32)dma_desc_pPN);

+	free_page((u32)dma_desc_rPN);

+	kfree(pn_buf);

+#endif

+

+	return 0;

+}

+#endif

+

+static void __exit jznand_cleanup(void)

+{

+#if defined(CONFIG_MTD_NAND_DMA)

+	jz4770_nand_dma_exit(jz_mtd);

+#endif

+

+	/* Unregister partitions */

+	del_mtd_partitions(jz_mtd);

+

+	/* Unregister the device */

+	del_mtd_device(jz_mtd);

+

+	/* Free the MTD device structure */

+	if ((this->planenum == 2) && !all_use_planes)

+		kfree (jz_mtd1);

+	kfree(jz_mtd);

+}

+

+module_exit(jznand_cleanup);

+#endif

diff --git a/drivers/mtd/nand/jz4810_nand.c b/drivers/mtd/nand/jz4810_nand.c
new file mode 100644
index 00000000000..d57f7bfb755
--- /dev/null
+++ b/drivers/mtd/nand/jz4810_nand.c
@@ -0,0 +1,2021 @@
+/*

+ * linux/drivers/mtd/nand/jz4810_nand.c

+ *

+ * JZ4810 NAND driver

+ *

+ * Copyright (c) 2005 - 2007 Ingenic Semiconductor Inc.

+ * Author: <lhhuang@ingenic.cn>

+ *

+ * This program is free software; you can redistribute it and/or modify

+ * it under the terms of the GNU General Public License as published by

+ * the Free Software Foundation; either version 2 of the License, or

+ * (at your option) any later version.

+ */

+

+#include <linux/slab.h>

+#include <linux/module.h>

+#include <linux/delay.h>

+#include <linux/init.h>

+

+#include <linux/mtd/mtd.h>

+#include <linux/mtd/nand.h>

+#include <linux/mtd/nand_ecc.h>

+#include <linux/mtd/partitions.h>

+

+#include <asm/io.h>

+#include <asm/jzsoc.h>

+

+#define BDMAC_DCMD_DS_NAND		BDMAC_DCMD_DS_64BYTE

+#define DIV_DS_NAND				64

+

+#define BDMAC_DCMD_DS_BCH		BDMAC_DCMD_DS_64BYTE

+#define DIV_DS_BCH           	64

+

+#ifdef CONFIG_MTD_NAND_BUS_WIDTH_16

+#define BDMAC_DCMD_DWDH_XX	BDMAC_DCMD_DWDH_16

+#else

+#define BDMAC_DCMD_DWDH_XX	BDMAC_DCMD_DWDH_8

+#endif

+

+#define USE_DIRECT	1

+#define	USE_PN		0

+#define	USE_COUNTER	0

+#define	COUNT_0		0	/* 1:count the number of 1; 0:count the number of 0 */

+#define PN_ENABLE			(1 | PN_RESET)

+#define PN_DISABLE			0

+#define PN_RESET			(1 << 1)

+#define COUNTER_ENABLE  	((1 << 3) | COUNTER_RESET)

+#define COUNTER_DISABLE 	(0 << 3)

+#define COUNTER_RESET   	(1 << 5)

+#define COUNT_FOR_1			(0 << 4)

+#define COUNT_FOR_0			(1 << 4)

+

+#define DEBUG1        0

+#if DEBUG1

+#define	dprintk(n,x...) printk(n,##x)

+#else

+#define	dprintk(n,x...)

+#endif

+

+#if defined(CONFIG_MTD_HW_BCH_24BIT)

+#define __ECC_ENCODING __ecc_encoding_24bit

+#define __ECC_DECODING __ecc_decoding_24bit

+#define ERRS_SIZE       13	/* 13 words */

+#define PAR_SIZE       	78	/* 24-bit */

+#elif defined(CONFIG_MTD_HW_BCH_20BIT)

+#define __ECC_ENCODING __ecc_encoding_20bit

+#define __ECC_DECODING __ecc_decoding_20bit

+#define ERRS_SIZE       11	/* 11 words */

+#define PAR_SIZE       	65	/* 20-bit */

+#elif defined(CONFIG_MTD_HW_BCH_16BIT)

+#define __ECC_ENCODING __ecc_encoding_16bit

+#define __ECC_DECODING __ecc_decoding_16bit

+#define ERRS_SIZE       9	/* 9 words */

+#define PAR_SIZE       	52	/* 16-bit */

+#elif defined(CONFIG_MTD_HW_BCH_12BIT)

+#define __ECC_ENCODING __ecc_encoding_12bit

+#define __ECC_DECODING __ecc_decoding_12bit

+#define ERRS_SIZE       7	/* 7 words */

+#define PAR_SIZE       	39	/* 12-bit */

+#elif defined(CONFIG_MTD_HW_BCH_8BIT)

+#define __ECC_ENCODING __ecc_encoding_8bit

+#define __ECC_DECODING __ecc_decoding_8bit

+#define ERRS_SIZE       5	/* 5 words */

+#define PAR_SIZE       	26	/* 8-bit */

+#else

+#define __ECC_ENCODING __ecc_encoding_4bit

+#define __ECC_DECODING __ecc_decoding_4bit

+#define ERRS_SIZE       3	/* 3 words */

+#define PAR_SIZE       	13	/* 4-bit */

+#endif

+

+#define NAND_DATA_PORT1	       0xBA000000	/* read-write area in static bank 1 */

+#define NAND_DATA_PORT2	       0xB8000000	/* read-write area in static bank 2 */

+#define NAND_DATA_PORT3	       0xB7000000	/* read-write area in static bank 3 */

+#define NAND_DATA_PORT4	       0xB6000000	/* read-write area in static bank 4 */

+

+#define NAND_ADDR_OFFSET       0x00800000      /* address port offset for unshare mode */

+#define NAND_CMD_OFFSET        0x00400000      /* command port offset for unshare mode */

+

+#if defined(CONFIG_MTD_NAND_DMA)

+#define  USE_IRQ      1

+enum {

+	NAND_NONE,

+	NAND_PROG,

+	NAND_READ

+};

+static volatile u8 nand_status;

+static volatile int dma_ack = 0;

+static volatile int dma_ack1 = 0;

+static char nand_dma_chan = 1;	/* fixed to channel 1 */

+static char bch_dma_chan = 0;	/* fixed to channel 0 */

+static u32 *errs;

+static jz_bdma_desc_8word *dma_desc_enc, *dma_desc_enc1, *dma_desc_dec, *dma_desc_dec1, *dma_desc_dec2,

+	*dma_desc_nand_prog, *dma_desc_nand_read;

+#if USE_PN

+static jz_bdma_desc_8word *dma_desc_pPN, *dma_desc_rPN;

+#endif

+static u32 *pval_nand_ddr;

+static u32 *pval_nand_cmd_pgprog; /* for sending 0x11 or 0x10 when programing*/

+#if defined(CONFIG_MTD_NAND_DMABUF)

+u8 *prog_buf, *read_buf;

+#endif

+#if USE_PN

+static u32 *pn_buf;

+#endif

+DECLARE_WAIT_QUEUE_HEAD(nand_prog_wait_queue);

+DECLARE_WAIT_QUEUE_HEAD(nand_read_wait_queue);

+#endif		/* CONFIG_MTD_NAND_DMA */

+

+struct buf_be_corrected {

+	u8 *data;

+	u8 *oob;

+};

+

+static u32 addr_offset;

+static u32 cmd_offset;

+

+extern int global_page; /* for two-plane operations */

+extern int global_mafid; /* ID of manufacture */

+

+/*

+ * MTD structure for JzSOC board

+ */

+static struct mtd_info *jz_mtd = NULL;

+extern struct mtd_info *jz_mtd1;

+extern char all_use_planes;

+

+/*

+ * Define partitions for flash devices

+ */

+#if defined(CONFIG_JZ4760_CYGNUS) || defined(CONFIG_JZ4760_LEPUS) || defined(CONFIG_JZ4810_F4810)

+static struct mtd_partition partition_info[] = {

+	{name:"NAND BOOT partition",

+	 offset:0 * 0x100000LL,

+	 size:4 * 0x100000LL,

+	 use_planes: 0},

+	{name:"NAND KERNEL partition",

+	 offset:4 * 0x100000LL,

+	 size:4 * 0x100000LL,

+	 use_planes: 0},

+	{name:"NAND ROOTFS partition",

+	 offset:8 * 0x100000LL,

+	 size:504 * 0x100000LL,

+	 use_planes: 0},

+	{name:"NAND DATA partition",

+	 offset:512 * 0x100000LL,

+	 size:512 * 0x100000LL,

+	 use_planes: 1},

+	{name:"NAND VFAT partition",

+	 offset:1024 * 0x100000LL,

+	 size:1024 * 0x100000LL,

+	 use_planes: 1},

+};

+

+/* Define max reserved bad blocks for each partition.

+ * This is used by the mtdblock-jz.c NAND FTL driver only.

+ *

+ * The NAND FTL driver reserves some good blocks which can't be

+ * seen by the upper layer. When the bad block number of a partition

+ * exceeds the max reserved blocks, then there is no more reserved

+ * good blocks to be used by the NAND FTL driver when another bad

+ * block generated.

+ */

+static int partition_reserved_badblocks[] = {

+	2,			/* reserved blocks of mtd0 */

+	2,			/* reserved blocks of mtd1 */

+	10,			/* reserved blocks of mtd2 */

+	10,			/* reserved blocks of mtd3 */

+	20,			/* reserved blocks of mtd4 */

+	20

+};				/* reserved blocks of mtd5 */

+#endif				/* CONFIG_JZ4760_CYGNUS || CONFIG_JZ4760_LEPUS */

+

+#if defined(CONFIG_JZ4760_ALTAIR)

+

+/* Reserve 32MB for bootloader, splash1, splash2 and radiofw */

+#define MISC_OFFSET		(32  * 0x100000LL)

+

+#define MISC_SIZE		(  1 * 0x100000LL)

+#define RECOVERY_SIZE		(  5 * 0x100000LL)

+#define BOOT_SIZE		(  4 * 0x100000LL)

+#define SYSTEM_SIZE		(90 * 0x100000LL)

+#define USERDATA_SIZE		(90 * 0x100000LL)

+#define CACHE_SIZE		(32 * 0x100000LL)

+#define STORAGE_SIZE		(MTDPART_SIZ_FULL)

+

+static struct mtd_partition partition_info[] = {

+

+	/* Android partitions:

+	 *

+	 * misc@mtd0 :      raw

+	 * recovery@mtd1:   raw

+	 * boot@mtd2:       raw

+	 * system@mtd3:     yaffs2

+	 * userdata@mtd4:   yaffs2

+	 * cache@mtd5:      yaffs2

+	 * storage@mtd6:    vfat

+	 */

+	{name:       "misc",

+	 offset:     MISC_OFFSET,

+	 size:       MISC_SIZE,

+	 use_planes: 0},

+	{name:       "recovery",

+	 offset:     (MISC_OFFSET+MISC_SIZE),

+	 size:       RECOVERY_SIZE,

+	 use_planes: 0},

+	{name:       "boot",

+	 offset:     (MISC_OFFSET+MISC_SIZE+RECOVERY_SIZE),

+	 size:       BOOT_SIZE,

+	 use_planes: 0},

+	{name:       "system",

+	 offset:     (MISC_OFFSET+MISC_SIZE+RECOVERY_SIZE+BOOT_SIZE),

+	 size:       SYSTEM_SIZE,

+	 use_planes: 0},

+	{name:       "userdata",

+	 offset:     (MISC_OFFSET+MISC_SIZE+RECOVERY_SIZE+BOOT_SIZE+SYSTEM_SIZE),

+	 size:       USERDATA_SIZE,

+	 use_planes: 0},

+	{name:       "cache",

+	 offset:     (MISC_OFFSET+MISC_SIZE+RECOVERY_SIZE+BOOT_SIZE+SYSTEM_SIZE+USERDATA_SIZE),

+	 size:       CACHE_SIZE,

+	 use_planes: 0},

+	{name:       "storage",

+	 offset:     (MISC_OFFSET+MISC_SIZE+RECOVERY_SIZE+BOOT_SIZE+SYSTEM_SIZE+USERDATA_SIZE+CACHE_SIZE),

+	 size:       STORAGE_SIZE,

+	 use_planes: 0}

+};

+

+/* Define max reserved bad blocks for each partition.

+ * This is used by the mtdblock-jz.c NAND FTL driver only.

+ *

+ * The NAND FTL driver reserves some good blocks which can't be

+ * seen by the upper layer. When the bad block number of a partition

+ * exceeds the max reserved blocks, then there is no more reserved

+ * good blocks to be used by the NAND FTL driver when another bad

+ * block generated.

+ */

+static int partition_reserved_badblocks[] = {

+	10,			/* reserved blocks of mtd0 */

+	10,			/* reserved blocks of mtd1 */

+	10,			/* reserved blocks of mtd2 */

+	10,			/* reserved blocks of mtd3 */

+	10,			/* reserved blocks of mtd4 */

+	10,			/* reserved blocks of mtd5 */

+	12			/* reserved blocks of mtd6 */

+};

+#endif	                        /* CONFIG_JZ4760_ALTAIR */

+

+/*-------------------------------------------------------------------------

+ * Following three functions are exported and used by the mtdblock-jz.c

+ * NAND FTL driver only.

+ */

+

+unsigned short get_mtdblock_write_verify_enable(void)

+{

+#ifdef CONFIG_MTD_MTDBLOCK_WRITE_VERIFY_ENABLE

+	return 1;

+#endif

+	return 0;

+}

+

+EXPORT_SYMBOL(get_mtdblock_write_verify_enable);

+

+unsigned short get_mtdblock_oob_copies(void)

+{

+	return CONFIG_MTD_OOB_COPIES;

+}

+

+EXPORT_SYMBOL(get_mtdblock_oob_copies);

+

+int *get_jz_badblock_table(void)

+{

+	return partition_reserved_badblocks;

+}

+

+EXPORT_SYMBOL(get_jz_badblock_table);

+

+/*-------------------------------------------------------------------------*/

+

+static void jz_hwcontrol(struct mtd_info *mtd, int dat, u32 ctrl)

+{

+	struct nand_chip *this = (struct nand_chip *)(mtd->priv);

+	u32 nandaddr = (u32)this->IO_ADDR_W;

+	extern u8 nand_nce;  /* defined in nand_base.c, indicates which chip select is used for current nand chip */

+

+	if (ctrl & NAND_CTRL_CHANGE) {

+		if (ctrl & NAND_NCE) {

+			switch (nand_nce) {

+			case NAND_NCE1:

+				this->IO_ADDR_W = this->IO_ADDR_R = (void __iomem *)NAND_DATA_PORT1;

+				REG_NEMC_NFCSR = NEMC_NFCSR_NFCE1 | NEMC_NFCSR_NFE1;

+				break;

+			case NAND_NCE2:

+				this->IO_ADDR_W = this->IO_ADDR_R = (void __iomem *)NAND_DATA_PORT2;

+				REG_NEMC_NFCSR = NEMC_NFCSR_NFCE2 | NEMC_NFCSR_NFE2;

+				break;

+			case NAND_NCE3:

+				this->IO_ADDR_W = this->IO_ADDR_R = (void __iomem *)NAND_DATA_PORT3;

+				REG_NEMC_NFCSR = NEMC_NFCSR_NFCE3 | NEMC_NFCSR_NFE3;

+				break;

+			case NAND_NCE4:

+				this->IO_ADDR_W = this->IO_ADDR_R = (void __iomem *)NAND_DATA_PORT4;

+				REG_NEMC_NFCSR = NEMC_NFCSR_NFCE4 | NEMC_NFCSR_NFE4;

+				break;

+			default:

+				printk("error: no nand_nce 0x%x\n",nand_nce);

+				break;

+			}

+		} else {

+

+		  REG_NEMC_NFCSR = 0;

+		}

+

+		if (ctrl & NAND_ALE)

+			nandaddr = (u32)((u32)(this->IO_ADDR_W) | addr_offset);

+		else

+			nandaddr = (u32)((u32)(this->IO_ADDR_W) & ~addr_offset);

+		if (ctrl & NAND_CLE)

+			nandaddr = (u32)(nandaddr | cmd_offset);

+		else

+			nandaddr = (u32)(nandaddr & ~cmd_offset);

+	}

+

+	this->IO_ADDR_W = (void __iomem *)nandaddr;

+	if (dat != NAND_CMD_NONE) {

+		writeb(dat, this->IO_ADDR_W);

+		/* printk("write cmd:0x%x to 0x%x\n",dat,(u32)this->IO_ADDR_W); */

+	}

+}

+

+static int jz_device_ready(struct mtd_info *mtd)

+{

+	int ready, wait = 10;

+	while (wait--);

+	ready = ((REG_GPIO_PXPIN(0) & 0x00100000) ? 1 : 0);

+	return ready;

+}

+

+/*

+ * NEMC setup

+ */

+static void jz_device_setup(void)

+{

+// PORT 0:

+// PORT 1:

+// PORT 2:

+// PIN/BIT N		FUNC0		FUNC1

+//	21		CS1#		-

+//	22		CS2#		-

+//	23		CS3#		-

+//	24		CS4#		-

+#define GPIO_CS2_N (32*0+22)

+#define GPIO_CS3_N (32*0+23)

+#define GPIO_CS4_N (32*0+24)

+

+#ifdef CONFIG_MTD_NAND_BUS_WIDTH_16

+#define SMCR_VAL   0x0d444440

+//#define SMCR_VAL   0x0fff7740  //slowest

+	__gpio_as_nand_16bit(1);

+#else

+#define SMCR_VAL   0x0d444400

+//#define SMCR_VAL   0x0fff7700  //slowest

+	__gpio_as_nand_8bit(1);

+#endif

+

+	/* Read/Write timings */

+	REG_NEMC_SMCR1 = SMCR_VAL;

+

+#if defined(CONFIG_MTD_NAND_CS2)

+	__gpio_as_func0(GPIO_CS2_N);

+

+	/* Read/Write timings */

+	REG_NEMC_SMCR2 = SMCR_VAL;

+#endif

+

+#if defined(CONFIG_MTD_NAND_CS3)

+	__gpio_as_func0(GPIO_CS3_N);

+

+	/* Read/Write timings */

+	REG_NEMC_SMCR3 = SMCR_VAL;

+#endif

+

+#if defined(CONFIG_MTD_NAND_CS4)

+	__gpio_as_func0(GPIO_CS4_N);

+

+	/* Read/Write timings */

+	REG_NEMC_SMCR4 = SMCR_VAL;

+#endif

+}

+

+#ifdef CONFIG_MTD_HW_BCH_ECC

+

+static void jzsoc_nand_enable_bch_hwecc(struct mtd_info *mtd, int mode)

+{

+	struct nand_chip *this = (struct nand_chip *)(mtd->priv);

+	int eccsize = this->ecc.size;

+	int eccsteps = this->ecc.steps / this->planenum;

+	int oob_per_eccsize = this->ecc.layout->eccpos[0] / eccsteps;

+

+	REG_BCH_INTS = 0xffffffff;

+	if (mode == NAND_ECC_READ) {

+		__ECC_DECODING();

+		__ecc_cnt_dec((eccsize + oob_per_eccsize) * 2 + PAR_SIZE);

+#if defined(CONFIG_MTD_NAND_DMA)

+		__ecc_dma_enable();

+#endif

+	}

+

+	if (mode == NAND_ECC_WRITE) {

+		__ECC_ENCODING();

+		__ecc_cnt_enc((eccsize + oob_per_eccsize) * 2);

+#if defined(CONFIG_MTD_NAND_DMA)

+		__ecc_dma_enable();

+#endif

+	}

+}

+

+/**

+ * bch_correct

+ * @dat:        data to be corrected

+ * @idx:        the index of error bit in an eccsize

+ */

+static void bch_correct(struct mtd_info *mtd, u8 * dat, int idx)

+{

+	struct nand_chip *this = (struct nand_chip *)(mtd->priv);

+	int eccsize = this->ecc.size;

+	int eccsteps = this->ecc.steps / this->planenum;

+	int ecc_pos = this->ecc.layout->eccpos[0];

+	int oob_per_eccsize = ecc_pos / eccsteps;

+	int i, bit;		/* the 'bit' of i byte is error */

+

+	i = (idx - 1) >> 3;

+	bit = (idx - 1) & 0x7;

+

+	dprintk("error:i=%d, bit=%d\n",i,bit);

+

+	if (i < eccsize){

+		((struct buf_be_corrected *)dat)->data[i] ^= (1 << bit);

+	} else if (i < eccsize + oob_per_eccsize) {

+		((struct buf_be_corrected *)dat)->oob[i-eccsize] ^= (1 << bit);

+	}

+}

+

+#if defined(CONFIG_MTD_NAND_DMA)

+

+/**

+ * jzsoc_nand_bch_correct_data

+ * @mtd:	mtd info structure

+ * @dat:        data to be corrected

+ * @errs0:      pointer to the dma target buffer of bch decoding which stores BHINTS and

+ *              BHERR0~3(8-bit BCH) or BHERR0~1(4-bit BCH)

+ * @calc_ecc:   no used

+ */

+static int jzsoc_nand_bch_correct_data(struct mtd_info *mtd, u_char * dat, u_char * errs0, u_char * calc_ecc)

+{

+	u32 stat, i;

+	u32 *errs = (u32 *)errs0;

+	int ret = 0;

+

+	if (REG_BDMAC_DCCSR(0) & BDMAC_DCCSR_BERR) {

+		stat = errs[0];

+		dprintk("stat=%x err0:%x err1:%x \n", stat, errs[1], errs[2]);

+

+		if (stat & BCH_INTS_ERR) {

+			if (stat & BCH_INTS_UNCOR) {

+				printk("NAND: Uncorrectable ECC error\n");

+				return -1;

+			} else {

+				u32 errcnt = (stat & BCH_INTS_ERRC_MASK) >> BCH_INTS_ERRC_BIT;

+				if(errcnt > 24)

+				  printk("NAND:err count[%d] is too big\n",errcnt);

+				else

+				{

+					/*begin at the second DWORD*/

+					errs = (u32 *)&errs0[4];

+					for(i = 0;i < errcnt;i++)

+					{

+						/* errs[i>>1] get the error report regester value,

+						* (i+1) the error bit index.

+						* errs[i>>1] >> (((i + 1) % 2) << 4) means when error

+						* bit index is even, errs[i>>1] >> 16*/

+						bch_correct(mtd, dat, ((errs[i>>1] >> ((i % 2) << 4))) & BCH_ERR_INDEX_MASK);

+					}

+				}

+			}

+		}

+	}

+

+	return ret;

+}

+

+#else				/* cpu mode */

+

+/**

+ * jzsoc_nand_bch_correct_data

+ * @mtd:	mtd info structure

+ * @dat:        data to be corrected

+ * @read_ecc:   pointer to ecc buffer calculated when nand writing

+ * @calc_ecc:   no used

+ */

+static int jzsoc_nand_bch_correct_data(struct mtd_info *mtd, u_char * dat, u_char * read_ecc, u_char * calc_ecc)

+{

+	struct nand_chip *this = (struct nand_chip *)(mtd->priv);

+	int eccsize = this->ecc.size;

+	int eccbytes = this->ecc.bytes;

+	int eccsteps = this->ecc.steps / this->planenum;

+	int ecc_pos = this->ecc.layout->eccpos[0];

+	int oob_per_eccsize = ecc_pos / eccsteps;

+	short k;

+	u32 stat;

+	int ret = 0;

+

+	/* Write data to REG_BCH_DR */

+	for (k = 0; k < eccsize; k++) {

+		REG_BCH_DR = ((struct buf_be_corrected *)dat)->data[k];

+	}

+	/* Write oob to REG_BCH_DR */

+	for (k = 0; k < oob_per_eccsize; k++) {

+		REG_BCH_DR = ((struct buf_be_corrected *)dat)->oob[k];

+	}

+	/* Write parities to REG_BCH_DR */

+	for (k = 0; k < eccbytes; k++) {

+		REG_BCH_DR = read_ecc[k];

+	}

+

+	/* Wait for completion */

+	__ecc_decode_sync();

+	__ecc_disable();

+

+	/* Check decoding */

+	stat = REG_BCH_INTS;

+

+	if (stat & BCH_INTS_ERR) {

+		/* Error occurred */

+		if (stat & BCH_INTS_UNCOR) {

+			printk("NAND: Uncorrectable ECC error--\n");

+			return -1;

+		} else {

+			u32 errcnt = (stat & BCH_INTS_ERRC_MASK) >> BCH_INTS_ERRC_BIT;

+			switch (errcnt) {

+			case 24:

+				bch_correct(mtd, dat, (REG_BCH_ERR11 & BCH_ERR_INDEX_ODD_MASK) >> BCH_ERR_INDEX_ODD_BIT);

+				/* FALL-THROUGH */

+			case 23:

+				bch_correct(mtd, dat, (REG_BCH_ERR11 & BCH_ERR_INDEX_EVEN_MASK) >> BCH_ERR_INDEX_EVEN_BIT);

+				/* FALL-THROUGH */

+			case 22:

+				bch_correct(mtd, dat, (REG_BCH_ERR10 & BCH_ERR_INDEX_ODD_MASK) >> BCH_ERR_INDEX_ODD_BIT);

+				/* FALL-THROUGH */

+			case 21:

+				bch_correct(mtd, dat, (REG_BCH_ERR10 & BCH_ERR_INDEX_EVEN_MASK) >> BCH_ERR_INDEX_EVEN_BIT);

+				/* FALL-THROUGH */

+			case 20:

+				bch_correct(mtd, dat, (REG_BCH_ERR9 & BCH_ERR_INDEX_ODD_MASK) >> BCH_ERR_INDEX_ODD_BIT);

+				/* FALL-THROUGH */

+			case 19:

+				bch_correct(mtd, dat, (REG_BCH_ERR9 & BCH_ERR_INDEX_EVEN_MASK) >> BCH_ERR_INDEX_EVEN_BIT);

+				/* FALL-THROUGH */

+			case 18:

+				bch_correct(mtd, dat, (REG_BCH_ERR8 & BCH_ERR_INDEX_ODD_MASK) >> BCH_ERR_INDEX_ODD_BIT);

+				/* FALL-THROUGH */

+			case 17:

+				bch_correct(mtd, dat, (REG_BCH_ERR8 & BCH_ERR_INDEX_EVEN_MASK) >> BCH_ERR_INDEX_EVEN_BIT);

+				/* FALL-THROUGH */

+			case 16:

+				bch_correct(mtd, dat, (REG_BCH_ERR7 & BCH_ERR_INDEX_ODD_MASK) >> BCH_ERR_INDEX_ODD_BIT);

+				/* FALL-THROUGH */

+			case 15:

+				bch_correct(mtd, dat, (REG_BCH_ERR7 & BCH_ERR_INDEX_EVEN_MASK) >> BCH_ERR_INDEX_EVEN_BIT);

+				/* FALL-THROUGH */

+			case 14:

+				bch_correct(mtd, dat, (REG_BCH_ERR6 & BCH_ERR_INDEX_ODD_MASK) >> BCH_ERR_INDEX_ODD_BIT);

+				/* FALL-THROUGH */

+			case 13:

+				bch_correct(mtd, dat, (REG_BCH_ERR6 & BCH_ERR_INDEX_EVEN_MASK) >> BCH_ERR_INDEX_EVEN_BIT);

+				/* FALL-THROUGH */

+			case 12:

+				bch_correct(mtd, dat, (REG_BCH_ERR5 & BCH_ERR_INDEX_ODD_MASK) >> BCH_ERR_INDEX_ODD_BIT);

+				/* FALL-THROUGH */

+			case 11:

+				bch_correct(mtd, dat, (REG_BCH_ERR5 & BCH_ERR_INDEX_EVEN_MASK) >> BCH_ERR_INDEX_EVEN_BIT);

+				/* FALL-THROUGH */

+			case 10:

+				bch_correct(mtd, dat, (REG_BCH_ERR4 & BCH_ERR_INDEX_ODD_MASK) >> BCH_ERR_INDEX_ODD_BIT);

+				/* FALL-THROUGH */

+			case 9:

+				bch_correct(mtd, dat, (REG_BCH_ERR4 & BCH_ERR_INDEX_EVEN_MASK) >> BCH_ERR_INDEX_EVEN_BIT);

+				/* FALL-THROUGH */

+			case 8:

+				bch_correct(mtd, dat, (REG_BCH_ERR3 & BCH_ERR_INDEX_ODD_MASK) >> BCH_ERR_INDEX_ODD_BIT);

+				/* FALL-THROUGH */

+			case 7:

+				bch_correct(mtd, dat, (REG_BCH_ERR3 & BCH_ERR_INDEX_EVEN_MASK) >> BCH_ERR_INDEX_EVEN_BIT);

+				/* FALL-THROUGH */

+			case 6:

+				bch_correct(mtd, dat, (REG_BCH_ERR2 & BCH_ERR_INDEX_ODD_MASK) >> BCH_ERR_INDEX_ODD_BIT);

+				/* FALL-THROUGH */

+			case 5:

+				bch_correct(mtd, dat, (REG_BCH_ERR2 & BCH_ERR_INDEX_EVEN_MASK) >> BCH_ERR_INDEX_EVEN_BIT);

+				/* FALL-THROUGH */

+			case 4:

+				bch_correct(mtd, dat, (REG_BCH_ERR1 & BCH_ERR_INDEX_ODD_MASK) >> BCH_ERR_INDEX_ODD_BIT);

+				/* FALL-THROUGH */

+			case 3:

+				bch_correct(mtd, dat, (REG_BCH_ERR1 & BCH_ERR_INDEX_EVEN_MASK) >> BCH_ERR_INDEX_EVEN_BIT);

+				/* FALL-THROUGH */

+			case 2:

+				bch_correct(mtd, dat, (REG_BCH_ERR0 & BCH_ERR_INDEX_ODD_MASK) >> BCH_ERR_INDEX_ODD_BIT);

+				/* FALL-THROUGH */

+			case 1:

+				bch_correct(mtd, dat, (REG_BCH_ERR0 & BCH_ERR_INDEX_EVEN_MASK) >> BCH_ERR_INDEX_EVEN_BIT);

+				return 0;

+			default:

+				break;

+			}

+		}

+	}

+

+	return ret;

+}

+#endif				/* CONFIG_MTD_NAND_DMA */

+

+static int jzsoc_nand_calculate_bch_ecc(struct mtd_info *mtd, const u_char * dat, u_char * ecc_code)

+{

+	struct nand_chip *this = (struct nand_chip *)(mtd->priv);

+	int eccsize = this->ecc.size;

+	int eccbytes = this->ecc.bytes;

+	int eccsteps = this->ecc.steps / this->planenum;

+	int ecc_pos = this->ecc.layout->eccpos[0];

+	int oob_per_eccsize = ecc_pos / eccsteps;

+	volatile u8 *paraddr = (volatile u8 *)BCH_PAR0;

+	short i;

+

+	/* Write data to REG_BCH_DR */

+	for (i = 0; i < eccsize; i++) {

+		REG_BCH_DR = ((struct buf_be_corrected *)dat)->data[i];

+	}

+	/* Write oob to REG_BCH_DR */

+	for (i = 0; i < oob_per_eccsize; i++) {

+		REG_BCH_DR = ((struct buf_be_corrected *)dat)->oob[i];

+	}

+	__ecc_encode_sync();

+	__ecc_disable();

+

+	for (i = 0; i < eccbytes; i++) {

+		ecc_code[i] = *paraddr++;

+	}

+

+	return 0;

+}

+

+extern int nand_sw_bch_ops(struct mtd_info *mtd, u8 *oobdata, int ops);

+

+#if defined(CONFIG_MTD_NAND_DMA)

+

+/**

+ * nand_write_page_hwecc_bch - [REPLACABLE] hardware ecc based page write function

+ * @mtd:	mtd info structure

+ * @chip:	nand chip info structure

+ * @buf:	data buffer

+ */

+static void nand_write_page_hwecc_bch0(struct mtd_info *mtd, struct nand_chip *chip, const uint8_t * buf, u8 cmd_pgprog)

+{

+	int eccsize = chip->ecc.size;

+	int eccsteps = chip->ecc.steps / chip->planenum;

+	int eccbytes = chip->ecc.bytes;

+	int ecc_pos = chip->ecc.layout->eccpos[0];

+	int oob_per_eccsize = ecc_pos / eccsteps;

+	int pagesize = mtd->writesize / chip->planenum;

+	int oobsize = mtd->oobsize / chip->planenum;

+	int i, err, timeout;

+	const u8 *databuf;

+	u8 *oobbuf;

+	jz_bdma_desc_8word *desc;

+

+	nand_sw_bch_ops(mtd, (u8 *)chip->oob_poi, 1);

+

+#if defined(CONFIG_MTD_NAND_DMABUF)

+	memcpy(prog_buf, buf, pagesize);

+	memcpy(prog_buf + pagesize, chip->oob_poi, oobsize);

+	dma_cache_wback_inv((u32)prog_buf, pagesize + oobsize);

+#else

+	databuf = buf;

+	oobbuf = chip->oob_poi;

+

+	/* descriptors for encoding data blocks */

+	desc = dma_desc_enc;

+	for (i = 0; i < eccsteps; i++) {

+		desc->dsadr = CPHYSADDR((u32)databuf) + i * eccsize;	/* DMA source address */

+		desc->dtadr = CPHYSADDR((u32)oobbuf) + ecc_pos + i * eccbytes;	/* DMA target address */

+		dprintk("dma_desc_enc:desc:%x cmd:%x sadr:%x tadr:%x dadr:%x\n", (u32)desc, desc->dcmd, desc->dsadr, desc->dtadr,

+			desc->ddadr);

+		desc++;

+	}

+

+	/* descriptors for encoding oob blocks */

+	desc = dma_desc_enc1;

+	for (i = 0; i < eccsteps; i++) {

+		desc->dsadr = CPHYSADDR((u32)oobbuf) + oob_per_eccsize * i;	/* DMA source address, 28/4 = 7bytes */

+		desc->dtadr = CPHYSADDR((u32)oobbuf) + ecc_pos + i * eccbytes;	/* DMA target address */

+		dprintk("dma_desc_enc1:desc:%x cmd:%x sadr:%x tadr:%x dadr:%x\n", (u32)desc, desc->dcmd, desc->dsadr, desc->dtadr,

+			desc->ddadr);

+		desc++;

+	}

+

+	/* descriptor for nand programing data block */

+	desc = dma_desc_nand_prog;

+	desc->dsadr = CPHYSADDR((u32)databuf);	/* DMA source address */

+	desc->dtadr = CPHYSADDR((u32)chip->IO_ADDR_W);  /* It will be changed when using multiply chip select */

+	dprintk("dma_desc_nand_prog:desc:%x cmd:%x sadr:%x tadr:%x dadr:%x\n", (u32)desc, desc->dcmd, desc->dsadr, desc->dtadr,

+	       desc->ddadr);

+

+	/* descriptor for nand programing oob block */

+	desc++;

+	desc->dsadr = CPHYSADDR((u32)oobbuf);	/* DMA source address */

+	desc->dtadr = CPHYSADDR((u32)chip->IO_ADDR_W);  /* It will be changed when using multiply chip select */

+	dprintk("dma_desc_oob_prog:desc:%x cmd:%x sadr:%x tadr:%x dadr:%x\n", (u32)desc, desc->dcmd, desc->dsadr, desc->dtadr,

+	       desc->ddadr);

+

+	/* descriptor for __nand_cmd(CMD_PGPROG) */

+	desc++;

+	*pval_nand_cmd_pgprog = cmd_pgprog | 0x40000000;

+	desc->dsadr = CPHYSADDR((u32)pval_nand_cmd_pgprog);

+	desc->dtadr = CPHYSADDR((u32)chip->IO_ADDR_R);	/* DMA target address: cmdport */

+	if (cmd_pgprog == 0x10)

+		desc->dcmd |= BDMAC_DCMD_LINK;  /* __nand_sync() by a DMA descriptor */

+	else if (cmd_pgprog == 0x11)

+		desc->dcmd &= ~BDMAC_DCMD_LINK; /* __nand_sync() by polling */

+

+	dma_cache_wback_inv((u32)dma_desc_enc, (eccsteps * 2 + 2 + 4) * (sizeof(jz_bdma_desc_8word)));

+	dma_cache_wback_inv((u32)databuf, pagesize);

+	dma_cache_wback_inv((u32)oobbuf, oobsize);

+	/* 4*6: pval_nand_ddr, pval_nand_dcs, pval_bch_ddr, pval_bch_dcs, dummy, pval_nand_cmd_pgprog */

+	dma_cache_wback_inv((u32)pval_nand_ddr, 4 * 8); /* 8 words, a cache line */

+#endif

+

+	REG_BDMAC_DCCSR(bch_dma_chan) = 0;

+	REG_BDMAC_DCCSR(nand_dma_chan) = 0;

+

+	/* Setup DMA descriptor address */

+	REG_BDMAC_DDA(bch_dma_chan) = CPHYSADDR((u32)dma_desc_enc);

+#if USE_PN

+	REG_BDMAC_DDA(nand_dma_chan) = CPHYSADDR((u32)dma_desc_pPN);

+#else

+	REG_BDMAC_DDA(nand_dma_chan) = CPHYSADDR((u32)dma_desc_nand_prog);

+#endif

+

+	/* Setup request source */

+	REG_BDMAC_DRSR(bch_dma_chan) = BDMAC_DRSR_RS_BCH_ENC;

+	REG_BDMAC_DRSR(nand_dma_chan) = BDMAC_DRSR_RS_AUTO;

+

+	/* Setup DMA channel control/status register */

+	REG_BDMAC_DCCSR(bch_dma_chan) = BDMAC_DCCSR_DES8 | BDMAC_DCCSR_EN;	/* descriptor transfer, clear status, start channel */

+	/* Enable DMA */

+	REG_BDMAC_DMACR |= BDMAC_DMACR_DMAE;

+

+	/* Enable BCH encoding */

+	chip->ecc.hwctl(mtd, NAND_ECC_WRITE);

+

+	dma_ack1 = 0;

+	nand_status = NAND_PROG;

+

+	/* DMA doorbell set -- start DMA now ... */

+	__bdmac_channel_set_doorbell(bch_dma_chan);

+

+#if USE_IRQ

+	if (cmd_pgprog == 0x10) {

+		dprintk("nand prog before wake up\n");

+		do {

+			err = wait_event_interruptible_timeout(nand_prog_wait_queue, dma_ack1, 3 * HZ);

+		}while(err == -ERESTARTSYS);

+

+		nand_status = NAND_NONE;

+		dprintk("nand prog after wake up\n");

+		if (!err) {

+			printk("*** NAND WRITE, Warning, wait event 3s timeout!\n");

+			dump_jz_bdma_channel(0);

+			dump_jz_bdma_channel(nand_dma_chan);

+			printk("REG_BCH_CR=%x REG_BCH_CNT=0x%x REG_BCH_INTS=%x\n", REG_BCH_CR, REG_BCH_CNT, REG_BCH_INTS);

+		}

+		dprintk("timeout remain = %d\n", err);

+	} else if (cmd_pgprog == 0x11) {

+		timeout = 100000;

+		while ((!__bdmac_channel_transmit_end_detected(nand_dma_chan)) && (timeout--));

+		if (timeout <= 0)

+			printk("two-plane prog 0x11 timeout!\n");

+	}

+#else

+	timeout = 100000;

+	while ((!__bdmac_channel_transmit_end_detected(nand_dma_chan)) && (timeout--));

+	while(!chip->dev_ready(mtd));

+	if (timeout <= 0)

+		printk("not use irq, prog timeout!\n");

+#endif

+}

+

+static void nand_write_page_hwecc_bch(struct mtd_info *mtd, struct nand_chip *chip, const uint8_t * buf)

+{

+	nand_write_page_hwecc_bch0(mtd, chip, buf, 0x10);

+}

+

+static void nand_write_page_hwecc_bch_planes(struct mtd_info *mtd, struct nand_chip *chip, const uint8_t * buf)

+{

+	int page;

+	int pagesize = mtd->writesize >> 1;

+	int ppb = mtd->erasesize / mtd->writesize;

+

+	page = (global_page / ppb) * ppb + global_page; /* = global_page%ppb + (global_page/ppb)*ppb*2 */

+

+	/* send cmd 0x80, the MSB should be valid if realplane is 4 */

+	if (chip->realplanenum == 2)

+	{

+		if(global_mafid == 0x2c)

+			chip->cmdfunc(mtd, 0x80, 0x00, page);

+		else

+			chip->cmdfunc(mtd, 0x80, 0x00, 0x00);

+	}

+	else

+		chip->cmdfunc(mtd, 0x80, 0x00, page & (1 << (chip->chip_shift - chip->page_shift)));

+

+	nand_write_page_hwecc_bch0(mtd, chip, buf, 0x11);

+	chip->cmdfunc(mtd, 0x81, 0x00, page + ppb);

+	nand_write_page_hwecc_bch0(mtd, chip, buf + pagesize, 0x10);

+}

+

+#else	/* nand write in cpu mode */

+

+static void nand_write_page_hwecc_bch(struct mtd_info *mtd, struct nand_chip *chip,

+				  const uint8_t *buf)

+{

+	int i, eccsize = chip->ecc.size;

+	int eccbytes = chip->ecc.bytes;

+	int eccsteps = chip->ecc.steps / chip->planenum;

+	int oob_per_eccsize = chip->ecc.layout->eccpos[0] / eccsteps;

+	int oobsize = mtd->oobsize / chip->planenum;

+	int ecctotal = chip->ecc.total / chip->planenum;

+        uint8_t *p = (uint8_t *)buf;

+	uint8_t *ecc_calc = chip->buffers->ecccalc;

+	uint32_t *eccpos = chip->ecc.layout->eccpos;

+	static struct buf_be_corrected buf_calc0;

+	struct buf_be_corrected *buf_calc = &buf_calc0;

+

+	nand_sw_bch_ops(mtd, (u8 *)chip->oob_poi, 1);

+

+	for (i = 0; i < eccsteps; i++, p += eccsize) {

+		buf_calc->data = (u8 *)buf + eccsize * i;

+		buf_calc->oob = chip->oob_poi + oob_per_eccsize * i;

+		chip->ecc.hwctl(mtd, NAND_ECC_WRITE);

+		chip->ecc.calculate(mtd, (u8 *)buf_calc, &ecc_calc[eccbytes*i]);

+		chip->write_buf(mtd, p, eccsize);

+	}

+

+	for (i = 0; i < ecctotal; i++)

+		chip->oob_poi[eccpos[i]] = ecc_calc[i];

+

+	chip->write_buf(mtd, chip->oob_poi, oobsize);

+}

+

+/* nand write using two-plane mode */

+static void nand_write_page_hwecc_bch_planes(struct mtd_info *mtd, struct nand_chip *chip,

+					     const uint8_t *buf)

+{

+	int pagesize = mtd->writesize >> 1;

+	int ppb = mtd->erasesize / mtd->writesize;

+	int page;

+

+	page = (global_page / ppb) * ppb + global_page; /* = global_page%ppb + (global_page/ppb)*ppb*2 */

+

+	/* send cmd 0x80, the MSB should be valid if realplane is 4 */

+	if (chip->realplanenum == 2)

+	{

+		if(global_mafid == 0x2c)

+			chip->cmdfunc(mtd, 0x80, 0x00, page);

+		else

+			chip->cmdfunc(mtd, 0x80, 0x00, 0x00);

+	}

+	else

+		chip->cmdfunc(mtd, 0x80, 0x00, page & (1 << (chip->chip_shift - chip->page_shift)));

+

+	nand_write_page_hwecc_bch(mtd, chip, buf);

+

+	chip->cmdfunc(mtd, 0x11, -1, -1); /* send cmd 0x11 */

+	ndelay(100);

+	while(!chip->dev_ready(mtd));

+

+	chip->cmdfunc(mtd, 0x81, 0x00, page + ppb); /* send cmd 0x81 */

+	nand_write_page_hwecc_bch(mtd, chip, buf + pagesize);

+}

+#endif				/* CONFIG_MTD_NAND_DMA */

+

+/**

+ * nand_read_page_hwecc_bch - [REPLACABLE] hardware ecc based page read function

+ * @mtd:	mtd info structure

+ * @chip:	nand chip info structure

+ * @buf:	buffer to store read data

+ *

+ * Not for syndrome calculating ecc controllers which need a special oob layout

+ */

+#if defined(CONFIG_MTD_NAND_DMA)

+static int nand_read_page_hwecc_bch0(struct mtd_info *mtd, struct nand_chip *chip, uint8_t * buf, u32 page)

+{

+	int i, eccsize = chip->ecc.size;

+	int eccsteps = chip->ecc.steps / chip->planenum;

+	int eccbytes = chip->ecc.bytes;

+	int ecc_pos = chip->ecc.layout->eccpos[0];

+	int oob_per_eccsize = ecc_pos / eccsteps;

+	int pagesize = mtd->writesize / chip->planenum;

+	int oobsize = mtd->oobsize / chip->planenum;

+	u8 *databuf, *oobbuf;

+	jz_bdma_desc_8word *desc;

+	int err;

+	u32 addrport, cmdport;

+	static struct buf_be_corrected buf_correct0;

+

+	addrport = (u32)(chip->IO_ADDR_R) | addr_offset;

+ 	cmdport = (u32)(chip->IO_ADDR_R) | cmd_offset;

+

+#if defined(CONFIG_MTD_NAND_DMABUF)

+	databuf = read_buf;

+	oobbuf = read_buf + pagesize;

+

+	dma_cache_inv((u32)read_buf, pagesize + oobsize);	// databuf should be invalidated.

+	memset(errs, 0, eccsteps * ERRS_SIZE * 4);

+	dma_cache_wback_inv((u32)errs, eccsteps * ERRS_SIZE * 4);

+#else

+

+	databuf = buf;

+	oobbuf = chip->oob_poi;

+

+	/* descriptor for nand reading data block */

+	desc = dma_desc_nand_read;

+	desc->dsadr = CPHYSADDR((u32)chip->IO_ADDR_R); /* It will be changed when using multiply chip select */

+	desc->dtadr = CPHYSADDR((u32)databuf);	/* DMA target address */

+

+	dprintk("desc_nand_read:desc:%x cmd:%x sadr:%x tadr:%x dadr:%x\n", (u32)desc, desc->dcmd, desc->dsadr, desc->dtadr,

+	       desc->ddadr);

+

+	/* descriptor for nand reading oob block */

+	desc++;

+	desc->dsadr = CPHYSADDR((u32)chip->IO_ADDR_R); /* It will be changed when using multiply chip select */

+	desc->dtadr = CPHYSADDR((u32)oobbuf);	/* DMA target address */

+	dprintk("desc_oob_read:desc:%x cmd:%x sadr:%x tadr:%x dadr:%x\n", (u32)desc, desc->dcmd, desc->dsadr, desc->dtadr,

+	       desc->ddadr);

+

+	/* descriptors for data to be written to bch */

+	desc = dma_desc_dec;

+	for (i = 0; i < eccsteps; i++) {

+		desc->dsadr = CPHYSADDR((u32)databuf) + i * eccsize;	/* DMA source address */

+		dprintk("dma_desc_dec:desc:%x cmd:%x sadr:%x tadr:%x dadr:%x\n", (u32)desc, desc->dcmd, desc->dsadr, desc->dtadr,

+			desc->ddadr);

+		desc++;

+	}

+

+	/* descriptors for oob to be written to bch */

+	desc = dma_desc_dec1;

+	for (i = 0; i < eccsteps; i++) {

+		desc->dsadr = CPHYSADDR((u32)oobbuf) + oob_per_eccsize * i;	/* DMA source address */

+		dprintk("dma_desc_dec1:desc:%x cmd:%x sadr:%x tadr:%x dadr:%x\n", (u32)desc, desc->dcmd, desc->dsadr, desc->dtadr,

+			desc->ddadr);

+		desc++;

+	}

+

+	/* descriptors for parities to be written to bch */

+	desc = dma_desc_dec2;

+	for (i = 0; i < eccsteps; i++) {

+		desc->dsadr = CPHYSADDR((u32)oobbuf) + ecc_pos + i * eccbytes;	/* DMA source address */

+		dprintk("dma_desc_dec2:desc:%x cmd:%x sadr:%x tadr:%x dadr:%x\n", (u32)desc, desc->dcmd, desc->dsadr, desc->dtadr,

+			desc->ddadr);

+		desc++;

+	}

+

+	dma_cache_wback_inv((u32)dma_desc_nand_read, (2 + eccsteps * 3) * (sizeof(jz_bdma_desc_8word)));

+

+	memset(errs, 0, eccsteps * ERRS_SIZE * 4);

+	dma_cache_inv((u32)databuf, pagesize);	// databuf should be invalidated.

+	dma_cache_inv((u32)oobbuf, oobsize);	// oobbuf should be invalidated too

+	dma_cache_wback_inv((u32)errs, eccsteps * ERRS_SIZE * 4);

+#endif

+	REG_BDMAC_DCCSR(bch_dma_chan) = 0;

+	REG_BDMAC_DCCSR(nand_dma_chan) = 0;

+

+	/* Setup DMA descriptor address */

+#if USE_PN

+	REG_BDMAC_DDA(nand_dma_chan) = CPHYSADDR((u32)dma_desc_rPN);

+#else

+	REG_BDMAC_DDA(nand_dma_chan) = CPHYSADDR((u32)dma_desc_nand_read);

+#endif

+	REG_BDMAC_DDA(bch_dma_chan) = CPHYSADDR((u32)dma_desc_dec);

+

+	/* Setup request source */

+#if USE_PN

+	REG_BDMAC_DRSR(nand_dma_chan) = BDMAC_DRSR_RS_AUTO;

+#else

+	REG_BDMAC_DRSR(nand_dma_chan) = BDMAC_DRSR_RS_NAND0;

+#endif

+	REG_BDMAC_DRSR(bch_dma_chan) = BDMAC_DRSR_RS_BCH_DEC;

+

+	/* Enable DMA */

+	REG_BDMAC_DMACR |= BDMAC_DMACR_DMAE;

+

+	/* Enable BCH decoding */

+	chip->ecc.hwctl(mtd, NAND_ECC_READ);

+

+	dma_ack = 0;

+	nand_status = NAND_READ;

+	/* DMA doorbell set -- start nand DMA now ... */

+	__bdmac_channel_set_doorbell(nand_dma_chan);

+

+	/* Setup DMA channel control/status register */

+	REG_BDMAC_DCCSR(nand_dma_chan) = BDMAC_DCCSR_DES8 | BDMAC_DCCSR_EN;

+

+#define __nand_cmd(n)		(REG8(cmdport) = (n))

+#define __nand_addr(n)		(REG8(addrport) = (n))

+

+	__nand_cmd(NAND_CMD_READ0);

+

+	__nand_addr(0);

+	if (pagesize != 512)

+		__nand_addr(0);

+

+	__nand_addr(page & 0xff);

+	__nand_addr((page >> 8) & 0xff);

+

+	/* One more address cycle for the devices whose number of page address bits > 16  */

+	if (((chip->chipsize >> chip->page_shift) >> 16) > 0)

+		__nand_addr((page >> 16) & 0xff);

+

+	if (pagesize != 512)

+		__nand_cmd(NAND_CMD_READSTART);

+

+#if USE_IRQ

+	do {

+		err = wait_event_interruptible_timeout(nand_read_wait_queue, dma_ack, 3 * HZ);

+	}while(err == -ERESTARTSYS);

+	nand_status = NAND_NONE;

+

+	if (!err) {

+		printk("*** NAND READ, Warning, wait event 3s timeout!\n");

+		dump_jz_bdma_channel(0);

+		dump_jz_bdma_channel(nand_dma_chan);

+		printk("REG_BCH_CR=%x REG_BCH_CNT=0x%x REG_BCH_INTS=%x\n", REG_BCH_CR, REG_BCH_CNT, REG_BCH_INTS);

+	}

+	dprintk("timeout remain = %d\n", err);

+#else

+	int timeout;

+	timeout = 100000;

+	while ((!__bdmac_channel_transmit_end_detected(bch_dma_chan)) && (timeout--));

+	if (timeout <= 0) {

+		printk("not use irq, NAND READ timeout!\n");

+	}

+#endif

+

+	for (i = 0; i < eccsteps; i++) {

+		int stat;

+		struct buf_be_corrected *buf_correct = &buf_correct0;

+

+		buf_correct->data = databuf + eccsize * i;

+		buf_correct->oob = oobbuf + oob_per_eccsize * i;

+

+		stat = chip->ecc.correct(mtd, (u8 *)buf_correct, (u8 *)&errs[i * ERRS_SIZE], NULL);

+		if (stat < 0)

+		{

+			printk("ecc Uncorrectable:global_page = %d,chip->planenum = %d\n",global_page,chip->planenum);

+			mtd->ecc_stats.failed++;

+		}

+		else

+			mtd->ecc_stats.corrected += stat;

+	}

+

+#if defined(CONFIG_MTD_NAND_DMABUF)

+	memcpy(buf, read_buf, pagesize);

+	memcpy(chip->oob_poi, read_buf + pagesize, oobsize);

+#endif

+	return 0;

+}

+

+static int nand_read_page_hwecc_bch(struct mtd_info *mtd, struct nand_chip *chip, uint8_t * buf)

+{

+	u32 page = global_page;

+

+	nand_read_page_hwecc_bch0(mtd, chip, buf, page);

+	return 0;

+}

+

+static int nand_read_page_hwecc_bch_planes(struct mtd_info *mtd, struct nand_chip *chip, uint8_t * buf)

+{

+	u32 page;

+	int pagesize = mtd->writesize >> 1;

+	int ppb = mtd->erasesize / mtd->writesize;

+

+	page = (global_page / ppb) * ppb + global_page; /* = global_page%ppb + (global_page/ppb)*ppb*2 */

+

+        /* read 1st page */

+	nand_read_page_hwecc_bch0(mtd, chip, buf, page);

+

+        /* read 2nd page */

+	nand_read_page_hwecc_bch0(mtd, chip, buf + pagesize, page + ppb);

+	return 0;

+}

+

+#else	/* nand read in cpu mode */

+

+static int nand_read_page_hwecc_bch(struct mtd_info *mtd, struct nand_chip *chip, uint8_t * buf)

+{

+	int i, eccsize = chip->ecc.size;

+	int eccbytes = chip->ecc.bytes;

+	int eccsteps = chip->ecc.steps / chip->planenum;

+	int ecc_pos = chip->ecc.layout->eccpos[0];

+	int oob_per_eccsize = ecc_pos / eccsteps;

+	uint8_t *ecc_calc = chip->buffers->ecccalc;

+	uint8_t *ecc_code = chip->buffers->ecccode;

+	uint32_t *eccpos = chip->ecc.layout->eccpos;

+	int pagesize = mtd->writesize / chip->planenum;

+	int oobsize = mtd->oobsize / chip->planenum;

+	int ecctotal = chip->ecc.total / chip->planenum;

+	static struct buf_be_corrected buf_correct0;

+

+	chip->read_buf(mtd, buf, pagesize);

+	chip->read_buf(mtd, chip->oob_poi, oobsize);

+

+	for (i = 0; i < ecctotal; i++) {

+		ecc_code[i] = chip->oob_poi[eccpos[i]];

+	}

+

+	for (i = 0; i < eccsteps; i++) {

+		int stat;

+		struct buf_be_corrected *buf_correct = &buf_correct0;

+

+		buf_correct->data = buf + eccsize * i;

+		buf_correct->oob = chip->oob_poi + oob_per_eccsize * i;

+

+		chip->ecc.hwctl(mtd, NAND_ECC_READ);

+		stat = chip->ecc.correct(mtd, (u8 *)buf_correct, &ecc_code[eccbytes*i], &ecc_calc[eccbytes*i]);

+		if (stat < 0)

+		{

+			printk("ecc Uncorrectable:global_page = %d,chip->planenum = %d\n",global_page,chip->planenum);

+			mtd->ecc_stats.failed++;

+		}

+		else

+			mtd->ecc_stats.corrected += stat;

+	}

+

+	return 0;

+}

+

+static int nand_read_page_hwecc_bch_planes(struct mtd_info *mtd, struct nand_chip *chip, uint8_t * buf)

+{

+	int pagesize = mtd->writesize >> 1;

+	int ppb = mtd->erasesize / mtd->writesize;

+	uint32_t page;

+

+	page = (global_page / ppb) * ppb + global_page; /* = global_page%ppb + (global_page/ppb)*ppb*2 */

+

+	/* Read first page */

+	chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);

+	nand_read_page_hwecc_bch(mtd, chip, buf);

+

+	/* Read 2nd page */

+	chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page + ppb);

+	nand_read_page_hwecc_bch(mtd, chip, buf+pagesize);

+	return 0;

+}

+#endif				/* CONFIG_MTD_NAND_DMA */

+

+#endif				/* CONFIG_MTD_HW_BCH_ECC */

+

+/* read oob using two-plane mode */

+static int nand_read_oob_std_planes(struct mtd_info *mtd, struct nand_chip *chip,

+				    int global_page, int sndcmd)

+{

+	int page;

+	int oobsize = mtd->oobsize >> 1;

+	int ppb = mtd->erasesize / mtd->writesize;

+

+	page = (global_page / ppb) * ppb + global_page; /* = global_page%ppb + (global_page/ppb)*ppb*2 */

+

+	/* Read first page OOB */

+	if (sndcmd) {

+		chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);

+	}

+	chip->read_buf(mtd, chip->oob_poi, oobsize);

+	nand_sw_bch_ops(mtd, (u8 *)chip->oob_poi, 0);

+

+	/* Read second page OOB */

+	page += ppb;

+	if (sndcmd) {

+		chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);

+		sndcmd = 0;

+	}

+	chip->read_buf(mtd, chip->oob_poi+oobsize, oobsize);

+	nand_sw_bch_ops(mtd, (u8 *)chip->oob_poi + oobsize, 0);

+

+	return 0;

+}

+

+/* write oob using two-plane mode */

+static int nand_write_oob_std_planes(struct mtd_info *mtd, struct nand_chip *chip,

+				     int global_page)

+{

+	int status = 0, page;

+	const uint8_t *buf = chip->oob_poi;

+	int pagesize = mtd->writesize >> 1;

+	int oobsize = mtd->oobsize >> 1;

+	int ppb = mtd->erasesize / mtd->writesize;

+

+	page = (global_page / ppb) * ppb + global_page; /* = global_page%ppb + (global_page/ppb)*ppb*2 */

+

+	/* send cmd 0x80, the MSB should be valid if realplane is 4 */

+	if (chip->realplanenum == 2)

+	{

+		if(global_mafid == 0x2c)

+			chip->cmdfunc(mtd, 0x80, pagesize, page);

+		else

+			chip->cmdfunc(mtd, 0x80, pagesize, 0x00);

+	}

+	else

+		chip->cmdfunc(mtd, 0x80, pagesize, page & (1 << (chip->chip_shift - chip->page_shift)));

+

+	nand_sw_bch_ops(mtd, (u8 *)buf, 1);

+	chip->write_buf(mtd, buf, oobsize);

+	/* Send first command to program the OOB data */

+	chip->cmdfunc(mtd, 0x11, -1, -1);

+	ndelay(100);

+	status = chip->waitfunc(mtd, chip);

+

+	page += ppb;

+	buf += oobsize;

+	chip->cmdfunc(mtd, 0x81, pagesize, page);

+	nand_sw_bch_ops(mtd, (u8 *)buf, 1);

+	chip->write_buf(mtd, buf, oobsize);

+	/* Send command to program the OOB data */

+	chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);

+	/* Wait long R/B */

+	ndelay(100);

+	status = chip->waitfunc(mtd, chip);

+

+	return status & NAND_STATUS_FAIL ? -EIO : 0;

+}

+

+/* nand erase using two-plane mode */

+static void single_erase_cmd_planes(struct mtd_info *mtd, int global_page)

+{

+	struct nand_chip *chip = mtd->priv;

+	int page, ppb = mtd->erasesize / mtd->writesize;

+

+	page = (global_page / ppb) * ppb + global_page; /* = global_page%ppb + (global_page/ppb)*ppb*2 */

+

+	/* send cmd 0x60, the MSB should be valid if realplane is 4 */

+	if (chip->realplanenum == 2)

+	{

+		if(global_mafid == 0x2c)

+			chip->cmdfunc(mtd, 0x60, -1, page);

+		else

+			chip->cmdfunc(mtd, 0x60, -1, 0x00);

+	}

+	else

+		chip->cmdfunc(mtd, 0x60, -1, page & (1 << (chip->chip_shift - chip->page_shift)));

+

+	page += ppb;

+	chip->cmdfunc(mtd, 0x60, -1, page & (~(ppb-1))); /* send cmd 0x60 */

+

+	chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1); /* send cmd 0xd0 */

+	/* Do not need wait R/B or check status */

+}

+

+#if defined(CONFIG_MTD_NAND_DMA)

+

+#if USE_IRQ

+static irqreturn_t nand_dma_irq(int irq, void *dev_id)

+{

+	u8 dma_chan;

+	volatile int wakeup = 0;

+

+	dma_chan = irq - IRQ_BDMA_0;

+

+	dprintk("jz4810_dma_irq %d, channel %d\n", irq, dma_chan);

+

+	if (__bdmac_channel_transmit_halt_detected(dma_chan)) {

+		__bdmac_channel_clear_transmit_halt(dma_chan);

+		wakeup = 1;

+		printk("DMA HALT\n");

+	}

+

+	if (__bdmac_channel_address_error_detected(dma_chan)) {

+

+		REG_BDMAC_DCCSR(dma_chan) &= ~BDMAC_DCCSR_EN;	/* disable DMA */

+		__bdmac_channel_clear_address_error(dma_chan);

+

+		REG_BDMAC_DSAR(dma_chan) = 0;	/* reset source address register */

+		REG_BDMAC_DTAR(dma_chan) = 0;	/* reset destination address register */

+

+		/* clear address error in BDMACR */

+		REG_BDMAC_DMACR &= ~(1 << 2);

+		wakeup = 1;

+		printk("DMA address error!\n");

+	}

+

+#if 0

+

+	while (!__bdmac_channel_transmit_end_detected(dma_chan));

+

+	if (__bdmac_channel_count_terminated_detected(dma_chan)) {

+		dprintk("DMA CT\n");

+		__bdmac_channel_clear_count_terminated(dma_chan);

+		wakeup = 0;

+	}

+#endif

+

+	if (__bdmac_channel_transmit_end_detected(dma_chan)) {

+		dprintk("DMA TT\n");

+		REG_BDMAC_DCCSR(dma_chan) &= ~BDMAC_DCCSR_EN;	/* disable DMA */

+		__bdmac_channel_clear_transmit_end(dma_chan);

+		wakeup = 1;

+	}

+

+	if (wakeup) {

+		dprintk("ack %d irq , wake up dma_chan %d nand_status %d\n", dma_ack, dma_chan, nand_status);

+		/* wakeup wait event */

+		if ((dma_chan == nand_dma_chan) && (nand_status == NAND_PROG)) {

+			dprintk("nand prog dma irq, wake up----\n");

+			dma_ack1 = 1;

+			wake_up_interruptible(&nand_prog_wait_queue);

+		}

+

+		if ((dma_chan == bch_dma_chan) && (nand_status == NAND_READ)) {

+			dprintk("nand read irq, wake up----\n");

+			dma_ack = 1;

+			wake_up_interruptible(&nand_read_wait_queue);

+		}

+		wakeup = 0;

+	}

+

+	return IRQ_HANDLED;

+}

+#endif				/* USE_IRQ */

+

+static int jz4810_nand_dma_init(struct mtd_info *mtd)

+{

+	struct nand_chip *chip = mtd->priv;

+	int eccsize = chip->ecc.size;

+	int eccsteps = chip->ecc.steps / chip->planenum;

+	int eccbytes = chip->ecc.bytes;

+	int ecc_pos = chip->ecc.layout->eccpos[0];

+	int oob_per_eccsize = ecc_pos / eccsteps;

+	int pagesize = mtd->writesize / chip->planenum;

+	int oobsize = mtd->oobsize / chip->planenum;

+	int i, err;

+	jz_bdma_desc_8word *desc, *dma_desc_bch_ddr, *dma_desc_nand_ddr, *dma_desc_nand_cmd_pgprog;

+	u32  *pval_nand_dcs, *pval_bch_ddr, *pval_bch_dcs, *dummy;

+	u32 next;

+#if defined(CONFIG_MTD_NAND_DMABUF)

+	u8 *oobbuf;

+#endif

+

+#if USE_IRQ

+	if ((err = request_irq(IRQ_BDMA_0 + nand_dma_chan, nand_dma_irq, IRQF_DISABLED, "nand_dma", NULL))) {

+		printk("can't reqeust DMA nand channel.\n");

+		return 0;

+	}

+

+	if ((err = request_irq(IRQ_BDMA_0 + bch_dma_chan, nand_dma_irq, IRQF_DISABLED, "bch_dma", NULL))) {

+		printk("bch_dma irq request err\n");

+		return 0;

+	}

+#endif

+

+#if USE_PN

+	dma_desc_pPN = (jz_bdma_desc_8word *)__get_free_page(GFP_KERNEL);

+	dma_desc_rPN = (jz_bdma_desc_8word *)__get_free_page(GFP_KERNEL);

+	pn_buf = kmalloc(2 * sizeof(unsigned int), GFP_KERNEL);

+

+	memset(dma_desc_pPN, 0, 4096);

+	memset(dma_desc_rPN, 0, 4096);

+	memset(pn_buf, 0, 2 * sizeof(unsigned int));

+

+	#if USE_COUNTER

+		*pn_buf = PN_ENABLE | COUNTER_ENABLE;

+		#if COUNT_0

+		    *pn_buf |= COUNT_FOR_0;

+		#endif

+	#else

+		*pn_buf = PN_ENABLE;

+	#endif

+

+	*(pn_buf + 1) = PN_DISABLE;

+	dma_cache_wback_inv((unsigned int)pn_buf, 2 * sizeof(unsigned int));

+#endif	/* USE_PN */

+

+	__bdmac_channel_enable_clk(nand_dma_chan);

+	__bdmac_channel_enable_clk(bch_dma_chan);

+

+#if defined(CONFIG_MTD_NAND_DMABUF)

+	if (pagesize < 4096) {

+		read_buf = prog_buf = (u8 *) __get_free_page(GFP_KERNEL);

+	} else {

+		read_buf = prog_buf = (u8 *) __get_free_pages(GFP_KERNEL, 1);

+	}

+	if (!read_buf)

+		return -ENOMEM;

+#endif

+	/* space for the error reports of bch decoding((4 * ERRS_SIZE * eccsteps) bytes), and the space for the value

+     * of ddr and dcs of channel 0 and channel nand_dma_chan (4 * (2 + 2) bytes) */

+	errs = (u32 *)kmalloc(4 * (2 + 2 + ERRS_SIZE * eccsteps), GFP_KERNEL);

+	if (!errs)

+		return -ENOMEM;

+

+	pval_nand_ddr = errs + ERRS_SIZE * eccsteps;

+	pval_nand_dcs = pval_nand_ddr + 1;

+	pval_bch_ddr = pval_nand_dcs + 1;

+	pval_bch_dcs = pval_bch_ddr + 1;

+    /* space for nand prog waiting target, the content is useless */

+	dummy = pval_bch_dcs + 1;

+    /* space to store CMD_PGPROG(0x10) or 0x11 */

+	pval_nand_cmd_pgprog = (u32 *)(dummy + 1);

+

+	/* desc can't across 4KB boundary, as desc base address is fixed */

+	/* space of descriptors for nand reading data and oob blocks */

+	dma_desc_nand_read = (jz_bdma_desc_8word *) __get_free_page(GFP_KERNEL);

+	if (!dma_desc_nand_read)

+		return -ENOMEM;

+	memset(dma_desc_nand_read, 0 ,4096);

+

+	/* space of descriptors for bch decoding */

+	dma_desc_dec = dma_desc_nand_read + 2;

+	dma_desc_dec1 = dma_desc_dec + eccsteps;

+	dma_desc_dec2 = dma_desc_dec + eccsteps * 2;

+

+	/* space of descriptors for notifying bch channel */

+	dma_desc_bch_ddr = dma_desc_dec2 + eccsteps;

+

+	/* space of descriptors for bch encoding */

+	dma_desc_enc = dma_desc_bch_ddr + 2;

+	dma_desc_enc1 = dma_desc_enc + eccsteps;

+

+	/* space of descriptors for nand programing data and oob blocks */

+	dma_desc_nand_prog = dma_desc_enc1 + eccsteps;

+

+        /* space of descriptors for nand prog waiting, including pgprog and sync */

+	dma_desc_nand_cmd_pgprog = dma_desc_nand_prog + 2;

+

+	/* space of descriptors for notifying nand channel, including ddr and dcsr */

+	dma_desc_nand_ddr = dma_desc_nand_cmd_pgprog + 2;

+

+/*************************************

+ * Setup of nand programing descriptors

+ *************************************/

+#if defined(CONFIG_MTD_NAND_DMABUF)

+	oobbuf = prog_buf + pagesize;

+#endif

+	/* set descriptor for encoding data blocks */

+	desc = dma_desc_enc;

+	for (i = 0; i < eccsteps; i++) {

+		next = CPHYSADDR((u32)dma_desc_enc1) + i * (sizeof(jz_bdma_desc_8word));

+

+		desc->dcmd =

+		    BDMAC_DCMD_SAI | BDMAC_DCMD_DAI | BDMAC_DCMD_SWDH_32 | BDMAC_DCMD_DWDH_8 |

+		    BDMAC_DCMD_DS_BCH | BDMAC_DCMD_LINK;

+#if defined(CONFIG_MTD_NAND_DMABUF)

+		desc->dsadr = CPHYSADDR((u32)prog_buf) + i * eccsize;	/* DMA source address */

+		desc->dtadr = CPHYSADDR((u32)oobbuf) + ecc_pos + i * eccbytes;	/* DMA target address */

+#endif

+		desc->dcnt = eccsize / DIV_DS_BCH;	/* size: eccsize bytes */

+		desc->dreqt = BDMAC_DRSR_RS_BCH_ENC;

+		desc->ddadr = next;

+		dprintk("cmd:%x sadr:%x tadr:%x dadr:%x\n", desc->dcmd, desc->dsadr, desc->dtadr, desc->ddadr);

+		desc++;

+	}

+

+	/* set descriptor for encoding oob blocks */

+	desc = dma_desc_enc1;

+	for (i = 0; i < eccsteps; i++) {

+		next = CPHYSADDR((u32)dma_desc_enc) + (i + 1) * (sizeof(jz_bdma_desc_8word));

+

+		desc->dcmd =

+		    BDMAC_DCMD_BLAST | BDMAC_DCMD_SAI | BDMAC_DCMD_DAI | BDMAC_DCMD_SWDH_8 |

+		    BDMAC_DCMD_DWDH_8 | BDMAC_DCMD_DS_8BIT | BDMAC_DCMD_LINK;

+#if defined(CONFIG_MTD_NAND_DMABUF)

+		desc->dsadr = CPHYSADDR((u32)oobbuf) + oob_per_eccsize * i;	/* DMA source address, 28/4 = 7bytes */

+		desc->dtadr = CPHYSADDR((u32)oobbuf) + ecc_pos + i * eccbytes;	/* DMA target address */

+#endif

+		desc->dcnt = oob_per_eccsize;	/* size: 7 bytes -> 2 words */

+		desc->dreqt = BDMAC_DRSR_RS_BCH_ENC;

+		desc->ddadr = next;

+		dprintk("cmd:%x sadr:%x tadr:%x dadr:%x\n", desc->dcmd, desc->dsadr, desc->dtadr, desc->ddadr);

+		desc++;

+	}

+

+	next = CPHYSADDR((u32)dma_desc_nand_ddr);

+	desc--;

+	desc->ddadr = next;

+

+	/* set the descriptor to set door bell of nand_dma_chan for programing nand */

+	desc = dma_desc_nand_ddr;

+	*pval_nand_ddr = 1 << nand_dma_chan;

+	next = CPHYSADDR((u32)dma_desc_nand_ddr) + sizeof(jz_bdma_desc_8word);

+	desc->dcmd = BDMAC_DCMD_SWDH_32 | BDMAC_DCMD_DWDH_32 | BDMAC_DCMD_DS_32BIT | BDMAC_DCMD_LINK;

+	desc->dsadr = CPHYSADDR((u32)pval_nand_ddr);	/* DMA source address */

+	desc->dtadr = CPHYSADDR(BDMAC_DMADBSR);	/* nand_dma_chan's descriptor addres register */

+	desc->dcnt = 1;	/* size: 1 word */

+	desc->dreqt = BDMAC_DRSR_RS_AUTO;

+	desc->ddadr = next;

+	dprintk("*pval_nand_ddr=0x%x\n", *pval_nand_ddr);

+

+	/* set the descriptor to write dccsr of nand_dma_chan for programing nand, dccsr should be set at last */

+	desc++;

+	*pval_nand_dcs = BDMAC_DCCSR_DES8 | BDMAC_DCCSR_EN;	/* set value for writing ddr to enable channel nand_dma_chan */

+	desc->dcmd = BDMAC_DCMD_SWDH_32 | BDMAC_DCMD_DWDH_32 | BDMAC_DCMD_DS_32BIT;

+	desc->dsadr = CPHYSADDR((u32)pval_nand_dcs);	/* DMA source address */

+	desc->dtadr = CPHYSADDR(BDMAC_DCCSR(nand_dma_chan));	/* address of dma door bell set register */

+	desc->dcnt = 1;	/* size: 1 word */

+	desc->dreqt = BDMAC_DRSR_RS_AUTO;

+	dprintk("*pval_nand_dcs=0x%x\n", *pval_nand_dcs);

+

+#if USE_PN

+	desc = dma_desc_pPN;

+	next = CPHYSADDR((u32)dma_desc_nand_prog);

+	desc->dcmd = BDMAC_DCMD_SWDH_32 | BDMAC_DCMD_DWDH_32 | BDMAC_DCMD_DS_32BIT | BDMAC_DCMD_LINK;

+	desc->dsadr = CPHYSADDR((unsigned int)pn_buf);    /* DMA source address */

+	desc->dtadr = CPHYSADDR(NEMC_PNCR); /* DMA target address */

+	desc->dcnt = 1;   /* size: 6 words */

+	desc->dreqt = BDMAC_DRSR_RS_AUTO;

+	desc->ddadr = next;

+#endif

+

+	/* set descriptor for nand programing data block */

+	desc = dma_desc_nand_prog;

+	next = CPHYSADDR((u32)dma_desc_nand_prog) + sizeof(jz_bdma_desc_8word);

+	desc->dcmd =

+	    BDMAC_DCMD_SAI | BDMAC_DCMD_DAI | BDMAC_DCMD_SWDH_32 | BDMAC_DCMD_DWDH_32 |

+	    BDMAC_DCMD_DS_NAND | BDMAC_DCMD_LINK;

+#if USE_DIRECT

+	desc->dcmd |= BDMAC_DCMD_NWR;

+#endif

+#if defined(CONFIG_MTD_NAND_DMABUF)

+	desc->dsadr = CPHYSADDR((u32)prog_buf);	/* DMA source address */

+#endif

+	desc->dtadr = CPHYSADDR((u32)(chip->IO_ADDR_W)); /* DMA target address */

+	desc->dcnt = pagesize / DIV_DS_NAND;	/* size: eccsize bytes */

+	desc->dreqt = BDMAC_DRSR_RS_AUTO;

+	desc->ddadr = next;

+	dprintk("cmd:%x sadr:%x tadr:%x dadr:%x\n", desc->dcmd, desc->dsadr, desc->dtadr, desc->ddadr);

+

+	/* set descriptor for nand programing oob block */

+	desc++;

+#if USE_PN

+	next = CPHYSADDR((unsigned long)dma_desc_pPN + sizeof(jz_bdma_desc_8word));

+#else

+	next = CPHYSADDR((u32)dma_desc_nand_cmd_pgprog);

+#endif

+	desc->dcmd =

+	    BDMAC_DCMD_SAI | BDMAC_DCMD_DAI | BDMAC_DCMD_SWDH_32 | BDMAC_DCMD_DWDH_32 |

+	    BDMAC_DCMD_DS_NAND | BDMAC_DCMD_LINK;

+#if USE_DIRECT

+	desc->dcmd |= BDMAC_DCMD_NWR;

+#endif

+#if defined(CONFIG_MTD_NAND_DMABUF)

+	desc->dsadr = CPHYSADDR((u32)oobbuf);                	/* DMA source address */

+#endif

+	desc->dtadr = CPHYSADDR((u32)(chip->IO_ADDR_W));	/* DMA target address: dataport */

+	desc->dcnt = oobsize / DIV_DS_NAND;            	/* size: eccsize bytes */

+	desc->dreqt = BDMAC_DRSR_RS_AUTO;

+	desc->ddadr = next;

+	dprintk("cmd:%x sadr:%x tadr:%x dadr:%x\n", desc->dcmd, desc->dsadr, desc->dtadr, desc->ddadr);

+

+#if USE_PN

+	desc = dma_desc_pPN + 1;

+	next = CPHYSADDR((u32)dma_desc_nand_cmd_pgprog);

+	desc->dcmd = BDMAC_DCMD_SWDH_32 | BDMAC_DCMD_DWDH_32 | BDMAC_DCMD_DS_32BIT | BDMAC_DCMD_LINK;

+	desc->dsadr = CPHYSADDR((unsigned int)pn_buf) + 4;    /* DMA source address */

+	desc->dtadr = CPHYSADDR(NEMC_PNCR); /* DMA target address */

+	desc->dcnt = 1;   /* size: 6 words */

+	desc->dreqt = BDMAC_DRSR_RS_AUTO;

+	desc->ddadr = next;

+#endif

+

+	/* set descriptor for __nand_cmd(CMD_PGPROG) */

+	desc = dma_desc_nand_cmd_pgprog;

+	*pval_nand_cmd_pgprog = NAND_CMD_PAGEPROG | 0x40000000;

+	next = CPHYSADDR((u32)dma_desc_nand_cmd_pgprog) + sizeof(jz_bdma_desc_8word);

+	desc->dcmd =

+	    BDMAC_DCMD_NAC | BDMAC_DCMD_SWDH_32 | BDMAC_DCMD_DWDH_XX | BDMAC_DCMD_DS_32BIT | BDMAC_DCMD_LINK;

+	desc->dsadr = CPHYSADDR((u32)pval_nand_cmd_pgprog);	        /* DMA source address */

+	desc->dtadr = CPHYSADDR((u32)chip->IO_ADDR_R);	/* DMA target address: cmdport */

+	desc->dcnt = 1;	                        /* size: 1 byte */

+	desc->dnt = 0;

+	desc->dreqt = BDMAC_DRSR_RS_AUTO;

+	desc->ddadr = next;

+	dprintk("cmd:%x sadr:%x tadr:%x dadr:%x\n", desc->dcmd, desc->dsadr, desc->dtadr, desc->ddadr);

+

+	/* set descriptor for __nand_sync() */

+	desc++;

+#if USE_IRQ

+	desc->dcmd =

+		BDMAC_DCMD_SWDH_32 | BDMAC_DCMD_DWDH_32 | BDMAC_DCMD_DS_32BIT | BDMAC_DCMD_TIE;

+#else

+	desc->dcmd =

+		BDMAC_DCMD_SWDH_32 | BDMAC_DCMD_DWDH_32 | BDMAC_DCMD_DS_32BIT;

+#endif

+	desc->dsadr = CPHYSADDR((u32)pval_nand_ddr);	/* DMA source address */

+	desc->dtadr = CPHYSADDR((u32)dummy);        	/* DMA target address, the content is useless */

+	desc->dcnt = 1;             	/* size: 1 word */

+	desc->dnt = 1;

+	desc->dreqt = BDMAC_DRSR_RS_NAND0;

+	dprintk("1cmd:%x sadr:%x tadr:%x dadr:%x\n", desc->dcmd, desc->dsadr, desc->dtadr, desc->ddadr);

+

+	/* eccsteps*2 + 2 + 2 + 2:

+		dma_desc_enc + dma_desc_enc1 + dma_desc_nand_prog(oob) + dma_desc_nand_ddr(csr)

+		+ dma_desc_nand_cmd_pgprog(sync) */

+	dma_cache_wback_inv((u32)dma_desc_enc, (eccsteps * 2 + 2 + 2 + 2) * (sizeof(jz_bdma_desc_8word)));

+	/* 4*6: pval_nand_ddr, pval_nand_dcs, pval_bch_ddr, pval_bch_dcs, dummy, pval_nand_cmd_pgprog */

+	dma_cache_wback_inv((u32)pval_nand_ddr, 4 * 8); /* 8 words, a cache line */

+#if USE_PN

+	dma_cache_wback_inv((unsigned long)dma_desc_pPN, 2*(sizeof(jz_bdma_desc_8word)));

+#endif

+

+/*************************************

+ * Setup of nand reading descriptors

+ *************************************/

+#if defined(CONFIG_MTD_NAND_DMABUF)

+	oobbuf = read_buf + pagesize;

+#endif

+

+#if USE_PN

+	desc = dma_desc_rPN;

+	next = CPHYSADDR((u32)dma_desc_nand_read);

+	desc->dcmd = BDMAC_DCMD_SWDH_32 | BDMAC_DCMD_DWDH_32 | BDMAC_DCMD_DS_32BIT | BDMAC_DCMD_LINK;

+	desc->dsadr = CPHYSADDR((u32)pn_buf);    /* DMA source address */

+	desc->dtadr = CPHYSADDR(NEMC_PNCR); /* DMA target address */

+	desc->dcnt = 1;   /* size: 6 words */

+	desc->dreqt = BDMAC_DRSR_RS_AUTO;

+	desc->ddadr = next;

+#endif

+

+	/* set descriptor for nand reading data block */

+	desc = dma_desc_nand_read;

+	next = CPHYSADDR((u32)dma_desc_nand_read) + sizeof(jz_bdma_desc_8word);

+	desc->dcmd =

+	    BDMAC_DCMD_SAI | BDMAC_DCMD_DAI | BDMAC_DCMD_SWDH_32 | BDMAC_DCMD_DWDH_32 |

+	    BDMAC_DCMD_DS_NAND | BDMAC_DCMD_LINK;

+#if USE_DIRECT

+	desc->dcmd |= BDMAC_DCMD_NRD;

+#endif

+	desc->dsadr = CPHYSADDR((u32)(chip->IO_ADDR_R));	/* DMA source address */

+#if defined(CONFIG_MTD_NAND_DMABUF)

+	desc->dtadr = CPHYSADDR((u32)read_buf);	/* DMA target address */

+#endif

+	desc->dcnt = pagesize / DIV_DS_NAND;	/* size: eccsize bytes */

+	desc->dreqt = BDMAC_DRSR_RS_NAND0;

+	desc->ddadr = next;

+	dprintk("cmd:%x sadr:%x tadr:%x dadr:%x\n", desc->dcmd, desc->dsadr, desc->dtadr, desc->ddadr);

+

+	/* set descriptor for nand reading oob block */

+	desc++;

+#if USE_PN

+	next = CPHYSADDR((u32)dma_desc_rPN + sizeof(jz_bdma_desc_8word));

+#else

+	next = CPHYSADDR((u32)dma_desc_bch_ddr);

+#endif

+	desc->dcmd =

+	    BDMAC_DCMD_SAI | BDMAC_DCMD_DAI | BDMAC_DCMD_SWDH_32 | BDMAC_DCMD_DWDH_32 |

+	    BDMAC_DCMD_DS_NAND | BDMAC_DCMD_LINK;

+#if USE_DIRECT

+	desc->dcmd |= BDMAC_DCMD_NRD;

+#endif

+	desc->dsadr = CPHYSADDR((u32)(chip->IO_ADDR_R));	/* DMA source address */

+#if defined(CONFIG_MTD_NAND_DMABUF)

+	desc->dtadr = CPHYSADDR((u32)oobbuf);	/* DMA target address */

+#endif

+	desc->dcnt = oobsize / DIV_DS_NAND;	/* size: eccsize bytes */

+	desc->dreqt = BDMAC_DRSR_RS_AUTO;

+	desc->ddadr = next;

+	dprintk("cmd:%x sadr:%x tadr:%x dadr:%x\n", desc->dcmd, desc->dsadr, desc->dtadr, desc->ddadr);

+

+#if USE_PN

+	desc = dma_desc_rPN + 1;

+	next = CPHYSADDR((u32)dma_desc_bch_ddr);

+	desc->dcmd = BDMAC_DCMD_SWDH_32 | BDMAC_DCMD_DWDH_32 | BDMAC_DCMD_DS_32BIT | BDMAC_DCMD_LINK;

+	desc->dsadr = CPHYSADDR((u32)pn_buf) + 4;    /* DMA source address */

+	desc->dtadr = CPHYSADDR(NEMC_PNCR); /* DMA target address */

+	desc->dcnt = 1;   /* size: 6 words */

+	desc->dreqt = BDMAC_DRSR_RS_AUTO;

+	desc->ddadr = next;

+#endif

+

+	/* set the descriptor to set door bell for bch */

+	desc = dma_desc_bch_ddr;

+	*pval_bch_ddr = BDMAC_DMADBSR_DBS0;	// set value for writing ddr to enable channel 0

+	next = CPHYSADDR((u32)dma_desc_bch_ddr) + sizeof(jz_bdma_desc_8word);

+	desc->dcmd = BDMAC_DCMD_SWDH_32 | BDMAC_DCMD_DWDH_32 | BDMAC_DCMD_DS_32BIT | BDMAC_DCMD_LINK;

+	desc->dsadr = CPHYSADDR((u32)pval_bch_ddr);	/* DMA source address */

+	desc->dtadr = CPHYSADDR(BDMAC_DMADBSR);	/* channel 1's descriptor addres register */

+	desc->dcnt = 1;	/* size: 1 word */

+	desc->dreqt = BDMAC_DRSR_RS_AUTO;

+	desc->ddadr = next;

+

+	/* set descriptor for writing dcsr */

+	desc++;

+	*pval_bch_dcs = BDMAC_DCCSR_DES8 | BDMAC_DCCSR_EN;	// set value for writing ddr to enable channel 1

+	desc->dcmd = BDMAC_DCMD_SWDH_32 | BDMAC_DCMD_DWDH_32 | BDMAC_DCMD_DS_32BIT;

+	desc->dsadr = CPHYSADDR((u32)pval_bch_dcs);	/* DMA source address */

+	desc->dtadr = CPHYSADDR(BDMAC_DCCSR(bch_dma_chan));	/* address of dma door bell set register */

+	desc->dcnt = 1;	/* size: 1 word */

+	desc->dreqt = BDMAC_DRSR_RS_AUTO;

+

+	/* descriptors for data to be written to bch */

+	desc = dma_desc_dec;

+	for (i = 0; i < eccsteps; i++) {

+		next = CPHYSADDR((u32)dma_desc_dec1 + i * (sizeof(jz_bdma_desc_8word)));

+

+		desc->dcmd =

+		    BDMAC_DCMD_SAI | BDMAC_DCMD_DAI | BDMAC_DCMD_SWDH_32 | BDMAC_DCMD_DWDH_32 |

+		    BDMAC_DCMD_DS_BCH | BDMAC_DCMD_LINK;

+#if defined(CONFIG_MTD_NAND_DMABUF)

+		desc->dsadr = CPHYSADDR((u32)read_buf) + i * eccsize;	/* DMA source address */

+#endif

+		desc->dtadr = CPHYSADDR((u32)errs) + i * 4 * ERRS_SIZE;	/* DMA target address */

+		desc->dcnt = eccsize / DIV_DS_BCH;	/* size: eccsize bytes */

+		desc->dreqt = BDMAC_DRSR_RS_BCH_DEC;

+		desc->ddadr = next;

+		dprintk("desc:%x cmd:%x sadr:%x tadr:%x dadr:%x\n", (u32)desc, desc->dcmd, desc->dsadr, desc->dtadr,

+			desc->ddadr);

+		desc++;

+	}

+

+	/* descriptors for oob to be written to bch */

+	desc = dma_desc_dec1;

+	for (i = 0; i < eccsteps; i++) {

+		next = CPHYSADDR((u32)dma_desc_dec2 + i * (sizeof(jz_bdma_desc_8word)));

+

+		desc->dcmd =

+		    BDMAC_DCMD_SAI | BDMAC_DCMD_DAI | BDMAC_DCMD_SWDH_8 | BDMAC_DCMD_DWDH_32 |

+		    BDMAC_DCMD_DS_8BIT | BDMAC_DCMD_LINK;

+#if defined(CONFIG_MTD_NAND_DMABUF)

+		desc->dsadr = CPHYSADDR((u32)oobbuf) + oob_per_eccsize * i;	/* DMA source address */

+#endif

+		desc->dtadr = CPHYSADDR((u32)errs) + i * 4 * ERRS_SIZE;	/* DMA target address */

+		desc->dcnt = oob_per_eccsize;	/* size: 7 bytes */

+		desc->dreqt = BDMAC_DRSR_RS_BCH_DEC;

+		desc->ddadr = next;

+		dprintk("desc:%x cmd:%x sadr:%x tadr:%x dadr:%x\n", (u32)desc, desc->dcmd, desc->dsadr, desc->dtadr,

+			desc->ddadr);

+		desc++;

+	}

+

+	/* descriptors for parities to be written to bch */

+	desc = dma_desc_dec2;

+	for (i = 0; i < eccsteps; i++) {

+		next = CPHYSADDR((u32)dma_desc_dec) + (i + 1) * (sizeof(jz_bdma_desc_8word));

+

+		desc->dcmd =

+		    BDMAC_DCMD_BLAST | BDMAC_DCMD_SAI | BDMAC_DCMD_DAI | BDMAC_DCMD_SWDH_8 |

+		    BDMAC_DCMD_DWDH_32 | BDMAC_DCMD_DS_32BIT | BDMAC_DCMD_LINK;

+#if defined(CONFIG_MTD_NAND_DMABUF)

+		desc->dsadr = CPHYSADDR((u32)oobbuf) + ecc_pos + i * eccbytes;	/* DMA source address */

+#endif

+		desc->dtadr = CPHYSADDR((u32)errs) + i * 4 * ERRS_SIZE;	/* DMA target address */

+		desc->dcnt = (eccbytes + 3) / 4;	/* size: eccbytes bytes */

+		desc->dreqt = BDMAC_DRSR_RS_BCH_DEC;

+		desc->ddadr = next;

+		dprintk("desc:%x cmd:%x sadr:%x tadr:%x dadr:%x\n", (u32)desc, desc->dcmd, desc->dsadr, desc->dtadr,

+			desc->ddadr);

+		desc++;

+	}

+	desc--;

+	desc->dcmd &= ~BDMAC_DCMD_LINK;

+#if USE_IRQ

+	desc->dcmd |= BDMAC_DCMD_TIE;

+#endif

+

+	dma_cache_wback_inv((u32)dma_desc_nand_read, (2 + 2 + eccsteps * 3) * (sizeof(jz_bdma_desc_8word)));

+	dma_cache_wback_inv((u32)pval_bch_ddr, 4 * 2); /* two words */

+#if USE_PN

+	dma_cache_wback_inv((unsigned long)dma_desc_rPN, 2*(sizeof(jz_bdma_desc_8word)));

+#endif

+

+	return 0;

+}

+

+#endif				/* CONFIG_MTD_NAND_DMA */

+/*

+ * Main initialization routine

+ */

+int __init jznand_init(void)

+{

+	struct nand_chip *this;

+	int nr_partitions, ret, i;

+

+	printk(KERN_INFO "JZ NAND init");

+#if defined(CONFIG_MTD_NAND_DMA)

+#if defined(CONFIG_MTD_NAND_DMABUF)

+	printk(KERN_INFO " DMA mode, using DMA buffer in NAND driver.\n");

+#else

+	printk(KERN_INFO " DMA mode, using DMA buffer in upper layer.\n");

+#endif

+#else

+	printk(KERN_INFO " CPU mode.\n");

+#endif

+

+#if 1

+	REG_GPIO_PXINTC(0) = 0x00430000; /* nor cs2 rd we function0 */

+	REG_GPIO_PXMASKC(0) = 0x00430000;

+	REG_GPIO_PXPAT1C(0) = 0x00430000;

+	REG_GPIO_PXPAT0C(0) = 0x00430000;

+#endif

+

+	__cpm_start_bdma();

+	/* start bdma channel 0 & 1 */

+	REG_BDMAC_DMACKES = 0x3;

+

+	/* Allocate memory for MTD device structure and private data */

+	jz_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL);

+	if (!jz_mtd) {

+		printk("Unable to allocate JzSOC NAND MTD device structure.\n");

+		return -ENOMEM;

+	}

+

+	/* Allocate memory for NAND when using only one plane */

+	jz_mtd1 = kmalloc(sizeof(struct mtd_info) + sizeof (struct nand_chip), GFP_KERNEL);

+	if (!jz_mtd1) {

+		printk ("Unable to allocate JzSOC NAND MTD device structure 1.\n");

+		kfree(jz_mtd);

+		return -ENOMEM;

+	}

+

+	/* Get pointer to private data */

+	this = (struct nand_chip *)(&jz_mtd[1]);

+

+	/* Initialize structures */

+	memset((char *)jz_mtd, 0, sizeof(struct mtd_info));

+	memset((char *)this, 0, sizeof(struct nand_chip));

+

+#ifdef CONFIG_MTD_NAND_BUS_WIDTH_16

+	this->options |= NAND_BUSWIDTH_16;

+#endif

+

+	/* Link the private data with the MTD structure */

+	jz_mtd->priv = this;

+

+

+	addr_offset = NAND_ADDR_OFFSET;

+	cmd_offset = NAND_CMD_OFFSET;

+

+	/* Set & initialize NAND Flash controller */

+	jz_device_setup();

+

+	/* Set address of NAND IO lines to static bank1 by default */

+	this->IO_ADDR_R = (void __iomem *)NAND_DATA_PORT1;

+	this->IO_ADDR_W = (void __iomem *)NAND_DATA_PORT1;

+	this->cmd_ctrl = jz_hwcontrol;

+	this->dev_ready = jz_device_ready;

+

+#ifdef CONFIG_MTD_HW_BCH_ECC

+	this->ecc.calculate = jzsoc_nand_calculate_bch_ecc;

+	this->ecc.correct = jzsoc_nand_bch_correct_data;

+	this->ecc.hwctl = jzsoc_nand_enable_bch_hwecc;

+	this->ecc.mode = NAND_ECC_HW;

+	this->ecc.size = 512;

+	this->ecc.read_page = nand_read_page_hwecc_bch;

+	this->ecc.write_page = nand_write_page_hwecc_bch;

+#if defined(CONFIG_MTD_HW_BCH_24BIT)

+	this->ecc.bytes = 39;

+#elif defined(CONFIG_MTD_HW_BCH_20BIT)

+	this->ecc.bytes = 33;

+#elif defined(CONFIG_MTD_HW_BCH_16BIT)

+	this->ecc.bytes = 26;

+#elif defined(CONFIG_MTD_HW_BCH_12BIT)

+	this->ecc.bytes = 20;

+#elif defined(CONFIG_MTD_HW_BCH_8BIT)

+	this->ecc.bytes = 13;

+#else

+	this->ecc.bytes = 7;

+#endif

+#endif

+

+#ifdef  CONFIG_MTD_SW_HM_ECC

+	this->ecc.mode = NAND_ECC_SOFT;

+#endif

+	/* 20 us command delay time */

+	this->chip_delay = 20;

+	/* Scan to find existance of the device */

+	ret = nand_scan_ident(jz_mtd, NAND_MAX_CHIPS);

+

+	if (!ret) {

+		if (this->planenum == 2) {

+			/* reset nand functions */

+			this->erase_cmd = single_erase_cmd_planes;

+			this->ecc.read_page = nand_read_page_hwecc_bch_planes;

+			this->ecc.write_page = nand_write_page_hwecc_bch_planes;

+			this->ecc.read_oob = nand_read_oob_std_planes;

+			this->ecc.write_oob = nand_write_oob_std_planes;

+

+			printk(KERN_INFO "Nand using two-plane mode, "

+			       "and resized to writesize:%d oobsize:%d blocksize:0x%x \n",

+			       jz_mtd->writesize, jz_mtd->oobsize, jz_mtd->erasesize);

+		}

+	}

+

+	/* Determine whether all the partitions will use multiple planes if supported */

+	nr_partitions = sizeof(partition_info) / sizeof(struct mtd_partition);

+	all_use_planes = 1;

+	for (i = 0; i < nr_partitions; i++) {

+		all_use_planes &= partition_info[i].use_planes;

+	}

+

+	if (!ret)

+		ret = nand_scan_tail(jz_mtd);

+

+	if (ret){

+		kfree (jz_mtd1);

+		kfree (jz_mtd);

+		return -ENXIO;

+	}

+

+#if defined(CONFIG_MTD_NAND_DMA)

+	jz4810_nand_dma_init(jz_mtd);

+#endif

+

+ 	((struct nand_chip *) (&jz_mtd1[1]))->ecc.read_page = nand_read_page_hwecc_bch;

+ 	((struct nand_chip *) (&jz_mtd1[1]))->ecc.write_page = nand_write_page_hwecc_bch;

+

+	/* Register the partitions */

+	printk (KERN_NOTICE "Creating %d MTD partitions on \"%s\":\n", nr_partitions, jz_mtd->name);

+

+	if ((this->planenum == 2) && !all_use_planes) {

+		for (i = 0; i < nr_partitions; i++) {

+			if (partition_info[i].use_planes)

+				add_mtd_partitions(jz_mtd, &partition_info[i], 1);

+			else

+				add_mtd_partitions(jz_mtd1, &partition_info[i], 1);

+		}

+	} else {

+		kfree(jz_mtd1);

+		add_mtd_partitions(jz_mtd, partition_info, nr_partitions);

+	}

+	return 0;

+}

+

+module_init(jznand_init);

+

+/*

+ * Clean up routine

+ */

+#ifdef MODULE

+

+#if defined(CONFIG_MTD_NAND_DMA)

+static int jz4810_nand_dma_exit(struct mtd_info *mtd)

+{

+	int pagesize = mtd->writesize / chip->planenum;

+

+#if USE_IRQ

+	free_irq(IRQ_BDMA_0 + nand_dma_chan, NULL);

+	free_irq(IRQ_BDMA_0 + bch_dma_chan, NULL);

+#endif

+

+	/* space for the error reports of bch decoding((4 * 5 * eccsteps) bytes),

+     * and the space for the value of ddr and dcs of channel 0 and channel

+     * nand_dma_chan (4 * (2 + 2) bytes) */

+	kfree(errs);

+

+	/* space for dma_desc_nand_read contains dma_desc_nand_prog,

+	 * dma_desc_enc and dma_desc_dec */

+	free_page((u32)dma_desc_nand_read);

+

+#if defined(CONFIG_MTD_NAND_DMABUF)

+	if (pagesize < 4096) {

+		free_page((u32)prog_buf);

+	} else {

+		free_pages((u32)prog_buf, 1);

+	}

+#endif

+

+#if USE_PN

+	free_page((u32)dma_desc_pPN);

+	free_page((u32)dma_desc_rPN);

+	kfree(pn_buf);

+#endif

+

+	return 0;

+}

+#endif

+

+static void __exit jznand_cleanup(void)

+{

+#if defined(CONFIG_MTD_NAND_DMA)

+	jz4810_nand_dma_exit(jz_mtd);

+#endif

+

+	/* Unregister partitions */

+	del_mtd_partitions(jz_mtd);

+

+	/* Unregister the device */

+	del_mtd_device(jz_mtd);

+

+	/* Free the MTD device structure */

+	if ((this->planenum == 2) && !all_use_planes)

+		kfree (jz_mtd1);

+	kfree(jz_mtd);

+}

+

+module_exit(jznand_cleanup);

+#endif

diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index acb90ead5ef..208174a741b 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -199,6 +199,105 @@ static struct nand_ecclayout nand_oob_128 = {
 #endif
 };
 
+static struct nand_ecclayout nand_oob_218 = {
+#if defined(CONFIG_MTD_HW_RS_ECC)
+/* Reed-Solomon ECC */
+	.eccbytes = 72,
+	.eccpos = {
+		28, 29, 30, 31,	32, 33, 34, 35,
+		36, 37, 38, 39, 40, 41, 42, 43,
+		44, 45, 46, 47, 48, 49, 50, 51,
+		52, 53, 54, 55, 56, 57, 58, 59,
+		60, 61, 62, 63, 64, 65, 66, 67,
+		68, 69, 70, 71, 72, 73, 74, 75,
+		76, 77, 78, 79, 80, 81, 82, 83,
+		84, 85, 86, 87, 88, 89, 90, 91,
+		92, 93, 94, 95,	96, 97, 98, 99},
+	.oobfree = {
+		{.offset = 2,
+		 .length = 26},
+		{.offset = 100,
+		 .length = 28}}
+#elif defined(CONFIG_MTD_HW_BCH_ECC)
+#if !defined(CONFIG_MTD_HW_BCH_8BIT)
+/* 4-bit BCH ECC */
+	.eccbytes = 56,
+	.eccpos = {
+		24, 25, 26, 27,	28, 29, 30, 31,
+		32, 33, 34, 35,	36, 37, 38, 39,
+		40, 41, 42, 43,	44, 45, 46, 47,
+		48, 49, 50, 51,	52, 53, 54, 55,
+		56, 57, 58, 59,	60, 61, 62, 63,
+		64, 65, 66, 67, 68, 69, 70, 71,
+		72, 73, 74, 75, 76, 77, 78, 79},
+	.oobfree = {
+		{.offset = 2,
+		 .length = 22},
+		{.offset = 80,
+		 .length = 48}}
+#else
+/* 8-bit BCH ECC */
+	.eccbytes = 104,
+	.eccpos = {
+		 24, 25, 26, 27, 28, 29, 30, 31,
+		 32, 33, 34, 35, 36, 37, 38, 39,
+		 40, 41, 42, 43, 44, 45, 46, 47,
+		 48, 49, 50, 51, 52, 53, 54, 55,
+		 56, 57, 58, 59, 60, 61, 62, 63,
+		 64, 65, 66, 67, 68, 69, 70, 71,
+		 72, 73, 74, 75, 76, 77, 78, 79,
+		 80, 81, 82, 83, 84, 85, 86, 87,
+		 88, 89, 90, 91, 92, 93, 94, 95,
+		 96, 97, 98, 99, 100, 101, 102, 103,
+		 104, 105, 106, 107, 108, 109, 110, 111,
+		 112, 113, 114, 115, 116, 117, 118, 119,
+		 120, 121, 122, 123, 124, 125, 126, 127,},
+	.oobfree = {
+		 {.offset = 2,
+		  .length = 22}}
+
+#endif
+#else
+/* HW&SW Hamming ECC */
+	.eccbytes = 48,
+	.eccpos = {
+		   80, 81, 82, 83, 84, 85, 86, 87,
+		   88, 89, 90, 91, 92, 93, 94, 95,
+		   96, 97, 98, 99, 100, 101, 102, 103,
+		   104, 105, 106, 107, 108, 109, 110, 111,
+		   112, 113, 114, 115, 116, 117, 118, 119,
+		   120, 121, 122, 123, 124, 125, 126, 127},
+	.oobfree = {
+		{.offset = 2,
+		 .length = 78}}
+#endif
+};
+
+static struct nand_ecclayout nand_oob_436 = {
+/* 24-bit BCH ECC */
+	.eccbytes = 104,
+	.eccpos = {
+		 24, 25, 26, 27, 28, 29, 30, 31,
+		 32, 33, 34, 35, 36, 37, 38, 39,
+		 40, 41, 42, 43, 44, 45, 46, 47,
+		 48, 49, 50, 51, 52, 53, 54, 55,
+		 56, 57, 58, 59, 60, 61, 62, 63,
+		 64, 65, 66, 67, 68, 69, 70, 71,
+		 72, 73, 74, 75, 76, 77, 78, 79,
+		 80, 81, 82, 83, 84, 85, 86, 87,
+		 88, 89, 90, 91, 92, 93, 94, 95,
+		 96, 97, 98, 99, 100, 101, 102, 103,
+		 104, 105, 106, 107, 108, 109, 110, 111,
+		 112, 113, 114, 115, 116, 117, 118, 119,
+		 120, 121, 122, 123, 124, 125, 126, 127,},
+	.oobfree = {
+		 {.offset = 2,
+		  .length = 22}}
+
+};
+
+int get_flash_num(void);
+
 static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
 			   int new_state);
 
@@ -606,6 +705,20 @@ void nand_wait_ready(struct mtd_info *mtd)
 }
 EXPORT_SYMBOL_GPL(nand_wait_ready);
 
+void buffer_dump(uint8_t *buffer, int length, const char *comment, char *file, char *function, int line)
+{
+	int i;
+	uint8_t *temp = buffer;
+	printk("BufferDump: %s %d %s %s %d\n", comment, length, file, function, line);
+	for(i = 0; i < length; i++) {
+		if (i % 16 == 0) printk("\n");
+		printk("%02x ", *temp++);
+	}
+	printk("\nOk.\n");
+}
+
+EXPORT_SYMBOL_GPL(buffer_dump);
+
 /**
  * nand_command - [DEFAULT] Send command to NAND device
  * @mtd:	MTD device structure
@@ -1494,8 +1607,7 @@ static int nand_read(struct mtd_info *mtd, loff_mtd_t from, size_mtd_t len,
 
 int nand_sw_bch_ops(struct mtd_info *mtd, u8 *oobdata, int ops)
 {
-#if !defined(CONFIG_SOC_JZ4750) && !defined(CONFIG_SOC_JZ4750D) && !defined(CONFIG_SOC_JZ4760)
-	//dprintk("%s: Not using jz4750 or jz4760\n", __FUNCTION__);
+#if !defined(CONFIG_SOC_JZ4750) && !defined(CONFIG_SOC_JZ4750D) && !defined(CONFIG_SOC_JZ4760) && !defined(CONFIG_SOC_JZ4760B)
 	return 0;
 #endif
 	
@@ -1684,9 +1796,6 @@ static int nand_do_read_oob(struct mtd_info *mtd, loff_mtd_t from,
 	int len;
 	uint8_t *buf = ops->oobbuf;
 
-	DEBUG(MTD_DEBUG_LEVEL3, "nand_read_oob: from = 0x%08Lx, len = %i\n",
-	      (unsigned long long)from, readlen);
-
 	if (ops->mode == MTD_OOB_AUTO)
 		len = chip->ecc.layout->oobavail;
 	else
@@ -1794,6 +1903,9 @@ static int nand_read_oob(struct mtd_info *mtd, loff_mtd_t from,
 		goto out;
 	}
 
+	DEBUG(MTD_DEBUG_LEVEL3, "nand_read_oob: from = 0x%08Lx,ooblen= %ld,len:%ld,oobretlen:%ld,ops->mode = %d\n",
+	      (unsigned long long)from, ops->ooblen,ops->len,ops->oobretlen,ops->mode);
+
 	if (!ops->datbuf)
 		ret = nand_do_read_oob(mtd, from, ops);
 	else
@@ -2020,7 +2132,11 @@ static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
 	/* Send command to read back the data */
 	chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
 
+#if !defined(CONFIG_SOC_JZ4760B)
 	if (chip->verify_buf(mtd, buf, mtd->writesize))
+#else
+	if (chip->verify_buf(mtd, buf, mtd->validsize))
+#endif
 		return -EIO;
 #endif
 	return 0;
@@ -2100,14 +2216,23 @@ static int nand_do_write_ops(struct mtd_info *mtd, loff_mtd_t to,
 		return 0;
 
 	/* reject writes, which are not page aligned */
+#if !defined(CONFIG_SOC_JZ4760B)
 	if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
+#else
+	if (NOTALIGNED(to)) {
+#endif
 		printk(KERN_NOTICE "nand_write: "
 		       "Attempt to write not page aligned data\n");
 		return -EINVAL;
 	}
 
 	column = to & (mtd->writesize - 1);
+
+#if !defined(CONFIG_SOC_JZ4760B)
 	subpage = column || (writelen & (mtd->writesize - 1));
+#else
+	subpage = column || (writelen % mtd->validsize != 0);
+#endif
 
 	if (subpage && oob)
 		return -EINVAL;
@@ -2133,10 +2258,18 @@ static int nand_do_write_ops(struct mtd_info *mtd, loff_mtd_t to,
 		memset(chip->oob_poi, 0xff, mtd->oobsize);
 
 	while(1) {
+
+#if !defined(CONFIG_SOC_JZ4760B)
 		int bytes = mtd->writesize;
+#else
+		int bytes = mtd->validsize;
+#endif
+
 		int cached = writelen > bytes && page != blockmask;
 		uint8_t *wbuf = buf;
 
+		memset(chip->oob_poi, 0xff, mtd->oobsize);
+
 		/* Partial page write ? */
 		if (unlikely(column || writelen < (mtd->writesize - 1))) {
 			cached = 0;
@@ -2147,9 +2280,10 @@ static int nand_do_write_ops(struct mtd_info *mtd, loff_mtd_t to,
 			wbuf = chip->buffers->databuf;
 		}
 
-		if (unlikely(oob))
+		if (unlikely(oob)) {
 			oob = nand_fill_oob(chip, oob, ops);
-
+			
+		}
 		ret = chip->write_page(mtd, chip, wbuf, page, cached,
 				       (ops->mode == MTD_OOB_RAW));
 		if (ret)
@@ -2444,6 +2578,8 @@ int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
 	if (nand_check_wp(mtd)) {
 		DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
 		      "Device is write protected!!!\n");
+		printk("nand_erase: "
+		      "Device is write protected!!!\n");
 		instr->state = MTD_ERASE_FAILED;
 		goto erase_exit;
 	}
@@ -2498,6 +2634,8 @@ int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
 		if (status & NAND_STATUS_FAIL) {
 			DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
 			      "Failed erase, page 0x%08x\n", page);
+			printk("nand_erase: "
+			      "Failed erase, page 0x%08x\n", page);
 			instr->state = MTD_ERASE_FAILED;
 			instr->fail_addr =
 				((loff_mtd_t)page << chip->page_shift);
@@ -2689,6 +2827,26 @@ static void nand_set_defaults(struct nand_chip *chip, int busw)
 
 }
 
+#if defined(CONFIG_MTD_HW_BCH_ECC)
+static uint32_t calc_free_size(struct mtd_info *mtd)
+{
+	struct nand_chip *this = (struct nand_chip *)mtd->priv;
+	uint32_t freesize;
+	uint32_t pagesize = mtd->writesize;
+	uint32_t oobsize = mtd->oobsize;
+	uint32_t eccsize = this->ecc.size;
+	uint32_t eccbytes = this->ecc.bytes;
+	uint32_t eccpos = this->ecc.layout->eccpos[0];
+
+	if ((pagesize / eccsize + 1) * eccbytes + eccpos > oobsize)
+		freesize = 512;
+	else
+		freesize = 0;
+
+	return freesize;
+} 
+#endif
+
 /*
  * Get the flash and manufacturer id and lookup if the type is supported
  */
@@ -2699,6 +2857,9 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
 	struct nand_flash_dev *type = NULL;
 	int i, dev_id, maf_idx;
 	int tmp_id, tmp_manf;
+	uint8_t ext_id[4] = {0};
+	uint32_t *ext_id_p = ext_id;
+	int flash_num;
 
 	/* Select the device */
 	chip->select_chip(mtd, 0);
@@ -2716,6 +2877,9 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
 	*maf_id = chip->read_byte(mtd);
 	dev_id = chip->read_byte(mtd);
 
+	chip->read_buf(mtd, ext_id, 4);
+	printk("ext_id:0x%08x\n",*ext_id_p);
+
 	/* Try again to make sure, as some systems the bus-hold or other
 	 * interface concerns can cause random data which looks like a
 	 * possibly credible NAND flash to appear. If the two results do
@@ -2736,9 +2900,16 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
 		return ERR_PTR(-ENODEV);
 	}
 
+	flash_num = get_flash_num();
+
+	dev_id |= (*maf_id << 8);
+	printk("dev_id:0x%08x\n",dev_id);
+
+	#define EXTID_MASK	0x00ffffff
+
 	/* Lookup the flash id */
-	for (i = 0; nand_flash_ids[i].name != NULL; i++) {
-		if (dev_id == nand_flash_ids[i].id) {
+	for (i = 0; i < flash_num; i++) {
+		if ((dev_id == nand_flash_ids[i].id) && ((*ext_id_p & EXTID_MASK) == (nand_flash_ids[i].extid & EXTID_MASK))) {
 			type =  &nand_flash_ids[i];
 			break;
 		}
@@ -2750,51 +2921,25 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
 	if (!mtd->name)
 		mtd->name = type->name;
 
-	chip->chipsize = (uint64_t)type->chipsize << 20;
-
-	/* Newer devices have all the information in additional id bytes */
-	if (!type->pagesize) {
-		int extid;
-		/* The 3rd id byte holds MLC / multichip data */
-		chip->cellinfo = chip->read_byte(mtd);
-		/* The 4th id byte is the important one */
-		extid = chip->read_byte(mtd);
-		/* Calc pagesize */
-		mtd->writesize = 1024 << (extid & 0x3);
-		extid >>= 2;
-		/* Calc oobsize */
-		mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
-		extid >>= 2;
-		/* Calc blocksize. Blocksize is multiples of 64KiB */
-		mtd->erasesize = (64 * 1024) << (extid & 0x03);
-		extid >>= 2;
-		/* Get buswidth information */
-		busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
-		/* The 5th id byte */
+	chip->chipsize = (uint64_t)(type->erasesize * type->maxvalidblocks);
+
+	mtd->writesize = type->pagesize;
+	mtd->erasesize = type->erasesize;
+	mtd->oobsize = type->oobsize;
+
 #if defined(CONFIG_MTD_NAND_MULTI_PLANE)
-		extid = chip->read_byte(mtd);
-		chip->realplanenum = 1 << ((extid & 0x0c) >> 2);
+	chip->realplanenum = type->realplanenum;
 #else
-		chip->realplanenum = 1;
+	chip->realplanenum = 1;
 #endif
 
-		if (chip->realplanenum > 1) {     /* use muti planes mode */
-			chip->planenum = 2;
-			mtd->writesize *= 2;  /* two pages as one page */
-			mtd->oobsize *= 2;
-			mtd->erasesize *= 2;  /* two blocks as one block */
-		} else
-			chip->planenum = 1;
-	} else {
-		/*
-		 * Old devices have chip data hardcoded in the device id table
-		 */
-		chip->realplanenum = 1;
-		mtd->erasesize = type->erasesize;
-		mtd->writesize = type->pagesize;
-		mtd->oobsize = mtd->writesize / 32;
-		busw = type->options & NAND_BUSWIDTH_16;
-	}
+	if (chip->realplanenum > 1) {     /* use muti planes mode */
+		chip->planenum = 2;
+		mtd->writesize *= 2;  /* two pages as one page */
+		mtd->erasesize *= 2;  /* two blocks as one block */
+		mtd->oobsize *= 2;
+	} else
+		chip->planenum = 1;
 
 	/* Try to identify manufacturer */
 	for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
@@ -2956,10 +3101,16 @@ int nand_scan_tail(struct mtd_info *mtd)
 			else
 				chip->ecc.layout = &nand_oob_128;
 			break;
+		case 218:
+			chip->ecc.layout = &nand_oob_218;
+			break;
 		case 256:
 			if (chip->planenum > 1)
 				chip->ecc.layout = &nand_oob_128;
 			break;
+		case 436:
+			chip->ecc.layout = &nand_oob_436;
+			break;
 		default:
 			printk(KERN_WARNING "No oob scheme defined for "
 			       "oobsize %d\n", mtd->oobsize);
@@ -2967,6 +3118,14 @@ int nand_scan_tail(struct mtd_info *mtd)
 		}
 	}
 
+#if defined(CONFIG_MTD_HW_BCH_ECC)
+	mtd->freesize = calc_free_size(mtd);
+#else
+	mtd->freesize = 0;
+#endif
+
+	mtd->validsize = mtd->writesize - mtd->freesize;
+
 	if (!chip->write_page)
 		chip->write_page = nand_write_page;
 
@@ -3076,8 +3235,13 @@ int nand_scan_tail(struct mtd_info *mtd)
 	 * Set the number of read / write steps for one page depending on ECC
 	 * mode
 	 */
+#if !defined(CONFIG_SOC_JZ4760B)
 	chip->ecc.steps = mtd->writesize / chip->ecc.size;
 	if(chip->ecc.steps * chip->ecc.size != mtd->writesize) {
+#else
+	chip->ecc.steps = mtd->validsize / chip->ecc.size;
+	if(chip->ecc.steps * chip->ecc.size != mtd->validsize) {
+#endif
 		printk(KERN_WARNING "Invalid ecc parameters\n");
 		BUG();
 	}
@@ -3126,8 +3290,6 @@ int nand_scan_tail(struct mtd_info *mtd)
 	mtd->unlock = NULL;
 	mtd->suspend = NULL;
 	mtd->resume = NULL;
-//	mtd->suspend = nand_suspend;
-//	mtd->resume = nand_resume;
 	mtd->block_isbad = nand_block_isbad;
 	mtd->block_markbad = nand_block_markbad;
 
@@ -3192,6 +3354,7 @@ int nand_scan_tail(struct mtd_info *mtd)
 #if defined(CONFIG_ALLOCATE_MTDBLOCK_JZ_EARLY) && !defined(CONFIG_SOC_JZ4730)
         /* Allocate a block cache for every partitions which works over mtdblock-jz */
 	{
+		printk("CONFIG_ALLOCATE_MTDBLOCK_JZ_EARLY.\n");
 		extern int nr_partitions;
 
 		jz_mtdblock_cache = kzalloc(nr_partitions * sizeof(unsigned char *), GFP_KERNEL);
diff --git a/drivers/mtd/nand/nand_ids.c b/drivers/mtd/nand/nand_ids.c
index f1738212d75..b7c51d25d47 100644
--- a/drivers/mtd/nand/nand_ids.c
+++ b/drivers/mtd/nand/nand_ids.c
@@ -10,6 +10,10 @@
  */
 #include <linux/module.h>
 #include <linux/mtd/nand.h>
+
+#define LP_OPTIONS (NAND_SAMSUNG_LP_OPTIONS | NAND_NO_READRDY | NAND_NO_AUTOINCR)
+#define LP_OPTIONS16 (LP_OPTIONS | NAND_BUSWIDTH_16)
+
 /*
 *	Chip ID list
 *
@@ -21,114 +25,115 @@
 +	256	256 Byte page size
 *	512	512 Byte page size
 */
-struct nand_flash_dev nand_flash_ids[] = {
-
-#ifdef CONFIG_MTD_NAND_MUSEUM_IDS
-	{"NAND 1MiB 5V 8-bit",		0x6e, 256, 1, 0x1000, 0},
-	{"NAND 2MiB 5V 8-bit",		0x64, 256, 2, 0x1000, 0},
-	{"NAND 4MiB 5V 8-bit",		0x6b, 512, 4, 0x2000, 0},
-	{"NAND 1MiB 3,3V 8-bit",	0xe8, 256, 1, 0x1000, 0},
-	{"NAND 1MiB 3,3V 8-bit",	0xec, 256, 1, 0x1000, 0},
-	{"NAND 2MiB 3,3V 8-bit",	0xea, 256, 2, 0x1000, 0},
-	{"NAND 4MiB 3,3V 8-bit",	0xd5, 512, 4, 0x2000, 0},
-	{"NAND 4MiB 3,3V 8-bit",	0xe3, 512, 4, 0x2000, 0},
-	{"NAND 4MiB 3,3V 8-bit",	0xe5, 512, 4, 0x2000, 0},
-	{"NAND 8MiB 3,3V 8-bit",	0xd6, 512, 8, 0x2000, 0},
-
-	{"NAND 8MiB 1,8V 8-bit",	0x39, 512, 8, 0x2000, 0},
-	{"NAND 8MiB 3,3V 8-bit",	0xe6, 512, 8, 0x2000, 0},
-	{"NAND 8MiB 1,8V 16-bit",	0x49, 512, 8, 0x2000, NAND_BUSWIDTH_16},
-	{"NAND 8MiB 3,3V 16-bit",	0x59, 512, 8, 0x2000, NAND_BUSWIDTH_16},
+struct nand_flash_dev nand_flash_ids[] =
+{
+	//	name              	id        	 extid       planenum  dienum   tals    talh	trp	twp    trhw	twhr	pagesize  blocksize oobsize rowcycle maxbadblocks maxvalidblocks eccblock  eccbit  buswidth  badblockpos options
+	{"MICRON_MT29F64G08CFAAA",	0x2CD7,		0x00843E94,	2,	1,	10,	5,	10,	10,	100,	60,	4096,     512*1024,	218,	3,	400,		4096*4,		539,	12,	8,	0,	LP_OPTIONS},
+	{"SAMSUNG_K9GAG08U0D",	  	0xECD5,		0x41342994,	1,	1,	12,	5,	12,	12,	100,	60,	4096,     512*1024, 	218, 	3,	100,		4096,		512,	8,	8,	0,	LP_OPTIONS},
+	{"SAMSUNG_K9GAG08U0M",	  	0xECD5,		0x0074b614,	1,	1,	12,	5,	12,	12,	100,	60,	4096,     512*1024, 	128, 	3,	100,		4096,		512,	8,	8,	0,	LP_OPTIONS},
+	{"SAMSUNG_K9GAG08U0E",	  	0xECD5,		0x42507284,	2,	1,	12,	5,	12,	12,	100,	60,	8192,     1024*1024, 	436, 	3,	100,		2048,		512,	8,	8,	0,	LP_OPTIONS},
+	{"SAMSUNG_K9GAG08U0E",	  	0xECD5,		0x42507284,	2,	1,	12,	5,	12,	12,	100,	60,	8192,     1024*1024, 	436, 	3,	100,		2048,		512,	8,	8,	0,	LP_OPTIONS},
+	{"SAMSUNG_K9GBG08U0M",          0xECD7,         0x42547294,     2,      1,      12,     5,      12,     12,     100,    60,     8192,     1024*1024,    436,    3,      100,            2048,           512,    8,      8,      0,      LP_OPTIONS},
+	{"HYNIX_H8BCS0UN0MCR",		0xADBC,	 	0x00545510,	1,	1,	25,	10,	25,	25,	100,	60,	2048,     128*1024,	64,	3,	80,		4096,		512,	4,	16,	0,	LP_OPTIONS16},
+	{"SAMSUNG_K9G8G08U0M",		0xECD3, 	0x00642514,	2,	1,	15,	5,	15, 	15,	60,   	60,  	2048,     256*1024,	64,     3,	100,		4096,		512,	4,	8,	0,	LP_OPTIONS},
+
+#if 0
+	{"SAMSUNG_K9GBG08U0M", 0xECD7, 0x00547294,	1,	    	15,	5,	15,	15,	100,  60,  8192,     1024*1024,	436, 	3,	100,		4096,		,	0,	,	,	},
+	{"SAMSUNG_K9F1G08U0M", 0xECF1,		0,     	1,		15, 	5,	15,	15,  	100,  60,  2048,     128*1024,	64, 	3,	20,		1024,		,	0,	,	,	},
+	{"SAMSUNG_K9GAG08U0D", 0xECD5, 0x00342994,  	1,		15,	5,	15,	15, 	100,  60,  4096,     512*1024,  128,    3,	100,		4096,		,	0,	,	,	},
+	{"SAMSUNG_K9GAG08U0M", 0xECD5, 0x0074b614,  	1,	   	12,	5,	12,	12,	100,  60,  4096,     512*1024, 	128, 	3,	100,		4096,		512,	4,	,	,	},
+	{"SAMSUNG_K9HBG08U1M", 0xECD5, 0x00682555,  0x800002,		15,	5,	15,	15,  	100,  60,  2048,     256*1024,	64, 	3,	200,		8192,		,	0,	,	,	},
+	{"SAMSUNG_K9HBG08U1M", 0xECD5, 0x01682555,  0x800002,		15,	5,	15,	15,  	100,  60,  2048,     256*1024,	64, 	3,      200*2,		8192*2,		,	0,	,	,	},
+	{"SAMSUNG_K9LBG08U0M", 0xECD7, 0x0078B655,     1,	   	12,	5,	15,	15,	100,  60,  4096,     512*1024,	64, 	3,      200,		8192,		,	0,	,	,	},
+	
+	{"SAMSUNG_K9G8G08U0A", 0xECD3, 0x0064a514,      2,		12,	5,  	12,	12,  	100,  60,  2048,     256*1024,	64, 	3,	100,		4096,		,	0,	,	,	},
+	{"SAMSUNG_K9K8G08U0A", 0xECD3, 0x00589551,  0x400002,		12, 	5,   	12,	12,  	100,  60,  2048,     128*1024,	64, 	3,	160,		8192,		,	0,	,	,	},
+	{"SAMSUNG_K9G8G08U0B", 0xECD3, 0x0064a514,      2,		12,	5,   	12,	12,  	100,  60,  2048,     256*1024,	64, 	3,	100,		4096,		,	0,	,	,	},
+	{"SAMSUNG_K9LAG08U0M", 0xECD5, 0x00682555,  0x800002,		12, 	5,   	12,	12,  	 60,  60,  2048,     256*1024,	64, 	3,	200,		8192,		,	0,	,	,	},
+	{"SAMSUNG_K9WAG08U1M", 0xECD3, 0x01589551,  0x400002,		12,	5,   	12,	12,  	100,  60,  2048,     128*1024,	64, 	3,	160*2,		8192*2,		512,	1,	,	,	},
+	{"SAMSUNG_K9LAG08U1M", 0xECD3, 0x01642514,	2,		15,	5,   	15,	15,  	100,  60,  2048,     256*1024,	64, 	3,	200,		8192,		,	0,	,	,	},
+	{"SAMSUNG_K9LAG08U0A", 0xECD5, 0x00682555,  0x800002,		15,	5,   	15,	15,  	100,  60,  2048,     256*1024,	64, 	3,	200,		8192,		,	0,	,	,	},
+	{"SAMSUNG_K9HBG08U1A", 0xECD5, 0x01682555,  0x800002,		15,	5,   	15,	15,  	100,  60,  2048,     256*1024,	64, 	3,	200*2,		8192*2,		,	0,	,	,	},
+	{"SAMSUNG_K9F4G08U0A", 0xECD3, 0x00549510,	2,		12,	5,   	12,	12,  	100,  60,  2048,     512*1024,	64, 	3,	80,		4096,		512,	1,	,	,	},
+	{"SAMSUNG_K9K8G08U0M", 0xECD3, 0x00589551,	2,		12,	5,   	12,	12,  	100,  60,  2048,     1024*1024,	64, 	3,	160,		8192,		512,	1,	,	,	},
+	
+	{"HYNIX_HY27UU08AG5M", 0xADD3, 0x0064A514,  	2,		12,	5,	12,	12,	100,  80,  2048,     256*1024,	64, 	3,	100,		4096,		,	0,	,	,	},
+	{"HYNIX_HY27UU08AG5M", 0xADD3, 0x0164A514,  	2,		12, 	5,	12,	12,	100,  80,  2048,     256*1024,	64, 	3,	200,		8192,		,	0,	,	,	},
+	{"HYNIX_HY27UT088G2M", 0xADD3, 0x0064A514,  0x400002,		12,	5,	12,	12,	100,  80,  2048,     256*1024,	64, 	3,	100,		4096,		528,	4,	,	,	},
+	{"HYNIX_HY27UT088G2A", 0xADD3, 0x0034A514,  	2,		12,  	5,   	12,	12,  	100,  80,  2048,     256*1024,	64, 	3,	100,		4096,		528,	4,	,	,	},
+	{"HYNIX_HY27UF081G2M", 0xADF1, 0x00001500,  	1,		5, 	15,  	25,	40,	60,   60,  2048,     128*1024,	64, 	2,	20,		1024,		,	0,	,	,	},
+	{"HYNIX_HY27UU08AG5A", 0xADD3, 0x0134A514,  	2,		12,  	5,   	12,	12,  	100,  80,  2048,     256*1024,	64, 	3,	200,		8192,		528,	4,	,	,	},
+	{"HYNIX_HY27UV08BG5A", 0xADD5, 0x0138A555,  0x800002,		12, 	5,   	12,	12,	100,  80,  2048,     256*1024,	64, 	3,	200*2,		8192*2,		528,	4,	,	,	},
+	{"HYNIX_HY27UU088G5M", 0xADDC, 0x01002584,      1,		5,  	15,  	40,	40,	80,   80,  2048,     256*1024,	64, 	3,	118,		4096,		,	0,	,	,	},
+	{"HYNIX_HY27UF082G2M", 0xADDA, 0x00001500,  	1,		0,  	10,  	25,	25,  	60,   60,  2048,     128*1024,	64, 	3,	40,		2048,		,	0,	,	,	},
+	{"HYNIX_HY27UF084G2M", 0xADDC, 0x00009580,  	1,		15,  	5,   	15,	15,  	60,   60,  2048,     128*1024,	64, 	3,	80,		4096,		512,	1,	,	,	},
+	{"HYNIX_HY27UT084G2M", 0xADDC, 0x00002584,  	1,		5, 	15,	40,	40,  	80,   80,  2048,     256*1024,	64, 	3,	59,		2048,		512,	4,	,	,	},
+	
+	{"MICRON_MT29F16G08MAA",  0x2CD3, 0x00743E94,   1,	 	10, 	5,   	10,	10,  	100,  60,  4096,     512*1024,	128,	3,	160,		4096,		539,	8,	,	,	},
+	{"MICRON_MT29F32G08QAA",  0x2CD5, 0x00743E94,   1,	 	10, 	5,   	10,	10,  	100,  60,  4096,     512*1024,	128,	3,	160*2,		4096*2,		,	0,	,	,	},
+	{"MICRON_MT29F64G08TAA",  0x2CD5, 0x00783ED5,   1,	 	10, 	5,   	10,	10,  	100,  60,  4096,     512*1024,	128,	3,	160*4,		4096*4,		,	0,	,	,	},
+	{"MICRON_MT29F32G08CBAAA",0x2CD7, 0x00843E94,   1,	 	10, 	5,   	10,	10,  	100,  60,  4096,     512*1024,	218,	3,	200,		8192,		,	0,	,	,	},		
+	
+	{"INTEL_29F16G08AAMC1",	  0x89D5, 0x00743E94,   1,		10, 	5,   	10,	10,  	100,  60,  4096,     512*1024,	128, 	3,	160,		4096,		539,	8,	,	,	},
+	{"INTEL_29F32G08CAMC1",	  0x89D5, 0x01743E94,   1,		10, 	5,   	10,	10,  	100,  60,  4096,     512*1024,	128, 	3,	160*2,		4096*2,		539,	8,	,	,	},
+	{"INTEL_29F64G08FAMC1",	  0x89D7, 0x01783ED5,   1,		10,	5,   	10,	10,  	100,  60,  4096,     512*1024,	128, 	3,	160*4,		4096*4,		539,	8,	,	,	},
+	{"INTEL_29F32G08AAMD1",	  0x89D7, 0x00843E94,   1,		10,	5,   	10,	10,  	100,  60,  4096,     512*1024,	218, 	3,	160,		4096,		,	0,	,	,	},
+	{"INTEL_29F32G08AAMDB",	  0x8968, 0x00a94604,   1,		10,  	5,   	10,	10,  	100,  60,  4096,     1024*1024,	218, 	3,	160,		4096,		,	0,	,	,	},
+
+
+
+		///////////////////////////////////////////////////
+		//The following list no tested......
+		///////////////////////////////////////////////////
+	
+	{"HYNIX_HY27UV08AG5A",	 0xADD3, 0x01002585,	1,		5,  	15,	40,	40,	80,   80,  2048,      256*1024, 64, 	3,             236,          8192,         528,  4        	,	},
+	{"HYNIX_HY27UV08BG5M",	 0xADD5, 0x0138A555,	2,		12,	5,	12,	12,	100,  80,  2048,      256*1024, 64, 	3,             400,         16384,         ,        0       ,	},
+	{"HYNIX_HY27UF081G2A",	 0xADF1, 0x00001D80,	1,		15,	5,	15,	15,	60,   60,  2048,      128*1024, 64, 	2,             20,          1024,          528,  1        	,	},
+	{"HYNIX_HY27UH08AGDM",	 0xADD3, 0x010095C1,	1,		15,	5,	15,	15,	60,   60,  2048,      128*1024, 64, 	3,             160*2,        8192*2,       512,  1       ,	},
+	{"HYNIX_HY27UH08AG5M",	 0xADD3, 0x010095C1,	1,		15,	5,	15,	15,	60,   60,  2048,      128*1024, 64, 	3,             160*2,        8192*2,       512,  1       ,	},
+	{"HYNIX_HY27UH088GDM",	 0xADDC, 0x00001500,	1,		5,	10,	25,	25,   60,   60,  2048,      128*1024, 64, 	3,             160,          8192,         ,     0        	,	},
+	{"HYNIX_HY27UH088G2M",	 0xADD3, 0x00001500,	1,		5,	10,	25,	25,   60,   60,  2048,      128*1024, 64, 	3,             160,          8192,         ,        0     	,	},
+	{"HYNIX_HY27UG088G5M",	 0xADDC, 0x01009580,	1,		15,	5,	15,	15,   60,   60,  2048,      128*1024, 64, 	3,             160,          8192,         512,  1        	,	},
+	{"HYNIX_HY27UG088GDM",	 0xADDC, 0x01009580,	1,		15,	5,	15,	15,   60,   60,  2048,      128*1024, 64, 	3,             160,          8192,         512,  1        	,	},
+	{"HYNIX_HY27UG084G2M",	 0xADDC, 0x00001500,	1,		5,	10,	25,	25,   60,   60,  2048,      128*1024, 64, 	3,             80,          4096,          ,     0        	,	},
+	{"HYNIX_HY27UG084GDM",	 0xADDA, 0x00001500,	1,		5,	10,	25,	25,   60,   60,  2048,      128*1024, 64, 	3,             80,          4096,           ,    0        	,	},
+	{"HYNIX_HY27UV08AG5M",	 0xADD3, 0x01002585,	1,		5,	15,	40,	40,  	80,   80,  2048,      256*1024, 64, 	3,             236,          8192,         528,  4        	,	},	
+		
+	{"SAMSUNG_K9L8G08U0M",	 0xECD3, 0x00582555,	2,		15,	5,	15,	15,  	100,  60,	 2048,      256*1024, 64, 	3,             100,          4096,          ,     0        	},
+	{"SAMSUNG_K9G4G08U0A",	 0xECDC, 0x00542514,	2,		15,	5,	15,	15,  	100,  60,  2048,      256*1024, 64, 	3,             50,          2048,           512,  4        	},	
+	{"SAMSUNG_K9MCG08U5M", 	 0xECD5, 0x03682555,0x800002,		25,	10,	25,	25,  	100,  60,  2048,      256*1024, 64, 	3,             200*4,        8192*4,        ,    0        	},
+	{"SAMSUNG_K9HCG08U1M",	 0xECD7, 0x0178B655,	1,		12,	5,	12,	12,  	100,  60,  4096,      512*1024, 128, 	3,             200*2,        8192*2,         ,     0        	},
+	{"SAMSUNG_K9K8G08U1M",	 0xECD3, 0x01009510,	1,		12,	5,	12,	12,  	100,  60,  2048,      128*1024, 64, 	3,             80*2,        4096*2,         ,     0        	},
+	{"SAMSUNG_K9W8G08U1M",	 0xECDC, 0x01001500,	1,		0,	10,	25,	15,  	100,  60,  2048,      128*1024, 64, 	3,             80*2,        4096*2,          ,     0        	},
+	{"SAMSUNG_K9F8G08U0M",	 0xECD3, 0x0064A610,	1,		12,	5,	12,	12,  	100,  60,  4096,      256*1024, 128, 	3,             80,          4096,           ,     0        	},
+	{"SAMSUNG_K9NBG08U5M",	 0xECD3, 0x03589551,0x400002,		25,	10,	25,	25,  	100,  60,  2048,      128*1024, 64, 	3,             160*4,        8192*4,         512,     1        	},
+	{"SAMSUNG_K9HAG08U1M",	 0xECD3, 0x01642514,	2,		15,	5,	15,	15,  	100,  60,  2048,      256*1024, 64, 	3,             200,          8192,           ,    0        	},
+		
+	{"MICRON_MT29F8G08FACWP",0x2CDC, 0x01001500,	1,		10,	5,	15,	15,   60,   60,  2048,      128*1024,  64, 		3,           80*2,        4096*2,          ,     0        	},
+	{"MICRON_MT29F8G08FABWP",0x2CDC, 0x01001500,	1,		10,	5,	15,	15,   60,   60,  2048,      128*1024,  64, 		3,           80*2,        4096*2,          ,     0        	},
+	{"MICRON_MT29F8G08BAA",	 0x2CD3, 0x005895D1,0x400002,		25,	10,	25,	25,  	100,  60,  2048,      128*1024,  64, 		3,           160,          8192,           ,     0       	},
+	{"MICRON_MT29F8G08DAA",	 0x2CDC, 0x01549590,	2,		25,	10,	25,	25,  	100,  60,  2048,      128*1024,  64, 		3,           80*2,        4096*2,          ,     0       	},
+	{"MICRON_MT29F16G08FAA", 0x2CD3, 0x015895D1,0x400002,		25,	10,	25,	25,  	100,  60,  2048,      128*1024,  64, 		3,           160*2,        8192*2,         ,     0        	},
+	{"MICRON_MT29F8G08AAA",	 0x2CD3, 0x00642E90,	1,		10,	5,	10,	10,  	100,  60,  4096,      256*1024,  128, 	3,          80,          4096,             ,     0        	},
+	{"MICRON_MT29F16G08DAA", 0x2CD3, 0x01642E90,	1,		10,	5,	10,	10,  	100,  60,  4096,      256*1024,  128, 		3,         80*2,        4096*2,           ,     0       	},
+	{"MICRON_MT29F32G08FAA", 0x2CD5, 0x01682ED1,	1,		10,	5,	10,	10,  	100,  60,  4096,      256*1024,  128, 		3,         160*2,        8192*2,          ,     0        	},
+	{"MICRON_MT29F8G08MAAWC",0x2CD3, 0x0064A594,	2,		10,	5,	15,	15,   60,   60,  2048,      256*1024,   64, 		3,         80,          4096,            ,     0        	},
+	{"MICRON_MT29F16G08QAAWC",0x2CD3,0x0164A594,	2,		10,	5,	25,	15,  	100,  60,  2048,      256*1024,   64, 		3,         80*2,        4096*2,          ,     0        	},
+	{"MICRON_MT29F32G08TAAWC",0x2CD5,0x0168A5D5,0x800002,		10,	5,	25,	15,  	100,  60,  2048,      256*1024,  64, 		3,           160*2,        8192*2,         ,     0        	},
+	{"MICRON_MT29F1G08ABB",	 0x2CA1, 0x00009580,	1,		25,	10,	25,	25,  	100,  80,  2048,      128*1024,  64, 		2,           80,          4096,             ,     0        	},
+	
+	{"INTEL_29F16G08FANB1",  0x89D3, 0x015895D1,0x400002,		25,	10,	25,	25,  	100,  60,  2048,      128*1024,   64, 		3,         160*2,        8192*2,         ,     0        	},
+	{"INTEL_29F08G08AAMB1",	 0x89D3, 0x0064A594,	2,		10,	5,	10,	15,  	100,  60,  2048,      256*1024,   64, 		3,         160,          4096,           ,     0        	},
+	{"INTEL_29F16G08CAMB1",  0x89D3, 0x0164A594,	2,		10,	5,	10,	15,  	100,  60,  2048,      256*1024,   64, 		3,         320,          8192,           ,     0        	},
+	{"INTEL_29F32G08FAMB1",  0x89D5, 0x0168A5D5,0x800002,		10,	5,	10,	15,  	100,  60,  2048,      256*1024,   64, 		3,         320*2,        8192*2,         ,     0        	},
+	{"INTEL_29F08G08AAMB2",  0x89D3, 0x0064A594,	2,		10,	5,	8,	15,  	100,  60,  2048,      256*1024,   64, 		3,         160,          4096,           ,     0        	},
+	{"INTEL_29F16G08CAMB2",  0x89D3, 0x0164A594,	2,		10,	5,	8,	15,  	100,  60,  2048,      256*1024,   64, 		3,         160*2,        4096*2,         ,     0        	},
+	{"INTEL_29F32G08FAMB2",  0x89D5, 0x0168A5D5,0x800002,		10,	5,	8,	15,  	100,  60,  2048,      256*1024,   64, 		3,         320*2,        8192*2,         ,     0        	},
+	
+	{"STMICRON_NAND08GW3B2AN6",0x20D3, 0x00009581,	1,		15,	5,	15,	15,   60,   60,  2048,      128*1024,   64, 		3,         160,          8192,           ,     0        	},
+	{"STMICRON_NAND08GW3C2AN1",0x20D3, 0x006CA514,	2,		12,	5,	12,	12,  	100,  80,  2048,      256*1024,   64, 		3,         80,          4096,            528,    4        	},
 #endif
 
-	{"NAND 16MiB 1,8V 8-bit",	0x33, 512, 16, 0x4000, 0},
-	{"NAND 16MiB 3,3V 8-bit",	0x73, 512, 16, 0x4000, 0},
-	{"NAND 16MiB 1,8V 16-bit",	0x43, 512, 16, 0x4000, NAND_BUSWIDTH_16},
-	{"NAND 16MiB 3,3V 16-bit",	0x53, 512, 16, 0x4000, NAND_BUSWIDTH_16},
-
-	{"NAND 32MiB 1,8V 8-bit",	0x35, 512, 32, 0x4000, 0},
-	{"NAND 32MiB 3,3V 8-bit",	0x75, 512, 32, 0x4000, 0},
-	{"NAND 32MiB 1,8V 16-bit",	0x45, 512, 32, 0x4000, NAND_BUSWIDTH_16},
-	{"NAND 32MiB 3,3V 16-bit",	0x55, 512, 32, 0x4000, NAND_BUSWIDTH_16},
-
-	{"NAND 64MiB 1,8V 8-bit",	0x36, 512, 64, 0x4000, 0},
-	{"NAND 64MiB 3,3V 8-bit",	0x76, 512, 64, 0x4000, 0},
-	{"NAND 64MiB 1,8V 16-bit",	0x46, 512, 64, 0x4000, NAND_BUSWIDTH_16},
-	{"NAND 64MiB 3,3V 16-bit",	0x56, 512, 64, 0x4000, NAND_BUSWIDTH_16},
-
-	{"NAND 128MiB 1,8V 8-bit",	0x78, 512, 128, 0x4000, 0},
-	{"NAND 128MiB 1,8V 8-bit",	0x39, 512, 128, 0x4000, 0},
-	{"NAND 128MiB 3,3V 8-bit",	0x79, 512, 128, 0x4000, 0},
-	{"NAND 128MiB 1,8V 16-bit",	0x72, 512, 128, 0x4000, NAND_BUSWIDTH_16},
-	{"NAND 128MiB 1,8V 16-bit",	0x49, 512, 128, 0x4000, NAND_BUSWIDTH_16},
-	{"NAND 128MiB 3,3V 16-bit",	0x74, 512, 128, 0x4000, NAND_BUSWIDTH_16},
-	{"NAND 128MiB 3,3V 16-bit",	0x59, 512, 128, 0x4000, NAND_BUSWIDTH_16},
-
-	{"NAND 256MiB 3,3V 8-bit",	0x71, 512, 256, 0x4000, 0},
-
-	/*
-	 * These are the new chips with large page size. The pagesize and the
-	 * erasesize is determined from the extended id bytes
-	 */
-#define LP_OPTIONS (NAND_SAMSUNG_LP_OPTIONS | NAND_NO_READRDY | NAND_NO_AUTOINCR)
-#define LP_OPTIONS16 (LP_OPTIONS | NAND_BUSWIDTH_16)
-
-	/*512 Megabit */
-	{"NAND 64MiB 1,8V 8-bit",	0xA2, 0,  64, 0, LP_OPTIONS},
-	{"NAND 64MiB 3,3V 8-bit",	0xF2, 0,  64, 0, LP_OPTIONS},
-	{"NAND 64MiB 1,8V 16-bit",	0xB2, 0,  64, 0, LP_OPTIONS16},
-	{"NAND 64MiB 3,3V 16-bit",	0xC2, 0,  64, 0, LP_OPTIONS16},
-
-	/* 1 Gigabit */
-	{"NAND 128MiB 1,8V 8-bit",	0xA1, 0, 128, 0, LP_OPTIONS},
-	{"NAND 128MiB 3,3V 8-bit",	0xF1, 0, 128, 0, LP_OPTIONS},
-	{"NAND 128MiB 1,8V 16-bit",	0xB1, 0, 128, 0, LP_OPTIONS16},
-	{"NAND 128MiB 3,3V 16-bit",	0xC1, 0, 128, 0, LP_OPTIONS16},
-
-	/* 2 Gigabit */
-	{"NAND 256MiB 1,8V 8-bit",	0xAA, 0, 256, 0, LP_OPTIONS},
-	{"NAND 256MiB 3,3V 8-bit",	0xDA, 0, 256, 0, LP_OPTIONS},
-	{"NAND 256MiB 1,8V 16-bit",	0xBA, 0, 256, 0, LP_OPTIONS16},
-	{"NAND 256MiB 3,3V 16-bit",	0xCA, 0, 256, 0, LP_OPTIONS16},
-
-	/* 4 Gigabit */
-	{"NAND 512MiB 1,8V 8-bit",	0xAC, 0, 512, 0, LP_OPTIONS},
-	{"NAND 512MiB 3,3V 8-bit",	0xDC, 0, 512, 0, LP_OPTIONS},
-	{"NAND 512MiB 1,8V 16-bit",	0xBC, 0, 512, 0, LP_OPTIONS16},
-	{"NAND 512MiB 3,3V 16-bit",	0xCC, 0, 512, 0, LP_OPTIONS16},
-
-	/* 8 Gigabit */
-	{"NAND 1GiB 1,8V 8-bit",	0xA3, 0, 1024, 0, LP_OPTIONS},
-	{"NAND 1GiB 3,3V 8-bit",	0xD3, 0, 1024, 0, LP_OPTIONS},
-	{"NAND 1GiB 1,8V 16-bit",	0xB3, 0, 1024, 0, LP_OPTIONS16},
-	{"NAND 1GiB 3,3V 16-bit",	0xC3, 0, 1024, 0, LP_OPTIONS16},
-
-	/* 16 Gigabit */
-	{"NAND 2GiB 1,8V 8-bit",	0xA5, 0, 2048, 0, LP_OPTIONS},
-	{"NAND 2GiB 3,3V 8-bit",	0xD5, 0, 2048, 0, LP_OPTIONS},
-	{"NAND 2GiB 1,8V 16-bit",	0xB5, 0, 2048, 0, LP_OPTIONS16},
-	{"NAND 2GiB 3,3V 16-bit",	0xC5, 0, 2048, 0, LP_OPTIONS16},
-
-	/* 32 Gigabit */
-	{"NAND 4GiB 3,3V 8-bit",	0xD7, 0, 4096, 0, LP_OPTIONS},
-
-
-	/*
-	 * Renesas AND 1 Gigabit. Those chips do not support extended id and
-	 * have a strange page/block layout !  The chosen minimum erasesize is
-	 * 4 * 2 * 2048 = 16384 Byte, as those chips have an array of 4 page
-	 * planes 1 block = 2 pages, but due to plane arrangement the blocks
-	 * 0-3 consists of page 0 + 4,1 + 5, 2 + 6, 3 + 7 Anyway JFFS2 would
-	 * increase the eraseblock size so we chose a combined one which can be
-	 * erased in one go There are more speed improvements for reads and
-	 * writes possible, but not implemented now
-	 */
-	{"AND 128MiB 3,3V 8-bit",	0x01, 2048, 128, 0x4000,
-	 NAND_IS_AND | NAND_NO_AUTOINCR |NAND_NO_READRDY | NAND_4PAGE_ARRAY |
-	 BBT_AUTO_REFRESH
-	},
-
-	{NULL,}
 };
 
 /*
@@ -147,8 +152,14 @@ struct nand_manufacturers nand_manuf_ids[] = {
 	{0x0, "Unknown"}
 };
 
+int get_flash_num(void)
+{
+	return (sizeof(nand_flash_ids) / sizeof(struct nand_flash_dev));
+}
+
 EXPORT_SYMBOL(nand_manuf_ids);
 EXPORT_SYMBOL(nand_flash_ids);
+EXPORT_SYMBOL(get_flash_num);
 
 MODULE_LICENSE("GPL");
 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 38dcee7469a..31e5dff5b59 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -218,7 +218,7 @@ config JZ_ETH
 
 config JZCS8900
 	tristate "JZ CS8900A Ethernet support"
-	depends on NET_ETHERNET && (SOC_JZ4740 || SOC_JZ4750 || SOC_JZ4760 )
+	depends on NET_ETHERNET && (SOC_JZ4740 || SOC_JZ4750 || SOC_JZ4760 || SOC_JZ4760B)
 	help
 	  Say Y for support of JZ CS8900A Ethernet interface.
 
@@ -227,13 +227,22 @@ config JZCS8900
 
 config JZ4760_ETH
 	tristate "JZ4760 On-Chip Ethernet support"
-	depends on NET_ETHERNET && (SOC_JZ4760 || SOC_JZ4810 || JZ_FPGA)
+	depends on NET_ETHERNET && (SOC_JZ4760 || SOC_JZ4810 || SOC_JZ4770 || JZ_FPGA)
 	help
 	  Say Y for support of JZ4760 On-Chip Ethernet interface.
 
 	  To compile this driver as a module, choose M here: the module
 	  will be called jz4760_eth.
 
+config JZ_AX88796C
+	tristate "AX88796C for Ingenic SOC"
+	depends on NET_ETHERNET && JZSOC
+	help
+	  Say Y for support of AX88796C Ethernet interface on Ingenic SOC.
+
+	  To compile this driver as a module, choose M here: the module
+	  will be called ax88796c.
+
 
 config MACB
 	tristate "Atmel MACB support"
@@ -3239,4 +3248,6 @@ config VIRTIO_NET
 	  This is the virtual network driver for virtio.  It can be used with
           lguest or QEMU based VMMs (like KVM or Xen).  Say Y or M.
 
+source "drivers/net/ath6kl/Kconfig"
+
 endif # NETDEVICES
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index b723ed5fac6..419d3be82b5 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -106,6 +106,7 @@ obj-$(CONFIG_PHYLIB) += phy/
 obj-$(CONFIG_JZ_ETH) += jz_eth.o
 obj-$(CONFIG_JZCS8900) += jzcs8900a.o
 obj-$(CONFIG_JZ4760_ETH) += jz4760_eth.o
+obj-$(CONFIG_JZ_AX88796C) += ax88796c/
 
 obj-$(CONFIG_SUNDANCE) += sundance.o
 obj-$(CONFIG_HAMACHI) += hamachi.o
@@ -284,3 +285,5 @@ obj-$(CONFIG_VIRTIO_NET) += virtio_net.o
 obj-$(CONFIG_SFC) += sfc/
 
 obj-$(CONFIG_WIMAX) += wimax/
+
+obj-$(CONFIG_ATH6K_LEGACY)      += ath6kl/
diff --git a/drivers/net/ath6kl/Kconfig b/drivers/net/ath6kl/Kconfig
new file mode 100644
index 00000000000..793b8d80c67
--- /dev/null
+++ b/drivers/net/ath6kl/Kconfig
@@ -0,0 +1,161 @@
+config ATH6K_LEGACY
+	tristate "Atheros AR6003 support (non mac80211)"
+        depends on MMC
+	help
+	This module adds support for wireless adapters based on Atheros AR6003 chipset running over SDIO. If you choose to build it as a module, it will be called ath6kl. Pls note that AR6002 and AR6001 are not supported by this driver.
+
+choice
+	prompt "AR6003 Board Data Configuration"
+	depends on ATH6K_LEGACY
+	default AR600x_SD31_XXX
+	help
+	Select the appropriate board data template from the list below that matches your AR6003 based reference design.
+
+config AR600x_SD31_XXX
+	bool "SD31-xxx"
+	help
+        Board Data file for a standard SD31 reference design (File: bdata.SD31.bin)
+
+config AR600x_WB31_XXX
+	bool "WB31-xxx"
+	help
+        Board Data file for a standard WB31 (BT/WiFi) reference design (File: bdata.WB31.bin)
+
+config AR600x_SD32_XXX
+	bool "SD32-xxx"
+	help
+        Board Data file for a standard SD32 (5GHz) reference design (File: bdata.SD32.bin)
+
+config AR600x_CUSTOM_XXX
+	bool "CUSTOM-xxx"
+	help
+        Board Data file for a custom reference design (File: should be named as bdata.CUSTOM.bin)
+endchoice
+
+config ATH6KL_ENABLE_COEXISTENCE
+	bool "BT Coexistence support"
+	depends on ATH6K_LEGACY
+	help
+	Enables WLAN/BT coexistence support. Select the apprpriate configuration from below.
+
+choice
+	prompt "Front-End Antenna Configuration"
+	depends on ATH6KL_ENABLE_COEXISTENCE
+	default AR600x_DUAL_ANTENNA
+	help
+	Indicates the number of antennas being used by BT and WLAN. Select the appropriate configuration from the list below that matches your AR6003 based reference design.
+
+config AR600x_DUAL_ANTENNA
+	bool "Dual Antenna"
+	help
+        Dual Antenna Design
+
+config AR600x_SINGLE_ANTENNA
+	bool "Single Antenna"
+	help
+        Single Antenna Design
+endchoice
+
+choice
+	prompt "Collocated Bluetooth Type"
+	depends on ATH6KL_ENABLE_COEXISTENCE
+	default AR600x_BT_AR3001
+	help
+	Select the appropriate configuration from the list below that matches your AR6003 based reference design.
+
+config AR600x_BT_QCOM
+	bool "Qualcomm BTS4020X"
+	help
+        Qualcomm BT (3 Wire PTA)
+
+config AR600x_BT_CSR
+	bool "CSR BC06"
+	help
+        CSR BT (3 Wire PTA)
+
+config AR600x_BT_AR3001
+	bool "Atheros AR3001"
+	help
+        Atheros BT (3 Wire PTA)
+endchoice
+
+config ATH6KL_HCI_BRIDGE
+	bool "HCI over SDIO support"
+	depends on ATH6K_LEGACY
+	help
+	Enables BT over SDIO. Applicable only for combo designs (eg: WB31)
+
+config ATH6KL_CONFIG_GPIO_BT_RESET
+	bool "Configure BT Reset GPIO"
+	depends on ATH6KL_HCI_BRIDGE
+	help
+	Configure a WLAN GPIO for use with BT.
+
+config AR600x_BT_RESET_PIN
+	int "GPIO"
+	depends on ATH6KL_CONFIG_GPIO_BT_RESET
+	default 22
+	help
+	WLAN GPIO to be used for resetting BT
+
+config ATH6KL_CFG80211
+	bool "CFG80211 support"
+	depends on ATH6K_LEGACY && CFG80211
+	help
+	Enables support for CFG80211 APIs. The default option is to use WEXT. Even with this option enabled, WEXT is not explicitly disabled and the onus of not exercising WEXT lies on the application(s) running in the user space.
+
+config ATH6KL_HTC_RAW_INTERFACE
+	bool "RAW HTC support"
+	depends on ATH6K_LEGACY
+	help
+	Enables raw HTC interface. Allows application to directly talk to the HTC interface via the ioctl interface
+
+config ATH6KL_VIRTUAL_SCATTER_GATHER
+	bool "Virtual Scatter-Gather support"
+	depends on ATH6K_LEGACY
+	help
+	Enables virtual scatter gather support for the hardware that does not support it natively.
+
+config ATH6KL_SKIP_ABI_VERSION_CHECK
+	bool "Skip ABI version check support"
+	depends on ATH6K_LEGACY
+	help
+	Forces the driver to disable ABI version check. Caution: Incompatilbity between the host driver and target firmware may lead to unknown side effects.
+
+config ATH6KL_BT_UART_FC_POLARITY
+	int "UART Flow Control Polarity"
+	depends on ATH6KL_LEGACY
+	default 0
+	help
+	Configures the polarity of UART Flow Control. A value of 0 implies active low and is the default setting. Set it to 1 for active high.
+
+config ATH6KL_DEBUG
+	bool "Debug support"
+	depends on ATH6K_LEGACY
+	help
+	Enables debug support
+
+config ATH6KL_ENABLE_HOST_DEBUG
+	bool "Host Debug support"
+	depends on ATH6KL_DEBUG
+	help
+	Enables debug support in the driver
+
+config ATH6KL_ENABLE_TARGET_DEBUG_PRINTS
+	bool "Target Debug support - Enable UART prints"
+	depends on ATH6KL_DEBUG
+	help
+	Enables uart prints
+
+config AR600x_DEBUG_UART_TX_PIN
+	int "GPIO"
+	depends on ATH6KL_ENABLE_TARGET_DEBUG_PRINTS
+	default 8
+	help
+	WLAN GPIO to be used for Debug UART (Tx)
+
+config ATH6KL_DISABLE_TARGET_DBGLOGS
+	bool "Target Debug support - Disable Debug logs"
+	depends on ATH6KL_DEBUG
+	help
+	Enables debug logs
diff --git a/drivers/net/ath6kl/Makefile b/drivers/net/ath6kl/Makefile
new file mode 100644
index 00000000000..ab68078699f
--- /dev/null
+++ b/drivers/net/ath6kl/Makefile
@@ -0,0 +1,159 @@
+#------------------------------------------------------------------------------
+# Copyright (c) 2004-2010 Atheros Communications Inc.
+# All rights reserved.
+#
+# 
+#
+# Permission to use, copy, modify, and/or distribute this software for any
+# purpose with or without fee is hereby granted, provided that the above
+# copyright notice and this permission notice appear in all copies.
+#
+# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+#
+#
+#
+# Author(s): ="Atheros"
+#------------------------------------------------------------------------------
+
+ccflags-y += -I$(obj)/include
+ccflags-y += -I$(obj)/include/common
+ccflags-y += -I$(obj)/wlan/include
+ccflags-y += -I$(obj)/os/linux/include
+ccflags-y += -I$(obj)/os
+ccflags-y += -I$(obj)/bmi/include
+ccflags-y += -I$(obj)/include/common/AR6002/hw4.0
+
+ifeq ($(CONFIG_AR600x_SD31_XXX),y)
+ccflags-y += -DAR600x_SD31_XXX
+endif
+
+ifeq ($(CONFIG_AR600x_WB31_XXX),y)
+ccflags-y += -DAR600x_WB31_XXX
+endif
+
+ifeq ($(CONFIG_AR600x_SD32_XXX),y)
+ccflags-y += -DAR600x_SD32_XXX
+endif
+
+ifeq ($(CONFIG_AR600x_CUSTOM_XXX),y)
+ccflags-y += -DAR600x_CUSTOM_XXX
+endif
+
+ifeq ($(CONFIG_ATH6KL_ENABLE_COEXISTENCE),y)
+ccflags-y += -DENABLE_COEXISTENCE
+endif
+
+ifeq ($(CONFIG_AR600x_DUAL_ANTENNA),y)
+ccflags-y += -DAR600x_DUAL_ANTENNA
+endif
+
+ifeq ($(CONFIG_AR600x_SINGLE_ANTENNA),y)
+ccflags-y += -DAR600x_SINGLE_ANTENNA
+endif
+
+ifeq ($(CONFIG_AR600x_BT_QCOM),y)
+ccflags-y += -DAR600x_BT_QCOM
+endif
+
+ifeq ($(CONFIG_AR600x_BT_CSR),y)
+ccflags-y += -DAR600x_BT_CSR
+endif
+
+ifeq ($(CONFIG_AR600x_BT_AR3001),y)
+ccflags-y += -DAR600x_BT_AR3001
+endif
+
+ifeq ($(CONFIG_ATH6KL_HCI_BRIDGE),y)
+ccflags-y += -DATH_AR6K_ENABLE_GMBOX
+ccflags-y += -DHCI_TRANSPORT_SDIO
+ccflags-y += -DSETUPHCI_ENABLED
+ccflags-y += -DSETUPBTDEV_ENABLED
+ath6kl-y += htc2/AR6000/ar6k_gmbox.o
+ath6kl-y += htc2/AR6000/ar6k_gmbox_hciuart.o
+ath6kl-y += miscdrv/ar3kconfig.o
+ath6kl-y += miscdrv/ar3kps/ar3kpsconfig.o
+ath6kl-y += miscdrv/ar3kps/ar3kpsparser.o
+endif
+
+ifeq ($(CONFIG_ATH6KL_CONFIG_GPIO_BT_RESET),y)
+ccflags-y += -DATH6KL_CONFIG_GPIO_BT_RESET
+endif
+
+ifeq ($(CONFIG_ATH6KL_CFG80211),y)
+ccflags-y += -DATH6K_CONFIG_CFG80211
+ath6kl-y += os/linux/cfg80211.o
+endif
+
+ifeq ($(CONFIG_ATH6KL_HTC_RAW_INTERFACE),y)
+ccflags-y += -DHTC_RAW_INTERFACE
+endif
+
+ifeq ($(CONFIG_ATH6KL_ENABLE_HOST_DEBUG),y)
+ccflags-y += -DDEBUG
+ccflags-y += -DATH_DEBUG_MODULE
+endif
+
+ifeq ($(CONFIG_ATH6KL_ENABLE_TARGET_DEBUG_PRINTS),y)
+ccflags-y += -DENABLEUARTPRINT_SET
+endif
+
+ifeq ($(CONFIG_ATH6KL_DISABLE_TARGET_DBGLOGS),y)
+ccflags-y += -DATH6KL_DISABLE_TARGET_DBGLOGS
+endif
+
+ifeq ($(CONFIG_ATH6KL_VIRTUAL_SCATTER_GATHER),y)
+ccflags-y += -DATH6KL_CONFIG_HIF_VIRTUAL_SCATTER
+endif
+
+ifeq ($(CONFIG_ATH6KL_SKIP_ABI_VERSION_CHECK),y)
+ccflags-y += -DATH6KL_SKIP_ABI_VERSION_CHECK
+endif
+
+ccflags-y += -DLINUX -DKERNEL_2_6
+ccflags-y += -DTCMD
+ccflags-y += -DSEND_EVENT_TO_APP
+ccflags-y += -DUSER_KEYS
+ccflags-y += -DNO_SYNC_FLUSH
+ccflags-y += -DHTC_EP_STAT_PROFILING
+ccflags-y += -DATH_AR6K_11N_SUPPORT
+ccflags-y += -DWAPI_ENABLE
+ccflags-y += -DCHECKSUM_OFFLOAD
+ccflags-y += -DWLAN_HEADERS
+ccflags-y += -DINIT_MODE_DRV_ENABLED
+ccflags-y += -DBMIENABLE_SET
+
+obj-$(CONFIG_ATH6K_LEGACY) := ath6kl.o
+ath6kl-y += htc2/AR6000/ar6k.o
+ath6kl-y += htc2/AR6000/ar6k_events.o
+ath6kl-y += htc2/htc_send.o
+ath6kl-y += htc2/htc_recv.o
+ath6kl-y += htc2/htc_services.o
+ath6kl-y += htc2/htc.o
+ath6kl-y += bmi/src/bmi.o
+ath6kl-y += os/linux/ar6000_drv.o
+ath6kl-y += os/linux/ar6000_raw_if.o
+ath6kl-y += os/linux/ar6000_pm.o
+ath6kl-y += os/linux/netbuf.o
+ath6kl-y += os/linux/wireless_ext.o
+ath6kl-y += os/linux/ioctl.o
+ath6kl-y += os/linux/hci_bridge.o
+ath6kl-y += os/linux/ar6k_pal.o
+ath6kl-y += miscdrv/common_drv.o
+ath6kl-y += miscdrv/credit_dist.o
+ath6kl-y += wmi/wmi.o
+ath6kl-y += reorder/rcv_aggr.o
+ath6kl-y += wlan/src/wlan_node.o
+ath6kl-y += wlan/src/wlan_recv_beacon.o
+ath6kl-y += wlan/src/wlan_utils.o			 
+
+# ATH_HIF_TYPE := sdio
+ccflags-y += -I$(obj)/hif/sdio/linux_sdio/include
+ccflags-y += -DSDIO
+ath6kl-y += hif/sdio/linux_sdio/src/hif.o
+ath6kl-y += hif/sdio/linux_sdio/src/hif_scatter.o
diff --git a/drivers/net/ath6kl/TODO b/drivers/net/ath6kl/TODO
new file mode 100644
index 00000000000..d4629274397
--- /dev/null
+++ b/drivers/net/ath6kl/TODO
@@ -0,0 +1,8 @@
+- The driver is a stop-gap measure until a proper mac80211 driver is available.
+- The driver does not conform to the Linux coding style.
+- The driver has been tested on a wide variety of embedded platforms running different versions of the Linux kernel but may still have bringup/performance issues with a new platform.
+- Pls use the following link to get information about the driver's architecture, exposed APIs, supported features, limitations, testing, hardware availability and other details.
+	http://wireless.kernel.org/en/users/Drivers/ath6kl
+- Pls send any patches to
+	- Greg Kroah-Hartman <greg@kroah.com>
+	- Vipin Mehta <vmehta@atheros.com>
diff --git a/drivers/net/ath6kl/bmi/include/bmi_internal.h b/drivers/net/ath6kl/bmi/include/bmi_internal.h
new file mode 100644
index 00000000000..a44027cee4e
--- /dev/null
+++ b/drivers/net/ath6kl/bmi/include/bmi_internal.h
@@ -0,0 +1,55 @@
+//------------------------------------------------------------------------------
+// Copyright (c) 2004-2010 Atheros Communications Inc.
+// All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef BMI_INTERNAL_H
+#define BMI_INTERNAL_H
+
+#include "a_config.h"
+#include "athdefs.h"
+#include "a_types.h"
+#include "a_osapi.h"
+#define ATH_MODULE_NAME bmi
+#include "a_debug.h"
+#include "AR6002/hw2.0/hw/mbox_host_reg.h"
+#include "bmi_msg.h"
+
+#define ATH_DEBUG_BMI  ATH_DEBUG_MAKE_MODULE_MASK(0)
+
+
+#define BMI_COMMUNICATION_TIMEOUT       100000
+
+/* ------ Global Variable Declarations ------- */
+static A_BOOL bmiDone;
+
+A_STATUS
+bmiBufferSend(HIF_DEVICE *device,
+              A_UCHAR *buffer,
+              A_UINT32 length);
+
+A_STATUS
+bmiBufferReceive(HIF_DEVICE *device,
+                 A_UCHAR *buffer,
+                 A_UINT32 length,
+                 A_BOOL want_timeout);
+
+#endif
diff --git a/drivers/net/ath6kl/bmi/src/bmi.c b/drivers/net/ath6kl/bmi/src/bmi.c
new file mode 100644
index 00000000000..f17f5636f5b
--- /dev/null
+++ b/drivers/net/ath6kl/bmi/src/bmi.c
@@ -0,0 +1,1010 @@
+//------------------------------------------------------------------------------
+// <copyright file="bmi.c" company="Atheros">
+//    Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+//
+// Author(s): ="Atheros"
+//==============================================================================
+
+
+#ifdef THREAD_X
+#include <string.h>
+#endif
+
+#include "hif.h"
+#include "bmi.h"
+#include "htc_api.h"
+#include "bmi_internal.h"
+
+#ifdef ATH_DEBUG_MODULE
+static ATH_DEBUG_MASK_DESCRIPTION bmi_debug_desc[] = {
+    { ATH_DEBUG_BMI , "BMI Tracing"},
+};
+
+ATH_DEBUG_INSTANTIATE_MODULE_VAR(bmi,
+                                 "bmi",
+                                 "Boot Manager Interface",
+                                 ATH_DEBUG_MASK_DEFAULTS,
+                                 ATH_DEBUG_DESCRIPTION_COUNT(bmi_debug_desc),
+                                 bmi_debug_desc);
+                                 
+#endif
+
+/*
+Although we had envisioned BMI to run on top of HTC, this is not how the
+final implementation ended up. On the Target side, BMI is a part of the BSP
+and does not use the HTC protocol nor even DMA -- it is intentionally kept
+very simple.
+*/
+
+static A_BOOL pendingEventsFuncCheck = FALSE; 
+static A_UINT32 *pBMICmdCredits;
+static A_UCHAR *pBMICmdBuf;
+#define MAX_BMI_CMDBUF_SZ (BMI_DATASZ_MAX + \
+                       sizeof(A_UINT32) /* cmd */ + \
+                       sizeof(A_UINT32) /* addr */ + \
+                       sizeof(A_UINT32))/* length */
+#define BMI_COMMAND_FITS(sz) ((sz) <= MAX_BMI_CMDBUF_SZ)
+    
+/* APIs visible to the driver */
+void
+BMIInit(void)
+{
+    bmiDone = FALSE;
+    pendingEventsFuncCheck = FALSE;
+
+    /*
+     * On some platforms, it's not possible to DMA to a static variable
+     * in a device driver (e.g. Linux loadable driver module).
+     * So we need to A_MALLOC space for "command credits" and for commands.
+     *
+     * Note: implicitly relies on A_MALLOC to provide a buffer that is
+     * suitable for DMA (or PIO).  This buffer will be passed down the
+     * bus stack.
+     */
+    if (!pBMICmdCredits) {
+        pBMICmdCredits = (A_UINT32 *)A_MALLOC_NOWAIT(4);
+        A_ASSERT(pBMICmdCredits);
+    }
+
+    if (!pBMICmdBuf) {
+        pBMICmdBuf = (A_UCHAR *)A_MALLOC_NOWAIT(MAX_BMI_CMDBUF_SZ);
+        A_ASSERT(pBMICmdBuf);
+    }
+    
+    A_REGISTER_MODULE_DEBUG_INFO(bmi);
+}
+
+void
+BMICleanup(void)
+{
+    if (pBMICmdCredits) {
+        A_FREE(pBMICmdCredits);
+        pBMICmdCredits = NULL;
+    }
+
+    if (pBMICmdBuf) {
+        A_FREE(pBMICmdBuf);
+        pBMICmdBuf = NULL;
+    }
+}
+
+A_STATUS
+BMIDone(HIF_DEVICE *device)
+{
+    A_STATUS status;
+    A_UINT32 cid;
+
+    if (bmiDone) {
+        AR_DEBUG_PRINTF (ATH_DEBUG_BMI, ("BMIDone skipped\n"));
+        return A_OK;
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Done: Enter (device: 0x%p)\n", device));
+    bmiDone = TRUE;
+    cid = BMI_DONE;
+
+    status = bmiBufferSend(device, (A_UCHAR *)&cid, sizeof(cid));
+    if (status != A_OK) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n"));
+        return A_ERROR;
+    }
+
+    if (pBMICmdCredits) {
+        A_FREE(pBMICmdCredits);
+        pBMICmdCredits = NULL;
+    }
+
+    if (pBMICmdBuf) {
+        A_FREE(pBMICmdBuf);
+        pBMICmdBuf = NULL;
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Done: Exit\n"));
+
+    return A_OK;
+}
+
+A_STATUS
+BMIGetTargetInfo(HIF_DEVICE *device, struct bmi_target_info *targ_info)
+{
+    A_STATUS status;
+    A_UINT32 cid;
+
+    if (bmiDone) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n"));
+        return A_ERROR;
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Get Target Info: Enter (device: 0x%p)\n", device));
+    cid = BMI_GET_TARGET_INFO;
+
+    status = bmiBufferSend(device, (A_UCHAR *)&cid, sizeof(cid));
+    if (status != A_OK) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n"));
+        return A_ERROR;
+    }
+
+    status = bmiBufferReceive(device, (A_UCHAR *)&targ_info->target_ver,
+                                                sizeof(targ_info->target_ver), TRUE);
+    if (status != A_OK) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read Target Version from the device\n"));
+        return A_ERROR;
+    }
+
+    if (targ_info->target_ver == TARGET_VERSION_SENTINAL) {
+        /* Determine how many bytes are in the Target's targ_info */
+        status = bmiBufferReceive(device, (A_UCHAR *)&targ_info->target_info_byte_count,
+                                            sizeof(targ_info->target_info_byte_count), TRUE);
+        if (status != A_OK) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read Target Info Byte Count from the device\n"));
+            return A_ERROR;
+        }
+
+        /*
+         * The Target's targ_info doesn't match the Host's targ_info.
+         * We need to do some backwards compatibility work to make this OK.
+         */
+        A_ASSERT(targ_info->target_info_byte_count == sizeof(*targ_info));
+
+        /* Read the remainder of the targ_info */
+        status = bmiBufferReceive(device,
+                        ((A_UCHAR *)targ_info)+sizeof(targ_info->target_info_byte_count),
+                        sizeof(*targ_info)-sizeof(targ_info->target_info_byte_count), TRUE);
+        if (status != A_OK) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read Target Info (%d bytes) from the device\n",
+                        					targ_info->target_info_byte_count));
+            return A_ERROR;
+        }
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Get Target Info: Exit (ver: 0x%x type: 0x%x)\n",
+        							targ_info->target_ver, targ_info->target_type));
+
+    return A_OK;
+}
+
+A_STATUS
+BMIReadMemory(HIF_DEVICE *device,
+              A_UINT32 address,
+              A_UCHAR *buffer,
+              A_UINT32 length)
+{
+    A_UINT32 cid;
+    A_STATUS status;
+    A_UINT32 offset;
+    A_UINT32 remaining, rxlen;
+
+    A_ASSERT(BMI_COMMAND_FITS(BMI_DATASZ_MAX + sizeof(cid) + sizeof(address) + sizeof(length)));
+    memset (pBMICmdBuf, 0, BMI_DATASZ_MAX + sizeof(cid) + sizeof(address) + sizeof(length));
+
+    if (bmiDone) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n"));
+        return A_ERROR;
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_BMI,
+       			("BMI Read Memory: Enter (device: 0x%p, address: 0x%x, length: %d)\n",
+        			device, address, length));
+
+    cid = BMI_READ_MEMORY;
+
+    remaining = length;
+
+    while (remaining)
+    {
+        rxlen = (remaining < BMI_DATASZ_MAX) ? remaining : BMI_DATASZ_MAX;
+        offset = 0;
+        A_MEMCPY(&(pBMICmdBuf[offset]), &cid, sizeof(cid));
+        offset += sizeof(cid);
+        A_MEMCPY(&(pBMICmdBuf[offset]), &address, sizeof(address));
+        offset += sizeof(address);
+        A_MEMCPY(&(pBMICmdBuf[offset]), &rxlen, sizeof(rxlen));
+        offset += sizeof(length);
+
+        status = bmiBufferSend(device, pBMICmdBuf, offset);
+        if (status != A_OK) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n"));
+            return A_ERROR;
+        }
+        status = bmiBufferReceive(device, pBMICmdBuf, rxlen, TRUE);
+        if (status != A_OK) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read from the device\n"));
+            return A_ERROR;
+        }
+        A_MEMCPY(&buffer[length - remaining], pBMICmdBuf, rxlen);
+        remaining -= rxlen; address += rxlen;
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Read Memory: Exit\n"));
+    return A_OK;
+}
+
+A_STATUS
+BMIWriteMemory(HIF_DEVICE *device,
+               A_UINT32 address,
+               A_UCHAR *buffer,
+               A_UINT32 length)
+{
+    A_UINT32 cid;
+    A_STATUS status;
+    A_UINT32 offset;
+    A_UINT32 remaining, txlen;
+    const A_UINT32 header = sizeof(cid) + sizeof(address) + sizeof(length);
+    A_UCHAR alignedBuffer[BMI_DATASZ_MAX];
+    A_UCHAR *src;
+
+    A_ASSERT(BMI_COMMAND_FITS(BMI_DATASZ_MAX + header));
+    memset (pBMICmdBuf, 0, BMI_DATASZ_MAX + header);
+
+    if (bmiDone) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n"));
+        return A_ERROR;
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_BMI,
+         ("BMI Write Memory: Enter (device: 0x%p, address: 0x%x, length: %d)\n",
+         device, address, length));
+
+    cid = BMI_WRITE_MEMORY;
+
+    remaining = length;
+    while (remaining)
+    {
+        src = &buffer[length - remaining];
+        if (remaining < (BMI_DATASZ_MAX - header)) {
+            if (remaining & 3) {
+                /* align it with 4 bytes */
+                remaining = remaining + (4 - (remaining & 3));
+                memcpy(alignedBuffer, src, remaining);
+                src = alignedBuffer;
+            } 
+            txlen = remaining;
+        } else {
+            txlen = (BMI_DATASZ_MAX - header);
+        }
+        offset = 0;
+        A_MEMCPY(&(pBMICmdBuf[offset]), &cid, sizeof(cid));
+        offset += sizeof(cid);
+        A_MEMCPY(&(pBMICmdBuf[offset]), &address, sizeof(address));
+        offset += sizeof(address);
+        A_MEMCPY(&(pBMICmdBuf[offset]), &txlen, sizeof(txlen));
+        offset += sizeof(txlen);
+        A_MEMCPY(&(pBMICmdBuf[offset]), src, txlen);
+        offset += txlen;
+        status = bmiBufferSend(device, pBMICmdBuf, offset);
+        if (status != A_OK) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n"));
+            return A_ERROR;
+        }
+        remaining -= txlen; address += txlen;
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Write Memory: Exit\n"));
+
+    return A_OK;
+}
+
+A_STATUS
+BMIExecute(HIF_DEVICE *device,
+           A_UINT32 address,
+           A_UINT32 *param)
+{
+    A_UINT32 cid;
+    A_STATUS status;
+    A_UINT32 offset;
+
+    A_ASSERT(BMI_COMMAND_FITS(sizeof(cid) + sizeof(address) + sizeof(param)));
+    memset (pBMICmdBuf, 0, sizeof(cid) + sizeof(address) + sizeof(param));
+
+    if (bmiDone) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n"));
+        return A_ERROR;
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_BMI,
+       ("BMI Execute: Enter (device: 0x%p, address: 0x%x, param: %d)\n",
+        device, address, *param));
+
+    cid = BMI_EXECUTE;
+
+    offset = 0;
+    A_MEMCPY(&(pBMICmdBuf[offset]), &cid, sizeof(cid));
+    offset += sizeof(cid);
+    A_MEMCPY(&(pBMICmdBuf[offset]), &address, sizeof(address));
+    offset += sizeof(address);
+    A_MEMCPY(&(pBMICmdBuf[offset]), param, sizeof(*param));
+    offset += sizeof(*param);
+    status = bmiBufferSend(device, pBMICmdBuf, offset);
+    if (status != A_OK) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n"));
+        return A_ERROR;
+    }
+
+    status = bmiBufferReceive(device, pBMICmdBuf, sizeof(*param), FALSE);
+    if (status != A_OK) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read from the device\n"));
+        return A_ERROR;
+    }
+
+    A_MEMCPY(param, pBMICmdBuf, sizeof(*param));
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Execute: Exit (param: %d)\n", *param));
+    return A_OK;
+}
+
+A_STATUS
+BMISetAppStart(HIF_DEVICE *device,
+               A_UINT32 address)
+{
+    A_UINT32 cid;
+    A_STATUS status;
+    A_UINT32 offset;
+
+    A_ASSERT(BMI_COMMAND_FITS(sizeof(cid) + sizeof(address)));
+    memset (pBMICmdBuf, 0, sizeof(cid) + sizeof(address));
+
+    if (bmiDone) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n"));
+        return A_ERROR;
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_BMI,
+       ("BMI Set App Start: Enter (device: 0x%p, address: 0x%x)\n",
+        device, address));
+
+    cid = BMI_SET_APP_START;
+
+    offset = 0;
+    A_MEMCPY(&(pBMICmdBuf[offset]), &cid, sizeof(cid));
+    offset += sizeof(cid);
+    A_MEMCPY(&(pBMICmdBuf[offset]), &address, sizeof(address));
+    offset += sizeof(address);
+    status = bmiBufferSend(device, pBMICmdBuf, offset);
+    if (status != A_OK) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n"));
+        return A_ERROR;
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Set App Start: Exit\n"));
+    return A_OK;
+}
+
+A_STATUS
+BMIReadSOCRegister(HIF_DEVICE *device,
+                   A_UINT32 address,
+                   A_UINT32 *param)
+{
+    A_UINT32 cid;
+    A_STATUS status;
+    A_UINT32 offset;
+
+    A_ASSERT(BMI_COMMAND_FITS(sizeof(cid) + sizeof(address)));
+    memset (pBMICmdBuf, 0, sizeof(cid) + sizeof(address));
+
+    if (bmiDone) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n"));
+        return A_ERROR;
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_BMI,
+       ("BMI Read SOC Register: Enter (device: 0x%p, address: 0x%x)\n",
+       device, address));
+
+    cid = BMI_READ_SOC_REGISTER;
+
+    offset = 0;
+    A_MEMCPY(&(pBMICmdBuf[offset]), &cid, sizeof(cid));
+    offset += sizeof(cid);
+    A_MEMCPY(&(pBMICmdBuf[offset]), &address, sizeof(address));
+    offset += sizeof(address);
+
+    status = bmiBufferSend(device, pBMICmdBuf, offset);
+    if (status != A_OK) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n"));
+        return A_ERROR;
+    }
+
+    status = bmiBufferReceive(device, pBMICmdBuf, sizeof(*param), TRUE);
+    if (status != A_OK) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read from the device\n"));
+        return A_ERROR;
+    }
+    A_MEMCPY(param, pBMICmdBuf, sizeof(*param));
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Read SOC Register: Exit (value: %d)\n", *param));
+    return A_OK;
+}
+
+A_STATUS
+BMIWriteSOCRegister(HIF_DEVICE *device,
+                    A_UINT32 address,
+                    A_UINT32 param)
+{
+    A_UINT32 cid;
+    A_STATUS status;
+    A_UINT32 offset;
+
+    A_ASSERT(BMI_COMMAND_FITS(sizeof(cid) + sizeof(address) + sizeof(param)));
+    memset (pBMICmdBuf, 0, sizeof(cid) + sizeof(address) + sizeof(param));
+
+    if (bmiDone) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n"));
+        return A_ERROR;
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_BMI,
+     ("BMI Write SOC Register: Enter (device: 0x%p, address: 0x%x, param: %d)\n",
+     device, address, param));
+
+    cid = BMI_WRITE_SOC_REGISTER;
+
+    offset = 0;
+    A_MEMCPY(&(pBMICmdBuf[offset]), &cid, sizeof(cid));
+    offset += sizeof(cid);
+    A_MEMCPY(&(pBMICmdBuf[offset]), &address, sizeof(address));
+    offset += sizeof(address);
+    A_MEMCPY(&(pBMICmdBuf[offset]), &param, sizeof(param));
+    offset += sizeof(param);
+    status = bmiBufferSend(device, pBMICmdBuf, offset);
+    if (status != A_OK) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n"));
+        return A_ERROR;
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Read SOC Register: Exit\n"));
+    return A_OK;
+}
+
+A_STATUS
+BMIrompatchInstall(HIF_DEVICE *device,
+                   A_UINT32 ROM_addr,
+                   A_UINT32 RAM_addr,
+                   A_UINT32 nbytes,
+                   A_UINT32 do_activate,
+                   A_UINT32 *rompatch_id)
+{
+    A_UINT32 cid;
+    A_STATUS status;
+    A_UINT32 offset;
+
+    A_ASSERT(BMI_COMMAND_FITS(sizeof(cid) + sizeof(ROM_addr) + sizeof(RAM_addr) +
+				sizeof(nbytes) + sizeof(do_activate)));
+    memset(pBMICmdBuf, 0, sizeof(cid) + sizeof(ROM_addr) + sizeof(RAM_addr) +
+			sizeof(nbytes) + sizeof(do_activate));
+
+    if (bmiDone) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n"));
+        return A_ERROR;
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_BMI,
+         ("BMI rompatch Install: Enter (device: 0x%p, ROMaddr: 0x%x, RAMaddr: 0x%x length: %d activate: %d)\n",
+         device, ROM_addr, RAM_addr, nbytes, do_activate));
+
+    cid = BMI_ROMPATCH_INSTALL;
+
+    offset = 0;
+    A_MEMCPY(&(pBMICmdBuf[offset]), &cid, sizeof(cid));
+    offset += sizeof(cid);
+    A_MEMCPY(&(pBMICmdBuf[offset]), &ROM_addr, sizeof(ROM_addr));
+    offset += sizeof(ROM_addr);
+    A_MEMCPY(&(pBMICmdBuf[offset]), &RAM_addr, sizeof(RAM_addr));
+    offset += sizeof(RAM_addr);
+    A_MEMCPY(&(pBMICmdBuf[offset]), &nbytes, sizeof(nbytes));
+    offset += sizeof(nbytes);
+    A_MEMCPY(&(pBMICmdBuf[offset]), &do_activate, sizeof(do_activate));
+    offset += sizeof(do_activate);
+    status = bmiBufferSend(device, pBMICmdBuf, offset);
+    if (status != A_OK) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n"));
+        return A_ERROR;
+    }
+
+    status = bmiBufferReceive(device, pBMICmdBuf, sizeof(*rompatch_id), TRUE);
+    if (status != A_OK) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read from the device\n"));
+        return A_ERROR;
+    }
+    A_MEMCPY(rompatch_id, pBMICmdBuf, sizeof(*rompatch_id));
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI rompatch Install: (rompatch_id=%d)\n", *rompatch_id));
+    return A_OK;
+}
+
+A_STATUS
+BMIrompatchUninstall(HIF_DEVICE *device,
+                     A_UINT32 rompatch_id)
+{
+    A_UINT32 cid;
+    A_STATUS status;
+    A_UINT32 offset;
+
+    A_ASSERT(BMI_COMMAND_FITS(sizeof(cid) + sizeof(rompatch_id)));
+    memset (pBMICmdBuf, 0, sizeof(cid) + sizeof(rompatch_id));
+
+    if (bmiDone) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n"));
+        return A_ERROR;
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_BMI,
+         ("BMI rompatch Uninstall: Enter (device: 0x%p, rompatch_id: %d)\n",
+         								 device, rompatch_id));
+
+    cid = BMI_ROMPATCH_UNINSTALL;
+
+    offset = 0;
+    A_MEMCPY(&(pBMICmdBuf[offset]), &cid, sizeof(cid));
+    offset += sizeof(cid);
+    A_MEMCPY(&(pBMICmdBuf[offset]), &rompatch_id, sizeof(rompatch_id));
+    offset += sizeof(rompatch_id);
+    status = bmiBufferSend(device, pBMICmdBuf, offset);
+    if (status != A_OK) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n"));
+        return A_ERROR;
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI rompatch UNinstall: (rompatch_id=0x%x)\n", rompatch_id));
+    return A_OK;
+}
+
+static A_STATUS
+_BMIrompatchChangeActivation(HIF_DEVICE *device,
+                             A_UINT32 rompatch_count,
+                             A_UINT32 *rompatch_list,
+                             A_UINT32 do_activate)
+{
+    A_UINT32 cid;
+    A_STATUS status;
+    A_UINT32 offset;
+    A_UINT32 length;
+
+    A_ASSERT(BMI_COMMAND_FITS(BMI_DATASZ_MAX + sizeof(cid) + sizeof(rompatch_count)));
+    memset(pBMICmdBuf, 0, BMI_DATASZ_MAX + sizeof(cid) + sizeof(rompatch_count));
+
+    if (bmiDone) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n"));
+        return A_ERROR;
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_BMI,
+         ("BMI Change rompatch Activation: Enter (device: 0x%p, count: %d)\n",
+           device, rompatch_count));
+
+    cid = do_activate ? BMI_ROMPATCH_ACTIVATE : BMI_ROMPATCH_DEACTIVATE;
+
+    offset = 0;
+    A_MEMCPY(&(pBMICmdBuf[offset]), &cid, sizeof(cid));
+    offset += sizeof(cid);
+    A_MEMCPY(&(pBMICmdBuf[offset]), &rompatch_count, sizeof(rompatch_count));
+    offset += sizeof(rompatch_count);
+    length = rompatch_count * sizeof(*rompatch_list);
+    A_MEMCPY(&(pBMICmdBuf[offset]), rompatch_list, length);
+    offset += length;
+    status = bmiBufferSend(device, pBMICmdBuf, offset);
+    if (status != A_OK) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n"));
+        return A_ERROR;
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Change rompatch Activation: Exit\n"));
+
+    return A_OK;
+}
+
+A_STATUS
+BMIrompatchActivate(HIF_DEVICE *device,
+                    A_UINT32 rompatch_count,
+                    A_UINT32 *rompatch_list)
+{
+    return _BMIrompatchChangeActivation(device, rompatch_count, rompatch_list, 1);
+}
+
+A_STATUS
+BMIrompatchDeactivate(HIF_DEVICE *device,
+                      A_UINT32 rompatch_count,
+                      A_UINT32 *rompatch_list)
+{
+    return _BMIrompatchChangeActivation(device, rompatch_count, rompatch_list, 0);
+}
+
+A_STATUS
+BMILZData(HIF_DEVICE *device,
+          A_UCHAR *buffer,
+          A_UINT32 length)
+{
+    A_UINT32 cid;
+    A_STATUS status;
+    A_UINT32 offset;
+    A_UINT32 remaining, txlen;
+    const A_UINT32 header = sizeof(cid) + sizeof(length);
+
+    A_ASSERT(BMI_COMMAND_FITS(BMI_DATASZ_MAX+header));
+    memset (pBMICmdBuf, 0, BMI_DATASZ_MAX+header);
+
+    if (bmiDone) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n"));
+        return A_ERROR;
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_BMI,
+         ("BMI Send LZ Data: Enter (device: 0x%p, length: %d)\n",
+         device, length));
+
+    cid = BMI_LZ_DATA;
+
+    remaining = length;
+    while (remaining)
+    {
+        txlen = (remaining < (BMI_DATASZ_MAX - header)) ?
+                                       remaining : (BMI_DATASZ_MAX - header);
+        offset = 0;
+        A_MEMCPY(&(pBMICmdBuf[offset]), &cid, sizeof(cid));
+        offset += sizeof(cid);
+        A_MEMCPY(&(pBMICmdBuf[offset]), &txlen, sizeof(txlen));
+        offset += sizeof(txlen);
+        A_MEMCPY(&(pBMICmdBuf[offset]), &buffer[length - remaining], txlen);
+        offset += txlen;
+        status = bmiBufferSend(device, pBMICmdBuf, offset);
+        if (status != A_OK) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n"));
+            return A_ERROR;
+        }
+        remaining -= txlen;
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI LZ Data: Exit\n"));
+
+    return A_OK;
+}
+
+A_STATUS
+BMILZStreamStart(HIF_DEVICE *device,
+                 A_UINT32 address)
+{
+    A_UINT32 cid;
+    A_STATUS status;
+    A_UINT32 offset;
+
+    A_ASSERT(BMI_COMMAND_FITS(sizeof(cid) + sizeof(address)));
+    memset (pBMICmdBuf, 0, sizeof(cid) + sizeof(address));
+
+    if (bmiDone) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n"));
+        return A_ERROR;
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_BMI,
+         ("BMI LZ Stream Start: Enter (device: 0x%p, address: 0x%x)\n",
+         device, address));
+
+    cid = BMI_LZ_STREAM_START;
+    offset = 0;
+    A_MEMCPY(&(pBMICmdBuf[offset]), &cid, sizeof(cid));
+    offset += sizeof(cid);
+    A_MEMCPY(&(pBMICmdBuf[offset]), &address, sizeof(address));
+    offset += sizeof(address);
+    status = bmiBufferSend(device, pBMICmdBuf, offset);
+    if (status != A_OK) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to Start LZ Stream to the device\n"));
+        return A_ERROR;
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI LZ Stream Start: Exit\n"));
+
+    return A_OK;
+}
+
+/* BMI Access routines */
+A_STATUS
+bmiBufferSend(HIF_DEVICE *device,
+              A_UCHAR *buffer,
+              A_UINT32 length)
+{
+    A_STATUS status;
+    A_UINT32 timeout;
+    A_UINT32 address;
+    A_UINT32 mboxAddress[HTC_MAILBOX_NUM_MAX];
+
+    HIFConfigureDevice(device, HIF_DEVICE_GET_MBOX_ADDR,
+                       &mboxAddress[0], sizeof(mboxAddress));
+
+    *pBMICmdCredits = 0;
+    timeout = BMI_COMMUNICATION_TIMEOUT;
+
+    while(timeout-- && !(*pBMICmdCredits)) {
+        /* Read the counter register to get the command credits */
+        address = COUNT_DEC_ADDRESS + (HTC_MAILBOX_NUM_MAX + ENDPOINT1) * 4;
+        /* hit the credit counter with a 4-byte access, the first byte read will hit the counter and cause
+         * a decrement, while the remaining 3 bytes has no effect.  The rationale behind this is to
+         * make all HIF accesses 4-byte aligned */
+        status = HIFReadWrite(device, address, (A_UINT8 *)pBMICmdCredits, 4,
+            HIF_RD_SYNC_BYTE_INC, NULL);
+        if (status != A_OK) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to decrement the command credit count register\n"));
+            return A_ERROR;
+        }
+        /* the counter is only 8=bits, ignore anything in the upper 3 bytes */
+        (*pBMICmdCredits) &= 0xFF;
+    }
+
+    if (*pBMICmdCredits) {
+        address = mboxAddress[ENDPOINT1];
+        status = HIFReadWrite(device, address, buffer, length,
+            HIF_WR_SYNC_BYTE_INC, NULL);
+        if (status != A_OK) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to send the BMI data to the device\n"));
+            return A_ERROR;
+        }
+    } else {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("BMI Communication timeout - bmiBufferSend\n"));
+        return A_ERROR;
+    }
+
+    return status;
+}
+
+A_STATUS
+bmiBufferReceive(HIF_DEVICE *device,
+                 A_UCHAR *buffer,
+                 A_UINT32 length,
+                 A_BOOL want_timeout)
+{
+    A_STATUS status;
+    A_UINT32 address;
+    A_UINT32 mboxAddress[HTC_MAILBOX_NUM_MAX];
+    HIF_PENDING_EVENTS_INFO     hifPendingEvents;
+    static HIF_PENDING_EVENTS_FUNC getPendingEventsFunc = NULL;
+    
+    if (!pendingEventsFuncCheck) {
+            /* see if the HIF layer implements an alternative function to get pending events
+             * do this only once! */
+        HIFConfigureDevice(device,
+                           HIF_DEVICE_GET_PENDING_EVENTS_FUNC,
+                           &getPendingEventsFunc,
+                           sizeof(getPendingEventsFunc));
+        pendingEventsFuncCheck = TRUE;
+    }
+                       
+    HIFConfigureDevice(device, HIF_DEVICE_GET_MBOX_ADDR,
+                       &mboxAddress[0], sizeof(mboxAddress));
+
+    /*
+     * During normal bootup, small reads may be required.
+     * Rather than issue an HIF Read and then wait as the Target
+     * adds successive bytes to the FIFO, we wait here until
+     * we know that response data is available.
+     *
+     * This allows us to cleanly timeout on an unexpected
+     * Target failure rather than risk problems at the HIF level.  In
+     * particular, this avoids SDIO timeouts and possibly garbage
+     * data on some host controllers.  And on an interconnect
+     * such as Compact Flash (as well as some SDIO masters) which
+     * does not provide any indication on data timeout, it avoids
+     * a potential hang or garbage response.
+     *
+     * Synchronization is more difficult for reads larger than the
+     * size of the MBOX FIFO (128B), because the Target is unable
+     * to push the 129th byte of data until AFTER the Host posts an
+     * HIF Read and removes some FIFO data.  So for large reads the
+     * Host proceeds to post an HIF Read BEFORE all the data is
+     * actually available to read.  Fortunately, large BMI reads do
+     * not occur in practice -- they're supported for debug/development.
+     *
+     * So Host/Target BMI synchronization is divided into these cases:
+     *  CASE 1: length < 4
+     *        Should not happen
+     *
+     *  CASE 2: 4 <= length <= 128
+     *        Wait for first 4 bytes to be in FIFO
+     *        If CONSERVATIVE_BMI_READ is enabled, also wait for
+     *        a BMI command credit, which indicates that the ENTIRE
+     *        response is available in the the FIFO
+     *
+     *  CASE 3: length > 128
+     *        Wait for the first 4 bytes to be in FIFO
+     *
+     * For most uses, a small timeout should be sufficient and we will
+     * usually see a response quickly; but there may be some unusual
+     * (debug) cases of BMI_EXECUTE where we want an larger timeout.
+     * For now, we use an unbounded busy loop while waiting for
+     * BMI_EXECUTE.
+     *
+     * If BMI_EXECUTE ever needs to support longer-latency execution,
+     * especially in production, this code needs to be enhanced to sleep
+     * and yield.  Also note that BMI_COMMUNICATION_TIMEOUT is currently
+     * a function of Host processor speed.
+     */
+    if (length >= 4) { /* NB: Currently, always true */
+        /*
+         * NB: word_available is declared static for esoteric reasons
+         * having to do with protection on some OSes.
+         */
+        static A_UINT32 word_available;
+        A_UINT32 timeout;
+
+        word_available = 0;
+        timeout = BMI_COMMUNICATION_TIMEOUT;
+        while((!want_timeout || timeout--) && !word_available) {
+            
+            if (getPendingEventsFunc != NULL) {
+                status = getPendingEventsFunc(device,
+                                              &hifPendingEvents,
+                                              NULL);
+                if (status != A_OK) {
+                    AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BMI: Failed to get pending events \n"));
+                    break;
+                }
+  
+                if (hifPendingEvents.AvailableRecvBytes >= sizeof(A_UINT32)) {
+                    word_available = 1;    
+                }
+                continue;    
+            }
+            
+            status = HIFReadWrite(device, RX_LOOKAHEAD_VALID_ADDRESS, (A_UINT8 *)&word_available,
+                sizeof(word_available), HIF_RD_SYNC_BYTE_INC, NULL);
+            if (status != A_OK) {
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read RX_LOOKAHEAD_VALID register\n"));
+                return A_ERROR;
+            }
+            /* We did a 4-byte read to the same register; all we really want is one bit */ 
+            word_available &= (1 << ENDPOINT1);
+        }
+
+        if (!word_available) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("BMI Communication timeout - bmiBufferReceive FIFO empty\n"));
+            return A_ERROR;
+        }
+    }
+
+#define CONSERVATIVE_BMI_READ 0
+#if CONSERVATIVE_BMI_READ
+    /*
+     * This is an extra-conservative CREDIT check.  It guarantees
+     * that ALL data is available in the FIFO before we start to
+     * read from the interconnect.
+     *
+     * This credit check is useless when firmware chooses to
+     * allow multiple outstanding BMI Command Credits, since the next
+     * credit will already be present.  To restrict the Target to one
+     * BMI Command Credit, see HI_OPTION_BMI_CRED_LIMIT.
+     *
+     * And for large reads (when HI_OPTION_BMI_CRED_LIMIT is set)
+     * we cannot wait for the next credit because the Target's FIFO
+     * will not hold the entire response.  So we need the Host to
+     * start to empty the FIFO sooner.  (And again, large reads are
+     * not used in practice; they are for debug/development only.)
+     *
+     * For a more conservative Host implementation (which would be
+     * safer for a Compact Flash interconnect):
+     *   Set CONSERVATIVE_BMI_READ (above) to 1
+     *   Set HI_OPTION_BMI_CRED_LIMIT and
+     *   reduce BMI_DATASZ_MAX to 32 or 64
+     */
+    if ((length > 4) && (length < 128)) { /* check against MBOX FIFO size */
+        A_UINT32 timeout;
+
+        *pBMICmdCredits = 0;
+        timeout = BMI_COMMUNICATION_TIMEOUT;
+        while((!want_timeout || timeout--) && !(*pBMICmdCredits) {
+            /* Read the counter register to get the command credits */
+            address = COUNT_ADDRESS + (HTC_MAILBOX_NUM_MAX + ENDPOINT1) * 1;
+            /* read the counter using a 4-byte read.  Since the counter is NOT auto-decrementing,
+             * we can read this counter multiple times using a non-incrementing address mode.
+             * The rationale here is to make all HIF accesses a multiple of 4 bytes */
+            status = HIFReadWrite(device, address, (A_UINT8 *)pBMICmdCredits, sizeof(*pBMICmdCredits),
+                HIF_RD_SYNC_BYTE_FIX, NULL);
+            if (status != A_OK) {
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read the command credit count register\n"));
+                return A_ERROR;
+            }
+                /* we did a 4-byte read to the same count register so mask off upper bytes */
+            (*pBMICmdCredits) &= 0xFF;
+        }
+
+        if (!(*pBMICmdCredits)) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("BMI Communication timeout- bmiBufferReceive no credit\n"));
+            return A_ERROR;
+        }
+    }
+#endif
+
+    address = mboxAddress[ENDPOINT1];
+    status = HIFReadWrite(device, address, buffer, length, HIF_RD_SYNC_BYTE_INC, NULL);
+    if (status != A_OK) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read the BMI data from the device\n"));
+        return A_ERROR;
+    }
+
+    return A_OK;
+}
+
+A_STATUS
+BMIFastDownload(HIF_DEVICE *device, A_UINT32 address, A_UCHAR *buffer, A_UINT32 length)
+{
+    A_STATUS status = A_ERROR;
+    A_UINT32  lastWord = 0;
+    A_UINT32  lastWordOffset = length & ~0x3;
+    A_UINT32  unalignedBytes = length & 0x3;
+
+    status = BMILZStreamStart (device, address);
+    if (A_FAILED(status)) {
+            return A_ERROR;
+    }
+
+    if (unalignedBytes) {
+            /* copy the last word into a zero padded buffer */
+        A_MEMCPY(&lastWord, &buffer[lastWordOffset], unalignedBytes);
+    }
+
+    status = BMILZData(device, buffer, lastWordOffset);
+
+    if (A_FAILED(status)) {
+        return A_ERROR;
+    }
+
+    if (unalignedBytes) {
+        status = BMILZData(device, (A_UINT8 *)&lastWord, 4);
+    }
+
+    if (A_SUCCESS(status)) {
+        //
+        // Close compressed stream and open a new (fake) one.  This serves mainly to flush Target caches.
+        //
+        status = BMILZStreamStart (device, 0x00);
+        if (A_FAILED(status)) {
+           return A_ERROR;
+        }
+    }
+	return status;
+}
+
+A_STATUS
+BMIRawWrite(HIF_DEVICE *device, A_UCHAR *buffer, A_UINT32 length)
+{
+    return bmiBufferSend(device, buffer, length);
+}
+
+A_STATUS
+BMIRawRead(HIF_DEVICE *device, A_UCHAR *buffer, A_UINT32 length, A_BOOL want_timeout)
+{
+    return bmiBufferReceive(device, buffer, length, want_timeout);
+}
diff --git a/drivers/net/ath6kl/hif/common/hif_sdio_common.h b/drivers/net/ath6kl/hif/common/hif_sdio_common.h
new file mode 100644
index 00000000000..0f4e913cb13
--- /dev/null
+++ b/drivers/net/ath6kl/hif/common/hif_sdio_common.h
@@ -0,0 +1,87 @@
+//------------------------------------------------------------------------------
+// Copyright (c) 2009-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// common header file for HIF modules designed for SDIO
+//
+// Author(s): ="Atheros"
+//==============================================================================
+
+#ifndef HIF_SDIO_COMMON_H_
+#define HIF_SDIO_COMMON_H_
+
+    /* SDIO manufacturer ID and Codes */
+#define MANUFACTURER_ID_AR6002_BASE        0x200
+#define MANUFACTURER_ID_AR6003_BASE        0x300
+#define MANUFACTURER_ID_AR6K_BASE_MASK     0xFF00
+#define FUNCTION_CLASS                     0x0
+#define MANUFACTURER_CODE                  0x271    /* Atheros */
+
+    /* Mailbox address in SDIO address space */
+#define HIF_MBOX_BASE_ADDR                 0x800
+#define HIF_MBOX_WIDTH                     0x800
+#define HIF_MBOX_START_ADDR(mbox)               \
+   ( HIF_MBOX_BASE_ADDR + mbox * HIF_MBOX_WIDTH)
+
+#define HIF_MBOX_END_ADDR(mbox)                 \
+    (HIF_MBOX_START_ADDR(mbox) + HIF_MBOX_WIDTH - 1)
+
+    /* extended MBOX address for larger MBOX writes to MBOX 0*/
+#define HIF_MBOX0_EXTENDED_BASE_ADDR       0x2800
+#define HIF_MBOX0_EXTENDED_WIDTH_AR6002    (6*1024)           
+#define HIF_MBOX0_EXTENDED_WIDTH_AR6003    (18*1024)   
+
+    /* version 1 of the chip has only a 12K extended mbox range */
+#define HIF_MBOX0_EXTENDED_BASE_ADDR_AR6003_V1  0x4000
+#define HIF_MBOX0_EXTENDED_WIDTH_AR6003_V1      (12*1024)  
+
+    /* GMBOX addresses */
+#define HIF_GMBOX_BASE_ADDR                0x7000
+#define HIF_GMBOX_WIDTH                    0x4000
+
+    /* for SDIO we recommend a 128-byte block size */
+#define HIF_DEFAULT_IO_BLOCK_SIZE          128
+
+    /* set extended MBOX window information for SDIO interconnects */
+static INLINE void SetExtendedMboxWindowInfo(A_UINT16 Manfid, HIF_DEVICE_MBOX_INFO *pInfo)
+{
+    switch (Manfid & MANUFACTURER_ID_AR6K_BASE_MASK) {                   
+        case MANUFACTURER_ID_AR6002_BASE :
+                /* MBOX 0 has an extended range */
+            pInfo->MboxProp[0].ExtendedAddress = HIF_MBOX0_EXTENDED_BASE_ADDR;             
+            pInfo->MboxProp[0].ExtendedSize = HIF_MBOX0_EXTENDED_WIDTH_AR6002;
+            break;
+        case MANUFACTURER_ID_AR6003_BASE :
+                /* MBOX 0 has an extended range */
+            pInfo->MboxProp[0].ExtendedAddress = HIF_MBOX0_EXTENDED_BASE_ADDR_AR6003_V1;             
+            pInfo->MboxProp[0].ExtendedSize = HIF_MBOX0_EXTENDED_WIDTH_AR6003_V1;
+            pInfo->GMboxAddress = HIF_GMBOX_BASE_ADDR;
+            pInfo->GMboxSize = HIF_GMBOX_WIDTH;
+            break;
+        default:
+            A_ASSERT(FALSE);
+            break;
+    }
+}
+             
+/* special CCCR (func 0) registers */
+
+#define CCCR_SDIO_IRQ_MODE_REG         0xF0        /* interrupt mode register */
+#define SDIO_IRQ_MODE_ASYNC_4BIT_IRQ   (1 << 0)    /* mode to enable special 4-bit interrupt assertion without clock*/ 
+                        
+#endif /*HIF_SDIO_COMMON_H_*/
diff --git a/drivers/net/ath6kl/hif/sdio/linux_sdio/include/hif_internal.h b/drivers/net/ath6kl/hif/sdio/linux_sdio/include/hif_internal.h
new file mode 100644
index 00000000000..857f35f36ca
--- /dev/null
+++ b/drivers/net/ath6kl/hif/sdio/linux_sdio/include/hif_internal.h
@@ -0,0 +1,134 @@
+//------------------------------------------------------------------------------
+// <copyright file="hif_internal.h" company="Atheros">
+//    Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// internal header file for hif layer
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _HIF_INTERNAL_H_
+#define _HIF_INTERNAL_H_
+
+#include "a_config.h"
+#include "athdefs.h"
+#include "a_types.h"
+#include "a_osapi.h"
+#include "hif.h"
+#include "../../../common/hif_sdio_common.h"
+#include <linux/scatterlist.h>
+#define HIF_LINUX_MMC_SCATTER_SUPPORT
+
+#define BUS_REQUEST_MAX_NUM                64
+
+#define SDIO_CLOCK_FREQUENCY_DEFAULT       25000000
+#define SDWLAN_ENABLE_DISABLE_TIMEOUT      20
+#define FLAGS_CARD_ENAB                    0x02
+#define FLAGS_CARD_IRQ_UNMSK               0x04
+
+#define HIF_MBOX_BLOCK_SIZE                HIF_DEFAULT_IO_BLOCK_SIZE
+#define HIF_MBOX0_BLOCK_SIZE               1
+#define HIF_MBOX1_BLOCK_SIZE               HIF_MBOX_BLOCK_SIZE
+#define HIF_MBOX2_BLOCK_SIZE               HIF_MBOX_BLOCK_SIZE
+#define HIF_MBOX3_BLOCK_SIZE               HIF_MBOX_BLOCK_SIZE
+
+struct _HIF_SCATTER_REQ_PRIV;
+
+typedef struct bus_request {
+    struct bus_request *next;       /* link list of available requests */
+    struct bus_request *inusenext;  /* link list of in use requests */
+    struct semaphore sem_req;
+    A_UINT32 address;               /* request data */
+    A_UCHAR *buffer;
+    A_UINT32 length;
+    A_UINT32 request;
+    void *context;
+    A_STATUS status;
+    struct _HIF_SCATTER_REQ_PRIV *pScatterReq;      /* this request is a scatter request */
+} BUS_REQUEST;
+
+struct hif_device {
+    struct sdio_func *func;
+    spinlock_t asynclock;
+    struct task_struct* async_task;             /* task to handle async commands */
+    struct semaphore sem_async;                 /* wake up for async task */
+    int    async_shutdown;                      /* stop the async task */
+    struct completion async_completion;          /* thread completion */
+    BUS_REQUEST   *asyncreq;                    /* request for async tasklet */
+    BUS_REQUEST *taskreq;                       /*  async tasklet data */
+    spinlock_t lock;
+    BUS_REQUEST *s_busRequestFreeQueue;         /* free list */
+    BUS_REQUEST busRequest[BUS_REQUEST_MAX_NUM]; /* available bus requests */
+    void     *claimedContext;
+    HTC_CALLBACKS htcCallbacks;
+    A_UINT8     *dma_buffer;
+    DL_LIST      ScatterReqHead;                /* scatter request list head */
+    A_BOOL       scatter_enabled;               /* scatter enabled flag */
+    A_BOOL   is_suspend;
+    A_BOOL   is_disabled;
+    atomic_t   irqHandling;
+    HIF_DEVICE_POWER_CHANGE_TYPE powerConfig;
+    const struct sdio_device_id *id;
+};
+
+#define HIF_DMA_BUFFER_SIZE (32 * 1024)
+#define CMD53_FIXED_ADDRESS 1
+#define CMD53_INCR_ADDRESS  2
+
+BUS_REQUEST *hifAllocateBusRequest(HIF_DEVICE *device);
+void hifFreeBusRequest(HIF_DEVICE *device, BUS_REQUEST *busrequest);
+void AddToAsyncList(HIF_DEVICE *device, BUS_REQUEST *busrequest);
+
+#ifdef HIF_LINUX_MMC_SCATTER_SUPPORT
+
+#define MAX_SCATTER_REQUESTS             4
+#define MAX_SCATTER_ENTRIES_PER_REQ      16
+#define MAX_SCATTER_REQ_TRANSFER_SIZE    32*1024
+
+typedef struct _HIF_SCATTER_REQ_PRIV {
+    HIF_SCATTER_REQ     *pHifScatterReq;  /* HIF scatter request with allocated entries */   
+    HIF_DEVICE          *device;          /* this device */
+    BUS_REQUEST         *busrequest;      /* request associated with request */
+        /* scatter list for linux */    
+    struct scatterlist  sgentries[MAX_SCATTER_ENTRIES_PER_REQ];   
+} HIF_SCATTER_REQ_PRIV;
+
+#define ATH_DEBUG_SCATTER  ATH_DEBUG_MAKE_MODULE_MASK(0)
+
+A_STATUS SetupHIFScatterSupport(HIF_DEVICE *device, HIF_DEVICE_SCATTER_SUPPORT_INFO *pInfo);
+void CleanupHIFScatterResources(HIF_DEVICE *device);
+A_STATUS DoHifReadWriteScatter(HIF_DEVICE *device, BUS_REQUEST *busrequest);
+
+#else  // HIF_LINUX_MMC_SCATTER_SUPPORT
+
+static inline A_STATUS SetupHIFScatterSupport(HIF_DEVICE *device, HIF_DEVICE_SCATTER_SUPPORT_INFO *pInfo) 
+{
+    return A_ENOTSUP;
+}
+
+static inline A_STATUS DoHifReadWriteScatter(HIF_DEVICE *device, BUS_REQUEST *busrequest) 
+{
+    return A_ENOTSUP;
+}
+
+#define CleanupHIFScatterResources(d) { }
+
+#endif // HIF_LINUX_MMC_SCATTER_SUPPORT
+
+#endif // _HIF_INTERNAL_H_
+
diff --git a/drivers/net/ath6kl/hif/sdio/linux_sdio/src/hif.c b/drivers/net/ath6kl/hif/sdio/linux_sdio/src/hif.c
new file mode 100644
index 00000000000..e96662b84ed
--- /dev/null
+++ b/drivers/net/ath6kl/hif/sdio/linux_sdio/src/hif.c
@@ -0,0 +1,1298 @@
+//------------------------------------------------------------------------------
+// <copyright file="hif.c" company="Atheros">
+//    Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// HIF layer reference implementation for Linux Native MMC stack
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#include <linux/mmc/card.h>
+#include <linux/mmc/mmc.h>
+#include <linux/mmc/host.h>
+#include <linux/mmc/sdio_func.h>
+#include <linux/mmc/sdio_ids.h>
+#include <linux/mmc/sdio.h>
+#include <linux/mmc/sd.h>
+#include <linux/kthread.h>
+
+/* by default setup a bounce buffer for the data packets, if the underlying host controller driver
+   does not use DMA you may be able to skip this step and save the memory allocation and transfer time */
+#define HIF_USE_DMA_BOUNCE_BUFFER 1
+#include "hif_internal.h"
+#define ATH_MODULE_NAME hif
+#include "a_debug.h"
+#include "AR6002/hw2.0/hw/mbox_host_reg.h"
+
+#if HIF_USE_DMA_BOUNCE_BUFFER
+/* macro to check if DMA buffer is WORD-aligned and DMA-able.  Most host controllers assume the
+ * buffer is DMA'able and will bug-check otherwise (i.e. buffers on the stack).  
+ * virt_addr_valid check fails on stack memory.  
+ */
+#define BUFFER_NEEDS_BOUNCE(buffer)  (((unsigned long)(buffer) & 0x3) || !virt_addr_valid((buffer)))
+#else
+#define BUFFER_NEEDS_BOUNCE(buffer)   (FALSE)
+#endif
+
+/* ATHENV */
+#if defined(CONFIG_PM)
+#define dev_to_sdio_func(d)	container_of(d, struct sdio_func, dev)
+#define to_sdio_driver(d)      container_of(d, struct sdio_driver, drv)
+static int hifDeviceSuspend(struct device *dev);
+static int hifDeviceResume(struct device *dev);
+#endif /* CONFIG_PM */
+static int hifDeviceInserted(struct sdio_func *func, const struct sdio_device_id *id);
+static void hifDeviceRemoved(struct sdio_func *func);
+static HIF_DEVICE *addHifDevice(struct sdio_func *func);
+static HIF_DEVICE *getHifDevice(struct sdio_func *func);
+static void delHifDevice(HIF_DEVICE * device);
+static int Func0_CMD52WriteByte(struct mmc_card *card, unsigned int address, unsigned char byte);
+static int Func0_CMD52ReadByte(struct mmc_card *card, unsigned int address, unsigned char *byte);
+
+int reset_sdio_on_unload = 0;
+module_param(reset_sdio_on_unload, int, 0644);
+
+extern A_UINT32 nohifscattersupport;
+
+
+/* ------ Static Variables ------ */
+static const struct sdio_device_id ar6k_id_table[] = {
+    {  SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6002_BASE | 0x0))  },
+    {  SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6002_BASE | 0x1))  },
+    {  SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6003_BASE | 0x0))  },
+    {  SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6003_BASE | 0x1))  },
+    { /* null */                                         },
+};
+MODULE_DEVICE_TABLE(sdio, ar6k_id_table);
+
+static struct sdio_driver ar6k_driver = {
+	.name = "ar6k_wlan",
+	.id_table = ar6k_id_table,
+	.probe = hifDeviceInserted,
+	.remove = hifDeviceRemoved,
+};
+
+#if defined(CONFIG_PM)
+/* New suspend/resume based on linux-2.6.32
+ * Need to patch linux-2.6.32 with mmc2.6.32_suspend.patch
+ * Need to patch with msmsdcc2.6.29_suspend.patch for msm_sdcc host
+     */
+static struct dev_pm_ops ar6k_device_pm_ops = {
+	.suspend = hifDeviceSuspend,
+	.resume = hifDeviceResume,
+};
+#endif /* CONFIG_PM */
+
+/* make sure we only unregister when registered. */
+static int registered = 0;
+
+OSDRV_CALLBACKS osdrvCallbacks;
+extern A_UINT32 onebitmode;
+extern A_UINT32 busspeedlow;
+extern A_UINT32 debughif;
+
+static void ResetAllCards(void);
+static A_STATUS hifDisableFunc(HIF_DEVICE *device, struct sdio_func *func);
+static A_STATUS hifEnableFunc(HIF_DEVICE *device, struct sdio_func *func);
+
+#ifdef DEBUG
+
+ATH_DEBUG_INSTANTIATE_MODULE_VAR(hif,
+                                 "hif",
+                                 "(Linux MMC) Host Interconnect Framework",
+                                 ATH_DEBUG_MASK_DEFAULTS,
+                                 0,
+                                 NULL);
+                                 
+#endif
+
+
+/* ------ Functions ------ */
+A_STATUS HIFInit(OSDRV_CALLBACKS *callbacks)
+{
+    int status;
+    AR_DEBUG_ASSERT(callbacks != NULL);
+
+    A_REGISTER_MODULE_DEBUG_INFO(hif);
+
+    /* store the callback handlers */
+    osdrvCallbacks = *callbacks;
+
+    /* Register with bus driver core */
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: HIFInit registering\n"));
+    registered = 1;
+#if defined(CONFIG_PM)
+    if (callbacks->deviceSuspendHandler && callbacks->deviceResumeHandler) {
+        ar6k_driver.drv.pm = &ar6k_device_pm_ops;
+    }
+#endif /* CONFIG_PM */
+    status = sdio_register_driver(&ar6k_driver);
+    AR_DEBUG_ASSERT(status==0);
+
+    if (status != 0) {
+        return A_ERROR;
+    }
+
+    return A_OK;
+
+}
+
+static A_STATUS
+__HIFReadWrite(HIF_DEVICE *device,
+             A_UINT32 address,
+             A_UCHAR *buffer,
+             A_UINT32 length,
+             A_UINT32 request,
+             void *context)
+{
+    A_UINT8 opcode;
+    A_STATUS    status = A_OK;
+    int     ret;
+    A_UINT8 *tbuffer;
+    A_BOOL   bounced = FALSE;
+
+    AR_DEBUG_ASSERT(device != NULL);
+    AR_DEBUG_ASSERT(device->func != NULL);
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: Device: 0x%p, buffer:0x%p (addr:0x%X)\n", 
+                    device, buffer, address));
+
+    do {
+        if (request & HIF_EXTENDED_IO) {
+            //AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: Command type: CMD53\n"));
+        } else {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
+                            ("AR6000: Invalid command type: 0x%08x\n", request));
+            status = A_EINVAL;
+            break;
+        }
+
+        if (request & HIF_BLOCK_BASIS) {
+            /* round to whole block length size */
+            length = (length / HIF_MBOX_BLOCK_SIZE) * HIF_MBOX_BLOCK_SIZE;
+            AR_DEBUG_PRINTF(ATH_DEBUG_TRACE,
+                            ("AR6000: Block mode (BlockLen: %d)\n",
+                            length));
+        } else if (request & HIF_BYTE_BASIS) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_TRACE,
+                            ("AR6000: Byte mode (BlockLen: %d)\n",
+                            length));
+        } else {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
+                            ("AR6000: Invalid data mode: 0x%08x\n", request));
+            status = A_EINVAL;
+            break;
+        }
+
+#if 0
+        /* useful for checking register accesses */
+        if (length & 0x3) {
+            A_PRINTF(KERN_ALERT"AR6000: HIF (%s) is not a multiple of 4 bytes, addr:0x%X, len:%d\n",
+                                request & HIF_WRITE ? "write":"read", address, length);
+        }
+#endif
+
+        if (request & HIF_WRITE) {
+            if ((address >= HIF_MBOX_START_ADDR(0)) &&
+                (address <= HIF_MBOX_END_ADDR(3)))
+            {
+    
+                AR_DEBUG_ASSERT(length <= HIF_MBOX_WIDTH);
+    
+                /*
+                 * Mailbox write. Adjust the address so that the last byte
+                 * falls on the EOM address.
+                 */
+                address += (HIF_MBOX_WIDTH - length);
+            }
+        }
+
+        if (request & HIF_FIXED_ADDRESS) {
+            opcode = CMD53_FIXED_ADDRESS;
+            AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: Address mode: Fixed 0x%X\n", address));
+        } else if (request & HIF_INCREMENTAL_ADDRESS) {
+            opcode = CMD53_INCR_ADDRESS;
+            AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: Address mode: Incremental 0x%X\n", address));
+        } else {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
+                            ("AR6000: Invalid address mode: 0x%08x\n", request));
+            status = A_EINVAL;
+            break;
+        }
+
+        if (request & HIF_WRITE) {
+#if HIF_USE_DMA_BOUNCE_BUFFER
+            if (BUFFER_NEEDS_BOUNCE(buffer)) {
+                AR_DEBUG_ASSERT(device->dma_buffer != NULL);
+                tbuffer = device->dma_buffer;
+                    /* copy the write data to the dma buffer */
+                AR_DEBUG_ASSERT(length <= HIF_DMA_BUFFER_SIZE);
+                memcpy(tbuffer, buffer, length);
+                bounced = TRUE;
+            } else {
+                tbuffer = buffer;    
+            }
+#else
+	        tbuffer = buffer;
+#endif
+            if (opcode == CMD53_FIXED_ADDRESS) {
+                ret = sdio_writesb(device->func, address, tbuffer, length);
+                AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: writesb ret=%d address: 0x%X, len: %d, 0x%X\n",
+						  ret, address, length, *(int *)tbuffer));
+            } else {
+                ret = sdio_memcpy_toio(device->func, address, tbuffer, length);
+                AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: writeio ret=%d address: 0x%X, len: %d, 0x%X\n",
+						  ret, address, length, *(int *)tbuffer));
+            }
+        } else if (request & HIF_READ) {
+#if HIF_USE_DMA_BOUNCE_BUFFER
+            if (BUFFER_NEEDS_BOUNCE(buffer)) {
+                AR_DEBUG_ASSERT(device->dma_buffer != NULL);
+                AR_DEBUG_ASSERT(length <= HIF_DMA_BUFFER_SIZE);
+                tbuffer = device->dma_buffer;
+                bounced = TRUE;
+            } else {
+                tbuffer = buffer;    
+            }
+#else
+            tbuffer = buffer;
+#endif
+            if (opcode == CMD53_FIXED_ADDRESS) {
+                ret = sdio_readsb(device->func, tbuffer, address, length);
+                AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: readsb ret=%d address: 0x%X, len: %d, 0x%X\n",
+						  ret, address, length, *(int *)tbuffer));
+            } else {
+                ret = sdio_memcpy_fromio(device->func, tbuffer, address, length);
+                AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: readio ret=%d address: 0x%X, len: %d, 0x%X\n",
+						  ret, address, length, *(int *)tbuffer));
+            }
+#if HIF_USE_DMA_BOUNCE_BUFFER
+            if (bounced) {
+    	           /* copy the read data from the dma buffer */
+                memcpy(buffer, tbuffer, length);
+            }
+#endif
+        } else {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
+                            ("AR6000: Invalid direction: 0x%08x\n", request));
+            status = A_EINVAL;
+            break;
+        }
+
+        if (ret) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
+                            ("AR6000: SDIO bus operation failed! MMC stack returned : %d \n", ret));
+            status = A_ERROR;
+        }
+    } while (FALSE);
+
+    return status;
+}
+
+void AddToAsyncList(HIF_DEVICE *device, BUS_REQUEST *busrequest)
+{
+    unsigned long flags;
+    BUS_REQUEST *async;
+    BUS_REQUEST *active;
+    
+    spin_lock_irqsave(&device->asynclock, flags);
+    active = device->asyncreq;
+    if (active == NULL) {
+        device->asyncreq = busrequest;
+        device->asyncreq->inusenext = NULL;
+    } else {
+        for (async = device->asyncreq;
+             async != NULL;
+             async = async->inusenext) {
+             active =  async;
+        }
+        active->inusenext = busrequest;
+        busrequest->inusenext = NULL;
+    }
+    spin_unlock_irqrestore(&device->asynclock, flags);
+}
+
+
+/* queue a read/write request */
+A_STATUS
+HIFReadWrite(HIF_DEVICE *device,
+             A_UINT32 address,
+             A_UCHAR *buffer,
+             A_UINT32 length,
+             A_UINT32 request,
+             void *context)
+{
+    A_STATUS    status = A_OK;
+    BUS_REQUEST *busrequest;
+
+
+    AR_DEBUG_ASSERT(device != NULL);
+    AR_DEBUG_ASSERT(device->func != NULL);
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: Device: %p addr:0x%X\n", device,address));
+
+    do {            
+        if ((request & HIF_ASYNCHRONOUS) || (request & HIF_SYNCHRONOUS)){
+            /* serialize all requests through the async thread */
+            AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: Execution mode: %s\n", 
+                        (request & HIF_ASYNCHRONOUS)?"Async":"Synch"));
+            busrequest = hifAllocateBusRequest(device);
+            if (busrequest == NULL) {
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, 
+                    ("AR6000: no async bus requests available (%s, addr:0x%X, len:%d) \n", 
+                        request & HIF_READ ? "READ":"WRITE", address, length));
+                return A_ERROR;
+            }
+            busrequest->address = address;
+            busrequest->buffer = buffer;
+            busrequest->length = length;
+            busrequest->request = request;
+            busrequest->context = context;
+            
+            AddToAsyncList(device, busrequest);
+            
+            if (request & HIF_SYNCHRONOUS) {
+                AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: queued sync req: 0x%lX\n", (unsigned long)busrequest));
+
+                /* wait for completion */
+                up(&device->sem_async);
+                if (down_interruptible(&busrequest->sem_req) != 0) {
+                    /* interrupted, exit */
+                    return A_ERROR;
+                } else {
+                    A_STATUS status = busrequest->status;
+                    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: sync return freeing 0x%lX: 0x%X\n", 
+						      (unsigned long)busrequest, busrequest->status));
+                    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: freeing req: 0x%X\n", (unsigned int)request));
+                    hifFreeBusRequest(device, busrequest);
+                    return status;
+                }
+            } else {
+                AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: queued async req: 0x%lX\n", (unsigned long)busrequest));
+                up(&device->sem_async);
+                return A_PENDING;
+            }
+        } else {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
+                            ("AR6000: Invalid execution mode: 0x%08x\n", (unsigned int)request));
+            status = A_EINVAL;
+            break;
+        }
+    } while(0);
+
+    return status;
+}
+/* thread to serialize all requests, both sync and async */
+static int async_task(void *param)
+ {
+    HIF_DEVICE *device;
+    BUS_REQUEST *request;
+    A_STATUS status;
+    unsigned long flags;
+
+    device = (HIF_DEVICE *)param;
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: async task\n"));
+    set_current_state(TASK_INTERRUPTIBLE);
+    while(!device->async_shutdown) {
+        /* wait for work */
+        if (down_interruptible(&device->sem_async) != 0) {
+            /* interrupted, exit */
+            AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: async task interrupted\n"));
+            break;
+        }
+        if (device->async_shutdown) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: async task stopping\n"));
+            break;
+        }
+        /* we want to hold the host over multiple cmds if possible, but holding the host blocks card interrupts */
+        sdio_claim_host(device->func);
+        spin_lock_irqsave(&device->asynclock, flags);
+        /* pull the request to work on */
+        while (device->asyncreq != NULL) {
+            request = device->asyncreq;
+            if (request->inusenext != NULL) {
+                device->asyncreq = request->inusenext;
+            } else {
+                device->asyncreq = NULL;
+            }
+            spin_unlock_irqrestore(&device->asynclock, flags);
+            AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: async_task processing req: 0x%lX\n", (unsigned long)request));
+            
+            if (request->pScatterReq != NULL) {
+                A_ASSERT(device->scatter_enabled);
+                    /* this is a queued scatter request, pass the request to scatter routine which
+                     * executes it synchronously, note, no need to free the request since scatter requests
+                     * are maintained on a separate list */
+                status = DoHifReadWriteScatter(device,request);
+            } else {                
+                    /* call HIFReadWrite in sync mode to do the work */
+                status = __HIFReadWrite(device, request->address, request->buffer,
+                                      request->length, request->request & ~HIF_SYNCHRONOUS, NULL);
+                if (request->request & HIF_ASYNCHRONOUS) {
+                    void *context = request->context;
+                    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: async_task freeing req: 0x%lX\n", (unsigned long)request));
+                    hifFreeBusRequest(device, request);
+                    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: async_task completion routine req: 0x%lX\n", (unsigned long)request));
+                    device->htcCallbacks.rwCompletionHandler(context, status);
+                } else {
+                    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: async_task upping req: 0x%lX\n", (unsigned long)request));
+                    request->status = status;
+                    up(&request->sem_req);
+                }
+            }
+            spin_lock_irqsave(&device->asynclock, flags);
+        }
+        spin_unlock_irqrestore(&device->asynclock, flags);
+        sdio_release_host(device->func);
+    }
+
+    complete_and_exit(&device->async_completion, 0);
+    return 0;
+}
+
+static A_INT32 IssueSDCommand(HIF_DEVICE *device, A_UINT32 opcode, A_UINT32 arg, A_UINT32 flags, A_UINT32 *resp)
+{
+    struct mmc_command cmd;
+    A_INT32 err;
+    struct mmc_host *host;
+    struct sdio_func *func;
+
+    func = device->func;
+    host = func->card->host;
+
+    memset(&cmd, 0, sizeof(struct mmc_command)); 
+    cmd.opcode = opcode;
+    cmd.arg = arg;
+    cmd.flags = flags;
+    err = mmc_wait_for_cmd(host, &cmd, 3);
+
+    if ((!err) && (resp)) {
+        *resp = cmd.resp[0];
+    }
+
+    return err;
+}
+
+A_STATUS ReinitSDIO(HIF_DEVICE *device)
+{
+    A_INT32 err;
+    struct mmc_host *host;
+    struct mmc_card *card;
+	struct sdio_func *func;
+    A_UINT8  cmd52_resp;
+    A_UINT32 clock;
+
+    func = device->func;
+    card = func->card;
+    host = card->host;
+   
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: +ReinitSDIO \n"));
+    sdio_claim_host(func);
+
+    do {
+        if (!device->is_suspend) {
+            A_UINT32 resp;
+            A_UINT16 rca;
+            A_UINT32 i;
+            int bit = fls(host->ocr_avail) - 1;
+            /* emulate the mmc_power_up(...) */
+            host->ios.vdd = bit;
+            host->ios.chip_select = MMC_CS_DONTCARE;
+            host->ios.bus_mode = MMC_BUSMODE_OPENDRAIN;
+            host->ios.power_mode = MMC_POWER_UP;
+            host->ios.bus_width = MMC_BUS_WIDTH_1;
+            host->ios.timing = MMC_TIMING_LEGACY;
+            host->ops->set_ios(host, &host->ios);
+            /*
+             * This delay should be sufficient to allow the power supply
+             * to reach the minimum voltage.
+             */
+            msleep(2);
+
+            host->ios.clock = host->f_min;
+            host->ios.power_mode = MMC_POWER_ON;
+            host->ops->set_ios(host, &host->ios);
+
+            /*
+             * This delay must be at least 74 clock sizes, or 1 ms, or the
+             * time required to reach a stable voltage.
+             */
+            msleep(2);
+
+            /* Issue CMD0. Goto idle state */
+	        host->ios.chip_select = MMC_CS_HIGH;
+            host->ops->set_ios(host, &host->ios);
+	        msleep(1);
+            err = IssueSDCommand(device, MMC_GO_IDLE_STATE, 0, (MMC_RSP_NONE | MMC_CMD_BC), NULL);
+            host->ios.chip_select = MMC_CS_DONTCARE;
+            host->ops->set_ios(host, &host->ios);
+	        msleep(1);
+            host->use_spi_crc = 0;
+
+            if (err) {
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("ReinitSDIO: CMD0 failed : %d \n",err));    
+                break;
+            }        
+
+            if (!host->ocr) {
+                /* Issue CMD5, arg = 0 */
+                err = IssueSDCommand(device, SD_IO_SEND_OP_COND, 0, (MMC_RSP_R4 | MMC_CMD_BCR), &resp);
+                if (err) {
+                    AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("ReinitSDIO: CMD5 failed : %d \n",err));    
+                    break;
+                }
+                host->ocr = resp;
+            }
+
+            /* Issue CMD5, arg = ocr. Wait till card is ready  */
+            for (i=0;i<100;i++) {
+                err = IssueSDCommand(device, SD_IO_SEND_OP_COND, host->ocr, (MMC_RSP_R4 | MMC_CMD_BCR), &resp);
+                if (err) {
+                    AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("ReinitSDIO: CMD5 failed : %d \n",err));    
+                    break;
+                }
+                if (resp & MMC_CARD_BUSY) {
+                    break;
+                }
+                msleep(10);
+            }
+
+            if ((i == 100) || (err)) {
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("ReinitSDIO: card in not ready : %d %d \n",i,err));    
+                break;
+            }
+
+            /* Issue CMD3, get RCA */
+            err = IssueSDCommand(device, SD_SEND_RELATIVE_ADDR, 0, MMC_RSP_R6 | MMC_CMD_BCR, &resp);
+            if (err) {
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("ReinitSDIO: CMD3 failed : %d \n",err));    
+                break;
+            }
+            rca = resp >> 16;
+            host->ios.bus_mode = MMC_BUSMODE_PUSHPULL;
+            host->ops->set_ios(host, &host->ios);
+
+            /* Issue CMD7, select card  */
+            err = IssueSDCommand(device, MMC_SELECT_CARD, (rca << 16), MMC_RSP_R1 | MMC_CMD_AC, NULL);
+            if (err) {
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("ReinitSDIO: CMD7 failed : %d \n",err));    
+                break;
+            }
+        }
+        
+        /* Enable high speed */
+        if (card->host->caps & MMC_CAP_SD_HIGHSPEED) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("ReinitSDIO: Set high speed mode\n"));    
+            err = Func0_CMD52ReadByte(card, SDIO_CCCR_SPEED, &cmd52_resp);
+            if (err) {
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("ReinitSDIO: CMD52 read to CCCR speed register failed  : %d \n",err));    
+                card->state &= ~MMC_STATE_HIGHSPEED;
+                /* no need to break */
+            } else {
+                err = Func0_CMD52WriteByte(card, SDIO_CCCR_SPEED, (cmd52_resp | SDIO_SPEED_EHS));
+                if (err) {
+                    AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("ReinitSDIO: CMD52 write to CCCR speed register failed  : %d \n",err));    
+                    break;
+                }
+                mmc_card_set_highspeed(card);
+                host->ios.timing = MMC_TIMING_SD_HS;
+                host->ops->set_ios(host, &host->ios);
+            }
+        }
+
+        /* Set clock */
+        if (mmc_card_highspeed(card)) {
+            clock = 50000000;
+        } else {
+            clock = card->cis.max_dtr;
+        }
+        
+        if (clock > host->f_max) {
+            clock = host->f_max;
+        }
+        host->ios.clock = clock;
+        host->ops->set_ios(host, &host->ios);
+        
+
+        if (card->host->caps & MMC_CAP_4_BIT_DATA) {
+            /* CMD52: Set bus width & disable card detect resistor */
+            err = Func0_CMD52WriteByte(card, SDIO_CCCR_IF, SDIO_BUS_CD_DISABLE | SDIO_BUS_WIDTH_4BIT);
+            if (err) {
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("ReinitSDIO: CMD52 to set bus mode failed : %d \n",err));    
+                break;
+            }
+            host->ios.bus_width = MMC_BUS_WIDTH_4;
+            host->ops->set_ios(host, &host->ios);
+        }
+    } while (0);
+
+    sdio_release_host(func);
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: -ReinitSDIO \n"));
+
+    return (err) ? A_ERROR : A_OK;
+}
+
+A_STATUS
+PowerStateChangeNotify(HIF_DEVICE *device, HIF_DEVICE_POWER_CHANGE_TYPE config)
+{
+    A_STATUS status = A_OK;
+#if defined(CONFIG_PM)
+	struct sdio_func *func = device->func;
+    int old_reset_val;
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: +PowerStateChangeNotify %d\n", config));
+    switch (config) {
+       case HIF_DEVICE_POWER_DOWN:
+       case HIF_DEVICE_POWER_CUT:
+            old_reset_val = reset_sdio_on_unload;
+            reset_sdio_on_unload = 1;
+            status = hifDisableFunc(device, func);
+            reset_sdio_on_unload = old_reset_val;
+            if (!device->is_suspend) {
+                struct mmc_host *host = func->card->host;
+	            host->ios.clock = 0;
+	            host->ios.vdd = 0;
+                host->ios.bus_mode = MMC_BUSMODE_OPENDRAIN;
+                host->ios.chip_select = MMC_CS_DONTCARE;
+                host->ios.power_mode = MMC_POWER_OFF;
+                host->ios.bus_width = MMC_BUS_WIDTH_1;
+                host->ios.timing = MMC_TIMING_LEGACY;
+                host->ops->set_ios(host, &host->ios);
+            }
+            break;
+       case HIF_DEVICE_POWER_UP:
+            if (device->powerConfig == HIF_DEVICE_POWER_CUT) {
+                status = ReinitSDIO(device);
+            }
+            if (status == A_OK) {
+                status = hifEnableFunc(device, func);
+            }
+            break;
+    } 
+    device->powerConfig = config;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: -PowerStateChangeNotify\n"));
+#endif
+    return status;
+}
+
+A_STATUS
+HIFConfigureDevice(HIF_DEVICE *device, HIF_DEVICE_CONFIG_OPCODE opcode,
+                   void *config, A_UINT32 configLen)
+{
+    A_UINT32 count;
+    A_STATUS status = A_OK;
+    
+    switch(opcode) {
+        case HIF_DEVICE_GET_MBOX_BLOCK_SIZE:
+            ((A_UINT32 *)config)[0] = HIF_MBOX0_BLOCK_SIZE;
+            ((A_UINT32 *)config)[1] = HIF_MBOX1_BLOCK_SIZE;
+            ((A_UINT32 *)config)[2] = HIF_MBOX2_BLOCK_SIZE;
+            ((A_UINT32 *)config)[3] = HIF_MBOX3_BLOCK_SIZE;
+            break;
+
+        case HIF_DEVICE_GET_MBOX_ADDR:
+            for (count = 0; count < 4; count ++) {
+                ((A_UINT32 *)config)[count] = HIF_MBOX_START_ADDR(count);
+            }
+            
+            if (configLen >= sizeof(HIF_DEVICE_MBOX_INFO)) {    
+                SetExtendedMboxWindowInfo((A_UINT16)device->func->device,
+                                          (HIF_DEVICE_MBOX_INFO *)config);
+            }
+                        
+            break;
+        case HIF_DEVICE_GET_IRQ_PROC_MODE:
+            *((HIF_DEVICE_IRQ_PROCESSING_MODE *)config) = HIF_DEVICE_IRQ_SYNC_ONLY;
+            break;
+       case HIF_CONFIGURE_QUERY_SCATTER_REQUEST_SUPPORT:
+            if (!device->scatter_enabled) {
+                return A_ENOTSUP;    
+            }
+            status = SetupHIFScatterSupport(device, (HIF_DEVICE_SCATTER_SUPPORT_INFO *)config);
+            if (A_FAILED(status)) {
+                device->scatter_enabled = FALSE;           
+            }
+            break; 
+        case HIF_DEVICE_GET_OS_DEVICE:
+                /* pass back a pointer to the SDIO function's "dev" struct */
+            ((HIF_DEVICE_OS_DEVICE_INFO *)config)->pOSDevice = &device->func->dev;
+            break; 
+        case HIF_DEVICE_POWER_STATE_CHANGE:
+            status = PowerStateChangeNotify(device, *(HIF_DEVICE_POWER_CHANGE_TYPE *)config);
+            break;
+        default:
+            AR_DEBUG_PRINTF(ATH_DEBUG_WARN,
+                            ("AR6000: Unsupported configuration opcode: %d\n", opcode));
+            status = A_ERROR;
+    }
+
+    return status;
+}
+
+void
+HIFShutDownDevice(HIF_DEVICE *device)
+{
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: +HIFShutDownDevice\n"));
+    if (device != NULL) {
+        AR_DEBUG_ASSERT(device->func != NULL);
+    } else {
+            /* since we are unloading the driver anyways, reset all cards in case the SDIO card
+             * is externally powered and we are unloading the SDIO stack.  This avoids the problem when
+             * the SDIO stack is reloaded and attempts are made to re-enumerate a card that is already
+             * enumerated */
+        AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: HIFShutDownDevice, resetting\n"));
+        ResetAllCards();
+
+        /* Unregister with bus driver core */
+        if (registered) {
+            registered = 0;
+            AR_DEBUG_PRINTF(ATH_DEBUG_TRACE,
+                            ("AR6000: Unregistering with the bus driver\n"));
+            sdio_unregister_driver(&ar6k_driver);
+            AR_DEBUG_PRINTF(ATH_DEBUG_TRACE,
+                            ("AR6000: Unregistered\n"));
+        }
+    }
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: -HIFShutDownDevice\n"));
+}
+
+static void
+hifIRQHandler(struct sdio_func *func)
+{
+    A_STATUS status;
+    HIF_DEVICE *device;
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: +hifIRQHandler\n"));
+
+    device = getHifDevice(func);
+    atomic_set(&device->irqHandling, 1);
+    /* release the host during ints so we can pick it back up when we process cmds */
+    sdio_release_host(device->func);
+    status = device->htcCallbacks.dsrHandler(device->htcCallbacks.context);
+    sdio_claim_host(device->func);
+    atomic_set(&device->irqHandling, 0);
+    AR_DEBUG_ASSERT(status == A_OK || status == A_ECANCELED);
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: -hifIRQHandler\n"));
+}
+
+/* handle HTC startup via thread*/
+static int startup_task(void *param)
+{
+    HIF_DEVICE *device;
+
+    device = (HIF_DEVICE *)param;
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: call HTC from startup_task\n"));
+        /* start  up inform DRV layer */
+    if ((osdrvCallbacks.deviceInsertedHandler(osdrvCallbacks.context,device)) != A_OK) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: Device rejected\n"));
+    }
+    return 0;
+}
+
+#if defined(CONFIG_PM)
+static int enable_task(void *param)
+{
+    HIF_DEVICE *device;
+    device = (HIF_DEVICE *)param;
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: call  from resume_task\n"));
+
+        /* start  up inform DRV layer */
+    if (device && 
+        device->claimedContext && 
+        osdrvCallbacks.devicePowerChangeHandler &&
+        osdrvCallbacks.devicePowerChangeHandler(device->claimedContext, HIF_DEVICE_POWER_UP) != A_OK) 
+    {
+        AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: Device rejected\n"));
+    }
+
+    return 0;
+}
+#endif
+
+static int hifDeviceInserted(struct sdio_func *func, const struct sdio_device_id *id)
+{
+    int ret;
+    HIF_DEVICE * device;
+    int count;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE,
+		    ("AR6000: hifDeviceInserted, Function: 0x%X, Vendor ID: 0x%X, Device ID: 0x%X, block size: 0x%X/0x%X\n",
+		     func->num, func->vendor, func->device, func->max_blksize, func->cur_blksize));
+
+    addHifDevice(func);
+    device = getHifDevice(func);
+
+    device->id = id;
+    device->is_disabled = TRUE;
+
+    spin_lock_init(&device->lock);
+
+    spin_lock_init(&device->asynclock);
+    
+    DL_LIST_INIT(&device->ScatterReqHead);
+    
+    if (!nohifscattersupport) {
+            /* try to allow scatter operation on all instances,
+             * unless globally overridden */
+        device->scatter_enabled = TRUE;
+    }
+
+    /* Initialize the bus requests to be used later */
+    A_MEMZERO(device->busRequest, sizeof(device->busRequest));
+    for (count = 0; count < BUS_REQUEST_MAX_NUM; count ++) {
+        sema_init(&device->busRequest[count].sem_req, 0);
+        hifFreeBusRequest(device, &device->busRequest[count]);
+    }
+    sema_init(&device->sem_async, 0);
+    
+    ret  = hifEnableFunc(device, func);
+
+    return ret;
+}
+
+
+void
+HIFAckInterrupt(HIF_DEVICE *device)
+{
+    AR_DEBUG_ASSERT(device != NULL);
+
+    /* Acknowledge our function IRQ */
+}
+
+void
+HIFUnMaskInterrupt(HIF_DEVICE *device)
+{
+    int ret;
+
+    AR_DEBUG_ASSERT(device != NULL);
+    AR_DEBUG_ASSERT(device->func != NULL);
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: HIFUnMaskInterrupt\n"));
+
+    /* Register the IRQ Handler */
+    sdio_claim_host(device->func);
+    ret = sdio_claim_irq(device->func, hifIRQHandler);
+    sdio_release_host(device->func);
+    AR_DEBUG_ASSERT(ret == 0);
+}
+
+void HIFMaskInterrupt(HIF_DEVICE *device)
+{
+    int ret;
+    AR_DEBUG_ASSERT(device != NULL);
+    AR_DEBUG_ASSERT(device->func != NULL);
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: HIFMaskInterrupt\n"));
+
+    /* Mask our function IRQ */
+    sdio_claim_host(device->func);
+    while (atomic_read(&device->irqHandling)) {        
+        sdio_release_host(device->func);
+        schedule_timeout(HZ/10);
+        sdio_claim_host(device->func);
+    }
+    ret = sdio_release_irq(device->func);
+    sdio_release_host(device->func);
+    AR_DEBUG_ASSERT(ret == 0);
+}
+
+BUS_REQUEST *hifAllocateBusRequest(HIF_DEVICE *device)
+{
+    BUS_REQUEST *busrequest;
+    unsigned long flag;
+
+    /* Acquire lock */
+    spin_lock_irqsave(&device->lock, flag);
+
+    /* Remove first in list */
+    if((busrequest = device->s_busRequestFreeQueue) != NULL)
+    {
+        device->s_busRequestFreeQueue = busrequest->next;
+    }
+    /* Release lock */
+    spin_unlock_irqrestore(&device->lock, flag);
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: hifAllocateBusRequest: 0x%p\n", busrequest));
+    return busrequest;
+}
+
+void
+hifFreeBusRequest(HIF_DEVICE *device, BUS_REQUEST *busrequest)
+{
+    unsigned long flag;
+
+    AR_DEBUG_ASSERT(busrequest != NULL);
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: hifFreeBusRequest: 0x%p\n", busrequest));
+    /* Acquire lock */
+    spin_lock_irqsave(&device->lock, flag);
+
+
+    /* Insert first in list */
+    busrequest->next = device->s_busRequestFreeQueue;
+    busrequest->inusenext = NULL;
+    device->s_busRequestFreeQueue = busrequest;
+
+    /* Release lock */
+    spin_unlock_irqrestore(&device->lock, flag);
+}
+
+static A_STATUS hifDisableFunc(HIF_DEVICE *device, struct sdio_func *func)
+{
+    int ret;
+    A_STATUS status = A_OK;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: +hifDisableFunc\n"));
+    device = getHifDevice(func);
+    if (!IS_ERR(device->async_task)) {
+        init_completion(&device->async_completion);
+        device->async_shutdown = 1;
+        up(&device->sem_async);
+        wait_for_completion(&device->async_completion);
+        device->async_task = NULL;
+    }
+    /* Disable the card */
+    sdio_claim_host(device->func);
+    ret = sdio_disable_func(device->func);
+    if (ret) {
+        status = A_ERROR;
+    } 
+
+    if (reset_sdio_on_unload) {
+        /* reset the SDIO interface.  This is useful in automated testing where the card
+         * does not need to be removed at the end of the test.  It is expected that the user will 
+         * also unload/reload the host controller driver to force the bus driver to re-enumerate the slot */
+        AR_DEBUG_PRINTF(ATH_DEBUG_WARN, ("AR6000: reseting SDIO card back to uninitialized state \n"));
+        
+        /* NOTE : sdio_f0_writeb() cannot be used here, that API only allows access
+         *        to undefined registers in the range of: 0xF0-0xFF */
+         
+        ret = Func0_CMD52WriteByte(device->func->card, SDIO_CCCR_ABORT, (1 << 3)); 
+        if (ret) {
+            status = A_ERROR;
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("AR6000: reset failed : %d \n",ret));    
+        }
+    }
+
+    sdio_release_host(device->func);
+
+    if (status == A_OK) {
+        device->is_disabled = TRUE;
+    }
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: -hifDisableFunc\n"));
+
+    return status;
+}
+
+static int hifEnableFunc(HIF_DEVICE *device, struct sdio_func *func)
+{
+    struct task_struct* pTask;
+    const char *taskName = NULL;
+    int (*taskFunc)(void *) = NULL;
+    int ret = A_OK;
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: +hifEnableFunc\n"));
+    device = getHifDevice(func);
+
+    if (device->is_disabled) {
+       /* enable the SDIO function */
+        sdio_claim_host(func);
+
+        if ((device->id->device & MANUFACTURER_ID_AR6K_BASE_MASK) >= MANUFACTURER_ID_AR6003_BASE) {
+            /* enable 4-bit ASYNC interrupt on AR6003 or later devices */
+            ret = Func0_CMD52WriteByte(func->card, CCCR_SDIO_IRQ_MODE_REG, SDIO_IRQ_MODE_ASYNC_4BIT_IRQ);
+            if (ret) {
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("AR6000: failed to enable 4-bit ASYNC IRQ mode %d \n",ret));
+                sdio_release_host(func);
+                return A_ERROR;
+            }
+            AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: 4-bit ASYNC IRQ mode enabled\n"));
+        }
+        /* give us some time to enable, in ms */
+        func->enable_timeout = 100;
+        ret = sdio_enable_func(func);
+        if (ret) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("AR6000: %s(), Unable to enable AR6K: 0x%X\n",
+					  __FUNCTION__, ret));
+            sdio_release_host(func);
+            return A_ERROR;
+        }
+        ret = sdio_set_block_size(func, HIF_MBOX_BLOCK_SIZE);
+        sdio_release_host(func);
+        if (ret) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("AR6000: %s(), Unable to set block size 0x%x  AR6K: 0x%X\n",
+					  __FUNCTION__, HIF_MBOX_BLOCK_SIZE, ret));
+            return A_ERROR;
+        }
+        device->is_disabled = FALSE;
+        /* create async I/O thread */
+        if (!device->async_task) {
+            device->async_shutdown = 0;
+            device->async_task = kthread_create(async_task,
+                                           (void *)device,
+                                           "AR6K Async");
+           if (IS_ERR(device->async_task)) {
+               AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("AR6000: %s(), to create async task\n", __FUNCTION__));
+                return A_ERROR;
+           }
+           AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: start async task\n"));
+           wake_up_process(device->async_task );    
+        }
+    }
+
+    if (!device->claimedContext) {
+        taskFunc = startup_task;
+        taskName = "AR6K startup";
+        ret = A_OK;
+#if defined(CONFIG_PM)
+    } else {
+        taskFunc = enable_task;
+        taskName = "AR6K enable";
+        ret = A_PENDING;
+#endif /* CONFIG_PM */
+    }
+    /* create resume thread */
+    pTask = kthread_create(taskFunc, (void *)device, taskName);
+    if (IS_ERR(pTask)) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("AR6000: %s(), to create enabel task\n", __FUNCTION__));
+        return A_ERROR;
+    }
+    wake_up_process(pTask);
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: -hifEnableFunc\n"));
+
+    /* task will call the enable func, indicate pending */
+    return ret;
+}
+
+#if defined(CONFIG_PM)
+static int hifDeviceSuspend(struct device *dev)
+{
+    struct sdio_func *func=dev_to_sdio_func(dev);
+    A_STATUS status = A_OK;
+    HIF_DEVICE *device;   
+
+    device = getHifDevice(func);
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: +hifDeviceSuspend\n"));
+    if (device && device->claimedContext && osdrvCallbacks.deviceSuspendHandler) {
+        device->is_suspend = TRUE; /* set true first for PowerStateChangeNotify(..) */
+        status = osdrvCallbacks.deviceSuspendHandler(device->claimedContext);
+        if (status != A_OK) {
+            device->is_suspend = FALSE;
+        }
+    }
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: -hifDeviceSuspend\n"));
+
+    switch (status) {
+    case A_OK:
+        return 0;
+    case A_EBUSY:
+        return -EBUSY; /* Hack for kernel in order to support deep sleep and wow */
+    default:
+        return -1;
+    }
+}
+
+static int hifDeviceResume(struct device *dev)
+{
+    struct sdio_func *func=dev_to_sdio_func(dev);
+    A_STATUS status = A_OK;
+    HIF_DEVICE *device;   
+
+    device = getHifDevice(func);
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: +hifDeviceResume\n"));
+    if (device && device->claimedContext && osdrvCallbacks.deviceSuspendHandler) {
+        status = osdrvCallbacks.deviceResumeHandler(device->claimedContext);
+        if (status == A_OK) {
+            device->is_suspend = FALSE;
+        }
+    }
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: -hifDeviceResume\n"));
+
+    return A_SUCCESS(status) ? 0 : status;
+}
+#endif /* CONFIG_PM */
+
+static void hifDeviceRemoved(struct sdio_func *func)
+{
+    A_STATUS status = A_OK;
+    HIF_DEVICE *device;
+    AR_DEBUG_ASSERT(func != NULL);
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: +hifDeviceRemoved\n"));
+    device = getHifDevice(func);
+    if (device->claimedContext != NULL) {
+        status = osdrvCallbacks.deviceRemovedHandler(device->claimedContext, device);
+    }
+
+    if (device->is_disabled) {
+        device->is_disabled = FALSE;
+    } else {
+        status = hifDisableFunc(device, func);
+    }
+    CleanupHIFScatterResources(device);
+     
+    delHifDevice(device);
+    AR_DEBUG_ASSERT(status == A_OK);
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: -hifDeviceRemoved\n"));
+}
+
+/*
+ * This should be moved to AR6K HTC layer.
+ */
+A_STATUS hifWaitForPendingRecv(HIF_DEVICE *device)
+{
+    A_INT32 cnt = 10;
+    A_UINT8 host_int_status;
+    A_STATUS status = A_OK;
+
+    do {            		    
+        while (atomic_read(&device->irqHandling)) {
+	        /* wait until irq handler finished all the jobs */
+			schedule_timeout(HZ/10);
+	    }
+		/* check if there is any pending irq due to force done */
+		host_int_status = 0;
+	    status = HIFReadWrite(device, HOST_INT_STATUS_ADDRESS,
+				    (A_UINT8 *)&host_int_status, sizeof(host_int_status),
+			  	     HIF_RD_SYNC_BYTE_INC, NULL);
+	    host_int_status = A_SUCCESS(status) ? (host_int_status & (1 << 0)) : 0;
+		if (host_int_status) {
+	        schedule(); /* schedule for next dsrHandler */
+		}
+	} while (host_int_status && --cnt > 0);
+
+    if (host_int_status && cnt == 0) {
+         AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, 
+                            ("AR6000: %s(), Unable clear up pending IRQ before the system suspended\n", __FUNCTION__));
+     }
+
+    return A_OK;
+}
+    
+
+static HIF_DEVICE *
+addHifDevice(struct sdio_func *func)
+{
+    HIF_DEVICE *hifdevice;
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: addHifDevice\n"));
+    AR_DEBUG_ASSERT(func != NULL);
+    hifdevice = kzalloc(sizeof(HIF_DEVICE), GFP_KERNEL);
+    AR_DEBUG_ASSERT(hifdevice != NULL);
+#if HIF_USE_DMA_BOUNCE_BUFFER
+    hifdevice->dma_buffer = kmalloc(HIF_DMA_BUFFER_SIZE, GFP_KERNEL);
+    AR_DEBUG_ASSERT(hifdevice->dma_buffer != NULL);
+#endif
+    hifdevice->func = func;
+    hifdevice->powerConfig = HIF_DEVICE_POWER_UP;
+    sdio_set_drvdata(func, hifdevice);
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: addHifDevice; 0x%p\n", hifdevice));
+    return hifdevice;
+}
+
+static HIF_DEVICE *
+getHifDevice(struct sdio_func *func)
+{
+    AR_DEBUG_ASSERT(func != NULL);
+    return (HIF_DEVICE *)sdio_get_drvdata(func);
+}
+
+static void
+delHifDevice(HIF_DEVICE * device)
+{
+    AR_DEBUG_ASSERT(device!= NULL);
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: delHifDevice; 0x%p\n", device));
+    if (device->dma_buffer != NULL) {
+        kfree(device->dma_buffer);
+    }
+    kfree(device);
+}
+
+static void ResetAllCards(void)
+{
+}
+
+void HIFClaimDevice(HIF_DEVICE  *device, void *context)
+{
+    device->claimedContext = context;
+}
+
+void HIFReleaseDevice(HIF_DEVICE  *device)
+{
+    device->claimedContext = NULL;
+}
+
+A_STATUS HIFAttachHTC(HIF_DEVICE *device, HTC_CALLBACKS *callbacks)
+{
+    if (device->htcCallbacks.context != NULL) {
+            /* already in use! */
+        return A_ERROR;
+    }
+    device->htcCallbacks = *callbacks;
+    return A_OK;
+}
+
+void HIFDetachHTC(HIF_DEVICE *device)
+{
+    A_MEMZERO(&device->htcCallbacks,sizeof(device->htcCallbacks));
+}
+
+#define SDIO_SET_CMD52_ARG(arg,rw,func,raw,address,writedata) \
+    (arg) = (((rw) & 1) << 31)           | \
+            (((func) & 0x7) << 28)       | \
+            (((raw) & 1) << 27)          | \
+            (1 << 26)                    | \
+            (((address) & 0x1FFFF) << 9) | \
+            (1 << 8)                     | \
+            ((writedata) & 0xFF)
+            
+#define SDIO_SET_CMD52_READ_ARG(arg,func,address) \
+    SDIO_SET_CMD52_ARG(arg,0,(func),0,address,0x00)
+#define SDIO_SET_CMD52_WRITE_ARG(arg,func,address,value) \
+    SDIO_SET_CMD52_ARG(arg,1,(func),0,address,value)
+    
+static int Func0_CMD52WriteByte(struct mmc_card *card, unsigned int address, unsigned char byte)
+{
+    struct mmc_command ioCmd;
+    unsigned long      arg;
+    
+    memset(&ioCmd,0,sizeof(ioCmd));
+    SDIO_SET_CMD52_WRITE_ARG(arg,0,address,byte);
+    ioCmd.opcode = SD_IO_RW_DIRECT;
+    ioCmd.arg = arg;
+    ioCmd.flags = MMC_RSP_R5 | MMC_CMD_AC;
+    
+    return mmc_wait_for_cmd(card->host, &ioCmd, 0);
+}
+
+static int Func0_CMD52ReadByte(struct mmc_card *card, unsigned int address, unsigned char *byte)
+{
+    struct mmc_command ioCmd;
+    unsigned long      arg;
+    A_INT32 err;
+    
+    memset(&ioCmd,0,sizeof(ioCmd));
+    SDIO_SET_CMD52_READ_ARG(arg,0,address);
+    ioCmd.opcode = SD_IO_RW_DIRECT;
+    ioCmd.arg = arg;
+    ioCmd.flags = MMC_RSP_R5 | MMC_CMD_AC;
+
+    err = mmc_wait_for_cmd(card->host, &ioCmd, 0);
+
+    if ((!err) && (byte)) {
+        *byte =  ioCmd.resp[0] & 0xFF;
+    }
+
+    return err;
+}
diff --git a/drivers/net/ath6kl/hif/sdio/linux_sdio/src/hif_scatter.c b/drivers/net/ath6kl/hif/sdio/linux_sdio/src/hif_scatter.c
new file mode 100644
index 00000000000..22c6c6659f5
--- /dev/null
+++ b/drivers/net/ath6kl/hif/sdio/linux_sdio/src/hif_scatter.c
@@ -0,0 +1,393 @@
+//------------------------------------------------------------------------------
+// Copyright (c) 2009-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// HIF scatter implementation
+//
+// Author(s): ="Atheros"
+//==============================================================================
+
+#include <linux/mmc/card.h>
+#include <linux/mmc/host.h>
+#include <linux/mmc/sdio_func.h>
+#include <linux/mmc/sdio_ids.h>
+#include <linux/mmc/sdio.h>
+#include <linux/kthread.h>
+#include "hif_internal.h"
+#define ATH_MODULE_NAME hif
+#include "a_debug.h"
+
+#ifdef HIF_LINUX_MMC_SCATTER_SUPPORT
+
+#define _CMD53_ARG_READ          0
+#define _CMD53_ARG_WRITE         1
+#define _CMD53_ARG_BLOCK_BASIS   1 
+#define _CMD53_ARG_FIXED_ADDRESS 0
+#define _CMD53_ARG_INCR_ADDRESS  1
+
+#define SDIO_SET_CMD53_ARG(arg,rw,func,mode,opcode,address,bytes_blocks) \
+    (arg) = (((rw) & 1) << 31)                  | \
+            (((func) & 0x7) << 28)              | \
+            (((mode) & 1) << 27)                | \
+            (((opcode) & 1) << 26)              | \
+            (((address) & 0x1FFFF) << 9)        | \
+            ((bytes_blocks) & 0x1FF)
+            
+static void FreeScatterReq(HIF_DEVICE *device, HIF_SCATTER_REQ *pReq)
+{   
+    unsigned long flag;
+
+    spin_lock_irqsave(&device->lock, flag);
+
+    DL_ListInsertTail(&device->ScatterReqHead, &pReq->ListLink);
+    
+    spin_unlock_irqrestore(&device->lock, flag);
+        
+}
+
+static HIF_SCATTER_REQ *AllocScatterReq(HIF_DEVICE *device) 
+{
+    DL_LIST       *pItem; 
+    unsigned long flag;
+
+    spin_lock_irqsave(&device->lock, flag);
+    
+    pItem = DL_ListRemoveItemFromHead(&device->ScatterReqHead);
+    
+    spin_unlock_irqrestore(&device->lock, flag);
+    
+    if (pItem != NULL) {
+        return A_CONTAINING_STRUCT(pItem, HIF_SCATTER_REQ, ListLink);
+    }
+    
+    return NULL;   
+}
+
+    /* called by async task to perform the operation synchronously using direct MMC APIs  */
+A_STATUS DoHifReadWriteScatter(HIF_DEVICE *device, BUS_REQUEST *busrequest)
+{
+    int                     i;
+    A_UINT8                 rw;
+    A_UINT8                 opcode;
+    struct mmc_request      mmcreq;
+    struct mmc_command      cmd;
+    struct mmc_data         data;
+    HIF_SCATTER_REQ_PRIV   *pReqPriv;   
+    HIF_SCATTER_REQ        *pReq;       
+    A_STATUS                status = A_OK;
+    struct                  scatterlist *pSg;
+    
+    pReqPriv = busrequest->pScatterReq;
+    
+    A_ASSERT(pReqPriv != NULL);
+    
+    pReq = pReqPriv->pHifScatterReq;
+    
+    memset(&mmcreq, 0, sizeof(struct mmc_request));
+    memset(&cmd, 0, sizeof(struct mmc_command));
+    memset(&data, 0, sizeof(struct mmc_data));
+       
+    data.blksz = HIF_MBOX_BLOCK_SIZE;
+    data.blocks = pReq->TotalLength / HIF_MBOX_BLOCK_SIZE;
+                        
+    AR_DEBUG_PRINTF(ATH_DEBUG_SCATTER, ("HIF-SCATTER: (%s) Address: 0x%X, (BlockLen: %d, BlockCount: %d) , (tot:%d,sg:%d)\n",
+              (pReq->Request & HIF_WRITE) ? "WRITE":"READ", pReq->Address, data.blksz, data.blocks,
+              pReq->TotalLength,pReq->ValidScatterEntries));
+         
+    if (pReq->Request  & HIF_WRITE) {
+        rw = _CMD53_ARG_WRITE;
+        data.flags = MMC_DATA_WRITE;
+    } else {
+        rw = _CMD53_ARG_READ;
+        data.flags = MMC_DATA_READ;
+    }
+
+    if (pReq->Request & HIF_FIXED_ADDRESS) {
+        opcode = _CMD53_ARG_FIXED_ADDRESS;
+    } else {
+        opcode = _CMD53_ARG_INCR_ADDRESS;
+    }
+    
+        /* fill SG entries */
+    pSg = pReqPriv->sgentries;   
+    sg_init_table(pSg, pReq->ValidScatterEntries); 
+          
+        /* assemble SG list */   
+    for (i = 0 ; i < pReq->ValidScatterEntries ; i++, pSg++) {
+            /* setup each sg entry */
+        if ((unsigned long)pReq->ScatterList[i].pBuffer & 0x3) {
+                /* note some scatter engines can handle unaligned buffers, print this
+                 * as informational only */
+            AR_DEBUG_PRINTF(ATH_DEBUG_SCATTER,
+                            ("HIF: (%s) Scatter Buffer is unaligned 0x%lx\n",
+                            pReq->Request & HIF_WRITE ? "WRITE":"READ",
+                            (unsigned long)pReq->ScatterList[i].pBuffer)); 
+        }
+        
+        AR_DEBUG_PRINTF(ATH_DEBUG_SCATTER, ("  %d:  Addr:0x%lX, Len:%d \n",
+            i,(unsigned long)pReq->ScatterList[i].pBuffer,pReq->ScatterList[i].Length));
+            
+        sg_set_buf(pSg, pReq->ScatterList[i].pBuffer, pReq->ScatterList[i].Length);
+    }
+        /* set scatter-gather table for request */
+    data.sg = pReqPriv->sgentries;
+    data.sg_len = pReq->ValidScatterEntries;
+        /* set command argument */    
+    SDIO_SET_CMD53_ARG(cmd.arg, 
+                       rw, 
+                       device->func->num, 
+                       _CMD53_ARG_BLOCK_BASIS, 
+                       opcode,  
+                       pReq->Address,
+                       data.blocks);  
+                       
+    cmd.opcode = SD_IO_RW_EXTENDED;
+    cmd.flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_ADTC;
+    
+    mmcreq.cmd = &cmd;
+    mmcreq.data = &data;
+    
+    mmc_set_data_timeout(&data, device->func->card);    
+        /* synchronous call to process request */
+    mmc_wait_for_req(device->func->card->host, &mmcreq);
+ 
+    if (cmd.error) {
+        status = A_ERROR;   
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("HIF-SCATTER: cmd error: %d \n",cmd.error));
+    }
+               
+    if (data.error) {
+        status = A_ERROR;
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("HIF-SCATTER: data error: %d \n",data.error));   
+    }
+
+    if (A_FAILED(status)) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("HIF-SCATTER: FAILED!!! (%s) Address: 0x%X, Block mode (BlockLen: %d, BlockCount: %d)\n",
+              (pReq->Request & HIF_WRITE) ? "WRITE":"READ",pReq->Address, data.blksz, data.blocks));        
+    }
+    
+        /* set completion status, fail or success */
+    pReq->CompletionStatus = status;
+    
+    if (pReq->Request & HIF_ASYNCHRONOUS) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_SCATTER, ("HIF-SCATTER: async_task completion routine req: 0x%lX (%d)\n",(unsigned long)busrequest, status));
+            /* complete the request */
+        A_ASSERT(pReq->CompletionRoutine != NULL);
+        pReq->CompletionRoutine(pReq);
+    } else {
+        AR_DEBUG_PRINTF(ATH_DEBUG_SCATTER, ("HIF-SCATTER async_task upping busrequest : 0x%lX (%d)\n", (unsigned long)busrequest,status));
+            /* signal wait */
+        up(&busrequest->sem_req);
+    }
+                                                               
+    return status;   
+}
+
+    /* callback to issue a read-write scatter request */
+static A_STATUS HifReadWriteScatter(HIF_DEVICE *device, HIF_SCATTER_REQ *pReq)
+{
+    A_STATUS             status = A_EINVAL;
+    A_UINT32             request = pReq->Request;
+    HIF_SCATTER_REQ_PRIV *pReqPriv = (HIF_SCATTER_REQ_PRIV *)pReq->HIFPrivate[0];
+    
+    do {
+        
+        A_ASSERT(pReqPriv != NULL);
+        
+        AR_DEBUG_PRINTF(ATH_DEBUG_SCATTER, ("HIF-SCATTER: total len: %d Scatter Entries: %d\n", 
+                            pReq->TotalLength, pReq->ValidScatterEntries));
+        
+        if (!(request & HIF_EXTENDED_IO)) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
+                            ("HIF-SCATTER: Invalid command type: 0x%08x\n", request));
+            break;
+        }
+        
+        if (!(request & (HIF_SYNCHRONOUS | HIF_ASYNCHRONOUS))) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
+                            ("HIF-SCATTER: Invalid execution mode: 0x%08x\n", request));
+            break;
+        }
+        
+        if (!(request & HIF_BLOCK_BASIS)) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
+                            ("HIF-SCATTER: Invalid data mode: 0x%08x\n", request));
+            break;   
+        }
+        
+        if (pReq->TotalLength > MAX_SCATTER_REQ_TRANSFER_SIZE) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
+                            ("HIF-SCATTER: Invalid length: %d \n", pReq->TotalLength));
+            break;          
+        }
+        
+        if (pReq->TotalLength == 0) {
+            A_ASSERT(FALSE);
+            break;    
+        }
+        
+            /* add bus request to the async list for the async I/O thread to process */
+        AddToAsyncList(device, pReqPriv->busrequest);
+
+        if (request & HIF_SYNCHRONOUS) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_SCATTER, ("HIF-SCATTER: queued sync req: 0x%lX\n", (unsigned long)pReqPriv->busrequest));
+            /* signal thread and wait */
+            up(&device->sem_async);
+            if (down_interruptible(&pReqPriv->busrequest->sem_req) != 0) {
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,("HIF-SCATTER: interrupted! \n"));
+                /* interrupted, exit */
+                status = A_ERROR;
+                break;
+            } else {
+                status = pReq->CompletionStatus;
+            }
+        } else {
+            AR_DEBUG_PRINTF(ATH_DEBUG_SCATTER, ("HIF-SCATTER: queued async req: 0x%lX\n", (unsigned long)pReqPriv->busrequest));
+                /* wake thread, it will process and then take care of the async callback */
+            up(&device->sem_async);
+            status = A_OK;
+        }           
+       
+    } while (FALSE);
+
+    if (A_FAILED(status) && (request & HIF_ASYNCHRONOUS)) {
+        pReq->CompletionStatus = status;
+        pReq->CompletionRoutine(pReq);
+        status = A_OK;
+    }
+        
+    return status;  
+}
+
+    /* setup of HIF scatter resources */
+A_STATUS SetupHIFScatterSupport(HIF_DEVICE *device, HIF_DEVICE_SCATTER_SUPPORT_INFO *pInfo)
+{
+    A_STATUS              status = A_ERROR;   
+    int                   i;
+    HIF_SCATTER_REQ_PRIV *pReqPriv;
+    BUS_REQUEST          *busrequest;
+        
+    do {
+        
+            /* check if host supports scatter requests and it meets our requirements */
+        if (device->func->card->host->max_hw_segs < MAX_SCATTER_ENTRIES_PER_REQ) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("HIF-SCATTER : host only supports scatter of : %d entries, need: %d \n",
+                    device->func->card->host->max_hw_segs, MAX_SCATTER_ENTRIES_PER_REQ));
+            status = A_ENOTSUP;
+            break;    
+        }
+                    
+        AR_DEBUG_PRINTF(ATH_DEBUG_ANY,("HIF-SCATTER Enabled: max scatter req : %d entries: %d \n",
+                MAX_SCATTER_REQUESTS, MAX_SCATTER_ENTRIES_PER_REQ)); 
+        
+        for (i = 0; i < MAX_SCATTER_REQUESTS; i++) {    
+                /* allocate the private request blob */
+            pReqPriv = (HIF_SCATTER_REQ_PRIV *)A_MALLOC(sizeof(HIF_SCATTER_REQ_PRIV));
+            if (NULL == pReqPriv) {
+                break;    
+            }
+            A_MEMZERO(pReqPriv, sizeof(HIF_SCATTER_REQ_PRIV));
+                /* save the device instance*/
+            pReqPriv->device = device;      
+                /* allocate the scatter request */
+            pReqPriv->pHifScatterReq = (HIF_SCATTER_REQ *)A_MALLOC(sizeof(HIF_SCATTER_REQ) + 
+                                         (MAX_SCATTER_ENTRIES_PER_REQ - 1) * (sizeof(HIF_SCATTER_ITEM))); 
+           
+            if (NULL == pReqPriv->pHifScatterReq) {
+                A_FREE(pReqPriv);
+                break;      
+            }           
+                /* just zero the main part of the scatter request */
+            A_MEMZERO(pReqPriv->pHifScatterReq, sizeof(HIF_SCATTER_REQ));
+                /* back pointer to the private struct */
+            pReqPriv->pHifScatterReq->HIFPrivate[0] = pReqPriv;
+                /* allocate a bus request for this scatter request */
+            busrequest = hifAllocateBusRequest(device);
+            if (NULL == busrequest) {
+                A_FREE(pReqPriv->pHifScatterReq);
+                A_FREE(pReqPriv);
+                break;    
+            }
+                /* assign the scatter request to this bus request */
+            busrequest->pScatterReq = pReqPriv;
+                /* point back to the request */
+            pReqPriv->busrequest = busrequest;                           
+                /* add it to the scatter pool */
+            FreeScatterReq(device,pReqPriv->pHifScatterReq);
+        }
+        
+        if (i != MAX_SCATTER_REQUESTS) {
+            status = A_NO_MEMORY;
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("HIF-SCATTER : failed to alloc scatter resources !\n"));
+            break;    
+        }
+        
+            /* set scatter function pointers */
+        pInfo->pAllocateReqFunc = AllocScatterReq;
+        pInfo->pFreeReqFunc = FreeScatterReq;
+        pInfo->pReadWriteScatterFunc = HifReadWriteScatter;   
+        pInfo->MaxScatterEntries = MAX_SCATTER_ENTRIES_PER_REQ;
+        pInfo->MaxTransferSizePerScatterReq = MAX_SCATTER_REQ_TRANSFER_SIZE;
+     
+        status = A_OK;
+        
+    } while (FALSE);
+    
+    if (A_FAILED(status)) {
+        CleanupHIFScatterResources(device);   
+    }
+    
+    return status;
+}
+
+    /* clean up scatter support */
+void CleanupHIFScatterResources(HIF_DEVICE *device)
+{
+    HIF_SCATTER_REQ_PRIV    *pReqPriv;
+    HIF_SCATTER_REQ         *pReq;
+    
+        /* empty the free list */
+        
+    while (1) {
+        
+        pReq = AllocScatterReq(device);
+                
+        if (NULL == pReq) {
+            break;    
+        }   
+        
+        pReqPriv = (HIF_SCATTER_REQ_PRIV *)pReq->HIFPrivate[0];
+        A_ASSERT(pReqPriv != NULL);
+        
+        if (pReqPriv->busrequest != NULL) {
+            pReqPriv->busrequest->pScatterReq = NULL;
+                /* free bus request */
+            hifFreeBusRequest(device, pReqPriv->busrequest);
+            pReqPriv->busrequest = NULL;
+        }
+        
+        if (pReqPriv->pHifScatterReq != NULL) {
+            A_FREE(pReqPriv->pHifScatterReq);   
+            pReqPriv->pHifScatterReq = NULL; 
+        }
+                
+        A_FREE(pReqPriv);       
+    }
+}
+
+#endif // HIF_LINUX_MMC_SCATTER_SUPPORT
diff --git a/drivers/net/ath6kl/htc2/AR6000/ar6k.c b/drivers/net/ath6kl/htc2/AR6000/ar6k.c
new file mode 100644
index 00000000000..1efc85ce02b
--- /dev/null
+++ b/drivers/net/ath6kl/htc2/AR6000/ar6k.c
@@ -0,0 +1,1471 @@
+//------------------------------------------------------------------------------
+// <copyright file="ar6k.c" company="Atheros">
+//    Copyright (c) 2007-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// AR6K device layer that handles register level I/O
+//
+// Author(s): ="Atheros"
+//==============================================================================
+
+#include "a_config.h"
+#include "athdefs.h"
+#include "a_types.h"
+#include "AR6002/hw2.0/hw/mbox_host_reg.h"
+#include "a_osapi.h"
+#include "../htc_debug.h"
+#include "hif.h"
+#include "htc_packet.h"
+#include "ar6k.h"
+
+#define MAILBOX_FOR_BLOCK_SIZE          1
+
+A_STATUS DevEnableInterrupts(AR6K_DEVICE *pDev);
+A_STATUS DevDisableInterrupts(AR6K_DEVICE *pDev);
+
+static void DevCleanupVirtualScatterSupport(AR6K_DEVICE *pDev);
+
+void AR6KFreeIOPacket(AR6K_DEVICE *pDev, HTC_PACKET *pPacket)
+{
+    LOCK_AR6K(pDev);
+    HTC_PACKET_ENQUEUE(&pDev->RegisterIOList,pPacket);
+    UNLOCK_AR6K(pDev);
+}
+
+HTC_PACKET *AR6KAllocIOPacket(AR6K_DEVICE *pDev)
+{
+    HTC_PACKET *pPacket;
+
+    LOCK_AR6K(pDev);
+    pPacket = HTC_PACKET_DEQUEUE(&pDev->RegisterIOList);
+    UNLOCK_AR6K(pDev);
+
+    return pPacket;
+}
+
+void DevCleanup(AR6K_DEVICE *pDev)
+{
+    DevCleanupGMbox(pDev);
+
+    if (pDev->HifAttached) {
+        HIFDetachHTC(pDev->HIFDevice);
+        pDev->HifAttached = FALSE;
+    }
+
+    DevCleanupVirtualScatterSupport(pDev);
+
+    if (A_IS_MUTEX_VALID(&pDev->Lock)) {
+        A_MUTEX_DELETE(&pDev->Lock);
+    }
+}
+
+A_STATUS DevSetup(AR6K_DEVICE *pDev)
+{
+    A_UINT32 blocksizes[AR6K_MAILBOXES];
+    A_STATUS status = A_OK;
+    int      i;
+    HTC_CALLBACKS htcCallbacks;
+
+    do {
+
+        DL_LIST_INIT(&pDev->ScatterReqHead);
+           /* initialize our free list of IO packets */
+        INIT_HTC_PACKET_QUEUE(&pDev->RegisterIOList);
+        A_MUTEX_INIT(&pDev->Lock);
+
+        A_MEMZERO(&htcCallbacks, sizeof(HTC_CALLBACKS));
+            /* the device layer handles these */
+        htcCallbacks.rwCompletionHandler = DevRWCompletionHandler;
+        htcCallbacks.dsrHandler = DevDsrHandler;
+        htcCallbacks.context = pDev;
+
+        status = HIFAttachHTC(pDev->HIFDevice, &htcCallbacks);
+
+        if (A_FAILED(status)) {
+            break;
+        }
+
+        pDev->HifAttached = TRUE;
+
+            /* get the addresses for all 4 mailboxes */
+        status = HIFConfigureDevice(pDev->HIFDevice, HIF_DEVICE_GET_MBOX_ADDR,
+                                    &pDev->MailBoxInfo, sizeof(pDev->MailBoxInfo));
+
+        if (status != A_OK) {
+            A_ASSERT(FALSE);
+            break;
+        }
+
+            /* carve up register I/O packets (these are for ASYNC register I/O ) */
+        for (i = 0; i < AR6K_MAX_REG_IO_BUFFERS; i++) {
+            HTC_PACKET *pIOPacket;
+            pIOPacket = &pDev->RegIOBuffers[i].HtcPacket;
+            SET_HTC_PACKET_INFO_RX_REFILL(pIOPacket,
+                                          pDev,
+                                          pDev->RegIOBuffers[i].Buffer,
+                                          AR6K_REG_IO_BUFFER_SIZE,
+                                          0); /* don't care */
+            AR6KFreeIOPacket(pDev,pIOPacket);
+        }
+
+            /* get the block sizes */
+        status = HIFConfigureDevice(pDev->HIFDevice, HIF_DEVICE_GET_MBOX_BLOCK_SIZE,
+                                    blocksizes, sizeof(blocksizes));
+
+        if (status != A_OK) {
+            A_ASSERT(FALSE);
+            break;
+        }
+
+            /* note: we actually get the block size of a mailbox other than 0, for SDIO the block
+             * size on mailbox 0 is artificially set to 1.  So we use the block size that is set
+             * for the other 3 mailboxes */
+        pDev->BlockSize = blocksizes[MAILBOX_FOR_BLOCK_SIZE];
+            /* must be a power of 2 */
+        A_ASSERT((pDev->BlockSize & (pDev->BlockSize - 1)) == 0);
+
+            /* assemble mask, used for padding to a block */
+        pDev->BlockMask = pDev->BlockSize - 1;
+
+        AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("BlockSize: %d, MailboxAddress:0x%X \n",
+                    pDev->BlockSize, pDev->MailBoxInfo.MboxAddresses[HTC_MAILBOX]));
+
+        pDev->GetPendingEventsFunc = NULL;
+            /* see if the HIF layer implements the get pending events function  */
+        HIFConfigureDevice(pDev->HIFDevice,
+                           HIF_DEVICE_GET_PENDING_EVENTS_FUNC,
+                           &pDev->GetPendingEventsFunc,
+                           sizeof(pDev->GetPendingEventsFunc));
+
+            /* assume we can process HIF interrupt events asynchronously */
+        pDev->HifIRQProcessingMode = HIF_DEVICE_IRQ_ASYNC_SYNC;
+
+            /* see if the HIF layer overrides this assumption */
+        HIFConfigureDevice(pDev->HIFDevice,
+                           HIF_DEVICE_GET_IRQ_PROC_MODE,
+                           &pDev->HifIRQProcessingMode,
+                           sizeof(pDev->HifIRQProcessingMode));
+
+        switch (pDev->HifIRQProcessingMode) {
+            case HIF_DEVICE_IRQ_SYNC_ONLY:
+                AR_DEBUG_PRINTF(ATH_DEBUG_WARN,("HIF Interrupt processing is SYNC ONLY\n"));
+                    /* see if HIF layer wants HTC to yield */
+                HIFConfigureDevice(pDev->HIFDevice,
+                                   HIF_DEVICE_GET_IRQ_YIELD_PARAMS,
+                                   &pDev->HifIRQYieldParams,
+                                   sizeof(pDev->HifIRQYieldParams));
+
+                if (pDev->HifIRQYieldParams.RecvPacketYieldCount > 0) {
+                    AR_DEBUG_PRINTF(ATH_DEBUG_WARN,
+                        ("HIF requests that DSR yield per %d RECV packets \n",
+                        pDev->HifIRQYieldParams.RecvPacketYieldCount));
+                    pDev->DSRCanYield = TRUE;
+                }
+                break;
+            case HIF_DEVICE_IRQ_ASYNC_SYNC:
+                AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("HIF Interrupt processing is ASYNC and SYNC\n"));
+                break;
+            default:
+                A_ASSERT(FALSE);
+        }
+
+        pDev->HifMaskUmaskRecvEvent = NULL;
+
+            /* see if the HIF layer implements the mask/unmask recv events function  */
+        HIFConfigureDevice(pDev->HIFDevice,
+                           HIF_DEVICE_GET_RECV_EVENT_MASK_UNMASK_FUNC,
+                           &pDev->HifMaskUmaskRecvEvent,
+                           sizeof(pDev->HifMaskUmaskRecvEvent));
+
+        AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("HIF special overrides : 0x%lX , 0x%lX\n",
+                 (unsigned long)pDev->GetPendingEventsFunc, (unsigned long)pDev->HifMaskUmaskRecvEvent));
+
+        status = DevDisableInterrupts(pDev);
+
+        if (A_FAILED(status)) {
+            break;
+        }
+
+        status = DevSetupGMbox(pDev);
+
+    } while (FALSE);
+
+    if (A_FAILED(status)) {
+        if (pDev->HifAttached) {
+            HIFDetachHTC(pDev->HIFDevice);
+            pDev->HifAttached = FALSE;
+        }
+    }
+
+    return status;
+
+}
+
+A_STATUS DevEnableInterrupts(AR6K_DEVICE *pDev)
+{
+    A_STATUS                  status;
+    AR6K_IRQ_ENABLE_REGISTERS regs;
+
+    LOCK_AR6K(pDev);
+
+        /* Enable all the interrupts except for the internal AR6000 CPU interrupt */
+    pDev->IrqEnableRegisters.int_status_enable = INT_STATUS_ENABLE_ERROR_SET(0x01) |
+                                      INT_STATUS_ENABLE_CPU_SET(0x01) |
+                                      INT_STATUS_ENABLE_COUNTER_SET(0x01);
+
+    if (NULL == pDev->GetPendingEventsFunc) {
+        pDev->IrqEnableRegisters.int_status_enable |= INT_STATUS_ENABLE_MBOX_DATA_SET(0x01);
+    } else {
+        /* The HIF layer provided us with a pending events function which means that
+         * the detection of pending mbox messages is handled in the HIF layer.
+         * This is the case for the SPI2 interface.
+         * In the normal case we enable MBOX interrupts, for the case
+         * with HIFs that offer this mechanism, we keep these interrupts
+         * masked */
+        pDev->IrqEnableRegisters.int_status_enable &= ~INT_STATUS_ENABLE_MBOX_DATA_SET(0x01);
+    }
+
+
+    /* Set up the CPU Interrupt Status Register */
+    pDev->IrqEnableRegisters.cpu_int_status_enable = CPU_INT_STATUS_ENABLE_BIT_SET(0x00);
+
+    /* Set up the Error Interrupt Status Register */
+    pDev->IrqEnableRegisters.error_status_enable =
+                                  ERROR_STATUS_ENABLE_RX_UNDERFLOW_SET(0x01) |
+                                  ERROR_STATUS_ENABLE_TX_OVERFLOW_SET(0x01);
+
+    /* Set up the Counter Interrupt Status Register (only for debug interrupt to catch fatal errors) */
+    pDev->IrqEnableRegisters.counter_int_status_enable =
+        COUNTER_INT_STATUS_ENABLE_BIT_SET(AR6K_TARGET_DEBUG_INTR_MASK);
+
+        /* copy into our temp area */
+    A_MEMCPY(&regs,&pDev->IrqEnableRegisters,AR6K_IRQ_ENABLE_REGS_SIZE);
+
+    UNLOCK_AR6K(pDev);
+
+        /* always synchronous */
+    status = HIFReadWrite(pDev->HIFDevice,
+                          INT_STATUS_ENABLE_ADDRESS,
+                          &regs.int_status_enable,
+                          AR6K_IRQ_ENABLE_REGS_SIZE,
+                          HIF_WR_SYNC_BYTE_INC,
+                          NULL);
+
+    if (status != A_OK) {
+        /* Can't write it for some reason */
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                        ("Failed to update interrupt control registers err: %d\n", status));
+
+    }
+
+    return status;
+}
+
+A_STATUS DevDisableInterrupts(AR6K_DEVICE *pDev)
+{
+    AR6K_IRQ_ENABLE_REGISTERS regs;
+
+    LOCK_AR6K(pDev);
+        /* Disable all interrupts */
+    pDev->IrqEnableRegisters.int_status_enable = 0;
+    pDev->IrqEnableRegisters.cpu_int_status_enable = 0;
+    pDev->IrqEnableRegisters.error_status_enable = 0;
+    pDev->IrqEnableRegisters.counter_int_status_enable = 0;
+        /* copy into our temp area */
+    A_MEMCPY(&regs,&pDev->IrqEnableRegisters,AR6K_IRQ_ENABLE_REGS_SIZE);
+
+    UNLOCK_AR6K(pDev);
+
+        /* always synchronous */
+    return HIFReadWrite(pDev->HIFDevice,
+                        INT_STATUS_ENABLE_ADDRESS,
+                        &regs.int_status_enable,
+                        AR6K_IRQ_ENABLE_REGS_SIZE,
+                        HIF_WR_SYNC_BYTE_INC,
+                        NULL);
+}
+
+/* enable device interrupts */
+A_STATUS DevUnmaskInterrupts(AR6K_DEVICE *pDev)
+{
+    /* for good measure, make sure interrupt are disabled before unmasking at the HIF
+     * layer.
+     * The rationale here is that between device insertion (where we clear the interrupts the first time)
+     * and when HTC is finally ready to handle interrupts, other software can perform target "soft" resets.
+     * The AR6K interrupt enables reset back to an "enabled" state when this happens.
+     *  */
+    A_STATUS IntStatus = A_OK;
+    DevDisableInterrupts(pDev);
+
+#ifdef THREAD_X
+    // Tobe verified...
+    IntStatus = DevEnableInterrupts(pDev);
+    /* Unmask the host controller interrupts */
+    HIFUnMaskInterrupt(pDev->HIFDevice);
+#else
+    /* Unmask the host controller interrupts */
+    HIFUnMaskInterrupt(pDev->HIFDevice);
+    IntStatus = DevEnableInterrupts(pDev);
+#endif
+
+    return IntStatus;
+}
+
+/* disable all device interrupts */
+A_STATUS DevMaskInterrupts(AR6K_DEVICE *pDev)
+{
+        /* mask the interrupt at the HIF layer, we don't want a stray interrupt taken while
+         * we zero out our shadow registers in DevDisableInterrupts()*/
+    HIFMaskInterrupt(pDev->HIFDevice);
+
+    return DevDisableInterrupts(pDev);
+}
+
+/* callback when our fetch to enable/disable completes */
+static void DevDoEnableDisableRecvAsyncHandler(void *Context, HTC_PACKET *pPacket)
+{
+    AR6K_DEVICE *pDev = (AR6K_DEVICE *)Context;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevDoEnableDisableRecvAsyncHandler: (dev: 0x%lX)\n", (unsigned long)pDev));
+
+    if (A_FAILED(pPacket->Status)) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                (" Failed to disable receiver, status:%d \n", pPacket->Status));
+    }
+        /* free this IO packet */
+    AR6KFreeIOPacket(pDev,pPacket);
+    AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevDoEnableDisableRecvAsyncHandler \n"));
+}
+
+/* disable packet reception (used in case the host runs out of buffers)
+ * this is the "override" method when the HIF reports another methods to
+ * disable recv events */
+static A_STATUS DevDoEnableDisableRecvOverride(AR6K_DEVICE *pDev, A_BOOL EnableRecv, A_BOOL AsyncMode)
+{
+    A_STATUS                  status = A_OK;
+    HTC_PACKET                *pIOPacket = NULL;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("DevDoEnableDisableRecvOverride: Enable:%d Mode:%d\n",
+            EnableRecv,AsyncMode));
+
+    do {
+
+        if (AsyncMode) {
+
+            pIOPacket = AR6KAllocIOPacket(pDev);
+
+            if (NULL == pIOPacket) {
+                status = A_NO_MEMORY;
+                A_ASSERT(FALSE);
+                break;
+            }
+
+                /* stick in our completion routine when the I/O operation completes */
+            pIOPacket->Completion = DevDoEnableDisableRecvAsyncHandler;
+            pIOPacket->pContext = pDev;
+
+                /* call the HIF layer override and do this asynchronously */
+            status = pDev->HifMaskUmaskRecvEvent(pDev->HIFDevice,
+                                                 EnableRecv ? HIF_UNMASK_RECV : HIF_MASK_RECV,
+                                                 pIOPacket);
+            break;
+        }
+
+            /* if we get here we are doing it synchronously */
+        status = pDev->HifMaskUmaskRecvEvent(pDev->HIFDevice,
+                                             EnableRecv ? HIF_UNMASK_RECV : HIF_MASK_RECV,
+                                             NULL);
+
+    } while (FALSE);
+
+    if (A_FAILED(status) && (pIOPacket != NULL)) {
+        AR6KFreeIOPacket(pDev,pIOPacket);
+    }
+
+    return status;
+}
+
+/* disable packet reception (used in case the host runs out of buffers)
+ * this is the "normal" method using the interrupt enable registers through
+ * the host I/F */
+static A_STATUS DevDoEnableDisableRecvNormal(AR6K_DEVICE *pDev, A_BOOL EnableRecv, A_BOOL AsyncMode)
+{
+    A_STATUS                  status = A_OK;
+    HTC_PACKET                *pIOPacket = NULL;
+    AR6K_IRQ_ENABLE_REGISTERS regs;
+
+        /* take the lock to protect interrupt enable shadows */
+    LOCK_AR6K(pDev);
+
+    if (EnableRecv) {
+        pDev->IrqEnableRegisters.int_status_enable |= INT_STATUS_ENABLE_MBOX_DATA_SET(0x01);
+    } else {
+        pDev->IrqEnableRegisters.int_status_enable &= ~INT_STATUS_ENABLE_MBOX_DATA_SET(0x01);
+    }
+
+        /* copy into our temp area */
+    A_MEMCPY(&regs,&pDev->IrqEnableRegisters,AR6K_IRQ_ENABLE_REGS_SIZE);
+    UNLOCK_AR6K(pDev);
+
+    do {
+
+        if (AsyncMode) {
+
+            pIOPacket = AR6KAllocIOPacket(pDev);
+
+            if (NULL == pIOPacket) {
+                status = A_NO_MEMORY;
+                A_ASSERT(FALSE);
+                break;
+            }
+
+                /* copy values to write to our async I/O buffer */
+            A_MEMCPY(pIOPacket->pBuffer,&regs,AR6K_IRQ_ENABLE_REGS_SIZE);
+
+                /* stick in our completion routine when the I/O operation completes */
+            pIOPacket->Completion = DevDoEnableDisableRecvAsyncHandler;
+            pIOPacket->pContext = pDev;
+
+                /* write it out asynchronously */
+            HIFReadWrite(pDev->HIFDevice,
+                         INT_STATUS_ENABLE_ADDRESS,
+                         pIOPacket->pBuffer,
+                         AR6K_IRQ_ENABLE_REGS_SIZE,
+                         HIF_WR_ASYNC_BYTE_INC,
+                         pIOPacket);
+            break;
+        }
+
+        /* if we get here we are doing it synchronously */
+
+        status = HIFReadWrite(pDev->HIFDevice,
+                              INT_STATUS_ENABLE_ADDRESS,
+                              &regs.int_status_enable,
+                              AR6K_IRQ_ENABLE_REGS_SIZE,
+                              HIF_WR_SYNC_BYTE_INC,
+                              NULL);
+
+    } while (FALSE);
+
+    if (A_FAILED(status) && (pIOPacket != NULL)) {
+        AR6KFreeIOPacket(pDev,pIOPacket);
+    }
+
+    return status;
+}
+
+
+A_STATUS DevStopRecv(AR6K_DEVICE *pDev, A_BOOL AsyncMode)
+{
+    if (NULL == pDev->HifMaskUmaskRecvEvent) {
+        return DevDoEnableDisableRecvNormal(pDev,FALSE,AsyncMode);
+    } else {
+        return DevDoEnableDisableRecvOverride(pDev,FALSE,AsyncMode);
+    }
+}
+
+A_STATUS DevEnableRecv(AR6K_DEVICE *pDev, A_BOOL AsyncMode)
+{
+    if (NULL == pDev->HifMaskUmaskRecvEvent) {
+        return DevDoEnableDisableRecvNormal(pDev,TRUE,AsyncMode);
+    } else {
+        return DevDoEnableDisableRecvOverride(pDev,TRUE,AsyncMode);
+    }
+}
+
+A_STATUS DevWaitForPendingRecv(AR6K_DEVICE *pDev,A_UINT32 TimeoutInMs,A_BOOL *pbIsRecvPending)
+{
+    A_STATUS    status          = A_OK;
+    A_UCHAR     host_int_status = 0x0;
+    A_UINT32    counter         = 0x0;
+
+    if(TimeoutInMs < 100)
+    {
+        TimeoutInMs = 100;
+    }
+
+    counter = TimeoutInMs / 100;
+
+    do
+    {
+        //Read the Host Interrupt Status Register
+        status = HIFReadWrite(pDev->HIFDevice,
+                              HOST_INT_STATUS_ADDRESS,
+                             &host_int_status,
+                              sizeof(A_UCHAR),
+                              HIF_RD_SYNC_BYTE_INC,
+                              NULL);
+        if(A_FAILED(status))
+        {
+            AR_DEBUG_PRINTF(ATH_LOG_ERR,("DevWaitForPendingRecv:Read HOST_INT_STATUS_ADDRESS Failed 0x%X\n",status));
+            break;
+        }
+
+        host_int_status = A_SUCCESS(status) ? (host_int_status & (1 << 0)):0;
+        if(!host_int_status)
+        {
+            status          = A_OK;
+           *pbIsRecvPending = FALSE;
+            break;
+        }
+        else
+        {
+            *pbIsRecvPending = TRUE;
+        }
+
+        A_MDELAY(100);
+
+        counter--;
+
+    }while(counter);
+    return status;
+}
+
+void DevDumpRegisters(AR6K_DEVICE               *pDev,
+                      AR6K_IRQ_PROC_REGISTERS   *pIrqProcRegs,
+                      AR6K_IRQ_ENABLE_REGISTERS *pIrqEnableRegs)
+{
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_ANY, ("\n<------- Register Table -------->\n"));
+
+    if (pIrqProcRegs != NULL) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
+            ("Host Int Status:           0x%x\n",pIrqProcRegs->host_int_status));
+        AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
+            ("CPU Int Status:            0x%x\n",pIrqProcRegs->cpu_int_status));
+        AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
+            ("Error Int Status:          0x%x\n",pIrqProcRegs->error_int_status));
+        AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
+            ("Counter Int Status:        0x%x\n",pIrqProcRegs->counter_int_status));
+        AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
+            ("Mbox Frame:                0x%x\n",pIrqProcRegs->mbox_frame));
+        AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
+            ("Rx Lookahead Valid:        0x%x\n",pIrqProcRegs->rx_lookahead_valid));
+        AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
+            ("Rx Lookahead 0:            0x%x\n",pIrqProcRegs->rx_lookahead[0]));
+        AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
+            ("Rx Lookahead 1:            0x%x\n",pIrqProcRegs->rx_lookahead[1]));
+
+        if (pDev->MailBoxInfo.GMboxAddress != 0) {
+                /* if the target supports GMBOX hardware, dump some additional state */
+            AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
+                ("GMBOX Host Int Status 2:   0x%x\n",pIrqProcRegs->host_int_status2));
+            AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
+                ("GMBOX RX Avail:            0x%x\n",pIrqProcRegs->gmbox_rx_avail));
+            AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
+                ("GMBOX lookahead alias 0:   0x%x\n",pIrqProcRegs->rx_gmbox_lookahead_alias[0]));
+            AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
+                ("GMBOX lookahead alias 1:   0x%x\n",pIrqProcRegs->rx_gmbox_lookahead_alias[1]));
+        }
+
+    }
+
+    if (pIrqEnableRegs != NULL) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
+            ("Int Status Enable:         0x%x\n",pIrqEnableRegs->int_status_enable));
+        AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
+            ("Counter Int Status Enable: 0x%x\n",pIrqEnableRegs->counter_int_status_enable));
+    }
+    AR_DEBUG_PRINTF(ATH_DEBUG_ANY, ("<------------------------------->\n"));
+}
+
+
+#define DEV_GET_VIRT_DMA_INFO(p)  ((DEV_SCATTER_DMA_VIRTUAL_INFO *)((p)->HIFPrivate[0]))
+
+static HIF_SCATTER_REQ *DevAllocScatterReq(HIF_DEVICE *Context)
+{
+    DL_LIST *pItem;
+    AR6K_DEVICE *pDev = (AR6K_DEVICE *)Context;
+    LOCK_AR6K(pDev);
+    pItem = DL_ListRemoveItemFromHead(&pDev->ScatterReqHead);
+    UNLOCK_AR6K(pDev);
+    if (pItem != NULL) {
+        return A_CONTAINING_STRUCT(pItem, HIF_SCATTER_REQ, ListLink);
+    }
+    return NULL;
+}
+
+static void DevFreeScatterReq(HIF_DEVICE *Context, HIF_SCATTER_REQ *pReq)
+{
+    AR6K_DEVICE *pDev = (AR6K_DEVICE *)Context;
+    LOCK_AR6K(pDev);
+    DL_ListInsertTail(&pDev->ScatterReqHead, &pReq->ListLink);
+    UNLOCK_AR6K(pDev);
+}
+
+A_STATUS DevCopyScatterListToFromDMABuffer(HIF_SCATTER_REQ *pReq, A_BOOL FromDMA)
+{
+    A_UINT8         *pDMABuffer = NULL;
+    int             i, remaining;
+    A_UINT32        length;
+
+    pDMABuffer = pReq->pScatterBounceBuffer;
+
+    if (pDMABuffer == NULL) {
+        A_ASSERT(FALSE);
+        return A_EINVAL;
+    }
+
+    remaining = (int)pReq->TotalLength;
+
+    for (i = 0; i < pReq->ValidScatterEntries; i++) {
+
+        length = min((int)pReq->ScatterList[i].Length, remaining);
+
+        if (length != (int)pReq->ScatterList[i].Length) {
+            A_ASSERT(FALSE);
+                /* there is a problem with the scatter list */
+            return A_EINVAL;
+        }
+
+        if (FromDMA) {
+                /* from DMA buffer */
+            A_MEMCPY(pReq->ScatterList[i].pBuffer, pDMABuffer , length);
+        } else {
+                /* to DMA buffer */
+            A_MEMCPY(pDMABuffer, pReq->ScatterList[i].pBuffer, length);
+        }
+
+        pDMABuffer += length;
+        remaining -= length;
+    }
+
+    return A_OK;
+}
+
+static void DevReadWriteScatterAsyncHandler(void *Context, HTC_PACKET *pPacket)
+{
+    AR6K_DEVICE     *pDev = (AR6K_DEVICE *)Context;
+    HIF_SCATTER_REQ *pReq = (HIF_SCATTER_REQ *)pPacket->pPktContext;
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("+DevReadWriteScatterAsyncHandler: (dev: 0x%lX)\n", (unsigned long)pDev));
+    
+    pReq->CompletionStatus = pPacket->Status;
+
+    AR6KFreeIOPacket(pDev,pPacket);
+
+    pReq->CompletionRoutine(pReq);
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("-DevReadWriteScatterAsyncHandler \n"));
+}
+
+static A_STATUS DevReadWriteScatter(HIF_DEVICE *Context, HIF_SCATTER_REQ *pReq)
+{
+    AR6K_DEVICE     *pDev = (AR6K_DEVICE *)Context;
+    A_STATUS        status = A_OK;
+    HTC_PACKET      *pIOPacket = NULL;
+    A_UINT32        request = pReq->Request;
+
+    do {
+
+        if (pReq->TotalLength > AR6K_MAX_TRANSFER_SIZE_PER_SCATTER) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                            ("Invalid length: %d \n", pReq->TotalLength));
+            break;
+        }
+
+        if (pReq->TotalLength == 0) {
+            A_ASSERT(FALSE);
+            break;
+        }
+
+        if (request & HIF_ASYNCHRONOUS) {
+                /* use an I/O packet to carry this request */
+            pIOPacket = AR6KAllocIOPacket(pDev);
+            if (NULL == pIOPacket) {
+                status = A_NO_MEMORY;
+                break;
+            }
+
+                /* save the request */
+            pIOPacket->pPktContext = pReq;
+                /* stick in our completion routine when the I/O operation completes */
+            pIOPacket->Completion = DevReadWriteScatterAsyncHandler;
+            pIOPacket->pContext = pDev;
+        }
+
+        if (request & HIF_WRITE) {
+            /* in virtual DMA, we are issuing the requests through the legacy HIFReadWrite API
+             * this API will adjust the address automatically for the last byte to fall on the mailbox
+             * EOM. */
+
+            /* if the address is an extended address, we can adjust the address here since the extended
+             * address will bypass the normal checks in legacy HIF layers */
+            if (pReq->Address == pDev->MailBoxInfo.MboxProp[HTC_MAILBOX].ExtendedAddress) {
+                pReq->Address += pDev->MailBoxInfo.MboxProp[HTC_MAILBOX].ExtendedSize - pReq->TotalLength;
+            }
+        }
+
+            /* use legacy readwrite */
+        status = HIFReadWrite(pDev->HIFDevice,
+                              pReq->Address,
+                              DEV_GET_VIRT_DMA_INFO(pReq)->pVirtDmaBuffer,
+                              pReq->TotalLength,
+                              request,
+                              (request & HIF_ASYNCHRONOUS) ? pIOPacket : NULL);
+
+    } while (FALSE);
+
+    if ((status != A_PENDING) && A_FAILED(status) && (request & HIF_ASYNCHRONOUS)) {
+        if (pIOPacket != NULL) {
+            AR6KFreeIOPacket(pDev,pIOPacket);
+        }
+        pReq->CompletionStatus = status;
+        pReq->CompletionRoutine(pReq);
+        status = A_OK;
+    }
+
+    return status;
+}
+
+
+static void DevCleanupVirtualScatterSupport(AR6K_DEVICE *pDev)
+{
+    HIF_SCATTER_REQ *pReq;
+
+    while (1) {
+        pReq = DevAllocScatterReq((HIF_DEVICE *)pDev);
+        if (NULL == pReq) {
+            break;
+        }
+        A_FREE(pReq);
+    }
+
+}
+
+    /* function to set up virtual scatter support if HIF layer has not implemented the interface */
+static A_STATUS DevSetupVirtualScatterSupport(AR6K_DEVICE *pDev)
+{
+    A_STATUS                     status = A_OK;
+    int                          bufferSize, sgreqSize;
+    int                          i;
+    DEV_SCATTER_DMA_VIRTUAL_INFO *pVirtualInfo;
+    HIF_SCATTER_REQ              *pReq;
+
+    bufferSize = sizeof(DEV_SCATTER_DMA_VIRTUAL_INFO) +
+                2 * (A_GET_CACHE_LINE_BYTES()) + AR6K_MAX_TRANSFER_SIZE_PER_SCATTER;
+
+    sgreqSize = sizeof(HIF_SCATTER_REQ) +
+                    (AR6K_SCATTER_ENTRIES_PER_REQ - 1) * (sizeof(HIF_SCATTER_ITEM));
+
+    for (i = 0; i < AR6K_SCATTER_REQS; i++) {
+            /* allocate the scatter request, buffer info and the actual virtual buffer itself */
+        pReq = (HIF_SCATTER_REQ *)A_MALLOC(sgreqSize + bufferSize);
+
+        if (NULL == pReq) {
+            status = A_NO_MEMORY;
+            break;
+        }
+
+        A_MEMZERO(pReq, sgreqSize);
+
+            /* the virtual DMA starts after the scatter request struct */
+        pVirtualInfo = (DEV_SCATTER_DMA_VIRTUAL_INFO *)((A_UINT8 *)pReq + sgreqSize);
+        A_MEMZERO(pVirtualInfo, sizeof(DEV_SCATTER_DMA_VIRTUAL_INFO));
+
+        pVirtualInfo->pVirtDmaBuffer = &pVirtualInfo->DataArea[0];
+            /* align buffer to cache line in case host controller can actually DMA this */
+        pVirtualInfo->pVirtDmaBuffer = A_ALIGN_TO_CACHE_LINE(pVirtualInfo->pVirtDmaBuffer);
+            /* store the structure in the private area */
+        pReq->HIFPrivate[0] = pVirtualInfo;
+            /* we emulate a DMA bounce interface */
+        pReq->ScatterMethod = HIF_SCATTER_DMA_BOUNCE;
+        pReq->pScatterBounceBuffer = pVirtualInfo->pVirtDmaBuffer;
+            /* free request to the list */
+        DevFreeScatterReq((HIF_DEVICE *)pDev,pReq);
+    }
+
+    if (A_FAILED(status)) {
+        DevCleanupVirtualScatterSupport(pDev);
+    } else {
+        pDev->HifScatterInfo.pAllocateReqFunc = DevAllocScatterReq;
+        pDev->HifScatterInfo.pFreeReqFunc = DevFreeScatterReq;
+        pDev->HifScatterInfo.pReadWriteScatterFunc = DevReadWriteScatter;
+        if (pDev->MailBoxInfo.MboxBusIFType == MBOX_BUS_IF_SPI) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_WARN, ("AR6K: SPI bus requires RX scatter limits\n"));
+            pDev->HifScatterInfo.MaxScatterEntries = AR6K_MIN_SCATTER_ENTRIES_PER_REQ;
+            pDev->HifScatterInfo.MaxTransferSizePerScatterReq = AR6K_MIN_TRANSFER_SIZE_PER_SCATTER;
+        } else {
+            pDev->HifScatterInfo.MaxScatterEntries = AR6K_SCATTER_ENTRIES_PER_REQ;
+            pDev->HifScatterInfo.MaxTransferSizePerScatterReq = AR6K_MAX_TRANSFER_SIZE_PER_SCATTER;
+        }
+        pDev->ScatterIsVirtual = TRUE;
+    }
+
+    return status;
+}
+
+
+A_STATUS DevSetupMsgBundling(AR6K_DEVICE *pDev, int MaxMsgsPerTransfer)
+{
+    A_STATUS status;
+
+    if (pDev->MailBoxInfo.Flags & HIF_MBOX_FLAG_NO_BUNDLING) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_WARN, ("HIF requires bundling disabled\n"));
+        return A_ENOTSUP;
+    }
+
+    status = HIFConfigureDevice(pDev->HIFDevice,
+                                HIF_CONFIGURE_QUERY_SCATTER_REQUEST_SUPPORT,
+                                &pDev->HifScatterInfo,
+                                sizeof(pDev->HifScatterInfo));
+
+    if (A_FAILED(status)) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_WARN,
+            ("AR6K: ** HIF layer does not support scatter requests (%d) \n",status));
+
+            /* we can try to use a virtual DMA scatter mechanism using legacy HIFReadWrite() */
+        status = DevSetupVirtualScatterSupport(pDev);
+
+        if (A_SUCCESS(status)) {
+             AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
+                ("AR6K: virtual scatter transfers enabled (max scatter items:%d: maxlen:%d) \n",
+                    DEV_GET_MAX_MSG_PER_BUNDLE(pDev), DEV_GET_MAX_BUNDLE_LENGTH(pDev)));
+        }
+
+    } else {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
+            ("AR6K: HIF layer supports scatter requests (max scatter items:%d: maxlen:%d) \n",
+                    DEV_GET_MAX_MSG_PER_BUNDLE(pDev), DEV_GET_MAX_BUNDLE_LENGTH(pDev)));
+    }
+
+    if (A_SUCCESS(status)) {
+            /* for the recv path, the maximum number of bytes per recv bundle is just limited
+             * by the maximum transfer size at the HIF layer */
+        pDev->MaxRecvBundleSize = pDev->HifScatterInfo.MaxTransferSizePerScatterReq;
+
+        if (pDev->MailBoxInfo.MboxBusIFType == MBOX_BUS_IF_SPI) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_WARN, ("AR6K : SPI bus requires TX bundling disabled\n"));
+            pDev->MaxSendBundleSize = 0;
+        } else {
+                /* for the send path, the max transfer size is limited by the existence and size of
+                 * the extended mailbox address range */
+            if (pDev->MailBoxInfo.MboxProp[0].ExtendedAddress != 0) {
+                pDev->MaxSendBundleSize = pDev->MailBoxInfo.MboxProp[0].ExtendedSize;
+            } else {
+                    /* legacy */
+                pDev->MaxSendBundleSize = AR6K_LEGACY_MAX_WRITE_LENGTH;
+            }
+
+            if (pDev->MaxSendBundleSize > pDev->HifScatterInfo.MaxTransferSizePerScatterReq) {
+                    /* limit send bundle size to what the HIF can support for scatter requests */
+                pDev->MaxSendBundleSize = pDev->HifScatterInfo.MaxTransferSizePerScatterReq;
+            }
+        }
+
+        AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
+            ("AR6K: max recv: %d max send: %d \n",
+                    DEV_GET_MAX_BUNDLE_RECV_LENGTH(pDev), DEV_GET_MAX_BUNDLE_SEND_LENGTH(pDev)));
+
+    }
+    return status;
+}
+
+A_STATUS DevSubmitScatterRequest(AR6K_DEVICE *pDev, HIF_SCATTER_REQ *pScatterReq, A_BOOL Read, A_BOOL Async)
+{
+    A_STATUS status;
+
+    if (Read) {
+            /* read operation */
+        pScatterReq->Request = (Async) ? HIF_RD_ASYNC_BLOCK_FIX : HIF_RD_SYNC_BLOCK_FIX;
+        pScatterReq->Address = pDev->MailBoxInfo.MboxAddresses[HTC_MAILBOX];
+        A_ASSERT(pScatterReq->TotalLength <= (A_UINT32)DEV_GET_MAX_BUNDLE_RECV_LENGTH(pDev));
+    } else {
+        A_UINT32 mailboxWidth;
+
+            /* write operation */
+        pScatterReq->Request = (Async) ? HIF_WR_ASYNC_BLOCK_INC : HIF_WR_SYNC_BLOCK_INC;
+        A_ASSERT(pScatterReq->TotalLength <= (A_UINT32)DEV_GET_MAX_BUNDLE_SEND_LENGTH(pDev));
+        if (pScatterReq->TotalLength > AR6K_LEGACY_MAX_WRITE_LENGTH) {
+                /* for large writes use the extended address */
+            pScatterReq->Address = pDev->MailBoxInfo.MboxProp[HTC_MAILBOX].ExtendedAddress;
+            mailboxWidth = pDev->MailBoxInfo.MboxProp[HTC_MAILBOX].ExtendedSize;
+        } else {
+            pScatterReq->Address = pDev->MailBoxInfo.MboxAddresses[HTC_MAILBOX];
+            mailboxWidth = AR6K_LEGACY_MAX_WRITE_LENGTH;
+        }
+
+        if (!pDev->ScatterIsVirtual) {
+            /* we are passing this scatter list down to the HIF layer' scatter request handler, fixup the address
+             * so that the last byte falls on the EOM, we do this for those HIFs that support the
+             * scatter API */
+            pScatterReq->Address += (mailboxWidth - pScatterReq->TotalLength);
+        }
+
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_RECV | ATH_DEBUG_SEND,
+                ("DevSubmitScatterRequest, Entries: %d, Total Length: %d Mbox:0x%X (mode: %s : %s)\n",
+                pScatterReq->ValidScatterEntries,
+                pScatterReq->TotalLength,
+                pScatterReq->Address,
+                Async ? "ASYNC" : "SYNC",
+                (Read) ? "RD" : "WR"));
+
+    status = DEV_PREPARE_SCATTER_OPERATION(pScatterReq);
+
+    if (A_FAILED(status)) {
+        if (Async) {
+            pScatterReq->CompletionStatus = status;
+            pScatterReq->CompletionRoutine(pScatterReq);
+            return A_OK;
+        }
+        return status;
+    }
+
+    status = pDev->HifScatterInfo.pReadWriteScatterFunc(pDev->ScatterIsVirtual ? pDev : pDev->HIFDevice,
+                                                        pScatterReq);
+    if (!Async) {
+            /* in sync mode, we can touch the scatter request */
+        pScatterReq->CompletionStatus = status;
+        DEV_FINISH_SCATTER_OPERATION(pScatterReq);
+    } else {
+        if (status == A_PENDING) {
+            status = A_OK;
+        }
+    }
+
+    return status;
+}
+
+
+#ifdef MBOXHW_UNIT_TEST
+
+
+/* This is a mailbox hardware unit test that must be called in a schedulable context
+ * This test is very simple, it will send a list of buffers with a counting pattern
+ * and the target will invert the data and send the message back
+ *
+ * the unit test has the following constraints:
+ *
+ * The target has at least 8 buffers of 256 bytes each. The host will send
+ * the following pattern of buffers in rapid succession :
+ *
+ * 1 buffer - 128 bytes
+ * 1 buffer - 256 bytes
+ * 1 buffer - 512 bytes
+ * 1 buffer - 1024 bytes
+ *
+ * The host will send the buffers to one mailbox and wait for buffers to be reflected
+ * back from the same mailbox. The target sends the buffers FIFO order.
+ * Once the final buffer has been received for a mailbox, the next mailbox is tested.
+ *
+ *
+ * Note:  To simplifythe test , we assume that the chosen buffer sizes
+ *        will fall on a nice block pad
+ *
+ * It is expected that higher-order tests will be written to stress the mailboxes using
+ * a message-based protocol (with some performance timming) that can create more
+ * randomness in the packets sent over mailboxes.
+ *
+ * */
+
+#define A_ROUND_UP_PWR2(x, align)    (((int) (x) + ((align)-1)) & ~((align)-1))
+
+#define BUFFER_BLOCK_PAD 128
+
+#if 0
+#define BUFFER1 128
+#define BUFFER2 256
+#define BUFFER3 512
+#define BUFFER4 1024
+#endif
+
+#if 1
+#define BUFFER1 80
+#define BUFFER2 200
+#define BUFFER3 444
+#define BUFFER4 800
+#endif
+
+#define TOTAL_BYTES (A_ROUND_UP_PWR2(BUFFER1,BUFFER_BLOCK_PAD) + \
+                     A_ROUND_UP_PWR2(BUFFER2,BUFFER_BLOCK_PAD) + \
+                     A_ROUND_UP_PWR2(BUFFER3,BUFFER_BLOCK_PAD) + \
+                     A_ROUND_UP_PWR2(BUFFER4,BUFFER_BLOCK_PAD) )
+
+#define TEST_BYTES (BUFFER1 +  BUFFER2 + BUFFER3 + BUFFER4)
+
+#define TEST_CREDITS_RECV_TIMEOUT 100
+
+static A_UINT8  g_Buffer[TOTAL_BYTES];
+static A_UINT32 g_MailboxAddrs[AR6K_MAILBOXES];
+static A_UINT32 g_BlockSizes[AR6K_MAILBOXES];
+
+#define BUFFER_PROC_LIST_DEPTH 4
+
+typedef struct _BUFFER_PROC_LIST{
+    A_UINT8  *pBuffer;
+    A_UINT32 length;
+}BUFFER_PROC_LIST;
+
+
+#define PUSH_BUFF_PROC_ENTRY(pList,len,pCurrpos) \
+{                                                   \
+    (pList)->pBuffer = (pCurrpos);                  \
+    (pList)->length = (len);                        \
+    (pCurrpos) += (len);                            \
+    (pList)++;                                      \
+}
+
+/* a simple and crude way to send different "message" sizes */
+static void AssembleBufferList(BUFFER_PROC_LIST *pList)
+{
+    A_UINT8 *pBuffer = g_Buffer;
+
+#if BUFFER_PROC_LIST_DEPTH < 4
+#error "Buffer processing list depth is not deep enough!!"
+#endif
+
+    PUSH_BUFF_PROC_ENTRY(pList,BUFFER1,pBuffer);
+    PUSH_BUFF_PROC_ENTRY(pList,BUFFER2,pBuffer);
+    PUSH_BUFF_PROC_ENTRY(pList,BUFFER3,pBuffer);
+    PUSH_BUFF_PROC_ENTRY(pList,BUFFER4,pBuffer);
+
+}
+
+#define FILL_ZERO     TRUE
+#define FILL_COUNTING FALSE
+static void InitBuffers(A_BOOL Zero)
+{
+    A_UINT16 *pBuffer16 = (A_UINT16 *)g_Buffer;
+    int      i;
+
+        /* fill buffer with 16 bit counting pattern or zeros */
+    for (i = 0; i <  (TOTAL_BYTES / 2) ; i++) {
+        if (!Zero) {
+            pBuffer16[i] = (A_UINT16)i;
+        } else {
+            pBuffer16[i] = 0;
+        }
+    }
+}
+
+
+static A_BOOL CheckOneBuffer(A_UINT16 *pBuffer16, int Length)
+{
+    int      i;
+    A_UINT16 startCount;
+    A_BOOL   success = TRUE;
+
+        /* get the starting count */
+    startCount = pBuffer16[0];
+        /* invert it, this is the expected value */
+    startCount = ~startCount;
+        /* scan the buffer and verify */
+    for (i = 0; i < (Length / 2) ; i++,startCount++) {
+            /* target will invert all the data */
+        if ((A_UINT16)pBuffer16[i] != (A_UINT16)~startCount) {
+            success = FALSE;
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Invalid Data Got:0x%X, Expecting:0x%X (offset:%d, total:%d) \n",
+                        pBuffer16[i], ((A_UINT16)~startCount), i, Length));
+             AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("0x%X 0x%X 0x%X 0x%X \n",
+                        pBuffer16[i], pBuffer16[i + 1], pBuffer16[i + 2],pBuffer16[i+3]));
+            break;
+        }
+    }
+
+    return success;
+}
+
+static A_BOOL CheckBuffers(void)
+{
+    int      i;
+    A_BOOL   success = TRUE;
+    BUFFER_PROC_LIST checkList[BUFFER_PROC_LIST_DEPTH];
+
+        /* assemble the list */
+    AssembleBufferList(checkList);
+
+        /* scan the buffers and verify */
+    for (i = 0; i < BUFFER_PROC_LIST_DEPTH ; i++) {
+        success = CheckOneBuffer((A_UINT16 *)checkList[i].pBuffer, checkList[i].length);
+        if (!success) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Buffer : 0x%X, Length:%d failed verify \n",
+                        (A_UINT32)checkList[i].pBuffer, checkList[i].length));
+            break;
+        }
+    }
+
+    return success;
+}
+
+    /* find the end marker for the last buffer we will be sending */
+static A_UINT16 GetEndMarker(void)
+{
+    A_UINT8  *pBuffer;
+    BUFFER_PROC_LIST checkList[BUFFER_PROC_LIST_DEPTH];
+
+        /* fill up buffers with the normal counting pattern */
+    InitBuffers(FILL_COUNTING);
+
+        /* assemble the list we will be sending down */
+    AssembleBufferList(checkList);
+        /* point to the last 2 bytes of the last buffer */
+    pBuffer = &(checkList[BUFFER_PROC_LIST_DEPTH - 1].pBuffer[(checkList[BUFFER_PROC_LIST_DEPTH - 1].length) - 2]);
+
+        /* the last count in the last buffer is the marker */
+    return (A_UINT16)pBuffer[0] | ((A_UINT16)pBuffer[1] << 8);
+}
+
+#define ATH_PRINT_OUT_ZONE ATH_DEBUG_ERR
+
+/* send the ordered buffers to the target */
+static A_STATUS SendBuffers(AR6K_DEVICE *pDev, int mbox)
+{
+    A_STATUS         status = A_OK;
+    A_UINT32         request = HIF_WR_SYNC_BLOCK_INC;
+    BUFFER_PROC_LIST sendList[BUFFER_PROC_LIST_DEPTH];
+    int              i;
+    int              totalBytes = 0;
+    int              paddedLength;
+    int              totalwPadding = 0;
+
+    AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Sending buffers on mailbox : %d \n",mbox));
+
+        /* fill buffer with counting pattern */
+    InitBuffers(FILL_COUNTING);
+
+        /* assemble the order in which we send */
+    AssembleBufferList(sendList);
+
+    for (i = 0; i < BUFFER_PROC_LIST_DEPTH; i++) {
+
+            /* we are doing block transfers, so we need to pad everything to a block size */
+        paddedLength = (sendList[i].length + (g_BlockSizes[mbox] - 1)) &
+                       (~(g_BlockSizes[mbox] - 1));
+
+            /* send each buffer synchronously */
+        status = HIFReadWrite(pDev->HIFDevice,
+                              g_MailboxAddrs[mbox],
+                              sendList[i].pBuffer,
+                              paddedLength,
+                              request,
+                              NULL);
+        if (status != A_OK) {
+            break;
+        }
+        totalBytes += sendList[i].length;
+        totalwPadding += paddedLength;
+    }
+
+    AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Sent %d bytes (%d padded bytes) to mailbox : %d \n",totalBytes,totalwPadding,mbox));
+
+    return status;
+}
+
+/* poll the mailbox credit counter until we get a credit or timeout */
+static A_STATUS GetCredits(AR6K_DEVICE *pDev, int mbox, int *pCredits)
+{
+    A_STATUS status = A_OK;
+    int      timeout = TEST_CREDITS_RECV_TIMEOUT;
+    A_UINT8  credits = 0;
+    A_UINT32 address;
+
+    while (TRUE) {
+
+            /* Read the counter register to get credits, this auto-decrements  */
+        address = COUNT_DEC_ADDRESS + (AR6K_MAILBOXES + mbox) * 4;
+        status = HIFReadWrite(pDev->HIFDevice, address, &credits, sizeof(credits),
+                              HIF_RD_SYNC_BYTE_FIX, NULL);
+        if (status != A_OK) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                ("Unable to decrement the command credit count register (mbox=%d)\n",mbox));
+            status = A_ERROR;
+            break;
+        }
+
+        if (credits) {
+            break;
+        }
+
+        timeout--;
+
+        if (timeout <= 0) {
+              AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                (" Timeout reading credit registers (mbox=%d, address:0x%X) \n",mbox,address));
+            status = A_ERROR;
+            break;
+        }
+
+         /* delay a little, target may not be ready */
+         A_MDELAY(1000);
+
+    }
+
+    if (status == A_OK) {
+        *pCredits = credits;
+    }
+
+    return status;
+}
+
+
+/* wait for the buffers to come back */
+static A_STATUS RecvBuffers(AR6K_DEVICE *pDev, int mbox)
+{
+    A_STATUS         status = A_OK;
+    A_UINT32         request = HIF_RD_SYNC_BLOCK_INC;
+    BUFFER_PROC_LIST recvList[BUFFER_PROC_LIST_DEPTH];
+    int              curBuffer;
+    int              credits;
+    int              i;
+    int              totalBytes = 0;
+    int              paddedLength;
+    int              totalwPadding = 0;
+
+    AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Waiting for buffers on mailbox : %d \n",mbox));
+
+        /* zero the buffers */
+    InitBuffers(FILL_ZERO);
+
+        /* assemble the order in which we should receive */
+    AssembleBufferList(recvList);
+
+    curBuffer = 0;
+
+    while (curBuffer < BUFFER_PROC_LIST_DEPTH) {
+
+            /* get number of buffers that have been completed, this blocks
+             * until we get at least 1 credit or it times out */
+        status = GetCredits(pDev, mbox, &credits);
+
+        if (status != A_OK) {
+            break;
+        }
+
+        AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Got %d messages on mailbox : %d \n",credits, mbox));
+
+            /* get all the buffers that are sitting on the queue */
+        for (i = 0; i < credits; i++) {
+            A_ASSERT(curBuffer < BUFFER_PROC_LIST_DEPTH);
+                /* recv the current buffer synchronously, the buffers should come back in
+                 * order... with padding applied by the target */
+            paddedLength = (recvList[curBuffer].length + (g_BlockSizes[mbox] - 1)) &
+                       (~(g_BlockSizes[mbox] - 1));
+
+            status = HIFReadWrite(pDev->HIFDevice,
+                                  g_MailboxAddrs[mbox],
+                                  recvList[curBuffer].pBuffer,
+                                  paddedLength,
+                                  request,
+                                  NULL);
+            if (status != A_OK) {
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to read %d bytes on mailbox:%d : address:0x%X \n",
+                        recvList[curBuffer].length, mbox, g_MailboxAddrs[mbox]));
+                break;
+            }
+
+            totalwPadding += paddedLength;
+            totalBytes += recvList[curBuffer].length;
+            curBuffer++;
+        }
+
+        if (status != A_OK) {
+            break;
+        }
+            /* go back and get some more */
+        credits = 0;
+    }
+
+    if (totalBytes != TEST_BYTES) {
+        A_ASSERT(FALSE);
+    }  else {
+        AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Got all buffers on mbox:%d total recv :%d (w/Padding : %d) \n",
+            mbox, totalBytes, totalwPadding));
+    }
+
+    return status;
+
+
+}
+
+static A_STATUS DoOneMboxHWTest(AR6K_DEVICE *pDev, int mbox)
+{
+    A_STATUS status;
+
+    do {
+            /* send out buffers */
+        status = SendBuffers(pDev,mbox);
+
+        if (status != A_OK) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Sending buffers Failed : %d mbox:%d\n",status,mbox));
+            break;
+        }
+
+            /* go get them, this will block */
+        status =  RecvBuffers(pDev, mbox);
+
+        if (status != A_OK) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Recv buffers Failed : %d mbox:%d\n",status,mbox));
+            break;
+        }
+
+            /* check the returned data patterns */
+        if (!CheckBuffers()) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Buffer Verify Failed : mbox:%d\n",mbox));
+            status = A_ERROR;
+            break;
+        }
+
+        AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, (" Send/Recv success! mailbox : %d \n",mbox));
+
+    }  while (FALSE);
+
+    return status;
+}
+
+/* here is where the test starts */
+A_STATUS DoMboxHWTest(AR6K_DEVICE *pDev)
+{
+    int      i;
+    A_STATUS status;
+    int      credits = 0;
+    A_UINT8  params[4];
+    int      numBufs;
+    int      bufferSize;
+    A_UINT16 temp;
+
+
+    AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, (" DoMboxHWTest START -  \n"));
+
+    do {
+            /* get the addresses for all 4 mailboxes */
+        status = HIFConfigureDevice(pDev->HIFDevice, HIF_DEVICE_GET_MBOX_ADDR,
+                                    g_MailboxAddrs, sizeof(g_MailboxAddrs));
+
+        if (status != A_OK) {
+            A_ASSERT(FALSE);
+            break;
+        }
+
+            /* get the block sizes */
+        status = HIFConfigureDevice(pDev->HIFDevice, HIF_DEVICE_GET_MBOX_BLOCK_SIZE,
+                                    g_BlockSizes, sizeof(g_BlockSizes));
+
+        if (status != A_OK) {
+            A_ASSERT(FALSE);
+            break;
+        }
+
+            /* note, the HIF layer usually reports mbox 0 to have a block size of
+             * 1, but our test wants to run in block-mode for all mailboxes, so we treat all mailboxes
+             * the same. */
+        g_BlockSizes[0] = g_BlockSizes[1];
+        AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Block Size to use: %d \n",g_BlockSizes[0]));
+
+        if (g_BlockSizes[1] > BUFFER_BLOCK_PAD) {
+            AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("%d Block size is too large for buffer pad %d\n",
+                g_BlockSizes[1], BUFFER_BLOCK_PAD));
+            break;
+        }
+
+        AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Waiting for target.... \n"));
+
+            /* the target lets us know it is ready by giving us 1 credit on
+             * mailbox 0 */
+        status = GetCredits(pDev, 0, &credits);
+
+        if (status != A_OK) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to wait for target ready \n"));
+            break;
+        }
+
+        AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Target is ready ...\n"));
+
+            /* read the first 4 scratch registers */
+        status = HIFReadWrite(pDev->HIFDevice,
+                              SCRATCH_ADDRESS,
+                              params,
+                              4,
+                              HIF_RD_SYNC_BYTE_INC,
+                              NULL);
+
+        if (status != A_OK) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to wait get parameters \n"));
+            break;
+        }
+
+        numBufs = params[0];
+        bufferSize = (int)(((A_UINT16)params[2] << 8) | (A_UINT16)params[1]);
+
+        AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE,
+            ("Target parameters: bufs per mailbox:%d, buffer size:%d bytes (total space: %d, minimum required space (w/padding): %d) \n",
+            numBufs, bufferSize, (numBufs * bufferSize), TOTAL_BYTES));
+
+        if ((numBufs * bufferSize) < TOTAL_BYTES) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Not Enough buffer space to run test! need:%d, got:%d \n",
+                TOTAL_BYTES, (numBufs*bufferSize)));
+            status = A_ERROR;
+            break;
+        }
+
+        temp = GetEndMarker();
+
+        status = HIFReadWrite(pDev->HIFDevice,
+                              SCRATCH_ADDRESS + 4,
+                              (A_UINT8 *)&temp,
+                              2,
+                              HIF_WR_SYNC_BYTE_INC,
+                              NULL);
+
+        if (status != A_OK) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to write end marker \n"));
+            break;
+        }
+
+        AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("End Marker: 0x%X \n",temp));
+
+        temp = (A_UINT16)g_BlockSizes[1];
+            /* convert to a mask */
+        temp = temp - 1;
+        status = HIFReadWrite(pDev->HIFDevice,
+                              SCRATCH_ADDRESS + 6,
+                              (A_UINT8 *)&temp,
+                              2,
+                              HIF_WR_SYNC_BYTE_INC,
+                              NULL);
+
+        if (status != A_OK) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to write block mask \n"));
+            break;
+        }
+
+        AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Set Block Mask: 0x%X \n",temp));
+
+            /* execute the test on each mailbox */
+        for (i = 0; i < AR6K_MAILBOXES; i++) {
+            status = DoOneMboxHWTest(pDev, i);
+            if (status != A_OK) {
+                break;
+            }
+        }
+
+    } while (FALSE);
+
+    if (status == A_OK) {
+        AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, (" DoMboxHWTest DONE - SUCCESS! -  \n"));
+    } else {
+        AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, (" DoMboxHWTest DONE - FAILED! -  \n"));
+    }
+        /* don't let HTC_Start continue, the target is actually not running any HTC code */
+    return A_ERROR;
+}
+#endif
+
+
+
diff --git a/drivers/net/ath6kl/htc2/AR6000/ar6k.h b/drivers/net/ath6kl/htc2/AR6000/ar6k.h
new file mode 100644
index 00000000000..b30fd877aeb
--- /dev/null
+++ b/drivers/net/ath6kl/htc2/AR6000/ar6k.h
@@ -0,0 +1,398 @@
+//------------------------------------------------------------------------------
+// <copyright file="ar6k.h" company="Atheros">
+//    Copyright (c) 2007-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// AR6K device layer that handles register level I/O
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef AR6K_H_
+#define AR6K_H_
+
+#include "hci_transport_api.h"
+#include "../htc_debug.h"
+
+#define AR6K_MAILBOXES 4
+
+/* HTC runs over mailbox 0 */
+#define HTC_MAILBOX          0
+
+#define AR6K_TARGET_DEBUG_INTR_MASK     0x01
+
+#define OTHER_INTS_ENABLED (INT_STATUS_ENABLE_ERROR_MASK |   \
+                            INT_STATUS_ENABLE_CPU_MASK   |   \
+                            INT_STATUS_ENABLE_COUNTER_MASK)
+
+
+//#define MBOXHW_UNIT_TEST 1
+
+#include "athstartpack.h"
+typedef PREPACK struct _AR6K_IRQ_PROC_REGISTERS {
+    A_UINT8                      host_int_status;
+    A_UINT8                      cpu_int_status;
+    A_UINT8                      error_int_status;
+    A_UINT8                      counter_int_status;
+    A_UINT8                      mbox_frame;
+    A_UINT8                      rx_lookahead_valid;
+    A_UINT8                      host_int_status2;
+    A_UINT8                      gmbox_rx_avail;
+    A_UINT32                     rx_lookahead[2];
+    A_UINT32                     rx_gmbox_lookahead_alias[2];
+} POSTPACK AR6K_IRQ_PROC_REGISTERS;
+
+#define AR6K_IRQ_PROC_REGS_SIZE sizeof(AR6K_IRQ_PROC_REGISTERS)
+
+typedef PREPACK struct _AR6K_IRQ_ENABLE_REGISTERS {
+    A_UINT8                      int_status_enable;
+    A_UINT8                      cpu_int_status_enable;
+    A_UINT8                      error_status_enable;
+    A_UINT8                      counter_int_status_enable;
+} POSTPACK AR6K_IRQ_ENABLE_REGISTERS;
+
+typedef PREPACK struct _AR6K_GMBOX_CTRL_REGISTERS {
+    A_UINT8                      int_status_enable;
+} POSTPACK AR6K_GMBOX_CTRL_REGISTERS;
+
+#include "athendpack.h"
+
+#define AR6K_IRQ_ENABLE_REGS_SIZE sizeof(AR6K_IRQ_ENABLE_REGISTERS)
+
+#define AR6K_REG_IO_BUFFER_SIZE     32
+#define AR6K_MAX_REG_IO_BUFFERS     8
+#define FROM_DMA_BUFFER TRUE
+#define TO_DMA_BUFFER   FALSE
+#define AR6K_SCATTER_ENTRIES_PER_REQ            16
+#define AR6K_MAX_TRANSFER_SIZE_PER_SCATTER      16*1024
+#define AR6K_SCATTER_REQS                       4
+#define AR6K_LEGACY_MAX_WRITE_LENGTH            2048
+
+#ifndef A_CACHE_LINE_PAD
+#define A_CACHE_LINE_PAD                        128
+#endif
+#define AR6K_MIN_SCATTER_ENTRIES_PER_REQ        2
+#define AR6K_MIN_TRANSFER_SIZE_PER_SCATTER      4*1024
+
+/* buffers for ASYNC I/O */
+typedef struct AR6K_ASYNC_REG_IO_BUFFER {
+    HTC_PACKET    HtcPacket;   /* we use an HTC packet as a wrapper for our async register-based I/O */
+    A_UINT8       _Pad1[A_CACHE_LINE_PAD];
+    A_UINT8       Buffer[AR6K_REG_IO_BUFFER_SIZE];  /* cache-line safe with pads around */
+    A_UINT8       _Pad2[A_CACHE_LINE_PAD];
+} AR6K_ASYNC_REG_IO_BUFFER;
+
+typedef struct _AR6K_GMBOX_INFO { 
+    void        *pProtocolContext;
+    A_STATUS    (*pMessagePendingCallBack)(void *pContext, A_UINT8 LookAheadBytes[], int ValidBytes);
+    A_STATUS    (*pCreditsPendingCallback)(void *pContext, int NumCredits,  A_BOOL CreditIRQEnabled);
+    void        (*pTargetFailureCallback)(void *pContext, A_STATUS Status);
+    void        (*pStateDumpCallback)(void *pContext);
+    A_BOOL      CreditCountIRQEnabled;    
+} AR6K_GMBOX_INFO; 
+
+typedef struct _AR6K_DEVICE {
+    A_MUTEX_T                   Lock;
+    A_UINT8       _Pad1[A_CACHE_LINE_PAD];
+    AR6K_IRQ_PROC_REGISTERS     IrqProcRegisters;   /* cache-line safe with pads around */
+    A_UINT8       _Pad2[A_CACHE_LINE_PAD];
+    AR6K_IRQ_ENABLE_REGISTERS   IrqEnableRegisters; /* cache-line safe with pads around */
+    A_UINT8       _Pad3[A_CACHE_LINE_PAD];
+    void                        *HIFDevice;
+    A_UINT32                    BlockSize;
+    A_UINT32                    BlockMask;
+    HIF_DEVICE_MBOX_INFO        MailBoxInfo;
+    HIF_PENDING_EVENTS_FUNC     GetPendingEventsFunc;
+    void                        *HTCContext;
+    HTC_PACKET_QUEUE            RegisterIOList;
+    AR6K_ASYNC_REG_IO_BUFFER    RegIOBuffers[AR6K_MAX_REG_IO_BUFFERS];
+    void                        (*TargetFailureCallback)(void *Context);
+    A_STATUS                    (*MessagePendingCallback)(void *Context, 
+                                                          A_UINT32 LookAheads[], 
+                                                          int NumLookAheads, 
+                                                          A_BOOL *pAsyncProc,
+                                                          int *pNumPktsFetched);
+    HIF_DEVICE_IRQ_PROCESSING_MODE  HifIRQProcessingMode;
+    HIF_MASK_UNMASK_RECV_EVENT      HifMaskUmaskRecvEvent;
+    A_BOOL                          HifAttached;
+    HIF_DEVICE_IRQ_YIELD_PARAMS     HifIRQYieldParams;
+    A_BOOL                          DSRCanYield;
+    int                             CurrentDSRRecvCount;
+    HIF_DEVICE_SCATTER_SUPPORT_INFO HifScatterInfo;
+    DL_LIST                         ScatterReqHead; 
+    A_BOOL                          ScatterIsVirtual;    
+    int                             MaxRecvBundleSize;
+    int                             MaxSendBundleSize;
+    AR6K_GMBOX_INFO                 GMboxInfo;
+    A_BOOL                          GMboxEnabled; 
+    AR6K_GMBOX_CTRL_REGISTERS       GMboxControlRegisters;
+    int                             RecheckIRQStatusCnt;
+} AR6K_DEVICE;
+
+#define LOCK_AR6K(p)      A_MUTEX_LOCK(&(p)->Lock);
+#define UNLOCK_AR6K(p)    A_MUTEX_UNLOCK(&(p)->Lock);
+#define REF_IRQ_STATUS_RECHECK(p) (p)->RecheckIRQStatusCnt = 1  /* note: no need to lock this, it only gets set */
+
+A_STATUS DevSetup(AR6K_DEVICE *pDev);
+void     DevCleanup(AR6K_DEVICE *pDev);
+A_STATUS DevUnmaskInterrupts(AR6K_DEVICE *pDev);
+A_STATUS DevMaskInterrupts(AR6K_DEVICE *pDev);
+A_STATUS DevPollMboxMsgRecv(AR6K_DEVICE *pDev,
+                            A_UINT32    *pLookAhead,
+                            int          TimeoutMS);
+A_STATUS DevRWCompletionHandler(void *context, A_STATUS status);
+A_STATUS DevDsrHandler(void *context);
+A_STATUS DevCheckPendingRecvMsgsAsync(void *context);
+void     DevAsyncIrqProcessComplete(AR6K_DEVICE *pDev);
+void     DevDumpRegisters(AR6K_DEVICE               *pDev,
+                          AR6K_IRQ_PROC_REGISTERS   *pIrqProcRegs,
+                          AR6K_IRQ_ENABLE_REGISTERS *pIrqEnableRegs);
+
+#define DEV_STOP_RECV_ASYNC TRUE
+#define DEV_STOP_RECV_SYNC  FALSE
+#define DEV_ENABLE_RECV_ASYNC TRUE
+#define DEV_ENABLE_RECV_SYNC  FALSE
+A_STATUS DevStopRecv(AR6K_DEVICE *pDev, A_BOOL ASyncMode);
+A_STATUS DevEnableRecv(AR6K_DEVICE *pDev, A_BOOL ASyncMode);
+A_STATUS DevEnableInterrupts(AR6K_DEVICE *pDev);
+A_STATUS DevDisableInterrupts(AR6K_DEVICE *pDev);
+A_STATUS DevWaitForPendingRecv(AR6K_DEVICE *pDev,A_UINT32 TimeoutInMs,A_BOOL *pbIsRecvPending);
+
+#define DEV_CALC_RECV_PADDED_LEN(pDev, length) (((length) + (pDev)->BlockMask) & (~((pDev)->BlockMask)))
+#define DEV_CALC_SEND_PADDED_LEN(pDev, length) DEV_CALC_RECV_PADDED_LEN(pDev,length)
+#define DEV_IS_LEN_BLOCK_ALIGNED(pDev, length) (((length) % (pDev)->BlockSize) == 0)
+
+static INLINE A_STATUS DevSendPacket(AR6K_DEVICE *pDev, HTC_PACKET *pPacket, A_UINT32 SendLength) {
+    A_UINT32 paddedLength;
+    A_BOOL   sync = (pPacket->Completion == NULL) ? TRUE : FALSE;
+    A_STATUS status;
+
+       /* adjust the length to be a multiple of block size if appropriate */
+    paddedLength = DEV_CALC_SEND_PADDED_LEN(pDev, SendLength);
+
+#if 0                    
+    if (paddedLength > pPacket->BufferLength) {
+        A_ASSERT(FALSE);
+        if (pPacket->Completion != NULL) {
+            COMPLETE_HTC_PACKET(pPacket,A_EINVAL);
+            return A_OK;
+        }
+        return A_EINVAL;
+    }
+#endif
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_SEND,
+                ("DevSendPacket, Padded Length: %d Mbox:0x%X (mode:%s)\n",
+                paddedLength,
+                pDev->MailBoxInfo.MboxAddresses[HTC_MAILBOX],
+                sync ? "SYNC" : "ASYNC"));
+
+    status = HIFReadWrite(pDev->HIFDevice,
+                          pDev->MailBoxInfo.MboxAddresses[HTC_MAILBOX],
+                          pPacket->pBuffer,
+                          paddedLength,     /* the padded length */
+                          sync ? HIF_WR_SYNC_BLOCK_INC : HIF_WR_ASYNC_BLOCK_INC,
+                          sync ? NULL : pPacket);  /* pass the packet as the context to the HIF request */
+
+    if (sync) {
+        pPacket->Status = status;
+    } else {
+        if (status == A_PENDING) {
+            status = A_OK;    
+        }    
+    }
+
+    return status;
+}
+                    
+static INLINE A_STATUS DevRecvPacket(AR6K_DEVICE *pDev, HTC_PACKET *pPacket, A_UINT32 RecvLength) {
+    A_UINT32 paddedLength;
+    A_STATUS status;
+    A_BOOL   sync = (pPacket->Completion == NULL) ? TRUE : FALSE;
+
+        /* adjust the length to be a multiple of block size if appropriate */
+    paddedLength = DEV_CALC_RECV_PADDED_LEN(pDev, RecvLength);
+                    
+    if (paddedLength > pPacket->BufferLength) {
+        A_ASSERT(FALSE);
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                ("DevRecvPacket, Not enough space for padlen:%d recvlen:%d bufferlen:%d \n",
+                    paddedLength,RecvLength,pPacket->BufferLength));
+        if (pPacket->Completion != NULL) {
+            COMPLETE_HTC_PACKET(pPacket,A_EINVAL);
+            return A_OK;
+        }
+        return A_EINVAL;
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
+                ("DevRecvPacket (0x%lX : hdr:0x%X) Padded Length: %d Mbox:0x%X (mode:%s)\n",
+                (unsigned long)pPacket, pPacket->PktInfo.AsRx.ExpectedHdr,
+                paddedLength,
+                pDev->MailBoxInfo.MboxAddresses[HTC_MAILBOX],
+                sync ? "SYNC" : "ASYNC"));
+
+    status = HIFReadWrite(pDev->HIFDevice,
+                          pDev->MailBoxInfo.MboxAddresses[HTC_MAILBOX],
+                          pPacket->pBuffer,
+                          paddedLength,
+                          sync ? HIF_RD_SYNC_BLOCK_FIX : HIF_RD_ASYNC_BLOCK_FIX,
+                          sync ? NULL : pPacket);  /* pass the packet as the context to the HIF request */
+
+    if (sync) {
+        pPacket->Status = status;
+    }
+
+    return status;
+}
+
+#define DEV_CHECK_RECV_YIELD(pDev) \
+            ((pDev)->CurrentDSRRecvCount >= (pDev)->HifIRQYieldParams.RecvPacketYieldCount)
+            
+#define IS_DEV_IRQ_PROC_SYNC_MODE(pDev) (HIF_DEVICE_IRQ_SYNC_ONLY == (pDev)->HifIRQProcessingMode)
+#define IS_DEV_IRQ_PROCESSING_ASYNC_ALLOWED(pDev) ((pDev)->HifIRQProcessingMode != HIF_DEVICE_IRQ_SYNC_ONLY)
+
+/**************************************************/
+/****** Scatter Function and Definitions
+ * 
+ *  
+ */
+  
+A_STATUS DevCopyScatterListToFromDMABuffer(HIF_SCATTER_REQ *pReq, A_BOOL FromDMA);
+    
+    /* copy any READ data back into scatter list */        
+#define DEV_FINISH_SCATTER_OPERATION(pR)                      \
+    if (A_SUCCESS((pR)->CompletionStatus) &&                  \
+        !((pR)->Request & HIF_WRITE) &&                       \
+         ((pR)->ScatterMethod == HIF_SCATTER_DMA_BOUNCE)) {   \
+         (pR)->CompletionStatus = DevCopyScatterListToFromDMABuffer((pR),FROM_DMA_BUFFER); \
+    }
+    
+    /* copy any WRITE data to bounce buffer */
+static INLINE A_STATUS DEV_PREPARE_SCATTER_OPERATION(HIF_SCATTER_REQ *pReq)  { 
+    if ((pReq->Request & HIF_WRITE) && (pReq->ScatterMethod == HIF_SCATTER_DMA_BOUNCE)) {
+        return DevCopyScatterListToFromDMABuffer(pReq,TO_DMA_BUFFER);    
+    } else {
+        return A_OK;    
+    }
+}
+        
+    
+A_STATUS DevSetupMsgBundling(AR6K_DEVICE *pDev, int MaxMsgsPerTransfer);
+                                  
+#define DEV_GET_MAX_MSG_PER_BUNDLE(pDev)        (pDev)->HifScatterInfo.MaxScatterEntries
+#define DEV_GET_MAX_BUNDLE_LENGTH(pDev)         (pDev)->HifScatterInfo.MaxTransferSizePerScatterReq
+#define DEV_ALLOC_SCATTER_REQ(pDev)             \
+    (pDev)->HifScatterInfo.pAllocateReqFunc((pDev)->ScatterIsVirtual ? (pDev) : (pDev)->HIFDevice)
+    
+#define DEV_FREE_SCATTER_REQ(pDev,pR)           \
+    (pDev)->HifScatterInfo.pFreeReqFunc((pDev)->ScatterIsVirtual ? (pDev) : (pDev)->HIFDevice,(pR))
+
+#define DEV_GET_MAX_BUNDLE_RECV_LENGTH(pDev)   (pDev)->MaxRecvBundleSize
+#define DEV_GET_MAX_BUNDLE_SEND_LENGTH(pDev)   (pDev)->MaxSendBundleSize
+
+#define DEV_SCATTER_READ  TRUE
+#define DEV_SCATTER_WRITE FALSE
+#define DEV_SCATTER_ASYNC TRUE
+#define DEV_SCATTER_SYNC  FALSE
+A_STATUS DevSubmitScatterRequest(AR6K_DEVICE *pDev, HIF_SCATTER_REQ *pScatterReq, A_BOOL Read, A_BOOL Async);
+
+#ifdef MBOXHW_UNIT_TEST
+A_STATUS DoMboxHWTest(AR6K_DEVICE *pDev);
+#endif
+
+    /* completely virtual */
+typedef struct _DEV_SCATTER_DMA_VIRTUAL_INFO {
+    A_UINT8            *pVirtDmaBuffer;      /* dma-able buffer - CPU accessible address */
+    A_UINT8            DataArea[1];      /* start of data area */
+} DEV_SCATTER_DMA_VIRTUAL_INFO;
+
+
+
+void     DumpAR6KDevState(AR6K_DEVICE *pDev);
+
+/**************************************************/
+/****** GMBOX functions and definitions
+ * 
+ *  
+ */
+
+#ifdef ATH_AR6K_ENABLE_GMBOX
+
+void     DevCleanupGMbox(AR6K_DEVICE *pDev);
+A_STATUS DevSetupGMbox(AR6K_DEVICE *pDev);
+A_STATUS DevCheckGMboxInterrupts(AR6K_DEVICE *pDev);
+void     DevNotifyGMboxTargetFailure(AR6K_DEVICE *pDev);
+
+#else
+
+    /* compiled out */
+#define DevCleanupGMbox(p)
+#define DevCheckGMboxInterrupts(p) A_OK
+#define DevNotifyGMboxTargetFailure(p)
+
+static INLINE A_STATUS DevSetupGMbox(AR6K_DEVICE *pDev) {
+    pDev->GMboxEnabled = FALSE;
+    return A_OK;    
+}
+
+#endif
+
+#ifdef ATH_AR6K_ENABLE_GMBOX
+
+    /* GMBOX protocol modules must expose each of these internal APIs */
+HCI_TRANSPORT_HANDLE GMboxAttachProtocol(AR6K_DEVICE *pDev, HCI_TRANSPORT_CONFIG_INFO *pInfo);
+A_STATUS             GMboxProtocolInstall(AR6K_DEVICE *pDev);
+void                 GMboxProtocolUninstall(AR6K_DEVICE *pDev);
+
+    /* API used by GMBOX protocol modules */
+AR6K_DEVICE  *HTCGetAR6KDevice(void *HTCHandle);
+#define DEV_GMBOX_SET_PROTOCOL(pDev,recv_callback,credits_pending,failure,statedump,context) \
+{                                                                  \
+    (pDev)->GMboxInfo.pProtocolContext = (context);                \
+    (pDev)->GMboxInfo.pMessagePendingCallBack = (recv_callback);   \
+    (pDev)->GMboxInfo.pCreditsPendingCallback = (credits_pending); \
+    (pDev)->GMboxInfo.pTargetFailureCallback = (failure);          \
+    (pDev)->GMboxInfo.pStateDumpCallback = (statedump);            \
+}
+
+#define DEV_GMBOX_GET_PROTOCOL(pDev)  (pDev)->GMboxInfo.pProtocolContext
+
+A_STATUS DevGMboxWrite(AR6K_DEVICE *pDev, HTC_PACKET *pPacket, A_UINT32 WriteLength);
+A_STATUS DevGMboxRead(AR6K_DEVICE *pDev, HTC_PACKET *pPacket, A_UINT32 ReadLength);
+
+#define PROC_IO_ASYNC TRUE
+#define PROC_IO_SYNC  FALSE
+typedef enum GMBOX_IRQ_ACTION_TYPE {
+    GMBOX_ACTION_NONE = 0,
+    GMBOX_DISABLE_ALL,
+    GMBOX_ERRORS_IRQ_ENABLE,
+    GMBOX_RECV_IRQ_ENABLE,
+    GMBOX_RECV_IRQ_DISABLE,
+    GMBOX_CREDIT_IRQ_ENABLE,
+    GMBOX_CREDIT_IRQ_DISABLE,
+} GMBOX_IRQ_ACTION_TYPE;
+
+A_STATUS DevGMboxIRQAction(AR6K_DEVICE *pDev, GMBOX_IRQ_ACTION_TYPE, A_BOOL AsyncMode);
+A_STATUS DevGMboxReadCreditCounter(AR6K_DEVICE *pDev, A_BOOL AsyncMode, int *pCredits);
+A_STATUS DevGMboxReadCreditSize(AR6K_DEVICE *pDev, int *pCreditSize);
+A_STATUS DevGMboxRecvLookAheadPeek(AR6K_DEVICE *pDev, A_UINT8 *pLookAheadBuffer, int *pLookAheadBytes);
+A_STATUS DevGMboxSetTargetInterrupt(AR6K_DEVICE *pDev, int SignalNumber, int AckTimeoutMS);
+
+#endif
+
+#endif /*AR6K_H_*/
diff --git a/drivers/net/ath6kl/htc2/AR6000/ar6k_events.c b/drivers/net/ath6kl/htc2/AR6000/ar6k_events.c
new file mode 100644
index 00000000000..920123b9ba1
--- /dev/null
+++ b/drivers/net/ath6kl/htc2/AR6000/ar6k_events.c
@@ -0,0 +1,784 @@
+//------------------------------------------------------------------------------
+// <copyright file="ar6k_events.c" company="Atheros">
+//    Copyright (c) 2007-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// AR6K Driver layer event handling (i.e. interrupts, message polling)
+//
+// Author(s): ="Atheros"
+//==============================================================================
+
+#include "a_config.h"
+#include "athdefs.h"
+#include "a_types.h"
+#include "AR6002/hw2.0/hw/mbox_host_reg.h"
+#include "a_osapi.h"
+#include "../htc_debug.h"
+#include "hif.h"
+#include "htc_packet.h"
+#include "ar6k.h"
+
+extern void AR6KFreeIOPacket(AR6K_DEVICE *pDev, HTC_PACKET *pPacket);
+extern HTC_PACKET *AR6KAllocIOPacket(AR6K_DEVICE *pDev);
+
+static A_STATUS DevServiceDebugInterrupt(AR6K_DEVICE *pDev);
+
+#define DELAY_PER_INTERVAL_MS 10  /* 10 MS delay per polling interval */
+
+/* completion routine for ALL HIF layer async I/O */
+A_STATUS DevRWCompletionHandler(void *context, A_STATUS status)
+{
+    HTC_PACKET *pPacket = (HTC_PACKET *)context;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
+                ("+DevRWCompletionHandler (Pkt:0x%lX) , Status: %d \n",
+                (unsigned long)pPacket,
+                status));
+
+    COMPLETE_HTC_PACKET(pPacket,status);
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
+                ("-DevRWCompletionHandler\n"));
+
+    return A_OK;
+}
+
+/* mailbox recv message polling */
+A_STATUS DevPollMboxMsgRecv(AR6K_DEVICE *pDev,
+                            A_UINT32    *pLookAhead,
+                            int          TimeoutMS)
+{
+    A_STATUS status = A_OK;
+    int      timeout = TimeoutMS/DELAY_PER_INTERVAL_MS;
+
+    A_ASSERT(timeout > 0);
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("+DevPollMboxMsgRecv \n"));
+
+    while (TRUE) {
+
+        if (pDev->GetPendingEventsFunc != NULL) {
+
+            HIF_PENDING_EVENTS_INFO events;
+
+#ifdef THREAD_X
+			events.Polling =1;
+#endif
+
+            /* the HIF layer uses a special mechanism to get events, do this
+             * synchronously */
+            status = pDev->GetPendingEventsFunc(pDev->HIFDevice,
+                                            &events,
+                                            NULL);
+            if (A_FAILED(status))
+            {
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Failed to get pending events \n"));
+                break;
+            }
+
+            if (events.Events & HIF_RECV_MSG_AVAIL)
+            {
+                    /*  there is a message available, the lookahead should be valid now */
+                *pLookAhead = events.LookAhead;
+
+                break;
+            }
+        } else {
+
+                /* this is the standard HIF way.... */
+                /* load the register table */
+            status = HIFReadWrite(pDev->HIFDevice,
+                                  HOST_INT_STATUS_ADDRESS,
+                                  (A_UINT8 *)&pDev->IrqProcRegisters,
+                                  AR6K_IRQ_PROC_REGS_SIZE,
+                                  HIF_RD_SYNC_BYTE_INC,
+                                  NULL);
+
+            if (A_FAILED(status)){
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Failed to read register table \n"));
+                break;
+            }
+
+                /* check for MBOX data and valid lookahead */
+            if (pDev->IrqProcRegisters.host_int_status & (1 << HTC_MAILBOX)) {
+                if (pDev->IrqProcRegisters.rx_lookahead_valid & (1 << HTC_MAILBOX))
+                {
+                    /* mailbox has a message and the look ahead is valid */
+                    *pLookAhead = pDev->IrqProcRegisters.rx_lookahead[HTC_MAILBOX];
+                    break;
+                }
+            }
+
+        }
+
+        timeout--;
+
+        if (timeout <= 0) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, (" Timeout waiting for recv message \n"));
+            status = A_ERROR;
+
+                /* check if the target asserted */
+            if ( pDev->IrqProcRegisters.counter_int_status & AR6K_TARGET_DEBUG_INTR_MASK) {
+                    /* target signaled an assert, process this pending interrupt
+                     * this will call the target failure handler */
+                DevServiceDebugInterrupt(pDev);
+            }
+
+            break;
+        }
+
+            /* delay a little  */
+        A_MDELAY(DELAY_PER_INTERVAL_MS);
+        AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("  Retry Mbox Poll : %d \n",timeout));
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("-DevPollMboxMsgRecv \n"));
+
+    return status;
+}
+
+static A_STATUS DevServiceCPUInterrupt(AR6K_DEVICE *pDev)
+{
+    A_STATUS status;
+    A_UINT8  cpu_int_status;
+    A_UINT8  regBuffer[4];
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("CPU Interrupt\n"));
+    cpu_int_status = pDev->IrqProcRegisters.cpu_int_status &
+                     pDev->IrqEnableRegisters.cpu_int_status_enable;
+    A_ASSERT(cpu_int_status);
+    AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,
+                    ("Valid interrupt source(s) in CPU_INT_STATUS: 0x%x\n",
+                    cpu_int_status));
+
+        /* Clear the interrupt */
+    pDev->IrqProcRegisters.cpu_int_status &= ~cpu_int_status; /* W1C */
+
+        /* set up the register transfer buffer to hit the register 4 times , this is done
+         * to make the access 4-byte aligned to mitigate issues with host bus interconnects that
+         * restrict bus transfer lengths to be a multiple of 4-bytes */
+
+        /* set W1C value to clear the interrupt, this hits the register first */
+    regBuffer[0] = cpu_int_status;
+        /* the remaining 4 values are set to zero which have no-effect  */
+    regBuffer[1] = 0;
+    regBuffer[2] = 0;
+    regBuffer[3] = 0;
+
+    status = HIFReadWrite(pDev->HIFDevice,
+                          CPU_INT_STATUS_ADDRESS,
+                          regBuffer,
+                          4,
+                          HIF_WR_SYNC_BYTE_FIX,
+                          NULL);
+
+    A_ASSERT(status == A_OK);
+    return status;
+}
+
+
+static A_STATUS DevServiceErrorInterrupt(AR6K_DEVICE *pDev)
+{
+    A_STATUS status;
+    A_UINT8  error_int_status;
+    A_UINT8  regBuffer[4];
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("Error Interrupt\n"));
+    error_int_status = pDev->IrqProcRegisters.error_int_status & 0x0F;
+    A_ASSERT(error_int_status);
+    AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,
+                    ("Valid interrupt source(s) in ERROR_INT_STATUS: 0x%x\n",
+                    error_int_status));
+
+    if (ERROR_INT_STATUS_WAKEUP_GET(error_int_status)) {
+        /* Wakeup */
+        AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("Error : Wakeup\n"));
+    }
+
+    if (ERROR_INT_STATUS_RX_UNDERFLOW_GET(error_int_status)) {
+        /* Rx Underflow */
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Error : Rx Underflow\n"));
+    }
+
+    if (ERROR_INT_STATUS_TX_OVERFLOW_GET(error_int_status)) {
+        /* Tx Overflow */
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Error : Tx Overflow\n"));
+    }
+
+        /* Clear the interrupt */
+    pDev->IrqProcRegisters.error_int_status &= ~error_int_status; /* W1C */
+
+        /* set up the register transfer buffer to hit the register 4 times , this is done
+         * to make the access 4-byte aligned to mitigate issues with host bus interconnects that
+         * restrict bus transfer lengths to be a multiple of 4-bytes */
+
+        /* set W1C value to clear the interrupt, this hits the register first */
+    regBuffer[0] = error_int_status;
+        /* the remaining 4 values are set to zero which have no-effect  */
+    regBuffer[1] = 0;
+    regBuffer[2] = 0;
+    regBuffer[3] = 0;
+
+    status = HIFReadWrite(pDev->HIFDevice,
+                          ERROR_INT_STATUS_ADDRESS,
+                          regBuffer,
+                          4,
+                          HIF_WR_SYNC_BYTE_FIX,
+                          NULL);
+
+    A_ASSERT(status == A_OK);
+    return status;
+}
+
+static A_STATUS DevServiceDebugInterrupt(AR6K_DEVICE *pDev)
+{
+    A_UINT32 dummy;
+    A_STATUS status;
+
+    /* Send a target failure event to the application */
+    AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Target debug interrupt\n"));
+
+    if (pDev->TargetFailureCallback != NULL) {
+        pDev->TargetFailureCallback(pDev->HTCContext);
+    }
+
+    if (pDev->GMboxEnabled) {
+        DevNotifyGMboxTargetFailure(pDev);
+    }
+
+    /* clear the interrupt , the debug error interrupt is
+     * counter 0 */
+        /* read counter to clear interrupt */
+    status = HIFReadWrite(pDev->HIFDevice,
+                          COUNT_DEC_ADDRESS,
+                          (A_UINT8 *)&dummy,
+                          4,
+                          HIF_RD_SYNC_BYTE_INC,
+                          NULL);
+
+    A_ASSERT(status == A_OK);
+    return status;
+}
+
+static A_STATUS DevServiceCounterInterrupt(AR6K_DEVICE *pDev)
+{
+    A_UINT8 counter_int_status;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("Counter Interrupt\n"));
+
+    counter_int_status = pDev->IrqProcRegisters.counter_int_status &
+                         pDev->IrqEnableRegisters.counter_int_status_enable;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,
+                    ("Valid interrupt source(s) in COUNTER_INT_STATUS: 0x%x\n",
+                    counter_int_status));
+
+        /* Check if the debug interrupt is pending
+         * NOTE: other modules like GMBOX may use the counter interrupt for
+         * credit flow control on other counters, we only need to check for the debug assertion
+         * counter interrupt */
+    if (counter_int_status & AR6K_TARGET_DEBUG_INTR_MASK) {
+        return DevServiceDebugInterrupt(pDev);
+    }
+
+    return A_OK;
+}
+
+/* callback when our fetch to get interrupt status registers completes */
+static void DevGetEventAsyncHandler(void *Context, HTC_PACKET *pPacket)
+{
+    AR6K_DEVICE *pDev = (AR6K_DEVICE *)Context;
+    A_UINT32    lookAhead = 0;
+    A_BOOL      otherInts = FALSE;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevGetEventAsyncHandler: (dev: 0x%lX)\n", (unsigned long)pDev));
+
+    do {
+
+        if (A_FAILED(pPacket->Status)) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                    (" GetEvents I/O request failed, status:%d \n", pPacket->Status));
+            /* bail out, don't unmask HIF interrupt */
+            break;
+        }
+
+        if (pDev->GetPendingEventsFunc != NULL) {
+                /* the HIF layer collected the information for us */
+            HIF_PENDING_EVENTS_INFO *pEvents = (HIF_PENDING_EVENTS_INFO *)pPacket->pBuffer;
+            if (pEvents->Events & HIF_RECV_MSG_AVAIL) {
+                lookAhead = pEvents->LookAhead;
+                if (0 == lookAhead) {
+                    AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" DevGetEventAsyncHandler1, lookAhead is zero! \n"));
+                }
+            }
+            if (pEvents->Events & HIF_OTHER_EVENTS) {
+                otherInts = TRUE;
+            }
+        } else {
+                /* standard interrupt table handling.... */
+            AR6K_IRQ_PROC_REGISTERS *pReg = (AR6K_IRQ_PROC_REGISTERS *)pPacket->pBuffer;
+            A_UINT8                 host_int_status;
+
+            host_int_status = pReg->host_int_status & pDev->IrqEnableRegisters.int_status_enable;
+
+            if (host_int_status & (1 << HTC_MAILBOX)) {
+                host_int_status &= ~(1 << HTC_MAILBOX);
+                if (pReg->rx_lookahead_valid & (1 << HTC_MAILBOX)) {
+                        /* mailbox has a message and the look ahead is valid */
+                    lookAhead = pReg->rx_lookahead[HTC_MAILBOX];
+                    if (0 == lookAhead) {
+                        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" DevGetEventAsyncHandler2, lookAhead is zero! \n"));
+                    }
+                }
+            }
+
+            if (host_int_status) {
+                    /* there are other interrupts to handle */
+                otherInts = TRUE;
+            }
+        }
+
+        if (otherInts || (lookAhead == 0)) {
+            /* if there are other interrupts to process, we cannot do this in the async handler so
+             * ack the interrupt which will cause our sync handler to run again
+             * if however there are no more messages, we can now ack the interrupt  */
+            AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,
+                (" Acking interrupt from DevGetEventAsyncHandler (otherints:%d, lookahead:0x%X)\n",
+                otherInts, lookAhead));
+            HIFAckInterrupt(pDev->HIFDevice);
+        } else {
+            int      fetched = 0;
+            A_STATUS status;
+
+            AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,
+                    (" DevGetEventAsyncHandler : detected another message, lookahead :0x%X \n",
+                    lookAhead));
+                /* lookahead is non-zero and there are no other interrupts to service,
+                 * go get the next message */
+            status = pDev->MessagePendingCallback(pDev->HTCContext, &lookAhead, 1, NULL, &fetched);
+
+            if (A_SUCCESS(status) && !fetched) {
+                    /* HTC layer could not pull out messages due to lack of resources, stop IRQ processing */
+                AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("MessagePendingCallback did not pull any messages, force-ack \n"));
+                DevAsyncIrqProcessComplete(pDev);
+            }
+        }
+
+    } while (FALSE);
+
+        /* free this IO packet */
+    AR6KFreeIOPacket(pDev,pPacket);
+    AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevGetEventAsyncHandler \n"));
+}
+
+/* called by the HTC layer when it wants us to check if the device has any more pending
+ * recv messages, this starts off a series of async requests to read interrupt registers  */
+A_STATUS DevCheckPendingRecvMsgsAsync(void *context)
+{
+    AR6K_DEVICE  *pDev = (AR6K_DEVICE *)context;
+    A_STATUS      status = A_OK;
+    HTC_PACKET   *pIOPacket;
+
+    /* this is called in an ASYNC only context, we may NOT block, sleep or call any apis that can
+     * cause us to switch contexts */
+
+   AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevCheckPendingRecvMsgsAsync: (dev: 0x%lX)\n", (unsigned long)pDev));
+
+   do {
+
+        if (HIF_DEVICE_IRQ_SYNC_ONLY == pDev->HifIRQProcessingMode) {
+                /* break the async processing chain right here, no need to continue.
+                 * The DevDsrHandler() will handle things in a loop when things are driven
+                 * synchronously  */
+            break;
+        }
+
+            /* an optimization to bypass reading the IRQ status registers unecessarily which can re-wake
+             * the target, if upper layers determine that we are in a low-throughput mode, we can
+             * rely on taking another interrupt rather than re-checking the status registers which can
+             * re-wake the target */
+        if (pDev->RecheckIRQStatusCnt == 0) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("Bypassing IRQ Status re-check, re-acking HIF interrupts\n"));
+                /* ack interrupt */
+            HIFAckInterrupt(pDev->HIFDevice);
+            break;
+        }
+
+            /* first allocate one of our HTC packets we created for async I/O
+             * we reuse HTC packet definitions so that we can use the completion mechanism
+             * in DevRWCompletionHandler() */
+        pIOPacket = AR6KAllocIOPacket(pDev);
+
+        if (NULL == pIOPacket) {
+                /* there should be only 1 asynchronous request out at a time to read these registers
+                 * so this should actually never happen */
+            status = A_NO_MEMORY;
+            A_ASSERT(FALSE);
+            break;
+        }
+
+            /* stick in our completion routine when the I/O operation completes */
+        pIOPacket->Completion = DevGetEventAsyncHandler;
+        pIOPacket->pContext = pDev;
+
+        if (pDev->GetPendingEventsFunc) {
+                /* HIF layer has it's own mechanism, pass the IO to it.. */
+            status = pDev->GetPendingEventsFunc(pDev->HIFDevice,
+                                                (HIF_PENDING_EVENTS_INFO *)pIOPacket->pBuffer,
+                                                pIOPacket);
+
+        } else {
+                /* standard way, read the interrupt register table asynchronously again */
+            status = HIFReadWrite(pDev->HIFDevice,
+                                  HOST_INT_STATUS_ADDRESS,
+                                  pIOPacket->pBuffer,
+                                  AR6K_IRQ_PROC_REGS_SIZE,
+                                  HIF_RD_ASYNC_BYTE_INC,
+                                  pIOPacket);
+        }
+
+        AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,(" Async IO issued to get interrupt status...\n"));
+   } while (FALSE);
+
+   AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevCheckPendingRecvMsgsAsync \n"));
+
+   return status;
+}
+
+void DevAsyncIrqProcessComplete(AR6K_DEVICE *pDev)
+{
+    AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("DevAsyncIrqProcessComplete - forcing HIF IRQ ACK \n"));
+    HIFAckInterrupt(pDev->HIFDevice);
+}
+
+/* process pending interrupts synchronously */
+static A_STATUS ProcessPendingIRQs(AR6K_DEVICE *pDev, A_BOOL *pDone, A_BOOL *pASyncProcessing)
+{
+    A_STATUS    status = A_OK;
+    A_UINT8     host_int_status = 0;
+    A_UINT32    lookAhead = 0;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+ProcessPendingIRQs: (dev: 0x%lX)\n", (unsigned long)pDev));
+
+    /*** NOTE: the HIF implementation guarantees that the context of this call allows
+     *         us to perform SYNCHRONOUS I/O, that is we can block, sleep or call any API that
+     *         can block or switch thread/task ontexts.
+     *         This is a fully schedulable context.
+     * */
+    do {
+
+            if (pDev->IrqEnableRegisters.int_status_enable == 0) {
+                /* interrupt enables have been cleared, do not try to process any pending interrupts that
+                 * may result in more bus transactions.  The target may be unresponsive at this
+                 * point. */
+                 break;
+            }
+
+            if (pDev->GetPendingEventsFunc != NULL) {
+                HIF_PENDING_EVENTS_INFO events;
+
+#ifdef THREAD_X
+            events.Polling= 0;
+#endif
+                /* the HIF layer uses a special mechanism to get events
+                 * get this synchronously  */
+            status = pDev->GetPendingEventsFunc(pDev->HIFDevice,
+                                                &events,
+                                                NULL);
+
+            if (A_FAILED(status)) {
+                break;
+            }
+
+            if (events.Events & HIF_RECV_MSG_AVAIL) {
+                lookAhead = events.LookAhead;
+                if (0 == lookAhead) {
+                    AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" ProcessPendingIRQs1 lookAhead is zero! \n"));
+                }
+            }
+
+            if (!(events.Events & HIF_OTHER_EVENTS) ||
+                !(pDev->IrqEnableRegisters.int_status_enable & OTHER_INTS_ENABLED)) {
+                    /* no need to read the register table, no other interesting interrupts.
+                     * Some interfaces (like SPI) can shadow interrupt sources without
+                     * requiring the host to do a full table read */
+                break;
+            }
+
+            /* otherwise fall through and read the register table */
+        }
+
+        /*
+         * Read the first 28 bytes of the HTC register table. This will yield us
+         * the value of different int status registers and the lookahead
+         * registers.
+         *    length = sizeof(int_status) + sizeof(cpu_int_status) +
+         *             sizeof(error_int_status) + sizeof(counter_int_status) +
+         *             sizeof(mbox_frame) + sizeof(rx_lookahead_valid) +
+         *             sizeof(hole) +  sizeof(rx_lookahead) +
+         *             sizeof(int_status_enable) + sizeof(cpu_int_status_enable) +
+         *             sizeof(error_status_enable) +
+         *             sizeof(counter_int_status_enable);
+         *
+        */
+#ifdef CONFIG_MMC_SDHCI_S3C
+            pDev->IrqProcRegisters.host_int_status = 0;
+            pDev->IrqProcRegisters.rx_lookahead_valid = 0;
+            pDev->IrqProcRegisters.host_int_status2 = 0;
+            pDev->IrqProcRegisters.rx_lookahead[0] = 0;
+            pDev->IrqProcRegisters.rx_lookahead[1] = 0xaaa5555;
+#endif /* CONFIG_MMC_SDHCI_S3C */
+        status = HIFReadWrite(pDev->HIFDevice,
+                              HOST_INT_STATUS_ADDRESS,
+                              (A_UINT8 *)&pDev->IrqProcRegisters,
+                              AR6K_IRQ_PROC_REGS_SIZE,
+                              HIF_RD_SYNC_BYTE_INC,
+                              NULL);
+
+        if (A_FAILED(status)) {
+            break;
+        }
+
+#ifdef ATH_DEBUG_MODULE
+        if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_IRQ)) {
+            DevDumpRegisters(pDev,
+                             &pDev->IrqProcRegisters,
+                             &pDev->IrqEnableRegisters);
+        }
+#endif
+
+            /* Update only those registers that are enabled */
+        host_int_status = pDev->IrqProcRegisters.host_int_status &
+                          pDev->IrqEnableRegisters.int_status_enable;
+
+        if (NULL == pDev->GetPendingEventsFunc) {
+                /* only look at mailbox status if the HIF layer did not provide this function,
+                 * on some HIF interfaces reading the RX lookahead is not valid to do */
+            if (host_int_status & (1 << HTC_MAILBOX)) {
+                    /* mask out pending mailbox value, we use "lookAhead" as the real flag for
+                     * mailbox processing below */
+                host_int_status &= ~(1 << HTC_MAILBOX);
+                if (pDev->IrqProcRegisters.rx_lookahead_valid & (1 << HTC_MAILBOX)) {
+                        /* mailbox has a message and the look ahead is valid */
+                    lookAhead = pDev->IrqProcRegisters.rx_lookahead[HTC_MAILBOX];
+                    if (0 == lookAhead) {
+                        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" ProcessPendingIRQs2, lookAhead is zero! \n"));
+                    }
+                }
+            }
+        } else {
+                /* not valid to check if the HIF has another mechanism for reading mailbox pending status*/
+            host_int_status &= ~(1 << HTC_MAILBOX);
+        }
+
+        if (pDev->GMboxEnabled) {
+                /*call GMBOX layer to process any interrupts of interest */
+            status = DevCheckGMboxInterrupts(pDev);
+        }
+
+    } while (FALSE);
+
+
+    do {
+
+            /* did the interrupt status fetches succeed? */
+        if (A_FAILED(status)) {
+            break;
+        }
+
+        if ((0 == host_int_status) && (0 == lookAhead)) {
+                /* nothing to process, the caller can use this to break out of a loop */
+            *pDone = TRUE;
+            break;
+        }
+
+        if (lookAhead != 0) {
+            int fetched = 0;
+
+            AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("Pending mailbox message, LookAhead: 0x%X\n",lookAhead));
+                /* Mailbox Interrupt, the HTC layer may issue async requests to empty the
+                 * mailbox...
+                 * When emptying the recv mailbox we use the async handler above called from the
+                 * completion routine of the callers read request. This can improve performance
+                 * by reducing context switching when we rapidly pull packets */
+            status = pDev->MessagePendingCallback(pDev->HTCContext, &lookAhead, 1, pASyncProcessing, &fetched);
+            if (A_FAILED(status)) {
+                break;
+            }
+
+            if (!fetched) {
+                    /* HTC could not pull any messages out due to lack of resources */
+                    /* force DSR handler to ack the interrupt */
+                *pASyncProcessing = FALSE;
+                pDev->RecheckIRQStatusCnt = 0;
+            }
+        }
+
+            /* now handle the rest of them */
+        AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,
+                            (" Valid interrupt source(s) for OTHER interrupts: 0x%x\n",
+                            host_int_status));
+
+        if (HOST_INT_STATUS_CPU_GET(host_int_status)) {
+                /* CPU Interrupt */
+            status = DevServiceCPUInterrupt(pDev);
+            if (A_FAILED(status)){
+                break;
+            }
+        }
+
+        if (HOST_INT_STATUS_ERROR_GET(host_int_status)) {
+                /* Error Interrupt */
+            status = DevServiceErrorInterrupt(pDev);
+            if (A_FAILED(status)){
+                break;
+            }
+        }
+
+        if (HOST_INT_STATUS_COUNTER_GET(host_int_status)) {
+                /* Counter Interrupt */
+            status = DevServiceCounterInterrupt(pDev);
+            if (A_FAILED(status)){
+                break;
+            }
+        }
+
+    } while (FALSE);
+
+        /* an optimization to bypass reading the IRQ status registers unecessarily which can re-wake
+         * the target, if upper layers determine that we are in a low-throughput mode, we can
+         * rely on taking another interrupt rather than re-checking the status registers which can
+         * re-wake the target.
+         *
+         * NOTE : for host interfaces that use the special GetPendingEventsFunc, this optimization cannot
+         * be used due to possible side-effects.  For example, SPI requires the host to drain all
+         * messages from the mailbox before exiting the ISR routine. */
+    if (!(*pASyncProcessing) && (pDev->RecheckIRQStatusCnt == 0) && (pDev->GetPendingEventsFunc == NULL)) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("Bypassing IRQ Status re-check, forcing done \n"));
+        *pDone = TRUE;
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-ProcessPendingIRQs: (done:%d, async:%d) status=%d \n",
+                *pDone, *pASyncProcessing, status));
+
+    return status;
+}
+
+
+/* Synchronousinterrupt handler, this handler kicks off all interrupt processing.*/
+A_STATUS DevDsrHandler(void *context)
+{
+    AR6K_DEVICE *pDev = (AR6K_DEVICE *)context;
+    A_STATUS    status = A_OK;
+    A_BOOL      done = FALSE;
+    A_BOOL      asyncProc = FALSE;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevDsrHandler: (dev: 0x%lX)\n", (unsigned long)pDev));
+
+        /* reset the recv counter that tracks when we need to yield from the DSR */
+    pDev->CurrentDSRRecvCount = 0;
+        /* reset counter used to flag a re-scan of IRQ status registers on the target */
+    pDev->RecheckIRQStatusCnt = 0;
+
+    while (!done) {
+        status = ProcessPendingIRQs(pDev, &done, &asyncProc);
+        if (A_FAILED(status)) {
+            break;
+        }
+
+        if (HIF_DEVICE_IRQ_SYNC_ONLY == pDev->HifIRQProcessingMode) {
+            /* the HIF layer does not allow async IRQ processing, override the asyncProc flag */
+            asyncProc = FALSE;
+            /* this will cause us to re-enter ProcessPendingIRQ() and re-read interrupt status registers.
+             * this has a nice side effect of blocking us until all async read requests are completed.
+             * This behavior is required on some HIF implementations that do not allow ASYNC
+             * processing in interrupt handlers (like Windows CE) */
+
+            if (pDev->DSRCanYield && DEV_CHECK_RECV_YIELD(pDev)) {
+                /* ProcessPendingIRQs() pulled enough recv messages to satisfy the yield count, stop
+                 * checking for more messages and return */
+                break;
+            }
+        }
+
+        if (asyncProc) {
+                /* the function performed some async I/O for performance, we
+                   need to exit the ISR immediately, the check below will prevent the interrupt from being
+                   Ack'd while we handle it asynchronously */
+            break;
+        }
+
+    }
+
+    if (A_SUCCESS(status) && !asyncProc) {
+            /* Ack the interrupt only if :
+             *  1. we did not get any errors in processing interrupts
+             *  2. there are no outstanding async processing requests */
+        if (pDev->DSRCanYield) {
+                /* if the DSR can yield do not ACK the interrupt, there could be more pending messages.
+                 * The HIF layer must ACK the interrupt on behalf of HTC */
+            AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,(" Yield in effect (cur RX count: %d) \n", pDev->CurrentDSRRecvCount));
+        } else {
+            AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,(" Acking interrupt from DevDsrHandler \n"));
+            HIFAckInterrupt(pDev->HIFDevice);
+        }
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevDsrHandler \n"));
+    return status;
+}
+
+#ifdef ATH_DEBUG_MODULE
+void DumpAR6KDevState(AR6K_DEVICE *pDev)
+{
+    A_STATUS                    status;
+    AR6K_IRQ_ENABLE_REGISTERS   regs;
+    AR6K_IRQ_PROC_REGISTERS     procRegs;
+
+    LOCK_AR6K(pDev);
+        /* copy into our temp area */
+    A_MEMCPY(&regs,&pDev->IrqEnableRegisters,AR6K_IRQ_ENABLE_REGS_SIZE);
+    UNLOCK_AR6K(pDev);
+
+        /* load the register table from the device */
+    status = HIFReadWrite(pDev->HIFDevice,
+                          HOST_INT_STATUS_ADDRESS,
+                          (A_UINT8 *)&procRegs,
+                          AR6K_IRQ_PROC_REGS_SIZE,
+                          HIF_RD_SYNC_BYTE_INC,
+                          NULL);
+
+    if (A_FAILED(status)) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+            ("DumpAR6KDevState : Failed to read register table (%d) \n",status));
+        return;
+    }
+
+    DevDumpRegisters(pDev,&procRegs,&regs);
+
+    if (pDev->GMboxInfo.pStateDumpCallback != NULL) {
+        pDev->GMboxInfo.pStateDumpCallback(pDev->GMboxInfo.pProtocolContext);
+    }
+
+        /* dump any bus state at the HIF layer */
+    HIFConfigureDevice(pDev->HIFDevice,HIF_DEVICE_DEBUG_BUS_STATE,NULL,0);
+
+}
+#endif
+
+
diff --git a/drivers/net/ath6kl/htc2/AR6000/ar6k_gmbox.c b/drivers/net/ath6kl/htc2/AR6000/ar6k_gmbox.c
new file mode 100644
index 00000000000..e3d270d1d62
--- /dev/null
+++ b/drivers/net/ath6kl/htc2/AR6000/ar6k_gmbox.c
@@ -0,0 +1,756 @@
+//------------------------------------------------------------------------------
+// <copyright file="ar6k_gmbox.c" company="Atheros">
+//    Copyright (c) 2007-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Generic MBOX API implementation
+// 
+// Author(s): ="Atheros"
+//==============================================================================
+#include "a_config.h"
+#include "athdefs.h"
+#include "a_types.h"
+#include "a_osapi.h"
+#include "../htc_debug.h"
+#include "hif.h"
+#include "htc_packet.h"
+#include "ar6k.h"
+#include "hw/mbox_host_reg.h"
+#include "gmboxif.h"
+
+/* 
+ * This file provides management functions and a toolbox for GMBOX protocol modules.  
+ * Only one protocol module can be installed at a time. The determination of which protocol
+ * module is installed is determined at compile time.  
+ * 
+ */
+#ifdef ATH_AR6K_ENABLE_GMBOX
+     /* GMBOX definitions */
+#define GMBOX_INT_STATUS_ENABLE_REG     0x488
+#define GMBOX_INT_STATUS_RX_DATA        (1 << 0)
+#define GMBOX_INT_STATUS_TX_OVERFLOW    (1 << 1)
+#define GMBOX_INT_STATUS_RX_OVERFLOW    (1 << 2)
+
+#define GMBOX_LOOKAHEAD_MUX_REG         0x498
+#define GMBOX_LA_MUX_OVERRIDE_2_3       (1 << 0)
+
+#define AR6K_GMBOX_CREDIT_DEC_ADDRESS   (COUNT_DEC_ADDRESS + 4 * AR6K_GMBOX_CREDIT_COUNTER)
+#define AR6K_GMBOX_CREDIT_SIZE_ADDRESS  (COUNT_ADDRESS     + AR6K_GMBOX_CREDIT_SIZE_COUNTER)
+
+
+    /* external APIs for allocating and freeing internal I/O packets to handle ASYNC I/O */ 
+extern void AR6KFreeIOPacket(AR6K_DEVICE *pDev, HTC_PACKET *pPacket);
+extern HTC_PACKET *AR6KAllocIOPacket(AR6K_DEVICE *pDev);
+
+
+/* callback when our fetch to enable/disable completes */
+static void DevGMboxIRQActionAsyncHandler(void *Context, HTC_PACKET *pPacket)
+{
+    AR6K_DEVICE *pDev = (AR6K_DEVICE *)Context;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevGMboxIRQActionAsyncHandler: (dev: 0x%lX)\n", (unsigned long)pDev));
+
+    if (A_FAILED(pPacket->Status)) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                ("IRQAction Operation (%d) failed! status:%d \n", pPacket->PktInfo.AsRx.HTCRxFlags,pPacket->Status));
+    }
+        /* free this IO packet */
+    AR6KFreeIOPacket(pDev,pPacket);
+    AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevGMboxIRQActionAsyncHandler \n"));
+}
+
+static A_STATUS DevGMboxCounterEnableDisable(AR6K_DEVICE *pDev, GMBOX_IRQ_ACTION_TYPE IrqAction, A_BOOL AsyncMode)
+{
+    A_STATUS                  status = A_OK;
+    AR6K_IRQ_ENABLE_REGISTERS regs;
+    HTC_PACKET                *pIOPacket = NULL;  
+    
+    LOCK_AR6K(pDev);
+    
+    if (GMBOX_CREDIT_IRQ_ENABLE == IrqAction) {
+        pDev->GMboxInfo.CreditCountIRQEnabled = TRUE;
+        pDev->IrqEnableRegisters.counter_int_status_enable |=
+            COUNTER_INT_STATUS_ENABLE_BIT_SET(1 << AR6K_GMBOX_CREDIT_COUNTER);
+        pDev->IrqEnableRegisters.int_status_enable |= INT_STATUS_ENABLE_COUNTER_SET(0x01);
+    } else {
+        pDev->GMboxInfo.CreditCountIRQEnabled = FALSE;
+        pDev->IrqEnableRegisters.counter_int_status_enable &=
+            ~(COUNTER_INT_STATUS_ENABLE_BIT_SET(1 << AR6K_GMBOX_CREDIT_COUNTER));    
+    }
+        /* copy into our temp area */
+    A_MEMCPY(&regs,&pDev->IrqEnableRegisters,AR6K_IRQ_ENABLE_REGS_SIZE);
+
+    UNLOCK_AR6K(pDev);
+
+    do {
+
+        if (AsyncMode) {
+
+            pIOPacket = AR6KAllocIOPacket(pDev);
+
+            if (NULL == pIOPacket) {
+                status = A_NO_MEMORY;
+                A_ASSERT(FALSE);
+                break;
+            }
+
+                /* copy values to write to our async I/O buffer */
+            A_MEMCPY(pIOPacket->pBuffer,&pDev->IrqEnableRegisters,AR6K_IRQ_ENABLE_REGS_SIZE);
+
+                /* stick in our completion routine when the I/O operation completes */
+            pIOPacket->Completion = DevGMboxIRQActionAsyncHandler;
+            pIOPacket->pContext = pDev;
+            pIOPacket->PktInfo.AsRx.HTCRxFlags = IrqAction;
+                /* write it out asynchronously */
+            HIFReadWrite(pDev->HIFDevice,
+                         INT_STATUS_ENABLE_ADDRESS,
+                         pIOPacket->pBuffer,
+                         AR6K_IRQ_ENABLE_REGS_SIZE,
+                         HIF_WR_ASYNC_BYTE_INC,
+                         pIOPacket);
+                         
+            pIOPacket = NULL; 
+            break;
+        } 
+
+            /* if we get here we are doing it synchronously */
+        status = HIFReadWrite(pDev->HIFDevice,
+                              INT_STATUS_ENABLE_ADDRESS,
+                              &regs.int_status_enable,
+                              AR6K_IRQ_ENABLE_REGS_SIZE,
+                              HIF_WR_SYNC_BYTE_INC,
+                              NULL);    
+    } while (FALSE);
+    
+    if (A_FAILED(status)) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                (" IRQAction Operation (%d) failed! status:%d \n", IrqAction, status));    
+    } else {
+        if (!AsyncMode) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,
+                    (" IRQAction Operation (%d) success \n", IrqAction)); 
+        }       
+    }
+    
+    if (pIOPacket != NULL) {
+        AR6KFreeIOPacket(pDev,pIOPacket);
+    }
+        
+    return status;
+}
+
+
+A_STATUS DevGMboxIRQAction(AR6K_DEVICE *pDev, GMBOX_IRQ_ACTION_TYPE IrqAction, A_BOOL AsyncMode)
+{
+    A_STATUS      status = A_OK;
+    HTC_PACKET    *pIOPacket = NULL;   
+    A_UINT8       GMboxIntControl[4];
+
+    if (GMBOX_CREDIT_IRQ_ENABLE == IrqAction) {
+        return DevGMboxCounterEnableDisable(pDev, GMBOX_CREDIT_IRQ_ENABLE, AsyncMode);
+    } else if(GMBOX_CREDIT_IRQ_DISABLE == IrqAction) {
+        return DevGMboxCounterEnableDisable(pDev, GMBOX_CREDIT_IRQ_DISABLE, AsyncMode);
+    }
+    
+    if (GMBOX_DISABLE_ALL == IrqAction) {
+            /* disable credit IRQ, those are on a different set of registers */
+        DevGMboxCounterEnableDisable(pDev, GMBOX_CREDIT_IRQ_DISABLE, AsyncMode);    
+    }
+            
+        /* take the lock to protect interrupt enable shadows */
+    LOCK_AR6K(pDev);
+
+    switch (IrqAction) {
+        
+        case GMBOX_DISABLE_ALL:
+            pDev->GMboxControlRegisters.int_status_enable = 0;
+            break;
+        case GMBOX_ERRORS_IRQ_ENABLE:
+            pDev->GMboxControlRegisters.int_status_enable |= GMBOX_INT_STATUS_TX_OVERFLOW |
+                                                             GMBOX_INT_STATUS_RX_OVERFLOW;
+            break;
+        case GMBOX_RECV_IRQ_ENABLE:
+            pDev->GMboxControlRegisters.int_status_enable |= GMBOX_INT_STATUS_RX_DATA;
+            break;
+        case GMBOX_RECV_IRQ_DISABLE:
+            pDev->GMboxControlRegisters.int_status_enable &= ~GMBOX_INT_STATUS_RX_DATA;
+            break;
+        case GMBOX_ACTION_NONE:
+        default:
+            A_ASSERT(FALSE);    
+            break;
+    }
+    
+    GMboxIntControl[0] = pDev->GMboxControlRegisters.int_status_enable;
+    GMboxIntControl[1] = GMboxIntControl[0];
+    GMboxIntControl[2] = GMboxIntControl[0];
+    GMboxIntControl[3] = GMboxIntControl[0];
+    
+    UNLOCK_AR6K(pDev);
+
+    do {
+
+        if (AsyncMode) {
+
+            pIOPacket = AR6KAllocIOPacket(pDev);
+
+            if (NULL == pIOPacket) {
+                status = A_NO_MEMORY;
+                A_ASSERT(FALSE);
+                break;
+            }
+
+                /* copy values to write to our async I/O buffer */
+            A_MEMCPY(pIOPacket->pBuffer,GMboxIntControl,sizeof(GMboxIntControl));
+
+                /* stick in our completion routine when the I/O operation completes */
+            pIOPacket->Completion = DevGMboxIRQActionAsyncHandler;
+            pIOPacket->pContext = pDev;
+            pIOPacket->PktInfo.AsRx.HTCRxFlags = IrqAction;
+                /* write it out asynchronously */
+            HIFReadWrite(pDev->HIFDevice,
+                         GMBOX_INT_STATUS_ENABLE_REG,
+                         pIOPacket->pBuffer,
+                         sizeof(GMboxIntControl),
+                         HIF_WR_ASYNC_BYTE_FIX,
+                         pIOPacket);
+            pIOPacket = NULL;
+            break;
+        }
+
+        /* if we get here we are doing it synchronously */
+
+        status = HIFReadWrite(pDev->HIFDevice,
+                              GMBOX_INT_STATUS_ENABLE_REG,
+                              GMboxIntControl,
+                              sizeof(GMboxIntControl),
+                              HIF_WR_SYNC_BYTE_FIX,
+                              NULL);
+
+    } while (FALSE);
+
+    if (A_FAILED(status)) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                (" IRQAction Operation (%d) failed! status:%d \n", IrqAction, status));    
+    } else {
+        if (!AsyncMode) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,
+                    (" IRQAction Operation (%d) success \n", IrqAction)); 
+        }      
+    }
+    
+    if (pIOPacket != NULL) {
+        AR6KFreeIOPacket(pDev,pIOPacket);
+    }
+
+    return status;
+}
+
+void DevCleanupGMbox(AR6K_DEVICE *pDev)
+{
+    if (pDev->GMboxEnabled) {
+        pDev->GMboxEnabled = FALSE;
+        GMboxProtocolUninstall(pDev);        
+    }
+}
+
+A_STATUS DevSetupGMbox(AR6K_DEVICE *pDev)
+{
+    A_STATUS    status = A_OK;
+    A_UINT8     muxControl[4];
+    
+    do {
+        
+        if (0 == pDev->MailBoxInfo.GMboxAddress) {
+            break;    
+        }
+    
+        AR_DEBUG_PRINTF(ATH_DEBUG_ANY,(" GMBOX Advertised: Address:0x%X , size:%d \n",
+                    pDev->MailBoxInfo.GMboxAddress, pDev->MailBoxInfo.GMboxSize));
+                    
+        status = DevGMboxIRQAction(pDev, GMBOX_DISABLE_ALL, PROC_IO_SYNC);
+        
+        if (A_FAILED(status)) {
+            break;    
+        }
+       
+            /* write to mailbox look ahead mux control register, we want the
+             * GMBOX lookaheads to appear on lookaheads 2 and 3 
+             * the register is 1-byte wide so we need to hit it 4 times to align the operation 
+             * to 4-bytes */            
+        muxControl[0] = GMBOX_LA_MUX_OVERRIDE_2_3;
+        muxControl[1] = GMBOX_LA_MUX_OVERRIDE_2_3;
+        muxControl[2] = GMBOX_LA_MUX_OVERRIDE_2_3;
+        muxControl[3] = GMBOX_LA_MUX_OVERRIDE_2_3;
+                
+        status = HIFReadWrite(pDev->HIFDevice,
+                              GMBOX_LOOKAHEAD_MUX_REG,
+                              muxControl,
+                              sizeof(muxControl),
+                              HIF_WR_SYNC_BYTE_FIX,  /* hit this register 4 times */
+                              NULL);
+        
+        if (A_FAILED(status)) {
+            break;    
+        }
+        
+        status = GMboxProtocolInstall(pDev);
+        
+        if (A_FAILED(status)) {
+            break;    
+        }
+        
+        pDev->GMboxEnabled = TRUE;
+        
+    } while (FALSE);
+    
+    return status;
+}
+
+A_STATUS DevCheckGMboxInterrupts(AR6K_DEVICE *pDev)
+{
+    A_STATUS status = A_OK;
+    A_UINT8  counter_int_status;
+    int      credits;
+    A_UINT8  host_int_status2;
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("+DevCheckGMboxInterrupts \n"));
+     
+    /* the caller guarantees that this is a context that allows for blocking I/O */
+    
+    do {
+        
+        host_int_status2 = pDev->IrqProcRegisters.host_int_status2 &
+                           pDev->GMboxControlRegisters.int_status_enable; 
+                
+        if (host_int_status2 & GMBOX_INT_STATUS_TX_OVERFLOW) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("GMBOX : TX Overflow \n"));  
+            status = A_ECOMM;   
+        }
+        
+        if (host_int_status2 & GMBOX_INT_STATUS_RX_OVERFLOW) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("GMBOX : RX Overflow \n"));  
+            status = A_ECOMM;    
+        }
+        
+        if (A_FAILED(status)) {
+            if (pDev->GMboxInfo.pTargetFailureCallback != NULL) {
+                pDev->GMboxInfo.pTargetFailureCallback(pDev->GMboxInfo.pProtocolContext, status);        
+            }
+            break;
+        }
+    
+        if (host_int_status2 & GMBOX_INT_STATUS_RX_DATA) {
+            if (pDev->IrqProcRegisters.gmbox_rx_avail > 0) {
+                A_ASSERT(pDev->GMboxInfo.pMessagePendingCallBack != NULL);
+                status = pDev->GMboxInfo.pMessagePendingCallBack(
+                                pDev->GMboxInfo.pProtocolContext,
+                                (A_UINT8 *)&pDev->IrqProcRegisters.rx_gmbox_lookahead_alias[0],
+                                pDev->IrqProcRegisters.gmbox_rx_avail);
+            }
+        } 
+        
+        if (A_FAILED(status)) {
+           break;                
+        }
+        
+        counter_int_status = pDev->IrqProcRegisters.counter_int_status &
+                             pDev->IrqEnableRegisters.counter_int_status_enable;
+    
+            /* check if credit interrupt is pending */
+        if (counter_int_status & (COUNTER_INT_STATUS_ENABLE_BIT_SET(1 << AR6K_GMBOX_CREDIT_COUNTER))) {
+            
+                /* do synchronous read */
+            status = DevGMboxReadCreditCounter(pDev, PROC_IO_SYNC, &credits);
+            
+            if (A_FAILED(status)) {
+                break;    
+            }
+            
+            A_ASSERT(pDev->GMboxInfo.pCreditsPendingCallback != NULL);
+            status = pDev->GMboxInfo.pCreditsPendingCallback(pDev->GMboxInfo.pProtocolContext,
+                                                             credits,
+                                                             pDev->GMboxInfo.CreditCountIRQEnabled);
+        }
+        
+    } while (FALSE);
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("-DevCheckGMboxInterrupts (%d) \n",status));
+    
+    return status;
+}
+
+
+A_STATUS DevGMboxWrite(AR6K_DEVICE *pDev, HTC_PACKET *pPacket, A_UINT32 WriteLength) 
+{
+    A_UINT32 paddedLength;
+    A_BOOL   sync = (pPacket->Completion == NULL) ? TRUE : FALSE;
+    A_STATUS status;
+    A_UINT32 address;
+    
+       /* adjust the length to be a multiple of block size if appropriate */
+    paddedLength = DEV_CALC_SEND_PADDED_LEN(pDev, WriteLength);
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_SEND,
+                ("DevGMboxWrite, Padded Length: %d Mbox:0x%X (mode:%s)\n",
+                WriteLength,
+                pDev->MailBoxInfo.GMboxAddress,
+                sync ? "SYNC" : "ASYNC"));
+                
+        /* last byte of packet has to hit the EOM marker */
+    address = pDev->MailBoxInfo.GMboxAddress + pDev->MailBoxInfo.GMboxSize - paddedLength;
+    
+    status = HIFReadWrite(pDev->HIFDevice,
+                          address,
+                          pPacket->pBuffer,
+                          paddedLength,     /* the padded length */
+                          sync ? HIF_WR_SYNC_BLOCK_INC : HIF_WR_ASYNC_BLOCK_INC,
+                          sync ? NULL : pPacket);  /* pass the packet as the context to the HIF request */
+
+    if (sync) {
+        pPacket->Status = status;
+    } else {
+        if (status == A_PENDING) {
+            status = A_OK;    
+        }    
+    }
+
+    return status;
+}
+
+A_STATUS DevGMboxRead(AR6K_DEVICE *pDev, HTC_PACKET *pPacket, A_UINT32 ReadLength) 
+{
+    
+    A_UINT32 paddedLength;
+    A_STATUS status;
+    A_BOOL   sync = (pPacket->Completion == NULL) ? TRUE : FALSE;
+
+        /* adjust the length to be a multiple of block size if appropriate */
+    paddedLength = DEV_CALC_RECV_PADDED_LEN(pDev, ReadLength);
+                    
+    if (paddedLength > pPacket->BufferLength) {
+        A_ASSERT(FALSE);
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                ("DevGMboxRead, Not enough space for padlen:%d recvlen:%d bufferlen:%d \n",
+                    paddedLength,ReadLength,pPacket->BufferLength));
+        if (pPacket->Completion != NULL) {
+            COMPLETE_HTC_PACKET(pPacket,A_EINVAL);
+            return A_OK;
+        }
+        return A_EINVAL;
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
+                ("DevGMboxRead (0x%lX : hdr:0x%X) Padded Length: %d Mbox:0x%X (mode:%s)\n",
+                (unsigned long)pPacket, pPacket->PktInfo.AsRx.ExpectedHdr,
+                paddedLength,
+                pDev->MailBoxInfo.GMboxAddress,
+                sync ? "SYNC" : "ASYNC"));
+
+    status = HIFReadWrite(pDev->HIFDevice,
+                          pDev->MailBoxInfo.GMboxAddress,
+                          pPacket->pBuffer,
+                          paddedLength,
+                          sync ? HIF_RD_SYNC_BLOCK_FIX : HIF_RD_ASYNC_BLOCK_FIX,
+                          sync ? NULL : pPacket);  /* pass the packet as the context to the HIF request */
+
+    if (sync) {
+        pPacket->Status = status;
+    }
+
+    return status;
+}
+
+
+static int ProcessCreditCounterReadBuffer(A_UINT8 *pBuffer, int Length)
+{
+    int     credits = 0;
+    
+    /* theory of how this works:
+     * We read the credit decrement register multiple times on a byte-wide basis. 
+     * The number of times (32) aligns the I/O operation to be a multiple of 4 bytes and provides a 
+     * reasonable chance to acquire "all" pending credits in a single I/O operation. 
+     * 
+     * Once we obtain the filled buffer, we can walk through it looking for credit decrement transitions.
+     * Each non-zero byte represents a single credit decrement (which is a credit given back to the host)
+     * For example if the target provides 3 credits and added 4 more during the 32-byte read operation the following
+     * pattern "could" appear:
+     * 
+     *    0x3 0x2 0x1 0x0 0x0 0x0 0x0 0x0 0x1 0x0 0x1 0x0 0x1 0x0 0x1 0x0 ......rest zeros
+     *    <--------->                     <----------------------------->
+     *         \_ credits aleady there              \_ target adding 4 more credits
+     * 
+     *    The total available credits would be 7, since there are 7 non-zero bytes in the buffer.
+     * 
+     * */
+    
+    if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_RECV)) {
+        DebugDumpBytes(pBuffer, Length, "GMBOX Credit read buffer");
+    } 
+        
+    while (Length) {
+        if (*pBuffer != 0) {
+            credits++;    
+        }
+        Length--;
+        pBuffer++;   
+    }  
+    
+    return credits;
+}
+   
+
+/* callback when our fetch to enable/disable completes */
+static void DevGMboxReadCreditsAsyncHandler(void *Context, HTC_PACKET *pPacket)
+{
+    AR6K_DEVICE *pDev = (AR6K_DEVICE *)Context;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevGMboxReadCreditsAsyncHandler: (dev: 0x%lX)\n", (unsigned long)pDev));
+
+    if (A_FAILED(pPacket->Status)) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                ("Read Credit Operation failed! status:%d \n", pPacket->Status));
+    } else {
+        int credits = 0;
+        credits = ProcessCreditCounterReadBuffer(pPacket->pBuffer, AR6K_REG_IO_BUFFER_SIZE);
+        pDev->GMboxInfo.pCreditsPendingCallback(pDev->GMboxInfo.pProtocolContext,
+                                                credits,
+                                                pDev->GMboxInfo.CreditCountIRQEnabled);
+        
+        
+    }
+        /* free this IO packet */
+    AR6KFreeIOPacket(pDev,pPacket);
+    AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevGMboxReadCreditsAsyncHandler \n"));
+}
+
+A_STATUS DevGMboxReadCreditCounter(AR6K_DEVICE *pDev, A_BOOL AsyncMode, int *pCredits)
+{
+    A_STATUS    status = A_OK;
+    HTC_PACKET  *pIOPacket = NULL;  
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("+DevGMboxReadCreditCounter (%s) \n", AsyncMode ? "ASYNC" : "SYNC"));
+                                            
+    do {
+        
+        pIOPacket = AR6KAllocIOPacket(pDev);
+
+        if (NULL == pIOPacket) {
+            status = A_NO_MEMORY;
+            A_ASSERT(FALSE);
+            break;
+        }
+        
+        A_MEMZERO(pIOPacket->pBuffer,AR6K_REG_IO_BUFFER_SIZE);
+      
+        if (AsyncMode) {   
+                /* stick in our completion routine when the I/O operation completes */
+            pIOPacket->Completion = DevGMboxReadCreditsAsyncHandler;
+            pIOPacket->pContext = pDev;
+                /* read registers asynchronously */
+            HIFReadWrite(pDev->HIFDevice,
+                         AR6K_GMBOX_CREDIT_DEC_ADDRESS,
+                         pIOPacket->pBuffer,
+                         AR6K_REG_IO_BUFFER_SIZE,  /* hit the register multiple times */
+                         HIF_RD_ASYNC_BYTE_FIX,
+                         pIOPacket);
+            pIOPacket = NULL;
+            break;
+        } 
+
+        pIOPacket->Completion = NULL;
+            /* if we get here we are doing it synchronously */
+        status = HIFReadWrite(pDev->HIFDevice,
+                              AR6K_GMBOX_CREDIT_DEC_ADDRESS,
+                              pIOPacket->pBuffer,
+                              AR6K_REG_IO_BUFFER_SIZE,
+                              HIF_RD_SYNC_BYTE_FIX,
+                              NULL);    
+    } while (FALSE);
+    
+    if (A_FAILED(status)) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                (" DevGMboxReadCreditCounter failed! status:%d \n", status));          
+    }
+    
+    if (pIOPacket != NULL) {
+        if (A_SUCCESS(status)) {
+                /* sync mode processing */
+            *pCredits = ProcessCreditCounterReadBuffer(pIOPacket->pBuffer, AR6K_REG_IO_BUFFER_SIZE);     
+        }
+        AR6KFreeIOPacket(pDev,pIOPacket);
+    }
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("-DevGMboxReadCreditCounter (%s) (%d) \n", 
+            AsyncMode ? "ASYNC" : "SYNC", status));
+    
+    return status;
+}
+
+A_STATUS DevGMboxReadCreditSize(AR6K_DEVICE *pDev, int *pCreditSize)
+{
+    A_STATUS    status;
+    A_UINT8     buffer[4];
+       
+    status = HIFReadWrite(pDev->HIFDevice,
+                          AR6K_GMBOX_CREDIT_SIZE_ADDRESS,
+                          buffer,
+                          sizeof(buffer),
+                          HIF_RD_SYNC_BYTE_FIX, /* hit the register 4 times to align the I/O */
+                          NULL);    
+    
+    if (A_SUCCESS(status)) {
+        if (buffer[0] == 0) {
+            *pCreditSize = 256;    
+        } else {   
+            *pCreditSize = buffer[0];
+        } 
+           
+    } 
+    
+    return status;
+}
+
+void DevNotifyGMboxTargetFailure(AR6K_DEVICE *pDev)
+{
+        /* Target ASSERTED!!! */
+    if (pDev->GMboxInfo.pTargetFailureCallback != NULL) {
+        pDev->GMboxInfo.pTargetFailureCallback(pDev->GMboxInfo.pProtocolContext, A_HARDWARE);        
+    }
+}
+
+A_STATUS DevGMboxRecvLookAheadPeek(AR6K_DEVICE *pDev, A_UINT8 *pLookAheadBuffer, int *pLookAheadBytes)
+{
+
+    A_STATUS                    status = A_OK;
+    AR6K_IRQ_PROC_REGISTERS     procRegs;
+    int                         maxCopy;
+  
+    do {
+            /* on entry the caller provides the length of the lookahead buffer */
+        if (*pLookAheadBytes > sizeof(procRegs.rx_gmbox_lookahead_alias)) {
+            A_ASSERT(FALSE);
+            status = A_EINVAL;
+            break;    
+        }
+        
+        maxCopy = *pLookAheadBytes;
+        *pLookAheadBytes = 0;
+            /* load the register table from the device */
+        status = HIFReadWrite(pDev->HIFDevice,
+                              HOST_INT_STATUS_ADDRESS,
+                              (A_UINT8 *)&procRegs,
+                              AR6K_IRQ_PROC_REGS_SIZE,
+                              HIF_RD_SYNC_BYTE_INC,
+                              NULL);
+
+        if (A_FAILED(status)) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                ("DevGMboxRecvLookAheadPeek : Failed to read register table (%d) \n",status));
+            break;
+        }
+        
+        if (procRegs.gmbox_rx_avail > 0) {
+            int bytes = procRegs.gmbox_rx_avail > maxCopy ? maxCopy : procRegs.gmbox_rx_avail;
+            A_MEMCPY(pLookAheadBuffer,&procRegs.rx_gmbox_lookahead_alias[0],bytes);
+            *pLookAheadBytes = bytes;
+        }
+        
+    } while (FALSE);
+       
+    return status; 
+}
+
+A_STATUS DevGMboxSetTargetInterrupt(AR6K_DEVICE *pDev, int Signal, int AckTimeoutMS)
+{
+    A_STATUS status = A_OK;
+    int      i;
+    A_UINT8  buffer[4];
+    
+    A_MEMZERO(buffer, sizeof(buffer));
+    
+    do {
+        
+        if (Signal >= MBOX_SIG_HCI_BRIDGE_MAX) {
+            status = A_EINVAL;
+            break;    
+        }
+        
+            /* set the last buffer to do the actual signal trigger */
+        buffer[3] = (1 << Signal);
+        
+        status = HIFReadWrite(pDev->HIFDevice,
+                              INT_WLAN_ADDRESS,
+                              buffer,
+                              sizeof(buffer),
+                              HIF_WR_SYNC_BYTE_FIX, /* hit the register 4 times to align the I/O */
+                              NULL);    
+                          
+        if (A_FAILED(status)) {
+            break;    
+        }
+        
+    } while (FALSE);
+    
+    
+    if (A_SUCCESS(status)) {        
+            /* now read back the register to see if the bit cleared */
+        while (AckTimeoutMS) {        
+            status = HIFReadWrite(pDev->HIFDevice,
+                                  INT_WLAN_ADDRESS,
+                                  buffer,
+                                  sizeof(buffer),
+                                  HIF_RD_SYNC_BYTE_FIX,
+                                  NULL);    
+                          
+            if (A_FAILED(status)) {
+                break;    
+            }
+                            
+            for (i = 0; i < sizeof(buffer); i++) {
+                if (buffer[i] & (1 << Signal)) {
+                    /* bit is still set */
+                    break;    
+                }   
+            }
+            
+            if (i >= sizeof(buffer)) {
+                /* done */
+                break;    
+            }
+            
+            AckTimeoutMS--;
+            A_MDELAY(1);  
+        }
+        
+        if (0 == AckTimeoutMS) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                ("DevGMboxSetTargetInterrupt : Ack Timed-out (sig:%d) \n",Signal));
+            status = A_ERROR;    
+        }        
+    }
+    
+    return status;
+    
+}
+
+#endif  //ATH_AR6K_ENABLE_GMBOX
+
+
+
+
diff --git a/drivers/net/ath6kl/htc2/AR6000/ar6k_gmbox_hciuart.c b/drivers/net/ath6kl/htc2/AR6000/ar6k_gmbox_hciuart.c
new file mode 100644
index 00000000000..db6d30c113b
--- /dev/null
+++ b/drivers/net/ath6kl/htc2/AR6000/ar6k_gmbox_hciuart.c
@@ -0,0 +1,1280 @@
+//------------------------------------------------------------------------------
+// <copyright file="ar6k_prot_hciUart.c" company="Atheros">
+//    Copyright (c) 2007-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Protocol module for use in bridging HCI-UART packets over the GMBOX interface
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#include "a_config.h"
+#include "athdefs.h"
+#include "a_types.h"
+#include "a_osapi.h"
+#include "../htc_debug.h"
+#include "hif.h"
+#include "htc_packet.h"
+#include "ar6k.h"
+#include "hci_transport_api.h"
+#include "gmboxif.h"
+#include "ar6000_diag.h"
+#include "hw/apb_map.h"
+#include "hw/mbox_reg.h"
+
+#ifdef ATH_AR6K_ENABLE_GMBOX
+#define HCI_UART_COMMAND_PKT 0x01
+#define HCI_UART_ACL_PKT     0x02
+#define HCI_UART_SCO_PKT     0x03
+#define HCI_UART_EVENT_PKT   0x04
+
+#define HCI_RECV_WAIT_BUFFERS (1 << 0)
+
+#define HCI_SEND_WAIT_CREDITS (1 << 0)
+
+#define HCI_UART_BRIDGE_CREDIT_SIZE     128
+
+#define CREDIT_POLL_COUNT       256
+
+#define HCI_DELAY_PER_INTERVAL_MS 10 
+#define BTON_TIMEOUT_MS           500
+#define BTOFF_TIMEOUT_MS          500
+#define BAUD_TIMEOUT_MS           1
+#define BTPWRSAV_TIMEOUT_MS       1  
+
+typedef struct {
+    HCI_TRANSPORT_CONFIG_INFO   HCIConfig;
+    A_BOOL                      HCIAttached;
+    A_BOOL                      HCIStopped;
+    A_UINT32                    RecvStateFlags;
+    A_UINT32                    SendStateFlags;
+    HCI_TRANSPORT_PACKET_TYPE   WaitBufferType;
+    HTC_PACKET_QUEUE            SendQueue;         /* write queue holding HCI Command and ACL packets */
+    HTC_PACKET_QUEUE            HCIACLRecvBuffers;  /* recv queue holding buffers for incomming ACL packets */
+    HTC_PACKET_QUEUE            HCIEventBuffers;    /* recv queue holding buffers for incomming event packets */
+    AR6K_DEVICE                 *pDev;
+    A_MUTEX_T                   HCIRxLock;
+    A_MUTEX_T                   HCITxLock;
+    int                         CreditsMax;
+    int                         CreditsConsumed;
+    int                         CreditsAvailable;
+    int                         CreditSize;
+    int                         CreditsCurrentSeek;
+    int                         SendProcessCount;
+} GMBOX_PROTO_HCI_UART;
+
+#define LOCK_HCI_RX(t)   A_MUTEX_LOCK(&(t)->HCIRxLock);
+#define UNLOCK_HCI_RX(t) A_MUTEX_UNLOCK(&(t)->HCIRxLock);
+#define LOCK_HCI_TX(t)   A_MUTEX_LOCK(&(t)->HCITxLock);
+#define UNLOCK_HCI_TX(t) A_MUTEX_UNLOCK(&(t)->HCITxLock);
+
+#define DO_HCI_RECV_INDICATION(p,pt) \
+{   AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("HCI: Indicate Recv on packet:0x%lX status:%d len:%d type:%d \n",  \
+      (unsigned long)(pt),(pt)->Status, A_SUCCESS((pt)->Status) ? (pt)->ActualLength : 0, HCI_GET_PACKET_TYPE(pt))); \
+    (p)->HCIConfig.pHCIPktRecv((p)->HCIConfig.pContext, (pt));                                 \
+}
+
+#define DO_HCI_SEND_INDICATION(p,pt) \
+{   AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("HCI: Indicate Send on packet:0x%lX status:%d type:%d \n",  \
+            (unsigned long)(pt),(pt)->Status,HCI_GET_PACKET_TYPE(pt)));                             \
+    (p)->HCIConfig.pHCISendComplete((p)->HCIConfig.pContext, (pt));                            \
+}
+    
+static A_STATUS HCITrySend(GMBOX_PROTO_HCI_UART *pProt, HTC_PACKET *pPacket, A_BOOL Synchronous);
+
+static void HCIUartCleanup(GMBOX_PROTO_HCI_UART *pProtocol)
+{
+    A_ASSERT(pProtocol != NULL);
+    
+    A_MUTEX_DELETE(&pProtocol->HCIRxLock);
+    A_MUTEX_DELETE(&pProtocol->HCITxLock);
+        
+    A_FREE(pProtocol);    
+}
+
+static A_STATUS InitTxCreditState(GMBOX_PROTO_HCI_UART *pProt)
+{
+    A_STATUS    status;
+    int         credits;
+    int         creditPollCount = CREDIT_POLL_COUNT;
+    A_BOOL      gotCredits = FALSE;
+
+    pProt->CreditsConsumed = 0;
+    
+    do {    
+        
+        if (pProt->CreditsMax != 0) {
+            /* we can only call this only once per target reset */
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("HCI: InitTxCreditState - already called!  \n"));
+            A_ASSERT(FALSE);
+            status = A_EINVAL;
+            break; 
+        }
+        
+        /* read the credit counter. At startup the target will set the credit counter
+         * to the max available, we read this in a loop because it may take
+         * multiple credit counter reads to get all credits  */
+                 
+        while (creditPollCount) {
+            
+            credits = 0;
+
+            status = DevGMboxReadCreditCounter(pProt->pDev, PROC_IO_SYNC, &credits);
+    
+            if (A_FAILED(status)) {
+                break;    
+            }
+            
+            if (!gotCredits && (0 == credits)) {
+                creditPollCount--;
+                AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("HCI: credit is 0, retrying (%d)  \n",creditPollCount));
+                A_MDELAY(HCI_DELAY_PER_INTERVAL_MS);
+                continue;  
+            } else {
+                gotCredits = TRUE;    
+            }
+            
+            if (0 == credits) {
+                break;    
+            }
+            
+            pProt->CreditsMax += credits;
+        }
+        
+        if (A_FAILED(status)) {
+            break;    
+        }
+        
+        if (0 == creditPollCount) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                    ("** HCI : Failed to get credits! GMBOX Target was not available \n"));        
+            status = A_ERROR;
+            break;
+        }
+        
+            /* now get the size */
+        status = DevGMboxReadCreditSize(pProt->pDev, &pProt->CreditSize);
+        
+        if (A_FAILED(status)) {
+            break;    
+        }
+               
+    } while (FALSE);
+    
+    if (A_SUCCESS(status)) {
+        pProt->CreditsAvailable = pProt->CreditsMax;
+        AR_DEBUG_PRINTF(ATH_DEBUG_ANY,("HCI : InitTxCreditState - credits avail: %d, size: %d \n",
+            pProt->CreditsAvailable, pProt->CreditSize));    
+    }    
+    
+    return status;
+}
+
+static A_STATUS CreditsAvailableCallback(void *pContext, int Credits, A_BOOL CreditIRQEnabled)
+{
+    GMBOX_PROTO_HCI_UART *pProt = (GMBOX_PROTO_HCI_UART *)pContext;    
+    A_BOOL               enableCreditIrq = FALSE;   
+    A_BOOL               disableCreditIrq = FALSE;
+    A_BOOL               doPendingSends = FALSE;
+    A_STATUS             status = A_OK;
+    
+    /** this callback is called under 2 conditions:
+     *   1. The credit IRQ interrupt was enabled and signaled.
+     *   2. A credit counter read completed.
+     * 
+     *   The function must not assume that the calling context can block !
+     */
+     
+    AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("+CreditsAvailableCallback (Credits:%d, IRQ:%s) \n",
+                Credits, CreditIRQEnabled ? "ON" : "OFF"));
+    
+    LOCK_HCI_TX(pProt);
+    
+    do {
+        
+        if (0 == Credits) {
+            if (!CreditIRQEnabled) {
+                    /* enable credit IRQ */
+                enableCreditIrq = TRUE;    
+            }
+            break;
+        }
+        
+        AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("HCI: current credit state, consumed:%d available:%d max:%d seek:%d\n",
+                         pProt->CreditsConsumed, 
+                         pProt->CreditsAvailable,  
+                         pProt->CreditsMax,
+                         pProt->CreditsCurrentSeek));
+                         
+        pProt->CreditsAvailable += Credits;
+        A_ASSERT(pProt->CreditsAvailable <= pProt->CreditsMax);
+        pProt->CreditsConsumed  -= Credits;
+        A_ASSERT(pProt->CreditsConsumed >= 0);
+            
+        AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("HCI: new credit state, consumed:%d available:%d max:%d seek:%d\n",
+                         pProt->CreditsConsumed, 
+                         pProt->CreditsAvailable,  
+                         pProt->CreditsMax,
+                         pProt->CreditsCurrentSeek));
+        
+        if (pProt->CreditsAvailable >= pProt->CreditsCurrentSeek) {
+                /* we have enough credits to fullfill at least 1 packet waiting in the queue */
+            pProt->CreditsCurrentSeek = 0;
+            pProt->SendStateFlags &= ~HCI_SEND_WAIT_CREDITS;  
+            doPendingSends = TRUE;  
+            if (CreditIRQEnabled) {
+                    /* credit IRQ was enabled, we shouldn't need it anymore */
+                disableCreditIrq = TRUE;    
+            }      
+        } else {
+                /* not enough credits yet, enable credit IRQ if we haven't already */
+            if (!CreditIRQEnabled) {               
+                enableCreditIrq = TRUE;    
+            }    
+        }
+                      
+    } while (FALSE);
+    
+    UNLOCK_HCI_TX(pProt);
+
+    if (enableCreditIrq) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_RECV,(" Enabling credit count IRQ...\n"));
+            /* must use async only */
+        status = DevGMboxIRQAction(pProt->pDev, GMBOX_CREDIT_IRQ_ENABLE, PROC_IO_ASYNC);    
+    } else if (disableCreditIrq) {
+            /* must use async only */
+        AR_DEBUG_PRINTF(ATH_DEBUG_RECV,(" Disabling credit count IRQ...\n"));
+        status = DevGMboxIRQAction(pProt->pDev, GMBOX_CREDIT_IRQ_DISABLE, PROC_IO_ASYNC); 
+    }
+       
+    if (doPendingSends) {
+        HCITrySend(pProt, NULL, FALSE);
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("+CreditsAvailableCallback \n"));
+    return status;
+}
+
+static INLINE void NotifyTransportFailure(GMBOX_PROTO_HCI_UART  *pProt, A_STATUS status)
+{
+    if (pProt->HCIConfig.TransportFailure != NULL) {
+        pProt->HCIConfig.TransportFailure(pProt->HCIConfig.pContext, status);
+    }
+}
+
+static void FailureCallback(void *pContext, A_STATUS Status)
+{
+    GMBOX_PROTO_HCI_UART  *pProt = (GMBOX_PROTO_HCI_UART *)pContext; 
+    
+        /* target assertion occured */           
+    NotifyTransportFailure(pProt, Status);  
+}
+
+static void StateDumpCallback(void *pContext)
+{
+    GMBOX_PROTO_HCI_UART  *pProt = (GMBOX_PROTO_HCI_UART *)pContext;
+   
+    AR_DEBUG_PRINTF(ATH_DEBUG_ANY,("============ HCIUart State ======================\n"));    
+    AR_DEBUG_PRINTF(ATH_DEBUG_ANY,("RecvStateFlags   :  0x%X \n",pProt->RecvStateFlags));
+    AR_DEBUG_PRINTF(ATH_DEBUG_ANY,("SendStateFlags   :  0x%X \n",pProt->SendStateFlags));
+    AR_DEBUG_PRINTF(ATH_DEBUG_ANY,("WaitBufferType   :  %d   \n",pProt->WaitBufferType));
+    AR_DEBUG_PRINTF(ATH_DEBUG_ANY,("SendQueue Depth  :  %d   \n",HTC_PACKET_QUEUE_DEPTH(&pProt->SendQueue)));
+    AR_DEBUG_PRINTF(ATH_DEBUG_ANY,("CreditsMax       :  %d   \n",pProt->CreditsMax));
+    AR_DEBUG_PRINTF(ATH_DEBUG_ANY,("CreditsConsumed  :  %d   \n",pProt->CreditsConsumed));
+    AR_DEBUG_PRINTF(ATH_DEBUG_ANY,("CreditsAvailable :  %d   \n",pProt->CreditsAvailable));
+    AR_DEBUG_PRINTF(ATH_DEBUG_ANY,("==================================================\n"));
+}
+
+static A_STATUS HCIUartMessagePending(void *pContext, A_UINT8 LookAheadBytes[], int ValidBytes)
+{
+    GMBOX_PROTO_HCI_UART        *pProt = (GMBOX_PROTO_HCI_UART *)pContext;
+    A_STATUS                    status = A_OK;
+    int                         totalRecvLength = 0;
+    HCI_TRANSPORT_PACKET_TYPE   pktType = HCI_PACKET_INVALID;
+    A_BOOL                      recvRefillCalled = FALSE;
+    A_BOOL                      blockRecv = FALSE;
+    HTC_PACKET                  *pPacket = NULL;
+    
+    /** caller guarantees that this is a fully block-able context (synch I/O is allowed) */
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("+HCIUartMessagePending Lookahead Bytes:%d \n",ValidBytes));
+    
+    LOCK_HCI_RX(pProt);
+        
+    do {
+    
+        if (ValidBytes < 3) {
+                /* not enough for ACL or event header */
+            break;    
+        }    
+        
+        if ((LookAheadBytes[0] == HCI_UART_ACL_PKT) && (ValidBytes < 5)) {
+                /* not enough for ACL data header */
+            break;    
+        }
+                
+        switch (LookAheadBytes[0]) {       
+            case HCI_UART_EVENT_PKT:
+                AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("HCI Event: %d param length: %d \n",
+                        LookAheadBytes[1], LookAheadBytes[2]));
+                totalRecvLength = LookAheadBytes[2];
+                totalRecvLength += 3; /* add type + event code + length field */
+                pktType = HCI_EVENT_TYPE;      
+                break;
+            case HCI_UART_ACL_PKT:                
+                totalRecvLength = (LookAheadBytes[4] << 8) | LookAheadBytes[3];                
+                AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("HCI ACL: conn:0x%X length: %d \n",
+                        ((LookAheadBytes[2] & 0xF0) << 8) | LookAheadBytes[1], totalRecvLength));
+                totalRecvLength += 5; /* add type + connection handle + length field */
+                pktType = HCI_ACL_TYPE;           
+                break;        
+            default:
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("**Invalid HCI packet type: %d \n",LookAheadBytes[0]));
+                status = A_EPROTO;
+                break;
+        }
+        
+        if (A_FAILED(status)) {
+            break;    
+        }
+                
+        if (pProt->HCIConfig.pHCIPktRecvAlloc != NULL) {
+            UNLOCK_HCI_RX(pProt);
+                /* user is using a per-packet allocation callback */
+            pPacket = pProt->HCIConfig.pHCIPktRecvAlloc(pProt->HCIConfig.pContext,
+                                                        pktType,
+                                                        totalRecvLength);
+            LOCK_HCI_RX(pProt);
+    
+        } else {
+            HTC_PACKET_QUEUE *pQueue;
+                /* user is using a refill handler that can refill multiple HTC buffers */
+            
+                /* select buffer queue */
+            if (pktType == HCI_ACL_TYPE) {
+                pQueue = &pProt->HCIACLRecvBuffers;    
+            } else {
+                pQueue = &pProt->HCIEventBuffers;              
+            }    
+            
+            if (HTC_QUEUE_EMPTY(pQueue)) {
+                AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
+                    ("** HCI pkt type: %d has no buffers available calling allocation handler \n", 
+                    pktType));
+                    /* check for refill handler */
+                if (pProt->HCIConfig.pHCIPktRecvRefill != NULL) {
+                    recvRefillCalled = TRUE;
+                    UNLOCK_HCI_RX(pProt);
+                        /* call the re-fill handler */
+                    pProt->HCIConfig.pHCIPktRecvRefill(pProt->HCIConfig.pContext,
+                                                       pktType,
+                                                       0);
+                    LOCK_HCI_RX(pProt);
+                        /* check if we have more buffers */
+                    pPacket = HTC_PACKET_DEQUEUE(pQueue);
+                        /* fall through */
+                }
+            } else {
+                pPacket = HTC_PACKET_DEQUEUE(pQueue);
+                AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
+                    ("HCI pkt type: %d now has %d recv buffers left \n", 
+                            pktType, HTC_PACKET_QUEUE_DEPTH(pQueue)));    
+            }
+        }
+     
+        if (NULL == pPacket) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
+                    ("** HCI pkt type: %d has no buffers available stopping recv...\n", pktType));
+                /* this is not an error, we simply need to mark that we are waiting for buffers.*/
+            pProt->RecvStateFlags |= HCI_RECV_WAIT_BUFFERS;
+            pProt->WaitBufferType = pktType;
+            blockRecv = TRUE;
+            break;
+        }
+        
+        if (totalRecvLength > (int)pPacket->BufferLength) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("** HCI-UART pkt: %d requires %d bytes (%d buffer bytes avail) ! \n",
+                LookAheadBytes[0], totalRecvLength, pPacket->BufferLength));
+            status = A_EINVAL;
+            break;
+        }
+        
+    } while (FALSE);
+    
+    UNLOCK_HCI_RX(pProt);
+    
+        /* locks are released, we can go fetch the packet */
+        
+    do {
+        
+        if (A_FAILED(status) || (NULL == pPacket)) {
+            break;    
+        } 
+        
+            /* do this synchronously, we don't need to be fast here */
+        pPacket->Completion = NULL;
+        
+        AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("HCI : getting recv packet len:%d hci-uart-type: %s \n",
+                totalRecvLength, (LookAheadBytes[0] == HCI_UART_EVENT_PKT) ? "EVENT" : "ACL"));
+                
+        status = DevGMboxRead(pProt->pDev, pPacket, totalRecvLength);     
+        
+        if (A_FAILED(status)) {
+            break;    
+        }
+        
+        if (pPacket->pBuffer[0] != LookAheadBytes[0]) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("** HCI buffer does not contain expected packet type: %d ! \n",
+                        pPacket->pBuffer[0]));
+            status = A_EPROTO;
+            break;   
+        }
+        
+        if (pPacket->pBuffer[0] == HCI_UART_EVENT_PKT) {
+                /* validate event header fields */
+            if ((pPacket->pBuffer[1] != LookAheadBytes[1]) ||
+                (pPacket->pBuffer[2] != LookAheadBytes[2])) {
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("** HCI buffer does not match lookahead! \n"));
+                DebugDumpBytes(LookAheadBytes, 3, "Expected HCI-UART Header");  
+                DebugDumpBytes(pPacket->pBuffer, 3, "** Bad HCI-UART Header");  
+                status = A_EPROTO;
+                break;       
+            }   
+        } else if (pPacket->pBuffer[0] == HCI_UART_ACL_PKT) {
+                /* validate acl header fields */
+            if ((pPacket->pBuffer[1] != LookAheadBytes[1]) ||
+                (pPacket->pBuffer[2] != LookAheadBytes[2]) ||
+                (pPacket->pBuffer[3] != LookAheadBytes[3]) ||
+                (pPacket->pBuffer[4] != LookAheadBytes[4])) {
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("** HCI buffer does not match lookahead! \n"));
+                DebugDumpBytes(LookAheadBytes, 5, "Expected HCI-UART Header");  
+                DebugDumpBytes(pPacket->pBuffer, 5, "** Bad HCI-UART Header");  
+                status = A_EPROTO;
+                break;       
+            }   
+        }
+        
+            /* adjust buffer to move past packet ID */
+        pPacket->pBuffer++;
+        pPacket->ActualLength = totalRecvLength - 1;
+        pPacket->Status = A_OK;
+            /* indicate packet */
+        DO_HCI_RECV_INDICATION(pProt,pPacket);
+        pPacket = NULL;
+        
+            /* check if we need to refill recv buffers */        
+        if ((pProt->HCIConfig.pHCIPktRecvRefill != NULL) && !recvRefillCalled) {           
+            HTC_PACKET_QUEUE *pQueue;
+            int              watermark;
+
+            if (pktType == HCI_ACL_TYPE) {
+                watermark = pProt->HCIConfig.ACLRecvBufferWaterMark;
+                pQueue = &pProt->HCIACLRecvBuffers;    
+            } else {
+                watermark = pProt->HCIConfig.EventRecvBufferWaterMark;     
+                pQueue = &pProt->HCIEventBuffers;        
+            }    
+            
+            if (HTC_PACKET_QUEUE_DEPTH(pQueue) < watermark) {
+                AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
+                    ("** HCI pkt type: %d watermark hit (%d) current:%d \n", 
+                    pktType, watermark, HTC_PACKET_QUEUE_DEPTH(pQueue)));
+                    /* call the re-fill handler */
+                pProt->HCIConfig.pHCIPktRecvRefill(pProt->HCIConfig.pContext,
+                                                   pktType,
+                                                   HTC_PACKET_QUEUE_DEPTH(pQueue));
+            }
+        }   
+        
+    } while (FALSE);
+        
+        /* check if we need to disable the reciever */
+    if (A_FAILED(status) || blockRecv) {
+        DevGMboxIRQAction(pProt->pDev, GMBOX_RECV_IRQ_DISABLE, PROC_IO_SYNC); 
+    }
+    
+        /* see if we need to recycle the recv buffer */    
+    if (A_FAILED(status) && (pPacket != NULL)) {
+        HTC_PACKET_QUEUE queue;
+        
+        if (A_EPROTO == status) {
+            DebugDumpBytes(pPacket->pBuffer, totalRecvLength, "Bad HCI-UART Recv packet");    
+        }
+            /* recycle packet */
+        HTC_PACKET_RESET_RX(pPacket);
+        INIT_HTC_PACKET_QUEUE_AND_ADD(&queue,pPacket);
+        HCI_TransportAddReceivePkts(pProt,&queue);
+        NotifyTransportFailure(pProt,status);    
+    }
+    
+ 
+    AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("-HCIUartMessagePending \n"));
+    
+    return status;
+}
+
+static void HCISendPacketCompletion(void *Context, HTC_PACKET *pPacket)
+{
+    GMBOX_PROTO_HCI_UART *pProt = (GMBOX_PROTO_HCI_UART *)Context;
+    AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("+HCISendPacketCompletion (pPacket:0x%lX) \n",(unsigned long)pPacket));
+    
+    if (A_FAILED(pPacket->Status)) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" Send Packet (0x%lX) failed: %d , len:%d \n",
+            (unsigned long)pPacket, pPacket->Status, pPacket->ActualLength));        
+    }
+    
+    DO_HCI_SEND_INDICATION(pProt,pPacket);
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("+HCISendPacketCompletion \n"));
+}
+
+static A_STATUS SeekCreditsSynch(GMBOX_PROTO_HCI_UART *pProt)
+{
+    A_STATUS status = A_OK;
+    int      credits;
+    int      retry = 100;
+    
+    while (TRUE) {                
+        credits = 0;
+        status =  DevGMboxReadCreditCounter(pProt->pDev, PROC_IO_SYNC, &credits);   
+        if (A_FAILED(status)) {
+            break;    
+        }
+        LOCK_HCI_TX(pProt);
+        pProt->CreditsAvailable += credits;        
+        pProt->CreditsConsumed -= credits;        
+        if (pProt->CreditsAvailable >= pProt->CreditsCurrentSeek) {
+            pProt->CreditsCurrentSeek = 0;
+            UNLOCK_HCI_TX(pProt);
+            break;    
+        }
+        UNLOCK_HCI_TX(pProt);
+        retry--;
+        if (0 == retry) {
+            status = A_EBUSY;
+            break;    
+        }
+        A_MDELAY(20);
+    }   
+    
+    return status;
+}
+
+static A_STATUS HCITrySend(GMBOX_PROTO_HCI_UART *pProt, HTC_PACKET *pPacket, A_BOOL Synchronous)
+{   
+    A_STATUS    status = A_OK;
+    int         transferLength;
+    int         creditsRequired, remainder;
+    A_UINT8     hciUartType;
+    A_BOOL      synchSendComplete = FALSE;
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("+HCITrySend (pPacket:0x%lX) %s \n",(unsigned long)pPacket,
+            Synchronous ? "SYNC" :"ASYNC"));
+    
+    LOCK_HCI_TX(pProt);
+     
+        /* increment write processing count on entry */    
+    pProt->SendProcessCount++;
+        
+    do {
+                                             
+        if (pProt->HCIStopped) {
+            status = A_ECANCELED;
+            break;     
+        }   
+         
+        if (pPacket != NULL) {  
+                /* packet was supplied */     
+            if (Synchronous) {
+                    /* in synchronous mode, the send queue can only hold 1 packet */
+                if (!HTC_QUEUE_EMPTY(&pProt->SendQueue)) {
+                    status = A_EBUSY;
+                    A_ASSERT(FALSE);
+                    break;    
+                }             
+                
+                if (pProt->SendProcessCount > 1) {
+                        /* another thread or task is draining the TX queues  */
+                    status = A_EBUSY;
+                    A_ASSERT(FALSE);
+                    break;
+                } 
+                  
+                HTC_PACKET_ENQUEUE(&pProt->SendQueue,pPacket);
+                
+            } else {
+                    /* see if adding this packet hits the max depth (asynchronous mode only) */
+                if ((pProt->HCIConfig.MaxSendQueueDepth > 0) && 
+                    ((HTC_PACKET_QUEUE_DEPTH(&pProt->SendQueue) + 1) >= pProt->HCIConfig.MaxSendQueueDepth)) {
+                    AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("HCI Send queue is full, Depth:%d, Max:%d \n",
+                            HTC_PACKET_QUEUE_DEPTH(&pProt->SendQueue), 
+                            pProt->HCIConfig.MaxSendQueueDepth));
+                        /* queue will be full, invoke any callbacks to determine what action to take */
+                    if (pProt->HCIConfig.pHCISendFull != NULL) {
+                        AR_DEBUG_PRINTF(ATH_DEBUG_SEND, 
+                                    ("HCI : Calling driver's send full callback.... \n"));
+                        if (pProt->HCIConfig.pHCISendFull(pProt->HCIConfig.pContext,
+                                                          pPacket) == HCI_SEND_FULL_DROP) {
+                                /* drop it */
+                            status = A_NO_RESOURCE;      
+                            break;
+                        }
+                    }               
+                }
+          
+                HTC_PACKET_ENQUEUE(&pProt->SendQueue,pPacket);
+            }
+
+        }
+               
+        if (pProt->SendStateFlags & HCI_SEND_WAIT_CREDITS) {
+            break;   
+        }
+
+        if (pProt->SendProcessCount > 1) {
+                /* another thread or task is draining the TX queues  */
+            break;
+        }
+    
+        /***** beyond this point only 1 thread may enter ******/
+           
+        /* now drain the send queue for transmission as long as we have enough
+         * credits */
+        while (!HTC_QUEUE_EMPTY(&pProt->SendQueue)) {
+            
+            pPacket = HTC_PACKET_DEQUEUE(&pProt->SendQueue);
+
+            switch (HCI_GET_PACKET_TYPE(pPacket)) {            
+                case HCI_COMMAND_TYPE:
+                    hciUartType = HCI_UART_COMMAND_PKT;
+                    break;
+                case HCI_ACL_TYPE:
+                    hciUartType = HCI_UART_ACL_PKT;
+                    break;
+                default:
+                    status = A_EINVAL;
+                    A_ASSERT(FALSE);
+                    break;
+            }
+                       
+            if (A_FAILED(status)) {
+                break;   
+            }
+            
+            AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("HCI: Got head packet:0x%lX , Type:%d  Length: %d Remaining Queue Depth: %d\n",
+                (unsigned long)pPacket, HCI_GET_PACKET_TYPE(pPacket), pPacket->ActualLength, 
+                HTC_PACKET_QUEUE_DEPTH(&pProt->SendQueue)));
+        
+            transferLength = 1;  /* UART type header is 1 byte */
+            transferLength += pPacket->ActualLength;
+            transferLength = DEV_CALC_SEND_PADDED_LEN(pProt->pDev, transferLength);
+                   
+                /* figure out how many credits this message requires */
+            creditsRequired = transferLength / pProt->CreditSize;
+            remainder = transferLength % pProt->CreditSize;
+
+            if (remainder) {
+                creditsRequired++;
+            }
+
+            AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("HCI: Creds Required:%d   Got:%d\n",
+                            creditsRequired, pProt->CreditsAvailable));
+            
+            if (creditsRequired > pProt->CreditsAvailable) {
+                if (Synchronous) {
+                        /* in synchronous mode we need to seek credits in synchronously */
+                    pProt->CreditsCurrentSeek = creditsRequired;
+                    UNLOCK_HCI_TX(pProt);
+                    status = SeekCreditsSynch(pProt);
+                    LOCK_HCI_TX(pProt);
+                    if (A_FAILED(status)) {
+                        break;    
+                    }                    
+                    /* fall through and continue processing this send op */                    
+                } else {
+                        /* not enough credits, queue back to the head */
+                    HTC_PACKET_ENQUEUE_TO_HEAD(&pProt->SendQueue,pPacket);
+                        /* waiting for credits */
+                    pProt->SendStateFlags |= HCI_SEND_WAIT_CREDITS;
+                        /* provide a hint to reduce attempts to re-send if credits are dribbling back
+                         * this hint is the short fall of credits */
+                    pProt->CreditsCurrentSeek = creditsRequired;
+                    AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("HCI: packet:0x%lX placed back in queue. head packet needs: %d credits \n",
+                                        (unsigned long)pPacket, pProt->CreditsCurrentSeek));
+                    pPacket = NULL;
+                    UNLOCK_HCI_TX(pProt);
+                    
+                        /* schedule a credit counter read, our CreditsAvailableCallback callback will be called
+                         * with the result */   
+                    DevGMboxReadCreditCounter(pProt->pDev, PROC_IO_ASYNC, NULL);
+                             
+                    LOCK_HCI_TX(pProt);
+                    break;              
+                }          
+            }
+        
+                /* caller guarantees some head room */
+            pPacket->pBuffer--;
+            pPacket->pBuffer[0] = hciUartType;
+            
+            pProt->CreditsAvailable -= creditsRequired;
+            pProt->CreditsConsumed  += creditsRequired;
+            A_ASSERT(pProt->CreditsConsumed <= pProt->CreditsMax);
+            
+            AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("HCI: new credit state: consumed:%d   available:%d max:%d\n",
+                             pProt->CreditsConsumed, pProt->CreditsAvailable,  pProt->CreditsMax));
+            
+            UNLOCK_HCI_TX(pProt);   
+            
+                /* write it out */   
+            if (Synchronous) {                            
+                pPacket->Completion = NULL;
+                pPacket->pContext = NULL;         
+            } else {                       
+                pPacket->Completion = HCISendPacketCompletion;
+                pPacket->pContext = pProt;    
+            }
+            
+            status = DevGMboxWrite(pProt->pDev,pPacket,transferLength);            
+            if (Synchronous) {            
+                synchSendComplete = TRUE;
+            } else {
+                pPacket = NULL;    
+            }
+            
+            LOCK_HCI_TX(pProt);
+              
+        }
+        
+    } while (FALSE);
+        
+    pProt->SendProcessCount--;
+    A_ASSERT(pProt->SendProcessCount >= 0);
+    UNLOCK_HCI_TX(pProt);
+    
+    if (Synchronous) {
+        A_ASSERT(pPacket != NULL);
+        if (A_SUCCESS(status) && (!synchSendComplete)) {
+            status = A_EBUSY;
+            A_ASSERT(FALSE);
+            LOCK_HCI_TX(pProt);
+            if (pPacket->ListLink.pNext != NULL) {
+                    /* remove from the queue */
+                HTC_PACKET_REMOVE(&pProt->SendQueue,pPacket);
+            }
+            UNLOCK_HCI_TX(pProt);
+        }
+    } else {   
+        if (A_FAILED(status) && (pPacket != NULL)) {
+            pPacket->Status = status;
+            DO_HCI_SEND_INDICATION(pProt,pPacket); 
+        }
+    }
+        
+    AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("-HCITrySend:  \n"));
+    return status;    
+}
+
+static void FlushSendQueue(GMBOX_PROTO_HCI_UART *pProt)
+{
+    HTC_PACKET          *pPacket;
+    HTC_PACKET_QUEUE    discardQueue;
+    
+    INIT_HTC_PACKET_QUEUE(&discardQueue);
+    
+    LOCK_HCI_TX(pProt);
+    
+    if (!HTC_QUEUE_EMPTY(&pProt->SendQueue)) {
+        HTC_PACKET_QUEUE_TRANSFER_TO_TAIL(&discardQueue,&pProt->SendQueue);    
+    }
+    
+    UNLOCK_HCI_TX(pProt);
+    
+        /* discard packets */
+    while (!HTC_QUEUE_EMPTY(&discardQueue)) {
+        pPacket = HTC_PACKET_DEQUEUE(&discardQueue);   
+        pPacket->Status = A_ECANCELED;
+        DO_HCI_SEND_INDICATION(pProt,pPacket);
+    }
+    
+}
+
+static void FlushRecvBuffers(GMBOX_PROTO_HCI_UART *pProt)
+{
+    HTC_PACKET_QUEUE discardQueue;
+    HTC_PACKET *pPacket;
+    
+    INIT_HTC_PACKET_QUEUE(&discardQueue);
+    
+    LOCK_HCI_RX(pProt);
+        /*transfer list items from ACL and event buffer queues to the discard queue */       
+    if (!HTC_QUEUE_EMPTY(&pProt->HCIACLRecvBuffers)) {
+        HTC_PACKET_QUEUE_TRANSFER_TO_TAIL(&discardQueue,&pProt->HCIACLRecvBuffers);    
+    }
+    if (!HTC_QUEUE_EMPTY(&pProt->HCIEventBuffers)) {
+        HTC_PACKET_QUEUE_TRANSFER_TO_TAIL(&discardQueue,&pProt->HCIEventBuffers);    
+    }
+    UNLOCK_HCI_RX(pProt);
+    
+        /* now empty the discard queue */
+    while (!HTC_QUEUE_EMPTY(&discardQueue)) {
+        pPacket = HTC_PACKET_DEQUEUE(&discardQueue);      
+        pPacket->Status = A_ECANCELED;
+        DO_HCI_RECV_INDICATION(pProt,pPacket);
+    }
+    
+}
+
+/*** protocol module install entry point ***/
+
+A_STATUS GMboxProtocolInstall(AR6K_DEVICE *pDev)
+{
+    A_STATUS                status = A_OK;
+    GMBOX_PROTO_HCI_UART    *pProtocol = NULL;
+        
+    do {
+        
+        pProtocol = A_MALLOC(sizeof(GMBOX_PROTO_HCI_UART));
+        
+        if (NULL == pProtocol) {
+            status = A_NO_MEMORY;
+            break;    
+        }
+        
+        A_MEMZERO(pProtocol, sizeof(*pProtocol));
+        pProtocol->pDev = pDev;
+        INIT_HTC_PACKET_QUEUE(&pProtocol->SendQueue);
+        INIT_HTC_PACKET_QUEUE(&pProtocol->HCIACLRecvBuffers);
+        INIT_HTC_PACKET_QUEUE(&pProtocol->HCIEventBuffers);
+        A_MUTEX_INIT(&pProtocol->HCIRxLock);
+        A_MUTEX_INIT(&pProtocol->HCITxLock);
+     
+    } while (FALSE);
+    
+    if (A_SUCCESS(status)) {
+        LOCK_AR6K(pDev);
+        DEV_GMBOX_SET_PROTOCOL(pDev,
+                               HCIUartMessagePending,
+                               CreditsAvailableCallback,
+                               FailureCallback,
+                               StateDumpCallback,
+                               pProtocol);
+        UNLOCK_AR6K(pDev);
+    } else {
+        if (pProtocol != NULL) {
+            HCIUartCleanup(pProtocol);    
+        }    
+    }
+    
+    return status;    
+}
+
+/*** protocol module uninstall entry point ***/
+void GMboxProtocolUninstall(AR6K_DEVICE *pDev)
+{
+    GMBOX_PROTO_HCI_UART *pProtocol = (GMBOX_PROTO_HCI_UART *)DEV_GMBOX_GET_PROTOCOL(pDev);
+    
+    if (pProtocol != NULL) {
+        
+            /* notify anyone attached */    
+        if (pProtocol->HCIAttached) {
+            A_ASSERT(pProtocol->HCIConfig.TransportRemoved != NULL);
+            pProtocol->HCIConfig.TransportRemoved(pProtocol->HCIConfig.pContext);
+            pProtocol->HCIAttached = FALSE;    
+        }
+        
+        HCIUartCleanup(pProtocol);
+        DEV_GMBOX_SET_PROTOCOL(pDev,NULL,NULL,NULL,NULL,NULL);       
+    }
+    
+}
+
+static A_STATUS NotifyTransportReady(GMBOX_PROTO_HCI_UART  *pProt)
+{
+    HCI_TRANSPORT_PROPERTIES props;
+    A_STATUS                 status = A_OK;
+    
+    do {
+        
+        A_MEMZERO(&props,sizeof(props));
+        
+            /* HCI UART only needs one extra byte at the head to indicate the packet TYPE */
+        props.HeadRoom = 1;
+        props.TailRoom = 0;
+        props.IOBlockPad = pProt->pDev->BlockSize;
+        if (pProt->HCIAttached) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ANY,("HCI: notifying attached client to transport... \n"));    
+            A_ASSERT(pProt->HCIConfig.TransportReady != NULL);
+            status = pProt->HCIConfig.TransportReady(pProt,
+                                                    &props,
+                                                    pProt->HCIConfig.pContext);
+        }
+        
+    } while (FALSE);
+    
+    return status;
+}
+
+/***********  HCI UART protocol implementation ************************************************/
+
+HCI_TRANSPORT_HANDLE HCI_TransportAttach(void *HTCHandle, HCI_TRANSPORT_CONFIG_INFO *pInfo)
+{
+    GMBOX_PROTO_HCI_UART  *pProtocol = NULL; 
+    AR6K_DEVICE           *pDev;
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("+HCI_TransportAttach \n"));
+    
+    pDev = HTCGetAR6KDevice(HTCHandle);
+    
+    LOCK_AR6K(pDev);
+    
+    do {
+        
+        pProtocol = (GMBOX_PROTO_HCI_UART *)DEV_GMBOX_GET_PROTOCOL(pDev);
+        
+        if (NULL == pProtocol) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("GMBOX protocol not installed! \n"));
+            break;
+        }
+        
+        if (pProtocol->HCIAttached) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("GMBOX protocol already attached! \n"));
+            break;    
+        }
+        
+        A_MEMCPY(&pProtocol->HCIConfig, pInfo, sizeof(HCI_TRANSPORT_CONFIG_INFO));
+        
+        A_ASSERT(pProtocol->HCIConfig.pHCIPktRecv != NULL);
+        A_ASSERT(pProtocol->HCIConfig.pHCISendComplete != NULL);
+        
+        pProtocol->HCIAttached = TRUE;
+        
+    } while (FALSE);
+    
+    UNLOCK_AR6K(pDev);
+    
+    if (pProtocol != NULL) {
+            /* TODO ... should we use a worker? */
+        NotifyTransportReady(pProtocol);
+    }
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("-HCI_TransportAttach (0x%lX) \n",(unsigned long)pProtocol));
+    return (HCI_TRANSPORT_HANDLE)pProtocol;
+}
+
+void HCI_TransportDetach(HCI_TRANSPORT_HANDLE HciTrans)
+{
+    GMBOX_PROTO_HCI_UART  *pProtocol = (GMBOX_PROTO_HCI_UART *)HciTrans; 
+    AR6K_DEVICE           *pDev = pProtocol->pDev;
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("+HCI_TransportDetach \n"));
+    
+    LOCK_AR6K(pDev);
+    if (!pProtocol->HCIAttached) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("GMBOX protocol not attached! \n"));
+        UNLOCK_AR6K(pDev);
+        return;
+    }
+    pProtocol->HCIAttached = FALSE;
+    UNLOCK_AR6K(pDev);
+    
+    HCI_TransportStop(HciTrans);
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("-HCI_TransportAttach \n"));
+}
+
+A_STATUS HCI_TransportAddReceivePkts(HCI_TRANSPORT_HANDLE HciTrans, HTC_PACKET_QUEUE *pQueue)
+{
+    GMBOX_PROTO_HCI_UART  *pProt = (GMBOX_PROTO_HCI_UART *)HciTrans; 
+    A_STATUS              status = A_OK;
+    A_BOOL                unblockRecv = FALSE;
+    HTC_PACKET            *pPacket;
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("+HCI_TransportAddReceivePkt \n"));
+    
+    LOCK_HCI_RX(pProt);
+   
+    do {
+         
+        if (pProt->HCIStopped) {
+            status = A_ECANCELED;
+            break;    
+        }
+        
+        pPacket = HTC_GET_PKT_AT_HEAD(pQueue);
+        
+        if (NULL == pPacket) {
+            status = A_EINVAL;
+            break;    
+        }
+        
+        AR_DEBUG_PRINTF(ATH_DEBUG_RECV,(" HCI recv packet added, type :%d, len:%d num:%d \n",
+                        HCI_GET_PACKET_TYPE(pPacket), pPacket->BufferLength, HTC_PACKET_QUEUE_DEPTH(pQueue)));
+                        
+        if (HCI_GET_PACKET_TYPE(pPacket) == HCI_EVENT_TYPE) {
+            HTC_PACKET_QUEUE_TRANSFER_TO_TAIL(&pProt->HCIEventBuffers, pQueue);
+        } else if (HCI_GET_PACKET_TYPE(pPacket) == HCI_ACL_TYPE) {
+            HTC_PACKET_QUEUE_TRANSFER_TO_TAIL(&pProt->HCIACLRecvBuffers, pQueue);    
+        } else {
+            status = A_EINVAL;
+            break;    
+        }
+        
+        if (pProt->RecvStateFlags & HCI_RECV_WAIT_BUFFERS) {
+            if (pProt->WaitBufferType == HCI_GET_PACKET_TYPE(pPacket)) {
+                AR_DEBUG_PRINTF(ATH_DEBUG_RECV,(" HCI recv was blocked on packet type :%d, unblocking.. \n",
+                        pProt->WaitBufferType));
+                pProt->RecvStateFlags &= ~HCI_RECV_WAIT_BUFFERS;
+                pProt->WaitBufferType = HCI_PACKET_INVALID;
+                unblockRecv = TRUE;
+            }
+        }
+        
+    } while (FALSE);
+    
+    UNLOCK_HCI_RX(pProt);
+    
+    if (A_FAILED(status)) {
+        while (!HTC_QUEUE_EMPTY(pQueue)) {
+            pPacket = HTC_PACKET_DEQUEUE(pQueue);      
+            pPacket->Status = A_ECANCELED;
+            DO_HCI_RECV_INDICATION(pProt,pPacket);
+        }   
+    }
+    
+    if (unblockRecv) {
+        DevGMboxIRQAction(pProt->pDev, GMBOX_RECV_IRQ_ENABLE, PROC_IO_ASYNC);
+    }
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("-HCI_TransportAddReceivePkt \n"));
+    
+    return A_OK;    
+}
+
+A_STATUS HCI_TransportSendPkt(HCI_TRANSPORT_HANDLE HciTrans, HTC_PACKET *pPacket, A_BOOL Synchronous)
+{
+    GMBOX_PROTO_HCI_UART  *pProt = (GMBOX_PROTO_HCI_UART *)HciTrans;  
+    
+    return HCITrySend(pProt,pPacket,Synchronous);
+}
+
+void HCI_TransportStop(HCI_TRANSPORT_HANDLE HciTrans)
+{
+    GMBOX_PROTO_HCI_UART  *pProt = (GMBOX_PROTO_HCI_UART *)HciTrans; 
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("+HCI_TransportStop \n"));
+     
+    LOCK_AR6K(pProt->pDev);
+    if (pProt->HCIStopped) {
+        UNLOCK_AR6K(pProt->pDev);
+        AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("-HCI_TransportStop \n"));
+        return;    
+    }
+    pProt->HCIStopped = TRUE;
+    UNLOCK_AR6K(pProt->pDev);
+     
+        /* disable interrupts */
+    DevGMboxIRQAction(pProt->pDev, GMBOX_DISABLE_ALL, PROC_IO_SYNC);
+    FlushSendQueue(pProt);
+    FlushRecvBuffers(pProt);
+    
+        /* signal bridge side to power down BT */
+    DevGMboxSetTargetInterrupt(pProt->pDev, MBOX_SIG_HCI_BRIDGE_BT_OFF, BTOFF_TIMEOUT_MS);
+           
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("-HCI_TransportStop \n"));
+}
+
+A_STATUS HCI_TransportStart(HCI_TRANSPORT_HANDLE HciTrans)
+{
+    A_STATUS              status;
+    GMBOX_PROTO_HCI_UART  *pProt = (GMBOX_PROTO_HCI_UART *)HciTrans;
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("+HCI_TransportStart \n"));
+    
+        /* set stopped in case we have a problem in starting */
+    pProt->HCIStopped = TRUE;
+    
+    do {
+        
+        status = InitTxCreditState(pProt);   
+        
+        if (A_FAILED(status)) {
+            break;    
+        }     
+        
+        status = DevGMboxIRQAction(pProt->pDev, GMBOX_ERRORS_IRQ_ENABLE, PROC_IO_SYNC);   
+        
+        if (A_FAILED(status)) {
+            break;   
+        } 
+            /* enable recv */   
+        status = DevGMboxIRQAction(pProt->pDev, GMBOX_RECV_IRQ_ENABLE, PROC_IO_SYNC);
+        
+        if (A_FAILED(status)) {
+            break;   
+        } 
+            /* signal bridge side to power up BT */
+        status = DevGMboxSetTargetInterrupt(pProt->pDev, MBOX_SIG_HCI_BRIDGE_BT_ON, BTON_TIMEOUT_MS);
+        
+        if (A_FAILED(status)) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("HCI_TransportStart : Failed to trigger BT ON \n"));
+            break;   
+        } 
+        
+            /* we made it */
+        pProt->HCIStopped = FALSE;
+        
+    } while (FALSE);
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("-HCI_TransportStart \n"));
+    
+    return status;
+}
+
+A_STATUS HCI_TransportEnableDisableAsyncRecv(HCI_TRANSPORT_HANDLE HciTrans, A_BOOL Enable)
+{
+    GMBOX_PROTO_HCI_UART  *pProt = (GMBOX_PROTO_HCI_UART *)HciTrans;
+    return DevGMboxIRQAction(pProt->pDev, 
+                             Enable ? GMBOX_RECV_IRQ_ENABLE : GMBOX_RECV_IRQ_DISABLE, 
+                             PROC_IO_SYNC);
+                             
+}
+
+A_STATUS HCI_TransportRecvHCIEventSync(HCI_TRANSPORT_HANDLE HciTrans,
+                                       HTC_PACKET           *pPacket,
+                                       int                  MaxPollMS)
+{
+    GMBOX_PROTO_HCI_UART  *pProt = (GMBOX_PROTO_HCI_UART *)HciTrans;
+    A_STATUS              status = A_OK;
+    A_UINT8               lookAhead[8];
+    int                   bytes;
+    int                   totalRecvLength;
+    
+    MaxPollMS = MaxPollMS / 16;
+    
+    if (MaxPollMS < 2) {
+        MaxPollMS = 2;    
+    }
+    
+    while (MaxPollMS) {
+        
+        bytes = sizeof(lookAhead);
+        status = DevGMboxRecvLookAheadPeek(pProt->pDev,lookAhead,&bytes);
+        if (A_FAILED(status)) {
+            break;    
+        }        
+                
+        if (bytes < 3) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("HCI recv poll got bytes: %d, retry : %d \n",
+                        bytes, MaxPollMS));
+            A_MDELAY(16);
+            MaxPollMS--;        
+            continue;
+        }
+        
+        totalRecvLength = 0;
+        switch (lookAhead[0]) {       
+            case HCI_UART_EVENT_PKT:
+                AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("HCI Event: %d param length: %d \n",
+                        lookAhead[1], lookAhead[2]));
+                totalRecvLength = lookAhead[2];
+                totalRecvLength += 3; /* add type + event code + length field */
+                break;
+            default:
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("**Invalid HCI packet type: %d \n",lookAhead[0]));
+                status = A_EPROTO;
+                break;
+        }
+        
+        if (A_FAILED(status)) {
+            break;    
+        }
+        
+        pPacket->Completion = NULL;
+        status = DevGMboxRead(pProt->pDev,pPacket,totalRecvLength); 
+        if (A_FAILED(status)) {
+            break;    
+        }
+        
+        pPacket->pBuffer++;
+        pPacket->ActualLength = totalRecvLength - 1;
+        pPacket->Status = A_OK;        
+        break; 
+    }
+    
+    if (MaxPollMS == 0) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("HCI recv poll timeout! \n"));
+        status = A_ERROR;    
+    }
+    
+    return status;
+}
+
+#define LSB_SCRATCH_IDX     4
+#define MSB_SCRATCH_IDX     5
+A_STATUS HCI_TransportSetBaudRate(HCI_TRANSPORT_HANDLE HciTrans, A_UINT32 Baud)
+{
+    GMBOX_PROTO_HCI_UART  *pProt = (GMBOX_PROTO_HCI_UART *)HciTrans;
+    HIF_DEVICE *pHIFDevice = (HIF_DEVICE *)(pProt->pDev->HIFDevice);
+    A_UINT32 scaledBaud, scratchAddr;
+    A_STATUS status = A_OK;
+
+    /* Divide the desired baud rate by 100
+     * Store the LSB in the local scratch register 4 and the MSB in the local
+     * scratch register 5 for the target to read
+     */
+    scratchAddr = MBOX_BASE_ADDRESS | (LOCAL_SCRATCH_ADDRESS + 4 * LSB_SCRATCH_IDX);
+    scaledBaud = (Baud / 100) & LOCAL_SCRATCH_VALUE_MASK;
+    status = ar6000_WriteRegDiag(pHIFDevice, &scratchAddr, &scaledBaud);                     
+    scratchAddr = MBOX_BASE_ADDRESS | (LOCAL_SCRATCH_ADDRESS + 4 * MSB_SCRATCH_IDX);
+    scaledBaud = ((Baud / 100) >> (LOCAL_SCRATCH_VALUE_MSB+1)) & LOCAL_SCRATCH_VALUE_MASK;
+    status |= ar6000_WriteRegDiag(pHIFDevice, &scratchAddr, &scaledBaud);                     
+    if (A_OK != status) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to set up baud rate in scratch register!"));            
+        return status;
+    }
+
+    /* Now interrupt the target to tell it about the baud rate */
+    status = DevGMboxSetTargetInterrupt(pProt->pDev, MBOX_SIG_HCI_BRIDGE_BAUD_SET, BAUD_TIMEOUT_MS);
+    if (A_OK != status) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to tell target to change baud rate!"));            
+    }
+    
+    return status;
+}
+
+A_STATUS HCI_TransportEnablePowerMgmt(HCI_TRANSPORT_HANDLE HciTrans, A_BOOL Enable)
+{
+    A_STATUS status;
+    GMBOX_PROTO_HCI_UART  *pProt = (GMBOX_PROTO_HCI_UART *)HciTrans;
+                             
+    if (Enable) {
+        status = DevGMboxSetTargetInterrupt(pProt->pDev, MBOX_SIG_HCI_BRIDGE_PWR_SAV_ON, BTPWRSAV_TIMEOUT_MS);
+    } else {
+        status = DevGMboxSetTargetInterrupt(pProt->pDev, MBOX_SIG_HCI_BRIDGE_PWR_SAV_OFF, BTPWRSAV_TIMEOUT_MS);
+    }
+
+    if (A_FAILED(status)) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Failed to enable/disable HCI power management!\n"));
+    } else {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("HCI power management enabled/disabled!\n"));
+    }
+
+    return status;
+}
+
+#endif  //ATH_AR6K_ENABLE_GMBOX
+
diff --git a/drivers/net/ath6kl/htc2/htc.c b/drivers/net/ath6kl/htc2/htc.c
new file mode 100644
index 00000000000..7df62a20d48
--- /dev/null
+++ b/drivers/net/ath6kl/htc2/htc.c
@@ -0,0 +1,579 @@
+//------------------------------------------------------------------------------
+// <copyright file="htc.c" company="Atheros">
+//    Copyright (c) 2007-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+#include "htc_internal.h"
+
+#ifdef ATH_DEBUG_MODULE
+static ATH_DEBUG_MASK_DESCRIPTION g_HTCDebugDescription[] = {
+    { ATH_DEBUG_SEND , "Send"},
+    { ATH_DEBUG_RECV , "Recv"},
+    { ATH_DEBUG_SYNC , "Sync"},
+    { ATH_DEBUG_DUMP , "Dump Data (RX or TX)"},
+    { ATH_DEBUG_IRQ  , "Interrupt Processing"}
+};
+
+ATH_DEBUG_INSTANTIATE_MODULE_VAR(htc,
+                                 "htc",
+                                 "Host Target Communications",
+                                 ATH_DEBUG_MASK_DEFAULTS,
+                                 ATH_DEBUG_DESCRIPTION_COUNT(g_HTCDebugDescription),
+                                 g_HTCDebugDescription);
+                                 
+#endif
+
+static void HTCReportFailure(void *Context);
+static void ResetEndpointStates(HTC_TARGET *target);
+
+void HTCFreeControlBuffer(HTC_TARGET *target, HTC_PACKET *pPacket, HTC_PACKET_QUEUE *pList)
+{
+    LOCK_HTC(target);
+    HTC_PACKET_ENQUEUE(pList,pPacket);
+    UNLOCK_HTC(target);
+}
+
+HTC_PACKET *HTCAllocControlBuffer(HTC_TARGET *target,  HTC_PACKET_QUEUE *pList)
+{
+    HTC_PACKET *pPacket;
+
+    LOCK_HTC(target);
+    pPacket = HTC_PACKET_DEQUEUE(pList);
+    UNLOCK_HTC(target);
+
+    return pPacket;
+}
+
+/* cleanup the HTC instance */
+static void HTCCleanup(HTC_TARGET *target)
+{
+    A_INT32 i;
+
+    DevCleanup(&target->Device);
+    
+    for (i = 0;i < NUM_CONTROL_BUFFERS;i++) {
+        if (target->HTCControlBuffers[i].Buffer) {
+            A_FREE(target->HTCControlBuffers[i].Buffer);
+        }
+    }
+    
+    if (A_IS_MUTEX_VALID(&target->HTCLock)) {
+        A_MUTEX_DELETE(&target->HTCLock);
+    }
+
+    if (A_IS_MUTEX_VALID(&target->HTCRxLock)) {
+        A_MUTEX_DELETE(&target->HTCRxLock);
+    }
+
+    if (A_IS_MUTEX_VALID(&target->HTCTxLock)) {
+        A_MUTEX_DELETE(&target->HTCTxLock);
+    }
+        /* free our instance */
+    A_FREE(target);
+}
+
+/* registered target arrival callback from the HIF layer */
+HTC_HANDLE HTCCreate(void *hif_handle, HTC_INIT_INFO *pInfo)
+{
+    HTC_TARGET              *target = NULL;
+    A_STATUS                 status = A_OK;
+    int                      i;
+    A_UINT32                 ctrl_bufsz;
+    A_UINT32                 blocksizes[HTC_MAILBOX_NUM_MAX];
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCCreate - Enter\n"));
+
+    A_REGISTER_MODULE_DEBUG_INFO(htc);
+    
+    do {
+
+            /* allocate target memory */
+        if ((target = (HTC_TARGET *)A_MALLOC(sizeof(HTC_TARGET))) == NULL) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to allocate memory\n"));
+            status = A_ERROR;
+            break;
+        }
+
+        A_MEMZERO(target, sizeof(HTC_TARGET));
+        A_MUTEX_INIT(&target->HTCLock);
+        A_MUTEX_INIT(&target->HTCRxLock);
+        A_MUTEX_INIT(&target->HTCTxLock);
+        INIT_HTC_PACKET_QUEUE(&target->ControlBufferTXFreeList);
+        INIT_HTC_PACKET_QUEUE(&target->ControlBufferRXFreeList);
+        
+            /* give device layer the hif device handle */
+        target->Device.HIFDevice = hif_handle;
+            /* give the device layer our context (for event processing)
+             * the device layer will register it's own context with HIF
+             * so we need to set this so we can fetch it in the target remove handler */
+        target->Device.HTCContext = target;
+            /* set device layer target failure callback */
+        target->Device.TargetFailureCallback = HTCReportFailure;
+            /* set device layer recv message pending callback */
+        target->Device.MessagePendingCallback = HTCRecvMessagePendingHandler;
+        target->EpWaitingForBuffers = ENDPOINT_MAX;
+
+        A_MEMCPY(&target->HTCInitInfo,pInfo,sizeof(HTC_INIT_INFO));
+        
+        ResetEndpointStates(target);
+          
+            /* setup device layer */
+        status = DevSetup(&target->Device);
+
+        if (A_FAILED(status)) {
+            break;
+        }
+
+
+        /* get the block sizes */
+        status = HIFConfigureDevice(hif_handle, HIF_DEVICE_GET_MBOX_BLOCK_SIZE,
+                                    blocksizes, sizeof(blocksizes));
+        if (A_FAILED(status)) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Failed to get block size info from HIF layer...\n"));
+            break;
+        }
+
+        /* Set the control buffer size based on the block size */
+        if (blocksizes[1] > HTC_MAX_CONTROL_MESSAGE_LENGTH) {
+            ctrl_bufsz = blocksizes[1] + HTC_HDR_LENGTH;
+        } else {
+            ctrl_bufsz = HTC_MAX_CONTROL_MESSAGE_LENGTH + HTC_HDR_LENGTH;
+        }
+        for (i = 0;i < NUM_CONTROL_BUFFERS;i++) {
+            target->HTCControlBuffers[i].Buffer = A_MALLOC(ctrl_bufsz);
+            if (target->HTCControlBuffers[i].Buffer == NULL) {
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to allocate memory\n"));
+                status = A_ERROR;
+                break;
+            }
+        }
+
+        if (A_FAILED(status)) {
+            break;
+        }
+
+            /* carve up buffers/packets for control messages */
+        for (i = 0; i < NUM_CONTROL_RX_BUFFERS; i++) {
+            HTC_PACKET *pControlPacket;
+            pControlPacket = &target->HTCControlBuffers[i].HtcPacket;
+            SET_HTC_PACKET_INFO_RX_REFILL(pControlPacket,
+                                          target,
+                                          target->HTCControlBuffers[i].Buffer,
+                                          ctrl_bufsz,
+                                          ENDPOINT_0);
+            HTC_FREE_CONTROL_RX(target,pControlPacket);
+        }
+
+        for (;i < NUM_CONTROL_BUFFERS;i++) {
+             HTC_PACKET *pControlPacket;
+             pControlPacket = &target->HTCControlBuffers[i].HtcPacket;
+             INIT_HTC_PACKET_INFO(pControlPacket,
+                                  target->HTCControlBuffers[i].Buffer,
+                                  ctrl_bufsz);
+             HTC_FREE_CONTROL_TX(target,pControlPacket);
+        }
+
+    } while (FALSE);
+
+    if (A_FAILED(status)) {
+        if (target != NULL) {
+            HTCCleanup(target);
+            target = NULL;
+        }
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCCreate - Exit\n"));
+
+    return target;
+}
+
+void  HTCDestroy(HTC_HANDLE HTCHandle)
+{
+    HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("+HTCDestroy ..  Destroying :0x%lX \n",(unsigned long)target));
+    HTCCleanup(target);
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("-HTCDestroy \n"));
+}
+
+/* get the low level HIF device for the caller , the caller may wish to do low level
+ * HIF requests */
+void *HTCGetHifDevice(HTC_HANDLE HTCHandle)
+{
+    HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
+    return target->Device.HIFDevice;
+}
+
+/* wait for the target to arrive (sends HTC Ready message)
+ * this operation is fully synchronous and the message is polled for */
+A_STATUS HTCWaitTarget(HTC_HANDLE HTCHandle)
+{
+    HTC_TARGET              *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
+    A_STATUS                 status;
+    HTC_PACKET              *pPacket = NULL;
+    HTC_READY_EX_MSG        *pRdyMsg;
+
+    HTC_SERVICE_CONNECT_REQ  connect;
+    HTC_SERVICE_CONNECT_RESP resp;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCWaitTarget - Enter (target:0x%lX) \n", (unsigned long)target));
+
+    do {
+
+#ifdef MBOXHW_UNIT_TEST
+
+        status = DoMboxHWTest(&target->Device);
+
+        if (status != A_OK) {
+            break;
+        }
+
+#endif
+
+            /* we should be getting 1 control message that the target is ready */
+        status = HTCWaitforControlMessage(target, &pPacket);
+
+        if (A_FAILED(status)) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, (" Target Not Available!!\n"));
+            break;
+        }
+
+            /* we controlled the buffer creation so it has to be properly aligned */
+        pRdyMsg = (HTC_READY_EX_MSG *)pPacket->pBuffer;
+
+        if ((pRdyMsg->Version2_0_Info.MessageID != HTC_MSG_READY_ID) ||
+            (pPacket->ActualLength < sizeof(HTC_READY_MSG))) {
+                /* this message is not valid */
+            AR_DEBUG_ASSERT(FALSE);
+            status = A_EPROTO;
+            break;
+        }
+
+        
+        if (pRdyMsg->Version2_0_Info.CreditCount == 0 || pRdyMsg->Version2_0_Info.CreditSize == 0) {
+              /* this message is not valid */
+            AR_DEBUG_ASSERT(FALSE);
+            status = A_EPROTO;
+            break;
+        }
+
+        target->TargetCredits = pRdyMsg->Version2_0_Info.CreditCount;
+        target->TargetCreditSize = pRdyMsg->Version2_0_Info.CreditSize;
+        
+        AR_DEBUG_PRINTF(ATH_DEBUG_WARN, (" Target Ready: credits: %d credit size: %d\n",
+                target->TargetCredits, target->TargetCreditSize));
+        
+            /* check if this is an extended ready message */        
+        if (pPacket->ActualLength >= sizeof(HTC_READY_EX_MSG)) {
+                /* this is an extended message */    
+            target->HTCTargetVersion = pRdyMsg->HTCVersion;   
+            target->MaxMsgPerBundle = pRdyMsg->MaxMsgsPerHTCBundle;     
+        } else {
+                /* legacy */
+            target->HTCTargetVersion = HTC_VERSION_2P0;
+            target->MaxMsgPerBundle = 0;    
+        }
+        
+#ifdef HTC_FORCE_LEGACY_2P0   
+            /* for testing and comparison...*/     
+        target->HTCTargetVersion = HTC_VERSION_2P0;
+        target->MaxMsgPerBundle = 0;
+#endif
+           
+        AR_DEBUG_PRINTF(ATH_DEBUG_TRC, 
+                    ("Using HTC Protocol Version : %s (%d)\n ", 
+                    (target->HTCTargetVersion == HTC_VERSION_2P0) ? "2.0" : ">= 2.1",
+                    target->HTCTargetVersion));
+                    
+        if (target->MaxMsgPerBundle > 0) {
+                /* limit what HTC can handle */
+            target->MaxMsgPerBundle = min(HTC_HOST_MAX_MSG_PER_BUNDLE, target->MaxMsgPerBundle);          
+                /* target supports message bundling, setup device layer */
+            if (A_FAILED(DevSetupMsgBundling(&target->Device,target->MaxMsgPerBundle))) {
+                    /* device layer can't handle bundling */
+                target->MaxMsgPerBundle = 0;        
+            } else {
+                    /* limit bundle what the device layer can handle */
+                target->MaxMsgPerBundle = min(DEV_GET_MAX_MSG_PER_BUNDLE(&target->Device),
+                                              target->MaxMsgPerBundle);     
+            }
+        }
+        
+        if (target->MaxMsgPerBundle > 0) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_TRC, 
+                    (" HTC bundling allowed. Max Msg Per HTC Bundle: %d\n", target->MaxMsgPerBundle));    
+           
+            if (DEV_GET_MAX_BUNDLE_SEND_LENGTH(&target->Device) != 0) {           
+                target->SendBundlingEnabled = TRUE;
+            }            
+            if (DEV_GET_MAX_BUNDLE_RECV_LENGTH(&target->Device) != 0) {    
+                target->RecvBundlingEnabled = TRUE;    
+            }
+                            
+            if (!DEV_IS_LEN_BLOCK_ALIGNED(&target->Device,target->TargetCreditSize)) {
+                AR_DEBUG_PRINTF(ATH_DEBUG_WARN, ("*** Credit size: %d is not block aligned! Disabling send bundling \n",
+                        target->TargetCreditSize));    
+                    /* disallow send bundling since the credit size is not aligned to a block size
+                     * the I/O block padding will spill into the next credit buffer which is fatal */
+                target->SendBundlingEnabled = FALSE;
+            }
+        }
+           
+            /* setup our pseudo HTC control endpoint connection */
+        A_MEMZERO(&connect,sizeof(connect));
+        A_MEMZERO(&resp,sizeof(resp));
+        connect.EpCallbacks.pContext = target;
+        connect.EpCallbacks.EpTxComplete = HTCControlTxComplete;
+        connect.EpCallbacks.EpRecv = HTCControlRecv;
+        connect.EpCallbacks.EpRecvRefill = NULL;  /* not needed */
+        connect.EpCallbacks.EpSendFull = NULL;    /* not nedded */
+        connect.MaxSendQueueDepth = NUM_CONTROL_BUFFERS;
+        connect.ServiceID = HTC_CTRL_RSVD_SVC;
+
+            /* connect fake service */
+        status = HTCConnectService((HTC_HANDLE)target,
+                                   &connect,
+                                   &resp);
+
+        if (!A_FAILED(status)) {
+            break;
+        }
+
+    } while (FALSE);
+
+    if (pPacket != NULL) {
+        HTC_FREE_CONTROL_RX(target,pPacket);
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCWaitTarget - Exit\n"));
+
+    return status;
+}
+
+
+
+/* Start HTC, enable interrupts and let the target know host has finished setup */
+A_STATUS HTCStart(HTC_HANDLE HTCHandle)
+{
+    HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
+    HTC_PACKET *pPacket;
+    A_STATUS   status;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCStart Enter\n"));
+
+        /* make sure interrupts are disabled at the chip level,
+         * this function can be called again from a reboot of the target without shutting down HTC */
+    DevDisableInterrupts(&target->Device);
+        /* make sure state is cleared again */
+    target->OpStateFlags = 0;
+    target->RecvStateFlags = 0;
+      
+        /* now that we are starting, push control receive buffers into the
+         * HTC control endpoint */
+
+    while (1) {
+        pPacket = HTC_ALLOC_CONTROL_RX(target);
+        if (NULL == pPacket) {
+            break;
+        }
+        HTCAddReceivePkt((HTC_HANDLE)target,pPacket);
+    }
+
+    do {
+
+        AR_DEBUG_ASSERT(target->InitCredits != NULL);
+        AR_DEBUG_ASSERT(target->EpCreditDistributionListHead != NULL);
+        AR_DEBUG_ASSERT(target->EpCreditDistributionListHead->pNext != NULL);
+
+            /* call init credits callback to do the distribution ,
+             * NOTE: the first entry in the distribution list is ENDPOINT_0, so
+             * we pass the start of the list after this one. */
+        target->InitCredits(target->pCredDistContext,
+                            target->EpCreditDistributionListHead->pNext,
+                            target->TargetCredits);
+
+#ifdef ATH_DEBUG_MODULE
+
+        if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_TRC)) {
+            DumpCreditDistStates(target);
+        }
+#endif
+
+            /* the caller is done connecting to services, so we can indicate to the
+            * target that the setup phase is complete */
+        status = HTCSendSetupComplete(target);
+
+        if (A_FAILED(status)) {
+            break;
+        }
+
+            /* unmask interrupts */
+        status = DevUnmaskInterrupts(&target->Device);
+
+        if (A_FAILED(status)) {
+            HTCStop(target);
+        }
+
+    } while (FALSE);
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCStart Exit\n"));
+    return status;
+}
+
+static void ResetEndpointStates(HTC_TARGET *target)
+{
+    HTC_ENDPOINT        *pEndpoint;
+    int                  i;
+
+    for (i = ENDPOINT_0; i < ENDPOINT_MAX; i++) {
+        pEndpoint = &target->EndPoint[i];
+        
+        A_MEMZERO(&pEndpoint->CreditDist, sizeof(pEndpoint->CreditDist));
+        pEndpoint->ServiceID = 0;
+        pEndpoint->MaxMsgLength = 0;
+        pEndpoint->MaxTxQueueDepth = 0;
+#ifdef HTC_EP_STAT_PROFILING
+        A_MEMZERO(&pEndpoint->EndPointStats,sizeof(pEndpoint->EndPointStats));
+#endif
+        INIT_HTC_PACKET_QUEUE(&pEndpoint->RxBuffers);
+        INIT_HTC_PACKET_QUEUE(&pEndpoint->TxQueue);
+        INIT_HTC_PACKET_QUEUE(&pEndpoint->RecvIndicationQueue);
+        pEndpoint->target = target;
+    }
+        /* reset distribution list */
+    target->EpCreditDistributionListHead = NULL;
+}
+
+/* stop HTC communications, i.e. stop interrupt reception, and flush all queued buffers */
+void HTCStop(HTC_HANDLE HTCHandle)
+{
+    HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("+HTCStop \n"));
+
+    LOCK_HTC(target);
+        /* mark that we are shutting down .. */
+    target->OpStateFlags |= HTC_OP_STATE_STOPPING;
+    UNLOCK_HTC(target);
+    
+        /* Masking interrupts is a synchronous operation, when this function returns
+         * all pending HIF I/O has completed, we can safely flush the queues */
+    DevMaskInterrupts(&target->Device);
+
+#ifdef THREAD_X
+	//
+	//	Is this delay required
+	//
+    A_MDELAY(200); // wait for IRQ process done
+#endif
+        /* flush all send packets */
+    HTCFlushSendPkts(target);
+        /* flush all recv buffers */
+    HTCFlushRecvBuffers(target);
+
+    ResetEndpointStates(target);
+   
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("-HTCStop \n"));
+}
+
+#ifdef ATH_DEBUG_MODULE
+void HTCDumpCreditStates(HTC_HANDLE HTCHandle)
+{
+    HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
+
+    LOCK_HTC_TX(target);
+
+    DumpCreditDistStates(target);
+
+    UNLOCK_HTC_TX(target);
+    
+    DumpAR6KDevState(&target->Device);
+}
+#endif
+/* report a target failure from the device, this is a callback from the device layer
+ * which uses a mechanism to report errors from the target (i.e. special interrupts) */
+static void HTCReportFailure(void *Context)
+{
+    HTC_TARGET *target = (HTC_TARGET *)Context;
+
+    target->TargetFailure = TRUE;
+
+    if (target->HTCInitInfo.TargetFailure != NULL) {
+            /* let upper layer know, it needs to call HTCStop() */
+        target->HTCInitInfo.TargetFailure(target->HTCInitInfo.pContext, A_ERROR);
+    }
+}
+
+A_BOOL HTCGetEndpointStatistics(HTC_HANDLE               HTCHandle,
+                                HTC_ENDPOINT_ID          Endpoint,
+                                HTC_ENDPOINT_STAT_ACTION Action,
+                                HTC_ENDPOINT_STATS       *pStats)
+{
+
+#ifdef HTC_EP_STAT_PROFILING
+    HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
+    A_BOOL     clearStats = FALSE;
+    A_BOOL     sample = FALSE;
+
+    switch (Action) {
+        case HTC_EP_STAT_SAMPLE :
+            sample = TRUE;
+            break;
+        case HTC_EP_STAT_SAMPLE_AND_CLEAR :
+            sample = TRUE;
+            clearStats = TRUE;
+            break;
+        case HTC_EP_STAT_CLEAR :
+            clearStats = TRUE;
+            break;
+        default:
+            break;
+    }
+
+    A_ASSERT(Endpoint < ENDPOINT_MAX);
+
+        /* lock out TX and RX while we sample and/or clear */
+    LOCK_HTC_TX(target);
+    LOCK_HTC_RX(target);
+
+    if (sample) {
+        A_ASSERT(pStats != NULL);
+            /* return the stats to the caller */
+        A_MEMCPY(pStats, &target->EndPoint[Endpoint].EndPointStats, sizeof(HTC_ENDPOINT_STATS));
+    }
+
+    if (clearStats) {
+            /* reset stats */
+        A_MEMZERO(&target->EndPoint[Endpoint].EndPointStats, sizeof(HTC_ENDPOINT_STATS));
+    }
+
+    UNLOCK_HTC_RX(target);
+    UNLOCK_HTC_TX(target);
+
+    return TRUE;
+#else
+    return FALSE;
+#endif
+}
+
+AR6K_DEVICE  *HTCGetAR6KDevice(void *HTCHandle)
+{
+    HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
+    return &target->Device;
+}
+
diff --git a/drivers/net/ath6kl/htc2/htc_debug.h b/drivers/net/ath6kl/htc2/htc_debug.h
new file mode 100644
index 00000000000..8455703e221
--- /dev/null
+++ b/drivers/net/ath6kl/htc2/htc_debug.h
@@ -0,0 +1,38 @@
+//------------------------------------------------------------------------------
+// <copyright file="htc_debug.h" company="Atheros">
+//    Copyright (c) 2007-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef HTC_DEBUG_H_
+#define HTC_DEBUG_H_
+
+#define ATH_MODULE_NAME htc
+#include "a_debug.h"
+
+/* ------- Debug related stuff ------- */
+
+#define  ATH_DEBUG_SEND ATH_DEBUG_MAKE_MODULE_MASK(0)
+#define  ATH_DEBUG_RECV ATH_DEBUG_MAKE_MODULE_MASK(1)
+#define  ATH_DEBUG_SYNC ATH_DEBUG_MAKE_MODULE_MASK(2)
+#define  ATH_DEBUG_DUMP ATH_DEBUG_MAKE_MODULE_MASK(3)
+#define  ATH_DEBUG_IRQ  ATH_DEBUG_MAKE_MODULE_MASK(4)
+
+
+#endif /*HTC_DEBUG_H_*/
diff --git a/drivers/net/ath6kl/htc2/htc_internal.h b/drivers/net/ath6kl/htc2/htc_internal.h
new file mode 100644
index 00000000000..bd6754beb22
--- /dev/null
+++ b/drivers/net/ath6kl/htc2/htc_internal.h
@@ -0,0 +1,220 @@
+//------------------------------------------------------------------------------
+// <copyright file="htc_internal.h" company="Atheros">
+//    Copyright (c) 2007-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _HTC_INTERNAL_H_
+#define _HTC_INTERNAL_H_
+
+/* for debugging, uncomment this to capture the last frame header, on frame header
+ * processing errors, the last frame header is dump for comparison */
+//#define HTC_CAPTURE_LAST_FRAME
+
+//#define HTC_EP_STAT_PROFILING
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* Header files */
+
+#include "a_config.h"
+#include "athdefs.h"
+#include "a_types.h"
+#include "a_osapi.h"
+#include "htc_debug.h"
+#include "htc.h"
+#include "htc_api.h"
+#include "bmi_msg.h"
+#include "hif.h"
+#include "AR6000/ar6k.h"
+
+/* HTC operational parameters */
+#define HTC_TARGET_RESPONSE_TIMEOUT        2000 /* in ms */
+#define HTC_TARGET_DEBUG_INTR_MASK         0x01
+#define HTC_TARGET_CREDIT_INTR_MASK        0xF0
+
+#define HTC_HOST_MAX_MSG_PER_BUNDLE        8
+#define HTC_MIN_HTC_MSGS_TO_BUNDLE         2
+
+/* packet flags */
+
+#define HTC_RX_PKT_IGNORE_LOOKAHEAD      (1 << 0)
+#define HTC_RX_PKT_REFRESH_HDR           (1 << 1)
+#define HTC_RX_PKT_PART_OF_BUNDLE        (1 << 2)
+#define HTC_RX_PKT_NO_RECYCLE            (1 << 3)
+
+/* scatter request flags */
+
+#define HTC_SCATTER_REQ_FLAGS_PARTIAL_BUNDLE  (1 << 0)
+
+typedef struct _HTC_ENDPOINT {
+    HTC_ENDPOINT_ID             Id;
+    HTC_SERVICE_ID              ServiceID;      /* service ID this endpoint is bound to
+                                                   non-zero value means this endpoint is in use */
+    HTC_PACKET_QUEUE            TxQueue;        /* HTC frame buffer TX queue */
+    HTC_PACKET_QUEUE            RxBuffers;      /* HTC frame buffer RX list */
+    HTC_ENDPOINT_CREDIT_DIST    CreditDist;     /* credit distribution structure (exposed to driver layer) */
+    HTC_EP_CALLBACKS            EpCallBacks;    /* callbacks associated with this endpoint */
+    int                         MaxTxQueueDepth;   /* max depth of the TX queue before we need to
+                                                      call driver's full handler */
+    int                         MaxMsgLength;        /* max length of endpoint message */
+    int                         TxProcessCount;  /* reference count to continue tx processing */
+    HTC_PACKET_QUEUE            RecvIndicationQueue;    /* recv packets ready to be indicated */
+    int                         RxProcessCount;         /* reference count to allow single processing context */
+    struct  _HTC_TARGET         *target;                /* back pointer to target */
+    A_UINT8                     SeqNo;                  /* TX seq no (helpful) for debugging */
+    A_UINT32                    LocalConnectionFlags;   /* local connection flags */
+#ifdef HTC_EP_STAT_PROFILING
+    HTC_ENDPOINT_STATS          EndPointStats;          /* endpoint statistics */
+#endif
+} HTC_ENDPOINT;
+
+#ifdef HTC_EP_STAT_PROFILING
+#define INC_HTC_EP_STAT(p,stat,count) (p)->EndPointStats.stat += (count);
+#else
+#define INC_HTC_EP_STAT(p,stat,count)
+#endif
+
+#define HTC_SERVICE_TX_PACKET_TAG  HTC_TX_PACKET_TAG_INTERNAL
+
+#define NUM_CONTROL_BUFFERS     8
+#define NUM_CONTROL_TX_BUFFERS  2
+#define NUM_CONTROL_RX_BUFFERS  (NUM_CONTROL_BUFFERS - NUM_CONTROL_TX_BUFFERS)
+
+typedef struct HTC_CONTROL_BUFFER {
+    HTC_PACKET    HtcPacket;
+    A_UINT8       *Buffer;
+} HTC_CONTROL_BUFFER;
+
+#define HTC_RECV_WAIT_BUFFERS        (1 << 0)
+#define HTC_OP_STATE_STOPPING        (1 << 0)
+
+/* our HTC target state */
+typedef struct _HTC_TARGET {
+    HTC_ENDPOINT                EndPoint[ENDPOINT_MAX];
+    HTC_CONTROL_BUFFER          HTCControlBuffers[NUM_CONTROL_BUFFERS];
+    HTC_ENDPOINT_CREDIT_DIST   *EpCreditDistributionListHead;
+    HTC_PACKET_QUEUE            ControlBufferTXFreeList;
+    HTC_PACKET_QUEUE            ControlBufferRXFreeList;
+    HTC_CREDIT_DIST_CALLBACK    DistributeCredits;
+    HTC_CREDIT_INIT_CALLBACK    InitCredits;
+    void                       *pCredDistContext;
+    int                         TargetCredits;
+    unsigned int                TargetCreditSize;
+    A_MUTEX_T                   HTCLock;
+    A_MUTEX_T                   HTCRxLock;
+    A_MUTEX_T                   HTCTxLock;
+    AR6K_DEVICE                 Device;         /* AR6K - specific state */
+    A_UINT32                    OpStateFlags;
+    A_UINT32                    RecvStateFlags;
+    HTC_ENDPOINT_ID             EpWaitingForBuffers;
+    A_BOOL                      TargetFailure;
+#ifdef HTC_CAPTURE_LAST_FRAME
+    HTC_FRAME_HDR               LastFrameHdr;  /* useful for debugging */
+    A_UINT8                     LastTrailer[256];
+    A_UINT8                     LastTrailerLength;
+#endif
+    HTC_INIT_INFO               HTCInitInfo;
+    A_UINT8                     HTCTargetVersion;
+    int                         MaxMsgPerBundle;       /* max messages per bundle for HTC */
+    A_BOOL                      SendBundlingEnabled;   /* run time enable for send bundling (dynamic) */
+    int                         RecvBundlingEnabled;   /* run time enable for recv bundling (dynamic) */
+} HTC_TARGET;
+
+#define HTC_STOPPING(t) ((t)->OpStateFlags & HTC_OP_STATE_STOPPING)
+#define LOCK_HTC(t)      A_MUTEX_LOCK(&(t)->HTCLock);
+#define UNLOCK_HTC(t)    A_MUTEX_UNLOCK(&(t)->HTCLock);
+#define LOCK_HTC_RX(t)   A_MUTEX_LOCK(&(t)->HTCRxLock);
+#define UNLOCK_HTC_RX(t) A_MUTEX_UNLOCK(&(t)->HTCRxLock);
+#define LOCK_HTC_TX(t)   A_MUTEX_LOCK(&(t)->HTCTxLock);
+#define UNLOCK_HTC_TX(t) A_MUTEX_UNLOCK(&(t)->HTCTxLock);
+
+#define GET_HTC_TARGET_FROM_HANDLE(hnd) ((HTC_TARGET *)(hnd))
+#define HTC_RECYCLE_RX_PKT(target,p,e)                           \
+{                                                                \
+    if ((p)->PktInfo.AsRx.HTCRxFlags & HTC_RX_PKT_NO_RECYCLE) {  \
+         HTC_PACKET_RESET_RX(pPacket);                           \
+         pPacket->Status = A_ECANCELED;                          \
+         (e)->EpCallBacks.EpRecv((e)->EpCallBacks.pContext,      \
+                                 (p));                           \
+    } else {                                                     \
+        HTC_PACKET_RESET_RX(pPacket);                            \
+        HTCAddReceivePkt((HTC_HANDLE)(target),(p));              \
+    }                                                            \
+}
+
+/* internal HTC functions */
+void        HTCControlTxComplete(void *Context, HTC_PACKET *pPacket);
+void        HTCControlRecv(void *Context, HTC_PACKET *pPacket);
+A_STATUS    HTCWaitforControlMessage(HTC_TARGET *target, HTC_PACKET **ppControlPacket);
+HTC_PACKET *HTCAllocControlBuffer(HTC_TARGET *target, HTC_PACKET_QUEUE *pList);
+void        HTCFreeControlBuffer(HTC_TARGET *target, HTC_PACKET *pPacket, HTC_PACKET_QUEUE *pList);
+A_STATUS    HTCIssueSend(HTC_TARGET *target, HTC_PACKET *pPacket);
+void        HTCRecvCompleteHandler(void *Context, HTC_PACKET *pPacket);
+A_STATUS    HTCRecvMessagePendingHandler(void *Context, A_UINT32 MsgLookAheads[], int NumLookAheads, A_BOOL *pAsyncProc, int *pNumPktsFetched);
+void        HTCProcessCreditRpt(HTC_TARGET *target, HTC_CREDIT_REPORT *pRpt, int NumEntries, HTC_ENDPOINT_ID FromEndpoint);
+A_STATUS    HTCSendSetupComplete(HTC_TARGET *target);
+void        HTCFlushRecvBuffers(HTC_TARGET *target);
+void        HTCFlushSendPkts(HTC_TARGET *target);
+
+#ifdef ATH_DEBUG_MODULE
+void        DumpCreditDist(HTC_ENDPOINT_CREDIT_DIST *pEPDist);
+void        DumpCreditDistStates(HTC_TARGET *target);
+void 		DebugDumpBytes(A_UCHAR *buffer, A_UINT16 length, char *pDescription);
+#endif
+
+static INLINE HTC_PACKET *HTC_ALLOC_CONTROL_TX(HTC_TARGET *target) {
+    HTC_PACKET *pPacket = HTCAllocControlBuffer(target,&target->ControlBufferTXFreeList);
+    if (pPacket != NULL) {
+            /* set payload pointer area with some headroom */
+        pPacket->pBuffer = pPacket->pBufferStart + HTC_HDR_LENGTH;
+    }
+    return pPacket;
+}
+
+#define HTC_FREE_CONTROL_TX(t,p) HTCFreeControlBuffer((t),(p),&(t)->ControlBufferTXFreeList)
+#define HTC_ALLOC_CONTROL_RX(t)  HTCAllocControlBuffer((t),&(t)->ControlBufferRXFreeList)
+#define HTC_FREE_CONTROL_RX(t,p) \
+{                                                                \
+    HTC_PACKET_RESET_RX(p);                                      \
+    HTCFreeControlBuffer((t),(p),&(t)->ControlBufferRXFreeList); \
+}
+
+#define HTC_PREPARE_SEND_PKT(pP,sendflags,ctrl0,ctrl1)       \
+{                                                   \
+    A_UINT8 *pHdrBuf;                               \
+    (pP)->pBuffer -= HTC_HDR_LENGTH;                \
+    pHdrBuf = (pP)->pBuffer;                        \
+    A_SET_UINT16_FIELD(pHdrBuf,HTC_FRAME_HDR,PayloadLen,(A_UINT16)(pP)->ActualLength);  \
+    A_SET_UINT8_FIELD(pHdrBuf,HTC_FRAME_HDR,Flags,(sendflags));                         \
+    A_SET_UINT8_FIELD(pHdrBuf,HTC_FRAME_HDR,EndpointID, (A_UINT8)(pP)->Endpoint); \
+    A_SET_UINT8_FIELD(pHdrBuf,HTC_FRAME_HDR,ControlBytes[0], (A_UINT8)(ctrl0));   \
+    A_SET_UINT8_FIELD(pHdrBuf,HTC_FRAME_HDR,ControlBytes[1], (A_UINT8)(ctrl1));   \
+}
+
+#define HTC_UNPREPARE_SEND_PKT(pP)     \
+    (pP)->pBuffer += HTC_HDR_LENGTH;   \
+    
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HTC_INTERNAL_H_ */
diff --git a/drivers/net/ath6kl/htc2/htc_recv.c b/drivers/net/ath6kl/htc2/htc_recv.c
new file mode 100644
index 00000000000..3503657fe7d
--- /dev/null
+++ b/drivers/net/ath6kl/htc2/htc_recv.c
@@ -0,0 +1,1578 @@
+//------------------------------------------------------------------------------
+// <copyright file="htc_recv.c" company="Atheros">
+//    Copyright (c) 2007-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+#include "htc_internal.h"
+
+#define HTCIssueRecv(t, p) \
+    DevRecvPacket(&(t)->Device,  \
+                  (p),          \
+                  (p)->ActualLength)
+
+#define DO_RCV_COMPLETION(e,q)  DoRecvCompletion(e,q)
+
+#define DUMP_RECV_PKT_INFO(pP) \
+    AR_DEBUG_PRINTF(ATH_DEBUG_RECV, (" HTC RECV packet 0x%lX (%d bytes) (hdr:0x%X) on ep : %d \n", \
+                        (unsigned long)(pP),                   \
+                        (pP)->ActualLength,                    \
+                        (pP)->PktInfo.AsRx.ExpectedHdr,        \
+                        (pP)->Endpoint))                         
+                        
+#ifdef HTC_EP_STAT_PROFILING
+#define HTC_RX_STAT_PROFILE(t,ep,numLookAheads)        \
+{                                                      \
+    INC_HTC_EP_STAT((ep), RxReceived, 1);              \
+    if ((numLookAheads) == 1) {                        \
+        INC_HTC_EP_STAT((ep), RxLookAheads, 1);        \
+    } else if ((numLookAheads) > 1) {                  \
+        INC_HTC_EP_STAT((ep), RxBundleLookAheads, 1);  \
+    }                                                  \
+}
+#else
+#define HTC_RX_STAT_PROFILE(t,ep,lookAhead)
+#endif
+
+static void DoRecvCompletion(HTC_ENDPOINT     *pEndpoint,
+                             HTC_PACKET_QUEUE *pQueueToIndicate)
+{           
+    
+    do {
+        
+        if (HTC_QUEUE_EMPTY(pQueueToIndicate)) {
+                /* nothing to indicate */
+            break;    
+        }
+ 
+        if (pEndpoint->EpCallBacks.EpRecvPktMultiple != NULL) {    
+            AR_DEBUG_PRINTF(ATH_DEBUG_RECV, (" HTC calling ep %d, recv multiple callback (%d pkts) \n",
+                     pEndpoint->Id, HTC_PACKET_QUEUE_DEPTH(pQueueToIndicate)));
+                /* a recv multiple handler is being used, pass the queue to the handler */                             
+            pEndpoint->EpCallBacks.EpRecvPktMultiple(pEndpoint->EpCallBacks.pContext,
+                                                     pQueueToIndicate);
+            INIT_HTC_PACKET_QUEUE(pQueueToIndicate);        
+        } else {
+            HTC_PACKET *pPacket;  
+            /* using legacy EpRecv */         
+            do {
+                pPacket = HTC_PACKET_DEQUEUE(pQueueToIndicate);
+                AR_DEBUG_PRINTF(ATH_DEBUG_RECV, (" HTC calling ep %d recv callback on packet 0x%lX \n", \
+                        pEndpoint->Id, (unsigned long)(pPacket)));
+                pEndpoint->EpCallBacks.EpRecv(pEndpoint->EpCallBacks.pContext, pPacket);                                              
+            } while (!HTC_QUEUE_EMPTY(pQueueToIndicate));                                              
+        }
+        
+    } while (FALSE);
+
+}
+
+static INLINE A_STATUS HTCProcessTrailer(HTC_TARGET *target,
+                                         A_UINT8    *pBuffer,
+                                         int         Length,
+                                         A_UINT32   *pNextLookAheads,
+                                         int        *pNumLookAheads,
+                                         HTC_ENDPOINT_ID FromEndpoint)
+{
+    HTC_RECORD_HDR          *pRecord;
+    A_UINT8                 *pRecordBuf;
+    HTC_LOOKAHEAD_REPORT    *pLookAhead;
+    A_UINT8                 *pOrigBuffer;
+    int                     origLength;
+    A_STATUS                status;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("+HTCProcessTrailer (length:%d) \n", Length));
+
+    if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_RECV)) {
+        AR_DEBUG_PRINTBUF(pBuffer,Length,"Recv Trailer");
+    }
+
+    pOrigBuffer = pBuffer;
+    origLength = Length;
+    status = A_OK;
+    
+    while (Length > 0) {
+
+        if (Length < sizeof(HTC_RECORD_HDR)) {
+            status = A_EPROTO;
+            break;
+        }
+            /* these are byte aligned structs */
+        pRecord = (HTC_RECORD_HDR *)pBuffer;
+        Length -= sizeof(HTC_RECORD_HDR);
+        pBuffer += sizeof(HTC_RECORD_HDR);
+
+        if (pRecord->Length > Length) {
+                /* no room left in buffer for record */
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                (" invalid record length: %d (id:%d) buffer has: %d bytes left \n",
+                        pRecord->Length, pRecord->RecordID, Length));
+            status = A_EPROTO;
+            break;
+        }
+            /* start of record follows the header */
+        pRecordBuf = pBuffer;
+
+        switch (pRecord->RecordID) {
+            case HTC_RECORD_CREDITS:
+                AR_DEBUG_ASSERT(pRecord->Length >= sizeof(HTC_CREDIT_REPORT));
+                HTCProcessCreditRpt(target,
+                                    (HTC_CREDIT_REPORT *)pRecordBuf,
+                                    pRecord->Length / (sizeof(HTC_CREDIT_REPORT)),
+                                    FromEndpoint);
+                break;
+            case HTC_RECORD_LOOKAHEAD:
+                AR_DEBUG_ASSERT(pRecord->Length >= sizeof(HTC_LOOKAHEAD_REPORT));
+                pLookAhead = (HTC_LOOKAHEAD_REPORT *)pRecordBuf;
+                if ((pLookAhead->PreValid == ((~pLookAhead->PostValid) & 0xFF)) &&
+                    (pNextLookAheads != NULL)) {
+
+                    AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
+                                (" LookAhead Report Found (pre valid:0x%X, post valid:0x%X) \n",
+                                pLookAhead->PreValid,
+                                pLookAhead->PostValid));
+
+                        /* look ahead bytes are valid, copy them over */
+                    ((A_UINT8 *)(&pNextLookAheads[0]))[0] = pLookAhead->LookAhead[0];
+                    ((A_UINT8 *)(&pNextLookAheads[0]))[1] = pLookAhead->LookAhead[1];
+                    ((A_UINT8 *)(&pNextLookAheads[0]))[2] = pLookAhead->LookAhead[2];
+                    ((A_UINT8 *)(&pNextLookAheads[0]))[3] = pLookAhead->LookAhead[3];
+
+#ifdef ATH_DEBUG_MODULE
+                    if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_RECV)) {
+                        DebugDumpBytes((A_UINT8 *)pNextLookAheads,4,"Next Look Ahead");
+                    }
+#endif
+                        /* just one normal lookahead */
+                    *pNumLookAheads = 1;
+                }
+                break;
+            case HTC_RECORD_LOOKAHEAD_BUNDLE:
+                AR_DEBUG_ASSERT(pRecord->Length >= sizeof(HTC_BUNDLED_LOOKAHEAD_REPORT));
+                if (pRecord->Length >= sizeof(HTC_BUNDLED_LOOKAHEAD_REPORT) &&
+                    (pNextLookAheads != NULL)) {                   
+                    HTC_BUNDLED_LOOKAHEAD_REPORT    *pBundledLookAheadRpt;
+                    int                             i;
+                    
+                    pBundledLookAheadRpt = (HTC_BUNDLED_LOOKAHEAD_REPORT *)pRecordBuf;
+                    
+#ifdef ATH_DEBUG_MODULE
+                    if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_RECV)) {
+                        DebugDumpBytes(pRecordBuf,pRecord->Length,"Bundle LookAhead");
+                    }
+#endif
+                    
+                    if ((pRecord->Length / (sizeof(HTC_BUNDLED_LOOKAHEAD_REPORT))) >
+                            HTC_HOST_MAX_MSG_PER_BUNDLE) {
+                            /* this should never happen, the target restricts the number
+                             * of messages per bundle configured by the host */        
+                        A_ASSERT(FALSE);
+                        status = A_EPROTO;
+                        break;        
+                    }
+                                         
+                    for (i = 0; i < (int)(pRecord->Length / (sizeof(HTC_BUNDLED_LOOKAHEAD_REPORT))); i++) {
+                        ((A_UINT8 *)(&pNextLookAheads[i]))[0] = pBundledLookAheadRpt->LookAhead[0];
+                        ((A_UINT8 *)(&pNextLookAheads[i]))[1] = pBundledLookAheadRpt->LookAhead[1];
+                        ((A_UINT8 *)(&pNextLookAheads[i]))[2] = pBundledLookAheadRpt->LookAhead[2];
+                        ((A_UINT8 *)(&pNextLookAheads[i]))[3] = pBundledLookAheadRpt->LookAhead[3];
+                        pBundledLookAheadRpt++;
+                    }
+                    
+                    *pNumLookAheads = i;
+                }               
+                break;
+            default:
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR, (" unhandled record: id:%d length:%d \n",
+                        pRecord->RecordID, pRecord->Length));
+                break;
+        }
+
+        if (A_FAILED(status)) {
+            break;
+        }
+
+            /* advance buffer past this record for next time around */
+        pBuffer += pRecord->Length;
+        Length -= pRecord->Length;
+    }
+
+#ifdef ATH_DEBUG_MODULE
+    if (A_FAILED(status)) {
+        DebugDumpBytes(pOrigBuffer,origLength,"BAD Recv Trailer");
+    }
+#endif
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("-HTCProcessTrailer \n"));
+    return status;
+
+}
+
+/* process a received message (i.e. strip off header, process any trailer data)
+ * note : locks must be released when this function is called */
+static A_STATUS HTCProcessRecvHeader(HTC_TARGET *target, 
+                                     HTC_PACKET *pPacket, 
+                                     A_UINT32   *pNextLookAheads, 
+                                     int        *pNumLookAheads)
+{
+    A_UINT8   temp;
+    A_UINT8   *pBuf;
+    A_STATUS  status = A_OK;
+    A_UINT16  payloadLen;
+    A_UINT32  lookAhead;
+
+    pBuf = pPacket->pBuffer;
+    
+    if (pNumLookAheads != NULL) {
+        *pNumLookAheads = 0;
+    }
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("+HTCProcessRecvHeader \n"));
+
+    if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_RECV)) {
+        AR_DEBUG_PRINTBUF(pBuf,pPacket->ActualLength,"HTC Recv PKT");
+    }
+
+    do {
+        /* note, we cannot assume the alignment of pBuffer, so we use the safe macros to
+         * retrieve 16 bit fields */
+        payloadLen = A_GET_UINT16_FIELD(pBuf, HTC_FRAME_HDR, PayloadLen);
+        
+        ((A_UINT8 *)&lookAhead)[0] = pBuf[0];
+        ((A_UINT8 *)&lookAhead)[1] = pBuf[1];
+        ((A_UINT8 *)&lookAhead)[2] = pBuf[2];
+        ((A_UINT8 *)&lookAhead)[3] = pBuf[3];
+
+        if (pPacket->PktInfo.AsRx.HTCRxFlags & HTC_RX_PKT_REFRESH_HDR) {
+                /* refresh expected hdr, since this was unknown at the time we grabbed the packets
+                 * as part of a bundle */
+            pPacket->PktInfo.AsRx.ExpectedHdr = lookAhead;
+                /* refresh actual length since we now have the real header */
+            pPacket->ActualLength = payloadLen + HTC_HDR_LENGTH;
+            
+                /* validate the actual header that was refreshed  */ 
+            if (pPacket->ActualLength > pPacket->BufferLength) {
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                    ("Refreshed HDR payload length (%d) in bundled RECV is invalid (hdr: 0x%X) \n", 
+                    payloadLen, lookAhead));
+                    /* limit this to max buffer just to print out some of the buffer */    
+                pPacket->ActualLength = min(pPacket->ActualLength, pPacket->BufferLength);
+                status = A_EPROTO;
+                break;    
+            }
+            
+            if (pPacket->Endpoint != A_GET_UINT8_FIELD(pBuf, HTC_FRAME_HDR, EndpointID)) {
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                    ("Refreshed HDR endpoint (%d) does not match expected endpoint (%d) \n", 
+                    A_GET_UINT8_FIELD(pBuf, HTC_FRAME_HDR, EndpointID), pPacket->Endpoint));
+                status = A_EPROTO;
+                break;      
+            }   
+        }
+                
+        if (lookAhead != pPacket->PktInfo.AsRx.ExpectedHdr) {
+            /* somehow the lookahead that gave us the full read length did not
+             * reflect the actual header in the pending message */
+             AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                    ("HTCProcessRecvHeader, lookahead mismatch! (pPkt:0x%lX flags:0x%X) \n", 
+                        (unsigned long)pPacket, pPacket->PktInfo.AsRx.HTCRxFlags));
+#ifdef ATH_DEBUG_MODULE
+             DebugDumpBytes((A_UINT8 *)&pPacket->PktInfo.AsRx.ExpectedHdr,4,"Expected Message LookAhead");
+             DebugDumpBytes(pBuf,sizeof(HTC_FRAME_HDR),"Current Frame Header");
+#ifdef HTC_CAPTURE_LAST_FRAME
+            DebugDumpBytes((A_UINT8 *)&target->LastFrameHdr,sizeof(HTC_FRAME_HDR),"Last Frame Header");
+            if (target->LastTrailerLength != 0) {
+                DebugDumpBytes(target->LastTrailer,
+                               target->LastTrailerLength,
+                               "Last trailer");
+            }
+#endif
+#endif
+            status = A_EPROTO;
+            break;
+        }
+
+            /* get flags */
+        temp = A_GET_UINT8_FIELD(pBuf, HTC_FRAME_HDR, Flags);
+
+        if (temp & HTC_FLAGS_RECV_TRAILER) {
+            /* this packet has a trailer */
+
+                /* extract the trailer length in control byte 0 */
+            temp = A_GET_UINT8_FIELD(pBuf, HTC_FRAME_HDR, ControlBytes[0]);
+
+            if ((temp < sizeof(HTC_RECORD_HDR)) || (temp > payloadLen)) {
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                    ("HTCProcessRecvHeader, invalid header (payloadlength should be :%d, CB[0] is:%d) \n",
+                        payloadLen, temp));
+                status = A_EPROTO;
+                break;
+            }
+
+            if (pPacket->PktInfo.AsRx.HTCRxFlags & HTC_RX_PKT_IGNORE_LOOKAHEAD) {
+                    /* this packet was fetched as part of an HTC bundle, the embedded lookahead is
+                     * not valid since the next packet may have already been fetched as part of the
+                     * bundle */
+                pNextLookAheads = NULL;   
+                pNumLookAheads = NULL;     
+            }
+            
+                /* process trailer data that follows HDR + application payload */
+            status = HTCProcessTrailer(target,
+                                       (pBuf + HTC_HDR_LENGTH + payloadLen - temp),
+                                       temp,
+                                       pNextLookAheads,
+                                       pNumLookAheads,
+                                       pPacket->Endpoint);
+
+            if (A_FAILED(status)) {
+                break;
+            }
+
+#ifdef HTC_CAPTURE_LAST_FRAME
+            A_MEMCPY(target->LastTrailer, (pBuf + HTC_HDR_LENGTH + payloadLen - temp), temp);
+            target->LastTrailerLength = temp;
+#endif
+                /* trim length by trailer bytes */
+            pPacket->ActualLength -= temp;
+        }
+#ifdef HTC_CAPTURE_LAST_FRAME
+         else {
+            target->LastTrailerLength = 0;
+        }
+#endif
+
+            /* if we get to this point, the packet is good */
+            /* remove header and adjust length */
+        pPacket->pBuffer += HTC_HDR_LENGTH;
+        pPacket->ActualLength -= HTC_HDR_LENGTH;
+
+    } while (FALSE);
+
+    if (A_FAILED(status)) {
+            /* dump the whole packet */
+#ifdef ATH_DEBUG_MODULE
+        DebugDumpBytes(pBuf,pPacket->ActualLength < 256 ? pPacket->ActualLength : 256 ,"BAD HTC Recv PKT");
+#endif
+    } else {
+#ifdef HTC_CAPTURE_LAST_FRAME
+        A_MEMCPY(&target->LastFrameHdr,pBuf,sizeof(HTC_FRAME_HDR));
+#endif
+        if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_RECV)) {
+            if (pPacket->ActualLength > 0) {
+                AR_DEBUG_PRINTBUF(pPacket->pBuffer,pPacket->ActualLength,"HTC - Application Msg");
+            }
+        }
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("-HTCProcessRecvHeader \n"));
+    return status;
+}
+
+static INLINE void HTCAsyncRecvCheckMorePackets(HTC_TARGET  *target, 
+                                                A_UINT32    NextLookAheads[], 
+                                                int         NumLookAheads,
+                                                A_BOOL      CheckMoreMsgs)
+{
+        /* was there a lookahead for the next packet? */
+    if (NumLookAheads > 0) {
+        A_STATUS nextStatus;
+        int      fetched = 0;
+        AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
+                        ("HTCAsyncRecvCheckMorePackets - num lookaheads were non-zero : %d \n",
+                         NumLookAheads));
+            /* force status re-check */                    
+        REF_IRQ_STATUS_RECHECK(&target->Device);
+            /* we have more packets, get the next packet fetch started */
+        nextStatus = HTCRecvMessagePendingHandler(target, NextLookAheads, NumLookAheads, NULL, &fetched);
+        if (A_EPROTO == nextStatus) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                        ("Next look ahead from recv header was INVALID\n"));
+#ifdef ATH_DEBUG_MODULE
+            DebugDumpBytes((A_UINT8 *)NextLookAheads,
+                            NumLookAheads * (sizeof(A_UINT32)),
+                            "BAD lookaheads from lookahead report");
+#endif
+        }
+        if (A_SUCCESS(nextStatus) && !fetched) {
+                /* we could not fetch any more packets due to resources */
+            DevAsyncIrqProcessComplete(&target->Device);        
+        }
+    } else {
+        if (CheckMoreMsgs) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
+                ("HTCAsyncRecvCheckMorePackets - rechecking for more messages...\n"));
+            /* if we did not get anything on the look-ahead,
+             * call device layer to asynchronously re-check for messages. If we can keep the async
+             * processing going we get better performance.  If there is a pending message we will keep processing
+             * messages asynchronously which should pipeline things nicely */
+            DevCheckPendingRecvMsgsAsync(&target->Device);
+        } else {
+            AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("HTCAsyncRecvCheckMorePackets - no check \n"));    
+        }
+    }
+    
+     
+}      
+
+    /* unload the recv completion queue */
+static INLINE void DrainRecvIndicationQueue(HTC_TARGET *target, HTC_ENDPOINT *pEndpoint)
+{
+    HTC_PACKET_QUEUE     recvCompletions;
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("+DrainRecvIndicationQueue \n"));
+                
+    INIT_HTC_PACKET_QUEUE(&recvCompletions);
+    
+    LOCK_HTC_RX(target);
+    
+            /* increment rx processing count on entry */    
+    pEndpoint->RxProcessCount++;
+    if (pEndpoint->RxProcessCount > 1) {
+         pEndpoint->RxProcessCount--;
+            /* another thread or task is draining the RX completion queue on this endpoint
+             * that thread will reset the rx processing count when the queue is drained */
+         UNLOCK_HTC_RX(target);
+         return;
+    }
+    
+    /******* at this point only 1 thread may enter ******/
+     
+    while (TRUE) { 
+                
+            /* transfer items from main recv queue to the local one so we can release the lock */ 
+        HTC_PACKET_QUEUE_TRANSFER_TO_TAIL(&recvCompletions, &pEndpoint->RecvIndicationQueue);
+            
+        if (HTC_QUEUE_EMPTY(&recvCompletions)) {
+                /* all drained */
+            break;    
+        }
+        
+            /* release lock while we do the recv completions 
+             * other threads can now queue more recv completions */
+        UNLOCK_HTC_RX(target);
+        
+        AR_DEBUG_PRINTF(ATH_DEBUG_RECV, 
+                ("DrainRecvIndicationQueue : completing %d RECV packets \n",
+                                        HTC_PACKET_QUEUE_DEPTH(&recvCompletions)));
+            /* do completion */
+        DO_RCV_COMPLETION(pEndpoint,&recvCompletions);     
+              
+            /* re-acquire lock to grab some more completions */
+        LOCK_HTC_RX(target);    
+    }
+    
+        /* reset count */
+    pEndpoint->RxProcessCount = 0;       
+    UNLOCK_HTC_RX(target);
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("-DrainRecvIndicationQueue \n"));
+  
+}
+
+    /* optimization for recv packets, we can indicate a "hint" that there are more
+     * single-packets to fetch on this endpoint */
+#define SET_MORE_RX_PACKET_INDICATION_FLAG(L,N,E,P) \
+    if ((N) > 0) { SetRxPacketIndicationFlags((L)[0],(E),(P)); }
+
+    /* for bundled frames, we can force the flag to indicate there are more packets */
+#define FORCE_MORE_RX_PACKET_INDICATION_FLAG(P) \
+    (P)->PktInfo.AsRx.IndicationFlags |= HTC_RX_FLAGS_INDICATE_MORE_PKTS; 
+   
+   /* note: this function can be called with the RX lock held */     
+static INLINE void SetRxPacketIndicationFlags(A_UINT32      LookAhead, 
+                                              HTC_ENDPOINT  *pEndpoint, 
+                                              HTC_PACKET    *pPacket)
+{
+    HTC_FRAME_HDR *pHdr = (HTC_FRAME_HDR *)&LookAhead;
+        /* check to see if the "next" packet is from the same endpoint of the
+           completing packet */
+    if (pHdr->EndpointID == pPacket->Endpoint) {
+            /* check that there is a buffer available to actually fetch it */
+        if (!HTC_QUEUE_EMPTY(&pEndpoint->RxBuffers)) {                        
+                /* provide a hint that there are more RX packets to fetch */
+            FORCE_MORE_RX_PACKET_INDICATION_FLAG(pPacket);        
+        }             
+    }                  
+}
+
+     
+/* asynchronous completion handler for recv packet fetching, when the device layer
+ * completes a read request, it will call this completion handler */
+void HTCRecvCompleteHandler(void *Context, HTC_PACKET *pPacket)
+{
+    HTC_TARGET      *target = (HTC_TARGET *)Context;
+    HTC_ENDPOINT    *pEndpoint;
+    A_UINT32        nextLookAheads[HTC_HOST_MAX_MSG_PER_BUNDLE];
+    int             numLookAheads = 0;
+    A_STATUS        status;
+    A_BOOL          checkMorePkts = TRUE;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("+HTCRecvCompleteHandler (pkt:0x%lX, status:%d, ep:%d) \n",
+                (unsigned long)pPacket, pPacket->Status, pPacket->Endpoint));
+
+    A_ASSERT(!IS_DEV_IRQ_PROC_SYNC_MODE(&target->Device));
+    AR_DEBUG_ASSERT(pPacket->Endpoint < ENDPOINT_MAX);
+    pEndpoint = &target->EndPoint[pPacket->Endpoint];
+    pPacket->Completion = NULL;
+
+        /* get completion status */
+    status = pPacket->Status;
+
+    do {
+        
+        if (A_FAILED(status)) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("HTCRecvCompleteHandler: request failed (status:%d, ep:%d) \n",
+                pPacket->Status, pPacket->Endpoint));
+            break;
+        }
+            /* process the header for any trailer data */
+        status = HTCProcessRecvHeader(target,pPacket,nextLookAheads,&numLookAheads);
+
+        if (A_FAILED(status)) {
+            break;
+        }
+        
+        if (pPacket->PktInfo.AsRx.HTCRxFlags & HTC_RX_PKT_IGNORE_LOOKAHEAD) {
+                /* this packet was part of a bundle that had to be broken up. 
+                 * It was fetched one message at a time.  There may be other asynchronous reads queued behind this one.
+                 * Do no issue another check for more packets since the last one in the series of requests
+                 * will handle it */
+            checkMorePkts = FALSE;    
+        }
+          
+        DUMP_RECV_PKT_INFO(pPacket);    
+        LOCK_HTC_RX(target);
+        SET_MORE_RX_PACKET_INDICATION_FLAG(nextLookAheads,numLookAheads,pEndpoint,pPacket);
+            /* we have a good packet, queue it to the completion queue */
+        HTC_PACKET_ENQUEUE(&pEndpoint->RecvIndicationQueue,pPacket);
+        HTC_RX_STAT_PROFILE(target,pEndpoint,numLookAheads);
+        UNLOCK_HTC_RX(target);     
+       
+            /* check for more recv packets before indicating */
+        HTCAsyncRecvCheckMorePackets(target,nextLookAheads,numLookAheads,checkMorePkts);
+
+    } while (FALSE);
+
+    if (A_FAILED(status)) {
+         AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                         ("HTCRecvCompleteHandler , message fetch failed (status = %d) \n",
+                         status));
+            /* recycle this packet */
+        HTC_RECYCLE_RX_PKT(target, pPacket, pEndpoint);
+    } else {
+            /* a good packet was queued, drain the queue */
+        DrainRecvIndicationQueue(target,pEndpoint);     
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("-HTCRecvCompleteHandler\n"));
+}
+
+/* synchronously wait for a control message from the target,
+ * This function is used at initialization time ONLY.  At init messages
+ * on ENDPOINT 0 are expected. */
+A_STATUS HTCWaitforControlMessage(HTC_TARGET *target, HTC_PACKET **ppControlPacket)
+{
+    A_STATUS        status;
+    A_UINT32        lookAhead;
+    HTC_PACKET      *pPacket = NULL;
+    HTC_FRAME_HDR   *pHdr;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("+HTCWaitforControlMessage \n"));
+
+    do  {
+
+        *ppControlPacket = NULL;
+
+            /* call the polling function to see if we have a message */
+        status = DevPollMboxMsgRecv(&target->Device,
+                                    &lookAhead,
+                                    HTC_TARGET_RESPONSE_TIMEOUT);
+
+        if (A_FAILED(status)) {
+            break;
+        }
+
+        AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
+                ("HTCWaitforControlMessage : lookAhead : 0x%X \n", lookAhead));
+
+            /* check the lookahead */
+        pHdr = (HTC_FRAME_HDR *)&lookAhead;
+
+        if (pHdr->EndpointID != ENDPOINT_0) {
+                /* unexpected endpoint number, should be zero */
+            AR_DEBUG_ASSERT(FALSE);
+            status = A_EPROTO;
+            break;
+        }
+
+        if (A_FAILED(status)) {
+                /* bad message */
+            AR_DEBUG_ASSERT(FALSE);
+            status = A_EPROTO;
+            break;
+        }
+
+        pPacket = HTC_ALLOC_CONTROL_RX(target);
+
+        if (pPacket == NULL) {
+            AR_DEBUG_ASSERT(FALSE);
+            status = A_NO_MEMORY;
+            break;
+        }
+        
+        pPacket->PktInfo.AsRx.HTCRxFlags = 0;
+        pPacket->PktInfo.AsRx.ExpectedHdr = lookAhead;
+        pPacket->ActualLength = pHdr->PayloadLen + HTC_HDR_LENGTH;
+
+        if (pPacket->ActualLength > pPacket->BufferLength) {
+            AR_DEBUG_ASSERT(FALSE);
+            status = A_EPROTO;
+            break;
+        }
+
+            /* we want synchronous operation */
+        pPacket->Completion = NULL;
+
+            /* get the message from the device, this will block */
+        status = HTCIssueRecv(target, pPacket);
+
+        if (A_FAILED(status)) {
+            break;
+        }
+
+            /* process receive header */
+        status = HTCProcessRecvHeader(target,pPacket,NULL,NULL);
+
+        pPacket->Status = status;
+
+        if (A_FAILED(status)) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                    ("HTCWaitforControlMessage, HTCProcessRecvHeader failed (status = %d) \n",
+                     status));
+            break;
+        }
+
+            /* give the caller this control message packet, they are responsible to free */
+        *ppControlPacket = pPacket;
+
+    } while (FALSE);
+
+    if (A_FAILED(status)) {
+        if (pPacket != NULL) {
+                /* cleanup buffer on error */
+            HTC_FREE_CONTROL_RX(target,pPacket);
+        }
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("-HTCWaitforControlMessage \n"));
+
+    return status;
+}
+
+static A_STATUS AllocAndPrepareRxPackets(HTC_TARGET       *target, 
+                                         A_UINT32         LookAheads[], 
+                                         int              Messages,                                        
+                                         HTC_ENDPOINT     *pEndpoint, 
+                                         HTC_PACKET_QUEUE *pQueue)
+{
+    A_STATUS         status = A_OK;
+    HTC_PACKET      *pPacket;
+    HTC_FRAME_HDR   *pHdr;
+    int              i,j;
+    int              numMessages;
+    int              fullLength;
+    A_BOOL           noRecycle;
+            
+        /* lock RX while we assemble the packet buffers */
+    LOCK_HTC_RX(target);
+                        
+    for (i = 0; i < Messages; i++) {   
+         
+        pHdr = (HTC_FRAME_HDR *)&LookAheads[i];
+
+        if (pHdr->EndpointID >= ENDPOINT_MAX) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Invalid Endpoint in look-ahead: %d \n",pHdr->EndpointID));
+                /* invalid endpoint */
+            status = A_EPROTO;
+            break;
+        }
+
+        if (pHdr->EndpointID != pEndpoint->Id) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Invalid Endpoint in look-ahead: %d should be : %d (index:%d)\n",
+                pHdr->EndpointID, pEndpoint->Id, i));
+                /* invalid endpoint */
+            status = A_EPROTO;
+            break;    
+        }    
+       
+        if (pHdr->PayloadLen > HTC_MAX_PAYLOAD_LENGTH) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Payload length %d exceeds max HTC : %d !\n",
+                    pHdr->PayloadLen, (A_UINT32)HTC_MAX_PAYLOAD_LENGTH));
+            status = A_EPROTO;
+            break;
+        }
+
+        if (0 == pEndpoint->ServiceID) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Endpoint %d is not connected !\n",pHdr->EndpointID));
+                /* endpoint isn't even connected */
+            status = A_EPROTO;
+            break;
+        }
+
+        if ((pHdr->Flags & HTC_FLAGS_RECV_BUNDLE_CNT_MASK) == 0) {
+                /* HTC header only indicates 1 message to fetch */
+            numMessages = 1;
+        } else {
+                /* HTC header indicates that every packet to follow has the same padded length so that it can
+                 * be optimally fetched as a full bundle */
+            numMessages = (pHdr->Flags & HTC_FLAGS_RECV_BUNDLE_CNT_MASK) >> HTC_FLAGS_RECV_BUNDLE_CNT_SHIFT;
+                /* the count doesn't include the starter frame, just a count of frames to follow */
+            numMessages++;
+            A_ASSERT(numMessages <= target->MaxMsgPerBundle);          
+            INC_HTC_EP_STAT(pEndpoint, RxBundleIndFromHdr, 1);
+            AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
+                ("HTC header indicates :%d messages can be fetched as a bundle \n",numMessages));           
+        }
+     
+        fullLength = DEV_CALC_RECV_PADDED_LEN(&target->Device,pHdr->PayloadLen + sizeof(HTC_FRAME_HDR));
+            
+            /* get packet buffers for each message, if there was a bundle detected in the header,
+             * use pHdr as a template to fetch all packets in the bundle */        
+        for (j = 0; j < numMessages; j++) {  
+            
+                /* reset flag, any packets allocated using the RecvAlloc() API cannot be recycled on cleanup,
+                 * they must be explicitly returned */
+            noRecycle = FALSE;
+                                                                                   
+            if (pEndpoint->EpCallBacks.EpRecvAlloc != NULL) {
+                UNLOCK_HTC_RX(target);
+                noRecycle = TRUE;
+                    /* user is using a per-packet allocation callback */
+                pPacket = pEndpoint->EpCallBacks.EpRecvAlloc(pEndpoint->EpCallBacks.pContext,
+                                                             pEndpoint->Id,
+                                                             fullLength);
+                LOCK_HTC_RX(target);
+    
+            } else if ((pEndpoint->EpCallBacks.EpRecvAllocThresh != NULL) &&
+                       (fullLength > pEndpoint->EpCallBacks.RecvAllocThreshold)) { 
+                INC_HTC_EP_STAT(pEndpoint,RxAllocThreshHit,1);
+                INC_HTC_EP_STAT(pEndpoint,RxAllocThreshBytes,pHdr->PayloadLen);                
+                    /* threshold was hit, call the special recv allocation callback */        
+                UNLOCK_HTC_RX(target);
+                noRecycle = TRUE;
+                    /* user wants to allocate packets above a certain threshold */
+                pPacket = pEndpoint->EpCallBacks.EpRecvAllocThresh(pEndpoint->EpCallBacks.pContext,
+                                                                   pEndpoint->Id,
+                                                                   fullLength);
+                LOCK_HTC_RX(target);        
+                        
+            } else {
+                    /* user is using a refill handler that can refill multiple HTC buffers */
+                    
+                    /* get a packet from the endpoint recv queue */
+                pPacket = HTC_PACKET_DEQUEUE(&pEndpoint->RxBuffers);
+    
+                if (NULL == pPacket) {
+                        /* check for refill handler */
+                    if (pEndpoint->EpCallBacks.EpRecvRefill != NULL) {
+                        UNLOCK_HTC_RX(target);
+                            /* call the re-fill handler */
+                        pEndpoint->EpCallBacks.EpRecvRefill(pEndpoint->EpCallBacks.pContext,
+                                                            pEndpoint->Id);
+                        LOCK_HTC_RX(target);
+                            /* check if we have more buffers */
+                        pPacket = HTC_PACKET_DEQUEUE(&pEndpoint->RxBuffers);
+                            /* fall through */
+                    }
+                }
+            }
+    
+            if (NULL == pPacket) {
+                    /* this is not an error, we simply need to mark that we are waiting for buffers.*/
+                target->RecvStateFlags |= HTC_RECV_WAIT_BUFFERS;
+                target->EpWaitingForBuffers = pEndpoint->Id;
+                status = A_NO_RESOURCE;
+                break;
+            }
+                             
+            AR_DEBUG_ASSERT(pPacket->Endpoint == pEndpoint->Id);
+                /* clear flags */
+            pPacket->PktInfo.AsRx.HTCRxFlags = 0;
+            pPacket->PktInfo.AsRx.IndicationFlags = 0;
+            pPacket->Status = A_OK;
+            
+            if (noRecycle) {
+                    /* flag that these packets cannot be recycled, they have to be returned to the 
+                     * user */
+                pPacket->PktInfo.AsRx.HTCRxFlags |= HTC_RX_PKT_NO_RECYCLE; 
+            }
+                /* add packet to queue (also incase we need to cleanup down below)  */
+            HTC_PACKET_ENQUEUE(pQueue,pPacket);
+            
+            if (HTC_STOPPING(target)) {
+                status = A_ECANCELED;
+                break;
+            }
+    
+                /* make sure this message can fit in the endpoint buffer */
+            if ((A_UINT32)fullLength > pPacket->BufferLength) {
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                        ("Payload Length Error : header reports payload of: %d (%d) endpoint buffer size: %d \n",
+                        pHdr->PayloadLen, fullLength, pPacket->BufferLength));
+                status = A_EPROTO;
+                break;
+            }
+            
+            if (j > 0) {
+                    /* for messages fetched in a bundle the expected lookahead is unknown since we
+                     * are only using the lookahead of the first packet as a template of what to
+                     * expect for lengths */
+                    /* flag that once we get the real HTC header we need to refesh the information */     
+                pPacket->PktInfo.AsRx.HTCRxFlags |= HTC_RX_PKT_REFRESH_HDR;
+                    /* set it to something invalid */
+                pPacket->PktInfo.AsRx.ExpectedHdr = 0xFFFFFFFF;    
+            } else {
+            
+                pPacket->PktInfo.AsRx.ExpectedHdr = LookAheads[i]; /* set expected look ahead */
+            }
+                /* set the amount of data to fetch */
+            pPacket->ActualLength = pHdr->PayloadLen + HTC_HDR_LENGTH;
+        }
+        
+        if (A_FAILED(status)) {
+            if (A_NO_RESOURCE == status) {
+                    /* this is actually okay */
+                status = A_OK;    
+            }
+            break;    
+        }
+                
+    }
+    
+    UNLOCK_HTC_RX(target);
+    
+    if (A_FAILED(status)) {
+        while (!HTC_QUEUE_EMPTY(pQueue)) {
+            pPacket = HTC_PACKET_DEQUEUE(pQueue);
+                /* recycle all allocated packets */
+            HTC_RECYCLE_RX_PKT(target,pPacket,&target->EndPoint[pPacket->Endpoint]);
+        }        
+    }
+        
+    return status; 
+}
+
+static void HTCAsyncRecvScatterCompletion(HIF_SCATTER_REQ *pScatterReq)
+{
+    int                 i;    
+    HTC_PACKET          *pPacket;
+    HTC_ENDPOINT        *pEndpoint;
+    A_UINT32            lookAheads[HTC_HOST_MAX_MSG_PER_BUNDLE];
+    int                 numLookAheads = 0;
+    HTC_TARGET          *target = (HTC_TARGET *)pScatterReq->Context;
+    A_STATUS            status;
+    A_BOOL              partialBundle = FALSE;
+    HTC_PACKET_QUEUE    localRecvQueue;
+    A_BOOL              procError = FALSE;
+           
+    AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("+HTCAsyncRecvScatterCompletion  TotLen: %d  Entries: %d\n",
+        pScatterReq->TotalLength, pScatterReq->ValidScatterEntries));
+    
+    A_ASSERT(!IS_DEV_IRQ_PROC_SYNC_MODE(&target->Device));
+           
+    if (A_FAILED(pScatterReq->CompletionStatus)) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("** Recv Scatter Request Failed: %d \n",pScatterReq->CompletionStatus));            
+    }
+    
+    if (pScatterReq->CallerFlags & HTC_SCATTER_REQ_FLAGS_PARTIAL_BUNDLE) {
+        partialBundle = TRUE;    
+    }
+    
+    DEV_FINISH_SCATTER_OPERATION(pScatterReq);
+    
+    INIT_HTC_PACKET_QUEUE(&localRecvQueue);
+        
+    pPacket = (HTC_PACKET *)pScatterReq->ScatterList[0].pCallerContexts[0];
+        /* note: all packets in a scatter req are for the same endpoint ! */
+    pEndpoint = &target->EndPoint[pPacket->Endpoint];
+         
+        /* walk through the scatter list and process */
+        /* **** NOTE: DO NOT HOLD ANY LOCKS here, HTCProcessRecvHeader can take the TX lock
+         * as it processes credit reports */
+    for (i = 0; i < pScatterReq->ValidScatterEntries; i++) {
+        pPacket = (HTC_PACKET *)pScatterReq->ScatterList[i].pCallerContexts[0];
+        A_ASSERT(pPacket != NULL);       
+            /* reset count, we are only interested in the look ahead in the last packet when we
+             * break out of this loop */
+        numLookAheads = 0;
+        
+        if (A_SUCCESS(pScatterReq->CompletionStatus)) {      
+                /* process header for each of the recv packets */            
+            status = HTCProcessRecvHeader(target,pPacket,lookAheads,&numLookAheads);
+        } else {
+            status = A_ERROR;    
+        }
+        
+        if (A_SUCCESS(status)) {    
+#ifdef HTC_EP_STAT_PROFILING
+            LOCK_HTC_RX(target);              
+            HTC_RX_STAT_PROFILE(target,pEndpoint,numLookAheads);
+            INC_HTC_EP_STAT(pEndpoint, RxPacketsBundled, 1);
+            UNLOCK_HTC_RX(target);
+#endif      
+            if (i == (pScatterReq->ValidScatterEntries - 1)) {
+                    /* last packet's more packets flag is set based on the lookahead */
+                SET_MORE_RX_PACKET_INDICATION_FLAG(lookAheads,numLookAheads,pEndpoint,pPacket);
+            } else {
+                    /* packets in a bundle automatically have this flag set */
+                FORCE_MORE_RX_PACKET_INDICATION_FLAG(pPacket);
+            }
+             
+            DUMP_RECV_PKT_INFO(pPacket);            
+                /* since we can't hold a lock in this loop, we insert into our local recv queue for
+                 * storage until we can transfer them to the recv completion queue */
+            HTC_PACKET_ENQUEUE(&localRecvQueue,pPacket);
+            
+        } else {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" Recv packet scatter entry %d failed (out of %d) \n",
+                    i, pScatterReq->ValidScatterEntries));
+                /* recycle failed recv */
+            HTC_RECYCLE_RX_PKT(target, pPacket, pEndpoint);
+                /* set flag and continue processing the remaining scatter entries */
+            procError = TRUE;
+        }   
+    
+    }
+  
+        /* free scatter request */
+    DEV_FREE_SCATTER_REQ(&target->Device,pScatterReq);
+   
+    LOCK_HTC_RX(target);   
+        /* transfer the packets in the local recv queue to the recv completion queue */
+    HTC_PACKET_QUEUE_TRANSFER_TO_TAIL(&pEndpoint->RecvIndicationQueue, &localRecvQueue);  
+    
+    UNLOCK_HTC_RX(target);
+    
+    if (!procError) {  
+            /* pipeline the next check (asynchronously) for more packets */           
+        HTCAsyncRecvCheckMorePackets(target,
+                                     lookAheads,
+                                     numLookAheads,
+                                     partialBundle ? FALSE : TRUE);
+    }
+    
+        /* now drain the indication queue */
+    DrainRecvIndicationQueue(target,pEndpoint);
+          
+    AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("-HTCAsyncRecvScatterCompletion \n"));
+}
+
+static A_STATUS HTCIssueRecvPacketBundle(HTC_TARGET        *target,
+                                         HTC_PACKET_QUEUE  *pRecvPktQueue, 
+                                         HTC_PACKET_QUEUE  *pSyncCompletionQueue,
+                                         int               *pNumPacketsFetched,
+                                         A_BOOL             PartialBundle)
+{
+    A_STATUS        status = A_OK;
+    HIF_SCATTER_REQ *pScatterReq;
+    int             i, totalLength;
+    int             pktsToScatter;
+    HTC_PACKET      *pPacket;
+    A_BOOL          asyncMode = (pSyncCompletionQueue == NULL) ? TRUE : FALSE;
+    int             scatterSpaceRemaining = DEV_GET_MAX_BUNDLE_RECV_LENGTH(&target->Device);
+        
+    pktsToScatter = HTC_PACKET_QUEUE_DEPTH(pRecvPktQueue);
+    pktsToScatter = min(pktsToScatter, target->MaxMsgPerBundle);
+        
+    if ((HTC_PACKET_QUEUE_DEPTH(pRecvPktQueue) - pktsToScatter) > 0) {
+            /* we were forced to split this bundle receive operation
+             * all packets in this partial bundle must have their lookaheads ignored */
+        PartialBundle = TRUE;
+            /* this would only happen if the target ignored our max bundle limit */
+        AR_DEBUG_PRINTF(ATH_DEBUG_WARN,
+                         ("HTCIssueRecvPacketBundle : partial bundle detected num:%d , %d \n",
+                         HTC_PACKET_QUEUE_DEPTH(pRecvPktQueue), pktsToScatter));       
+    }
+    
+    totalLength = 0;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("+HTCIssueRecvPacketBundle (Numpackets: %d , actual : %d) \n", 
+        HTC_PACKET_QUEUE_DEPTH(pRecvPktQueue), pktsToScatter));
+    
+    do {
+        
+        pScatterReq = DEV_ALLOC_SCATTER_REQ(&target->Device); 
+        
+        if (pScatterReq == NULL) {
+                /* no scatter resources left, just let caller handle it the legacy way */
+            break;    
+        }        
+    
+        pScatterReq->CallerFlags = 0;
+             
+        if (PartialBundle) {
+                /* mark that this is a partial bundle, this has special ramifications to the
+                 * scatter completion routine */
+            pScatterReq->CallerFlags |= HTC_SCATTER_REQ_FLAGS_PARTIAL_BUNDLE;
+        }
+                   
+            /* convert HTC packets to scatter list */                   
+        for (i = 0; i < pktsToScatter; i++) {
+            int paddedLength;
+            
+            pPacket = HTC_PACKET_DEQUEUE(pRecvPktQueue);
+            A_ASSERT(pPacket != NULL);
+            
+            paddedLength = DEV_CALC_RECV_PADDED_LEN(&target->Device, pPacket->ActualLength);
+     
+            if ((scatterSpaceRemaining - paddedLength) < 0) {
+                    /* exceeds what we can transfer, put the packet back */  
+                HTC_PACKET_ENQUEUE_TO_HEAD(pRecvPktQueue,pPacket);
+                break;    
+            }
+                        
+            scatterSpaceRemaining -= paddedLength;
+                       
+            if (PartialBundle || (i < (pktsToScatter - 1))) {
+                    /* packet 0..n-1 cannot be checked for look-aheads since we are fetching a bundle
+                     * the last packet however can have it's lookahead used */
+                pPacket->PktInfo.AsRx.HTCRxFlags |= HTC_RX_PKT_IGNORE_LOOKAHEAD;
+            }
+            
+            /* note: 1 HTC packet per scatter entry */           
+                /* setup packet into */   
+            pScatterReq->ScatterList[i].pBuffer = pPacket->pBuffer;
+            pScatterReq->ScatterList[i].Length = paddedLength;
+            
+            pPacket->PktInfo.AsRx.HTCRxFlags |= HTC_RX_PKT_PART_OF_BUNDLE;
+            
+            if (asyncMode) {
+                    /* save HTC packet for async completion routine */
+                pScatterReq->ScatterList[i].pCallerContexts[0] = pPacket;
+            } else {
+                    /* queue to caller's sync completion queue, caller will unload this when we return */
+                HTC_PACKET_ENQUEUE(pSyncCompletionQueue,pPacket);    
+            }             
+                   
+            A_ASSERT(pScatterReq->ScatterList[i].Length);
+            totalLength += pScatterReq->ScatterList[i].Length;
+        }            
+        
+        pScatterReq->TotalLength = totalLength;
+        pScatterReq->ValidScatterEntries = i;
+        
+        if (asyncMode) {
+            pScatterReq->CompletionRoutine = HTCAsyncRecvScatterCompletion;
+            pScatterReq->Context = target;
+        }
+        
+        status = DevSubmitScatterRequest(&target->Device, pScatterReq, DEV_SCATTER_READ, asyncMode);
+        
+        if (A_SUCCESS(status)) {
+            *pNumPacketsFetched = i;    
+        }
+        
+        if (!asyncMode) {
+                /* free scatter request */
+            DEV_FREE_SCATTER_REQ(&target->Device, pScatterReq);   
+        }
+        
+    } while (FALSE);
+   
+    AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("-HTCIssueRecvPacketBundle (status:%d) (fetched:%d) \n",
+            status,*pNumPacketsFetched));
+        
+    return status;
+}
+
+static INLINE void CheckRecvWaterMark(HTC_ENDPOINT    *pEndpoint)
+{  
+        /* see if endpoint is using a refill watermark 
+         * ** no need to use a lock here, since we are only inspecting...
+         * caller may must not hold locks when calling this function */
+    if (pEndpoint->EpCallBacks.RecvRefillWaterMark > 0) {
+        if (HTC_PACKET_QUEUE_DEPTH(&pEndpoint->RxBuffers) < pEndpoint->EpCallBacks.RecvRefillWaterMark) {
+                /* call the re-fill handler before we continue */
+            pEndpoint->EpCallBacks.EpRecvRefill(pEndpoint->EpCallBacks.pContext,
+                                                pEndpoint->Id);
+        }
+    }  
+}
+
+/* callback when device layer or lookahead report parsing detects a pending message */
+A_STATUS HTCRecvMessagePendingHandler(void *Context, A_UINT32 MsgLookAheads[], int NumLookAheads, A_BOOL *pAsyncProc, int *pNumPktsFetched)
+{
+    HTC_TARGET      *target = (HTC_TARGET *)Context;
+    A_STATUS         status = A_OK;
+    HTC_PACKET      *pPacket;
+    HTC_ENDPOINT    *pEndpoint;
+    A_BOOL          asyncProc = FALSE;
+    A_UINT32        lookAheads[HTC_HOST_MAX_MSG_PER_BUNDLE];
+    int             pktsFetched;
+    HTC_PACKET_QUEUE recvPktQueue, syncCompletedPktsQueue;
+    A_BOOL          partialBundle;
+    HTC_ENDPOINT_ID id;
+    int             totalFetched = 0;
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("+HTCRecvMessagePendingHandler NumLookAheads: %d \n",NumLookAheads));
+    
+    if (pNumPktsFetched != NULL) {
+        *pNumPktsFetched = 0;    
+    }
+    
+    if (IS_DEV_IRQ_PROCESSING_ASYNC_ALLOWED(&target->Device)) {
+            /* We use async mode to get the packets if the device layer supports it.
+             * The device layer interfaces with HIF in which HIF may have restrictions on
+             * how interrupts are processed */
+        asyncProc = TRUE;
+    }
+
+    if (pAsyncProc != NULL) {
+            /* indicate to caller how we decided to process this */
+        *pAsyncProc = asyncProc;
+    }
+    
+    if (NumLookAheads > HTC_HOST_MAX_MSG_PER_BUNDLE) {
+        A_ASSERT(FALSE);
+        return A_EPROTO; 
+    }
+        
+        /* on first entry copy the lookaheads into our temp array for processing */
+    A_MEMCPY(lookAheads, MsgLookAheads, (sizeof(A_UINT32)) * NumLookAheads);  
+            
+    while (TRUE) {
+        
+            /* reset packets queues */
+        INIT_HTC_PACKET_QUEUE(&recvPktQueue);
+        INIT_HTC_PACKET_QUEUE(&syncCompletedPktsQueue);
+        
+        if (NumLookAheads > HTC_HOST_MAX_MSG_PER_BUNDLE) {
+            status = A_EPROTO;
+            A_ASSERT(FALSE);
+            break;    
+        }
+   
+            /* first lookahead sets the expected endpoint IDs for all packets in a bundle */
+        id = ((HTC_FRAME_HDR *)&lookAheads[0])->EndpointID;
+        pEndpoint = &target->EndPoint[id];
+        
+        if (id >= ENDPOINT_MAX) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("MsgPend, Invalid Endpoint in look-ahead: %d \n",id));
+            status = A_EPROTO;
+            break;
+        }
+        
+            /* try to allocate as many HTC RX packets indicated by the lookaheads
+             * these packets are stored in the recvPkt queue */
+        status = AllocAndPrepareRxPackets(target, 
+                                          lookAheads, 
+                                          NumLookAheads,
+                                          pEndpoint, 
+                                          &recvPktQueue);        
+        if (A_FAILED(status)) {
+            break;    
+        }
+ 
+        if (HTC_PACKET_QUEUE_DEPTH(&recvPktQueue) >= 2) {
+                /* a recv bundle was detected, force IRQ status re-check again */
+            REF_IRQ_STATUS_RECHECK(&target->Device);
+        }
+        
+        totalFetched += HTC_PACKET_QUEUE_DEPTH(&recvPktQueue);
+               
+            /* we've got packet buffers for all we can currently fetch, 
+             * this count is not valid anymore  */
+        NumLookAheads = 0;
+        partialBundle = FALSE;
+       
+            /* now go fetch the list of HTC packets */
+        while (!HTC_QUEUE_EMPTY(&recvPktQueue)) {   
+            
+            pktsFetched = 0;
+                       
+            if (target->RecvBundlingEnabled && (HTC_PACKET_QUEUE_DEPTH(&recvPktQueue) > 1)) {             
+                    /* there are enough packets to attempt a bundle transfer and recv bundling is allowed  */
+                status = HTCIssueRecvPacketBundle(target,
+                                                  &recvPktQueue,
+                                                  asyncProc ? NULL : &syncCompletedPktsQueue,
+                                                  &pktsFetched,
+                                                  partialBundle);                                                   
+                if (A_FAILED(status)) {
+                    break;
+                }
+                
+                if (HTC_PACKET_QUEUE_DEPTH(&recvPktQueue) != 0) {
+                        /* we couldn't fetch all packets at one time, this creates a broken
+                         * bundle  */
+                    partialBundle = TRUE;    
+                }                                                                     
+            }
+            
+                /* see if the previous operation fetched any packets using bundling */
+            if (0 == pktsFetched) {  
+                    /* dequeue one packet */
+                pPacket = HTC_PACKET_DEQUEUE(&recvPktQueue);
+                A_ASSERT(pPacket != NULL);                 
+                                     
+                if (asyncProc) {
+                        /* we use async mode to get the packet if the device layer supports it
+                         * set our callback and context */
+                    pPacket->Completion = HTCRecvCompleteHandler;
+                    pPacket->pContext = target;
+                } else {
+                        /* fully synchronous */
+                    pPacket->Completion = NULL;
+                }
+                
+                if (HTC_PACKET_QUEUE_DEPTH(&recvPktQueue) > 0) {
+                        /* lookaheads in all packets except the last one in the bundle must be ignored */
+                    pPacket->PktInfo.AsRx.HTCRxFlags |= HTC_RX_PKT_IGNORE_LOOKAHEAD;
+                }
+                                    
+                    /* go fetch the packet */
+                status = HTCIssueRecv(target, pPacket);              
+                if (A_FAILED(status)) {
+                    break;
+                }  
+                               
+                if (!asyncProc) {               
+                        /* sent synchronously, queue this packet for synchronous completion */
+                    HTC_PACKET_ENQUEUE(&syncCompletedPktsQueue,pPacket);
+                } 
+                               
+            }
+            
+        }
+
+        if (A_SUCCESS(status)) {  
+            CheckRecvWaterMark(pEndpoint);
+        }
+            
+        if (asyncProc) {
+                /* we did this asynchronously so we can get out of the loop, the asynch processing
+                 * creates a chain of requests to continue processing pending messages in the
+                 * context of callbacks  */
+            break;
+        }
+
+            /* synchronous handling */
+        if (target->Device.DSRCanYield) {
+                /* for the SYNC case, increment count that tracks when the DSR should yield */
+            target->Device.CurrentDSRRecvCount++;    
+        }
+            
+            /* in the sync case, all packet buffers are now filled, 
+             * we can process each packet, check lookaheads and then repeat */ 
+             
+             /* unload sync completion queue */      
+        while (!HTC_QUEUE_EMPTY(&syncCompletedPktsQueue)) {
+            HTC_PACKET_QUEUE    container;
+           
+            pPacket = HTC_PACKET_DEQUEUE(&syncCompletedPktsQueue);
+            A_ASSERT(pPacket != NULL);
+            
+            pEndpoint = &target->EndPoint[pPacket->Endpoint];           
+                /* reset count on each iteration, we are only interested in the last packet's lookahead
+                 * information when we break out of this loop */
+            NumLookAheads = 0;
+                /* process header for each of the recv packets
+                 * note: the lookahead of the last packet is useful for us to continue in this loop */            
+            status = HTCProcessRecvHeader(target,pPacket,lookAheads,&NumLookAheads);
+            if (A_FAILED(status)) {
+                break;
+            }
+            
+            if (HTC_QUEUE_EMPTY(&syncCompletedPktsQueue)) {
+                    /* last packet's more packets flag is set based on the lookahead */
+                SET_MORE_RX_PACKET_INDICATION_FLAG(lookAheads,NumLookAheads,pEndpoint,pPacket);
+            } else {
+                    /* packets in a bundle automatically have this flag set */
+                FORCE_MORE_RX_PACKET_INDICATION_FLAG(pPacket);
+            }
+                /* good packet, indicate it */
+            HTC_RX_STAT_PROFILE(target,pEndpoint,NumLookAheads);
+            
+            if (pPacket->PktInfo.AsRx.HTCRxFlags & HTC_RX_PKT_PART_OF_BUNDLE) {
+                INC_HTC_EP_STAT(pEndpoint, RxPacketsBundled, 1);
+            }
+            
+            INIT_HTC_PACKET_QUEUE_AND_ADD(&container,pPacket);
+            DO_RCV_COMPLETION(pEndpoint,&container);
+        }
+
+        if (A_FAILED(status)) {
+            break;
+        }
+            
+        if (NumLookAheads == 0) {
+                /* no more look aheads */
+            break;    
+        }
+
+            /* when we process recv synchronously we need to check if we should yield and stop
+             * fetching more packets indicated by the embedded lookaheads */
+        if (target->Device.DSRCanYield) {
+            if (DEV_CHECK_RECV_YIELD(&target->Device)) {
+                    /* break out, don't fetch any more packets */
+                break;  
+            }  
+        }
+            
+
+        /* check whether other OS contexts have queued any WMI command/data for WLAN. 
+         * This check is needed only if WLAN Tx and Rx happens in same thread context */
+        A_CHECK_DRV_TX();
+        
+            /* for SYNCH processing, if we get here, we are running through the loop again due to a detected lookahead.
+             * Set flag that we should re-check IRQ status registers again before leaving IRQ processing,
+             * this can net better performance in high throughput situations */
+        REF_IRQ_STATUS_RECHECK(&target->Device);
+    }
+    
+    if (A_FAILED(status)) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                        ("Failed to get pending recv messages (%d) \n",status));
+            /* cleanup any packets we allocated but didn't use to actually fetch any packets */                        
+        while (!HTC_QUEUE_EMPTY(&recvPktQueue)) {   
+            pPacket = HTC_PACKET_DEQUEUE(&recvPktQueue);
+                /* clean up packets */
+            HTC_RECYCLE_RX_PKT(target, pPacket, &target->EndPoint[pPacket->Endpoint]);
+        }
+            /* cleanup any packets in sync completion queue */
+        while (!HTC_QUEUE_EMPTY(&syncCompletedPktsQueue)) {   
+            pPacket = HTC_PACKET_DEQUEUE(&syncCompletedPktsQueue);
+                /* clean up packets */
+            HTC_RECYCLE_RX_PKT(target, pPacket, &target->EndPoint[pPacket->Endpoint]);
+        }
+        if  (HTC_STOPPING(target)) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_WARN,
+                (" Host is going to stop. blocking receiver for HTCStop.. \n"));
+            DevStopRecv(&target->Device, asyncProc ? DEV_STOP_RECV_ASYNC : DEV_STOP_RECV_SYNC);
+        }
+    }
+        /* before leaving, check to see if host ran out of buffers and needs to stop the
+         * receiver */
+    if (target->RecvStateFlags & HTC_RECV_WAIT_BUFFERS) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_WARN,
+                (" Host has no RX buffers, blocking receiver to prevent overrun.. \n"));
+            /* try to stop receive at the device layer */
+        DevStopRecv(&target->Device, asyncProc ? DEV_STOP_RECV_ASYNC : DEV_STOP_RECV_SYNC);
+    }
+    
+    if (pNumPktsFetched != NULL) {
+        *pNumPktsFetched = totalFetched;    
+    }
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("-HTCRecvMessagePendingHandler \n"));
+
+    return status;
+}
+
+A_STATUS HTCAddReceivePktMultiple(HTC_HANDLE HTCHandle, HTC_PACKET_QUEUE *pPktQueue)
+{
+    HTC_TARGET      *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
+    HTC_ENDPOINT    *pEndpoint;
+    A_BOOL          unblockRecv = FALSE;
+    A_STATUS        status = A_OK;
+    HTC_PACKET      *pFirstPacket;
+
+    pFirstPacket = HTC_GET_PKT_AT_HEAD(pPktQueue);
+    
+    if (NULL == pFirstPacket) {
+        A_ASSERT(FALSE);
+        return A_EINVAL;    
+    }
+    
+    AR_DEBUG_ASSERT(pFirstPacket->Endpoint < ENDPOINT_MAX);
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
+                    ("+- HTCAddReceivePktMultiple : endPointId: %d, cnt:%d, length: %d\n",
+                    pFirstPacket->Endpoint,
+                    HTC_PACKET_QUEUE_DEPTH(pPktQueue), 
+                    pFirstPacket->BufferLength));
+
+    do {
+
+        pEndpoint = &target->EndPoint[pFirstPacket->Endpoint];
+
+        LOCK_HTC_RX(target);
+
+        if (HTC_STOPPING(target)) {
+            HTC_PACKET *pPacket;
+            
+            UNLOCK_HTC_RX(target);
+            
+                /* walk through queue and mark each one canceled */
+            HTC_PACKET_QUEUE_ITERATE_ALLOW_REMOVE(pPktQueue,pPacket) {
+                pPacket->Status = A_ECANCELED;    
+            } HTC_PACKET_QUEUE_ITERATE_END;
+            
+            DO_RCV_COMPLETION(pEndpoint,pPktQueue);
+            break;
+        }
+
+            /* store receive packets */
+        HTC_PACKET_QUEUE_TRANSFER_TO_TAIL(&pEndpoint->RxBuffers, pPktQueue);
+
+            /* check if we are blocked waiting for a new buffer */
+        if (target->RecvStateFlags & HTC_RECV_WAIT_BUFFERS) {
+            if (target->EpWaitingForBuffers == pFirstPacket->Endpoint) {
+                AR_DEBUG_PRINTF(ATH_DEBUG_RECV,(" receiver was blocked on ep:%d, unblocking.. \n",
+                    target->EpWaitingForBuffers));
+                target->RecvStateFlags &= ~HTC_RECV_WAIT_BUFFERS;
+                target->EpWaitingForBuffers = ENDPOINT_MAX;
+                unblockRecv = TRUE;
+            }
+        }
+
+        UNLOCK_HTC_RX(target);
+
+        if (unblockRecv && !HTC_STOPPING(target)) {
+                /* TODO : implement a buffer threshold count? */
+            DevEnableRecv(&target->Device,DEV_ENABLE_RECV_SYNC);
+        }
+
+    } while (FALSE);
+
+    return status;
+}
+
+/* Makes a buffer available to the HTC module */
+A_STATUS HTCAddReceivePkt(HTC_HANDLE HTCHandle, HTC_PACKET *pPacket)
+{
+    HTC_PACKET_QUEUE queue;
+    INIT_HTC_PACKET_QUEUE_AND_ADD(&queue,pPacket); 
+    return HTCAddReceivePktMultiple(HTCHandle, &queue);       
+}
+
+void HTCUnblockRecv(HTC_HANDLE HTCHandle)
+{
+    HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
+    A_BOOL      unblockRecv = FALSE;
+
+    LOCK_HTC_RX(target);
+
+        /* check if we are blocked waiting for a new buffer */
+    if (target->RecvStateFlags & HTC_RECV_WAIT_BUFFERS) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("HTCUnblockRx : receiver was blocked on ep:%d, unblocking.. \n",
+            target->EpWaitingForBuffers));
+        target->RecvStateFlags &= ~HTC_RECV_WAIT_BUFFERS;
+        target->EpWaitingForBuffers = ENDPOINT_MAX;
+        unblockRecv = TRUE;
+    }
+
+    UNLOCK_HTC_RX(target);
+
+    if (unblockRecv && !HTC_STOPPING(target)) {
+            /* re-enable */
+        DevEnableRecv(&target->Device,DEV_ENABLE_RECV_ASYNC);
+    }
+}
+
+static void HTCFlushRxQueue(HTC_TARGET *target, HTC_ENDPOINT *pEndpoint, HTC_PACKET_QUEUE *pQueue)
+{
+    HTC_PACKET  *pPacket;
+    HTC_PACKET_QUEUE container;
+    
+    LOCK_HTC_RX(target);
+
+    while (1) {
+        pPacket = HTC_PACKET_DEQUEUE(pQueue);
+        if (NULL == pPacket) {
+            break;
+        }
+        UNLOCK_HTC_RX(target);
+        pPacket->Status = A_ECANCELED;
+        pPacket->ActualLength = 0;
+        AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("  Flushing RX packet:0x%lX, length:%d, ep:%d \n",
+                (unsigned long)pPacket, pPacket->BufferLength, pPacket->Endpoint));
+        INIT_HTC_PACKET_QUEUE_AND_ADD(&container,pPacket);
+            /* give the packet back */
+        DO_RCV_COMPLETION(pEndpoint,&container);
+        LOCK_HTC_RX(target);
+    }
+    
+    UNLOCK_HTC_RX(target);
+}
+
+static void HTCFlushEndpointRX(HTC_TARGET *target, HTC_ENDPOINT *pEndpoint)
+{
+        /* flush any recv indications not already made */
+    HTCFlushRxQueue(target,pEndpoint,&pEndpoint->RecvIndicationQueue);
+        /* flush any rx buffers */
+    HTCFlushRxQueue(target,pEndpoint,&pEndpoint->RxBuffers);
+}
+
+void HTCFlushRecvBuffers(HTC_TARGET *target)
+{
+    HTC_ENDPOINT    *pEndpoint;
+    int             i;
+
+    for (i = ENDPOINT_0; i < ENDPOINT_MAX; i++) {
+        pEndpoint = &target->EndPoint[i];
+        if (pEndpoint->ServiceID == 0) {
+                /* not in use.. */
+            continue;
+        }
+        HTCFlushEndpointRX(target,pEndpoint);
+    }
+}
+
+
+void HTCEnableRecv(HTC_HANDLE HTCHandle)
+{
+    HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
+
+    if (!HTC_STOPPING(target)) {
+            /* re-enable */
+        DevEnableRecv(&target->Device,DEV_ENABLE_RECV_SYNC);
+    }
+}
+
+void HTCDisableRecv(HTC_HANDLE HTCHandle)
+{
+    HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
+
+    if (!HTC_STOPPING(target)) {
+            /* disable */
+        DevStopRecv(&target->Device,DEV_ENABLE_RECV_SYNC);
+    }
+}
+
+int HTCGetNumRecvBuffers(HTC_HANDLE      HTCHandle,
+                         HTC_ENDPOINT_ID Endpoint)
+{
+    HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);    
+    return HTC_PACKET_QUEUE_DEPTH(&(target->EndPoint[Endpoint].RxBuffers));
+}
+
+A_STATUS HTCWaitForPendingRecv(HTC_HANDLE   HTCHandle,
+                               A_UINT32     TimeoutInMs,
+                               A_BOOL      *pbIsRecvPending)
+{
+    A_STATUS    status  = A_OK;
+    HTC_TARGET *target  = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
+
+    status = DevWaitForPendingRecv(&target->Device,
+                                    TimeoutInMs,
+                                    pbIsRecvPending);
+
+    return status;
+}
diff --git a/drivers/net/ath6kl/htc2/htc_send.c b/drivers/net/ath6kl/htc2/htc_send.c
new file mode 100644
index 00000000000..bc7ee784826
--- /dev/null
+++ b/drivers/net/ath6kl/htc2/htc_send.c
@@ -0,0 +1,1023 @@
+//------------------------------------------------------------------------------
+// <copyright file="htc_send.c" company="Atheros">
+//    Copyright (c) 2007-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+#include "htc_internal.h"
+
+typedef enum _HTC_SEND_QUEUE_RESULT {
+    HTC_SEND_QUEUE_OK = 0,    /* packet was queued */
+    HTC_SEND_QUEUE_DROP = 1,  /* this packet should be dropped */
+} HTC_SEND_QUEUE_RESULT;
+
+#define DO_EP_TX_COMPLETION(ep,q)  DoSendCompletion(ep,q)
+
+/* call the distribute credits callback with the distribution */
+#define DO_DISTRIBUTION(t,reason,description,pList) \
+{                                             \
+    AR_DEBUG_PRINTF(ATH_DEBUG_SEND,           \
+        ("  calling distribute function (%s) (dfn:0x%lX, ctxt:0x%lX, dist:0x%lX) \n", \
+                (description),                                           \
+                (unsigned long)(t)->DistributeCredits,                   \
+                (unsigned long)(t)->pCredDistContext,                    \
+                (unsigned long)pList));                                  \
+    (t)->DistributeCredits((t)->pCredDistContext,                        \
+                           (pList),                                      \
+                           (reason));                                    \
+}
+
+static void DoSendCompletion(HTC_ENDPOINT       *pEndpoint,
+                             HTC_PACKET_QUEUE   *pQueueToIndicate)
+{           
+    do {
+                
+        if (HTC_QUEUE_EMPTY(pQueueToIndicate)) {
+                /* nothing to indicate */
+            break;    
+        }
+ 
+        if (pEndpoint->EpCallBacks.EpTxCompleteMultiple != NULL) {    
+            AR_DEBUG_PRINTF(ATH_DEBUG_SEND, (" HTC calling ep %d, send complete multiple callback (%d pkts) \n",
+                     pEndpoint->Id, HTC_PACKET_QUEUE_DEPTH(pQueueToIndicate)));
+                /* a multiple send complete handler is being used, pass the queue to the handler */                             
+            pEndpoint->EpCallBacks.EpTxCompleteMultiple(pEndpoint->EpCallBacks.pContext,
+                                                        pQueueToIndicate);
+                /* all packets are now owned by the callback, reset queue to be safe */
+            INIT_HTC_PACKET_QUEUE(pQueueToIndicate);                                                      
+        } else {
+            HTC_PACKET *pPacket;  
+            /* using legacy EpTxComplete */         
+            do {
+                pPacket = HTC_PACKET_DEQUEUE(pQueueToIndicate);
+                AR_DEBUG_PRINTF(ATH_DEBUG_SEND, (" HTC calling ep %d send complete callback on packet 0x%lX \n", \
+                        pEndpoint->Id, (unsigned long)(pPacket)));
+                pEndpoint->EpCallBacks.EpTxComplete(pEndpoint->EpCallBacks.pContext, pPacket);                                              
+            } while (!HTC_QUEUE_EMPTY(pQueueToIndicate));                                              
+        }
+        
+    } while (FALSE);
+
+}
+
+/* do final completion on sent packet */
+static INLINE void CompleteSentPacket(HTC_TARGET *target, HTC_ENDPOINT *pEndpoint, HTC_PACKET *pPacket)
+{
+    pPacket->Completion = NULL;  
+    
+    if (A_FAILED(pPacket->Status)) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+            ("CompleteSentPacket: request failed (status:%d, ep:%d, length:%d creds:%d) \n",
+                pPacket->Status, pPacket->Endpoint, pPacket->ActualLength, pPacket->PktInfo.AsTx.CreditsUsed));                
+            /* on failure to submit, reclaim credits for this packet */        
+        LOCK_HTC_TX(target);        
+        pEndpoint->CreditDist.TxCreditsToDist += pPacket->PktInfo.AsTx.CreditsUsed;
+        pEndpoint->CreditDist.TxQueueDepth = HTC_PACKET_QUEUE_DEPTH(&pEndpoint->TxQueue);
+        DO_DISTRIBUTION(target,
+                        HTC_CREDIT_DIST_SEND_COMPLETE,
+                        "Send Complete",
+                        target->EpCreditDistributionListHead->pNext);
+        UNLOCK_HTC_TX(target);            
+    }
+        /* first, fixup the head room we allocated */
+    pPacket->pBuffer += HTC_HDR_LENGTH; 
+}
+
+/* our internal send packet completion handler when packets are submited to the AR6K device
+ * layer */
+static void HTCSendPktCompletionHandler(void *Context, HTC_PACKET *pPacket)
+{
+    HTC_TARGET      *target = (HTC_TARGET *)Context;
+    HTC_ENDPOINT    *pEndpoint = &target->EndPoint[pPacket->Endpoint];
+    HTC_PACKET_QUEUE container;
+    
+    CompleteSentPacket(target,pEndpoint,pPacket);
+    INIT_HTC_PACKET_QUEUE_AND_ADD(&container,pPacket);
+        /* do completion */
+    DO_EP_TX_COMPLETION(pEndpoint,&container);
+}
+
+A_STATUS HTCIssueSend(HTC_TARGET *target, HTC_PACKET *pPacket)
+{
+    A_STATUS status;
+    A_BOOL   sync = FALSE;
+
+    if (pPacket->Completion == NULL) {
+            /* mark that this request was synchronously issued */
+        sync = TRUE;
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_SEND,
+                    ("+-HTCIssueSend: transmit length : %d (%s) \n",
+                    pPacket->ActualLength + (A_UINT32)HTC_HDR_LENGTH,
+                    sync ? "SYNC" : "ASYNC" ));
+
+        /* send message to device */
+    status = DevSendPacket(&target->Device,
+                           pPacket,
+                           pPacket->ActualLength + HTC_HDR_LENGTH);
+
+    if (sync) {
+            /* use local sync variable.  If this was issued asynchronously, pPacket is no longer
+             * safe to access. */
+        pPacket->pBuffer += HTC_HDR_LENGTH;
+    }
+    
+    /* if this request was asynchronous, the packet completion routine will be invoked by
+     * the device layer when the HIF layer completes the request */
+
+    return status;
+}
+
+    /* get HTC send packets from the TX queue on an endpoint */
+static INLINE void GetHTCSendPackets(HTC_TARGET        *target, 
+                                     HTC_ENDPOINT      *pEndpoint, 
+                                     HTC_PACKET_QUEUE  *pQueue)
+{
+    int          creditsRequired;
+    int          remainder;
+    A_UINT8      sendFlags;
+    HTC_PACKET   *pPacket;
+    unsigned int transferLength;
+
+    /****** NOTE : the TX lock is held when this function is called *****************/
+    AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("+GetHTCSendPackets \n"));
+     
+        /* loop until we can grab as many packets out of the queue as we can */       
+    while (TRUE) {    
+        
+        sendFlags = 0;   
+            /* get packet at head, but don't remove it */
+        pPacket = HTC_GET_PKT_AT_HEAD(&pEndpoint->TxQueue);       
+        if (pPacket == NULL) {
+            break;    
+        }
+        
+        AR_DEBUG_PRINTF(ATH_DEBUG_SEND,(" Got head packet:0x%lX , Queue Depth: %d\n",
+                (unsigned long)pPacket, HTC_PACKET_QUEUE_DEPTH(&pEndpoint->TxQueue)));
+        
+        transferLength = DEV_CALC_SEND_PADDED_LEN(&target->Device, pPacket->ActualLength + HTC_HDR_LENGTH);       
+       
+        if (transferLength <= target->TargetCreditSize) {
+            creditsRequired = 1;    
+        } else {
+                /* figure out how many credits this message requires */
+            creditsRequired = transferLength / target->TargetCreditSize;
+            remainder = transferLength % target->TargetCreditSize;
+            
+            if (remainder) {
+                creditsRequired++;
+            }
+        }
+
+        AR_DEBUG_PRINTF(ATH_DEBUG_SEND,(" Creds Required:%d   Got:%d\n",
+                            creditsRequired, pEndpoint->CreditDist.TxCredits));
+
+        if (pEndpoint->CreditDist.TxCredits < creditsRequired) {
+
+                /* not enough credits */
+            if (pPacket->Endpoint == ENDPOINT_0) {
+                    /* leave it in the queue */
+                break;
+            }
+                /* invoke the registered distribution function only if this is not
+                 * endpoint 0, we let the driver layer provide more credits if it can.
+                 * We pass the credit distribution list starting at the endpoint in question
+                 * */
+
+                /* set how many credits we need  */
+            pEndpoint->CreditDist.TxCreditsSeek =
+                                    creditsRequired - pEndpoint->CreditDist.TxCredits;
+            DO_DISTRIBUTION(target,
+                            HTC_CREDIT_DIST_SEEK_CREDITS,
+                            "Seek Credits",
+                            &pEndpoint->CreditDist);
+            pEndpoint->CreditDist.TxCreditsSeek = 0;
+
+            if (pEndpoint->CreditDist.TxCredits < creditsRequired) {
+                    /* still not enough credits to send, leave packet in the queue */
+                AR_DEBUG_PRINTF(ATH_DEBUG_SEND,
+                    (" Not enough credits for ep %d leaving packet in queue..\n",
+                    pPacket->Endpoint));
+                break;
+            }
+
+        }
+
+        pEndpoint->CreditDist.TxCredits -= creditsRequired;
+        INC_HTC_EP_STAT(pEndpoint, TxCreditsConsummed, creditsRequired);
+
+            /* check if we need credits back from the target */
+        if (pEndpoint->CreditDist.TxCredits < pEndpoint->CreditDist.TxCreditsPerMaxMsg) {
+                /* we are getting low on credits, see if we can ask for more from the distribution function */
+            pEndpoint->CreditDist.TxCreditsSeek =
+                        pEndpoint->CreditDist.TxCreditsPerMaxMsg - pEndpoint->CreditDist.TxCredits;
+
+            DO_DISTRIBUTION(target,
+                            HTC_CREDIT_DIST_SEEK_CREDITS,
+                            "Seek Credits",
+                            &pEndpoint->CreditDist);
+
+            pEndpoint->CreditDist.TxCreditsSeek = 0;
+                /* see if we were successful in getting more */
+            if (pEndpoint->CreditDist.TxCredits < pEndpoint->CreditDist.TxCreditsPerMaxMsg) {
+                    /* tell the target we need credits ASAP! */
+                sendFlags |= HTC_FLAGS_NEED_CREDIT_UPDATE;
+                INC_HTC_EP_STAT(pEndpoint, TxCreditLowIndications, 1);
+                AR_DEBUG_PRINTF(ATH_DEBUG_SEND,(" Host Needs Credits  \n"));
+            }
+        }
+                        
+            /* now we can fully dequeue */
+        pPacket = HTC_PACKET_DEQUEUE(&pEndpoint->TxQueue); 
+            /* save the number of credits this packet consumed */
+        pPacket->PktInfo.AsTx.CreditsUsed = creditsRequired;
+            /* all TX packets are handled asynchronously */
+        pPacket->Completion = HTCSendPktCompletionHandler;
+        pPacket->pContext = target;
+        INC_HTC_EP_STAT(pEndpoint, TxIssued, 1);
+            /* save send flags */
+        pPacket->PktInfo.AsTx.SendFlags = sendFlags;
+        pPacket->PktInfo.AsTx.SeqNo = pEndpoint->SeqNo;         
+        pEndpoint->SeqNo++;
+            /* queue this packet into the caller's queue */
+        HTC_PACKET_ENQUEUE(pQueue,pPacket);
+    }
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("-GetHTCSendPackets \n"));
+     
+}
+
+static void HTCAsyncSendScatterCompletion(HIF_SCATTER_REQ *pScatterReq)
+{
+    int                 i;    
+    HTC_PACKET          *pPacket;
+    HTC_ENDPOINT        *pEndpoint = (HTC_ENDPOINT *)pScatterReq->Context;
+    HTC_TARGET          *target = (HTC_TARGET *)pEndpoint->target;
+    A_STATUS            status = A_OK;
+    HTC_PACKET_QUEUE    sendCompletes;
+    
+    INIT_HTC_PACKET_QUEUE(&sendCompletes);
+          
+    AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("+HTCAsyncSendScatterCompletion  TotLen: %d  Entries: %d\n",
+        pScatterReq->TotalLength, pScatterReq->ValidScatterEntries));
+    
+    DEV_FINISH_SCATTER_OPERATION(pScatterReq);
+           
+    if (A_FAILED(pScatterReq->CompletionStatus)) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("** Send Scatter Request Failed: %d \n",pScatterReq->CompletionStatus));            
+        status = A_ERROR;
+    }
+    
+        /* walk through the scatter list and process */
+    for (i = 0; i < pScatterReq->ValidScatterEntries; i++) {
+        pPacket = (HTC_PACKET *)(pScatterReq->ScatterList[i].pCallerContexts[0]);
+        A_ASSERT(pPacket != NULL);
+        pPacket->Status = status;
+        CompleteSentPacket(target,pEndpoint,pPacket);
+            /* add it to the completion queue */
+        HTC_PACKET_ENQUEUE(&sendCompletes, pPacket);      
+    }
+    
+        /* free scatter request */
+    DEV_FREE_SCATTER_REQ(&target->Device,pScatterReq);
+        /* complete all packets */
+    DO_EP_TX_COMPLETION(pEndpoint,&sendCompletes);
+               
+    AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("-HTCAsyncSendScatterCompletion \n"));
+}
+
+    /* drain a queue and send as bundles 
+     * this function may return without fully draining the queue under the following conditions :
+     *    - scatter resources are exhausted
+     *    - a message that will consume a partial credit will stop the bundling process early 
+     *    - we drop below the minimum number of messages for a bundle 
+     * */
+static void HTCIssueSendBundle(HTC_ENDPOINT      *pEndpoint, 
+                               HTC_PACKET_QUEUE  *pQueue, 
+                               int               *pBundlesSent, 
+                               int               *pTotalBundlesPkts)
+{
+    int                 pktsToScatter;
+    unsigned int        scatterSpaceRemaining;
+    HIF_SCATTER_REQ     *pScatterReq = NULL;
+    int                 i, packetsInScatterReq;
+    unsigned int        transferLength;
+    HTC_PACKET          *pPacket;
+    A_BOOL              done = FALSE;
+    int                 bundlesSent = 0;
+    int                 totalPktsInBundle = 0;
+    HTC_TARGET          *target = pEndpoint->target;
+    int                 creditRemainder = 0;
+    int                 creditPad;
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("+HTCIssueSendBundle \n"));
+    
+    while (!done) {
+          
+        pktsToScatter = HTC_PACKET_QUEUE_DEPTH(pQueue);
+        pktsToScatter = min(pktsToScatter, target->MaxMsgPerBundle);
+        
+        if (pktsToScatter < HTC_MIN_HTC_MSGS_TO_BUNDLE) {
+                /* not enough to bundle */
+            break;    
+        }
+        
+        pScatterReq = DEV_ALLOC_SCATTER_REQ(&target->Device); 
+        
+        if (pScatterReq == NULL) {
+                /* no scatter resources  */
+            AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("   No more scatter resources \n"));
+            break;    
+        }       
+        
+        AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("   pkts to scatter: %d \n", pktsToScatter));
+        
+        pScatterReq->TotalLength = 0;
+        pScatterReq->ValidScatterEntries = 0;  
+        
+        packetsInScatterReq = 0;
+        scatterSpaceRemaining = DEV_GET_MAX_BUNDLE_SEND_LENGTH(&target->Device);
+        
+        for (i = 0; i < pktsToScatter; i++) {
+            
+            pScatterReq->ScatterList[i].pCallerContexts[0] = NULL;
+            
+            pPacket = HTC_GET_PKT_AT_HEAD(pQueue);        
+            if (pPacket == NULL) {
+                A_ASSERT(FALSE);
+                break;    
+            }
+            
+            creditPad = 0;
+            transferLength = DEV_CALC_SEND_PADDED_LEN(&target->Device, 
+                                                      pPacket->ActualLength + HTC_HDR_LENGTH);               
+                /* see if the padded transfer length falls on a credit boundary */         
+            creditRemainder = transferLength % target->TargetCreditSize;
+                                
+            if (creditRemainder != 0) {
+                    /* the transfer consumes a "partial" credit, this packet cannot be bundled unless
+                     * we add additional "dummy" padding (max 255 bytes) to consume the entire credit 
+                     *** NOTE: only allow the send padding if the endpoint is allowed to */
+                if (pEndpoint->LocalConnectionFlags & HTC_LOCAL_CONN_FLAGS_ENABLE_SEND_BUNDLE_PADDING) {
+                    if (transferLength < target->TargetCreditSize) {
+                            /* special case where the transfer is less than a credit */
+                        creditPad = target->TargetCreditSize - transferLength;                    
+                    } else {
+                        creditPad = creditRemainder;    
+                    }
+                                    
+                        /* now check to see if we can indicate padding in the HTC header */
+                    if ((creditPad > 0) && (creditPad <= 255)) {
+                            /* adjust the transferlength of this packet with the new credit padding */
+                        transferLength += creditPad;            
+                    } else {
+                            /* the amount to pad is too large, bail on this packet, we have to 
+                             * send it using the non-bundled method */
+                        pPacket = NULL;
+                    }
+                } else {
+                        /* bail on this packet, user does not want padding applied */
+                    pPacket = NULL;    
+                }
+            }                       
+                       
+            if (NULL == pPacket) {
+                    /* can't bundle */
+                done = TRUE;
+                break;    
+            }         
+               
+            if (scatterSpaceRemaining < transferLength) {
+                    /* exceeds what we can transfer */
+                break;    
+            }
+            
+            scatterSpaceRemaining -= transferLength;
+                /* now remove it from the queue */ 
+            pPacket = HTC_PACKET_DEQUEUE(pQueue);           
+                /* save it in the scatter list */
+            pScatterReq->ScatterList[i].pCallerContexts[0] = pPacket;            
+                /* prepare packet and flag message as part of a send bundle */               
+            HTC_PREPARE_SEND_PKT(pPacket,
+                                 pPacket->PktInfo.AsTx.SendFlags | HTC_FLAGS_SEND_BUNDLE, 
+                                 creditPad,                                 
+                                 pPacket->PktInfo.AsTx.SeqNo); 
+            pScatterReq->ScatterList[i].pBuffer = pPacket->pBuffer;
+            pScatterReq->ScatterList[i].Length = transferLength;
+            A_ASSERT(transferLength);
+            pScatterReq->TotalLength += transferLength;
+            pScatterReq->ValidScatterEntries++;
+            packetsInScatterReq++;             
+            AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("  %d, Adding packet : 0x%lX, len:%d (remaining space:%d) \n", 
+                    i, (unsigned long)pPacket,transferLength,scatterSpaceRemaining));                                                      
+        }
+                    
+        if (packetsInScatterReq >= HTC_MIN_HTC_MSGS_TO_BUNDLE) {          
+                /* send path is always asynchronous */
+            pScatterReq->CompletionRoutine = HTCAsyncSendScatterCompletion;
+            pScatterReq->Context = pEndpoint;
+            bundlesSent++;
+            totalPktsInBundle += packetsInScatterReq;
+            packetsInScatterReq = 0;
+            AR_DEBUG_PRINTF(ATH_DEBUG_SEND,(" Send Scatter total bytes: %d , entries: %d\n",
+                                pScatterReq->TotalLength,pScatterReq->ValidScatterEntries));
+            DevSubmitScatterRequest(&target->Device, pScatterReq, DEV_SCATTER_WRITE, DEV_SCATTER_ASYNC);
+                /* we don't own this anymore */
+            pScatterReq = NULL;
+                /* try to send some more */
+            continue;               
+        } 
+        
+            /* not enough packets to use the scatter request, cleanup */
+        if (pScatterReq != NULL) {
+            if (packetsInScatterReq > 0) {
+                    /* work backwards to requeue requests */
+                for (i = (packetsInScatterReq - 1); i >= 0; i--) {
+                    pPacket = (HTC_PACKET *)(pScatterReq->ScatterList[i].pCallerContexts[0]);
+                    if (pPacket != NULL) {
+                            /* undo any prep */
+                        HTC_UNPREPARE_SEND_PKT(pPacket);
+                            /* queue back to the head */
+                        HTC_PACKET_ENQUEUE_TO_HEAD(pQueue,pPacket);   
+                    }  
+                }  
+            }               
+            DEV_FREE_SCATTER_REQ(&target->Device,pScatterReq);    
+        }  
+        
+        /* if we get here, we sent all that we could, get out */
+        break;  
+        
+    }
+    
+    *pBundlesSent = bundlesSent;
+    *pTotalBundlesPkts = totalPktsInBundle;
+    AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("-HTCIssueSendBundle (sent:%d) \n",bundlesSent));  
+     
+    return; 
+}
+
+/*
+ * if there are no credits, the packet(s) remains in the queue.
+ * this function returns the result of the attempt to send a queue of HTC packets */
+static HTC_SEND_QUEUE_RESULT HTCTrySend(HTC_TARGET       *target,
+                                        HTC_ENDPOINT     *pEndpoint,
+                                        HTC_PACKET_QUEUE *pCallersSendQueue)
+{
+    HTC_PACKET_QUEUE      sendQueue; /* temp queue to hold packets at various stages */
+    HTC_PACKET            *pPacket;
+    int                   bundlesSent;
+    int                   pktsInBundles;
+    int                   overflow;
+    HTC_SEND_QUEUE_RESULT result = HTC_SEND_QUEUE_OK;
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("+HTCTrySend (Queue:0x%lX Depth:%d)\n",
+            (unsigned long)pCallersSendQueue, 
+            (pCallersSendQueue == NULL) ? 0 : HTC_PACKET_QUEUE_DEPTH(pCallersSendQueue)));
+
+        /* init the local send queue */
+    INIT_HTC_PACKET_QUEUE(&sendQueue);
+    
+    do {
+        
+        if (NULL == pCallersSendQueue) {
+                /* caller didn't provide a queue, just wants us to check queues and send */
+            break;    
+        }
+        
+        if (HTC_QUEUE_EMPTY(pCallersSendQueue)) {
+                /* empty queue */
+            result = HTC_SEND_QUEUE_DROP;
+            break;    
+        }
+  
+        if (HTC_PACKET_QUEUE_DEPTH(&pEndpoint->TxQueue) >= pEndpoint->MaxTxQueueDepth) {
+                    /* we've already overflowed */
+            overflow = HTC_PACKET_QUEUE_DEPTH(pCallersSendQueue);    
+        } else {
+                /* figure out how much we will overflow by */
+            overflow = HTC_PACKET_QUEUE_DEPTH(&pEndpoint->TxQueue);
+            overflow += HTC_PACKET_QUEUE_DEPTH(pCallersSendQueue); 
+                /* figure out how much we will overflow the TX queue by */
+            overflow -= pEndpoint->MaxTxQueueDepth;     
+        }
+                     
+            /* if overflow is negative or zero, we are okay */    
+        if (overflow > 0) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_SEND, 
+                (" Endpoint %d, TX queue will overflow :%d , Tx Depth:%d, Max:%d \n",
+                pEndpoint->Id, overflow, HTC_PACKET_QUEUE_DEPTH(&pEndpoint->TxQueue), pEndpoint->MaxTxQueueDepth));      
+        }   
+        if ((overflow <= 0) || (pEndpoint->EpCallBacks.EpSendFull == NULL)) {
+                /* all packets will fit or caller did not provide send full indication handler
+                 * --  just move all of them to the local sendQueue object */
+            HTC_PACKET_QUEUE_TRANSFER_TO_TAIL(&sendQueue, pCallersSendQueue);           
+        } else {
+            int               i;
+            int               goodPkts = HTC_PACKET_QUEUE_DEPTH(pCallersSendQueue) - overflow;
+                        
+            A_ASSERT(goodPkts >= 0);
+                /* we have overflowed, and a callback is provided */        
+                /* dequeue all non-overflow packets into the sendqueue */
+            for (i = 0; i < goodPkts; i++) {
+                    /* pop off caller's queue*/
+                pPacket = HTC_PACKET_DEQUEUE(pCallersSendQueue);
+                A_ASSERT(pPacket != NULL);
+                    /* insert into local queue */
+                HTC_PACKET_ENQUEUE(&sendQueue,pPacket);
+            }
+            
+                /* the caller's queue has all the packets that won't fit*/                
+                /* walk through the caller's queue and indicate each one to the send full handler */            
+            ITERATE_OVER_LIST_ALLOW_REMOVE(&pCallersSendQueue->QueueHead, pPacket, HTC_PACKET, ListLink) {            
+                
+                AR_DEBUG_PRINTF(ATH_DEBUG_SEND, (" Indicating overflowed TX packet: 0x%lX \n", 
+                                            (unsigned long)pPacket));    
+                if (pEndpoint->EpCallBacks.EpSendFull(pEndpoint->EpCallBacks.pContext,
+                                                      pPacket) == HTC_SEND_FULL_DROP) {
+                        /* callback wants the packet dropped */
+                    INC_HTC_EP_STAT(pEndpoint, TxDropped, 1);
+                        /* leave this one in the caller's queue for cleanup */
+                } else {
+                        /* callback wants to keep this packet, remove from caller's queue */
+                    HTC_PACKET_REMOVE(pCallersSendQueue, pPacket);
+                        /* put it in the send queue */
+                    HTC_PACKET_ENQUEUE(&sendQueue,pPacket);                                      
+                }
+                
+            } ITERATE_END;
+            
+            if (HTC_QUEUE_EMPTY(&sendQueue)) {
+                    /* no packets made it in, caller will cleanup */
+                result = HTC_SEND_QUEUE_DROP;
+                break;   
+            } 
+        }
+        
+    } while (FALSE);
+    
+    if (result != HTC_SEND_QUEUE_OK) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("-HTCTrySend:  \n"));
+        return result;
+    }
+
+    LOCK_HTC_TX(target);
+    
+    if (!HTC_QUEUE_EMPTY(&sendQueue)) {
+            /* transfer packets */
+        HTC_PACKET_QUEUE_TRANSFER_TO_TAIL(&pEndpoint->TxQueue,&sendQueue);
+        A_ASSERT(HTC_QUEUE_EMPTY(&sendQueue));
+        INIT_HTC_PACKET_QUEUE(&sendQueue); 
+    }
+    
+        /* increment tx processing count on entry */    
+    pEndpoint->TxProcessCount++;
+    if (pEndpoint->TxProcessCount > 1) {
+            /* another thread or task is draining the TX queues on this endpoint
+             * that thread will reset the tx processing count when the queue is drained */
+        pEndpoint->TxProcessCount--;
+        UNLOCK_HTC_TX(target);
+        AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("-HTCTrySend (busy) \n"));
+        return HTC_SEND_QUEUE_OK; 
+    }
+    
+    /***** beyond this point only 1 thread may enter ******/
+            
+        /* now drain the endpoint TX queue for transmission as long as we have enough
+         * credits */
+    while (TRUE) {
+          
+        if (HTC_PACKET_QUEUE_DEPTH(&pEndpoint->TxQueue) == 0) {
+            break;
+        }
+                
+            /* get all the packets for this endpoint that we can for this pass */
+        GetHTCSendPackets(target, pEndpoint, &sendQueue);        
+     
+        if (HTC_PACKET_QUEUE_DEPTH(&sendQueue) == 0) {
+                /* didn't get any packets due to a lack of credits */
+            break;    
+        }
+        
+        UNLOCK_HTC_TX(target);
+        
+            /* any packets to send are now in our local send queue */    
+         
+        bundlesSent = 0;
+        pktsInBundles = 0;
+     
+        while (TRUE) {
+            
+                /* try to send a bundle on each pass */            
+            if ((target->SendBundlingEnabled) &&
+                    (HTC_PACKET_QUEUE_DEPTH(&sendQueue) >= HTC_MIN_HTC_MSGS_TO_BUNDLE)) {
+                 int temp1,temp2;       
+                    /* bundling is enabled and there is at least a minimum number of packets in the send queue
+                     * send what we can in this pass */                       
+                 HTCIssueSendBundle(pEndpoint, &sendQueue, &temp1, &temp2);
+                 bundlesSent += temp1;
+                 pktsInBundles += temp2;
+            }
+        
+                /* if not bundling or there was a packet that could not be placed in a bundle, pull it out
+                 * and send it the normal way */
+            pPacket = HTC_PACKET_DEQUEUE(&sendQueue);
+            if (NULL == pPacket) {
+                    /* local queue is fully drained */
+                break;    
+            }
+            HTC_PREPARE_SEND_PKT(pPacket,
+                                 pPacket->PktInfo.AsTx.SendFlags,
+                                 0,
+                                 pPacket->PktInfo.AsTx.SeqNo);  
+            HTCIssueSend(target, pPacket);
+            
+                /* go back and see if we can bundle some more */
+        }
+        
+        LOCK_HTC_TX(target);
+        
+        INC_HTC_EP_STAT(pEndpoint, TxBundles, bundlesSent);
+        INC_HTC_EP_STAT(pEndpoint, TxPacketsBundled, pktsInBundles);
+        
+    }
+        
+        /* done with this endpoint, we can clear the count */
+    pEndpoint->TxProcessCount = 0;
+    UNLOCK_HTC_TX(target);
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("-HTCTrySend:  \n"));
+
+    return HTC_SEND_QUEUE_OK;
+}
+
+A_STATUS  HTCSendPktsMultiple(HTC_HANDLE HTCHandle, HTC_PACKET_QUEUE *pPktQueue)
+{
+    HTC_TARGET      *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
+    HTC_ENDPOINT    *pEndpoint;
+    HTC_PACKET      *pPacket;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("+HTCSendPktsMultiple: Queue: 0x%lX, Pkts %d \n",
+                    (unsigned long)pPktQueue, HTC_PACKET_QUEUE_DEPTH(pPktQueue)));
+    
+        /* get packet at head to figure out which endpoint these packets will go into */
+    pPacket = HTC_GET_PKT_AT_HEAD(pPktQueue);
+    if (NULL == pPacket) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("-HTCSendPktsMultiple \n"));
+        return A_EINVAL;   
+    }
+    
+    AR_DEBUG_ASSERT(pPacket->Endpoint < ENDPOINT_MAX);
+    pEndpoint = &target->EndPoint[pPacket->Endpoint];
+    
+    HTCTrySend(target, pEndpoint, pPktQueue);
+
+        /* do completion on any packets that couldn't get in */
+    if (!HTC_QUEUE_EMPTY(pPktQueue)) {        
+        
+        HTC_PACKET_QUEUE_ITERATE_ALLOW_REMOVE(pPktQueue,pPacket) {
+            if (HTC_STOPPING(target)) {
+                pPacket->Status = A_ECANCELED;
+            } else {
+                pPacket->Status = A_NO_RESOURCE;
+            } 
+        } HTC_PACKET_QUEUE_ITERATE_END;
+                   
+        DO_EP_TX_COMPLETION(pEndpoint,pPktQueue);
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("-HTCSendPktsMultiple \n"));
+
+    return A_OK;   
+}
+
+/* HTC API - HTCSendPkt */
+A_STATUS HTCSendPkt(HTC_HANDLE HTCHandle, HTC_PACKET *pPacket)
+{
+    HTC_PACKET_QUEUE queue;
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_SEND,
+                    ("+-HTCSendPkt: Enter endPointId: %d, buffer: 0x%lX, length: %d \n",
+                    pPacket->Endpoint, (unsigned long)pPacket->pBuffer, pPacket->ActualLength));                   
+    INIT_HTC_PACKET_QUEUE_AND_ADD(&queue,pPacket); 
+    return HTCSendPktsMultiple(HTCHandle, &queue);
+}
+
+/* check TX queues to drain because of credit distribution update */
+static INLINE void HTCCheckEndpointTxQueues(HTC_TARGET *target)
+{
+    HTC_ENDPOINT                *pEndpoint;
+    HTC_ENDPOINT_CREDIT_DIST    *pDistItem;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("+HTCCheckEndpointTxQueues \n"));
+    pDistItem = target->EpCreditDistributionListHead;
+
+        /* run through the credit distribution list to see
+         * if there are packets queued
+         * NOTE: no locks need to be taken since the distribution list
+         * is not dynamic (cannot be re-ordered) and we are not modifying any state */
+    while (pDistItem != NULL) {
+        pEndpoint = (HTC_ENDPOINT *)pDistItem->pHTCReserved;
+
+        if (HTC_PACKET_QUEUE_DEPTH(&pEndpoint->TxQueue) > 0) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_SEND, (" Ep %d has %d credits and %d Packets in TX Queue \n",
+                    pDistItem->Endpoint, pEndpoint->CreditDist.TxCredits, HTC_PACKET_QUEUE_DEPTH(&pEndpoint->TxQueue)));
+                /* try to start the stalled queue, this list is ordered by priority.
+                 * Highest priority queue get's processed first, if there are credits available the
+                 * highest priority queue will get a chance to reclaim credits from lower priority
+                 * ones */
+            HTCTrySend(target, pEndpoint, NULL);
+        }
+
+        pDistItem = pDistItem->pNext;
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("-HTCCheckEndpointTxQueues \n"));
+}
+
+/* process credit reports and call distribution function */
+void HTCProcessCreditRpt(HTC_TARGET *target, HTC_CREDIT_REPORT *pRpt, int NumEntries, HTC_ENDPOINT_ID FromEndpoint)
+{
+    int             i;
+    HTC_ENDPOINT    *pEndpoint;
+    int             totalCredits = 0;
+    A_BOOL          doDist = FALSE;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("+HTCProcessCreditRpt, Credit Report Entries:%d \n", NumEntries));
+
+        /* lock out TX while we update credits */
+    LOCK_HTC_TX(target);
+
+    for (i = 0; i < NumEntries; i++, pRpt++) {
+        if (pRpt->EndpointID >= ENDPOINT_MAX) {
+            AR_DEBUG_ASSERT(FALSE);
+            break;
+        }
+
+        pEndpoint = &target->EndPoint[pRpt->EndpointID];
+
+        AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("  Endpoint %d got %d credits \n",
+                pRpt->EndpointID, pRpt->Credits));
+
+
+#ifdef HTC_EP_STAT_PROFILING
+
+        INC_HTC_EP_STAT(pEndpoint, TxCreditRpts, 1);
+        INC_HTC_EP_STAT(pEndpoint, TxCreditsReturned, pRpt->Credits);
+
+        if (FromEndpoint == pRpt->EndpointID) {
+                /* this credit report arrived on the same endpoint indicating it arrived in an RX
+                 * packet */
+            INC_HTC_EP_STAT(pEndpoint, TxCreditsFromRx, pRpt->Credits);
+            INC_HTC_EP_STAT(pEndpoint, TxCreditRptsFromRx, 1);
+        } else if (FromEndpoint == ENDPOINT_0) {
+                /* this credit arrived on endpoint 0 as a NULL message */
+            INC_HTC_EP_STAT(pEndpoint, TxCreditsFromEp0, pRpt->Credits);
+            INC_HTC_EP_STAT(pEndpoint, TxCreditRptsFromEp0, 1);
+        } else {
+                /* arrived on another endpoint */
+            INC_HTC_EP_STAT(pEndpoint, TxCreditsFromOther, pRpt->Credits);
+            INC_HTC_EP_STAT(pEndpoint, TxCreditRptsFromOther, 1);
+        }
+
+#endif
+
+        if (ENDPOINT_0 == pRpt->EndpointID) {
+                /* always give endpoint 0 credits back */
+            pEndpoint->CreditDist.TxCredits += pRpt->Credits;
+        } else {
+                /* for all other endpoints, update credits to distribute, the distribution function
+                 * will handle giving out credits back to the endpoints */
+            pEndpoint->CreditDist.TxCreditsToDist += pRpt->Credits;
+                /* flag that we have to do the distribution */
+            doDist = TRUE;
+        }
+        
+            /* refresh tx depth for distribution function that will recover these credits
+             * NOTE: this is only valid when there are credits to recover! */
+        pEndpoint->CreditDist.TxQueueDepth = HTC_PACKET_QUEUE_DEPTH(&pEndpoint->TxQueue);
+        
+        totalCredits += pRpt->Credits;
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("  Report indicated %d credits to distribute \n", totalCredits));
+
+    if (doDist) {
+            /* this was a credit return based on a completed send operations
+             * note, this is done with the lock held */
+        DO_DISTRIBUTION(target,
+                        HTC_CREDIT_DIST_SEND_COMPLETE,
+                        "Send Complete",
+                        target->EpCreditDistributionListHead->pNext);
+    }
+
+    UNLOCK_HTC_TX(target);
+
+    if (totalCredits) {
+        HTCCheckEndpointTxQueues(target);
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("-HTCProcessCreditRpt \n"));
+}
+
+/* flush endpoint TX queue */
+static void HTCFlushEndpointTX(HTC_TARGET *target, HTC_ENDPOINT *pEndpoint, HTC_TX_TAG Tag)
+{
+    HTC_PACKET          *pPacket;
+    HTC_PACKET_QUEUE    discardQueue;
+    HTC_PACKET_QUEUE    container;
+
+        /* initialize the discard queue */
+    INIT_HTC_PACKET_QUEUE(&discardQueue);
+
+    LOCK_HTC_TX(target);
+
+        /* interate from the front of the TX queue and flush out packets */
+    ITERATE_OVER_LIST_ALLOW_REMOVE(&pEndpoint->TxQueue.QueueHead, pPacket, HTC_PACKET, ListLink) {
+
+            /* check for removal */
+        if ((HTC_TX_PACKET_TAG_ALL == Tag) || (Tag == pPacket->PktInfo.AsTx.Tag)) {
+                /* remove from queue */
+            HTC_PACKET_REMOVE(&pEndpoint->TxQueue, pPacket);
+                /* add it to the discard pile */
+            HTC_PACKET_ENQUEUE(&discardQueue, pPacket);
+        }
+
+    } ITERATE_END;
+
+    UNLOCK_HTC_TX(target);
+
+        /* empty the discard queue */
+    while (1) {
+        pPacket = HTC_PACKET_DEQUEUE(&discardQueue);
+        if (NULL == pPacket) {
+            break;
+        }
+        pPacket->Status = A_ECANCELED;
+        AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("  Flushing TX packet:0x%lX, length:%d, ep:%d tag:0x%X \n",
+                (unsigned long)pPacket, pPacket->ActualLength, pPacket->Endpoint, pPacket->PktInfo.AsTx.Tag));
+        INIT_HTC_PACKET_QUEUE_AND_ADD(&container,pPacket);
+        DO_EP_TX_COMPLETION(pEndpoint,&container);
+    }
+
+}
+
+void DumpCreditDist(HTC_ENDPOINT_CREDIT_DIST *pEPDist)
+{
+    AR_DEBUG_PRINTF(ATH_DEBUG_ANY, ("--- EP : %d  ServiceID: 0x%X    --------------\n",
+                        pEPDist->Endpoint, pEPDist->ServiceID));
+    AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" this:0x%lX next:0x%lX prev:0x%lX\n",
+                (unsigned long)pEPDist, (unsigned long)pEPDist->pNext, (unsigned long)pEPDist->pPrev));
+    AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" DistFlags          : 0x%X \n", pEPDist->DistFlags));
+    AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditsNorm      : %d \n", pEPDist->TxCreditsNorm));
+    AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditsMin       : %d \n", pEPDist->TxCreditsMin));
+    AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCredits          : %d \n", pEPDist->TxCredits));
+    AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditsAssigned  : %d \n", pEPDist->TxCreditsAssigned));
+    AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditsSeek      : %d \n", pEPDist->TxCreditsSeek));
+    AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditSize       : %d \n", pEPDist->TxCreditSize));
+    AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditsPerMaxMsg : %d \n", pEPDist->TxCreditsPerMaxMsg));
+    AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditsToDist    : %d \n", pEPDist->TxCreditsToDist));
+    AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxQueueDepth       : %d \n", 
+                    HTC_PACKET_QUEUE_DEPTH(&((HTC_ENDPOINT *)pEPDist->pHTCReserved)->TxQueue)));                                      
+    AR_DEBUG_PRINTF(ATH_DEBUG_ANY, ("----------------------------------------------------\n"));
+}
+
+void DumpCreditDistStates(HTC_TARGET *target)
+{
+    HTC_ENDPOINT_CREDIT_DIST *pEPList = target->EpCreditDistributionListHead;
+
+    while (pEPList != NULL) {
+        DumpCreditDist(pEPList);
+        pEPList = pEPList->pNext;
+    }
+
+    if (target->DistributeCredits != NULL) {
+        DO_DISTRIBUTION(target,
+                        HTC_DUMP_CREDIT_STATE,
+                        "Dump State",
+                        NULL);
+    }
+}
+
+/* flush all send packets from all endpoint queues */
+void HTCFlushSendPkts(HTC_TARGET *target)
+{
+    HTC_ENDPOINT    *pEndpoint;
+    int             i;
+
+    if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_TRC)) {
+        DumpCreditDistStates(target);
+    }
+
+    for (i = ENDPOINT_0; i < ENDPOINT_MAX; i++) {
+        pEndpoint = &target->EndPoint[i];
+        if (pEndpoint->ServiceID == 0) {
+                /* not in use.. */
+            continue;
+        }
+        HTCFlushEndpointTX(target,pEndpoint,HTC_TX_PACKET_TAG_ALL);
+    }
+
+
+}
+
+/* HTC API to flush an endpoint's TX queue*/
+void HTCFlushEndpoint(HTC_HANDLE HTCHandle, HTC_ENDPOINT_ID Endpoint, HTC_TX_TAG Tag)
+{
+    HTC_TARGET      *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
+    HTC_ENDPOINT    *pEndpoint = &target->EndPoint[Endpoint];
+
+    if (pEndpoint->ServiceID == 0) {
+        AR_DEBUG_ASSERT(FALSE);
+        /* not in use.. */
+        return;
+    }
+
+    HTCFlushEndpointTX(target, pEndpoint, Tag);
+}
+
+/* HTC API to indicate activity to the credit distribution function */
+void HTCIndicateActivityChange(HTC_HANDLE      HTCHandle,
+                               HTC_ENDPOINT_ID Endpoint,
+                               A_BOOL          Active)
+{
+    HTC_TARGET      *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
+    HTC_ENDPOINT    *pEndpoint = &target->EndPoint[Endpoint];
+    A_BOOL          doDist = FALSE;
+
+    if (pEndpoint->ServiceID == 0) {
+        AR_DEBUG_ASSERT(FALSE);
+        /* not in use.. */
+        return;
+    }
+
+    LOCK_HTC_TX(target);
+
+    if (Active) {
+        if (!(pEndpoint->CreditDist.DistFlags & HTC_EP_ACTIVE)) {
+                /* mark active now */
+            pEndpoint->CreditDist.DistFlags |= HTC_EP_ACTIVE;
+            doDist = TRUE;
+        }
+    } else {
+        if (pEndpoint->CreditDist.DistFlags & HTC_EP_ACTIVE) {
+                /* mark inactive now */
+            pEndpoint->CreditDist.DistFlags &= ~HTC_EP_ACTIVE;
+            doDist = TRUE;
+        }
+    }
+
+    if (doDist) {
+            /* indicate current Tx Queue depth to the credit distribution function */
+        pEndpoint->CreditDist.TxQueueDepth = HTC_PACKET_QUEUE_DEPTH(&pEndpoint->TxQueue);
+        /* do distribution again based on activity change
+         * note, this is done with the lock held */
+        DO_DISTRIBUTION(target,
+                        HTC_CREDIT_DIST_ACTIVITY_CHANGE,
+                        "Activity Change",
+                        target->EpCreditDistributionListHead->pNext);
+    }
+
+    UNLOCK_HTC_TX(target);
+
+    if (doDist && !Active) {
+        /* if a stream went inactive and this resulted in a credit distribution change,
+         * some credits may now be available for HTC packets that are stuck in
+         * HTC queues */
+        HTCCheckEndpointTxQueues(target);
+    }
+}
+
+A_BOOL HTCIsEndpointActive(HTC_HANDLE      HTCHandle,
+                           HTC_ENDPOINT_ID Endpoint)
+{
+    HTC_TARGET      *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
+    HTC_ENDPOINT    *pEndpoint = &target->EndPoint[Endpoint];
+
+    if (pEndpoint->ServiceID == 0) {
+        return FALSE;
+    }
+    
+    if (pEndpoint->CreditDist.DistFlags & HTC_EP_ACTIVE) {
+        return TRUE;
+    }
+    
+    return FALSE;
+}
diff --git a/drivers/net/ath6kl/htc2/htc_services.c b/drivers/net/ath6kl/htc2/htc_services.c
new file mode 100644
index 00000000000..64fddc0ee37
--- /dev/null
+++ b/drivers/net/ath6kl/htc2/htc_services.c
@@ -0,0 +1,450 @@
+//------------------------------------------------------------------------------
+// <copyright file="htc_services.c" company="Atheros">
+//    Copyright (c) 2007-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+#include "htc_internal.h"
+
+void HTCControlTxComplete(void *Context, HTC_PACKET *pPacket)
+{
+        /* not implemented
+         * we do not send control TX frames during normal runtime, only during setup  */
+    AR_DEBUG_ASSERT(FALSE);
+}
+
+    /* callback when a control message arrives on this endpoint */
+void HTCControlRecv(void *Context, HTC_PACKET *pPacket)
+{
+    AR_DEBUG_ASSERT(pPacket->Endpoint == ENDPOINT_0);
+
+    if (pPacket->Status == A_ECANCELED) {
+        /* this is a flush operation, return the control packet back to the pool */
+        HTC_FREE_CONTROL_RX((HTC_TARGET*)Context,pPacket);    
+        return;
+    }  
+    
+        /* the only control messages we are expecting are NULL messages (credit resports) */   
+    if (pPacket->ActualLength > 0) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                        ("HTCControlRecv, got message with length:%d \n",
+                        pPacket->ActualLength + (A_UINT32)HTC_HDR_LENGTH));
+
+#ifdef ATH_DEBUG_MODULE
+            /* dump header and message */
+        DebugDumpBytes(pPacket->pBuffer - HTC_HDR_LENGTH,
+                       pPacket->ActualLength + HTC_HDR_LENGTH,
+                       "Unexpected ENDPOINT 0 Message");
+#endif
+    }
+
+    HTC_RECYCLE_RX_PKT((HTC_TARGET*)Context,pPacket,&((HTC_TARGET*)Context)->EndPoint[0]);
+}
+
+A_STATUS HTCSendSetupComplete(HTC_TARGET *target)
+{
+    HTC_PACKET             *pSendPacket = NULL;
+    A_STATUS                status;
+
+    do {
+           /* allocate a packet to send to the target */
+        pSendPacket = HTC_ALLOC_CONTROL_TX(target);
+
+        if (NULL == pSendPacket) {
+            status = A_NO_MEMORY;
+            break;
+        }
+
+        if (target->HTCTargetVersion >= HTC_VERSION_2P1) {
+            HTC_SETUP_COMPLETE_EX_MSG *pSetupCompleteEx;
+            A_UINT32                  setupFlags = 0;
+                   
+            pSetupCompleteEx = (HTC_SETUP_COMPLETE_EX_MSG *)pSendPacket->pBuffer;
+            A_MEMZERO(pSetupCompleteEx, sizeof(HTC_SETUP_COMPLETE_EX_MSG));
+            pSetupCompleteEx->MessageID = HTC_MSG_SETUP_COMPLETE_EX_ID;   
+            if (target->MaxMsgPerBundle > 0) {
+                    /* host can do HTC bundling, indicate this to the target */
+                setupFlags |= HTC_SETUP_COMPLETE_FLAGS_ENABLE_BUNDLE_RECV; 
+                pSetupCompleteEx->MaxMsgsPerBundledRecv = target->MaxMsgPerBundle;
+            }    
+            A_MEMCPY(&pSetupCompleteEx->SetupFlags, &setupFlags, sizeof(pSetupCompleteEx->SetupFlags));            
+            SET_HTC_PACKET_INFO_TX(pSendPacket,
+                                   NULL,
+                                   (A_UINT8 *)pSetupCompleteEx,
+                                   sizeof(HTC_SETUP_COMPLETE_EX_MSG),
+                                   ENDPOINT_0,
+                                   HTC_SERVICE_TX_PACKET_TAG);
+      
+        }  else {            
+            HTC_SETUP_COMPLETE_MSG *pSetupComplete;
+                /* assemble setup complete message */
+            pSetupComplete = (HTC_SETUP_COMPLETE_MSG *)pSendPacket->pBuffer;
+            A_MEMZERO(pSetupComplete, sizeof(HTC_SETUP_COMPLETE_MSG));
+            pSetupComplete->MessageID = HTC_MSG_SETUP_COMPLETE_ID;   
+            SET_HTC_PACKET_INFO_TX(pSendPacket,
+                                   NULL,
+                                   (A_UINT8 *)pSetupComplete,
+                                   sizeof(HTC_SETUP_COMPLETE_MSG),
+                                   ENDPOINT_0,
+                                   HTC_SERVICE_TX_PACKET_TAG);
+        }
+
+            /* we want synchronous operation */
+        pSendPacket->Completion = NULL;
+        HTC_PREPARE_SEND_PKT(pSendPacket,0,0,0);
+            /* send the message */
+        status = HTCIssueSend(target,pSendPacket);
+
+    } while (FALSE);
+
+    if (pSendPacket != NULL) {
+        HTC_FREE_CONTROL_TX(target,pSendPacket);
+    }
+
+    return status;
+}
+
+
+A_STATUS HTCConnectService(HTC_HANDLE               HTCHandle,
+                           HTC_SERVICE_CONNECT_REQ  *pConnectReq,
+                           HTC_SERVICE_CONNECT_RESP *pConnectResp)
+{
+    HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
+    A_STATUS                            status = A_OK;
+    HTC_PACKET                          *pRecvPacket = NULL;
+    HTC_PACKET                          *pSendPacket = NULL;
+    HTC_CONNECT_SERVICE_RESPONSE_MSG    *pResponseMsg;
+    HTC_CONNECT_SERVICE_MSG             *pConnectMsg;
+    HTC_ENDPOINT_ID                     assignedEndpoint = ENDPOINT_MAX;
+    HTC_ENDPOINT                        *pEndpoint;
+    unsigned int                        maxMsgSize = 0;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("+HTCConnectService, target:0x%lX SvcID:0x%X \n",
+               (unsigned long)target, pConnectReq->ServiceID));
+
+    do {
+
+        AR_DEBUG_ASSERT(pConnectReq->ServiceID != 0);
+
+        if (HTC_CTRL_RSVD_SVC == pConnectReq->ServiceID) {
+                /* special case for pseudo control service */
+            assignedEndpoint = ENDPOINT_0;
+            maxMsgSize = HTC_MAX_CONTROL_MESSAGE_LENGTH;
+        } else {
+                /* allocate a packet to send to the target */
+            pSendPacket = HTC_ALLOC_CONTROL_TX(target);
+
+            if (NULL == pSendPacket) {
+                AR_DEBUG_ASSERT(FALSE);
+                status = A_NO_MEMORY;
+                break;
+            }
+                /* assemble connect service message */
+            pConnectMsg = (HTC_CONNECT_SERVICE_MSG *)pSendPacket->pBuffer;
+            AR_DEBUG_ASSERT(pConnectMsg != NULL);
+            A_MEMZERO(pConnectMsg,sizeof(HTC_CONNECT_SERVICE_MSG));
+            pConnectMsg->MessageID = HTC_MSG_CONNECT_SERVICE_ID;
+            pConnectMsg->ServiceID = pConnectReq->ServiceID;
+            pConnectMsg->ConnectionFlags = pConnectReq->ConnectionFlags;
+                /* check caller if it wants to transfer meta data */
+            if ((pConnectReq->pMetaData != NULL) &&
+                (pConnectReq->MetaDataLength <= HTC_SERVICE_META_DATA_MAX_LENGTH)) {
+                    /* copy meta data into message buffer (after header ) */
+                A_MEMCPY((A_UINT8 *)pConnectMsg + sizeof(HTC_CONNECT_SERVICE_MSG),
+                         pConnectReq->pMetaData,
+                         pConnectReq->MetaDataLength);
+                pConnectMsg->ServiceMetaLength = pConnectReq->MetaDataLength;
+            }
+
+            SET_HTC_PACKET_INFO_TX(pSendPacket,
+                                   NULL,
+                                   (A_UINT8 *)pConnectMsg,
+                                   sizeof(HTC_CONNECT_SERVICE_MSG) + pConnectMsg->ServiceMetaLength,
+                                   ENDPOINT_0,
+                                   HTC_SERVICE_TX_PACKET_TAG);
+
+                /* we want synchronous operation */
+            pSendPacket->Completion = NULL;
+            HTC_PREPARE_SEND_PKT(pSendPacket,0,0,0);
+            status = HTCIssueSend(target,pSendPacket);
+
+            if (A_FAILED(status)) {
+                break;
+            }
+
+                /* wait for response */
+            status = HTCWaitforControlMessage(target, &pRecvPacket);
+
+            if (A_FAILED(status)) {
+                break;
+            }
+                /* we controlled the buffer creation so it has to be properly aligned */
+            pResponseMsg = (HTC_CONNECT_SERVICE_RESPONSE_MSG *)pRecvPacket->pBuffer;
+
+            if ((pResponseMsg->MessageID != HTC_MSG_CONNECT_SERVICE_RESPONSE_ID) ||
+                (pRecvPacket->ActualLength < sizeof(HTC_CONNECT_SERVICE_RESPONSE_MSG))) {
+                    /* this message is not valid */
+                AR_DEBUG_ASSERT(FALSE);
+                status = A_EPROTO;
+                break;
+            }
+
+            pConnectResp->ConnectRespCode = pResponseMsg->Status;
+                /* check response status */
+            if (pResponseMsg->Status != HTC_SERVICE_SUCCESS) {
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                    (" Target failed service 0x%X connect request (status:%d)\n",
+                                pResponseMsg->ServiceID, pResponseMsg->Status));
+                status = A_EPROTO;
+                break;
+            }
+
+            assignedEndpoint = (HTC_ENDPOINT_ID) pResponseMsg->EndpointID;
+            maxMsgSize = pResponseMsg->MaxMsgSize;
+
+            if ((pConnectResp->pMetaData != NULL) &&
+                (pResponseMsg->ServiceMetaLength > 0) &&
+                (pResponseMsg->ServiceMetaLength <= HTC_SERVICE_META_DATA_MAX_LENGTH)) {
+                    /* caller supplied a buffer and the target responded with data */
+                int copyLength = min((int)pConnectResp->BufferLength, (int)pResponseMsg->ServiceMetaLength);
+                    /* copy the meta data */
+                A_MEMCPY(pConnectResp->pMetaData,
+                         ((A_UINT8 *)pResponseMsg) + sizeof(HTC_CONNECT_SERVICE_RESPONSE_MSG),
+                         copyLength);
+                pConnectResp->ActualLength = copyLength;
+            }
+
+        }
+
+            /* the rest of these are parameter checks so set the error status */
+        status = A_EPROTO;
+
+        if (assignedEndpoint >= ENDPOINT_MAX) {
+            AR_DEBUG_ASSERT(FALSE);
+            break;
+        }
+
+        if (0 == maxMsgSize) {
+            AR_DEBUG_ASSERT(FALSE);
+            break;
+        }
+
+        pEndpoint = &target->EndPoint[assignedEndpoint];
+        pEndpoint->Id = assignedEndpoint;
+        if (pEndpoint->ServiceID != 0) {
+            /* endpoint already in use! */
+            AR_DEBUG_ASSERT(FALSE);
+            break;
+        }
+
+            /* return assigned endpoint to caller */
+        pConnectResp->Endpoint = assignedEndpoint;
+        pConnectResp->MaxMsgLength = maxMsgSize;
+
+            /* setup the endpoint */
+        pEndpoint->ServiceID = pConnectReq->ServiceID; /* this marks the endpoint in use */
+        pEndpoint->MaxTxQueueDepth = pConnectReq->MaxSendQueueDepth;
+        pEndpoint->MaxMsgLength = maxMsgSize;
+            /* copy all the callbacks */
+        pEndpoint->EpCallBacks = pConnectReq->EpCallbacks;
+            /* set the credit distribution info for this endpoint, this information is
+             * passed back to the credit distribution callback function */
+        pEndpoint->CreditDist.ServiceID = pConnectReq->ServiceID;
+        pEndpoint->CreditDist.pHTCReserved = pEndpoint;
+        pEndpoint->CreditDist.Endpoint = assignedEndpoint;
+        pEndpoint->CreditDist.TxCreditSize = target->TargetCreditSize;
+        
+        if (pConnectReq->MaxSendMsgSize != 0) {
+                /* override TxCreditsPerMaxMsg calculation, this optimizes the credit-low indications
+                 * since the host will actually issue smaller messages in the Send path */
+            if (pConnectReq->MaxSendMsgSize > maxMsgSize) {
+                    /* can't be larger than the maximum the target can support */
+                AR_DEBUG_ASSERT(FALSE);
+                break;       
+            }
+            pEndpoint->CreditDist.TxCreditsPerMaxMsg = pConnectReq->MaxSendMsgSize / target->TargetCreditSize;
+        } else {
+            pEndpoint->CreditDist.TxCreditsPerMaxMsg = maxMsgSize / target->TargetCreditSize;
+        }
+        
+        if (0 == pEndpoint->CreditDist.TxCreditsPerMaxMsg) {
+            pEndpoint->CreditDist.TxCreditsPerMaxMsg = 1;
+        }
+        
+            /* save local connection flags */
+        pEndpoint->LocalConnectionFlags = pConnectReq->LocalConnectionFlags;
+        
+        status = A_OK;
+
+    } while (FALSE);
+
+    if (pSendPacket != NULL) {
+        HTC_FREE_CONTROL_TX(target,pSendPacket);
+    }
+
+    if (pRecvPacket != NULL) {
+        HTC_FREE_CONTROL_RX(target,pRecvPacket);
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("-HTCConnectService \n"));
+
+    return status;
+}
+
+static void AddToEndpointDistList(HTC_TARGET *target, HTC_ENDPOINT_CREDIT_DIST *pEpDist)
+{
+    HTC_ENDPOINT_CREDIT_DIST *pCurEntry,*pLastEntry;
+
+    if (NULL == target->EpCreditDistributionListHead) {
+        target->EpCreditDistributionListHead = pEpDist;
+        pEpDist->pNext = NULL;
+        pEpDist->pPrev = NULL;
+        return;
+    }
+
+        /* queue to the end of the list, this does not have to be very
+         * fast since this list is built at startup time */
+    pCurEntry = target->EpCreditDistributionListHead;
+
+    while (pCurEntry) {
+        pLastEntry = pCurEntry;
+        pCurEntry = pCurEntry->pNext;
+    }
+
+    pLastEntry->pNext = pEpDist;
+    pEpDist->pPrev = pLastEntry;
+    pEpDist->pNext = NULL;
+}
+
+
+
+/* default credit init callback */
+static void HTCDefaultCreditInit(void                     *Context,
+                                 HTC_ENDPOINT_CREDIT_DIST *pEPList,
+                                 int                      TotalCredits)
+{
+    HTC_ENDPOINT_CREDIT_DIST *pCurEpDist;
+    int                      totalEps = 0;
+    int                      creditsPerEndpoint;
+
+    pCurEpDist = pEPList;
+        /* first run through the list and figure out how many endpoints we are dealing with */
+    while (pCurEpDist != NULL) {
+        pCurEpDist = pCurEpDist->pNext;
+        totalEps++;
+    }
+
+        /* even distribution */
+    creditsPerEndpoint = TotalCredits/totalEps;
+
+    pCurEpDist = pEPList;
+        /* run through the list and set minimum and normal credits and
+         * provide the endpoint with some credits to start */
+    while (pCurEpDist != NULL) {
+
+        if (creditsPerEndpoint < pCurEpDist->TxCreditsPerMaxMsg) {
+                /* too many endpoints and not enough credits */
+            AR_DEBUG_ASSERT(FALSE);
+            break;
+        }
+            /* our minimum is set for at least 1 max message */
+        pCurEpDist->TxCreditsMin = pCurEpDist->TxCreditsPerMaxMsg;
+            /* this value is ignored by our credit alg, since we do
+             * not dynamically adjust credits, this is the policy of
+             * the "default" credit distribution, something simple and easy */
+        pCurEpDist->TxCreditsNorm = 0xFFFF;
+            /* give the endpoint minimum credits */
+        pCurEpDist->TxCredits = creditsPerEndpoint;
+        pCurEpDist->TxCreditsAssigned = creditsPerEndpoint;
+        pCurEpDist = pCurEpDist->pNext;
+    }
+
+}
+
+/* default credit distribution callback, NOTE, this callback holds the TX lock */
+void HTCDefaultCreditDist(void                     *Context,
+                          HTC_ENDPOINT_CREDIT_DIST *pEPDistList,
+                          HTC_CREDIT_DIST_REASON   Reason)
+{
+    HTC_ENDPOINT_CREDIT_DIST *pCurEpDist;
+
+    if (Reason == HTC_CREDIT_DIST_SEND_COMPLETE) {
+        pCurEpDist = pEPDistList;
+            /* simple distribution */
+        while (pCurEpDist != NULL) {
+            if (pCurEpDist->TxCreditsToDist > 0) {
+                    /* just give the endpoint back the credits */
+                pCurEpDist->TxCredits += pCurEpDist->TxCreditsToDist;
+                pCurEpDist->TxCreditsToDist = 0;
+            }
+            pCurEpDist = pCurEpDist->pNext;
+        }
+    }
+
+    /* note we do not need to handle the other reason codes as this is a very
+     * simple distribution scheme, no need to seek for more credits or handle inactivity */
+}
+
+void HTCSetCreditDistribution(HTC_HANDLE               HTCHandle,
+                              void                     *pCreditDistContext,
+                              HTC_CREDIT_DIST_CALLBACK CreditDistFunc,
+                              HTC_CREDIT_INIT_CALLBACK CreditInitFunc,
+                              HTC_SERVICE_ID           ServicePriorityOrder[],
+                              int                      ListLength)
+{
+    HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
+    int i;
+    int ep;
+
+    if (CreditInitFunc != NULL) {
+            /* caller has supplied their own distribution functions */
+        target->InitCredits = CreditInitFunc;
+        AR_DEBUG_ASSERT(CreditDistFunc != NULL);
+        target->DistributeCredits = CreditDistFunc;
+        target->pCredDistContext = pCreditDistContext;
+    } else {
+        /* caller wants HTC to do distribution */
+        /* if caller wants service to handle distributions then
+         * it must set both of these to NULL! */
+        AR_DEBUG_ASSERT(CreditDistFunc == NULL);
+        target->InitCredits = HTCDefaultCreditInit;
+        target->DistributeCredits = HTCDefaultCreditDist;
+        target->pCredDistContext = target;
+    }
+
+        /* always add HTC control endpoint first, we only expose the list after the
+         * first one, this is added for TX queue checking */
+    AddToEndpointDistList(target, &target->EndPoint[ENDPOINT_0].CreditDist);
+
+        /* build the list of credit distribution structures in priority order
+         * supplied by the caller, these will follow endpoint 0 */
+    for (i = 0; i < ListLength; i++) {
+            /* match services with endpoints and add the endpoints to the distribution list
+             * in FIFO order */
+        for (ep = ENDPOINT_1; ep < ENDPOINT_MAX; ep++) {
+            if (target->EndPoint[ep].ServiceID == ServicePriorityOrder[i]) {
+                    /* queue this one to the list */
+                AddToEndpointDistList(target, &target->EndPoint[ep].CreditDist);
+                break;
+            }
+        }
+        AR_DEBUG_ASSERT(ep < ENDPOINT_MAX);
+    }
+
+}
diff --git a/drivers/net/ath6kl/include/a_config.h b/drivers/net/ath6kl/include/a_config.h
new file mode 100644
index 00000000000..4a0083c6511
--- /dev/null
+++ b/drivers/net/ath6kl/include/a_config.h
@@ -0,0 +1,53 @@
+//------------------------------------------------------------------------------
+// <copyright file="a_config.h" company="Atheros">
+//    Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// This file contains software configuration options that enables
+// specific software "features"
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _A_CONFIG_H_
+#define _A_CONFIG_H_
+
+#ifdef UNDER_NWIFI
+#include "../os/windows/include/config.h"
+#endif
+
+#ifdef ATHR_CE_LEGACY
+#include "../os/windows/include/config.h"
+#endif
+
+#if defined(__linux__) && !defined(LINUX_EMULATION)
+#include "../os/linux/include/config_linux.h"
+#endif
+
+#ifdef REXOS
+#include "../os/rexos/include/common/config_rexos.h"
+#endif
+
+#ifdef WIN_NWF
+#include "../os/windows/include/win/config_win.h"
+#endif
+
+#ifdef THREADX
+#include "../os/threadx/include/common/config_threadx.h"
+#endif
+
+#endif
diff --git a/drivers/net/ath6kl/include/a_debug.h b/drivers/net/ath6kl/include/a_debug.h
new file mode 100644
index 00000000000..5a1b01fbb93
--- /dev/null
+++ b/drivers/net/ath6kl/include/a_debug.h
@@ -0,0 +1,224 @@
+//------------------------------------------------------------------------------
+// <copyright file="a_debug.h" company="Atheros">
+//    Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _A_DEBUG_H_
+#define _A_DEBUG_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include <a_types.h>
+#include <a_osapi.h>
+
+    /* standard debug print masks bits 0..7 */
+#define ATH_DEBUG_ERR   (1 << 0)   /* errors */
+#define ATH_DEBUG_WARN  (1 << 1)   /* warnings */
+#define ATH_DEBUG_INFO  (1 << 2)   /* informational (module startup info) */
+#define ATH_DEBUG_TRC   (1 << 3)   /* generic function call tracing */
+#define ATH_DEBUG_RSVD1 (1 << 4)
+#define ATH_DEBUG_RSVD2 (1 << 5)
+#define ATH_DEBUG_RSVD3 (1 << 6)
+#define ATH_DEBUG_RSVD4 (1 << 7)
+
+#define ATH_DEBUG_MASK_DEFAULTS  (ATH_DEBUG_ERR | ATH_DEBUG_WARN)
+#define ATH_DEBUG_ANY  0xFFFF
+
+    /* other aliases used throughout */
+#define ATH_DEBUG_ERROR   ATH_DEBUG_ERR
+#define ATH_LOG_ERR       ATH_DEBUG_ERR
+#define ATH_LOG_INF       ATH_DEBUG_INFO
+#define ATH_LOG_TRC       ATH_DEBUG_TRC
+#define ATH_DEBUG_TRACE   ATH_DEBUG_TRC
+#define ATH_DEBUG_INIT    ATH_DEBUG_INFO
+
+    /* bits 8..31 are module-specific masks */
+#define ATH_DEBUG_MODULE_MASK_SHIFT   8
+
+    /* macro to make a module-specific masks */
+#define ATH_DEBUG_MAKE_MODULE_MASK(index)  (1 << (ATH_DEBUG_MODULE_MASK_SHIFT + (index)))
+
+void DebugDumpBytes(A_UCHAR *buffer, A_UINT16 length, char *pDescription);
+
+/* Debug support on a per-module basis
+ *
+ * Usage:
+ *
+ *   Each module can utilize it's own debug mask variable.  A set of commonly used
+ *   masks are provided (ERRORS, WARNINGS, TRACE etc..).  It is up to each module
+ *   to define module-specific masks using the macros above.
+ *
+ *   Each module defines a single debug mask variable debug_XXX where the "name" of the module is
+ *   common to all C-files within that module.  This requires every C-file that includes a_debug.h
+ *   to define the module name in that file.
+ *
+ *   Example:
+ *
+ *   #define ATH_MODULE_NAME htc
+ *   #include "a_debug.h"
+ *
+ *   This will define a debug mask structure called debug_htc and all debug macros will reference this
+ *   variable.
+ *
+ *   A module can define module-specific bit masks using the ATH_DEBUG_MAKE_MODULE_MASK() macro:
+ *
+ *      #define ATH_DEBUG_MY_MASK1  ATH_DEBUG_MAKE_MODULE_MASK(0)
+ *      #define ATH_DEBUG_MY_MASK2  ATH_DEBUG_MAKE_MODULE_MASK(1)
+ *
+ *   The instantiation of the debug structure should be made by the module.  When a module is
+ *   instantiated, the module can set a description string, a default mask and an array of description
+ *   entries containing information on each module-defined debug mask.
+ *   NOTE: The instantiation is statically allocated, only one instance can exist per module.
+ *
+ *   Example:
+ *
+ *
+ *   #define ATH_DEBUG_BMI  ATH_DEBUG_MAKE_MODULE_MASK(0)
+ *
+ *   #ifdef DEBUG
+ *   static ATH_DEBUG_MASK_DESCRIPTION bmi_debug_desc[] = {
+ *       { ATH_DEBUG_BMI , "BMI Tracing"},   <== description of the module specific mask
+ *   };
+ *
+ *   ATH_DEBUG_INSTANTIATE_MODULE_VAR(bmi,
+ *                                    "bmi"  <== module name
+ *                                    "Boot Manager Interface",  <== description of module
+ *                                    ATH_DEBUG_MASK_DEFAULTS,          <== defaults
+ *                                    ATH_DEBUG_DESCRIPTION_COUNT(bmi_debug_desc),
+ *                                    bmi_debug_desc);
+ *
+ *   #endif
+ *
+ *  A module can optionally register it's debug module information in order for other tools to change the
+ *  bit mask at runtime.  A module can call  A_REGISTER_MODULE_DEBUG_INFO() in it's module
+ *  init code.  This macro can be called multiple times without consequence.  The debug info maintains
+ *  state to indicate whether the information was previously registered.
+ *
+ * */
+
+#define ATH_DEBUG_MAX_MASK_DESC_LENGTH   32
+#define ATH_DEBUG_MAX_MOD_DESC_LENGTH    64
+
+typedef struct {
+    A_UINT32 Mask;
+    A_CHAR   Description[ATH_DEBUG_MAX_MASK_DESC_LENGTH];
+} ATH_DEBUG_MASK_DESCRIPTION;
+
+#define ATH_DEBUG_INFO_FLAGS_REGISTERED (1 << 0)
+
+typedef struct  _ATH_DEBUG_MODULE_DBG_INFO{
+    struct _ATH_DEBUG_MODULE_DBG_INFO *pNext;
+    A_CHAR                      ModuleName[16];
+    A_CHAR                      ModuleDescription[ATH_DEBUG_MAX_MOD_DESC_LENGTH];
+    A_UINT32                    Flags;
+    A_UINT32                    CurrentMask;
+    int                         MaxDescriptions;
+    ATH_DEBUG_MASK_DESCRIPTION  *pMaskDescriptions; /* pointer to array of descriptions */
+} ATH_DEBUG_MODULE_DBG_INFO;
+
+#define ATH_DEBUG_DESCRIPTION_COUNT(d)  (int)((sizeof((d))) / (sizeof(ATH_DEBUG_MASK_DESCRIPTION)))
+
+#define GET_ATH_MODULE_DEBUG_VAR_NAME(s) _XGET_ATH_MODULE_NAME_DEBUG_(s)
+#define GET_ATH_MODULE_DEBUG_VAR_MASK(s) _XGET_ATH_MODULE_NAME_DEBUG_(s).CurrentMask
+#define _XGET_ATH_MODULE_NAME_DEBUG_(s) debug_ ## s
+
+#ifdef ATH_DEBUG_MODULE
+
+    /* for source files that will instantiate the debug variables */
+#define ATH_DEBUG_INSTANTIATE_MODULE_VAR(s,name,moddesc,initmask,count,descriptions) \
+ATH_DEBUG_MODULE_DBG_INFO GET_ATH_MODULE_DEBUG_VAR_NAME(s) = \
+            {NULL,(name),(moddesc),0,(initmask),count,(descriptions)}
+
+#ifdef ATH_MODULE_NAME
+extern ATH_DEBUG_MODULE_DBG_INFO GET_ATH_MODULE_DEBUG_VAR_NAME(ATH_MODULE_NAME);
+#define AR_DEBUG_LVL_CHECK(lvl) (GET_ATH_MODULE_DEBUG_VAR_MASK(ATH_MODULE_NAME) & (lvl))
+#endif /* ATH_MODULE_NAME */
+
+#define ATH_DEBUG_SET_DEBUG_MASK(s,lvl) GET_ATH_MODULE_DEBUG_VAR_MASK(s) = (lvl)
+
+#define ATH_DEBUG_DECLARE_EXTERN(s) \
+    extern ATH_DEBUG_MODULE_DBG_INFO GET_ATH_MODULE_DEBUG_VAR_NAME(s)
+
+#define AR_DEBUG_PRINTBUF(buffer, length, desc) DebugDumpBytes(buffer,length,desc)
+
+
+#define AR_DEBUG_ASSERT A_ASSERT
+
+void a_dump_module_debug_info(ATH_DEBUG_MODULE_DBG_INFO *pInfo);
+void a_register_module_debug_info(ATH_DEBUG_MODULE_DBG_INFO *pInfo);
+#define A_DUMP_MODULE_DEBUG_INFO(s) a_dump_module_debug_info(&(GET_ATH_MODULE_DEBUG_VAR_NAME(s)))
+#define A_REGISTER_MODULE_DEBUG_INFO(s) a_register_module_debug_info(&(GET_ATH_MODULE_DEBUG_VAR_NAME(s)))
+
+#else /* !ATH_DEBUG_MODULE */
+    /* NON ATH_DEBUG_MODULE */
+#define ATH_DEBUG_INSTANTIATE_MODULE_VAR(s,name,moddesc,initmask,count,descriptions)
+#define AR_DEBUG_LVL_CHECK(lvl) 0
+#define AR_DEBUG_PRINTBUF(buffer, length, desc)
+#define AR_DEBUG_ASSERT(test)
+#define ATH_DEBUG_DECLARE_EXTERN(s)
+#define ATH_DEBUG_SET_DEBUG_MASK(s,lvl)
+#define A_DUMP_MODULE_DEBUG_INFO(s)
+#define A_REGISTER_MODULE_DEBUG_INFO(s)
+
+#endif
+
+A_STATUS a_get_module_mask(A_CHAR *module_name, A_UINT32 *pMask);
+A_STATUS a_set_module_mask(A_CHAR *module_name, A_UINT32 Mask);
+void a_dump_module_debug_info_by_name(A_CHAR *module_name);
+void a_module_debug_support_init(void);
+void a_module_debug_support_cleanup(void);
+
+#ifdef UNDER_NWIFI
+#include "../os/windows/include/debug.h"
+#endif
+
+#ifdef ATHR_CE_LEGACY
+#include "../os/windows/include/debug.h"
+#endif
+
+#if defined(__linux__) && !defined(LINUX_EMULATION)
+#include "../os/linux/include/debug_linux.h"
+#endif
+
+#ifdef REXOS
+#include "../os/rexos/include/common/debug_rexos.h"
+#endif
+
+#if defined ART_WIN
+#include "../os/win_art/include/debug_win.h"
+#endif
+
+#ifdef WIN_NWF
+#include <debug_win.h>
+#endif
+
+#ifdef THREADX
+#define ATH_DEBUG_MAKE_MODULE_MASK(index)  (1 << (ATH_DEBUG_MODULE_MASK_SHIFT + (index)))
+#include "../os/threadx/include/common/debug_threadx.h"
+#endif  
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif
diff --git a/drivers/net/ath6kl/include/a_drv.h b/drivers/net/ath6kl/include/a_drv.h
new file mode 100644
index 00000000000..6db10f0f2d1
--- /dev/null
+++ b/drivers/net/ath6kl/include/a_drv.h
@@ -0,0 +1,54 @@
+//------------------------------------------------------------------------------
+// <copyright file="a_drv.h" company="Atheros">
+//    Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// This file contains the definitions of the basic atheros data types.
+// It is used to map the data types in atheros files to a platform specific
+// type.
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _A_DRV_H_
+#define _A_DRV_H_
+
+#if defined(__linux__) && !defined(LINUX_EMULATION)
+#include "../os/linux/include/athdrv_linux.h"
+#endif
+
+#ifdef UNDER_NWIFI
+#include "../os/windows/include/athdrv.h"
+#endif
+
+#ifdef ATHR_CE_LEGACY
+#include "../os/windows/include/athdrv.h"
+#endif
+
+#ifdef REXOS
+#include "../os/rexos/include/common/athdrv_rexos.h"
+#endif
+
+#ifdef WIN_NWF
+#include "../os/windows/include/athdrv.h"
+#endif
+
+#ifdef THREADX
+#include "../os/threadx/include/common/athdrv_threadx.h"
+#endif
+
+#endif /* _ADRV_H_ */
diff --git a/drivers/net/ath6kl/include/a_drv_api.h b/drivers/net/ath6kl/include/a_drv_api.h
new file mode 100644
index 00000000000..7d077c62ad7
--- /dev/null
+++ b/drivers/net/ath6kl/include/a_drv_api.h
@@ -0,0 +1,232 @@
+//------------------------------------------------------------------------------
+// <copyright file="a_drv_api.h" company="Atheros">
+//    Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _A_DRV_API_H_
+#define _A_DRV_API_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/****************************************************************************/
+/****************************************************************************/
+/**                                                                        **/
+/** WMI related hooks                                                      **/
+/**                                                                        **/
+/****************************************************************************/
+/****************************************************************************/
+
+#include <ar6000_api.h>
+
+#define A_WMI_CHANNELLIST_RX(devt, numChan, chanList)   \
+    ar6000_channelList_rx((devt), (numChan), (chanList))
+
+#define A_WMI_SET_NUMDATAENDPTS(devt, num)  \
+    ar6000_set_numdataendpts((devt), (num))
+
+#define A_WMI_CONTROL_TX(devt, osbuf, streamID) \
+    ar6000_control_tx((devt), (osbuf), (streamID))
+
+#define A_WMI_TARGETSTATS_EVENT(devt, pStats, len)  \
+    ar6000_targetStats_event((devt), (pStats), (len))
+
+#define A_WMI_SCANCOMPLETE_EVENT(devt, status)  \
+    ar6000_scanComplete_event((devt), (status))
+
+#ifdef CONFIG_HOST_DSET_SUPPORT
+
+#define A_WMI_DSET_DATA_REQ(devt, access_cookie, offset, length, targ_buf, targ_reply_fn, targ_reply_arg)   \
+    ar6000_dset_data_req((devt), (access_cookie), (offset), (length), (targ_buf), (targ_reply_fn), (targ_reply_arg))
+
+#define A_WMI_DSET_CLOSE(devt, access_cookie)   \
+    ar6000_dset_close((devt), (access_cookie))
+
+#endif
+
+#define A_WMI_DSET_OPEN_REQ(devt, id, targ_handle, targ_reply_fn, targ_reply_arg) \
+    ar6000_dset_open_req((devt), (id), (targ_handle), (targ_reply_fn), (targ_reply_arg))
+
+#define A_WMI_CONNECT_EVENT(devt, channel, bssid, listenInterval, beaconInterval, networkType, beaconIeLen, assocReqLen, assocRespLen, assocInfo) \
+    ar6000_connect_event((devt), (channel), (bssid), (listenInterval), (beaconInterval), (networkType), (beaconIeLen), (assocReqLen), (assocRespLen), (assocInfo))
+
+#define A_WMI_PSPOLL_EVENT(devt, aid)\
+    ar6000_pspoll_event((devt),(aid))
+
+#define A_WMI_DTIMEXPIRY_EVENT(devt)\
+    ar6000_dtimexpiry_event((devt))
+
+#ifdef WAPI_ENABLE
+#define A_WMI_WAPI_REKEY_EVENT(devt, type, mac)\
+    ap_wapi_rekey_event((devt),(type),(mac))
+#endif
+
+#define A_WMI_REGDOMAIN_EVENT(devt, regCode)    \
+    ar6000_regDomain_event((devt), (regCode))
+
+#define A_WMI_NEIGHBORREPORT_EVENT(devt, numAps, info)  \
+    ar6000_neighborReport_event((devt), (numAps), (info))
+
+#define A_WMI_DISCONNECT_EVENT(devt, reason, bssid, assocRespLen, assocInfo, protocolReasonStatus)  \
+    ar6000_disconnect_event((devt), (reason), (bssid), (assocRespLen), (assocInfo), (protocolReasonStatus))
+
+#define A_WMI_TKIP_MICERR_EVENT(devt, keyid, ismcast)   \
+    ar6000_tkip_micerr_event((devt), (keyid), (ismcast))
+
+#define A_WMI_BITRATE_RX(devt, rateKbps)    \
+    ar6000_bitrate_rx((devt), (rateKbps))
+
+#define A_WMI_TXPWR_RX(devt, txPwr) \
+    ar6000_txPwr_rx((devt), (txPwr))
+
+#define A_WMI_READY_EVENT(devt, datap, phyCap, sw_ver, abi_ver) \
+    ar6000_ready_event((devt), (datap), (phyCap), (sw_ver), (abi_ver))
+
+#define A_WMI_DBGLOG_INIT_DONE(ar) \
+    ar6000_dbglog_init_done(ar);
+
+#define A_WMI_RSSI_THRESHOLD_EVENT(devt, newThreshold, rssi)    \
+    ar6000_rssiThreshold_event((devt), (newThreshold), (rssi))
+
+#define A_WMI_REPORT_ERROR_EVENT(devt, errorVal)    \
+    ar6000_reportError_event((devt), (errorVal))
+
+#define A_WMI_ROAM_TABLE_EVENT(devt, pTbl) \
+    ar6000_roam_tbl_event((devt), (pTbl))
+
+#define A_WMI_ROAM_DATA_EVENT(devt, p) \
+    ar6000_roam_data_event((devt), (p))
+
+#define A_WMI_WOW_LIST_EVENT(devt, num_filters, wow_filters)    \
+    ar6000_wow_list_event((devt), (num_filters), (wow_filters))
+
+#define A_WMI_CAC_EVENT(devt, ac, cac_indication, statusCode, tspecSuggestion)  \
+    ar6000_cac_event((devt), (ac), (cac_indication), (statusCode), (tspecSuggestion))
+
+#define A_WMI_CHANNEL_CHANGE_EVENT(devt, oldChannel, newChannel)  \
+    ar6000_channel_change_event((devt), (oldChannel), (newChannel))
+
+#define A_WMI_PMKID_LIST_EVENT(devt, num_pmkid, pmkid_list, bssid_list) \
+    ar6000_pmkid_list_event((devt), (num_pmkid), (pmkid_list), (bssid_list))
+
+#define A_WMI_PEER_EVENT(devt, eventCode, bssid)    \
+    ar6000_peer_event ((devt), (eventCode), (bssid))
+
+#ifdef CONFIG_HOST_GPIO_SUPPORT
+
+#define A_WMI_GPIO_INTR_RX(intr_mask, input_values) \
+    ar6000_gpio_intr_rx((intr_mask), (input_values))
+
+#define A_WMI_GPIO_DATA_RX(reg_id, value) \
+    ar6000_gpio_data_rx((reg_id), (value))
+
+#define A_WMI_GPIO_ACK_RX() \
+    ar6000_gpio_ack_rx()
+
+#endif
+
+#ifdef SEND_EVENT_TO_APP
+
+#define A_WMI_SEND_EVENT_TO_APP(ar, eventId, datap, len) \
+    ar6000_send_event_to_app((ar), (eventId), (datap), (len))
+
+#define A_WMI_SEND_GENERIC_EVENT_TO_APP(ar, eventId, datap, len) \
+    ar6000_send_generic_event_to_app((ar), (eventId), (datap), (len))
+
+#else
+
+#define A_WMI_SEND_EVENT_TO_APP(ar, eventId, datap, len)
+#define A_WMI_SEND_GENERIC_EVENT_TO_APP(ar, eventId, datap, len)
+
+#endif
+
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+#define A_WMI_TCMD_RX_REPORT_EVENT(devt, results, len) \
+    ar6000_tcmd_rx_report_event((devt), (results), (len))
+#endif
+
+#define A_WMI_HBCHALLENGERESP_EVENT(devt, cookie, source)    \
+    ar6000_hbChallengeResp_event((devt), (cookie), (source))
+
+#define A_WMI_TX_RETRY_ERR_EVENT(devt) \
+    ar6000_tx_retry_err_event((devt))
+
+#define A_WMI_SNR_THRESHOLD_EVENT_RX(devt, newThreshold, snr) \
+    ar6000_snrThresholdEvent_rx((devt), (newThreshold), (snr))
+
+#define A_WMI_LQ_THRESHOLD_EVENT_RX(devt, range, lqVal) \
+    ar6000_lqThresholdEvent_rx((devt), (range), (lqVal))
+
+#define A_WMI_RATEMASK_RX(devt, ratemask) \
+    ar6000_ratemask_rx((devt), (ratemask))
+
+#define A_WMI_KEEPALIVE_RX(devt, configured)    \
+    ar6000_keepalive_rx((devt), (configured))
+
+#define A_WMI_BSSINFO_EVENT_RX(ar, datp, len)   \
+    ar6000_bssInfo_event_rx((ar), (datap), (len))
+
+#define A_WMI_DBGLOG_EVENT(ar, dropped, buffer, length) \
+    ar6000_dbglog_event((ar), (dropped), (buffer), (length));
+
+#define A_WMI_STREAM_TX_ACTIVE(devt,trafficClass) \
+    ar6000_indicate_tx_activity((devt),(trafficClass), TRUE)
+
+#define A_WMI_STREAM_TX_INACTIVE(devt,trafficClass) \
+    ar6000_indicate_tx_activity((devt),(trafficClass), FALSE)
+#define A_WMI_Ac2EndpointID(devht, ac)\
+    ar6000_ac2_endpoint_id((devht), (ac))
+
+#define A_WMI_AGGR_RECV_ADDBA_REQ_EVT(devt, cmd)\
+    ar6000_aggr_rcv_addba_req_evt((devt), (cmd))
+#define A_WMI_AGGR_RECV_ADDBA_RESP_EVT(devt, cmd)\
+    ar6000_aggr_rcv_addba_resp_evt((devt), (cmd))
+#define A_WMI_AGGR_RECV_DELBA_REQ_EVT(devt, cmd)\
+    ar6000_aggr_rcv_delba_req_evt((devt), (cmd))
+#define A_WMI_HCI_EVENT_EVT(devt, cmd)\
+    ar6000_hci_event_rcv_evt((devt), (cmd))
+
+#define A_WMI_Endpoint2Ac(devt, ep) \
+    ar6000_endpoint_id2_ac((devt), (ep))
+
+#define A_WMI_BTCOEX_CONFIG_EVENT(devt, evt, len)\
+	ar6000_btcoex_config_event((devt), (evt), (len))
+
+#define A_WMI_BTCOEX_STATS_EVENT(devt, datap, len)\
+	ar6000_btcoex_stats_event((devt), (datap), (len))
+
+/****************************************************************************/
+/****************************************************************************/
+/**                                                                        **/
+/** HTC related hooks                                                      **/
+/**                                                                        **/
+/****************************************************************************/
+/****************************************************************************/
+
+#if defined(CONFIG_TARGET_PROFILE_SUPPORT)
+#define A_WMI_PROF_COUNT_RX(addr, count) prof_count_rx((addr), (count))
+#endif /* CONFIG_TARGET_PROFILE_SUPPORT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/drivers/net/ath6kl/include/a_osapi.h b/drivers/net/ath6kl/include/a_osapi.h
new file mode 100644
index 00000000000..7bdeeea2150
--- /dev/null
+++ b/drivers/net/ath6kl/include/a_osapi.h
@@ -0,0 +1,61 @@
+//------------------------------------------------------------------------------
+// <copyright file="a_osapi.h" company="Atheros">
+//    Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// This file contains the definitions of the basic atheros data types.
+// It is used to map the data types in atheros files to a platform specific
+// type.
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _A_OSAPI_H_
+#define _A_OSAPI_H_
+
+#if defined(__linux__) && !defined(LINUX_EMULATION)
+#include "../os/linux/include/osapi_linux.h"
+#endif
+
+#ifdef UNDER_NWIFI
+#include "../os/windows/include/osapi.h"
+#include "../os/windows/include/netbuf.h"
+#endif
+
+#ifdef ATHR_CE_LEGACY
+#include "../os/windows/include/osapi.h"
+#include "../os/windows/include/netbuf.h"
+#endif
+
+#ifdef REXOS
+#include "../os/rexos/include/common/osapi_rexos.h"
+#endif
+
+#if defined ART_WIN
+#include "../os/win_art/include/osapi_win.h"
+#include "../os/win_art/include/netbuf.h"
+#endif
+
+#ifdef WIN_NWF
+#include <osapi_win.h>
+#endif 
+
+#if defined(THREADX)
+#include "../os/threadx/include/common/osapi_threadx.h"
+#endif 
+
+#endif /* _OSAPI_H_ */
diff --git a/drivers/net/ath6kl/include/a_types.h b/drivers/net/ath6kl/include/a_types.h
new file mode 100644
index 00000000000..18f4cfe4f97
--- /dev/null
+++ b/drivers/net/ath6kl/include/a_types.h
@@ -0,0 +1,58 @@
+//------------------------------------------------------------------------------
+// <copyright file="a_types.h" company="Atheros">
+//    Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// This file contains the definitions of the basic atheros data types.
+// It is used to map the data types in atheros files to a platform specific
+// type.
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _A_TYPES_H_
+#define _A_TYPES_H_
+
+#if defined(__linux__) && !defined(LINUX_EMULATION)
+#include "../os/linux/include/athtypes_linux.h"
+#endif
+
+#ifdef UNDER_NWIFI
+#include "../os/windows/include/athtypes.h"
+#endif
+
+#ifdef ATHR_CE_LEGACY
+#include "../os/windows/include/athtypes.h"
+#endif
+
+#ifdef REXOS
+#include "../os/rexos/include/common/athtypes_rexos.h"
+#endif
+
+#if defined ART_WIN
+#include "../os/win_art/include/athtypes_win.h"
+#endif
+
+#ifdef WIN_NWF
+#include <athtypes_win.h>
+#endif
+
+#ifdef THREADX
+#include "../os/threadx/include/common/athtypes_threadx.h"
+#endif
+
+#endif /* _ATHTYPES_H_ */
diff --git a/drivers/net/ath6kl/include/aggr_recv_api.h b/drivers/net/ath6kl/include/aggr_recv_api.h
new file mode 100644
index 00000000000..0682bb4edcf
--- /dev/null
+++ b/drivers/net/ath6kl/include/aggr_recv_api.h
@@ -0,0 +1,140 @@
+/*
+ *
+ * Copyright (c) 2004-2010 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ * 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+ *
+ */
+
+#ifndef __AGGR_RECV_API_H__
+#define __AGGR_RECV_API_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef void (* RX_CALLBACK)(void * dev, void *osbuf);
+
+typedef void (* ALLOC_NETBUFS)(A_NETBUF_QUEUE_T *q, A_UINT16 num);
+
+/*
+ * aggr_init:
+ * Initialises the data structures, allocates data queues and 
+ * os buffers. Netbuf allocator is the input param, used by the
+ * aggr module for allocation of NETBUFs from driver context.
+ * These NETBUFs are used for AMSDU processing.
+ * Returns the context for the aggr module.
+ */
+void *
+aggr_init(ALLOC_NETBUFS netbuf_allocator);
+
+
+/*
+ * aggr_register_rx_dispatcher:
+ * Registers OS call back function to deliver the
+ * frames to OS. This is generally the topmost layer of
+ * the driver context, after which the frames go to
+ * IP stack via the call back function.
+ * This dispatcher is active only when aggregation is ON.
+ */
+void
+aggr_register_rx_dispatcher(void *cntxt, void * dev,  RX_CALLBACK fn);
+
+
+/*
+ * aggr_process_bar:
+ * When target receives BAR, it communicates to host driver
+ * for modifying window parameters. Target indicates this via the 
+ * event: WMI_ADDBA_REQ_EVENTID. Host will dequeue all frames
+ * up to the indicated sequence number.
+ */
+void
+aggr_process_bar(void *cntxt, A_UINT8 tid, A_UINT16 seq_no);
+
+
+/*
+ * aggr_recv_addba_req_evt:
+ * This event is to initiate/modify the receive side window.
+ * Target will send WMI_ADDBA_REQ_EVENTID event to host - to setup 
+ * recv re-ordering queues. Target will negotiate ADDBA with peer, 
+ * and indicate via this event after succesfully completing the 
+ * negotiation. This happens in two situations:
+ *  1. Initial setup of aggregation
+ *  2. Renegotiation of current recv window.
+ * Window size for re-ordering is limited by target buffer
+ * space, which is reflected in win_sz.
+ * (Re)Start the periodic timer to deliver long standing frames,
+ * in hold_q to OS.
+ */
+void
+aggr_recv_addba_req_evt(void * cntxt, A_UINT8 tid, A_UINT16 seq_no, A_UINT8 win_sz);
+
+
+/*
+ * aggr_recv_delba_req_evt:
+ * Target indicates deletion of a BA window for a tid via the
+ * WMI_DELBA_EVENTID. Host would deliver all the frames in the 
+ * hold_q, reset tid config and disable the periodic timer, if 
+ * aggr is not enabled on any tid.
+ */
+void
+aggr_recv_delba_req_evt(void * cntxt, A_UINT8 tid);
+
+
+
+/*
+ * aggr_process_recv_frm:
+ * Called only for data frames. When aggr is ON for a tid, the buffer 
+ * is always consumed, and osbuf would be NULL. For a non-aggr case,
+ * osbuf is not modified.
+ * AMSDU frames are consumed and are later freed. They are sliced and 
+ * diced to individual frames and dispatched to stack.
+ * After consuming a osbuf(when aggr is ON), a previously registered
+ * callback may be called to deliver frames in order.
+ */
+void
+aggr_process_recv_frm(void *cntxt, A_UINT8 tid, A_UINT16 seq_no, A_BOOL is_amsdu, void **osbuf);
+
+
+/*
+ * aggr_module_destroy:
+ * Frees up all the queues and frames in them. Releases the cntxt to OS.
+ */
+void
+aggr_module_destroy(void *cntxt);
+
+/*
+ * Dumps the aggregation stats 
+ */
+void
+aggr_dump_stats(void *cntxt, PACKET_LOG **log_buf);
+
+/* 
+ * aggr_reset_state -- Called when it is deemed necessary to clear the aggregate
+ *  hold Q state.  Examples include when a Connect event or disconnect event is 
+ *  received. 
+ */
+void
+aggr_reset_state(void *cntxt);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__AGGR_RECV_API_H__ */
diff --git a/drivers/net/ath6kl/include/ar3kconfig.h b/drivers/net/ath6kl/include/ar3kconfig.h
new file mode 100644
index 00000000000..a10788cee46
--- /dev/null
+++ b/drivers/net/ath6kl/include/ar3kconfig.h
@@ -0,0 +1,65 @@
+//------------------------------------------------------------------------------
+// Copyright (c) 2009-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+/* AR3K module configuration APIs for HCI-bridge operation */
+
+#ifndef AR3KCONFIG_H_
+#define AR3KCONFIG_H_
+
+#include <net/bluetooth/bluetooth.h>
+#include <net/bluetooth/hci_core.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define AR3K_CONFIG_FLAG_FORCE_MINBOOT_EXIT         (1 << 0)
+#define AR3K_CONFIG_FLAG_SET_AR3K_BAUD              (1 << 1)
+#define AR3K_CONFIG_FLAG_AR3K_BAUD_CHANGE_DELAY     (1 << 2)
+#define AR3K_CONFIG_FLAG_SET_AR6K_SCALE_STEP        (1 << 3)
+
+
+typedef struct {
+    A_UINT32                 Flags;           /* config flags */
+    void                     *pHCIDev;        /* HCI bridge device     */
+    HCI_TRANSPORT_PROPERTIES *pHCIProps;      /* HCI bridge props      */
+    HIF_DEVICE               *pHIFDevice;     /* HIF layer device      */
+    
+    A_UINT32                 AR3KBaudRate;    /* AR3K operational baud rate */
+    A_UINT16                 AR6KScale;       /* AR6K UART scale value */    
+    A_UINT16                 AR6KStep;        /* AR6K UART step value  */
+    struct hci_dev           *pBtStackHCIDev; /* BT Stack HCI dev */
+    A_UINT32                 PwrMgmtEnabled;  /* TLPM enabled? */  
+    A_UINT16                 IdleTimeout;     /* TLPM idle timeout */
+    A_UINT16                 WakeupTimeout;   /* TLPM wakeup timeout */
+    A_UINT8                  bdaddr[6];       /* Bluetooth device address */
+} AR3K_CONFIG_INFO;
+                                                                                        
+A_STATUS AR3KConfigure(AR3K_CONFIG_INFO *pConfigInfo);
+
+A_STATUS AR3KConfigureExit(void *config);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*AR3KCONFIG_H_*/
diff --git a/drivers/net/ath6kl/include/ar6000_api.h b/drivers/net/ath6kl/include/ar6000_api.h
new file mode 100644
index 00000000000..1e1d92a507e
--- /dev/null
+++ b/drivers/net/ath6kl/include/ar6000_api.h
@@ -0,0 +1,54 @@
+//------------------------------------------------------------------------------
+// <copyright file="ar6000_api.h" company="Atheros">
+//    Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// This file contains the API to access the OS dependent atheros host driver
+// by the WMI or WLAN generic modules.
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _AR6000_API_H_
+#define _AR6000_API_H_
+
+#if defined(__linux__) && !defined(LINUX_EMULATION)
+#include "../os/linux/include/ar6xapi_linux.h"
+#endif
+
+#ifdef UNDER_NWIFI
+#include "../os/windows/include/ar6xapi.h"
+#endif
+
+#ifdef ATHR_CE_LEGACY
+#include "../os/windows/include/ar6xapi.h"
+#endif
+
+#ifdef REXOS
+#include "../os/rexos/include/common/ar6xapi_rexos.h"
+#endif
+
+#if defined ART_WIN
+#include "../os/win_art/include/ar6xapi_win.h"
+#endif
+
+#ifdef WIN_NWF
+#include "../os/windows/include/ar6xapi.h"
+#endif
+
+#endif /* _AR6000_API_H */
+
diff --git a/drivers/net/ath6kl/include/ar6000_diag.h b/drivers/net/ath6kl/include/ar6000_diag.h
new file mode 100644
index 00000000000..b53512e23d3
--- /dev/null
+++ b/drivers/net/ath6kl/include/ar6000_diag.h
@@ -0,0 +1,48 @@
+//------------------------------------------------------------------------------
+// <copyright file="ar6000_diag.h" company="Atheros">
+//    Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+#ifndef AR6000_DIAG_H_
+#define AR6000_DIAG_H_
+
+
+A_STATUS
+ar6000_ReadRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data);
+
+A_STATUS
+ar6000_WriteRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data);
+
+A_STATUS
+ar6000_ReadDataDiag(HIF_DEVICE *hifDevice, A_UINT32 address,
+                    A_UCHAR *data, A_UINT32 length);
+
+A_STATUS
+ar6000_WriteDataDiag(HIF_DEVICE *hifDevice, A_UINT32 address,
+                     A_UCHAR *data, A_UINT32 length);
+
+A_STATUS
+ar6k_ReadTargetRegister(HIF_DEVICE *hifDevice, int regsel, A_UINT32 *regval);
+
+void
+ar6k_FetchTargetRegs(HIF_DEVICE *hifDevice, A_UINT32 *targregs);
+
+#endif /*AR6000_DIAG_H_*/
diff --git a/drivers/net/ath6kl/include/ar6kap_common.h b/drivers/net/ath6kl/include/ar6kap_common.h
new file mode 100644
index 00000000000..9b1b8bfae67
--- /dev/null
+++ b/drivers/net/ath6kl/include/ar6kap_common.h
@@ -0,0 +1,44 @@
+//------------------------------------------------------------------------------
+
+// <copyright file="ar6kap_common.h" company="Atheros">
+//    Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+
+//==============================================================================
+
+// This file contains the definitions of common AP mode data structures.
+//
+// Author(s): ="Atheros"
+//==============================================================================
+
+#ifndef _AR6KAP_COMMON_H_
+#define _AR6KAP_COMMON_H_
+/*
+ * Used with AR6000_XIOCTL_AP_GET_STA_LIST
+ */
+typedef struct {
+    A_UINT8     mac[ATH_MAC_LEN];
+    A_UINT8     aid;
+    A_UINT8     keymgmt;
+    A_UINT8     ucipher;
+    A_UINT8     auth;
+} station_t;
+typedef struct {
+    station_t sta[AP_MAX_NUM_STA];
+} ap_get_sta_t;
+#endif /* _AR6KAP_COMMON_H_ */
diff --git a/drivers/net/ath6kl/include/athbtfilter.h b/drivers/net/ath6kl/include/athbtfilter.h
new file mode 100644
index 00000000000..dbe68bbb727
--- /dev/null
+++ b/drivers/net/ath6kl/include/athbtfilter.h
@@ -0,0 +1,135 @@
+//------------------------------------------------------------------------------
+// <copyright file="athbtfilter.h" company="Atheros">
+//    Copyright (c) 2007-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Public Bluetooth filter APIs
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef ATHBTFILTER_H_
+#define ATHBTFILTER_H_
+
+#define ATH_DEBUG_INFO  (1 << 2)
+#define ATH_DEBUG_INF    ATH_DEBUG_INFO
+
+typedef enum _ATHBT_HCI_CTRL_TYPE {
+    ATHBT_HCI_COMMAND     = 0,
+    ATHBT_HCI_EVENT       = 1,
+} ATHBT_HCI_CTRL_TYPE;
+
+typedef enum _ATHBT_STATE_INDICATION {
+    ATH_BT_NOOP        = 0,
+    ATH_BT_INQUIRY     = 1,
+    ATH_BT_CONNECT     = 2,
+    ATH_BT_SCO         = 3,
+    ATH_BT_ACL         = 4,
+    ATH_BT_A2DP        = 5,
+    ATH_BT_ESCO        = 6,
+    /* new states go here.. */
+
+    ATH_BT_MAX_STATE_INDICATION
+} ATHBT_STATE_INDICATION;
+
+    /* filter function for OUTGOING commands and INCOMMING events */
+typedef void   (*ATHBT_FILTER_CMD_EVENTS_FN)(void *pContext, ATHBT_HCI_CTRL_TYPE Type, unsigned char *pBuffer, int Length);
+
+    /* filter function for OUTGOING data HCI packets */
+typedef void   (*ATHBT_FILTER_DATA_FN)(void *pContext, unsigned char *pBuffer, int Length);
+
+typedef enum _ATHBT_STATE {
+    STATE_OFF  = 0,
+    STATE_ON   = 1,
+    STATE_MAX
+} ATHBT_STATE;
+
+    /* BT state indication (when filter functions are not used) */
+
+typedef void   (*ATHBT_INDICATE_STATE_FN)(void *pContext, ATHBT_STATE_INDICATION Indication, ATHBT_STATE State, unsigned char LMPVersion);
+
+typedef struct _ATHBT_FILTER_INSTANCE {
+#ifdef UNDER_CE
+    WCHAR                       *pWlanAdapterName;  /* filled in by user */
+#else
+    char                        *pWlanAdapterName;  /* filled in by user */
+#endif /* UNDER_CE */
+    int                         FilterEnabled;      /* filtering is enabled */
+    int                         Attached;           /* filter library is attached */
+    void                        *pContext;          /* private context for filter library */
+    ATHBT_FILTER_CMD_EVENTS_FN  pFilterCmdEvents;   /* function ptr to filter a command or event */
+    ATHBT_FILTER_DATA_FN        pFilterAclDataOut;  /* function ptr to filter ACL data out (to radio) */
+    ATHBT_FILTER_DATA_FN        pFilterAclDataIn;   /* function ptr to filter ACL data in (from radio) */
+    ATHBT_INDICATE_STATE_FN     pIndicateState;     /* function ptr to indicate a state */
+} ATH_BT_FILTER_INSTANCE;
+
+
+/* API MACROS */
+
+#define AthBtFilterHciCommand(instance,packet,length)          \
+    if ((instance)->FilterEnabled) {                           \
+        (instance)->pFilterCmdEvents((instance)->pContext,     \
+                                   ATHBT_HCI_COMMAND,          \
+                                   (unsigned char *)(packet),  \
+                                   (length));                  \
+    }
+
+#define AthBtFilterHciEvent(instance,packet,length)            \
+    if ((instance)->FilterEnabled) {                           \
+        (instance)->pFilterCmdEvents((instance)->pContext,     \
+                                   ATHBT_HCI_EVENT,            \
+                                   (unsigned char *)(packet),  \
+                                   (length));                  \
+    }
+
+#define AthBtFilterHciAclDataOut(instance,packet,length)     \
+    if ((instance)->FilterEnabled) {                         \
+        (instance)->pFilterAclDataOut((instance)->pContext,  \
+                                 (unsigned char *)(packet),  \
+                                 (length));                  \
+    }
+
+#define AthBtFilterHciAclDataIn(instance,packet,length)      \
+    if ((instance)->FilterEnabled) {                         \
+        (instance)->pFilterAclDataIn((instance)->pContext,   \
+                                 (unsigned char *)(packet),  \
+                                 (length));                  \
+    }
+        
+/* if filtering is not desired, the application can indicate the state directly using this
+ * macro:
+ */
+#define AthBtIndicateState(instance,indication,state)           \
+    if ((instance)->FilterEnabled) {                            \
+        (instance)->pIndicateState((instance)->pContext,        \
+                                   (indication),                \
+                                   (state),                     \
+                                   0);                          \
+    }
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* API prototypes */
+int     AthBtFilter_Attach(ATH_BT_FILTER_INSTANCE *pInstance, unsigned int flags);
+void    AthBtFilter_Detach(ATH_BT_FILTER_INSTANCE *pInstance);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*ATHBTFILTER_H_*/
diff --git a/drivers/net/ath6kl/include/athendpack.h b/drivers/net/ath6kl/include/athendpack.h
new file mode 100644
index 00000000000..1b940503bb2
--- /dev/null
+++ b/drivers/net/ath6kl/include/athendpack.h
@@ -0,0 +1,52 @@
+//------------------------------------------------------------------------------
+// <copyright file="athendpack.h" company="Atheros">
+//    Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// end compiler-specific structure packing
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#ifdef VXWORKS
+#endif /* VXWORKS */
+
+#if defined(LINUX) || defined(__linux__)
+#endif /* LINUX */
+
+#ifdef QNX
+#endif /* QNX */
+
+#ifdef INTEGRITY
+#include "integrity/athendpack_integrity.h"
+#endif /* INTEGRITY */
+
+#ifdef NUCLEUS
+#endif /* NUCLEUS */
+
+
+#ifdef UNDER_NWIFI
+#include "../os/windows/include/athendpack.h"
+#endif
+
+#ifdef ATHR_CE_LEGACY
+#include "../os/windows/include/athendpack.h"
+#endif /* WINCE */
+
+#ifdef WIN_NWF
+#include <athendpack_win.h>
+#endif 
diff --git a/drivers/net/ath6kl/include/athstartpack.h b/drivers/net/ath6kl/include/athstartpack.h
new file mode 100644
index 00000000000..1c45f666d8a
--- /dev/null
+++ b/drivers/net/ath6kl/include/athstartpack.h
@@ -0,0 +1,55 @@
+//------------------------------------------------------------------------------
+// <copyright file="athstartpack.h" company="Atheros">
+//    Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// start compiler-specific structure packing
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#ifdef VXWORKS
+#endif /* VXWORKS */
+
+#if defined(LINUX) || defined(__linux__)
+#endif /* LINUX */
+
+#ifdef QNX
+#endif /* QNX */
+
+#ifdef INTEGRITY
+#include "integrity/athstartpack_integrity.h"
+#endif /* INTEGRITY */
+
+#ifdef NUCLEUS
+#endif /* NUCLEUS */
+
+#ifdef UNDER_NWIFI
+#include "../os/windows/include/athstartpack.h"
+#endif
+
+#ifdef ATHR_CE_LEGACY
+#include "../os/windows/include/athstartpack.h"
+#endif /* WINCE */
+
+#ifdef WIN_NWF
+#include <athstartpack_win.h>
+#endif
+
+#ifdef THREADX
+#include "../os/threadx/include/common/osapi_threadx.h"
+#endif 
diff --git a/drivers/net/ath6kl/include/bmi.h b/drivers/net/ath6kl/include/bmi.h
new file mode 100644
index 00000000000..27aa98df9c0
--- /dev/null
+++ b/drivers/net/ath6kl/include/bmi.h
@@ -0,0 +1,135 @@
+//------------------------------------------------------------------------------
+// <copyright file="bmi.h" company="Atheros">
+//    Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// BMI declarations and prototypes
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _BMI_H_
+#define _BMI_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* Header files */
+#include "a_config.h"
+#include "athdefs.h"
+#include "a_types.h"
+#include "hif.h"
+#include "a_osapi.h"
+#include "bmi_msg.h"
+
+void
+BMIInit(void);
+
+void
+BMICleanup(void);
+
+A_STATUS
+BMIDone(HIF_DEVICE *device);
+
+A_STATUS
+BMIGetTargetInfo(HIF_DEVICE *device, struct bmi_target_info *targ_info);
+
+A_STATUS
+BMIReadMemory(HIF_DEVICE *device,
+              A_UINT32 address,
+              A_UCHAR *buffer,
+              A_UINT32 length);
+
+A_STATUS
+BMIWriteMemory(HIF_DEVICE *device,
+               A_UINT32 address,
+               A_UCHAR *buffer,
+               A_UINT32 length);
+
+A_STATUS
+BMIExecute(HIF_DEVICE *device,
+           A_UINT32 address,
+           A_UINT32 *param);
+
+A_STATUS
+BMISetAppStart(HIF_DEVICE *device,
+               A_UINT32 address);
+
+A_STATUS
+BMIReadSOCRegister(HIF_DEVICE *device,
+                   A_UINT32 address,
+                   A_UINT32 *param);
+
+A_STATUS
+BMIWriteSOCRegister(HIF_DEVICE *device,
+                    A_UINT32 address,
+                    A_UINT32 param);
+
+A_STATUS
+BMIrompatchInstall(HIF_DEVICE *device,
+                   A_UINT32 ROM_addr,
+                   A_UINT32 RAM_addr,
+                   A_UINT32 nbytes,
+                   A_UINT32 do_activate,
+                   A_UINT32 *patch_id);
+
+A_STATUS
+BMIrompatchUninstall(HIF_DEVICE *device,
+                     A_UINT32 rompatch_id);
+
+A_STATUS
+BMIrompatchActivate(HIF_DEVICE *device,
+                    A_UINT32 rompatch_count,
+                    A_UINT32 *rompatch_list);
+
+A_STATUS
+BMIrompatchDeactivate(HIF_DEVICE *device,
+                      A_UINT32 rompatch_count,
+                      A_UINT32 *rompatch_list);
+
+A_STATUS
+BMILZStreamStart(HIF_DEVICE *device,
+                 A_UINT32 address);
+
+A_STATUS
+BMILZData(HIF_DEVICE *device,
+          A_UCHAR *buffer,
+          A_UINT32 length);
+
+A_STATUS
+BMIFastDownload(HIF_DEVICE *device,
+                A_UINT32 address,
+                A_UCHAR *buffer,
+                A_UINT32 length);
+
+A_STATUS
+BMIRawWrite(HIF_DEVICE *device,
+            A_UCHAR *buffer,
+            A_UINT32 length);
+
+A_STATUS
+BMIRawRead(HIF_DEVICE *device, 
+           A_UCHAR *buffer, 
+           A_UINT32 length, 
+           A_BOOL want_timeout);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _BMI_H_ */
diff --git a/drivers/net/ath6kl/include/common/AR6002/AR6002_regdump.h b/drivers/net/ath6kl/include/common/AR6002/AR6002_regdump.h
new file mode 100644
index 00000000000..e3291cf4dbd
--- /dev/null
+++ b/drivers/net/ath6kl/include/common/AR6002/AR6002_regdump.h
@@ -0,0 +1,60 @@
+//------------------------------------------------------------------------------
+// Copyright (c) 2006-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+#ifndef __AR6002_REGDUMP_H__
+#define __AR6002_REGDUMP_H__
+
+#if !defined(__ASSEMBLER__)
+/*
+ * XTensa CPU state
+ * This must match the state saved by the target exception handler.
+ */
+struct XTensa_exception_frame_s {
+    A_UINT32 xt_pc;
+    A_UINT32 xt_ps;
+    A_UINT32 xt_sar;
+    A_UINT32 xt_vpri;
+    A_UINT32 xt_a2;
+    A_UINT32 xt_a3;
+    A_UINT32 xt_a4;
+    A_UINT32 xt_a5;
+    A_UINT32 xt_exccause;
+    A_UINT32 xt_lcount;
+    A_UINT32 xt_lbeg;
+    A_UINT32 xt_lend;
+
+    A_UINT32 epc1, epc2, epc3, epc4;
+
+    /* Extra info to simplify post-mortem stack walkback */
+#define AR6002_REGDUMP_FRAMES 10
+    struct {
+        A_UINT32 a0;  /* pc */
+        A_UINT32 a1;  /* sp */
+        A_UINT32 a2;
+        A_UINT32 a3;
+    } wb[AR6002_REGDUMP_FRAMES];
+};
+typedef struct XTensa_exception_frame_s CPU_exception_frame_t; 
+#define RD_SIZE sizeof(CPU_exception_frame_t)
+
+#endif
+#endif /* __AR6002_REGDUMP_H__ */
diff --git a/drivers/net/ath6kl/include/common/AR6002/AR6K_version.h b/drivers/net/ath6kl/include/common/AR6002/AR6K_version.h
new file mode 100644
index 00000000000..5407e05d9b0
--- /dev/null
+++ b/drivers/net/ath6kl/include/common/AR6002/AR6K_version.h
@@ -0,0 +1,52 @@
+//------------------------------------------------------------------------------
+// <copyright file="AR6K_version.h" company="Atheros">
+//    Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+#define __VER_MAJOR_ 3
+#define __VER_MINOR_ 0 
+#define __VER_PATCH_ 0
+
+/* The makear6ksdk script (used for release builds) modifies the following line. */
+#define __BUILD_NUMBER_ 233
+
+
+/* Format of the version number. */
+#define VER_MAJOR_BIT_OFFSET        28
+#define VER_MINOR_BIT_OFFSET        24
+#define VER_PATCH_BIT_OFFSET        16
+#define VER_BUILD_NUM_BIT_OFFSET    0
+
+
+/*
+ * The version has the following format:
+ * Bits 28-31: Major version
+ * Bits 24-27: Minor version
+ * Bits 16-23: Patch version
+ * Bits 0-15:  Build number (automatically generated during build process )
+ * E.g. Build 1.1.3.7 would be represented as 0x11030007.
+ *
+ * DO NOT split the following macro into multiple lines as this may confuse the build scripts.
+ */
+#define AR6K_SW_VERSION     ( ( __VER_MAJOR_ << VER_MAJOR_BIT_OFFSET ) + ( __VER_MINOR_ << VER_MINOR_BIT_OFFSET ) + ( __VER_PATCH_ << VER_PATCH_BIT_OFFSET ) + ( __BUILD_NUMBER_ << VER_BUILD_NUM_BIT_OFFSET ) )
+
+/* ABI Version. Reflects the version of binary interface exposed by AR6K target firmware. Needs to be incremented by 1 for any change in the firmware that requires upgrade of the driver on the host side for the change to work correctly */
+#define AR6K_ABI_VERSION        1
diff --git a/drivers/net/ath6kl/include/common/AR6002/addrs.h b/drivers/net/ath6kl/include/common/AR6002/addrs.h
new file mode 100644
index 00000000000..eaaccf4cad7
--- /dev/null
+++ b/drivers/net/ath6kl/include/common/AR6002/addrs.h
@@ -0,0 +1,90 @@
+//------------------------------------------------------------------------------
+// Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+//
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//
+// Author(s): ="Atheros"
+//------------------------------------------------------------------------------
+
+#ifndef __ADDRS_H__
+#define __ADDRS_H__
+
+/*
+ * Special AR6002 Addresses that may be needed by special
+ * applications (e.g. ART) on the Host as well as Target.
+ */
+
+#if defined(AR6002_REV2)
+#define AR6K_RAM_START 0x00500000
+#define TARG_RAM_OFFSET(vaddr) ((A_UINT32)(vaddr) & 0xfffff)
+#define TARG_RAM_SZ (184*1024)
+#define TARG_ROM_SZ (80*1024)
+#endif
+#if defined(AR6002_REV4) || defined(AR6003)
+#define AR6K_RAM_START 0x00540000
+#define TARG_RAM_OFFSET(vaddr) (((A_UINT32)(vaddr) & 0xfffff) - 0x40000)
+#define TARG_RAM_SZ (256*1024)
+#define TARG_ROM_SZ (256*1024)
+#endif
+
+#define AR6002_BOARD_DATA_SZ 768
+#define AR6002_BOARD_EXT_DATA_SZ 0
+#define AR6003_BOARD_DATA_SZ 1024
+#define AR6003_BOARD_EXT_DATA_SZ 768
+
+#define AR6K_RAM_ADDR(byte_offset) (AR6K_RAM_START+(byte_offset))
+#define TARG_RAM_ADDRS(byte_offset) AR6K_RAM_ADDR(byte_offset)
+
+#define AR6K_ROM_START 0x004e0000
+#define TARG_ROM_OFFSET(vaddr) (((A_UINT32)(vaddr) & 0x1fffff) - 0xe0000)
+#define AR6K_ROM_ADDR(byte_offset) (AR6K_ROM_START+(byte_offset))
+#define TARG_ROM_ADDRS(byte_offset) AR6K_ROM_ADDR(byte_offset)
+
+/*
+ * At this ROM address is a pointer to the start of the ROM DataSet Index.
+ * If there are no ROM DataSets, there's a 0 at this address.
+ */
+#define ROM_DATASET_INDEX_ADDR          (TARG_ROM_ADDRS(TARG_ROM_SZ)-8)
+#define ROM_MBIST_CKSUM_ADDR            (TARG_ROM_ADDRS(TARG_ROM_SZ)-4)
+
+/*
+ * The API A_BOARD_DATA_ADDR() is the proper way to get a read pointer to
+ * board data.
+ */
+
+/* Size of Board Data, in bytes */
+#if defined(AR6002_REV4) || defined(AR6003)
+#define BOARD_DATA_SZ AR6003_BOARD_DATA_SZ
+#else
+#define BOARD_DATA_SZ AR6002_BOARD_DATA_SZ
+#endif
+
+
+/*
+ * Constants used by ASM code to access fields of host_interest_s,
+ * which is at a fixed location in RAM.
+ */
+#if defined(AR6002_REV4) || defined(AR6003)
+#define HOST_INTEREST_FLASH_IS_PRESENT_ADDR  (AR6K_RAM_START + 0x60c)
+#else
+#define HOST_INTEREST_FLASH_IS_PRESENT_ADDR  (AR6K_RAM_START + 0x40c)
+#endif
+#define FLASH_IS_PRESENT_TARGADDR       HOST_INTEREST_FLASH_IS_PRESENT_ADDR
+
+#endif /* __ADDRS_H__ */
+
+
+
diff --git a/drivers/net/ath6kl/include/common/AR6002/hw2.0/hw/analog_intf_reg.h b/drivers/net/ath6kl/include/common/AR6002/hw2.0/hw/analog_intf_reg.h
new file mode 100644
index 00000000000..9c82767b6ef
--- /dev/null
+++ b/drivers/net/ath6kl/include/common/AR6002/hw2.0/hw/analog_intf_reg.h
@@ -0,0 +1,64 @@
+#ifndef _ANALOG_INTF_REG_REG_H_
+#define _ANALOG_INTF_REG_REG_H_
+
+#define SW_OVERRIDE_ADDRESS                      0x00000080
+#define SW_OVERRIDE_OFFSET                       0x00000080
+#define SW_OVERRIDE_SUPDATE_DELAY_MSB            1
+#define SW_OVERRIDE_SUPDATE_DELAY_LSB            1
+#define SW_OVERRIDE_SUPDATE_DELAY_MASK           0x00000002
+#define SW_OVERRIDE_SUPDATE_DELAY_GET(x)         (((x) & SW_OVERRIDE_SUPDATE_DELAY_MASK) >> SW_OVERRIDE_SUPDATE_DELAY_LSB)
+#define SW_OVERRIDE_SUPDATE_DELAY_SET(x)         (((x) << SW_OVERRIDE_SUPDATE_DELAY_LSB) & SW_OVERRIDE_SUPDATE_DELAY_MASK)
+#define SW_OVERRIDE_ENABLE_MSB                   0
+#define SW_OVERRIDE_ENABLE_LSB                   0
+#define SW_OVERRIDE_ENABLE_MASK                  0x00000001
+#define SW_OVERRIDE_ENABLE_GET(x)                (((x) & SW_OVERRIDE_ENABLE_MASK) >> SW_OVERRIDE_ENABLE_LSB)
+#define SW_OVERRIDE_ENABLE_SET(x)                (((x) << SW_OVERRIDE_ENABLE_LSB) & SW_OVERRIDE_ENABLE_MASK)
+
+#define SIN_VAL_ADDRESS                          0x00000084
+#define SIN_VAL_OFFSET                           0x00000084
+#define SIN_VAL_SIN_MSB                          0
+#define SIN_VAL_SIN_LSB                          0
+#define SIN_VAL_SIN_MASK                         0x00000001
+#define SIN_VAL_SIN_GET(x)                       (((x) & SIN_VAL_SIN_MASK) >> SIN_VAL_SIN_LSB)
+#define SIN_VAL_SIN_SET(x)                       (((x) << SIN_VAL_SIN_LSB) & SIN_VAL_SIN_MASK)
+
+#define SW_SCLK_ADDRESS                          0x00000088
+#define SW_SCLK_OFFSET                           0x00000088
+#define SW_SCLK_SW_SCLK_MSB                      0
+#define SW_SCLK_SW_SCLK_LSB                      0
+#define SW_SCLK_SW_SCLK_MASK                     0x00000001
+#define SW_SCLK_SW_SCLK_GET(x)                   (((x) & SW_SCLK_SW_SCLK_MASK) >> SW_SCLK_SW_SCLK_LSB)
+#define SW_SCLK_SW_SCLK_SET(x)                   (((x) << SW_SCLK_SW_SCLK_LSB) & SW_SCLK_SW_SCLK_MASK)
+
+#define SW_CNTL_ADDRESS                          0x0000008c
+#define SW_CNTL_OFFSET                           0x0000008c
+#define SW_CNTL_SW_SCAPTURE_MSB                  2
+#define SW_CNTL_SW_SCAPTURE_LSB                  2
+#define SW_CNTL_SW_SCAPTURE_MASK                 0x00000004
+#define SW_CNTL_SW_SCAPTURE_GET(x)               (((x) & SW_CNTL_SW_SCAPTURE_MASK) >> SW_CNTL_SW_SCAPTURE_LSB)
+#define SW_CNTL_SW_SCAPTURE_SET(x)               (((x) << SW_CNTL_SW_SCAPTURE_LSB) & SW_CNTL_SW_SCAPTURE_MASK)
+#define SW_CNTL_SW_SUPDATE_MSB                   1
+#define SW_CNTL_SW_SUPDATE_LSB                   1
+#define SW_CNTL_SW_SUPDATE_MASK                  0x00000002
+#define SW_CNTL_SW_SUPDATE_GET(x)                (((x) & SW_CNTL_SW_SUPDATE_MASK) >> SW_CNTL_SW_SUPDATE_LSB)
+#define SW_CNTL_SW_SUPDATE_SET(x)                (((x) << SW_CNTL_SW_SUPDATE_LSB) & SW_CNTL_SW_SUPDATE_MASK)
+#define SW_CNTL_SW_SOUT_MSB                      0
+#define SW_CNTL_SW_SOUT_LSB                      0
+#define SW_CNTL_SW_SOUT_MASK                     0x00000001
+#define SW_CNTL_SW_SOUT_GET(x)                   (((x) & SW_CNTL_SW_SOUT_MASK) >> SW_CNTL_SW_SOUT_LSB)
+#define SW_CNTL_SW_SOUT_SET(x)                   (((x) << SW_CNTL_SW_SOUT_LSB) & SW_CNTL_SW_SOUT_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct analog_intf_reg_reg_s {
+  unsigned char pad0[128]; /* pad to 0x80 */
+  volatile unsigned int sw_override;
+  volatile unsigned int sin_val;
+  volatile unsigned int sw_sclk;
+  volatile unsigned int sw_cntl;
+} analog_intf_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _ANALOG_INTF_REG_H_ */
diff --git a/drivers/net/ath6kl/include/common/AR6002/hw2.0/hw/analog_reg.h b/drivers/net/ath6kl/include/common/AR6002/hw2.0/hw/analog_reg.h
new file mode 100644
index 00000000000..cf562b86f65
--- /dev/null
+++ b/drivers/net/ath6kl/include/common/AR6002/hw2.0/hw/analog_reg.h
@@ -0,0 +1,1932 @@
+#ifndef _ANALOG_REG_REG_H_
+#define _ANALOG_REG_REG_H_
+
+#define SYNTH_SYNTH1_ADDRESS                     0x00000000
+#define SYNTH_SYNTH1_OFFSET                      0x00000000
+#define SYNTH_SYNTH1_PWD_BIAS_MSB                31
+#define SYNTH_SYNTH1_PWD_BIAS_LSB                31
+#define SYNTH_SYNTH1_PWD_BIAS_MASK               0x80000000
+#define SYNTH_SYNTH1_PWD_BIAS_GET(x)             (((x) & SYNTH_SYNTH1_PWD_BIAS_MASK) >> SYNTH_SYNTH1_PWD_BIAS_LSB)
+#define SYNTH_SYNTH1_PWD_BIAS_SET(x)             (((x) << SYNTH_SYNTH1_PWD_BIAS_LSB) & SYNTH_SYNTH1_PWD_BIAS_MASK)
+#define SYNTH_SYNTH1_PWD_CP_MSB                  30
+#define SYNTH_SYNTH1_PWD_CP_LSB                  30
+#define SYNTH_SYNTH1_PWD_CP_MASK                 0x40000000
+#define SYNTH_SYNTH1_PWD_CP_GET(x)               (((x) & SYNTH_SYNTH1_PWD_CP_MASK) >> SYNTH_SYNTH1_PWD_CP_LSB)
+#define SYNTH_SYNTH1_PWD_CP_SET(x)               (((x) << SYNTH_SYNTH1_PWD_CP_LSB) & SYNTH_SYNTH1_PWD_CP_MASK)
+#define SYNTH_SYNTH1_PWD_VCMON_MSB               29
+#define SYNTH_SYNTH1_PWD_VCMON_LSB               29
+#define SYNTH_SYNTH1_PWD_VCMON_MASK              0x20000000
+#define SYNTH_SYNTH1_PWD_VCMON_GET(x)            (((x) & SYNTH_SYNTH1_PWD_VCMON_MASK) >> SYNTH_SYNTH1_PWD_VCMON_LSB)
+#define SYNTH_SYNTH1_PWD_VCMON_SET(x)            (((x) << SYNTH_SYNTH1_PWD_VCMON_LSB) & SYNTH_SYNTH1_PWD_VCMON_MASK)
+#define SYNTH_SYNTH1_PWD_VCO_MSB                 28
+#define SYNTH_SYNTH1_PWD_VCO_LSB                 28
+#define SYNTH_SYNTH1_PWD_VCO_MASK                0x10000000
+#define SYNTH_SYNTH1_PWD_VCO_GET(x)              (((x) & SYNTH_SYNTH1_PWD_VCO_MASK) >> SYNTH_SYNTH1_PWD_VCO_LSB)
+#define SYNTH_SYNTH1_PWD_VCO_SET(x)              (((x) << SYNTH_SYNTH1_PWD_VCO_LSB) & SYNTH_SYNTH1_PWD_VCO_MASK)
+#define SYNTH_SYNTH1_PWD_PRESC_MSB               27
+#define SYNTH_SYNTH1_PWD_PRESC_LSB               27
+#define SYNTH_SYNTH1_PWD_PRESC_MASK              0x08000000
+#define SYNTH_SYNTH1_PWD_PRESC_GET(x)            (((x) & SYNTH_SYNTH1_PWD_PRESC_MASK) >> SYNTH_SYNTH1_PWD_PRESC_LSB)
+#define SYNTH_SYNTH1_PWD_PRESC_SET(x)            (((x) << SYNTH_SYNTH1_PWD_PRESC_LSB) & SYNTH_SYNTH1_PWD_PRESC_MASK)
+#define SYNTH_SYNTH1_PWD_LODIV_MSB               26
+#define SYNTH_SYNTH1_PWD_LODIV_LSB               26
+#define SYNTH_SYNTH1_PWD_LODIV_MASK              0x04000000
+#define SYNTH_SYNTH1_PWD_LODIV_GET(x)            (((x) & SYNTH_SYNTH1_PWD_LODIV_MASK) >> SYNTH_SYNTH1_PWD_LODIV_LSB)
+#define SYNTH_SYNTH1_PWD_LODIV_SET(x)            (((x) << SYNTH_SYNTH1_PWD_LODIV_LSB) & SYNTH_SYNTH1_PWD_LODIV_MASK)
+#define SYNTH_SYNTH1_PWD_LOMIX_MSB               25
+#define SYNTH_SYNTH1_PWD_LOMIX_LSB               25
+#define SYNTH_SYNTH1_PWD_LOMIX_MASK              0x02000000
+#define SYNTH_SYNTH1_PWD_LOMIX_GET(x)            (((x) & SYNTH_SYNTH1_PWD_LOMIX_MASK) >> SYNTH_SYNTH1_PWD_LOMIX_LSB)
+#define SYNTH_SYNTH1_PWD_LOMIX_SET(x)            (((x) << SYNTH_SYNTH1_PWD_LOMIX_LSB) & SYNTH_SYNTH1_PWD_LOMIX_MASK)
+#define SYNTH_SYNTH1_FORCE_LO_ON_MSB             24
+#define SYNTH_SYNTH1_FORCE_LO_ON_LSB             24
+#define SYNTH_SYNTH1_FORCE_LO_ON_MASK            0x01000000
+#define SYNTH_SYNTH1_FORCE_LO_ON_GET(x)          (((x) & SYNTH_SYNTH1_FORCE_LO_ON_MASK) >> SYNTH_SYNTH1_FORCE_LO_ON_LSB)
+#define SYNTH_SYNTH1_FORCE_LO_ON_SET(x)          (((x) << SYNTH_SYNTH1_FORCE_LO_ON_LSB) & SYNTH_SYNTH1_FORCE_LO_ON_MASK)
+#define SYNTH_SYNTH1_PWD_LOBUF5G_MSB             23
+#define SYNTH_SYNTH1_PWD_LOBUF5G_LSB             23
+#define SYNTH_SYNTH1_PWD_LOBUF5G_MASK            0x00800000
+#define SYNTH_SYNTH1_PWD_LOBUF5G_GET(x)          (((x) & SYNTH_SYNTH1_PWD_LOBUF5G_MASK) >> SYNTH_SYNTH1_PWD_LOBUF5G_LSB)
+#define SYNTH_SYNTH1_PWD_LOBUF5G_SET(x)          (((x) << SYNTH_SYNTH1_PWD_LOBUF5G_LSB) & SYNTH_SYNTH1_PWD_LOBUF5G_MASK)
+#define SYNTH_SYNTH1_VCOREGBYPASS_MSB            22
+#define SYNTH_SYNTH1_VCOREGBYPASS_LSB            22
+#define SYNTH_SYNTH1_VCOREGBYPASS_MASK           0x00400000
+#define SYNTH_SYNTH1_VCOREGBYPASS_GET(x)         (((x) & SYNTH_SYNTH1_VCOREGBYPASS_MASK) >> SYNTH_SYNTH1_VCOREGBYPASS_LSB)
+#define SYNTH_SYNTH1_VCOREGBYPASS_SET(x)         (((x) << SYNTH_SYNTH1_VCOREGBYPASS_LSB) & SYNTH_SYNTH1_VCOREGBYPASS_MASK)
+#define SYNTH_SYNTH1_VCOREGLEVEL_MSB             21
+#define SYNTH_SYNTH1_VCOREGLEVEL_LSB             20
+#define SYNTH_SYNTH1_VCOREGLEVEL_MASK            0x00300000
+#define SYNTH_SYNTH1_VCOREGLEVEL_GET(x)          (((x) & SYNTH_SYNTH1_VCOREGLEVEL_MASK) >> SYNTH_SYNTH1_VCOREGLEVEL_LSB)
+#define SYNTH_SYNTH1_VCOREGLEVEL_SET(x)          (((x) << SYNTH_SYNTH1_VCOREGLEVEL_LSB) & SYNTH_SYNTH1_VCOREGLEVEL_MASK)
+#define SYNTH_SYNTH1_VCOREGBIAS_MSB              19
+#define SYNTH_SYNTH1_VCOREGBIAS_LSB              18
+#define SYNTH_SYNTH1_VCOREGBIAS_MASK             0x000c0000
+#define SYNTH_SYNTH1_VCOREGBIAS_GET(x)           (((x) & SYNTH_SYNTH1_VCOREGBIAS_MASK) >> SYNTH_SYNTH1_VCOREGBIAS_LSB)
+#define SYNTH_SYNTH1_VCOREGBIAS_SET(x)           (((x) << SYNTH_SYNTH1_VCOREGBIAS_LSB) & SYNTH_SYNTH1_VCOREGBIAS_MASK)
+#define SYNTH_SYNTH1_SLIDINGIF_MSB               17
+#define SYNTH_SYNTH1_SLIDINGIF_LSB               17
+#define SYNTH_SYNTH1_SLIDINGIF_MASK              0x00020000
+#define SYNTH_SYNTH1_SLIDINGIF_GET(x)            (((x) & SYNTH_SYNTH1_SLIDINGIF_MASK) >> SYNTH_SYNTH1_SLIDINGIF_LSB)
+#define SYNTH_SYNTH1_SLIDINGIF_SET(x)            (((x) << SYNTH_SYNTH1_SLIDINGIF_LSB) & SYNTH_SYNTH1_SLIDINGIF_MASK)
+#define SYNTH_SYNTH1_SPARE_PWD_MSB               16
+#define SYNTH_SYNTH1_SPARE_PWD_LSB               16
+#define SYNTH_SYNTH1_SPARE_PWD_MASK              0x00010000
+#define SYNTH_SYNTH1_SPARE_PWD_GET(x)            (((x) & SYNTH_SYNTH1_SPARE_PWD_MASK) >> SYNTH_SYNTH1_SPARE_PWD_LSB)
+#define SYNTH_SYNTH1_SPARE_PWD_SET(x)            (((x) << SYNTH_SYNTH1_SPARE_PWD_LSB) & SYNTH_SYNTH1_SPARE_PWD_MASK)
+#define SYNTH_SYNTH1_CON_VDDVCOREG_MSB           15
+#define SYNTH_SYNTH1_CON_VDDVCOREG_LSB           15
+#define SYNTH_SYNTH1_CON_VDDVCOREG_MASK          0x00008000
+#define SYNTH_SYNTH1_CON_VDDVCOREG_GET(x)        (((x) & SYNTH_SYNTH1_CON_VDDVCOREG_MASK) >> SYNTH_SYNTH1_CON_VDDVCOREG_LSB)
+#define SYNTH_SYNTH1_CON_VDDVCOREG_SET(x)        (((x) << SYNTH_SYNTH1_CON_VDDVCOREG_LSB) & SYNTH_SYNTH1_CON_VDDVCOREG_MASK)
+#define SYNTH_SYNTH1_CON_IVCOREG_MSB             14
+#define SYNTH_SYNTH1_CON_IVCOREG_LSB             14
+#define SYNTH_SYNTH1_CON_IVCOREG_MASK            0x00004000
+#define SYNTH_SYNTH1_CON_IVCOREG_GET(x)          (((x) & SYNTH_SYNTH1_CON_IVCOREG_MASK) >> SYNTH_SYNTH1_CON_IVCOREG_LSB)
+#define SYNTH_SYNTH1_CON_IVCOREG_SET(x)          (((x) << SYNTH_SYNTH1_CON_IVCOREG_LSB) & SYNTH_SYNTH1_CON_IVCOREG_MASK)
+#define SYNTH_SYNTH1_CON_IVCOBUF_MSB             13
+#define SYNTH_SYNTH1_CON_IVCOBUF_LSB             13
+#define SYNTH_SYNTH1_CON_IVCOBUF_MASK            0x00002000
+#define SYNTH_SYNTH1_CON_IVCOBUF_GET(x)          (((x) & SYNTH_SYNTH1_CON_IVCOBUF_MASK) >> SYNTH_SYNTH1_CON_IVCOBUF_LSB)
+#define SYNTH_SYNTH1_CON_IVCOBUF_SET(x)          (((x) << SYNTH_SYNTH1_CON_IVCOBUF_LSB) & SYNTH_SYNTH1_CON_IVCOBUF_MASK)
+#define SYNTH_SYNTH1_SEL_VCMONABUS_MSB           12
+#define SYNTH_SYNTH1_SEL_VCMONABUS_LSB           10
+#define SYNTH_SYNTH1_SEL_VCMONABUS_MASK          0x00001c00
+#define SYNTH_SYNTH1_SEL_VCMONABUS_GET(x)        (((x) & SYNTH_SYNTH1_SEL_VCMONABUS_MASK) >> SYNTH_SYNTH1_SEL_VCMONABUS_LSB)
+#define SYNTH_SYNTH1_SEL_VCMONABUS_SET(x)        (((x) << SYNTH_SYNTH1_SEL_VCMONABUS_LSB) & SYNTH_SYNTH1_SEL_VCMONABUS_MASK)
+#define SYNTH_SYNTH1_PWUP_VCOBUF_PD_MSB          9
+#define SYNTH_SYNTH1_PWUP_VCOBUF_PD_LSB          9
+#define SYNTH_SYNTH1_PWUP_VCOBUF_PD_MASK         0x00000200
+#define SYNTH_SYNTH1_PWUP_VCOBUF_PD_GET(x)       (((x) & SYNTH_SYNTH1_PWUP_VCOBUF_PD_MASK) >> SYNTH_SYNTH1_PWUP_VCOBUF_PD_LSB)
+#define SYNTH_SYNTH1_PWUP_VCOBUF_PD_SET(x)       (((x) << SYNTH_SYNTH1_PWUP_VCOBUF_PD_LSB) & SYNTH_SYNTH1_PWUP_VCOBUF_PD_MASK)
+#define SYNTH_SYNTH1_PWUP_LODIV_PD_MSB           8
+#define SYNTH_SYNTH1_PWUP_LODIV_PD_LSB           8
+#define SYNTH_SYNTH1_PWUP_LODIV_PD_MASK          0x00000100
+#define SYNTH_SYNTH1_PWUP_LODIV_PD_GET(x)        (((x) & SYNTH_SYNTH1_PWUP_LODIV_PD_MASK) >> SYNTH_SYNTH1_PWUP_LODIV_PD_LSB)
+#define SYNTH_SYNTH1_PWUP_LODIV_PD_SET(x)        (((x) << SYNTH_SYNTH1_PWUP_LODIV_PD_LSB) & SYNTH_SYNTH1_PWUP_LODIV_PD_MASK)
+#define SYNTH_SYNTH1_PWUP_LOMIX_PD_MSB           7
+#define SYNTH_SYNTH1_PWUP_LOMIX_PD_LSB           7
+#define SYNTH_SYNTH1_PWUP_LOMIX_PD_MASK          0x00000080
+#define SYNTH_SYNTH1_PWUP_LOMIX_PD_GET(x)        (((x) & SYNTH_SYNTH1_PWUP_LOMIX_PD_MASK) >> SYNTH_SYNTH1_PWUP_LOMIX_PD_LSB)
+#define SYNTH_SYNTH1_PWUP_LOMIX_PD_SET(x)        (((x) << SYNTH_SYNTH1_PWUP_LOMIX_PD_LSB) & SYNTH_SYNTH1_PWUP_LOMIX_PD_MASK)
+#define SYNTH_SYNTH1_PWUP_LOBUF5G_PD_MSB         6
+#define SYNTH_SYNTH1_PWUP_LOBUF5G_PD_LSB         6
+#define SYNTH_SYNTH1_PWUP_LOBUF5G_PD_MASK        0x00000040
+#define SYNTH_SYNTH1_PWUP_LOBUF5G_PD_GET(x)      (((x) & SYNTH_SYNTH1_PWUP_LOBUF5G_PD_MASK) >> SYNTH_SYNTH1_PWUP_LOBUF5G_PD_LSB)
+#define SYNTH_SYNTH1_PWUP_LOBUF5G_PD_SET(x)      (((x) << SYNTH_SYNTH1_PWUP_LOBUF5G_PD_LSB) & SYNTH_SYNTH1_PWUP_LOBUF5G_PD_MASK)
+#define SYNTH_SYNTH1_MONITOR_FB_MSB              5
+#define SYNTH_SYNTH1_MONITOR_FB_LSB              5
+#define SYNTH_SYNTH1_MONITOR_FB_MASK             0x00000020
+#define SYNTH_SYNTH1_MONITOR_FB_GET(x)           (((x) & SYNTH_SYNTH1_MONITOR_FB_MASK) >> SYNTH_SYNTH1_MONITOR_FB_LSB)
+#define SYNTH_SYNTH1_MONITOR_FB_SET(x)           (((x) << SYNTH_SYNTH1_MONITOR_FB_LSB) & SYNTH_SYNTH1_MONITOR_FB_MASK)
+#define SYNTH_SYNTH1_MONITOR_REF_MSB             4
+#define SYNTH_SYNTH1_MONITOR_REF_LSB             4
+#define SYNTH_SYNTH1_MONITOR_REF_MASK            0x00000010
+#define SYNTH_SYNTH1_MONITOR_REF_GET(x)          (((x) & SYNTH_SYNTH1_MONITOR_REF_MASK) >> SYNTH_SYNTH1_MONITOR_REF_LSB)
+#define SYNTH_SYNTH1_MONITOR_REF_SET(x)          (((x) << SYNTH_SYNTH1_MONITOR_REF_LSB) & SYNTH_SYNTH1_MONITOR_REF_MASK)
+#define SYNTH_SYNTH1_MONITOR_FB_DIV2_MSB         3
+#define SYNTH_SYNTH1_MONITOR_FB_DIV2_LSB         3
+#define SYNTH_SYNTH1_MONITOR_FB_DIV2_MASK        0x00000008
+#define SYNTH_SYNTH1_MONITOR_FB_DIV2_GET(x)      (((x) & SYNTH_SYNTH1_MONITOR_FB_DIV2_MASK) >> SYNTH_SYNTH1_MONITOR_FB_DIV2_LSB)
+#define SYNTH_SYNTH1_MONITOR_FB_DIV2_SET(x)      (((x) << SYNTH_SYNTH1_MONITOR_FB_DIV2_LSB) & SYNTH_SYNTH1_MONITOR_FB_DIV2_MASK)
+#define SYNTH_SYNTH1_MONITOR_VC2HIGH_MSB         2
+#define SYNTH_SYNTH1_MONITOR_VC2HIGH_LSB         2
+#define SYNTH_SYNTH1_MONITOR_VC2HIGH_MASK        0x00000004
+#define SYNTH_SYNTH1_MONITOR_VC2HIGH_GET(x)      (((x) & SYNTH_SYNTH1_MONITOR_VC2HIGH_MASK) >> SYNTH_SYNTH1_MONITOR_VC2HIGH_LSB)
+#define SYNTH_SYNTH1_MONITOR_VC2HIGH_SET(x)      (((x) << SYNTH_SYNTH1_MONITOR_VC2HIGH_LSB) & SYNTH_SYNTH1_MONITOR_VC2HIGH_MASK)
+#define SYNTH_SYNTH1_MONITOR_VC2LOW_MSB          1
+#define SYNTH_SYNTH1_MONITOR_VC2LOW_LSB          1
+#define SYNTH_SYNTH1_MONITOR_VC2LOW_MASK         0x00000002
+#define SYNTH_SYNTH1_MONITOR_VC2LOW_GET(x)       (((x) & SYNTH_SYNTH1_MONITOR_VC2LOW_MASK) >> SYNTH_SYNTH1_MONITOR_VC2LOW_LSB)
+#define SYNTH_SYNTH1_MONITOR_VC2LOW_SET(x)       (((x) << SYNTH_SYNTH1_MONITOR_VC2LOW_LSB) & SYNTH_SYNTH1_MONITOR_VC2LOW_MASK)
+#define SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_MSB   0
+#define SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_LSB   0
+#define SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_MASK  0x00000001
+#define SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_GET(x) (((x) & SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_MASK) >> SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_LSB)
+#define SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_SET(x) (((x) << SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_LSB) & SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_MASK)
+
+#define SYNTH_SYNTH2_ADDRESS                     0x00000004
+#define SYNTH_SYNTH2_OFFSET                      0x00000004
+#define SYNTH_SYNTH2_VC_CAL_REF_MSB              31
+#define SYNTH_SYNTH2_VC_CAL_REF_LSB              29
+#define SYNTH_SYNTH2_VC_CAL_REF_MASK             0xe0000000
+#define SYNTH_SYNTH2_VC_CAL_REF_GET(x)           (((x) & SYNTH_SYNTH2_VC_CAL_REF_MASK) >> SYNTH_SYNTH2_VC_CAL_REF_LSB)
+#define SYNTH_SYNTH2_VC_CAL_REF_SET(x)           (((x) << SYNTH_SYNTH2_VC_CAL_REF_LSB) & SYNTH_SYNTH2_VC_CAL_REF_MASK)
+#define SYNTH_SYNTH2_VC_HI_REF_MSB               28
+#define SYNTH_SYNTH2_VC_HI_REF_LSB               26
+#define SYNTH_SYNTH2_VC_HI_REF_MASK              0x1c000000
+#define SYNTH_SYNTH2_VC_HI_REF_GET(x)            (((x) & SYNTH_SYNTH2_VC_HI_REF_MASK) >> SYNTH_SYNTH2_VC_HI_REF_LSB)
+#define SYNTH_SYNTH2_VC_HI_REF_SET(x)            (((x) << SYNTH_SYNTH2_VC_HI_REF_LSB) & SYNTH_SYNTH2_VC_HI_REF_MASK)
+#define SYNTH_SYNTH2_VC_MID_REF_MSB              25
+#define SYNTH_SYNTH2_VC_MID_REF_LSB              23
+#define SYNTH_SYNTH2_VC_MID_REF_MASK             0x03800000
+#define SYNTH_SYNTH2_VC_MID_REF_GET(x)           (((x) & SYNTH_SYNTH2_VC_MID_REF_MASK) >> SYNTH_SYNTH2_VC_MID_REF_LSB)
+#define SYNTH_SYNTH2_VC_MID_REF_SET(x)           (((x) << SYNTH_SYNTH2_VC_MID_REF_LSB) & SYNTH_SYNTH2_VC_MID_REF_MASK)
+#define SYNTH_SYNTH2_VC_LOW_REF_MSB              22
+#define SYNTH_SYNTH2_VC_LOW_REF_LSB              20
+#define SYNTH_SYNTH2_VC_LOW_REF_MASK             0x00700000
+#define SYNTH_SYNTH2_VC_LOW_REF_GET(x)           (((x) & SYNTH_SYNTH2_VC_LOW_REF_MASK) >> SYNTH_SYNTH2_VC_LOW_REF_LSB)
+#define SYNTH_SYNTH2_VC_LOW_REF_SET(x)           (((x) << SYNTH_SYNTH2_VC_LOW_REF_LSB) & SYNTH_SYNTH2_VC_LOW_REF_MASK)
+#define SYNTH_SYNTH2_LOOP_3RD_ORDER_R_MSB        19
+#define SYNTH_SYNTH2_LOOP_3RD_ORDER_R_LSB        15
+#define SYNTH_SYNTH2_LOOP_3RD_ORDER_R_MASK       0x000f8000
+#define SYNTH_SYNTH2_LOOP_3RD_ORDER_R_GET(x)     (((x) & SYNTH_SYNTH2_LOOP_3RD_ORDER_R_MASK) >> SYNTH_SYNTH2_LOOP_3RD_ORDER_R_LSB)
+#define SYNTH_SYNTH2_LOOP_3RD_ORDER_R_SET(x)     (((x) << SYNTH_SYNTH2_LOOP_3RD_ORDER_R_LSB) & SYNTH_SYNTH2_LOOP_3RD_ORDER_R_MASK)
+#define SYNTH_SYNTH2_LOOP_CP_MSB                 14
+#define SYNTH_SYNTH2_LOOP_CP_LSB                 10
+#define SYNTH_SYNTH2_LOOP_CP_MASK                0x00007c00
+#define SYNTH_SYNTH2_LOOP_CP_GET(x)              (((x) & SYNTH_SYNTH2_LOOP_CP_MASK) >> SYNTH_SYNTH2_LOOP_CP_LSB)
+#define SYNTH_SYNTH2_LOOP_CP_SET(x)              (((x) << SYNTH_SYNTH2_LOOP_CP_LSB) & SYNTH_SYNTH2_LOOP_CP_MASK)
+#define SYNTH_SYNTH2_LOOP_RS_MSB                 9
+#define SYNTH_SYNTH2_LOOP_RS_LSB                 5
+#define SYNTH_SYNTH2_LOOP_RS_MASK                0x000003e0
+#define SYNTH_SYNTH2_LOOP_RS_GET(x)              (((x) & SYNTH_SYNTH2_LOOP_RS_MASK) >> SYNTH_SYNTH2_LOOP_RS_LSB)
+#define SYNTH_SYNTH2_LOOP_RS_SET(x)              (((x) << SYNTH_SYNTH2_LOOP_RS_LSB) & SYNTH_SYNTH2_LOOP_RS_MASK)
+#define SYNTH_SYNTH2_LOOP_CS_MSB                 4
+#define SYNTH_SYNTH2_LOOP_CS_LSB                 3
+#define SYNTH_SYNTH2_LOOP_CS_MASK                0x00000018
+#define SYNTH_SYNTH2_LOOP_CS_GET(x)              (((x) & SYNTH_SYNTH2_LOOP_CS_MASK) >> SYNTH_SYNTH2_LOOP_CS_LSB)
+#define SYNTH_SYNTH2_LOOP_CS_SET(x)              (((x) << SYNTH_SYNTH2_LOOP_CS_LSB) & SYNTH_SYNTH2_LOOP_CS_MASK)
+#define SYNTH_SYNTH2_SPARE_BITS_MSB              2
+#define SYNTH_SYNTH2_SPARE_BITS_LSB              0
+#define SYNTH_SYNTH2_SPARE_BITS_MASK             0x00000007
+#define SYNTH_SYNTH2_SPARE_BITS_GET(x)           (((x) & SYNTH_SYNTH2_SPARE_BITS_MASK) >> SYNTH_SYNTH2_SPARE_BITS_LSB)
+#define SYNTH_SYNTH2_SPARE_BITS_SET(x)           (((x) << SYNTH_SYNTH2_SPARE_BITS_LSB) & SYNTH_SYNTH2_SPARE_BITS_MASK)
+
+#define SYNTH_SYNTH3_ADDRESS                     0x00000008
+#define SYNTH_SYNTH3_OFFSET                      0x00000008
+#define SYNTH_SYNTH3_DIS_CLK_XTAL_MSB            31
+#define SYNTH_SYNTH3_DIS_CLK_XTAL_LSB            31
+#define SYNTH_SYNTH3_DIS_CLK_XTAL_MASK           0x80000000
+#define SYNTH_SYNTH3_DIS_CLK_XTAL_GET(x)         (((x) & SYNTH_SYNTH3_DIS_CLK_XTAL_MASK) >> SYNTH_SYNTH3_DIS_CLK_XTAL_LSB)
+#define SYNTH_SYNTH3_DIS_CLK_XTAL_SET(x)         (((x) << SYNTH_SYNTH3_DIS_CLK_XTAL_LSB) & SYNTH_SYNTH3_DIS_CLK_XTAL_MASK)
+#define SYNTH_SYNTH3_SEL_CLK_DIV2_MSB            30
+#define SYNTH_SYNTH3_SEL_CLK_DIV2_LSB            30
+#define SYNTH_SYNTH3_SEL_CLK_DIV2_MASK           0x40000000
+#define SYNTH_SYNTH3_SEL_CLK_DIV2_GET(x)         (((x) & SYNTH_SYNTH3_SEL_CLK_DIV2_MASK) >> SYNTH_SYNTH3_SEL_CLK_DIV2_LSB)
+#define SYNTH_SYNTH3_SEL_CLK_DIV2_SET(x)         (((x) << SYNTH_SYNTH3_SEL_CLK_DIV2_LSB) & SYNTH_SYNTH3_SEL_CLK_DIV2_MASK)
+#define SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_MSB       29
+#define SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_LSB       24
+#define SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_MASK      0x3f000000
+#define SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_GET(x)    (((x) & SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_MASK) >> SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_LSB)
+#define SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_SET(x)    (((x) << SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_LSB) & SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_MASK)
+#define SYNTH_SYNTH3_WAIT_PWRUP_MSB              23
+#define SYNTH_SYNTH3_WAIT_PWRUP_LSB              18
+#define SYNTH_SYNTH3_WAIT_PWRUP_MASK             0x00fc0000
+#define SYNTH_SYNTH3_WAIT_PWRUP_GET(x)           (((x) & SYNTH_SYNTH3_WAIT_PWRUP_MASK) >> SYNTH_SYNTH3_WAIT_PWRUP_LSB)
+#define SYNTH_SYNTH3_WAIT_PWRUP_SET(x)           (((x) << SYNTH_SYNTH3_WAIT_PWRUP_LSB) & SYNTH_SYNTH3_WAIT_PWRUP_MASK)
+#define SYNTH_SYNTH3_WAIT_CAL_BIN_MSB            17
+#define SYNTH_SYNTH3_WAIT_CAL_BIN_LSB            12
+#define SYNTH_SYNTH3_WAIT_CAL_BIN_MASK           0x0003f000
+#define SYNTH_SYNTH3_WAIT_CAL_BIN_GET(x)         (((x) & SYNTH_SYNTH3_WAIT_CAL_BIN_MASK) >> SYNTH_SYNTH3_WAIT_CAL_BIN_LSB)
+#define SYNTH_SYNTH3_WAIT_CAL_BIN_SET(x)         (((x) << SYNTH_SYNTH3_WAIT_CAL_BIN_LSB) & SYNTH_SYNTH3_WAIT_CAL_BIN_MASK)
+#define SYNTH_SYNTH3_WAIT_CAL_LIN_MSB            11
+#define SYNTH_SYNTH3_WAIT_CAL_LIN_LSB            6
+#define SYNTH_SYNTH3_WAIT_CAL_LIN_MASK           0x00000fc0
+#define SYNTH_SYNTH3_WAIT_CAL_LIN_GET(x)         (((x) & SYNTH_SYNTH3_WAIT_CAL_LIN_MASK) >> SYNTH_SYNTH3_WAIT_CAL_LIN_LSB)
+#define SYNTH_SYNTH3_WAIT_CAL_LIN_SET(x)         (((x) << SYNTH_SYNTH3_WAIT_CAL_LIN_LSB) & SYNTH_SYNTH3_WAIT_CAL_LIN_MASK)
+#define SYNTH_SYNTH3_WAIT_VC_CHECK_MSB           5
+#define SYNTH_SYNTH3_WAIT_VC_CHECK_LSB           0
+#define SYNTH_SYNTH3_WAIT_VC_CHECK_MASK          0x0000003f
+#define SYNTH_SYNTH3_WAIT_VC_CHECK_GET(x)        (((x) & SYNTH_SYNTH3_WAIT_VC_CHECK_MASK) >> SYNTH_SYNTH3_WAIT_VC_CHECK_LSB)
+#define SYNTH_SYNTH3_WAIT_VC_CHECK_SET(x)        (((x) << SYNTH_SYNTH3_WAIT_VC_CHECK_LSB) & SYNTH_SYNTH3_WAIT_VC_CHECK_MASK)
+
+#define SYNTH_SYNTH4_ADDRESS                     0x0000000c
+#define SYNTH_SYNTH4_OFFSET                      0x0000000c
+#define SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_MSB       31
+#define SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_LSB       31
+#define SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_MASK      0x80000000
+#define SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_GET(x)    (((x) & SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_MASK) >> SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_LSB)
+#define SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_SET(x)    (((x) << SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_LSB) & SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_MASK)
+#define SYNTH_SYNTH4_DIS_LOSTVC_MSB              30
+#define SYNTH_SYNTH4_DIS_LOSTVC_LSB              30
+#define SYNTH_SYNTH4_DIS_LOSTVC_MASK             0x40000000
+#define SYNTH_SYNTH4_DIS_LOSTVC_GET(x)           (((x) & SYNTH_SYNTH4_DIS_LOSTVC_MASK) >> SYNTH_SYNTH4_DIS_LOSTVC_LSB)
+#define SYNTH_SYNTH4_DIS_LOSTVC_SET(x)           (((x) << SYNTH_SYNTH4_DIS_LOSTVC_LSB) & SYNTH_SYNTH4_DIS_LOSTVC_MASK)
+#define SYNTH_SYNTH4_ALWAYS_SHORTR_MSB           29
+#define SYNTH_SYNTH4_ALWAYS_SHORTR_LSB           29
+#define SYNTH_SYNTH4_ALWAYS_SHORTR_MASK          0x20000000
+#define SYNTH_SYNTH4_ALWAYS_SHORTR_GET(x)        (((x) & SYNTH_SYNTH4_ALWAYS_SHORTR_MASK) >> SYNTH_SYNTH4_ALWAYS_SHORTR_LSB)
+#define SYNTH_SYNTH4_ALWAYS_SHORTR_SET(x)        (((x) << SYNTH_SYNTH4_ALWAYS_SHORTR_LSB) & SYNTH_SYNTH4_ALWAYS_SHORTR_MASK)
+#define SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_MSB     28
+#define SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_LSB     28
+#define SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_MASK    0x10000000
+#define SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_GET(x)  (((x) & SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_MASK) >> SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_LSB)
+#define SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_SET(x)  (((x) << SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_LSB) & SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_MASK)
+#define SYNTH_SYNTH4_FORCE_PINVC_MSB             27
+#define SYNTH_SYNTH4_FORCE_PINVC_LSB             27
+#define SYNTH_SYNTH4_FORCE_PINVC_MASK            0x08000000
+#define SYNTH_SYNTH4_FORCE_PINVC_GET(x)          (((x) & SYNTH_SYNTH4_FORCE_PINVC_MASK) >> SYNTH_SYNTH4_FORCE_PINVC_LSB)
+#define SYNTH_SYNTH4_FORCE_PINVC_SET(x)          (((x) << SYNTH_SYNTH4_FORCE_PINVC_LSB) & SYNTH_SYNTH4_FORCE_PINVC_MASK)
+#define SYNTH_SYNTH4_FORCE_VCOCAP_MSB            26
+#define SYNTH_SYNTH4_FORCE_VCOCAP_LSB            26
+#define SYNTH_SYNTH4_FORCE_VCOCAP_MASK           0x04000000
+#define SYNTH_SYNTH4_FORCE_VCOCAP_GET(x)         (((x) & SYNTH_SYNTH4_FORCE_VCOCAP_MASK) >> SYNTH_SYNTH4_FORCE_VCOCAP_LSB)
+#define SYNTH_SYNTH4_FORCE_VCOCAP_SET(x)         (((x) << SYNTH_SYNTH4_FORCE_VCOCAP_LSB) & SYNTH_SYNTH4_FORCE_VCOCAP_MASK)
+#define SYNTH_SYNTH4_VCOCAP_OVR_MSB              25
+#define SYNTH_SYNTH4_VCOCAP_OVR_LSB              18
+#define SYNTH_SYNTH4_VCOCAP_OVR_MASK             0x03fc0000
+#define SYNTH_SYNTH4_VCOCAP_OVR_GET(x)           (((x) & SYNTH_SYNTH4_VCOCAP_OVR_MASK) >> SYNTH_SYNTH4_VCOCAP_OVR_LSB)
+#define SYNTH_SYNTH4_VCOCAP_OVR_SET(x)           (((x) << SYNTH_SYNTH4_VCOCAP_OVR_LSB) & SYNTH_SYNTH4_VCOCAP_OVR_MASK)
+#define SYNTH_SYNTH4_VCOCAPPULLUP_MSB            17
+#define SYNTH_SYNTH4_VCOCAPPULLUP_LSB            17
+#define SYNTH_SYNTH4_VCOCAPPULLUP_MASK           0x00020000
+#define SYNTH_SYNTH4_VCOCAPPULLUP_GET(x)         (((x) & SYNTH_SYNTH4_VCOCAPPULLUP_MASK) >> SYNTH_SYNTH4_VCOCAPPULLUP_LSB)
+#define SYNTH_SYNTH4_VCOCAPPULLUP_SET(x)         (((x) << SYNTH_SYNTH4_VCOCAPPULLUP_LSB) & SYNTH_SYNTH4_VCOCAPPULLUP_MASK)
+#define SYNTH_SYNTH4_REFDIVSEL_MSB               16
+#define SYNTH_SYNTH4_REFDIVSEL_LSB               15
+#define SYNTH_SYNTH4_REFDIVSEL_MASK              0x00018000
+#define SYNTH_SYNTH4_REFDIVSEL_GET(x)            (((x) & SYNTH_SYNTH4_REFDIVSEL_MASK) >> SYNTH_SYNTH4_REFDIVSEL_LSB)
+#define SYNTH_SYNTH4_REFDIVSEL_SET(x)            (((x) << SYNTH_SYNTH4_REFDIVSEL_LSB) & SYNTH_SYNTH4_REFDIVSEL_MASK)
+#define SYNTH_SYNTH4_PFDDELAY_MSB                14
+#define SYNTH_SYNTH4_PFDDELAY_LSB                14
+#define SYNTH_SYNTH4_PFDDELAY_MASK               0x00004000
+#define SYNTH_SYNTH4_PFDDELAY_GET(x)             (((x) & SYNTH_SYNTH4_PFDDELAY_MASK) >> SYNTH_SYNTH4_PFDDELAY_LSB)
+#define SYNTH_SYNTH4_PFDDELAY_SET(x)             (((x) << SYNTH_SYNTH4_PFDDELAY_LSB) & SYNTH_SYNTH4_PFDDELAY_MASK)
+#define SYNTH_SYNTH4_PFD_DISABLE_MSB             13
+#define SYNTH_SYNTH4_PFD_DISABLE_LSB             13
+#define SYNTH_SYNTH4_PFD_DISABLE_MASK            0x00002000
+#define SYNTH_SYNTH4_PFD_DISABLE_GET(x)          (((x) & SYNTH_SYNTH4_PFD_DISABLE_MASK) >> SYNTH_SYNTH4_PFD_DISABLE_LSB)
+#define SYNTH_SYNTH4_PFD_DISABLE_SET(x)          (((x) << SYNTH_SYNTH4_PFD_DISABLE_LSB) & SYNTH_SYNTH4_PFD_DISABLE_MASK)
+#define SYNTH_SYNTH4_PRESCSEL_MSB                12
+#define SYNTH_SYNTH4_PRESCSEL_LSB                11
+#define SYNTH_SYNTH4_PRESCSEL_MASK               0x00001800
+#define SYNTH_SYNTH4_PRESCSEL_GET(x)             (((x) & SYNTH_SYNTH4_PRESCSEL_MASK) >> SYNTH_SYNTH4_PRESCSEL_LSB)
+#define SYNTH_SYNTH4_PRESCSEL_SET(x)             (((x) << SYNTH_SYNTH4_PRESCSEL_LSB) & SYNTH_SYNTH4_PRESCSEL_MASK)
+#define SYNTH_SYNTH4_RESET_PRESC_MSB             10
+#define SYNTH_SYNTH4_RESET_PRESC_LSB             10
+#define SYNTH_SYNTH4_RESET_PRESC_MASK            0x00000400
+#define SYNTH_SYNTH4_RESET_PRESC_GET(x)          (((x) & SYNTH_SYNTH4_RESET_PRESC_MASK) >> SYNTH_SYNTH4_RESET_PRESC_LSB)
+#define SYNTH_SYNTH4_RESET_PRESC_SET(x)          (((x) << SYNTH_SYNTH4_RESET_PRESC_LSB) & SYNTH_SYNTH4_RESET_PRESC_MASK)
+#define SYNTH_SYNTH4_SDM_DISABLE_MSB             9
+#define SYNTH_SYNTH4_SDM_DISABLE_LSB             9
+#define SYNTH_SYNTH4_SDM_DISABLE_MASK            0x00000200
+#define SYNTH_SYNTH4_SDM_DISABLE_GET(x)          (((x) & SYNTH_SYNTH4_SDM_DISABLE_MASK) >> SYNTH_SYNTH4_SDM_DISABLE_LSB)
+#define SYNTH_SYNTH4_SDM_DISABLE_SET(x)          (((x) << SYNTH_SYNTH4_SDM_DISABLE_LSB) & SYNTH_SYNTH4_SDM_DISABLE_MASK)
+#define SYNTH_SYNTH4_SDM_MODE_MSB                8
+#define SYNTH_SYNTH4_SDM_MODE_LSB                8
+#define SYNTH_SYNTH4_SDM_MODE_MASK               0x00000100
+#define SYNTH_SYNTH4_SDM_MODE_GET(x)             (((x) & SYNTH_SYNTH4_SDM_MODE_MASK) >> SYNTH_SYNTH4_SDM_MODE_LSB)
+#define SYNTH_SYNTH4_SDM_MODE_SET(x)             (((x) << SYNTH_SYNTH4_SDM_MODE_LSB) & SYNTH_SYNTH4_SDM_MODE_MASK)
+#define SYNTH_SYNTH4_SDM_DITHER_MSB              7
+#define SYNTH_SYNTH4_SDM_DITHER_LSB              6
+#define SYNTH_SYNTH4_SDM_DITHER_MASK             0x000000c0
+#define SYNTH_SYNTH4_SDM_DITHER_GET(x)           (((x) & SYNTH_SYNTH4_SDM_DITHER_MASK) >> SYNTH_SYNTH4_SDM_DITHER_LSB)
+#define SYNTH_SYNTH4_SDM_DITHER_SET(x)           (((x) << SYNTH_SYNTH4_SDM_DITHER_LSB) & SYNTH_SYNTH4_SDM_DITHER_MASK)
+#define SYNTH_SYNTH4_PSCOUNT_FBSEL_MSB           5
+#define SYNTH_SYNTH4_PSCOUNT_FBSEL_LSB           5
+#define SYNTH_SYNTH4_PSCOUNT_FBSEL_MASK          0x00000020
+#define SYNTH_SYNTH4_PSCOUNT_FBSEL_GET(x)        (((x) & SYNTH_SYNTH4_PSCOUNT_FBSEL_MASK) >> SYNTH_SYNTH4_PSCOUNT_FBSEL_LSB)
+#define SYNTH_SYNTH4_PSCOUNT_FBSEL_SET(x)        (((x) << SYNTH_SYNTH4_PSCOUNT_FBSEL_LSB) & SYNTH_SYNTH4_PSCOUNT_FBSEL_MASK)
+#define SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_MSB        4
+#define SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_LSB        4
+#define SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_MASK       0x00000010
+#define SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_GET(x)     (((x) & SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_MASK) >> SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_LSB)
+#define SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_SET(x)     (((x) << SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_LSB) & SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_MASK)
+#define SYNTH_SYNTH4_SPARE_MISC_MSB              3
+#define SYNTH_SYNTH4_SPARE_MISC_LSB              2
+#define SYNTH_SYNTH4_SPARE_MISC_MASK             0x0000000c
+#define SYNTH_SYNTH4_SPARE_MISC_GET(x)           (((x) & SYNTH_SYNTH4_SPARE_MISC_MASK) >> SYNTH_SYNTH4_SPARE_MISC_LSB)
+#define SYNTH_SYNTH4_SPARE_MISC_SET(x)           (((x) << SYNTH_SYNTH4_SPARE_MISC_LSB) & SYNTH_SYNTH4_SPARE_MISC_MASK)
+#define SYNTH_SYNTH4_LONGSHIFTSEL_MSB            1
+#define SYNTH_SYNTH4_LONGSHIFTSEL_LSB            1
+#define SYNTH_SYNTH4_LONGSHIFTSEL_MASK           0x00000002
+#define SYNTH_SYNTH4_LONGSHIFTSEL_GET(x)         (((x) & SYNTH_SYNTH4_LONGSHIFTSEL_MASK) >> SYNTH_SYNTH4_LONGSHIFTSEL_LSB)
+#define SYNTH_SYNTH4_LONGSHIFTSEL_SET(x)         (((x) << SYNTH_SYNTH4_LONGSHIFTSEL_LSB) & SYNTH_SYNTH4_LONGSHIFTSEL_MASK)
+#define SYNTH_SYNTH4_FORCE_SHIFTREG_MSB          0
+#define SYNTH_SYNTH4_FORCE_SHIFTREG_LSB          0
+#define SYNTH_SYNTH4_FORCE_SHIFTREG_MASK         0x00000001
+#define SYNTH_SYNTH4_FORCE_SHIFTREG_GET(x)       (((x) & SYNTH_SYNTH4_FORCE_SHIFTREG_MASK) >> SYNTH_SYNTH4_FORCE_SHIFTREG_LSB)
+#define SYNTH_SYNTH4_FORCE_SHIFTREG_SET(x)       (((x) << SYNTH_SYNTH4_FORCE_SHIFTREG_LSB) & SYNTH_SYNTH4_FORCE_SHIFTREG_MASK)
+
+#define SYNTH_SYNTH5_ADDRESS                     0x00000010
+#define SYNTH_SYNTH5_OFFSET                      0x00000010
+#define SYNTH_SYNTH5_LOOP_IP0_MSB                31
+#define SYNTH_SYNTH5_LOOP_IP0_LSB                28
+#define SYNTH_SYNTH5_LOOP_IP0_MASK               0xf0000000
+#define SYNTH_SYNTH5_LOOP_IP0_GET(x)             (((x) & SYNTH_SYNTH5_LOOP_IP0_MASK) >> SYNTH_SYNTH5_LOOP_IP0_LSB)
+#define SYNTH_SYNTH5_LOOP_IP0_SET(x)             (((x) << SYNTH_SYNTH5_LOOP_IP0_LSB) & SYNTH_SYNTH5_LOOP_IP0_MASK)
+#define SYNTH_SYNTH5_SLOPE_IP_MSB                27
+#define SYNTH_SYNTH5_SLOPE_IP_LSB                25
+#define SYNTH_SYNTH5_SLOPE_IP_MASK               0x0e000000
+#define SYNTH_SYNTH5_SLOPE_IP_GET(x)             (((x) & SYNTH_SYNTH5_SLOPE_IP_MASK) >> SYNTH_SYNTH5_SLOPE_IP_LSB)
+#define SYNTH_SYNTH5_SLOPE_IP_SET(x)             (((x) << SYNTH_SYNTH5_SLOPE_IP_LSB) & SYNTH_SYNTH5_SLOPE_IP_MASK)
+#define SYNTH_SYNTH5_CPBIAS_MSB                  24
+#define SYNTH_SYNTH5_CPBIAS_LSB                  23
+#define SYNTH_SYNTH5_CPBIAS_MASK                 0x01800000
+#define SYNTH_SYNTH5_CPBIAS_GET(x)               (((x) & SYNTH_SYNTH5_CPBIAS_MASK) >> SYNTH_SYNTH5_CPBIAS_LSB)
+#define SYNTH_SYNTH5_CPBIAS_SET(x)               (((x) << SYNTH_SYNTH5_CPBIAS_LSB) & SYNTH_SYNTH5_CPBIAS_MASK)
+#define SYNTH_SYNTH5_CPSTEERING_EN_MSB           22
+#define SYNTH_SYNTH5_CPSTEERING_EN_LSB           22
+#define SYNTH_SYNTH5_CPSTEERING_EN_MASK          0x00400000
+#define SYNTH_SYNTH5_CPSTEERING_EN_GET(x)        (((x) & SYNTH_SYNTH5_CPSTEERING_EN_MASK) >> SYNTH_SYNTH5_CPSTEERING_EN_LSB)
+#define SYNTH_SYNTH5_CPSTEERING_EN_SET(x)        (((x) << SYNTH_SYNTH5_CPSTEERING_EN_LSB) & SYNTH_SYNTH5_CPSTEERING_EN_MASK)
+#define SYNTH_SYNTH5_CPLOWLK_MSB                 21
+#define SYNTH_SYNTH5_CPLOWLK_LSB                 21
+#define SYNTH_SYNTH5_CPLOWLK_MASK                0x00200000
+#define SYNTH_SYNTH5_CPLOWLK_GET(x)              (((x) & SYNTH_SYNTH5_CPLOWLK_MASK) >> SYNTH_SYNTH5_CPLOWLK_LSB)
+#define SYNTH_SYNTH5_CPLOWLK_SET(x)              (((x) << SYNTH_SYNTH5_CPLOWLK_LSB) & SYNTH_SYNTH5_CPLOWLK_MASK)
+#define SYNTH_SYNTH5_LOOPLEAKCUR_MSB             20
+#define SYNTH_SYNTH5_LOOPLEAKCUR_LSB             17
+#define SYNTH_SYNTH5_LOOPLEAKCUR_MASK            0x001e0000
+#define SYNTH_SYNTH5_LOOPLEAKCUR_GET(x)          (((x) & SYNTH_SYNTH5_LOOPLEAKCUR_MASK) >> SYNTH_SYNTH5_LOOPLEAKCUR_LSB)
+#define SYNTH_SYNTH5_LOOPLEAKCUR_SET(x)          (((x) << SYNTH_SYNTH5_LOOPLEAKCUR_LSB) & SYNTH_SYNTH5_LOOPLEAKCUR_MASK)
+#define SYNTH_SYNTH5_CAPRANGE1_MSB               16
+#define SYNTH_SYNTH5_CAPRANGE1_LSB               13
+#define SYNTH_SYNTH5_CAPRANGE1_MASK              0x0001e000
+#define SYNTH_SYNTH5_CAPRANGE1_GET(x)            (((x) & SYNTH_SYNTH5_CAPRANGE1_MASK) >> SYNTH_SYNTH5_CAPRANGE1_LSB)
+#define SYNTH_SYNTH5_CAPRANGE1_SET(x)            (((x) << SYNTH_SYNTH5_CAPRANGE1_LSB) & SYNTH_SYNTH5_CAPRANGE1_MASK)
+#define SYNTH_SYNTH5_CAPRANGE2_MSB               12
+#define SYNTH_SYNTH5_CAPRANGE2_LSB               9
+#define SYNTH_SYNTH5_CAPRANGE2_MASK              0x00001e00
+#define SYNTH_SYNTH5_CAPRANGE2_GET(x)            (((x) & SYNTH_SYNTH5_CAPRANGE2_MASK) >> SYNTH_SYNTH5_CAPRANGE2_LSB)
+#define SYNTH_SYNTH5_CAPRANGE2_SET(x)            (((x) << SYNTH_SYNTH5_CAPRANGE2_LSB) & SYNTH_SYNTH5_CAPRANGE2_MASK)
+#define SYNTH_SYNTH5_CAPRANGE3_MSB               8
+#define SYNTH_SYNTH5_CAPRANGE3_LSB               5
+#define SYNTH_SYNTH5_CAPRANGE3_MASK              0x000001e0
+#define SYNTH_SYNTH5_CAPRANGE3_GET(x)            (((x) & SYNTH_SYNTH5_CAPRANGE3_MASK) >> SYNTH_SYNTH5_CAPRANGE3_LSB)
+#define SYNTH_SYNTH5_CAPRANGE3_SET(x)            (((x) << SYNTH_SYNTH5_CAPRANGE3_LSB) & SYNTH_SYNTH5_CAPRANGE3_MASK)
+#define SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_MSB       4
+#define SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_LSB       4
+#define SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_MASK      0x00000010
+#define SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_GET(x)    (((x) & SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_MASK) >> SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_LSB)
+#define SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_SET(x)    (((x) << SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_LSB) & SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_MASK)
+#define SYNTH_SYNTH5_LOBUF5GTUNE_OVR_MSB         3
+#define SYNTH_SYNTH5_LOBUF5GTUNE_OVR_LSB         2
+#define SYNTH_SYNTH5_LOBUF5GTUNE_OVR_MASK        0x0000000c
+#define SYNTH_SYNTH5_LOBUF5GTUNE_OVR_GET(x)      (((x) & SYNTH_SYNTH5_LOBUF5GTUNE_OVR_MASK) >> SYNTH_SYNTH5_LOBUF5GTUNE_OVR_LSB)
+#define SYNTH_SYNTH5_LOBUF5GTUNE_OVR_SET(x)      (((x) << SYNTH_SYNTH5_LOBUF5GTUNE_OVR_LSB) & SYNTH_SYNTH5_LOBUF5GTUNE_OVR_MASK)
+#define SYNTH_SYNTH5_SPARE_MSB                   1
+#define SYNTH_SYNTH5_SPARE_LSB                   0
+#define SYNTH_SYNTH5_SPARE_MASK                  0x00000003
+#define SYNTH_SYNTH5_SPARE_GET(x)                (((x) & SYNTH_SYNTH5_SPARE_MASK) >> SYNTH_SYNTH5_SPARE_LSB)
+#define SYNTH_SYNTH5_SPARE_SET(x)                (((x) << SYNTH_SYNTH5_SPARE_LSB) & SYNTH_SYNTH5_SPARE_MASK)
+
+#define SYNTH_SYNTH6_ADDRESS                     0x00000014
+#define SYNTH_SYNTH6_OFFSET                      0x00000014
+#define SYNTH_SYNTH6_IRCP_MSB                    31
+#define SYNTH_SYNTH6_IRCP_LSB                    29
+#define SYNTH_SYNTH6_IRCP_MASK                   0xe0000000
+#define SYNTH_SYNTH6_IRCP_GET(x)                 (((x) & SYNTH_SYNTH6_IRCP_MASK) >> SYNTH_SYNTH6_IRCP_LSB)
+#define SYNTH_SYNTH6_IRCP_SET(x)                 (((x) << SYNTH_SYNTH6_IRCP_LSB) & SYNTH_SYNTH6_IRCP_MASK)
+#define SYNTH_SYNTH6_IRVCMON_MSB                 28
+#define SYNTH_SYNTH6_IRVCMON_LSB                 26
+#define SYNTH_SYNTH6_IRVCMON_MASK                0x1c000000
+#define SYNTH_SYNTH6_IRVCMON_GET(x)              (((x) & SYNTH_SYNTH6_IRVCMON_MASK) >> SYNTH_SYNTH6_IRVCMON_LSB)
+#define SYNTH_SYNTH6_IRVCMON_SET(x)              (((x) << SYNTH_SYNTH6_IRVCMON_LSB) & SYNTH_SYNTH6_IRVCMON_MASK)
+#define SYNTH_SYNTH6_IRSPARE_MSB                 25
+#define SYNTH_SYNTH6_IRSPARE_LSB                 23
+#define SYNTH_SYNTH6_IRSPARE_MASK                0x03800000
+#define SYNTH_SYNTH6_IRSPARE_GET(x)              (((x) & SYNTH_SYNTH6_IRSPARE_MASK) >> SYNTH_SYNTH6_IRSPARE_LSB)
+#define SYNTH_SYNTH6_IRSPARE_SET(x)              (((x) << SYNTH_SYNTH6_IRSPARE_LSB) & SYNTH_SYNTH6_IRSPARE_MASK)
+#define SYNTH_SYNTH6_ICPRESC_MSB                 22
+#define SYNTH_SYNTH6_ICPRESC_LSB                 20
+#define SYNTH_SYNTH6_ICPRESC_MASK                0x00700000
+#define SYNTH_SYNTH6_ICPRESC_GET(x)              (((x) & SYNTH_SYNTH6_ICPRESC_MASK) >> SYNTH_SYNTH6_ICPRESC_LSB)
+#define SYNTH_SYNTH6_ICPRESC_SET(x)              (((x) << SYNTH_SYNTH6_ICPRESC_LSB) & SYNTH_SYNTH6_ICPRESC_MASK)
+#define SYNTH_SYNTH6_ICLODIV_MSB                 19
+#define SYNTH_SYNTH6_ICLODIV_LSB                 17
+#define SYNTH_SYNTH6_ICLODIV_MASK                0x000e0000
+#define SYNTH_SYNTH6_ICLODIV_GET(x)              (((x) & SYNTH_SYNTH6_ICLODIV_MASK) >> SYNTH_SYNTH6_ICLODIV_LSB)
+#define SYNTH_SYNTH6_ICLODIV_SET(x)              (((x) << SYNTH_SYNTH6_ICLODIV_LSB) & SYNTH_SYNTH6_ICLODIV_MASK)
+#define SYNTH_SYNTH6_ICLOMIX_MSB                 16
+#define SYNTH_SYNTH6_ICLOMIX_LSB                 14
+#define SYNTH_SYNTH6_ICLOMIX_MASK                0x0001c000
+#define SYNTH_SYNTH6_ICLOMIX_GET(x)              (((x) & SYNTH_SYNTH6_ICLOMIX_MASK) >> SYNTH_SYNTH6_ICLOMIX_LSB)
+#define SYNTH_SYNTH6_ICLOMIX_SET(x)              (((x) << SYNTH_SYNTH6_ICLOMIX_LSB) & SYNTH_SYNTH6_ICLOMIX_MASK)
+#define SYNTH_SYNTH6_ICSPAREA_MSB                13
+#define SYNTH_SYNTH6_ICSPAREA_LSB                11
+#define SYNTH_SYNTH6_ICSPAREA_MASK               0x00003800
+#define SYNTH_SYNTH6_ICSPAREA_GET(x)             (((x) & SYNTH_SYNTH6_ICSPAREA_MASK) >> SYNTH_SYNTH6_ICSPAREA_LSB)
+#define SYNTH_SYNTH6_ICSPAREA_SET(x)             (((x) << SYNTH_SYNTH6_ICSPAREA_LSB) & SYNTH_SYNTH6_ICSPAREA_MASK)
+#define SYNTH_SYNTH6_ICSPAREB_MSB                10
+#define SYNTH_SYNTH6_ICSPAREB_LSB                8
+#define SYNTH_SYNTH6_ICSPAREB_MASK               0x00000700
+#define SYNTH_SYNTH6_ICSPAREB_GET(x)             (((x) & SYNTH_SYNTH6_ICSPAREB_MASK) >> SYNTH_SYNTH6_ICSPAREB_LSB)
+#define SYNTH_SYNTH6_ICSPAREB_SET(x)             (((x) << SYNTH_SYNTH6_ICSPAREB_LSB) & SYNTH_SYNTH6_ICSPAREB_MASK)
+#define SYNTH_SYNTH6_ICVCO_MSB                   7
+#define SYNTH_SYNTH6_ICVCO_LSB                   5
+#define SYNTH_SYNTH6_ICVCO_MASK                  0x000000e0
+#define SYNTH_SYNTH6_ICVCO_GET(x)                (((x) & SYNTH_SYNTH6_ICVCO_MASK) >> SYNTH_SYNTH6_ICVCO_LSB)
+#define SYNTH_SYNTH6_ICVCO_SET(x)                (((x) << SYNTH_SYNTH6_ICVCO_LSB) & SYNTH_SYNTH6_ICVCO_MASK)
+#define SYNTH_SYNTH6_VCOBUFBIAS_MSB              4
+#define SYNTH_SYNTH6_VCOBUFBIAS_LSB              3
+#define SYNTH_SYNTH6_VCOBUFBIAS_MASK             0x00000018
+#define SYNTH_SYNTH6_VCOBUFBIAS_GET(x)           (((x) & SYNTH_SYNTH6_VCOBUFBIAS_MASK) >> SYNTH_SYNTH6_VCOBUFBIAS_LSB)
+#define SYNTH_SYNTH6_VCOBUFBIAS_SET(x)           (((x) << SYNTH_SYNTH6_VCOBUFBIAS_LSB) & SYNTH_SYNTH6_VCOBUFBIAS_MASK)
+#define SYNTH_SYNTH6_SPARE_BIAS_MSB              2
+#define SYNTH_SYNTH6_SPARE_BIAS_LSB              0
+#define SYNTH_SYNTH6_SPARE_BIAS_MASK             0x00000007
+#define SYNTH_SYNTH6_SPARE_BIAS_GET(x)           (((x) & SYNTH_SYNTH6_SPARE_BIAS_MASK) >> SYNTH_SYNTH6_SPARE_BIAS_LSB)
+#define SYNTH_SYNTH6_SPARE_BIAS_SET(x)           (((x) << SYNTH_SYNTH6_SPARE_BIAS_LSB) & SYNTH_SYNTH6_SPARE_BIAS_MASK)
+
+#define SYNTH_SYNTH7_ADDRESS                     0x00000018
+#define SYNTH_SYNTH7_OFFSET                      0x00000018
+#define SYNTH_SYNTH7_SYNTH_ON_MSB                31
+#define SYNTH_SYNTH7_SYNTH_ON_LSB                31
+#define SYNTH_SYNTH7_SYNTH_ON_MASK               0x80000000
+#define SYNTH_SYNTH7_SYNTH_ON_GET(x)             (((x) & SYNTH_SYNTH7_SYNTH_ON_MASK) >> SYNTH_SYNTH7_SYNTH_ON_LSB)
+#define SYNTH_SYNTH7_SYNTH_ON_SET(x)             (((x) << SYNTH_SYNTH7_SYNTH_ON_LSB) & SYNTH_SYNTH7_SYNTH_ON_MASK)
+#define SYNTH_SYNTH7_SYNTH_SM_STATE_MSB          30
+#define SYNTH_SYNTH7_SYNTH_SM_STATE_LSB          27
+#define SYNTH_SYNTH7_SYNTH_SM_STATE_MASK         0x78000000
+#define SYNTH_SYNTH7_SYNTH_SM_STATE_GET(x)       (((x) & SYNTH_SYNTH7_SYNTH_SM_STATE_MASK) >> SYNTH_SYNTH7_SYNTH_SM_STATE_LSB)
+#define SYNTH_SYNTH7_SYNTH_SM_STATE_SET(x)       (((x) << SYNTH_SYNTH7_SYNTH_SM_STATE_LSB) & SYNTH_SYNTH7_SYNTH_SM_STATE_MASK)
+#define SYNTH_SYNTH7_CAP_SEARCH_MSB              26
+#define SYNTH_SYNTH7_CAP_SEARCH_LSB              26
+#define SYNTH_SYNTH7_CAP_SEARCH_MASK             0x04000000
+#define SYNTH_SYNTH7_CAP_SEARCH_GET(x)           (((x) & SYNTH_SYNTH7_CAP_SEARCH_MASK) >> SYNTH_SYNTH7_CAP_SEARCH_LSB)
+#define SYNTH_SYNTH7_CAP_SEARCH_SET(x)           (((x) << SYNTH_SYNTH7_CAP_SEARCH_LSB) & SYNTH_SYNTH7_CAP_SEARCH_MASK)
+#define SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_MSB        25
+#define SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_LSB        25
+#define SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_MASK       0x02000000
+#define SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_GET(x)     (((x) & SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_MASK) >> SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_LSB)
+#define SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_SET(x)     (((x) << SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_LSB) & SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_MASK)
+#define SYNTH_SYNTH7_PIN_VC_MSB                  24
+#define SYNTH_SYNTH7_PIN_VC_LSB                  24
+#define SYNTH_SYNTH7_PIN_VC_MASK                 0x01000000
+#define SYNTH_SYNTH7_PIN_VC_GET(x)               (((x) & SYNTH_SYNTH7_PIN_VC_MASK) >> SYNTH_SYNTH7_PIN_VC_LSB)
+#define SYNTH_SYNTH7_PIN_VC_SET(x)               (((x) << SYNTH_SYNTH7_PIN_VC_LSB) & SYNTH_SYNTH7_PIN_VC_MASK)
+#define SYNTH_SYNTH7_VCO_CAP_ST_MSB              23
+#define SYNTH_SYNTH7_VCO_CAP_ST_LSB              16
+#define SYNTH_SYNTH7_VCO_CAP_ST_MASK             0x00ff0000
+#define SYNTH_SYNTH7_VCO_CAP_ST_GET(x)           (((x) & SYNTH_SYNTH7_VCO_CAP_ST_MASK) >> SYNTH_SYNTH7_VCO_CAP_ST_LSB)
+#define SYNTH_SYNTH7_VCO_CAP_ST_SET(x)           (((x) << SYNTH_SYNTH7_VCO_CAP_ST_LSB) & SYNTH_SYNTH7_VCO_CAP_ST_MASK)
+#define SYNTH_SYNTH7_SHORT_R_MSB                 15
+#define SYNTH_SYNTH7_SHORT_R_LSB                 15
+#define SYNTH_SYNTH7_SHORT_R_MASK                0x00008000
+#define SYNTH_SYNTH7_SHORT_R_GET(x)              (((x) & SYNTH_SYNTH7_SHORT_R_MASK) >> SYNTH_SYNTH7_SHORT_R_LSB)
+#define SYNTH_SYNTH7_SHORT_R_SET(x)              (((x) << SYNTH_SYNTH7_SHORT_R_LSB) & SYNTH_SYNTH7_SHORT_R_MASK)
+#define SYNTH_SYNTH7_RESET_RFD_MSB               14
+#define SYNTH_SYNTH7_RESET_RFD_LSB               14
+#define SYNTH_SYNTH7_RESET_RFD_MASK              0x00004000
+#define SYNTH_SYNTH7_RESET_RFD_GET(x)            (((x) & SYNTH_SYNTH7_RESET_RFD_MASK) >> SYNTH_SYNTH7_RESET_RFD_LSB)
+#define SYNTH_SYNTH7_RESET_RFD_SET(x)            (((x) << SYNTH_SYNTH7_RESET_RFD_LSB) & SYNTH_SYNTH7_RESET_RFD_MASK)
+#define SYNTH_SYNTH7_RESET_PFD_MSB               13
+#define SYNTH_SYNTH7_RESET_PFD_LSB               13
+#define SYNTH_SYNTH7_RESET_PFD_MASK              0x00002000
+#define SYNTH_SYNTH7_RESET_PFD_GET(x)            (((x) & SYNTH_SYNTH7_RESET_PFD_MASK) >> SYNTH_SYNTH7_RESET_PFD_LSB)
+#define SYNTH_SYNTH7_RESET_PFD_SET(x)            (((x) << SYNTH_SYNTH7_RESET_PFD_LSB) & SYNTH_SYNTH7_RESET_PFD_MASK)
+#define SYNTH_SYNTH7_RESET_PSCOUNTERS_MSB        12
+#define SYNTH_SYNTH7_RESET_PSCOUNTERS_LSB        12
+#define SYNTH_SYNTH7_RESET_PSCOUNTERS_MASK       0x00001000
+#define SYNTH_SYNTH7_RESET_PSCOUNTERS_GET(x)     (((x) & SYNTH_SYNTH7_RESET_PSCOUNTERS_MASK) >> SYNTH_SYNTH7_RESET_PSCOUNTERS_LSB)
+#define SYNTH_SYNTH7_RESET_PSCOUNTERS_SET(x)     (((x) << SYNTH_SYNTH7_RESET_PSCOUNTERS_LSB) & SYNTH_SYNTH7_RESET_PSCOUNTERS_MASK)
+#define SYNTH_SYNTH7_RESET_SDM_B_MSB             11
+#define SYNTH_SYNTH7_RESET_SDM_B_LSB             11
+#define SYNTH_SYNTH7_RESET_SDM_B_MASK            0x00000800
+#define SYNTH_SYNTH7_RESET_SDM_B_GET(x)          (((x) & SYNTH_SYNTH7_RESET_SDM_B_MASK) >> SYNTH_SYNTH7_RESET_SDM_B_LSB)
+#define SYNTH_SYNTH7_RESET_SDM_B_SET(x)          (((x) << SYNTH_SYNTH7_RESET_SDM_B_LSB) & SYNTH_SYNTH7_RESET_SDM_B_MASK)
+#define SYNTH_SYNTH7_VC2HIGH_MSB                 10
+#define SYNTH_SYNTH7_VC2HIGH_LSB                 10
+#define SYNTH_SYNTH7_VC2HIGH_MASK                0x00000400
+#define SYNTH_SYNTH7_VC2HIGH_GET(x)              (((x) & SYNTH_SYNTH7_VC2HIGH_MASK) >> SYNTH_SYNTH7_VC2HIGH_LSB)
+#define SYNTH_SYNTH7_VC2HIGH_SET(x)              (((x) << SYNTH_SYNTH7_VC2HIGH_LSB) & SYNTH_SYNTH7_VC2HIGH_MASK)
+#define SYNTH_SYNTH7_VC2LOW_MSB                  9
+#define SYNTH_SYNTH7_VC2LOW_LSB                  9
+#define SYNTH_SYNTH7_VC2LOW_MASK                 0x00000200
+#define SYNTH_SYNTH7_VC2LOW_GET(x)               (((x) & SYNTH_SYNTH7_VC2LOW_MASK) >> SYNTH_SYNTH7_VC2LOW_LSB)
+#define SYNTH_SYNTH7_VC2LOW_SET(x)               (((x) << SYNTH_SYNTH7_VC2LOW_LSB) & SYNTH_SYNTH7_VC2LOW_MASK)
+#define SYNTH_SYNTH7_LOOP_IP_MSB                 8
+#define SYNTH_SYNTH7_LOOP_IP_LSB                 5
+#define SYNTH_SYNTH7_LOOP_IP_MASK                0x000001e0
+#define SYNTH_SYNTH7_LOOP_IP_GET(x)              (((x) & SYNTH_SYNTH7_LOOP_IP_MASK) >> SYNTH_SYNTH7_LOOP_IP_LSB)
+#define SYNTH_SYNTH7_LOOP_IP_SET(x)              (((x) << SYNTH_SYNTH7_LOOP_IP_LSB) & SYNTH_SYNTH7_LOOP_IP_MASK)
+#define SYNTH_SYNTH7_LOBUF5GTUNE_MSB             4
+#define SYNTH_SYNTH7_LOBUF5GTUNE_LSB             3
+#define SYNTH_SYNTH7_LOBUF5GTUNE_MASK            0x00000018
+#define SYNTH_SYNTH7_LOBUF5GTUNE_GET(x)          (((x) & SYNTH_SYNTH7_LOBUF5GTUNE_MASK) >> SYNTH_SYNTH7_LOBUF5GTUNE_LSB)
+#define SYNTH_SYNTH7_LOBUF5GTUNE_SET(x)          (((x) << SYNTH_SYNTH7_LOBUF5GTUNE_LSB) & SYNTH_SYNTH7_LOBUF5GTUNE_MASK)
+#define SYNTH_SYNTH7_SPARE_READ_MSB              2
+#define SYNTH_SYNTH7_SPARE_READ_LSB              0
+#define SYNTH_SYNTH7_SPARE_READ_MASK             0x00000007
+#define SYNTH_SYNTH7_SPARE_READ_GET(x)           (((x) & SYNTH_SYNTH7_SPARE_READ_MASK) >> SYNTH_SYNTH7_SPARE_READ_LSB)
+#define SYNTH_SYNTH7_SPARE_READ_SET(x)           (((x) << SYNTH_SYNTH7_SPARE_READ_LSB) & SYNTH_SYNTH7_SPARE_READ_MASK)
+
+#define SYNTH_SYNTH8_ADDRESS                     0x0000001c
+#define SYNTH_SYNTH8_OFFSET                      0x0000001c
+#define SYNTH_SYNTH8_LOADSYNTHCHANNEL_MSB        31
+#define SYNTH_SYNTH8_LOADSYNTHCHANNEL_LSB        31
+#define SYNTH_SYNTH8_LOADSYNTHCHANNEL_MASK       0x80000000
+#define SYNTH_SYNTH8_LOADSYNTHCHANNEL_GET(x)     (((x) & SYNTH_SYNTH8_LOADSYNTHCHANNEL_MASK) >> SYNTH_SYNTH8_LOADSYNTHCHANNEL_LSB)
+#define SYNTH_SYNTH8_LOADSYNTHCHANNEL_SET(x)     (((x) << SYNTH_SYNTH8_LOADSYNTHCHANNEL_LSB) & SYNTH_SYNTH8_LOADSYNTHCHANNEL_MASK)
+#define SYNTH_SYNTH8_FRACMODE_MSB                30
+#define SYNTH_SYNTH8_FRACMODE_LSB                30
+#define SYNTH_SYNTH8_FRACMODE_MASK               0x40000000
+#define SYNTH_SYNTH8_FRACMODE_GET(x)             (((x) & SYNTH_SYNTH8_FRACMODE_MASK) >> SYNTH_SYNTH8_FRACMODE_LSB)
+#define SYNTH_SYNTH8_FRACMODE_SET(x)             (((x) << SYNTH_SYNTH8_FRACMODE_LSB) & SYNTH_SYNTH8_FRACMODE_MASK)
+#define SYNTH_SYNTH8_AMODEREFSEL_MSB             29
+#define SYNTH_SYNTH8_AMODEREFSEL_LSB             28
+#define SYNTH_SYNTH8_AMODEREFSEL_MASK            0x30000000
+#define SYNTH_SYNTH8_AMODEREFSEL_GET(x)          (((x) & SYNTH_SYNTH8_AMODEREFSEL_MASK) >> SYNTH_SYNTH8_AMODEREFSEL_LSB)
+#define SYNTH_SYNTH8_AMODEREFSEL_SET(x)          (((x) << SYNTH_SYNTH8_AMODEREFSEL_LSB) & SYNTH_SYNTH8_AMODEREFSEL_MASK)
+#define SYNTH_SYNTH8_SPARE_MSB                   27
+#define SYNTH_SYNTH8_SPARE_LSB                   27
+#define SYNTH_SYNTH8_SPARE_MASK                  0x08000000
+#define SYNTH_SYNTH8_SPARE_GET(x)                (((x) & SYNTH_SYNTH8_SPARE_MASK) >> SYNTH_SYNTH8_SPARE_LSB)
+#define SYNTH_SYNTH8_SPARE_SET(x)                (((x) << SYNTH_SYNTH8_SPARE_LSB) & SYNTH_SYNTH8_SPARE_MASK)
+#define SYNTH_SYNTH8_CHANSEL_MSB                 26
+#define SYNTH_SYNTH8_CHANSEL_LSB                 18
+#define SYNTH_SYNTH8_CHANSEL_MASK                0x07fc0000
+#define SYNTH_SYNTH8_CHANSEL_GET(x)              (((x) & SYNTH_SYNTH8_CHANSEL_MASK) >> SYNTH_SYNTH8_CHANSEL_LSB)
+#define SYNTH_SYNTH8_CHANSEL_SET(x)              (((x) << SYNTH_SYNTH8_CHANSEL_LSB) & SYNTH_SYNTH8_CHANSEL_MASK)
+#define SYNTH_SYNTH8_CHANFRAC_MSB                17
+#define SYNTH_SYNTH8_CHANFRAC_LSB                1
+#define SYNTH_SYNTH8_CHANFRAC_MASK               0x0003fffe
+#define SYNTH_SYNTH8_CHANFRAC_GET(x)             (((x) & SYNTH_SYNTH8_CHANFRAC_MASK) >> SYNTH_SYNTH8_CHANFRAC_LSB)
+#define SYNTH_SYNTH8_CHANFRAC_SET(x)             (((x) << SYNTH_SYNTH8_CHANFRAC_LSB) & SYNTH_SYNTH8_CHANFRAC_MASK)
+#define SYNTH_SYNTH8_FORCE_FRACLSB_MSB           0
+#define SYNTH_SYNTH8_FORCE_FRACLSB_LSB           0
+#define SYNTH_SYNTH8_FORCE_FRACLSB_MASK          0x00000001
+#define SYNTH_SYNTH8_FORCE_FRACLSB_GET(x)        (((x) & SYNTH_SYNTH8_FORCE_FRACLSB_MASK) >> SYNTH_SYNTH8_FORCE_FRACLSB_LSB)
+#define SYNTH_SYNTH8_FORCE_FRACLSB_SET(x)        (((x) << SYNTH_SYNTH8_FORCE_FRACLSB_LSB) & SYNTH_SYNTH8_FORCE_FRACLSB_MASK)
+
+#define RF5G_RF5G1_ADDRESS                       0x00000020
+#define RF5G_RF5G1_OFFSET                        0x00000020
+#define RF5G_RF5G1_PDTXLO5_MSB                   31
+#define RF5G_RF5G1_PDTXLO5_LSB                   31
+#define RF5G_RF5G1_PDTXLO5_MASK                  0x80000000
+#define RF5G_RF5G1_PDTXLO5_GET(x)                (((x) & RF5G_RF5G1_PDTXLO5_MASK) >> RF5G_RF5G1_PDTXLO5_LSB)
+#define RF5G_RF5G1_PDTXLO5_SET(x)                (((x) << RF5G_RF5G1_PDTXLO5_LSB) & RF5G_RF5G1_PDTXLO5_MASK)
+#define RF5G_RF5G1_PDTXMIX5_MSB                  30
+#define RF5G_RF5G1_PDTXMIX5_LSB                  30
+#define RF5G_RF5G1_PDTXMIX5_MASK                 0x40000000
+#define RF5G_RF5G1_PDTXMIX5_GET(x)               (((x) & RF5G_RF5G1_PDTXMIX5_MASK) >> RF5G_RF5G1_PDTXMIX5_LSB)
+#define RF5G_RF5G1_PDTXMIX5_SET(x)               (((x) << RF5G_RF5G1_PDTXMIX5_LSB) & RF5G_RF5G1_PDTXMIX5_MASK)
+#define RF5G_RF5G1_PDTXBUF5_MSB                  29
+#define RF5G_RF5G1_PDTXBUF5_LSB                  29
+#define RF5G_RF5G1_PDTXBUF5_MASK                 0x20000000
+#define RF5G_RF5G1_PDTXBUF5_GET(x)               (((x) & RF5G_RF5G1_PDTXBUF5_MASK) >> RF5G_RF5G1_PDTXBUF5_LSB)
+#define RF5G_RF5G1_PDTXBUF5_SET(x)               (((x) << RF5G_RF5G1_PDTXBUF5_LSB) & RF5G_RF5G1_PDTXBUF5_MASK)
+#define RF5G_RF5G1_PDPADRV5_MSB                  28
+#define RF5G_RF5G1_PDPADRV5_LSB                  28
+#define RF5G_RF5G1_PDPADRV5_MASK                 0x10000000
+#define RF5G_RF5G1_PDPADRV5_GET(x)               (((x) & RF5G_RF5G1_PDPADRV5_MASK) >> RF5G_RF5G1_PDPADRV5_LSB)
+#define RF5G_RF5G1_PDPADRV5_SET(x)               (((x) << RF5G_RF5G1_PDPADRV5_LSB) & RF5G_RF5G1_PDPADRV5_MASK)
+#define RF5G_RF5G1_PDPAOUT5_MSB                  27
+#define RF5G_RF5G1_PDPAOUT5_LSB                  27
+#define RF5G_RF5G1_PDPAOUT5_MASK                 0x08000000
+#define RF5G_RF5G1_PDPAOUT5_GET(x)               (((x) & RF5G_RF5G1_PDPAOUT5_MASK) >> RF5G_RF5G1_PDPAOUT5_LSB)
+#define RF5G_RF5G1_PDPAOUT5_SET(x)               (((x) << RF5G_RF5G1_PDPAOUT5_LSB) & RF5G_RF5G1_PDPAOUT5_MASK)
+#define RF5G_RF5G1_TUNE_PADRV5_MSB               26
+#define RF5G_RF5G1_TUNE_PADRV5_LSB               24
+#define RF5G_RF5G1_TUNE_PADRV5_MASK              0x07000000
+#define RF5G_RF5G1_TUNE_PADRV5_GET(x)            (((x) & RF5G_RF5G1_TUNE_PADRV5_MASK) >> RF5G_RF5G1_TUNE_PADRV5_LSB)
+#define RF5G_RF5G1_TUNE_PADRV5_SET(x)            (((x) << RF5G_RF5G1_TUNE_PADRV5_LSB) & RF5G_RF5G1_TUNE_PADRV5_MASK)
+#define RF5G_RF5G1_PWDTXPKD_MSB                  23
+#define RF5G_RF5G1_PWDTXPKD_LSB                  21
+#define RF5G_RF5G1_PWDTXPKD_MASK                 0x00e00000
+#define RF5G_RF5G1_PWDTXPKD_GET(x)               (((x) & RF5G_RF5G1_PWDTXPKD_MASK) >> RF5G_RF5G1_PWDTXPKD_LSB)
+#define RF5G_RF5G1_PWDTXPKD_SET(x)               (((x) << RF5G_RF5G1_PWDTXPKD_LSB) & RF5G_RF5G1_PWDTXPKD_MASK)
+#define RF5G_RF5G1_DB5_MSB                       20
+#define RF5G_RF5G1_DB5_LSB                       18
+#define RF5G_RF5G1_DB5_MASK                      0x001c0000
+#define RF5G_RF5G1_DB5_GET(x)                    (((x) & RF5G_RF5G1_DB5_MASK) >> RF5G_RF5G1_DB5_LSB)
+#define RF5G_RF5G1_DB5_SET(x)                    (((x) << RF5G_RF5G1_DB5_LSB) & RF5G_RF5G1_DB5_MASK)
+#define RF5G_RF5G1_OB5_MSB                       17
+#define RF5G_RF5G1_OB5_LSB                       15
+#define RF5G_RF5G1_OB5_MASK                      0x00038000
+#define RF5G_RF5G1_OB5_GET(x)                    (((x) & RF5G_RF5G1_OB5_MASK) >> RF5G_RF5G1_OB5_LSB)
+#define RF5G_RF5G1_OB5_SET(x)                    (((x) << RF5G_RF5G1_OB5_LSB) & RF5G_RF5G1_OB5_MASK)
+#define RF5G_RF5G1_TX5_ATB_SEL_MSB               14
+#define RF5G_RF5G1_TX5_ATB_SEL_LSB               12
+#define RF5G_RF5G1_TX5_ATB_SEL_MASK              0x00007000
+#define RF5G_RF5G1_TX5_ATB_SEL_GET(x)            (((x) & RF5G_RF5G1_TX5_ATB_SEL_MASK) >> RF5G_RF5G1_TX5_ATB_SEL_LSB)
+#define RF5G_RF5G1_TX5_ATB_SEL_SET(x)            (((x) << RF5G_RF5G1_TX5_ATB_SEL_LSB) & RF5G_RF5G1_TX5_ATB_SEL_MASK)
+#define RF5G_RF5G1_PDLO5DIV_MSB                  11
+#define RF5G_RF5G1_PDLO5DIV_LSB                  11
+#define RF5G_RF5G1_PDLO5DIV_MASK                 0x00000800
+#define RF5G_RF5G1_PDLO5DIV_GET(x)               (((x) & RF5G_RF5G1_PDLO5DIV_MASK) >> RF5G_RF5G1_PDLO5DIV_LSB)
+#define RF5G_RF5G1_PDLO5DIV_SET(x)               (((x) << RF5G_RF5G1_PDLO5DIV_LSB) & RF5G_RF5G1_PDLO5DIV_MASK)
+#define RF5G_RF5G1_PDLO5MIX_MSB                  10
+#define RF5G_RF5G1_PDLO5MIX_LSB                  10
+#define RF5G_RF5G1_PDLO5MIX_MASK                 0x00000400
+#define RF5G_RF5G1_PDLO5MIX_GET(x)               (((x) & RF5G_RF5G1_PDLO5MIX_MASK) >> RF5G_RF5G1_PDLO5MIX_LSB)
+#define RF5G_RF5G1_PDLO5MIX_SET(x)               (((x) << RF5G_RF5G1_PDLO5MIX_LSB) & RF5G_RF5G1_PDLO5MIX_MASK)
+#define RF5G_RF5G1_PDQBUF5_MSB                   9
+#define RF5G_RF5G1_PDQBUF5_LSB                   9
+#define RF5G_RF5G1_PDQBUF5_MASK                  0x00000200
+#define RF5G_RF5G1_PDQBUF5_GET(x)                (((x) & RF5G_RF5G1_PDQBUF5_MASK) >> RF5G_RF5G1_PDQBUF5_LSB)
+#define RF5G_RF5G1_PDQBUF5_SET(x)                (((x) << RF5G_RF5G1_PDQBUF5_LSB) & RF5G_RF5G1_PDQBUF5_MASK)
+#define RF5G_RF5G1_PDLO5AGC_MSB                  8
+#define RF5G_RF5G1_PDLO5AGC_LSB                  8
+#define RF5G_RF5G1_PDLO5AGC_MASK                 0x00000100
+#define RF5G_RF5G1_PDLO5AGC_GET(x)               (((x) & RF5G_RF5G1_PDLO5AGC_MASK) >> RF5G_RF5G1_PDLO5AGC_LSB)
+#define RF5G_RF5G1_PDLO5AGC_SET(x)               (((x) << RF5G_RF5G1_PDLO5AGC_LSB) & RF5G_RF5G1_PDLO5AGC_MASK)
+#define RF5G_RF5G1_PDREGLO5_MSB                  7
+#define RF5G_RF5G1_PDREGLO5_LSB                  7
+#define RF5G_RF5G1_PDREGLO5_MASK                 0x00000080
+#define RF5G_RF5G1_PDREGLO5_GET(x)               (((x) & RF5G_RF5G1_PDREGLO5_MASK) >> RF5G_RF5G1_PDREGLO5_LSB)
+#define RF5G_RF5G1_PDREGLO5_SET(x)               (((x) << RF5G_RF5G1_PDREGLO5_LSB) & RF5G_RF5G1_PDREGLO5_MASK)
+#define RF5G_RF5G1_LO5_ATB_SEL_MSB               6
+#define RF5G_RF5G1_LO5_ATB_SEL_LSB               4
+#define RF5G_RF5G1_LO5_ATB_SEL_MASK              0x00000070
+#define RF5G_RF5G1_LO5_ATB_SEL_GET(x)            (((x) & RF5G_RF5G1_LO5_ATB_SEL_MASK) >> RF5G_RF5G1_LO5_ATB_SEL_LSB)
+#define RF5G_RF5G1_LO5_ATB_SEL_SET(x)            (((x) << RF5G_RF5G1_LO5_ATB_SEL_LSB) & RF5G_RF5G1_LO5_ATB_SEL_MASK)
+#define RF5G_RF5G1_LO5CONTROL_MSB                3
+#define RF5G_RF5G1_LO5CONTROL_LSB                3
+#define RF5G_RF5G1_LO5CONTROL_MASK               0x00000008
+#define RF5G_RF5G1_LO5CONTROL_GET(x)             (((x) & RF5G_RF5G1_LO5CONTROL_MASK) >> RF5G_RF5G1_LO5CONTROL_LSB)
+#define RF5G_RF5G1_LO5CONTROL_SET(x)             (((x) << RF5G_RF5G1_LO5CONTROL_LSB) & RF5G_RF5G1_LO5CONTROL_MASK)
+#define RF5G_RF5G1_REGLO_BYPASS5_MSB             2
+#define RF5G_RF5G1_REGLO_BYPASS5_LSB             2
+#define RF5G_RF5G1_REGLO_BYPASS5_MASK            0x00000004
+#define RF5G_RF5G1_REGLO_BYPASS5_GET(x)          (((x) & RF5G_RF5G1_REGLO_BYPASS5_MASK) >> RF5G_RF5G1_REGLO_BYPASS5_LSB)
+#define RF5G_RF5G1_REGLO_BYPASS5_SET(x)          (((x) << RF5G_RF5G1_REGLO_BYPASS5_LSB) & RF5G_RF5G1_REGLO_BYPASS5_MASK)
+#define RF5G_RF5G1_SPARE_MSB                     1
+#define RF5G_RF5G1_SPARE_LSB                     0
+#define RF5G_RF5G1_SPARE_MASK                    0x00000003
+#define RF5G_RF5G1_SPARE_GET(x)                  (((x) & RF5G_RF5G1_SPARE_MASK) >> RF5G_RF5G1_SPARE_LSB)
+#define RF5G_RF5G1_SPARE_SET(x)                  (((x) << RF5G_RF5G1_SPARE_LSB) & RF5G_RF5G1_SPARE_MASK)
+
+#define RF5G_RF5G2_ADDRESS                       0x00000024
+#define RF5G_RF5G2_OFFSET                        0x00000024
+#define RF5G_RF5G2_AGCLO_B_MSB                   31
+#define RF5G_RF5G2_AGCLO_B_LSB                   29
+#define RF5G_RF5G2_AGCLO_B_MASK                  0xe0000000
+#define RF5G_RF5G2_AGCLO_B_GET(x)                (((x) & RF5G_RF5G2_AGCLO_B_MASK) >> RF5G_RF5G2_AGCLO_B_LSB)
+#define RF5G_RF5G2_AGCLO_B_SET(x)                (((x) << RF5G_RF5G2_AGCLO_B_LSB) & RF5G_RF5G2_AGCLO_B_MASK)
+#define RF5G_RF5G2_RX5_ATB_SEL_MSB               28
+#define RF5G_RF5G2_RX5_ATB_SEL_LSB               26
+#define RF5G_RF5G2_RX5_ATB_SEL_MASK              0x1c000000
+#define RF5G_RF5G2_RX5_ATB_SEL_GET(x)            (((x) & RF5G_RF5G2_RX5_ATB_SEL_MASK) >> RF5G_RF5G2_RX5_ATB_SEL_LSB)
+#define RF5G_RF5G2_RX5_ATB_SEL_SET(x)            (((x) << RF5G_RF5G2_RX5_ATB_SEL_LSB) & RF5G_RF5G2_RX5_ATB_SEL_MASK)
+#define RF5G_RF5G2_PDCMOSLO5_MSB                 25
+#define RF5G_RF5G2_PDCMOSLO5_LSB                 25
+#define RF5G_RF5G2_PDCMOSLO5_MASK                0x02000000
+#define RF5G_RF5G2_PDCMOSLO5_GET(x)              (((x) & RF5G_RF5G2_PDCMOSLO5_MASK) >> RF5G_RF5G2_PDCMOSLO5_LSB)
+#define RF5G_RF5G2_PDCMOSLO5_SET(x)              (((x) << RF5G_RF5G2_PDCMOSLO5_LSB) & RF5G_RF5G2_PDCMOSLO5_MASK)
+#define RF5G_RF5G2_PDVGM5_MSB                    24
+#define RF5G_RF5G2_PDVGM5_LSB                    24
+#define RF5G_RF5G2_PDVGM5_MASK                   0x01000000
+#define RF5G_RF5G2_PDVGM5_GET(x)                 (((x) & RF5G_RF5G2_PDVGM5_MASK) >> RF5G_RF5G2_PDVGM5_LSB)
+#define RF5G_RF5G2_PDVGM5_SET(x)                 (((x) << RF5G_RF5G2_PDVGM5_LSB) & RF5G_RF5G2_PDVGM5_MASK)
+#define RF5G_RF5G2_PDCSLNA5_MSB                  23
+#define RF5G_RF5G2_PDCSLNA5_LSB                  23
+#define RF5G_RF5G2_PDCSLNA5_MASK                 0x00800000
+#define RF5G_RF5G2_PDCSLNA5_GET(x)               (((x) & RF5G_RF5G2_PDCSLNA5_MASK) >> RF5G_RF5G2_PDCSLNA5_LSB)
+#define RF5G_RF5G2_PDCSLNA5_SET(x)               (((x) << RF5G_RF5G2_PDCSLNA5_LSB) & RF5G_RF5G2_PDCSLNA5_MASK)
+#define RF5G_RF5G2_PDRFVGA5_MSB                  22
+#define RF5G_RF5G2_PDRFVGA5_LSB                  22
+#define RF5G_RF5G2_PDRFVGA5_MASK                 0x00400000
+#define RF5G_RF5G2_PDRFVGA5_GET(x)               (((x) & RF5G_RF5G2_PDRFVGA5_MASK) >> RF5G_RF5G2_PDRFVGA5_LSB)
+#define RF5G_RF5G2_PDRFVGA5_SET(x)               (((x) << RF5G_RF5G2_PDRFVGA5_LSB) & RF5G_RF5G2_PDRFVGA5_MASK)
+#define RF5G_RF5G2_PDREGFE5_MSB                  21
+#define RF5G_RF5G2_PDREGFE5_LSB                  21
+#define RF5G_RF5G2_PDREGFE5_MASK                 0x00200000
+#define RF5G_RF5G2_PDREGFE5_GET(x)               (((x) & RF5G_RF5G2_PDREGFE5_MASK) >> RF5G_RF5G2_PDREGFE5_LSB)
+#define RF5G_RF5G2_PDREGFE5_SET(x)               (((x) << RF5G_RF5G2_PDREGFE5_LSB) & RF5G_RF5G2_PDREGFE5_MASK)
+#define RF5G_RF5G2_TUNE_RFVGA5_MSB               20
+#define RF5G_RF5G2_TUNE_RFVGA5_LSB               18
+#define RF5G_RF5G2_TUNE_RFVGA5_MASK              0x001c0000
+#define RF5G_RF5G2_TUNE_RFVGA5_GET(x)            (((x) & RF5G_RF5G2_TUNE_RFVGA5_MASK) >> RF5G_RF5G2_TUNE_RFVGA5_LSB)
+#define RF5G_RF5G2_TUNE_RFVGA5_SET(x)            (((x) << RF5G_RF5G2_TUNE_RFVGA5_LSB) & RF5G_RF5G2_TUNE_RFVGA5_MASK)
+#define RF5G_RF5G2_BRFVGA5_MSB                   17
+#define RF5G_RF5G2_BRFVGA5_LSB                   15
+#define RF5G_RF5G2_BRFVGA5_MASK                  0x00038000
+#define RF5G_RF5G2_BRFVGA5_GET(x)                (((x) & RF5G_RF5G2_BRFVGA5_MASK) >> RF5G_RF5G2_BRFVGA5_LSB)
+#define RF5G_RF5G2_BRFVGA5_SET(x)                (((x) << RF5G_RF5G2_BRFVGA5_LSB) & RF5G_RF5G2_BRFVGA5_MASK)
+#define RF5G_RF5G2_BCSLNA5_MSB                   14
+#define RF5G_RF5G2_BCSLNA5_LSB                   12
+#define RF5G_RF5G2_BCSLNA5_MASK                  0x00007000
+#define RF5G_RF5G2_BCSLNA5_GET(x)                (((x) & RF5G_RF5G2_BCSLNA5_MASK) >> RF5G_RF5G2_BCSLNA5_LSB)
+#define RF5G_RF5G2_BCSLNA5_SET(x)                (((x) << RF5G_RF5G2_BCSLNA5_LSB) & RF5G_RF5G2_BCSLNA5_MASK)
+#define RF5G_RF5G2_BVGM5_MSB                     11
+#define RF5G_RF5G2_BVGM5_LSB                     9
+#define RF5G_RF5G2_BVGM5_MASK                    0x00000e00
+#define RF5G_RF5G2_BVGM5_GET(x)                  (((x) & RF5G_RF5G2_BVGM5_MASK) >> RF5G_RF5G2_BVGM5_LSB)
+#define RF5G_RF5G2_BVGM5_SET(x)                  (((x) << RF5G_RF5G2_BVGM5_LSB) & RF5G_RF5G2_BVGM5_MASK)
+#define RF5G_RF5G2_REGFE_BYPASS5_MSB             8
+#define RF5G_RF5G2_REGFE_BYPASS5_LSB             8
+#define RF5G_RF5G2_REGFE_BYPASS5_MASK            0x00000100
+#define RF5G_RF5G2_REGFE_BYPASS5_GET(x)          (((x) & RF5G_RF5G2_REGFE_BYPASS5_MASK) >> RF5G_RF5G2_REGFE_BYPASS5_LSB)
+#define RF5G_RF5G2_REGFE_BYPASS5_SET(x)          (((x) << RF5G_RF5G2_REGFE_BYPASS5_LSB) & RF5G_RF5G2_REGFE_BYPASS5_MASK)
+#define RF5G_RF5G2_LNA5_ATTENMODE_MSB            7
+#define RF5G_RF5G2_LNA5_ATTENMODE_LSB            6
+#define RF5G_RF5G2_LNA5_ATTENMODE_MASK           0x000000c0
+#define RF5G_RF5G2_LNA5_ATTENMODE_GET(x)         (((x) & RF5G_RF5G2_LNA5_ATTENMODE_MASK) >> RF5G_RF5G2_LNA5_ATTENMODE_LSB)
+#define RF5G_RF5G2_LNA5_ATTENMODE_SET(x)         (((x) << RF5G_RF5G2_LNA5_ATTENMODE_LSB) & RF5G_RF5G2_LNA5_ATTENMODE_MASK)
+#define RF5G_RF5G2_ENABLE_PCA_MSB                5
+#define RF5G_RF5G2_ENABLE_PCA_LSB                5
+#define RF5G_RF5G2_ENABLE_PCA_MASK               0x00000020
+#define RF5G_RF5G2_ENABLE_PCA_GET(x)             (((x) & RF5G_RF5G2_ENABLE_PCA_MASK) >> RF5G_RF5G2_ENABLE_PCA_LSB)
+#define RF5G_RF5G2_ENABLE_PCA_SET(x)             (((x) << RF5G_RF5G2_ENABLE_PCA_LSB) & RF5G_RF5G2_ENABLE_PCA_MASK)
+#define RF5G_RF5G2_TUNE_LO_MSB                   4
+#define RF5G_RF5G2_TUNE_LO_LSB                   2
+#define RF5G_RF5G2_TUNE_LO_MASK                  0x0000001c
+#define RF5G_RF5G2_TUNE_LO_GET(x)                (((x) & RF5G_RF5G2_TUNE_LO_MASK) >> RF5G_RF5G2_TUNE_LO_LSB)
+#define RF5G_RF5G2_TUNE_LO_SET(x)                (((x) << RF5G_RF5G2_TUNE_LO_LSB) & RF5G_RF5G2_TUNE_LO_MASK)
+#define RF5G_RF5G2_SPARE_MSB                     1
+#define RF5G_RF5G2_SPARE_LSB                     0
+#define RF5G_RF5G2_SPARE_MASK                    0x00000003
+#define RF5G_RF5G2_SPARE_GET(x)                  (((x) & RF5G_RF5G2_SPARE_MASK) >> RF5G_RF5G2_SPARE_LSB)
+#define RF5G_RF5G2_SPARE_SET(x)                  (((x) << RF5G_RF5G2_SPARE_LSB) & RF5G_RF5G2_SPARE_MASK)
+
+#define RF2G_RF2G1_ADDRESS                       0x00000028
+#define RF2G_RF2G1_OFFSET                        0x00000028
+#define RF2G_RF2G1_BLNA1_MSB                     31
+#define RF2G_RF2G1_BLNA1_LSB                     29
+#define RF2G_RF2G1_BLNA1_MASK                    0xe0000000
+#define RF2G_RF2G1_BLNA1_GET(x)                  (((x) & RF2G_RF2G1_BLNA1_MASK) >> RF2G_RF2G1_BLNA1_LSB)
+#define RF2G_RF2G1_BLNA1_SET(x)                  (((x) << RF2G_RF2G1_BLNA1_LSB) & RF2G_RF2G1_BLNA1_MASK)
+#define RF2G_RF2G1_BLNA1F_MSB                    28
+#define RF2G_RF2G1_BLNA1F_LSB                    26
+#define RF2G_RF2G1_BLNA1F_MASK                   0x1c000000
+#define RF2G_RF2G1_BLNA1F_GET(x)                 (((x) & RF2G_RF2G1_BLNA1F_MASK) >> RF2G_RF2G1_BLNA1F_LSB)
+#define RF2G_RF2G1_BLNA1F_SET(x)                 (((x) << RF2G_RF2G1_BLNA1F_LSB) & RF2G_RF2G1_BLNA1F_MASK)
+#define RF2G_RF2G1_BLNA1BUF_MSB                  25
+#define RF2G_RF2G1_BLNA1BUF_LSB                  23
+#define RF2G_RF2G1_BLNA1BUF_MASK                 0x03800000
+#define RF2G_RF2G1_BLNA1BUF_GET(x)               (((x) & RF2G_RF2G1_BLNA1BUF_MASK) >> RF2G_RF2G1_BLNA1BUF_LSB)
+#define RF2G_RF2G1_BLNA1BUF_SET(x)               (((x) << RF2G_RF2G1_BLNA1BUF_LSB) & RF2G_RF2G1_BLNA1BUF_MASK)
+#define RF2G_RF2G1_BLNA2_MSB                     22
+#define RF2G_RF2G1_BLNA2_LSB                     20
+#define RF2G_RF2G1_BLNA2_MASK                    0x00700000
+#define RF2G_RF2G1_BLNA2_GET(x)                  (((x) & RF2G_RF2G1_BLNA2_MASK) >> RF2G_RF2G1_BLNA2_LSB)
+#define RF2G_RF2G1_BLNA2_SET(x)                  (((x) << RF2G_RF2G1_BLNA2_LSB) & RF2G_RF2G1_BLNA2_MASK)
+#define RF2G_RF2G1_DB_MSB                        19
+#define RF2G_RF2G1_DB_LSB                        17
+#define RF2G_RF2G1_DB_MASK                       0x000e0000
+#define RF2G_RF2G1_DB_GET(x)                     (((x) & RF2G_RF2G1_DB_MASK) >> RF2G_RF2G1_DB_LSB)
+#define RF2G_RF2G1_DB_SET(x)                     (((x) << RF2G_RF2G1_DB_LSB) & RF2G_RF2G1_DB_MASK)
+#define RF2G_RF2G1_OB_MSB                        16
+#define RF2G_RF2G1_OB_LSB                        14
+#define RF2G_RF2G1_OB_MASK                       0x0001c000
+#define RF2G_RF2G1_OB_GET(x)                     (((x) & RF2G_RF2G1_OB_MASK) >> RF2G_RF2G1_OB_LSB)
+#define RF2G_RF2G1_OB_SET(x)                     (((x) << RF2G_RF2G1_OB_LSB) & RF2G_RF2G1_OB_MASK)
+#define RF2G_RF2G1_FE_ATB_SEL_MSB                13
+#define RF2G_RF2G1_FE_ATB_SEL_LSB                11
+#define RF2G_RF2G1_FE_ATB_SEL_MASK               0x00003800
+#define RF2G_RF2G1_FE_ATB_SEL_GET(x)             (((x) & RF2G_RF2G1_FE_ATB_SEL_MASK) >> RF2G_RF2G1_FE_ATB_SEL_LSB)
+#define RF2G_RF2G1_FE_ATB_SEL_SET(x)             (((x) << RF2G_RF2G1_FE_ATB_SEL_LSB) & RF2G_RF2G1_FE_ATB_SEL_MASK)
+#define RF2G_RF2G1_RF_ATB_SEL_MSB                10
+#define RF2G_RF2G1_RF_ATB_SEL_LSB                8
+#define RF2G_RF2G1_RF_ATB_SEL_MASK               0x00000700
+#define RF2G_RF2G1_RF_ATB_SEL_GET(x)             (((x) & RF2G_RF2G1_RF_ATB_SEL_MASK) >> RF2G_RF2G1_RF_ATB_SEL_LSB)
+#define RF2G_RF2G1_RF_ATB_SEL_SET(x)             (((x) << RF2G_RF2G1_RF_ATB_SEL_LSB) & RF2G_RF2G1_RF_ATB_SEL_MASK)
+#define RF2G_RF2G1_SELLNA_MSB                    7
+#define RF2G_RF2G1_SELLNA_LSB                    7
+#define RF2G_RF2G1_SELLNA_MASK                   0x00000080
+#define RF2G_RF2G1_SELLNA_GET(x)                 (((x) & RF2G_RF2G1_SELLNA_MASK) >> RF2G_RF2G1_SELLNA_LSB)
+#define RF2G_RF2G1_SELLNA_SET(x)                 (((x) << RF2G_RF2G1_SELLNA_LSB) & RF2G_RF2G1_SELLNA_MASK)
+#define RF2G_RF2G1_LOCONTROL_MSB                 6
+#define RF2G_RF2G1_LOCONTROL_LSB                 6
+#define RF2G_RF2G1_LOCONTROL_MASK                0x00000040
+#define RF2G_RF2G1_LOCONTROL_GET(x)              (((x) & RF2G_RF2G1_LOCONTROL_MASK) >> RF2G_RF2G1_LOCONTROL_LSB)
+#define RF2G_RF2G1_LOCONTROL_SET(x)              (((x) << RF2G_RF2G1_LOCONTROL_LSB) & RF2G_RF2G1_LOCONTROL_MASK)
+#define RF2G_RF2G1_SHORTLNA2_MSB                 5
+#define RF2G_RF2G1_SHORTLNA2_LSB                 5
+#define RF2G_RF2G1_SHORTLNA2_MASK                0x00000020
+#define RF2G_RF2G1_SHORTLNA2_GET(x)              (((x) & RF2G_RF2G1_SHORTLNA2_MASK) >> RF2G_RF2G1_SHORTLNA2_LSB)
+#define RF2G_RF2G1_SHORTLNA2_SET(x)              (((x) << RF2G_RF2G1_SHORTLNA2_LSB) & RF2G_RF2G1_SHORTLNA2_MASK)
+#define RF2G_RF2G1_SPARE_MSB                     4
+#define RF2G_RF2G1_SPARE_LSB                     0
+#define RF2G_RF2G1_SPARE_MASK                    0x0000001f
+#define RF2G_RF2G1_SPARE_GET(x)                  (((x) & RF2G_RF2G1_SPARE_MASK) >> RF2G_RF2G1_SPARE_LSB)
+#define RF2G_RF2G1_SPARE_SET(x)                  (((x) << RF2G_RF2G1_SPARE_LSB) & RF2G_RF2G1_SPARE_MASK)
+
+#define RF2G_RF2G2_ADDRESS                       0x0000002c
+#define RF2G_RF2G2_OFFSET                        0x0000002c
+#define RF2G_RF2G2_PDCGLNA_MSB                   31
+#define RF2G_RF2G2_PDCGLNA_LSB                   31
+#define RF2G_RF2G2_PDCGLNA_MASK                  0x80000000
+#define RF2G_RF2G2_PDCGLNA_GET(x)                (((x) & RF2G_RF2G2_PDCGLNA_MASK) >> RF2G_RF2G2_PDCGLNA_LSB)
+#define RF2G_RF2G2_PDCGLNA_SET(x)                (((x) << RF2G_RF2G2_PDCGLNA_LSB) & RF2G_RF2G2_PDCGLNA_MASK)
+#define RF2G_RF2G2_PDCGLNABUF_MSB                30
+#define RF2G_RF2G2_PDCGLNABUF_LSB                30
+#define RF2G_RF2G2_PDCGLNABUF_MASK               0x40000000
+#define RF2G_RF2G2_PDCGLNABUF_GET(x)             (((x) & RF2G_RF2G2_PDCGLNABUF_MASK) >> RF2G_RF2G2_PDCGLNABUF_LSB)
+#define RF2G_RF2G2_PDCGLNABUF_SET(x)             (((x) << RF2G_RF2G2_PDCGLNABUF_LSB) & RF2G_RF2G2_PDCGLNABUF_MASK)
+#define RF2G_RF2G2_PDCSLNA_MSB                   29
+#define RF2G_RF2G2_PDCSLNA_LSB                   29
+#define RF2G_RF2G2_PDCSLNA_MASK                  0x20000000
+#define RF2G_RF2G2_PDCSLNA_GET(x)                (((x) & RF2G_RF2G2_PDCSLNA_MASK) >> RF2G_RF2G2_PDCSLNA_LSB)
+#define RF2G_RF2G2_PDCSLNA_SET(x)                (((x) << RF2G_RF2G2_PDCSLNA_LSB) & RF2G_RF2G2_PDCSLNA_MASK)
+#define RF2G_RF2G2_PDDIV_MSB                     28
+#define RF2G_RF2G2_PDDIV_LSB                     28
+#define RF2G_RF2G2_PDDIV_MASK                    0x10000000
+#define RF2G_RF2G2_PDDIV_GET(x)                  (((x) & RF2G_RF2G2_PDDIV_MASK) >> RF2G_RF2G2_PDDIV_LSB)
+#define RF2G_RF2G2_PDDIV_SET(x)                  (((x) << RF2G_RF2G2_PDDIV_LSB) & RF2G_RF2G2_PDDIV_MASK)
+#define RF2G_RF2G2_PDPADRV_MSB                   27
+#define RF2G_RF2G2_PDPADRV_LSB                   27
+#define RF2G_RF2G2_PDPADRV_MASK                  0x08000000
+#define RF2G_RF2G2_PDPADRV_GET(x)                (((x) & RF2G_RF2G2_PDPADRV_MASK) >> RF2G_RF2G2_PDPADRV_LSB)
+#define RF2G_RF2G2_PDPADRV_SET(x)                (((x) << RF2G_RF2G2_PDPADRV_LSB) & RF2G_RF2G2_PDPADRV_MASK)
+#define RF2G_RF2G2_PDPAOUT_MSB                   26
+#define RF2G_RF2G2_PDPAOUT_LSB                   26
+#define RF2G_RF2G2_PDPAOUT_MASK                  0x04000000
+#define RF2G_RF2G2_PDPAOUT_GET(x)                (((x) & RF2G_RF2G2_PDPAOUT_MASK) >> RF2G_RF2G2_PDPAOUT_LSB)
+#define RF2G_RF2G2_PDPAOUT_SET(x)                (((x) << RF2G_RF2G2_PDPAOUT_LSB) & RF2G_RF2G2_PDPAOUT_MASK)
+#define RF2G_RF2G2_PDREGLNA_MSB                  25
+#define RF2G_RF2G2_PDREGLNA_LSB                  25
+#define RF2G_RF2G2_PDREGLNA_MASK                 0x02000000
+#define RF2G_RF2G2_PDREGLNA_GET(x)               (((x) & RF2G_RF2G2_PDREGLNA_MASK) >> RF2G_RF2G2_PDREGLNA_LSB)
+#define RF2G_RF2G2_PDREGLNA_SET(x)               (((x) << RF2G_RF2G2_PDREGLNA_LSB) & RF2G_RF2G2_PDREGLNA_MASK)
+#define RF2G_RF2G2_PDREGLO_MSB                   24
+#define RF2G_RF2G2_PDREGLO_LSB                   24
+#define RF2G_RF2G2_PDREGLO_MASK                  0x01000000
+#define RF2G_RF2G2_PDREGLO_GET(x)                (((x) & RF2G_RF2G2_PDREGLO_MASK) >> RF2G_RF2G2_PDREGLO_LSB)
+#define RF2G_RF2G2_PDREGLO_SET(x)                (((x) << RF2G_RF2G2_PDREGLO_LSB) & RF2G_RF2G2_PDREGLO_MASK)
+#define RF2G_RF2G2_PDRFGM_MSB                    23
+#define RF2G_RF2G2_PDRFGM_LSB                    23
+#define RF2G_RF2G2_PDRFGM_MASK                   0x00800000
+#define RF2G_RF2G2_PDRFGM_GET(x)                 (((x) & RF2G_RF2G2_PDRFGM_MASK) >> RF2G_RF2G2_PDRFGM_LSB)
+#define RF2G_RF2G2_PDRFGM_SET(x)                 (((x) << RF2G_RF2G2_PDRFGM_LSB) & RF2G_RF2G2_PDRFGM_MASK)
+#define RF2G_RF2G2_PDRXLO_MSB                    22
+#define RF2G_RF2G2_PDRXLO_LSB                    22
+#define RF2G_RF2G2_PDRXLO_MASK                   0x00400000
+#define RF2G_RF2G2_PDRXLO_GET(x)                 (((x) & RF2G_RF2G2_PDRXLO_MASK) >> RF2G_RF2G2_PDRXLO_LSB)
+#define RF2G_RF2G2_PDRXLO_SET(x)                 (((x) << RF2G_RF2G2_PDRXLO_LSB) & RF2G_RF2G2_PDRXLO_MASK)
+#define RF2G_RF2G2_PDTXLO_MSB                    21
+#define RF2G_RF2G2_PDTXLO_LSB                    21
+#define RF2G_RF2G2_PDTXLO_MASK                   0x00200000
+#define RF2G_RF2G2_PDTXLO_GET(x)                 (((x) & RF2G_RF2G2_PDTXLO_MASK) >> RF2G_RF2G2_PDTXLO_LSB)
+#define RF2G_RF2G2_PDTXLO_SET(x)                 (((x) << RF2G_RF2G2_PDTXLO_LSB) & RF2G_RF2G2_PDTXLO_MASK)
+#define RF2G_RF2G2_PDTXMIX_MSB                   20
+#define RF2G_RF2G2_PDTXMIX_LSB                   20
+#define RF2G_RF2G2_PDTXMIX_MASK                  0x00100000
+#define RF2G_RF2G2_PDTXMIX_GET(x)                (((x) & RF2G_RF2G2_PDTXMIX_MASK) >> RF2G_RF2G2_PDTXMIX_LSB)
+#define RF2G_RF2G2_PDTXMIX_SET(x)                (((x) << RF2G_RF2G2_PDTXMIX_LSB) & RF2G_RF2G2_PDTXMIX_MASK)
+#define RF2G_RF2G2_REGLNA_BYPASS_MSB             19
+#define RF2G_RF2G2_REGLNA_BYPASS_LSB             19
+#define RF2G_RF2G2_REGLNA_BYPASS_MASK            0x00080000
+#define RF2G_RF2G2_REGLNA_BYPASS_GET(x)          (((x) & RF2G_RF2G2_REGLNA_BYPASS_MASK) >> RF2G_RF2G2_REGLNA_BYPASS_LSB)
+#define RF2G_RF2G2_REGLNA_BYPASS_SET(x)          (((x) << RF2G_RF2G2_REGLNA_BYPASS_LSB) & RF2G_RF2G2_REGLNA_BYPASS_MASK)
+#define RF2G_RF2G2_REGLO_BYPASS_MSB              18
+#define RF2G_RF2G2_REGLO_BYPASS_LSB              18
+#define RF2G_RF2G2_REGLO_BYPASS_MASK             0x00040000
+#define RF2G_RF2G2_REGLO_BYPASS_GET(x)           (((x) & RF2G_RF2G2_REGLO_BYPASS_MASK) >> RF2G_RF2G2_REGLO_BYPASS_LSB)
+#define RF2G_RF2G2_REGLO_BYPASS_SET(x)           (((x) << RF2G_RF2G2_REGLO_BYPASS_LSB) & RF2G_RF2G2_REGLO_BYPASS_MASK)
+#define RF2G_RF2G2_ENABLE_PCB_MSB                17
+#define RF2G_RF2G2_ENABLE_PCB_LSB                17
+#define RF2G_RF2G2_ENABLE_PCB_MASK               0x00020000
+#define RF2G_RF2G2_ENABLE_PCB_GET(x)             (((x) & RF2G_RF2G2_ENABLE_PCB_MASK) >> RF2G_RF2G2_ENABLE_PCB_LSB)
+#define RF2G_RF2G2_ENABLE_PCB_SET(x)             (((x) << RF2G_RF2G2_ENABLE_PCB_LSB) & RF2G_RF2G2_ENABLE_PCB_MASK)
+#define RF2G_RF2G2_SPARE_MSB                     16
+#define RF2G_RF2G2_SPARE_LSB                     0
+#define RF2G_RF2G2_SPARE_MASK                    0x0001ffff
+#define RF2G_RF2G2_SPARE_GET(x)                  (((x) & RF2G_RF2G2_SPARE_MASK) >> RF2G_RF2G2_SPARE_LSB)
+#define RF2G_RF2G2_SPARE_SET(x)                  (((x) << RF2G_RF2G2_SPARE_LSB) & RF2G_RF2G2_SPARE_MASK)
+
+#define TOP_GAIN_ADDRESS                         0x00000030
+#define TOP_GAIN_OFFSET                          0x00000030
+#define TOP_GAIN_TX6DBLOQGAIN_MSB                31
+#define TOP_GAIN_TX6DBLOQGAIN_LSB                30
+#define TOP_GAIN_TX6DBLOQGAIN_MASK               0xc0000000
+#define TOP_GAIN_TX6DBLOQGAIN_GET(x)             (((x) & TOP_GAIN_TX6DBLOQGAIN_MASK) >> TOP_GAIN_TX6DBLOQGAIN_LSB)
+#define TOP_GAIN_TX6DBLOQGAIN_SET(x)             (((x) << TOP_GAIN_TX6DBLOQGAIN_LSB) & TOP_GAIN_TX6DBLOQGAIN_MASK)
+#define TOP_GAIN_TX1DBLOQGAIN_MSB                29
+#define TOP_GAIN_TX1DBLOQGAIN_LSB                27
+#define TOP_GAIN_TX1DBLOQGAIN_MASK               0x38000000
+#define TOP_GAIN_TX1DBLOQGAIN_GET(x)             (((x) & TOP_GAIN_TX1DBLOQGAIN_MASK) >> TOP_GAIN_TX1DBLOQGAIN_LSB)
+#define TOP_GAIN_TX1DBLOQGAIN_SET(x)             (((x) << TOP_GAIN_TX1DBLOQGAIN_LSB) & TOP_GAIN_TX1DBLOQGAIN_MASK)
+#define TOP_GAIN_TXV2IGAIN_MSB                   26
+#define TOP_GAIN_TXV2IGAIN_LSB                   25
+#define TOP_GAIN_TXV2IGAIN_MASK                  0x06000000
+#define TOP_GAIN_TXV2IGAIN_GET(x)                (((x) & TOP_GAIN_TXV2IGAIN_MASK) >> TOP_GAIN_TXV2IGAIN_LSB)
+#define TOP_GAIN_TXV2IGAIN_SET(x)                (((x) << TOP_GAIN_TXV2IGAIN_LSB) & TOP_GAIN_TXV2IGAIN_MASK)
+#define TOP_GAIN_PABUF5GN_MSB                    24
+#define TOP_GAIN_PABUF5GN_LSB                    24
+#define TOP_GAIN_PABUF5GN_MASK                   0x01000000
+#define TOP_GAIN_PABUF5GN_GET(x)                 (((x) & TOP_GAIN_PABUF5GN_MASK) >> TOP_GAIN_PABUF5GN_LSB)
+#define TOP_GAIN_PABUF5GN_SET(x)                 (((x) << TOP_GAIN_PABUF5GN_LSB) & TOP_GAIN_PABUF5GN_MASK)
+#define TOP_GAIN_PADRVGN_MSB                     23
+#define TOP_GAIN_PADRVGN_LSB                     21
+#define TOP_GAIN_PADRVGN_MASK                    0x00e00000
+#define TOP_GAIN_PADRVGN_GET(x)                  (((x) & TOP_GAIN_PADRVGN_MASK) >> TOP_GAIN_PADRVGN_LSB)
+#define TOP_GAIN_PADRVGN_SET(x)                  (((x) << TOP_GAIN_PADRVGN_LSB) & TOP_GAIN_PADRVGN_MASK)
+#define TOP_GAIN_PAOUT2GN_MSB                    20
+#define TOP_GAIN_PAOUT2GN_LSB                    18
+#define TOP_GAIN_PAOUT2GN_MASK                   0x001c0000
+#define TOP_GAIN_PAOUT2GN_GET(x)                 (((x) & TOP_GAIN_PAOUT2GN_MASK) >> TOP_GAIN_PAOUT2GN_LSB)
+#define TOP_GAIN_PAOUT2GN_SET(x)                 (((x) << TOP_GAIN_PAOUT2GN_LSB) & TOP_GAIN_PAOUT2GN_MASK)
+#define TOP_GAIN_LNAON_MSB                       17
+#define TOP_GAIN_LNAON_LSB                       17
+#define TOP_GAIN_LNAON_MASK                      0x00020000
+#define TOP_GAIN_LNAON_GET(x)                    (((x) & TOP_GAIN_LNAON_MASK) >> TOP_GAIN_LNAON_LSB)
+#define TOP_GAIN_LNAON_SET(x)                    (((x) << TOP_GAIN_LNAON_LSB) & TOP_GAIN_LNAON_MASK)
+#define TOP_GAIN_LNAGAIN_MSB                     16
+#define TOP_GAIN_LNAGAIN_LSB                     13
+#define TOP_GAIN_LNAGAIN_MASK                    0x0001e000
+#define TOP_GAIN_LNAGAIN_GET(x)                  (((x) & TOP_GAIN_LNAGAIN_MASK) >> TOP_GAIN_LNAGAIN_LSB)
+#define TOP_GAIN_LNAGAIN_SET(x)                  (((x) << TOP_GAIN_LNAGAIN_LSB) & TOP_GAIN_LNAGAIN_MASK)
+#define TOP_GAIN_RFVGA5GAIN_MSB                  12
+#define TOP_GAIN_RFVGA5GAIN_LSB                  11
+#define TOP_GAIN_RFVGA5GAIN_MASK                 0x00001800
+#define TOP_GAIN_RFVGA5GAIN_GET(x)               (((x) & TOP_GAIN_RFVGA5GAIN_MASK) >> TOP_GAIN_RFVGA5GAIN_LSB)
+#define TOP_GAIN_RFVGA5GAIN_SET(x)               (((x) << TOP_GAIN_RFVGA5GAIN_LSB) & TOP_GAIN_RFVGA5GAIN_MASK)
+#define TOP_GAIN_RFGMGN_MSB                      10
+#define TOP_GAIN_RFGMGN_LSB                      8
+#define TOP_GAIN_RFGMGN_MASK                     0x00000700
+#define TOP_GAIN_RFGMGN_GET(x)                   (((x) & TOP_GAIN_RFGMGN_MASK) >> TOP_GAIN_RFGMGN_LSB)
+#define TOP_GAIN_RFGMGN_SET(x)                   (((x) << TOP_GAIN_RFGMGN_LSB) & TOP_GAIN_RFGMGN_MASK)
+#define TOP_GAIN_RX6DBLOQGAIN_MSB                7
+#define TOP_GAIN_RX6DBLOQGAIN_LSB                6
+#define TOP_GAIN_RX6DBLOQGAIN_MASK               0x000000c0
+#define TOP_GAIN_RX6DBLOQGAIN_GET(x)             (((x) & TOP_GAIN_RX6DBLOQGAIN_MASK) >> TOP_GAIN_RX6DBLOQGAIN_LSB)
+#define TOP_GAIN_RX6DBLOQGAIN_SET(x)             (((x) << TOP_GAIN_RX6DBLOQGAIN_LSB) & TOP_GAIN_RX6DBLOQGAIN_MASK)
+#define TOP_GAIN_RX1DBLOQGAIN_MSB                5
+#define TOP_GAIN_RX1DBLOQGAIN_LSB                3
+#define TOP_GAIN_RX1DBLOQGAIN_MASK               0x00000038
+#define TOP_GAIN_RX1DBLOQGAIN_GET(x)             (((x) & TOP_GAIN_RX1DBLOQGAIN_MASK) >> TOP_GAIN_RX1DBLOQGAIN_LSB)
+#define TOP_GAIN_RX1DBLOQGAIN_SET(x)             (((x) << TOP_GAIN_RX1DBLOQGAIN_LSB) & TOP_GAIN_RX1DBLOQGAIN_MASK)
+#define TOP_GAIN_RX6DBHIQGAIN_MSB                2
+#define TOP_GAIN_RX6DBHIQGAIN_LSB                1
+#define TOP_GAIN_RX6DBHIQGAIN_MASK               0x00000006
+#define TOP_GAIN_RX6DBHIQGAIN_GET(x)             (((x) & TOP_GAIN_RX6DBHIQGAIN_MASK) >> TOP_GAIN_RX6DBHIQGAIN_LSB)
+#define TOP_GAIN_RX6DBHIQGAIN_SET(x)             (((x) << TOP_GAIN_RX6DBHIQGAIN_LSB) & TOP_GAIN_RX6DBHIQGAIN_MASK)
+#define TOP_GAIN_SPARE_MSB                       0
+#define TOP_GAIN_SPARE_LSB                       0
+#define TOP_GAIN_SPARE_MASK                      0x00000001
+#define TOP_GAIN_SPARE_GET(x)                    (((x) & TOP_GAIN_SPARE_MASK) >> TOP_GAIN_SPARE_LSB)
+#define TOP_GAIN_SPARE_SET(x)                    (((x) << TOP_GAIN_SPARE_LSB) & TOP_GAIN_SPARE_MASK)
+
+#define TOP_TOP_ADDRESS                          0x00000034
+#define TOP_TOP_OFFSET                           0x00000034
+#define TOP_TOP_LOCALTXGAIN_MSB                  31
+#define TOP_TOP_LOCALTXGAIN_LSB                  31
+#define TOP_TOP_LOCALTXGAIN_MASK                 0x80000000
+#define TOP_TOP_LOCALTXGAIN_GET(x)               (((x) & TOP_TOP_LOCALTXGAIN_MASK) >> TOP_TOP_LOCALTXGAIN_LSB)
+#define TOP_TOP_LOCALTXGAIN_SET(x)               (((x) << TOP_TOP_LOCALTXGAIN_LSB) & TOP_TOP_LOCALTXGAIN_MASK)
+#define TOP_TOP_LOCALRXGAIN_MSB                  30
+#define TOP_TOP_LOCALRXGAIN_LSB                  30
+#define TOP_TOP_LOCALRXGAIN_MASK                 0x40000000
+#define TOP_TOP_LOCALRXGAIN_GET(x)               (((x) & TOP_TOP_LOCALRXGAIN_MASK) >> TOP_TOP_LOCALRXGAIN_LSB)
+#define TOP_TOP_LOCALRXGAIN_SET(x)               (((x) << TOP_TOP_LOCALRXGAIN_LSB) & TOP_TOP_LOCALRXGAIN_MASK)
+#define TOP_TOP_LOCALMODE_MSB                    29
+#define TOP_TOP_LOCALMODE_LSB                    29
+#define TOP_TOP_LOCALMODE_MASK                   0x20000000
+#define TOP_TOP_LOCALMODE_GET(x)                 (((x) & TOP_TOP_LOCALMODE_MASK) >> TOP_TOP_LOCALMODE_LSB)
+#define TOP_TOP_LOCALMODE_SET(x)                 (((x) << TOP_TOP_LOCALMODE_LSB) & TOP_TOP_LOCALMODE_MASK)
+#define TOP_TOP_CALFC_MSB                        28
+#define TOP_TOP_CALFC_LSB                        28
+#define TOP_TOP_CALFC_MASK                       0x10000000
+#define TOP_TOP_CALFC_GET(x)                     (((x) & TOP_TOP_CALFC_MASK) >> TOP_TOP_CALFC_LSB)
+#define TOP_TOP_CALFC_SET(x)                     (((x) << TOP_TOP_CALFC_LSB) & TOP_TOP_CALFC_MASK)
+#define TOP_TOP_CALDC_MSB                        27
+#define TOP_TOP_CALDC_LSB                        27
+#define TOP_TOP_CALDC_MASK                       0x08000000
+#define TOP_TOP_CALDC_GET(x)                     (((x) & TOP_TOP_CALDC_MASK) >> TOP_TOP_CALDC_LSB)
+#define TOP_TOP_CALDC_SET(x)                     (((x) << TOP_TOP_CALDC_LSB) & TOP_TOP_CALDC_MASK)
+#define TOP_TOP_CAL_RESIDUE_MSB                  26
+#define TOP_TOP_CAL_RESIDUE_LSB                  26
+#define TOP_TOP_CAL_RESIDUE_MASK                 0x04000000
+#define TOP_TOP_CAL_RESIDUE_GET(x)               (((x) & TOP_TOP_CAL_RESIDUE_MASK) >> TOP_TOP_CAL_RESIDUE_LSB)
+#define TOP_TOP_CAL_RESIDUE_SET(x)               (((x) << TOP_TOP_CAL_RESIDUE_LSB) & TOP_TOP_CAL_RESIDUE_MASK)
+#define TOP_TOP_BMODE_MSB                        25
+#define TOP_TOP_BMODE_LSB                        25
+#define TOP_TOP_BMODE_MASK                       0x02000000
+#define TOP_TOP_BMODE_GET(x)                     (((x) & TOP_TOP_BMODE_MASK) >> TOP_TOP_BMODE_LSB)
+#define TOP_TOP_BMODE_SET(x)                     (((x) << TOP_TOP_BMODE_LSB) & TOP_TOP_BMODE_MASK)
+#define TOP_TOP_SYNTHON_MSB                      24
+#define TOP_TOP_SYNTHON_LSB                      24
+#define TOP_TOP_SYNTHON_MASK                     0x01000000
+#define TOP_TOP_SYNTHON_GET(x)                   (((x) & TOP_TOP_SYNTHON_MASK) >> TOP_TOP_SYNTHON_LSB)
+#define TOP_TOP_SYNTHON_SET(x)                   (((x) << TOP_TOP_SYNTHON_LSB) & TOP_TOP_SYNTHON_MASK)
+#define TOP_TOP_RXON_MSB                         23
+#define TOP_TOP_RXON_LSB                         23
+#define TOP_TOP_RXON_MASK                        0x00800000
+#define TOP_TOP_RXON_GET(x)                      (((x) & TOP_TOP_RXON_MASK) >> TOP_TOP_RXON_LSB)
+#define TOP_TOP_RXON_SET(x)                      (((x) << TOP_TOP_RXON_LSB) & TOP_TOP_RXON_MASK)
+#define TOP_TOP_TXON_MSB                         22
+#define TOP_TOP_TXON_LSB                         22
+#define TOP_TOP_TXON_MASK                        0x00400000
+#define TOP_TOP_TXON_GET(x)                      (((x) & TOP_TOP_TXON_MASK) >> TOP_TOP_TXON_LSB)
+#define TOP_TOP_TXON_SET(x)                      (((x) << TOP_TOP_TXON_LSB) & TOP_TOP_TXON_MASK)
+#define TOP_TOP_PAON_MSB                         21
+#define TOP_TOP_PAON_LSB                         21
+#define TOP_TOP_PAON_MASK                        0x00200000
+#define TOP_TOP_PAON_GET(x)                      (((x) & TOP_TOP_PAON_MASK) >> TOP_TOP_PAON_LSB)
+#define TOP_TOP_PAON_SET(x)                      (((x) << TOP_TOP_PAON_LSB) & TOP_TOP_PAON_MASK)
+#define TOP_TOP_CALTX_MSB                        20
+#define TOP_TOP_CALTX_LSB                        20
+#define TOP_TOP_CALTX_MASK                       0x00100000
+#define TOP_TOP_CALTX_GET(x)                     (((x) & TOP_TOP_CALTX_MASK) >> TOP_TOP_CALTX_LSB)
+#define TOP_TOP_CALTX_SET(x)                     (((x) << TOP_TOP_CALTX_LSB) & TOP_TOP_CALTX_MASK)
+#define TOP_TOP_LOCALADDAC_MSB                   19
+#define TOP_TOP_LOCALADDAC_LSB                   19
+#define TOP_TOP_LOCALADDAC_MASK                  0x00080000
+#define TOP_TOP_LOCALADDAC_GET(x)                (((x) & TOP_TOP_LOCALADDAC_MASK) >> TOP_TOP_LOCALADDAC_LSB)
+#define TOP_TOP_LOCALADDAC_SET(x)                (((x) << TOP_TOP_LOCALADDAC_LSB) & TOP_TOP_LOCALADDAC_MASK)
+#define TOP_TOP_PWDPLL_MSB                       18
+#define TOP_TOP_PWDPLL_LSB                       18
+#define TOP_TOP_PWDPLL_MASK                      0x00040000
+#define TOP_TOP_PWDPLL_GET(x)                    (((x) & TOP_TOP_PWDPLL_MASK) >> TOP_TOP_PWDPLL_LSB)
+#define TOP_TOP_PWDPLL_SET(x)                    (((x) << TOP_TOP_PWDPLL_LSB) & TOP_TOP_PWDPLL_MASK)
+#define TOP_TOP_PWDADC_MSB                       17
+#define TOP_TOP_PWDADC_LSB                       17
+#define TOP_TOP_PWDADC_MASK                      0x00020000
+#define TOP_TOP_PWDADC_GET(x)                    (((x) & TOP_TOP_PWDADC_MASK) >> TOP_TOP_PWDADC_LSB)
+#define TOP_TOP_PWDADC_SET(x)                    (((x) << TOP_TOP_PWDADC_LSB) & TOP_TOP_PWDADC_MASK)
+#define TOP_TOP_PWDDAC_MSB                       16
+#define TOP_TOP_PWDDAC_LSB                       16
+#define TOP_TOP_PWDDAC_MASK                      0x00010000
+#define TOP_TOP_PWDDAC_GET(x)                    (((x) & TOP_TOP_PWDDAC_MASK) >> TOP_TOP_PWDDAC_LSB)
+#define TOP_TOP_PWDDAC_SET(x)                    (((x) << TOP_TOP_PWDDAC_LSB) & TOP_TOP_PWDDAC_MASK)
+#define TOP_TOP_LOCALXTAL_MSB                    15
+#define TOP_TOP_LOCALXTAL_LSB                    15
+#define TOP_TOP_LOCALXTAL_MASK                   0x00008000
+#define TOP_TOP_LOCALXTAL_GET(x)                 (((x) & TOP_TOP_LOCALXTAL_MASK) >> TOP_TOP_LOCALXTAL_LSB)
+#define TOP_TOP_LOCALXTAL_SET(x)                 (((x) << TOP_TOP_LOCALXTAL_LSB) & TOP_TOP_LOCALXTAL_MASK)
+#define TOP_TOP_PWDCLKIN_MSB                     14
+#define TOP_TOP_PWDCLKIN_LSB                     14
+#define TOP_TOP_PWDCLKIN_MASK                    0x00004000
+#define TOP_TOP_PWDCLKIN_GET(x)                  (((x) & TOP_TOP_PWDCLKIN_MASK) >> TOP_TOP_PWDCLKIN_LSB)
+#define TOP_TOP_PWDCLKIN_SET(x)                  (((x) << TOP_TOP_PWDCLKIN_LSB) & TOP_TOP_PWDCLKIN_MASK)
+#define TOP_TOP_OSCON_MSB                        13
+#define TOP_TOP_OSCON_LSB                        13
+#define TOP_TOP_OSCON_MASK                       0x00002000
+#define TOP_TOP_OSCON_GET(x)                     (((x) & TOP_TOP_OSCON_MASK) >> TOP_TOP_OSCON_LSB)
+#define TOP_TOP_OSCON_SET(x)                     (((x) << TOP_TOP_OSCON_LSB) & TOP_TOP_OSCON_MASK)
+#define TOP_TOP_SCLKEN_FORCE_MSB                 12
+#define TOP_TOP_SCLKEN_FORCE_LSB                 12
+#define TOP_TOP_SCLKEN_FORCE_MASK                0x00001000
+#define TOP_TOP_SCLKEN_FORCE_GET(x)              (((x) & TOP_TOP_SCLKEN_FORCE_MASK) >> TOP_TOP_SCLKEN_FORCE_LSB)
+#define TOP_TOP_SCLKEN_FORCE_SET(x)              (((x) << TOP_TOP_SCLKEN_FORCE_LSB) & TOP_TOP_SCLKEN_FORCE_MASK)
+#define TOP_TOP_SYNTHON_FORCE_MSB                11
+#define TOP_TOP_SYNTHON_FORCE_LSB                11
+#define TOP_TOP_SYNTHON_FORCE_MASK               0x00000800
+#define TOP_TOP_SYNTHON_FORCE_GET(x)             (((x) & TOP_TOP_SYNTHON_FORCE_MASK) >> TOP_TOP_SYNTHON_FORCE_LSB)
+#define TOP_TOP_SYNTHON_FORCE_SET(x)             (((x) << TOP_TOP_SYNTHON_FORCE_LSB) & TOP_TOP_SYNTHON_FORCE_MASK)
+#define TOP_TOP_PDBIAS_MSB                       10
+#define TOP_TOP_PDBIAS_LSB                       10
+#define TOP_TOP_PDBIAS_MASK                      0x00000400
+#define TOP_TOP_PDBIAS_GET(x)                    (((x) & TOP_TOP_PDBIAS_MASK) >> TOP_TOP_PDBIAS_LSB)
+#define TOP_TOP_PDBIAS_SET(x)                    (((x) << TOP_TOP_PDBIAS_LSB) & TOP_TOP_PDBIAS_MASK)
+#define TOP_TOP_DATAOUTSEL_MSB                   9
+#define TOP_TOP_DATAOUTSEL_LSB                   8
+#define TOP_TOP_DATAOUTSEL_MASK                  0x00000300
+#define TOP_TOP_DATAOUTSEL_GET(x)                (((x) & TOP_TOP_DATAOUTSEL_MASK) >> TOP_TOP_DATAOUTSEL_LSB)
+#define TOP_TOP_DATAOUTSEL_SET(x)                (((x) << TOP_TOP_DATAOUTSEL_LSB) & TOP_TOP_DATAOUTSEL_MASK)
+#define TOP_TOP_REVID_MSB                        7
+#define TOP_TOP_REVID_LSB                        5
+#define TOP_TOP_REVID_MASK                       0x000000e0
+#define TOP_TOP_REVID_GET(x)                     (((x) & TOP_TOP_REVID_MASK) >> TOP_TOP_REVID_LSB)
+#define TOP_TOP_REVID_SET(x)                     (((x) << TOP_TOP_REVID_LSB) & TOP_TOP_REVID_MASK)
+#define TOP_TOP_INT2PAD_MSB                      4
+#define TOP_TOP_INT2PAD_LSB                      4
+#define TOP_TOP_INT2PAD_MASK                     0x00000010
+#define TOP_TOP_INT2PAD_GET(x)                   (((x) & TOP_TOP_INT2PAD_MASK) >> TOP_TOP_INT2PAD_LSB)
+#define TOP_TOP_INT2PAD_SET(x)                   (((x) << TOP_TOP_INT2PAD_LSB) & TOP_TOP_INT2PAD_MASK)
+#define TOP_TOP_INTH2PAD_MSB                     3
+#define TOP_TOP_INTH2PAD_LSB                     3
+#define TOP_TOP_INTH2PAD_MASK                    0x00000008
+#define TOP_TOP_INTH2PAD_GET(x)                  (((x) & TOP_TOP_INTH2PAD_MASK) >> TOP_TOP_INTH2PAD_LSB)
+#define TOP_TOP_INTH2PAD_SET(x)                  (((x) << TOP_TOP_INTH2PAD_LSB) & TOP_TOP_INTH2PAD_MASK)
+#define TOP_TOP_PAD2GND_MSB                      2
+#define TOP_TOP_PAD2GND_LSB                      2
+#define TOP_TOP_PAD2GND_MASK                     0x00000004
+#define TOP_TOP_PAD2GND_GET(x)                   (((x) & TOP_TOP_PAD2GND_MASK) >> TOP_TOP_PAD2GND_LSB)
+#define TOP_TOP_PAD2GND_SET(x)                   (((x) << TOP_TOP_PAD2GND_LSB) & TOP_TOP_PAD2GND_MASK)
+#define TOP_TOP_INT2GND_MSB                      1
+#define TOP_TOP_INT2GND_LSB                      1
+#define TOP_TOP_INT2GND_MASK                     0x00000002
+#define TOP_TOP_INT2GND_GET(x)                   (((x) & TOP_TOP_INT2GND_MASK) >> TOP_TOP_INT2GND_LSB)
+#define TOP_TOP_INT2GND_SET(x)                   (((x) << TOP_TOP_INT2GND_LSB) & TOP_TOP_INT2GND_MASK)
+#define TOP_TOP_FORCE_XPAON_MSB                  0
+#define TOP_TOP_FORCE_XPAON_LSB                  0
+#define TOP_TOP_FORCE_XPAON_MASK                 0x00000001
+#define TOP_TOP_FORCE_XPAON_GET(x)               (((x) & TOP_TOP_FORCE_XPAON_MASK) >> TOP_TOP_FORCE_XPAON_LSB)
+#define TOP_TOP_FORCE_XPAON_SET(x)               (((x) << TOP_TOP_FORCE_XPAON_LSB) & TOP_TOP_FORCE_XPAON_MASK)
+
+#define BIAS_BIAS_SEL_ADDRESS                    0x00000038
+#define BIAS_BIAS_SEL_OFFSET                     0x00000038
+#define BIAS_BIAS_SEL_PADON_MSB                  31
+#define BIAS_BIAS_SEL_PADON_LSB                  31
+#define BIAS_BIAS_SEL_PADON_MASK                 0x80000000
+#define BIAS_BIAS_SEL_PADON_GET(x)               (((x) & BIAS_BIAS_SEL_PADON_MASK) >> BIAS_BIAS_SEL_PADON_LSB)
+#define BIAS_BIAS_SEL_PADON_SET(x)               (((x) << BIAS_BIAS_SEL_PADON_LSB) & BIAS_BIAS_SEL_PADON_MASK)
+#define BIAS_BIAS_SEL_SEL_BIAS_MSB               30
+#define BIAS_BIAS_SEL_SEL_BIAS_LSB               25
+#define BIAS_BIAS_SEL_SEL_BIAS_MASK              0x7e000000
+#define BIAS_BIAS_SEL_SEL_BIAS_GET(x)            (((x) & BIAS_BIAS_SEL_SEL_BIAS_MASK) >> BIAS_BIAS_SEL_SEL_BIAS_LSB)
+#define BIAS_BIAS_SEL_SEL_BIAS_SET(x)            (((x) << BIAS_BIAS_SEL_SEL_BIAS_LSB) & BIAS_BIAS_SEL_SEL_BIAS_MASK)
+#define BIAS_BIAS_SEL_SEL_SPARE_MSB              24
+#define BIAS_BIAS_SEL_SEL_SPARE_LSB              21
+#define BIAS_BIAS_SEL_SEL_SPARE_MASK             0x01e00000
+#define BIAS_BIAS_SEL_SEL_SPARE_GET(x)           (((x) & BIAS_BIAS_SEL_SEL_SPARE_MASK) >> BIAS_BIAS_SEL_SEL_SPARE_LSB)
+#define BIAS_BIAS_SEL_SEL_SPARE_SET(x)           (((x) << BIAS_BIAS_SEL_SEL_SPARE_LSB) & BIAS_BIAS_SEL_SEL_SPARE_MASK)
+#define BIAS_BIAS_SEL_SPARE_MSB                  20
+#define BIAS_BIAS_SEL_SPARE_LSB                  20
+#define BIAS_BIAS_SEL_SPARE_MASK                 0x00100000
+#define BIAS_BIAS_SEL_SPARE_GET(x)               (((x) & BIAS_BIAS_SEL_SPARE_MASK) >> BIAS_BIAS_SEL_SPARE_LSB)
+#define BIAS_BIAS_SEL_SPARE_SET(x)               (((x) << BIAS_BIAS_SEL_SPARE_LSB) & BIAS_BIAS_SEL_SPARE_MASK)
+#define BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_MSB   19
+#define BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_LSB   17
+#define BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_MASK  0x000e0000
+#define BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_MASK) >> BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_LSB)
+#define BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_LSB) & BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_MASK)
+#define BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_MSB    16
+#define BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_LSB    16
+#define BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_MASK   0x00010000
+#define BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_GET(x) (((x) & BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_MASK) >> BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_LSB)
+#define BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_SET(x) (((x) << BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_LSB) & BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_MASK)
+#define BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_MSB 15
+#define BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_LSB 15
+#define BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_MASK 0x00008000
+#define BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_GET(x) (((x) & BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_MASK) >> BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_LSB)
+#define BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_SET(x) (((x) << BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_LSB) & BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_MASK)
+#define BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_MSB   14
+#define BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_LSB   14
+#define BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_MASK  0x00004000
+#define BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_MASK) >> BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_LSB)
+#define BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_LSB) & BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_MASK)
+#define BIAS_BIAS_SEL_PWD_ICCPLL25_MSB           13
+#define BIAS_BIAS_SEL_PWD_ICCPLL25_LSB           13
+#define BIAS_BIAS_SEL_PWD_ICCPLL25_MASK          0x00002000
+#define BIAS_BIAS_SEL_PWD_ICCPLL25_GET(x)        (((x) & BIAS_BIAS_SEL_PWD_ICCPLL25_MASK) >> BIAS_BIAS_SEL_PWD_ICCPLL25_LSB)
+#define BIAS_BIAS_SEL_PWD_ICCPLL25_SET(x)        (((x) << BIAS_BIAS_SEL_PWD_ICCPLL25_LSB) & BIAS_BIAS_SEL_PWD_ICCPLL25_MASK)
+#define BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_MSB       12
+#define BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_LSB       10
+#define BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_MASK      0x00001c00
+#define BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_GET(x)    (((x) & BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_MASK) >> BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_LSB)
+#define BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_SET(x)    (((x) << BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_LSB) & BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_MASK)
+#define BIAS_BIAS_SEL_PWD_ICXTAL25_MSB           9
+#define BIAS_BIAS_SEL_PWD_ICXTAL25_LSB           7
+#define BIAS_BIAS_SEL_PWD_ICXTAL25_MASK          0x00000380
+#define BIAS_BIAS_SEL_PWD_ICXTAL25_GET(x)        (((x) & BIAS_BIAS_SEL_PWD_ICXTAL25_MASK) >> BIAS_BIAS_SEL_PWD_ICXTAL25_LSB)
+#define BIAS_BIAS_SEL_PWD_ICXTAL25_SET(x)        (((x) << BIAS_BIAS_SEL_PWD_ICXTAL25_LSB) & BIAS_BIAS_SEL_PWD_ICXTAL25_MASK)
+#define BIAS_BIAS_SEL_PWD_ICTSENS25_MSB          6
+#define BIAS_BIAS_SEL_PWD_ICTSENS25_LSB          4
+#define BIAS_BIAS_SEL_PWD_ICTSENS25_MASK         0x00000070
+#define BIAS_BIAS_SEL_PWD_ICTSENS25_GET(x)       (((x) & BIAS_BIAS_SEL_PWD_ICTSENS25_MASK) >> BIAS_BIAS_SEL_PWD_ICTSENS25_LSB)
+#define BIAS_BIAS_SEL_PWD_ICTSENS25_SET(x)       (((x) << BIAS_BIAS_SEL_PWD_ICTSENS25_LSB) & BIAS_BIAS_SEL_PWD_ICTSENS25_MASK)
+#define BIAS_BIAS_SEL_PWD_ICTXPC25_MSB           3
+#define BIAS_BIAS_SEL_PWD_ICTXPC25_LSB           1
+#define BIAS_BIAS_SEL_PWD_ICTXPC25_MASK          0x0000000e
+#define BIAS_BIAS_SEL_PWD_ICTXPC25_GET(x)        (((x) & BIAS_BIAS_SEL_PWD_ICTXPC25_MASK) >> BIAS_BIAS_SEL_PWD_ICTXPC25_LSB)
+#define BIAS_BIAS_SEL_PWD_ICTXPC25_SET(x)        (((x) << BIAS_BIAS_SEL_PWD_ICTXPC25_LSB) & BIAS_BIAS_SEL_PWD_ICTXPC25_MASK)
+#define BIAS_BIAS_SEL_PWD_ICLDO25_MSB            0
+#define BIAS_BIAS_SEL_PWD_ICLDO25_LSB            0
+#define BIAS_BIAS_SEL_PWD_ICLDO25_MASK           0x00000001
+#define BIAS_BIAS_SEL_PWD_ICLDO25_GET(x)         (((x) & BIAS_BIAS_SEL_PWD_ICLDO25_MASK) >> BIAS_BIAS_SEL_PWD_ICLDO25_LSB)
+#define BIAS_BIAS_SEL_PWD_ICLDO25_SET(x)         (((x) << BIAS_BIAS_SEL_PWD_ICLDO25_LSB) & BIAS_BIAS_SEL_PWD_ICLDO25_MASK)
+
+#define BIAS_BIAS1_ADDRESS                       0x0000003c
+#define BIAS_BIAS1_OFFSET                        0x0000003c
+#define BIAS_BIAS1_PWD_ICDAC2BB25_MSB            31
+#define BIAS_BIAS1_PWD_ICDAC2BB25_LSB            29
+#define BIAS_BIAS1_PWD_ICDAC2BB25_MASK           0xe0000000
+#define BIAS_BIAS1_PWD_ICDAC2BB25_GET(x)         (((x) & BIAS_BIAS1_PWD_ICDAC2BB25_MASK) >> BIAS_BIAS1_PWD_ICDAC2BB25_LSB)
+#define BIAS_BIAS1_PWD_ICDAC2BB25_SET(x)         (((x) << BIAS_BIAS1_PWD_ICDAC2BB25_LSB) & BIAS_BIAS1_PWD_ICDAC2BB25_MASK)
+#define BIAS_BIAS1_PWD_IC2GVGM25_MSB             28
+#define BIAS_BIAS1_PWD_IC2GVGM25_LSB             26
+#define BIAS_BIAS1_PWD_IC2GVGM25_MASK            0x1c000000
+#define BIAS_BIAS1_PWD_IC2GVGM25_GET(x)          (((x) & BIAS_BIAS1_PWD_IC2GVGM25_MASK) >> BIAS_BIAS1_PWD_IC2GVGM25_LSB)
+#define BIAS_BIAS1_PWD_IC2GVGM25_SET(x)          (((x) << BIAS_BIAS1_PWD_IC2GVGM25_LSB) & BIAS_BIAS1_PWD_IC2GVGM25_MASK)
+#define BIAS_BIAS1_PWD_IC2GRFFE25_MSB            25
+#define BIAS_BIAS1_PWD_IC2GRFFE25_LSB            23
+#define BIAS_BIAS1_PWD_IC2GRFFE25_MASK           0x03800000
+#define BIAS_BIAS1_PWD_IC2GRFFE25_GET(x)         (((x) & BIAS_BIAS1_PWD_IC2GRFFE25_MASK) >> BIAS_BIAS1_PWD_IC2GRFFE25_LSB)
+#define BIAS_BIAS1_PWD_IC2GRFFE25_SET(x)         (((x) << BIAS_BIAS1_PWD_IC2GRFFE25_LSB) & BIAS_BIAS1_PWD_IC2GRFFE25_MASK)
+#define BIAS_BIAS1_PWD_IC2GLOREG25_MSB           22
+#define BIAS_BIAS1_PWD_IC2GLOREG25_LSB           20
+#define BIAS_BIAS1_PWD_IC2GLOREG25_MASK          0x00700000
+#define BIAS_BIAS1_PWD_IC2GLOREG25_GET(x)        (((x) & BIAS_BIAS1_PWD_IC2GLOREG25_MASK) >> BIAS_BIAS1_PWD_IC2GLOREG25_LSB)
+#define BIAS_BIAS1_PWD_IC2GLOREG25_SET(x)        (((x) << BIAS_BIAS1_PWD_IC2GLOREG25_LSB) & BIAS_BIAS1_PWD_IC2GLOREG25_MASK)
+#define BIAS_BIAS1_PWD_IC2GLNAREG25_MSB          19
+#define BIAS_BIAS1_PWD_IC2GLNAREG25_LSB          17
+#define BIAS_BIAS1_PWD_IC2GLNAREG25_MASK         0x000e0000
+#define BIAS_BIAS1_PWD_IC2GLNAREG25_GET(x)       (((x) & BIAS_BIAS1_PWD_IC2GLNAREG25_MASK) >> BIAS_BIAS1_PWD_IC2GLNAREG25_LSB)
+#define BIAS_BIAS1_PWD_IC2GLNAREG25_SET(x)       (((x) << BIAS_BIAS1_PWD_IC2GLNAREG25_LSB) & BIAS_BIAS1_PWD_IC2GLNAREG25_MASK)
+#define BIAS_BIAS1_PWD_ICDETECTORB25_MSB         16
+#define BIAS_BIAS1_PWD_ICDETECTORB25_LSB         16
+#define BIAS_BIAS1_PWD_ICDETECTORB25_MASK        0x00010000
+#define BIAS_BIAS1_PWD_ICDETECTORB25_GET(x)      (((x) & BIAS_BIAS1_PWD_ICDETECTORB25_MASK) >> BIAS_BIAS1_PWD_ICDETECTORB25_LSB)
+#define BIAS_BIAS1_PWD_ICDETECTORB25_SET(x)      (((x) << BIAS_BIAS1_PWD_ICDETECTORB25_LSB) & BIAS_BIAS1_PWD_ICDETECTORB25_MASK)
+#define BIAS_BIAS1_PWD_ICDETECTORA25_MSB         15
+#define BIAS_BIAS1_PWD_ICDETECTORA25_LSB         15
+#define BIAS_BIAS1_PWD_ICDETECTORA25_MASK        0x00008000
+#define BIAS_BIAS1_PWD_ICDETECTORA25_GET(x)      (((x) & BIAS_BIAS1_PWD_ICDETECTORA25_MASK) >> BIAS_BIAS1_PWD_ICDETECTORA25_LSB)
+#define BIAS_BIAS1_PWD_ICDETECTORA25_SET(x)      (((x) << BIAS_BIAS1_PWD_ICDETECTORA25_LSB) & BIAS_BIAS1_PWD_ICDETECTORA25_MASK)
+#define BIAS_BIAS1_PWD_IC5GRXRF25_MSB            14
+#define BIAS_BIAS1_PWD_IC5GRXRF25_LSB            14
+#define BIAS_BIAS1_PWD_IC5GRXRF25_MASK           0x00004000
+#define BIAS_BIAS1_PWD_IC5GRXRF25_GET(x)         (((x) & BIAS_BIAS1_PWD_IC5GRXRF25_MASK) >> BIAS_BIAS1_PWD_IC5GRXRF25_LSB)
+#define BIAS_BIAS1_PWD_IC5GRXRF25_SET(x)         (((x) << BIAS_BIAS1_PWD_IC5GRXRF25_LSB) & BIAS_BIAS1_PWD_IC5GRXRF25_MASK)
+#define BIAS_BIAS1_PWD_IC5GTXPA25_MSB            13
+#define BIAS_BIAS1_PWD_IC5GTXPA25_LSB            11
+#define BIAS_BIAS1_PWD_IC5GTXPA25_MASK           0x00003800
+#define BIAS_BIAS1_PWD_IC5GTXPA25_GET(x)         (((x) & BIAS_BIAS1_PWD_IC5GTXPA25_MASK) >> BIAS_BIAS1_PWD_IC5GTXPA25_LSB)
+#define BIAS_BIAS1_PWD_IC5GTXPA25_SET(x)         (((x) << BIAS_BIAS1_PWD_IC5GTXPA25_LSB) & BIAS_BIAS1_PWD_IC5GTXPA25_MASK)
+#define BIAS_BIAS1_PWD_IC5GTXBUF25_MSB           10
+#define BIAS_BIAS1_PWD_IC5GTXBUF25_LSB           8
+#define BIAS_BIAS1_PWD_IC5GTXBUF25_MASK          0x00000700
+#define BIAS_BIAS1_PWD_IC5GTXBUF25_GET(x)        (((x) & BIAS_BIAS1_PWD_IC5GTXBUF25_MASK) >> BIAS_BIAS1_PWD_IC5GTXBUF25_LSB)
+#define BIAS_BIAS1_PWD_IC5GTXBUF25_SET(x)        (((x) << BIAS_BIAS1_PWD_IC5GTXBUF25_LSB) & BIAS_BIAS1_PWD_IC5GTXBUF25_MASK)
+#define BIAS_BIAS1_PWD_IC5GQB25_MSB              7
+#define BIAS_BIAS1_PWD_IC5GQB25_LSB              5
+#define BIAS_BIAS1_PWD_IC5GQB25_MASK             0x000000e0
+#define BIAS_BIAS1_PWD_IC5GQB25_GET(x)           (((x) & BIAS_BIAS1_PWD_IC5GQB25_MASK) >> BIAS_BIAS1_PWD_IC5GQB25_LSB)
+#define BIAS_BIAS1_PWD_IC5GQB25_SET(x)           (((x) << BIAS_BIAS1_PWD_IC5GQB25_LSB) & BIAS_BIAS1_PWD_IC5GQB25_MASK)
+#define BIAS_BIAS1_PWD_IC5GMIXQ25_MSB            4
+#define BIAS_BIAS1_PWD_IC5GMIXQ25_LSB            2
+#define BIAS_BIAS1_PWD_IC5GMIXQ25_MASK           0x0000001c
+#define BIAS_BIAS1_PWD_IC5GMIXQ25_GET(x)         (((x) & BIAS_BIAS1_PWD_IC5GMIXQ25_MASK) >> BIAS_BIAS1_PWD_IC5GMIXQ25_LSB)
+#define BIAS_BIAS1_PWD_IC5GMIXQ25_SET(x)         (((x) << BIAS_BIAS1_PWD_IC5GMIXQ25_LSB) & BIAS_BIAS1_PWD_IC5GMIXQ25_MASK)
+#define BIAS_BIAS1_SPARE_MSB                     1
+#define BIAS_BIAS1_SPARE_LSB                     0
+#define BIAS_BIAS1_SPARE_MASK                    0x00000003
+#define BIAS_BIAS1_SPARE_GET(x)                  (((x) & BIAS_BIAS1_SPARE_MASK) >> BIAS_BIAS1_SPARE_LSB)
+#define BIAS_BIAS1_SPARE_SET(x)                  (((x) << BIAS_BIAS1_SPARE_LSB) & BIAS_BIAS1_SPARE_MASK)
+
+#define BIAS_BIAS2_ADDRESS                       0x00000040
+#define BIAS_BIAS2_OFFSET                        0x00000040
+#define BIAS_BIAS2_PWD_IC5GMIXI25_MSB            31
+#define BIAS_BIAS2_PWD_IC5GMIXI25_LSB            29
+#define BIAS_BIAS2_PWD_IC5GMIXI25_MASK           0xe0000000
+#define BIAS_BIAS2_PWD_IC5GMIXI25_GET(x)         (((x) & BIAS_BIAS2_PWD_IC5GMIXI25_MASK) >> BIAS_BIAS2_PWD_IC5GMIXI25_LSB)
+#define BIAS_BIAS2_PWD_IC5GMIXI25_SET(x)         (((x) << BIAS_BIAS2_PWD_IC5GMIXI25_LSB) & BIAS_BIAS2_PWD_IC5GMIXI25_MASK)
+#define BIAS_BIAS2_PWD_IC5GDIV25_MSB             28
+#define BIAS_BIAS2_PWD_IC5GDIV25_LSB             26
+#define BIAS_BIAS2_PWD_IC5GDIV25_MASK            0x1c000000
+#define BIAS_BIAS2_PWD_IC5GDIV25_GET(x)          (((x) & BIAS_BIAS2_PWD_IC5GDIV25_MASK) >> BIAS_BIAS2_PWD_IC5GDIV25_LSB)
+#define BIAS_BIAS2_PWD_IC5GDIV25_SET(x)          (((x) << BIAS_BIAS2_PWD_IC5GDIV25_LSB) & BIAS_BIAS2_PWD_IC5GDIV25_MASK)
+#define BIAS_BIAS2_PWD_IC5GLOREG25_MSB           25
+#define BIAS_BIAS2_PWD_IC5GLOREG25_LSB           23
+#define BIAS_BIAS2_PWD_IC5GLOREG25_MASK          0x03800000
+#define BIAS_BIAS2_PWD_IC5GLOREG25_GET(x)        (((x) & BIAS_BIAS2_PWD_IC5GLOREG25_MASK) >> BIAS_BIAS2_PWD_IC5GLOREG25_LSB)
+#define BIAS_BIAS2_PWD_IC5GLOREG25_SET(x)        (((x) << BIAS_BIAS2_PWD_IC5GLOREG25_LSB) & BIAS_BIAS2_PWD_IC5GLOREG25_MASK)
+#define BIAS_BIAS2_PWD_IRPLL25_MSB               22
+#define BIAS_BIAS2_PWD_IRPLL25_LSB               22
+#define BIAS_BIAS2_PWD_IRPLL25_MASK              0x00400000
+#define BIAS_BIAS2_PWD_IRPLL25_GET(x)            (((x) & BIAS_BIAS2_PWD_IRPLL25_MASK) >> BIAS_BIAS2_PWD_IRPLL25_LSB)
+#define BIAS_BIAS2_PWD_IRPLL25_SET(x)            (((x) << BIAS_BIAS2_PWD_IRPLL25_LSB) & BIAS_BIAS2_PWD_IRPLL25_MASK)
+#define BIAS_BIAS2_PWD_IRXTAL25_MSB              21
+#define BIAS_BIAS2_PWD_IRXTAL25_LSB              19
+#define BIAS_BIAS2_PWD_IRXTAL25_MASK             0x00380000
+#define BIAS_BIAS2_PWD_IRXTAL25_GET(x)           (((x) & BIAS_BIAS2_PWD_IRXTAL25_MASK) >> BIAS_BIAS2_PWD_IRXTAL25_LSB)
+#define BIAS_BIAS2_PWD_IRXTAL25_SET(x)           (((x) << BIAS_BIAS2_PWD_IRXTAL25_LSB) & BIAS_BIAS2_PWD_IRXTAL25_MASK)
+#define BIAS_BIAS2_PWD_IRTSENS25_MSB             18
+#define BIAS_BIAS2_PWD_IRTSENS25_LSB             16
+#define BIAS_BIAS2_PWD_IRTSENS25_MASK            0x00070000
+#define BIAS_BIAS2_PWD_IRTSENS25_GET(x)          (((x) & BIAS_BIAS2_PWD_IRTSENS25_MASK) >> BIAS_BIAS2_PWD_IRTSENS25_LSB)
+#define BIAS_BIAS2_PWD_IRTSENS25_SET(x)          (((x) << BIAS_BIAS2_PWD_IRTSENS25_LSB) & BIAS_BIAS2_PWD_IRTSENS25_MASK)
+#define BIAS_BIAS2_PWD_IRTXPC25_MSB              15
+#define BIAS_BIAS2_PWD_IRTXPC25_LSB              13
+#define BIAS_BIAS2_PWD_IRTXPC25_MASK             0x0000e000
+#define BIAS_BIAS2_PWD_IRTXPC25_GET(x)           (((x) & BIAS_BIAS2_PWD_IRTXPC25_MASK) >> BIAS_BIAS2_PWD_IRTXPC25_LSB)
+#define BIAS_BIAS2_PWD_IRTXPC25_SET(x)           (((x) << BIAS_BIAS2_PWD_IRTXPC25_LSB) & BIAS_BIAS2_PWD_IRTXPC25_MASK)
+#define BIAS_BIAS2_PWD_IRLDO25_MSB               12
+#define BIAS_BIAS2_PWD_IRLDO25_LSB               12
+#define BIAS_BIAS2_PWD_IRLDO25_MASK              0x00001000
+#define BIAS_BIAS2_PWD_IRLDO25_GET(x)            (((x) & BIAS_BIAS2_PWD_IRLDO25_MASK) >> BIAS_BIAS2_PWD_IRLDO25_LSB)
+#define BIAS_BIAS2_PWD_IRLDO25_SET(x)            (((x) << BIAS_BIAS2_PWD_IRLDO25_LSB) & BIAS_BIAS2_PWD_IRLDO25_MASK)
+#define BIAS_BIAS2_PWD_IR2GTXMIX25_MSB           11
+#define BIAS_BIAS2_PWD_IR2GTXMIX25_LSB           9
+#define BIAS_BIAS2_PWD_IR2GTXMIX25_MASK          0x00000e00
+#define BIAS_BIAS2_PWD_IR2GTXMIX25_GET(x)        (((x) & BIAS_BIAS2_PWD_IR2GTXMIX25_MASK) >> BIAS_BIAS2_PWD_IR2GTXMIX25_LSB)
+#define BIAS_BIAS2_PWD_IR2GTXMIX25_SET(x)        (((x) << BIAS_BIAS2_PWD_IR2GTXMIX25_LSB) & BIAS_BIAS2_PWD_IR2GTXMIX25_MASK)
+#define BIAS_BIAS2_PWD_IR2GLOREG25_MSB           8
+#define BIAS_BIAS2_PWD_IR2GLOREG25_LSB           6
+#define BIAS_BIAS2_PWD_IR2GLOREG25_MASK          0x000001c0
+#define BIAS_BIAS2_PWD_IR2GLOREG25_GET(x)        (((x) & BIAS_BIAS2_PWD_IR2GLOREG25_MASK) >> BIAS_BIAS2_PWD_IR2GLOREG25_LSB)
+#define BIAS_BIAS2_PWD_IR2GLOREG25_SET(x)        (((x) << BIAS_BIAS2_PWD_IR2GLOREG25_LSB) & BIAS_BIAS2_PWD_IR2GLOREG25_MASK)
+#define BIAS_BIAS2_PWD_IR2GLNAREG25_MSB          5
+#define BIAS_BIAS2_PWD_IR2GLNAREG25_LSB          3
+#define BIAS_BIAS2_PWD_IR2GLNAREG25_MASK         0x00000038
+#define BIAS_BIAS2_PWD_IR2GLNAREG25_GET(x)       (((x) & BIAS_BIAS2_PWD_IR2GLNAREG25_MASK) >> BIAS_BIAS2_PWD_IR2GLNAREG25_LSB)
+#define BIAS_BIAS2_PWD_IR2GLNAREG25_SET(x)       (((x) << BIAS_BIAS2_PWD_IR2GLNAREG25_LSB) & BIAS_BIAS2_PWD_IR2GLNAREG25_MASK)
+#define BIAS_BIAS2_PWD_IR5GRFVREF2525_MSB        2
+#define BIAS_BIAS2_PWD_IR5GRFVREF2525_LSB        0
+#define BIAS_BIAS2_PWD_IR5GRFVREF2525_MASK       0x00000007
+#define BIAS_BIAS2_PWD_IR5GRFVREF2525_GET(x)     (((x) & BIAS_BIAS2_PWD_IR5GRFVREF2525_MASK) >> BIAS_BIAS2_PWD_IR5GRFVREF2525_LSB)
+#define BIAS_BIAS2_PWD_IR5GRFVREF2525_SET(x)     (((x) << BIAS_BIAS2_PWD_IR5GRFVREF2525_LSB) & BIAS_BIAS2_PWD_IR5GRFVREF2525_MASK)
+
+#define BIAS_BIAS3_ADDRESS                       0x00000044
+#define BIAS_BIAS3_OFFSET                        0x00000044
+#define BIAS_BIAS3_PWD_IR5GTXMIX25_MSB           31
+#define BIAS_BIAS3_PWD_IR5GTXMIX25_LSB           29
+#define BIAS_BIAS3_PWD_IR5GTXMIX25_MASK          0xe0000000
+#define BIAS_BIAS3_PWD_IR5GTXMIX25_GET(x)        (((x) & BIAS_BIAS3_PWD_IR5GTXMIX25_MASK) >> BIAS_BIAS3_PWD_IR5GTXMIX25_LSB)
+#define BIAS_BIAS3_PWD_IR5GTXMIX25_SET(x)        (((x) << BIAS_BIAS3_PWD_IR5GTXMIX25_LSB) & BIAS_BIAS3_PWD_IR5GTXMIX25_MASK)
+#define BIAS_BIAS3_PWD_IR5GAGC25_MSB             28
+#define BIAS_BIAS3_PWD_IR5GAGC25_LSB             26
+#define BIAS_BIAS3_PWD_IR5GAGC25_MASK            0x1c000000
+#define BIAS_BIAS3_PWD_IR5GAGC25_GET(x)          (((x) & BIAS_BIAS3_PWD_IR5GAGC25_MASK) >> BIAS_BIAS3_PWD_IR5GAGC25_LSB)
+#define BIAS_BIAS3_PWD_IR5GAGC25_SET(x)          (((x) << BIAS_BIAS3_PWD_IR5GAGC25_LSB) & BIAS_BIAS3_PWD_IR5GAGC25_MASK)
+#define BIAS_BIAS3_PWD_ICDAC50_MSB               25
+#define BIAS_BIAS3_PWD_ICDAC50_LSB               23
+#define BIAS_BIAS3_PWD_ICDAC50_MASK              0x03800000
+#define BIAS_BIAS3_PWD_ICDAC50_GET(x)            (((x) & BIAS_BIAS3_PWD_ICDAC50_MASK) >> BIAS_BIAS3_PWD_ICDAC50_LSB)
+#define BIAS_BIAS3_PWD_ICDAC50_SET(x)            (((x) << BIAS_BIAS3_PWD_ICDAC50_LSB) & BIAS_BIAS3_PWD_ICDAC50_MASK)
+#define BIAS_BIAS3_PWD_ICSYNTH50_MSB             22
+#define BIAS_BIAS3_PWD_ICSYNTH50_LSB             22
+#define BIAS_BIAS3_PWD_ICSYNTH50_MASK            0x00400000
+#define BIAS_BIAS3_PWD_ICSYNTH50_GET(x)          (((x) & BIAS_BIAS3_PWD_ICSYNTH50_MASK) >> BIAS_BIAS3_PWD_ICSYNTH50_LSB)
+#define BIAS_BIAS3_PWD_ICSYNTH50_SET(x)          (((x) << BIAS_BIAS3_PWD_ICSYNTH50_LSB) & BIAS_BIAS3_PWD_ICSYNTH50_MASK)
+#define BIAS_BIAS3_PWD_ICBB50_MSB                21
+#define BIAS_BIAS3_PWD_ICBB50_LSB                21
+#define BIAS_BIAS3_PWD_ICBB50_MASK               0x00200000
+#define BIAS_BIAS3_PWD_ICBB50_GET(x)             (((x) & BIAS_BIAS3_PWD_ICBB50_MASK) >> BIAS_BIAS3_PWD_ICBB50_LSB)
+#define BIAS_BIAS3_PWD_ICBB50_SET(x)             (((x) << BIAS_BIAS3_PWD_ICBB50_LSB) & BIAS_BIAS3_PWD_ICBB50_MASK)
+#define BIAS_BIAS3_PWD_IC2GDIV50_MSB             20
+#define BIAS_BIAS3_PWD_IC2GDIV50_LSB             18
+#define BIAS_BIAS3_PWD_IC2GDIV50_MASK            0x001c0000
+#define BIAS_BIAS3_PWD_IC2GDIV50_GET(x)          (((x) & BIAS_BIAS3_PWD_IC2GDIV50_MASK) >> BIAS_BIAS3_PWD_IC2GDIV50_LSB)
+#define BIAS_BIAS3_PWD_IC2GDIV50_SET(x)          (((x) << BIAS_BIAS3_PWD_IC2GDIV50_LSB) & BIAS_BIAS3_PWD_IC2GDIV50_MASK)
+#define BIAS_BIAS3_PWD_IRSYNTH50_MSB             17
+#define BIAS_BIAS3_PWD_IRSYNTH50_LSB             17
+#define BIAS_BIAS3_PWD_IRSYNTH50_MASK            0x00020000
+#define BIAS_BIAS3_PWD_IRSYNTH50_GET(x)          (((x) & BIAS_BIAS3_PWD_IRSYNTH50_MASK) >> BIAS_BIAS3_PWD_IRSYNTH50_LSB)
+#define BIAS_BIAS3_PWD_IRSYNTH50_SET(x)          (((x) << BIAS_BIAS3_PWD_IRSYNTH50_LSB) & BIAS_BIAS3_PWD_IRSYNTH50_MASK)
+#define BIAS_BIAS3_PWD_IRBB50_MSB                16
+#define BIAS_BIAS3_PWD_IRBB50_LSB                16
+#define BIAS_BIAS3_PWD_IRBB50_MASK               0x00010000
+#define BIAS_BIAS3_PWD_IRBB50_GET(x)             (((x) & BIAS_BIAS3_PWD_IRBB50_MASK) >> BIAS_BIAS3_PWD_IRBB50_LSB)
+#define BIAS_BIAS3_PWD_IRBB50_SET(x)             (((x) << BIAS_BIAS3_PWD_IRBB50_LSB) & BIAS_BIAS3_PWD_IRBB50_MASK)
+#define BIAS_BIAS3_PWD_IC25SPARE1_MSB            15
+#define BIAS_BIAS3_PWD_IC25SPARE1_LSB            13
+#define BIAS_BIAS3_PWD_IC25SPARE1_MASK           0x0000e000
+#define BIAS_BIAS3_PWD_IC25SPARE1_GET(x)         (((x) & BIAS_BIAS3_PWD_IC25SPARE1_MASK) >> BIAS_BIAS3_PWD_IC25SPARE1_LSB)
+#define BIAS_BIAS3_PWD_IC25SPARE1_SET(x)         (((x) << BIAS_BIAS3_PWD_IC25SPARE1_LSB) & BIAS_BIAS3_PWD_IC25SPARE1_MASK)
+#define BIAS_BIAS3_PWD_IC25SPARE2_MSB            12
+#define BIAS_BIAS3_PWD_IC25SPARE2_LSB            10
+#define BIAS_BIAS3_PWD_IC25SPARE2_MASK           0x00001c00
+#define BIAS_BIAS3_PWD_IC25SPARE2_GET(x)         (((x) & BIAS_BIAS3_PWD_IC25SPARE2_MASK) >> BIAS_BIAS3_PWD_IC25SPARE2_LSB)
+#define BIAS_BIAS3_PWD_IC25SPARE2_SET(x)         (((x) << BIAS_BIAS3_PWD_IC25SPARE2_LSB) & BIAS_BIAS3_PWD_IC25SPARE2_MASK)
+#define BIAS_BIAS3_PWD_IR25SPARE1_MSB            9
+#define BIAS_BIAS3_PWD_IR25SPARE1_LSB            7
+#define BIAS_BIAS3_PWD_IR25SPARE1_MASK           0x00000380
+#define BIAS_BIAS3_PWD_IR25SPARE1_GET(x)         (((x) & BIAS_BIAS3_PWD_IR25SPARE1_MASK) >> BIAS_BIAS3_PWD_IR25SPARE1_LSB)
+#define BIAS_BIAS3_PWD_IR25SPARE1_SET(x)         (((x) << BIAS_BIAS3_PWD_IR25SPARE1_LSB) & BIAS_BIAS3_PWD_IR25SPARE1_MASK)
+#define BIAS_BIAS3_PWD_IR25SPARE2_MSB            6
+#define BIAS_BIAS3_PWD_IR25SPARE2_LSB            4
+#define BIAS_BIAS3_PWD_IR25SPARE2_MASK           0x00000070
+#define BIAS_BIAS3_PWD_IR25SPARE2_GET(x)         (((x) & BIAS_BIAS3_PWD_IR25SPARE2_MASK) >> BIAS_BIAS3_PWD_IR25SPARE2_LSB)
+#define BIAS_BIAS3_PWD_IR25SPARE2_SET(x)         (((x) << BIAS_BIAS3_PWD_IR25SPARE2_LSB) & BIAS_BIAS3_PWD_IR25SPARE2_MASK)
+#define BIAS_BIAS3_PWD_ICDACREG12P5_MSB          3
+#define BIAS_BIAS3_PWD_ICDACREG12P5_LSB          1
+#define BIAS_BIAS3_PWD_ICDACREG12P5_MASK         0x0000000e
+#define BIAS_BIAS3_PWD_ICDACREG12P5_GET(x)       (((x) & BIAS_BIAS3_PWD_ICDACREG12P5_MASK) >> BIAS_BIAS3_PWD_ICDACREG12P5_LSB)
+#define BIAS_BIAS3_PWD_ICDACREG12P5_SET(x)       (((x) << BIAS_BIAS3_PWD_ICDACREG12P5_LSB) & BIAS_BIAS3_PWD_ICDACREG12P5_MASK)
+#define BIAS_BIAS3_SPARE_MSB                     0
+#define BIAS_BIAS3_SPARE_LSB                     0
+#define BIAS_BIAS3_SPARE_MASK                    0x00000001
+#define BIAS_BIAS3_SPARE_GET(x)                  (((x) & BIAS_BIAS3_SPARE_MASK) >> BIAS_BIAS3_SPARE_LSB)
+#define BIAS_BIAS3_SPARE_SET(x)                  (((x) << BIAS_BIAS3_SPARE_LSB) & BIAS_BIAS3_SPARE_MASK)
+
+#define TXPC_TXPC_ADDRESS                        0x00000048
+#define TXPC_TXPC_OFFSET                         0x00000048
+#define TXPC_TXPC_SELINTPD_MSB                   31
+#define TXPC_TXPC_SELINTPD_LSB                   31
+#define TXPC_TXPC_SELINTPD_MASK                  0x80000000
+#define TXPC_TXPC_SELINTPD_GET(x)                (((x) & TXPC_TXPC_SELINTPD_MASK) >> TXPC_TXPC_SELINTPD_LSB)
+#define TXPC_TXPC_SELINTPD_SET(x)                (((x) << TXPC_TXPC_SELINTPD_LSB) & TXPC_TXPC_SELINTPD_MASK)
+#define TXPC_TXPC_TEST_MSB                       30
+#define TXPC_TXPC_TEST_LSB                       30
+#define TXPC_TXPC_TEST_MASK                      0x40000000
+#define TXPC_TXPC_TEST_GET(x)                    (((x) & TXPC_TXPC_TEST_MASK) >> TXPC_TXPC_TEST_LSB)
+#define TXPC_TXPC_TEST_SET(x)                    (((x) << TXPC_TXPC_TEST_LSB) & TXPC_TXPC_TEST_MASK)
+#define TXPC_TXPC_TESTGAIN_MSB                   29
+#define TXPC_TXPC_TESTGAIN_LSB                   28
+#define TXPC_TXPC_TESTGAIN_MASK                  0x30000000
+#define TXPC_TXPC_TESTGAIN_GET(x)                (((x) & TXPC_TXPC_TESTGAIN_MASK) >> TXPC_TXPC_TESTGAIN_LSB)
+#define TXPC_TXPC_TESTGAIN_SET(x)                (((x) << TXPC_TXPC_TESTGAIN_LSB) & TXPC_TXPC_TESTGAIN_MASK)
+#define TXPC_TXPC_TESTDAC_MSB                    27
+#define TXPC_TXPC_TESTDAC_LSB                    22
+#define TXPC_TXPC_TESTDAC_MASK                   0x0fc00000
+#define TXPC_TXPC_TESTDAC_GET(x)                 (((x) & TXPC_TXPC_TESTDAC_MASK) >> TXPC_TXPC_TESTDAC_LSB)
+#define TXPC_TXPC_TESTDAC_SET(x)                 (((x) << TXPC_TXPC_TESTDAC_LSB) & TXPC_TXPC_TESTDAC_MASK)
+#define TXPC_TXPC_TESTPWDPC_MSB                  21
+#define TXPC_TXPC_TESTPWDPC_LSB                  21
+#define TXPC_TXPC_TESTPWDPC_MASK                 0x00200000
+#define TXPC_TXPC_TESTPWDPC_GET(x)               (((x) & TXPC_TXPC_TESTPWDPC_MASK) >> TXPC_TXPC_TESTPWDPC_LSB)
+#define TXPC_TXPC_TESTPWDPC_SET(x)               (((x) << TXPC_TXPC_TESTPWDPC_LSB) & TXPC_TXPC_TESTPWDPC_MASK)
+#define TXPC_TXPC_CURHALF_MSB                    20
+#define TXPC_TXPC_CURHALF_LSB                    20
+#define TXPC_TXPC_CURHALF_MASK                   0x00100000
+#define TXPC_TXPC_CURHALF_GET(x)                 (((x) & TXPC_TXPC_CURHALF_MASK) >> TXPC_TXPC_CURHALF_LSB)
+#define TXPC_TXPC_CURHALF_SET(x)                 (((x) << TXPC_TXPC_CURHALF_LSB) & TXPC_TXPC_CURHALF_MASK)
+#define TXPC_TXPC_NEGOUT_MSB                     19
+#define TXPC_TXPC_NEGOUT_LSB                     19
+#define TXPC_TXPC_NEGOUT_MASK                    0x00080000
+#define TXPC_TXPC_NEGOUT_GET(x)                  (((x) & TXPC_TXPC_NEGOUT_MASK) >> TXPC_TXPC_NEGOUT_LSB)
+#define TXPC_TXPC_NEGOUT_SET(x)                  (((x) << TXPC_TXPC_NEGOUT_LSB) & TXPC_TXPC_NEGOUT_MASK)
+#define TXPC_TXPC_CLKDELAY_MSB                   18
+#define TXPC_TXPC_CLKDELAY_LSB                   18
+#define TXPC_TXPC_CLKDELAY_MASK                  0x00040000
+#define TXPC_TXPC_CLKDELAY_GET(x)                (((x) & TXPC_TXPC_CLKDELAY_MASK) >> TXPC_TXPC_CLKDELAY_LSB)
+#define TXPC_TXPC_CLKDELAY_SET(x)                (((x) << TXPC_TXPC_CLKDELAY_LSB) & TXPC_TXPC_CLKDELAY_MASK)
+#define TXPC_TXPC_SELMODREF_MSB                  17
+#define TXPC_TXPC_SELMODREF_LSB                  17
+#define TXPC_TXPC_SELMODREF_MASK                 0x00020000
+#define TXPC_TXPC_SELMODREF_GET(x)               (((x) & TXPC_TXPC_SELMODREF_MASK) >> TXPC_TXPC_SELMODREF_LSB)
+#define TXPC_TXPC_SELMODREF_SET(x)               (((x) << TXPC_TXPC_SELMODREF_LSB) & TXPC_TXPC_SELMODREF_MASK)
+#define TXPC_TXPC_SELCMOUT_MSB                   16
+#define TXPC_TXPC_SELCMOUT_LSB                   16
+#define TXPC_TXPC_SELCMOUT_MASK                  0x00010000
+#define TXPC_TXPC_SELCMOUT_GET(x)                (((x) & TXPC_TXPC_SELCMOUT_MASK) >> TXPC_TXPC_SELCMOUT_LSB)
+#define TXPC_TXPC_SELCMOUT_SET(x)                (((x) << TXPC_TXPC_SELCMOUT_LSB) & TXPC_TXPC_SELCMOUT_MASK)
+#define TXPC_TXPC_TSMODE_MSB                     15
+#define TXPC_TXPC_TSMODE_LSB                     14
+#define TXPC_TXPC_TSMODE_MASK                    0x0000c000
+#define TXPC_TXPC_TSMODE_GET(x)                  (((x) & TXPC_TXPC_TSMODE_MASK) >> TXPC_TXPC_TSMODE_LSB)
+#define TXPC_TXPC_TSMODE_SET(x)                  (((x) << TXPC_TXPC_TSMODE_LSB) & TXPC_TXPC_TSMODE_MASK)
+#define TXPC_TXPC_N_MSB                          13
+#define TXPC_TXPC_N_LSB                          6
+#define TXPC_TXPC_N_MASK                         0x00003fc0
+#define TXPC_TXPC_N_GET(x)                       (((x) & TXPC_TXPC_N_MASK) >> TXPC_TXPC_N_LSB)
+#define TXPC_TXPC_N_SET(x)                       (((x) << TXPC_TXPC_N_LSB) & TXPC_TXPC_N_MASK)
+#define TXPC_TXPC_ON1STSYNTHON_MSB               5
+#define TXPC_TXPC_ON1STSYNTHON_LSB               5
+#define TXPC_TXPC_ON1STSYNTHON_MASK              0x00000020
+#define TXPC_TXPC_ON1STSYNTHON_GET(x)            (((x) & TXPC_TXPC_ON1STSYNTHON_MASK) >> TXPC_TXPC_ON1STSYNTHON_LSB)
+#define TXPC_TXPC_ON1STSYNTHON_SET(x)            (((x) << TXPC_TXPC_ON1STSYNTHON_LSB) & TXPC_TXPC_ON1STSYNTHON_MASK)
+#define TXPC_TXPC_SELINIT_MSB                    4
+#define TXPC_TXPC_SELINIT_LSB                    3
+#define TXPC_TXPC_SELINIT_MASK                   0x00000018
+#define TXPC_TXPC_SELINIT_GET(x)                 (((x) & TXPC_TXPC_SELINIT_MASK) >> TXPC_TXPC_SELINIT_LSB)
+#define TXPC_TXPC_SELINIT_SET(x)                 (((x) << TXPC_TXPC_SELINIT_LSB) & TXPC_TXPC_SELINIT_MASK)
+#define TXPC_TXPC_SELCOUNT_MSB                   2
+#define TXPC_TXPC_SELCOUNT_LSB                   2
+#define TXPC_TXPC_SELCOUNT_MASK                  0x00000004
+#define TXPC_TXPC_SELCOUNT_GET(x)                (((x) & TXPC_TXPC_SELCOUNT_MASK) >> TXPC_TXPC_SELCOUNT_LSB)
+#define TXPC_TXPC_SELCOUNT_SET(x)                (((x) << TXPC_TXPC_SELCOUNT_LSB) & TXPC_TXPC_SELCOUNT_MASK)
+#define TXPC_TXPC_ATBSEL_MSB                     1
+#define TXPC_TXPC_ATBSEL_LSB                     0
+#define TXPC_TXPC_ATBSEL_MASK                    0x00000003
+#define TXPC_TXPC_ATBSEL_GET(x)                  (((x) & TXPC_TXPC_ATBSEL_MASK) >> TXPC_TXPC_ATBSEL_LSB)
+#define TXPC_TXPC_ATBSEL_SET(x)                  (((x) << TXPC_TXPC_ATBSEL_LSB) & TXPC_TXPC_ATBSEL_MASK)
+
+#define TXPC_MISC_ADDRESS                        0x0000004c
+#define TXPC_MISC_OFFSET                         0x0000004c
+#define TXPC_MISC_FLIPBMODE_MSB                  31
+#define TXPC_MISC_FLIPBMODE_LSB                  31
+#define TXPC_MISC_FLIPBMODE_MASK                 0x80000000
+#define TXPC_MISC_FLIPBMODE_GET(x)               (((x) & TXPC_MISC_FLIPBMODE_MASK) >> TXPC_MISC_FLIPBMODE_LSB)
+#define TXPC_MISC_FLIPBMODE_SET(x)               (((x) << TXPC_MISC_FLIPBMODE_LSB) & TXPC_MISC_FLIPBMODE_MASK)
+#define TXPC_MISC_LEVEL_MSB                      30
+#define TXPC_MISC_LEVEL_LSB                      29
+#define TXPC_MISC_LEVEL_MASK                     0x60000000
+#define TXPC_MISC_LEVEL_GET(x)                   (((x) & TXPC_MISC_LEVEL_MASK) >> TXPC_MISC_LEVEL_LSB)
+#define TXPC_MISC_LEVEL_SET(x)                   (((x) << TXPC_MISC_LEVEL_LSB) & TXPC_MISC_LEVEL_MASK)
+#define TXPC_MISC_LDO_TEST_MODE_MSB              28
+#define TXPC_MISC_LDO_TEST_MODE_LSB              28
+#define TXPC_MISC_LDO_TEST_MODE_MASK             0x10000000
+#define TXPC_MISC_LDO_TEST_MODE_GET(x)           (((x) & TXPC_MISC_LDO_TEST_MODE_MASK) >> TXPC_MISC_LDO_TEST_MODE_LSB)
+#define TXPC_MISC_LDO_TEST_MODE_SET(x)           (((x) << TXPC_MISC_LDO_TEST_MODE_LSB) & TXPC_MISC_LDO_TEST_MODE_MASK)
+#define TXPC_MISC_NOTCXODET_MSB                  27
+#define TXPC_MISC_NOTCXODET_LSB                  27
+#define TXPC_MISC_NOTCXODET_MASK                 0x08000000
+#define TXPC_MISC_NOTCXODET_GET(x)               (((x) & TXPC_MISC_NOTCXODET_MASK) >> TXPC_MISC_NOTCXODET_LSB)
+#define TXPC_MISC_NOTCXODET_SET(x)               (((x) << TXPC_MISC_NOTCXODET_LSB) & TXPC_MISC_NOTCXODET_MASK)
+#define TXPC_MISC_PWDCLKIND_MSB                  26
+#define TXPC_MISC_PWDCLKIND_LSB                  26
+#define TXPC_MISC_PWDCLKIND_MASK                 0x04000000
+#define TXPC_MISC_PWDCLKIND_GET(x)               (((x) & TXPC_MISC_PWDCLKIND_MASK) >> TXPC_MISC_PWDCLKIND_LSB)
+#define TXPC_MISC_PWDCLKIND_SET(x)               (((x) << TXPC_MISC_PWDCLKIND_LSB) & TXPC_MISC_PWDCLKIND_MASK)
+#define TXPC_MISC_PWDXINPAD_MSB                  25
+#define TXPC_MISC_PWDXINPAD_LSB                  25
+#define TXPC_MISC_PWDXINPAD_MASK                 0x02000000
+#define TXPC_MISC_PWDXINPAD_GET(x)               (((x) & TXPC_MISC_PWDXINPAD_MASK) >> TXPC_MISC_PWDXINPAD_LSB)
+#define TXPC_MISC_PWDXINPAD_SET(x)               (((x) << TXPC_MISC_PWDXINPAD_LSB) & TXPC_MISC_PWDXINPAD_MASK)
+#define TXPC_MISC_LOCALBIAS_MSB                  24
+#define TXPC_MISC_LOCALBIAS_LSB                  24
+#define TXPC_MISC_LOCALBIAS_MASK                 0x01000000
+#define TXPC_MISC_LOCALBIAS_GET(x)               (((x) & TXPC_MISC_LOCALBIAS_MASK) >> TXPC_MISC_LOCALBIAS_LSB)
+#define TXPC_MISC_LOCALBIAS_SET(x)               (((x) << TXPC_MISC_LOCALBIAS_LSB) & TXPC_MISC_LOCALBIAS_MASK)
+#define TXPC_MISC_LOCALBIAS2X_MSB                23
+#define TXPC_MISC_LOCALBIAS2X_LSB                23
+#define TXPC_MISC_LOCALBIAS2X_MASK               0x00800000
+#define TXPC_MISC_LOCALBIAS2X_GET(x)             (((x) & TXPC_MISC_LOCALBIAS2X_MASK) >> TXPC_MISC_LOCALBIAS2X_LSB)
+#define TXPC_MISC_LOCALBIAS2X_SET(x)             (((x) << TXPC_MISC_LOCALBIAS2X_LSB) & TXPC_MISC_LOCALBIAS2X_MASK)
+#define TXPC_MISC_SELTSP_MSB                     22
+#define TXPC_MISC_SELTSP_LSB                     22
+#define TXPC_MISC_SELTSP_MASK                    0x00400000
+#define TXPC_MISC_SELTSP_GET(x)                  (((x) & TXPC_MISC_SELTSP_MASK) >> TXPC_MISC_SELTSP_LSB)
+#define TXPC_MISC_SELTSP_SET(x)                  (((x) << TXPC_MISC_SELTSP_LSB) & TXPC_MISC_SELTSP_MASK)
+#define TXPC_MISC_SELTSN_MSB                     21
+#define TXPC_MISC_SELTSN_LSB                     21
+#define TXPC_MISC_SELTSN_MASK                    0x00200000
+#define TXPC_MISC_SELTSN_GET(x)                  (((x) & TXPC_MISC_SELTSN_MASK) >> TXPC_MISC_SELTSN_LSB)
+#define TXPC_MISC_SELTSN_SET(x)                  (((x) << TXPC_MISC_SELTSN_LSB) & TXPC_MISC_SELTSN_MASK)
+#define TXPC_MISC_SPARE_A_MSB                    20
+#define TXPC_MISC_SPARE_A_LSB                    18
+#define TXPC_MISC_SPARE_A_MASK                   0x001c0000
+#define TXPC_MISC_SPARE_A_GET(x)                 (((x) & TXPC_MISC_SPARE_A_MASK) >> TXPC_MISC_SPARE_A_LSB)
+#define TXPC_MISC_SPARE_A_SET(x)                 (((x) << TXPC_MISC_SPARE_A_LSB) & TXPC_MISC_SPARE_A_MASK)
+#define TXPC_MISC_DECOUT_MSB                     17
+#define TXPC_MISC_DECOUT_LSB                     8
+#define TXPC_MISC_DECOUT_MASK                    0x0003ff00
+#define TXPC_MISC_DECOUT_GET(x)                  (((x) & TXPC_MISC_DECOUT_MASK) >> TXPC_MISC_DECOUT_LSB)
+#define TXPC_MISC_DECOUT_SET(x)                  (((x) << TXPC_MISC_DECOUT_LSB) & TXPC_MISC_DECOUT_MASK)
+#define TXPC_MISC_XTALDIV_MSB                    7
+#define TXPC_MISC_XTALDIV_LSB                    6
+#define TXPC_MISC_XTALDIV_MASK                   0x000000c0
+#define TXPC_MISC_XTALDIV_GET(x)                 (((x) & TXPC_MISC_XTALDIV_MASK) >> TXPC_MISC_XTALDIV_LSB)
+#define TXPC_MISC_XTALDIV_SET(x)                 (((x) << TXPC_MISC_XTALDIV_LSB) & TXPC_MISC_XTALDIV_MASK)
+#define TXPC_MISC_SPARE_MSB                      5
+#define TXPC_MISC_SPARE_LSB                      0
+#define TXPC_MISC_SPARE_MASK                     0x0000003f
+#define TXPC_MISC_SPARE_GET(x)                   (((x) & TXPC_MISC_SPARE_MASK) >> TXPC_MISC_SPARE_LSB)
+#define TXPC_MISC_SPARE_SET(x)                   (((x) << TXPC_MISC_SPARE_LSB) & TXPC_MISC_SPARE_MASK)
+
+#define RXTXBB_RXTXBB1_ADDRESS                   0x00000050
+#define RXTXBB_RXTXBB1_OFFSET                    0x00000050
+#define RXTXBB_RXTXBB1_SPARE_MSB                 31
+#define RXTXBB_RXTXBB1_SPARE_LSB                 19
+#define RXTXBB_RXTXBB1_SPARE_MASK                0xfff80000
+#define RXTXBB_RXTXBB1_SPARE_GET(x)              (((x) & RXTXBB_RXTXBB1_SPARE_MASK) >> RXTXBB_RXTXBB1_SPARE_LSB)
+#define RXTXBB_RXTXBB1_SPARE_SET(x)              (((x) << RXTXBB_RXTXBB1_SPARE_LSB) & RXTXBB_RXTXBB1_SPARE_MASK)
+#define RXTXBB_RXTXBB1_FNOTCH_MSB                18
+#define RXTXBB_RXTXBB1_FNOTCH_LSB                17
+#define RXTXBB_RXTXBB1_FNOTCH_MASK               0x00060000
+#define RXTXBB_RXTXBB1_FNOTCH_GET(x)             (((x) & RXTXBB_RXTXBB1_FNOTCH_MASK) >> RXTXBB_RXTXBB1_FNOTCH_LSB)
+#define RXTXBB_RXTXBB1_FNOTCH_SET(x)             (((x) << RXTXBB_RXTXBB1_FNOTCH_LSB) & RXTXBB_RXTXBB1_FNOTCH_MASK)
+#define RXTXBB_RXTXBB1_SEL_ATB_MSB               16
+#define RXTXBB_RXTXBB1_SEL_ATB_LSB               9
+#define RXTXBB_RXTXBB1_SEL_ATB_MASK              0x0001fe00
+#define RXTXBB_RXTXBB1_SEL_ATB_GET(x)            (((x) & RXTXBB_RXTXBB1_SEL_ATB_MASK) >> RXTXBB_RXTXBB1_SEL_ATB_LSB)
+#define RXTXBB_RXTXBB1_SEL_ATB_SET(x)            (((x) << RXTXBB_RXTXBB1_SEL_ATB_LSB) & RXTXBB_RXTXBB1_SEL_ATB_MASK)
+#define RXTXBB_RXTXBB1_PDDACINTERFACE_MSB        8
+#define RXTXBB_RXTXBB1_PDDACINTERFACE_LSB        8
+#define RXTXBB_RXTXBB1_PDDACINTERFACE_MASK       0x00000100
+#define RXTXBB_RXTXBB1_PDDACINTERFACE_GET(x)     (((x) & RXTXBB_RXTXBB1_PDDACINTERFACE_MASK) >> RXTXBB_RXTXBB1_PDDACINTERFACE_LSB)
+#define RXTXBB_RXTXBB1_PDDACINTERFACE_SET(x)     (((x) << RXTXBB_RXTXBB1_PDDACINTERFACE_LSB) & RXTXBB_RXTXBB1_PDDACINTERFACE_MASK)
+#define RXTXBB_RXTXBB1_PDV2I_MSB                 7
+#define RXTXBB_RXTXBB1_PDV2I_LSB                 7
+#define RXTXBB_RXTXBB1_PDV2I_MASK                0x00000080
+#define RXTXBB_RXTXBB1_PDV2I_GET(x)              (((x) & RXTXBB_RXTXBB1_PDV2I_MASK) >> RXTXBB_RXTXBB1_PDV2I_LSB)
+#define RXTXBB_RXTXBB1_PDV2I_SET(x)              (((x) << RXTXBB_RXTXBB1_PDV2I_LSB) & RXTXBB_RXTXBB1_PDV2I_MASK)
+#define RXTXBB_RXTXBB1_PDI2V_MSB                 6
+#define RXTXBB_RXTXBB1_PDI2V_LSB                 6
+#define RXTXBB_RXTXBB1_PDI2V_MASK                0x00000040
+#define RXTXBB_RXTXBB1_PDI2V_GET(x)              (((x) & RXTXBB_RXTXBB1_PDI2V_MASK) >> RXTXBB_RXTXBB1_PDI2V_LSB)
+#define RXTXBB_RXTXBB1_PDI2V_SET(x)              (((x) << RXTXBB_RXTXBB1_PDI2V_LSB) & RXTXBB_RXTXBB1_PDI2V_MASK)
+#define RXTXBB_RXTXBB1_PDRXTXBB_MSB              5
+#define RXTXBB_RXTXBB1_PDRXTXBB_LSB              5
+#define RXTXBB_RXTXBB1_PDRXTXBB_MASK             0x00000020
+#define RXTXBB_RXTXBB1_PDRXTXBB_GET(x)           (((x) & RXTXBB_RXTXBB1_PDRXTXBB_MASK) >> RXTXBB_RXTXBB1_PDRXTXBB_LSB)
+#define RXTXBB_RXTXBB1_PDRXTXBB_SET(x)           (((x) << RXTXBB_RXTXBB1_PDRXTXBB_LSB) & RXTXBB_RXTXBB1_PDRXTXBB_MASK)
+#define RXTXBB_RXTXBB1_PDOFFSETLOQ_MSB           4
+#define RXTXBB_RXTXBB1_PDOFFSETLOQ_LSB           4
+#define RXTXBB_RXTXBB1_PDOFFSETLOQ_MASK          0x00000010
+#define RXTXBB_RXTXBB1_PDOFFSETLOQ_GET(x)        (((x) & RXTXBB_RXTXBB1_PDOFFSETLOQ_MASK) >> RXTXBB_RXTXBB1_PDOFFSETLOQ_LSB)
+#define RXTXBB_RXTXBB1_PDOFFSETLOQ_SET(x)        (((x) << RXTXBB_RXTXBB1_PDOFFSETLOQ_LSB) & RXTXBB_RXTXBB1_PDOFFSETLOQ_MASK)
+#define RXTXBB_RXTXBB1_PDOFFSETHIQ_MSB           3
+#define RXTXBB_RXTXBB1_PDOFFSETHIQ_LSB           3
+#define RXTXBB_RXTXBB1_PDOFFSETHIQ_MASK          0x00000008
+#define RXTXBB_RXTXBB1_PDOFFSETHIQ_GET(x)        (((x) & RXTXBB_RXTXBB1_PDOFFSETHIQ_MASK) >> RXTXBB_RXTXBB1_PDOFFSETHIQ_LSB)
+#define RXTXBB_RXTXBB1_PDOFFSETHIQ_SET(x)        (((x) << RXTXBB_RXTXBB1_PDOFFSETHIQ_LSB) & RXTXBB_RXTXBB1_PDOFFSETHIQ_MASK)
+#define RXTXBB_RXTXBB1_PDOFFSETI2V_MSB           2
+#define RXTXBB_RXTXBB1_PDOFFSETI2V_LSB           2
+#define RXTXBB_RXTXBB1_PDOFFSETI2V_MASK          0x00000004
+#define RXTXBB_RXTXBB1_PDOFFSETI2V_GET(x)        (((x) & RXTXBB_RXTXBB1_PDOFFSETI2V_MASK) >> RXTXBB_RXTXBB1_PDOFFSETI2V_LSB)
+#define RXTXBB_RXTXBB1_PDOFFSETI2V_SET(x)        (((x) << RXTXBB_RXTXBB1_PDOFFSETI2V_LSB) & RXTXBB_RXTXBB1_PDOFFSETI2V_MASK)
+#define RXTXBB_RXTXBB1_PDLOQ_MSB                 1
+#define RXTXBB_RXTXBB1_PDLOQ_LSB                 1
+#define RXTXBB_RXTXBB1_PDLOQ_MASK                0x00000002
+#define RXTXBB_RXTXBB1_PDLOQ_GET(x)              (((x) & RXTXBB_RXTXBB1_PDLOQ_MASK) >> RXTXBB_RXTXBB1_PDLOQ_LSB)
+#define RXTXBB_RXTXBB1_PDLOQ_SET(x)              (((x) << RXTXBB_RXTXBB1_PDLOQ_LSB) & RXTXBB_RXTXBB1_PDLOQ_MASK)
+#define RXTXBB_RXTXBB1_PDHIQ_MSB                 0
+#define RXTXBB_RXTXBB1_PDHIQ_LSB                 0
+#define RXTXBB_RXTXBB1_PDHIQ_MASK                0x00000001
+#define RXTXBB_RXTXBB1_PDHIQ_GET(x)              (((x) & RXTXBB_RXTXBB1_PDHIQ_MASK) >> RXTXBB_RXTXBB1_PDHIQ_LSB)
+#define RXTXBB_RXTXBB1_PDHIQ_SET(x)              (((x) << RXTXBB_RXTXBB1_PDHIQ_LSB) & RXTXBB_RXTXBB1_PDHIQ_MASK)
+
+#define RXTXBB_RXTXBB2_ADDRESS                   0x00000054
+#define RXTXBB_RXTXBB2_OFFSET                    0x00000054
+#define RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_MSB    31
+#define RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_LSB    29
+#define RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_MASK   0xe0000000
+#define RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_GET(x) (((x) & RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_MASK) >> RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_LSB)
+#define RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_SET(x) (((x) << RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_LSB) & RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_MASK)
+#define RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_MSB    28
+#define RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_LSB    26
+#define RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_MASK   0x1c000000
+#define RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_GET(x) (((x) & RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_MASK) >> RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_LSB)
+#define RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_SET(x) (((x) << RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_LSB) & RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_MASK)
+#define RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_MSB   25
+#define RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_LSB   23
+#define RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_MASK  0x03800000
+#define RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_GET(x) (((x) & RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_MASK) >> RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_LSB)
+#define RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_SET(x) (((x) << RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_LSB) & RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_MASK)
+#define RXTXBB_RXTXBB2_SPARE_MSB                 22
+#define RXTXBB_RXTXBB2_SPARE_LSB                 21
+#define RXTXBB_RXTXBB2_SPARE_MASK                0x00600000
+#define RXTXBB_RXTXBB2_SPARE_GET(x)              (((x) & RXTXBB_RXTXBB2_SPARE_MASK) >> RXTXBB_RXTXBB2_SPARE_LSB)
+#define RXTXBB_RXTXBB2_SPARE_SET(x)              (((x) << RXTXBB_RXTXBB2_SPARE_LSB) & RXTXBB_RXTXBB2_SPARE_MASK)
+#define RXTXBB_RXTXBB2_SHORTBUFFER_MSB           20
+#define RXTXBB_RXTXBB2_SHORTBUFFER_LSB           20
+#define RXTXBB_RXTXBB2_SHORTBUFFER_MASK          0x00100000
+#define RXTXBB_RXTXBB2_SHORTBUFFER_GET(x)        (((x) & RXTXBB_RXTXBB2_SHORTBUFFER_MASK) >> RXTXBB_RXTXBB2_SHORTBUFFER_LSB)
+#define RXTXBB_RXTXBB2_SHORTBUFFER_SET(x)        (((x) << RXTXBB_RXTXBB2_SHORTBUFFER_LSB) & RXTXBB_RXTXBB2_SHORTBUFFER_MASK)
+#define RXTXBB_RXTXBB2_SELBUFFER_MSB             19
+#define RXTXBB_RXTXBB2_SELBUFFER_LSB             19
+#define RXTXBB_RXTXBB2_SELBUFFER_MASK            0x00080000
+#define RXTXBB_RXTXBB2_SELBUFFER_GET(x)          (((x) & RXTXBB_RXTXBB2_SELBUFFER_MASK) >> RXTXBB_RXTXBB2_SELBUFFER_LSB)
+#define RXTXBB_RXTXBB2_SELBUFFER_SET(x)          (((x) << RXTXBB_RXTXBB2_SELBUFFER_LSB) & RXTXBB_RXTXBB2_SELBUFFER_MASK)
+#define RXTXBB_RXTXBB2_SEL_DAC_TEST_MSB          18
+#define RXTXBB_RXTXBB2_SEL_DAC_TEST_LSB          18
+#define RXTXBB_RXTXBB2_SEL_DAC_TEST_MASK         0x00040000
+#define RXTXBB_RXTXBB2_SEL_DAC_TEST_GET(x)       (((x) & RXTXBB_RXTXBB2_SEL_DAC_TEST_MASK) >> RXTXBB_RXTXBB2_SEL_DAC_TEST_LSB)
+#define RXTXBB_RXTXBB2_SEL_DAC_TEST_SET(x)       (((x) << RXTXBB_RXTXBB2_SEL_DAC_TEST_LSB) & RXTXBB_RXTXBB2_SEL_DAC_TEST_MASK)
+#define RXTXBB_RXTXBB2_SEL_LOQ_TEST_MSB          17
+#define RXTXBB_RXTXBB2_SEL_LOQ_TEST_LSB          17
+#define RXTXBB_RXTXBB2_SEL_LOQ_TEST_MASK         0x00020000
+#define RXTXBB_RXTXBB2_SEL_LOQ_TEST_GET(x)       (((x) & RXTXBB_RXTXBB2_SEL_LOQ_TEST_MASK) >> RXTXBB_RXTXBB2_SEL_LOQ_TEST_LSB)
+#define RXTXBB_RXTXBB2_SEL_LOQ_TEST_SET(x)       (((x) << RXTXBB_RXTXBB2_SEL_LOQ_TEST_LSB) & RXTXBB_RXTXBB2_SEL_LOQ_TEST_MASK)
+#define RXTXBB_RXTXBB2_SEL_HIQ_TEST_MSB          16
+#define RXTXBB_RXTXBB2_SEL_HIQ_TEST_LSB          16
+#define RXTXBB_RXTXBB2_SEL_HIQ_TEST_MASK         0x00010000
+#define RXTXBB_RXTXBB2_SEL_HIQ_TEST_GET(x)       (((x) & RXTXBB_RXTXBB2_SEL_HIQ_TEST_MASK) >> RXTXBB_RXTXBB2_SEL_HIQ_TEST_LSB)
+#define RXTXBB_RXTXBB2_SEL_HIQ_TEST_SET(x)       (((x) << RXTXBB_RXTXBB2_SEL_HIQ_TEST_LSB) & RXTXBB_RXTXBB2_SEL_HIQ_TEST_MASK)
+#define RXTXBB_RXTXBB2_SEL_I2V_TEST_MSB          15
+#define RXTXBB_RXTXBB2_SEL_I2V_TEST_LSB          15
+#define RXTXBB_RXTXBB2_SEL_I2V_TEST_MASK         0x00008000
+#define RXTXBB_RXTXBB2_SEL_I2V_TEST_GET(x)       (((x) & RXTXBB_RXTXBB2_SEL_I2V_TEST_MASK) >> RXTXBB_RXTXBB2_SEL_I2V_TEST_LSB)
+#define RXTXBB_RXTXBB2_SEL_I2V_TEST_SET(x)       (((x) << RXTXBB_RXTXBB2_SEL_I2V_TEST_LSB) & RXTXBB_RXTXBB2_SEL_I2V_TEST_MASK)
+#define RXTXBB_RXTXBB2_CMSEL_MSB                 14
+#define RXTXBB_RXTXBB2_CMSEL_LSB                 13
+#define RXTXBB_RXTXBB2_CMSEL_MASK                0x00006000
+#define RXTXBB_RXTXBB2_CMSEL_GET(x)              (((x) & RXTXBB_RXTXBB2_CMSEL_MASK) >> RXTXBB_RXTXBB2_CMSEL_LSB)
+#define RXTXBB_RXTXBB2_CMSEL_SET(x)              (((x) << RXTXBB_RXTXBB2_CMSEL_LSB) & RXTXBB_RXTXBB2_CMSEL_MASK)
+#define RXTXBB_RXTXBB2_FILTERFC_MSB              12
+#define RXTXBB_RXTXBB2_FILTERFC_LSB              8
+#define RXTXBB_RXTXBB2_FILTERFC_MASK             0x00001f00
+#define RXTXBB_RXTXBB2_FILTERFC_GET(x)           (((x) & RXTXBB_RXTXBB2_FILTERFC_MASK) >> RXTXBB_RXTXBB2_FILTERFC_LSB)
+#define RXTXBB_RXTXBB2_FILTERFC_SET(x)           (((x) << RXTXBB_RXTXBB2_FILTERFC_LSB) & RXTXBB_RXTXBB2_FILTERFC_MASK)
+#define RXTXBB_RXTXBB2_LOCALFILTERTUNING_MSB     7
+#define RXTXBB_RXTXBB2_LOCALFILTERTUNING_LSB     7
+#define RXTXBB_RXTXBB2_LOCALFILTERTUNING_MASK    0x00000080
+#define RXTXBB_RXTXBB2_LOCALFILTERTUNING_GET(x)  (((x) & RXTXBB_RXTXBB2_LOCALFILTERTUNING_MASK) >> RXTXBB_RXTXBB2_LOCALFILTERTUNING_LSB)
+#define RXTXBB_RXTXBB2_LOCALFILTERTUNING_SET(x)  (((x) << RXTXBB_RXTXBB2_LOCALFILTERTUNING_LSB) & RXTXBB_RXTXBB2_LOCALFILTERTUNING_MASK)
+#define RXTXBB_RXTXBB2_FILTERDOUBLEBW_MSB        6
+#define RXTXBB_RXTXBB2_FILTERDOUBLEBW_LSB        6
+#define RXTXBB_RXTXBB2_FILTERDOUBLEBW_MASK       0x00000040
+#define RXTXBB_RXTXBB2_FILTERDOUBLEBW_GET(x)     (((x) & RXTXBB_RXTXBB2_FILTERDOUBLEBW_MASK) >> RXTXBB_RXTXBB2_FILTERDOUBLEBW_LSB)
+#define RXTXBB_RXTXBB2_FILTERDOUBLEBW_SET(x)     (((x) << RXTXBB_RXTXBB2_FILTERDOUBLEBW_LSB) & RXTXBB_RXTXBB2_FILTERDOUBLEBW_MASK)
+#define RXTXBB_RXTXBB2_PATH2HIQ_EN_MSB           5
+#define RXTXBB_RXTXBB2_PATH2HIQ_EN_LSB           5
+#define RXTXBB_RXTXBB2_PATH2HIQ_EN_MASK          0x00000020
+#define RXTXBB_RXTXBB2_PATH2HIQ_EN_GET(x)        (((x) & RXTXBB_RXTXBB2_PATH2HIQ_EN_MASK) >> RXTXBB_RXTXBB2_PATH2HIQ_EN_LSB)
+#define RXTXBB_RXTXBB2_PATH2HIQ_EN_SET(x)        (((x) << RXTXBB_RXTXBB2_PATH2HIQ_EN_LSB) & RXTXBB_RXTXBB2_PATH2HIQ_EN_MASK)
+#define RXTXBB_RXTXBB2_PATH1HIQ_EN_MSB           4
+#define RXTXBB_RXTXBB2_PATH1HIQ_EN_LSB           4
+#define RXTXBB_RXTXBB2_PATH1HIQ_EN_MASK          0x00000010
+#define RXTXBB_RXTXBB2_PATH1HIQ_EN_GET(x)        (((x) & RXTXBB_RXTXBB2_PATH1HIQ_EN_MASK) >> RXTXBB_RXTXBB2_PATH1HIQ_EN_LSB)
+#define RXTXBB_RXTXBB2_PATH1HIQ_EN_SET(x)        (((x) << RXTXBB_RXTXBB2_PATH1HIQ_EN_LSB) & RXTXBB_RXTXBB2_PATH1HIQ_EN_MASK)
+#define RXTXBB_RXTXBB2_PATH3LOQ_EN_MSB           3
+#define RXTXBB_RXTXBB2_PATH3LOQ_EN_LSB           3
+#define RXTXBB_RXTXBB2_PATH3LOQ_EN_MASK          0x00000008
+#define RXTXBB_RXTXBB2_PATH3LOQ_EN_GET(x)        (((x) & RXTXBB_RXTXBB2_PATH3LOQ_EN_MASK) >> RXTXBB_RXTXBB2_PATH3LOQ_EN_LSB)
+#define RXTXBB_RXTXBB2_PATH3LOQ_EN_SET(x)        (((x) << RXTXBB_RXTXBB2_PATH3LOQ_EN_LSB) & RXTXBB_RXTXBB2_PATH3LOQ_EN_MASK)
+#define RXTXBB_RXTXBB2_PATH2LOQ_EN_MSB           2
+#define RXTXBB_RXTXBB2_PATH2LOQ_EN_LSB           2
+#define RXTXBB_RXTXBB2_PATH2LOQ_EN_MASK          0x00000004
+#define RXTXBB_RXTXBB2_PATH2LOQ_EN_GET(x)        (((x) & RXTXBB_RXTXBB2_PATH2LOQ_EN_MASK) >> RXTXBB_RXTXBB2_PATH2LOQ_EN_LSB)
+#define RXTXBB_RXTXBB2_PATH2LOQ_EN_SET(x)        (((x) << RXTXBB_RXTXBB2_PATH2LOQ_EN_LSB) & RXTXBB_RXTXBB2_PATH2LOQ_EN_MASK)
+#define RXTXBB_RXTXBB2_PATH1LOQ_EN_MSB           1
+#define RXTXBB_RXTXBB2_PATH1LOQ_EN_LSB           1
+#define RXTXBB_RXTXBB2_PATH1LOQ_EN_MASK          0x00000002
+#define RXTXBB_RXTXBB2_PATH1LOQ_EN_GET(x)        (((x) & RXTXBB_RXTXBB2_PATH1LOQ_EN_MASK) >> RXTXBB_RXTXBB2_PATH1LOQ_EN_LSB)
+#define RXTXBB_RXTXBB2_PATH1LOQ_EN_SET(x)        (((x) << RXTXBB_RXTXBB2_PATH1LOQ_EN_LSB) & RXTXBB_RXTXBB2_PATH1LOQ_EN_MASK)
+#define RXTXBB_RXTXBB2_PATH_OVERRIDE_MSB         0
+#define RXTXBB_RXTXBB2_PATH_OVERRIDE_LSB         0
+#define RXTXBB_RXTXBB2_PATH_OVERRIDE_MASK        0x00000001
+#define RXTXBB_RXTXBB2_PATH_OVERRIDE_GET(x)      (((x) & RXTXBB_RXTXBB2_PATH_OVERRIDE_MASK) >> RXTXBB_RXTXBB2_PATH_OVERRIDE_LSB)
+#define RXTXBB_RXTXBB2_PATH_OVERRIDE_SET(x)      (((x) << RXTXBB_RXTXBB2_PATH_OVERRIDE_LSB) & RXTXBB_RXTXBB2_PATH_OVERRIDE_MASK)
+
+#define RXTXBB_RXTXBB3_ADDRESS                   0x00000058
+#define RXTXBB_RXTXBB3_OFFSET                    0x00000058
+#define RXTXBB_RXTXBB3_SPARE_MSB                 31
+#define RXTXBB_RXTXBB3_SPARE_LSB                 27
+#define RXTXBB_RXTXBB3_SPARE_MASK                0xf8000000
+#define RXTXBB_RXTXBB3_SPARE_GET(x)              (((x) & RXTXBB_RXTXBB3_SPARE_MASK) >> RXTXBB_RXTXBB3_SPARE_LSB)
+#define RXTXBB_RXTXBB3_SPARE_SET(x)              (((x) << RXTXBB_RXTXBB3_SPARE_LSB) & RXTXBB_RXTXBB3_SPARE_MASK)
+#define RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_MSB 26
+#define RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_LSB 24
+#define RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_MASK 0x07000000
+#define RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_LSB)
+#define RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_MASK)
+#define RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_MSB    23
+#define RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_LSB    21
+#define RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_MASK   0x00e00000
+#define RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_LSB)
+#define RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_MASK)
+#define RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_MSB      20
+#define RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_LSB      18
+#define RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_MASK     0x001c0000
+#define RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_GET(x)   (((x) & RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_LSB)
+#define RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_SET(x)   (((x) << RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_MASK)
+#define RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_MSB      17
+#define RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_LSB      15
+#define RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_MASK     0x00038000
+#define RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_GET(x)   (((x) & RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_LSB)
+#define RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_SET(x)   (((x) << RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_MASK)
+#define RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_MSB      14
+#define RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_LSB      12
+#define RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_MASK     0x00007000
+#define RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_GET(x)   (((x) & RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_LSB)
+#define RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_SET(x)   (((x) << RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_MASK)
+#define RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_MSB      11
+#define RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_LSB      9
+#define RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_MASK     0x00000e00
+#define RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_GET(x)   (((x) & RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_LSB)
+#define RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_SET(x)   (((x) << RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_MASK)
+#define RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_MSB      8
+#define RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_LSB      6
+#define RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_MASK     0x000001c0
+#define RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_GET(x)   (((x) & RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_LSB)
+#define RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_SET(x)   (((x) << RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_MASK)
+#define RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_MSB     5
+#define RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_LSB     3
+#define RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_MASK    0x00000038
+#define RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_GET(x)  (((x) & RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_MASK) >> RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_LSB)
+#define RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_SET(x)  (((x) << RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_LSB) & RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_MASK)
+#define RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_MSB    2
+#define RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_LSB    0
+#define RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_MASK   0x00000007
+#define RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_LSB)
+#define RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_MASK)
+
+#define RXTXBB_RXTXBB4_ADDRESS                   0x0000005c
+#define RXTXBB_RXTXBB4_OFFSET                    0x0000005c
+#define RXTXBB_RXTXBB4_SPARE_MSB                 31
+#define RXTXBB_RXTXBB4_SPARE_LSB                 31
+#define RXTXBB_RXTXBB4_SPARE_MASK                0x80000000
+#define RXTXBB_RXTXBB4_SPARE_GET(x)              (((x) & RXTXBB_RXTXBB4_SPARE_MASK) >> RXTXBB_RXTXBB4_SPARE_LSB)
+#define RXTXBB_RXTXBB4_SPARE_SET(x)              (((x) << RXTXBB_RXTXBB4_SPARE_LSB) & RXTXBB_RXTXBB4_SPARE_MASK)
+#define RXTXBB_RXTXBB4_LOCALOFFSET_MSB           30
+#define RXTXBB_RXTXBB4_LOCALOFFSET_LSB           30
+#define RXTXBB_RXTXBB4_LOCALOFFSET_MASK          0x40000000
+#define RXTXBB_RXTXBB4_LOCALOFFSET_GET(x)        (((x) & RXTXBB_RXTXBB4_LOCALOFFSET_MASK) >> RXTXBB_RXTXBB4_LOCALOFFSET_LSB)
+#define RXTXBB_RXTXBB4_LOCALOFFSET_SET(x)        (((x) << RXTXBB_RXTXBB4_LOCALOFFSET_LSB) & RXTXBB_RXTXBB4_LOCALOFFSET_MASK)
+#define RXTXBB_RXTXBB4_OFSTCORRHII_MSB           29
+#define RXTXBB_RXTXBB4_OFSTCORRHII_LSB           25
+#define RXTXBB_RXTXBB4_OFSTCORRHII_MASK          0x3e000000
+#define RXTXBB_RXTXBB4_OFSTCORRHII_GET(x)        (((x) & RXTXBB_RXTXBB4_OFSTCORRHII_MASK) >> RXTXBB_RXTXBB4_OFSTCORRHII_LSB)
+#define RXTXBB_RXTXBB4_OFSTCORRHII_SET(x)        (((x) << RXTXBB_RXTXBB4_OFSTCORRHII_LSB) & RXTXBB_RXTXBB4_OFSTCORRHII_MASK)
+#define RXTXBB_RXTXBB4_OFSTCORRHIQ_MSB           24
+#define RXTXBB_RXTXBB4_OFSTCORRHIQ_LSB           20
+#define RXTXBB_RXTXBB4_OFSTCORRHIQ_MASK          0x01f00000
+#define RXTXBB_RXTXBB4_OFSTCORRHIQ_GET(x)        (((x) & RXTXBB_RXTXBB4_OFSTCORRHIQ_MASK) >> RXTXBB_RXTXBB4_OFSTCORRHIQ_LSB)
+#define RXTXBB_RXTXBB4_OFSTCORRHIQ_SET(x)        (((x) << RXTXBB_RXTXBB4_OFSTCORRHIQ_LSB) & RXTXBB_RXTXBB4_OFSTCORRHIQ_MASK)
+#define RXTXBB_RXTXBB4_OFSTCORRLOI_MSB           19
+#define RXTXBB_RXTXBB4_OFSTCORRLOI_LSB           15
+#define RXTXBB_RXTXBB4_OFSTCORRLOI_MASK          0x000f8000
+#define RXTXBB_RXTXBB4_OFSTCORRLOI_GET(x)        (((x) & RXTXBB_RXTXBB4_OFSTCORRLOI_MASK) >> RXTXBB_RXTXBB4_OFSTCORRLOI_LSB)
+#define RXTXBB_RXTXBB4_OFSTCORRLOI_SET(x)        (((x) << RXTXBB_RXTXBB4_OFSTCORRLOI_LSB) & RXTXBB_RXTXBB4_OFSTCORRLOI_MASK)
+#define RXTXBB_RXTXBB4_OFSTCORRLOQ_MSB           14
+#define RXTXBB_RXTXBB4_OFSTCORRLOQ_LSB           10
+#define RXTXBB_RXTXBB4_OFSTCORRLOQ_MASK          0x00007c00
+#define RXTXBB_RXTXBB4_OFSTCORRLOQ_GET(x)        (((x) & RXTXBB_RXTXBB4_OFSTCORRLOQ_MASK) >> RXTXBB_RXTXBB4_OFSTCORRLOQ_LSB)
+#define RXTXBB_RXTXBB4_OFSTCORRLOQ_SET(x)        (((x) << RXTXBB_RXTXBB4_OFSTCORRLOQ_LSB) & RXTXBB_RXTXBB4_OFSTCORRLOQ_MASK)
+#define RXTXBB_RXTXBB4_OFSTCORRI2VI_MSB          9
+#define RXTXBB_RXTXBB4_OFSTCORRI2VI_LSB          5
+#define RXTXBB_RXTXBB4_OFSTCORRI2VI_MASK         0x000003e0
+#define RXTXBB_RXTXBB4_OFSTCORRI2VI_GET(x)       (((x) & RXTXBB_RXTXBB4_OFSTCORRI2VI_MASK) >> RXTXBB_RXTXBB4_OFSTCORRI2VI_LSB)
+#define RXTXBB_RXTXBB4_OFSTCORRI2VI_SET(x)       (((x) << RXTXBB_RXTXBB4_OFSTCORRI2VI_LSB) & RXTXBB_RXTXBB4_OFSTCORRI2VI_MASK)
+#define RXTXBB_RXTXBB4_OFSTCORRI2VQ_MSB          4
+#define RXTXBB_RXTXBB4_OFSTCORRI2VQ_LSB          0
+#define RXTXBB_RXTXBB4_OFSTCORRI2VQ_MASK         0x0000001f
+#define RXTXBB_RXTXBB4_OFSTCORRI2VQ_GET(x)       (((x) & RXTXBB_RXTXBB4_OFSTCORRI2VQ_MASK) >> RXTXBB_RXTXBB4_OFSTCORRI2VQ_LSB)
+#define RXTXBB_RXTXBB4_OFSTCORRI2VQ_SET(x)       (((x) << RXTXBB_RXTXBB4_OFSTCORRI2VQ_LSB) & RXTXBB_RXTXBB4_OFSTCORRI2VQ_MASK)
+
+#define ADDAC_ADDAC1_ADDRESS                     0x00000060
+#define ADDAC_ADDAC1_OFFSET                      0x00000060
+#define ADDAC_ADDAC1_PLL_SVREG_MSB               31
+#define ADDAC_ADDAC1_PLL_SVREG_LSB               31
+#define ADDAC_ADDAC1_PLL_SVREG_MASK              0x80000000
+#define ADDAC_ADDAC1_PLL_SVREG_GET(x)            (((x) & ADDAC_ADDAC1_PLL_SVREG_MASK) >> ADDAC_ADDAC1_PLL_SVREG_LSB)
+#define ADDAC_ADDAC1_PLL_SVREG_SET(x)            (((x) << ADDAC_ADDAC1_PLL_SVREG_LSB) & ADDAC_ADDAC1_PLL_SVREG_MASK)
+#define ADDAC_ADDAC1_PLL_SCLAMP_MSB              30
+#define ADDAC_ADDAC1_PLL_SCLAMP_LSB              28
+#define ADDAC_ADDAC1_PLL_SCLAMP_MASK             0x70000000
+#define ADDAC_ADDAC1_PLL_SCLAMP_GET(x)           (((x) & ADDAC_ADDAC1_PLL_SCLAMP_MASK) >> ADDAC_ADDAC1_PLL_SCLAMP_LSB)
+#define ADDAC_ADDAC1_PLL_SCLAMP_SET(x)           (((x) << ADDAC_ADDAC1_PLL_SCLAMP_LSB) & ADDAC_ADDAC1_PLL_SCLAMP_MASK)
+#define ADDAC_ADDAC1_PLL_ATB_MSB                 27
+#define ADDAC_ADDAC1_PLL_ATB_LSB                 26
+#define ADDAC_ADDAC1_PLL_ATB_MASK                0x0c000000
+#define ADDAC_ADDAC1_PLL_ATB_GET(x)              (((x) & ADDAC_ADDAC1_PLL_ATB_MASK) >> ADDAC_ADDAC1_PLL_ATB_LSB)
+#define ADDAC_ADDAC1_PLL_ATB_SET(x)              (((x) << ADDAC_ADDAC1_PLL_ATB_LSB) & ADDAC_ADDAC1_PLL_ATB_MASK)
+#define ADDAC_ADDAC1_PLL_ICP_MSB                 25
+#define ADDAC_ADDAC1_PLL_ICP_LSB                 23
+#define ADDAC_ADDAC1_PLL_ICP_MASK                0x03800000
+#define ADDAC_ADDAC1_PLL_ICP_GET(x)              (((x) & ADDAC_ADDAC1_PLL_ICP_MASK) >> ADDAC_ADDAC1_PLL_ICP_LSB)
+#define ADDAC_ADDAC1_PLL_ICP_SET(x)              (((x) << ADDAC_ADDAC1_PLL_ICP_LSB) & ADDAC_ADDAC1_PLL_ICP_MASK)
+#define ADDAC_ADDAC1_PLL_FILTER_MSB              22
+#define ADDAC_ADDAC1_PLL_FILTER_LSB              15
+#define ADDAC_ADDAC1_PLL_FILTER_MASK             0x007f8000
+#define ADDAC_ADDAC1_PLL_FILTER_GET(x)           (((x) & ADDAC_ADDAC1_PLL_FILTER_MASK) >> ADDAC_ADDAC1_PLL_FILTER_LSB)
+#define ADDAC_ADDAC1_PLL_FILTER_SET(x)           (((x) << ADDAC_ADDAC1_PLL_FILTER_LSB) & ADDAC_ADDAC1_PLL_FILTER_MASK)
+#define ADDAC_ADDAC1_PWDPLL_MSB                  14
+#define ADDAC_ADDAC1_PWDPLL_LSB                  14
+#define ADDAC_ADDAC1_PWDPLL_MASK                 0x00004000
+#define ADDAC_ADDAC1_PWDPLL_GET(x)               (((x) & ADDAC_ADDAC1_PWDPLL_MASK) >> ADDAC_ADDAC1_PWDPLL_LSB)
+#define ADDAC_ADDAC1_PWDPLL_SET(x)               (((x) << ADDAC_ADDAC1_PWDPLL_LSB) & ADDAC_ADDAC1_PWDPLL_MASK)
+#define ADDAC_ADDAC1_PWDADC_MSB                  13
+#define ADDAC_ADDAC1_PWDADC_LSB                  13
+#define ADDAC_ADDAC1_PWDADC_MASK                 0x00002000
+#define ADDAC_ADDAC1_PWDADC_GET(x)               (((x) & ADDAC_ADDAC1_PWDADC_MASK) >> ADDAC_ADDAC1_PWDADC_LSB)
+#define ADDAC_ADDAC1_PWDADC_SET(x)               (((x) << ADDAC_ADDAC1_PWDADC_LSB) & ADDAC_ADDAC1_PWDADC_MASK)
+#define ADDAC_ADDAC1_PWDDAC_MSB                  12
+#define ADDAC_ADDAC1_PWDDAC_LSB                  12
+#define ADDAC_ADDAC1_PWDDAC_MASK                 0x00001000
+#define ADDAC_ADDAC1_PWDDAC_GET(x)               (((x) & ADDAC_ADDAC1_PWDDAC_MASK) >> ADDAC_ADDAC1_PWDDAC_LSB)
+#define ADDAC_ADDAC1_PWDDAC_SET(x)               (((x) << ADDAC_ADDAC1_PWDDAC_LSB) & ADDAC_ADDAC1_PWDDAC_MASK)
+#define ADDAC_ADDAC1_FORCEMSBLOW_MSB             11
+#define ADDAC_ADDAC1_FORCEMSBLOW_LSB             11
+#define ADDAC_ADDAC1_FORCEMSBLOW_MASK            0x00000800
+#define ADDAC_ADDAC1_FORCEMSBLOW_GET(x)          (((x) & ADDAC_ADDAC1_FORCEMSBLOW_MASK) >> ADDAC_ADDAC1_FORCEMSBLOW_LSB)
+#define ADDAC_ADDAC1_FORCEMSBLOW_SET(x)          (((x) << ADDAC_ADDAC1_FORCEMSBLOW_LSB) & ADDAC_ADDAC1_FORCEMSBLOW_MASK)
+#define ADDAC_ADDAC1_SELMANPWDS_MSB              10
+#define ADDAC_ADDAC1_SELMANPWDS_LSB              10
+#define ADDAC_ADDAC1_SELMANPWDS_MASK             0x00000400
+#define ADDAC_ADDAC1_SELMANPWDS_GET(x)           (((x) & ADDAC_ADDAC1_SELMANPWDS_MASK) >> ADDAC_ADDAC1_SELMANPWDS_LSB)
+#define ADDAC_ADDAC1_SELMANPWDS_SET(x)           (((x) << ADDAC_ADDAC1_SELMANPWDS_LSB) & ADDAC_ADDAC1_SELMANPWDS_MASK)
+#define ADDAC_ADDAC1_INV_CLK160_ADC_MSB          9
+#define ADDAC_ADDAC1_INV_CLK160_ADC_LSB          9
+#define ADDAC_ADDAC1_INV_CLK160_ADC_MASK         0x00000200
+#define ADDAC_ADDAC1_INV_CLK160_ADC_GET(x)       (((x) & ADDAC_ADDAC1_INV_CLK160_ADC_MASK) >> ADDAC_ADDAC1_INV_CLK160_ADC_LSB)
+#define ADDAC_ADDAC1_INV_CLK160_ADC_SET(x)       (((x) << ADDAC_ADDAC1_INV_CLK160_ADC_LSB) & ADDAC_ADDAC1_INV_CLK160_ADC_MASK)
+#define ADDAC_ADDAC1_CM_SEL_MSB                  8
+#define ADDAC_ADDAC1_CM_SEL_LSB                  7
+#define ADDAC_ADDAC1_CM_SEL_MASK                 0x00000180
+#define ADDAC_ADDAC1_CM_SEL_GET(x)               (((x) & ADDAC_ADDAC1_CM_SEL_MASK) >> ADDAC_ADDAC1_CM_SEL_LSB)
+#define ADDAC_ADDAC1_CM_SEL_SET(x)               (((x) << ADDAC_ADDAC1_CM_SEL_LSB) & ADDAC_ADDAC1_CM_SEL_MASK)
+#define ADDAC_ADDAC1_DISABLE_DAC_REG_MSB         6
+#define ADDAC_ADDAC1_DISABLE_DAC_REG_LSB         6
+#define ADDAC_ADDAC1_DISABLE_DAC_REG_MASK        0x00000040
+#define ADDAC_ADDAC1_DISABLE_DAC_REG_GET(x)      (((x) & ADDAC_ADDAC1_DISABLE_DAC_REG_MASK) >> ADDAC_ADDAC1_DISABLE_DAC_REG_LSB)
+#define ADDAC_ADDAC1_DISABLE_DAC_REG_SET(x)      (((x) << ADDAC_ADDAC1_DISABLE_DAC_REG_LSB) & ADDAC_ADDAC1_DISABLE_DAC_REG_MASK)
+#define ADDAC_ADDAC1_SPARE_MSB                   5
+#define ADDAC_ADDAC1_SPARE_LSB                   0
+#define ADDAC_ADDAC1_SPARE_MASK                  0x0000003f
+#define ADDAC_ADDAC1_SPARE_GET(x)                (((x) & ADDAC_ADDAC1_SPARE_MASK) >> ADDAC_ADDAC1_SPARE_LSB)
+#define ADDAC_ADDAC1_SPARE_SET(x)                (((x) << ADDAC_ADDAC1_SPARE_LSB) & ADDAC_ADDAC1_SPARE_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct analog_reg_reg_s {
+  volatile unsigned int synth_synth1;
+  volatile unsigned int synth_synth2;
+  volatile unsigned int synth_synth3;
+  volatile unsigned int synth_synth4;
+  volatile unsigned int synth_synth5;
+  volatile unsigned int synth_synth6;
+  volatile unsigned int synth_synth7;
+  volatile unsigned int synth_synth8;
+  volatile unsigned int rf5g_rf5g1;
+  volatile unsigned int rf5g_rf5g2;
+  volatile unsigned int rf2g_rf2g1;
+  volatile unsigned int rf2g_rf2g2;
+  volatile unsigned int top_gain;
+  volatile unsigned int top_top;
+  volatile unsigned int bias_bias_sel;
+  volatile unsigned int bias_bias1;
+  volatile unsigned int bias_bias2;
+  volatile unsigned int bias_bias3;
+  volatile unsigned int txpc_txpc;
+  volatile unsigned int txpc_misc;
+  volatile unsigned int rxtxbb_rxtxbb1;
+  volatile unsigned int rxtxbb_rxtxbb2;
+  volatile unsigned int rxtxbb_rxtxbb3;
+  volatile unsigned int rxtxbb_rxtxbb4;
+  volatile unsigned int addac_addac1;
+} analog_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _ANALOG_REG_H_ */
diff --git a/drivers/net/ath6kl/include/common/AR6002/hw2.0/hw/apb_map.h b/drivers/net/ath6kl/include/common/AR6002/hw2.0/hw/apb_map.h
new file mode 100644
index 00000000000..f3bf6d6cc82
--- /dev/null
+++ b/drivers/net/ath6kl/include/common/AR6002/hw2.0/hw/apb_map.h
@@ -0,0 +1,13 @@
+#ifndef _APB_MAP_H_
+#define _APB_MAP_H_
+
+#define RTC_BASE_ADDRESS                         0x00004000
+#define VMC_BASE_ADDRESS                         0x00008000
+#define UART_BASE_ADDRESS                        0x0000c000
+#define SI_BASE_ADDRESS                          0x00010000
+#define GPIO_BASE_ADDRESS                        0x00014000
+#define MBOX_BASE_ADDRESS                        0x00018000
+#define ANALOG_INTF_BASE_ADDRESS                 0x0001c000
+#define MAC_BASE_ADDRESS                         0x00020000
+
+#endif /* _APB_MAP_REG_H_ */
diff --git a/drivers/net/ath6kl/include/common/AR6002/hw2.0/hw/gpio_reg.h b/drivers/net/ath6kl/include/common/AR6002/hw2.0/hw/gpio_reg.h
new file mode 100644
index 00000000000..4f2b964b7df
--- /dev/null
+++ b/drivers/net/ath6kl/include/common/AR6002/hw2.0/hw/gpio_reg.h
@@ -0,0 +1,977 @@
+#ifndef _GPIO_REG_REG_H_
+#define _GPIO_REG_REG_H_
+
+#define GPIO_OUT_ADDRESS                         0x00000000
+#define GPIO_OUT_OFFSET                          0x00000000
+#define GPIO_OUT_DATA_MSB                        17
+#define GPIO_OUT_DATA_LSB                        0
+#define GPIO_OUT_DATA_MASK                       0x0003ffff
+#define GPIO_OUT_DATA_GET(x)                     (((x) & GPIO_OUT_DATA_MASK) >> GPIO_OUT_DATA_LSB)
+#define GPIO_OUT_DATA_SET(x)                     (((x) << GPIO_OUT_DATA_LSB) & GPIO_OUT_DATA_MASK)
+
+#define GPIO_OUT_W1TS_ADDRESS                    0x00000004
+#define GPIO_OUT_W1TS_OFFSET                     0x00000004
+#define GPIO_OUT_W1TS_DATA_MSB                   17
+#define GPIO_OUT_W1TS_DATA_LSB                   0
+#define GPIO_OUT_W1TS_DATA_MASK                  0x0003ffff
+#define GPIO_OUT_W1TS_DATA_GET(x)                (((x) & GPIO_OUT_W1TS_DATA_MASK) >> GPIO_OUT_W1TS_DATA_LSB)
+#define GPIO_OUT_W1TS_DATA_SET(x)                (((x) << GPIO_OUT_W1TS_DATA_LSB) & GPIO_OUT_W1TS_DATA_MASK)
+
+#define GPIO_OUT_W1TC_ADDRESS                    0x00000008
+#define GPIO_OUT_W1TC_OFFSET                     0x00000008
+#define GPIO_OUT_W1TC_DATA_MSB                   17
+#define GPIO_OUT_W1TC_DATA_LSB                   0
+#define GPIO_OUT_W1TC_DATA_MASK                  0x0003ffff
+#define GPIO_OUT_W1TC_DATA_GET(x)                (((x) & GPIO_OUT_W1TC_DATA_MASK) >> GPIO_OUT_W1TC_DATA_LSB)
+#define GPIO_OUT_W1TC_DATA_SET(x)                (((x) << GPIO_OUT_W1TC_DATA_LSB) & GPIO_OUT_W1TC_DATA_MASK)
+
+#define GPIO_ENABLE_ADDRESS                      0x0000000c
+#define GPIO_ENABLE_OFFSET                       0x0000000c
+#define GPIO_ENABLE_DATA_MSB                     17
+#define GPIO_ENABLE_DATA_LSB                     0
+#define GPIO_ENABLE_DATA_MASK                    0x0003ffff
+#define GPIO_ENABLE_DATA_GET(x)                  (((x) & GPIO_ENABLE_DATA_MASK) >> GPIO_ENABLE_DATA_LSB)
+#define GPIO_ENABLE_DATA_SET(x)                  (((x) << GPIO_ENABLE_DATA_LSB) & GPIO_ENABLE_DATA_MASK)
+
+#define GPIO_ENABLE_W1TS_ADDRESS                 0x00000010
+#define GPIO_ENABLE_W1TS_OFFSET                  0x00000010
+#define GPIO_ENABLE_W1TS_DATA_MSB                17
+#define GPIO_ENABLE_W1TS_DATA_LSB                0
+#define GPIO_ENABLE_W1TS_DATA_MASK               0x0003ffff
+#define GPIO_ENABLE_W1TS_DATA_GET(x)             (((x) & GPIO_ENABLE_W1TS_DATA_MASK) >> GPIO_ENABLE_W1TS_DATA_LSB)
+#define GPIO_ENABLE_W1TS_DATA_SET(x)             (((x) << GPIO_ENABLE_W1TS_DATA_LSB) & GPIO_ENABLE_W1TS_DATA_MASK)
+
+#define GPIO_ENABLE_W1TC_ADDRESS                 0x00000014
+#define GPIO_ENABLE_W1TC_OFFSET                  0x00000014
+#define GPIO_ENABLE_W1TC_DATA_MSB                17
+#define GPIO_ENABLE_W1TC_DATA_LSB                0
+#define GPIO_ENABLE_W1TC_DATA_MASK               0x0003ffff
+#define GPIO_ENABLE_W1TC_DATA_GET(x)             (((x) & GPIO_ENABLE_W1TC_DATA_MASK) >> GPIO_ENABLE_W1TC_DATA_LSB)
+#define GPIO_ENABLE_W1TC_DATA_SET(x)             (((x) << GPIO_ENABLE_W1TC_DATA_LSB) & GPIO_ENABLE_W1TC_DATA_MASK)
+
+#define GPIO_IN_ADDRESS                          0x00000018
+#define GPIO_IN_OFFSET                           0x00000018
+#define GPIO_IN_DATA_MSB                         17
+#define GPIO_IN_DATA_LSB                         0
+#define GPIO_IN_DATA_MASK                        0x0003ffff
+#define GPIO_IN_DATA_GET(x)                      (((x) & GPIO_IN_DATA_MASK) >> GPIO_IN_DATA_LSB)
+#define GPIO_IN_DATA_SET(x)                      (((x) << GPIO_IN_DATA_LSB) & GPIO_IN_DATA_MASK)
+
+#define GPIO_STATUS_ADDRESS                      0x0000001c
+#define GPIO_STATUS_OFFSET                       0x0000001c
+#define GPIO_STATUS_INTERRUPT_MSB                17
+#define GPIO_STATUS_INTERRUPT_LSB                0
+#define GPIO_STATUS_INTERRUPT_MASK               0x0003ffff
+#define GPIO_STATUS_INTERRUPT_GET(x)             (((x) & GPIO_STATUS_INTERRUPT_MASK) >> GPIO_STATUS_INTERRUPT_LSB)
+#define GPIO_STATUS_INTERRUPT_SET(x)             (((x) << GPIO_STATUS_INTERRUPT_LSB) & GPIO_STATUS_INTERRUPT_MASK)
+
+#define GPIO_STATUS_W1TS_ADDRESS                 0x00000020
+#define GPIO_STATUS_W1TS_OFFSET                  0x00000020
+#define GPIO_STATUS_W1TS_INTERRUPT_MSB           17
+#define GPIO_STATUS_W1TS_INTERRUPT_LSB           0
+#define GPIO_STATUS_W1TS_INTERRUPT_MASK          0x0003ffff
+#define GPIO_STATUS_W1TS_INTERRUPT_GET(x)        (((x) & GPIO_STATUS_W1TS_INTERRUPT_MASK) >> GPIO_STATUS_W1TS_INTERRUPT_LSB)
+#define GPIO_STATUS_W1TS_INTERRUPT_SET(x)        (((x) << GPIO_STATUS_W1TS_INTERRUPT_LSB) & GPIO_STATUS_W1TS_INTERRUPT_MASK)
+
+#define GPIO_STATUS_W1TC_ADDRESS                 0x00000024
+#define GPIO_STATUS_W1TC_OFFSET                  0x00000024
+#define GPIO_STATUS_W1TC_INTERRUPT_MSB           17
+#define GPIO_STATUS_W1TC_INTERRUPT_LSB           0
+#define GPIO_STATUS_W1TC_INTERRUPT_MASK          0x0003ffff
+#define GPIO_STATUS_W1TC_INTERRUPT_GET(x)        (((x) & GPIO_STATUS_W1TC_INTERRUPT_MASK) >> GPIO_STATUS_W1TC_INTERRUPT_LSB)
+#define GPIO_STATUS_W1TC_INTERRUPT_SET(x)        (((x) << GPIO_STATUS_W1TC_INTERRUPT_LSB) & GPIO_STATUS_W1TC_INTERRUPT_MASK)
+
+#define GPIO_PIN0_ADDRESS                        0x00000028
+#define GPIO_PIN0_OFFSET                         0x00000028
+#define GPIO_PIN0_CONFIG_MSB                     12
+#define GPIO_PIN0_CONFIG_LSB                     11
+#define GPIO_PIN0_CONFIG_MASK                    0x00001800
+#define GPIO_PIN0_CONFIG_GET(x)                  (((x) & GPIO_PIN0_CONFIG_MASK) >> GPIO_PIN0_CONFIG_LSB)
+#define GPIO_PIN0_CONFIG_SET(x)                  (((x) << GPIO_PIN0_CONFIG_LSB) & GPIO_PIN0_CONFIG_MASK)
+#define GPIO_PIN0_WAKEUP_ENABLE_MSB              10
+#define GPIO_PIN0_WAKEUP_ENABLE_LSB              10
+#define GPIO_PIN0_WAKEUP_ENABLE_MASK             0x00000400
+#define GPIO_PIN0_WAKEUP_ENABLE_GET(x)           (((x) & GPIO_PIN0_WAKEUP_ENABLE_MASK) >> GPIO_PIN0_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN0_WAKEUP_ENABLE_SET(x)           (((x) << GPIO_PIN0_WAKEUP_ENABLE_LSB) & GPIO_PIN0_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN0_INT_TYPE_MSB                   9
+#define GPIO_PIN0_INT_TYPE_LSB                   7
+#define GPIO_PIN0_INT_TYPE_MASK                  0x00000380
+#define GPIO_PIN0_INT_TYPE_GET(x)                (((x) & GPIO_PIN0_INT_TYPE_MASK) >> GPIO_PIN0_INT_TYPE_LSB)
+#define GPIO_PIN0_INT_TYPE_SET(x)                (((x) << GPIO_PIN0_INT_TYPE_LSB) & GPIO_PIN0_INT_TYPE_MASK)
+#define GPIO_PIN0_PAD_DRIVER_MSB                 2
+#define GPIO_PIN0_PAD_DRIVER_LSB                 2
+#define GPIO_PIN0_PAD_DRIVER_MASK                0x00000004
+#define GPIO_PIN0_PAD_DRIVER_GET(x)              (((x) & GPIO_PIN0_PAD_DRIVER_MASK) >> GPIO_PIN0_PAD_DRIVER_LSB)
+#define GPIO_PIN0_PAD_DRIVER_SET(x)              (((x) << GPIO_PIN0_PAD_DRIVER_LSB) & GPIO_PIN0_PAD_DRIVER_MASK)
+#define GPIO_PIN0_SOURCE_MSB                     0
+#define GPIO_PIN0_SOURCE_LSB                     0
+#define GPIO_PIN0_SOURCE_MASK                    0x00000001
+#define GPIO_PIN0_SOURCE_GET(x)                  (((x) & GPIO_PIN0_SOURCE_MASK) >> GPIO_PIN0_SOURCE_LSB)
+#define GPIO_PIN0_SOURCE_SET(x)                  (((x) << GPIO_PIN0_SOURCE_LSB) & GPIO_PIN0_SOURCE_MASK)
+
+#define GPIO_PIN1_ADDRESS                        0x0000002c
+#define GPIO_PIN1_OFFSET                         0x0000002c
+#define GPIO_PIN1_CONFIG_MSB                     12
+#define GPIO_PIN1_CONFIG_LSB                     11
+#define GPIO_PIN1_CONFIG_MASK                    0x00001800
+#define GPIO_PIN1_CONFIG_GET(x)                  (((x) & GPIO_PIN1_CONFIG_MASK) >> GPIO_PIN1_CONFIG_LSB)
+#define GPIO_PIN1_CONFIG_SET(x)                  (((x) << GPIO_PIN1_CONFIG_LSB) & GPIO_PIN1_CONFIG_MASK)
+#define GPIO_PIN1_WAKEUP_ENABLE_MSB              10
+#define GPIO_PIN1_WAKEUP_ENABLE_LSB              10
+#define GPIO_PIN1_WAKEUP_ENABLE_MASK             0x00000400
+#define GPIO_PIN1_WAKEUP_ENABLE_GET(x)           (((x) & GPIO_PIN1_WAKEUP_ENABLE_MASK) >> GPIO_PIN1_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN1_WAKEUP_ENABLE_SET(x)           (((x) << GPIO_PIN1_WAKEUP_ENABLE_LSB) & GPIO_PIN1_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN1_INT_TYPE_MSB                   9
+#define GPIO_PIN1_INT_TYPE_LSB                   7
+#define GPIO_PIN1_INT_TYPE_MASK                  0x00000380
+#define GPIO_PIN1_INT_TYPE_GET(x)                (((x) & GPIO_PIN1_INT_TYPE_MASK) >> GPIO_PIN1_INT_TYPE_LSB)
+#define GPIO_PIN1_INT_TYPE_SET(x)                (((x) << GPIO_PIN1_INT_TYPE_LSB) & GPIO_PIN1_INT_TYPE_MASK)
+#define GPIO_PIN1_PAD_DRIVER_MSB                 2
+#define GPIO_PIN1_PAD_DRIVER_LSB                 2
+#define GPIO_PIN1_PAD_DRIVER_MASK                0x00000004
+#define GPIO_PIN1_PAD_DRIVER_GET(x)              (((x) & GPIO_PIN1_PAD_DRIVER_MASK) >> GPIO_PIN1_PAD_DRIVER_LSB)
+#define GPIO_PIN1_PAD_DRIVER_SET(x)              (((x) << GPIO_PIN1_PAD_DRIVER_LSB) & GPIO_PIN1_PAD_DRIVER_MASK)
+#define GPIO_PIN1_SOURCE_MSB                     0
+#define GPIO_PIN1_SOURCE_LSB                     0
+#define GPIO_PIN1_SOURCE_MASK                    0x00000001
+#define GPIO_PIN1_SOURCE_GET(x)                  (((x) & GPIO_PIN1_SOURCE_MASK) >> GPIO_PIN1_SOURCE_LSB)
+#define GPIO_PIN1_SOURCE_SET(x)                  (((x) << GPIO_PIN1_SOURCE_LSB) & GPIO_PIN1_SOURCE_MASK)
+
+#define GPIO_PIN2_ADDRESS                        0x00000030
+#define GPIO_PIN2_OFFSET                         0x00000030
+#define GPIO_PIN2_CONFIG_MSB                     12
+#define GPIO_PIN2_CONFIG_LSB                     11
+#define GPIO_PIN2_CONFIG_MASK                    0x00001800
+#define GPIO_PIN2_CONFIG_GET(x)                  (((x) & GPIO_PIN2_CONFIG_MASK) >> GPIO_PIN2_CONFIG_LSB)
+#define GPIO_PIN2_CONFIG_SET(x)                  (((x) << GPIO_PIN2_CONFIG_LSB) & GPIO_PIN2_CONFIG_MASK)
+#define GPIO_PIN2_WAKEUP_ENABLE_MSB              10
+#define GPIO_PIN2_WAKEUP_ENABLE_LSB              10
+#define GPIO_PIN2_WAKEUP_ENABLE_MASK             0x00000400
+#define GPIO_PIN2_WAKEUP_ENABLE_GET(x)           (((x) & GPIO_PIN2_WAKEUP_ENABLE_MASK) >> GPIO_PIN2_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN2_WAKEUP_ENABLE_SET(x)           (((x) << GPIO_PIN2_WAKEUP_ENABLE_LSB) & GPIO_PIN2_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN2_INT_TYPE_MSB                   9
+#define GPIO_PIN2_INT_TYPE_LSB                   7
+#define GPIO_PIN2_INT_TYPE_MASK                  0x00000380
+#define GPIO_PIN2_INT_TYPE_GET(x)                (((x) & GPIO_PIN2_INT_TYPE_MASK) >> GPIO_PIN2_INT_TYPE_LSB)
+#define GPIO_PIN2_INT_TYPE_SET(x)                (((x) << GPIO_PIN2_INT_TYPE_LSB) & GPIO_PIN2_INT_TYPE_MASK)
+#define GPIO_PIN2_PAD_DRIVER_MSB                 2
+#define GPIO_PIN2_PAD_DRIVER_LSB                 2
+#define GPIO_PIN2_PAD_DRIVER_MASK                0x00000004
+#define GPIO_PIN2_PAD_DRIVER_GET(x)              (((x) & GPIO_PIN2_PAD_DRIVER_MASK) >> GPIO_PIN2_PAD_DRIVER_LSB)
+#define GPIO_PIN2_PAD_DRIVER_SET(x)              (((x) << GPIO_PIN2_PAD_DRIVER_LSB) & GPIO_PIN2_PAD_DRIVER_MASK)
+#define GPIO_PIN2_SOURCE_MSB                     0
+#define GPIO_PIN2_SOURCE_LSB                     0
+#define GPIO_PIN2_SOURCE_MASK                    0x00000001
+#define GPIO_PIN2_SOURCE_GET(x)                  (((x) & GPIO_PIN2_SOURCE_MASK) >> GPIO_PIN2_SOURCE_LSB)
+#define GPIO_PIN2_SOURCE_SET(x)                  (((x) << GPIO_PIN2_SOURCE_LSB) & GPIO_PIN2_SOURCE_MASK)
+
+#define GPIO_PIN3_ADDRESS                        0x00000034
+#define GPIO_PIN3_OFFSET                         0x00000034
+#define GPIO_PIN3_CONFIG_MSB                     12
+#define GPIO_PIN3_CONFIG_LSB                     11
+#define GPIO_PIN3_CONFIG_MASK                    0x00001800
+#define GPIO_PIN3_CONFIG_GET(x)                  (((x) & GPIO_PIN3_CONFIG_MASK) >> GPIO_PIN3_CONFIG_LSB)
+#define GPIO_PIN3_CONFIG_SET(x)                  (((x) << GPIO_PIN3_CONFIG_LSB) & GPIO_PIN3_CONFIG_MASK)
+#define GPIO_PIN3_WAKEUP_ENABLE_MSB              10
+#define GPIO_PIN3_WAKEUP_ENABLE_LSB              10
+#define GPIO_PIN3_WAKEUP_ENABLE_MASK             0x00000400
+#define GPIO_PIN3_WAKEUP_ENABLE_GET(x)           (((x) & GPIO_PIN3_WAKEUP_ENABLE_MASK) >> GPIO_PIN3_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN3_WAKEUP_ENABLE_SET(x)           (((x) << GPIO_PIN3_WAKEUP_ENABLE_LSB) & GPIO_PIN3_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN3_INT_TYPE_MSB                   9
+#define GPIO_PIN3_INT_TYPE_LSB                   7
+#define GPIO_PIN3_INT_TYPE_MASK                  0x00000380
+#define GPIO_PIN3_INT_TYPE_GET(x)                (((x) & GPIO_PIN3_INT_TYPE_MASK) >> GPIO_PIN3_INT_TYPE_LSB)
+#define GPIO_PIN3_INT_TYPE_SET(x)                (((x) << GPIO_PIN3_INT_TYPE_LSB) & GPIO_PIN3_INT_TYPE_MASK)
+#define GPIO_PIN3_PAD_DRIVER_MSB                 2
+#define GPIO_PIN3_PAD_DRIVER_LSB                 2
+#define GPIO_PIN3_PAD_DRIVER_MASK                0x00000004
+#define GPIO_PIN3_PAD_DRIVER_GET(x)              (((x) & GPIO_PIN3_PAD_DRIVER_MASK) >> GPIO_PIN3_PAD_DRIVER_LSB)
+#define GPIO_PIN3_PAD_DRIVER_SET(x)              (((x) << GPIO_PIN3_PAD_DRIVER_LSB) & GPIO_PIN3_PAD_DRIVER_MASK)
+#define GPIO_PIN3_SOURCE_MSB                     0
+#define GPIO_PIN3_SOURCE_LSB                     0
+#define GPIO_PIN3_SOURCE_MASK                    0x00000001
+#define GPIO_PIN3_SOURCE_GET(x)                  (((x) & GPIO_PIN3_SOURCE_MASK) >> GPIO_PIN3_SOURCE_LSB)
+#define GPIO_PIN3_SOURCE_SET(x)                  (((x) << GPIO_PIN3_SOURCE_LSB) & GPIO_PIN3_SOURCE_MASK)
+
+#define GPIO_PIN4_ADDRESS                        0x00000038
+#define GPIO_PIN4_OFFSET                         0x00000038
+#define GPIO_PIN4_CONFIG_MSB                     12
+#define GPIO_PIN4_CONFIG_LSB                     11
+#define GPIO_PIN4_CONFIG_MASK                    0x00001800
+#define GPIO_PIN4_CONFIG_GET(x)                  (((x) & GPIO_PIN4_CONFIG_MASK) >> GPIO_PIN4_CONFIG_LSB)
+#define GPIO_PIN4_CONFIG_SET(x)                  (((x) << GPIO_PIN4_CONFIG_LSB) & GPIO_PIN4_CONFIG_MASK)
+#define GPIO_PIN4_WAKEUP_ENABLE_MSB              10
+#define GPIO_PIN4_WAKEUP_ENABLE_LSB              10
+#define GPIO_PIN4_WAKEUP_ENABLE_MASK             0x00000400
+#define GPIO_PIN4_WAKEUP_ENABLE_GET(x)           (((x) & GPIO_PIN4_WAKEUP_ENABLE_MASK) >> GPIO_PIN4_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN4_WAKEUP_ENABLE_SET(x)           (((x) << GPIO_PIN4_WAKEUP_ENABLE_LSB) & GPIO_PIN4_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN4_INT_TYPE_MSB                   9
+#define GPIO_PIN4_INT_TYPE_LSB                   7
+#define GPIO_PIN4_INT_TYPE_MASK                  0x00000380
+#define GPIO_PIN4_INT_TYPE_GET(x)                (((x) & GPIO_PIN4_INT_TYPE_MASK) >> GPIO_PIN4_INT_TYPE_LSB)
+#define GPIO_PIN4_INT_TYPE_SET(x)                (((x) << GPIO_PIN4_INT_TYPE_LSB) & GPIO_PIN4_INT_TYPE_MASK)
+#define GPIO_PIN4_PAD_DRIVER_MSB                 2
+#define GPIO_PIN4_PAD_DRIVER_LSB                 2
+#define GPIO_PIN4_PAD_DRIVER_MASK                0x00000004
+#define GPIO_PIN4_PAD_DRIVER_GET(x)              (((x) & GPIO_PIN4_PAD_DRIVER_MASK) >> GPIO_PIN4_PAD_DRIVER_LSB)
+#define GPIO_PIN4_PAD_DRIVER_SET(x)              (((x) << GPIO_PIN4_PAD_DRIVER_LSB) & GPIO_PIN4_PAD_DRIVER_MASK)
+#define GPIO_PIN4_SOURCE_MSB                     0
+#define GPIO_PIN4_SOURCE_LSB                     0
+#define GPIO_PIN4_SOURCE_MASK                    0x00000001
+#define GPIO_PIN4_SOURCE_GET(x)                  (((x) & GPIO_PIN4_SOURCE_MASK) >> GPIO_PIN4_SOURCE_LSB)
+#define GPIO_PIN4_SOURCE_SET(x)                  (((x) << GPIO_PIN4_SOURCE_LSB) & GPIO_PIN4_SOURCE_MASK)
+
+#define GPIO_PIN5_ADDRESS                        0x0000003c
+#define GPIO_PIN5_OFFSET                         0x0000003c
+#define GPIO_PIN5_CONFIG_MSB                     12
+#define GPIO_PIN5_CONFIG_LSB                     11
+#define GPIO_PIN5_CONFIG_MASK                    0x00001800
+#define GPIO_PIN5_CONFIG_GET(x)                  (((x) & GPIO_PIN5_CONFIG_MASK) >> GPIO_PIN5_CONFIG_LSB)
+#define GPIO_PIN5_CONFIG_SET(x)                  (((x) << GPIO_PIN5_CONFIG_LSB) & GPIO_PIN5_CONFIG_MASK)
+#define GPIO_PIN5_WAKEUP_ENABLE_MSB              10
+#define GPIO_PIN5_WAKEUP_ENABLE_LSB              10
+#define GPIO_PIN5_WAKEUP_ENABLE_MASK             0x00000400
+#define GPIO_PIN5_WAKEUP_ENABLE_GET(x)           (((x) & GPIO_PIN5_WAKEUP_ENABLE_MASK) >> GPIO_PIN5_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN5_WAKEUP_ENABLE_SET(x)           (((x) << GPIO_PIN5_WAKEUP_ENABLE_LSB) & GPIO_PIN5_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN5_INT_TYPE_MSB                   9
+#define GPIO_PIN5_INT_TYPE_LSB                   7
+#define GPIO_PIN5_INT_TYPE_MASK                  0x00000380
+#define GPIO_PIN5_INT_TYPE_GET(x)                (((x) & GPIO_PIN5_INT_TYPE_MASK) >> GPIO_PIN5_INT_TYPE_LSB)
+#define GPIO_PIN5_INT_TYPE_SET(x)                (((x) << GPIO_PIN5_INT_TYPE_LSB) & GPIO_PIN5_INT_TYPE_MASK)
+#define GPIO_PIN5_PAD_DRIVER_MSB                 2
+#define GPIO_PIN5_PAD_DRIVER_LSB                 2
+#define GPIO_PIN5_PAD_DRIVER_MASK                0x00000004
+#define GPIO_PIN5_PAD_DRIVER_GET(x)              (((x) & GPIO_PIN5_PAD_DRIVER_MASK) >> GPIO_PIN5_PAD_DRIVER_LSB)
+#define GPIO_PIN5_PAD_DRIVER_SET(x)              (((x) << GPIO_PIN5_PAD_DRIVER_LSB) & GPIO_PIN5_PAD_DRIVER_MASK)
+#define GPIO_PIN5_SOURCE_MSB                     0
+#define GPIO_PIN5_SOURCE_LSB                     0
+#define GPIO_PIN5_SOURCE_MASK                    0x00000001
+#define GPIO_PIN5_SOURCE_GET(x)                  (((x) & GPIO_PIN5_SOURCE_MASK) >> GPIO_PIN5_SOURCE_LSB)
+#define GPIO_PIN5_SOURCE_SET(x)                  (((x) << GPIO_PIN5_SOURCE_LSB) & GPIO_PIN5_SOURCE_MASK)
+
+#define GPIO_PIN6_ADDRESS                        0x00000040
+#define GPIO_PIN6_OFFSET                         0x00000040
+#define GPIO_PIN6_CONFIG_MSB                     12
+#define GPIO_PIN6_CONFIG_LSB                     11
+#define GPIO_PIN6_CONFIG_MASK                    0x00001800
+#define GPIO_PIN6_CONFIG_GET(x)                  (((x) & GPIO_PIN6_CONFIG_MASK) >> GPIO_PIN6_CONFIG_LSB)
+#define GPIO_PIN6_CONFIG_SET(x)                  (((x) << GPIO_PIN6_CONFIG_LSB) & GPIO_PIN6_CONFIG_MASK)
+#define GPIO_PIN6_WAKEUP_ENABLE_MSB              10
+#define GPIO_PIN6_WAKEUP_ENABLE_LSB              10
+#define GPIO_PIN6_WAKEUP_ENABLE_MASK             0x00000400
+#define GPIO_PIN6_WAKEUP_ENABLE_GET(x)           (((x) & GPIO_PIN6_WAKEUP_ENABLE_MASK) >> GPIO_PIN6_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN6_WAKEUP_ENABLE_SET(x)           (((x) << GPIO_PIN6_WAKEUP_ENABLE_LSB) & GPIO_PIN6_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN6_INT_TYPE_MSB                   9
+#define GPIO_PIN6_INT_TYPE_LSB                   7
+#define GPIO_PIN6_INT_TYPE_MASK                  0x00000380
+#define GPIO_PIN6_INT_TYPE_GET(x)                (((x) & GPIO_PIN6_INT_TYPE_MASK) >> GPIO_PIN6_INT_TYPE_LSB)
+#define GPIO_PIN6_INT_TYPE_SET(x)                (((x) << GPIO_PIN6_INT_TYPE_LSB) & GPIO_PIN6_INT_TYPE_MASK)
+#define GPIO_PIN6_PAD_DRIVER_MSB                 2
+#define GPIO_PIN6_PAD_DRIVER_LSB                 2
+#define GPIO_PIN6_PAD_DRIVER_MASK                0x00000004
+#define GPIO_PIN6_PAD_DRIVER_GET(x)              (((x) & GPIO_PIN6_PAD_DRIVER_MASK) >> GPIO_PIN6_PAD_DRIVER_LSB)
+#define GPIO_PIN6_PAD_DRIVER_SET(x)              (((x) << GPIO_PIN6_PAD_DRIVER_LSB) & GPIO_PIN6_PAD_DRIVER_MASK)
+#define GPIO_PIN6_SOURCE_MSB                     0
+#define GPIO_PIN6_SOURCE_LSB                     0
+#define GPIO_PIN6_SOURCE_MASK                    0x00000001
+#define GPIO_PIN6_SOURCE_GET(x)                  (((x) & GPIO_PIN6_SOURCE_MASK) >> GPIO_PIN6_SOURCE_LSB)
+#define GPIO_PIN6_SOURCE_SET(x)                  (((x) << GPIO_PIN6_SOURCE_LSB) & GPIO_PIN6_SOURCE_MASK)
+
+#define GPIO_PIN7_ADDRESS                        0x00000044
+#define GPIO_PIN7_OFFSET                         0x00000044
+#define GPIO_PIN7_CONFIG_MSB                     12
+#define GPIO_PIN7_CONFIG_LSB                     11
+#define GPIO_PIN7_CONFIG_MASK                    0x00001800
+#define GPIO_PIN7_CONFIG_GET(x)                  (((x) & GPIO_PIN7_CONFIG_MASK) >> GPIO_PIN7_CONFIG_LSB)
+#define GPIO_PIN7_CONFIG_SET(x)                  (((x) << GPIO_PIN7_CONFIG_LSB) & GPIO_PIN7_CONFIG_MASK)
+#define GPIO_PIN7_WAKEUP_ENABLE_MSB              10
+#define GPIO_PIN7_WAKEUP_ENABLE_LSB              10
+#define GPIO_PIN7_WAKEUP_ENABLE_MASK             0x00000400
+#define GPIO_PIN7_WAKEUP_ENABLE_GET(x)           (((x) & GPIO_PIN7_WAKEUP_ENABLE_MASK) >> GPIO_PIN7_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN7_WAKEUP_ENABLE_SET(x)           (((x) << GPIO_PIN7_WAKEUP_ENABLE_LSB) & GPIO_PIN7_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN7_INT_TYPE_MSB                   9
+#define GPIO_PIN7_INT_TYPE_LSB                   7
+#define GPIO_PIN7_INT_TYPE_MASK                  0x00000380
+#define GPIO_PIN7_INT_TYPE_GET(x)                (((x) & GPIO_PIN7_INT_TYPE_MASK) >> GPIO_PIN7_INT_TYPE_LSB)
+#define GPIO_PIN7_INT_TYPE_SET(x)                (((x) << GPIO_PIN7_INT_TYPE_LSB) & GPIO_PIN7_INT_TYPE_MASK)
+#define GPIO_PIN7_PAD_DRIVER_MSB                 2
+#define GPIO_PIN7_PAD_DRIVER_LSB                 2
+#define GPIO_PIN7_PAD_DRIVER_MASK                0x00000004
+#define GPIO_PIN7_PAD_DRIVER_GET(x)              (((x) & GPIO_PIN7_PAD_DRIVER_MASK) >> GPIO_PIN7_PAD_DRIVER_LSB)
+#define GPIO_PIN7_PAD_DRIVER_SET(x)              (((x) << GPIO_PIN7_PAD_DRIVER_LSB) & GPIO_PIN7_PAD_DRIVER_MASK)
+#define GPIO_PIN7_SOURCE_MSB                     0
+#define GPIO_PIN7_SOURCE_LSB                     0
+#define GPIO_PIN7_SOURCE_MASK                    0x00000001
+#define GPIO_PIN7_SOURCE_GET(x)                  (((x) & GPIO_PIN7_SOURCE_MASK) >> GPIO_PIN7_SOURCE_LSB)
+#define GPIO_PIN7_SOURCE_SET(x)                  (((x) << GPIO_PIN7_SOURCE_LSB) & GPIO_PIN7_SOURCE_MASK)
+
+#define GPIO_PIN8_ADDRESS                        0x00000048
+#define GPIO_PIN8_OFFSET                         0x00000048
+#define GPIO_PIN8_CONFIG_MSB                     12
+#define GPIO_PIN8_CONFIG_LSB                     11
+#define GPIO_PIN8_CONFIG_MASK                    0x00001800
+#define GPIO_PIN8_CONFIG_GET(x)                  (((x) & GPIO_PIN8_CONFIG_MASK) >> GPIO_PIN8_CONFIG_LSB)
+#define GPIO_PIN8_CONFIG_SET(x)                  (((x) << GPIO_PIN8_CONFIG_LSB) & GPIO_PIN8_CONFIG_MASK)
+#define GPIO_PIN8_WAKEUP_ENABLE_MSB              10
+#define GPIO_PIN8_WAKEUP_ENABLE_LSB              10
+#define GPIO_PIN8_WAKEUP_ENABLE_MASK             0x00000400
+#define GPIO_PIN8_WAKEUP_ENABLE_GET(x)           (((x) & GPIO_PIN8_WAKEUP_ENABLE_MASK) >> GPIO_PIN8_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN8_WAKEUP_ENABLE_SET(x)           (((x) << GPIO_PIN8_WAKEUP_ENABLE_LSB) & GPIO_PIN8_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN8_INT_TYPE_MSB                   9
+#define GPIO_PIN8_INT_TYPE_LSB                   7
+#define GPIO_PIN8_INT_TYPE_MASK                  0x00000380
+#define GPIO_PIN8_INT_TYPE_GET(x)                (((x) & GPIO_PIN8_INT_TYPE_MASK) >> GPIO_PIN8_INT_TYPE_LSB)
+#define GPIO_PIN8_INT_TYPE_SET(x)                (((x) << GPIO_PIN8_INT_TYPE_LSB) & GPIO_PIN8_INT_TYPE_MASK)
+#define GPIO_PIN8_PAD_DRIVER_MSB                 2
+#define GPIO_PIN8_PAD_DRIVER_LSB                 2
+#define GPIO_PIN8_PAD_DRIVER_MASK                0x00000004
+#define GPIO_PIN8_PAD_DRIVER_GET(x)              (((x) & GPIO_PIN8_PAD_DRIVER_MASK) >> GPIO_PIN8_PAD_DRIVER_LSB)
+#define GPIO_PIN8_PAD_DRIVER_SET(x)              (((x) << GPIO_PIN8_PAD_DRIVER_LSB) & GPIO_PIN8_PAD_DRIVER_MASK)
+#define GPIO_PIN8_SOURCE_MSB                     0
+#define GPIO_PIN8_SOURCE_LSB                     0
+#define GPIO_PIN8_SOURCE_MASK                    0x00000001
+#define GPIO_PIN8_SOURCE_GET(x)                  (((x) & GPIO_PIN8_SOURCE_MASK) >> GPIO_PIN8_SOURCE_LSB)
+#define GPIO_PIN8_SOURCE_SET(x)                  (((x) << GPIO_PIN8_SOURCE_LSB) & GPIO_PIN8_SOURCE_MASK)
+
+#define GPIO_PIN9_ADDRESS                        0x0000004c
+#define GPIO_PIN9_OFFSET                         0x0000004c
+#define GPIO_PIN9_CONFIG_MSB                     12
+#define GPIO_PIN9_CONFIG_LSB                     11
+#define GPIO_PIN9_CONFIG_MASK                    0x00001800
+#define GPIO_PIN9_CONFIG_GET(x)                  (((x) & GPIO_PIN9_CONFIG_MASK) >> GPIO_PIN9_CONFIG_LSB)
+#define GPIO_PIN9_CONFIG_SET(x)                  (((x) << GPIO_PIN9_CONFIG_LSB) & GPIO_PIN9_CONFIG_MASK)
+#define GPIO_PIN9_WAKEUP_ENABLE_MSB              10
+#define GPIO_PIN9_WAKEUP_ENABLE_LSB              10
+#define GPIO_PIN9_WAKEUP_ENABLE_MASK             0x00000400
+#define GPIO_PIN9_WAKEUP_ENABLE_GET(x)           (((x) & GPIO_PIN9_WAKEUP_ENABLE_MASK) >> GPIO_PIN9_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN9_WAKEUP_ENABLE_SET(x)           (((x) << GPIO_PIN9_WAKEUP_ENABLE_LSB) & GPIO_PIN9_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN9_INT_TYPE_MSB                   9
+#define GPIO_PIN9_INT_TYPE_LSB                   7
+#define GPIO_PIN9_INT_TYPE_MASK                  0x00000380
+#define GPIO_PIN9_INT_TYPE_GET(x)                (((x) & GPIO_PIN9_INT_TYPE_MASK) >> GPIO_PIN9_INT_TYPE_LSB)
+#define GPIO_PIN9_INT_TYPE_SET(x)                (((x) << GPIO_PIN9_INT_TYPE_LSB) & GPIO_PIN9_INT_TYPE_MASK)
+#define GPIO_PIN9_PAD_DRIVER_MSB                 2
+#define GPIO_PIN9_PAD_DRIVER_LSB                 2
+#define GPIO_PIN9_PAD_DRIVER_MASK                0x00000004
+#define GPIO_PIN9_PAD_DRIVER_GET(x)              (((x) & GPIO_PIN9_PAD_DRIVER_MASK) >> GPIO_PIN9_PAD_DRIVER_LSB)
+#define GPIO_PIN9_PAD_DRIVER_SET(x)              (((x) << GPIO_PIN9_PAD_DRIVER_LSB) & GPIO_PIN9_PAD_DRIVER_MASK)
+#define GPIO_PIN9_SOURCE_MSB                     0
+#define GPIO_PIN9_SOURCE_LSB                     0
+#define GPIO_PIN9_SOURCE_MASK                    0x00000001
+#define GPIO_PIN9_SOURCE_GET(x)                  (((x) & GPIO_PIN9_SOURCE_MASK) >> GPIO_PIN9_SOURCE_LSB)
+#define GPIO_PIN9_SOURCE_SET(x)                  (((x) << GPIO_PIN9_SOURCE_LSB) & GPIO_PIN9_SOURCE_MASK)
+
+#define GPIO_PIN10_ADDRESS                       0x00000050
+#define GPIO_PIN10_OFFSET                        0x00000050
+#define GPIO_PIN10_CONFIG_MSB                    12
+#define GPIO_PIN10_CONFIG_LSB                    11
+#define GPIO_PIN10_CONFIG_MASK                   0x00001800
+#define GPIO_PIN10_CONFIG_GET(x)                 (((x) & GPIO_PIN10_CONFIG_MASK) >> GPIO_PIN10_CONFIG_LSB)
+#define GPIO_PIN10_CONFIG_SET(x)                 (((x) << GPIO_PIN10_CONFIG_LSB) & GPIO_PIN10_CONFIG_MASK)
+#define GPIO_PIN10_WAKEUP_ENABLE_MSB             10
+#define GPIO_PIN10_WAKEUP_ENABLE_LSB             10
+#define GPIO_PIN10_WAKEUP_ENABLE_MASK            0x00000400
+#define GPIO_PIN10_WAKEUP_ENABLE_GET(x)          (((x) & GPIO_PIN10_WAKEUP_ENABLE_MASK) >> GPIO_PIN10_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN10_WAKEUP_ENABLE_SET(x)          (((x) << GPIO_PIN10_WAKEUP_ENABLE_LSB) & GPIO_PIN10_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN10_INT_TYPE_MSB                  9
+#define GPIO_PIN10_INT_TYPE_LSB                  7
+#define GPIO_PIN10_INT_TYPE_MASK                 0x00000380
+#define GPIO_PIN10_INT_TYPE_GET(x)               (((x) & GPIO_PIN10_INT_TYPE_MASK) >> GPIO_PIN10_INT_TYPE_LSB)
+#define GPIO_PIN10_INT_TYPE_SET(x)               (((x) << GPIO_PIN10_INT_TYPE_LSB) & GPIO_PIN10_INT_TYPE_MASK)
+#define GPIO_PIN10_PAD_DRIVER_MSB                2
+#define GPIO_PIN10_PAD_DRIVER_LSB                2
+#define GPIO_PIN10_PAD_DRIVER_MASK               0x00000004
+#define GPIO_PIN10_PAD_DRIVER_GET(x)             (((x) & GPIO_PIN10_PAD_DRIVER_MASK) >> GPIO_PIN10_PAD_DRIVER_LSB)
+#define GPIO_PIN10_PAD_DRIVER_SET(x)             (((x) << GPIO_PIN10_PAD_DRIVER_LSB) & GPIO_PIN10_PAD_DRIVER_MASK)
+#define GPIO_PIN10_SOURCE_MSB                    0
+#define GPIO_PIN10_SOURCE_LSB                    0
+#define GPIO_PIN10_SOURCE_MASK                   0x00000001
+#define GPIO_PIN10_SOURCE_GET(x)                 (((x) & GPIO_PIN10_SOURCE_MASK) >> GPIO_PIN10_SOURCE_LSB)
+#define GPIO_PIN10_SOURCE_SET(x)                 (((x) << GPIO_PIN10_SOURCE_LSB) & GPIO_PIN10_SOURCE_MASK)
+
+#define GPIO_PIN11_ADDRESS                       0x00000054
+#define GPIO_PIN11_OFFSET                        0x00000054
+#define GPIO_PIN11_CONFIG_MSB                    12
+#define GPIO_PIN11_CONFIG_LSB                    11
+#define GPIO_PIN11_CONFIG_MASK                   0x00001800
+#define GPIO_PIN11_CONFIG_GET(x)                 (((x) & GPIO_PIN11_CONFIG_MASK) >> GPIO_PIN11_CONFIG_LSB)
+#define GPIO_PIN11_CONFIG_SET(x)                 (((x) << GPIO_PIN11_CONFIG_LSB) & GPIO_PIN11_CONFIG_MASK)
+#define GPIO_PIN11_WAKEUP_ENABLE_MSB             10
+#define GPIO_PIN11_WAKEUP_ENABLE_LSB             10
+#define GPIO_PIN11_WAKEUP_ENABLE_MASK            0x00000400
+#define GPIO_PIN11_WAKEUP_ENABLE_GET(x)          (((x) & GPIO_PIN11_WAKEUP_ENABLE_MASK) >> GPIO_PIN11_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN11_WAKEUP_ENABLE_SET(x)          (((x) << GPIO_PIN11_WAKEUP_ENABLE_LSB) & GPIO_PIN11_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN11_INT_TYPE_MSB                  9
+#define GPIO_PIN11_INT_TYPE_LSB                  7
+#define GPIO_PIN11_INT_TYPE_MASK                 0x00000380
+#define GPIO_PIN11_INT_TYPE_GET(x)               (((x) & GPIO_PIN11_INT_TYPE_MASK) >> GPIO_PIN11_INT_TYPE_LSB)
+#define GPIO_PIN11_INT_TYPE_SET(x)               (((x) << GPIO_PIN11_INT_TYPE_LSB) & GPIO_PIN11_INT_TYPE_MASK)
+#define GPIO_PIN11_PAD_DRIVER_MSB                2
+#define GPIO_PIN11_PAD_DRIVER_LSB                2
+#define GPIO_PIN11_PAD_DRIVER_MASK               0x00000004
+#define GPIO_PIN11_PAD_DRIVER_GET(x)             (((x) & GPIO_PIN11_PAD_DRIVER_MASK) >> GPIO_PIN11_PAD_DRIVER_LSB)
+#define GPIO_PIN11_PAD_DRIVER_SET(x)             (((x) << GPIO_PIN11_PAD_DRIVER_LSB) & GPIO_PIN11_PAD_DRIVER_MASK)
+#define GPIO_PIN11_SOURCE_MSB                    0
+#define GPIO_PIN11_SOURCE_LSB                    0
+#define GPIO_PIN11_SOURCE_MASK                   0x00000001
+#define GPIO_PIN11_SOURCE_GET(x)                 (((x) & GPIO_PIN11_SOURCE_MASK) >> GPIO_PIN11_SOURCE_LSB)
+#define GPIO_PIN11_SOURCE_SET(x)                 (((x) << GPIO_PIN11_SOURCE_LSB) & GPIO_PIN11_SOURCE_MASK)
+
+#define GPIO_PIN12_ADDRESS                       0x00000058
+#define GPIO_PIN12_OFFSET                        0x00000058
+#define GPIO_PIN12_CONFIG_MSB                    12
+#define GPIO_PIN12_CONFIG_LSB                    11
+#define GPIO_PIN12_CONFIG_MASK                   0x00001800
+#define GPIO_PIN12_CONFIG_GET(x)                 (((x) & GPIO_PIN12_CONFIG_MASK) >> GPIO_PIN12_CONFIG_LSB)
+#define GPIO_PIN12_CONFIG_SET(x)                 (((x) << GPIO_PIN12_CONFIG_LSB) & GPIO_PIN12_CONFIG_MASK)
+#define GPIO_PIN12_WAKEUP_ENABLE_MSB             10
+#define GPIO_PIN12_WAKEUP_ENABLE_LSB             10
+#define GPIO_PIN12_WAKEUP_ENABLE_MASK            0x00000400
+#define GPIO_PIN12_WAKEUP_ENABLE_GET(x)          (((x) & GPIO_PIN12_WAKEUP_ENABLE_MASK) >> GPIO_PIN12_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN12_WAKEUP_ENABLE_SET(x)          (((x) << GPIO_PIN12_WAKEUP_ENABLE_LSB) & GPIO_PIN12_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN12_INT_TYPE_MSB                  9
+#define GPIO_PIN12_INT_TYPE_LSB                  7
+#define GPIO_PIN12_INT_TYPE_MASK                 0x00000380
+#define GPIO_PIN12_INT_TYPE_GET(x)               (((x) & GPIO_PIN12_INT_TYPE_MASK) >> GPIO_PIN12_INT_TYPE_LSB)
+#define GPIO_PIN12_INT_TYPE_SET(x)               (((x) << GPIO_PIN12_INT_TYPE_LSB) & GPIO_PIN12_INT_TYPE_MASK)
+#define GPIO_PIN12_PAD_DRIVER_MSB                2
+#define GPIO_PIN12_PAD_DRIVER_LSB                2
+#define GPIO_PIN12_PAD_DRIVER_MASK               0x00000004
+#define GPIO_PIN12_PAD_DRIVER_GET(x)             (((x) & GPIO_PIN12_PAD_DRIVER_MASK) >> GPIO_PIN12_PAD_DRIVER_LSB)
+#define GPIO_PIN12_PAD_DRIVER_SET(x)             (((x) << GPIO_PIN12_PAD_DRIVER_LSB) & GPIO_PIN12_PAD_DRIVER_MASK)
+#define GPIO_PIN12_SOURCE_MSB                    0
+#define GPIO_PIN12_SOURCE_LSB                    0
+#define GPIO_PIN12_SOURCE_MASK                   0x00000001
+#define GPIO_PIN12_SOURCE_GET(x)                 (((x) & GPIO_PIN12_SOURCE_MASK) >> GPIO_PIN12_SOURCE_LSB)
+#define GPIO_PIN12_SOURCE_SET(x)                 (((x) << GPIO_PIN12_SOURCE_LSB) & GPIO_PIN12_SOURCE_MASK)
+
+#define GPIO_PIN13_ADDRESS                       0x0000005c
+#define GPIO_PIN13_OFFSET                        0x0000005c
+#define GPIO_PIN13_CONFIG_MSB                    12
+#define GPIO_PIN13_CONFIG_LSB                    11
+#define GPIO_PIN13_CONFIG_MASK                   0x00001800
+#define GPIO_PIN13_CONFIG_GET(x)                 (((x) & GPIO_PIN13_CONFIG_MASK) >> GPIO_PIN13_CONFIG_LSB)
+#define GPIO_PIN13_CONFIG_SET(x)                 (((x) << GPIO_PIN13_CONFIG_LSB) & GPIO_PIN13_CONFIG_MASK)
+#define GPIO_PIN13_WAKEUP_ENABLE_MSB             10
+#define GPIO_PIN13_WAKEUP_ENABLE_LSB             10
+#define GPIO_PIN13_WAKEUP_ENABLE_MASK            0x00000400
+#define GPIO_PIN13_WAKEUP_ENABLE_GET(x)          (((x) & GPIO_PIN13_WAKEUP_ENABLE_MASK) >> GPIO_PIN13_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN13_WAKEUP_ENABLE_SET(x)          (((x) << GPIO_PIN13_WAKEUP_ENABLE_LSB) & GPIO_PIN13_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN13_INT_TYPE_MSB                  9
+#define GPIO_PIN13_INT_TYPE_LSB                  7
+#define GPIO_PIN13_INT_TYPE_MASK                 0x00000380
+#define GPIO_PIN13_INT_TYPE_GET(x)               (((x) & GPIO_PIN13_INT_TYPE_MASK) >> GPIO_PIN13_INT_TYPE_LSB)
+#define GPIO_PIN13_INT_TYPE_SET(x)               (((x) << GPIO_PIN13_INT_TYPE_LSB) & GPIO_PIN13_INT_TYPE_MASK)
+#define GPIO_PIN13_PAD_DRIVER_MSB                2
+#define GPIO_PIN13_PAD_DRIVER_LSB                2
+#define GPIO_PIN13_PAD_DRIVER_MASK               0x00000004
+#define GPIO_PIN13_PAD_DRIVER_GET(x)             (((x) & GPIO_PIN13_PAD_DRIVER_MASK) >> GPIO_PIN13_PAD_DRIVER_LSB)
+#define GPIO_PIN13_PAD_DRIVER_SET(x)             (((x) << GPIO_PIN13_PAD_DRIVER_LSB) & GPIO_PIN13_PAD_DRIVER_MASK)
+#define GPIO_PIN13_SOURCE_MSB                    0
+#define GPIO_PIN13_SOURCE_LSB                    0
+#define GPIO_PIN13_SOURCE_MASK                   0x00000001
+#define GPIO_PIN13_SOURCE_GET(x)                 (((x) & GPIO_PIN13_SOURCE_MASK) >> GPIO_PIN13_SOURCE_LSB)
+#define GPIO_PIN13_SOURCE_SET(x)                 (((x) << GPIO_PIN13_SOURCE_LSB) & GPIO_PIN13_SOURCE_MASK)
+
+#define GPIO_PIN14_ADDRESS                       0x00000060
+#define GPIO_PIN14_OFFSET                        0x00000060
+#define GPIO_PIN14_CONFIG_MSB                    12
+#define GPIO_PIN14_CONFIG_LSB                    11
+#define GPIO_PIN14_CONFIG_MASK                   0x00001800
+#define GPIO_PIN14_CONFIG_GET(x)                 (((x) & GPIO_PIN14_CONFIG_MASK) >> GPIO_PIN14_CONFIG_LSB)
+#define GPIO_PIN14_CONFIG_SET(x)                 (((x) << GPIO_PIN14_CONFIG_LSB) & GPIO_PIN14_CONFIG_MASK)
+#define GPIO_PIN14_WAKEUP_ENABLE_MSB             10
+#define GPIO_PIN14_WAKEUP_ENABLE_LSB             10
+#define GPIO_PIN14_WAKEUP_ENABLE_MASK            0x00000400
+#define GPIO_PIN14_WAKEUP_ENABLE_GET(x)          (((x) & GPIO_PIN14_WAKEUP_ENABLE_MASK) >> GPIO_PIN14_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN14_WAKEUP_ENABLE_SET(x)          (((x) << GPIO_PIN14_WAKEUP_ENABLE_LSB) & GPIO_PIN14_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN14_INT_TYPE_MSB                  9
+#define GPIO_PIN14_INT_TYPE_LSB                  7
+#define GPIO_PIN14_INT_TYPE_MASK                 0x00000380
+#define GPIO_PIN14_INT_TYPE_GET(x)               (((x) & GPIO_PIN14_INT_TYPE_MASK) >> GPIO_PIN14_INT_TYPE_LSB)
+#define GPIO_PIN14_INT_TYPE_SET(x)               (((x) << GPIO_PIN14_INT_TYPE_LSB) & GPIO_PIN14_INT_TYPE_MASK)
+#define GPIO_PIN14_PAD_DRIVER_MSB                2
+#define GPIO_PIN14_PAD_DRIVER_LSB                2
+#define GPIO_PIN14_PAD_DRIVER_MASK               0x00000004
+#define GPIO_PIN14_PAD_DRIVER_GET(x)             (((x) & GPIO_PIN14_PAD_DRIVER_MASK) >> GPIO_PIN14_PAD_DRIVER_LSB)
+#define GPIO_PIN14_PAD_DRIVER_SET(x)             (((x) << GPIO_PIN14_PAD_DRIVER_LSB) & GPIO_PIN14_PAD_DRIVER_MASK)
+#define GPIO_PIN14_SOURCE_MSB                    0
+#define GPIO_PIN14_SOURCE_LSB                    0
+#define GPIO_PIN14_SOURCE_MASK                   0x00000001
+#define GPIO_PIN14_SOURCE_GET(x)                 (((x) & GPIO_PIN14_SOURCE_MASK) >> GPIO_PIN14_SOURCE_LSB)
+#define GPIO_PIN14_SOURCE_SET(x)                 (((x) << GPIO_PIN14_SOURCE_LSB) & GPIO_PIN14_SOURCE_MASK)
+
+#define GPIO_PIN15_ADDRESS                       0x00000064
+#define GPIO_PIN15_OFFSET                        0x00000064
+#define GPIO_PIN15_CONFIG_MSB                    12
+#define GPIO_PIN15_CONFIG_LSB                    11
+#define GPIO_PIN15_CONFIG_MASK                   0x00001800
+#define GPIO_PIN15_CONFIG_GET(x)                 (((x) & GPIO_PIN15_CONFIG_MASK) >> GPIO_PIN15_CONFIG_LSB)
+#define GPIO_PIN15_CONFIG_SET(x)                 (((x) << GPIO_PIN15_CONFIG_LSB) & GPIO_PIN15_CONFIG_MASK)
+#define GPIO_PIN15_WAKEUP_ENABLE_MSB             10
+#define GPIO_PIN15_WAKEUP_ENABLE_LSB             10
+#define GPIO_PIN15_WAKEUP_ENABLE_MASK            0x00000400
+#define GPIO_PIN15_WAKEUP_ENABLE_GET(x)          (((x) & GPIO_PIN15_WAKEUP_ENABLE_MASK) >> GPIO_PIN15_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN15_WAKEUP_ENABLE_SET(x)          (((x) << GPIO_PIN15_WAKEUP_ENABLE_LSB) & GPIO_PIN15_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN15_INT_TYPE_MSB                  9
+#define GPIO_PIN15_INT_TYPE_LSB                  7
+#define GPIO_PIN15_INT_TYPE_MASK                 0x00000380
+#define GPIO_PIN15_INT_TYPE_GET(x)               (((x) & GPIO_PIN15_INT_TYPE_MASK) >> GPIO_PIN15_INT_TYPE_LSB)
+#define GPIO_PIN15_INT_TYPE_SET(x)               (((x) << GPIO_PIN15_INT_TYPE_LSB) & GPIO_PIN15_INT_TYPE_MASK)
+#define GPIO_PIN15_PAD_DRIVER_MSB                2
+#define GPIO_PIN15_PAD_DRIVER_LSB                2
+#define GPIO_PIN15_PAD_DRIVER_MASK               0x00000004
+#define GPIO_PIN15_PAD_DRIVER_GET(x)             (((x) & GPIO_PIN15_PAD_DRIVER_MASK) >> GPIO_PIN15_PAD_DRIVER_LSB)
+#define GPIO_PIN15_PAD_DRIVER_SET(x)             (((x) << GPIO_PIN15_PAD_DRIVER_LSB) & GPIO_PIN15_PAD_DRIVER_MASK)
+#define GPIO_PIN15_SOURCE_MSB                    0
+#define GPIO_PIN15_SOURCE_LSB                    0
+#define GPIO_PIN15_SOURCE_MASK                   0x00000001
+#define GPIO_PIN15_SOURCE_GET(x)                 (((x) & GPIO_PIN15_SOURCE_MASK) >> GPIO_PIN15_SOURCE_LSB)
+#define GPIO_PIN15_SOURCE_SET(x)                 (((x) << GPIO_PIN15_SOURCE_LSB) & GPIO_PIN15_SOURCE_MASK)
+
+#define GPIO_PIN16_ADDRESS                       0x00000068
+#define GPIO_PIN16_OFFSET                        0x00000068
+#define GPIO_PIN16_CONFIG_MSB                    12
+#define GPIO_PIN16_CONFIG_LSB                    11
+#define GPIO_PIN16_CONFIG_MASK                   0x00001800
+#define GPIO_PIN16_CONFIG_GET(x)                 (((x) & GPIO_PIN16_CONFIG_MASK) >> GPIO_PIN16_CONFIG_LSB)
+#define GPIO_PIN16_CONFIG_SET(x)                 (((x) << GPIO_PIN16_CONFIG_LSB) & GPIO_PIN16_CONFIG_MASK)
+#define GPIO_PIN16_WAKEUP_ENABLE_MSB             10
+#define GPIO_PIN16_WAKEUP_ENABLE_LSB             10
+#define GPIO_PIN16_WAKEUP_ENABLE_MASK            0x00000400
+#define GPIO_PIN16_WAKEUP_ENABLE_GET(x)          (((x) & GPIO_PIN16_WAKEUP_ENABLE_MASK) >> GPIO_PIN16_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN16_WAKEUP_ENABLE_SET(x)          (((x) << GPIO_PIN16_WAKEUP_ENABLE_LSB) & GPIO_PIN16_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN16_INT_TYPE_MSB                  9
+#define GPIO_PIN16_INT_TYPE_LSB                  7
+#define GPIO_PIN16_INT_TYPE_MASK                 0x00000380
+#define GPIO_PIN16_INT_TYPE_GET(x)               (((x) & GPIO_PIN16_INT_TYPE_MASK) >> GPIO_PIN16_INT_TYPE_LSB)
+#define GPIO_PIN16_INT_TYPE_SET(x)               (((x) << GPIO_PIN16_INT_TYPE_LSB) & GPIO_PIN16_INT_TYPE_MASK)
+#define GPIO_PIN16_PAD_DRIVER_MSB                2
+#define GPIO_PIN16_PAD_DRIVER_LSB                2
+#define GPIO_PIN16_PAD_DRIVER_MASK               0x00000004
+#define GPIO_PIN16_PAD_DRIVER_GET(x)             (((x) & GPIO_PIN16_PAD_DRIVER_MASK) >> GPIO_PIN16_PAD_DRIVER_LSB)
+#define GPIO_PIN16_PAD_DRIVER_SET(x)             (((x) << GPIO_PIN16_PAD_DRIVER_LSB) & GPIO_PIN16_PAD_DRIVER_MASK)
+#define GPIO_PIN16_SOURCE_MSB                    0
+#define GPIO_PIN16_SOURCE_LSB                    0
+#define GPIO_PIN16_SOURCE_MASK                   0x00000001
+#define GPIO_PIN16_SOURCE_GET(x)                 (((x) & GPIO_PIN16_SOURCE_MASK) >> GPIO_PIN16_SOURCE_LSB)
+#define GPIO_PIN16_SOURCE_SET(x)                 (((x) << GPIO_PIN16_SOURCE_LSB) & GPIO_PIN16_SOURCE_MASK)
+
+#define GPIO_PIN17_ADDRESS                       0x0000006c
+#define GPIO_PIN17_OFFSET                        0x0000006c
+#define GPIO_PIN17_CONFIG_MSB                    12
+#define GPIO_PIN17_CONFIG_LSB                    11
+#define GPIO_PIN17_CONFIG_MASK                   0x00001800
+#define GPIO_PIN17_CONFIG_GET(x)                 (((x) & GPIO_PIN17_CONFIG_MASK) >> GPIO_PIN17_CONFIG_LSB)
+#define GPIO_PIN17_CONFIG_SET(x)                 (((x) << GPIO_PIN17_CONFIG_LSB) & GPIO_PIN17_CONFIG_MASK)
+#define GPIO_PIN17_WAKEUP_ENABLE_MSB             10
+#define GPIO_PIN17_WAKEUP_ENABLE_LSB             10
+#define GPIO_PIN17_WAKEUP_ENABLE_MASK            0x00000400
+#define GPIO_PIN17_WAKEUP_ENABLE_GET(x)          (((x) & GPIO_PIN17_WAKEUP_ENABLE_MASK) >> GPIO_PIN17_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN17_WAKEUP_ENABLE_SET(x)          (((x) << GPIO_PIN17_WAKEUP_ENABLE_LSB) & GPIO_PIN17_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN17_INT_TYPE_MSB                  9
+#define GPIO_PIN17_INT_TYPE_LSB                  7
+#define GPIO_PIN17_INT_TYPE_MASK                 0x00000380
+#define GPIO_PIN17_INT_TYPE_GET(x)               (((x) & GPIO_PIN17_INT_TYPE_MASK) >> GPIO_PIN17_INT_TYPE_LSB)
+#define GPIO_PIN17_INT_TYPE_SET(x)               (((x) << GPIO_PIN17_INT_TYPE_LSB) & GPIO_PIN17_INT_TYPE_MASK)
+#define GPIO_PIN17_PAD_DRIVER_MSB                2
+#define GPIO_PIN17_PAD_DRIVER_LSB                2
+#define GPIO_PIN17_PAD_DRIVER_MASK               0x00000004
+#define GPIO_PIN17_PAD_DRIVER_GET(x)             (((x) & GPIO_PIN17_PAD_DRIVER_MASK) >> GPIO_PIN17_PAD_DRIVER_LSB)
+#define GPIO_PIN17_PAD_DRIVER_SET(x)             (((x) << GPIO_PIN17_PAD_DRIVER_LSB) & GPIO_PIN17_PAD_DRIVER_MASK)
+#define GPIO_PIN17_SOURCE_MSB                    0
+#define GPIO_PIN17_SOURCE_LSB                    0
+#define GPIO_PIN17_SOURCE_MASK                   0x00000001
+#define GPIO_PIN17_SOURCE_GET(x)                 (((x) & GPIO_PIN17_SOURCE_MASK) >> GPIO_PIN17_SOURCE_LSB)
+#define GPIO_PIN17_SOURCE_SET(x)                 (((x) << GPIO_PIN17_SOURCE_LSB) & GPIO_PIN17_SOURCE_MASK)
+
+#define SDIO_PIN_ADDRESS                         0x00000070
+#define SDIO_PIN_OFFSET                          0x00000070
+#define SDIO_PIN_PAD_PULL_MSB                    3
+#define SDIO_PIN_PAD_PULL_LSB                    2
+#define SDIO_PIN_PAD_PULL_MASK                   0x0000000c
+#define SDIO_PIN_PAD_PULL_GET(x)                 (((x) & SDIO_PIN_PAD_PULL_MASK) >> SDIO_PIN_PAD_PULL_LSB)
+#define SDIO_PIN_PAD_PULL_SET(x)                 (((x) << SDIO_PIN_PAD_PULL_LSB) & SDIO_PIN_PAD_PULL_MASK)
+#define SDIO_PIN_PAD_STRENGTH_MSB                1
+#define SDIO_PIN_PAD_STRENGTH_LSB                0
+#define SDIO_PIN_PAD_STRENGTH_MASK               0x00000003
+#define SDIO_PIN_PAD_STRENGTH_GET(x)             (((x) & SDIO_PIN_PAD_STRENGTH_MASK) >> SDIO_PIN_PAD_STRENGTH_LSB)
+#define SDIO_PIN_PAD_STRENGTH_SET(x)             (((x) << SDIO_PIN_PAD_STRENGTH_LSB) & SDIO_PIN_PAD_STRENGTH_MASK)
+
+#define CLK_REQ_PIN_ADDRESS                      0x00000074
+#define CLK_REQ_PIN_OFFSET                       0x00000074
+#define CLK_REQ_PIN_ATE_OE_L_MSB                 4
+#define CLK_REQ_PIN_ATE_OE_L_LSB                 4
+#define CLK_REQ_PIN_ATE_OE_L_MASK                0x00000010
+#define CLK_REQ_PIN_ATE_OE_L_GET(x)              (((x) & CLK_REQ_PIN_ATE_OE_L_MASK) >> CLK_REQ_PIN_ATE_OE_L_LSB)
+#define CLK_REQ_PIN_ATE_OE_L_SET(x)              (((x) << CLK_REQ_PIN_ATE_OE_L_LSB) & CLK_REQ_PIN_ATE_OE_L_MASK)
+#define CLK_REQ_PIN_PAD_PULL_MSB                 3
+#define CLK_REQ_PIN_PAD_PULL_LSB                 2
+#define CLK_REQ_PIN_PAD_PULL_MASK                0x0000000c
+#define CLK_REQ_PIN_PAD_PULL_GET(x)              (((x) & CLK_REQ_PIN_PAD_PULL_MASK) >> CLK_REQ_PIN_PAD_PULL_LSB)
+#define CLK_REQ_PIN_PAD_PULL_SET(x)              (((x) << CLK_REQ_PIN_PAD_PULL_LSB) & CLK_REQ_PIN_PAD_PULL_MASK)
+#define CLK_REQ_PIN_PAD_STRENGTH_MSB             1
+#define CLK_REQ_PIN_PAD_STRENGTH_LSB             0
+#define CLK_REQ_PIN_PAD_STRENGTH_MASK            0x00000003
+#define CLK_REQ_PIN_PAD_STRENGTH_GET(x)          (((x) & CLK_REQ_PIN_PAD_STRENGTH_MASK) >> CLK_REQ_PIN_PAD_STRENGTH_LSB)
+#define CLK_REQ_PIN_PAD_STRENGTH_SET(x)          (((x) << CLK_REQ_PIN_PAD_STRENGTH_LSB) & CLK_REQ_PIN_PAD_STRENGTH_MASK)
+
+#define SIGMA_DELTA_ADDRESS                      0x00000078
+#define SIGMA_DELTA_OFFSET                       0x00000078
+#define SIGMA_DELTA_ENABLE_MSB                   16
+#define SIGMA_DELTA_ENABLE_LSB                   16
+#define SIGMA_DELTA_ENABLE_MASK                  0x00010000
+#define SIGMA_DELTA_ENABLE_GET(x)                (((x) & SIGMA_DELTA_ENABLE_MASK) >> SIGMA_DELTA_ENABLE_LSB)
+#define SIGMA_DELTA_ENABLE_SET(x)                (((x) << SIGMA_DELTA_ENABLE_LSB) & SIGMA_DELTA_ENABLE_MASK)
+#define SIGMA_DELTA_PRESCALAR_MSB                15
+#define SIGMA_DELTA_PRESCALAR_LSB                8
+#define SIGMA_DELTA_PRESCALAR_MASK               0x0000ff00
+#define SIGMA_DELTA_PRESCALAR_GET(x)             (((x) & SIGMA_DELTA_PRESCALAR_MASK) >> SIGMA_DELTA_PRESCALAR_LSB)
+#define SIGMA_DELTA_PRESCALAR_SET(x)             (((x) << SIGMA_DELTA_PRESCALAR_LSB) & SIGMA_DELTA_PRESCALAR_MASK)
+#define SIGMA_DELTA_TARGET_MSB                   7
+#define SIGMA_DELTA_TARGET_LSB                   0
+#define SIGMA_DELTA_TARGET_MASK                  0x000000ff
+#define SIGMA_DELTA_TARGET_GET(x)                (((x) & SIGMA_DELTA_TARGET_MASK) >> SIGMA_DELTA_TARGET_LSB)
+#define SIGMA_DELTA_TARGET_SET(x)                (((x) << SIGMA_DELTA_TARGET_LSB) & SIGMA_DELTA_TARGET_MASK)
+
+#define DEBUG_CONTROL_ADDRESS                    0x0000007c
+#define DEBUG_CONTROL_OFFSET                     0x0000007c
+#define DEBUG_CONTROL_OBS_OE_L_MSB               1
+#define DEBUG_CONTROL_OBS_OE_L_LSB               1
+#define DEBUG_CONTROL_OBS_OE_L_MASK              0x00000002
+#define DEBUG_CONTROL_OBS_OE_L_GET(x)            (((x) & DEBUG_CONTROL_OBS_OE_L_MASK) >> DEBUG_CONTROL_OBS_OE_L_LSB)
+#define DEBUG_CONTROL_OBS_OE_L_SET(x)            (((x) << DEBUG_CONTROL_OBS_OE_L_LSB) & DEBUG_CONTROL_OBS_OE_L_MASK)
+#define DEBUG_CONTROL_ENABLE_MSB                 0
+#define DEBUG_CONTROL_ENABLE_LSB                 0
+#define DEBUG_CONTROL_ENABLE_MASK                0x00000001
+#define DEBUG_CONTROL_ENABLE_GET(x)              (((x) & DEBUG_CONTROL_ENABLE_MASK) >> DEBUG_CONTROL_ENABLE_LSB)
+#define DEBUG_CONTROL_ENABLE_SET(x)              (((x) << DEBUG_CONTROL_ENABLE_LSB) & DEBUG_CONTROL_ENABLE_MASK)
+
+#define DEBUG_INPUT_SEL_ADDRESS                  0x00000080
+#define DEBUG_INPUT_SEL_OFFSET                   0x00000080
+#define DEBUG_INPUT_SEL_SRC_MSB                  3
+#define DEBUG_INPUT_SEL_SRC_LSB                  0
+#define DEBUG_INPUT_SEL_SRC_MASK                 0x0000000f
+#define DEBUG_INPUT_SEL_SRC_GET(x)               (((x) & DEBUG_INPUT_SEL_SRC_MASK) >> DEBUG_INPUT_SEL_SRC_LSB)
+#define DEBUG_INPUT_SEL_SRC_SET(x)               (((x) << DEBUG_INPUT_SEL_SRC_LSB) & DEBUG_INPUT_SEL_SRC_MASK)
+
+#define DEBUG_OUT_ADDRESS                        0x00000084
+#define DEBUG_OUT_OFFSET                         0x00000084
+#define DEBUG_OUT_DATA_MSB                       17
+#define DEBUG_OUT_DATA_LSB                       0
+#define DEBUG_OUT_DATA_MASK                      0x0003ffff
+#define DEBUG_OUT_DATA_GET(x)                    (((x) & DEBUG_OUT_DATA_MASK) >> DEBUG_OUT_DATA_LSB)
+#define DEBUG_OUT_DATA_SET(x)                    (((x) << DEBUG_OUT_DATA_LSB) & DEBUG_OUT_DATA_MASK)
+
+#define LA_CONTROL_ADDRESS                       0x00000088
+#define LA_CONTROL_OFFSET                        0x00000088
+#define LA_CONTROL_RUN_MSB                       1
+#define LA_CONTROL_RUN_LSB                       1
+#define LA_CONTROL_RUN_MASK                      0x00000002
+#define LA_CONTROL_RUN_GET(x)                    (((x) & LA_CONTROL_RUN_MASK) >> LA_CONTROL_RUN_LSB)
+#define LA_CONTROL_RUN_SET(x)                    (((x) << LA_CONTROL_RUN_LSB) & LA_CONTROL_RUN_MASK)
+#define LA_CONTROL_TRIGGERED_MSB                 0
+#define LA_CONTROL_TRIGGERED_LSB                 0
+#define LA_CONTROL_TRIGGERED_MASK                0x00000001
+#define LA_CONTROL_TRIGGERED_GET(x)              (((x) & LA_CONTROL_TRIGGERED_MASK) >> LA_CONTROL_TRIGGERED_LSB)
+#define LA_CONTROL_TRIGGERED_SET(x)              (((x) << LA_CONTROL_TRIGGERED_LSB) & LA_CONTROL_TRIGGERED_MASK)
+
+#define LA_CLOCK_ADDRESS                         0x0000008c
+#define LA_CLOCK_OFFSET                          0x0000008c
+#define LA_CLOCK_DIV_MSB                         7
+#define LA_CLOCK_DIV_LSB                         0
+#define LA_CLOCK_DIV_MASK                        0x000000ff
+#define LA_CLOCK_DIV_GET(x)                      (((x) & LA_CLOCK_DIV_MASK) >> LA_CLOCK_DIV_LSB)
+#define LA_CLOCK_DIV_SET(x)                      (((x) << LA_CLOCK_DIV_LSB) & LA_CLOCK_DIV_MASK)
+
+#define LA_STATUS_ADDRESS                        0x00000090
+#define LA_STATUS_OFFSET                         0x00000090
+#define LA_STATUS_INTERRUPT_MSB                  0
+#define LA_STATUS_INTERRUPT_LSB                  0
+#define LA_STATUS_INTERRUPT_MASK                 0x00000001
+#define LA_STATUS_INTERRUPT_GET(x)               (((x) & LA_STATUS_INTERRUPT_MASK) >> LA_STATUS_INTERRUPT_LSB)
+#define LA_STATUS_INTERRUPT_SET(x)               (((x) << LA_STATUS_INTERRUPT_LSB) & LA_STATUS_INTERRUPT_MASK)
+
+#define LA_TRIGGER_SAMPLE_ADDRESS                0x00000094
+#define LA_TRIGGER_SAMPLE_OFFSET                 0x00000094
+#define LA_TRIGGER_SAMPLE_COUNT_MSB              15
+#define LA_TRIGGER_SAMPLE_COUNT_LSB              0
+#define LA_TRIGGER_SAMPLE_COUNT_MASK             0x0000ffff
+#define LA_TRIGGER_SAMPLE_COUNT_GET(x)           (((x) & LA_TRIGGER_SAMPLE_COUNT_MASK) >> LA_TRIGGER_SAMPLE_COUNT_LSB)
+#define LA_TRIGGER_SAMPLE_COUNT_SET(x)           (((x) << LA_TRIGGER_SAMPLE_COUNT_LSB) & LA_TRIGGER_SAMPLE_COUNT_MASK)
+
+#define LA_TRIGGER_POSITION_ADDRESS              0x00000098
+#define LA_TRIGGER_POSITION_OFFSET               0x00000098
+#define LA_TRIGGER_POSITION_VALUE_MSB            15
+#define LA_TRIGGER_POSITION_VALUE_LSB            0
+#define LA_TRIGGER_POSITION_VALUE_MASK           0x0000ffff
+#define LA_TRIGGER_POSITION_VALUE_GET(x)         (((x) & LA_TRIGGER_POSITION_VALUE_MASK) >> LA_TRIGGER_POSITION_VALUE_LSB)
+#define LA_TRIGGER_POSITION_VALUE_SET(x)         (((x) << LA_TRIGGER_POSITION_VALUE_LSB) & LA_TRIGGER_POSITION_VALUE_MASK)
+
+#define LA_PRE_TRIGGER_ADDRESS                   0x0000009c
+#define LA_PRE_TRIGGER_OFFSET                    0x0000009c
+#define LA_PRE_TRIGGER_COUNT_MSB                 15
+#define LA_PRE_TRIGGER_COUNT_LSB                 0
+#define LA_PRE_TRIGGER_COUNT_MASK                0x0000ffff
+#define LA_PRE_TRIGGER_COUNT_GET(x)              (((x) & LA_PRE_TRIGGER_COUNT_MASK) >> LA_PRE_TRIGGER_COUNT_LSB)
+#define LA_PRE_TRIGGER_COUNT_SET(x)              (((x) << LA_PRE_TRIGGER_COUNT_LSB) & LA_PRE_TRIGGER_COUNT_MASK)
+
+#define LA_POST_TRIGGER_ADDRESS                  0x000000a0
+#define LA_POST_TRIGGER_OFFSET                   0x000000a0
+#define LA_POST_TRIGGER_COUNT_MSB                15
+#define LA_POST_TRIGGER_COUNT_LSB                0
+#define LA_POST_TRIGGER_COUNT_MASK               0x0000ffff
+#define LA_POST_TRIGGER_COUNT_GET(x)             (((x) & LA_POST_TRIGGER_COUNT_MASK) >> LA_POST_TRIGGER_COUNT_LSB)
+#define LA_POST_TRIGGER_COUNT_SET(x)             (((x) << LA_POST_TRIGGER_COUNT_LSB) & LA_POST_TRIGGER_COUNT_MASK)
+
+#define LA_FILTER_CONTROL_ADDRESS                0x000000a4
+#define LA_FILTER_CONTROL_OFFSET                 0x000000a4
+#define LA_FILTER_CONTROL_DELTA_MSB              0
+#define LA_FILTER_CONTROL_DELTA_LSB              0
+#define LA_FILTER_CONTROL_DELTA_MASK             0x00000001
+#define LA_FILTER_CONTROL_DELTA_GET(x)           (((x) & LA_FILTER_CONTROL_DELTA_MASK) >> LA_FILTER_CONTROL_DELTA_LSB)
+#define LA_FILTER_CONTROL_DELTA_SET(x)           (((x) << LA_FILTER_CONTROL_DELTA_LSB) & LA_FILTER_CONTROL_DELTA_MASK)
+
+#define LA_FILTER_DATA_ADDRESS                   0x000000a8
+#define LA_FILTER_DATA_OFFSET                    0x000000a8
+#define LA_FILTER_DATA_MATCH_MSB                 17
+#define LA_FILTER_DATA_MATCH_LSB                 0
+#define LA_FILTER_DATA_MATCH_MASK                0x0003ffff
+#define LA_FILTER_DATA_MATCH_GET(x)              (((x) & LA_FILTER_DATA_MATCH_MASK) >> LA_FILTER_DATA_MATCH_LSB)
+#define LA_FILTER_DATA_MATCH_SET(x)              (((x) << LA_FILTER_DATA_MATCH_LSB) & LA_FILTER_DATA_MATCH_MASK)
+
+#define LA_FILTER_WILDCARD_ADDRESS               0x000000ac
+#define LA_FILTER_WILDCARD_OFFSET                0x000000ac
+#define LA_FILTER_WILDCARD_MATCH_MSB             17
+#define LA_FILTER_WILDCARD_MATCH_LSB             0
+#define LA_FILTER_WILDCARD_MATCH_MASK            0x0003ffff
+#define LA_FILTER_WILDCARD_MATCH_GET(x)          (((x) & LA_FILTER_WILDCARD_MATCH_MASK) >> LA_FILTER_WILDCARD_MATCH_LSB)
+#define LA_FILTER_WILDCARD_MATCH_SET(x)          (((x) << LA_FILTER_WILDCARD_MATCH_LSB) & LA_FILTER_WILDCARD_MATCH_MASK)
+
+#define LA_TRIGGERA_DATA_ADDRESS                 0x000000b0
+#define LA_TRIGGERA_DATA_OFFSET                  0x000000b0
+#define LA_TRIGGERA_DATA_MATCH_MSB               17
+#define LA_TRIGGERA_DATA_MATCH_LSB               0
+#define LA_TRIGGERA_DATA_MATCH_MASK              0x0003ffff
+#define LA_TRIGGERA_DATA_MATCH_GET(x)            (((x) & LA_TRIGGERA_DATA_MATCH_MASK) >> LA_TRIGGERA_DATA_MATCH_LSB)
+#define LA_TRIGGERA_DATA_MATCH_SET(x)            (((x) << LA_TRIGGERA_DATA_MATCH_LSB) & LA_TRIGGERA_DATA_MATCH_MASK)
+
+#define LA_TRIGGERA_WILDCARD_ADDRESS             0x000000b4
+#define LA_TRIGGERA_WILDCARD_OFFSET              0x000000b4
+#define LA_TRIGGERA_WILDCARD_MATCH_MSB           17
+#define LA_TRIGGERA_WILDCARD_MATCH_LSB           0
+#define LA_TRIGGERA_WILDCARD_MATCH_MASK          0x0003ffff
+#define LA_TRIGGERA_WILDCARD_MATCH_GET(x)        (((x) & LA_TRIGGERA_WILDCARD_MATCH_MASK) >> LA_TRIGGERA_WILDCARD_MATCH_LSB)
+#define LA_TRIGGERA_WILDCARD_MATCH_SET(x)        (((x) << LA_TRIGGERA_WILDCARD_MATCH_LSB) & LA_TRIGGERA_WILDCARD_MATCH_MASK)
+
+#define LA_TRIGGERB_DATA_ADDRESS                 0x000000b8
+#define LA_TRIGGERB_DATA_OFFSET                  0x000000b8
+#define LA_TRIGGERB_DATA_MATCH_MSB               17
+#define LA_TRIGGERB_DATA_MATCH_LSB               0
+#define LA_TRIGGERB_DATA_MATCH_MASK              0x0003ffff
+#define LA_TRIGGERB_DATA_MATCH_GET(x)            (((x) & LA_TRIGGERB_DATA_MATCH_MASK) >> LA_TRIGGERB_DATA_MATCH_LSB)
+#define LA_TRIGGERB_DATA_MATCH_SET(x)            (((x) << LA_TRIGGERB_DATA_MATCH_LSB) & LA_TRIGGERB_DATA_MATCH_MASK)
+
+#define LA_TRIGGERB_WILDCARD_ADDRESS             0x000000bc
+#define LA_TRIGGERB_WILDCARD_OFFSET              0x000000bc
+#define LA_TRIGGERB_WILDCARD_MATCH_MSB           17
+#define LA_TRIGGERB_WILDCARD_MATCH_LSB           0
+#define LA_TRIGGERB_WILDCARD_MATCH_MASK          0x0003ffff
+#define LA_TRIGGERB_WILDCARD_MATCH_GET(x)        (((x) & LA_TRIGGERB_WILDCARD_MATCH_MASK) >> LA_TRIGGERB_WILDCARD_MATCH_LSB)
+#define LA_TRIGGERB_WILDCARD_MATCH_SET(x)        (((x) << LA_TRIGGERB_WILDCARD_MATCH_LSB) & LA_TRIGGERB_WILDCARD_MATCH_MASK)
+
+#define LA_TRIGGER_ADDRESS                       0x000000c0
+#define LA_TRIGGER_OFFSET                        0x000000c0
+#define LA_TRIGGER_EVENT_MSB                     2
+#define LA_TRIGGER_EVENT_LSB                     0
+#define LA_TRIGGER_EVENT_MASK                    0x00000007
+#define LA_TRIGGER_EVENT_GET(x)                  (((x) & LA_TRIGGER_EVENT_MASK) >> LA_TRIGGER_EVENT_LSB)
+#define LA_TRIGGER_EVENT_SET(x)                  (((x) << LA_TRIGGER_EVENT_LSB) & LA_TRIGGER_EVENT_MASK)
+
+#define LA_FIFO_ADDRESS                          0x000000c4
+#define LA_FIFO_OFFSET                           0x000000c4
+#define LA_FIFO_FULL_MSB                         1
+#define LA_FIFO_FULL_LSB                         1
+#define LA_FIFO_FULL_MASK                        0x00000002
+#define LA_FIFO_FULL_GET(x)                      (((x) & LA_FIFO_FULL_MASK) >> LA_FIFO_FULL_LSB)
+#define LA_FIFO_FULL_SET(x)                      (((x) << LA_FIFO_FULL_LSB) & LA_FIFO_FULL_MASK)
+#define LA_FIFO_EMPTY_MSB                        0
+#define LA_FIFO_EMPTY_LSB                        0
+#define LA_FIFO_EMPTY_MASK                       0x00000001
+#define LA_FIFO_EMPTY_GET(x)                     (((x) & LA_FIFO_EMPTY_MASK) >> LA_FIFO_EMPTY_LSB)
+#define LA_FIFO_EMPTY_SET(x)                     (((x) << LA_FIFO_EMPTY_LSB) & LA_FIFO_EMPTY_MASK)
+
+#define LA_ADDRESS                               0x000000c8
+#define LA_OFFSET                                0x000000c8
+#define LA_DATA_MSB                              17
+#define LA_DATA_LSB                              0
+#define LA_DATA_MASK                             0x0003ffff
+#define LA_DATA_GET(x)                           (((x) & LA_DATA_MASK) >> LA_DATA_LSB)
+#define LA_DATA_SET(x)                           (((x) << LA_DATA_LSB) & LA_DATA_MASK)
+
+#define ANT_PIN_ADDRESS                          0x000000d0
+#define ANT_PIN_OFFSET                           0x000000d0
+#define ANT_PIN_PAD_PULL_MSB                     3
+#define ANT_PIN_PAD_PULL_LSB                     2
+#define ANT_PIN_PAD_PULL_MASK                    0x0000000c
+#define ANT_PIN_PAD_PULL_GET(x)                  (((x) & ANT_PIN_PAD_PULL_MASK) >> ANT_PIN_PAD_PULL_LSB)
+#define ANT_PIN_PAD_PULL_SET(x)                  (((x) << ANT_PIN_PAD_PULL_LSB) & ANT_PIN_PAD_PULL_MASK)
+#define ANT_PIN_PAD_STRENGTH_MSB                 1
+#define ANT_PIN_PAD_STRENGTH_LSB                 0
+#define ANT_PIN_PAD_STRENGTH_MASK                0x00000003
+#define ANT_PIN_PAD_STRENGTH_GET(x)              (((x) & ANT_PIN_PAD_STRENGTH_MASK) >> ANT_PIN_PAD_STRENGTH_LSB)
+#define ANT_PIN_PAD_STRENGTH_SET(x)              (((x) << ANT_PIN_PAD_STRENGTH_LSB) & ANT_PIN_PAD_STRENGTH_MASK)
+
+#define ANTD_PIN_ADDRESS                         0x000000d4
+#define ANTD_PIN_OFFSET                          0x000000d4
+#define ANTD_PIN_PAD_PULL_MSB                    1
+#define ANTD_PIN_PAD_PULL_LSB                    0
+#define ANTD_PIN_PAD_PULL_MASK                   0x00000003
+#define ANTD_PIN_PAD_PULL_GET(x)                 (((x) & ANTD_PIN_PAD_PULL_MASK) >> ANTD_PIN_PAD_PULL_LSB)
+#define ANTD_PIN_PAD_PULL_SET(x)                 (((x) << ANTD_PIN_PAD_PULL_LSB) & ANTD_PIN_PAD_PULL_MASK)
+
+#define GPIO_PIN_ADDRESS                         0x000000d8
+#define GPIO_PIN_OFFSET                          0x000000d8
+#define GPIO_PIN_PAD_PULL_MSB                    3
+#define GPIO_PIN_PAD_PULL_LSB                    2
+#define GPIO_PIN_PAD_PULL_MASK                   0x0000000c
+#define GPIO_PIN_PAD_PULL_GET(x)                 (((x) & GPIO_PIN_PAD_PULL_MASK) >> GPIO_PIN_PAD_PULL_LSB)
+#define GPIO_PIN_PAD_PULL_SET(x)                 (((x) << GPIO_PIN_PAD_PULL_LSB) & GPIO_PIN_PAD_PULL_MASK)
+#define GPIO_PIN_PAD_STRENGTH_MSB                1
+#define GPIO_PIN_PAD_STRENGTH_LSB                0
+#define GPIO_PIN_PAD_STRENGTH_MASK               0x00000003
+#define GPIO_PIN_PAD_STRENGTH_GET(x)             (((x) & GPIO_PIN_PAD_STRENGTH_MASK) >> GPIO_PIN_PAD_STRENGTH_LSB)
+#define GPIO_PIN_PAD_STRENGTH_SET(x)             (((x) << GPIO_PIN_PAD_STRENGTH_LSB) & GPIO_PIN_PAD_STRENGTH_MASK)
+
+#define GPIO_H_PIN_ADDRESS                       0x000000dc
+#define GPIO_H_PIN_OFFSET                        0x000000dc
+#define GPIO_H_PIN_PAD_PULL_MSB                  1
+#define GPIO_H_PIN_PAD_PULL_LSB                  0
+#define GPIO_H_PIN_PAD_PULL_MASK                 0x00000003
+#define GPIO_H_PIN_PAD_PULL_GET(x)               (((x) & GPIO_H_PIN_PAD_PULL_MASK) >> GPIO_H_PIN_PAD_PULL_LSB)
+#define GPIO_H_PIN_PAD_PULL_SET(x)               (((x) << GPIO_H_PIN_PAD_PULL_LSB) & GPIO_H_PIN_PAD_PULL_MASK)
+
+#define BT_PIN_ADDRESS                           0x000000e0
+#define BT_PIN_OFFSET                            0x000000e0
+#define BT_PIN_PAD_PULL_MSB                      3
+#define BT_PIN_PAD_PULL_LSB                      2
+#define BT_PIN_PAD_PULL_MASK                     0x0000000c
+#define BT_PIN_PAD_PULL_GET(x)                   (((x) & BT_PIN_PAD_PULL_MASK) >> BT_PIN_PAD_PULL_LSB)
+#define BT_PIN_PAD_PULL_SET(x)                   (((x) << BT_PIN_PAD_PULL_LSB) & BT_PIN_PAD_PULL_MASK)
+#define BT_PIN_PAD_STRENGTH_MSB                  1
+#define BT_PIN_PAD_STRENGTH_LSB                  0
+#define BT_PIN_PAD_STRENGTH_MASK                 0x00000003
+#define BT_PIN_PAD_STRENGTH_GET(x)               (((x) & BT_PIN_PAD_STRENGTH_MASK) >> BT_PIN_PAD_STRENGTH_LSB)
+#define BT_PIN_PAD_STRENGTH_SET(x)               (((x) << BT_PIN_PAD_STRENGTH_LSB) & BT_PIN_PAD_STRENGTH_MASK)
+
+#define BT_WLAN_PIN_ADDRESS                      0x000000e4
+#define BT_WLAN_PIN_OFFSET                       0x000000e4
+#define BT_WLAN_PIN_PAD_PULL_MSB                 1
+#define BT_WLAN_PIN_PAD_PULL_LSB                 0
+#define BT_WLAN_PIN_PAD_PULL_MASK                0x00000003
+#define BT_WLAN_PIN_PAD_PULL_GET(x)              (((x) & BT_WLAN_PIN_PAD_PULL_MASK) >> BT_WLAN_PIN_PAD_PULL_LSB)
+#define BT_WLAN_PIN_PAD_PULL_SET(x)              (((x) << BT_WLAN_PIN_PAD_PULL_LSB) & BT_WLAN_PIN_PAD_PULL_MASK)
+
+#define SI_UART_PIN_ADDRESS                      0x000000e8
+#define SI_UART_PIN_OFFSET                       0x000000e8
+#define SI_UART_PIN_PAD_PULL_MSB                 3
+#define SI_UART_PIN_PAD_PULL_LSB                 2
+#define SI_UART_PIN_PAD_PULL_MASK                0x0000000c
+#define SI_UART_PIN_PAD_PULL_GET(x)              (((x) & SI_UART_PIN_PAD_PULL_MASK) >> SI_UART_PIN_PAD_PULL_LSB)
+#define SI_UART_PIN_PAD_PULL_SET(x)              (((x) << SI_UART_PIN_PAD_PULL_LSB) & SI_UART_PIN_PAD_PULL_MASK)
+#define SI_UART_PIN_PAD_STRENGTH_MSB             1
+#define SI_UART_PIN_PAD_STRENGTH_LSB             0
+#define SI_UART_PIN_PAD_STRENGTH_MASK            0x00000003
+#define SI_UART_PIN_PAD_STRENGTH_GET(x)          (((x) & SI_UART_PIN_PAD_STRENGTH_MASK) >> SI_UART_PIN_PAD_STRENGTH_LSB)
+#define SI_UART_PIN_PAD_STRENGTH_SET(x)          (((x) << SI_UART_PIN_PAD_STRENGTH_LSB) & SI_UART_PIN_PAD_STRENGTH_MASK)
+
+#define CLK32K_PIN_ADDRESS                       0x000000ec
+#define CLK32K_PIN_OFFSET                        0x000000ec
+#define CLK32K_PIN_PAD_PULL_MSB                  1
+#define CLK32K_PIN_PAD_PULL_LSB                  0
+#define CLK32K_PIN_PAD_PULL_MASK                 0x00000003
+#define CLK32K_PIN_PAD_PULL_GET(x)               (((x) & CLK32K_PIN_PAD_PULL_MASK) >> CLK32K_PIN_PAD_PULL_LSB)
+#define CLK32K_PIN_PAD_PULL_SET(x)               (((x) << CLK32K_PIN_PAD_PULL_LSB) & CLK32K_PIN_PAD_PULL_MASK)
+
+#define RESET_TUPLE_STATUS_ADDRESS               0x000000f0
+#define RESET_TUPLE_STATUS_OFFSET                0x000000f0
+#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MSB  11
+#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB  8
+#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK 0x00000f00
+#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_GET(x) (((x) & RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK) >> RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB)
+#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_SET(x) (((x) << RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB) & RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK)
+#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MSB   7
+#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB   0
+#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK  0x000000ff
+#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_GET(x) (((x) & RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK) >> RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB)
+#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_SET(x) (((x) << RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB) & RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct gpio_reg_reg_s {
+  volatile unsigned int gpio_out;
+  volatile unsigned int gpio_out_w1ts;
+  volatile unsigned int gpio_out_w1tc;
+  volatile unsigned int gpio_enable;
+  volatile unsigned int gpio_enable_w1ts;
+  volatile unsigned int gpio_enable_w1tc;
+  volatile unsigned int gpio_in;
+  volatile unsigned int gpio_status;
+  volatile unsigned int gpio_status_w1ts;
+  volatile unsigned int gpio_status_w1tc;
+  volatile unsigned int gpio_pin0;
+  volatile unsigned int gpio_pin1;
+  volatile unsigned int gpio_pin2;
+  volatile unsigned int gpio_pin3;
+  volatile unsigned int gpio_pin4;
+  volatile unsigned int gpio_pin5;
+  volatile unsigned int gpio_pin6;
+  volatile unsigned int gpio_pin7;
+  volatile unsigned int gpio_pin8;
+  volatile unsigned int gpio_pin9;
+  volatile unsigned int gpio_pin10;
+  volatile unsigned int gpio_pin11;
+  volatile unsigned int gpio_pin12;
+  volatile unsigned int gpio_pin13;
+  volatile unsigned int gpio_pin14;
+  volatile unsigned int gpio_pin15;
+  volatile unsigned int gpio_pin16;
+  volatile unsigned int gpio_pin17;
+  volatile unsigned int sdio_pin;
+  volatile unsigned int clk_req_pin;
+  volatile unsigned int sigma_delta;
+  volatile unsigned int debug_control;
+  volatile unsigned int debug_input_sel;
+  volatile unsigned int debug_out;
+  volatile unsigned int la_control;
+  volatile unsigned int la_clock;
+  volatile unsigned int la_status;
+  volatile unsigned int la_trigger_sample;
+  volatile unsigned int la_trigger_position;
+  volatile unsigned int la_pre_trigger;
+  volatile unsigned int la_post_trigger;
+  volatile unsigned int la_filter_control;
+  volatile unsigned int la_filter_data;
+  volatile unsigned int la_filter_wildcard;
+  volatile unsigned int la_triggera_data;
+  volatile unsigned int la_triggera_wildcard;
+  volatile unsigned int la_triggerb_data;
+  volatile unsigned int la_triggerb_wildcard;
+  volatile unsigned int la_trigger;
+  volatile unsigned int la_fifo;
+  volatile unsigned int la[2];
+  volatile unsigned int ant_pin;
+  volatile unsigned int antd_pin;
+  volatile unsigned int gpio_pin;
+  volatile unsigned int gpio_h_pin;
+  volatile unsigned int bt_pin;
+  volatile unsigned int bt_wlan_pin;
+  volatile unsigned int si_uart_pin;
+  volatile unsigned int clk32k_pin;
+  volatile unsigned int reset_tuple_status;
+} gpio_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _GPIO_REG_H_ */
diff --git a/drivers/net/ath6kl/include/common/AR6002/hw2.0/hw/mbox_host_reg.h b/drivers/net/ath6kl/include/common/AR6002/hw2.0/hw/mbox_host_reg.h
new file mode 100644
index 00000000000..f836ae47a30
--- /dev/null
+++ b/drivers/net/ath6kl/include/common/AR6002/hw2.0/hw/mbox_host_reg.h
@@ -0,0 +1,386 @@
+#ifndef _MBOX_HOST_REG_REG_H_
+#define _MBOX_HOST_REG_REG_H_
+
+#define HOST_INT_STATUS_ADDRESS                  0x00000400
+#define HOST_INT_STATUS_OFFSET                   0x00000400
+#define HOST_INT_STATUS_ERROR_MSB                7
+#define HOST_INT_STATUS_ERROR_LSB                7
+#define HOST_INT_STATUS_ERROR_MASK               0x00000080
+#define HOST_INT_STATUS_ERROR_GET(x)             (((x) & HOST_INT_STATUS_ERROR_MASK) >> HOST_INT_STATUS_ERROR_LSB)
+#define HOST_INT_STATUS_ERROR_SET(x)             (((x) << HOST_INT_STATUS_ERROR_LSB) & HOST_INT_STATUS_ERROR_MASK)
+#define HOST_INT_STATUS_CPU_MSB                  6
+#define HOST_INT_STATUS_CPU_LSB                  6
+#define HOST_INT_STATUS_CPU_MASK                 0x00000040
+#define HOST_INT_STATUS_CPU_GET(x)               (((x) & HOST_INT_STATUS_CPU_MASK) >> HOST_INT_STATUS_CPU_LSB)
+#define HOST_INT_STATUS_CPU_SET(x)               (((x) << HOST_INT_STATUS_CPU_LSB) & HOST_INT_STATUS_CPU_MASK)
+#define HOST_INT_STATUS_DRAGON_INT_MSB           5
+#define HOST_INT_STATUS_DRAGON_INT_LSB           5
+#define HOST_INT_STATUS_DRAGON_INT_MASK          0x00000020
+#define HOST_INT_STATUS_DRAGON_INT_GET(x)        (((x) & HOST_INT_STATUS_DRAGON_INT_MASK) >> HOST_INT_STATUS_DRAGON_INT_LSB)
+#define HOST_INT_STATUS_DRAGON_INT_SET(x)        (((x) << HOST_INT_STATUS_DRAGON_INT_LSB) & HOST_INT_STATUS_DRAGON_INT_MASK)
+#define HOST_INT_STATUS_COUNTER_MSB              4
+#define HOST_INT_STATUS_COUNTER_LSB              4
+#define HOST_INT_STATUS_COUNTER_MASK             0x00000010
+#define HOST_INT_STATUS_COUNTER_GET(x)           (((x) & HOST_INT_STATUS_COUNTER_MASK) >> HOST_INT_STATUS_COUNTER_LSB)
+#define HOST_INT_STATUS_COUNTER_SET(x)           (((x) << HOST_INT_STATUS_COUNTER_LSB) & HOST_INT_STATUS_COUNTER_MASK)
+#define HOST_INT_STATUS_MBOX_DATA_MSB            3
+#define HOST_INT_STATUS_MBOX_DATA_LSB            0
+#define HOST_INT_STATUS_MBOX_DATA_MASK           0x0000000f
+#define HOST_INT_STATUS_MBOX_DATA_GET(x)         (((x) & HOST_INT_STATUS_MBOX_DATA_MASK) >> HOST_INT_STATUS_MBOX_DATA_LSB)
+#define HOST_INT_STATUS_MBOX_DATA_SET(x)         (((x) << HOST_INT_STATUS_MBOX_DATA_LSB) & HOST_INT_STATUS_MBOX_DATA_MASK)
+
+#define CPU_INT_STATUS_ADDRESS                   0x00000401
+#define CPU_INT_STATUS_OFFSET                    0x00000401
+#define CPU_INT_STATUS_BIT_MSB                   7
+#define CPU_INT_STATUS_BIT_LSB                   0
+#define CPU_INT_STATUS_BIT_MASK                  0x000000ff
+#define CPU_INT_STATUS_BIT_GET(x)                (((x) & CPU_INT_STATUS_BIT_MASK) >> CPU_INT_STATUS_BIT_LSB)
+#define CPU_INT_STATUS_BIT_SET(x)                (((x) << CPU_INT_STATUS_BIT_LSB) & CPU_INT_STATUS_BIT_MASK)
+
+#define ERROR_INT_STATUS_ADDRESS                 0x00000402
+#define ERROR_INT_STATUS_OFFSET                  0x00000402
+#define ERROR_INT_STATUS_SPI_MSB                 3
+#define ERROR_INT_STATUS_SPI_LSB                 3
+#define ERROR_INT_STATUS_SPI_MASK                0x00000008
+#define ERROR_INT_STATUS_SPI_GET(x)              (((x) & ERROR_INT_STATUS_SPI_MASK) >> ERROR_INT_STATUS_SPI_LSB)
+#define ERROR_INT_STATUS_SPI_SET(x)              (((x) << ERROR_INT_STATUS_SPI_LSB) & ERROR_INT_STATUS_SPI_MASK)
+#define ERROR_INT_STATUS_WAKEUP_MSB              2
+#define ERROR_INT_STATUS_WAKEUP_LSB              2
+#define ERROR_INT_STATUS_WAKEUP_MASK             0x00000004
+#define ERROR_INT_STATUS_WAKEUP_GET(x)           (((x) & ERROR_INT_STATUS_WAKEUP_MASK) >> ERROR_INT_STATUS_WAKEUP_LSB)
+#define ERROR_INT_STATUS_WAKEUP_SET(x)           (((x) << ERROR_INT_STATUS_WAKEUP_LSB) & ERROR_INT_STATUS_WAKEUP_MASK)
+#define ERROR_INT_STATUS_RX_UNDERFLOW_MSB        1
+#define ERROR_INT_STATUS_RX_UNDERFLOW_LSB        1
+#define ERROR_INT_STATUS_RX_UNDERFLOW_MASK       0x00000002
+#define ERROR_INT_STATUS_RX_UNDERFLOW_GET(x)     (((x) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK) >> ERROR_INT_STATUS_RX_UNDERFLOW_LSB)
+#define ERROR_INT_STATUS_RX_UNDERFLOW_SET(x)     (((x) << ERROR_INT_STATUS_RX_UNDERFLOW_LSB) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK)
+#define ERROR_INT_STATUS_TX_OVERFLOW_MSB         0
+#define ERROR_INT_STATUS_TX_OVERFLOW_LSB         0
+#define ERROR_INT_STATUS_TX_OVERFLOW_MASK        0x00000001
+#define ERROR_INT_STATUS_TX_OVERFLOW_GET(x)      (((x) & ERROR_INT_STATUS_TX_OVERFLOW_MASK) >> ERROR_INT_STATUS_TX_OVERFLOW_LSB)
+#define ERROR_INT_STATUS_TX_OVERFLOW_SET(x)      (((x) << ERROR_INT_STATUS_TX_OVERFLOW_LSB) & ERROR_INT_STATUS_TX_OVERFLOW_MASK)
+
+#define COUNTER_INT_STATUS_ADDRESS               0x00000403
+#define COUNTER_INT_STATUS_OFFSET                0x00000403
+#define COUNTER_INT_STATUS_COUNTER_MSB           7
+#define COUNTER_INT_STATUS_COUNTER_LSB           0
+#define COUNTER_INT_STATUS_COUNTER_MASK          0x000000ff
+#define COUNTER_INT_STATUS_COUNTER_GET(x)        (((x) & COUNTER_INT_STATUS_COUNTER_MASK) >> COUNTER_INT_STATUS_COUNTER_LSB)
+#define COUNTER_INT_STATUS_COUNTER_SET(x)        (((x) << COUNTER_INT_STATUS_COUNTER_LSB) & COUNTER_INT_STATUS_COUNTER_MASK)
+
+#define MBOX_FRAME_ADDRESS                       0x00000404
+#define MBOX_FRAME_OFFSET                        0x00000404
+#define MBOX_FRAME_RX_EOM_MSB                    7
+#define MBOX_FRAME_RX_EOM_LSB                    4
+#define MBOX_FRAME_RX_EOM_MASK                   0x000000f0
+#define MBOX_FRAME_RX_EOM_GET(x)                 (((x) & MBOX_FRAME_RX_EOM_MASK) >> MBOX_FRAME_RX_EOM_LSB)
+#define MBOX_FRAME_RX_EOM_SET(x)                 (((x) << MBOX_FRAME_RX_EOM_LSB) & MBOX_FRAME_RX_EOM_MASK)
+#define MBOX_FRAME_RX_SOM_MSB                    3
+#define MBOX_FRAME_RX_SOM_LSB                    0
+#define MBOX_FRAME_RX_SOM_MASK                   0x0000000f
+#define MBOX_FRAME_RX_SOM_GET(x)                 (((x) & MBOX_FRAME_RX_SOM_MASK) >> MBOX_FRAME_RX_SOM_LSB)
+#define MBOX_FRAME_RX_SOM_SET(x)                 (((x) << MBOX_FRAME_RX_SOM_LSB) & MBOX_FRAME_RX_SOM_MASK)
+
+#define RX_LOOKAHEAD_VALID_ADDRESS               0x00000405
+#define RX_LOOKAHEAD_VALID_OFFSET                0x00000405
+#define RX_LOOKAHEAD_VALID_MBOX_MSB              3
+#define RX_LOOKAHEAD_VALID_MBOX_LSB              0
+#define RX_LOOKAHEAD_VALID_MBOX_MASK             0x0000000f
+#define RX_LOOKAHEAD_VALID_MBOX_GET(x)           (((x) & RX_LOOKAHEAD_VALID_MBOX_MASK) >> RX_LOOKAHEAD_VALID_MBOX_LSB)
+#define RX_LOOKAHEAD_VALID_MBOX_SET(x)           (((x) << RX_LOOKAHEAD_VALID_MBOX_LSB) & RX_LOOKAHEAD_VALID_MBOX_MASK)
+
+#define RX_LOOKAHEAD0_ADDRESS                    0x00000408
+#define RX_LOOKAHEAD0_OFFSET                     0x00000408
+#define RX_LOOKAHEAD0_DATA_MSB                   7
+#define RX_LOOKAHEAD0_DATA_LSB                   0
+#define RX_LOOKAHEAD0_DATA_MASK                  0x000000ff
+#define RX_LOOKAHEAD0_DATA_GET(x)                (((x) & RX_LOOKAHEAD0_DATA_MASK) >> RX_LOOKAHEAD0_DATA_LSB)
+#define RX_LOOKAHEAD0_DATA_SET(x)                (((x) << RX_LOOKAHEAD0_DATA_LSB) & RX_LOOKAHEAD0_DATA_MASK)
+
+#define RX_LOOKAHEAD1_ADDRESS                    0x0000040c
+#define RX_LOOKAHEAD1_OFFSET                     0x0000040c
+#define RX_LOOKAHEAD1_DATA_MSB                   7
+#define RX_LOOKAHEAD1_DATA_LSB                   0
+#define RX_LOOKAHEAD1_DATA_MASK                  0x000000ff
+#define RX_LOOKAHEAD1_DATA_GET(x)                (((x) & RX_LOOKAHEAD1_DATA_MASK) >> RX_LOOKAHEAD1_DATA_LSB)
+#define RX_LOOKAHEAD1_DATA_SET(x)                (((x) << RX_LOOKAHEAD1_DATA_LSB) & RX_LOOKAHEAD1_DATA_MASK)
+
+#define RX_LOOKAHEAD2_ADDRESS                    0x00000410
+#define RX_LOOKAHEAD2_OFFSET                     0x00000410
+#define RX_LOOKAHEAD2_DATA_MSB                   7
+#define RX_LOOKAHEAD2_DATA_LSB                   0
+#define RX_LOOKAHEAD2_DATA_MASK                  0x000000ff
+#define RX_LOOKAHEAD2_DATA_GET(x)                (((x) & RX_LOOKAHEAD2_DATA_MASK) >> RX_LOOKAHEAD2_DATA_LSB)
+#define RX_LOOKAHEAD2_DATA_SET(x)                (((x) << RX_LOOKAHEAD2_DATA_LSB) & RX_LOOKAHEAD2_DATA_MASK)
+
+#define RX_LOOKAHEAD3_ADDRESS                    0x00000414
+#define RX_LOOKAHEAD3_OFFSET                     0x00000414
+#define RX_LOOKAHEAD3_DATA_MSB                   7
+#define RX_LOOKAHEAD3_DATA_LSB                   0
+#define RX_LOOKAHEAD3_DATA_MASK                  0x000000ff
+#define RX_LOOKAHEAD3_DATA_GET(x)                (((x) & RX_LOOKAHEAD3_DATA_MASK) >> RX_LOOKAHEAD3_DATA_LSB)
+#define RX_LOOKAHEAD3_DATA_SET(x)                (((x) << RX_LOOKAHEAD3_DATA_LSB) & RX_LOOKAHEAD3_DATA_MASK)
+
+#define INT_STATUS_ENABLE_ADDRESS                0x00000418
+#define INT_STATUS_ENABLE_OFFSET                 0x00000418
+#define INT_STATUS_ENABLE_ERROR_MSB              7
+#define INT_STATUS_ENABLE_ERROR_LSB              7
+#define INT_STATUS_ENABLE_ERROR_MASK             0x00000080
+#define INT_STATUS_ENABLE_ERROR_GET(x)           (((x) & INT_STATUS_ENABLE_ERROR_MASK) >> INT_STATUS_ENABLE_ERROR_LSB)
+#define INT_STATUS_ENABLE_ERROR_SET(x)           (((x) << INT_STATUS_ENABLE_ERROR_LSB) & INT_STATUS_ENABLE_ERROR_MASK)
+#define INT_STATUS_ENABLE_CPU_MSB                6
+#define INT_STATUS_ENABLE_CPU_LSB                6
+#define INT_STATUS_ENABLE_CPU_MASK               0x00000040
+#define INT_STATUS_ENABLE_CPU_GET(x)             (((x) & INT_STATUS_ENABLE_CPU_MASK) >> INT_STATUS_ENABLE_CPU_LSB)
+#define INT_STATUS_ENABLE_CPU_SET(x)             (((x) << INT_STATUS_ENABLE_CPU_LSB) & INT_STATUS_ENABLE_CPU_MASK)
+#define INT_STATUS_ENABLE_DRAGON_INT_MSB         5
+#define INT_STATUS_ENABLE_DRAGON_INT_LSB         5
+#define INT_STATUS_ENABLE_DRAGON_INT_MASK        0x00000020
+#define INT_STATUS_ENABLE_DRAGON_INT_GET(x)      (((x) & INT_STATUS_ENABLE_DRAGON_INT_MASK) >> INT_STATUS_ENABLE_DRAGON_INT_LSB)
+#define INT_STATUS_ENABLE_DRAGON_INT_SET(x)      (((x) << INT_STATUS_ENABLE_DRAGON_INT_LSB) & INT_STATUS_ENABLE_DRAGON_INT_MASK)
+#define INT_STATUS_ENABLE_COUNTER_MSB            4
+#define INT_STATUS_ENABLE_COUNTER_LSB            4
+#define INT_STATUS_ENABLE_COUNTER_MASK           0x00000010
+#define INT_STATUS_ENABLE_COUNTER_GET(x)         (((x) & INT_STATUS_ENABLE_COUNTER_MASK) >> INT_STATUS_ENABLE_COUNTER_LSB)
+#define INT_STATUS_ENABLE_COUNTER_SET(x)         (((x) << INT_STATUS_ENABLE_COUNTER_LSB) & INT_STATUS_ENABLE_COUNTER_MASK)
+#define INT_STATUS_ENABLE_MBOX_DATA_MSB          3
+#define INT_STATUS_ENABLE_MBOX_DATA_LSB          0
+#define INT_STATUS_ENABLE_MBOX_DATA_MASK         0x0000000f
+#define INT_STATUS_ENABLE_MBOX_DATA_GET(x)       (((x) & INT_STATUS_ENABLE_MBOX_DATA_MASK) >> INT_STATUS_ENABLE_MBOX_DATA_LSB)
+#define INT_STATUS_ENABLE_MBOX_DATA_SET(x)       (((x) << INT_STATUS_ENABLE_MBOX_DATA_LSB) & INT_STATUS_ENABLE_MBOX_DATA_MASK)
+
+#define CPU_INT_STATUS_ENABLE_ADDRESS            0x00000419
+#define CPU_INT_STATUS_ENABLE_OFFSET             0x00000419
+#define CPU_INT_STATUS_ENABLE_BIT_MSB            7
+#define CPU_INT_STATUS_ENABLE_BIT_LSB            0
+#define CPU_INT_STATUS_ENABLE_BIT_MASK           0x000000ff
+#define CPU_INT_STATUS_ENABLE_BIT_GET(x)         (((x) & CPU_INT_STATUS_ENABLE_BIT_MASK) >> CPU_INT_STATUS_ENABLE_BIT_LSB)
+#define CPU_INT_STATUS_ENABLE_BIT_SET(x)         (((x) << CPU_INT_STATUS_ENABLE_BIT_LSB) & CPU_INT_STATUS_ENABLE_BIT_MASK)
+
+#define ERROR_STATUS_ENABLE_ADDRESS              0x0000041a
+#define ERROR_STATUS_ENABLE_OFFSET               0x0000041a
+#define ERROR_STATUS_ENABLE_WAKEUP_MSB           2
+#define ERROR_STATUS_ENABLE_WAKEUP_LSB           2
+#define ERROR_STATUS_ENABLE_WAKEUP_MASK          0x00000004
+#define ERROR_STATUS_ENABLE_WAKEUP_GET(x)        (((x) & ERROR_STATUS_ENABLE_WAKEUP_MASK) >> ERROR_STATUS_ENABLE_WAKEUP_LSB)
+#define ERROR_STATUS_ENABLE_WAKEUP_SET(x)        (((x) << ERROR_STATUS_ENABLE_WAKEUP_LSB) & ERROR_STATUS_ENABLE_WAKEUP_MASK)
+#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MSB     1
+#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB     1
+#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK    0x00000002
+#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_GET(x)  (((x) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK) >> ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB)
+#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_SET(x)  (((x) << ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK)
+#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MSB      0
+#define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB      0
+#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK     0x00000001
+#define ERROR_STATUS_ENABLE_TX_OVERFLOW_GET(x)   (((x) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK) >> ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB)
+#define ERROR_STATUS_ENABLE_TX_OVERFLOW_SET(x)   (((x) << ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK)
+
+#define COUNTER_INT_STATUS_ENABLE_ADDRESS        0x0000041b
+#define COUNTER_INT_STATUS_ENABLE_OFFSET         0x0000041b
+#define COUNTER_INT_STATUS_ENABLE_BIT_MSB        7
+#define COUNTER_INT_STATUS_ENABLE_BIT_LSB        0
+#define COUNTER_INT_STATUS_ENABLE_BIT_MASK       0x000000ff
+#define COUNTER_INT_STATUS_ENABLE_BIT_GET(x)     (((x) & COUNTER_INT_STATUS_ENABLE_BIT_MASK) >> COUNTER_INT_STATUS_ENABLE_BIT_LSB)
+#define COUNTER_INT_STATUS_ENABLE_BIT_SET(x)     (((x) << COUNTER_INT_STATUS_ENABLE_BIT_LSB) & COUNTER_INT_STATUS_ENABLE_BIT_MASK)
+
+#define COUNT_ADDRESS                            0x00000420
+#define COUNT_OFFSET                             0x00000420
+#define COUNT_VALUE_MSB                          7
+#define COUNT_VALUE_LSB                          0
+#define COUNT_VALUE_MASK                         0x000000ff
+#define COUNT_VALUE_GET(x)                       (((x) & COUNT_VALUE_MASK) >> COUNT_VALUE_LSB)
+#define COUNT_VALUE_SET(x)                       (((x) << COUNT_VALUE_LSB) & COUNT_VALUE_MASK)
+
+#define COUNT_DEC_ADDRESS                        0x00000440
+#define COUNT_DEC_OFFSET                         0x00000440
+#define COUNT_DEC_VALUE_MSB                      7
+#define COUNT_DEC_VALUE_LSB                      0
+#define COUNT_DEC_VALUE_MASK                     0x000000ff
+#define COUNT_DEC_VALUE_GET(x)                   (((x) & COUNT_DEC_VALUE_MASK) >> COUNT_DEC_VALUE_LSB)
+#define COUNT_DEC_VALUE_SET(x)                   (((x) << COUNT_DEC_VALUE_LSB) & COUNT_DEC_VALUE_MASK)
+
+#define SCRATCH_ADDRESS                          0x00000460
+#define SCRATCH_OFFSET                           0x00000460
+#define SCRATCH_VALUE_MSB                        7
+#define SCRATCH_VALUE_LSB                        0
+#define SCRATCH_VALUE_MASK                       0x000000ff
+#define SCRATCH_VALUE_GET(x)                     (((x) & SCRATCH_VALUE_MASK) >> SCRATCH_VALUE_LSB)
+#define SCRATCH_VALUE_SET(x)                     (((x) << SCRATCH_VALUE_LSB) & SCRATCH_VALUE_MASK)
+
+#define FIFO_TIMEOUT_ADDRESS                     0x00000468
+#define FIFO_TIMEOUT_OFFSET                      0x00000468
+#define FIFO_TIMEOUT_VALUE_MSB                   7
+#define FIFO_TIMEOUT_VALUE_LSB                   0
+#define FIFO_TIMEOUT_VALUE_MASK                  0x000000ff
+#define FIFO_TIMEOUT_VALUE_GET(x)                (((x) & FIFO_TIMEOUT_VALUE_MASK) >> FIFO_TIMEOUT_VALUE_LSB)
+#define FIFO_TIMEOUT_VALUE_SET(x)                (((x) << FIFO_TIMEOUT_VALUE_LSB) & FIFO_TIMEOUT_VALUE_MASK)
+
+#define FIFO_TIMEOUT_ENABLE_ADDRESS              0x00000469
+#define FIFO_TIMEOUT_ENABLE_OFFSET               0x00000469
+#define FIFO_TIMEOUT_ENABLE_SET_MSB              0
+#define FIFO_TIMEOUT_ENABLE_SET_LSB              0
+#define FIFO_TIMEOUT_ENABLE_SET_MASK             0x00000001
+#define FIFO_TIMEOUT_ENABLE_SET_GET(x)           (((x) & FIFO_TIMEOUT_ENABLE_SET_MASK) >> FIFO_TIMEOUT_ENABLE_SET_LSB)
+#define FIFO_TIMEOUT_ENABLE_SET_SET(x)           (((x) << FIFO_TIMEOUT_ENABLE_SET_LSB) & FIFO_TIMEOUT_ENABLE_SET_MASK)
+
+#define DISABLE_SLEEP_ADDRESS                    0x0000046a
+#define DISABLE_SLEEP_OFFSET                     0x0000046a
+#define DISABLE_SLEEP_FOR_INT_MSB                1
+#define DISABLE_SLEEP_FOR_INT_LSB                1
+#define DISABLE_SLEEP_FOR_INT_MASK               0x00000002
+#define DISABLE_SLEEP_FOR_INT_GET(x)             (((x) & DISABLE_SLEEP_FOR_INT_MASK) >> DISABLE_SLEEP_FOR_INT_LSB)
+#define DISABLE_SLEEP_FOR_INT_SET(x)             (((x) << DISABLE_SLEEP_FOR_INT_LSB) & DISABLE_SLEEP_FOR_INT_MASK)
+#define DISABLE_SLEEP_ON_MSB                     0
+#define DISABLE_SLEEP_ON_LSB                     0
+#define DISABLE_SLEEP_ON_MASK                    0x00000001
+#define DISABLE_SLEEP_ON_GET(x)                  (((x) & DISABLE_SLEEP_ON_MASK) >> DISABLE_SLEEP_ON_LSB)
+#define DISABLE_SLEEP_ON_SET(x)                  (((x) << DISABLE_SLEEP_ON_LSB) & DISABLE_SLEEP_ON_MASK)
+
+#define LOCAL_BUS_ADDRESS                        0x00000470
+#define LOCAL_BUS_OFFSET                         0x00000470
+#define LOCAL_BUS_STATE_MSB                      1
+#define LOCAL_BUS_STATE_LSB                      0
+#define LOCAL_BUS_STATE_MASK                     0x00000003
+#define LOCAL_BUS_STATE_GET(x)                   (((x) & LOCAL_BUS_STATE_MASK) >> LOCAL_BUS_STATE_LSB)
+#define LOCAL_BUS_STATE_SET(x)                   (((x) << LOCAL_BUS_STATE_LSB) & LOCAL_BUS_STATE_MASK)
+
+#define INT_WLAN_ADDRESS                         0x00000472
+#define INT_WLAN_OFFSET                          0x00000472
+#define INT_WLAN_VECTOR_MSB                      7
+#define INT_WLAN_VECTOR_LSB                      0
+#define INT_WLAN_VECTOR_MASK                     0x000000ff
+#define INT_WLAN_VECTOR_GET(x)                   (((x) & INT_WLAN_VECTOR_MASK) >> INT_WLAN_VECTOR_LSB)
+#define INT_WLAN_VECTOR_SET(x)                   (((x) << INT_WLAN_VECTOR_LSB) & INT_WLAN_VECTOR_MASK)
+
+#define WINDOW_DATA_ADDRESS                      0x00000474
+#define WINDOW_DATA_OFFSET                       0x00000474
+#define WINDOW_DATA_DATA_MSB                     7
+#define WINDOW_DATA_DATA_LSB                     0
+#define WINDOW_DATA_DATA_MASK                    0x000000ff
+#define WINDOW_DATA_DATA_GET(x)                  (((x) & WINDOW_DATA_DATA_MASK) >> WINDOW_DATA_DATA_LSB)
+#define WINDOW_DATA_DATA_SET(x)                  (((x) << WINDOW_DATA_DATA_LSB) & WINDOW_DATA_DATA_MASK)
+
+#define WINDOW_WRITE_ADDR_ADDRESS                0x00000478
+#define WINDOW_WRITE_ADDR_OFFSET                 0x00000478
+#define WINDOW_WRITE_ADDR_ADDR_MSB               7
+#define WINDOW_WRITE_ADDR_ADDR_LSB               0
+#define WINDOW_WRITE_ADDR_ADDR_MASK              0x000000ff
+#define WINDOW_WRITE_ADDR_ADDR_GET(x)            (((x) & WINDOW_WRITE_ADDR_ADDR_MASK) >> WINDOW_WRITE_ADDR_ADDR_LSB)
+#define WINDOW_WRITE_ADDR_ADDR_SET(x)            (((x) << WINDOW_WRITE_ADDR_ADDR_LSB) & WINDOW_WRITE_ADDR_ADDR_MASK)
+
+#define WINDOW_READ_ADDR_ADDRESS                 0x0000047c
+#define WINDOW_READ_ADDR_OFFSET                  0x0000047c
+#define WINDOW_READ_ADDR_ADDR_MSB                7
+#define WINDOW_READ_ADDR_ADDR_LSB                0
+#define WINDOW_READ_ADDR_ADDR_MASK               0x000000ff
+#define WINDOW_READ_ADDR_ADDR_GET(x)             (((x) & WINDOW_READ_ADDR_ADDR_MASK) >> WINDOW_READ_ADDR_ADDR_LSB)
+#define WINDOW_READ_ADDR_ADDR_SET(x)             (((x) << WINDOW_READ_ADDR_ADDR_LSB) & WINDOW_READ_ADDR_ADDR_MASK)
+
+#define SPI_CONFIG_ADDRESS                       0x00000480
+#define SPI_CONFIG_OFFSET                        0x00000480
+#define SPI_CONFIG_SPI_RESET_MSB                 4
+#define SPI_CONFIG_SPI_RESET_LSB                 4
+#define SPI_CONFIG_SPI_RESET_MASK                0x00000010
+#define SPI_CONFIG_SPI_RESET_GET(x)              (((x) & SPI_CONFIG_SPI_RESET_MASK) >> SPI_CONFIG_SPI_RESET_LSB)
+#define SPI_CONFIG_SPI_RESET_SET(x)              (((x) << SPI_CONFIG_SPI_RESET_LSB) & SPI_CONFIG_SPI_RESET_MASK)
+#define SPI_CONFIG_INTERRUPT_ENABLE_MSB          3
+#define SPI_CONFIG_INTERRUPT_ENABLE_LSB          3
+#define SPI_CONFIG_INTERRUPT_ENABLE_MASK         0x00000008
+#define SPI_CONFIG_INTERRUPT_ENABLE_GET(x)       (((x) & SPI_CONFIG_INTERRUPT_ENABLE_MASK) >> SPI_CONFIG_INTERRUPT_ENABLE_LSB)
+#define SPI_CONFIG_INTERRUPT_ENABLE_SET(x)       (((x) << SPI_CONFIG_INTERRUPT_ENABLE_LSB) & SPI_CONFIG_INTERRUPT_ENABLE_MASK)
+#define SPI_CONFIG_TEST_MODE_MSB                 2
+#define SPI_CONFIG_TEST_MODE_LSB                 2
+#define SPI_CONFIG_TEST_MODE_MASK                0x00000004
+#define SPI_CONFIG_TEST_MODE_GET(x)              (((x) & SPI_CONFIG_TEST_MODE_MASK) >> SPI_CONFIG_TEST_MODE_LSB)
+#define SPI_CONFIG_TEST_MODE_SET(x)              (((x) << SPI_CONFIG_TEST_MODE_LSB) & SPI_CONFIG_TEST_MODE_MASK)
+#define SPI_CONFIG_DATA_SIZE_MSB                 1
+#define SPI_CONFIG_DATA_SIZE_LSB                 0
+#define SPI_CONFIG_DATA_SIZE_MASK                0x00000003
+#define SPI_CONFIG_DATA_SIZE_GET(x)              (((x) & SPI_CONFIG_DATA_SIZE_MASK) >> SPI_CONFIG_DATA_SIZE_LSB)
+#define SPI_CONFIG_DATA_SIZE_SET(x)              (((x) << SPI_CONFIG_DATA_SIZE_LSB) & SPI_CONFIG_DATA_SIZE_MASK)
+
+#define SPI_STATUS_ADDRESS                       0x00000481
+#define SPI_STATUS_OFFSET                        0x00000481
+#define SPI_STATUS_ADDR_ERR_MSB                  3
+#define SPI_STATUS_ADDR_ERR_LSB                  3
+#define SPI_STATUS_ADDR_ERR_MASK                 0x00000008
+#define SPI_STATUS_ADDR_ERR_GET(x)               (((x) & SPI_STATUS_ADDR_ERR_MASK) >> SPI_STATUS_ADDR_ERR_LSB)
+#define SPI_STATUS_ADDR_ERR_SET(x)               (((x) << SPI_STATUS_ADDR_ERR_LSB) & SPI_STATUS_ADDR_ERR_MASK)
+#define SPI_STATUS_RD_ERR_MSB                    2
+#define SPI_STATUS_RD_ERR_LSB                    2
+#define SPI_STATUS_RD_ERR_MASK                   0x00000004
+#define SPI_STATUS_RD_ERR_GET(x)                 (((x) & SPI_STATUS_RD_ERR_MASK) >> SPI_STATUS_RD_ERR_LSB)
+#define SPI_STATUS_RD_ERR_SET(x)                 (((x) << SPI_STATUS_RD_ERR_LSB) & SPI_STATUS_RD_ERR_MASK)
+#define SPI_STATUS_WR_ERR_MSB                    1
+#define SPI_STATUS_WR_ERR_LSB                    1
+#define SPI_STATUS_WR_ERR_MASK                   0x00000002
+#define SPI_STATUS_WR_ERR_GET(x)                 (((x) & SPI_STATUS_WR_ERR_MASK) >> SPI_STATUS_WR_ERR_LSB)
+#define SPI_STATUS_WR_ERR_SET(x)                 (((x) << SPI_STATUS_WR_ERR_LSB) & SPI_STATUS_WR_ERR_MASK)
+#define SPI_STATUS_READY_MSB                     0
+#define SPI_STATUS_READY_LSB                     0
+#define SPI_STATUS_READY_MASK                    0x00000001
+#define SPI_STATUS_READY_GET(x)                  (((x) & SPI_STATUS_READY_MASK) >> SPI_STATUS_READY_LSB)
+#define SPI_STATUS_READY_SET(x)                  (((x) << SPI_STATUS_READY_LSB) & SPI_STATUS_READY_MASK)
+
+#define NON_ASSOC_SLEEP_EN_ADDRESS               0x00000482
+#define NON_ASSOC_SLEEP_EN_OFFSET                0x00000482
+#define NON_ASSOC_SLEEP_EN_BIT_MSB               0
+#define NON_ASSOC_SLEEP_EN_BIT_LSB               0
+#define NON_ASSOC_SLEEP_EN_BIT_MASK              0x00000001
+#define NON_ASSOC_SLEEP_EN_BIT_GET(x)            (((x) & NON_ASSOC_SLEEP_EN_BIT_MASK) >> NON_ASSOC_SLEEP_EN_BIT_LSB)
+#define NON_ASSOC_SLEEP_EN_BIT_SET(x)            (((x) << NON_ASSOC_SLEEP_EN_BIT_LSB) & NON_ASSOC_SLEEP_EN_BIT_MASK)
+
+#define CIS_WINDOW_ADDRESS                       0x00000600
+#define CIS_WINDOW_OFFSET                        0x00000600
+#define CIS_WINDOW_DATA_MSB                      7
+#define CIS_WINDOW_DATA_LSB                      0
+#define CIS_WINDOW_DATA_MASK                     0x000000ff
+#define CIS_WINDOW_DATA_GET(x)                   (((x) & CIS_WINDOW_DATA_MASK) >> CIS_WINDOW_DATA_LSB)
+#define CIS_WINDOW_DATA_SET(x)                   (((x) << CIS_WINDOW_DATA_LSB) & CIS_WINDOW_DATA_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct mbox_host_reg_reg_s {
+  unsigned char pad0[1024]; /* pad to 0x400 */
+  volatile unsigned char host_int_status;
+  volatile unsigned char cpu_int_status;
+  volatile unsigned char error_int_status;
+  volatile unsigned char counter_int_status;
+  volatile unsigned char mbox_frame;
+  volatile unsigned char rx_lookahead_valid;
+  unsigned char pad1[2]; /* pad to 0x408 */
+  volatile unsigned char rx_lookahead0[4];
+  volatile unsigned char rx_lookahead1[4];
+  volatile unsigned char rx_lookahead2[4];
+  volatile unsigned char rx_lookahead3[4];
+  volatile unsigned char int_status_enable;
+  volatile unsigned char cpu_int_status_enable;
+  volatile unsigned char error_status_enable;
+  volatile unsigned char counter_int_status_enable;
+  unsigned char pad2[4]; /* pad to 0x420 */
+  volatile unsigned char count[8];
+  unsigned char pad3[24]; /* pad to 0x440 */
+  volatile unsigned char count_dec[32];
+  volatile unsigned char scratch[8];
+  volatile unsigned char fifo_timeout;
+  volatile unsigned char fifo_timeout_enable;
+  volatile unsigned char disable_sleep;
+  unsigned char pad4[5]; /* pad to 0x470 */
+  volatile unsigned char local_bus;
+  unsigned char pad5[1]; /* pad to 0x472 */
+  volatile unsigned char int_wlan;
+  unsigned char pad6[1]; /* pad to 0x474 */
+  volatile unsigned char window_data[4];
+  volatile unsigned char window_write_addr[4];
+  volatile unsigned char window_read_addr[4];
+  volatile unsigned char spi_config;
+  volatile unsigned char spi_status;
+  volatile unsigned char non_assoc_sleep_en;
+  unsigned char pad7[381]; /* pad to 0x600 */
+  volatile unsigned char cis_window[512];
+} mbox_host_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _MBOX_HOST_REG_H_ */
diff --git a/drivers/net/ath6kl/include/common/AR6002/hw2.0/hw/mbox_reg.h b/drivers/net/ath6kl/include/common/AR6002/hw2.0/hw/mbox_reg.h
new file mode 100644
index 00000000000..4e07d228610
--- /dev/null
+++ b/drivers/net/ath6kl/include/common/AR6002/hw2.0/hw/mbox_reg.h
@@ -0,0 +1,481 @@
+#ifndef _MBOX_REG_REG_H_
+#define _MBOX_REG_REG_H_
+
+#define MBOX_FIFO_ADDRESS                        0x00000000
+#define MBOX_FIFO_OFFSET                         0x00000000
+#define MBOX_FIFO_DATA_MSB                       19
+#define MBOX_FIFO_DATA_LSB                       0
+#define MBOX_FIFO_DATA_MASK                      0x000fffff
+#define MBOX_FIFO_DATA_GET(x)                    (((x) & MBOX_FIFO_DATA_MASK) >> MBOX_FIFO_DATA_LSB)
+#define MBOX_FIFO_DATA_SET(x)                    (((x) << MBOX_FIFO_DATA_LSB) & MBOX_FIFO_DATA_MASK)
+
+#define MBOX_FIFO_STATUS_ADDRESS                 0x00000010
+#define MBOX_FIFO_STATUS_OFFSET                  0x00000010
+#define MBOX_FIFO_STATUS_EMPTY_MSB               19
+#define MBOX_FIFO_STATUS_EMPTY_LSB               16
+#define MBOX_FIFO_STATUS_EMPTY_MASK              0x000f0000
+#define MBOX_FIFO_STATUS_EMPTY_GET(x)            (((x) & MBOX_FIFO_STATUS_EMPTY_MASK) >> MBOX_FIFO_STATUS_EMPTY_LSB)
+#define MBOX_FIFO_STATUS_EMPTY_SET(x)            (((x) << MBOX_FIFO_STATUS_EMPTY_LSB) & MBOX_FIFO_STATUS_EMPTY_MASK)
+#define MBOX_FIFO_STATUS_FULL_MSB                15
+#define MBOX_FIFO_STATUS_FULL_LSB                12
+#define MBOX_FIFO_STATUS_FULL_MASK               0x0000f000
+#define MBOX_FIFO_STATUS_FULL_GET(x)             (((x) & MBOX_FIFO_STATUS_FULL_MASK) >> MBOX_FIFO_STATUS_FULL_LSB)
+#define MBOX_FIFO_STATUS_FULL_SET(x)             (((x) << MBOX_FIFO_STATUS_FULL_LSB) & MBOX_FIFO_STATUS_FULL_MASK)
+
+#define MBOX_DMA_POLICY_ADDRESS                  0x00000014
+#define MBOX_DMA_POLICY_OFFSET                   0x00000014
+#define MBOX_DMA_POLICY_TX_QUANTUM_MSB           3
+#define MBOX_DMA_POLICY_TX_QUANTUM_LSB           3
+#define MBOX_DMA_POLICY_TX_QUANTUM_MASK          0x00000008
+#define MBOX_DMA_POLICY_TX_QUANTUM_GET(x)        (((x) & MBOX_DMA_POLICY_TX_QUANTUM_MASK) >> MBOX_DMA_POLICY_TX_QUANTUM_LSB)
+#define MBOX_DMA_POLICY_TX_QUANTUM_SET(x)        (((x) << MBOX_DMA_POLICY_TX_QUANTUM_LSB) & MBOX_DMA_POLICY_TX_QUANTUM_MASK)
+#define MBOX_DMA_POLICY_TX_ORDER_MSB             2
+#define MBOX_DMA_POLICY_TX_ORDER_LSB             2
+#define MBOX_DMA_POLICY_TX_ORDER_MASK            0x00000004
+#define MBOX_DMA_POLICY_TX_ORDER_GET(x)          (((x) & MBOX_DMA_POLICY_TX_ORDER_MASK) >> MBOX_DMA_POLICY_TX_ORDER_LSB)
+#define MBOX_DMA_POLICY_TX_ORDER_SET(x)          (((x) << MBOX_DMA_POLICY_TX_ORDER_LSB) & MBOX_DMA_POLICY_TX_ORDER_MASK)
+#define MBOX_DMA_POLICY_RX_QUANTUM_MSB           1
+#define MBOX_DMA_POLICY_RX_QUANTUM_LSB           1
+#define MBOX_DMA_POLICY_RX_QUANTUM_MASK          0x00000002
+#define MBOX_DMA_POLICY_RX_QUANTUM_GET(x)        (((x) & MBOX_DMA_POLICY_RX_QUANTUM_MASK) >> MBOX_DMA_POLICY_RX_QUANTUM_LSB)
+#define MBOX_DMA_POLICY_RX_QUANTUM_SET(x)        (((x) << MBOX_DMA_POLICY_RX_QUANTUM_LSB) & MBOX_DMA_POLICY_RX_QUANTUM_MASK)
+#define MBOX_DMA_POLICY_RX_ORDER_MSB             0
+#define MBOX_DMA_POLICY_RX_ORDER_LSB             0
+#define MBOX_DMA_POLICY_RX_ORDER_MASK            0x00000001
+#define MBOX_DMA_POLICY_RX_ORDER_GET(x)          (((x) & MBOX_DMA_POLICY_RX_ORDER_MASK) >> MBOX_DMA_POLICY_RX_ORDER_LSB)
+#define MBOX_DMA_POLICY_RX_ORDER_SET(x)          (((x) << MBOX_DMA_POLICY_RX_ORDER_LSB) & MBOX_DMA_POLICY_RX_ORDER_MASK)
+
+#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS     0x00000018
+#define MBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET      0x00000018
+#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define MBOX0_DMA_RX_CONTROL_ADDRESS             0x0000001c
+#define MBOX0_DMA_RX_CONTROL_OFFSET              0x0000001c
+#define MBOX0_DMA_RX_CONTROL_RESUME_MSB          2
+#define MBOX0_DMA_RX_CONTROL_RESUME_LSB          2
+#define MBOX0_DMA_RX_CONTROL_RESUME_MASK         0x00000004
+#define MBOX0_DMA_RX_CONTROL_RESUME_GET(x)       (((x) & MBOX0_DMA_RX_CONTROL_RESUME_MASK) >> MBOX0_DMA_RX_CONTROL_RESUME_LSB)
+#define MBOX0_DMA_RX_CONTROL_RESUME_SET(x)       (((x) << MBOX0_DMA_RX_CONTROL_RESUME_LSB) & MBOX0_DMA_RX_CONTROL_RESUME_MASK)
+#define MBOX0_DMA_RX_CONTROL_START_MSB           1
+#define MBOX0_DMA_RX_CONTROL_START_LSB           1
+#define MBOX0_DMA_RX_CONTROL_START_MASK          0x00000002
+#define MBOX0_DMA_RX_CONTROL_START_GET(x)        (((x) & MBOX0_DMA_RX_CONTROL_START_MASK) >> MBOX0_DMA_RX_CONTROL_START_LSB)
+#define MBOX0_DMA_RX_CONTROL_START_SET(x)        (((x) << MBOX0_DMA_RX_CONTROL_START_LSB) & MBOX0_DMA_RX_CONTROL_START_MASK)
+#define MBOX0_DMA_RX_CONTROL_STOP_MSB            0
+#define MBOX0_DMA_RX_CONTROL_STOP_LSB            0
+#define MBOX0_DMA_RX_CONTROL_STOP_MASK           0x00000001
+#define MBOX0_DMA_RX_CONTROL_STOP_GET(x)         (((x) & MBOX0_DMA_RX_CONTROL_STOP_MASK) >> MBOX0_DMA_RX_CONTROL_STOP_LSB)
+#define MBOX0_DMA_RX_CONTROL_STOP_SET(x)         (((x) << MBOX0_DMA_RX_CONTROL_STOP_LSB) & MBOX0_DMA_RX_CONTROL_STOP_MASK)
+
+#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS     0x00000020
+#define MBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET      0x00000020
+#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define MBOX0_DMA_TX_CONTROL_ADDRESS             0x00000024
+#define MBOX0_DMA_TX_CONTROL_OFFSET              0x00000024
+#define MBOX0_DMA_TX_CONTROL_RESUME_MSB          2
+#define MBOX0_DMA_TX_CONTROL_RESUME_LSB          2
+#define MBOX0_DMA_TX_CONTROL_RESUME_MASK         0x00000004
+#define MBOX0_DMA_TX_CONTROL_RESUME_GET(x)       (((x) & MBOX0_DMA_TX_CONTROL_RESUME_MASK) >> MBOX0_DMA_TX_CONTROL_RESUME_LSB)
+#define MBOX0_DMA_TX_CONTROL_RESUME_SET(x)       (((x) << MBOX0_DMA_TX_CONTROL_RESUME_LSB) & MBOX0_DMA_TX_CONTROL_RESUME_MASK)
+#define MBOX0_DMA_TX_CONTROL_START_MSB           1
+#define MBOX0_DMA_TX_CONTROL_START_LSB           1
+#define MBOX0_DMA_TX_CONTROL_START_MASK          0x00000002
+#define MBOX0_DMA_TX_CONTROL_START_GET(x)        (((x) & MBOX0_DMA_TX_CONTROL_START_MASK) >> MBOX0_DMA_TX_CONTROL_START_LSB)
+#define MBOX0_DMA_TX_CONTROL_START_SET(x)        (((x) << MBOX0_DMA_TX_CONTROL_START_LSB) & MBOX0_DMA_TX_CONTROL_START_MASK)
+#define MBOX0_DMA_TX_CONTROL_STOP_MSB            0
+#define MBOX0_DMA_TX_CONTROL_STOP_LSB            0
+#define MBOX0_DMA_TX_CONTROL_STOP_MASK           0x00000001
+#define MBOX0_DMA_TX_CONTROL_STOP_GET(x)         (((x) & MBOX0_DMA_TX_CONTROL_STOP_MASK) >> MBOX0_DMA_TX_CONTROL_STOP_LSB)
+#define MBOX0_DMA_TX_CONTROL_STOP_SET(x)         (((x) << MBOX0_DMA_TX_CONTROL_STOP_LSB) & MBOX0_DMA_TX_CONTROL_STOP_MASK)
+
+#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS     0x00000028
+#define MBOX1_DMA_RX_DESCRIPTOR_BASE_OFFSET      0x00000028
+#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define MBOX1_DMA_RX_CONTROL_ADDRESS             0x0000002c
+#define MBOX1_DMA_RX_CONTROL_OFFSET              0x0000002c
+#define MBOX1_DMA_RX_CONTROL_RESUME_MSB          2
+#define MBOX1_DMA_RX_CONTROL_RESUME_LSB          2
+#define MBOX1_DMA_RX_CONTROL_RESUME_MASK         0x00000004
+#define MBOX1_DMA_RX_CONTROL_RESUME_GET(x)       (((x) & MBOX1_DMA_RX_CONTROL_RESUME_MASK) >> MBOX1_DMA_RX_CONTROL_RESUME_LSB)
+#define MBOX1_DMA_RX_CONTROL_RESUME_SET(x)       (((x) << MBOX1_DMA_RX_CONTROL_RESUME_LSB) & MBOX1_DMA_RX_CONTROL_RESUME_MASK)
+#define MBOX1_DMA_RX_CONTROL_START_MSB           1
+#define MBOX1_DMA_RX_CONTROL_START_LSB           1
+#define MBOX1_DMA_RX_CONTROL_START_MASK          0x00000002
+#define MBOX1_DMA_RX_CONTROL_START_GET(x)        (((x) & MBOX1_DMA_RX_CONTROL_START_MASK) >> MBOX1_DMA_RX_CONTROL_START_LSB)
+#define MBOX1_DMA_RX_CONTROL_START_SET(x)        (((x) << MBOX1_DMA_RX_CONTROL_START_LSB) & MBOX1_DMA_RX_CONTROL_START_MASK)
+#define MBOX1_DMA_RX_CONTROL_STOP_MSB            0
+#define MBOX1_DMA_RX_CONTROL_STOP_LSB            0
+#define MBOX1_DMA_RX_CONTROL_STOP_MASK           0x00000001
+#define MBOX1_DMA_RX_CONTROL_STOP_GET(x)         (((x) & MBOX1_DMA_RX_CONTROL_STOP_MASK) >> MBOX1_DMA_RX_CONTROL_STOP_LSB)
+#define MBOX1_DMA_RX_CONTROL_STOP_SET(x)         (((x) << MBOX1_DMA_RX_CONTROL_STOP_LSB) & MBOX1_DMA_RX_CONTROL_STOP_MASK)
+
+#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS     0x00000030
+#define MBOX1_DMA_TX_DESCRIPTOR_BASE_OFFSET      0x00000030
+#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define MBOX1_DMA_TX_CONTROL_ADDRESS             0x00000034
+#define MBOX1_DMA_TX_CONTROL_OFFSET              0x00000034
+#define MBOX1_DMA_TX_CONTROL_RESUME_MSB          2
+#define MBOX1_DMA_TX_CONTROL_RESUME_LSB          2
+#define MBOX1_DMA_TX_CONTROL_RESUME_MASK         0x00000004
+#define MBOX1_DMA_TX_CONTROL_RESUME_GET(x)       (((x) & MBOX1_DMA_TX_CONTROL_RESUME_MASK) >> MBOX1_DMA_TX_CONTROL_RESUME_LSB)
+#define MBOX1_DMA_TX_CONTROL_RESUME_SET(x)       (((x) << MBOX1_DMA_TX_CONTROL_RESUME_LSB) & MBOX1_DMA_TX_CONTROL_RESUME_MASK)
+#define MBOX1_DMA_TX_CONTROL_START_MSB           1
+#define MBOX1_DMA_TX_CONTROL_START_LSB           1
+#define MBOX1_DMA_TX_CONTROL_START_MASK          0x00000002
+#define MBOX1_DMA_TX_CONTROL_START_GET(x)        (((x) & MBOX1_DMA_TX_CONTROL_START_MASK) >> MBOX1_DMA_TX_CONTROL_START_LSB)
+#define MBOX1_DMA_TX_CONTROL_START_SET(x)        (((x) << MBOX1_DMA_TX_CONTROL_START_LSB) & MBOX1_DMA_TX_CONTROL_START_MASK)
+#define MBOX1_DMA_TX_CONTROL_STOP_MSB            0
+#define MBOX1_DMA_TX_CONTROL_STOP_LSB            0
+#define MBOX1_DMA_TX_CONTROL_STOP_MASK           0x00000001
+#define MBOX1_DMA_TX_CONTROL_STOP_GET(x)         (((x) & MBOX1_DMA_TX_CONTROL_STOP_MASK) >> MBOX1_DMA_TX_CONTROL_STOP_LSB)
+#define MBOX1_DMA_TX_CONTROL_STOP_SET(x)         (((x) << MBOX1_DMA_TX_CONTROL_STOP_LSB) & MBOX1_DMA_TX_CONTROL_STOP_MASK)
+
+#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS     0x00000038
+#define MBOX2_DMA_RX_DESCRIPTOR_BASE_OFFSET      0x00000038
+#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define MBOX2_DMA_RX_CONTROL_ADDRESS             0x0000003c
+#define MBOX2_DMA_RX_CONTROL_OFFSET              0x0000003c
+#define MBOX2_DMA_RX_CONTROL_RESUME_MSB          2
+#define MBOX2_DMA_RX_CONTROL_RESUME_LSB          2
+#define MBOX2_DMA_RX_CONTROL_RESUME_MASK         0x00000004
+#define MBOX2_DMA_RX_CONTROL_RESUME_GET(x)       (((x) & MBOX2_DMA_RX_CONTROL_RESUME_MASK) >> MBOX2_DMA_RX_CONTROL_RESUME_LSB)
+#define MBOX2_DMA_RX_CONTROL_RESUME_SET(x)       (((x) << MBOX2_DMA_RX_CONTROL_RESUME_LSB) & MBOX2_DMA_RX_CONTROL_RESUME_MASK)
+#define MBOX2_DMA_RX_CONTROL_START_MSB           1
+#define MBOX2_DMA_RX_CONTROL_START_LSB           1
+#define MBOX2_DMA_RX_CONTROL_START_MASK          0x00000002
+#define MBOX2_DMA_RX_CONTROL_START_GET(x)        (((x) & MBOX2_DMA_RX_CONTROL_START_MASK) >> MBOX2_DMA_RX_CONTROL_START_LSB)
+#define MBOX2_DMA_RX_CONTROL_START_SET(x)        (((x) << MBOX2_DMA_RX_CONTROL_START_LSB) & MBOX2_DMA_RX_CONTROL_START_MASK)
+#define MBOX2_DMA_RX_CONTROL_STOP_MSB            0
+#define MBOX2_DMA_RX_CONTROL_STOP_LSB            0
+#define MBOX2_DMA_RX_CONTROL_STOP_MASK           0x00000001
+#define MBOX2_DMA_RX_CONTROL_STOP_GET(x)         (((x) & MBOX2_DMA_RX_CONTROL_STOP_MASK) >> MBOX2_DMA_RX_CONTROL_STOP_LSB)
+#define MBOX2_DMA_RX_CONTROL_STOP_SET(x)         (((x) << MBOX2_DMA_RX_CONTROL_STOP_LSB) & MBOX2_DMA_RX_CONTROL_STOP_MASK)
+
+#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS     0x00000040
+#define MBOX2_DMA_TX_DESCRIPTOR_BASE_OFFSET      0x00000040
+#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define MBOX2_DMA_TX_CONTROL_ADDRESS             0x00000044
+#define MBOX2_DMA_TX_CONTROL_OFFSET              0x00000044
+#define MBOX2_DMA_TX_CONTROL_RESUME_MSB          2
+#define MBOX2_DMA_TX_CONTROL_RESUME_LSB          2
+#define MBOX2_DMA_TX_CONTROL_RESUME_MASK         0x00000004
+#define MBOX2_DMA_TX_CONTROL_RESUME_GET(x)       (((x) & MBOX2_DMA_TX_CONTROL_RESUME_MASK) >> MBOX2_DMA_TX_CONTROL_RESUME_LSB)
+#define MBOX2_DMA_TX_CONTROL_RESUME_SET(x)       (((x) << MBOX2_DMA_TX_CONTROL_RESUME_LSB) & MBOX2_DMA_TX_CONTROL_RESUME_MASK)
+#define MBOX2_DMA_TX_CONTROL_START_MSB           1
+#define MBOX2_DMA_TX_CONTROL_START_LSB           1
+#define MBOX2_DMA_TX_CONTROL_START_MASK          0x00000002
+#define MBOX2_DMA_TX_CONTROL_START_GET(x)        (((x) & MBOX2_DMA_TX_CONTROL_START_MASK) >> MBOX2_DMA_TX_CONTROL_START_LSB)
+#define MBOX2_DMA_TX_CONTROL_START_SET(x)        (((x) << MBOX2_DMA_TX_CONTROL_START_LSB) & MBOX2_DMA_TX_CONTROL_START_MASK)
+#define MBOX2_DMA_TX_CONTROL_STOP_MSB            0
+#define MBOX2_DMA_TX_CONTROL_STOP_LSB            0
+#define MBOX2_DMA_TX_CONTROL_STOP_MASK           0x00000001
+#define MBOX2_DMA_TX_CONTROL_STOP_GET(x)         (((x) & MBOX2_DMA_TX_CONTROL_STOP_MASK) >> MBOX2_DMA_TX_CONTROL_STOP_LSB)
+#define MBOX2_DMA_TX_CONTROL_STOP_SET(x)         (((x) << MBOX2_DMA_TX_CONTROL_STOP_LSB) & MBOX2_DMA_TX_CONTROL_STOP_MASK)
+
+#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS     0x00000048
+#define MBOX3_DMA_RX_DESCRIPTOR_BASE_OFFSET      0x00000048
+#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define MBOX3_DMA_RX_CONTROL_ADDRESS             0x0000004c
+#define MBOX3_DMA_RX_CONTROL_OFFSET              0x0000004c
+#define MBOX3_DMA_RX_CONTROL_RESUME_MSB          2
+#define MBOX3_DMA_RX_CONTROL_RESUME_LSB          2
+#define MBOX3_DMA_RX_CONTROL_RESUME_MASK         0x00000004
+#define MBOX3_DMA_RX_CONTROL_RESUME_GET(x)       (((x) & MBOX3_DMA_RX_CONTROL_RESUME_MASK) >> MBOX3_DMA_RX_CONTROL_RESUME_LSB)
+#define MBOX3_DMA_RX_CONTROL_RESUME_SET(x)       (((x) << MBOX3_DMA_RX_CONTROL_RESUME_LSB) & MBOX3_DMA_RX_CONTROL_RESUME_MASK)
+#define MBOX3_DMA_RX_CONTROL_START_MSB           1
+#define MBOX3_DMA_RX_CONTROL_START_LSB           1
+#define MBOX3_DMA_RX_CONTROL_START_MASK          0x00000002
+#define MBOX3_DMA_RX_CONTROL_START_GET(x)        (((x) & MBOX3_DMA_RX_CONTROL_START_MASK) >> MBOX3_DMA_RX_CONTROL_START_LSB)
+#define MBOX3_DMA_RX_CONTROL_START_SET(x)        (((x) << MBOX3_DMA_RX_CONTROL_START_LSB) & MBOX3_DMA_RX_CONTROL_START_MASK)
+#define MBOX3_DMA_RX_CONTROL_STOP_MSB            0
+#define MBOX3_DMA_RX_CONTROL_STOP_LSB            0
+#define MBOX3_DMA_RX_CONTROL_STOP_MASK           0x00000001
+#define MBOX3_DMA_RX_CONTROL_STOP_GET(x)         (((x) & MBOX3_DMA_RX_CONTROL_STOP_MASK) >> MBOX3_DMA_RX_CONTROL_STOP_LSB)
+#define MBOX3_DMA_RX_CONTROL_STOP_SET(x)         (((x) << MBOX3_DMA_RX_CONTROL_STOP_LSB) & MBOX3_DMA_RX_CONTROL_STOP_MASK)
+
+#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS     0x00000050
+#define MBOX3_DMA_TX_DESCRIPTOR_BASE_OFFSET      0x00000050
+#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define MBOX3_DMA_TX_CONTROL_ADDRESS             0x00000054
+#define MBOX3_DMA_TX_CONTROL_OFFSET              0x00000054
+#define MBOX3_DMA_TX_CONTROL_RESUME_MSB          2
+#define MBOX3_DMA_TX_CONTROL_RESUME_LSB          2
+#define MBOX3_DMA_TX_CONTROL_RESUME_MASK         0x00000004
+#define MBOX3_DMA_TX_CONTROL_RESUME_GET(x)       (((x) & MBOX3_DMA_TX_CONTROL_RESUME_MASK) >> MBOX3_DMA_TX_CONTROL_RESUME_LSB)
+#define MBOX3_DMA_TX_CONTROL_RESUME_SET(x)       (((x) << MBOX3_DMA_TX_CONTROL_RESUME_LSB) & MBOX3_DMA_TX_CONTROL_RESUME_MASK)
+#define MBOX3_DMA_TX_CONTROL_START_MSB           1
+#define MBOX3_DMA_TX_CONTROL_START_LSB           1
+#define MBOX3_DMA_TX_CONTROL_START_MASK          0x00000002
+#define MBOX3_DMA_TX_CONTROL_START_GET(x)        (((x) & MBOX3_DMA_TX_CONTROL_START_MASK) >> MBOX3_DMA_TX_CONTROL_START_LSB)
+#define MBOX3_DMA_TX_CONTROL_START_SET(x)        (((x) << MBOX3_DMA_TX_CONTROL_START_LSB) & MBOX3_DMA_TX_CONTROL_START_MASK)
+#define MBOX3_DMA_TX_CONTROL_STOP_MSB            0
+#define MBOX3_DMA_TX_CONTROL_STOP_LSB            0
+#define MBOX3_DMA_TX_CONTROL_STOP_MASK           0x00000001
+#define MBOX3_DMA_TX_CONTROL_STOP_GET(x)         (((x) & MBOX3_DMA_TX_CONTROL_STOP_MASK) >> MBOX3_DMA_TX_CONTROL_STOP_LSB)
+#define MBOX3_DMA_TX_CONTROL_STOP_SET(x)         (((x) << MBOX3_DMA_TX_CONTROL_STOP_LSB) & MBOX3_DMA_TX_CONTROL_STOP_MASK)
+
+#define MBOX_INT_STATUS_ADDRESS                  0x00000058
+#define MBOX_INT_STATUS_OFFSET                   0x00000058
+#define MBOX_INT_STATUS_RX_DMA_COMPLETE_MSB      31
+#define MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB      28
+#define MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK     0xf0000000
+#define MBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x)   (((x) & MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK) >> MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB)
+#define MBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x)   (((x) << MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB) & MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK)
+#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB  27
+#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB  24
+#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK 0x0f000000
+#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) (((x) & MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK) >> MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB)
+#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) (((x) << MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB) & MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK)
+#define MBOX_INT_STATUS_TX_DMA_COMPLETE_MSB      23
+#define MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB      20
+#define MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK     0x00f00000
+#define MBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x)   (((x) & MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK) >> MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB)
+#define MBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x)   (((x) << MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB) & MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK)
+#define MBOX_INT_STATUS_TX_OVERFLOW_MSB          17
+#define MBOX_INT_STATUS_TX_OVERFLOW_LSB          17
+#define MBOX_INT_STATUS_TX_OVERFLOW_MASK         0x00020000
+#define MBOX_INT_STATUS_TX_OVERFLOW_GET(x)       (((x) & MBOX_INT_STATUS_TX_OVERFLOW_MASK) >> MBOX_INT_STATUS_TX_OVERFLOW_LSB)
+#define MBOX_INT_STATUS_TX_OVERFLOW_SET(x)       (((x) << MBOX_INT_STATUS_TX_OVERFLOW_LSB) & MBOX_INT_STATUS_TX_OVERFLOW_MASK)
+#define MBOX_INT_STATUS_RX_UNDERFLOW_MSB         16
+#define MBOX_INT_STATUS_RX_UNDERFLOW_LSB         16
+#define MBOX_INT_STATUS_RX_UNDERFLOW_MASK        0x00010000
+#define MBOX_INT_STATUS_RX_UNDERFLOW_GET(x)      (((x) & MBOX_INT_STATUS_RX_UNDERFLOW_MASK) >> MBOX_INT_STATUS_RX_UNDERFLOW_LSB)
+#define MBOX_INT_STATUS_RX_UNDERFLOW_SET(x)      (((x) << MBOX_INT_STATUS_RX_UNDERFLOW_LSB) & MBOX_INT_STATUS_RX_UNDERFLOW_MASK)
+#define MBOX_INT_STATUS_TX_NOT_EMPTY_MSB         15
+#define MBOX_INT_STATUS_TX_NOT_EMPTY_LSB         12
+#define MBOX_INT_STATUS_TX_NOT_EMPTY_MASK        0x0000f000
+#define MBOX_INT_STATUS_TX_NOT_EMPTY_GET(x)      (((x) & MBOX_INT_STATUS_TX_NOT_EMPTY_MASK) >> MBOX_INT_STATUS_TX_NOT_EMPTY_LSB)
+#define MBOX_INT_STATUS_TX_NOT_EMPTY_SET(x)      (((x) << MBOX_INT_STATUS_TX_NOT_EMPTY_LSB) & MBOX_INT_STATUS_TX_NOT_EMPTY_MASK)
+#define MBOX_INT_STATUS_RX_NOT_FULL_MSB          11
+#define MBOX_INT_STATUS_RX_NOT_FULL_LSB          8
+#define MBOX_INT_STATUS_RX_NOT_FULL_MASK         0x00000f00
+#define MBOX_INT_STATUS_RX_NOT_FULL_GET(x)       (((x) & MBOX_INT_STATUS_RX_NOT_FULL_MASK) >> MBOX_INT_STATUS_RX_NOT_FULL_LSB)
+#define MBOX_INT_STATUS_RX_NOT_FULL_SET(x)       (((x) << MBOX_INT_STATUS_RX_NOT_FULL_LSB) & MBOX_INT_STATUS_RX_NOT_FULL_MASK)
+#define MBOX_INT_STATUS_HOST_MSB                 7
+#define MBOX_INT_STATUS_HOST_LSB                 0
+#define MBOX_INT_STATUS_HOST_MASK                0x000000ff
+#define MBOX_INT_STATUS_HOST_GET(x)              (((x) & MBOX_INT_STATUS_HOST_MASK) >> MBOX_INT_STATUS_HOST_LSB)
+#define MBOX_INT_STATUS_HOST_SET(x)              (((x) << MBOX_INT_STATUS_HOST_LSB) & MBOX_INT_STATUS_HOST_MASK)
+
+#define MBOX_INT_ENABLE_ADDRESS                  0x0000005c
+#define MBOX_INT_ENABLE_OFFSET                   0x0000005c
+#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB      31
+#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB      28
+#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK     0xf0000000
+#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x)   (((x) & MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK) >> MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB)
+#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x)   (((x) << MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB) & MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK)
+#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB  27
+#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB  24
+#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK 0x0f000000
+#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) (((x) & MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK) >> MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB)
+#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) (((x) << MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB) & MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK)
+#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB      23
+#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB      20
+#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK     0x00f00000
+#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x)   (((x) & MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK) >> MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB)
+#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x)   (((x) << MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB) & MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK)
+#define MBOX_INT_ENABLE_TX_OVERFLOW_MSB          17
+#define MBOX_INT_ENABLE_TX_OVERFLOW_LSB          17
+#define MBOX_INT_ENABLE_TX_OVERFLOW_MASK         0x00020000
+#define MBOX_INT_ENABLE_TX_OVERFLOW_GET(x)       (((x) & MBOX_INT_ENABLE_TX_OVERFLOW_MASK) >> MBOX_INT_ENABLE_TX_OVERFLOW_LSB)
+#define MBOX_INT_ENABLE_TX_OVERFLOW_SET(x)       (((x) << MBOX_INT_ENABLE_TX_OVERFLOW_LSB) & MBOX_INT_ENABLE_TX_OVERFLOW_MASK)
+#define MBOX_INT_ENABLE_RX_UNDERFLOW_MSB         16
+#define MBOX_INT_ENABLE_RX_UNDERFLOW_LSB         16
+#define MBOX_INT_ENABLE_RX_UNDERFLOW_MASK        0x00010000
+#define MBOX_INT_ENABLE_RX_UNDERFLOW_GET(x)      (((x) & MBOX_INT_ENABLE_RX_UNDERFLOW_MASK) >> MBOX_INT_ENABLE_RX_UNDERFLOW_LSB)
+#define MBOX_INT_ENABLE_RX_UNDERFLOW_SET(x)      (((x) << MBOX_INT_ENABLE_RX_UNDERFLOW_LSB) & MBOX_INT_ENABLE_RX_UNDERFLOW_MASK)
+#define MBOX_INT_ENABLE_TX_NOT_EMPTY_MSB         15
+#define MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB         12
+#define MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK        0x0000f000
+#define MBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x)      (((x) & MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK) >> MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB)
+#define MBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x)      (((x) << MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB) & MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK)
+#define MBOX_INT_ENABLE_RX_NOT_FULL_MSB          11
+#define MBOX_INT_ENABLE_RX_NOT_FULL_LSB          8
+#define MBOX_INT_ENABLE_RX_NOT_FULL_MASK         0x00000f00
+#define MBOX_INT_ENABLE_RX_NOT_FULL_GET(x)       (((x) & MBOX_INT_ENABLE_RX_NOT_FULL_MASK) >> MBOX_INT_ENABLE_RX_NOT_FULL_LSB)
+#define MBOX_INT_ENABLE_RX_NOT_FULL_SET(x)       (((x) << MBOX_INT_ENABLE_RX_NOT_FULL_LSB) & MBOX_INT_ENABLE_RX_NOT_FULL_MASK)
+#define MBOX_INT_ENABLE_HOST_MSB                 7
+#define MBOX_INT_ENABLE_HOST_LSB                 0
+#define MBOX_INT_ENABLE_HOST_MASK                0x000000ff
+#define MBOX_INT_ENABLE_HOST_GET(x)              (((x) & MBOX_INT_ENABLE_HOST_MASK) >> MBOX_INT_ENABLE_HOST_LSB)
+#define MBOX_INT_ENABLE_HOST_SET(x)              (((x) << MBOX_INT_ENABLE_HOST_LSB) & MBOX_INT_ENABLE_HOST_MASK)
+
+#define INT_HOST_ADDRESS                         0x00000060
+#define INT_HOST_OFFSET                          0x00000060
+#define INT_HOST_VECTOR_MSB                      7
+#define INT_HOST_VECTOR_LSB                      0
+#define INT_HOST_VECTOR_MASK                     0x000000ff
+#define INT_HOST_VECTOR_GET(x)                   (((x) & INT_HOST_VECTOR_MASK) >> INT_HOST_VECTOR_LSB)
+#define INT_HOST_VECTOR_SET(x)                   (((x) << INT_HOST_VECTOR_LSB) & INT_HOST_VECTOR_MASK)
+
+#define LOCAL_COUNT_ADDRESS                      0x00000080
+#define LOCAL_COUNT_OFFSET                       0x00000080
+#define LOCAL_COUNT_VALUE_MSB                    7
+#define LOCAL_COUNT_VALUE_LSB                    0
+#define LOCAL_COUNT_VALUE_MASK                   0x000000ff
+#define LOCAL_COUNT_VALUE_GET(x)                 (((x) & LOCAL_COUNT_VALUE_MASK) >> LOCAL_COUNT_VALUE_LSB)
+#define LOCAL_COUNT_VALUE_SET(x)                 (((x) << LOCAL_COUNT_VALUE_LSB) & LOCAL_COUNT_VALUE_MASK)
+
+#define COUNT_INC_ADDRESS                        0x000000a0
+#define COUNT_INC_OFFSET                         0x000000a0
+#define COUNT_INC_VALUE_MSB                      7
+#define COUNT_INC_VALUE_LSB                      0
+#define COUNT_INC_VALUE_MASK                     0x000000ff
+#define COUNT_INC_VALUE_GET(x)                   (((x) & COUNT_INC_VALUE_MASK) >> COUNT_INC_VALUE_LSB)
+#define COUNT_INC_VALUE_SET(x)                   (((x) << COUNT_INC_VALUE_LSB) & COUNT_INC_VALUE_MASK)
+
+#define LOCAL_SCRATCH_ADDRESS                    0x000000c0
+#define LOCAL_SCRATCH_OFFSET                     0x000000c0
+#define LOCAL_SCRATCH_VALUE_MSB                  7
+#define LOCAL_SCRATCH_VALUE_LSB                  0
+#define LOCAL_SCRATCH_VALUE_MASK                 0x000000ff
+#define LOCAL_SCRATCH_VALUE_GET(x)               (((x) & LOCAL_SCRATCH_VALUE_MASK) >> LOCAL_SCRATCH_VALUE_LSB)
+#define LOCAL_SCRATCH_VALUE_SET(x)               (((x) << LOCAL_SCRATCH_VALUE_LSB) & LOCAL_SCRATCH_VALUE_MASK)
+
+#define USE_LOCAL_BUS_ADDRESS                    0x000000e0
+#define USE_LOCAL_BUS_OFFSET                     0x000000e0
+#define USE_LOCAL_BUS_PIN_INIT_MSB               0
+#define USE_LOCAL_BUS_PIN_INIT_LSB               0
+#define USE_LOCAL_BUS_PIN_INIT_MASK              0x00000001
+#define USE_LOCAL_BUS_PIN_INIT_GET(x)            (((x) & USE_LOCAL_BUS_PIN_INIT_MASK) >> USE_LOCAL_BUS_PIN_INIT_LSB)
+#define USE_LOCAL_BUS_PIN_INIT_SET(x)            (((x) << USE_LOCAL_BUS_PIN_INIT_LSB) & USE_LOCAL_BUS_PIN_INIT_MASK)
+
+#define SDIO_CONFIG_ADDRESS                      0x000000e4
+#define SDIO_CONFIG_OFFSET                       0x000000e4
+#define SDIO_CONFIG_CCCR_IOR1_MSB                0
+#define SDIO_CONFIG_CCCR_IOR1_LSB                0
+#define SDIO_CONFIG_CCCR_IOR1_MASK               0x00000001
+#define SDIO_CONFIG_CCCR_IOR1_GET(x)             (((x) & SDIO_CONFIG_CCCR_IOR1_MASK) >> SDIO_CONFIG_CCCR_IOR1_LSB)
+#define SDIO_CONFIG_CCCR_IOR1_SET(x)             (((x) << SDIO_CONFIG_CCCR_IOR1_LSB) & SDIO_CONFIG_CCCR_IOR1_MASK)
+
+#define MBOX_DEBUG_ADDRESS                       0x000000e8
+#define MBOX_DEBUG_OFFSET                        0x000000e8
+#define MBOX_DEBUG_SEL_MSB                       2
+#define MBOX_DEBUG_SEL_LSB                       0
+#define MBOX_DEBUG_SEL_MASK                      0x00000007
+#define MBOX_DEBUG_SEL_GET(x)                    (((x) & MBOX_DEBUG_SEL_MASK) >> MBOX_DEBUG_SEL_LSB)
+#define MBOX_DEBUG_SEL_SET(x)                    (((x) << MBOX_DEBUG_SEL_LSB) & MBOX_DEBUG_SEL_MASK)
+
+#define MBOX_FIFO_RESET_ADDRESS                  0x000000ec
+#define MBOX_FIFO_RESET_OFFSET                   0x000000ec
+#define MBOX_FIFO_RESET_INIT_MSB                 0
+#define MBOX_FIFO_RESET_INIT_LSB                 0
+#define MBOX_FIFO_RESET_INIT_MASK                0x00000001
+#define MBOX_FIFO_RESET_INIT_GET(x)              (((x) & MBOX_FIFO_RESET_INIT_MASK) >> MBOX_FIFO_RESET_INIT_LSB)
+#define MBOX_FIFO_RESET_INIT_SET(x)              (((x) << MBOX_FIFO_RESET_INIT_LSB) & MBOX_FIFO_RESET_INIT_MASK)
+
+#define MBOX_TXFIFO_POP_ADDRESS                  0x000000f0
+#define MBOX_TXFIFO_POP_OFFSET                   0x000000f0
+#define MBOX_TXFIFO_POP_DATA_MSB                 0
+#define MBOX_TXFIFO_POP_DATA_LSB                 0
+#define MBOX_TXFIFO_POP_DATA_MASK                0x00000001
+#define MBOX_TXFIFO_POP_DATA_GET(x)              (((x) & MBOX_TXFIFO_POP_DATA_MASK) >> MBOX_TXFIFO_POP_DATA_LSB)
+#define MBOX_TXFIFO_POP_DATA_SET(x)              (((x) << MBOX_TXFIFO_POP_DATA_LSB) & MBOX_TXFIFO_POP_DATA_MASK)
+
+#define MBOX_RXFIFO_POP_ADDRESS                  0x00000100
+#define MBOX_RXFIFO_POP_OFFSET                   0x00000100
+#define MBOX_RXFIFO_POP_DATA_MSB                 0
+#define MBOX_RXFIFO_POP_DATA_LSB                 0
+#define MBOX_RXFIFO_POP_DATA_MASK                0x00000001
+#define MBOX_RXFIFO_POP_DATA_GET(x)              (((x) & MBOX_RXFIFO_POP_DATA_MASK) >> MBOX_RXFIFO_POP_DATA_LSB)
+#define MBOX_RXFIFO_POP_DATA_SET(x)              (((x) << MBOX_RXFIFO_POP_DATA_LSB) & MBOX_RXFIFO_POP_DATA_MASK)
+
+#define SDIO_DEBUG_ADDRESS                       0x00000110
+#define SDIO_DEBUG_OFFSET                        0x00000110
+#define SDIO_DEBUG_SEL_MSB                       3
+#define SDIO_DEBUG_SEL_LSB                       0
+#define SDIO_DEBUG_SEL_MASK                      0x0000000f
+#define SDIO_DEBUG_SEL_GET(x)                    (((x) & SDIO_DEBUG_SEL_MASK) >> SDIO_DEBUG_SEL_LSB)
+#define SDIO_DEBUG_SEL_SET(x)                    (((x) << SDIO_DEBUG_SEL_LSB) & SDIO_DEBUG_SEL_MASK)
+
+#define HOST_IF_WINDOW_ADDRESS                   0x00002000
+#define HOST_IF_WINDOW_OFFSET                    0x00002000
+#define HOST_IF_WINDOW_DATA_MSB                  7
+#define HOST_IF_WINDOW_DATA_LSB                  0
+#define HOST_IF_WINDOW_DATA_MASK                 0x000000ff
+#define HOST_IF_WINDOW_DATA_GET(x)               (((x) & HOST_IF_WINDOW_DATA_MASK) >> HOST_IF_WINDOW_DATA_LSB)
+#define HOST_IF_WINDOW_DATA_SET(x)               (((x) << HOST_IF_WINDOW_DATA_LSB) & HOST_IF_WINDOW_DATA_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct mbox_reg_reg_s {
+  volatile unsigned int mbox_fifo[4];
+  volatile unsigned int mbox_fifo_status;
+  volatile unsigned int mbox_dma_policy;
+  volatile unsigned int mbox0_dma_rx_descriptor_base;
+  volatile unsigned int mbox0_dma_rx_control;
+  volatile unsigned int mbox0_dma_tx_descriptor_base;
+  volatile unsigned int mbox0_dma_tx_control;
+  volatile unsigned int mbox1_dma_rx_descriptor_base;
+  volatile unsigned int mbox1_dma_rx_control;
+  volatile unsigned int mbox1_dma_tx_descriptor_base;
+  volatile unsigned int mbox1_dma_tx_control;
+  volatile unsigned int mbox2_dma_rx_descriptor_base;
+  volatile unsigned int mbox2_dma_rx_control;
+  volatile unsigned int mbox2_dma_tx_descriptor_base;
+  volatile unsigned int mbox2_dma_tx_control;
+  volatile unsigned int mbox3_dma_rx_descriptor_base;
+  volatile unsigned int mbox3_dma_rx_control;
+  volatile unsigned int mbox3_dma_tx_descriptor_base;
+  volatile unsigned int mbox3_dma_tx_control;
+  volatile unsigned int mbox_int_status;
+  volatile unsigned int mbox_int_enable;
+  volatile unsigned int int_host;
+  unsigned char pad0[28]; /* pad to 0x80 */
+  volatile unsigned int local_count[8];
+  volatile unsigned int count_inc[8];
+  volatile unsigned int local_scratch[8];
+  volatile unsigned int use_local_bus;
+  volatile unsigned int sdio_config;
+  volatile unsigned int mbox_debug;
+  volatile unsigned int mbox_fifo_reset;
+  volatile unsigned int mbox_txfifo_pop[4];
+  volatile unsigned int mbox_rxfifo_pop[4];
+  volatile unsigned int sdio_debug;
+  unsigned char pad1[7916]; /* pad to 0x2000 */
+  volatile unsigned int host_if_window[2048];
+} mbox_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _MBOX_REG_H_ */
diff --git a/drivers/net/ath6kl/include/common/AR6002/hw2.0/hw/rtc_reg.h b/drivers/net/ath6kl/include/common/AR6002/hw2.0/hw/rtc_reg.h
new file mode 100644
index 00000000000..8b3980afb64
--- /dev/null
+++ b/drivers/net/ath6kl/include/common/AR6002/hw2.0/hw/rtc_reg.h
@@ -0,0 +1,1163 @@
+#ifndef _RTC_REG_REG_H_
+#define _RTC_REG_REG_H_
+
+#define RESET_CONTROL_ADDRESS                    0x00000000
+#define RESET_CONTROL_OFFSET                     0x00000000
+#define RESET_CONTROL_CPU_INIT_RESET_MSB         11
+#define RESET_CONTROL_CPU_INIT_RESET_LSB         11
+#define RESET_CONTROL_CPU_INIT_RESET_MASK        0x00000800
+#define RESET_CONTROL_CPU_INIT_RESET_GET(x)      (((x) & RESET_CONTROL_CPU_INIT_RESET_MASK) >> RESET_CONTROL_CPU_INIT_RESET_LSB)
+#define RESET_CONTROL_CPU_INIT_RESET_SET(x)      (((x) << RESET_CONTROL_CPU_INIT_RESET_LSB) & RESET_CONTROL_CPU_INIT_RESET_MASK)
+#define RESET_CONTROL_VMC_REMAP_RESET_MSB        10
+#define RESET_CONTROL_VMC_REMAP_RESET_LSB        10
+#define RESET_CONTROL_VMC_REMAP_RESET_MASK       0x00000400
+#define RESET_CONTROL_VMC_REMAP_RESET_GET(x)     (((x) & RESET_CONTROL_VMC_REMAP_RESET_MASK) >> RESET_CONTROL_VMC_REMAP_RESET_LSB)
+#define RESET_CONTROL_VMC_REMAP_RESET_SET(x)     (((x) << RESET_CONTROL_VMC_REMAP_RESET_LSB) & RESET_CONTROL_VMC_REMAP_RESET_MASK)
+#define RESET_CONTROL_RST_OUT_MSB                9
+#define RESET_CONTROL_RST_OUT_LSB                9
+#define RESET_CONTROL_RST_OUT_MASK               0x00000200
+#define RESET_CONTROL_RST_OUT_GET(x)             (((x) & RESET_CONTROL_RST_OUT_MASK) >> RESET_CONTROL_RST_OUT_LSB)
+#define RESET_CONTROL_RST_OUT_SET(x)             (((x) << RESET_CONTROL_RST_OUT_LSB) & RESET_CONTROL_RST_OUT_MASK)
+#define RESET_CONTROL_COLD_RST_MSB               8
+#define RESET_CONTROL_COLD_RST_LSB               8
+#define RESET_CONTROL_COLD_RST_MASK              0x00000100
+#define RESET_CONTROL_COLD_RST_GET(x)            (((x) & RESET_CONTROL_COLD_RST_MASK) >> RESET_CONTROL_COLD_RST_LSB)
+#define RESET_CONTROL_COLD_RST_SET(x)            (((x) << RESET_CONTROL_COLD_RST_LSB) & RESET_CONTROL_COLD_RST_MASK)
+#define RESET_CONTROL_WARM_RST_MSB               7
+#define RESET_CONTROL_WARM_RST_LSB               7
+#define RESET_CONTROL_WARM_RST_MASK              0x00000080
+#define RESET_CONTROL_WARM_RST_GET(x)            (((x) & RESET_CONTROL_WARM_RST_MASK) >> RESET_CONTROL_WARM_RST_LSB)
+#define RESET_CONTROL_WARM_RST_SET(x)            (((x) << RESET_CONTROL_WARM_RST_LSB) & RESET_CONTROL_WARM_RST_MASK)
+#define RESET_CONTROL_CPU_WARM_RST_MSB           6
+#define RESET_CONTROL_CPU_WARM_RST_LSB           6
+#define RESET_CONTROL_CPU_WARM_RST_MASK          0x00000040
+#define RESET_CONTROL_CPU_WARM_RST_GET(x)        (((x) & RESET_CONTROL_CPU_WARM_RST_MASK) >> RESET_CONTROL_CPU_WARM_RST_LSB)
+#define RESET_CONTROL_CPU_WARM_RST_SET(x)        (((x) << RESET_CONTROL_CPU_WARM_RST_LSB) & RESET_CONTROL_CPU_WARM_RST_MASK)
+#define RESET_CONTROL_MAC_COLD_RST_MSB           5
+#define RESET_CONTROL_MAC_COLD_RST_LSB           5
+#define RESET_CONTROL_MAC_COLD_RST_MASK          0x00000020
+#define RESET_CONTROL_MAC_COLD_RST_GET(x)        (((x) & RESET_CONTROL_MAC_COLD_RST_MASK) >> RESET_CONTROL_MAC_COLD_RST_LSB)
+#define RESET_CONTROL_MAC_COLD_RST_SET(x)        (((x) << RESET_CONTROL_MAC_COLD_RST_LSB) & RESET_CONTROL_MAC_COLD_RST_MASK)
+#define RESET_CONTROL_MAC_WARM_RST_MSB           4
+#define RESET_CONTROL_MAC_WARM_RST_LSB           4
+#define RESET_CONTROL_MAC_WARM_RST_MASK          0x00000010
+#define RESET_CONTROL_MAC_WARM_RST_GET(x)        (((x) & RESET_CONTROL_MAC_WARM_RST_MASK) >> RESET_CONTROL_MAC_WARM_RST_LSB)
+#define RESET_CONTROL_MAC_WARM_RST_SET(x)        (((x) << RESET_CONTROL_MAC_WARM_RST_LSB) & RESET_CONTROL_MAC_WARM_RST_MASK)
+#define RESET_CONTROL_MBOX_RST_MSB               2
+#define RESET_CONTROL_MBOX_RST_LSB               2
+#define RESET_CONTROL_MBOX_RST_MASK              0x00000004
+#define RESET_CONTROL_MBOX_RST_GET(x)            (((x) & RESET_CONTROL_MBOX_RST_MASK) >> RESET_CONTROL_MBOX_RST_LSB)
+#define RESET_CONTROL_MBOX_RST_SET(x)            (((x) << RESET_CONTROL_MBOX_RST_LSB) & RESET_CONTROL_MBOX_RST_MASK)
+#define RESET_CONTROL_UART_RST_MSB               1
+#define RESET_CONTROL_UART_RST_LSB               1
+#define RESET_CONTROL_UART_RST_MASK              0x00000002
+#define RESET_CONTROL_UART_RST_GET(x)            (((x) & RESET_CONTROL_UART_RST_MASK) >> RESET_CONTROL_UART_RST_LSB)
+#define RESET_CONTROL_UART_RST_SET(x)            (((x) << RESET_CONTROL_UART_RST_LSB) & RESET_CONTROL_UART_RST_MASK)
+#define RESET_CONTROL_SI0_RST_MSB                0
+#define RESET_CONTROL_SI0_RST_LSB                0
+#define RESET_CONTROL_SI0_RST_MASK               0x00000001
+#define RESET_CONTROL_SI0_RST_GET(x)             (((x) & RESET_CONTROL_SI0_RST_MASK) >> RESET_CONTROL_SI0_RST_LSB)
+#define RESET_CONTROL_SI0_RST_SET(x)             (((x) << RESET_CONTROL_SI0_RST_LSB) & RESET_CONTROL_SI0_RST_MASK)
+
+#define XTAL_CONTROL_ADDRESS                     0x00000004
+#define XTAL_CONTROL_OFFSET                      0x00000004
+#define XTAL_CONTROL_TCXO_MSB                    0
+#define XTAL_CONTROL_TCXO_LSB                    0
+#define XTAL_CONTROL_TCXO_MASK                   0x00000001
+#define XTAL_CONTROL_TCXO_GET(x)                 (((x) & XTAL_CONTROL_TCXO_MASK) >> XTAL_CONTROL_TCXO_LSB)
+#define XTAL_CONTROL_TCXO_SET(x)                 (((x) << XTAL_CONTROL_TCXO_LSB) & XTAL_CONTROL_TCXO_MASK)
+
+#define TCXO_DETECT_ADDRESS                      0x00000008
+#define TCXO_DETECT_OFFSET                       0x00000008
+#define TCXO_DETECT_PRESENT_MSB                  0
+#define TCXO_DETECT_PRESENT_LSB                  0
+#define TCXO_DETECT_PRESENT_MASK                 0x00000001
+#define TCXO_DETECT_PRESENT_GET(x)               (((x) & TCXO_DETECT_PRESENT_MASK) >> TCXO_DETECT_PRESENT_LSB)
+#define TCXO_DETECT_PRESENT_SET(x)               (((x) << TCXO_DETECT_PRESENT_LSB) & TCXO_DETECT_PRESENT_MASK)
+
+#define XTAL_TEST_ADDRESS                        0x0000000c
+#define XTAL_TEST_OFFSET                         0x0000000c
+#define XTAL_TEST_NOTCXODET_MSB                  0
+#define XTAL_TEST_NOTCXODET_LSB                  0
+#define XTAL_TEST_NOTCXODET_MASK                 0x00000001
+#define XTAL_TEST_NOTCXODET_GET(x)               (((x) & XTAL_TEST_NOTCXODET_MASK) >> XTAL_TEST_NOTCXODET_LSB)
+#define XTAL_TEST_NOTCXODET_SET(x)               (((x) << XTAL_TEST_NOTCXODET_LSB) & XTAL_TEST_NOTCXODET_MASK)
+
+#define QUADRATURE_ADDRESS                       0x00000010
+#define QUADRATURE_OFFSET                        0x00000010
+#define QUADRATURE_ADC_MSB                       5
+#define QUADRATURE_ADC_LSB                       4
+#define QUADRATURE_ADC_MASK                      0x00000030
+#define QUADRATURE_ADC_GET(x)                    (((x) & QUADRATURE_ADC_MASK) >> QUADRATURE_ADC_LSB)
+#define QUADRATURE_ADC_SET(x)                    (((x) << QUADRATURE_ADC_LSB) & QUADRATURE_ADC_MASK)
+#define QUADRATURE_SEL_MSB                       2
+#define QUADRATURE_SEL_LSB                       2
+#define QUADRATURE_SEL_MASK                      0x00000004
+#define QUADRATURE_SEL_GET(x)                    (((x) & QUADRATURE_SEL_MASK) >> QUADRATURE_SEL_LSB)
+#define QUADRATURE_SEL_SET(x)                    (((x) << QUADRATURE_SEL_LSB) & QUADRATURE_SEL_MASK)
+#define QUADRATURE_DAC_MSB                       1
+#define QUADRATURE_DAC_LSB                       0
+#define QUADRATURE_DAC_MASK                      0x00000003
+#define QUADRATURE_DAC_GET(x)                    (((x) & QUADRATURE_DAC_MASK) >> QUADRATURE_DAC_LSB)
+#define QUADRATURE_DAC_SET(x)                    (((x) << QUADRATURE_DAC_LSB) & QUADRATURE_DAC_MASK)
+
+#define PLL_CONTROL_ADDRESS                      0x00000014
+#define PLL_CONTROL_OFFSET                       0x00000014
+#define PLL_CONTROL_DIG_TEST_CLK_MSB             20
+#define PLL_CONTROL_DIG_TEST_CLK_LSB             20
+#define PLL_CONTROL_DIG_TEST_CLK_MASK            0x00100000
+#define PLL_CONTROL_DIG_TEST_CLK_GET(x)          (((x) & PLL_CONTROL_DIG_TEST_CLK_MASK) >> PLL_CONTROL_DIG_TEST_CLK_LSB)
+#define PLL_CONTROL_DIG_TEST_CLK_SET(x)          (((x) << PLL_CONTROL_DIG_TEST_CLK_LSB) & PLL_CONTROL_DIG_TEST_CLK_MASK)
+#define PLL_CONTROL_MAC_OVERRIDE_MSB             19
+#define PLL_CONTROL_MAC_OVERRIDE_LSB             19
+#define PLL_CONTROL_MAC_OVERRIDE_MASK            0x00080000
+#define PLL_CONTROL_MAC_OVERRIDE_GET(x)          (((x) & PLL_CONTROL_MAC_OVERRIDE_MASK) >> PLL_CONTROL_MAC_OVERRIDE_LSB)
+#define PLL_CONTROL_MAC_OVERRIDE_SET(x)          (((x) << PLL_CONTROL_MAC_OVERRIDE_LSB) & PLL_CONTROL_MAC_OVERRIDE_MASK)
+#define PLL_CONTROL_NOPWD_MSB                    18
+#define PLL_CONTROL_NOPWD_LSB                    18
+#define PLL_CONTROL_NOPWD_MASK                   0x00040000
+#define PLL_CONTROL_NOPWD_GET(x)                 (((x) & PLL_CONTROL_NOPWD_MASK) >> PLL_CONTROL_NOPWD_LSB)
+#define PLL_CONTROL_NOPWD_SET(x)                 (((x) << PLL_CONTROL_NOPWD_LSB) & PLL_CONTROL_NOPWD_MASK)
+#define PLL_CONTROL_UPDATING_MSB                 17
+#define PLL_CONTROL_UPDATING_LSB                 17
+#define PLL_CONTROL_UPDATING_MASK                0x00020000
+#define PLL_CONTROL_UPDATING_GET(x)              (((x) & PLL_CONTROL_UPDATING_MASK) >> PLL_CONTROL_UPDATING_LSB)
+#define PLL_CONTROL_UPDATING_SET(x)              (((x) << PLL_CONTROL_UPDATING_LSB) & PLL_CONTROL_UPDATING_MASK)
+#define PLL_CONTROL_BYPASS_MSB                   16
+#define PLL_CONTROL_BYPASS_LSB                   16
+#define PLL_CONTROL_BYPASS_MASK                  0x00010000
+#define PLL_CONTROL_BYPASS_GET(x)                (((x) & PLL_CONTROL_BYPASS_MASK) >> PLL_CONTROL_BYPASS_LSB)
+#define PLL_CONTROL_BYPASS_SET(x)                (((x) << PLL_CONTROL_BYPASS_LSB) & PLL_CONTROL_BYPASS_MASK)
+#define PLL_CONTROL_REFDIV_MSB                   15
+#define PLL_CONTROL_REFDIV_LSB                   12
+#define PLL_CONTROL_REFDIV_MASK                  0x0000f000
+#define PLL_CONTROL_REFDIV_GET(x)                (((x) & PLL_CONTROL_REFDIV_MASK) >> PLL_CONTROL_REFDIV_LSB)
+#define PLL_CONTROL_REFDIV_SET(x)                (((x) << PLL_CONTROL_REFDIV_LSB) & PLL_CONTROL_REFDIV_MASK)
+#define PLL_CONTROL_DIV_MSB                      9
+#define PLL_CONTROL_DIV_LSB                      0
+#define PLL_CONTROL_DIV_MASK                     0x000003ff
+#define PLL_CONTROL_DIV_GET(x)                   (((x) & PLL_CONTROL_DIV_MASK) >> PLL_CONTROL_DIV_LSB)
+#define PLL_CONTROL_DIV_SET(x)                   (((x) << PLL_CONTROL_DIV_LSB) & PLL_CONTROL_DIV_MASK)
+
+#define PLL_SETTLE_ADDRESS                       0x00000018
+#define PLL_SETTLE_OFFSET                        0x00000018
+#define PLL_SETTLE_TIME_MSB                      11
+#define PLL_SETTLE_TIME_LSB                      0
+#define PLL_SETTLE_TIME_MASK                     0x00000fff
+#define PLL_SETTLE_TIME_GET(x)                   (((x) & PLL_SETTLE_TIME_MASK) >> PLL_SETTLE_TIME_LSB)
+#define PLL_SETTLE_TIME_SET(x)                   (((x) << PLL_SETTLE_TIME_LSB) & PLL_SETTLE_TIME_MASK)
+
+#define XTAL_SETTLE_ADDRESS                      0x0000001c
+#define XTAL_SETTLE_OFFSET                       0x0000001c
+#define XTAL_SETTLE_TIME_MSB                     7
+#define XTAL_SETTLE_TIME_LSB                     0
+#define XTAL_SETTLE_TIME_MASK                    0x000000ff
+#define XTAL_SETTLE_TIME_GET(x)                  (((x) & XTAL_SETTLE_TIME_MASK) >> XTAL_SETTLE_TIME_LSB)
+#define XTAL_SETTLE_TIME_SET(x)                  (((x) << XTAL_SETTLE_TIME_LSB) & XTAL_SETTLE_TIME_MASK)
+
+#define CPU_CLOCK_ADDRESS                        0x00000020
+#define CPU_CLOCK_OFFSET                         0x00000020
+#define CPU_CLOCK_STANDARD_MSB                   1
+#define CPU_CLOCK_STANDARD_LSB                   0
+#define CPU_CLOCK_STANDARD_MASK                  0x00000003
+#define CPU_CLOCK_STANDARD_GET(x)                (((x) & CPU_CLOCK_STANDARD_MASK) >> CPU_CLOCK_STANDARD_LSB)
+#define CPU_CLOCK_STANDARD_SET(x)                (((x) << CPU_CLOCK_STANDARD_LSB) & CPU_CLOCK_STANDARD_MASK)
+
+#define CLOCK_OUT_ADDRESS                        0x00000024
+#define CLOCK_OUT_OFFSET                         0x00000024
+#define CLOCK_OUT_SELECT_MSB                     3
+#define CLOCK_OUT_SELECT_LSB                     0
+#define CLOCK_OUT_SELECT_MASK                    0x0000000f
+#define CLOCK_OUT_SELECT_GET(x)                  (((x) & CLOCK_OUT_SELECT_MASK) >> CLOCK_OUT_SELECT_LSB)
+#define CLOCK_OUT_SELECT_SET(x)                  (((x) << CLOCK_OUT_SELECT_LSB) & CLOCK_OUT_SELECT_MASK)
+
+#define CLOCK_CONTROL_ADDRESS                    0x00000028
+#define CLOCK_CONTROL_OFFSET                     0x00000028
+#define CLOCK_CONTROL_LF_CLK32_MSB               2
+#define CLOCK_CONTROL_LF_CLK32_LSB               2
+#define CLOCK_CONTROL_LF_CLK32_MASK              0x00000004
+#define CLOCK_CONTROL_LF_CLK32_GET(x)            (((x) & CLOCK_CONTROL_LF_CLK32_MASK) >> CLOCK_CONTROL_LF_CLK32_LSB)
+#define CLOCK_CONTROL_LF_CLK32_SET(x)            (((x) << CLOCK_CONTROL_LF_CLK32_LSB) & CLOCK_CONTROL_LF_CLK32_MASK)
+#define CLOCK_CONTROL_UART_CLK_MSB               1
+#define CLOCK_CONTROL_UART_CLK_LSB               1
+#define CLOCK_CONTROL_UART_CLK_MASK              0x00000002
+#define CLOCK_CONTROL_UART_CLK_GET(x)            (((x) & CLOCK_CONTROL_UART_CLK_MASK) >> CLOCK_CONTROL_UART_CLK_LSB)
+#define CLOCK_CONTROL_UART_CLK_SET(x)            (((x) << CLOCK_CONTROL_UART_CLK_LSB) & CLOCK_CONTROL_UART_CLK_MASK)
+#define CLOCK_CONTROL_SI0_CLK_MSB                0
+#define CLOCK_CONTROL_SI0_CLK_LSB                0
+#define CLOCK_CONTROL_SI0_CLK_MASK               0x00000001
+#define CLOCK_CONTROL_SI0_CLK_GET(x)             (((x) & CLOCK_CONTROL_SI0_CLK_MASK) >> CLOCK_CONTROL_SI0_CLK_LSB)
+#define CLOCK_CONTROL_SI0_CLK_SET(x)             (((x) << CLOCK_CONTROL_SI0_CLK_LSB) & CLOCK_CONTROL_SI0_CLK_MASK)
+
+#define BIAS_OVERRIDE_ADDRESS                    0x0000002c
+#define BIAS_OVERRIDE_OFFSET                     0x0000002c
+#define BIAS_OVERRIDE_ON_MSB                     0
+#define BIAS_OVERRIDE_ON_LSB                     0
+#define BIAS_OVERRIDE_ON_MASK                    0x00000001
+#define BIAS_OVERRIDE_ON_GET(x)                  (((x) & BIAS_OVERRIDE_ON_MASK) >> BIAS_OVERRIDE_ON_LSB)
+#define BIAS_OVERRIDE_ON_SET(x)                  (((x) << BIAS_OVERRIDE_ON_LSB) & BIAS_OVERRIDE_ON_MASK)
+
+#define WDT_CONTROL_ADDRESS                      0x00000030
+#define WDT_CONTROL_OFFSET                       0x00000030
+#define WDT_CONTROL_ACTION_MSB                   2
+#define WDT_CONTROL_ACTION_LSB                   0
+#define WDT_CONTROL_ACTION_MASK                  0x00000007
+#define WDT_CONTROL_ACTION_GET(x)                (((x) & WDT_CONTROL_ACTION_MASK) >> WDT_CONTROL_ACTION_LSB)
+#define WDT_CONTROL_ACTION_SET(x)                (((x) << WDT_CONTROL_ACTION_LSB) & WDT_CONTROL_ACTION_MASK)
+
+#define WDT_STATUS_ADDRESS                       0x00000034
+#define WDT_STATUS_OFFSET                        0x00000034
+#define WDT_STATUS_INTERRUPT_MSB                 0
+#define WDT_STATUS_INTERRUPT_LSB                 0
+#define WDT_STATUS_INTERRUPT_MASK                0x00000001
+#define WDT_STATUS_INTERRUPT_GET(x)              (((x) & WDT_STATUS_INTERRUPT_MASK) >> WDT_STATUS_INTERRUPT_LSB)
+#define WDT_STATUS_INTERRUPT_SET(x)              (((x) << WDT_STATUS_INTERRUPT_LSB) & WDT_STATUS_INTERRUPT_MASK)
+
+#define WDT_ADDRESS                              0x00000038
+#define WDT_OFFSET                               0x00000038
+#define WDT_TARGET_MSB                           21
+#define WDT_TARGET_LSB                           0
+#define WDT_TARGET_MASK                          0x003fffff
+#define WDT_TARGET_GET(x)                        (((x) & WDT_TARGET_MASK) >> WDT_TARGET_LSB)
+#define WDT_TARGET_SET(x)                        (((x) << WDT_TARGET_LSB) & WDT_TARGET_MASK)
+
+#define WDT_COUNT_ADDRESS                        0x0000003c
+#define WDT_COUNT_OFFSET                         0x0000003c
+#define WDT_COUNT_VALUE_MSB                      21
+#define WDT_COUNT_VALUE_LSB                      0
+#define WDT_COUNT_VALUE_MASK                     0x003fffff
+#define WDT_COUNT_VALUE_GET(x)                   (((x) & WDT_COUNT_VALUE_MASK) >> WDT_COUNT_VALUE_LSB)
+#define WDT_COUNT_VALUE_SET(x)                   (((x) << WDT_COUNT_VALUE_LSB) & WDT_COUNT_VALUE_MASK)
+
+#define WDT_RESET_ADDRESS                        0x00000040
+#define WDT_RESET_OFFSET                         0x00000040
+#define WDT_RESET_VALUE_MSB                      0
+#define WDT_RESET_VALUE_LSB                      0
+#define WDT_RESET_VALUE_MASK                     0x00000001
+#define WDT_RESET_VALUE_GET(x)                   (((x) & WDT_RESET_VALUE_MASK) >> WDT_RESET_VALUE_LSB)
+#define WDT_RESET_VALUE_SET(x)                   (((x) << WDT_RESET_VALUE_LSB) & WDT_RESET_VALUE_MASK)
+
+#define INT_STATUS_ADDRESS                       0x00000044
+#define INT_STATUS_OFFSET                        0x00000044
+#define INT_STATUS_RTC_POWER_MSB                 14
+#define INT_STATUS_RTC_POWER_LSB                 14
+#define INT_STATUS_RTC_POWER_MASK                0x00004000
+#define INT_STATUS_RTC_POWER_GET(x)              (((x) & INT_STATUS_RTC_POWER_MASK) >> INT_STATUS_RTC_POWER_LSB)
+#define INT_STATUS_RTC_POWER_SET(x)              (((x) << INT_STATUS_RTC_POWER_LSB) & INT_STATUS_RTC_POWER_MASK)
+#define INT_STATUS_MAC_MSB                       13
+#define INT_STATUS_MAC_LSB                       13
+#define INT_STATUS_MAC_MASK                      0x00002000
+#define INT_STATUS_MAC_GET(x)                    (((x) & INT_STATUS_MAC_MASK) >> INT_STATUS_MAC_LSB)
+#define INT_STATUS_MAC_SET(x)                    (((x) << INT_STATUS_MAC_LSB) & INT_STATUS_MAC_MASK)
+#define INT_STATUS_MAILBOX_MSB                   12
+#define INT_STATUS_MAILBOX_LSB                   12
+#define INT_STATUS_MAILBOX_MASK                  0x00001000
+#define INT_STATUS_MAILBOX_GET(x)                (((x) & INT_STATUS_MAILBOX_MASK) >> INT_STATUS_MAILBOX_LSB)
+#define INT_STATUS_MAILBOX_SET(x)                (((x) << INT_STATUS_MAILBOX_LSB) & INT_STATUS_MAILBOX_MASK)
+#define INT_STATUS_RTC_ALARM_MSB                 11
+#define INT_STATUS_RTC_ALARM_LSB                 11
+#define INT_STATUS_RTC_ALARM_MASK                0x00000800
+#define INT_STATUS_RTC_ALARM_GET(x)              (((x) & INT_STATUS_RTC_ALARM_MASK) >> INT_STATUS_RTC_ALARM_LSB)
+#define INT_STATUS_RTC_ALARM_SET(x)              (((x) << INT_STATUS_RTC_ALARM_LSB) & INT_STATUS_RTC_ALARM_MASK)
+#define INT_STATUS_HF_TIMER_MSB                  10
+#define INT_STATUS_HF_TIMER_LSB                  10
+#define INT_STATUS_HF_TIMER_MASK                 0x00000400
+#define INT_STATUS_HF_TIMER_GET(x)               (((x) & INT_STATUS_HF_TIMER_MASK) >> INT_STATUS_HF_TIMER_LSB)
+#define INT_STATUS_HF_TIMER_SET(x)               (((x) << INT_STATUS_HF_TIMER_LSB) & INT_STATUS_HF_TIMER_MASK)
+#define INT_STATUS_LF_TIMER3_MSB                 9
+#define INT_STATUS_LF_TIMER3_LSB                 9
+#define INT_STATUS_LF_TIMER3_MASK                0x00000200
+#define INT_STATUS_LF_TIMER3_GET(x)              (((x) & INT_STATUS_LF_TIMER3_MASK) >> INT_STATUS_LF_TIMER3_LSB)
+#define INT_STATUS_LF_TIMER3_SET(x)              (((x) << INT_STATUS_LF_TIMER3_LSB) & INT_STATUS_LF_TIMER3_MASK)
+#define INT_STATUS_LF_TIMER2_MSB                 8
+#define INT_STATUS_LF_TIMER2_LSB                 8
+#define INT_STATUS_LF_TIMER2_MASK                0x00000100
+#define INT_STATUS_LF_TIMER2_GET(x)              (((x) & INT_STATUS_LF_TIMER2_MASK) >> INT_STATUS_LF_TIMER2_LSB)
+#define INT_STATUS_LF_TIMER2_SET(x)              (((x) << INT_STATUS_LF_TIMER2_LSB) & INT_STATUS_LF_TIMER2_MASK)
+#define INT_STATUS_LF_TIMER1_MSB                 7
+#define INT_STATUS_LF_TIMER1_LSB                 7
+#define INT_STATUS_LF_TIMER1_MASK                0x00000080
+#define INT_STATUS_LF_TIMER1_GET(x)              (((x) & INT_STATUS_LF_TIMER1_MASK) >> INT_STATUS_LF_TIMER1_LSB)
+#define INT_STATUS_LF_TIMER1_SET(x)              (((x) << INT_STATUS_LF_TIMER1_LSB) & INT_STATUS_LF_TIMER1_MASK)
+#define INT_STATUS_LF_TIMER0_MSB                 6
+#define INT_STATUS_LF_TIMER0_LSB                 6
+#define INT_STATUS_LF_TIMER0_MASK                0x00000040
+#define INT_STATUS_LF_TIMER0_GET(x)              (((x) & INT_STATUS_LF_TIMER0_MASK) >> INT_STATUS_LF_TIMER0_LSB)
+#define INT_STATUS_LF_TIMER0_SET(x)              (((x) << INT_STATUS_LF_TIMER0_LSB) & INT_STATUS_LF_TIMER0_MASK)
+#define INT_STATUS_KEYPAD_MSB                    5
+#define INT_STATUS_KEYPAD_LSB                    5
+#define INT_STATUS_KEYPAD_MASK                   0x00000020
+#define INT_STATUS_KEYPAD_GET(x)                 (((x) & INT_STATUS_KEYPAD_MASK) >> INT_STATUS_KEYPAD_LSB)
+#define INT_STATUS_KEYPAD_SET(x)                 (((x) << INT_STATUS_KEYPAD_LSB) & INT_STATUS_KEYPAD_MASK)
+#define INT_STATUS_SI_MSB                        4
+#define INT_STATUS_SI_LSB                        4
+#define INT_STATUS_SI_MASK                       0x00000010
+#define INT_STATUS_SI_GET(x)                     (((x) & INT_STATUS_SI_MASK) >> INT_STATUS_SI_LSB)
+#define INT_STATUS_SI_SET(x)                     (((x) << INT_STATUS_SI_LSB) & INT_STATUS_SI_MASK)
+#define INT_STATUS_GPIO_MSB                      3
+#define INT_STATUS_GPIO_LSB                      3
+#define INT_STATUS_GPIO_MASK                     0x00000008
+#define INT_STATUS_GPIO_GET(x)                   (((x) & INT_STATUS_GPIO_MASK) >> INT_STATUS_GPIO_LSB)
+#define INT_STATUS_GPIO_SET(x)                   (((x) << INT_STATUS_GPIO_LSB) & INT_STATUS_GPIO_MASK)
+#define INT_STATUS_UART_MSB                      2
+#define INT_STATUS_UART_LSB                      2
+#define INT_STATUS_UART_MASK                     0x00000004
+#define INT_STATUS_UART_GET(x)                   (((x) & INT_STATUS_UART_MASK) >> INT_STATUS_UART_LSB)
+#define INT_STATUS_UART_SET(x)                   (((x) << INT_STATUS_UART_LSB) & INT_STATUS_UART_MASK)
+#define INT_STATUS_ERROR_MSB                     1
+#define INT_STATUS_ERROR_LSB                     1
+#define INT_STATUS_ERROR_MASK                    0x00000002
+#define INT_STATUS_ERROR_GET(x)                  (((x) & INT_STATUS_ERROR_MASK) >> INT_STATUS_ERROR_LSB)
+#define INT_STATUS_ERROR_SET(x)                  (((x) << INT_STATUS_ERROR_LSB) & INT_STATUS_ERROR_MASK)
+#define INT_STATUS_WDT_INT_MSB                   0
+#define INT_STATUS_WDT_INT_LSB                   0
+#define INT_STATUS_WDT_INT_MASK                  0x00000001
+#define INT_STATUS_WDT_INT_GET(x)                (((x) & INT_STATUS_WDT_INT_MASK) >> INT_STATUS_WDT_INT_LSB)
+#define INT_STATUS_WDT_INT_SET(x)                (((x) << INT_STATUS_WDT_INT_LSB) & INT_STATUS_WDT_INT_MASK)
+
+#define LF_TIMER0_ADDRESS                        0x00000048
+#define LF_TIMER0_OFFSET                         0x00000048
+#define LF_TIMER0_TARGET_MSB                     31
+#define LF_TIMER0_TARGET_LSB                     0
+#define LF_TIMER0_TARGET_MASK                    0xffffffff
+#define LF_TIMER0_TARGET_GET(x)                  (((x) & LF_TIMER0_TARGET_MASK) >> LF_TIMER0_TARGET_LSB)
+#define LF_TIMER0_TARGET_SET(x)                  (((x) << LF_TIMER0_TARGET_LSB) & LF_TIMER0_TARGET_MASK)
+
+#define LF_TIMER_COUNT0_ADDRESS                  0x0000004c
+#define LF_TIMER_COUNT0_OFFSET                   0x0000004c
+#define LF_TIMER_COUNT0_VALUE_MSB                31
+#define LF_TIMER_COUNT0_VALUE_LSB                0
+#define LF_TIMER_COUNT0_VALUE_MASK               0xffffffff
+#define LF_TIMER_COUNT0_VALUE_GET(x)             (((x) & LF_TIMER_COUNT0_VALUE_MASK) >> LF_TIMER_COUNT0_VALUE_LSB)
+#define LF_TIMER_COUNT0_VALUE_SET(x)             (((x) << LF_TIMER_COUNT0_VALUE_LSB) & LF_TIMER_COUNT0_VALUE_MASK)
+
+#define LF_TIMER_CONTROL0_ADDRESS                0x00000050
+#define LF_TIMER_CONTROL0_OFFSET                 0x00000050
+#define LF_TIMER_CONTROL0_ENABLE_MSB             2
+#define LF_TIMER_CONTROL0_ENABLE_LSB             2
+#define LF_TIMER_CONTROL0_ENABLE_MASK            0x00000004
+#define LF_TIMER_CONTROL0_ENABLE_GET(x)          (((x) & LF_TIMER_CONTROL0_ENABLE_MASK) >> LF_TIMER_CONTROL0_ENABLE_LSB)
+#define LF_TIMER_CONTROL0_ENABLE_SET(x)          (((x) << LF_TIMER_CONTROL0_ENABLE_LSB) & LF_TIMER_CONTROL0_ENABLE_MASK)
+#define LF_TIMER_CONTROL0_AUTO_RESTART_MSB       1
+#define LF_TIMER_CONTROL0_AUTO_RESTART_LSB       1
+#define LF_TIMER_CONTROL0_AUTO_RESTART_MASK      0x00000002
+#define LF_TIMER_CONTROL0_AUTO_RESTART_GET(x)    (((x) & LF_TIMER_CONTROL0_AUTO_RESTART_MASK) >> LF_TIMER_CONTROL0_AUTO_RESTART_LSB)
+#define LF_TIMER_CONTROL0_AUTO_RESTART_SET(x)    (((x) << LF_TIMER_CONTROL0_AUTO_RESTART_LSB) & LF_TIMER_CONTROL0_AUTO_RESTART_MASK)
+#define LF_TIMER_CONTROL0_RESET_MSB              0
+#define LF_TIMER_CONTROL0_RESET_LSB              0
+#define LF_TIMER_CONTROL0_RESET_MASK             0x00000001
+#define LF_TIMER_CONTROL0_RESET_GET(x)           (((x) & LF_TIMER_CONTROL0_RESET_MASK) >> LF_TIMER_CONTROL0_RESET_LSB)
+#define LF_TIMER_CONTROL0_RESET_SET(x)           (((x) << LF_TIMER_CONTROL0_RESET_LSB) & LF_TIMER_CONTROL0_RESET_MASK)
+
+#define LF_TIMER_STATUS0_ADDRESS                 0x00000054
+#define LF_TIMER_STATUS0_OFFSET                  0x00000054
+#define LF_TIMER_STATUS0_INTERRUPT_MSB           0
+#define LF_TIMER_STATUS0_INTERRUPT_LSB           0
+#define LF_TIMER_STATUS0_INTERRUPT_MASK          0x00000001
+#define LF_TIMER_STATUS0_INTERRUPT_GET(x)        (((x) & LF_TIMER_STATUS0_INTERRUPT_MASK) >> LF_TIMER_STATUS0_INTERRUPT_LSB)
+#define LF_TIMER_STATUS0_INTERRUPT_SET(x)        (((x) << LF_TIMER_STATUS0_INTERRUPT_LSB) & LF_TIMER_STATUS0_INTERRUPT_MASK)
+
+#define LF_TIMER1_ADDRESS                        0x00000058
+#define LF_TIMER1_OFFSET                         0x00000058
+#define LF_TIMER1_TARGET_MSB                     31
+#define LF_TIMER1_TARGET_LSB                     0
+#define LF_TIMER1_TARGET_MASK                    0xffffffff
+#define LF_TIMER1_TARGET_GET(x)                  (((x) & LF_TIMER1_TARGET_MASK) >> LF_TIMER1_TARGET_LSB)
+#define LF_TIMER1_TARGET_SET(x)                  (((x) << LF_TIMER1_TARGET_LSB) & LF_TIMER1_TARGET_MASK)
+
+#define LF_TIMER_COUNT1_ADDRESS                  0x0000005c
+#define LF_TIMER_COUNT1_OFFSET                   0x0000005c
+#define LF_TIMER_COUNT1_VALUE_MSB                31
+#define LF_TIMER_COUNT1_VALUE_LSB                0
+#define LF_TIMER_COUNT1_VALUE_MASK               0xffffffff
+#define LF_TIMER_COUNT1_VALUE_GET(x)             (((x) & LF_TIMER_COUNT1_VALUE_MASK) >> LF_TIMER_COUNT1_VALUE_LSB)
+#define LF_TIMER_COUNT1_VALUE_SET(x)             (((x) << LF_TIMER_COUNT1_VALUE_LSB) & LF_TIMER_COUNT1_VALUE_MASK)
+
+#define LF_TIMER_CONTROL1_ADDRESS                0x00000060
+#define LF_TIMER_CONTROL1_OFFSET                 0x00000060
+#define LF_TIMER_CONTROL1_ENABLE_MSB             2
+#define LF_TIMER_CONTROL1_ENABLE_LSB             2
+#define LF_TIMER_CONTROL1_ENABLE_MASK            0x00000004
+#define LF_TIMER_CONTROL1_ENABLE_GET(x)          (((x) & LF_TIMER_CONTROL1_ENABLE_MASK) >> LF_TIMER_CONTROL1_ENABLE_LSB)
+#define LF_TIMER_CONTROL1_ENABLE_SET(x)          (((x) << LF_TIMER_CONTROL1_ENABLE_LSB) & LF_TIMER_CONTROL1_ENABLE_MASK)
+#define LF_TIMER_CONTROL1_AUTO_RESTART_MSB       1
+#define LF_TIMER_CONTROL1_AUTO_RESTART_LSB       1
+#define LF_TIMER_CONTROL1_AUTO_RESTART_MASK      0x00000002
+#define LF_TIMER_CONTROL1_AUTO_RESTART_GET(x)    (((x) & LF_TIMER_CONTROL1_AUTO_RESTART_MASK) >> LF_TIMER_CONTROL1_AUTO_RESTART_LSB)
+#define LF_TIMER_CONTROL1_AUTO_RESTART_SET(x)    (((x) << LF_TIMER_CONTROL1_AUTO_RESTART_LSB) & LF_TIMER_CONTROL1_AUTO_RESTART_MASK)
+#define LF_TIMER_CONTROL1_RESET_MSB              0
+#define LF_TIMER_CONTROL1_RESET_LSB              0
+#define LF_TIMER_CONTROL1_RESET_MASK             0x00000001
+#define LF_TIMER_CONTROL1_RESET_GET(x)           (((x) & LF_TIMER_CONTROL1_RESET_MASK) >> LF_TIMER_CONTROL1_RESET_LSB)
+#define LF_TIMER_CONTROL1_RESET_SET(x)           (((x) << LF_TIMER_CONTROL1_RESET_LSB) & LF_TIMER_CONTROL1_RESET_MASK)
+
+#define LF_TIMER_STATUS1_ADDRESS                 0x00000064
+#define LF_TIMER_STATUS1_OFFSET                  0x00000064
+#define LF_TIMER_STATUS1_INTERRUPT_MSB           0
+#define LF_TIMER_STATUS1_INTERRUPT_LSB           0
+#define LF_TIMER_STATUS1_INTERRUPT_MASK          0x00000001
+#define LF_TIMER_STATUS1_INTERRUPT_GET(x)        (((x) & LF_TIMER_STATUS1_INTERRUPT_MASK) >> LF_TIMER_STATUS1_INTERRUPT_LSB)
+#define LF_TIMER_STATUS1_INTERRUPT_SET(x)        (((x) << LF_TIMER_STATUS1_INTERRUPT_LSB) & LF_TIMER_STATUS1_INTERRUPT_MASK)
+
+#define LF_TIMER2_ADDRESS                        0x00000068
+#define LF_TIMER2_OFFSET                         0x00000068
+#define LF_TIMER2_TARGET_MSB                     31
+#define LF_TIMER2_TARGET_LSB                     0
+#define LF_TIMER2_TARGET_MASK                    0xffffffff
+#define LF_TIMER2_TARGET_GET(x)                  (((x) & LF_TIMER2_TARGET_MASK) >> LF_TIMER2_TARGET_LSB)
+#define LF_TIMER2_TARGET_SET(x)                  (((x) << LF_TIMER2_TARGET_LSB) & LF_TIMER2_TARGET_MASK)
+
+#define LF_TIMER_COUNT2_ADDRESS                  0x0000006c
+#define LF_TIMER_COUNT2_OFFSET                   0x0000006c
+#define LF_TIMER_COUNT2_VALUE_MSB                31
+#define LF_TIMER_COUNT2_VALUE_LSB                0
+#define LF_TIMER_COUNT2_VALUE_MASK               0xffffffff
+#define LF_TIMER_COUNT2_VALUE_GET(x)             (((x) & LF_TIMER_COUNT2_VALUE_MASK) >> LF_TIMER_COUNT2_VALUE_LSB)
+#define LF_TIMER_COUNT2_VALUE_SET(x)             (((x) << LF_TIMER_COUNT2_VALUE_LSB) & LF_TIMER_COUNT2_VALUE_MASK)
+
+#define LF_TIMER_CONTROL2_ADDRESS                0x00000070
+#define LF_TIMER_CONTROL2_OFFSET                 0x00000070
+#define LF_TIMER_CONTROL2_ENABLE_MSB             2
+#define LF_TIMER_CONTROL2_ENABLE_LSB             2
+#define LF_TIMER_CONTROL2_ENABLE_MASK            0x00000004
+#define LF_TIMER_CONTROL2_ENABLE_GET(x)          (((x) & LF_TIMER_CONTROL2_ENABLE_MASK) >> LF_TIMER_CONTROL2_ENABLE_LSB)
+#define LF_TIMER_CONTROL2_ENABLE_SET(x)          (((x) << LF_TIMER_CONTROL2_ENABLE_LSB) & LF_TIMER_CONTROL2_ENABLE_MASK)
+#define LF_TIMER_CONTROL2_AUTO_RESTART_MSB       1
+#define LF_TIMER_CONTROL2_AUTO_RESTART_LSB       1
+#define LF_TIMER_CONTROL2_AUTO_RESTART_MASK      0x00000002
+#define LF_TIMER_CONTROL2_AUTO_RESTART_GET(x)    (((x) & LF_TIMER_CONTROL2_AUTO_RESTART_MASK) >> LF_TIMER_CONTROL2_AUTO_RESTART_LSB)
+#define LF_TIMER_CONTROL2_AUTO_RESTART_SET(x)    (((x) << LF_TIMER_CONTROL2_AUTO_RESTART_LSB) & LF_TIMER_CONTROL2_AUTO_RESTART_MASK)
+#define LF_TIMER_CONTROL2_RESET_MSB              0
+#define LF_TIMER_CONTROL2_RESET_LSB              0
+#define LF_TIMER_CONTROL2_RESET_MASK             0x00000001
+#define LF_TIMER_CONTROL2_RESET_GET(x)           (((x) & LF_TIMER_CONTROL2_RESET_MASK) >> LF_TIMER_CONTROL2_RESET_LSB)
+#define LF_TIMER_CONTROL2_RESET_SET(x)           (((x) << LF_TIMER_CONTROL2_RESET_LSB) & LF_TIMER_CONTROL2_RESET_MASK)
+
+#define LF_TIMER_STATUS2_ADDRESS                 0x00000074
+#define LF_TIMER_STATUS2_OFFSET                  0x00000074
+#define LF_TIMER_STATUS2_INTERRUPT_MSB           0
+#define LF_TIMER_STATUS2_INTERRUPT_LSB           0
+#define LF_TIMER_STATUS2_INTERRUPT_MASK          0x00000001
+#define LF_TIMER_STATUS2_INTERRUPT_GET(x)        (((x) & LF_TIMER_STATUS2_INTERRUPT_MASK) >> LF_TIMER_STATUS2_INTERRUPT_LSB)
+#define LF_TIMER_STATUS2_INTERRUPT_SET(x)        (((x) << LF_TIMER_STATUS2_INTERRUPT_LSB) & LF_TIMER_STATUS2_INTERRUPT_MASK)
+
+#define LF_TIMER3_ADDRESS                        0x00000078
+#define LF_TIMER3_OFFSET                         0x00000078
+#define LF_TIMER3_TARGET_MSB                     31
+#define LF_TIMER3_TARGET_LSB                     0
+#define LF_TIMER3_TARGET_MASK                    0xffffffff
+#define LF_TIMER3_TARGET_GET(x)                  (((x) & LF_TIMER3_TARGET_MASK) >> LF_TIMER3_TARGET_LSB)
+#define LF_TIMER3_TARGET_SET(x)                  (((x) << LF_TIMER3_TARGET_LSB) & LF_TIMER3_TARGET_MASK)
+
+#define LF_TIMER_COUNT3_ADDRESS                  0x0000007c
+#define LF_TIMER_COUNT3_OFFSET                   0x0000007c
+#define LF_TIMER_COUNT3_VALUE_MSB                31
+#define LF_TIMER_COUNT3_VALUE_LSB                0
+#define LF_TIMER_COUNT3_VALUE_MASK               0xffffffff
+#define LF_TIMER_COUNT3_VALUE_GET(x)             (((x) & LF_TIMER_COUNT3_VALUE_MASK) >> LF_TIMER_COUNT3_VALUE_LSB)
+#define LF_TIMER_COUNT3_VALUE_SET(x)             (((x) << LF_TIMER_COUNT3_VALUE_LSB) & LF_TIMER_COUNT3_VALUE_MASK)
+
+#define LF_TIMER_CONTROL3_ADDRESS                0x00000080
+#define LF_TIMER_CONTROL3_OFFSET                 0x00000080
+#define LF_TIMER_CONTROL3_ENABLE_MSB             2
+#define LF_TIMER_CONTROL3_ENABLE_LSB             2
+#define LF_TIMER_CONTROL3_ENABLE_MASK            0x00000004
+#define LF_TIMER_CONTROL3_ENABLE_GET(x)          (((x) & LF_TIMER_CONTROL3_ENABLE_MASK) >> LF_TIMER_CONTROL3_ENABLE_LSB)
+#define LF_TIMER_CONTROL3_ENABLE_SET(x)          (((x) << LF_TIMER_CONTROL3_ENABLE_LSB) & LF_TIMER_CONTROL3_ENABLE_MASK)
+#define LF_TIMER_CONTROL3_AUTO_RESTART_MSB       1
+#define LF_TIMER_CONTROL3_AUTO_RESTART_LSB       1
+#define LF_TIMER_CONTROL3_AUTO_RESTART_MASK      0x00000002
+#define LF_TIMER_CONTROL3_AUTO_RESTART_GET(x)    (((x) & LF_TIMER_CONTROL3_AUTO_RESTART_MASK) >> LF_TIMER_CONTROL3_AUTO_RESTART_LSB)
+#define LF_TIMER_CONTROL3_AUTO_RESTART_SET(x)    (((x) << LF_TIMER_CONTROL3_AUTO_RESTART_LSB) & LF_TIMER_CONTROL3_AUTO_RESTART_MASK)
+#define LF_TIMER_CONTROL3_RESET_MSB              0
+#define LF_TIMER_CONTROL3_RESET_LSB              0
+#define LF_TIMER_CONTROL3_RESET_MASK             0x00000001
+#define LF_TIMER_CONTROL3_RESET_GET(x)           (((x) & LF_TIMER_CONTROL3_RESET_MASK) >> LF_TIMER_CONTROL3_RESET_LSB)
+#define LF_TIMER_CONTROL3_RESET_SET(x)           (((x) << LF_TIMER_CONTROL3_RESET_LSB) & LF_TIMER_CONTROL3_RESET_MASK)
+
+#define LF_TIMER_STATUS3_ADDRESS                 0x00000084
+#define LF_TIMER_STATUS3_OFFSET                  0x00000084
+#define LF_TIMER_STATUS3_INTERRUPT_MSB           0
+#define LF_TIMER_STATUS3_INTERRUPT_LSB           0
+#define LF_TIMER_STATUS3_INTERRUPT_MASK          0x00000001
+#define LF_TIMER_STATUS3_INTERRUPT_GET(x)        (((x) & LF_TIMER_STATUS3_INTERRUPT_MASK) >> LF_TIMER_STATUS3_INTERRUPT_LSB)
+#define LF_TIMER_STATUS3_INTERRUPT_SET(x)        (((x) << LF_TIMER_STATUS3_INTERRUPT_LSB) & LF_TIMER_STATUS3_INTERRUPT_MASK)
+
+#define HF_TIMER_ADDRESS                         0x00000088
+#define HF_TIMER_OFFSET                          0x00000088
+#define HF_TIMER_TARGET_MSB                      31
+#define HF_TIMER_TARGET_LSB                      12
+#define HF_TIMER_TARGET_MASK                     0xfffff000
+#define HF_TIMER_TARGET_GET(x)                   (((x) & HF_TIMER_TARGET_MASK) >> HF_TIMER_TARGET_LSB)
+#define HF_TIMER_TARGET_SET(x)                   (((x) << HF_TIMER_TARGET_LSB) & HF_TIMER_TARGET_MASK)
+
+#define HF_TIMER_COUNT_ADDRESS                   0x0000008c
+#define HF_TIMER_COUNT_OFFSET                    0x0000008c
+#define HF_TIMER_COUNT_VALUE_MSB                 31
+#define HF_TIMER_COUNT_VALUE_LSB                 12
+#define HF_TIMER_COUNT_VALUE_MASK                0xfffff000
+#define HF_TIMER_COUNT_VALUE_GET(x)              (((x) & HF_TIMER_COUNT_VALUE_MASK) >> HF_TIMER_COUNT_VALUE_LSB)
+#define HF_TIMER_COUNT_VALUE_SET(x)              (((x) << HF_TIMER_COUNT_VALUE_LSB) & HF_TIMER_COUNT_VALUE_MASK)
+
+#define HF_LF_COUNT_ADDRESS                      0x00000090
+#define HF_LF_COUNT_OFFSET                       0x00000090
+#define HF_LF_COUNT_VALUE_MSB                    31
+#define HF_LF_COUNT_VALUE_LSB                    0
+#define HF_LF_COUNT_VALUE_MASK                   0xffffffff
+#define HF_LF_COUNT_VALUE_GET(x)                 (((x) & HF_LF_COUNT_VALUE_MASK) >> HF_LF_COUNT_VALUE_LSB)
+#define HF_LF_COUNT_VALUE_SET(x)                 (((x) << HF_LF_COUNT_VALUE_LSB) & HF_LF_COUNT_VALUE_MASK)
+
+#define HF_TIMER_CONTROL_ADDRESS                 0x00000094
+#define HF_TIMER_CONTROL_OFFSET                  0x00000094
+#define HF_TIMER_CONTROL_ENABLE_MSB              3
+#define HF_TIMER_CONTROL_ENABLE_LSB              3
+#define HF_TIMER_CONTROL_ENABLE_MASK             0x00000008
+#define HF_TIMER_CONTROL_ENABLE_GET(x)           (((x) & HF_TIMER_CONTROL_ENABLE_MASK) >> HF_TIMER_CONTROL_ENABLE_LSB)
+#define HF_TIMER_CONTROL_ENABLE_SET(x)           (((x) << HF_TIMER_CONTROL_ENABLE_LSB) & HF_TIMER_CONTROL_ENABLE_MASK)
+#define HF_TIMER_CONTROL_ON_MSB                  2
+#define HF_TIMER_CONTROL_ON_LSB                  2
+#define HF_TIMER_CONTROL_ON_MASK                 0x00000004
+#define HF_TIMER_CONTROL_ON_GET(x)               (((x) & HF_TIMER_CONTROL_ON_MASK) >> HF_TIMER_CONTROL_ON_LSB)
+#define HF_TIMER_CONTROL_ON_SET(x)               (((x) << HF_TIMER_CONTROL_ON_LSB) & HF_TIMER_CONTROL_ON_MASK)
+#define HF_TIMER_CONTROL_AUTO_RESTART_MSB        1
+#define HF_TIMER_CONTROL_AUTO_RESTART_LSB        1
+#define HF_TIMER_CONTROL_AUTO_RESTART_MASK       0x00000002
+#define HF_TIMER_CONTROL_AUTO_RESTART_GET(x)     (((x) & HF_TIMER_CONTROL_AUTO_RESTART_MASK) >> HF_TIMER_CONTROL_AUTO_RESTART_LSB)
+#define HF_TIMER_CONTROL_AUTO_RESTART_SET(x)     (((x) << HF_TIMER_CONTROL_AUTO_RESTART_LSB) & HF_TIMER_CONTROL_AUTO_RESTART_MASK)
+#define HF_TIMER_CONTROL_RESET_MSB               0
+#define HF_TIMER_CONTROL_RESET_LSB               0
+#define HF_TIMER_CONTROL_RESET_MASK              0x00000001
+#define HF_TIMER_CONTROL_RESET_GET(x)            (((x) & HF_TIMER_CONTROL_RESET_MASK) >> HF_TIMER_CONTROL_RESET_LSB)
+#define HF_TIMER_CONTROL_RESET_SET(x)            (((x) << HF_TIMER_CONTROL_RESET_LSB) & HF_TIMER_CONTROL_RESET_MASK)
+
+#define HF_TIMER_STATUS_ADDRESS                  0x00000098
+#define HF_TIMER_STATUS_OFFSET                   0x00000098
+#define HF_TIMER_STATUS_INTERRUPT_MSB            0
+#define HF_TIMER_STATUS_INTERRUPT_LSB            0
+#define HF_TIMER_STATUS_INTERRUPT_MASK           0x00000001
+#define HF_TIMER_STATUS_INTERRUPT_GET(x)         (((x) & HF_TIMER_STATUS_INTERRUPT_MASK) >> HF_TIMER_STATUS_INTERRUPT_LSB)
+#define HF_TIMER_STATUS_INTERRUPT_SET(x)         (((x) << HF_TIMER_STATUS_INTERRUPT_LSB) & HF_TIMER_STATUS_INTERRUPT_MASK)
+
+#define RTC_CONTROL_ADDRESS                      0x0000009c
+#define RTC_CONTROL_OFFSET                       0x0000009c
+#define RTC_CONTROL_ENABLE_MSB                   2
+#define RTC_CONTROL_ENABLE_LSB                   2
+#define RTC_CONTROL_ENABLE_MASK                  0x00000004
+#define RTC_CONTROL_ENABLE_GET(x)                (((x) & RTC_CONTROL_ENABLE_MASK) >> RTC_CONTROL_ENABLE_LSB)
+#define RTC_CONTROL_ENABLE_SET(x)                (((x) << RTC_CONTROL_ENABLE_LSB) & RTC_CONTROL_ENABLE_MASK)
+#define RTC_CONTROL_LOAD_RTC_MSB                 1
+#define RTC_CONTROL_LOAD_RTC_LSB                 1
+#define RTC_CONTROL_LOAD_RTC_MASK                0x00000002
+#define RTC_CONTROL_LOAD_RTC_GET(x)              (((x) & RTC_CONTROL_LOAD_RTC_MASK) >> RTC_CONTROL_LOAD_RTC_LSB)
+#define RTC_CONTROL_LOAD_RTC_SET(x)              (((x) << RTC_CONTROL_LOAD_RTC_LSB) & RTC_CONTROL_LOAD_RTC_MASK)
+#define RTC_CONTROL_LOAD_ALARM_MSB               0
+#define RTC_CONTROL_LOAD_ALARM_LSB               0
+#define RTC_CONTROL_LOAD_ALARM_MASK              0x00000001
+#define RTC_CONTROL_LOAD_ALARM_GET(x)            (((x) & RTC_CONTROL_LOAD_ALARM_MASK) >> RTC_CONTROL_LOAD_ALARM_LSB)
+#define RTC_CONTROL_LOAD_ALARM_SET(x)            (((x) << RTC_CONTROL_LOAD_ALARM_LSB) & RTC_CONTROL_LOAD_ALARM_MASK)
+
+#define RTC_TIME_ADDRESS                         0x000000a0
+#define RTC_TIME_OFFSET                          0x000000a0
+#define RTC_TIME_WEEK_DAY_MSB                    26
+#define RTC_TIME_WEEK_DAY_LSB                    24
+#define RTC_TIME_WEEK_DAY_MASK                   0x07000000
+#define RTC_TIME_WEEK_DAY_GET(x)                 (((x) & RTC_TIME_WEEK_DAY_MASK) >> RTC_TIME_WEEK_DAY_LSB)
+#define RTC_TIME_WEEK_DAY_SET(x)                 (((x) << RTC_TIME_WEEK_DAY_LSB) & RTC_TIME_WEEK_DAY_MASK)
+#define RTC_TIME_HOUR_MSB                        21
+#define RTC_TIME_HOUR_LSB                        16
+#define RTC_TIME_HOUR_MASK                       0x003f0000
+#define RTC_TIME_HOUR_GET(x)                     (((x) & RTC_TIME_HOUR_MASK) >> RTC_TIME_HOUR_LSB)
+#define RTC_TIME_HOUR_SET(x)                     (((x) << RTC_TIME_HOUR_LSB) & RTC_TIME_HOUR_MASK)
+#define RTC_TIME_MINUTE_MSB                      14
+#define RTC_TIME_MINUTE_LSB                      8
+#define RTC_TIME_MINUTE_MASK                     0x00007f00
+#define RTC_TIME_MINUTE_GET(x)                   (((x) & RTC_TIME_MINUTE_MASK) >> RTC_TIME_MINUTE_LSB)
+#define RTC_TIME_MINUTE_SET(x)                   (((x) << RTC_TIME_MINUTE_LSB) & RTC_TIME_MINUTE_MASK)
+#define RTC_TIME_SECOND_MSB                      6
+#define RTC_TIME_SECOND_LSB                      0
+#define RTC_TIME_SECOND_MASK                     0x0000007f
+#define RTC_TIME_SECOND_GET(x)                   (((x) & RTC_TIME_SECOND_MASK) >> RTC_TIME_SECOND_LSB)
+#define RTC_TIME_SECOND_SET(x)                   (((x) << RTC_TIME_SECOND_LSB) & RTC_TIME_SECOND_MASK)
+
+#define RTC_DATE_ADDRESS                         0x000000a4
+#define RTC_DATE_OFFSET                          0x000000a4
+#define RTC_DATE_YEAR_MSB                        23
+#define RTC_DATE_YEAR_LSB                        16
+#define RTC_DATE_YEAR_MASK                       0x00ff0000
+#define RTC_DATE_YEAR_GET(x)                     (((x) & RTC_DATE_YEAR_MASK) >> RTC_DATE_YEAR_LSB)
+#define RTC_DATE_YEAR_SET(x)                     (((x) << RTC_DATE_YEAR_LSB) & RTC_DATE_YEAR_MASK)
+#define RTC_DATE_MONTH_MSB                       12
+#define RTC_DATE_MONTH_LSB                       8
+#define RTC_DATE_MONTH_MASK                      0x00001f00
+#define RTC_DATE_MONTH_GET(x)                    (((x) & RTC_DATE_MONTH_MASK) >> RTC_DATE_MONTH_LSB)
+#define RTC_DATE_MONTH_SET(x)                    (((x) << RTC_DATE_MONTH_LSB) & RTC_DATE_MONTH_MASK)
+#define RTC_DATE_MONTH_DAY_MSB                   5
+#define RTC_DATE_MONTH_DAY_LSB                   0
+#define RTC_DATE_MONTH_DAY_MASK                  0x0000003f
+#define RTC_DATE_MONTH_DAY_GET(x)                (((x) & RTC_DATE_MONTH_DAY_MASK) >> RTC_DATE_MONTH_DAY_LSB)
+#define RTC_DATE_MONTH_DAY_SET(x)                (((x) << RTC_DATE_MONTH_DAY_LSB) & RTC_DATE_MONTH_DAY_MASK)
+
+#define RTC_SET_TIME_ADDRESS                     0x000000a8
+#define RTC_SET_TIME_OFFSET                      0x000000a8
+#define RTC_SET_TIME_WEEK_DAY_MSB                26
+#define RTC_SET_TIME_WEEK_DAY_LSB                24
+#define RTC_SET_TIME_WEEK_DAY_MASK               0x07000000
+#define RTC_SET_TIME_WEEK_DAY_GET(x)             (((x) & RTC_SET_TIME_WEEK_DAY_MASK) >> RTC_SET_TIME_WEEK_DAY_LSB)
+#define RTC_SET_TIME_WEEK_DAY_SET(x)             (((x) << RTC_SET_TIME_WEEK_DAY_LSB) & RTC_SET_TIME_WEEK_DAY_MASK)
+#define RTC_SET_TIME_HOUR_MSB                    21
+#define RTC_SET_TIME_HOUR_LSB                    16
+#define RTC_SET_TIME_HOUR_MASK                   0x003f0000
+#define RTC_SET_TIME_HOUR_GET(x)                 (((x) & RTC_SET_TIME_HOUR_MASK) >> RTC_SET_TIME_HOUR_LSB)
+#define RTC_SET_TIME_HOUR_SET(x)                 (((x) << RTC_SET_TIME_HOUR_LSB) & RTC_SET_TIME_HOUR_MASK)
+#define RTC_SET_TIME_MINUTE_MSB                  14
+#define RTC_SET_TIME_MINUTE_LSB                  8
+#define RTC_SET_TIME_MINUTE_MASK                 0x00007f00
+#define RTC_SET_TIME_MINUTE_GET(x)               (((x) & RTC_SET_TIME_MINUTE_MASK) >> RTC_SET_TIME_MINUTE_LSB)
+#define RTC_SET_TIME_MINUTE_SET(x)               (((x) << RTC_SET_TIME_MINUTE_LSB) & RTC_SET_TIME_MINUTE_MASK)
+#define RTC_SET_TIME_SECOND_MSB                  6
+#define RTC_SET_TIME_SECOND_LSB                  0
+#define RTC_SET_TIME_SECOND_MASK                 0x0000007f
+#define RTC_SET_TIME_SECOND_GET(x)               (((x) & RTC_SET_TIME_SECOND_MASK) >> RTC_SET_TIME_SECOND_LSB)
+#define RTC_SET_TIME_SECOND_SET(x)               (((x) << RTC_SET_TIME_SECOND_LSB) & RTC_SET_TIME_SECOND_MASK)
+
+#define RTC_SET_DATE_ADDRESS                     0x000000ac
+#define RTC_SET_DATE_OFFSET                      0x000000ac
+#define RTC_SET_DATE_YEAR_MSB                    23
+#define RTC_SET_DATE_YEAR_LSB                    16
+#define RTC_SET_DATE_YEAR_MASK                   0x00ff0000
+#define RTC_SET_DATE_YEAR_GET(x)                 (((x) & RTC_SET_DATE_YEAR_MASK) >> RTC_SET_DATE_YEAR_LSB)
+#define RTC_SET_DATE_YEAR_SET(x)                 (((x) << RTC_SET_DATE_YEAR_LSB) & RTC_SET_DATE_YEAR_MASK)
+#define RTC_SET_DATE_MONTH_MSB                   12
+#define RTC_SET_DATE_MONTH_LSB                   8
+#define RTC_SET_DATE_MONTH_MASK                  0x00001f00
+#define RTC_SET_DATE_MONTH_GET(x)                (((x) & RTC_SET_DATE_MONTH_MASK) >> RTC_SET_DATE_MONTH_LSB)
+#define RTC_SET_DATE_MONTH_SET(x)                (((x) << RTC_SET_DATE_MONTH_LSB) & RTC_SET_DATE_MONTH_MASK)
+#define RTC_SET_DATE_MONTH_DAY_MSB               5
+#define RTC_SET_DATE_MONTH_DAY_LSB               0
+#define RTC_SET_DATE_MONTH_DAY_MASK              0x0000003f
+#define RTC_SET_DATE_MONTH_DAY_GET(x)            (((x) & RTC_SET_DATE_MONTH_DAY_MASK) >> RTC_SET_DATE_MONTH_DAY_LSB)
+#define RTC_SET_DATE_MONTH_DAY_SET(x)            (((x) << RTC_SET_DATE_MONTH_DAY_LSB) & RTC_SET_DATE_MONTH_DAY_MASK)
+
+#define RTC_SET_ALARM_ADDRESS                    0x000000b0
+#define RTC_SET_ALARM_OFFSET                     0x000000b0
+#define RTC_SET_ALARM_HOUR_MSB                   21
+#define RTC_SET_ALARM_HOUR_LSB                   16
+#define RTC_SET_ALARM_HOUR_MASK                  0x003f0000
+#define RTC_SET_ALARM_HOUR_GET(x)                (((x) & RTC_SET_ALARM_HOUR_MASK) >> RTC_SET_ALARM_HOUR_LSB)
+#define RTC_SET_ALARM_HOUR_SET(x)                (((x) << RTC_SET_ALARM_HOUR_LSB) & RTC_SET_ALARM_HOUR_MASK)
+#define RTC_SET_ALARM_MINUTE_MSB                 14
+#define RTC_SET_ALARM_MINUTE_LSB                 8
+#define RTC_SET_ALARM_MINUTE_MASK                0x00007f00
+#define RTC_SET_ALARM_MINUTE_GET(x)              (((x) & RTC_SET_ALARM_MINUTE_MASK) >> RTC_SET_ALARM_MINUTE_LSB)
+#define RTC_SET_ALARM_MINUTE_SET(x)              (((x) << RTC_SET_ALARM_MINUTE_LSB) & RTC_SET_ALARM_MINUTE_MASK)
+#define RTC_SET_ALARM_SECOND_MSB                 6
+#define RTC_SET_ALARM_SECOND_LSB                 0
+#define RTC_SET_ALARM_SECOND_MASK                0x0000007f
+#define RTC_SET_ALARM_SECOND_GET(x)              (((x) & RTC_SET_ALARM_SECOND_MASK) >> RTC_SET_ALARM_SECOND_LSB)
+#define RTC_SET_ALARM_SECOND_SET(x)              (((x) << RTC_SET_ALARM_SECOND_LSB) & RTC_SET_ALARM_SECOND_MASK)
+
+#define RTC_CONFIG_ADDRESS                       0x000000b4
+#define RTC_CONFIG_OFFSET                        0x000000b4
+#define RTC_CONFIG_BCD_MSB                       2
+#define RTC_CONFIG_BCD_LSB                       2
+#define RTC_CONFIG_BCD_MASK                      0x00000004
+#define RTC_CONFIG_BCD_GET(x)                    (((x) & RTC_CONFIG_BCD_MASK) >> RTC_CONFIG_BCD_LSB)
+#define RTC_CONFIG_BCD_SET(x)                    (((x) << RTC_CONFIG_BCD_LSB) & RTC_CONFIG_BCD_MASK)
+#define RTC_CONFIG_TWELVE_HOUR_MSB               1
+#define RTC_CONFIG_TWELVE_HOUR_LSB               1
+#define RTC_CONFIG_TWELVE_HOUR_MASK              0x00000002
+#define RTC_CONFIG_TWELVE_HOUR_GET(x)            (((x) & RTC_CONFIG_TWELVE_HOUR_MASK) >> RTC_CONFIG_TWELVE_HOUR_LSB)
+#define RTC_CONFIG_TWELVE_HOUR_SET(x)            (((x) << RTC_CONFIG_TWELVE_HOUR_LSB) & RTC_CONFIG_TWELVE_HOUR_MASK)
+#define RTC_CONFIG_DSE_MSB                       0
+#define RTC_CONFIG_DSE_LSB                       0
+#define RTC_CONFIG_DSE_MASK                      0x00000001
+#define RTC_CONFIG_DSE_GET(x)                    (((x) & RTC_CONFIG_DSE_MASK) >> RTC_CONFIG_DSE_LSB)
+#define RTC_CONFIG_DSE_SET(x)                    (((x) << RTC_CONFIG_DSE_LSB) & RTC_CONFIG_DSE_MASK)
+
+#define RTC_ALARM_STATUS_ADDRESS                 0x000000b8
+#define RTC_ALARM_STATUS_OFFSET                  0x000000b8
+#define RTC_ALARM_STATUS_ENABLE_MSB              1
+#define RTC_ALARM_STATUS_ENABLE_LSB              1
+#define RTC_ALARM_STATUS_ENABLE_MASK             0x00000002
+#define RTC_ALARM_STATUS_ENABLE_GET(x)           (((x) & RTC_ALARM_STATUS_ENABLE_MASK) >> RTC_ALARM_STATUS_ENABLE_LSB)
+#define RTC_ALARM_STATUS_ENABLE_SET(x)           (((x) << RTC_ALARM_STATUS_ENABLE_LSB) & RTC_ALARM_STATUS_ENABLE_MASK)
+#define RTC_ALARM_STATUS_INTERRUPT_MSB           0
+#define RTC_ALARM_STATUS_INTERRUPT_LSB           0
+#define RTC_ALARM_STATUS_INTERRUPT_MASK          0x00000001
+#define RTC_ALARM_STATUS_INTERRUPT_GET(x)        (((x) & RTC_ALARM_STATUS_INTERRUPT_MASK) >> RTC_ALARM_STATUS_INTERRUPT_LSB)
+#define RTC_ALARM_STATUS_INTERRUPT_SET(x)        (((x) << RTC_ALARM_STATUS_INTERRUPT_LSB) & RTC_ALARM_STATUS_INTERRUPT_MASK)
+
+#define UART_WAKEUP_ADDRESS                      0x000000bc
+#define UART_WAKEUP_OFFSET                       0x000000bc
+#define UART_WAKEUP_ENABLE_MSB                   0
+#define UART_WAKEUP_ENABLE_LSB                   0
+#define UART_WAKEUP_ENABLE_MASK                  0x00000001
+#define UART_WAKEUP_ENABLE_GET(x)                (((x) & UART_WAKEUP_ENABLE_MASK) >> UART_WAKEUP_ENABLE_LSB)
+#define UART_WAKEUP_ENABLE_SET(x)                (((x) << UART_WAKEUP_ENABLE_LSB) & UART_WAKEUP_ENABLE_MASK)
+
+#define RESET_CAUSE_ADDRESS                      0x000000c0
+#define RESET_CAUSE_OFFSET                       0x000000c0
+#define RESET_CAUSE_LAST_MSB                     2
+#define RESET_CAUSE_LAST_LSB                     0
+#define RESET_CAUSE_LAST_MASK                    0x00000007
+#define RESET_CAUSE_LAST_GET(x)                  (((x) & RESET_CAUSE_LAST_MASK) >> RESET_CAUSE_LAST_LSB)
+#define RESET_CAUSE_LAST_SET(x)                  (((x) << RESET_CAUSE_LAST_LSB) & RESET_CAUSE_LAST_MASK)
+
+#define SYSTEM_SLEEP_ADDRESS                     0x000000c4
+#define SYSTEM_SLEEP_OFFSET                      0x000000c4
+#define SYSTEM_SLEEP_HOST_IF_MSB                 4
+#define SYSTEM_SLEEP_HOST_IF_LSB                 4
+#define SYSTEM_SLEEP_HOST_IF_MASK                0x00000010
+#define SYSTEM_SLEEP_HOST_IF_GET(x)              (((x) & SYSTEM_SLEEP_HOST_IF_MASK) >> SYSTEM_SLEEP_HOST_IF_LSB)
+#define SYSTEM_SLEEP_HOST_IF_SET(x)              (((x) << SYSTEM_SLEEP_HOST_IF_LSB) & SYSTEM_SLEEP_HOST_IF_MASK)
+#define SYSTEM_SLEEP_MBOX_MSB                    3
+#define SYSTEM_SLEEP_MBOX_LSB                    3
+#define SYSTEM_SLEEP_MBOX_MASK                   0x00000008
+#define SYSTEM_SLEEP_MBOX_GET(x)                 (((x) & SYSTEM_SLEEP_MBOX_MASK) >> SYSTEM_SLEEP_MBOX_LSB)
+#define SYSTEM_SLEEP_MBOX_SET(x)                 (((x) << SYSTEM_SLEEP_MBOX_LSB) & SYSTEM_SLEEP_MBOX_MASK)
+#define SYSTEM_SLEEP_MAC_IF_MSB                  2
+#define SYSTEM_SLEEP_MAC_IF_LSB                  2
+#define SYSTEM_SLEEP_MAC_IF_MASK                 0x00000004
+#define SYSTEM_SLEEP_MAC_IF_GET(x)               (((x) & SYSTEM_SLEEP_MAC_IF_MASK) >> SYSTEM_SLEEP_MAC_IF_LSB)
+#define SYSTEM_SLEEP_MAC_IF_SET(x)               (((x) << SYSTEM_SLEEP_MAC_IF_LSB) & SYSTEM_SLEEP_MAC_IF_MASK)
+#define SYSTEM_SLEEP_LIGHT_MSB                   1
+#define SYSTEM_SLEEP_LIGHT_LSB                   1
+#define SYSTEM_SLEEP_LIGHT_MASK                  0x00000002
+#define SYSTEM_SLEEP_LIGHT_GET(x)                (((x) & SYSTEM_SLEEP_LIGHT_MASK) >> SYSTEM_SLEEP_LIGHT_LSB)
+#define SYSTEM_SLEEP_LIGHT_SET(x)                (((x) << SYSTEM_SLEEP_LIGHT_LSB) & SYSTEM_SLEEP_LIGHT_MASK)
+#define SYSTEM_SLEEP_DISABLE_MSB                 0
+#define SYSTEM_SLEEP_DISABLE_LSB                 0
+#define SYSTEM_SLEEP_DISABLE_MASK                0x00000001
+#define SYSTEM_SLEEP_DISABLE_GET(x)              (((x) & SYSTEM_SLEEP_DISABLE_MASK) >> SYSTEM_SLEEP_DISABLE_LSB)
+#define SYSTEM_SLEEP_DISABLE_SET(x)              (((x) << SYSTEM_SLEEP_DISABLE_LSB) & SYSTEM_SLEEP_DISABLE_MASK)
+
+#define SDIO_WRAPPER_ADDRESS                     0x000000c8
+#define SDIO_WRAPPER_OFFSET                      0x000000c8
+#define SDIO_WRAPPER_SLEEP_MSB                   3
+#define SDIO_WRAPPER_SLEEP_LSB                   3
+#define SDIO_WRAPPER_SLEEP_MASK                  0x00000008
+#define SDIO_WRAPPER_SLEEP_GET(x)                (((x) & SDIO_WRAPPER_SLEEP_MASK) >> SDIO_WRAPPER_SLEEP_LSB)
+#define SDIO_WRAPPER_SLEEP_SET(x)                (((x) << SDIO_WRAPPER_SLEEP_LSB) & SDIO_WRAPPER_SLEEP_MASK)
+#define SDIO_WRAPPER_WAKEUP_MSB                  2
+#define SDIO_WRAPPER_WAKEUP_LSB                  2
+#define SDIO_WRAPPER_WAKEUP_MASK                 0x00000004
+#define SDIO_WRAPPER_WAKEUP_GET(x)               (((x) & SDIO_WRAPPER_WAKEUP_MASK) >> SDIO_WRAPPER_WAKEUP_LSB)
+#define SDIO_WRAPPER_WAKEUP_SET(x)               (((x) << SDIO_WRAPPER_WAKEUP_LSB) & SDIO_WRAPPER_WAKEUP_MASK)
+#define SDIO_WRAPPER_SOC_ON_MSB                  1
+#define SDIO_WRAPPER_SOC_ON_LSB                  1
+#define SDIO_WRAPPER_SOC_ON_MASK                 0x00000002
+#define SDIO_WRAPPER_SOC_ON_GET(x)               (((x) & SDIO_WRAPPER_SOC_ON_MASK) >> SDIO_WRAPPER_SOC_ON_LSB)
+#define SDIO_WRAPPER_SOC_ON_SET(x)               (((x) << SDIO_WRAPPER_SOC_ON_LSB) & SDIO_WRAPPER_SOC_ON_MASK)
+#define SDIO_WRAPPER_ON_MSB                      0
+#define SDIO_WRAPPER_ON_LSB                      0
+#define SDIO_WRAPPER_ON_MASK                     0x00000001
+#define SDIO_WRAPPER_ON_GET(x)                   (((x) & SDIO_WRAPPER_ON_MASK) >> SDIO_WRAPPER_ON_LSB)
+#define SDIO_WRAPPER_ON_SET(x)                   (((x) << SDIO_WRAPPER_ON_LSB) & SDIO_WRAPPER_ON_MASK)
+
+#define MAC_SLEEP_CONTROL_ADDRESS                0x000000cc
+#define MAC_SLEEP_CONTROL_OFFSET                 0x000000cc
+#define MAC_SLEEP_CONTROL_ENABLE_MSB             1
+#define MAC_SLEEP_CONTROL_ENABLE_LSB             0
+#define MAC_SLEEP_CONTROL_ENABLE_MASK            0x00000003
+#define MAC_SLEEP_CONTROL_ENABLE_GET(x)          (((x) & MAC_SLEEP_CONTROL_ENABLE_MASK) >> MAC_SLEEP_CONTROL_ENABLE_LSB)
+#define MAC_SLEEP_CONTROL_ENABLE_SET(x)          (((x) << MAC_SLEEP_CONTROL_ENABLE_LSB) & MAC_SLEEP_CONTROL_ENABLE_MASK)
+
+#define KEEP_AWAKE_ADDRESS                       0x000000d0
+#define KEEP_AWAKE_OFFSET                        0x000000d0
+#define KEEP_AWAKE_COUNT_MSB                     7
+#define KEEP_AWAKE_COUNT_LSB                     0
+#define KEEP_AWAKE_COUNT_MASK                    0x000000ff
+#define KEEP_AWAKE_COUNT_GET(x)                  (((x) & KEEP_AWAKE_COUNT_MASK) >> KEEP_AWAKE_COUNT_LSB)
+#define KEEP_AWAKE_COUNT_SET(x)                  (((x) << KEEP_AWAKE_COUNT_LSB) & KEEP_AWAKE_COUNT_MASK)
+
+#define LPO_CAL_TIME_ADDRESS                     0x000000d4
+#define LPO_CAL_TIME_OFFSET                      0x000000d4
+#define LPO_CAL_TIME_LENGTH_MSB                  13
+#define LPO_CAL_TIME_LENGTH_LSB                  0
+#define LPO_CAL_TIME_LENGTH_MASK                 0x00003fff
+#define LPO_CAL_TIME_LENGTH_GET(x)               (((x) & LPO_CAL_TIME_LENGTH_MASK) >> LPO_CAL_TIME_LENGTH_LSB)
+#define LPO_CAL_TIME_LENGTH_SET(x)               (((x) << LPO_CAL_TIME_LENGTH_LSB) & LPO_CAL_TIME_LENGTH_MASK)
+
+#define LPO_INIT_DIVIDEND_INT_ADDRESS            0x000000d8
+#define LPO_INIT_DIVIDEND_INT_OFFSET             0x000000d8
+#define LPO_INIT_DIVIDEND_INT_VALUE_MSB          23
+#define LPO_INIT_DIVIDEND_INT_VALUE_LSB          0
+#define LPO_INIT_DIVIDEND_INT_VALUE_MASK         0x00ffffff
+#define LPO_INIT_DIVIDEND_INT_VALUE_GET(x)       (((x) & LPO_INIT_DIVIDEND_INT_VALUE_MASK) >> LPO_INIT_DIVIDEND_INT_VALUE_LSB)
+#define LPO_INIT_DIVIDEND_INT_VALUE_SET(x)       (((x) << LPO_INIT_DIVIDEND_INT_VALUE_LSB) & LPO_INIT_DIVIDEND_INT_VALUE_MASK)
+
+#define LPO_INIT_DIVIDEND_FRACTION_ADDRESS       0x000000dc
+#define LPO_INIT_DIVIDEND_FRACTION_OFFSET        0x000000dc
+#define LPO_INIT_DIVIDEND_FRACTION_VALUE_MSB     10
+#define LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB     0
+#define LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK    0x000007ff
+#define LPO_INIT_DIVIDEND_FRACTION_VALUE_GET(x)  (((x) & LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK) >> LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB)
+#define LPO_INIT_DIVIDEND_FRACTION_VALUE_SET(x)  (((x) << LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB) & LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK)
+
+#define LPO_CAL_ADDRESS                          0x000000e0
+#define LPO_CAL_OFFSET                           0x000000e0
+#define LPO_CAL_ENABLE_MSB                       20
+#define LPO_CAL_ENABLE_LSB                       20
+#define LPO_CAL_ENABLE_MASK                      0x00100000
+#define LPO_CAL_ENABLE_GET(x)                    (((x) & LPO_CAL_ENABLE_MASK) >> LPO_CAL_ENABLE_LSB)
+#define LPO_CAL_ENABLE_SET(x)                    (((x) << LPO_CAL_ENABLE_LSB) & LPO_CAL_ENABLE_MASK)
+#define LPO_CAL_COUNT_MSB                        19
+#define LPO_CAL_COUNT_LSB                        0
+#define LPO_CAL_COUNT_MASK                       0x000fffff
+#define LPO_CAL_COUNT_GET(x)                     (((x) & LPO_CAL_COUNT_MASK) >> LPO_CAL_COUNT_LSB)
+#define LPO_CAL_COUNT_SET(x)                     (((x) << LPO_CAL_COUNT_LSB) & LPO_CAL_COUNT_MASK)
+
+#define LPO_CAL_TEST_CONTROL_ADDRESS             0x000000e4
+#define LPO_CAL_TEST_CONTROL_OFFSET              0x000000e4
+#define LPO_CAL_TEST_CONTROL_ENABLE_MSB          5
+#define LPO_CAL_TEST_CONTROL_ENABLE_LSB          5
+#define LPO_CAL_TEST_CONTROL_ENABLE_MASK         0x00000020
+#define LPO_CAL_TEST_CONTROL_ENABLE_GET(x)       (((x) & LPO_CAL_TEST_CONTROL_ENABLE_MASK) >> LPO_CAL_TEST_CONTROL_ENABLE_LSB)
+#define LPO_CAL_TEST_CONTROL_ENABLE_SET(x)       (((x) << LPO_CAL_TEST_CONTROL_ENABLE_LSB) & LPO_CAL_TEST_CONTROL_ENABLE_MASK)
+#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_MSB      4
+#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB      0
+#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK     0x0000001f
+#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_GET(x)   (((x) & LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK) >> LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB)
+#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_SET(x)   (((x) << LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB) & LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK)
+
+#define LPO_CAL_TEST_STATUS_ADDRESS              0x000000e8
+#define LPO_CAL_TEST_STATUS_OFFSET               0x000000e8
+#define LPO_CAL_TEST_STATUS_READY_MSB            16
+#define LPO_CAL_TEST_STATUS_READY_LSB            16
+#define LPO_CAL_TEST_STATUS_READY_MASK           0x00010000
+#define LPO_CAL_TEST_STATUS_READY_GET(x)         (((x) & LPO_CAL_TEST_STATUS_READY_MASK) >> LPO_CAL_TEST_STATUS_READY_LSB)
+#define LPO_CAL_TEST_STATUS_READY_SET(x)         (((x) << LPO_CAL_TEST_STATUS_READY_LSB) & LPO_CAL_TEST_STATUS_READY_MASK)
+#define LPO_CAL_TEST_STATUS_COUNT_MSB            15
+#define LPO_CAL_TEST_STATUS_COUNT_LSB            0
+#define LPO_CAL_TEST_STATUS_COUNT_MASK           0x0000ffff
+#define LPO_CAL_TEST_STATUS_COUNT_GET(x)         (((x) & LPO_CAL_TEST_STATUS_COUNT_MASK) >> LPO_CAL_TEST_STATUS_COUNT_LSB)
+#define LPO_CAL_TEST_STATUS_COUNT_SET(x)         (((x) << LPO_CAL_TEST_STATUS_COUNT_LSB) & LPO_CAL_TEST_STATUS_COUNT_MASK)
+
+#define CHIP_ID_ADDRESS                          0x000000ec
+#define CHIP_ID_OFFSET                           0x000000ec
+#define CHIP_ID_DEVICE_ID_MSB                    31
+#define CHIP_ID_DEVICE_ID_LSB                    16
+#define CHIP_ID_DEVICE_ID_MASK                   0xffff0000
+#define CHIP_ID_DEVICE_ID_GET(x)                 (((x) & CHIP_ID_DEVICE_ID_MASK) >> CHIP_ID_DEVICE_ID_LSB)
+#define CHIP_ID_DEVICE_ID_SET(x)                 (((x) << CHIP_ID_DEVICE_ID_LSB) & CHIP_ID_DEVICE_ID_MASK)
+#define CHIP_ID_CONFIG_ID_MSB                    15
+#define CHIP_ID_CONFIG_ID_LSB                    4
+#define CHIP_ID_CONFIG_ID_MASK                   0x0000fff0
+#define CHIP_ID_CONFIG_ID_GET(x)                 (((x) & CHIP_ID_CONFIG_ID_MASK) >> CHIP_ID_CONFIG_ID_LSB)
+#define CHIP_ID_CONFIG_ID_SET(x)                 (((x) << CHIP_ID_CONFIG_ID_LSB) & CHIP_ID_CONFIG_ID_MASK)
+#define CHIP_ID_VERSION_ID_MSB                   3
+#define CHIP_ID_VERSION_ID_LSB                   0
+#define CHIP_ID_VERSION_ID_MASK                  0x0000000f
+#define CHIP_ID_VERSION_ID_GET(x)                (((x) & CHIP_ID_VERSION_ID_MASK) >> CHIP_ID_VERSION_ID_LSB)
+#define CHIP_ID_VERSION_ID_SET(x)                (((x) << CHIP_ID_VERSION_ID_LSB) & CHIP_ID_VERSION_ID_MASK)
+
+#define DERIVED_RTC_CLK_ADDRESS                  0x000000f0
+#define DERIVED_RTC_CLK_OFFSET                   0x000000f0
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MSB   20
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB   20
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK  0x00100000
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_GET(x) (((x) & DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK) >> DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB)
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_SET(x) (((x) << DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB) & DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK)
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_MSB      18
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB      18
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK     0x00040000
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_GET(x)   (((x) & DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK) >> DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB)
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_SET(x)   (((x) << DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB) & DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK)
+#define DERIVED_RTC_CLK_FORCE_MSB                17
+#define DERIVED_RTC_CLK_FORCE_LSB                16
+#define DERIVED_RTC_CLK_FORCE_MASK               0x00030000
+#define DERIVED_RTC_CLK_FORCE_GET(x)             (((x) & DERIVED_RTC_CLK_FORCE_MASK) >> DERIVED_RTC_CLK_FORCE_LSB)
+#define DERIVED_RTC_CLK_FORCE_SET(x)             (((x) << DERIVED_RTC_CLK_FORCE_LSB) & DERIVED_RTC_CLK_FORCE_MASK)
+#define DERIVED_RTC_CLK_PERIOD_MSB               15
+#define DERIVED_RTC_CLK_PERIOD_LSB               1
+#define DERIVED_RTC_CLK_PERIOD_MASK              0x0000fffe
+#define DERIVED_RTC_CLK_PERIOD_GET(x)            (((x) & DERIVED_RTC_CLK_PERIOD_MASK) >> DERIVED_RTC_CLK_PERIOD_LSB)
+#define DERIVED_RTC_CLK_PERIOD_SET(x)            (((x) << DERIVED_RTC_CLK_PERIOD_LSB) & DERIVED_RTC_CLK_PERIOD_MASK)
+
+#define MAC_PCU_SLP32_MODE_ADDRESS               0x000000f4
+#define MAC_PCU_SLP32_MODE_OFFSET                0x000000f4
+#define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_MSB 21
+#define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_LSB 21
+#define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_MASK 0x00200000
+#define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_GET(x) (((x) & MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_MASK) >> MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_LSB)
+#define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_SET(x) (((x) << MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_LSB) & MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_MASK)
+#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MSB  19
+#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_LSB  0
+#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MASK 0x000fffff
+#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_GET(x) (((x) & MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MASK) >> MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_LSB)
+#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_SET(x) (((x) << MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_LSB) & MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MASK)
+
+#define MAC_PCU_SLP32_WAKE_ADDRESS               0x000000f8
+#define MAC_PCU_SLP32_WAKE_OFFSET                0x000000f8
+#define MAC_PCU_SLP32_WAKE_XTL_TIME_MSB          15
+#define MAC_PCU_SLP32_WAKE_XTL_TIME_LSB          0
+#define MAC_PCU_SLP32_WAKE_XTL_TIME_MASK         0x0000ffff
+#define MAC_PCU_SLP32_WAKE_XTL_TIME_GET(x)       (((x) & MAC_PCU_SLP32_WAKE_XTL_TIME_MASK) >> MAC_PCU_SLP32_WAKE_XTL_TIME_LSB)
+#define MAC_PCU_SLP32_WAKE_XTL_TIME_SET(x)       (((x) << MAC_PCU_SLP32_WAKE_XTL_TIME_LSB) & MAC_PCU_SLP32_WAKE_XTL_TIME_MASK)
+
+#define MAC_PCU_SLP32_INC_ADDRESS                0x000000fc
+#define MAC_PCU_SLP32_INC_OFFSET                 0x000000fc
+#define MAC_PCU_SLP32_INC_TSF_INC_MSB            19
+#define MAC_PCU_SLP32_INC_TSF_INC_LSB            0
+#define MAC_PCU_SLP32_INC_TSF_INC_MASK           0x000fffff
+#define MAC_PCU_SLP32_INC_TSF_INC_GET(x)         (((x) & MAC_PCU_SLP32_INC_TSF_INC_MASK) >> MAC_PCU_SLP32_INC_TSF_INC_LSB)
+#define MAC_PCU_SLP32_INC_TSF_INC_SET(x)         (((x) << MAC_PCU_SLP32_INC_TSF_INC_LSB) & MAC_PCU_SLP32_INC_TSF_INC_MASK)
+
+#define MAC_PCU_SLP_MIB1_ADDRESS                 0x00000100
+#define MAC_PCU_SLP_MIB1_OFFSET                  0x00000100
+#define MAC_PCU_SLP_MIB1_SLEEP_CNT_MSB           31
+#define MAC_PCU_SLP_MIB1_SLEEP_CNT_LSB           0
+#define MAC_PCU_SLP_MIB1_SLEEP_CNT_MASK          0xffffffff
+#define MAC_PCU_SLP_MIB1_SLEEP_CNT_GET(x)        (((x) & MAC_PCU_SLP_MIB1_SLEEP_CNT_MASK) >> MAC_PCU_SLP_MIB1_SLEEP_CNT_LSB)
+#define MAC_PCU_SLP_MIB1_SLEEP_CNT_SET(x)        (((x) << MAC_PCU_SLP_MIB1_SLEEP_CNT_LSB) & MAC_PCU_SLP_MIB1_SLEEP_CNT_MASK)
+
+#define MAC_PCU_SLP_MIB2_ADDRESS                 0x00000104
+#define MAC_PCU_SLP_MIB2_OFFSET                  0x00000104
+#define MAC_PCU_SLP_MIB2_CYCLE_CNT_MSB           31
+#define MAC_PCU_SLP_MIB2_CYCLE_CNT_LSB           0
+#define MAC_PCU_SLP_MIB2_CYCLE_CNT_MASK          0xffffffff
+#define MAC_PCU_SLP_MIB2_CYCLE_CNT_GET(x)        (((x) & MAC_PCU_SLP_MIB2_CYCLE_CNT_MASK) >> MAC_PCU_SLP_MIB2_CYCLE_CNT_LSB)
+#define MAC_PCU_SLP_MIB2_CYCLE_CNT_SET(x)        (((x) << MAC_PCU_SLP_MIB2_CYCLE_CNT_LSB) & MAC_PCU_SLP_MIB2_CYCLE_CNT_MASK)
+
+#define MAC_PCU_SLP_MIB3_ADDRESS                 0x00000108
+#define MAC_PCU_SLP_MIB3_OFFSET                  0x00000108
+#define MAC_PCU_SLP_MIB3_PENDING_MSB             1
+#define MAC_PCU_SLP_MIB3_PENDING_LSB             1
+#define MAC_PCU_SLP_MIB3_PENDING_MASK            0x00000002
+#define MAC_PCU_SLP_MIB3_PENDING_GET(x)          (((x) & MAC_PCU_SLP_MIB3_PENDING_MASK) >> MAC_PCU_SLP_MIB3_PENDING_LSB)
+#define MAC_PCU_SLP_MIB3_PENDING_SET(x)          (((x) << MAC_PCU_SLP_MIB3_PENDING_LSB) & MAC_PCU_SLP_MIB3_PENDING_MASK)
+#define MAC_PCU_SLP_MIB3_CLR_CNT_MSB             0
+#define MAC_PCU_SLP_MIB3_CLR_CNT_LSB             0
+#define MAC_PCU_SLP_MIB3_CLR_CNT_MASK            0x00000001
+#define MAC_PCU_SLP_MIB3_CLR_CNT_GET(x)          (((x) & MAC_PCU_SLP_MIB3_CLR_CNT_MASK) >> MAC_PCU_SLP_MIB3_CLR_CNT_LSB)
+#define MAC_PCU_SLP_MIB3_CLR_CNT_SET(x)          (((x) << MAC_PCU_SLP_MIB3_CLR_CNT_LSB) & MAC_PCU_SLP_MIB3_CLR_CNT_MASK)
+
+#define MAC_PCU_SLP_BEACON_ADDRESS               0x0000010c
+#define MAC_PCU_SLP_BEACON_OFFSET                0x0000010c
+#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_MSB 24
+#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_LSB 24
+#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_MASK 0x01000000
+#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_GET(x) (((x) & MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_MASK) >> MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_LSB)
+#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_SET(x) (((x) << MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_LSB) & MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_MASK)
+#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_MSB     23
+#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_LSB     0
+#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_MASK    0x00ffffff
+#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_GET(x)  (((x) & MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_MASK) >> MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_LSB)
+#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_SET(x)  (((x) << MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_LSB) & MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_MASK)
+
+#define POWER_REG_ADDRESS                        0x00000110
+#define POWER_REG_OFFSET                         0x00000110
+#define POWER_REG_VLVL_MSB                       11
+#define POWER_REG_VLVL_LSB                       8
+#define POWER_REG_VLVL_MASK                      0x00000f00
+#define POWER_REG_VLVL_GET(x)                    (((x) & POWER_REG_VLVL_MASK) >> POWER_REG_VLVL_LSB)
+#define POWER_REG_VLVL_SET(x)                    (((x) << POWER_REG_VLVL_LSB) & POWER_REG_VLVL_MASK)
+#define POWER_REG_CPU_INT_ENABLE_MSB             7
+#define POWER_REG_CPU_INT_ENABLE_LSB             7
+#define POWER_REG_CPU_INT_ENABLE_MASK            0x00000080
+#define POWER_REG_CPU_INT_ENABLE_GET(x)          (((x) & POWER_REG_CPU_INT_ENABLE_MASK) >> POWER_REG_CPU_INT_ENABLE_LSB)
+#define POWER_REG_CPU_INT_ENABLE_SET(x)          (((x) << POWER_REG_CPU_INT_ENABLE_LSB) & POWER_REG_CPU_INT_ENABLE_MASK)
+#define POWER_REG_WLAN_ISO_DIS_MSB               6
+#define POWER_REG_WLAN_ISO_DIS_LSB               6
+#define POWER_REG_WLAN_ISO_DIS_MASK              0x00000040
+#define POWER_REG_WLAN_ISO_DIS_GET(x)            (((x) & POWER_REG_WLAN_ISO_DIS_MASK) >> POWER_REG_WLAN_ISO_DIS_LSB)
+#define POWER_REG_WLAN_ISO_DIS_SET(x)            (((x) << POWER_REG_WLAN_ISO_DIS_LSB) & POWER_REG_WLAN_ISO_DIS_MASK)
+#define POWER_REG_WLAN_ISO_CNTL_MSB              5
+#define POWER_REG_WLAN_ISO_CNTL_LSB              5
+#define POWER_REG_WLAN_ISO_CNTL_MASK             0x00000020
+#define POWER_REG_WLAN_ISO_CNTL_GET(x)           (((x) & POWER_REG_WLAN_ISO_CNTL_MASK) >> POWER_REG_WLAN_ISO_CNTL_LSB)
+#define POWER_REG_WLAN_ISO_CNTL_SET(x)           (((x) << POWER_REG_WLAN_ISO_CNTL_LSB) & POWER_REG_WLAN_ISO_CNTL_MASK)
+#define POWER_REG_RADIO_PWD_EN_MSB               4
+#define POWER_REG_RADIO_PWD_EN_LSB               4
+#define POWER_REG_RADIO_PWD_EN_MASK              0x00000010
+#define POWER_REG_RADIO_PWD_EN_GET(x)            (((x) & POWER_REG_RADIO_PWD_EN_MASK) >> POWER_REG_RADIO_PWD_EN_LSB)
+#define POWER_REG_RADIO_PWD_EN_SET(x)            (((x) << POWER_REG_RADIO_PWD_EN_LSB) & POWER_REG_RADIO_PWD_EN_MASK)
+#define POWER_REG_SOC_SCALE_EN_MSB               3
+#define POWER_REG_SOC_SCALE_EN_LSB               3
+#define POWER_REG_SOC_SCALE_EN_MASK              0x00000008
+#define POWER_REG_SOC_SCALE_EN_GET(x)            (((x) & POWER_REG_SOC_SCALE_EN_MASK) >> POWER_REG_SOC_SCALE_EN_LSB)
+#define POWER_REG_SOC_SCALE_EN_SET(x)            (((x) << POWER_REG_SOC_SCALE_EN_LSB) & POWER_REG_SOC_SCALE_EN_MASK)
+#define POWER_REG_WLAN_SCALE_EN_MSB              2
+#define POWER_REG_WLAN_SCALE_EN_LSB              2
+#define POWER_REG_WLAN_SCALE_EN_MASK             0x00000004
+#define POWER_REG_WLAN_SCALE_EN_GET(x)           (((x) & POWER_REG_WLAN_SCALE_EN_MASK) >> POWER_REG_WLAN_SCALE_EN_LSB)
+#define POWER_REG_WLAN_SCALE_EN_SET(x)           (((x) << POWER_REG_WLAN_SCALE_EN_LSB) & POWER_REG_WLAN_SCALE_EN_MASK)
+#define POWER_REG_WLAN_PWD_EN_MSB                1
+#define POWER_REG_WLAN_PWD_EN_LSB                1
+#define POWER_REG_WLAN_PWD_EN_MASK               0x00000002
+#define POWER_REG_WLAN_PWD_EN_GET(x)             (((x) & POWER_REG_WLAN_PWD_EN_MASK) >> POWER_REG_WLAN_PWD_EN_LSB)
+#define POWER_REG_WLAN_PWD_EN_SET(x)             (((x) << POWER_REG_WLAN_PWD_EN_LSB) & POWER_REG_WLAN_PWD_EN_MASK)
+#define POWER_REG_POWER_EN_MSB                   0
+#define POWER_REG_POWER_EN_LSB                   0
+#define POWER_REG_POWER_EN_MASK                  0x00000001
+#define POWER_REG_POWER_EN_GET(x)                (((x) & POWER_REG_POWER_EN_MASK) >> POWER_REG_POWER_EN_LSB)
+#define POWER_REG_POWER_EN_SET(x)                (((x) << POWER_REG_POWER_EN_LSB) & POWER_REG_POWER_EN_MASK)
+
+#define CORE_CLK_CTRL_ADDRESS                    0x00000114
+#define CORE_CLK_CTRL_OFFSET                     0x00000114
+#define CORE_CLK_CTRL_DIV_MSB                    2
+#define CORE_CLK_CTRL_DIV_LSB                    0
+#define CORE_CLK_CTRL_DIV_MASK                   0x00000007
+#define CORE_CLK_CTRL_DIV_GET(x)                 (((x) & CORE_CLK_CTRL_DIV_MASK) >> CORE_CLK_CTRL_DIV_LSB)
+#define CORE_CLK_CTRL_DIV_SET(x)                 (((x) << CORE_CLK_CTRL_DIV_LSB) & CORE_CLK_CTRL_DIV_MASK)
+
+#define SDIO_SETUP_CIRCUIT_ADDRESS               0x00000120
+#define SDIO_SETUP_CIRCUIT_OFFSET                0x00000120
+#define SDIO_SETUP_CIRCUIT_VECTOR_MSB            7
+#define SDIO_SETUP_CIRCUIT_VECTOR_LSB            0
+#define SDIO_SETUP_CIRCUIT_VECTOR_MASK           0x000000ff
+#define SDIO_SETUP_CIRCUIT_VECTOR_GET(x)         (((x) & SDIO_SETUP_CIRCUIT_VECTOR_MASK) >> SDIO_SETUP_CIRCUIT_VECTOR_LSB)
+#define SDIO_SETUP_CIRCUIT_VECTOR_SET(x)         (((x) << SDIO_SETUP_CIRCUIT_VECTOR_LSB) & SDIO_SETUP_CIRCUIT_VECTOR_MASK)
+
+#define SDIO_SETUP_CONFIG_ADDRESS                0x00000140
+#define SDIO_SETUP_CONFIG_OFFSET                 0x00000140
+#define SDIO_SETUP_CONFIG_ENABLE_MSB             1
+#define SDIO_SETUP_CONFIG_ENABLE_LSB             1
+#define SDIO_SETUP_CONFIG_ENABLE_MASK            0x00000002
+#define SDIO_SETUP_CONFIG_ENABLE_GET(x)          (((x) & SDIO_SETUP_CONFIG_ENABLE_MASK) >> SDIO_SETUP_CONFIG_ENABLE_LSB)
+#define SDIO_SETUP_CONFIG_ENABLE_SET(x)          (((x) << SDIO_SETUP_CONFIG_ENABLE_LSB) & SDIO_SETUP_CONFIG_ENABLE_MASK)
+#define SDIO_SETUP_CONFIG_CLEAR_MSB              0
+#define SDIO_SETUP_CONFIG_CLEAR_LSB              0
+#define SDIO_SETUP_CONFIG_CLEAR_MASK             0x00000001
+#define SDIO_SETUP_CONFIG_CLEAR_GET(x)           (((x) & SDIO_SETUP_CONFIG_CLEAR_MASK) >> SDIO_SETUP_CONFIG_CLEAR_LSB)
+#define SDIO_SETUP_CONFIG_CLEAR_SET(x)           (((x) << SDIO_SETUP_CONFIG_CLEAR_LSB) & SDIO_SETUP_CONFIG_CLEAR_MASK)
+
+#define CPU_SETUP_CONFIG_ADDRESS                 0x00000144
+#define CPU_SETUP_CONFIG_OFFSET                  0x00000144
+#define CPU_SETUP_CONFIG_ENABLE_MSB              1
+#define CPU_SETUP_CONFIG_ENABLE_LSB              1
+#define CPU_SETUP_CONFIG_ENABLE_MASK             0x00000002
+#define CPU_SETUP_CONFIG_ENABLE_GET(x)           (((x) & CPU_SETUP_CONFIG_ENABLE_MASK) >> CPU_SETUP_CONFIG_ENABLE_LSB)
+#define CPU_SETUP_CONFIG_ENABLE_SET(x)           (((x) << CPU_SETUP_CONFIG_ENABLE_LSB) & CPU_SETUP_CONFIG_ENABLE_MASK)
+#define CPU_SETUP_CONFIG_CLEAR_MSB               0
+#define CPU_SETUP_CONFIG_CLEAR_LSB               0
+#define CPU_SETUP_CONFIG_CLEAR_MASK              0x00000001
+#define CPU_SETUP_CONFIG_CLEAR_GET(x)            (((x) & CPU_SETUP_CONFIG_CLEAR_MASK) >> CPU_SETUP_CONFIG_CLEAR_LSB)
+#define CPU_SETUP_CONFIG_CLEAR_SET(x)            (((x) << CPU_SETUP_CONFIG_CLEAR_LSB) & CPU_SETUP_CONFIG_CLEAR_MASK)
+
+#define CPU_SETUP_CIRCUIT_ADDRESS                0x00000160
+#define CPU_SETUP_CIRCUIT_OFFSET                 0x00000160
+#define CPU_SETUP_CIRCUIT_VECTOR_MSB             7
+#define CPU_SETUP_CIRCUIT_VECTOR_LSB             0
+#define CPU_SETUP_CIRCUIT_VECTOR_MASK            0x000000ff
+#define CPU_SETUP_CIRCUIT_VECTOR_GET(x)          (((x) & CPU_SETUP_CIRCUIT_VECTOR_MASK) >> CPU_SETUP_CIRCUIT_VECTOR_LSB)
+#define CPU_SETUP_CIRCUIT_VECTOR_SET(x)          (((x) << CPU_SETUP_CIRCUIT_VECTOR_LSB) & CPU_SETUP_CIRCUIT_VECTOR_MASK)
+
+#define BB_SETUP_CONFIG_ADDRESS                  0x00000180
+#define BB_SETUP_CONFIG_OFFSET                   0x00000180
+#define BB_SETUP_CONFIG_ENABLE_MSB               1
+#define BB_SETUP_CONFIG_ENABLE_LSB               1
+#define BB_SETUP_CONFIG_ENABLE_MASK              0x00000002
+#define BB_SETUP_CONFIG_ENABLE_GET(x)            (((x) & BB_SETUP_CONFIG_ENABLE_MASK) >> BB_SETUP_CONFIG_ENABLE_LSB)
+#define BB_SETUP_CONFIG_ENABLE_SET(x)            (((x) << BB_SETUP_CONFIG_ENABLE_LSB) & BB_SETUP_CONFIG_ENABLE_MASK)
+#define BB_SETUP_CONFIG_CLEAR_MSB                0
+#define BB_SETUP_CONFIG_CLEAR_LSB                0
+#define BB_SETUP_CONFIG_CLEAR_MASK               0x00000001
+#define BB_SETUP_CONFIG_CLEAR_GET(x)             (((x) & BB_SETUP_CONFIG_CLEAR_MASK) >> BB_SETUP_CONFIG_CLEAR_LSB)
+#define BB_SETUP_CONFIG_CLEAR_SET(x)             (((x) << BB_SETUP_CONFIG_CLEAR_LSB) & BB_SETUP_CONFIG_CLEAR_MASK)
+
+#define BB_SETUP_CIRCUIT_ADDRESS                 0x000001a0
+#define BB_SETUP_CIRCUIT_OFFSET                  0x000001a0
+#define BB_SETUP_CIRCUIT_VECTOR_MSB              7
+#define BB_SETUP_CIRCUIT_VECTOR_LSB              0
+#define BB_SETUP_CIRCUIT_VECTOR_MASK             0x000000ff
+#define BB_SETUP_CIRCUIT_VECTOR_GET(x)           (((x) & BB_SETUP_CIRCUIT_VECTOR_MASK) >> BB_SETUP_CIRCUIT_VECTOR_LSB)
+#define BB_SETUP_CIRCUIT_VECTOR_SET(x)           (((x) << BB_SETUP_CIRCUIT_VECTOR_LSB) & BB_SETUP_CIRCUIT_VECTOR_MASK)
+
+#define GPIO_WAKEUP_CONTROL_ADDRESS              0x000001c0
+#define GPIO_WAKEUP_CONTROL_OFFSET               0x000001c0
+#define GPIO_WAKEUP_CONTROL_ENABLE_MSB           0
+#define GPIO_WAKEUP_CONTROL_ENABLE_LSB           0
+#define GPIO_WAKEUP_CONTROL_ENABLE_MASK          0x00000001
+#define GPIO_WAKEUP_CONTROL_ENABLE_GET(x)        (((x) & GPIO_WAKEUP_CONTROL_ENABLE_MASK) >> GPIO_WAKEUP_CONTROL_ENABLE_LSB)
+#define GPIO_WAKEUP_CONTROL_ENABLE_SET(x)        (((x) << GPIO_WAKEUP_CONTROL_ENABLE_LSB) & GPIO_WAKEUP_CONTROL_ENABLE_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct rtc_reg_reg_s {
+  volatile unsigned int reset_control;
+  volatile unsigned int xtal_control;
+  volatile unsigned int tcxo_detect;
+  volatile unsigned int xtal_test;
+  volatile unsigned int quadrature;
+  volatile unsigned int pll_control;
+  volatile unsigned int pll_settle;
+  volatile unsigned int xtal_settle;
+  volatile unsigned int cpu_clock;
+  volatile unsigned int clock_out;
+  volatile unsigned int clock_control;
+  volatile unsigned int bias_override;
+  volatile unsigned int wdt_control;
+  volatile unsigned int wdt_status;
+  volatile unsigned int wdt;
+  volatile unsigned int wdt_count;
+  volatile unsigned int wdt_reset;
+  volatile unsigned int int_status;
+  volatile unsigned int lf_timer0;
+  volatile unsigned int lf_timer_count0;
+  volatile unsigned int lf_timer_control0;
+  volatile unsigned int lf_timer_status0;
+  volatile unsigned int lf_timer1;
+  volatile unsigned int lf_timer_count1;
+  volatile unsigned int lf_timer_control1;
+  volatile unsigned int lf_timer_status1;
+  volatile unsigned int lf_timer2;
+  volatile unsigned int lf_timer_count2;
+  volatile unsigned int lf_timer_control2;
+  volatile unsigned int lf_timer_status2;
+  volatile unsigned int lf_timer3;
+  volatile unsigned int lf_timer_count3;
+  volatile unsigned int lf_timer_control3;
+  volatile unsigned int lf_timer_status3;
+  volatile unsigned int hf_timer;
+  volatile unsigned int hf_timer_count;
+  volatile unsigned int hf_lf_count;
+  volatile unsigned int hf_timer_control;
+  volatile unsigned int hf_timer_status;
+  volatile unsigned int rtc_control;
+  volatile unsigned int rtc_time;
+  volatile unsigned int rtc_date;
+  volatile unsigned int rtc_set_time;
+  volatile unsigned int rtc_set_date;
+  volatile unsigned int rtc_set_alarm;
+  volatile unsigned int rtc_config;
+  volatile unsigned int rtc_alarm_status;
+  volatile unsigned int uart_wakeup;
+  volatile unsigned int reset_cause;
+  volatile unsigned int system_sleep;
+  volatile unsigned int sdio_wrapper;
+  volatile unsigned int mac_sleep_control;
+  volatile unsigned int keep_awake;
+  volatile unsigned int lpo_cal_time;
+  volatile unsigned int lpo_init_dividend_int;
+  volatile unsigned int lpo_init_dividend_fraction;
+  volatile unsigned int lpo_cal;
+  volatile unsigned int lpo_cal_test_control;
+  volatile unsigned int lpo_cal_test_status;
+  volatile unsigned int chip_id;
+  volatile unsigned int derived_rtc_clk;
+  volatile unsigned int mac_pcu_slp32_mode;
+  volatile unsigned int mac_pcu_slp32_wake;
+  volatile unsigned int mac_pcu_slp32_inc;
+  volatile unsigned int mac_pcu_slp_mib1;
+  volatile unsigned int mac_pcu_slp_mib2;
+  volatile unsigned int mac_pcu_slp_mib3;
+  volatile unsigned int mac_pcu_slp_beacon;
+  volatile unsigned int power_reg;
+  volatile unsigned int core_clk_ctrl;
+  unsigned char pad0[8]; /* pad to 0x120 */
+  volatile unsigned int sdio_setup_circuit[8];
+  volatile unsigned int sdio_setup_config;
+  volatile unsigned int cpu_setup_config;
+  unsigned char pad1[24]; /* pad to 0x160 */
+  volatile unsigned int cpu_setup_circuit[8];
+  volatile unsigned int bb_setup_config;
+  unsigned char pad2[28]; /* pad to 0x1a0 */
+  volatile unsigned int bb_setup_circuit[8];
+  volatile unsigned int gpio_wakeup_control;
+} rtc_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _RTC_REG_H_ */
diff --git a/drivers/net/ath6kl/include/common/AR6002/hw2.0/hw/si_reg.h b/drivers/net/ath6kl/include/common/AR6002/hw2.0/hw/si_reg.h
new file mode 100644
index 00000000000..16fb99cfd0b
--- /dev/null
+++ b/drivers/net/ath6kl/include/common/AR6002/hw2.0/hw/si_reg.h
@@ -0,0 +1,186 @@
+#ifndef _SI_REG_REG_H_
+#define _SI_REG_REG_H_
+
+#define SI_CONFIG_ADDRESS                        0x00000000
+#define SI_CONFIG_OFFSET                         0x00000000
+#define SI_CONFIG_ERR_INT_MSB                    19
+#define SI_CONFIG_ERR_INT_LSB                    19
+#define SI_CONFIG_ERR_INT_MASK                   0x00080000
+#define SI_CONFIG_ERR_INT_GET(x)                 (((x) & SI_CONFIG_ERR_INT_MASK) >> SI_CONFIG_ERR_INT_LSB)
+#define SI_CONFIG_ERR_INT_SET(x)                 (((x) << SI_CONFIG_ERR_INT_LSB) & SI_CONFIG_ERR_INT_MASK)
+#define SI_CONFIG_BIDIR_OD_DATA_MSB              18
+#define SI_CONFIG_BIDIR_OD_DATA_LSB              18
+#define SI_CONFIG_BIDIR_OD_DATA_MASK             0x00040000
+#define SI_CONFIG_BIDIR_OD_DATA_GET(x)           (((x) & SI_CONFIG_BIDIR_OD_DATA_MASK) >> SI_CONFIG_BIDIR_OD_DATA_LSB)
+#define SI_CONFIG_BIDIR_OD_DATA_SET(x)           (((x) << SI_CONFIG_BIDIR_OD_DATA_LSB) & SI_CONFIG_BIDIR_OD_DATA_MASK)
+#define SI_CONFIG_I2C_MSB                        16
+#define SI_CONFIG_I2C_LSB                        16
+#define SI_CONFIG_I2C_MASK                       0x00010000
+#define SI_CONFIG_I2C_GET(x)                     (((x) & SI_CONFIG_I2C_MASK) >> SI_CONFIG_I2C_LSB)
+#define SI_CONFIG_I2C_SET(x)                     (((x) << SI_CONFIG_I2C_LSB) & SI_CONFIG_I2C_MASK)
+#define SI_CONFIG_POS_SAMPLE_MSB                 7
+#define SI_CONFIG_POS_SAMPLE_LSB                 7
+#define SI_CONFIG_POS_SAMPLE_MASK                0x00000080
+#define SI_CONFIG_POS_SAMPLE_GET(x)              (((x) & SI_CONFIG_POS_SAMPLE_MASK) >> SI_CONFIG_POS_SAMPLE_LSB)
+#define SI_CONFIG_POS_SAMPLE_SET(x)              (((x) << SI_CONFIG_POS_SAMPLE_LSB) & SI_CONFIG_POS_SAMPLE_MASK)
+#define SI_CONFIG_POS_DRIVE_MSB                  6
+#define SI_CONFIG_POS_DRIVE_LSB                  6
+#define SI_CONFIG_POS_DRIVE_MASK                 0x00000040
+#define SI_CONFIG_POS_DRIVE_GET(x)               (((x) & SI_CONFIG_POS_DRIVE_MASK) >> SI_CONFIG_POS_DRIVE_LSB)
+#define SI_CONFIG_POS_DRIVE_SET(x)               (((x) << SI_CONFIG_POS_DRIVE_LSB) & SI_CONFIG_POS_DRIVE_MASK)
+#define SI_CONFIG_INACTIVE_DATA_MSB              5
+#define SI_CONFIG_INACTIVE_DATA_LSB              5
+#define SI_CONFIG_INACTIVE_DATA_MASK             0x00000020
+#define SI_CONFIG_INACTIVE_DATA_GET(x)           (((x) & SI_CONFIG_INACTIVE_DATA_MASK) >> SI_CONFIG_INACTIVE_DATA_LSB)
+#define SI_CONFIG_INACTIVE_DATA_SET(x)           (((x) << SI_CONFIG_INACTIVE_DATA_LSB) & SI_CONFIG_INACTIVE_DATA_MASK)
+#define SI_CONFIG_INACTIVE_CLK_MSB               4
+#define SI_CONFIG_INACTIVE_CLK_LSB               4
+#define SI_CONFIG_INACTIVE_CLK_MASK              0x00000010
+#define SI_CONFIG_INACTIVE_CLK_GET(x)            (((x) & SI_CONFIG_INACTIVE_CLK_MASK) >> SI_CONFIG_INACTIVE_CLK_LSB)
+#define SI_CONFIG_INACTIVE_CLK_SET(x)            (((x) << SI_CONFIG_INACTIVE_CLK_LSB) & SI_CONFIG_INACTIVE_CLK_MASK)
+#define SI_CONFIG_DIVIDER_MSB                    3
+#define SI_CONFIG_DIVIDER_LSB                    0
+#define SI_CONFIG_DIVIDER_MASK                   0x0000000f
+#define SI_CONFIG_DIVIDER_GET(x)                 (((x) & SI_CONFIG_DIVIDER_MASK) >> SI_CONFIG_DIVIDER_LSB)
+#define SI_CONFIG_DIVIDER_SET(x)                 (((x) << SI_CONFIG_DIVIDER_LSB) & SI_CONFIG_DIVIDER_MASK)
+
+#define SI_CS_ADDRESS                            0x00000004
+#define SI_CS_OFFSET                             0x00000004
+#define SI_CS_BIT_CNT_IN_LAST_BYTE_MSB           13
+#define SI_CS_BIT_CNT_IN_LAST_BYTE_LSB           11
+#define SI_CS_BIT_CNT_IN_LAST_BYTE_MASK          0x00003800
+#define SI_CS_BIT_CNT_IN_LAST_BYTE_GET(x)        (((x) & SI_CS_BIT_CNT_IN_LAST_BYTE_MASK) >> SI_CS_BIT_CNT_IN_LAST_BYTE_LSB)
+#define SI_CS_BIT_CNT_IN_LAST_BYTE_SET(x)        (((x) << SI_CS_BIT_CNT_IN_LAST_BYTE_LSB) & SI_CS_BIT_CNT_IN_LAST_BYTE_MASK)
+#define SI_CS_DONE_ERR_MSB                       10
+#define SI_CS_DONE_ERR_LSB                       10
+#define SI_CS_DONE_ERR_MASK                      0x00000400
+#define SI_CS_DONE_ERR_GET(x)                    (((x) & SI_CS_DONE_ERR_MASK) >> SI_CS_DONE_ERR_LSB)
+#define SI_CS_DONE_ERR_SET(x)                    (((x) << SI_CS_DONE_ERR_LSB) & SI_CS_DONE_ERR_MASK)
+#define SI_CS_DONE_INT_MSB                       9
+#define SI_CS_DONE_INT_LSB                       9
+#define SI_CS_DONE_INT_MASK                      0x00000200
+#define SI_CS_DONE_INT_GET(x)                    (((x) & SI_CS_DONE_INT_MASK) >> SI_CS_DONE_INT_LSB)
+#define SI_CS_DONE_INT_SET(x)                    (((x) << SI_CS_DONE_INT_LSB) & SI_CS_DONE_INT_MASK)
+#define SI_CS_START_MSB                          8
+#define SI_CS_START_LSB                          8
+#define SI_CS_START_MASK                         0x00000100
+#define SI_CS_START_GET(x)                       (((x) & SI_CS_START_MASK) >> SI_CS_START_LSB)
+#define SI_CS_START_SET(x)                       (((x) << SI_CS_START_LSB) & SI_CS_START_MASK)
+#define SI_CS_RX_CNT_MSB                         7
+#define SI_CS_RX_CNT_LSB                         4
+#define SI_CS_RX_CNT_MASK                        0x000000f0
+#define SI_CS_RX_CNT_GET(x)                      (((x) & SI_CS_RX_CNT_MASK) >> SI_CS_RX_CNT_LSB)
+#define SI_CS_RX_CNT_SET(x)                      (((x) << SI_CS_RX_CNT_LSB) & SI_CS_RX_CNT_MASK)
+#define SI_CS_TX_CNT_MSB                         3
+#define SI_CS_TX_CNT_LSB                         0
+#define SI_CS_TX_CNT_MASK                        0x0000000f
+#define SI_CS_TX_CNT_GET(x)                      (((x) & SI_CS_TX_CNT_MASK) >> SI_CS_TX_CNT_LSB)
+#define SI_CS_TX_CNT_SET(x)                      (((x) << SI_CS_TX_CNT_LSB) & SI_CS_TX_CNT_MASK)
+
+#define SI_TX_DATA0_ADDRESS                      0x00000008
+#define SI_TX_DATA0_OFFSET                       0x00000008
+#define SI_TX_DATA0_DATA3_MSB                    31
+#define SI_TX_DATA0_DATA3_LSB                    24
+#define SI_TX_DATA0_DATA3_MASK                   0xff000000
+#define SI_TX_DATA0_DATA3_GET(x)                 (((x) & SI_TX_DATA0_DATA3_MASK) >> SI_TX_DATA0_DATA3_LSB)
+#define SI_TX_DATA0_DATA3_SET(x)                 (((x) << SI_TX_DATA0_DATA3_LSB) & SI_TX_DATA0_DATA3_MASK)
+#define SI_TX_DATA0_DATA2_MSB                    23
+#define SI_TX_DATA0_DATA2_LSB                    16
+#define SI_TX_DATA0_DATA2_MASK                   0x00ff0000
+#define SI_TX_DATA0_DATA2_GET(x)                 (((x) & SI_TX_DATA0_DATA2_MASK) >> SI_TX_DATA0_DATA2_LSB)
+#define SI_TX_DATA0_DATA2_SET(x)                 (((x) << SI_TX_DATA0_DATA2_LSB) & SI_TX_DATA0_DATA2_MASK)
+#define SI_TX_DATA0_DATA1_MSB                    15
+#define SI_TX_DATA0_DATA1_LSB                    8
+#define SI_TX_DATA0_DATA1_MASK                   0x0000ff00
+#define SI_TX_DATA0_DATA1_GET(x)                 (((x) & SI_TX_DATA0_DATA1_MASK) >> SI_TX_DATA0_DATA1_LSB)
+#define SI_TX_DATA0_DATA1_SET(x)                 (((x) << SI_TX_DATA0_DATA1_LSB) & SI_TX_DATA0_DATA1_MASK)
+#define SI_TX_DATA0_DATA0_MSB                    7
+#define SI_TX_DATA0_DATA0_LSB                    0
+#define SI_TX_DATA0_DATA0_MASK                   0x000000ff
+#define SI_TX_DATA0_DATA0_GET(x)                 (((x) & SI_TX_DATA0_DATA0_MASK) >> SI_TX_DATA0_DATA0_LSB)
+#define SI_TX_DATA0_DATA0_SET(x)                 (((x) << SI_TX_DATA0_DATA0_LSB) & SI_TX_DATA0_DATA0_MASK)
+
+#define SI_TX_DATA1_ADDRESS                      0x0000000c
+#define SI_TX_DATA1_OFFSET                       0x0000000c
+#define SI_TX_DATA1_DATA7_MSB                    31
+#define SI_TX_DATA1_DATA7_LSB                    24
+#define SI_TX_DATA1_DATA7_MASK                   0xff000000
+#define SI_TX_DATA1_DATA7_GET(x)                 (((x) & SI_TX_DATA1_DATA7_MASK) >> SI_TX_DATA1_DATA7_LSB)
+#define SI_TX_DATA1_DATA7_SET(x)                 (((x) << SI_TX_DATA1_DATA7_LSB) & SI_TX_DATA1_DATA7_MASK)
+#define SI_TX_DATA1_DATA6_MSB                    23
+#define SI_TX_DATA1_DATA6_LSB                    16
+#define SI_TX_DATA1_DATA6_MASK                   0x00ff0000
+#define SI_TX_DATA1_DATA6_GET(x)                 (((x) & SI_TX_DATA1_DATA6_MASK) >> SI_TX_DATA1_DATA6_LSB)
+#define SI_TX_DATA1_DATA6_SET(x)                 (((x) << SI_TX_DATA1_DATA6_LSB) & SI_TX_DATA1_DATA6_MASK)
+#define SI_TX_DATA1_DATA5_MSB                    15
+#define SI_TX_DATA1_DATA5_LSB                    8
+#define SI_TX_DATA1_DATA5_MASK                   0x0000ff00
+#define SI_TX_DATA1_DATA5_GET(x)                 (((x) & SI_TX_DATA1_DATA5_MASK) >> SI_TX_DATA1_DATA5_LSB)
+#define SI_TX_DATA1_DATA5_SET(x)                 (((x) << SI_TX_DATA1_DATA5_LSB) & SI_TX_DATA1_DATA5_MASK)
+#define SI_TX_DATA1_DATA4_MSB                    7
+#define SI_TX_DATA1_DATA4_LSB                    0
+#define SI_TX_DATA1_DATA4_MASK                   0x000000ff
+#define SI_TX_DATA1_DATA4_GET(x)                 (((x) & SI_TX_DATA1_DATA4_MASK) >> SI_TX_DATA1_DATA4_LSB)
+#define SI_TX_DATA1_DATA4_SET(x)                 (((x) << SI_TX_DATA1_DATA4_LSB) & SI_TX_DATA1_DATA4_MASK)
+
+#define SI_RX_DATA0_ADDRESS                      0x00000010
+#define SI_RX_DATA0_OFFSET                       0x00000010
+#define SI_RX_DATA0_DATA3_MSB                    31
+#define SI_RX_DATA0_DATA3_LSB                    24
+#define SI_RX_DATA0_DATA3_MASK                   0xff000000
+#define SI_RX_DATA0_DATA3_GET(x)                 (((x) & SI_RX_DATA0_DATA3_MASK) >> SI_RX_DATA0_DATA3_LSB)
+#define SI_RX_DATA0_DATA3_SET(x)                 (((x) << SI_RX_DATA0_DATA3_LSB) & SI_RX_DATA0_DATA3_MASK)
+#define SI_RX_DATA0_DATA2_MSB                    23
+#define SI_RX_DATA0_DATA2_LSB                    16
+#define SI_RX_DATA0_DATA2_MASK                   0x00ff0000
+#define SI_RX_DATA0_DATA2_GET(x)                 (((x) & SI_RX_DATA0_DATA2_MASK) >> SI_RX_DATA0_DATA2_LSB)
+#define SI_RX_DATA0_DATA2_SET(x)                 (((x) << SI_RX_DATA0_DATA2_LSB) & SI_RX_DATA0_DATA2_MASK)
+#define SI_RX_DATA0_DATA1_MSB                    15
+#define SI_RX_DATA0_DATA1_LSB                    8
+#define SI_RX_DATA0_DATA1_MASK                   0x0000ff00
+#define SI_RX_DATA0_DATA1_GET(x)                 (((x) & SI_RX_DATA0_DATA1_MASK) >> SI_RX_DATA0_DATA1_LSB)
+#define SI_RX_DATA0_DATA1_SET(x)                 (((x) << SI_RX_DATA0_DATA1_LSB) & SI_RX_DATA0_DATA1_MASK)
+#define SI_RX_DATA0_DATA0_MSB                    7
+#define SI_RX_DATA0_DATA0_LSB                    0
+#define SI_RX_DATA0_DATA0_MASK                   0x000000ff
+#define SI_RX_DATA0_DATA0_GET(x)                 (((x) & SI_RX_DATA0_DATA0_MASK) >> SI_RX_DATA0_DATA0_LSB)
+#define SI_RX_DATA0_DATA0_SET(x)                 (((x) << SI_RX_DATA0_DATA0_LSB) & SI_RX_DATA0_DATA0_MASK)
+
+#define SI_RX_DATA1_ADDRESS                      0x00000014
+#define SI_RX_DATA1_OFFSET                       0x00000014
+#define SI_RX_DATA1_DATA7_MSB                    31
+#define SI_RX_DATA1_DATA7_LSB                    24
+#define SI_RX_DATA1_DATA7_MASK                   0xff000000
+#define SI_RX_DATA1_DATA7_GET(x)                 (((x) & SI_RX_DATA1_DATA7_MASK) >> SI_RX_DATA1_DATA7_LSB)
+#define SI_RX_DATA1_DATA7_SET(x)                 (((x) << SI_RX_DATA1_DATA7_LSB) & SI_RX_DATA1_DATA7_MASK)
+#define SI_RX_DATA1_DATA6_MSB                    23
+#define SI_RX_DATA1_DATA6_LSB                    16
+#define SI_RX_DATA1_DATA6_MASK                   0x00ff0000
+#define SI_RX_DATA1_DATA6_GET(x)                 (((x) & SI_RX_DATA1_DATA6_MASK) >> SI_RX_DATA1_DATA6_LSB)
+#define SI_RX_DATA1_DATA6_SET(x)                 (((x) << SI_RX_DATA1_DATA6_LSB) & SI_RX_DATA1_DATA6_MASK)
+#define SI_RX_DATA1_DATA5_MSB                    15
+#define SI_RX_DATA1_DATA5_LSB                    8
+#define SI_RX_DATA1_DATA5_MASK                   0x0000ff00
+#define SI_RX_DATA1_DATA5_GET(x)                 (((x) & SI_RX_DATA1_DATA5_MASK) >> SI_RX_DATA1_DATA5_LSB)
+#define SI_RX_DATA1_DATA5_SET(x)                 (((x) << SI_RX_DATA1_DATA5_LSB) & SI_RX_DATA1_DATA5_MASK)
+#define SI_RX_DATA1_DATA4_MSB                    7
+#define SI_RX_DATA1_DATA4_LSB                    0
+#define SI_RX_DATA1_DATA4_MASK                   0x000000ff
+#define SI_RX_DATA1_DATA4_GET(x)                 (((x) & SI_RX_DATA1_DATA4_MASK) >> SI_RX_DATA1_DATA4_LSB)
+#define SI_RX_DATA1_DATA4_SET(x)                 (((x) << SI_RX_DATA1_DATA4_LSB) & SI_RX_DATA1_DATA4_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct si_reg_reg_s {
+  volatile unsigned int si_config;
+  volatile unsigned int si_cs;
+  volatile unsigned int si_tx_data0;
+  volatile unsigned int si_tx_data1;
+  volatile unsigned int si_rx_data0;
+  volatile unsigned int si_rx_data1;
+} si_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _SI_REG_H_ */
diff --git a/drivers/net/ath6kl/include/common/AR6002/hw2.0/hw/uart_reg.h b/drivers/net/ath6kl/include/common/AR6002/hw2.0/hw/uart_reg.h
new file mode 100644
index 00000000000..5db321b72b2
--- /dev/null
+++ b/drivers/net/ath6kl/include/common/AR6002/hw2.0/hw/uart_reg.h
@@ -0,0 +1,327 @@
+#ifndef _UART_REG_REG_H_
+#define _UART_REG_REG_H_
+
+#define RBR_ADDRESS                              0x00000000
+#define RBR_OFFSET                               0x00000000
+#define RBR_RBR_MSB                              7
+#define RBR_RBR_LSB                              0
+#define RBR_RBR_MASK                             0x000000ff
+#define RBR_RBR_GET(x)                           (((x) & RBR_RBR_MASK) >> RBR_RBR_LSB)
+#define RBR_RBR_SET(x)                           (((x) << RBR_RBR_LSB) & RBR_RBR_MASK)
+
+#define THR_ADDRESS                              0x00000000
+#define THR_OFFSET                               0x00000000
+#define THR_THR_MSB                              7
+#define THR_THR_LSB                              0
+#define THR_THR_MASK                             0x000000ff
+#define THR_THR_GET(x)                           (((x) & THR_THR_MASK) >> THR_THR_LSB)
+#define THR_THR_SET(x)                           (((x) << THR_THR_LSB) & THR_THR_MASK)
+
+#define DLL_ADDRESS                              0x00000000
+#define DLL_OFFSET                               0x00000000
+#define DLL_DLL_MSB                              7
+#define DLL_DLL_LSB                              0
+#define DLL_DLL_MASK                             0x000000ff
+#define DLL_DLL_GET(x)                           (((x) & DLL_DLL_MASK) >> DLL_DLL_LSB)
+#define DLL_DLL_SET(x)                           (((x) << DLL_DLL_LSB) & DLL_DLL_MASK)
+
+#define DLH_ADDRESS                              0x00000004
+#define DLH_OFFSET                               0x00000004
+#define DLH_DLH_MSB                              7
+#define DLH_DLH_LSB                              0
+#define DLH_DLH_MASK                             0x000000ff
+#define DLH_DLH_GET(x)                           (((x) & DLH_DLH_MASK) >> DLH_DLH_LSB)
+#define DLH_DLH_SET(x)                           (((x) << DLH_DLH_LSB) & DLH_DLH_MASK)
+
+#define IER_ADDRESS                              0x00000004
+#define IER_OFFSET                               0x00000004
+#define IER_EDDSI_MSB                            3
+#define IER_EDDSI_LSB                            3
+#define IER_EDDSI_MASK                           0x00000008
+#define IER_EDDSI_GET(x)                         (((x) & IER_EDDSI_MASK) >> IER_EDDSI_LSB)
+#define IER_EDDSI_SET(x)                         (((x) << IER_EDDSI_LSB) & IER_EDDSI_MASK)
+#define IER_ELSI_MSB                             2
+#define IER_ELSI_LSB                             2
+#define IER_ELSI_MASK                            0x00000004
+#define IER_ELSI_GET(x)                          (((x) & IER_ELSI_MASK) >> IER_ELSI_LSB)
+#define IER_ELSI_SET(x)                          (((x) << IER_ELSI_LSB) & IER_ELSI_MASK)
+#define IER_ETBEI_MSB                            1
+#define IER_ETBEI_LSB                            1
+#define IER_ETBEI_MASK                           0x00000002
+#define IER_ETBEI_GET(x)                         (((x) & IER_ETBEI_MASK) >> IER_ETBEI_LSB)
+#define IER_ETBEI_SET(x)                         (((x) << IER_ETBEI_LSB) & IER_ETBEI_MASK)
+#define IER_ERBFI_MSB                            0
+#define IER_ERBFI_LSB                            0
+#define IER_ERBFI_MASK                           0x00000001
+#define IER_ERBFI_GET(x)                         (((x) & IER_ERBFI_MASK) >> IER_ERBFI_LSB)
+#define IER_ERBFI_SET(x)                         (((x) << IER_ERBFI_LSB) & IER_ERBFI_MASK)
+
+#define IIR_ADDRESS                              0x00000008
+#define IIR_OFFSET                               0x00000008
+#define IIR_FIFO_STATUS_MSB                      7
+#define IIR_FIFO_STATUS_LSB                      6
+#define IIR_FIFO_STATUS_MASK                     0x000000c0
+#define IIR_FIFO_STATUS_GET(x)                   (((x) & IIR_FIFO_STATUS_MASK) >> IIR_FIFO_STATUS_LSB)
+#define IIR_FIFO_STATUS_SET(x)                   (((x) << IIR_FIFO_STATUS_LSB) & IIR_FIFO_STATUS_MASK)
+#define IIR_IID_MSB                              3
+#define IIR_IID_LSB                              0
+#define IIR_IID_MASK                             0x0000000f
+#define IIR_IID_GET(x)                           (((x) & IIR_IID_MASK) >> IIR_IID_LSB)
+#define IIR_IID_SET(x)                           (((x) << IIR_IID_LSB) & IIR_IID_MASK)
+
+#define FCR_ADDRESS                              0x00000008
+#define FCR_OFFSET                               0x00000008
+#define FCR_RCVR_TRIG_MSB                        7
+#define FCR_RCVR_TRIG_LSB                        6
+#define FCR_RCVR_TRIG_MASK                       0x000000c0
+#define FCR_RCVR_TRIG_GET(x)                     (((x) & FCR_RCVR_TRIG_MASK) >> FCR_RCVR_TRIG_LSB)
+#define FCR_RCVR_TRIG_SET(x)                     (((x) << FCR_RCVR_TRIG_LSB) & FCR_RCVR_TRIG_MASK)
+#define FCR_DMA_MODE_MSB                         3
+#define FCR_DMA_MODE_LSB                         3
+#define FCR_DMA_MODE_MASK                        0x00000008
+#define FCR_DMA_MODE_GET(x)                      (((x) & FCR_DMA_MODE_MASK) >> FCR_DMA_MODE_LSB)
+#define FCR_DMA_MODE_SET(x)                      (((x) << FCR_DMA_MODE_LSB) & FCR_DMA_MODE_MASK)
+#define FCR_XMIT_FIFO_RST_MSB                    2
+#define FCR_XMIT_FIFO_RST_LSB                    2
+#define FCR_XMIT_FIFO_RST_MASK                   0x00000004
+#define FCR_XMIT_FIFO_RST_GET(x)                 (((x) & FCR_XMIT_FIFO_RST_MASK) >> FCR_XMIT_FIFO_RST_LSB)
+#define FCR_XMIT_FIFO_RST_SET(x)                 (((x) << FCR_XMIT_FIFO_RST_LSB) & FCR_XMIT_FIFO_RST_MASK)
+#define FCR_RCVR_FIFO_RST_MSB                    1
+#define FCR_RCVR_FIFO_RST_LSB                    1
+#define FCR_RCVR_FIFO_RST_MASK                   0x00000002
+#define FCR_RCVR_FIFO_RST_GET(x)                 (((x) & FCR_RCVR_FIFO_RST_MASK) >> FCR_RCVR_FIFO_RST_LSB)
+#define FCR_RCVR_FIFO_RST_SET(x)                 (((x) << FCR_RCVR_FIFO_RST_LSB) & FCR_RCVR_FIFO_RST_MASK)
+#define FCR_FIFO_EN_MSB                          0
+#define FCR_FIFO_EN_LSB                          0
+#define FCR_FIFO_EN_MASK                         0x00000001
+#define FCR_FIFO_EN_GET(x)                       (((x) & FCR_FIFO_EN_MASK) >> FCR_FIFO_EN_LSB)
+#define FCR_FIFO_EN_SET(x)                       (((x) << FCR_FIFO_EN_LSB) & FCR_FIFO_EN_MASK)
+
+#define LCR_ADDRESS                              0x0000000c
+#define LCR_OFFSET                               0x0000000c
+#define LCR_DLAB_MSB                             7
+#define LCR_DLAB_LSB                             7
+#define LCR_DLAB_MASK                            0x00000080
+#define LCR_DLAB_GET(x)                          (((x) & LCR_DLAB_MASK) >> LCR_DLAB_LSB)
+#define LCR_DLAB_SET(x)                          (((x) << LCR_DLAB_LSB) & LCR_DLAB_MASK)
+#define LCR_BREAK_MSB                            6
+#define LCR_BREAK_LSB                            6
+#define LCR_BREAK_MASK                           0x00000040
+#define LCR_BREAK_GET(x)                         (((x) & LCR_BREAK_MASK) >> LCR_BREAK_LSB)
+#define LCR_BREAK_SET(x)                         (((x) << LCR_BREAK_LSB) & LCR_BREAK_MASK)
+#define LCR_EPS_MSB                              4
+#define LCR_EPS_LSB                              4
+#define LCR_EPS_MASK                             0x00000010
+#define LCR_EPS_GET(x)                           (((x) & LCR_EPS_MASK) >> LCR_EPS_LSB)
+#define LCR_EPS_SET(x)                           (((x) << LCR_EPS_LSB) & LCR_EPS_MASK)
+#define LCR_PEN_MSB                              3
+#define LCR_PEN_LSB                              3
+#define LCR_PEN_MASK                             0x00000008
+#define LCR_PEN_GET(x)                           (((x) & LCR_PEN_MASK) >> LCR_PEN_LSB)
+#define LCR_PEN_SET(x)                           (((x) << LCR_PEN_LSB) & LCR_PEN_MASK)
+#define LCR_STOP_MSB                             2
+#define LCR_STOP_LSB                             2
+#define LCR_STOP_MASK                            0x00000004
+#define LCR_STOP_GET(x)                          (((x) & LCR_STOP_MASK) >> LCR_STOP_LSB)
+#define LCR_STOP_SET(x)                          (((x) << LCR_STOP_LSB) & LCR_STOP_MASK)
+#define LCR_CLS_MSB                              1
+#define LCR_CLS_LSB                              0
+#define LCR_CLS_MASK                             0x00000003
+#define LCR_CLS_GET(x)                           (((x) & LCR_CLS_MASK) >> LCR_CLS_LSB)
+#define LCR_CLS_SET(x)                           (((x) << LCR_CLS_LSB) & LCR_CLS_MASK)
+
+#define MCR_ADDRESS                              0x00000010
+#define MCR_OFFSET                               0x00000010
+#define MCR_LOOPBACK_MSB                         5
+#define MCR_LOOPBACK_LSB                         5
+#define MCR_LOOPBACK_MASK                        0x00000020
+#define MCR_LOOPBACK_GET(x)                      (((x) & MCR_LOOPBACK_MASK) >> MCR_LOOPBACK_LSB)
+#define MCR_LOOPBACK_SET(x)                      (((x) << MCR_LOOPBACK_LSB) & MCR_LOOPBACK_MASK)
+#define MCR_OUT2_MSB                             3
+#define MCR_OUT2_LSB                             3
+#define MCR_OUT2_MASK                            0x00000008
+#define MCR_OUT2_GET(x)                          (((x) & MCR_OUT2_MASK) >> MCR_OUT2_LSB)
+#define MCR_OUT2_SET(x)                          (((x) << MCR_OUT2_LSB) & MCR_OUT2_MASK)
+#define MCR_OUT1_MSB                             2
+#define MCR_OUT1_LSB                             2
+#define MCR_OUT1_MASK                            0x00000004
+#define MCR_OUT1_GET(x)                          (((x) & MCR_OUT1_MASK) >> MCR_OUT1_LSB)
+#define MCR_OUT1_SET(x)                          (((x) << MCR_OUT1_LSB) & MCR_OUT1_MASK)
+#define MCR_RTS_MSB                              1
+#define MCR_RTS_LSB                              1
+#define MCR_RTS_MASK                             0x00000002
+#define MCR_RTS_GET(x)                           (((x) & MCR_RTS_MASK) >> MCR_RTS_LSB)
+#define MCR_RTS_SET(x)                           (((x) << MCR_RTS_LSB) & MCR_RTS_MASK)
+#define MCR_DTR_MSB                              0
+#define MCR_DTR_LSB                              0
+#define MCR_DTR_MASK                             0x00000001
+#define MCR_DTR_GET(x)                           (((x) & MCR_DTR_MASK) >> MCR_DTR_LSB)
+#define MCR_DTR_SET(x)                           (((x) << MCR_DTR_LSB) & MCR_DTR_MASK)
+
+#define LSR_ADDRESS                              0x00000014
+#define LSR_OFFSET                               0x00000014
+#define LSR_FERR_MSB                             7
+#define LSR_FERR_LSB                             7
+#define LSR_FERR_MASK                            0x00000080
+#define LSR_FERR_GET(x)                          (((x) & LSR_FERR_MASK) >> LSR_FERR_LSB)
+#define LSR_FERR_SET(x)                          (((x) << LSR_FERR_LSB) & LSR_FERR_MASK)
+#define LSR_TEMT_MSB                             6
+#define LSR_TEMT_LSB                             6
+#define LSR_TEMT_MASK                            0x00000040
+#define LSR_TEMT_GET(x)                          (((x) & LSR_TEMT_MASK) >> LSR_TEMT_LSB)
+#define LSR_TEMT_SET(x)                          (((x) << LSR_TEMT_LSB) & LSR_TEMT_MASK)
+#define LSR_THRE_MSB                             5
+#define LSR_THRE_LSB                             5
+#define LSR_THRE_MASK                            0x00000020
+#define LSR_THRE_GET(x)                          (((x) & LSR_THRE_MASK) >> LSR_THRE_LSB)
+#define LSR_THRE_SET(x)                          (((x) << LSR_THRE_LSB) & LSR_THRE_MASK)
+#define LSR_BI_MSB                               4
+#define LSR_BI_LSB                               4
+#define LSR_BI_MASK                              0x00000010
+#define LSR_BI_GET(x)                            (((x) & LSR_BI_MASK) >> LSR_BI_LSB)
+#define LSR_BI_SET(x)                            (((x) << LSR_BI_LSB) & LSR_BI_MASK)
+#define LSR_FE_MSB                               3
+#define LSR_FE_LSB                               3
+#define LSR_FE_MASK                              0x00000008
+#define LSR_FE_GET(x)                            (((x) & LSR_FE_MASK) >> LSR_FE_LSB)
+#define LSR_FE_SET(x)                            (((x) << LSR_FE_LSB) & LSR_FE_MASK)
+#define LSR_PE_MSB                               2
+#define LSR_PE_LSB                               2
+#define LSR_PE_MASK                              0x00000004
+#define LSR_PE_GET(x)                            (((x) & LSR_PE_MASK) >> LSR_PE_LSB)
+#define LSR_PE_SET(x)                            (((x) << LSR_PE_LSB) & LSR_PE_MASK)
+#define LSR_OE_MSB                               1
+#define LSR_OE_LSB                               1
+#define LSR_OE_MASK                              0x00000002
+#define LSR_OE_GET(x)                            (((x) & LSR_OE_MASK) >> LSR_OE_LSB)
+#define LSR_OE_SET(x)                            (((x) << LSR_OE_LSB) & LSR_OE_MASK)
+#define LSR_DR_MSB                               0
+#define LSR_DR_LSB                               0
+#define LSR_DR_MASK                              0x00000001
+#define LSR_DR_GET(x)                            (((x) & LSR_DR_MASK) >> LSR_DR_LSB)
+#define LSR_DR_SET(x)                            (((x) << LSR_DR_LSB) & LSR_DR_MASK)
+
+#define MSR_ADDRESS                              0x00000018
+#define MSR_OFFSET                               0x00000018
+#define MSR_DCD_MSB                              7
+#define MSR_DCD_LSB                              7
+#define MSR_DCD_MASK                             0x00000080
+#define MSR_DCD_GET(x)                           (((x) & MSR_DCD_MASK) >> MSR_DCD_LSB)
+#define MSR_DCD_SET(x)                           (((x) << MSR_DCD_LSB) & MSR_DCD_MASK)
+#define MSR_RI_MSB                               6
+#define MSR_RI_LSB                               6
+#define MSR_RI_MASK                              0x00000040
+#define MSR_RI_GET(x)                            (((x) & MSR_RI_MASK) >> MSR_RI_LSB)
+#define MSR_RI_SET(x)                            (((x) << MSR_RI_LSB) & MSR_RI_MASK)
+#define MSR_DSR_MSB                              5
+#define MSR_DSR_LSB                              5
+#define MSR_DSR_MASK                             0x00000020
+#define MSR_DSR_GET(x)                           (((x) & MSR_DSR_MASK) >> MSR_DSR_LSB)
+#define MSR_DSR_SET(x)                           (((x) << MSR_DSR_LSB) & MSR_DSR_MASK)
+#define MSR_CTS_MSB                              4
+#define MSR_CTS_LSB                              4
+#define MSR_CTS_MASK                             0x00000010
+#define MSR_CTS_GET(x)                           (((x) & MSR_CTS_MASK) >> MSR_CTS_LSB)
+#define MSR_CTS_SET(x)                           (((x) << MSR_CTS_LSB) & MSR_CTS_MASK)
+#define MSR_DDCD_MSB                             3
+#define MSR_DDCD_LSB                             3
+#define MSR_DDCD_MASK                            0x00000008
+#define MSR_DDCD_GET(x)                          (((x) & MSR_DDCD_MASK) >> MSR_DDCD_LSB)
+#define MSR_DDCD_SET(x)                          (((x) << MSR_DDCD_LSB) & MSR_DDCD_MASK)
+#define MSR_TERI_MSB                             2
+#define MSR_TERI_LSB                             2
+#define MSR_TERI_MASK                            0x00000004
+#define MSR_TERI_GET(x)                          (((x) & MSR_TERI_MASK) >> MSR_TERI_LSB)
+#define MSR_TERI_SET(x)                          (((x) << MSR_TERI_LSB) & MSR_TERI_MASK)
+#define MSR_DDSR_MSB                             1
+#define MSR_DDSR_LSB                             1
+#define MSR_DDSR_MASK                            0x00000002
+#define MSR_DDSR_GET(x)                          (((x) & MSR_DDSR_MASK) >> MSR_DDSR_LSB)
+#define MSR_DDSR_SET(x)                          (((x) << MSR_DDSR_LSB) & MSR_DDSR_MASK)
+#define MSR_DCTS_MSB                             0
+#define MSR_DCTS_LSB                             0
+#define MSR_DCTS_MASK                            0x00000001
+#define MSR_DCTS_GET(x)                          (((x) & MSR_DCTS_MASK) >> MSR_DCTS_LSB)
+#define MSR_DCTS_SET(x)                          (((x) << MSR_DCTS_LSB) & MSR_DCTS_MASK)
+
+#define SCR_ADDRESS                              0x0000001c
+#define SCR_OFFSET                               0x0000001c
+#define SCR_SCR_MSB                              7
+#define SCR_SCR_LSB                              0
+#define SCR_SCR_MASK                             0x000000ff
+#define SCR_SCR_GET(x)                           (((x) & SCR_SCR_MASK) >> SCR_SCR_LSB)
+#define SCR_SCR_SET(x)                           (((x) << SCR_SCR_LSB) & SCR_SCR_MASK)
+
+#define SRBR_ADDRESS                             0x00000020
+#define SRBR_OFFSET                              0x00000020
+#define SRBR_SRBR_MSB                            7
+#define SRBR_SRBR_LSB                            0
+#define SRBR_SRBR_MASK                           0x000000ff
+#define SRBR_SRBR_GET(x)                         (((x) & SRBR_SRBR_MASK) >> SRBR_SRBR_LSB)
+#define SRBR_SRBR_SET(x)                         (((x) << SRBR_SRBR_LSB) & SRBR_SRBR_MASK)
+
+#define SIIR_ADDRESS                             0x00000028
+#define SIIR_OFFSET                              0x00000028
+#define SIIR_SIIR_MSB                            7
+#define SIIR_SIIR_LSB                            0
+#define SIIR_SIIR_MASK                           0x000000ff
+#define SIIR_SIIR_GET(x)                         (((x) & SIIR_SIIR_MASK) >> SIIR_SIIR_LSB)
+#define SIIR_SIIR_SET(x)                         (((x) << SIIR_SIIR_LSB) & SIIR_SIIR_MASK)
+
+#define MWR_ADDRESS                              0x0000002c
+#define MWR_OFFSET                               0x0000002c
+#define MWR_MWR_MSB                              31
+#define MWR_MWR_LSB                              0
+#define MWR_MWR_MASK                             0xffffffff
+#define MWR_MWR_GET(x)                           (((x) & MWR_MWR_MASK) >> MWR_MWR_LSB)
+#define MWR_MWR_SET(x)                           (((x) << MWR_MWR_LSB) & MWR_MWR_MASK)
+
+#define SLSR_ADDRESS                             0x00000034
+#define SLSR_OFFSET                              0x00000034
+#define SLSR_SLSR_MSB                            7
+#define SLSR_SLSR_LSB                            0
+#define SLSR_SLSR_MASK                           0x000000ff
+#define SLSR_SLSR_GET(x)                         (((x) & SLSR_SLSR_MASK) >> SLSR_SLSR_LSB)
+#define SLSR_SLSR_SET(x)                         (((x) << SLSR_SLSR_LSB) & SLSR_SLSR_MASK)
+
+#define SMSR_ADDRESS                             0x00000038
+#define SMSR_OFFSET                              0x00000038
+#define SMSR_SMSR_MSB                            7
+#define SMSR_SMSR_LSB                            0
+#define SMSR_SMSR_MASK                           0x000000ff
+#define SMSR_SMSR_GET(x)                         (((x) & SMSR_SMSR_MASK) >> SMSR_SMSR_LSB)
+#define SMSR_SMSR_SET(x)                         (((x) << SMSR_SMSR_LSB) & SMSR_SMSR_MASK)
+
+#define MRR_ADDRESS                              0x0000003c
+#define MRR_OFFSET                               0x0000003c
+#define MRR_MRR_MSB                              31
+#define MRR_MRR_LSB                              0
+#define MRR_MRR_MASK                             0xffffffff
+#define MRR_MRR_GET(x)                           (((x) & MRR_MRR_MASK) >> MRR_MRR_LSB)
+#define MRR_MRR_SET(x)                           (((x) << MRR_MRR_LSB) & MRR_MRR_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct uart_reg_reg_s {
+  volatile unsigned int rbr;
+  volatile unsigned int dlh;
+  volatile unsigned int iir;
+  volatile unsigned int lcr;
+  volatile unsigned int mcr;
+  volatile unsigned int lsr;
+  volatile unsigned int msr;
+  volatile unsigned int scr;
+  volatile unsigned int srbr;
+  unsigned char pad0[4]; /* pad to 0x28 */
+  volatile unsigned int siir;
+  volatile unsigned int mwr;
+  unsigned char pad1[4]; /* pad to 0x34 */
+  volatile unsigned int slsr;
+  volatile unsigned int smsr;
+  volatile unsigned int mrr;
+} uart_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _UART_REG_H_ */
diff --git a/drivers/net/ath6kl/include/common/AR6002/hw2.0/hw/vmc_reg.h b/drivers/net/ath6kl/include/common/AR6002/hw2.0/hw/vmc_reg.h
new file mode 100644
index 00000000000..932ec510d26
--- /dev/null
+++ b/drivers/net/ath6kl/include/common/AR6002/hw2.0/hw/vmc_reg.h
@@ -0,0 +1,76 @@
+#ifndef _VMC_REG_REG_H_
+#define _VMC_REG_REG_H_
+
+#define MC_TCAM_VALID_ADDRESS                    0x00000000
+#define MC_TCAM_VALID_OFFSET                     0x00000000
+#define MC_TCAM_VALID_BIT_MSB                    0
+#define MC_TCAM_VALID_BIT_LSB                    0
+#define MC_TCAM_VALID_BIT_MASK                   0x00000001
+#define MC_TCAM_VALID_BIT_GET(x)                 (((x) & MC_TCAM_VALID_BIT_MASK) >> MC_TCAM_VALID_BIT_LSB)
+#define MC_TCAM_VALID_BIT_SET(x)                 (((x) << MC_TCAM_VALID_BIT_LSB) & MC_TCAM_VALID_BIT_MASK)
+
+#define MC_TCAM_MASK_ADDRESS                     0x00000080
+#define MC_TCAM_MASK_OFFSET                      0x00000080
+#define MC_TCAM_MASK_SIZE_MSB                    2
+#define MC_TCAM_MASK_SIZE_LSB                    0
+#define MC_TCAM_MASK_SIZE_MASK                   0x00000007
+#define MC_TCAM_MASK_SIZE_GET(x)                 (((x) & MC_TCAM_MASK_SIZE_MASK) >> MC_TCAM_MASK_SIZE_LSB)
+#define MC_TCAM_MASK_SIZE_SET(x)                 (((x) << MC_TCAM_MASK_SIZE_LSB) & MC_TCAM_MASK_SIZE_MASK)
+
+#define MC_TCAM_COMPARE_ADDRESS                  0x00000100
+#define MC_TCAM_COMPARE_OFFSET                   0x00000100
+#define MC_TCAM_COMPARE_KEY_MSB                  21
+#define MC_TCAM_COMPARE_KEY_LSB                  5
+#define MC_TCAM_COMPARE_KEY_MASK                 0x003fffe0
+#define MC_TCAM_COMPARE_KEY_GET(x)               (((x) & MC_TCAM_COMPARE_KEY_MASK) >> MC_TCAM_COMPARE_KEY_LSB)
+#define MC_TCAM_COMPARE_KEY_SET(x)               (((x) << MC_TCAM_COMPARE_KEY_LSB) & MC_TCAM_COMPARE_KEY_MASK)
+
+#define MC_TCAM_TARGET_ADDRESS                   0x00000180
+#define MC_TCAM_TARGET_OFFSET                    0x00000180
+#define MC_TCAM_TARGET_ADDR_MSB                  21
+#define MC_TCAM_TARGET_ADDR_LSB                  5
+#define MC_TCAM_TARGET_ADDR_MASK                 0x003fffe0
+#define MC_TCAM_TARGET_ADDR_GET(x)               (((x) & MC_TCAM_TARGET_ADDR_MASK) >> MC_TCAM_TARGET_ADDR_LSB)
+#define MC_TCAM_TARGET_ADDR_SET(x)               (((x) << MC_TCAM_TARGET_ADDR_LSB) & MC_TCAM_TARGET_ADDR_MASK)
+
+#define ADDR_ERROR_CONTROL_ADDRESS               0x00000200
+#define ADDR_ERROR_CONTROL_OFFSET                0x00000200
+#define ADDR_ERROR_CONTROL_QUAL_ENABLE_MSB       1
+#define ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB       1
+#define ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK      0x00000002
+#define ADDR_ERROR_CONTROL_QUAL_ENABLE_GET(x)    (((x) & ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK) >> ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB)
+#define ADDR_ERROR_CONTROL_QUAL_ENABLE_SET(x)    (((x) << ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB) & ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK)
+#define ADDR_ERROR_CONTROL_ENABLE_MSB            0
+#define ADDR_ERROR_CONTROL_ENABLE_LSB            0
+#define ADDR_ERROR_CONTROL_ENABLE_MASK           0x00000001
+#define ADDR_ERROR_CONTROL_ENABLE_GET(x)         (((x) & ADDR_ERROR_CONTROL_ENABLE_MASK) >> ADDR_ERROR_CONTROL_ENABLE_LSB)
+#define ADDR_ERROR_CONTROL_ENABLE_SET(x)         (((x) << ADDR_ERROR_CONTROL_ENABLE_LSB) & ADDR_ERROR_CONTROL_ENABLE_MASK)
+
+#define ADDR_ERROR_STATUS_ADDRESS                0x00000204
+#define ADDR_ERROR_STATUS_OFFSET                 0x00000204
+#define ADDR_ERROR_STATUS_WRITE_MSB              25
+#define ADDR_ERROR_STATUS_WRITE_LSB              25
+#define ADDR_ERROR_STATUS_WRITE_MASK             0x02000000
+#define ADDR_ERROR_STATUS_WRITE_GET(x)           (((x) & ADDR_ERROR_STATUS_WRITE_MASK) >> ADDR_ERROR_STATUS_WRITE_LSB)
+#define ADDR_ERROR_STATUS_WRITE_SET(x)           (((x) << ADDR_ERROR_STATUS_WRITE_LSB) & ADDR_ERROR_STATUS_WRITE_MASK)
+#define ADDR_ERROR_STATUS_ADDRESS_MSB            24
+#define ADDR_ERROR_STATUS_ADDRESS_LSB            0
+#define ADDR_ERROR_STATUS_ADDRESS_MASK           0x01ffffff
+#define ADDR_ERROR_STATUS_ADDRESS_GET(x)         (((x) & ADDR_ERROR_STATUS_ADDRESS_MASK) >> ADDR_ERROR_STATUS_ADDRESS_LSB)
+#define ADDR_ERROR_STATUS_ADDRESS_SET(x)         (((x) << ADDR_ERROR_STATUS_ADDRESS_LSB) & ADDR_ERROR_STATUS_ADDRESS_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct vmc_reg_reg_s {
+  volatile unsigned int mc_tcam_valid[32];
+  volatile unsigned int mc_tcam_mask[32];
+  volatile unsigned int mc_tcam_compare[32];
+  volatile unsigned int mc_tcam_target[32];
+  volatile unsigned int addr_error_control;
+  volatile unsigned int addr_error_status;
+} vmc_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _VMC_REG_H_ */
diff --git a/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/analog_intf_ares_reg.h b/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/analog_intf_ares_reg.h
new file mode 100644
index 00000000000..5970fa94d4d
--- /dev/null
+++ b/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/analog_intf_ares_reg.h
@@ -0,0 +1,3291 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+/* Copyright (C) 2009 Denali Software Inc.  All rights reserved              */
+/* THIS FILE IS AUTOMATICALLY GENERATED BY DENALI BLUEPRINT, DO NOT EDIT     */
+
+
+#ifndef _ANALOG_INTF_ARES_REG_REG_H_
+#define _ANALOG_INTF_ARES_REG_REG_H_
+
+
+/* macros for RXRF_BIAS1 */
+#define PHY_ANALOG_RXRF_BIAS1_ADDRESS                                                                0x00000000
+#define PHY_ANALOG_RXRF_BIAS1_OFFSET                                                                 0x00000000
+#define PHY_ANALOG_RXRF_BIAS1_SPARE_MSB                                                                       0
+#define PHY_ANALOG_RXRF_BIAS1_SPARE_LSB                                                                       0
+#define PHY_ANALOG_RXRF_BIAS1_SPARE_MASK                                                             0x00000001
+#define PHY_ANALOG_RXRF_BIAS1_SPARE_GET(x)                                            (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_RXRF_BIAS1_SPARE_SET(x)                                            (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25SPARE_MSB                                                               3
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25SPARE_LSB                                                               1
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25SPARE_MASK                                                     0x0000000e
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25SPARE_GET(x)                                    (((x) & 0x0000000e) >> 1)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25SPARE_SET(x)                                    (((x) << 1) & 0x0000000e)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO18_MSB                                                                6
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO18_LSB                                                                4
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO18_MASK                                                      0x00000070
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO18_GET(x)                                     (((x) & 0x00000070) >> 4)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO18_SET(x)                                     (((x) << 4) & 0x00000070)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25LO36_MSB                                                                9
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25LO36_LSB                                                                7
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25LO36_MASK                                                      0x00000380
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25LO36_GET(x)                                     (((x) & 0x00000380) >> 7)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25LO36_SET(x)                                     (((x) << 7) & 0x00000380)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2_5GH_MSB                                                           12
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2_5GH_LSB                                                           10
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2_5GH_MASK                                                  0x00001c00
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2_5GH_GET(x)                                (((x) & 0x00001c00) >> 10)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2_5GH_SET(x)                                (((x) << 10) & 0x00001c00)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR5GH_MSB                                                             15
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR5GH_LSB                                                             13
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR5GH_MASK                                                    0x0000e000
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR5GH_GET(x)                                  (((x) & 0x0000e000) >> 13)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR5GH_SET(x)                                  (((x) << 13) & 0x0000e000)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25VGA5G_MSB                                                              18
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25VGA5G_LSB                                                              16
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25VGA5G_MASK                                                     0x00070000
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25VGA5G_GET(x)                                   (((x) & 0x00070000) >> 16)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25VGA5G_SET(x)                                   (((x) << 16) & 0x00070000)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA5G_MSB                                                              21
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA5G_LSB                                                              19
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA5G_MASK                                                     0x00380000
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA5G_GET(x)                                   (((x) & 0x00380000) >> 19)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA5G_SET(x)                                   (((x) << 19) & 0x00380000)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO24_MSB                                                               24
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO24_LSB                                                               22
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO24_MASK                                                      0x01c00000
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO24_GET(x)                                    (((x) & 0x01c00000) >> 22)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO24_SET(x)                                    (((x) << 22) & 0x01c00000)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2GH_MSB                                                             27
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2GH_LSB                                                             25
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2GH_MASK                                                    0x0e000000
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2GH_GET(x)                                  (((x) & 0x0e000000) >> 25)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2GH_SET(x)                                  (((x) << 25) & 0x0e000000)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA2G_MSB                                                              30
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA2G_LSB                                                              28
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA2G_MASK                                                     0x70000000
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA2G_GET(x)                                   (((x) & 0x70000000) >> 28)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA2G_SET(x)                                   (((x) << 28) & 0x70000000)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_BIAS_MSB                                                                   31
+#define PHY_ANALOG_RXRF_BIAS1_PWD_BIAS_LSB                                                                   31
+#define PHY_ANALOG_RXRF_BIAS1_PWD_BIAS_MASK                                                          0x80000000
+#define PHY_ANALOG_RXRF_BIAS1_PWD_BIAS_GET(x)                                        (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_BIAS_SET(x)                                        (((x) << 31) & 0x80000000)
+
+/* macros for RXRF_BIAS2 */
+#define PHY_ANALOG_RXRF_BIAS2_ADDRESS                                                                0x00000004
+#define PHY_ANALOG_RXRF_BIAS2_OFFSET                                                                 0x00000004
+#define PHY_ANALOG_RXRF_BIAS2_SPARE_MSB                                                                       0
+#define PHY_ANALOG_RXRF_BIAS2_SPARE_LSB                                                                       0
+#define PHY_ANALOG_RXRF_BIAS2_SPARE_MASK                                                             0x00000001
+#define PHY_ANALOG_RXRF_BIAS2_SPARE_GET(x)                                            (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_RXRF_BIAS2_SPARE_SET(x)                                            (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_RXRF_BIAS2_PKEN_MSB                                                                        3
+#define PHY_ANALOG_RXRF_BIAS2_PKEN_LSB                                                                        1
+#define PHY_ANALOG_RXRF_BIAS2_PKEN_MASK                                                              0x0000000e
+#define PHY_ANALOG_RXRF_BIAS2_PKEN_GET(x)                                             (((x) & 0x0000000e) >> 1)
+#define PHY_ANALOG_RXRF_BIAS2_PKEN_SET(x)                                             (((x) << 1) & 0x0000000e)
+#define PHY_ANALOG_RXRF_BIAS2_VCMVALUE_MSB                                                                    6
+#define PHY_ANALOG_RXRF_BIAS2_VCMVALUE_LSB                                                                    4
+#define PHY_ANALOG_RXRF_BIAS2_VCMVALUE_MASK                                                          0x00000070
+#define PHY_ANALOG_RXRF_BIAS2_VCMVALUE_GET(x)                                         (((x) & 0x00000070) >> 4)
+#define PHY_ANALOG_RXRF_BIAS2_VCMVALUE_SET(x)                                         (((x) << 4) & 0x00000070)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_VCMBUF_MSB                                                                  7
+#define PHY_ANALOG_RXRF_BIAS2_PWD_VCMBUF_LSB                                                                  7
+#define PHY_ANALOG_RXRF_BIAS2_PWD_VCMBUF_MASK                                                        0x00000080
+#define PHY_ANALOG_RXRF_BIAS2_PWD_VCMBUF_GET(x)                                       (((x) & 0x00000080) >> 7)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_VCMBUF_SET(x)                                       (((x) << 7) & 0x00000080)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC5GH_MSB                                                             10
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC5GH_LSB                                                              8
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC5GH_MASK                                                    0x00000700
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC5GH_GET(x)                                   (((x) & 0x00000700) >> 8)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC5GH_SET(x)                                   (((x) << 8) & 0x00000700)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC5G_MSB                                                              13
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC5G_LSB                                                              11
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC5G_MASK                                                     0x00003800
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC5G_GET(x)                                   (((x) & 0x00003800) >> 11)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC5G_SET(x)                                   (((x) << 11) & 0x00003800)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC5G_MSB                                                              16
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC5G_LSB                                                              14
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC5G_MASK                                                     0x0001c000
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC5G_GET(x)                                   (((x) & 0x0001c000) >> 14)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC5G_SET(x)                                   (((x) << 14) & 0x0001c000)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC2GH_MSB                                                             19
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC2GH_LSB                                                             17
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC2GH_MASK                                                    0x000e0000
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC2GH_GET(x)                                  (((x) & 0x000e0000) >> 17)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC2GH_SET(x)                                  (((x) << 17) & 0x000e0000)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC2G_MSB                                                              22
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC2G_LSB                                                              20
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC2G_MASK                                                     0x00700000
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC2G_GET(x)                                   (((x) & 0x00700000) >> 20)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC2G_SET(x)                                   (((x) << 20) & 0x00700000)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC2G_MSB                                                              25
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC2G_LSB                                                              23
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC2G_MASK                                                     0x03800000
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC2G_GET(x)                                   (((x) & 0x03800000) >> 23)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC2G_SET(x)                                   (((x) << 23) & 0x03800000)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25VCMBUF_MSB                                                             28
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25VCMBUF_LSB                                                             26
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25VCMBUF_MASK                                                    0x1c000000
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25VCMBUF_GET(x)                                  (((x) & 0x1c000000) >> 26)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25VCMBUF_SET(x)                                  (((x) << 26) & 0x1c000000)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25VCM_MSB                                                                31
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25VCM_LSB                                                                29
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25VCM_MASK                                                       0xe0000000
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25VCM_GET(x)                                     (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25VCM_SET(x)                                     (((x) << 29) & 0xe0000000)
+
+/* macros for RXRF_GAINSTAGES */
+#define PHY_ANALOG_RXRF_GAINSTAGES_ADDRESS                                                           0x00000008
+#define PHY_ANALOG_RXRF_GAINSTAGES_OFFSET                                                            0x00000008
+#define PHY_ANALOG_RXRF_GAINSTAGES_SPARE_MSB                                                                  0
+#define PHY_ANALOG_RXRF_GAINSTAGES_SPARE_LSB                                                                  0
+#define PHY_ANALOG_RXRF_GAINSTAGES_SPARE_MASK                                                        0x00000001
+#define PHY_ANALOG_RXRF_GAINSTAGES_SPARE_GET(x)                                       (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_RXRF_GAINSTAGES_SPARE_SET(x)                                       (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNAON_CALDC_MSB                                                            1
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNAON_CALDC_LSB                                                            1
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNAON_CALDC_MASK                                                  0x00000002
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNAON_CALDC_GET(x)                                 (((x) & 0x00000002) >> 1)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNAON_CALDC_SET(x)                                 (((x) << 1) & 0x00000002)
+#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_CAP_MSB                                                              3
+#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_CAP_LSB                                                              2
+#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_CAP_MASK                                                    0x0000000c
+#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_CAP_GET(x)                                   (((x) & 0x0000000c) >> 2)
+#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_CAP_SET(x)                                   (((x) << 2) & 0x0000000c)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_CAP_MSB                                                              5
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_CAP_LSB                                                              4
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_CAP_MASK                                                    0x00000030
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_CAP_GET(x)                                   (((x) & 0x00000030) >> 4)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_CAP_SET(x)                                   (((x) << 4) & 0x00000030)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_SHORTINP_MSB                                                         6
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_SHORTINP_LSB                                                         6
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_SHORTINP_MASK                                               0x00000040
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_SHORTINP_GET(x)                              (((x) & 0x00000040) >> 6)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_SHORTINP_SET(x)                              (((x) << 6) & 0x00000040)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO5G_MSB                                                               7
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO5G_LSB                                                               7
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO5G_MASK                                                     0x00000080
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO5G_GET(x)                                    (((x) & 0x00000080) >> 7)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO5G_SET(x)                                    (((x) << 7) & 0x00000080)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_VGA5G_MSB                                                              8
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_VGA5G_LSB                                                              8
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_VGA5G_MASK                                                    0x00000100
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_VGA5G_GET(x)                                   (((x) & 0x00000100) >> 8)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_VGA5G_SET(x)                                   (((x) << 8) & 0x00000100)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR5G_MSB                                                              9
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR5G_LSB                                                              9
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR5G_MASK                                                    0x00000200
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR5G_GET(x)                                   (((x) & 0x00000200) >> 9)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR5G_SET(x)                                   (((x) << 9) & 0x00000200)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA5G_MSB                                                             10
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA5G_LSB                                                             10
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA5G_MASK                                                    0x00000400
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA5G_GET(x)                                  (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA5G_SET(x)                                  (((x) << 10) & 0x00000400)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_CAP_MSB                                                             12
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_CAP_LSB                                                             11
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_CAP_MASK                                                    0x00001800
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_CAP_GET(x)                                  (((x) & 0x00001800) >> 11)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_CAP_SET(x)                                  (((x) << 11) & 0x00001800)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_SHORTINP_MSB                                                        13
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_SHORTINP_LSB                                                        13
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_SHORTINP_MASK                                               0x00002000
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_SHORTINP_GET(x)                             (((x) & 0x00002000) >> 13)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_SHORTINP_SET(x)                             (((x) << 13) & 0x00002000)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_LP_MSB                                                              14
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_LP_LSB                                                              14
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_LP_MASK                                                     0x00004000
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_LP_GET(x)                                   (((x) & 0x00004000) >> 14)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_LP_SET(x)                                   (((x) << 14) & 0x00004000)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO2G_MSB                                                              15
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO2G_LSB                                                              15
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO2G_MASK                                                     0x00008000
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO2G_GET(x)                                   (((x) & 0x00008000) >> 15)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO2G_SET(x)                                   (((x) << 15) & 0x00008000)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR2G_MSB                                                             16
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR2G_LSB                                                             16
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR2G_MASK                                                    0x00010000
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR2G_GET(x)                                  (((x) & 0x00010000) >> 16)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR2G_SET(x)                                  (((x) << 16) & 0x00010000)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA2G_MSB                                                             17
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA2G_LSB                                                             17
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA2G_MASK                                                    0x00020000
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA2G_GET(x)                                  (((x) & 0x00020000) >> 17)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA2G_SET(x)                                  (((x) << 17) & 0x00020000)
+#define PHY_ANALOG_RXRF_GAINSTAGES_MXR5G_GAIN_OVR_MSB                                                        19
+#define PHY_ANALOG_RXRF_GAINSTAGES_MXR5G_GAIN_OVR_LSB                                                        18
+#define PHY_ANALOG_RXRF_GAINSTAGES_MXR5G_GAIN_OVR_MASK                                               0x000c0000
+#define PHY_ANALOG_RXRF_GAINSTAGES_MXR5G_GAIN_OVR_GET(x)                             (((x) & 0x000c0000) >> 18)
+#define PHY_ANALOG_RXRF_GAINSTAGES_MXR5G_GAIN_OVR_SET(x)                             (((x) << 18) & 0x000c0000)
+#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_GAIN_OVR_MSB                                                        22
+#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_GAIN_OVR_LSB                                                        20
+#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_GAIN_OVR_MASK                                               0x00700000
+#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_GAIN_OVR_GET(x)                             (((x) & 0x00700000) >> 20)
+#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_GAIN_OVR_SET(x)                             (((x) << 20) & 0x00700000)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_MSB                                                        25
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_LSB                                                        23
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_MASK                                               0x03800000
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_GET(x)                             (((x) & 0x03800000) >> 23)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_SET(x)                             (((x) << 23) & 0x03800000)
+#define PHY_ANALOG_RXRF_GAINSTAGES_MXR2G_GAIN_OVR_MSB                                                        27
+#define PHY_ANALOG_RXRF_GAINSTAGES_MXR2G_GAIN_OVR_LSB                                                        26
+#define PHY_ANALOG_RXRF_GAINSTAGES_MXR2G_GAIN_OVR_MASK                                               0x0c000000
+#define PHY_ANALOG_RXRF_GAINSTAGES_MXR2G_GAIN_OVR_GET(x)                             (((x) & 0x0c000000) >> 26)
+#define PHY_ANALOG_RXRF_GAINSTAGES_MXR2G_GAIN_OVR_SET(x)                             (((x) << 26) & 0x0c000000)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_MSB                                                        30
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_LSB                                                        28
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_MASK                                               0x70000000
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_GET(x)                             (((x) & 0x70000000) >> 28)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_SET(x)                             (((x) << 28) & 0x70000000)
+#define PHY_ANALOG_RXRF_GAINSTAGES_RX_OVERRIDE_MSB                                                           31
+#define PHY_ANALOG_RXRF_GAINSTAGES_RX_OVERRIDE_LSB                                                           31
+#define PHY_ANALOG_RXRF_GAINSTAGES_RX_OVERRIDE_MASK                                                  0x80000000
+#define PHY_ANALOG_RXRF_GAINSTAGES_RX_OVERRIDE_GET(x)                                (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_RXRF_GAINSTAGES_RX_OVERRIDE_SET(x)                                (((x) << 31) & 0x80000000)
+
+/* macros for RXRF_AGC */
+#define PHY_ANALOG_RXRF_AGC_ADDRESS                                                                  0x0000000c
+#define PHY_ANALOG_RXRF_AGC_OFFSET                                                                   0x0000000c
+#define PHY_ANALOG_RXRF_AGC_SPARE_MSB                                                                         5
+#define PHY_ANALOG_RXRF_AGC_SPARE_LSB                                                                         0
+#define PHY_ANALOG_RXRF_AGC_SPARE_MASK                                                               0x0000003f
+#define PHY_ANALOG_RXRF_AGC_SPARE_GET(x)                                              (((x) & 0x0000003f) >> 0)
+#define PHY_ANALOG_RXRF_AGC_SPARE_SET(x)                                              (((x) << 0) & 0x0000003f)
+#define PHY_ANALOG_RXRF_AGC_AGC_FALL_CTRL_MSB                                                                 8
+#define PHY_ANALOG_RXRF_AGC_AGC_FALL_CTRL_LSB                                                                 6
+#define PHY_ANALOG_RXRF_AGC_AGC_FALL_CTRL_MASK                                                       0x000001c0
+#define PHY_ANALOG_RXRF_AGC_AGC_FALL_CTRL_GET(x)                                      (((x) & 0x000001c0) >> 6)
+#define PHY_ANALOG_RXRF_AGC_AGC_FALL_CTRL_SET(x)                                      (((x) << 6) & 0x000001c0)
+#define PHY_ANALOG_RXRF_AGC_AGC5G_CALDAC_OVR_MSB                                                             14
+#define PHY_ANALOG_RXRF_AGC_AGC5G_CALDAC_OVR_LSB                                                              9
+#define PHY_ANALOG_RXRF_AGC_AGC5G_CALDAC_OVR_MASK                                                    0x00007e00
+#define PHY_ANALOG_RXRF_AGC_AGC5G_CALDAC_OVR_GET(x)                                   (((x) & 0x00007e00) >> 9)
+#define PHY_ANALOG_RXRF_AGC_AGC5G_CALDAC_OVR_SET(x)                                   (((x) << 9) & 0x00007e00)
+#define PHY_ANALOG_RXRF_AGC_AGC5G_DBDAC_OVR_MSB                                                              18
+#define PHY_ANALOG_RXRF_AGC_AGC5G_DBDAC_OVR_LSB                                                              15
+#define PHY_ANALOG_RXRF_AGC_AGC5G_DBDAC_OVR_MASK                                                     0x00078000
+#define PHY_ANALOG_RXRF_AGC_AGC5G_DBDAC_OVR_GET(x)                                   (((x) & 0x00078000) >> 15)
+#define PHY_ANALOG_RXRF_AGC_AGC5G_DBDAC_OVR_SET(x)                                   (((x) << 15) & 0x00078000)
+#define PHY_ANALOG_RXRF_AGC_AGC2G_CALDAC_OVR_MSB                                                             24
+#define PHY_ANALOG_RXRF_AGC_AGC2G_CALDAC_OVR_LSB                                                             19
+#define PHY_ANALOG_RXRF_AGC_AGC2G_CALDAC_OVR_MASK                                                    0x01f80000
+#define PHY_ANALOG_RXRF_AGC_AGC2G_CALDAC_OVR_GET(x)                                  (((x) & 0x01f80000) >> 19)
+#define PHY_ANALOG_RXRF_AGC_AGC2G_CALDAC_OVR_SET(x)                                  (((x) << 19) & 0x01f80000)
+#define PHY_ANALOG_RXRF_AGC_AGC2G_DBDAC_OVR_MSB                                                              28
+#define PHY_ANALOG_RXRF_AGC_AGC2G_DBDAC_OVR_LSB                                                              25
+#define PHY_ANALOG_RXRF_AGC_AGC2G_DBDAC_OVR_MASK                                                     0x1e000000
+#define PHY_ANALOG_RXRF_AGC_AGC2G_DBDAC_OVR_GET(x)                                   (((x) & 0x1e000000) >> 25)
+#define PHY_ANALOG_RXRF_AGC_AGC2G_DBDAC_OVR_SET(x)                                   (((x) << 25) & 0x1e000000)
+#define PHY_ANALOG_RXRF_AGC_AGC_CAL_OVR_MSB                                                                  29
+#define PHY_ANALOG_RXRF_AGC_AGC_CAL_OVR_LSB                                                                  29
+#define PHY_ANALOG_RXRF_AGC_AGC_CAL_OVR_MASK                                                         0x20000000
+#define PHY_ANALOG_RXRF_AGC_AGC_CAL_OVR_GET(x)                                       (((x) & 0x20000000) >> 29)
+#define PHY_ANALOG_RXRF_AGC_AGC_CAL_OVR_SET(x)                                       (((x) << 29) & 0x20000000)
+#define PHY_ANALOG_RXRF_AGC_AGC_ON_OVR_MSB                                                                   30
+#define PHY_ANALOG_RXRF_AGC_AGC_ON_OVR_LSB                                                                   30
+#define PHY_ANALOG_RXRF_AGC_AGC_ON_OVR_MASK                                                          0x40000000
+#define PHY_ANALOG_RXRF_AGC_AGC_ON_OVR_GET(x)                                        (((x) & 0x40000000) >> 30)
+#define PHY_ANALOG_RXRF_AGC_AGC_ON_OVR_SET(x)                                        (((x) << 30) & 0x40000000)
+#define PHY_ANALOG_RXRF_AGC_AGC_OVERRIDE_MSB                                                                 31
+#define PHY_ANALOG_RXRF_AGC_AGC_OVERRIDE_LSB                                                                 31
+#define PHY_ANALOG_RXRF_AGC_AGC_OVERRIDE_MASK                                                        0x80000000
+#define PHY_ANALOG_RXRF_AGC_AGC_OVERRIDE_GET(x)                                      (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_RXRF_AGC_AGC_OVERRIDE_SET(x)                                      (((x) << 31) & 0x80000000)
+
+/* macros for TXRF1 */
+#define PHY_ANALOG_TXRF1_ADDRESS                                                                     0x00000040
+#define PHY_ANALOG_TXRF1_OFFSET                                                                      0x00000040
+#define PHY_ANALOG_TXRF1_DCAS2G_MSB                                                                           2
+#define PHY_ANALOG_TXRF1_DCAS2G_LSB                                                                           0
+#define PHY_ANALOG_TXRF1_DCAS2G_MASK                                                                 0x00000007
+#define PHY_ANALOG_TXRF1_DCAS2G_GET(x)                                                (((x) & 0x00000007) >> 0)
+#define PHY_ANALOG_TXRF1_DCAS2G_SET(x)                                                (((x) << 0) & 0x00000007)
+#define PHY_ANALOG_TXRF1_OB2G_PALOFF_MSB                                                                      5
+#define PHY_ANALOG_TXRF1_OB2G_PALOFF_LSB                                                                      3
+#define PHY_ANALOG_TXRF1_OB2G_PALOFF_MASK                                                            0x00000038
+#define PHY_ANALOG_TXRF1_OB2G_PALOFF_GET(x)                                           (((x) & 0x00000038) >> 3)
+#define PHY_ANALOG_TXRF1_OB2G_PALOFF_SET(x)                                           (((x) << 3) & 0x00000038)
+#define PHY_ANALOG_TXRF1_OB2G_QAM_MSB                                                                         8
+#define PHY_ANALOG_TXRF1_OB2G_QAM_LSB                                                                         6
+#define PHY_ANALOG_TXRF1_OB2G_QAM_MASK                                                               0x000001c0
+#define PHY_ANALOG_TXRF1_OB2G_QAM_GET(x)                                              (((x) & 0x000001c0) >> 6)
+#define PHY_ANALOG_TXRF1_OB2G_QAM_SET(x)                                              (((x) << 6) & 0x000001c0)
+#define PHY_ANALOG_TXRF1_OB2G_PSK_MSB                                                                        11
+#define PHY_ANALOG_TXRF1_OB2G_PSK_LSB                                                                         9
+#define PHY_ANALOG_TXRF1_OB2G_PSK_MASK                                                               0x00000e00
+#define PHY_ANALOG_TXRF1_OB2G_PSK_GET(x)                                              (((x) & 0x00000e00) >> 9)
+#define PHY_ANALOG_TXRF1_OB2G_PSK_SET(x)                                              (((x) << 9) & 0x00000e00)
+#define PHY_ANALOG_TXRF1_OB2G_CCK_MSB                                                                        14
+#define PHY_ANALOG_TXRF1_OB2G_CCK_LSB                                                                        12
+#define PHY_ANALOG_TXRF1_OB2G_CCK_MASK                                                               0x00007000
+#define PHY_ANALOG_TXRF1_OB2G_CCK_GET(x)                                             (((x) & 0x00007000) >> 12)
+#define PHY_ANALOG_TXRF1_OB2G_CCK_SET(x)                                             (((x) << 12) & 0x00007000)
+#define PHY_ANALOG_TXRF1_DB2G_MSB                                                                            17
+#define PHY_ANALOG_TXRF1_DB2G_LSB                                                                            15
+#define PHY_ANALOG_TXRF1_DB2G_MASK                                                                   0x00038000
+#define PHY_ANALOG_TXRF1_DB2G_GET(x)                                                 (((x) & 0x00038000) >> 15)
+#define PHY_ANALOG_TXRF1_DB2G_SET(x)                                                 (((x) << 15) & 0x00038000)
+#define PHY_ANALOG_TXRF1_PDOUT2G_MSB                                                                         18
+#define PHY_ANALOG_TXRF1_PDOUT2G_LSB                                                                         18
+#define PHY_ANALOG_TXRF1_PDOUT2G_MASK                                                                0x00040000
+#define PHY_ANALOG_TXRF1_PDOUT2G_GET(x)                                              (((x) & 0x00040000) >> 18)
+#define PHY_ANALOG_TXRF1_PDOUT2G_SET(x)                                              (((x) << 18) & 0x00040000)
+#define PHY_ANALOG_TXRF1_PDDR2G_MSB                                                                          19
+#define PHY_ANALOG_TXRF1_PDDR2G_LSB                                                                          19
+#define PHY_ANALOG_TXRF1_PDDR2G_MASK                                                                 0x00080000
+#define PHY_ANALOG_TXRF1_PDDR2G_GET(x)                                               (((x) & 0x00080000) >> 19)
+#define PHY_ANALOG_TXRF1_PDDR2G_SET(x)                                               (((x) << 19) & 0x00080000)
+#define PHY_ANALOG_TXRF1_PDMXR2G_MSB                                                                         20
+#define PHY_ANALOG_TXRF1_PDMXR2G_LSB                                                                         20
+#define PHY_ANALOG_TXRF1_PDMXR2G_MASK                                                                0x00100000
+#define PHY_ANALOG_TXRF1_PDMXR2G_GET(x)                                              (((x) & 0x00100000) >> 20)
+#define PHY_ANALOG_TXRF1_PDMXR2G_SET(x)                                              (((x) << 20) & 0x00100000)
+#define PHY_ANALOG_TXRF1_PDLO2G_MSB                                                                          21
+#define PHY_ANALOG_TXRF1_PDLO2G_LSB                                                                          21
+#define PHY_ANALOG_TXRF1_PDLO2G_MASK                                                                 0x00200000
+#define PHY_ANALOG_TXRF1_PDLO2G_GET(x)                                               (((x) & 0x00200000) >> 21)
+#define PHY_ANALOG_TXRF1_PDLO2G_SET(x)                                               (((x) << 21) & 0x00200000)
+#define PHY_ANALOG_TXRF1_LOBUF2GFORCED_MSB                                                                   22
+#define PHY_ANALOG_TXRF1_LOBUF2GFORCED_LSB                                                                   22
+#define PHY_ANALOG_TXRF1_LOBUF2GFORCED_MASK                                                          0x00400000
+#define PHY_ANALOG_TXRF1_LOBUF2GFORCED_GET(x)                                        (((x) & 0x00400000) >> 22)
+#define PHY_ANALOG_TXRF1_LOBUF2GFORCED_SET(x)                                        (((x) << 22) & 0x00400000)
+#define PHY_ANALOG_TXRF1_LODIV2GFORCED_MSB                                                                   23
+#define PHY_ANALOG_TXRF1_LODIV2GFORCED_LSB                                                                   23
+#define PHY_ANALOG_TXRF1_LODIV2GFORCED_MASK                                                          0x00800000
+#define PHY_ANALOG_TXRF1_LODIV2GFORCED_GET(x)                                        (((x) & 0x00800000) >> 23)
+#define PHY_ANALOG_TXRF1_LODIV2GFORCED_SET(x)                                        (((x) << 23) & 0x00800000)
+#define PHY_ANALOG_TXRF1_PADRVGN2G_MSB                                                                       30
+#define PHY_ANALOG_TXRF1_PADRVGN2G_LSB                                                                       24
+#define PHY_ANALOG_TXRF1_PADRVGN2G_MASK                                                              0x7f000000
+#define PHY_ANALOG_TXRF1_PADRVGN2G_GET(x)                                            (((x) & 0x7f000000) >> 24)
+#define PHY_ANALOG_TXRF1_PADRVGN2G_SET(x)                                            (((x) << 24) & 0x7f000000)
+#define PHY_ANALOG_TXRF1_LOCALTXGAIN2G_MSB                                                                   31
+#define PHY_ANALOG_TXRF1_LOCALTXGAIN2G_LSB                                                                   31
+#define PHY_ANALOG_TXRF1_LOCALTXGAIN2G_MASK                                                          0x80000000
+#define PHY_ANALOG_TXRF1_LOCALTXGAIN2G_GET(x)                                        (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_TXRF1_LOCALTXGAIN2G_SET(x)                                        (((x) << 31) & 0x80000000)
+
+/* macros for TXRF2 */
+#define PHY_ANALOG_TXRF2_ADDRESS                                                                     0x00000044
+#define PHY_ANALOG_TXRF2_OFFSET                                                                      0x00000044
+#define PHY_ANALOG_TXRF2_SPARE2_MSB                                                                           0
+#define PHY_ANALOG_TXRF2_SPARE2_LSB                                                                           0
+#define PHY_ANALOG_TXRF2_SPARE2_MASK                                                                 0x00000001
+#define PHY_ANALOG_TXRF2_SPARE2_GET(x)                                                (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_TXRF2_SPARE2_SET(x)                                                (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_TXRF2_D3B5G_MSB                                                                            3
+#define PHY_ANALOG_TXRF2_D3B5G_LSB                                                                            1
+#define PHY_ANALOG_TXRF2_D3B5G_MASK                                                                  0x0000000e
+#define PHY_ANALOG_TXRF2_D3B5G_GET(x)                                                 (((x) & 0x0000000e) >> 1)
+#define PHY_ANALOG_TXRF2_D3B5G_SET(x)                                                 (((x) << 1) & 0x0000000e)
+#define PHY_ANALOG_TXRF2_D4B5G_MSB                                                                            6
+#define PHY_ANALOG_TXRF2_D4B5G_LSB                                                                            4
+#define PHY_ANALOG_TXRF2_D4B5G_MASK                                                                  0x00000070
+#define PHY_ANALOG_TXRF2_D4B5G_GET(x)                                                 (((x) & 0x00000070) >> 4)
+#define PHY_ANALOG_TXRF2_D4B5G_SET(x)                                                 (((x) << 4) & 0x00000070)
+#define PHY_ANALOG_TXRF2_PDOUT5G_MSB                                                                         10
+#define PHY_ANALOG_TXRF2_PDOUT5G_LSB                                                                          7
+#define PHY_ANALOG_TXRF2_PDOUT5G_MASK                                                                0x00000780
+#define PHY_ANALOG_TXRF2_PDOUT5G_GET(x)                                               (((x) & 0x00000780) >> 7)
+#define PHY_ANALOG_TXRF2_PDOUT5G_SET(x)                                               (((x) << 7) & 0x00000780)
+#define PHY_ANALOG_TXRF2_PDMXR5G_MSB                                                                         11
+#define PHY_ANALOG_TXRF2_PDMXR5G_LSB                                                                         11
+#define PHY_ANALOG_TXRF2_PDMXR5G_MASK                                                                0x00000800
+#define PHY_ANALOG_TXRF2_PDMXR5G_GET(x)                                              (((x) & 0x00000800) >> 11)
+#define PHY_ANALOG_TXRF2_PDMXR5G_SET(x)                                              (((x) << 11) & 0x00000800)
+#define PHY_ANALOG_TXRF2_PDLOBUF5G_MSB                                                                       12
+#define PHY_ANALOG_TXRF2_PDLOBUF5G_LSB                                                                       12
+#define PHY_ANALOG_TXRF2_PDLOBUF5G_MASK                                                              0x00001000
+#define PHY_ANALOG_TXRF2_PDLOBUF5G_GET(x)                                            (((x) & 0x00001000) >> 12)
+#define PHY_ANALOG_TXRF2_PDLOBUF5G_SET(x)                                            (((x) << 12) & 0x00001000)
+#define PHY_ANALOG_TXRF2_PDLODIV5G_MSB                                                                       13
+#define PHY_ANALOG_TXRF2_PDLODIV5G_LSB                                                                       13
+#define PHY_ANALOG_TXRF2_PDLODIV5G_MASK                                                              0x00002000
+#define PHY_ANALOG_TXRF2_PDLODIV5G_GET(x)                                            (((x) & 0x00002000) >> 13)
+#define PHY_ANALOG_TXRF2_PDLODIV5G_SET(x)                                            (((x) << 13) & 0x00002000)
+#define PHY_ANALOG_TXRF2_LOBUF5GFORCED_MSB                                                                   14
+#define PHY_ANALOG_TXRF2_LOBUF5GFORCED_LSB                                                                   14
+#define PHY_ANALOG_TXRF2_LOBUF5GFORCED_MASK                                                          0x00004000
+#define PHY_ANALOG_TXRF2_LOBUF5GFORCED_GET(x)                                        (((x) & 0x00004000) >> 14)
+#define PHY_ANALOG_TXRF2_LOBUF5GFORCED_SET(x)                                        (((x) << 14) & 0x00004000)
+#define PHY_ANALOG_TXRF2_LODIV5GFORCED_MSB                                                                   15
+#define PHY_ANALOG_TXRF2_LODIV5GFORCED_LSB                                                                   15
+#define PHY_ANALOG_TXRF2_LODIV5GFORCED_MASK                                                          0x00008000
+#define PHY_ANALOG_TXRF2_LODIV5GFORCED_GET(x)                                        (((x) & 0x00008000) >> 15)
+#define PHY_ANALOG_TXRF2_LODIV5GFORCED_SET(x)                                        (((x) << 15) & 0x00008000)
+#define PHY_ANALOG_TXRF2_PADRV2GN5G_MSB                                                                      19
+#define PHY_ANALOG_TXRF2_PADRV2GN5G_LSB                                                                      16
+#define PHY_ANALOG_TXRF2_PADRV2GN5G_MASK                                                             0x000f0000
+#define PHY_ANALOG_TXRF2_PADRV2GN5G_GET(x)                                           (((x) & 0x000f0000) >> 16)
+#define PHY_ANALOG_TXRF2_PADRV2GN5G_SET(x)                                           (((x) << 16) & 0x000f0000)
+#define PHY_ANALOG_TXRF2_PADRV3GN5G_MSB                                                                      23
+#define PHY_ANALOG_TXRF2_PADRV3GN5G_LSB                                                                      20
+#define PHY_ANALOG_TXRF2_PADRV3GN5G_MASK                                                             0x00f00000
+#define PHY_ANALOG_TXRF2_PADRV3GN5G_GET(x)                                           (((x) & 0x00f00000) >> 20)
+#define PHY_ANALOG_TXRF2_PADRV3GN5G_SET(x)                                           (((x) << 20) & 0x00f00000)
+#define PHY_ANALOG_TXRF2_PADRV4GN5G_MSB                                                                      27
+#define PHY_ANALOG_TXRF2_PADRV4GN5G_LSB                                                                      24
+#define PHY_ANALOG_TXRF2_PADRV4GN5G_MASK                                                             0x0f000000
+#define PHY_ANALOG_TXRF2_PADRV4GN5G_GET(x)                                           (((x) & 0x0f000000) >> 24)
+#define PHY_ANALOG_TXRF2_PADRV4GN5G_SET(x)                                           (((x) << 24) & 0x0f000000)
+#define PHY_ANALOG_TXRF2_LOCALTXGAIN5G_MSB                                                                   28
+#define PHY_ANALOG_TXRF2_LOCALTXGAIN5G_LSB                                                                   28
+#define PHY_ANALOG_TXRF2_LOCALTXGAIN5G_MASK                                                          0x10000000
+#define PHY_ANALOG_TXRF2_LOCALTXGAIN5G_GET(x)                                        (((x) & 0x10000000) >> 28)
+#define PHY_ANALOG_TXRF2_LOCALTXGAIN5G_SET(x)                                        (((x) << 28) & 0x10000000)
+#define PHY_ANALOG_TXRF2_OCAS2G_MSB                                                                          31
+#define PHY_ANALOG_TXRF2_OCAS2G_LSB                                                                          29
+#define PHY_ANALOG_TXRF2_OCAS2G_MASK                                                                 0xe0000000
+#define PHY_ANALOG_TXRF2_OCAS2G_GET(x)                                               (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_TXRF2_OCAS2G_SET(x)                                               (((x) << 29) & 0xe0000000)
+
+/* macros for TXRF3 */
+#define PHY_ANALOG_TXRF3_ADDRESS                                                                     0x00000048
+#define PHY_ANALOG_TXRF3_OFFSET                                                                      0x00000048
+#define PHY_ANALOG_TXRF3_SPARE3_MSB                                                                          22
+#define PHY_ANALOG_TXRF3_SPARE3_LSB                                                                           0
+#define PHY_ANALOG_TXRF3_SPARE3_MASK                                                                 0x007fffff
+#define PHY_ANALOG_TXRF3_SPARE3_GET(x)                                                (((x) & 0x007fffff) >> 0)
+#define PHY_ANALOG_TXRF3_SPARE3_SET(x)                                                (((x) << 0) & 0x007fffff)
+#define PHY_ANALOG_TXRF3_CAS5G_MSB                                                                           25
+#define PHY_ANALOG_TXRF3_CAS5G_LSB                                                                           23
+#define PHY_ANALOG_TXRF3_CAS5G_MASK                                                                  0x03800000
+#define PHY_ANALOG_TXRF3_CAS5G_GET(x)                                                (((x) & 0x03800000) >> 23)
+#define PHY_ANALOG_TXRF3_CAS5G_SET(x)                                                (((x) << 23) & 0x03800000)
+#define PHY_ANALOG_TXRF3_OB5G_MSB                                                                            28
+#define PHY_ANALOG_TXRF3_OB5G_LSB                                                                            26
+#define PHY_ANALOG_TXRF3_OB5G_MASK                                                                   0x1c000000
+#define PHY_ANALOG_TXRF3_OB5G_GET(x)                                                 (((x) & 0x1c000000) >> 26)
+#define PHY_ANALOG_TXRF3_OB5G_SET(x)                                                 (((x) << 26) & 0x1c000000)
+#define PHY_ANALOG_TXRF3_D2B5G_MSB                                                                           31
+#define PHY_ANALOG_TXRF3_D2B5G_LSB                                                                           29
+#define PHY_ANALOG_TXRF3_D2B5G_MASK                                                                  0xe0000000
+#define PHY_ANALOG_TXRF3_D2B5G_GET(x)                                                (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_TXRF3_D2B5G_SET(x)                                                (((x) << 29) & 0xe0000000)
+
+/* macros for TXRF4 */
+#define PHY_ANALOG_TXRF4_ADDRESS                                                                     0x0000004c
+#define PHY_ANALOG_TXRF4_OFFSET                                                                      0x0000004c
+#define PHY_ANALOG_TXRF4_COMP2G_PSK_MSB                                                                       2
+#define PHY_ANALOG_TXRF4_COMP2G_PSK_LSB                                                                       0
+#define PHY_ANALOG_TXRF4_COMP2G_PSK_MASK                                                             0x00000007
+#define PHY_ANALOG_TXRF4_COMP2G_PSK_GET(x)                                            (((x) & 0x00000007) >> 0)
+#define PHY_ANALOG_TXRF4_COMP2G_PSK_SET(x)                                            (((x) << 0) & 0x00000007)
+#define PHY_ANALOG_TXRF4_COMP2G_CCK_MSB                                                                       5
+#define PHY_ANALOG_TXRF4_COMP2G_CCK_LSB                                                                       3
+#define PHY_ANALOG_TXRF4_COMP2G_CCK_MASK                                                             0x00000038
+#define PHY_ANALOG_TXRF4_COMP2G_CCK_GET(x)                                            (((x) & 0x00000038) >> 3)
+#define PHY_ANALOG_TXRF4_COMP2G_CCK_SET(x)                                            (((x) << 3) & 0x00000038)
+#define PHY_ANALOG_TXRF4_AMP2B2G_QAM_MSB                                                                      8
+#define PHY_ANALOG_TXRF4_AMP2B2G_QAM_LSB                                                                      6
+#define PHY_ANALOG_TXRF4_AMP2B2G_QAM_MASK                                                            0x000001c0
+#define PHY_ANALOG_TXRF4_AMP2B2G_QAM_GET(x)                                           (((x) & 0x000001c0) >> 6)
+#define PHY_ANALOG_TXRF4_AMP2B2G_QAM_SET(x)                                           (((x) << 6) & 0x000001c0)
+#define PHY_ANALOG_TXRF4_AMP2B2G_PSK_MSB                                                                     11
+#define PHY_ANALOG_TXRF4_AMP2B2G_PSK_LSB                                                                      9
+#define PHY_ANALOG_TXRF4_AMP2B2G_PSK_MASK                                                            0x00000e00
+#define PHY_ANALOG_TXRF4_AMP2B2G_PSK_GET(x)                                           (((x) & 0x00000e00) >> 9)
+#define PHY_ANALOG_TXRF4_AMP2B2G_PSK_SET(x)                                           (((x) << 9) & 0x00000e00)
+#define PHY_ANALOG_TXRF4_AMP2B2G_CCK_MSB                                                                     14
+#define PHY_ANALOG_TXRF4_AMP2B2G_CCK_LSB                                                                     12
+#define PHY_ANALOG_TXRF4_AMP2B2G_CCK_MASK                                                            0x00007000
+#define PHY_ANALOG_TXRF4_AMP2B2G_CCK_GET(x)                                          (((x) & 0x00007000) >> 12)
+#define PHY_ANALOG_TXRF4_AMP2B2G_CCK_SET(x)                                          (((x) << 12) & 0x00007000)
+#define PHY_ANALOG_TXRF4_AMP2CAS2G_MSB                                                                       17
+#define PHY_ANALOG_TXRF4_AMP2CAS2G_LSB                                                                       15
+#define PHY_ANALOG_TXRF4_AMP2CAS2G_MASK                                                              0x00038000
+#define PHY_ANALOG_TXRF4_AMP2CAS2G_GET(x)                                            (((x) & 0x00038000) >> 15)
+#define PHY_ANALOG_TXRF4_AMP2CAS2G_SET(x)                                            (((x) << 15) & 0x00038000)
+#define PHY_ANALOG_TXRF4_FILTR2G_MSB                                                                         19
+#define PHY_ANALOG_TXRF4_FILTR2G_LSB                                                                         18
+#define PHY_ANALOG_TXRF4_FILTR2G_MASK                                                                0x000c0000
+#define PHY_ANALOG_TXRF4_FILTR2G_GET(x)                                              (((x) & 0x000c0000) >> 18)
+#define PHY_ANALOG_TXRF4_FILTR2G_SET(x)                                              (((x) << 18) & 0x000c0000)
+#define PHY_ANALOG_TXRF4_PWDFB2_2G_MSB                                                                       20
+#define PHY_ANALOG_TXRF4_PWDFB2_2G_LSB                                                                       20
+#define PHY_ANALOG_TXRF4_PWDFB2_2G_MASK                                                              0x00100000
+#define PHY_ANALOG_TXRF4_PWDFB2_2G_GET(x)                                            (((x) & 0x00100000) >> 20)
+#define PHY_ANALOG_TXRF4_PWDFB2_2G_SET(x)                                            (((x) << 20) & 0x00100000)
+#define PHY_ANALOG_TXRF4_PWDFB1_2G_MSB                                                                       21
+#define PHY_ANALOG_TXRF4_PWDFB1_2G_LSB                                                                       21
+#define PHY_ANALOG_TXRF4_PWDFB1_2G_MASK                                                              0x00200000
+#define PHY_ANALOG_TXRF4_PWDFB1_2G_GET(x)                                            (((x) & 0x00200000) >> 21)
+#define PHY_ANALOG_TXRF4_PWDFB1_2G_SET(x)                                            (((x) << 21) & 0x00200000)
+#define PHY_ANALOG_TXRF4_PDFB2G_MSB                                                                          22
+#define PHY_ANALOG_TXRF4_PDFB2G_LSB                                                                          22
+#define PHY_ANALOG_TXRF4_PDFB2G_MASK                                                                 0x00400000
+#define PHY_ANALOG_TXRF4_PDFB2G_GET(x)                                               (((x) & 0x00400000) >> 22)
+#define PHY_ANALOG_TXRF4_PDFB2G_SET(x)                                               (((x) << 22) & 0x00400000)
+#define PHY_ANALOG_TXRF4_RDIV5G_MSB                                                                          24
+#define PHY_ANALOG_TXRF4_RDIV5G_LSB                                                                          23
+#define PHY_ANALOG_TXRF4_RDIV5G_MASK                                                                 0x01800000
+#define PHY_ANALOG_TXRF4_RDIV5G_GET(x)                                               (((x) & 0x01800000) >> 23)
+#define PHY_ANALOG_TXRF4_RDIV5G_SET(x)                                               (((x) << 23) & 0x01800000)
+#define PHY_ANALOG_TXRF4_CAPDIV5G_MSB                                                                        27
+#define PHY_ANALOG_TXRF4_CAPDIV5G_LSB                                                                        25
+#define PHY_ANALOG_TXRF4_CAPDIV5G_MASK                                                               0x0e000000
+#define PHY_ANALOG_TXRF4_CAPDIV5G_GET(x)                                             (((x) & 0x0e000000) >> 25)
+#define PHY_ANALOG_TXRF4_CAPDIV5G_SET(x)                                             (((x) << 25) & 0x0e000000)
+#define PHY_ANALOG_TXRF4_PDPREDIST5G_MSB                                                                     28
+#define PHY_ANALOG_TXRF4_PDPREDIST5G_LSB                                                                     28
+#define PHY_ANALOG_TXRF4_PDPREDIST5G_MASK                                                            0x10000000
+#define PHY_ANALOG_TXRF4_PDPREDIST5G_GET(x)                                          (((x) & 0x10000000) >> 28)
+#define PHY_ANALOG_TXRF4_PDPREDIST5G_SET(x)                                          (((x) << 28) & 0x10000000)
+#define PHY_ANALOG_TXRF4_RDIV2G_MSB                                                                          30
+#define PHY_ANALOG_TXRF4_RDIV2G_LSB                                                                          29
+#define PHY_ANALOG_TXRF4_RDIV2G_MASK                                                                 0x60000000
+#define PHY_ANALOG_TXRF4_RDIV2G_GET(x)                                               (((x) & 0x60000000) >> 29)
+#define PHY_ANALOG_TXRF4_RDIV2G_SET(x)                                               (((x) << 29) & 0x60000000)
+#define PHY_ANALOG_TXRF4_PDPREDIST2G_MSB                                                                     31
+#define PHY_ANALOG_TXRF4_PDPREDIST2G_LSB                                                                     31
+#define PHY_ANALOG_TXRF4_PDPREDIST2G_MASK                                                            0x80000000
+#define PHY_ANALOG_TXRF4_PDPREDIST2G_GET(x)                                          (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_TXRF4_PDPREDIST2G_SET(x)                                          (((x) << 31) & 0x80000000)
+
+/* macros for TXRF5 */
+#define PHY_ANALOG_TXRF5_ADDRESS                                                                     0x00000050
+#define PHY_ANALOG_TXRF5_OFFSET                                                                      0x00000050
+#define PHY_ANALOG_TXRF5_FBHI2G_MSB                                                                           0
+#define PHY_ANALOG_TXRF5_FBHI2G_LSB                                                                           0
+#define PHY_ANALOG_TXRF5_FBHI2G_MASK                                                                 0x00000001
+#define PHY_ANALOG_TXRF5_FBHI2G_GET(x)                                                (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_TXRF5_FBLO2G_MSB                                                                           1
+#define PHY_ANALOG_TXRF5_FBLO2G_LSB                                                                           1
+#define PHY_ANALOG_TXRF5_FBLO2G_MASK                                                                 0x00000002
+#define PHY_ANALOG_TXRF5_FBLO2G_GET(x)                                                (((x) & 0x00000002) >> 1)
+#define PHY_ANALOG_TXRF5_REFHI2G_MSB                                                                          4
+#define PHY_ANALOG_TXRF5_REFHI2G_LSB                                                                          2
+#define PHY_ANALOG_TXRF5_REFHI2G_MASK                                                                0x0000001c
+#define PHY_ANALOG_TXRF5_REFHI2G_GET(x)                                               (((x) & 0x0000001c) >> 2)
+#define PHY_ANALOG_TXRF5_REFHI2G_SET(x)                                               (((x) << 2) & 0x0000001c)
+#define PHY_ANALOG_TXRF5_REFLO2G_MSB                                                                          7
+#define PHY_ANALOG_TXRF5_REFLO2G_LSB                                                                          5
+#define PHY_ANALOG_TXRF5_REFLO2G_MASK                                                                0x000000e0
+#define PHY_ANALOG_TXRF5_REFLO2G_GET(x)                                               (((x) & 0x000000e0) >> 5)
+#define PHY_ANALOG_TXRF5_REFLO2G_SET(x)                                               (((x) << 5) & 0x000000e0)
+#define PHY_ANALOG_TXRF5_PK2B2G_QAM_MSB                                                                       9
+#define PHY_ANALOG_TXRF5_PK2B2G_QAM_LSB                                                                       8
+#define PHY_ANALOG_TXRF5_PK2B2G_QAM_MASK                                                             0x00000300
+#define PHY_ANALOG_TXRF5_PK2B2G_QAM_GET(x)                                            (((x) & 0x00000300) >> 8)
+#define PHY_ANALOG_TXRF5_PK2B2G_QAM_SET(x)                                            (((x) << 8) & 0x00000300)
+#define PHY_ANALOG_TXRF5_PK2B2G_PSK_MSB                                                                      11
+#define PHY_ANALOG_TXRF5_PK2B2G_PSK_LSB                                                                      10
+#define PHY_ANALOG_TXRF5_PK2B2G_PSK_MASK                                                             0x00000c00
+#define PHY_ANALOG_TXRF5_PK2B2G_PSK_GET(x)                                           (((x) & 0x00000c00) >> 10)
+#define PHY_ANALOG_TXRF5_PK2B2G_PSK_SET(x)                                           (((x) << 10) & 0x00000c00)
+#define PHY_ANALOG_TXRF5_PK2B2G_CCK_MSB                                                                      13
+#define PHY_ANALOG_TXRF5_PK2B2G_CCK_LSB                                                                      12
+#define PHY_ANALOG_TXRF5_PK2B2G_CCK_MASK                                                             0x00003000
+#define PHY_ANALOG_TXRF5_PK2B2G_CCK_GET(x)                                           (((x) & 0x00003000) >> 12)
+#define PHY_ANALOG_TXRF5_PK2B2G_CCK_SET(x)                                           (((x) << 12) & 0x00003000)
+#define PHY_ANALOG_TXRF5_PK1B2G_QAM_MSB                                                                      15
+#define PHY_ANALOG_TXRF5_PK1B2G_QAM_LSB                                                                      14
+#define PHY_ANALOG_TXRF5_PK1B2G_QAM_MASK                                                             0x0000c000
+#define PHY_ANALOG_TXRF5_PK1B2G_QAM_GET(x)                                           (((x) & 0x0000c000) >> 14)
+#define PHY_ANALOG_TXRF5_PK1B2G_QAM_SET(x)                                           (((x) << 14) & 0x0000c000)
+#define PHY_ANALOG_TXRF5_PK1B2G_PSK_MSB                                                                      17
+#define PHY_ANALOG_TXRF5_PK1B2G_PSK_LSB                                                                      16
+#define PHY_ANALOG_TXRF5_PK1B2G_PSK_MASK                                                             0x00030000
+#define PHY_ANALOG_TXRF5_PK1B2G_PSK_GET(x)                                           (((x) & 0x00030000) >> 16)
+#define PHY_ANALOG_TXRF5_PK1B2G_PSK_SET(x)                                           (((x) << 16) & 0x00030000)
+#define PHY_ANALOG_TXRF5_PK1B2G_CCK_MSB                                                                      19
+#define PHY_ANALOG_TXRF5_PK1B2G_CCK_LSB                                                                      18
+#define PHY_ANALOG_TXRF5_PK1B2G_CCK_MASK                                                             0x000c0000
+#define PHY_ANALOG_TXRF5_PK1B2G_CCK_GET(x)                                           (((x) & 0x000c0000) >> 18)
+#define PHY_ANALOG_TXRF5_PK1B2G_CCK_SET(x)                                           (((x) << 18) & 0x000c0000)
+#define PHY_ANALOG_TXRF5_MIOB2G_QAM_MSB                                                                      22
+#define PHY_ANALOG_TXRF5_MIOB2G_QAM_LSB                                                                      20
+#define PHY_ANALOG_TXRF5_MIOB2G_QAM_MASK                                                             0x00700000
+#define PHY_ANALOG_TXRF5_MIOB2G_QAM_GET(x)                                           (((x) & 0x00700000) >> 20)
+#define PHY_ANALOG_TXRF5_MIOB2G_QAM_SET(x)                                           (((x) << 20) & 0x00700000)
+#define PHY_ANALOG_TXRF5_MIOB2G_PSK_MSB                                                                      25
+#define PHY_ANALOG_TXRF5_MIOB2G_PSK_LSB                                                                      23
+#define PHY_ANALOG_TXRF5_MIOB2G_PSK_MASK                                                             0x03800000
+#define PHY_ANALOG_TXRF5_MIOB2G_PSK_GET(x)                                           (((x) & 0x03800000) >> 23)
+#define PHY_ANALOG_TXRF5_MIOB2G_PSK_SET(x)                                           (((x) << 23) & 0x03800000)
+#define PHY_ANALOG_TXRF5_MIOB2G_CCK_MSB                                                                      28
+#define PHY_ANALOG_TXRF5_MIOB2G_CCK_LSB                                                                      26
+#define PHY_ANALOG_TXRF5_MIOB2G_CCK_MASK                                                             0x1c000000
+#define PHY_ANALOG_TXRF5_MIOB2G_CCK_GET(x)                                           (((x) & 0x1c000000) >> 26)
+#define PHY_ANALOG_TXRF5_MIOB2G_CCK_SET(x)                                           (((x) << 26) & 0x1c000000)
+#define PHY_ANALOG_TXRF5_COMP2G_QAM_MSB                                                                      31
+#define PHY_ANALOG_TXRF5_COMP2G_QAM_LSB                                                                      29
+#define PHY_ANALOG_TXRF5_COMP2G_QAM_MASK                                                             0xe0000000
+#define PHY_ANALOG_TXRF5_COMP2G_QAM_GET(x)                                           (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_TXRF5_COMP2G_QAM_SET(x)                                           (((x) << 29) & 0xe0000000)
+
+/* macros for TXRF6 */
+#define PHY_ANALOG_TXRF6_ADDRESS                                                                     0x00000054
+#define PHY_ANALOG_TXRF6_OFFSET                                                                      0x00000054
+#define PHY_ANALOG_TXRF6_SPARE6_MSB                                                                           0
+#define PHY_ANALOG_TXRF6_SPARE6_LSB                                                                           0
+#define PHY_ANALOG_TXRF6_SPARE6_MASK                                                                 0x00000001
+#define PHY_ANALOG_TXRF6_SPARE6_GET(x)                                                (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_TXRF6_SPARE6_SET(x)                                                (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_TXRF6_PAL_LOCKED_MSB                                                                       1
+#define PHY_ANALOG_TXRF6_PAL_LOCKED_LSB                                                                       1
+#define PHY_ANALOG_TXRF6_PAL_LOCKED_MASK                                                             0x00000002
+#define PHY_ANALOG_TXRF6_PAL_LOCKED_GET(x)                                            (((x) & 0x00000002) >> 1)
+#define PHY_ANALOG_TXRF6_PADRVGN2G_SMOUT_MSB                                                                  7
+#define PHY_ANALOG_TXRF6_PADRVGN2G_SMOUT_LSB                                                                  2
+#define PHY_ANALOG_TXRF6_PADRVGN2G_SMOUT_MASK                                                        0x000000fc
+#define PHY_ANALOG_TXRF6_PADRVGN2G_SMOUT_GET(x)                                       (((x) & 0x000000fc) >> 2)
+#define PHY_ANALOG_TXRF6_GAINSTEP2G_MSB                                                                      10
+#define PHY_ANALOG_TXRF6_GAINSTEP2G_LSB                                                                       8
+#define PHY_ANALOG_TXRF6_GAINSTEP2G_MASK                                                             0x00000700
+#define PHY_ANALOG_TXRF6_GAINSTEP2G_GET(x)                                            (((x) & 0x00000700) >> 8)
+#define PHY_ANALOG_TXRF6_GAINSTEP2G_SET(x)                                            (((x) << 8) & 0x00000700)
+#define PHY_ANALOG_TXRF6_USE_GAIN_DELTA2G_MSB                                                                11
+#define PHY_ANALOG_TXRF6_USE_GAIN_DELTA2G_LSB                                                                11
+#define PHY_ANALOG_TXRF6_USE_GAIN_DELTA2G_MASK                                                       0x00000800
+#define PHY_ANALOG_TXRF6_USE_GAIN_DELTA2G_GET(x)                                     (((x) & 0x00000800) >> 11)
+#define PHY_ANALOG_TXRF6_USE_GAIN_DELTA2G_SET(x)                                     (((x) << 11) & 0x00000800)
+#define PHY_ANALOG_TXRF6_PADRVGN_INDEX_I2G_MSB                                                               15
+#define PHY_ANALOG_TXRF6_PADRVGN_INDEX_I2G_LSB                                                               12
+#define PHY_ANALOG_TXRF6_PADRVGN_INDEX_I2G_MASK                                                      0x0000f000
+#define PHY_ANALOG_TXRF6_PADRVGN_INDEX_I2G_GET(x)                                    (((x) & 0x0000f000) >> 12)
+#define PHY_ANALOG_TXRF6_PADRVGN_INDEX_I2G_SET(x)                                    (((x) << 12) & 0x0000f000)
+#define PHY_ANALOG_TXRF6_VCMONDELAY2G_MSB                                                                    18
+#define PHY_ANALOG_TXRF6_VCMONDELAY2G_LSB                                                                    16
+#define PHY_ANALOG_TXRF6_VCMONDELAY2G_MASK                                                           0x00070000
+#define PHY_ANALOG_TXRF6_VCMONDELAY2G_GET(x)                                         (((x) & 0x00070000) >> 16)
+#define PHY_ANALOG_TXRF6_VCMONDELAY2G_SET(x)                                         (((x) << 16) & 0x00070000)
+#define PHY_ANALOG_TXRF6_CAPDIV2G_MSB                                                                        21
+#define PHY_ANALOG_TXRF6_CAPDIV2G_LSB                                                                        19
+#define PHY_ANALOG_TXRF6_CAPDIV2G_MASK                                                               0x00380000
+#define PHY_ANALOG_TXRF6_CAPDIV2G_GET(x)                                             (((x) & 0x00380000) >> 19)
+#define PHY_ANALOG_TXRF6_CAPDIV2G_SET(x)                                             (((x) << 19) & 0x00380000)
+#define PHY_ANALOG_TXRF6_CAPDIV2GOVR_MSB                                                                     22
+#define PHY_ANALOG_TXRF6_CAPDIV2GOVR_LSB                                                                     22
+#define PHY_ANALOG_TXRF6_CAPDIV2GOVR_MASK                                                            0x00400000
+#define PHY_ANALOG_TXRF6_CAPDIV2GOVR_GET(x)                                          (((x) & 0x00400000) >> 22)
+#define PHY_ANALOG_TXRF6_CAPDIV2GOVR_SET(x)                                          (((x) << 22) & 0x00400000)
+#define PHY_ANALOG_TXRF6_ENPACAL2G_MSB                                                                       23
+#define PHY_ANALOG_TXRF6_ENPACAL2G_LSB                                                                       23
+#define PHY_ANALOG_TXRF6_ENPACAL2G_MASK                                                              0x00800000
+#define PHY_ANALOG_TXRF6_ENPACAL2G_GET(x)                                            (((x) & 0x00800000) >> 23)
+#define PHY_ANALOG_TXRF6_ENPACAL2G_SET(x)                                            (((x) << 23) & 0x00800000)
+#define PHY_ANALOG_TXRF6_OFFSET2G_MSB                                                                        30
+#define PHY_ANALOG_TXRF6_OFFSET2G_LSB                                                                        24
+#define PHY_ANALOG_TXRF6_OFFSET2G_MASK                                                               0x7f000000
+#define PHY_ANALOG_TXRF6_OFFSET2G_GET(x)                                             (((x) & 0x7f000000) >> 24)
+#define PHY_ANALOG_TXRF6_OFFSET2G_SET(x)                                             (((x) << 24) & 0x7f000000)
+#define PHY_ANALOG_TXRF6_ENOFFSETCAL2G_MSB                                                                   31
+#define PHY_ANALOG_TXRF6_ENOFFSETCAL2G_LSB                                                                   31
+#define PHY_ANALOG_TXRF6_ENOFFSETCAL2G_MASK                                                          0x80000000
+#define PHY_ANALOG_TXRF6_ENOFFSETCAL2G_GET(x)                                        (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_TXRF6_ENOFFSETCAL2G_SET(x)                                        (((x) << 31) & 0x80000000)
+
+/* macros for TXRF7 */
+#define PHY_ANALOG_TXRF7_ADDRESS                                                                     0x00000058
+#define PHY_ANALOG_TXRF7_OFFSET                                                                      0x00000058
+#define PHY_ANALOG_TXRF7_SPARE7_MSB                                                                           1
+#define PHY_ANALOG_TXRF7_SPARE7_LSB                                                                           0
+#define PHY_ANALOG_TXRF7_SPARE7_MASK                                                                 0x00000003
+#define PHY_ANALOG_TXRF7_SPARE7_GET(x)                                                (((x) & 0x00000003) >> 0)
+#define PHY_ANALOG_TXRF7_SPARE7_SET(x)                                                (((x) << 0) & 0x00000003)
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_4_MSB                                                                     7
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_4_LSB                                                                     2
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_4_MASK                                                           0x000000fc
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_4_GET(x)                                          (((x) & 0x000000fc) >> 2)
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_4_SET(x)                                          (((x) << 2) & 0x000000fc)
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_3_MSB                                                                    13
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_3_LSB                                                                     8
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_3_MASK                                                           0x00003f00
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_3_GET(x)                                          (((x) & 0x00003f00) >> 8)
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_3_SET(x)                                          (((x) << 8) & 0x00003f00)
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_2_MSB                                                                    19
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_2_LSB                                                                    14
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_2_MASK                                                           0x000fc000
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_2_GET(x)                                         (((x) & 0x000fc000) >> 14)
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_2_SET(x)                                         (((x) << 14) & 0x000fc000)
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_1_MSB                                                                    25
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_1_LSB                                                                    20
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_1_MASK                                                           0x03f00000
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_1_GET(x)                                         (((x) & 0x03f00000) >> 20)
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_1_SET(x)                                         (((x) << 20) & 0x03f00000)
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_0_MSB                                                                    31
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_0_LSB                                                                    26
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_0_MASK                                                           0xfc000000
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_0_GET(x)                                         (((x) & 0xfc000000) >> 26)
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_0_SET(x)                                         (((x) << 26) & 0xfc000000)
+
+/* macros for TXRF8 */
+#define PHY_ANALOG_TXRF8_ADDRESS                                                                     0x0000005c
+#define PHY_ANALOG_TXRF8_OFFSET                                                                      0x0000005c
+#define PHY_ANALOG_TXRF8_SPARE8_MSB                                                                           1
+#define PHY_ANALOG_TXRF8_SPARE8_LSB                                                                           0
+#define PHY_ANALOG_TXRF8_SPARE8_MASK                                                                 0x00000003
+#define PHY_ANALOG_TXRF8_SPARE8_GET(x)                                                (((x) & 0x00000003) >> 0)
+#define PHY_ANALOG_TXRF8_SPARE8_SET(x)                                                (((x) << 0) & 0x00000003)
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_9_MSB                                                                     7
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_9_LSB                                                                     2
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_9_MASK                                                           0x000000fc
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_9_GET(x)                                          (((x) & 0x000000fc) >> 2)
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_9_SET(x)                                          (((x) << 2) & 0x000000fc)
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_8_MSB                                                                    13
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_8_LSB                                                                     8
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_8_MASK                                                           0x00003f00
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_8_GET(x)                                          (((x) & 0x00003f00) >> 8)
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_8_SET(x)                                          (((x) << 8) & 0x00003f00)
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_7_MSB                                                                    19
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_7_LSB                                                                    14
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_7_MASK                                                           0x000fc000
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_7_GET(x)                                         (((x) & 0x000fc000) >> 14)
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_7_SET(x)                                         (((x) << 14) & 0x000fc000)
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_6_MSB                                                                    25
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_6_LSB                                                                    20
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_6_MASK                                                           0x03f00000
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_6_GET(x)                                         (((x) & 0x03f00000) >> 20)
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_6_SET(x)                                         (((x) << 20) & 0x03f00000)
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_5_MSB                                                                    31
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_5_LSB                                                                    26
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_5_MASK                                                           0xfc000000
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_5_GET(x)                                         (((x) & 0xfc000000) >> 26)
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_5_SET(x)                                         (((x) << 26) & 0xfc000000)
+
+/* macros for TXRF9 */
+#define PHY_ANALOG_TXRF9_ADDRESS                                                                     0x00000060
+#define PHY_ANALOG_TXRF9_OFFSET                                                                      0x00000060
+#define PHY_ANALOG_TXRF9_SPARE9_MSB                                                                           1
+#define PHY_ANALOG_TXRF9_SPARE9_LSB                                                                           0
+#define PHY_ANALOG_TXRF9_SPARE9_MASK                                                                 0x00000003
+#define PHY_ANALOG_TXRF9_SPARE9_GET(x)                                                (((x) & 0x00000003) >> 0)
+#define PHY_ANALOG_TXRF9_SPARE9_SET(x)                                                (((x) << 0) & 0x00000003)
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_14_MSB                                                                    7
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_14_LSB                                                                    2
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_14_MASK                                                          0x000000fc
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_14_GET(x)                                         (((x) & 0x000000fc) >> 2)
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_14_SET(x)                                         (((x) << 2) & 0x000000fc)
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_13_MSB                                                                   13
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_13_LSB                                                                    8
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_13_MASK                                                          0x00003f00
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_13_GET(x)                                         (((x) & 0x00003f00) >> 8)
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_13_SET(x)                                         (((x) << 8) & 0x00003f00)
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_12_MSB                                                                   19
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_12_LSB                                                                   14
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_12_MASK                                                          0x000fc000
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_12_GET(x)                                        (((x) & 0x000fc000) >> 14)
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_12_SET(x)                                        (((x) << 14) & 0x000fc000)
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_11_MSB                                                                   25
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_11_LSB                                                                   20
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_11_MASK                                                          0x03f00000
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_11_GET(x)                                        (((x) & 0x03f00000) >> 20)
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_11_SET(x)                                        (((x) << 20) & 0x03f00000)
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_10_MSB                                                                   31
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_10_LSB                                                                   26
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_10_MASK                                                          0xfc000000
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_10_GET(x)                                        (((x) & 0xfc000000) >> 26)
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_10_SET(x)                                        (((x) << 26) & 0xfc000000)
+
+/* macros for TXRF10 */
+#define PHY_ANALOG_TXRF10_ADDRESS                                                                    0x00000064
+#define PHY_ANALOG_TXRF10_OFFSET                                                                     0x00000064
+#define PHY_ANALOG_TXRF10_SPARE10_MSB                                                                        12
+#define PHY_ANALOG_TXRF10_SPARE10_LSB                                                                         0
+#define PHY_ANALOG_TXRF10_SPARE10_MASK                                                               0x00001fff
+#define PHY_ANALOG_TXRF10_SPARE10_GET(x)                                              (((x) & 0x00001fff) >> 0)
+#define PHY_ANALOG_TXRF10_SPARE10_SET(x)                                              (((x) << 0) & 0x00001fff)
+#define PHY_ANALOG_TXRF10_PDOUT5G_3CALTX_MSB                                                                 13
+#define PHY_ANALOG_TXRF10_PDOUT5G_3CALTX_LSB                                                                 13
+#define PHY_ANALOG_TXRF10_PDOUT5G_3CALTX_MASK                                                        0x00002000
+#define PHY_ANALOG_TXRF10_PDOUT5G_3CALTX_GET(x)                                      (((x) & 0x00002000) >> 13)
+#define PHY_ANALOG_TXRF10_PDOUT5G_3CALTX_SET(x)                                      (((x) << 13) & 0x00002000)
+#define PHY_ANALOG_TXRF10_D3B5GCALTX_MSB                                                                     16
+#define PHY_ANALOG_TXRF10_D3B5GCALTX_LSB                                                                     14
+#define PHY_ANALOG_TXRF10_D3B5GCALTX_MASK                                                            0x0001c000
+#define PHY_ANALOG_TXRF10_D3B5GCALTX_GET(x)                                          (((x) & 0x0001c000) >> 14)
+#define PHY_ANALOG_TXRF10_D3B5GCALTX_SET(x)                                          (((x) << 14) & 0x0001c000)
+#define PHY_ANALOG_TXRF10_D4B5GCALTX_MSB                                                                     19
+#define PHY_ANALOG_TXRF10_D4B5GCALTX_LSB                                                                     17
+#define PHY_ANALOG_TXRF10_D4B5GCALTX_MASK                                                            0x000e0000
+#define PHY_ANALOG_TXRF10_D4B5GCALTX_GET(x)                                          (((x) & 0x000e0000) >> 17)
+#define PHY_ANALOG_TXRF10_D4B5GCALTX_SET(x)                                          (((x) << 17) & 0x000e0000)
+#define PHY_ANALOG_TXRF10_PADRVGN2GCALTX_MSB                                                                 26
+#define PHY_ANALOG_TXRF10_PADRVGN2GCALTX_LSB                                                                 20
+#define PHY_ANALOG_TXRF10_PADRVGN2GCALTX_MASK                                                        0x07f00000
+#define PHY_ANALOG_TXRF10_PADRVGN2GCALTX_GET(x)                                      (((x) & 0x07f00000) >> 20)
+#define PHY_ANALOG_TXRF10_PADRVGN2GCALTX_SET(x)                                      (((x) << 20) & 0x07f00000)
+#define PHY_ANALOG_TXRF10_DB2GCALTX_MSB                                                                      29
+#define PHY_ANALOG_TXRF10_DB2GCALTX_LSB                                                                      27
+#define PHY_ANALOG_TXRF10_DB2GCALTX_MASK                                                             0x38000000
+#define PHY_ANALOG_TXRF10_DB2GCALTX_GET(x)                                           (((x) & 0x38000000) >> 27)
+#define PHY_ANALOG_TXRF10_DB2GCALTX_SET(x)                                           (((x) << 27) & 0x38000000)
+#define PHY_ANALOG_TXRF10_CALTXSHIFT_MSB                                                                     30
+#define PHY_ANALOG_TXRF10_CALTXSHIFT_LSB                                                                     30
+#define PHY_ANALOG_TXRF10_CALTXSHIFT_MASK                                                            0x40000000
+#define PHY_ANALOG_TXRF10_CALTXSHIFT_GET(x)                                          (((x) & 0x40000000) >> 30)
+#define PHY_ANALOG_TXRF10_CALTXSHIFT_SET(x)                                          (((x) << 30) & 0x40000000)
+#define PHY_ANALOG_TXRF10_CALTXSHIFTOVR_MSB                                                                  31
+#define PHY_ANALOG_TXRF10_CALTXSHIFTOVR_LSB                                                                  31
+#define PHY_ANALOG_TXRF10_CALTXSHIFTOVR_MASK                                                         0x80000000
+#define PHY_ANALOG_TXRF10_CALTXSHIFTOVR_GET(x)                                       (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_TXRF10_CALTXSHIFTOVR_SET(x)                                       (((x) << 31) & 0x80000000)
+
+/* macros for TXRF11 */
+#define PHY_ANALOG_TXRF11_ADDRESS                                                                    0x00000068
+#define PHY_ANALOG_TXRF11_OFFSET                                                                     0x00000068
+#define PHY_ANALOG_TXRF11_SPARE11_MSB                                                                         1
+#define PHY_ANALOG_TXRF11_SPARE11_LSB                                                                         0
+#define PHY_ANALOG_TXRF11_SPARE11_MASK                                                               0x00000003
+#define PHY_ANALOG_TXRF11_SPARE11_GET(x)                                              (((x) & 0x00000003) >> 0)
+#define PHY_ANALOG_TXRF11_SPARE11_SET(x)                                              (((x) << 0) & 0x00000003)
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS5G_MSB                                                               4
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS5G_LSB                                                               2
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS5G_MASK                                                     0x0000001c
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS5G_GET(x)                                    (((x) & 0x0000001c) >> 2)
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS5G_SET(x)                                    (((x) << 2) & 0x0000001c)
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV5G_MSB                                                                7
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV5G_LSB                                                                5
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV5G_MASK                                                      0x000000e0
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV5G_GET(x)                                     (((x) & 0x000000e0) >> 5)
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV5G_SET(x)                                     (((x) << 5) & 0x000000e0)
+#define PHY_ANALOG_TXRF11_PWD_IR25PA2G_MSB                                                                   10
+#define PHY_ANALOG_TXRF11_PWD_IR25PA2G_LSB                                                                    8
+#define PHY_ANALOG_TXRF11_PWD_IR25PA2G_MASK                                                          0x00000700
+#define PHY_ANALOG_TXRF11_PWD_IR25PA2G_GET(x)                                         (((x) & 0x00000700) >> 8)
+#define PHY_ANALOG_TXRF11_PWD_IR25PA2G_SET(x)                                         (((x) << 8) & 0x00000700)
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS2G_MSB                                                              13
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS2G_LSB                                                              11
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS2G_MASK                                                     0x00003800
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS2G_GET(x)                                   (((x) & 0x00003800) >> 11)
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS2G_SET(x)                                   (((x) << 11) & 0x00003800)
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV2G_MSB                                                               16
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV2G_LSB                                                               14
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV2G_MASK                                                      0x0001c000
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV2G_GET(x)                                    (((x) & 0x0001c000) >> 14)
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV2G_SET(x)                                    (((x) << 14) & 0x0001c000)
+#define PHY_ANALOG_TXRF11_PWD_ICSPARE_MSB                                                                    19
+#define PHY_ANALOG_TXRF11_PWD_ICSPARE_LSB                                                                    17
+#define PHY_ANALOG_TXRF11_PWD_ICSPARE_MASK                                                           0x000e0000
+#define PHY_ANALOG_TXRF11_PWD_ICSPARE_GET(x)                                         (((x) & 0x000e0000) >> 17)
+#define PHY_ANALOG_TXRF11_PWD_ICSPARE_SET(x)                                         (((x) << 17) & 0x000e0000)
+#define PHY_ANALOG_TXRF11_PWD_IC25PA5G2_MSB                                                                  22
+#define PHY_ANALOG_TXRF11_PWD_IC25PA5G2_LSB                                                                  20
+#define PHY_ANALOG_TXRF11_PWD_IC25PA5G2_MASK                                                         0x00700000
+#define PHY_ANALOG_TXRF11_PWD_IC25PA5G2_GET(x)                                       (((x) & 0x00700000) >> 20)
+#define PHY_ANALOG_TXRF11_PWD_IC25PA5G2_SET(x)                                       (((x) << 20) & 0x00700000)
+#define PHY_ANALOG_TXRF11_PWD_IC25PA5G1_MSB                                                                  25
+#define PHY_ANALOG_TXRF11_PWD_IC25PA5G1_LSB                                                                  23
+#define PHY_ANALOG_TXRF11_PWD_IC25PA5G1_MASK                                                         0x03800000
+#define PHY_ANALOG_TXRF11_PWD_IC25PA5G1_GET(x)                                       (((x) & 0x03800000) >> 23)
+#define PHY_ANALOG_TXRF11_PWD_IC25PA5G1_SET(x)                                       (((x) << 23) & 0x03800000)
+#define PHY_ANALOG_TXRF11_PWD_IC25MIXBUF5G_MSB                                                               28
+#define PHY_ANALOG_TXRF11_PWD_IC25MIXBUF5G_LSB                                                               26
+#define PHY_ANALOG_TXRF11_PWD_IC25MIXBUF5G_MASK                                                      0x1c000000
+#define PHY_ANALOG_TXRF11_PWD_IC25MIXBUF5G_GET(x)                                    (((x) & 0x1c000000) >> 26)
+#define PHY_ANALOG_TXRF11_PWD_IC25MIXBUF5G_SET(x)                                    (((x) << 26) & 0x1c000000)
+#define PHY_ANALOG_TXRF11_PWD_IC25PA2G_MSB                                                                   31
+#define PHY_ANALOG_TXRF11_PWD_IC25PA2G_LSB                                                                   29
+#define PHY_ANALOG_TXRF11_PWD_IC25PA2G_MASK                                                          0xe0000000
+#define PHY_ANALOG_TXRF11_PWD_IC25PA2G_GET(x)                                        (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_TXRF11_PWD_IC25PA2G_SET(x)                                        (((x) << 29) & 0xe0000000)
+
+/* macros for TXRF12 */
+#define PHY_ANALOG_TXRF12_ADDRESS                                                                    0x0000006c
+#define PHY_ANALOG_TXRF12_OFFSET                                                                     0x0000006c
+#define PHY_ANALOG_TXRF12_SPARE12_2_MSB                                                                       7
+#define PHY_ANALOG_TXRF12_SPARE12_2_LSB                                                                       0
+#define PHY_ANALOG_TXRF12_SPARE12_2_MASK                                                             0x000000ff
+#define PHY_ANALOG_TXRF12_SPARE12_2_GET(x)                                            (((x) & 0x000000ff) >> 0)
+#define PHY_ANALOG_TXRF12_SPARE12_1_MSB                                                                      15
+#define PHY_ANALOG_TXRF12_SPARE12_1_LSB                                                                       8
+#define PHY_ANALOG_TXRF12_SPARE12_1_MASK                                                             0x0000ff00
+#define PHY_ANALOG_TXRF12_SPARE12_1_GET(x)                                            (((x) & 0x0000ff00) >> 8)
+#define PHY_ANALOG_TXRF12_SPARE12_1_SET(x)                                            (((x) << 8) & 0x0000ff00)
+#define PHY_ANALOG_TXRF12_ATBSEL5G_MSB                                                                       19
+#define PHY_ANALOG_TXRF12_ATBSEL5G_LSB                                                                       16
+#define PHY_ANALOG_TXRF12_ATBSEL5G_MASK                                                              0x000f0000
+#define PHY_ANALOG_TXRF12_ATBSEL5G_GET(x)                                            (((x) & 0x000f0000) >> 16)
+#define PHY_ANALOG_TXRF12_ATBSEL5G_SET(x)                                            (((x) << 16) & 0x000f0000)
+#define PHY_ANALOG_TXRF12_ATBSEL2G_MSB                                                                       22
+#define PHY_ANALOG_TXRF12_ATBSEL2G_LSB                                                                       20
+#define PHY_ANALOG_TXRF12_ATBSEL2G_MASK                                                              0x00700000
+#define PHY_ANALOG_TXRF12_ATBSEL2G_GET(x)                                            (((x) & 0x00700000) >> 20)
+#define PHY_ANALOG_TXRF12_ATBSEL2G_SET(x)                                            (((x) << 20) & 0x00700000)
+#define PHY_ANALOG_TXRF12_PWD_IRSPARE_MSB                                                                    25
+#define PHY_ANALOG_TXRF12_PWD_IRSPARE_LSB                                                                    23
+#define PHY_ANALOG_TXRF12_PWD_IRSPARE_MASK                                                           0x03800000
+#define PHY_ANALOG_TXRF12_PWD_IRSPARE_GET(x)                                         (((x) & 0x03800000) >> 23)
+#define PHY_ANALOG_TXRF12_PWD_IRSPARE_SET(x)                                         (((x) << 23) & 0x03800000)
+#define PHY_ANALOG_TXRF12_PWD_IR25PA5G2_MSB                                                                  28
+#define PHY_ANALOG_TXRF12_PWD_IR25PA5G2_LSB                                                                  26
+#define PHY_ANALOG_TXRF12_PWD_IR25PA5G2_MASK                                                         0x1c000000
+#define PHY_ANALOG_TXRF12_PWD_IR25PA5G2_GET(x)                                       (((x) & 0x1c000000) >> 26)
+#define PHY_ANALOG_TXRF12_PWD_IR25PA5G2_SET(x)                                       (((x) << 26) & 0x1c000000)
+#define PHY_ANALOG_TXRF12_PWD_IR25PA5G1_MSB                                                                  31
+#define PHY_ANALOG_TXRF12_PWD_IR25PA5G1_LSB                                                                  29
+#define PHY_ANALOG_TXRF12_PWD_IR25PA5G1_MASK                                                         0xe0000000
+#define PHY_ANALOG_TXRF12_PWD_IR25PA5G1_GET(x)                                       (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_TXRF12_PWD_IR25PA5G1_SET(x)                                       (((x) << 29) & 0xe0000000)
+
+/* macros for SYNTH1 */
+#define PHY_ANALOG_SYNTH1_ADDRESS                                                                    0x00000080
+#define PHY_ANALOG_SYNTH1_OFFSET                                                                     0x00000080
+#define PHY_ANALOG_SYNTH1_SEL_VCMONABUS_MSB                                                                   2
+#define PHY_ANALOG_SYNTH1_SEL_VCMONABUS_LSB                                                                   0
+#define PHY_ANALOG_SYNTH1_SEL_VCMONABUS_MASK                                                         0x00000007
+#define PHY_ANALOG_SYNTH1_SEL_VCMONABUS_GET(x)                                        (((x) & 0x00000007) >> 0)
+#define PHY_ANALOG_SYNTH1_SEL_VCMONABUS_SET(x)                                        (((x) << 0) & 0x00000007)
+#define PHY_ANALOG_SYNTH1_SEL_VCOABUS_MSB                                                                     5
+#define PHY_ANALOG_SYNTH1_SEL_VCOABUS_LSB                                                                     3
+#define PHY_ANALOG_SYNTH1_SEL_VCOABUS_MASK                                                           0x00000038
+#define PHY_ANALOG_SYNTH1_SEL_VCOABUS_GET(x)                                          (((x) & 0x00000038) >> 3)
+#define PHY_ANALOG_SYNTH1_SEL_VCOABUS_SET(x)                                          (((x) << 3) & 0x00000038)
+#define PHY_ANALOG_SYNTH1_MONITOR_SYNTHLOCKVCOK_MSB                                                           6
+#define PHY_ANALOG_SYNTH1_MONITOR_SYNTHLOCKVCOK_LSB                                                           6
+#define PHY_ANALOG_SYNTH1_MONITOR_SYNTHLOCKVCOK_MASK                                                 0x00000040
+#define PHY_ANALOG_SYNTH1_MONITOR_SYNTHLOCKVCOK_GET(x)                                (((x) & 0x00000040) >> 6)
+#define PHY_ANALOG_SYNTH1_MONITOR_SYNTHLOCKVCOK_SET(x)                                (((x) << 6) & 0x00000040)
+#define PHY_ANALOG_SYNTH1_MONITOR_VC2LOW_MSB                                                                  7
+#define PHY_ANALOG_SYNTH1_MONITOR_VC2LOW_LSB                                                                  7
+#define PHY_ANALOG_SYNTH1_MONITOR_VC2LOW_MASK                                                        0x00000080
+#define PHY_ANALOG_SYNTH1_MONITOR_VC2LOW_GET(x)                                       (((x) & 0x00000080) >> 7)
+#define PHY_ANALOG_SYNTH1_MONITOR_VC2LOW_SET(x)                                       (((x) << 7) & 0x00000080)
+#define PHY_ANALOG_SYNTH1_MONITOR_VC2HIGH_MSB                                                                 8
+#define PHY_ANALOG_SYNTH1_MONITOR_VC2HIGH_LSB                                                                 8
+#define PHY_ANALOG_SYNTH1_MONITOR_VC2HIGH_MASK                                                       0x00000100
+#define PHY_ANALOG_SYNTH1_MONITOR_VC2HIGH_GET(x)                                      (((x) & 0x00000100) >> 8)
+#define PHY_ANALOG_SYNTH1_MONITOR_VC2HIGH_SET(x)                                      (((x) << 8) & 0x00000100)
+#define PHY_ANALOG_SYNTH1_MONITOR_FB_DIV2_MSB                                                                 9
+#define PHY_ANALOG_SYNTH1_MONITOR_FB_DIV2_LSB                                                                 9
+#define PHY_ANALOG_SYNTH1_MONITOR_FB_DIV2_MASK                                                       0x00000200
+#define PHY_ANALOG_SYNTH1_MONITOR_FB_DIV2_GET(x)                                      (((x) & 0x00000200) >> 9)
+#define PHY_ANALOG_SYNTH1_MONITOR_FB_DIV2_SET(x)                                      (((x) << 9) & 0x00000200)
+#define PHY_ANALOG_SYNTH1_MONITOR_REF_MSB                                                                    10
+#define PHY_ANALOG_SYNTH1_MONITOR_REF_LSB                                                                    10
+#define PHY_ANALOG_SYNTH1_MONITOR_REF_MASK                                                           0x00000400
+#define PHY_ANALOG_SYNTH1_MONITOR_REF_GET(x)                                         (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_SYNTH1_MONITOR_REF_SET(x)                                         (((x) << 10) & 0x00000400)
+#define PHY_ANALOG_SYNTH1_MONITOR_FB_MSB                                                                     11
+#define PHY_ANALOG_SYNTH1_MONITOR_FB_LSB                                                                     11
+#define PHY_ANALOG_SYNTH1_MONITOR_FB_MASK                                                            0x00000800
+#define PHY_ANALOG_SYNTH1_MONITOR_FB_GET(x)                                          (((x) & 0x00000800) >> 11)
+#define PHY_ANALOG_SYNTH1_MONITOR_FB_SET(x)                                          (((x) << 11) & 0x00000800)
+#define PHY_ANALOG_SYNTH1_SEVENBITVCOCAP_MSB                                                                 12
+#define PHY_ANALOG_SYNTH1_SEVENBITVCOCAP_LSB                                                                 12
+#define PHY_ANALOG_SYNTH1_SEVENBITVCOCAP_MASK                                                        0x00001000
+#define PHY_ANALOG_SYNTH1_SEVENBITVCOCAP_GET(x)                                      (((x) & 0x00001000) >> 12)
+#define PHY_ANALOG_SYNTH1_SEVENBITVCOCAP_SET(x)                                      (((x) << 12) & 0x00001000)
+#define PHY_ANALOG_SYNTH1_PWUP_PD_MSB                                                                        15
+#define PHY_ANALOG_SYNTH1_PWUP_PD_LSB                                                                        13
+#define PHY_ANALOG_SYNTH1_PWUP_PD_MASK                                                               0x0000e000
+#define PHY_ANALOG_SYNTH1_PWUP_PD_GET(x)                                             (((x) & 0x0000e000) >> 13)
+#define PHY_ANALOG_SYNTH1_PWUP_PD_SET(x)                                             (((x) << 13) & 0x0000e000)
+#define PHY_ANALOG_SYNTH1_PWD_VCOBUF_MSB                                                                     16
+#define PHY_ANALOG_SYNTH1_PWD_VCOBUF_LSB                                                                     16
+#define PHY_ANALOG_SYNTH1_PWD_VCOBUF_MASK                                                            0x00010000
+#define PHY_ANALOG_SYNTH1_PWD_VCOBUF_GET(x)                                          (((x) & 0x00010000) >> 16)
+#define PHY_ANALOG_SYNTH1_PWD_VCOBUF_SET(x)                                          (((x) << 16) & 0x00010000)
+#define PHY_ANALOG_SYNTH1_VCOBUFGAIN_MSB                                                                     18
+#define PHY_ANALOG_SYNTH1_VCOBUFGAIN_LSB                                                                     17
+#define PHY_ANALOG_SYNTH1_VCOBUFGAIN_MASK                                                            0x00060000
+#define PHY_ANALOG_SYNTH1_VCOBUFGAIN_GET(x)                                          (((x) & 0x00060000) >> 17)
+#define PHY_ANALOG_SYNTH1_VCOBUFGAIN_SET(x)                                          (((x) << 17) & 0x00060000)
+#define PHY_ANALOG_SYNTH1_VCOREGLEVEL_MSB                                                                    20
+#define PHY_ANALOG_SYNTH1_VCOREGLEVEL_LSB                                                                    19
+#define PHY_ANALOG_SYNTH1_VCOREGLEVEL_MASK                                                           0x00180000
+#define PHY_ANALOG_SYNTH1_VCOREGLEVEL_GET(x)                                         (((x) & 0x00180000) >> 19)
+#define PHY_ANALOG_SYNTH1_VCOREGLEVEL_SET(x)                                         (((x) << 19) & 0x00180000)
+#define PHY_ANALOG_SYNTH1_VCOREGBYPASS_MSB                                                                   21
+#define PHY_ANALOG_SYNTH1_VCOREGBYPASS_LSB                                                                   21
+#define PHY_ANALOG_SYNTH1_VCOREGBYPASS_MASK                                                          0x00200000
+#define PHY_ANALOG_SYNTH1_VCOREGBYPASS_GET(x)                                        (((x) & 0x00200000) >> 21)
+#define PHY_ANALOG_SYNTH1_VCOREGBYPASS_SET(x)                                        (((x) << 21) & 0x00200000)
+#define PHY_ANALOG_SYNTH1_PWUP_LOREF_MSB                                                                     22
+#define PHY_ANALOG_SYNTH1_PWUP_LOREF_LSB                                                                     22
+#define PHY_ANALOG_SYNTH1_PWUP_LOREF_MASK                                                            0x00400000
+#define PHY_ANALOG_SYNTH1_PWUP_LOREF_GET(x)                                          (((x) & 0x00400000) >> 22)
+#define PHY_ANALOG_SYNTH1_PWUP_LOREF_SET(x)                                          (((x) << 22) & 0x00400000)
+#define PHY_ANALOG_SYNTH1_PWD_LOMIX_MSB                                                                      23
+#define PHY_ANALOG_SYNTH1_PWD_LOMIX_LSB                                                                      23
+#define PHY_ANALOG_SYNTH1_PWD_LOMIX_MASK                                                             0x00800000
+#define PHY_ANALOG_SYNTH1_PWD_LOMIX_GET(x)                                           (((x) & 0x00800000) >> 23)
+#define PHY_ANALOG_SYNTH1_PWD_LOMIX_SET(x)                                           (((x) << 23) & 0x00800000)
+#define PHY_ANALOG_SYNTH1_PWD_LODIV_MSB                                                                      24
+#define PHY_ANALOG_SYNTH1_PWD_LODIV_LSB                                                                      24
+#define PHY_ANALOG_SYNTH1_PWD_LODIV_MASK                                                             0x01000000
+#define PHY_ANALOG_SYNTH1_PWD_LODIV_GET(x)                                           (((x) & 0x01000000) >> 24)
+#define PHY_ANALOG_SYNTH1_PWD_LODIV_SET(x)                                           (((x) << 24) & 0x01000000)
+#define PHY_ANALOG_SYNTH1_PWD_LOBUF5G_MSB                                                                    25
+#define PHY_ANALOG_SYNTH1_PWD_LOBUF5G_LSB                                                                    25
+#define PHY_ANALOG_SYNTH1_PWD_LOBUF5G_MASK                                                           0x02000000
+#define PHY_ANALOG_SYNTH1_PWD_LOBUF5G_GET(x)                                         (((x) & 0x02000000) >> 25)
+#define PHY_ANALOG_SYNTH1_PWD_LOBUF5G_SET(x)                                         (((x) << 25) & 0x02000000)
+#define PHY_ANALOG_SYNTH1_PWD_LOBUF2G_MSB                                                                    26
+#define PHY_ANALOG_SYNTH1_PWD_LOBUF2G_LSB                                                                    26
+#define PHY_ANALOG_SYNTH1_PWD_LOBUF2G_MASK                                                           0x04000000
+#define PHY_ANALOG_SYNTH1_PWD_LOBUF2G_GET(x)                                         (((x) & 0x04000000) >> 26)
+#define PHY_ANALOG_SYNTH1_PWD_LOBUF2G_SET(x)                                         (((x) << 26) & 0x04000000)
+#define PHY_ANALOG_SYNTH1_PWD_PRESC_MSB                                                                      27
+#define PHY_ANALOG_SYNTH1_PWD_PRESC_LSB                                                                      27
+#define PHY_ANALOG_SYNTH1_PWD_PRESC_MASK                                                             0x08000000
+#define PHY_ANALOG_SYNTH1_PWD_PRESC_GET(x)                                           (((x) & 0x08000000) >> 27)
+#define PHY_ANALOG_SYNTH1_PWD_PRESC_SET(x)                                           (((x) << 27) & 0x08000000)
+#define PHY_ANALOG_SYNTH1_PWD_VCO_MSB                                                                        28
+#define PHY_ANALOG_SYNTH1_PWD_VCO_LSB                                                                        28
+#define PHY_ANALOG_SYNTH1_PWD_VCO_MASK                                                               0x10000000
+#define PHY_ANALOG_SYNTH1_PWD_VCO_GET(x)                                             (((x) & 0x10000000) >> 28)
+#define PHY_ANALOG_SYNTH1_PWD_VCO_SET(x)                                             (((x) << 28) & 0x10000000)
+#define PHY_ANALOG_SYNTH1_PWD_VCMON_MSB                                                                      29
+#define PHY_ANALOG_SYNTH1_PWD_VCMON_LSB                                                                      29
+#define PHY_ANALOG_SYNTH1_PWD_VCMON_MASK                                                             0x20000000
+#define PHY_ANALOG_SYNTH1_PWD_VCMON_GET(x)                                           (((x) & 0x20000000) >> 29)
+#define PHY_ANALOG_SYNTH1_PWD_VCMON_SET(x)                                           (((x) << 29) & 0x20000000)
+#define PHY_ANALOG_SYNTH1_PWD_CP_MSB                                                                         30
+#define PHY_ANALOG_SYNTH1_PWD_CP_LSB                                                                         30
+#define PHY_ANALOG_SYNTH1_PWD_CP_MASK                                                                0x40000000
+#define PHY_ANALOG_SYNTH1_PWD_CP_GET(x)                                              (((x) & 0x40000000) >> 30)
+#define PHY_ANALOG_SYNTH1_PWD_CP_SET(x)                                              (((x) << 30) & 0x40000000)
+#define PHY_ANALOG_SYNTH1_PWD_BIAS_MSB                                                                       31
+#define PHY_ANALOG_SYNTH1_PWD_BIAS_LSB                                                                       31
+#define PHY_ANALOG_SYNTH1_PWD_BIAS_MASK                                                              0x80000000
+#define PHY_ANALOG_SYNTH1_PWD_BIAS_GET(x)                                            (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_SYNTH1_PWD_BIAS_SET(x)                                            (((x) << 31) & 0x80000000)
+
+/* macros for SYNTH2 */
+#define PHY_ANALOG_SYNTH2_ADDRESS                                                                    0x00000084
+#define PHY_ANALOG_SYNTH2_OFFSET                                                                     0x00000084
+#define PHY_ANALOG_SYNTH2_CAPRANGE3_MSB                                                                       3
+#define PHY_ANALOG_SYNTH2_CAPRANGE3_LSB                                                                       0
+#define PHY_ANALOG_SYNTH2_CAPRANGE3_MASK                                                             0x0000000f
+#define PHY_ANALOG_SYNTH2_CAPRANGE3_GET(x)                                            (((x) & 0x0000000f) >> 0)
+#define PHY_ANALOG_SYNTH2_CAPRANGE3_SET(x)                                            (((x) << 0) & 0x0000000f)
+#define PHY_ANALOG_SYNTH2_CAPRANGE2_MSB                                                                       7
+#define PHY_ANALOG_SYNTH2_CAPRANGE2_LSB                                                                       4
+#define PHY_ANALOG_SYNTH2_CAPRANGE2_MASK                                                             0x000000f0
+#define PHY_ANALOG_SYNTH2_CAPRANGE2_GET(x)                                            (((x) & 0x000000f0) >> 4)
+#define PHY_ANALOG_SYNTH2_CAPRANGE2_SET(x)                                            (((x) << 4) & 0x000000f0)
+#define PHY_ANALOG_SYNTH2_CAPRANGE1_MSB                                                                      11
+#define PHY_ANALOG_SYNTH2_CAPRANGE1_LSB                                                                       8
+#define PHY_ANALOG_SYNTH2_CAPRANGE1_MASK                                                             0x00000f00
+#define PHY_ANALOG_SYNTH2_CAPRANGE1_GET(x)                                            (((x) & 0x00000f00) >> 8)
+#define PHY_ANALOG_SYNTH2_CAPRANGE1_SET(x)                                            (((x) << 8) & 0x00000f00)
+#define PHY_ANALOG_SYNTH2_LOOPLEAKCUR_MSB                                                                    15
+#define PHY_ANALOG_SYNTH2_LOOPLEAKCUR_LSB                                                                    12
+#define PHY_ANALOG_SYNTH2_LOOPLEAKCUR_MASK                                                           0x0000f000
+#define PHY_ANALOG_SYNTH2_LOOPLEAKCUR_GET(x)                                         (((x) & 0x0000f000) >> 12)
+#define PHY_ANALOG_SYNTH2_LOOPLEAKCUR_SET(x)                                         (((x) << 12) & 0x0000f000)
+#define PHY_ANALOG_SYNTH2_CPLOWLK_MSB                                                                        16
+#define PHY_ANALOG_SYNTH2_CPLOWLK_LSB                                                                        16
+#define PHY_ANALOG_SYNTH2_CPLOWLK_MASK                                                               0x00010000
+#define PHY_ANALOG_SYNTH2_CPLOWLK_GET(x)                                             (((x) & 0x00010000) >> 16)
+#define PHY_ANALOG_SYNTH2_CPLOWLK_SET(x)                                             (((x) << 16) & 0x00010000)
+#define PHY_ANALOG_SYNTH2_CPSTEERING_EN_INTN_MSB                                                             17
+#define PHY_ANALOG_SYNTH2_CPSTEERING_EN_INTN_LSB                                                             17
+#define PHY_ANALOG_SYNTH2_CPSTEERING_EN_INTN_MASK                                                    0x00020000
+#define PHY_ANALOG_SYNTH2_CPSTEERING_EN_INTN_GET(x)                                  (((x) & 0x00020000) >> 17)
+#define PHY_ANALOG_SYNTH2_CPSTEERING_EN_INTN_SET(x)                                  (((x) << 17) & 0x00020000)
+#define PHY_ANALOG_SYNTH2_CPBIAS_MSB                                                                         19
+#define PHY_ANALOG_SYNTH2_CPBIAS_LSB                                                                         18
+#define PHY_ANALOG_SYNTH2_CPBIAS_MASK                                                                0x000c0000
+#define PHY_ANALOG_SYNTH2_CPBIAS_GET(x)                                              (((x) & 0x000c0000) >> 18)
+#define PHY_ANALOG_SYNTH2_CPBIAS_SET(x)                                              (((x) << 18) & 0x000c0000)
+#define PHY_ANALOG_SYNTH2_VC_LOW_REF_MSB                                                                     22
+#define PHY_ANALOG_SYNTH2_VC_LOW_REF_LSB                                                                     20
+#define PHY_ANALOG_SYNTH2_VC_LOW_REF_MASK                                                            0x00700000
+#define PHY_ANALOG_SYNTH2_VC_LOW_REF_GET(x)                                          (((x) & 0x00700000) >> 20)
+#define PHY_ANALOG_SYNTH2_VC_LOW_REF_SET(x)                                          (((x) << 20) & 0x00700000)
+#define PHY_ANALOG_SYNTH2_VC_MID_REF_MSB                                                                     25
+#define PHY_ANALOG_SYNTH2_VC_MID_REF_LSB                                                                     23
+#define PHY_ANALOG_SYNTH2_VC_MID_REF_MASK                                                            0x03800000
+#define PHY_ANALOG_SYNTH2_VC_MID_REF_GET(x)                                          (((x) & 0x03800000) >> 23)
+#define PHY_ANALOG_SYNTH2_VC_MID_REF_SET(x)                                          (((x) << 23) & 0x03800000)
+#define PHY_ANALOG_SYNTH2_VC_HI_REF_MSB                                                                      28
+#define PHY_ANALOG_SYNTH2_VC_HI_REF_LSB                                                                      26
+#define PHY_ANALOG_SYNTH2_VC_HI_REF_MASK                                                             0x1c000000
+#define PHY_ANALOG_SYNTH2_VC_HI_REF_GET(x)                                           (((x) & 0x1c000000) >> 26)
+#define PHY_ANALOG_SYNTH2_VC_HI_REF_SET(x)                                           (((x) << 26) & 0x1c000000)
+#define PHY_ANALOG_SYNTH2_VC_CAL_REF_MSB                                                                     31
+#define PHY_ANALOG_SYNTH2_VC_CAL_REF_LSB                                                                     29
+#define PHY_ANALOG_SYNTH2_VC_CAL_REF_MASK                                                            0xe0000000
+#define PHY_ANALOG_SYNTH2_VC_CAL_REF_GET(x)                                          (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_SYNTH2_VC_CAL_REF_SET(x)                                          (((x) << 29) & 0xe0000000)
+
+/* macros for SYNTH3 */
+#define PHY_ANALOG_SYNTH3_ADDRESS                                                                    0x00000088
+#define PHY_ANALOG_SYNTH3_OFFSET                                                                     0x00000088
+#define PHY_ANALOG_SYNTH3_WAIT_VC_CHECK_MSB                                                                   5
+#define PHY_ANALOG_SYNTH3_WAIT_VC_CHECK_LSB                                                                   0
+#define PHY_ANALOG_SYNTH3_WAIT_VC_CHECK_MASK                                                         0x0000003f
+#define PHY_ANALOG_SYNTH3_WAIT_VC_CHECK_GET(x)                                        (((x) & 0x0000003f) >> 0)
+#define PHY_ANALOG_SYNTH3_WAIT_VC_CHECK_SET(x)                                        (((x) << 0) & 0x0000003f)
+#define PHY_ANALOG_SYNTH3_WAIT_CAL_LIN_MSB                                                                   11
+#define PHY_ANALOG_SYNTH3_WAIT_CAL_LIN_LSB                                                                    6
+#define PHY_ANALOG_SYNTH3_WAIT_CAL_LIN_MASK                                                          0x00000fc0
+#define PHY_ANALOG_SYNTH3_WAIT_CAL_LIN_GET(x)                                         (((x) & 0x00000fc0) >> 6)
+#define PHY_ANALOG_SYNTH3_WAIT_CAL_LIN_SET(x)                                         (((x) << 6) & 0x00000fc0)
+#define PHY_ANALOG_SYNTH3_WAIT_CAL_BIN_MSB                                                                   17
+#define PHY_ANALOG_SYNTH3_WAIT_CAL_BIN_LSB                                                                   12
+#define PHY_ANALOG_SYNTH3_WAIT_CAL_BIN_MASK                                                          0x0003f000
+#define PHY_ANALOG_SYNTH3_WAIT_CAL_BIN_GET(x)                                        (((x) & 0x0003f000) >> 12)
+#define PHY_ANALOG_SYNTH3_WAIT_CAL_BIN_SET(x)                                        (((x) << 12) & 0x0003f000)
+#define PHY_ANALOG_SYNTH3_WAIT_PWRUP_MSB                                                                     23
+#define PHY_ANALOG_SYNTH3_WAIT_PWRUP_LSB                                                                     18
+#define PHY_ANALOG_SYNTH3_WAIT_PWRUP_MASK                                                            0x00fc0000
+#define PHY_ANALOG_SYNTH3_WAIT_PWRUP_GET(x)                                          (((x) & 0x00fc0000) >> 18)
+#define PHY_ANALOG_SYNTH3_WAIT_PWRUP_SET(x)                                          (((x) << 18) & 0x00fc0000)
+#define PHY_ANALOG_SYNTH3_WAIT_SHORTR_PWRUP_MSB                                                              29
+#define PHY_ANALOG_SYNTH3_WAIT_SHORTR_PWRUP_LSB                                                              24
+#define PHY_ANALOG_SYNTH3_WAIT_SHORTR_PWRUP_MASK                                                     0x3f000000
+#define PHY_ANALOG_SYNTH3_WAIT_SHORTR_PWRUP_GET(x)                                   (((x) & 0x3f000000) >> 24)
+#define PHY_ANALOG_SYNTH3_WAIT_SHORTR_PWRUP_SET(x)                                   (((x) << 24) & 0x3f000000)
+#define PHY_ANALOG_SYNTH3_SEL_CLK_DIV2_MSB                                                                   30
+#define PHY_ANALOG_SYNTH3_SEL_CLK_DIV2_LSB                                                                   30
+#define PHY_ANALOG_SYNTH3_SEL_CLK_DIV2_MASK                                                          0x40000000
+#define PHY_ANALOG_SYNTH3_SEL_CLK_DIV2_GET(x)                                        (((x) & 0x40000000) >> 30)
+#define PHY_ANALOG_SYNTH3_SEL_CLK_DIV2_SET(x)                                        (((x) << 30) & 0x40000000)
+#define PHY_ANALOG_SYNTH3_DIS_CLK_XTAL_MSB                                                                   31
+#define PHY_ANALOG_SYNTH3_DIS_CLK_XTAL_LSB                                                                   31
+#define PHY_ANALOG_SYNTH3_DIS_CLK_XTAL_MASK                                                          0x80000000
+#define PHY_ANALOG_SYNTH3_DIS_CLK_XTAL_GET(x)                                        (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_SYNTH3_DIS_CLK_XTAL_SET(x)                                        (((x) << 31) & 0x80000000)
+
+/* macros for SYNTH4 */
+#define PHY_ANALOG_SYNTH4_ADDRESS                                                                    0x0000008c
+#define PHY_ANALOG_SYNTH4_OFFSET                                                                     0x0000008c
+#define PHY_ANALOG_SYNTH4_PS_SINGLE_PULSE_MSB                                                                 0
+#define PHY_ANALOG_SYNTH4_PS_SINGLE_PULSE_LSB                                                                 0
+#define PHY_ANALOG_SYNTH4_PS_SINGLE_PULSE_MASK                                                       0x00000001
+#define PHY_ANALOG_SYNTH4_PS_SINGLE_PULSE_GET(x)                                      (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_SYNTH4_PS_SINGLE_PULSE_SET(x)                                      (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_SYNTH4_LONGSHIFTSEL_MSB                                                                    1
+#define PHY_ANALOG_SYNTH4_LONGSHIFTSEL_LSB                                                                    1
+#define PHY_ANALOG_SYNTH4_LONGSHIFTSEL_MASK                                                          0x00000002
+#define PHY_ANALOG_SYNTH4_LONGSHIFTSEL_GET(x)                                         (((x) & 0x00000002) >> 1)
+#define PHY_ANALOG_SYNTH4_LONGSHIFTSEL_SET(x)                                         (((x) << 1) & 0x00000002)
+#define PHY_ANALOG_SYNTH4_LOBUF5GTUNE_OVR_MSB                                                                 3
+#define PHY_ANALOG_SYNTH4_LOBUF5GTUNE_OVR_LSB                                                                 2
+#define PHY_ANALOG_SYNTH4_LOBUF5GTUNE_OVR_MASK                                                       0x0000000c
+#define PHY_ANALOG_SYNTH4_LOBUF5GTUNE_OVR_GET(x)                                      (((x) & 0x0000000c) >> 2)
+#define PHY_ANALOG_SYNTH4_LOBUF5GTUNE_OVR_SET(x)                                      (((x) << 2) & 0x0000000c)
+#define PHY_ANALOG_SYNTH4_FORCE_LOBUF5GTUNE_MSB                                                               4
+#define PHY_ANALOG_SYNTH4_FORCE_LOBUF5GTUNE_LSB                                                               4
+#define PHY_ANALOG_SYNTH4_FORCE_LOBUF5GTUNE_MASK                                                     0x00000010
+#define PHY_ANALOG_SYNTH4_FORCE_LOBUF5GTUNE_GET(x)                                    (((x) & 0x00000010) >> 4)
+#define PHY_ANALOG_SYNTH4_FORCE_LOBUF5GTUNE_SET(x)                                    (((x) << 4) & 0x00000010)
+#define PHY_ANALOG_SYNTH4_PSCOUNT_FBSEL_MSB                                                                   5
+#define PHY_ANALOG_SYNTH4_PSCOUNT_FBSEL_LSB                                                                   5
+#define PHY_ANALOG_SYNTH4_PSCOUNT_FBSEL_MASK                                                         0x00000020
+#define PHY_ANALOG_SYNTH4_PSCOUNT_FBSEL_GET(x)                                        (((x) & 0x00000020) >> 5)
+#define PHY_ANALOG_SYNTH4_PSCOUNT_FBSEL_SET(x)                                        (((x) << 5) & 0x00000020)
+#define PHY_ANALOG_SYNTH4_SDM_DITHER_MSB                                                                      7
+#define PHY_ANALOG_SYNTH4_SDM_DITHER_LSB                                                                      6
+#define PHY_ANALOG_SYNTH4_SDM_DITHER_MASK                                                            0x000000c0
+#define PHY_ANALOG_SYNTH4_SDM_DITHER_GET(x)                                           (((x) & 0x000000c0) >> 6)
+#define PHY_ANALOG_SYNTH4_SDM_DITHER_SET(x)                                           (((x) << 6) & 0x000000c0)
+#define PHY_ANALOG_SYNTH4_SDM_MODE_MSB                                                                        8
+#define PHY_ANALOG_SYNTH4_SDM_MODE_LSB                                                                        8
+#define PHY_ANALOG_SYNTH4_SDM_MODE_MASK                                                              0x00000100
+#define PHY_ANALOG_SYNTH4_SDM_MODE_GET(x)                                             (((x) & 0x00000100) >> 8)
+#define PHY_ANALOG_SYNTH4_SDM_MODE_SET(x)                                             (((x) << 8) & 0x00000100)
+#define PHY_ANALOG_SYNTH4_SDM_DISABLE_MSB                                                                     9
+#define PHY_ANALOG_SYNTH4_SDM_DISABLE_LSB                                                                     9
+#define PHY_ANALOG_SYNTH4_SDM_DISABLE_MASK                                                           0x00000200
+#define PHY_ANALOG_SYNTH4_SDM_DISABLE_GET(x)                                          (((x) & 0x00000200) >> 9)
+#define PHY_ANALOG_SYNTH4_SDM_DISABLE_SET(x)                                          (((x) << 9) & 0x00000200)
+#define PHY_ANALOG_SYNTH4_RESET_PRESC_MSB                                                                    10
+#define PHY_ANALOG_SYNTH4_RESET_PRESC_LSB                                                                    10
+#define PHY_ANALOG_SYNTH4_RESET_PRESC_MASK                                                           0x00000400
+#define PHY_ANALOG_SYNTH4_RESET_PRESC_GET(x)                                         (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_SYNTH4_RESET_PRESC_SET(x)                                         (((x) << 10) & 0x00000400)
+#define PHY_ANALOG_SYNTH4_PRESCSEL_MSB                                                                       12
+#define PHY_ANALOG_SYNTH4_PRESCSEL_LSB                                                                       11
+#define PHY_ANALOG_SYNTH4_PRESCSEL_MASK                                                              0x00001800
+#define PHY_ANALOG_SYNTH4_PRESCSEL_GET(x)                                            (((x) & 0x00001800) >> 11)
+#define PHY_ANALOG_SYNTH4_PRESCSEL_SET(x)                                            (((x) << 11) & 0x00001800)
+#define PHY_ANALOG_SYNTH4_PFD_DISABLE_MSB                                                                    13
+#define PHY_ANALOG_SYNTH4_PFD_DISABLE_LSB                                                                    13
+#define PHY_ANALOG_SYNTH4_PFD_DISABLE_MASK                                                           0x00002000
+#define PHY_ANALOG_SYNTH4_PFD_DISABLE_GET(x)                                         (((x) & 0x00002000) >> 13)
+#define PHY_ANALOG_SYNTH4_PFD_DISABLE_SET(x)                                         (((x) << 13) & 0x00002000)
+#define PHY_ANALOG_SYNTH4_PFDDELAY_FRACN_MSB                                                                 14
+#define PHY_ANALOG_SYNTH4_PFDDELAY_FRACN_LSB                                                                 14
+#define PHY_ANALOG_SYNTH4_PFDDELAY_FRACN_MASK                                                        0x00004000
+#define PHY_ANALOG_SYNTH4_PFDDELAY_FRACN_GET(x)                                      (((x) & 0x00004000) >> 14)
+#define PHY_ANALOG_SYNTH4_PFDDELAY_FRACN_SET(x)                                      (((x) << 14) & 0x00004000)
+#define PHY_ANALOG_SYNTH4_FORCE_LO_ON_MSB                                                                    15
+#define PHY_ANALOG_SYNTH4_FORCE_LO_ON_LSB                                                                    15
+#define PHY_ANALOG_SYNTH4_FORCE_LO_ON_MASK                                                           0x00008000
+#define PHY_ANALOG_SYNTH4_FORCE_LO_ON_GET(x)                                         (((x) & 0x00008000) >> 15)
+#define PHY_ANALOG_SYNTH4_FORCE_LO_ON_SET(x)                                         (((x) << 15) & 0x00008000)
+#define PHY_ANALOG_SYNTH4_CLKXTAL_EDGE_SEL_MSB                                                               16
+#define PHY_ANALOG_SYNTH4_CLKXTAL_EDGE_SEL_LSB                                                               16
+#define PHY_ANALOG_SYNTH4_CLKXTAL_EDGE_SEL_MASK                                                      0x00010000
+#define PHY_ANALOG_SYNTH4_CLKXTAL_EDGE_SEL_GET(x)                                    (((x) & 0x00010000) >> 16)
+#define PHY_ANALOG_SYNTH4_CLKXTAL_EDGE_SEL_SET(x)                                    (((x) << 16) & 0x00010000)
+#define PHY_ANALOG_SYNTH4_VCOCAPPULLUP_MSB                                                                   17
+#define PHY_ANALOG_SYNTH4_VCOCAPPULLUP_LSB                                                                   17
+#define PHY_ANALOG_SYNTH4_VCOCAPPULLUP_MASK                                                          0x00020000
+#define PHY_ANALOG_SYNTH4_VCOCAPPULLUP_GET(x)                                        (((x) & 0x00020000) >> 17)
+#define PHY_ANALOG_SYNTH4_VCOCAPPULLUP_SET(x)                                        (((x) << 17) & 0x00020000)
+#define PHY_ANALOG_SYNTH4_VCOCAP_OVR_MSB                                                                     25
+#define PHY_ANALOG_SYNTH4_VCOCAP_OVR_LSB                                                                     18
+#define PHY_ANALOG_SYNTH4_VCOCAP_OVR_MASK                                                            0x03fc0000
+#define PHY_ANALOG_SYNTH4_VCOCAP_OVR_GET(x)                                          (((x) & 0x03fc0000) >> 18)
+#define PHY_ANALOG_SYNTH4_VCOCAP_OVR_SET(x)                                          (((x) << 18) & 0x03fc0000)
+#define PHY_ANALOG_SYNTH4_FORCE_VCOCAP_MSB                                                                   26
+#define PHY_ANALOG_SYNTH4_FORCE_VCOCAP_LSB                                                                   26
+#define PHY_ANALOG_SYNTH4_FORCE_VCOCAP_MASK                                                          0x04000000
+#define PHY_ANALOG_SYNTH4_FORCE_VCOCAP_GET(x)                                        (((x) & 0x04000000) >> 26)
+#define PHY_ANALOG_SYNTH4_FORCE_VCOCAP_SET(x)                                        (((x) << 26) & 0x04000000)
+#define PHY_ANALOG_SYNTH4_FORCE_PINVC_MSB                                                                    27
+#define PHY_ANALOG_SYNTH4_FORCE_PINVC_LSB                                                                    27
+#define PHY_ANALOG_SYNTH4_FORCE_PINVC_MASK                                                           0x08000000
+#define PHY_ANALOG_SYNTH4_FORCE_PINVC_GET(x)                                         (((x) & 0x08000000) >> 27)
+#define PHY_ANALOG_SYNTH4_FORCE_PINVC_SET(x)                                         (((x) << 27) & 0x08000000)
+#define PHY_ANALOG_SYNTH4_SHORTR_UNTIL_LOCKED_MSB                                                            28
+#define PHY_ANALOG_SYNTH4_SHORTR_UNTIL_LOCKED_LSB                                                            28
+#define PHY_ANALOG_SYNTH4_SHORTR_UNTIL_LOCKED_MASK                                                   0x10000000
+#define PHY_ANALOG_SYNTH4_SHORTR_UNTIL_LOCKED_GET(x)                                 (((x) & 0x10000000) >> 28)
+#define PHY_ANALOG_SYNTH4_SHORTR_UNTIL_LOCKED_SET(x)                                 (((x) << 28) & 0x10000000)
+#define PHY_ANALOG_SYNTH4_ALWAYS_SHORTR_MSB                                                                  29
+#define PHY_ANALOG_SYNTH4_ALWAYS_SHORTR_LSB                                                                  29
+#define PHY_ANALOG_SYNTH4_ALWAYS_SHORTR_MASK                                                         0x20000000
+#define PHY_ANALOG_SYNTH4_ALWAYS_SHORTR_GET(x)                                       (((x) & 0x20000000) >> 29)
+#define PHY_ANALOG_SYNTH4_ALWAYS_SHORTR_SET(x)                                       (((x) << 29) & 0x20000000)
+#define PHY_ANALOG_SYNTH4_DIS_LOSTVC_MSB                                                                     30
+#define PHY_ANALOG_SYNTH4_DIS_LOSTVC_LSB                                                                     30
+#define PHY_ANALOG_SYNTH4_DIS_LOSTVC_MASK                                                            0x40000000
+#define PHY_ANALOG_SYNTH4_DIS_LOSTVC_GET(x)                                          (((x) & 0x40000000) >> 30)
+#define PHY_ANALOG_SYNTH4_DIS_LOSTVC_SET(x)                                          (((x) << 30) & 0x40000000)
+#define PHY_ANALOG_SYNTH4_DIS_LIN_CAPSEARCH_MSB                                                              31
+#define PHY_ANALOG_SYNTH4_DIS_LIN_CAPSEARCH_LSB                                                              31
+#define PHY_ANALOG_SYNTH4_DIS_LIN_CAPSEARCH_MASK                                                     0x80000000
+#define PHY_ANALOG_SYNTH4_DIS_LIN_CAPSEARCH_GET(x)                                   (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_SYNTH4_DIS_LIN_CAPSEARCH_SET(x)                                   (((x) << 31) & 0x80000000)
+
+/* macros for SYNTH5 */
+#define PHY_ANALOG_SYNTH5_ADDRESS                                                                    0x00000090
+#define PHY_ANALOG_SYNTH5_OFFSET                                                                     0x00000090
+#define PHY_ANALOG_SYNTH5_VCOBIAS_MSB                                                                         1
+#define PHY_ANALOG_SYNTH5_VCOBIAS_LSB                                                                         0
+#define PHY_ANALOG_SYNTH5_VCOBIAS_MASK                                                               0x00000003
+#define PHY_ANALOG_SYNTH5_VCOBIAS_GET(x)                                              (((x) & 0x00000003) >> 0)
+#define PHY_ANALOG_SYNTH5_VCOBIAS_SET(x)                                              (((x) << 0) & 0x00000003)
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF5G50_MSB                                                                4
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF5G50_LSB                                                                2
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF5G50_MASK                                                      0x0000001c
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF5G50_GET(x)                                     (((x) & 0x0000001c) >> 2)
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF5G50_SET(x)                                     (((x) << 2) & 0x0000001c)
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF2G50_MSB                                                                7
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF2G50_LSB                                                                5
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF2G50_MASK                                                      0x000000e0
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF2G50_GET(x)                                     (((x) & 0x000000e0) >> 5)
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF2G50_SET(x)                                     (((x) << 5) & 0x000000e0)
+#define PHY_ANALOG_SYNTH5_PWDB_ICVCO25_MSB                                                                   10
+#define PHY_ANALOG_SYNTH5_PWDB_ICVCO25_LSB                                                                    8
+#define PHY_ANALOG_SYNTH5_PWDB_ICVCO25_MASK                                                          0x00000700
+#define PHY_ANALOG_SYNTH5_PWDB_ICVCO25_GET(x)                                         (((x) & 0x00000700) >> 8)
+#define PHY_ANALOG_SYNTH5_PWDB_ICVCO25_SET(x)                                         (((x) << 8) & 0x00000700)
+#define PHY_ANALOG_SYNTH5_PWDB_ICVCOREG25_MSB                                                                13
+#define PHY_ANALOG_SYNTH5_PWDB_ICVCOREG25_LSB                                                                11
+#define PHY_ANALOG_SYNTH5_PWDB_ICVCOREG25_MASK                                                       0x00003800
+#define PHY_ANALOG_SYNTH5_PWDB_ICVCOREG25_GET(x)                                     (((x) & 0x00003800) >> 11)
+#define PHY_ANALOG_SYNTH5_PWDB_ICVCOREG25_SET(x)                                     (((x) << 11) & 0x00003800)
+#define PHY_ANALOG_SYNTH5_PWDB_IRVCOREG50_MSB                                                                14
+#define PHY_ANALOG_SYNTH5_PWDB_IRVCOREG50_LSB                                                                14
+#define PHY_ANALOG_SYNTH5_PWDB_IRVCOREG50_MASK                                                       0x00004000
+#define PHY_ANALOG_SYNTH5_PWDB_IRVCOREG50_GET(x)                                     (((x) & 0x00004000) >> 14)
+#define PHY_ANALOG_SYNTH5_PWDB_IRVCOREG50_SET(x)                                     (((x) << 14) & 0x00004000)
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOMIX_MSB                                                                   17
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOMIX_LSB                                                                   15
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOMIX_MASK                                                          0x00038000
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOMIX_GET(x)                                        (((x) & 0x00038000) >> 15)
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOMIX_SET(x)                                        (((x) << 15) & 0x00038000)
+#define PHY_ANALOG_SYNTH5_PWDB_ICLODIV50_MSB                                                                 20
+#define PHY_ANALOG_SYNTH5_PWDB_ICLODIV50_LSB                                                                 18
+#define PHY_ANALOG_SYNTH5_PWDB_ICLODIV50_MASK                                                        0x001c0000
+#define PHY_ANALOG_SYNTH5_PWDB_ICLODIV50_GET(x)                                      (((x) & 0x001c0000) >> 18)
+#define PHY_ANALOG_SYNTH5_PWDB_ICLODIV50_SET(x)                                      (((x) << 18) & 0x001c0000)
+#define PHY_ANALOG_SYNTH5_PWDB_ICPRESC50_MSB                                                                 23
+#define PHY_ANALOG_SYNTH5_PWDB_ICPRESC50_LSB                                                                 21
+#define PHY_ANALOG_SYNTH5_PWDB_ICPRESC50_MASK                                                        0x00e00000
+#define PHY_ANALOG_SYNTH5_PWDB_ICPRESC50_GET(x)                                      (((x) & 0x00e00000) >> 21)
+#define PHY_ANALOG_SYNTH5_PWDB_ICPRESC50_SET(x)                                      (((x) << 21) & 0x00e00000)
+#define PHY_ANALOG_SYNTH5_PWDB_IRVCMON25_MSB                                                                 26
+#define PHY_ANALOG_SYNTH5_PWDB_IRVCMON25_LSB                                                                 24
+#define PHY_ANALOG_SYNTH5_PWDB_IRVCMON25_MASK                                                        0x07000000
+#define PHY_ANALOG_SYNTH5_PWDB_IRVCMON25_GET(x)                                      (((x) & 0x07000000) >> 24)
+#define PHY_ANALOG_SYNTH5_PWDB_IRVCMON25_SET(x)                                      (((x) << 24) & 0x07000000)
+#define PHY_ANALOG_SYNTH5_PWDB_IRPFDCP_MSB                                                                   29
+#define PHY_ANALOG_SYNTH5_PWDB_IRPFDCP_LSB                                                                   27
+#define PHY_ANALOG_SYNTH5_PWDB_IRPFDCP_MASK                                                          0x38000000
+#define PHY_ANALOG_SYNTH5_PWDB_IRPFDCP_GET(x)                                        (((x) & 0x38000000) >> 27)
+#define PHY_ANALOG_SYNTH5_PWDB_IRPFDCP_SET(x)                                        (((x) << 27) & 0x38000000)
+#define PHY_ANALOG_SYNTH5_SPARE5A_MSB                                                                        31
+#define PHY_ANALOG_SYNTH5_SPARE5A_LSB                                                                        30
+#define PHY_ANALOG_SYNTH5_SPARE5A_MASK                                                               0xc0000000
+#define PHY_ANALOG_SYNTH5_SPARE5A_GET(x)                                             (((x) & 0xc0000000) >> 30)
+#define PHY_ANALOG_SYNTH5_SPARE5A_SET(x)                                             (((x) << 30) & 0xc0000000)
+
+/* macros for SYNTH6 */
+#define PHY_ANALOG_SYNTH6_ADDRESS                                                                    0x00000094
+#define PHY_ANALOG_SYNTH6_OFFSET                                                                     0x00000094
+#define PHY_ANALOG_SYNTH6_LOBUF5GTUNE_MSB                                                                     1
+#define PHY_ANALOG_SYNTH6_LOBUF5GTUNE_LSB                                                                     0
+#define PHY_ANALOG_SYNTH6_LOBUF5GTUNE_MASK                                                           0x00000003
+#define PHY_ANALOG_SYNTH6_LOBUF5GTUNE_GET(x)                                          (((x) & 0x00000003) >> 0)
+#define PHY_ANALOG_SYNTH6_LOOP_IP_MSB                                                                         8
+#define PHY_ANALOG_SYNTH6_LOOP_IP_LSB                                                                         2
+#define PHY_ANALOG_SYNTH6_LOOP_IP_MASK                                                               0x000001fc
+#define PHY_ANALOG_SYNTH6_LOOP_IP_GET(x)                                              (((x) & 0x000001fc) >> 2)
+#define PHY_ANALOG_SYNTH6_VC2LOW_MSB                                                                          9
+#define PHY_ANALOG_SYNTH6_VC2LOW_LSB                                                                          9
+#define PHY_ANALOG_SYNTH6_VC2LOW_MASK                                                                0x00000200
+#define PHY_ANALOG_SYNTH6_VC2LOW_GET(x)                                               (((x) & 0x00000200) >> 9)
+#define PHY_ANALOG_SYNTH6_VC2HIGH_MSB                                                                        10
+#define PHY_ANALOG_SYNTH6_VC2HIGH_LSB                                                                        10
+#define PHY_ANALOG_SYNTH6_VC2HIGH_MASK                                                               0x00000400
+#define PHY_ANALOG_SYNTH6_VC2HIGH_GET(x)                                             (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_SYNTH6_RESET_SDM_B_MSB                                                                    11
+#define PHY_ANALOG_SYNTH6_RESET_SDM_B_LSB                                                                    11
+#define PHY_ANALOG_SYNTH6_RESET_SDM_B_MASK                                                           0x00000800
+#define PHY_ANALOG_SYNTH6_RESET_SDM_B_GET(x)                                         (((x) & 0x00000800) >> 11)
+#define PHY_ANALOG_SYNTH6_RESET_PSCOUNTERS_MSB                                                               12
+#define PHY_ANALOG_SYNTH6_RESET_PSCOUNTERS_LSB                                                               12
+#define PHY_ANALOG_SYNTH6_RESET_PSCOUNTERS_MASK                                                      0x00001000
+#define PHY_ANALOG_SYNTH6_RESET_PSCOUNTERS_GET(x)                                    (((x) & 0x00001000) >> 12)
+#define PHY_ANALOG_SYNTH6_RESET_PFD_MSB                                                                      13
+#define PHY_ANALOG_SYNTH6_RESET_PFD_LSB                                                                      13
+#define PHY_ANALOG_SYNTH6_RESET_PFD_MASK                                                             0x00002000
+#define PHY_ANALOG_SYNTH6_RESET_PFD_GET(x)                                           (((x) & 0x00002000) >> 13)
+#define PHY_ANALOG_SYNTH6_RESET_RFD_MSB                                                                      14
+#define PHY_ANALOG_SYNTH6_RESET_RFD_LSB                                                                      14
+#define PHY_ANALOG_SYNTH6_RESET_RFD_MASK                                                             0x00004000
+#define PHY_ANALOG_SYNTH6_RESET_RFD_GET(x)                                           (((x) & 0x00004000) >> 14)
+#define PHY_ANALOG_SYNTH6_SHORT_R_MSB                                                                        15
+#define PHY_ANALOG_SYNTH6_SHORT_R_LSB                                                                        15
+#define PHY_ANALOG_SYNTH6_SHORT_R_MASK                                                               0x00008000
+#define PHY_ANALOG_SYNTH6_SHORT_R_GET(x)                                             (((x) & 0x00008000) >> 15)
+#define PHY_ANALOG_SYNTH6_VCO_CAP_ST_MSB                                                                     23
+#define PHY_ANALOG_SYNTH6_VCO_CAP_ST_LSB                                                                     16
+#define PHY_ANALOG_SYNTH6_VCO_CAP_ST_MASK                                                            0x00ff0000
+#define PHY_ANALOG_SYNTH6_VCO_CAP_ST_GET(x)                                          (((x) & 0x00ff0000) >> 16)
+#define PHY_ANALOG_SYNTH6_PIN_VC_MSB                                                                         24
+#define PHY_ANALOG_SYNTH6_PIN_VC_LSB                                                                         24
+#define PHY_ANALOG_SYNTH6_PIN_VC_MASK                                                                0x01000000
+#define PHY_ANALOG_SYNTH6_PIN_VC_GET(x)                                              (((x) & 0x01000000) >> 24)
+#define PHY_ANALOG_SYNTH6_SYNTH_LOCK_VC_OK_MSB                                                               25
+#define PHY_ANALOG_SYNTH6_SYNTH_LOCK_VC_OK_LSB                                                               25
+#define PHY_ANALOG_SYNTH6_SYNTH_LOCK_VC_OK_MASK                                                      0x02000000
+#define PHY_ANALOG_SYNTH6_SYNTH_LOCK_VC_OK_GET(x)                                    (((x) & 0x02000000) >> 25)
+#define PHY_ANALOG_SYNTH6_CAP_SEARCH_MSB                                                                     26
+#define PHY_ANALOG_SYNTH6_CAP_SEARCH_LSB                                                                     26
+#define PHY_ANALOG_SYNTH6_CAP_SEARCH_MASK                                                            0x04000000
+#define PHY_ANALOG_SYNTH6_CAP_SEARCH_GET(x)                                          (((x) & 0x04000000) >> 26)
+#define PHY_ANALOG_SYNTH6_SYNTH_SM_STATE_MSB                                                                 30
+#define PHY_ANALOG_SYNTH6_SYNTH_SM_STATE_LSB                                                                 27
+#define PHY_ANALOG_SYNTH6_SYNTH_SM_STATE_MASK                                                        0x78000000
+#define PHY_ANALOG_SYNTH6_SYNTH_SM_STATE_GET(x)                                      (((x) & 0x78000000) >> 27)
+#define PHY_ANALOG_SYNTH6_SYNTH_ON_MSB                                                                       31
+#define PHY_ANALOG_SYNTH6_SYNTH_ON_LSB                                                                       31
+#define PHY_ANALOG_SYNTH6_SYNTH_ON_MASK                                                              0x80000000
+#define PHY_ANALOG_SYNTH6_SYNTH_ON_GET(x)                                            (((x) & 0x80000000) >> 31)
+
+/* macros for SYNTH7 */
+#define PHY_ANALOG_SYNTH7_ADDRESS                                                                    0x00000098
+#define PHY_ANALOG_SYNTH7_OFFSET                                                                     0x00000098
+#define PHY_ANALOG_SYNTH7_OVRCHANDECODER_MSB                                                                  0
+#define PHY_ANALOG_SYNTH7_OVRCHANDECODER_LSB                                                                  0
+#define PHY_ANALOG_SYNTH7_OVRCHANDECODER_MASK                                                        0x00000001
+#define PHY_ANALOG_SYNTH7_OVRCHANDECODER_GET(x)                                       (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_SYNTH7_OVRCHANDECODER_SET(x)                                       (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_SYNTH7_FORCE_FRACLSB_MSB                                                                   1
+#define PHY_ANALOG_SYNTH7_FORCE_FRACLSB_LSB                                                                   1
+#define PHY_ANALOG_SYNTH7_FORCE_FRACLSB_MASK                                                         0x00000002
+#define PHY_ANALOG_SYNTH7_FORCE_FRACLSB_GET(x)                                        (((x) & 0x00000002) >> 1)
+#define PHY_ANALOG_SYNTH7_FORCE_FRACLSB_SET(x)                                        (((x) << 1) & 0x00000002)
+#define PHY_ANALOG_SYNTH7_CHANFRAC_MSB                                                                       18
+#define PHY_ANALOG_SYNTH7_CHANFRAC_LSB                                                                        2
+#define PHY_ANALOG_SYNTH7_CHANFRAC_MASK                                                              0x0007fffc
+#define PHY_ANALOG_SYNTH7_CHANFRAC_GET(x)                                             (((x) & 0x0007fffc) >> 2)
+#define PHY_ANALOG_SYNTH7_CHANFRAC_SET(x)                                             (((x) << 2) & 0x0007fffc)
+#define PHY_ANALOG_SYNTH7_CHANSEL_MSB                                                                        27
+#define PHY_ANALOG_SYNTH7_CHANSEL_LSB                                                                        19
+#define PHY_ANALOG_SYNTH7_CHANSEL_MASK                                                               0x0ff80000
+#define PHY_ANALOG_SYNTH7_CHANSEL_GET(x)                                             (((x) & 0x0ff80000) >> 19)
+#define PHY_ANALOG_SYNTH7_CHANSEL_SET(x)                                             (((x) << 19) & 0x0ff80000)
+#define PHY_ANALOG_SYNTH7_AMODEREFSEL_MSB                                                                    29
+#define PHY_ANALOG_SYNTH7_AMODEREFSEL_LSB                                                                    28
+#define PHY_ANALOG_SYNTH7_AMODEREFSEL_MASK                                                           0x30000000
+#define PHY_ANALOG_SYNTH7_AMODEREFSEL_GET(x)                                         (((x) & 0x30000000) >> 28)
+#define PHY_ANALOG_SYNTH7_AMODEREFSEL_SET(x)                                         (((x) << 28) & 0x30000000)
+#define PHY_ANALOG_SYNTH7_FRACMODE_MSB                                                                       30
+#define PHY_ANALOG_SYNTH7_FRACMODE_LSB                                                                       30
+#define PHY_ANALOG_SYNTH7_FRACMODE_MASK                                                              0x40000000
+#define PHY_ANALOG_SYNTH7_FRACMODE_GET(x)                                            (((x) & 0x40000000) >> 30)
+#define PHY_ANALOG_SYNTH7_FRACMODE_SET(x)                                            (((x) << 30) & 0x40000000)
+#define PHY_ANALOG_SYNTH7_LOADSYNTHCHANNEL_MSB                                                               31
+#define PHY_ANALOG_SYNTH7_LOADSYNTHCHANNEL_LSB                                                               31
+#define PHY_ANALOG_SYNTH7_LOADSYNTHCHANNEL_MASK                                                      0x80000000
+#define PHY_ANALOG_SYNTH7_LOADSYNTHCHANNEL_GET(x)                                    (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_SYNTH7_LOADSYNTHCHANNEL_SET(x)                                    (((x) << 31) & 0x80000000)
+
+/* macros for SYNTH8 */
+#define PHY_ANALOG_SYNTH8_ADDRESS                                                                    0x0000009c
+#define PHY_ANALOG_SYNTH8_OFFSET                                                                     0x0000009c
+#define PHY_ANALOG_SYNTH8_CPSTEERING_EN_FRACN_MSB                                                             0
+#define PHY_ANALOG_SYNTH8_CPSTEERING_EN_FRACN_LSB                                                             0
+#define PHY_ANALOG_SYNTH8_CPSTEERING_EN_FRACN_MASK                                                   0x00000001
+#define PHY_ANALOG_SYNTH8_CPSTEERING_EN_FRACN_GET(x)                                  (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_SYNTH8_CPSTEERING_EN_FRACN_SET(x)                                  (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_SYNTH8_LOOP_ICPB_MSB                                                                       7
+#define PHY_ANALOG_SYNTH8_LOOP_ICPB_LSB                                                                       1
+#define PHY_ANALOG_SYNTH8_LOOP_ICPB_MASK                                                             0x000000fe
+#define PHY_ANALOG_SYNTH8_LOOP_ICPB_GET(x)                                            (((x) & 0x000000fe) >> 1)
+#define PHY_ANALOG_SYNTH8_LOOP_ICPB_SET(x)                                            (((x) << 1) & 0x000000fe)
+#define PHY_ANALOG_SYNTH8_LOOP_CSB_MSB                                                                       11
+#define PHY_ANALOG_SYNTH8_LOOP_CSB_LSB                                                                        8
+#define PHY_ANALOG_SYNTH8_LOOP_CSB_MASK                                                              0x00000f00
+#define PHY_ANALOG_SYNTH8_LOOP_CSB_GET(x)                                             (((x) & 0x00000f00) >> 8)
+#define PHY_ANALOG_SYNTH8_LOOP_CSB_SET(x)                                             (((x) << 8) & 0x00000f00)
+#define PHY_ANALOG_SYNTH8_LOOP_RSB_MSB                                                                       16
+#define PHY_ANALOG_SYNTH8_LOOP_RSB_LSB                                                                       12
+#define PHY_ANALOG_SYNTH8_LOOP_RSB_MASK                                                              0x0001f000
+#define PHY_ANALOG_SYNTH8_LOOP_RSB_GET(x)                                            (((x) & 0x0001f000) >> 12)
+#define PHY_ANALOG_SYNTH8_LOOP_RSB_SET(x)                                            (((x) << 12) & 0x0001f000)
+#define PHY_ANALOG_SYNTH8_LOOP_CPB_MSB                                                                       21
+#define PHY_ANALOG_SYNTH8_LOOP_CPB_LSB                                                                       17
+#define PHY_ANALOG_SYNTH8_LOOP_CPB_MASK                                                              0x003e0000
+#define PHY_ANALOG_SYNTH8_LOOP_CPB_GET(x)                                            (((x) & 0x003e0000) >> 17)
+#define PHY_ANALOG_SYNTH8_LOOP_CPB_SET(x)                                            (((x) << 17) & 0x003e0000)
+#define PHY_ANALOG_SYNTH8_LOOP_3RD_ORDER_RB_MSB                                                              26
+#define PHY_ANALOG_SYNTH8_LOOP_3RD_ORDER_RB_LSB                                                              22
+#define PHY_ANALOG_SYNTH8_LOOP_3RD_ORDER_RB_MASK                                                     0x07c00000
+#define PHY_ANALOG_SYNTH8_LOOP_3RD_ORDER_RB_GET(x)                                   (((x) & 0x07c00000) >> 22)
+#define PHY_ANALOG_SYNTH8_LOOP_3RD_ORDER_RB_SET(x)                                   (((x) << 22) & 0x07c00000)
+#define PHY_ANALOG_SYNTH8_REFDIVB_MSB                                                                        31
+#define PHY_ANALOG_SYNTH8_REFDIVB_LSB                                                                        27
+#define PHY_ANALOG_SYNTH8_REFDIVB_MASK                                                               0xf8000000
+#define PHY_ANALOG_SYNTH8_REFDIVB_GET(x)                                             (((x) & 0xf8000000) >> 27)
+#define PHY_ANALOG_SYNTH8_REFDIVB_SET(x)                                             (((x) << 27) & 0xf8000000)
+
+/* macros for SYNTH9 */
+#define PHY_ANALOG_SYNTH9_ADDRESS                                                                    0x000000a0
+#define PHY_ANALOG_SYNTH9_OFFSET                                                                     0x000000a0
+#define PHY_ANALOG_SYNTH9_PFDDELAY_INTN_MSB                                                                   0
+#define PHY_ANALOG_SYNTH9_PFDDELAY_INTN_LSB                                                                   0
+#define PHY_ANALOG_SYNTH9_PFDDELAY_INTN_MASK                                                         0x00000001
+#define PHY_ANALOG_SYNTH9_PFDDELAY_INTN_GET(x)                                        (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_SYNTH9_PFDDELAY_INTN_SET(x)                                        (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_SYNTH9_SLOPE_ICPA0_MSB                                                                     3
+#define PHY_ANALOG_SYNTH9_SLOPE_ICPA0_LSB                                                                     1
+#define PHY_ANALOG_SYNTH9_SLOPE_ICPA0_MASK                                                           0x0000000e
+#define PHY_ANALOG_SYNTH9_SLOPE_ICPA0_GET(x)                                          (((x) & 0x0000000e) >> 1)
+#define PHY_ANALOG_SYNTH9_SLOPE_ICPA0_SET(x)                                          (((x) << 1) & 0x0000000e)
+#define PHY_ANALOG_SYNTH9_LOOP_ICPA0_MSB                                                                      7
+#define PHY_ANALOG_SYNTH9_LOOP_ICPA0_LSB                                                                      4
+#define PHY_ANALOG_SYNTH9_LOOP_ICPA0_MASK                                                            0x000000f0
+#define PHY_ANALOG_SYNTH9_LOOP_ICPA0_GET(x)                                           (((x) & 0x000000f0) >> 4)
+#define PHY_ANALOG_SYNTH9_LOOP_ICPA0_SET(x)                                           (((x) << 4) & 0x000000f0)
+#define PHY_ANALOG_SYNTH9_LOOP_CSA0_MSB                                                                      11
+#define PHY_ANALOG_SYNTH9_LOOP_CSA0_LSB                                                                       8
+#define PHY_ANALOG_SYNTH9_LOOP_CSA0_MASK                                                             0x00000f00
+#define PHY_ANALOG_SYNTH9_LOOP_CSA0_GET(x)                                            (((x) & 0x00000f00) >> 8)
+#define PHY_ANALOG_SYNTH9_LOOP_CSA0_SET(x)                                            (((x) << 8) & 0x00000f00)
+#define PHY_ANALOG_SYNTH9_LOOP_RSA0_MSB                                                                      16
+#define PHY_ANALOG_SYNTH9_LOOP_RSA0_LSB                                                                      12
+#define PHY_ANALOG_SYNTH9_LOOP_RSA0_MASK                                                             0x0001f000
+#define PHY_ANALOG_SYNTH9_LOOP_RSA0_GET(x)                                           (((x) & 0x0001f000) >> 12)
+#define PHY_ANALOG_SYNTH9_LOOP_RSA0_SET(x)                                           (((x) << 12) & 0x0001f000)
+#define PHY_ANALOG_SYNTH9_LOOP_CPA0_MSB                                                                      21
+#define PHY_ANALOG_SYNTH9_LOOP_CPA0_LSB                                                                      17
+#define PHY_ANALOG_SYNTH9_LOOP_CPA0_MASK                                                             0x003e0000
+#define PHY_ANALOG_SYNTH9_LOOP_CPA0_GET(x)                                           (((x) & 0x003e0000) >> 17)
+#define PHY_ANALOG_SYNTH9_LOOP_CPA0_SET(x)                                           (((x) << 17) & 0x003e0000)
+#define PHY_ANALOG_SYNTH9_LOOP_3RD_ORDER_RA_MSB                                                              26
+#define PHY_ANALOG_SYNTH9_LOOP_3RD_ORDER_RA_LSB                                                              22
+#define PHY_ANALOG_SYNTH9_LOOP_3RD_ORDER_RA_MASK                                                     0x07c00000
+#define PHY_ANALOG_SYNTH9_LOOP_3RD_ORDER_RA_GET(x)                                   (((x) & 0x07c00000) >> 22)
+#define PHY_ANALOG_SYNTH9_LOOP_3RD_ORDER_RA_SET(x)                                   (((x) << 22) & 0x07c00000)
+#define PHY_ANALOG_SYNTH9_REFDIVA_MSB                                                                        31
+#define PHY_ANALOG_SYNTH9_REFDIVA_LSB                                                                        27
+#define PHY_ANALOG_SYNTH9_REFDIVA_MASK                                                               0xf8000000
+#define PHY_ANALOG_SYNTH9_REFDIVA_GET(x)                                             (((x) & 0xf8000000) >> 27)
+#define PHY_ANALOG_SYNTH9_REFDIVA_SET(x)                                             (((x) << 27) & 0xf8000000)
+
+/* macros for SYNTH10 */
+#define PHY_ANALOG_SYNTH10_ADDRESS                                                                   0x000000a4
+#define PHY_ANALOG_SYNTH10_OFFSET                                                                    0x000000a4
+#define PHY_ANALOG_SYNTH10_SPARE10A_MSB                                                                       0
+#define PHY_ANALOG_SYNTH10_SPARE10A_LSB                                                                       0
+#define PHY_ANALOG_SYNTH10_SPARE10A_MASK                                                             0x00000001
+#define PHY_ANALOG_SYNTH10_SPARE10A_GET(x)                                            (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_SYNTH10_SPARE10A_SET(x)                                            (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_SYNTH10_PWDB_ICLOBIAS50_MSB                                                                3
+#define PHY_ANALOG_SYNTH10_PWDB_ICLOBIAS50_LSB                                                                1
+#define PHY_ANALOG_SYNTH10_PWDB_ICLOBIAS50_MASK                                                      0x0000000e
+#define PHY_ANALOG_SYNTH10_PWDB_ICLOBIAS50_GET(x)                                     (((x) & 0x0000000e) >> 1)
+#define PHY_ANALOG_SYNTH10_PWDB_ICLOBIAS50_SET(x)                                     (((x) << 1) & 0x0000000e)
+#define PHY_ANALOG_SYNTH10_EN_2X_LOOPFILT_MSB                                                                 4
+#define PHY_ANALOG_SYNTH10_EN_2X_LOOPFILT_LSB                                                                 4
+#define PHY_ANALOG_SYNTH10_EN_2X_LOOPFILT_MASK                                                       0x00000010
+#define PHY_ANALOG_SYNTH10_EN_2X_LOOPFILT_GET(x)                                      (((x) & 0x00000010) >> 4)
+#define PHY_ANALOG_SYNTH10_EN_2X_LOOPFILT_SET(x)                                      (((x) << 4) & 0x00000010)
+#define PHY_ANALOG_SYNTH10_PWDB_IRSPARE25_MSB                                                                 7
+#define PHY_ANALOG_SYNTH10_PWDB_IRSPARE25_LSB                                                                 5
+#define PHY_ANALOG_SYNTH10_PWDB_IRSPARE25_MASK                                                       0x000000e0
+#define PHY_ANALOG_SYNTH10_PWDB_IRSPARE25_GET(x)                                      (((x) & 0x000000e0) >> 5)
+#define PHY_ANALOG_SYNTH10_PWDB_IRSPARE25_SET(x)                                      (((x) << 5) & 0x000000e0)
+#define PHY_ANALOG_SYNTH10_PWDB_ICSPARE25_MSB                                                                10
+#define PHY_ANALOG_SYNTH10_PWDB_ICSPARE25_LSB                                                                 8
+#define PHY_ANALOG_SYNTH10_PWDB_ICSPARE25_MASK                                                       0x00000700
+#define PHY_ANALOG_SYNTH10_PWDB_ICSPARE25_GET(x)                                      (((x) & 0x00000700) >> 8)
+#define PHY_ANALOG_SYNTH10_PWDB_ICSPARE25_SET(x)                                      (((x) << 8) & 0x00000700)
+#define PHY_ANALOG_SYNTH10_SLOPE_ICPA1_MSB                                                                   13
+#define PHY_ANALOG_SYNTH10_SLOPE_ICPA1_LSB                                                                   11
+#define PHY_ANALOG_SYNTH10_SLOPE_ICPA1_MASK                                                          0x00003800
+#define PHY_ANALOG_SYNTH10_SLOPE_ICPA1_GET(x)                                        (((x) & 0x00003800) >> 11)
+#define PHY_ANALOG_SYNTH10_SLOPE_ICPA1_SET(x)                                        (((x) << 11) & 0x00003800)
+#define PHY_ANALOG_SYNTH10_LOOP_ICPA1_MSB                                                                    17
+#define PHY_ANALOG_SYNTH10_LOOP_ICPA1_LSB                                                                    14
+#define PHY_ANALOG_SYNTH10_LOOP_ICPA1_MASK                                                           0x0003c000
+#define PHY_ANALOG_SYNTH10_LOOP_ICPA1_GET(x)                                         (((x) & 0x0003c000) >> 14)
+#define PHY_ANALOG_SYNTH10_LOOP_ICPA1_SET(x)                                         (((x) << 14) & 0x0003c000)
+#define PHY_ANALOG_SYNTH10_LOOP_CSA1_MSB                                                                     21
+#define PHY_ANALOG_SYNTH10_LOOP_CSA1_LSB                                                                     18
+#define PHY_ANALOG_SYNTH10_LOOP_CSA1_MASK                                                            0x003c0000
+#define PHY_ANALOG_SYNTH10_LOOP_CSA1_GET(x)                                          (((x) & 0x003c0000) >> 18)
+#define PHY_ANALOG_SYNTH10_LOOP_CSA1_SET(x)                                          (((x) << 18) & 0x003c0000)
+#define PHY_ANALOG_SYNTH10_LOOP_RSA1_MSB                                                                     26
+#define PHY_ANALOG_SYNTH10_LOOP_RSA1_LSB                                                                     22
+#define PHY_ANALOG_SYNTH10_LOOP_RSA1_MASK                                                            0x07c00000
+#define PHY_ANALOG_SYNTH10_LOOP_RSA1_GET(x)                                          (((x) & 0x07c00000) >> 22)
+#define PHY_ANALOG_SYNTH10_LOOP_RSA1_SET(x)                                          (((x) << 22) & 0x07c00000)
+#define PHY_ANALOG_SYNTH10_LOOP_CPA1_MSB                                                                     31
+#define PHY_ANALOG_SYNTH10_LOOP_CPA1_LSB                                                                     27
+#define PHY_ANALOG_SYNTH10_LOOP_CPA1_MASK                                                            0xf8000000
+#define PHY_ANALOG_SYNTH10_LOOP_CPA1_GET(x)                                          (((x) & 0xf8000000) >> 27)
+#define PHY_ANALOG_SYNTH10_LOOP_CPA1_SET(x)                                          (((x) << 27) & 0xf8000000)
+
+/* macros for SYNTH11 */
+#define PHY_ANALOG_SYNTH11_ADDRESS                                                                   0x000000a8
+#define PHY_ANALOG_SYNTH11_OFFSET                                                                    0x000000a8
+#define PHY_ANALOG_SYNTH11_SPARE11A_MSB                                                                       4
+#define PHY_ANALOG_SYNTH11_SPARE11A_LSB                                                                       0
+#define PHY_ANALOG_SYNTH11_SPARE11A_MASK                                                             0x0000001f
+#define PHY_ANALOG_SYNTH11_SPARE11A_GET(x)                                            (((x) & 0x0000001f) >> 0)
+#define PHY_ANALOG_SYNTH11_SPARE11A_SET(x)                                            (((x) << 0) & 0x0000001f)
+#define PHY_ANALOG_SYNTH11_FORCE_LOBUF5G_ON_MSB                                                               5
+#define PHY_ANALOG_SYNTH11_FORCE_LOBUF5G_ON_LSB                                                               5
+#define PHY_ANALOG_SYNTH11_FORCE_LOBUF5G_ON_MASK                                                     0x00000020
+#define PHY_ANALOG_SYNTH11_FORCE_LOBUF5G_ON_GET(x)                                    (((x) & 0x00000020) >> 5)
+#define PHY_ANALOG_SYNTH11_FORCE_LOBUF5G_ON_SET(x)                                    (((x) << 5) & 0x00000020)
+#define PHY_ANALOG_SYNTH11_LOREFSEL_MSB                                                                       7
+#define PHY_ANALOG_SYNTH11_LOREFSEL_LSB                                                                       6
+#define PHY_ANALOG_SYNTH11_LOREFSEL_MASK                                                             0x000000c0
+#define PHY_ANALOG_SYNTH11_LOREFSEL_GET(x)                                            (((x) & 0x000000c0) >> 6)
+#define PHY_ANALOG_SYNTH11_LOREFSEL_SET(x)                                            (((x) << 6) & 0x000000c0)
+#define PHY_ANALOG_SYNTH11_LOBUF2GTUNE_MSB                                                                    9
+#define PHY_ANALOG_SYNTH11_LOBUF2GTUNE_LSB                                                                    8
+#define PHY_ANALOG_SYNTH11_LOBUF2GTUNE_MASK                                                          0x00000300
+#define PHY_ANALOG_SYNTH11_LOBUF2GTUNE_GET(x)                                         (((x) & 0x00000300) >> 8)
+#define PHY_ANALOG_SYNTH11_LOBUF2GTUNE_SET(x)                                         (((x) << 8) & 0x00000300)
+#define PHY_ANALOG_SYNTH11_CPSTEERING_MODE_MSB                                                               10
+#define PHY_ANALOG_SYNTH11_CPSTEERING_MODE_LSB                                                               10
+#define PHY_ANALOG_SYNTH11_CPSTEERING_MODE_MASK                                                      0x00000400
+#define PHY_ANALOG_SYNTH11_CPSTEERING_MODE_GET(x)                                    (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_SYNTH11_CPSTEERING_MODE_SET(x)                                    (((x) << 10) & 0x00000400)
+#define PHY_ANALOG_SYNTH11_SLOPE_ICPA2_MSB                                                                   13
+#define PHY_ANALOG_SYNTH11_SLOPE_ICPA2_LSB                                                                   11
+#define PHY_ANALOG_SYNTH11_SLOPE_ICPA2_MASK                                                          0x00003800
+#define PHY_ANALOG_SYNTH11_SLOPE_ICPA2_GET(x)                                        (((x) & 0x00003800) >> 11)
+#define PHY_ANALOG_SYNTH11_SLOPE_ICPA2_SET(x)                                        (((x) << 11) & 0x00003800)
+#define PHY_ANALOG_SYNTH11_LOOP_ICPA2_MSB                                                                    17
+#define PHY_ANALOG_SYNTH11_LOOP_ICPA2_LSB                                                                    14
+#define PHY_ANALOG_SYNTH11_LOOP_ICPA2_MASK                                                           0x0003c000
+#define PHY_ANALOG_SYNTH11_LOOP_ICPA2_GET(x)                                         (((x) & 0x0003c000) >> 14)
+#define PHY_ANALOG_SYNTH11_LOOP_ICPA2_SET(x)                                         (((x) << 14) & 0x0003c000)
+#define PHY_ANALOG_SYNTH11_LOOP_CSA2_MSB                                                                     21
+#define PHY_ANALOG_SYNTH11_LOOP_CSA2_LSB                                                                     18
+#define PHY_ANALOG_SYNTH11_LOOP_CSA2_MASK                                                            0x003c0000
+#define PHY_ANALOG_SYNTH11_LOOP_CSA2_GET(x)                                          (((x) & 0x003c0000) >> 18)
+#define PHY_ANALOG_SYNTH11_LOOP_CSA2_SET(x)                                          (((x) << 18) & 0x003c0000)
+#define PHY_ANALOG_SYNTH11_LOOP_RSA2_MSB                                                                     26
+#define PHY_ANALOG_SYNTH11_LOOP_RSA2_LSB                                                                     22
+#define PHY_ANALOG_SYNTH11_LOOP_RSA2_MASK                                                            0x07c00000
+#define PHY_ANALOG_SYNTH11_LOOP_RSA2_GET(x)                                          (((x) & 0x07c00000) >> 22)
+#define PHY_ANALOG_SYNTH11_LOOP_RSA2_SET(x)                                          (((x) << 22) & 0x07c00000)
+#define PHY_ANALOG_SYNTH11_LOOP_CPA2_MSB                                                                     31
+#define PHY_ANALOG_SYNTH11_LOOP_CPA2_LSB                                                                     27
+#define PHY_ANALOG_SYNTH11_LOOP_CPA2_MASK                                                            0xf8000000
+#define PHY_ANALOG_SYNTH11_LOOP_CPA2_GET(x)                                          (((x) & 0xf8000000) >> 27)
+#define PHY_ANALOG_SYNTH11_LOOP_CPA2_SET(x)                                          (((x) << 27) & 0xf8000000)
+
+/* macros for SYNTH12 */
+#define PHY_ANALOG_SYNTH12_ADDRESS                                                                   0x000000ac
+#define PHY_ANALOG_SYNTH12_OFFSET                                                                    0x000000ac
+#define PHY_ANALOG_SYNTH12_SPARE12A_MSB                                                                      17
+#define PHY_ANALOG_SYNTH12_SPARE12A_LSB                                                                       0
+#define PHY_ANALOG_SYNTH12_SPARE12A_MASK                                                             0x0003ffff
+#define PHY_ANALOG_SYNTH12_SPARE12A_GET(x)                                            (((x) & 0x0003ffff) >> 0)
+#define PHY_ANALOG_SYNTH12_SPARE12A_SET(x)                                            (((x) << 0) & 0x0003ffff)
+#define PHY_ANALOG_SYNTH12_STRCONT_MSB                                                                       18
+#define PHY_ANALOG_SYNTH12_STRCONT_LSB                                                                       18
+#define PHY_ANALOG_SYNTH12_STRCONT_MASK                                                              0x00040000
+#define PHY_ANALOG_SYNTH12_STRCONT_GET(x)                                            (((x) & 0x00040000) >> 18)
+#define PHY_ANALOG_SYNTH12_STRCONT_SET(x)                                            (((x) << 18) & 0x00040000)
+#define PHY_ANALOG_SYNTH12_VREFMUL3_MSB                                                                      22
+#define PHY_ANALOG_SYNTH12_VREFMUL3_LSB                                                                      19
+#define PHY_ANALOG_SYNTH12_VREFMUL3_MASK                                                             0x00780000
+#define PHY_ANALOG_SYNTH12_VREFMUL3_GET(x)                                           (((x) & 0x00780000) >> 19)
+#define PHY_ANALOG_SYNTH12_VREFMUL3_SET(x)                                           (((x) << 19) & 0x00780000)
+#define PHY_ANALOG_SYNTH12_VREFMUL2_MSB                                                                      26
+#define PHY_ANALOG_SYNTH12_VREFMUL2_LSB                                                                      23
+#define PHY_ANALOG_SYNTH12_VREFMUL2_MASK                                                             0x07800000
+#define PHY_ANALOG_SYNTH12_VREFMUL2_GET(x)                                           (((x) & 0x07800000) >> 23)
+#define PHY_ANALOG_SYNTH12_VREFMUL2_SET(x)                                           (((x) << 23) & 0x07800000)
+#define PHY_ANALOG_SYNTH12_VREFMUL1_MSB                                                                      30
+#define PHY_ANALOG_SYNTH12_VREFMUL1_LSB                                                                      27
+#define PHY_ANALOG_SYNTH12_VREFMUL1_MASK                                                             0x78000000
+#define PHY_ANALOG_SYNTH12_VREFMUL1_GET(x)                                           (((x) & 0x78000000) >> 27)
+#define PHY_ANALOG_SYNTH12_VREFMUL1_SET(x)                                           (((x) << 27) & 0x78000000)
+#define PHY_ANALOG_SYNTH12_CLK_DOUBLER_EN_MSB                                                                31
+#define PHY_ANALOG_SYNTH12_CLK_DOUBLER_EN_LSB                                                                31
+#define PHY_ANALOG_SYNTH12_CLK_DOUBLER_EN_MASK                                                       0x80000000
+#define PHY_ANALOG_SYNTH12_CLK_DOUBLER_EN_GET(x)                                     (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_SYNTH12_CLK_DOUBLER_EN_SET(x)                                     (((x) << 31) & 0x80000000)
+
+/* macros for BIAS1 */
+#define PHY_ANALOG_BIAS1_ADDRESS                                                                     0x000000c0
+#define PHY_ANALOG_BIAS1_OFFSET                                                                      0x000000c0
+#define PHY_ANALOG_BIAS1_SPARE1_MSB                                                                           6
+#define PHY_ANALOG_BIAS1_SPARE1_LSB                                                                           0
+#define PHY_ANALOG_BIAS1_SPARE1_MASK                                                                 0x0000007f
+#define PHY_ANALOG_BIAS1_SPARE1_GET(x)                                                (((x) & 0x0000007f) >> 0)
+#define PHY_ANALOG_BIAS1_SPARE1_SET(x)                                                (((x) << 0) & 0x0000007f)
+#define PHY_ANALOG_BIAS1_PWD_IC25V2IQ_MSB                                                                     9
+#define PHY_ANALOG_BIAS1_PWD_IC25V2IQ_LSB                                                                     7
+#define PHY_ANALOG_BIAS1_PWD_IC25V2IQ_MASK                                                           0x00000380
+#define PHY_ANALOG_BIAS1_PWD_IC25V2IQ_GET(x)                                          (((x) & 0x00000380) >> 7)
+#define PHY_ANALOG_BIAS1_PWD_IC25V2IQ_SET(x)                                          (((x) << 7) & 0x00000380)
+#define PHY_ANALOG_BIAS1_PWD_IC25V2II_MSB                                                                    12
+#define PHY_ANALOG_BIAS1_PWD_IC25V2II_LSB                                                                    10
+#define PHY_ANALOG_BIAS1_PWD_IC25V2II_MASK                                                           0x00001c00
+#define PHY_ANALOG_BIAS1_PWD_IC25V2II_GET(x)                                         (((x) & 0x00001c00) >> 10)
+#define PHY_ANALOG_BIAS1_PWD_IC25V2II_SET(x)                                         (((x) << 10) & 0x00001c00)
+#define PHY_ANALOG_BIAS1_PWD_IC25BB_MSB                                                                      15
+#define PHY_ANALOG_BIAS1_PWD_IC25BB_LSB                                                                      13
+#define PHY_ANALOG_BIAS1_PWD_IC25BB_MASK                                                             0x0000e000
+#define PHY_ANALOG_BIAS1_PWD_IC25BB_GET(x)                                           (((x) & 0x0000e000) >> 13)
+#define PHY_ANALOG_BIAS1_PWD_IC25BB_SET(x)                                           (((x) << 13) & 0x0000e000)
+#define PHY_ANALOG_BIAS1_PWD_IC25DAC_MSB                                                                     18
+#define PHY_ANALOG_BIAS1_PWD_IC25DAC_LSB                                                                     16
+#define PHY_ANALOG_BIAS1_PWD_IC25DAC_MASK                                                            0x00070000
+#define PHY_ANALOG_BIAS1_PWD_IC25DAC_GET(x)                                          (((x) & 0x00070000) >> 16)
+#define PHY_ANALOG_BIAS1_PWD_IC25DAC_SET(x)                                          (((x) << 16) & 0x00070000)
+#define PHY_ANALOG_BIAS1_PWD_IC25FIR_MSB                                                                     21
+#define PHY_ANALOG_BIAS1_PWD_IC25FIR_LSB                                                                     19
+#define PHY_ANALOG_BIAS1_PWD_IC25FIR_MASK                                                            0x00380000
+#define PHY_ANALOG_BIAS1_PWD_IC25FIR_GET(x)                                          (((x) & 0x00380000) >> 19)
+#define PHY_ANALOG_BIAS1_PWD_IC25FIR_SET(x)                                          (((x) << 19) & 0x00380000)
+#define PHY_ANALOG_BIAS1_PWD_IC25ADC_MSB                                                                     24
+#define PHY_ANALOG_BIAS1_PWD_IC25ADC_LSB                                                                     22
+#define PHY_ANALOG_BIAS1_PWD_IC25ADC_MASK                                                            0x01c00000
+#define PHY_ANALOG_BIAS1_PWD_IC25ADC_GET(x)                                          (((x) & 0x01c00000) >> 22)
+#define PHY_ANALOG_BIAS1_PWD_IC25ADC_SET(x)                                          (((x) << 22) & 0x01c00000)
+#define PHY_ANALOG_BIAS1_BIAS_SEL_MSB                                                                        31
+#define PHY_ANALOG_BIAS1_BIAS_SEL_LSB                                                                        25
+#define PHY_ANALOG_BIAS1_BIAS_SEL_MASK                                                               0xfe000000
+#define PHY_ANALOG_BIAS1_BIAS_SEL_GET(x)                                             (((x) & 0xfe000000) >> 25)
+#define PHY_ANALOG_BIAS1_BIAS_SEL_SET(x)                                             (((x) << 25) & 0xfe000000)
+
+/* macros for BIAS2 */
+#define PHY_ANALOG_BIAS2_ADDRESS                                                                     0x000000c4
+#define PHY_ANALOG_BIAS2_OFFSET                                                                      0x000000c4
+#define PHY_ANALOG_BIAS2_SPARE2_MSB                                                                           4
+#define PHY_ANALOG_BIAS2_SPARE2_LSB                                                                           0
+#define PHY_ANALOG_BIAS2_SPARE2_MASK                                                                 0x0000001f
+#define PHY_ANALOG_BIAS2_SPARE2_GET(x)                                                (((x) & 0x0000001f) >> 0)
+#define PHY_ANALOG_BIAS2_SPARE2_SET(x)                                                (((x) << 0) & 0x0000001f)
+#define PHY_ANALOG_BIAS2_PWD_IC25XTALREG_MSB                                                                  7
+#define PHY_ANALOG_BIAS2_PWD_IC25XTALREG_LSB                                                                  5
+#define PHY_ANALOG_BIAS2_PWD_IC25XTALREG_MASK                                                        0x000000e0
+#define PHY_ANALOG_BIAS2_PWD_IC25XTALREG_GET(x)                                       (((x) & 0x000000e0) >> 5)
+#define PHY_ANALOG_BIAS2_PWD_IC25XTALREG_SET(x)                                       (((x) << 5) & 0x000000e0)
+#define PHY_ANALOG_BIAS2_PWD_IC25XTAL_MSB                                                                    10
+#define PHY_ANALOG_BIAS2_PWD_IC25XTAL_LSB                                                                     8
+#define PHY_ANALOG_BIAS2_PWD_IC25XTAL_MASK                                                           0x00000700
+#define PHY_ANALOG_BIAS2_PWD_IC25XTAL_GET(x)                                          (((x) & 0x00000700) >> 8)
+#define PHY_ANALOG_BIAS2_PWD_IC25XTAL_SET(x)                                          (((x) << 8) & 0x00000700)
+#define PHY_ANALOG_BIAS2_PWD_IC25TXRF_MSB                                                                    13
+#define PHY_ANALOG_BIAS2_PWD_IC25TXRF_LSB                                                                    11
+#define PHY_ANALOG_BIAS2_PWD_IC25TXRF_MASK                                                           0x00003800
+#define PHY_ANALOG_BIAS2_PWD_IC25TXRF_GET(x)                                         (((x) & 0x00003800) >> 11)
+#define PHY_ANALOG_BIAS2_PWD_IC25TXRF_SET(x)                                         (((x) << 11) & 0x00003800)
+#define PHY_ANALOG_BIAS2_PWD_IC25RXRF_MSB                                                                    16
+#define PHY_ANALOG_BIAS2_PWD_IC25RXRF_LSB                                                                    14
+#define PHY_ANALOG_BIAS2_PWD_IC25RXRF_MASK                                                           0x0001c000
+#define PHY_ANALOG_BIAS2_PWD_IC25RXRF_GET(x)                                         (((x) & 0x0001c000) >> 14)
+#define PHY_ANALOG_BIAS2_PWD_IC25RXRF_SET(x)                                         (((x) << 14) & 0x0001c000)
+#define PHY_ANALOG_BIAS2_PWD_IC50SYNTH_MSB                                                                   19
+#define PHY_ANALOG_BIAS2_PWD_IC50SYNTH_LSB                                                                   17
+#define PHY_ANALOG_BIAS2_PWD_IC50SYNTH_MASK                                                          0x000e0000
+#define PHY_ANALOG_BIAS2_PWD_IC50SYNTH_GET(x)                                        (((x) & 0x000e0000) >> 17)
+#define PHY_ANALOG_BIAS2_PWD_IC50SYNTH_SET(x)                                        (((x) << 17) & 0x000e0000)
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLREG_MSB                                                                  22
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLREG_LSB                                                                  20
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLREG_MASK                                                         0x00700000
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLREG_GET(x)                                       (((x) & 0x00700000) >> 20)
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLREG_SET(x)                                       (((x) << 20) & 0x00700000)
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP2_MSB                                                                  25
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP2_LSB                                                                  23
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP2_MASK                                                         0x03800000
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP2_GET(x)                                       (((x) & 0x03800000) >> 23)
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP2_SET(x)                                       (((x) << 23) & 0x03800000)
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP_MSB                                                                   28
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP_LSB                                                                   26
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP_MASK                                                          0x1c000000
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP_GET(x)                                        (((x) & 0x1c000000) >> 26)
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP_SET(x)                                        (((x) << 26) & 0x1c000000)
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLGM_MSB                                                                   31
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLGM_LSB                                                                   29
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLGM_MASK                                                          0xe0000000
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLGM_GET(x)                                        (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLGM_SET(x)                                        (((x) << 29) & 0xe0000000)
+
+/* macros for BIAS3 */
+#define PHY_ANALOG_BIAS3_ADDRESS                                                                     0x000000c8
+#define PHY_ANALOG_BIAS3_OFFSET                                                                      0x000000c8
+#define PHY_ANALOG_BIAS3_SPARE3_MSB                                                                           1
+#define PHY_ANALOG_BIAS3_SPARE3_LSB                                                                           0
+#define PHY_ANALOG_BIAS3_SPARE3_MASK                                                                 0x00000003
+#define PHY_ANALOG_BIAS3_SPARE3_GET(x)                                                (((x) & 0x00000003) >> 0)
+#define PHY_ANALOG_BIAS3_SPARE3_SET(x)                                                (((x) << 0) & 0x00000003)
+#define PHY_ANALOG_BIAS3_PWD_IR25XTALREG_MSB                                                                  4
+#define PHY_ANALOG_BIAS3_PWD_IR25XTALREG_LSB                                                                  2
+#define PHY_ANALOG_BIAS3_PWD_IR25XTALREG_MASK                                                        0x0000001c
+#define PHY_ANALOG_BIAS3_PWD_IR25XTALREG_GET(x)                                       (((x) & 0x0000001c) >> 2)
+#define PHY_ANALOG_BIAS3_PWD_IR25XTALREG_SET(x)                                       (((x) << 2) & 0x0000001c)
+#define PHY_ANALOG_BIAS3_PWD_IR25TXRF_MSB                                                                     7
+#define PHY_ANALOG_BIAS3_PWD_IR25TXRF_LSB                                                                     5
+#define PHY_ANALOG_BIAS3_PWD_IR25TXRF_MASK                                                           0x000000e0
+#define PHY_ANALOG_BIAS3_PWD_IR25TXRF_GET(x)                                          (((x) & 0x000000e0) >> 5)
+#define PHY_ANALOG_BIAS3_PWD_IR25TXRF_SET(x)                                          (((x) << 5) & 0x000000e0)
+#define PHY_ANALOG_BIAS3_PWD_IR25RXRF_MSB                                                                    10
+#define PHY_ANALOG_BIAS3_PWD_IR25RXRF_LSB                                                                     8
+#define PHY_ANALOG_BIAS3_PWD_IR25RXRF_MASK                                                           0x00000700
+#define PHY_ANALOG_BIAS3_PWD_IR25RXRF_GET(x)                                          (((x) & 0x00000700) >> 8)
+#define PHY_ANALOG_BIAS3_PWD_IR25RXRF_SET(x)                                          (((x) << 8) & 0x00000700)
+#define PHY_ANALOG_BIAS3_PWD_IR50SYNTH_MSB                                                                   13
+#define PHY_ANALOG_BIAS3_PWD_IR50SYNTH_LSB                                                                   11
+#define PHY_ANALOG_BIAS3_PWD_IR50SYNTH_MASK                                                          0x00003800
+#define PHY_ANALOG_BIAS3_PWD_IR50SYNTH_GET(x)                                        (((x) & 0x00003800) >> 11)
+#define PHY_ANALOG_BIAS3_PWD_IR50SYNTH_SET(x)                                        (((x) << 11) & 0x00003800)
+#define PHY_ANALOG_BIAS3_PWD_IR25PLLREG_MSB                                                                  16
+#define PHY_ANALOG_BIAS3_PWD_IR25PLLREG_LSB                                                                  14
+#define PHY_ANALOG_BIAS3_PWD_IR25PLLREG_MASK                                                         0x0001c000
+#define PHY_ANALOG_BIAS3_PWD_IR25PLLREG_GET(x)                                       (((x) & 0x0001c000) >> 14)
+#define PHY_ANALOG_BIAS3_PWD_IR25PLLREG_SET(x)                                       (((x) << 14) & 0x0001c000)
+#define PHY_ANALOG_BIAS3_PWD_IR25BB_MSB                                                                      19
+#define PHY_ANALOG_BIAS3_PWD_IR25BB_LSB                                                                      17
+#define PHY_ANALOG_BIAS3_PWD_IR25BB_MASK                                                             0x000e0000
+#define PHY_ANALOG_BIAS3_PWD_IR25BB_GET(x)                                           (((x) & 0x000e0000) >> 17)
+#define PHY_ANALOG_BIAS3_PWD_IR25BB_SET(x)                                           (((x) << 17) & 0x000e0000)
+#define PHY_ANALOG_BIAS3_PWD_IR50DAC_MSB                                                                     22
+#define PHY_ANALOG_BIAS3_PWD_IR50DAC_LSB                                                                     20
+#define PHY_ANALOG_BIAS3_PWD_IR50DAC_MASK                                                            0x00700000
+#define PHY_ANALOG_BIAS3_PWD_IR50DAC_GET(x)                                          (((x) & 0x00700000) >> 20)
+#define PHY_ANALOG_BIAS3_PWD_IR50DAC_SET(x)                                          (((x) << 20) & 0x00700000)
+#define PHY_ANALOG_BIAS3_PWD_IR25DAC_MSB                                                                     25
+#define PHY_ANALOG_BIAS3_PWD_IR25DAC_LSB                                                                     23
+#define PHY_ANALOG_BIAS3_PWD_IR25DAC_MASK                                                            0x03800000
+#define PHY_ANALOG_BIAS3_PWD_IR25DAC_GET(x)                                          (((x) & 0x03800000) >> 23)
+#define PHY_ANALOG_BIAS3_PWD_IR25DAC_SET(x)                                          (((x) << 23) & 0x03800000)
+#define PHY_ANALOG_BIAS3_PWD_IR25FIR_MSB                                                                     28
+#define PHY_ANALOG_BIAS3_PWD_IR25FIR_LSB                                                                     26
+#define PHY_ANALOG_BIAS3_PWD_IR25FIR_MASK                                                            0x1c000000
+#define PHY_ANALOG_BIAS3_PWD_IR25FIR_GET(x)                                          (((x) & 0x1c000000) >> 26)
+#define PHY_ANALOG_BIAS3_PWD_IR25FIR_SET(x)                                          (((x) << 26) & 0x1c000000)
+#define PHY_ANALOG_BIAS3_PWD_IR50ADC_MSB                                                                     31
+#define PHY_ANALOG_BIAS3_PWD_IR50ADC_LSB                                                                     29
+#define PHY_ANALOG_BIAS3_PWD_IR50ADC_MASK                                                            0xe0000000
+#define PHY_ANALOG_BIAS3_PWD_IR50ADC_GET(x)                                          (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_BIAS3_PWD_IR50ADC_SET(x)                                          (((x) << 29) & 0xe0000000)
+
+/* macros for BIAS4 */
+#define PHY_ANALOG_BIAS4_ADDRESS                                                                     0x000000cc
+#define PHY_ANALOG_BIAS4_OFFSET                                                                      0x000000cc
+#define PHY_ANALOG_BIAS4_SPARE4_MSB                                                                          13
+#define PHY_ANALOG_BIAS4_SPARE4_LSB                                                                           0
+#define PHY_ANALOG_BIAS4_SPARE4_MASK                                                                 0x00003fff
+#define PHY_ANALOG_BIAS4_SPARE4_GET(x)                                                (((x) & 0x00003fff) >> 0)
+#define PHY_ANALOG_BIAS4_SPARE4_SET(x)                                                (((x) << 0) & 0x00003fff)
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREC_MSB                                                                  16
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREC_LSB                                                                  14
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREC_MASK                                                         0x0001c000
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREC_GET(x)                                       (((x) & 0x0001c000) >> 14)
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREC_SET(x)                                       (((x) << 14) & 0x0001c000)
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREB_MSB                                                                  19
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREB_LSB                                                                  17
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREB_MASK                                                         0x000e0000
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREB_GET(x)                                       (((x) & 0x000e0000) >> 17)
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREB_SET(x)                                       (((x) << 17) & 0x000e0000)
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREA_MSB                                                                  22
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREA_LSB                                                                  20
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREA_MASK                                                         0x00700000
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREA_GET(x)                                       (((x) & 0x00700000) >> 20)
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREA_SET(x)                                       (((x) << 20) & 0x00700000)
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREC_MSB                                                                  25
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREC_LSB                                                                  23
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREC_MASK                                                         0x03800000
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREC_GET(x)                                       (((x) & 0x03800000) >> 23)
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREC_SET(x)                                       (((x) << 23) & 0x03800000)
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREB_MSB                                                                  28
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREB_LSB                                                                  26
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREB_MASK                                                         0x1c000000
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREB_GET(x)                                       (((x) & 0x1c000000) >> 26)
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREB_SET(x)                                       (((x) << 26) & 0x1c000000)
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREA_MSB                                                                  31
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREA_LSB                                                                  29
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREA_MASK                                                         0xe0000000
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREA_GET(x)                                       (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREA_SET(x)                                       (((x) << 29) & 0xe0000000)
+
+/* macros for RXTX1 */
+#define PHY_ANALOG_RXTX1_ADDRESS                                                                     0x00000100
+#define PHY_ANALOG_RXTX1_OFFSET                                                                      0x00000100
+#define PHY_ANALOG_RXTX1_SCFIR_GAIN_MSB                                                                       0
+#define PHY_ANALOG_RXTX1_SCFIR_GAIN_LSB                                                                       0
+#define PHY_ANALOG_RXTX1_SCFIR_GAIN_MASK                                                             0x00000001
+#define PHY_ANALOG_RXTX1_SCFIR_GAIN_GET(x)                                            (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_RXTX1_SCFIR_GAIN_SET(x)                                            (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_RXTX1_MANRXGAIN_MSB                                                                        1
+#define PHY_ANALOG_RXTX1_MANRXGAIN_LSB                                                                        1
+#define PHY_ANALOG_RXTX1_MANRXGAIN_MASK                                                              0x00000002
+#define PHY_ANALOG_RXTX1_MANRXGAIN_GET(x)                                             (((x) & 0x00000002) >> 1)
+#define PHY_ANALOG_RXTX1_MANRXGAIN_SET(x)                                             (((x) << 1) & 0x00000002)
+#define PHY_ANALOG_RXTX1_AGC_DBDAC_MSB                                                                        5
+#define PHY_ANALOG_RXTX1_AGC_DBDAC_LSB                                                                        2
+#define PHY_ANALOG_RXTX1_AGC_DBDAC_MASK                                                              0x0000003c
+#define PHY_ANALOG_RXTX1_AGC_DBDAC_GET(x)                                             (((x) & 0x0000003c) >> 2)
+#define PHY_ANALOG_RXTX1_AGC_DBDAC_SET(x)                                             (((x) << 2) & 0x0000003c)
+#define PHY_ANALOG_RXTX1_OVR_AGC_DBDAC_MSB                                                                    6
+#define PHY_ANALOG_RXTX1_OVR_AGC_DBDAC_LSB                                                                    6
+#define PHY_ANALOG_RXTX1_OVR_AGC_DBDAC_MASK                                                          0x00000040
+#define PHY_ANALOG_RXTX1_OVR_AGC_DBDAC_GET(x)                                         (((x) & 0x00000040) >> 6)
+#define PHY_ANALOG_RXTX1_OVR_AGC_DBDAC_SET(x)                                         (((x) << 6) & 0x00000040)
+#define PHY_ANALOG_RXTX1_ENABLE_PAL_MSB                                                                       7
+#define PHY_ANALOG_RXTX1_ENABLE_PAL_LSB                                                                       7
+#define PHY_ANALOG_RXTX1_ENABLE_PAL_MASK                                                             0x00000080
+#define PHY_ANALOG_RXTX1_ENABLE_PAL_GET(x)                                            (((x) & 0x00000080) >> 7)
+#define PHY_ANALOG_RXTX1_ENABLE_PAL_SET(x)                                            (((x) << 7) & 0x00000080)
+#define PHY_ANALOG_RXTX1_ENABLE_PAL_OVR_MSB                                                                   8
+#define PHY_ANALOG_RXTX1_ENABLE_PAL_OVR_LSB                                                                   8
+#define PHY_ANALOG_RXTX1_ENABLE_PAL_OVR_MASK                                                         0x00000100
+#define PHY_ANALOG_RXTX1_ENABLE_PAL_OVR_GET(x)                                        (((x) & 0x00000100) >> 8)
+#define PHY_ANALOG_RXTX1_ENABLE_PAL_OVR_SET(x)                                        (((x) << 8) & 0x00000100)
+#define PHY_ANALOG_RXTX1_TX1DB_BIQUAD_MSB                                                                    11
+#define PHY_ANALOG_RXTX1_TX1DB_BIQUAD_LSB                                                                     9
+#define PHY_ANALOG_RXTX1_TX1DB_BIQUAD_MASK                                                           0x00000e00
+#define PHY_ANALOG_RXTX1_TX1DB_BIQUAD_GET(x)                                          (((x) & 0x00000e00) >> 9)
+#define PHY_ANALOG_RXTX1_TX1DB_BIQUAD_SET(x)                                          (((x) << 9) & 0x00000e00)
+#define PHY_ANALOG_RXTX1_TX6DB_BIQUAD_MSB                                                                    13
+#define PHY_ANALOG_RXTX1_TX6DB_BIQUAD_LSB                                                                    12
+#define PHY_ANALOG_RXTX1_TX6DB_BIQUAD_MASK                                                           0x00003000
+#define PHY_ANALOG_RXTX1_TX6DB_BIQUAD_GET(x)                                         (((x) & 0x00003000) >> 12)
+#define PHY_ANALOG_RXTX1_TX6DB_BIQUAD_SET(x)                                         (((x) << 12) & 0x00003000)
+#define PHY_ANALOG_RXTX1_PADRVHALFGN2G_MSB                                                                   14
+#define PHY_ANALOG_RXTX1_PADRVHALFGN2G_LSB                                                                   14
+#define PHY_ANALOG_RXTX1_PADRVHALFGN2G_MASK                                                          0x00004000
+#define PHY_ANALOG_RXTX1_PADRVHALFGN2G_GET(x)                                        (((x) & 0x00004000) >> 14)
+#define PHY_ANALOG_RXTX1_PADRVHALFGN2G_SET(x)                                        (((x) << 14) & 0x00004000)
+#define PHY_ANALOG_RXTX1_PADRV2GN_MSB                                                                        18
+#define PHY_ANALOG_RXTX1_PADRV2GN_LSB                                                                        15
+#define PHY_ANALOG_RXTX1_PADRV2GN_MASK                                                               0x00078000
+#define PHY_ANALOG_RXTX1_PADRV2GN_GET(x)                                             (((x) & 0x00078000) >> 15)
+#define PHY_ANALOG_RXTX1_PADRV2GN_SET(x)                                             (((x) << 15) & 0x00078000)
+#define PHY_ANALOG_RXTX1_PADRV3GN5G_MSB                                                                      22
+#define PHY_ANALOG_RXTX1_PADRV3GN5G_LSB                                                                      19
+#define PHY_ANALOG_RXTX1_PADRV3GN5G_MASK                                                             0x00780000
+#define PHY_ANALOG_RXTX1_PADRV3GN5G_GET(x)                                           (((x) & 0x00780000) >> 19)
+#define PHY_ANALOG_RXTX1_PADRV3GN5G_SET(x)                                           (((x) << 19) & 0x00780000)
+#define PHY_ANALOG_RXTX1_PADRV4GN5G_MSB                                                                      26
+#define PHY_ANALOG_RXTX1_PADRV4GN5G_LSB                                                                      23
+#define PHY_ANALOG_RXTX1_PADRV4GN5G_MASK                                                             0x07800000
+#define PHY_ANALOG_RXTX1_PADRV4GN5G_GET(x)                                           (((x) & 0x07800000) >> 23)
+#define PHY_ANALOG_RXTX1_PADRV4GN5G_SET(x)                                           (((x) << 23) & 0x07800000)
+#define PHY_ANALOG_RXTX1_TXBB_GC_MSB                                                                         30
+#define PHY_ANALOG_RXTX1_TXBB_GC_LSB                                                                         27
+#define PHY_ANALOG_RXTX1_TXBB_GC_MASK                                                                0x78000000
+#define PHY_ANALOG_RXTX1_TXBB_GC_GET(x)                                              (((x) & 0x78000000) >> 27)
+#define PHY_ANALOG_RXTX1_TXBB_GC_SET(x)                                              (((x) << 27) & 0x78000000)
+#define PHY_ANALOG_RXTX1_MANTXGAIN_MSB                                                                       31
+#define PHY_ANALOG_RXTX1_MANTXGAIN_LSB                                                                       31
+#define PHY_ANALOG_RXTX1_MANTXGAIN_MASK                                                              0x80000000
+#define PHY_ANALOG_RXTX1_MANTXGAIN_GET(x)                                            (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_RXTX1_MANTXGAIN_SET(x)                                            (((x) << 31) & 0x80000000)
+
+/* macros for RXTX2 */
+#define PHY_ANALOG_RXTX2_ADDRESS                                                                     0x00000104
+#define PHY_ANALOG_RXTX2_OFFSET                                                                      0x00000104
+#define PHY_ANALOG_RXTX2_BMODE_MSB                                                                            0
+#define PHY_ANALOG_RXTX2_BMODE_LSB                                                                            0
+#define PHY_ANALOG_RXTX2_BMODE_MASK                                                                  0x00000001
+#define PHY_ANALOG_RXTX2_BMODE_GET(x)                                                 (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_RXTX2_BMODE_SET(x)                                                 (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_RXTX2_BMODE_OVR_MSB                                                                        1
+#define PHY_ANALOG_RXTX2_BMODE_OVR_LSB                                                                        1
+#define PHY_ANALOG_RXTX2_BMODE_OVR_MASK                                                              0x00000002
+#define PHY_ANALOG_RXTX2_BMODE_OVR_GET(x)                                             (((x) & 0x00000002) >> 1)
+#define PHY_ANALOG_RXTX2_BMODE_OVR_SET(x)                                             (((x) << 1) & 0x00000002)
+#define PHY_ANALOG_RXTX2_SYNTHON_MSB                                                                          2
+#define PHY_ANALOG_RXTX2_SYNTHON_LSB                                                                          2
+#define PHY_ANALOG_RXTX2_SYNTHON_MASK                                                                0x00000004
+#define PHY_ANALOG_RXTX2_SYNTHON_GET(x)                                               (((x) & 0x00000004) >> 2)
+#define PHY_ANALOG_RXTX2_SYNTHON_SET(x)                                               (((x) << 2) & 0x00000004)
+#define PHY_ANALOG_RXTX2_SYNTHON_OVR_MSB                                                                      3
+#define PHY_ANALOG_RXTX2_SYNTHON_OVR_LSB                                                                      3
+#define PHY_ANALOG_RXTX2_SYNTHON_OVR_MASK                                                            0x00000008
+#define PHY_ANALOG_RXTX2_SYNTHON_OVR_GET(x)                                           (((x) & 0x00000008) >> 3)
+#define PHY_ANALOG_RXTX2_SYNTHON_OVR_SET(x)                                           (((x) << 3) & 0x00000008)
+#define PHY_ANALOG_RXTX2_BW_ST_MSB                                                                            5
+#define PHY_ANALOG_RXTX2_BW_ST_LSB                                                                            4
+#define PHY_ANALOG_RXTX2_BW_ST_MASK                                                                  0x00000030
+#define PHY_ANALOG_RXTX2_BW_ST_GET(x)                                                 (((x) & 0x00000030) >> 4)
+#define PHY_ANALOG_RXTX2_BW_ST_SET(x)                                                 (((x) << 4) & 0x00000030)
+#define PHY_ANALOG_RXTX2_BW_ST_OVR_MSB                                                                        6
+#define PHY_ANALOG_RXTX2_BW_ST_OVR_LSB                                                                        6
+#define PHY_ANALOG_RXTX2_BW_ST_OVR_MASK                                                              0x00000040
+#define PHY_ANALOG_RXTX2_BW_ST_OVR_GET(x)                                             (((x) & 0x00000040) >> 6)
+#define PHY_ANALOG_RXTX2_BW_ST_OVR_SET(x)                                             (((x) << 6) & 0x00000040)
+#define PHY_ANALOG_RXTX2_TXON_MSB                                                                             7
+#define PHY_ANALOG_RXTX2_TXON_LSB                                                                             7
+#define PHY_ANALOG_RXTX2_TXON_MASK                                                                   0x00000080
+#define PHY_ANALOG_RXTX2_TXON_GET(x)                                                  (((x) & 0x00000080) >> 7)
+#define PHY_ANALOG_RXTX2_TXON_SET(x)                                                  (((x) << 7) & 0x00000080)
+#define PHY_ANALOG_RXTX2_TXON_OVR_MSB                                                                         8
+#define PHY_ANALOG_RXTX2_TXON_OVR_LSB                                                                         8
+#define PHY_ANALOG_RXTX2_TXON_OVR_MASK                                                               0x00000100
+#define PHY_ANALOG_RXTX2_TXON_OVR_GET(x)                                              (((x) & 0x00000100) >> 8)
+#define PHY_ANALOG_RXTX2_TXON_OVR_SET(x)                                              (((x) << 8) & 0x00000100)
+#define PHY_ANALOG_RXTX2_PAON_MSB                                                                             9
+#define PHY_ANALOG_RXTX2_PAON_LSB                                                                             9
+#define PHY_ANALOG_RXTX2_PAON_MASK                                                                   0x00000200
+#define PHY_ANALOG_RXTX2_PAON_GET(x)                                                  (((x) & 0x00000200) >> 9)
+#define PHY_ANALOG_RXTX2_PAON_SET(x)                                                  (((x) << 9) & 0x00000200)
+#define PHY_ANALOG_RXTX2_PAON_OVR_MSB                                                                        10
+#define PHY_ANALOG_RXTX2_PAON_OVR_LSB                                                                        10
+#define PHY_ANALOG_RXTX2_PAON_OVR_MASK                                                               0x00000400
+#define PHY_ANALOG_RXTX2_PAON_OVR_GET(x)                                             (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_RXTX2_PAON_OVR_SET(x)                                             (((x) << 10) & 0x00000400)
+#define PHY_ANALOG_RXTX2_RXON_MSB                                                                            11
+#define PHY_ANALOG_RXTX2_RXON_LSB                                                                            11
+#define PHY_ANALOG_RXTX2_RXON_MASK                                                                   0x00000800
+#define PHY_ANALOG_RXTX2_RXON_GET(x)                                                 (((x) & 0x00000800) >> 11)
+#define PHY_ANALOG_RXTX2_RXON_SET(x)                                                 (((x) << 11) & 0x00000800)
+#define PHY_ANALOG_RXTX2_RXON_OVR_MSB                                                                        12
+#define PHY_ANALOG_RXTX2_RXON_OVR_LSB                                                                        12
+#define PHY_ANALOG_RXTX2_RXON_OVR_MASK                                                               0x00001000
+#define PHY_ANALOG_RXTX2_RXON_OVR_GET(x)                                             (((x) & 0x00001000) >> 12)
+#define PHY_ANALOG_RXTX2_RXON_OVR_SET(x)                                             (((x) << 12) & 0x00001000)
+#define PHY_ANALOG_RXTX2_AGCON_MSB                                                                           13
+#define PHY_ANALOG_RXTX2_AGCON_LSB                                                                           13
+#define PHY_ANALOG_RXTX2_AGCON_MASK                                                                  0x00002000
+#define PHY_ANALOG_RXTX2_AGCON_GET(x)                                                (((x) & 0x00002000) >> 13)
+#define PHY_ANALOG_RXTX2_AGCON_SET(x)                                                (((x) << 13) & 0x00002000)
+#define PHY_ANALOG_RXTX2_AGCON_OVR_MSB                                                                       14
+#define PHY_ANALOG_RXTX2_AGCON_OVR_LSB                                                                       14
+#define PHY_ANALOG_RXTX2_AGCON_OVR_MASK                                                              0x00004000
+#define PHY_ANALOG_RXTX2_AGCON_OVR_GET(x)                                            (((x) & 0x00004000) >> 14)
+#define PHY_ANALOG_RXTX2_AGCON_OVR_SET(x)                                            (((x) << 14) & 0x00004000)
+#define PHY_ANALOG_RXTX2_TXMOD_MSB                                                                           17
+#define PHY_ANALOG_RXTX2_TXMOD_LSB                                                                           15
+#define PHY_ANALOG_RXTX2_TXMOD_MASK                                                                  0x00038000
+#define PHY_ANALOG_RXTX2_TXMOD_GET(x)                                                (((x) & 0x00038000) >> 15)
+#define PHY_ANALOG_RXTX2_TXMOD_SET(x)                                                (((x) << 15) & 0x00038000)
+#define PHY_ANALOG_RXTX2_TXMOD_OVR_MSB                                                                       18
+#define PHY_ANALOG_RXTX2_TXMOD_OVR_LSB                                                                       18
+#define PHY_ANALOG_RXTX2_TXMOD_OVR_MASK                                                              0x00040000
+#define PHY_ANALOG_RXTX2_TXMOD_OVR_GET(x)                                            (((x) & 0x00040000) >> 18)
+#define PHY_ANALOG_RXTX2_TXMOD_OVR_SET(x)                                            (((x) << 18) & 0x00040000)
+#define PHY_ANALOG_RXTX2_RX1DB_BIQUAD_MSB                                                                    21
+#define PHY_ANALOG_RXTX2_RX1DB_BIQUAD_LSB                                                                    19
+#define PHY_ANALOG_RXTX2_RX1DB_BIQUAD_MASK                                                           0x00380000
+#define PHY_ANALOG_RXTX2_RX1DB_BIQUAD_GET(x)                                         (((x) & 0x00380000) >> 19)
+#define PHY_ANALOG_RXTX2_RX1DB_BIQUAD_SET(x)                                         (((x) << 19) & 0x00380000)
+#define PHY_ANALOG_RXTX2_RX6DB_BIQUAD_MSB                                                                    23
+#define PHY_ANALOG_RXTX2_RX6DB_BIQUAD_LSB                                                                    22
+#define PHY_ANALOG_RXTX2_RX6DB_BIQUAD_MASK                                                           0x00c00000
+#define PHY_ANALOG_RXTX2_RX6DB_BIQUAD_GET(x)                                         (((x) & 0x00c00000) >> 22)
+#define PHY_ANALOG_RXTX2_RX6DB_BIQUAD_SET(x)                                         (((x) << 22) & 0x00c00000)
+#define PHY_ANALOG_RXTX2_MXRGAIN_MSB                                                                         25
+#define PHY_ANALOG_RXTX2_MXRGAIN_LSB                                                                         24
+#define PHY_ANALOG_RXTX2_MXRGAIN_MASK                                                                0x03000000
+#define PHY_ANALOG_RXTX2_MXRGAIN_GET(x)                                              (((x) & 0x03000000) >> 24)
+#define PHY_ANALOG_RXTX2_MXRGAIN_SET(x)                                              (((x) << 24) & 0x03000000)
+#define PHY_ANALOG_RXTX2_VGAGAIN_MSB                                                                         28
+#define PHY_ANALOG_RXTX2_VGAGAIN_LSB                                                                         26
+#define PHY_ANALOG_RXTX2_VGAGAIN_MASK                                                                0x1c000000
+#define PHY_ANALOG_RXTX2_VGAGAIN_GET(x)                                              (((x) & 0x1c000000) >> 26)
+#define PHY_ANALOG_RXTX2_VGAGAIN_SET(x)                                              (((x) << 26) & 0x1c000000)
+#define PHY_ANALOG_RXTX2_LNAGAIN_MSB                                                                         31
+#define PHY_ANALOG_RXTX2_LNAGAIN_LSB                                                                         29
+#define PHY_ANALOG_RXTX2_LNAGAIN_MASK                                                                0xe0000000
+#define PHY_ANALOG_RXTX2_LNAGAIN_GET(x)                                              (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_RXTX2_LNAGAIN_SET(x)                                              (((x) << 29) & 0xe0000000)
+
+/* macros for RXTX3 */
+#define PHY_ANALOG_RXTX3_ADDRESS                                                                     0x00000108
+#define PHY_ANALOG_RXTX3_OFFSET                                                                      0x00000108
+#define PHY_ANALOG_RXTX3_SPARE3_MSB                                                                           2
+#define PHY_ANALOG_RXTX3_SPARE3_LSB                                                                           0
+#define PHY_ANALOG_RXTX3_SPARE3_MASK                                                                 0x00000007
+#define PHY_ANALOG_RXTX3_SPARE3_GET(x)                                                (((x) & 0x00000007) >> 0)
+#define PHY_ANALOG_RXTX3_SPARE3_SET(x)                                                (((x) << 0) & 0x00000007)
+#define PHY_ANALOG_RXTX3_DACFULLSCALE_MSB                                                                     3
+#define PHY_ANALOG_RXTX3_DACFULLSCALE_LSB                                                                     3
+#define PHY_ANALOG_RXTX3_DACFULLSCALE_MASK                                                           0x00000008
+#define PHY_ANALOG_RXTX3_DACFULLSCALE_GET(x)                                          (((x) & 0x00000008) >> 3)
+#define PHY_ANALOG_RXTX3_DACFULLSCALE_SET(x)                                          (((x) << 3) & 0x00000008)
+#define PHY_ANALOG_RXTX3_DACRSTB_MSB                                                                          4
+#define PHY_ANALOG_RXTX3_DACRSTB_LSB                                                                          4
+#define PHY_ANALOG_RXTX3_DACRSTB_MASK                                                                0x00000010
+#define PHY_ANALOG_RXTX3_DACRSTB_GET(x)                                               (((x) & 0x00000010) >> 4)
+#define PHY_ANALOG_RXTX3_DACRSTB_SET(x)                                               (((x) << 4) & 0x00000010)
+#define PHY_ANALOG_RXTX3_ADDACLOOPBACK_MSB                                                                    5
+#define PHY_ANALOG_RXTX3_ADDACLOOPBACK_LSB                                                                    5
+#define PHY_ANALOG_RXTX3_ADDACLOOPBACK_MASK                                                          0x00000020
+#define PHY_ANALOG_RXTX3_ADDACLOOPBACK_GET(x)                                         (((x) & 0x00000020) >> 5)
+#define PHY_ANALOG_RXTX3_ADDACLOOPBACK_SET(x)                                         (((x) << 5) & 0x00000020)
+#define PHY_ANALOG_RXTX3_ADCSHORT_MSB                                                                         6
+#define PHY_ANALOG_RXTX3_ADCSHORT_LSB                                                                         6
+#define PHY_ANALOG_RXTX3_ADCSHORT_MASK                                                               0x00000040
+#define PHY_ANALOG_RXTX3_ADCSHORT_GET(x)                                              (((x) & 0x00000040) >> 6)
+#define PHY_ANALOG_RXTX3_ADCSHORT_SET(x)                                              (((x) << 6) & 0x00000040)
+#define PHY_ANALOG_RXTX3_DACPWD_MSB                                                                           7
+#define PHY_ANALOG_RXTX3_DACPWD_LSB                                                                           7
+#define PHY_ANALOG_RXTX3_DACPWD_MASK                                                                 0x00000080
+#define PHY_ANALOG_RXTX3_DACPWD_GET(x)                                                (((x) & 0x00000080) >> 7)
+#define PHY_ANALOG_RXTX3_DACPWD_SET(x)                                                (((x) << 7) & 0x00000080)
+#define PHY_ANALOG_RXTX3_DACPWD_OVR_MSB                                                                       8
+#define PHY_ANALOG_RXTX3_DACPWD_OVR_LSB                                                                       8
+#define PHY_ANALOG_RXTX3_DACPWD_OVR_MASK                                                             0x00000100
+#define PHY_ANALOG_RXTX3_DACPWD_OVR_GET(x)                                            (((x) & 0x00000100) >> 8)
+#define PHY_ANALOG_RXTX3_DACPWD_OVR_SET(x)                                            (((x) << 8) & 0x00000100)
+#define PHY_ANALOG_RXTX3_ADCPWD_MSB                                                                           9
+#define PHY_ANALOG_RXTX3_ADCPWD_LSB                                                                           9
+#define PHY_ANALOG_RXTX3_ADCPWD_MASK                                                                 0x00000200
+#define PHY_ANALOG_RXTX3_ADCPWD_GET(x)                                                (((x) & 0x00000200) >> 9)
+#define PHY_ANALOG_RXTX3_ADCPWD_SET(x)                                                (((x) << 9) & 0x00000200)
+#define PHY_ANALOG_RXTX3_ADCPWD_OVR_MSB                                                                      10
+#define PHY_ANALOG_RXTX3_ADCPWD_OVR_LSB                                                                      10
+#define PHY_ANALOG_RXTX3_ADCPWD_OVR_MASK                                                             0x00000400
+#define PHY_ANALOG_RXTX3_ADCPWD_OVR_GET(x)                                           (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_RXTX3_ADCPWD_OVR_SET(x)                                           (((x) << 10) & 0x00000400)
+#define PHY_ANALOG_RXTX3_AGC_CALDAC_MSB                                                                      16
+#define PHY_ANALOG_RXTX3_AGC_CALDAC_LSB                                                                      11
+#define PHY_ANALOG_RXTX3_AGC_CALDAC_MASK                                                             0x0001f800
+#define PHY_ANALOG_RXTX3_AGC_CALDAC_GET(x)                                           (((x) & 0x0001f800) >> 11)
+#define PHY_ANALOG_RXTX3_AGC_CALDAC_SET(x)                                           (((x) << 11) & 0x0001f800)
+#define PHY_ANALOG_RXTX3_AGC_CAL_MSB                                                                         17
+#define PHY_ANALOG_RXTX3_AGC_CAL_LSB                                                                         17
+#define PHY_ANALOG_RXTX3_AGC_CAL_MASK                                                                0x00020000
+#define PHY_ANALOG_RXTX3_AGC_CAL_GET(x)                                              (((x) & 0x00020000) >> 17)
+#define PHY_ANALOG_RXTX3_AGC_CAL_SET(x)                                              (((x) << 17) & 0x00020000)
+#define PHY_ANALOG_RXTX3_AGC_CAL_OVR_MSB                                                                     18
+#define PHY_ANALOG_RXTX3_AGC_CAL_OVR_LSB                                                                     18
+#define PHY_ANALOG_RXTX3_AGC_CAL_OVR_MASK                                                            0x00040000
+#define PHY_ANALOG_RXTX3_AGC_CAL_OVR_GET(x)                                          (((x) & 0x00040000) >> 18)
+#define PHY_ANALOG_RXTX3_AGC_CAL_OVR_SET(x)                                          (((x) << 18) & 0x00040000)
+#define PHY_ANALOG_RXTX3_LOFORCEDON_MSB                                                                      19
+#define PHY_ANALOG_RXTX3_LOFORCEDON_LSB                                                                      19
+#define PHY_ANALOG_RXTX3_LOFORCEDON_MASK                                                             0x00080000
+#define PHY_ANALOG_RXTX3_LOFORCEDON_GET(x)                                           (((x) & 0x00080000) >> 19)
+#define PHY_ANALOG_RXTX3_LOFORCEDON_SET(x)                                           (((x) << 19) & 0x00080000)
+#define PHY_ANALOG_RXTX3_CALRESIDUE_MSB                                                                      20
+#define PHY_ANALOG_RXTX3_CALRESIDUE_LSB                                                                      20
+#define PHY_ANALOG_RXTX3_CALRESIDUE_MASK                                                             0x00100000
+#define PHY_ANALOG_RXTX3_CALRESIDUE_GET(x)                                           (((x) & 0x00100000) >> 20)
+#define PHY_ANALOG_RXTX3_CALRESIDUE_SET(x)                                           (((x) << 20) & 0x00100000)
+#define PHY_ANALOG_RXTX3_CALRESIDUE_OVR_MSB                                                                  21
+#define PHY_ANALOG_RXTX3_CALRESIDUE_OVR_LSB                                                                  21
+#define PHY_ANALOG_RXTX3_CALRESIDUE_OVR_MASK                                                         0x00200000
+#define PHY_ANALOG_RXTX3_CALRESIDUE_OVR_GET(x)                                       (((x) & 0x00200000) >> 21)
+#define PHY_ANALOG_RXTX3_CALRESIDUE_OVR_SET(x)                                       (((x) << 21) & 0x00200000)
+#define PHY_ANALOG_RXTX3_CALFC_MSB                                                                           22
+#define PHY_ANALOG_RXTX3_CALFC_LSB                                                                           22
+#define PHY_ANALOG_RXTX3_CALFC_MASK                                                                  0x00400000
+#define PHY_ANALOG_RXTX3_CALFC_GET(x)                                                (((x) & 0x00400000) >> 22)
+#define PHY_ANALOG_RXTX3_CALFC_SET(x)                                                (((x) << 22) & 0x00400000)
+#define PHY_ANALOG_RXTX3_CALFC_OVR_MSB                                                                       23
+#define PHY_ANALOG_RXTX3_CALFC_OVR_LSB                                                                       23
+#define PHY_ANALOG_RXTX3_CALFC_OVR_MASK                                                              0x00800000
+#define PHY_ANALOG_RXTX3_CALFC_OVR_GET(x)                                            (((x) & 0x00800000) >> 23)
+#define PHY_ANALOG_RXTX3_CALFC_OVR_SET(x)                                            (((x) << 23) & 0x00800000)
+#define PHY_ANALOG_RXTX3_CALTX_MSB                                                                           24
+#define PHY_ANALOG_RXTX3_CALTX_LSB                                                                           24
+#define PHY_ANALOG_RXTX3_CALTX_MASK                                                                  0x01000000
+#define PHY_ANALOG_RXTX3_CALTX_GET(x)                                                (((x) & 0x01000000) >> 24)
+#define PHY_ANALOG_RXTX3_CALTX_SET(x)                                                (((x) << 24) & 0x01000000)
+#define PHY_ANALOG_RXTX3_CALTX_OVR_MSB                                                                       25
+#define PHY_ANALOG_RXTX3_CALTX_OVR_LSB                                                                       25
+#define PHY_ANALOG_RXTX3_CALTX_OVR_MASK                                                              0x02000000
+#define PHY_ANALOG_RXTX3_CALTX_OVR_GET(x)                                            (((x) & 0x02000000) >> 25)
+#define PHY_ANALOG_RXTX3_CALTX_OVR_SET(x)                                            (((x) << 25) & 0x02000000)
+#define PHY_ANALOG_RXTX3_CALTXSHIFT_MSB                                                                      26
+#define PHY_ANALOG_RXTX3_CALTXSHIFT_LSB                                                                      26
+#define PHY_ANALOG_RXTX3_CALTXSHIFT_MASK                                                             0x04000000
+#define PHY_ANALOG_RXTX3_CALTXSHIFT_GET(x)                                           (((x) & 0x04000000) >> 26)
+#define PHY_ANALOG_RXTX3_CALTXSHIFT_SET(x)                                           (((x) << 26) & 0x04000000)
+#define PHY_ANALOG_RXTX3_CALTXSHIFT_OVR_MSB                                                                  27
+#define PHY_ANALOG_RXTX3_CALTXSHIFT_OVR_LSB                                                                  27
+#define PHY_ANALOG_RXTX3_CALTXSHIFT_OVR_MASK                                                         0x08000000
+#define PHY_ANALOG_RXTX3_CALTXSHIFT_OVR_GET(x)                                       (((x) & 0x08000000) >> 27)
+#define PHY_ANALOG_RXTX3_CALTXSHIFT_OVR_SET(x)                                       (((x) << 27) & 0x08000000)
+#define PHY_ANALOG_RXTX3_CALPA_MSB                                                                           28
+#define PHY_ANALOG_RXTX3_CALPA_LSB                                                                           28
+#define PHY_ANALOG_RXTX3_CALPA_MASK                                                                  0x10000000
+#define PHY_ANALOG_RXTX3_CALPA_GET(x)                                                (((x) & 0x10000000) >> 28)
+#define PHY_ANALOG_RXTX3_CALPA_SET(x)                                                (((x) << 28) & 0x10000000)
+#define PHY_ANALOG_RXTX3_CALPA_OVR_MSB                                                                       29
+#define PHY_ANALOG_RXTX3_CALPA_OVR_LSB                                                                       29
+#define PHY_ANALOG_RXTX3_CALPA_OVR_MASK                                                              0x20000000
+#define PHY_ANALOG_RXTX3_CALPA_OVR_GET(x)                                            (((x) & 0x20000000) >> 29)
+#define PHY_ANALOG_RXTX3_CALPA_OVR_SET(x)                                            (((x) << 29) & 0x20000000)
+#define PHY_ANALOG_RXTX3_SPURON_MSB                                                                          30
+#define PHY_ANALOG_RXTX3_SPURON_LSB                                                                          30
+#define PHY_ANALOG_RXTX3_SPURON_MASK                                                                 0x40000000
+#define PHY_ANALOG_RXTX3_SPURON_GET(x)                                               (((x) & 0x40000000) >> 30)
+#define PHY_ANALOG_RXTX3_SPURON_SET(x)                                               (((x) << 30) & 0x40000000)
+#define PHY_ANALOG_RXTX3_SPURON_OVR_MSB                                                                      31
+#define PHY_ANALOG_RXTX3_SPURON_OVR_LSB                                                                      31
+#define PHY_ANALOG_RXTX3_SPURON_OVR_MASK                                                             0x80000000
+#define PHY_ANALOG_RXTX3_SPURON_OVR_GET(x)                                           (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_RXTX3_SPURON_OVR_SET(x)                                           (((x) << 31) & 0x80000000)
+
+/* macros for BB1 */
+#define PHY_ANALOG_BB1_ADDRESS                                                                       0x00000140
+#define PHY_ANALOG_BB1_OFFSET                                                                        0x00000140
+#define PHY_ANALOG_BB1_I2V_CURR2X_MSB                                                                         0
+#define PHY_ANALOG_BB1_I2V_CURR2X_LSB                                                                         0
+#define PHY_ANALOG_BB1_I2V_CURR2X_MASK                                                               0x00000001
+#define PHY_ANALOG_BB1_I2V_CURR2X_GET(x)                                              (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_BB1_I2V_CURR2X_SET(x)                                              (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_BB1_ENABLE_LOQ_MSB                                                                         1
+#define PHY_ANALOG_BB1_ENABLE_LOQ_LSB                                                                         1
+#define PHY_ANALOG_BB1_ENABLE_LOQ_MASK                                                               0x00000002
+#define PHY_ANALOG_BB1_ENABLE_LOQ_GET(x)                                              (((x) & 0x00000002) >> 1)
+#define PHY_ANALOG_BB1_ENABLE_LOQ_SET(x)                                              (((x) << 1) & 0x00000002)
+#define PHY_ANALOG_BB1_FORCE_LOQ_MSB                                                                          2
+#define PHY_ANALOG_BB1_FORCE_LOQ_LSB                                                                          2
+#define PHY_ANALOG_BB1_FORCE_LOQ_MASK                                                                0x00000004
+#define PHY_ANALOG_BB1_FORCE_LOQ_GET(x)                                               (((x) & 0x00000004) >> 2)
+#define PHY_ANALOG_BB1_FORCE_LOQ_SET(x)                                               (((x) << 2) & 0x00000004)
+#define PHY_ANALOG_BB1_ENABLE_NOTCH_MSB                                                                       3
+#define PHY_ANALOG_BB1_ENABLE_NOTCH_LSB                                                                       3
+#define PHY_ANALOG_BB1_ENABLE_NOTCH_MASK                                                             0x00000008
+#define PHY_ANALOG_BB1_ENABLE_NOTCH_GET(x)                                            (((x) & 0x00000008) >> 3)
+#define PHY_ANALOG_BB1_ENABLE_NOTCH_SET(x)                                            (((x) << 3) & 0x00000008)
+#define PHY_ANALOG_BB1_FORCE_NOTCH_MSB                                                                        4
+#define PHY_ANALOG_BB1_FORCE_NOTCH_LSB                                                                        4
+#define PHY_ANALOG_BB1_FORCE_NOTCH_MASK                                                              0x00000010
+#define PHY_ANALOG_BB1_FORCE_NOTCH_GET(x)                                             (((x) & 0x00000010) >> 4)
+#define PHY_ANALOG_BB1_FORCE_NOTCH_SET(x)                                             (((x) << 4) & 0x00000010)
+#define PHY_ANALOG_BB1_ENABLE_BIQUAD_MSB                                                                      5
+#define PHY_ANALOG_BB1_ENABLE_BIQUAD_LSB                                                                      5
+#define PHY_ANALOG_BB1_ENABLE_BIQUAD_MASK                                                            0x00000020
+#define PHY_ANALOG_BB1_ENABLE_BIQUAD_GET(x)                                           (((x) & 0x00000020) >> 5)
+#define PHY_ANALOG_BB1_ENABLE_BIQUAD_SET(x)                                           (((x) << 5) & 0x00000020)
+#define PHY_ANALOG_BB1_FORCE_BIQUAD_MSB                                                                       6
+#define PHY_ANALOG_BB1_FORCE_BIQUAD_LSB                                                                       6
+#define PHY_ANALOG_BB1_FORCE_BIQUAD_MASK                                                             0x00000040
+#define PHY_ANALOG_BB1_FORCE_BIQUAD_GET(x)                                            (((x) & 0x00000040) >> 6)
+#define PHY_ANALOG_BB1_FORCE_BIQUAD_SET(x)                                            (((x) << 6) & 0x00000040)
+#define PHY_ANALOG_BB1_ENABLE_OSDAC_MSB                                                                       7
+#define PHY_ANALOG_BB1_ENABLE_OSDAC_LSB                                                                       7
+#define PHY_ANALOG_BB1_ENABLE_OSDAC_MASK                                                             0x00000080
+#define PHY_ANALOG_BB1_ENABLE_OSDAC_GET(x)                                            (((x) & 0x00000080) >> 7)
+#define PHY_ANALOG_BB1_ENABLE_OSDAC_SET(x)                                            (((x) << 7) & 0x00000080)
+#define PHY_ANALOG_BB1_FORCE_OSDAC_MSB                                                                        8
+#define PHY_ANALOG_BB1_FORCE_OSDAC_LSB                                                                        8
+#define PHY_ANALOG_BB1_FORCE_OSDAC_MASK                                                              0x00000100
+#define PHY_ANALOG_BB1_FORCE_OSDAC_GET(x)                                             (((x) & 0x00000100) >> 8)
+#define PHY_ANALOG_BB1_FORCE_OSDAC_SET(x)                                             (((x) << 8) & 0x00000100)
+#define PHY_ANALOG_BB1_ENABLE_V2I_MSB                                                                         9
+#define PHY_ANALOG_BB1_ENABLE_V2I_LSB                                                                         9
+#define PHY_ANALOG_BB1_ENABLE_V2I_MASK                                                               0x00000200
+#define PHY_ANALOG_BB1_ENABLE_V2I_GET(x)                                              (((x) & 0x00000200) >> 9)
+#define PHY_ANALOG_BB1_ENABLE_V2I_SET(x)                                              (((x) << 9) & 0x00000200)
+#define PHY_ANALOG_BB1_FORCE_V2I_MSB                                                                         10
+#define PHY_ANALOG_BB1_FORCE_V2I_LSB                                                                         10
+#define PHY_ANALOG_BB1_FORCE_V2I_MASK                                                                0x00000400
+#define PHY_ANALOG_BB1_FORCE_V2I_GET(x)                                              (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_BB1_FORCE_V2I_SET(x)                                              (((x) << 10) & 0x00000400)
+#define PHY_ANALOG_BB1_ENABLE_I2V_MSB                                                                        11
+#define PHY_ANALOG_BB1_ENABLE_I2V_LSB                                                                        11
+#define PHY_ANALOG_BB1_ENABLE_I2V_MASK                                                               0x00000800
+#define PHY_ANALOG_BB1_ENABLE_I2V_GET(x)                                             (((x) & 0x00000800) >> 11)
+#define PHY_ANALOG_BB1_ENABLE_I2V_SET(x)                                             (((x) << 11) & 0x00000800)
+#define PHY_ANALOG_BB1_FORCE_I2V_MSB                                                                         12
+#define PHY_ANALOG_BB1_FORCE_I2V_LSB                                                                         12
+#define PHY_ANALOG_BB1_FORCE_I2V_MASK                                                                0x00001000
+#define PHY_ANALOG_BB1_FORCE_I2V_GET(x)                                              (((x) & 0x00001000) >> 12)
+#define PHY_ANALOG_BB1_FORCE_I2V_SET(x)                                              (((x) << 12) & 0x00001000)
+#define PHY_ANALOG_BB1_CMSEL_MSB                                                                             15
+#define PHY_ANALOG_BB1_CMSEL_LSB                                                                             13
+#define PHY_ANALOG_BB1_CMSEL_MASK                                                                    0x0000e000
+#define PHY_ANALOG_BB1_CMSEL_GET(x)                                                  (((x) & 0x0000e000) >> 13)
+#define PHY_ANALOG_BB1_CMSEL_SET(x)                                                  (((x) << 13) & 0x0000e000)
+#define PHY_ANALOG_BB1_ATBSEL_MSB                                                                            17
+#define PHY_ANALOG_BB1_ATBSEL_LSB                                                                            16
+#define PHY_ANALOG_BB1_ATBSEL_MASK                                                                   0x00030000
+#define PHY_ANALOG_BB1_ATBSEL_GET(x)                                                 (((x) & 0x00030000) >> 16)
+#define PHY_ANALOG_BB1_ATBSEL_SET(x)                                                 (((x) << 16) & 0x00030000)
+#define PHY_ANALOG_BB1_PD_OSDAC_CALTX_CALPA_MSB                                                              18
+#define PHY_ANALOG_BB1_PD_OSDAC_CALTX_CALPA_LSB                                                              18
+#define PHY_ANALOG_BB1_PD_OSDAC_CALTX_CALPA_MASK                                                     0x00040000
+#define PHY_ANALOG_BB1_PD_OSDAC_CALTX_CALPA_GET(x)                                   (((x) & 0x00040000) >> 18)
+#define PHY_ANALOG_BB1_PD_OSDAC_CALTX_CALPA_SET(x)                                   (((x) << 18) & 0x00040000)
+#define PHY_ANALOG_BB1_OFSTCORRI2VQ_MSB                                                                      23
+#define PHY_ANALOG_BB1_OFSTCORRI2VQ_LSB                                                                      19
+#define PHY_ANALOG_BB1_OFSTCORRI2VQ_MASK                                                             0x00f80000
+#define PHY_ANALOG_BB1_OFSTCORRI2VQ_GET(x)                                           (((x) & 0x00f80000) >> 19)
+#define PHY_ANALOG_BB1_OFSTCORRI2VQ_SET(x)                                           (((x) << 19) & 0x00f80000)
+#define PHY_ANALOG_BB1_OFSTCORRI2VI_MSB                                                                      28
+#define PHY_ANALOG_BB1_OFSTCORRI2VI_LSB                                                                      24
+#define PHY_ANALOG_BB1_OFSTCORRI2VI_MASK                                                             0x1f000000
+#define PHY_ANALOG_BB1_OFSTCORRI2VI_GET(x)                                           (((x) & 0x1f000000) >> 24)
+#define PHY_ANALOG_BB1_OFSTCORRI2VI_SET(x)                                           (((x) << 24) & 0x1f000000)
+#define PHY_ANALOG_BB1_LOCALOFFSET_MSB                                                                       29
+#define PHY_ANALOG_BB1_LOCALOFFSET_LSB                                                                       29
+#define PHY_ANALOG_BB1_LOCALOFFSET_MASK                                                              0x20000000
+#define PHY_ANALOG_BB1_LOCALOFFSET_GET(x)                                            (((x) & 0x20000000) >> 29)
+#define PHY_ANALOG_BB1_LOCALOFFSET_SET(x)                                            (((x) << 29) & 0x20000000)
+#define PHY_ANALOG_BB1_RANGE_OSDAC_MSB                                                                       31
+#define PHY_ANALOG_BB1_RANGE_OSDAC_LSB                                                                       30
+#define PHY_ANALOG_BB1_RANGE_OSDAC_MASK                                                              0xc0000000
+#define PHY_ANALOG_BB1_RANGE_OSDAC_GET(x)                                            (((x) & 0xc0000000) >> 30)
+#define PHY_ANALOG_BB1_RANGE_OSDAC_SET(x)                                            (((x) << 30) & 0xc0000000)
+
+/* macros for BB2 */
+#define PHY_ANALOG_BB2_ADDRESS                                                                       0x00000144
+#define PHY_ANALOG_BB2_OFFSET                                                                        0x00000144
+#define PHY_ANALOG_BB2_SPARE_MSB                                                                              6
+#define PHY_ANALOG_BB2_SPARE_LSB                                                                              0
+#define PHY_ANALOG_BB2_SPARE_MASK                                                                    0x0000007f
+#define PHY_ANALOG_BB2_SPARE_GET(x)                                                   (((x) & 0x0000007f) >> 0)
+#define PHY_ANALOG_BB2_SPARE_SET(x)                                                   (((x) << 0) & 0x0000007f)
+#define PHY_ANALOG_BB2_SEL_TEST_MSB                                                                           9
+#define PHY_ANALOG_BB2_SEL_TEST_LSB                                                                           7
+#define PHY_ANALOG_BB2_SEL_TEST_MASK                                                                 0x00000380
+#define PHY_ANALOG_BB2_SEL_TEST_GET(x)                                                (((x) & 0x00000380) >> 7)
+#define PHY_ANALOG_BB2_SEL_TEST_SET(x)                                                (((x) << 7) & 0x00000380)
+#define PHY_ANALOG_BB2_SCFIR_CAP_MSB                                                                         14
+#define PHY_ANALOG_BB2_SCFIR_CAP_LSB                                                                         10
+#define PHY_ANALOG_BB2_SCFIR_CAP_MASK                                                                0x00007c00
+#define PHY_ANALOG_BB2_SCFIR_CAP_GET(x)                                              (((x) & 0x00007c00) >> 10)
+#define PHY_ANALOG_BB2_SCFIR_CAP_SET(x)                                              (((x) << 10) & 0x00007c00)
+#define PHY_ANALOG_BB2_OVERRIDE_SCFIR_CAP_MSB                                                                15
+#define PHY_ANALOG_BB2_OVERRIDE_SCFIR_CAP_LSB                                                                15
+#define PHY_ANALOG_BB2_OVERRIDE_SCFIR_CAP_MASK                                                       0x00008000
+#define PHY_ANALOG_BB2_OVERRIDE_SCFIR_CAP_GET(x)                                     (((x) & 0x00008000) >> 15)
+#define PHY_ANALOG_BB2_OVERRIDE_SCFIR_CAP_SET(x)                                     (((x) << 15) & 0x00008000)
+#define PHY_ANALOG_BB2_FNOTCH_MSB                                                                            19
+#define PHY_ANALOG_BB2_FNOTCH_LSB                                                                            16
+#define PHY_ANALOG_BB2_FNOTCH_MASK                                                                   0x000f0000
+#define PHY_ANALOG_BB2_FNOTCH_GET(x)                                                 (((x) & 0x000f0000) >> 16)
+#define PHY_ANALOG_BB2_FNOTCH_SET(x)                                                 (((x) << 16) & 0x000f0000)
+#define PHY_ANALOG_BB2_OVERRIDE_FNOTCH_MSB                                                                   20
+#define PHY_ANALOG_BB2_OVERRIDE_FNOTCH_LSB                                                                   20
+#define PHY_ANALOG_BB2_OVERRIDE_FNOTCH_MASK                                                          0x00100000
+#define PHY_ANALOG_BB2_OVERRIDE_FNOTCH_GET(x)                                        (((x) & 0x00100000) >> 20)
+#define PHY_ANALOG_BB2_OVERRIDE_FNOTCH_SET(x)                                        (((x) << 20) & 0x00100000)
+#define PHY_ANALOG_BB2_FILTERFC_MSB                                                                          25
+#define PHY_ANALOG_BB2_FILTERFC_LSB                                                                          21
+#define PHY_ANALOG_BB2_FILTERFC_MASK                                                                 0x03e00000
+#define PHY_ANALOG_BB2_FILTERFC_GET(x)                                               (((x) & 0x03e00000) >> 21)
+#define PHY_ANALOG_BB2_FILTERFC_SET(x)                                               (((x) << 21) & 0x03e00000)
+#define PHY_ANALOG_BB2_OVERRIDE_FILTERFC_MSB                                                                 26
+#define PHY_ANALOG_BB2_OVERRIDE_FILTERFC_LSB                                                                 26
+#define PHY_ANALOG_BB2_OVERRIDE_FILTERFC_MASK                                                        0x04000000
+#define PHY_ANALOG_BB2_OVERRIDE_FILTERFC_GET(x)                                      (((x) & 0x04000000) >> 26)
+#define PHY_ANALOG_BB2_OVERRIDE_FILTERFC_SET(x)                                      (((x) << 26) & 0x04000000)
+#define PHY_ANALOG_BB2_I2V2RXOUT_EN_MSB                                                                      27
+#define PHY_ANALOG_BB2_I2V2RXOUT_EN_LSB                                                                      27
+#define PHY_ANALOG_BB2_I2V2RXOUT_EN_MASK                                                             0x08000000
+#define PHY_ANALOG_BB2_I2V2RXOUT_EN_GET(x)                                           (((x) & 0x08000000) >> 27)
+#define PHY_ANALOG_BB2_I2V2RXOUT_EN_SET(x)                                           (((x) << 27) & 0x08000000)
+#define PHY_ANALOG_BB2_BQ2RXOUT_EN_MSB                                                                       28
+#define PHY_ANALOG_BB2_BQ2RXOUT_EN_LSB                                                                       28
+#define PHY_ANALOG_BB2_BQ2RXOUT_EN_MASK                                                              0x10000000
+#define PHY_ANALOG_BB2_BQ2RXOUT_EN_GET(x)                                            (((x) & 0x10000000) >> 28)
+#define PHY_ANALOG_BB2_BQ2RXOUT_EN_SET(x)                                            (((x) << 28) & 0x10000000)
+#define PHY_ANALOG_BB2_RXIN2I2V_EN_MSB                                                                       29
+#define PHY_ANALOG_BB2_RXIN2I2V_EN_LSB                                                                       29
+#define PHY_ANALOG_BB2_RXIN2I2V_EN_MASK                                                              0x20000000
+#define PHY_ANALOG_BB2_RXIN2I2V_EN_GET(x)                                            (((x) & 0x20000000) >> 29)
+#define PHY_ANALOG_BB2_RXIN2I2V_EN_SET(x)                                            (((x) << 29) & 0x20000000)
+#define PHY_ANALOG_BB2_RXIN2BQ_EN_MSB                                                                        30
+#define PHY_ANALOG_BB2_RXIN2BQ_EN_LSB                                                                        30
+#define PHY_ANALOG_BB2_RXIN2BQ_EN_MASK                                                               0x40000000
+#define PHY_ANALOG_BB2_RXIN2BQ_EN_GET(x)                                             (((x) & 0x40000000) >> 30)
+#define PHY_ANALOG_BB2_RXIN2BQ_EN_SET(x)                                             (((x) << 30) & 0x40000000)
+#define PHY_ANALOG_BB2_SWITCH_OVERRIDE_MSB                                                                   31
+#define PHY_ANALOG_BB2_SWITCH_OVERRIDE_LSB                                                                   31
+#define PHY_ANALOG_BB2_SWITCH_OVERRIDE_MASK                                                          0x80000000
+#define PHY_ANALOG_BB2_SWITCH_OVERRIDE_GET(x)                                        (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_BB2_SWITCH_OVERRIDE_SET(x)                                        (((x) << 31) & 0x80000000)
+
+/* macros for TOP1 */
+#define PHY_ANALOG_TOP1_ADDRESS                                                                      0x00000280
+#define PHY_ANALOG_TOP1_OFFSET                                                                       0x00000280
+#define PHY_ANALOG_TOP1_SEL_KVCO_MSB                                                                          1
+#define PHY_ANALOG_TOP1_SEL_KVCO_LSB                                                                          0
+#define PHY_ANALOG_TOP1_SEL_KVCO_MASK                                                                0x00000003
+#define PHY_ANALOG_TOP1_SEL_KVCO_GET(x)                                               (((x) & 0x00000003) >> 0)
+#define PHY_ANALOG_TOP1_SEL_KVCO_SET(x)                                               (((x) << 0) & 0x00000003)
+#define PHY_ANALOG_TOP1_PLLATB_MSB                                                                            3
+#define PHY_ANALOG_TOP1_PLLATB_LSB                                                                            2
+#define PHY_ANALOG_TOP1_PLLATB_MASK                                                                  0x0000000c
+#define PHY_ANALOG_TOP1_PLLATB_GET(x)                                                 (((x) & 0x0000000c) >> 2)
+#define PHY_ANALOG_TOP1_PLLATB_SET(x)                                                 (((x) << 2) & 0x0000000c)
+#define PHY_ANALOG_TOP1_PLL_SVREG_MSB                                                                         4
+#define PHY_ANALOG_TOP1_PLL_SVREG_LSB                                                                         4
+#define PHY_ANALOG_TOP1_PLL_SVREG_MASK                                                               0x00000010
+#define PHY_ANALOG_TOP1_PLL_SVREG_GET(x)                                              (((x) & 0x00000010) >> 4)
+#define PHY_ANALOG_TOP1_PLL_SVREG_SET(x)                                              (((x) << 4) & 0x00000010)
+#define PHY_ANALOG_TOP1_HI_FREQ_EN_MSB                                                                        5
+#define PHY_ANALOG_TOP1_HI_FREQ_EN_LSB                                                                        5
+#define PHY_ANALOG_TOP1_HI_FREQ_EN_MASK                                                              0x00000020
+#define PHY_ANALOG_TOP1_HI_FREQ_EN_GET(x)                                             (((x) & 0x00000020) >> 5)
+#define PHY_ANALOG_TOP1_HI_FREQ_EN_SET(x)                                             (((x) << 5) & 0x00000020)
+#define PHY_ANALOG_TOP1_PWDPLL_MSB                                                                            6
+#define PHY_ANALOG_TOP1_PWDPLL_LSB                                                                            6
+#define PHY_ANALOG_TOP1_PWDPLL_MASK                                                                  0x00000040
+#define PHY_ANALOG_TOP1_PWDPLL_GET(x)                                                 (((x) & 0x00000040) >> 6)
+#define PHY_ANALOG_TOP1_PWDPLL_SET(x)                                                 (((x) << 6) & 0x00000040)
+#define PHY_ANALOG_TOP1_PWDEXTCLKBUF_MSB                                                                      7
+#define PHY_ANALOG_TOP1_PWDEXTCLKBUF_LSB                                                                      7
+#define PHY_ANALOG_TOP1_PWDEXTCLKBUF_MASK                                                            0x00000080
+#define PHY_ANALOG_TOP1_PWDEXTCLKBUF_GET(x)                                           (((x) & 0x00000080) >> 7)
+#define PHY_ANALOG_TOP1_PWDEXTCLKBUF_SET(x)                                           (((x) << 7) & 0x00000080)
+#define PHY_ANALOG_TOP1_ADCPWD_PHASE_MSB                                                                      9
+#define PHY_ANALOG_TOP1_ADCPWD_PHASE_LSB                                                                      8
+#define PHY_ANALOG_TOP1_ADCPWD_PHASE_MASK                                                            0x00000300
+#define PHY_ANALOG_TOP1_ADCPWD_PHASE_GET(x)                                           (((x) & 0x00000300) >> 8)
+#define PHY_ANALOG_TOP1_ADCPWD_PHASE_SET(x)                                           (((x) << 8) & 0x00000300)
+#define PHY_ANALOG_TOP1_ADCCLK_PHASE_MSB                                                                     11
+#define PHY_ANALOG_TOP1_ADCCLK_PHASE_LSB                                                                     10
+#define PHY_ANALOG_TOP1_ADCCLK_PHASE_MASK                                                            0x00000c00
+#define PHY_ANALOG_TOP1_ADCCLK_PHASE_GET(x)                                          (((x) & 0x00000c00) >> 10)
+#define PHY_ANALOG_TOP1_ADCCLK_PHASE_SET(x)                                          (((x) << 10) & 0x00000c00)
+#define PHY_ANALOG_TOP1_DAC_CLK_SEL_MSB                                                                      13
+#define PHY_ANALOG_TOP1_DAC_CLK_SEL_LSB                                                                      12
+#define PHY_ANALOG_TOP1_DAC_CLK_SEL_MASK                                                             0x00003000
+#define PHY_ANALOG_TOP1_DAC_CLK_SEL_GET(x)                                           (((x) & 0x00003000) >> 12)
+#define PHY_ANALOG_TOP1_DAC_CLK_SEL_SET(x)                                           (((x) << 12) & 0x00003000)
+#define PHY_ANALOG_TOP1_ADC_CLK_SEL_MSB                                                                      15
+#define PHY_ANALOG_TOP1_ADC_CLK_SEL_LSB                                                                      14
+#define PHY_ANALOG_TOP1_ADC_CLK_SEL_MASK                                                             0x0000c000
+#define PHY_ANALOG_TOP1_ADC_CLK_SEL_GET(x)                                           (((x) & 0x0000c000) >> 14)
+#define PHY_ANALOG_TOP1_ADC_CLK_SEL_SET(x)                                           (((x) << 14) & 0x0000c000)
+#define PHY_ANALOG_TOP1_REFDIV_MSB                                                                           19
+#define PHY_ANALOG_TOP1_REFDIV_LSB                                                                           16
+#define PHY_ANALOG_TOP1_REFDIV_MASK                                                                  0x000f0000
+#define PHY_ANALOG_TOP1_REFDIV_GET(x)                                                (((x) & 0x000f0000) >> 16)
+#define PHY_ANALOG_TOP1_REFDIV_SET(x)                                                (((x) << 16) & 0x000f0000)
+#define PHY_ANALOG_TOP1_DIV_MSB                                                                              29
+#define PHY_ANALOG_TOP1_DIV_LSB                                                                              20
+#define PHY_ANALOG_TOP1_DIV_MASK                                                                     0x3ff00000
+#define PHY_ANALOG_TOP1_DIV_GET(x)                                                   (((x) & 0x3ff00000) >> 20)
+#define PHY_ANALOG_TOP1_DIV_SET(x)                                                   (((x) << 20) & 0x3ff00000)
+#define PHY_ANALOG_TOP1_PLLBYPASS_MSB                                                                        30
+#define PHY_ANALOG_TOP1_PLLBYPASS_LSB                                                                        30
+#define PHY_ANALOG_TOP1_PLLBYPASS_MASK                                                               0x40000000
+#define PHY_ANALOG_TOP1_PLLBYPASS_GET(x)                                             (((x) & 0x40000000) >> 30)
+#define PHY_ANALOG_TOP1_PLLBYPASS_SET(x)                                             (((x) << 30) & 0x40000000)
+#define PHY_ANALOG_TOP1_CLKMOD_RSTB_MSB                                                                      31
+#define PHY_ANALOG_TOP1_CLKMOD_RSTB_LSB                                                                      31
+#define PHY_ANALOG_TOP1_CLKMOD_RSTB_MASK                                                             0x80000000
+#define PHY_ANALOG_TOP1_CLKMOD_RSTB_GET(x)                                           (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_TOP1_CLKMOD_RSTB_SET(x)                                           (((x) << 31) & 0x80000000)
+
+/* macros for TOP2 */
+#define PHY_ANALOG_TOP2_ADDRESS                                                                      0x00000284
+#define PHY_ANALOG_TOP2_OFFSET                                                                       0x00000284
+#define PHY_ANALOG_TOP2_PLL_LOWLEAK_MSB                                                                       0
+#define PHY_ANALOG_TOP2_PLL_LOWLEAK_LSB                                                                       0
+#define PHY_ANALOG_TOP2_PLL_LOWLEAK_MASK                                                             0x00000001
+#define PHY_ANALOG_TOP2_PLL_LOWLEAK_GET(x)                                            (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_TOP2_PLL_LOWLEAK_SET(x)                                            (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_TOP2_PLL_LEAK_MSB                                                                          4
+#define PHY_ANALOG_TOP2_PLL_LEAK_LSB                                                                          1
+#define PHY_ANALOG_TOP2_PLL_LEAK_MASK                                                                0x0000001e
+#define PHY_ANALOG_TOP2_PLL_LEAK_GET(x)                                               (((x) & 0x0000001e) >> 1)
+#define PHY_ANALOG_TOP2_PLL_LEAK_SET(x)                                               (((x) << 1) & 0x0000001e)
+#define PHY_ANALOG_TOP2_PLLFRAC_MSB                                                                          19
+#define PHY_ANALOG_TOP2_PLLFRAC_LSB                                                                           5
+#define PHY_ANALOG_TOP2_PLLFRAC_MASK                                                                 0x000fffe0
+#define PHY_ANALOG_TOP2_PLLFRAC_GET(x)                                                (((x) & 0x000fffe0) >> 5)
+#define PHY_ANALOG_TOP2_PLLFRAC_SET(x)                                                (((x) << 5) & 0x000fffe0)
+#define PHY_ANALOG_TOP2_PWD_PLLSDM_MSB                                                                       20
+#define PHY_ANALOG_TOP2_PWD_PLLSDM_LSB                                                                       20
+#define PHY_ANALOG_TOP2_PWD_PLLSDM_MASK                                                              0x00100000
+#define PHY_ANALOG_TOP2_PWD_PLLSDM_GET(x)                                            (((x) & 0x00100000) >> 20)
+#define PHY_ANALOG_TOP2_PWD_PLLSDM_SET(x)                                            (((x) << 20) & 0x00100000)
+#define PHY_ANALOG_TOP2_PLLICP_MSB                                                                           23
+#define PHY_ANALOG_TOP2_PLLICP_LSB                                                                           21
+#define PHY_ANALOG_TOP2_PLLICP_MASK                                                                  0x00e00000
+#define PHY_ANALOG_TOP2_PLLICP_GET(x)                                                (((x) & 0x00e00000) >> 21)
+#define PHY_ANALOG_TOP2_PLLICP_SET(x)                                                (((x) << 21) & 0x00e00000)
+#define PHY_ANALOG_TOP2_PLLFILTER_MSB                                                                        31
+#define PHY_ANALOG_TOP2_PLLFILTER_LSB                                                                        24
+#define PHY_ANALOG_TOP2_PLLFILTER_MASK                                                               0xff000000
+#define PHY_ANALOG_TOP2_PLLFILTER_GET(x)                                             (((x) & 0xff000000) >> 24)
+#define PHY_ANALOG_TOP2_PLLFILTER_SET(x)                                             (((x) << 24) & 0xff000000)
+
+/* macros for TOP3 */
+#define PHY_ANALOG_TOP3_ADDRESS                                                                      0x00000288
+#define PHY_ANALOG_TOP3_OFFSET                                                                       0x00000288
+#define PHY_ANALOG_TOP3_INT2GND_MSB                                                                           0
+#define PHY_ANALOG_TOP3_INT2GND_LSB                                                                           0
+#define PHY_ANALOG_TOP3_INT2GND_MASK                                                                 0x00000001
+#define PHY_ANALOG_TOP3_INT2GND_GET(x)                                                (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_TOP3_INT2GND_SET(x)                                                (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_TOP3_PWDPALCLK_MSB                                                                         1
+#define PHY_ANALOG_TOP3_PWDPALCLK_LSB                                                                         1
+#define PHY_ANALOG_TOP3_PWDPALCLK_MASK                                                               0x00000002
+#define PHY_ANALOG_TOP3_PWDPALCLK_GET(x)                                              (((x) & 0x00000002) >> 1)
+#define PHY_ANALOG_TOP3_PWDPALCLK_SET(x)                                              (((x) << 1) & 0x00000002)
+#define PHY_ANALOG_TOP3_PWDAGCCLK_MSB                                                                         2
+#define PHY_ANALOG_TOP3_PWDAGCCLK_LSB                                                                         2
+#define PHY_ANALOG_TOP3_PWDAGCCLK_MASK                                                               0x00000004
+#define PHY_ANALOG_TOP3_PWDAGCCLK_GET(x)                                              (((x) & 0x00000004) >> 2)
+#define PHY_ANALOG_TOP3_PWDAGCCLK_SET(x)                                              (((x) << 2) & 0x00000004)
+#define PHY_ANALOG_TOP3_PWDV2I_MSB                                                                            3
+#define PHY_ANALOG_TOP3_PWDV2I_LSB                                                                            3
+#define PHY_ANALOG_TOP3_PWDV2I_MASK                                                                  0x00000008
+#define PHY_ANALOG_TOP3_PWDV2I_GET(x)                                                 (((x) & 0x00000008) >> 3)
+#define PHY_ANALOG_TOP3_PWDV2I_SET(x)                                                 (((x) << 3) & 0x00000008)
+#define PHY_ANALOG_TOP3_PWDBIAS_MSB                                                                           4
+#define PHY_ANALOG_TOP3_PWDBIAS_LSB                                                                           4
+#define PHY_ANALOG_TOP3_PWDBIAS_MASK                                                                 0x00000010
+#define PHY_ANALOG_TOP3_PWDBIAS_GET(x)                                                (((x) & 0x00000010) >> 4)
+#define PHY_ANALOG_TOP3_PWDBIAS_SET(x)                                                (((x) << 4) & 0x00000010)
+#define PHY_ANALOG_TOP3_PWDBG_MSB                                                                             5
+#define PHY_ANALOG_TOP3_PWDBG_LSB                                                                             5
+#define PHY_ANALOG_TOP3_PWDBG_MASK                                                                   0x00000020
+#define PHY_ANALOG_TOP3_PWDBG_GET(x)                                                  (((x) & 0x00000020) >> 5)
+#define PHY_ANALOG_TOP3_PWDBG_SET(x)                                                  (((x) << 5) & 0x00000020)
+#define PHY_ANALOG_TOP3_XTAL_SELVREG_MSB                                                                      6
+#define PHY_ANALOG_TOP3_XTAL_SELVREG_LSB                                                                      6
+#define PHY_ANALOG_TOP3_XTAL_SELVREG_MASK                                                            0x00000040
+#define PHY_ANALOG_TOP3_XTAL_SELVREG_GET(x)                                           (((x) & 0x00000040) >> 6)
+#define PHY_ANALOG_TOP3_XTAL_SELVREG_SET(x)                                           (((x) << 6) & 0x00000040)
+#define PHY_ANALOG_TOP3_XTAL_PWDREG_MSB                                                                       7
+#define PHY_ANALOG_TOP3_XTAL_PWDREG_LSB                                                                       7
+#define PHY_ANALOG_TOP3_XTAL_PWDREG_MASK                                                             0x00000080
+#define PHY_ANALOG_TOP3_XTAL_PWDREG_GET(x)                                            (((x) & 0x00000080) >> 7)
+#define PHY_ANALOG_TOP3_XTAL_PWDREG_SET(x)                                            (((x) << 7) & 0x00000080)
+#define PHY_ANALOG_TOP3_XTAL_PWDCLKIN_MSB                                                                     8
+#define PHY_ANALOG_TOP3_XTAL_PWDCLKIN_LSB                                                                     8
+#define PHY_ANALOG_TOP3_XTAL_PWDCLKIN_MASK                                                           0x00000100
+#define PHY_ANALOG_TOP3_XTAL_PWDCLKIN_GET(x)                                          (((x) & 0x00000100) >> 8)
+#define PHY_ANALOG_TOP3_XTAL_PWDCLKIN_SET(x)                                          (((x) << 8) & 0x00000100)
+#define PHY_ANALOG_TOP3_XTAL_PWDCLKD_MSB                                                                      9
+#define PHY_ANALOG_TOP3_XTAL_PWDCLKD_LSB                                                                      9
+#define PHY_ANALOG_TOP3_XTAL_PWDCLKD_MASK                                                            0x00000200
+#define PHY_ANALOG_TOP3_XTAL_PWDCLKD_GET(x)                                           (((x) & 0x00000200) >> 9)
+#define PHY_ANALOG_TOP3_XTAL_PWDCLKD_SET(x)                                           (((x) << 9) & 0x00000200)
+#define PHY_ANALOG_TOP3_XTAL_OSCON_MSB                                                                       10
+#define PHY_ANALOG_TOP3_XTAL_OSCON_LSB                                                                       10
+#define PHY_ANALOG_TOP3_XTAL_OSCON_MASK                                                              0x00000400
+#define PHY_ANALOG_TOP3_XTAL_OSCON_GET(x)                                            (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_TOP3_XTAL_OSCON_SET(x)                                            (((x) << 10) & 0x00000400)
+#define PHY_ANALOG_TOP3_XTAL_NOTCXODET_MSB                                                                   11
+#define PHY_ANALOG_TOP3_XTAL_NOTCXODET_LSB                                                                   11
+#define PHY_ANALOG_TOP3_XTAL_NOTCXODET_MASK                                                          0x00000800
+#define PHY_ANALOG_TOP3_XTAL_NOTCXODET_GET(x)                                        (((x) & 0x00000800) >> 11)
+#define PHY_ANALOG_TOP3_XTAL_NOTCXODET_SET(x)                                        (((x) << 11) & 0x00000800)
+#define PHY_ANALOG_TOP3_XTAL_LOCALBIAS_MSB                                                                   12
+#define PHY_ANALOG_TOP3_XTAL_LOCALBIAS_LSB                                                                   12
+#define PHY_ANALOG_TOP3_XTAL_LOCALBIAS_MASK                                                          0x00001000
+#define PHY_ANALOG_TOP3_XTAL_LOCALBIAS_GET(x)                                        (((x) & 0x00001000) >> 12)
+#define PHY_ANALOG_TOP3_XTAL_LOCALBIAS_SET(x)                                        (((x) << 12) & 0x00001000)
+#define PHY_ANALOG_TOP3_XTAL_HIGHZ_MSB                                                                       13
+#define PHY_ANALOG_TOP3_XTAL_HIGHZ_LSB                                                                       13
+#define PHY_ANALOG_TOP3_XTAL_HIGHZ_MASK                                                              0x00002000
+#define PHY_ANALOG_TOP3_XTAL_HIGHZ_GET(x)                                            (((x) & 0x00002000) >> 13)
+#define PHY_ANALOG_TOP3_XTAL_HIGHZ_SET(x)                                            (((x) << 13) & 0x00002000)
+#define PHY_ANALOG_TOP3_XTAL_DRVPNR_MSB                                                                      15
+#define PHY_ANALOG_TOP3_XTAL_DRVPNR_LSB                                                                      14
+#define PHY_ANALOG_TOP3_XTAL_DRVPNR_MASK                                                             0x0000c000
+#define PHY_ANALOG_TOP3_XTAL_DRVPNR_GET(x)                                           (((x) & 0x0000c000) >> 14)
+#define PHY_ANALOG_TOP3_XTAL_DRVPNR_SET(x)                                           (((x) << 14) & 0x0000c000)
+#define PHY_ANALOG_TOP3_XTALCAPOUTDAC_MSB                                                                    22
+#define PHY_ANALOG_TOP3_XTALCAPOUTDAC_LSB                                                                    16
+#define PHY_ANALOG_TOP3_XTALCAPOUTDAC_MASK                                                           0x007f0000
+#define PHY_ANALOG_TOP3_XTALCAPOUTDAC_GET(x)                                         (((x) & 0x007f0000) >> 16)
+#define PHY_ANALOG_TOP3_XTALCAPOUTDAC_SET(x)                                         (((x) << 16) & 0x007f0000)
+#define PHY_ANALOG_TOP3_XTAL_CAPINDAC_MSB                                                                    29
+#define PHY_ANALOG_TOP3_XTAL_CAPINDAC_LSB                                                                    23
+#define PHY_ANALOG_TOP3_XTAL_CAPINDAC_MASK                                                           0x3f800000
+#define PHY_ANALOG_TOP3_XTAL_CAPINDAC_GET(x)                                         (((x) & 0x3f800000) >> 23)
+#define PHY_ANALOG_TOP3_XTAL_CAPINDAC_SET(x)                                         (((x) << 23) & 0x3f800000)
+#define PHY_ANALOG_TOP3_XTAL_BIAS2X_MSB                                                                      30
+#define PHY_ANALOG_TOP3_XTAL_BIAS2X_LSB                                                                      30
+#define PHY_ANALOG_TOP3_XTAL_BIAS2X_MASK                                                             0x40000000
+#define PHY_ANALOG_TOP3_XTAL_BIAS2X_GET(x)                                           (((x) & 0x40000000) >> 30)
+#define PHY_ANALOG_TOP3_XTAL_BIAS2X_SET(x)                                           (((x) << 30) & 0x40000000)
+#define PHY_ANALOG_TOP3_TCXODET_MSB                                                                          31
+#define PHY_ANALOG_TOP3_TCXODET_LSB                                                                          31
+#define PHY_ANALOG_TOP3_TCXODET_MASK                                                                 0x80000000
+#define PHY_ANALOG_TOP3_TCXODET_GET(x)                                               (((x) & 0x80000000) >> 31)
+
+/* macros for TOP4 */
+#define PHY_ANALOG_TOP4_ADDRESS                                                                      0x0000028c
+#define PHY_ANALOG_TOP4_OFFSET                                                                       0x0000028c
+#define PHY_ANALOG_TOP4_SPARE4_MSB                                                                           19
+#define PHY_ANALOG_TOP4_SPARE4_LSB                                                                            0
+#define PHY_ANALOG_TOP4_SPARE4_MASK                                                                  0x000fffff
+#define PHY_ANALOG_TOP4_SPARE4_GET(x)                                                 (((x) & 0x000fffff) >> 0)
+#define PHY_ANALOG_TOP4_SPARE4_SET(x)                                                 (((x) << 0) & 0x000fffff)
+#define PHY_ANALOG_TOP4_SEL_TEMPSENSOR_MSB                                                                   20
+#define PHY_ANALOG_TOP4_SEL_TEMPSENSOR_LSB                                                                   20
+#define PHY_ANALOG_TOP4_SEL_TEMPSENSOR_MASK                                                          0x00100000
+#define PHY_ANALOG_TOP4_SEL_TEMPSENSOR_GET(x)                                        (((x) & 0x00100000) >> 20)
+#define PHY_ANALOG_TOP4_SEL_TEMPSENSOR_SET(x)                                        (((x) << 20) & 0x00100000)
+#define PHY_ANALOG_TOP4_ADCPWD_OVR_MSB                                                                       21
+#define PHY_ANALOG_TOP4_ADCPWD_OVR_LSB                                                                       21
+#define PHY_ANALOG_TOP4_ADCPWD_OVR_MASK                                                              0x00200000
+#define PHY_ANALOG_TOP4_ADCPWD_OVR_GET(x)                                            (((x) & 0x00200000) >> 21)
+#define PHY_ANALOG_TOP4_ADCPWD_OVR_SET(x)                                            (((x) << 21) & 0x00200000)
+#define PHY_ANALOG_TOP4_ADCPWD_INT_MSB                                                                       22
+#define PHY_ANALOG_TOP4_ADCPWD_INT_LSB                                                                       22
+#define PHY_ANALOG_TOP4_ADCPWD_INT_MASK                                                              0x00400000
+#define PHY_ANALOG_TOP4_ADCPWD_INT_GET(x)                                            (((x) & 0x00400000) >> 22)
+#define PHY_ANALOG_TOP4_ADCPWD_INT_SET(x)                                            (((x) << 22) & 0x00400000)
+#define PHY_ANALOG_TOP4_TESTIQ_OFF_MSB                                                                       23
+#define PHY_ANALOG_TOP4_TESTIQ_OFF_LSB                                                                       23
+#define PHY_ANALOG_TOP4_TESTIQ_OFF_MASK                                                              0x00800000
+#define PHY_ANALOG_TOP4_TESTIQ_OFF_GET(x)                                            (((x) & 0x00800000) >> 23)
+#define PHY_ANALOG_TOP4_TESTIQ_OFF_SET(x)                                            (((x) << 23) & 0x00800000)
+#define PHY_ANALOG_TOP4_TESTIQ_BUFEN_MSB                                                                     24
+#define PHY_ANALOG_TOP4_TESTIQ_BUFEN_LSB                                                                     24
+#define PHY_ANALOG_TOP4_TESTIQ_BUFEN_MASK                                                            0x01000000
+#define PHY_ANALOG_TOP4_TESTIQ_BUFEN_GET(x)                                          (((x) & 0x01000000) >> 24)
+#define PHY_ANALOG_TOP4_TESTIQ_BUFEN_SET(x)                                          (((x) << 24) & 0x01000000)
+#define PHY_ANALOG_TOP4_PAL_LOCKEDEN_MSB                                                                     25
+#define PHY_ANALOG_TOP4_PAL_LOCKEDEN_LSB                                                                     25
+#define PHY_ANALOG_TOP4_PAL_LOCKEDEN_MASK                                                            0x02000000
+#define PHY_ANALOG_TOP4_PAL_LOCKEDEN_GET(x)                                          (((x) & 0x02000000) >> 25)
+#define PHY_ANALOG_TOP4_PAL_LOCKEDEN_SET(x)                                          (((x) << 25) & 0x02000000)
+#define PHY_ANALOG_TOP4_SYNTHDIGOUTEN_MSB                                                                    26
+#define PHY_ANALOG_TOP4_SYNTHDIGOUTEN_LSB                                                                    26
+#define PHY_ANALOG_TOP4_SYNTHDIGOUTEN_MASK                                                           0x04000000
+#define PHY_ANALOG_TOP4_SYNTHDIGOUTEN_GET(x)                                         (((x) & 0x04000000) >> 26)
+#define PHY_ANALOG_TOP4_SYNTHDIGOUTEN_SET(x)                                         (((x) << 26) & 0x04000000)
+#define PHY_ANALOG_TOP4_ENBTCLK_MSB                                                                          27
+#define PHY_ANALOG_TOP4_ENBTCLK_LSB                                                                          27
+#define PHY_ANALOG_TOP4_ENBTCLK_MASK                                                                 0x08000000
+#define PHY_ANALOG_TOP4_ENBTCLK_GET(x)                                               (((x) & 0x08000000) >> 27)
+#define PHY_ANALOG_TOP4_ENBTCLK_SET(x)                                               (((x) << 27) & 0x08000000)
+#define PHY_ANALOG_TOP4_PAD2GND_MSB                                                                          28
+#define PHY_ANALOG_TOP4_PAD2GND_LSB                                                                          28
+#define PHY_ANALOG_TOP4_PAD2GND_MASK                                                                 0x10000000
+#define PHY_ANALOG_TOP4_PAD2GND_GET(x)                                               (((x) & 0x10000000) >> 28)
+#define PHY_ANALOG_TOP4_PAD2GND_SET(x)                                               (((x) << 28) & 0x10000000)
+#define PHY_ANALOG_TOP4_INTH2PAD_MSB                                                                         29
+#define PHY_ANALOG_TOP4_INTH2PAD_LSB                                                                         29
+#define PHY_ANALOG_TOP4_INTH2PAD_MASK                                                                0x20000000
+#define PHY_ANALOG_TOP4_INTH2PAD_GET(x)                                              (((x) & 0x20000000) >> 29)
+#define PHY_ANALOG_TOP4_INTH2PAD_SET(x)                                              (((x) << 29) & 0x20000000)
+#define PHY_ANALOG_TOP4_INTH2GND_MSB                                                                         30
+#define PHY_ANALOG_TOP4_INTH2GND_LSB                                                                         30
+#define PHY_ANALOG_TOP4_INTH2GND_MASK                                                                0x40000000
+#define PHY_ANALOG_TOP4_INTH2GND_GET(x)                                              (((x) & 0x40000000) >> 30)
+#define PHY_ANALOG_TOP4_INTH2GND_SET(x)                                              (((x) << 30) & 0x40000000)
+#define PHY_ANALOG_TOP4_INT2PAD_MSB                                                                          31
+#define PHY_ANALOG_TOP4_INT2PAD_LSB                                                                          31
+#define PHY_ANALOG_TOP4_INT2PAD_MASK                                                                 0x80000000
+#define PHY_ANALOG_TOP4_INT2PAD_GET(x)                                               (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_TOP4_INT2PAD_SET(x)                                               (((x) << 31) & 0x80000000)
+
+/* macros for rbist_cntrl */
+#define PHY_ANALOG_RBIST_CNTRL_ADDRESS                                                               0x00000380
+#define PHY_ANALOG_RBIST_CNTRL_OFFSET                                                                0x00000380
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_MSB                                                      0
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_LSB                                                      0
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_MASK                                            0x00000001
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_GET(x)                           (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_SET(x)                           (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_MSB                                                   1
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_LSB                                                   1
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_MASK                                         0x00000002
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_GET(x)                        (((x) & 0x00000002) >> 1)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_SET(x)                        (((x) << 1) & 0x00000002)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_MSB                                                   2
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_LSB                                                   2
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_MASK                                         0x00000004
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_GET(x)                        (((x) & 0x00000004) >> 2)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_SET(x)                        (((x) << 2) & 0x00000004)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_MSB                                                 3
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_LSB                                                 3
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_MASK                                       0x00000008
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_GET(x)                      (((x) & 0x00000008) >> 3)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_SET(x)                      (((x) << 3) & 0x00000008)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_MSB                                               4
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_LSB                                               4
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_MASK                                     0x00000010
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_GET(x)                    (((x) & 0x00000010) >> 4)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_SET(x)                    (((x) << 4) & 0x00000010)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_MSB                                               5
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_LSB                                               5
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_MASK                                     0x00000020
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_GET(x)                    (((x) & 0x00000020) >> 5)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_SET(x)                    (((x) << 5) & 0x00000020)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_MSB                                                  6
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_LSB                                                  6
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_MASK                                        0x00000040
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_GET(x)                       (((x) & 0x00000040) >> 6)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_SET(x)                       (((x) << 6) & 0x00000040)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_MSB                                                  7
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_LSB                                                  7
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_MASK                                        0x00000080
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_GET(x)                       (((x) & 0x00000080) >> 7)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_SET(x)                       (((x) << 7) & 0x00000080)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_MSB                                                8
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_LSB                                                8
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_MASK                                      0x00000100
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_GET(x)                     (((x) & 0x00000100) >> 8)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_SET(x)                     (((x) << 8) & 0x00000100)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_MSB                                                         9
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_LSB                                                         9
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_MASK                                               0x00000200
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_GET(x)                              (((x) & 0x00000200) >> 9)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_SET(x)                              (((x) << 9) & 0x00000200)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_MSB                                                      10
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_LSB                                                      10
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_MASK                                             0x00000400
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_GET(x)                           (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_SET(x)                           (((x) << 10) & 0x00000400)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_MSB                                                     11
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_LSB                                                     11
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_MASK                                            0x00000800
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_GET(x)                          (((x) & 0x00000800) >> 11)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_SET(x)                          (((x) << 11) & 0x00000800)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_MSB                                                        12
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_LSB                                                        12
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_MASK                                               0x00001000
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_GET(x)                             (((x) & 0x00001000) >> 12)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_SET(x)                             (((x) << 12) & 0x00001000)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_MSB                                                      13
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_LSB                                                      13
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_MASK                                             0x00002000
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_GET(x)                           (((x) & 0x00002000) >> 13)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_SET(x)                           (((x) << 13) & 0x00002000)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_MSB                                                 14
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_LSB                                                 14
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_MASK                                        0x00004000
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_GET(x)                      (((x) & 0x00004000) >> 14)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_SET(x)                      (((x) << 14) & 0x00004000)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_MSB                                                       15
+#define PHY_ANALOG_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_LSB                                                       15
+#define PHY_ANALOG_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_MASK                                              0x00008000
+#define PHY_ANALOG_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_GET(x)                            (((x) & 0x00008000) >> 15)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_SET(x)                            (((x) << 15) & 0x00008000)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_RBIST_ENABLE_MSB                                                          16
+#define PHY_ANALOG_RBIST_CNTRL_ATE_RBIST_ENABLE_LSB                                                          16
+#define PHY_ANALOG_RBIST_CNTRL_ATE_RBIST_ENABLE_MASK                                                 0x00010000
+#define PHY_ANALOG_RBIST_CNTRL_ATE_RBIST_ENABLE_GET(x)                               (((x) & 0x00010000) >> 16)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_RBIST_ENABLE_SET(x)                               (((x) << 16) & 0x00010000)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_ADC_CLK_INVERT_MSB                                                        17
+#define PHY_ANALOG_RBIST_CNTRL_ATE_ADC_CLK_INVERT_LSB                                                        17
+#define PHY_ANALOG_RBIST_CNTRL_ATE_ADC_CLK_INVERT_MASK                                               0x00020000
+#define PHY_ANALOG_RBIST_CNTRL_ATE_ADC_CLK_INVERT_GET(x)                             (((x) & 0x00020000) >> 17)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_ADC_CLK_INVERT_SET(x)                             (((x) << 17) & 0x00020000)
+
+/* macros for tx_dc_offset */
+#define PHY_ANALOG_TX_DC_OFFSET_ADDRESS                                                              0x00000384
+#define PHY_ANALOG_TX_DC_OFFSET_OFFSET                                                               0x00000384
+#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_I_MSB                                                         10
+#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_I_LSB                                                          0
+#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_I_MASK                                                0x000007ff
+#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_I_GET(x)                               (((x) & 0x000007ff) >> 0)
+#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_I_SET(x)                               (((x) << 0) & 0x000007ff)
+#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_MSB                                                         26
+#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_LSB                                                         16
+#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_MASK                                                0x07ff0000
+#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_GET(x)                              (((x) & 0x07ff0000) >> 16)
+#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_SET(x)                              (((x) << 16) & 0x07ff0000)
+
+/* macros for tx_tonegen0 */
+#define PHY_ANALOG_TX_TONEGEN0_ADDRESS                                                               0x00000388
+#define PHY_ANALOG_TX_TONEGEN0_OFFSET                                                                0x00000388
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_MSB                                                      6
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_LSB                                                      0
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_MASK                                            0x0000007f
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_GET(x)                           (((x) & 0x0000007f) >> 0)
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_SET(x)                           (((x) << 0) & 0x0000007f)
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_EXP_MSB                                                    11
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_EXP_LSB                                                     8
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_EXP_MASK                                           0x00000f00
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_EXP_GET(x)                          (((x) & 0x00000f00) >> 8)
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_EXP_SET(x)                          (((x) << 8) & 0x00000f00)
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_MAN_MSB                                                    23
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_MAN_LSB                                                    16
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_MAN_MASK                                           0x00ff0000
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_MAN_GET(x)                         (((x) & 0x00ff0000) >> 16)
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_MAN_SET(x)                         (((x) << 16) & 0x00ff0000)
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_MSB                                                    30
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_LSB                                                    24
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_MASK                                           0x7f000000
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_GET(x)                         (((x) & 0x7f000000) >> 24)
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_SET(x)                         (((x) << 24) & 0x7f000000)
+
+/* macros for tx_tonegen1 */
+#define PHY_ANALOG_TX_TONEGEN1_ADDRESS                                                               0x0000038c
+#define PHY_ANALOG_TX_TONEGEN1_OFFSET                                                                0x0000038c
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_MSB                                                      6
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_LSB                                                      0
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_MASK                                            0x0000007f
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_GET(x)                           (((x) & 0x0000007f) >> 0)
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_SET(x)                           (((x) << 0) & 0x0000007f)
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_EXP_MSB                                                    11
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_EXP_LSB                                                     8
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_EXP_MASK                                           0x00000f00
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_EXP_GET(x)                          (((x) & 0x00000f00) >> 8)
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_EXP_SET(x)                          (((x) << 8) & 0x00000f00)
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_MAN_MSB                                                    23
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_MAN_LSB                                                    16
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_MAN_MASK                                           0x00ff0000
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_MAN_GET(x)                         (((x) & 0x00ff0000) >> 16)
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_MAN_SET(x)                         (((x) << 16) & 0x00ff0000)
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_MSB                                                    30
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_LSB                                                    24
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_MASK                                           0x7f000000
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_GET(x)                         (((x) & 0x7f000000) >> 24)
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_SET(x)                         (((x) << 24) & 0x7f000000)
+
+/* macros for tx_lftonegen0 */
+#define PHY_ANALOG_TX_LFTONEGEN0_ADDRESS                                                             0x00000390
+#define PHY_ANALOG_TX_LFTONEGEN0_OFFSET                                                              0x00000390
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_MSB                                                    6
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_LSB                                                    0
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_MASK                                          0x0000007f
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_GET(x)                         (((x) & 0x0000007f) >> 0)
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_SET(x)                         (((x) << 0) & 0x0000007f)
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_EXP_MSB                                                  11
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_EXP_LSB                                                   8
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_EXP_MASK                                         0x00000f00
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_EXP_GET(x)                        (((x) & 0x00000f00) >> 8)
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_EXP_SET(x)                        (((x) << 8) & 0x00000f00)
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_MAN_MSB                                                  23
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_MAN_LSB                                                  16
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_MAN_MASK                                         0x00ff0000
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_MAN_GET(x)                       (((x) & 0x00ff0000) >> 16)
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_MAN_SET(x)                       (((x) << 16) & 0x00ff0000)
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_MSB                                                  30
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_LSB                                                  24
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_MASK                                         0x7f000000
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_GET(x)                       (((x) & 0x7f000000) >> 24)
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_SET(x)                       (((x) << 24) & 0x7f000000)
+
+/* macros for tx_linear_ramp_i */
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ADDRESS                                                          0x00000394
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_OFFSET                                                           0x00000394
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_MSB                                             10
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_LSB                                              0
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_MASK                                    0x000007ff
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_GET(x)                   (((x) & 0x000007ff) >> 0)
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_SET(x)                   (((x) << 0) & 0x000007ff)
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_MSB                                            21
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_LSB                                            12
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_MASK                                   0x003ff000
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_GET(x)                 (((x) & 0x003ff000) >> 12)
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_SET(x)                 (((x) << 12) & 0x003ff000)
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_MSB                                             29
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_LSB                                             24
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_MASK                                    0x3f000000
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_GET(x)                  (((x) & 0x3f000000) >> 24)
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_SET(x)                  (((x) << 24) & 0x3f000000)
+
+/* macros for tx_linear_ramp_q */
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ADDRESS                                                          0x00000398
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_OFFSET                                                           0x00000398
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_MSB                                             10
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_LSB                                              0
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_MASK                                    0x000007ff
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_GET(x)                   (((x) & 0x000007ff) >> 0)
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_SET(x)                   (((x) << 0) & 0x000007ff)
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_MSB                                            21
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_LSB                                            12
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_MASK                                   0x003ff000
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_GET(x)                 (((x) & 0x003ff000) >> 12)
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_SET(x)                 (((x) << 12) & 0x003ff000)
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_MSB                                             29
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_LSB                                             24
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_MASK                                    0x3f000000
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_GET(x)                  (((x) & 0x3f000000) >> 24)
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_SET(x)                  (((x) << 24) & 0x3f000000)
+
+/* macros for tx_prbs_mag */
+#define PHY_ANALOG_TX_PRBS_MAG_ADDRESS                                                               0x0000039c
+#define PHY_ANALOG_TX_PRBS_MAG_OFFSET                                                                0x0000039c
+#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_MSB                                               9
+#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_LSB                                               0
+#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_MASK                                     0x000003ff
+#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_GET(x)                    (((x) & 0x000003ff) >> 0)
+#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_SET(x)                    (((x) << 0) & 0x000003ff)
+#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_MSB                                              25
+#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_LSB                                              16
+#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_MASK                                     0x03ff0000
+#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_GET(x)                   (((x) & 0x03ff0000) >> 16)
+#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_SET(x)                   (((x) << 16) & 0x03ff0000)
+
+/* macros for tx_prbs_seed_i */
+#define PHY_ANALOG_TX_PRBS_SEED_I_ADDRESS                                                            0x000003a0
+#define PHY_ANALOG_TX_PRBS_SEED_I_OFFSET                                                             0x000003a0
+#define PHY_ANALOG_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_MSB                                                  30
+#define PHY_ANALOG_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_LSB                                                   0
+#define PHY_ANALOG_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_MASK                                         0x7fffffff
+#define PHY_ANALOG_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_GET(x)                        (((x) & 0x7fffffff) >> 0)
+#define PHY_ANALOG_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_SET(x)                        (((x) << 0) & 0x7fffffff)
+
+/* macros for tx_prbs_seed_q */
+#define PHY_ANALOG_TX_PRBS_SEED_Q_ADDRESS                                                            0x000003a4
+#define PHY_ANALOG_TX_PRBS_SEED_Q_OFFSET                                                             0x000003a4
+#define PHY_ANALOG_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_MSB                                                  30
+#define PHY_ANALOG_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_LSB                                                   0
+#define PHY_ANALOG_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_MASK                                         0x7fffffff
+#define PHY_ANALOG_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_GET(x)                        (((x) & 0x7fffffff) >> 0)
+#define PHY_ANALOG_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_SET(x)                        (((x) << 0) & 0x7fffffff)
+
+/* macros for cmac_dc_cancel */
+#define PHY_ANALOG_CMAC_DC_CANCEL_ADDRESS                                                            0x000003a8
+#define PHY_ANALOG_CMAC_DC_CANCEL_OFFSET                                                             0x000003a8
+#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_MSB                                                    9
+#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_LSB                                                    0
+#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_MASK                                          0x000003ff
+#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_GET(x)                         (((x) & 0x000003ff) >> 0)
+#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_SET(x)                         (((x) << 0) & 0x000003ff)
+#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_MSB                                                   25
+#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_LSB                                                   16
+#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_MASK                                          0x03ff0000
+#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_GET(x)                        (((x) & 0x03ff0000) >> 16)
+#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_SET(x)                        (((x) << 16) & 0x03ff0000)
+
+/* macros for cmac_dc_offset */
+#define PHY_ANALOG_CMAC_DC_OFFSET_ADDRESS                                                            0x000003ac
+#define PHY_ANALOG_CMAC_DC_OFFSET_OFFSET                                                             0x000003ac
+#define PHY_ANALOG_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_MSB                                                      3
+#define PHY_ANALOG_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_LSB                                                      0
+#define PHY_ANALOG_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_MASK                                            0x0000000f
+#define PHY_ANALOG_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_GET(x)                           (((x) & 0x0000000f) >> 0)
+#define PHY_ANALOG_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_SET(x)                           (((x) << 0) & 0x0000000f)
+
+/* macros for cmac_corr */
+#define PHY_ANALOG_CMAC_CORR_ADDRESS                                                                 0x000003b0
+#define PHY_ANALOG_CMAC_CORR_OFFSET                                                                  0x000003b0
+#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_CYCLES_MSB                                                         4
+#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_CYCLES_LSB                                                         0
+#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_CYCLES_MASK                                               0x0000001f
+#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_CYCLES_GET(x)                              (((x) & 0x0000001f) >> 0)
+#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_CYCLES_SET(x)                              (((x) << 0) & 0x0000001f)
+#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_FREQ_MSB                                                          13
+#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_FREQ_LSB                                                           8
+#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_FREQ_MASK                                                 0x00003f00
+#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_FREQ_GET(x)                                (((x) & 0x00003f00) >> 8)
+#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_FREQ_SET(x)                                (((x) << 8) & 0x00003f00)
+
+/* macros for cmac_power */
+#define PHY_ANALOG_CMAC_POWER_ADDRESS                                                                0x000003b4
+#define PHY_ANALOG_CMAC_POWER_OFFSET                                                                 0x000003b4
+#define PHY_ANALOG_CMAC_POWER_ATE_CMAC_POWER_CYCLES_MSB                                                       3
+#define PHY_ANALOG_CMAC_POWER_ATE_CMAC_POWER_CYCLES_LSB                                                       0
+#define PHY_ANALOG_CMAC_POWER_ATE_CMAC_POWER_CYCLES_MASK                                             0x0000000f
+#define PHY_ANALOG_CMAC_POWER_ATE_CMAC_POWER_CYCLES_GET(x)                            (((x) & 0x0000000f) >> 0)
+#define PHY_ANALOG_CMAC_POWER_ATE_CMAC_POWER_CYCLES_SET(x)                            (((x) << 0) & 0x0000000f)
+
+/* macros for cmac_cross_corr */
+#define PHY_ANALOG_CMAC_CROSS_CORR_ADDRESS                                                           0x000003b8
+#define PHY_ANALOG_CMAC_CROSS_CORR_OFFSET                                                            0x000003b8
+#define PHY_ANALOG_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_MSB                                                     3
+#define PHY_ANALOG_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_LSB                                                     0
+#define PHY_ANALOG_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_MASK                                           0x0000000f
+#define PHY_ANALOG_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_GET(x)                          (((x) & 0x0000000f) >> 0)
+#define PHY_ANALOG_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_SET(x)                          (((x) << 0) & 0x0000000f)
+
+/* macros for cmac_i2q2 */
+#define PHY_ANALOG_CMAC_I2Q2_ADDRESS                                                                 0x000003bc
+#define PHY_ANALOG_CMAC_I2Q2_OFFSET                                                                  0x000003bc
+#define PHY_ANALOG_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_MSB                                                         3
+#define PHY_ANALOG_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_LSB                                                         0
+#define PHY_ANALOG_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_MASK                                               0x0000000f
+#define PHY_ANALOG_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_GET(x)                              (((x) & 0x0000000f) >> 0)
+#define PHY_ANALOG_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_SET(x)                              (((x) << 0) & 0x0000000f)
+
+/* macros for cmac_power_hpf */
+#define PHY_ANALOG_CMAC_POWER_HPF_ADDRESS                                                            0x000003c0
+#define PHY_ANALOG_CMAC_POWER_HPF_OFFSET                                                             0x000003c0
+#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_MSB                                               3
+#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_LSB                                               0
+#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_MASK                                     0x0000000f
+#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_GET(x)                    (((x) & 0x0000000f) >> 0)
+#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_SET(x)                    (((x) << 0) & 0x0000000f)
+#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_MSB                                                 7
+#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_LSB                                                 4
+#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_MASK                                       0x000000f0
+#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_GET(x)                      (((x) & 0x000000f0) >> 4)
+#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_SET(x)                      (((x) << 4) & 0x000000f0)
+
+/* macros for rxdac_set1 */
+#define PHY_ANALOG_RXDAC_SET1_ADDRESS                                                                0x000003c4
+#define PHY_ANALOG_RXDAC_SET1_OFFSET                                                                 0x000003c4
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_MUX_MSB                                                               1
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_MUX_LSB                                                               0
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_MUX_MASK                                                     0x00000003
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_MUX_GET(x)                                    (((x) & 0x00000003) >> 0)
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_MUX_SET(x)                                    (((x) << 0) & 0x00000003)
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_HI_GAIN_MSB                                                           4
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_HI_GAIN_LSB                                                           4
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_HI_GAIN_MASK                                                 0x00000010
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_HI_GAIN_GET(x)                                (((x) & 0x00000010) >> 4)
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_HI_GAIN_SET(x)                                (((x) << 4) & 0x00000010)
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_MSB                                                         13
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_LSB                                                          8
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_MASK                                                0x00003f00
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_GET(x)                               (((x) & 0x00003f00) >> 8)
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_SET(x)                               (((x) << 8) & 0x00003f00)
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_MSB                                                 19
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_LSB                                                 16
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_MASK                                        0x000f0000
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_GET(x)                      (((x) & 0x000f0000) >> 16)
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_SET(x)                      (((x) << 16) & 0x000f0000)
+
+/* macros for rxdac_set2 */
+#define PHY_ANALOG_RXDAC_SET2_ADDRESS                                                                0x000003c8
+#define PHY_ANALOG_RXDAC_SET2_OFFSET                                                                 0x000003c8
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_HI_MSB                                                              4
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_HI_LSB                                                              0
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_HI_MASK                                                    0x0000001f
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_HI_GET(x)                                   (((x) & 0x0000001f) >> 0)
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_HI_SET(x)                                   (((x) << 0) & 0x0000001f)
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_HI_MSB                                                             12
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_HI_LSB                                                              8
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_HI_MASK                                                    0x00001f00
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_HI_GET(x)                                   (((x) & 0x00001f00) >> 8)
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_HI_SET(x)                                   (((x) << 8) & 0x00001f00)
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_LOW_MSB                                                            20
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_LOW_LSB                                                            16
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_LOW_MASK                                                   0x001f0000
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_LOW_GET(x)                                 (((x) & 0x001f0000) >> 16)
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_LOW_SET(x)                                 (((x) << 16) & 0x001f0000)
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_LOW_MSB                                                            28
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_LOW_LSB                                                            24
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_LOW_MASK                                                   0x1f000000
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_LOW_GET(x)                                 (((x) & 0x1f000000) >> 24)
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_LOW_SET(x)                                 (((x) << 24) & 0x1f000000)
+
+/* macros for rxdac_long_shift */
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_ADDRESS                                                          0x000003cc
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_OFFSET                                                           0x000003cc
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_MSB                                                    4
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_LSB                                                    0
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_MASK                                          0x0000001f
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_GET(x)                         (((x) & 0x0000001f) >> 0)
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_SET(x)                         (((x) << 0) & 0x0000001f)
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_MSB                                                   12
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_LSB                                                    8
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_MASK                                          0x00001f00
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_GET(x)                         (((x) & 0x00001f00) >> 8)
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_SET(x)                         (((x) << 8) & 0x00001f00)
+
+/* macros for cmac_results_i */
+#define PHY_ANALOG_CMAC_RESULTS_I_ADDRESS                                                            0x000003d0
+#define PHY_ANALOG_CMAC_RESULTS_I_OFFSET                                                             0x000003d0
+#define PHY_ANALOG_CMAC_RESULTS_I_ATE_CMAC_RESULTS_MSB                                                       31
+#define PHY_ANALOG_CMAC_RESULTS_I_ATE_CMAC_RESULTS_LSB                                                        0
+#define PHY_ANALOG_CMAC_RESULTS_I_ATE_CMAC_RESULTS_MASK                                              0xffffffff
+#define PHY_ANALOG_CMAC_RESULTS_I_ATE_CMAC_RESULTS_GET(x)                             (((x) & 0xffffffff) >> 0)
+#define PHY_ANALOG_CMAC_RESULTS_I_ATE_CMAC_RESULTS_SET(x)                             (((x) << 0) & 0xffffffff)
+
+/* macros for cmac_results_q */
+#define PHY_ANALOG_CMAC_RESULTS_Q_ADDRESS                                                            0x000003d4
+#define PHY_ANALOG_CMAC_RESULTS_Q_OFFSET                                                             0x000003d4
+#define PHY_ANALOG_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_MSB                                                       31
+#define PHY_ANALOG_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_LSB                                                        0
+#define PHY_ANALOG_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_MASK                                              0xffffffff
+#define PHY_ANALOG_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_GET(x)                             (((x) & 0xffffffff) >> 0)
+#define PHY_ANALOG_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_SET(x)                             (((x) << 0) & 0xffffffff)
+
+/* macros for PMU1 */
+#define PHY_ANALOG_PMU1_ADDRESS                                                                      0x00000740
+#define PHY_ANALOG_PMU1_OFFSET                                                                       0x00000740
+#define PHY_ANALOG_PMU1_SPARE_MSB                                                                            10
+#define PHY_ANALOG_PMU1_SPARE_LSB                                                                             0
+#define PHY_ANALOG_PMU1_SPARE_MASK                                                                   0x000007ff
+#define PHY_ANALOG_PMU1_SPARE_GET(x)                                                  (((x) & 0x000007ff) >> 0)
+#define PHY_ANALOG_PMU1_SPARE_SET(x)                                                  (((x) << 0) & 0x000007ff)
+#define PHY_ANALOG_PMU1_OTP_V25_PWD_MSB                                                                      11
+#define PHY_ANALOG_PMU1_OTP_V25_PWD_LSB                                                                      11
+#define PHY_ANALOG_PMU1_OTP_V25_PWD_MASK                                                             0x00000800
+#define PHY_ANALOG_PMU1_OTP_V25_PWD_GET(x)                                           (((x) & 0x00000800) >> 11)
+#define PHY_ANALOG_PMU1_OTP_V25_PWD_SET(x)                                           (((x) << 11) & 0x00000800)
+#define PHY_ANALOG_PMU1_PAREGON_MAN_MSB                                                                      12
+#define PHY_ANALOG_PMU1_PAREGON_MAN_LSB                                                                      12
+#define PHY_ANALOG_PMU1_PAREGON_MAN_MASK                                                             0x00001000
+#define PHY_ANALOG_PMU1_PAREGON_MAN_GET(x)                                           (((x) & 0x00001000) >> 12)
+#define PHY_ANALOG_PMU1_PAREGON_MAN_SET(x)                                           (((x) << 12) & 0x00001000)
+#define PHY_ANALOG_PMU1_OTPREGON_MAN_MSB                                                                     13
+#define PHY_ANALOG_PMU1_OTPREGON_MAN_LSB                                                                     13
+#define PHY_ANALOG_PMU1_OTPREGON_MAN_MASK                                                            0x00002000
+#define PHY_ANALOG_PMU1_OTPREGON_MAN_GET(x)                                          (((x) & 0x00002000) >> 13)
+#define PHY_ANALOG_PMU1_OTPREGON_MAN_SET(x)                                          (((x) << 13) & 0x00002000)
+#define PHY_ANALOG_PMU1_DREGON_MAN_MSB                                                                       14
+#define PHY_ANALOG_PMU1_DREGON_MAN_LSB                                                                       14
+#define PHY_ANALOG_PMU1_DREGON_MAN_MASK                                                              0x00004000
+#define PHY_ANALOG_PMU1_DREGON_MAN_GET(x)                                            (((x) & 0x00004000) >> 14)
+#define PHY_ANALOG_PMU1_DREGON_MAN_SET(x)                                            (((x) << 14) & 0x00004000)
+#define PHY_ANALOG_PMU1_DISCONTMODEEN_MSB                                                                    15
+#define PHY_ANALOG_PMU1_DISCONTMODEEN_LSB                                                                    15
+#define PHY_ANALOG_PMU1_DISCONTMODEEN_MASK                                                           0x00008000
+#define PHY_ANALOG_PMU1_DISCONTMODEEN_GET(x)                                         (((x) & 0x00008000) >> 15)
+#define PHY_ANALOG_PMU1_DISCONTMODEEN_SET(x)                                         (((x) << 15) & 0x00008000)
+#define PHY_ANALOG_PMU1_SWREGON_MAN_MSB                                                                      16
+#define PHY_ANALOG_PMU1_SWREGON_MAN_LSB                                                                      16
+#define PHY_ANALOG_PMU1_SWREGON_MAN_MASK                                                             0x00010000
+#define PHY_ANALOG_PMU1_SWREGON_MAN_GET(x)                                           (((x) & 0x00010000) >> 16)
+#define PHY_ANALOG_PMU1_SWREGON_MAN_SET(x)                                           (((x) << 16) & 0x00010000)
+#define PHY_ANALOG_PMU1_SWREG_FREQCUR_MSB                                                                    18
+#define PHY_ANALOG_PMU1_SWREG_FREQCUR_LSB                                                                    17
+#define PHY_ANALOG_PMU1_SWREG_FREQCUR_MASK                                                           0x00060000
+#define PHY_ANALOG_PMU1_SWREG_FREQCUR_GET(x)                                         (((x) & 0x00060000) >> 17)
+#define PHY_ANALOG_PMU1_SWREG_FREQCUR_SET(x)                                         (((x) << 17) & 0x00060000)
+#define PHY_ANALOG_PMU1_SWREG_FREQCAP_MSB                                                                    21
+#define PHY_ANALOG_PMU1_SWREG_FREQCAP_LSB                                                                    19
+#define PHY_ANALOG_PMU1_SWREG_FREQCAP_MASK                                                           0x00380000
+#define PHY_ANALOG_PMU1_SWREG_FREQCAP_GET(x)                                         (((x) & 0x00380000) >> 19)
+#define PHY_ANALOG_PMU1_SWREG_FREQCAP_SET(x)                                         (((x) << 19) & 0x00380000)
+#define PHY_ANALOG_PMU1_SWREG_LVLCTR_MSB                                                                     23
+#define PHY_ANALOG_PMU1_SWREG_LVLCTR_LSB                                                                     22
+#define PHY_ANALOG_PMU1_SWREG_LVLCTR_MASK                                                            0x00c00000
+#define PHY_ANALOG_PMU1_SWREG_LVLCTR_GET(x)                                          (((x) & 0x00c00000) >> 22)
+#define PHY_ANALOG_PMU1_SWREG_LVLCTR_SET(x)                                          (((x) << 22) & 0x00c00000)
+#define PHY_ANALOG_PMU1_SREG_LVLCTR_MSB                                                                      25
+#define PHY_ANALOG_PMU1_SREG_LVLCTR_LSB                                                                      24
+#define PHY_ANALOG_PMU1_SREG_LVLCTR_MASK                                                             0x03000000
+#define PHY_ANALOG_PMU1_SREG_LVLCTR_GET(x)                                           (((x) & 0x03000000) >> 24)
+#define PHY_ANALOG_PMU1_SREG_LVLCTR_SET(x)                                           (((x) << 24) & 0x03000000)
+#define PHY_ANALOG_PMU1_DREG_LVLCTR_MSB                                                                      27
+#define PHY_ANALOG_PMU1_DREG_LVLCTR_LSB                                                                      26
+#define PHY_ANALOG_PMU1_DREG_LVLCTR_MASK                                                             0x0c000000
+#define PHY_ANALOG_PMU1_DREG_LVLCTR_GET(x)                                           (((x) & 0x0c000000) >> 26)
+#define PHY_ANALOG_PMU1_DREG_LVLCTR_SET(x)                                           (((x) << 26) & 0x0c000000)
+#define PHY_ANALOG_PMU1_PAREG_XPNP_MSB                                                                       28
+#define PHY_ANALOG_PMU1_PAREG_XPNP_LSB                                                                       28
+#define PHY_ANALOG_PMU1_PAREG_XPNP_MASK                                                              0x10000000
+#define PHY_ANALOG_PMU1_PAREG_XPNP_GET(x)                                            (((x) & 0x10000000) >> 28)
+#define PHY_ANALOG_PMU1_PAREG_XPNP_SET(x)                                            (((x) << 28) & 0x10000000)
+#define PHY_ANALOG_PMU1_PAREG_LVLCTR_MSB                                                                     31
+#define PHY_ANALOG_PMU1_PAREG_LVLCTR_LSB                                                                     29
+#define PHY_ANALOG_PMU1_PAREG_LVLCTR_MASK                                                            0xe0000000
+#define PHY_ANALOG_PMU1_PAREG_LVLCTR_GET(x)                                          (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_PMU1_PAREG_LVLCTR_SET(x)                                          (((x) << 29) & 0xe0000000)
+
+/* macros for PMU2 */
+#define PHY_ANALOG_PMU2_ADDRESS                                                                      0x00000744
+#define PHY_ANALOG_PMU2_OFFSET                                                                       0x00000744
+#define PHY_ANALOG_PMU2_SPARE_MSB                                                                             7
+#define PHY_ANALOG_PMU2_SPARE_LSB                                                                             0
+#define PHY_ANALOG_PMU2_SPARE_MASK                                                                   0x000000ff
+#define PHY_ANALOG_PMU2_SPARE_GET(x)                                                  (((x) & 0x000000ff) >> 0)
+#define PHY_ANALOG_PMU2_SPARE_SET(x)                                                  (((x) << 0) & 0x000000ff)
+#define PHY_ANALOG_PMU2_VBATT_1_3TOATB_MSB                                                                    8
+#define PHY_ANALOG_PMU2_VBATT_1_3TOATB_LSB                                                                    8
+#define PHY_ANALOG_PMU2_VBATT_1_3TOATB_MASK                                                          0x00000100
+#define PHY_ANALOG_PMU2_VBATT_1_3TOATB_GET(x)                                         (((x) & 0x00000100) >> 8)
+#define PHY_ANALOG_PMU2_VBATT_1_3TOATB_SET(x)                                         (((x) << 8) & 0x00000100)
+#define PHY_ANALOG_PMU2_VBATT_1_2TOATB_MSB                                                                    9
+#define PHY_ANALOG_PMU2_VBATT_1_2TOATB_LSB                                                                    9
+#define PHY_ANALOG_PMU2_VBATT_1_2TOATB_MASK                                                          0x00000200
+#define PHY_ANALOG_PMU2_VBATT_1_2TOATB_GET(x)                                         (((x) & 0x00000200) >> 9)
+#define PHY_ANALOG_PMU2_VBATT_1_2TOATB_SET(x)                                         (((x) << 9) & 0x00000200)
+#define PHY_ANALOG_PMU2_VBATT_2_3TOATB_MSB                                                                   10
+#define PHY_ANALOG_PMU2_VBATT_2_3TOATB_LSB                                                                   10
+#define PHY_ANALOG_PMU2_VBATT_2_3TOATB_MASK                                                          0x00000400
+#define PHY_ANALOG_PMU2_VBATT_2_3TOATB_GET(x)                                        (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_PMU2_VBATT_2_3TOATB_SET(x)                                        (((x) << 10) & 0x00000400)
+#define PHY_ANALOG_PMU2_PWD_BANDGAP_MAN_MSB                                                                  11
+#define PHY_ANALOG_PMU2_PWD_BANDGAP_MAN_LSB                                                                  11
+#define PHY_ANALOG_PMU2_PWD_BANDGAP_MAN_MASK                                                         0x00000800
+#define PHY_ANALOG_PMU2_PWD_BANDGAP_MAN_GET(x)                                       (((x) & 0x00000800) >> 11)
+#define PHY_ANALOG_PMU2_PWD_BANDGAP_MAN_SET(x)                                       (((x) << 11) & 0x00000800)
+#define PHY_ANALOG_PMU2_PWD_LFO_MAN_MSB                                                                      12
+#define PHY_ANALOG_PMU2_PWD_LFO_MAN_LSB                                                                      12
+#define PHY_ANALOG_PMU2_PWD_LFO_MAN_MASK                                                             0x00001000
+#define PHY_ANALOG_PMU2_PWD_LFO_MAN_GET(x)                                           (((x) & 0x00001000) >> 12)
+#define PHY_ANALOG_PMU2_PWD_LFO_MAN_SET(x)                                           (((x) << 12) & 0x00001000)
+#define PHY_ANALOG_PMU2_VBATT_LT_3P2_MSB                                                                     13
+#define PHY_ANALOG_PMU2_VBATT_LT_3P2_LSB                                                                     13
+#define PHY_ANALOG_PMU2_VBATT_LT_3P2_MASK                                                            0x00002000
+#define PHY_ANALOG_PMU2_VBATT_LT_3P2_GET(x)                                          (((x) & 0x00002000) >> 13)
+#define PHY_ANALOG_PMU2_VBATT_LT_3P2_SET(x)                                          (((x) << 13) & 0x00002000)
+#define PHY_ANALOG_PMU2_VBATT_LT_2P8_MSB                                                                     14
+#define PHY_ANALOG_PMU2_VBATT_LT_2P8_LSB                                                                     14
+#define PHY_ANALOG_PMU2_VBATT_LT_2P8_MASK                                                            0x00004000
+#define PHY_ANALOG_PMU2_VBATT_LT_2P8_GET(x)                                          (((x) & 0x00004000) >> 14)
+#define PHY_ANALOG_PMU2_VBATT_LT_2P8_SET(x)                                          (((x) << 14) & 0x00004000)
+#define PHY_ANALOG_PMU2_VBATT_GT_4P2_MSB                                                                     15
+#define PHY_ANALOG_PMU2_VBATT_GT_4P2_LSB                                                                     15
+#define PHY_ANALOG_PMU2_VBATT_GT_4P2_MASK                                                            0x00008000
+#define PHY_ANALOG_PMU2_VBATT_GT_4P2_GET(x)                                          (((x) & 0x00008000) >> 15)
+#define PHY_ANALOG_PMU2_VBATT_GT_4P2_SET(x)                                          (((x) << 15) & 0x00008000)
+#define PHY_ANALOG_PMU2_PMU_MAN_OVERRIDE_EN_MSB                                                              16
+#define PHY_ANALOG_PMU2_PMU_MAN_OVERRIDE_EN_LSB                                                              16
+#define PHY_ANALOG_PMU2_PMU_MAN_OVERRIDE_EN_MASK                                                     0x00010000
+#define PHY_ANALOG_PMU2_PMU_MAN_OVERRIDE_EN_GET(x)                                   (((x) & 0x00010000) >> 16)
+#define PHY_ANALOG_PMU2_PMU_MAN_OVERRIDE_EN_SET(x)                                   (((x) << 16) & 0x00010000)
+#define PHY_ANALOG_PMU2_VBATT_GT_LVLCTR_MSB                                                                  18
+#define PHY_ANALOG_PMU2_VBATT_GT_LVLCTR_LSB                                                                  17
+#define PHY_ANALOG_PMU2_VBATT_GT_LVLCTR_MASK                                                         0x00060000
+#define PHY_ANALOG_PMU2_VBATT_GT_LVLCTR_GET(x)                                       (((x) & 0x00060000) >> 17)
+#define PHY_ANALOG_PMU2_VBATT_GT_LVLCTR_SET(x)                                       (((x) << 17) & 0x00060000)
+#define PHY_ANALOG_PMU2_SWREGVSSL2ATB_MSB                                                                    19
+#define PHY_ANALOG_PMU2_SWREGVSSL2ATB_LSB                                                                    19
+#define PHY_ANALOG_PMU2_SWREGVSSL2ATB_MASK                                                           0x00080000
+#define PHY_ANALOG_PMU2_SWREGVSSL2ATB_GET(x)                                         (((x) & 0x00080000) >> 19)
+#define PHY_ANALOG_PMU2_SWREGVSSL2ATB_SET(x)                                         (((x) << 19) & 0x00080000)
+#define PHY_ANALOG_PMU2_SWREGVSSL_LVLCTR_MSB                                                                 21
+#define PHY_ANALOG_PMU2_SWREGVSSL_LVLCTR_LSB                                                                 20
+#define PHY_ANALOG_PMU2_SWREGVSSL_LVLCTR_MASK                                                        0x00300000
+#define PHY_ANALOG_PMU2_SWREGVSSL_LVLCTR_GET(x)                                      (((x) & 0x00300000) >> 20)
+#define PHY_ANALOG_PMU2_SWREGVSSL_LVLCTR_SET(x)                                      (((x) << 20) & 0x00300000)
+#define PHY_ANALOG_PMU2_SWREGVDDH2ATB_MSB                                                                    22
+#define PHY_ANALOG_PMU2_SWREGVDDH2ATB_LSB                                                                    22
+#define PHY_ANALOG_PMU2_SWREGVDDH2ATB_MASK                                                           0x00400000
+#define PHY_ANALOG_PMU2_SWREGVDDH2ATB_GET(x)                                         (((x) & 0x00400000) >> 22)
+#define PHY_ANALOG_PMU2_SWREGVDDH2ATB_SET(x)                                         (((x) << 22) & 0x00400000)
+#define PHY_ANALOG_PMU2_SWREGVDDH_LVLCTR_MSB                                                                 24
+#define PHY_ANALOG_PMU2_SWREGVDDH_LVLCTR_LSB                                                                 23
+#define PHY_ANALOG_PMU2_SWREGVDDH_LVLCTR_MASK                                                        0x01800000
+#define PHY_ANALOG_PMU2_SWREGVDDH_LVLCTR_GET(x)                                      (((x) & 0x01800000) >> 23)
+#define PHY_ANALOG_PMU2_SWREGVDDH_LVLCTR_SET(x)                                      (((x) << 23) & 0x01800000)
+#define PHY_ANALOG_PMU2_SWREG2ATB_MSB                                                                        27
+#define PHY_ANALOG_PMU2_SWREG2ATB_LSB                                                                        25
+#define PHY_ANALOG_PMU2_SWREG2ATB_MASK                                                               0x0e000000
+#define PHY_ANALOG_PMU2_SWREG2ATB_GET(x)                                             (((x) & 0x0e000000) >> 25)
+#define PHY_ANALOG_PMU2_SWREG2ATB_SET(x)                                             (((x) << 25) & 0x0e000000)
+#define PHY_ANALOG_PMU2_OTPREG2ATB_MSB                                                                       28
+#define PHY_ANALOG_PMU2_OTPREG2ATB_LSB                                                                       28
+#define PHY_ANALOG_PMU2_OTPREG2ATB_MASK                                                              0x10000000
+#define PHY_ANALOG_PMU2_OTPREG2ATB_GET(x)                                            (((x) & 0x10000000) >> 28)
+#define PHY_ANALOG_PMU2_OTPREG2ATB_SET(x)                                            (((x) << 28) & 0x10000000)
+#define PHY_ANALOG_PMU2_OTPREG_LVLCTR_MSB                                                                    30
+#define PHY_ANALOG_PMU2_OTPREG_LVLCTR_LSB                                                                    29
+#define PHY_ANALOG_PMU2_OTPREG_LVLCTR_MASK                                                           0x60000000
+#define PHY_ANALOG_PMU2_OTPREG_LVLCTR_GET(x)                                         (((x) & 0x60000000) >> 29)
+#define PHY_ANALOG_PMU2_OTPREG_LVLCTR_SET(x)                                         (((x) << 29) & 0x60000000)
+#define PHY_ANALOG_PMU2_DREG_LVLCTR_MANOVR_EN_MSB                                                            31
+#define PHY_ANALOG_PMU2_DREG_LVLCTR_MANOVR_EN_LSB                                                            31
+#define PHY_ANALOG_PMU2_DREG_LVLCTR_MANOVR_EN_MASK                                                   0x80000000
+#define PHY_ANALOG_PMU2_DREG_LVLCTR_MANOVR_EN_GET(x)                                 (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_PMU2_DREG_LVLCTR_MANOVR_EN_SET(x)                                 (((x) << 31) & 0x80000000)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct analog_intf_ares_reg_reg_s {
+  volatile unsigned int RXRF_BIAS1;                                    /*        0x0 - 0x4        */
+  volatile unsigned int RXRF_BIAS2;                                    /*        0x4 - 0x8        */
+  volatile unsigned int RXRF_GAINSTAGES;                               /*        0x8 - 0xc        */
+  volatile unsigned int RXRF_AGC;                                      /*        0xc - 0x10       */
+  volatile char pad__0[0x30];                                          /*       0x10 - 0x40       */
+  volatile unsigned int TXRF1;                                         /*       0x40 - 0x44       */
+  volatile unsigned int TXRF2;                                         /*       0x44 - 0x48       */
+  volatile unsigned int TXRF3;                                         /*       0x48 - 0x4c       */
+  volatile unsigned int TXRF4;                                         /*       0x4c - 0x50       */
+  volatile unsigned int TXRF5;                                         /*       0x50 - 0x54       */
+  volatile unsigned int TXRF6;                                         /*       0x54 - 0x58       */
+  volatile unsigned int TXRF7;                                         /*       0x58 - 0x5c       */
+  volatile unsigned int TXRF8;                                         /*       0x5c - 0x60       */
+  volatile unsigned int TXRF9;                                         /*       0x60 - 0x64       */
+  volatile unsigned int TXRF10;                                        /*       0x64 - 0x68       */
+  volatile unsigned int TXRF11;                                        /*       0x68 - 0x6c       */
+  volatile unsigned int TXRF12;                                        /*       0x6c - 0x70       */
+  volatile char pad__1[0x10];                                          /*       0x70 - 0x80       */
+  volatile unsigned int SYNTH1;                                        /*       0x80 - 0x84       */
+  volatile unsigned int SYNTH2;                                        /*       0x84 - 0x88       */
+  volatile unsigned int SYNTH3;                                        /*       0x88 - 0x8c       */
+  volatile unsigned int SYNTH4;                                        /*       0x8c - 0x90       */
+  volatile unsigned int SYNTH5;                                        /*       0x90 - 0x94       */
+  volatile unsigned int SYNTH6;                                        /*       0x94 - 0x98       */
+  volatile unsigned int SYNTH7;                                        /*       0x98 - 0x9c       */
+  volatile unsigned int SYNTH8;                                        /*       0x9c - 0xa0       */
+  volatile unsigned int SYNTH9;                                        /*       0xa0 - 0xa4       */
+  volatile unsigned int SYNTH10;                                       /*       0xa4 - 0xa8       */
+  volatile unsigned int SYNTH11;                                       /*       0xa8 - 0xac       */
+  volatile unsigned int SYNTH12;                                       /*       0xac - 0xb0       */
+  volatile char pad__2[0x10];                                          /*       0xb0 - 0xc0       */
+  volatile unsigned int BIAS1;                                         /*       0xc0 - 0xc4       */
+  volatile unsigned int BIAS2;                                         /*       0xc4 - 0xc8       */
+  volatile unsigned int BIAS3;                                         /*       0xc8 - 0xcc       */
+  volatile unsigned int BIAS4;                                         /*       0xcc - 0xd0       */
+  volatile char pad__3[0x30];                                          /*       0xd0 - 0x100      */
+  volatile unsigned int RXTX1;                                         /*      0x100 - 0x104      */
+  volatile unsigned int RXTX2;                                         /*      0x104 - 0x108      */
+  volatile unsigned int RXTX3;                                         /*      0x108 - 0x10c      */
+  volatile char pad__4[0x34];                                          /*      0x10c - 0x140      */
+  volatile unsigned int BB1;                                           /*      0x140 - 0x144      */
+  volatile unsigned int BB2;                                           /*      0x144 - 0x148      */
+  volatile char pad__5[0x138];                                         /*      0x148 - 0x280      */
+  volatile unsigned int TOP1;                                          /*      0x280 - 0x284      */
+  volatile unsigned int TOP2;                                          /*      0x284 - 0x288      */
+  volatile unsigned int TOP3;                                          /*      0x288 - 0x28c      */
+  volatile unsigned int TOP4;                                          /*      0x28c - 0x290      */
+  volatile char pad__6[0xf0];                                          /*      0x290 - 0x380      */
+  volatile unsigned int rbist_cntrl;                                   /*      0x380 - 0x384      */
+  volatile unsigned int tx_dc_offset;                                  /*      0x384 - 0x388      */
+  volatile unsigned int tx_tonegen0;                                   /*      0x388 - 0x38c      */
+  volatile unsigned int tx_tonegen1;                                   /*      0x38c - 0x390      */
+  volatile unsigned int tx_lftonegen0;                                 /*      0x390 - 0x394      */
+  volatile unsigned int tx_linear_ramp_i;                              /*      0x394 - 0x398      */
+  volatile unsigned int tx_linear_ramp_q;                              /*      0x398 - 0x39c      */
+  volatile unsigned int tx_prbs_mag;                                   /*      0x39c - 0x3a0      */
+  volatile unsigned int tx_prbs_seed_i;                                /*      0x3a0 - 0x3a4      */
+  volatile unsigned int tx_prbs_seed_q;                                /*      0x3a4 - 0x3a8      */
+  volatile unsigned int cmac_dc_cancel;                                /*      0x3a8 - 0x3ac      */
+  volatile unsigned int cmac_dc_offset;                                /*      0x3ac - 0x3b0      */
+  volatile unsigned int cmac_corr;                                     /*      0x3b0 - 0x3b4      */
+  volatile unsigned int cmac_power;                                    /*      0x3b4 - 0x3b8      */
+  volatile unsigned int cmac_cross_corr;                               /*      0x3b8 - 0x3bc      */
+  volatile unsigned int cmac_i2q2;                                     /*      0x3bc - 0x3c0      */
+  volatile unsigned int cmac_power_hpf;                                /*      0x3c0 - 0x3c4      */
+  volatile unsigned int rxdac_set1;                                    /*      0x3c4 - 0x3c8      */
+  volatile unsigned int rxdac_set2;                                    /*      0x3c8 - 0x3cc      */
+  volatile unsigned int rxdac_long_shift;                              /*      0x3cc - 0x3d0      */
+  volatile unsigned int cmac_results_i;                                /*      0x3d0 - 0x3d4      */
+  volatile unsigned int cmac_results_q;                                /*      0x3d4 - 0x3d8      */
+  volatile char pad__7[0x368];                                         /*      0x3d8 - 0x740      */
+  volatile unsigned int PMU1;                                          /*      0x740 - 0x744      */
+  volatile unsigned int PMU2;                                          /*      0x744 - 0x748      */
+} analog_intf_ares_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _ANALOG_INTF_ARES_REG_REG_H_ */
diff --git a/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/analog_intf_athr_wlan_reg.h b/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/analog_intf_athr_wlan_reg.h
new file mode 100644
index 00000000000..1c243fbbc81
--- /dev/null
+++ b/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/analog_intf_athr_wlan_reg.h
@@ -0,0 +1,3674 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+/* Copyright (C) 2009 Denali Software Inc.  All rights reserved              */
+/* THIS FILE IS AUTOMATICALLY GENERATED BY DENALI BLUEPRINT, DO NOT EDIT     */
+
+
+#ifndef _ANALOG_INTF_ATHR_WLAN_REG_REG_H_
+#define _ANALOG_INTF_ATHR_WLAN_REG_REG_H_
+
+
+/* macros for RXRF_BIAS1 */
+#define PHY_ANALOG_RXRF_BIAS1_ADDRESS                                                                0x00000000
+#define PHY_ANALOG_RXRF_BIAS1_OFFSET                                                                 0x00000000
+#define PHY_ANALOG_RXRF_BIAS1_SPARE_MSB                                                                       0
+#define PHY_ANALOG_RXRF_BIAS1_SPARE_LSB                                                                       0
+#define PHY_ANALOG_RXRF_BIAS1_SPARE_MASK                                                             0x00000001
+#define PHY_ANALOG_RXRF_BIAS1_SPARE_GET(x)                                            (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_RXRF_BIAS1_SPARE_SET(x)                                            (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25SPARE_MSB                                                               3
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25SPARE_LSB                                                               1
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25SPARE_MASK                                                     0x0000000e
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25SPARE_GET(x)                                    (((x) & 0x0000000e) >> 1)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25SPARE_SET(x)                                    (((x) << 1) & 0x0000000e)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO18_MSB                                                                6
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO18_LSB                                                                4
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO18_MASK                                                      0x00000070
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO18_GET(x)                                     (((x) & 0x00000070) >> 4)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO18_SET(x)                                     (((x) << 4) & 0x00000070)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25LO36_MSB                                                                9
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25LO36_LSB                                                                7
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25LO36_MASK                                                      0x00000380
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25LO36_GET(x)                                     (((x) & 0x00000380) >> 7)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25LO36_SET(x)                                     (((x) << 7) & 0x00000380)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2_5GH_MSB                                                           12
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2_5GH_LSB                                                           10
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2_5GH_MASK                                                  0x00001c00
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2_5GH_GET(x)                                (((x) & 0x00001c00) >> 10)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2_5GH_SET(x)                                (((x) << 10) & 0x00001c00)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR5GH_MSB                                                             15
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR5GH_LSB                                                             13
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR5GH_MASK                                                    0x0000e000
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR5GH_GET(x)                                  (((x) & 0x0000e000) >> 13)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR5GH_SET(x)                                  (((x) << 13) & 0x0000e000)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25VGA5G_MSB                                                              18
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25VGA5G_LSB                                                              16
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25VGA5G_MASK                                                     0x00070000
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25VGA5G_GET(x)                                   (((x) & 0x00070000) >> 16)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25VGA5G_SET(x)                                   (((x) << 16) & 0x00070000)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA5G_MSB                                                              21
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA5G_LSB                                                              19
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA5G_MASK                                                     0x00380000
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA5G_GET(x)                                   (((x) & 0x00380000) >> 19)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA5G_SET(x)                                   (((x) << 19) & 0x00380000)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO24_MSB                                                               24
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO24_LSB                                                               22
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO24_MASK                                                      0x01c00000
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO24_GET(x)                                    (((x) & 0x01c00000) >> 22)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO24_SET(x)                                    (((x) << 22) & 0x01c00000)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2GH_MSB                                                             27
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2GH_LSB                                                             25
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2GH_MASK                                                    0x0e000000
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2GH_GET(x)                                  (((x) & 0x0e000000) >> 25)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2GH_SET(x)                                  (((x) << 25) & 0x0e000000)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA2G_MSB                                                              30
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA2G_LSB                                                              28
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA2G_MASK                                                     0x70000000
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA2G_GET(x)                                   (((x) & 0x70000000) >> 28)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA2G_SET(x)                                   (((x) << 28) & 0x70000000)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_BIAS_MSB                                                                   31
+#define PHY_ANALOG_RXRF_BIAS1_PWD_BIAS_LSB                                                                   31
+#define PHY_ANALOG_RXRF_BIAS1_PWD_BIAS_MASK                                                          0x80000000
+#define PHY_ANALOG_RXRF_BIAS1_PWD_BIAS_GET(x)                                        (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_BIAS_SET(x)                                        (((x) << 31) & 0x80000000)
+
+/* macros for RXRF_BIAS2 */
+#define PHY_ANALOG_RXRF_BIAS2_ADDRESS                                                                0x00000004
+#define PHY_ANALOG_RXRF_BIAS2_OFFSET                                                                 0x00000004
+#define PHY_ANALOG_RXRF_BIAS2_SPARE_MSB                                                                       0
+#define PHY_ANALOG_RXRF_BIAS2_SPARE_LSB                                                                       0
+#define PHY_ANALOG_RXRF_BIAS2_SPARE_MASK                                                             0x00000001
+#define PHY_ANALOG_RXRF_BIAS2_SPARE_GET(x)                                            (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_RXRF_BIAS2_SPARE_SET(x)                                            (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_RXRF_BIAS2_PKEN_MSB                                                                        3
+#define PHY_ANALOG_RXRF_BIAS2_PKEN_LSB                                                                        1
+#define PHY_ANALOG_RXRF_BIAS2_PKEN_MASK                                                              0x0000000e
+#define PHY_ANALOG_RXRF_BIAS2_PKEN_GET(x)                                             (((x) & 0x0000000e) >> 1)
+#define PHY_ANALOG_RXRF_BIAS2_PKEN_SET(x)                                             (((x) << 1) & 0x0000000e)
+#define PHY_ANALOG_RXRF_BIAS2_VCMVALUE_MSB                                                                    6
+#define PHY_ANALOG_RXRF_BIAS2_VCMVALUE_LSB                                                                    4
+#define PHY_ANALOG_RXRF_BIAS2_VCMVALUE_MASK                                                          0x00000070
+#define PHY_ANALOG_RXRF_BIAS2_VCMVALUE_GET(x)                                         (((x) & 0x00000070) >> 4)
+#define PHY_ANALOG_RXRF_BIAS2_VCMVALUE_SET(x)                                         (((x) << 4) & 0x00000070)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_VCMBUF_MSB                                                                  7
+#define PHY_ANALOG_RXRF_BIAS2_PWD_VCMBUF_LSB                                                                  7
+#define PHY_ANALOG_RXRF_BIAS2_PWD_VCMBUF_MASK                                                        0x00000080
+#define PHY_ANALOG_RXRF_BIAS2_PWD_VCMBUF_GET(x)                                       (((x) & 0x00000080) >> 7)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_VCMBUF_SET(x)                                       (((x) << 7) & 0x00000080)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25SPAREH_MSB                                                             10
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25SPAREH_LSB                                                              8
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25SPAREH_MASK                                                    0x00000700
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25SPAREH_GET(x)                                   (((x) & 0x00000700) >> 8)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25SPAREH_SET(x)                                   (((x) << 8) & 0x00000700)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25SPARE_MSB                                                              13
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25SPARE_LSB                                                              11
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25SPARE_MASK                                                     0x00003800
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25SPARE_GET(x)                                   (((x) & 0x00003800) >> 11)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25SPARE_SET(x)                                   (((x) << 11) & 0x00003800)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25LNABUF_MSB                                                             16
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25LNABUF_LSB                                                             14
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25LNABUF_MASK                                                    0x0001c000
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25LNABUF_GET(x)                                  (((x) & 0x0001c000) >> 14)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25LNABUF_SET(x)                                  (((x) << 14) & 0x0001c000)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGCH_MSB                                                               19
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGCH_LSB                                                               17
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGCH_MASK                                                      0x000e0000
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGCH_GET(x)                                    (((x) & 0x000e0000) >> 17)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGCH_SET(x)                                    (((x) << 17) & 0x000e0000)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC_MSB                                                                22
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC_LSB                                                                20
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC_MASK                                                       0x00700000
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC_GET(x)                                     (((x) & 0x00700000) >> 20)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC_SET(x)                                     (((x) << 20) & 0x00700000)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC_MSB                                                                25
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC_LSB                                                                23
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC_MASK                                                       0x03800000
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC_GET(x)                                     (((x) & 0x03800000) >> 23)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC_SET(x)                                     (((x) << 23) & 0x03800000)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25VCMBUF_MSB                                                             28
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25VCMBUF_LSB                                                             26
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25VCMBUF_MASK                                                    0x1c000000
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25VCMBUF_GET(x)                                  (((x) & 0x1c000000) >> 26)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25VCMBUF_SET(x)                                  (((x) << 26) & 0x1c000000)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25VCM_MSB                                                                31
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25VCM_LSB                                                                29
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25VCM_MASK                                                       0xe0000000
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25VCM_GET(x)                                     (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25VCM_SET(x)                                     (((x) << 29) & 0xe0000000)
+
+/* macros for RXRF_GAINSTAGES */
+#define PHY_ANALOG_RXRF_GAINSTAGES_ADDRESS                                                           0x00000008
+#define PHY_ANALOG_RXRF_GAINSTAGES_OFFSET                                                            0x00000008
+#define PHY_ANALOG_RXRF_GAINSTAGES_SPARE_MSB                                                                  0
+#define PHY_ANALOG_RXRF_GAINSTAGES_SPARE_LSB                                                                  0
+#define PHY_ANALOG_RXRF_GAINSTAGES_SPARE_MASK                                                        0x00000001
+#define PHY_ANALOG_RXRF_GAINSTAGES_SPARE_GET(x)                                       (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_RXRF_GAINSTAGES_SPARE_SET(x)                                       (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNAON_CALDC_MSB                                                            1
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNAON_CALDC_LSB                                                            1
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNAON_CALDC_MASK                                                  0x00000002
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNAON_CALDC_GET(x)                                 (((x) & 0x00000002) >> 1)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNAON_CALDC_SET(x)                                 (((x) << 1) & 0x00000002)
+#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_CAP_MSB                                                              3
+#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_CAP_LSB                                                              2
+#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_CAP_MASK                                                    0x0000000c
+#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_CAP_GET(x)                                   (((x) & 0x0000000c) >> 2)
+#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_CAP_SET(x)                                   (((x) << 2) & 0x0000000c)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_CAP_MSB                                                              5
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_CAP_LSB                                                              4
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_CAP_MASK                                                    0x00000030
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_CAP_GET(x)                                   (((x) & 0x00000030) >> 4)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_CAP_SET(x)                                   (((x) << 4) & 0x00000030)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_SHORTINP_MSB                                                         6
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_SHORTINP_LSB                                                         6
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_SHORTINP_MASK                                               0x00000040
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_SHORTINP_GET(x)                              (((x) & 0x00000040) >> 6)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_SHORTINP_SET(x)                              (((x) << 6) & 0x00000040)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO5G_MSB                                                               7
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO5G_LSB                                                               7
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO5G_MASK                                                     0x00000080
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO5G_GET(x)                                    (((x) & 0x00000080) >> 7)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO5G_SET(x)                                    (((x) << 7) & 0x00000080)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_VGA5G_MSB                                                              8
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_VGA5G_LSB                                                              8
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_VGA5G_MASK                                                    0x00000100
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_VGA5G_GET(x)                                   (((x) & 0x00000100) >> 8)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_VGA5G_SET(x)                                   (((x) << 8) & 0x00000100)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR5G_MSB                                                              9
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR5G_LSB                                                              9
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR5G_MASK                                                    0x00000200
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR5G_GET(x)                                   (((x) & 0x00000200) >> 9)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR5G_SET(x)                                   (((x) << 9) & 0x00000200)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA5G_MSB                                                             10
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA5G_LSB                                                             10
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA5G_MASK                                                    0x00000400
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA5G_GET(x)                                  (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA5G_SET(x)                                  (((x) << 10) & 0x00000400)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_CAP_MSB                                                             12
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_CAP_LSB                                                             11
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_CAP_MASK                                                    0x00001800
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_CAP_GET(x)                                  (((x) & 0x00001800) >> 11)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_CAP_SET(x)                                  (((x) << 11) & 0x00001800)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_SHORTINP_MSB                                                        13
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_SHORTINP_LSB                                                        13
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_SHORTINP_MASK                                               0x00002000
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_SHORTINP_GET(x)                             (((x) & 0x00002000) >> 13)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_SHORTINP_SET(x)                             (((x) << 13) & 0x00002000)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_LP_MSB                                                              14
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_LP_LSB                                                              14
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_LP_MASK                                                     0x00004000
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_LP_GET(x)                                   (((x) & 0x00004000) >> 14)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_LP_SET(x)                                   (((x) << 14) & 0x00004000)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO2G_MSB                                                              15
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO2G_LSB                                                              15
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO2G_MASK                                                     0x00008000
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO2G_GET(x)                                   (((x) & 0x00008000) >> 15)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO2G_SET(x)                                   (((x) << 15) & 0x00008000)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR2G_MSB                                                             16
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR2G_LSB                                                             16
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR2G_MASK                                                    0x00010000
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR2G_GET(x)                                  (((x) & 0x00010000) >> 16)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR2G_SET(x)                                  (((x) << 16) & 0x00010000)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA2G_MSB                                                             17
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA2G_LSB                                                             17
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA2G_MASK                                                    0x00020000
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA2G_GET(x)                                  (((x) & 0x00020000) >> 17)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA2G_SET(x)                                  (((x) << 17) & 0x00020000)
+#define PHY_ANALOG_RXRF_GAINSTAGES_MXR5G_GAIN_OVR_MSB                                                        19
+#define PHY_ANALOG_RXRF_GAINSTAGES_MXR5G_GAIN_OVR_LSB                                                        18
+#define PHY_ANALOG_RXRF_GAINSTAGES_MXR5G_GAIN_OVR_MASK                                               0x000c0000
+#define PHY_ANALOG_RXRF_GAINSTAGES_MXR5G_GAIN_OVR_GET(x)                             (((x) & 0x000c0000) >> 18)
+#define PHY_ANALOG_RXRF_GAINSTAGES_MXR5G_GAIN_OVR_SET(x)                             (((x) << 18) & 0x000c0000)
+#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_GAIN_OVR_MSB                                                        22
+#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_GAIN_OVR_LSB                                                        20
+#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_GAIN_OVR_MASK                                               0x00700000
+#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_GAIN_OVR_GET(x)                             (((x) & 0x00700000) >> 20)
+#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_GAIN_OVR_SET(x)                             (((x) << 20) & 0x00700000)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_MSB                                                        25
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_LSB                                                        23
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_MASK                                               0x03800000
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_GET(x)                             (((x) & 0x03800000) >> 23)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_SET(x)                             (((x) << 23) & 0x03800000)
+#define PHY_ANALOG_RXRF_GAINSTAGES_MXR2G_GAIN_OVR_MSB                                                        27
+#define PHY_ANALOG_RXRF_GAINSTAGES_MXR2G_GAIN_OVR_LSB                                                        26
+#define PHY_ANALOG_RXRF_GAINSTAGES_MXR2G_GAIN_OVR_MASK                                               0x0c000000
+#define PHY_ANALOG_RXRF_GAINSTAGES_MXR2G_GAIN_OVR_GET(x)                             (((x) & 0x0c000000) >> 26)
+#define PHY_ANALOG_RXRF_GAINSTAGES_MXR2G_GAIN_OVR_SET(x)                             (((x) << 26) & 0x0c000000)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_MSB                                                        30
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_LSB                                                        28
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_MASK                                               0x70000000
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_GET(x)                             (((x) & 0x70000000) >> 28)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_SET(x)                             (((x) << 28) & 0x70000000)
+#define PHY_ANALOG_RXRF_GAINSTAGES_RX_OVERRIDE_MSB                                                           31
+#define PHY_ANALOG_RXRF_GAINSTAGES_RX_OVERRIDE_LSB                                                           31
+#define PHY_ANALOG_RXRF_GAINSTAGES_RX_OVERRIDE_MASK                                                  0x80000000
+#define PHY_ANALOG_RXRF_GAINSTAGES_RX_OVERRIDE_GET(x)                                (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_RXRF_GAINSTAGES_RX_OVERRIDE_SET(x)                                (((x) << 31) & 0x80000000)
+
+/* macros for RXRF_AGC */
+#define PHY_ANALOG_RXRF_AGC_ADDRESS                                                                  0x0000000c
+#define PHY_ANALOG_RXRF_AGC_OFFSET                                                                   0x0000000c
+#define PHY_ANALOG_RXRF_AGC_RF5G_ON_DURING_CALPA_MSB                                                          0
+#define PHY_ANALOG_RXRF_AGC_RF5G_ON_DURING_CALPA_LSB                                                          0
+#define PHY_ANALOG_RXRF_AGC_RF5G_ON_DURING_CALPA_MASK                                                0x00000001
+#define PHY_ANALOG_RXRF_AGC_RF5G_ON_DURING_CALPA_GET(x)                               (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_RXRF_AGC_RF5G_ON_DURING_CALPA_SET(x)                               (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_RXRF_AGC_RF2G_ON_DURING_CALPA_MSB                                                          1
+#define PHY_ANALOG_RXRF_AGC_RF2G_ON_DURING_CALPA_LSB                                                          1
+#define PHY_ANALOG_RXRF_AGC_RF2G_ON_DURING_CALPA_MASK                                                0x00000002
+#define PHY_ANALOG_RXRF_AGC_RF2G_ON_DURING_CALPA_GET(x)                               (((x) & 0x00000002) >> 1)
+#define PHY_ANALOG_RXRF_AGC_RF2G_ON_DURING_CALPA_SET(x)                               (((x) << 1) & 0x00000002)
+#define PHY_ANALOG_RXRF_AGC_AGC_OUT_MSB                                                                       2
+#define PHY_ANALOG_RXRF_AGC_AGC_OUT_LSB                                                                       2
+#define PHY_ANALOG_RXRF_AGC_AGC_OUT_MASK                                                             0x00000004
+#define PHY_ANALOG_RXRF_AGC_AGC_OUT_GET(x)                                            (((x) & 0x00000004) >> 2)
+#define PHY_ANALOG_RXRF_AGC_LNABUFGAIN2X_MSB                                                                  3
+#define PHY_ANALOG_RXRF_AGC_LNABUFGAIN2X_LSB                                                                  3
+#define PHY_ANALOG_RXRF_AGC_LNABUFGAIN2X_MASK                                                        0x00000008
+#define PHY_ANALOG_RXRF_AGC_LNABUFGAIN2X_GET(x)                                       (((x) & 0x00000008) >> 3)
+#define PHY_ANALOG_RXRF_AGC_LNABUFGAIN2X_SET(x)                                       (((x) << 3) & 0x00000008)
+#define PHY_ANALOG_RXRF_AGC_LNABUF_PWD_OVR_MSB                                                                4
+#define PHY_ANALOG_RXRF_AGC_LNABUF_PWD_OVR_LSB                                                                4
+#define PHY_ANALOG_RXRF_AGC_LNABUF_PWD_OVR_MASK                                                      0x00000010
+#define PHY_ANALOG_RXRF_AGC_LNABUF_PWD_OVR_GET(x)                                     (((x) & 0x00000010) >> 4)
+#define PHY_ANALOG_RXRF_AGC_LNABUF_PWD_OVR_SET(x)                                     (((x) << 4) & 0x00000010)
+#define PHY_ANALOG_RXRF_AGC_PWD_LNABUF_MSB                                                                    5
+#define PHY_ANALOG_RXRF_AGC_PWD_LNABUF_LSB                                                                    5
+#define PHY_ANALOG_RXRF_AGC_PWD_LNABUF_MASK                                                          0x00000020
+#define PHY_ANALOG_RXRF_AGC_PWD_LNABUF_GET(x)                                         (((x) & 0x00000020) >> 5)
+#define PHY_ANALOG_RXRF_AGC_PWD_LNABUF_SET(x)                                         (((x) << 5) & 0x00000020)
+#define PHY_ANALOG_RXRF_AGC_AGC_FALL_CTRL_MSB                                                                 8
+#define PHY_ANALOG_RXRF_AGC_AGC_FALL_CTRL_LSB                                                                 6
+#define PHY_ANALOG_RXRF_AGC_AGC_FALL_CTRL_MASK                                                       0x000001c0
+#define PHY_ANALOG_RXRF_AGC_AGC_FALL_CTRL_GET(x)                                      (((x) & 0x000001c0) >> 6)
+#define PHY_ANALOG_RXRF_AGC_AGC_FALL_CTRL_SET(x)                                      (((x) << 6) & 0x000001c0)
+#define PHY_ANALOG_RXRF_AGC_AGC5G_CALDAC_OVR_MSB                                                             14
+#define PHY_ANALOG_RXRF_AGC_AGC5G_CALDAC_OVR_LSB                                                              9
+#define PHY_ANALOG_RXRF_AGC_AGC5G_CALDAC_OVR_MASK                                                    0x00007e00
+#define PHY_ANALOG_RXRF_AGC_AGC5G_CALDAC_OVR_GET(x)                                   (((x) & 0x00007e00) >> 9)
+#define PHY_ANALOG_RXRF_AGC_AGC5G_CALDAC_OVR_SET(x)                                   (((x) << 9) & 0x00007e00)
+#define PHY_ANALOG_RXRF_AGC_AGC5G_DBDAC_OVR_MSB                                                              18
+#define PHY_ANALOG_RXRF_AGC_AGC5G_DBDAC_OVR_LSB                                                              15
+#define PHY_ANALOG_RXRF_AGC_AGC5G_DBDAC_OVR_MASK                                                     0x00078000
+#define PHY_ANALOG_RXRF_AGC_AGC5G_DBDAC_OVR_GET(x)                                   (((x) & 0x00078000) >> 15)
+#define PHY_ANALOG_RXRF_AGC_AGC5G_DBDAC_OVR_SET(x)                                   (((x) << 15) & 0x00078000)
+#define PHY_ANALOG_RXRF_AGC_AGC2G_CALDAC_OVR_MSB                                                             24
+#define PHY_ANALOG_RXRF_AGC_AGC2G_CALDAC_OVR_LSB                                                             19
+#define PHY_ANALOG_RXRF_AGC_AGC2G_CALDAC_OVR_MASK                                                    0x01f80000
+#define PHY_ANALOG_RXRF_AGC_AGC2G_CALDAC_OVR_GET(x)                                  (((x) & 0x01f80000) >> 19)
+#define PHY_ANALOG_RXRF_AGC_AGC2G_CALDAC_OVR_SET(x)                                  (((x) << 19) & 0x01f80000)
+#define PHY_ANALOG_RXRF_AGC_AGC2G_DBDAC_OVR_MSB                                                              28
+#define PHY_ANALOG_RXRF_AGC_AGC2G_DBDAC_OVR_LSB                                                              25
+#define PHY_ANALOG_RXRF_AGC_AGC2G_DBDAC_OVR_MASK                                                     0x1e000000
+#define PHY_ANALOG_RXRF_AGC_AGC2G_DBDAC_OVR_GET(x)                                   (((x) & 0x1e000000) >> 25)
+#define PHY_ANALOG_RXRF_AGC_AGC2G_DBDAC_OVR_SET(x)                                   (((x) << 25) & 0x1e000000)
+#define PHY_ANALOG_RXRF_AGC_AGC_CAL_OVR_MSB                                                                  29
+#define PHY_ANALOG_RXRF_AGC_AGC_CAL_OVR_LSB                                                                  29
+#define PHY_ANALOG_RXRF_AGC_AGC_CAL_OVR_MASK                                                         0x20000000
+#define PHY_ANALOG_RXRF_AGC_AGC_CAL_OVR_GET(x)                                       (((x) & 0x20000000) >> 29)
+#define PHY_ANALOG_RXRF_AGC_AGC_CAL_OVR_SET(x)                                       (((x) << 29) & 0x20000000)
+#define PHY_ANALOG_RXRF_AGC_AGC_ON_OVR_MSB                                                                   30
+#define PHY_ANALOG_RXRF_AGC_AGC_ON_OVR_LSB                                                                   30
+#define PHY_ANALOG_RXRF_AGC_AGC_ON_OVR_MASK                                                          0x40000000
+#define PHY_ANALOG_RXRF_AGC_AGC_ON_OVR_GET(x)                                        (((x) & 0x40000000) >> 30)
+#define PHY_ANALOG_RXRF_AGC_AGC_ON_OVR_SET(x)                                        (((x) << 30) & 0x40000000)
+#define PHY_ANALOG_RXRF_AGC_AGC_OVERRIDE_MSB                                                                 31
+#define PHY_ANALOG_RXRF_AGC_AGC_OVERRIDE_LSB                                                                 31
+#define PHY_ANALOG_RXRF_AGC_AGC_OVERRIDE_MASK                                                        0x80000000
+#define PHY_ANALOG_RXRF_AGC_AGC_OVERRIDE_GET(x)                                      (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_RXRF_AGC_AGC_OVERRIDE_SET(x)                                      (((x) << 31) & 0x80000000)
+
+/* macros for TXRF1 */
+#define PHY_ANALOG_TXRF1_ADDRESS                                                                     0x00000040
+#define PHY_ANALOG_TXRF1_OFFSET                                                                      0x00000040
+#define PHY_ANALOG_TXRF1_PDLOBUF5G_MSB                                                                        0
+#define PHY_ANALOG_TXRF1_PDLOBUF5G_LSB                                                                        0
+#define PHY_ANALOG_TXRF1_PDLOBUF5G_MASK                                                              0x00000001
+#define PHY_ANALOG_TXRF1_PDLOBUF5G_GET(x)                                             (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_TXRF1_PDLOBUF5G_SET(x)                                             (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_TXRF1_PDLODIV5G_MSB                                                                        1
+#define PHY_ANALOG_TXRF1_PDLODIV5G_LSB                                                                        1
+#define PHY_ANALOG_TXRF1_PDLODIV5G_MASK                                                              0x00000002
+#define PHY_ANALOG_TXRF1_PDLODIV5G_GET(x)                                             (((x) & 0x00000002) >> 1)
+#define PHY_ANALOG_TXRF1_PDLODIV5G_SET(x)                                             (((x) << 1) & 0x00000002)
+#define PHY_ANALOG_TXRF1_LOBUF5GFORCED_MSB                                                                    2
+#define PHY_ANALOG_TXRF1_LOBUF5GFORCED_LSB                                                                    2
+#define PHY_ANALOG_TXRF1_LOBUF5GFORCED_MASK                                                          0x00000004
+#define PHY_ANALOG_TXRF1_LOBUF5GFORCED_GET(x)                                         (((x) & 0x00000004) >> 2)
+#define PHY_ANALOG_TXRF1_LOBUF5GFORCED_SET(x)                                         (((x) << 2) & 0x00000004)
+#define PHY_ANALOG_TXRF1_LODIV5GFORCED_MSB                                                                    3
+#define PHY_ANALOG_TXRF1_LODIV5GFORCED_LSB                                                                    3
+#define PHY_ANALOG_TXRF1_LODIV5GFORCED_MASK                                                          0x00000008
+#define PHY_ANALOG_TXRF1_LODIV5GFORCED_GET(x)                                         (((x) & 0x00000008) >> 3)
+#define PHY_ANALOG_TXRF1_LODIV5GFORCED_SET(x)                                         (((x) << 3) & 0x00000008)
+#define PHY_ANALOG_TXRF1_PADRV2GN5G_MSB                                                                       7
+#define PHY_ANALOG_TXRF1_PADRV2GN5G_LSB                                                                       4
+#define PHY_ANALOG_TXRF1_PADRV2GN5G_MASK                                                             0x000000f0
+#define PHY_ANALOG_TXRF1_PADRV2GN5G_GET(x)                                            (((x) & 0x000000f0) >> 4)
+#define PHY_ANALOG_TXRF1_PADRV2GN5G_SET(x)                                            (((x) << 4) & 0x000000f0)
+#define PHY_ANALOG_TXRF1_PADRV3GN5G_MSB                                                                      11
+#define PHY_ANALOG_TXRF1_PADRV3GN5G_LSB                                                                       8
+#define PHY_ANALOG_TXRF1_PADRV3GN5G_MASK                                                             0x00000f00
+#define PHY_ANALOG_TXRF1_PADRV3GN5G_GET(x)                                            (((x) & 0x00000f00) >> 8)
+#define PHY_ANALOG_TXRF1_PADRV3GN5G_SET(x)                                            (((x) << 8) & 0x00000f00)
+#define PHY_ANALOG_TXRF1_PADRV4GN5G_MSB                                                                      15
+#define PHY_ANALOG_TXRF1_PADRV4GN5G_LSB                                                                      12
+#define PHY_ANALOG_TXRF1_PADRV4GN5G_MASK                                                             0x0000f000
+#define PHY_ANALOG_TXRF1_PADRV4GN5G_GET(x)                                           (((x) & 0x0000f000) >> 12)
+#define PHY_ANALOG_TXRF1_PADRV4GN5G_SET(x)                                           (((x) << 12) & 0x0000f000)
+#define PHY_ANALOG_TXRF1_LOCALTXGAIN5G_MSB                                                                   16
+#define PHY_ANALOG_TXRF1_LOCALTXGAIN5G_LSB                                                                   16
+#define PHY_ANALOG_TXRF1_LOCALTXGAIN5G_MASK                                                          0x00010000
+#define PHY_ANALOG_TXRF1_LOCALTXGAIN5G_GET(x)                                        (((x) & 0x00010000) >> 16)
+#define PHY_ANALOG_TXRF1_LOCALTXGAIN5G_SET(x)                                        (((x) << 16) & 0x00010000)
+#define PHY_ANALOG_TXRF1_PDOUT2G_MSB                                                                         17
+#define PHY_ANALOG_TXRF1_PDOUT2G_LSB                                                                         17
+#define PHY_ANALOG_TXRF1_PDOUT2G_MASK                                                                0x00020000
+#define PHY_ANALOG_TXRF1_PDOUT2G_GET(x)                                              (((x) & 0x00020000) >> 17)
+#define PHY_ANALOG_TXRF1_PDOUT2G_SET(x)                                              (((x) << 17) & 0x00020000)
+#define PHY_ANALOG_TXRF1_PDDR2G_MSB                                                                          18
+#define PHY_ANALOG_TXRF1_PDDR2G_LSB                                                                          18
+#define PHY_ANALOG_TXRF1_PDDR2G_MASK                                                                 0x00040000
+#define PHY_ANALOG_TXRF1_PDDR2G_GET(x)                                               (((x) & 0x00040000) >> 18)
+#define PHY_ANALOG_TXRF1_PDDR2G_SET(x)                                               (((x) << 18) & 0x00040000)
+#define PHY_ANALOG_TXRF1_PDMXR2G_MSB                                                                         19
+#define PHY_ANALOG_TXRF1_PDMXR2G_LSB                                                                         19
+#define PHY_ANALOG_TXRF1_PDMXR2G_MASK                                                                0x00080000
+#define PHY_ANALOG_TXRF1_PDMXR2G_GET(x)                                              (((x) & 0x00080000) >> 19)
+#define PHY_ANALOG_TXRF1_PDMXR2G_SET(x)                                              (((x) << 19) & 0x00080000)
+#define PHY_ANALOG_TXRF1_PDLOBUF2G_MSB                                                                       20
+#define PHY_ANALOG_TXRF1_PDLOBUF2G_LSB                                                                       20
+#define PHY_ANALOG_TXRF1_PDLOBUF2G_MASK                                                              0x00100000
+#define PHY_ANALOG_TXRF1_PDLOBUF2G_GET(x)                                            (((x) & 0x00100000) >> 20)
+#define PHY_ANALOG_TXRF1_PDLOBUF2G_SET(x)                                            (((x) << 20) & 0x00100000)
+#define PHY_ANALOG_TXRF1_PDLODIV2G_MSB                                                                       21
+#define PHY_ANALOG_TXRF1_PDLODIV2G_LSB                                                                       21
+#define PHY_ANALOG_TXRF1_PDLODIV2G_MASK                                                              0x00200000
+#define PHY_ANALOG_TXRF1_PDLODIV2G_GET(x)                                            (((x) & 0x00200000) >> 21)
+#define PHY_ANALOG_TXRF1_PDLODIV2G_SET(x)                                            (((x) << 21) & 0x00200000)
+#define PHY_ANALOG_TXRF1_LOBUF2GFORCED_MSB                                                                   22
+#define PHY_ANALOG_TXRF1_LOBUF2GFORCED_LSB                                                                   22
+#define PHY_ANALOG_TXRF1_LOBUF2GFORCED_MASK                                                          0x00400000
+#define PHY_ANALOG_TXRF1_LOBUF2GFORCED_GET(x)                                        (((x) & 0x00400000) >> 22)
+#define PHY_ANALOG_TXRF1_LOBUF2GFORCED_SET(x)                                        (((x) << 22) & 0x00400000)
+#define PHY_ANALOG_TXRF1_LODIV2GFORCED_MSB                                                                   23
+#define PHY_ANALOG_TXRF1_LODIV2GFORCED_LSB                                                                   23
+#define PHY_ANALOG_TXRF1_LODIV2GFORCED_MASK                                                          0x00800000
+#define PHY_ANALOG_TXRF1_LODIV2GFORCED_GET(x)                                        (((x) & 0x00800000) >> 23)
+#define PHY_ANALOG_TXRF1_LODIV2GFORCED_SET(x)                                        (((x) << 23) & 0x00800000)
+#define PHY_ANALOG_TXRF1_PADRVGN2G_MSB                                                                       30
+#define PHY_ANALOG_TXRF1_PADRVGN2G_LSB                                                                       24
+#define PHY_ANALOG_TXRF1_PADRVGN2G_MASK                                                              0x7f000000
+#define PHY_ANALOG_TXRF1_PADRVGN2G_GET(x)                                            (((x) & 0x7f000000) >> 24)
+#define PHY_ANALOG_TXRF1_PADRVGN2G_SET(x)                                            (((x) << 24) & 0x7f000000)
+#define PHY_ANALOG_TXRF1_LOCALTXGAIN2G_MSB                                                                   31
+#define PHY_ANALOG_TXRF1_LOCALTXGAIN2G_LSB                                                                   31
+#define PHY_ANALOG_TXRF1_LOCALTXGAIN2G_MASK                                                          0x80000000
+#define PHY_ANALOG_TXRF1_LOCALTXGAIN2G_GET(x)                                        (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_TXRF1_LOCALTXGAIN2G_SET(x)                                        (((x) << 31) & 0x80000000)
+
+/* macros for TXRF2 */
+#define PHY_ANALOG_TXRF2_ADDRESS                                                                     0x00000044
+#define PHY_ANALOG_TXRF2_OFFSET                                                                      0x00000044
+#define PHY_ANALOG_TXRF2_D3B5G_MSB                                                                            2
+#define PHY_ANALOG_TXRF2_D3B5G_LSB                                                                            0
+#define PHY_ANALOG_TXRF2_D3B5G_MASK                                                                  0x00000007
+#define PHY_ANALOG_TXRF2_D3B5G_GET(x)                                                 (((x) & 0x00000007) >> 0)
+#define PHY_ANALOG_TXRF2_D3B5G_SET(x)                                                 (((x) << 0) & 0x00000007)
+#define PHY_ANALOG_TXRF2_D4B5G_MSB                                                                            5
+#define PHY_ANALOG_TXRF2_D4B5G_LSB                                                                            3
+#define PHY_ANALOG_TXRF2_D4B5G_MASK                                                                  0x00000038
+#define PHY_ANALOG_TXRF2_D4B5G_GET(x)                                                 (((x) & 0x00000038) >> 3)
+#define PHY_ANALOG_TXRF2_D4B5G_SET(x)                                                 (((x) << 3) & 0x00000038)
+#define PHY_ANALOG_TXRF2_OCAS2G_MSB                                                                           8
+#define PHY_ANALOG_TXRF2_OCAS2G_LSB                                                                           6
+#define PHY_ANALOG_TXRF2_OCAS2G_MASK                                                                 0x000001c0
+#define PHY_ANALOG_TXRF2_OCAS2G_GET(x)                                                (((x) & 0x000001c0) >> 6)
+#define PHY_ANALOG_TXRF2_OCAS2G_SET(x)                                                (((x) << 6) & 0x000001c0)
+#define PHY_ANALOG_TXRF2_DCAS2G_MSB                                                                          11
+#define PHY_ANALOG_TXRF2_DCAS2G_LSB                                                                           9
+#define PHY_ANALOG_TXRF2_DCAS2G_MASK                                                                 0x00000e00
+#define PHY_ANALOG_TXRF2_DCAS2G_GET(x)                                                (((x) & 0x00000e00) >> 9)
+#define PHY_ANALOG_TXRF2_DCAS2G_SET(x)                                                (((x) << 9) & 0x00000e00)
+#define PHY_ANALOG_TXRF2_OB2G_PALOFF_MSB                                                                     14
+#define PHY_ANALOG_TXRF2_OB2G_PALOFF_LSB                                                                     12
+#define PHY_ANALOG_TXRF2_OB2G_PALOFF_MASK                                                            0x00007000
+#define PHY_ANALOG_TXRF2_OB2G_PALOFF_GET(x)                                          (((x) & 0x00007000) >> 12)
+#define PHY_ANALOG_TXRF2_OB2G_PALOFF_SET(x)                                          (((x) << 12) & 0x00007000)
+#define PHY_ANALOG_TXRF2_OB2G_QAM_MSB                                                                        17
+#define PHY_ANALOG_TXRF2_OB2G_QAM_LSB                                                                        15
+#define PHY_ANALOG_TXRF2_OB2G_QAM_MASK                                                               0x00038000
+#define PHY_ANALOG_TXRF2_OB2G_QAM_GET(x)                                             (((x) & 0x00038000) >> 15)
+#define PHY_ANALOG_TXRF2_OB2G_QAM_SET(x)                                             (((x) << 15) & 0x00038000)
+#define PHY_ANALOG_TXRF2_OB2G_PSK_MSB                                                                        20
+#define PHY_ANALOG_TXRF2_OB2G_PSK_LSB                                                                        18
+#define PHY_ANALOG_TXRF2_OB2G_PSK_MASK                                                               0x001c0000
+#define PHY_ANALOG_TXRF2_OB2G_PSK_GET(x)                                             (((x) & 0x001c0000) >> 18)
+#define PHY_ANALOG_TXRF2_OB2G_PSK_SET(x)                                             (((x) << 18) & 0x001c0000)
+#define PHY_ANALOG_TXRF2_OB2G_CCK_MSB                                                                        23
+#define PHY_ANALOG_TXRF2_OB2G_CCK_LSB                                                                        21
+#define PHY_ANALOG_TXRF2_OB2G_CCK_MASK                                                               0x00e00000
+#define PHY_ANALOG_TXRF2_OB2G_CCK_GET(x)                                             (((x) & 0x00e00000) >> 21)
+#define PHY_ANALOG_TXRF2_OB2G_CCK_SET(x)                                             (((x) << 21) & 0x00e00000)
+#define PHY_ANALOG_TXRF2_DB2G_MSB                                                                            26
+#define PHY_ANALOG_TXRF2_DB2G_LSB                                                                            24
+#define PHY_ANALOG_TXRF2_DB2G_MASK                                                                   0x07000000
+#define PHY_ANALOG_TXRF2_DB2G_GET(x)                                                 (((x) & 0x07000000) >> 24)
+#define PHY_ANALOG_TXRF2_DB2G_SET(x)                                                 (((x) << 24) & 0x07000000)
+#define PHY_ANALOG_TXRF2_PDOUT5G_MSB                                                                         30
+#define PHY_ANALOG_TXRF2_PDOUT5G_LSB                                                                         27
+#define PHY_ANALOG_TXRF2_PDOUT5G_MASK                                                                0x78000000
+#define PHY_ANALOG_TXRF2_PDOUT5G_GET(x)                                              (((x) & 0x78000000) >> 27)
+#define PHY_ANALOG_TXRF2_PDOUT5G_SET(x)                                              (((x) << 27) & 0x78000000)
+#define PHY_ANALOG_TXRF2_PDMXR5G_MSB                                                                         31
+#define PHY_ANALOG_TXRF2_PDMXR5G_LSB                                                                         31
+#define PHY_ANALOG_TXRF2_PDMXR5G_MASK                                                                0x80000000
+#define PHY_ANALOG_TXRF2_PDMXR5G_GET(x)                                              (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_TXRF2_PDMXR5G_SET(x)                                              (((x) << 31) & 0x80000000)
+
+/* macros for TXRF3 */
+#define PHY_ANALOG_TXRF3_ADDRESS                                                                     0x00000048
+#define PHY_ANALOG_TXRF3_OFFSET                                                                      0x00000048
+#define PHY_ANALOG_TXRF3_FILTR2G_MSB                                                                          1
+#define PHY_ANALOG_TXRF3_FILTR2G_LSB                                                                          0
+#define PHY_ANALOG_TXRF3_FILTR2G_MASK                                                                0x00000003
+#define PHY_ANALOG_TXRF3_FILTR2G_GET(x)                                               (((x) & 0x00000003) >> 0)
+#define PHY_ANALOG_TXRF3_FILTR2G_SET(x)                                               (((x) << 0) & 0x00000003)
+#define PHY_ANALOG_TXRF3_PWDFB2_2G_MSB                                                                        2
+#define PHY_ANALOG_TXRF3_PWDFB2_2G_LSB                                                                        2
+#define PHY_ANALOG_TXRF3_PWDFB2_2G_MASK                                                              0x00000004
+#define PHY_ANALOG_TXRF3_PWDFB2_2G_GET(x)                                             (((x) & 0x00000004) >> 2)
+#define PHY_ANALOG_TXRF3_PWDFB2_2G_SET(x)                                             (((x) << 2) & 0x00000004)
+#define PHY_ANALOG_TXRF3_PWDFB1_2G_MSB                                                                        3
+#define PHY_ANALOG_TXRF3_PWDFB1_2G_LSB                                                                        3
+#define PHY_ANALOG_TXRF3_PWDFB1_2G_MASK                                                              0x00000008
+#define PHY_ANALOG_TXRF3_PWDFB1_2G_GET(x)                                             (((x) & 0x00000008) >> 3)
+#define PHY_ANALOG_TXRF3_PWDFB1_2G_SET(x)                                             (((x) << 3) & 0x00000008)
+#define PHY_ANALOG_TXRF3_PDFB2G_MSB                                                                           4
+#define PHY_ANALOG_TXRF3_PDFB2G_LSB                                                                           4
+#define PHY_ANALOG_TXRF3_PDFB2G_MASK                                                                 0x00000010
+#define PHY_ANALOG_TXRF3_PDFB2G_GET(x)                                                (((x) & 0x00000010) >> 4)
+#define PHY_ANALOG_TXRF3_PDFB2G_SET(x)                                                (((x) << 4) & 0x00000010)
+#define PHY_ANALOG_TXRF3_RDIV5G_MSB                                                                           6
+#define PHY_ANALOG_TXRF3_RDIV5G_LSB                                                                           5
+#define PHY_ANALOG_TXRF3_RDIV5G_MASK                                                                 0x00000060
+#define PHY_ANALOG_TXRF3_RDIV5G_GET(x)                                                (((x) & 0x00000060) >> 5)
+#define PHY_ANALOG_TXRF3_RDIV5G_SET(x)                                                (((x) << 5) & 0x00000060)
+#define PHY_ANALOG_TXRF3_CAPDIV5G_MSB                                                                         9
+#define PHY_ANALOG_TXRF3_CAPDIV5G_LSB                                                                         7
+#define PHY_ANALOG_TXRF3_CAPDIV5G_MASK                                                               0x00000380
+#define PHY_ANALOG_TXRF3_CAPDIV5G_GET(x)                                              (((x) & 0x00000380) >> 7)
+#define PHY_ANALOG_TXRF3_CAPDIV5G_SET(x)                                              (((x) << 7) & 0x00000380)
+#define PHY_ANALOG_TXRF3_PDPREDIST5G_MSB                                                                     10
+#define PHY_ANALOG_TXRF3_PDPREDIST5G_LSB                                                                     10
+#define PHY_ANALOG_TXRF3_PDPREDIST5G_MASK                                                            0x00000400
+#define PHY_ANALOG_TXRF3_PDPREDIST5G_GET(x)                                          (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_TXRF3_PDPREDIST5G_SET(x)                                          (((x) << 10) & 0x00000400)
+#define PHY_ANALOG_TXRF3_RDIV2G_MSB                                                                          12
+#define PHY_ANALOG_TXRF3_RDIV2G_LSB                                                                          11
+#define PHY_ANALOG_TXRF3_RDIV2G_MASK                                                                 0x00001800
+#define PHY_ANALOG_TXRF3_RDIV2G_GET(x)                                               (((x) & 0x00001800) >> 11)
+#define PHY_ANALOG_TXRF3_RDIV2G_SET(x)                                               (((x) << 11) & 0x00001800)
+#define PHY_ANALOG_TXRF3_PDPREDIST2G_MSB                                                                     13
+#define PHY_ANALOG_TXRF3_PDPREDIST2G_LSB                                                                     13
+#define PHY_ANALOG_TXRF3_PDPREDIST2G_MASK                                                            0x00002000
+#define PHY_ANALOG_TXRF3_PDPREDIST2G_GET(x)                                          (((x) & 0x00002000) >> 13)
+#define PHY_ANALOG_TXRF3_PDPREDIST2G_SET(x)                                          (((x) << 13) & 0x00002000)
+#define PHY_ANALOG_TXRF3_OCAS5G_MSB                                                                          16
+#define PHY_ANALOG_TXRF3_OCAS5G_LSB                                                                          14
+#define PHY_ANALOG_TXRF3_OCAS5G_MASK                                                                 0x0001c000
+#define PHY_ANALOG_TXRF3_OCAS5G_GET(x)                                               (((x) & 0x0001c000) >> 14)
+#define PHY_ANALOG_TXRF3_OCAS5G_SET(x)                                               (((x) << 14) & 0x0001c000)
+#define PHY_ANALOG_TXRF3_D2CAS5G_MSB                                                                         19
+#define PHY_ANALOG_TXRF3_D2CAS5G_LSB                                                                         17
+#define PHY_ANALOG_TXRF3_D2CAS5G_MASK                                                                0x000e0000
+#define PHY_ANALOG_TXRF3_D2CAS5G_GET(x)                                              (((x) & 0x000e0000) >> 17)
+#define PHY_ANALOG_TXRF3_D2CAS5G_SET(x)                                              (((x) << 17) & 0x000e0000)
+#define PHY_ANALOG_TXRF3_D3CAS5G_MSB                                                                         22
+#define PHY_ANALOG_TXRF3_D3CAS5G_LSB                                                                         20
+#define PHY_ANALOG_TXRF3_D3CAS5G_MASK                                                                0x00700000
+#define PHY_ANALOG_TXRF3_D3CAS5G_GET(x)                                              (((x) & 0x00700000) >> 20)
+#define PHY_ANALOG_TXRF3_D3CAS5G_SET(x)                                              (((x) << 20) & 0x00700000)
+#define PHY_ANALOG_TXRF3_D4CAS5G_MSB                                                                         25
+#define PHY_ANALOG_TXRF3_D4CAS5G_LSB                                                                         23
+#define PHY_ANALOG_TXRF3_D4CAS5G_MASK                                                                0x03800000
+#define PHY_ANALOG_TXRF3_D4CAS5G_GET(x)                                              (((x) & 0x03800000) >> 23)
+#define PHY_ANALOG_TXRF3_D4CAS5G_SET(x)                                              (((x) << 23) & 0x03800000)
+#define PHY_ANALOG_TXRF3_OB5G_MSB                                                                            28
+#define PHY_ANALOG_TXRF3_OB5G_LSB                                                                            26
+#define PHY_ANALOG_TXRF3_OB5G_MASK                                                                   0x1c000000
+#define PHY_ANALOG_TXRF3_OB5G_GET(x)                                                 (((x) & 0x1c000000) >> 26)
+#define PHY_ANALOG_TXRF3_OB5G_SET(x)                                                 (((x) << 26) & 0x1c000000)
+#define PHY_ANALOG_TXRF3_D2B5G_MSB                                                                           31
+#define PHY_ANALOG_TXRF3_D2B5G_LSB                                                                           29
+#define PHY_ANALOG_TXRF3_D2B5G_MASK                                                                  0xe0000000
+#define PHY_ANALOG_TXRF3_D2B5G_GET(x)                                                (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_TXRF3_D2B5G_SET(x)                                                (((x) << 29) & 0xe0000000)
+
+/* macros for TXRF4 */
+#define PHY_ANALOG_TXRF4_ADDRESS                                                                     0x0000004c
+#define PHY_ANALOG_TXRF4_OFFSET                                                                      0x0000004c
+#define PHY_ANALOG_TXRF4_PK1B2G_CCK_MSB                                                                       1
+#define PHY_ANALOG_TXRF4_PK1B2G_CCK_LSB                                                                       0
+#define PHY_ANALOG_TXRF4_PK1B2G_CCK_MASK                                                             0x00000003
+#define PHY_ANALOG_TXRF4_PK1B2G_CCK_GET(x)                                            (((x) & 0x00000003) >> 0)
+#define PHY_ANALOG_TXRF4_PK1B2G_CCK_SET(x)                                            (((x) << 0) & 0x00000003)
+#define PHY_ANALOG_TXRF4_MIOB2G_QAM_MSB                                                                       4
+#define PHY_ANALOG_TXRF4_MIOB2G_QAM_LSB                                                                       2
+#define PHY_ANALOG_TXRF4_MIOB2G_QAM_MASK                                                             0x0000001c
+#define PHY_ANALOG_TXRF4_MIOB2G_QAM_GET(x)                                            (((x) & 0x0000001c) >> 2)
+#define PHY_ANALOG_TXRF4_MIOB2G_QAM_SET(x)                                            (((x) << 2) & 0x0000001c)
+#define PHY_ANALOG_TXRF4_MIOB2G_PSK_MSB                                                                       7
+#define PHY_ANALOG_TXRF4_MIOB2G_PSK_LSB                                                                       5
+#define PHY_ANALOG_TXRF4_MIOB2G_PSK_MASK                                                             0x000000e0
+#define PHY_ANALOG_TXRF4_MIOB2G_PSK_GET(x)                                            (((x) & 0x000000e0) >> 5)
+#define PHY_ANALOG_TXRF4_MIOB2G_PSK_SET(x)                                            (((x) << 5) & 0x000000e0)
+#define PHY_ANALOG_TXRF4_MIOB2G_CCK_MSB                                                                      10
+#define PHY_ANALOG_TXRF4_MIOB2G_CCK_LSB                                                                       8
+#define PHY_ANALOG_TXRF4_MIOB2G_CCK_MASK                                                             0x00000700
+#define PHY_ANALOG_TXRF4_MIOB2G_CCK_GET(x)                                            (((x) & 0x00000700) >> 8)
+#define PHY_ANALOG_TXRF4_MIOB2G_CCK_SET(x)                                            (((x) << 8) & 0x00000700)
+#define PHY_ANALOG_TXRF4_COMP2G_QAM_MSB                                                                      13
+#define PHY_ANALOG_TXRF4_COMP2G_QAM_LSB                                                                      11
+#define PHY_ANALOG_TXRF4_COMP2G_QAM_MASK                                                             0x00003800
+#define PHY_ANALOG_TXRF4_COMP2G_QAM_GET(x)                                           (((x) & 0x00003800) >> 11)
+#define PHY_ANALOG_TXRF4_COMP2G_QAM_SET(x)                                           (((x) << 11) & 0x00003800)
+#define PHY_ANALOG_TXRF4_COMP2G_PSK_MSB                                                                      16
+#define PHY_ANALOG_TXRF4_COMP2G_PSK_LSB                                                                      14
+#define PHY_ANALOG_TXRF4_COMP2G_PSK_MASK                                                             0x0001c000
+#define PHY_ANALOG_TXRF4_COMP2G_PSK_GET(x)                                           (((x) & 0x0001c000) >> 14)
+#define PHY_ANALOG_TXRF4_COMP2G_PSK_SET(x)                                           (((x) << 14) & 0x0001c000)
+#define PHY_ANALOG_TXRF4_COMP2G_CCK_MSB                                                                      19
+#define PHY_ANALOG_TXRF4_COMP2G_CCK_LSB                                                                      17
+#define PHY_ANALOG_TXRF4_COMP2G_CCK_MASK                                                             0x000e0000
+#define PHY_ANALOG_TXRF4_COMP2G_CCK_GET(x)                                           (((x) & 0x000e0000) >> 17)
+#define PHY_ANALOG_TXRF4_COMP2G_CCK_SET(x)                                           (((x) << 17) & 0x000e0000)
+#define PHY_ANALOG_TXRF4_AMP2B2G_QAM_MSB                                                                     22
+#define PHY_ANALOG_TXRF4_AMP2B2G_QAM_LSB                                                                     20
+#define PHY_ANALOG_TXRF4_AMP2B2G_QAM_MASK                                                            0x00700000
+#define PHY_ANALOG_TXRF4_AMP2B2G_QAM_GET(x)                                          (((x) & 0x00700000) >> 20)
+#define PHY_ANALOG_TXRF4_AMP2B2G_QAM_SET(x)                                          (((x) << 20) & 0x00700000)
+#define PHY_ANALOG_TXRF4_AMP2B2G_PSK_MSB                                                                     25
+#define PHY_ANALOG_TXRF4_AMP2B2G_PSK_LSB                                                                     23
+#define PHY_ANALOG_TXRF4_AMP2B2G_PSK_MASK                                                            0x03800000
+#define PHY_ANALOG_TXRF4_AMP2B2G_PSK_GET(x)                                          (((x) & 0x03800000) >> 23)
+#define PHY_ANALOG_TXRF4_AMP2B2G_PSK_SET(x)                                          (((x) << 23) & 0x03800000)
+#define PHY_ANALOG_TXRF4_AMP2B2G_CCK_MSB                                                                     28
+#define PHY_ANALOG_TXRF4_AMP2B2G_CCK_LSB                                                                     26
+#define PHY_ANALOG_TXRF4_AMP2B2G_CCK_MASK                                                            0x1c000000
+#define PHY_ANALOG_TXRF4_AMP2B2G_CCK_GET(x)                                          (((x) & 0x1c000000) >> 26)
+#define PHY_ANALOG_TXRF4_AMP2B2G_CCK_SET(x)                                          (((x) << 26) & 0x1c000000)
+#define PHY_ANALOG_TXRF4_AMP2CAS2G_MSB                                                                       31
+#define PHY_ANALOG_TXRF4_AMP2CAS2G_LSB                                                                       29
+#define PHY_ANALOG_TXRF4_AMP2CAS2G_MASK                                                              0xe0000000
+#define PHY_ANALOG_TXRF4_AMP2CAS2G_GET(x)                                            (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_TXRF4_AMP2CAS2G_SET(x)                                            (((x) << 29) & 0xe0000000)
+
+/* macros for TXRF5 */
+#define PHY_ANALOG_TXRF5_ADDRESS                                                                     0x00000050
+#define PHY_ANALOG_TXRF5_OFFSET                                                                      0x00000050
+#define PHY_ANALOG_TXRF5_SPARE5_MSB                                                                           0
+#define PHY_ANALOG_TXRF5_SPARE5_LSB                                                                           0
+#define PHY_ANALOG_TXRF5_SPARE5_MASK                                                                 0x00000001
+#define PHY_ANALOG_TXRF5_SPARE5_GET(x)                                                (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_TXRF5_SPARE5_SET(x)                                                (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_TXRF5_PAL_LOCKED_MSB                                                                       1
+#define PHY_ANALOG_TXRF5_PAL_LOCKED_LSB                                                                       1
+#define PHY_ANALOG_TXRF5_PAL_LOCKED_MASK                                                             0x00000002
+#define PHY_ANALOG_TXRF5_PAL_LOCKED_GET(x)                                            (((x) & 0x00000002) >> 1)
+#define PHY_ANALOG_TXRF5_FBHI2G_MSB                                                                           2
+#define PHY_ANALOG_TXRF5_FBHI2G_LSB                                                                           2
+#define PHY_ANALOG_TXRF5_FBHI2G_MASK                                                                 0x00000004
+#define PHY_ANALOG_TXRF5_FBHI2G_GET(x)                                                (((x) & 0x00000004) >> 2)
+#define PHY_ANALOG_TXRF5_FBLO2G_MSB                                                                           3
+#define PHY_ANALOG_TXRF5_FBLO2G_LSB                                                                           3
+#define PHY_ANALOG_TXRF5_FBLO2G_MASK                                                                 0x00000008
+#define PHY_ANALOG_TXRF5_FBLO2G_GET(x)                                                (((x) & 0x00000008) >> 3)
+#define PHY_ANALOG_TXRF5_NOPALGAIN2G_MSB                                                                      4
+#define PHY_ANALOG_TXRF5_NOPALGAIN2G_LSB                                                                      4
+#define PHY_ANALOG_TXRF5_NOPALGAIN2G_MASK                                                            0x00000010
+#define PHY_ANALOG_TXRF5_NOPALGAIN2G_GET(x)                                           (((x) & 0x00000010) >> 4)
+#define PHY_ANALOG_TXRF5_NOPALGAIN2G_SET(x)                                           (((x) << 4) & 0x00000010)
+#define PHY_ANALOG_TXRF5_ENPACAL2G_MSB                                                                        5
+#define PHY_ANALOG_TXRF5_ENPACAL2G_LSB                                                                        5
+#define PHY_ANALOG_TXRF5_ENPACAL2G_MASK                                                              0x00000020
+#define PHY_ANALOG_TXRF5_ENPACAL2G_GET(x)                                             (((x) & 0x00000020) >> 5)
+#define PHY_ANALOG_TXRF5_ENPACAL2G_SET(x)                                             (((x) << 5) & 0x00000020)
+#define PHY_ANALOG_TXRF5_OFFSET2G_MSB                                                                        12
+#define PHY_ANALOG_TXRF5_OFFSET2G_LSB                                                                         6
+#define PHY_ANALOG_TXRF5_OFFSET2G_MASK                                                               0x00001fc0
+#define PHY_ANALOG_TXRF5_OFFSET2G_GET(x)                                              (((x) & 0x00001fc0) >> 6)
+#define PHY_ANALOG_TXRF5_OFFSET2G_SET(x)                                              (((x) << 6) & 0x00001fc0)
+#define PHY_ANALOG_TXRF5_ENOFFSETCAL2G_MSB                                                                   13
+#define PHY_ANALOG_TXRF5_ENOFFSETCAL2G_LSB                                                                   13
+#define PHY_ANALOG_TXRF5_ENOFFSETCAL2G_MASK                                                          0x00002000
+#define PHY_ANALOG_TXRF5_ENOFFSETCAL2G_GET(x)                                        (((x) & 0x00002000) >> 13)
+#define PHY_ANALOG_TXRF5_ENOFFSETCAL2G_SET(x)                                        (((x) << 13) & 0x00002000)
+#define PHY_ANALOG_TXRF5_REFHI2G_MSB                                                                         16
+#define PHY_ANALOG_TXRF5_REFHI2G_LSB                                                                         14
+#define PHY_ANALOG_TXRF5_REFHI2G_MASK                                                                0x0001c000
+#define PHY_ANALOG_TXRF5_REFHI2G_GET(x)                                              (((x) & 0x0001c000) >> 14)
+#define PHY_ANALOG_TXRF5_REFHI2G_SET(x)                                              (((x) << 14) & 0x0001c000)
+#define PHY_ANALOG_TXRF5_REFLO2G_MSB                                                                         19
+#define PHY_ANALOG_TXRF5_REFLO2G_LSB                                                                         17
+#define PHY_ANALOG_TXRF5_REFLO2G_MASK                                                                0x000e0000
+#define PHY_ANALOG_TXRF5_REFLO2G_GET(x)                                              (((x) & 0x000e0000) >> 17)
+#define PHY_ANALOG_TXRF5_REFLO2G_SET(x)                                              (((x) << 17) & 0x000e0000)
+#define PHY_ANALOG_TXRF5_PALCLAMP2G_MSB                                                                      21
+#define PHY_ANALOG_TXRF5_PALCLAMP2G_LSB                                                                      20
+#define PHY_ANALOG_TXRF5_PALCLAMP2G_MASK                                                             0x00300000
+#define PHY_ANALOG_TXRF5_PALCLAMP2G_GET(x)                                           (((x) & 0x00300000) >> 20)
+#define PHY_ANALOG_TXRF5_PALCLAMP2G_SET(x)                                           (((x) << 20) & 0x00300000)
+#define PHY_ANALOG_TXRF5_PK2B2G_QAM_MSB                                                                      23
+#define PHY_ANALOG_TXRF5_PK2B2G_QAM_LSB                                                                      22
+#define PHY_ANALOG_TXRF5_PK2B2G_QAM_MASK                                                             0x00c00000
+#define PHY_ANALOG_TXRF5_PK2B2G_QAM_GET(x)                                           (((x) & 0x00c00000) >> 22)
+#define PHY_ANALOG_TXRF5_PK2B2G_QAM_SET(x)                                           (((x) << 22) & 0x00c00000)
+#define PHY_ANALOG_TXRF5_PK2B2G_PSK_MSB                                                                      25
+#define PHY_ANALOG_TXRF5_PK2B2G_PSK_LSB                                                                      24
+#define PHY_ANALOG_TXRF5_PK2B2G_PSK_MASK                                                             0x03000000
+#define PHY_ANALOG_TXRF5_PK2B2G_PSK_GET(x)                                           (((x) & 0x03000000) >> 24)
+#define PHY_ANALOG_TXRF5_PK2B2G_PSK_SET(x)                                           (((x) << 24) & 0x03000000)
+#define PHY_ANALOG_TXRF5_PK2B2G_CCK_MSB                                                                      27
+#define PHY_ANALOG_TXRF5_PK2B2G_CCK_LSB                                                                      26
+#define PHY_ANALOG_TXRF5_PK2B2G_CCK_MASK                                                             0x0c000000
+#define PHY_ANALOG_TXRF5_PK2B2G_CCK_GET(x)                                           (((x) & 0x0c000000) >> 26)
+#define PHY_ANALOG_TXRF5_PK2B2G_CCK_SET(x)                                           (((x) << 26) & 0x0c000000)
+#define PHY_ANALOG_TXRF5_PK1B2G_QAM_MSB                                                                      29
+#define PHY_ANALOG_TXRF5_PK1B2G_QAM_LSB                                                                      28
+#define PHY_ANALOG_TXRF5_PK1B2G_QAM_MASK                                                             0x30000000
+#define PHY_ANALOG_TXRF5_PK1B2G_QAM_GET(x)                                           (((x) & 0x30000000) >> 28)
+#define PHY_ANALOG_TXRF5_PK1B2G_QAM_SET(x)                                           (((x) << 28) & 0x30000000)
+#define PHY_ANALOG_TXRF5_PK1B2G_PSK_MSB                                                                      31
+#define PHY_ANALOG_TXRF5_PK1B2G_PSK_LSB                                                                      30
+#define PHY_ANALOG_TXRF5_PK1B2G_PSK_MASK                                                             0xc0000000
+#define PHY_ANALOG_TXRF5_PK1B2G_PSK_GET(x)                                           (((x) & 0xc0000000) >> 30)
+#define PHY_ANALOG_TXRF5_PK1B2G_PSK_SET(x)                                           (((x) << 30) & 0xc0000000)
+
+/* macros for TXRF6 */
+#define PHY_ANALOG_TXRF6_ADDRESS                                                                     0x00000054
+#define PHY_ANALOG_TXRF6_OFFSET                                                                      0x00000054
+#define PHY_ANALOG_TXRF6_PALCLKGATE2G_MSB                                                                     0
+#define PHY_ANALOG_TXRF6_PALCLKGATE2G_LSB                                                                     0
+#define PHY_ANALOG_TXRF6_PALCLKGATE2G_MASK                                                           0x00000001
+#define PHY_ANALOG_TXRF6_PALCLKGATE2G_GET(x)                                          (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_TXRF6_PALCLKGATE2G_SET(x)                                          (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_TXRF6_PALFLUCTCOUNT2G_MSB                                                                  8
+#define PHY_ANALOG_TXRF6_PALFLUCTCOUNT2G_LSB                                                                  1
+#define PHY_ANALOG_TXRF6_PALFLUCTCOUNT2G_MASK                                                        0x000001fe
+#define PHY_ANALOG_TXRF6_PALFLUCTCOUNT2G_GET(x)                                       (((x) & 0x000001fe) >> 1)
+#define PHY_ANALOG_TXRF6_PALFLUCTCOUNT2G_SET(x)                                       (((x) << 1) & 0x000001fe)
+#define PHY_ANALOG_TXRF6_PALFLUCTGAIN2G_MSB                                                                  10
+#define PHY_ANALOG_TXRF6_PALFLUCTGAIN2G_LSB                                                                   9
+#define PHY_ANALOG_TXRF6_PALFLUCTGAIN2G_MASK                                                         0x00000600
+#define PHY_ANALOG_TXRF6_PALFLUCTGAIN2G_GET(x)                                        (((x) & 0x00000600) >> 9)
+#define PHY_ANALOG_TXRF6_PALFLUCTGAIN2G_SET(x)                                        (((x) << 9) & 0x00000600)
+#define PHY_ANALOG_TXRF6_PALNOFLUCT2G_MSB                                                                    11
+#define PHY_ANALOG_TXRF6_PALNOFLUCT2G_LSB                                                                    11
+#define PHY_ANALOG_TXRF6_PALNOFLUCT2G_MASK                                                           0x00000800
+#define PHY_ANALOG_TXRF6_PALNOFLUCT2G_GET(x)                                         (((x) & 0x00000800) >> 11)
+#define PHY_ANALOG_TXRF6_PALNOFLUCT2G_SET(x)                                         (((x) << 11) & 0x00000800)
+#define PHY_ANALOG_TXRF6_GAINSTEP2G_MSB                                                                      14
+#define PHY_ANALOG_TXRF6_GAINSTEP2G_LSB                                                                      12
+#define PHY_ANALOG_TXRF6_GAINSTEP2G_MASK                                                             0x00007000
+#define PHY_ANALOG_TXRF6_GAINSTEP2G_GET(x)                                           (((x) & 0x00007000) >> 12)
+#define PHY_ANALOG_TXRF6_GAINSTEP2G_SET(x)                                           (((x) << 12) & 0x00007000)
+#define PHY_ANALOG_TXRF6_USE_GAIN_DELTA2G_MSB                                                                15
+#define PHY_ANALOG_TXRF6_USE_GAIN_DELTA2G_LSB                                                                15
+#define PHY_ANALOG_TXRF6_USE_GAIN_DELTA2G_MASK                                                       0x00008000
+#define PHY_ANALOG_TXRF6_USE_GAIN_DELTA2G_GET(x)                                     (((x) & 0x00008000) >> 15)
+#define PHY_ANALOG_TXRF6_USE_GAIN_DELTA2G_SET(x)                                     (((x) << 15) & 0x00008000)
+#define PHY_ANALOG_TXRF6_CAPDIV_I2G_MSB                                                                      19
+#define PHY_ANALOG_TXRF6_CAPDIV_I2G_LSB                                                                      16
+#define PHY_ANALOG_TXRF6_CAPDIV_I2G_MASK                                                             0x000f0000
+#define PHY_ANALOG_TXRF6_CAPDIV_I2G_GET(x)                                           (((x) & 0x000f0000) >> 16)
+#define PHY_ANALOG_TXRF6_CAPDIV_I2G_SET(x)                                           (((x) << 16) & 0x000f0000)
+#define PHY_ANALOG_TXRF6_PADRVGN_INDEX_I2G_MSB                                                               23
+#define PHY_ANALOG_TXRF6_PADRVGN_INDEX_I2G_LSB                                                               20
+#define PHY_ANALOG_TXRF6_PADRVGN_INDEX_I2G_MASK                                                      0x00f00000
+#define PHY_ANALOG_TXRF6_PADRVGN_INDEX_I2G_GET(x)                                    (((x) & 0x00f00000) >> 20)
+#define PHY_ANALOG_TXRF6_PADRVGN_INDEX_I2G_SET(x)                                    (((x) << 20) & 0x00f00000)
+#define PHY_ANALOG_TXRF6_VCMONDELAY2G_MSB                                                                    26
+#define PHY_ANALOG_TXRF6_VCMONDELAY2G_LSB                                                                    24
+#define PHY_ANALOG_TXRF6_VCMONDELAY2G_MASK                                                           0x07000000
+#define PHY_ANALOG_TXRF6_VCMONDELAY2G_GET(x)                                         (((x) & 0x07000000) >> 24)
+#define PHY_ANALOG_TXRF6_VCMONDELAY2G_SET(x)                                         (((x) << 24) & 0x07000000)
+#define PHY_ANALOG_TXRF6_CAPDIV2G_MSB                                                                        30
+#define PHY_ANALOG_TXRF6_CAPDIV2G_LSB                                                                        27
+#define PHY_ANALOG_TXRF6_CAPDIV2G_MASK                                                               0x78000000
+#define PHY_ANALOG_TXRF6_CAPDIV2G_GET(x)                                             (((x) & 0x78000000) >> 27)
+#define PHY_ANALOG_TXRF6_CAPDIV2G_SET(x)                                             (((x) << 27) & 0x78000000)
+#define PHY_ANALOG_TXRF6_CAPDIV2GOVR_MSB                                                                     31
+#define PHY_ANALOG_TXRF6_CAPDIV2GOVR_LSB                                                                     31
+#define PHY_ANALOG_TXRF6_CAPDIV2GOVR_MASK                                                            0x80000000
+#define PHY_ANALOG_TXRF6_CAPDIV2GOVR_GET(x)                                          (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_TXRF6_CAPDIV2GOVR_SET(x)                                          (((x) << 31) & 0x80000000)
+
+/* macros for TXRF7 */
+#define PHY_ANALOG_TXRF7_ADDRESS                                                                     0x00000058
+#define PHY_ANALOG_TXRF7_OFFSET                                                                      0x00000058
+#define PHY_ANALOG_TXRF7_SPARE7_MSB                                                                           1
+#define PHY_ANALOG_TXRF7_SPARE7_LSB                                                                           0
+#define PHY_ANALOG_TXRF7_SPARE7_MASK                                                                 0x00000003
+#define PHY_ANALOG_TXRF7_SPARE7_GET(x)                                                (((x) & 0x00000003) >> 0)
+#define PHY_ANALOG_TXRF7_SPARE7_SET(x)                                                (((x) << 0) & 0x00000003)
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_4_MSB                                                                     7
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_4_LSB                                                                     2
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_4_MASK                                                           0x000000fc
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_4_GET(x)                                          (((x) & 0x000000fc) >> 2)
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_4_SET(x)                                          (((x) << 2) & 0x000000fc)
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_3_MSB                                                                    13
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_3_LSB                                                                     8
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_3_MASK                                                           0x00003f00
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_3_GET(x)                                          (((x) & 0x00003f00) >> 8)
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_3_SET(x)                                          (((x) << 8) & 0x00003f00)
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_2_MSB                                                                    19
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_2_LSB                                                                    14
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_2_MASK                                                           0x000fc000
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_2_GET(x)                                         (((x) & 0x000fc000) >> 14)
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_2_SET(x)                                         (((x) << 14) & 0x000fc000)
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_1_MSB                                                                    25
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_1_LSB                                                                    20
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_1_MASK                                                           0x03f00000
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_1_GET(x)                                         (((x) & 0x03f00000) >> 20)
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_1_SET(x)                                         (((x) << 20) & 0x03f00000)
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_0_MSB                                                                    31
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_0_LSB                                                                    26
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_0_MASK                                                           0xfc000000
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_0_GET(x)                                         (((x) & 0xfc000000) >> 26)
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_0_SET(x)                                         (((x) << 26) & 0xfc000000)
+
+/* macros for TXRF8 */
+#define PHY_ANALOG_TXRF8_ADDRESS                                                                     0x0000005c
+#define PHY_ANALOG_TXRF8_OFFSET                                                                      0x0000005c
+#define PHY_ANALOG_TXRF8_SPARE8_MSB                                                                           1
+#define PHY_ANALOG_TXRF8_SPARE8_LSB                                                                           0
+#define PHY_ANALOG_TXRF8_SPARE8_MASK                                                                 0x00000003
+#define PHY_ANALOG_TXRF8_SPARE8_GET(x)                                                (((x) & 0x00000003) >> 0)
+#define PHY_ANALOG_TXRF8_SPARE8_SET(x)                                                (((x) << 0) & 0x00000003)
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_9_MSB                                                                     7
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_9_LSB                                                                     2
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_9_MASK                                                           0x000000fc
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_9_GET(x)                                          (((x) & 0x000000fc) >> 2)
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_9_SET(x)                                          (((x) << 2) & 0x000000fc)
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_8_MSB                                                                    13
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_8_LSB                                                                     8
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_8_MASK                                                           0x00003f00
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_8_GET(x)                                          (((x) & 0x00003f00) >> 8)
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_8_SET(x)                                          (((x) << 8) & 0x00003f00)
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_7_MSB                                                                    19
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_7_LSB                                                                    14
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_7_MASK                                                           0x000fc000
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_7_GET(x)                                         (((x) & 0x000fc000) >> 14)
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_7_SET(x)                                         (((x) << 14) & 0x000fc000)
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_6_MSB                                                                    25
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_6_LSB                                                                    20
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_6_MASK                                                           0x03f00000
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_6_GET(x)                                         (((x) & 0x03f00000) >> 20)
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_6_SET(x)                                         (((x) << 20) & 0x03f00000)
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_5_MSB                                                                    31
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_5_LSB                                                                    26
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_5_MASK                                                           0xfc000000
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_5_GET(x)                                         (((x) & 0xfc000000) >> 26)
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_5_SET(x)                                         (((x) << 26) & 0xfc000000)
+
+/* macros for TXRF9 */
+#define PHY_ANALOG_TXRF9_ADDRESS                                                                     0x00000060
+#define PHY_ANALOG_TXRF9_OFFSET                                                                      0x00000060
+#define PHY_ANALOG_TXRF9_SPARE9_MSB                                                                           1
+#define PHY_ANALOG_TXRF9_SPARE9_LSB                                                                           0
+#define PHY_ANALOG_TXRF9_SPARE9_MASK                                                                 0x00000003
+#define PHY_ANALOG_TXRF9_SPARE9_GET(x)                                                (((x) & 0x00000003) >> 0)
+#define PHY_ANALOG_TXRF9_SPARE9_SET(x)                                                (((x) << 0) & 0x00000003)
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_14_MSB                                                                    7
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_14_LSB                                                                    2
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_14_MASK                                                          0x000000fc
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_14_GET(x)                                         (((x) & 0x000000fc) >> 2)
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_14_SET(x)                                         (((x) << 2) & 0x000000fc)
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_13_MSB                                                                   13
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_13_LSB                                                                    8
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_13_MASK                                                          0x00003f00
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_13_GET(x)                                         (((x) & 0x00003f00) >> 8)
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_13_SET(x)                                         (((x) << 8) & 0x00003f00)
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_12_MSB                                                                   19
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_12_LSB                                                                   14
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_12_MASK                                                          0x000fc000
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_12_GET(x)                                        (((x) & 0x000fc000) >> 14)
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_12_SET(x)                                        (((x) << 14) & 0x000fc000)
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_11_MSB                                                                   25
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_11_LSB                                                                   20
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_11_MASK                                                          0x03f00000
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_11_GET(x)                                        (((x) & 0x03f00000) >> 20)
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_11_SET(x)                                        (((x) << 20) & 0x03f00000)
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_10_MSB                                                                   31
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_10_LSB                                                                   26
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_10_MASK                                                          0xfc000000
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_10_GET(x)                                        (((x) & 0xfc000000) >> 26)
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_10_SET(x)                                        (((x) << 26) & 0xfc000000)
+
+/* macros for TXRF10 */
+#define PHY_ANALOG_TXRF10_ADDRESS                                                                    0x00000064
+#define PHY_ANALOG_TXRF10_OFFSET                                                                     0x00000064
+#define PHY_ANALOG_TXRF10_SPARE10_MSB                                                                         2
+#define PHY_ANALOG_TXRF10_SPARE10_LSB                                                                         0
+#define PHY_ANALOG_TXRF10_SPARE10_MASK                                                               0x00000007
+#define PHY_ANALOG_TXRF10_SPARE10_GET(x)                                              (((x) & 0x00000007) >> 0)
+#define PHY_ANALOG_TXRF10_SPARE10_SET(x)                                              (((x) << 0) & 0x00000007)
+#define PHY_ANALOG_TXRF10_PDOUT5G_3CALTX_MSB                                                                  3
+#define PHY_ANALOG_TXRF10_PDOUT5G_3CALTX_LSB                                                                  3
+#define PHY_ANALOG_TXRF10_PDOUT5G_3CALTX_MASK                                                        0x00000008
+#define PHY_ANALOG_TXRF10_PDOUT5G_3CALTX_GET(x)                                       (((x) & 0x00000008) >> 3)
+#define PHY_ANALOG_TXRF10_PDOUT5G_3CALTX_SET(x)                                       (((x) << 3) & 0x00000008)
+#define PHY_ANALOG_TXRF10_D3B5GCALTX_MSB                                                                      6
+#define PHY_ANALOG_TXRF10_D3B5GCALTX_LSB                                                                      4
+#define PHY_ANALOG_TXRF10_D3B5GCALTX_MASK                                                            0x00000070
+#define PHY_ANALOG_TXRF10_D3B5GCALTX_GET(x)                                           (((x) & 0x00000070) >> 4)
+#define PHY_ANALOG_TXRF10_D3B5GCALTX_SET(x)                                           (((x) << 4) & 0x00000070)
+#define PHY_ANALOG_TXRF10_D4B5GCALTX_MSB                                                                      9
+#define PHY_ANALOG_TXRF10_D4B5GCALTX_LSB                                                                      7
+#define PHY_ANALOG_TXRF10_D4B5GCALTX_MASK                                                            0x00000380
+#define PHY_ANALOG_TXRF10_D4B5GCALTX_GET(x)                                           (((x) & 0x00000380) >> 7)
+#define PHY_ANALOG_TXRF10_D4B5GCALTX_SET(x)                                           (((x) << 7) & 0x00000380)
+#define PHY_ANALOG_TXRF10_PADRVGN2GCALTX_MSB                                                                 16
+#define PHY_ANALOG_TXRF10_PADRVGN2GCALTX_LSB                                                                 10
+#define PHY_ANALOG_TXRF10_PADRVGN2GCALTX_MASK                                                        0x0001fc00
+#define PHY_ANALOG_TXRF10_PADRVGN2GCALTX_GET(x)                                      (((x) & 0x0001fc00) >> 10)
+#define PHY_ANALOG_TXRF10_PADRVGN2GCALTX_SET(x)                                      (((x) << 10) & 0x0001fc00)
+#define PHY_ANALOG_TXRF10_DB2GCALTX_MSB                                                                      19
+#define PHY_ANALOG_TXRF10_DB2GCALTX_LSB                                                                      17
+#define PHY_ANALOG_TXRF10_DB2GCALTX_MASK                                                             0x000e0000
+#define PHY_ANALOG_TXRF10_DB2GCALTX_GET(x)                                           (((x) & 0x000e0000) >> 17)
+#define PHY_ANALOG_TXRF10_DB2GCALTX_SET(x)                                           (((x) << 17) & 0x000e0000)
+#define PHY_ANALOG_TXRF10_CALTXSHIFT_MSB                                                                     20
+#define PHY_ANALOG_TXRF10_CALTXSHIFT_LSB                                                                     20
+#define PHY_ANALOG_TXRF10_CALTXSHIFT_MASK                                                            0x00100000
+#define PHY_ANALOG_TXRF10_CALTXSHIFT_GET(x)                                          (((x) & 0x00100000) >> 20)
+#define PHY_ANALOG_TXRF10_CALTXSHIFT_SET(x)                                          (((x) << 20) & 0x00100000)
+#define PHY_ANALOG_TXRF10_CALTXSHIFTOVR_MSB                                                                  21
+#define PHY_ANALOG_TXRF10_CALTXSHIFTOVR_LSB                                                                  21
+#define PHY_ANALOG_TXRF10_CALTXSHIFTOVR_MASK                                                         0x00200000
+#define PHY_ANALOG_TXRF10_CALTXSHIFTOVR_GET(x)                                       (((x) & 0x00200000) >> 21)
+#define PHY_ANALOG_TXRF10_CALTXSHIFTOVR_SET(x)                                       (((x) << 21) & 0x00200000)
+#define PHY_ANALOG_TXRF10_PADRVGN2G_SMOUT_MSB                                                                27
+#define PHY_ANALOG_TXRF10_PADRVGN2G_SMOUT_LSB                                                                22
+#define PHY_ANALOG_TXRF10_PADRVGN2G_SMOUT_MASK                                                       0x0fc00000
+#define PHY_ANALOG_TXRF10_PADRVGN2G_SMOUT_GET(x)                                     (((x) & 0x0fc00000) >> 22)
+#define PHY_ANALOG_TXRF10_PADRVGN_INDEX2G_SMOUT_MSB                                                          31
+#define PHY_ANALOG_TXRF10_PADRVGN_INDEX2G_SMOUT_LSB                                                          28
+#define PHY_ANALOG_TXRF10_PADRVGN_INDEX2G_SMOUT_MASK                                                 0xf0000000
+#define PHY_ANALOG_TXRF10_PADRVGN_INDEX2G_SMOUT_GET(x)                               (((x) & 0xf0000000) >> 28)
+
+/* macros for TXRF11 */
+#define PHY_ANALOG_TXRF11_ADDRESS                                                                    0x00000068
+#define PHY_ANALOG_TXRF11_OFFSET                                                                     0x00000068
+#define PHY_ANALOG_TXRF11_SPARE11_MSB                                                                         1
+#define PHY_ANALOG_TXRF11_SPARE11_LSB                                                                         0
+#define PHY_ANALOG_TXRF11_SPARE11_MASK                                                               0x00000003
+#define PHY_ANALOG_TXRF11_SPARE11_GET(x)                                              (((x) & 0x00000003) >> 0)
+#define PHY_ANALOG_TXRF11_SPARE11_SET(x)                                              (((x) << 0) & 0x00000003)
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV5G_MSB                                                                4
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV5G_LSB                                                                2
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV5G_MASK                                                      0x0000001c
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV5G_GET(x)                                     (((x) & 0x0000001c) >> 2)
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV5G_SET(x)                                     (((x) << 2) & 0x0000001c)
+#define PHY_ANALOG_TXRF11_PWD_IR25PA2G_MSB                                                                    7
+#define PHY_ANALOG_TXRF11_PWD_IR25PA2G_LSB                                                                    5
+#define PHY_ANALOG_TXRF11_PWD_IR25PA2G_MASK                                                          0x000000e0
+#define PHY_ANALOG_TXRF11_PWD_IR25PA2G_GET(x)                                         (((x) & 0x000000e0) >> 5)
+#define PHY_ANALOG_TXRF11_PWD_IR25PA2G_SET(x)                                         (((x) << 5) & 0x000000e0)
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS2G_MSB                                                              10
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS2G_LSB                                                               8
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS2G_MASK                                                     0x00000700
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS2G_GET(x)                                    (((x) & 0x00000700) >> 8)
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS2G_SET(x)                                    (((x) << 8) & 0x00000700)
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV2G_MSB                                                               13
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV2G_LSB                                                               11
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV2G_MASK                                                      0x00003800
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV2G_GET(x)                                    (((x) & 0x00003800) >> 11)
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV2G_SET(x)                                    (((x) << 11) & 0x00003800)
+#define PHY_ANALOG_TXRF11_PWD_ICSPARE_MSB                                                                    16
+#define PHY_ANALOG_TXRF11_PWD_ICSPARE_LSB                                                                    14
+#define PHY_ANALOG_TXRF11_PWD_ICSPARE_MASK                                                           0x0001c000
+#define PHY_ANALOG_TXRF11_PWD_ICSPARE_GET(x)                                         (((x) & 0x0001c000) >> 14)
+#define PHY_ANALOG_TXRF11_PWD_ICSPARE_SET(x)                                         (((x) << 14) & 0x0001c000)
+#define PHY_ANALOG_TXRF11_PWD_IC25TEMPSEN_MSB                                                                19
+#define PHY_ANALOG_TXRF11_PWD_IC25TEMPSEN_LSB                                                                17
+#define PHY_ANALOG_TXRF11_PWD_IC25TEMPSEN_MASK                                                       0x000e0000
+#define PHY_ANALOG_TXRF11_PWD_IC25TEMPSEN_GET(x)                                     (((x) & 0x000e0000) >> 17)
+#define PHY_ANALOG_TXRF11_PWD_IC25TEMPSEN_SET(x)                                     (((x) << 17) & 0x000e0000)
+#define PHY_ANALOG_TXRF11_PWD_IC25PA5G2_MSB                                                                  22
+#define PHY_ANALOG_TXRF11_PWD_IC25PA5G2_LSB                                                                  20
+#define PHY_ANALOG_TXRF11_PWD_IC25PA5G2_MASK                                                         0x00700000
+#define PHY_ANALOG_TXRF11_PWD_IC25PA5G2_GET(x)                                       (((x) & 0x00700000) >> 20)
+#define PHY_ANALOG_TXRF11_PWD_IC25PA5G2_SET(x)                                       (((x) << 20) & 0x00700000)
+#define PHY_ANALOG_TXRF11_PWD_IC25PA5G1_MSB                                                                  25
+#define PHY_ANALOG_TXRF11_PWD_IC25PA5G1_LSB                                                                  23
+#define PHY_ANALOG_TXRF11_PWD_IC25PA5G1_MASK                                                         0x03800000
+#define PHY_ANALOG_TXRF11_PWD_IC25PA5G1_GET(x)                                       (((x) & 0x03800000) >> 23)
+#define PHY_ANALOG_TXRF11_PWD_IC25PA5G1_SET(x)                                       (((x) << 23) & 0x03800000)
+#define PHY_ANALOG_TXRF11_PWD_IC25MIXBUF5G_MSB                                                               28
+#define PHY_ANALOG_TXRF11_PWD_IC25MIXBUF5G_LSB                                                               26
+#define PHY_ANALOG_TXRF11_PWD_IC25MIXBUF5G_MASK                                                      0x1c000000
+#define PHY_ANALOG_TXRF11_PWD_IC25MIXBUF5G_GET(x)                                    (((x) & 0x1c000000) >> 26)
+#define PHY_ANALOG_TXRF11_PWD_IC25MIXBUF5G_SET(x)                                    (((x) << 26) & 0x1c000000)
+#define PHY_ANALOG_TXRF11_PWD_IC25PA2G_MSB                                                                   31
+#define PHY_ANALOG_TXRF11_PWD_IC25PA2G_LSB                                                                   29
+#define PHY_ANALOG_TXRF11_PWD_IC25PA2G_MASK                                                          0xe0000000
+#define PHY_ANALOG_TXRF11_PWD_IC25PA2G_GET(x)                                        (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_TXRF11_PWD_IC25PA2G_SET(x)                                        (((x) << 29) & 0xe0000000)
+
+/* macros for TXRF12 */
+#define PHY_ANALOG_TXRF12_ADDRESS                                                                    0x0000006c
+#define PHY_ANALOG_TXRF12_OFFSET                                                                     0x0000006c
+#define PHY_ANALOG_TXRF12_SPARE12_2_MSB                                                                       7
+#define PHY_ANALOG_TXRF12_SPARE12_2_LSB                                                                       0
+#define PHY_ANALOG_TXRF12_SPARE12_2_MASK                                                             0x000000ff
+#define PHY_ANALOG_TXRF12_SPARE12_2_GET(x)                                            (((x) & 0x000000ff) >> 0)
+#define PHY_ANALOG_TXRF12_SPARE12_1_MSB                                                                       9
+#define PHY_ANALOG_TXRF12_SPARE12_1_LSB                                                                       8
+#define PHY_ANALOG_TXRF12_SPARE12_1_MASK                                                             0x00000300
+#define PHY_ANALOG_TXRF12_SPARE12_1_GET(x)                                            (((x) & 0x00000300) >> 8)
+#define PHY_ANALOG_TXRF12_SPARE12_1_SET(x)                                            (((x) << 8) & 0x00000300)
+#define PHY_ANALOG_TXRF12_ATBSEL5G_MSB                                                                       13
+#define PHY_ANALOG_TXRF12_ATBSEL5G_LSB                                                                       10
+#define PHY_ANALOG_TXRF12_ATBSEL5G_MASK                                                              0x00003c00
+#define PHY_ANALOG_TXRF12_ATBSEL5G_GET(x)                                            (((x) & 0x00003c00) >> 10)
+#define PHY_ANALOG_TXRF12_ATBSEL5G_SET(x)                                            (((x) << 10) & 0x00003c00)
+#define PHY_ANALOG_TXRF12_ATBSEL2G_MSB                                                                       16
+#define PHY_ANALOG_TXRF12_ATBSEL2G_LSB                                                                       14
+#define PHY_ANALOG_TXRF12_ATBSEL2G_MASK                                                              0x0001c000
+#define PHY_ANALOG_TXRF12_ATBSEL2G_GET(x)                                            (((x) & 0x0001c000) >> 14)
+#define PHY_ANALOG_TXRF12_ATBSEL2G_SET(x)                                            (((x) << 14) & 0x0001c000)
+#define PHY_ANALOG_TXRF12_PWD_IRSPARE_MSB                                                                    19
+#define PHY_ANALOG_TXRF12_PWD_IRSPARE_LSB                                                                    17
+#define PHY_ANALOG_TXRF12_PWD_IRSPARE_MASK                                                           0x000e0000
+#define PHY_ANALOG_TXRF12_PWD_IRSPARE_GET(x)                                         (((x) & 0x000e0000) >> 17)
+#define PHY_ANALOG_TXRF12_PWD_IRSPARE_SET(x)                                         (((x) << 17) & 0x000e0000)
+#define PHY_ANALOG_TXRF12_PWD_IR25TEMPSEN_MSB                                                                22
+#define PHY_ANALOG_TXRF12_PWD_IR25TEMPSEN_LSB                                                                20
+#define PHY_ANALOG_TXRF12_PWD_IR25TEMPSEN_MASK                                                       0x00700000
+#define PHY_ANALOG_TXRF12_PWD_IR25TEMPSEN_GET(x)                                     (((x) & 0x00700000) >> 20)
+#define PHY_ANALOG_TXRF12_PWD_IR25TEMPSEN_SET(x)                                     (((x) << 20) & 0x00700000)
+#define PHY_ANALOG_TXRF12_PWD_IR25PA5G2_MSB                                                                  25
+#define PHY_ANALOG_TXRF12_PWD_IR25PA5G2_LSB                                                                  23
+#define PHY_ANALOG_TXRF12_PWD_IR25PA5G2_MASK                                                         0x03800000
+#define PHY_ANALOG_TXRF12_PWD_IR25PA5G2_GET(x)                                       (((x) & 0x03800000) >> 23)
+#define PHY_ANALOG_TXRF12_PWD_IR25PA5G2_SET(x)                                       (((x) << 23) & 0x03800000)
+#define PHY_ANALOG_TXRF12_PWD_IR25PA5G1_MSB                                                                  28
+#define PHY_ANALOG_TXRF12_PWD_IR25PA5G1_LSB                                                                  26
+#define PHY_ANALOG_TXRF12_PWD_IR25PA5G1_MASK                                                         0x1c000000
+#define PHY_ANALOG_TXRF12_PWD_IR25PA5G1_GET(x)                                       (((x) & 0x1c000000) >> 26)
+#define PHY_ANALOG_TXRF12_PWD_IR25PA5G1_SET(x)                                       (((x) << 26) & 0x1c000000)
+#define PHY_ANALOG_TXRF12_PWD_IR25MIXBIAS5G_MSB                                                              31
+#define PHY_ANALOG_TXRF12_PWD_IR25MIXBIAS5G_LSB                                                              29
+#define PHY_ANALOG_TXRF12_PWD_IR25MIXBIAS5G_MASK                                                     0xe0000000
+#define PHY_ANALOG_TXRF12_PWD_IR25MIXBIAS5G_GET(x)                                   (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_TXRF12_PWD_IR25MIXBIAS5G_SET(x)                                   (((x) << 29) & 0xe0000000)
+
+/* macros for SYNTH1 */
+#define PHY_ANALOG_SYNTH1_ADDRESS                                                                    0x00000080
+#define PHY_ANALOG_SYNTH1_OFFSET                                                                     0x00000080
+#define PHY_ANALOG_SYNTH1_SEL_VCMONABUS_MSB                                                                   2
+#define PHY_ANALOG_SYNTH1_SEL_VCMONABUS_LSB                                                                   0
+#define PHY_ANALOG_SYNTH1_SEL_VCMONABUS_MASK                                                         0x00000007
+#define PHY_ANALOG_SYNTH1_SEL_VCMONABUS_GET(x)                                        (((x) & 0x00000007) >> 0)
+#define PHY_ANALOG_SYNTH1_SEL_VCMONABUS_SET(x)                                        (((x) << 0) & 0x00000007)
+#define PHY_ANALOG_SYNTH1_SEL_VCOABUS_MSB                                                                     5
+#define PHY_ANALOG_SYNTH1_SEL_VCOABUS_LSB                                                                     3
+#define PHY_ANALOG_SYNTH1_SEL_VCOABUS_MASK                                                           0x00000038
+#define PHY_ANALOG_SYNTH1_SEL_VCOABUS_GET(x)                                          (((x) & 0x00000038) >> 3)
+#define PHY_ANALOG_SYNTH1_SEL_VCOABUS_SET(x)                                          (((x) << 3) & 0x00000038)
+#define PHY_ANALOG_SYNTH1_MONITOR_SYNTHLOCKVCOK_MSB                                                           6
+#define PHY_ANALOG_SYNTH1_MONITOR_SYNTHLOCKVCOK_LSB                                                           6
+#define PHY_ANALOG_SYNTH1_MONITOR_SYNTHLOCKVCOK_MASK                                                 0x00000040
+#define PHY_ANALOG_SYNTH1_MONITOR_SYNTHLOCKVCOK_GET(x)                                (((x) & 0x00000040) >> 6)
+#define PHY_ANALOG_SYNTH1_MONITOR_SYNTHLOCKVCOK_SET(x)                                (((x) << 6) & 0x00000040)
+#define PHY_ANALOG_SYNTH1_MONITOR_VC2LOW_MSB                                                                  7
+#define PHY_ANALOG_SYNTH1_MONITOR_VC2LOW_LSB                                                                  7
+#define PHY_ANALOG_SYNTH1_MONITOR_VC2LOW_MASK                                                        0x00000080
+#define PHY_ANALOG_SYNTH1_MONITOR_VC2LOW_GET(x)                                       (((x) & 0x00000080) >> 7)
+#define PHY_ANALOG_SYNTH1_MONITOR_VC2LOW_SET(x)                                       (((x) << 7) & 0x00000080)
+#define PHY_ANALOG_SYNTH1_MONITOR_VC2HIGH_MSB                                                                 8
+#define PHY_ANALOG_SYNTH1_MONITOR_VC2HIGH_LSB                                                                 8
+#define PHY_ANALOG_SYNTH1_MONITOR_VC2HIGH_MASK                                                       0x00000100
+#define PHY_ANALOG_SYNTH1_MONITOR_VC2HIGH_GET(x)                                      (((x) & 0x00000100) >> 8)
+#define PHY_ANALOG_SYNTH1_MONITOR_VC2HIGH_SET(x)                                      (((x) << 8) & 0x00000100)
+#define PHY_ANALOG_SYNTH1_MONITOR_FB_DIV2_MSB                                                                 9
+#define PHY_ANALOG_SYNTH1_MONITOR_FB_DIV2_LSB                                                                 9
+#define PHY_ANALOG_SYNTH1_MONITOR_FB_DIV2_MASK                                                       0x00000200
+#define PHY_ANALOG_SYNTH1_MONITOR_FB_DIV2_GET(x)                                      (((x) & 0x00000200) >> 9)
+#define PHY_ANALOG_SYNTH1_MONITOR_FB_DIV2_SET(x)                                      (((x) << 9) & 0x00000200)
+#define PHY_ANALOG_SYNTH1_MONITOR_REF_MSB                                                                    10
+#define PHY_ANALOG_SYNTH1_MONITOR_REF_LSB                                                                    10
+#define PHY_ANALOG_SYNTH1_MONITOR_REF_MASK                                                           0x00000400
+#define PHY_ANALOG_SYNTH1_MONITOR_REF_GET(x)                                         (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_SYNTH1_MONITOR_REF_SET(x)                                         (((x) << 10) & 0x00000400)
+#define PHY_ANALOG_SYNTH1_MONITOR_FB_MSB                                                                     11
+#define PHY_ANALOG_SYNTH1_MONITOR_FB_LSB                                                                     11
+#define PHY_ANALOG_SYNTH1_MONITOR_FB_MASK                                                            0x00000800
+#define PHY_ANALOG_SYNTH1_MONITOR_FB_GET(x)                                          (((x) & 0x00000800) >> 11)
+#define PHY_ANALOG_SYNTH1_MONITOR_FB_SET(x)                                          (((x) << 11) & 0x00000800)
+#define PHY_ANALOG_SYNTH1_SEVENBITVCOCAP_MSB                                                                 12
+#define PHY_ANALOG_SYNTH1_SEVENBITVCOCAP_LSB                                                                 12
+#define PHY_ANALOG_SYNTH1_SEVENBITVCOCAP_MASK                                                        0x00001000
+#define PHY_ANALOG_SYNTH1_SEVENBITVCOCAP_GET(x)                                      (((x) & 0x00001000) >> 12)
+#define PHY_ANALOG_SYNTH1_SEVENBITVCOCAP_SET(x)                                      (((x) << 12) & 0x00001000)
+#define PHY_ANALOG_SYNTH1_PWUP_PD_MSB                                                                        15
+#define PHY_ANALOG_SYNTH1_PWUP_PD_LSB                                                                        13
+#define PHY_ANALOG_SYNTH1_PWUP_PD_MASK                                                               0x0000e000
+#define PHY_ANALOG_SYNTH1_PWUP_PD_GET(x)                                             (((x) & 0x0000e000) >> 13)
+#define PHY_ANALOG_SYNTH1_PWUP_PD_SET(x)                                             (((x) << 13) & 0x0000e000)
+#define PHY_ANALOG_SYNTH1_PWD_VCOBUF_MSB                                                                     16
+#define PHY_ANALOG_SYNTH1_PWD_VCOBUF_LSB                                                                     16
+#define PHY_ANALOG_SYNTH1_PWD_VCOBUF_MASK                                                            0x00010000
+#define PHY_ANALOG_SYNTH1_PWD_VCOBUF_GET(x)                                          (((x) & 0x00010000) >> 16)
+#define PHY_ANALOG_SYNTH1_PWD_VCOBUF_SET(x)                                          (((x) << 16) & 0x00010000)
+#define PHY_ANALOG_SYNTH1_VCOBUFGAIN_MSB                                                                     18
+#define PHY_ANALOG_SYNTH1_VCOBUFGAIN_LSB                                                                     17
+#define PHY_ANALOG_SYNTH1_VCOBUFGAIN_MASK                                                            0x00060000
+#define PHY_ANALOG_SYNTH1_VCOBUFGAIN_GET(x)                                          (((x) & 0x00060000) >> 17)
+#define PHY_ANALOG_SYNTH1_VCOBUFGAIN_SET(x)                                          (((x) << 17) & 0x00060000)
+#define PHY_ANALOG_SYNTH1_VCOREGLEVEL_MSB                                                                    20
+#define PHY_ANALOG_SYNTH1_VCOREGLEVEL_LSB                                                                    19
+#define PHY_ANALOG_SYNTH1_VCOREGLEVEL_MASK                                                           0x00180000
+#define PHY_ANALOG_SYNTH1_VCOREGLEVEL_GET(x)                                         (((x) & 0x00180000) >> 19)
+#define PHY_ANALOG_SYNTH1_VCOREGLEVEL_SET(x)                                         (((x) << 19) & 0x00180000)
+#define PHY_ANALOG_SYNTH1_VCOREGBYPASS_MSB                                                                   21
+#define PHY_ANALOG_SYNTH1_VCOREGBYPASS_LSB                                                                   21
+#define PHY_ANALOG_SYNTH1_VCOREGBYPASS_MASK                                                          0x00200000
+#define PHY_ANALOG_SYNTH1_VCOREGBYPASS_GET(x)                                        (((x) & 0x00200000) >> 21)
+#define PHY_ANALOG_SYNTH1_VCOREGBYPASS_SET(x)                                        (((x) << 21) & 0x00200000)
+#define PHY_ANALOG_SYNTH1_PWUP_LOREF_MSB                                                                     22
+#define PHY_ANALOG_SYNTH1_PWUP_LOREF_LSB                                                                     22
+#define PHY_ANALOG_SYNTH1_PWUP_LOREF_MASK                                                            0x00400000
+#define PHY_ANALOG_SYNTH1_PWUP_LOREF_GET(x)                                          (((x) & 0x00400000) >> 22)
+#define PHY_ANALOG_SYNTH1_PWUP_LOREF_SET(x)                                          (((x) << 22) & 0x00400000)
+#define PHY_ANALOG_SYNTH1_PWD_LOMIX_MSB                                                                      23
+#define PHY_ANALOG_SYNTH1_PWD_LOMIX_LSB                                                                      23
+#define PHY_ANALOG_SYNTH1_PWD_LOMIX_MASK                                                             0x00800000
+#define PHY_ANALOG_SYNTH1_PWD_LOMIX_GET(x)                                           (((x) & 0x00800000) >> 23)
+#define PHY_ANALOG_SYNTH1_PWD_LOMIX_SET(x)                                           (((x) << 23) & 0x00800000)
+#define PHY_ANALOG_SYNTH1_PWD_LODIV_MSB                                                                      24
+#define PHY_ANALOG_SYNTH1_PWD_LODIV_LSB                                                                      24
+#define PHY_ANALOG_SYNTH1_PWD_LODIV_MASK                                                             0x01000000
+#define PHY_ANALOG_SYNTH1_PWD_LODIV_GET(x)                                           (((x) & 0x01000000) >> 24)
+#define PHY_ANALOG_SYNTH1_PWD_LODIV_SET(x)                                           (((x) << 24) & 0x01000000)
+#define PHY_ANALOG_SYNTH1_PWD_LOBUF5G_MSB                                                                    25
+#define PHY_ANALOG_SYNTH1_PWD_LOBUF5G_LSB                                                                    25
+#define PHY_ANALOG_SYNTH1_PWD_LOBUF5G_MASK                                                           0x02000000
+#define PHY_ANALOG_SYNTH1_PWD_LOBUF5G_GET(x)                                         (((x) & 0x02000000) >> 25)
+#define PHY_ANALOG_SYNTH1_PWD_LOBUF5G_SET(x)                                         (((x) << 25) & 0x02000000)
+#define PHY_ANALOG_SYNTH1_PWD_LOBUF2G_MSB                                                                    26
+#define PHY_ANALOG_SYNTH1_PWD_LOBUF2G_LSB                                                                    26
+#define PHY_ANALOG_SYNTH1_PWD_LOBUF2G_MASK                                                           0x04000000
+#define PHY_ANALOG_SYNTH1_PWD_LOBUF2G_GET(x)                                         (((x) & 0x04000000) >> 26)
+#define PHY_ANALOG_SYNTH1_PWD_LOBUF2G_SET(x)                                         (((x) << 26) & 0x04000000)
+#define PHY_ANALOG_SYNTH1_PWD_PRESC_MSB                                                                      27
+#define PHY_ANALOG_SYNTH1_PWD_PRESC_LSB                                                                      27
+#define PHY_ANALOG_SYNTH1_PWD_PRESC_MASK                                                             0x08000000
+#define PHY_ANALOG_SYNTH1_PWD_PRESC_GET(x)                                           (((x) & 0x08000000) >> 27)
+#define PHY_ANALOG_SYNTH1_PWD_PRESC_SET(x)                                           (((x) << 27) & 0x08000000)
+#define PHY_ANALOG_SYNTH1_PWD_VCO_MSB                                                                        28
+#define PHY_ANALOG_SYNTH1_PWD_VCO_LSB                                                                        28
+#define PHY_ANALOG_SYNTH1_PWD_VCO_MASK                                                               0x10000000
+#define PHY_ANALOG_SYNTH1_PWD_VCO_GET(x)                                             (((x) & 0x10000000) >> 28)
+#define PHY_ANALOG_SYNTH1_PWD_VCO_SET(x)                                             (((x) << 28) & 0x10000000)
+#define PHY_ANALOG_SYNTH1_PWD_VCMON_MSB                                                                      29
+#define PHY_ANALOG_SYNTH1_PWD_VCMON_LSB                                                                      29
+#define PHY_ANALOG_SYNTH1_PWD_VCMON_MASK                                                             0x20000000
+#define PHY_ANALOG_SYNTH1_PWD_VCMON_GET(x)                                           (((x) & 0x20000000) >> 29)
+#define PHY_ANALOG_SYNTH1_PWD_VCMON_SET(x)                                           (((x) << 29) & 0x20000000)
+#define PHY_ANALOG_SYNTH1_PWD_CP_MSB                                                                         30
+#define PHY_ANALOG_SYNTH1_PWD_CP_LSB                                                                         30
+#define PHY_ANALOG_SYNTH1_PWD_CP_MASK                                                                0x40000000
+#define PHY_ANALOG_SYNTH1_PWD_CP_GET(x)                                              (((x) & 0x40000000) >> 30)
+#define PHY_ANALOG_SYNTH1_PWD_CP_SET(x)                                              (((x) << 30) & 0x40000000)
+#define PHY_ANALOG_SYNTH1_PWD_BIAS_MSB                                                                       31
+#define PHY_ANALOG_SYNTH1_PWD_BIAS_LSB                                                                       31
+#define PHY_ANALOG_SYNTH1_PWD_BIAS_MASK                                                              0x80000000
+#define PHY_ANALOG_SYNTH1_PWD_BIAS_GET(x)                                            (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_SYNTH1_PWD_BIAS_SET(x)                                            (((x) << 31) & 0x80000000)
+
+/* macros for SYNTH2 */
+#define PHY_ANALOG_SYNTH2_ADDRESS                                                                    0x00000084
+#define PHY_ANALOG_SYNTH2_OFFSET                                                                     0x00000084
+#define PHY_ANALOG_SYNTH2_CAPRANGE3_MSB                                                                       3
+#define PHY_ANALOG_SYNTH2_CAPRANGE3_LSB                                                                       0
+#define PHY_ANALOG_SYNTH2_CAPRANGE3_MASK                                                             0x0000000f
+#define PHY_ANALOG_SYNTH2_CAPRANGE3_GET(x)                                            (((x) & 0x0000000f) >> 0)
+#define PHY_ANALOG_SYNTH2_CAPRANGE3_SET(x)                                            (((x) << 0) & 0x0000000f)
+#define PHY_ANALOG_SYNTH2_CAPRANGE2_MSB                                                                       7
+#define PHY_ANALOG_SYNTH2_CAPRANGE2_LSB                                                                       4
+#define PHY_ANALOG_SYNTH2_CAPRANGE2_MASK                                                             0x000000f0
+#define PHY_ANALOG_SYNTH2_CAPRANGE2_GET(x)                                            (((x) & 0x000000f0) >> 4)
+#define PHY_ANALOG_SYNTH2_CAPRANGE2_SET(x)                                            (((x) << 4) & 0x000000f0)
+#define PHY_ANALOG_SYNTH2_CAPRANGE1_MSB                                                                      11
+#define PHY_ANALOG_SYNTH2_CAPRANGE1_LSB                                                                       8
+#define PHY_ANALOG_SYNTH2_CAPRANGE1_MASK                                                             0x00000f00
+#define PHY_ANALOG_SYNTH2_CAPRANGE1_GET(x)                                            (((x) & 0x00000f00) >> 8)
+#define PHY_ANALOG_SYNTH2_CAPRANGE1_SET(x)                                            (((x) << 8) & 0x00000f00)
+#define PHY_ANALOG_SYNTH2_LOOPLEAKCUR_INTN_MSB                                                               15
+#define PHY_ANALOG_SYNTH2_LOOPLEAKCUR_INTN_LSB                                                               12
+#define PHY_ANALOG_SYNTH2_LOOPLEAKCUR_INTN_MASK                                                      0x0000f000
+#define PHY_ANALOG_SYNTH2_LOOPLEAKCUR_INTN_GET(x)                                    (((x) & 0x0000f000) >> 12)
+#define PHY_ANALOG_SYNTH2_LOOPLEAKCUR_INTN_SET(x)                                    (((x) << 12) & 0x0000f000)
+#define PHY_ANALOG_SYNTH2_CPLOWLK_INTN_MSB                                                                   16
+#define PHY_ANALOG_SYNTH2_CPLOWLK_INTN_LSB                                                                   16
+#define PHY_ANALOG_SYNTH2_CPLOWLK_INTN_MASK                                                          0x00010000
+#define PHY_ANALOG_SYNTH2_CPLOWLK_INTN_GET(x)                                        (((x) & 0x00010000) >> 16)
+#define PHY_ANALOG_SYNTH2_CPLOWLK_INTN_SET(x)                                        (((x) << 16) & 0x00010000)
+#define PHY_ANALOG_SYNTH2_CPSTEERING_EN_INTN_MSB                                                             17
+#define PHY_ANALOG_SYNTH2_CPSTEERING_EN_INTN_LSB                                                             17
+#define PHY_ANALOG_SYNTH2_CPSTEERING_EN_INTN_MASK                                                    0x00020000
+#define PHY_ANALOG_SYNTH2_CPSTEERING_EN_INTN_GET(x)                                  (((x) & 0x00020000) >> 17)
+#define PHY_ANALOG_SYNTH2_CPSTEERING_EN_INTN_SET(x)                                  (((x) << 17) & 0x00020000)
+#define PHY_ANALOG_SYNTH2_CPBIAS_INTN_MSB                                                                    19
+#define PHY_ANALOG_SYNTH2_CPBIAS_INTN_LSB                                                                    18
+#define PHY_ANALOG_SYNTH2_CPBIAS_INTN_MASK                                                           0x000c0000
+#define PHY_ANALOG_SYNTH2_CPBIAS_INTN_GET(x)                                         (((x) & 0x000c0000) >> 18)
+#define PHY_ANALOG_SYNTH2_CPBIAS_INTN_SET(x)                                         (((x) << 18) & 0x000c0000)
+#define PHY_ANALOG_SYNTH2_VC_LOW_REF_MSB                                                                     22
+#define PHY_ANALOG_SYNTH2_VC_LOW_REF_LSB                                                                     20
+#define PHY_ANALOG_SYNTH2_VC_LOW_REF_MASK                                                            0x00700000
+#define PHY_ANALOG_SYNTH2_VC_LOW_REF_GET(x)                                          (((x) & 0x00700000) >> 20)
+#define PHY_ANALOG_SYNTH2_VC_LOW_REF_SET(x)                                          (((x) << 20) & 0x00700000)
+#define PHY_ANALOG_SYNTH2_VC_MID_REF_MSB                                                                     25
+#define PHY_ANALOG_SYNTH2_VC_MID_REF_LSB                                                                     23
+#define PHY_ANALOG_SYNTH2_VC_MID_REF_MASK                                                            0x03800000
+#define PHY_ANALOG_SYNTH2_VC_MID_REF_GET(x)                                          (((x) & 0x03800000) >> 23)
+#define PHY_ANALOG_SYNTH2_VC_MID_REF_SET(x)                                          (((x) << 23) & 0x03800000)
+#define PHY_ANALOG_SYNTH2_VC_HI_REF_MSB                                                                      28
+#define PHY_ANALOG_SYNTH2_VC_HI_REF_LSB                                                                      26
+#define PHY_ANALOG_SYNTH2_VC_HI_REF_MASK                                                             0x1c000000
+#define PHY_ANALOG_SYNTH2_VC_HI_REF_GET(x)                                           (((x) & 0x1c000000) >> 26)
+#define PHY_ANALOG_SYNTH2_VC_HI_REF_SET(x)                                           (((x) << 26) & 0x1c000000)
+#define PHY_ANALOG_SYNTH2_VC_CAL_REF_MSB                                                                     31
+#define PHY_ANALOG_SYNTH2_VC_CAL_REF_LSB                                                                     29
+#define PHY_ANALOG_SYNTH2_VC_CAL_REF_MASK                                                            0xe0000000
+#define PHY_ANALOG_SYNTH2_VC_CAL_REF_GET(x)                                          (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_SYNTH2_VC_CAL_REF_SET(x)                                          (((x) << 29) & 0xe0000000)
+
+/* macros for SYNTH3 */
+#define PHY_ANALOG_SYNTH3_ADDRESS                                                                    0x00000088
+#define PHY_ANALOG_SYNTH3_OFFSET                                                                     0x00000088
+#define PHY_ANALOG_SYNTH3_WAIT_VC_CHECK_MSB                                                                   5
+#define PHY_ANALOG_SYNTH3_WAIT_VC_CHECK_LSB                                                                   0
+#define PHY_ANALOG_SYNTH3_WAIT_VC_CHECK_MASK                                                         0x0000003f
+#define PHY_ANALOG_SYNTH3_WAIT_VC_CHECK_GET(x)                                        (((x) & 0x0000003f) >> 0)
+#define PHY_ANALOG_SYNTH3_WAIT_VC_CHECK_SET(x)                                        (((x) << 0) & 0x0000003f)
+#define PHY_ANALOG_SYNTH3_WAIT_CAL_LIN_MSB                                                                   11
+#define PHY_ANALOG_SYNTH3_WAIT_CAL_LIN_LSB                                                                    6
+#define PHY_ANALOG_SYNTH3_WAIT_CAL_LIN_MASK                                                          0x00000fc0
+#define PHY_ANALOG_SYNTH3_WAIT_CAL_LIN_GET(x)                                         (((x) & 0x00000fc0) >> 6)
+#define PHY_ANALOG_SYNTH3_WAIT_CAL_LIN_SET(x)                                         (((x) << 6) & 0x00000fc0)
+#define PHY_ANALOG_SYNTH3_WAIT_CAL_BIN_MSB                                                                   17
+#define PHY_ANALOG_SYNTH3_WAIT_CAL_BIN_LSB                                                                   12
+#define PHY_ANALOG_SYNTH3_WAIT_CAL_BIN_MASK                                                          0x0003f000
+#define PHY_ANALOG_SYNTH3_WAIT_CAL_BIN_GET(x)                                        (((x) & 0x0003f000) >> 12)
+#define PHY_ANALOG_SYNTH3_WAIT_CAL_BIN_SET(x)                                        (((x) << 12) & 0x0003f000)
+#define PHY_ANALOG_SYNTH3_WAIT_PWRUP_MSB                                                                     23
+#define PHY_ANALOG_SYNTH3_WAIT_PWRUP_LSB                                                                     18
+#define PHY_ANALOG_SYNTH3_WAIT_PWRUP_MASK                                                            0x00fc0000
+#define PHY_ANALOG_SYNTH3_WAIT_PWRUP_GET(x)                                          (((x) & 0x00fc0000) >> 18)
+#define PHY_ANALOG_SYNTH3_WAIT_PWRUP_SET(x)                                          (((x) << 18) & 0x00fc0000)
+#define PHY_ANALOG_SYNTH3_WAIT_SHORTR_PWRUP_MSB                                                              29
+#define PHY_ANALOG_SYNTH3_WAIT_SHORTR_PWRUP_LSB                                                              24
+#define PHY_ANALOG_SYNTH3_WAIT_SHORTR_PWRUP_MASK                                                     0x3f000000
+#define PHY_ANALOG_SYNTH3_WAIT_SHORTR_PWRUP_GET(x)                                   (((x) & 0x3f000000) >> 24)
+#define PHY_ANALOG_SYNTH3_WAIT_SHORTR_PWRUP_SET(x)                                   (((x) << 24) & 0x3f000000)
+#define PHY_ANALOG_SYNTH3_SEL_CLK_DIV2_MSB                                                                   30
+#define PHY_ANALOG_SYNTH3_SEL_CLK_DIV2_LSB                                                                   30
+#define PHY_ANALOG_SYNTH3_SEL_CLK_DIV2_MASK                                                          0x40000000
+#define PHY_ANALOG_SYNTH3_SEL_CLK_DIV2_GET(x)                                        (((x) & 0x40000000) >> 30)
+#define PHY_ANALOG_SYNTH3_SEL_CLK_DIV2_SET(x)                                        (((x) << 30) & 0x40000000)
+#define PHY_ANALOG_SYNTH3_DIS_CLK_XTAL_MSB                                                                   31
+#define PHY_ANALOG_SYNTH3_DIS_CLK_XTAL_LSB                                                                   31
+#define PHY_ANALOG_SYNTH3_DIS_CLK_XTAL_MASK                                                          0x80000000
+#define PHY_ANALOG_SYNTH3_DIS_CLK_XTAL_GET(x)                                        (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_SYNTH3_DIS_CLK_XTAL_SET(x)                                        (((x) << 31) & 0x80000000)
+
+/* macros for SYNTH4 */
+#define PHY_ANALOG_SYNTH4_ADDRESS                                                                    0x0000008c
+#define PHY_ANALOG_SYNTH4_OFFSET                                                                     0x0000008c
+#define PHY_ANALOG_SYNTH4_PS_SINGLE_PULSE_MSB                                                                 0
+#define PHY_ANALOG_SYNTH4_PS_SINGLE_PULSE_LSB                                                                 0
+#define PHY_ANALOG_SYNTH4_PS_SINGLE_PULSE_MASK                                                       0x00000001
+#define PHY_ANALOG_SYNTH4_PS_SINGLE_PULSE_GET(x)                                      (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_SYNTH4_PS_SINGLE_PULSE_SET(x)                                      (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_SYNTH4_LONGSHIFTSEL_MSB                                                                    1
+#define PHY_ANALOG_SYNTH4_LONGSHIFTSEL_LSB                                                                    1
+#define PHY_ANALOG_SYNTH4_LONGSHIFTSEL_MASK                                                          0x00000002
+#define PHY_ANALOG_SYNTH4_LONGSHIFTSEL_GET(x)                                         (((x) & 0x00000002) >> 1)
+#define PHY_ANALOG_SYNTH4_LONGSHIFTSEL_SET(x)                                         (((x) << 1) & 0x00000002)
+#define PHY_ANALOG_SYNTH4_LOBUF5GTUNE_OVR_MSB                                                                 3
+#define PHY_ANALOG_SYNTH4_LOBUF5GTUNE_OVR_LSB                                                                 2
+#define PHY_ANALOG_SYNTH4_LOBUF5GTUNE_OVR_MASK                                                       0x0000000c
+#define PHY_ANALOG_SYNTH4_LOBUF5GTUNE_OVR_GET(x)                                      (((x) & 0x0000000c) >> 2)
+#define PHY_ANALOG_SYNTH4_LOBUF5GTUNE_OVR_SET(x)                                      (((x) << 2) & 0x0000000c)
+#define PHY_ANALOG_SYNTH4_FORCE_LOBUF5GTUNE_MSB                                                               4
+#define PHY_ANALOG_SYNTH4_FORCE_LOBUF5GTUNE_LSB                                                               4
+#define PHY_ANALOG_SYNTH4_FORCE_LOBUF5GTUNE_MASK                                                     0x00000010
+#define PHY_ANALOG_SYNTH4_FORCE_LOBUF5GTUNE_GET(x)                                    (((x) & 0x00000010) >> 4)
+#define PHY_ANALOG_SYNTH4_FORCE_LOBUF5GTUNE_SET(x)                                    (((x) << 4) & 0x00000010)
+#define PHY_ANALOG_SYNTH4_PSCOUNT_FBSEL_MSB                                                                   5
+#define PHY_ANALOG_SYNTH4_PSCOUNT_FBSEL_LSB                                                                   5
+#define PHY_ANALOG_SYNTH4_PSCOUNT_FBSEL_MASK                                                         0x00000020
+#define PHY_ANALOG_SYNTH4_PSCOUNT_FBSEL_GET(x)                                        (((x) & 0x00000020) >> 5)
+#define PHY_ANALOG_SYNTH4_PSCOUNT_FBSEL_SET(x)                                        (((x) << 5) & 0x00000020)
+#define PHY_ANALOG_SYNTH4_SDM_DITHER1_MSB                                                                     7
+#define PHY_ANALOG_SYNTH4_SDM_DITHER1_LSB                                                                     6
+#define PHY_ANALOG_SYNTH4_SDM_DITHER1_MASK                                                           0x000000c0
+#define PHY_ANALOG_SYNTH4_SDM_DITHER1_GET(x)                                          (((x) & 0x000000c0) >> 6)
+#define PHY_ANALOG_SYNTH4_SDM_DITHER1_SET(x)                                          (((x) << 6) & 0x000000c0)
+#define PHY_ANALOG_SYNTH4_SDM_MODE_MSB                                                                        8
+#define PHY_ANALOG_SYNTH4_SDM_MODE_LSB                                                                        8
+#define PHY_ANALOG_SYNTH4_SDM_MODE_MASK                                                              0x00000100
+#define PHY_ANALOG_SYNTH4_SDM_MODE_GET(x)                                             (((x) & 0x00000100) >> 8)
+#define PHY_ANALOG_SYNTH4_SDM_MODE_SET(x)                                             (((x) << 8) & 0x00000100)
+#define PHY_ANALOG_SYNTH4_SDM_DISABLE_MSB                                                                     9
+#define PHY_ANALOG_SYNTH4_SDM_DISABLE_LSB                                                                     9
+#define PHY_ANALOG_SYNTH4_SDM_DISABLE_MASK                                                           0x00000200
+#define PHY_ANALOG_SYNTH4_SDM_DISABLE_GET(x)                                          (((x) & 0x00000200) >> 9)
+#define PHY_ANALOG_SYNTH4_SDM_DISABLE_SET(x)                                          (((x) << 9) & 0x00000200)
+#define PHY_ANALOG_SYNTH4_RESET_PRESC_MSB                                                                    10
+#define PHY_ANALOG_SYNTH4_RESET_PRESC_LSB                                                                    10
+#define PHY_ANALOG_SYNTH4_RESET_PRESC_MASK                                                           0x00000400
+#define PHY_ANALOG_SYNTH4_RESET_PRESC_GET(x)                                         (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_SYNTH4_RESET_PRESC_SET(x)                                         (((x) << 10) & 0x00000400)
+#define PHY_ANALOG_SYNTH4_PRESCSEL_MSB                                                                       12
+#define PHY_ANALOG_SYNTH4_PRESCSEL_LSB                                                                       11
+#define PHY_ANALOG_SYNTH4_PRESCSEL_MASK                                                              0x00001800
+#define PHY_ANALOG_SYNTH4_PRESCSEL_GET(x)                                            (((x) & 0x00001800) >> 11)
+#define PHY_ANALOG_SYNTH4_PRESCSEL_SET(x)                                            (((x) << 11) & 0x00001800)
+#define PHY_ANALOG_SYNTH4_PFD_DISABLE_MSB                                                                    13
+#define PHY_ANALOG_SYNTH4_PFD_DISABLE_LSB                                                                    13
+#define PHY_ANALOG_SYNTH4_PFD_DISABLE_MASK                                                           0x00002000
+#define PHY_ANALOG_SYNTH4_PFD_DISABLE_GET(x)                                         (((x) & 0x00002000) >> 13)
+#define PHY_ANALOG_SYNTH4_PFD_DISABLE_SET(x)                                         (((x) << 13) & 0x00002000)
+#define PHY_ANALOG_SYNTH4_PFDDELAY_FRACN_MSB                                                                 14
+#define PHY_ANALOG_SYNTH4_PFDDELAY_FRACN_LSB                                                                 14
+#define PHY_ANALOG_SYNTH4_PFDDELAY_FRACN_MASK                                                        0x00004000
+#define PHY_ANALOG_SYNTH4_PFDDELAY_FRACN_GET(x)                                      (((x) & 0x00004000) >> 14)
+#define PHY_ANALOG_SYNTH4_PFDDELAY_FRACN_SET(x)                                      (((x) << 14) & 0x00004000)
+#define PHY_ANALOG_SYNTH4_FORCE_LO_ON_MSB                                                                    15
+#define PHY_ANALOG_SYNTH4_FORCE_LO_ON_LSB                                                                    15
+#define PHY_ANALOG_SYNTH4_FORCE_LO_ON_MASK                                                           0x00008000
+#define PHY_ANALOG_SYNTH4_FORCE_LO_ON_GET(x)                                         (((x) & 0x00008000) >> 15)
+#define PHY_ANALOG_SYNTH4_FORCE_LO_ON_SET(x)                                         (((x) << 15) & 0x00008000)
+#define PHY_ANALOG_SYNTH4_CLKXTAL_EDGE_SEL_MSB                                                               16
+#define PHY_ANALOG_SYNTH4_CLKXTAL_EDGE_SEL_LSB                                                               16
+#define PHY_ANALOG_SYNTH4_CLKXTAL_EDGE_SEL_MASK                                                      0x00010000
+#define PHY_ANALOG_SYNTH4_CLKXTAL_EDGE_SEL_GET(x)                                    (((x) & 0x00010000) >> 16)
+#define PHY_ANALOG_SYNTH4_CLKXTAL_EDGE_SEL_SET(x)                                    (((x) << 16) & 0x00010000)
+#define PHY_ANALOG_SYNTH4_VCOCAPPULLUP_MSB                                                                   17
+#define PHY_ANALOG_SYNTH4_VCOCAPPULLUP_LSB                                                                   17
+#define PHY_ANALOG_SYNTH4_VCOCAPPULLUP_MASK                                                          0x00020000
+#define PHY_ANALOG_SYNTH4_VCOCAPPULLUP_GET(x)                                        (((x) & 0x00020000) >> 17)
+#define PHY_ANALOG_SYNTH4_VCOCAPPULLUP_SET(x)                                        (((x) << 17) & 0x00020000)
+#define PHY_ANALOG_SYNTH4_VCOCAP_OVR_MSB                                                                     25
+#define PHY_ANALOG_SYNTH4_VCOCAP_OVR_LSB                                                                     18
+#define PHY_ANALOG_SYNTH4_VCOCAP_OVR_MASK                                                            0x03fc0000
+#define PHY_ANALOG_SYNTH4_VCOCAP_OVR_GET(x)                                          (((x) & 0x03fc0000) >> 18)
+#define PHY_ANALOG_SYNTH4_VCOCAP_OVR_SET(x)                                          (((x) << 18) & 0x03fc0000)
+#define PHY_ANALOG_SYNTH4_FORCE_VCOCAP_MSB                                                                   26
+#define PHY_ANALOG_SYNTH4_FORCE_VCOCAP_LSB                                                                   26
+#define PHY_ANALOG_SYNTH4_FORCE_VCOCAP_MASK                                                          0x04000000
+#define PHY_ANALOG_SYNTH4_FORCE_VCOCAP_GET(x)                                        (((x) & 0x04000000) >> 26)
+#define PHY_ANALOG_SYNTH4_FORCE_VCOCAP_SET(x)                                        (((x) << 26) & 0x04000000)
+#define PHY_ANALOG_SYNTH4_FORCE_PINVC_MSB                                                                    27
+#define PHY_ANALOG_SYNTH4_FORCE_PINVC_LSB                                                                    27
+#define PHY_ANALOG_SYNTH4_FORCE_PINVC_MASK                                                           0x08000000
+#define PHY_ANALOG_SYNTH4_FORCE_PINVC_GET(x)                                         (((x) & 0x08000000) >> 27)
+#define PHY_ANALOG_SYNTH4_FORCE_PINVC_SET(x)                                         (((x) << 27) & 0x08000000)
+#define PHY_ANALOG_SYNTH4_SHORTR_UNTIL_LOCKED_MSB                                                            28
+#define PHY_ANALOG_SYNTH4_SHORTR_UNTIL_LOCKED_LSB                                                            28
+#define PHY_ANALOG_SYNTH4_SHORTR_UNTIL_LOCKED_MASK                                                   0x10000000
+#define PHY_ANALOG_SYNTH4_SHORTR_UNTIL_LOCKED_GET(x)                                 (((x) & 0x10000000) >> 28)
+#define PHY_ANALOG_SYNTH4_SHORTR_UNTIL_LOCKED_SET(x)                                 (((x) << 28) & 0x10000000)
+#define PHY_ANALOG_SYNTH4_ALWAYS_SHORTR_MSB                                                                  29
+#define PHY_ANALOG_SYNTH4_ALWAYS_SHORTR_LSB                                                                  29
+#define PHY_ANALOG_SYNTH4_ALWAYS_SHORTR_MASK                                                         0x20000000
+#define PHY_ANALOG_SYNTH4_ALWAYS_SHORTR_GET(x)                                       (((x) & 0x20000000) >> 29)
+#define PHY_ANALOG_SYNTH4_ALWAYS_SHORTR_SET(x)                                       (((x) << 29) & 0x20000000)
+#define PHY_ANALOG_SYNTH4_DIS_LOSTVC_MSB                                                                     30
+#define PHY_ANALOG_SYNTH4_DIS_LOSTVC_LSB                                                                     30
+#define PHY_ANALOG_SYNTH4_DIS_LOSTVC_MASK                                                            0x40000000
+#define PHY_ANALOG_SYNTH4_DIS_LOSTVC_GET(x)                                          (((x) & 0x40000000) >> 30)
+#define PHY_ANALOG_SYNTH4_DIS_LOSTVC_SET(x)                                          (((x) << 30) & 0x40000000)
+#define PHY_ANALOG_SYNTH4_DIS_LIN_CAPSEARCH_MSB                                                              31
+#define PHY_ANALOG_SYNTH4_DIS_LIN_CAPSEARCH_LSB                                                              31
+#define PHY_ANALOG_SYNTH4_DIS_LIN_CAPSEARCH_MASK                                                     0x80000000
+#define PHY_ANALOG_SYNTH4_DIS_LIN_CAPSEARCH_GET(x)                                   (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_SYNTH4_DIS_LIN_CAPSEARCH_SET(x)                                   (((x) << 31) & 0x80000000)
+
+/* macros for SYNTH5 */
+#define PHY_ANALOG_SYNTH5_ADDRESS                                                                    0x00000090
+#define PHY_ANALOG_SYNTH5_OFFSET                                                                     0x00000090
+#define PHY_ANALOG_SYNTH5_VCOBIAS_MSB                                                                         1
+#define PHY_ANALOG_SYNTH5_VCOBIAS_LSB                                                                         0
+#define PHY_ANALOG_SYNTH5_VCOBIAS_MASK                                                               0x00000003
+#define PHY_ANALOG_SYNTH5_VCOBIAS_GET(x)                                              (((x) & 0x00000003) >> 0)
+#define PHY_ANALOG_SYNTH5_VCOBIAS_SET(x)                                              (((x) << 0) & 0x00000003)
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF5G50_MSB                                                                4
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF5G50_LSB                                                                2
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF5G50_MASK                                                      0x0000001c
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF5G50_GET(x)                                     (((x) & 0x0000001c) >> 2)
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF5G50_SET(x)                                     (((x) << 2) & 0x0000001c)
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF2G50_MSB                                                                7
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF2G50_LSB                                                                5
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF2G50_MASK                                                      0x000000e0
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF2G50_GET(x)                                     (((x) & 0x000000e0) >> 5)
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF2G50_SET(x)                                     (((x) << 5) & 0x000000e0)
+#define PHY_ANALOG_SYNTH5_PWDB_ICVCO25_MSB                                                                   10
+#define PHY_ANALOG_SYNTH5_PWDB_ICVCO25_LSB                                                                    8
+#define PHY_ANALOG_SYNTH5_PWDB_ICVCO25_MASK                                                          0x00000700
+#define PHY_ANALOG_SYNTH5_PWDB_ICVCO25_GET(x)                                         (((x) & 0x00000700) >> 8)
+#define PHY_ANALOG_SYNTH5_PWDB_ICVCO25_SET(x)                                         (((x) << 8) & 0x00000700)
+#define PHY_ANALOG_SYNTH5_PWDB_ICVCOREG25_MSB                                                                13
+#define PHY_ANALOG_SYNTH5_PWDB_ICVCOREG25_LSB                                                                11
+#define PHY_ANALOG_SYNTH5_PWDB_ICVCOREG25_MASK                                                       0x00003800
+#define PHY_ANALOG_SYNTH5_PWDB_ICVCOREG25_GET(x)                                     (((x) & 0x00003800) >> 11)
+#define PHY_ANALOG_SYNTH5_PWDB_ICVCOREG25_SET(x)                                     (((x) << 11) & 0x00003800)
+#define PHY_ANALOG_SYNTH5_PWDB_IRVCOREG50_MSB                                                                14
+#define PHY_ANALOG_SYNTH5_PWDB_IRVCOREG50_LSB                                                                14
+#define PHY_ANALOG_SYNTH5_PWDB_IRVCOREG50_MASK                                                       0x00004000
+#define PHY_ANALOG_SYNTH5_PWDB_IRVCOREG50_GET(x)                                     (((x) & 0x00004000) >> 14)
+#define PHY_ANALOG_SYNTH5_PWDB_IRVCOREG50_SET(x)                                     (((x) << 14) & 0x00004000)
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOMIX_MSB                                                                   17
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOMIX_LSB                                                                   15
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOMIX_MASK                                                          0x00038000
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOMIX_GET(x)                                        (((x) & 0x00038000) >> 15)
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOMIX_SET(x)                                        (((x) << 15) & 0x00038000)
+#define PHY_ANALOG_SYNTH5_PWDB_ICLODIV50_MSB                                                                 20
+#define PHY_ANALOG_SYNTH5_PWDB_ICLODIV50_LSB                                                                 18
+#define PHY_ANALOG_SYNTH5_PWDB_ICLODIV50_MASK                                                        0x001c0000
+#define PHY_ANALOG_SYNTH5_PWDB_ICLODIV50_GET(x)                                      (((x) & 0x001c0000) >> 18)
+#define PHY_ANALOG_SYNTH5_PWDB_ICLODIV50_SET(x)                                      (((x) << 18) & 0x001c0000)
+#define PHY_ANALOG_SYNTH5_PWDB_ICPRESC50_MSB                                                                 23
+#define PHY_ANALOG_SYNTH5_PWDB_ICPRESC50_LSB                                                                 21
+#define PHY_ANALOG_SYNTH5_PWDB_ICPRESC50_MASK                                                        0x00e00000
+#define PHY_ANALOG_SYNTH5_PWDB_ICPRESC50_GET(x)                                      (((x) & 0x00e00000) >> 21)
+#define PHY_ANALOG_SYNTH5_PWDB_ICPRESC50_SET(x)                                      (((x) << 21) & 0x00e00000)
+#define PHY_ANALOG_SYNTH5_PWDB_IRVCMON25_MSB                                                                 26
+#define PHY_ANALOG_SYNTH5_PWDB_IRVCMON25_LSB                                                                 24
+#define PHY_ANALOG_SYNTH5_PWDB_IRVCMON25_MASK                                                        0x07000000
+#define PHY_ANALOG_SYNTH5_PWDB_IRVCMON25_GET(x)                                      (((x) & 0x07000000) >> 24)
+#define PHY_ANALOG_SYNTH5_PWDB_IRVCMON25_SET(x)                                      (((x) << 24) & 0x07000000)
+#define PHY_ANALOG_SYNTH5_PWDB_IRPFDCP_MSB                                                                   29
+#define PHY_ANALOG_SYNTH5_PWDB_IRPFDCP_LSB                                                                   27
+#define PHY_ANALOG_SYNTH5_PWDB_IRPFDCP_MASK                                                          0x38000000
+#define PHY_ANALOG_SYNTH5_PWDB_IRPFDCP_GET(x)                                        (((x) & 0x38000000) >> 27)
+#define PHY_ANALOG_SYNTH5_PWDB_IRPFDCP_SET(x)                                        (((x) << 27) & 0x38000000)
+#define PHY_ANALOG_SYNTH5_SDM_DITHER2_MSB                                                                    31
+#define PHY_ANALOG_SYNTH5_SDM_DITHER2_LSB                                                                    30
+#define PHY_ANALOG_SYNTH5_SDM_DITHER2_MASK                                                           0xc0000000
+#define PHY_ANALOG_SYNTH5_SDM_DITHER2_GET(x)                                         (((x) & 0xc0000000) >> 30)
+#define PHY_ANALOG_SYNTH5_SDM_DITHER2_SET(x)                                         (((x) << 30) & 0xc0000000)
+
+/* macros for SYNTH6 */
+#define PHY_ANALOG_SYNTH6_ADDRESS                                                                    0x00000094
+#define PHY_ANALOG_SYNTH6_OFFSET                                                                     0x00000094
+#define PHY_ANALOG_SYNTH6_LOBUF5GTUNE_MSB                                                                     1
+#define PHY_ANALOG_SYNTH6_LOBUF5GTUNE_LSB                                                                     0
+#define PHY_ANALOG_SYNTH6_LOBUF5GTUNE_MASK                                                           0x00000003
+#define PHY_ANALOG_SYNTH6_LOBUF5GTUNE_GET(x)                                          (((x) & 0x00000003) >> 0)
+#define PHY_ANALOG_SYNTH6_LOOP_IP_MSB                                                                         8
+#define PHY_ANALOG_SYNTH6_LOOP_IP_LSB                                                                         2
+#define PHY_ANALOG_SYNTH6_LOOP_IP_MASK                                                               0x000001fc
+#define PHY_ANALOG_SYNTH6_LOOP_IP_GET(x)                                              (((x) & 0x000001fc) >> 2)
+#define PHY_ANALOG_SYNTH6_VC2LOW_MSB                                                                          9
+#define PHY_ANALOG_SYNTH6_VC2LOW_LSB                                                                          9
+#define PHY_ANALOG_SYNTH6_VC2LOW_MASK                                                                0x00000200
+#define PHY_ANALOG_SYNTH6_VC2LOW_GET(x)                                               (((x) & 0x00000200) >> 9)
+#define PHY_ANALOG_SYNTH6_VC2HIGH_MSB                                                                        10
+#define PHY_ANALOG_SYNTH6_VC2HIGH_LSB                                                                        10
+#define PHY_ANALOG_SYNTH6_VC2HIGH_MASK                                                               0x00000400
+#define PHY_ANALOG_SYNTH6_VC2HIGH_GET(x)                                             (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_SYNTH6_RESET_SDM_B_MSB                                                                    11
+#define PHY_ANALOG_SYNTH6_RESET_SDM_B_LSB                                                                    11
+#define PHY_ANALOG_SYNTH6_RESET_SDM_B_MASK                                                           0x00000800
+#define PHY_ANALOG_SYNTH6_RESET_SDM_B_GET(x)                                         (((x) & 0x00000800) >> 11)
+#define PHY_ANALOG_SYNTH6_RESET_PSCOUNTERS_MSB                                                               12
+#define PHY_ANALOG_SYNTH6_RESET_PSCOUNTERS_LSB                                                               12
+#define PHY_ANALOG_SYNTH6_RESET_PSCOUNTERS_MASK                                                      0x00001000
+#define PHY_ANALOG_SYNTH6_RESET_PSCOUNTERS_GET(x)                                    (((x) & 0x00001000) >> 12)
+#define PHY_ANALOG_SYNTH6_RESET_PFD_MSB                                                                      13
+#define PHY_ANALOG_SYNTH6_RESET_PFD_LSB                                                                      13
+#define PHY_ANALOG_SYNTH6_RESET_PFD_MASK                                                             0x00002000
+#define PHY_ANALOG_SYNTH6_RESET_PFD_GET(x)                                           (((x) & 0x00002000) >> 13)
+#define PHY_ANALOG_SYNTH6_RESET_RFD_MSB                                                                      14
+#define PHY_ANALOG_SYNTH6_RESET_RFD_LSB                                                                      14
+#define PHY_ANALOG_SYNTH6_RESET_RFD_MASK                                                             0x00004000
+#define PHY_ANALOG_SYNTH6_RESET_RFD_GET(x)                                           (((x) & 0x00004000) >> 14)
+#define PHY_ANALOG_SYNTH6_SHORT_R_MSB                                                                        15
+#define PHY_ANALOG_SYNTH6_SHORT_R_LSB                                                                        15
+#define PHY_ANALOG_SYNTH6_SHORT_R_MASK                                                               0x00008000
+#define PHY_ANALOG_SYNTH6_SHORT_R_GET(x)                                             (((x) & 0x00008000) >> 15)
+#define PHY_ANALOG_SYNTH6_VCO_CAP_ST_MSB                                                                     23
+#define PHY_ANALOG_SYNTH6_VCO_CAP_ST_LSB                                                                     16
+#define PHY_ANALOG_SYNTH6_VCO_CAP_ST_MASK                                                            0x00ff0000
+#define PHY_ANALOG_SYNTH6_VCO_CAP_ST_GET(x)                                          (((x) & 0x00ff0000) >> 16)
+#define PHY_ANALOG_SYNTH6_PIN_VC_MSB                                                                         24
+#define PHY_ANALOG_SYNTH6_PIN_VC_LSB                                                                         24
+#define PHY_ANALOG_SYNTH6_PIN_VC_MASK                                                                0x01000000
+#define PHY_ANALOG_SYNTH6_PIN_VC_GET(x)                                              (((x) & 0x01000000) >> 24)
+#define PHY_ANALOG_SYNTH6_SYNTH_LOCK_VC_OK_MSB                                                               25
+#define PHY_ANALOG_SYNTH6_SYNTH_LOCK_VC_OK_LSB                                                               25
+#define PHY_ANALOG_SYNTH6_SYNTH_LOCK_VC_OK_MASK                                                      0x02000000
+#define PHY_ANALOG_SYNTH6_SYNTH_LOCK_VC_OK_GET(x)                                    (((x) & 0x02000000) >> 25)
+#define PHY_ANALOG_SYNTH6_CAP_SEARCH_MSB                                                                     26
+#define PHY_ANALOG_SYNTH6_CAP_SEARCH_LSB                                                                     26
+#define PHY_ANALOG_SYNTH6_CAP_SEARCH_MASK                                                            0x04000000
+#define PHY_ANALOG_SYNTH6_CAP_SEARCH_GET(x)                                          (((x) & 0x04000000) >> 26)
+#define PHY_ANALOG_SYNTH6_SYNTH_SM_STATE_MSB                                                                 30
+#define PHY_ANALOG_SYNTH6_SYNTH_SM_STATE_LSB                                                                 27
+#define PHY_ANALOG_SYNTH6_SYNTH_SM_STATE_MASK                                                        0x78000000
+#define PHY_ANALOG_SYNTH6_SYNTH_SM_STATE_GET(x)                                      (((x) & 0x78000000) >> 27)
+#define PHY_ANALOG_SYNTH6_SYNTH_ON_MSB                                                                       31
+#define PHY_ANALOG_SYNTH6_SYNTH_ON_LSB                                                                       31
+#define PHY_ANALOG_SYNTH6_SYNTH_ON_MASK                                                              0x80000000
+#define PHY_ANALOG_SYNTH6_SYNTH_ON_GET(x)                                            (((x) & 0x80000000) >> 31)
+
+/* macros for SYNTH7 */
+#define PHY_ANALOG_SYNTH7_ADDRESS                                                                    0x00000098
+#define PHY_ANALOG_SYNTH7_OFFSET                                                                     0x00000098
+#define PHY_ANALOG_SYNTH7_OVRCHANDECODER_MSB                                                                  0
+#define PHY_ANALOG_SYNTH7_OVRCHANDECODER_LSB                                                                  0
+#define PHY_ANALOG_SYNTH7_OVRCHANDECODER_MASK                                                        0x00000001
+#define PHY_ANALOG_SYNTH7_OVRCHANDECODER_GET(x)                                       (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_SYNTH7_OVRCHANDECODER_SET(x)                                       (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_SYNTH7_FORCE_FRACLSB_MSB                                                                   1
+#define PHY_ANALOG_SYNTH7_FORCE_FRACLSB_LSB                                                                   1
+#define PHY_ANALOG_SYNTH7_FORCE_FRACLSB_MASK                                                         0x00000002
+#define PHY_ANALOG_SYNTH7_FORCE_FRACLSB_GET(x)                                        (((x) & 0x00000002) >> 1)
+#define PHY_ANALOG_SYNTH7_FORCE_FRACLSB_SET(x)                                        (((x) << 1) & 0x00000002)
+#define PHY_ANALOG_SYNTH7_CHANFRAC_MSB                                                                       18
+#define PHY_ANALOG_SYNTH7_CHANFRAC_LSB                                                                        2
+#define PHY_ANALOG_SYNTH7_CHANFRAC_MASK                                                              0x0007fffc
+#define PHY_ANALOG_SYNTH7_CHANFRAC_GET(x)                                             (((x) & 0x0007fffc) >> 2)
+#define PHY_ANALOG_SYNTH7_CHANFRAC_SET(x)                                             (((x) << 2) & 0x0007fffc)
+#define PHY_ANALOG_SYNTH7_CHANSEL_MSB                                                                        27
+#define PHY_ANALOG_SYNTH7_CHANSEL_LSB                                                                        19
+#define PHY_ANALOG_SYNTH7_CHANSEL_MASK                                                               0x0ff80000
+#define PHY_ANALOG_SYNTH7_CHANSEL_GET(x)                                             (((x) & 0x0ff80000) >> 19)
+#define PHY_ANALOG_SYNTH7_CHANSEL_SET(x)                                             (((x) << 19) & 0x0ff80000)
+#define PHY_ANALOG_SYNTH7_AMODEREFSEL_MSB                                                                    29
+#define PHY_ANALOG_SYNTH7_AMODEREFSEL_LSB                                                                    28
+#define PHY_ANALOG_SYNTH7_AMODEREFSEL_MASK                                                           0x30000000
+#define PHY_ANALOG_SYNTH7_AMODEREFSEL_GET(x)                                         (((x) & 0x30000000) >> 28)
+#define PHY_ANALOG_SYNTH7_AMODEREFSEL_SET(x)                                         (((x) << 28) & 0x30000000)
+#define PHY_ANALOG_SYNTH7_FRACMODE_MSB                                                                       30
+#define PHY_ANALOG_SYNTH7_FRACMODE_LSB                                                                       30
+#define PHY_ANALOG_SYNTH7_FRACMODE_MASK                                                              0x40000000
+#define PHY_ANALOG_SYNTH7_FRACMODE_GET(x)                                            (((x) & 0x40000000) >> 30)
+#define PHY_ANALOG_SYNTH7_FRACMODE_SET(x)                                            (((x) << 30) & 0x40000000)
+#define PHY_ANALOG_SYNTH7_LOADSYNTHCHANNEL_MSB                                                               31
+#define PHY_ANALOG_SYNTH7_LOADSYNTHCHANNEL_LSB                                                               31
+#define PHY_ANALOG_SYNTH7_LOADSYNTHCHANNEL_MASK                                                      0x80000000
+#define PHY_ANALOG_SYNTH7_LOADSYNTHCHANNEL_GET(x)                                    (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_SYNTH7_LOADSYNTHCHANNEL_SET(x)                                    (((x) << 31) & 0x80000000)
+
+/* macros for SYNTH8 */
+#define PHY_ANALOG_SYNTH8_ADDRESS                                                                    0x0000009c
+#define PHY_ANALOG_SYNTH8_OFFSET                                                                     0x0000009c
+#define PHY_ANALOG_SYNTH8_CPSTEERING_EN_FRACN_MSB                                                             0
+#define PHY_ANALOG_SYNTH8_CPSTEERING_EN_FRACN_LSB                                                             0
+#define PHY_ANALOG_SYNTH8_CPSTEERING_EN_FRACN_MASK                                                   0x00000001
+#define PHY_ANALOG_SYNTH8_CPSTEERING_EN_FRACN_GET(x)                                  (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_SYNTH8_CPSTEERING_EN_FRACN_SET(x)                                  (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_SYNTH8_LOOP_ICPB_MSB                                                                       7
+#define PHY_ANALOG_SYNTH8_LOOP_ICPB_LSB                                                                       1
+#define PHY_ANALOG_SYNTH8_LOOP_ICPB_MASK                                                             0x000000fe
+#define PHY_ANALOG_SYNTH8_LOOP_ICPB_GET(x)                                            (((x) & 0x000000fe) >> 1)
+#define PHY_ANALOG_SYNTH8_LOOP_ICPB_SET(x)                                            (((x) << 1) & 0x000000fe)
+#define PHY_ANALOG_SYNTH8_LOOP_CSB_MSB                                                                       11
+#define PHY_ANALOG_SYNTH8_LOOP_CSB_LSB                                                                        8
+#define PHY_ANALOG_SYNTH8_LOOP_CSB_MASK                                                              0x00000f00
+#define PHY_ANALOG_SYNTH8_LOOP_CSB_GET(x)                                             (((x) & 0x00000f00) >> 8)
+#define PHY_ANALOG_SYNTH8_LOOP_CSB_SET(x)                                             (((x) << 8) & 0x00000f00)
+#define PHY_ANALOG_SYNTH8_LOOP_RSB_MSB                                                                       16
+#define PHY_ANALOG_SYNTH8_LOOP_RSB_LSB                                                                       12
+#define PHY_ANALOG_SYNTH8_LOOP_RSB_MASK                                                              0x0001f000
+#define PHY_ANALOG_SYNTH8_LOOP_RSB_GET(x)                                            (((x) & 0x0001f000) >> 12)
+#define PHY_ANALOG_SYNTH8_LOOP_RSB_SET(x)                                            (((x) << 12) & 0x0001f000)
+#define PHY_ANALOG_SYNTH8_LOOP_CPB_MSB                                                                       21
+#define PHY_ANALOG_SYNTH8_LOOP_CPB_LSB                                                                       17
+#define PHY_ANALOG_SYNTH8_LOOP_CPB_MASK                                                              0x003e0000
+#define PHY_ANALOG_SYNTH8_LOOP_CPB_GET(x)                                            (((x) & 0x003e0000) >> 17)
+#define PHY_ANALOG_SYNTH8_LOOP_CPB_SET(x)                                            (((x) << 17) & 0x003e0000)
+#define PHY_ANALOG_SYNTH8_LOOP_3RD_ORDER_RB_MSB                                                              26
+#define PHY_ANALOG_SYNTH8_LOOP_3RD_ORDER_RB_LSB                                                              22
+#define PHY_ANALOG_SYNTH8_LOOP_3RD_ORDER_RB_MASK                                                     0x07c00000
+#define PHY_ANALOG_SYNTH8_LOOP_3RD_ORDER_RB_GET(x)                                   (((x) & 0x07c00000) >> 22)
+#define PHY_ANALOG_SYNTH8_LOOP_3RD_ORDER_RB_SET(x)                                   (((x) << 22) & 0x07c00000)
+#define PHY_ANALOG_SYNTH8_REFDIVB_MSB                                                                        31
+#define PHY_ANALOG_SYNTH8_REFDIVB_LSB                                                                        27
+#define PHY_ANALOG_SYNTH8_REFDIVB_MASK                                                               0xf8000000
+#define PHY_ANALOG_SYNTH8_REFDIVB_GET(x)                                             (((x) & 0xf8000000) >> 27)
+#define PHY_ANALOG_SYNTH8_REFDIVB_SET(x)                                             (((x) << 27) & 0xf8000000)
+
+/* macros for SYNTH9 */
+#define PHY_ANALOG_SYNTH9_ADDRESS                                                                    0x000000a0
+#define PHY_ANALOG_SYNTH9_OFFSET                                                                     0x000000a0
+#define PHY_ANALOG_SYNTH9_PFDDELAY_INTN_MSB                                                                   0
+#define PHY_ANALOG_SYNTH9_PFDDELAY_INTN_LSB                                                                   0
+#define PHY_ANALOG_SYNTH9_PFDDELAY_INTN_MASK                                                         0x00000001
+#define PHY_ANALOG_SYNTH9_PFDDELAY_INTN_GET(x)                                        (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_SYNTH9_PFDDELAY_INTN_SET(x)                                        (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_SYNTH9_SLOPE_ICPA0_MSB                                                                     3
+#define PHY_ANALOG_SYNTH9_SLOPE_ICPA0_LSB                                                                     1
+#define PHY_ANALOG_SYNTH9_SLOPE_ICPA0_MASK                                                           0x0000000e
+#define PHY_ANALOG_SYNTH9_SLOPE_ICPA0_GET(x)                                          (((x) & 0x0000000e) >> 1)
+#define PHY_ANALOG_SYNTH9_SLOPE_ICPA0_SET(x)                                          (((x) << 1) & 0x0000000e)
+#define PHY_ANALOG_SYNTH9_LOOP_ICPA0_MSB                                                                      7
+#define PHY_ANALOG_SYNTH9_LOOP_ICPA0_LSB                                                                      4
+#define PHY_ANALOG_SYNTH9_LOOP_ICPA0_MASK                                                            0x000000f0
+#define PHY_ANALOG_SYNTH9_LOOP_ICPA0_GET(x)                                           (((x) & 0x000000f0) >> 4)
+#define PHY_ANALOG_SYNTH9_LOOP_ICPA0_SET(x)                                           (((x) << 4) & 0x000000f0)
+#define PHY_ANALOG_SYNTH9_LOOP_CSA0_MSB                                                                      11
+#define PHY_ANALOG_SYNTH9_LOOP_CSA0_LSB                                                                       8
+#define PHY_ANALOG_SYNTH9_LOOP_CSA0_MASK                                                             0x00000f00
+#define PHY_ANALOG_SYNTH9_LOOP_CSA0_GET(x)                                            (((x) & 0x00000f00) >> 8)
+#define PHY_ANALOG_SYNTH9_LOOP_CSA0_SET(x)                                            (((x) << 8) & 0x00000f00)
+#define PHY_ANALOG_SYNTH9_LOOP_RSA0_MSB                                                                      16
+#define PHY_ANALOG_SYNTH9_LOOP_RSA0_LSB                                                                      12
+#define PHY_ANALOG_SYNTH9_LOOP_RSA0_MASK                                                             0x0001f000
+#define PHY_ANALOG_SYNTH9_LOOP_RSA0_GET(x)                                           (((x) & 0x0001f000) >> 12)
+#define PHY_ANALOG_SYNTH9_LOOP_RSA0_SET(x)                                           (((x) << 12) & 0x0001f000)
+#define PHY_ANALOG_SYNTH9_LOOP_CPA0_MSB                                                                      21
+#define PHY_ANALOG_SYNTH9_LOOP_CPA0_LSB                                                                      17
+#define PHY_ANALOG_SYNTH9_LOOP_CPA0_MASK                                                             0x003e0000
+#define PHY_ANALOG_SYNTH9_LOOP_CPA0_GET(x)                                           (((x) & 0x003e0000) >> 17)
+#define PHY_ANALOG_SYNTH9_LOOP_CPA0_SET(x)                                           (((x) << 17) & 0x003e0000)
+#define PHY_ANALOG_SYNTH9_LOOP_3RD_ORDER_RA_MSB                                                              26
+#define PHY_ANALOG_SYNTH9_LOOP_3RD_ORDER_RA_LSB                                                              22
+#define PHY_ANALOG_SYNTH9_LOOP_3RD_ORDER_RA_MASK                                                     0x07c00000
+#define PHY_ANALOG_SYNTH9_LOOP_3RD_ORDER_RA_GET(x)                                   (((x) & 0x07c00000) >> 22)
+#define PHY_ANALOG_SYNTH9_LOOP_3RD_ORDER_RA_SET(x)                                   (((x) << 22) & 0x07c00000)
+#define PHY_ANALOG_SYNTH9_REFDIVA_MSB                                                                        31
+#define PHY_ANALOG_SYNTH9_REFDIVA_LSB                                                                        27
+#define PHY_ANALOG_SYNTH9_REFDIVA_MASK                                                               0xf8000000
+#define PHY_ANALOG_SYNTH9_REFDIVA_GET(x)                                             (((x) & 0xf8000000) >> 27)
+#define PHY_ANALOG_SYNTH9_REFDIVA_SET(x)                                             (((x) << 27) & 0xf8000000)
+
+/* macros for SYNTH10 */
+#define PHY_ANALOG_SYNTH10_ADDRESS                                                                   0x000000a4
+#define PHY_ANALOG_SYNTH10_OFFSET                                                                    0x000000a4
+#define PHY_ANALOG_SYNTH10_SPARE10A_MSB                                                                       1
+#define PHY_ANALOG_SYNTH10_SPARE10A_LSB                                                                       0
+#define PHY_ANALOG_SYNTH10_SPARE10A_MASK                                                             0x00000003
+#define PHY_ANALOG_SYNTH10_SPARE10A_GET(x)                                            (((x) & 0x00000003) >> 0)
+#define PHY_ANALOG_SYNTH10_SPARE10A_SET(x)                                            (((x) << 0) & 0x00000003)
+#define PHY_ANALOG_SYNTH10_PWDB_ICLOBIAS50_MSB                                                                4
+#define PHY_ANALOG_SYNTH10_PWDB_ICLOBIAS50_LSB                                                                2
+#define PHY_ANALOG_SYNTH10_PWDB_ICLOBIAS50_MASK                                                      0x0000001c
+#define PHY_ANALOG_SYNTH10_PWDB_ICLOBIAS50_GET(x)                                     (((x) & 0x0000001c) >> 2)
+#define PHY_ANALOG_SYNTH10_PWDB_ICLOBIAS50_SET(x)                                     (((x) << 2) & 0x0000001c)
+#define PHY_ANALOG_SYNTH10_PWDB_IRSPARE25_MSB                                                                 7
+#define PHY_ANALOG_SYNTH10_PWDB_IRSPARE25_LSB                                                                 5
+#define PHY_ANALOG_SYNTH10_PWDB_IRSPARE25_MASK                                                       0x000000e0
+#define PHY_ANALOG_SYNTH10_PWDB_IRSPARE25_GET(x)                                      (((x) & 0x000000e0) >> 5)
+#define PHY_ANALOG_SYNTH10_PWDB_IRSPARE25_SET(x)                                      (((x) << 5) & 0x000000e0)
+#define PHY_ANALOG_SYNTH10_PWDB_ICSPARE25_MSB                                                                10
+#define PHY_ANALOG_SYNTH10_PWDB_ICSPARE25_LSB                                                                 8
+#define PHY_ANALOG_SYNTH10_PWDB_ICSPARE25_MASK                                                       0x00000700
+#define PHY_ANALOG_SYNTH10_PWDB_ICSPARE25_GET(x)                                      (((x) & 0x00000700) >> 8)
+#define PHY_ANALOG_SYNTH10_PWDB_ICSPARE25_SET(x)                                      (((x) << 8) & 0x00000700)
+#define PHY_ANALOG_SYNTH10_SLOPE_ICPA1_MSB                                                                   13
+#define PHY_ANALOG_SYNTH10_SLOPE_ICPA1_LSB                                                                   11
+#define PHY_ANALOG_SYNTH10_SLOPE_ICPA1_MASK                                                          0x00003800
+#define PHY_ANALOG_SYNTH10_SLOPE_ICPA1_GET(x)                                        (((x) & 0x00003800) >> 11)
+#define PHY_ANALOG_SYNTH10_SLOPE_ICPA1_SET(x)                                        (((x) << 11) & 0x00003800)
+#define PHY_ANALOG_SYNTH10_LOOP_ICPA1_MSB                                                                    17
+#define PHY_ANALOG_SYNTH10_LOOP_ICPA1_LSB                                                                    14
+#define PHY_ANALOG_SYNTH10_LOOP_ICPA1_MASK                                                           0x0003c000
+#define PHY_ANALOG_SYNTH10_LOOP_ICPA1_GET(x)                                         (((x) & 0x0003c000) >> 14)
+#define PHY_ANALOG_SYNTH10_LOOP_ICPA1_SET(x)                                         (((x) << 14) & 0x0003c000)
+#define PHY_ANALOG_SYNTH10_LOOP_CSA1_MSB                                                                     21
+#define PHY_ANALOG_SYNTH10_LOOP_CSA1_LSB                                                                     18
+#define PHY_ANALOG_SYNTH10_LOOP_CSA1_MASK                                                            0x003c0000
+#define PHY_ANALOG_SYNTH10_LOOP_CSA1_GET(x)                                          (((x) & 0x003c0000) >> 18)
+#define PHY_ANALOG_SYNTH10_LOOP_CSA1_SET(x)                                          (((x) << 18) & 0x003c0000)
+#define PHY_ANALOG_SYNTH10_LOOP_RSA1_MSB                                                                     26
+#define PHY_ANALOG_SYNTH10_LOOP_RSA1_LSB                                                                     22
+#define PHY_ANALOG_SYNTH10_LOOP_RSA1_MASK                                                            0x07c00000
+#define PHY_ANALOG_SYNTH10_LOOP_RSA1_GET(x)                                          (((x) & 0x07c00000) >> 22)
+#define PHY_ANALOG_SYNTH10_LOOP_RSA1_SET(x)                                          (((x) << 22) & 0x07c00000)
+#define PHY_ANALOG_SYNTH10_LOOP_CPA1_MSB                                                                     31
+#define PHY_ANALOG_SYNTH10_LOOP_CPA1_LSB                                                                     27
+#define PHY_ANALOG_SYNTH10_LOOP_CPA1_MASK                                                            0xf8000000
+#define PHY_ANALOG_SYNTH10_LOOP_CPA1_GET(x)                                          (((x) & 0xf8000000) >> 27)
+#define PHY_ANALOG_SYNTH10_LOOP_CPA1_SET(x)                                          (((x) << 27) & 0xf8000000)
+
+/* macros for SYNTH11 */
+#define PHY_ANALOG_SYNTH11_ADDRESS                                                                   0x000000a8
+#define PHY_ANALOG_SYNTH11_OFFSET                                                                    0x000000a8
+#define PHY_ANALOG_SYNTH11_SPARE11A_MSB                                                                       4
+#define PHY_ANALOG_SYNTH11_SPARE11A_LSB                                                                       0
+#define PHY_ANALOG_SYNTH11_SPARE11A_MASK                                                             0x0000001f
+#define PHY_ANALOG_SYNTH11_SPARE11A_GET(x)                                            (((x) & 0x0000001f) >> 0)
+#define PHY_ANALOG_SYNTH11_SPARE11A_SET(x)                                            (((x) << 0) & 0x0000001f)
+#define PHY_ANALOG_SYNTH11_FORCE_LOBUF5G_ON_MSB                                                               5
+#define PHY_ANALOG_SYNTH11_FORCE_LOBUF5G_ON_LSB                                                               5
+#define PHY_ANALOG_SYNTH11_FORCE_LOBUF5G_ON_MASK                                                     0x00000020
+#define PHY_ANALOG_SYNTH11_FORCE_LOBUF5G_ON_GET(x)                                    (((x) & 0x00000020) >> 5)
+#define PHY_ANALOG_SYNTH11_FORCE_LOBUF5G_ON_SET(x)                                    (((x) << 5) & 0x00000020)
+#define PHY_ANALOG_SYNTH11_LOREFSEL_MSB                                                                       7
+#define PHY_ANALOG_SYNTH11_LOREFSEL_LSB                                                                       6
+#define PHY_ANALOG_SYNTH11_LOREFSEL_MASK                                                             0x000000c0
+#define PHY_ANALOG_SYNTH11_LOREFSEL_GET(x)                                            (((x) & 0x000000c0) >> 6)
+#define PHY_ANALOG_SYNTH11_LOREFSEL_SET(x)                                            (((x) << 6) & 0x000000c0)
+#define PHY_ANALOG_SYNTH11_LOBUF2GTUNE_MSB                                                                    9
+#define PHY_ANALOG_SYNTH11_LOBUF2GTUNE_LSB                                                                    8
+#define PHY_ANALOG_SYNTH11_LOBUF2GTUNE_MASK                                                          0x00000300
+#define PHY_ANALOG_SYNTH11_LOBUF2GTUNE_GET(x)                                         (((x) & 0x00000300) >> 8)
+#define PHY_ANALOG_SYNTH11_LOBUF2GTUNE_SET(x)                                         (((x) << 8) & 0x00000300)
+#define PHY_ANALOG_SYNTH11_CPSTEERING_MODE_MSB                                                               10
+#define PHY_ANALOG_SYNTH11_CPSTEERING_MODE_LSB                                                               10
+#define PHY_ANALOG_SYNTH11_CPSTEERING_MODE_MASK                                                      0x00000400
+#define PHY_ANALOG_SYNTH11_CPSTEERING_MODE_GET(x)                                    (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_SYNTH11_CPSTEERING_MODE_SET(x)                                    (((x) << 10) & 0x00000400)
+#define PHY_ANALOG_SYNTH11_SLOPE_ICPA2_MSB                                                                   13
+#define PHY_ANALOG_SYNTH11_SLOPE_ICPA2_LSB                                                                   11
+#define PHY_ANALOG_SYNTH11_SLOPE_ICPA2_MASK                                                          0x00003800
+#define PHY_ANALOG_SYNTH11_SLOPE_ICPA2_GET(x)                                        (((x) & 0x00003800) >> 11)
+#define PHY_ANALOG_SYNTH11_SLOPE_ICPA2_SET(x)                                        (((x) << 11) & 0x00003800)
+#define PHY_ANALOG_SYNTH11_LOOP_ICPA2_MSB                                                                    17
+#define PHY_ANALOG_SYNTH11_LOOP_ICPA2_LSB                                                                    14
+#define PHY_ANALOG_SYNTH11_LOOP_ICPA2_MASK                                                           0x0003c000
+#define PHY_ANALOG_SYNTH11_LOOP_ICPA2_GET(x)                                         (((x) & 0x0003c000) >> 14)
+#define PHY_ANALOG_SYNTH11_LOOP_ICPA2_SET(x)                                         (((x) << 14) & 0x0003c000)
+#define PHY_ANALOG_SYNTH11_LOOP_CSA2_MSB                                                                     21
+#define PHY_ANALOG_SYNTH11_LOOP_CSA2_LSB                                                                     18
+#define PHY_ANALOG_SYNTH11_LOOP_CSA2_MASK                                                            0x003c0000
+#define PHY_ANALOG_SYNTH11_LOOP_CSA2_GET(x)                                          (((x) & 0x003c0000) >> 18)
+#define PHY_ANALOG_SYNTH11_LOOP_CSA2_SET(x)                                          (((x) << 18) & 0x003c0000)
+#define PHY_ANALOG_SYNTH11_LOOP_RSA2_MSB                                                                     26
+#define PHY_ANALOG_SYNTH11_LOOP_RSA2_LSB                                                                     22
+#define PHY_ANALOG_SYNTH11_LOOP_RSA2_MASK                                                            0x07c00000
+#define PHY_ANALOG_SYNTH11_LOOP_RSA2_GET(x)                                          (((x) & 0x07c00000) >> 22)
+#define PHY_ANALOG_SYNTH11_LOOP_RSA2_SET(x)                                          (((x) << 22) & 0x07c00000)
+#define PHY_ANALOG_SYNTH11_LOOP_CPA2_MSB                                                                     31
+#define PHY_ANALOG_SYNTH11_LOOP_CPA2_LSB                                                                     27
+#define PHY_ANALOG_SYNTH11_LOOP_CPA2_MASK                                                            0xf8000000
+#define PHY_ANALOG_SYNTH11_LOOP_CPA2_GET(x)                                          (((x) & 0xf8000000) >> 27)
+#define PHY_ANALOG_SYNTH11_LOOP_CPA2_SET(x)                                          (((x) << 27) & 0xf8000000)
+
+/* macros for SYNTH12 */
+#define PHY_ANALOG_SYNTH12_ADDRESS                                                                   0x000000ac
+#define PHY_ANALOG_SYNTH12_OFFSET                                                                    0x000000ac
+#define PHY_ANALOG_SYNTH12_SPARE12A_MSB                                                                       9
+#define PHY_ANALOG_SYNTH12_SPARE12A_LSB                                                                       0
+#define PHY_ANALOG_SYNTH12_SPARE12A_MASK                                                             0x000003ff
+#define PHY_ANALOG_SYNTH12_SPARE12A_GET(x)                                            (((x) & 0x000003ff) >> 0)
+#define PHY_ANALOG_SYNTH12_SPARE12A_SET(x)                                            (((x) << 0) & 0x000003ff)
+#define PHY_ANALOG_SYNTH12_LOOPLEAKCUR_FRACN_MSB                                                             13
+#define PHY_ANALOG_SYNTH12_LOOPLEAKCUR_FRACN_LSB                                                             10
+#define PHY_ANALOG_SYNTH12_LOOPLEAKCUR_FRACN_MASK                                                    0x00003c00
+#define PHY_ANALOG_SYNTH12_LOOPLEAKCUR_FRACN_GET(x)                                  (((x) & 0x00003c00) >> 10)
+#define PHY_ANALOG_SYNTH12_LOOPLEAKCUR_FRACN_SET(x)                                  (((x) << 10) & 0x00003c00)
+#define PHY_ANALOG_SYNTH12_CPLOWLK_FRACN_MSB                                                                 14
+#define PHY_ANALOG_SYNTH12_CPLOWLK_FRACN_LSB                                                                 14
+#define PHY_ANALOG_SYNTH12_CPLOWLK_FRACN_MASK                                                        0x00004000
+#define PHY_ANALOG_SYNTH12_CPLOWLK_FRACN_GET(x)                                      (((x) & 0x00004000) >> 14)
+#define PHY_ANALOG_SYNTH12_CPLOWLK_FRACN_SET(x)                                      (((x) << 14) & 0x00004000)
+#define PHY_ANALOG_SYNTH12_CPBIAS_FRACN_MSB                                                                  16
+#define PHY_ANALOG_SYNTH12_CPBIAS_FRACN_LSB                                                                  15
+#define PHY_ANALOG_SYNTH12_CPBIAS_FRACN_MASK                                                         0x00018000
+#define PHY_ANALOG_SYNTH12_CPBIAS_FRACN_GET(x)                                       (((x) & 0x00018000) >> 15)
+#define PHY_ANALOG_SYNTH12_CPBIAS_FRACN_SET(x)                                       (((x) << 15) & 0x00018000)
+#define PHY_ANALOG_SYNTH12_SYNTHDIGOUTEN_MSB                                                                 17
+#define PHY_ANALOG_SYNTH12_SYNTHDIGOUTEN_LSB                                                                 17
+#define PHY_ANALOG_SYNTH12_SYNTHDIGOUTEN_MASK                                                        0x00020000
+#define PHY_ANALOG_SYNTH12_SYNTHDIGOUTEN_GET(x)                                      (((x) & 0x00020000) >> 17)
+#define PHY_ANALOG_SYNTH12_SYNTHDIGOUTEN_SET(x)                                      (((x) << 17) & 0x00020000)
+#define PHY_ANALOG_SYNTH12_STRCONT_MSB                                                                       18
+#define PHY_ANALOG_SYNTH12_STRCONT_LSB                                                                       18
+#define PHY_ANALOG_SYNTH12_STRCONT_MASK                                                              0x00040000
+#define PHY_ANALOG_SYNTH12_STRCONT_GET(x)                                            (((x) & 0x00040000) >> 18)
+#define PHY_ANALOG_SYNTH12_STRCONT_SET(x)                                            (((x) << 18) & 0x00040000)
+#define PHY_ANALOG_SYNTH12_VREFMUL3_MSB                                                                      22
+#define PHY_ANALOG_SYNTH12_VREFMUL3_LSB                                                                      19
+#define PHY_ANALOG_SYNTH12_VREFMUL3_MASK                                                             0x00780000
+#define PHY_ANALOG_SYNTH12_VREFMUL3_GET(x)                                           (((x) & 0x00780000) >> 19)
+#define PHY_ANALOG_SYNTH12_VREFMUL3_SET(x)                                           (((x) << 19) & 0x00780000)
+#define PHY_ANALOG_SYNTH12_VREFMUL2_MSB                                                                      26
+#define PHY_ANALOG_SYNTH12_VREFMUL2_LSB                                                                      23
+#define PHY_ANALOG_SYNTH12_VREFMUL2_MASK                                                             0x07800000
+#define PHY_ANALOG_SYNTH12_VREFMUL2_GET(x)                                           (((x) & 0x07800000) >> 23)
+#define PHY_ANALOG_SYNTH12_VREFMUL2_SET(x)                                           (((x) << 23) & 0x07800000)
+#define PHY_ANALOG_SYNTH12_VREFMUL1_MSB                                                                      30
+#define PHY_ANALOG_SYNTH12_VREFMUL1_LSB                                                                      27
+#define PHY_ANALOG_SYNTH12_VREFMUL1_MASK                                                             0x78000000
+#define PHY_ANALOG_SYNTH12_VREFMUL1_GET(x)                                           (((x) & 0x78000000) >> 27)
+#define PHY_ANALOG_SYNTH12_VREFMUL1_SET(x)                                           (((x) << 27) & 0x78000000)
+#define PHY_ANALOG_SYNTH12_CLK_DOUBLER_EN_MSB                                                                31
+#define PHY_ANALOG_SYNTH12_CLK_DOUBLER_EN_LSB                                                                31
+#define PHY_ANALOG_SYNTH12_CLK_DOUBLER_EN_MASK                                                       0x80000000
+#define PHY_ANALOG_SYNTH12_CLK_DOUBLER_EN_GET(x)                                     (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_SYNTH12_CLK_DOUBLER_EN_SET(x)                                     (((x) << 31) & 0x80000000)
+
+/* macros for SYNTH13 */
+#define PHY_ANALOG_SYNTH13_ADDRESS                                                                   0x000000b0
+#define PHY_ANALOG_SYNTH13_OFFSET                                                                    0x000000b0
+#define PHY_ANALOG_SYNTH13_SPARE13A_MSB                                                                       0
+#define PHY_ANALOG_SYNTH13_SPARE13A_LSB                                                                       0
+#define PHY_ANALOG_SYNTH13_SPARE13A_MASK                                                             0x00000001
+#define PHY_ANALOG_SYNTH13_SPARE13A_GET(x)                                            (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_SYNTH13_SPARE13A_SET(x)                                            (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_SYNTH13_SLOPE_ICPA_FRACN_MSB                                                               3
+#define PHY_ANALOG_SYNTH13_SLOPE_ICPA_FRACN_LSB                                                               1
+#define PHY_ANALOG_SYNTH13_SLOPE_ICPA_FRACN_MASK                                                     0x0000000e
+#define PHY_ANALOG_SYNTH13_SLOPE_ICPA_FRACN_GET(x)                                    (((x) & 0x0000000e) >> 1)
+#define PHY_ANALOG_SYNTH13_SLOPE_ICPA_FRACN_SET(x)                                    (((x) << 1) & 0x0000000e)
+#define PHY_ANALOG_SYNTH13_LOOP_ICPA_FRACN_MSB                                                                7
+#define PHY_ANALOG_SYNTH13_LOOP_ICPA_FRACN_LSB                                                                4
+#define PHY_ANALOG_SYNTH13_LOOP_ICPA_FRACN_MASK                                                      0x000000f0
+#define PHY_ANALOG_SYNTH13_LOOP_ICPA_FRACN_GET(x)                                     (((x) & 0x000000f0) >> 4)
+#define PHY_ANALOG_SYNTH13_LOOP_ICPA_FRACN_SET(x)                                     (((x) << 4) & 0x000000f0)
+#define PHY_ANALOG_SYNTH13_LOOP_CSA_FRACN_MSB                                                                11
+#define PHY_ANALOG_SYNTH13_LOOP_CSA_FRACN_LSB                                                                 8
+#define PHY_ANALOG_SYNTH13_LOOP_CSA_FRACN_MASK                                                       0x00000f00
+#define PHY_ANALOG_SYNTH13_LOOP_CSA_FRACN_GET(x)                                      (((x) & 0x00000f00) >> 8)
+#define PHY_ANALOG_SYNTH13_LOOP_CSA_FRACN_SET(x)                                      (((x) << 8) & 0x00000f00)
+#define PHY_ANALOG_SYNTH13_LOOP_RSA_FRACN_MSB                                                                16
+#define PHY_ANALOG_SYNTH13_LOOP_RSA_FRACN_LSB                                                                12
+#define PHY_ANALOG_SYNTH13_LOOP_RSA_FRACN_MASK                                                       0x0001f000
+#define PHY_ANALOG_SYNTH13_LOOP_RSA_FRACN_GET(x)                                     (((x) & 0x0001f000) >> 12)
+#define PHY_ANALOG_SYNTH13_LOOP_RSA_FRACN_SET(x)                                     (((x) << 12) & 0x0001f000)
+#define PHY_ANALOG_SYNTH13_LOOP_CPA_FRACN_MSB                                                                21
+#define PHY_ANALOG_SYNTH13_LOOP_CPA_FRACN_LSB                                                                17
+#define PHY_ANALOG_SYNTH13_LOOP_CPA_FRACN_MASK                                                       0x003e0000
+#define PHY_ANALOG_SYNTH13_LOOP_CPA_FRACN_GET(x)                                     (((x) & 0x003e0000) >> 17)
+#define PHY_ANALOG_SYNTH13_LOOP_CPA_FRACN_SET(x)                                     (((x) << 17) & 0x003e0000)
+#define PHY_ANALOG_SYNTH13_LOOP_3RD_ORDER_RA_FRACN_MSB                                                       26
+#define PHY_ANALOG_SYNTH13_LOOP_3RD_ORDER_RA_FRACN_LSB                                                       22
+#define PHY_ANALOG_SYNTH13_LOOP_3RD_ORDER_RA_FRACN_MASK                                              0x07c00000
+#define PHY_ANALOG_SYNTH13_LOOP_3RD_ORDER_RA_FRACN_GET(x)                            (((x) & 0x07c00000) >> 22)
+#define PHY_ANALOG_SYNTH13_LOOP_3RD_ORDER_RA_FRACN_SET(x)                            (((x) << 22) & 0x07c00000)
+#define PHY_ANALOG_SYNTH13_REFDIVA_FRACN_MSB                                                                 31
+#define PHY_ANALOG_SYNTH13_REFDIVA_FRACN_LSB                                                                 27
+#define PHY_ANALOG_SYNTH13_REFDIVA_FRACN_MASK                                                        0xf8000000
+#define PHY_ANALOG_SYNTH13_REFDIVA_FRACN_GET(x)                                      (((x) & 0xf8000000) >> 27)
+#define PHY_ANALOG_SYNTH13_REFDIVA_FRACN_SET(x)                                      (((x) << 27) & 0xf8000000)
+
+/* macros for SYNTH14 */
+#define PHY_ANALOG_SYNTH14_ADDRESS                                                                   0x000000b4
+#define PHY_ANALOG_SYNTH14_OFFSET                                                                    0x000000b4
+#define PHY_ANALOG_SYNTH14_SPARE14A_MSB                                                                       1
+#define PHY_ANALOG_SYNTH14_SPARE14A_LSB                                                                       0
+#define PHY_ANALOG_SYNTH14_SPARE14A_MASK                                                             0x00000003
+#define PHY_ANALOG_SYNTH14_SPARE14A_GET(x)                                            (((x) & 0x00000003) >> 0)
+#define PHY_ANALOG_SYNTH14_SPARE14A_SET(x)                                            (((x) << 0) & 0x00000003)
+#define PHY_ANALOG_SYNTH14_LOBUF5GTUNE_3_MSB                                                                  3
+#define PHY_ANALOG_SYNTH14_LOBUF5GTUNE_3_LSB                                                                  2
+#define PHY_ANALOG_SYNTH14_LOBUF5GTUNE_3_MASK                                                        0x0000000c
+#define PHY_ANALOG_SYNTH14_LOBUF5GTUNE_3_GET(x)                                       (((x) & 0x0000000c) >> 2)
+#define PHY_ANALOG_SYNTH14_LOBUF5GTUNE_3_SET(x)                                       (((x) << 2) & 0x0000000c)
+#define PHY_ANALOG_SYNTH14_LOBUF2GTUNE_3_MSB                                                                  5
+#define PHY_ANALOG_SYNTH14_LOBUF2GTUNE_3_LSB                                                                  4
+#define PHY_ANALOG_SYNTH14_LOBUF2GTUNE_3_MASK                                                        0x00000030
+#define PHY_ANALOG_SYNTH14_LOBUF2GTUNE_3_GET(x)                                       (((x) & 0x00000030) >> 4)
+#define PHY_ANALOG_SYNTH14_LOBUF2GTUNE_3_SET(x)                                       (((x) << 4) & 0x00000030)
+#define PHY_ANALOG_SYNTH14_LOBUF5GTUNE_2_MSB                                                                  7
+#define PHY_ANALOG_SYNTH14_LOBUF5GTUNE_2_LSB                                                                  6
+#define PHY_ANALOG_SYNTH14_LOBUF5GTUNE_2_MASK                                                        0x000000c0
+#define PHY_ANALOG_SYNTH14_LOBUF5GTUNE_2_GET(x)                                       (((x) & 0x000000c0) >> 6)
+#define PHY_ANALOG_SYNTH14_LOBUF5GTUNE_2_SET(x)                                       (((x) << 6) & 0x000000c0)
+#define PHY_ANALOG_SYNTH14_LOBUF2GTUNE_2_MSB                                                                  9
+#define PHY_ANALOG_SYNTH14_LOBUF2GTUNE_2_LSB                                                                  8
+#define PHY_ANALOG_SYNTH14_LOBUF2GTUNE_2_MASK                                                        0x00000300
+#define PHY_ANALOG_SYNTH14_LOBUF2GTUNE_2_GET(x)                                       (((x) & 0x00000300) >> 8)
+#define PHY_ANALOG_SYNTH14_LOBUF2GTUNE_2_SET(x)                                       (((x) << 8) & 0x00000300)
+#define PHY_ANALOG_SYNTH14_PWD_LOBUF5G_3_MSB                                                                 10
+#define PHY_ANALOG_SYNTH14_PWD_LOBUF5G_3_LSB                                                                 10
+#define PHY_ANALOG_SYNTH14_PWD_LOBUF5G_3_MASK                                                        0x00000400
+#define PHY_ANALOG_SYNTH14_PWD_LOBUF5G_3_GET(x)                                      (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_SYNTH14_PWD_LOBUF5G_3_SET(x)                                      (((x) << 10) & 0x00000400)
+#define PHY_ANALOG_SYNTH14_PWD_LOBUF2G_3_MSB                                                                 11
+#define PHY_ANALOG_SYNTH14_PWD_LOBUF2G_3_LSB                                                                 11
+#define PHY_ANALOG_SYNTH14_PWD_LOBUF2G_3_MASK                                                        0x00000800
+#define PHY_ANALOG_SYNTH14_PWD_LOBUF2G_3_GET(x)                                      (((x) & 0x00000800) >> 11)
+#define PHY_ANALOG_SYNTH14_PWD_LOBUF2G_3_SET(x)                                      (((x) << 11) & 0x00000800)
+#define PHY_ANALOG_SYNTH14_PWD_LOBUF5G_2_MSB                                                                 12
+#define PHY_ANALOG_SYNTH14_PWD_LOBUF5G_2_LSB                                                                 12
+#define PHY_ANALOG_SYNTH14_PWD_LOBUF5G_2_MASK                                                        0x00001000
+#define PHY_ANALOG_SYNTH14_PWD_LOBUF5G_2_GET(x)                                      (((x) & 0x00001000) >> 12)
+#define PHY_ANALOG_SYNTH14_PWD_LOBUF5G_2_SET(x)                                      (((x) << 12) & 0x00001000)
+#define PHY_ANALOG_SYNTH14_PWD_LOBUF2G_2_MSB                                                                 13
+#define PHY_ANALOG_SYNTH14_PWD_LOBUF2G_2_LSB                                                                 13
+#define PHY_ANALOG_SYNTH14_PWD_LOBUF2G_2_MASK                                                        0x00002000
+#define PHY_ANALOG_SYNTH14_PWD_LOBUF2G_2_GET(x)                                      (((x) & 0x00002000) >> 13)
+#define PHY_ANALOG_SYNTH14_PWD_LOBUF2G_2_SET(x)                                      (((x) << 13) & 0x00002000)
+#define PHY_ANALOG_SYNTH14_PWUPLO23_PD_MSB                                                                   16
+#define PHY_ANALOG_SYNTH14_PWUPLO23_PD_LSB                                                                   14
+#define PHY_ANALOG_SYNTH14_PWUPLO23_PD_MASK                                                          0x0001c000
+#define PHY_ANALOG_SYNTH14_PWUPLO23_PD_GET(x)                                        (((x) & 0x0001c000) >> 14)
+#define PHY_ANALOG_SYNTH14_PWUPLO23_PD_SET(x)                                        (((x) << 14) & 0x0001c000)
+#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF5G50_3_MSB                                                            19
+#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF5G50_3_LSB                                                            17
+#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF5G50_3_MASK                                                   0x000e0000
+#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF5G50_3_GET(x)                                 (((x) & 0x000e0000) >> 17)
+#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF5G50_3_SET(x)                                 (((x) << 17) & 0x000e0000)
+#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF2G50_3_MSB                                                            22
+#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF2G50_3_LSB                                                            20
+#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF2G50_3_MASK                                                   0x00700000
+#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF2G50_3_GET(x)                                 (((x) & 0x00700000) >> 20)
+#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF2G50_3_SET(x)                                 (((x) << 20) & 0x00700000)
+#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF5G50_2_MSB                                                            25
+#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF5G50_2_LSB                                                            23
+#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF5G50_2_MASK                                                   0x03800000
+#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF5G50_2_GET(x)                                 (((x) & 0x03800000) >> 23)
+#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF5G50_2_SET(x)                                 (((x) << 23) & 0x03800000)
+#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF2G50_2_MSB                                                            28
+#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF2G50_2_LSB                                                            26
+#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF2G50_2_MASK                                                   0x1c000000
+#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF2G50_2_GET(x)                                 (((x) & 0x1c000000) >> 26)
+#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF2G50_2_SET(x)                                 (((x) << 26) & 0x1c000000)
+#define PHY_ANALOG_SYNTH14_PWDB_ICLVLSHFT_MSB                                                                31
+#define PHY_ANALOG_SYNTH14_PWDB_ICLVLSHFT_LSB                                                                29
+#define PHY_ANALOG_SYNTH14_PWDB_ICLVLSHFT_MASK                                                       0xe0000000
+#define PHY_ANALOG_SYNTH14_PWDB_ICLVLSHFT_GET(x)                                     (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_SYNTH14_PWDB_ICLVLSHFT_SET(x)                                     (((x) << 29) & 0xe0000000)
+
+/* macros for BIAS1 */
+#define PHY_ANALOG_BIAS1_ADDRESS                                                                     0x000000c0
+#define PHY_ANALOG_BIAS1_OFFSET                                                                      0x000000c0
+#define PHY_ANALOG_BIAS1_SPARE1_MSB                                                                           6
+#define PHY_ANALOG_BIAS1_SPARE1_LSB                                                                           0
+#define PHY_ANALOG_BIAS1_SPARE1_MASK                                                                 0x0000007f
+#define PHY_ANALOG_BIAS1_SPARE1_GET(x)                                                (((x) & 0x0000007f) >> 0)
+#define PHY_ANALOG_BIAS1_SPARE1_SET(x)                                                (((x) << 0) & 0x0000007f)
+#define PHY_ANALOG_BIAS1_PWD_IC25V2IQ_MSB                                                                     9
+#define PHY_ANALOG_BIAS1_PWD_IC25V2IQ_LSB                                                                     7
+#define PHY_ANALOG_BIAS1_PWD_IC25V2IQ_MASK                                                           0x00000380
+#define PHY_ANALOG_BIAS1_PWD_IC25V2IQ_GET(x)                                          (((x) & 0x00000380) >> 7)
+#define PHY_ANALOG_BIAS1_PWD_IC25V2IQ_SET(x)                                          (((x) << 7) & 0x00000380)
+#define PHY_ANALOG_BIAS1_PWD_IC25V2II_MSB                                                                    12
+#define PHY_ANALOG_BIAS1_PWD_IC25V2II_LSB                                                                    10
+#define PHY_ANALOG_BIAS1_PWD_IC25V2II_MASK                                                           0x00001c00
+#define PHY_ANALOG_BIAS1_PWD_IC25V2II_GET(x)                                         (((x) & 0x00001c00) >> 10)
+#define PHY_ANALOG_BIAS1_PWD_IC25V2II_SET(x)                                         (((x) << 10) & 0x00001c00)
+#define PHY_ANALOG_BIAS1_PWD_IC25BB_MSB                                                                      15
+#define PHY_ANALOG_BIAS1_PWD_IC25BB_LSB                                                                      13
+#define PHY_ANALOG_BIAS1_PWD_IC25BB_MASK                                                             0x0000e000
+#define PHY_ANALOG_BIAS1_PWD_IC25BB_GET(x)                                           (((x) & 0x0000e000) >> 13)
+#define PHY_ANALOG_BIAS1_PWD_IC25BB_SET(x)                                           (((x) << 13) & 0x0000e000)
+#define PHY_ANALOG_BIAS1_PWD_IC25DAC_MSB                                                                     18
+#define PHY_ANALOG_BIAS1_PWD_IC25DAC_LSB                                                                     16
+#define PHY_ANALOG_BIAS1_PWD_IC25DAC_MASK                                                            0x00070000
+#define PHY_ANALOG_BIAS1_PWD_IC25DAC_GET(x)                                          (((x) & 0x00070000) >> 16)
+#define PHY_ANALOG_BIAS1_PWD_IC25DAC_SET(x)                                          (((x) << 16) & 0x00070000)
+#define PHY_ANALOG_BIAS1_PWD_IC25FIR_MSB                                                                     21
+#define PHY_ANALOG_BIAS1_PWD_IC25FIR_LSB                                                                     19
+#define PHY_ANALOG_BIAS1_PWD_IC25FIR_MASK                                                            0x00380000
+#define PHY_ANALOG_BIAS1_PWD_IC25FIR_GET(x)                                          (((x) & 0x00380000) >> 19)
+#define PHY_ANALOG_BIAS1_PWD_IC25FIR_SET(x)                                          (((x) << 19) & 0x00380000)
+#define PHY_ANALOG_BIAS1_PWD_IC25ADC_MSB                                                                     24
+#define PHY_ANALOG_BIAS1_PWD_IC25ADC_LSB                                                                     22
+#define PHY_ANALOG_BIAS1_PWD_IC25ADC_MASK                                                            0x01c00000
+#define PHY_ANALOG_BIAS1_PWD_IC25ADC_GET(x)                                          (((x) & 0x01c00000) >> 22)
+#define PHY_ANALOG_BIAS1_PWD_IC25ADC_SET(x)                                          (((x) << 22) & 0x01c00000)
+#define PHY_ANALOG_BIAS1_BIAS_SEL_MSB                                                                        31
+#define PHY_ANALOG_BIAS1_BIAS_SEL_LSB                                                                        25
+#define PHY_ANALOG_BIAS1_BIAS_SEL_MASK                                                               0xfe000000
+#define PHY_ANALOG_BIAS1_BIAS_SEL_GET(x)                                             (((x) & 0xfe000000) >> 25)
+#define PHY_ANALOG_BIAS1_BIAS_SEL_SET(x)                                             (((x) << 25) & 0xfe000000)
+
+/* macros for BIAS2 */
+#define PHY_ANALOG_BIAS2_ADDRESS                                                                     0x000000c4
+#define PHY_ANALOG_BIAS2_OFFSET                                                                      0x000000c4
+#define PHY_ANALOG_BIAS2_SPARE2_MSB                                                                           4
+#define PHY_ANALOG_BIAS2_SPARE2_LSB                                                                           0
+#define PHY_ANALOG_BIAS2_SPARE2_MASK                                                                 0x0000001f
+#define PHY_ANALOG_BIAS2_SPARE2_GET(x)                                                (((x) & 0x0000001f) >> 0)
+#define PHY_ANALOG_BIAS2_SPARE2_SET(x)                                                (((x) << 0) & 0x0000001f)
+#define PHY_ANALOG_BIAS2_PWD_IC25XPA_MSB                                                                      7
+#define PHY_ANALOG_BIAS2_PWD_IC25XPA_LSB                                                                      5
+#define PHY_ANALOG_BIAS2_PWD_IC25XPA_MASK                                                            0x000000e0
+#define PHY_ANALOG_BIAS2_PWD_IC25XPA_GET(x)                                           (((x) & 0x000000e0) >> 5)
+#define PHY_ANALOG_BIAS2_PWD_IC25XPA_SET(x)                                           (((x) << 5) & 0x000000e0)
+#define PHY_ANALOG_BIAS2_PWD_IC25XTAL_MSB                                                                    10
+#define PHY_ANALOG_BIAS2_PWD_IC25XTAL_LSB                                                                     8
+#define PHY_ANALOG_BIAS2_PWD_IC25XTAL_MASK                                                           0x00000700
+#define PHY_ANALOG_BIAS2_PWD_IC25XTAL_GET(x)                                          (((x) & 0x00000700) >> 8)
+#define PHY_ANALOG_BIAS2_PWD_IC25XTAL_SET(x)                                          (((x) << 8) & 0x00000700)
+#define PHY_ANALOG_BIAS2_PWD_IC25TXRF_MSB                                                                    13
+#define PHY_ANALOG_BIAS2_PWD_IC25TXRF_LSB                                                                    11
+#define PHY_ANALOG_BIAS2_PWD_IC25TXRF_MASK                                                           0x00003800
+#define PHY_ANALOG_BIAS2_PWD_IC25TXRF_GET(x)                                         (((x) & 0x00003800) >> 11)
+#define PHY_ANALOG_BIAS2_PWD_IC25TXRF_SET(x)                                         (((x) << 11) & 0x00003800)
+#define PHY_ANALOG_BIAS2_PWD_IC25RXRF_MSB                                                                    16
+#define PHY_ANALOG_BIAS2_PWD_IC25RXRF_LSB                                                                    14
+#define PHY_ANALOG_BIAS2_PWD_IC25RXRF_MASK                                                           0x0001c000
+#define PHY_ANALOG_BIAS2_PWD_IC25RXRF_GET(x)                                         (((x) & 0x0001c000) >> 14)
+#define PHY_ANALOG_BIAS2_PWD_IC25RXRF_SET(x)                                         (((x) << 14) & 0x0001c000)
+#define PHY_ANALOG_BIAS2_PWD_IC25SYNTH_MSB                                                                   19
+#define PHY_ANALOG_BIAS2_PWD_IC25SYNTH_LSB                                                                   17
+#define PHY_ANALOG_BIAS2_PWD_IC25SYNTH_MASK                                                          0x000e0000
+#define PHY_ANALOG_BIAS2_PWD_IC25SYNTH_GET(x)                                        (((x) & 0x000e0000) >> 17)
+#define PHY_ANALOG_BIAS2_PWD_IC25SYNTH_SET(x)                                        (((x) << 17) & 0x000e0000)
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLREG_MSB                                                                  22
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLREG_LSB                                                                  20
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLREG_MASK                                                         0x00700000
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLREG_GET(x)                                       (((x) & 0x00700000) >> 20)
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLREG_SET(x)                                       (((x) << 20) & 0x00700000)
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP2_MSB                                                                  25
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP2_LSB                                                                  23
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP2_MASK                                                         0x03800000
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP2_GET(x)                                       (((x) & 0x03800000) >> 23)
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP2_SET(x)                                       (((x) << 23) & 0x03800000)
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP_MSB                                                                   28
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP_LSB                                                                   26
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP_MASK                                                          0x1c000000
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP_GET(x)                                        (((x) & 0x1c000000) >> 26)
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP_SET(x)                                        (((x) << 26) & 0x1c000000)
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLGM_MSB                                                                   31
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLGM_LSB                                                                   29
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLGM_MASK                                                          0xe0000000
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLGM_GET(x)                                        (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLGM_SET(x)                                        (((x) << 29) & 0xe0000000)
+
+/* macros for BIAS3 */
+#define PHY_ANALOG_BIAS3_ADDRESS                                                                     0x000000c8
+#define PHY_ANALOG_BIAS3_OFFSET                                                                      0x000000c8
+#define PHY_ANALOG_BIAS3_SPARE3_MSB                                                                           1
+#define PHY_ANALOG_BIAS3_SPARE3_LSB                                                                           0
+#define PHY_ANALOG_BIAS3_SPARE3_MASK                                                                 0x00000003
+#define PHY_ANALOG_BIAS3_SPARE3_GET(x)                                                (((x) & 0x00000003) >> 0)
+#define PHY_ANALOG_BIAS3_SPARE3_SET(x)                                                (((x) << 0) & 0x00000003)
+#define PHY_ANALOG_BIAS3_PWD_IR25SAR_MSB                                                                      4
+#define PHY_ANALOG_BIAS3_PWD_IR25SAR_LSB                                                                      2
+#define PHY_ANALOG_BIAS3_PWD_IR25SAR_MASK                                                            0x0000001c
+#define PHY_ANALOG_BIAS3_PWD_IR25SAR_GET(x)                                           (((x) & 0x0000001c) >> 2)
+#define PHY_ANALOG_BIAS3_PWD_IR25SAR_SET(x)                                           (((x) << 2) & 0x0000001c)
+#define PHY_ANALOG_BIAS3_PWD_IR25TXRF_MSB                                                                     7
+#define PHY_ANALOG_BIAS3_PWD_IR25TXRF_LSB                                                                     5
+#define PHY_ANALOG_BIAS3_PWD_IR25TXRF_MASK                                                           0x000000e0
+#define PHY_ANALOG_BIAS3_PWD_IR25TXRF_GET(x)                                          (((x) & 0x000000e0) >> 5)
+#define PHY_ANALOG_BIAS3_PWD_IR25TXRF_SET(x)                                          (((x) << 5) & 0x000000e0)
+#define PHY_ANALOG_BIAS3_PWD_IR25RXRF_MSB                                                                    10
+#define PHY_ANALOG_BIAS3_PWD_IR25RXRF_LSB                                                                     8
+#define PHY_ANALOG_BIAS3_PWD_IR25RXRF_MASK                                                           0x00000700
+#define PHY_ANALOG_BIAS3_PWD_IR25RXRF_GET(x)                                          (((x) & 0x00000700) >> 8)
+#define PHY_ANALOG_BIAS3_PWD_IR25RXRF_SET(x)                                          (((x) << 8) & 0x00000700)
+#define PHY_ANALOG_BIAS3_PWD_IR25SYNTH_MSB                                                                   13
+#define PHY_ANALOG_BIAS3_PWD_IR25SYNTH_LSB                                                                   11
+#define PHY_ANALOG_BIAS3_PWD_IR25SYNTH_MASK                                                          0x00003800
+#define PHY_ANALOG_BIAS3_PWD_IR25SYNTH_GET(x)                                        (((x) & 0x00003800) >> 11)
+#define PHY_ANALOG_BIAS3_PWD_IR25SYNTH_SET(x)                                        (((x) << 11) & 0x00003800)
+#define PHY_ANALOG_BIAS3_PWD_IR25PLLREG_MSB                                                                  16
+#define PHY_ANALOG_BIAS3_PWD_IR25PLLREG_LSB                                                                  14
+#define PHY_ANALOG_BIAS3_PWD_IR25PLLREG_MASK                                                         0x0001c000
+#define PHY_ANALOG_BIAS3_PWD_IR25PLLREG_GET(x)                                       (((x) & 0x0001c000) >> 14)
+#define PHY_ANALOG_BIAS3_PWD_IR25PLLREG_SET(x)                                       (((x) << 14) & 0x0001c000)
+#define PHY_ANALOG_BIAS3_PWD_IR25BB_MSB                                                                      19
+#define PHY_ANALOG_BIAS3_PWD_IR25BB_LSB                                                                      17
+#define PHY_ANALOG_BIAS3_PWD_IR25BB_MASK                                                             0x000e0000
+#define PHY_ANALOG_BIAS3_PWD_IR25BB_GET(x)                                           (((x) & 0x000e0000) >> 17)
+#define PHY_ANALOG_BIAS3_PWD_IR25BB_SET(x)                                           (((x) << 17) & 0x000e0000)
+#define PHY_ANALOG_BIAS3_PWD_IR50DAC_MSB                                                                     22
+#define PHY_ANALOG_BIAS3_PWD_IR50DAC_LSB                                                                     20
+#define PHY_ANALOG_BIAS3_PWD_IR50DAC_MASK                                                            0x00700000
+#define PHY_ANALOG_BIAS3_PWD_IR50DAC_GET(x)                                          (((x) & 0x00700000) >> 20)
+#define PHY_ANALOG_BIAS3_PWD_IR50DAC_SET(x)                                          (((x) << 20) & 0x00700000)
+#define PHY_ANALOG_BIAS3_PWD_IR25DAC_MSB                                                                     25
+#define PHY_ANALOG_BIAS3_PWD_IR25DAC_LSB                                                                     23
+#define PHY_ANALOG_BIAS3_PWD_IR25DAC_MASK                                                            0x03800000
+#define PHY_ANALOG_BIAS3_PWD_IR25DAC_GET(x)                                          (((x) & 0x03800000) >> 23)
+#define PHY_ANALOG_BIAS3_PWD_IR25DAC_SET(x)                                          (((x) << 23) & 0x03800000)
+#define PHY_ANALOG_BIAS3_PWD_IR25FIR_MSB                                                                     28
+#define PHY_ANALOG_BIAS3_PWD_IR25FIR_LSB                                                                     26
+#define PHY_ANALOG_BIAS3_PWD_IR25FIR_MASK                                                            0x1c000000
+#define PHY_ANALOG_BIAS3_PWD_IR25FIR_GET(x)                                          (((x) & 0x1c000000) >> 26)
+#define PHY_ANALOG_BIAS3_PWD_IR25FIR_SET(x)                                          (((x) << 26) & 0x1c000000)
+#define PHY_ANALOG_BIAS3_PWD_IR50ADC_MSB                                                                     31
+#define PHY_ANALOG_BIAS3_PWD_IR50ADC_LSB                                                                     29
+#define PHY_ANALOG_BIAS3_PWD_IR50ADC_MASK                                                            0xe0000000
+#define PHY_ANALOG_BIAS3_PWD_IR50ADC_GET(x)                                          (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_BIAS3_PWD_IR50ADC_SET(x)                                          (((x) << 29) & 0xe0000000)
+
+/* macros for BIAS4 */
+#define PHY_ANALOG_BIAS4_ADDRESS                                                                     0x000000cc
+#define PHY_ANALOG_BIAS4_OFFSET                                                                      0x000000cc
+#define PHY_ANALOG_BIAS4_SPARE4_MSB                                                                          10
+#define PHY_ANALOG_BIAS4_SPARE4_LSB                                                                           0
+#define PHY_ANALOG_BIAS4_SPARE4_MASK                                                                 0x000007ff
+#define PHY_ANALOG_BIAS4_SPARE4_GET(x)                                                (((x) & 0x000007ff) >> 0)
+#define PHY_ANALOG_BIAS4_SPARE4_SET(x)                                                (((x) << 0) & 0x000007ff)
+#define PHY_ANALOG_BIAS4_PWD_IR25SPARED_MSB                                                                  13
+#define PHY_ANALOG_BIAS4_PWD_IR25SPARED_LSB                                                                  11
+#define PHY_ANALOG_BIAS4_PWD_IR25SPARED_MASK                                                         0x00003800
+#define PHY_ANALOG_BIAS4_PWD_IR25SPARED_GET(x)                                       (((x) & 0x00003800) >> 11)
+#define PHY_ANALOG_BIAS4_PWD_IR25SPARED_SET(x)                                       (((x) << 11) & 0x00003800)
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREC_MSB                                                                  16
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREC_LSB                                                                  14
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREC_MASK                                                         0x0001c000
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREC_GET(x)                                       (((x) & 0x0001c000) >> 14)
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREC_SET(x)                                       (((x) << 14) & 0x0001c000)
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREB_MSB                                                                  19
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREB_LSB                                                                  17
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREB_MASK                                                         0x000e0000
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREB_GET(x)                                       (((x) & 0x000e0000) >> 17)
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREB_SET(x)                                       (((x) << 17) & 0x000e0000)
+#define PHY_ANALOG_BIAS4_PWD_IR25XPA_MSB                                                                     22
+#define PHY_ANALOG_BIAS4_PWD_IR25XPA_LSB                                                                     20
+#define PHY_ANALOG_BIAS4_PWD_IR25XPA_MASK                                                            0x00700000
+#define PHY_ANALOG_BIAS4_PWD_IR25XPA_GET(x)                                          (((x) & 0x00700000) >> 20)
+#define PHY_ANALOG_BIAS4_PWD_IR25XPA_SET(x)                                          (((x) << 20) & 0x00700000)
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREC_MSB                                                                  25
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREC_LSB                                                                  23
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREC_MASK                                                         0x03800000
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREC_GET(x)                                       (((x) & 0x03800000) >> 23)
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREC_SET(x)                                       (((x) << 23) & 0x03800000)
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREB_MSB                                                                  28
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREB_LSB                                                                  26
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREB_MASK                                                         0x1c000000
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREB_GET(x)                                       (((x) & 0x1c000000) >> 26)
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREB_SET(x)                                       (((x) << 26) & 0x1c000000)
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREA_MSB                                                                  31
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREA_LSB                                                                  29
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREA_MASK                                                         0xe0000000
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREA_GET(x)                                       (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREA_SET(x)                                       (((x) << 29) & 0xe0000000)
+
+/* macros for RXTX1 */
+#define PHY_ANALOG_RXTX1_ADDRESS                                                                     0x00000100
+#define PHY_ANALOG_RXTX1_OFFSET                                                                      0x00000100
+#define PHY_ANALOG_RXTX1_SCFIR_GAIN_MSB                                                                       0
+#define PHY_ANALOG_RXTX1_SCFIR_GAIN_LSB                                                                       0
+#define PHY_ANALOG_RXTX1_SCFIR_GAIN_MASK                                                             0x00000001
+#define PHY_ANALOG_RXTX1_SCFIR_GAIN_GET(x)                                            (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_RXTX1_SCFIR_GAIN_SET(x)                                            (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_RXTX1_MANRXGAIN_MSB                                                                        1
+#define PHY_ANALOG_RXTX1_MANRXGAIN_LSB                                                                        1
+#define PHY_ANALOG_RXTX1_MANRXGAIN_MASK                                                              0x00000002
+#define PHY_ANALOG_RXTX1_MANRXGAIN_GET(x)                                             (((x) & 0x00000002) >> 1)
+#define PHY_ANALOG_RXTX1_MANRXGAIN_SET(x)                                             (((x) << 1) & 0x00000002)
+#define PHY_ANALOG_RXTX1_AGC_DBDAC_MSB                                                                        5
+#define PHY_ANALOG_RXTX1_AGC_DBDAC_LSB                                                                        2
+#define PHY_ANALOG_RXTX1_AGC_DBDAC_MASK                                                              0x0000003c
+#define PHY_ANALOG_RXTX1_AGC_DBDAC_GET(x)                                             (((x) & 0x0000003c) >> 2)
+#define PHY_ANALOG_RXTX1_AGC_DBDAC_SET(x)                                             (((x) << 2) & 0x0000003c)
+#define PHY_ANALOG_RXTX1_OVR_AGC_DBDAC_MSB                                                                    6
+#define PHY_ANALOG_RXTX1_OVR_AGC_DBDAC_LSB                                                                    6
+#define PHY_ANALOG_RXTX1_OVR_AGC_DBDAC_MASK                                                          0x00000040
+#define PHY_ANALOG_RXTX1_OVR_AGC_DBDAC_GET(x)                                         (((x) & 0x00000040) >> 6)
+#define PHY_ANALOG_RXTX1_OVR_AGC_DBDAC_SET(x)                                         (((x) << 6) & 0x00000040)
+#define PHY_ANALOG_RXTX1_ENABLE_PAL_MSB                                                                       7
+#define PHY_ANALOG_RXTX1_ENABLE_PAL_LSB                                                                       7
+#define PHY_ANALOG_RXTX1_ENABLE_PAL_MASK                                                             0x00000080
+#define PHY_ANALOG_RXTX1_ENABLE_PAL_GET(x)                                            (((x) & 0x00000080) >> 7)
+#define PHY_ANALOG_RXTX1_ENABLE_PAL_SET(x)                                            (((x) << 7) & 0x00000080)
+#define PHY_ANALOG_RXTX1_ENABLE_PAL_OVR_MSB                                                                   8
+#define PHY_ANALOG_RXTX1_ENABLE_PAL_OVR_LSB                                                                   8
+#define PHY_ANALOG_RXTX1_ENABLE_PAL_OVR_MASK                                                         0x00000100
+#define PHY_ANALOG_RXTX1_ENABLE_PAL_OVR_GET(x)                                        (((x) & 0x00000100) >> 8)
+#define PHY_ANALOG_RXTX1_ENABLE_PAL_OVR_SET(x)                                        (((x) << 8) & 0x00000100)
+#define PHY_ANALOG_RXTX1_TX1DB_BIQUAD_MSB                                                                    11
+#define PHY_ANALOG_RXTX1_TX1DB_BIQUAD_LSB                                                                     9
+#define PHY_ANALOG_RXTX1_TX1DB_BIQUAD_MASK                                                           0x00000e00
+#define PHY_ANALOG_RXTX1_TX1DB_BIQUAD_GET(x)                                          (((x) & 0x00000e00) >> 9)
+#define PHY_ANALOG_RXTX1_TX1DB_BIQUAD_SET(x)                                          (((x) << 9) & 0x00000e00)
+#define PHY_ANALOG_RXTX1_TX6DB_BIQUAD_MSB                                                                    13
+#define PHY_ANALOG_RXTX1_TX6DB_BIQUAD_LSB                                                                    12
+#define PHY_ANALOG_RXTX1_TX6DB_BIQUAD_MASK                                                           0x00003000
+#define PHY_ANALOG_RXTX1_TX6DB_BIQUAD_GET(x)                                         (((x) & 0x00003000) >> 12)
+#define PHY_ANALOG_RXTX1_TX6DB_BIQUAD_SET(x)                                         (((x) << 12) & 0x00003000)
+#define PHY_ANALOG_RXTX1_PADRVHALFGN2G_MSB                                                                   14
+#define PHY_ANALOG_RXTX1_PADRVHALFGN2G_LSB                                                                   14
+#define PHY_ANALOG_RXTX1_PADRVHALFGN2G_MASK                                                          0x00004000
+#define PHY_ANALOG_RXTX1_PADRVHALFGN2G_GET(x)                                        (((x) & 0x00004000) >> 14)
+#define PHY_ANALOG_RXTX1_PADRVHALFGN2G_SET(x)                                        (((x) << 14) & 0x00004000)
+#define PHY_ANALOG_RXTX1_PADRV2GN_MSB                                                                        18
+#define PHY_ANALOG_RXTX1_PADRV2GN_LSB                                                                        15
+#define PHY_ANALOG_RXTX1_PADRV2GN_MASK                                                               0x00078000
+#define PHY_ANALOG_RXTX1_PADRV2GN_GET(x)                                             (((x) & 0x00078000) >> 15)
+#define PHY_ANALOG_RXTX1_PADRV2GN_SET(x)                                             (((x) << 15) & 0x00078000)
+#define PHY_ANALOG_RXTX1_PADRV3GN5G_MSB                                                                      22
+#define PHY_ANALOG_RXTX1_PADRV3GN5G_LSB                                                                      19
+#define PHY_ANALOG_RXTX1_PADRV3GN5G_MASK                                                             0x00780000
+#define PHY_ANALOG_RXTX1_PADRV3GN5G_GET(x)                                           (((x) & 0x00780000) >> 19)
+#define PHY_ANALOG_RXTX1_PADRV3GN5G_SET(x)                                           (((x) << 19) & 0x00780000)
+#define PHY_ANALOG_RXTX1_PADRV4GN5G_MSB                                                                      26
+#define PHY_ANALOG_RXTX1_PADRV4GN5G_LSB                                                                      23
+#define PHY_ANALOG_RXTX1_PADRV4GN5G_MASK                                                             0x07800000
+#define PHY_ANALOG_RXTX1_PADRV4GN5G_GET(x)                                           (((x) & 0x07800000) >> 23)
+#define PHY_ANALOG_RXTX1_PADRV4GN5G_SET(x)                                           (((x) << 23) & 0x07800000)
+#define PHY_ANALOG_RXTX1_TXBB_GC_MSB                                                                         30
+#define PHY_ANALOG_RXTX1_TXBB_GC_LSB                                                                         27
+#define PHY_ANALOG_RXTX1_TXBB_GC_MASK                                                                0x78000000
+#define PHY_ANALOG_RXTX1_TXBB_GC_GET(x)                                              (((x) & 0x78000000) >> 27)
+#define PHY_ANALOG_RXTX1_TXBB_GC_SET(x)                                              (((x) << 27) & 0x78000000)
+#define PHY_ANALOG_RXTX1_MANTXGAIN_MSB                                                                       31
+#define PHY_ANALOG_RXTX1_MANTXGAIN_LSB                                                                       31
+#define PHY_ANALOG_RXTX1_MANTXGAIN_MASK                                                              0x80000000
+#define PHY_ANALOG_RXTX1_MANTXGAIN_GET(x)                                            (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_RXTX1_MANTXGAIN_SET(x)                                            (((x) << 31) & 0x80000000)
+
+/* macros for RXTX2 */
+#define PHY_ANALOG_RXTX2_ADDRESS                                                                     0x00000104
+#define PHY_ANALOG_RXTX2_OFFSET                                                                      0x00000104
+#define PHY_ANALOG_RXTX2_BMODE_MSB                                                                            0
+#define PHY_ANALOG_RXTX2_BMODE_LSB                                                                            0
+#define PHY_ANALOG_RXTX2_BMODE_MASK                                                                  0x00000001
+#define PHY_ANALOG_RXTX2_BMODE_GET(x)                                                 (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_RXTX2_BMODE_SET(x)                                                 (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_RXTX2_BMODE_OVR_MSB                                                                        1
+#define PHY_ANALOG_RXTX2_BMODE_OVR_LSB                                                                        1
+#define PHY_ANALOG_RXTX2_BMODE_OVR_MASK                                                              0x00000002
+#define PHY_ANALOG_RXTX2_BMODE_OVR_GET(x)                                             (((x) & 0x00000002) >> 1)
+#define PHY_ANALOG_RXTX2_BMODE_OVR_SET(x)                                             (((x) << 1) & 0x00000002)
+#define PHY_ANALOG_RXTX2_SYNTHON_MSB                                                                          2
+#define PHY_ANALOG_RXTX2_SYNTHON_LSB                                                                          2
+#define PHY_ANALOG_RXTX2_SYNTHON_MASK                                                                0x00000004
+#define PHY_ANALOG_RXTX2_SYNTHON_GET(x)                                               (((x) & 0x00000004) >> 2)
+#define PHY_ANALOG_RXTX2_SYNTHON_SET(x)                                               (((x) << 2) & 0x00000004)
+#define PHY_ANALOG_RXTX2_SYNTHON_OVR_MSB                                                                      3
+#define PHY_ANALOG_RXTX2_SYNTHON_OVR_LSB                                                                      3
+#define PHY_ANALOG_RXTX2_SYNTHON_OVR_MASK                                                            0x00000008
+#define PHY_ANALOG_RXTX2_SYNTHON_OVR_GET(x)                                           (((x) & 0x00000008) >> 3)
+#define PHY_ANALOG_RXTX2_SYNTHON_OVR_SET(x)                                           (((x) << 3) & 0x00000008)
+#define PHY_ANALOG_RXTX2_BW_ST_MSB                                                                            5
+#define PHY_ANALOG_RXTX2_BW_ST_LSB                                                                            4
+#define PHY_ANALOG_RXTX2_BW_ST_MASK                                                                  0x00000030
+#define PHY_ANALOG_RXTX2_BW_ST_GET(x)                                                 (((x) & 0x00000030) >> 4)
+#define PHY_ANALOG_RXTX2_BW_ST_SET(x)                                                 (((x) << 4) & 0x00000030)
+#define PHY_ANALOG_RXTX2_BW_ST_OVR_MSB                                                                        6
+#define PHY_ANALOG_RXTX2_BW_ST_OVR_LSB                                                                        6
+#define PHY_ANALOG_RXTX2_BW_ST_OVR_MASK                                                              0x00000040
+#define PHY_ANALOG_RXTX2_BW_ST_OVR_GET(x)                                             (((x) & 0x00000040) >> 6)
+#define PHY_ANALOG_RXTX2_BW_ST_OVR_SET(x)                                             (((x) << 6) & 0x00000040)
+#define PHY_ANALOG_RXTX2_TXON_MSB                                                                             7
+#define PHY_ANALOG_RXTX2_TXON_LSB                                                                             7
+#define PHY_ANALOG_RXTX2_TXON_MASK                                                                   0x00000080
+#define PHY_ANALOG_RXTX2_TXON_GET(x)                                                  (((x) & 0x00000080) >> 7)
+#define PHY_ANALOG_RXTX2_TXON_SET(x)                                                  (((x) << 7) & 0x00000080)
+#define PHY_ANALOG_RXTX2_TXON_OVR_MSB                                                                         8
+#define PHY_ANALOG_RXTX2_TXON_OVR_LSB                                                                         8
+#define PHY_ANALOG_RXTX2_TXON_OVR_MASK                                                               0x00000100
+#define PHY_ANALOG_RXTX2_TXON_OVR_GET(x)                                              (((x) & 0x00000100) >> 8)
+#define PHY_ANALOG_RXTX2_TXON_OVR_SET(x)                                              (((x) << 8) & 0x00000100)
+#define PHY_ANALOG_RXTX2_PAON_MSB                                                                             9
+#define PHY_ANALOG_RXTX2_PAON_LSB                                                                             9
+#define PHY_ANALOG_RXTX2_PAON_MASK                                                                   0x00000200
+#define PHY_ANALOG_RXTX2_PAON_GET(x)                                                  (((x) & 0x00000200) >> 9)
+#define PHY_ANALOG_RXTX2_PAON_SET(x)                                                  (((x) << 9) & 0x00000200)
+#define PHY_ANALOG_RXTX2_PAON_OVR_MSB                                                                        10
+#define PHY_ANALOG_RXTX2_PAON_OVR_LSB                                                                        10
+#define PHY_ANALOG_RXTX2_PAON_OVR_MASK                                                               0x00000400
+#define PHY_ANALOG_RXTX2_PAON_OVR_GET(x)                                             (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_RXTX2_PAON_OVR_SET(x)                                             (((x) << 10) & 0x00000400)
+#define PHY_ANALOG_RXTX2_RXON_MSB                                                                            11
+#define PHY_ANALOG_RXTX2_RXON_LSB                                                                            11
+#define PHY_ANALOG_RXTX2_RXON_MASK                                                                   0x00000800
+#define PHY_ANALOG_RXTX2_RXON_GET(x)                                                 (((x) & 0x00000800) >> 11)
+#define PHY_ANALOG_RXTX2_RXON_SET(x)                                                 (((x) << 11) & 0x00000800)
+#define PHY_ANALOG_RXTX2_RXON_OVR_MSB                                                                        12
+#define PHY_ANALOG_RXTX2_RXON_OVR_LSB                                                                        12
+#define PHY_ANALOG_RXTX2_RXON_OVR_MASK                                                               0x00001000
+#define PHY_ANALOG_RXTX2_RXON_OVR_GET(x)                                             (((x) & 0x00001000) >> 12)
+#define PHY_ANALOG_RXTX2_RXON_OVR_SET(x)                                             (((x) << 12) & 0x00001000)
+#define PHY_ANALOG_RXTX2_AGCON_MSB                                                                           13
+#define PHY_ANALOG_RXTX2_AGCON_LSB                                                                           13
+#define PHY_ANALOG_RXTX2_AGCON_MASK                                                                  0x00002000
+#define PHY_ANALOG_RXTX2_AGCON_GET(x)                                                (((x) & 0x00002000) >> 13)
+#define PHY_ANALOG_RXTX2_AGCON_SET(x)                                                (((x) << 13) & 0x00002000)
+#define PHY_ANALOG_RXTX2_AGCON_OVR_MSB                                                                       14
+#define PHY_ANALOG_RXTX2_AGCON_OVR_LSB                                                                       14
+#define PHY_ANALOG_RXTX2_AGCON_OVR_MASK                                                              0x00004000
+#define PHY_ANALOG_RXTX2_AGCON_OVR_GET(x)                                            (((x) & 0x00004000) >> 14)
+#define PHY_ANALOG_RXTX2_AGCON_OVR_SET(x)                                            (((x) << 14) & 0x00004000)
+#define PHY_ANALOG_RXTX2_TXMOD_MSB                                                                           17
+#define PHY_ANALOG_RXTX2_TXMOD_LSB                                                                           15
+#define PHY_ANALOG_RXTX2_TXMOD_MASK                                                                  0x00038000
+#define PHY_ANALOG_RXTX2_TXMOD_GET(x)                                                (((x) & 0x00038000) >> 15)
+#define PHY_ANALOG_RXTX2_TXMOD_SET(x)                                                (((x) << 15) & 0x00038000)
+#define PHY_ANALOG_RXTX2_TXMOD_OVR_MSB                                                                       18
+#define PHY_ANALOG_RXTX2_TXMOD_OVR_LSB                                                                       18
+#define PHY_ANALOG_RXTX2_TXMOD_OVR_MASK                                                              0x00040000
+#define PHY_ANALOG_RXTX2_TXMOD_OVR_GET(x)                                            (((x) & 0x00040000) >> 18)
+#define PHY_ANALOG_RXTX2_TXMOD_OVR_SET(x)                                            (((x) << 18) & 0x00040000)
+#define PHY_ANALOG_RXTX2_RX1DB_BIQUAD_MSB                                                                    21
+#define PHY_ANALOG_RXTX2_RX1DB_BIQUAD_LSB                                                                    19
+#define PHY_ANALOG_RXTX2_RX1DB_BIQUAD_MASK                                                           0x00380000
+#define PHY_ANALOG_RXTX2_RX1DB_BIQUAD_GET(x)                                         (((x) & 0x00380000) >> 19)
+#define PHY_ANALOG_RXTX2_RX1DB_BIQUAD_SET(x)                                         (((x) << 19) & 0x00380000)
+#define PHY_ANALOG_RXTX2_RX6DB_BIQUAD_MSB                                                                    23
+#define PHY_ANALOG_RXTX2_RX6DB_BIQUAD_LSB                                                                    22
+#define PHY_ANALOG_RXTX2_RX6DB_BIQUAD_MASK                                                           0x00c00000
+#define PHY_ANALOG_RXTX2_RX6DB_BIQUAD_GET(x)                                         (((x) & 0x00c00000) >> 22)
+#define PHY_ANALOG_RXTX2_RX6DB_BIQUAD_SET(x)                                         (((x) << 22) & 0x00c00000)
+#define PHY_ANALOG_RXTX2_MXRGAIN_MSB                                                                         25
+#define PHY_ANALOG_RXTX2_MXRGAIN_LSB                                                                         24
+#define PHY_ANALOG_RXTX2_MXRGAIN_MASK                                                                0x03000000
+#define PHY_ANALOG_RXTX2_MXRGAIN_GET(x)                                              (((x) & 0x03000000) >> 24)
+#define PHY_ANALOG_RXTX2_MXRGAIN_SET(x)                                              (((x) << 24) & 0x03000000)
+#define PHY_ANALOG_RXTX2_VGAGAIN_MSB                                                                         28
+#define PHY_ANALOG_RXTX2_VGAGAIN_LSB                                                                         26
+#define PHY_ANALOG_RXTX2_VGAGAIN_MASK                                                                0x1c000000
+#define PHY_ANALOG_RXTX2_VGAGAIN_GET(x)                                              (((x) & 0x1c000000) >> 26)
+#define PHY_ANALOG_RXTX2_VGAGAIN_SET(x)                                              (((x) << 26) & 0x1c000000)
+#define PHY_ANALOG_RXTX2_LNAGAIN_MSB                                                                         31
+#define PHY_ANALOG_RXTX2_LNAGAIN_LSB                                                                         29
+#define PHY_ANALOG_RXTX2_LNAGAIN_MASK                                                                0xe0000000
+#define PHY_ANALOG_RXTX2_LNAGAIN_GET(x)                                              (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_RXTX2_LNAGAIN_SET(x)                                              (((x) << 29) & 0xe0000000)
+
+/* macros for RXTX3 */
+#define PHY_ANALOG_RXTX3_ADDRESS                                                                     0x00000108
+#define PHY_ANALOG_RXTX3_OFFSET                                                                      0x00000108
+#define PHY_ANALOG_RXTX3_SPARE3_MSB                                                                           2
+#define PHY_ANALOG_RXTX3_SPARE3_LSB                                                                           0
+#define PHY_ANALOG_RXTX3_SPARE3_MASK                                                                 0x00000007
+#define PHY_ANALOG_RXTX3_SPARE3_GET(x)                                                (((x) & 0x00000007) >> 0)
+#define PHY_ANALOG_RXTX3_SPARE3_SET(x)                                                (((x) << 0) & 0x00000007)
+#define PHY_ANALOG_RXTX3_SPURON_MSB                                                                           3
+#define PHY_ANALOG_RXTX3_SPURON_LSB                                                                           3
+#define PHY_ANALOG_RXTX3_SPURON_MASK                                                                 0x00000008
+#define PHY_ANALOG_RXTX3_SPURON_GET(x)                                                (((x) & 0x00000008) >> 3)
+#define PHY_ANALOG_RXTX3_SPURON_SET(x)                                                (((x) << 3) & 0x00000008)
+#define PHY_ANALOG_RXTX3_PAL_LOCKEDEN_MSB                                                                     4
+#define PHY_ANALOG_RXTX3_PAL_LOCKEDEN_LSB                                                                     4
+#define PHY_ANALOG_RXTX3_PAL_LOCKEDEN_MASK                                                           0x00000010
+#define PHY_ANALOG_RXTX3_PAL_LOCKEDEN_GET(x)                                          (((x) & 0x00000010) >> 4)
+#define PHY_ANALOG_RXTX3_PAL_LOCKEDEN_SET(x)                                          (((x) << 4) & 0x00000010)
+#define PHY_ANALOG_RXTX3_DACFULLSCALE_MSB                                                                     5
+#define PHY_ANALOG_RXTX3_DACFULLSCALE_LSB                                                                     5
+#define PHY_ANALOG_RXTX3_DACFULLSCALE_MASK                                                           0x00000020
+#define PHY_ANALOG_RXTX3_DACFULLSCALE_GET(x)                                          (((x) & 0x00000020) >> 5)
+#define PHY_ANALOG_RXTX3_DACFULLSCALE_SET(x)                                          (((x) << 5) & 0x00000020)
+#define PHY_ANALOG_RXTX3_ADCSHORT_MSB                                                                         6
+#define PHY_ANALOG_RXTX3_ADCSHORT_LSB                                                                         6
+#define PHY_ANALOG_RXTX3_ADCSHORT_MASK                                                               0x00000040
+#define PHY_ANALOG_RXTX3_ADCSHORT_GET(x)                                              (((x) & 0x00000040) >> 6)
+#define PHY_ANALOG_RXTX3_ADCSHORT_SET(x)                                              (((x) << 6) & 0x00000040)
+#define PHY_ANALOG_RXTX3_DACPWD_MSB                                                                           7
+#define PHY_ANALOG_RXTX3_DACPWD_LSB                                                                           7
+#define PHY_ANALOG_RXTX3_DACPWD_MASK                                                                 0x00000080
+#define PHY_ANALOG_RXTX3_DACPWD_GET(x)                                                (((x) & 0x00000080) >> 7)
+#define PHY_ANALOG_RXTX3_DACPWD_SET(x)                                                (((x) << 7) & 0x00000080)
+#define PHY_ANALOG_RXTX3_DACPWD_OVR_MSB                                                                       8
+#define PHY_ANALOG_RXTX3_DACPWD_OVR_LSB                                                                       8
+#define PHY_ANALOG_RXTX3_DACPWD_OVR_MASK                                                             0x00000100
+#define PHY_ANALOG_RXTX3_DACPWD_OVR_GET(x)                                            (((x) & 0x00000100) >> 8)
+#define PHY_ANALOG_RXTX3_DACPWD_OVR_SET(x)                                            (((x) << 8) & 0x00000100)
+#define PHY_ANALOG_RXTX3_ADCPWD_MSB                                                                           9
+#define PHY_ANALOG_RXTX3_ADCPWD_LSB                                                                           9
+#define PHY_ANALOG_RXTX3_ADCPWD_MASK                                                                 0x00000200
+#define PHY_ANALOG_RXTX3_ADCPWD_GET(x)                                                (((x) & 0x00000200) >> 9)
+#define PHY_ANALOG_RXTX3_ADCPWD_SET(x)                                                (((x) << 9) & 0x00000200)
+#define PHY_ANALOG_RXTX3_ADCPWD_OVR_MSB                                                                      10
+#define PHY_ANALOG_RXTX3_ADCPWD_OVR_LSB                                                                      10
+#define PHY_ANALOG_RXTX3_ADCPWD_OVR_MASK                                                             0x00000400
+#define PHY_ANALOG_RXTX3_ADCPWD_OVR_GET(x)                                           (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_RXTX3_ADCPWD_OVR_SET(x)                                           (((x) << 10) & 0x00000400)
+#define PHY_ANALOG_RXTX3_AGC_CALDAC_MSB                                                                      16
+#define PHY_ANALOG_RXTX3_AGC_CALDAC_LSB                                                                      11
+#define PHY_ANALOG_RXTX3_AGC_CALDAC_MASK                                                             0x0001f800
+#define PHY_ANALOG_RXTX3_AGC_CALDAC_GET(x)                                           (((x) & 0x0001f800) >> 11)
+#define PHY_ANALOG_RXTX3_AGC_CALDAC_SET(x)                                           (((x) << 11) & 0x0001f800)
+#define PHY_ANALOG_RXTX3_AGC_CAL_MSB                                                                         17
+#define PHY_ANALOG_RXTX3_AGC_CAL_LSB                                                                         17
+#define PHY_ANALOG_RXTX3_AGC_CAL_MASK                                                                0x00020000
+#define PHY_ANALOG_RXTX3_AGC_CAL_GET(x)                                              (((x) & 0x00020000) >> 17)
+#define PHY_ANALOG_RXTX3_AGC_CAL_SET(x)                                              (((x) << 17) & 0x00020000)
+#define PHY_ANALOG_RXTX3_AGC_CAL_OVR_MSB                                                                     18
+#define PHY_ANALOG_RXTX3_AGC_CAL_OVR_LSB                                                                     18
+#define PHY_ANALOG_RXTX3_AGC_CAL_OVR_MASK                                                            0x00040000
+#define PHY_ANALOG_RXTX3_AGC_CAL_OVR_GET(x)                                          (((x) & 0x00040000) >> 18)
+#define PHY_ANALOG_RXTX3_AGC_CAL_OVR_SET(x)                                          (((x) << 18) & 0x00040000)
+#define PHY_ANALOG_RXTX3_LOFORCEDON_MSB                                                                      19
+#define PHY_ANALOG_RXTX3_LOFORCEDON_LSB                                                                      19
+#define PHY_ANALOG_RXTX3_LOFORCEDON_MASK                                                             0x00080000
+#define PHY_ANALOG_RXTX3_LOFORCEDON_GET(x)                                           (((x) & 0x00080000) >> 19)
+#define PHY_ANALOG_RXTX3_LOFORCEDON_SET(x)                                           (((x) << 19) & 0x00080000)
+#define PHY_ANALOG_RXTX3_CALRESIDUE_MSB                                                                      20
+#define PHY_ANALOG_RXTX3_CALRESIDUE_LSB                                                                      20
+#define PHY_ANALOG_RXTX3_CALRESIDUE_MASK                                                             0x00100000
+#define PHY_ANALOG_RXTX3_CALRESIDUE_GET(x)                                           (((x) & 0x00100000) >> 20)
+#define PHY_ANALOG_RXTX3_CALRESIDUE_SET(x)                                           (((x) << 20) & 0x00100000)
+#define PHY_ANALOG_RXTX3_CALRESIDUE_OVR_MSB                                                                  21
+#define PHY_ANALOG_RXTX3_CALRESIDUE_OVR_LSB                                                                  21
+#define PHY_ANALOG_RXTX3_CALRESIDUE_OVR_MASK                                                         0x00200000
+#define PHY_ANALOG_RXTX3_CALRESIDUE_OVR_GET(x)                                       (((x) & 0x00200000) >> 21)
+#define PHY_ANALOG_RXTX3_CALRESIDUE_OVR_SET(x)                                       (((x) << 21) & 0x00200000)
+#define PHY_ANALOG_RXTX3_CALFC_MSB                                                                           22
+#define PHY_ANALOG_RXTX3_CALFC_LSB                                                                           22
+#define PHY_ANALOG_RXTX3_CALFC_MASK                                                                  0x00400000
+#define PHY_ANALOG_RXTX3_CALFC_GET(x)                                                (((x) & 0x00400000) >> 22)
+#define PHY_ANALOG_RXTX3_CALFC_SET(x)                                                (((x) << 22) & 0x00400000)
+#define PHY_ANALOG_RXTX3_CALFC_OVR_MSB                                                                       23
+#define PHY_ANALOG_RXTX3_CALFC_OVR_LSB                                                                       23
+#define PHY_ANALOG_RXTX3_CALFC_OVR_MASK                                                              0x00800000
+#define PHY_ANALOG_RXTX3_CALFC_OVR_GET(x)                                            (((x) & 0x00800000) >> 23)
+#define PHY_ANALOG_RXTX3_CALFC_OVR_SET(x)                                            (((x) << 23) & 0x00800000)
+#define PHY_ANALOG_RXTX3_CALTX_MSB                                                                           24
+#define PHY_ANALOG_RXTX3_CALTX_LSB                                                                           24
+#define PHY_ANALOG_RXTX3_CALTX_MASK                                                                  0x01000000
+#define PHY_ANALOG_RXTX3_CALTX_GET(x)                                                (((x) & 0x01000000) >> 24)
+#define PHY_ANALOG_RXTX3_CALTX_SET(x)                                                (((x) << 24) & 0x01000000)
+#define PHY_ANALOG_RXTX3_CALTX_OVR_MSB                                                                       25
+#define PHY_ANALOG_RXTX3_CALTX_OVR_LSB                                                                       25
+#define PHY_ANALOG_RXTX3_CALTX_OVR_MASK                                                              0x02000000
+#define PHY_ANALOG_RXTX3_CALTX_OVR_GET(x)                                            (((x) & 0x02000000) >> 25)
+#define PHY_ANALOG_RXTX3_CALTX_OVR_SET(x)                                            (((x) << 25) & 0x02000000)
+#define PHY_ANALOG_RXTX3_CALTXSHIFT_MSB                                                                      26
+#define PHY_ANALOG_RXTX3_CALTXSHIFT_LSB                                                                      26
+#define PHY_ANALOG_RXTX3_CALTXSHIFT_MASK                                                             0x04000000
+#define PHY_ANALOG_RXTX3_CALTXSHIFT_GET(x)                                           (((x) & 0x04000000) >> 26)
+#define PHY_ANALOG_RXTX3_CALTXSHIFT_SET(x)                                           (((x) << 26) & 0x04000000)
+#define PHY_ANALOG_RXTX3_CALTXSHIFT_OVR_MSB                                                                  27
+#define PHY_ANALOG_RXTX3_CALTXSHIFT_OVR_LSB                                                                  27
+#define PHY_ANALOG_RXTX3_CALTXSHIFT_OVR_MASK                                                         0x08000000
+#define PHY_ANALOG_RXTX3_CALTXSHIFT_OVR_GET(x)                                       (((x) & 0x08000000) >> 27)
+#define PHY_ANALOG_RXTX3_CALTXSHIFT_OVR_SET(x)                                       (((x) << 27) & 0x08000000)
+#define PHY_ANALOG_RXTX3_CALPA_MSB                                                                           28
+#define PHY_ANALOG_RXTX3_CALPA_LSB                                                                           28
+#define PHY_ANALOG_RXTX3_CALPA_MASK                                                                  0x10000000
+#define PHY_ANALOG_RXTX3_CALPA_GET(x)                                                (((x) & 0x10000000) >> 28)
+#define PHY_ANALOG_RXTX3_CALPA_SET(x)                                                (((x) << 28) & 0x10000000)
+#define PHY_ANALOG_RXTX3_CALPA_OVR_MSB                                                                       29
+#define PHY_ANALOG_RXTX3_CALPA_OVR_LSB                                                                       29
+#define PHY_ANALOG_RXTX3_CALPA_OVR_MASK                                                              0x20000000
+#define PHY_ANALOG_RXTX3_CALPA_OVR_GET(x)                                            (((x) & 0x20000000) >> 29)
+#define PHY_ANALOG_RXTX3_CALPA_OVR_SET(x)                                            (((x) << 29) & 0x20000000)
+#define PHY_ANALOG_RXTX3_TURBOADC_MSB                                                                        30
+#define PHY_ANALOG_RXTX3_TURBOADC_LSB                                                                        30
+#define PHY_ANALOG_RXTX3_TURBOADC_MASK                                                               0x40000000
+#define PHY_ANALOG_RXTX3_TURBOADC_GET(x)                                             (((x) & 0x40000000) >> 30)
+#define PHY_ANALOG_RXTX3_TURBOADC_SET(x)                                             (((x) << 30) & 0x40000000)
+#define PHY_ANALOG_RXTX3_TURBOADC_OVR_MSB                                                                    31
+#define PHY_ANALOG_RXTX3_TURBOADC_OVR_LSB                                                                    31
+#define PHY_ANALOG_RXTX3_TURBOADC_OVR_MASK                                                           0x80000000
+#define PHY_ANALOG_RXTX3_TURBOADC_OVR_GET(x)                                         (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_RXTX3_TURBOADC_OVR_SET(x)                                         (((x) << 31) & 0x80000000)
+
+/* macros for BB1 */
+#define PHY_ANALOG_BB1_ADDRESS                                                                       0x00000140
+#define PHY_ANALOG_BB1_OFFSET                                                                        0x00000140
+#define PHY_ANALOG_BB1_I2V_CURR2X_MSB                                                                         0
+#define PHY_ANALOG_BB1_I2V_CURR2X_LSB                                                                         0
+#define PHY_ANALOG_BB1_I2V_CURR2X_MASK                                                               0x00000001
+#define PHY_ANALOG_BB1_I2V_CURR2X_GET(x)                                              (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_BB1_I2V_CURR2X_SET(x)                                              (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_BB1_ENABLE_LOQ_MSB                                                                         1
+#define PHY_ANALOG_BB1_ENABLE_LOQ_LSB                                                                         1
+#define PHY_ANALOG_BB1_ENABLE_LOQ_MASK                                                               0x00000002
+#define PHY_ANALOG_BB1_ENABLE_LOQ_GET(x)                                              (((x) & 0x00000002) >> 1)
+#define PHY_ANALOG_BB1_ENABLE_LOQ_SET(x)                                              (((x) << 1) & 0x00000002)
+#define PHY_ANALOG_BB1_FORCE_LOQ_MSB                                                                          2
+#define PHY_ANALOG_BB1_FORCE_LOQ_LSB                                                                          2
+#define PHY_ANALOG_BB1_FORCE_LOQ_MASK                                                                0x00000004
+#define PHY_ANALOG_BB1_FORCE_LOQ_GET(x)                                               (((x) & 0x00000004) >> 2)
+#define PHY_ANALOG_BB1_FORCE_LOQ_SET(x)                                               (((x) << 2) & 0x00000004)
+#define PHY_ANALOG_BB1_ENABLE_NOTCH_MSB                                                                       3
+#define PHY_ANALOG_BB1_ENABLE_NOTCH_LSB                                                                       3
+#define PHY_ANALOG_BB1_ENABLE_NOTCH_MASK                                                             0x00000008
+#define PHY_ANALOG_BB1_ENABLE_NOTCH_GET(x)                                            (((x) & 0x00000008) >> 3)
+#define PHY_ANALOG_BB1_ENABLE_NOTCH_SET(x)                                            (((x) << 3) & 0x00000008)
+#define PHY_ANALOG_BB1_FORCE_NOTCH_MSB                                                                        4
+#define PHY_ANALOG_BB1_FORCE_NOTCH_LSB                                                                        4
+#define PHY_ANALOG_BB1_FORCE_NOTCH_MASK                                                              0x00000010
+#define PHY_ANALOG_BB1_FORCE_NOTCH_GET(x)                                             (((x) & 0x00000010) >> 4)
+#define PHY_ANALOG_BB1_FORCE_NOTCH_SET(x)                                             (((x) << 4) & 0x00000010)
+#define PHY_ANALOG_BB1_ENABLE_BIQUAD_MSB                                                                      5
+#define PHY_ANALOG_BB1_ENABLE_BIQUAD_LSB                                                                      5
+#define PHY_ANALOG_BB1_ENABLE_BIQUAD_MASK                                                            0x00000020
+#define PHY_ANALOG_BB1_ENABLE_BIQUAD_GET(x)                                           (((x) & 0x00000020) >> 5)
+#define PHY_ANALOG_BB1_ENABLE_BIQUAD_SET(x)                                           (((x) << 5) & 0x00000020)
+#define PHY_ANALOG_BB1_FORCE_BIQUAD_MSB                                                                       6
+#define PHY_ANALOG_BB1_FORCE_BIQUAD_LSB                                                                       6
+#define PHY_ANALOG_BB1_FORCE_BIQUAD_MASK                                                             0x00000040
+#define PHY_ANALOG_BB1_FORCE_BIQUAD_GET(x)                                            (((x) & 0x00000040) >> 6)
+#define PHY_ANALOG_BB1_FORCE_BIQUAD_SET(x)                                            (((x) << 6) & 0x00000040)
+#define PHY_ANALOG_BB1_ENABLE_OSDAC_MSB                                                                       7
+#define PHY_ANALOG_BB1_ENABLE_OSDAC_LSB                                                                       7
+#define PHY_ANALOG_BB1_ENABLE_OSDAC_MASK                                                             0x00000080
+#define PHY_ANALOG_BB1_ENABLE_OSDAC_GET(x)                                            (((x) & 0x00000080) >> 7)
+#define PHY_ANALOG_BB1_ENABLE_OSDAC_SET(x)                                            (((x) << 7) & 0x00000080)
+#define PHY_ANALOG_BB1_FORCE_OSDAC_MSB                                                                        8
+#define PHY_ANALOG_BB1_FORCE_OSDAC_LSB                                                                        8
+#define PHY_ANALOG_BB1_FORCE_OSDAC_MASK                                                              0x00000100
+#define PHY_ANALOG_BB1_FORCE_OSDAC_GET(x)                                             (((x) & 0x00000100) >> 8)
+#define PHY_ANALOG_BB1_FORCE_OSDAC_SET(x)                                             (((x) << 8) & 0x00000100)
+#define PHY_ANALOG_BB1_ENABLE_V2I_MSB                                                                         9
+#define PHY_ANALOG_BB1_ENABLE_V2I_LSB                                                                         9
+#define PHY_ANALOG_BB1_ENABLE_V2I_MASK                                                               0x00000200
+#define PHY_ANALOG_BB1_ENABLE_V2I_GET(x)                                              (((x) & 0x00000200) >> 9)
+#define PHY_ANALOG_BB1_ENABLE_V2I_SET(x)                                              (((x) << 9) & 0x00000200)
+#define PHY_ANALOG_BB1_FORCE_V2I_MSB                                                                         10
+#define PHY_ANALOG_BB1_FORCE_V2I_LSB                                                                         10
+#define PHY_ANALOG_BB1_FORCE_V2I_MASK                                                                0x00000400
+#define PHY_ANALOG_BB1_FORCE_V2I_GET(x)                                              (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_BB1_FORCE_V2I_SET(x)                                              (((x) << 10) & 0x00000400)
+#define PHY_ANALOG_BB1_ENABLE_I2V_MSB                                                                        11
+#define PHY_ANALOG_BB1_ENABLE_I2V_LSB                                                                        11
+#define PHY_ANALOG_BB1_ENABLE_I2V_MASK                                                               0x00000800
+#define PHY_ANALOG_BB1_ENABLE_I2V_GET(x)                                             (((x) & 0x00000800) >> 11)
+#define PHY_ANALOG_BB1_ENABLE_I2V_SET(x)                                             (((x) << 11) & 0x00000800)
+#define PHY_ANALOG_BB1_FORCE_I2V_MSB                                                                         12
+#define PHY_ANALOG_BB1_FORCE_I2V_LSB                                                                         12
+#define PHY_ANALOG_BB1_FORCE_I2V_MASK                                                                0x00001000
+#define PHY_ANALOG_BB1_FORCE_I2V_GET(x)                                              (((x) & 0x00001000) >> 12)
+#define PHY_ANALOG_BB1_FORCE_I2V_SET(x)                                              (((x) << 12) & 0x00001000)
+#define PHY_ANALOG_BB1_CMSEL_MSB                                                                             15
+#define PHY_ANALOG_BB1_CMSEL_LSB                                                                             13
+#define PHY_ANALOG_BB1_CMSEL_MASK                                                                    0x0000e000
+#define PHY_ANALOG_BB1_CMSEL_GET(x)                                                  (((x) & 0x0000e000) >> 13)
+#define PHY_ANALOG_BB1_CMSEL_SET(x)                                                  (((x) << 13) & 0x0000e000)
+#define PHY_ANALOG_BB1_ATBSEL_MSB                                                                            17
+#define PHY_ANALOG_BB1_ATBSEL_LSB                                                                            16
+#define PHY_ANALOG_BB1_ATBSEL_MASK                                                                   0x00030000
+#define PHY_ANALOG_BB1_ATBSEL_GET(x)                                                 (((x) & 0x00030000) >> 16)
+#define PHY_ANALOG_BB1_ATBSEL_SET(x)                                                 (((x) << 16) & 0x00030000)
+#define PHY_ANALOG_BB1_PD_OSDAC_CALTX_CALPA_MSB                                                              18
+#define PHY_ANALOG_BB1_PD_OSDAC_CALTX_CALPA_LSB                                                              18
+#define PHY_ANALOG_BB1_PD_OSDAC_CALTX_CALPA_MASK                                                     0x00040000
+#define PHY_ANALOG_BB1_PD_OSDAC_CALTX_CALPA_GET(x)                                   (((x) & 0x00040000) >> 18)
+#define PHY_ANALOG_BB1_PD_OSDAC_CALTX_CALPA_SET(x)                                   (((x) << 18) & 0x00040000)
+#define PHY_ANALOG_BB1_OFSTCORRI2VQ_MSB                                                                      23
+#define PHY_ANALOG_BB1_OFSTCORRI2VQ_LSB                                                                      19
+#define PHY_ANALOG_BB1_OFSTCORRI2VQ_MASK                                                             0x00f80000
+#define PHY_ANALOG_BB1_OFSTCORRI2VQ_GET(x)                                           (((x) & 0x00f80000) >> 19)
+#define PHY_ANALOG_BB1_OFSTCORRI2VQ_SET(x)                                           (((x) << 19) & 0x00f80000)
+#define PHY_ANALOG_BB1_OFSTCORRI2VI_MSB                                                                      28
+#define PHY_ANALOG_BB1_OFSTCORRI2VI_LSB                                                                      24
+#define PHY_ANALOG_BB1_OFSTCORRI2VI_MASK                                                             0x1f000000
+#define PHY_ANALOG_BB1_OFSTCORRI2VI_GET(x)                                           (((x) & 0x1f000000) >> 24)
+#define PHY_ANALOG_BB1_OFSTCORRI2VI_SET(x)                                           (((x) << 24) & 0x1f000000)
+#define PHY_ANALOG_BB1_LOCALOFFSET_MSB                                                                       29
+#define PHY_ANALOG_BB1_LOCALOFFSET_LSB                                                                       29
+#define PHY_ANALOG_BB1_LOCALOFFSET_MASK                                                              0x20000000
+#define PHY_ANALOG_BB1_LOCALOFFSET_GET(x)                                            (((x) & 0x20000000) >> 29)
+#define PHY_ANALOG_BB1_LOCALOFFSET_SET(x)                                            (((x) << 29) & 0x20000000)
+#define PHY_ANALOG_BB1_RANGE_OSDAC_MSB                                                                       31
+#define PHY_ANALOG_BB1_RANGE_OSDAC_LSB                                                                       30
+#define PHY_ANALOG_BB1_RANGE_OSDAC_MASK                                                              0xc0000000
+#define PHY_ANALOG_BB1_RANGE_OSDAC_GET(x)                                            (((x) & 0xc0000000) >> 30)
+#define PHY_ANALOG_BB1_RANGE_OSDAC_SET(x)                                            (((x) << 30) & 0xc0000000)
+
+/* macros for BB2 */
+#define PHY_ANALOG_BB2_ADDRESS                                                                       0x00000144
+#define PHY_ANALOG_BB2_OFFSET                                                                        0x00000144
+#define PHY_ANALOG_BB2_SPARE_MSB                                                                              3
+#define PHY_ANALOG_BB2_SPARE_LSB                                                                              0
+#define PHY_ANALOG_BB2_SPARE_MASK                                                                    0x0000000f
+#define PHY_ANALOG_BB2_SPARE_GET(x)                                                   (((x) & 0x0000000f) >> 0)
+#define PHY_ANALOG_BB2_SPARE_SET(x)                                                   (((x) << 0) & 0x0000000f)
+#define PHY_ANALOG_BB2_MXR_HIGHGAINMASK_MSB                                                                   7
+#define PHY_ANALOG_BB2_MXR_HIGHGAINMASK_LSB                                                                   4
+#define PHY_ANALOG_BB2_MXR_HIGHGAINMASK_MASK                                                         0x000000f0
+#define PHY_ANALOG_BB2_MXR_HIGHGAINMASK_GET(x)                                        (((x) & 0x000000f0) >> 4)
+#define PHY_ANALOG_BB2_MXR_HIGHGAINMASK_SET(x)                                        (((x) << 4) & 0x000000f0)
+#define PHY_ANALOG_BB2_SEL_TEST_MSB                                                                           9
+#define PHY_ANALOG_BB2_SEL_TEST_LSB                                                                           8
+#define PHY_ANALOG_BB2_SEL_TEST_MASK                                                                 0x00000300
+#define PHY_ANALOG_BB2_SEL_TEST_GET(x)                                                (((x) & 0x00000300) >> 8)
+#define PHY_ANALOG_BB2_SEL_TEST_SET(x)                                                (((x) << 8) & 0x00000300)
+#define PHY_ANALOG_BB2_RCFILTER_CAP_MSB                                                                      14
+#define PHY_ANALOG_BB2_RCFILTER_CAP_LSB                                                                      10
+#define PHY_ANALOG_BB2_RCFILTER_CAP_MASK                                                             0x00007c00
+#define PHY_ANALOG_BB2_RCFILTER_CAP_GET(x)                                           (((x) & 0x00007c00) >> 10)
+#define PHY_ANALOG_BB2_RCFILTER_CAP_SET(x)                                           (((x) << 10) & 0x00007c00)
+#define PHY_ANALOG_BB2_OVERRIDE_RCFILTER_CAP_MSB                                                             15
+#define PHY_ANALOG_BB2_OVERRIDE_RCFILTER_CAP_LSB                                                             15
+#define PHY_ANALOG_BB2_OVERRIDE_RCFILTER_CAP_MASK                                                    0x00008000
+#define PHY_ANALOG_BB2_OVERRIDE_RCFILTER_CAP_GET(x)                                  (((x) & 0x00008000) >> 15)
+#define PHY_ANALOG_BB2_OVERRIDE_RCFILTER_CAP_SET(x)                                  (((x) << 15) & 0x00008000)
+#define PHY_ANALOG_BB2_FNOTCH_MSB                                                                            19
+#define PHY_ANALOG_BB2_FNOTCH_LSB                                                                            16
+#define PHY_ANALOG_BB2_FNOTCH_MASK                                                                   0x000f0000
+#define PHY_ANALOG_BB2_FNOTCH_GET(x)                                                 (((x) & 0x000f0000) >> 16)
+#define PHY_ANALOG_BB2_FNOTCH_SET(x)                                                 (((x) << 16) & 0x000f0000)
+#define PHY_ANALOG_BB2_OVERRIDE_FNOTCH_MSB                                                                   20
+#define PHY_ANALOG_BB2_OVERRIDE_FNOTCH_LSB                                                                   20
+#define PHY_ANALOG_BB2_OVERRIDE_FNOTCH_MASK                                                          0x00100000
+#define PHY_ANALOG_BB2_OVERRIDE_FNOTCH_GET(x)                                        (((x) & 0x00100000) >> 20)
+#define PHY_ANALOG_BB2_OVERRIDE_FNOTCH_SET(x)                                        (((x) << 20) & 0x00100000)
+#define PHY_ANALOG_BB2_FILTERFC_MSB                                                                          25
+#define PHY_ANALOG_BB2_FILTERFC_LSB                                                                          21
+#define PHY_ANALOG_BB2_FILTERFC_MASK                                                                 0x03e00000
+#define PHY_ANALOG_BB2_FILTERFC_GET(x)                                               (((x) & 0x03e00000) >> 21)
+#define PHY_ANALOG_BB2_FILTERFC_SET(x)                                               (((x) << 21) & 0x03e00000)
+#define PHY_ANALOG_BB2_OVERRIDE_FILTERFC_MSB                                                                 26
+#define PHY_ANALOG_BB2_OVERRIDE_FILTERFC_LSB                                                                 26
+#define PHY_ANALOG_BB2_OVERRIDE_FILTERFC_MASK                                                        0x04000000
+#define PHY_ANALOG_BB2_OVERRIDE_FILTERFC_GET(x)                                      (((x) & 0x04000000) >> 26)
+#define PHY_ANALOG_BB2_OVERRIDE_FILTERFC_SET(x)                                      (((x) << 26) & 0x04000000)
+#define PHY_ANALOG_BB2_I2V2RXOUT_EN_MSB                                                                      27
+#define PHY_ANALOG_BB2_I2V2RXOUT_EN_LSB                                                                      27
+#define PHY_ANALOG_BB2_I2V2RXOUT_EN_MASK                                                             0x08000000
+#define PHY_ANALOG_BB2_I2V2RXOUT_EN_GET(x)                                           (((x) & 0x08000000) >> 27)
+#define PHY_ANALOG_BB2_I2V2RXOUT_EN_SET(x)                                           (((x) << 27) & 0x08000000)
+#define PHY_ANALOG_BB2_BQ2RXOUT_EN_MSB                                                                       28
+#define PHY_ANALOG_BB2_BQ2RXOUT_EN_LSB                                                                       28
+#define PHY_ANALOG_BB2_BQ2RXOUT_EN_MASK                                                              0x10000000
+#define PHY_ANALOG_BB2_BQ2RXOUT_EN_GET(x)                                            (((x) & 0x10000000) >> 28)
+#define PHY_ANALOG_BB2_BQ2RXOUT_EN_SET(x)                                            (((x) << 28) & 0x10000000)
+#define PHY_ANALOG_BB2_RXIN2I2V_EN_MSB                                                                       29
+#define PHY_ANALOG_BB2_RXIN2I2V_EN_LSB                                                                       29
+#define PHY_ANALOG_BB2_RXIN2I2V_EN_MASK                                                              0x20000000
+#define PHY_ANALOG_BB2_RXIN2I2V_EN_GET(x)                                            (((x) & 0x20000000) >> 29)
+#define PHY_ANALOG_BB2_RXIN2I2V_EN_SET(x)                                            (((x) << 29) & 0x20000000)
+#define PHY_ANALOG_BB2_RXIN2BQ_EN_MSB                                                                        30
+#define PHY_ANALOG_BB2_RXIN2BQ_EN_LSB                                                                        30
+#define PHY_ANALOG_BB2_RXIN2BQ_EN_MASK                                                               0x40000000
+#define PHY_ANALOG_BB2_RXIN2BQ_EN_GET(x)                                             (((x) & 0x40000000) >> 30)
+#define PHY_ANALOG_BB2_RXIN2BQ_EN_SET(x)                                             (((x) << 30) & 0x40000000)
+#define PHY_ANALOG_BB2_SWITCH_OVERRIDE_MSB                                                                   31
+#define PHY_ANALOG_BB2_SWITCH_OVERRIDE_LSB                                                                   31
+#define PHY_ANALOG_BB2_SWITCH_OVERRIDE_MASK                                                          0x80000000
+#define PHY_ANALOG_BB2_SWITCH_OVERRIDE_GET(x)                                        (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_BB2_SWITCH_OVERRIDE_SET(x)                                        (((x) << 31) & 0x80000000)
+
+/* macros for BB3 */
+#define PHY_ANALOG_BB3_ADDRESS                                                                       0x00000148
+#define PHY_ANALOG_BB3_OFFSET                                                                        0x00000148
+#define PHY_ANALOG_BB3_SPARE_MSB                                                                             15
+#define PHY_ANALOG_BB3_SPARE_LSB                                                                              0
+#define PHY_ANALOG_BB3_SPARE_MASK                                                                    0x0000ffff
+#define PHY_ANALOG_BB3_SPARE_GET(x)                                                   (((x) & 0x0000ffff) >> 0)
+#define PHY_ANALOG_BB3_SPARE_SET(x)                                                   (((x) << 0) & 0x0000ffff)
+#define PHY_ANALOG_BB3_FILTERFC_MSB                                                                          20
+#define PHY_ANALOG_BB3_FILTERFC_LSB                                                                          16
+#define PHY_ANALOG_BB3_FILTERFC_MASK                                                                 0x001f0000
+#define PHY_ANALOG_BB3_FILTERFC_GET(x)                                               (((x) & 0x001f0000) >> 16)
+#define PHY_ANALOG_BB3_OFSTCORRI2VQ_MSB                                                                      25
+#define PHY_ANALOG_BB3_OFSTCORRI2VQ_LSB                                                                      21
+#define PHY_ANALOG_BB3_OFSTCORRI2VQ_MASK                                                             0x03e00000
+#define PHY_ANALOG_BB3_OFSTCORRI2VQ_GET(x)                                           (((x) & 0x03e00000) >> 21)
+#define PHY_ANALOG_BB3_OFSTCORRI2VI_MSB                                                                      30
+#define PHY_ANALOG_BB3_OFSTCORRI2VI_LSB                                                                      26
+#define PHY_ANALOG_BB3_OFSTCORRI2VI_MASK                                                             0x7c000000
+#define PHY_ANALOG_BB3_OFSTCORRI2VI_GET(x)                                           (((x) & 0x7c000000) >> 26)
+#define PHY_ANALOG_BB3_EN_TXBBCONSTCUR_MSB                                                                   31
+#define PHY_ANALOG_BB3_EN_TXBBCONSTCUR_LSB                                                                   31
+#define PHY_ANALOG_BB3_EN_TXBBCONSTCUR_MASK                                                          0x80000000
+#define PHY_ANALOG_BB3_EN_TXBBCONSTCUR_GET(x)                                        (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_BB3_EN_TXBBCONSTCUR_SET(x)                                        (((x) << 31) & 0x80000000)
+
+/* macros for PLLCLKMODA */
+#define PHY_ANALOG_PLLCLKMODA_ADDRESS                                                                0x00000280
+#define PHY_ANALOG_PLLCLKMODA_OFFSET                                                                 0x00000280
+#define PHY_ANALOG_PLLCLKMODA_PWD_PLLSDM_MSB                                                                  0
+#define PHY_ANALOG_PLLCLKMODA_PWD_PLLSDM_LSB                                                                  0
+#define PHY_ANALOG_PLLCLKMODA_PWD_PLLSDM_MASK                                                        0x00000001
+#define PHY_ANALOG_PLLCLKMODA_PWD_PLLSDM_GET(x)                                       (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_PLLCLKMODA_PWD_PLLSDM_SET(x)                                       (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_PLLCLKMODA_PWDPLL_MSB                                                                      1
+#define PHY_ANALOG_PLLCLKMODA_PWDPLL_LSB                                                                      1
+#define PHY_ANALOG_PLLCLKMODA_PWDPLL_MASK                                                            0x00000002
+#define PHY_ANALOG_PLLCLKMODA_PWDPLL_GET(x)                                           (((x) & 0x00000002) >> 1)
+#define PHY_ANALOG_PLLCLKMODA_PWDPLL_SET(x)                                           (((x) << 1) & 0x00000002)
+#define PHY_ANALOG_PLLCLKMODA_PLLFRAC_MSB                                                                    16
+#define PHY_ANALOG_PLLCLKMODA_PLLFRAC_LSB                                                                     2
+#define PHY_ANALOG_PLLCLKMODA_PLLFRAC_MASK                                                           0x0001fffc
+#define PHY_ANALOG_PLLCLKMODA_PLLFRAC_GET(x)                                          (((x) & 0x0001fffc) >> 2)
+#define PHY_ANALOG_PLLCLKMODA_PLLFRAC_SET(x)                                          (((x) << 2) & 0x0001fffc)
+#define PHY_ANALOG_PLLCLKMODA_REFDIV_MSB                                                                     20
+#define PHY_ANALOG_PLLCLKMODA_REFDIV_LSB                                                                     17
+#define PHY_ANALOG_PLLCLKMODA_REFDIV_MASK                                                            0x001e0000
+#define PHY_ANALOG_PLLCLKMODA_REFDIV_GET(x)                                          (((x) & 0x001e0000) >> 17)
+#define PHY_ANALOG_PLLCLKMODA_REFDIV_SET(x)                                          (((x) << 17) & 0x001e0000)
+#define PHY_ANALOG_PLLCLKMODA_DIV_MSB                                                                        30
+#define PHY_ANALOG_PLLCLKMODA_DIV_LSB                                                                        21
+#define PHY_ANALOG_PLLCLKMODA_DIV_MASK                                                               0x7fe00000
+#define PHY_ANALOG_PLLCLKMODA_DIV_GET(x)                                             (((x) & 0x7fe00000) >> 21)
+#define PHY_ANALOG_PLLCLKMODA_DIV_SET(x)                                             (((x) << 21) & 0x7fe00000)
+#define PHY_ANALOG_PLLCLKMODA_LOCAL_PLL_MSB                                                                  31
+#define PHY_ANALOG_PLLCLKMODA_LOCAL_PLL_LSB                                                                  31
+#define PHY_ANALOG_PLLCLKMODA_LOCAL_PLL_MASK                                                         0x80000000
+#define PHY_ANALOG_PLLCLKMODA_LOCAL_PLL_GET(x)                                       (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_PLLCLKMODA_LOCAL_PLL_SET(x)                                       (((x) << 31) & 0x80000000)
+
+/* macros for PLLCLKMODA2 */
+#define PHY_ANALOG_PLLCLKMODA2_ADDRESS                                                               0x00000284
+#define PHY_ANALOG_PLLCLKMODA2_OFFSET                                                                0x00000284
+#define PHY_ANALOG_PLLCLKMODA2_SPARE_MSB                                                                      3
+#define PHY_ANALOG_PLLCLKMODA2_SPARE_LSB                                                                      0
+#define PHY_ANALOG_PLLCLKMODA2_SPARE_MASK                                                            0x0000000f
+#define PHY_ANALOG_PLLCLKMODA2_SPARE_GET(x)                                           (((x) & 0x0000000f) >> 0)
+#define PHY_ANALOG_PLLCLKMODA2_SPARE_SET(x)                                           (((x) << 0) & 0x0000000f)
+#define PHY_ANALOG_PLLCLKMODA2_DACPWD_MSB                                                                     4
+#define PHY_ANALOG_PLLCLKMODA2_DACPWD_LSB                                                                     4
+#define PHY_ANALOG_PLLCLKMODA2_DACPWD_MASK                                                           0x00000010
+#define PHY_ANALOG_PLLCLKMODA2_DACPWD_GET(x)                                          (((x) & 0x00000010) >> 4)
+#define PHY_ANALOG_PLLCLKMODA2_DACPWD_SET(x)                                          (((x) << 4) & 0x00000010)
+#define PHY_ANALOG_PLLCLKMODA2_ADCPWD_MSB                                                                     5
+#define PHY_ANALOG_PLLCLKMODA2_ADCPWD_LSB                                                                     5
+#define PHY_ANALOG_PLLCLKMODA2_ADCPWD_MASK                                                           0x00000020
+#define PHY_ANALOG_PLLCLKMODA2_ADCPWD_GET(x)                                          (((x) & 0x00000020) >> 5)
+#define PHY_ANALOG_PLLCLKMODA2_ADCPWD_SET(x)                                          (((x) << 5) & 0x00000020)
+#define PHY_ANALOG_PLLCLKMODA2_LOCAL_ADDAC_MSB                                                                6
+#define PHY_ANALOG_PLLCLKMODA2_LOCAL_ADDAC_LSB                                                                6
+#define PHY_ANALOG_PLLCLKMODA2_LOCAL_ADDAC_MASK                                                      0x00000040
+#define PHY_ANALOG_PLLCLKMODA2_LOCAL_ADDAC_GET(x)                                     (((x) & 0x00000040) >> 6)
+#define PHY_ANALOG_PLLCLKMODA2_LOCAL_ADDAC_SET(x)                                     (((x) << 6) & 0x00000040)
+#define PHY_ANALOG_PLLCLKMODA2_DAC_CLK_SEL_MSB                                                                8
+#define PHY_ANALOG_PLLCLKMODA2_DAC_CLK_SEL_LSB                                                                7
+#define PHY_ANALOG_PLLCLKMODA2_DAC_CLK_SEL_MASK                                                      0x00000180
+#define PHY_ANALOG_PLLCLKMODA2_DAC_CLK_SEL_GET(x)                                     (((x) & 0x00000180) >> 7)
+#define PHY_ANALOG_PLLCLKMODA2_DAC_CLK_SEL_SET(x)                                     (((x) << 7) & 0x00000180)
+#define PHY_ANALOG_PLLCLKMODA2_ADC_CLK_SEL_MSB                                                               12
+#define PHY_ANALOG_PLLCLKMODA2_ADC_CLK_SEL_LSB                                                                9
+#define PHY_ANALOG_PLLCLKMODA2_ADC_CLK_SEL_MASK                                                      0x00001e00
+#define PHY_ANALOG_PLLCLKMODA2_ADC_CLK_SEL_GET(x)                                     (((x) & 0x00001e00) >> 9)
+#define PHY_ANALOG_PLLCLKMODA2_ADC_CLK_SEL_SET(x)                                     (((x) << 9) & 0x00001e00)
+#define PHY_ANALOG_PLLCLKMODA2_LOCAL_CLKMODA_MSB                                                             13
+#define PHY_ANALOG_PLLCLKMODA2_LOCAL_CLKMODA_LSB                                                             13
+#define PHY_ANALOG_PLLCLKMODA2_LOCAL_CLKMODA_MASK                                                    0x00002000
+#define PHY_ANALOG_PLLCLKMODA2_LOCAL_CLKMODA_GET(x)                                  (((x) & 0x00002000) >> 13)
+#define PHY_ANALOG_PLLCLKMODA2_LOCAL_CLKMODA_SET(x)                                  (((x) << 13) & 0x00002000)
+#define PHY_ANALOG_PLLCLKMODA2_PLLBYPASS_MSB                                                                 14
+#define PHY_ANALOG_PLLCLKMODA2_PLLBYPASS_LSB                                                                 14
+#define PHY_ANALOG_PLLCLKMODA2_PLLBYPASS_MASK                                                        0x00004000
+#define PHY_ANALOG_PLLCLKMODA2_PLLBYPASS_GET(x)                                      (((x) & 0x00004000) >> 14)
+#define PHY_ANALOG_PLLCLKMODA2_PLLBYPASS_SET(x)                                      (((x) << 14) & 0x00004000)
+#define PHY_ANALOG_PLLCLKMODA2_LOCAL_PLLBYPASS_MSB                                                           15
+#define PHY_ANALOG_PLLCLKMODA2_LOCAL_PLLBYPASS_LSB                                                           15
+#define PHY_ANALOG_PLLCLKMODA2_LOCAL_PLLBYPASS_MASK                                                  0x00008000
+#define PHY_ANALOG_PLLCLKMODA2_LOCAL_PLLBYPASS_GET(x)                                (((x) & 0x00008000) >> 15)
+#define PHY_ANALOG_PLLCLKMODA2_LOCAL_PLLBYPASS_SET(x)                                (((x) << 15) & 0x00008000)
+#define PHY_ANALOG_PLLCLKMODA2_PLLATB_MSB                                                                    17
+#define PHY_ANALOG_PLLCLKMODA2_PLLATB_LSB                                                                    16
+#define PHY_ANALOG_PLLCLKMODA2_PLLATB_MASK                                                           0x00030000
+#define PHY_ANALOG_PLLCLKMODA2_PLLATB_GET(x)                                         (((x) & 0x00030000) >> 16)
+#define PHY_ANALOG_PLLCLKMODA2_PLLATB_SET(x)                                         (((x) << 16) & 0x00030000)
+#define PHY_ANALOG_PLLCLKMODA2_PLL_SVREG_MSB                                                                 18
+#define PHY_ANALOG_PLLCLKMODA2_PLL_SVREG_LSB                                                                 18
+#define PHY_ANALOG_PLLCLKMODA2_PLL_SVREG_MASK                                                        0x00040000
+#define PHY_ANALOG_PLLCLKMODA2_PLL_SVREG_GET(x)                                      (((x) & 0x00040000) >> 18)
+#define PHY_ANALOG_PLLCLKMODA2_PLL_SVREG_SET(x)                                      (((x) << 18) & 0x00040000)
+#define PHY_ANALOG_PLLCLKMODA2_HI_FREQ_EN_MSB                                                                19
+#define PHY_ANALOG_PLLCLKMODA2_HI_FREQ_EN_LSB                                                                19
+#define PHY_ANALOG_PLLCLKMODA2_HI_FREQ_EN_MASK                                                       0x00080000
+#define PHY_ANALOG_PLLCLKMODA2_HI_FREQ_EN_GET(x)                                     (((x) & 0x00080000) >> 19)
+#define PHY_ANALOG_PLLCLKMODA2_HI_FREQ_EN_SET(x)                                     (((x) << 19) & 0x00080000)
+#define PHY_ANALOG_PLLCLKMODA2_RST_WARM_INT_L_MSB                                                            20
+#define PHY_ANALOG_PLLCLKMODA2_RST_WARM_INT_L_LSB                                                            20
+#define PHY_ANALOG_PLLCLKMODA2_RST_WARM_INT_L_MASK                                                   0x00100000
+#define PHY_ANALOG_PLLCLKMODA2_RST_WARM_INT_L_GET(x)                                 (((x) & 0x00100000) >> 20)
+#define PHY_ANALOG_PLLCLKMODA2_RST_WARM_INT_L_SET(x)                                 (((x) << 20) & 0x00100000)
+#define PHY_ANALOG_PLLCLKMODA2_RST_WARM_OVR_MSB                                                              21
+#define PHY_ANALOG_PLLCLKMODA2_RST_WARM_OVR_LSB                                                              21
+#define PHY_ANALOG_PLLCLKMODA2_RST_WARM_OVR_MASK                                                     0x00200000
+#define PHY_ANALOG_PLLCLKMODA2_RST_WARM_OVR_GET(x)                                   (((x) & 0x00200000) >> 21)
+#define PHY_ANALOG_PLLCLKMODA2_RST_WARM_OVR_SET(x)                                   (((x) << 21) & 0x00200000)
+#define PHY_ANALOG_PLLCLKMODA2_PLL_KVCO_MSB                                                                  23
+#define PHY_ANALOG_PLLCLKMODA2_PLL_KVCO_LSB                                                                  22
+#define PHY_ANALOG_PLLCLKMODA2_PLL_KVCO_MASK                                                         0x00c00000
+#define PHY_ANALOG_PLLCLKMODA2_PLL_KVCO_GET(x)                                       (((x) & 0x00c00000) >> 22)
+#define PHY_ANALOG_PLLCLKMODA2_PLL_KVCO_SET(x)                                       (((x) << 22) & 0x00c00000)
+#define PHY_ANALOG_PLLCLKMODA2_PLLICP_MSB                                                                    26
+#define PHY_ANALOG_PLLCLKMODA2_PLLICP_LSB                                                                    24
+#define PHY_ANALOG_PLLCLKMODA2_PLLICP_MASK                                                           0x07000000
+#define PHY_ANALOG_PLLCLKMODA2_PLLICP_GET(x)                                         (((x) & 0x07000000) >> 24)
+#define PHY_ANALOG_PLLCLKMODA2_PLLICP_SET(x)                                         (((x) << 24) & 0x07000000)
+#define PHY_ANALOG_PLLCLKMODA2_PLLFILTER_MSB                                                                 31
+#define PHY_ANALOG_PLLCLKMODA2_PLLFILTER_LSB                                                                 27
+#define PHY_ANALOG_PLLCLKMODA2_PLLFILTER_MASK                                                        0xf8000000
+#define PHY_ANALOG_PLLCLKMODA2_PLLFILTER_GET(x)                                      (((x) & 0xf8000000) >> 27)
+#define PHY_ANALOG_PLLCLKMODA2_PLLFILTER_SET(x)                                      (((x) << 27) & 0xf8000000)
+
+/* macros for TOP */
+#define PHY_ANALOG_TOP_ADDRESS                                                                       0x00000288
+#define PHY_ANALOG_TOP_OFFSET                                                                        0x00000288
+#define PHY_ANALOG_TOP_SPARE_MSB                                                                              2
+#define PHY_ANALOG_TOP_SPARE_LSB                                                                              0
+#define PHY_ANALOG_TOP_SPARE_MASK                                                                    0x00000007
+#define PHY_ANALOG_TOP_SPARE_GET(x)                                                   (((x) & 0x00000007) >> 0)
+#define PHY_ANALOG_TOP_SPARE_SET(x)                                                   (((x) << 0) & 0x00000007)
+#define PHY_ANALOG_TOP_PWDBIAS_MSB                                                                            3
+#define PHY_ANALOG_TOP_PWDBIAS_LSB                                                                            3
+#define PHY_ANALOG_TOP_PWDBIAS_MASK                                                                  0x00000008
+#define PHY_ANALOG_TOP_PWDBIAS_GET(x)                                                 (((x) & 0x00000008) >> 3)
+#define PHY_ANALOG_TOP_PWDBIAS_SET(x)                                                 (((x) << 3) & 0x00000008)
+#define PHY_ANALOG_TOP_FLIP_XPABIAS_MSB                                                                       4
+#define PHY_ANALOG_TOP_FLIP_XPABIAS_LSB                                                                       4
+#define PHY_ANALOG_TOP_FLIP_XPABIAS_MASK                                                             0x00000010
+#define PHY_ANALOG_TOP_FLIP_XPABIAS_GET(x)                                            (((x) & 0x00000010) >> 4)
+#define PHY_ANALOG_TOP_FLIP_XPABIAS_SET(x)                                            (((x) << 4) & 0x00000010)
+#define PHY_ANALOG_TOP_XPAON2_MSB                                                                             5
+#define PHY_ANALOG_TOP_XPAON2_LSB                                                                             5
+#define PHY_ANALOG_TOP_XPAON2_MASK                                                                   0x00000020
+#define PHY_ANALOG_TOP_XPAON2_GET(x)                                                  (((x) & 0x00000020) >> 5)
+#define PHY_ANALOG_TOP_XPAON2_SET(x)                                                  (((x) << 5) & 0x00000020)
+#define PHY_ANALOG_TOP_XPAON5_MSB                                                                             6
+#define PHY_ANALOG_TOP_XPAON5_LSB                                                                             6
+#define PHY_ANALOG_TOP_XPAON5_MASK                                                                   0x00000040
+#define PHY_ANALOG_TOP_XPAON5_GET(x)                                                  (((x) & 0x00000040) >> 6)
+#define PHY_ANALOG_TOP_XPAON5_SET(x)                                                  (((x) << 6) & 0x00000040)
+#define PHY_ANALOG_TOP_XPASHORT2GND_MSB                                                                       7
+#define PHY_ANALOG_TOP_XPASHORT2GND_LSB                                                                       7
+#define PHY_ANALOG_TOP_XPASHORT2GND_MASK                                                             0x00000080
+#define PHY_ANALOG_TOP_XPASHORT2GND_GET(x)                                            (((x) & 0x00000080) >> 7)
+#define PHY_ANALOG_TOP_XPASHORT2GND_SET(x)                                            (((x) << 7) & 0x00000080)
+#define PHY_ANALOG_TOP_XPABIASLVL_MSB                                                                        11
+#define PHY_ANALOG_TOP_XPABIASLVL_LSB                                                                         8
+#define PHY_ANALOG_TOP_XPABIASLVL_MASK                                                               0x00000f00
+#define PHY_ANALOG_TOP_XPABIASLVL_GET(x)                                              (((x) & 0x00000f00) >> 8)
+#define PHY_ANALOG_TOP_XPABIASLVL_SET(x)                                              (((x) << 8) & 0x00000f00)
+#define PHY_ANALOG_TOP_XPABIAS_EN_MSB                                                                        12
+#define PHY_ANALOG_TOP_XPABIAS_EN_LSB                                                                        12
+#define PHY_ANALOG_TOP_XPABIAS_EN_MASK                                                               0x00001000
+#define PHY_ANALOG_TOP_XPABIAS_EN_GET(x)                                             (((x) & 0x00001000) >> 12)
+#define PHY_ANALOG_TOP_XPABIAS_EN_SET(x)                                             (((x) << 12) & 0x00001000)
+#define PHY_ANALOG_TOP_ATBSELECT_MSB                                                                         13
+#define PHY_ANALOG_TOP_ATBSELECT_LSB                                                                         13
+#define PHY_ANALOG_TOP_ATBSELECT_MASK                                                                0x00002000
+#define PHY_ANALOG_TOP_ATBSELECT_GET(x)                                              (((x) & 0x00002000) >> 13)
+#define PHY_ANALOG_TOP_ATBSELECT_SET(x)                                              (((x) << 13) & 0x00002000)
+#define PHY_ANALOG_TOP_LOCAL_XPA_MSB                                                                         14
+#define PHY_ANALOG_TOP_LOCAL_XPA_LSB                                                                         14
+#define PHY_ANALOG_TOP_LOCAL_XPA_MASK                                                                0x00004000
+#define PHY_ANALOG_TOP_LOCAL_XPA_GET(x)                                              (((x) & 0x00004000) >> 14)
+#define PHY_ANALOG_TOP_LOCAL_XPA_SET(x)                                              (((x) << 14) & 0x00004000)
+#define PHY_ANALOG_TOP_XPABIAS_BYPASS_MSB                                                                    15
+#define PHY_ANALOG_TOP_XPABIAS_BYPASS_LSB                                                                    15
+#define PHY_ANALOG_TOP_XPABIAS_BYPASS_MASK                                                           0x00008000
+#define PHY_ANALOG_TOP_XPABIAS_BYPASS_GET(x)                                         (((x) & 0x00008000) >> 15)
+#define PHY_ANALOG_TOP_XPABIAS_BYPASS_SET(x)                                         (((x) << 15) & 0x00008000)
+#define PHY_ANALOG_TOP_TEST_PADQ_EN_MSB                                                                      16
+#define PHY_ANALOG_TOP_TEST_PADQ_EN_LSB                                                                      16
+#define PHY_ANALOG_TOP_TEST_PADQ_EN_MASK                                                             0x00010000
+#define PHY_ANALOG_TOP_TEST_PADQ_EN_GET(x)                                           (((x) & 0x00010000) >> 16)
+#define PHY_ANALOG_TOP_TEST_PADQ_EN_SET(x)                                           (((x) << 16) & 0x00010000)
+#define PHY_ANALOG_TOP_TEST_PADI_EN_MSB                                                                      17
+#define PHY_ANALOG_TOP_TEST_PADI_EN_LSB                                                                      17
+#define PHY_ANALOG_TOP_TEST_PADI_EN_MASK                                                             0x00020000
+#define PHY_ANALOG_TOP_TEST_PADI_EN_GET(x)                                           (((x) & 0x00020000) >> 17)
+#define PHY_ANALOG_TOP_TEST_PADI_EN_SET(x)                                           (((x) << 17) & 0x00020000)
+#define PHY_ANALOG_TOP_TESTIQ_RSEL_MSB                                                                       18
+#define PHY_ANALOG_TOP_TESTIQ_RSEL_LSB                                                                       18
+#define PHY_ANALOG_TOP_TESTIQ_RSEL_MASK                                                              0x00040000
+#define PHY_ANALOG_TOP_TESTIQ_RSEL_GET(x)                                            (((x) & 0x00040000) >> 18)
+#define PHY_ANALOG_TOP_TESTIQ_RSEL_SET(x)                                            (((x) << 18) & 0x00040000)
+#define PHY_ANALOG_TOP_TESTIQ_BUFEN_MSB                                                                      19
+#define PHY_ANALOG_TOP_TESTIQ_BUFEN_LSB                                                                      19
+#define PHY_ANALOG_TOP_TESTIQ_BUFEN_MASK                                                             0x00080000
+#define PHY_ANALOG_TOP_TESTIQ_BUFEN_GET(x)                                           (((x) & 0x00080000) >> 19)
+#define PHY_ANALOG_TOP_TESTIQ_BUFEN_SET(x)                                           (((x) << 19) & 0x00080000)
+#define PHY_ANALOG_TOP_PAD2GND_MSB                                                                           20
+#define PHY_ANALOG_TOP_PAD2GND_LSB                                                                           20
+#define PHY_ANALOG_TOP_PAD2GND_MASK                                                                  0x00100000
+#define PHY_ANALOG_TOP_PAD2GND_GET(x)                                                (((x) & 0x00100000) >> 20)
+#define PHY_ANALOG_TOP_PAD2GND_SET(x)                                                (((x) << 20) & 0x00100000)
+#define PHY_ANALOG_TOP_INTH2PAD_MSB                                                                          21
+#define PHY_ANALOG_TOP_INTH2PAD_LSB                                                                          21
+#define PHY_ANALOG_TOP_INTH2PAD_MASK                                                                 0x00200000
+#define PHY_ANALOG_TOP_INTH2PAD_GET(x)                                               (((x) & 0x00200000) >> 21)
+#define PHY_ANALOG_TOP_INTH2PAD_SET(x)                                               (((x) << 21) & 0x00200000)
+#define PHY_ANALOG_TOP_INTH2GND_MSB                                                                          22
+#define PHY_ANALOG_TOP_INTH2GND_LSB                                                                          22
+#define PHY_ANALOG_TOP_INTH2GND_MASK                                                                 0x00400000
+#define PHY_ANALOG_TOP_INTH2GND_GET(x)                                               (((x) & 0x00400000) >> 22)
+#define PHY_ANALOG_TOP_INTH2GND_SET(x)                                               (((x) << 22) & 0x00400000)
+#define PHY_ANALOG_TOP_INT2PAD_MSB                                                                           23
+#define PHY_ANALOG_TOP_INT2PAD_LSB                                                                           23
+#define PHY_ANALOG_TOP_INT2PAD_MASK                                                                  0x00800000
+#define PHY_ANALOG_TOP_INT2PAD_GET(x)                                                (((x) & 0x00800000) >> 23)
+#define PHY_ANALOG_TOP_INT2PAD_SET(x)                                                (((x) << 23) & 0x00800000)
+#define PHY_ANALOG_TOP_INT2GND_MSB                                                                           24
+#define PHY_ANALOG_TOP_INT2GND_LSB                                                                           24
+#define PHY_ANALOG_TOP_INT2GND_MASK                                                                  0x01000000
+#define PHY_ANALOG_TOP_INT2GND_GET(x)                                                (((x) & 0x01000000) >> 24)
+#define PHY_ANALOG_TOP_INT2GND_SET(x)                                                (((x) << 24) & 0x01000000)
+#define PHY_ANALOG_TOP_PWDPALCLK_MSB                                                                         25
+#define PHY_ANALOG_TOP_PWDPALCLK_LSB                                                                         25
+#define PHY_ANALOG_TOP_PWDPALCLK_MASK                                                                0x02000000
+#define PHY_ANALOG_TOP_PWDPALCLK_GET(x)                                              (((x) & 0x02000000) >> 25)
+#define PHY_ANALOG_TOP_PWDPALCLK_SET(x)                                              (((x) << 25) & 0x02000000)
+#define PHY_ANALOG_TOP_INV_CLK320_ADC_MSB                                                                    26
+#define PHY_ANALOG_TOP_INV_CLK320_ADC_LSB                                                                    26
+#define PHY_ANALOG_TOP_INV_CLK320_ADC_MASK                                                           0x04000000
+#define PHY_ANALOG_TOP_INV_CLK320_ADC_GET(x)                                         (((x) & 0x04000000) >> 26)
+#define PHY_ANALOG_TOP_INV_CLK320_ADC_SET(x)                                         (((x) << 26) & 0x04000000)
+#define PHY_ANALOG_TOP_FLIP_REFCLK40_MSB                                                                     27
+#define PHY_ANALOG_TOP_FLIP_REFCLK40_LSB                                                                     27
+#define PHY_ANALOG_TOP_FLIP_REFCLK40_MASK                                                            0x08000000
+#define PHY_ANALOG_TOP_FLIP_REFCLK40_GET(x)                                          (((x) & 0x08000000) >> 27)
+#define PHY_ANALOG_TOP_FLIP_REFCLK40_SET(x)                                          (((x) << 27) & 0x08000000)
+#define PHY_ANALOG_TOP_FLIP_PLLCLK320_MSB                                                                    28
+#define PHY_ANALOG_TOP_FLIP_PLLCLK320_LSB                                                                    28
+#define PHY_ANALOG_TOP_FLIP_PLLCLK320_MASK                                                           0x10000000
+#define PHY_ANALOG_TOP_FLIP_PLLCLK320_GET(x)                                         (((x) & 0x10000000) >> 28)
+#define PHY_ANALOG_TOP_FLIP_PLLCLK320_SET(x)                                         (((x) << 28) & 0x10000000)
+#define PHY_ANALOG_TOP_FLIP_PLLCLK160_MSB                                                                    29
+#define PHY_ANALOG_TOP_FLIP_PLLCLK160_LSB                                                                    29
+#define PHY_ANALOG_TOP_FLIP_PLLCLK160_MASK                                                           0x20000000
+#define PHY_ANALOG_TOP_FLIP_PLLCLK160_GET(x)                                         (((x) & 0x20000000) >> 29)
+#define PHY_ANALOG_TOP_FLIP_PLLCLK160_SET(x)                                         (((x) << 29) & 0x20000000)
+#define PHY_ANALOG_TOP_CLK_SEL_MSB                                                                           31
+#define PHY_ANALOG_TOP_CLK_SEL_LSB                                                                           30
+#define PHY_ANALOG_TOP_CLK_SEL_MASK                                                                  0xc0000000
+#define PHY_ANALOG_TOP_CLK_SEL_GET(x)                                                (((x) & 0xc0000000) >> 30)
+#define PHY_ANALOG_TOP_CLK_SEL_SET(x)                                                (((x) << 30) & 0xc0000000)
+
+/* macros for THERM */
+#define PHY_ANALOG_THERM_ADDRESS                                                                     0x0000028c
+#define PHY_ANALOG_THERM_OFFSET                                                                      0x0000028c
+#define PHY_ANALOG_THERM_LOREG_LVL_MSB                                                                        2
+#define PHY_ANALOG_THERM_LOREG_LVL_LSB                                                                        0
+#define PHY_ANALOG_THERM_LOREG_LVL_MASK                                                              0x00000007
+#define PHY_ANALOG_THERM_LOREG_LVL_GET(x)                                             (((x) & 0x00000007) >> 0)
+#define PHY_ANALOG_THERM_LOREG_LVL_SET(x)                                             (((x) << 0) & 0x00000007)
+#define PHY_ANALOG_THERM_RFREG_LVL_MSB                                                                        5
+#define PHY_ANALOG_THERM_RFREG_LVL_LSB                                                                        3
+#define PHY_ANALOG_THERM_RFREG_LVL_MASK                                                              0x00000038
+#define PHY_ANALOG_THERM_RFREG_LVL_GET(x)                                             (((x) & 0x00000038) >> 3)
+#define PHY_ANALOG_THERM_RFREG_LVL_SET(x)                                             (((x) << 3) & 0x00000038)
+#define PHY_ANALOG_THERM_SAR_ADC_DONE_MSB                                                                     6
+#define PHY_ANALOG_THERM_SAR_ADC_DONE_LSB                                                                     6
+#define PHY_ANALOG_THERM_SAR_ADC_DONE_MASK                                                           0x00000040
+#define PHY_ANALOG_THERM_SAR_ADC_DONE_GET(x)                                          (((x) & 0x00000040) >> 6)
+#define PHY_ANALOG_THERM_SAR_ADC_OUT_MSB                                                                     14
+#define PHY_ANALOG_THERM_SAR_ADC_OUT_LSB                                                                      7
+#define PHY_ANALOG_THERM_SAR_ADC_OUT_MASK                                                            0x00007f80
+#define PHY_ANALOG_THERM_SAR_ADC_OUT_GET(x)                                           (((x) & 0x00007f80) >> 7)
+#define PHY_ANALOG_THERM_SAR_DACTEST_CODE_MSB                                                                22
+#define PHY_ANALOG_THERM_SAR_DACTEST_CODE_LSB                                                                15
+#define PHY_ANALOG_THERM_SAR_DACTEST_CODE_MASK                                                       0x007f8000
+#define PHY_ANALOG_THERM_SAR_DACTEST_CODE_GET(x)                                     (((x) & 0x007f8000) >> 15)
+#define PHY_ANALOG_THERM_SAR_DACTEST_CODE_SET(x)                                     (((x) << 15) & 0x007f8000)
+#define PHY_ANALOG_THERM_SAR_DACTEST_EN_MSB                                                                  23
+#define PHY_ANALOG_THERM_SAR_DACTEST_EN_LSB                                                                  23
+#define PHY_ANALOG_THERM_SAR_DACTEST_EN_MASK                                                         0x00800000
+#define PHY_ANALOG_THERM_SAR_DACTEST_EN_GET(x)                                       (((x) & 0x00800000) >> 23)
+#define PHY_ANALOG_THERM_SAR_DACTEST_EN_SET(x)                                       (((x) << 23) & 0x00800000)
+#define PHY_ANALOG_THERM_SAR_ADCCAL_EN_MSB                                                                   24
+#define PHY_ANALOG_THERM_SAR_ADCCAL_EN_LSB                                                                   24
+#define PHY_ANALOG_THERM_SAR_ADCCAL_EN_MASK                                                          0x01000000
+#define PHY_ANALOG_THERM_SAR_ADCCAL_EN_GET(x)                                        (((x) & 0x01000000) >> 24)
+#define PHY_ANALOG_THERM_SAR_ADCCAL_EN_SET(x)                                        (((x) << 24) & 0x01000000)
+#define PHY_ANALOG_THERM_THERMSEL_MSB                                                                        26
+#define PHY_ANALOG_THERM_THERMSEL_LSB                                                                        25
+#define PHY_ANALOG_THERM_THERMSEL_MASK                                                               0x06000000
+#define PHY_ANALOG_THERM_THERMSEL_GET(x)                                             (((x) & 0x06000000) >> 25)
+#define PHY_ANALOG_THERM_THERMSEL_SET(x)                                             (((x) << 25) & 0x06000000)
+#define PHY_ANALOG_THERM_SAR_SLOW_EN_MSB                                                                     27
+#define PHY_ANALOG_THERM_SAR_SLOW_EN_LSB                                                                     27
+#define PHY_ANALOG_THERM_SAR_SLOW_EN_MASK                                                            0x08000000
+#define PHY_ANALOG_THERM_SAR_SLOW_EN_GET(x)                                          (((x) & 0x08000000) >> 27)
+#define PHY_ANALOG_THERM_SAR_SLOW_EN_SET(x)                                          (((x) << 27) & 0x08000000)
+#define PHY_ANALOG_THERM_THERMSTART_MSB                                                                      28
+#define PHY_ANALOG_THERM_THERMSTART_LSB                                                                      28
+#define PHY_ANALOG_THERM_THERMSTART_MASK                                                             0x10000000
+#define PHY_ANALOG_THERM_THERMSTART_GET(x)                                           (((x) & 0x10000000) >> 28)
+#define PHY_ANALOG_THERM_THERMSTART_SET(x)                                           (((x) << 28) & 0x10000000)
+#define PHY_ANALOG_THERM_SAR_AUTOPWD_EN_MSB                                                                  29
+#define PHY_ANALOG_THERM_SAR_AUTOPWD_EN_LSB                                                                  29
+#define PHY_ANALOG_THERM_SAR_AUTOPWD_EN_MASK                                                         0x20000000
+#define PHY_ANALOG_THERM_SAR_AUTOPWD_EN_GET(x)                                       (((x) & 0x20000000) >> 29)
+#define PHY_ANALOG_THERM_SAR_AUTOPWD_EN_SET(x)                                       (((x) << 29) & 0x20000000)
+#define PHY_ANALOG_THERM_THERMON_MSB                                                                         30
+#define PHY_ANALOG_THERM_THERMON_LSB                                                                         30
+#define PHY_ANALOG_THERM_THERMON_MASK                                                                0x40000000
+#define PHY_ANALOG_THERM_THERMON_GET(x)                                              (((x) & 0x40000000) >> 30)
+#define PHY_ANALOG_THERM_THERMON_SET(x)                                              (((x) << 30) & 0x40000000)
+#define PHY_ANALOG_THERM_LOCAL_THERM_MSB                                                                     31
+#define PHY_ANALOG_THERM_LOCAL_THERM_LSB                                                                     31
+#define PHY_ANALOG_THERM_LOCAL_THERM_MASK                                                            0x80000000
+#define PHY_ANALOG_THERM_LOCAL_THERM_GET(x)                                          (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_THERM_LOCAL_THERM_SET(x)                                          (((x) << 31) & 0x80000000)
+
+/* macros for XTAL */
+#define PHY_ANALOG_XTAL_ADDRESS                                                                      0x00000290
+#define PHY_ANALOG_XTAL_OFFSET                                                                       0x00000290
+#define PHY_ANALOG_XTAL_SPARE_MSB                                                                             5
+#define PHY_ANALOG_XTAL_SPARE_LSB                                                                             0
+#define PHY_ANALOG_XTAL_SPARE_MASK                                                                   0x0000003f
+#define PHY_ANALOG_XTAL_SPARE_GET(x)                                                  (((x) & 0x0000003f) >> 0)
+#define PHY_ANALOG_XTAL_SPARE_SET(x)                                                  (((x) << 0) & 0x0000003f)
+#define PHY_ANALOG_XTAL_XTAL_NOTCXODET_MSB                                                                    6
+#define PHY_ANALOG_XTAL_XTAL_NOTCXODET_LSB                                                                    6
+#define PHY_ANALOG_XTAL_XTAL_NOTCXODET_MASK                                                          0x00000040
+#define PHY_ANALOG_XTAL_XTAL_NOTCXODET_GET(x)                                         (((x) & 0x00000040) >> 6)
+#define PHY_ANALOG_XTAL_XTAL_NOTCXODET_SET(x)                                         (((x) << 6) & 0x00000040)
+#define PHY_ANALOG_XTAL_LOCALBIAS2X_MSB                                                                       7
+#define PHY_ANALOG_XTAL_LOCALBIAS2X_LSB                                                                       7
+#define PHY_ANALOG_XTAL_LOCALBIAS2X_MASK                                                             0x00000080
+#define PHY_ANALOG_XTAL_LOCALBIAS2X_GET(x)                                            (((x) & 0x00000080) >> 7)
+#define PHY_ANALOG_XTAL_LOCALBIAS2X_SET(x)                                            (((x) << 7) & 0x00000080)
+#define PHY_ANALOG_XTAL_LOCAL_XTAL_MSB                                                                        8
+#define PHY_ANALOG_XTAL_LOCAL_XTAL_LSB                                                                        8
+#define PHY_ANALOG_XTAL_LOCAL_XTAL_MASK                                                              0x00000100
+#define PHY_ANALOG_XTAL_LOCAL_XTAL_GET(x)                                             (((x) & 0x00000100) >> 8)
+#define PHY_ANALOG_XTAL_LOCAL_XTAL_SET(x)                                             (((x) << 8) & 0x00000100)
+#define PHY_ANALOG_XTAL_XTAL_PWDCLKIN_MSB                                                                     9
+#define PHY_ANALOG_XTAL_XTAL_PWDCLKIN_LSB                                                                     9
+#define PHY_ANALOG_XTAL_XTAL_PWDCLKIN_MASK                                                           0x00000200
+#define PHY_ANALOG_XTAL_XTAL_PWDCLKIN_GET(x)                                          (((x) & 0x00000200) >> 9)
+#define PHY_ANALOG_XTAL_XTAL_PWDCLKIN_SET(x)                                          (((x) << 9) & 0x00000200)
+#define PHY_ANALOG_XTAL_XTAL_OSCON_MSB                                                                       10
+#define PHY_ANALOG_XTAL_XTAL_OSCON_LSB                                                                       10
+#define PHY_ANALOG_XTAL_XTAL_OSCON_MASK                                                              0x00000400
+#define PHY_ANALOG_XTAL_XTAL_OSCON_GET(x)                                            (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_XTAL_XTAL_OSCON_SET(x)                                            (((x) << 10) & 0x00000400)
+#define PHY_ANALOG_XTAL_XTAL_PWDCLKD_MSB                                                                     11
+#define PHY_ANALOG_XTAL_XTAL_PWDCLKD_LSB                                                                     11
+#define PHY_ANALOG_XTAL_XTAL_PWDCLKD_MASK                                                            0x00000800
+#define PHY_ANALOG_XTAL_XTAL_PWDCLKD_GET(x)                                          (((x) & 0x00000800) >> 11)
+#define PHY_ANALOG_XTAL_XTAL_PWDCLKD_SET(x)                                          (((x) << 11) & 0x00000800)
+#define PHY_ANALOG_XTAL_XTAL_LOCALBIAS_MSB                                                                   12
+#define PHY_ANALOG_XTAL_XTAL_LOCALBIAS_LSB                                                                   12
+#define PHY_ANALOG_XTAL_XTAL_LOCALBIAS_MASK                                                          0x00001000
+#define PHY_ANALOG_XTAL_XTAL_LOCALBIAS_GET(x)                                        (((x) & 0x00001000) >> 12)
+#define PHY_ANALOG_XTAL_XTAL_LOCALBIAS_SET(x)                                        (((x) << 12) & 0x00001000)
+#define PHY_ANALOG_XTAL_XTAL_SHRTXIN_MSB                                                                     13
+#define PHY_ANALOG_XTAL_XTAL_SHRTXIN_LSB                                                                     13
+#define PHY_ANALOG_XTAL_XTAL_SHRTXIN_MASK                                                            0x00002000
+#define PHY_ANALOG_XTAL_XTAL_SHRTXIN_GET(x)                                          (((x) & 0x00002000) >> 13)
+#define PHY_ANALOG_XTAL_XTAL_SHRTXIN_SET(x)                                          (((x) << 13) & 0x00002000)
+#define PHY_ANALOG_XTAL_XTAL_DRVSTR_MSB                                                                      15
+#define PHY_ANALOG_XTAL_XTAL_DRVSTR_LSB                                                                      14
+#define PHY_ANALOG_XTAL_XTAL_DRVSTR_MASK                                                             0x0000c000
+#define PHY_ANALOG_XTAL_XTAL_DRVSTR_GET(x)                                           (((x) & 0x0000c000) >> 14)
+#define PHY_ANALOG_XTAL_XTAL_DRVSTR_SET(x)                                           (((x) << 14) & 0x0000c000)
+#define PHY_ANALOG_XTAL_XTAL_CAPOUTDAC_MSB                                                                   22
+#define PHY_ANALOG_XTAL_XTAL_CAPOUTDAC_LSB                                                                   16
+#define PHY_ANALOG_XTAL_XTAL_CAPOUTDAC_MASK                                                          0x007f0000
+#define PHY_ANALOG_XTAL_XTAL_CAPOUTDAC_GET(x)                                        (((x) & 0x007f0000) >> 16)
+#define PHY_ANALOG_XTAL_XTAL_CAPOUTDAC_SET(x)                                        (((x) << 16) & 0x007f0000)
+#define PHY_ANALOG_XTAL_XTAL_CAPINDAC_MSB                                                                    29
+#define PHY_ANALOG_XTAL_XTAL_CAPINDAC_LSB                                                                    23
+#define PHY_ANALOG_XTAL_XTAL_CAPINDAC_MASK                                                           0x3f800000
+#define PHY_ANALOG_XTAL_XTAL_CAPINDAC_GET(x)                                         (((x) & 0x3f800000) >> 23)
+#define PHY_ANALOG_XTAL_XTAL_CAPINDAC_SET(x)                                         (((x) << 23) & 0x3f800000)
+#define PHY_ANALOG_XTAL_XTAL_BIAS2X_MSB                                                                      30
+#define PHY_ANALOG_XTAL_XTAL_BIAS2X_LSB                                                                      30
+#define PHY_ANALOG_XTAL_XTAL_BIAS2X_MASK                                                             0x40000000
+#define PHY_ANALOG_XTAL_XTAL_BIAS2X_GET(x)                                           (((x) & 0x40000000) >> 30)
+#define PHY_ANALOG_XTAL_XTAL_BIAS2X_SET(x)                                           (((x) << 30) & 0x40000000)
+#define PHY_ANALOG_XTAL_TCXODET_MSB                                                                          31
+#define PHY_ANALOG_XTAL_TCXODET_LSB                                                                          31
+#define PHY_ANALOG_XTAL_TCXODET_MASK                                                                 0x80000000
+#define PHY_ANALOG_XTAL_TCXODET_GET(x)                                               (((x) & 0x80000000) >> 31)
+
+/* macros for rbist_cntrl */
+#define PHY_ANALOG_RBIST_CNTRL_ADDRESS                                                               0x00000380
+#define PHY_ANALOG_RBIST_CNTRL_OFFSET                                                                0x00000380
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_MSB                                                      0
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_LSB                                                      0
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_MASK                                            0x00000001
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_GET(x)                           (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_SET(x)                           (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_MSB                                                   1
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_LSB                                                   1
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_MASK                                         0x00000002
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_GET(x)                        (((x) & 0x00000002) >> 1)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_SET(x)                        (((x) << 1) & 0x00000002)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_MSB                                                   2
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_LSB                                                   2
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_MASK                                         0x00000004
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_GET(x)                        (((x) & 0x00000004) >> 2)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_SET(x)                        (((x) << 2) & 0x00000004)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_MSB                                                 3
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_LSB                                                 3
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_MASK                                       0x00000008
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_GET(x)                      (((x) & 0x00000008) >> 3)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_SET(x)                      (((x) << 3) & 0x00000008)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_MSB                                               4
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_LSB                                               4
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_MASK                                     0x00000010
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_GET(x)                    (((x) & 0x00000010) >> 4)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_SET(x)                    (((x) << 4) & 0x00000010)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_MSB                                               5
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_LSB                                               5
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_MASK                                     0x00000020
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_GET(x)                    (((x) & 0x00000020) >> 5)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_SET(x)                    (((x) << 5) & 0x00000020)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_MSB                                                  6
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_LSB                                                  6
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_MASK                                        0x00000040
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_GET(x)                       (((x) & 0x00000040) >> 6)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_SET(x)                       (((x) << 6) & 0x00000040)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_MSB                                                  7
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_LSB                                                  7
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_MASK                                        0x00000080
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_GET(x)                       (((x) & 0x00000080) >> 7)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_SET(x)                       (((x) << 7) & 0x00000080)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_MSB                                                8
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_LSB                                                8
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_MASK                                      0x00000100
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_GET(x)                     (((x) & 0x00000100) >> 8)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_SET(x)                     (((x) << 8) & 0x00000100)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_MSB                                                         9
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_LSB                                                         9
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_MASK                                               0x00000200
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_GET(x)                              (((x) & 0x00000200) >> 9)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_SET(x)                              (((x) << 9) & 0x00000200)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_MSB                                                      10
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_LSB                                                      10
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_MASK                                             0x00000400
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_GET(x)                           (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_SET(x)                           (((x) << 10) & 0x00000400)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_MSB                                                     11
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_LSB                                                     11
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_MASK                                            0x00000800
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_GET(x)                          (((x) & 0x00000800) >> 11)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_SET(x)                          (((x) << 11) & 0x00000800)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_MSB                                                        12
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_LSB                                                        12
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_MASK                                               0x00001000
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_GET(x)                             (((x) & 0x00001000) >> 12)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_SET(x)                             (((x) << 12) & 0x00001000)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_MSB                                                      13
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_LSB                                                      13
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_MASK                                             0x00002000
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_GET(x)                           (((x) & 0x00002000) >> 13)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_SET(x)                           (((x) << 13) & 0x00002000)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_MSB                                                 14
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_LSB                                                 14
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_MASK                                        0x00004000
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_GET(x)                      (((x) & 0x00004000) >> 14)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_SET(x)                      (((x) << 14) & 0x00004000)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_MSB                                                       15
+#define PHY_ANALOG_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_LSB                                                       15
+#define PHY_ANALOG_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_MASK                                              0x00008000
+#define PHY_ANALOG_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_GET(x)                            (((x) & 0x00008000) >> 15)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_SET(x)                            (((x) << 15) & 0x00008000)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_RBIST_ENABLE_MSB                                                          16
+#define PHY_ANALOG_RBIST_CNTRL_ATE_RBIST_ENABLE_LSB                                                          16
+#define PHY_ANALOG_RBIST_CNTRL_ATE_RBIST_ENABLE_MASK                                                 0x00010000
+#define PHY_ANALOG_RBIST_CNTRL_ATE_RBIST_ENABLE_GET(x)                               (((x) & 0x00010000) >> 16)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_RBIST_ENABLE_SET(x)                               (((x) << 16) & 0x00010000)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_ADC_CLK_INVERT_MSB                                                        17
+#define PHY_ANALOG_RBIST_CNTRL_ATE_ADC_CLK_INVERT_LSB                                                        17
+#define PHY_ANALOG_RBIST_CNTRL_ATE_ADC_CLK_INVERT_MASK                                               0x00020000
+#define PHY_ANALOG_RBIST_CNTRL_ATE_ADC_CLK_INVERT_GET(x)                             (((x) & 0x00020000) >> 17)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_ADC_CLK_INVERT_SET(x)                             (((x) << 17) & 0x00020000)
+
+/* macros for tx_dc_offset */
+#define PHY_ANALOG_TX_DC_OFFSET_ADDRESS                                                              0x00000384
+#define PHY_ANALOG_TX_DC_OFFSET_OFFSET                                                               0x00000384
+#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_I_MSB                                                         10
+#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_I_LSB                                                          0
+#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_I_MASK                                                0x000007ff
+#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_I_GET(x)                               (((x) & 0x000007ff) >> 0)
+#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_I_SET(x)                               (((x) << 0) & 0x000007ff)
+#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_MSB                                                         26
+#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_LSB                                                         16
+#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_MASK                                                0x07ff0000
+#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_GET(x)                              (((x) & 0x07ff0000) >> 16)
+#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_SET(x)                              (((x) << 16) & 0x07ff0000)
+
+/* macros for tx_tonegen0 */
+#define PHY_ANALOG_TX_TONEGEN0_ADDRESS                                                               0x00000388
+#define PHY_ANALOG_TX_TONEGEN0_OFFSET                                                                0x00000388
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_MSB                                                      6
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_LSB                                                      0
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_MASK                                            0x0000007f
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_GET(x)                           (((x) & 0x0000007f) >> 0)
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_SET(x)                           (((x) << 0) & 0x0000007f)
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_EXP_MSB                                                    11
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_EXP_LSB                                                     8
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_EXP_MASK                                           0x00000f00
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_EXP_GET(x)                          (((x) & 0x00000f00) >> 8)
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_EXP_SET(x)                          (((x) << 8) & 0x00000f00)
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_MAN_MSB                                                    23
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_MAN_LSB                                                    16
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_MAN_MASK                                           0x00ff0000
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_MAN_GET(x)                         (((x) & 0x00ff0000) >> 16)
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_MAN_SET(x)                         (((x) << 16) & 0x00ff0000)
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_MSB                                                    30
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_LSB                                                    24
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_MASK                                           0x7f000000
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_GET(x)                         (((x) & 0x7f000000) >> 24)
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_SET(x)                         (((x) << 24) & 0x7f000000)
+
+/* macros for tx_tonegen1 */
+#define PHY_ANALOG_TX_TONEGEN1_ADDRESS                                                               0x0000038c
+#define PHY_ANALOG_TX_TONEGEN1_OFFSET                                                                0x0000038c
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_MSB                                                      6
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_LSB                                                      0
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_MASK                                            0x0000007f
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_GET(x)                           (((x) & 0x0000007f) >> 0)
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_SET(x)                           (((x) << 0) & 0x0000007f)
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_EXP_MSB                                                    11
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_EXP_LSB                                                     8
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_EXP_MASK                                           0x00000f00
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_EXP_GET(x)                          (((x) & 0x00000f00) >> 8)
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_EXP_SET(x)                          (((x) << 8) & 0x00000f00)
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_MAN_MSB                                                    23
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_MAN_LSB                                                    16
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_MAN_MASK                                           0x00ff0000
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_MAN_GET(x)                         (((x) & 0x00ff0000) >> 16)
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_MAN_SET(x)                         (((x) << 16) & 0x00ff0000)
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_MSB                                                    30
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_LSB                                                    24
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_MASK                                           0x7f000000
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_GET(x)                         (((x) & 0x7f000000) >> 24)
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_SET(x)                         (((x) << 24) & 0x7f000000)
+
+/* macros for tx_lftonegen0 */
+#define PHY_ANALOG_TX_LFTONEGEN0_ADDRESS                                                             0x00000390
+#define PHY_ANALOG_TX_LFTONEGEN0_OFFSET                                                              0x00000390
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_MSB                                                    6
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_LSB                                                    0
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_MASK                                          0x0000007f
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_GET(x)                         (((x) & 0x0000007f) >> 0)
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_SET(x)                         (((x) << 0) & 0x0000007f)
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_EXP_MSB                                                  11
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_EXP_LSB                                                   8
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_EXP_MASK                                         0x00000f00
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_EXP_GET(x)                        (((x) & 0x00000f00) >> 8)
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_EXP_SET(x)                        (((x) << 8) & 0x00000f00)
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_MAN_MSB                                                  23
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_MAN_LSB                                                  16
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_MAN_MASK                                         0x00ff0000
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_MAN_GET(x)                       (((x) & 0x00ff0000) >> 16)
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_MAN_SET(x)                       (((x) << 16) & 0x00ff0000)
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_MSB                                                  30
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_LSB                                                  24
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_MASK                                         0x7f000000
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_GET(x)                       (((x) & 0x7f000000) >> 24)
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_SET(x)                       (((x) << 24) & 0x7f000000)
+
+/* macros for tx_linear_ramp_i */
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ADDRESS                                                          0x00000394
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_OFFSET                                                           0x00000394
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_MSB                                             10
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_LSB                                              0
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_MASK                                    0x000007ff
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_GET(x)                   (((x) & 0x000007ff) >> 0)
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_SET(x)                   (((x) << 0) & 0x000007ff)
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_MSB                                            21
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_LSB                                            12
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_MASK                                   0x003ff000
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_GET(x)                 (((x) & 0x003ff000) >> 12)
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_SET(x)                 (((x) << 12) & 0x003ff000)
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_MSB                                             29
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_LSB                                             24
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_MASK                                    0x3f000000
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_GET(x)                  (((x) & 0x3f000000) >> 24)
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_SET(x)                  (((x) << 24) & 0x3f000000)
+
+/* macros for tx_linear_ramp_q */
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ADDRESS                                                          0x00000398
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_OFFSET                                                           0x00000398
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_MSB                                             10
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_LSB                                              0
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_MASK                                    0x000007ff
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_GET(x)                   (((x) & 0x000007ff) >> 0)
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_SET(x)                   (((x) << 0) & 0x000007ff)
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_MSB                                            21
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_LSB                                            12
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_MASK                                   0x003ff000
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_GET(x)                 (((x) & 0x003ff000) >> 12)
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_SET(x)                 (((x) << 12) & 0x003ff000)
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_MSB                                             29
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_LSB                                             24
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_MASK                                    0x3f000000
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_GET(x)                  (((x) & 0x3f000000) >> 24)
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_SET(x)                  (((x) << 24) & 0x3f000000)
+
+/* macros for tx_prbs_mag */
+#define PHY_ANALOG_TX_PRBS_MAG_ADDRESS                                                               0x0000039c
+#define PHY_ANALOG_TX_PRBS_MAG_OFFSET                                                                0x0000039c
+#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_MSB                                               9
+#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_LSB                                               0
+#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_MASK                                     0x000003ff
+#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_GET(x)                    (((x) & 0x000003ff) >> 0)
+#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_SET(x)                    (((x) << 0) & 0x000003ff)
+#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_MSB                                              25
+#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_LSB                                              16
+#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_MASK                                     0x03ff0000
+#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_GET(x)                   (((x) & 0x03ff0000) >> 16)
+#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_SET(x)                   (((x) << 16) & 0x03ff0000)
+
+/* macros for tx_prbs_seed_i */
+#define PHY_ANALOG_TX_PRBS_SEED_I_ADDRESS                                                            0x000003a0
+#define PHY_ANALOG_TX_PRBS_SEED_I_OFFSET                                                             0x000003a0
+#define PHY_ANALOG_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_MSB                                                  30
+#define PHY_ANALOG_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_LSB                                                   0
+#define PHY_ANALOG_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_MASK                                         0x7fffffff
+#define PHY_ANALOG_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_GET(x)                        (((x) & 0x7fffffff) >> 0)
+#define PHY_ANALOG_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_SET(x)                        (((x) << 0) & 0x7fffffff)
+
+/* macros for tx_prbs_seed_q */
+#define PHY_ANALOG_TX_PRBS_SEED_Q_ADDRESS                                                            0x000003a4
+#define PHY_ANALOG_TX_PRBS_SEED_Q_OFFSET                                                             0x000003a4
+#define PHY_ANALOG_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_MSB                                                  30
+#define PHY_ANALOG_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_LSB                                                   0
+#define PHY_ANALOG_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_MASK                                         0x7fffffff
+#define PHY_ANALOG_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_GET(x)                        (((x) & 0x7fffffff) >> 0)
+#define PHY_ANALOG_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_SET(x)                        (((x) << 0) & 0x7fffffff)
+
+/* macros for cmac_dc_cancel */
+#define PHY_ANALOG_CMAC_DC_CANCEL_ADDRESS                                                            0x000003a8
+#define PHY_ANALOG_CMAC_DC_CANCEL_OFFSET                                                             0x000003a8
+#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_MSB                                                    9
+#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_LSB                                                    0
+#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_MASK                                          0x000003ff
+#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_GET(x)                         (((x) & 0x000003ff) >> 0)
+#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_SET(x)                         (((x) << 0) & 0x000003ff)
+#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_MSB                                                   25
+#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_LSB                                                   16
+#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_MASK                                          0x03ff0000
+#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_GET(x)                        (((x) & 0x03ff0000) >> 16)
+#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_SET(x)                        (((x) << 16) & 0x03ff0000)
+
+/* macros for cmac_dc_offset */
+#define PHY_ANALOG_CMAC_DC_OFFSET_ADDRESS                                                            0x000003ac
+#define PHY_ANALOG_CMAC_DC_OFFSET_OFFSET                                                             0x000003ac
+#define PHY_ANALOG_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_MSB                                                      3
+#define PHY_ANALOG_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_LSB                                                      0
+#define PHY_ANALOG_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_MASK                                            0x0000000f
+#define PHY_ANALOG_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_GET(x)                           (((x) & 0x0000000f) >> 0)
+#define PHY_ANALOG_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_SET(x)                           (((x) << 0) & 0x0000000f)
+
+/* macros for cmac_corr */
+#define PHY_ANALOG_CMAC_CORR_ADDRESS                                                                 0x000003b0
+#define PHY_ANALOG_CMAC_CORR_OFFSET                                                                  0x000003b0
+#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_CYCLES_MSB                                                         4
+#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_CYCLES_LSB                                                         0
+#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_CYCLES_MASK                                               0x0000001f
+#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_CYCLES_GET(x)                              (((x) & 0x0000001f) >> 0)
+#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_CYCLES_SET(x)                              (((x) << 0) & 0x0000001f)
+#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_FREQ_MSB                                                          13
+#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_FREQ_LSB                                                           8
+#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_FREQ_MASK                                                 0x00003f00
+#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_FREQ_GET(x)                                (((x) & 0x00003f00) >> 8)
+#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_FREQ_SET(x)                                (((x) << 8) & 0x00003f00)
+
+/* macros for cmac_power */
+#define PHY_ANALOG_CMAC_POWER_ADDRESS                                                                0x000003b4
+#define PHY_ANALOG_CMAC_POWER_OFFSET                                                                 0x000003b4
+#define PHY_ANALOG_CMAC_POWER_ATE_CMAC_POWER_CYCLES_MSB                                                       3
+#define PHY_ANALOG_CMAC_POWER_ATE_CMAC_POWER_CYCLES_LSB                                                       0
+#define PHY_ANALOG_CMAC_POWER_ATE_CMAC_POWER_CYCLES_MASK                                             0x0000000f
+#define PHY_ANALOG_CMAC_POWER_ATE_CMAC_POWER_CYCLES_GET(x)                            (((x) & 0x0000000f) >> 0)
+#define PHY_ANALOG_CMAC_POWER_ATE_CMAC_POWER_CYCLES_SET(x)                            (((x) << 0) & 0x0000000f)
+
+/* macros for cmac_cross_corr */
+#define PHY_ANALOG_CMAC_CROSS_CORR_ADDRESS                                                           0x000003b8
+#define PHY_ANALOG_CMAC_CROSS_CORR_OFFSET                                                            0x000003b8
+#define PHY_ANALOG_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_MSB                                                     3
+#define PHY_ANALOG_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_LSB                                                     0
+#define PHY_ANALOG_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_MASK                                           0x0000000f
+#define PHY_ANALOG_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_GET(x)                          (((x) & 0x0000000f) >> 0)
+#define PHY_ANALOG_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_SET(x)                          (((x) << 0) & 0x0000000f)
+
+/* macros for cmac_i2q2 */
+#define PHY_ANALOG_CMAC_I2Q2_ADDRESS                                                                 0x000003bc
+#define PHY_ANALOG_CMAC_I2Q2_OFFSET                                                                  0x000003bc
+#define PHY_ANALOG_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_MSB                                                         3
+#define PHY_ANALOG_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_LSB                                                         0
+#define PHY_ANALOG_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_MASK                                               0x0000000f
+#define PHY_ANALOG_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_GET(x)                              (((x) & 0x0000000f) >> 0)
+#define PHY_ANALOG_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_SET(x)                              (((x) << 0) & 0x0000000f)
+
+/* macros for cmac_power_hpf */
+#define PHY_ANALOG_CMAC_POWER_HPF_ADDRESS                                                            0x000003c0
+#define PHY_ANALOG_CMAC_POWER_HPF_OFFSET                                                             0x000003c0
+#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_MSB                                               3
+#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_LSB                                               0
+#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_MASK                                     0x0000000f
+#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_GET(x)                    (((x) & 0x0000000f) >> 0)
+#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_SET(x)                    (((x) << 0) & 0x0000000f)
+#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_MSB                                                 7
+#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_LSB                                                 4
+#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_MASK                                       0x000000f0
+#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_GET(x)                      (((x) & 0x000000f0) >> 4)
+#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_SET(x)                      (((x) << 4) & 0x000000f0)
+
+/* macros for rxdac_set1 */
+#define PHY_ANALOG_RXDAC_SET1_ADDRESS                                                                0x000003c4
+#define PHY_ANALOG_RXDAC_SET1_OFFSET                                                                 0x000003c4
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_MUX_MSB                                                               1
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_MUX_LSB                                                               0
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_MUX_MASK                                                     0x00000003
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_MUX_GET(x)                                    (((x) & 0x00000003) >> 0)
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_MUX_SET(x)                                    (((x) << 0) & 0x00000003)
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_HI_GAIN_MSB                                                           4
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_HI_GAIN_LSB                                                           4
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_HI_GAIN_MASK                                                 0x00000010
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_HI_GAIN_GET(x)                                (((x) & 0x00000010) >> 4)
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_HI_GAIN_SET(x)                                (((x) << 4) & 0x00000010)
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_MSB                                                         13
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_LSB                                                          8
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_MASK                                                0x00003f00
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_GET(x)                               (((x) & 0x00003f00) >> 8)
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_SET(x)                               (((x) << 8) & 0x00003f00)
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_MSB                                                 19
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_LSB                                                 16
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_MASK                                        0x000f0000
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_GET(x)                      (((x) & 0x000f0000) >> 16)
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_SET(x)                      (((x) << 16) & 0x000f0000)
+
+/* macros for rxdac_set2 */
+#define PHY_ANALOG_RXDAC_SET2_ADDRESS                                                                0x000003c8
+#define PHY_ANALOG_RXDAC_SET2_OFFSET                                                                 0x000003c8
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_HI_MSB                                                              4
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_HI_LSB                                                              0
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_HI_MASK                                                    0x0000001f
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_HI_GET(x)                                   (((x) & 0x0000001f) >> 0)
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_HI_SET(x)                                   (((x) << 0) & 0x0000001f)
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_HI_MSB                                                             12
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_HI_LSB                                                              8
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_HI_MASK                                                    0x00001f00
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_HI_GET(x)                                   (((x) & 0x00001f00) >> 8)
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_HI_SET(x)                                   (((x) << 8) & 0x00001f00)
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_LOW_MSB                                                            20
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_LOW_LSB                                                            16
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_LOW_MASK                                                   0x001f0000
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_LOW_GET(x)                                 (((x) & 0x001f0000) >> 16)
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_LOW_SET(x)                                 (((x) << 16) & 0x001f0000)
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_LOW_MSB                                                            28
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_LOW_LSB                                                            24
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_LOW_MASK                                                   0x1f000000
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_LOW_GET(x)                                 (((x) & 0x1f000000) >> 24)
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_LOW_SET(x)                                 (((x) << 24) & 0x1f000000)
+
+/* macros for rxdac_long_shift */
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_ADDRESS                                                          0x000003cc
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_OFFSET                                                           0x000003cc
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_MSB                                                    4
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_LSB                                                    0
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_MASK                                          0x0000001f
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_GET(x)                         (((x) & 0x0000001f) >> 0)
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_SET(x)                         (((x) << 0) & 0x0000001f)
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_MSB                                                   12
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_LSB                                                    8
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_MASK                                          0x00001f00
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_GET(x)                         (((x) & 0x00001f00) >> 8)
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_SET(x)                         (((x) << 8) & 0x00001f00)
+
+/* macros for cmac_results_i */
+#define PHY_ANALOG_CMAC_RESULTS_I_ADDRESS                                                            0x000003d0
+#define PHY_ANALOG_CMAC_RESULTS_I_OFFSET                                                             0x000003d0
+#define PHY_ANALOG_CMAC_RESULTS_I_ATE_CMAC_RESULTS_MSB                                                       31
+#define PHY_ANALOG_CMAC_RESULTS_I_ATE_CMAC_RESULTS_LSB                                                        0
+#define PHY_ANALOG_CMAC_RESULTS_I_ATE_CMAC_RESULTS_MASK                                              0xffffffff
+#define PHY_ANALOG_CMAC_RESULTS_I_ATE_CMAC_RESULTS_GET(x)                             (((x) & 0xffffffff) >> 0)
+#define PHY_ANALOG_CMAC_RESULTS_I_ATE_CMAC_RESULTS_SET(x)                             (((x) << 0) & 0xffffffff)
+
+/* macros for cmac_results_q */
+#define PHY_ANALOG_CMAC_RESULTS_Q_ADDRESS                                                            0x000003d4
+#define PHY_ANALOG_CMAC_RESULTS_Q_OFFSET                                                             0x000003d4
+#define PHY_ANALOG_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_MSB                                                       31
+#define PHY_ANALOG_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_LSB                                                        0
+#define PHY_ANALOG_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_MASK                                              0xffffffff
+#define PHY_ANALOG_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_GET(x)                             (((x) & 0xffffffff) >> 0)
+#define PHY_ANALOG_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_SET(x)                             (((x) << 0) & 0xffffffff)
+
+/* macros for PMU1 */
+#define PHY_ANALOG_PMU1_ADDRESS                                                                      0x00000740
+#define PHY_ANALOG_PMU1_OFFSET                                                                       0x00000740
+#define PHY_ANALOG_PMU1_SPARE_MSB                                                                            10
+#define PHY_ANALOG_PMU1_SPARE_LSB                                                                             0
+#define PHY_ANALOG_PMU1_SPARE_MASK                                                                   0x000007ff
+#define PHY_ANALOG_PMU1_SPARE_GET(x)                                                  (((x) & 0x000007ff) >> 0)
+#define PHY_ANALOG_PMU1_SPARE_SET(x)                                                  (((x) << 0) & 0x000007ff)
+#define PHY_ANALOG_PMU1_OTP_V25_PWD_MSB                                                                      11
+#define PHY_ANALOG_PMU1_OTP_V25_PWD_LSB                                                                      11
+#define PHY_ANALOG_PMU1_OTP_V25_PWD_MASK                                                             0x00000800
+#define PHY_ANALOG_PMU1_OTP_V25_PWD_GET(x)                                           (((x) & 0x00000800) >> 11)
+#define PHY_ANALOG_PMU1_OTP_V25_PWD_SET(x)                                           (((x) << 11) & 0x00000800)
+#define PHY_ANALOG_PMU1_PAREGON_MAN_MSB                                                                      12
+#define PHY_ANALOG_PMU1_PAREGON_MAN_LSB                                                                      12
+#define PHY_ANALOG_PMU1_PAREGON_MAN_MASK                                                             0x00001000
+#define PHY_ANALOG_PMU1_PAREGON_MAN_GET(x)                                           (((x) & 0x00001000) >> 12)
+#define PHY_ANALOG_PMU1_PAREGON_MAN_SET(x)                                           (((x) << 12) & 0x00001000)
+#define PHY_ANALOG_PMU1_OTPREGON_MAN_MSB                                                                     13
+#define PHY_ANALOG_PMU1_OTPREGON_MAN_LSB                                                                     13
+#define PHY_ANALOG_PMU1_OTPREGON_MAN_MASK                                                            0x00002000
+#define PHY_ANALOG_PMU1_OTPREGON_MAN_GET(x)                                          (((x) & 0x00002000) >> 13)
+#define PHY_ANALOG_PMU1_OTPREGON_MAN_SET(x)                                          (((x) << 13) & 0x00002000)
+#define PHY_ANALOG_PMU1_DREGON_MAN_MSB                                                                       14
+#define PHY_ANALOG_PMU1_DREGON_MAN_LSB                                                                       14
+#define PHY_ANALOG_PMU1_DREGON_MAN_MASK                                                              0x00004000
+#define PHY_ANALOG_PMU1_DREGON_MAN_GET(x)                                            (((x) & 0x00004000) >> 14)
+#define PHY_ANALOG_PMU1_DREGON_MAN_SET(x)                                            (((x) << 14) & 0x00004000)
+#define PHY_ANALOG_PMU1_DISCONTMODEEN_MSB                                                                    15
+#define PHY_ANALOG_PMU1_DISCONTMODEEN_LSB                                                                    15
+#define PHY_ANALOG_PMU1_DISCONTMODEEN_MASK                                                           0x00008000
+#define PHY_ANALOG_PMU1_DISCONTMODEEN_GET(x)                                         (((x) & 0x00008000) >> 15)
+#define PHY_ANALOG_PMU1_DISCONTMODEEN_SET(x)                                         (((x) << 15) & 0x00008000)
+#define PHY_ANALOG_PMU1_SWREGON_MAN_MSB                                                                      16
+#define PHY_ANALOG_PMU1_SWREGON_MAN_LSB                                                                      16
+#define PHY_ANALOG_PMU1_SWREGON_MAN_MASK                                                             0x00010000
+#define PHY_ANALOG_PMU1_SWREGON_MAN_GET(x)                                           (((x) & 0x00010000) >> 16)
+#define PHY_ANALOG_PMU1_SWREGON_MAN_SET(x)                                           (((x) << 16) & 0x00010000)
+#define PHY_ANALOG_PMU1_SWREG_FREQCUR_MSB                                                                    18
+#define PHY_ANALOG_PMU1_SWREG_FREQCUR_LSB                                                                    17
+#define PHY_ANALOG_PMU1_SWREG_FREQCUR_MASK                                                           0x00060000
+#define PHY_ANALOG_PMU1_SWREG_FREQCUR_GET(x)                                         (((x) & 0x00060000) >> 17)
+#define PHY_ANALOG_PMU1_SWREG_FREQCUR_SET(x)                                         (((x) << 17) & 0x00060000)
+#define PHY_ANALOG_PMU1_SWREG_FREQCAP_MSB                                                                    21
+#define PHY_ANALOG_PMU1_SWREG_FREQCAP_LSB                                                                    19
+#define PHY_ANALOG_PMU1_SWREG_FREQCAP_MASK                                                           0x00380000
+#define PHY_ANALOG_PMU1_SWREG_FREQCAP_GET(x)                                         (((x) & 0x00380000) >> 19)
+#define PHY_ANALOG_PMU1_SWREG_FREQCAP_SET(x)                                         (((x) << 19) & 0x00380000)
+#define PHY_ANALOG_PMU1_SWREG_LVLCTR_MSB                                                                     23
+#define PHY_ANALOG_PMU1_SWREG_LVLCTR_LSB                                                                     22
+#define PHY_ANALOG_PMU1_SWREG_LVLCTR_MASK                                                            0x00c00000
+#define PHY_ANALOG_PMU1_SWREG_LVLCTR_GET(x)                                          (((x) & 0x00c00000) >> 22)
+#define PHY_ANALOG_PMU1_SWREG_LVLCTR_SET(x)                                          (((x) << 22) & 0x00c00000)
+#define PHY_ANALOG_PMU1_SREG_LVLCTR_MSB                                                                      25
+#define PHY_ANALOG_PMU1_SREG_LVLCTR_LSB                                                                      24
+#define PHY_ANALOG_PMU1_SREG_LVLCTR_MASK                                                             0x03000000
+#define PHY_ANALOG_PMU1_SREG_LVLCTR_GET(x)                                           (((x) & 0x03000000) >> 24)
+#define PHY_ANALOG_PMU1_SREG_LVLCTR_SET(x)                                           (((x) << 24) & 0x03000000)
+#define PHY_ANALOG_PMU1_DREG_LVLCTR_MSB                                                                      27
+#define PHY_ANALOG_PMU1_DREG_LVLCTR_LSB                                                                      26
+#define PHY_ANALOG_PMU1_DREG_LVLCTR_MASK                                                             0x0c000000
+#define PHY_ANALOG_PMU1_DREG_LVLCTR_GET(x)                                           (((x) & 0x0c000000) >> 26)
+#define PHY_ANALOG_PMU1_DREG_LVLCTR_SET(x)                                           (((x) << 26) & 0x0c000000)
+#define PHY_ANALOG_PMU1_PAREG_XPNP_MSB                                                                       28
+#define PHY_ANALOG_PMU1_PAREG_XPNP_LSB                                                                       28
+#define PHY_ANALOG_PMU1_PAREG_XPNP_MASK                                                              0x10000000
+#define PHY_ANALOG_PMU1_PAREG_XPNP_GET(x)                                            (((x) & 0x10000000) >> 28)
+#define PHY_ANALOG_PMU1_PAREG_XPNP_SET(x)                                            (((x) << 28) & 0x10000000)
+#define PHY_ANALOG_PMU1_PAREG_LVLCTR_MSB                                                                     31
+#define PHY_ANALOG_PMU1_PAREG_LVLCTR_LSB                                                                     29
+#define PHY_ANALOG_PMU1_PAREG_LVLCTR_MASK                                                            0xe0000000
+#define PHY_ANALOG_PMU1_PAREG_LVLCTR_GET(x)                                          (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_PMU1_PAREG_LVLCTR_SET(x)                                          (((x) << 29) & 0xe0000000)
+
+/* macros for PMU2 */
+#define PHY_ANALOG_PMU2_ADDRESS                                                                      0x00000744
+#define PHY_ANALOG_PMU2_OFFSET                                                                       0x00000744
+#define PHY_ANALOG_PMU2_SPARE_MSB                                                                             7
+#define PHY_ANALOG_PMU2_SPARE_LSB                                                                             0
+#define PHY_ANALOG_PMU2_SPARE_MASK                                                                   0x000000ff
+#define PHY_ANALOG_PMU2_SPARE_GET(x)                                                  (((x) & 0x000000ff) >> 0)
+#define PHY_ANALOG_PMU2_SPARE_SET(x)                                                  (((x) << 0) & 0x000000ff)
+#define PHY_ANALOG_PMU2_VBATT_1_3TOATB_MSB                                                                    8
+#define PHY_ANALOG_PMU2_VBATT_1_3TOATB_LSB                                                                    8
+#define PHY_ANALOG_PMU2_VBATT_1_3TOATB_MASK                                                          0x00000100
+#define PHY_ANALOG_PMU2_VBATT_1_3TOATB_GET(x)                                         (((x) & 0x00000100) >> 8)
+#define PHY_ANALOG_PMU2_VBATT_1_3TOATB_SET(x)                                         (((x) << 8) & 0x00000100)
+#define PHY_ANALOG_PMU2_VBATT_1_2TOATB_MSB                                                                    9
+#define PHY_ANALOG_PMU2_VBATT_1_2TOATB_LSB                                                                    9
+#define PHY_ANALOG_PMU2_VBATT_1_2TOATB_MASK                                                          0x00000200
+#define PHY_ANALOG_PMU2_VBATT_1_2TOATB_GET(x)                                         (((x) & 0x00000200) >> 9)
+#define PHY_ANALOG_PMU2_VBATT_1_2TOATB_SET(x)                                         (((x) << 9) & 0x00000200)
+#define PHY_ANALOG_PMU2_VBATT_2_3TOATB_MSB                                                                   10
+#define PHY_ANALOG_PMU2_VBATT_2_3TOATB_LSB                                                                   10
+#define PHY_ANALOG_PMU2_VBATT_2_3TOATB_MASK                                                          0x00000400
+#define PHY_ANALOG_PMU2_VBATT_2_3TOATB_GET(x)                                        (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_PMU2_VBATT_2_3TOATB_SET(x)                                        (((x) << 10) & 0x00000400)
+#define PHY_ANALOG_PMU2_PWD_BANDGAP_MAN_MSB                                                                  11
+#define PHY_ANALOG_PMU2_PWD_BANDGAP_MAN_LSB                                                                  11
+#define PHY_ANALOG_PMU2_PWD_BANDGAP_MAN_MASK                                                         0x00000800
+#define PHY_ANALOG_PMU2_PWD_BANDGAP_MAN_GET(x)                                       (((x) & 0x00000800) >> 11)
+#define PHY_ANALOG_PMU2_PWD_BANDGAP_MAN_SET(x)                                       (((x) << 11) & 0x00000800)
+#define PHY_ANALOG_PMU2_PWD_LFO_MAN_MSB                                                                      12
+#define PHY_ANALOG_PMU2_PWD_LFO_MAN_LSB                                                                      12
+#define PHY_ANALOG_PMU2_PWD_LFO_MAN_MASK                                                             0x00001000
+#define PHY_ANALOG_PMU2_PWD_LFO_MAN_GET(x)                                           (((x) & 0x00001000) >> 12)
+#define PHY_ANALOG_PMU2_PWD_LFO_MAN_SET(x)                                           (((x) << 12) & 0x00001000)
+#define PHY_ANALOG_PMU2_VBATT_LT_3P2_MSB                                                                     13
+#define PHY_ANALOG_PMU2_VBATT_LT_3P2_LSB                                                                     13
+#define PHY_ANALOG_PMU2_VBATT_LT_3P2_MASK                                                            0x00002000
+#define PHY_ANALOG_PMU2_VBATT_LT_3P2_GET(x)                                          (((x) & 0x00002000) >> 13)
+#define PHY_ANALOG_PMU2_VBATT_LT_3P2_SET(x)                                          (((x) << 13) & 0x00002000)
+#define PHY_ANALOG_PMU2_VBATT_LT_2P8_MSB                                                                     14
+#define PHY_ANALOG_PMU2_VBATT_LT_2P8_LSB                                                                     14
+#define PHY_ANALOG_PMU2_VBATT_LT_2P8_MASK                                                            0x00004000
+#define PHY_ANALOG_PMU2_VBATT_LT_2P8_GET(x)                                          (((x) & 0x00004000) >> 14)
+#define PHY_ANALOG_PMU2_VBATT_LT_2P8_SET(x)                                          (((x) << 14) & 0x00004000)
+#define PHY_ANALOG_PMU2_VBATT_GT_4P2_MSB                                                                     15
+#define PHY_ANALOG_PMU2_VBATT_GT_4P2_LSB                                                                     15
+#define PHY_ANALOG_PMU2_VBATT_GT_4P2_MASK                                                            0x00008000
+#define PHY_ANALOG_PMU2_VBATT_GT_4P2_GET(x)                                          (((x) & 0x00008000) >> 15)
+#define PHY_ANALOG_PMU2_VBATT_GT_4P2_SET(x)                                          (((x) << 15) & 0x00008000)
+#define PHY_ANALOG_PMU2_PMU_MAN_OVERRIDE_EN_MSB                                                              16
+#define PHY_ANALOG_PMU2_PMU_MAN_OVERRIDE_EN_LSB                                                              16
+#define PHY_ANALOG_PMU2_PMU_MAN_OVERRIDE_EN_MASK                                                     0x00010000
+#define PHY_ANALOG_PMU2_PMU_MAN_OVERRIDE_EN_GET(x)                                   (((x) & 0x00010000) >> 16)
+#define PHY_ANALOG_PMU2_PMU_MAN_OVERRIDE_EN_SET(x)                                   (((x) << 16) & 0x00010000)
+#define PHY_ANALOG_PMU2_VBATT_GT_LVLCTR_MSB                                                                  18
+#define PHY_ANALOG_PMU2_VBATT_GT_LVLCTR_LSB                                                                  17
+#define PHY_ANALOG_PMU2_VBATT_GT_LVLCTR_MASK                                                         0x00060000
+#define PHY_ANALOG_PMU2_VBATT_GT_LVLCTR_GET(x)                                       (((x) & 0x00060000) >> 17)
+#define PHY_ANALOG_PMU2_VBATT_GT_LVLCTR_SET(x)                                       (((x) << 17) & 0x00060000)
+#define PHY_ANALOG_PMU2_SWREGVSSL2ATB_MSB                                                                    19
+#define PHY_ANALOG_PMU2_SWREGVSSL2ATB_LSB                                                                    19
+#define PHY_ANALOG_PMU2_SWREGVSSL2ATB_MASK                                                           0x00080000
+#define PHY_ANALOG_PMU2_SWREGVSSL2ATB_GET(x)                                         (((x) & 0x00080000) >> 19)
+#define PHY_ANALOG_PMU2_SWREGVSSL2ATB_SET(x)                                         (((x) << 19) & 0x00080000)
+#define PHY_ANALOG_PMU2_SWREGVSSL_LVLCTR_MSB                                                                 21
+#define PHY_ANALOG_PMU2_SWREGVSSL_LVLCTR_LSB                                                                 20
+#define PHY_ANALOG_PMU2_SWREGVSSL_LVLCTR_MASK                                                        0x00300000
+#define PHY_ANALOG_PMU2_SWREGVSSL_LVLCTR_GET(x)                                      (((x) & 0x00300000) >> 20)
+#define PHY_ANALOG_PMU2_SWREGVSSL_LVLCTR_SET(x)                                      (((x) << 20) & 0x00300000)
+#define PHY_ANALOG_PMU2_SWREGVDDH2ATB_MSB                                                                    22
+#define PHY_ANALOG_PMU2_SWREGVDDH2ATB_LSB                                                                    22
+#define PHY_ANALOG_PMU2_SWREGVDDH2ATB_MASK                                                           0x00400000
+#define PHY_ANALOG_PMU2_SWREGVDDH2ATB_GET(x)                                         (((x) & 0x00400000) >> 22)
+#define PHY_ANALOG_PMU2_SWREGVDDH2ATB_SET(x)                                         (((x) << 22) & 0x00400000)
+#define PHY_ANALOG_PMU2_SWREGVDDH_LVLCTR_MSB                                                                 24
+#define PHY_ANALOG_PMU2_SWREGVDDH_LVLCTR_LSB                                                                 23
+#define PHY_ANALOG_PMU2_SWREGVDDH_LVLCTR_MASK                                                        0x01800000
+#define PHY_ANALOG_PMU2_SWREGVDDH_LVLCTR_GET(x)                                      (((x) & 0x01800000) >> 23)
+#define PHY_ANALOG_PMU2_SWREGVDDH_LVLCTR_SET(x)                                      (((x) << 23) & 0x01800000)
+#define PHY_ANALOG_PMU2_SWREG2ATB_MSB                                                                        27
+#define PHY_ANALOG_PMU2_SWREG2ATB_LSB                                                                        25
+#define PHY_ANALOG_PMU2_SWREG2ATB_MASK                                                               0x0e000000
+#define PHY_ANALOG_PMU2_SWREG2ATB_GET(x)                                             (((x) & 0x0e000000) >> 25)
+#define PHY_ANALOG_PMU2_SWREG2ATB_SET(x)                                             (((x) << 25) & 0x0e000000)
+#define PHY_ANALOG_PMU2_OTPREG2ATB_MSB                                                                       28
+#define PHY_ANALOG_PMU2_OTPREG2ATB_LSB                                                                       28
+#define PHY_ANALOG_PMU2_OTPREG2ATB_MASK                                                              0x10000000
+#define PHY_ANALOG_PMU2_OTPREG2ATB_GET(x)                                            (((x) & 0x10000000) >> 28)
+#define PHY_ANALOG_PMU2_OTPREG2ATB_SET(x)                                            (((x) << 28) & 0x10000000)
+#define PHY_ANALOG_PMU2_OTPREG_LVLCTR_MSB                                                                    30
+#define PHY_ANALOG_PMU2_OTPREG_LVLCTR_LSB                                                                    29
+#define PHY_ANALOG_PMU2_OTPREG_LVLCTR_MASK                                                           0x60000000
+#define PHY_ANALOG_PMU2_OTPREG_LVLCTR_GET(x)                                         (((x) & 0x60000000) >> 29)
+#define PHY_ANALOG_PMU2_OTPREG_LVLCTR_SET(x)                                         (((x) << 29) & 0x60000000)
+#define PHY_ANALOG_PMU2_DREG_LVLCTR_MANOVR_EN_MSB                                                            31
+#define PHY_ANALOG_PMU2_DREG_LVLCTR_MANOVR_EN_LSB                                                            31
+#define PHY_ANALOG_PMU2_DREG_LVLCTR_MANOVR_EN_MASK                                                   0x80000000
+#define PHY_ANALOG_PMU2_DREG_LVLCTR_MANOVR_EN_GET(x)                                 (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_PMU2_DREG_LVLCTR_MANOVR_EN_SET(x)                                 (((x) << 31) & 0x80000000)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct analog_intf_athr_wlan_reg_reg_s {
+  volatile unsigned int RXRF_BIAS1;                                    /*        0x0 - 0x4        */
+  volatile unsigned int RXRF_BIAS2;                                    /*        0x4 - 0x8        */
+  volatile unsigned int RXRF_GAINSTAGES;                               /*        0x8 - 0xc        */
+  volatile unsigned int RXRF_AGC;                                      /*        0xc - 0x10       */
+  volatile char pad__0[0x30];                                          /*       0x10 - 0x40       */
+  volatile unsigned int TXRF1;                                         /*       0x40 - 0x44       */
+  volatile unsigned int TXRF2;                                         /*       0x44 - 0x48       */
+  volatile unsigned int TXRF3;                                         /*       0x48 - 0x4c       */
+  volatile unsigned int TXRF4;                                         /*       0x4c - 0x50       */
+  volatile unsigned int TXRF5;                                         /*       0x50 - 0x54       */
+  volatile unsigned int TXRF6;                                         /*       0x54 - 0x58       */
+  volatile unsigned int TXRF7;                                         /*       0x58 - 0x5c       */
+  volatile unsigned int TXRF8;                                         /*       0x5c - 0x60       */
+  volatile unsigned int TXRF9;                                         /*       0x60 - 0x64       */
+  volatile unsigned int TXRF10;                                        /*       0x64 - 0x68       */
+  volatile unsigned int TXRF11;                                        /*       0x68 - 0x6c       */
+  volatile unsigned int TXRF12;                                        /*       0x6c - 0x70       */
+  volatile char pad__1[0x10];                                          /*       0x70 - 0x80       */
+  volatile unsigned int SYNTH1;                                        /*       0x80 - 0x84       */
+  volatile unsigned int SYNTH2;                                        /*       0x84 - 0x88       */
+  volatile unsigned int SYNTH3;                                        /*       0x88 - 0x8c       */
+  volatile unsigned int SYNTH4;                                        /*       0x8c - 0x90       */
+  volatile unsigned int SYNTH5;                                        /*       0x90 - 0x94       */
+  volatile unsigned int SYNTH6;                                        /*       0x94 - 0x98       */
+  volatile unsigned int SYNTH7;                                        /*       0x98 - 0x9c       */
+  volatile unsigned int SYNTH8;                                        /*       0x9c - 0xa0       */
+  volatile unsigned int SYNTH9;                                        /*       0xa0 - 0xa4       */
+  volatile unsigned int SYNTH10;                                       /*       0xa4 - 0xa8       */
+  volatile unsigned int SYNTH11;                                       /*       0xa8 - 0xac       */
+  volatile unsigned int SYNTH12;                                       /*       0xac - 0xb0       */
+  volatile unsigned int SYNTH13;                                       /*       0xb0 - 0xb4       */
+  volatile unsigned int SYNTH14;                                       /*       0xb4 - 0xb8       */
+  volatile char pad__2[0x8];                                           /*       0xb8 - 0xc0       */
+  volatile unsigned int BIAS1;                                         /*       0xc0 - 0xc4       */
+  volatile unsigned int BIAS2;                                         /*       0xc4 - 0xc8       */
+  volatile unsigned int BIAS3;                                         /*       0xc8 - 0xcc       */
+  volatile unsigned int BIAS4;                                         /*       0xcc - 0xd0       */
+  volatile char pad__3[0x30];                                          /*       0xd0 - 0x100      */
+  volatile unsigned int RXTX1;                                         /*      0x100 - 0x104      */
+  volatile unsigned int RXTX2;                                         /*      0x104 - 0x108      */
+  volatile unsigned int RXTX3;                                         /*      0x108 - 0x10c      */
+  volatile char pad__4[0x34];                                          /*      0x10c - 0x140      */
+  volatile unsigned int BB1;                                           /*      0x140 - 0x144      */
+  volatile unsigned int BB2;                                           /*      0x144 - 0x148      */
+  volatile unsigned int BB3;                                           /*      0x148 - 0x14c      */
+  volatile char pad__5[0x134];                                         /*      0x14c - 0x280      */
+  volatile unsigned int PLLCLKMODA;                                    /*      0x280 - 0x284      */
+  volatile unsigned int PLLCLKMODA2;                                   /*      0x284 - 0x288      */
+  volatile unsigned int TOP;                                           /*      0x288 - 0x28c      */
+  volatile unsigned int THERM;                                         /*      0x28c - 0x290      */
+  volatile unsigned int XTAL;                                          /*      0x290 - 0x294      */
+  volatile char pad__6[0xec];                                          /*      0x294 - 0x380      */
+  volatile unsigned int rbist_cntrl;                                   /*      0x380 - 0x384      */
+  volatile unsigned int tx_dc_offset;                                  /*      0x384 - 0x388      */
+  volatile unsigned int tx_tonegen0;                                   /*      0x388 - 0x38c      */
+  volatile unsigned int tx_tonegen1;                                   /*      0x38c - 0x390      */
+  volatile unsigned int tx_lftonegen0;                                 /*      0x390 - 0x394      */
+  volatile unsigned int tx_linear_ramp_i;                              /*      0x394 - 0x398      */
+  volatile unsigned int tx_linear_ramp_q;                              /*      0x398 - 0x39c      */
+  volatile unsigned int tx_prbs_mag;                                   /*      0x39c - 0x3a0      */
+  volatile unsigned int tx_prbs_seed_i;                                /*      0x3a0 - 0x3a4      */
+  volatile unsigned int tx_prbs_seed_q;                                /*      0x3a4 - 0x3a8      */
+  volatile unsigned int cmac_dc_cancel;                                /*      0x3a8 - 0x3ac      */
+  volatile unsigned int cmac_dc_offset;                                /*      0x3ac - 0x3b0      */
+  volatile unsigned int cmac_corr;                                     /*      0x3b0 - 0x3b4      */
+  volatile unsigned int cmac_power;                                    /*      0x3b4 - 0x3b8      */
+  volatile unsigned int cmac_cross_corr;                               /*      0x3b8 - 0x3bc      */
+  volatile unsigned int cmac_i2q2;                                     /*      0x3bc - 0x3c0      */
+  volatile unsigned int cmac_power_hpf;                                /*      0x3c0 - 0x3c4      */
+  volatile unsigned int rxdac_set1;                                    /*      0x3c4 - 0x3c8      */
+  volatile unsigned int rxdac_set2;                                    /*      0x3c8 - 0x3cc      */
+  volatile unsigned int rxdac_long_shift;                              /*      0x3cc - 0x3d0      */
+  volatile unsigned int cmac_results_i;                                /*      0x3d0 - 0x3d4      */
+  volatile unsigned int cmac_results_q;                                /*      0x3d4 - 0x3d8      */
+  volatile char pad__7[0x368];                                         /*      0x3d8 - 0x740      */
+  volatile unsigned int PMU1;                                          /*      0x740 - 0x744      */
+  volatile unsigned int PMU2;                                          /*      0x744 - 0x748      */
+} analog_intf_athr_wlan_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _ANALOG_INTF_ATHR_WLAN_REG_REG_H_ */
diff --git a/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/analog_intf_reg.h b/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/analog_intf_reg.h
new file mode 100644
index 00000000000..01b9eb54a43
--- /dev/null
+++ b/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/analog_intf_reg.h
@@ -0,0 +1,37 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifdef WLAN_HEADERS
+
+#include "analog_intf_athr_wlan_reg.h"
+
+
+#ifndef BT_HEADERS
+
+
+
+#endif
+#endif
+
+
+
diff --git a/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/apb_athr_wlan_map.h b/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/apb_athr_wlan_map.h
new file mode 100644
index 00000000000..609eb9841f5
--- /dev/null
+++ b/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/apb_athr_wlan_map.h
@@ -0,0 +1,40 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _APB_ATHR_WLAN_MAP_H_
+#define _APB_ATHR_WLAN_MAP_H_
+
+#define WLAN_RTC_BASE_ADDRESS                    0x00004000
+#define WLAN_VMC_BASE_ADDRESS                    0x00008000
+#define WLAN_UART_BASE_ADDRESS                   0x0000c000
+#define WLAN_DBG_UART_BASE_ADDRESS               0x0000d000
+#define WLAN_UMBOX_BASE_ADDRESS                  0x0000e000
+#define WLAN_SI_BASE_ADDRESS                     0x00010000
+#define WLAN_GPIO_BASE_ADDRESS                   0x00014000
+#define WLAN_MBOX_BASE_ADDRESS                   0x00018000
+#define WLAN_ANALOG_INTF_BASE_ADDRESS            0x0001c000
+#define WLAN_MAC_BASE_ADDRESS                    0x00020000
+#define WLAN_RDMA_BASE_ADDRESS                   0x00030100
+#define EFUSE_BASE_ADDRESS                       0x00031000
+
+#endif /* _APB_ATHR_WLAN_MAP_REG_H_ */
diff --git a/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/apb_map.h b/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/apb_map.h
new file mode 100644
index 00000000000..e4d2d62f0bb
--- /dev/null
+++ b/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/apb_map.h
@@ -0,0 +1,48 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifdef WLAN_HEADERS
+
+#include "apb_athr_wlan_map.h"
+
+
+#ifndef BT_HEADERS
+
+#define RTC_BASE_ADDRESS WLAN_RTC_BASE_ADDRESS
+#define VMC_BASE_ADDRESS WLAN_VMC_BASE_ADDRESS
+#define UART_BASE_ADDRESS WLAN_UART_BASE_ADDRESS
+#define DBG_UART_BASE_ADDRESS WLAN_DBG_UART_BASE_ADDRESS
+#define UMBOX_BASE_ADDRESS WLAN_UMBOX_BASE_ADDRESS
+#define SI_BASE_ADDRESS WLAN_SI_BASE_ADDRESS
+#define GPIO_BASE_ADDRESS WLAN_GPIO_BASE_ADDRESS
+#define MBOX_BASE_ADDRESS WLAN_MBOX_BASE_ADDRESS
+#define ANALOG_INTF_BASE_ADDRESS WLAN_ANALOG_INTF_BASE_ADDRESS
+#define MAC_BASE_ADDRESS WLAN_MAC_BASE_ADDRESS
+#define RDMA_BASE_ADDRESS WLAN_RDMA_BASE_ADDRESS
+
+
+#endif
+#endif
+
+
+
diff --git a/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/bb_lc_reg.h b/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/bb_lc_reg.h
new file mode 100644
index 00000000000..27119295316
--- /dev/null
+++ b/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/bb_lc_reg.h
@@ -0,0 +1,7076 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+/* Copyright (C) 2009 Denali Software Inc.  All rights reserved              */
+/* THIS FILE IS AUTOMATICALLY GENERATED BY DENALI BLUEPRINT, DO NOT EDIT     */
+
+
+#ifndef _BB_LC_REG_REG_H_
+#define _BB_LC_REG_REG_H_
+
+
+/* macros for BB_test_controls */
+#define PHY_BB_TEST_CONTROLS_ADDRESS                                                          0x00009800
+#define PHY_BB_TEST_CONTROLS_OFFSET                                                           0x00009800
+#define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_SEL_MSB                                                        3
+#define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_SEL_LSB                                                        0
+#define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_SEL_MASK                                              0x0000000f
+#define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_SEL_GET(x)                             (((x) & 0x0000000f) >> 0)
+#define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_SEL_SET(x)                             (((x) << 0) & 0x0000000f)
+#define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_MSB                                                            4
+#define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_LSB                                                            4
+#define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_MASK                                                  0x00000010
+#define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_GET(x)                                 (((x) & 0x00000010) >> 4)
+#define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_SET(x)                                 (((x) << 4) & 0x00000010)
+#define PHY_BB_TEST_CONTROLS_CF_RFSHIFT_SEL_MSB                                                        6
+#define PHY_BB_TEST_CONTROLS_CF_RFSHIFT_SEL_LSB                                                        5
+#define PHY_BB_TEST_CONTROLS_CF_RFSHIFT_SEL_MASK                                              0x00000060
+#define PHY_BB_TEST_CONTROLS_CF_RFSHIFT_SEL_GET(x)                             (((x) & 0x00000060) >> 5)
+#define PHY_BB_TEST_CONTROLS_CF_RFSHIFT_SEL_SET(x)                             (((x) << 5) & 0x00000060)
+#define PHY_BB_TEST_CONTROLS_CARDBUS_MODE_MSB                                                          9
+#define PHY_BB_TEST_CONTROLS_CARDBUS_MODE_LSB                                                          8
+#define PHY_BB_TEST_CONTROLS_CARDBUS_MODE_MASK                                                0x00000300
+#define PHY_BB_TEST_CONTROLS_CARDBUS_MODE_GET(x)                               (((x) & 0x00000300) >> 8)
+#define PHY_BB_TEST_CONTROLS_CARDBUS_MODE_SET(x)                               (((x) << 8) & 0x00000300)
+#define PHY_BB_TEST_CONTROLS_CLKOUT_IS_CLK32_MSB                                                      10
+#define PHY_BB_TEST_CONTROLS_CLKOUT_IS_CLK32_LSB                                                      10
+#define PHY_BB_TEST_CONTROLS_CLKOUT_IS_CLK32_MASK                                             0x00000400
+#define PHY_BB_TEST_CONTROLS_CLKOUT_IS_CLK32_GET(x)                           (((x) & 0x00000400) >> 10)
+#define PHY_BB_TEST_CONTROLS_CLKOUT_IS_CLK32_SET(x)                           (((x) << 10) & 0x00000400)
+#define PHY_BB_TEST_CONTROLS_ENABLE_RFSILENT_BB_MSB                                                   13
+#define PHY_BB_TEST_CONTROLS_ENABLE_RFSILENT_BB_LSB                                                   13
+#define PHY_BB_TEST_CONTROLS_ENABLE_RFSILENT_BB_MASK                                          0x00002000
+#define PHY_BB_TEST_CONTROLS_ENABLE_RFSILENT_BB_GET(x)                        (((x) & 0x00002000) >> 13)
+#define PHY_BB_TEST_CONTROLS_ENABLE_RFSILENT_BB_SET(x)                        (((x) << 13) & 0x00002000)
+#define PHY_BB_TEST_CONTROLS_ENABLE_MINI_OBS_MSB                                                      15
+#define PHY_BB_TEST_CONTROLS_ENABLE_MINI_OBS_LSB                                                      15
+#define PHY_BB_TEST_CONTROLS_ENABLE_MINI_OBS_MASK                                             0x00008000
+#define PHY_BB_TEST_CONTROLS_ENABLE_MINI_OBS_GET(x)                           (((x) & 0x00008000) >> 15)
+#define PHY_BB_TEST_CONTROLS_ENABLE_MINI_OBS_SET(x)                           (((x) << 15) & 0x00008000)
+#define PHY_BB_TEST_CONTROLS_SLOW_CLK160_MSB                                                          17
+#define PHY_BB_TEST_CONTROLS_SLOW_CLK160_LSB                                                          17
+#define PHY_BB_TEST_CONTROLS_SLOW_CLK160_MASK                                                 0x00020000
+#define PHY_BB_TEST_CONTROLS_SLOW_CLK160_GET(x)                               (((x) & 0x00020000) >> 17)
+#define PHY_BB_TEST_CONTROLS_SLOW_CLK160_SET(x)                               (((x) << 17) & 0x00020000)
+#define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_3_MSB                                                        18
+#define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_3_LSB                                                        18
+#define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_3_MASK                                               0x00040000
+#define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_3_GET(x)                             (((x) & 0x00040000) >> 18)
+#define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_3_SET(x)                             (((x) << 18) & 0x00040000)
+#define PHY_BB_TEST_CONTROLS_CF_BBB_OBS_SEL_MSB                                                       22
+#define PHY_BB_TEST_CONTROLS_CF_BBB_OBS_SEL_LSB                                                       19
+#define PHY_BB_TEST_CONTROLS_CF_BBB_OBS_SEL_MASK                                              0x00780000
+#define PHY_BB_TEST_CONTROLS_CF_BBB_OBS_SEL_GET(x)                            (((x) & 0x00780000) >> 19)
+#define PHY_BB_TEST_CONTROLS_CF_BBB_OBS_SEL_SET(x)                            (((x) << 19) & 0x00780000)
+#define PHY_BB_TEST_CONTROLS_RX_OBS_SEL_5TH_BIT_MSB                                                   23
+#define PHY_BB_TEST_CONTROLS_RX_OBS_SEL_5TH_BIT_LSB                                                   23
+#define PHY_BB_TEST_CONTROLS_RX_OBS_SEL_5TH_BIT_MASK                                          0x00800000
+#define PHY_BB_TEST_CONTROLS_RX_OBS_SEL_5TH_BIT_GET(x)                        (((x) & 0x00800000) >> 23)
+#define PHY_BB_TEST_CONTROLS_RX_OBS_SEL_5TH_BIT_SET(x)                        (((x) << 23) & 0x00800000)
+#define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_4_MSB                                                        24
+#define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_4_LSB                                                        24
+#define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_4_MASK                                               0x01000000
+#define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_4_GET(x)                             (((x) & 0x01000000) >> 24)
+#define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_4_SET(x)                             (((x) << 24) & 0x01000000)
+#define PHY_BB_TEST_CONTROLS_FORCE_AGC_CLEAR_MSB                                                      28
+#define PHY_BB_TEST_CONTROLS_FORCE_AGC_CLEAR_LSB                                                      28
+#define PHY_BB_TEST_CONTROLS_FORCE_AGC_CLEAR_MASK                                             0x10000000
+#define PHY_BB_TEST_CONTROLS_FORCE_AGC_CLEAR_GET(x)                           (((x) & 0x10000000) >> 28)
+#define PHY_BB_TEST_CONTROLS_FORCE_AGC_CLEAR_SET(x)                           (((x) << 28) & 0x10000000)
+#define PHY_BB_TEST_CONTROLS_TSTDAC_OUT_SEL_MSB                                                       31
+#define PHY_BB_TEST_CONTROLS_TSTDAC_OUT_SEL_LSB                                                       30
+#define PHY_BB_TEST_CONTROLS_TSTDAC_OUT_SEL_MASK                                              0xc0000000
+#define PHY_BB_TEST_CONTROLS_TSTDAC_OUT_SEL_GET(x)                            (((x) & 0xc0000000) >> 30)
+#define PHY_BB_TEST_CONTROLS_TSTDAC_OUT_SEL_SET(x)                            (((x) << 30) & 0xc0000000)
+
+/* macros for BB_gen_controls */
+#define PHY_BB_GEN_CONTROLS_ADDRESS                                                           0x00009804
+#define PHY_BB_GEN_CONTROLS_OFFSET                                                            0x00009804
+#define PHY_BB_GEN_CONTROLS_TURBO_MSB                                                                  0
+#define PHY_BB_GEN_CONTROLS_TURBO_LSB                                                                  0
+#define PHY_BB_GEN_CONTROLS_TURBO_MASK                                                        0x00000001
+#define PHY_BB_GEN_CONTROLS_TURBO_GET(x)                                       (((x) & 0x00000001) >> 0)
+#define PHY_BB_GEN_CONTROLS_TURBO_SET(x)                                       (((x) << 0) & 0x00000001)
+#define PHY_BB_GEN_CONTROLS_CF_SHORT20_MSB                                                             1
+#define PHY_BB_GEN_CONTROLS_CF_SHORT20_LSB                                                             1
+#define PHY_BB_GEN_CONTROLS_CF_SHORT20_MASK                                                   0x00000002
+#define PHY_BB_GEN_CONTROLS_CF_SHORT20_GET(x)                                  (((x) & 0x00000002) >> 1)
+#define PHY_BB_GEN_CONTROLS_CF_SHORT20_SET(x)                                  (((x) << 1) & 0x00000002)
+#define PHY_BB_GEN_CONTROLS_DYN_20_40_MSB                                                              2
+#define PHY_BB_GEN_CONTROLS_DYN_20_40_LSB                                                              2
+#define PHY_BB_GEN_CONTROLS_DYN_20_40_MASK                                                    0x00000004
+#define PHY_BB_GEN_CONTROLS_DYN_20_40_GET(x)                                   (((x) & 0x00000004) >> 2)
+#define PHY_BB_GEN_CONTROLS_DYN_20_40_SET(x)                                   (((x) << 2) & 0x00000004)
+#define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_ONLY_MSB                                                     3
+#define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_ONLY_LSB                                                     3
+#define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_ONLY_MASK                                           0x00000008
+#define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_ONLY_GET(x)                          (((x) & 0x00000008) >> 3)
+#define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_ONLY_SET(x)                          (((x) << 3) & 0x00000008)
+#define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_CHN_MSB                                                      4
+#define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_CHN_LSB                                                      4
+#define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_CHN_MASK                                            0x00000010
+#define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_CHN_GET(x)                           (((x) & 0x00000010) >> 4)
+#define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_CHN_SET(x)                           (((x) << 4) & 0x00000010)
+#define PHY_BB_GEN_CONTROLS_DYN_20_40_EXT_CHN_MSB                                                      5
+#define PHY_BB_GEN_CONTROLS_DYN_20_40_EXT_CHN_LSB                                                      5
+#define PHY_BB_GEN_CONTROLS_DYN_20_40_EXT_CHN_MASK                                            0x00000020
+#define PHY_BB_GEN_CONTROLS_DYN_20_40_EXT_CHN_GET(x)                           (((x) & 0x00000020) >> 5)
+#define PHY_BB_GEN_CONTROLS_DYN_20_40_EXT_CHN_SET(x)                           (((x) << 5) & 0x00000020)
+#define PHY_BB_GEN_CONTROLS_HT_ENABLE_MSB                                                              6
+#define PHY_BB_GEN_CONTROLS_HT_ENABLE_LSB                                                              6
+#define PHY_BB_GEN_CONTROLS_HT_ENABLE_MASK                                                    0x00000040
+#define PHY_BB_GEN_CONTROLS_HT_ENABLE_GET(x)                                   (((x) & 0x00000040) >> 6)
+#define PHY_BB_GEN_CONTROLS_HT_ENABLE_SET(x)                                   (((x) << 6) & 0x00000040)
+#define PHY_BB_GEN_CONTROLS_ALLOW_SHORT_GI_MSB                                                         7
+#define PHY_BB_GEN_CONTROLS_ALLOW_SHORT_GI_LSB                                                         7
+#define PHY_BB_GEN_CONTROLS_ALLOW_SHORT_GI_MASK                                               0x00000080
+#define PHY_BB_GEN_CONTROLS_ALLOW_SHORT_GI_GET(x)                              (((x) & 0x00000080) >> 7)
+#define PHY_BB_GEN_CONTROLS_ALLOW_SHORT_GI_SET(x)                              (((x) << 7) & 0x00000080)
+#define PHY_BB_GEN_CONTROLS_CF_2_CHAINS_USE_WALSH_MSB                                                  8
+#define PHY_BB_GEN_CONTROLS_CF_2_CHAINS_USE_WALSH_LSB                                                  8
+#define PHY_BB_GEN_CONTROLS_CF_2_CHAINS_USE_WALSH_MASK                                        0x00000100
+#define PHY_BB_GEN_CONTROLS_CF_2_CHAINS_USE_WALSH_GET(x)                       (((x) & 0x00000100) >> 8)
+#define PHY_BB_GEN_CONTROLS_CF_2_CHAINS_USE_WALSH_SET(x)                       (((x) << 8) & 0x00000100)
+#define PHY_BB_GEN_CONTROLS_CF_SINGLE_HT_LTF1_MSB                                                      9
+#define PHY_BB_GEN_CONTROLS_CF_SINGLE_HT_LTF1_LSB                                                      9
+#define PHY_BB_GEN_CONTROLS_CF_SINGLE_HT_LTF1_MASK                                            0x00000200
+#define PHY_BB_GEN_CONTROLS_CF_SINGLE_HT_LTF1_GET(x)                           (((x) & 0x00000200) >> 9)
+#define PHY_BB_GEN_CONTROLS_CF_SINGLE_HT_LTF1_SET(x)                           (((x) << 9) & 0x00000200)
+#define PHY_BB_GEN_CONTROLS_GF_ENABLE_MSB                                                             10
+#define PHY_BB_GEN_CONTROLS_GF_ENABLE_LSB                                                             10
+#define PHY_BB_GEN_CONTROLS_GF_ENABLE_MASK                                                    0x00000400
+#define PHY_BB_GEN_CONTROLS_GF_ENABLE_GET(x)                                  (((x) & 0x00000400) >> 10)
+#define PHY_BB_GEN_CONTROLS_GF_ENABLE_SET(x)                                  (((x) << 10) & 0x00000400)
+#define PHY_BB_GEN_CONTROLS_BYPASS_DAC_FIFO_N_MSB                                                     11
+#define PHY_BB_GEN_CONTROLS_BYPASS_DAC_FIFO_N_LSB                                                     11
+#define PHY_BB_GEN_CONTROLS_BYPASS_DAC_FIFO_N_MASK                                            0x00000800
+#define PHY_BB_GEN_CONTROLS_BYPASS_DAC_FIFO_N_GET(x)                          (((x) & 0x00000800) >> 11)
+#define PHY_BB_GEN_CONTROLS_BYPASS_DAC_FIFO_N_SET(x)                          (((x) << 11) & 0x00000800)
+
+/* macros for BB_test_controls_status */
+#define PHY_BB_TEST_CONTROLS_STATUS_ADDRESS                                                   0x00009808
+#define PHY_BB_TEST_CONTROLS_STATUS_OFFSET                                                    0x00009808
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTDAC_EN_MSB                                                   0
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTDAC_EN_LSB                                                   0
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTDAC_EN_MASK                                         0x00000001
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTDAC_EN_GET(x)                        (((x) & 0x00000001) >> 0)
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTDAC_EN_SET(x)                        (((x) << 0) & 0x00000001)
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_IS_TSTDAC_MSB                                            1
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_IS_TSTDAC_LSB                                            1
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_IS_TSTDAC_MASK                                  0x00000002
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_IS_TSTDAC_GET(x)                 (((x) & 0x00000002) >> 1)
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_IS_TSTDAC_SET(x)                 (((x) << 1) & 0x00000002)
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_SEL_MSB                                                  4
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_SEL_LSB                                                  2
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_SEL_MASK                                        0x0000001c
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_SEL_GET(x)                       (((x) & 0x0000001c) >> 2)
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_SEL_SET(x)                       (((x) << 2) & 0x0000001c)
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_MUX_SEL_MSB                                              6
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_MUX_SEL_LSB                                              5
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_MUX_SEL_MASK                                    0x00000060
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_MUX_SEL_GET(x)                   (((x) & 0x00000060) >> 5)
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_MUX_SEL_SET(x)                   (((x) << 5) & 0x00000060)
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_ALTERNATE_MSB                                            7
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_ALTERNATE_LSB                                            7
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_ALTERNATE_MASK                                  0x00000080
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_ALTERNATE_GET(x)                 (((x) & 0x00000080) >> 7)
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_ALTERNATE_SET(x)                 (((x) << 7) & 0x00000080)
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTADC_EN_MSB                                                   8
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTADC_EN_LSB                                                   8
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTADC_EN_MASK                                         0x00000100
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTADC_EN_GET(x)                        (((x) & 0x00000100) >> 8)
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTADC_EN_SET(x)                        (((x) << 8) & 0x00000100)
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_RX_SRC_IS_TSTADC_MSB                                            9
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_RX_SRC_IS_TSTADC_LSB                                            9
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_RX_SRC_IS_TSTADC_MASK                                  0x00000200
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_RX_SRC_IS_TSTADC_GET(x)                 (((x) & 0x00000200) >> 9)
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_RX_SRC_IS_TSTADC_SET(x)                 (((x) << 9) & 0x00000200)
+#define PHY_BB_TEST_CONTROLS_STATUS_RX_OBS_SEL_MSB                                                    13
+#define PHY_BB_TEST_CONTROLS_STATUS_RX_OBS_SEL_LSB                                                    10
+#define PHY_BB_TEST_CONTROLS_STATUS_RX_OBS_SEL_MASK                                           0x00003c00
+#define PHY_BB_TEST_CONTROLS_STATUS_RX_OBS_SEL_GET(x)                         (((x) & 0x00003c00) >> 10)
+#define PHY_BB_TEST_CONTROLS_STATUS_RX_OBS_SEL_SET(x)                         (((x) << 10) & 0x00003c00)
+#define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_A2_WARM_RESET_MSB                                         14
+#define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_A2_WARM_RESET_LSB                                         14
+#define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_A2_WARM_RESET_MASK                                0x00004000
+#define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_A2_WARM_RESET_GET(x)              (((x) & 0x00004000) >> 14)
+#define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_A2_WARM_RESET_SET(x)              (((x) << 14) & 0x00004000)
+#define PHY_BB_TEST_CONTROLS_STATUS_RESET_A2_MSB                                                      15
+#define PHY_BB_TEST_CONTROLS_STATUS_RESET_A2_LSB                                                      15
+#define PHY_BB_TEST_CONTROLS_STATUS_RESET_A2_MASK                                             0x00008000
+#define PHY_BB_TEST_CONTROLS_STATUS_RESET_A2_GET(x)                           (((x) & 0x00008000) >> 15)
+#define PHY_BB_TEST_CONTROLS_STATUS_RESET_A2_SET(x)                           (((x) << 15) & 0x00008000)
+#define PHY_BB_TEST_CONTROLS_STATUS_AGC_OBS_SEL_MSB                                                   18
+#define PHY_BB_TEST_CONTROLS_STATUS_AGC_OBS_SEL_LSB                                                   16
+#define PHY_BB_TEST_CONTROLS_STATUS_AGC_OBS_SEL_MASK                                          0x00070000
+#define PHY_BB_TEST_CONTROLS_STATUS_AGC_OBS_SEL_GET(x)                        (((x) & 0x00070000) >> 16)
+#define PHY_BB_TEST_CONTROLS_STATUS_AGC_OBS_SEL_SET(x)                        (((x) << 16) & 0x00070000)
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_ENABLE_FFT_DUMP_MSB                                            19
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_ENABLE_FFT_DUMP_LSB                                            19
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_ENABLE_FFT_DUMP_MASK                                   0x00080000
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_ENABLE_FFT_DUMP_GET(x)                 (((x) & 0x00080000) >> 19)
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_ENABLE_FFT_DUMP_SET(x)                 (((x) << 19) & 0x00080000)
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_IN_MSB                                               23
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_IN_LSB                                               23
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_IN_MASK                                      0x00800000
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_IN_GET(x)                    (((x) & 0x00800000) >> 23)
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_IN_SET(x)                    (((x) << 23) & 0x00800000)
+#define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_AGC_TO_A2_MSB                                             27
+#define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_AGC_TO_A2_LSB                                             27
+#define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_AGC_TO_A2_MASK                                    0x08000000
+#define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_AGC_TO_A2_GET(x)                  (((x) & 0x08000000) >> 27)
+#define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_AGC_TO_A2_SET(x)                  (((x) << 27) & 0x08000000)
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_EN_MSB                                               28
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_EN_LSB                                               28
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_EN_MASK                                      0x10000000
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_EN_GET(x)                    (((x) & 0x10000000) >> 28)
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_EN_SET(x)                    (((x) << 28) & 0x10000000)
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_SEL_MSB                                              30
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_SEL_LSB                                              29
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_SEL_MASK                                     0x60000000
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_SEL_GET(x)                   (((x) & 0x60000000) >> 29)
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_SEL_SET(x)                   (((x) << 29) & 0x60000000)
+
+/* macros for BB_timing_controls_1 */
+#define PHY_BB_TIMING_CONTROLS_1_ADDRESS                                                      0x0000980c
+#define PHY_BB_TIMING_CONTROLS_1_OFFSET                                                       0x0000980c
+#define PHY_BB_TIMING_CONTROLS_1_STE_THR_MSB                                                           6
+#define PHY_BB_TIMING_CONTROLS_1_STE_THR_LSB                                                           0
+#define PHY_BB_TIMING_CONTROLS_1_STE_THR_MASK                                                 0x0000007f
+#define PHY_BB_TIMING_CONTROLS_1_STE_THR_GET(x)                                (((x) & 0x0000007f) >> 0)
+#define PHY_BB_TIMING_CONTROLS_1_STE_THR_SET(x)                                (((x) << 0) & 0x0000007f)
+#define PHY_BB_TIMING_CONTROLS_1_STE_TO_LONG1_MSB                                                     12
+#define PHY_BB_TIMING_CONTROLS_1_STE_TO_LONG1_LSB                                                      7
+#define PHY_BB_TIMING_CONTROLS_1_STE_TO_LONG1_MASK                                            0x00001f80
+#define PHY_BB_TIMING_CONTROLS_1_STE_TO_LONG1_GET(x)                           (((x) & 0x00001f80) >> 7)
+#define PHY_BB_TIMING_CONTROLS_1_STE_TO_LONG1_SET(x)                           (((x) << 7) & 0x00001f80)
+#define PHY_BB_TIMING_CONTROLS_1_TIMING_BACKOFF_MSB                                                   16
+#define PHY_BB_TIMING_CONTROLS_1_TIMING_BACKOFF_LSB                                                   13
+#define PHY_BB_TIMING_CONTROLS_1_TIMING_BACKOFF_MASK                                          0x0001e000
+#define PHY_BB_TIMING_CONTROLS_1_TIMING_BACKOFF_GET(x)                        (((x) & 0x0001e000) >> 13)
+#define PHY_BB_TIMING_CONTROLS_1_TIMING_BACKOFF_SET(x)                        (((x) << 13) & 0x0001e000)
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_HT_FINE_PPM_MSB                                               17
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_HT_FINE_PPM_LSB                                               17
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_HT_FINE_PPM_MASK                                      0x00020000
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_HT_FINE_PPM_GET(x)                    (((x) & 0x00020000) >> 17)
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_HT_FINE_PPM_SET(x)                    (((x) << 17) & 0x00020000)
+#define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_STREAM_MSB                                               19
+#define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_STREAM_LSB                                               18
+#define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_STREAM_MASK                                      0x000c0000
+#define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_STREAM_GET(x)                    (((x) & 0x000c0000) >> 18)
+#define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_STREAM_SET(x)                    (((x) << 18) & 0x000c0000)
+#define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_QAM_MSB                                                  21
+#define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_QAM_LSB                                                  20
+#define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_QAM_MASK                                         0x00300000
+#define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_QAM_GET(x)                       (((x) & 0x00300000) >> 20)
+#define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_QAM_SET(x)                       (((x) << 20) & 0x00300000)
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_CHANFIL_MSB                                              22
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_CHANFIL_LSB                                              22
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_CHANFIL_MASK                                     0x00400000
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_CHANFIL_GET(x)                   (((x) & 0x00400000) >> 22)
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_CHANFIL_SET(x)                   (((x) << 22) & 0x00400000)
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_RX_STBC_MSB                                                   23
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_RX_STBC_LSB                                                   23
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_RX_STBC_MASK                                          0x00800000
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_RX_STBC_GET(x)                        (((x) & 0x00800000) >> 23)
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_RX_STBC_SET(x)                        (((x) << 23) & 0x00800000)
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_CHANNEL_FILTER_MSB                                            24
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_CHANNEL_FILTER_LSB                                            24
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_CHANNEL_FILTER_MASK                                   0x01000000
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_CHANNEL_FILTER_GET(x)                 (((x) & 0x01000000) >> 24)
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_CHANNEL_FILTER_SET(x)                 (((x) << 24) & 0x01000000)
+#define PHY_BB_TIMING_CONTROLS_1_FALSE_ALARM_MSB                                                      26
+#define PHY_BB_TIMING_CONTROLS_1_FALSE_ALARM_LSB                                                      25
+#define PHY_BB_TIMING_CONTROLS_1_FALSE_ALARM_MASK                                             0x06000000
+#define PHY_BB_TIMING_CONTROLS_1_FALSE_ALARM_GET(x)                           (((x) & 0x06000000) >> 25)
+#define PHY_BB_TIMING_CONTROLS_1_FALSE_ALARM_SET(x)                           (((x) << 25) & 0x06000000)
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_RESCALE_MSB                                              27
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_RESCALE_LSB                                              27
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_RESCALE_MASK                                     0x08000000
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_RESCALE_GET(x)                   (((x) & 0x08000000) >> 27)
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_RESCALE_SET(x)                   (((x) << 27) & 0x08000000)
+#define PHY_BB_TIMING_CONTROLS_1_TIMING_LEAK_ENABLE_MSB                                               28
+#define PHY_BB_TIMING_CONTROLS_1_TIMING_LEAK_ENABLE_LSB                                               28
+#define PHY_BB_TIMING_CONTROLS_1_TIMING_LEAK_ENABLE_MASK                                      0x10000000
+#define PHY_BB_TIMING_CONTROLS_1_TIMING_LEAK_ENABLE_GET(x)                    (((x) & 0x10000000) >> 28)
+#define PHY_BB_TIMING_CONTROLS_1_TIMING_LEAK_ENABLE_SET(x)                    (((x) << 28) & 0x10000000)
+#define PHY_BB_TIMING_CONTROLS_1_COARSE_PPM_SELECT_MSB                                                30
+#define PHY_BB_TIMING_CONTROLS_1_COARSE_PPM_SELECT_LSB                                                29
+#define PHY_BB_TIMING_CONTROLS_1_COARSE_PPM_SELECT_MASK                                       0x60000000
+#define PHY_BB_TIMING_CONTROLS_1_COARSE_PPM_SELECT_GET(x)                     (((x) & 0x60000000) >> 29)
+#define PHY_BB_TIMING_CONTROLS_1_COARSE_PPM_SELECT_SET(x)                     (((x) << 29) & 0x60000000)
+#define PHY_BB_TIMING_CONTROLS_1_FFT_SCALING_MSB                                                      31
+#define PHY_BB_TIMING_CONTROLS_1_FFT_SCALING_LSB                                                      31
+#define PHY_BB_TIMING_CONTROLS_1_FFT_SCALING_MASK                                             0x80000000
+#define PHY_BB_TIMING_CONTROLS_1_FFT_SCALING_GET(x)                           (((x) & 0x80000000) >> 31)
+#define PHY_BB_TIMING_CONTROLS_1_FFT_SCALING_SET(x)                           (((x) << 31) & 0x80000000)
+
+/* macros for BB_timing_controls_2 */
+#define PHY_BB_TIMING_CONTROLS_2_ADDRESS                                                      0x00009810
+#define PHY_BB_TIMING_CONTROLS_2_OFFSET                                                       0x00009810
+#define PHY_BB_TIMING_CONTROLS_2_FORCED_DELTA_PHI_SYMBOL_MSB                                          11
+#define PHY_BB_TIMING_CONTROLS_2_FORCED_DELTA_PHI_SYMBOL_LSB                                           0
+#define PHY_BB_TIMING_CONTROLS_2_FORCED_DELTA_PHI_SYMBOL_MASK                                 0x00000fff
+#define PHY_BB_TIMING_CONTROLS_2_FORCED_DELTA_PHI_SYMBOL_GET(x)                (((x) & 0x00000fff) >> 0)
+#define PHY_BB_TIMING_CONTROLS_2_FORCED_DELTA_PHI_SYMBOL_SET(x)                (((x) << 0) & 0x00000fff)
+#define PHY_BB_TIMING_CONTROLS_2_FORCE_DELTA_PHI_SYMBOL_MSB                                           12
+#define PHY_BB_TIMING_CONTROLS_2_FORCE_DELTA_PHI_SYMBOL_LSB                                           12
+#define PHY_BB_TIMING_CONTROLS_2_FORCE_DELTA_PHI_SYMBOL_MASK                                  0x00001000
+#define PHY_BB_TIMING_CONTROLS_2_FORCE_DELTA_PHI_SYMBOL_GET(x)                (((x) & 0x00001000) >> 12)
+#define PHY_BB_TIMING_CONTROLS_2_FORCE_DELTA_PHI_SYMBOL_SET(x)                (((x) << 12) & 0x00001000)
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_MAGNITUDE_TRACK_MSB                                           13
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_MAGNITUDE_TRACK_LSB                                           13
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_MAGNITUDE_TRACK_MASK                                  0x00002000
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_MAGNITUDE_TRACK_GET(x)                (((x) & 0x00002000) >> 13)
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_MAGNITUDE_TRACK_SET(x)                (((x) << 13) & 0x00002000)
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_SLOPE_FILTER_MSB                                              14
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_SLOPE_FILTER_LSB                                              14
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_SLOPE_FILTER_MASK                                     0x00004000
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_SLOPE_FILTER_GET(x)                   (((x) & 0x00004000) >> 14)
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_SLOPE_FILTER_SET(x)                   (((x) << 14) & 0x00004000)
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_OFFSET_FILTER_MSB                                             15
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_OFFSET_FILTER_LSB                                             15
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_OFFSET_FILTER_MASK                                    0x00008000
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_OFFSET_FILTER_GET(x)                  (((x) & 0x00008000) >> 15)
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_OFFSET_FILTER_SET(x)                  (((x) << 15) & 0x00008000)
+#define PHY_BB_TIMING_CONTROLS_2_DC_OFF_DELTAF_THRES_MSB                                              22
+#define PHY_BB_TIMING_CONTROLS_2_DC_OFF_DELTAF_THRES_LSB                                              16
+#define PHY_BB_TIMING_CONTROLS_2_DC_OFF_DELTAF_THRES_MASK                                     0x007f0000
+#define PHY_BB_TIMING_CONTROLS_2_DC_OFF_DELTAF_THRES_GET(x)                   (((x) & 0x007f0000) >> 16)
+#define PHY_BB_TIMING_CONTROLS_2_DC_OFF_DELTAF_THRES_SET(x)                   (((x) << 16) & 0x007f0000)
+#define PHY_BB_TIMING_CONTROLS_2_DC_OFF_TIM_CONST_MSB                                                 26
+#define PHY_BB_TIMING_CONTROLS_2_DC_OFF_TIM_CONST_LSB                                                 24
+#define PHY_BB_TIMING_CONTROLS_2_DC_OFF_TIM_CONST_MASK                                        0x07000000
+#define PHY_BB_TIMING_CONTROLS_2_DC_OFF_TIM_CONST_GET(x)                      (((x) & 0x07000000) >> 24)
+#define PHY_BB_TIMING_CONTROLS_2_DC_OFF_TIM_CONST_SET(x)                      (((x) << 24) & 0x07000000)
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_MSB                                                 27
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_LSB                                                 27
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_MASK                                        0x08000000
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_GET(x)                      (((x) & 0x08000000) >> 27)
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_SET(x)                      (((x) << 27) & 0x08000000)
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_TRACK_MSB                                           28
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_TRACK_LSB                                           28
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_TRACK_MASK                                  0x10000000
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_TRACK_GET(x)                (((x) & 0x10000000) >> 28)
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_TRACK_SET(x)                (((x) << 28) & 0x10000000)
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_WEIGHTING_MSB                                                 29
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_WEIGHTING_LSB                                                 29
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_WEIGHTING_MASK                                        0x20000000
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_WEIGHTING_GET(x)                      (((x) & 0x20000000) >> 29)
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_WEIGHTING_SET(x)                      (((x) << 29) & 0x20000000)
+#define PHY_BB_TIMING_CONTROLS_2_TRACEBACK128_MSB                                                     30
+#define PHY_BB_TIMING_CONTROLS_2_TRACEBACK128_LSB                                                     30
+#define PHY_BB_TIMING_CONTROLS_2_TRACEBACK128_MASK                                            0x40000000
+#define PHY_BB_TIMING_CONTROLS_2_TRACEBACK128_GET(x)                          (((x) & 0x40000000) >> 30)
+#define PHY_BB_TIMING_CONTROLS_2_TRACEBACK128_SET(x)                          (((x) << 30) & 0x40000000)
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_HT_FINE_TIMING_MSB                                            31
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_HT_FINE_TIMING_LSB                                            31
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_HT_FINE_TIMING_MASK                                   0x80000000
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_HT_FINE_TIMING_GET(x)                 (((x) & 0x80000000) >> 31)
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_HT_FINE_TIMING_SET(x)                 (((x) << 31) & 0x80000000)
+
+/* macros for BB_timing_controls_3 */
+#define PHY_BB_TIMING_CONTROLS_3_ADDRESS                                                      0x00009814
+#define PHY_BB_TIMING_CONTROLS_3_OFFSET                                                       0x00009814
+#define PHY_BB_TIMING_CONTROLS_3_PPM_RESCUE_INTERVAL_MSB                                               7
+#define PHY_BB_TIMING_CONTROLS_3_PPM_RESCUE_INTERVAL_LSB                                               0
+#define PHY_BB_TIMING_CONTROLS_3_PPM_RESCUE_INTERVAL_MASK                                     0x000000ff
+#define PHY_BB_TIMING_CONTROLS_3_PPM_RESCUE_INTERVAL_GET(x)                    (((x) & 0x000000ff) >> 0)
+#define PHY_BB_TIMING_CONTROLS_3_PPM_RESCUE_INTERVAL_SET(x)                    (((x) << 0) & 0x000000ff)
+#define PHY_BB_TIMING_CONTROLS_3_ENABLE_PPM_RESCUE_MSB                                                 8
+#define PHY_BB_TIMING_CONTROLS_3_ENABLE_PPM_RESCUE_LSB                                                 8
+#define PHY_BB_TIMING_CONTROLS_3_ENABLE_PPM_RESCUE_MASK                                       0x00000100
+#define PHY_BB_TIMING_CONTROLS_3_ENABLE_PPM_RESCUE_GET(x)                      (((x) & 0x00000100) >> 8)
+#define PHY_BB_TIMING_CONTROLS_3_ENABLE_PPM_RESCUE_SET(x)                      (((x) << 8) & 0x00000100)
+#define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_PPM_MSB                                                   9
+#define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_PPM_LSB                                                   9
+#define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_PPM_MASK                                         0x00000200
+#define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_PPM_GET(x)                        (((x) & 0x00000200) >> 9)
+#define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_PPM_SET(x)                        (((x) << 9) & 0x00000200)
+#define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_INTERP_MSB                                               10
+#define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_INTERP_LSB                                               10
+#define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_INTERP_MASK                                      0x00000400
+#define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_INTERP_GET(x)                    (((x) & 0x00000400) >> 10)
+#define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_INTERP_SET(x)                    (((x) << 10) & 0x00000400)
+#define PHY_BB_TIMING_CONTROLS_3_CONTINUOUS_PPM_RESCUE_MSB                                            11
+#define PHY_BB_TIMING_CONTROLS_3_CONTINUOUS_PPM_RESCUE_LSB                                            11
+#define PHY_BB_TIMING_CONTROLS_3_CONTINUOUS_PPM_RESCUE_MASK                                   0x00000800
+#define PHY_BB_TIMING_CONTROLS_3_CONTINUOUS_PPM_RESCUE_GET(x)                 (((x) & 0x00000800) >> 11)
+#define PHY_BB_TIMING_CONTROLS_3_CONTINUOUS_PPM_RESCUE_SET(x)                 (((x) << 11) & 0x00000800)
+#define PHY_BB_TIMING_CONTROLS_3_ENABLE_DF_CHANEST_MSB                                                12
+#define PHY_BB_TIMING_CONTROLS_3_ENABLE_DF_CHANEST_LSB                                                12
+#define PHY_BB_TIMING_CONTROLS_3_ENABLE_DF_CHANEST_MASK                                       0x00001000
+#define PHY_BB_TIMING_CONTROLS_3_ENABLE_DF_CHANEST_GET(x)                     (((x) & 0x00001000) >> 12)
+#define PHY_BB_TIMING_CONTROLS_3_ENABLE_DF_CHANEST_SET(x)                     (((x) << 12) & 0x00001000)
+#define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_EXP_MSB                                             16
+#define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_EXP_LSB                                             13
+#define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_EXP_MASK                                    0x0001e000
+#define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_EXP_GET(x)                  (((x) & 0x0001e000) >> 13)
+#define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_EXP_SET(x)                  (((x) << 13) & 0x0001e000)
+#define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_MAN_MSB                                             31
+#define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_MAN_LSB                                             17
+#define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_MAN_MASK                                    0xfffe0000
+#define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_MAN_GET(x)                  (((x) & 0xfffe0000) >> 17)
+#define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_MAN_SET(x)                  (((x) << 17) & 0xfffe0000)
+
+/* macros for BB_D2_chip_id */
+#define PHY_BB_D2_CHIP_ID_ADDRESS                                                             0x00009818
+#define PHY_BB_D2_CHIP_ID_OFFSET                                                              0x00009818
+#define PHY_BB_D2_CHIP_ID_OLD_ID_MSB                                                                   7
+#define PHY_BB_D2_CHIP_ID_OLD_ID_LSB                                                                   0
+#define PHY_BB_D2_CHIP_ID_OLD_ID_MASK                                                         0x000000ff
+#define PHY_BB_D2_CHIP_ID_OLD_ID_GET(x)                                        (((x) & 0x000000ff) >> 0)
+#define PHY_BB_D2_CHIP_ID_ID_MSB                                                                      31
+#define PHY_BB_D2_CHIP_ID_ID_LSB                                                                       8
+#define PHY_BB_D2_CHIP_ID_ID_MASK                                                             0xffffff00
+#define PHY_BB_D2_CHIP_ID_ID_GET(x)                                            (((x) & 0xffffff00) >> 8)
+
+/* macros for BB_active */
+#define PHY_BB_ACTIVE_ADDRESS                                                                 0x0000981c
+#define PHY_BB_ACTIVE_OFFSET                                                                  0x0000981c
+#define PHY_BB_ACTIVE_CF_ACTIVE_MSB                                                                    0
+#define PHY_BB_ACTIVE_CF_ACTIVE_LSB                                                                    0
+#define PHY_BB_ACTIVE_CF_ACTIVE_MASK                                                          0x00000001
+#define PHY_BB_ACTIVE_CF_ACTIVE_GET(x)                                         (((x) & 0x00000001) >> 0)
+#define PHY_BB_ACTIVE_CF_ACTIVE_SET(x)                                         (((x) << 0) & 0x00000001)
+
+/* macros for BB_tx_timing_1 */
+#define PHY_BB_TX_TIMING_1_ADDRESS                                                            0x00009820
+#define PHY_BB_TX_TIMING_1_OFFSET                                                             0x00009820
+#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_ADC_OFF_MSB                                                     7
+#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_ADC_OFF_LSB                                                     0
+#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_ADC_OFF_MASK                                           0x000000ff
+#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_ADC_OFF_GET(x)                          (((x) & 0x000000ff) >> 0)
+#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_ADC_OFF_SET(x)                          (((x) << 0) & 0x000000ff)
+#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_RX_OFF_MSB                                                  15
+#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_RX_OFF_LSB                                                   8
+#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_RX_OFF_MASK                                         0x0000ff00
+#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_RX_OFF_GET(x)                        (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_RX_OFF_SET(x)                        (((x) << 8) & 0x0000ff00)
+#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_DAC_ON_MSB                                                     23
+#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_DAC_ON_LSB                                                     16
+#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_DAC_ON_MASK                                            0x00ff0000
+#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_DAC_ON_GET(x)                          (((x) & 0x00ff0000) >> 16)
+#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_DAC_ON_SET(x)                          (((x) << 16) & 0x00ff0000)
+#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_TX_ON_MSB                                                   31
+#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_TX_ON_LSB                                                   24
+#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_TX_ON_MASK                                          0xff000000
+#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_TX_ON_GET(x)                        (((x) & 0xff000000) >> 24)
+#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_TX_ON_SET(x)                        (((x) << 24) & 0xff000000)
+
+/* macros for BB_tx_timing_2 */
+#define PHY_BB_TX_TIMING_2_ADDRESS                                                            0x00009824
+#define PHY_BB_TX_TIMING_2_OFFSET                                                             0x00009824
+#define PHY_BB_TX_TIMING_2_TX_FRAME_TO_TX_D_START_MSB                                                  7
+#define PHY_BB_TX_TIMING_2_TX_FRAME_TO_TX_D_START_LSB                                                  0
+#define PHY_BB_TX_TIMING_2_TX_FRAME_TO_TX_D_START_MASK                                        0x000000ff
+#define PHY_BB_TX_TIMING_2_TX_FRAME_TO_TX_D_START_GET(x)                       (((x) & 0x000000ff) >> 0)
+#define PHY_BB_TX_TIMING_2_TX_FRAME_TO_TX_D_START_SET(x)                       (((x) << 0) & 0x000000ff)
+#define PHY_BB_TX_TIMING_2_TX_FRAME_TO_PA_ON_MSB                                                      15
+#define PHY_BB_TX_TIMING_2_TX_FRAME_TO_PA_ON_LSB                                                       8
+#define PHY_BB_TX_TIMING_2_TX_FRAME_TO_PA_ON_MASK                                             0x0000ff00
+#define PHY_BB_TX_TIMING_2_TX_FRAME_TO_PA_ON_GET(x)                            (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_TX_TIMING_2_TX_FRAME_TO_PA_ON_SET(x)                            (((x) << 8) & 0x0000ff00)
+#define PHY_BB_TX_TIMING_2_TX_END_TO_PA_OFF_MSB                                                       23
+#define PHY_BB_TX_TIMING_2_TX_END_TO_PA_OFF_LSB                                                       16
+#define PHY_BB_TX_TIMING_2_TX_END_TO_PA_OFF_MASK                                              0x00ff0000
+#define PHY_BB_TX_TIMING_2_TX_END_TO_PA_OFF_GET(x)                            (((x) & 0x00ff0000) >> 16)
+#define PHY_BB_TX_TIMING_2_TX_END_TO_PA_OFF_SET(x)                            (((x) << 16) & 0x00ff0000)
+#define PHY_BB_TX_TIMING_2_TX_END_TO_A2_TX_OFF_MSB                                                    31
+#define PHY_BB_TX_TIMING_2_TX_END_TO_A2_TX_OFF_LSB                                                    24
+#define PHY_BB_TX_TIMING_2_TX_END_TO_A2_TX_OFF_MASK                                           0xff000000
+#define PHY_BB_TX_TIMING_2_TX_END_TO_A2_TX_OFF_GET(x)                         (((x) & 0xff000000) >> 24)
+#define PHY_BB_TX_TIMING_2_TX_END_TO_A2_TX_OFF_SET(x)                         (((x) << 24) & 0xff000000)
+
+/* macros for BB_tx_timing_3 */
+#define PHY_BB_TX_TIMING_3_ADDRESS                                                            0x00009828
+#define PHY_BB_TX_TIMING_3_OFFSET                                                             0x00009828
+#define PHY_BB_TX_TIMING_3_TX_END_TO_DAC_OFF_MSB                                                       7
+#define PHY_BB_TX_TIMING_3_TX_END_TO_DAC_OFF_LSB                                                       0
+#define PHY_BB_TX_TIMING_3_TX_END_TO_DAC_OFF_MASK                                             0x000000ff
+#define PHY_BB_TX_TIMING_3_TX_END_TO_DAC_OFF_GET(x)                            (((x) & 0x000000ff) >> 0)
+#define PHY_BB_TX_TIMING_3_TX_END_TO_DAC_OFF_SET(x)                            (((x) << 0) & 0x000000ff)
+#define PHY_BB_TX_TIMING_3_TX_FRAME_TO_THERM_CHAIN_ON_MSB                                             15
+#define PHY_BB_TX_TIMING_3_TX_FRAME_TO_THERM_CHAIN_ON_LSB                                              8
+#define PHY_BB_TX_TIMING_3_TX_FRAME_TO_THERM_CHAIN_ON_MASK                                    0x0000ff00
+#define PHY_BB_TX_TIMING_3_TX_FRAME_TO_THERM_CHAIN_ON_GET(x)                   (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_TX_TIMING_3_TX_FRAME_TO_THERM_CHAIN_ON_SET(x)                   (((x) << 8) & 0x0000ff00)
+#define PHY_BB_TX_TIMING_3_TX_END_TO_A2_RX_ON_MSB                                                     23
+#define PHY_BB_TX_TIMING_3_TX_END_TO_A2_RX_ON_LSB                                                     16
+#define PHY_BB_TX_TIMING_3_TX_END_TO_A2_RX_ON_MASK                                            0x00ff0000
+#define PHY_BB_TX_TIMING_3_TX_END_TO_A2_RX_ON_GET(x)                          (((x) & 0x00ff0000) >> 16)
+#define PHY_BB_TX_TIMING_3_TX_END_TO_A2_RX_ON_SET(x)                          (((x) << 16) & 0x00ff0000)
+#define PHY_BB_TX_TIMING_3_TX_END_TO_ADC_ON_MSB                                                       31
+#define PHY_BB_TX_TIMING_3_TX_END_TO_ADC_ON_LSB                                                       24
+#define PHY_BB_TX_TIMING_3_TX_END_TO_ADC_ON_MASK                                              0xff000000
+#define PHY_BB_TX_TIMING_3_TX_END_TO_ADC_ON_GET(x)                            (((x) & 0xff000000) >> 24)
+#define PHY_BB_TX_TIMING_3_TX_END_TO_ADC_ON_SET(x)                            (((x) << 24) & 0xff000000)
+
+/* macros for BB_addac_parallel_control */
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_ADDRESS                                                 0x0000982c
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFFSET                                                  0x0000982c
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_DACLPMODE_MSB                                               12
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_DACLPMODE_LSB                                               12
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_DACLPMODE_MASK                                      0x00001000
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_DACLPMODE_GET(x)                    (((x) & 0x00001000) >> 12)
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_DACLPMODE_SET(x)                    (((x) << 12) & 0x00001000)
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDDAC_MSB                                                  13
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDDAC_LSB                                                  13
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDDAC_MASK                                         0x00002000
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDDAC_GET(x)                       (((x) & 0x00002000) >> 13)
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDDAC_SET(x)                       (((x) << 13) & 0x00002000)
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDADC_MSB                                                  15
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDADC_LSB                                                  15
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDADC_MASK                                         0x00008000
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDADC_GET(x)                       (((x) & 0x00008000) >> 15)
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDADC_SET(x)                       (((x) << 15) & 0x00008000)
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_DACLPMODE_MSB                                                28
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_DACLPMODE_LSB                                                28
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_DACLPMODE_MASK                                       0x10000000
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_DACLPMODE_GET(x)                     (((x) & 0x10000000) >> 28)
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_DACLPMODE_SET(x)                     (((x) << 28) & 0x10000000)
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDDAC_MSB                                                   29
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDDAC_LSB                                                   29
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDDAC_MASK                                          0x20000000
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDDAC_GET(x)                        (((x) & 0x20000000) >> 29)
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDDAC_SET(x)                        (((x) << 29) & 0x20000000)
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDADC_MSB                                                   31
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDADC_LSB                                                   31
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDADC_MASK                                          0x80000000
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDADC_GET(x)                        (((x) & 0x80000000) >> 31)
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDADC_SET(x)                        (((x) << 31) & 0x80000000)
+
+/* macros for BB_xpa_timing_control */
+#define PHY_BB_XPA_TIMING_CONTROL_ADDRESS                                                     0x00009834
+#define PHY_BB_XPA_TIMING_CONTROL_OFFSET                                                      0x00009834
+#define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAA_ON_MSB                                              7
+#define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAA_ON_LSB                                              0
+#define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAA_ON_MASK                                    0x000000ff
+#define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAA_ON_GET(x)                   (((x) & 0x000000ff) >> 0)
+#define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAA_ON_SET(x)                   (((x) << 0) & 0x000000ff)
+#define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAB_ON_MSB                                             15
+#define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAB_ON_LSB                                              8
+#define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAB_ON_MASK                                    0x0000ff00
+#define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAB_ON_GET(x)                   (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAB_ON_SET(x)                   (((x) << 8) & 0x0000ff00)
+#define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAA_OFF_MSB                                              23
+#define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAA_OFF_LSB                                              16
+#define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAA_OFF_MASK                                     0x00ff0000
+#define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAA_OFF_GET(x)                   (((x) & 0x00ff0000) >> 16)
+#define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAA_OFF_SET(x)                   (((x) << 16) & 0x00ff0000)
+#define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAB_OFF_MSB                                              31
+#define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAB_OFF_LSB                                              24
+#define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAB_OFF_MASK                                     0xff000000
+#define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAB_OFF_GET(x)                   (((x) & 0xff000000) >> 24)
+#define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAB_OFF_SET(x)                   (((x) << 24) & 0xff000000)
+
+/* macros for BB_misc_pa_control */
+#define PHY_BB_MISC_PA_CONTROL_ADDRESS                                                        0x00009838
+#define PHY_BB_MISC_PA_CONTROL_OFFSET                                                         0x00009838
+#define PHY_BB_MISC_PA_CONTROL_XPAA_ACTIVE_HIGH_MSB                                                    0
+#define PHY_BB_MISC_PA_CONTROL_XPAA_ACTIVE_HIGH_LSB                                                    0
+#define PHY_BB_MISC_PA_CONTROL_XPAA_ACTIVE_HIGH_MASK                                          0x00000001
+#define PHY_BB_MISC_PA_CONTROL_XPAA_ACTIVE_HIGH_GET(x)                         (((x) & 0x00000001) >> 0)
+#define PHY_BB_MISC_PA_CONTROL_XPAA_ACTIVE_HIGH_SET(x)                         (((x) << 0) & 0x00000001)
+#define PHY_BB_MISC_PA_CONTROL_XPAB_ACTIVE_HIGH_MSB                                                    1
+#define PHY_BB_MISC_PA_CONTROL_XPAB_ACTIVE_HIGH_LSB                                                    1
+#define PHY_BB_MISC_PA_CONTROL_XPAB_ACTIVE_HIGH_MASK                                          0x00000002
+#define PHY_BB_MISC_PA_CONTROL_XPAB_ACTIVE_HIGH_GET(x)                         (((x) & 0x00000002) >> 1)
+#define PHY_BB_MISC_PA_CONTROL_XPAB_ACTIVE_HIGH_SET(x)                         (((x) << 1) & 0x00000002)
+#define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAA_MSB                                                         2
+#define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAA_LSB                                                         2
+#define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAA_MASK                                               0x00000004
+#define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAA_GET(x)                              (((x) & 0x00000004) >> 2)
+#define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAA_SET(x)                              (((x) << 2) & 0x00000004)
+#define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAB_MSB                                                         3
+#define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAB_LSB                                                         3
+#define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAB_MASK                                               0x00000008
+#define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAB_GET(x)                              (((x) & 0x00000008) >> 3)
+#define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAB_SET(x)                              (((x) << 3) & 0x00000008)
+
+/* macros for BB_tstdac_constant */
+#define PHY_BB_TSTDAC_CONSTANT_ADDRESS                                                        0x0000983c
+#define PHY_BB_TSTDAC_CONSTANT_OFFSET                                                         0x0000983c
+#define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_I_MSB                                               10
+#define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_I_LSB                                                0
+#define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_I_MASK                                      0x000007ff
+#define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_I_GET(x)                     (((x) & 0x000007ff) >> 0)
+#define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_I_SET(x)                     (((x) << 0) & 0x000007ff)
+#define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_Q_MSB                                               21
+#define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_Q_LSB                                               11
+#define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_Q_MASK                                      0x003ff800
+#define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_Q_GET(x)                    (((x) & 0x003ff800) >> 11)
+#define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_Q_SET(x)                    (((x) << 11) & 0x003ff800)
+
+/* macros for BB_find_signal_low */
+#define PHY_BB_FIND_SIGNAL_LOW_ADDRESS                                                        0x00009840
+#define PHY_BB_FIND_SIGNAL_LOW_OFFSET                                                         0x00009840
+#define PHY_BB_FIND_SIGNAL_LOW_RELSTEP_LOW_MSB                                                         5
+#define PHY_BB_FIND_SIGNAL_LOW_RELSTEP_LOW_LSB                                                         0
+#define PHY_BB_FIND_SIGNAL_LOW_RELSTEP_LOW_MASK                                               0x0000003f
+#define PHY_BB_FIND_SIGNAL_LOW_RELSTEP_LOW_GET(x)                              (((x) & 0x0000003f) >> 0)
+#define PHY_BB_FIND_SIGNAL_LOW_RELSTEP_LOW_SET(x)                              (((x) << 0) & 0x0000003f)
+#define PHY_BB_FIND_SIGNAL_LOW_FIRSTEP_LOW_MSB                                                        11
+#define PHY_BB_FIND_SIGNAL_LOW_FIRSTEP_LOW_LSB                                                         6
+#define PHY_BB_FIND_SIGNAL_LOW_FIRSTEP_LOW_MASK                                               0x00000fc0
+#define PHY_BB_FIND_SIGNAL_LOW_FIRSTEP_LOW_GET(x)                              (((x) & 0x00000fc0) >> 6)
+#define PHY_BB_FIND_SIGNAL_LOW_FIRSTEP_LOW_SET(x)                              (((x) << 6) & 0x00000fc0)
+#define PHY_BB_FIND_SIGNAL_LOW_FIRPWR_LOW_MSB                                                         19
+#define PHY_BB_FIND_SIGNAL_LOW_FIRPWR_LOW_LSB                                                         12
+#define PHY_BB_FIND_SIGNAL_LOW_FIRPWR_LOW_MASK                                                0x000ff000
+#define PHY_BB_FIND_SIGNAL_LOW_FIRPWR_LOW_GET(x)                              (((x) & 0x000ff000) >> 12)
+#define PHY_BB_FIND_SIGNAL_LOW_FIRPWR_LOW_SET(x)                              (((x) << 12) & 0x000ff000)
+#define PHY_BB_FIND_SIGNAL_LOW_YCOK_MAX_LOW_MSB                                                       23
+#define PHY_BB_FIND_SIGNAL_LOW_YCOK_MAX_LOW_LSB                                                       20
+#define PHY_BB_FIND_SIGNAL_LOW_YCOK_MAX_LOW_MASK                                              0x00f00000
+#define PHY_BB_FIND_SIGNAL_LOW_YCOK_MAX_LOW_GET(x)                            (((x) & 0x00f00000) >> 20)
+#define PHY_BB_FIND_SIGNAL_LOW_YCOK_MAX_LOW_SET(x)                            (((x) << 20) & 0x00f00000)
+#define PHY_BB_FIND_SIGNAL_LOW_LONG_SC_THRESH_MSB                                                     30
+#define PHY_BB_FIND_SIGNAL_LOW_LONG_SC_THRESH_LSB                                                     24
+#define PHY_BB_FIND_SIGNAL_LOW_LONG_SC_THRESH_MASK                                            0x7f000000
+#define PHY_BB_FIND_SIGNAL_LOW_LONG_SC_THRESH_GET(x)                          (((x) & 0x7f000000) >> 24)
+#define PHY_BB_FIND_SIGNAL_LOW_LONG_SC_THRESH_SET(x)                          (((x) << 24) & 0x7f000000)
+
+/* macros for BB_settling_time */
+#define PHY_BB_SETTLING_TIME_ADDRESS                                                          0x00009844
+#define PHY_BB_SETTLING_TIME_OFFSET                                                           0x00009844
+#define PHY_BB_SETTLING_TIME_AGC_SETTLING_MSB                                                          6
+#define PHY_BB_SETTLING_TIME_AGC_SETTLING_LSB                                                          0
+#define PHY_BB_SETTLING_TIME_AGC_SETTLING_MASK                                                0x0000007f
+#define PHY_BB_SETTLING_TIME_AGC_SETTLING_GET(x)                               (((x) & 0x0000007f) >> 0)
+#define PHY_BB_SETTLING_TIME_AGC_SETTLING_SET(x)                               (((x) << 0) & 0x0000007f)
+#define PHY_BB_SETTLING_TIME_SWITCH_SETTLING_MSB                                                      13
+#define PHY_BB_SETTLING_TIME_SWITCH_SETTLING_LSB                                                       7
+#define PHY_BB_SETTLING_TIME_SWITCH_SETTLING_MASK                                             0x00003f80
+#define PHY_BB_SETTLING_TIME_SWITCH_SETTLING_GET(x)                            (((x) & 0x00003f80) >> 7)
+#define PHY_BB_SETTLING_TIME_SWITCH_SETTLING_SET(x)                            (((x) << 7) & 0x00003f80)
+#define PHY_BB_SETTLING_TIME_ADCSAT_THRL_MSB                                                          19
+#define PHY_BB_SETTLING_TIME_ADCSAT_THRL_LSB                                                          14
+#define PHY_BB_SETTLING_TIME_ADCSAT_THRL_MASK                                                 0x000fc000
+#define PHY_BB_SETTLING_TIME_ADCSAT_THRL_GET(x)                               (((x) & 0x000fc000) >> 14)
+#define PHY_BB_SETTLING_TIME_ADCSAT_THRL_SET(x)                               (((x) << 14) & 0x000fc000)
+#define PHY_BB_SETTLING_TIME_ADCSAT_THRH_MSB                                                          25
+#define PHY_BB_SETTLING_TIME_ADCSAT_THRH_LSB                                                          20
+#define PHY_BB_SETTLING_TIME_ADCSAT_THRH_MASK                                                 0x03f00000
+#define PHY_BB_SETTLING_TIME_ADCSAT_THRH_GET(x)                               (((x) & 0x03f00000) >> 20)
+#define PHY_BB_SETTLING_TIME_ADCSAT_THRH_SET(x)                               (((x) << 20) & 0x03f00000)
+#define PHY_BB_SETTLING_TIME_LBRESET_ADVANCE_MSB                                                      29
+#define PHY_BB_SETTLING_TIME_LBRESET_ADVANCE_LSB                                                      26
+#define PHY_BB_SETTLING_TIME_LBRESET_ADVANCE_MASK                                             0x3c000000
+#define PHY_BB_SETTLING_TIME_LBRESET_ADVANCE_GET(x)                           (((x) & 0x3c000000) >> 26)
+#define PHY_BB_SETTLING_TIME_LBRESET_ADVANCE_SET(x)                           (((x) << 26) & 0x3c000000)
+
+/* macros for BB_gain_force_max_gains_b0 */
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_ADDRESS                                                0x00009848
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_OFFSET                                                 0x00009848
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN1_HYST_MARGIN_0_MSB                                      13
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN1_HYST_MARGIN_0_LSB                                       7
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN1_HYST_MARGIN_0_MASK                             0x00003f80
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN1_HYST_MARGIN_0_GET(x)            (((x) & 0x00003f80) >> 7)
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN1_HYST_MARGIN_0_SET(x)            (((x) << 7) & 0x00003f80)
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN2_HYST_MARGIN_0_MSB                                      20
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN2_HYST_MARGIN_0_LSB                                      14
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN2_HYST_MARGIN_0_MASK                             0x001fc000
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN2_HYST_MARGIN_0_GET(x)           (((x) & 0x001fc000) >> 14)
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN2_HYST_MARGIN_0_SET(x)           (((x) << 14) & 0x001fc000)
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_GAIN_FORCE_MSB                                                 21
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_GAIN_FORCE_LSB                                                 21
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_GAIN_FORCE_MASK                                        0x00200000
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_GAIN_FORCE_GET(x)                      (((x) & 0x00200000) >> 21)
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_GAIN_FORCE_SET(x)                      (((x) << 21) & 0x00200000)
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_ENABLE_SHARED_RX_MSB                                           31
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_ENABLE_SHARED_RX_LSB                                           31
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_ENABLE_SHARED_RX_MASK                                  0x80000000
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_ENABLE_SHARED_RX_GET(x)                (((x) & 0x80000000) >> 31)
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_ENABLE_SHARED_RX_SET(x)                (((x) << 31) & 0x80000000)
+
+/* macros for BB_gains_min_offsets_b0 */
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_ADDRESS                                                   0x0000984c
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSET                                                    0x0000984c
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC1_MSB                                                       6
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC1_LSB                                                       0
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC1_MASK                                             0x0000007f
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC1_GET(x)                            (((x) & 0x0000007f) >> 0)
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC1_SET(x)                            (((x) << 0) & 0x0000007f)
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC2_MSB                                                      11
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC2_LSB                                                       7
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC2_MASK                                             0x00000f80
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC2_GET(x)                            (((x) & 0x00000f80) >> 7)
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC2_SET(x)                            (((x) << 7) & 0x00000f80)
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC3_MSB                                                      16
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC3_LSB                                                      12
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC3_MASK                                             0x0001f000
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC3_GET(x)                           (((x) & 0x0001f000) >> 12)
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC3_SET(x)                           (((x) << 12) & 0x0001f000)
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_RF_GAIN_F_0_MSB                                                   24
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_RF_GAIN_F_0_LSB                                                   17
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_RF_GAIN_F_0_MASK                                          0x01fe0000
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_RF_GAIN_F_0_GET(x)                        (((x) & 0x01fe0000) >> 17)
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_RF_GAIN_F_0_SET(x)                        (((x) << 17) & 0x01fe0000)
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN1_SW_F_0_MSB                                                25
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN1_SW_F_0_LSB                                                25
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN1_SW_F_0_MASK                                       0x02000000
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN1_SW_F_0_GET(x)                     (((x) & 0x02000000) >> 25)
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN1_SW_F_0_SET(x)                     (((x) << 25) & 0x02000000)
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN2_SW_F_0_MSB                                                26
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN2_SW_F_0_LSB                                                26
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN2_SW_F_0_MASK                                       0x04000000
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN2_SW_F_0_GET(x)                     (((x) & 0x04000000) >> 26)
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN2_SW_F_0_SET(x)                     (((x) << 26) & 0x04000000)
+
+/* macros for BB_desired_sigsize */
+#define PHY_BB_DESIRED_SIGSIZE_ADDRESS                                                        0x00009850
+#define PHY_BB_DESIRED_SIGSIZE_OFFSET                                                         0x00009850
+#define PHY_BB_DESIRED_SIGSIZE_ADC_DESIRED_SIZE_MSB                                                    7
+#define PHY_BB_DESIRED_SIGSIZE_ADC_DESIRED_SIZE_LSB                                                    0
+#define PHY_BB_DESIRED_SIGSIZE_ADC_DESIRED_SIZE_MASK                                          0x000000ff
+#define PHY_BB_DESIRED_SIGSIZE_ADC_DESIRED_SIZE_GET(x)                         (((x) & 0x000000ff) >> 0)
+#define PHY_BB_DESIRED_SIGSIZE_ADC_DESIRED_SIZE_SET(x)                         (((x) << 0) & 0x000000ff)
+#define PHY_BB_DESIRED_SIGSIZE_TOTAL_DESIRED_MSB                                                      27
+#define PHY_BB_DESIRED_SIGSIZE_TOTAL_DESIRED_LSB                                                      20
+#define PHY_BB_DESIRED_SIGSIZE_TOTAL_DESIRED_MASK                                             0x0ff00000
+#define PHY_BB_DESIRED_SIGSIZE_TOTAL_DESIRED_GET(x)                           (((x) & 0x0ff00000) >> 20)
+#define PHY_BB_DESIRED_SIGSIZE_TOTAL_DESIRED_SET(x)                           (((x) << 20) & 0x0ff00000)
+#define PHY_BB_DESIRED_SIGSIZE_INIT_GC_COUNT_MAX_MSB                                                  29
+#define PHY_BB_DESIRED_SIGSIZE_INIT_GC_COUNT_MAX_LSB                                                  28
+#define PHY_BB_DESIRED_SIGSIZE_INIT_GC_COUNT_MAX_MASK                                         0x30000000
+#define PHY_BB_DESIRED_SIGSIZE_INIT_GC_COUNT_MAX_GET(x)                       (((x) & 0x30000000) >> 28)
+#define PHY_BB_DESIRED_SIGSIZE_INIT_GC_COUNT_MAX_SET(x)                       (((x) << 28) & 0x30000000)
+#define PHY_BB_DESIRED_SIGSIZE_REDUCE_INIT_GC_COUNT_MSB                                               30
+#define PHY_BB_DESIRED_SIGSIZE_REDUCE_INIT_GC_COUNT_LSB                                               30
+#define PHY_BB_DESIRED_SIGSIZE_REDUCE_INIT_GC_COUNT_MASK                                      0x40000000
+#define PHY_BB_DESIRED_SIGSIZE_REDUCE_INIT_GC_COUNT_GET(x)                    (((x) & 0x40000000) >> 30)
+#define PHY_BB_DESIRED_SIGSIZE_REDUCE_INIT_GC_COUNT_SET(x)                    (((x) << 30) & 0x40000000)
+#define PHY_BB_DESIRED_SIGSIZE_ENA_INIT_GAIN_MSB                                                      31
+#define PHY_BB_DESIRED_SIGSIZE_ENA_INIT_GAIN_LSB                                                      31
+#define PHY_BB_DESIRED_SIGSIZE_ENA_INIT_GAIN_MASK                                             0x80000000
+#define PHY_BB_DESIRED_SIGSIZE_ENA_INIT_GAIN_GET(x)                           (((x) & 0x80000000) >> 31)
+#define PHY_BB_DESIRED_SIGSIZE_ENA_INIT_GAIN_SET(x)                           (((x) << 31) & 0x80000000)
+
+/* macros for BB_timing_control_3a */
+#define PHY_BB_TIMING_CONTROL_3A_ADDRESS                                                      0x00009854
+#define PHY_BB_TIMING_CONTROL_3A_OFFSET                                                       0x00009854
+#define PHY_BB_TIMING_CONTROL_3A_STE_THR_HI_RSSI_MSB                                                   6
+#define PHY_BB_TIMING_CONTROL_3A_STE_THR_HI_RSSI_LSB                                                   0
+#define PHY_BB_TIMING_CONTROL_3A_STE_THR_HI_RSSI_MASK                                         0x0000007f
+#define PHY_BB_TIMING_CONTROL_3A_STE_THR_HI_RSSI_GET(x)                        (((x) & 0x0000007f) >> 0)
+#define PHY_BB_TIMING_CONTROL_3A_STE_THR_HI_RSSI_SET(x)                        (((x) << 0) & 0x0000007f)
+
+/* macros for BB_find_signal */
+#define PHY_BB_FIND_SIGNAL_ADDRESS                                                            0x00009858
+#define PHY_BB_FIND_SIGNAL_OFFSET                                                             0x00009858
+#define PHY_BB_FIND_SIGNAL_RELSTEP_MSB                                                                 5
+#define PHY_BB_FIND_SIGNAL_RELSTEP_LSB                                                                 0
+#define PHY_BB_FIND_SIGNAL_RELSTEP_MASK                                                       0x0000003f
+#define PHY_BB_FIND_SIGNAL_RELSTEP_GET(x)                                      (((x) & 0x0000003f) >> 0)
+#define PHY_BB_FIND_SIGNAL_RELSTEP_SET(x)                                      (((x) << 0) & 0x0000003f)
+#define PHY_BB_FIND_SIGNAL_RELPWR_MSB                                                                 11
+#define PHY_BB_FIND_SIGNAL_RELPWR_LSB                                                                  6
+#define PHY_BB_FIND_SIGNAL_RELPWR_MASK                                                        0x00000fc0
+#define PHY_BB_FIND_SIGNAL_RELPWR_GET(x)                                       (((x) & 0x00000fc0) >> 6)
+#define PHY_BB_FIND_SIGNAL_RELPWR_SET(x)                                       (((x) << 6) & 0x00000fc0)
+#define PHY_BB_FIND_SIGNAL_FIRSTEP_MSB                                                                17
+#define PHY_BB_FIND_SIGNAL_FIRSTEP_LSB                                                                12
+#define PHY_BB_FIND_SIGNAL_FIRSTEP_MASK                                                       0x0003f000
+#define PHY_BB_FIND_SIGNAL_FIRSTEP_GET(x)                                     (((x) & 0x0003f000) >> 12)
+#define PHY_BB_FIND_SIGNAL_FIRSTEP_SET(x)                                     (((x) << 12) & 0x0003f000)
+#define PHY_BB_FIND_SIGNAL_FIRPWR_MSB                                                                 25
+#define PHY_BB_FIND_SIGNAL_FIRPWR_LSB                                                                 18
+#define PHY_BB_FIND_SIGNAL_FIRPWR_MASK                                                        0x03fc0000
+#define PHY_BB_FIND_SIGNAL_FIRPWR_GET(x)                                      (((x) & 0x03fc0000) >> 18)
+#define PHY_BB_FIND_SIGNAL_FIRPWR_SET(x)                                      (((x) << 18) & 0x03fc0000)
+#define PHY_BB_FIND_SIGNAL_M1COUNT_MAX_MSB                                                            31
+#define PHY_BB_FIND_SIGNAL_M1COUNT_MAX_LSB                                                            26
+#define PHY_BB_FIND_SIGNAL_M1COUNT_MAX_MASK                                                   0xfc000000
+#define PHY_BB_FIND_SIGNAL_M1COUNT_MAX_GET(x)                                 (((x) & 0xfc000000) >> 26)
+#define PHY_BB_FIND_SIGNAL_M1COUNT_MAX_SET(x)                                 (((x) << 26) & 0xfc000000)
+
+/* macros for BB_agc */
+#define PHY_BB_AGC_ADDRESS                                                                    0x0000985c
+#define PHY_BB_AGC_OFFSET                                                                     0x0000985c
+#define PHY_BB_AGC_COARSEPWR_CONST_MSB                                                                 6
+#define PHY_BB_AGC_COARSEPWR_CONST_LSB                                                                 0
+#define PHY_BB_AGC_COARSEPWR_CONST_MASK                                                       0x0000007f
+#define PHY_BB_AGC_COARSEPWR_CONST_GET(x)                                      (((x) & 0x0000007f) >> 0)
+#define PHY_BB_AGC_COARSEPWR_CONST_SET(x)                                      (((x) << 0) & 0x0000007f)
+#define PHY_BB_AGC_COARSE_LOW_MSB                                                                     14
+#define PHY_BB_AGC_COARSE_LOW_LSB                                                                      7
+#define PHY_BB_AGC_COARSE_LOW_MASK                                                            0x00007f80
+#define PHY_BB_AGC_COARSE_LOW_GET(x)                                           (((x) & 0x00007f80) >> 7)
+#define PHY_BB_AGC_COARSE_LOW_SET(x)                                           (((x) << 7) & 0x00007f80)
+#define PHY_BB_AGC_COARSE_HIGH_MSB                                                                    21
+#define PHY_BB_AGC_COARSE_HIGH_LSB                                                                    15
+#define PHY_BB_AGC_COARSE_HIGH_MASK                                                           0x003f8000
+#define PHY_BB_AGC_COARSE_HIGH_GET(x)                                         (((x) & 0x003f8000) >> 15)
+#define PHY_BB_AGC_COARSE_HIGH_SET(x)                                         (((x) << 15) & 0x003f8000)
+#define PHY_BB_AGC_QUICK_DROP_MSB                                                                     29
+#define PHY_BB_AGC_QUICK_DROP_LSB                                                                     22
+#define PHY_BB_AGC_QUICK_DROP_MASK                                                            0x3fc00000
+#define PHY_BB_AGC_QUICK_DROP_GET(x)                                          (((x) & 0x3fc00000) >> 22)
+#define PHY_BB_AGC_QUICK_DROP_SET(x)                                          (((x) << 22) & 0x3fc00000)
+#define PHY_BB_AGC_RSSI_OUT_SELECT_MSB                                                                31
+#define PHY_BB_AGC_RSSI_OUT_SELECT_LSB                                                                30
+#define PHY_BB_AGC_RSSI_OUT_SELECT_MASK                                                       0xc0000000
+#define PHY_BB_AGC_RSSI_OUT_SELECT_GET(x)                                     (((x) & 0xc0000000) >> 30)
+#define PHY_BB_AGC_RSSI_OUT_SELECT_SET(x)                                     (((x) << 30) & 0xc0000000)
+
+/* macros for BB_agc_control */
+#define PHY_BB_AGC_CONTROL_ADDRESS                                                            0x00009860
+#define PHY_BB_AGC_CONTROL_OFFSET                                                             0x00009860
+#define PHY_BB_AGC_CONTROL_DO_CALIBRATE_MSB                                                            0
+#define PHY_BB_AGC_CONTROL_DO_CALIBRATE_LSB                                                            0
+#define PHY_BB_AGC_CONTROL_DO_CALIBRATE_MASK                                                  0x00000001
+#define PHY_BB_AGC_CONTROL_DO_CALIBRATE_GET(x)                                 (((x) & 0x00000001) >> 0)
+#define PHY_BB_AGC_CONTROL_DO_CALIBRATE_SET(x)                                 (((x) << 0) & 0x00000001)
+#define PHY_BB_AGC_CONTROL_DO_NOISEFLOOR_MSB                                                           1
+#define PHY_BB_AGC_CONTROL_DO_NOISEFLOOR_LSB                                                           1
+#define PHY_BB_AGC_CONTROL_DO_NOISEFLOOR_MASK                                                 0x00000002
+#define PHY_BB_AGC_CONTROL_DO_NOISEFLOOR_GET(x)                                (((x) & 0x00000002) >> 1)
+#define PHY_BB_AGC_CONTROL_DO_NOISEFLOOR_SET(x)                                (((x) << 1) & 0x00000002)
+#define PHY_BB_AGC_CONTROL_MIN_NUM_GAIN_CHANGE_MSB                                                     5
+#define PHY_BB_AGC_CONTROL_MIN_NUM_GAIN_CHANGE_LSB                                                     3
+#define PHY_BB_AGC_CONTROL_MIN_NUM_GAIN_CHANGE_MASK                                           0x00000038
+#define PHY_BB_AGC_CONTROL_MIN_NUM_GAIN_CHANGE_GET(x)                          (((x) & 0x00000038) >> 3)
+#define PHY_BB_AGC_CONTROL_MIN_NUM_GAIN_CHANGE_SET(x)                          (((x) << 3) & 0x00000038)
+#define PHY_BB_AGC_CONTROL_YCOK_MAX_MSB                                                                9
+#define PHY_BB_AGC_CONTROL_YCOK_MAX_LSB                                                                6
+#define PHY_BB_AGC_CONTROL_YCOK_MAX_MASK                                                      0x000003c0
+#define PHY_BB_AGC_CONTROL_YCOK_MAX_GET(x)                                     (((x) & 0x000003c0) >> 6)
+#define PHY_BB_AGC_CONTROL_YCOK_MAX_SET(x)                                     (((x) << 6) & 0x000003c0)
+#define PHY_BB_AGC_CONTROL_LEAKY_BUCKET_ENABLE_MSB                                                    10
+#define PHY_BB_AGC_CONTROL_LEAKY_BUCKET_ENABLE_LSB                                                    10
+#define PHY_BB_AGC_CONTROL_LEAKY_BUCKET_ENABLE_MASK                                           0x00000400
+#define PHY_BB_AGC_CONTROL_LEAKY_BUCKET_ENABLE_GET(x)                         (((x) & 0x00000400) >> 10)
+#define PHY_BB_AGC_CONTROL_LEAKY_BUCKET_ENABLE_SET(x)                         (((x) << 10) & 0x00000400)
+#define PHY_BB_AGC_CONTROL_CAL_ENABLE_MSB                                                             11
+#define PHY_BB_AGC_CONTROL_CAL_ENABLE_LSB                                                             11
+#define PHY_BB_AGC_CONTROL_CAL_ENABLE_MASK                                                    0x00000800
+#define PHY_BB_AGC_CONTROL_CAL_ENABLE_GET(x)                                  (((x) & 0x00000800) >> 11)
+#define PHY_BB_AGC_CONTROL_CAL_ENABLE_SET(x)                                  (((x) << 11) & 0x00000800)
+#define PHY_BB_AGC_CONTROL_USE_TABLE_SEED_MSB                                                         12
+#define PHY_BB_AGC_CONTROL_USE_TABLE_SEED_LSB                                                         12
+#define PHY_BB_AGC_CONTROL_USE_TABLE_SEED_MASK                                                0x00001000
+#define PHY_BB_AGC_CONTROL_USE_TABLE_SEED_GET(x)                              (((x) & 0x00001000) >> 12)
+#define PHY_BB_AGC_CONTROL_USE_TABLE_SEED_SET(x)                              (((x) << 12) & 0x00001000)
+#define PHY_BB_AGC_CONTROL_AGC_UPDATE_TABLE_SEED_MSB                                                  13
+#define PHY_BB_AGC_CONTROL_AGC_UPDATE_TABLE_SEED_LSB                                                  13
+#define PHY_BB_AGC_CONTROL_AGC_UPDATE_TABLE_SEED_MASK                                         0x00002000
+#define PHY_BB_AGC_CONTROL_AGC_UPDATE_TABLE_SEED_GET(x)                       (((x) & 0x00002000) >> 13)
+#define PHY_BB_AGC_CONTROL_AGC_UPDATE_TABLE_SEED_SET(x)                       (((x) << 13) & 0x00002000)
+#define PHY_BB_AGC_CONTROL_ENABLE_NOISEFLOOR_MSB                                                      15
+#define PHY_BB_AGC_CONTROL_ENABLE_NOISEFLOOR_LSB                                                      15
+#define PHY_BB_AGC_CONTROL_ENABLE_NOISEFLOOR_MASK                                             0x00008000
+#define PHY_BB_AGC_CONTROL_ENABLE_NOISEFLOOR_GET(x)                           (((x) & 0x00008000) >> 15)
+#define PHY_BB_AGC_CONTROL_ENABLE_NOISEFLOOR_SET(x)                           (((x) << 15) & 0x00008000)
+#define PHY_BB_AGC_CONTROL_ENABLE_FLTR_CAL_MSB                                                        16
+#define PHY_BB_AGC_CONTROL_ENABLE_FLTR_CAL_LSB                                                        16
+#define PHY_BB_AGC_CONTROL_ENABLE_FLTR_CAL_MASK                                               0x00010000
+#define PHY_BB_AGC_CONTROL_ENABLE_FLTR_CAL_GET(x)                             (((x) & 0x00010000) >> 16)
+#define PHY_BB_AGC_CONTROL_ENABLE_FLTR_CAL_SET(x)                             (((x) << 16) & 0x00010000)
+#define PHY_BB_AGC_CONTROL_NO_UPDATE_NOISEFLOOR_MSB                                                   17
+#define PHY_BB_AGC_CONTROL_NO_UPDATE_NOISEFLOOR_LSB                                                   17
+#define PHY_BB_AGC_CONTROL_NO_UPDATE_NOISEFLOOR_MASK                                          0x00020000
+#define PHY_BB_AGC_CONTROL_NO_UPDATE_NOISEFLOOR_GET(x)                        (((x) & 0x00020000) >> 17)
+#define PHY_BB_AGC_CONTROL_NO_UPDATE_NOISEFLOOR_SET(x)                        (((x) << 17) & 0x00020000)
+#define PHY_BB_AGC_CONTROL_EXTEND_NF_PWR_MEAS_MSB                                                     18
+#define PHY_BB_AGC_CONTROL_EXTEND_NF_PWR_MEAS_LSB                                                     18
+#define PHY_BB_AGC_CONTROL_EXTEND_NF_PWR_MEAS_MASK                                            0x00040000
+#define PHY_BB_AGC_CONTROL_EXTEND_NF_PWR_MEAS_GET(x)                          (((x) & 0x00040000) >> 18)
+#define PHY_BB_AGC_CONTROL_EXTEND_NF_PWR_MEAS_SET(x)                          (((x) << 18) & 0x00040000)
+#define PHY_BB_AGC_CONTROL_CLC_SUCCESS_MSB                                                            19
+#define PHY_BB_AGC_CONTROL_CLC_SUCCESS_LSB                                                            19
+#define PHY_BB_AGC_CONTROL_CLC_SUCCESS_MASK                                                   0x00080000
+#define PHY_BB_AGC_CONTROL_CLC_SUCCESS_GET(x)                                 (((x) & 0x00080000) >> 19)
+#define PHY_BB_AGC_CONTROL_ENABLE_PKDET_CAL_MSB                                                       20
+#define PHY_BB_AGC_CONTROL_ENABLE_PKDET_CAL_LSB                                                       20
+#define PHY_BB_AGC_CONTROL_ENABLE_PKDET_CAL_MASK                                              0x00100000
+#define PHY_BB_AGC_CONTROL_ENABLE_PKDET_CAL_GET(x)                            (((x) & 0x00100000) >> 20)
+#define PHY_BB_AGC_CONTROL_ENABLE_PKDET_CAL_SET(x)                            (((x) << 20) & 0x00100000)
+
+/* macros for BB_cca_b0 */
+#define PHY_BB_CCA_B0_ADDRESS                                                                 0x00009864
+#define PHY_BB_CCA_B0_OFFSET                                                                  0x00009864
+#define PHY_BB_CCA_B0_CF_MAXCCAPWR_0_MSB                                                               8
+#define PHY_BB_CCA_B0_CF_MAXCCAPWR_0_LSB                                                               0
+#define PHY_BB_CCA_B0_CF_MAXCCAPWR_0_MASK                                                     0x000001ff
+#define PHY_BB_CCA_B0_CF_MAXCCAPWR_0_GET(x)                                    (((x) & 0x000001ff) >> 0)
+#define PHY_BB_CCA_B0_CF_MAXCCAPWR_0_SET(x)                                    (((x) << 0) & 0x000001ff)
+#define PHY_BB_CCA_B0_CF_CCA_COUNT_MAXC_MSB                                                           11
+#define PHY_BB_CCA_B0_CF_CCA_COUNT_MAXC_LSB                                                            9
+#define PHY_BB_CCA_B0_CF_CCA_COUNT_MAXC_MASK                                                  0x00000e00
+#define PHY_BB_CCA_B0_CF_CCA_COUNT_MAXC_GET(x)                                 (((x) & 0x00000e00) >> 9)
+#define PHY_BB_CCA_B0_CF_CCA_COUNT_MAXC_SET(x)                                 (((x) << 9) & 0x00000e00)
+#define PHY_BB_CCA_B0_CF_THRESH62_MSB                                                                 19
+#define PHY_BB_CCA_B0_CF_THRESH62_LSB                                                                 12
+#define PHY_BB_CCA_B0_CF_THRESH62_MASK                                                        0x000ff000
+#define PHY_BB_CCA_B0_CF_THRESH62_GET(x)                                      (((x) & 0x000ff000) >> 12)
+#define PHY_BB_CCA_B0_CF_THRESH62_SET(x)                                      (((x) << 12) & 0x000ff000)
+#define PHY_BB_CCA_B0_MINCCAPWR_0_MSB                                                                 28
+#define PHY_BB_CCA_B0_MINCCAPWR_0_LSB                                                                 20
+#define PHY_BB_CCA_B0_MINCCAPWR_0_MASK                                                        0x1ff00000
+#define PHY_BB_CCA_B0_MINCCAPWR_0_GET(x)                                      (((x) & 0x1ff00000) >> 20)
+
+/* macros for BB_sfcorr */
+#define PHY_BB_SFCORR_ADDRESS                                                                 0x00009868
+#define PHY_BB_SFCORR_OFFSET                                                                  0x00009868
+#define PHY_BB_SFCORR_M2COUNT_THR_MSB                                                                  4
+#define PHY_BB_SFCORR_M2COUNT_THR_LSB                                                                  0
+#define PHY_BB_SFCORR_M2COUNT_THR_MASK                                                        0x0000001f
+#define PHY_BB_SFCORR_M2COUNT_THR_GET(x)                                       (((x) & 0x0000001f) >> 0)
+#define PHY_BB_SFCORR_M2COUNT_THR_SET(x)                                       (((x) << 0) & 0x0000001f)
+#define PHY_BB_SFCORR_ADCSAT_THRESH_MSB                                                               10
+#define PHY_BB_SFCORR_ADCSAT_THRESH_LSB                                                                5
+#define PHY_BB_SFCORR_ADCSAT_THRESH_MASK                                                      0x000007e0
+#define PHY_BB_SFCORR_ADCSAT_THRESH_GET(x)                                     (((x) & 0x000007e0) >> 5)
+#define PHY_BB_SFCORR_ADCSAT_THRESH_SET(x)                                     (((x) << 5) & 0x000007e0)
+#define PHY_BB_SFCORR_ADCSAT_ICOUNT_MSB                                                               16
+#define PHY_BB_SFCORR_ADCSAT_ICOUNT_LSB                                                               11
+#define PHY_BB_SFCORR_ADCSAT_ICOUNT_MASK                                                      0x0001f800
+#define PHY_BB_SFCORR_ADCSAT_ICOUNT_GET(x)                                    (((x) & 0x0001f800) >> 11)
+#define PHY_BB_SFCORR_ADCSAT_ICOUNT_SET(x)                                    (((x) << 11) & 0x0001f800)
+#define PHY_BB_SFCORR_M1_THRES_MSB                                                                    23
+#define PHY_BB_SFCORR_M1_THRES_LSB                                                                    17
+#define PHY_BB_SFCORR_M1_THRES_MASK                                                           0x00fe0000
+#define PHY_BB_SFCORR_M1_THRES_GET(x)                                         (((x) & 0x00fe0000) >> 17)
+#define PHY_BB_SFCORR_M1_THRES_SET(x)                                         (((x) << 17) & 0x00fe0000)
+#define PHY_BB_SFCORR_M2_THRES_MSB                                                                    30
+#define PHY_BB_SFCORR_M2_THRES_LSB                                                                    24
+#define PHY_BB_SFCORR_M2_THRES_MASK                                                           0x7f000000
+#define PHY_BB_SFCORR_M2_THRES_GET(x)                                         (((x) & 0x7f000000) >> 24)
+#define PHY_BB_SFCORR_M2_THRES_SET(x)                                         (((x) << 24) & 0x7f000000)
+
+/* macros for BB_self_corr_low */
+#define PHY_BB_SELF_CORR_LOW_ADDRESS                                                          0x0000986c
+#define PHY_BB_SELF_CORR_LOW_OFFSET                                                           0x0000986c
+#define PHY_BB_SELF_CORR_LOW_USE_SELF_CORR_LOW_MSB                                                     0
+#define PHY_BB_SELF_CORR_LOW_USE_SELF_CORR_LOW_LSB                                                     0
+#define PHY_BB_SELF_CORR_LOW_USE_SELF_CORR_LOW_MASK                                           0x00000001
+#define PHY_BB_SELF_CORR_LOW_USE_SELF_CORR_LOW_GET(x)                          (((x) & 0x00000001) >> 0)
+#define PHY_BB_SELF_CORR_LOW_USE_SELF_CORR_LOW_SET(x)                          (((x) << 0) & 0x00000001)
+#define PHY_BB_SELF_CORR_LOW_M1COUNT_MAX_LOW_MSB                                                       7
+#define PHY_BB_SELF_CORR_LOW_M1COUNT_MAX_LOW_LSB                                                       1
+#define PHY_BB_SELF_CORR_LOW_M1COUNT_MAX_LOW_MASK                                             0x000000fe
+#define PHY_BB_SELF_CORR_LOW_M1COUNT_MAX_LOW_GET(x)                            (((x) & 0x000000fe) >> 1)
+#define PHY_BB_SELF_CORR_LOW_M1COUNT_MAX_LOW_SET(x)                            (((x) << 1) & 0x000000fe)
+#define PHY_BB_SELF_CORR_LOW_M2COUNT_THR_LOW_MSB                                                      13
+#define PHY_BB_SELF_CORR_LOW_M2COUNT_THR_LOW_LSB                                                       8
+#define PHY_BB_SELF_CORR_LOW_M2COUNT_THR_LOW_MASK                                             0x00003f00
+#define PHY_BB_SELF_CORR_LOW_M2COUNT_THR_LOW_GET(x)                            (((x) & 0x00003f00) >> 8)
+#define PHY_BB_SELF_CORR_LOW_M2COUNT_THR_LOW_SET(x)                            (((x) << 8) & 0x00003f00)
+#define PHY_BB_SELF_CORR_LOW_M1_THRESH_LOW_MSB                                                        20
+#define PHY_BB_SELF_CORR_LOW_M1_THRESH_LOW_LSB                                                        14
+#define PHY_BB_SELF_CORR_LOW_M1_THRESH_LOW_MASK                                               0x001fc000
+#define PHY_BB_SELF_CORR_LOW_M1_THRESH_LOW_GET(x)                             (((x) & 0x001fc000) >> 14)
+#define PHY_BB_SELF_CORR_LOW_M1_THRESH_LOW_SET(x)                             (((x) << 14) & 0x001fc000)
+#define PHY_BB_SELF_CORR_LOW_M2_THRESH_LOW_MSB                                                        27
+#define PHY_BB_SELF_CORR_LOW_M2_THRESH_LOW_LSB                                                        21
+#define PHY_BB_SELF_CORR_LOW_M2_THRESH_LOW_MASK                                               0x0fe00000
+#define PHY_BB_SELF_CORR_LOW_M2_THRESH_LOW_GET(x)                             (((x) & 0x0fe00000) >> 21)
+#define PHY_BB_SELF_CORR_LOW_M2_THRESH_LOW_SET(x)                             (((x) << 21) & 0x0fe00000)
+
+/* macros for BB_synth_control */
+#define PHY_BB_SYNTH_CONTROL_ADDRESS                                                          0x00009874
+#define PHY_BB_SYNTH_CONTROL_OFFSET                                                           0x00009874
+#define PHY_BB_SYNTH_CONTROL_RFCHANFRAC_MSB                                                           16
+#define PHY_BB_SYNTH_CONTROL_RFCHANFRAC_LSB                                                            0
+#define PHY_BB_SYNTH_CONTROL_RFCHANFRAC_MASK                                                  0x0001ffff
+#define PHY_BB_SYNTH_CONTROL_RFCHANFRAC_GET(x)                                 (((x) & 0x0001ffff) >> 0)
+#define PHY_BB_SYNTH_CONTROL_RFCHANFRAC_SET(x)                                 (((x) << 0) & 0x0001ffff)
+#define PHY_BB_SYNTH_CONTROL_RFCHANNEL_MSB                                                            25
+#define PHY_BB_SYNTH_CONTROL_RFCHANNEL_LSB                                                            17
+#define PHY_BB_SYNTH_CONTROL_RFCHANNEL_MASK                                                   0x03fe0000
+#define PHY_BB_SYNTH_CONTROL_RFCHANNEL_GET(x)                                 (((x) & 0x03fe0000) >> 17)
+#define PHY_BB_SYNTH_CONTROL_RFCHANNEL_SET(x)                                 (((x) << 17) & 0x03fe0000)
+#define PHY_BB_SYNTH_CONTROL_RFAMODEREFSEL_MSB                                                        27
+#define PHY_BB_SYNTH_CONTROL_RFAMODEREFSEL_LSB                                                        26
+#define PHY_BB_SYNTH_CONTROL_RFAMODEREFSEL_MASK                                               0x0c000000
+#define PHY_BB_SYNTH_CONTROL_RFAMODEREFSEL_GET(x)                             (((x) & 0x0c000000) >> 26)
+#define PHY_BB_SYNTH_CONTROL_RFAMODEREFSEL_SET(x)                             (((x) << 26) & 0x0c000000)
+#define PHY_BB_SYNTH_CONTROL_RFFRACMODE_MSB                                                           28
+#define PHY_BB_SYNTH_CONTROL_RFFRACMODE_LSB                                                           28
+#define PHY_BB_SYNTH_CONTROL_RFFRACMODE_MASK                                                  0x10000000
+#define PHY_BB_SYNTH_CONTROL_RFFRACMODE_GET(x)                                (((x) & 0x10000000) >> 28)
+#define PHY_BB_SYNTH_CONTROL_RFFRACMODE_SET(x)                                (((x) << 28) & 0x10000000)
+#define PHY_BB_SYNTH_CONTROL_RFBMODE_MSB                                                              29
+#define PHY_BB_SYNTH_CONTROL_RFBMODE_LSB                                                              29
+#define PHY_BB_SYNTH_CONTROL_RFBMODE_MASK                                                     0x20000000
+#define PHY_BB_SYNTH_CONTROL_RFBMODE_GET(x)                                   (((x) & 0x20000000) >> 29)
+#define PHY_BB_SYNTH_CONTROL_RFBMODE_SET(x)                                   (((x) << 29) & 0x20000000)
+#define PHY_BB_SYNTH_CONTROL_RFSYNTH_CTRL_SSHIFT_MSB                                                  30
+#define PHY_BB_SYNTH_CONTROL_RFSYNTH_CTRL_SSHIFT_LSB                                                  30
+#define PHY_BB_SYNTH_CONTROL_RFSYNTH_CTRL_SSHIFT_MASK                                         0x40000000
+#define PHY_BB_SYNTH_CONTROL_RFSYNTH_CTRL_SSHIFT_GET(x)                       (((x) & 0x40000000) >> 30)
+#define PHY_BB_SYNTH_CONTROL_RFSYNTH_CTRL_SSHIFT_SET(x)                       (((x) << 30) & 0x40000000)
+
+/* macros for BB_addac_clk_select */
+#define PHY_BB_ADDAC_CLK_SELECT_ADDRESS                                                       0x00009878
+#define PHY_BB_ADDAC_CLK_SELECT_OFFSET                                                        0x00009878
+#define PHY_BB_ADDAC_CLK_SELECT_BB_DAC_CLK_SELECT_MSB                                                  3
+#define PHY_BB_ADDAC_CLK_SELECT_BB_DAC_CLK_SELECT_LSB                                                  2
+#define PHY_BB_ADDAC_CLK_SELECT_BB_DAC_CLK_SELECT_MASK                                        0x0000000c
+#define PHY_BB_ADDAC_CLK_SELECT_BB_DAC_CLK_SELECT_GET(x)                       (((x) & 0x0000000c) >> 2)
+#define PHY_BB_ADDAC_CLK_SELECT_BB_DAC_CLK_SELECT_SET(x)                       (((x) << 2) & 0x0000000c)
+#define PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_MSB                                                  5
+#define PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_LSB                                                  4
+#define PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_MASK                                        0x00000030
+#define PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_GET(x)                       (((x) & 0x00000030) >> 4)
+#define PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_SET(x)                       (((x) << 4) & 0x00000030)
+
+/* macros for BB_pll_cntl */
+#define PHY_BB_PLL_CNTL_ADDRESS                                                               0x0000987c
+#define PHY_BB_PLL_CNTL_OFFSET                                                                0x0000987c
+#define PHY_BB_PLL_CNTL_BB_PLL_DIV_MSB                                                                 9
+#define PHY_BB_PLL_CNTL_BB_PLL_DIV_LSB                                                                 0
+#define PHY_BB_PLL_CNTL_BB_PLL_DIV_MASK                                                       0x000003ff
+#define PHY_BB_PLL_CNTL_BB_PLL_DIV_GET(x)                                      (((x) & 0x000003ff) >> 0)
+#define PHY_BB_PLL_CNTL_BB_PLL_DIV_SET(x)                                      (((x) << 0) & 0x000003ff)
+#define PHY_BB_PLL_CNTL_BB_PLL_REFDIV_MSB                                                             13
+#define PHY_BB_PLL_CNTL_BB_PLL_REFDIV_LSB                                                             10
+#define PHY_BB_PLL_CNTL_BB_PLL_REFDIV_MASK                                                    0x00003c00
+#define PHY_BB_PLL_CNTL_BB_PLL_REFDIV_GET(x)                                  (((x) & 0x00003c00) >> 10)
+#define PHY_BB_PLL_CNTL_BB_PLL_REFDIV_SET(x)                                  (((x) << 10) & 0x00003c00)
+#define PHY_BB_PLL_CNTL_BB_PLL_CLK_SEL_MSB                                                            15
+#define PHY_BB_PLL_CNTL_BB_PLL_CLK_SEL_LSB                                                            14
+#define PHY_BB_PLL_CNTL_BB_PLL_CLK_SEL_MASK                                                   0x0000c000
+#define PHY_BB_PLL_CNTL_BB_PLL_CLK_SEL_GET(x)                                 (((x) & 0x0000c000) >> 14)
+#define PHY_BB_PLL_CNTL_BB_PLL_CLK_SEL_SET(x)                                 (((x) << 14) & 0x0000c000)
+#define PHY_BB_PLL_CNTL_BB_PLLBYPASS_MSB                                                              16
+#define PHY_BB_PLL_CNTL_BB_PLLBYPASS_LSB                                                              16
+#define PHY_BB_PLL_CNTL_BB_PLLBYPASS_MASK                                                     0x00010000
+#define PHY_BB_PLL_CNTL_BB_PLLBYPASS_GET(x)                                   (((x) & 0x00010000) >> 16)
+#define PHY_BB_PLL_CNTL_BB_PLLBYPASS_SET(x)                                   (((x) << 16) & 0x00010000)
+#define PHY_BB_PLL_CNTL_BB_PLL_SETTLE_TIME_MSB                                                        27
+#define PHY_BB_PLL_CNTL_BB_PLL_SETTLE_TIME_LSB                                                        17
+#define PHY_BB_PLL_CNTL_BB_PLL_SETTLE_TIME_MASK                                               0x0ffe0000
+#define PHY_BB_PLL_CNTL_BB_PLL_SETTLE_TIME_GET(x)                             (((x) & 0x0ffe0000) >> 17)
+#define PHY_BB_PLL_CNTL_BB_PLL_SETTLE_TIME_SET(x)                             (((x) << 17) & 0x0ffe0000)
+
+/* macros for BB_vit_spur_mask_A */
+#define PHY_BB_VIT_SPUR_MASK_A_ADDRESS                                                        0x00009900
+#define PHY_BB_VIT_SPUR_MASK_A_OFFSET                                                         0x00009900
+#define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_A_MSB                                                      9
+#define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_A_LSB                                                      0
+#define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_A_MASK                                            0x000003ff
+#define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_A_GET(x)                           (((x) & 0x000003ff) >> 0)
+#define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_A_SET(x)                           (((x) << 0) & 0x000003ff)
+#define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_MSB                                                 16
+#define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_LSB                                                 10
+#define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_MASK                                        0x0001fc00
+#define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_GET(x)                      (((x) & 0x0001fc00) >> 10)
+#define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_SET(x)                      (((x) << 10) & 0x0001fc00)
+
+/* macros for BB_vit_spur_mask_B */
+#define PHY_BB_VIT_SPUR_MASK_B_ADDRESS                                                        0x00009904
+#define PHY_BB_VIT_SPUR_MASK_B_OFFSET                                                         0x00009904
+#define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_B_MSB                                                      9
+#define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_B_LSB                                                      0
+#define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_B_MASK                                            0x000003ff
+#define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_B_GET(x)                           (((x) & 0x000003ff) >> 0)
+#define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_B_SET(x)                           (((x) << 0) & 0x000003ff)
+#define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_IDX_B_MSB                                                 16
+#define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_IDX_B_LSB                                                 10
+#define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_IDX_B_MASK                                        0x0001fc00
+#define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_IDX_B_GET(x)                      (((x) & 0x0001fc00) >> 10)
+#define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_IDX_B_SET(x)                      (((x) << 10) & 0x0001fc00)
+
+/* macros for BB_pilot_spur_mask */
+#define PHY_BB_PILOT_SPUR_MASK_ADDRESS                                                        0x00009908
+#define PHY_BB_PILOT_SPUR_MASK_OFFSET                                                         0x00009908
+#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_A_MSB                                                     4
+#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_A_LSB                                                     0
+#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_A_MASK                                           0x0000001f
+#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_A_GET(x)                          (((x) & 0x0000001f) >> 0)
+#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_A_SET(x)                          (((x) << 0) & 0x0000001f)
+#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_MSB                                                11
+#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_LSB                                                 5
+#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_MASK                                       0x00000fe0
+#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_GET(x)                      (((x) & 0x00000fe0) >> 5)
+#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_SET(x)                      (((x) << 5) & 0x00000fe0)
+#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_B_MSB                                                    16
+#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_B_LSB                                                    12
+#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_B_MASK                                           0x0001f000
+#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_B_GET(x)                         (((x) & 0x0001f000) >> 12)
+#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_B_SET(x)                         (((x) << 12) & 0x0001f000)
+#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B_MSB                                                23
+#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B_LSB                                                17
+#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B_MASK                                       0x00fe0000
+#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B_GET(x)                     (((x) & 0x00fe0000) >> 17)
+#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B_SET(x)                     (((x) << 17) & 0x00fe0000)
+
+/* macros for BB_chan_spur_mask */
+#define PHY_BB_CHAN_SPUR_MASK_ADDRESS                                                         0x0000990c
+#define PHY_BB_CHAN_SPUR_MASK_OFFSET                                                          0x0000990c
+#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_A_MSB                                                       4
+#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_A_LSB                                                       0
+#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_A_MASK                                             0x0000001f
+#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_A_GET(x)                            (((x) & 0x0000001f) >> 0)
+#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_A_SET(x)                            (((x) << 0) & 0x0000001f)
+#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_MSB                                                  11
+#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_LSB                                                   5
+#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_MASK                                         0x00000fe0
+#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_GET(x)                        (((x) & 0x00000fe0) >> 5)
+#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_SET(x)                        (((x) << 5) & 0x00000fe0)
+#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_B_MSB                                                      16
+#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_B_LSB                                                      12
+#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_B_MASK                                             0x0001f000
+#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_B_GET(x)                           (((x) & 0x0001f000) >> 12)
+#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_B_SET(x)                           (((x) << 12) & 0x0001f000)
+#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B_MSB                                                  23
+#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B_LSB                                                  17
+#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B_MASK                                         0x00fe0000
+#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B_GET(x)                       (((x) & 0x00fe0000) >> 17)
+#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B_SET(x)                       (((x) << 17) & 0x00fe0000)
+
+/* macros for BB_spectral_scan */
+#define PHY_BB_SPECTRAL_SCAN_ADDRESS                                                          0x00009910
+#define PHY_BB_SPECTRAL_SCAN_OFFSET                                                           0x00009910
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ENA_MSB                                                     0
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ENA_LSB                                                     0
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ENA_MASK                                           0x00000001
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ENA_GET(x)                          (((x) & 0x00000001) >> 0)
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ENA_SET(x)                          (((x) << 0) & 0x00000001)
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ACTIVE_MSB                                                  1
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ACTIVE_LSB                                                  1
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ACTIVE_MASK                                        0x00000002
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ACTIVE_GET(x)                       (((x) & 0x00000002) >> 1)
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ACTIVE_SET(x)                       (((x) << 1) & 0x00000002)
+#define PHY_BB_SPECTRAL_SCAN_DISABLE_RADAR_TCTL_RST_MSB                                                2
+#define PHY_BB_SPECTRAL_SCAN_DISABLE_RADAR_TCTL_RST_LSB                                                2
+#define PHY_BB_SPECTRAL_SCAN_DISABLE_RADAR_TCTL_RST_MASK                                      0x00000004
+#define PHY_BB_SPECTRAL_SCAN_DISABLE_RADAR_TCTL_RST_GET(x)                     (((x) & 0x00000004) >> 2)
+#define PHY_BB_SPECTRAL_SCAN_DISABLE_RADAR_TCTL_RST_SET(x)                     (((x) << 2) & 0x00000004)
+#define PHY_BB_SPECTRAL_SCAN_DISABLE_PULSE_COARSE_LOW_MSB                                              3
+#define PHY_BB_SPECTRAL_SCAN_DISABLE_PULSE_COARSE_LOW_LSB                                              3
+#define PHY_BB_SPECTRAL_SCAN_DISABLE_PULSE_COARSE_LOW_MASK                                    0x00000008
+#define PHY_BB_SPECTRAL_SCAN_DISABLE_PULSE_COARSE_LOW_GET(x)                   (((x) & 0x00000008) >> 3)
+#define PHY_BB_SPECTRAL_SCAN_DISABLE_PULSE_COARSE_LOW_SET(x)                   (((x) << 3) & 0x00000008)
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_FFT_PERIOD_MSB                                              7
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_FFT_PERIOD_LSB                                              4
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_FFT_PERIOD_MASK                                    0x000000f0
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_FFT_PERIOD_GET(x)                   (((x) & 0x000000f0) >> 4)
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_FFT_PERIOD_SET(x)                   (((x) << 4) & 0x000000f0)
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PERIOD_MSB                                                 15
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PERIOD_LSB                                                  8
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PERIOD_MASK                                        0x0000ff00
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PERIOD_GET(x)                       (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PERIOD_SET(x)                       (((x) << 8) & 0x0000ff00)
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_COUNT_MSB                                                  27
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_COUNT_LSB                                                  16
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_COUNT_MASK                                         0x0fff0000
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_COUNT_GET(x)                       (((x) & 0x0fff0000) >> 16)
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_COUNT_SET(x)                       (((x) << 16) & 0x0fff0000)
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_SHORT_RPT_MSB                                              28
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_SHORT_RPT_LSB                                              28
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_SHORT_RPT_MASK                                     0x10000000
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_SHORT_RPT_GET(x)                   (((x) & 0x10000000) >> 28)
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_SHORT_RPT_SET(x)                   (((x) << 28) & 0x10000000)
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PRIORITY_MSB                                               29
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PRIORITY_LSB                                               29
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PRIORITY_MASK                                      0x20000000
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PRIORITY_GET(x)                    (((x) & 0x20000000) >> 29)
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PRIORITY_SET(x)                    (((x) << 29) & 0x20000000)
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_USE_ERR5_MSB                                               30
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_USE_ERR5_LSB                                               30
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_USE_ERR5_MASK                                      0x40000000
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_USE_ERR5_GET(x)                    (((x) & 0x40000000) >> 30)
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_USE_ERR5_SET(x)                    (((x) << 30) & 0x40000000)
+
+/* macros for BB_analog_power_on_time */
+#define PHY_BB_ANALOG_POWER_ON_TIME_ADDRESS                                                   0x00009914
+#define PHY_BB_ANALOG_POWER_ON_TIME_OFFSET                                                    0x00009914
+#define PHY_BB_ANALOG_POWER_ON_TIME_ACTIVE_TO_RECEIVE_MSB                                             13
+#define PHY_BB_ANALOG_POWER_ON_TIME_ACTIVE_TO_RECEIVE_LSB                                              0
+#define PHY_BB_ANALOG_POWER_ON_TIME_ACTIVE_TO_RECEIVE_MASK                                    0x00003fff
+#define PHY_BB_ANALOG_POWER_ON_TIME_ACTIVE_TO_RECEIVE_GET(x)                   (((x) & 0x00003fff) >> 0)
+#define PHY_BB_ANALOG_POWER_ON_TIME_ACTIVE_TO_RECEIVE_SET(x)                   (((x) << 0) & 0x00003fff)
+
+/* macros for BB_search_start_delay */
+#define PHY_BB_SEARCH_START_DELAY_ADDRESS                                                     0x00009918
+#define PHY_BB_SEARCH_START_DELAY_OFFSET                                                      0x00009918
+#define PHY_BB_SEARCH_START_DELAY_SEARCH_START_DELAY_MSB                                              11
+#define PHY_BB_SEARCH_START_DELAY_SEARCH_START_DELAY_LSB                                               0
+#define PHY_BB_SEARCH_START_DELAY_SEARCH_START_DELAY_MASK                                     0x00000fff
+#define PHY_BB_SEARCH_START_DELAY_SEARCH_START_DELAY_GET(x)                    (((x) & 0x00000fff) >> 0)
+#define PHY_BB_SEARCH_START_DELAY_SEARCH_START_DELAY_SET(x)                    (((x) << 0) & 0x00000fff)
+#define PHY_BB_SEARCH_START_DELAY_ENABLE_FLT_SVD_MSB                                                  12
+#define PHY_BB_SEARCH_START_DELAY_ENABLE_FLT_SVD_LSB                                                  12
+#define PHY_BB_SEARCH_START_DELAY_ENABLE_FLT_SVD_MASK                                         0x00001000
+#define PHY_BB_SEARCH_START_DELAY_ENABLE_FLT_SVD_GET(x)                       (((x) & 0x00001000) >> 12)
+#define PHY_BB_SEARCH_START_DELAY_ENABLE_FLT_SVD_SET(x)                       (((x) << 12) & 0x00001000)
+#define PHY_BB_SEARCH_START_DELAY_ENABLE_SEND_CHAN_MSB                                                13
+#define PHY_BB_SEARCH_START_DELAY_ENABLE_SEND_CHAN_LSB                                                13
+#define PHY_BB_SEARCH_START_DELAY_ENABLE_SEND_CHAN_MASK                                       0x00002000
+#define PHY_BB_SEARCH_START_DELAY_ENABLE_SEND_CHAN_GET(x)                     (((x) & 0x00002000) >> 13)
+#define PHY_BB_SEARCH_START_DELAY_ENABLE_SEND_CHAN_SET(x)                     (((x) << 13) & 0x00002000)
+
+/* macros for BB_max_rx_length */
+#define PHY_BB_MAX_RX_LENGTH_ADDRESS                                                          0x0000991c
+#define PHY_BB_MAX_RX_LENGTH_OFFSET                                                           0x0000991c
+#define PHY_BB_MAX_RX_LENGTH_MAX_RX_LENGTH_MSB                                                        11
+#define PHY_BB_MAX_RX_LENGTH_MAX_RX_LENGTH_LSB                                                         0
+#define PHY_BB_MAX_RX_LENGTH_MAX_RX_LENGTH_MASK                                               0x00000fff
+#define PHY_BB_MAX_RX_LENGTH_MAX_RX_LENGTH_GET(x)                              (((x) & 0x00000fff) >> 0)
+#define PHY_BB_MAX_RX_LENGTH_MAX_RX_LENGTH_SET(x)                              (((x) << 0) & 0x00000fff)
+#define PHY_BB_MAX_RX_LENGTH_MAX_HT_LENGTH_MSB                                                        29
+#define PHY_BB_MAX_RX_LENGTH_MAX_HT_LENGTH_LSB                                                        12
+#define PHY_BB_MAX_RX_LENGTH_MAX_HT_LENGTH_MASK                                               0x3ffff000
+#define PHY_BB_MAX_RX_LENGTH_MAX_HT_LENGTH_GET(x)                             (((x) & 0x3ffff000) >> 12)
+#define PHY_BB_MAX_RX_LENGTH_MAX_HT_LENGTH_SET(x)                             (((x) << 12) & 0x3ffff000)
+
+/* macros for BB_timing_control_4 */
+#define PHY_BB_TIMING_CONTROL_4_ADDRESS                                                       0x00009920
+#define PHY_BB_TIMING_CONTROL_4_OFFSET                                                        0x00009920
+#define PHY_BB_TIMING_CONTROL_4_CAL_LG_COUNT_MAX_MSB                                                  15
+#define PHY_BB_TIMING_CONTROL_4_CAL_LG_COUNT_MAX_LSB                                                  12
+#define PHY_BB_TIMING_CONTROL_4_CAL_LG_COUNT_MAX_MASK                                         0x0000f000
+#define PHY_BB_TIMING_CONTROL_4_CAL_LG_COUNT_MAX_GET(x)                       (((x) & 0x0000f000) >> 12)
+#define PHY_BB_TIMING_CONTROL_4_CAL_LG_COUNT_MAX_SET(x)                       (((x) << 12) & 0x0000f000)
+#define PHY_BB_TIMING_CONTROL_4_DO_GAIN_DC_IQ_CAL_MSB                                                 16
+#define PHY_BB_TIMING_CONTROL_4_DO_GAIN_DC_IQ_CAL_LSB                                                 16
+#define PHY_BB_TIMING_CONTROL_4_DO_GAIN_DC_IQ_CAL_MASK                                        0x00010000
+#define PHY_BB_TIMING_CONTROL_4_DO_GAIN_DC_IQ_CAL_GET(x)                      (((x) & 0x00010000) >> 16)
+#define PHY_BB_TIMING_CONTROL_4_DO_GAIN_DC_IQ_CAL_SET(x)                      (((x) << 16) & 0x00010000)
+#define PHY_BB_TIMING_CONTROL_4_USE_PILOT_TRACK_DF_MSB                                                20
+#define PHY_BB_TIMING_CONTROL_4_USE_PILOT_TRACK_DF_LSB                                                17
+#define PHY_BB_TIMING_CONTROL_4_USE_PILOT_TRACK_DF_MASK                                       0x001e0000
+#define PHY_BB_TIMING_CONTROL_4_USE_PILOT_TRACK_DF_GET(x)                     (((x) & 0x001e0000) >> 17)
+#define PHY_BB_TIMING_CONTROL_4_USE_PILOT_TRACK_DF_SET(x)                     (((x) << 17) & 0x001e0000)
+#define PHY_BB_TIMING_CONTROL_4_EARLY_TRIGGER_THR_MSB                                                 27
+#define PHY_BB_TIMING_CONTROL_4_EARLY_TRIGGER_THR_LSB                                                 21
+#define PHY_BB_TIMING_CONTROL_4_EARLY_TRIGGER_THR_MASK                                        0x0fe00000
+#define PHY_BB_TIMING_CONTROL_4_EARLY_TRIGGER_THR_GET(x)                      (((x) & 0x0fe00000) >> 21)
+#define PHY_BB_TIMING_CONTROL_4_EARLY_TRIGGER_THR_SET(x)                      (((x) << 21) & 0x0fe00000)
+#define PHY_BB_TIMING_CONTROL_4_ENABLE_PILOT_MASK_MSB                                                 28
+#define PHY_BB_TIMING_CONTROL_4_ENABLE_PILOT_MASK_LSB                                                 28
+#define PHY_BB_TIMING_CONTROL_4_ENABLE_PILOT_MASK_MASK                                        0x10000000
+#define PHY_BB_TIMING_CONTROL_4_ENABLE_PILOT_MASK_GET(x)                      (((x) & 0x10000000) >> 28)
+#define PHY_BB_TIMING_CONTROL_4_ENABLE_PILOT_MASK_SET(x)                      (((x) << 28) & 0x10000000)
+#define PHY_BB_TIMING_CONTROL_4_ENABLE_CHAN_MASK_MSB                                                  29
+#define PHY_BB_TIMING_CONTROL_4_ENABLE_CHAN_MASK_LSB                                                  29
+#define PHY_BB_TIMING_CONTROL_4_ENABLE_CHAN_MASK_MASK                                         0x20000000
+#define PHY_BB_TIMING_CONTROL_4_ENABLE_CHAN_MASK_GET(x)                       (((x) & 0x20000000) >> 29)
+#define PHY_BB_TIMING_CONTROL_4_ENABLE_CHAN_MASK_SET(x)                       (((x) << 29) & 0x20000000)
+#define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_FILTER_MSB                                                30
+#define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_FILTER_LSB                                                30
+#define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_FILTER_MASK                                       0x40000000
+#define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_FILTER_GET(x)                     (((x) & 0x40000000) >> 30)
+#define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_FILTER_SET(x)                     (((x) << 30) & 0x40000000)
+#define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_RSSI_MSB                                                  31
+#define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_RSSI_LSB                                                  31
+#define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_RSSI_MASK                                         0x80000000
+#define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_RSSI_GET(x)                       (((x) & 0x80000000) >> 31)
+#define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_RSSI_SET(x)                       (((x) << 31) & 0x80000000)
+
+/* macros for BB_timing_control_5 */
+#define PHY_BB_TIMING_CONTROL_5_ADDRESS                                                       0x00009924
+#define PHY_BB_TIMING_CONTROL_5_OFFSET                                                        0x00009924
+#define PHY_BB_TIMING_CONTROL_5_ENABLE_CYCPWR_THR1_MSB                                                 0
+#define PHY_BB_TIMING_CONTROL_5_ENABLE_CYCPWR_THR1_LSB                                                 0
+#define PHY_BB_TIMING_CONTROL_5_ENABLE_CYCPWR_THR1_MASK                                       0x00000001
+#define PHY_BB_TIMING_CONTROL_5_ENABLE_CYCPWR_THR1_GET(x)                      (((x) & 0x00000001) >> 0)
+#define PHY_BB_TIMING_CONTROL_5_ENABLE_CYCPWR_THR1_SET(x)                      (((x) << 0) & 0x00000001)
+#define PHY_BB_TIMING_CONTROL_5_CYCPWR_THR1_MSB                                                        7
+#define PHY_BB_TIMING_CONTROL_5_CYCPWR_THR1_LSB                                                        1
+#define PHY_BB_TIMING_CONTROL_5_CYCPWR_THR1_MASK                                              0x000000fe
+#define PHY_BB_TIMING_CONTROL_5_CYCPWR_THR1_GET(x)                             (((x) & 0x000000fe) >> 1)
+#define PHY_BB_TIMING_CONTROL_5_CYCPWR_THR1_SET(x)                             (((x) << 1) & 0x000000fe)
+#define PHY_BB_TIMING_CONTROL_5_ENABLE_RSSI_THR1A_MSB                                                 15
+#define PHY_BB_TIMING_CONTROL_5_ENABLE_RSSI_THR1A_LSB                                                 15
+#define PHY_BB_TIMING_CONTROL_5_ENABLE_RSSI_THR1A_MASK                                        0x00008000
+#define PHY_BB_TIMING_CONTROL_5_ENABLE_RSSI_THR1A_GET(x)                      (((x) & 0x00008000) >> 15)
+#define PHY_BB_TIMING_CONTROL_5_ENABLE_RSSI_THR1A_SET(x)                      (((x) << 15) & 0x00008000)
+#define PHY_BB_TIMING_CONTROL_5_RSSI_THR1A_MSB                                                        22
+#define PHY_BB_TIMING_CONTROL_5_RSSI_THR1A_LSB                                                        16
+#define PHY_BB_TIMING_CONTROL_5_RSSI_THR1A_MASK                                               0x007f0000
+#define PHY_BB_TIMING_CONTROL_5_RSSI_THR1A_GET(x)                             (((x) & 0x007f0000) >> 16)
+#define PHY_BB_TIMING_CONTROL_5_RSSI_THR1A_SET(x)                             (((x) << 16) & 0x007f0000)
+#define PHY_BB_TIMING_CONTROL_5_LONG_SC_THRESH_HI_RSSI_MSB                                            29
+#define PHY_BB_TIMING_CONTROL_5_LONG_SC_THRESH_HI_RSSI_LSB                                            23
+#define PHY_BB_TIMING_CONTROL_5_LONG_SC_THRESH_HI_RSSI_MASK                                   0x3f800000
+#define PHY_BB_TIMING_CONTROL_5_LONG_SC_THRESH_HI_RSSI_GET(x)                 (((x) & 0x3f800000) >> 23)
+#define PHY_BB_TIMING_CONTROL_5_LONG_SC_THRESH_HI_RSSI_SET(x)                 (((x) << 23) & 0x3f800000)
+#define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_MSB                                                30
+#define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_LSB                                                30
+#define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_MASK                                       0x40000000
+#define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_GET(x)                     (((x) & 0x40000000) >> 30)
+#define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_SET(x)                     (((x) << 30) & 0x40000000)
+#define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_EN_MSB                                             31
+#define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_EN_LSB                                             31
+#define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_EN_MASK                                    0x80000000
+#define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_EN_GET(x)                  (((x) & 0x80000000) >> 31)
+#define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_EN_SET(x)                  (((x) << 31) & 0x80000000)
+
+/* macros for BB_phyonly_warm_reset */
+#define PHY_BB_PHYONLY_WARM_RESET_ADDRESS                                                     0x00009928
+#define PHY_BB_PHYONLY_WARM_RESET_OFFSET                                                      0x00009928
+#define PHY_BB_PHYONLY_WARM_RESET_PHYONLY_RST_WARM_L_MSB                                               0
+#define PHY_BB_PHYONLY_WARM_RESET_PHYONLY_RST_WARM_L_LSB                                               0
+#define PHY_BB_PHYONLY_WARM_RESET_PHYONLY_RST_WARM_L_MASK                                     0x00000001
+#define PHY_BB_PHYONLY_WARM_RESET_PHYONLY_RST_WARM_L_GET(x)                    (((x) & 0x00000001) >> 0)
+#define PHY_BB_PHYONLY_WARM_RESET_PHYONLY_RST_WARM_L_SET(x)                    (((x) << 0) & 0x00000001)
+
+/* macros for BB_phyonly_control */
+#define PHY_BB_PHYONLY_CONTROL_ADDRESS                                                        0x0000992c
+#define PHY_BB_PHYONLY_CONTROL_OFFSET                                                         0x0000992c
+#define PHY_BB_PHYONLY_CONTROL_RX_DRAIN_RATE_MSB                                                       0
+#define PHY_BB_PHYONLY_CONTROL_RX_DRAIN_RATE_LSB                                                       0
+#define PHY_BB_PHYONLY_CONTROL_RX_DRAIN_RATE_MASK                                             0x00000001
+#define PHY_BB_PHYONLY_CONTROL_RX_DRAIN_RATE_GET(x)                            (((x) & 0x00000001) >> 0)
+#define PHY_BB_PHYONLY_CONTROL_RX_DRAIN_RATE_SET(x)                            (((x) << 0) & 0x00000001)
+#define PHY_BB_PHYONLY_CONTROL_LATE_TX_SIGNAL_SYMBOL_MSB                                               1
+#define PHY_BB_PHYONLY_CONTROL_LATE_TX_SIGNAL_SYMBOL_LSB                                               1
+#define PHY_BB_PHYONLY_CONTROL_LATE_TX_SIGNAL_SYMBOL_MASK                                     0x00000002
+#define PHY_BB_PHYONLY_CONTROL_LATE_TX_SIGNAL_SYMBOL_GET(x)                    (((x) & 0x00000002) >> 1)
+#define PHY_BB_PHYONLY_CONTROL_LATE_TX_SIGNAL_SYMBOL_SET(x)                    (((x) << 1) & 0x00000002)
+#define PHY_BB_PHYONLY_CONTROL_GENERATE_SCRAMBLER_MSB                                                  2
+#define PHY_BB_PHYONLY_CONTROL_GENERATE_SCRAMBLER_LSB                                                  2
+#define PHY_BB_PHYONLY_CONTROL_GENERATE_SCRAMBLER_MASK                                        0x00000004
+#define PHY_BB_PHYONLY_CONTROL_GENERATE_SCRAMBLER_GET(x)                       (((x) & 0x00000004) >> 2)
+#define PHY_BB_PHYONLY_CONTROL_GENERATE_SCRAMBLER_SET(x)                       (((x) << 2) & 0x00000004)
+#define PHY_BB_PHYONLY_CONTROL_TX_ANTENNA_SELECT_MSB                                                   3
+#define PHY_BB_PHYONLY_CONTROL_TX_ANTENNA_SELECT_LSB                                                   3
+#define PHY_BB_PHYONLY_CONTROL_TX_ANTENNA_SELECT_MASK                                         0x00000008
+#define PHY_BB_PHYONLY_CONTROL_TX_ANTENNA_SELECT_GET(x)                        (((x) & 0x00000008) >> 3)
+#define PHY_BB_PHYONLY_CONTROL_TX_ANTENNA_SELECT_SET(x)                        (((x) << 3) & 0x00000008)
+#define PHY_BB_PHYONLY_CONTROL_STATIC_TX_ANTENNA_MSB                                                   4
+#define PHY_BB_PHYONLY_CONTROL_STATIC_TX_ANTENNA_LSB                                                   4
+#define PHY_BB_PHYONLY_CONTROL_STATIC_TX_ANTENNA_MASK                                         0x00000010
+#define PHY_BB_PHYONLY_CONTROL_STATIC_TX_ANTENNA_GET(x)                        (((x) & 0x00000010) >> 4)
+#define PHY_BB_PHYONLY_CONTROL_STATIC_TX_ANTENNA_SET(x)                        (((x) << 4) & 0x00000010)
+#define PHY_BB_PHYONLY_CONTROL_RX_ANTENNA_SELECT_MSB                                                   5
+#define PHY_BB_PHYONLY_CONTROL_RX_ANTENNA_SELECT_LSB                                                   5
+#define PHY_BB_PHYONLY_CONTROL_RX_ANTENNA_SELECT_MASK                                         0x00000020
+#define PHY_BB_PHYONLY_CONTROL_RX_ANTENNA_SELECT_GET(x)                        (((x) & 0x00000020) >> 5)
+#define PHY_BB_PHYONLY_CONTROL_RX_ANTENNA_SELECT_SET(x)                        (((x) << 5) & 0x00000020)
+#define PHY_BB_PHYONLY_CONTROL_STATIC_RX_ANTENNA_MSB                                                   6
+#define PHY_BB_PHYONLY_CONTROL_STATIC_RX_ANTENNA_LSB                                                   6
+#define PHY_BB_PHYONLY_CONTROL_STATIC_RX_ANTENNA_MASK                                         0x00000040
+#define PHY_BB_PHYONLY_CONTROL_STATIC_RX_ANTENNA_GET(x)                        (((x) & 0x00000040) >> 6)
+#define PHY_BB_PHYONLY_CONTROL_STATIC_RX_ANTENNA_SET(x)                        (((x) << 6) & 0x00000040)
+#define PHY_BB_PHYONLY_CONTROL_EN_LOW_FREQ_SLEEP_MSB                                                   7
+#define PHY_BB_PHYONLY_CONTROL_EN_LOW_FREQ_SLEEP_LSB                                                   7
+#define PHY_BB_PHYONLY_CONTROL_EN_LOW_FREQ_SLEEP_MASK                                         0x00000080
+#define PHY_BB_PHYONLY_CONTROL_EN_LOW_FREQ_SLEEP_GET(x)                        (((x) & 0x00000080) >> 7)
+#define PHY_BB_PHYONLY_CONTROL_EN_LOW_FREQ_SLEEP_SET(x)                        (((x) << 7) & 0x00000080)
+
+/* macros for BB_powertx_rate1 */
+#define PHY_BB_POWERTX_RATE1_ADDRESS                                                          0x00009934
+#define PHY_BB_POWERTX_RATE1_OFFSET                                                           0x00009934
+#define PHY_BB_POWERTX_RATE1_POWERTX_0_MSB                                                             5
+#define PHY_BB_POWERTX_RATE1_POWERTX_0_LSB                                                             0
+#define PHY_BB_POWERTX_RATE1_POWERTX_0_MASK                                                   0x0000003f
+#define PHY_BB_POWERTX_RATE1_POWERTX_0_GET(x)                                  (((x) & 0x0000003f) >> 0)
+#define PHY_BB_POWERTX_RATE1_POWERTX_0_SET(x)                                  (((x) << 0) & 0x0000003f)
+#define PHY_BB_POWERTX_RATE1_POWERTX_1_MSB                                                            13
+#define PHY_BB_POWERTX_RATE1_POWERTX_1_LSB                                                             8
+#define PHY_BB_POWERTX_RATE1_POWERTX_1_MASK                                                   0x00003f00
+#define PHY_BB_POWERTX_RATE1_POWERTX_1_GET(x)                                  (((x) & 0x00003f00) >> 8)
+#define PHY_BB_POWERTX_RATE1_POWERTX_1_SET(x)                                  (((x) << 8) & 0x00003f00)
+#define PHY_BB_POWERTX_RATE1_POWERTX_2_MSB                                                            21
+#define PHY_BB_POWERTX_RATE1_POWERTX_2_LSB                                                            16
+#define PHY_BB_POWERTX_RATE1_POWERTX_2_MASK                                                   0x003f0000
+#define PHY_BB_POWERTX_RATE1_POWERTX_2_GET(x)                                 (((x) & 0x003f0000) >> 16)
+#define PHY_BB_POWERTX_RATE1_POWERTX_2_SET(x)                                 (((x) << 16) & 0x003f0000)
+#define PHY_BB_POWERTX_RATE1_POWERTX_3_MSB                                                            29
+#define PHY_BB_POWERTX_RATE1_POWERTX_3_LSB                                                            24
+#define PHY_BB_POWERTX_RATE1_POWERTX_3_MASK                                                   0x3f000000
+#define PHY_BB_POWERTX_RATE1_POWERTX_3_GET(x)                                 (((x) & 0x3f000000) >> 24)
+#define PHY_BB_POWERTX_RATE1_POWERTX_3_SET(x)                                 (((x) << 24) & 0x3f000000)
+
+/* macros for BB_powertx_rate2 */
+#define PHY_BB_POWERTX_RATE2_ADDRESS                                                          0x00009938
+#define PHY_BB_POWERTX_RATE2_OFFSET                                                           0x00009938
+#define PHY_BB_POWERTX_RATE2_POWERTX_4_MSB                                                             5
+#define PHY_BB_POWERTX_RATE2_POWERTX_4_LSB                                                             0
+#define PHY_BB_POWERTX_RATE2_POWERTX_4_MASK                                                   0x0000003f
+#define PHY_BB_POWERTX_RATE2_POWERTX_4_GET(x)                                  (((x) & 0x0000003f) >> 0)
+#define PHY_BB_POWERTX_RATE2_POWERTX_4_SET(x)                                  (((x) << 0) & 0x0000003f)
+#define PHY_BB_POWERTX_RATE2_POWERTX_5_MSB                                                            13
+#define PHY_BB_POWERTX_RATE2_POWERTX_5_LSB                                                             8
+#define PHY_BB_POWERTX_RATE2_POWERTX_5_MASK                                                   0x00003f00
+#define PHY_BB_POWERTX_RATE2_POWERTX_5_GET(x)                                  (((x) & 0x00003f00) >> 8)
+#define PHY_BB_POWERTX_RATE2_POWERTX_5_SET(x)                                  (((x) << 8) & 0x00003f00)
+#define PHY_BB_POWERTX_RATE2_POWERTX_6_MSB                                                            21
+#define PHY_BB_POWERTX_RATE2_POWERTX_6_LSB                                                            16
+#define PHY_BB_POWERTX_RATE2_POWERTX_6_MASK                                                   0x003f0000
+#define PHY_BB_POWERTX_RATE2_POWERTX_6_GET(x)                                 (((x) & 0x003f0000) >> 16)
+#define PHY_BB_POWERTX_RATE2_POWERTX_6_SET(x)                                 (((x) << 16) & 0x003f0000)
+#define PHY_BB_POWERTX_RATE2_POWERTX_7_MSB                                                            29
+#define PHY_BB_POWERTX_RATE2_POWERTX_7_LSB                                                            24
+#define PHY_BB_POWERTX_RATE2_POWERTX_7_MASK                                                   0x3f000000
+#define PHY_BB_POWERTX_RATE2_POWERTX_7_GET(x)                                 (((x) & 0x3f000000) >> 24)
+#define PHY_BB_POWERTX_RATE2_POWERTX_7_SET(x)                                 (((x) << 24) & 0x3f000000)
+
+/* macros for BB_powertx_max */
+#define PHY_BB_POWERTX_MAX_ADDRESS                                                            0x0000993c
+#define PHY_BB_POWERTX_MAX_OFFSET                                                             0x0000993c
+#define PHY_BB_POWERTX_MAX_USE_PER_PACKET_POWERTX_MAX_MSB                                              6
+#define PHY_BB_POWERTX_MAX_USE_PER_PACKET_POWERTX_MAX_LSB                                              6
+#define PHY_BB_POWERTX_MAX_USE_PER_PACKET_POWERTX_MAX_MASK                                    0x00000040
+#define PHY_BB_POWERTX_MAX_USE_PER_PACKET_POWERTX_MAX_GET(x)                   (((x) & 0x00000040) >> 6)
+#define PHY_BB_POWERTX_MAX_USE_PER_PACKET_POWERTX_MAX_SET(x)                   (((x) << 6) & 0x00000040)
+
+/* macros for BB_extension_radar */
+#define PHY_BB_EXTENSION_RADAR_ADDRESS                                                        0x00009940
+#define PHY_BB_EXTENSION_RADAR_OFFSET                                                         0x00009940
+#define PHY_BB_EXTENSION_RADAR_BLOCKER40_MAX_RADAR_MSB                                                13
+#define PHY_BB_EXTENSION_RADAR_BLOCKER40_MAX_RADAR_LSB                                                 8
+#define PHY_BB_EXTENSION_RADAR_BLOCKER40_MAX_RADAR_MASK                                       0x00003f00
+#define PHY_BB_EXTENSION_RADAR_BLOCKER40_MAX_RADAR_GET(x)                      (((x) & 0x00003f00) >> 8)
+#define PHY_BB_EXTENSION_RADAR_BLOCKER40_MAX_RADAR_SET(x)                      (((x) << 8) & 0x00003f00)
+#define PHY_BB_EXTENSION_RADAR_ENABLE_EXT_RADAR_MSB                                                   14
+#define PHY_BB_EXTENSION_RADAR_ENABLE_EXT_RADAR_LSB                                                   14
+#define PHY_BB_EXTENSION_RADAR_ENABLE_EXT_RADAR_MASK                                          0x00004000
+#define PHY_BB_EXTENSION_RADAR_ENABLE_EXT_RADAR_GET(x)                        (((x) & 0x00004000) >> 14)
+#define PHY_BB_EXTENSION_RADAR_ENABLE_EXT_RADAR_SET(x)                        (((x) << 14) & 0x00004000)
+#define PHY_BB_EXTENSION_RADAR_RADAR_DC_PWR_THRESH_MSB                                                22
+#define PHY_BB_EXTENSION_RADAR_RADAR_DC_PWR_THRESH_LSB                                                15
+#define PHY_BB_EXTENSION_RADAR_RADAR_DC_PWR_THRESH_MASK                                       0x007f8000
+#define PHY_BB_EXTENSION_RADAR_RADAR_DC_PWR_THRESH_GET(x)                     (((x) & 0x007f8000) >> 15)
+#define PHY_BB_EXTENSION_RADAR_RADAR_DC_PWR_THRESH_SET(x)                     (((x) << 15) & 0x007f8000)
+#define PHY_BB_EXTENSION_RADAR_RADAR_LB_DC_CAP_MSB                                                    30
+#define PHY_BB_EXTENSION_RADAR_RADAR_LB_DC_CAP_LSB                                                    23
+#define PHY_BB_EXTENSION_RADAR_RADAR_LB_DC_CAP_MASK                                           0x7f800000
+#define PHY_BB_EXTENSION_RADAR_RADAR_LB_DC_CAP_GET(x)                         (((x) & 0x7f800000) >> 23)
+#define PHY_BB_EXTENSION_RADAR_RADAR_LB_DC_CAP_SET(x)                         (((x) << 23) & 0x7f800000)
+#define PHY_BB_EXTENSION_RADAR_DISABLE_ADCSAT_HOLD_MSB                                                31
+#define PHY_BB_EXTENSION_RADAR_DISABLE_ADCSAT_HOLD_LSB                                                31
+#define PHY_BB_EXTENSION_RADAR_DISABLE_ADCSAT_HOLD_MASK                                       0x80000000
+#define PHY_BB_EXTENSION_RADAR_DISABLE_ADCSAT_HOLD_GET(x)                     (((x) & 0x80000000) >> 31)
+#define PHY_BB_EXTENSION_RADAR_DISABLE_ADCSAT_HOLD_SET(x)                     (((x) << 31) & 0x80000000)
+
+/* macros for BB_frame_control */
+#define PHY_BB_FRAME_CONTROL_ADDRESS                                                          0x00009944
+#define PHY_BB_FRAME_CONTROL_OFFSET                                                           0x00009944
+#define PHY_BB_FRAME_CONTROL_CF_OVERLAP_WINDOW_MSB                                                     1
+#define PHY_BB_FRAME_CONTROL_CF_OVERLAP_WINDOW_LSB                                                     0
+#define PHY_BB_FRAME_CONTROL_CF_OVERLAP_WINDOW_MASK                                           0x00000003
+#define PHY_BB_FRAME_CONTROL_CF_OVERLAP_WINDOW_GET(x)                          (((x) & 0x00000003) >> 0)
+#define PHY_BB_FRAME_CONTROL_CF_OVERLAP_WINDOW_SET(x)                          (((x) << 0) & 0x00000003)
+#define PHY_BB_FRAME_CONTROL_CF_SCALE_SHORT_MSB                                                        2
+#define PHY_BB_FRAME_CONTROL_CF_SCALE_SHORT_LSB                                                        2
+#define PHY_BB_FRAME_CONTROL_CF_SCALE_SHORT_MASK                                              0x00000004
+#define PHY_BB_FRAME_CONTROL_CF_SCALE_SHORT_GET(x)                             (((x) & 0x00000004) >> 2)
+#define PHY_BB_FRAME_CONTROL_CF_SCALE_SHORT_SET(x)                             (((x) << 2) & 0x00000004)
+#define PHY_BB_FRAME_CONTROL_CF_TX_CLIP_MSB                                                            5
+#define PHY_BB_FRAME_CONTROL_CF_TX_CLIP_LSB                                                            3
+#define PHY_BB_FRAME_CONTROL_CF_TX_CLIP_MASK                                                  0x00000038
+#define PHY_BB_FRAME_CONTROL_CF_TX_CLIP_GET(x)                                 (((x) & 0x00000038) >> 3)
+#define PHY_BB_FRAME_CONTROL_CF_TX_CLIP_SET(x)                                 (((x) << 3) & 0x00000038)
+#define PHY_BB_FRAME_CONTROL_CF_TX_DOUBLESAMP_DAC_MSB                                                  7
+#define PHY_BB_FRAME_CONTROL_CF_TX_DOUBLESAMP_DAC_LSB                                                  6
+#define PHY_BB_FRAME_CONTROL_CF_TX_DOUBLESAMP_DAC_MASK                                        0x000000c0
+#define PHY_BB_FRAME_CONTROL_CF_TX_DOUBLESAMP_DAC_GET(x)                       (((x) & 0x000000c0) >> 6)
+#define PHY_BB_FRAME_CONTROL_CF_TX_DOUBLESAMP_DAC_SET(x)                       (((x) << 6) & 0x000000c0)
+#define PHY_BB_FRAME_CONTROL_TX_END_ADJUST_MSB                                                        15
+#define PHY_BB_FRAME_CONTROL_TX_END_ADJUST_LSB                                                         8
+#define PHY_BB_FRAME_CONTROL_TX_END_ADJUST_MASK                                               0x0000ff00
+#define PHY_BB_FRAME_CONTROL_TX_END_ADJUST_GET(x)                              (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_FRAME_CONTROL_TX_END_ADJUST_SET(x)                              (((x) << 8) & 0x0000ff00)
+#define PHY_BB_FRAME_CONTROL_PREPEND_CHAN_INFO_MSB                                                    16
+#define PHY_BB_FRAME_CONTROL_PREPEND_CHAN_INFO_LSB                                                    16
+#define PHY_BB_FRAME_CONTROL_PREPEND_CHAN_INFO_MASK                                           0x00010000
+#define PHY_BB_FRAME_CONTROL_PREPEND_CHAN_INFO_GET(x)                         (((x) & 0x00010000) >> 16)
+#define PHY_BB_FRAME_CONTROL_PREPEND_CHAN_INFO_SET(x)                         (((x) << 16) & 0x00010000)
+#define PHY_BB_FRAME_CONTROL_SHORT_HIGH_PAR_NORM_MSB                                                  17
+#define PHY_BB_FRAME_CONTROL_SHORT_HIGH_PAR_NORM_LSB                                                  17
+#define PHY_BB_FRAME_CONTROL_SHORT_HIGH_PAR_NORM_MASK                                         0x00020000
+#define PHY_BB_FRAME_CONTROL_SHORT_HIGH_PAR_NORM_GET(x)                       (((x) & 0x00020000) >> 17)
+#define PHY_BB_FRAME_CONTROL_SHORT_HIGH_PAR_NORM_SET(x)                       (((x) << 17) & 0x00020000)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_GREEN_FIELD_MSB                                                   18
+#define PHY_BB_FRAME_CONTROL_EN_ERR_GREEN_FIELD_LSB                                                   18
+#define PHY_BB_FRAME_CONTROL_EN_ERR_GREEN_FIELD_MASK                                          0x00040000
+#define PHY_BB_FRAME_CONTROL_EN_ERR_GREEN_FIELD_GET(x)                        (((x) & 0x00040000) >> 18)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_GREEN_FIELD_SET(x)                        (((x) << 18) & 0x00040000)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_XR_POWER_RATIO_MSB                                                19
+#define PHY_BB_FRAME_CONTROL_EN_ERR_XR_POWER_RATIO_LSB                                                19
+#define PHY_BB_FRAME_CONTROL_EN_ERR_XR_POWER_RATIO_MASK                                       0x00080000
+#define PHY_BB_FRAME_CONTROL_EN_ERR_XR_POWER_RATIO_GET(x)                     (((x) & 0x00080000) >> 19)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_XR_POWER_RATIO_SET(x)                     (((x) << 19) & 0x00080000)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_OFDM_XCORR_MSB                                                    20
+#define PHY_BB_FRAME_CONTROL_EN_ERR_OFDM_XCORR_LSB                                                    20
+#define PHY_BB_FRAME_CONTROL_EN_ERR_OFDM_XCORR_MASK                                           0x00100000
+#define PHY_BB_FRAME_CONTROL_EN_ERR_OFDM_XCORR_GET(x)                         (((x) & 0x00100000) >> 20)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_OFDM_XCORR_SET(x)                         (((x) << 20) & 0x00100000)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_LONG_SC_THR_MSB                                                   21
+#define PHY_BB_FRAME_CONTROL_EN_ERR_LONG_SC_THR_LSB                                                   21
+#define PHY_BB_FRAME_CONTROL_EN_ERR_LONG_SC_THR_MASK                                          0x00200000
+#define PHY_BB_FRAME_CONTROL_EN_ERR_LONG_SC_THR_GET(x)                        (((x) & 0x00200000) >> 21)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_LONG_SC_THR_SET(x)                        (((x) << 21) & 0x00200000)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_LONG1_MSB                                                     22
+#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_LONG1_LSB                                                     22
+#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_LONG1_MASK                                            0x00400000
+#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_LONG1_GET(x)                          (((x) & 0x00400000) >> 22)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_LONG1_SET(x)                          (((x) << 22) & 0x00400000)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_EARLY_TRIG_MSB                                                23
+#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_EARLY_TRIG_LSB                                                23
+#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_EARLY_TRIG_MASK                                       0x00800000
+#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_EARLY_TRIG_GET(x)                     (((x) & 0x00800000) >> 23)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_EARLY_TRIG_SET(x)                     (((x) << 23) & 0x00800000)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_TIMEOUT_MSB                                                   24
+#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_TIMEOUT_LSB                                                   24
+#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_TIMEOUT_MASK                                          0x01000000
+#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_TIMEOUT_GET(x)                        (((x) & 0x01000000) >> 24)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_TIMEOUT_SET(x)                        (((x) << 24) & 0x01000000)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_SIGNAL_PARITY_MSB                                                 25
+#define PHY_BB_FRAME_CONTROL_EN_ERR_SIGNAL_PARITY_LSB                                                 25
+#define PHY_BB_FRAME_CONTROL_EN_ERR_SIGNAL_PARITY_MASK                                        0x02000000
+#define PHY_BB_FRAME_CONTROL_EN_ERR_SIGNAL_PARITY_GET(x)                      (((x) & 0x02000000) >> 25)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_SIGNAL_PARITY_SET(x)                      (((x) << 25) & 0x02000000)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_RATE_ILLEGAL_MSB                                                  26
+#define PHY_BB_FRAME_CONTROL_EN_ERR_RATE_ILLEGAL_LSB                                                  26
+#define PHY_BB_FRAME_CONTROL_EN_ERR_RATE_ILLEGAL_MASK                                         0x04000000
+#define PHY_BB_FRAME_CONTROL_EN_ERR_RATE_ILLEGAL_GET(x)                       (((x) & 0x04000000) >> 26)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_RATE_ILLEGAL_SET(x)                       (((x) << 26) & 0x04000000)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_LENGTH_ILLEGAL_MSB                                                27
+#define PHY_BB_FRAME_CONTROL_EN_ERR_LENGTH_ILLEGAL_LSB                                                27
+#define PHY_BB_FRAME_CONTROL_EN_ERR_LENGTH_ILLEGAL_MASK                                       0x08000000
+#define PHY_BB_FRAME_CONTROL_EN_ERR_LENGTH_ILLEGAL_GET(x)                     (((x) & 0x08000000) >> 27)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_LENGTH_ILLEGAL_SET(x)                     (((x) << 27) & 0x08000000)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_HT_SERVICE_MSB                                                    28
+#define PHY_BB_FRAME_CONTROL_EN_ERR_HT_SERVICE_LSB                                                    28
+#define PHY_BB_FRAME_CONTROL_EN_ERR_HT_SERVICE_MASK                                           0x10000000
+#define PHY_BB_FRAME_CONTROL_EN_ERR_HT_SERVICE_GET(x)                         (((x) & 0x10000000) >> 28)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_HT_SERVICE_SET(x)                         (((x) << 28) & 0x10000000)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_SERVICE_MSB                                                       29
+#define PHY_BB_FRAME_CONTROL_EN_ERR_SERVICE_LSB                                                       29
+#define PHY_BB_FRAME_CONTROL_EN_ERR_SERVICE_MASK                                              0x20000000
+#define PHY_BB_FRAME_CONTROL_EN_ERR_SERVICE_GET(x)                            (((x) & 0x20000000) >> 29)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_SERVICE_SET(x)                            (((x) << 29) & 0x20000000)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_TX_UNDERRUN_MSB                                                   30
+#define PHY_BB_FRAME_CONTROL_EN_ERR_TX_UNDERRUN_LSB                                                   30
+#define PHY_BB_FRAME_CONTROL_EN_ERR_TX_UNDERRUN_MASK                                          0x40000000
+#define PHY_BB_FRAME_CONTROL_EN_ERR_TX_UNDERRUN_GET(x)                        (((x) & 0x40000000) >> 30)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_TX_UNDERRUN_SET(x)                        (((x) << 30) & 0x40000000)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_RX_ABORT_MSB                                                      31
+#define PHY_BB_FRAME_CONTROL_EN_ERR_RX_ABORT_LSB                                                      31
+#define PHY_BB_FRAME_CONTROL_EN_ERR_RX_ABORT_MASK                                             0x80000000
+#define PHY_BB_FRAME_CONTROL_EN_ERR_RX_ABORT_GET(x)                           (((x) & 0x80000000) >> 31)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_RX_ABORT_SET(x)                           (((x) << 31) & 0x80000000)
+
+/* macros for BB_timing_control_6 */
+#define PHY_BB_TIMING_CONTROL_6_ADDRESS                                                       0x00009948
+#define PHY_BB_TIMING_CONTROL_6_OFFSET                                                        0x00009948
+#define PHY_BB_TIMING_CONTROL_6_HI_RSSI_THRESH_MSB                                                     7
+#define PHY_BB_TIMING_CONTROL_6_HI_RSSI_THRESH_LSB                                                     0
+#define PHY_BB_TIMING_CONTROL_6_HI_RSSI_THRESH_MASK                                           0x000000ff
+#define PHY_BB_TIMING_CONTROL_6_HI_RSSI_THRESH_GET(x)                          (((x) & 0x000000ff) >> 0)
+#define PHY_BB_TIMING_CONTROL_6_HI_RSSI_THRESH_SET(x)                          (((x) << 0) & 0x000000ff)
+#define PHY_BB_TIMING_CONTROL_6_EARLY_TRIGGER_THR_HI_RSSI_MSB                                         14
+#define PHY_BB_TIMING_CONTROL_6_EARLY_TRIGGER_THR_HI_RSSI_LSB                                          8
+#define PHY_BB_TIMING_CONTROL_6_EARLY_TRIGGER_THR_HI_RSSI_MASK                                0x00007f00
+#define PHY_BB_TIMING_CONTROL_6_EARLY_TRIGGER_THR_HI_RSSI_GET(x)               (((x) & 0x00007f00) >> 8)
+#define PHY_BB_TIMING_CONTROL_6_EARLY_TRIGGER_THR_HI_RSSI_SET(x)               (((x) << 8) & 0x00007f00)
+#define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_MSB                                                 20
+#define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_LSB                                                 15
+#define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_MASK                                        0x001f8000
+#define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_GET(x)                      (((x) & 0x001f8000) >> 15)
+#define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_SET(x)                      (((x) << 15) & 0x001f8000)
+#define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_HI_RSSI_MSB                                         27
+#define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_HI_RSSI_LSB                                         21
+#define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_HI_RSSI_MASK                                0x0fe00000
+#define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_HI_RSSI_GET(x)              (((x) & 0x0fe00000) >> 21)
+#define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_HI_RSSI_SET(x)              (((x) << 21) & 0x0fe00000)
+#define PHY_BB_TIMING_CONTROL_6_LONG_MEDIUM_RATIO_THR_MSB                                             31
+#define PHY_BB_TIMING_CONTROL_6_LONG_MEDIUM_RATIO_THR_LSB                                             28
+#define PHY_BB_TIMING_CONTROL_6_LONG_MEDIUM_RATIO_THR_MASK                                    0xf0000000
+#define PHY_BB_TIMING_CONTROL_6_LONG_MEDIUM_RATIO_THR_GET(x)                  (((x) & 0xf0000000) >> 28)
+#define PHY_BB_TIMING_CONTROL_6_LONG_MEDIUM_RATIO_THR_SET(x)                  (((x) << 28) & 0xf0000000)
+
+/* macros for BB_spur_mask_controls */
+#define PHY_BB_SPUR_MASK_CONTROLS_ADDRESS                                                     0x0000994c
+#define PHY_BB_SPUR_MASK_CONTROLS_OFFSET                                                      0x0000994c
+#define PHY_BB_SPUR_MASK_CONTROLS_SPUR_RSSI_THRESH_MSB                                                 7
+#define PHY_BB_SPUR_MASK_CONTROLS_SPUR_RSSI_THRESH_LSB                                                 0
+#define PHY_BB_SPUR_MASK_CONTROLS_SPUR_RSSI_THRESH_MASK                                       0x000000ff
+#define PHY_BB_SPUR_MASK_CONTROLS_SPUR_RSSI_THRESH_GET(x)                      (((x) & 0x000000ff) >> 0)
+#define PHY_BB_SPUR_MASK_CONTROLS_SPUR_RSSI_THRESH_SET(x)                      (((x) << 0) & 0x000000ff)
+#define PHY_BB_SPUR_MASK_CONTROLS_EN_VIT_SPUR_RSSI_MSB                                                 8
+#define PHY_BB_SPUR_MASK_CONTROLS_EN_VIT_SPUR_RSSI_LSB                                                 8
+#define PHY_BB_SPUR_MASK_CONTROLS_EN_VIT_SPUR_RSSI_MASK                                       0x00000100
+#define PHY_BB_SPUR_MASK_CONTROLS_EN_VIT_SPUR_RSSI_GET(x)                      (((x) & 0x00000100) >> 8)
+#define PHY_BB_SPUR_MASK_CONTROLS_EN_VIT_SPUR_RSSI_SET(x)                      (((x) << 8) & 0x00000100)
+#define PHY_BB_SPUR_MASK_CONTROLS_ENABLE_MASK_PPM_MSB                                                 17
+#define PHY_BB_SPUR_MASK_CONTROLS_ENABLE_MASK_PPM_LSB                                                 17
+#define PHY_BB_SPUR_MASK_CONTROLS_ENABLE_MASK_PPM_MASK                                        0x00020000
+#define PHY_BB_SPUR_MASK_CONTROLS_ENABLE_MASK_PPM_GET(x)                      (((x) & 0x00020000) >> 17)
+#define PHY_BB_SPUR_MASK_CONTROLS_ENABLE_MASK_PPM_SET(x)                      (((x) << 17) & 0x00020000)
+#define PHY_BB_SPUR_MASK_CONTROLS_MASK_RATE_CNTL_MSB                                                  25
+#define PHY_BB_SPUR_MASK_CONTROLS_MASK_RATE_CNTL_LSB                                                  18
+#define PHY_BB_SPUR_MASK_CONTROLS_MASK_RATE_CNTL_MASK                                         0x03fc0000
+#define PHY_BB_SPUR_MASK_CONTROLS_MASK_RATE_CNTL_GET(x)                       (((x) & 0x03fc0000) >> 18)
+#define PHY_BB_SPUR_MASK_CONTROLS_MASK_RATE_CNTL_SET(x)                       (((x) << 18) & 0x03fc0000)
+
+/* macros for BB_rx_iq_corr_b0 */
+#define PHY_BB_RX_IQ_CORR_B0_ADDRESS                                                          0x00009950
+#define PHY_BB_RX_IQ_CORR_B0_OFFSET                                                           0x00009950
+#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_Q_COFF_0_MSB                                                  6
+#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_Q_COFF_0_LSB                                                  0
+#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_Q_COFF_0_MASK                                        0x0000007f
+#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_Q_COFF_0_GET(x)                       (((x) & 0x0000007f) >> 0)
+#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_Q_COFF_0_SET(x)                       (((x) << 0) & 0x0000007f)
+#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_I_COFF_0_MSB                                                 13
+#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_I_COFF_0_LSB                                                  7
+#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_I_COFF_0_MASK                                        0x00003f80
+#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_I_COFF_0_GET(x)                       (((x) & 0x00003f80) >> 7)
+#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_I_COFF_0_SET(x)                       (((x) << 7) & 0x00003f80)
+#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_ENABLE_MSB                                                     14
+#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_ENABLE_LSB                                                     14
+#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_ENABLE_MASK                                            0x00004000
+#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_ENABLE_GET(x)                          (((x) & 0x00004000) >> 14)
+#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_ENABLE_SET(x)                          (((x) << 14) & 0x00004000)
+#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_Q_COFF_0_MSB                                           21
+#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_Q_COFF_0_LSB                                           15
+#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_Q_COFF_0_MASK                                  0x003f8000
+#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_Q_COFF_0_GET(x)                (((x) & 0x003f8000) >> 15)
+#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_Q_COFF_0_SET(x)                (((x) << 15) & 0x003f8000)
+#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_I_COFF_0_MSB                                           28
+#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_I_COFF_0_LSB                                           22
+#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_I_COFF_0_MASK                                  0x1fc00000
+#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_I_COFF_0_GET(x)                (((x) & 0x1fc00000) >> 22)
+#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_I_COFF_0_SET(x)                (((x) << 22) & 0x1fc00000)
+#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_ENABLE_MSB                                               29
+#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_ENABLE_LSB                                               29
+#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_ENABLE_MASK                                      0x20000000
+#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_ENABLE_GET(x)                    (((x) & 0x20000000) >> 29)
+#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_ENABLE_SET(x)                    (((x) << 29) & 0x20000000)
+
+/* macros for BB_radar_detection */
+#define PHY_BB_RADAR_DETECTION_ADDRESS                                                        0x00009954
+#define PHY_BB_RADAR_DETECTION_OFFSET                                                         0x00009954
+#define PHY_BB_RADAR_DETECTION_PULSE_DETECT_ENABLE_MSB                                                 0
+#define PHY_BB_RADAR_DETECTION_PULSE_DETECT_ENABLE_LSB                                                 0
+#define PHY_BB_RADAR_DETECTION_PULSE_DETECT_ENABLE_MASK                                       0x00000001
+#define PHY_BB_RADAR_DETECTION_PULSE_DETECT_ENABLE_GET(x)                      (((x) & 0x00000001) >> 0)
+#define PHY_BB_RADAR_DETECTION_PULSE_DETECT_ENABLE_SET(x)                      (((x) << 0) & 0x00000001)
+#define PHY_BB_RADAR_DETECTION_PULSE_IN_BAND_THRESH_MSB                                                5
+#define PHY_BB_RADAR_DETECTION_PULSE_IN_BAND_THRESH_LSB                                                1
+#define PHY_BB_RADAR_DETECTION_PULSE_IN_BAND_THRESH_MASK                                      0x0000003e
+#define PHY_BB_RADAR_DETECTION_PULSE_IN_BAND_THRESH_GET(x)                     (((x) & 0x0000003e) >> 1)
+#define PHY_BB_RADAR_DETECTION_PULSE_IN_BAND_THRESH_SET(x)                     (((x) << 1) & 0x0000003e)
+#define PHY_BB_RADAR_DETECTION_PULSE_RSSI_THRESH_MSB                                                  11
+#define PHY_BB_RADAR_DETECTION_PULSE_RSSI_THRESH_LSB                                                   6
+#define PHY_BB_RADAR_DETECTION_PULSE_RSSI_THRESH_MASK                                         0x00000fc0
+#define PHY_BB_RADAR_DETECTION_PULSE_RSSI_THRESH_GET(x)                        (((x) & 0x00000fc0) >> 6)
+#define PHY_BB_RADAR_DETECTION_PULSE_RSSI_THRESH_SET(x)                        (((x) << 6) & 0x00000fc0)
+#define PHY_BB_RADAR_DETECTION_PULSE_HEIGHT_THRESH_MSB                                                17
+#define PHY_BB_RADAR_DETECTION_PULSE_HEIGHT_THRESH_LSB                                                12
+#define PHY_BB_RADAR_DETECTION_PULSE_HEIGHT_THRESH_MASK                                       0x0003f000
+#define PHY_BB_RADAR_DETECTION_PULSE_HEIGHT_THRESH_GET(x)                     (((x) & 0x0003f000) >> 12)
+#define PHY_BB_RADAR_DETECTION_PULSE_HEIGHT_THRESH_SET(x)                     (((x) << 12) & 0x0003f000)
+#define PHY_BB_RADAR_DETECTION_RADAR_RSSI_THRESH_MSB                                                  23
+#define PHY_BB_RADAR_DETECTION_RADAR_RSSI_THRESH_LSB                                                  18
+#define PHY_BB_RADAR_DETECTION_RADAR_RSSI_THRESH_MASK                                         0x00fc0000
+#define PHY_BB_RADAR_DETECTION_RADAR_RSSI_THRESH_GET(x)                       (((x) & 0x00fc0000) >> 18)
+#define PHY_BB_RADAR_DETECTION_RADAR_RSSI_THRESH_SET(x)                       (((x) << 18) & 0x00fc0000)
+#define PHY_BB_RADAR_DETECTION_RADAR_FIRPWR_THRESH_MSB                                                30
+#define PHY_BB_RADAR_DETECTION_RADAR_FIRPWR_THRESH_LSB                                                24
+#define PHY_BB_RADAR_DETECTION_RADAR_FIRPWR_THRESH_MASK                                       0x7f000000
+#define PHY_BB_RADAR_DETECTION_RADAR_FIRPWR_THRESH_GET(x)                     (((x) & 0x7f000000) >> 24)
+#define PHY_BB_RADAR_DETECTION_RADAR_FIRPWR_THRESH_SET(x)                     (((x) << 24) & 0x7f000000)
+#define PHY_BB_RADAR_DETECTION_ENABLE_RADAR_FFT_MSB                                                   31
+#define PHY_BB_RADAR_DETECTION_ENABLE_RADAR_FFT_LSB                                                   31
+#define PHY_BB_RADAR_DETECTION_ENABLE_RADAR_FFT_MASK                                          0x80000000
+#define PHY_BB_RADAR_DETECTION_ENABLE_RADAR_FFT_GET(x)                        (((x) & 0x80000000) >> 31)
+#define PHY_BB_RADAR_DETECTION_ENABLE_RADAR_FFT_SET(x)                        (((x) << 31) & 0x80000000)
+
+/* macros for BB_radar_detection_2 */
+#define PHY_BB_RADAR_DETECTION_2_ADDRESS                                                      0x00009958
+#define PHY_BB_RADAR_DETECTION_2_OFFSET                                                       0x00009958
+#define PHY_BB_RADAR_DETECTION_2_RADAR_LENGTH_MAX_MSB                                                  7
+#define PHY_BB_RADAR_DETECTION_2_RADAR_LENGTH_MAX_LSB                                                  0
+#define PHY_BB_RADAR_DETECTION_2_RADAR_LENGTH_MAX_MASK                                        0x000000ff
+#define PHY_BB_RADAR_DETECTION_2_RADAR_LENGTH_MAX_GET(x)                       (((x) & 0x000000ff) >> 0)
+#define PHY_BB_RADAR_DETECTION_2_RADAR_LENGTH_MAX_SET(x)                       (((x) << 0) & 0x000000ff)
+#define PHY_BB_RADAR_DETECTION_2_PULSE_RELSTEP_THRESH_MSB                                             12
+#define PHY_BB_RADAR_DETECTION_2_PULSE_RELSTEP_THRESH_LSB                                              8
+#define PHY_BB_RADAR_DETECTION_2_PULSE_RELSTEP_THRESH_MASK                                    0x00001f00
+#define PHY_BB_RADAR_DETECTION_2_PULSE_RELSTEP_THRESH_GET(x)                   (((x) & 0x00001f00) >> 8)
+#define PHY_BB_RADAR_DETECTION_2_PULSE_RELSTEP_THRESH_SET(x)                   (((x) << 8) & 0x00001f00)
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_RELSTEP_CHECK_MSB                                       13
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_RELSTEP_CHECK_LSB                                       13
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_RELSTEP_CHECK_MASK                              0x00002000
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_RELSTEP_CHECK_GET(x)            (((x) & 0x00002000) >> 13)
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_RELSTEP_CHECK_SET(x)            (((x) << 13) & 0x00002000)
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_MAX_RADAR_RSSI_MSB                                            14
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_MAX_RADAR_RSSI_LSB                                            14
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_MAX_RADAR_RSSI_MASK                                   0x00004000
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_MAX_RADAR_RSSI_GET(x)                 (((x) & 0x00004000) >> 14)
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_MAX_RADAR_RSSI_SET(x)                 (((x) << 14) & 0x00004000)
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_BLOCK_RADAR_CHECK_MSB                                         15
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_BLOCK_RADAR_CHECK_LSB                                         15
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_BLOCK_RADAR_CHECK_MASK                                0x00008000
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_BLOCK_RADAR_CHECK_GET(x)              (((x) & 0x00008000) >> 15)
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_BLOCK_RADAR_CHECK_SET(x)              (((x) << 15) & 0x00008000)
+#define PHY_BB_RADAR_DETECTION_2_RADAR_RELPWR_THRESH_MSB                                              21
+#define PHY_BB_RADAR_DETECTION_2_RADAR_RELPWR_THRESH_LSB                                              16
+#define PHY_BB_RADAR_DETECTION_2_RADAR_RELPWR_THRESH_MASK                                     0x003f0000
+#define PHY_BB_RADAR_DETECTION_2_RADAR_RELPWR_THRESH_GET(x)                   (((x) & 0x003f0000) >> 16)
+#define PHY_BB_RADAR_DETECTION_2_RADAR_RELPWR_THRESH_SET(x)                   (((x) << 16) & 0x003f0000)
+#define PHY_BB_RADAR_DETECTION_2_RADAR_USE_FIRPWR_128_MSB                                             22
+#define PHY_BB_RADAR_DETECTION_2_RADAR_USE_FIRPWR_128_LSB                                             22
+#define PHY_BB_RADAR_DETECTION_2_RADAR_USE_FIRPWR_128_MASK                                    0x00400000
+#define PHY_BB_RADAR_DETECTION_2_RADAR_USE_FIRPWR_128_GET(x)                  (((x) & 0x00400000) >> 22)
+#define PHY_BB_RADAR_DETECTION_2_RADAR_USE_FIRPWR_128_SET(x)                  (((x) << 22) & 0x00400000)
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_RADAR_RELPWR_CHECK_MSB                                        23
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_RADAR_RELPWR_CHECK_LSB                                        23
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_RADAR_RELPWR_CHECK_MASK                               0x00800000
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_RADAR_RELPWR_CHECK_GET(x)             (((x) & 0x00800000) >> 23)
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_RADAR_RELPWR_CHECK_SET(x)             (((x) << 23) & 0x00800000)
+#define PHY_BB_RADAR_DETECTION_2_CF_RADAR_BIN_THRESH_SEL_MSB                                          26
+#define PHY_BB_RADAR_DETECTION_2_CF_RADAR_BIN_THRESH_SEL_LSB                                          24
+#define PHY_BB_RADAR_DETECTION_2_CF_RADAR_BIN_THRESH_SEL_MASK                                 0x07000000
+#define PHY_BB_RADAR_DETECTION_2_CF_RADAR_BIN_THRESH_SEL_GET(x)               (((x) & 0x07000000) >> 24)
+#define PHY_BB_RADAR_DETECTION_2_CF_RADAR_BIN_THRESH_SEL_SET(x)               (((x) << 24) & 0x07000000)
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_GC_COUNT_CHECK_MSB                                      27
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_GC_COUNT_CHECK_LSB                                      27
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_GC_COUNT_CHECK_MASK                             0x08000000
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_GC_COUNT_CHECK_GET(x)           (((x) & 0x08000000) >> 27)
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_GC_COUNT_CHECK_SET(x)           (((x) << 27) & 0x08000000)
+
+/* macros for BB_tx_phase_ramp_b0 */
+#define PHY_BB_TX_PHASE_RAMP_B0_ADDRESS                                                       0x0000995c
+#define PHY_BB_TX_PHASE_RAMP_B0_OFFSET                                                        0x0000995c
+#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ENABLE_0_MSB                                             0
+#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ENABLE_0_LSB                                             0
+#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ENABLE_0_MASK                                   0x00000001
+#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ENABLE_0_GET(x)                  (((x) & 0x00000001) >> 0)
+#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ENABLE_0_SET(x)                  (((x) << 0) & 0x00000001)
+#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_BIAS_0_MSB                                               6
+#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_BIAS_0_LSB                                               1
+#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_BIAS_0_MASK                                     0x0000007e
+#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_BIAS_0_GET(x)                    (((x) & 0x0000007e) >> 1)
+#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_BIAS_0_SET(x)                    (((x) << 1) & 0x0000007e)
+#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_INIT_0_MSB                                              16
+#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_INIT_0_LSB                                               7
+#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_INIT_0_MASK                                     0x0001ff80
+#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_INIT_0_GET(x)                    (((x) & 0x0001ff80) >> 7)
+#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_INIT_0_SET(x)                    (((x) << 7) & 0x0001ff80)
+#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ALPHA_0_MSB                                             24
+#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ALPHA_0_LSB                                             17
+#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ALPHA_0_MASK                                    0x01fe0000
+#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ALPHA_0_GET(x)                  (((x) & 0x01fe0000) >> 17)
+#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ALPHA_0_SET(x)                  (((x) << 17) & 0x01fe0000)
+
+/* macros for BB_switch_table_chn_b0 */
+#define PHY_BB_SWITCH_TABLE_CHN_B0_ADDRESS                                                    0x00009960
+#define PHY_BB_SWITCH_TABLE_CHN_B0_OFFSET                                                     0x00009960
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_IDLE_0_MSB                                             1
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_IDLE_0_LSB                                             0
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_IDLE_0_MASK                                   0x00000003
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_IDLE_0_GET(x)                  (((x) & 0x00000003) >> 0)
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_IDLE_0_SET(x)                  (((x) << 0) & 0x00000003)
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_T_0_MSB                                                3
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_T_0_LSB                                                2
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_T_0_MASK                                      0x0000000c
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_T_0_GET(x)                     (((x) & 0x0000000c) >> 2)
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_T_0_SET(x)                     (((x) << 2) & 0x0000000c)
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_R_0_MSB                                                5
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_R_0_LSB                                                4
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_R_0_MASK                                      0x00000030
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_R_0_GET(x)                     (((x) & 0x00000030) >> 4)
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_R_0_SET(x)                     (((x) << 4) & 0x00000030)
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX1_0_MSB                                              7
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX1_0_LSB                                              6
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX1_0_MASK                                    0x000000c0
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX1_0_GET(x)                   (((x) & 0x000000c0) >> 6)
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX1_0_SET(x)                   (((x) << 6) & 0x000000c0)
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX12_0_MSB                                             9
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX12_0_LSB                                             8
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX12_0_MASK                                   0x00000300
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX12_0_GET(x)                  (((x) & 0x00000300) >> 8)
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX12_0_SET(x)                  (((x) << 8) & 0x00000300)
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_B_0_MSB                                               11
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_B_0_LSB                                               10
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_B_0_MASK                                      0x00000c00
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_B_0_GET(x)                    (((x) & 0x00000c00) >> 10)
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_B_0_SET(x)                    (((x) << 10) & 0x00000c00)
+
+/* macros for BB_switch_table_com1 */
+#define PHY_BB_SWITCH_TABLE_COM1_ADDRESS                                                      0x00009964
+#define PHY_BB_SWITCH_TABLE_COM1_OFFSET                                                       0x00009964
+#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_IDLE_MSB                                             3
+#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_IDLE_LSB                                             0
+#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_IDLE_MASK                                   0x0000000f
+#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_IDLE_GET(x)                  (((x) & 0x0000000f) >> 0)
+#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_IDLE_SET(x)                  (((x) << 0) & 0x0000000f)
+#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T1_MSB                                               7
+#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T1_LSB                                               4
+#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T1_MASK                                     0x000000f0
+#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T1_GET(x)                    (((x) & 0x000000f0) >> 4)
+#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T1_SET(x)                    (((x) << 4) & 0x000000f0)
+#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T2_MSB                                              11
+#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T2_LSB                                               8
+#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T2_MASK                                     0x00000f00
+#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T2_GET(x)                    (((x) & 0x00000f00) >> 8)
+#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T2_SET(x)                    (((x) << 8) & 0x00000f00)
+#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_B_MSB                                               15
+#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_B_LSB                                               12
+#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_B_MASK                                      0x0000f000
+#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_B_GET(x)                    (((x) & 0x0000f000) >> 12)
+#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_B_SET(x)                    (((x) << 12) & 0x0000f000)
+
+/* macros for BB_cca_ctrl_2_b0 */
+#define PHY_BB_CCA_CTRL_2_B0_ADDRESS                                                          0x00009968
+#define PHY_BB_CCA_CTRL_2_B0_OFFSET                                                           0x00009968
+#define PHY_BB_CCA_CTRL_2_B0_MINCCAPWR_THR_0_MSB                                                       8
+#define PHY_BB_CCA_CTRL_2_B0_MINCCAPWR_THR_0_LSB                                                       0
+#define PHY_BB_CCA_CTRL_2_B0_MINCCAPWR_THR_0_MASK                                             0x000001ff
+#define PHY_BB_CCA_CTRL_2_B0_MINCCAPWR_THR_0_GET(x)                            (((x) & 0x000001ff) >> 0)
+#define PHY_BB_CCA_CTRL_2_B0_MINCCAPWR_THR_0_SET(x)                            (((x) << 0) & 0x000001ff)
+#define PHY_BB_CCA_CTRL_2_B0_ENABLE_MINCCAPWR_THR_MSB                                                  9
+#define PHY_BB_CCA_CTRL_2_B0_ENABLE_MINCCAPWR_THR_LSB                                                  9
+#define PHY_BB_CCA_CTRL_2_B0_ENABLE_MINCCAPWR_THR_MASK                                        0x00000200
+#define PHY_BB_CCA_CTRL_2_B0_ENABLE_MINCCAPWR_THR_GET(x)                       (((x) & 0x00000200) >> 9)
+#define PHY_BB_CCA_CTRL_2_B0_ENABLE_MINCCAPWR_THR_SET(x)                       (((x) << 9) & 0x00000200)
+#define PHY_BB_CCA_CTRL_2_B0_NF_GAIN_COMP_0_MSB                                                       17
+#define PHY_BB_CCA_CTRL_2_B0_NF_GAIN_COMP_0_LSB                                                       10
+#define PHY_BB_CCA_CTRL_2_B0_NF_GAIN_COMP_0_MASK                                              0x0003fc00
+#define PHY_BB_CCA_CTRL_2_B0_NF_GAIN_COMP_0_GET(x)                            (((x) & 0x0003fc00) >> 10)
+#define PHY_BB_CCA_CTRL_2_B0_NF_GAIN_COMP_0_SET(x)                            (((x) << 10) & 0x0003fc00)
+#define PHY_BB_CCA_CTRL_2_B0_THRESH62_MODE_MSB                                                        18
+#define PHY_BB_CCA_CTRL_2_B0_THRESH62_MODE_LSB                                                        18
+#define PHY_BB_CCA_CTRL_2_B0_THRESH62_MODE_MASK                                               0x00040000
+#define PHY_BB_CCA_CTRL_2_B0_THRESH62_MODE_GET(x)                             (((x) & 0x00040000) >> 18)
+#define PHY_BB_CCA_CTRL_2_B0_THRESH62_MODE_SET(x)                             (((x) << 18) & 0x00040000)
+
+/* macros for BB_switch_table_com2 */
+#define PHY_BB_SWITCH_TABLE_COM2_ADDRESS                                                      0x0000996c
+#define PHY_BB_SWITCH_TABLE_COM2_OFFSET                                                       0x0000996c
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL1_MSB                                         3
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL1_LSB                                         0
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL1_MASK                               0x0000000f
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL1_GET(x)              (((x) & 0x0000000f) >> 0)
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL1_SET(x)              (((x) << 0) & 0x0000000f)
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL1_MSB                                         7
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL1_LSB                                         4
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL1_MASK                               0x000000f0
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL1_GET(x)              (((x) & 0x000000f0) >> 4)
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL1_SET(x)              (((x) << 4) & 0x000000f0)
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL1_MSB                                         11
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL1_LSB                                          8
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL1_MASK                                0x00000f00
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL1_GET(x)               (((x) & 0x00000f00) >> 8)
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL1_SET(x)               (((x) << 8) & 0x00000f00)
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL1_MSB                                         15
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL1_LSB                                         12
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL1_MASK                                0x0000f000
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL1_GET(x)              (((x) & 0x0000f000) >> 12)
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL1_SET(x)              (((x) << 12) & 0x0000f000)
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL2_MSB                                        19
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL2_LSB                                        16
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL2_MASK                               0x000f0000
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL2_GET(x)             (((x) & 0x000f0000) >> 16)
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL2_SET(x)             (((x) << 16) & 0x000f0000)
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL2_MSB                                        23
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL2_LSB                                        20
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL2_MASK                               0x00f00000
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL2_GET(x)             (((x) & 0x00f00000) >> 20)
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL2_SET(x)             (((x) << 20) & 0x00f00000)
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL2_MSB                                         27
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL2_LSB                                         24
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL2_MASK                                0x0f000000
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL2_GET(x)              (((x) & 0x0f000000) >> 24)
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL2_SET(x)              (((x) << 24) & 0x0f000000)
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL2_MSB                                         31
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL2_LSB                                         28
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL2_MASK                                0xf0000000
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL2_GET(x)              (((x) & 0xf0000000) >> 28)
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL2_SET(x)              (((x) << 28) & 0xf0000000)
+
+/* macros for BB_restart */
+#define PHY_BB_RESTART_ADDRESS                                                                0x00009970
+#define PHY_BB_RESTART_OFFSET                                                                 0x00009970
+#define PHY_BB_RESTART_ENABLE_RESTART_MSB                                                              0
+#define PHY_BB_RESTART_ENABLE_RESTART_LSB                                                              0
+#define PHY_BB_RESTART_ENABLE_RESTART_MASK                                                    0x00000001
+#define PHY_BB_RESTART_ENABLE_RESTART_GET(x)                                   (((x) & 0x00000001) >> 0)
+#define PHY_BB_RESTART_ENABLE_RESTART_SET(x)                                   (((x) << 0) & 0x00000001)
+#define PHY_BB_RESTART_RESTART_LGFIRPWR_DELTA_MSB                                                      5
+#define PHY_BB_RESTART_RESTART_LGFIRPWR_DELTA_LSB                                                      1
+#define PHY_BB_RESTART_RESTART_LGFIRPWR_DELTA_MASK                                            0x0000003e
+#define PHY_BB_RESTART_RESTART_LGFIRPWR_DELTA_GET(x)                           (((x) & 0x0000003e) >> 1)
+#define PHY_BB_RESTART_RESTART_LGFIRPWR_DELTA_SET(x)                           (((x) << 1) & 0x0000003e)
+#define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_MSB                                                         6
+#define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_LSB                                                         6
+#define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_MASK                                               0x00000040
+#define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_GET(x)                              (((x) & 0x00000040) >> 6)
+#define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_SET(x)                              (((x) << 6) & 0x00000040)
+#define PHY_BB_RESTART_PWRDROP_LGFIRPWR_DELTA_MSB                                                     11
+#define PHY_BB_RESTART_PWRDROP_LGFIRPWR_DELTA_LSB                                                      7
+#define PHY_BB_RESTART_PWRDROP_LGFIRPWR_DELTA_MASK                                            0x00000f80
+#define PHY_BB_RESTART_PWRDROP_LGFIRPWR_DELTA_GET(x)                           (((x) & 0x00000f80) >> 7)
+#define PHY_BB_RESTART_PWRDROP_LGFIRPWR_DELTA_SET(x)                           (((x) << 7) & 0x00000f80)
+#define PHY_BB_RESTART_OFDM_CCK_RSSI_BIAS_MSB                                                         17
+#define PHY_BB_RESTART_OFDM_CCK_RSSI_BIAS_LSB                                                         12
+#define PHY_BB_RESTART_OFDM_CCK_RSSI_BIAS_MASK                                                0x0003f000
+#define PHY_BB_RESTART_OFDM_CCK_RSSI_BIAS_GET(x)                              (((x) & 0x0003f000) >> 12)
+#define PHY_BB_RESTART_OFDM_CCK_RSSI_BIAS_SET(x)                              (((x) << 12) & 0x0003f000)
+#define PHY_BB_RESTART_ANT_FAST_DIV_GC_LIMIT_MSB                                                      20
+#define PHY_BB_RESTART_ANT_FAST_DIV_GC_LIMIT_LSB                                                      18
+#define PHY_BB_RESTART_ANT_FAST_DIV_GC_LIMIT_MASK                                             0x001c0000
+#define PHY_BB_RESTART_ANT_FAST_DIV_GC_LIMIT_GET(x)                           (((x) & 0x001c0000) >> 18)
+#define PHY_BB_RESTART_ANT_FAST_DIV_GC_LIMIT_SET(x)                           (((x) << 18) & 0x001c0000)
+#define PHY_BB_RESTART_ENABLE_ANT_FAST_DIV_M2FLAG_MSB                                                 21
+#define PHY_BB_RESTART_ENABLE_ANT_FAST_DIV_M2FLAG_LSB                                                 21
+#define PHY_BB_RESTART_ENABLE_ANT_FAST_DIV_M2FLAG_MASK                                        0x00200000
+#define PHY_BB_RESTART_ENABLE_ANT_FAST_DIV_M2FLAG_GET(x)                      (((x) & 0x00200000) >> 21)
+#define PHY_BB_RESTART_ENABLE_ANT_FAST_DIV_M2FLAG_SET(x)                      (((x) << 21) & 0x00200000)
+#define PHY_BB_RESTART_WEAK_RSSI_VOTE_THR_MSB                                                         28
+#define PHY_BB_RESTART_WEAK_RSSI_VOTE_THR_LSB                                                         22
+#define PHY_BB_RESTART_WEAK_RSSI_VOTE_THR_MASK                                                0x1fc00000
+#define PHY_BB_RESTART_WEAK_RSSI_VOTE_THR_GET(x)                              (((x) & 0x1fc00000) >> 22)
+#define PHY_BB_RESTART_WEAK_RSSI_VOTE_THR_SET(x)                              (((x) << 22) & 0x1fc00000)
+#define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_CCK_MSB                                                    29
+#define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_CCK_LSB                                                    29
+#define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_CCK_MASK                                           0x20000000
+#define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_CCK_GET(x)                         (((x) & 0x20000000) >> 29)
+#define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_CCK_SET(x)                         (((x) << 29) & 0x20000000)
+#define PHY_BB_RESTART_DISABLE_DC_RESTART_MSB                                                         30
+#define PHY_BB_RESTART_DISABLE_DC_RESTART_LSB                                                         30
+#define PHY_BB_RESTART_DISABLE_DC_RESTART_MASK                                                0x40000000
+#define PHY_BB_RESTART_DISABLE_DC_RESTART_GET(x)                              (((x) & 0x40000000) >> 30)
+#define PHY_BB_RESTART_DISABLE_DC_RESTART_SET(x)                              (((x) << 30) & 0x40000000)
+#define PHY_BB_RESTART_RESTART_MODE_BW40_MSB                                                          31
+#define PHY_BB_RESTART_RESTART_MODE_BW40_LSB                                                          31
+#define PHY_BB_RESTART_RESTART_MODE_BW40_MASK                                                 0x80000000
+#define PHY_BB_RESTART_RESTART_MODE_BW40_GET(x)                               (((x) & 0x80000000) >> 31)
+#define PHY_BB_RESTART_RESTART_MODE_BW40_SET(x)                               (((x) << 31) & 0x80000000)
+
+/* macros for BB_scrambler_seed */
+#define PHY_BB_SCRAMBLER_SEED_ADDRESS                                                         0x00009978
+#define PHY_BB_SCRAMBLER_SEED_OFFSET                                                          0x00009978
+#define PHY_BB_SCRAMBLER_SEED_FIXED_SCRAMBLER_SEED_MSB                                                 6
+#define PHY_BB_SCRAMBLER_SEED_FIXED_SCRAMBLER_SEED_LSB                                                 0
+#define PHY_BB_SCRAMBLER_SEED_FIXED_SCRAMBLER_SEED_MASK                                       0x0000007f
+#define PHY_BB_SCRAMBLER_SEED_FIXED_SCRAMBLER_SEED_GET(x)                      (((x) & 0x0000007f) >> 0)
+#define PHY_BB_SCRAMBLER_SEED_FIXED_SCRAMBLER_SEED_SET(x)                      (((x) << 0) & 0x0000007f)
+
+/* macros for BB_rfbus_request */
+#define PHY_BB_RFBUS_REQUEST_ADDRESS                                                          0x0000997c
+#define PHY_BB_RFBUS_REQUEST_OFFSET                                                           0x0000997c
+#define PHY_BB_RFBUS_REQUEST_RFBUS_REQUEST_MSB                                                         0
+#define PHY_BB_RFBUS_REQUEST_RFBUS_REQUEST_LSB                                                         0
+#define PHY_BB_RFBUS_REQUEST_RFBUS_REQUEST_MASK                                               0x00000001
+#define PHY_BB_RFBUS_REQUEST_RFBUS_REQUEST_GET(x)                              (((x) & 0x00000001) >> 0)
+#define PHY_BB_RFBUS_REQUEST_RFBUS_REQUEST_SET(x)                              (((x) << 0) & 0x00000001)
+
+/* macros for BB_timing_control_11 */
+#define PHY_BB_TIMING_CONTROL_11_ADDRESS                                                      0x000099a0
+#define PHY_BB_TIMING_CONTROL_11_OFFSET                                                       0x000099a0
+#define PHY_BB_TIMING_CONTROL_11_SPUR_DELTA_PHASE_MSB                                                 19
+#define PHY_BB_TIMING_CONTROL_11_SPUR_DELTA_PHASE_LSB                                                  0
+#define PHY_BB_TIMING_CONTROL_11_SPUR_DELTA_PHASE_MASK                                        0x000fffff
+#define PHY_BB_TIMING_CONTROL_11_SPUR_DELTA_PHASE_GET(x)                       (((x) & 0x000fffff) >> 0)
+#define PHY_BB_TIMING_CONTROL_11_SPUR_DELTA_PHASE_SET(x)                       (((x) << 0) & 0x000fffff)
+#define PHY_BB_TIMING_CONTROL_11_SPUR_FREQ_SD_MSB                                                     29
+#define PHY_BB_TIMING_CONTROL_11_SPUR_FREQ_SD_LSB                                                     20
+#define PHY_BB_TIMING_CONTROL_11_SPUR_FREQ_SD_MASK                                            0x3ff00000
+#define PHY_BB_TIMING_CONTROL_11_SPUR_FREQ_SD_GET(x)                          (((x) & 0x3ff00000) >> 20)
+#define PHY_BB_TIMING_CONTROL_11_SPUR_FREQ_SD_SET(x)                          (((x) << 20) & 0x3ff00000)
+#define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_AGC_MSB                                           30
+#define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_AGC_LSB                                           30
+#define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_AGC_MASK                                  0x40000000
+#define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_AGC_GET(x)                (((x) & 0x40000000) >> 30)
+#define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_AGC_SET(x)                (((x) << 30) & 0x40000000)
+#define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_SELFCOR_MSB                                       31
+#define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_SELFCOR_LSB                                       31
+#define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_SELFCOR_MASK                              0x80000000
+#define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_SELFCOR_GET(x)            (((x) & 0x80000000) >> 31)
+#define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_SELFCOR_SET(x)            (((x) << 31) & 0x80000000)
+
+/* macros for BB_multichain_enable */
+#define PHY_BB_MULTICHAIN_ENABLE_ADDRESS                                                      0x000099a4
+#define PHY_BB_MULTICHAIN_ENABLE_OFFSET                                                       0x000099a4
+#define PHY_BB_MULTICHAIN_ENABLE_RX_CHAIN_MASK_MSB                                                     2
+#define PHY_BB_MULTICHAIN_ENABLE_RX_CHAIN_MASK_LSB                                                     0
+#define PHY_BB_MULTICHAIN_ENABLE_RX_CHAIN_MASK_MASK                                           0x00000007
+#define PHY_BB_MULTICHAIN_ENABLE_RX_CHAIN_MASK_GET(x)                          (((x) & 0x00000007) >> 0)
+#define PHY_BB_MULTICHAIN_ENABLE_RX_CHAIN_MASK_SET(x)                          (((x) << 0) & 0x00000007)
+
+/* macros for BB_multichain_control */
+#define PHY_BB_MULTICHAIN_CONTROL_ADDRESS                                                     0x000099a8
+#define PHY_BB_MULTICHAIN_CONTROL_OFFSET                                                      0x000099a8
+#define PHY_BB_MULTICHAIN_CONTROL_FORCE_ANALOG_GAIN_DIFF_MSB                                           0
+#define PHY_BB_MULTICHAIN_CONTROL_FORCE_ANALOG_GAIN_DIFF_LSB                                           0
+#define PHY_BB_MULTICHAIN_CONTROL_FORCE_ANALOG_GAIN_DIFF_MASK                                 0x00000001
+#define PHY_BB_MULTICHAIN_CONTROL_FORCE_ANALOG_GAIN_DIFF_GET(x)                (((x) & 0x00000001) >> 0)
+#define PHY_BB_MULTICHAIN_CONTROL_FORCE_ANALOG_GAIN_DIFF_SET(x)                (((x) << 0) & 0x00000001)
+#define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_01_MSB                                              7
+#define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_01_LSB                                              1
+#define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_01_MASK                                    0x000000fe
+#define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_01_GET(x)                   (((x) & 0x000000fe) >> 1)
+#define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_01_SET(x)                   (((x) << 1) & 0x000000fe)
+#define PHY_BB_MULTICHAIN_CONTROL_SYNC_SYNTHON_MSB                                                     8
+#define PHY_BB_MULTICHAIN_CONTROL_SYNC_SYNTHON_LSB                                                     8
+#define PHY_BB_MULTICHAIN_CONTROL_SYNC_SYNTHON_MASK                                           0x00000100
+#define PHY_BB_MULTICHAIN_CONTROL_SYNC_SYNTHON_GET(x)                          (((x) & 0x00000100) >> 8)
+#define PHY_BB_MULTICHAIN_CONTROL_SYNC_SYNTHON_SET(x)                          (((x) << 8) & 0x00000100)
+#define PHY_BB_MULTICHAIN_CONTROL_USE_POSEDGE_REFCLK_MSB                                               9
+#define PHY_BB_MULTICHAIN_CONTROL_USE_POSEDGE_REFCLK_LSB                                               9
+#define PHY_BB_MULTICHAIN_CONTROL_USE_POSEDGE_REFCLK_MASK                                     0x00000200
+#define PHY_BB_MULTICHAIN_CONTROL_USE_POSEDGE_REFCLK_GET(x)                    (((x) & 0x00000200) >> 9)
+#define PHY_BB_MULTICHAIN_CONTROL_USE_POSEDGE_REFCLK_SET(x)                    (((x) << 9) & 0x00000200)
+#define PHY_BB_MULTICHAIN_CONTROL_CF_SHORT_SAT_MSB                                                    20
+#define PHY_BB_MULTICHAIN_CONTROL_CF_SHORT_SAT_LSB                                                    10
+#define PHY_BB_MULTICHAIN_CONTROL_CF_SHORT_SAT_MASK                                           0x001ffc00
+#define PHY_BB_MULTICHAIN_CONTROL_CF_SHORT_SAT_GET(x)                         (((x) & 0x001ffc00) >> 10)
+#define PHY_BB_MULTICHAIN_CONTROL_CF_SHORT_SAT_SET(x)                         (((x) << 10) & 0x001ffc00)
+#define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_02_MSB                                             28
+#define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_02_LSB                                             22
+#define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_02_MASK                                    0x1fc00000
+#define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_02_GET(x)                  (((x) & 0x1fc00000) >> 22)
+#define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_02_SET(x)                  (((x) << 22) & 0x1fc00000)
+#define PHY_BB_MULTICHAIN_CONTROL_FORCE_SIGMA_ZERO_MSB                                                29
+#define PHY_BB_MULTICHAIN_CONTROL_FORCE_SIGMA_ZERO_LSB                                                29
+#define PHY_BB_MULTICHAIN_CONTROL_FORCE_SIGMA_ZERO_MASK                                       0x20000000
+#define PHY_BB_MULTICHAIN_CONTROL_FORCE_SIGMA_ZERO_GET(x)                     (((x) & 0x20000000) >> 29)
+#define PHY_BB_MULTICHAIN_CONTROL_FORCE_SIGMA_ZERO_SET(x)                     (((x) << 29) & 0x20000000)
+
+/* macros for BB_multichain_gain_ctrl */
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ADDRESS                                                   0x000099ac
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_OFFSET                                                    0x000099ac
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_QUICKDROP_LOW_MSB                                                  7
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_QUICKDROP_LOW_LSB                                                  0
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_QUICKDROP_LOW_MASK                                        0x000000ff
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_QUICKDROP_LOW_GET(x)                       (((x) & 0x000000ff) >> 0)
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_QUICKDROP_LOW_SET(x)                       (((x) << 0) & 0x000000ff)
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_CHECK_STRONG_ANT_MSB                                        8
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_CHECK_STRONG_ANT_LSB                                        8
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_CHECK_STRONG_ANT_MASK                              0x00000100
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_CHECK_STRONG_ANT_GET(x)             (((x) & 0x00000100) >> 8)
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_CHECK_STRONG_ANT_SET(x)             (((x) << 8) & 0x00000100)
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_FAST_DIV_BIAS_MSB                                             14
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_FAST_DIV_BIAS_LSB                                              9
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_FAST_DIV_BIAS_MASK                                    0x00007e00
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_FAST_DIV_BIAS_GET(x)                   (((x) & 0x00007e00) >> 9)
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_FAST_DIV_BIAS_SET(x)                   (((x) << 9) & 0x00007e00)
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_SNR_MSB                                            20
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_SNR_LSB                                            15
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_SNR_MASK                                   0x001f8000
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_SNR_GET(x)                 (((x) & 0x001f8000) >> 15)
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_SNR_SET(x)                 (((x) << 15) & 0x001f8000)
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_ENA_MSB                                            21
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_ENA_LSB                                            21
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_ENA_MASK                                   0x00200000
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_ENA_GET(x)                 (((x) & 0x00200000) >> 21)
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_ENA_SET(x)                 (((x) << 21) & 0x00200000)
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_MODE_MSB                                           22
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_MODE_LSB                                           22
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_MODE_MASK                                  0x00400000
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_MODE_GET(x)                (((x) & 0x00400000) >> 22)
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_MODE_SET(x)                (((x) << 22) & 0x00400000)
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_SW_RX_PROT_MSB                                         23
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_SW_RX_PROT_LSB                                         23
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_SW_RX_PROT_MASK                                0x00800000
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_SW_RX_PROT_GET(x)              (((x) & 0x00800000) >> 23)
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_SW_RX_PROT_SET(x)              (((x) << 23) & 0x00800000)
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_DIV_LNADIV_MSB                                         24
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_DIV_LNADIV_LSB                                         24
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_DIV_LNADIV_MASK                                0x01000000
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_DIV_LNADIV_GET(x)              (((x) & 0x01000000) >> 24)
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_DIV_LNADIV_SET(x)              (((x) << 24) & 0x01000000)
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_LNACONF_MSB                                           26
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_LNACONF_LSB                                           25
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_LNACONF_MASK                                  0x06000000
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_LNACONF_GET(x)                (((x) & 0x06000000) >> 25)
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_LNACONF_SET(x)                (((x) << 25) & 0x06000000)
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_LNACONF_MSB                                          28
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_LNACONF_LSB                                          27
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_LNACONF_MASK                                 0x18000000
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_LNACONF_GET(x)               (((x) & 0x18000000) >> 27)
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_LNACONF_SET(x)               (((x) << 27) & 0x18000000)
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_GAINTB_MSB                                            29
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_GAINTB_LSB                                            29
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_GAINTB_MASK                                   0x20000000
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_GAINTB_GET(x)                 (((x) & 0x20000000) >> 29)
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_GAINTB_SET(x)                 (((x) << 29) & 0x20000000)
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_GAINTB_MSB                                           30
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_GAINTB_LSB                                           30
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_GAINTB_MASK                                  0x40000000
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_GAINTB_GET(x)                (((x) & 0x40000000) >> 30)
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_GAINTB_SET(x)                (((x) << 30) & 0x40000000)
+
+/* macros for BB_adc_gain_dc_corr_b0 */
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADDRESS                                                    0x000099b4
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_OFFSET                                                     0x000099b4
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_Q_COEFF_0_MSB                                         5
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_Q_COEFF_0_LSB                                         0
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_Q_COEFF_0_MASK                               0x0000003f
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_Q_COEFF_0_GET(x)              (((x) & 0x0000003f) >> 0)
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_Q_COEFF_0_SET(x)              (((x) << 0) & 0x0000003f)
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_I_COEFF_0_MSB                                        11
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_I_COEFF_0_LSB                                         6
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_I_COEFF_0_MASK                               0x00000fc0
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_I_COEFF_0_GET(x)              (((x) & 0x00000fc0) >> 6)
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_I_COEFF_0_SET(x)              (((x) << 6) & 0x00000fc0)
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_Q_COEFF_0_MSB                                          20
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_Q_COEFF_0_LSB                                          12
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_Q_COEFF_0_MASK                                 0x001ff000
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_Q_COEFF_0_GET(x)               (((x) & 0x001ff000) >> 12)
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_Q_COEFF_0_SET(x)               (((x) << 12) & 0x001ff000)
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_I_COEFF_0_MSB                                          29
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_I_COEFF_0_LSB                                          21
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_I_COEFF_0_MASK                                 0x3fe00000
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_I_COEFF_0_GET(x)               (((x) & 0x3fe00000) >> 21)
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_I_COEFF_0_SET(x)               (((x) << 21) & 0x3fe00000)
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_ENABLE_MSB                                           30
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_ENABLE_LSB                                           30
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_ENABLE_MASK                                  0x40000000
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_ENABLE_GET(x)                (((x) & 0x40000000) >> 30)
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_ENABLE_SET(x)                (((x) << 30) & 0x40000000)
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_ENABLE_MSB                                             31
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_ENABLE_LSB                                             31
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_ENABLE_MASK                                    0x80000000
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_ENABLE_GET(x)                  (((x) & 0x80000000) >> 31)
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_ENABLE_SET(x)                  (((x) << 31) & 0x80000000)
+
+/* macros for BB_ext_chan_pwr_thr_1 */
+#define PHY_BB_EXT_CHAN_PWR_THR_1_ADDRESS                                                     0x000099b8
+#define PHY_BB_EXT_CHAN_PWR_THR_1_OFFSET                                                      0x000099b8
+#define PHY_BB_EXT_CHAN_PWR_THR_1_THRESH62_EXT_MSB                                                     7
+#define PHY_BB_EXT_CHAN_PWR_THR_1_THRESH62_EXT_LSB                                                     0
+#define PHY_BB_EXT_CHAN_PWR_THR_1_THRESH62_EXT_MASK                                           0x000000ff
+#define PHY_BB_EXT_CHAN_PWR_THR_1_THRESH62_EXT_GET(x)                          (((x) & 0x000000ff) >> 0)
+#define PHY_BB_EXT_CHAN_PWR_THR_1_THRESH62_EXT_SET(x)                          (((x) << 0) & 0x000000ff)
+#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_MINGAINIDX_MSB                                      15
+#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_MINGAINIDX_LSB                                       8
+#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_MINGAINIDX_MASK                             0x0000ff00
+#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_MINGAINIDX_GET(x)            (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_MINGAINIDX_SET(x)            (((x) << 8) & 0x0000ff00)
+#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTAGAINIDX_MSB                                    20
+#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTAGAINIDX_LSB                                    16
+#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTAGAINIDX_MASK                           0x001f0000
+#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTAGAINIDX_GET(x)         (((x) & 0x001f0000) >> 16)
+#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTAGAINIDX_SET(x)         (((x) << 16) & 0x001f0000)
+#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTANF_MSB                                         26
+#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTANF_LSB                                         21
+#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTANF_MASK                                0x07e00000
+#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTANF_GET(x)              (((x) & 0x07e00000) >> 21)
+#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTANF_SET(x)              (((x) << 21) & 0x07e00000)
+
+/* macros for BB_ext_chan_pwr_thr_2_b0 */
+#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_ADDRESS                                                  0x000099bc
+#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_OFFSET                                                   0x000099bc
+#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CF_MAXCCAPWR_EXT_0_MSB                                            8
+#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CF_MAXCCAPWR_EXT_0_LSB                                            0
+#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CF_MAXCCAPWR_EXT_0_MASK                                  0x000001ff
+#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CF_MAXCCAPWR_EXT_0_GET(x)                 (((x) & 0x000001ff) >> 0)
+#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CF_MAXCCAPWR_EXT_0_SET(x)                 (((x) << 0) & 0x000001ff)
+#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CYCPWR_THR1_EXT_MSB                                              15
+#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CYCPWR_THR1_EXT_LSB                                               9
+#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CYCPWR_THR1_EXT_MASK                                     0x0000fe00
+#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CYCPWR_THR1_EXT_GET(x)                    (((x) & 0x0000fe00) >> 9)
+#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CYCPWR_THR1_EXT_SET(x)                    (((x) << 9) & 0x0000fe00)
+#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_MINCCAPWR_EXT_0_MSB                                              24
+#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_MINCCAPWR_EXT_0_LSB                                              16
+#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_MINCCAPWR_EXT_0_MASK                                     0x01ff0000
+#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_MINCCAPWR_EXT_0_GET(x)                   (((x) & 0x01ff0000) >> 16)
+
+/* macros for BB_ext_chan_scorr_thr */
+#define PHY_BB_EXT_CHAN_SCORR_THR_ADDRESS                                                     0x000099c0
+#define PHY_BB_EXT_CHAN_SCORR_THR_OFFSET                                                      0x000099c0
+#define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_EXT_MSB                                                     6
+#define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_EXT_LSB                                                     0
+#define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_EXT_MASK                                           0x0000007f
+#define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_EXT_GET(x)                          (((x) & 0x0000007f) >> 0)
+#define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_EXT_SET(x)                          (((x) << 0) & 0x0000007f)
+#define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_EXT_MSB                                                    13
+#define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_EXT_LSB                                                     7
+#define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_EXT_MASK                                           0x00003f80
+#define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_EXT_GET(x)                          (((x) & 0x00003f80) >> 7)
+#define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_EXT_SET(x)                          (((x) << 7) & 0x00003f80)
+#define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_LOW_EXT_MSB                                                20
+#define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_LOW_EXT_LSB                                                14
+#define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_LOW_EXT_MASK                                       0x001fc000
+#define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_LOW_EXT_GET(x)                     (((x) & 0x001fc000) >> 14)
+#define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_LOW_EXT_SET(x)                     (((x) << 14) & 0x001fc000)
+#define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_LOW_EXT_MSB                                                27
+#define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_LOW_EXT_LSB                                                21
+#define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_LOW_EXT_MASK                                       0x0fe00000
+#define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_LOW_EXT_GET(x)                     (((x) & 0x0fe00000) >> 21)
+#define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_LOW_EXT_SET(x)                     (((x) << 21) & 0x0fe00000)
+#define PHY_BB_EXT_CHAN_SCORR_THR_SPUR_SUBCHANNEL_SD_MSB                                              28
+#define PHY_BB_EXT_CHAN_SCORR_THR_SPUR_SUBCHANNEL_SD_LSB                                              28
+#define PHY_BB_EXT_CHAN_SCORR_THR_SPUR_SUBCHANNEL_SD_MASK                                     0x10000000
+#define PHY_BB_EXT_CHAN_SCORR_THR_SPUR_SUBCHANNEL_SD_GET(x)                   (((x) & 0x10000000) >> 28)
+#define PHY_BB_EXT_CHAN_SCORR_THR_SPUR_SUBCHANNEL_SD_SET(x)                   (((x) << 28) & 0x10000000)
+
+/* macros for BB_ext_chan_detect_win */
+#define PHY_BB_EXT_CHAN_DETECT_WIN_ADDRESS                                                    0x000099c4
+#define PHY_BB_EXT_CHAN_DETECT_WIN_OFFSET                                                     0x000099c4
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_MSB                                               3
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_LSB                                               0
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_MASK                                     0x0000000f
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_GET(x)                    (((x) & 0x0000000f) >> 0)
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_SET(x)                    (((x) << 0) & 0x0000000f)
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_LOW_MSB                                           7
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_LOW_LSB                                           4
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_LOW_MASK                                 0x000000f0
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_LOW_GET(x)                (((x) & 0x000000f0) >> 4)
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_LOW_SET(x)                (((x) << 4) & 0x000000f0)
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_CCK_MSB                                          12
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_CCK_LSB                                           8
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_CCK_MASK                                 0x00001f00
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_CCK_GET(x)                (((x) & 0x00001f00) >> 8)
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_CCK_SET(x)                (((x) << 8) & 0x00001f00)
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_20H_COUNT_MSB                                                  15
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_20H_COUNT_LSB                                                  13
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_20H_COUNT_MASK                                         0x0000e000
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_20H_COUNT_GET(x)                       (((x) & 0x0000e000) >> 13)
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_20H_COUNT_SET(x)                       (((x) << 13) & 0x0000e000)
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_EXT_BLK_COUNT_MSB                                              18
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_EXT_BLK_COUNT_LSB                                              16
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_EXT_BLK_COUNT_MASK                                     0x00070000
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_EXT_BLK_COUNT_GET(x)                   (((x) & 0x00070000) >> 16)
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_EXT_BLK_COUNT_SET(x)                   (((x) << 16) & 0x00070000)
+#define PHY_BB_EXT_CHAN_DETECT_WIN_WEAK_SIG_THR_CCK_EXT_MSB                                           24
+#define PHY_BB_EXT_CHAN_DETECT_WIN_WEAK_SIG_THR_CCK_EXT_LSB                                           19
+#define PHY_BB_EXT_CHAN_DETECT_WIN_WEAK_SIG_THR_CCK_EXT_MASK                                  0x01f80000
+#define PHY_BB_EXT_CHAN_DETECT_WIN_WEAK_SIG_THR_CCK_EXT_GET(x)                (((x) & 0x01f80000) >> 19)
+#define PHY_BB_EXT_CHAN_DETECT_WIN_WEAK_SIG_THR_CCK_EXT_SET(x)                (((x) << 19) & 0x01f80000)
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_THRESH_MSB                                            28
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_THRESH_LSB                                            25
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_THRESH_MASK                                   0x1e000000
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_THRESH_GET(x)                 (((x) & 0x1e000000) >> 25)
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_THRESH_SET(x)                 (((x) << 25) & 0x1e000000)
+
+/* macros for BB_pwr_thr_20_40_det */
+#define PHY_BB_PWR_THR_20_40_DET_ADDRESS                                                      0x000099c8
+#define PHY_BB_PWR_THR_20_40_DET_OFFSET                                                       0x000099c8
+#define PHY_BB_PWR_THR_20_40_DET_PWRDIFF40_THRSTR_MSB                                                  4
+#define PHY_BB_PWR_THR_20_40_DET_PWRDIFF40_THRSTR_LSB                                                  0
+#define PHY_BB_PWR_THR_20_40_DET_PWRDIFF40_THRSTR_MASK                                        0x0000001f
+#define PHY_BB_PWR_THR_20_40_DET_PWRDIFF40_THRSTR_GET(x)                       (((x) & 0x0000001f) >> 0)
+#define PHY_BB_PWR_THR_20_40_DET_PWRDIFF40_THRSTR_SET(x)                       (((x) << 0) & 0x0000001f)
+#define PHY_BB_PWR_THR_20_40_DET_BLOCKER40_MAX_MSB                                                    10
+#define PHY_BB_PWR_THR_20_40_DET_BLOCKER40_MAX_LSB                                                     5
+#define PHY_BB_PWR_THR_20_40_DET_BLOCKER40_MAX_MASK                                           0x000007e0
+#define PHY_BB_PWR_THR_20_40_DET_BLOCKER40_MAX_GET(x)                          (((x) & 0x000007e0) >> 5)
+#define PHY_BB_PWR_THR_20_40_DET_BLOCKER40_MAX_SET(x)                          (((x) << 5) & 0x000007e0)
+#define PHY_BB_PWR_THR_20_40_DET_DET40_PWRSTEP_MAX_MSB                                                15
+#define PHY_BB_PWR_THR_20_40_DET_DET40_PWRSTEP_MAX_LSB                                                11
+#define PHY_BB_PWR_THR_20_40_DET_DET40_PWRSTEP_MAX_MASK                                       0x0000f800
+#define PHY_BB_PWR_THR_20_40_DET_DET40_PWRSTEP_MAX_GET(x)                     (((x) & 0x0000f800) >> 11)
+#define PHY_BB_PWR_THR_20_40_DET_DET40_PWRSTEP_MAX_SET(x)                     (((x) << 11) & 0x0000f800)
+#define PHY_BB_PWR_THR_20_40_DET_DET40_THR_SNR_MSB                                                    23
+#define PHY_BB_PWR_THR_20_40_DET_DET40_THR_SNR_LSB                                                    16
+#define PHY_BB_PWR_THR_20_40_DET_DET40_THR_SNR_MASK                                           0x00ff0000
+#define PHY_BB_PWR_THR_20_40_DET_DET40_THR_SNR_GET(x)                         (((x) & 0x00ff0000) >> 16)
+#define PHY_BB_PWR_THR_20_40_DET_DET40_THR_SNR_SET(x)                         (((x) << 16) & 0x00ff0000)
+#define PHY_BB_PWR_THR_20_40_DET_DET40_PRI_BIAS_MSB                                                   28
+#define PHY_BB_PWR_THR_20_40_DET_DET40_PRI_BIAS_LSB                                                   24
+#define PHY_BB_PWR_THR_20_40_DET_DET40_PRI_BIAS_MASK                                          0x1f000000
+#define PHY_BB_PWR_THR_20_40_DET_DET40_PRI_BIAS_GET(x)                        (((x) & 0x1f000000) >> 24)
+#define PHY_BB_PWR_THR_20_40_DET_DET40_PRI_BIAS_SET(x)                        (((x) << 24) & 0x1f000000)
+#define PHY_BB_PWR_THR_20_40_DET_PWRSTEP40_ENA_MSB                                                    29
+#define PHY_BB_PWR_THR_20_40_DET_PWRSTEP40_ENA_LSB                                                    29
+#define PHY_BB_PWR_THR_20_40_DET_PWRSTEP40_ENA_MASK                                           0x20000000
+#define PHY_BB_PWR_THR_20_40_DET_PWRSTEP40_ENA_GET(x)                         (((x) & 0x20000000) >> 29)
+#define PHY_BB_PWR_THR_20_40_DET_PWRSTEP40_ENA_SET(x)                         (((x) << 29) & 0x20000000)
+#define PHY_BB_PWR_THR_20_40_DET_LOWSNR40_ENA_MSB                                                     30
+#define PHY_BB_PWR_THR_20_40_DET_LOWSNR40_ENA_LSB                                                     30
+#define PHY_BB_PWR_THR_20_40_DET_LOWSNR40_ENA_MASK                                            0x40000000
+#define PHY_BB_PWR_THR_20_40_DET_LOWSNR40_ENA_GET(x)                          (((x) & 0x40000000) >> 30)
+#define PHY_BB_PWR_THR_20_40_DET_LOWSNR40_ENA_SET(x)                          (((x) << 30) & 0x40000000)
+
+/* macros for BB_short_gi_delta_slope */
+#define PHY_BB_SHORT_GI_DELTA_SLOPE_ADDRESS                                                   0x000099d0
+#define PHY_BB_SHORT_GI_DELTA_SLOPE_OFFSET                                                    0x000099d0
+#define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_EXP_SHORT_GI_MSB                                  3
+#define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_EXP_SHORT_GI_LSB                                  0
+#define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_EXP_SHORT_GI_MASK                        0x0000000f
+#define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_EXP_SHORT_GI_GET(x)       (((x) & 0x0000000f) >> 0)
+#define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_EXP_SHORT_GI_SET(x)       (((x) << 0) & 0x0000000f)
+#define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_MAN_SHORT_GI_MSB                                 18
+#define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_MAN_SHORT_GI_LSB                                  4
+#define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_MAN_SHORT_GI_MASK                        0x0007fff0
+#define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_MAN_SHORT_GI_GET(x)       (((x) & 0x0007fff0) >> 4)
+#define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_MAN_SHORT_GI_SET(x)       (((x) << 4) & 0x0007fff0)
+
+/* macros for BB_chaninfo_ctrl */
+#define PHY_BB_CHANINFO_CTRL_ADDRESS                                                          0x000099dc
+#define PHY_BB_CHANINFO_CTRL_OFFSET                                                           0x000099dc
+#define PHY_BB_CHANINFO_CTRL_CAPTURE_CHAN_INFO_MSB                                                     0
+#define PHY_BB_CHANINFO_CTRL_CAPTURE_CHAN_INFO_LSB                                                     0
+#define PHY_BB_CHANINFO_CTRL_CAPTURE_CHAN_INFO_MASK                                           0x00000001
+#define PHY_BB_CHANINFO_CTRL_CAPTURE_CHAN_INFO_GET(x)                          (((x) & 0x00000001) >> 0)
+#define PHY_BB_CHANINFO_CTRL_CAPTURE_CHAN_INFO_SET(x)                          (((x) << 0) & 0x00000001)
+#define PHY_BB_CHANINFO_CTRL_DISABLE_CHANINFOMEM_MSB                                                   1
+#define PHY_BB_CHANINFO_CTRL_DISABLE_CHANINFOMEM_LSB                                                   1
+#define PHY_BB_CHANINFO_CTRL_DISABLE_CHANINFOMEM_MASK                                         0x00000002
+#define PHY_BB_CHANINFO_CTRL_DISABLE_CHANINFOMEM_GET(x)                        (((x) & 0x00000002) >> 1)
+#define PHY_BB_CHANINFO_CTRL_DISABLE_CHANINFOMEM_SET(x)                        (((x) << 1) & 0x00000002)
+
+/* macros for BB_heavy_clip_ctrl */
+#define PHY_BB_HEAVY_CLIP_CTRL_ADDRESS                                                        0x000099e0
+#define PHY_BB_HEAVY_CLIP_CTRL_OFFSET                                                         0x000099e0
+#define PHY_BB_HEAVY_CLIP_CTRL_CF_HEAVY_CLIP_ENABLE_MSB                                                8
+#define PHY_BB_HEAVY_CLIP_CTRL_CF_HEAVY_CLIP_ENABLE_LSB                                                0
+#define PHY_BB_HEAVY_CLIP_CTRL_CF_HEAVY_CLIP_ENABLE_MASK                                      0x000001ff
+#define PHY_BB_HEAVY_CLIP_CTRL_CF_HEAVY_CLIP_ENABLE_GET(x)                     (((x) & 0x000001ff) >> 0)
+#define PHY_BB_HEAVY_CLIP_CTRL_CF_HEAVY_CLIP_ENABLE_SET(x)                     (((x) << 0) & 0x000001ff)
+#define PHY_BB_HEAVY_CLIP_CTRL_PRE_EMP_HT40_ENABLE_MSB                                                 9
+#define PHY_BB_HEAVY_CLIP_CTRL_PRE_EMP_HT40_ENABLE_LSB                                                 9
+#define PHY_BB_HEAVY_CLIP_CTRL_PRE_EMP_HT40_ENABLE_MASK                                       0x00000200
+#define PHY_BB_HEAVY_CLIP_CTRL_PRE_EMP_HT40_ENABLE_GET(x)                      (((x) & 0x00000200) >> 9)
+#define PHY_BB_HEAVY_CLIP_CTRL_PRE_EMP_HT40_ENABLE_SET(x)                      (((x) << 9) & 0x00000200)
+
+/* macros for BB_heavy_clip_20 */
+#define PHY_BB_HEAVY_CLIP_20_ADDRESS                                                          0x000099e4
+#define PHY_BB_HEAVY_CLIP_20_OFFSET                                                           0x000099e4
+#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_0_MSB                                                   7
+#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_0_LSB                                                   0
+#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_0_MASK                                         0x000000ff
+#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_0_GET(x)                        (((x) & 0x000000ff) >> 0)
+#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_0_SET(x)                        (((x) << 0) & 0x000000ff)
+#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_1_MSB                                                  15
+#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_1_LSB                                                   8
+#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_1_MASK                                         0x0000ff00
+#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_1_GET(x)                        (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_1_SET(x)                        (((x) << 8) & 0x0000ff00)
+#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_2_MSB                                                  23
+#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_2_LSB                                                  16
+#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_2_MASK                                         0x00ff0000
+#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_2_GET(x)                       (((x) & 0x00ff0000) >> 16)
+#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_2_SET(x)                       (((x) << 16) & 0x00ff0000)
+#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_3_MSB                                                  31
+#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_3_LSB                                                  24
+#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_3_MASK                                         0xff000000
+#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_3_GET(x)                       (((x) & 0xff000000) >> 24)
+#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_3_SET(x)                       (((x) << 24) & 0xff000000)
+
+/* macros for BB_heavy_clip_40 */
+#define PHY_BB_HEAVY_CLIP_40_ADDRESS                                                          0x000099e8
+#define PHY_BB_HEAVY_CLIP_40_OFFSET                                                           0x000099e8
+#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_4_MSB                                                   7
+#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_4_LSB                                                   0
+#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_4_MASK                                         0x000000ff
+#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_4_GET(x)                        (((x) & 0x000000ff) >> 0)
+#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_4_SET(x)                        (((x) << 0) & 0x000000ff)
+#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_5_MSB                                                  15
+#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_5_LSB                                                   8
+#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_5_MASK                                         0x0000ff00
+#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_5_GET(x)                        (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_5_SET(x)                        (((x) << 8) & 0x0000ff00)
+#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_6_MSB                                                  23
+#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_6_LSB                                                  16
+#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_6_MASK                                         0x00ff0000
+#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_6_GET(x)                       (((x) & 0x00ff0000) >> 16)
+#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_6_SET(x)                       (((x) << 16) & 0x00ff0000)
+#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_7_MSB                                                  31
+#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_7_LSB                                                  24
+#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_7_MASK                                         0xff000000
+#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_7_GET(x)                       (((x) & 0xff000000) >> 24)
+#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_7_SET(x)                       (((x) << 24) & 0xff000000)
+
+/* macros for BB_rifs_srch */
+#define PHY_BB_RIFS_SRCH_ADDRESS                                                              0x000099ec
+#define PHY_BB_RIFS_SRCH_OFFSET                                                               0x000099ec
+#define PHY_BB_RIFS_SRCH_HEAVY_CLIP_FACTOR_XR_MSB                                                      7
+#define PHY_BB_RIFS_SRCH_HEAVY_CLIP_FACTOR_XR_LSB                                                      0
+#define PHY_BB_RIFS_SRCH_HEAVY_CLIP_FACTOR_XR_MASK                                            0x000000ff
+#define PHY_BB_RIFS_SRCH_HEAVY_CLIP_FACTOR_XR_GET(x)                           (((x) & 0x000000ff) >> 0)
+#define PHY_BB_RIFS_SRCH_HEAVY_CLIP_FACTOR_XR_SET(x)                           (((x) << 0) & 0x000000ff)
+#define PHY_BB_RIFS_SRCH_INIT_GAIN_DB_OFFSET_MSB                                                      15
+#define PHY_BB_RIFS_SRCH_INIT_GAIN_DB_OFFSET_LSB                                                       8
+#define PHY_BB_RIFS_SRCH_INIT_GAIN_DB_OFFSET_MASK                                             0x0000ff00
+#define PHY_BB_RIFS_SRCH_INIT_GAIN_DB_OFFSET_GET(x)                            (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_RIFS_SRCH_INIT_GAIN_DB_OFFSET_SET(x)                            (((x) << 8) & 0x0000ff00)
+#define PHY_BB_RIFS_SRCH_RIFS_INIT_DELAY_MSB                                                          25
+#define PHY_BB_RIFS_SRCH_RIFS_INIT_DELAY_LSB                                                          16
+#define PHY_BB_RIFS_SRCH_RIFS_INIT_DELAY_MASK                                                 0x03ff0000
+#define PHY_BB_RIFS_SRCH_RIFS_INIT_DELAY_GET(x)                               (((x) & 0x03ff0000) >> 16)
+#define PHY_BB_RIFS_SRCH_RIFS_INIT_DELAY_SET(x)                               (((x) << 16) & 0x03ff0000)
+#define PHY_BB_RIFS_SRCH_RIFS_DISABLE_PWRLOW_GC_MSB                                                   26
+#define PHY_BB_RIFS_SRCH_RIFS_DISABLE_PWRLOW_GC_LSB                                                   26
+#define PHY_BB_RIFS_SRCH_RIFS_DISABLE_PWRLOW_GC_MASK                                          0x04000000
+#define PHY_BB_RIFS_SRCH_RIFS_DISABLE_PWRLOW_GC_GET(x)                        (((x) & 0x04000000) >> 26)
+#define PHY_BB_RIFS_SRCH_RIFS_DISABLE_PWRLOW_GC_SET(x)                        (((x) << 26) & 0x04000000)
+#define PHY_BB_RIFS_SRCH_RIFS_DISABLE_CCK_DET_MSB                                                     27
+#define PHY_BB_RIFS_SRCH_RIFS_DISABLE_CCK_DET_LSB                                                     27
+#define PHY_BB_RIFS_SRCH_RIFS_DISABLE_CCK_DET_MASK                                            0x08000000
+#define PHY_BB_RIFS_SRCH_RIFS_DISABLE_CCK_DET_GET(x)                          (((x) & 0x08000000) >> 27)
+#define PHY_BB_RIFS_SRCH_RIFS_DISABLE_CCK_DET_SET(x)                          (((x) << 27) & 0x08000000)
+
+/* macros for BB_iq_adc_cal_mode */
+#define PHY_BB_IQ_ADC_CAL_MODE_ADDRESS                                                        0x000099f0
+#define PHY_BB_IQ_ADC_CAL_MODE_OFFSET                                                         0x000099f0
+#define PHY_BB_IQ_ADC_CAL_MODE_GAIN_DC_IQ_CAL_MODE_MSB                                                 1
+#define PHY_BB_IQ_ADC_CAL_MODE_GAIN_DC_IQ_CAL_MODE_LSB                                                 0
+#define PHY_BB_IQ_ADC_CAL_MODE_GAIN_DC_IQ_CAL_MODE_MASK                                       0x00000003
+#define PHY_BB_IQ_ADC_CAL_MODE_GAIN_DC_IQ_CAL_MODE_GET(x)                      (((x) & 0x00000003) >> 0)
+#define PHY_BB_IQ_ADC_CAL_MODE_GAIN_DC_IQ_CAL_MODE_SET(x)                      (((x) << 0) & 0x00000003)
+#define PHY_BB_IQ_ADC_CAL_MODE_TEST_CALADCOFF_MSB                                                      2
+#define PHY_BB_IQ_ADC_CAL_MODE_TEST_CALADCOFF_LSB                                                      2
+#define PHY_BB_IQ_ADC_CAL_MODE_TEST_CALADCOFF_MASK                                            0x00000004
+#define PHY_BB_IQ_ADC_CAL_MODE_TEST_CALADCOFF_GET(x)                           (((x) & 0x00000004) >> 2)
+#define PHY_BB_IQ_ADC_CAL_MODE_TEST_CALADCOFF_SET(x)                           (((x) << 2) & 0x00000004)
+
+/* macros for BB_per_chain_csd */
+#define PHY_BB_PER_CHAIN_CSD_ADDRESS                                                          0x000099fc
+#define PHY_BB_PER_CHAIN_CSD_OFFSET                                                           0x000099fc
+#define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_2CHAINS_MSB                                                      4
+#define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_2CHAINS_LSB                                                      0
+#define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_2CHAINS_MASK                                            0x0000001f
+#define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_2CHAINS_GET(x)                           (((x) & 0x0000001f) >> 0)
+#define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_2CHAINS_SET(x)                           (((x) << 0) & 0x0000001f)
+#define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_3CHAINS_MSB                                                      9
+#define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_3CHAINS_LSB                                                      5
+#define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_3CHAINS_MASK                                            0x000003e0
+#define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_3CHAINS_GET(x)                           (((x) & 0x000003e0) >> 5)
+#define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_3CHAINS_SET(x)                           (((x) << 5) & 0x000003e0)
+#define PHY_BB_PER_CHAIN_CSD_CSD_CHN2_3CHAINS_MSB                                                     14
+#define PHY_BB_PER_CHAIN_CSD_CSD_CHN2_3CHAINS_LSB                                                     10
+#define PHY_BB_PER_CHAIN_CSD_CSD_CHN2_3CHAINS_MASK                                            0x00007c00
+#define PHY_BB_PER_CHAIN_CSD_CSD_CHN2_3CHAINS_GET(x)                          (((x) & 0x00007c00) >> 10)
+#define PHY_BB_PER_CHAIN_CSD_CSD_CHN2_3CHAINS_SET(x)                          (((x) << 10) & 0x00007c00)
+
+/* macros for BB_rx_ocgain */
+#define PHY_BB_RX_OCGAIN_ADDRESS                                                              0x00009a00
+#define PHY_BB_RX_OCGAIN_OFFSET                                                               0x00009a00
+#define PHY_BB_RX_OCGAIN_GAIN_ENTRY_MSB                                                               31
+#define PHY_BB_RX_OCGAIN_GAIN_ENTRY_LSB                                                                0
+#define PHY_BB_RX_OCGAIN_GAIN_ENTRY_MASK                                                      0xffffffff
+#define PHY_BB_RX_OCGAIN_GAIN_ENTRY_SET(x)                                     (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_crc */
+#define PHY_BB_TX_CRC_ADDRESS                                                                 0x00009c00
+#define PHY_BB_TX_CRC_OFFSET                                                                  0x00009c00
+#define PHY_BB_TX_CRC_TX_CRC_MSB                                                                      15
+#define PHY_BB_TX_CRC_TX_CRC_LSB                                                                       0
+#define PHY_BB_TX_CRC_TX_CRC_MASK                                                             0x0000ffff
+#define PHY_BB_TX_CRC_TX_CRC_GET(x)                                            (((x) & 0x0000ffff) >> 0)
+
+/* macros for BB_iq_adc_meas_0_b0 */
+#define PHY_BB_IQ_ADC_MEAS_0_B0_ADDRESS                                                       0x00009c10
+#define PHY_BB_IQ_ADC_MEAS_0_B0_OFFSET                                                        0x00009c10
+#define PHY_BB_IQ_ADC_MEAS_0_B0_GAIN_DC_IQ_CAL_MEAS_0_0_MSB                                           31
+#define PHY_BB_IQ_ADC_MEAS_0_B0_GAIN_DC_IQ_CAL_MEAS_0_0_LSB                                            0
+#define PHY_BB_IQ_ADC_MEAS_0_B0_GAIN_DC_IQ_CAL_MEAS_0_0_MASK                                  0xffffffff
+#define PHY_BB_IQ_ADC_MEAS_0_B0_GAIN_DC_IQ_CAL_MEAS_0_0_GET(x)                 (((x) & 0xffffffff) >> 0)
+
+/* macros for BB_iq_adc_meas_1_b0 */
+#define PHY_BB_IQ_ADC_MEAS_1_B0_ADDRESS                                                       0x00009c14
+#define PHY_BB_IQ_ADC_MEAS_1_B0_OFFSET                                                        0x00009c14
+#define PHY_BB_IQ_ADC_MEAS_1_B0_GAIN_DC_IQ_CAL_MEAS_1_0_MSB                                           31
+#define PHY_BB_IQ_ADC_MEAS_1_B0_GAIN_DC_IQ_CAL_MEAS_1_0_LSB                                            0
+#define PHY_BB_IQ_ADC_MEAS_1_B0_GAIN_DC_IQ_CAL_MEAS_1_0_MASK                                  0xffffffff
+#define PHY_BB_IQ_ADC_MEAS_1_B0_GAIN_DC_IQ_CAL_MEAS_1_0_GET(x)                 (((x) & 0xffffffff) >> 0)
+
+/* macros for BB_iq_adc_meas_2_b0 */
+#define PHY_BB_IQ_ADC_MEAS_2_B0_ADDRESS                                                       0x00009c18
+#define PHY_BB_IQ_ADC_MEAS_2_B0_OFFSET                                                        0x00009c18
+#define PHY_BB_IQ_ADC_MEAS_2_B0_GAIN_DC_IQ_CAL_MEAS_2_0_MSB                                           31
+#define PHY_BB_IQ_ADC_MEAS_2_B0_GAIN_DC_IQ_CAL_MEAS_2_0_LSB                                            0
+#define PHY_BB_IQ_ADC_MEAS_2_B0_GAIN_DC_IQ_CAL_MEAS_2_0_MASK                                  0xffffffff
+#define PHY_BB_IQ_ADC_MEAS_2_B0_GAIN_DC_IQ_CAL_MEAS_2_0_GET(x)                 (((x) & 0xffffffff) >> 0)
+
+/* macros for BB_iq_adc_meas_3_b0 */
+#define PHY_BB_IQ_ADC_MEAS_3_B0_ADDRESS                                                       0x00009c1c
+#define PHY_BB_IQ_ADC_MEAS_3_B0_OFFSET                                                        0x00009c1c
+#define PHY_BB_IQ_ADC_MEAS_3_B0_GAIN_DC_IQ_CAL_MEAS_3_0_MSB                                           31
+#define PHY_BB_IQ_ADC_MEAS_3_B0_GAIN_DC_IQ_CAL_MEAS_3_0_LSB                                            0
+#define PHY_BB_IQ_ADC_MEAS_3_B0_GAIN_DC_IQ_CAL_MEAS_3_0_MASK                                  0xffffffff
+#define PHY_BB_IQ_ADC_MEAS_3_B0_GAIN_DC_IQ_CAL_MEAS_3_0_GET(x)                 (((x) & 0xffffffff) >> 0)
+
+/* macros for BB_rfbus_grant */
+#define PHY_BB_RFBUS_GRANT_ADDRESS                                                            0x00009c20
+#define PHY_BB_RFBUS_GRANT_OFFSET                                                             0x00009c20
+#define PHY_BB_RFBUS_GRANT_RFBUS_GRANT_MSB                                                             0
+#define PHY_BB_RFBUS_GRANT_RFBUS_GRANT_LSB                                                             0
+#define PHY_BB_RFBUS_GRANT_RFBUS_GRANT_MASK                                                   0x00000001
+#define PHY_BB_RFBUS_GRANT_RFBUS_GRANT_GET(x)                                  (((x) & 0x00000001) >> 0)
+#define PHY_BB_RFBUS_GRANT_BT_ANT_MSB                                                                  1
+#define PHY_BB_RFBUS_GRANT_BT_ANT_LSB                                                                  1
+#define PHY_BB_RFBUS_GRANT_BT_ANT_MASK                                                        0x00000002
+#define PHY_BB_RFBUS_GRANT_BT_ANT_GET(x)                                       (((x) & 0x00000002) >> 1)
+
+/* macros for BB_tstadc */
+#define PHY_BB_TSTADC_ADDRESS                                                                 0x00009c24
+#define PHY_BB_TSTADC_OFFSET                                                                  0x00009c24
+#define PHY_BB_TSTADC_TSTADC_OUT_Q_MSB                                                                 9
+#define PHY_BB_TSTADC_TSTADC_OUT_Q_LSB                                                                 0
+#define PHY_BB_TSTADC_TSTADC_OUT_Q_MASK                                                       0x000003ff
+#define PHY_BB_TSTADC_TSTADC_OUT_Q_GET(x)                                      (((x) & 0x000003ff) >> 0)
+#define PHY_BB_TSTADC_TSTADC_OUT_I_MSB                                                                19
+#define PHY_BB_TSTADC_TSTADC_OUT_I_LSB                                                                10
+#define PHY_BB_TSTADC_TSTADC_OUT_I_MASK                                                       0x000ffc00
+#define PHY_BB_TSTADC_TSTADC_OUT_I_GET(x)                                     (((x) & 0x000ffc00) >> 10)
+
+/* macros for BB_tstdac */
+#define PHY_BB_TSTDAC_ADDRESS                                                                 0x00009c28
+#define PHY_BB_TSTDAC_OFFSET                                                                  0x00009c28
+#define PHY_BB_TSTDAC_TSTDAC_OUT_Q_MSB                                                                 9
+#define PHY_BB_TSTDAC_TSTDAC_OUT_Q_LSB                                                                 0
+#define PHY_BB_TSTDAC_TSTDAC_OUT_Q_MASK                                                       0x000003ff
+#define PHY_BB_TSTDAC_TSTDAC_OUT_Q_GET(x)                                      (((x) & 0x000003ff) >> 0)
+#define PHY_BB_TSTDAC_TSTDAC_OUT_I_MSB                                                                19
+#define PHY_BB_TSTDAC_TSTDAC_OUT_I_LSB                                                                10
+#define PHY_BB_TSTDAC_TSTDAC_OUT_I_MASK                                                       0x000ffc00
+#define PHY_BB_TSTDAC_TSTDAC_OUT_I_GET(x)                                     (((x) & 0x000ffc00) >> 10)
+
+/* macros for BB_illegal_tx_rate */
+#define PHY_BB_ILLEGAL_TX_RATE_ADDRESS                                                        0x00009c30
+#define PHY_BB_ILLEGAL_TX_RATE_OFFSET                                                         0x00009c30
+#define PHY_BB_ILLEGAL_TX_RATE_ILLEGAL_TX_RATE_MSB                                                     0
+#define PHY_BB_ILLEGAL_TX_RATE_ILLEGAL_TX_RATE_LSB                                                     0
+#define PHY_BB_ILLEGAL_TX_RATE_ILLEGAL_TX_RATE_MASK                                           0x00000001
+#define PHY_BB_ILLEGAL_TX_RATE_ILLEGAL_TX_RATE_GET(x)                          (((x) & 0x00000001) >> 0)
+
+/* macros for BB_spur_report_b0 */
+#define PHY_BB_SPUR_REPORT_B0_ADDRESS                                                         0x00009c34
+#define PHY_BB_SPUR_REPORT_B0_OFFSET                                                          0x00009c34
+#define PHY_BB_SPUR_REPORT_B0_SPUR_EST_I_0_MSB                                                         7
+#define PHY_BB_SPUR_REPORT_B0_SPUR_EST_I_0_LSB                                                         0
+#define PHY_BB_SPUR_REPORT_B0_SPUR_EST_I_0_MASK                                               0x000000ff
+#define PHY_BB_SPUR_REPORT_B0_SPUR_EST_I_0_GET(x)                              (((x) & 0x000000ff) >> 0)
+#define PHY_BB_SPUR_REPORT_B0_SPUR_EST_Q_0_MSB                                                        15
+#define PHY_BB_SPUR_REPORT_B0_SPUR_EST_Q_0_LSB                                                         8
+#define PHY_BB_SPUR_REPORT_B0_SPUR_EST_Q_0_MASK                                               0x0000ff00
+#define PHY_BB_SPUR_REPORT_B0_SPUR_EST_Q_0_GET(x)                              (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_SPUR_REPORT_B0_POWER_WITH_SPUR_REMOVED_0_MSB                                           31
+#define PHY_BB_SPUR_REPORT_B0_POWER_WITH_SPUR_REMOVED_0_LSB                                           16
+#define PHY_BB_SPUR_REPORT_B0_POWER_WITH_SPUR_REMOVED_0_MASK                                  0xffff0000
+#define PHY_BB_SPUR_REPORT_B0_POWER_WITH_SPUR_REMOVED_0_GET(x)                (((x) & 0xffff0000) >> 16)
+
+/* macros for BB_channel_status */
+#define PHY_BB_CHANNEL_STATUS_ADDRESS                                                         0x00009c38
+#define PHY_BB_CHANNEL_STATUS_OFFSET                                                          0x00009c38
+#define PHY_BB_CHANNEL_STATUS_BT_ACTIVE_MSB                                                            0
+#define PHY_BB_CHANNEL_STATUS_BT_ACTIVE_LSB                                                            0
+#define PHY_BB_CHANNEL_STATUS_BT_ACTIVE_MASK                                                  0x00000001
+#define PHY_BB_CHANNEL_STATUS_BT_ACTIVE_GET(x)                                 (((x) & 0x00000001) >> 0)
+#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_RAW_MSB                                                         1
+#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_RAW_LSB                                                         1
+#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_RAW_MASK                                               0x00000002
+#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_RAW_GET(x)                              (((x) & 0x00000002) >> 1)
+#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_MAC_MSB                                                         2
+#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_MAC_LSB                                                         2
+#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_MAC_MASK                                               0x00000004
+#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_MAC_GET(x)                              (((x) & 0x00000004) >> 2)
+#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_PAD_MSB                                                         3
+#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_PAD_LSB                                                         3
+#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_PAD_MASK                                               0x00000008
+#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_PAD_GET(x)                              (((x) & 0x00000008) >> 3)
+#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_0_MSB                                                          5
+#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_0_LSB                                                          4
+#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_0_MASK                                                0x00000030
+#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_0_GET(x)                               (((x) & 0x00000030) >> 4)
+#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_1_MSB                                                          7
+#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_1_LSB                                                          6
+#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_1_MASK                                                0x000000c0
+#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_1_GET(x)                               (((x) & 0x000000c0) >> 6)
+#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_2_MSB                                                          9
+#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_2_LSB                                                          8
+#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_2_MASK                                                0x00000300
+#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_2_GET(x)                               (((x) & 0x00000300) >> 8)
+#define PHY_BB_CHANNEL_STATUS_BB_SW_COM_OUT_MSB                                                       13
+#define PHY_BB_CHANNEL_STATUS_BB_SW_COM_OUT_LSB                                                       10
+#define PHY_BB_CHANNEL_STATUS_BB_SW_COM_OUT_MASK                                              0x00003c00
+#define PHY_BB_CHANNEL_STATUS_BB_SW_COM_OUT_GET(x)                            (((x) & 0x00003c00) >> 10)
+#define PHY_BB_CHANNEL_STATUS_ANT_DIV_CFG_USED_MSB                                                    16
+#define PHY_BB_CHANNEL_STATUS_ANT_DIV_CFG_USED_LSB                                                    14
+#define PHY_BB_CHANNEL_STATUS_ANT_DIV_CFG_USED_MASK                                           0x0001c000
+#define PHY_BB_CHANNEL_STATUS_ANT_DIV_CFG_USED_GET(x)                         (((x) & 0x0001c000) >> 14)
+
+/* macros for BB_rssi_b0 */
+#define PHY_BB_RSSI_B0_ADDRESS                                                                0x00009c3c
+#define PHY_BB_RSSI_B0_OFFSET                                                                 0x00009c3c
+#define PHY_BB_RSSI_B0_RSSI_0_MSB                                                                      7
+#define PHY_BB_RSSI_B0_RSSI_0_LSB                                                                      0
+#define PHY_BB_RSSI_B0_RSSI_0_MASK                                                            0x000000ff
+#define PHY_BB_RSSI_B0_RSSI_0_GET(x)                                           (((x) & 0x000000ff) >> 0)
+#define PHY_BB_RSSI_B0_RSSI_EXT_0_MSB                                                                 15
+#define PHY_BB_RSSI_B0_RSSI_EXT_0_LSB                                                                  8
+#define PHY_BB_RSSI_B0_RSSI_EXT_0_MASK                                                        0x0000ff00
+#define PHY_BB_RSSI_B0_RSSI_EXT_0_GET(x)                                       (((x) & 0x0000ff00) >> 8)
+
+/* macros for BB_spur_est_cck_report_b0 */
+#define PHY_BB_SPUR_EST_CCK_REPORT_B0_ADDRESS                                                 0x00009c40
+#define PHY_BB_SPUR_EST_CCK_REPORT_B0_OFFSET                                                  0x00009c40
+#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_SD_I_0_CCK_MSB                                          7
+#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_SD_I_0_CCK_LSB                                          0
+#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_SD_I_0_CCK_MASK                                0x000000ff
+#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_SD_I_0_CCK_GET(x)               (((x) & 0x000000ff) >> 0)
+#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_SD_Q_0_CCK_MSB                                         15
+#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_SD_Q_0_CCK_LSB                                          8
+#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_SD_Q_0_CCK_MASK                                0x0000ff00
+#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_SD_Q_0_CCK_GET(x)               (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_I_0_CCK_MSB                                            23
+#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_I_0_CCK_LSB                                            16
+#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_I_0_CCK_MASK                                   0x00ff0000
+#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_I_0_CCK_GET(x)                 (((x) & 0x00ff0000) >> 16)
+#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_Q_0_CCK_MSB                                            31
+#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_Q_0_CCK_LSB                                            24
+#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_Q_0_CCK_MASK                                   0xff000000
+#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_Q_0_CCK_GET(x)                 (((x) & 0xff000000) >> 24)
+
+/* macros for BB_chan_info_noise_pwr */
+#define PHY_BB_CHAN_INFO_NOISE_PWR_ADDRESS                                                    0x00009cac
+#define PHY_BB_CHAN_INFO_NOISE_PWR_OFFSET                                                     0x00009cac
+#define PHY_BB_CHAN_INFO_NOISE_PWR_NOISE_POWER_MSB                                                    11
+#define PHY_BB_CHAN_INFO_NOISE_PWR_NOISE_POWER_LSB                                                     0
+#define PHY_BB_CHAN_INFO_NOISE_PWR_NOISE_POWER_MASK                                           0x00000fff
+#define PHY_BB_CHAN_INFO_NOISE_PWR_NOISE_POWER_GET(x)                          (((x) & 0x00000fff) >> 0)
+
+/* macros for BB_chan_info_gain_diff */
+#define PHY_BB_CHAN_INFO_GAIN_DIFF_ADDRESS                                                    0x00009cb0
+#define PHY_BB_CHAN_INFO_GAIN_DIFF_OFFSET                                                     0x00009cb0
+#define PHY_BB_CHAN_INFO_GAIN_DIFF_FINE_PPM_MSB                                                       11
+#define PHY_BB_CHAN_INFO_GAIN_DIFF_FINE_PPM_LSB                                                        0
+#define PHY_BB_CHAN_INFO_GAIN_DIFF_FINE_PPM_MASK                                              0x00000fff
+#define PHY_BB_CHAN_INFO_GAIN_DIFF_FINE_PPM_GET(x)                             (((x) & 0x00000fff) >> 0)
+
+/* macros for BB_chan_info_fine_timing */
+#define PHY_BB_CHAN_INFO_FINE_TIMING_ADDRESS                                                  0x00009cb4
+#define PHY_BB_CHAN_INFO_FINE_TIMING_OFFSET                                                   0x00009cb4
+#define PHY_BB_CHAN_INFO_FINE_TIMING_COARSE_PPM_MSB                                                   11
+#define PHY_BB_CHAN_INFO_FINE_TIMING_COARSE_PPM_LSB                                                    0
+#define PHY_BB_CHAN_INFO_FINE_TIMING_COARSE_PPM_MASK                                          0x00000fff
+#define PHY_BB_CHAN_INFO_FINE_TIMING_COARSE_PPM_GET(x)                         (((x) & 0x00000fff) >> 0)
+#define PHY_BB_CHAN_INFO_FINE_TIMING_FINE_TIMING_MSB                                                  21
+#define PHY_BB_CHAN_INFO_FINE_TIMING_FINE_TIMING_LSB                                                  12
+#define PHY_BB_CHAN_INFO_FINE_TIMING_FINE_TIMING_MASK                                         0x003ff000
+#define PHY_BB_CHAN_INFO_FINE_TIMING_FINE_TIMING_GET(x)                       (((x) & 0x003ff000) >> 12)
+
+/* macros for BB_chan_info_gain_b0 */
+#define PHY_BB_CHAN_INFO_GAIN_B0_ADDRESS                                                      0x00009cb8
+#define PHY_BB_CHAN_INFO_GAIN_B0_OFFSET                                                       0x00009cb8
+#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RSSI_0_MSB                                                  7
+#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RSSI_0_LSB                                                  0
+#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RSSI_0_MASK                                        0x000000ff
+#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RSSI_0_GET(x)                       (((x) & 0x000000ff) >> 0)
+#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RF_GAIN_0_MSB                                              15
+#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RF_GAIN_0_LSB                                               8
+#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RF_GAIN_0_MASK                                     0x0000ff00
+#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RF_GAIN_0_GET(x)                    (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN1_SW_0_MSB                                           16
+#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN1_SW_0_LSB                                           16
+#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN1_SW_0_MASK                                  0x00010000
+#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN1_SW_0_GET(x)                (((x) & 0x00010000) >> 16)
+#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN2_SW_0_MSB                                           17
+#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN2_SW_0_LSB                                           17
+#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN2_SW_0_MASK                                  0x00020000
+#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN2_SW_0_GET(x)                (((x) & 0x00020000) >> 17)
+
+/* macros for BB_chan_info_chan_tab_b0 */
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_ADDRESS                                                  0x00009cbc
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_OFFSET                                                   0x00009cbc
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_Q_0_MSB                                                       5
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_Q_0_LSB                                                       0
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_Q_0_MASK                                             0x0000003f
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_Q_0_GET(x)                            (((x) & 0x0000003f) >> 0)
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_I_0_MSB                                                      11
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_I_0_LSB                                                       6
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_I_0_MASK                                             0x00000fc0
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_I_0_GET(x)                            (((x) & 0x00000fc0) >> 6)
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_EXP_0_MSB                                                        15
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_EXP_0_LSB                                                        12
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_EXP_0_MASK                                               0x0000f000
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_EXP_0_GET(x)                             (((x) & 0x0000f000) >> 12)
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_Q_1_MSB                                                      21
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_Q_1_LSB                                                      16
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_Q_1_MASK                                             0x003f0000
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_Q_1_GET(x)                           (((x) & 0x003f0000) >> 16)
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_I_1_MSB                                                      27
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_I_1_LSB                                                      22
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_I_1_MASK                                             0x0fc00000
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_I_1_GET(x)                           (((x) & 0x0fc00000) >> 22)
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_EXP_1_MSB                                                        31
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_EXP_1_LSB                                                        28
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_EXP_1_MASK                                               0xf0000000
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_EXP_1_GET(x)                             (((x) & 0xf0000000) >> 28)
+
+/* macros for BB_paprd_am2am_mask */
+#define PHY_BB_PAPRD_AM2AM_MASK_ADDRESS                                                       0x00009de4
+#define PHY_BB_PAPRD_AM2AM_MASK_OFFSET                                                        0x00009de4
+#define PHY_BB_PAPRD_AM2AM_MASK_PAPRD_AM2AM_MASK_MSB                                                  24
+#define PHY_BB_PAPRD_AM2AM_MASK_PAPRD_AM2AM_MASK_LSB                                                   0
+#define PHY_BB_PAPRD_AM2AM_MASK_PAPRD_AM2AM_MASK_MASK                                         0x01ffffff
+#define PHY_BB_PAPRD_AM2AM_MASK_PAPRD_AM2AM_MASK_GET(x)                        (((x) & 0x01ffffff) >> 0)
+#define PHY_BB_PAPRD_AM2AM_MASK_PAPRD_AM2AM_MASK_SET(x)                        (((x) << 0) & 0x01ffffff)
+
+/* macros for BB_paprd_am2pm_mask */
+#define PHY_BB_PAPRD_AM2PM_MASK_ADDRESS                                                       0x00009de8
+#define PHY_BB_PAPRD_AM2PM_MASK_OFFSET                                                        0x00009de8
+#define PHY_BB_PAPRD_AM2PM_MASK_PAPRD_AM2PM_MASK_MSB                                                  24
+#define PHY_BB_PAPRD_AM2PM_MASK_PAPRD_AM2PM_MASK_LSB                                                   0
+#define PHY_BB_PAPRD_AM2PM_MASK_PAPRD_AM2PM_MASK_MASK                                         0x01ffffff
+#define PHY_BB_PAPRD_AM2PM_MASK_PAPRD_AM2PM_MASK_GET(x)                        (((x) & 0x01ffffff) >> 0)
+#define PHY_BB_PAPRD_AM2PM_MASK_PAPRD_AM2PM_MASK_SET(x)                        (((x) << 0) & 0x01ffffff)
+
+/* macros for BB_paprd_ht40_mask */
+#define PHY_BB_PAPRD_HT40_MASK_ADDRESS                                                        0x00009dec
+#define PHY_BB_PAPRD_HT40_MASK_OFFSET                                                         0x00009dec
+#define PHY_BB_PAPRD_HT40_MASK_PAPRD_HT40_MASK_MSB                                                    24
+#define PHY_BB_PAPRD_HT40_MASK_PAPRD_HT40_MASK_LSB                                                     0
+#define PHY_BB_PAPRD_HT40_MASK_PAPRD_HT40_MASK_MASK                                           0x01ffffff
+#define PHY_BB_PAPRD_HT40_MASK_PAPRD_HT40_MASK_GET(x)                          (((x) & 0x01ffffff) >> 0)
+#define PHY_BB_PAPRD_HT40_MASK_PAPRD_HT40_MASK_SET(x)                          (((x) << 0) & 0x01ffffff)
+
+/* macros for BB_paprd_ctrl0 */
+#define PHY_BB_PAPRD_CTRL0_ADDRESS                                                            0x00009df0
+#define PHY_BB_PAPRD_CTRL0_OFFSET                                                             0x00009df0
+#define PHY_BB_PAPRD_CTRL0_PAPRD_ENABLE_MSB                                                            0
+#define PHY_BB_PAPRD_CTRL0_PAPRD_ENABLE_LSB                                                            0
+#define PHY_BB_PAPRD_CTRL0_PAPRD_ENABLE_MASK                                                  0x00000001
+#define PHY_BB_PAPRD_CTRL0_PAPRD_ENABLE_GET(x)                                 (((x) & 0x00000001) >> 0)
+#define PHY_BB_PAPRD_CTRL0_PAPRD_ENABLE_SET(x)                                 (((x) << 0) & 0x00000001)
+#define PHY_BB_PAPRD_CTRL0_PAPRD_ADAPTIVE_USE_SINGLE_TABLE_MSB                                         1
+#define PHY_BB_PAPRD_CTRL0_PAPRD_ADAPTIVE_USE_SINGLE_TABLE_LSB                                         1
+#define PHY_BB_PAPRD_CTRL0_PAPRD_ADAPTIVE_USE_SINGLE_TABLE_MASK                               0x00000002
+#define PHY_BB_PAPRD_CTRL0_PAPRD_ADAPTIVE_USE_SINGLE_TABLE_GET(x)              (((x) & 0x00000002) >> 1)
+#define PHY_BB_PAPRD_CTRL0_PAPRD_ADAPTIVE_USE_SINGLE_TABLE_SET(x)              (((x) << 1) & 0x00000002)
+#define PHY_BB_PAPRD_CTRL0_PAPRD_VALID_GAIN_MSB                                                       26
+#define PHY_BB_PAPRD_CTRL0_PAPRD_VALID_GAIN_LSB                                                        2
+#define PHY_BB_PAPRD_CTRL0_PAPRD_VALID_GAIN_MASK                                              0x07fffffc
+#define PHY_BB_PAPRD_CTRL0_PAPRD_VALID_GAIN_GET(x)                             (((x) & 0x07fffffc) >> 2)
+#define PHY_BB_PAPRD_CTRL0_PAPRD_VALID_GAIN_SET(x)                             (((x) << 2) & 0x07fffffc)
+#define PHY_BB_PAPRD_CTRL0_PAPRD_MAG_THRSH_MSB                                                        31
+#define PHY_BB_PAPRD_CTRL0_PAPRD_MAG_THRSH_LSB                                                        27
+#define PHY_BB_PAPRD_CTRL0_PAPRD_MAG_THRSH_MASK                                               0xf8000000
+#define PHY_BB_PAPRD_CTRL0_PAPRD_MAG_THRSH_GET(x)                             (((x) & 0xf8000000) >> 27)
+#define PHY_BB_PAPRD_CTRL0_PAPRD_MAG_THRSH_SET(x)                             (((x) << 27) & 0xf8000000)
+
+/* macros for BB_paprd_ctrl1 */
+#define PHY_BB_PAPRD_CTRL1_ADDRESS                                                            0x00009df4
+#define PHY_BB_PAPRD_CTRL1_OFFSET                                                             0x00009df4
+#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_SCALING_ENABLE_MSB                                           0
+#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_SCALING_ENABLE_LSB                                           0
+#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_SCALING_ENABLE_MASK                                 0x00000001
+#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_SCALING_ENABLE_GET(x)                (((x) & 0x00000001) >> 0)
+#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_SCALING_ENABLE_SET(x)                (((x) << 0) & 0x00000001)
+#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2AM_ENABLE_MSB                                             1
+#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2AM_ENABLE_LSB                                             1
+#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2AM_ENABLE_MASK                                   0x00000002
+#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2AM_ENABLE_GET(x)                  (((x) & 0x00000002) >> 1)
+#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2AM_ENABLE_SET(x)                  (((x) << 1) & 0x00000002)
+#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2PM_ENABLE_MSB                                             2
+#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2PM_ENABLE_LSB                                             2
+#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2PM_ENABLE_MASK                                   0x00000004
+#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2PM_ENABLE_GET(x)                  (((x) & 0x00000004) >> 2)
+#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2PM_ENABLE_SET(x)                  (((x) << 2) & 0x00000004)
+#define PHY_BB_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL_MSB                                                8
+#define PHY_BB_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL_LSB                                                3
+#define PHY_BB_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL_MASK                                      0x000001f8
+#define PHY_BB_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL_GET(x)                     (((x) & 0x000001f8) >> 3)
+#define PHY_BB_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL_SET(x)                     (((x) << 3) & 0x000001f8)
+#define PHY_BB_PAPRD_CTRL1_PA_GAIN_SCALE_FACTOR_MSB                                                   16
+#define PHY_BB_PAPRD_CTRL1_PA_GAIN_SCALE_FACTOR_LSB                                                    9
+#define PHY_BB_PAPRD_CTRL1_PA_GAIN_SCALE_FACTOR_MASK                                          0x0001fe00
+#define PHY_BB_PAPRD_CTRL1_PA_GAIN_SCALE_FACTOR_GET(x)                         (((x) & 0x0001fe00) >> 9)
+#define PHY_BB_PAPRD_CTRL1_PA_GAIN_SCALE_FACTOR_SET(x)                         (((x) << 9) & 0x0001fe00)
+#define PHY_BB_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACTOR_MSB                                                 26
+#define PHY_BB_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACTOR_LSB                                                 17
+#define PHY_BB_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACTOR_MASK                                        0x07fe0000
+#define PHY_BB_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACTOR_GET(x)                      (((x) & 0x07fe0000) >> 17)
+#define PHY_BB_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACTOR_SET(x)                      (((x) << 17) & 0x07fe0000)
+#define PHY_BB_PAPRD_CTRL1_PAPRD_TRAINER_IANDQ_SEL_MSB                                                27
+#define PHY_BB_PAPRD_CTRL1_PAPRD_TRAINER_IANDQ_SEL_LSB                                                27
+#define PHY_BB_PAPRD_CTRL1_PAPRD_TRAINER_IANDQ_SEL_MASK                                       0x08000000
+#define PHY_BB_PAPRD_CTRL1_PAPRD_TRAINER_IANDQ_SEL_GET(x)                     (((x) & 0x08000000) >> 27)
+#define PHY_BB_PAPRD_CTRL1_PAPRD_TRAINER_IANDQ_SEL_SET(x)                     (((x) << 27) & 0x08000000)
+
+/* macros for BB_pa_gain123 */
+#define PHY_BB_PA_GAIN123_ADDRESS                                                             0x00009df8
+#define PHY_BB_PA_GAIN123_OFFSET                                                              0x00009df8
+#define PHY_BB_PA_GAIN123_PA_GAIN1_MSB                                                                 9
+#define PHY_BB_PA_GAIN123_PA_GAIN1_LSB                                                                 0
+#define PHY_BB_PA_GAIN123_PA_GAIN1_MASK                                                       0x000003ff
+#define PHY_BB_PA_GAIN123_PA_GAIN1_GET(x)                                      (((x) & 0x000003ff) >> 0)
+#define PHY_BB_PA_GAIN123_PA_GAIN1_SET(x)                                      (((x) << 0) & 0x000003ff)
+#define PHY_BB_PA_GAIN123_PA_GAIN2_MSB                                                                19
+#define PHY_BB_PA_GAIN123_PA_GAIN2_LSB                                                                10
+#define PHY_BB_PA_GAIN123_PA_GAIN2_MASK                                                       0x000ffc00
+#define PHY_BB_PA_GAIN123_PA_GAIN2_GET(x)                                     (((x) & 0x000ffc00) >> 10)
+#define PHY_BB_PA_GAIN123_PA_GAIN2_SET(x)                                     (((x) << 10) & 0x000ffc00)
+#define PHY_BB_PA_GAIN123_PA_GAIN3_MSB                                                                29
+#define PHY_BB_PA_GAIN123_PA_GAIN3_LSB                                                                20
+#define PHY_BB_PA_GAIN123_PA_GAIN3_MASK                                                       0x3ff00000
+#define PHY_BB_PA_GAIN123_PA_GAIN3_GET(x)                                     (((x) & 0x3ff00000) >> 20)
+#define PHY_BB_PA_GAIN123_PA_GAIN3_SET(x)                                     (((x) << 20) & 0x3ff00000)
+
+/* macros for BB_pa_gain45 */
+#define PHY_BB_PA_GAIN45_ADDRESS                                                              0x00009dfc
+#define PHY_BB_PA_GAIN45_OFFSET                                                               0x00009dfc
+#define PHY_BB_PA_GAIN45_PA_GAIN4_MSB                                                                  9
+#define PHY_BB_PA_GAIN45_PA_GAIN4_LSB                                                                  0
+#define PHY_BB_PA_GAIN45_PA_GAIN4_MASK                                                        0x000003ff
+#define PHY_BB_PA_GAIN45_PA_GAIN4_GET(x)                                       (((x) & 0x000003ff) >> 0)
+#define PHY_BB_PA_GAIN45_PA_GAIN4_SET(x)                                       (((x) << 0) & 0x000003ff)
+#define PHY_BB_PA_GAIN45_PA_GAIN5_MSB                                                                 19
+#define PHY_BB_PA_GAIN45_PA_GAIN5_LSB                                                                 10
+#define PHY_BB_PA_GAIN45_PA_GAIN5_MASK                                                        0x000ffc00
+#define PHY_BB_PA_GAIN45_PA_GAIN5_GET(x)                                      (((x) & 0x000ffc00) >> 10)
+#define PHY_BB_PA_GAIN45_PA_GAIN5_SET(x)                                      (((x) << 10) & 0x000ffc00)
+#define PHY_BB_PA_GAIN45_PAPRD_ADAPTIVE_TABLE_VALID_MSB                                               24
+#define PHY_BB_PA_GAIN45_PAPRD_ADAPTIVE_TABLE_VALID_LSB                                               20
+#define PHY_BB_PA_GAIN45_PAPRD_ADAPTIVE_TABLE_VALID_MASK                                      0x01f00000
+#define PHY_BB_PA_GAIN45_PAPRD_ADAPTIVE_TABLE_VALID_GET(x)                    (((x) & 0x01f00000) >> 20)
+#define PHY_BB_PA_GAIN45_PAPRD_ADAPTIVE_TABLE_VALID_SET(x)                    (((x) << 20) & 0x01f00000)
+
+/* macros for BB_paprd_pre_post_scale_0 */
+#define PHY_BB_PAPRD_PRE_POST_SCALE_0_ADDRESS                                                 0x00009e00
+#define PHY_BB_PAPRD_PRE_POST_SCALE_0_OFFSET                                                  0x00009e00
+#define PHY_BB_PAPRD_PRE_POST_SCALE_0_PAPRD_PRE_POST_SCALING_0_MSB                                    17
+#define PHY_BB_PAPRD_PRE_POST_SCALE_0_PAPRD_PRE_POST_SCALING_0_LSB                                     0
+#define PHY_BB_PAPRD_PRE_POST_SCALE_0_PAPRD_PRE_POST_SCALING_0_MASK                           0x0003ffff
+#define PHY_BB_PAPRD_PRE_POST_SCALE_0_PAPRD_PRE_POST_SCALING_0_GET(x)          (((x) & 0x0003ffff) >> 0)
+#define PHY_BB_PAPRD_PRE_POST_SCALE_0_PAPRD_PRE_POST_SCALING_0_SET(x)          (((x) << 0) & 0x0003ffff)
+
+/* macros for BB_paprd_pre_post_scale_1 */
+#define PHY_BB_PAPRD_PRE_POST_SCALE_1_ADDRESS                                                 0x00009e04
+#define PHY_BB_PAPRD_PRE_POST_SCALE_1_OFFSET                                                  0x00009e04
+#define PHY_BB_PAPRD_PRE_POST_SCALE_1_PAPRD_PRE_POST_SCALING_1_MSB                                    17
+#define PHY_BB_PAPRD_PRE_POST_SCALE_1_PAPRD_PRE_POST_SCALING_1_LSB                                     0
+#define PHY_BB_PAPRD_PRE_POST_SCALE_1_PAPRD_PRE_POST_SCALING_1_MASK                           0x0003ffff
+#define PHY_BB_PAPRD_PRE_POST_SCALE_1_PAPRD_PRE_POST_SCALING_1_GET(x)          (((x) & 0x0003ffff) >> 0)
+#define PHY_BB_PAPRD_PRE_POST_SCALE_1_PAPRD_PRE_POST_SCALING_1_SET(x)          (((x) << 0) & 0x0003ffff)
+
+/* macros for BB_paprd_pre_post_scale_2 */
+#define PHY_BB_PAPRD_PRE_POST_SCALE_2_ADDRESS                                                 0x00009e08
+#define PHY_BB_PAPRD_PRE_POST_SCALE_2_OFFSET                                                  0x00009e08
+#define PHY_BB_PAPRD_PRE_POST_SCALE_2_PAPRD_PRE_POST_SCALING_2_MSB                                    17
+#define PHY_BB_PAPRD_PRE_POST_SCALE_2_PAPRD_PRE_POST_SCALING_2_LSB                                     0
+#define PHY_BB_PAPRD_PRE_POST_SCALE_2_PAPRD_PRE_POST_SCALING_2_MASK                           0x0003ffff
+#define PHY_BB_PAPRD_PRE_POST_SCALE_2_PAPRD_PRE_POST_SCALING_2_GET(x)          (((x) & 0x0003ffff) >> 0)
+#define PHY_BB_PAPRD_PRE_POST_SCALE_2_PAPRD_PRE_POST_SCALING_2_SET(x)          (((x) << 0) & 0x0003ffff)
+
+/* macros for BB_paprd_pre_post_scale_3 */
+#define PHY_BB_PAPRD_PRE_POST_SCALE_3_ADDRESS                                                 0x00009e0c
+#define PHY_BB_PAPRD_PRE_POST_SCALE_3_OFFSET                                                  0x00009e0c
+#define PHY_BB_PAPRD_PRE_POST_SCALE_3_PAPRD_PRE_POST_SCALING_3_MSB                                    17
+#define PHY_BB_PAPRD_PRE_POST_SCALE_3_PAPRD_PRE_POST_SCALING_3_LSB                                     0
+#define PHY_BB_PAPRD_PRE_POST_SCALE_3_PAPRD_PRE_POST_SCALING_3_MASK                           0x0003ffff
+#define PHY_BB_PAPRD_PRE_POST_SCALE_3_PAPRD_PRE_POST_SCALING_3_GET(x)          (((x) & 0x0003ffff) >> 0)
+#define PHY_BB_PAPRD_PRE_POST_SCALE_3_PAPRD_PRE_POST_SCALING_3_SET(x)          (((x) << 0) & 0x0003ffff)
+
+/* macros for BB_paprd_pre_post_scale_4 */
+#define PHY_BB_PAPRD_PRE_POST_SCALE_4_ADDRESS                                                 0x00009e10
+#define PHY_BB_PAPRD_PRE_POST_SCALE_4_OFFSET                                                  0x00009e10
+#define PHY_BB_PAPRD_PRE_POST_SCALE_4_PAPRD_PRE_POST_SCALING_4_MSB                                    17
+#define PHY_BB_PAPRD_PRE_POST_SCALE_4_PAPRD_PRE_POST_SCALING_4_LSB                                     0
+#define PHY_BB_PAPRD_PRE_POST_SCALE_4_PAPRD_PRE_POST_SCALING_4_MASK                           0x0003ffff
+#define PHY_BB_PAPRD_PRE_POST_SCALE_4_PAPRD_PRE_POST_SCALING_4_GET(x)          (((x) & 0x0003ffff) >> 0)
+#define PHY_BB_PAPRD_PRE_POST_SCALE_4_PAPRD_PRE_POST_SCALING_4_SET(x)          (((x) << 0) & 0x0003ffff)
+
+/* macros for BB_paprd_pre_post_scale_5 */
+#define PHY_BB_PAPRD_PRE_POST_SCALE_5_ADDRESS                                                 0x00009e14
+#define PHY_BB_PAPRD_PRE_POST_SCALE_5_OFFSET                                                  0x00009e14
+#define PHY_BB_PAPRD_PRE_POST_SCALE_5_PAPRD_PRE_POST_SCALING_5_MSB                                    17
+#define PHY_BB_PAPRD_PRE_POST_SCALE_5_PAPRD_PRE_POST_SCALING_5_LSB                                     0
+#define PHY_BB_PAPRD_PRE_POST_SCALE_5_PAPRD_PRE_POST_SCALING_5_MASK                           0x0003ffff
+#define PHY_BB_PAPRD_PRE_POST_SCALE_5_PAPRD_PRE_POST_SCALING_5_GET(x)          (((x) & 0x0003ffff) >> 0)
+#define PHY_BB_PAPRD_PRE_POST_SCALE_5_PAPRD_PRE_POST_SCALING_5_SET(x)          (((x) << 0) & 0x0003ffff)
+
+/* macros for BB_paprd_pre_post_scale_6 */
+#define PHY_BB_PAPRD_PRE_POST_SCALE_6_ADDRESS                                                 0x00009e18
+#define PHY_BB_PAPRD_PRE_POST_SCALE_6_OFFSET                                                  0x00009e18
+#define PHY_BB_PAPRD_PRE_POST_SCALE_6_PAPRD_PRE_POST_SCALING_6_MSB                                    17
+#define PHY_BB_PAPRD_PRE_POST_SCALE_6_PAPRD_PRE_POST_SCALING_6_LSB                                     0
+#define PHY_BB_PAPRD_PRE_POST_SCALE_6_PAPRD_PRE_POST_SCALING_6_MASK                           0x0003ffff
+#define PHY_BB_PAPRD_PRE_POST_SCALE_6_PAPRD_PRE_POST_SCALING_6_GET(x)          (((x) & 0x0003ffff) >> 0)
+#define PHY_BB_PAPRD_PRE_POST_SCALE_6_PAPRD_PRE_POST_SCALING_6_SET(x)          (((x) << 0) & 0x0003ffff)
+
+/* macros for BB_paprd_pre_post_scale_7 */
+#define PHY_BB_PAPRD_PRE_POST_SCALE_7_ADDRESS                                                 0x00009e1c
+#define PHY_BB_PAPRD_PRE_POST_SCALE_7_OFFSET                                                  0x00009e1c
+#define PHY_BB_PAPRD_PRE_POST_SCALE_7_PAPRD_PRE_POST_SCALING_7_MSB                                    17
+#define PHY_BB_PAPRD_PRE_POST_SCALE_7_PAPRD_PRE_POST_SCALING_7_LSB                                     0
+#define PHY_BB_PAPRD_PRE_POST_SCALE_7_PAPRD_PRE_POST_SCALING_7_MASK                           0x0003ffff
+#define PHY_BB_PAPRD_PRE_POST_SCALE_7_PAPRD_PRE_POST_SCALING_7_GET(x)          (((x) & 0x0003ffff) >> 0)
+#define PHY_BB_PAPRD_PRE_POST_SCALE_7_PAPRD_PRE_POST_SCALING_7_SET(x)          (((x) << 0) & 0x0003ffff)
+
+/* macros for BB_paprd_mem_tab */
+#define PHY_BB_PAPRD_MEM_TAB_ADDRESS                                                          0x00009e20
+#define PHY_BB_PAPRD_MEM_TAB_OFFSET                                                           0x00009e20
+#define PHY_BB_PAPRD_MEM_TAB_PAPRD_MEM_MSB                                                            21
+#define PHY_BB_PAPRD_MEM_TAB_PAPRD_MEM_LSB                                                             0
+#define PHY_BB_PAPRD_MEM_TAB_PAPRD_MEM_MASK                                                   0x003fffff
+#define PHY_BB_PAPRD_MEM_TAB_PAPRD_MEM_GET(x)                                  (((x) & 0x003fffff) >> 0)
+#define PHY_BB_PAPRD_MEM_TAB_PAPRD_MEM_SET(x)                                  (((x) << 0) & 0x003fffff)
+
+/* macros for BB_peak_det_ctrl_1 */
+#define PHY_BB_PEAK_DET_CTRL_1_ADDRESS                                                        0x0000a000
+#define PHY_BB_PEAK_DET_CTRL_1_OFFSET                                                         0x0000a000
+#define PHY_BB_PEAK_DET_CTRL_1_USE_OC_GAIN_TABLE_MSB                                                   0
+#define PHY_BB_PEAK_DET_CTRL_1_USE_OC_GAIN_TABLE_LSB                                                   0
+#define PHY_BB_PEAK_DET_CTRL_1_USE_OC_GAIN_TABLE_MASK                                         0x00000001
+#define PHY_BB_PEAK_DET_CTRL_1_USE_OC_GAIN_TABLE_GET(x)                        (((x) & 0x00000001) >> 0)
+#define PHY_BB_PEAK_DET_CTRL_1_USE_OC_GAIN_TABLE_SET(x)                        (((x) << 0) & 0x00000001)
+#define PHY_BB_PEAK_DET_CTRL_1_USE_PEAK_DET_MSB                                                        1
+#define PHY_BB_PEAK_DET_CTRL_1_USE_PEAK_DET_LSB                                                        1
+#define PHY_BB_PEAK_DET_CTRL_1_USE_PEAK_DET_MASK                                              0x00000002
+#define PHY_BB_PEAK_DET_CTRL_1_USE_PEAK_DET_GET(x)                             (((x) & 0x00000002) >> 1)
+#define PHY_BB_PEAK_DET_CTRL_1_USE_PEAK_DET_SET(x)                             (((x) << 1) & 0x00000002)
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_WIN_LEN_MSB                                                    7
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_WIN_LEN_LSB                                                    2
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_WIN_LEN_MASK                                          0x000000fc
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_WIN_LEN_GET(x)                         (((x) & 0x000000fc) >> 2)
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_WIN_LEN_SET(x)                         (((x) << 2) & 0x000000fc)
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_LOW_MSB                                             12
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_LOW_LSB                                              8
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_LOW_MASK                                    0x00001f00
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_LOW_GET(x)                   (((x) & 0x00001f00) >> 8)
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_LOW_SET(x)                   (((x) << 8) & 0x00001f00)
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_MED_MSB                                             17
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_MED_LSB                                             13
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_MED_MASK                                    0x0003e000
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_MED_GET(x)                  (((x) & 0x0003e000) >> 13)
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_MED_SET(x)                  (((x) << 13) & 0x0003e000)
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_HIGH_MSB                                            22
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_HIGH_LSB                                            18
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_HIGH_MASK                                   0x007c0000
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_HIGH_GET(x)                 (((x) & 0x007c0000) >> 18)
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_HIGH_SET(x)                 (((x) << 18) & 0x007c0000)
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_SETTLING_MSB                                                  29
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_SETTLING_LSB                                                  23
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_SETTLING_MASK                                         0x3f800000
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_SETTLING_GET(x)                       (((x) & 0x3f800000) >> 23)
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_SETTLING_SET(x)                       (((x) << 23) & 0x3f800000)
+#define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_CAL_MSB                                               30
+#define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_CAL_LSB                                               30
+#define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_CAL_MASK                                      0x40000000
+#define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_CAL_GET(x)                    (((x) & 0x40000000) >> 30)
+#define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_CAL_SET(x)                    (((x) << 30) & 0x40000000)
+#define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_RX_MSB                                                31
+#define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_RX_LSB                                                31
+#define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_RX_MASK                                       0x80000000
+#define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_RX_GET(x)                     (((x) & 0x80000000) >> 31)
+#define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_RX_SET(x)                     (((x) << 31) & 0x80000000)
+
+/* macros for BB_peak_det_ctrl_2 */
+#define PHY_BB_PEAK_DET_CTRL_2_ADDRESS                                                        0x0000a004
+#define PHY_BB_PEAK_DET_CTRL_2_OFFSET                                                         0x0000a004
+#define PHY_BB_PEAK_DET_CTRL_2_RFSAT_2_ADD_RFGAIN_DEL_MSB                                              9
+#define PHY_BB_PEAK_DET_CTRL_2_RFSAT_2_ADD_RFGAIN_DEL_LSB                                              0
+#define PHY_BB_PEAK_DET_CTRL_2_RFSAT_2_ADD_RFGAIN_DEL_MASK                                    0x000003ff
+#define PHY_BB_PEAK_DET_CTRL_2_RFSAT_2_ADD_RFGAIN_DEL_GET(x)                   (((x) & 0x000003ff) >> 0)
+#define PHY_BB_PEAK_DET_CTRL_2_RFSAT_2_ADD_RFGAIN_DEL_SET(x)                   (((x) << 0) & 0x000003ff)
+#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_LOW_MSB                                                14
+#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_LOW_LSB                                                10
+#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_LOW_MASK                                       0x00007c00
+#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_LOW_GET(x)                     (((x) & 0x00007c00) >> 10)
+#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_LOW_SET(x)                     (((x) << 10) & 0x00007c00)
+#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_MED_MSB                                                19
+#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_MED_LSB                                                15
+#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_MED_MASK                                       0x000f8000
+#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_MED_GET(x)                     (((x) & 0x000f8000) >> 15)
+#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_MED_SET(x)                     (((x) << 15) & 0x000f8000)
+#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_HIGH_MSB                                               24
+#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_HIGH_LSB                                               20
+#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_HIGH_MASK                                      0x01f00000
+#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_HIGH_GET(x)                    (((x) & 0x01f00000) >> 20)
+#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_HIGH_SET(x)                    (((x) << 20) & 0x01f00000)
+#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_NON_MSB                                                29
+#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_NON_LSB                                                25
+#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_NON_MASK                                       0x3e000000
+#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_NON_GET(x)                     (((x) & 0x3e000000) >> 25)
+#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_NON_SET(x)                     (((x) << 25) & 0x3e000000)
+
+/* macros for BB_rx_gain_bounds_1 */
+#define PHY_BB_RX_GAIN_BOUNDS_1_ADDRESS                                                       0x0000a008
+#define PHY_BB_RX_GAIN_BOUNDS_1_OFFSET                                                        0x0000a008
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_MB_GAIN_MSB                                                     7
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_MB_GAIN_LSB                                                     0
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_MB_GAIN_MASK                                           0x000000ff
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_MB_GAIN_GET(x)                          (((x) & 0x000000ff) >> 0)
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_MB_GAIN_SET(x)                          (((x) << 0) & 0x000000ff)
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_REF_MSB                                                15
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_REF_LSB                                                 8
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_REF_MASK                                       0x0000ff00
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_REF_GET(x)                      (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_REF_SET(x)                      (((x) << 8) & 0x0000ff00)
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_MSB                                                    23
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_LSB                                                    16
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_MASK                                           0x00ff0000
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_GET(x)                         (((x) & 0x00ff0000) >> 16)
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_SET(x)                         (((x) << 16) & 0x00ff0000)
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_2G_MSB                                                  24
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_2G_LSB                                                  24
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_2G_MASK                                         0x01000000
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_2G_GET(x)                       (((x) & 0x01000000) >> 24)
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_2G_SET(x)                       (((x) << 24) & 0x01000000)
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_5G_MSB                                                  25
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_5G_LSB                                                  25
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_5G_MASK                                         0x02000000
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_5G_GET(x)                       (((x) & 0x02000000) >> 25)
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_5G_SET(x)                       (((x) << 25) & 0x02000000)
+
+/* macros for BB_rx_gain_bounds_2 */
+#define PHY_BB_RX_GAIN_BOUNDS_2_ADDRESS                                                       0x0000a00c
+#define PHY_BB_RX_GAIN_BOUNDS_2_OFFSET                                                        0x0000a00c
+#define PHY_BB_RX_GAIN_BOUNDS_2_GC_RSSI_LOW_DB_MSB                                                     7
+#define PHY_BB_RX_GAIN_BOUNDS_2_GC_RSSI_LOW_DB_LSB                                                     0
+#define PHY_BB_RX_GAIN_BOUNDS_2_GC_RSSI_LOW_DB_MASK                                           0x000000ff
+#define PHY_BB_RX_GAIN_BOUNDS_2_GC_RSSI_LOW_DB_GET(x)                          (((x) & 0x000000ff) >> 0)
+#define PHY_BB_RX_GAIN_BOUNDS_2_GC_RSSI_LOW_DB_SET(x)                          (((x) << 0) & 0x000000ff)
+#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_REF_BASE_ADDR_MSB                                             15
+#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_REF_BASE_ADDR_LSB                                              8
+#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_REF_BASE_ADDR_MASK                                    0x0000ff00
+#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_REF_BASE_ADDR_GET(x)                   (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_REF_BASE_ADDR_SET(x)                   (((x) << 8) & 0x0000ff00)
+#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_BASE_ADDR_MSB                                                 23
+#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_BASE_ADDR_LSB                                                 16
+#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_BASE_ADDR_MASK                                        0x00ff0000
+#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_BASE_ADDR_GET(x)                      (((x) & 0x00ff0000) >> 16)
+#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_BASE_ADDR_SET(x)                      (((x) << 16) & 0x00ff0000)
+#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_DIV_BASE_ADDR_MSB                                             31
+#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_DIV_BASE_ADDR_LSB                                             24
+#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_DIV_BASE_ADDR_MASK                                    0xff000000
+#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_DIV_BASE_ADDR_GET(x)                  (((x) & 0xff000000) >> 24)
+#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_DIV_BASE_ADDR_SET(x)                  (((x) << 24) & 0xff000000)
+
+/* macros for BB_peak_det_cal_ctrl */
+#define PHY_BB_PEAK_DET_CAL_CTRL_ADDRESS                                                      0x0000a010
+#define PHY_BB_PEAK_DET_CAL_CTRL_OFFSET                                                       0x0000a010
+#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_WIN_THR_MSB                                                 5
+#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_WIN_THR_LSB                                                 0
+#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_WIN_THR_MASK                                       0x0000003f
+#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_WIN_THR_GET(x)                      (((x) & 0x0000003f) >> 0)
+#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_WIN_THR_SET(x)                      (((x) << 0) & 0x0000003f)
+#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_BIAS_MSB                                                   11
+#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_BIAS_LSB                                                    6
+#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_BIAS_MASK                                          0x00000fc0
+#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_BIAS_GET(x)                         (((x) & 0x00000fc0) >> 6)
+#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_BIAS_SET(x)                         (((x) << 6) & 0x00000fc0)
+#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_MEAS_TIME_SEL_MSB                                          13
+#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_MEAS_TIME_SEL_LSB                                          12
+#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_MEAS_TIME_SEL_MASK                                 0x00003000
+#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_MEAS_TIME_SEL_GET(x)               (((x) & 0x00003000) >> 12)
+#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_MEAS_TIME_SEL_SET(x)               (((x) << 12) & 0x00003000)
+
+/* macros for BB_agc_dig_dc_ctrl */
+#define PHY_BB_AGC_DIG_DC_CTRL_ADDRESS                                                        0x0000a014
+#define PHY_BB_AGC_DIG_DC_CTRL_OFFSET                                                         0x0000a014
+#define PHY_BB_AGC_DIG_DC_CTRL_USE_DIG_DC_MSB                                                          0
+#define PHY_BB_AGC_DIG_DC_CTRL_USE_DIG_DC_LSB                                                          0
+#define PHY_BB_AGC_DIG_DC_CTRL_USE_DIG_DC_MASK                                                0x00000001
+#define PHY_BB_AGC_DIG_DC_CTRL_USE_DIG_DC_GET(x)                               (((x) & 0x00000001) >> 0)
+#define PHY_BB_AGC_DIG_DC_CTRL_USE_DIG_DC_SET(x)                               (((x) << 0) & 0x00000001)
+#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_SCALE_BIAS_MSB                                                   3
+#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_SCALE_BIAS_LSB                                                   1
+#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_SCALE_BIAS_MASK                                         0x0000000e
+#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_SCALE_BIAS_GET(x)                        (((x) & 0x0000000e) >> 1)
+#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_SCALE_BIAS_SET(x)                        (((x) << 1) & 0x0000000e)
+#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_CORRECT_CAP_MSB                                                  9
+#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_CORRECT_CAP_LSB                                                  4
+#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_CORRECT_CAP_MASK                                        0x000003f0
+#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_CORRECT_CAP_GET(x)                       (((x) & 0x000003f0) >> 4)
+#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_CORRECT_CAP_SET(x)                       (((x) << 4) & 0x000003f0)
+#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_MIXER_SEL_MASK_MSB                                              31
+#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_MIXER_SEL_MASK_LSB                                              16
+#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_MIXER_SEL_MASK_MASK                                     0xffff0000
+#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_MIXER_SEL_MASK_GET(x)                   (((x) & 0xffff0000) >> 16)
+#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_MIXER_SEL_MASK_SET(x)                   (((x) << 16) & 0xffff0000)
+
+/* macros for BB_agc_dig_dc_status_i_b0 */
+#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_ADDRESS                                                 0x0000a018
+#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_OFFSET                                                  0x0000a018
+#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C1_RES_I_0_MSB                                            8
+#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C1_RES_I_0_LSB                                            0
+#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C1_RES_I_0_MASK                                  0x000001ff
+#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C1_RES_I_0_GET(x)                 (((x) & 0x000001ff) >> 0)
+#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C2_RES_I_0_MSB                                           17
+#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C2_RES_I_0_LSB                                            9
+#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C2_RES_I_0_MASK                                  0x0003fe00
+#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C2_RES_I_0_GET(x)                 (((x) & 0x0003fe00) >> 9)
+#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C3_RES_I_0_MSB                                           26
+#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C3_RES_I_0_LSB                                           18
+#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C3_RES_I_0_MASK                                  0x07fc0000
+#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C3_RES_I_0_GET(x)                (((x) & 0x07fc0000) >> 18)
+
+/* macros for BB_agc_dig_dc_status_q_b0 */
+#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_ADDRESS                                                 0x0000a01c
+#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_OFFSET                                                  0x0000a01c
+#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C1_RES_Q_0_MSB                                            8
+#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C1_RES_Q_0_LSB                                            0
+#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C1_RES_Q_0_MASK                                  0x000001ff
+#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C1_RES_Q_0_GET(x)                 (((x) & 0x000001ff) >> 0)
+#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C2_RES_Q_0_MSB                                           17
+#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C2_RES_Q_0_LSB                                            9
+#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C2_RES_Q_0_MASK                                  0x0003fe00
+#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C2_RES_Q_0_GET(x)                 (((x) & 0x0003fe00) >> 9)
+#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C3_RES_Q_0_MSB                                           26
+#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C3_RES_Q_0_LSB                                           18
+#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C3_RES_Q_0_MASK                                  0x07fc0000
+#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C3_RES_Q_0_GET(x)                (((x) & 0x07fc0000) >> 18)
+
+/* macros for BB_bbb_txfir_0 */
+#define PHY_BB_BBB_TXFIR_0_ADDRESS                                                            0x0000a1f4
+#define PHY_BB_BBB_TXFIR_0_OFFSET                                                             0x0000a1f4
+#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H0_MSB                                                          3
+#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H0_LSB                                                          0
+#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H0_MASK                                                0x0000000f
+#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H0_GET(x)                               (((x) & 0x0000000f) >> 0)
+#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H0_SET(x)                               (((x) << 0) & 0x0000000f)
+#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H1_MSB                                                         11
+#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H1_LSB                                                          8
+#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H1_MASK                                                0x00000f00
+#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H1_GET(x)                               (((x) & 0x00000f00) >> 8)
+#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H1_SET(x)                               (((x) << 8) & 0x00000f00)
+#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H2_MSB                                                         20
+#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H2_LSB                                                         16
+#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H2_MASK                                                0x001f0000
+#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H2_GET(x)                              (((x) & 0x001f0000) >> 16)
+#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H2_SET(x)                              (((x) << 16) & 0x001f0000)
+#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H3_MSB                                                         28
+#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H3_LSB                                                         24
+#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H3_MASK                                                0x1f000000
+#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H3_GET(x)                              (((x) & 0x1f000000) >> 24)
+#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H3_SET(x)                              (((x) << 24) & 0x1f000000)
+
+/* macros for BB_bbb_txfir_1 */
+#define PHY_BB_BBB_TXFIR_1_ADDRESS                                                            0x0000a1f8
+#define PHY_BB_BBB_TXFIR_1_OFFSET                                                             0x0000a1f8
+#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H4_MSB                                                          5
+#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H4_LSB                                                          0
+#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H4_MASK                                                0x0000003f
+#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H4_GET(x)                               (((x) & 0x0000003f) >> 0)
+#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H4_SET(x)                               (((x) << 0) & 0x0000003f)
+#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H5_MSB                                                         13
+#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H5_LSB                                                          8
+#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H5_MASK                                                0x00003f00
+#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H5_GET(x)                               (((x) & 0x00003f00) >> 8)
+#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H5_SET(x)                               (((x) << 8) & 0x00003f00)
+#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H6_MSB                                                         22
+#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H6_LSB                                                         16
+#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H6_MASK                                                0x007f0000
+#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H6_GET(x)                              (((x) & 0x007f0000) >> 16)
+#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H6_SET(x)                              (((x) << 16) & 0x007f0000)
+#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H7_MSB                                                         30
+#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H7_LSB                                                         24
+#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H7_MASK                                                0x7f000000
+#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H7_GET(x)                              (((x) & 0x7f000000) >> 24)
+#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H7_SET(x)                              (((x) << 24) & 0x7f000000)
+
+/* macros for BB_bbb_txfir_2 */
+#define PHY_BB_BBB_TXFIR_2_ADDRESS                                                            0x0000a1fc
+#define PHY_BB_BBB_TXFIR_2_OFFSET                                                             0x0000a1fc
+#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H8_MSB                                                          7
+#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H8_LSB                                                          0
+#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H8_MASK                                                0x000000ff
+#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H8_GET(x)                               (((x) & 0x000000ff) >> 0)
+#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H8_SET(x)                               (((x) << 0) & 0x000000ff)
+#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H9_MSB                                                         15
+#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H9_LSB                                                          8
+#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H9_MASK                                                0x0000ff00
+#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H9_GET(x)                               (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H9_SET(x)                               (((x) << 8) & 0x0000ff00)
+#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H10_MSB                                                        23
+#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H10_LSB                                                        16
+#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H10_MASK                                               0x00ff0000
+#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H10_GET(x)                             (((x) & 0x00ff0000) >> 16)
+#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H10_SET(x)                             (((x) << 16) & 0x00ff0000)
+#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H11_MSB                                                        31
+#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H11_LSB                                                        24
+#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H11_MASK                                               0xff000000
+#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H11_GET(x)                             (((x) & 0xff000000) >> 24)
+#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H11_SET(x)                             (((x) << 24) & 0xff000000)
+
+/* macros for BB_modes_select */
+#define PHY_BB_MODES_SELECT_ADDRESS                                                           0x0000a200
+#define PHY_BB_MODES_SELECT_OFFSET                                                            0x0000a200
+#define PHY_BB_MODES_SELECT_CCK_MODE_MSB                                                               0
+#define PHY_BB_MODES_SELECT_CCK_MODE_LSB                                                               0
+#define PHY_BB_MODES_SELECT_CCK_MODE_MASK                                                     0x00000001
+#define PHY_BB_MODES_SELECT_CCK_MODE_GET(x)                                    (((x) & 0x00000001) >> 0)
+#define PHY_BB_MODES_SELECT_CCK_MODE_SET(x)                                    (((x) << 0) & 0x00000001)
+#define PHY_BB_MODES_SELECT_DYN_OFDM_CCK_MODE_MSB                                                      2
+#define PHY_BB_MODES_SELECT_DYN_OFDM_CCK_MODE_LSB                                                      2
+#define PHY_BB_MODES_SELECT_DYN_OFDM_CCK_MODE_MASK                                            0x00000004
+#define PHY_BB_MODES_SELECT_DYN_OFDM_CCK_MODE_GET(x)                           (((x) & 0x00000004) >> 2)
+#define PHY_BB_MODES_SELECT_DYN_OFDM_CCK_MODE_SET(x)                           (((x) << 2) & 0x00000004)
+#define PHY_BB_MODES_SELECT_HALF_RATE_MODE_MSB                                                         5
+#define PHY_BB_MODES_SELECT_HALF_RATE_MODE_LSB                                                         5
+#define PHY_BB_MODES_SELECT_HALF_RATE_MODE_MASK                                               0x00000020
+#define PHY_BB_MODES_SELECT_HALF_RATE_MODE_GET(x)                              (((x) & 0x00000020) >> 5)
+#define PHY_BB_MODES_SELECT_HALF_RATE_MODE_SET(x)                              (((x) << 5) & 0x00000020)
+#define PHY_BB_MODES_SELECT_QUARTER_RATE_MODE_MSB                                                      6
+#define PHY_BB_MODES_SELECT_QUARTER_RATE_MODE_LSB                                                      6
+#define PHY_BB_MODES_SELECT_QUARTER_RATE_MODE_MASK                                            0x00000040
+#define PHY_BB_MODES_SELECT_QUARTER_RATE_MODE_GET(x)                           (((x) & 0x00000040) >> 6)
+#define PHY_BB_MODES_SELECT_QUARTER_RATE_MODE_SET(x)                           (((x) << 6) & 0x00000040)
+#define PHY_BB_MODES_SELECT_MAC_CLK_MODE_MSB                                                           7
+#define PHY_BB_MODES_SELECT_MAC_CLK_MODE_LSB                                                           7
+#define PHY_BB_MODES_SELECT_MAC_CLK_MODE_MASK                                                 0x00000080
+#define PHY_BB_MODES_SELECT_MAC_CLK_MODE_GET(x)                                (((x) & 0x00000080) >> 7)
+#define PHY_BB_MODES_SELECT_MAC_CLK_MODE_SET(x)                                (((x) << 7) & 0x00000080)
+#define PHY_BB_MODES_SELECT_DISABLE_DYN_CCK_DET_MSB                                                    8
+#define PHY_BB_MODES_SELECT_DISABLE_DYN_CCK_DET_LSB                                                    8
+#define PHY_BB_MODES_SELECT_DISABLE_DYN_CCK_DET_MASK                                          0x00000100
+#define PHY_BB_MODES_SELECT_DISABLE_DYN_CCK_DET_GET(x)                         (((x) & 0x00000100) >> 8)
+#define PHY_BB_MODES_SELECT_DISABLE_DYN_CCK_DET_SET(x)                         (((x) << 8) & 0x00000100)
+
+/* macros for BB_bbb_tx_ctrl */
+#define PHY_BB_BBB_TX_CTRL_ADDRESS                                                            0x0000a204
+#define PHY_BB_BBB_TX_CTRL_OFFSET                                                             0x0000a204
+#define PHY_BB_BBB_TX_CTRL_DISABLE_SCRAMBLER_MSB                                                       0
+#define PHY_BB_BBB_TX_CTRL_DISABLE_SCRAMBLER_LSB                                                       0
+#define PHY_BB_BBB_TX_CTRL_DISABLE_SCRAMBLER_MASK                                             0x00000001
+#define PHY_BB_BBB_TX_CTRL_DISABLE_SCRAMBLER_GET(x)                            (((x) & 0x00000001) >> 0)
+#define PHY_BB_BBB_TX_CTRL_DISABLE_SCRAMBLER_SET(x)                            (((x) << 0) & 0x00000001)
+#define PHY_BB_BBB_TX_CTRL_USE_SCRAMBLER_SEED_MSB                                                      1
+#define PHY_BB_BBB_TX_CTRL_USE_SCRAMBLER_SEED_LSB                                                      1
+#define PHY_BB_BBB_TX_CTRL_USE_SCRAMBLER_SEED_MASK                                            0x00000002
+#define PHY_BB_BBB_TX_CTRL_USE_SCRAMBLER_SEED_GET(x)                           (((x) & 0x00000002) >> 1)
+#define PHY_BB_BBB_TX_CTRL_USE_SCRAMBLER_SEED_SET(x)                           (((x) << 1) & 0x00000002)
+#define PHY_BB_BBB_TX_CTRL_TX_DAC_SCALE_CCK_MSB                                                        3
+#define PHY_BB_BBB_TX_CTRL_TX_DAC_SCALE_CCK_LSB                                                        2
+#define PHY_BB_BBB_TX_CTRL_TX_DAC_SCALE_CCK_MASK                                              0x0000000c
+#define PHY_BB_BBB_TX_CTRL_TX_DAC_SCALE_CCK_GET(x)                             (((x) & 0x0000000c) >> 2)
+#define PHY_BB_BBB_TX_CTRL_TX_DAC_SCALE_CCK_SET(x)                             (((x) << 2) & 0x0000000c)
+#define PHY_BB_BBB_TX_CTRL_TXFIR_JAPAN_CCK_MSB                                                         4
+#define PHY_BB_BBB_TX_CTRL_TXFIR_JAPAN_CCK_LSB                                                         4
+#define PHY_BB_BBB_TX_CTRL_TXFIR_JAPAN_CCK_MASK                                               0x00000010
+#define PHY_BB_BBB_TX_CTRL_TXFIR_JAPAN_CCK_GET(x)                              (((x) & 0x00000010) >> 4)
+#define PHY_BB_BBB_TX_CTRL_TXFIR_JAPAN_CCK_SET(x)                              (((x) << 4) & 0x00000010)
+#define PHY_BB_BBB_TX_CTRL_ALLOW_1MBPS_SHORT_MSB                                                       5
+#define PHY_BB_BBB_TX_CTRL_ALLOW_1MBPS_SHORT_LSB                                                       5
+#define PHY_BB_BBB_TX_CTRL_ALLOW_1MBPS_SHORT_MASK                                             0x00000020
+#define PHY_BB_BBB_TX_CTRL_ALLOW_1MBPS_SHORT_GET(x)                            (((x) & 0x00000020) >> 5)
+#define PHY_BB_BBB_TX_CTRL_ALLOW_1MBPS_SHORT_SET(x)                            (((x) << 5) & 0x00000020)
+#define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_1_MSB                                                          8
+#define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_1_LSB                                                          6
+#define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_1_MASK                                                0x000001c0
+#define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_1_GET(x)                               (((x) & 0x000001c0) >> 6)
+#define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_1_SET(x)                               (((x) << 6) & 0x000001c0)
+#define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_2_MSB                                                         11
+#define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_2_LSB                                                          9
+#define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_2_MASK                                                0x00000e00
+#define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_2_GET(x)                               (((x) & 0x00000e00) >> 9)
+#define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_2_SET(x)                               (((x) << 9) & 0x00000e00)
+
+/* macros for BB_bbb_sig_detect */
+#define PHY_BB_BBB_SIG_DETECT_ADDRESS                                                         0x0000a208
+#define PHY_BB_BBB_SIG_DETECT_OFFSET                                                          0x0000a208
+#define PHY_BB_BBB_SIG_DETECT_WEAK_SIG_THR_CCK_MSB                                                     5
+#define PHY_BB_BBB_SIG_DETECT_WEAK_SIG_THR_CCK_LSB                                                     0
+#define PHY_BB_BBB_SIG_DETECT_WEAK_SIG_THR_CCK_MASK                                           0x0000003f
+#define PHY_BB_BBB_SIG_DETECT_WEAK_SIG_THR_CCK_GET(x)                          (((x) & 0x0000003f) >> 0)
+#define PHY_BB_BBB_SIG_DETECT_WEAK_SIG_THR_CCK_SET(x)                          (((x) << 0) & 0x0000003f)
+#define PHY_BB_BBB_SIG_DETECT_ANT_SWITCH_TIME_MSB                                                     12
+#define PHY_BB_BBB_SIG_DETECT_ANT_SWITCH_TIME_LSB                                                      6
+#define PHY_BB_BBB_SIG_DETECT_ANT_SWITCH_TIME_MASK                                            0x00001fc0
+#define PHY_BB_BBB_SIG_DETECT_ANT_SWITCH_TIME_GET(x)                           (((x) & 0x00001fc0) >> 6)
+#define PHY_BB_BBB_SIG_DETECT_ANT_SWITCH_TIME_SET(x)                           (((x) << 6) & 0x00001fc0)
+#define PHY_BB_BBB_SIG_DETECT_ENABLE_ANT_FAST_DIV_MSB                                                 13
+#define PHY_BB_BBB_SIG_DETECT_ENABLE_ANT_FAST_DIV_LSB                                                 13
+#define PHY_BB_BBB_SIG_DETECT_ENABLE_ANT_FAST_DIV_MASK                                        0x00002000
+#define PHY_BB_BBB_SIG_DETECT_ENABLE_ANT_FAST_DIV_GET(x)                      (((x) & 0x00002000) >> 13)
+#define PHY_BB_BBB_SIG_DETECT_ENABLE_ANT_FAST_DIV_SET(x)                      (((x) << 13) & 0x00002000)
+#define PHY_BB_BBB_SIG_DETECT_LB_ALPHA_128_CCK_MSB                                                    14
+#define PHY_BB_BBB_SIG_DETECT_LB_ALPHA_128_CCK_LSB                                                    14
+#define PHY_BB_BBB_SIG_DETECT_LB_ALPHA_128_CCK_MASK                                           0x00004000
+#define PHY_BB_BBB_SIG_DETECT_LB_ALPHA_128_CCK_GET(x)                         (((x) & 0x00004000) >> 14)
+#define PHY_BB_BBB_SIG_DETECT_LB_ALPHA_128_CCK_SET(x)                         (((x) << 14) & 0x00004000)
+#define PHY_BB_BBB_SIG_DETECT_LB_RX_ENABLE_CCK_MSB                                                    15
+#define PHY_BB_BBB_SIG_DETECT_LB_RX_ENABLE_CCK_LSB                                                    15
+#define PHY_BB_BBB_SIG_DETECT_LB_RX_ENABLE_CCK_MASK                                           0x00008000
+#define PHY_BB_BBB_SIG_DETECT_LB_RX_ENABLE_CCK_GET(x)                         (((x) & 0x00008000) >> 15)
+#define PHY_BB_BBB_SIG_DETECT_LB_RX_ENABLE_CCK_SET(x)                         (((x) << 15) & 0x00008000)
+#define PHY_BB_BBB_SIG_DETECT_CYC32_COARSE_DC_EST_CCK_MSB                                             16
+#define PHY_BB_BBB_SIG_DETECT_CYC32_COARSE_DC_EST_CCK_LSB                                             16
+#define PHY_BB_BBB_SIG_DETECT_CYC32_COARSE_DC_EST_CCK_MASK                                    0x00010000
+#define PHY_BB_BBB_SIG_DETECT_CYC32_COARSE_DC_EST_CCK_GET(x)                  (((x) & 0x00010000) >> 16)
+#define PHY_BB_BBB_SIG_DETECT_CYC32_COARSE_DC_EST_CCK_SET(x)                  (((x) << 16) & 0x00010000)
+#define PHY_BB_BBB_SIG_DETECT_CYC64_COARSE_DC_EST_CCK_MSB                                             17
+#define PHY_BB_BBB_SIG_DETECT_CYC64_COARSE_DC_EST_CCK_LSB                                             17
+#define PHY_BB_BBB_SIG_DETECT_CYC64_COARSE_DC_EST_CCK_MASK                                    0x00020000
+#define PHY_BB_BBB_SIG_DETECT_CYC64_COARSE_DC_EST_CCK_GET(x)                  (((x) & 0x00020000) >> 17)
+#define PHY_BB_BBB_SIG_DETECT_CYC64_COARSE_DC_EST_CCK_SET(x)                  (((x) << 17) & 0x00020000)
+#define PHY_BB_BBB_SIG_DETECT_ENABLE_COARSE_DC_CCK_MSB                                                18
+#define PHY_BB_BBB_SIG_DETECT_ENABLE_COARSE_DC_CCK_LSB                                                18
+#define PHY_BB_BBB_SIG_DETECT_ENABLE_COARSE_DC_CCK_MASK                                       0x00040000
+#define PHY_BB_BBB_SIG_DETECT_ENABLE_COARSE_DC_CCK_GET(x)                     (((x) & 0x00040000) >> 18)
+#define PHY_BB_BBB_SIG_DETECT_ENABLE_COARSE_DC_CCK_SET(x)                     (((x) << 18) & 0x00040000)
+#define PHY_BB_BBB_SIG_DETECT_CYC256_FINE_DC_EST_CCK_MSB                                              19
+#define PHY_BB_BBB_SIG_DETECT_CYC256_FINE_DC_EST_CCK_LSB                                              19
+#define PHY_BB_BBB_SIG_DETECT_CYC256_FINE_DC_EST_CCK_MASK                                     0x00080000
+#define PHY_BB_BBB_SIG_DETECT_CYC256_FINE_DC_EST_CCK_GET(x)                   (((x) & 0x00080000) >> 19)
+#define PHY_BB_BBB_SIG_DETECT_CYC256_FINE_DC_EST_CCK_SET(x)                   (((x) << 19) & 0x00080000)
+#define PHY_BB_BBB_SIG_DETECT_ENABLE_FINE_DC_CCK_MSB                                                  20
+#define PHY_BB_BBB_SIG_DETECT_ENABLE_FINE_DC_CCK_LSB                                                  20
+#define PHY_BB_BBB_SIG_DETECT_ENABLE_FINE_DC_CCK_MASK                                         0x00100000
+#define PHY_BB_BBB_SIG_DETECT_ENABLE_FINE_DC_CCK_GET(x)                       (((x) & 0x00100000) >> 20)
+#define PHY_BB_BBB_SIG_DETECT_ENABLE_FINE_DC_CCK_SET(x)                       (((x) << 20) & 0x00100000)
+#define PHY_BB_BBB_SIG_DETECT_DELAY_START_SYNC_CCK_MSB                                                21
+#define PHY_BB_BBB_SIG_DETECT_DELAY_START_SYNC_CCK_LSB                                                21
+#define PHY_BB_BBB_SIG_DETECT_DELAY_START_SYNC_CCK_MASK                                       0x00200000
+#define PHY_BB_BBB_SIG_DETECT_DELAY_START_SYNC_CCK_GET(x)                     (((x) & 0x00200000) >> 21)
+#define PHY_BB_BBB_SIG_DETECT_DELAY_START_SYNC_CCK_SET(x)                     (((x) << 21) & 0x00200000)
+#define PHY_BB_BBB_SIG_DETECT_USE_DC_EST_DURING_SRCH_MSB                                              22
+#define PHY_BB_BBB_SIG_DETECT_USE_DC_EST_DURING_SRCH_LSB                                              22
+#define PHY_BB_BBB_SIG_DETECT_USE_DC_EST_DURING_SRCH_MASK                                     0x00400000
+#define PHY_BB_BBB_SIG_DETECT_USE_DC_EST_DURING_SRCH_GET(x)                   (((x) & 0x00400000) >> 22)
+#define PHY_BB_BBB_SIG_DETECT_USE_DC_EST_DURING_SRCH_SET(x)                   (((x) << 22) & 0x00400000)
+#define PHY_BB_BBB_SIG_DETECT_ENABLE_BARKER_TWO_PHASE_MSB                                             31
+#define PHY_BB_BBB_SIG_DETECT_ENABLE_BARKER_TWO_PHASE_LSB                                             31
+#define PHY_BB_BBB_SIG_DETECT_ENABLE_BARKER_TWO_PHASE_MASK                                    0x80000000
+#define PHY_BB_BBB_SIG_DETECT_ENABLE_BARKER_TWO_PHASE_GET(x)                  (((x) & 0x80000000) >> 31)
+#define PHY_BB_BBB_SIG_DETECT_ENABLE_BARKER_TWO_PHASE_SET(x)                  (((x) << 31) & 0x80000000)
+
+/* macros for BB_ext_atten_switch_ctl_b0 */
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_ADDRESS                                                0x0000a20c
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_OFFSET                                                 0x0000a20c
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_DB_0_MSB                                                5
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_DB_0_LSB                                                0
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_DB_0_MASK                                      0x0000003f
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_DB_0_GET(x)                     (((x) & 0x0000003f) >> 0)
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_DB_0_SET(x)                     (((x) << 0) & 0x0000003f)
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_DB_0_MSB                                               11
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_DB_0_LSB                                                6
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_DB_0_MASK                                      0x00000fc0
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_DB_0_GET(x)                     (((x) & 0x00000fc0) >> 6)
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_DB_0_SET(x)                     (((x) << 6) & 0x00000fc0)
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_MARGIN_0_MSB                                           16
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_MARGIN_0_LSB                                           12
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_MARGIN_0_MASK                                  0x0001f000
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_MARGIN_0_GET(x)                (((x) & 0x0001f000) >> 12)
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_MARGIN_0_SET(x)                (((x) << 12) & 0x0001f000)
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_MARGIN_0_MSB                                           21
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_MARGIN_0_LSB                                           17
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_MARGIN_0_MASK                                  0x003e0000
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_MARGIN_0_GET(x)                (((x) & 0x003e0000) >> 17)
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_MARGIN_0_SET(x)                (((x) << 17) & 0x003e0000)
+
+/* macros for BB_bbb_rx_ctrl_1 */
+#define PHY_BB_BBB_RX_CTRL_1_ADDRESS                                                          0x0000a210
+#define PHY_BB_BBB_RX_CTRL_1_OFFSET                                                           0x0000a210
+#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_2_MSB                                                2
+#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_2_LSB                                                0
+#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_2_MASK                                      0x00000007
+#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_2_GET(x)                     (((x) & 0x00000007) >> 0)
+#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_2_SET(x)                     (((x) << 0) & 0x00000007)
+#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_MSB                                                  7
+#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_LSB                                                  3
+#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_MASK                                        0x000000f8
+#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_GET(x)                       (((x) & 0x000000f8) >> 3)
+#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_SET(x)                       (((x) << 3) & 0x000000f8)
+#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_N_SYNC_MSB                                                    10
+#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_N_SYNC_LSB                                                     8
+#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_N_SYNC_MASK                                           0x00000700
+#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_N_SYNC_GET(x)                          (((x) & 0x00000700) >> 8)
+#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_N_SYNC_SET(x)                          (((x) << 8) & 0x00000700)
+#define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_LONG_MSB                                                         15
+#define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_LONG_LSB                                                         11
+#define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_LONG_MASK                                                0x0000f800
+#define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_LONG_GET(x)                              (((x) & 0x0000f800) >> 11)
+#define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_LONG_SET(x)                              (((x) << 11) & 0x0000f800)
+#define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_SHORT_MSB                                                        20
+#define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_SHORT_LSB                                                        16
+#define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_SHORT_MASK                                               0x001f0000
+#define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_SHORT_GET(x)                             (((x) & 0x001f0000) >> 16)
+#define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_SHORT_SET(x)                             (((x) << 16) & 0x001f0000)
+#define PHY_BB_BBB_RX_CTRL_1_RECON_LMS_STEP_MSB                                                       23
+#define PHY_BB_BBB_RX_CTRL_1_RECON_LMS_STEP_LSB                                                       21
+#define PHY_BB_BBB_RX_CTRL_1_RECON_LMS_STEP_MASK                                              0x00e00000
+#define PHY_BB_BBB_RX_CTRL_1_RECON_LMS_STEP_GET(x)                            (((x) & 0x00e00000) >> 21)
+#define PHY_BB_BBB_RX_CTRL_1_RECON_LMS_STEP_SET(x)                            (((x) << 21) & 0x00e00000)
+#define PHY_BB_BBB_RX_CTRL_1_SB_CHECK_WIN_MSB                                                         30
+#define PHY_BB_BBB_RX_CTRL_1_SB_CHECK_WIN_LSB                                                         24
+#define PHY_BB_BBB_RX_CTRL_1_SB_CHECK_WIN_MASK                                                0x7f000000
+#define PHY_BB_BBB_RX_CTRL_1_SB_CHECK_WIN_GET(x)                              (((x) & 0x7f000000) >> 24)
+#define PHY_BB_BBB_RX_CTRL_1_SB_CHECK_WIN_SET(x)                              (((x) << 24) & 0x7f000000)
+#define PHY_BB_BBB_RX_CTRL_1_EN_RX_ABORT_CCK_MSB                                                      31
+#define PHY_BB_BBB_RX_CTRL_1_EN_RX_ABORT_CCK_LSB                                                      31
+#define PHY_BB_BBB_RX_CTRL_1_EN_RX_ABORT_CCK_MASK                                             0x80000000
+#define PHY_BB_BBB_RX_CTRL_1_EN_RX_ABORT_CCK_GET(x)                           (((x) & 0x80000000) >> 31)
+#define PHY_BB_BBB_RX_CTRL_1_EN_RX_ABORT_CCK_SET(x)                           (((x) << 31) & 0x80000000)
+
+/* macros for BB_bbb_rx_ctrl_2 */
+#define PHY_BB_BBB_RX_CTRL_2_ADDRESS                                                          0x0000a214
+#define PHY_BB_BBB_RX_CTRL_2_OFFSET                                                           0x0000a214
+#define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_N_AVG_LONG_MSB                                                   5
+#define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_N_AVG_LONG_LSB                                                   0
+#define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_N_AVG_LONG_MASK                                         0x0000003f
+#define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_N_AVG_LONG_GET(x)                        (((x) & 0x0000003f) >> 0)
+#define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_N_AVG_LONG_SET(x)                        (((x) << 0) & 0x0000003f)
+#define PHY_BB_BBB_RX_CTRL_2_CHAN_AVG_LONG_MSB                                                        11
+#define PHY_BB_BBB_RX_CTRL_2_CHAN_AVG_LONG_LSB                                                         6
+#define PHY_BB_BBB_RX_CTRL_2_CHAN_AVG_LONG_MASK                                               0x00000fc0
+#define PHY_BB_BBB_RX_CTRL_2_CHAN_AVG_LONG_GET(x)                              (((x) & 0x00000fc0) >> 6)
+#define PHY_BB_BBB_RX_CTRL_2_CHAN_AVG_LONG_SET(x)                              (((x) << 6) & 0x00000fc0)
+#define PHY_BB_BBB_RX_CTRL_2_COARSE_TIM_THRESHOLD_3_MSB                                               16
+#define PHY_BB_BBB_RX_CTRL_2_COARSE_TIM_THRESHOLD_3_LSB                                               12
+#define PHY_BB_BBB_RX_CTRL_2_COARSE_TIM_THRESHOLD_3_MASK                                      0x0001f000
+#define PHY_BB_BBB_RX_CTRL_2_COARSE_TIM_THRESHOLD_3_GET(x)                    (((x) & 0x0001f000) >> 12)
+#define PHY_BB_BBB_RX_CTRL_2_COARSE_TIM_THRESHOLD_3_SET(x)                    (((x) << 12) & 0x0001f000)
+#define PHY_BB_BBB_RX_CTRL_2_FREQ_TRACK_UPDATE_PERIOD_MSB                                             21
+#define PHY_BB_BBB_RX_CTRL_2_FREQ_TRACK_UPDATE_PERIOD_LSB                                             17
+#define PHY_BB_BBB_RX_CTRL_2_FREQ_TRACK_UPDATE_PERIOD_MASK                                    0x003e0000
+#define PHY_BB_BBB_RX_CTRL_2_FREQ_TRACK_UPDATE_PERIOD_GET(x)                  (((x) & 0x003e0000) >> 17)
+#define PHY_BB_BBB_RX_CTRL_2_FREQ_TRACK_UPDATE_PERIOD_SET(x)                  (((x) << 17) & 0x003e0000)
+#define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_SCALING_PERIOD_MSB                                              25
+#define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_SCALING_PERIOD_LSB                                              22
+#define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_SCALING_PERIOD_MASK                                     0x03c00000
+#define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_SCALING_PERIOD_GET(x)                   (((x) & 0x03c00000) >> 22)
+#define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_SCALING_PERIOD_SET(x)                   (((x) << 22) & 0x03c00000)
+#define PHY_BB_BBB_RX_CTRL_2_LOOP_COEF_DPSK_C2_DATA_MSB                                               31
+#define PHY_BB_BBB_RX_CTRL_2_LOOP_COEF_DPSK_C2_DATA_LSB                                               26
+#define PHY_BB_BBB_RX_CTRL_2_LOOP_COEF_DPSK_C2_DATA_MASK                                      0xfc000000
+#define PHY_BB_BBB_RX_CTRL_2_LOOP_COEF_DPSK_C2_DATA_GET(x)                    (((x) & 0xfc000000) >> 26)
+#define PHY_BB_BBB_RX_CTRL_2_LOOP_COEF_DPSK_C2_DATA_SET(x)                    (((x) << 26) & 0xfc000000)
+
+/* macros for BB_bbb_rx_ctrl_3 */
+#define PHY_BB_BBB_RX_CTRL_3_ADDRESS                                                          0x0000a218
+#define PHY_BB_BBB_RX_CTRL_3_OFFSET                                                           0x0000a218
+#define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_DPSK_MSB                                                  7
+#define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_DPSK_LSB                                                  0
+#define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_DPSK_MASK                                        0x000000ff
+#define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_DPSK_GET(x)                       (((x) & 0x000000ff) >> 0)
+#define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_DPSK_SET(x)                       (((x) << 0) & 0x000000ff)
+#define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_CCK_MSB                                                  15
+#define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_CCK_LSB                                                   8
+#define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_CCK_MASK                                         0x0000ff00
+#define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_CCK_GET(x)                        (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_CCK_SET(x)                        (((x) << 8) & 0x0000ff00)
+#define PHY_BB_BBB_RX_CTRL_3_TIMER_N_SFD_MSB                                                          23
+#define PHY_BB_BBB_RX_CTRL_3_TIMER_N_SFD_LSB                                                          16
+#define PHY_BB_BBB_RX_CTRL_3_TIMER_N_SFD_MASK                                                 0x00ff0000
+#define PHY_BB_BBB_RX_CTRL_3_TIMER_N_SFD_GET(x)                               (((x) & 0x00ff0000) >> 16)
+#define PHY_BB_BBB_RX_CTRL_3_TIMER_N_SFD_SET(x)                               (((x) << 16) & 0x00ff0000)
+
+/* macros for BB_bbb_rx_ctrl_4 */
+#define PHY_BB_BBB_RX_CTRL_4_ADDRESS                                                          0x0000a21c
+#define PHY_BB_BBB_RX_CTRL_4_OFFSET                                                           0x0000a21c
+#define PHY_BB_BBB_RX_CTRL_4_TIMER_N_SYNC_MSB                                                          3
+#define PHY_BB_BBB_RX_CTRL_4_TIMER_N_SYNC_LSB                                                          0
+#define PHY_BB_BBB_RX_CTRL_4_TIMER_N_SYNC_MASK                                                0x0000000f
+#define PHY_BB_BBB_RX_CTRL_4_TIMER_N_SYNC_GET(x)                               (((x) & 0x0000000f) >> 0)
+#define PHY_BB_BBB_RX_CTRL_4_TIMER_N_SYNC_SET(x)                               (((x) << 0) & 0x0000000f)
+#define PHY_BB_BBB_RX_CTRL_4_TIM_ADJUST_TIMER_EXP_MSB                                                 15
+#define PHY_BB_BBB_RX_CTRL_4_TIM_ADJUST_TIMER_EXP_LSB                                                  4
+#define PHY_BB_BBB_RX_CTRL_4_TIM_ADJUST_TIMER_EXP_MASK                                        0x0000fff0
+#define PHY_BB_BBB_RX_CTRL_4_TIM_ADJUST_TIMER_EXP_GET(x)                       (((x) & 0x0000fff0) >> 4)
+#define PHY_BB_BBB_RX_CTRL_4_TIM_ADJUST_TIMER_EXP_SET(x)                       (((x) << 4) & 0x0000fff0)
+#define PHY_BB_BBB_RX_CTRL_4_FORCE_UNLOCKED_CLOCKS_MSB                                                16
+#define PHY_BB_BBB_RX_CTRL_4_FORCE_UNLOCKED_CLOCKS_LSB                                                16
+#define PHY_BB_BBB_RX_CTRL_4_FORCE_UNLOCKED_CLOCKS_MASK                                       0x00010000
+#define PHY_BB_BBB_RX_CTRL_4_FORCE_UNLOCKED_CLOCKS_GET(x)                     (((x) & 0x00010000) >> 16)
+#define PHY_BB_BBB_RX_CTRL_4_FORCE_UNLOCKED_CLOCKS_SET(x)                     (((x) << 16) & 0x00010000)
+#define PHY_BB_BBB_RX_CTRL_4_DYNAMIC_PREAM_SEL_MSB                                                    17
+#define PHY_BB_BBB_RX_CTRL_4_DYNAMIC_PREAM_SEL_LSB                                                    17
+#define PHY_BB_BBB_RX_CTRL_4_DYNAMIC_PREAM_SEL_MASK                                           0x00020000
+#define PHY_BB_BBB_RX_CTRL_4_DYNAMIC_PREAM_SEL_GET(x)                         (((x) & 0x00020000) >> 17)
+#define PHY_BB_BBB_RX_CTRL_4_DYNAMIC_PREAM_SEL_SET(x)                         (((x) << 17) & 0x00020000)
+#define PHY_BB_BBB_RX_CTRL_4_SHORT_PREAMBLE_MSB                                                       18
+#define PHY_BB_BBB_RX_CTRL_4_SHORT_PREAMBLE_LSB                                                       18
+#define PHY_BB_BBB_RX_CTRL_4_SHORT_PREAMBLE_MASK                                              0x00040000
+#define PHY_BB_BBB_RX_CTRL_4_SHORT_PREAMBLE_GET(x)                            (((x) & 0x00040000) >> 18)
+#define PHY_BB_BBB_RX_CTRL_4_SHORT_PREAMBLE_SET(x)                            (((x) << 18) & 0x00040000)
+#define PHY_BB_BBB_RX_CTRL_4_FREQ_EST_N_AVG_SHORT_MSB                                                 24
+#define PHY_BB_BBB_RX_CTRL_4_FREQ_EST_N_AVG_SHORT_LSB                                                 19
+#define PHY_BB_BBB_RX_CTRL_4_FREQ_EST_N_AVG_SHORT_MASK                                        0x01f80000
+#define PHY_BB_BBB_RX_CTRL_4_FREQ_EST_N_AVG_SHORT_GET(x)                      (((x) & 0x01f80000) >> 19)
+#define PHY_BB_BBB_RX_CTRL_4_FREQ_EST_N_AVG_SHORT_SET(x)                      (((x) << 19) & 0x01f80000)
+#define PHY_BB_BBB_RX_CTRL_4_CHAN_AVG_SHORT_MSB                                                       30
+#define PHY_BB_BBB_RX_CTRL_4_CHAN_AVG_SHORT_LSB                                                       25
+#define PHY_BB_BBB_RX_CTRL_4_CHAN_AVG_SHORT_MASK                                              0x7e000000
+#define PHY_BB_BBB_RX_CTRL_4_CHAN_AVG_SHORT_GET(x)                            (((x) & 0x7e000000) >> 25)
+#define PHY_BB_BBB_RX_CTRL_4_CHAN_AVG_SHORT_SET(x)                            (((x) << 25) & 0x7e000000)
+
+/* macros for BB_bbb_rx_ctrl_5 */
+#define PHY_BB_BBB_RX_CTRL_5_ADDRESS                                                          0x0000a220
+#define PHY_BB_BBB_RX_CTRL_5_OFFSET                                                           0x0000a220
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_DATA_MSB                                                4
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_DATA_LSB                                                0
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_DATA_MASK                                      0x0000001f
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_DATA_GET(x)                     (((x) & 0x0000001f) >> 0)
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_DATA_SET(x)                     (((x) << 0) & 0x0000001f)
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_HEAD_MSB                                                9
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_HEAD_LSB                                                5
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_HEAD_MASK                                      0x000003e0
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_HEAD_GET(x)                     (((x) & 0x000003e0) >> 5)
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_HEAD_SET(x)                     (((x) << 5) & 0x000003e0)
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C2_HEAD_MSB                                               15
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C2_HEAD_LSB                                               10
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C2_HEAD_MASK                                      0x0000fc00
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C2_HEAD_GET(x)                    (((x) & 0x0000fc00) >> 10)
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C2_HEAD_SET(x)                    (((x) << 10) & 0x0000fc00)
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C1_MSB                                                     20
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C1_LSB                                                     16
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C1_MASK                                            0x001f0000
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C1_GET(x)                          (((x) & 0x001f0000) >> 16)
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C1_SET(x)                          (((x) << 16) & 0x001f0000)
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C2_MSB                                                     26
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C2_LSB                                                     21
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C2_MASK                                            0x07e00000
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C2_GET(x)                          (((x) & 0x07e00000) >> 21)
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C2_SET(x)                          (((x) << 21) & 0x07e00000)
+
+/* macros for BB_bbb_rx_ctrl_6 */
+#define PHY_BB_BBB_RX_CTRL_6_ADDRESS                                                          0x0000a224
+#define PHY_BB_BBB_RX_CTRL_6_OFFSET                                                           0x0000a224
+#define PHY_BB_BBB_RX_CTRL_6_SYNC_START_DELAY_MSB                                                      9
+#define PHY_BB_BBB_RX_CTRL_6_SYNC_START_DELAY_LSB                                                      0
+#define PHY_BB_BBB_RX_CTRL_6_SYNC_START_DELAY_MASK                                            0x000003ff
+#define PHY_BB_BBB_RX_CTRL_6_SYNC_START_DELAY_GET(x)                           (((x) & 0x000003ff) >> 0)
+#define PHY_BB_BBB_RX_CTRL_6_SYNC_START_DELAY_SET(x)                           (((x) << 0) & 0x000003ff)
+#define PHY_BB_BBB_RX_CTRL_6_MAP_1S_TO_2S_MSB                                                         10
+#define PHY_BB_BBB_RX_CTRL_6_MAP_1S_TO_2S_LSB                                                         10
+#define PHY_BB_BBB_RX_CTRL_6_MAP_1S_TO_2S_MASK                                                0x00000400
+#define PHY_BB_BBB_RX_CTRL_6_MAP_1S_TO_2S_GET(x)                              (((x) & 0x00000400) >> 10)
+#define PHY_BB_BBB_RX_CTRL_6_MAP_1S_TO_2S_SET(x)                              (((x) << 10) & 0x00000400)
+#define PHY_BB_BBB_RX_CTRL_6_START_IIR_DELAY_MSB                                                      20
+#define PHY_BB_BBB_RX_CTRL_6_START_IIR_DELAY_LSB                                                      11
+#define PHY_BB_BBB_RX_CTRL_6_START_IIR_DELAY_MASK                                             0x001ff800
+#define PHY_BB_BBB_RX_CTRL_6_START_IIR_DELAY_GET(x)                           (((x) & 0x001ff800) >> 11)
+#define PHY_BB_BBB_RX_CTRL_6_START_IIR_DELAY_SET(x)                           (((x) << 11) & 0x001ff800)
+
+/* macros for BB_bbb_dagc_ctrl */
+#define PHY_BB_BBB_DAGC_CTRL_ADDRESS                                                          0x0000a228
+#define PHY_BB_BBB_DAGC_CTRL_OFFSET                                                           0x0000a228
+#define PHY_BB_BBB_DAGC_CTRL_ENABLE_DAGC_CCK_MSB                                                       0
+#define PHY_BB_BBB_DAGC_CTRL_ENABLE_DAGC_CCK_LSB                                                       0
+#define PHY_BB_BBB_DAGC_CTRL_ENABLE_DAGC_CCK_MASK                                             0x00000001
+#define PHY_BB_BBB_DAGC_CTRL_ENABLE_DAGC_CCK_GET(x)                            (((x) & 0x00000001) >> 0)
+#define PHY_BB_BBB_DAGC_CTRL_ENABLE_DAGC_CCK_SET(x)                            (((x) << 0) & 0x00000001)
+#define PHY_BB_BBB_DAGC_CTRL_DAGC_TARGET_PWR_CCK_MSB                                                   8
+#define PHY_BB_BBB_DAGC_CTRL_DAGC_TARGET_PWR_CCK_LSB                                                   1
+#define PHY_BB_BBB_DAGC_CTRL_DAGC_TARGET_PWR_CCK_MASK                                         0x000001fe
+#define PHY_BB_BBB_DAGC_CTRL_DAGC_TARGET_PWR_CCK_GET(x)                        (((x) & 0x000001fe) >> 1)
+#define PHY_BB_BBB_DAGC_CTRL_DAGC_TARGET_PWR_CCK_SET(x)                        (((x) << 1) & 0x000001fe)
+#define PHY_BB_BBB_DAGC_CTRL_ENABLE_BARKER_RSSI_THR_MSB                                                9
+#define PHY_BB_BBB_DAGC_CTRL_ENABLE_BARKER_RSSI_THR_LSB                                                9
+#define PHY_BB_BBB_DAGC_CTRL_ENABLE_BARKER_RSSI_THR_MASK                                      0x00000200
+#define PHY_BB_BBB_DAGC_CTRL_ENABLE_BARKER_RSSI_THR_GET(x)                     (((x) & 0x00000200) >> 9)
+#define PHY_BB_BBB_DAGC_CTRL_ENABLE_BARKER_RSSI_THR_SET(x)                     (((x) << 9) & 0x00000200)
+#define PHY_BB_BBB_DAGC_CTRL_BARKER_RSSI_THR_MSB                                                      16
+#define PHY_BB_BBB_DAGC_CTRL_BARKER_RSSI_THR_LSB                                                      10
+#define PHY_BB_BBB_DAGC_CTRL_BARKER_RSSI_THR_MASK                                             0x0001fc00
+#define PHY_BB_BBB_DAGC_CTRL_BARKER_RSSI_THR_GET(x)                           (((x) & 0x0001fc00) >> 10)
+#define PHY_BB_BBB_DAGC_CTRL_BARKER_RSSI_THR_SET(x)                           (((x) << 10) & 0x0001fc00)
+#define PHY_BB_BBB_DAGC_CTRL_ENABLE_FIRSTEP_SEL_MSB                                                   17
+#define PHY_BB_BBB_DAGC_CTRL_ENABLE_FIRSTEP_SEL_LSB                                                   17
+#define PHY_BB_BBB_DAGC_CTRL_ENABLE_FIRSTEP_SEL_MASK                                          0x00020000
+#define PHY_BB_BBB_DAGC_CTRL_ENABLE_FIRSTEP_SEL_GET(x)                        (((x) & 0x00020000) >> 17)
+#define PHY_BB_BBB_DAGC_CTRL_ENABLE_FIRSTEP_SEL_SET(x)                        (((x) << 17) & 0x00020000)
+#define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_2_MSB                                                            23
+#define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_2_LSB                                                            18
+#define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_2_MASK                                                   0x00fc0000
+#define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_2_GET(x)                                 (((x) & 0x00fc0000) >> 18)
+#define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_2_SET(x)                                 (((x) << 18) & 0x00fc0000)
+#define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_COUNT_LGMAX_MSB                                                  27
+#define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_COUNT_LGMAX_LSB                                                  24
+#define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_COUNT_LGMAX_MASK                                         0x0f000000
+#define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_COUNT_LGMAX_GET(x)                       (((x) & 0x0f000000) >> 24)
+#define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_COUNT_LGMAX_SET(x)                       (((x) << 24) & 0x0f000000)
+
+/* macros for BB_force_clken_cck */
+#define PHY_BB_FORCE_CLKEN_CCK_ADDRESS                                                        0x0000a22c
+#define PHY_BB_FORCE_CLKEN_CCK_OFFSET                                                         0x0000a22c
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE0_MSB                                                    0
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE0_LSB                                                    0
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE0_MASK                                          0x00000001
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE0_GET(x)                         (((x) & 0x00000001) >> 0)
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE0_SET(x)                         (((x) << 0) & 0x00000001)
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE1_MSB                                                    1
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE1_LSB                                                    1
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE1_MASK                                          0x00000002
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE1_GET(x)                         (((x) & 0x00000002) >> 1)
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE1_SET(x)                         (((x) << 1) & 0x00000002)
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE2_MSB                                                    2
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE2_LSB                                                    2
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE2_MASK                                          0x00000004
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE2_GET(x)                         (((x) & 0x00000004) >> 2)
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE2_SET(x)                         (((x) << 2) & 0x00000004)
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE3_MSB                                                    3
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE3_LSB                                                    3
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE3_MASK                                          0x00000008
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE3_GET(x)                         (((x) & 0x00000008) >> 3)
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE3_SET(x)                         (((x) << 3) & 0x00000008)
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ALWAYS_MSB                                                     4
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ALWAYS_LSB                                                     4
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ALWAYS_MASK                                           0x00000010
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ALWAYS_GET(x)                          (((x) & 0x00000010) >> 4)
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ALWAYS_SET(x)                          (((x) << 4) & 0x00000010)
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_TXSM_CLKEN_MSB                                                    5
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_TXSM_CLKEN_LSB                                                    5
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_TXSM_CLKEN_MASK                                          0x00000020
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_TXSM_CLKEN_GET(x)                         (((x) & 0x00000020) >> 5)
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_TXSM_CLKEN_SET(x)                         (((x) << 5) & 0x00000020)
+
+/* macros for BB_rx_clear_delay */
+#define PHY_BB_RX_CLEAR_DELAY_ADDRESS                                                         0x0000a230
+#define PHY_BB_RX_CLEAR_DELAY_OFFSET                                                          0x0000a230
+#define PHY_BB_RX_CLEAR_DELAY_OFDM_XR_RX_CLEAR_DELAY_MSB                                               9
+#define PHY_BB_RX_CLEAR_DELAY_OFDM_XR_RX_CLEAR_DELAY_LSB                                               0
+#define PHY_BB_RX_CLEAR_DELAY_OFDM_XR_RX_CLEAR_DELAY_MASK                                     0x000003ff
+#define PHY_BB_RX_CLEAR_DELAY_OFDM_XR_RX_CLEAR_DELAY_GET(x)                    (((x) & 0x000003ff) >> 0)
+#define PHY_BB_RX_CLEAR_DELAY_OFDM_XR_RX_CLEAR_DELAY_SET(x)                    (((x) << 0) & 0x000003ff)
+
+/* macros for BB_powertx_rate3 */
+#define PHY_BB_POWERTX_RATE3_ADDRESS                                                          0x0000a234
+#define PHY_BB_POWERTX_RATE3_OFFSET                                                           0x0000a234
+#define PHY_BB_POWERTX_RATE3_POWERTX_1L_MSB                                                            5
+#define PHY_BB_POWERTX_RATE3_POWERTX_1L_LSB                                                            0
+#define PHY_BB_POWERTX_RATE3_POWERTX_1L_MASK                                                  0x0000003f
+#define PHY_BB_POWERTX_RATE3_POWERTX_1L_GET(x)                                 (((x) & 0x0000003f) >> 0)
+#define PHY_BB_POWERTX_RATE3_POWERTX_1L_SET(x)                                 (((x) << 0) & 0x0000003f)
+#define PHY_BB_POWERTX_RATE3_POWERTX_2L_MSB                                                           21
+#define PHY_BB_POWERTX_RATE3_POWERTX_2L_LSB                                                           16
+#define PHY_BB_POWERTX_RATE3_POWERTX_2L_MASK                                                  0x003f0000
+#define PHY_BB_POWERTX_RATE3_POWERTX_2L_GET(x)                                (((x) & 0x003f0000) >> 16)
+#define PHY_BB_POWERTX_RATE3_POWERTX_2L_SET(x)                                (((x) << 16) & 0x003f0000)
+#define PHY_BB_POWERTX_RATE3_POWERTX_2S_MSB                                                           29
+#define PHY_BB_POWERTX_RATE3_POWERTX_2S_LSB                                                           24
+#define PHY_BB_POWERTX_RATE3_POWERTX_2S_MASK                                                  0x3f000000
+#define PHY_BB_POWERTX_RATE3_POWERTX_2S_GET(x)                                (((x) & 0x3f000000) >> 24)
+#define PHY_BB_POWERTX_RATE3_POWERTX_2S_SET(x)                                (((x) << 24) & 0x3f000000)
+
+/* macros for BB_powertx_rate4 */
+#define PHY_BB_POWERTX_RATE4_ADDRESS                                                          0x0000a238
+#define PHY_BB_POWERTX_RATE4_OFFSET                                                           0x0000a238
+#define PHY_BB_POWERTX_RATE4_POWERTX_55L_MSB                                                           5
+#define PHY_BB_POWERTX_RATE4_POWERTX_55L_LSB                                                           0
+#define PHY_BB_POWERTX_RATE4_POWERTX_55L_MASK                                                 0x0000003f
+#define PHY_BB_POWERTX_RATE4_POWERTX_55L_GET(x)                                (((x) & 0x0000003f) >> 0)
+#define PHY_BB_POWERTX_RATE4_POWERTX_55L_SET(x)                                (((x) << 0) & 0x0000003f)
+#define PHY_BB_POWERTX_RATE4_POWERTX_55S_MSB                                                          13
+#define PHY_BB_POWERTX_RATE4_POWERTX_55S_LSB                                                           8
+#define PHY_BB_POWERTX_RATE4_POWERTX_55S_MASK                                                 0x00003f00
+#define PHY_BB_POWERTX_RATE4_POWERTX_55S_GET(x)                                (((x) & 0x00003f00) >> 8)
+#define PHY_BB_POWERTX_RATE4_POWERTX_55S_SET(x)                                (((x) << 8) & 0x00003f00)
+#define PHY_BB_POWERTX_RATE4_POWERTX_11L_MSB                                                          21
+#define PHY_BB_POWERTX_RATE4_POWERTX_11L_LSB                                                          16
+#define PHY_BB_POWERTX_RATE4_POWERTX_11L_MASK                                                 0x003f0000
+#define PHY_BB_POWERTX_RATE4_POWERTX_11L_GET(x)                               (((x) & 0x003f0000) >> 16)
+#define PHY_BB_POWERTX_RATE4_POWERTX_11L_SET(x)                               (((x) << 16) & 0x003f0000)
+#define PHY_BB_POWERTX_RATE4_POWERTX_11S_MSB                                                          29
+#define PHY_BB_POWERTX_RATE4_POWERTX_11S_LSB                                                          24
+#define PHY_BB_POWERTX_RATE4_POWERTX_11S_MASK                                                 0x3f000000
+#define PHY_BB_POWERTX_RATE4_POWERTX_11S_GET(x)                               (((x) & 0x3f000000) >> 24)
+#define PHY_BB_POWERTX_RATE4_POWERTX_11S_SET(x)                               (((x) << 24) & 0x3f000000)
+
+/* macros for BB_cck_spur_mit */
+#define PHY_BB_CCK_SPUR_MIT_ADDRESS                                                           0x0000a240
+#define PHY_BB_CCK_SPUR_MIT_OFFSET                                                            0x0000a240
+#define PHY_BB_CCK_SPUR_MIT_USE_CCK_SPUR_MIT_MSB                                                       0
+#define PHY_BB_CCK_SPUR_MIT_USE_CCK_SPUR_MIT_LSB                                                       0
+#define PHY_BB_CCK_SPUR_MIT_USE_CCK_SPUR_MIT_MASK                                             0x00000001
+#define PHY_BB_CCK_SPUR_MIT_USE_CCK_SPUR_MIT_GET(x)                            (((x) & 0x00000001) >> 0)
+#define PHY_BB_CCK_SPUR_MIT_USE_CCK_SPUR_MIT_SET(x)                            (((x) << 0) & 0x00000001)
+#define PHY_BB_CCK_SPUR_MIT_SPUR_RSSI_THR_MSB                                                          8
+#define PHY_BB_CCK_SPUR_MIT_SPUR_RSSI_THR_LSB                                                          1
+#define PHY_BB_CCK_SPUR_MIT_SPUR_RSSI_THR_MASK                                                0x000001fe
+#define PHY_BB_CCK_SPUR_MIT_SPUR_RSSI_THR_GET(x)                               (((x) & 0x000001fe) >> 1)
+#define PHY_BB_CCK_SPUR_MIT_SPUR_RSSI_THR_SET(x)                               (((x) << 1) & 0x000001fe)
+#define PHY_BB_CCK_SPUR_MIT_CCK_SPUR_FREQ_MSB                                                         28
+#define PHY_BB_CCK_SPUR_MIT_CCK_SPUR_FREQ_LSB                                                          9
+#define PHY_BB_CCK_SPUR_MIT_CCK_SPUR_FREQ_MASK                                                0x1ffffe00
+#define PHY_BB_CCK_SPUR_MIT_CCK_SPUR_FREQ_GET(x)                               (((x) & 0x1ffffe00) >> 9)
+#define PHY_BB_CCK_SPUR_MIT_CCK_SPUR_FREQ_SET(x)                               (((x) << 9) & 0x1ffffe00)
+#define PHY_BB_CCK_SPUR_MIT_SPUR_FILTER_TYPE_MSB                                                      30
+#define PHY_BB_CCK_SPUR_MIT_SPUR_FILTER_TYPE_LSB                                                      29
+#define PHY_BB_CCK_SPUR_MIT_SPUR_FILTER_TYPE_MASK                                             0x60000000
+#define PHY_BB_CCK_SPUR_MIT_SPUR_FILTER_TYPE_GET(x)                           (((x) & 0x60000000) >> 29)
+#define PHY_BB_CCK_SPUR_MIT_SPUR_FILTER_TYPE_SET(x)                           (((x) << 29) & 0x60000000)
+
+/* macros for BB_panic_watchdog_status */
+#define PHY_BB_PANIC_WATCHDOG_STATUS_ADDRESS                                                  0x0000a244
+#define PHY_BB_PANIC_WATCHDOG_STATUS_OFFSET                                                   0x0000a244
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_1_MSB                                       2
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_1_LSB                                       0
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_1_MASK                             0x00000007
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_1_GET(x)            (((x) & 0x00000007) >> 0)
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_1_SET(x)            (((x) << 0) & 0x00000007)
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_DET_HANG_MSB                                       3
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_DET_HANG_LSB                                       3
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_DET_HANG_MASK                             0x00000008
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_DET_HANG_GET(x)            (((x) & 0x00000008) >> 3)
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_DET_HANG_SET(x)            (((x) << 3) & 0x00000008)
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_2_MSB                                       7
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_2_LSB                                       4
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_2_MASK                             0x000000f0
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_2_GET(x)            (((x) & 0x000000f0) >> 4)
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_2_SET(x)            (((x) << 4) & 0x000000f0)
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_3_MSB                                      11
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_3_LSB                                       8
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_3_MASK                             0x00000f00
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_3_GET(x)            (((x) & 0x00000f00) >> 8)
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_3_SET(x)            (((x) << 8) & 0x00000f00)
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_4_MSB                                      15
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_4_LSB                                      12
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_4_MASK                             0x0000f000
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_4_GET(x)           (((x) & 0x0000f000) >> 12)
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_4_SET(x)           (((x) << 12) & 0x0000f000)
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_5_MSB                                      19
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_5_LSB                                      16
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_5_MASK                             0x000f0000
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_5_GET(x)           (((x) & 0x000f0000) >> 16)
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_5_SET(x)           (((x) << 16) & 0x000f0000)
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_6_MSB                                      23
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_6_LSB                                      20
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_6_MASK                             0x00f00000
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_6_GET(x)           (((x) & 0x00f00000) >> 20)
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_6_SET(x)           (((x) << 20) & 0x00f00000)
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_7_MSB                                      27
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_7_LSB                                      24
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_7_MASK                             0x0f000000
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_7_GET(x)           (((x) & 0x0f000000) >> 24)
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_7_SET(x)           (((x) << 24) & 0x0f000000)
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_8_MSB                                      31
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_8_LSB                                      28
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_8_MASK                             0xf0000000
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_8_GET(x)           (((x) & 0xf0000000) >> 28)
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_8_SET(x)           (((x) << 28) & 0xf0000000)
+
+/* macros for BB_panic_watchdog_ctrl_1 */
+#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ADDRESS                                                  0x0000a248
+#define PHY_BB_PANIC_WATCHDOG_CTRL_1_OFFSET                                                   0x0000a248
+#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_NON_IDLE_MSB                                0
+#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_NON_IDLE_LSB                                0
+#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_NON_IDLE_MASK                      0x00000001
+#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_NON_IDLE_GET(x)     (((x) & 0x00000001) >> 0)
+#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_NON_IDLE_SET(x)     (((x) << 0) & 0x00000001)
+#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_IDLE_MSB                                    1
+#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_IDLE_LSB                                    1
+#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_IDLE_MASK                          0x00000002
+#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_IDLE_GET(x)         (((x) & 0x00000002) >> 1)
+#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_IDLE_SET(x)         (((x) << 1) & 0x00000002)
+#define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_NON_IDLE_LIMIT_MSB                                15
+#define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_NON_IDLE_LIMIT_LSB                                 2
+#define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_NON_IDLE_LIMIT_MASK                       0x0000fffc
+#define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_NON_IDLE_LIMIT_GET(x)      (((x) & 0x0000fffc) >> 2)
+#define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_NON_IDLE_LIMIT_SET(x)      (((x) << 2) & 0x0000fffc)
+#define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_IDLE_LIMIT_MSB                                    31
+#define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_IDLE_LIMIT_LSB                                    16
+#define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_IDLE_LIMIT_MASK                           0xffff0000
+#define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_IDLE_LIMIT_GET(x)         (((x) & 0xffff0000) >> 16)
+#define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_IDLE_LIMIT_SET(x)         (((x) << 16) & 0xffff0000)
+
+/* macros for BB_panic_watchdog_ctrl_2 */
+#define PHY_BB_PANIC_WATCHDOG_CTRL_2_ADDRESS                                                  0x0000a24c
+#define PHY_BB_PANIC_WATCHDOG_CTRL_2_OFFSET                                                   0x0000a24c
+#define PHY_BB_PANIC_WATCHDOG_CTRL_2_FORCE_FAST_ADC_CLK_MSB                                            0
+#define PHY_BB_PANIC_WATCHDOG_CTRL_2_FORCE_FAST_ADC_CLK_LSB                                            0
+#define PHY_BB_PANIC_WATCHDOG_CTRL_2_FORCE_FAST_ADC_CLK_MASK                                  0x00000001
+#define PHY_BB_PANIC_WATCHDOG_CTRL_2_FORCE_FAST_ADC_CLK_GET(x)                 (((x) & 0x00000001) >> 0)
+#define PHY_BB_PANIC_WATCHDOG_CTRL_2_FORCE_FAST_ADC_CLK_SET(x)                 (((x) << 0) & 0x00000001)
+#define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_RESET_ENA_MSB                                      1
+#define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_RESET_ENA_LSB                                      1
+#define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_RESET_ENA_MASK                            0x00000002
+#define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_RESET_ENA_GET(x)           (((x) & 0x00000002) >> 1)
+#define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_RESET_ENA_SET(x)           (((x) << 1) & 0x00000002)
+#define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_IRQ_ENA_MSB                                        2
+#define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_IRQ_ENA_LSB                                        2
+#define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_IRQ_ENA_MASK                              0x00000004
+#define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_IRQ_ENA_GET(x)             (((x) & 0x00000004) >> 2)
+#define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_IRQ_ENA_SET(x)             (((x) << 2) & 0x00000004)
+
+/* macros for BB_iqcorr_ctrl_cck */
+#define PHY_BB_IQCORR_CTRL_CCK_ADDRESS                                                        0x0000a250
+#define PHY_BB_IQCORR_CTRL_CCK_OFFSET                                                         0x0000a250
+#define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_Q_COFF_CCK_MSB                                                 4
+#define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_Q_COFF_CCK_LSB                                                 0
+#define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_Q_COFF_CCK_MASK                                       0x0000001f
+#define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_Q_COFF_CCK_GET(x)                      (((x) & 0x0000001f) >> 0)
+#define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_Q_COFF_CCK_SET(x)                      (((x) << 0) & 0x0000001f)
+#define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_I_COFF_CCK_MSB                                                10
+#define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_I_COFF_CCK_LSB                                                 5
+#define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_I_COFF_CCK_MASK                                       0x000007e0
+#define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_I_COFF_CCK_GET(x)                      (((x) & 0x000007e0) >> 5)
+#define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_I_COFF_CCK_SET(x)                      (((x) << 5) & 0x000007e0)
+#define PHY_BB_IQCORR_CTRL_CCK_ENABLE_IQCORR_CCK_MSB                                                  11
+#define PHY_BB_IQCORR_CTRL_CCK_ENABLE_IQCORR_CCK_LSB                                                  11
+#define PHY_BB_IQCORR_CTRL_CCK_ENABLE_IQCORR_CCK_MASK                                         0x00000800
+#define PHY_BB_IQCORR_CTRL_CCK_ENABLE_IQCORR_CCK_GET(x)                       (((x) & 0x00000800) >> 11)
+#define PHY_BB_IQCORR_CTRL_CCK_ENABLE_IQCORR_CCK_SET(x)                       (((x) << 11) & 0x00000800)
+#define PHY_BB_IQCORR_CTRL_CCK_RXCAL_MEAS_TIME_SEL_MSB                                                13
+#define PHY_BB_IQCORR_CTRL_CCK_RXCAL_MEAS_TIME_SEL_LSB                                                12
+#define PHY_BB_IQCORR_CTRL_CCK_RXCAL_MEAS_TIME_SEL_MASK                                       0x00003000
+#define PHY_BB_IQCORR_CTRL_CCK_RXCAL_MEAS_TIME_SEL_GET(x)                     (((x) & 0x00003000) >> 12)
+#define PHY_BB_IQCORR_CTRL_CCK_RXCAL_MEAS_TIME_SEL_SET(x)                     (((x) << 12) & 0x00003000)
+#define PHY_BB_IQCORR_CTRL_CCK_CLCAL_MEAS_TIME_SEL_MSB                                                15
+#define PHY_BB_IQCORR_CTRL_CCK_CLCAL_MEAS_TIME_SEL_LSB                                                14
+#define PHY_BB_IQCORR_CTRL_CCK_CLCAL_MEAS_TIME_SEL_MASK                                       0x0000c000
+#define PHY_BB_IQCORR_CTRL_CCK_CLCAL_MEAS_TIME_SEL_GET(x)                     (((x) & 0x0000c000) >> 14)
+#define PHY_BB_IQCORR_CTRL_CCK_CLCAL_MEAS_TIME_SEL_SET(x)                     (((x) << 14) & 0x0000c000)
+#define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_INIT_RFGAIN_MSB                                                 20
+#define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_INIT_RFGAIN_LSB                                                 16
+#define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_INIT_RFGAIN_MASK                                        0x001f0000
+#define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_INIT_RFGAIN_GET(x)                      (((x) & 0x001f0000) >> 16)
+#define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_INIT_RFGAIN_SET(x)                      (((x) << 16) & 0x001f0000)
+#define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_PAL_MODE_MSB                                                    21
+#define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_PAL_MODE_LSB                                                    21
+#define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_PAL_MODE_MASK                                           0x00200000
+#define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_PAL_MODE_GET(x)                         (((x) & 0x00200000) >> 21)
+#define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_PAL_MODE_SET(x)                         (((x) << 21) & 0x00200000)
+
+/* macros for BB_bluetooth_cntl */
+#define PHY_BB_BLUETOOTH_CNTL_ADDRESS                                                         0x0000a254
+#define PHY_BB_BLUETOOTH_CNTL_OFFSET                                                          0x0000a254
+#define PHY_BB_BLUETOOTH_CNTL_BT_BREAK_CCK_EN_MSB                                                      0
+#define PHY_BB_BLUETOOTH_CNTL_BT_BREAK_CCK_EN_LSB                                                      0
+#define PHY_BB_BLUETOOTH_CNTL_BT_BREAK_CCK_EN_MASK                                            0x00000001
+#define PHY_BB_BLUETOOTH_CNTL_BT_BREAK_CCK_EN_GET(x)                           (((x) & 0x00000001) >> 0)
+#define PHY_BB_BLUETOOTH_CNTL_BT_BREAK_CCK_EN_SET(x)                           (((x) << 0) & 0x00000001)
+#define PHY_BB_BLUETOOTH_CNTL_BT_ANT_HALT_WLAN_MSB                                                     1
+#define PHY_BB_BLUETOOTH_CNTL_BT_ANT_HALT_WLAN_LSB                                                     1
+#define PHY_BB_BLUETOOTH_CNTL_BT_ANT_HALT_WLAN_MASK                                           0x00000002
+#define PHY_BB_BLUETOOTH_CNTL_BT_ANT_HALT_WLAN_GET(x)                          (((x) & 0x00000002) >> 1)
+#define PHY_BB_BLUETOOTH_CNTL_BT_ANT_HALT_WLAN_SET(x)                          (((x) << 1) & 0x00000002)
+
+/* macros for BB_tpc_1 */
+#define PHY_BB_TPC_1_ADDRESS                                                                  0x0000a258
+#define PHY_BB_TPC_1_OFFSET                                                                   0x0000a258
+#define PHY_BB_TPC_1_FORCE_DAC_GAIN_MSB                                                                0
+#define PHY_BB_TPC_1_FORCE_DAC_GAIN_LSB                                                                0
+#define PHY_BB_TPC_1_FORCE_DAC_GAIN_MASK                                                      0x00000001
+#define PHY_BB_TPC_1_FORCE_DAC_GAIN_GET(x)                                     (((x) & 0x00000001) >> 0)
+#define PHY_BB_TPC_1_FORCE_DAC_GAIN_SET(x)                                     (((x) << 0) & 0x00000001)
+#define PHY_BB_TPC_1_FORCED_DAC_GAIN_MSB                                                               5
+#define PHY_BB_TPC_1_FORCED_DAC_GAIN_LSB                                                               1
+#define PHY_BB_TPC_1_FORCED_DAC_GAIN_MASK                                                     0x0000003e
+#define PHY_BB_TPC_1_FORCED_DAC_GAIN_GET(x)                                    (((x) & 0x0000003e) >> 1)
+#define PHY_BB_TPC_1_FORCED_DAC_GAIN_SET(x)                                    (((x) << 1) & 0x0000003e)
+#define PHY_BB_TPC_1_PD_DC_OFFSET_TARGET_MSB                                                          13
+#define PHY_BB_TPC_1_PD_DC_OFFSET_TARGET_LSB                                                           6
+#define PHY_BB_TPC_1_PD_DC_OFFSET_TARGET_MASK                                                 0x00003fc0
+#define PHY_BB_TPC_1_PD_DC_OFFSET_TARGET_GET(x)                                (((x) & 0x00003fc0) >> 6)
+#define PHY_BB_TPC_1_PD_DC_OFFSET_TARGET_SET(x)                                (((x) << 6) & 0x00003fc0)
+#define PHY_BB_TPC_1_NUM_PD_GAIN_MSB                                                                  15
+#define PHY_BB_TPC_1_NUM_PD_GAIN_LSB                                                                  14
+#define PHY_BB_TPC_1_NUM_PD_GAIN_MASK                                                         0x0000c000
+#define PHY_BB_TPC_1_NUM_PD_GAIN_GET(x)                                       (((x) & 0x0000c000) >> 14)
+#define PHY_BB_TPC_1_NUM_PD_GAIN_SET(x)                                       (((x) << 14) & 0x0000c000)
+#define PHY_BB_TPC_1_PD_GAIN_SETTING1_MSB                                                             17
+#define PHY_BB_TPC_1_PD_GAIN_SETTING1_LSB                                                             16
+#define PHY_BB_TPC_1_PD_GAIN_SETTING1_MASK                                                    0x00030000
+#define PHY_BB_TPC_1_PD_GAIN_SETTING1_GET(x)                                  (((x) & 0x00030000) >> 16)
+#define PHY_BB_TPC_1_PD_GAIN_SETTING1_SET(x)                                  (((x) << 16) & 0x00030000)
+#define PHY_BB_TPC_1_PD_GAIN_SETTING2_MSB                                                             19
+#define PHY_BB_TPC_1_PD_GAIN_SETTING2_LSB                                                             18
+#define PHY_BB_TPC_1_PD_GAIN_SETTING2_MASK                                                    0x000c0000
+#define PHY_BB_TPC_1_PD_GAIN_SETTING2_GET(x)                                  (((x) & 0x000c0000) >> 18)
+#define PHY_BB_TPC_1_PD_GAIN_SETTING2_SET(x)                                  (((x) << 18) & 0x000c0000)
+#define PHY_BB_TPC_1_PD_GAIN_SETTING3_MSB                                                             21
+#define PHY_BB_TPC_1_PD_GAIN_SETTING3_LSB                                                             20
+#define PHY_BB_TPC_1_PD_GAIN_SETTING3_MASK                                                    0x00300000
+#define PHY_BB_TPC_1_PD_GAIN_SETTING3_GET(x)                                  (((x) & 0x00300000) >> 20)
+#define PHY_BB_TPC_1_PD_GAIN_SETTING3_SET(x)                                  (((x) << 20) & 0x00300000)
+#define PHY_BB_TPC_1_ENABLE_PD_CALIBRATE_MSB                                                          22
+#define PHY_BB_TPC_1_ENABLE_PD_CALIBRATE_LSB                                                          22
+#define PHY_BB_TPC_1_ENABLE_PD_CALIBRATE_MASK                                                 0x00400000
+#define PHY_BB_TPC_1_ENABLE_PD_CALIBRATE_GET(x)                               (((x) & 0x00400000) >> 22)
+#define PHY_BB_TPC_1_ENABLE_PD_CALIBRATE_SET(x)                               (((x) << 22) & 0x00400000)
+#define PHY_BB_TPC_1_PD_CALIBRATE_WAIT_MSB                                                            28
+#define PHY_BB_TPC_1_PD_CALIBRATE_WAIT_LSB                                                            23
+#define PHY_BB_TPC_1_PD_CALIBRATE_WAIT_MASK                                                   0x1f800000
+#define PHY_BB_TPC_1_PD_CALIBRATE_WAIT_GET(x)                                 (((x) & 0x1f800000) >> 23)
+#define PHY_BB_TPC_1_PD_CALIBRATE_WAIT_SET(x)                                 (((x) << 23) & 0x1f800000)
+#define PHY_BB_TPC_1_FORCE_PDADC_GAIN_MSB                                                             29
+#define PHY_BB_TPC_1_FORCE_PDADC_GAIN_LSB                                                             29
+#define PHY_BB_TPC_1_FORCE_PDADC_GAIN_MASK                                                    0x20000000
+#define PHY_BB_TPC_1_FORCE_PDADC_GAIN_GET(x)                                  (((x) & 0x20000000) >> 29)
+#define PHY_BB_TPC_1_FORCE_PDADC_GAIN_SET(x)                                  (((x) << 29) & 0x20000000)
+#define PHY_BB_TPC_1_FORCED_PDADC_GAIN_MSB                                                            31
+#define PHY_BB_TPC_1_FORCED_PDADC_GAIN_LSB                                                            30
+#define PHY_BB_TPC_1_FORCED_PDADC_GAIN_MASK                                                   0xc0000000
+#define PHY_BB_TPC_1_FORCED_PDADC_GAIN_GET(x)                                 (((x) & 0xc0000000) >> 30)
+#define PHY_BB_TPC_1_FORCED_PDADC_GAIN_SET(x)                                 (((x) << 30) & 0xc0000000)
+
+/* macros for BB_tpc_2 */
+#define PHY_BB_TPC_2_ADDRESS                                                                  0x0000a25c
+#define PHY_BB_TPC_2_OFFSET                                                                   0x0000a25c
+#define PHY_BB_TPC_2_TX_FRAME_TO_PDADC_ON_MSB                                                          7
+#define PHY_BB_TPC_2_TX_FRAME_TO_PDADC_ON_LSB                                                          0
+#define PHY_BB_TPC_2_TX_FRAME_TO_PDADC_ON_MASK                                                0x000000ff
+#define PHY_BB_TPC_2_TX_FRAME_TO_PDADC_ON_GET(x)                               (((x) & 0x000000ff) >> 0)
+#define PHY_BB_TPC_2_TX_FRAME_TO_PDADC_ON_SET(x)                               (((x) << 0) & 0x000000ff)
+#define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_OFDM_MSB                                                      15
+#define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_OFDM_LSB                                                       8
+#define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_OFDM_MASK                                             0x0000ff00
+#define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_OFDM_GET(x)                            (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_OFDM_SET(x)                            (((x) << 8) & 0x0000ff00)
+#define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_CCK_MSB                                                       23
+#define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_CCK_LSB                                                       16
+#define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_CCK_MASK                                              0x00ff0000
+#define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_CCK_GET(x)                            (((x) & 0x00ff0000) >> 16)
+#define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_CCK_SET(x)                            (((x) << 16) & 0x00ff0000)
+
+/* macros for BB_tpc_3 */
+#define PHY_BB_TPC_3_ADDRESS                                                                  0x0000a260
+#define PHY_BB_TPC_3_OFFSET                                                                   0x0000a260
+#define PHY_BB_TPC_3_TX_END_TO_PDADC_ON_MSB                                                            7
+#define PHY_BB_TPC_3_TX_END_TO_PDADC_ON_LSB                                                            0
+#define PHY_BB_TPC_3_TX_END_TO_PDADC_ON_MASK                                                  0x000000ff
+#define PHY_BB_TPC_3_TX_END_TO_PDADC_ON_GET(x)                                 (((x) & 0x000000ff) >> 0)
+#define PHY_BB_TPC_3_TX_END_TO_PDADC_ON_SET(x)                                 (((x) << 0) & 0x000000ff)
+#define PHY_BB_TPC_3_TX_END_TO_PD_ACC_ON_MSB                                                          15
+#define PHY_BB_TPC_3_TX_END_TO_PD_ACC_ON_LSB                                                           8
+#define PHY_BB_TPC_3_TX_END_TO_PD_ACC_ON_MASK                                                 0x0000ff00
+#define PHY_BB_TPC_3_TX_END_TO_PD_ACC_ON_GET(x)                                (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_TPC_3_TX_END_TO_PD_ACC_ON_SET(x)                                (((x) << 8) & 0x0000ff00)
+#define PHY_BB_TPC_3_PD_ACC_WINDOW_DC_OFF_MSB                                                         18
+#define PHY_BB_TPC_3_PD_ACC_WINDOW_DC_OFF_LSB                                                         16
+#define PHY_BB_TPC_3_PD_ACC_WINDOW_DC_OFF_MASK                                                0x00070000
+#define PHY_BB_TPC_3_PD_ACC_WINDOW_DC_OFF_GET(x)                              (((x) & 0x00070000) >> 16)
+#define PHY_BB_TPC_3_PD_ACC_WINDOW_DC_OFF_SET(x)                              (((x) << 16) & 0x00070000)
+#define PHY_BB_TPC_3_PD_ACC_WINDOW_CAL_MSB                                                            21
+#define PHY_BB_TPC_3_PD_ACC_WINDOW_CAL_LSB                                                            19
+#define PHY_BB_TPC_3_PD_ACC_WINDOW_CAL_MASK                                                   0x00380000
+#define PHY_BB_TPC_3_PD_ACC_WINDOW_CAL_GET(x)                                 (((x) & 0x00380000) >> 19)
+#define PHY_BB_TPC_3_PD_ACC_WINDOW_CAL_SET(x)                                 (((x) << 19) & 0x00380000)
+#define PHY_BB_TPC_3_PD_ACC_WINDOW_OFDM_MSB                                                           24
+#define PHY_BB_TPC_3_PD_ACC_WINDOW_OFDM_LSB                                                           22
+#define PHY_BB_TPC_3_PD_ACC_WINDOW_OFDM_MASK                                                  0x01c00000
+#define PHY_BB_TPC_3_PD_ACC_WINDOW_OFDM_GET(x)                                (((x) & 0x01c00000) >> 22)
+#define PHY_BB_TPC_3_PD_ACC_WINDOW_OFDM_SET(x)                                (((x) << 22) & 0x01c00000)
+#define PHY_BB_TPC_3_PD_ACC_WINDOW_CCK_MSB                                                            27
+#define PHY_BB_TPC_3_PD_ACC_WINDOW_CCK_LSB                                                            25
+#define PHY_BB_TPC_3_PD_ACC_WINDOW_CCK_MASK                                                   0x0e000000
+#define PHY_BB_TPC_3_PD_ACC_WINDOW_CCK_GET(x)                                 (((x) & 0x0e000000) >> 25)
+#define PHY_BB_TPC_3_PD_ACC_WINDOW_CCK_SET(x)                                 (((x) << 25) & 0x0e000000)
+#define PHY_BB_TPC_3_TPC_CLK_GATE_ENABLE_MSB                                                          31
+#define PHY_BB_TPC_3_TPC_CLK_GATE_ENABLE_LSB                                                          31
+#define PHY_BB_TPC_3_TPC_CLK_GATE_ENABLE_MASK                                                 0x80000000
+#define PHY_BB_TPC_3_TPC_CLK_GATE_ENABLE_GET(x)                               (((x) & 0x80000000) >> 31)
+#define PHY_BB_TPC_3_TPC_CLK_GATE_ENABLE_SET(x)                               (((x) << 31) & 0x80000000)
+
+/* macros for BB_tpc_4_b0 */
+#define PHY_BB_TPC_4_B0_ADDRESS                                                               0x0000a264
+#define PHY_BB_TPC_4_B0_OFFSET                                                                0x0000a264
+#define PHY_BB_TPC_4_B0_PD_AVG_VALID_0_MSB                                                             0
+#define PHY_BB_TPC_4_B0_PD_AVG_VALID_0_LSB                                                             0
+#define PHY_BB_TPC_4_B0_PD_AVG_VALID_0_MASK                                                   0x00000001
+#define PHY_BB_TPC_4_B0_PD_AVG_VALID_0_GET(x)                                  (((x) & 0x00000001) >> 0)
+#define PHY_BB_TPC_4_B0_PD_AVG_OUT_0_MSB                                                               8
+#define PHY_BB_TPC_4_B0_PD_AVG_OUT_0_LSB                                                               1
+#define PHY_BB_TPC_4_B0_PD_AVG_OUT_0_MASK                                                     0x000001fe
+#define PHY_BB_TPC_4_B0_PD_AVG_OUT_0_GET(x)                                    (((x) & 0x000001fe) >> 1)
+#define PHY_BB_TPC_4_B0_DAC_GAIN_0_MSB                                                                13
+#define PHY_BB_TPC_4_B0_DAC_GAIN_0_LSB                                                                 9
+#define PHY_BB_TPC_4_B0_DAC_GAIN_0_MASK                                                       0x00003e00
+#define PHY_BB_TPC_4_B0_DAC_GAIN_0_GET(x)                                      (((x) & 0x00003e00) >> 9)
+#define PHY_BB_TPC_4_B0_TX_GAIN_SETTING_0_MSB                                                         19
+#define PHY_BB_TPC_4_B0_TX_GAIN_SETTING_0_LSB                                                         14
+#define PHY_BB_TPC_4_B0_TX_GAIN_SETTING_0_MASK                                                0x000fc000
+#define PHY_BB_TPC_4_B0_TX_GAIN_SETTING_0_GET(x)                              (((x) & 0x000fc000) >> 14)
+#define PHY_BB_TPC_4_B0_RATE_SENT_0_MSB                                                               24
+#define PHY_BB_TPC_4_B0_RATE_SENT_0_LSB                                                               20
+#define PHY_BB_TPC_4_B0_RATE_SENT_0_MASK                                                      0x01f00000
+#define PHY_BB_TPC_4_B0_RATE_SENT_0_GET(x)                                    (((x) & 0x01f00000) >> 20)
+#define PHY_BB_TPC_4_B0_ERROR_EST_UPDATE_POWER_THRESH_MSB                                             30
+#define PHY_BB_TPC_4_B0_ERROR_EST_UPDATE_POWER_THRESH_LSB                                             25
+#define PHY_BB_TPC_4_B0_ERROR_EST_UPDATE_POWER_THRESH_MASK                                    0x7e000000
+#define PHY_BB_TPC_4_B0_ERROR_EST_UPDATE_POWER_THRESH_GET(x)                  (((x) & 0x7e000000) >> 25)
+#define PHY_BB_TPC_4_B0_ERROR_EST_UPDATE_POWER_THRESH_SET(x)                  (((x) << 25) & 0x7e000000)
+
+/* macros for BB_analog_swap */
+#define PHY_BB_ANALOG_SWAP_ADDRESS                                                            0x0000a268
+#define PHY_BB_ANALOG_SWAP_OFFSET                                                             0x0000a268
+#define PHY_BB_ANALOG_SWAP_ANALOG_RX_SWAP_CNTL_MSB                                                     2
+#define PHY_BB_ANALOG_SWAP_ANALOG_RX_SWAP_CNTL_LSB                                                     0
+#define PHY_BB_ANALOG_SWAP_ANALOG_RX_SWAP_CNTL_MASK                                           0x00000007
+#define PHY_BB_ANALOG_SWAP_ANALOG_RX_SWAP_CNTL_GET(x)                          (((x) & 0x00000007) >> 0)
+#define PHY_BB_ANALOG_SWAP_ANALOG_RX_SWAP_CNTL_SET(x)                          (((x) << 0) & 0x00000007)
+#define PHY_BB_ANALOG_SWAP_ANALOG_TX_SWAP_CNTL_MSB                                                     5
+#define PHY_BB_ANALOG_SWAP_ANALOG_TX_SWAP_CNTL_LSB                                                     3
+#define PHY_BB_ANALOG_SWAP_ANALOG_TX_SWAP_CNTL_MASK                                           0x00000038
+#define PHY_BB_ANALOG_SWAP_ANALOG_TX_SWAP_CNTL_GET(x)                          (((x) & 0x00000038) >> 3)
+#define PHY_BB_ANALOG_SWAP_ANALOG_TX_SWAP_CNTL_SET(x)                          (((x) << 3) & 0x00000038)
+#define PHY_BB_ANALOG_SWAP_SWAP_ALT_CHN_MSB                                                            6
+#define PHY_BB_ANALOG_SWAP_SWAP_ALT_CHN_LSB                                                            6
+#define PHY_BB_ANALOG_SWAP_SWAP_ALT_CHN_MASK                                                  0x00000040
+#define PHY_BB_ANALOG_SWAP_SWAP_ALT_CHN_GET(x)                                 (((x) & 0x00000040) >> 6)
+#define PHY_BB_ANALOG_SWAP_SWAP_ALT_CHN_SET(x)                                 (((x) << 6) & 0x00000040)
+#define PHY_BB_ANALOG_SWAP_ANALOG_DC_DAC_POLARITY_MSB                                                  7
+#define PHY_BB_ANALOG_SWAP_ANALOG_DC_DAC_POLARITY_LSB                                                  7
+#define PHY_BB_ANALOG_SWAP_ANALOG_DC_DAC_POLARITY_MASK                                        0x00000080
+#define PHY_BB_ANALOG_SWAP_ANALOG_DC_DAC_POLARITY_GET(x)                       (((x) & 0x00000080) >> 7)
+#define PHY_BB_ANALOG_SWAP_ANALOG_DC_DAC_POLARITY_SET(x)                       (((x) << 7) & 0x00000080)
+#define PHY_BB_ANALOG_SWAP_ANALOG_PKDET_DAC_POLARITY_MSB                                               8
+#define PHY_BB_ANALOG_SWAP_ANALOG_PKDET_DAC_POLARITY_LSB                                               8
+#define PHY_BB_ANALOG_SWAP_ANALOG_PKDET_DAC_POLARITY_MASK                                     0x00000100
+#define PHY_BB_ANALOG_SWAP_ANALOG_PKDET_DAC_POLARITY_GET(x)                    (((x) & 0x00000100) >> 8)
+#define PHY_BB_ANALOG_SWAP_ANALOG_PKDET_DAC_POLARITY_SET(x)                    (((x) << 8) & 0x00000100)
+
+/* macros for BB_tpc_5_b0 */
+#define PHY_BB_TPC_5_B0_ADDRESS                                                               0x0000a26c
+#define PHY_BB_TPC_5_B0_OFFSET                                                                0x0000a26c
+#define PHY_BB_TPC_5_B0_PD_GAIN_OVERLAP_MSB                                                            3
+#define PHY_BB_TPC_5_B0_PD_GAIN_OVERLAP_LSB                                                            0
+#define PHY_BB_TPC_5_B0_PD_GAIN_OVERLAP_MASK                                                  0x0000000f
+#define PHY_BB_TPC_5_B0_PD_GAIN_OVERLAP_GET(x)                                 (((x) & 0x0000000f) >> 0)
+#define PHY_BB_TPC_5_B0_PD_GAIN_OVERLAP_SET(x)                                 (((x) << 0) & 0x0000000f)
+#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_1_0_MSB                                                       9
+#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_1_0_LSB                                                       4
+#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_1_0_MASK                                             0x000003f0
+#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_1_0_GET(x)                            (((x) & 0x000003f0) >> 4)
+#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_1_0_SET(x)                            (((x) << 4) & 0x000003f0)
+#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_2_0_MSB                                                      15
+#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_2_0_LSB                                                      10
+#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_2_0_MASK                                             0x0000fc00
+#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_2_0_GET(x)                           (((x) & 0x0000fc00) >> 10)
+#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_2_0_SET(x)                           (((x) << 10) & 0x0000fc00)
+#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_3_0_MSB                                                      21
+#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_3_0_LSB                                                      16
+#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_3_0_MASK                                             0x003f0000
+#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_3_0_GET(x)                           (((x) & 0x003f0000) >> 16)
+#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_3_0_SET(x)                           (((x) << 16) & 0x003f0000)
+#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_4_0_MSB                                                      27
+#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_4_0_LSB                                                      22
+#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_4_0_MASK                                             0x0fc00000
+#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_4_0_GET(x)                           (((x) & 0x0fc00000) >> 22)
+#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_4_0_SET(x)                           (((x) << 22) & 0x0fc00000)
+
+/* macros for BB_tpc_6_b0 */
+#define PHY_BB_TPC_6_B0_ADDRESS                                                               0x0000a270
+#define PHY_BB_TPC_6_B0_OFFSET                                                                0x0000a270
+#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_1_0_MSB                                                         5
+#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_1_0_LSB                                                         0
+#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_1_0_MASK                                               0x0000003f
+#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_1_0_GET(x)                              (((x) & 0x0000003f) >> 0)
+#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_1_0_SET(x)                              (((x) << 0) & 0x0000003f)
+#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_2_0_MSB                                                        11
+#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_2_0_LSB                                                         6
+#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_2_0_MASK                                               0x00000fc0
+#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_2_0_GET(x)                              (((x) & 0x00000fc0) >> 6)
+#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_2_0_SET(x)                              (((x) << 6) & 0x00000fc0)
+#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_3_0_MSB                                                        17
+#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_3_0_LSB                                                        12
+#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_3_0_MASK                                               0x0003f000
+#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_3_0_GET(x)                             (((x) & 0x0003f000) >> 12)
+#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_3_0_SET(x)                             (((x) << 12) & 0x0003f000)
+#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_4_0_MSB                                                        23
+#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_4_0_LSB                                                        18
+#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_4_0_MASK                                               0x00fc0000
+#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_4_0_GET(x)                             (((x) & 0x00fc0000) >> 18)
+#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_4_0_SET(x)                             (((x) << 18) & 0x00fc0000)
+#define PHY_BB_TPC_6_B0_ERROR_EST_MODE_MSB                                                            25
+#define PHY_BB_TPC_6_B0_ERROR_EST_MODE_LSB                                                            24
+#define PHY_BB_TPC_6_B0_ERROR_EST_MODE_MASK                                                   0x03000000
+#define PHY_BB_TPC_6_B0_ERROR_EST_MODE_GET(x)                                 (((x) & 0x03000000) >> 24)
+#define PHY_BB_TPC_6_B0_ERROR_EST_MODE_SET(x)                                 (((x) << 24) & 0x03000000)
+#define PHY_BB_TPC_6_B0_ERROR_EST_FILTER_COEFF_MSB                                                    28
+#define PHY_BB_TPC_6_B0_ERROR_EST_FILTER_COEFF_LSB                                                    26
+#define PHY_BB_TPC_6_B0_ERROR_EST_FILTER_COEFF_MASK                                           0x1c000000
+#define PHY_BB_TPC_6_B0_ERROR_EST_FILTER_COEFF_GET(x)                         (((x) & 0x1c000000) >> 26)
+#define PHY_BB_TPC_6_B0_ERROR_EST_FILTER_COEFF_SET(x)                         (((x) << 26) & 0x1c000000)
+
+/* macros for BB_tpc_7 */
+#define PHY_BB_TPC_7_ADDRESS                                                                  0x0000a274
+#define PHY_BB_TPC_7_OFFSET                                                                   0x0000a274
+#define PHY_BB_TPC_7_TX_GAIN_TABLE_MAX_MSB                                                             5
+#define PHY_BB_TPC_7_TX_GAIN_TABLE_MAX_LSB                                                             0
+#define PHY_BB_TPC_7_TX_GAIN_TABLE_MAX_MASK                                                   0x0000003f
+#define PHY_BB_TPC_7_TX_GAIN_TABLE_MAX_GET(x)                                  (((x) & 0x0000003f) >> 0)
+#define PHY_BB_TPC_7_TX_GAIN_TABLE_MAX_SET(x)                                  (((x) << 0) & 0x0000003f)
+#define PHY_BB_TPC_7_INIT_TX_GAIN_SETTING_MSB                                                         11
+#define PHY_BB_TPC_7_INIT_TX_GAIN_SETTING_LSB                                                          6
+#define PHY_BB_TPC_7_INIT_TX_GAIN_SETTING_MASK                                                0x00000fc0
+#define PHY_BB_TPC_7_INIT_TX_GAIN_SETTING_GET(x)                               (((x) & 0x00000fc0) >> 6)
+#define PHY_BB_TPC_7_INIT_TX_GAIN_SETTING_SET(x)                               (((x) << 6) & 0x00000fc0)
+#define PHY_BB_TPC_7_EN_CL_GAIN_MOD_MSB                                                               12
+#define PHY_BB_TPC_7_EN_CL_GAIN_MOD_LSB                                                               12
+#define PHY_BB_TPC_7_EN_CL_GAIN_MOD_MASK                                                      0x00001000
+#define PHY_BB_TPC_7_EN_CL_GAIN_MOD_GET(x)                                    (((x) & 0x00001000) >> 12)
+#define PHY_BB_TPC_7_EN_CL_GAIN_MOD_SET(x)                                    (((x) << 12) & 0x00001000)
+#define PHY_BB_TPC_7_USE_TX_PD_IN_XPA_MSB                                                             13
+#define PHY_BB_TPC_7_USE_TX_PD_IN_XPA_LSB                                                             13
+#define PHY_BB_TPC_7_USE_TX_PD_IN_XPA_MASK                                                    0x00002000
+#define PHY_BB_TPC_7_USE_TX_PD_IN_XPA_GET(x)                                  (((x) & 0x00002000) >> 13)
+#define PHY_BB_TPC_7_USE_TX_PD_IN_XPA_SET(x)                                  (((x) << 13) & 0x00002000)
+#define PHY_BB_TPC_7_EXTEND_TX_FRAME_FOR_TPC_MSB                                                      14
+#define PHY_BB_TPC_7_EXTEND_TX_FRAME_FOR_TPC_LSB                                                      14
+#define PHY_BB_TPC_7_EXTEND_TX_FRAME_FOR_TPC_MASK                                             0x00004000
+#define PHY_BB_TPC_7_EXTEND_TX_FRAME_FOR_TPC_GET(x)                           (((x) & 0x00004000) >> 14)
+#define PHY_BB_TPC_7_EXTEND_TX_FRAME_FOR_TPC_SET(x)                           (((x) << 14) & 0x00004000)
+#define PHY_BB_TPC_7_USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET_MSB                                    15
+#define PHY_BB_TPC_7_USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET_LSB                                    15
+#define PHY_BB_TPC_7_USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET_MASK                           0x00008000
+#define PHY_BB_TPC_7_USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET_GET(x)         (((x) & 0x00008000) >> 15)
+#define PHY_BB_TPC_7_USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET_SET(x)         (((x) << 15) & 0x00008000)
+
+/* macros for BB_tpc_8 */
+#define PHY_BB_TPC_8_ADDRESS                                                                  0x0000a278
+#define PHY_BB_TPC_8_OFFSET                                                                   0x0000a278
+#define PHY_BB_TPC_8_DESIRED_SCALE_0_MSB                                                               4
+#define PHY_BB_TPC_8_DESIRED_SCALE_0_LSB                                                               0
+#define PHY_BB_TPC_8_DESIRED_SCALE_0_MASK                                                     0x0000001f
+#define PHY_BB_TPC_8_DESIRED_SCALE_0_GET(x)                                    (((x) & 0x0000001f) >> 0)
+#define PHY_BB_TPC_8_DESIRED_SCALE_0_SET(x)                                    (((x) << 0) & 0x0000001f)
+#define PHY_BB_TPC_8_DESIRED_SCALE_1_MSB                                                               9
+#define PHY_BB_TPC_8_DESIRED_SCALE_1_LSB                                                               5
+#define PHY_BB_TPC_8_DESIRED_SCALE_1_MASK                                                     0x000003e0
+#define PHY_BB_TPC_8_DESIRED_SCALE_1_GET(x)                                    (((x) & 0x000003e0) >> 5)
+#define PHY_BB_TPC_8_DESIRED_SCALE_1_SET(x)                                    (((x) << 5) & 0x000003e0)
+#define PHY_BB_TPC_8_DESIRED_SCALE_2_MSB                                                              14
+#define PHY_BB_TPC_8_DESIRED_SCALE_2_LSB                                                              10
+#define PHY_BB_TPC_8_DESIRED_SCALE_2_MASK                                                     0x00007c00
+#define PHY_BB_TPC_8_DESIRED_SCALE_2_GET(x)                                   (((x) & 0x00007c00) >> 10)
+#define PHY_BB_TPC_8_DESIRED_SCALE_2_SET(x)                                   (((x) << 10) & 0x00007c00)
+#define PHY_BB_TPC_8_DESIRED_SCALE_3_MSB                                                              19
+#define PHY_BB_TPC_8_DESIRED_SCALE_3_LSB                                                              15
+#define PHY_BB_TPC_8_DESIRED_SCALE_3_MASK                                                     0x000f8000
+#define PHY_BB_TPC_8_DESIRED_SCALE_3_GET(x)                                   (((x) & 0x000f8000) >> 15)
+#define PHY_BB_TPC_8_DESIRED_SCALE_3_SET(x)                                   (((x) << 15) & 0x000f8000)
+#define PHY_BB_TPC_8_DESIRED_SCALE_4_MSB                                                              24
+#define PHY_BB_TPC_8_DESIRED_SCALE_4_LSB                                                              20
+#define PHY_BB_TPC_8_DESIRED_SCALE_4_MASK                                                     0x01f00000
+#define PHY_BB_TPC_8_DESIRED_SCALE_4_GET(x)                                   (((x) & 0x01f00000) >> 20)
+#define PHY_BB_TPC_8_DESIRED_SCALE_4_SET(x)                                   (((x) << 20) & 0x01f00000)
+#define PHY_BB_TPC_8_DESIRED_SCALE_5_MSB                                                              29
+#define PHY_BB_TPC_8_DESIRED_SCALE_5_LSB                                                              25
+#define PHY_BB_TPC_8_DESIRED_SCALE_5_MASK                                                     0x3e000000
+#define PHY_BB_TPC_8_DESIRED_SCALE_5_GET(x)                                   (((x) & 0x3e000000) >> 25)
+#define PHY_BB_TPC_8_DESIRED_SCALE_5_SET(x)                                   (((x) << 25) & 0x3e000000)
+
+/* macros for BB_tpc_9 */
+#define PHY_BB_TPC_9_ADDRESS                                                                  0x0000a27c
+#define PHY_BB_TPC_9_OFFSET                                                                   0x0000a27c
+#define PHY_BB_TPC_9_DESIRED_SCALE_6_MSB                                                               4
+#define PHY_BB_TPC_9_DESIRED_SCALE_6_LSB                                                               0
+#define PHY_BB_TPC_9_DESIRED_SCALE_6_MASK                                                     0x0000001f
+#define PHY_BB_TPC_9_DESIRED_SCALE_6_GET(x)                                    (((x) & 0x0000001f) >> 0)
+#define PHY_BB_TPC_9_DESIRED_SCALE_6_SET(x)                                    (((x) << 0) & 0x0000001f)
+#define PHY_BB_TPC_9_DESIRED_SCALE_7_MSB                                                               9
+#define PHY_BB_TPC_9_DESIRED_SCALE_7_LSB                                                               5
+#define PHY_BB_TPC_9_DESIRED_SCALE_7_MASK                                                     0x000003e0
+#define PHY_BB_TPC_9_DESIRED_SCALE_7_GET(x)                                    (((x) & 0x000003e0) >> 5)
+#define PHY_BB_TPC_9_DESIRED_SCALE_7_SET(x)                                    (((x) << 5) & 0x000003e0)
+#define PHY_BB_TPC_9_DESIRED_SCALE_CCK_MSB                                                            14
+#define PHY_BB_TPC_9_DESIRED_SCALE_CCK_LSB                                                            10
+#define PHY_BB_TPC_9_DESIRED_SCALE_CCK_MASK                                                   0x00007c00
+#define PHY_BB_TPC_9_DESIRED_SCALE_CCK_GET(x)                                 (((x) & 0x00007c00) >> 10)
+#define PHY_BB_TPC_9_DESIRED_SCALE_CCK_SET(x)                                 (((x) << 10) & 0x00007c00)
+#define PHY_BB_TPC_9_EN_PD_DC_OFFSET_THR_MSB                                                          20
+#define PHY_BB_TPC_9_EN_PD_DC_OFFSET_THR_LSB                                                          20
+#define PHY_BB_TPC_9_EN_PD_DC_OFFSET_THR_MASK                                                 0x00100000
+#define PHY_BB_TPC_9_EN_PD_DC_OFFSET_THR_GET(x)                               (((x) & 0x00100000) >> 20)
+#define PHY_BB_TPC_9_EN_PD_DC_OFFSET_THR_SET(x)                               (((x) << 20) & 0x00100000)
+#define PHY_BB_TPC_9_PD_DC_OFFSET_THR_MSB                                                             26
+#define PHY_BB_TPC_9_PD_DC_OFFSET_THR_LSB                                                             21
+#define PHY_BB_TPC_9_PD_DC_OFFSET_THR_MASK                                                    0x07e00000
+#define PHY_BB_TPC_9_PD_DC_OFFSET_THR_GET(x)                                  (((x) & 0x07e00000) >> 21)
+#define PHY_BB_TPC_9_PD_DC_OFFSET_THR_SET(x)                                  (((x) << 21) & 0x07e00000)
+#define PHY_BB_TPC_9_WAIT_CALTX_SETTLE_MSB                                                            30
+#define PHY_BB_TPC_9_WAIT_CALTX_SETTLE_LSB                                                            27
+#define PHY_BB_TPC_9_WAIT_CALTX_SETTLE_MASK                                                   0x78000000
+#define PHY_BB_TPC_9_WAIT_CALTX_SETTLE_GET(x)                                 (((x) & 0x78000000) >> 27)
+#define PHY_BB_TPC_9_WAIT_CALTX_SETTLE_SET(x)                                 (((x) << 27) & 0x78000000)
+#define PHY_BB_TPC_9_DISABLE_PDADC_RESIDUAL_DC_REMOVAL_MSB                                            31
+#define PHY_BB_TPC_9_DISABLE_PDADC_RESIDUAL_DC_REMOVAL_LSB                                            31
+#define PHY_BB_TPC_9_DISABLE_PDADC_RESIDUAL_DC_REMOVAL_MASK                                   0x80000000
+#define PHY_BB_TPC_9_DISABLE_PDADC_RESIDUAL_DC_REMOVAL_GET(x)                 (((x) & 0x80000000) >> 31)
+#define PHY_BB_TPC_9_DISABLE_PDADC_RESIDUAL_DC_REMOVAL_SET(x)                 (((x) << 31) & 0x80000000)
+
+/* macros for BB_pdadc_tab_b0 */
+#define PHY_BB_PDADC_TAB_B0_ADDRESS                                                           0x0000a280
+#define PHY_BB_PDADC_TAB_B0_OFFSET                                                            0x0000a280
+#define PHY_BB_PDADC_TAB_B0_TAB_ENTRY_MSB                                                             31
+#define PHY_BB_PDADC_TAB_B0_TAB_ENTRY_LSB                                                              0
+#define PHY_BB_PDADC_TAB_B0_TAB_ENTRY_MASK                                                    0xffffffff
+#define PHY_BB_PDADC_TAB_B0_TAB_ENTRY_SET(x)                                   (((x) << 0) & 0xffffffff)
+
+/* macros for BB_cl_tab_b0 */
+#define PHY_BB_CL_TAB_B0_ADDRESS                                                              0x0000a300
+#define PHY_BB_CL_TAB_B0_OFFSET                                                               0x0000a300
+#define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_MSB                                                               4
+#define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_LSB                                                               0
+#define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_MASK                                                     0x0000001f
+#define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_GET(x)                                    (((x) & 0x0000001f) >> 0)
+#define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_SET(x)                                    (((x) << 0) & 0x0000001f)
+#define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_MSB                                                         15
+#define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_LSB                                                          5
+#define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_MASK                                                0x0000ffe0
+#define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_GET(x)                               (((x) & 0x0000ffe0) >> 5)
+#define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_SET(x)                               (((x) << 5) & 0x0000ffe0)
+#define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_MSB                                                         26
+#define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_LSB                                                         16
+#define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_MASK                                                0x07ff0000
+#define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_GET(x)                              (((x) & 0x07ff0000) >> 16)
+#define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_SET(x)                              (((x) << 16) & 0x07ff0000)
+#define PHY_BB_CL_TAB_B0_BB_GAIN_MSB                                                                  30
+#define PHY_BB_CL_TAB_B0_BB_GAIN_LSB                                                                  27
+#define PHY_BB_CL_TAB_B0_BB_GAIN_MASK                                                         0x78000000
+#define PHY_BB_CL_TAB_B0_BB_GAIN_GET(x)                                       (((x) & 0x78000000) >> 27)
+#define PHY_BB_CL_TAB_B0_BB_GAIN_SET(x)                                       (((x) << 27) & 0x78000000)
+
+/* macros for BB_cl_map_0_b0 */
+#define PHY_BB_CL_MAP_0_B0_ADDRESS                                                            0x0000a340
+#define PHY_BB_CL_MAP_0_B0_OFFSET                                                             0x0000a340
+#define PHY_BB_CL_MAP_0_B0_CL_MAP_0_MSB                                                               31
+#define PHY_BB_CL_MAP_0_B0_CL_MAP_0_LSB                                                                0
+#define PHY_BB_CL_MAP_0_B0_CL_MAP_0_MASK                                                      0xffffffff
+#define PHY_BB_CL_MAP_0_B0_CL_MAP_0_GET(x)                                     (((x) & 0xffffffff) >> 0)
+#define PHY_BB_CL_MAP_0_B0_CL_MAP_0_SET(x)                                     (((x) << 0) & 0xffffffff)
+
+/* macros for BB_cl_map_1_b0 */
+#define PHY_BB_CL_MAP_1_B0_ADDRESS                                                            0x0000a344
+#define PHY_BB_CL_MAP_1_B0_OFFSET                                                             0x0000a344
+#define PHY_BB_CL_MAP_1_B0_CL_MAP_1_MSB                                                               31
+#define PHY_BB_CL_MAP_1_B0_CL_MAP_1_LSB                                                                0
+#define PHY_BB_CL_MAP_1_B0_CL_MAP_1_MASK                                                      0xffffffff
+#define PHY_BB_CL_MAP_1_B0_CL_MAP_1_GET(x)                                     (((x) & 0xffffffff) >> 0)
+#define PHY_BB_CL_MAP_1_B0_CL_MAP_1_SET(x)                                     (((x) << 0) & 0xffffffff)
+
+/* macros for BB_cl_map_2_b0 */
+#define PHY_BB_CL_MAP_2_B0_ADDRESS                                                            0x0000a348
+#define PHY_BB_CL_MAP_2_B0_OFFSET                                                             0x0000a348
+#define PHY_BB_CL_MAP_2_B0_CL_MAP_2_MSB                                                               31
+#define PHY_BB_CL_MAP_2_B0_CL_MAP_2_LSB                                                                0
+#define PHY_BB_CL_MAP_2_B0_CL_MAP_2_MASK                                                      0xffffffff
+#define PHY_BB_CL_MAP_2_B0_CL_MAP_2_GET(x)                                     (((x) & 0xffffffff) >> 0)
+#define PHY_BB_CL_MAP_2_B0_CL_MAP_2_SET(x)                                     (((x) << 0) & 0xffffffff)
+
+/* macros for BB_cl_map_3_b0 */
+#define PHY_BB_CL_MAP_3_B0_ADDRESS                                                            0x0000a34c
+#define PHY_BB_CL_MAP_3_B0_OFFSET                                                             0x0000a34c
+#define PHY_BB_CL_MAP_3_B0_CL_MAP_3_MSB                                                               31
+#define PHY_BB_CL_MAP_3_B0_CL_MAP_3_LSB                                                                0
+#define PHY_BB_CL_MAP_3_B0_CL_MAP_3_MASK                                                      0xffffffff
+#define PHY_BB_CL_MAP_3_B0_CL_MAP_3_GET(x)                                     (((x) & 0xffffffff) >> 0)
+#define PHY_BB_CL_MAP_3_B0_CL_MAP_3_SET(x)                                     (((x) << 0) & 0xffffffff)
+
+/* macros for BB_cl_cal_ctrl */
+#define PHY_BB_CL_CAL_CTRL_ADDRESS                                                            0x0000a358
+#define PHY_BB_CL_CAL_CTRL_OFFSET                                                             0x0000a358
+#define PHY_BB_CL_CAL_CTRL_ENABLE_PARALLEL_CAL_MSB                                                     0
+#define PHY_BB_CL_CAL_CTRL_ENABLE_PARALLEL_CAL_LSB                                                     0
+#define PHY_BB_CL_CAL_CTRL_ENABLE_PARALLEL_CAL_MASK                                           0x00000001
+#define PHY_BB_CL_CAL_CTRL_ENABLE_PARALLEL_CAL_GET(x)                          (((x) & 0x00000001) >> 0)
+#define PHY_BB_CL_CAL_CTRL_ENABLE_PARALLEL_CAL_SET(x)                          (((x) << 0) & 0x00000001)
+#define PHY_BB_CL_CAL_CTRL_ENABLE_CL_CALIBRATE_MSB                                                     1
+#define PHY_BB_CL_CAL_CTRL_ENABLE_CL_CALIBRATE_LSB                                                     1
+#define PHY_BB_CL_CAL_CTRL_ENABLE_CL_CALIBRATE_MASK                                           0x00000002
+#define PHY_BB_CL_CAL_CTRL_ENABLE_CL_CALIBRATE_GET(x)                          (((x) & 0x00000002) >> 1)
+#define PHY_BB_CL_CAL_CTRL_ENABLE_CL_CALIBRATE_SET(x)                          (((x) << 1) & 0x00000002)
+#define PHY_BB_CL_CAL_CTRL_CF_CLC_TEST_POINT_MSB                                                       3
+#define PHY_BB_CL_CAL_CTRL_CF_CLC_TEST_POINT_LSB                                                       2
+#define PHY_BB_CL_CAL_CTRL_CF_CLC_TEST_POINT_MASK                                             0x0000000c
+#define PHY_BB_CL_CAL_CTRL_CF_CLC_TEST_POINT_GET(x)                            (((x) & 0x0000000c) >> 2)
+#define PHY_BB_CL_CAL_CTRL_CF_CLC_TEST_POINT_SET(x)                            (((x) << 2) & 0x0000000c)
+#define PHY_BB_CL_CAL_CTRL_CF_CLC_FORCED_PAGAIN_MSB                                                    7
+#define PHY_BB_CL_CAL_CTRL_CF_CLC_FORCED_PAGAIN_LSB                                                    4
+#define PHY_BB_CL_CAL_CTRL_CF_CLC_FORCED_PAGAIN_MASK                                          0x000000f0
+#define PHY_BB_CL_CAL_CTRL_CF_CLC_FORCED_PAGAIN_GET(x)                         (((x) & 0x000000f0) >> 4)
+#define PHY_BB_CL_CAL_CTRL_CF_CLC_FORCED_PAGAIN_SET(x)                         (((x) << 4) & 0x000000f0)
+#define PHY_BB_CL_CAL_CTRL_CARR_LEAK_MAX_OFFSET_MSB                                                   15
+#define PHY_BB_CL_CAL_CTRL_CARR_LEAK_MAX_OFFSET_LSB                                                    8
+#define PHY_BB_CL_CAL_CTRL_CARR_LEAK_MAX_OFFSET_MASK                                          0x0000ff00
+#define PHY_BB_CL_CAL_CTRL_CARR_LEAK_MAX_OFFSET_GET(x)                         (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_CL_CAL_CTRL_CARR_LEAK_MAX_OFFSET_SET(x)                         (((x) << 8) & 0x0000ff00)
+#define PHY_BB_CL_CAL_CTRL_CF_CLC_INIT_BBGAIN_MSB                                                     21
+#define PHY_BB_CL_CAL_CTRL_CF_CLC_INIT_BBGAIN_LSB                                                     16
+#define PHY_BB_CL_CAL_CTRL_CF_CLC_INIT_BBGAIN_MASK                                            0x003f0000
+#define PHY_BB_CL_CAL_CTRL_CF_CLC_INIT_BBGAIN_GET(x)                          (((x) & 0x003f0000) >> 16)
+#define PHY_BB_CL_CAL_CTRL_CF_CLC_INIT_BBGAIN_SET(x)                          (((x) << 16) & 0x003f0000)
+#define PHY_BB_CL_CAL_CTRL_CF_ADC_BOUND_MSB                                                           29
+#define PHY_BB_CL_CAL_CTRL_CF_ADC_BOUND_LSB                                                           22
+#define PHY_BB_CL_CAL_CTRL_CF_ADC_BOUND_MASK                                                  0x3fc00000
+#define PHY_BB_CL_CAL_CTRL_CF_ADC_BOUND_GET(x)                                (((x) & 0x3fc00000) >> 22)
+#define PHY_BB_CL_CAL_CTRL_CF_ADC_BOUND_SET(x)                                (((x) << 22) & 0x3fc00000)
+#define PHY_BB_CL_CAL_CTRL_USE_DAC_CL_CORRECTION_MSB                                                  30
+#define PHY_BB_CL_CAL_CTRL_USE_DAC_CL_CORRECTION_LSB                                                  30
+#define PHY_BB_CL_CAL_CTRL_USE_DAC_CL_CORRECTION_MASK                                         0x40000000
+#define PHY_BB_CL_CAL_CTRL_USE_DAC_CL_CORRECTION_GET(x)                       (((x) & 0x40000000) >> 30)
+#define PHY_BB_CL_CAL_CTRL_USE_DAC_CL_CORRECTION_SET(x)                       (((x) << 30) & 0x40000000)
+#define PHY_BB_CL_CAL_CTRL_CL_MAP_HW_GEN_MSB                                                          31
+#define PHY_BB_CL_CAL_CTRL_CL_MAP_HW_GEN_LSB                                                          31
+#define PHY_BB_CL_CAL_CTRL_CL_MAP_HW_GEN_MASK                                                 0x80000000
+#define PHY_BB_CL_CAL_CTRL_CL_MAP_HW_GEN_GET(x)                               (((x) & 0x80000000) >> 31)
+#define PHY_BB_CL_CAL_CTRL_CL_MAP_HW_GEN_SET(x)                               (((x) << 31) & 0x80000000)
+
+/* macros for BB_cl_map_pal_0_b0 */
+#define PHY_BB_CL_MAP_PAL_0_B0_ADDRESS                                                        0x0000a35c
+#define PHY_BB_CL_MAP_PAL_0_B0_OFFSET                                                         0x0000a35c
+#define PHY_BB_CL_MAP_PAL_0_B0_CL_MAP_0_MSB                                                           31
+#define PHY_BB_CL_MAP_PAL_0_B0_CL_MAP_0_LSB                                                            0
+#define PHY_BB_CL_MAP_PAL_0_B0_CL_MAP_0_MASK                                                  0xffffffff
+#define PHY_BB_CL_MAP_PAL_0_B0_CL_MAP_0_GET(x)                                 (((x) & 0xffffffff) >> 0)
+#define PHY_BB_CL_MAP_PAL_0_B0_CL_MAP_0_SET(x)                                 (((x) << 0) & 0xffffffff)
+
+/* macros for BB_cl_map_pal_1_b0 */
+#define PHY_BB_CL_MAP_PAL_1_B0_ADDRESS                                                        0x0000a360
+#define PHY_BB_CL_MAP_PAL_1_B0_OFFSET                                                         0x0000a360
+#define PHY_BB_CL_MAP_PAL_1_B0_CL_MAP_1_MSB                                                           31
+#define PHY_BB_CL_MAP_PAL_1_B0_CL_MAP_1_LSB                                                            0
+#define PHY_BB_CL_MAP_PAL_1_B0_CL_MAP_1_MASK                                                  0xffffffff
+#define PHY_BB_CL_MAP_PAL_1_B0_CL_MAP_1_GET(x)                                 (((x) & 0xffffffff) >> 0)
+#define PHY_BB_CL_MAP_PAL_1_B0_CL_MAP_1_SET(x)                                 (((x) << 0) & 0xffffffff)
+
+/* macros for BB_cl_map_pal_2_b0 */
+#define PHY_BB_CL_MAP_PAL_2_B0_ADDRESS                                                        0x0000a364
+#define PHY_BB_CL_MAP_PAL_2_B0_OFFSET                                                         0x0000a364
+#define PHY_BB_CL_MAP_PAL_2_B0_CL_MAP_2_MSB                                                           31
+#define PHY_BB_CL_MAP_PAL_2_B0_CL_MAP_2_LSB                                                            0
+#define PHY_BB_CL_MAP_PAL_2_B0_CL_MAP_2_MASK                                                  0xffffffff
+#define PHY_BB_CL_MAP_PAL_2_B0_CL_MAP_2_GET(x)                                 (((x) & 0xffffffff) >> 0)
+#define PHY_BB_CL_MAP_PAL_2_B0_CL_MAP_2_SET(x)                                 (((x) << 0) & 0xffffffff)
+
+/* macros for BB_cl_map_pal_3_b0 */
+#define PHY_BB_CL_MAP_PAL_3_B0_ADDRESS                                                        0x0000a368
+#define PHY_BB_CL_MAP_PAL_3_B0_OFFSET                                                         0x0000a368
+#define PHY_BB_CL_MAP_PAL_3_B0_CL_MAP_3_MSB                                                           31
+#define PHY_BB_CL_MAP_PAL_3_B0_CL_MAP_3_LSB                                                            0
+#define PHY_BB_CL_MAP_PAL_3_B0_CL_MAP_3_MASK                                                  0xffffffff
+#define PHY_BB_CL_MAP_PAL_3_B0_CL_MAP_3_GET(x)                                 (((x) & 0xffffffff) >> 0)
+#define PHY_BB_CL_MAP_PAL_3_B0_CL_MAP_3_SET(x)                                 (((x) << 0) & 0xffffffff)
+
+/* macros for BB_rifs */
+#define PHY_BB_RIFS_ADDRESS                                                                   0x0000a388
+#define PHY_BB_RIFS_OFFSET                                                                    0x0000a388
+#define PHY_BB_RIFS_DISABLE_FCC_FIX_MSB                                                               25
+#define PHY_BB_RIFS_DISABLE_FCC_FIX_LSB                                                               25
+#define PHY_BB_RIFS_DISABLE_FCC_FIX_MASK                                                      0x02000000
+#define PHY_BB_RIFS_DISABLE_FCC_FIX_GET(x)                                    (((x) & 0x02000000) >> 25)
+#define PHY_BB_RIFS_DISABLE_FCC_FIX_SET(x)                                    (((x) << 25) & 0x02000000)
+#define PHY_BB_RIFS_ENABLE_RESET_TDOMAIN_MSB                                                          26
+#define PHY_BB_RIFS_ENABLE_RESET_TDOMAIN_LSB                                                          26
+#define PHY_BB_RIFS_ENABLE_RESET_TDOMAIN_MASK                                                 0x04000000
+#define PHY_BB_RIFS_ENABLE_RESET_TDOMAIN_GET(x)                               (((x) & 0x04000000) >> 26)
+#define PHY_BB_RIFS_ENABLE_RESET_TDOMAIN_SET(x)                               (((x) << 26) & 0x04000000)
+#define PHY_BB_RIFS_DISABLE_FCC_FIX2_MSB                                                              27
+#define PHY_BB_RIFS_DISABLE_FCC_FIX2_LSB                                                              27
+#define PHY_BB_RIFS_DISABLE_FCC_FIX2_MASK                                                     0x08000000
+#define PHY_BB_RIFS_DISABLE_FCC_FIX2_GET(x)                                   (((x) & 0x08000000) >> 27)
+#define PHY_BB_RIFS_DISABLE_FCC_FIX2_SET(x)                                   (((x) << 27) & 0x08000000)
+#define PHY_BB_RIFS_DISABLE_RIFS_CCK_FIX_MSB                                                          28
+#define PHY_BB_RIFS_DISABLE_RIFS_CCK_FIX_LSB                                                          28
+#define PHY_BB_RIFS_DISABLE_RIFS_CCK_FIX_MASK                                                 0x10000000
+#define PHY_BB_RIFS_DISABLE_RIFS_CCK_FIX_GET(x)                               (((x) & 0x10000000) >> 28)
+#define PHY_BB_RIFS_DISABLE_RIFS_CCK_FIX_SET(x)                               (((x) << 28) & 0x10000000)
+#define PHY_BB_RIFS_DISABLE_ERROR_RESET_FIX_MSB                                                       29
+#define PHY_BB_RIFS_DISABLE_ERROR_RESET_FIX_LSB                                                       29
+#define PHY_BB_RIFS_DISABLE_ERROR_RESET_FIX_MASK                                              0x20000000
+#define PHY_BB_RIFS_DISABLE_ERROR_RESET_FIX_GET(x)                            (((x) & 0x20000000) >> 29)
+#define PHY_BB_RIFS_DISABLE_ERROR_RESET_FIX_SET(x)                            (((x) << 29) & 0x20000000)
+#define PHY_BB_RIFS_RADAR_USE_FDOMAIN_RESET_MSB                                                       30
+#define PHY_BB_RIFS_RADAR_USE_FDOMAIN_RESET_LSB                                                       30
+#define PHY_BB_RIFS_RADAR_USE_FDOMAIN_RESET_MASK                                              0x40000000
+#define PHY_BB_RIFS_RADAR_USE_FDOMAIN_RESET_GET(x)                            (((x) & 0x40000000) >> 30)
+#define PHY_BB_RIFS_RADAR_USE_FDOMAIN_RESET_SET(x)                            (((x) << 30) & 0x40000000)
+
+/* macros for BB_powertx_rate5 */
+#define PHY_BB_POWERTX_RATE5_ADDRESS                                                          0x0000a38c
+#define PHY_BB_POWERTX_RATE5_OFFSET                                                           0x0000a38c
+#define PHY_BB_POWERTX_RATE5_POWERTXHT20_0_MSB                                                         5
+#define PHY_BB_POWERTX_RATE5_POWERTXHT20_0_LSB                                                         0
+#define PHY_BB_POWERTX_RATE5_POWERTXHT20_0_MASK                                               0x0000003f
+#define PHY_BB_POWERTX_RATE5_POWERTXHT20_0_GET(x)                              (((x) & 0x0000003f) >> 0)
+#define PHY_BB_POWERTX_RATE5_POWERTXHT20_0_SET(x)                              (((x) << 0) & 0x0000003f)
+#define PHY_BB_POWERTX_RATE5_POWERTXHT20_1_MSB                                                        13
+#define PHY_BB_POWERTX_RATE5_POWERTXHT20_1_LSB                                                         8
+#define PHY_BB_POWERTX_RATE5_POWERTXHT20_1_MASK                                               0x00003f00
+#define PHY_BB_POWERTX_RATE5_POWERTXHT20_1_GET(x)                              (((x) & 0x00003f00) >> 8)
+#define PHY_BB_POWERTX_RATE5_POWERTXHT20_1_SET(x)                              (((x) << 8) & 0x00003f00)
+#define PHY_BB_POWERTX_RATE5_POWERTXHT20_2_MSB                                                        21
+#define PHY_BB_POWERTX_RATE5_POWERTXHT20_2_LSB                                                        16
+#define PHY_BB_POWERTX_RATE5_POWERTXHT20_2_MASK                                               0x003f0000
+#define PHY_BB_POWERTX_RATE5_POWERTXHT20_2_GET(x)                             (((x) & 0x003f0000) >> 16)
+#define PHY_BB_POWERTX_RATE5_POWERTXHT20_2_SET(x)                             (((x) << 16) & 0x003f0000)
+#define PHY_BB_POWERTX_RATE5_POWERTXHT20_3_MSB                                                        29
+#define PHY_BB_POWERTX_RATE5_POWERTXHT20_3_LSB                                                        24
+#define PHY_BB_POWERTX_RATE5_POWERTXHT20_3_MASK                                               0x3f000000
+#define PHY_BB_POWERTX_RATE5_POWERTXHT20_3_GET(x)                             (((x) & 0x3f000000) >> 24)
+#define PHY_BB_POWERTX_RATE5_POWERTXHT20_3_SET(x)                             (((x) << 24) & 0x3f000000)
+
+/* macros for BB_powertx_rate6 */
+#define PHY_BB_POWERTX_RATE6_ADDRESS                                                          0x0000a390
+#define PHY_BB_POWERTX_RATE6_OFFSET                                                           0x0000a390
+#define PHY_BB_POWERTX_RATE6_POWERTXHT20_4_MSB                                                         5
+#define PHY_BB_POWERTX_RATE6_POWERTXHT20_4_LSB                                                         0
+#define PHY_BB_POWERTX_RATE6_POWERTXHT20_4_MASK                                               0x0000003f
+#define PHY_BB_POWERTX_RATE6_POWERTXHT20_4_GET(x)                              (((x) & 0x0000003f) >> 0)
+#define PHY_BB_POWERTX_RATE6_POWERTXHT20_4_SET(x)                              (((x) << 0) & 0x0000003f)
+#define PHY_BB_POWERTX_RATE6_POWERTXHT20_5_MSB                                                        13
+#define PHY_BB_POWERTX_RATE6_POWERTXHT20_5_LSB                                                         8
+#define PHY_BB_POWERTX_RATE6_POWERTXHT20_5_MASK                                               0x00003f00
+#define PHY_BB_POWERTX_RATE6_POWERTXHT20_5_GET(x)                              (((x) & 0x00003f00) >> 8)
+#define PHY_BB_POWERTX_RATE6_POWERTXHT20_5_SET(x)                              (((x) << 8) & 0x00003f00)
+#define PHY_BB_POWERTX_RATE6_POWERTXHT20_6_MSB                                                        21
+#define PHY_BB_POWERTX_RATE6_POWERTXHT20_6_LSB                                                        16
+#define PHY_BB_POWERTX_RATE6_POWERTXHT20_6_MASK                                               0x003f0000
+#define PHY_BB_POWERTX_RATE6_POWERTXHT20_6_GET(x)                             (((x) & 0x003f0000) >> 16)
+#define PHY_BB_POWERTX_RATE6_POWERTXHT20_6_SET(x)                             (((x) << 16) & 0x003f0000)
+#define PHY_BB_POWERTX_RATE6_POWERTXHT20_7_MSB                                                        29
+#define PHY_BB_POWERTX_RATE6_POWERTXHT20_7_LSB                                                        24
+#define PHY_BB_POWERTX_RATE6_POWERTXHT20_7_MASK                                               0x3f000000
+#define PHY_BB_POWERTX_RATE6_POWERTXHT20_7_GET(x)                             (((x) & 0x3f000000) >> 24)
+#define PHY_BB_POWERTX_RATE6_POWERTXHT20_7_SET(x)                             (((x) << 24) & 0x3f000000)
+
+/* macros for BB_tpc_10 */
+#define PHY_BB_TPC_10_ADDRESS                                                                 0x0000a394
+#define PHY_BB_TPC_10_OFFSET                                                                  0x0000a394
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_0_MSB                                                         4
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_0_LSB                                                         0
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_0_MASK                                               0x0000001f
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_0_GET(x)                              (((x) & 0x0000001f) >> 0)
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_0_SET(x)                              (((x) << 0) & 0x0000001f)
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_1_MSB                                                         9
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_1_LSB                                                         5
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_1_MASK                                               0x000003e0
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_1_GET(x)                              (((x) & 0x000003e0) >> 5)
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_1_SET(x)                              (((x) << 5) & 0x000003e0)
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_2_MSB                                                        14
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_2_LSB                                                        10
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_2_MASK                                               0x00007c00
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_2_GET(x)                             (((x) & 0x00007c00) >> 10)
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_2_SET(x)                             (((x) << 10) & 0x00007c00)
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_3_MSB                                                        19
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_3_LSB                                                        15
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_3_MASK                                               0x000f8000
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_3_GET(x)                             (((x) & 0x000f8000) >> 15)
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_3_SET(x)                             (((x) << 15) & 0x000f8000)
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_4_MSB                                                        24
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_4_LSB                                                        20
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_4_MASK                                               0x01f00000
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_4_GET(x)                             (((x) & 0x01f00000) >> 20)
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_4_SET(x)                             (((x) << 20) & 0x01f00000)
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_5_MSB                                                        29
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_5_LSB                                                        25
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_5_MASK                                               0x3e000000
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_5_GET(x)                             (((x) & 0x3e000000) >> 25)
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_5_SET(x)                             (((x) << 25) & 0x3e000000)
+
+/* macros for BB_tpc_11_b0 */
+#define PHY_BB_TPC_11_B0_ADDRESS                                                              0x0000a398
+#define PHY_BB_TPC_11_B0_OFFSET                                                               0x0000a398
+#define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_6_MSB                                                      4
+#define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_6_LSB                                                      0
+#define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_6_MASK                                            0x0000001f
+#define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_6_GET(x)                           (((x) & 0x0000001f) >> 0)
+#define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_6_SET(x)                           (((x) << 0) & 0x0000001f)
+#define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_7_MSB                                                      9
+#define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_7_LSB                                                      5
+#define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_7_MASK                                            0x000003e0
+#define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_7_GET(x)                           (((x) & 0x000003e0) >> 5)
+#define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_7_SET(x)                           (((x) << 5) & 0x000003e0)
+#define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_MSB                                                        23
+#define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_LSB                                                        16
+#define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_MASK                                               0x00ff0000
+#define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_GET(x)                             (((x) & 0x00ff0000) >> 16)
+#define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_SET(x)                             (((x) << 16) & 0x00ff0000)
+#define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_PAL_ON_MSB                                                 31
+#define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_PAL_ON_LSB                                                 24
+#define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_PAL_ON_MASK                                        0xff000000
+#define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_PAL_ON_GET(x)                      (((x) & 0xff000000) >> 24)
+#define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_PAL_ON_SET(x)                      (((x) << 24) & 0xff000000)
+
+/* macros for BB_cal_chain_mask */
+#define PHY_BB_CAL_CHAIN_MASK_ADDRESS                                                         0x0000a39c
+#define PHY_BB_CAL_CHAIN_MASK_OFFSET                                                          0x0000a39c
+#define PHY_BB_CAL_CHAIN_MASK_CAL_CHAIN_MASK_MSB                                                       2
+#define PHY_BB_CAL_CHAIN_MASK_CAL_CHAIN_MASK_LSB                                                       0
+#define PHY_BB_CAL_CHAIN_MASK_CAL_CHAIN_MASK_MASK                                             0x00000007
+#define PHY_BB_CAL_CHAIN_MASK_CAL_CHAIN_MASK_GET(x)                            (((x) & 0x00000007) >> 0)
+#define PHY_BB_CAL_CHAIN_MASK_CAL_CHAIN_MASK_SET(x)                            (((x) << 0) & 0x00000007)
+
+/* macros for BB_powertx_sub */
+#define PHY_BB_POWERTX_SUB_ADDRESS                                                            0x0000a3bc
+#define PHY_BB_POWERTX_SUB_OFFSET                                                             0x0000a3bc
+#define PHY_BB_POWERTX_SUB_POWERTX_SUB_FOR_2CHAIN_MSB                                                  5
+#define PHY_BB_POWERTX_SUB_POWERTX_SUB_FOR_2CHAIN_LSB                                                  0
+#define PHY_BB_POWERTX_SUB_POWERTX_SUB_FOR_2CHAIN_MASK                                        0x0000003f
+#define PHY_BB_POWERTX_SUB_POWERTX_SUB_FOR_2CHAIN_GET(x)                       (((x) & 0x0000003f) >> 0)
+#define PHY_BB_POWERTX_SUB_POWERTX_SUB_FOR_2CHAIN_SET(x)                       (((x) << 0) & 0x0000003f)
+
+/* macros for BB_powertx_rate7 */
+#define PHY_BB_POWERTX_RATE7_ADDRESS                                                          0x0000a3c0
+#define PHY_BB_POWERTX_RATE7_OFFSET                                                           0x0000a3c0
+#define PHY_BB_POWERTX_RATE7_POWERTXHT40_0_MSB                                                         5
+#define PHY_BB_POWERTX_RATE7_POWERTXHT40_0_LSB                                                         0
+#define PHY_BB_POWERTX_RATE7_POWERTXHT40_0_MASK                                               0x0000003f
+#define PHY_BB_POWERTX_RATE7_POWERTXHT40_0_GET(x)                              (((x) & 0x0000003f) >> 0)
+#define PHY_BB_POWERTX_RATE7_POWERTXHT40_0_SET(x)                              (((x) << 0) & 0x0000003f)
+#define PHY_BB_POWERTX_RATE7_POWERTXHT40_1_MSB                                                        13
+#define PHY_BB_POWERTX_RATE7_POWERTXHT40_1_LSB                                                         8
+#define PHY_BB_POWERTX_RATE7_POWERTXHT40_1_MASK                                               0x00003f00
+#define PHY_BB_POWERTX_RATE7_POWERTXHT40_1_GET(x)                              (((x) & 0x00003f00) >> 8)
+#define PHY_BB_POWERTX_RATE7_POWERTXHT40_1_SET(x)                              (((x) << 8) & 0x00003f00)
+#define PHY_BB_POWERTX_RATE7_POWERTXHT40_2_MSB                                                        21
+#define PHY_BB_POWERTX_RATE7_POWERTXHT40_2_LSB                                                        16
+#define PHY_BB_POWERTX_RATE7_POWERTXHT40_2_MASK                                               0x003f0000
+#define PHY_BB_POWERTX_RATE7_POWERTXHT40_2_GET(x)                             (((x) & 0x003f0000) >> 16)
+#define PHY_BB_POWERTX_RATE7_POWERTXHT40_2_SET(x)                             (((x) << 16) & 0x003f0000)
+#define PHY_BB_POWERTX_RATE7_POWERTXHT40_3_MSB                                                        29
+#define PHY_BB_POWERTX_RATE7_POWERTXHT40_3_LSB                                                        24
+#define PHY_BB_POWERTX_RATE7_POWERTXHT40_3_MASK                                               0x3f000000
+#define PHY_BB_POWERTX_RATE7_POWERTXHT40_3_GET(x)                             (((x) & 0x3f000000) >> 24)
+#define PHY_BB_POWERTX_RATE7_POWERTXHT40_3_SET(x)                             (((x) << 24) & 0x3f000000)
+
+/* macros for BB_powertx_rate8 */
+#define PHY_BB_POWERTX_RATE8_ADDRESS                                                          0x0000a3c4
+#define PHY_BB_POWERTX_RATE8_OFFSET                                                           0x0000a3c4
+#define PHY_BB_POWERTX_RATE8_POWERTXHT40_4_MSB                                                         5
+#define PHY_BB_POWERTX_RATE8_POWERTXHT40_4_LSB                                                         0
+#define PHY_BB_POWERTX_RATE8_POWERTXHT40_4_MASK                                               0x0000003f
+#define PHY_BB_POWERTX_RATE8_POWERTXHT40_4_GET(x)                              (((x) & 0x0000003f) >> 0)
+#define PHY_BB_POWERTX_RATE8_POWERTXHT40_4_SET(x)                              (((x) << 0) & 0x0000003f)
+#define PHY_BB_POWERTX_RATE8_POWERTXHT40_5_MSB                                                        13
+#define PHY_BB_POWERTX_RATE8_POWERTXHT40_5_LSB                                                         8
+#define PHY_BB_POWERTX_RATE8_POWERTXHT40_5_MASK                                               0x00003f00
+#define PHY_BB_POWERTX_RATE8_POWERTXHT40_5_GET(x)                              (((x) & 0x00003f00) >> 8)
+#define PHY_BB_POWERTX_RATE8_POWERTXHT40_5_SET(x)                              (((x) << 8) & 0x00003f00)
+#define PHY_BB_POWERTX_RATE8_POWERTXHT40_6_MSB                                                        21
+#define PHY_BB_POWERTX_RATE8_POWERTXHT40_6_LSB                                                        16
+#define PHY_BB_POWERTX_RATE8_POWERTXHT40_6_MASK                                               0x003f0000
+#define PHY_BB_POWERTX_RATE8_POWERTXHT40_6_GET(x)                             (((x) & 0x003f0000) >> 16)
+#define PHY_BB_POWERTX_RATE8_POWERTXHT40_6_SET(x)                             (((x) << 16) & 0x003f0000)
+#define PHY_BB_POWERTX_RATE8_POWERTXHT40_7_MSB                                                        29
+#define PHY_BB_POWERTX_RATE8_POWERTXHT40_7_LSB                                                        24
+#define PHY_BB_POWERTX_RATE8_POWERTXHT40_7_MASK                                               0x3f000000
+#define PHY_BB_POWERTX_RATE8_POWERTXHT40_7_GET(x)                             (((x) & 0x3f000000) >> 24)
+#define PHY_BB_POWERTX_RATE8_POWERTXHT40_7_SET(x)                             (((x) << 24) & 0x3f000000)
+
+/* macros for BB_powertx_rate9 */
+#define PHY_BB_POWERTX_RATE9_ADDRESS                                                          0x0000a3c8
+#define PHY_BB_POWERTX_RATE9_OFFSET                                                           0x0000a3c8
+#define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_CCK_MSB                                                     5
+#define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_CCK_LSB                                                     0
+#define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_CCK_MASK                                           0x0000003f
+#define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_CCK_GET(x)                          (((x) & 0x0000003f) >> 0)
+#define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_CCK_SET(x)                          (((x) << 0) & 0x0000003f)
+#define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_OFDM_MSB                                                   13
+#define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_OFDM_LSB                                                    8
+#define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_OFDM_MASK                                          0x00003f00
+#define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_OFDM_GET(x)                         (((x) & 0x00003f00) >> 8)
+#define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_OFDM_SET(x)                         (((x) << 8) & 0x00003f00)
+#define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_CCK_MSB                                                    21
+#define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_CCK_LSB                                                    16
+#define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_CCK_MASK                                           0x003f0000
+#define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_CCK_GET(x)                         (((x) & 0x003f0000) >> 16)
+#define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_CCK_SET(x)                         (((x) << 16) & 0x003f0000)
+#define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_OFDM_MSB                                                   29
+#define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_OFDM_LSB                                                   24
+#define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_OFDM_MASK                                          0x3f000000
+#define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_OFDM_GET(x)                        (((x) & 0x3f000000) >> 24)
+#define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_OFDM_SET(x)                        (((x) << 24) & 0x3f000000)
+
+/* macros for BB_powertx_rate10 */
+#define PHY_BB_POWERTX_RATE10_ADDRESS                                                         0x0000a3cc
+#define PHY_BB_POWERTX_RATE10_OFFSET                                                          0x0000a3cc
+#define PHY_BB_POWERTX_RATE10_POWERTXHT20_8_MSB                                                        5
+#define PHY_BB_POWERTX_RATE10_POWERTXHT20_8_LSB                                                        0
+#define PHY_BB_POWERTX_RATE10_POWERTXHT20_8_MASK                                              0x0000003f
+#define PHY_BB_POWERTX_RATE10_POWERTXHT20_8_GET(x)                             (((x) & 0x0000003f) >> 0)
+#define PHY_BB_POWERTX_RATE10_POWERTXHT20_8_SET(x)                             (((x) << 0) & 0x0000003f)
+#define PHY_BB_POWERTX_RATE10_POWERTXHT20_9_MSB                                                       13
+#define PHY_BB_POWERTX_RATE10_POWERTXHT20_9_LSB                                                        8
+#define PHY_BB_POWERTX_RATE10_POWERTXHT20_9_MASK                                              0x00003f00
+#define PHY_BB_POWERTX_RATE10_POWERTXHT20_9_GET(x)                             (((x) & 0x00003f00) >> 8)
+#define PHY_BB_POWERTX_RATE10_POWERTXHT20_9_SET(x)                             (((x) << 8) & 0x00003f00)
+#define PHY_BB_POWERTX_RATE10_POWERTXHT20_10_MSB                                                      21
+#define PHY_BB_POWERTX_RATE10_POWERTXHT20_10_LSB                                                      16
+#define PHY_BB_POWERTX_RATE10_POWERTXHT20_10_MASK                                             0x003f0000
+#define PHY_BB_POWERTX_RATE10_POWERTXHT20_10_GET(x)                           (((x) & 0x003f0000) >> 16)
+#define PHY_BB_POWERTX_RATE10_POWERTXHT20_10_SET(x)                           (((x) << 16) & 0x003f0000)
+#define PHY_BB_POWERTX_RATE10_POWERTXHT20_11_MSB                                                      29
+#define PHY_BB_POWERTX_RATE10_POWERTXHT20_11_LSB                                                      24
+#define PHY_BB_POWERTX_RATE10_POWERTXHT20_11_MASK                                             0x3f000000
+#define PHY_BB_POWERTX_RATE10_POWERTXHT20_11_GET(x)                           (((x) & 0x3f000000) >> 24)
+#define PHY_BB_POWERTX_RATE10_POWERTXHT20_11_SET(x)                           (((x) << 24) & 0x3f000000)
+
+/* macros for BB_powertx_rate11 */
+#define PHY_BB_POWERTX_RATE11_ADDRESS                                                         0x0000a3d0
+#define PHY_BB_POWERTX_RATE11_OFFSET                                                          0x0000a3d0
+#define PHY_BB_POWERTX_RATE11_POWERTXHT20_12_MSB                                                       5
+#define PHY_BB_POWERTX_RATE11_POWERTXHT20_12_LSB                                                       0
+#define PHY_BB_POWERTX_RATE11_POWERTXHT20_12_MASK                                             0x0000003f
+#define PHY_BB_POWERTX_RATE11_POWERTXHT20_12_GET(x)                            (((x) & 0x0000003f) >> 0)
+#define PHY_BB_POWERTX_RATE11_POWERTXHT20_12_SET(x)                            (((x) << 0) & 0x0000003f)
+#define PHY_BB_POWERTX_RATE11_POWERTXHT20_13_MSB                                                      13
+#define PHY_BB_POWERTX_RATE11_POWERTXHT20_13_LSB                                                       8
+#define PHY_BB_POWERTX_RATE11_POWERTXHT20_13_MASK                                             0x00003f00
+#define PHY_BB_POWERTX_RATE11_POWERTXHT20_13_GET(x)                            (((x) & 0x00003f00) >> 8)
+#define PHY_BB_POWERTX_RATE11_POWERTXHT20_13_SET(x)                            (((x) << 8) & 0x00003f00)
+#define PHY_BB_POWERTX_RATE11_POWERTXHT40_12_MSB                                                      21
+#define PHY_BB_POWERTX_RATE11_POWERTXHT40_12_LSB                                                      16
+#define PHY_BB_POWERTX_RATE11_POWERTXHT40_12_MASK                                             0x003f0000
+#define PHY_BB_POWERTX_RATE11_POWERTXHT40_12_GET(x)                           (((x) & 0x003f0000) >> 16)
+#define PHY_BB_POWERTX_RATE11_POWERTXHT40_12_SET(x)                           (((x) << 16) & 0x003f0000)
+#define PHY_BB_POWERTX_RATE11_POWERTXHT40_13_MSB                                                      29
+#define PHY_BB_POWERTX_RATE11_POWERTXHT40_13_LSB                                                      24
+#define PHY_BB_POWERTX_RATE11_POWERTXHT40_13_MASK                                             0x3f000000
+#define PHY_BB_POWERTX_RATE11_POWERTXHT40_13_GET(x)                           (((x) & 0x3f000000) >> 24)
+#define PHY_BB_POWERTX_RATE11_POWERTXHT40_13_SET(x)                           (((x) << 24) & 0x3f000000)
+
+/* macros for BB_powertx_rate12 */
+#define PHY_BB_POWERTX_RATE12_ADDRESS                                                         0x0000a3d4
+#define PHY_BB_POWERTX_RATE12_OFFSET                                                          0x0000a3d4
+#define PHY_BB_POWERTX_RATE12_POWERTXHT40_8_MSB                                                        5
+#define PHY_BB_POWERTX_RATE12_POWERTXHT40_8_LSB                                                        0
+#define PHY_BB_POWERTX_RATE12_POWERTXHT40_8_MASK                                              0x0000003f
+#define PHY_BB_POWERTX_RATE12_POWERTXHT40_8_GET(x)                             (((x) & 0x0000003f) >> 0)
+#define PHY_BB_POWERTX_RATE12_POWERTXHT40_8_SET(x)                             (((x) << 0) & 0x0000003f)
+#define PHY_BB_POWERTX_RATE12_POWERTXHT40_9_MSB                                                       13
+#define PHY_BB_POWERTX_RATE12_POWERTXHT40_9_LSB                                                        8
+#define PHY_BB_POWERTX_RATE12_POWERTXHT40_9_MASK                                              0x00003f00
+#define PHY_BB_POWERTX_RATE12_POWERTXHT40_9_GET(x)                             (((x) & 0x00003f00) >> 8)
+#define PHY_BB_POWERTX_RATE12_POWERTXHT40_9_SET(x)                             (((x) << 8) & 0x00003f00)
+#define PHY_BB_POWERTX_RATE12_POWERTXHT40_10_MSB                                                      21
+#define PHY_BB_POWERTX_RATE12_POWERTXHT40_10_LSB                                                      16
+#define PHY_BB_POWERTX_RATE12_POWERTXHT40_10_MASK                                             0x003f0000
+#define PHY_BB_POWERTX_RATE12_POWERTXHT40_10_GET(x)                           (((x) & 0x003f0000) >> 16)
+#define PHY_BB_POWERTX_RATE12_POWERTXHT40_10_SET(x)                           (((x) << 16) & 0x003f0000)
+#define PHY_BB_POWERTX_RATE12_POWERTXHT40_11_MSB                                                      29
+#define PHY_BB_POWERTX_RATE12_POWERTXHT40_11_LSB                                                      24
+#define PHY_BB_POWERTX_RATE12_POWERTXHT40_11_MASK                                             0x3f000000
+#define PHY_BB_POWERTX_RATE12_POWERTXHT40_11_GET(x)                           (((x) & 0x3f000000) >> 24)
+#define PHY_BB_POWERTX_RATE12_POWERTXHT40_11_SET(x)                           (((x) << 24) & 0x3f000000)
+
+/* macros for BB_force_analog */
+#define PHY_BB_FORCE_ANALOG_ADDRESS                                                           0x0000a3d8
+#define PHY_BB_FORCE_ANALOG_OFFSET                                                            0x0000a3d8
+#define PHY_BB_FORCE_ANALOG_FORCE_XPAON_MSB                                                            0
+#define PHY_BB_FORCE_ANALOG_FORCE_XPAON_LSB                                                            0
+#define PHY_BB_FORCE_ANALOG_FORCE_XPAON_MASK                                                  0x00000001
+#define PHY_BB_FORCE_ANALOG_FORCE_XPAON_GET(x)                                 (((x) & 0x00000001) >> 0)
+#define PHY_BB_FORCE_ANALOG_FORCE_XPAON_SET(x)                                 (((x) << 0) & 0x00000001)
+#define PHY_BB_FORCE_ANALOG_FORCED_XPAON_MSB                                                           3
+#define PHY_BB_FORCE_ANALOG_FORCED_XPAON_LSB                                                           1
+#define PHY_BB_FORCE_ANALOG_FORCED_XPAON_MASK                                                 0x0000000e
+#define PHY_BB_FORCE_ANALOG_FORCED_XPAON_GET(x)                                (((x) & 0x0000000e) >> 1)
+#define PHY_BB_FORCE_ANALOG_FORCED_XPAON_SET(x)                                (((x) << 1) & 0x0000000e)
+#define PHY_BB_FORCE_ANALOG_FORCE_PDADC_PWD_MSB                                                        4
+#define PHY_BB_FORCE_ANALOG_FORCE_PDADC_PWD_LSB                                                        4
+#define PHY_BB_FORCE_ANALOG_FORCE_PDADC_PWD_MASK                                              0x00000010
+#define PHY_BB_FORCE_ANALOG_FORCE_PDADC_PWD_GET(x)                             (((x) & 0x00000010) >> 4)
+#define PHY_BB_FORCE_ANALOG_FORCE_PDADC_PWD_SET(x)                             (((x) << 4) & 0x00000010)
+#define PHY_BB_FORCE_ANALOG_FORCED_PDADC_PWD_MSB                                                       7
+#define PHY_BB_FORCE_ANALOG_FORCED_PDADC_PWD_LSB                                                       5
+#define PHY_BB_FORCE_ANALOG_FORCED_PDADC_PWD_MASK                                             0x000000e0
+#define PHY_BB_FORCE_ANALOG_FORCED_PDADC_PWD_GET(x)                            (((x) & 0x000000e0) >> 5)
+#define PHY_BB_FORCE_ANALOG_FORCED_PDADC_PWD_SET(x)                            (((x) << 5) & 0x000000e0)
+
+/* macros for BB_tpc_12 */
+#define PHY_BB_TPC_12_ADDRESS                                                                 0x0000a3dc
+#define PHY_BB_TPC_12_OFFSET                                                                  0x0000a3dc
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_0_MSB                                                         4
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_0_LSB                                                         0
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_0_MASK                                               0x0000001f
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_0_GET(x)                              (((x) & 0x0000001f) >> 0)
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_0_SET(x)                              (((x) << 0) & 0x0000001f)
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_1_MSB                                                         9
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_1_LSB                                                         5
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_1_MASK                                               0x000003e0
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_1_GET(x)                              (((x) & 0x000003e0) >> 5)
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_1_SET(x)                              (((x) << 5) & 0x000003e0)
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_2_MSB                                                        14
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_2_LSB                                                        10
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_2_MASK                                               0x00007c00
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_2_GET(x)                             (((x) & 0x00007c00) >> 10)
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_2_SET(x)                             (((x) << 10) & 0x00007c00)
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_3_MSB                                                        19
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_3_LSB                                                        15
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_3_MASK                                               0x000f8000
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_3_GET(x)                             (((x) & 0x000f8000) >> 15)
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_3_SET(x)                             (((x) << 15) & 0x000f8000)
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_4_MSB                                                        24
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_4_LSB                                                        20
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_4_MASK                                               0x01f00000
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_4_GET(x)                             (((x) & 0x01f00000) >> 20)
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_4_SET(x)                             (((x) << 20) & 0x01f00000)
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_5_MSB                                                        29
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_5_LSB                                                        25
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_5_MASK                                               0x3e000000
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_5_GET(x)                             (((x) & 0x3e000000) >> 25)
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_5_SET(x)                             (((x) << 25) & 0x3e000000)
+
+/* macros for BB_tpc_13 */
+#define PHY_BB_TPC_13_ADDRESS                                                                 0x0000a3e0
+#define PHY_BB_TPC_13_OFFSET                                                                  0x0000a3e0
+#define PHY_BB_TPC_13_DESIRED_SCALE_HT40_6_MSB                                                         4
+#define PHY_BB_TPC_13_DESIRED_SCALE_HT40_6_LSB                                                         0
+#define PHY_BB_TPC_13_DESIRED_SCALE_HT40_6_MASK                                               0x0000001f
+#define PHY_BB_TPC_13_DESIRED_SCALE_HT40_6_GET(x)                              (((x) & 0x0000001f) >> 0)
+#define PHY_BB_TPC_13_DESIRED_SCALE_HT40_6_SET(x)                              (((x) << 0) & 0x0000001f)
+#define PHY_BB_TPC_13_DESIRED_SCALE_HT40_7_MSB                                                         9
+#define PHY_BB_TPC_13_DESIRED_SCALE_HT40_7_LSB                                                         5
+#define PHY_BB_TPC_13_DESIRED_SCALE_HT40_7_MASK                                               0x000003e0
+#define PHY_BB_TPC_13_DESIRED_SCALE_HT40_7_GET(x)                              (((x) & 0x000003e0) >> 5)
+#define PHY_BB_TPC_13_DESIRED_SCALE_HT40_7_SET(x)                              (((x) << 5) & 0x000003e0)
+
+/* macros for BB_tpc_14 */
+#define PHY_BB_TPC_14_ADDRESS                                                                 0x0000a3e4
+#define PHY_BB_TPC_14_OFFSET                                                                  0x0000a3e4
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_8_MSB                                                         4
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_8_LSB                                                         0
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_8_MASK                                               0x0000001f
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_8_GET(x)                              (((x) & 0x0000001f) >> 0)
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_8_SET(x)                              (((x) << 0) & 0x0000001f)
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_9_MSB                                                         9
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_9_LSB                                                         5
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_9_MASK                                               0x000003e0
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_9_GET(x)                              (((x) & 0x000003e0) >> 5)
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_9_SET(x)                              (((x) << 5) & 0x000003e0)
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_10_MSB                                                       14
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_10_LSB                                                       10
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_10_MASK                                              0x00007c00
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_10_GET(x)                            (((x) & 0x00007c00) >> 10)
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_10_SET(x)                            (((x) << 10) & 0x00007c00)
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_11_MSB                                                       19
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_11_LSB                                                       15
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_11_MASK                                              0x000f8000
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_11_GET(x)                            (((x) & 0x000f8000) >> 15)
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_11_SET(x)                            (((x) << 15) & 0x000f8000)
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_12_MSB                                                       24
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_12_LSB                                                       20
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_12_MASK                                              0x01f00000
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_12_GET(x)                            (((x) & 0x01f00000) >> 20)
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_12_SET(x)                            (((x) << 20) & 0x01f00000)
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_13_MSB                                                       29
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_13_LSB                                                       25
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_13_MASK                                              0x3e000000
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_13_GET(x)                            (((x) & 0x3e000000) >> 25)
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_13_SET(x)                            (((x) << 25) & 0x3e000000)
+
+/* macros for BB_tpc_15 */
+#define PHY_BB_TPC_15_ADDRESS                                                                 0x0000a3e8
+#define PHY_BB_TPC_15_OFFSET                                                                  0x0000a3e8
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_8_MSB                                                         4
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_8_LSB                                                         0
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_8_MASK                                               0x0000001f
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_8_GET(x)                              (((x) & 0x0000001f) >> 0)
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_8_SET(x)                              (((x) << 0) & 0x0000001f)
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_9_MSB                                                         9
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_9_LSB                                                         5
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_9_MASK                                               0x000003e0
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_9_GET(x)                              (((x) & 0x000003e0) >> 5)
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_9_SET(x)                              (((x) << 5) & 0x000003e0)
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_10_MSB                                                       14
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_10_LSB                                                       10
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_10_MASK                                              0x00007c00
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_10_GET(x)                            (((x) & 0x00007c00) >> 10)
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_10_SET(x)                            (((x) << 10) & 0x00007c00)
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_11_MSB                                                       19
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_11_LSB                                                       15
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_11_MASK                                              0x000f8000
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_11_GET(x)                            (((x) & 0x000f8000) >> 15)
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_11_SET(x)                            (((x) << 15) & 0x000f8000)
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_12_MSB                                                       24
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_12_LSB                                                       20
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_12_MASK                                              0x01f00000
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_12_GET(x)                            (((x) & 0x01f00000) >> 20)
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_12_SET(x)                            (((x) << 20) & 0x01f00000)
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_13_MSB                                                       29
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_13_LSB                                                       25
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_13_MASK                                              0x3e000000
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_13_GET(x)                            (((x) & 0x3e000000) >> 25)
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_13_SET(x)                            (((x) << 25) & 0x3e000000)
+
+/* macros for BB_tpc_16 */
+#define PHY_BB_TPC_16_ADDRESS                                                                 0x0000a3ec
+#define PHY_BB_TPC_16_OFFSET                                                                  0x0000a3ec
+#define PHY_BB_TPC_16_PDADC_PAR_CORR_CCK_MSB                                                          13
+#define PHY_BB_TPC_16_PDADC_PAR_CORR_CCK_LSB                                                           8
+#define PHY_BB_TPC_16_PDADC_PAR_CORR_CCK_MASK                                                 0x00003f00
+#define PHY_BB_TPC_16_PDADC_PAR_CORR_CCK_GET(x)                                (((x) & 0x00003f00) >> 8)
+#define PHY_BB_TPC_16_PDADC_PAR_CORR_CCK_SET(x)                                (((x) << 8) & 0x00003f00)
+#define PHY_BB_TPC_16_PDADC_PAR_CORR_OFDM_MSB                                                         21
+#define PHY_BB_TPC_16_PDADC_PAR_CORR_OFDM_LSB                                                         16
+#define PHY_BB_TPC_16_PDADC_PAR_CORR_OFDM_MASK                                                0x003f0000
+#define PHY_BB_TPC_16_PDADC_PAR_CORR_OFDM_GET(x)                              (((x) & 0x003f0000) >> 16)
+#define PHY_BB_TPC_16_PDADC_PAR_CORR_OFDM_SET(x)                              (((x) << 16) & 0x003f0000)
+#define PHY_BB_TPC_16_PDADC_PAR_CORR_HT40_MSB                                                         29
+#define PHY_BB_TPC_16_PDADC_PAR_CORR_HT40_LSB                                                         24
+#define PHY_BB_TPC_16_PDADC_PAR_CORR_HT40_MASK                                                0x3f000000
+#define PHY_BB_TPC_16_PDADC_PAR_CORR_HT40_GET(x)                              (((x) & 0x3f000000) >> 24)
+#define PHY_BB_TPC_16_PDADC_PAR_CORR_HT40_SET(x)                              (((x) << 24) & 0x3f000000)
+
+/* macros for BB_tpc_17 */
+#define PHY_BB_TPC_17_ADDRESS                                                                 0x0000a3f0
+#define PHY_BB_TPC_17_OFFSET                                                                  0x0000a3f0
+#define PHY_BB_TPC_17_ENABLE_PAL_MSB                                                                   0
+#define PHY_BB_TPC_17_ENABLE_PAL_LSB                                                                   0
+#define PHY_BB_TPC_17_ENABLE_PAL_MASK                                                         0x00000001
+#define PHY_BB_TPC_17_ENABLE_PAL_GET(x)                                        (((x) & 0x00000001) >> 0)
+#define PHY_BB_TPC_17_ENABLE_PAL_SET(x)                                        (((x) << 0) & 0x00000001)
+#define PHY_BB_TPC_17_ENABLE_PAL_CCK_MSB                                                               1
+#define PHY_BB_TPC_17_ENABLE_PAL_CCK_LSB                                                               1
+#define PHY_BB_TPC_17_ENABLE_PAL_CCK_MASK                                                     0x00000002
+#define PHY_BB_TPC_17_ENABLE_PAL_CCK_GET(x)                                    (((x) & 0x00000002) >> 1)
+#define PHY_BB_TPC_17_ENABLE_PAL_CCK_SET(x)                                    (((x) << 1) & 0x00000002)
+#define PHY_BB_TPC_17_ENABLE_PAL_OFDM_20_MSB                                                           2
+#define PHY_BB_TPC_17_ENABLE_PAL_OFDM_20_LSB                                                           2
+#define PHY_BB_TPC_17_ENABLE_PAL_OFDM_20_MASK                                                 0x00000004
+#define PHY_BB_TPC_17_ENABLE_PAL_OFDM_20_GET(x)                                (((x) & 0x00000004) >> 2)
+#define PHY_BB_TPC_17_ENABLE_PAL_OFDM_20_SET(x)                                (((x) << 2) & 0x00000004)
+#define PHY_BB_TPC_17_ENABLE_PAL_OFDM_40_MSB                                                           3
+#define PHY_BB_TPC_17_ENABLE_PAL_OFDM_40_LSB                                                           3
+#define PHY_BB_TPC_17_ENABLE_PAL_OFDM_40_MASK                                                 0x00000008
+#define PHY_BB_TPC_17_ENABLE_PAL_OFDM_40_GET(x)                                (((x) & 0x00000008) >> 3)
+#define PHY_BB_TPC_17_ENABLE_PAL_OFDM_40_SET(x)                                (((x) << 3) & 0x00000008)
+#define PHY_BB_TPC_17_PAL_POWER_THRESHOLD_MSB                                                          9
+#define PHY_BB_TPC_17_PAL_POWER_THRESHOLD_LSB                                                          4
+#define PHY_BB_TPC_17_PAL_POWER_THRESHOLD_MASK                                                0x000003f0
+#define PHY_BB_TPC_17_PAL_POWER_THRESHOLD_GET(x)                               (((x) & 0x000003f0) >> 4)
+#define PHY_BB_TPC_17_PAL_POWER_THRESHOLD_SET(x)                               (((x) << 4) & 0x000003f0)
+#define PHY_BB_TPC_17_FORCE_PAL_LOCKED_MSB                                                            10
+#define PHY_BB_TPC_17_FORCE_PAL_LOCKED_LSB                                                            10
+#define PHY_BB_TPC_17_FORCE_PAL_LOCKED_MASK                                                   0x00000400
+#define PHY_BB_TPC_17_FORCE_PAL_LOCKED_GET(x)                                 (((x) & 0x00000400) >> 10)
+#define PHY_BB_TPC_17_FORCE_PAL_LOCKED_SET(x)                                 (((x) << 10) & 0x00000400)
+#define PHY_BB_TPC_17_INIT_TX_GAIN_SETTING_PAL_ON_MSB                                                 16
+#define PHY_BB_TPC_17_INIT_TX_GAIN_SETTING_PAL_ON_LSB                                                 11
+#define PHY_BB_TPC_17_INIT_TX_GAIN_SETTING_PAL_ON_MASK                                        0x0001f800
+#define PHY_BB_TPC_17_INIT_TX_GAIN_SETTING_PAL_ON_GET(x)                      (((x) & 0x0001f800) >> 11)
+#define PHY_BB_TPC_17_INIT_TX_GAIN_SETTING_PAL_ON_SET(x)                      (((x) << 11) & 0x0001f800)
+
+/* macros for BB_tpc_18 */
+#define PHY_BB_TPC_18_ADDRESS                                                                 0x0000a3f4
+#define PHY_BB_TPC_18_OFFSET                                                                  0x0000a3f4
+#define PHY_BB_TPC_18_THERM_CAL_VALUE_MSB                                                              7
+#define PHY_BB_TPC_18_THERM_CAL_VALUE_LSB                                                              0
+#define PHY_BB_TPC_18_THERM_CAL_VALUE_MASK                                                    0x000000ff
+#define PHY_BB_TPC_18_THERM_CAL_VALUE_GET(x)                                   (((x) & 0x000000ff) >> 0)
+#define PHY_BB_TPC_18_THERM_CAL_VALUE_SET(x)                                   (((x) << 0) & 0x000000ff)
+#define PHY_BB_TPC_18_VOLT_CAL_VALUE_MSB                                                              15
+#define PHY_BB_TPC_18_VOLT_CAL_VALUE_LSB                                                               8
+#define PHY_BB_TPC_18_VOLT_CAL_VALUE_MASK                                                     0x0000ff00
+#define PHY_BB_TPC_18_VOLT_CAL_VALUE_GET(x)                                    (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_TPC_18_VOLT_CAL_VALUE_SET(x)                                    (((x) << 8) & 0x0000ff00)
+#define PHY_BB_TPC_18_USE_LEGACY_TPC_MSB                                                              16
+#define PHY_BB_TPC_18_USE_LEGACY_TPC_LSB                                                              16
+#define PHY_BB_TPC_18_USE_LEGACY_TPC_MASK                                                     0x00010000
+#define PHY_BB_TPC_18_USE_LEGACY_TPC_GET(x)                                   (((x) & 0x00010000) >> 16)
+#define PHY_BB_TPC_18_USE_LEGACY_TPC_SET(x)                                   (((x) << 16) & 0x00010000)
+
+/* macros for BB_tpc_19 */
+#define PHY_BB_TPC_19_ADDRESS                                                                 0x0000a3f8
+#define PHY_BB_TPC_19_OFFSET                                                                  0x0000a3f8
+#define PHY_BB_TPC_19_ALPHA_THERM_MSB                                                                  7
+#define PHY_BB_TPC_19_ALPHA_THERM_LSB                                                                  0
+#define PHY_BB_TPC_19_ALPHA_THERM_MASK                                                        0x000000ff
+#define PHY_BB_TPC_19_ALPHA_THERM_GET(x)                                       (((x) & 0x000000ff) >> 0)
+#define PHY_BB_TPC_19_ALPHA_THERM_SET(x)                                       (((x) << 0) & 0x000000ff)
+#define PHY_BB_TPC_19_ALPHA_THERM_PAL_ON_MSB                                                          15
+#define PHY_BB_TPC_19_ALPHA_THERM_PAL_ON_LSB                                                           8
+#define PHY_BB_TPC_19_ALPHA_THERM_PAL_ON_MASK                                                 0x0000ff00
+#define PHY_BB_TPC_19_ALPHA_THERM_PAL_ON_GET(x)                                (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_TPC_19_ALPHA_THERM_PAL_ON_SET(x)                                (((x) << 8) & 0x0000ff00)
+#define PHY_BB_TPC_19_ALPHA_VOLT_MSB                                                                  20
+#define PHY_BB_TPC_19_ALPHA_VOLT_LSB                                                                  16
+#define PHY_BB_TPC_19_ALPHA_VOLT_MASK                                                         0x001f0000
+#define PHY_BB_TPC_19_ALPHA_VOLT_GET(x)                                       (((x) & 0x001f0000) >> 16)
+#define PHY_BB_TPC_19_ALPHA_VOLT_SET(x)                                       (((x) << 16) & 0x001f0000)
+#define PHY_BB_TPC_19_ALPHA_VOLT_PAL_ON_MSB                                                           25
+#define PHY_BB_TPC_19_ALPHA_VOLT_PAL_ON_LSB                                                           21
+#define PHY_BB_TPC_19_ALPHA_VOLT_PAL_ON_MASK                                                  0x03e00000
+#define PHY_BB_TPC_19_ALPHA_VOLT_PAL_ON_GET(x)                                (((x) & 0x03e00000) >> 21)
+#define PHY_BB_TPC_19_ALPHA_VOLT_PAL_ON_SET(x)                                (((x) << 21) & 0x03e00000)
+
+/* macros for BB_tpc_20 */
+#define PHY_BB_TPC_20_ADDRESS                                                                 0x0000a3fc
+#define PHY_BB_TPC_20_OFFSET                                                                  0x0000a3fc
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_0_MSB                                                             0
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_0_LSB                                                             0
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_0_MASK                                                   0x00000001
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_0_GET(x)                                  (((x) & 0x00000001) >> 0)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_0_SET(x)                                  (((x) << 0) & 0x00000001)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_1_MSB                                                             1
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_1_LSB                                                             1
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_1_MASK                                                   0x00000002
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_1_GET(x)                                  (((x) & 0x00000002) >> 1)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_1_SET(x)                                  (((x) << 1) & 0x00000002)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_2_MSB                                                             2
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_2_LSB                                                             2
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_2_MASK                                                   0x00000004
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_2_GET(x)                                  (((x) & 0x00000004) >> 2)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_2_SET(x)                                  (((x) << 2) & 0x00000004)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_3_MSB                                                             3
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_3_LSB                                                             3
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_3_MASK                                                   0x00000008
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_3_GET(x)                                  (((x) & 0x00000008) >> 3)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_3_SET(x)                                  (((x) << 3) & 0x00000008)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_4_MSB                                                             4
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_4_LSB                                                             4
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_4_MASK                                                   0x00000010
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_4_GET(x)                                  (((x) & 0x00000010) >> 4)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_4_SET(x)                                  (((x) << 4) & 0x00000010)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_5_MSB                                                             5
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_5_LSB                                                             5
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_5_MASK                                                   0x00000020
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_5_GET(x)                                  (((x) & 0x00000020) >> 5)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_5_SET(x)                                  (((x) << 5) & 0x00000020)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_6_MSB                                                             6
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_6_LSB                                                             6
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_6_MASK                                                   0x00000040
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_6_GET(x)                                  (((x) & 0x00000040) >> 6)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_6_SET(x)                                  (((x) << 6) & 0x00000040)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_7_MSB                                                             7
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_7_LSB                                                             7
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_7_MASK                                                   0x00000080
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_7_GET(x)                                  (((x) & 0x00000080) >> 7)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_7_SET(x)                                  (((x) << 7) & 0x00000080)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_8_MSB                                                             8
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_8_LSB                                                             8
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_8_MASK                                                   0x00000100
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_8_GET(x)                                  (((x) & 0x00000100) >> 8)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_8_SET(x)                                  (((x) << 8) & 0x00000100)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_9_MSB                                                             9
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_9_LSB                                                             9
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_9_MASK                                                   0x00000200
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_9_GET(x)                                  (((x) & 0x00000200) >> 9)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_9_SET(x)                                  (((x) << 9) & 0x00000200)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_10_MSB                                                           10
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_10_LSB                                                           10
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_10_MASK                                                  0x00000400
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_10_GET(x)                                (((x) & 0x00000400) >> 10)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_10_SET(x)                                (((x) << 10) & 0x00000400)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_11_MSB                                                           11
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_11_LSB                                                           11
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_11_MASK                                                  0x00000800
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_11_GET(x)                                (((x) & 0x00000800) >> 11)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_11_SET(x)                                (((x) << 11) & 0x00000800)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_12_MSB                                                           12
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_12_LSB                                                           12
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_12_MASK                                                  0x00001000
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_12_GET(x)                                (((x) & 0x00001000) >> 12)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_12_SET(x)                                (((x) << 12) & 0x00001000)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_13_MSB                                                           13
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_13_LSB                                                           13
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_13_MASK                                                  0x00002000
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_13_GET(x)                                (((x) & 0x00002000) >> 13)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_13_SET(x)                                (((x) << 13) & 0x00002000)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_14_MSB                                                           14
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_14_LSB                                                           14
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_14_MASK                                                  0x00004000
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_14_GET(x)                                (((x) & 0x00004000) >> 14)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_14_SET(x)                                (((x) << 14) & 0x00004000)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_15_MSB                                                           15
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_15_LSB                                                           15
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_15_MASK                                                  0x00008000
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_15_GET(x)                                (((x) & 0x00008000) >> 15)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_15_SET(x)                                (((x) << 15) & 0x00008000)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_16_MSB                                                           16
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_16_LSB                                                           16
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_16_MASK                                                  0x00010000
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_16_GET(x)                                (((x) & 0x00010000) >> 16)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_16_SET(x)                                (((x) << 16) & 0x00010000)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_17_MSB                                                           17
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_17_LSB                                                           17
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_17_MASK                                                  0x00020000
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_17_GET(x)                                (((x) & 0x00020000) >> 17)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_17_SET(x)                                (((x) << 17) & 0x00020000)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_18_MSB                                                           18
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_18_LSB                                                           18
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_18_MASK                                                  0x00040000
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_18_GET(x)                                (((x) & 0x00040000) >> 18)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_18_SET(x)                                (((x) << 18) & 0x00040000)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_19_MSB                                                           19
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_19_LSB                                                           19
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_19_MASK                                                  0x00080000
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_19_GET(x)                                (((x) & 0x00080000) >> 19)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_19_SET(x)                                (((x) << 19) & 0x00080000)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_20_MSB                                                           20
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_20_LSB                                                           20
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_20_MASK                                                  0x00100000
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_20_GET(x)                                (((x) & 0x00100000) >> 20)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_20_SET(x)                                (((x) << 20) & 0x00100000)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_21_MSB                                                           21
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_21_LSB                                                           21
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_21_MASK                                                  0x00200000
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_21_GET(x)                                (((x) & 0x00200000) >> 21)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_21_SET(x)                                (((x) << 21) & 0x00200000)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_22_MSB                                                           22
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_22_LSB                                                           22
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_22_MASK                                                  0x00400000
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_22_GET(x)                                (((x) & 0x00400000) >> 22)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_22_SET(x)                                (((x) << 22) & 0x00400000)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_23_MSB                                                           23
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_23_LSB                                                           23
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_23_MASK                                                  0x00800000
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_23_GET(x)                                (((x) & 0x00800000) >> 23)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_23_SET(x)                                (((x) << 23) & 0x00800000)
+
+/* macros for BB_tx_gain_tab_1 */
+#define PHY_BB_TX_GAIN_TAB_1_ADDRESS                                                          0x0000a400
+#define PHY_BB_TX_GAIN_TAB_1_OFFSET                                                           0x0000a400
+#define PHY_BB_TX_GAIN_TAB_1_TG_TABLE1_MSB                                                            31
+#define PHY_BB_TX_GAIN_TAB_1_TG_TABLE1_LSB                                                             0
+#define PHY_BB_TX_GAIN_TAB_1_TG_TABLE1_MASK                                                   0xffffffff
+#define PHY_BB_TX_GAIN_TAB_1_TG_TABLE1_GET(x)                                  (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_1_TG_TABLE1_SET(x)                                  (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_2 */
+#define PHY_BB_TX_GAIN_TAB_2_ADDRESS                                                          0x0000a404
+#define PHY_BB_TX_GAIN_TAB_2_OFFSET                                                           0x0000a404
+#define PHY_BB_TX_GAIN_TAB_2_TG_TABLE2_MSB                                                            31
+#define PHY_BB_TX_GAIN_TAB_2_TG_TABLE2_LSB                                                             0
+#define PHY_BB_TX_GAIN_TAB_2_TG_TABLE2_MASK                                                   0xffffffff
+#define PHY_BB_TX_GAIN_TAB_2_TG_TABLE2_GET(x)                                  (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_2_TG_TABLE2_SET(x)                                  (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_3 */
+#define PHY_BB_TX_GAIN_TAB_3_ADDRESS                                                          0x0000a408
+#define PHY_BB_TX_GAIN_TAB_3_OFFSET                                                           0x0000a408
+#define PHY_BB_TX_GAIN_TAB_3_TG_TABLE3_MSB                                                            31
+#define PHY_BB_TX_GAIN_TAB_3_TG_TABLE3_LSB                                                             0
+#define PHY_BB_TX_GAIN_TAB_3_TG_TABLE3_MASK                                                   0xffffffff
+#define PHY_BB_TX_GAIN_TAB_3_TG_TABLE3_GET(x)                                  (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_3_TG_TABLE3_SET(x)                                  (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_4 */
+#define PHY_BB_TX_GAIN_TAB_4_ADDRESS                                                          0x0000a40c
+#define PHY_BB_TX_GAIN_TAB_4_OFFSET                                                           0x0000a40c
+#define PHY_BB_TX_GAIN_TAB_4_TG_TABLE4_MSB                                                            31
+#define PHY_BB_TX_GAIN_TAB_4_TG_TABLE4_LSB                                                             0
+#define PHY_BB_TX_GAIN_TAB_4_TG_TABLE4_MASK                                                   0xffffffff
+#define PHY_BB_TX_GAIN_TAB_4_TG_TABLE4_GET(x)                                  (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_4_TG_TABLE4_SET(x)                                  (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_5 */
+#define PHY_BB_TX_GAIN_TAB_5_ADDRESS                                                          0x0000a410
+#define PHY_BB_TX_GAIN_TAB_5_OFFSET                                                           0x0000a410
+#define PHY_BB_TX_GAIN_TAB_5_TG_TABLE5_MSB                                                            31
+#define PHY_BB_TX_GAIN_TAB_5_TG_TABLE5_LSB                                                             0
+#define PHY_BB_TX_GAIN_TAB_5_TG_TABLE5_MASK                                                   0xffffffff
+#define PHY_BB_TX_GAIN_TAB_5_TG_TABLE5_GET(x)                                  (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_5_TG_TABLE5_SET(x)                                  (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_6 */
+#define PHY_BB_TX_GAIN_TAB_6_ADDRESS                                                          0x0000a414
+#define PHY_BB_TX_GAIN_TAB_6_OFFSET                                                           0x0000a414
+#define PHY_BB_TX_GAIN_TAB_6_TG_TABLE6_MSB                                                            31
+#define PHY_BB_TX_GAIN_TAB_6_TG_TABLE6_LSB                                                             0
+#define PHY_BB_TX_GAIN_TAB_6_TG_TABLE6_MASK                                                   0xffffffff
+#define PHY_BB_TX_GAIN_TAB_6_TG_TABLE6_GET(x)                                  (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_6_TG_TABLE6_SET(x)                                  (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_7 */
+#define PHY_BB_TX_GAIN_TAB_7_ADDRESS                                                          0x0000a418
+#define PHY_BB_TX_GAIN_TAB_7_OFFSET                                                           0x0000a418
+#define PHY_BB_TX_GAIN_TAB_7_TG_TABLE7_MSB                                                            31
+#define PHY_BB_TX_GAIN_TAB_7_TG_TABLE7_LSB                                                             0
+#define PHY_BB_TX_GAIN_TAB_7_TG_TABLE7_MASK                                                   0xffffffff
+#define PHY_BB_TX_GAIN_TAB_7_TG_TABLE7_GET(x)                                  (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_7_TG_TABLE7_SET(x)                                  (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_8 */
+#define PHY_BB_TX_GAIN_TAB_8_ADDRESS                                                          0x0000a41c
+#define PHY_BB_TX_GAIN_TAB_8_OFFSET                                                           0x0000a41c
+#define PHY_BB_TX_GAIN_TAB_8_TG_TABLE8_MSB                                                            31
+#define PHY_BB_TX_GAIN_TAB_8_TG_TABLE8_LSB                                                             0
+#define PHY_BB_TX_GAIN_TAB_8_TG_TABLE8_MASK                                                   0xffffffff
+#define PHY_BB_TX_GAIN_TAB_8_TG_TABLE8_GET(x)                                  (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_8_TG_TABLE8_SET(x)                                  (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_9 */
+#define PHY_BB_TX_GAIN_TAB_9_ADDRESS                                                          0x0000a420
+#define PHY_BB_TX_GAIN_TAB_9_OFFSET                                                           0x0000a420
+#define PHY_BB_TX_GAIN_TAB_9_TG_TABLE9_MSB                                                            31
+#define PHY_BB_TX_GAIN_TAB_9_TG_TABLE9_LSB                                                             0
+#define PHY_BB_TX_GAIN_TAB_9_TG_TABLE9_MASK                                                   0xffffffff
+#define PHY_BB_TX_GAIN_TAB_9_TG_TABLE9_GET(x)                                  (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_9_TG_TABLE9_SET(x)                                  (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_10 */
+#define PHY_BB_TX_GAIN_TAB_10_ADDRESS                                                         0x0000a424
+#define PHY_BB_TX_GAIN_TAB_10_OFFSET                                                          0x0000a424
+#define PHY_BB_TX_GAIN_TAB_10_TG_TABLE10_MSB                                                          31
+#define PHY_BB_TX_GAIN_TAB_10_TG_TABLE10_LSB                                                           0
+#define PHY_BB_TX_GAIN_TAB_10_TG_TABLE10_MASK                                                 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_10_TG_TABLE10_GET(x)                                (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_10_TG_TABLE10_SET(x)                                (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_11 */
+#define PHY_BB_TX_GAIN_TAB_11_ADDRESS                                                         0x0000a428
+#define PHY_BB_TX_GAIN_TAB_11_OFFSET                                                          0x0000a428
+#define PHY_BB_TX_GAIN_TAB_11_TG_TABLE11_MSB                                                          31
+#define PHY_BB_TX_GAIN_TAB_11_TG_TABLE11_LSB                                                           0
+#define PHY_BB_TX_GAIN_TAB_11_TG_TABLE11_MASK                                                 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_11_TG_TABLE11_GET(x)                                (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_11_TG_TABLE11_SET(x)                                (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_12 */
+#define PHY_BB_TX_GAIN_TAB_12_ADDRESS                                                         0x0000a42c
+#define PHY_BB_TX_GAIN_TAB_12_OFFSET                                                          0x0000a42c
+#define PHY_BB_TX_GAIN_TAB_12_TG_TABLE12_MSB                                                          31
+#define PHY_BB_TX_GAIN_TAB_12_TG_TABLE12_LSB                                                           0
+#define PHY_BB_TX_GAIN_TAB_12_TG_TABLE12_MASK                                                 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_12_TG_TABLE12_GET(x)                                (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_12_TG_TABLE12_SET(x)                                (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_13 */
+#define PHY_BB_TX_GAIN_TAB_13_ADDRESS                                                         0x0000a430
+#define PHY_BB_TX_GAIN_TAB_13_OFFSET                                                          0x0000a430
+#define PHY_BB_TX_GAIN_TAB_13_TG_TABLE13_MSB                                                          31
+#define PHY_BB_TX_GAIN_TAB_13_TG_TABLE13_LSB                                                           0
+#define PHY_BB_TX_GAIN_TAB_13_TG_TABLE13_MASK                                                 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_13_TG_TABLE13_GET(x)                                (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_13_TG_TABLE13_SET(x)                                (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_14 */
+#define PHY_BB_TX_GAIN_TAB_14_ADDRESS                                                         0x0000a434
+#define PHY_BB_TX_GAIN_TAB_14_OFFSET                                                          0x0000a434
+#define PHY_BB_TX_GAIN_TAB_14_TG_TABLE14_MSB                                                          31
+#define PHY_BB_TX_GAIN_TAB_14_TG_TABLE14_LSB                                                           0
+#define PHY_BB_TX_GAIN_TAB_14_TG_TABLE14_MASK                                                 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_14_TG_TABLE14_GET(x)                                (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_14_TG_TABLE14_SET(x)                                (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_15 */
+#define PHY_BB_TX_GAIN_TAB_15_ADDRESS                                                         0x0000a438
+#define PHY_BB_TX_GAIN_TAB_15_OFFSET                                                          0x0000a438
+#define PHY_BB_TX_GAIN_TAB_15_TG_TABLE15_MSB                                                          31
+#define PHY_BB_TX_GAIN_TAB_15_TG_TABLE15_LSB                                                           0
+#define PHY_BB_TX_GAIN_TAB_15_TG_TABLE15_MASK                                                 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_15_TG_TABLE15_GET(x)                                (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_15_TG_TABLE15_SET(x)                                (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_16 */
+#define PHY_BB_TX_GAIN_TAB_16_ADDRESS                                                         0x0000a43c
+#define PHY_BB_TX_GAIN_TAB_16_OFFSET                                                          0x0000a43c
+#define PHY_BB_TX_GAIN_TAB_16_TG_TABLE16_MSB                                                          31
+#define PHY_BB_TX_GAIN_TAB_16_TG_TABLE16_LSB                                                           0
+#define PHY_BB_TX_GAIN_TAB_16_TG_TABLE16_MASK                                                 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_16_TG_TABLE16_GET(x)                                (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_16_TG_TABLE16_SET(x)                                (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_17 */
+#define PHY_BB_TX_GAIN_TAB_17_ADDRESS                                                         0x0000a440
+#define PHY_BB_TX_GAIN_TAB_17_OFFSET                                                          0x0000a440
+#define PHY_BB_TX_GAIN_TAB_17_TG_TABLE17_MSB                                                          31
+#define PHY_BB_TX_GAIN_TAB_17_TG_TABLE17_LSB                                                           0
+#define PHY_BB_TX_GAIN_TAB_17_TG_TABLE17_MASK                                                 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_17_TG_TABLE17_GET(x)                                (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_17_TG_TABLE17_SET(x)                                (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_18 */
+#define PHY_BB_TX_GAIN_TAB_18_ADDRESS                                                         0x0000a444
+#define PHY_BB_TX_GAIN_TAB_18_OFFSET                                                          0x0000a444
+#define PHY_BB_TX_GAIN_TAB_18_TG_TABLE18_MSB                                                          31
+#define PHY_BB_TX_GAIN_TAB_18_TG_TABLE18_LSB                                                           0
+#define PHY_BB_TX_GAIN_TAB_18_TG_TABLE18_MASK                                                 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_18_TG_TABLE18_GET(x)                                (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_18_TG_TABLE18_SET(x)                                (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_19 */
+#define PHY_BB_TX_GAIN_TAB_19_ADDRESS                                                         0x0000a448
+#define PHY_BB_TX_GAIN_TAB_19_OFFSET                                                          0x0000a448
+#define PHY_BB_TX_GAIN_TAB_19_TG_TABLE19_MSB                                                          31
+#define PHY_BB_TX_GAIN_TAB_19_TG_TABLE19_LSB                                                           0
+#define PHY_BB_TX_GAIN_TAB_19_TG_TABLE19_MASK                                                 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_19_TG_TABLE19_GET(x)                                (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_19_TG_TABLE19_SET(x)                                (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_20 */
+#define PHY_BB_TX_GAIN_TAB_20_ADDRESS                                                         0x0000a44c
+#define PHY_BB_TX_GAIN_TAB_20_OFFSET                                                          0x0000a44c
+#define PHY_BB_TX_GAIN_TAB_20_TG_TABLE20_MSB                                                          31
+#define PHY_BB_TX_GAIN_TAB_20_TG_TABLE20_LSB                                                           0
+#define PHY_BB_TX_GAIN_TAB_20_TG_TABLE20_MASK                                                 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_20_TG_TABLE20_GET(x)                                (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_20_TG_TABLE20_SET(x)                                (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_21 */
+#define PHY_BB_TX_GAIN_TAB_21_ADDRESS                                                         0x0000a450
+#define PHY_BB_TX_GAIN_TAB_21_OFFSET                                                          0x0000a450
+#define PHY_BB_TX_GAIN_TAB_21_TG_TABLE21_MSB                                                          31
+#define PHY_BB_TX_GAIN_TAB_21_TG_TABLE21_LSB                                                           0
+#define PHY_BB_TX_GAIN_TAB_21_TG_TABLE21_MASK                                                 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_21_TG_TABLE21_GET(x)                                (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_21_TG_TABLE21_SET(x)                                (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_22 */
+#define PHY_BB_TX_GAIN_TAB_22_ADDRESS                                                         0x0000a454
+#define PHY_BB_TX_GAIN_TAB_22_OFFSET                                                          0x0000a454
+#define PHY_BB_TX_GAIN_TAB_22_TG_TABLE22_MSB                                                          31
+#define PHY_BB_TX_GAIN_TAB_22_TG_TABLE22_LSB                                                           0
+#define PHY_BB_TX_GAIN_TAB_22_TG_TABLE22_MASK                                                 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_22_TG_TABLE22_GET(x)                                (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_22_TG_TABLE22_SET(x)                                (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_23 */
+#define PHY_BB_TX_GAIN_TAB_23_ADDRESS                                                         0x0000a458
+#define PHY_BB_TX_GAIN_TAB_23_OFFSET                                                          0x0000a458
+#define PHY_BB_TX_GAIN_TAB_23_TG_TABLE23_MSB                                                          31
+#define PHY_BB_TX_GAIN_TAB_23_TG_TABLE23_LSB                                                           0
+#define PHY_BB_TX_GAIN_TAB_23_TG_TABLE23_MASK                                                 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_23_TG_TABLE23_GET(x)                                (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_23_TG_TABLE23_SET(x)                                (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_24 */
+#define PHY_BB_TX_GAIN_TAB_24_ADDRESS                                                         0x0000a45c
+#define PHY_BB_TX_GAIN_TAB_24_OFFSET                                                          0x0000a45c
+#define PHY_BB_TX_GAIN_TAB_24_TG_TABLE24_MSB                                                          31
+#define PHY_BB_TX_GAIN_TAB_24_TG_TABLE24_LSB                                                           0
+#define PHY_BB_TX_GAIN_TAB_24_TG_TABLE24_MASK                                                 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_24_TG_TABLE24_GET(x)                                (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_24_TG_TABLE24_SET(x)                                (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_25 */
+#define PHY_BB_TX_GAIN_TAB_25_ADDRESS                                                         0x0000a460
+#define PHY_BB_TX_GAIN_TAB_25_OFFSET                                                          0x0000a460
+#define PHY_BB_TX_GAIN_TAB_25_TG_TABLE25_MSB                                                          31
+#define PHY_BB_TX_GAIN_TAB_25_TG_TABLE25_LSB                                                           0
+#define PHY_BB_TX_GAIN_TAB_25_TG_TABLE25_MASK                                                 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_25_TG_TABLE25_GET(x)                                (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_25_TG_TABLE25_SET(x)                                (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_26 */
+#define PHY_BB_TX_GAIN_TAB_26_ADDRESS                                                         0x0000a464
+#define PHY_BB_TX_GAIN_TAB_26_OFFSET                                                          0x0000a464
+#define PHY_BB_TX_GAIN_TAB_26_TG_TABLE26_MSB                                                          31
+#define PHY_BB_TX_GAIN_TAB_26_TG_TABLE26_LSB                                                           0
+#define PHY_BB_TX_GAIN_TAB_26_TG_TABLE26_MASK                                                 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_26_TG_TABLE26_GET(x)                                (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_26_TG_TABLE26_SET(x)                                (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_27 */
+#define PHY_BB_TX_GAIN_TAB_27_ADDRESS                                                         0x0000a468
+#define PHY_BB_TX_GAIN_TAB_27_OFFSET                                                          0x0000a468
+#define PHY_BB_TX_GAIN_TAB_27_TG_TABLE27_MSB                                                          31
+#define PHY_BB_TX_GAIN_TAB_27_TG_TABLE27_LSB                                                           0
+#define PHY_BB_TX_GAIN_TAB_27_TG_TABLE27_MASK                                                 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_27_TG_TABLE27_GET(x)                                (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_27_TG_TABLE27_SET(x)                                (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_28 */
+#define PHY_BB_TX_GAIN_TAB_28_ADDRESS                                                         0x0000a46c
+#define PHY_BB_TX_GAIN_TAB_28_OFFSET                                                          0x0000a46c
+#define PHY_BB_TX_GAIN_TAB_28_TG_TABLE28_MSB                                                          31
+#define PHY_BB_TX_GAIN_TAB_28_TG_TABLE28_LSB                                                           0
+#define PHY_BB_TX_GAIN_TAB_28_TG_TABLE28_MASK                                                 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_28_TG_TABLE28_GET(x)                                (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_28_TG_TABLE28_SET(x)                                (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_29 */
+#define PHY_BB_TX_GAIN_TAB_29_ADDRESS                                                         0x0000a470
+#define PHY_BB_TX_GAIN_TAB_29_OFFSET                                                          0x0000a470
+#define PHY_BB_TX_GAIN_TAB_29_TG_TABLE29_MSB                                                          31
+#define PHY_BB_TX_GAIN_TAB_29_TG_TABLE29_LSB                                                           0
+#define PHY_BB_TX_GAIN_TAB_29_TG_TABLE29_MASK                                                 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_29_TG_TABLE29_GET(x)                                (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_29_TG_TABLE29_SET(x)                                (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_30 */
+#define PHY_BB_TX_GAIN_TAB_30_ADDRESS                                                         0x0000a474
+#define PHY_BB_TX_GAIN_TAB_30_OFFSET                                                          0x0000a474
+#define PHY_BB_TX_GAIN_TAB_30_TG_TABLE30_MSB                                                          31
+#define PHY_BB_TX_GAIN_TAB_30_TG_TABLE30_LSB                                                           0
+#define PHY_BB_TX_GAIN_TAB_30_TG_TABLE30_MASK                                                 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_30_TG_TABLE30_GET(x)                                (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_30_TG_TABLE30_SET(x)                                (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_31 */
+#define PHY_BB_TX_GAIN_TAB_31_ADDRESS                                                         0x0000a478
+#define PHY_BB_TX_GAIN_TAB_31_OFFSET                                                          0x0000a478
+#define PHY_BB_TX_GAIN_TAB_31_TG_TABLE31_MSB                                                          31
+#define PHY_BB_TX_GAIN_TAB_31_TG_TABLE31_LSB                                                           0
+#define PHY_BB_TX_GAIN_TAB_31_TG_TABLE31_MASK                                                 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_31_TG_TABLE31_GET(x)                                (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_31_TG_TABLE31_SET(x)                                (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_32 */
+#define PHY_BB_TX_GAIN_TAB_32_ADDRESS                                                         0x0000a47c
+#define PHY_BB_TX_GAIN_TAB_32_OFFSET                                                          0x0000a47c
+#define PHY_BB_TX_GAIN_TAB_32_TG_TABLE32_MSB                                                          31
+#define PHY_BB_TX_GAIN_TAB_32_TG_TABLE32_LSB                                                           0
+#define PHY_BB_TX_GAIN_TAB_32_TG_TABLE32_MASK                                                 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_32_TG_TABLE32_GET(x)                                (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_32_TG_TABLE32_SET(x)                                (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_1 */
+#define PHY_BB_TX_GAIN_TAB_PAL_1_ADDRESS                                                      0x0000a480
+#define PHY_BB_TX_GAIN_TAB_PAL_1_OFFSET                                                       0x0000a480
+#define PHY_BB_TX_GAIN_TAB_PAL_1_TG_TABLE1_PAL_ON_MSB                                                 31
+#define PHY_BB_TX_GAIN_TAB_PAL_1_TG_TABLE1_PAL_ON_LSB                                                  0
+#define PHY_BB_TX_GAIN_TAB_PAL_1_TG_TABLE1_PAL_ON_MASK                                        0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_1_TG_TABLE1_PAL_ON_GET(x)                       (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_1_TG_TABLE1_PAL_ON_SET(x)                       (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_2 */
+#define PHY_BB_TX_GAIN_TAB_PAL_2_ADDRESS                                                      0x0000a484
+#define PHY_BB_TX_GAIN_TAB_PAL_2_OFFSET                                                       0x0000a484
+#define PHY_BB_TX_GAIN_TAB_PAL_2_TG_TABLE2_PAL_ON_MSB                                                 31
+#define PHY_BB_TX_GAIN_TAB_PAL_2_TG_TABLE2_PAL_ON_LSB                                                  0
+#define PHY_BB_TX_GAIN_TAB_PAL_2_TG_TABLE2_PAL_ON_MASK                                        0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_2_TG_TABLE2_PAL_ON_GET(x)                       (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_2_TG_TABLE2_PAL_ON_SET(x)                       (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_3 */
+#define PHY_BB_TX_GAIN_TAB_PAL_3_ADDRESS                                                      0x0000a488
+#define PHY_BB_TX_GAIN_TAB_PAL_3_OFFSET                                                       0x0000a488
+#define PHY_BB_TX_GAIN_TAB_PAL_3_TG_TABLE3_PAL_ON_MSB                                                 31
+#define PHY_BB_TX_GAIN_TAB_PAL_3_TG_TABLE3_PAL_ON_LSB                                                  0
+#define PHY_BB_TX_GAIN_TAB_PAL_3_TG_TABLE3_PAL_ON_MASK                                        0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_3_TG_TABLE3_PAL_ON_GET(x)                       (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_3_TG_TABLE3_PAL_ON_SET(x)                       (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_4 */
+#define PHY_BB_TX_GAIN_TAB_PAL_4_ADDRESS                                                      0x0000a48c
+#define PHY_BB_TX_GAIN_TAB_PAL_4_OFFSET                                                       0x0000a48c
+#define PHY_BB_TX_GAIN_TAB_PAL_4_TG_TABLE4_PAL_ON_MSB                                                 31
+#define PHY_BB_TX_GAIN_TAB_PAL_4_TG_TABLE4_PAL_ON_LSB                                                  0
+#define PHY_BB_TX_GAIN_TAB_PAL_4_TG_TABLE4_PAL_ON_MASK                                        0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_4_TG_TABLE4_PAL_ON_GET(x)                       (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_4_TG_TABLE4_PAL_ON_SET(x)                       (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_5 */
+#define PHY_BB_TX_GAIN_TAB_PAL_5_ADDRESS                                                      0x0000a490
+#define PHY_BB_TX_GAIN_TAB_PAL_5_OFFSET                                                       0x0000a490
+#define PHY_BB_TX_GAIN_TAB_PAL_5_TG_TABLE5_PAL_ON_MSB                                                 31
+#define PHY_BB_TX_GAIN_TAB_PAL_5_TG_TABLE5_PAL_ON_LSB                                                  0
+#define PHY_BB_TX_GAIN_TAB_PAL_5_TG_TABLE5_PAL_ON_MASK                                        0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_5_TG_TABLE5_PAL_ON_GET(x)                       (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_5_TG_TABLE5_PAL_ON_SET(x)                       (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_6 */
+#define PHY_BB_TX_GAIN_TAB_PAL_6_ADDRESS                                                      0x0000a494
+#define PHY_BB_TX_GAIN_TAB_PAL_6_OFFSET                                                       0x0000a494
+#define PHY_BB_TX_GAIN_TAB_PAL_6_TG_TABLE6_PAL_ON_MSB                                                 31
+#define PHY_BB_TX_GAIN_TAB_PAL_6_TG_TABLE6_PAL_ON_LSB                                                  0
+#define PHY_BB_TX_GAIN_TAB_PAL_6_TG_TABLE6_PAL_ON_MASK                                        0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_6_TG_TABLE6_PAL_ON_GET(x)                       (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_6_TG_TABLE6_PAL_ON_SET(x)                       (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_7 */
+#define PHY_BB_TX_GAIN_TAB_PAL_7_ADDRESS                                                      0x0000a498
+#define PHY_BB_TX_GAIN_TAB_PAL_7_OFFSET                                                       0x0000a498
+#define PHY_BB_TX_GAIN_TAB_PAL_7_TG_TABLE7_PAL_ON_MSB                                                 31
+#define PHY_BB_TX_GAIN_TAB_PAL_7_TG_TABLE7_PAL_ON_LSB                                                  0
+#define PHY_BB_TX_GAIN_TAB_PAL_7_TG_TABLE7_PAL_ON_MASK                                        0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_7_TG_TABLE7_PAL_ON_GET(x)                       (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_7_TG_TABLE7_PAL_ON_SET(x)                       (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_8 */
+#define PHY_BB_TX_GAIN_TAB_PAL_8_ADDRESS                                                      0x0000a49c
+#define PHY_BB_TX_GAIN_TAB_PAL_8_OFFSET                                                       0x0000a49c
+#define PHY_BB_TX_GAIN_TAB_PAL_8_TG_TABLE8_PAL_ON_MSB                                                 31
+#define PHY_BB_TX_GAIN_TAB_PAL_8_TG_TABLE8_PAL_ON_LSB                                                  0
+#define PHY_BB_TX_GAIN_TAB_PAL_8_TG_TABLE8_PAL_ON_MASK                                        0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_8_TG_TABLE8_PAL_ON_GET(x)                       (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_8_TG_TABLE8_PAL_ON_SET(x)                       (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_9 */
+#define PHY_BB_TX_GAIN_TAB_PAL_9_ADDRESS                                                      0x0000a4a0
+#define PHY_BB_TX_GAIN_TAB_PAL_9_OFFSET                                                       0x0000a4a0
+#define PHY_BB_TX_GAIN_TAB_PAL_9_TG_TABLE9_PAL_ON_MSB                                                 31
+#define PHY_BB_TX_GAIN_TAB_PAL_9_TG_TABLE9_PAL_ON_LSB                                                  0
+#define PHY_BB_TX_GAIN_TAB_PAL_9_TG_TABLE9_PAL_ON_MASK                                        0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_9_TG_TABLE9_PAL_ON_GET(x)                       (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_9_TG_TABLE9_PAL_ON_SET(x)                       (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_10 */
+#define PHY_BB_TX_GAIN_TAB_PAL_10_ADDRESS                                                     0x0000a4a4
+#define PHY_BB_TX_GAIN_TAB_PAL_10_OFFSET                                                      0x0000a4a4
+#define PHY_BB_TX_GAIN_TAB_PAL_10_TG_TABLE10_PAL_ON_MSB                                               31
+#define PHY_BB_TX_GAIN_TAB_PAL_10_TG_TABLE10_PAL_ON_LSB                                                0
+#define PHY_BB_TX_GAIN_TAB_PAL_10_TG_TABLE10_PAL_ON_MASK                                      0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_10_TG_TABLE10_PAL_ON_GET(x)                     (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_10_TG_TABLE10_PAL_ON_SET(x)                     (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_11 */
+#define PHY_BB_TX_GAIN_TAB_PAL_11_ADDRESS                                                     0x0000a4a8
+#define PHY_BB_TX_GAIN_TAB_PAL_11_OFFSET                                                      0x0000a4a8
+#define PHY_BB_TX_GAIN_TAB_PAL_11_TG_TABLE11_PAL_ON_MSB                                               31
+#define PHY_BB_TX_GAIN_TAB_PAL_11_TG_TABLE11_PAL_ON_LSB                                                0
+#define PHY_BB_TX_GAIN_TAB_PAL_11_TG_TABLE11_PAL_ON_MASK                                      0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_11_TG_TABLE11_PAL_ON_GET(x)                     (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_11_TG_TABLE11_PAL_ON_SET(x)                     (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_12 */
+#define PHY_BB_TX_GAIN_TAB_PAL_12_ADDRESS                                                     0x0000a4ac
+#define PHY_BB_TX_GAIN_TAB_PAL_12_OFFSET                                                      0x0000a4ac
+#define PHY_BB_TX_GAIN_TAB_PAL_12_TG_TABLE12_PAL_ON_MSB                                               31
+#define PHY_BB_TX_GAIN_TAB_PAL_12_TG_TABLE12_PAL_ON_LSB                                                0
+#define PHY_BB_TX_GAIN_TAB_PAL_12_TG_TABLE12_PAL_ON_MASK                                      0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_12_TG_TABLE12_PAL_ON_GET(x)                     (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_12_TG_TABLE12_PAL_ON_SET(x)                     (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_13 */
+#define PHY_BB_TX_GAIN_TAB_PAL_13_ADDRESS                                                     0x0000a4b0
+#define PHY_BB_TX_GAIN_TAB_PAL_13_OFFSET                                                      0x0000a4b0
+#define PHY_BB_TX_GAIN_TAB_PAL_13_TG_TABLE13_PAL_ON_MSB                                               31
+#define PHY_BB_TX_GAIN_TAB_PAL_13_TG_TABLE13_PAL_ON_LSB                                                0
+#define PHY_BB_TX_GAIN_TAB_PAL_13_TG_TABLE13_PAL_ON_MASK                                      0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_13_TG_TABLE13_PAL_ON_GET(x)                     (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_13_TG_TABLE13_PAL_ON_SET(x)                     (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_14 */
+#define PHY_BB_TX_GAIN_TAB_PAL_14_ADDRESS                                                     0x0000a4b4
+#define PHY_BB_TX_GAIN_TAB_PAL_14_OFFSET                                                      0x0000a4b4
+#define PHY_BB_TX_GAIN_TAB_PAL_14_TG_TABLE14_PAL_ON_MSB                                               31
+#define PHY_BB_TX_GAIN_TAB_PAL_14_TG_TABLE14_PAL_ON_LSB                                                0
+#define PHY_BB_TX_GAIN_TAB_PAL_14_TG_TABLE14_PAL_ON_MASK                                      0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_14_TG_TABLE14_PAL_ON_GET(x)                     (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_14_TG_TABLE14_PAL_ON_SET(x)                     (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_15 */
+#define PHY_BB_TX_GAIN_TAB_PAL_15_ADDRESS                                                     0x0000a4b8
+#define PHY_BB_TX_GAIN_TAB_PAL_15_OFFSET                                                      0x0000a4b8
+#define PHY_BB_TX_GAIN_TAB_PAL_15_TG_TABLE15_PAL_ON_MSB                                               31
+#define PHY_BB_TX_GAIN_TAB_PAL_15_TG_TABLE15_PAL_ON_LSB                                                0
+#define PHY_BB_TX_GAIN_TAB_PAL_15_TG_TABLE15_PAL_ON_MASK                                      0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_15_TG_TABLE15_PAL_ON_GET(x)                     (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_15_TG_TABLE15_PAL_ON_SET(x)                     (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_16 */
+#define PHY_BB_TX_GAIN_TAB_PAL_16_ADDRESS                                                     0x0000a4bc
+#define PHY_BB_TX_GAIN_TAB_PAL_16_OFFSET                                                      0x0000a4bc
+#define PHY_BB_TX_GAIN_TAB_PAL_16_TG_TABLE16_PAL_ON_MSB                                               31
+#define PHY_BB_TX_GAIN_TAB_PAL_16_TG_TABLE16_PAL_ON_LSB                                                0
+#define PHY_BB_TX_GAIN_TAB_PAL_16_TG_TABLE16_PAL_ON_MASK                                      0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_16_TG_TABLE16_PAL_ON_GET(x)                     (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_16_TG_TABLE16_PAL_ON_SET(x)                     (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_17 */
+#define PHY_BB_TX_GAIN_TAB_PAL_17_ADDRESS                                                     0x0000a4c0
+#define PHY_BB_TX_GAIN_TAB_PAL_17_OFFSET                                                      0x0000a4c0
+#define PHY_BB_TX_GAIN_TAB_PAL_17_TG_TABLE17_PAL_ON_MSB                                               31
+#define PHY_BB_TX_GAIN_TAB_PAL_17_TG_TABLE17_PAL_ON_LSB                                                0
+#define PHY_BB_TX_GAIN_TAB_PAL_17_TG_TABLE17_PAL_ON_MASK                                      0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_17_TG_TABLE17_PAL_ON_GET(x)                     (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_17_TG_TABLE17_PAL_ON_SET(x)                     (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_18 */
+#define PHY_BB_TX_GAIN_TAB_PAL_18_ADDRESS                                                     0x0000a4c4
+#define PHY_BB_TX_GAIN_TAB_PAL_18_OFFSET                                                      0x0000a4c4
+#define PHY_BB_TX_GAIN_TAB_PAL_18_TG_TABLE18_PAL_ON_MSB                                               31
+#define PHY_BB_TX_GAIN_TAB_PAL_18_TG_TABLE18_PAL_ON_LSB                                                0
+#define PHY_BB_TX_GAIN_TAB_PAL_18_TG_TABLE18_PAL_ON_MASK                                      0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_18_TG_TABLE18_PAL_ON_GET(x)                     (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_18_TG_TABLE18_PAL_ON_SET(x)                     (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_19 */
+#define PHY_BB_TX_GAIN_TAB_PAL_19_ADDRESS                                                     0x0000a4c8
+#define PHY_BB_TX_GAIN_TAB_PAL_19_OFFSET                                                      0x0000a4c8
+#define PHY_BB_TX_GAIN_TAB_PAL_19_TG_TABLE19_PAL_ON_MSB                                               31
+#define PHY_BB_TX_GAIN_TAB_PAL_19_TG_TABLE19_PAL_ON_LSB                                                0
+#define PHY_BB_TX_GAIN_TAB_PAL_19_TG_TABLE19_PAL_ON_MASK                                      0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_19_TG_TABLE19_PAL_ON_GET(x)                     (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_19_TG_TABLE19_PAL_ON_SET(x)                     (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_20 */
+#define PHY_BB_TX_GAIN_TAB_PAL_20_ADDRESS                                                     0x0000a4cc
+#define PHY_BB_TX_GAIN_TAB_PAL_20_OFFSET                                                      0x0000a4cc
+#define PHY_BB_TX_GAIN_TAB_PAL_20_TG_TABLE20_PAL_ON_MSB                                               31
+#define PHY_BB_TX_GAIN_TAB_PAL_20_TG_TABLE20_PAL_ON_LSB                                                0
+#define PHY_BB_TX_GAIN_TAB_PAL_20_TG_TABLE20_PAL_ON_MASK                                      0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_20_TG_TABLE20_PAL_ON_GET(x)                     (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_20_TG_TABLE20_PAL_ON_SET(x)                     (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_21 */
+#define PHY_BB_TX_GAIN_TAB_PAL_21_ADDRESS                                                     0x0000a4d0
+#define PHY_BB_TX_GAIN_TAB_PAL_21_OFFSET                                                      0x0000a4d0
+#define PHY_BB_TX_GAIN_TAB_PAL_21_TG_TABLE21_PAL_ON_MSB                                               31
+#define PHY_BB_TX_GAIN_TAB_PAL_21_TG_TABLE21_PAL_ON_LSB                                                0
+#define PHY_BB_TX_GAIN_TAB_PAL_21_TG_TABLE21_PAL_ON_MASK                                      0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_21_TG_TABLE21_PAL_ON_GET(x)                     (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_21_TG_TABLE21_PAL_ON_SET(x)                     (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_22 */
+#define PHY_BB_TX_GAIN_TAB_PAL_22_ADDRESS                                                     0x0000a4d4
+#define PHY_BB_TX_GAIN_TAB_PAL_22_OFFSET                                                      0x0000a4d4
+#define PHY_BB_TX_GAIN_TAB_PAL_22_TG_TABLE22_PAL_ON_MSB                                               31
+#define PHY_BB_TX_GAIN_TAB_PAL_22_TG_TABLE22_PAL_ON_LSB                                                0
+#define PHY_BB_TX_GAIN_TAB_PAL_22_TG_TABLE22_PAL_ON_MASK                                      0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_22_TG_TABLE22_PAL_ON_GET(x)                     (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_22_TG_TABLE22_PAL_ON_SET(x)                     (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_23 */
+#define PHY_BB_TX_GAIN_TAB_PAL_23_ADDRESS                                                     0x0000a4d8
+#define PHY_BB_TX_GAIN_TAB_PAL_23_OFFSET                                                      0x0000a4d8
+#define PHY_BB_TX_GAIN_TAB_PAL_23_TG_TABLE23_PAL_ON_MSB                                               31
+#define PHY_BB_TX_GAIN_TAB_PAL_23_TG_TABLE23_PAL_ON_LSB                                                0
+#define PHY_BB_TX_GAIN_TAB_PAL_23_TG_TABLE23_PAL_ON_MASK                                      0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_23_TG_TABLE23_PAL_ON_GET(x)                     (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_23_TG_TABLE23_PAL_ON_SET(x)                     (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_24 */
+#define PHY_BB_TX_GAIN_TAB_PAL_24_ADDRESS                                                     0x0000a4dc
+#define PHY_BB_TX_GAIN_TAB_PAL_24_OFFSET                                                      0x0000a4dc
+#define PHY_BB_TX_GAIN_TAB_PAL_24_TG_TABLE24_PAL_ON_MSB                                               31
+#define PHY_BB_TX_GAIN_TAB_PAL_24_TG_TABLE24_PAL_ON_LSB                                                0
+#define PHY_BB_TX_GAIN_TAB_PAL_24_TG_TABLE24_PAL_ON_MASK                                      0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_24_TG_TABLE24_PAL_ON_GET(x)                     (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_24_TG_TABLE24_PAL_ON_SET(x)                     (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_25 */
+#define PHY_BB_TX_GAIN_TAB_PAL_25_ADDRESS                                                     0x0000a4e0
+#define PHY_BB_TX_GAIN_TAB_PAL_25_OFFSET                                                      0x0000a4e0
+#define PHY_BB_TX_GAIN_TAB_PAL_25_TG_TABLE25_PAL_ON_MSB                                               31
+#define PHY_BB_TX_GAIN_TAB_PAL_25_TG_TABLE25_PAL_ON_LSB                                                0
+#define PHY_BB_TX_GAIN_TAB_PAL_25_TG_TABLE25_PAL_ON_MASK                                      0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_25_TG_TABLE25_PAL_ON_GET(x)                     (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_25_TG_TABLE25_PAL_ON_SET(x)                     (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_26 */
+#define PHY_BB_TX_GAIN_TAB_PAL_26_ADDRESS                                                     0x0000a4e4
+#define PHY_BB_TX_GAIN_TAB_PAL_26_OFFSET                                                      0x0000a4e4
+#define PHY_BB_TX_GAIN_TAB_PAL_26_TG_TABLE26_PAL_ON_MSB                                               31
+#define PHY_BB_TX_GAIN_TAB_PAL_26_TG_TABLE26_PAL_ON_LSB                                                0
+#define PHY_BB_TX_GAIN_TAB_PAL_26_TG_TABLE26_PAL_ON_MASK                                      0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_26_TG_TABLE26_PAL_ON_GET(x)                     (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_26_TG_TABLE26_PAL_ON_SET(x)                     (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_27 */
+#define PHY_BB_TX_GAIN_TAB_PAL_27_ADDRESS                                                     0x0000a4e8
+#define PHY_BB_TX_GAIN_TAB_PAL_27_OFFSET                                                      0x0000a4e8
+#define PHY_BB_TX_GAIN_TAB_PAL_27_TG_TABLE27_PAL_ON_MSB                                               31
+#define PHY_BB_TX_GAIN_TAB_PAL_27_TG_TABLE27_PAL_ON_LSB                                                0
+#define PHY_BB_TX_GAIN_TAB_PAL_27_TG_TABLE27_PAL_ON_MASK                                      0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_27_TG_TABLE27_PAL_ON_GET(x)                     (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_27_TG_TABLE27_PAL_ON_SET(x)                     (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_28 */
+#define PHY_BB_TX_GAIN_TAB_PAL_28_ADDRESS                                                     0x0000a4ec
+#define PHY_BB_TX_GAIN_TAB_PAL_28_OFFSET                                                      0x0000a4ec
+#define PHY_BB_TX_GAIN_TAB_PAL_28_TG_TABLE28_PAL_ON_MSB                                               31
+#define PHY_BB_TX_GAIN_TAB_PAL_28_TG_TABLE28_PAL_ON_LSB                                                0
+#define PHY_BB_TX_GAIN_TAB_PAL_28_TG_TABLE28_PAL_ON_MASK                                      0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_28_TG_TABLE28_PAL_ON_GET(x)                     (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_28_TG_TABLE28_PAL_ON_SET(x)                     (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_29 */
+#define PHY_BB_TX_GAIN_TAB_PAL_29_ADDRESS                                                     0x0000a4f0
+#define PHY_BB_TX_GAIN_TAB_PAL_29_OFFSET                                                      0x0000a4f0
+#define PHY_BB_TX_GAIN_TAB_PAL_29_TG_TABLE29_PAL_ON_MSB                                               31
+#define PHY_BB_TX_GAIN_TAB_PAL_29_TG_TABLE29_PAL_ON_LSB                                                0
+#define PHY_BB_TX_GAIN_TAB_PAL_29_TG_TABLE29_PAL_ON_MASK                                      0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_29_TG_TABLE29_PAL_ON_GET(x)                     (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_29_TG_TABLE29_PAL_ON_SET(x)                     (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_30 */
+#define PHY_BB_TX_GAIN_TAB_PAL_30_ADDRESS                                                     0x0000a4f4
+#define PHY_BB_TX_GAIN_TAB_PAL_30_OFFSET                                                      0x0000a4f4
+#define PHY_BB_TX_GAIN_TAB_PAL_30_TG_TABLE30_PAL_ON_MSB                                               31
+#define PHY_BB_TX_GAIN_TAB_PAL_30_TG_TABLE30_PAL_ON_LSB                                                0
+#define PHY_BB_TX_GAIN_TAB_PAL_30_TG_TABLE30_PAL_ON_MASK                                      0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_30_TG_TABLE30_PAL_ON_GET(x)                     (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_30_TG_TABLE30_PAL_ON_SET(x)                     (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_31 */
+#define PHY_BB_TX_GAIN_TAB_PAL_31_ADDRESS                                                     0x0000a4f8
+#define PHY_BB_TX_GAIN_TAB_PAL_31_OFFSET                                                      0x0000a4f8
+#define PHY_BB_TX_GAIN_TAB_PAL_31_TG_TABLE31_PAL_ON_MSB                                               31
+#define PHY_BB_TX_GAIN_TAB_PAL_31_TG_TABLE31_PAL_ON_LSB                                                0
+#define PHY_BB_TX_GAIN_TAB_PAL_31_TG_TABLE31_PAL_ON_MASK                                      0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_31_TG_TABLE31_PAL_ON_GET(x)                     (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_31_TG_TABLE31_PAL_ON_SET(x)                     (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_32 */
+#define PHY_BB_TX_GAIN_TAB_PAL_32_ADDRESS                                                     0x0000a4fc
+#define PHY_BB_TX_GAIN_TAB_PAL_32_OFFSET                                                      0x0000a4fc
+#define PHY_BB_TX_GAIN_TAB_PAL_32_TG_TABLE32_PAL_ON_MSB                                               31
+#define PHY_BB_TX_GAIN_TAB_PAL_32_TG_TABLE32_PAL_ON_LSB                                                0
+#define PHY_BB_TX_GAIN_TAB_PAL_32_TG_TABLE32_PAL_ON_MASK                                      0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_32_TG_TABLE32_PAL_ON_GET(x)                     (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_32_TG_TABLE32_PAL_ON_SET(x)                     (((x) << 0) & 0xffffffff)
+
+/* macros for BB_caltx_gain_set_0 */
+#define PHY_BB_CALTX_GAIN_SET_0_ADDRESS                                                       0x0000a518
+#define PHY_BB_CALTX_GAIN_SET_0_OFFSET                                                        0x0000a518
+#define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_0_MSB                                                  13
+#define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_0_LSB                                                   0
+#define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_0_MASK                                         0x00003fff
+#define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_0_GET(x)                        (((x) & 0x00003fff) >> 0)
+#define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_0_SET(x)                        (((x) << 0) & 0x00003fff)
+#define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_1_MSB                                                  27
+#define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_1_LSB                                                  14
+#define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_1_MASK                                         0x0fffc000
+#define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_1_GET(x)                       (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_1_SET(x)                       (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_caltx_gain_set_2 */
+#define PHY_BB_CALTX_GAIN_SET_2_ADDRESS                                                       0x0000a51c
+#define PHY_BB_CALTX_GAIN_SET_2_OFFSET                                                        0x0000a51c
+#define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_2_MSB                                                  13
+#define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_2_LSB                                                   0
+#define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_2_MASK                                         0x00003fff
+#define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_2_GET(x)                        (((x) & 0x00003fff) >> 0)
+#define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_2_SET(x)                        (((x) << 0) & 0x00003fff)
+#define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_3_MSB                                                  27
+#define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_3_LSB                                                  14
+#define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_3_MASK                                         0x0fffc000
+#define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_3_GET(x)                       (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_3_SET(x)                       (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_caltx_gain_set_4 */
+#define PHY_BB_CALTX_GAIN_SET_4_ADDRESS                                                       0x0000a520
+#define PHY_BB_CALTX_GAIN_SET_4_OFFSET                                                        0x0000a520
+#define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_4_MSB                                                  13
+#define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_4_LSB                                                   0
+#define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_4_MASK                                         0x00003fff
+#define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_4_GET(x)                        (((x) & 0x00003fff) >> 0)
+#define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_4_SET(x)                        (((x) << 0) & 0x00003fff)
+#define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_5_MSB                                                  27
+#define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_5_LSB                                                  14
+#define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_5_MASK                                         0x0fffc000
+#define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_5_GET(x)                       (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_5_SET(x)                       (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_caltx_gain_set_6 */
+#define PHY_BB_CALTX_GAIN_SET_6_ADDRESS                                                       0x0000a524
+#define PHY_BB_CALTX_GAIN_SET_6_OFFSET                                                        0x0000a524
+#define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_6_MSB                                                  13
+#define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_6_LSB                                                   0
+#define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_6_MASK                                         0x00003fff
+#define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_6_GET(x)                        (((x) & 0x00003fff) >> 0)
+#define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_6_SET(x)                        (((x) << 0) & 0x00003fff)
+#define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_7_MSB                                                  27
+#define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_7_LSB                                                  14
+#define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_7_MASK                                         0x0fffc000
+#define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_7_GET(x)                       (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_7_SET(x)                       (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_caltx_gain_set_8 */
+#define PHY_BB_CALTX_GAIN_SET_8_ADDRESS                                                       0x0000a528
+#define PHY_BB_CALTX_GAIN_SET_8_OFFSET                                                        0x0000a528
+#define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_8_MSB                                                  13
+#define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_8_LSB                                                   0
+#define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_8_MASK                                         0x00003fff
+#define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_8_GET(x)                        (((x) & 0x00003fff) >> 0)
+#define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_8_SET(x)                        (((x) << 0) & 0x00003fff)
+#define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_9_MSB                                                  27
+#define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_9_LSB                                                  14
+#define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_9_MASK                                         0x0fffc000
+#define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_9_GET(x)                       (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_9_SET(x)                       (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_caltx_gain_set_10 */
+#define PHY_BB_CALTX_GAIN_SET_10_ADDRESS                                                      0x0000a52c
+#define PHY_BB_CALTX_GAIN_SET_10_OFFSET                                                       0x0000a52c
+#define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_10_MSB                                                13
+#define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_10_LSB                                                 0
+#define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_10_MASK                                       0x00003fff
+#define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_10_GET(x)                      (((x) & 0x00003fff) >> 0)
+#define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_10_SET(x)                      (((x) << 0) & 0x00003fff)
+#define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_11_MSB                                                27
+#define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_11_LSB                                                14
+#define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_11_MASK                                       0x0fffc000
+#define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_11_GET(x)                     (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_11_SET(x)                     (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_caltx_gain_set_12 */
+#define PHY_BB_CALTX_GAIN_SET_12_ADDRESS                                                      0x0000a530
+#define PHY_BB_CALTX_GAIN_SET_12_OFFSET                                                       0x0000a530
+#define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_12_MSB                                                13
+#define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_12_LSB                                                 0
+#define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_12_MASK                                       0x00003fff
+#define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_12_GET(x)                      (((x) & 0x00003fff) >> 0)
+#define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_12_SET(x)                      (((x) << 0) & 0x00003fff)
+#define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_13_MSB                                                27
+#define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_13_LSB                                                14
+#define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_13_MASK                                       0x0fffc000
+#define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_13_GET(x)                     (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_13_SET(x)                     (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_caltx_gain_set_14 */
+#define PHY_BB_CALTX_GAIN_SET_14_ADDRESS                                                      0x0000a534
+#define PHY_BB_CALTX_GAIN_SET_14_OFFSET                                                       0x0000a534
+#define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_14_MSB                                                13
+#define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_14_LSB                                                 0
+#define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_14_MASK                                       0x00003fff
+#define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_14_GET(x)                      (((x) & 0x00003fff) >> 0)
+#define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_14_SET(x)                      (((x) << 0) & 0x00003fff)
+#define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_15_MSB                                                27
+#define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_15_LSB                                                14
+#define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_15_MASK                                       0x0fffc000
+#define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_15_GET(x)                     (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_15_SET(x)                     (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_caltx_gain_set_16 */
+#define PHY_BB_CALTX_GAIN_SET_16_ADDRESS                                                      0x0000a538
+#define PHY_BB_CALTX_GAIN_SET_16_OFFSET                                                       0x0000a538
+#define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_16_MSB                                                13
+#define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_16_LSB                                                 0
+#define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_16_MASK                                       0x00003fff
+#define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_16_GET(x)                      (((x) & 0x00003fff) >> 0)
+#define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_16_SET(x)                      (((x) << 0) & 0x00003fff)
+#define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_17_MSB                                                27
+#define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_17_LSB                                                14
+#define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_17_MASK                                       0x0fffc000
+#define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_17_GET(x)                     (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_17_SET(x)                     (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_caltx_gain_set_18 */
+#define PHY_BB_CALTX_GAIN_SET_18_ADDRESS                                                      0x0000a53c
+#define PHY_BB_CALTX_GAIN_SET_18_OFFSET                                                       0x0000a53c
+#define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_18_MSB                                                13
+#define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_18_LSB                                                 0
+#define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_18_MASK                                       0x00003fff
+#define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_18_GET(x)                      (((x) & 0x00003fff) >> 0)
+#define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_18_SET(x)                      (((x) << 0) & 0x00003fff)
+#define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_19_MSB                                                27
+#define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_19_LSB                                                14
+#define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_19_MASK                                       0x0fffc000
+#define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_19_GET(x)                     (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_19_SET(x)                     (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_caltx_gain_set_20 */
+#define PHY_BB_CALTX_GAIN_SET_20_ADDRESS                                                      0x0000a540
+#define PHY_BB_CALTX_GAIN_SET_20_OFFSET                                                       0x0000a540
+#define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_20_MSB                                                13
+#define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_20_LSB                                                 0
+#define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_20_MASK                                       0x00003fff
+#define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_20_GET(x)                      (((x) & 0x00003fff) >> 0)
+#define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_20_SET(x)                      (((x) << 0) & 0x00003fff)
+#define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_21_MSB                                                27
+#define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_21_LSB                                                14
+#define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_21_MASK                                       0x0fffc000
+#define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_21_GET(x)                     (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_21_SET(x)                     (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_caltx_gain_set_22 */
+#define PHY_BB_CALTX_GAIN_SET_22_ADDRESS                                                      0x0000a544
+#define PHY_BB_CALTX_GAIN_SET_22_OFFSET                                                       0x0000a544
+#define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_22_MSB                                                13
+#define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_22_LSB                                                 0
+#define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_22_MASK                                       0x00003fff
+#define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_22_GET(x)                      (((x) & 0x00003fff) >> 0)
+#define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_22_SET(x)                      (((x) << 0) & 0x00003fff)
+#define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_23_MSB                                                27
+#define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_23_LSB                                                14
+#define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_23_MASK                                       0x0fffc000
+#define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_23_GET(x)                     (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_23_SET(x)                     (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_caltx_gain_set_24 */
+#define PHY_BB_CALTX_GAIN_SET_24_ADDRESS                                                      0x0000a548
+#define PHY_BB_CALTX_GAIN_SET_24_OFFSET                                                       0x0000a548
+#define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_24_MSB                                                13
+#define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_24_LSB                                                 0
+#define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_24_MASK                                       0x00003fff
+#define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_24_GET(x)                      (((x) & 0x00003fff) >> 0)
+#define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_24_SET(x)                      (((x) << 0) & 0x00003fff)
+#define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_25_MSB                                                27
+#define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_25_LSB                                                14
+#define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_25_MASK                                       0x0fffc000
+#define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_25_GET(x)                     (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_25_SET(x)                     (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_caltx_gain_set_26 */
+#define PHY_BB_CALTX_GAIN_SET_26_ADDRESS                                                      0x0000a54c
+#define PHY_BB_CALTX_GAIN_SET_26_OFFSET                                                       0x0000a54c
+#define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_26_MSB                                                13
+#define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_26_LSB                                                 0
+#define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_26_MASK                                       0x00003fff
+#define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_26_GET(x)                      (((x) & 0x00003fff) >> 0)
+#define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_26_SET(x)                      (((x) << 0) & 0x00003fff)
+#define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_27_MSB                                                27
+#define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_27_LSB                                                14
+#define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_27_MASK                                       0x0fffc000
+#define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_27_GET(x)                     (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_27_SET(x)                     (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_caltx_gain_set_28 */
+#define PHY_BB_CALTX_GAIN_SET_28_ADDRESS                                                      0x0000a550
+#define PHY_BB_CALTX_GAIN_SET_28_OFFSET                                                       0x0000a550
+#define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_28_MSB                                                13
+#define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_28_LSB                                                 0
+#define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_28_MASK                                       0x00003fff
+#define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_28_GET(x)                      (((x) & 0x00003fff) >> 0)
+#define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_28_SET(x)                      (((x) << 0) & 0x00003fff)
+#define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_29_MSB                                                27
+#define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_29_LSB                                                14
+#define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_29_MASK                                       0x0fffc000
+#define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_29_GET(x)                     (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_29_SET(x)                     (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_caltx_gain_set_30 */
+#define PHY_BB_CALTX_GAIN_SET_30_ADDRESS                                                      0x0000a554
+#define PHY_BB_CALTX_GAIN_SET_30_OFFSET                                                       0x0000a554
+#define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_30_MSB                                                13
+#define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_30_LSB                                                 0
+#define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_30_MASK                                       0x00003fff
+#define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_30_GET(x)                      (((x) & 0x00003fff) >> 0)
+#define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_30_SET(x)                      (((x) << 0) & 0x00003fff)
+#define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_31_MSB                                                27
+#define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_31_LSB                                                14
+#define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_31_MASK                                       0x0fffc000
+#define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_31_GET(x)                     (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_31_SET(x)                     (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_txiqcal_meas_b0 */
+#define PHY_BB_TXIQCAL_MEAS_B0_ADDRESS                                                        0x0000a558
+#define PHY_BB_TXIQCAL_MEAS_B0_OFFSET                                                         0x0000a558
+#define PHY_BB_TXIQCAL_MEAS_B0_TXIQC_MEAS_DATA0_0_MSB                                                 11
+#define PHY_BB_TXIQCAL_MEAS_B0_TXIQC_MEAS_DATA0_0_LSB                                                  0
+#define PHY_BB_TXIQCAL_MEAS_B0_TXIQC_MEAS_DATA0_0_MASK                                        0x00000fff
+#define PHY_BB_TXIQCAL_MEAS_B0_TXIQC_MEAS_DATA0_0_GET(x)                       (((x) & 0x00000fff) >> 0)
+#define PHY_BB_TXIQCAL_MEAS_B0_TXIQC_MEAS_DATA1_0_MSB                                                 23
+#define PHY_BB_TXIQCAL_MEAS_B0_TXIQC_MEAS_DATA1_0_LSB                                                 12
+#define PHY_BB_TXIQCAL_MEAS_B0_TXIQC_MEAS_DATA1_0_MASK                                        0x00fff000
+#define PHY_BB_TXIQCAL_MEAS_B0_TXIQC_MEAS_DATA1_0_GET(x)                      (((x) & 0x00fff000) >> 12)
+
+/* macros for BB_txiqcal_start */
+#define PHY_BB_TXIQCAL_START_ADDRESS                                                          0x0000a6d8
+#define PHY_BB_TXIQCAL_START_OFFSET                                                           0x0000a6d8
+#define PHY_BB_TXIQCAL_START_DO_TX_IQCAL_MSB                                                           0
+#define PHY_BB_TXIQCAL_START_DO_TX_IQCAL_LSB                                                           0
+#define PHY_BB_TXIQCAL_START_DO_TX_IQCAL_MASK                                                 0x00000001
+#define PHY_BB_TXIQCAL_START_DO_TX_IQCAL_GET(x)                                (((x) & 0x00000001) >> 0)
+#define PHY_BB_TXIQCAL_START_DO_TX_IQCAL_SET(x)                                (((x) << 0) & 0x00000001)
+
+/* macros for BB_txiqcal_control_0 */
+#define PHY_BB_TXIQCAL_CONTROL_0_ADDRESS                                                      0x0000a6dc
+#define PHY_BB_TXIQCAL_CONTROL_0_OFFSET                                                       0x0000a6dc
+#define PHY_BB_TXIQCAL_CONTROL_0_IQC_TX_TABLE_SEL_MSB                                                  0
+#define PHY_BB_TXIQCAL_CONTROL_0_IQC_TX_TABLE_SEL_LSB                                                  0
+#define PHY_BB_TXIQCAL_CONTROL_0_IQC_TX_TABLE_SEL_MASK                                        0x00000001
+#define PHY_BB_TXIQCAL_CONTROL_0_IQC_TX_TABLE_SEL_GET(x)                       (((x) & 0x00000001) >> 0)
+#define PHY_BB_TXIQCAL_CONTROL_0_IQC_TX_TABLE_SEL_SET(x)                       (((x) << 0) & 0x00000001)
+#define PHY_BB_TXIQCAL_CONTROL_0_BASE_TX_TONE_DB_MSB                                                   6
+#define PHY_BB_TXIQCAL_CONTROL_0_BASE_TX_TONE_DB_LSB                                                   1
+#define PHY_BB_TXIQCAL_CONTROL_0_BASE_TX_TONE_DB_MASK                                         0x0000007e
+#define PHY_BB_TXIQCAL_CONTROL_0_BASE_TX_TONE_DB_GET(x)                        (((x) & 0x0000007e) >> 1)
+#define PHY_BB_TXIQCAL_CONTROL_0_BASE_TX_TONE_DB_SET(x)                        (((x) << 1) & 0x0000007e)
+#define PHY_BB_TXIQCAL_CONTROL_0_MAX_TX_TONE_GAIN_MSB                                                 12
+#define PHY_BB_TXIQCAL_CONTROL_0_MAX_TX_TONE_GAIN_LSB                                                  7
+#define PHY_BB_TXIQCAL_CONTROL_0_MAX_TX_TONE_GAIN_MASK                                        0x00001f80
+#define PHY_BB_TXIQCAL_CONTROL_0_MAX_TX_TONE_GAIN_GET(x)                       (((x) & 0x00001f80) >> 7)
+#define PHY_BB_TXIQCAL_CONTROL_0_MAX_TX_TONE_GAIN_SET(x)                       (((x) << 7) & 0x00001f80)
+#define PHY_BB_TXIQCAL_CONTROL_0_MIN_TX_TONE_GAIN_MSB                                                 18
+#define PHY_BB_TXIQCAL_CONTROL_0_MIN_TX_TONE_GAIN_LSB                                                 13
+#define PHY_BB_TXIQCAL_CONTROL_0_MIN_TX_TONE_GAIN_MASK                                        0x0007e000
+#define PHY_BB_TXIQCAL_CONTROL_0_MIN_TX_TONE_GAIN_GET(x)                      (((x) & 0x0007e000) >> 13)
+#define PHY_BB_TXIQCAL_CONTROL_0_MIN_TX_TONE_GAIN_SET(x)                      (((x) << 13) & 0x0007e000)
+#define PHY_BB_TXIQCAL_CONTROL_0_CALTXSHIFT_DELAY_MSB                                                 22
+#define PHY_BB_TXIQCAL_CONTROL_0_CALTXSHIFT_DELAY_LSB                                                 19
+#define PHY_BB_TXIQCAL_CONTROL_0_CALTXSHIFT_DELAY_MASK                                        0x00780000
+#define PHY_BB_TXIQCAL_CONTROL_0_CALTXSHIFT_DELAY_GET(x)                      (((x) & 0x00780000) >> 19)
+#define PHY_BB_TXIQCAL_CONTROL_0_CALTXSHIFT_DELAY_SET(x)                      (((x) << 19) & 0x00780000)
+#define PHY_BB_TXIQCAL_CONTROL_0_LOOPBACK_DELAY_MSB                                                   29
+#define PHY_BB_TXIQCAL_CONTROL_0_LOOPBACK_DELAY_LSB                                                   23
+#define PHY_BB_TXIQCAL_CONTROL_0_LOOPBACK_DELAY_MASK                                          0x3f800000
+#define PHY_BB_TXIQCAL_CONTROL_0_LOOPBACK_DELAY_GET(x)                        (((x) & 0x3f800000) >> 23)
+#define PHY_BB_TXIQCAL_CONTROL_0_LOOPBACK_DELAY_SET(x)                        (((x) << 23) & 0x3f800000)
+
+/* macros for BB_txiqcal_control_1 */
+#define PHY_BB_TXIQCAL_CONTROL_1_ADDRESS                                                      0x0000a6e0
+#define PHY_BB_TXIQCAL_CONTROL_1_OFFSET                                                       0x0000a6e0
+#define PHY_BB_TXIQCAL_CONTROL_1_RX_INIT_GAIN_DB_MSB                                                   5
+#define PHY_BB_TXIQCAL_CONTROL_1_RX_INIT_GAIN_DB_LSB                                                   0
+#define PHY_BB_TXIQCAL_CONTROL_1_RX_INIT_GAIN_DB_MASK                                         0x0000003f
+#define PHY_BB_TXIQCAL_CONTROL_1_RX_INIT_GAIN_DB_GET(x)                        (((x) & 0x0000003f) >> 0)
+#define PHY_BB_TXIQCAL_CONTROL_1_RX_INIT_GAIN_DB_SET(x)                        (((x) << 0) & 0x0000003f)
+#define PHY_BB_TXIQCAL_CONTROL_1_MAX_RX_GAIN_DB_MSB                                                   11
+#define PHY_BB_TXIQCAL_CONTROL_1_MAX_RX_GAIN_DB_LSB                                                    6
+#define PHY_BB_TXIQCAL_CONTROL_1_MAX_RX_GAIN_DB_MASK                                          0x00000fc0
+#define PHY_BB_TXIQCAL_CONTROL_1_MAX_RX_GAIN_DB_GET(x)                         (((x) & 0x00000fc0) >> 6)
+#define PHY_BB_TXIQCAL_CONTROL_1_MAX_RX_GAIN_DB_SET(x)                         (((x) << 6) & 0x00000fc0)
+#define PHY_BB_TXIQCAL_CONTROL_1_MIN_RX_GAIN_DB_MSB                                                   17
+#define PHY_BB_TXIQCAL_CONTROL_1_MIN_RX_GAIN_DB_LSB                                                   12
+#define PHY_BB_TXIQCAL_CONTROL_1_MIN_RX_GAIN_DB_MASK                                          0x0003f000
+#define PHY_BB_TXIQCAL_CONTROL_1_MIN_RX_GAIN_DB_GET(x)                        (((x) & 0x0003f000) >> 12)
+#define PHY_BB_TXIQCAL_CONTROL_1_MIN_RX_GAIN_DB_SET(x)                        (((x) << 12) & 0x0003f000)
+#define PHY_BB_TXIQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_MSB                                            24
+#define PHY_BB_TXIQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_LSB                                            18
+#define PHY_BB_TXIQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_MASK                                   0x01fc0000
+#define PHY_BB_TXIQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_GET(x)                 (((x) & 0x01fc0000) >> 18)
+#define PHY_BB_TXIQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_SET(x)                 (((x) << 18) & 0x01fc0000)
+
+/* macros for BB_txiqcal_control_2 */
+#define PHY_BB_TXIQCAL_CONTROL_2_ADDRESS                                                      0x0000a6e4
+#define PHY_BB_TXIQCAL_CONTROL_2_OFFSET                                                       0x0000a6e4
+#define PHY_BB_TXIQCAL_CONTROL_2_IQC_FORCED_PAGAIN_MSB                                                 3
+#define PHY_BB_TXIQCAL_CONTROL_2_IQC_FORCED_PAGAIN_LSB                                                 0
+#define PHY_BB_TXIQCAL_CONTROL_2_IQC_FORCED_PAGAIN_MASK                                       0x0000000f
+#define PHY_BB_TXIQCAL_CONTROL_2_IQC_FORCED_PAGAIN_GET(x)                      (((x) & 0x0000000f) >> 0)
+#define PHY_BB_TXIQCAL_CONTROL_2_IQC_FORCED_PAGAIN_SET(x)                      (((x) << 0) & 0x0000000f)
+#define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MIN_TX_GAIN_MSB                                                 8
+#define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MIN_TX_GAIN_LSB                                                 4
+#define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MIN_TX_GAIN_MASK                                       0x000001f0
+#define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MIN_TX_GAIN_GET(x)                      (((x) & 0x000001f0) >> 4)
+#define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MIN_TX_GAIN_SET(x)                      (((x) << 4) & 0x000001f0)
+#define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MAX_TX_GAIN_MSB                                                13
+#define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MAX_TX_GAIN_LSB                                                 9
+#define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MAX_TX_GAIN_MASK                                       0x00003e00
+#define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MAX_TX_GAIN_GET(x)                      (((x) & 0x00003e00) >> 9)
+#define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MAX_TX_GAIN_SET(x)                      (((x) << 9) & 0x00003e00)
+
+/* macros for BB_txiqcal_control_3 */
+#define PHY_BB_TXIQCAL_CONTROL_3_ADDRESS                                                      0x0000a6e8
+#define PHY_BB_TXIQCAL_CONTROL_3_OFFSET                                                       0x0000a6e8
+#define PHY_BB_TXIQCAL_CONTROL_3_PWR_HIGH_DB_MSB                                                       5
+#define PHY_BB_TXIQCAL_CONTROL_3_PWR_HIGH_DB_LSB                                                       0
+#define PHY_BB_TXIQCAL_CONTROL_3_PWR_HIGH_DB_MASK                                             0x0000003f
+#define PHY_BB_TXIQCAL_CONTROL_3_PWR_HIGH_DB_GET(x)                            (((x) & 0x0000003f) >> 0)
+#define PHY_BB_TXIQCAL_CONTROL_3_PWR_HIGH_DB_SET(x)                            (((x) << 0) & 0x0000003f)
+#define PHY_BB_TXIQCAL_CONTROL_3_PWR_LOW_DB_MSB                                                       11
+#define PHY_BB_TXIQCAL_CONTROL_3_PWR_LOW_DB_LSB                                                        6
+#define PHY_BB_TXIQCAL_CONTROL_3_PWR_LOW_DB_MASK                                              0x00000fc0
+#define PHY_BB_TXIQCAL_CONTROL_3_PWR_LOW_DB_GET(x)                             (((x) & 0x00000fc0) >> 6)
+#define PHY_BB_TXIQCAL_CONTROL_3_PWR_LOW_DB_SET(x)                             (((x) << 6) & 0x00000fc0)
+#define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_TONE_PHS_STEP_MSB                                              21
+#define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_TONE_PHS_STEP_LSB                                              12
+#define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_TONE_PHS_STEP_MASK                                     0x003ff000
+#define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_TONE_PHS_STEP_GET(x)                   (((x) & 0x003ff000) >> 12)
+#define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_TONE_PHS_STEP_SET(x)                   (((x) << 12) & 0x003ff000)
+#define PHY_BB_TXIQCAL_CONTROL_3_DC_EST_LEN_MSB                                                       23
+#define PHY_BB_TXIQCAL_CONTROL_3_DC_EST_LEN_LSB                                                       22
+#define PHY_BB_TXIQCAL_CONTROL_3_DC_EST_LEN_MASK                                              0x00c00000
+#define PHY_BB_TXIQCAL_CONTROL_3_DC_EST_LEN_GET(x)                            (((x) & 0x00c00000) >> 22)
+#define PHY_BB_TXIQCAL_CONTROL_3_DC_EST_LEN_SET(x)                            (((x) << 22) & 0x00c00000)
+#define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_LEN_MSB                                                      24
+#define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_LEN_LSB                                                      24
+#define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_LEN_MASK                                             0x01000000
+#define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_LEN_GET(x)                           (((x) & 0x01000000) >> 24)
+#define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_LEN_SET(x)                           (((x) << 24) & 0x01000000)
+#define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_SEL_MSB                                                      26
+#define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_SEL_LSB                                                      25
+#define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_SEL_MASK                                             0x06000000
+#define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_SEL_GET(x)                           (((x) & 0x06000000) >> 25)
+#define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_SEL_SET(x)                           (((x) << 25) & 0x06000000)
+#define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_MEAS_LEN_MSB                                                   28
+#define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_MEAS_LEN_LSB                                                   27
+#define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_MEAS_LEN_MASK                                          0x18000000
+#define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_MEAS_LEN_GET(x)                        (((x) & 0x18000000) >> 27)
+#define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_MEAS_LEN_SET(x)                        (((x) << 27) & 0x18000000)
+#define PHY_BB_TXIQCAL_CONTROL_3_DESIRED_SIZE_DB_MSB                                                  30
+#define PHY_BB_TXIQCAL_CONTROL_3_DESIRED_SIZE_DB_LSB                                                  29
+#define PHY_BB_TXIQCAL_CONTROL_3_DESIRED_SIZE_DB_MASK                                         0x60000000
+#define PHY_BB_TXIQCAL_CONTROL_3_DESIRED_SIZE_DB_GET(x)                       (((x) & 0x60000000) >> 29)
+#define PHY_BB_TXIQCAL_CONTROL_3_DESIRED_SIZE_DB_SET(x)                       (((x) << 29) & 0x60000000)
+#define PHY_BB_TXIQCAL_CONTROL_3_TX_IQCORR_EN_MSB                                                     31
+#define PHY_BB_TXIQCAL_CONTROL_3_TX_IQCORR_EN_LSB                                                     31
+#define PHY_BB_TXIQCAL_CONTROL_3_TX_IQCORR_EN_MASK                                            0x80000000
+#define PHY_BB_TXIQCAL_CONTROL_3_TX_IQCORR_EN_GET(x)                          (((x) & 0x80000000) >> 31)
+#define PHY_BB_TXIQCAL_CONTROL_3_TX_IQCORR_EN_SET(x)                          (((x) << 31) & 0x80000000)
+
+/* macros for BB_txiq_corr_coeff_01_b0 */
+#define PHY_BB_TXIQ_CORR_COEFF_01_B0_ADDRESS                                                  0x0000a6ec
+#define PHY_BB_TXIQ_CORR_COEFF_01_B0_OFFSET                                                   0x0000a6ec
+#define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_0_0_MSB                                          13
+#define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_0_0_LSB                                           0
+#define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_0_0_MASK                                 0x00003fff
+#define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_0_0_GET(x)                (((x) & 0x00003fff) >> 0)
+#define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_0_0_SET(x)                (((x) << 0) & 0x00003fff)
+#define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_1_0_MSB                                          27
+#define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_1_0_LSB                                          14
+#define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_1_0_MASK                                 0x0fffc000
+#define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_1_0_GET(x)               (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_1_0_SET(x)               (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_txiq_corr_coeff_23_b0 */
+#define PHY_BB_TXIQ_CORR_COEFF_23_B0_ADDRESS                                                  0x0000a6f0
+#define PHY_BB_TXIQ_CORR_COEFF_23_B0_OFFSET                                                   0x0000a6f0
+#define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_2_0_MSB                                          13
+#define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_2_0_LSB                                           0
+#define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_2_0_MASK                                 0x00003fff
+#define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_2_0_GET(x)                (((x) & 0x00003fff) >> 0)
+#define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_2_0_SET(x)                (((x) << 0) & 0x00003fff)
+#define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_3_0_MSB                                          27
+#define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_3_0_LSB                                          14
+#define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_3_0_MASK                                 0x0fffc000
+#define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_3_0_GET(x)               (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_3_0_SET(x)               (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_txiq_corr_coeff_45_b0 */
+#define PHY_BB_TXIQ_CORR_COEFF_45_B0_ADDRESS                                                  0x0000a6f4
+#define PHY_BB_TXIQ_CORR_COEFF_45_B0_OFFSET                                                   0x0000a6f4
+#define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_4_0_MSB                                          13
+#define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_4_0_LSB                                           0
+#define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_4_0_MASK                                 0x00003fff
+#define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_4_0_GET(x)                (((x) & 0x00003fff) >> 0)
+#define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_4_0_SET(x)                (((x) << 0) & 0x00003fff)
+#define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_5_0_MSB                                          27
+#define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_5_0_LSB                                          14
+#define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_5_0_MASK                                 0x0fffc000
+#define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_5_0_GET(x)               (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_5_0_SET(x)               (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_txiq_corr_coeff_67_b0 */
+#define PHY_BB_TXIQ_CORR_COEFF_67_B0_ADDRESS                                                  0x0000a6f8
+#define PHY_BB_TXIQ_CORR_COEFF_67_B0_OFFSET                                                   0x0000a6f8
+#define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_6_0_MSB                                          13
+#define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_6_0_LSB                                           0
+#define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_6_0_MASK                                 0x00003fff
+#define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_6_0_GET(x)                (((x) & 0x00003fff) >> 0)
+#define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_6_0_SET(x)                (((x) << 0) & 0x00003fff)
+#define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_7_0_MSB                                          27
+#define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_7_0_LSB                                          14
+#define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_7_0_MASK                                 0x0fffc000
+#define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_7_0_GET(x)               (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_7_0_SET(x)               (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_txiq_corr_coeff_89_b0 */
+#define PHY_BB_TXIQ_CORR_COEFF_89_B0_ADDRESS                                                  0x0000a6fc
+#define PHY_BB_TXIQ_CORR_COEFF_89_B0_OFFSET                                                   0x0000a6fc
+#define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_8_0_MSB                                          13
+#define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_8_0_LSB                                           0
+#define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_8_0_MASK                                 0x00003fff
+#define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_8_0_GET(x)                (((x) & 0x00003fff) >> 0)
+#define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_8_0_SET(x)                (((x) << 0) & 0x00003fff)
+#define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_9_0_MSB                                          27
+#define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_9_0_LSB                                          14
+#define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_9_0_MASK                                 0x0fffc000
+#define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_9_0_GET(x)               (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_9_0_SET(x)               (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_txiq_corr_coeff_ab_b0 */
+#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_ADDRESS                                                  0x0000a700
+#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_OFFSET                                                   0x0000a700
+#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_A_0_MSB                                          13
+#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_A_0_LSB                                           0
+#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_A_0_MASK                                 0x00003fff
+#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_A_0_GET(x)                (((x) & 0x00003fff) >> 0)
+#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_A_0_SET(x)                (((x) << 0) & 0x00003fff)
+#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_B_0_MSB                                          27
+#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_B_0_LSB                                          14
+#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_B_0_MASK                                 0x0fffc000
+#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_B_0_GET(x)               (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_B_0_SET(x)               (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_txiq_corr_coeff_cd_b0 */
+#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_ADDRESS                                                  0x0000a704
+#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_OFFSET                                                   0x0000a704
+#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_C_0_MSB                                          13
+#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_C_0_LSB                                           0
+#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_C_0_MASK                                 0x00003fff
+#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_C_0_GET(x)                (((x) & 0x00003fff) >> 0)
+#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_C_0_SET(x)                (((x) << 0) & 0x00003fff)
+#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_D_0_MSB                                          27
+#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_D_0_LSB                                          14
+#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_D_0_MASK                                 0x0fffc000
+#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_D_0_GET(x)               (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_D_0_SET(x)               (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_txiq_corr_coeff_ef_b0 */
+#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_ADDRESS                                                  0x0000a708
+#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_OFFSET                                                   0x0000a708
+#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_E_0_MSB                                          13
+#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_E_0_LSB                                           0
+#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_E_0_MASK                                 0x00003fff
+#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_E_0_GET(x)                (((x) & 0x00003fff) >> 0)
+#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_E_0_SET(x)                (((x) << 0) & 0x00003fff)
+#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_F_0_MSB                                          27
+#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_F_0_LSB                                          14
+#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_F_0_MASK                                 0x0fffc000
+#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_F_0_GET(x)               (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_F_0_SET(x)               (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_cal_rxbb_gain_tbl_0 */
+#define PHY_BB_CAL_RXBB_GAIN_TBL_0_ADDRESS                                                    0x0000a70c
+#define PHY_BB_CAL_RXBB_GAIN_TBL_0_OFFSET                                                     0x0000a70c
+#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_0_MSB                                        5
+#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_0_LSB                                        0
+#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_0_MASK                              0x0000003f
+#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_0_GET(x)             (((x) & 0x0000003f) >> 0)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_0_SET(x)             (((x) << 0) & 0x0000003f)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_1_MSB                                       11
+#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_1_LSB                                        6
+#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_1_MASK                              0x00000fc0
+#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_1_GET(x)             (((x) & 0x00000fc0) >> 6)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_1_SET(x)             (((x) << 6) & 0x00000fc0)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_2_MSB                                       17
+#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_2_LSB                                       12
+#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_2_MASK                              0x0003f000
+#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_2_GET(x)            (((x) & 0x0003f000) >> 12)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_2_SET(x)            (((x) << 12) & 0x0003f000)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_3_MSB                                       23
+#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_3_LSB                                       18
+#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_3_MASK                              0x00fc0000
+#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_3_GET(x)            (((x) & 0x00fc0000) >> 18)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_3_SET(x)            (((x) << 18) & 0x00fc0000)
+
+/* macros for BB_cal_rxbb_gain_tbl_4 */
+#define PHY_BB_CAL_RXBB_GAIN_TBL_4_ADDRESS                                                    0x0000a710
+#define PHY_BB_CAL_RXBB_GAIN_TBL_4_OFFSET                                                     0x0000a710
+#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_4_MSB                                        5
+#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_4_LSB                                        0
+#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_4_MASK                              0x0000003f
+#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_4_GET(x)             (((x) & 0x0000003f) >> 0)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_4_SET(x)             (((x) << 0) & 0x0000003f)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_5_MSB                                       11
+#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_5_LSB                                        6
+#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_5_MASK                              0x00000fc0
+#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_5_GET(x)             (((x) & 0x00000fc0) >> 6)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_5_SET(x)             (((x) << 6) & 0x00000fc0)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_6_MSB                                       17
+#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_6_LSB                                       12
+#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_6_MASK                              0x0003f000
+#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_6_GET(x)            (((x) & 0x0003f000) >> 12)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_6_SET(x)            (((x) << 12) & 0x0003f000)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_7_MSB                                       23
+#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_7_LSB                                       18
+#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_7_MASK                              0x00fc0000
+#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_7_GET(x)            (((x) & 0x00fc0000) >> 18)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_7_SET(x)            (((x) << 18) & 0x00fc0000)
+
+/* macros for BB_cal_rxbb_gain_tbl_8 */
+#define PHY_BB_CAL_RXBB_GAIN_TBL_8_ADDRESS                                                    0x0000a714
+#define PHY_BB_CAL_RXBB_GAIN_TBL_8_OFFSET                                                     0x0000a714
+#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_8_MSB                                        5
+#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_8_LSB                                        0
+#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_8_MASK                              0x0000003f
+#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_8_GET(x)             (((x) & 0x0000003f) >> 0)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_8_SET(x)             (((x) << 0) & 0x0000003f)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_9_MSB                                       11
+#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_9_LSB                                        6
+#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_9_MASK                              0x00000fc0
+#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_9_GET(x)             (((x) & 0x00000fc0) >> 6)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_9_SET(x)             (((x) << 6) & 0x00000fc0)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_10_MSB                                      17
+#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_10_LSB                                      12
+#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_10_MASK                             0x0003f000
+#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_10_GET(x)           (((x) & 0x0003f000) >> 12)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_10_SET(x)           (((x) << 12) & 0x0003f000)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_11_MSB                                      23
+#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_11_LSB                                      18
+#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_11_MASK                             0x00fc0000
+#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_11_GET(x)           (((x) & 0x00fc0000) >> 18)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_11_SET(x)           (((x) << 18) & 0x00fc0000)
+
+/* macros for BB_cal_rxbb_gain_tbl_12 */
+#define PHY_BB_CAL_RXBB_GAIN_TBL_12_ADDRESS                                                   0x0000a718
+#define PHY_BB_CAL_RXBB_GAIN_TBL_12_OFFSET                                                    0x0000a718
+#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_12_MSB                                      5
+#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_12_LSB                                      0
+#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_12_MASK                            0x0000003f
+#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_12_GET(x)           (((x) & 0x0000003f) >> 0)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_12_SET(x)           (((x) << 0) & 0x0000003f)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_13_MSB                                     11
+#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_13_LSB                                      6
+#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_13_MASK                            0x00000fc0
+#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_13_GET(x)           (((x) & 0x00000fc0) >> 6)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_13_SET(x)           (((x) << 6) & 0x00000fc0)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_14_MSB                                     17
+#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_14_LSB                                     12
+#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_14_MASK                            0x0003f000
+#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_14_GET(x)          (((x) & 0x0003f000) >> 12)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_14_SET(x)          (((x) << 12) & 0x0003f000)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_15_MSB                                     23
+#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_15_LSB                                     18
+#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_15_MASK                            0x00fc0000
+#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_15_GET(x)          (((x) & 0x00fc0000) >> 18)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_15_SET(x)          (((x) << 18) & 0x00fc0000)
+
+/* macros for BB_cal_rxbb_gain_tbl_16 */
+#define PHY_BB_CAL_RXBB_GAIN_TBL_16_ADDRESS                                                   0x0000a71c
+#define PHY_BB_CAL_RXBB_GAIN_TBL_16_OFFSET                                                    0x0000a71c
+#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_16_MSB                                      5
+#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_16_LSB                                      0
+#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_16_MASK                            0x0000003f
+#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_16_GET(x)           (((x) & 0x0000003f) >> 0)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_16_SET(x)           (((x) << 0) & 0x0000003f)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_17_MSB                                     11
+#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_17_LSB                                      6
+#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_17_MASK                            0x00000fc0
+#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_17_GET(x)           (((x) & 0x00000fc0) >> 6)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_17_SET(x)           (((x) << 6) & 0x00000fc0)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_18_MSB                                     17
+#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_18_LSB                                     12
+#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_18_MASK                            0x0003f000
+#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_18_GET(x)          (((x) & 0x0003f000) >> 12)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_18_SET(x)          (((x) << 12) & 0x0003f000)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_19_MSB                                     23
+#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_19_LSB                                     18
+#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_19_MASK                            0x00fc0000
+#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_19_GET(x)          (((x) & 0x00fc0000) >> 18)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_19_SET(x)          (((x) << 18) & 0x00fc0000)
+
+/* macros for BB_cal_rxbb_gain_tbl_20 */
+#define PHY_BB_CAL_RXBB_GAIN_TBL_20_ADDRESS                                                   0x0000a720
+#define PHY_BB_CAL_RXBB_GAIN_TBL_20_OFFSET                                                    0x0000a720
+#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_20_MSB                                      5
+#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_20_LSB                                      0
+#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_20_MASK                            0x0000003f
+#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_20_GET(x)           (((x) & 0x0000003f) >> 0)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_20_SET(x)           (((x) << 0) & 0x0000003f)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_21_MSB                                     11
+#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_21_LSB                                      6
+#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_21_MASK                            0x00000fc0
+#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_21_GET(x)           (((x) & 0x00000fc0) >> 6)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_21_SET(x)           (((x) << 6) & 0x00000fc0)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_22_MSB                                     17
+#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_22_LSB                                     12
+#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_22_MASK                            0x0003f000
+#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_22_GET(x)          (((x) & 0x0003f000) >> 12)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_22_SET(x)          (((x) << 12) & 0x0003f000)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_23_MSB                                     23
+#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_23_LSB                                     18
+#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_23_MASK                            0x00fc0000
+#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_23_GET(x)          (((x) & 0x00fc0000) >> 18)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_23_SET(x)          (((x) << 18) & 0x00fc0000)
+
+/* macros for BB_cal_rxbb_gain_tbl_24 */
+#define PHY_BB_CAL_RXBB_GAIN_TBL_24_ADDRESS                                                   0x0000a724
+#define PHY_BB_CAL_RXBB_GAIN_TBL_24_OFFSET                                                    0x0000a724
+#define PHY_BB_CAL_RXBB_GAIN_TBL_24_TXCAL_RX_BB_GAIN_TABLE_24_MSB                                      5
+#define PHY_BB_CAL_RXBB_GAIN_TBL_24_TXCAL_RX_BB_GAIN_TABLE_24_LSB                                      0
+#define PHY_BB_CAL_RXBB_GAIN_TBL_24_TXCAL_RX_BB_GAIN_TABLE_24_MASK                            0x0000003f
+#define PHY_BB_CAL_RXBB_GAIN_TBL_24_TXCAL_RX_BB_GAIN_TABLE_24_GET(x)           (((x) & 0x0000003f) >> 0)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_24_TXCAL_RX_BB_GAIN_TABLE_24_SET(x)           (((x) << 0) & 0x0000003f)
+
+/* macros for BB_txiqcal_status_b0 */
+#define PHY_BB_TXIQCAL_STATUS_B0_ADDRESS                                                      0x0000a728
+#define PHY_BB_TXIQCAL_STATUS_B0_OFFSET                                                       0x0000a728
+#define PHY_BB_TXIQCAL_STATUS_B0_TXIQCAL_FAILED_0_MSB                                                  0
+#define PHY_BB_TXIQCAL_STATUS_B0_TXIQCAL_FAILED_0_LSB                                                  0
+#define PHY_BB_TXIQCAL_STATUS_B0_TXIQCAL_FAILED_0_MASK                                        0x00000001
+#define PHY_BB_TXIQCAL_STATUS_B0_TXIQCAL_FAILED_0_GET(x)                       (((x) & 0x00000001) >> 0)
+#define PHY_BB_TXIQCAL_STATUS_B0_CALIBRATED_GAINS_0_MSB                                                5
+#define PHY_BB_TXIQCAL_STATUS_B0_CALIBRATED_GAINS_0_LSB                                                1
+#define PHY_BB_TXIQCAL_STATUS_B0_CALIBRATED_GAINS_0_MASK                                      0x0000003e
+#define PHY_BB_TXIQCAL_STATUS_B0_CALIBRATED_GAINS_0_GET(x)                     (((x) & 0x0000003e) >> 1)
+#define PHY_BB_TXIQCAL_STATUS_B0_TONE_GAIN_USED_0_MSB                                                 11
+#define PHY_BB_TXIQCAL_STATUS_B0_TONE_GAIN_USED_0_LSB                                                  6
+#define PHY_BB_TXIQCAL_STATUS_B0_TONE_GAIN_USED_0_MASK                                        0x00000fc0
+#define PHY_BB_TXIQCAL_STATUS_B0_TONE_GAIN_USED_0_GET(x)                       (((x) & 0x00000fc0) >> 6)
+#define PHY_BB_TXIQCAL_STATUS_B0_RX_GAIN_USED_0_MSB                                                   17
+#define PHY_BB_TXIQCAL_STATUS_B0_RX_GAIN_USED_0_LSB                                                   12
+#define PHY_BB_TXIQCAL_STATUS_B0_RX_GAIN_USED_0_MASK                                          0x0003f000
+#define PHY_BB_TXIQCAL_STATUS_B0_RX_GAIN_USED_0_GET(x)                        (((x) & 0x0003f000) >> 12)
+#define PHY_BB_TXIQCAL_STATUS_B0_LAST_MEAS_ADDR_0_MSB                                                 24
+#define PHY_BB_TXIQCAL_STATUS_B0_LAST_MEAS_ADDR_0_LSB                                                 18
+#define PHY_BB_TXIQCAL_STATUS_B0_LAST_MEAS_ADDR_0_MASK                                        0x01fc0000
+#define PHY_BB_TXIQCAL_STATUS_B0_LAST_MEAS_ADDR_0_GET(x)                      (((x) & 0x01fc0000) >> 18)
+
+/* macros for BB_paprd_trainer_cntl1 */
+#define PHY_BB_PAPRD_TRAINER_CNTL1_ADDRESS                                                    0x0000a72c
+#define PHY_BB_PAPRD_TRAINER_CNTL1_OFFSET                                                     0x0000a72c
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TRAIN_ENABLE_MSB                                           0
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TRAIN_ENABLE_LSB                                           0
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TRAIN_ENABLE_MASK                                 0x00000001
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TRAIN_ENABLE_GET(x)                (((x) & 0x00000001) >> 0)
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TRAIN_ENABLE_SET(x)                (((x) << 0) & 0x00000001)
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING_MSB                                          7
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING_LSB                                          1
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING_MASK                                0x000000fe
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING_GET(x)               (((x) & 0x000000fe) >> 1)
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING_SET(x)               (((x) << 1) & 0x000000fe)
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE_MSB                                          8
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE_LSB                                          8
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE_MASK                                0x00000100
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE_GET(x)               (((x) & 0x00000100) >> 8)
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE_SET(x)               (((x) << 8) & 0x00000100)
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE_MSB                                       9
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE_LSB                                       9
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE_MASK                             0x00000200
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE_GET(x)            (((x) & 0x00000200) >> 9)
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE_SET(x)            (((x) << 9) & 0x00000200)
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE_MSB                                         10
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE_LSB                                         10
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE_MASK                                0x00000400
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE_GET(x)              (((x) & 0x00000400) >> 10)
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE_SET(x)              (((x) << 10) & 0x00000400)
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE_MSB                                             11
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE_LSB                                             11
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE_MASK                                    0x00000800
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE_GET(x)                  (((x) & 0x00000800) >> 11)
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE_SET(x)                  (((x) << 11) & 0x00000800)
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP_MSB                                               18
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP_LSB                                               12
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP_MASK                                      0x0007f000
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP_GET(x)                    (((x) & 0x0007f000) >> 12)
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP_SET(x)                    (((x) << 12) & 0x0007f000)
+
+/* macros for BB_paprd_trainer_cntl2 */
+#define PHY_BB_PAPRD_TRAINER_CNTL2_ADDRESS                                                    0x0000a730
+#define PHY_BB_PAPRD_TRAINER_CNTL2_OFFSET                                                     0x0000a730
+#define PHY_BB_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_MSB                                       31
+#define PHY_BB_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_LSB                                        0
+#define PHY_BB_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_MASK                              0xffffffff
+#define PHY_BB_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_GET(x)             (((x) & 0xffffffff) >> 0)
+#define PHY_BB_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_SET(x)             (((x) << 0) & 0xffffffff)
+
+/* macros for BB_paprd_trainer_cntl3 */
+#define PHY_BB_PAPRD_TRAINER_CNTL3_ADDRESS                                                    0x0000a734
+#define PHY_BB_PAPRD_TRAINER_CNTL3_OFFSET                                                     0x0000a734
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE_MSB                                       5
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE_LSB                                       0
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE_MASK                             0x0000003f
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE_GET(x)            (((x) & 0x0000003f) >> 0)
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE_SET(x)            (((x) << 0) & 0x0000003f)
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP_MSB                                            11
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP_LSB                                             6
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP_MASK                                   0x00000fc0
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP_GET(x)                  (((x) & 0x00000fc0) >> 6)
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP_SET(x)                  (((x) << 6) & 0x00000fc0)
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL_MSB                                      16
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL_LSB                                      12
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL_MASK                             0x0001f000
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL_GET(x)           (((x) & 0x0001f000) >> 12)
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL_SET(x)           (((x) << 12) & 0x0001f000)
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES_MSB                                       19
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES_LSB                                       17
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES_MASK                              0x000e0000
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES_GET(x)            (((x) & 0x000e0000) >> 17)
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES_SET(x)            (((x) << 17) & 0x000e0000)
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN_MSB                                       23
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN_LSB                                       20
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN_MASK                              0x00f00000
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN_GET(x)            (((x) & 0x00f00000) >> 20)
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN_SET(x)            (((x) << 20) & 0x00f00000)
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN_MSB                                         27
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN_LSB                                         24
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN_MASK                                0x0f000000
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN_GET(x)              (((x) & 0x0f000000) >> 24)
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN_SET(x)              (((x) << 24) & 0x0f000000)
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_MSB                                       28
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_LSB                                       28
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_MASK                              0x10000000
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_GET(x)            (((x) & 0x10000000) >> 28)
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_SET(x)            (((x) << 28) & 0x10000000)
+
+/* macros for BB_paprd_trainer_cntl4 */
+#define PHY_BB_PAPRD_TRAINER_CNTL4_ADDRESS                                                    0x0000a738
+#define PHY_BB_PAPRD_TRAINER_CNTL4_OFFSET                                                     0x0000a738
+#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR_MSB                                              11
+#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR_LSB                                               0
+#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR_MASK                                     0x00000fff
+#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR_GET(x)                    (((x) & 0x00000fff) >> 0)
+#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR_SET(x)                    (((x) << 0) & 0x00000fff)
+#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA_MSB                                          15
+#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA_LSB                                          12
+#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA_MASK                                 0x0000f000
+#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA_GET(x)               (((x) & 0x0000f000) >> 12)
+#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA_SET(x)               (((x) << 12) & 0x0000f000)
+#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_MSB                                     25
+#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_LSB                                     16
+#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_MASK                            0x03ff0000
+#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_GET(x)          (((x) & 0x03ff0000) >> 16)
+#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_SET(x)          (((x) << 16) & 0x03ff0000)
+
+/* macros for BB_paprd_trainer_stat1 */
+#define PHY_BB_PAPRD_TRAINER_STAT1_ADDRESS                                                    0x0000a73c
+#define PHY_BB_PAPRD_TRAINER_STAT1_OFFSET                                                     0x0000a73c
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE_MSB                                                0
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE_LSB                                                0
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE_MASK                                      0x00000001
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE_GET(x)                     (((x) & 0x00000001) >> 0)
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE_SET(x)                     (((x) << 0) & 0x00000001)
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE_MSB                                          1
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE_LSB                                          1
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE_MASK                                0x00000002
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE_GET(x)               (((x) & 0x00000002) >> 1)
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR_MSB                                                  2
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR_LSB                                                  2
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR_MASK                                        0x00000004
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR_GET(x)                       (((x) & 0x00000004) >> 2)
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE_MSB                                              3
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE_LSB                                              3
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE_MASK                                    0x00000008
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE_GET(x)                   (((x) & 0x00000008) >> 3)
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX_MSB                                               8
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX_LSB                                               4
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX_MASK                                     0x000001f0
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX_GET(x)                    (((x) & 0x000001f0) >> 4)
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR_MSB                                                 16
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR_LSB                                                  9
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR_MASK                                        0x0001fe00
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR_GET(x)                       (((x) & 0x0001fe00) >> 9)
+
+/* macros for BB_paprd_trainer_stat2 */
+#define PHY_BB_PAPRD_TRAINER_STAT2_ADDRESS                                                    0x0000a740
+#define PHY_BB_PAPRD_TRAINER_STAT2_OFFSET                                                     0x0000a740
+#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL_MSB                                                 15
+#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL_LSB                                                  0
+#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL_MASK                                        0x0000ffff
+#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL_GET(x)                       (((x) & 0x0000ffff) >> 0)
+#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX_MSB                                               20
+#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX_LSB                                               16
+#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX_MASK                                      0x001f0000
+#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX_GET(x)                    (((x) & 0x001f0000) >> 16)
+#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX_MSB                                                 22
+#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX_LSB                                                 21
+#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX_MASK                                        0x00600000
+#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX_GET(x)                      (((x) & 0x00600000) >> 21)
+
+/* macros for BB_paprd_trainer_stat3 */
+#define PHY_BB_PAPRD_TRAINER_STAT3_ADDRESS                                                    0x0000a744
+#define PHY_BB_PAPRD_TRAINER_STAT3_OFFSET                                                     0x0000a744
+#define PHY_BB_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT_MSB                                        19
+#define PHY_BB_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT_LSB                                         0
+#define PHY_BB_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT_MASK                               0x000fffff
+#define PHY_BB_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT_GET(x)              (((x) & 0x000fffff) >> 0)
+
+/* macros for BB_fcal_1 */
+#define PHY_BB_FCAL_1_ADDRESS                                                                 0x0000a7d8
+#define PHY_BB_FCAL_1_OFFSET                                                                  0x0000a7d8
+#define PHY_BB_FCAL_1_FLC_PB_FSTEP_MSB                                                                 9
+#define PHY_BB_FCAL_1_FLC_PB_FSTEP_LSB                                                                 0
+#define PHY_BB_FCAL_1_FLC_PB_FSTEP_MASK                                                       0x000003ff
+#define PHY_BB_FCAL_1_FLC_PB_FSTEP_GET(x)                                      (((x) & 0x000003ff) >> 0)
+#define PHY_BB_FCAL_1_FLC_PB_FSTEP_SET(x)                                      (((x) << 0) & 0x000003ff)
+#define PHY_BB_FCAL_1_FLC_SB_FSTEP_MSB                                                                19
+#define PHY_BB_FCAL_1_FLC_SB_FSTEP_LSB                                                                10
+#define PHY_BB_FCAL_1_FLC_SB_FSTEP_MASK                                                       0x000ffc00
+#define PHY_BB_FCAL_1_FLC_SB_FSTEP_GET(x)                                     (((x) & 0x000ffc00) >> 10)
+#define PHY_BB_FCAL_1_FLC_SB_FSTEP_SET(x)                                     (((x) << 10) & 0x000ffc00)
+#define PHY_BB_FCAL_1_FLC_PB_ATTEN_MSB                                                                24
+#define PHY_BB_FCAL_1_FLC_PB_ATTEN_LSB                                                                20
+#define PHY_BB_FCAL_1_FLC_PB_ATTEN_MASK                                                       0x01f00000
+#define PHY_BB_FCAL_1_FLC_PB_ATTEN_GET(x)                                     (((x) & 0x01f00000) >> 20)
+#define PHY_BB_FCAL_1_FLC_PB_ATTEN_SET(x)                                     (((x) << 20) & 0x01f00000)
+#define PHY_BB_FCAL_1_FLC_SB_ATTEN_MSB                                                                29
+#define PHY_BB_FCAL_1_FLC_SB_ATTEN_LSB                                                                25
+#define PHY_BB_FCAL_1_FLC_SB_ATTEN_MASK                                                       0x3e000000
+#define PHY_BB_FCAL_1_FLC_SB_ATTEN_GET(x)                                     (((x) & 0x3e000000) >> 25)
+#define PHY_BB_FCAL_1_FLC_SB_ATTEN_SET(x)                                     (((x) << 25) & 0x3e000000)
+
+/* macros for BB_fcal_2_b0 */
+#define PHY_BB_FCAL_2_B0_ADDRESS                                                              0x0000a7dc
+#define PHY_BB_FCAL_2_B0_OFFSET                                                               0x0000a7dc
+#define PHY_BB_FCAL_2_B0_FLC_PWR_THRESH_MSB                                                            2
+#define PHY_BB_FCAL_2_B0_FLC_PWR_THRESH_LSB                                                            0
+#define PHY_BB_FCAL_2_B0_FLC_PWR_THRESH_MASK                                                  0x00000007
+#define PHY_BB_FCAL_2_B0_FLC_PWR_THRESH_GET(x)                                 (((x) & 0x00000007) >> 0)
+#define PHY_BB_FCAL_2_B0_FLC_PWR_THRESH_SET(x)                                 (((x) << 0) & 0x00000007)
+#define PHY_BB_FCAL_2_B0_FLC_SW_CAP_VAL_0_MSB                                                          7
+#define PHY_BB_FCAL_2_B0_FLC_SW_CAP_VAL_0_LSB                                                          3
+#define PHY_BB_FCAL_2_B0_FLC_SW_CAP_VAL_0_MASK                                                0x000000f8
+#define PHY_BB_FCAL_2_B0_FLC_SW_CAP_VAL_0_GET(x)                               (((x) & 0x000000f8) >> 3)
+#define PHY_BB_FCAL_2_B0_FLC_SW_CAP_VAL_0_SET(x)                               (((x) << 3) & 0x000000f8)
+#define PHY_BB_FCAL_2_B0_FLC_BBMISCGAIN_MSB                                                            9
+#define PHY_BB_FCAL_2_B0_FLC_BBMISCGAIN_LSB                                                            8
+#define PHY_BB_FCAL_2_B0_FLC_BBMISCGAIN_MASK                                                  0x00000300
+#define PHY_BB_FCAL_2_B0_FLC_BBMISCGAIN_GET(x)                                 (((x) & 0x00000300) >> 8)
+#define PHY_BB_FCAL_2_B0_FLC_BBMISCGAIN_SET(x)                                 (((x) << 8) & 0x00000300)
+#define PHY_BB_FCAL_2_B0_FLC_BB1DBGAIN_MSB                                                            12
+#define PHY_BB_FCAL_2_B0_FLC_BB1DBGAIN_LSB                                                            10
+#define PHY_BB_FCAL_2_B0_FLC_BB1DBGAIN_MASK                                                   0x00001c00
+#define PHY_BB_FCAL_2_B0_FLC_BB1DBGAIN_GET(x)                                 (((x) & 0x00001c00) >> 10)
+#define PHY_BB_FCAL_2_B0_FLC_BB1DBGAIN_SET(x)                                 (((x) << 10) & 0x00001c00)
+#define PHY_BB_FCAL_2_B0_FLC_BB6DBGAIN_MSB                                                            14
+#define PHY_BB_FCAL_2_B0_FLC_BB6DBGAIN_LSB                                                            13
+#define PHY_BB_FCAL_2_B0_FLC_BB6DBGAIN_MASK                                                   0x00006000
+#define PHY_BB_FCAL_2_B0_FLC_BB6DBGAIN_GET(x)                                 (((x) & 0x00006000) >> 13)
+#define PHY_BB_FCAL_2_B0_FLC_BB6DBGAIN_SET(x)                                 (((x) << 13) & 0x00006000)
+#define PHY_BB_FCAL_2_B0_FLC_SW_CAP_SET_MSB                                                           15
+#define PHY_BB_FCAL_2_B0_FLC_SW_CAP_SET_LSB                                                           15
+#define PHY_BB_FCAL_2_B0_FLC_SW_CAP_SET_MASK                                                  0x00008000
+#define PHY_BB_FCAL_2_B0_FLC_SW_CAP_SET_GET(x)                                (((x) & 0x00008000) >> 15)
+#define PHY_BB_FCAL_2_B0_FLC_SW_CAP_SET_SET(x)                                (((x) << 15) & 0x00008000)
+#define PHY_BB_FCAL_2_B0_FLC_MEAS_WIN_MSB                                                             18
+#define PHY_BB_FCAL_2_B0_FLC_MEAS_WIN_LSB                                                             16
+#define PHY_BB_FCAL_2_B0_FLC_MEAS_WIN_MASK                                                    0x00070000
+#define PHY_BB_FCAL_2_B0_FLC_MEAS_WIN_GET(x)                                  (((x) & 0x00070000) >> 16)
+#define PHY_BB_FCAL_2_B0_FLC_MEAS_WIN_SET(x)                                  (((x) << 16) & 0x00070000)
+#define PHY_BB_FCAL_2_B0_FLC_CAP_VAL_STATUS_0_MSB                                                     24
+#define PHY_BB_FCAL_2_B0_FLC_CAP_VAL_STATUS_0_LSB                                                     20
+#define PHY_BB_FCAL_2_B0_FLC_CAP_VAL_STATUS_0_MASK                                            0x01f00000
+#define PHY_BB_FCAL_2_B0_FLC_CAP_VAL_STATUS_0_GET(x)                          (((x) & 0x01f00000) >> 20)
+
+/* macros for BB_radar_bw_filter */
+#define PHY_BB_RADAR_BW_FILTER_ADDRESS                                                        0x0000a7e0
+#define PHY_BB_RADAR_BW_FILTER_OFFSET                                                         0x0000a7e0
+#define PHY_BB_RADAR_BW_FILTER_RADAR_AVG_BW_CHECK_MSB                                                  0
+#define PHY_BB_RADAR_BW_FILTER_RADAR_AVG_BW_CHECK_LSB                                                  0
+#define PHY_BB_RADAR_BW_FILTER_RADAR_AVG_BW_CHECK_MASK                                        0x00000001
+#define PHY_BB_RADAR_BW_FILTER_RADAR_AVG_BW_CHECK_GET(x)                       (((x) & 0x00000001) >> 0)
+#define PHY_BB_RADAR_BW_FILTER_RADAR_AVG_BW_CHECK_SET(x)                       (((x) << 0) & 0x00000001)
+#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_SRC_SEL_MSB                                                    1
+#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_SRC_SEL_LSB                                                    1
+#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_SRC_SEL_MASK                                          0x00000002
+#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_SRC_SEL_GET(x)                         (((x) & 0x00000002) >> 1)
+#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_SRC_SEL_SET(x)                         (((x) << 1) & 0x00000002)
+#define PHY_BB_RADAR_BW_FILTER_RADAR_FIRPWR_SEL_MSB                                                    3
+#define PHY_BB_RADAR_BW_FILTER_RADAR_FIRPWR_SEL_LSB                                                    2
+#define PHY_BB_RADAR_BW_FILTER_RADAR_FIRPWR_SEL_MASK                                          0x0000000c
+#define PHY_BB_RADAR_BW_FILTER_RADAR_FIRPWR_SEL_GET(x)                         (((x) & 0x0000000c) >> 2)
+#define PHY_BB_RADAR_BW_FILTER_RADAR_FIRPWR_SEL_SET(x)                         (((x) << 2) & 0x0000000c)
+#define PHY_BB_RADAR_BW_FILTER_RADAR_PULSE_WIDTH_SEL_MSB                                               5
+#define PHY_BB_RADAR_BW_FILTER_RADAR_PULSE_WIDTH_SEL_LSB                                               4
+#define PHY_BB_RADAR_BW_FILTER_RADAR_PULSE_WIDTH_SEL_MASK                                     0x00000030
+#define PHY_BB_RADAR_BW_FILTER_RADAR_PULSE_WIDTH_SEL_GET(x)                    (((x) & 0x00000030) >> 4)
+#define PHY_BB_RADAR_BW_FILTER_RADAR_PULSE_WIDTH_SEL_SET(x)                    (((x) << 4) & 0x00000030)
+#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_FIRPWR_THRESH_MSB                                             14
+#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_FIRPWR_THRESH_LSB                                              8
+#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_FIRPWR_THRESH_MASK                                    0x00007f00
+#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_FIRPWR_THRESH_GET(x)                   (((x) & 0x00007f00) >> 8)
+#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_FIRPWR_THRESH_SET(x)                   (((x) << 8) & 0x00007f00)
+#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_PWR_BIAS_MSB                                                  20
+#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_PWR_BIAS_LSB                                                  15
+#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_PWR_BIAS_MASK                                         0x001f8000
+#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_PWR_BIAS_GET(x)                       (((x) & 0x001f8000) >> 15)
+#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_PWR_BIAS_SET(x)                       (((x) << 15) & 0x001f8000)
+#define PHY_BB_RADAR_BW_FILTER_RADAR_BIN_MAX_BW_MSB                                                   26
+#define PHY_BB_RADAR_BW_FILTER_RADAR_BIN_MAX_BW_LSB                                                   21
+#define PHY_BB_RADAR_BW_FILTER_RADAR_BIN_MAX_BW_MASK                                          0x07e00000
+#define PHY_BB_RADAR_BW_FILTER_RADAR_BIN_MAX_BW_GET(x)                        (((x) & 0x07e00000) >> 21)
+#define PHY_BB_RADAR_BW_FILTER_RADAR_BIN_MAX_BW_SET(x)                        (((x) << 21) & 0x07e00000)
+
+/* macros for BB_dft_tone_ctrl_b0 */
+#define PHY_BB_DFT_TONE_CTRL_B0_ADDRESS                                                       0x0000a7e4
+#define PHY_BB_DFT_TONE_CTRL_B0_OFFSET                                                        0x0000a7e4
+#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_EN_0_MSB                                                      0
+#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_EN_0_LSB                                                      0
+#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_EN_0_MASK                                            0x00000001
+#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_EN_0_GET(x)                           (((x) & 0x00000001) >> 0)
+#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_EN_0_SET(x)                           (((x) << 0) & 0x00000001)
+#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_AMP_SEL_0_MSB                                                 3
+#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_AMP_SEL_0_LSB                                                 2
+#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_AMP_SEL_0_MASK                                       0x0000000c
+#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_AMP_SEL_0_GET(x)                      (((x) & 0x0000000c) >> 2)
+#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_AMP_SEL_0_SET(x)                      (((x) << 2) & 0x0000000c)
+#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_FREQ_ANG_0_MSB                                               12
+#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_FREQ_ANG_0_LSB                                                4
+#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_FREQ_ANG_0_MASK                                      0x00001ff0
+#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_FREQ_ANG_0_GET(x)                     (((x) & 0x00001ff0) >> 4)
+#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_FREQ_ANG_0_SET(x)                     (((x) << 4) & 0x00001ff0)
+
+/* macros for BB_therm_adc_1 */
+#define PHY_BB_THERM_ADC_1_ADDRESS                                                            0x0000a7e8
+#define PHY_BB_THERM_ADC_1_OFFSET                                                             0x0000a7e8
+#define PHY_BB_THERM_ADC_1_INIT_THERM_SETTING_MSB                                                      7
+#define PHY_BB_THERM_ADC_1_INIT_THERM_SETTING_LSB                                                      0
+#define PHY_BB_THERM_ADC_1_INIT_THERM_SETTING_MASK                                            0x000000ff
+#define PHY_BB_THERM_ADC_1_INIT_THERM_SETTING_GET(x)                           (((x) & 0x000000ff) >> 0)
+#define PHY_BB_THERM_ADC_1_INIT_THERM_SETTING_SET(x)                           (((x) << 0) & 0x000000ff)
+#define PHY_BB_THERM_ADC_1_INIT_VOLT_SETTING_MSB                                                      15
+#define PHY_BB_THERM_ADC_1_INIT_VOLT_SETTING_LSB                                                       8
+#define PHY_BB_THERM_ADC_1_INIT_VOLT_SETTING_MASK                                             0x0000ff00
+#define PHY_BB_THERM_ADC_1_INIT_VOLT_SETTING_GET(x)                            (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_THERM_ADC_1_INIT_VOLT_SETTING_SET(x)                            (((x) << 8) & 0x0000ff00)
+#define PHY_BB_THERM_ADC_1_INIT_ATB_SETTING_MSB                                                       23
+#define PHY_BB_THERM_ADC_1_INIT_ATB_SETTING_LSB                                                       16
+#define PHY_BB_THERM_ADC_1_INIT_ATB_SETTING_MASK                                              0x00ff0000
+#define PHY_BB_THERM_ADC_1_INIT_ATB_SETTING_GET(x)                            (((x) & 0x00ff0000) >> 16)
+#define PHY_BB_THERM_ADC_1_INIT_ATB_SETTING_SET(x)                            (((x) << 16) & 0x00ff0000)
+#define PHY_BB_THERM_ADC_1_SAMPLES_CNT_CODING_MSB                                                     25
+#define PHY_BB_THERM_ADC_1_SAMPLES_CNT_CODING_LSB                                                     24
+#define PHY_BB_THERM_ADC_1_SAMPLES_CNT_CODING_MASK                                            0x03000000
+#define PHY_BB_THERM_ADC_1_SAMPLES_CNT_CODING_GET(x)                          (((x) & 0x03000000) >> 24)
+#define PHY_BB_THERM_ADC_1_SAMPLES_CNT_CODING_SET(x)                          (((x) << 24) & 0x03000000)
+#define PHY_BB_THERM_ADC_1_USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET_MSB                               26
+#define PHY_BB_THERM_ADC_1_USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET_LSB                               26
+#define PHY_BB_THERM_ADC_1_USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET_MASK                      0x04000000
+#define PHY_BB_THERM_ADC_1_USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET_GET(x)    (((x) & 0x04000000) >> 26)
+#define PHY_BB_THERM_ADC_1_USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET_SET(x)    (((x) << 26) & 0x04000000)
+#define PHY_BB_THERM_ADC_1_FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS_MSB                                  27
+#define PHY_BB_THERM_ADC_1_FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS_LSB                                  27
+#define PHY_BB_THERM_ADC_1_FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS_MASK                         0x08000000
+#define PHY_BB_THERM_ADC_1_FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS_GET(x)       (((x) & 0x08000000) >> 27)
+#define PHY_BB_THERM_ADC_1_FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS_SET(x)       (((x) << 27) & 0x08000000)
+
+/* macros for BB_therm_adc_2 */
+#define PHY_BB_THERM_ADC_2_ADDRESS                                                            0x0000a7ec
+#define PHY_BB_THERM_ADC_2_OFFSET                                                             0x0000a7ec
+#define PHY_BB_THERM_ADC_2_MEASURE_THERM_FREQ_MSB                                                     11
+#define PHY_BB_THERM_ADC_2_MEASURE_THERM_FREQ_LSB                                                      0
+#define PHY_BB_THERM_ADC_2_MEASURE_THERM_FREQ_MASK                                            0x00000fff
+#define PHY_BB_THERM_ADC_2_MEASURE_THERM_FREQ_GET(x)                           (((x) & 0x00000fff) >> 0)
+#define PHY_BB_THERM_ADC_2_MEASURE_THERM_FREQ_SET(x)                           (((x) << 0) & 0x00000fff)
+#define PHY_BB_THERM_ADC_2_MEASURE_VOLT_FREQ_MSB                                                      21
+#define PHY_BB_THERM_ADC_2_MEASURE_VOLT_FREQ_LSB                                                      12
+#define PHY_BB_THERM_ADC_2_MEASURE_VOLT_FREQ_MASK                                             0x003ff000
+#define PHY_BB_THERM_ADC_2_MEASURE_VOLT_FREQ_GET(x)                           (((x) & 0x003ff000) >> 12)
+#define PHY_BB_THERM_ADC_2_MEASURE_VOLT_FREQ_SET(x)                           (((x) << 12) & 0x003ff000)
+#define PHY_BB_THERM_ADC_2_MEASURE_ATB_FREQ_MSB                                                       31
+#define PHY_BB_THERM_ADC_2_MEASURE_ATB_FREQ_LSB                                                       22
+#define PHY_BB_THERM_ADC_2_MEASURE_ATB_FREQ_MASK                                              0xffc00000
+#define PHY_BB_THERM_ADC_2_MEASURE_ATB_FREQ_GET(x)                            (((x) & 0xffc00000) >> 22)
+#define PHY_BB_THERM_ADC_2_MEASURE_ATB_FREQ_SET(x)                            (((x) << 22) & 0xffc00000)
+
+/* macros for BB_therm_adc_3 */
+#define PHY_BB_THERM_ADC_3_ADDRESS                                                            0x0000a7f0
+#define PHY_BB_THERM_ADC_3_OFFSET                                                             0x0000a7f0
+#define PHY_BB_THERM_ADC_3_THERM_ADC_OFFSET_MSB                                                        7
+#define PHY_BB_THERM_ADC_3_THERM_ADC_OFFSET_LSB                                                        0
+#define PHY_BB_THERM_ADC_3_THERM_ADC_OFFSET_MASK                                              0x000000ff
+#define PHY_BB_THERM_ADC_3_THERM_ADC_OFFSET_GET(x)                             (((x) & 0x000000ff) >> 0)
+#define PHY_BB_THERM_ADC_3_THERM_ADC_OFFSET_SET(x)                             (((x) << 0) & 0x000000ff)
+#define PHY_BB_THERM_ADC_3_THERM_ADC_SCALED_GAIN_MSB                                                  16
+#define PHY_BB_THERM_ADC_3_THERM_ADC_SCALED_GAIN_LSB                                                   8
+#define PHY_BB_THERM_ADC_3_THERM_ADC_SCALED_GAIN_MASK                                         0x0001ff00
+#define PHY_BB_THERM_ADC_3_THERM_ADC_SCALED_GAIN_GET(x)                        (((x) & 0x0001ff00) >> 8)
+#define PHY_BB_THERM_ADC_3_THERM_ADC_SCALED_GAIN_SET(x)                        (((x) << 8) & 0x0001ff00)
+#define PHY_BB_THERM_ADC_3_ADC_INTERVAL_MSB                                                           29
+#define PHY_BB_THERM_ADC_3_ADC_INTERVAL_LSB                                                           17
+#define PHY_BB_THERM_ADC_3_ADC_INTERVAL_MASK                                                  0x3ffe0000
+#define PHY_BB_THERM_ADC_3_ADC_INTERVAL_GET(x)                                (((x) & 0x3ffe0000) >> 17)
+#define PHY_BB_THERM_ADC_3_ADC_INTERVAL_SET(x)                                (((x) << 17) & 0x3ffe0000)
+
+/* macros for BB_therm_adc_4 */
+#define PHY_BB_THERM_ADC_4_ADDRESS                                                            0x0000a7f4
+#define PHY_BB_THERM_ADC_4_OFFSET                                                             0x0000a7f4
+#define PHY_BB_THERM_ADC_4_LATEST_THERM_VALUE_MSB                                                      7
+#define PHY_BB_THERM_ADC_4_LATEST_THERM_VALUE_LSB                                                      0
+#define PHY_BB_THERM_ADC_4_LATEST_THERM_VALUE_MASK                                            0x000000ff
+#define PHY_BB_THERM_ADC_4_LATEST_THERM_VALUE_GET(x)                           (((x) & 0x000000ff) >> 0)
+#define PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE_MSB                                                      15
+#define PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE_LSB                                                       8
+#define PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE_MASK                                             0x0000ff00
+#define PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE_GET(x)                            (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_THERM_ADC_4_LATEST_ATB_VALUE_MSB                                                       23
+#define PHY_BB_THERM_ADC_4_LATEST_ATB_VALUE_LSB                                                       16
+#define PHY_BB_THERM_ADC_4_LATEST_ATB_VALUE_MASK                                              0x00ff0000
+#define PHY_BB_THERM_ADC_4_LATEST_ATB_VALUE_GET(x)                            (((x) & 0x00ff0000) >> 16)
+
+/* macros for BB_tx_forced_gain */
+#define PHY_BB_TX_FORCED_GAIN_ADDRESS                                                         0x0000a7f8
+#define PHY_BB_TX_FORCED_GAIN_OFFSET                                                          0x0000a7f8
+#define PHY_BB_TX_FORCED_GAIN_FORCE_TX_GAIN_MSB                                                        0
+#define PHY_BB_TX_FORCED_GAIN_FORCE_TX_GAIN_LSB                                                        0
+#define PHY_BB_TX_FORCED_GAIN_FORCE_TX_GAIN_MASK                                              0x00000001
+#define PHY_BB_TX_FORCED_GAIN_FORCE_TX_GAIN_GET(x)                             (((x) & 0x00000001) >> 0)
+#define PHY_BB_TX_FORCED_GAIN_FORCE_TX_GAIN_SET(x)                             (((x) << 0) & 0x00000001)
+#define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN_MSB                                                   3
+#define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN_LSB                                                   1
+#define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN_MASK                                         0x0000000e
+#define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN_GET(x)                        (((x) & 0x0000000e) >> 1)
+#define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN_SET(x)                        (((x) << 1) & 0x0000000e)
+#define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN_MSB                                                   5
+#define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN_LSB                                                   4
+#define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN_MASK                                         0x00000030
+#define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN_GET(x)                        (((x) & 0x00000030) >> 4)
+#define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN_SET(x)                        (((x) << 4) & 0x00000030)
+#define PHY_BB_TX_FORCED_GAIN_FORCED_TXMXRGAIN_MSB                                                     9
+#define PHY_BB_TX_FORCED_GAIN_FORCED_TXMXRGAIN_LSB                                                     6
+#define PHY_BB_TX_FORCED_GAIN_FORCED_TXMXRGAIN_MASK                                           0x000003c0
+#define PHY_BB_TX_FORCED_GAIN_FORCED_TXMXRGAIN_GET(x)                          (((x) & 0x000003c0) >> 6)
+#define PHY_BB_TX_FORCED_GAIN_FORCED_TXMXRGAIN_SET(x)                          (((x) << 6) & 0x000003c0)
+#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNA_MSB                                                     13
+#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNA_LSB                                                     10
+#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNA_MASK                                            0x00003c00
+#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNA_GET(x)                          (((x) & 0x00003c00) >> 10)
+#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNA_SET(x)                          (((x) << 10) & 0x00003c00)
+#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNB_MSB                                                     17
+#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNB_LSB                                                     14
+#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNB_MASK                                            0x0003c000
+#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNB_GET(x)                          (((x) & 0x0003c000) >> 14)
+#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNB_SET(x)                          (((x) << 14) & 0x0003c000)
+#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNC_MSB                                                     21
+#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNC_LSB                                                     18
+#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNC_MASK                                            0x003c0000
+#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNC_GET(x)                          (((x) & 0x003c0000) >> 18)
+#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNC_SET(x)                          (((x) << 18) & 0x003c0000)
+#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGND_MSB                                                     23
+#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGND_LSB                                                     22
+#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGND_MASK                                            0x00c00000
+#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGND_GET(x)                          (((x) & 0x00c00000) >> 22)
+#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGND_SET(x)                          (((x) << 22) & 0x00c00000)
+#define PHY_BB_TX_FORCED_GAIN_FORCED_ENABLE_PAL_MSB                                                   24
+#define PHY_BB_TX_FORCED_GAIN_FORCED_ENABLE_PAL_LSB                                                   24
+#define PHY_BB_TX_FORCED_GAIN_FORCED_ENABLE_PAL_MASK                                          0x01000000
+#define PHY_BB_TX_FORCED_GAIN_FORCED_ENABLE_PAL_GET(x)                        (((x) & 0x01000000) >> 24)
+#define PHY_BB_TX_FORCED_GAIN_FORCED_ENABLE_PAL_SET(x)                        (((x) << 24) & 0x01000000)
+
+/* macros for BB_eco_ctrl */
+#define PHY_BB_ECO_CTRL_ADDRESS                                                               0x0000a7fc
+#define PHY_BB_ECO_CTRL_OFFSET                                                                0x0000a7fc
+#define PHY_BB_ECO_CTRL_ECO_CTRL_MSB                                                                   7
+#define PHY_BB_ECO_CTRL_ECO_CTRL_LSB                                                                   0
+#define PHY_BB_ECO_CTRL_ECO_CTRL_MASK                                                         0x000000ff
+#define PHY_BB_ECO_CTRL_ECO_CTRL_GET(x)                                        (((x) & 0x000000ff) >> 0)
+#define PHY_BB_ECO_CTRL_ECO_CTRL_SET(x)                                        (((x) << 0) & 0x000000ff)
+
+/* macros for BB_gain_force_max_gains_b1 */
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_ADDRESS                                                0x0000a848
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_OFFSET                                                 0x0000a848
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN1_HYST_MARGIN_1_MSB                                      13
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN1_HYST_MARGIN_1_LSB                                       7
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN1_HYST_MARGIN_1_MASK                             0x00003f80
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN1_HYST_MARGIN_1_GET(x)            (((x) & 0x00003f80) >> 7)
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN1_HYST_MARGIN_1_SET(x)            (((x) << 7) & 0x00003f80)
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN2_HYST_MARGIN_1_MSB                                      20
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN2_HYST_MARGIN_1_LSB                                      14
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN2_HYST_MARGIN_1_MASK                             0x001fc000
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN2_HYST_MARGIN_1_GET(x)           (((x) & 0x001fc000) >> 14)
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN2_HYST_MARGIN_1_SET(x)           (((x) << 14) & 0x001fc000)
+
+/* macros for BB_gains_min_offsets_b1 */
+#define PHY_BB_GAINS_MIN_OFFSETS_B1_ADDRESS                                                   0x0000a84c
+#define PHY_BB_GAINS_MIN_OFFSETS_B1_OFFSET                                                    0x0000a84c
+#define PHY_BB_GAINS_MIN_OFFSETS_B1_RF_GAIN_F_1_MSB                                                   24
+#define PHY_BB_GAINS_MIN_OFFSETS_B1_RF_GAIN_F_1_LSB                                                   17
+#define PHY_BB_GAINS_MIN_OFFSETS_B1_RF_GAIN_F_1_MASK                                          0x01fe0000
+#define PHY_BB_GAINS_MIN_OFFSETS_B1_RF_GAIN_F_1_GET(x)                        (((x) & 0x01fe0000) >> 17)
+#define PHY_BB_GAINS_MIN_OFFSETS_B1_RF_GAIN_F_1_SET(x)                        (((x) << 17) & 0x01fe0000)
+#define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN1_SW_F_1_MSB                                                25
+#define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN1_SW_F_1_LSB                                                25
+#define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN1_SW_F_1_MASK                                       0x02000000
+#define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN1_SW_F_1_GET(x)                     (((x) & 0x02000000) >> 25)
+#define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN1_SW_F_1_SET(x)                     (((x) << 25) & 0x02000000)
+#define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN2_SW_F_1_MSB                                                26
+#define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN2_SW_F_1_LSB                                                26
+#define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN2_SW_F_1_MASK                                       0x04000000
+#define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN2_SW_F_1_GET(x)                     (((x) & 0x04000000) >> 26)
+#define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN2_SW_F_1_SET(x)                     (((x) << 26) & 0x04000000)
+
+/* macros for BB_rx_ocgain2 */
+#define PHY_BB_RX_OCGAIN2_ADDRESS                                                             0x0000aa00
+#define PHY_BB_RX_OCGAIN2_OFFSET                                                              0x0000aa00
+#define PHY_BB_RX_OCGAIN2_GAIN_ENTRY2_MSB                                                             31
+#define PHY_BB_RX_OCGAIN2_GAIN_ENTRY2_LSB                                                              0
+#define PHY_BB_RX_OCGAIN2_GAIN_ENTRY2_MASK                                                    0xffffffff
+#define PHY_BB_RX_OCGAIN2_GAIN_ENTRY2_SET(x)                                   (((x) << 0) & 0xffffffff)
+
+/* macros for BB_ext_atten_switch_ctl_b1 */
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_ADDRESS                                                0x0000b20c
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_OFFSET                                                 0x0000b20c
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_DB_1_MSB                                                5
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_DB_1_LSB                                                0
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_DB_1_MASK                                      0x0000003f
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_DB_1_GET(x)                     (((x) & 0x0000003f) >> 0)
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_DB_1_SET(x)                     (((x) << 0) & 0x0000003f)
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_DB_1_MSB                                               11
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_DB_1_LSB                                                6
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_DB_1_MASK                                      0x00000fc0
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_DB_1_GET(x)                     (((x) & 0x00000fc0) >> 6)
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_DB_1_SET(x)                     (((x) << 6) & 0x00000fc0)
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_MARGIN_1_MSB                                           16
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_MARGIN_1_LSB                                           12
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_MARGIN_1_MASK                                  0x0001f000
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_MARGIN_1_GET(x)                (((x) & 0x0001f000) >> 12)
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_MARGIN_1_SET(x)                (((x) << 12) & 0x0001f000)
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_MARGIN_1_MSB                                           21
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_MARGIN_1_LSB                                           17
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_MARGIN_1_MASK                                  0x003e0000
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_MARGIN_1_GET(x)                (((x) & 0x003e0000) >> 17)
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_MARGIN_1_SET(x)                (((x) << 17) & 0x003e0000)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct bb_lc_reg_reg_s {
+  volatile char pad__0[0x9800];                                        /*        0x0 - 0x9800     */
+  volatile unsigned int BB_test_controls;                              /*     0x9800 - 0x9804     */
+  volatile unsigned int BB_gen_controls;                               /*     0x9804 - 0x9808     */
+  volatile unsigned int BB_test_controls_status;                       /*     0x9808 - 0x980c     */
+  volatile unsigned int BB_timing_controls_1;                          /*     0x980c - 0x9810     */
+  volatile unsigned int BB_timing_controls_2;                          /*     0x9810 - 0x9814     */
+  volatile unsigned int BB_timing_controls_3;                          /*     0x9814 - 0x9818     */
+  volatile unsigned int BB_D2_chip_id;                                 /*     0x9818 - 0x981c     */
+  volatile unsigned int BB_active;                                     /*     0x981c - 0x9820     */
+  volatile unsigned int BB_tx_timing_1;                                /*     0x9820 - 0x9824     */
+  volatile unsigned int BB_tx_timing_2;                                /*     0x9824 - 0x9828     */
+  volatile unsigned int BB_tx_timing_3;                                /*     0x9828 - 0x982c     */
+  volatile unsigned int BB_addac_parallel_control;                     /*     0x982c - 0x9830     */
+  volatile char pad__1[0x4];                                           /*     0x9830 - 0x9834     */
+  volatile unsigned int BB_xpa_timing_control;                         /*     0x9834 - 0x9838     */
+  volatile unsigned int BB_misc_pa_control;                            /*     0x9838 - 0x983c     */
+  volatile unsigned int BB_tstdac_constant;                            /*     0x983c - 0x9840     */
+  volatile unsigned int BB_find_signal_low;                            /*     0x9840 - 0x9844     */
+  volatile unsigned int BB_settling_time;                              /*     0x9844 - 0x9848     */
+  volatile unsigned int BB_gain_force_max_gains_b0;                    /*     0x9848 - 0x984c     */
+  volatile unsigned int BB_gains_min_offsets_b0;                       /*     0x984c - 0x9850     */
+  volatile unsigned int BB_desired_sigsize;                            /*     0x9850 - 0x9854     */
+  volatile unsigned int BB_timing_control_3a;                          /*     0x9854 - 0x9858     */
+  volatile unsigned int BB_find_signal;                                /*     0x9858 - 0x985c     */
+  volatile unsigned int BB_agc;                                        /*     0x985c - 0x9860     */
+  volatile unsigned int BB_agc_control;                                /*     0x9860 - 0x9864     */
+  volatile unsigned int BB_cca_b0;                                     /*     0x9864 - 0x9868     */
+  volatile unsigned int BB_sfcorr;                                     /*     0x9868 - 0x986c     */
+  volatile unsigned int BB_self_corr_low;                              /*     0x986c - 0x9870     */
+  volatile char pad__2[0x4];                                           /*     0x9870 - 0x9874     */
+  volatile unsigned int BB_synth_control;                              /*     0x9874 - 0x9878     */
+  volatile unsigned int BB_addac_clk_select;                           /*     0x9878 - 0x987c     */
+  volatile unsigned int BB_pll_cntl;                                   /*     0x987c - 0x9880     */
+  volatile char pad__3[0x80];                                          /*     0x9880 - 0x9900     */
+  volatile unsigned int BB_vit_spur_mask_A;                            /*     0x9900 - 0x9904     */
+  volatile unsigned int BB_vit_spur_mask_B;                            /*     0x9904 - 0x9908     */
+  volatile unsigned int BB_pilot_spur_mask;                            /*     0x9908 - 0x990c     */
+  volatile unsigned int BB_chan_spur_mask;                             /*     0x990c - 0x9910     */
+  volatile unsigned int BB_spectral_scan;                              /*     0x9910 - 0x9914     */
+  volatile unsigned int BB_analog_power_on_time;                       /*     0x9914 - 0x9918     */
+  volatile unsigned int BB_search_start_delay;                         /*     0x9918 - 0x991c     */
+  volatile unsigned int BB_max_rx_length;                              /*     0x991c - 0x9920     */
+  volatile unsigned int BB_timing_control_4;                           /*     0x9920 - 0x9924     */
+  volatile unsigned int BB_timing_control_5;                           /*     0x9924 - 0x9928     */
+  volatile unsigned int BB_phyonly_warm_reset;                         /*     0x9928 - 0x992c     */
+  volatile unsigned int BB_phyonly_control;                            /*     0x992c - 0x9930     */
+  volatile char pad__4[0x4];                                           /*     0x9930 - 0x9934     */
+  volatile unsigned int BB_powertx_rate1;                              /*     0x9934 - 0x9938     */
+  volatile unsigned int BB_powertx_rate2;                              /*     0x9938 - 0x993c     */
+  volatile unsigned int BB_powertx_max;                                /*     0x993c - 0x9940     */
+  volatile unsigned int BB_extension_radar;                            /*     0x9940 - 0x9944     */
+  volatile unsigned int BB_frame_control;                              /*     0x9944 - 0x9948     */
+  volatile unsigned int BB_timing_control_6;                           /*     0x9948 - 0x994c     */
+  volatile unsigned int BB_spur_mask_controls;                         /*     0x994c - 0x9950     */
+  volatile unsigned int BB_rx_iq_corr_b0;                              /*     0x9950 - 0x9954     */
+  volatile unsigned int BB_radar_detection;                            /*     0x9954 - 0x9958     */
+  volatile unsigned int BB_radar_detection_2;                          /*     0x9958 - 0x995c     */
+  volatile unsigned int BB_tx_phase_ramp_b0;                           /*     0x995c - 0x9960     */
+  volatile unsigned int BB_switch_table_chn_b0;                        /*     0x9960 - 0x9964     */
+  volatile unsigned int BB_switch_table_com1;                          /*     0x9964 - 0x9968     */
+  volatile unsigned int BB_cca_ctrl_2_b0;                              /*     0x9968 - 0x996c     */
+  volatile unsigned int BB_switch_table_com2;                          /*     0x996c - 0x9970     */
+  volatile unsigned int BB_restart;                                    /*     0x9970 - 0x9974     */
+  volatile char pad__5[0x4];                                           /*     0x9974 - 0x9978     */
+  volatile unsigned int BB_scrambler_seed;                             /*     0x9978 - 0x997c     */
+  volatile unsigned int BB_rfbus_request;                              /*     0x997c - 0x9980     */
+  volatile char pad__6[0x20];                                          /*     0x9980 - 0x99a0     */
+  volatile unsigned int BB_timing_control_11;                          /*     0x99a0 - 0x99a4     */
+  volatile unsigned int BB_multichain_enable;                          /*     0x99a4 - 0x99a8     */
+  volatile unsigned int BB_multichain_control;                         /*     0x99a8 - 0x99ac     */
+  volatile unsigned int BB_multichain_gain_ctrl;                       /*     0x99ac - 0x99b0     */
+  volatile char pad__7[0x4];                                           /*     0x99b0 - 0x99b4     */
+  volatile unsigned int BB_adc_gain_dc_corr_b0;                        /*     0x99b4 - 0x99b8     */
+  volatile unsigned int BB_ext_chan_pwr_thr_1;                         /*     0x99b8 - 0x99bc     */
+  volatile unsigned int BB_ext_chan_pwr_thr_2_b0;                      /*     0x99bc - 0x99c0     */
+  volatile unsigned int BB_ext_chan_scorr_thr;                         /*     0x99c0 - 0x99c4     */
+  volatile unsigned int BB_ext_chan_detect_win;                        /*     0x99c4 - 0x99c8     */
+  volatile unsigned int BB_pwr_thr_20_40_det;                          /*     0x99c8 - 0x99cc     */
+  volatile char pad__8[0x4];                                           /*     0x99cc - 0x99d0     */
+  volatile unsigned int BB_short_gi_delta_slope;                       /*     0x99d0 - 0x99d4     */
+  volatile char pad__9[0x8];                                           /*     0x99d4 - 0x99dc     */
+  volatile unsigned int BB_chaninfo_ctrl;                              /*     0x99dc - 0x99e0     */
+  volatile unsigned int BB_heavy_clip_ctrl;                            /*     0x99e0 - 0x99e4     */
+  volatile unsigned int BB_heavy_clip_20;                              /*     0x99e4 - 0x99e8     */
+  volatile unsigned int BB_heavy_clip_40;                              /*     0x99e8 - 0x99ec     */
+  volatile unsigned int BB_rifs_srch;                                  /*     0x99ec - 0x99f0     */
+  volatile unsigned int BB_iq_adc_cal_mode;                            /*     0x99f0 - 0x99f4     */
+  volatile char pad__10[0x8];                                          /*     0x99f4 - 0x99fc     */
+  volatile unsigned int BB_per_chain_csd;                              /*     0x99fc - 0x9a00     */
+  volatile unsigned int BB_rx_ocgain[128];                             /*     0x9a00 - 0x9c00     */
+  volatile unsigned int BB_tx_crc;                                     /*     0x9c00 - 0x9c04     */
+  volatile char pad__11[0xc];                                          /*     0x9c04 - 0x9c10     */
+  volatile unsigned int BB_iq_adc_meas_0_b0;                           /*     0x9c10 - 0x9c14     */
+  volatile unsigned int BB_iq_adc_meas_1_b0;                           /*     0x9c14 - 0x9c18     */
+  volatile unsigned int BB_iq_adc_meas_2_b0;                           /*     0x9c18 - 0x9c1c     */
+  volatile unsigned int BB_iq_adc_meas_3_b0;                           /*     0x9c1c - 0x9c20     */
+  volatile unsigned int BB_rfbus_grant;                                /*     0x9c20 - 0x9c24     */
+  volatile unsigned int BB_tstadc;                                     /*     0x9c24 - 0x9c28     */
+  volatile unsigned int BB_tstdac;                                     /*     0x9c28 - 0x9c2c     */
+  volatile char pad__12[0x4];                                          /*     0x9c2c - 0x9c30     */
+  volatile unsigned int BB_illegal_tx_rate;                            /*     0x9c30 - 0x9c34     */
+  volatile unsigned int BB_spur_report_b0;                             /*     0x9c34 - 0x9c38     */
+  volatile unsigned int BB_channel_status;                             /*     0x9c38 - 0x9c3c     */
+  volatile unsigned int BB_rssi_b0;                                    /*     0x9c3c - 0x9c40     */
+  volatile unsigned int BB_spur_est_cck_report_b0;                     /*     0x9c40 - 0x9c44     */
+  volatile char pad__13[0x68];                                         /*     0x9c44 - 0x9cac     */
+  volatile unsigned int BB_chan_info_noise_pwr;                        /*     0x9cac - 0x9cb0     */
+  volatile unsigned int BB_chan_info_gain_diff;                        /*     0x9cb0 - 0x9cb4     */
+  volatile unsigned int BB_chan_info_fine_timing;                      /*     0x9cb4 - 0x9cb8     */
+  volatile unsigned int BB_chan_info_gain_b0;                          /*     0x9cb8 - 0x9cbc     */
+  volatile unsigned int BB_chan_info_chan_tab_b0[60];                  /*     0x9cbc - 0x9dac     */
+  volatile char pad__14[0x38];                                         /*     0x9dac - 0x9de4     */
+  volatile unsigned int BB_paprd_am2am_mask;                           /*     0x9de4 - 0x9de8     */
+  volatile unsigned int BB_paprd_am2pm_mask;                           /*     0x9de8 - 0x9dec     */
+  volatile unsigned int BB_paprd_ht40_mask;                            /*     0x9dec - 0x9df0     */
+  volatile unsigned int BB_paprd_ctrl0;                                /*     0x9df0 - 0x9df4     */
+  volatile unsigned int BB_paprd_ctrl1;                                /*     0x9df4 - 0x9df8     */
+  volatile unsigned int BB_pa_gain123;                                 /*     0x9df8 - 0x9dfc     */
+  volatile unsigned int BB_pa_gain45;                                  /*     0x9dfc - 0x9e00     */
+  volatile unsigned int BB_paprd_pre_post_scale_0;                     /*     0x9e00 - 0x9e04     */
+  volatile unsigned int BB_paprd_pre_post_scale_1;                     /*     0x9e04 - 0x9e08     */
+  volatile unsigned int BB_paprd_pre_post_scale_2;                     /*     0x9e08 - 0x9e0c     */
+  volatile unsigned int BB_paprd_pre_post_scale_3;                     /*     0x9e0c - 0x9e10     */
+  volatile unsigned int BB_paprd_pre_post_scale_4;                     /*     0x9e10 - 0x9e14     */
+  volatile unsigned int BB_paprd_pre_post_scale_5;                     /*     0x9e14 - 0x9e18     */
+  volatile unsigned int BB_paprd_pre_post_scale_6;                     /*     0x9e18 - 0x9e1c     */
+  volatile unsigned int BB_paprd_pre_post_scale_7;                     /*     0x9e1c - 0x9e20     */
+  volatile unsigned int BB_paprd_mem_tab[120];                         /*     0x9e20 - 0xa000     */
+  volatile unsigned int BB_peak_det_ctrl_1;                            /*     0xa000 - 0xa004     */
+  volatile unsigned int BB_peak_det_ctrl_2;                            /*     0xa004 - 0xa008     */
+  volatile unsigned int BB_rx_gain_bounds_1;                           /*     0xa008 - 0xa00c     */
+  volatile unsigned int BB_rx_gain_bounds_2;                           /*     0xa00c - 0xa010     */
+  volatile unsigned int BB_peak_det_cal_ctrl;                          /*     0xa010 - 0xa014     */
+  volatile unsigned int BB_agc_dig_dc_ctrl;                            /*     0xa014 - 0xa018     */
+  volatile unsigned int BB_agc_dig_dc_status_i_b0;                     /*     0xa018 - 0xa01c     */
+  volatile unsigned int BB_agc_dig_dc_status_q_b0;                     /*     0xa01c - 0xa020     */
+  volatile char pad__15[0x1d4];                                        /*     0xa020 - 0xa1f4     */
+  volatile unsigned int BB_bbb_txfir_0;                                /*     0xa1f4 - 0xa1f8     */
+  volatile unsigned int BB_bbb_txfir_1;                                /*     0xa1f8 - 0xa1fc     */
+  volatile unsigned int BB_bbb_txfir_2;                                /*     0xa1fc - 0xa200     */
+  volatile unsigned int BB_modes_select;                               /*     0xa200 - 0xa204     */
+  volatile unsigned int BB_bbb_tx_ctrl;                                /*     0xa204 - 0xa208     */
+  volatile unsigned int BB_bbb_sig_detect;                             /*     0xa208 - 0xa20c     */
+  volatile unsigned int BB_ext_atten_switch_ctl_b0;                    /*     0xa20c - 0xa210     */
+  volatile unsigned int BB_bbb_rx_ctrl_1;                              /*     0xa210 - 0xa214     */
+  volatile unsigned int BB_bbb_rx_ctrl_2;                              /*     0xa214 - 0xa218     */
+  volatile unsigned int BB_bbb_rx_ctrl_3;                              /*     0xa218 - 0xa21c     */
+  volatile unsigned int BB_bbb_rx_ctrl_4;                              /*     0xa21c - 0xa220     */
+  volatile unsigned int BB_bbb_rx_ctrl_5;                              /*     0xa220 - 0xa224     */
+  volatile unsigned int BB_bbb_rx_ctrl_6;                              /*     0xa224 - 0xa228     */
+  volatile unsigned int BB_bbb_dagc_ctrl;                              /*     0xa228 - 0xa22c     */
+  volatile unsigned int BB_force_clken_cck;                            /*     0xa22c - 0xa230     */
+  volatile unsigned int BB_rx_clear_delay;                             /*     0xa230 - 0xa234     */
+  volatile unsigned int BB_powertx_rate3;                              /*     0xa234 - 0xa238     */
+  volatile unsigned int BB_powertx_rate4;                              /*     0xa238 - 0xa23c     */
+  volatile char pad__16[0x4];                                          /*     0xa23c - 0xa240     */
+  volatile unsigned int BB_cck_spur_mit;                               /*     0xa240 - 0xa244     */
+  volatile unsigned int BB_panic_watchdog_status;                      /*     0xa244 - 0xa248     */
+  volatile unsigned int BB_panic_watchdog_ctrl_1;                      /*     0xa248 - 0xa24c     */
+  volatile unsigned int BB_panic_watchdog_ctrl_2;                      /*     0xa24c - 0xa250     */
+  volatile unsigned int BB_iqcorr_ctrl_cck;                            /*     0xa250 - 0xa254     */
+  volatile unsigned int BB_bluetooth_cntl;                             /*     0xa254 - 0xa258     */
+  volatile unsigned int BB_tpc_1;                                      /*     0xa258 - 0xa25c     */
+  volatile unsigned int BB_tpc_2;                                      /*     0xa25c - 0xa260     */
+  volatile unsigned int BB_tpc_3;                                      /*     0xa260 - 0xa264     */
+  volatile unsigned int BB_tpc_4_b0;                                   /*     0xa264 - 0xa268     */
+  volatile unsigned int BB_analog_swap;                                /*     0xa268 - 0xa26c     */
+  volatile unsigned int BB_tpc_5_b0;                                   /*     0xa26c - 0xa270     */
+  volatile unsigned int BB_tpc_6_b0;                                   /*     0xa270 - 0xa274     */
+  volatile unsigned int BB_tpc_7;                                      /*     0xa274 - 0xa278     */
+  volatile unsigned int BB_tpc_8;                                      /*     0xa278 - 0xa27c     */
+  volatile unsigned int BB_tpc_9;                                      /*     0xa27c - 0xa280     */
+  volatile unsigned int BB_pdadc_tab_b0[32];                           /*     0xa280 - 0xa300     */
+  volatile unsigned int BB_cl_tab_b0[16];                              /*     0xa300 - 0xa340     */
+  volatile unsigned int BB_cl_map_0_b0;                                /*     0xa340 - 0xa344     */
+  volatile unsigned int BB_cl_map_1_b0;                                /*     0xa344 - 0xa348     */
+  volatile unsigned int BB_cl_map_2_b0;                                /*     0xa348 - 0xa34c     */
+  volatile unsigned int BB_cl_map_3_b0;                                /*     0xa34c - 0xa350     */
+  volatile char pad__17[0x8];                                          /*     0xa350 - 0xa358     */
+  volatile unsigned int BB_cl_cal_ctrl;                                /*     0xa358 - 0xa35c     */
+  volatile unsigned int BB_cl_map_pal_0_b0;                            /*     0xa35c - 0xa360     */
+  volatile unsigned int BB_cl_map_pal_1_b0;                            /*     0xa360 - 0xa364     */
+  volatile unsigned int BB_cl_map_pal_2_b0;                            /*     0xa364 - 0xa368     */
+  volatile unsigned int BB_cl_map_pal_3_b0;                            /*     0xa368 - 0xa36c     */
+  volatile char pad__18[0x1c];                                         /*     0xa36c - 0xa388     */
+  volatile unsigned int BB_rifs;                                       /*     0xa388 - 0xa38c     */
+  volatile unsigned int BB_powertx_rate5;                              /*     0xa38c - 0xa390     */
+  volatile unsigned int BB_powertx_rate6;                              /*     0xa390 - 0xa394     */
+  volatile unsigned int BB_tpc_10;                                     /*     0xa394 - 0xa398     */
+  volatile unsigned int BB_tpc_11_b0;                                  /*     0xa398 - 0xa39c     */
+  volatile unsigned int BB_cal_chain_mask;                             /*     0xa39c - 0xa3a0     */
+  volatile char pad__19[0x1c];                                         /*     0xa3a0 - 0xa3bc     */
+  volatile unsigned int BB_powertx_sub;                                /*     0xa3bc - 0xa3c0     */
+  volatile unsigned int BB_powertx_rate7;                              /*     0xa3c0 - 0xa3c4     */
+  volatile unsigned int BB_powertx_rate8;                              /*     0xa3c4 - 0xa3c8     */
+  volatile unsigned int BB_powertx_rate9;                              /*     0xa3c8 - 0xa3cc     */
+  volatile unsigned int BB_powertx_rate10;                             /*     0xa3cc - 0xa3d0     */
+  volatile unsigned int BB_powertx_rate11;                             /*     0xa3d0 - 0xa3d4     */
+  volatile unsigned int BB_powertx_rate12;                             /*     0xa3d4 - 0xa3d8     */
+  volatile unsigned int BB_force_analog;                               /*     0xa3d8 - 0xa3dc     */
+  volatile unsigned int BB_tpc_12;                                     /*     0xa3dc - 0xa3e0     */
+  volatile unsigned int BB_tpc_13;                                     /*     0xa3e0 - 0xa3e4     */
+  volatile unsigned int BB_tpc_14;                                     /*     0xa3e4 - 0xa3e8     */
+  volatile unsigned int BB_tpc_15;                                     /*     0xa3e8 - 0xa3ec     */
+  volatile unsigned int BB_tpc_16;                                     /*     0xa3ec - 0xa3f0     */
+  volatile unsigned int BB_tpc_17;                                     /*     0xa3f0 - 0xa3f4     */
+  volatile unsigned int BB_tpc_18;                                     /*     0xa3f4 - 0xa3f8     */
+  volatile unsigned int BB_tpc_19;                                     /*     0xa3f8 - 0xa3fc     */
+  volatile unsigned int BB_tpc_20;                                     /*     0xa3fc - 0xa400     */
+  volatile unsigned int BB_tx_gain_tab_1;                              /*     0xa400 - 0xa404     */
+  volatile unsigned int BB_tx_gain_tab_2;                              /*     0xa404 - 0xa408     */
+  volatile unsigned int BB_tx_gain_tab_3;                              /*     0xa408 - 0xa40c     */
+  volatile unsigned int BB_tx_gain_tab_4;                              /*     0xa40c - 0xa410     */
+  volatile unsigned int BB_tx_gain_tab_5;                              /*     0xa410 - 0xa414     */
+  volatile unsigned int BB_tx_gain_tab_6;                              /*     0xa414 - 0xa418     */
+  volatile unsigned int BB_tx_gain_tab_7;                              /*     0xa418 - 0xa41c     */
+  volatile unsigned int BB_tx_gain_tab_8;                              /*     0xa41c - 0xa420     */
+  volatile unsigned int BB_tx_gain_tab_9;                              /*     0xa420 - 0xa424     */
+  volatile unsigned int BB_tx_gain_tab_10;                             /*     0xa424 - 0xa428     */
+  volatile unsigned int BB_tx_gain_tab_11;                             /*     0xa428 - 0xa42c     */
+  volatile unsigned int BB_tx_gain_tab_12;                             /*     0xa42c - 0xa430     */
+  volatile unsigned int BB_tx_gain_tab_13;                             /*     0xa430 - 0xa434     */
+  volatile unsigned int BB_tx_gain_tab_14;                             /*     0xa434 - 0xa438     */
+  volatile unsigned int BB_tx_gain_tab_15;                             /*     0xa438 - 0xa43c     */
+  volatile unsigned int BB_tx_gain_tab_16;                             /*     0xa43c - 0xa440     */
+  volatile unsigned int BB_tx_gain_tab_17;                             /*     0xa440 - 0xa444     */
+  volatile unsigned int BB_tx_gain_tab_18;                             /*     0xa444 - 0xa448     */
+  volatile unsigned int BB_tx_gain_tab_19;                             /*     0xa448 - 0xa44c     */
+  volatile unsigned int BB_tx_gain_tab_20;                             /*     0xa44c - 0xa450     */
+  volatile unsigned int BB_tx_gain_tab_21;                             /*     0xa450 - 0xa454     */
+  volatile unsigned int BB_tx_gain_tab_22;                             /*     0xa454 - 0xa458     */
+  volatile unsigned int BB_tx_gain_tab_23;                             /*     0xa458 - 0xa45c     */
+  volatile unsigned int BB_tx_gain_tab_24;                             /*     0xa45c - 0xa460     */
+  volatile unsigned int BB_tx_gain_tab_25;                             /*     0xa460 - 0xa464     */
+  volatile unsigned int BB_tx_gain_tab_26;                             /*     0xa464 - 0xa468     */
+  volatile unsigned int BB_tx_gain_tab_27;                             /*     0xa468 - 0xa46c     */
+  volatile unsigned int BB_tx_gain_tab_28;                             /*     0xa46c - 0xa470     */
+  volatile unsigned int BB_tx_gain_tab_29;                             /*     0xa470 - 0xa474     */
+  volatile unsigned int BB_tx_gain_tab_30;                             /*     0xa474 - 0xa478     */
+  volatile unsigned int BB_tx_gain_tab_31;                             /*     0xa478 - 0xa47c     */
+  volatile unsigned int BB_tx_gain_tab_32;                             /*     0xa47c - 0xa480     */
+  volatile unsigned int BB_tx_gain_tab_pal_1;                          /*     0xa480 - 0xa484     */
+  volatile unsigned int BB_tx_gain_tab_pal_2;                          /*     0xa484 - 0xa488     */
+  volatile unsigned int BB_tx_gain_tab_pal_3;                          /*     0xa488 - 0xa48c     */
+  volatile unsigned int BB_tx_gain_tab_pal_4;                          /*     0xa48c - 0xa490     */
+  volatile unsigned int BB_tx_gain_tab_pal_5;                          /*     0xa490 - 0xa494     */
+  volatile unsigned int BB_tx_gain_tab_pal_6;                          /*     0xa494 - 0xa498     */
+  volatile unsigned int BB_tx_gain_tab_pal_7;                          /*     0xa498 - 0xa49c     */
+  volatile unsigned int BB_tx_gain_tab_pal_8;                          /*     0xa49c - 0xa4a0     */
+  volatile unsigned int BB_tx_gain_tab_pal_9;                          /*     0xa4a0 - 0xa4a4     */
+  volatile unsigned int BB_tx_gain_tab_pal_10;                         /*     0xa4a4 - 0xa4a8     */
+  volatile unsigned int BB_tx_gain_tab_pal_11;                         /*     0xa4a8 - 0xa4ac     */
+  volatile unsigned int BB_tx_gain_tab_pal_12;                         /*     0xa4ac - 0xa4b0     */
+  volatile unsigned int BB_tx_gain_tab_pal_13;                         /*     0xa4b0 - 0xa4b4     */
+  volatile unsigned int BB_tx_gain_tab_pal_14;                         /*     0xa4b4 - 0xa4b8     */
+  volatile unsigned int BB_tx_gain_tab_pal_15;                         /*     0xa4b8 - 0xa4bc     */
+  volatile unsigned int BB_tx_gain_tab_pal_16;                         /*     0xa4bc - 0xa4c0     */
+  volatile unsigned int BB_tx_gain_tab_pal_17;                         /*     0xa4c0 - 0xa4c4     */
+  volatile unsigned int BB_tx_gain_tab_pal_18;                         /*     0xa4c4 - 0xa4c8     */
+  volatile unsigned int BB_tx_gain_tab_pal_19;                         /*     0xa4c8 - 0xa4cc     */
+  volatile unsigned int BB_tx_gain_tab_pal_20;                         /*     0xa4cc - 0xa4d0     */
+  volatile unsigned int BB_tx_gain_tab_pal_21;                         /*     0xa4d0 - 0xa4d4     */
+  volatile unsigned int BB_tx_gain_tab_pal_22;                         /*     0xa4d4 - 0xa4d8     */
+  volatile unsigned int BB_tx_gain_tab_pal_23;                         /*     0xa4d8 - 0xa4dc     */
+  volatile unsigned int BB_tx_gain_tab_pal_24;                         /*     0xa4dc - 0xa4e0     */
+  volatile unsigned int BB_tx_gain_tab_pal_25;                         /*     0xa4e0 - 0xa4e4     */
+  volatile unsigned int BB_tx_gain_tab_pal_26;                         /*     0xa4e4 - 0xa4e8     */
+  volatile unsigned int BB_tx_gain_tab_pal_27;                         /*     0xa4e8 - 0xa4ec     */
+  volatile unsigned int BB_tx_gain_tab_pal_28;                         /*     0xa4ec - 0xa4f0     */
+  volatile unsigned int BB_tx_gain_tab_pal_29;                         /*     0xa4f0 - 0xa4f4     */
+  volatile unsigned int BB_tx_gain_tab_pal_30;                         /*     0xa4f4 - 0xa4f8     */
+  volatile unsigned int BB_tx_gain_tab_pal_31;                         /*     0xa4f8 - 0xa4fc     */
+  volatile unsigned int BB_tx_gain_tab_pal_32;                         /*     0xa4fc - 0xa500     */
+  volatile char pad__20[0x18];                                         /*     0xa500 - 0xa518     */
+  volatile unsigned int BB_caltx_gain_set_0;                           /*     0xa518 - 0xa51c     */
+  volatile unsigned int BB_caltx_gain_set_2;                           /*     0xa51c - 0xa520     */
+  volatile unsigned int BB_caltx_gain_set_4;                           /*     0xa520 - 0xa524     */
+  volatile unsigned int BB_caltx_gain_set_6;                           /*     0xa524 - 0xa528     */
+  volatile unsigned int BB_caltx_gain_set_8;                           /*     0xa528 - 0xa52c     */
+  volatile unsigned int BB_caltx_gain_set_10;                          /*     0xa52c - 0xa530     */
+  volatile unsigned int BB_caltx_gain_set_12;                          /*     0xa530 - 0xa534     */
+  volatile unsigned int BB_caltx_gain_set_14;                          /*     0xa534 - 0xa538     */
+  volatile unsigned int BB_caltx_gain_set_16;                          /*     0xa538 - 0xa53c     */
+  volatile unsigned int BB_caltx_gain_set_18;                          /*     0xa53c - 0xa540     */
+  volatile unsigned int BB_caltx_gain_set_20;                          /*     0xa540 - 0xa544     */
+  volatile unsigned int BB_caltx_gain_set_22;                          /*     0xa544 - 0xa548     */
+  volatile unsigned int BB_caltx_gain_set_24;                          /*     0xa548 - 0xa54c     */
+  volatile unsigned int BB_caltx_gain_set_26;                          /*     0xa54c - 0xa550     */
+  volatile unsigned int BB_caltx_gain_set_28;                          /*     0xa550 - 0xa554     */
+  volatile unsigned int BB_caltx_gain_set_30;                          /*     0xa554 - 0xa558     */
+  volatile unsigned int BB_txiqcal_meas_b0[96];                        /*     0xa558 - 0xa6d8     */
+  volatile unsigned int BB_txiqcal_start;                              /*     0xa6d8 - 0xa6dc     */
+  volatile unsigned int BB_txiqcal_control_0;                          /*     0xa6dc - 0xa6e0     */
+  volatile unsigned int BB_txiqcal_control_1;                          /*     0xa6e0 - 0xa6e4     */
+  volatile unsigned int BB_txiqcal_control_2;                          /*     0xa6e4 - 0xa6e8     */
+  volatile unsigned int BB_txiqcal_control_3;                          /*     0xa6e8 - 0xa6ec     */
+  volatile unsigned int BB_txiq_corr_coeff_01_b0;                      /*     0xa6ec - 0xa6f0     */
+  volatile unsigned int BB_txiq_corr_coeff_23_b0;                      /*     0xa6f0 - 0xa6f4     */
+  volatile unsigned int BB_txiq_corr_coeff_45_b0;                      /*     0xa6f4 - 0xa6f8     */
+  volatile unsigned int BB_txiq_corr_coeff_67_b0;                      /*     0xa6f8 - 0xa6fc     */
+  volatile unsigned int BB_txiq_corr_coeff_89_b0;                      /*     0xa6fc - 0xa700     */
+  volatile unsigned int BB_txiq_corr_coeff_ab_b0;                      /*     0xa700 - 0xa704     */
+  volatile unsigned int BB_txiq_corr_coeff_cd_b0;                      /*     0xa704 - 0xa708     */
+  volatile unsigned int BB_txiq_corr_coeff_ef_b0;                      /*     0xa708 - 0xa70c     */
+  volatile unsigned int BB_cal_rxbb_gain_tbl_0;                        /*     0xa70c - 0xa710     */
+  volatile unsigned int BB_cal_rxbb_gain_tbl_4;                        /*     0xa710 - 0xa714     */
+  volatile unsigned int BB_cal_rxbb_gain_tbl_8;                        /*     0xa714 - 0xa718     */
+  volatile unsigned int BB_cal_rxbb_gain_tbl_12;                       /*     0xa718 - 0xa71c     */
+  volatile unsigned int BB_cal_rxbb_gain_tbl_16;                       /*     0xa71c - 0xa720     */
+  volatile unsigned int BB_cal_rxbb_gain_tbl_20;                       /*     0xa720 - 0xa724     */
+  volatile unsigned int BB_cal_rxbb_gain_tbl_24;                       /*     0xa724 - 0xa728     */
+  volatile unsigned int BB_txiqcal_status_b0;                          /*     0xa728 - 0xa72c     */
+  volatile unsigned int BB_paprd_trainer_cntl1;                        /*     0xa72c - 0xa730     */
+  volatile unsigned int BB_paprd_trainer_cntl2;                        /*     0xa730 - 0xa734     */
+  volatile unsigned int BB_paprd_trainer_cntl3;                        /*     0xa734 - 0xa738     */
+  volatile unsigned int BB_paprd_trainer_cntl4;                        /*     0xa738 - 0xa73c     */
+  volatile unsigned int BB_paprd_trainer_stat1;                        /*     0xa73c - 0xa740     */
+  volatile unsigned int BB_paprd_trainer_stat2;                        /*     0xa740 - 0xa744     */
+  volatile unsigned int BB_paprd_trainer_stat3;                        /*     0xa744 - 0xa748     */
+  volatile char pad__21[0x90];                                         /*     0xa748 - 0xa7d8     */
+  volatile unsigned int BB_fcal_1;                                     /*     0xa7d8 - 0xa7dc     */
+  volatile unsigned int BB_fcal_2_b0;                                  /*     0xa7dc - 0xa7e0     */
+  volatile unsigned int BB_radar_bw_filter;                            /*     0xa7e0 - 0xa7e4     */
+  volatile unsigned int BB_dft_tone_ctrl_b0;                           /*     0xa7e4 - 0xa7e8     */
+  volatile unsigned int BB_therm_adc_1;                                /*     0xa7e8 - 0xa7ec     */
+  volatile unsigned int BB_therm_adc_2;                                /*     0xa7ec - 0xa7f0     */
+  volatile unsigned int BB_therm_adc_3;                                /*     0xa7f0 - 0xa7f4     */
+  volatile unsigned int BB_therm_adc_4;                                /*     0xa7f4 - 0xa7f8     */
+  volatile unsigned int BB_tx_forced_gain;                             /*     0xa7f8 - 0xa7fc     */
+  volatile unsigned int BB_eco_ctrl;                                   /*     0xa7fc - 0xa800     */
+  volatile char pad__22[0x48];                                         /*     0xa800 - 0xa848     */
+  volatile unsigned int BB_gain_force_max_gains_b1;                    /*     0xa848 - 0xa84c     */
+  volatile unsigned int BB_gains_min_offsets_b1;                       /*     0xa84c - 0xa850     */
+  volatile char pad__23[0x1b0];                                        /*     0xa850 - 0xaa00     */
+  volatile unsigned int BB_rx_ocgain2[128];                            /*     0xaa00 - 0xac00     */
+  volatile char pad__24[0x60c];                                        /*     0xac00 - 0xb20c     */
+  volatile unsigned int BB_ext_atten_switch_ctl_b1;                    /*     0xb20c - 0xb210     */
+} bb_lc_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _BB_LC_REG_REG_H_ */
diff --git a/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/efuse_reg.h b/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/efuse_reg.h
new file mode 100644
index 00000000000..12cadb33748
--- /dev/null
+++ b/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/efuse_reg.h
@@ -0,0 +1,108 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _EFUSE_REG_REG_H_
+#define _EFUSE_REG_REG_H_
+
+#define EFUSE_WR_ENABLE_REG_ADDRESS              0x00000000
+#define EFUSE_WR_ENABLE_REG_OFFSET               0x00000000
+#define EFUSE_WR_ENABLE_REG_V_MSB                0
+#define EFUSE_WR_ENABLE_REG_V_LSB                0
+#define EFUSE_WR_ENABLE_REG_V_MASK               0x00000001
+#define EFUSE_WR_ENABLE_REG_V_GET(x)             (((x) & EFUSE_WR_ENABLE_REG_V_MASK) >> EFUSE_WR_ENABLE_REG_V_LSB)
+#define EFUSE_WR_ENABLE_REG_V_SET(x)             (((x) << EFUSE_WR_ENABLE_REG_V_LSB) & EFUSE_WR_ENABLE_REG_V_MASK)
+
+#define EFUSE_INT_ENABLE_REG_ADDRESS             0x00000004
+#define EFUSE_INT_ENABLE_REG_OFFSET              0x00000004
+#define EFUSE_INT_ENABLE_REG_V_MSB               0
+#define EFUSE_INT_ENABLE_REG_V_LSB               0
+#define EFUSE_INT_ENABLE_REG_V_MASK              0x00000001
+#define EFUSE_INT_ENABLE_REG_V_GET(x)            (((x) & EFUSE_INT_ENABLE_REG_V_MASK) >> EFUSE_INT_ENABLE_REG_V_LSB)
+#define EFUSE_INT_ENABLE_REG_V_SET(x)            (((x) << EFUSE_INT_ENABLE_REG_V_LSB) & EFUSE_INT_ENABLE_REG_V_MASK)
+
+#define EFUSE_INT_STATUS_REG_ADDRESS             0x00000008
+#define EFUSE_INT_STATUS_REG_OFFSET              0x00000008
+#define EFUSE_INT_STATUS_REG_V_MSB               0
+#define EFUSE_INT_STATUS_REG_V_LSB               0
+#define EFUSE_INT_STATUS_REG_V_MASK              0x00000001
+#define EFUSE_INT_STATUS_REG_V_GET(x)            (((x) & EFUSE_INT_STATUS_REG_V_MASK) >> EFUSE_INT_STATUS_REG_V_LSB)
+#define EFUSE_INT_STATUS_REG_V_SET(x)            (((x) << EFUSE_INT_STATUS_REG_V_LSB) & EFUSE_INT_STATUS_REG_V_MASK)
+
+#define BITMASK_WR_REG_ADDRESS                   0x0000000c
+#define BITMASK_WR_REG_OFFSET                    0x0000000c
+#define BITMASK_WR_REG_V_MSB                     31
+#define BITMASK_WR_REG_V_LSB                     0
+#define BITMASK_WR_REG_V_MASK                    0xffffffff
+#define BITMASK_WR_REG_V_GET(x)                  (((x) & BITMASK_WR_REG_V_MASK) >> BITMASK_WR_REG_V_LSB)
+#define BITMASK_WR_REG_V_SET(x)                  (((x) << BITMASK_WR_REG_V_LSB) & BITMASK_WR_REG_V_MASK)
+
+#define VDDQ_SETTLE_TIME_REG_ADDRESS             0x00000010
+#define VDDQ_SETTLE_TIME_REG_OFFSET              0x00000010
+#define VDDQ_SETTLE_TIME_REG_V_MSB               31
+#define VDDQ_SETTLE_TIME_REG_V_LSB               0
+#define VDDQ_SETTLE_TIME_REG_V_MASK              0xffffffff
+#define VDDQ_SETTLE_TIME_REG_V_GET(x)            (((x) & VDDQ_SETTLE_TIME_REG_V_MASK) >> VDDQ_SETTLE_TIME_REG_V_LSB)
+#define VDDQ_SETTLE_TIME_REG_V_SET(x)            (((x) << VDDQ_SETTLE_TIME_REG_V_LSB) & VDDQ_SETTLE_TIME_REG_V_MASK)
+
+#define RD_STROBE_PW_REG_ADDRESS                 0x00000014
+#define RD_STROBE_PW_REG_OFFSET                  0x00000014
+#define RD_STROBE_PW_REG_V_MSB                   31
+#define RD_STROBE_PW_REG_V_LSB                   0
+#define RD_STROBE_PW_REG_V_MASK                  0xffffffff
+#define RD_STROBE_PW_REG_V_GET(x)                (((x) & RD_STROBE_PW_REG_V_MASK) >> RD_STROBE_PW_REG_V_LSB)
+#define RD_STROBE_PW_REG_V_SET(x)                (((x) << RD_STROBE_PW_REG_V_LSB) & RD_STROBE_PW_REG_V_MASK)
+
+#define PG_STROBE_PW_REG_ADDRESS                 0x00000018
+#define PG_STROBE_PW_REG_OFFSET                  0x00000018
+#define PG_STROBE_PW_REG_V_MSB                   31
+#define PG_STROBE_PW_REG_V_LSB                   0
+#define PG_STROBE_PW_REG_V_MASK                  0xffffffff
+#define PG_STROBE_PW_REG_V_GET(x)                (((x) & PG_STROBE_PW_REG_V_MASK) >> PG_STROBE_PW_REG_V_LSB)
+#define PG_STROBE_PW_REG_V_SET(x)                (((x) << PG_STROBE_PW_REG_V_LSB) & PG_STROBE_PW_REG_V_MASK)
+
+#define EFUSE_INTF_ADDRESS                       0x00000800
+#define EFUSE_INTF_OFFSET                        0x00000800
+#define EFUSE_INTF_R_MSB                         31
+#define EFUSE_INTF_R_LSB                         0
+#define EFUSE_INTF_R_MASK                        0xffffffff
+#define EFUSE_INTF_R_GET(x)                      (((x) & EFUSE_INTF_R_MASK) >> EFUSE_INTF_R_LSB)
+#define EFUSE_INTF_R_SET(x)                      (((x) << EFUSE_INTF_R_LSB) & EFUSE_INTF_R_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct efuse_reg_reg_s {
+  volatile unsigned int efuse_wr_enable_reg;
+  volatile unsigned int efuse_int_enable_reg;
+  volatile unsigned int efuse_int_status_reg;
+  volatile unsigned int bitmask_wr_reg;
+  volatile unsigned int vddq_settle_time_reg;
+  volatile unsigned int rd_strobe_pw_reg;
+  volatile unsigned int pg_strobe_pw_reg;
+  unsigned char pad0[2020]; /* pad to 0x800 */
+  volatile unsigned int efuse_intf[512];
+} efuse_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _EFUSE_REG_H_ */
diff --git a/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/gpio_athr_wlan_reg.h b/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/gpio_athr_wlan_reg.h
new file mode 100644
index 00000000000..1adee707de7
--- /dev/null
+++ b/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/gpio_athr_wlan_reg.h
@@ -0,0 +1,1253 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _GPIO_ATHR_WLAN_REG_REG_H_
+#define _GPIO_ATHR_WLAN_REG_REG_H_
+
+#define WLAN_GPIO_OUT_ADDRESS                    0x00000000
+#define WLAN_GPIO_OUT_OFFSET                     0x00000000
+#define WLAN_GPIO_OUT_DATA_MSB                   25
+#define WLAN_GPIO_OUT_DATA_LSB                   0
+#define WLAN_GPIO_OUT_DATA_MASK                  0x03ffffff
+#define WLAN_GPIO_OUT_DATA_GET(x)                (((x) & WLAN_GPIO_OUT_DATA_MASK) >> WLAN_GPIO_OUT_DATA_LSB)
+#define WLAN_GPIO_OUT_DATA_SET(x)                (((x) << WLAN_GPIO_OUT_DATA_LSB) & WLAN_GPIO_OUT_DATA_MASK)
+
+#define WLAN_GPIO_OUT_W1TS_ADDRESS               0x00000004
+#define WLAN_GPIO_OUT_W1TS_OFFSET                0x00000004
+#define WLAN_GPIO_OUT_W1TS_DATA_MSB              25
+#define WLAN_GPIO_OUT_W1TS_DATA_LSB              0
+#define WLAN_GPIO_OUT_W1TS_DATA_MASK             0x03ffffff
+#define WLAN_GPIO_OUT_W1TS_DATA_GET(x)           (((x) & WLAN_GPIO_OUT_W1TS_DATA_MASK) >> WLAN_GPIO_OUT_W1TS_DATA_LSB)
+#define WLAN_GPIO_OUT_W1TS_DATA_SET(x)           (((x) << WLAN_GPIO_OUT_W1TS_DATA_LSB) & WLAN_GPIO_OUT_W1TS_DATA_MASK)
+
+#define WLAN_GPIO_OUT_W1TC_ADDRESS               0x00000008
+#define WLAN_GPIO_OUT_W1TC_OFFSET                0x00000008
+#define WLAN_GPIO_OUT_W1TC_DATA_MSB              25
+#define WLAN_GPIO_OUT_W1TC_DATA_LSB              0
+#define WLAN_GPIO_OUT_W1TC_DATA_MASK             0x03ffffff
+#define WLAN_GPIO_OUT_W1TC_DATA_GET(x)           (((x) & WLAN_GPIO_OUT_W1TC_DATA_MASK) >> WLAN_GPIO_OUT_W1TC_DATA_LSB)
+#define WLAN_GPIO_OUT_W1TC_DATA_SET(x)           (((x) << WLAN_GPIO_OUT_W1TC_DATA_LSB) & WLAN_GPIO_OUT_W1TC_DATA_MASK)
+
+#define WLAN_GPIO_ENABLE_ADDRESS                 0x0000000c
+#define WLAN_GPIO_ENABLE_OFFSET                  0x0000000c
+#define WLAN_GPIO_ENABLE_DATA_MSB                25
+#define WLAN_GPIO_ENABLE_DATA_LSB                0
+#define WLAN_GPIO_ENABLE_DATA_MASK               0x03ffffff
+#define WLAN_GPIO_ENABLE_DATA_GET(x)             (((x) & WLAN_GPIO_ENABLE_DATA_MASK) >> WLAN_GPIO_ENABLE_DATA_LSB)
+#define WLAN_GPIO_ENABLE_DATA_SET(x)             (((x) << WLAN_GPIO_ENABLE_DATA_LSB) & WLAN_GPIO_ENABLE_DATA_MASK)
+
+#define WLAN_GPIO_ENABLE_W1TS_ADDRESS            0x00000010
+#define WLAN_GPIO_ENABLE_W1TS_OFFSET             0x00000010
+#define WLAN_GPIO_ENABLE_W1TS_DATA_MSB           25
+#define WLAN_GPIO_ENABLE_W1TS_DATA_LSB           0
+#define WLAN_GPIO_ENABLE_W1TS_DATA_MASK          0x03ffffff
+#define WLAN_GPIO_ENABLE_W1TS_DATA_GET(x)        (((x) & WLAN_GPIO_ENABLE_W1TS_DATA_MASK) >> WLAN_GPIO_ENABLE_W1TS_DATA_LSB)
+#define WLAN_GPIO_ENABLE_W1TS_DATA_SET(x)        (((x) << WLAN_GPIO_ENABLE_W1TS_DATA_LSB) & WLAN_GPIO_ENABLE_W1TS_DATA_MASK)
+
+#define WLAN_GPIO_ENABLE_W1TC_ADDRESS            0x00000014
+#define WLAN_GPIO_ENABLE_W1TC_OFFSET             0x00000014
+#define WLAN_GPIO_ENABLE_W1TC_DATA_MSB           25
+#define WLAN_GPIO_ENABLE_W1TC_DATA_LSB           0
+#define WLAN_GPIO_ENABLE_W1TC_DATA_MASK          0x03ffffff
+#define WLAN_GPIO_ENABLE_W1TC_DATA_GET(x)        (((x) & WLAN_GPIO_ENABLE_W1TC_DATA_MASK) >> WLAN_GPIO_ENABLE_W1TC_DATA_LSB)
+#define WLAN_GPIO_ENABLE_W1TC_DATA_SET(x)        (((x) << WLAN_GPIO_ENABLE_W1TC_DATA_LSB) & WLAN_GPIO_ENABLE_W1TC_DATA_MASK)
+
+#define WLAN_GPIO_IN_ADDRESS                     0x00000018
+#define WLAN_GPIO_IN_OFFSET                      0x00000018
+#define WLAN_GPIO_IN_DATA_MSB                    25
+#define WLAN_GPIO_IN_DATA_LSB                    0
+#define WLAN_GPIO_IN_DATA_MASK                   0x03ffffff
+#define WLAN_GPIO_IN_DATA_GET(x)                 (((x) & WLAN_GPIO_IN_DATA_MASK) >> WLAN_GPIO_IN_DATA_LSB)
+#define WLAN_GPIO_IN_DATA_SET(x)                 (((x) << WLAN_GPIO_IN_DATA_LSB) & WLAN_GPIO_IN_DATA_MASK)
+
+#define WLAN_GPIO_STATUS_ADDRESS                 0x0000001c
+#define WLAN_GPIO_STATUS_OFFSET                  0x0000001c
+#define WLAN_GPIO_STATUS_INTERRUPT_MSB           25
+#define WLAN_GPIO_STATUS_INTERRUPT_LSB           0
+#define WLAN_GPIO_STATUS_INTERRUPT_MASK          0x03ffffff
+#define WLAN_GPIO_STATUS_INTERRUPT_GET(x)        (((x) & WLAN_GPIO_STATUS_INTERRUPT_MASK) >> WLAN_GPIO_STATUS_INTERRUPT_LSB)
+#define WLAN_GPIO_STATUS_INTERRUPT_SET(x)        (((x) << WLAN_GPIO_STATUS_INTERRUPT_LSB) & WLAN_GPIO_STATUS_INTERRUPT_MASK)
+
+#define WLAN_GPIO_STATUS_W1TS_ADDRESS            0x00000020
+#define WLAN_GPIO_STATUS_W1TS_OFFSET             0x00000020
+#define WLAN_GPIO_STATUS_W1TS_INTERRUPT_MSB      25
+#define WLAN_GPIO_STATUS_W1TS_INTERRUPT_LSB      0
+#define WLAN_GPIO_STATUS_W1TS_INTERRUPT_MASK     0x03ffffff
+#define WLAN_GPIO_STATUS_W1TS_INTERRUPT_GET(x)   (((x) & WLAN_GPIO_STATUS_W1TS_INTERRUPT_MASK) >> WLAN_GPIO_STATUS_W1TS_INTERRUPT_LSB)
+#define WLAN_GPIO_STATUS_W1TS_INTERRUPT_SET(x)   (((x) << WLAN_GPIO_STATUS_W1TS_INTERRUPT_LSB) & WLAN_GPIO_STATUS_W1TS_INTERRUPT_MASK)
+
+#define WLAN_GPIO_STATUS_W1TC_ADDRESS            0x00000024
+#define WLAN_GPIO_STATUS_W1TC_OFFSET             0x00000024
+#define WLAN_GPIO_STATUS_W1TC_INTERRUPT_MSB      25
+#define WLAN_GPIO_STATUS_W1TC_INTERRUPT_LSB      0
+#define WLAN_GPIO_STATUS_W1TC_INTERRUPT_MASK     0x03ffffff
+#define WLAN_GPIO_STATUS_W1TC_INTERRUPT_GET(x)   (((x) & WLAN_GPIO_STATUS_W1TC_INTERRUPT_MASK) >> WLAN_GPIO_STATUS_W1TC_INTERRUPT_LSB)
+#define WLAN_GPIO_STATUS_W1TC_INTERRUPT_SET(x)   (((x) << WLAN_GPIO_STATUS_W1TC_INTERRUPT_LSB) & WLAN_GPIO_STATUS_W1TC_INTERRUPT_MASK)
+
+#define WLAN_GPIO_PIN0_ADDRESS                   0x00000028
+#define WLAN_GPIO_PIN0_OFFSET                    0x00000028
+#define WLAN_GPIO_PIN0_CONFIG_MSB                13
+#define WLAN_GPIO_PIN0_CONFIG_LSB                11
+#define WLAN_GPIO_PIN0_CONFIG_MASK               0x00003800
+#define WLAN_GPIO_PIN0_CONFIG_GET(x)             (((x) & WLAN_GPIO_PIN0_CONFIG_MASK) >> WLAN_GPIO_PIN0_CONFIG_LSB)
+#define WLAN_GPIO_PIN0_CONFIG_SET(x)             (((x) << WLAN_GPIO_PIN0_CONFIG_LSB) & WLAN_GPIO_PIN0_CONFIG_MASK)
+#define WLAN_GPIO_PIN0_WAKEUP_ENABLE_MSB         10
+#define WLAN_GPIO_PIN0_WAKEUP_ENABLE_LSB         10
+#define WLAN_GPIO_PIN0_WAKEUP_ENABLE_MASK        0x00000400
+#define WLAN_GPIO_PIN0_WAKEUP_ENABLE_GET(x)      (((x) & WLAN_GPIO_PIN0_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN0_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN0_WAKEUP_ENABLE_SET(x)      (((x) << WLAN_GPIO_PIN0_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN0_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN0_INT_TYPE_MSB              9
+#define WLAN_GPIO_PIN0_INT_TYPE_LSB              7
+#define WLAN_GPIO_PIN0_INT_TYPE_MASK             0x00000380
+#define WLAN_GPIO_PIN0_INT_TYPE_GET(x)           (((x) & WLAN_GPIO_PIN0_INT_TYPE_MASK) >> WLAN_GPIO_PIN0_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN0_INT_TYPE_SET(x)           (((x) << WLAN_GPIO_PIN0_INT_TYPE_LSB) & WLAN_GPIO_PIN0_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN0_PAD_PULL_MSB              6
+#define WLAN_GPIO_PIN0_PAD_PULL_LSB              5
+#define WLAN_GPIO_PIN0_PAD_PULL_MASK             0x00000060
+#define WLAN_GPIO_PIN0_PAD_PULL_GET(x)           (((x) & WLAN_GPIO_PIN0_PAD_PULL_MASK) >> WLAN_GPIO_PIN0_PAD_PULL_LSB)
+#define WLAN_GPIO_PIN0_PAD_PULL_SET(x)           (((x) << WLAN_GPIO_PIN0_PAD_PULL_LSB) & WLAN_GPIO_PIN0_PAD_PULL_MASK)
+#define WLAN_GPIO_PIN0_PAD_STRENGTH_MSB          4
+#define WLAN_GPIO_PIN0_PAD_STRENGTH_LSB          3
+#define WLAN_GPIO_PIN0_PAD_STRENGTH_MASK         0x00000018
+#define WLAN_GPIO_PIN0_PAD_STRENGTH_GET(x)       (((x) & WLAN_GPIO_PIN0_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN0_PAD_STRENGTH_LSB)
+#define WLAN_GPIO_PIN0_PAD_STRENGTH_SET(x)       (((x) << WLAN_GPIO_PIN0_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN0_PAD_STRENGTH_MASK)
+#define WLAN_GPIO_PIN0_PAD_DRIVER_MSB            2
+#define WLAN_GPIO_PIN0_PAD_DRIVER_LSB            2
+#define WLAN_GPIO_PIN0_PAD_DRIVER_MASK           0x00000004
+#define WLAN_GPIO_PIN0_PAD_DRIVER_GET(x)         (((x) & WLAN_GPIO_PIN0_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN0_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN0_PAD_DRIVER_SET(x)         (((x) << WLAN_GPIO_PIN0_PAD_DRIVER_LSB) & WLAN_GPIO_PIN0_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN0_SOURCE_MSB                0
+#define WLAN_GPIO_PIN0_SOURCE_LSB                0
+#define WLAN_GPIO_PIN0_SOURCE_MASK               0x00000001
+#define WLAN_GPIO_PIN0_SOURCE_GET(x)             (((x) & WLAN_GPIO_PIN0_SOURCE_MASK) >> WLAN_GPIO_PIN0_SOURCE_LSB)
+#define WLAN_GPIO_PIN0_SOURCE_SET(x)             (((x) << WLAN_GPIO_PIN0_SOURCE_LSB) & WLAN_GPIO_PIN0_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN1_ADDRESS                   0x0000002c
+#define WLAN_GPIO_PIN1_OFFSET                    0x0000002c
+#define WLAN_GPIO_PIN1_CONFIG_MSB                13
+#define WLAN_GPIO_PIN1_CONFIG_LSB                11
+#define WLAN_GPIO_PIN1_CONFIG_MASK               0x00003800
+#define WLAN_GPIO_PIN1_CONFIG_GET(x)             (((x) & WLAN_GPIO_PIN1_CONFIG_MASK) >> WLAN_GPIO_PIN1_CONFIG_LSB)
+#define WLAN_GPIO_PIN1_CONFIG_SET(x)             (((x) << WLAN_GPIO_PIN1_CONFIG_LSB) & WLAN_GPIO_PIN1_CONFIG_MASK)
+#define WLAN_GPIO_PIN1_WAKEUP_ENABLE_MSB         10
+#define WLAN_GPIO_PIN1_WAKEUP_ENABLE_LSB         10
+#define WLAN_GPIO_PIN1_WAKEUP_ENABLE_MASK        0x00000400
+#define WLAN_GPIO_PIN1_WAKEUP_ENABLE_GET(x)      (((x) & WLAN_GPIO_PIN1_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN1_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN1_WAKEUP_ENABLE_SET(x)      (((x) << WLAN_GPIO_PIN1_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN1_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN1_INT_TYPE_MSB              9
+#define WLAN_GPIO_PIN1_INT_TYPE_LSB              7
+#define WLAN_GPIO_PIN1_INT_TYPE_MASK             0x00000380
+#define WLAN_GPIO_PIN1_INT_TYPE_GET(x)           (((x) & WLAN_GPIO_PIN1_INT_TYPE_MASK) >> WLAN_GPIO_PIN1_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN1_INT_TYPE_SET(x)           (((x) << WLAN_GPIO_PIN1_INT_TYPE_LSB) & WLAN_GPIO_PIN1_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN1_PAD_PULL_MSB              6
+#define WLAN_GPIO_PIN1_PAD_PULL_LSB              5
+#define WLAN_GPIO_PIN1_PAD_PULL_MASK             0x00000060
+#define WLAN_GPIO_PIN1_PAD_PULL_GET(x)           (((x) & WLAN_GPIO_PIN1_PAD_PULL_MASK) >> WLAN_GPIO_PIN1_PAD_PULL_LSB)
+#define WLAN_GPIO_PIN1_PAD_PULL_SET(x)           (((x) << WLAN_GPIO_PIN1_PAD_PULL_LSB) & WLAN_GPIO_PIN1_PAD_PULL_MASK)
+#define WLAN_GPIO_PIN1_PAD_STRENGTH_MSB          4
+#define WLAN_GPIO_PIN1_PAD_STRENGTH_LSB          3
+#define WLAN_GPIO_PIN1_PAD_STRENGTH_MASK         0x00000018
+#define WLAN_GPIO_PIN1_PAD_STRENGTH_GET(x)       (((x) & WLAN_GPIO_PIN1_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN1_PAD_STRENGTH_LSB)
+#define WLAN_GPIO_PIN1_PAD_STRENGTH_SET(x)       (((x) << WLAN_GPIO_PIN1_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN1_PAD_STRENGTH_MASK)
+#define WLAN_GPIO_PIN1_PAD_DRIVER_MSB            2
+#define WLAN_GPIO_PIN1_PAD_DRIVER_LSB            2
+#define WLAN_GPIO_PIN1_PAD_DRIVER_MASK           0x00000004
+#define WLAN_GPIO_PIN1_PAD_DRIVER_GET(x)         (((x) & WLAN_GPIO_PIN1_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN1_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN1_PAD_DRIVER_SET(x)         (((x) << WLAN_GPIO_PIN1_PAD_DRIVER_LSB) & WLAN_GPIO_PIN1_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN1_SOURCE_MSB                0
+#define WLAN_GPIO_PIN1_SOURCE_LSB                0
+#define WLAN_GPIO_PIN1_SOURCE_MASK               0x00000001
+#define WLAN_GPIO_PIN1_SOURCE_GET(x)             (((x) & WLAN_GPIO_PIN1_SOURCE_MASK) >> WLAN_GPIO_PIN1_SOURCE_LSB)
+#define WLAN_GPIO_PIN1_SOURCE_SET(x)             (((x) << WLAN_GPIO_PIN1_SOURCE_LSB) & WLAN_GPIO_PIN1_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN2_ADDRESS                   0x00000030
+#define WLAN_GPIO_PIN2_OFFSET                    0x00000030
+#define WLAN_GPIO_PIN2_CONFIG_MSB                13
+#define WLAN_GPIO_PIN2_CONFIG_LSB                11
+#define WLAN_GPIO_PIN2_CONFIG_MASK               0x00003800
+#define WLAN_GPIO_PIN2_CONFIG_GET(x)             (((x) & WLAN_GPIO_PIN2_CONFIG_MASK) >> WLAN_GPIO_PIN2_CONFIG_LSB)
+#define WLAN_GPIO_PIN2_CONFIG_SET(x)             (((x) << WLAN_GPIO_PIN2_CONFIG_LSB) & WLAN_GPIO_PIN2_CONFIG_MASK)
+#define WLAN_GPIO_PIN2_WAKEUP_ENABLE_MSB         10
+#define WLAN_GPIO_PIN2_WAKEUP_ENABLE_LSB         10
+#define WLAN_GPIO_PIN2_WAKEUP_ENABLE_MASK        0x00000400
+#define WLAN_GPIO_PIN2_WAKEUP_ENABLE_GET(x)      (((x) & WLAN_GPIO_PIN2_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN2_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN2_WAKEUP_ENABLE_SET(x)      (((x) << WLAN_GPIO_PIN2_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN2_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN2_INT_TYPE_MSB              9
+#define WLAN_GPIO_PIN2_INT_TYPE_LSB              7
+#define WLAN_GPIO_PIN2_INT_TYPE_MASK             0x00000380
+#define WLAN_GPIO_PIN2_INT_TYPE_GET(x)           (((x) & WLAN_GPIO_PIN2_INT_TYPE_MASK) >> WLAN_GPIO_PIN2_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN2_INT_TYPE_SET(x)           (((x) << WLAN_GPIO_PIN2_INT_TYPE_LSB) & WLAN_GPIO_PIN2_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN2_PAD_PULL_MSB              6
+#define WLAN_GPIO_PIN2_PAD_PULL_LSB              5
+#define WLAN_GPIO_PIN2_PAD_PULL_MASK             0x00000060
+#define WLAN_GPIO_PIN2_PAD_PULL_GET(x)           (((x) & WLAN_GPIO_PIN2_PAD_PULL_MASK) >> WLAN_GPIO_PIN2_PAD_PULL_LSB)
+#define WLAN_GPIO_PIN2_PAD_PULL_SET(x)           (((x) << WLAN_GPIO_PIN2_PAD_PULL_LSB) & WLAN_GPIO_PIN2_PAD_PULL_MASK)
+#define WLAN_GPIO_PIN2_PAD_STRENGTH_MSB          4
+#define WLAN_GPIO_PIN2_PAD_STRENGTH_LSB          3
+#define WLAN_GPIO_PIN2_PAD_STRENGTH_MASK         0x00000018
+#define WLAN_GPIO_PIN2_PAD_STRENGTH_GET(x)       (((x) & WLAN_GPIO_PIN2_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN2_PAD_STRENGTH_LSB)
+#define WLAN_GPIO_PIN2_PAD_STRENGTH_SET(x)       (((x) << WLAN_GPIO_PIN2_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN2_PAD_STRENGTH_MASK)
+#define WLAN_GPIO_PIN2_PAD_DRIVER_MSB            2
+#define WLAN_GPIO_PIN2_PAD_DRIVER_LSB            2
+#define WLAN_GPIO_PIN2_PAD_DRIVER_MASK           0x00000004
+#define WLAN_GPIO_PIN2_PAD_DRIVER_GET(x)         (((x) & WLAN_GPIO_PIN2_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN2_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN2_PAD_DRIVER_SET(x)         (((x) << WLAN_GPIO_PIN2_PAD_DRIVER_LSB) & WLAN_GPIO_PIN2_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN2_SOURCE_MSB                0
+#define WLAN_GPIO_PIN2_SOURCE_LSB                0
+#define WLAN_GPIO_PIN2_SOURCE_MASK               0x00000001
+#define WLAN_GPIO_PIN2_SOURCE_GET(x)             (((x) & WLAN_GPIO_PIN2_SOURCE_MASK) >> WLAN_GPIO_PIN2_SOURCE_LSB)
+#define WLAN_GPIO_PIN2_SOURCE_SET(x)             (((x) << WLAN_GPIO_PIN2_SOURCE_LSB) & WLAN_GPIO_PIN2_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN3_ADDRESS                   0x00000034
+#define WLAN_GPIO_PIN3_OFFSET                    0x00000034
+#define WLAN_GPIO_PIN3_CONFIG_MSB                13
+#define WLAN_GPIO_PIN3_CONFIG_LSB                11
+#define WLAN_GPIO_PIN3_CONFIG_MASK               0x00003800
+#define WLAN_GPIO_PIN3_CONFIG_GET(x)             (((x) & WLAN_GPIO_PIN3_CONFIG_MASK) >> WLAN_GPIO_PIN3_CONFIG_LSB)
+#define WLAN_GPIO_PIN3_CONFIG_SET(x)             (((x) << WLAN_GPIO_PIN3_CONFIG_LSB) & WLAN_GPIO_PIN3_CONFIG_MASK)
+#define WLAN_GPIO_PIN3_WAKEUP_ENABLE_MSB         10
+#define WLAN_GPIO_PIN3_WAKEUP_ENABLE_LSB         10
+#define WLAN_GPIO_PIN3_WAKEUP_ENABLE_MASK        0x00000400
+#define WLAN_GPIO_PIN3_WAKEUP_ENABLE_GET(x)      (((x) & WLAN_GPIO_PIN3_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN3_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN3_WAKEUP_ENABLE_SET(x)      (((x) << WLAN_GPIO_PIN3_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN3_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN3_INT_TYPE_MSB              9
+#define WLAN_GPIO_PIN3_INT_TYPE_LSB              7
+#define WLAN_GPIO_PIN3_INT_TYPE_MASK             0x00000380
+#define WLAN_GPIO_PIN3_INT_TYPE_GET(x)           (((x) & WLAN_GPIO_PIN3_INT_TYPE_MASK) >> WLAN_GPIO_PIN3_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN3_INT_TYPE_SET(x)           (((x) << WLAN_GPIO_PIN3_INT_TYPE_LSB) & WLAN_GPIO_PIN3_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN3_PAD_PULL_MSB              6
+#define WLAN_GPIO_PIN3_PAD_PULL_LSB              5
+#define WLAN_GPIO_PIN3_PAD_PULL_MASK             0x00000060
+#define WLAN_GPIO_PIN3_PAD_PULL_GET(x)           (((x) & WLAN_GPIO_PIN3_PAD_PULL_MASK) >> WLAN_GPIO_PIN3_PAD_PULL_LSB)
+#define WLAN_GPIO_PIN3_PAD_PULL_SET(x)           (((x) << WLAN_GPIO_PIN3_PAD_PULL_LSB) & WLAN_GPIO_PIN3_PAD_PULL_MASK)
+#define WLAN_GPIO_PIN3_PAD_STRENGTH_MSB          4
+#define WLAN_GPIO_PIN3_PAD_STRENGTH_LSB          3
+#define WLAN_GPIO_PIN3_PAD_STRENGTH_MASK         0x00000018
+#define WLAN_GPIO_PIN3_PAD_STRENGTH_GET(x)       (((x) & WLAN_GPIO_PIN3_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN3_PAD_STRENGTH_LSB)
+#define WLAN_GPIO_PIN3_PAD_STRENGTH_SET(x)       (((x) << WLAN_GPIO_PIN3_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN3_PAD_STRENGTH_MASK)
+#define WLAN_GPIO_PIN3_PAD_DRIVER_MSB            2
+#define WLAN_GPIO_PIN3_PAD_DRIVER_LSB            2
+#define WLAN_GPIO_PIN3_PAD_DRIVER_MASK           0x00000004
+#define WLAN_GPIO_PIN3_PAD_DRIVER_GET(x)         (((x) & WLAN_GPIO_PIN3_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN3_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN3_PAD_DRIVER_SET(x)         (((x) << WLAN_GPIO_PIN3_PAD_DRIVER_LSB) & WLAN_GPIO_PIN3_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN3_SOURCE_MSB                0
+#define WLAN_GPIO_PIN3_SOURCE_LSB                0
+#define WLAN_GPIO_PIN3_SOURCE_MASK               0x00000001
+#define WLAN_GPIO_PIN3_SOURCE_GET(x)             (((x) & WLAN_GPIO_PIN3_SOURCE_MASK) >> WLAN_GPIO_PIN3_SOURCE_LSB)
+#define WLAN_GPIO_PIN3_SOURCE_SET(x)             (((x) << WLAN_GPIO_PIN3_SOURCE_LSB) & WLAN_GPIO_PIN3_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN4_ADDRESS                   0x00000038
+#define WLAN_GPIO_PIN4_OFFSET                    0x00000038
+#define WLAN_GPIO_PIN4_CONFIG_MSB                13
+#define WLAN_GPIO_PIN4_CONFIG_LSB                11
+#define WLAN_GPIO_PIN4_CONFIG_MASK               0x00003800
+#define WLAN_GPIO_PIN4_CONFIG_GET(x)             (((x) & WLAN_GPIO_PIN4_CONFIG_MASK) >> WLAN_GPIO_PIN4_CONFIG_LSB)
+#define WLAN_GPIO_PIN4_CONFIG_SET(x)             (((x) << WLAN_GPIO_PIN4_CONFIG_LSB) & WLAN_GPIO_PIN4_CONFIG_MASK)
+#define WLAN_GPIO_PIN4_WAKEUP_ENABLE_MSB         10
+#define WLAN_GPIO_PIN4_WAKEUP_ENABLE_LSB         10
+#define WLAN_GPIO_PIN4_WAKEUP_ENABLE_MASK        0x00000400
+#define WLAN_GPIO_PIN4_WAKEUP_ENABLE_GET(x)      (((x) & WLAN_GPIO_PIN4_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN4_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN4_WAKEUP_ENABLE_SET(x)      (((x) << WLAN_GPIO_PIN4_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN4_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN4_INT_TYPE_MSB              9
+#define WLAN_GPIO_PIN4_INT_TYPE_LSB              7
+#define WLAN_GPIO_PIN4_INT_TYPE_MASK             0x00000380
+#define WLAN_GPIO_PIN4_INT_TYPE_GET(x)           (((x) & WLAN_GPIO_PIN4_INT_TYPE_MASK) >> WLAN_GPIO_PIN4_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN4_INT_TYPE_SET(x)           (((x) << WLAN_GPIO_PIN4_INT_TYPE_LSB) & WLAN_GPIO_PIN4_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN4_PAD_PULL_MSB              6
+#define WLAN_GPIO_PIN4_PAD_PULL_LSB              5
+#define WLAN_GPIO_PIN4_PAD_PULL_MASK             0x00000060
+#define WLAN_GPIO_PIN4_PAD_PULL_GET(x)           (((x) & WLAN_GPIO_PIN4_PAD_PULL_MASK) >> WLAN_GPIO_PIN4_PAD_PULL_LSB)
+#define WLAN_GPIO_PIN4_PAD_PULL_SET(x)           (((x) << WLAN_GPIO_PIN4_PAD_PULL_LSB) & WLAN_GPIO_PIN4_PAD_PULL_MASK)
+#define WLAN_GPIO_PIN4_PAD_STRENGTH_MSB          4
+#define WLAN_GPIO_PIN4_PAD_STRENGTH_LSB          3
+#define WLAN_GPIO_PIN4_PAD_STRENGTH_MASK         0x00000018
+#define WLAN_GPIO_PIN4_PAD_STRENGTH_GET(x)       (((x) & WLAN_GPIO_PIN4_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN4_PAD_STRENGTH_LSB)
+#define WLAN_GPIO_PIN4_PAD_STRENGTH_SET(x)       (((x) << WLAN_GPIO_PIN4_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN4_PAD_STRENGTH_MASK)
+#define WLAN_GPIO_PIN4_PAD_DRIVER_MSB            2
+#define WLAN_GPIO_PIN4_PAD_DRIVER_LSB            2
+#define WLAN_GPIO_PIN4_PAD_DRIVER_MASK           0x00000004
+#define WLAN_GPIO_PIN4_PAD_DRIVER_GET(x)         (((x) & WLAN_GPIO_PIN4_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN4_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN4_PAD_DRIVER_SET(x)         (((x) << WLAN_GPIO_PIN4_PAD_DRIVER_LSB) & WLAN_GPIO_PIN4_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN4_SOURCE_MSB                0
+#define WLAN_GPIO_PIN4_SOURCE_LSB                0
+#define WLAN_GPIO_PIN4_SOURCE_MASK               0x00000001
+#define WLAN_GPIO_PIN4_SOURCE_GET(x)             (((x) & WLAN_GPIO_PIN4_SOURCE_MASK) >> WLAN_GPIO_PIN4_SOURCE_LSB)
+#define WLAN_GPIO_PIN4_SOURCE_SET(x)             (((x) << WLAN_GPIO_PIN4_SOURCE_LSB) & WLAN_GPIO_PIN4_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN5_ADDRESS                   0x0000003c
+#define WLAN_GPIO_PIN5_OFFSET                    0x0000003c
+#define WLAN_GPIO_PIN5_CONFIG_MSB                13
+#define WLAN_GPIO_PIN5_CONFIG_LSB                11
+#define WLAN_GPIO_PIN5_CONFIG_MASK               0x00003800
+#define WLAN_GPIO_PIN5_CONFIG_GET(x)             (((x) & WLAN_GPIO_PIN5_CONFIG_MASK) >> WLAN_GPIO_PIN5_CONFIG_LSB)
+#define WLAN_GPIO_PIN5_CONFIG_SET(x)             (((x) << WLAN_GPIO_PIN5_CONFIG_LSB) & WLAN_GPIO_PIN5_CONFIG_MASK)
+#define WLAN_GPIO_PIN5_WAKEUP_ENABLE_MSB         10
+#define WLAN_GPIO_PIN5_WAKEUP_ENABLE_LSB         10
+#define WLAN_GPIO_PIN5_WAKEUP_ENABLE_MASK        0x00000400
+#define WLAN_GPIO_PIN5_WAKEUP_ENABLE_GET(x)      (((x) & WLAN_GPIO_PIN5_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN5_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN5_WAKEUP_ENABLE_SET(x)      (((x) << WLAN_GPIO_PIN5_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN5_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN5_INT_TYPE_MSB              9
+#define WLAN_GPIO_PIN5_INT_TYPE_LSB              7
+#define WLAN_GPIO_PIN5_INT_TYPE_MASK             0x00000380
+#define WLAN_GPIO_PIN5_INT_TYPE_GET(x)           (((x) & WLAN_GPIO_PIN5_INT_TYPE_MASK) >> WLAN_GPIO_PIN5_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN5_INT_TYPE_SET(x)           (((x) << WLAN_GPIO_PIN5_INT_TYPE_LSB) & WLAN_GPIO_PIN5_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN5_PAD_PULL_MSB              6
+#define WLAN_GPIO_PIN5_PAD_PULL_LSB              5
+#define WLAN_GPIO_PIN5_PAD_PULL_MASK             0x00000060
+#define WLAN_GPIO_PIN5_PAD_PULL_GET(x)           (((x) & WLAN_GPIO_PIN5_PAD_PULL_MASK) >> WLAN_GPIO_PIN5_PAD_PULL_LSB)
+#define WLAN_GPIO_PIN5_PAD_PULL_SET(x)           (((x) << WLAN_GPIO_PIN5_PAD_PULL_LSB) & WLAN_GPIO_PIN5_PAD_PULL_MASK)
+#define WLAN_GPIO_PIN5_PAD_STRENGTH_MSB          4
+#define WLAN_GPIO_PIN5_PAD_STRENGTH_LSB          3
+#define WLAN_GPIO_PIN5_PAD_STRENGTH_MASK         0x00000018
+#define WLAN_GPIO_PIN5_PAD_STRENGTH_GET(x)       (((x) & WLAN_GPIO_PIN5_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN5_PAD_STRENGTH_LSB)
+#define WLAN_GPIO_PIN5_PAD_STRENGTH_SET(x)       (((x) << WLAN_GPIO_PIN5_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN5_PAD_STRENGTH_MASK)
+#define WLAN_GPIO_PIN5_PAD_DRIVER_MSB            2
+#define WLAN_GPIO_PIN5_PAD_DRIVER_LSB            2
+#define WLAN_GPIO_PIN5_PAD_DRIVER_MASK           0x00000004
+#define WLAN_GPIO_PIN5_PAD_DRIVER_GET(x)         (((x) & WLAN_GPIO_PIN5_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN5_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN5_PAD_DRIVER_SET(x)         (((x) << WLAN_GPIO_PIN5_PAD_DRIVER_LSB) & WLAN_GPIO_PIN5_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN5_SOURCE_MSB                0
+#define WLAN_GPIO_PIN5_SOURCE_LSB                0
+#define WLAN_GPIO_PIN5_SOURCE_MASK               0x00000001
+#define WLAN_GPIO_PIN5_SOURCE_GET(x)             (((x) & WLAN_GPIO_PIN5_SOURCE_MASK) >> WLAN_GPIO_PIN5_SOURCE_LSB)
+#define WLAN_GPIO_PIN5_SOURCE_SET(x)             (((x) << WLAN_GPIO_PIN5_SOURCE_LSB) & WLAN_GPIO_PIN5_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN6_ADDRESS                   0x00000040
+#define WLAN_GPIO_PIN6_OFFSET                    0x00000040
+#define WLAN_GPIO_PIN6_CONFIG_MSB                13
+#define WLAN_GPIO_PIN6_CONFIG_LSB                11
+#define WLAN_GPIO_PIN6_CONFIG_MASK               0x00003800
+#define WLAN_GPIO_PIN6_CONFIG_GET(x)             (((x) & WLAN_GPIO_PIN6_CONFIG_MASK) >> WLAN_GPIO_PIN6_CONFIG_LSB)
+#define WLAN_GPIO_PIN6_CONFIG_SET(x)             (((x) << WLAN_GPIO_PIN6_CONFIG_LSB) & WLAN_GPIO_PIN6_CONFIG_MASK)
+#define WLAN_GPIO_PIN6_WAKEUP_ENABLE_MSB         10
+#define WLAN_GPIO_PIN6_WAKEUP_ENABLE_LSB         10
+#define WLAN_GPIO_PIN6_WAKEUP_ENABLE_MASK        0x00000400
+#define WLAN_GPIO_PIN6_WAKEUP_ENABLE_GET(x)      (((x) & WLAN_GPIO_PIN6_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN6_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN6_WAKEUP_ENABLE_SET(x)      (((x) << WLAN_GPIO_PIN6_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN6_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN6_INT_TYPE_MSB              9
+#define WLAN_GPIO_PIN6_INT_TYPE_LSB              7
+#define WLAN_GPIO_PIN6_INT_TYPE_MASK             0x00000380
+#define WLAN_GPIO_PIN6_INT_TYPE_GET(x)           (((x) & WLAN_GPIO_PIN6_INT_TYPE_MASK) >> WLAN_GPIO_PIN6_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN6_INT_TYPE_SET(x)           (((x) << WLAN_GPIO_PIN6_INT_TYPE_LSB) & WLAN_GPIO_PIN6_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN6_PAD_PULL_MSB              6
+#define WLAN_GPIO_PIN6_PAD_PULL_LSB              5
+#define WLAN_GPIO_PIN6_PAD_PULL_MASK             0x00000060
+#define WLAN_GPIO_PIN6_PAD_PULL_GET(x)           (((x) & WLAN_GPIO_PIN6_PAD_PULL_MASK) >> WLAN_GPIO_PIN6_PAD_PULL_LSB)
+#define WLAN_GPIO_PIN6_PAD_PULL_SET(x)           (((x) << WLAN_GPIO_PIN6_PAD_PULL_LSB) & WLAN_GPIO_PIN6_PAD_PULL_MASK)
+#define WLAN_GPIO_PIN6_PAD_STRENGTH_MSB          4
+#define WLAN_GPIO_PIN6_PAD_STRENGTH_LSB          3
+#define WLAN_GPIO_PIN6_PAD_STRENGTH_MASK         0x00000018
+#define WLAN_GPIO_PIN6_PAD_STRENGTH_GET(x)       (((x) & WLAN_GPIO_PIN6_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN6_PAD_STRENGTH_LSB)
+#define WLAN_GPIO_PIN6_PAD_STRENGTH_SET(x)       (((x) << WLAN_GPIO_PIN6_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN6_PAD_STRENGTH_MASK)
+#define WLAN_GPIO_PIN6_PAD_DRIVER_MSB            2
+#define WLAN_GPIO_PIN6_PAD_DRIVER_LSB            2
+#define WLAN_GPIO_PIN6_PAD_DRIVER_MASK           0x00000004
+#define WLAN_GPIO_PIN6_PAD_DRIVER_GET(x)         (((x) & WLAN_GPIO_PIN6_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN6_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN6_PAD_DRIVER_SET(x)         (((x) << WLAN_GPIO_PIN6_PAD_DRIVER_LSB) & WLAN_GPIO_PIN6_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN6_SOURCE_MSB                0
+#define WLAN_GPIO_PIN6_SOURCE_LSB                0
+#define WLAN_GPIO_PIN6_SOURCE_MASK               0x00000001
+#define WLAN_GPIO_PIN6_SOURCE_GET(x)             (((x) & WLAN_GPIO_PIN6_SOURCE_MASK) >> WLAN_GPIO_PIN6_SOURCE_LSB)
+#define WLAN_GPIO_PIN6_SOURCE_SET(x)             (((x) << WLAN_GPIO_PIN6_SOURCE_LSB) & WLAN_GPIO_PIN6_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN7_ADDRESS                   0x00000044
+#define WLAN_GPIO_PIN7_OFFSET                    0x00000044
+#define WLAN_GPIO_PIN7_CONFIG_MSB                13
+#define WLAN_GPIO_PIN7_CONFIG_LSB                11
+#define WLAN_GPIO_PIN7_CONFIG_MASK               0x00003800
+#define WLAN_GPIO_PIN7_CONFIG_GET(x)             (((x) & WLAN_GPIO_PIN7_CONFIG_MASK) >> WLAN_GPIO_PIN7_CONFIG_LSB)
+#define WLAN_GPIO_PIN7_CONFIG_SET(x)             (((x) << WLAN_GPIO_PIN7_CONFIG_LSB) & WLAN_GPIO_PIN7_CONFIG_MASK)
+#define WLAN_GPIO_PIN7_WAKEUP_ENABLE_MSB         10
+#define WLAN_GPIO_PIN7_WAKEUP_ENABLE_LSB         10
+#define WLAN_GPIO_PIN7_WAKEUP_ENABLE_MASK        0x00000400
+#define WLAN_GPIO_PIN7_WAKEUP_ENABLE_GET(x)      (((x) & WLAN_GPIO_PIN7_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN7_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN7_WAKEUP_ENABLE_SET(x)      (((x) << WLAN_GPIO_PIN7_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN7_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN7_INT_TYPE_MSB              9
+#define WLAN_GPIO_PIN7_INT_TYPE_LSB              7
+#define WLAN_GPIO_PIN7_INT_TYPE_MASK             0x00000380
+#define WLAN_GPIO_PIN7_INT_TYPE_GET(x)           (((x) & WLAN_GPIO_PIN7_INT_TYPE_MASK) >> WLAN_GPIO_PIN7_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN7_INT_TYPE_SET(x)           (((x) << WLAN_GPIO_PIN7_INT_TYPE_LSB) & WLAN_GPIO_PIN7_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN7_PAD_PULL_MSB              6
+#define WLAN_GPIO_PIN7_PAD_PULL_LSB              5
+#define WLAN_GPIO_PIN7_PAD_PULL_MASK             0x00000060
+#define WLAN_GPIO_PIN7_PAD_PULL_GET(x)           (((x) & WLAN_GPIO_PIN7_PAD_PULL_MASK) >> WLAN_GPIO_PIN7_PAD_PULL_LSB)
+#define WLAN_GPIO_PIN7_PAD_PULL_SET(x)           (((x) << WLAN_GPIO_PIN7_PAD_PULL_LSB) & WLAN_GPIO_PIN7_PAD_PULL_MASK)
+#define WLAN_GPIO_PIN7_PAD_STRENGTH_MSB          4
+#define WLAN_GPIO_PIN7_PAD_STRENGTH_LSB          3
+#define WLAN_GPIO_PIN7_PAD_STRENGTH_MASK         0x00000018
+#define WLAN_GPIO_PIN7_PAD_STRENGTH_GET(x)       (((x) & WLAN_GPIO_PIN7_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN7_PAD_STRENGTH_LSB)
+#define WLAN_GPIO_PIN7_PAD_STRENGTH_SET(x)       (((x) << WLAN_GPIO_PIN7_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN7_PAD_STRENGTH_MASK)
+#define WLAN_GPIO_PIN7_PAD_DRIVER_MSB            2
+#define WLAN_GPIO_PIN7_PAD_DRIVER_LSB            2
+#define WLAN_GPIO_PIN7_PAD_DRIVER_MASK           0x00000004
+#define WLAN_GPIO_PIN7_PAD_DRIVER_GET(x)         (((x) & WLAN_GPIO_PIN7_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN7_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN7_PAD_DRIVER_SET(x)         (((x) << WLAN_GPIO_PIN7_PAD_DRIVER_LSB) & WLAN_GPIO_PIN7_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN7_SOURCE_MSB                0
+#define WLAN_GPIO_PIN7_SOURCE_LSB                0
+#define WLAN_GPIO_PIN7_SOURCE_MASK               0x00000001
+#define WLAN_GPIO_PIN7_SOURCE_GET(x)             (((x) & WLAN_GPIO_PIN7_SOURCE_MASK) >> WLAN_GPIO_PIN7_SOURCE_LSB)
+#define WLAN_GPIO_PIN7_SOURCE_SET(x)             (((x) << WLAN_GPIO_PIN7_SOURCE_LSB) & WLAN_GPIO_PIN7_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN8_ADDRESS                   0x00000048
+#define WLAN_GPIO_PIN8_OFFSET                    0x00000048
+#define WLAN_GPIO_PIN8_CONFIG_MSB                13
+#define WLAN_GPIO_PIN8_CONFIG_LSB                11
+#define WLAN_GPIO_PIN8_CONFIG_MASK               0x00003800
+#define WLAN_GPIO_PIN8_CONFIG_GET(x)             (((x) & WLAN_GPIO_PIN8_CONFIG_MASK) >> WLAN_GPIO_PIN8_CONFIG_LSB)
+#define WLAN_GPIO_PIN8_CONFIG_SET(x)             (((x) << WLAN_GPIO_PIN8_CONFIG_LSB) & WLAN_GPIO_PIN8_CONFIG_MASK)
+#define WLAN_GPIO_PIN8_WAKEUP_ENABLE_MSB         10
+#define WLAN_GPIO_PIN8_WAKEUP_ENABLE_LSB         10
+#define WLAN_GPIO_PIN8_WAKEUP_ENABLE_MASK        0x00000400
+#define WLAN_GPIO_PIN8_WAKEUP_ENABLE_GET(x)      (((x) & WLAN_GPIO_PIN8_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN8_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN8_WAKEUP_ENABLE_SET(x)      (((x) << WLAN_GPIO_PIN8_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN8_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN8_INT_TYPE_MSB              9
+#define WLAN_GPIO_PIN8_INT_TYPE_LSB              7
+#define WLAN_GPIO_PIN8_INT_TYPE_MASK             0x00000380
+#define WLAN_GPIO_PIN8_INT_TYPE_GET(x)           (((x) & WLAN_GPIO_PIN8_INT_TYPE_MASK) >> WLAN_GPIO_PIN8_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN8_INT_TYPE_SET(x)           (((x) << WLAN_GPIO_PIN8_INT_TYPE_LSB) & WLAN_GPIO_PIN8_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN8_PAD_PULL_MSB              6
+#define WLAN_GPIO_PIN8_PAD_PULL_LSB              5
+#define WLAN_GPIO_PIN8_PAD_PULL_MASK             0x00000060
+#define WLAN_GPIO_PIN8_PAD_PULL_GET(x)           (((x) & WLAN_GPIO_PIN8_PAD_PULL_MASK) >> WLAN_GPIO_PIN8_PAD_PULL_LSB)
+#define WLAN_GPIO_PIN8_PAD_PULL_SET(x)           (((x) << WLAN_GPIO_PIN8_PAD_PULL_LSB) & WLAN_GPIO_PIN8_PAD_PULL_MASK)
+#define WLAN_GPIO_PIN8_PAD_STRENGTH_MSB          4
+#define WLAN_GPIO_PIN8_PAD_STRENGTH_LSB          3
+#define WLAN_GPIO_PIN8_PAD_STRENGTH_MASK         0x00000018
+#define WLAN_GPIO_PIN8_PAD_STRENGTH_GET(x)       (((x) & WLAN_GPIO_PIN8_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN8_PAD_STRENGTH_LSB)
+#define WLAN_GPIO_PIN8_PAD_STRENGTH_SET(x)       (((x) << WLAN_GPIO_PIN8_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN8_PAD_STRENGTH_MASK)
+#define WLAN_GPIO_PIN8_PAD_DRIVER_MSB            2
+#define WLAN_GPIO_PIN8_PAD_DRIVER_LSB            2
+#define WLAN_GPIO_PIN8_PAD_DRIVER_MASK           0x00000004
+#define WLAN_GPIO_PIN8_PAD_DRIVER_GET(x)         (((x) & WLAN_GPIO_PIN8_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN8_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN8_PAD_DRIVER_SET(x)         (((x) << WLAN_GPIO_PIN8_PAD_DRIVER_LSB) & WLAN_GPIO_PIN8_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN8_SOURCE_MSB                0
+#define WLAN_GPIO_PIN8_SOURCE_LSB                0
+#define WLAN_GPIO_PIN8_SOURCE_MASK               0x00000001
+#define WLAN_GPIO_PIN8_SOURCE_GET(x)             (((x) & WLAN_GPIO_PIN8_SOURCE_MASK) >> WLAN_GPIO_PIN8_SOURCE_LSB)
+#define WLAN_GPIO_PIN8_SOURCE_SET(x)             (((x) << WLAN_GPIO_PIN8_SOURCE_LSB) & WLAN_GPIO_PIN8_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN9_ADDRESS                   0x0000004c
+#define WLAN_GPIO_PIN9_OFFSET                    0x0000004c
+#define WLAN_GPIO_PIN9_CONFIG_MSB                13
+#define WLAN_GPIO_PIN9_CONFIG_LSB                11
+#define WLAN_GPIO_PIN9_CONFIG_MASK               0x00003800
+#define WLAN_GPIO_PIN9_CONFIG_GET(x)             (((x) & WLAN_GPIO_PIN9_CONFIG_MASK) >> WLAN_GPIO_PIN9_CONFIG_LSB)
+#define WLAN_GPIO_PIN9_CONFIG_SET(x)             (((x) << WLAN_GPIO_PIN9_CONFIG_LSB) & WLAN_GPIO_PIN9_CONFIG_MASK)
+#define WLAN_GPIO_PIN9_WAKEUP_ENABLE_MSB         10
+#define WLAN_GPIO_PIN9_WAKEUP_ENABLE_LSB         10
+#define WLAN_GPIO_PIN9_WAKEUP_ENABLE_MASK        0x00000400
+#define WLAN_GPIO_PIN9_WAKEUP_ENABLE_GET(x)      (((x) & WLAN_GPIO_PIN9_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN9_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN9_WAKEUP_ENABLE_SET(x)      (((x) << WLAN_GPIO_PIN9_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN9_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN9_INT_TYPE_MSB              9
+#define WLAN_GPIO_PIN9_INT_TYPE_LSB              7
+#define WLAN_GPIO_PIN9_INT_TYPE_MASK             0x00000380
+#define WLAN_GPIO_PIN9_INT_TYPE_GET(x)           (((x) & WLAN_GPIO_PIN9_INT_TYPE_MASK) >> WLAN_GPIO_PIN9_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN9_INT_TYPE_SET(x)           (((x) << WLAN_GPIO_PIN9_INT_TYPE_LSB) & WLAN_GPIO_PIN9_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN9_PAD_PULL_MSB              6
+#define WLAN_GPIO_PIN9_PAD_PULL_LSB              5
+#define WLAN_GPIO_PIN9_PAD_PULL_MASK             0x00000060
+#define WLAN_GPIO_PIN9_PAD_PULL_GET(x)           (((x) & WLAN_GPIO_PIN9_PAD_PULL_MASK) >> WLAN_GPIO_PIN9_PAD_PULL_LSB)
+#define WLAN_GPIO_PIN9_PAD_PULL_SET(x)           (((x) << WLAN_GPIO_PIN9_PAD_PULL_LSB) & WLAN_GPIO_PIN9_PAD_PULL_MASK)
+#define WLAN_GPIO_PIN9_PAD_STRENGTH_MSB          4
+#define WLAN_GPIO_PIN9_PAD_STRENGTH_LSB          3
+#define WLAN_GPIO_PIN9_PAD_STRENGTH_MASK         0x00000018
+#define WLAN_GPIO_PIN9_PAD_STRENGTH_GET(x)       (((x) & WLAN_GPIO_PIN9_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN9_PAD_STRENGTH_LSB)
+#define WLAN_GPIO_PIN9_PAD_STRENGTH_SET(x)       (((x) << WLAN_GPIO_PIN9_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN9_PAD_STRENGTH_MASK)
+#define WLAN_GPIO_PIN9_PAD_DRIVER_MSB            2
+#define WLAN_GPIO_PIN9_PAD_DRIVER_LSB            2
+#define WLAN_GPIO_PIN9_PAD_DRIVER_MASK           0x00000004
+#define WLAN_GPIO_PIN9_PAD_DRIVER_GET(x)         (((x) & WLAN_GPIO_PIN9_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN9_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN9_PAD_DRIVER_SET(x)         (((x) << WLAN_GPIO_PIN9_PAD_DRIVER_LSB) & WLAN_GPIO_PIN9_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN9_SOURCE_MSB                0
+#define WLAN_GPIO_PIN9_SOURCE_LSB                0
+#define WLAN_GPIO_PIN9_SOURCE_MASK               0x00000001
+#define WLAN_GPIO_PIN9_SOURCE_GET(x)             (((x) & WLAN_GPIO_PIN9_SOURCE_MASK) >> WLAN_GPIO_PIN9_SOURCE_LSB)
+#define WLAN_GPIO_PIN9_SOURCE_SET(x)             (((x) << WLAN_GPIO_PIN9_SOURCE_LSB) & WLAN_GPIO_PIN9_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN10_ADDRESS                  0x00000050
+#define WLAN_GPIO_PIN10_OFFSET                   0x00000050
+#define WLAN_GPIO_PIN10_CONFIG_MSB               13
+#define WLAN_GPIO_PIN10_CONFIG_LSB               11
+#define WLAN_GPIO_PIN10_CONFIG_MASK              0x00003800
+#define WLAN_GPIO_PIN10_CONFIG_GET(x)            (((x) & WLAN_GPIO_PIN10_CONFIG_MASK) >> WLAN_GPIO_PIN10_CONFIG_LSB)
+#define WLAN_GPIO_PIN10_CONFIG_SET(x)            (((x) << WLAN_GPIO_PIN10_CONFIG_LSB) & WLAN_GPIO_PIN10_CONFIG_MASK)
+#define WLAN_GPIO_PIN10_WAKEUP_ENABLE_MSB        10
+#define WLAN_GPIO_PIN10_WAKEUP_ENABLE_LSB        10
+#define WLAN_GPIO_PIN10_WAKEUP_ENABLE_MASK       0x00000400
+#define WLAN_GPIO_PIN10_WAKEUP_ENABLE_GET(x)     (((x) & WLAN_GPIO_PIN10_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN10_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN10_WAKEUP_ENABLE_SET(x)     (((x) << WLAN_GPIO_PIN10_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN10_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN10_INT_TYPE_MSB             9
+#define WLAN_GPIO_PIN10_INT_TYPE_LSB             7
+#define WLAN_GPIO_PIN10_INT_TYPE_MASK            0x00000380
+#define WLAN_GPIO_PIN10_INT_TYPE_GET(x)          (((x) & WLAN_GPIO_PIN10_INT_TYPE_MASK) >> WLAN_GPIO_PIN10_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN10_INT_TYPE_SET(x)          (((x) << WLAN_GPIO_PIN10_INT_TYPE_LSB) & WLAN_GPIO_PIN10_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN10_PAD_PULL_MSB             6
+#define WLAN_GPIO_PIN10_PAD_PULL_LSB             5
+#define WLAN_GPIO_PIN10_PAD_PULL_MASK            0x00000060
+#define WLAN_GPIO_PIN10_PAD_PULL_GET(x)          (((x) & WLAN_GPIO_PIN10_PAD_PULL_MASK) >> WLAN_GPIO_PIN10_PAD_PULL_LSB)
+#define WLAN_GPIO_PIN10_PAD_PULL_SET(x)          (((x) << WLAN_GPIO_PIN10_PAD_PULL_LSB) & WLAN_GPIO_PIN10_PAD_PULL_MASK)
+#define WLAN_GPIO_PIN10_PAD_STRENGTH_MSB         4
+#define WLAN_GPIO_PIN10_PAD_STRENGTH_LSB         3
+#define WLAN_GPIO_PIN10_PAD_STRENGTH_MASK        0x00000018
+#define WLAN_GPIO_PIN10_PAD_STRENGTH_GET(x)      (((x) & WLAN_GPIO_PIN10_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN10_PAD_STRENGTH_LSB)
+#define WLAN_GPIO_PIN10_PAD_STRENGTH_SET(x)      (((x) << WLAN_GPIO_PIN10_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN10_PAD_STRENGTH_MASK)
+#define WLAN_GPIO_PIN10_PAD_DRIVER_MSB           2
+#define WLAN_GPIO_PIN10_PAD_DRIVER_LSB           2
+#define WLAN_GPIO_PIN10_PAD_DRIVER_MASK          0x00000004
+#define WLAN_GPIO_PIN10_PAD_DRIVER_GET(x)        (((x) & WLAN_GPIO_PIN10_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN10_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN10_PAD_DRIVER_SET(x)        (((x) << WLAN_GPIO_PIN10_PAD_DRIVER_LSB) & WLAN_GPIO_PIN10_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN10_SOURCE_MSB               0
+#define WLAN_GPIO_PIN10_SOURCE_LSB               0
+#define WLAN_GPIO_PIN10_SOURCE_MASK              0x00000001
+#define WLAN_GPIO_PIN10_SOURCE_GET(x)            (((x) & WLAN_GPIO_PIN10_SOURCE_MASK) >> WLAN_GPIO_PIN10_SOURCE_LSB)
+#define WLAN_GPIO_PIN10_SOURCE_SET(x)            (((x) << WLAN_GPIO_PIN10_SOURCE_LSB) & WLAN_GPIO_PIN10_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN11_ADDRESS                  0x00000054
+#define WLAN_GPIO_PIN11_OFFSET                   0x00000054
+#define WLAN_GPIO_PIN11_CONFIG_MSB               13
+#define WLAN_GPIO_PIN11_CONFIG_LSB               11
+#define WLAN_GPIO_PIN11_CONFIG_MASK              0x00003800
+#define WLAN_GPIO_PIN11_CONFIG_GET(x)            (((x) & WLAN_GPIO_PIN11_CONFIG_MASK) >> WLAN_GPIO_PIN11_CONFIG_LSB)
+#define WLAN_GPIO_PIN11_CONFIG_SET(x)            (((x) << WLAN_GPIO_PIN11_CONFIG_LSB) & WLAN_GPIO_PIN11_CONFIG_MASK)
+#define WLAN_GPIO_PIN11_WAKEUP_ENABLE_MSB        10
+#define WLAN_GPIO_PIN11_WAKEUP_ENABLE_LSB        10
+#define WLAN_GPIO_PIN11_WAKEUP_ENABLE_MASK       0x00000400
+#define WLAN_GPIO_PIN11_WAKEUP_ENABLE_GET(x)     (((x) & WLAN_GPIO_PIN11_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN11_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN11_WAKEUP_ENABLE_SET(x)     (((x) << WLAN_GPIO_PIN11_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN11_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN11_INT_TYPE_MSB             9
+#define WLAN_GPIO_PIN11_INT_TYPE_LSB             7
+#define WLAN_GPIO_PIN11_INT_TYPE_MASK            0x00000380
+#define WLAN_GPIO_PIN11_INT_TYPE_GET(x)          (((x) & WLAN_GPIO_PIN11_INT_TYPE_MASK) >> WLAN_GPIO_PIN11_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN11_INT_TYPE_SET(x)          (((x) << WLAN_GPIO_PIN11_INT_TYPE_LSB) & WLAN_GPIO_PIN11_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN11_PAD_PULL_MSB             6
+#define WLAN_GPIO_PIN11_PAD_PULL_LSB             5
+#define WLAN_GPIO_PIN11_PAD_PULL_MASK            0x00000060
+#define WLAN_GPIO_PIN11_PAD_PULL_GET(x)          (((x) & WLAN_GPIO_PIN11_PAD_PULL_MASK) >> WLAN_GPIO_PIN11_PAD_PULL_LSB)
+#define WLAN_GPIO_PIN11_PAD_PULL_SET(x)          (((x) << WLAN_GPIO_PIN11_PAD_PULL_LSB) & WLAN_GPIO_PIN11_PAD_PULL_MASK)
+#define WLAN_GPIO_PIN11_PAD_STRENGTH_MSB         4
+#define WLAN_GPIO_PIN11_PAD_STRENGTH_LSB         3
+#define WLAN_GPIO_PIN11_PAD_STRENGTH_MASK        0x00000018
+#define WLAN_GPIO_PIN11_PAD_STRENGTH_GET(x)      (((x) & WLAN_GPIO_PIN11_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN11_PAD_STRENGTH_LSB)
+#define WLAN_GPIO_PIN11_PAD_STRENGTH_SET(x)      (((x) << WLAN_GPIO_PIN11_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN11_PAD_STRENGTH_MASK)
+#define WLAN_GPIO_PIN11_PAD_DRIVER_MSB           2
+#define WLAN_GPIO_PIN11_PAD_DRIVER_LSB           2
+#define WLAN_GPIO_PIN11_PAD_DRIVER_MASK          0x00000004
+#define WLAN_GPIO_PIN11_PAD_DRIVER_GET(x)        (((x) & WLAN_GPIO_PIN11_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN11_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN11_PAD_DRIVER_SET(x)        (((x) << WLAN_GPIO_PIN11_PAD_DRIVER_LSB) & WLAN_GPIO_PIN11_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN11_SOURCE_MSB               0
+#define WLAN_GPIO_PIN11_SOURCE_LSB               0
+#define WLAN_GPIO_PIN11_SOURCE_MASK              0x00000001
+#define WLAN_GPIO_PIN11_SOURCE_GET(x)            (((x) & WLAN_GPIO_PIN11_SOURCE_MASK) >> WLAN_GPIO_PIN11_SOURCE_LSB)
+#define WLAN_GPIO_PIN11_SOURCE_SET(x)            (((x) << WLAN_GPIO_PIN11_SOURCE_LSB) & WLAN_GPIO_PIN11_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN12_ADDRESS                  0x00000058
+#define WLAN_GPIO_PIN12_OFFSET                   0x00000058
+#define WLAN_GPIO_PIN12_CONFIG_MSB               13
+#define WLAN_GPIO_PIN12_CONFIG_LSB               11
+#define WLAN_GPIO_PIN12_CONFIG_MASK              0x00003800
+#define WLAN_GPIO_PIN12_CONFIG_GET(x)            (((x) & WLAN_GPIO_PIN12_CONFIG_MASK) >> WLAN_GPIO_PIN12_CONFIG_LSB)
+#define WLAN_GPIO_PIN12_CONFIG_SET(x)            (((x) << WLAN_GPIO_PIN12_CONFIG_LSB) & WLAN_GPIO_PIN12_CONFIG_MASK)
+#define WLAN_GPIO_PIN12_WAKEUP_ENABLE_MSB        10
+#define WLAN_GPIO_PIN12_WAKEUP_ENABLE_LSB        10
+#define WLAN_GPIO_PIN12_WAKEUP_ENABLE_MASK       0x00000400
+#define WLAN_GPIO_PIN12_WAKEUP_ENABLE_GET(x)     (((x) & WLAN_GPIO_PIN12_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN12_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN12_WAKEUP_ENABLE_SET(x)     (((x) << WLAN_GPIO_PIN12_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN12_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN12_INT_TYPE_MSB             9
+#define WLAN_GPIO_PIN12_INT_TYPE_LSB             7
+#define WLAN_GPIO_PIN12_INT_TYPE_MASK            0x00000380
+#define WLAN_GPIO_PIN12_INT_TYPE_GET(x)          (((x) & WLAN_GPIO_PIN12_INT_TYPE_MASK) >> WLAN_GPIO_PIN12_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN12_INT_TYPE_SET(x)          (((x) << WLAN_GPIO_PIN12_INT_TYPE_LSB) & WLAN_GPIO_PIN12_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN12_PAD_PULL_MSB             6
+#define WLAN_GPIO_PIN12_PAD_PULL_LSB             5
+#define WLAN_GPIO_PIN12_PAD_PULL_MASK            0x00000060
+#define WLAN_GPIO_PIN12_PAD_PULL_GET(x)          (((x) & WLAN_GPIO_PIN12_PAD_PULL_MASK) >> WLAN_GPIO_PIN12_PAD_PULL_LSB)
+#define WLAN_GPIO_PIN12_PAD_PULL_SET(x)          (((x) << WLAN_GPIO_PIN12_PAD_PULL_LSB) & WLAN_GPIO_PIN12_PAD_PULL_MASK)
+#define WLAN_GPIO_PIN12_PAD_STRENGTH_MSB         4
+#define WLAN_GPIO_PIN12_PAD_STRENGTH_LSB         3
+#define WLAN_GPIO_PIN12_PAD_STRENGTH_MASK        0x00000018
+#define WLAN_GPIO_PIN12_PAD_STRENGTH_GET(x)      (((x) & WLAN_GPIO_PIN12_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN12_PAD_STRENGTH_LSB)
+#define WLAN_GPIO_PIN12_PAD_STRENGTH_SET(x)      (((x) << WLAN_GPIO_PIN12_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN12_PAD_STRENGTH_MASK)
+#define WLAN_GPIO_PIN12_PAD_DRIVER_MSB           2
+#define WLAN_GPIO_PIN12_PAD_DRIVER_LSB           2
+#define WLAN_GPIO_PIN12_PAD_DRIVER_MASK          0x00000004
+#define WLAN_GPIO_PIN12_PAD_DRIVER_GET(x)        (((x) & WLAN_GPIO_PIN12_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN12_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN12_PAD_DRIVER_SET(x)        (((x) << WLAN_GPIO_PIN12_PAD_DRIVER_LSB) & WLAN_GPIO_PIN12_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN12_SOURCE_MSB               0
+#define WLAN_GPIO_PIN12_SOURCE_LSB               0
+#define WLAN_GPIO_PIN12_SOURCE_MASK              0x00000001
+#define WLAN_GPIO_PIN12_SOURCE_GET(x)            (((x) & WLAN_GPIO_PIN12_SOURCE_MASK) >> WLAN_GPIO_PIN12_SOURCE_LSB)
+#define WLAN_GPIO_PIN12_SOURCE_SET(x)            (((x) << WLAN_GPIO_PIN12_SOURCE_LSB) & WLAN_GPIO_PIN12_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN13_ADDRESS                  0x0000005c
+#define WLAN_GPIO_PIN13_OFFSET                   0x0000005c
+#define WLAN_GPIO_PIN13_CONFIG_MSB               13
+#define WLAN_GPIO_PIN13_CONFIG_LSB               11
+#define WLAN_GPIO_PIN13_CONFIG_MASK              0x00003800
+#define WLAN_GPIO_PIN13_CONFIG_GET(x)            (((x) & WLAN_GPIO_PIN13_CONFIG_MASK) >> WLAN_GPIO_PIN13_CONFIG_LSB)
+#define WLAN_GPIO_PIN13_CONFIG_SET(x)            (((x) << WLAN_GPIO_PIN13_CONFIG_LSB) & WLAN_GPIO_PIN13_CONFIG_MASK)
+#define WLAN_GPIO_PIN13_WAKEUP_ENABLE_MSB        10
+#define WLAN_GPIO_PIN13_WAKEUP_ENABLE_LSB        10
+#define WLAN_GPIO_PIN13_WAKEUP_ENABLE_MASK       0x00000400
+#define WLAN_GPIO_PIN13_WAKEUP_ENABLE_GET(x)     (((x) & WLAN_GPIO_PIN13_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN13_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN13_WAKEUP_ENABLE_SET(x)     (((x) << WLAN_GPIO_PIN13_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN13_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN13_INT_TYPE_MSB             9
+#define WLAN_GPIO_PIN13_INT_TYPE_LSB             7
+#define WLAN_GPIO_PIN13_INT_TYPE_MASK            0x00000380
+#define WLAN_GPIO_PIN13_INT_TYPE_GET(x)          (((x) & WLAN_GPIO_PIN13_INT_TYPE_MASK) >> WLAN_GPIO_PIN13_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN13_INT_TYPE_SET(x)          (((x) << WLAN_GPIO_PIN13_INT_TYPE_LSB) & WLAN_GPIO_PIN13_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN13_PAD_PULL_MSB             6
+#define WLAN_GPIO_PIN13_PAD_PULL_LSB             5
+#define WLAN_GPIO_PIN13_PAD_PULL_MASK            0x00000060
+#define WLAN_GPIO_PIN13_PAD_PULL_GET(x)          (((x) & WLAN_GPIO_PIN13_PAD_PULL_MASK) >> WLAN_GPIO_PIN13_PAD_PULL_LSB)
+#define WLAN_GPIO_PIN13_PAD_PULL_SET(x)          (((x) << WLAN_GPIO_PIN13_PAD_PULL_LSB) & WLAN_GPIO_PIN13_PAD_PULL_MASK)
+#define WLAN_GPIO_PIN13_PAD_STRENGTH_MSB         4
+#define WLAN_GPIO_PIN13_PAD_STRENGTH_LSB         3
+#define WLAN_GPIO_PIN13_PAD_STRENGTH_MASK        0x00000018
+#define WLAN_GPIO_PIN13_PAD_STRENGTH_GET(x)      (((x) & WLAN_GPIO_PIN13_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN13_PAD_STRENGTH_LSB)
+#define WLAN_GPIO_PIN13_PAD_STRENGTH_SET(x)      (((x) << WLAN_GPIO_PIN13_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN13_PAD_STRENGTH_MASK)
+#define WLAN_GPIO_PIN13_PAD_DRIVER_MSB           2
+#define WLAN_GPIO_PIN13_PAD_DRIVER_LSB           2
+#define WLAN_GPIO_PIN13_PAD_DRIVER_MASK          0x00000004
+#define WLAN_GPIO_PIN13_PAD_DRIVER_GET(x)        (((x) & WLAN_GPIO_PIN13_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN13_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN13_PAD_DRIVER_SET(x)        (((x) << WLAN_GPIO_PIN13_PAD_DRIVER_LSB) & WLAN_GPIO_PIN13_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN13_SOURCE_MSB               0
+#define WLAN_GPIO_PIN13_SOURCE_LSB               0
+#define WLAN_GPIO_PIN13_SOURCE_MASK              0x00000001
+#define WLAN_GPIO_PIN13_SOURCE_GET(x)            (((x) & WLAN_GPIO_PIN13_SOURCE_MASK) >> WLAN_GPIO_PIN13_SOURCE_LSB)
+#define WLAN_GPIO_PIN13_SOURCE_SET(x)            (((x) << WLAN_GPIO_PIN13_SOURCE_LSB) & WLAN_GPIO_PIN13_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN14_ADDRESS                  0x00000060
+#define WLAN_GPIO_PIN14_OFFSET                   0x00000060
+#define WLAN_GPIO_PIN14_CONFIG_MSB               13
+#define WLAN_GPIO_PIN14_CONFIG_LSB               11
+#define WLAN_GPIO_PIN14_CONFIG_MASK              0x00003800
+#define WLAN_GPIO_PIN14_CONFIG_GET(x)            (((x) & WLAN_GPIO_PIN14_CONFIG_MASK) >> WLAN_GPIO_PIN14_CONFIG_LSB)
+#define WLAN_GPIO_PIN14_CONFIG_SET(x)            (((x) << WLAN_GPIO_PIN14_CONFIG_LSB) & WLAN_GPIO_PIN14_CONFIG_MASK)
+#define WLAN_GPIO_PIN14_WAKEUP_ENABLE_MSB        10
+#define WLAN_GPIO_PIN14_WAKEUP_ENABLE_LSB        10
+#define WLAN_GPIO_PIN14_WAKEUP_ENABLE_MASK       0x00000400
+#define WLAN_GPIO_PIN14_WAKEUP_ENABLE_GET(x)     (((x) & WLAN_GPIO_PIN14_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN14_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN14_WAKEUP_ENABLE_SET(x)     (((x) << WLAN_GPIO_PIN14_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN14_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN14_INT_TYPE_MSB             9
+#define WLAN_GPIO_PIN14_INT_TYPE_LSB             7
+#define WLAN_GPIO_PIN14_INT_TYPE_MASK            0x00000380
+#define WLAN_GPIO_PIN14_INT_TYPE_GET(x)          (((x) & WLAN_GPIO_PIN14_INT_TYPE_MASK) >> WLAN_GPIO_PIN14_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN14_INT_TYPE_SET(x)          (((x) << WLAN_GPIO_PIN14_INT_TYPE_LSB) & WLAN_GPIO_PIN14_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN14_PAD_PULL_MSB             6
+#define WLAN_GPIO_PIN14_PAD_PULL_LSB             5
+#define WLAN_GPIO_PIN14_PAD_PULL_MASK            0x00000060
+#define WLAN_GPIO_PIN14_PAD_PULL_GET(x)          (((x) & WLAN_GPIO_PIN14_PAD_PULL_MASK) >> WLAN_GPIO_PIN14_PAD_PULL_LSB)
+#define WLAN_GPIO_PIN14_PAD_PULL_SET(x)          (((x) << WLAN_GPIO_PIN14_PAD_PULL_LSB) & WLAN_GPIO_PIN14_PAD_PULL_MASK)
+#define WLAN_GPIO_PIN14_PAD_STRENGTH_MSB         4
+#define WLAN_GPIO_PIN14_PAD_STRENGTH_LSB         3
+#define WLAN_GPIO_PIN14_PAD_STRENGTH_MASK        0x00000018
+#define WLAN_GPIO_PIN14_PAD_STRENGTH_GET(x)      (((x) & WLAN_GPIO_PIN14_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN14_PAD_STRENGTH_LSB)
+#define WLAN_GPIO_PIN14_PAD_STRENGTH_SET(x)      (((x) << WLAN_GPIO_PIN14_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN14_PAD_STRENGTH_MASK)
+#define WLAN_GPIO_PIN14_PAD_DRIVER_MSB           2
+#define WLAN_GPIO_PIN14_PAD_DRIVER_LSB           2
+#define WLAN_GPIO_PIN14_PAD_DRIVER_MASK          0x00000004
+#define WLAN_GPIO_PIN14_PAD_DRIVER_GET(x)        (((x) & WLAN_GPIO_PIN14_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN14_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN14_PAD_DRIVER_SET(x)        (((x) << WLAN_GPIO_PIN14_PAD_DRIVER_LSB) & WLAN_GPIO_PIN14_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN14_SOURCE_MSB               0
+#define WLAN_GPIO_PIN14_SOURCE_LSB               0
+#define WLAN_GPIO_PIN14_SOURCE_MASK              0x00000001
+#define WLAN_GPIO_PIN14_SOURCE_GET(x)            (((x) & WLAN_GPIO_PIN14_SOURCE_MASK) >> WLAN_GPIO_PIN14_SOURCE_LSB)
+#define WLAN_GPIO_PIN14_SOURCE_SET(x)            (((x) << WLAN_GPIO_PIN14_SOURCE_LSB) & WLAN_GPIO_PIN14_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN15_ADDRESS                  0x00000064
+#define WLAN_GPIO_PIN15_OFFSET                   0x00000064
+#define WLAN_GPIO_PIN15_CONFIG_MSB               13
+#define WLAN_GPIO_PIN15_CONFIG_LSB               11
+#define WLAN_GPIO_PIN15_CONFIG_MASK              0x00003800
+#define WLAN_GPIO_PIN15_CONFIG_GET(x)            (((x) & WLAN_GPIO_PIN15_CONFIG_MASK) >> WLAN_GPIO_PIN15_CONFIG_LSB)
+#define WLAN_GPIO_PIN15_CONFIG_SET(x)            (((x) << WLAN_GPIO_PIN15_CONFIG_LSB) & WLAN_GPIO_PIN15_CONFIG_MASK)
+#define WLAN_GPIO_PIN15_WAKEUP_ENABLE_MSB        10
+#define WLAN_GPIO_PIN15_WAKEUP_ENABLE_LSB        10
+#define WLAN_GPIO_PIN15_WAKEUP_ENABLE_MASK       0x00000400
+#define WLAN_GPIO_PIN15_WAKEUP_ENABLE_GET(x)     (((x) & WLAN_GPIO_PIN15_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN15_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN15_WAKEUP_ENABLE_SET(x)     (((x) << WLAN_GPIO_PIN15_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN15_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN15_INT_TYPE_MSB             9
+#define WLAN_GPIO_PIN15_INT_TYPE_LSB             7
+#define WLAN_GPIO_PIN15_INT_TYPE_MASK            0x00000380
+#define WLAN_GPIO_PIN15_INT_TYPE_GET(x)          (((x) & WLAN_GPIO_PIN15_INT_TYPE_MASK) >> WLAN_GPIO_PIN15_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN15_INT_TYPE_SET(x)          (((x) << WLAN_GPIO_PIN15_INT_TYPE_LSB) & WLAN_GPIO_PIN15_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN15_PAD_PULL_MSB             6
+#define WLAN_GPIO_PIN15_PAD_PULL_LSB             5
+#define WLAN_GPIO_PIN15_PAD_PULL_MASK            0x00000060
+#define WLAN_GPIO_PIN15_PAD_PULL_GET(x)          (((x) & WLAN_GPIO_PIN15_PAD_PULL_MASK) >> WLAN_GPIO_PIN15_PAD_PULL_LSB)
+#define WLAN_GPIO_PIN15_PAD_PULL_SET(x)          (((x) << WLAN_GPIO_PIN15_PAD_PULL_LSB) & WLAN_GPIO_PIN15_PAD_PULL_MASK)
+#define WLAN_GPIO_PIN15_PAD_STRENGTH_MSB         4
+#define WLAN_GPIO_PIN15_PAD_STRENGTH_LSB         3
+#define WLAN_GPIO_PIN15_PAD_STRENGTH_MASK        0x00000018
+#define WLAN_GPIO_PIN15_PAD_STRENGTH_GET(x)      (((x) & WLAN_GPIO_PIN15_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN15_PAD_STRENGTH_LSB)
+#define WLAN_GPIO_PIN15_PAD_STRENGTH_SET(x)      (((x) << WLAN_GPIO_PIN15_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN15_PAD_STRENGTH_MASK)
+#define WLAN_GPIO_PIN15_PAD_DRIVER_MSB           2
+#define WLAN_GPIO_PIN15_PAD_DRIVER_LSB           2
+#define WLAN_GPIO_PIN15_PAD_DRIVER_MASK          0x00000004
+#define WLAN_GPIO_PIN15_PAD_DRIVER_GET(x)        (((x) & WLAN_GPIO_PIN15_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN15_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN15_PAD_DRIVER_SET(x)        (((x) << WLAN_GPIO_PIN15_PAD_DRIVER_LSB) & WLAN_GPIO_PIN15_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN15_SOURCE_MSB               0
+#define WLAN_GPIO_PIN15_SOURCE_LSB               0
+#define WLAN_GPIO_PIN15_SOURCE_MASK              0x00000001
+#define WLAN_GPIO_PIN15_SOURCE_GET(x)            (((x) & WLAN_GPIO_PIN15_SOURCE_MASK) >> WLAN_GPIO_PIN15_SOURCE_LSB)
+#define WLAN_GPIO_PIN15_SOURCE_SET(x)            (((x) << WLAN_GPIO_PIN15_SOURCE_LSB) & WLAN_GPIO_PIN15_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN16_ADDRESS                  0x00000068
+#define WLAN_GPIO_PIN16_OFFSET                   0x00000068
+#define WLAN_GPIO_PIN16_CONFIG_MSB               13
+#define WLAN_GPIO_PIN16_CONFIG_LSB               11
+#define WLAN_GPIO_PIN16_CONFIG_MASK              0x00003800
+#define WLAN_GPIO_PIN16_CONFIG_GET(x)            (((x) & WLAN_GPIO_PIN16_CONFIG_MASK) >> WLAN_GPIO_PIN16_CONFIG_LSB)
+#define WLAN_GPIO_PIN16_CONFIG_SET(x)            (((x) << WLAN_GPIO_PIN16_CONFIG_LSB) & WLAN_GPIO_PIN16_CONFIG_MASK)
+#define WLAN_GPIO_PIN16_WAKEUP_ENABLE_MSB        10
+#define WLAN_GPIO_PIN16_WAKEUP_ENABLE_LSB        10
+#define WLAN_GPIO_PIN16_WAKEUP_ENABLE_MASK       0x00000400
+#define WLAN_GPIO_PIN16_WAKEUP_ENABLE_GET(x)     (((x) & WLAN_GPIO_PIN16_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN16_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN16_WAKEUP_ENABLE_SET(x)     (((x) << WLAN_GPIO_PIN16_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN16_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN16_INT_TYPE_MSB             9
+#define WLAN_GPIO_PIN16_INT_TYPE_LSB             7
+#define WLAN_GPIO_PIN16_INT_TYPE_MASK            0x00000380
+#define WLAN_GPIO_PIN16_INT_TYPE_GET(x)          (((x) & WLAN_GPIO_PIN16_INT_TYPE_MASK) >> WLAN_GPIO_PIN16_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN16_INT_TYPE_SET(x)          (((x) << WLAN_GPIO_PIN16_INT_TYPE_LSB) & WLAN_GPIO_PIN16_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN16_PAD_PULL_MSB             6
+#define WLAN_GPIO_PIN16_PAD_PULL_LSB             5
+#define WLAN_GPIO_PIN16_PAD_PULL_MASK            0x00000060
+#define WLAN_GPIO_PIN16_PAD_PULL_GET(x)          (((x) & WLAN_GPIO_PIN16_PAD_PULL_MASK) >> WLAN_GPIO_PIN16_PAD_PULL_LSB)
+#define WLAN_GPIO_PIN16_PAD_PULL_SET(x)          (((x) << WLAN_GPIO_PIN16_PAD_PULL_LSB) & WLAN_GPIO_PIN16_PAD_PULL_MASK)
+#define WLAN_GPIO_PIN16_PAD_STRENGTH_MSB         4
+#define WLAN_GPIO_PIN16_PAD_STRENGTH_LSB         3
+#define WLAN_GPIO_PIN16_PAD_STRENGTH_MASK        0x00000018
+#define WLAN_GPIO_PIN16_PAD_STRENGTH_GET(x)      (((x) & WLAN_GPIO_PIN16_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN16_PAD_STRENGTH_LSB)
+#define WLAN_GPIO_PIN16_PAD_STRENGTH_SET(x)      (((x) << WLAN_GPIO_PIN16_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN16_PAD_STRENGTH_MASK)
+#define WLAN_GPIO_PIN16_PAD_DRIVER_MSB           2
+#define WLAN_GPIO_PIN16_PAD_DRIVER_LSB           2
+#define WLAN_GPIO_PIN16_PAD_DRIVER_MASK          0x00000004
+#define WLAN_GPIO_PIN16_PAD_DRIVER_GET(x)        (((x) & WLAN_GPIO_PIN16_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN16_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN16_PAD_DRIVER_SET(x)        (((x) << WLAN_GPIO_PIN16_PAD_DRIVER_LSB) & WLAN_GPIO_PIN16_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN16_SOURCE_MSB               0
+#define WLAN_GPIO_PIN16_SOURCE_LSB               0
+#define WLAN_GPIO_PIN16_SOURCE_MASK              0x00000001
+#define WLAN_GPIO_PIN16_SOURCE_GET(x)            (((x) & WLAN_GPIO_PIN16_SOURCE_MASK) >> WLAN_GPIO_PIN16_SOURCE_LSB)
+#define WLAN_GPIO_PIN16_SOURCE_SET(x)            (((x) << WLAN_GPIO_PIN16_SOURCE_LSB) & WLAN_GPIO_PIN16_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN17_ADDRESS                  0x0000006c
+#define WLAN_GPIO_PIN17_OFFSET                   0x0000006c
+#define WLAN_GPIO_PIN17_CONFIG_MSB               13
+#define WLAN_GPIO_PIN17_CONFIG_LSB               11
+#define WLAN_GPIO_PIN17_CONFIG_MASK              0x00003800
+#define WLAN_GPIO_PIN17_CONFIG_GET(x)            (((x) & WLAN_GPIO_PIN17_CONFIG_MASK) >> WLAN_GPIO_PIN17_CONFIG_LSB)
+#define WLAN_GPIO_PIN17_CONFIG_SET(x)            (((x) << WLAN_GPIO_PIN17_CONFIG_LSB) & WLAN_GPIO_PIN17_CONFIG_MASK)
+#define WLAN_GPIO_PIN17_WAKEUP_ENABLE_MSB        10
+#define WLAN_GPIO_PIN17_WAKEUP_ENABLE_LSB        10
+#define WLAN_GPIO_PIN17_WAKEUP_ENABLE_MASK       0x00000400
+#define WLAN_GPIO_PIN17_WAKEUP_ENABLE_GET(x)     (((x) & WLAN_GPIO_PIN17_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN17_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN17_WAKEUP_ENABLE_SET(x)     (((x) << WLAN_GPIO_PIN17_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN17_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN17_INT_TYPE_MSB             9
+#define WLAN_GPIO_PIN17_INT_TYPE_LSB             7
+#define WLAN_GPIO_PIN17_INT_TYPE_MASK            0x00000380
+#define WLAN_GPIO_PIN17_INT_TYPE_GET(x)          (((x) & WLAN_GPIO_PIN17_INT_TYPE_MASK) >> WLAN_GPIO_PIN17_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN17_INT_TYPE_SET(x)          (((x) << WLAN_GPIO_PIN17_INT_TYPE_LSB) & WLAN_GPIO_PIN17_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN17_PAD_PULL_MSB             6
+#define WLAN_GPIO_PIN17_PAD_PULL_LSB             5
+#define WLAN_GPIO_PIN17_PAD_PULL_MASK            0x00000060
+#define WLAN_GPIO_PIN17_PAD_PULL_GET(x)          (((x) & WLAN_GPIO_PIN17_PAD_PULL_MASK) >> WLAN_GPIO_PIN17_PAD_PULL_LSB)
+#define WLAN_GPIO_PIN17_PAD_PULL_SET(x)          (((x) << WLAN_GPIO_PIN17_PAD_PULL_LSB) & WLAN_GPIO_PIN17_PAD_PULL_MASK)
+#define WLAN_GPIO_PIN17_PAD_STRENGTH_MSB         4
+#define WLAN_GPIO_PIN17_PAD_STRENGTH_LSB         3
+#define WLAN_GPIO_PIN17_PAD_STRENGTH_MASK        0x00000018
+#define WLAN_GPIO_PIN17_PAD_STRENGTH_GET(x)      (((x) & WLAN_GPIO_PIN17_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN17_PAD_STRENGTH_LSB)
+#define WLAN_GPIO_PIN17_PAD_STRENGTH_SET(x)      (((x) << WLAN_GPIO_PIN17_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN17_PAD_STRENGTH_MASK)
+#define WLAN_GPIO_PIN17_PAD_DRIVER_MSB           2
+#define WLAN_GPIO_PIN17_PAD_DRIVER_LSB           2
+#define WLAN_GPIO_PIN17_PAD_DRIVER_MASK          0x00000004
+#define WLAN_GPIO_PIN17_PAD_DRIVER_GET(x)        (((x) & WLAN_GPIO_PIN17_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN17_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN17_PAD_DRIVER_SET(x)        (((x) << WLAN_GPIO_PIN17_PAD_DRIVER_LSB) & WLAN_GPIO_PIN17_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN17_SOURCE_MSB               0
+#define WLAN_GPIO_PIN17_SOURCE_LSB               0
+#define WLAN_GPIO_PIN17_SOURCE_MASK              0x00000001
+#define WLAN_GPIO_PIN17_SOURCE_GET(x)            (((x) & WLAN_GPIO_PIN17_SOURCE_MASK) >> WLAN_GPIO_PIN17_SOURCE_LSB)
+#define WLAN_GPIO_PIN17_SOURCE_SET(x)            (((x) << WLAN_GPIO_PIN17_SOURCE_LSB) & WLAN_GPIO_PIN17_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN18_ADDRESS                  0x00000070
+#define WLAN_GPIO_PIN18_OFFSET                   0x00000070
+#define WLAN_GPIO_PIN18_CONFIG_MSB               13
+#define WLAN_GPIO_PIN18_CONFIG_LSB               11
+#define WLAN_GPIO_PIN18_CONFIG_MASK              0x00003800
+#define WLAN_GPIO_PIN18_CONFIG_GET(x)            (((x) & WLAN_GPIO_PIN18_CONFIG_MASK) >> WLAN_GPIO_PIN18_CONFIG_LSB)
+#define WLAN_GPIO_PIN18_CONFIG_SET(x)            (((x) << WLAN_GPIO_PIN18_CONFIG_LSB) & WLAN_GPIO_PIN18_CONFIG_MASK)
+#define WLAN_GPIO_PIN18_WAKEUP_ENABLE_MSB        10
+#define WLAN_GPIO_PIN18_WAKEUP_ENABLE_LSB        10
+#define WLAN_GPIO_PIN18_WAKEUP_ENABLE_MASK       0x00000400
+#define WLAN_GPIO_PIN18_WAKEUP_ENABLE_GET(x)     (((x) & WLAN_GPIO_PIN18_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN18_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN18_WAKEUP_ENABLE_SET(x)     (((x) << WLAN_GPIO_PIN18_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN18_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN18_INT_TYPE_MSB             9
+#define WLAN_GPIO_PIN18_INT_TYPE_LSB             7
+#define WLAN_GPIO_PIN18_INT_TYPE_MASK            0x00000380
+#define WLAN_GPIO_PIN18_INT_TYPE_GET(x)          (((x) & WLAN_GPIO_PIN18_INT_TYPE_MASK) >> WLAN_GPIO_PIN18_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN18_INT_TYPE_SET(x)          (((x) << WLAN_GPIO_PIN18_INT_TYPE_LSB) & WLAN_GPIO_PIN18_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN18_PAD_PULL_MSB             6
+#define WLAN_GPIO_PIN18_PAD_PULL_LSB             5
+#define WLAN_GPIO_PIN18_PAD_PULL_MASK            0x00000060
+#define WLAN_GPIO_PIN18_PAD_PULL_GET(x)          (((x) & WLAN_GPIO_PIN18_PAD_PULL_MASK) >> WLAN_GPIO_PIN18_PAD_PULL_LSB)
+#define WLAN_GPIO_PIN18_PAD_PULL_SET(x)          (((x) << WLAN_GPIO_PIN18_PAD_PULL_LSB) & WLAN_GPIO_PIN18_PAD_PULL_MASK)
+#define WLAN_GPIO_PIN18_PAD_STRENGTH_MSB         4
+#define WLAN_GPIO_PIN18_PAD_STRENGTH_LSB         3
+#define WLAN_GPIO_PIN18_PAD_STRENGTH_MASK        0x00000018
+#define WLAN_GPIO_PIN18_PAD_STRENGTH_GET(x)      (((x) & WLAN_GPIO_PIN18_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN18_PAD_STRENGTH_LSB)
+#define WLAN_GPIO_PIN18_PAD_STRENGTH_SET(x)      (((x) << WLAN_GPIO_PIN18_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN18_PAD_STRENGTH_MASK)
+#define WLAN_GPIO_PIN18_PAD_DRIVER_MSB           2
+#define WLAN_GPIO_PIN18_PAD_DRIVER_LSB           2
+#define WLAN_GPIO_PIN18_PAD_DRIVER_MASK          0x00000004
+#define WLAN_GPIO_PIN18_PAD_DRIVER_GET(x)        (((x) & WLAN_GPIO_PIN18_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN18_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN18_PAD_DRIVER_SET(x)        (((x) << WLAN_GPIO_PIN18_PAD_DRIVER_LSB) & WLAN_GPIO_PIN18_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN18_SOURCE_MSB               0
+#define WLAN_GPIO_PIN18_SOURCE_LSB               0
+#define WLAN_GPIO_PIN18_SOURCE_MASK              0x00000001
+#define WLAN_GPIO_PIN18_SOURCE_GET(x)            (((x) & WLAN_GPIO_PIN18_SOURCE_MASK) >> WLAN_GPIO_PIN18_SOURCE_LSB)
+#define WLAN_GPIO_PIN18_SOURCE_SET(x)            (((x) << WLAN_GPIO_PIN18_SOURCE_LSB) & WLAN_GPIO_PIN18_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN19_ADDRESS                  0x00000074
+#define WLAN_GPIO_PIN19_OFFSET                   0x00000074
+#define WLAN_GPIO_PIN19_CONFIG_MSB               13
+#define WLAN_GPIO_PIN19_CONFIG_LSB               11
+#define WLAN_GPIO_PIN19_CONFIG_MASK              0x00003800
+#define WLAN_GPIO_PIN19_CONFIG_GET(x)            (((x) & WLAN_GPIO_PIN19_CONFIG_MASK) >> WLAN_GPIO_PIN19_CONFIG_LSB)
+#define WLAN_GPIO_PIN19_CONFIG_SET(x)            (((x) << WLAN_GPIO_PIN19_CONFIG_LSB) & WLAN_GPIO_PIN19_CONFIG_MASK)
+#define WLAN_GPIO_PIN19_WAKEUP_ENABLE_MSB        10
+#define WLAN_GPIO_PIN19_WAKEUP_ENABLE_LSB        10
+#define WLAN_GPIO_PIN19_WAKEUP_ENABLE_MASK       0x00000400
+#define WLAN_GPIO_PIN19_WAKEUP_ENABLE_GET(x)     (((x) & WLAN_GPIO_PIN19_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN19_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN19_WAKEUP_ENABLE_SET(x)     (((x) << WLAN_GPIO_PIN19_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN19_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN19_INT_TYPE_MSB             9
+#define WLAN_GPIO_PIN19_INT_TYPE_LSB             7
+#define WLAN_GPIO_PIN19_INT_TYPE_MASK            0x00000380
+#define WLAN_GPIO_PIN19_INT_TYPE_GET(x)          (((x) & WLAN_GPIO_PIN19_INT_TYPE_MASK) >> WLAN_GPIO_PIN19_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN19_INT_TYPE_SET(x)          (((x) << WLAN_GPIO_PIN19_INT_TYPE_LSB) & WLAN_GPIO_PIN19_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN19_PAD_PULL_MSB             6
+#define WLAN_GPIO_PIN19_PAD_PULL_LSB             5
+#define WLAN_GPIO_PIN19_PAD_PULL_MASK            0x00000060
+#define WLAN_GPIO_PIN19_PAD_PULL_GET(x)          (((x) & WLAN_GPIO_PIN19_PAD_PULL_MASK) >> WLAN_GPIO_PIN19_PAD_PULL_LSB)
+#define WLAN_GPIO_PIN19_PAD_PULL_SET(x)          (((x) << WLAN_GPIO_PIN19_PAD_PULL_LSB) & WLAN_GPIO_PIN19_PAD_PULL_MASK)
+#define WLAN_GPIO_PIN19_PAD_STRENGTH_MSB         4
+#define WLAN_GPIO_PIN19_PAD_STRENGTH_LSB         3
+#define WLAN_GPIO_PIN19_PAD_STRENGTH_MASK        0x00000018
+#define WLAN_GPIO_PIN19_PAD_STRENGTH_GET(x)      (((x) & WLAN_GPIO_PIN19_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN19_PAD_STRENGTH_LSB)
+#define WLAN_GPIO_PIN19_PAD_STRENGTH_SET(x)      (((x) << WLAN_GPIO_PIN19_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN19_PAD_STRENGTH_MASK)
+#define WLAN_GPIO_PIN19_PAD_DRIVER_MSB           2
+#define WLAN_GPIO_PIN19_PAD_DRIVER_LSB           2
+#define WLAN_GPIO_PIN19_PAD_DRIVER_MASK          0x00000004
+#define WLAN_GPIO_PIN19_PAD_DRIVER_GET(x)        (((x) & WLAN_GPIO_PIN19_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN19_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN19_PAD_DRIVER_SET(x)        (((x) << WLAN_GPIO_PIN19_PAD_DRIVER_LSB) & WLAN_GPIO_PIN19_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN19_SOURCE_MSB               0
+#define WLAN_GPIO_PIN19_SOURCE_LSB               0
+#define WLAN_GPIO_PIN19_SOURCE_MASK              0x00000001
+#define WLAN_GPIO_PIN19_SOURCE_GET(x)            (((x) & WLAN_GPIO_PIN19_SOURCE_MASK) >> WLAN_GPIO_PIN19_SOURCE_LSB)
+#define WLAN_GPIO_PIN19_SOURCE_SET(x)            (((x) << WLAN_GPIO_PIN19_SOURCE_LSB) & WLAN_GPIO_PIN19_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN20_ADDRESS                  0x00000078
+#define WLAN_GPIO_PIN20_OFFSET                   0x00000078
+#define WLAN_GPIO_PIN20_CONFIG_MSB               13
+#define WLAN_GPIO_PIN20_CONFIG_LSB               11
+#define WLAN_GPIO_PIN20_CONFIG_MASK              0x00003800
+#define WLAN_GPIO_PIN20_CONFIG_GET(x)            (((x) & WLAN_GPIO_PIN20_CONFIG_MASK) >> WLAN_GPIO_PIN20_CONFIG_LSB)
+#define WLAN_GPIO_PIN20_CONFIG_SET(x)            (((x) << WLAN_GPIO_PIN20_CONFIG_LSB) & WLAN_GPIO_PIN20_CONFIG_MASK)
+#define WLAN_GPIO_PIN20_WAKEUP_ENABLE_MSB        10
+#define WLAN_GPIO_PIN20_WAKEUP_ENABLE_LSB        10
+#define WLAN_GPIO_PIN20_WAKEUP_ENABLE_MASK       0x00000400
+#define WLAN_GPIO_PIN20_WAKEUP_ENABLE_GET(x)     (((x) & WLAN_GPIO_PIN20_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN20_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN20_WAKEUP_ENABLE_SET(x)     (((x) << WLAN_GPIO_PIN20_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN20_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN20_INT_TYPE_MSB             9
+#define WLAN_GPIO_PIN20_INT_TYPE_LSB             7
+#define WLAN_GPIO_PIN20_INT_TYPE_MASK            0x00000380
+#define WLAN_GPIO_PIN20_INT_TYPE_GET(x)          (((x) & WLAN_GPIO_PIN20_INT_TYPE_MASK) >> WLAN_GPIO_PIN20_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN20_INT_TYPE_SET(x)          (((x) << WLAN_GPIO_PIN20_INT_TYPE_LSB) & WLAN_GPIO_PIN20_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN20_PAD_PULL_MSB             6
+#define WLAN_GPIO_PIN20_PAD_PULL_LSB             5
+#define WLAN_GPIO_PIN20_PAD_PULL_MASK            0x00000060
+#define WLAN_GPIO_PIN20_PAD_PULL_GET(x)          (((x) & WLAN_GPIO_PIN20_PAD_PULL_MASK) >> WLAN_GPIO_PIN20_PAD_PULL_LSB)
+#define WLAN_GPIO_PIN20_PAD_PULL_SET(x)          (((x) << WLAN_GPIO_PIN20_PAD_PULL_LSB) & WLAN_GPIO_PIN20_PAD_PULL_MASK)
+#define WLAN_GPIO_PIN20_PAD_STRENGTH_MSB         4
+#define WLAN_GPIO_PIN20_PAD_STRENGTH_LSB         3
+#define WLAN_GPIO_PIN20_PAD_STRENGTH_MASK        0x00000018
+#define WLAN_GPIO_PIN20_PAD_STRENGTH_GET(x)      (((x) & WLAN_GPIO_PIN20_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN20_PAD_STRENGTH_LSB)
+#define WLAN_GPIO_PIN20_PAD_STRENGTH_SET(x)      (((x) << WLAN_GPIO_PIN20_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN20_PAD_STRENGTH_MASK)
+#define WLAN_GPIO_PIN20_PAD_DRIVER_MSB           2
+#define WLAN_GPIO_PIN20_PAD_DRIVER_LSB           2
+#define WLAN_GPIO_PIN20_PAD_DRIVER_MASK          0x00000004
+#define WLAN_GPIO_PIN20_PAD_DRIVER_GET(x)        (((x) & WLAN_GPIO_PIN20_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN20_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN20_PAD_DRIVER_SET(x)        (((x) << WLAN_GPIO_PIN20_PAD_DRIVER_LSB) & WLAN_GPIO_PIN20_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN20_SOURCE_MSB               0
+#define WLAN_GPIO_PIN20_SOURCE_LSB               0
+#define WLAN_GPIO_PIN20_SOURCE_MASK              0x00000001
+#define WLAN_GPIO_PIN20_SOURCE_GET(x)            (((x) & WLAN_GPIO_PIN20_SOURCE_MASK) >> WLAN_GPIO_PIN20_SOURCE_LSB)
+#define WLAN_GPIO_PIN20_SOURCE_SET(x)            (((x) << WLAN_GPIO_PIN20_SOURCE_LSB) & WLAN_GPIO_PIN20_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN21_ADDRESS                  0x0000007c
+#define WLAN_GPIO_PIN21_OFFSET                   0x0000007c
+#define WLAN_GPIO_PIN21_CONFIG_MSB               13
+#define WLAN_GPIO_PIN21_CONFIG_LSB               11
+#define WLAN_GPIO_PIN21_CONFIG_MASK              0x00003800
+#define WLAN_GPIO_PIN21_CONFIG_GET(x)            (((x) & WLAN_GPIO_PIN21_CONFIG_MASK) >> WLAN_GPIO_PIN21_CONFIG_LSB)
+#define WLAN_GPIO_PIN21_CONFIG_SET(x)            (((x) << WLAN_GPIO_PIN21_CONFIG_LSB) & WLAN_GPIO_PIN21_CONFIG_MASK)
+#define WLAN_GPIO_PIN21_WAKEUP_ENABLE_MSB        10
+#define WLAN_GPIO_PIN21_WAKEUP_ENABLE_LSB        10
+#define WLAN_GPIO_PIN21_WAKEUP_ENABLE_MASK       0x00000400
+#define WLAN_GPIO_PIN21_WAKEUP_ENABLE_GET(x)     (((x) & WLAN_GPIO_PIN21_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN21_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN21_WAKEUP_ENABLE_SET(x)     (((x) << WLAN_GPIO_PIN21_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN21_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN21_INT_TYPE_MSB             9
+#define WLAN_GPIO_PIN21_INT_TYPE_LSB             7
+#define WLAN_GPIO_PIN21_INT_TYPE_MASK            0x00000380
+#define WLAN_GPIO_PIN21_INT_TYPE_GET(x)          (((x) & WLAN_GPIO_PIN21_INT_TYPE_MASK) >> WLAN_GPIO_PIN21_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN21_INT_TYPE_SET(x)          (((x) << WLAN_GPIO_PIN21_INT_TYPE_LSB) & WLAN_GPIO_PIN21_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN21_PAD_PULL_MSB             6
+#define WLAN_GPIO_PIN21_PAD_PULL_LSB             5
+#define WLAN_GPIO_PIN21_PAD_PULL_MASK            0x00000060
+#define WLAN_GPIO_PIN21_PAD_PULL_GET(x)          (((x) & WLAN_GPIO_PIN21_PAD_PULL_MASK) >> WLAN_GPIO_PIN21_PAD_PULL_LSB)
+#define WLAN_GPIO_PIN21_PAD_PULL_SET(x)          (((x) << WLAN_GPIO_PIN21_PAD_PULL_LSB) & WLAN_GPIO_PIN21_PAD_PULL_MASK)
+#define WLAN_GPIO_PIN21_PAD_STRENGTH_MSB         4
+#define WLAN_GPIO_PIN21_PAD_STRENGTH_LSB         3
+#define WLAN_GPIO_PIN21_PAD_STRENGTH_MASK        0x00000018
+#define WLAN_GPIO_PIN21_PAD_STRENGTH_GET(x)      (((x) & WLAN_GPIO_PIN21_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN21_PAD_STRENGTH_LSB)
+#define WLAN_GPIO_PIN21_PAD_STRENGTH_SET(x)      (((x) << WLAN_GPIO_PIN21_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN21_PAD_STRENGTH_MASK)
+#define WLAN_GPIO_PIN21_PAD_DRIVER_MSB           2
+#define WLAN_GPIO_PIN21_PAD_DRIVER_LSB           2
+#define WLAN_GPIO_PIN21_PAD_DRIVER_MASK          0x00000004
+#define WLAN_GPIO_PIN21_PAD_DRIVER_GET(x)        (((x) & WLAN_GPIO_PIN21_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN21_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN21_PAD_DRIVER_SET(x)        (((x) << WLAN_GPIO_PIN21_PAD_DRIVER_LSB) & WLAN_GPIO_PIN21_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN21_SOURCE_MSB               0
+#define WLAN_GPIO_PIN21_SOURCE_LSB               0
+#define WLAN_GPIO_PIN21_SOURCE_MASK              0x00000001
+#define WLAN_GPIO_PIN21_SOURCE_GET(x)            (((x) & WLAN_GPIO_PIN21_SOURCE_MASK) >> WLAN_GPIO_PIN21_SOURCE_LSB)
+#define WLAN_GPIO_PIN21_SOURCE_SET(x)            (((x) << WLAN_GPIO_PIN21_SOURCE_LSB) & WLAN_GPIO_PIN21_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN22_ADDRESS                  0x00000080
+#define WLAN_GPIO_PIN22_OFFSET                   0x00000080
+#define WLAN_GPIO_PIN22_CONFIG_MSB               13
+#define WLAN_GPIO_PIN22_CONFIG_LSB               11
+#define WLAN_GPIO_PIN22_CONFIG_MASK              0x00003800
+#define WLAN_GPIO_PIN22_CONFIG_GET(x)            (((x) & WLAN_GPIO_PIN22_CONFIG_MASK) >> WLAN_GPIO_PIN22_CONFIG_LSB)
+#define WLAN_GPIO_PIN22_CONFIG_SET(x)            (((x) << WLAN_GPIO_PIN22_CONFIG_LSB) & WLAN_GPIO_PIN22_CONFIG_MASK)
+#define WLAN_GPIO_PIN22_WAKEUP_ENABLE_MSB        10
+#define WLAN_GPIO_PIN22_WAKEUP_ENABLE_LSB        10
+#define WLAN_GPIO_PIN22_WAKEUP_ENABLE_MASK       0x00000400
+#define WLAN_GPIO_PIN22_WAKEUP_ENABLE_GET(x)     (((x) & WLAN_GPIO_PIN22_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN22_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN22_WAKEUP_ENABLE_SET(x)     (((x) << WLAN_GPIO_PIN22_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN22_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN22_INT_TYPE_MSB             9
+#define WLAN_GPIO_PIN22_INT_TYPE_LSB             7
+#define WLAN_GPIO_PIN22_INT_TYPE_MASK            0x00000380
+#define WLAN_GPIO_PIN22_INT_TYPE_GET(x)          (((x) & WLAN_GPIO_PIN22_INT_TYPE_MASK) >> WLAN_GPIO_PIN22_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN22_INT_TYPE_SET(x)          (((x) << WLAN_GPIO_PIN22_INT_TYPE_LSB) & WLAN_GPIO_PIN22_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN22_PAD_PULL_MSB             6
+#define WLAN_GPIO_PIN22_PAD_PULL_LSB             5
+#define WLAN_GPIO_PIN22_PAD_PULL_MASK            0x00000060
+#define WLAN_GPIO_PIN22_PAD_PULL_GET(x)          (((x) & WLAN_GPIO_PIN22_PAD_PULL_MASK) >> WLAN_GPIO_PIN22_PAD_PULL_LSB)
+#define WLAN_GPIO_PIN22_PAD_PULL_SET(x)          (((x) << WLAN_GPIO_PIN22_PAD_PULL_LSB) & WLAN_GPIO_PIN22_PAD_PULL_MASK)
+#define WLAN_GPIO_PIN22_PAD_STRENGTH_MSB         4
+#define WLAN_GPIO_PIN22_PAD_STRENGTH_LSB         3
+#define WLAN_GPIO_PIN22_PAD_STRENGTH_MASK        0x00000018
+#define WLAN_GPIO_PIN22_PAD_STRENGTH_GET(x)      (((x) & WLAN_GPIO_PIN22_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN22_PAD_STRENGTH_LSB)
+#define WLAN_GPIO_PIN22_PAD_STRENGTH_SET(x)      (((x) << WLAN_GPIO_PIN22_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN22_PAD_STRENGTH_MASK)
+#define WLAN_GPIO_PIN22_PAD_DRIVER_MSB           2
+#define WLAN_GPIO_PIN22_PAD_DRIVER_LSB           2
+#define WLAN_GPIO_PIN22_PAD_DRIVER_MASK          0x00000004
+#define WLAN_GPIO_PIN22_PAD_DRIVER_GET(x)        (((x) & WLAN_GPIO_PIN22_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN22_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN22_PAD_DRIVER_SET(x)        (((x) << WLAN_GPIO_PIN22_PAD_DRIVER_LSB) & WLAN_GPIO_PIN22_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN22_SOURCE_MSB               0
+#define WLAN_GPIO_PIN22_SOURCE_LSB               0
+#define WLAN_GPIO_PIN22_SOURCE_MASK              0x00000001
+#define WLAN_GPIO_PIN22_SOURCE_GET(x)            (((x) & WLAN_GPIO_PIN22_SOURCE_MASK) >> WLAN_GPIO_PIN22_SOURCE_LSB)
+#define WLAN_GPIO_PIN22_SOURCE_SET(x)            (((x) << WLAN_GPIO_PIN22_SOURCE_LSB) & WLAN_GPIO_PIN22_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN23_ADDRESS                  0x00000084
+#define WLAN_GPIO_PIN23_OFFSET                   0x00000084
+#define WLAN_GPIO_PIN23_CONFIG_MSB               13
+#define WLAN_GPIO_PIN23_CONFIG_LSB               11
+#define WLAN_GPIO_PIN23_CONFIG_MASK              0x00003800
+#define WLAN_GPIO_PIN23_CONFIG_GET(x)            (((x) & WLAN_GPIO_PIN23_CONFIG_MASK) >> WLAN_GPIO_PIN23_CONFIG_LSB)
+#define WLAN_GPIO_PIN23_CONFIG_SET(x)            (((x) << WLAN_GPIO_PIN23_CONFIG_LSB) & WLAN_GPIO_PIN23_CONFIG_MASK)
+#define WLAN_GPIO_PIN23_WAKEUP_ENABLE_MSB        10
+#define WLAN_GPIO_PIN23_WAKEUP_ENABLE_LSB        10
+#define WLAN_GPIO_PIN23_WAKEUP_ENABLE_MASK       0x00000400
+#define WLAN_GPIO_PIN23_WAKEUP_ENABLE_GET(x)     (((x) & WLAN_GPIO_PIN23_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN23_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN23_WAKEUP_ENABLE_SET(x)     (((x) << WLAN_GPIO_PIN23_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN23_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN23_INT_TYPE_MSB             9
+#define WLAN_GPIO_PIN23_INT_TYPE_LSB             7
+#define WLAN_GPIO_PIN23_INT_TYPE_MASK            0x00000380
+#define WLAN_GPIO_PIN23_INT_TYPE_GET(x)          (((x) & WLAN_GPIO_PIN23_INT_TYPE_MASK) >> WLAN_GPIO_PIN23_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN23_INT_TYPE_SET(x)          (((x) << WLAN_GPIO_PIN23_INT_TYPE_LSB) & WLAN_GPIO_PIN23_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN23_PAD_DRIVER_MSB           2
+#define WLAN_GPIO_PIN23_PAD_DRIVER_LSB           2
+#define WLAN_GPIO_PIN23_PAD_DRIVER_MASK          0x00000004
+#define WLAN_GPIO_PIN23_PAD_DRIVER_GET(x)        (((x) & WLAN_GPIO_PIN23_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN23_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN23_PAD_DRIVER_SET(x)        (((x) << WLAN_GPIO_PIN23_PAD_DRIVER_LSB) & WLAN_GPIO_PIN23_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN23_SOURCE_MSB               0
+#define WLAN_GPIO_PIN23_SOURCE_LSB               0
+#define WLAN_GPIO_PIN23_SOURCE_MASK              0x00000001
+#define WLAN_GPIO_PIN23_SOURCE_GET(x)            (((x) & WLAN_GPIO_PIN23_SOURCE_MASK) >> WLAN_GPIO_PIN23_SOURCE_LSB)
+#define WLAN_GPIO_PIN23_SOURCE_SET(x)            (((x) << WLAN_GPIO_PIN23_SOURCE_LSB) & WLAN_GPIO_PIN23_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN24_ADDRESS                  0x00000088
+#define WLAN_GPIO_PIN24_OFFSET                   0x00000088
+#define WLAN_GPIO_PIN24_CONFIG_MSB               13
+#define WLAN_GPIO_PIN24_CONFIG_LSB               11
+#define WLAN_GPIO_PIN24_CONFIG_MASK              0x00003800
+#define WLAN_GPIO_PIN24_CONFIG_GET(x)            (((x) & WLAN_GPIO_PIN24_CONFIG_MASK) >> WLAN_GPIO_PIN24_CONFIG_LSB)
+#define WLAN_GPIO_PIN24_CONFIG_SET(x)            (((x) << WLAN_GPIO_PIN24_CONFIG_LSB) & WLAN_GPIO_PIN24_CONFIG_MASK)
+#define WLAN_GPIO_PIN24_WAKEUP_ENABLE_MSB        10
+#define WLAN_GPIO_PIN24_WAKEUP_ENABLE_LSB        10
+#define WLAN_GPIO_PIN24_WAKEUP_ENABLE_MASK       0x00000400
+#define WLAN_GPIO_PIN24_WAKEUP_ENABLE_GET(x)     (((x) & WLAN_GPIO_PIN24_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN24_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN24_WAKEUP_ENABLE_SET(x)     (((x) << WLAN_GPIO_PIN24_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN24_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN24_INT_TYPE_MSB             9
+#define WLAN_GPIO_PIN24_INT_TYPE_LSB             7
+#define WLAN_GPIO_PIN24_INT_TYPE_MASK            0x00000380
+#define WLAN_GPIO_PIN24_INT_TYPE_GET(x)          (((x) & WLAN_GPIO_PIN24_INT_TYPE_MASK) >> WLAN_GPIO_PIN24_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN24_INT_TYPE_SET(x)          (((x) << WLAN_GPIO_PIN24_INT_TYPE_LSB) & WLAN_GPIO_PIN24_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN24_PAD_DRIVER_MSB           2
+#define WLAN_GPIO_PIN24_PAD_DRIVER_LSB           2
+#define WLAN_GPIO_PIN24_PAD_DRIVER_MASK          0x00000004
+#define WLAN_GPIO_PIN24_PAD_DRIVER_GET(x)        (((x) & WLAN_GPIO_PIN24_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN24_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN24_PAD_DRIVER_SET(x)        (((x) << WLAN_GPIO_PIN24_PAD_DRIVER_LSB) & WLAN_GPIO_PIN24_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN24_SOURCE_MSB               0
+#define WLAN_GPIO_PIN24_SOURCE_LSB               0
+#define WLAN_GPIO_PIN24_SOURCE_MASK              0x00000001
+#define WLAN_GPIO_PIN24_SOURCE_GET(x)            (((x) & WLAN_GPIO_PIN24_SOURCE_MASK) >> WLAN_GPIO_PIN24_SOURCE_LSB)
+#define WLAN_GPIO_PIN24_SOURCE_SET(x)            (((x) << WLAN_GPIO_PIN24_SOURCE_LSB) & WLAN_GPIO_PIN24_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN25_ADDRESS                  0x0000008c
+#define WLAN_GPIO_PIN25_OFFSET                   0x0000008c
+#define WLAN_GPIO_PIN25_CONFIG_MSB               13
+#define WLAN_GPIO_PIN25_CONFIG_LSB               11
+#define WLAN_GPIO_PIN25_CONFIG_MASK              0x00003800
+#define WLAN_GPIO_PIN25_CONFIG_GET(x)            (((x) & WLAN_GPIO_PIN25_CONFIG_MASK) >> WLAN_GPIO_PIN25_CONFIG_LSB)
+#define WLAN_GPIO_PIN25_CONFIG_SET(x)            (((x) << WLAN_GPIO_PIN25_CONFIG_LSB) & WLAN_GPIO_PIN25_CONFIG_MASK)
+#define WLAN_GPIO_PIN25_WAKEUP_ENABLE_MSB        10
+#define WLAN_GPIO_PIN25_WAKEUP_ENABLE_LSB        10
+#define WLAN_GPIO_PIN25_WAKEUP_ENABLE_MASK       0x00000400
+#define WLAN_GPIO_PIN25_WAKEUP_ENABLE_GET(x)     (((x) & WLAN_GPIO_PIN25_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN25_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN25_WAKEUP_ENABLE_SET(x)     (((x) << WLAN_GPIO_PIN25_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN25_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN25_INT_TYPE_MSB             9
+#define WLAN_GPIO_PIN25_INT_TYPE_LSB             7
+#define WLAN_GPIO_PIN25_INT_TYPE_MASK            0x00000380
+#define WLAN_GPIO_PIN25_INT_TYPE_GET(x)          (((x) & WLAN_GPIO_PIN25_INT_TYPE_MASK) >> WLAN_GPIO_PIN25_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN25_INT_TYPE_SET(x)          (((x) << WLAN_GPIO_PIN25_INT_TYPE_LSB) & WLAN_GPIO_PIN25_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN25_PAD_DRIVER_MSB           2
+#define WLAN_GPIO_PIN25_PAD_DRIVER_LSB           2
+#define WLAN_GPIO_PIN25_PAD_DRIVER_MASK          0x00000004
+#define WLAN_GPIO_PIN25_PAD_DRIVER_GET(x)        (((x) & WLAN_GPIO_PIN25_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN25_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN25_PAD_DRIVER_SET(x)        (((x) << WLAN_GPIO_PIN25_PAD_DRIVER_LSB) & WLAN_GPIO_PIN25_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN25_SOURCE_MSB               0
+#define WLAN_GPIO_PIN25_SOURCE_LSB               0
+#define WLAN_GPIO_PIN25_SOURCE_MASK              0x00000001
+#define WLAN_GPIO_PIN25_SOURCE_GET(x)            (((x) & WLAN_GPIO_PIN25_SOURCE_MASK) >> WLAN_GPIO_PIN25_SOURCE_LSB)
+#define WLAN_GPIO_PIN25_SOURCE_SET(x)            (((x) << WLAN_GPIO_PIN25_SOURCE_LSB) & WLAN_GPIO_PIN25_SOURCE_MASK)
+
+#define SDIO_ADDRESS                             0x00000090
+#define SDIO_OFFSET                              0x00000090
+#define SDIO_PINS_EN_MSB                         0
+#define SDIO_PINS_EN_LSB                         0
+#define SDIO_PINS_EN_MASK                        0x00000001
+#define SDIO_PINS_EN_GET(x)                      (((x) & SDIO_PINS_EN_MASK) >> SDIO_PINS_EN_LSB)
+#define SDIO_PINS_EN_SET(x)                      (((x) << SDIO_PINS_EN_LSB) & SDIO_PINS_EN_MASK)
+
+#define FUNC_BUS_ADDRESS                         0x00000094
+#define FUNC_BUS_OFFSET                          0x00000094
+#define FUNC_BUS_GPIO_MODE_MSB                   22
+#define FUNC_BUS_GPIO_MODE_LSB                   22
+#define FUNC_BUS_GPIO_MODE_MASK                  0x00400000
+#define FUNC_BUS_GPIO_MODE_GET(x)                (((x) & FUNC_BUS_GPIO_MODE_MASK) >> FUNC_BUS_GPIO_MODE_LSB)
+#define FUNC_BUS_GPIO_MODE_SET(x)                (((x) << FUNC_BUS_GPIO_MODE_LSB) & FUNC_BUS_GPIO_MODE_MASK)
+#define FUNC_BUS_OE_L_MSB                        21
+#define FUNC_BUS_OE_L_LSB                        0
+#define FUNC_BUS_OE_L_MASK                       0x003fffff
+#define FUNC_BUS_OE_L_GET(x)                     (((x) & FUNC_BUS_OE_L_MASK) >> FUNC_BUS_OE_L_LSB)
+#define FUNC_BUS_OE_L_SET(x)                     (((x) << FUNC_BUS_OE_L_LSB) & FUNC_BUS_OE_L_MASK)
+
+#define WL_SOC_APB_ADDRESS                       0x00000098
+#define WL_SOC_APB_OFFSET                        0x00000098
+#define WL_SOC_APB_TOGGLE_MSB                    0
+#define WL_SOC_APB_TOGGLE_LSB                    0
+#define WL_SOC_APB_TOGGLE_MASK                   0x00000001
+#define WL_SOC_APB_TOGGLE_GET(x)                 (((x) & WL_SOC_APB_TOGGLE_MASK) >> WL_SOC_APB_TOGGLE_LSB)
+#define WL_SOC_APB_TOGGLE_SET(x)                 (((x) << WL_SOC_APB_TOGGLE_LSB) & WL_SOC_APB_TOGGLE_MASK)
+
+#define WLAN_SIGMA_DELTA_ADDRESS                 0x0000009c
+#define WLAN_SIGMA_DELTA_OFFSET                  0x0000009c
+#define WLAN_SIGMA_DELTA_ENABLE_MSB              16
+#define WLAN_SIGMA_DELTA_ENABLE_LSB              16
+#define WLAN_SIGMA_DELTA_ENABLE_MASK             0x00010000
+#define WLAN_SIGMA_DELTA_ENABLE_GET(x)           (((x) & WLAN_SIGMA_DELTA_ENABLE_MASK) >> WLAN_SIGMA_DELTA_ENABLE_LSB)
+#define WLAN_SIGMA_DELTA_ENABLE_SET(x)           (((x) << WLAN_SIGMA_DELTA_ENABLE_LSB) & WLAN_SIGMA_DELTA_ENABLE_MASK)
+#define WLAN_SIGMA_DELTA_PRESCALAR_MSB           15
+#define WLAN_SIGMA_DELTA_PRESCALAR_LSB           8
+#define WLAN_SIGMA_DELTA_PRESCALAR_MASK          0x0000ff00
+#define WLAN_SIGMA_DELTA_PRESCALAR_GET(x)        (((x) & WLAN_SIGMA_DELTA_PRESCALAR_MASK) >> WLAN_SIGMA_DELTA_PRESCALAR_LSB)
+#define WLAN_SIGMA_DELTA_PRESCALAR_SET(x)        (((x) << WLAN_SIGMA_DELTA_PRESCALAR_LSB) & WLAN_SIGMA_DELTA_PRESCALAR_MASK)
+#define WLAN_SIGMA_DELTA_TARGET_MSB              7
+#define WLAN_SIGMA_DELTA_TARGET_LSB              0
+#define WLAN_SIGMA_DELTA_TARGET_MASK             0x000000ff
+#define WLAN_SIGMA_DELTA_TARGET_GET(x)           (((x) & WLAN_SIGMA_DELTA_TARGET_MASK) >> WLAN_SIGMA_DELTA_TARGET_LSB)
+#define WLAN_SIGMA_DELTA_TARGET_SET(x)           (((x) << WLAN_SIGMA_DELTA_TARGET_LSB) & WLAN_SIGMA_DELTA_TARGET_MASK)
+
+#define WL_BOOTSTRAP_ADDRESS                     0x000000a0
+#define WL_BOOTSTRAP_OFFSET                      0x000000a0
+#define WL_BOOTSTRAP_STATUS_MSB                  22
+#define WL_BOOTSTRAP_STATUS_LSB                  0
+#define WL_BOOTSTRAP_STATUS_MASK                 0x007fffff
+#define WL_BOOTSTRAP_STATUS_GET(x)               (((x) & WL_BOOTSTRAP_STATUS_MASK) >> WL_BOOTSTRAP_STATUS_LSB)
+#define WL_BOOTSTRAP_STATUS_SET(x)               (((x) << WL_BOOTSTRAP_STATUS_LSB) & WL_BOOTSTRAP_STATUS_MASK)
+
+#define CLOCK_GPIO_ADDRESS                       0x000000a4
+#define CLOCK_GPIO_OFFSET                        0x000000a4
+#define CLOCK_GPIO_CLK_REQ_OUT_EN_MSB            2
+#define CLOCK_GPIO_CLK_REQ_OUT_EN_LSB            2
+#define CLOCK_GPIO_CLK_REQ_OUT_EN_MASK           0x00000004
+#define CLOCK_GPIO_CLK_REQ_OUT_EN_GET(x)         (((x) & CLOCK_GPIO_CLK_REQ_OUT_EN_MASK) >> CLOCK_GPIO_CLK_REQ_OUT_EN_LSB)
+#define CLOCK_GPIO_CLK_REQ_OUT_EN_SET(x)         (((x) << CLOCK_GPIO_CLK_REQ_OUT_EN_LSB) & CLOCK_GPIO_CLK_REQ_OUT_EN_MASK)
+#define CLOCK_GPIO_BT_CLK_REQ_EN_MSB             1
+#define CLOCK_GPIO_BT_CLK_REQ_EN_LSB             1
+#define CLOCK_GPIO_BT_CLK_REQ_EN_MASK            0x00000002
+#define CLOCK_GPIO_BT_CLK_REQ_EN_GET(x)          (((x) & CLOCK_GPIO_BT_CLK_REQ_EN_MASK) >> CLOCK_GPIO_BT_CLK_REQ_EN_LSB)
+#define CLOCK_GPIO_BT_CLK_REQ_EN_SET(x)          (((x) << CLOCK_GPIO_BT_CLK_REQ_EN_LSB) & CLOCK_GPIO_BT_CLK_REQ_EN_MASK)
+#define CLOCK_GPIO_BT_CLK_OUT_EN_MSB             0
+#define CLOCK_GPIO_BT_CLK_OUT_EN_LSB             0
+#define CLOCK_GPIO_BT_CLK_OUT_EN_MASK            0x00000001
+#define CLOCK_GPIO_BT_CLK_OUT_EN_GET(x)          (((x) & CLOCK_GPIO_BT_CLK_OUT_EN_MASK) >> CLOCK_GPIO_BT_CLK_OUT_EN_LSB)
+#define CLOCK_GPIO_BT_CLK_OUT_EN_SET(x)          (((x) << CLOCK_GPIO_BT_CLK_OUT_EN_LSB) & CLOCK_GPIO_BT_CLK_OUT_EN_MASK)
+
+#define WLAN_DEBUG_CONTROL_ADDRESS               0x000000a8
+#define WLAN_DEBUG_CONTROL_OFFSET                0x000000a8
+#define WLAN_DEBUG_CONTROL_ENABLE_MSB            0
+#define WLAN_DEBUG_CONTROL_ENABLE_LSB            0
+#define WLAN_DEBUG_CONTROL_ENABLE_MASK           0x00000001
+#define WLAN_DEBUG_CONTROL_ENABLE_GET(x)         (((x) & WLAN_DEBUG_CONTROL_ENABLE_MASK) >> WLAN_DEBUG_CONTROL_ENABLE_LSB)
+#define WLAN_DEBUG_CONTROL_ENABLE_SET(x)         (((x) << WLAN_DEBUG_CONTROL_ENABLE_LSB) & WLAN_DEBUG_CONTROL_ENABLE_MASK)
+
+#define WLAN_DEBUG_INPUT_SEL_ADDRESS             0x000000ac
+#define WLAN_DEBUG_INPUT_SEL_OFFSET              0x000000ac
+#define WLAN_DEBUG_INPUT_SEL_SHIFT_MSB           5
+#define WLAN_DEBUG_INPUT_SEL_SHIFT_LSB           4
+#define WLAN_DEBUG_INPUT_SEL_SHIFT_MASK          0x00000030
+#define WLAN_DEBUG_INPUT_SEL_SHIFT_GET(x)        (((x) & WLAN_DEBUG_INPUT_SEL_SHIFT_MASK) >> WLAN_DEBUG_INPUT_SEL_SHIFT_LSB)
+#define WLAN_DEBUG_INPUT_SEL_SHIFT_SET(x)        (((x) << WLAN_DEBUG_INPUT_SEL_SHIFT_LSB) & WLAN_DEBUG_INPUT_SEL_SHIFT_MASK)
+#define WLAN_DEBUG_INPUT_SEL_SRC_MSB             3
+#define WLAN_DEBUG_INPUT_SEL_SRC_LSB             0
+#define WLAN_DEBUG_INPUT_SEL_SRC_MASK            0x0000000f
+#define WLAN_DEBUG_INPUT_SEL_SRC_GET(x)          (((x) & WLAN_DEBUG_INPUT_SEL_SRC_MASK) >> WLAN_DEBUG_INPUT_SEL_SRC_LSB)
+#define WLAN_DEBUG_INPUT_SEL_SRC_SET(x)          (((x) << WLAN_DEBUG_INPUT_SEL_SRC_LSB) & WLAN_DEBUG_INPUT_SEL_SRC_MASK)
+
+#define WLAN_DEBUG_OUT_ADDRESS                   0x000000b0
+#define WLAN_DEBUG_OUT_OFFSET                    0x000000b0
+#define WLAN_DEBUG_OUT_DATA_MSB                  17
+#define WLAN_DEBUG_OUT_DATA_LSB                  0
+#define WLAN_DEBUG_OUT_DATA_MASK                 0x0003ffff
+#define WLAN_DEBUG_OUT_DATA_GET(x)               (((x) & WLAN_DEBUG_OUT_DATA_MASK) >> WLAN_DEBUG_OUT_DATA_LSB)
+#define WLAN_DEBUG_OUT_DATA_SET(x)               (((x) << WLAN_DEBUG_OUT_DATA_LSB) & WLAN_DEBUG_OUT_DATA_MASK)
+
+#define WLAN_RESET_TUPLE_STATUS_ADDRESS          0x000000b4
+#define WLAN_RESET_TUPLE_STATUS_OFFSET           0x000000b4
+#define WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MSB 11
+#define WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB 8
+#define WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK 0x00000f00
+#define WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_GET(x) (((x) & WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK) >> WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB)
+#define WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_SET(x) (((x) << WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB) & WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK)
+#define WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MSB 7
+#define WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB 0
+#define WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK 0x000000ff
+#define WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_GET(x) (((x) & WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK) >> WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB)
+#define WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_SET(x) (((x) << WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB) & WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK)
+
+#define ANTENNA_SLEEP_CONTROL_ADDRESS            0x000000b8
+#define ANTENNA_SLEEP_CONTROL_OFFSET             0x000000b8
+#define ANTENNA_SLEEP_CONTROL_OVERRIDE_MSB       14
+#define ANTENNA_SLEEP_CONTROL_OVERRIDE_LSB       10
+#define ANTENNA_SLEEP_CONTROL_OVERRIDE_MASK      0x00007c00
+#define ANTENNA_SLEEP_CONTROL_OVERRIDE_GET(x)    (((x) & ANTENNA_SLEEP_CONTROL_OVERRIDE_MASK) >> ANTENNA_SLEEP_CONTROL_OVERRIDE_LSB)
+#define ANTENNA_SLEEP_CONTROL_OVERRIDE_SET(x)    (((x) << ANTENNA_SLEEP_CONTROL_OVERRIDE_LSB) & ANTENNA_SLEEP_CONTROL_OVERRIDE_MASK)
+#define ANTENNA_SLEEP_CONTROL_VALUE_MSB          9
+#define ANTENNA_SLEEP_CONTROL_VALUE_LSB          5
+#define ANTENNA_SLEEP_CONTROL_VALUE_MASK         0x000003e0
+#define ANTENNA_SLEEP_CONTROL_VALUE_GET(x)       (((x) & ANTENNA_SLEEP_CONTROL_VALUE_MASK) >> ANTENNA_SLEEP_CONTROL_VALUE_LSB)
+#define ANTENNA_SLEEP_CONTROL_VALUE_SET(x)       (((x) << ANTENNA_SLEEP_CONTROL_VALUE_LSB) & ANTENNA_SLEEP_CONTROL_VALUE_MASK)
+#define ANTENNA_SLEEP_CONTROL_ENABLE_MSB         4
+#define ANTENNA_SLEEP_CONTROL_ENABLE_LSB         0
+#define ANTENNA_SLEEP_CONTROL_ENABLE_MASK        0x0000001f
+#define ANTENNA_SLEEP_CONTROL_ENABLE_GET(x)      (((x) & ANTENNA_SLEEP_CONTROL_ENABLE_MASK) >> ANTENNA_SLEEP_CONTROL_ENABLE_LSB)
+#define ANTENNA_SLEEP_CONTROL_ENABLE_SET(x)      (((x) << ANTENNA_SLEEP_CONTROL_ENABLE_LSB) & ANTENNA_SLEEP_CONTROL_ENABLE_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct gpio_athr_wlan_reg_reg_s {
+  volatile unsigned int wlan_gpio_out;
+  volatile unsigned int wlan_gpio_out_w1ts;
+  volatile unsigned int wlan_gpio_out_w1tc;
+  volatile unsigned int wlan_gpio_enable;
+  volatile unsigned int wlan_gpio_enable_w1ts;
+  volatile unsigned int wlan_gpio_enable_w1tc;
+  volatile unsigned int wlan_gpio_in;
+  volatile unsigned int wlan_gpio_status;
+  volatile unsigned int wlan_gpio_status_w1ts;
+  volatile unsigned int wlan_gpio_status_w1tc;
+  volatile unsigned int wlan_gpio_pin0;
+  volatile unsigned int wlan_gpio_pin1;
+  volatile unsigned int wlan_gpio_pin2;
+  volatile unsigned int wlan_gpio_pin3;
+  volatile unsigned int wlan_gpio_pin4;
+  volatile unsigned int wlan_gpio_pin5;
+  volatile unsigned int wlan_gpio_pin6;
+  volatile unsigned int wlan_gpio_pin7;
+  volatile unsigned int wlan_gpio_pin8;
+  volatile unsigned int wlan_gpio_pin9;
+  volatile unsigned int wlan_gpio_pin10;
+  volatile unsigned int wlan_gpio_pin11;
+  volatile unsigned int wlan_gpio_pin12;
+  volatile unsigned int wlan_gpio_pin13;
+  volatile unsigned int wlan_gpio_pin14;
+  volatile unsigned int wlan_gpio_pin15;
+  volatile unsigned int wlan_gpio_pin16;
+  volatile unsigned int wlan_gpio_pin17;
+  volatile unsigned int wlan_gpio_pin18;
+  volatile unsigned int wlan_gpio_pin19;
+  volatile unsigned int wlan_gpio_pin20;
+  volatile unsigned int wlan_gpio_pin21;
+  volatile unsigned int wlan_gpio_pin22;
+  volatile unsigned int wlan_gpio_pin23;
+  volatile unsigned int wlan_gpio_pin24;
+  volatile unsigned int wlan_gpio_pin25;
+  volatile unsigned int sdio;
+  volatile unsigned int func_bus;
+  volatile unsigned int wl_soc_apb;
+  volatile unsigned int wlan_sigma_delta;
+  volatile unsigned int wl_bootstrap;
+  volatile unsigned int clock_gpio;
+  volatile unsigned int wlan_debug_control;
+  volatile unsigned int wlan_debug_input_sel;
+  volatile unsigned int wlan_debug_out;
+  volatile unsigned int wlan_reset_tuple_status;
+  volatile unsigned int antenna_sleep_control;
+} gpio_athr_wlan_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _GPIO_ATHR_WLAN_REG_H_ */
diff --git a/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/gpio_reg.h b/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/gpio_reg.h
new file mode 100644
index 00000000000..b3e7126e26a
--- /dev/null
+++ b/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/gpio_reg.h
@@ -0,0 +1,1094 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifdef WLAN_HEADERS
+
+#include "gpio_athr_wlan_reg.h"
+
+
+#ifndef BT_HEADERS
+
+#define GPIO_OUT_ADDRESS WLAN_GPIO_OUT_ADDRESS
+#define GPIO_OUT_OFFSET WLAN_GPIO_OUT_OFFSET
+#define GPIO_OUT_DATA_MSB WLAN_GPIO_OUT_DATA_MSB
+#define GPIO_OUT_DATA_LSB WLAN_GPIO_OUT_DATA_LSB
+#define GPIO_OUT_DATA_MASK WLAN_GPIO_OUT_DATA_MASK
+#define GPIO_OUT_DATA_GET(x) WLAN_GPIO_OUT_DATA_GET(x)
+#define GPIO_OUT_DATA_SET(x) WLAN_GPIO_OUT_DATA_SET(x)
+#define GPIO_OUT_W1TS_ADDRESS WLAN_GPIO_OUT_W1TS_ADDRESS
+#define GPIO_OUT_W1TS_OFFSET WLAN_GPIO_OUT_W1TS_OFFSET
+#define GPIO_OUT_W1TS_DATA_MSB WLAN_GPIO_OUT_W1TS_DATA_MSB
+#define GPIO_OUT_W1TS_DATA_LSB WLAN_GPIO_OUT_W1TS_DATA_LSB
+#define GPIO_OUT_W1TS_DATA_MASK WLAN_GPIO_OUT_W1TS_DATA_MASK
+#define GPIO_OUT_W1TS_DATA_GET(x) WLAN_GPIO_OUT_W1TS_DATA_GET(x)
+#define GPIO_OUT_W1TS_DATA_SET(x) WLAN_GPIO_OUT_W1TS_DATA_SET(x)
+#define GPIO_OUT_W1TC_ADDRESS WLAN_GPIO_OUT_W1TC_ADDRESS
+#define GPIO_OUT_W1TC_OFFSET WLAN_GPIO_OUT_W1TC_OFFSET
+#define GPIO_OUT_W1TC_DATA_MSB WLAN_GPIO_OUT_W1TC_DATA_MSB
+#define GPIO_OUT_W1TC_DATA_LSB WLAN_GPIO_OUT_W1TC_DATA_LSB
+#define GPIO_OUT_W1TC_DATA_MASK WLAN_GPIO_OUT_W1TC_DATA_MASK
+#define GPIO_OUT_W1TC_DATA_GET(x) WLAN_GPIO_OUT_W1TC_DATA_GET(x)
+#define GPIO_OUT_W1TC_DATA_SET(x) WLAN_GPIO_OUT_W1TC_DATA_SET(x)
+#define GPIO_ENABLE_ADDRESS WLAN_GPIO_ENABLE_ADDRESS
+#define GPIO_ENABLE_OFFSET WLAN_GPIO_ENABLE_OFFSET
+#define GPIO_ENABLE_DATA_MSB WLAN_GPIO_ENABLE_DATA_MSB
+#define GPIO_ENABLE_DATA_LSB WLAN_GPIO_ENABLE_DATA_LSB
+#define GPIO_ENABLE_DATA_MASK WLAN_GPIO_ENABLE_DATA_MASK
+#define GPIO_ENABLE_DATA_GET(x) WLAN_GPIO_ENABLE_DATA_GET(x)
+#define GPIO_ENABLE_DATA_SET(x) WLAN_GPIO_ENABLE_DATA_SET(x)
+#define GPIO_ENABLE_W1TS_ADDRESS WLAN_GPIO_ENABLE_W1TS_ADDRESS
+#define GPIO_ENABLE_W1TS_OFFSET WLAN_GPIO_ENABLE_W1TS_OFFSET
+#define GPIO_ENABLE_W1TS_DATA_MSB WLAN_GPIO_ENABLE_W1TS_DATA_MSB
+#define GPIO_ENABLE_W1TS_DATA_LSB WLAN_GPIO_ENABLE_W1TS_DATA_LSB
+#define GPIO_ENABLE_W1TS_DATA_MASK WLAN_GPIO_ENABLE_W1TS_DATA_MASK
+#define GPIO_ENABLE_W1TS_DATA_GET(x) WLAN_GPIO_ENABLE_W1TS_DATA_GET(x)
+#define GPIO_ENABLE_W1TS_DATA_SET(x) WLAN_GPIO_ENABLE_W1TS_DATA_SET(x)
+#define GPIO_ENABLE_W1TC_ADDRESS WLAN_GPIO_ENABLE_W1TC_ADDRESS
+#define GPIO_ENABLE_W1TC_OFFSET WLAN_GPIO_ENABLE_W1TC_OFFSET
+#define GPIO_ENABLE_W1TC_DATA_MSB WLAN_GPIO_ENABLE_W1TC_DATA_MSB
+#define GPIO_ENABLE_W1TC_DATA_LSB WLAN_GPIO_ENABLE_W1TC_DATA_LSB
+#define GPIO_ENABLE_W1TC_DATA_MASK WLAN_GPIO_ENABLE_W1TC_DATA_MASK
+#define GPIO_ENABLE_W1TC_DATA_GET(x) WLAN_GPIO_ENABLE_W1TC_DATA_GET(x)
+#define GPIO_ENABLE_W1TC_DATA_SET(x) WLAN_GPIO_ENABLE_W1TC_DATA_SET(x)
+#define GPIO_IN_ADDRESS WLAN_GPIO_IN_ADDRESS
+#define GPIO_IN_OFFSET WLAN_GPIO_IN_OFFSET
+#define GPIO_IN_DATA_MSB WLAN_GPIO_IN_DATA_MSB
+#define GPIO_IN_DATA_LSB WLAN_GPIO_IN_DATA_LSB
+#define GPIO_IN_DATA_MASK WLAN_GPIO_IN_DATA_MASK
+#define GPIO_IN_DATA_GET(x) WLAN_GPIO_IN_DATA_GET(x)
+#define GPIO_IN_DATA_SET(x) WLAN_GPIO_IN_DATA_SET(x)
+#define GPIO_STATUS_ADDRESS WLAN_GPIO_STATUS_ADDRESS
+#define GPIO_STATUS_OFFSET WLAN_GPIO_STATUS_OFFSET
+#define GPIO_STATUS_INTERRUPT_MSB WLAN_GPIO_STATUS_INTERRUPT_MSB
+#define GPIO_STATUS_INTERRUPT_LSB WLAN_GPIO_STATUS_INTERRUPT_LSB
+#define GPIO_STATUS_INTERRUPT_MASK WLAN_GPIO_STATUS_INTERRUPT_MASK
+#define GPIO_STATUS_INTERRUPT_GET(x) WLAN_GPIO_STATUS_INTERRUPT_GET(x)
+#define GPIO_STATUS_INTERRUPT_SET(x) WLAN_GPIO_STATUS_INTERRUPT_SET(x)
+#define GPIO_STATUS_W1TS_ADDRESS WLAN_GPIO_STATUS_W1TS_ADDRESS
+#define GPIO_STATUS_W1TS_OFFSET WLAN_GPIO_STATUS_W1TS_OFFSET
+#define GPIO_STATUS_W1TS_INTERRUPT_MSB WLAN_GPIO_STATUS_W1TS_INTERRUPT_MSB
+#define GPIO_STATUS_W1TS_INTERRUPT_LSB WLAN_GPIO_STATUS_W1TS_INTERRUPT_LSB
+#define GPIO_STATUS_W1TS_INTERRUPT_MASK WLAN_GPIO_STATUS_W1TS_INTERRUPT_MASK
+#define GPIO_STATUS_W1TS_INTERRUPT_GET(x) WLAN_GPIO_STATUS_W1TS_INTERRUPT_GET(x)
+#define GPIO_STATUS_W1TS_INTERRUPT_SET(x) WLAN_GPIO_STATUS_W1TS_INTERRUPT_SET(x)
+#define GPIO_STATUS_W1TC_ADDRESS WLAN_GPIO_STATUS_W1TC_ADDRESS
+#define GPIO_STATUS_W1TC_OFFSET WLAN_GPIO_STATUS_W1TC_OFFSET
+#define GPIO_STATUS_W1TC_INTERRUPT_MSB WLAN_GPIO_STATUS_W1TC_INTERRUPT_MSB
+#define GPIO_STATUS_W1TC_INTERRUPT_LSB WLAN_GPIO_STATUS_W1TC_INTERRUPT_LSB
+#define GPIO_STATUS_W1TC_INTERRUPT_MASK WLAN_GPIO_STATUS_W1TC_INTERRUPT_MASK
+#define GPIO_STATUS_W1TC_INTERRUPT_GET(x) WLAN_GPIO_STATUS_W1TC_INTERRUPT_GET(x)
+#define GPIO_STATUS_W1TC_INTERRUPT_SET(x) WLAN_GPIO_STATUS_W1TC_INTERRUPT_SET(x)
+#define GPIO_PIN0_ADDRESS WLAN_GPIO_PIN0_ADDRESS
+#define GPIO_PIN0_OFFSET WLAN_GPIO_PIN0_OFFSET
+#define GPIO_PIN0_CONFIG_MSB WLAN_GPIO_PIN0_CONFIG_MSB
+#define GPIO_PIN0_CONFIG_LSB WLAN_GPIO_PIN0_CONFIG_LSB
+#define GPIO_PIN0_CONFIG_MASK WLAN_GPIO_PIN0_CONFIG_MASK
+#define GPIO_PIN0_CONFIG_GET(x) WLAN_GPIO_PIN0_CONFIG_GET(x)
+#define GPIO_PIN0_CONFIG_SET(x) WLAN_GPIO_PIN0_CONFIG_SET(x)
+#define GPIO_PIN0_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN0_WAKEUP_ENABLE_MSB
+#define GPIO_PIN0_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN0_WAKEUP_ENABLE_LSB
+#define GPIO_PIN0_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN0_WAKEUP_ENABLE_MASK
+#define GPIO_PIN0_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN0_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN0_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN0_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN0_INT_TYPE_MSB WLAN_GPIO_PIN0_INT_TYPE_MSB
+#define GPIO_PIN0_INT_TYPE_LSB WLAN_GPIO_PIN0_INT_TYPE_LSB
+#define GPIO_PIN0_INT_TYPE_MASK WLAN_GPIO_PIN0_INT_TYPE_MASK
+#define GPIO_PIN0_INT_TYPE_GET(x) WLAN_GPIO_PIN0_INT_TYPE_GET(x)
+#define GPIO_PIN0_INT_TYPE_SET(x) WLAN_GPIO_PIN0_INT_TYPE_SET(x)
+#define GPIO_PIN0_PAD_PULL_MSB WLAN_GPIO_PIN0_PAD_PULL_MSB
+#define GPIO_PIN0_PAD_PULL_LSB WLAN_GPIO_PIN0_PAD_PULL_LSB
+#define GPIO_PIN0_PAD_PULL_MASK WLAN_GPIO_PIN0_PAD_PULL_MASK
+#define GPIO_PIN0_PAD_PULL_GET(x) WLAN_GPIO_PIN0_PAD_PULL_GET(x)
+#define GPIO_PIN0_PAD_PULL_SET(x) WLAN_GPIO_PIN0_PAD_PULL_SET(x)
+#define GPIO_PIN0_PAD_STRENGTH_MSB WLAN_GPIO_PIN0_PAD_STRENGTH_MSB
+#define GPIO_PIN0_PAD_STRENGTH_LSB WLAN_GPIO_PIN0_PAD_STRENGTH_LSB
+#define GPIO_PIN0_PAD_STRENGTH_MASK WLAN_GPIO_PIN0_PAD_STRENGTH_MASK
+#define GPIO_PIN0_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN0_PAD_STRENGTH_GET(x)
+#define GPIO_PIN0_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN0_PAD_STRENGTH_SET(x)
+#define GPIO_PIN0_PAD_DRIVER_MSB WLAN_GPIO_PIN0_PAD_DRIVER_MSB
+#define GPIO_PIN0_PAD_DRIVER_LSB WLAN_GPIO_PIN0_PAD_DRIVER_LSB
+#define GPIO_PIN0_PAD_DRIVER_MASK WLAN_GPIO_PIN0_PAD_DRIVER_MASK
+#define GPIO_PIN0_PAD_DRIVER_GET(x) WLAN_GPIO_PIN0_PAD_DRIVER_GET(x)
+#define GPIO_PIN0_PAD_DRIVER_SET(x) WLAN_GPIO_PIN0_PAD_DRIVER_SET(x)
+#define GPIO_PIN0_SOURCE_MSB WLAN_GPIO_PIN0_SOURCE_MSB
+#define GPIO_PIN0_SOURCE_LSB WLAN_GPIO_PIN0_SOURCE_LSB
+#define GPIO_PIN0_SOURCE_MASK WLAN_GPIO_PIN0_SOURCE_MASK
+#define GPIO_PIN0_SOURCE_GET(x) WLAN_GPIO_PIN0_SOURCE_GET(x)
+#define GPIO_PIN0_SOURCE_SET(x) WLAN_GPIO_PIN0_SOURCE_SET(x)
+#define GPIO_PIN1_ADDRESS WLAN_GPIO_PIN1_ADDRESS
+#define GPIO_PIN1_OFFSET WLAN_GPIO_PIN1_OFFSET
+#define GPIO_PIN1_CONFIG_MSB WLAN_GPIO_PIN1_CONFIG_MSB
+#define GPIO_PIN1_CONFIG_LSB WLAN_GPIO_PIN1_CONFIG_LSB
+#define GPIO_PIN1_CONFIG_MASK WLAN_GPIO_PIN1_CONFIG_MASK
+#define GPIO_PIN1_CONFIG_GET(x) WLAN_GPIO_PIN1_CONFIG_GET(x)
+#define GPIO_PIN1_CONFIG_SET(x) WLAN_GPIO_PIN1_CONFIG_SET(x)
+#define GPIO_PIN1_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN1_WAKEUP_ENABLE_MSB
+#define GPIO_PIN1_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN1_WAKEUP_ENABLE_LSB
+#define GPIO_PIN1_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN1_WAKEUP_ENABLE_MASK
+#define GPIO_PIN1_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN1_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN1_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN1_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN1_INT_TYPE_MSB WLAN_GPIO_PIN1_INT_TYPE_MSB
+#define GPIO_PIN1_INT_TYPE_LSB WLAN_GPIO_PIN1_INT_TYPE_LSB
+#define GPIO_PIN1_INT_TYPE_MASK WLAN_GPIO_PIN1_INT_TYPE_MASK
+#define GPIO_PIN1_INT_TYPE_GET(x) WLAN_GPIO_PIN1_INT_TYPE_GET(x)
+#define GPIO_PIN1_INT_TYPE_SET(x) WLAN_GPIO_PIN1_INT_TYPE_SET(x)
+#define GPIO_PIN1_PAD_PULL_MSB WLAN_GPIO_PIN1_PAD_PULL_MSB
+#define GPIO_PIN1_PAD_PULL_LSB WLAN_GPIO_PIN1_PAD_PULL_LSB
+#define GPIO_PIN1_PAD_PULL_MASK WLAN_GPIO_PIN1_PAD_PULL_MASK
+#define GPIO_PIN1_PAD_PULL_GET(x) WLAN_GPIO_PIN1_PAD_PULL_GET(x)
+#define GPIO_PIN1_PAD_PULL_SET(x) WLAN_GPIO_PIN1_PAD_PULL_SET(x)
+#define GPIO_PIN1_PAD_STRENGTH_MSB WLAN_GPIO_PIN1_PAD_STRENGTH_MSB
+#define GPIO_PIN1_PAD_STRENGTH_LSB WLAN_GPIO_PIN1_PAD_STRENGTH_LSB
+#define GPIO_PIN1_PAD_STRENGTH_MASK WLAN_GPIO_PIN1_PAD_STRENGTH_MASK
+#define GPIO_PIN1_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN1_PAD_STRENGTH_GET(x)
+#define GPIO_PIN1_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN1_PAD_STRENGTH_SET(x)
+#define GPIO_PIN1_PAD_DRIVER_MSB WLAN_GPIO_PIN1_PAD_DRIVER_MSB
+#define GPIO_PIN1_PAD_DRIVER_LSB WLAN_GPIO_PIN1_PAD_DRIVER_LSB
+#define GPIO_PIN1_PAD_DRIVER_MASK WLAN_GPIO_PIN1_PAD_DRIVER_MASK
+#define GPIO_PIN1_PAD_DRIVER_GET(x) WLAN_GPIO_PIN1_PAD_DRIVER_GET(x)
+#define GPIO_PIN1_PAD_DRIVER_SET(x) WLAN_GPIO_PIN1_PAD_DRIVER_SET(x)
+#define GPIO_PIN1_SOURCE_MSB WLAN_GPIO_PIN1_SOURCE_MSB
+#define GPIO_PIN1_SOURCE_LSB WLAN_GPIO_PIN1_SOURCE_LSB
+#define GPIO_PIN1_SOURCE_MASK WLAN_GPIO_PIN1_SOURCE_MASK
+#define GPIO_PIN1_SOURCE_GET(x) WLAN_GPIO_PIN1_SOURCE_GET(x)
+#define GPIO_PIN1_SOURCE_SET(x) WLAN_GPIO_PIN1_SOURCE_SET(x)
+#define GPIO_PIN2_ADDRESS WLAN_GPIO_PIN2_ADDRESS
+#define GPIO_PIN2_OFFSET WLAN_GPIO_PIN2_OFFSET
+#define GPIO_PIN2_CONFIG_MSB WLAN_GPIO_PIN2_CONFIG_MSB
+#define GPIO_PIN2_CONFIG_LSB WLAN_GPIO_PIN2_CONFIG_LSB
+#define GPIO_PIN2_CONFIG_MASK WLAN_GPIO_PIN2_CONFIG_MASK
+#define GPIO_PIN2_CONFIG_GET(x) WLAN_GPIO_PIN2_CONFIG_GET(x)
+#define GPIO_PIN2_CONFIG_SET(x) WLAN_GPIO_PIN2_CONFIG_SET(x)
+#define GPIO_PIN2_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN2_WAKEUP_ENABLE_MSB
+#define GPIO_PIN2_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN2_WAKEUP_ENABLE_LSB
+#define GPIO_PIN2_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN2_WAKEUP_ENABLE_MASK
+#define GPIO_PIN2_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN2_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN2_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN2_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN2_INT_TYPE_MSB WLAN_GPIO_PIN2_INT_TYPE_MSB
+#define GPIO_PIN2_INT_TYPE_LSB WLAN_GPIO_PIN2_INT_TYPE_LSB
+#define GPIO_PIN2_INT_TYPE_MASK WLAN_GPIO_PIN2_INT_TYPE_MASK
+#define GPIO_PIN2_INT_TYPE_GET(x) WLAN_GPIO_PIN2_INT_TYPE_GET(x)
+#define GPIO_PIN2_INT_TYPE_SET(x) WLAN_GPIO_PIN2_INT_TYPE_SET(x)
+#define GPIO_PIN2_PAD_PULL_MSB WLAN_GPIO_PIN2_PAD_PULL_MSB
+#define GPIO_PIN2_PAD_PULL_LSB WLAN_GPIO_PIN2_PAD_PULL_LSB
+#define GPIO_PIN2_PAD_PULL_MASK WLAN_GPIO_PIN2_PAD_PULL_MASK
+#define GPIO_PIN2_PAD_PULL_GET(x) WLAN_GPIO_PIN2_PAD_PULL_GET(x)
+#define GPIO_PIN2_PAD_PULL_SET(x) WLAN_GPIO_PIN2_PAD_PULL_SET(x)
+#define GPIO_PIN2_PAD_STRENGTH_MSB WLAN_GPIO_PIN2_PAD_STRENGTH_MSB
+#define GPIO_PIN2_PAD_STRENGTH_LSB WLAN_GPIO_PIN2_PAD_STRENGTH_LSB
+#define GPIO_PIN2_PAD_STRENGTH_MASK WLAN_GPIO_PIN2_PAD_STRENGTH_MASK
+#define GPIO_PIN2_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN2_PAD_STRENGTH_GET(x)
+#define GPIO_PIN2_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN2_PAD_STRENGTH_SET(x)
+#define GPIO_PIN2_PAD_DRIVER_MSB WLAN_GPIO_PIN2_PAD_DRIVER_MSB
+#define GPIO_PIN2_PAD_DRIVER_LSB WLAN_GPIO_PIN2_PAD_DRIVER_LSB
+#define GPIO_PIN2_PAD_DRIVER_MASK WLAN_GPIO_PIN2_PAD_DRIVER_MASK
+#define GPIO_PIN2_PAD_DRIVER_GET(x) WLAN_GPIO_PIN2_PAD_DRIVER_GET(x)
+#define GPIO_PIN2_PAD_DRIVER_SET(x) WLAN_GPIO_PIN2_PAD_DRIVER_SET(x)
+#define GPIO_PIN2_SOURCE_MSB WLAN_GPIO_PIN2_SOURCE_MSB
+#define GPIO_PIN2_SOURCE_LSB WLAN_GPIO_PIN2_SOURCE_LSB
+#define GPIO_PIN2_SOURCE_MASK WLAN_GPIO_PIN2_SOURCE_MASK
+#define GPIO_PIN2_SOURCE_GET(x) WLAN_GPIO_PIN2_SOURCE_GET(x)
+#define GPIO_PIN2_SOURCE_SET(x) WLAN_GPIO_PIN2_SOURCE_SET(x)
+#define GPIO_PIN3_ADDRESS WLAN_GPIO_PIN3_ADDRESS
+#define GPIO_PIN3_OFFSET WLAN_GPIO_PIN3_OFFSET
+#define GPIO_PIN3_CONFIG_MSB WLAN_GPIO_PIN3_CONFIG_MSB
+#define GPIO_PIN3_CONFIG_LSB WLAN_GPIO_PIN3_CONFIG_LSB
+#define GPIO_PIN3_CONFIG_MASK WLAN_GPIO_PIN3_CONFIG_MASK
+#define GPIO_PIN3_CONFIG_GET(x) WLAN_GPIO_PIN3_CONFIG_GET(x)
+#define GPIO_PIN3_CONFIG_SET(x) WLAN_GPIO_PIN3_CONFIG_SET(x)
+#define GPIO_PIN3_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN3_WAKEUP_ENABLE_MSB
+#define GPIO_PIN3_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN3_WAKEUP_ENABLE_LSB
+#define GPIO_PIN3_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN3_WAKEUP_ENABLE_MASK
+#define GPIO_PIN3_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN3_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN3_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN3_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN3_INT_TYPE_MSB WLAN_GPIO_PIN3_INT_TYPE_MSB
+#define GPIO_PIN3_INT_TYPE_LSB WLAN_GPIO_PIN3_INT_TYPE_LSB
+#define GPIO_PIN3_INT_TYPE_MASK WLAN_GPIO_PIN3_INT_TYPE_MASK
+#define GPIO_PIN3_INT_TYPE_GET(x) WLAN_GPIO_PIN3_INT_TYPE_GET(x)
+#define GPIO_PIN3_INT_TYPE_SET(x) WLAN_GPIO_PIN3_INT_TYPE_SET(x)
+#define GPIO_PIN3_PAD_PULL_MSB WLAN_GPIO_PIN3_PAD_PULL_MSB
+#define GPIO_PIN3_PAD_PULL_LSB WLAN_GPIO_PIN3_PAD_PULL_LSB
+#define GPIO_PIN3_PAD_PULL_MASK WLAN_GPIO_PIN3_PAD_PULL_MASK
+#define GPIO_PIN3_PAD_PULL_GET(x) WLAN_GPIO_PIN3_PAD_PULL_GET(x)
+#define GPIO_PIN3_PAD_PULL_SET(x) WLAN_GPIO_PIN3_PAD_PULL_SET(x)
+#define GPIO_PIN3_PAD_STRENGTH_MSB WLAN_GPIO_PIN3_PAD_STRENGTH_MSB
+#define GPIO_PIN3_PAD_STRENGTH_LSB WLAN_GPIO_PIN3_PAD_STRENGTH_LSB
+#define GPIO_PIN3_PAD_STRENGTH_MASK WLAN_GPIO_PIN3_PAD_STRENGTH_MASK
+#define GPIO_PIN3_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN3_PAD_STRENGTH_GET(x)
+#define GPIO_PIN3_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN3_PAD_STRENGTH_SET(x)
+#define GPIO_PIN3_PAD_DRIVER_MSB WLAN_GPIO_PIN3_PAD_DRIVER_MSB
+#define GPIO_PIN3_PAD_DRIVER_LSB WLAN_GPIO_PIN3_PAD_DRIVER_LSB
+#define GPIO_PIN3_PAD_DRIVER_MASK WLAN_GPIO_PIN3_PAD_DRIVER_MASK
+#define GPIO_PIN3_PAD_DRIVER_GET(x) WLAN_GPIO_PIN3_PAD_DRIVER_GET(x)
+#define GPIO_PIN3_PAD_DRIVER_SET(x) WLAN_GPIO_PIN3_PAD_DRIVER_SET(x)
+#define GPIO_PIN3_SOURCE_MSB WLAN_GPIO_PIN3_SOURCE_MSB
+#define GPIO_PIN3_SOURCE_LSB WLAN_GPIO_PIN3_SOURCE_LSB
+#define GPIO_PIN3_SOURCE_MASK WLAN_GPIO_PIN3_SOURCE_MASK
+#define GPIO_PIN3_SOURCE_GET(x) WLAN_GPIO_PIN3_SOURCE_GET(x)
+#define GPIO_PIN3_SOURCE_SET(x) WLAN_GPIO_PIN3_SOURCE_SET(x)
+#define GPIO_PIN4_ADDRESS WLAN_GPIO_PIN4_ADDRESS
+#define GPIO_PIN4_OFFSET WLAN_GPIO_PIN4_OFFSET
+#define GPIO_PIN4_CONFIG_MSB WLAN_GPIO_PIN4_CONFIG_MSB
+#define GPIO_PIN4_CONFIG_LSB WLAN_GPIO_PIN4_CONFIG_LSB
+#define GPIO_PIN4_CONFIG_MASK WLAN_GPIO_PIN4_CONFIG_MASK
+#define GPIO_PIN4_CONFIG_GET(x) WLAN_GPIO_PIN4_CONFIG_GET(x)
+#define GPIO_PIN4_CONFIG_SET(x) WLAN_GPIO_PIN4_CONFIG_SET(x)
+#define GPIO_PIN4_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN4_WAKEUP_ENABLE_MSB
+#define GPIO_PIN4_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN4_WAKEUP_ENABLE_LSB
+#define GPIO_PIN4_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN4_WAKEUP_ENABLE_MASK
+#define GPIO_PIN4_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN4_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN4_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN4_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN4_INT_TYPE_MSB WLAN_GPIO_PIN4_INT_TYPE_MSB
+#define GPIO_PIN4_INT_TYPE_LSB WLAN_GPIO_PIN4_INT_TYPE_LSB
+#define GPIO_PIN4_INT_TYPE_MASK WLAN_GPIO_PIN4_INT_TYPE_MASK
+#define GPIO_PIN4_INT_TYPE_GET(x) WLAN_GPIO_PIN4_INT_TYPE_GET(x)
+#define GPIO_PIN4_INT_TYPE_SET(x) WLAN_GPIO_PIN4_INT_TYPE_SET(x)
+#define GPIO_PIN4_PAD_PULL_MSB WLAN_GPIO_PIN4_PAD_PULL_MSB
+#define GPIO_PIN4_PAD_PULL_LSB WLAN_GPIO_PIN4_PAD_PULL_LSB
+#define GPIO_PIN4_PAD_PULL_MASK WLAN_GPIO_PIN4_PAD_PULL_MASK
+#define GPIO_PIN4_PAD_PULL_GET(x) WLAN_GPIO_PIN4_PAD_PULL_GET(x)
+#define GPIO_PIN4_PAD_PULL_SET(x) WLAN_GPIO_PIN4_PAD_PULL_SET(x)
+#define GPIO_PIN4_PAD_STRENGTH_MSB WLAN_GPIO_PIN4_PAD_STRENGTH_MSB
+#define GPIO_PIN4_PAD_STRENGTH_LSB WLAN_GPIO_PIN4_PAD_STRENGTH_LSB
+#define GPIO_PIN4_PAD_STRENGTH_MASK WLAN_GPIO_PIN4_PAD_STRENGTH_MASK
+#define GPIO_PIN4_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN4_PAD_STRENGTH_GET(x)
+#define GPIO_PIN4_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN4_PAD_STRENGTH_SET(x)
+#define GPIO_PIN4_PAD_DRIVER_MSB WLAN_GPIO_PIN4_PAD_DRIVER_MSB
+#define GPIO_PIN4_PAD_DRIVER_LSB WLAN_GPIO_PIN4_PAD_DRIVER_LSB
+#define GPIO_PIN4_PAD_DRIVER_MASK WLAN_GPIO_PIN4_PAD_DRIVER_MASK
+#define GPIO_PIN4_PAD_DRIVER_GET(x) WLAN_GPIO_PIN4_PAD_DRIVER_GET(x)
+#define GPIO_PIN4_PAD_DRIVER_SET(x) WLAN_GPIO_PIN4_PAD_DRIVER_SET(x)
+#define GPIO_PIN4_SOURCE_MSB WLAN_GPIO_PIN4_SOURCE_MSB
+#define GPIO_PIN4_SOURCE_LSB WLAN_GPIO_PIN4_SOURCE_LSB
+#define GPIO_PIN4_SOURCE_MASK WLAN_GPIO_PIN4_SOURCE_MASK
+#define GPIO_PIN4_SOURCE_GET(x) WLAN_GPIO_PIN4_SOURCE_GET(x)
+#define GPIO_PIN4_SOURCE_SET(x) WLAN_GPIO_PIN4_SOURCE_SET(x)
+#define GPIO_PIN5_ADDRESS WLAN_GPIO_PIN5_ADDRESS
+#define GPIO_PIN5_OFFSET WLAN_GPIO_PIN5_OFFSET
+#define GPIO_PIN5_CONFIG_MSB WLAN_GPIO_PIN5_CONFIG_MSB
+#define GPIO_PIN5_CONFIG_LSB WLAN_GPIO_PIN5_CONFIG_LSB
+#define GPIO_PIN5_CONFIG_MASK WLAN_GPIO_PIN5_CONFIG_MASK
+#define GPIO_PIN5_CONFIG_GET(x) WLAN_GPIO_PIN5_CONFIG_GET(x)
+#define GPIO_PIN5_CONFIG_SET(x) WLAN_GPIO_PIN5_CONFIG_SET(x)
+#define GPIO_PIN5_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN5_WAKEUP_ENABLE_MSB
+#define GPIO_PIN5_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN5_WAKEUP_ENABLE_LSB
+#define GPIO_PIN5_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN5_WAKEUP_ENABLE_MASK
+#define GPIO_PIN5_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN5_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN5_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN5_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN5_INT_TYPE_MSB WLAN_GPIO_PIN5_INT_TYPE_MSB
+#define GPIO_PIN5_INT_TYPE_LSB WLAN_GPIO_PIN5_INT_TYPE_LSB
+#define GPIO_PIN5_INT_TYPE_MASK WLAN_GPIO_PIN5_INT_TYPE_MASK
+#define GPIO_PIN5_INT_TYPE_GET(x) WLAN_GPIO_PIN5_INT_TYPE_GET(x)
+#define GPIO_PIN5_INT_TYPE_SET(x) WLAN_GPIO_PIN5_INT_TYPE_SET(x)
+#define GPIO_PIN5_PAD_PULL_MSB WLAN_GPIO_PIN5_PAD_PULL_MSB
+#define GPIO_PIN5_PAD_PULL_LSB WLAN_GPIO_PIN5_PAD_PULL_LSB
+#define GPIO_PIN5_PAD_PULL_MASK WLAN_GPIO_PIN5_PAD_PULL_MASK
+#define GPIO_PIN5_PAD_PULL_GET(x) WLAN_GPIO_PIN5_PAD_PULL_GET(x)
+#define GPIO_PIN5_PAD_PULL_SET(x) WLAN_GPIO_PIN5_PAD_PULL_SET(x)
+#define GPIO_PIN5_PAD_STRENGTH_MSB WLAN_GPIO_PIN5_PAD_STRENGTH_MSB
+#define GPIO_PIN5_PAD_STRENGTH_LSB WLAN_GPIO_PIN5_PAD_STRENGTH_LSB
+#define GPIO_PIN5_PAD_STRENGTH_MASK WLAN_GPIO_PIN5_PAD_STRENGTH_MASK
+#define GPIO_PIN5_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN5_PAD_STRENGTH_GET(x)
+#define GPIO_PIN5_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN5_PAD_STRENGTH_SET(x)
+#define GPIO_PIN5_PAD_DRIVER_MSB WLAN_GPIO_PIN5_PAD_DRIVER_MSB
+#define GPIO_PIN5_PAD_DRIVER_LSB WLAN_GPIO_PIN5_PAD_DRIVER_LSB
+#define GPIO_PIN5_PAD_DRIVER_MASK WLAN_GPIO_PIN5_PAD_DRIVER_MASK
+#define GPIO_PIN5_PAD_DRIVER_GET(x) WLAN_GPIO_PIN5_PAD_DRIVER_GET(x)
+#define GPIO_PIN5_PAD_DRIVER_SET(x) WLAN_GPIO_PIN5_PAD_DRIVER_SET(x)
+#define GPIO_PIN5_SOURCE_MSB WLAN_GPIO_PIN5_SOURCE_MSB
+#define GPIO_PIN5_SOURCE_LSB WLAN_GPIO_PIN5_SOURCE_LSB
+#define GPIO_PIN5_SOURCE_MASK WLAN_GPIO_PIN5_SOURCE_MASK
+#define GPIO_PIN5_SOURCE_GET(x) WLAN_GPIO_PIN5_SOURCE_GET(x)
+#define GPIO_PIN5_SOURCE_SET(x) WLAN_GPIO_PIN5_SOURCE_SET(x)
+#define GPIO_PIN6_ADDRESS WLAN_GPIO_PIN6_ADDRESS
+#define GPIO_PIN6_OFFSET WLAN_GPIO_PIN6_OFFSET
+#define GPIO_PIN6_CONFIG_MSB WLAN_GPIO_PIN6_CONFIG_MSB
+#define GPIO_PIN6_CONFIG_LSB WLAN_GPIO_PIN6_CONFIG_LSB
+#define GPIO_PIN6_CONFIG_MASK WLAN_GPIO_PIN6_CONFIG_MASK
+#define GPIO_PIN6_CONFIG_GET(x) WLAN_GPIO_PIN6_CONFIG_GET(x)
+#define GPIO_PIN6_CONFIG_SET(x) WLAN_GPIO_PIN6_CONFIG_SET(x)
+#define GPIO_PIN6_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN6_WAKEUP_ENABLE_MSB
+#define GPIO_PIN6_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN6_WAKEUP_ENABLE_LSB
+#define GPIO_PIN6_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN6_WAKEUP_ENABLE_MASK
+#define GPIO_PIN6_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN6_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN6_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN6_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN6_INT_TYPE_MSB WLAN_GPIO_PIN6_INT_TYPE_MSB
+#define GPIO_PIN6_INT_TYPE_LSB WLAN_GPIO_PIN6_INT_TYPE_LSB
+#define GPIO_PIN6_INT_TYPE_MASK WLAN_GPIO_PIN6_INT_TYPE_MASK
+#define GPIO_PIN6_INT_TYPE_GET(x) WLAN_GPIO_PIN6_INT_TYPE_GET(x)
+#define GPIO_PIN6_INT_TYPE_SET(x) WLAN_GPIO_PIN6_INT_TYPE_SET(x)
+#define GPIO_PIN6_PAD_PULL_MSB WLAN_GPIO_PIN6_PAD_PULL_MSB
+#define GPIO_PIN6_PAD_PULL_LSB WLAN_GPIO_PIN6_PAD_PULL_LSB
+#define GPIO_PIN6_PAD_PULL_MASK WLAN_GPIO_PIN6_PAD_PULL_MASK
+#define GPIO_PIN6_PAD_PULL_GET(x) WLAN_GPIO_PIN6_PAD_PULL_GET(x)
+#define GPIO_PIN6_PAD_PULL_SET(x) WLAN_GPIO_PIN6_PAD_PULL_SET(x)
+#define GPIO_PIN6_PAD_STRENGTH_MSB WLAN_GPIO_PIN6_PAD_STRENGTH_MSB
+#define GPIO_PIN6_PAD_STRENGTH_LSB WLAN_GPIO_PIN6_PAD_STRENGTH_LSB
+#define GPIO_PIN6_PAD_STRENGTH_MASK WLAN_GPIO_PIN6_PAD_STRENGTH_MASK
+#define GPIO_PIN6_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN6_PAD_STRENGTH_GET(x)
+#define GPIO_PIN6_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN6_PAD_STRENGTH_SET(x)
+#define GPIO_PIN6_PAD_DRIVER_MSB WLAN_GPIO_PIN6_PAD_DRIVER_MSB
+#define GPIO_PIN6_PAD_DRIVER_LSB WLAN_GPIO_PIN6_PAD_DRIVER_LSB
+#define GPIO_PIN6_PAD_DRIVER_MASK WLAN_GPIO_PIN6_PAD_DRIVER_MASK
+#define GPIO_PIN6_PAD_DRIVER_GET(x) WLAN_GPIO_PIN6_PAD_DRIVER_GET(x)
+#define GPIO_PIN6_PAD_DRIVER_SET(x) WLAN_GPIO_PIN6_PAD_DRIVER_SET(x)
+#define GPIO_PIN6_SOURCE_MSB WLAN_GPIO_PIN6_SOURCE_MSB
+#define GPIO_PIN6_SOURCE_LSB WLAN_GPIO_PIN6_SOURCE_LSB
+#define GPIO_PIN6_SOURCE_MASK WLAN_GPIO_PIN6_SOURCE_MASK
+#define GPIO_PIN6_SOURCE_GET(x) WLAN_GPIO_PIN6_SOURCE_GET(x)
+#define GPIO_PIN6_SOURCE_SET(x) WLAN_GPIO_PIN6_SOURCE_SET(x)
+#define GPIO_PIN7_ADDRESS WLAN_GPIO_PIN7_ADDRESS
+#define GPIO_PIN7_OFFSET WLAN_GPIO_PIN7_OFFSET
+#define GPIO_PIN7_CONFIG_MSB WLAN_GPIO_PIN7_CONFIG_MSB
+#define GPIO_PIN7_CONFIG_LSB WLAN_GPIO_PIN7_CONFIG_LSB
+#define GPIO_PIN7_CONFIG_MASK WLAN_GPIO_PIN7_CONFIG_MASK
+#define GPIO_PIN7_CONFIG_GET(x) WLAN_GPIO_PIN7_CONFIG_GET(x)
+#define GPIO_PIN7_CONFIG_SET(x) WLAN_GPIO_PIN7_CONFIG_SET(x)
+#define GPIO_PIN7_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN7_WAKEUP_ENABLE_MSB
+#define GPIO_PIN7_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN7_WAKEUP_ENABLE_LSB
+#define GPIO_PIN7_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN7_WAKEUP_ENABLE_MASK
+#define GPIO_PIN7_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN7_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN7_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN7_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN7_INT_TYPE_MSB WLAN_GPIO_PIN7_INT_TYPE_MSB
+#define GPIO_PIN7_INT_TYPE_LSB WLAN_GPIO_PIN7_INT_TYPE_LSB
+#define GPIO_PIN7_INT_TYPE_MASK WLAN_GPIO_PIN7_INT_TYPE_MASK
+#define GPIO_PIN7_INT_TYPE_GET(x) WLAN_GPIO_PIN7_INT_TYPE_GET(x)
+#define GPIO_PIN7_INT_TYPE_SET(x) WLAN_GPIO_PIN7_INT_TYPE_SET(x)
+#define GPIO_PIN7_PAD_PULL_MSB WLAN_GPIO_PIN7_PAD_PULL_MSB
+#define GPIO_PIN7_PAD_PULL_LSB WLAN_GPIO_PIN7_PAD_PULL_LSB
+#define GPIO_PIN7_PAD_PULL_MASK WLAN_GPIO_PIN7_PAD_PULL_MASK
+#define GPIO_PIN7_PAD_PULL_GET(x) WLAN_GPIO_PIN7_PAD_PULL_GET(x)
+#define GPIO_PIN7_PAD_PULL_SET(x) WLAN_GPIO_PIN7_PAD_PULL_SET(x)
+#define GPIO_PIN7_PAD_STRENGTH_MSB WLAN_GPIO_PIN7_PAD_STRENGTH_MSB
+#define GPIO_PIN7_PAD_STRENGTH_LSB WLAN_GPIO_PIN7_PAD_STRENGTH_LSB
+#define GPIO_PIN7_PAD_STRENGTH_MASK WLAN_GPIO_PIN7_PAD_STRENGTH_MASK
+#define GPIO_PIN7_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN7_PAD_STRENGTH_GET(x)
+#define GPIO_PIN7_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN7_PAD_STRENGTH_SET(x)
+#define GPIO_PIN7_PAD_DRIVER_MSB WLAN_GPIO_PIN7_PAD_DRIVER_MSB
+#define GPIO_PIN7_PAD_DRIVER_LSB WLAN_GPIO_PIN7_PAD_DRIVER_LSB
+#define GPIO_PIN7_PAD_DRIVER_MASK WLAN_GPIO_PIN7_PAD_DRIVER_MASK
+#define GPIO_PIN7_PAD_DRIVER_GET(x) WLAN_GPIO_PIN7_PAD_DRIVER_GET(x)
+#define GPIO_PIN7_PAD_DRIVER_SET(x) WLAN_GPIO_PIN7_PAD_DRIVER_SET(x)
+#define GPIO_PIN7_SOURCE_MSB WLAN_GPIO_PIN7_SOURCE_MSB
+#define GPIO_PIN7_SOURCE_LSB WLAN_GPIO_PIN7_SOURCE_LSB
+#define GPIO_PIN7_SOURCE_MASK WLAN_GPIO_PIN7_SOURCE_MASK
+#define GPIO_PIN7_SOURCE_GET(x) WLAN_GPIO_PIN7_SOURCE_GET(x)
+#define GPIO_PIN7_SOURCE_SET(x) WLAN_GPIO_PIN7_SOURCE_SET(x)
+#define GPIO_PIN8_ADDRESS WLAN_GPIO_PIN8_ADDRESS
+#define GPIO_PIN8_OFFSET WLAN_GPIO_PIN8_OFFSET
+#define GPIO_PIN8_CONFIG_MSB WLAN_GPIO_PIN8_CONFIG_MSB
+#define GPIO_PIN8_CONFIG_LSB WLAN_GPIO_PIN8_CONFIG_LSB
+#define GPIO_PIN8_CONFIG_MASK WLAN_GPIO_PIN8_CONFIG_MASK
+#define GPIO_PIN8_CONFIG_GET(x) WLAN_GPIO_PIN8_CONFIG_GET(x)
+#define GPIO_PIN8_CONFIG_SET(x) WLAN_GPIO_PIN8_CONFIG_SET(x)
+#define GPIO_PIN8_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN8_WAKEUP_ENABLE_MSB
+#define GPIO_PIN8_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN8_WAKEUP_ENABLE_LSB
+#define GPIO_PIN8_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN8_WAKEUP_ENABLE_MASK
+#define GPIO_PIN8_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN8_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN8_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN8_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN8_INT_TYPE_MSB WLAN_GPIO_PIN8_INT_TYPE_MSB
+#define GPIO_PIN8_INT_TYPE_LSB WLAN_GPIO_PIN8_INT_TYPE_LSB
+#define GPIO_PIN8_INT_TYPE_MASK WLAN_GPIO_PIN8_INT_TYPE_MASK
+#define GPIO_PIN8_INT_TYPE_GET(x) WLAN_GPIO_PIN8_INT_TYPE_GET(x)
+#define GPIO_PIN8_INT_TYPE_SET(x) WLAN_GPIO_PIN8_INT_TYPE_SET(x)
+#define GPIO_PIN8_PAD_PULL_MSB WLAN_GPIO_PIN8_PAD_PULL_MSB
+#define GPIO_PIN8_PAD_PULL_LSB WLAN_GPIO_PIN8_PAD_PULL_LSB
+#define GPIO_PIN8_PAD_PULL_MASK WLAN_GPIO_PIN8_PAD_PULL_MASK
+#define GPIO_PIN8_PAD_PULL_GET(x) WLAN_GPIO_PIN8_PAD_PULL_GET(x)
+#define GPIO_PIN8_PAD_PULL_SET(x) WLAN_GPIO_PIN8_PAD_PULL_SET(x)
+#define GPIO_PIN8_PAD_STRENGTH_MSB WLAN_GPIO_PIN8_PAD_STRENGTH_MSB
+#define GPIO_PIN8_PAD_STRENGTH_LSB WLAN_GPIO_PIN8_PAD_STRENGTH_LSB
+#define GPIO_PIN8_PAD_STRENGTH_MASK WLAN_GPIO_PIN8_PAD_STRENGTH_MASK
+#define GPIO_PIN8_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN8_PAD_STRENGTH_GET(x)
+#define GPIO_PIN8_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN8_PAD_STRENGTH_SET(x)
+#define GPIO_PIN8_PAD_DRIVER_MSB WLAN_GPIO_PIN8_PAD_DRIVER_MSB
+#define GPIO_PIN8_PAD_DRIVER_LSB WLAN_GPIO_PIN8_PAD_DRIVER_LSB
+#define GPIO_PIN8_PAD_DRIVER_MASK WLAN_GPIO_PIN8_PAD_DRIVER_MASK
+#define GPIO_PIN8_PAD_DRIVER_GET(x) WLAN_GPIO_PIN8_PAD_DRIVER_GET(x)
+#define GPIO_PIN8_PAD_DRIVER_SET(x) WLAN_GPIO_PIN8_PAD_DRIVER_SET(x)
+#define GPIO_PIN8_SOURCE_MSB WLAN_GPIO_PIN8_SOURCE_MSB
+#define GPIO_PIN8_SOURCE_LSB WLAN_GPIO_PIN8_SOURCE_LSB
+#define GPIO_PIN8_SOURCE_MASK WLAN_GPIO_PIN8_SOURCE_MASK
+#define GPIO_PIN8_SOURCE_GET(x) WLAN_GPIO_PIN8_SOURCE_GET(x)
+#define GPIO_PIN8_SOURCE_SET(x) WLAN_GPIO_PIN8_SOURCE_SET(x)
+#define GPIO_PIN9_ADDRESS WLAN_GPIO_PIN9_ADDRESS
+#define GPIO_PIN9_OFFSET WLAN_GPIO_PIN9_OFFSET
+#define GPIO_PIN9_CONFIG_MSB WLAN_GPIO_PIN9_CONFIG_MSB
+#define GPIO_PIN9_CONFIG_LSB WLAN_GPIO_PIN9_CONFIG_LSB
+#define GPIO_PIN9_CONFIG_MASK WLAN_GPIO_PIN9_CONFIG_MASK
+#define GPIO_PIN9_CONFIG_GET(x) WLAN_GPIO_PIN9_CONFIG_GET(x)
+#define GPIO_PIN9_CONFIG_SET(x) WLAN_GPIO_PIN9_CONFIG_SET(x)
+#define GPIO_PIN9_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN9_WAKEUP_ENABLE_MSB
+#define GPIO_PIN9_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN9_WAKEUP_ENABLE_LSB
+#define GPIO_PIN9_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN9_WAKEUP_ENABLE_MASK
+#define GPIO_PIN9_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN9_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN9_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN9_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN9_INT_TYPE_MSB WLAN_GPIO_PIN9_INT_TYPE_MSB
+#define GPIO_PIN9_INT_TYPE_LSB WLAN_GPIO_PIN9_INT_TYPE_LSB
+#define GPIO_PIN9_INT_TYPE_MASK WLAN_GPIO_PIN9_INT_TYPE_MASK
+#define GPIO_PIN9_INT_TYPE_GET(x) WLAN_GPIO_PIN9_INT_TYPE_GET(x)
+#define GPIO_PIN9_INT_TYPE_SET(x) WLAN_GPIO_PIN9_INT_TYPE_SET(x)
+#define GPIO_PIN9_PAD_PULL_MSB WLAN_GPIO_PIN9_PAD_PULL_MSB
+#define GPIO_PIN9_PAD_PULL_LSB WLAN_GPIO_PIN9_PAD_PULL_LSB
+#define GPIO_PIN9_PAD_PULL_MASK WLAN_GPIO_PIN9_PAD_PULL_MASK
+#define GPIO_PIN9_PAD_PULL_GET(x) WLAN_GPIO_PIN9_PAD_PULL_GET(x)
+#define GPIO_PIN9_PAD_PULL_SET(x) WLAN_GPIO_PIN9_PAD_PULL_SET(x)
+#define GPIO_PIN9_PAD_STRENGTH_MSB WLAN_GPIO_PIN9_PAD_STRENGTH_MSB
+#define GPIO_PIN9_PAD_STRENGTH_LSB WLAN_GPIO_PIN9_PAD_STRENGTH_LSB
+#define GPIO_PIN9_PAD_STRENGTH_MASK WLAN_GPIO_PIN9_PAD_STRENGTH_MASK
+#define GPIO_PIN9_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN9_PAD_STRENGTH_GET(x)
+#define GPIO_PIN9_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN9_PAD_STRENGTH_SET(x)
+#define GPIO_PIN9_PAD_DRIVER_MSB WLAN_GPIO_PIN9_PAD_DRIVER_MSB
+#define GPIO_PIN9_PAD_DRIVER_LSB WLAN_GPIO_PIN9_PAD_DRIVER_LSB
+#define GPIO_PIN9_PAD_DRIVER_MASK WLAN_GPIO_PIN9_PAD_DRIVER_MASK
+#define GPIO_PIN9_PAD_DRIVER_GET(x) WLAN_GPIO_PIN9_PAD_DRIVER_GET(x)
+#define GPIO_PIN9_PAD_DRIVER_SET(x) WLAN_GPIO_PIN9_PAD_DRIVER_SET(x)
+#define GPIO_PIN9_SOURCE_MSB WLAN_GPIO_PIN9_SOURCE_MSB
+#define GPIO_PIN9_SOURCE_LSB WLAN_GPIO_PIN9_SOURCE_LSB
+#define GPIO_PIN9_SOURCE_MASK WLAN_GPIO_PIN9_SOURCE_MASK
+#define GPIO_PIN9_SOURCE_GET(x) WLAN_GPIO_PIN9_SOURCE_GET(x)
+#define GPIO_PIN9_SOURCE_SET(x) WLAN_GPIO_PIN9_SOURCE_SET(x)
+#define GPIO_PIN10_ADDRESS WLAN_GPIO_PIN10_ADDRESS
+#define GPIO_PIN10_OFFSET WLAN_GPIO_PIN10_OFFSET
+#define GPIO_PIN10_CONFIG_MSB WLAN_GPIO_PIN10_CONFIG_MSB
+#define GPIO_PIN10_CONFIG_LSB WLAN_GPIO_PIN10_CONFIG_LSB
+#define GPIO_PIN10_CONFIG_MASK WLAN_GPIO_PIN10_CONFIG_MASK
+#define GPIO_PIN10_CONFIG_GET(x) WLAN_GPIO_PIN10_CONFIG_GET(x)
+#define GPIO_PIN10_CONFIG_SET(x) WLAN_GPIO_PIN10_CONFIG_SET(x)
+#define GPIO_PIN10_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN10_WAKEUP_ENABLE_MSB
+#define GPIO_PIN10_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN10_WAKEUP_ENABLE_LSB
+#define GPIO_PIN10_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN10_WAKEUP_ENABLE_MASK
+#define GPIO_PIN10_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN10_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN10_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN10_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN10_INT_TYPE_MSB WLAN_GPIO_PIN10_INT_TYPE_MSB
+#define GPIO_PIN10_INT_TYPE_LSB WLAN_GPIO_PIN10_INT_TYPE_LSB
+#define GPIO_PIN10_INT_TYPE_MASK WLAN_GPIO_PIN10_INT_TYPE_MASK
+#define GPIO_PIN10_INT_TYPE_GET(x) WLAN_GPIO_PIN10_INT_TYPE_GET(x)
+#define GPIO_PIN10_INT_TYPE_SET(x) WLAN_GPIO_PIN10_INT_TYPE_SET(x)
+#define GPIO_PIN10_PAD_PULL_MSB WLAN_GPIO_PIN10_PAD_PULL_MSB
+#define GPIO_PIN10_PAD_PULL_LSB WLAN_GPIO_PIN10_PAD_PULL_LSB
+#define GPIO_PIN10_PAD_PULL_MASK WLAN_GPIO_PIN10_PAD_PULL_MASK
+#define GPIO_PIN10_PAD_PULL_GET(x) WLAN_GPIO_PIN10_PAD_PULL_GET(x)
+#define GPIO_PIN10_PAD_PULL_SET(x) WLAN_GPIO_PIN10_PAD_PULL_SET(x)
+#define GPIO_PIN10_PAD_STRENGTH_MSB WLAN_GPIO_PIN10_PAD_STRENGTH_MSB
+#define GPIO_PIN10_PAD_STRENGTH_LSB WLAN_GPIO_PIN10_PAD_STRENGTH_LSB
+#define GPIO_PIN10_PAD_STRENGTH_MASK WLAN_GPIO_PIN10_PAD_STRENGTH_MASK
+#define GPIO_PIN10_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN10_PAD_STRENGTH_GET(x)
+#define GPIO_PIN10_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN10_PAD_STRENGTH_SET(x)
+#define GPIO_PIN10_PAD_DRIVER_MSB WLAN_GPIO_PIN10_PAD_DRIVER_MSB
+#define GPIO_PIN10_PAD_DRIVER_LSB WLAN_GPIO_PIN10_PAD_DRIVER_LSB
+#define GPIO_PIN10_PAD_DRIVER_MASK WLAN_GPIO_PIN10_PAD_DRIVER_MASK
+#define GPIO_PIN10_PAD_DRIVER_GET(x) WLAN_GPIO_PIN10_PAD_DRIVER_GET(x)
+#define GPIO_PIN10_PAD_DRIVER_SET(x) WLAN_GPIO_PIN10_PAD_DRIVER_SET(x)
+#define GPIO_PIN10_SOURCE_MSB WLAN_GPIO_PIN10_SOURCE_MSB
+#define GPIO_PIN10_SOURCE_LSB WLAN_GPIO_PIN10_SOURCE_LSB
+#define GPIO_PIN10_SOURCE_MASK WLAN_GPIO_PIN10_SOURCE_MASK
+#define GPIO_PIN10_SOURCE_GET(x) WLAN_GPIO_PIN10_SOURCE_GET(x)
+#define GPIO_PIN10_SOURCE_SET(x) WLAN_GPIO_PIN10_SOURCE_SET(x)
+#define GPIO_PIN11_ADDRESS WLAN_GPIO_PIN11_ADDRESS
+#define GPIO_PIN11_OFFSET WLAN_GPIO_PIN11_OFFSET
+#define GPIO_PIN11_CONFIG_MSB WLAN_GPIO_PIN11_CONFIG_MSB
+#define GPIO_PIN11_CONFIG_LSB WLAN_GPIO_PIN11_CONFIG_LSB
+#define GPIO_PIN11_CONFIG_MASK WLAN_GPIO_PIN11_CONFIG_MASK
+#define GPIO_PIN11_CONFIG_GET(x) WLAN_GPIO_PIN11_CONFIG_GET(x)
+#define GPIO_PIN11_CONFIG_SET(x) WLAN_GPIO_PIN11_CONFIG_SET(x)
+#define GPIO_PIN11_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN11_WAKEUP_ENABLE_MSB
+#define GPIO_PIN11_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN11_WAKEUP_ENABLE_LSB
+#define GPIO_PIN11_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN11_WAKEUP_ENABLE_MASK
+#define GPIO_PIN11_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN11_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN11_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN11_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN11_INT_TYPE_MSB WLAN_GPIO_PIN11_INT_TYPE_MSB
+#define GPIO_PIN11_INT_TYPE_LSB WLAN_GPIO_PIN11_INT_TYPE_LSB
+#define GPIO_PIN11_INT_TYPE_MASK WLAN_GPIO_PIN11_INT_TYPE_MASK
+#define GPIO_PIN11_INT_TYPE_GET(x) WLAN_GPIO_PIN11_INT_TYPE_GET(x)
+#define GPIO_PIN11_INT_TYPE_SET(x) WLAN_GPIO_PIN11_INT_TYPE_SET(x)
+#define GPIO_PIN11_PAD_PULL_MSB WLAN_GPIO_PIN11_PAD_PULL_MSB
+#define GPIO_PIN11_PAD_PULL_LSB WLAN_GPIO_PIN11_PAD_PULL_LSB
+#define GPIO_PIN11_PAD_PULL_MASK WLAN_GPIO_PIN11_PAD_PULL_MASK
+#define GPIO_PIN11_PAD_PULL_GET(x) WLAN_GPIO_PIN11_PAD_PULL_GET(x)
+#define GPIO_PIN11_PAD_PULL_SET(x) WLAN_GPIO_PIN11_PAD_PULL_SET(x)
+#define GPIO_PIN11_PAD_STRENGTH_MSB WLAN_GPIO_PIN11_PAD_STRENGTH_MSB
+#define GPIO_PIN11_PAD_STRENGTH_LSB WLAN_GPIO_PIN11_PAD_STRENGTH_LSB
+#define GPIO_PIN11_PAD_STRENGTH_MASK WLAN_GPIO_PIN11_PAD_STRENGTH_MASK
+#define GPIO_PIN11_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN11_PAD_STRENGTH_GET(x)
+#define GPIO_PIN11_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN11_PAD_STRENGTH_SET(x)
+#define GPIO_PIN11_PAD_DRIVER_MSB WLAN_GPIO_PIN11_PAD_DRIVER_MSB
+#define GPIO_PIN11_PAD_DRIVER_LSB WLAN_GPIO_PIN11_PAD_DRIVER_LSB
+#define GPIO_PIN11_PAD_DRIVER_MASK WLAN_GPIO_PIN11_PAD_DRIVER_MASK
+#define GPIO_PIN11_PAD_DRIVER_GET(x) WLAN_GPIO_PIN11_PAD_DRIVER_GET(x)
+#define GPIO_PIN11_PAD_DRIVER_SET(x) WLAN_GPIO_PIN11_PAD_DRIVER_SET(x)
+#define GPIO_PIN11_SOURCE_MSB WLAN_GPIO_PIN11_SOURCE_MSB
+#define GPIO_PIN11_SOURCE_LSB WLAN_GPIO_PIN11_SOURCE_LSB
+#define GPIO_PIN11_SOURCE_MASK WLAN_GPIO_PIN11_SOURCE_MASK
+#define GPIO_PIN11_SOURCE_GET(x) WLAN_GPIO_PIN11_SOURCE_GET(x)
+#define GPIO_PIN11_SOURCE_SET(x) WLAN_GPIO_PIN11_SOURCE_SET(x)
+#define GPIO_PIN12_ADDRESS WLAN_GPIO_PIN12_ADDRESS
+#define GPIO_PIN12_OFFSET WLAN_GPIO_PIN12_OFFSET
+#define GPIO_PIN12_CONFIG_MSB WLAN_GPIO_PIN12_CONFIG_MSB
+#define GPIO_PIN12_CONFIG_LSB WLAN_GPIO_PIN12_CONFIG_LSB
+#define GPIO_PIN12_CONFIG_MASK WLAN_GPIO_PIN12_CONFIG_MASK
+#define GPIO_PIN12_CONFIG_GET(x) WLAN_GPIO_PIN12_CONFIG_GET(x)
+#define GPIO_PIN12_CONFIG_SET(x) WLAN_GPIO_PIN12_CONFIG_SET(x)
+#define GPIO_PIN12_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN12_WAKEUP_ENABLE_MSB
+#define GPIO_PIN12_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN12_WAKEUP_ENABLE_LSB
+#define GPIO_PIN12_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN12_WAKEUP_ENABLE_MASK
+#define GPIO_PIN12_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN12_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN12_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN12_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN12_INT_TYPE_MSB WLAN_GPIO_PIN12_INT_TYPE_MSB
+#define GPIO_PIN12_INT_TYPE_LSB WLAN_GPIO_PIN12_INT_TYPE_LSB
+#define GPIO_PIN12_INT_TYPE_MASK WLAN_GPIO_PIN12_INT_TYPE_MASK
+#define GPIO_PIN12_INT_TYPE_GET(x) WLAN_GPIO_PIN12_INT_TYPE_GET(x)
+#define GPIO_PIN12_INT_TYPE_SET(x) WLAN_GPIO_PIN12_INT_TYPE_SET(x)
+#define GPIO_PIN12_PAD_PULL_MSB WLAN_GPIO_PIN12_PAD_PULL_MSB
+#define GPIO_PIN12_PAD_PULL_LSB WLAN_GPIO_PIN12_PAD_PULL_LSB
+#define GPIO_PIN12_PAD_PULL_MASK WLAN_GPIO_PIN12_PAD_PULL_MASK
+#define GPIO_PIN12_PAD_PULL_GET(x) WLAN_GPIO_PIN12_PAD_PULL_GET(x)
+#define GPIO_PIN12_PAD_PULL_SET(x) WLAN_GPIO_PIN12_PAD_PULL_SET(x)
+#define GPIO_PIN12_PAD_STRENGTH_MSB WLAN_GPIO_PIN12_PAD_STRENGTH_MSB
+#define GPIO_PIN12_PAD_STRENGTH_LSB WLAN_GPIO_PIN12_PAD_STRENGTH_LSB
+#define GPIO_PIN12_PAD_STRENGTH_MASK WLAN_GPIO_PIN12_PAD_STRENGTH_MASK
+#define GPIO_PIN12_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN12_PAD_STRENGTH_GET(x)
+#define GPIO_PIN12_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN12_PAD_STRENGTH_SET(x)
+#define GPIO_PIN12_PAD_DRIVER_MSB WLAN_GPIO_PIN12_PAD_DRIVER_MSB
+#define GPIO_PIN12_PAD_DRIVER_LSB WLAN_GPIO_PIN12_PAD_DRIVER_LSB
+#define GPIO_PIN12_PAD_DRIVER_MASK WLAN_GPIO_PIN12_PAD_DRIVER_MASK
+#define GPIO_PIN12_PAD_DRIVER_GET(x) WLAN_GPIO_PIN12_PAD_DRIVER_GET(x)
+#define GPIO_PIN12_PAD_DRIVER_SET(x) WLAN_GPIO_PIN12_PAD_DRIVER_SET(x)
+#define GPIO_PIN12_SOURCE_MSB WLAN_GPIO_PIN12_SOURCE_MSB
+#define GPIO_PIN12_SOURCE_LSB WLAN_GPIO_PIN12_SOURCE_LSB
+#define GPIO_PIN12_SOURCE_MASK WLAN_GPIO_PIN12_SOURCE_MASK
+#define GPIO_PIN12_SOURCE_GET(x) WLAN_GPIO_PIN12_SOURCE_GET(x)
+#define GPIO_PIN12_SOURCE_SET(x) WLAN_GPIO_PIN12_SOURCE_SET(x)
+#define GPIO_PIN13_ADDRESS WLAN_GPIO_PIN13_ADDRESS
+#define GPIO_PIN13_OFFSET WLAN_GPIO_PIN13_OFFSET
+#define GPIO_PIN13_CONFIG_MSB WLAN_GPIO_PIN13_CONFIG_MSB
+#define GPIO_PIN13_CONFIG_LSB WLAN_GPIO_PIN13_CONFIG_LSB
+#define GPIO_PIN13_CONFIG_MASK WLAN_GPIO_PIN13_CONFIG_MASK
+#define GPIO_PIN13_CONFIG_GET(x) WLAN_GPIO_PIN13_CONFIG_GET(x)
+#define GPIO_PIN13_CONFIG_SET(x) WLAN_GPIO_PIN13_CONFIG_SET(x)
+#define GPIO_PIN13_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN13_WAKEUP_ENABLE_MSB
+#define GPIO_PIN13_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN13_WAKEUP_ENABLE_LSB
+#define GPIO_PIN13_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN13_WAKEUP_ENABLE_MASK
+#define GPIO_PIN13_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN13_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN13_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN13_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN13_INT_TYPE_MSB WLAN_GPIO_PIN13_INT_TYPE_MSB
+#define GPIO_PIN13_INT_TYPE_LSB WLAN_GPIO_PIN13_INT_TYPE_LSB
+#define GPIO_PIN13_INT_TYPE_MASK WLAN_GPIO_PIN13_INT_TYPE_MASK
+#define GPIO_PIN13_INT_TYPE_GET(x) WLAN_GPIO_PIN13_INT_TYPE_GET(x)
+#define GPIO_PIN13_INT_TYPE_SET(x) WLAN_GPIO_PIN13_INT_TYPE_SET(x)
+#define GPIO_PIN13_PAD_PULL_MSB WLAN_GPIO_PIN13_PAD_PULL_MSB
+#define GPIO_PIN13_PAD_PULL_LSB WLAN_GPIO_PIN13_PAD_PULL_LSB
+#define GPIO_PIN13_PAD_PULL_MASK WLAN_GPIO_PIN13_PAD_PULL_MASK
+#define GPIO_PIN13_PAD_PULL_GET(x) WLAN_GPIO_PIN13_PAD_PULL_GET(x)
+#define GPIO_PIN13_PAD_PULL_SET(x) WLAN_GPIO_PIN13_PAD_PULL_SET(x)
+#define GPIO_PIN13_PAD_STRENGTH_MSB WLAN_GPIO_PIN13_PAD_STRENGTH_MSB
+#define GPIO_PIN13_PAD_STRENGTH_LSB WLAN_GPIO_PIN13_PAD_STRENGTH_LSB
+#define GPIO_PIN13_PAD_STRENGTH_MASK WLAN_GPIO_PIN13_PAD_STRENGTH_MASK
+#define GPIO_PIN13_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN13_PAD_STRENGTH_GET(x)
+#define GPIO_PIN13_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN13_PAD_STRENGTH_SET(x)
+#define GPIO_PIN13_PAD_DRIVER_MSB WLAN_GPIO_PIN13_PAD_DRIVER_MSB
+#define GPIO_PIN13_PAD_DRIVER_LSB WLAN_GPIO_PIN13_PAD_DRIVER_LSB
+#define GPIO_PIN13_PAD_DRIVER_MASK WLAN_GPIO_PIN13_PAD_DRIVER_MASK
+#define GPIO_PIN13_PAD_DRIVER_GET(x) WLAN_GPIO_PIN13_PAD_DRIVER_GET(x)
+#define GPIO_PIN13_PAD_DRIVER_SET(x) WLAN_GPIO_PIN13_PAD_DRIVER_SET(x)
+#define GPIO_PIN13_SOURCE_MSB WLAN_GPIO_PIN13_SOURCE_MSB
+#define GPIO_PIN13_SOURCE_LSB WLAN_GPIO_PIN13_SOURCE_LSB
+#define GPIO_PIN13_SOURCE_MASK WLAN_GPIO_PIN13_SOURCE_MASK
+#define GPIO_PIN13_SOURCE_GET(x) WLAN_GPIO_PIN13_SOURCE_GET(x)
+#define GPIO_PIN13_SOURCE_SET(x) WLAN_GPIO_PIN13_SOURCE_SET(x)
+#define GPIO_PIN14_ADDRESS WLAN_GPIO_PIN14_ADDRESS
+#define GPIO_PIN14_OFFSET WLAN_GPIO_PIN14_OFFSET
+#define GPIO_PIN14_CONFIG_MSB WLAN_GPIO_PIN14_CONFIG_MSB
+#define GPIO_PIN14_CONFIG_LSB WLAN_GPIO_PIN14_CONFIG_LSB
+#define GPIO_PIN14_CONFIG_MASK WLAN_GPIO_PIN14_CONFIG_MASK
+#define GPIO_PIN14_CONFIG_GET(x) WLAN_GPIO_PIN14_CONFIG_GET(x)
+#define GPIO_PIN14_CONFIG_SET(x) WLAN_GPIO_PIN14_CONFIG_SET(x)
+#define GPIO_PIN14_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN14_WAKEUP_ENABLE_MSB
+#define GPIO_PIN14_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN14_WAKEUP_ENABLE_LSB
+#define GPIO_PIN14_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN14_WAKEUP_ENABLE_MASK
+#define GPIO_PIN14_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN14_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN14_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN14_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN14_INT_TYPE_MSB WLAN_GPIO_PIN14_INT_TYPE_MSB
+#define GPIO_PIN14_INT_TYPE_LSB WLAN_GPIO_PIN14_INT_TYPE_LSB
+#define GPIO_PIN14_INT_TYPE_MASK WLAN_GPIO_PIN14_INT_TYPE_MASK
+#define GPIO_PIN14_INT_TYPE_GET(x) WLAN_GPIO_PIN14_INT_TYPE_GET(x)
+#define GPIO_PIN14_INT_TYPE_SET(x) WLAN_GPIO_PIN14_INT_TYPE_SET(x)
+#define GPIO_PIN14_PAD_PULL_MSB WLAN_GPIO_PIN14_PAD_PULL_MSB
+#define GPIO_PIN14_PAD_PULL_LSB WLAN_GPIO_PIN14_PAD_PULL_LSB
+#define GPIO_PIN14_PAD_PULL_MASK WLAN_GPIO_PIN14_PAD_PULL_MASK
+#define GPIO_PIN14_PAD_PULL_GET(x) WLAN_GPIO_PIN14_PAD_PULL_GET(x)
+#define GPIO_PIN14_PAD_PULL_SET(x) WLAN_GPIO_PIN14_PAD_PULL_SET(x)
+#define GPIO_PIN14_PAD_STRENGTH_MSB WLAN_GPIO_PIN14_PAD_STRENGTH_MSB
+#define GPIO_PIN14_PAD_STRENGTH_LSB WLAN_GPIO_PIN14_PAD_STRENGTH_LSB
+#define GPIO_PIN14_PAD_STRENGTH_MASK WLAN_GPIO_PIN14_PAD_STRENGTH_MASK
+#define GPIO_PIN14_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN14_PAD_STRENGTH_GET(x)
+#define GPIO_PIN14_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN14_PAD_STRENGTH_SET(x)
+#define GPIO_PIN14_PAD_DRIVER_MSB WLAN_GPIO_PIN14_PAD_DRIVER_MSB
+#define GPIO_PIN14_PAD_DRIVER_LSB WLAN_GPIO_PIN14_PAD_DRIVER_LSB
+#define GPIO_PIN14_PAD_DRIVER_MASK WLAN_GPIO_PIN14_PAD_DRIVER_MASK
+#define GPIO_PIN14_PAD_DRIVER_GET(x) WLAN_GPIO_PIN14_PAD_DRIVER_GET(x)
+#define GPIO_PIN14_PAD_DRIVER_SET(x) WLAN_GPIO_PIN14_PAD_DRIVER_SET(x)
+#define GPIO_PIN14_SOURCE_MSB WLAN_GPIO_PIN14_SOURCE_MSB
+#define GPIO_PIN14_SOURCE_LSB WLAN_GPIO_PIN14_SOURCE_LSB
+#define GPIO_PIN14_SOURCE_MASK WLAN_GPIO_PIN14_SOURCE_MASK
+#define GPIO_PIN14_SOURCE_GET(x) WLAN_GPIO_PIN14_SOURCE_GET(x)
+#define GPIO_PIN14_SOURCE_SET(x) WLAN_GPIO_PIN14_SOURCE_SET(x)
+#define GPIO_PIN15_ADDRESS WLAN_GPIO_PIN15_ADDRESS
+#define GPIO_PIN15_OFFSET WLAN_GPIO_PIN15_OFFSET
+#define GPIO_PIN15_CONFIG_MSB WLAN_GPIO_PIN15_CONFIG_MSB
+#define GPIO_PIN15_CONFIG_LSB WLAN_GPIO_PIN15_CONFIG_LSB
+#define GPIO_PIN15_CONFIG_MASK WLAN_GPIO_PIN15_CONFIG_MASK
+#define GPIO_PIN15_CONFIG_GET(x) WLAN_GPIO_PIN15_CONFIG_GET(x)
+#define GPIO_PIN15_CONFIG_SET(x) WLAN_GPIO_PIN15_CONFIG_SET(x)
+#define GPIO_PIN15_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN15_WAKEUP_ENABLE_MSB
+#define GPIO_PIN15_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN15_WAKEUP_ENABLE_LSB
+#define GPIO_PIN15_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN15_WAKEUP_ENABLE_MASK
+#define GPIO_PIN15_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN15_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN15_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN15_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN15_INT_TYPE_MSB WLAN_GPIO_PIN15_INT_TYPE_MSB
+#define GPIO_PIN15_INT_TYPE_LSB WLAN_GPIO_PIN15_INT_TYPE_LSB
+#define GPIO_PIN15_INT_TYPE_MASK WLAN_GPIO_PIN15_INT_TYPE_MASK
+#define GPIO_PIN15_INT_TYPE_GET(x) WLAN_GPIO_PIN15_INT_TYPE_GET(x)
+#define GPIO_PIN15_INT_TYPE_SET(x) WLAN_GPIO_PIN15_INT_TYPE_SET(x)
+#define GPIO_PIN15_PAD_PULL_MSB WLAN_GPIO_PIN15_PAD_PULL_MSB
+#define GPIO_PIN15_PAD_PULL_LSB WLAN_GPIO_PIN15_PAD_PULL_LSB
+#define GPIO_PIN15_PAD_PULL_MASK WLAN_GPIO_PIN15_PAD_PULL_MASK
+#define GPIO_PIN15_PAD_PULL_GET(x) WLAN_GPIO_PIN15_PAD_PULL_GET(x)
+#define GPIO_PIN15_PAD_PULL_SET(x) WLAN_GPIO_PIN15_PAD_PULL_SET(x)
+#define GPIO_PIN15_PAD_STRENGTH_MSB WLAN_GPIO_PIN15_PAD_STRENGTH_MSB
+#define GPIO_PIN15_PAD_STRENGTH_LSB WLAN_GPIO_PIN15_PAD_STRENGTH_LSB
+#define GPIO_PIN15_PAD_STRENGTH_MASK WLAN_GPIO_PIN15_PAD_STRENGTH_MASK
+#define GPIO_PIN15_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN15_PAD_STRENGTH_GET(x)
+#define GPIO_PIN15_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN15_PAD_STRENGTH_SET(x)
+#define GPIO_PIN15_PAD_DRIVER_MSB WLAN_GPIO_PIN15_PAD_DRIVER_MSB
+#define GPIO_PIN15_PAD_DRIVER_LSB WLAN_GPIO_PIN15_PAD_DRIVER_LSB
+#define GPIO_PIN15_PAD_DRIVER_MASK WLAN_GPIO_PIN15_PAD_DRIVER_MASK
+#define GPIO_PIN15_PAD_DRIVER_GET(x) WLAN_GPIO_PIN15_PAD_DRIVER_GET(x)
+#define GPIO_PIN15_PAD_DRIVER_SET(x) WLAN_GPIO_PIN15_PAD_DRIVER_SET(x)
+#define GPIO_PIN15_SOURCE_MSB WLAN_GPIO_PIN15_SOURCE_MSB
+#define GPIO_PIN15_SOURCE_LSB WLAN_GPIO_PIN15_SOURCE_LSB
+#define GPIO_PIN15_SOURCE_MASK WLAN_GPIO_PIN15_SOURCE_MASK
+#define GPIO_PIN15_SOURCE_GET(x) WLAN_GPIO_PIN15_SOURCE_GET(x)
+#define GPIO_PIN15_SOURCE_SET(x) WLAN_GPIO_PIN15_SOURCE_SET(x)
+#define GPIO_PIN16_ADDRESS WLAN_GPIO_PIN16_ADDRESS
+#define GPIO_PIN16_OFFSET WLAN_GPIO_PIN16_OFFSET
+#define GPIO_PIN16_CONFIG_MSB WLAN_GPIO_PIN16_CONFIG_MSB
+#define GPIO_PIN16_CONFIG_LSB WLAN_GPIO_PIN16_CONFIG_LSB
+#define GPIO_PIN16_CONFIG_MASK WLAN_GPIO_PIN16_CONFIG_MASK
+#define GPIO_PIN16_CONFIG_GET(x) WLAN_GPIO_PIN16_CONFIG_GET(x)
+#define GPIO_PIN16_CONFIG_SET(x) WLAN_GPIO_PIN16_CONFIG_SET(x)
+#define GPIO_PIN16_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN16_WAKEUP_ENABLE_MSB
+#define GPIO_PIN16_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN16_WAKEUP_ENABLE_LSB
+#define GPIO_PIN16_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN16_WAKEUP_ENABLE_MASK
+#define GPIO_PIN16_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN16_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN16_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN16_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN16_INT_TYPE_MSB WLAN_GPIO_PIN16_INT_TYPE_MSB
+#define GPIO_PIN16_INT_TYPE_LSB WLAN_GPIO_PIN16_INT_TYPE_LSB
+#define GPIO_PIN16_INT_TYPE_MASK WLAN_GPIO_PIN16_INT_TYPE_MASK
+#define GPIO_PIN16_INT_TYPE_GET(x) WLAN_GPIO_PIN16_INT_TYPE_GET(x)
+#define GPIO_PIN16_INT_TYPE_SET(x) WLAN_GPIO_PIN16_INT_TYPE_SET(x)
+#define GPIO_PIN16_PAD_PULL_MSB WLAN_GPIO_PIN16_PAD_PULL_MSB
+#define GPIO_PIN16_PAD_PULL_LSB WLAN_GPIO_PIN16_PAD_PULL_LSB
+#define GPIO_PIN16_PAD_PULL_MASK WLAN_GPIO_PIN16_PAD_PULL_MASK
+#define GPIO_PIN16_PAD_PULL_GET(x) WLAN_GPIO_PIN16_PAD_PULL_GET(x)
+#define GPIO_PIN16_PAD_PULL_SET(x) WLAN_GPIO_PIN16_PAD_PULL_SET(x)
+#define GPIO_PIN16_PAD_STRENGTH_MSB WLAN_GPIO_PIN16_PAD_STRENGTH_MSB
+#define GPIO_PIN16_PAD_STRENGTH_LSB WLAN_GPIO_PIN16_PAD_STRENGTH_LSB
+#define GPIO_PIN16_PAD_STRENGTH_MASK WLAN_GPIO_PIN16_PAD_STRENGTH_MASK
+#define GPIO_PIN16_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN16_PAD_STRENGTH_GET(x)
+#define GPIO_PIN16_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN16_PAD_STRENGTH_SET(x)
+#define GPIO_PIN16_PAD_DRIVER_MSB WLAN_GPIO_PIN16_PAD_DRIVER_MSB
+#define GPIO_PIN16_PAD_DRIVER_LSB WLAN_GPIO_PIN16_PAD_DRIVER_LSB
+#define GPIO_PIN16_PAD_DRIVER_MASK WLAN_GPIO_PIN16_PAD_DRIVER_MASK
+#define GPIO_PIN16_PAD_DRIVER_GET(x) WLAN_GPIO_PIN16_PAD_DRIVER_GET(x)
+#define GPIO_PIN16_PAD_DRIVER_SET(x) WLAN_GPIO_PIN16_PAD_DRIVER_SET(x)
+#define GPIO_PIN16_SOURCE_MSB WLAN_GPIO_PIN16_SOURCE_MSB
+#define GPIO_PIN16_SOURCE_LSB WLAN_GPIO_PIN16_SOURCE_LSB
+#define GPIO_PIN16_SOURCE_MASK WLAN_GPIO_PIN16_SOURCE_MASK
+#define GPIO_PIN16_SOURCE_GET(x) WLAN_GPIO_PIN16_SOURCE_GET(x)
+#define GPIO_PIN16_SOURCE_SET(x) WLAN_GPIO_PIN16_SOURCE_SET(x)
+#define GPIO_PIN17_ADDRESS WLAN_GPIO_PIN17_ADDRESS
+#define GPIO_PIN17_OFFSET WLAN_GPIO_PIN17_OFFSET
+#define GPIO_PIN17_CONFIG_MSB WLAN_GPIO_PIN17_CONFIG_MSB
+#define GPIO_PIN17_CONFIG_LSB WLAN_GPIO_PIN17_CONFIG_LSB
+#define GPIO_PIN17_CONFIG_MASK WLAN_GPIO_PIN17_CONFIG_MASK
+#define GPIO_PIN17_CONFIG_GET(x) WLAN_GPIO_PIN17_CONFIG_GET(x)
+#define GPIO_PIN17_CONFIG_SET(x) WLAN_GPIO_PIN17_CONFIG_SET(x)
+#define GPIO_PIN17_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN17_WAKEUP_ENABLE_MSB
+#define GPIO_PIN17_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN17_WAKEUP_ENABLE_LSB
+#define GPIO_PIN17_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN17_WAKEUP_ENABLE_MASK
+#define GPIO_PIN17_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN17_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN17_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN17_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN17_INT_TYPE_MSB WLAN_GPIO_PIN17_INT_TYPE_MSB
+#define GPIO_PIN17_INT_TYPE_LSB WLAN_GPIO_PIN17_INT_TYPE_LSB
+#define GPIO_PIN17_INT_TYPE_MASK WLAN_GPIO_PIN17_INT_TYPE_MASK
+#define GPIO_PIN17_INT_TYPE_GET(x) WLAN_GPIO_PIN17_INT_TYPE_GET(x)
+#define GPIO_PIN17_INT_TYPE_SET(x) WLAN_GPIO_PIN17_INT_TYPE_SET(x)
+#define GPIO_PIN17_PAD_PULL_MSB WLAN_GPIO_PIN17_PAD_PULL_MSB
+#define GPIO_PIN17_PAD_PULL_LSB WLAN_GPIO_PIN17_PAD_PULL_LSB
+#define GPIO_PIN17_PAD_PULL_MASK WLAN_GPIO_PIN17_PAD_PULL_MASK
+#define GPIO_PIN17_PAD_PULL_GET(x) WLAN_GPIO_PIN17_PAD_PULL_GET(x)
+#define GPIO_PIN17_PAD_PULL_SET(x) WLAN_GPIO_PIN17_PAD_PULL_SET(x)
+#define GPIO_PIN17_PAD_STRENGTH_MSB WLAN_GPIO_PIN17_PAD_STRENGTH_MSB
+#define GPIO_PIN17_PAD_STRENGTH_LSB WLAN_GPIO_PIN17_PAD_STRENGTH_LSB
+#define GPIO_PIN17_PAD_STRENGTH_MASK WLAN_GPIO_PIN17_PAD_STRENGTH_MASK
+#define GPIO_PIN17_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN17_PAD_STRENGTH_GET(x)
+#define GPIO_PIN17_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN17_PAD_STRENGTH_SET(x)
+#define GPIO_PIN17_PAD_DRIVER_MSB WLAN_GPIO_PIN17_PAD_DRIVER_MSB
+#define GPIO_PIN17_PAD_DRIVER_LSB WLAN_GPIO_PIN17_PAD_DRIVER_LSB
+#define GPIO_PIN17_PAD_DRIVER_MASK WLAN_GPIO_PIN17_PAD_DRIVER_MASK
+#define GPIO_PIN17_PAD_DRIVER_GET(x) WLAN_GPIO_PIN17_PAD_DRIVER_GET(x)
+#define GPIO_PIN17_PAD_DRIVER_SET(x) WLAN_GPIO_PIN17_PAD_DRIVER_SET(x)
+#define GPIO_PIN17_SOURCE_MSB WLAN_GPIO_PIN17_SOURCE_MSB
+#define GPIO_PIN17_SOURCE_LSB WLAN_GPIO_PIN17_SOURCE_LSB
+#define GPIO_PIN17_SOURCE_MASK WLAN_GPIO_PIN17_SOURCE_MASK
+#define GPIO_PIN17_SOURCE_GET(x) WLAN_GPIO_PIN17_SOURCE_GET(x)
+#define GPIO_PIN17_SOURCE_SET(x) WLAN_GPIO_PIN17_SOURCE_SET(x)
+#define GPIO_PIN18_ADDRESS WLAN_GPIO_PIN18_ADDRESS
+#define GPIO_PIN18_OFFSET WLAN_GPIO_PIN18_OFFSET
+#define GPIO_PIN18_CONFIG_MSB WLAN_GPIO_PIN18_CONFIG_MSB
+#define GPIO_PIN18_CONFIG_LSB WLAN_GPIO_PIN18_CONFIG_LSB
+#define GPIO_PIN18_CONFIG_MASK WLAN_GPIO_PIN18_CONFIG_MASK
+#define GPIO_PIN18_CONFIG_GET(x) WLAN_GPIO_PIN18_CONFIG_GET(x)
+#define GPIO_PIN18_CONFIG_SET(x) WLAN_GPIO_PIN18_CONFIG_SET(x)
+#define GPIO_PIN18_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN18_WAKEUP_ENABLE_MSB
+#define GPIO_PIN18_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN18_WAKEUP_ENABLE_LSB
+#define GPIO_PIN18_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN18_WAKEUP_ENABLE_MASK
+#define GPIO_PIN18_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN18_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN18_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN18_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN18_INT_TYPE_MSB WLAN_GPIO_PIN18_INT_TYPE_MSB
+#define GPIO_PIN18_INT_TYPE_LSB WLAN_GPIO_PIN18_INT_TYPE_LSB
+#define GPIO_PIN18_INT_TYPE_MASK WLAN_GPIO_PIN18_INT_TYPE_MASK
+#define GPIO_PIN18_INT_TYPE_GET(x) WLAN_GPIO_PIN18_INT_TYPE_GET(x)
+#define GPIO_PIN18_INT_TYPE_SET(x) WLAN_GPIO_PIN18_INT_TYPE_SET(x)
+#define GPIO_PIN18_PAD_PULL_MSB WLAN_GPIO_PIN18_PAD_PULL_MSB
+#define GPIO_PIN18_PAD_PULL_LSB WLAN_GPIO_PIN18_PAD_PULL_LSB
+#define GPIO_PIN18_PAD_PULL_MASK WLAN_GPIO_PIN18_PAD_PULL_MASK
+#define GPIO_PIN18_PAD_PULL_GET(x) WLAN_GPIO_PIN18_PAD_PULL_GET(x)
+#define GPIO_PIN18_PAD_PULL_SET(x) WLAN_GPIO_PIN18_PAD_PULL_SET(x)
+#define GPIO_PIN18_PAD_STRENGTH_MSB WLAN_GPIO_PIN18_PAD_STRENGTH_MSB
+#define GPIO_PIN18_PAD_STRENGTH_LSB WLAN_GPIO_PIN18_PAD_STRENGTH_LSB
+#define GPIO_PIN18_PAD_STRENGTH_MASK WLAN_GPIO_PIN18_PAD_STRENGTH_MASK
+#define GPIO_PIN18_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN18_PAD_STRENGTH_GET(x)
+#define GPIO_PIN18_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN18_PAD_STRENGTH_SET(x)
+#define GPIO_PIN18_PAD_DRIVER_MSB WLAN_GPIO_PIN18_PAD_DRIVER_MSB
+#define GPIO_PIN18_PAD_DRIVER_LSB WLAN_GPIO_PIN18_PAD_DRIVER_LSB
+#define GPIO_PIN18_PAD_DRIVER_MASK WLAN_GPIO_PIN18_PAD_DRIVER_MASK
+#define GPIO_PIN18_PAD_DRIVER_GET(x) WLAN_GPIO_PIN18_PAD_DRIVER_GET(x)
+#define GPIO_PIN18_PAD_DRIVER_SET(x) WLAN_GPIO_PIN18_PAD_DRIVER_SET(x)
+#define GPIO_PIN18_SOURCE_MSB WLAN_GPIO_PIN18_SOURCE_MSB
+#define GPIO_PIN18_SOURCE_LSB WLAN_GPIO_PIN18_SOURCE_LSB
+#define GPIO_PIN18_SOURCE_MASK WLAN_GPIO_PIN18_SOURCE_MASK
+#define GPIO_PIN18_SOURCE_GET(x) WLAN_GPIO_PIN18_SOURCE_GET(x)
+#define GPIO_PIN18_SOURCE_SET(x) WLAN_GPIO_PIN18_SOURCE_SET(x)
+#define GPIO_PIN19_ADDRESS WLAN_GPIO_PIN19_ADDRESS
+#define GPIO_PIN19_OFFSET WLAN_GPIO_PIN19_OFFSET
+#define GPIO_PIN19_CONFIG_MSB WLAN_GPIO_PIN19_CONFIG_MSB
+#define GPIO_PIN19_CONFIG_LSB WLAN_GPIO_PIN19_CONFIG_LSB
+#define GPIO_PIN19_CONFIG_MASK WLAN_GPIO_PIN19_CONFIG_MASK
+#define GPIO_PIN19_CONFIG_GET(x) WLAN_GPIO_PIN19_CONFIG_GET(x)
+#define GPIO_PIN19_CONFIG_SET(x) WLAN_GPIO_PIN19_CONFIG_SET(x)
+#define GPIO_PIN19_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN19_WAKEUP_ENABLE_MSB
+#define GPIO_PIN19_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN19_WAKEUP_ENABLE_LSB
+#define GPIO_PIN19_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN19_WAKEUP_ENABLE_MASK
+#define GPIO_PIN19_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN19_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN19_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN19_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN19_INT_TYPE_MSB WLAN_GPIO_PIN19_INT_TYPE_MSB
+#define GPIO_PIN19_INT_TYPE_LSB WLAN_GPIO_PIN19_INT_TYPE_LSB
+#define GPIO_PIN19_INT_TYPE_MASK WLAN_GPIO_PIN19_INT_TYPE_MASK
+#define GPIO_PIN19_INT_TYPE_GET(x) WLAN_GPIO_PIN19_INT_TYPE_GET(x)
+#define GPIO_PIN19_INT_TYPE_SET(x) WLAN_GPIO_PIN19_INT_TYPE_SET(x)
+#define GPIO_PIN19_PAD_PULL_MSB WLAN_GPIO_PIN19_PAD_PULL_MSB
+#define GPIO_PIN19_PAD_PULL_LSB WLAN_GPIO_PIN19_PAD_PULL_LSB
+#define GPIO_PIN19_PAD_PULL_MASK WLAN_GPIO_PIN19_PAD_PULL_MASK
+#define GPIO_PIN19_PAD_PULL_GET(x) WLAN_GPIO_PIN19_PAD_PULL_GET(x)
+#define GPIO_PIN19_PAD_PULL_SET(x) WLAN_GPIO_PIN19_PAD_PULL_SET(x)
+#define GPIO_PIN19_PAD_STRENGTH_MSB WLAN_GPIO_PIN19_PAD_STRENGTH_MSB
+#define GPIO_PIN19_PAD_STRENGTH_LSB WLAN_GPIO_PIN19_PAD_STRENGTH_LSB
+#define GPIO_PIN19_PAD_STRENGTH_MASK WLAN_GPIO_PIN19_PAD_STRENGTH_MASK
+#define GPIO_PIN19_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN19_PAD_STRENGTH_GET(x)
+#define GPIO_PIN19_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN19_PAD_STRENGTH_SET(x)
+#define GPIO_PIN19_PAD_DRIVER_MSB WLAN_GPIO_PIN19_PAD_DRIVER_MSB
+#define GPIO_PIN19_PAD_DRIVER_LSB WLAN_GPIO_PIN19_PAD_DRIVER_LSB
+#define GPIO_PIN19_PAD_DRIVER_MASK WLAN_GPIO_PIN19_PAD_DRIVER_MASK
+#define GPIO_PIN19_PAD_DRIVER_GET(x) WLAN_GPIO_PIN19_PAD_DRIVER_GET(x)
+#define GPIO_PIN19_PAD_DRIVER_SET(x) WLAN_GPIO_PIN19_PAD_DRIVER_SET(x)
+#define GPIO_PIN19_SOURCE_MSB WLAN_GPIO_PIN19_SOURCE_MSB
+#define GPIO_PIN19_SOURCE_LSB WLAN_GPIO_PIN19_SOURCE_LSB
+#define GPIO_PIN19_SOURCE_MASK WLAN_GPIO_PIN19_SOURCE_MASK
+#define GPIO_PIN19_SOURCE_GET(x) WLAN_GPIO_PIN19_SOURCE_GET(x)
+#define GPIO_PIN19_SOURCE_SET(x) WLAN_GPIO_PIN19_SOURCE_SET(x)
+#define GPIO_PIN20_ADDRESS WLAN_GPIO_PIN20_ADDRESS
+#define GPIO_PIN20_OFFSET WLAN_GPIO_PIN20_OFFSET
+#define GPIO_PIN20_CONFIG_MSB WLAN_GPIO_PIN20_CONFIG_MSB
+#define GPIO_PIN20_CONFIG_LSB WLAN_GPIO_PIN20_CONFIG_LSB
+#define GPIO_PIN20_CONFIG_MASK WLAN_GPIO_PIN20_CONFIG_MASK
+#define GPIO_PIN20_CONFIG_GET(x) WLAN_GPIO_PIN20_CONFIG_GET(x)
+#define GPIO_PIN20_CONFIG_SET(x) WLAN_GPIO_PIN20_CONFIG_SET(x)
+#define GPIO_PIN20_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN20_WAKEUP_ENABLE_MSB
+#define GPIO_PIN20_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN20_WAKEUP_ENABLE_LSB
+#define GPIO_PIN20_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN20_WAKEUP_ENABLE_MASK
+#define GPIO_PIN20_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN20_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN20_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN20_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN20_INT_TYPE_MSB WLAN_GPIO_PIN20_INT_TYPE_MSB
+#define GPIO_PIN20_INT_TYPE_LSB WLAN_GPIO_PIN20_INT_TYPE_LSB
+#define GPIO_PIN20_INT_TYPE_MASK WLAN_GPIO_PIN20_INT_TYPE_MASK
+#define GPIO_PIN20_INT_TYPE_GET(x) WLAN_GPIO_PIN20_INT_TYPE_GET(x)
+#define GPIO_PIN20_INT_TYPE_SET(x) WLAN_GPIO_PIN20_INT_TYPE_SET(x)
+#define GPIO_PIN20_PAD_PULL_MSB WLAN_GPIO_PIN20_PAD_PULL_MSB
+#define GPIO_PIN20_PAD_PULL_LSB WLAN_GPIO_PIN20_PAD_PULL_LSB
+#define GPIO_PIN20_PAD_PULL_MASK WLAN_GPIO_PIN20_PAD_PULL_MASK
+#define GPIO_PIN20_PAD_PULL_GET(x) WLAN_GPIO_PIN20_PAD_PULL_GET(x)
+#define GPIO_PIN20_PAD_PULL_SET(x) WLAN_GPIO_PIN20_PAD_PULL_SET(x)
+#define GPIO_PIN20_PAD_STRENGTH_MSB WLAN_GPIO_PIN20_PAD_STRENGTH_MSB
+#define GPIO_PIN20_PAD_STRENGTH_LSB WLAN_GPIO_PIN20_PAD_STRENGTH_LSB
+#define GPIO_PIN20_PAD_STRENGTH_MASK WLAN_GPIO_PIN20_PAD_STRENGTH_MASK
+#define GPIO_PIN20_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN20_PAD_STRENGTH_GET(x)
+#define GPIO_PIN20_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN20_PAD_STRENGTH_SET(x)
+#define GPIO_PIN20_PAD_DRIVER_MSB WLAN_GPIO_PIN20_PAD_DRIVER_MSB
+#define GPIO_PIN20_PAD_DRIVER_LSB WLAN_GPIO_PIN20_PAD_DRIVER_LSB
+#define GPIO_PIN20_PAD_DRIVER_MASK WLAN_GPIO_PIN20_PAD_DRIVER_MASK
+#define GPIO_PIN20_PAD_DRIVER_GET(x) WLAN_GPIO_PIN20_PAD_DRIVER_GET(x)
+#define GPIO_PIN20_PAD_DRIVER_SET(x) WLAN_GPIO_PIN20_PAD_DRIVER_SET(x)
+#define GPIO_PIN20_SOURCE_MSB WLAN_GPIO_PIN20_SOURCE_MSB
+#define GPIO_PIN20_SOURCE_LSB WLAN_GPIO_PIN20_SOURCE_LSB
+#define GPIO_PIN20_SOURCE_MASK WLAN_GPIO_PIN20_SOURCE_MASK
+#define GPIO_PIN20_SOURCE_GET(x) WLAN_GPIO_PIN20_SOURCE_GET(x)
+#define GPIO_PIN20_SOURCE_SET(x) WLAN_GPIO_PIN20_SOURCE_SET(x)
+#define GPIO_PIN21_ADDRESS WLAN_GPIO_PIN21_ADDRESS
+#define GPIO_PIN21_OFFSET WLAN_GPIO_PIN21_OFFSET
+#define GPIO_PIN21_CONFIG_MSB WLAN_GPIO_PIN21_CONFIG_MSB
+#define GPIO_PIN21_CONFIG_LSB WLAN_GPIO_PIN21_CONFIG_LSB
+#define GPIO_PIN21_CONFIG_MASK WLAN_GPIO_PIN21_CONFIG_MASK
+#define GPIO_PIN21_CONFIG_GET(x) WLAN_GPIO_PIN21_CONFIG_GET(x)
+#define GPIO_PIN21_CONFIG_SET(x) WLAN_GPIO_PIN21_CONFIG_SET(x)
+#define GPIO_PIN21_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN21_WAKEUP_ENABLE_MSB
+#define GPIO_PIN21_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN21_WAKEUP_ENABLE_LSB
+#define GPIO_PIN21_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN21_WAKEUP_ENABLE_MASK
+#define GPIO_PIN21_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN21_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN21_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN21_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN21_INT_TYPE_MSB WLAN_GPIO_PIN21_INT_TYPE_MSB
+#define GPIO_PIN21_INT_TYPE_LSB WLAN_GPIO_PIN21_INT_TYPE_LSB
+#define GPIO_PIN21_INT_TYPE_MASK WLAN_GPIO_PIN21_INT_TYPE_MASK
+#define GPIO_PIN21_INT_TYPE_GET(x) WLAN_GPIO_PIN21_INT_TYPE_GET(x)
+#define GPIO_PIN21_INT_TYPE_SET(x) WLAN_GPIO_PIN21_INT_TYPE_SET(x)
+#define GPIO_PIN21_PAD_PULL_MSB WLAN_GPIO_PIN21_PAD_PULL_MSB
+#define GPIO_PIN21_PAD_PULL_LSB WLAN_GPIO_PIN21_PAD_PULL_LSB
+#define GPIO_PIN21_PAD_PULL_MASK WLAN_GPIO_PIN21_PAD_PULL_MASK
+#define GPIO_PIN21_PAD_PULL_GET(x) WLAN_GPIO_PIN21_PAD_PULL_GET(x)
+#define GPIO_PIN21_PAD_PULL_SET(x) WLAN_GPIO_PIN21_PAD_PULL_SET(x)
+#define GPIO_PIN21_PAD_STRENGTH_MSB WLAN_GPIO_PIN21_PAD_STRENGTH_MSB
+#define GPIO_PIN21_PAD_STRENGTH_LSB WLAN_GPIO_PIN21_PAD_STRENGTH_LSB
+#define GPIO_PIN21_PAD_STRENGTH_MASK WLAN_GPIO_PIN21_PAD_STRENGTH_MASK
+#define GPIO_PIN21_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN21_PAD_STRENGTH_GET(x)
+#define GPIO_PIN21_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN21_PAD_STRENGTH_SET(x)
+#define GPIO_PIN21_PAD_DRIVER_MSB WLAN_GPIO_PIN21_PAD_DRIVER_MSB
+#define GPIO_PIN21_PAD_DRIVER_LSB WLAN_GPIO_PIN21_PAD_DRIVER_LSB
+#define GPIO_PIN21_PAD_DRIVER_MASK WLAN_GPIO_PIN21_PAD_DRIVER_MASK
+#define GPIO_PIN21_PAD_DRIVER_GET(x) WLAN_GPIO_PIN21_PAD_DRIVER_GET(x)
+#define GPIO_PIN21_PAD_DRIVER_SET(x) WLAN_GPIO_PIN21_PAD_DRIVER_SET(x)
+#define GPIO_PIN21_SOURCE_MSB WLAN_GPIO_PIN21_SOURCE_MSB
+#define GPIO_PIN21_SOURCE_LSB WLAN_GPIO_PIN21_SOURCE_LSB
+#define GPIO_PIN21_SOURCE_MASK WLAN_GPIO_PIN21_SOURCE_MASK
+#define GPIO_PIN21_SOURCE_GET(x) WLAN_GPIO_PIN21_SOURCE_GET(x)
+#define GPIO_PIN21_SOURCE_SET(x) WLAN_GPIO_PIN21_SOURCE_SET(x)
+#define GPIO_PIN22_ADDRESS WLAN_GPIO_PIN22_ADDRESS
+#define GPIO_PIN22_OFFSET WLAN_GPIO_PIN22_OFFSET
+#define GPIO_PIN22_CONFIG_MSB WLAN_GPIO_PIN22_CONFIG_MSB
+#define GPIO_PIN22_CONFIG_LSB WLAN_GPIO_PIN22_CONFIG_LSB
+#define GPIO_PIN22_CONFIG_MASK WLAN_GPIO_PIN22_CONFIG_MASK
+#define GPIO_PIN22_CONFIG_GET(x) WLAN_GPIO_PIN22_CONFIG_GET(x)
+#define GPIO_PIN22_CONFIG_SET(x) WLAN_GPIO_PIN22_CONFIG_SET(x)
+#define GPIO_PIN22_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN22_WAKEUP_ENABLE_MSB
+#define GPIO_PIN22_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN22_WAKEUP_ENABLE_LSB
+#define GPIO_PIN22_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN22_WAKEUP_ENABLE_MASK
+#define GPIO_PIN22_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN22_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN22_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN22_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN22_INT_TYPE_MSB WLAN_GPIO_PIN22_INT_TYPE_MSB
+#define GPIO_PIN22_INT_TYPE_LSB WLAN_GPIO_PIN22_INT_TYPE_LSB
+#define GPIO_PIN22_INT_TYPE_MASK WLAN_GPIO_PIN22_INT_TYPE_MASK
+#define GPIO_PIN22_INT_TYPE_GET(x) WLAN_GPIO_PIN22_INT_TYPE_GET(x)
+#define GPIO_PIN22_INT_TYPE_SET(x) WLAN_GPIO_PIN22_INT_TYPE_SET(x)
+#define GPIO_PIN22_PAD_PULL_MSB WLAN_GPIO_PIN22_PAD_PULL_MSB
+#define GPIO_PIN22_PAD_PULL_LSB WLAN_GPIO_PIN22_PAD_PULL_LSB
+#define GPIO_PIN22_PAD_PULL_MASK WLAN_GPIO_PIN22_PAD_PULL_MASK
+#define GPIO_PIN22_PAD_PULL_GET(x) WLAN_GPIO_PIN22_PAD_PULL_GET(x)
+#define GPIO_PIN22_PAD_PULL_SET(x) WLAN_GPIO_PIN22_PAD_PULL_SET(x)
+#define GPIO_PIN22_PAD_STRENGTH_MSB WLAN_GPIO_PIN22_PAD_STRENGTH_MSB
+#define GPIO_PIN22_PAD_STRENGTH_LSB WLAN_GPIO_PIN22_PAD_STRENGTH_LSB
+#define GPIO_PIN22_PAD_STRENGTH_MASK WLAN_GPIO_PIN22_PAD_STRENGTH_MASK
+#define GPIO_PIN22_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN22_PAD_STRENGTH_GET(x)
+#define GPIO_PIN22_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN22_PAD_STRENGTH_SET(x)
+#define GPIO_PIN22_PAD_DRIVER_MSB WLAN_GPIO_PIN22_PAD_DRIVER_MSB
+#define GPIO_PIN22_PAD_DRIVER_LSB WLAN_GPIO_PIN22_PAD_DRIVER_LSB
+#define GPIO_PIN22_PAD_DRIVER_MASK WLAN_GPIO_PIN22_PAD_DRIVER_MASK
+#define GPIO_PIN22_PAD_DRIVER_GET(x) WLAN_GPIO_PIN22_PAD_DRIVER_GET(x)
+#define GPIO_PIN22_PAD_DRIVER_SET(x) WLAN_GPIO_PIN22_PAD_DRIVER_SET(x)
+#define GPIO_PIN22_SOURCE_MSB WLAN_GPIO_PIN22_SOURCE_MSB
+#define GPIO_PIN22_SOURCE_LSB WLAN_GPIO_PIN22_SOURCE_LSB
+#define GPIO_PIN22_SOURCE_MASK WLAN_GPIO_PIN22_SOURCE_MASK
+#define GPIO_PIN22_SOURCE_GET(x) WLAN_GPIO_PIN22_SOURCE_GET(x)
+#define GPIO_PIN22_SOURCE_SET(x) WLAN_GPIO_PIN22_SOURCE_SET(x)
+#define GPIO_PIN23_ADDRESS WLAN_GPIO_PIN23_ADDRESS
+#define GPIO_PIN23_OFFSET WLAN_GPIO_PIN23_OFFSET
+#define GPIO_PIN23_CONFIG_MSB WLAN_GPIO_PIN23_CONFIG_MSB
+#define GPIO_PIN23_CONFIG_LSB WLAN_GPIO_PIN23_CONFIG_LSB
+#define GPIO_PIN23_CONFIG_MASK WLAN_GPIO_PIN23_CONFIG_MASK
+#define GPIO_PIN23_CONFIG_GET(x) WLAN_GPIO_PIN23_CONFIG_GET(x)
+#define GPIO_PIN23_CONFIG_SET(x) WLAN_GPIO_PIN23_CONFIG_SET(x)
+#define GPIO_PIN23_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN23_WAKEUP_ENABLE_MSB
+#define GPIO_PIN23_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN23_WAKEUP_ENABLE_LSB
+#define GPIO_PIN23_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN23_WAKEUP_ENABLE_MASK
+#define GPIO_PIN23_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN23_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN23_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN23_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN23_INT_TYPE_MSB WLAN_GPIO_PIN23_INT_TYPE_MSB
+#define GPIO_PIN23_INT_TYPE_LSB WLAN_GPIO_PIN23_INT_TYPE_LSB
+#define GPIO_PIN23_INT_TYPE_MASK WLAN_GPIO_PIN23_INT_TYPE_MASK
+#define GPIO_PIN23_INT_TYPE_GET(x) WLAN_GPIO_PIN23_INT_TYPE_GET(x)
+#define GPIO_PIN23_INT_TYPE_SET(x) WLAN_GPIO_PIN23_INT_TYPE_SET(x)
+#define GPIO_PIN23_PAD_DRIVER_MSB WLAN_GPIO_PIN23_PAD_DRIVER_MSB
+#define GPIO_PIN23_PAD_DRIVER_LSB WLAN_GPIO_PIN23_PAD_DRIVER_LSB
+#define GPIO_PIN23_PAD_DRIVER_MASK WLAN_GPIO_PIN23_PAD_DRIVER_MASK
+#define GPIO_PIN23_PAD_DRIVER_GET(x) WLAN_GPIO_PIN23_PAD_DRIVER_GET(x)
+#define GPIO_PIN23_PAD_DRIVER_SET(x) WLAN_GPIO_PIN23_PAD_DRIVER_SET(x)
+#define GPIO_PIN23_SOURCE_MSB WLAN_GPIO_PIN23_SOURCE_MSB
+#define GPIO_PIN23_SOURCE_LSB WLAN_GPIO_PIN23_SOURCE_LSB
+#define GPIO_PIN23_SOURCE_MASK WLAN_GPIO_PIN23_SOURCE_MASK
+#define GPIO_PIN23_SOURCE_GET(x) WLAN_GPIO_PIN23_SOURCE_GET(x)
+#define GPIO_PIN23_SOURCE_SET(x) WLAN_GPIO_PIN23_SOURCE_SET(x)
+#define GPIO_PIN24_ADDRESS WLAN_GPIO_PIN24_ADDRESS
+#define GPIO_PIN24_OFFSET WLAN_GPIO_PIN24_OFFSET
+#define GPIO_PIN24_CONFIG_MSB WLAN_GPIO_PIN24_CONFIG_MSB
+#define GPIO_PIN24_CONFIG_LSB WLAN_GPIO_PIN24_CONFIG_LSB
+#define GPIO_PIN24_CONFIG_MASK WLAN_GPIO_PIN24_CONFIG_MASK
+#define GPIO_PIN24_CONFIG_GET(x) WLAN_GPIO_PIN24_CONFIG_GET(x)
+#define GPIO_PIN24_CONFIG_SET(x) WLAN_GPIO_PIN24_CONFIG_SET(x)
+#define GPIO_PIN24_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN24_WAKEUP_ENABLE_MSB
+#define GPIO_PIN24_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN24_WAKEUP_ENABLE_LSB
+#define GPIO_PIN24_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN24_WAKEUP_ENABLE_MASK
+#define GPIO_PIN24_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN24_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN24_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN24_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN24_INT_TYPE_MSB WLAN_GPIO_PIN24_INT_TYPE_MSB
+#define GPIO_PIN24_INT_TYPE_LSB WLAN_GPIO_PIN24_INT_TYPE_LSB
+#define GPIO_PIN24_INT_TYPE_MASK WLAN_GPIO_PIN24_INT_TYPE_MASK
+#define GPIO_PIN24_INT_TYPE_GET(x) WLAN_GPIO_PIN24_INT_TYPE_GET(x)
+#define GPIO_PIN24_INT_TYPE_SET(x) WLAN_GPIO_PIN24_INT_TYPE_SET(x)
+#define GPIO_PIN24_PAD_DRIVER_MSB WLAN_GPIO_PIN24_PAD_DRIVER_MSB
+#define GPIO_PIN24_PAD_DRIVER_LSB WLAN_GPIO_PIN24_PAD_DRIVER_LSB
+#define GPIO_PIN24_PAD_DRIVER_MASK WLAN_GPIO_PIN24_PAD_DRIVER_MASK
+#define GPIO_PIN24_PAD_DRIVER_GET(x) WLAN_GPIO_PIN24_PAD_DRIVER_GET(x)
+#define GPIO_PIN24_PAD_DRIVER_SET(x) WLAN_GPIO_PIN24_PAD_DRIVER_SET(x)
+#define GPIO_PIN24_SOURCE_MSB WLAN_GPIO_PIN24_SOURCE_MSB
+#define GPIO_PIN24_SOURCE_LSB WLAN_GPIO_PIN24_SOURCE_LSB
+#define GPIO_PIN24_SOURCE_MASK WLAN_GPIO_PIN24_SOURCE_MASK
+#define GPIO_PIN24_SOURCE_GET(x) WLAN_GPIO_PIN24_SOURCE_GET(x)
+#define GPIO_PIN24_SOURCE_SET(x) WLAN_GPIO_PIN24_SOURCE_SET(x)
+#define GPIO_PIN25_ADDRESS WLAN_GPIO_PIN25_ADDRESS
+#define GPIO_PIN25_OFFSET WLAN_GPIO_PIN25_OFFSET
+#define GPIO_PIN25_CONFIG_MSB WLAN_GPIO_PIN25_CONFIG_MSB
+#define GPIO_PIN25_CONFIG_LSB WLAN_GPIO_PIN25_CONFIG_LSB
+#define GPIO_PIN25_CONFIG_MASK WLAN_GPIO_PIN25_CONFIG_MASK
+#define GPIO_PIN25_CONFIG_GET(x) WLAN_GPIO_PIN25_CONFIG_GET(x)
+#define GPIO_PIN25_CONFIG_SET(x) WLAN_GPIO_PIN25_CONFIG_SET(x)
+#define GPIO_PIN25_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN25_WAKEUP_ENABLE_MSB
+#define GPIO_PIN25_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN25_WAKEUP_ENABLE_LSB
+#define GPIO_PIN25_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN25_WAKEUP_ENABLE_MASK
+#define GPIO_PIN25_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN25_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN25_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN25_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN25_INT_TYPE_MSB WLAN_GPIO_PIN25_INT_TYPE_MSB
+#define GPIO_PIN25_INT_TYPE_LSB WLAN_GPIO_PIN25_INT_TYPE_LSB
+#define GPIO_PIN25_INT_TYPE_MASK WLAN_GPIO_PIN25_INT_TYPE_MASK
+#define GPIO_PIN25_INT_TYPE_GET(x) WLAN_GPIO_PIN25_INT_TYPE_GET(x)
+#define GPIO_PIN25_INT_TYPE_SET(x) WLAN_GPIO_PIN25_INT_TYPE_SET(x)
+#define GPIO_PIN25_PAD_DRIVER_MSB WLAN_GPIO_PIN25_PAD_DRIVER_MSB
+#define GPIO_PIN25_PAD_DRIVER_LSB WLAN_GPIO_PIN25_PAD_DRIVER_LSB
+#define GPIO_PIN25_PAD_DRIVER_MASK WLAN_GPIO_PIN25_PAD_DRIVER_MASK
+#define GPIO_PIN25_PAD_DRIVER_GET(x) WLAN_GPIO_PIN25_PAD_DRIVER_GET(x)
+#define GPIO_PIN25_PAD_DRIVER_SET(x) WLAN_GPIO_PIN25_PAD_DRIVER_SET(x)
+#define GPIO_PIN25_SOURCE_MSB WLAN_GPIO_PIN25_SOURCE_MSB
+#define GPIO_PIN25_SOURCE_LSB WLAN_GPIO_PIN25_SOURCE_LSB
+#define GPIO_PIN25_SOURCE_MASK WLAN_GPIO_PIN25_SOURCE_MASK
+#define GPIO_PIN25_SOURCE_GET(x) WLAN_GPIO_PIN25_SOURCE_GET(x)
+#define GPIO_PIN25_SOURCE_SET(x) WLAN_GPIO_PIN25_SOURCE_SET(x)
+#define SIGMA_DELTA_ADDRESS WLAN_SIGMA_DELTA_ADDRESS
+#define SIGMA_DELTA_OFFSET WLAN_SIGMA_DELTA_OFFSET
+#define SIGMA_DELTA_ENABLE_MSB WLAN_SIGMA_DELTA_ENABLE_MSB
+#define SIGMA_DELTA_ENABLE_LSB WLAN_SIGMA_DELTA_ENABLE_LSB
+#define SIGMA_DELTA_ENABLE_MASK WLAN_SIGMA_DELTA_ENABLE_MASK
+#define SIGMA_DELTA_ENABLE_GET(x) WLAN_SIGMA_DELTA_ENABLE_GET(x)
+#define SIGMA_DELTA_ENABLE_SET(x) WLAN_SIGMA_DELTA_ENABLE_SET(x)
+#define SIGMA_DELTA_PRESCALAR_MSB WLAN_SIGMA_DELTA_PRESCALAR_MSB
+#define SIGMA_DELTA_PRESCALAR_LSB WLAN_SIGMA_DELTA_PRESCALAR_LSB
+#define SIGMA_DELTA_PRESCALAR_MASK WLAN_SIGMA_DELTA_PRESCALAR_MASK
+#define SIGMA_DELTA_PRESCALAR_GET(x) WLAN_SIGMA_DELTA_PRESCALAR_GET(x)
+#define SIGMA_DELTA_PRESCALAR_SET(x) WLAN_SIGMA_DELTA_PRESCALAR_SET(x)
+#define SIGMA_DELTA_TARGET_MSB WLAN_SIGMA_DELTA_TARGET_MSB
+#define SIGMA_DELTA_TARGET_LSB WLAN_SIGMA_DELTA_TARGET_LSB
+#define SIGMA_DELTA_TARGET_MASK WLAN_SIGMA_DELTA_TARGET_MASK
+#define SIGMA_DELTA_TARGET_GET(x) WLAN_SIGMA_DELTA_TARGET_GET(x)
+#define SIGMA_DELTA_TARGET_SET(x) WLAN_SIGMA_DELTA_TARGET_SET(x)
+#define DEBUG_CONTROL_ADDRESS WLAN_DEBUG_CONTROL_ADDRESS
+#define DEBUG_CONTROL_OFFSET WLAN_DEBUG_CONTROL_OFFSET
+#define DEBUG_CONTROL_ENABLE_MSB WLAN_DEBUG_CONTROL_ENABLE_MSB
+#define DEBUG_CONTROL_ENABLE_LSB WLAN_DEBUG_CONTROL_ENABLE_LSB
+#define DEBUG_CONTROL_ENABLE_MASK WLAN_DEBUG_CONTROL_ENABLE_MASK
+#define DEBUG_CONTROL_ENABLE_GET(x) WLAN_DEBUG_CONTROL_ENABLE_GET(x)
+#define DEBUG_CONTROL_ENABLE_SET(x) WLAN_DEBUG_CONTROL_ENABLE_SET(x)
+#define DEBUG_INPUT_SEL_ADDRESS WLAN_DEBUG_INPUT_SEL_ADDRESS
+#define DEBUG_INPUT_SEL_OFFSET WLAN_DEBUG_INPUT_SEL_OFFSET
+#define DEBUG_INPUT_SEL_SHIFT_MSB WLAN_DEBUG_INPUT_SEL_SHIFT_MSB
+#define DEBUG_INPUT_SEL_SHIFT_LSB WLAN_DEBUG_INPUT_SEL_SHIFT_LSB
+#define DEBUG_INPUT_SEL_SHIFT_MASK WLAN_DEBUG_INPUT_SEL_SHIFT_MASK
+#define DEBUG_INPUT_SEL_SHIFT_GET(x) WLAN_DEBUG_INPUT_SEL_SHIFT_GET(x)
+#define DEBUG_INPUT_SEL_SHIFT_SET(x) WLAN_DEBUG_INPUT_SEL_SHIFT_SET(x)
+#define DEBUG_INPUT_SEL_SRC_MSB WLAN_DEBUG_INPUT_SEL_SRC_MSB
+#define DEBUG_INPUT_SEL_SRC_LSB WLAN_DEBUG_INPUT_SEL_SRC_LSB
+#define DEBUG_INPUT_SEL_SRC_MASK WLAN_DEBUG_INPUT_SEL_SRC_MASK
+#define DEBUG_INPUT_SEL_SRC_GET(x) WLAN_DEBUG_INPUT_SEL_SRC_GET(x)
+#define DEBUG_INPUT_SEL_SRC_SET(x) WLAN_DEBUG_INPUT_SEL_SRC_SET(x)
+#define DEBUG_OUT_ADDRESS WLAN_DEBUG_OUT_ADDRESS
+#define DEBUG_OUT_OFFSET WLAN_DEBUG_OUT_OFFSET
+#define DEBUG_OUT_DATA_MSB WLAN_DEBUG_OUT_DATA_MSB
+#define DEBUG_OUT_DATA_LSB WLAN_DEBUG_OUT_DATA_LSB
+#define DEBUG_OUT_DATA_MASK WLAN_DEBUG_OUT_DATA_MASK
+#define DEBUG_OUT_DATA_GET(x) WLAN_DEBUG_OUT_DATA_GET(x)
+#define DEBUG_OUT_DATA_SET(x) WLAN_DEBUG_OUT_DATA_SET(x)
+#define RESET_TUPLE_STATUS_ADDRESS WLAN_RESET_TUPLE_STATUS_ADDRESS
+#define RESET_TUPLE_STATUS_OFFSET WLAN_RESET_TUPLE_STATUS_OFFSET
+#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MSB WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MSB
+#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB
+#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK
+#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_GET(x) WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_GET(x)
+#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_SET(x) WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_SET(x)
+#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MSB WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MSB
+#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB
+#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK
+#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_GET(x) WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_GET(x)
+#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_SET(x) WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_SET(x)
+
+
+#endif
+#endif
+
+
+
diff --git a/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/mac_dma_reg.h b/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/mac_dma_reg.h
new file mode 100644
index 00000000000..f82f809171a
--- /dev/null
+++ b/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/mac_dma_reg.h
@@ -0,0 +1,605 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2002-2010 Atheros Communications Inc.
+// All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+/*****************************************************************************/
+/* AR6003 WLAN MAC DMA register definitions                                  */
+/*****************************************************************************/
+
+#ifndef _AR6000_DMAREG_H_
+#define _AR6000_DMAREG_H_
+
+/*
+ * Definitions for the Atheros AR6003 chipset.
+ */
+
+/* DMA Control and Interrupt Registers */
+#define MAC_DMA_CR_ADDRESS                       0x00000008 /* MAC control register */
+#define MAC_DMA_CR_RXE_MASK                      0x00000004 /* Receive enable */
+#define MAC_DMA_CR_RXD_MASK                      0x00000020 /* Receive disable */
+#define MAC_DMA_CR_SWI_MASK                      0x00000040 /* One-shot software interrupt */
+
+#define MAC_DMA_RXDP_ADDRESS                     0x0000000C /* MAC receive queue descriptor pointer */
+
+#define MAC_DMA_CFG_ADDRESS                      0x00000014 /* MAC configuration and status register */
+#define MAC_DMA_CFG_SWTD_MASK                    0x00000001 /* byteswap tx descriptor words */
+#define MAC_DMA_CFG_SWTB_MASK                    0x00000002 /* byteswap tx data buffer words */
+#define MAC_DMA_CFG_SWRD_MASK                    0x00000004 /* byteswap rx descriptor words */
+#define MAC_DMA_CFG_SWRB_MASK                    0x00000008 /* byteswap rx data buffer words */
+#define MAC_DMA_CFG_SWRG_MASK                    0x00000010 /* byteswap register access data words */
+#define MAC_DMA_CFG_AP_ADHOC_INDICATION_MASK     0x00000020 /* AP/adhoc indication (0-AP, 1-Adhoc) */
+#define MAC_DMA_CFG_PHOK_MASK                    0x00000100 /* PHY OK status */
+#define MAC_DMA_CFG_CLK_GATE_DIS_MASK            0x00000400 /* Clock gating disable  */
+
+#define MAC_DMA_MIRT_ADDRESS                     0x00000020 /* Maximum rate threshold register */
+#define MAC_DMA_MIRT_THRESH_MASK                 0x0000FFFF 
+
+#define MAC_DMA_IER_ADDRESS                      0x00000024  /* MAC Interrupt enable register */
+#define MAC_DMA_IER_ENABLE_MASK                  0x00000001 /* Global interrupt enable */
+#define MAC_DMA_IER_DISABLE_MASK                 0x00000000 /* Global interrupt disable */
+
+#define MAC_DMA_TIMT_ADDRESS                     0x00000028 /* Transmit Interrupt Mitigation Threshold */
+#define MAC_DMA_TIMT_LAST_PACKER_THRESH_MASK     0x0000FFFF /* Last packet threshold mask */
+#define MAC_DMA_TIMT_FIRST_PACKER_THRESH_MASK    0xFFFF0000 /* First packet threshold mask */
+
+#define MAC_DMA_RIMT_ADDRESS                     0x0000002C /* Receive Interrupt Mitigation Threshold */
+#define MAC_DMA_RIMT_LAST_PACKER_THRESH_MASK     0x0000FFFF /* Last packet threshold mask */
+#define MAC_DMA_RIMT_FIRST_PACKER_THRESH_MASK    0xFFFF0000 /* First packet threshold mask */
+
+#define MAC_DMA_TXCFG_ADDRESS                    0x00000030  /* MAC tx DMA size config register */
+#define MAC_DMA_FTRIG_MASK                       0x000003F0 /* Mask for Frame trigger level */
+#define MAC_DMA_FTRIG_LSB                        4          /* Shift for Frame trigger level */
+#define MAC_DMA_FTRIG_IMMED                      0x00000000 /* bytes in PCU TX FIFO before air */
+#define MAC_DMA_FTRIG_64B                        0x00000010 /* default */
+#define MAC_DMA_FTRIG_128B                       0x00000020
+#define MAC_DMA_FTRIG_192B                       0x00000030
+#define MAC_DMA_FTRIG_256B                       0x00000040 /* 5 bits total */
+#define MAC_DMA_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY_MASK 0x00000800
+
+#define MAC_DMA_RXCFG_ADDRESS                     0x00000034  /* MAC rx DMA size config register */
+#define MAC_DMA_RXCFG_ZLFDMA_MASK                 0x00000010 /* Enable DMA of zero-length frame */
+#define MAC_DMA_RXCFG_DMASIZE_4B                  0x00000000 /* DMA size 4 bytes (TXCFG + RXCFG) */
+#define MAC_DMA_RXCFG_DMASIZE_8B                  0x00000001 /* DMA size 8 bytes */
+#define MAC_DMA_RXCFG_DMASIZE_16B                 0x00000002 /* DMA size 16 bytes */
+#define MAC_DMA_RXCFG_DMASIZE_32B                 0x00000003 /* DMA size 32 bytes */
+#define MAC_DMA_RXCFG_DMASIZE_64B                 0x00000004 /* DMA size 64 bytes */
+#define MAC_DMA_RXCFG_DMASIZE_128B                0x00000005 /* DMA size 128 bytes */
+#define MAC_DMA_RXCFG_DMASIZE_256B                0x00000006 /* DMA size 256 bytes */
+#define MAC_DMA_RXCFG_DMASIZE_512B                0x00000007 /* DMA size 512 bytes */
+
+#define MAC_DMA_MIBC_ADDRESS                      0x00000040  /* MAC MIB control register */
+#define MAC_DMA_MIBC_COW_MASK                     0x00000001 /* counter overflow warning */
+#define MAC_DMA_MIBC_FMC_MASK                     0x00000002 /* freeze MIB counters */
+#define MAC_DMA_MIBC_CMC_MASK                     0x00000004 /* clear MIB counters */
+#define MAC_DMA_MIBC_MCS_MASK                     0x00000008 /* MIB counter strobe, increment all */
+
+#define MAC_DMA_TOPS_ADDRESS                      0x00000044  /* MAC timeout prescale count */
+#define MAC_DMA_TOPS_MASK                         0x0000FFFF /* Mask for timeout prescale */
+
+#define MAC_DMA_RXNPTO_ADDRESS                    0x00000048  /* MAC no frame received timeout */
+#define MAC_DMA_RXNPTO_MASK                       0x000003FF /* Mask for no frame received timeout */
+
+#define MAC_DMA_TXNPTO_ADDRESS                    0x0000004C  /* MAC no frame trasmitted timeout */
+#define MAC_DMA_TXNPTO_MASK                       0x000003FF /* Mask for no frame transmitted timeout */
+#define MAC_DMA_TXNPTO_QCU_MASK                   0x000FFC00 /* Mask indicating the set of QCUs */
+                                                       /* for which frame completions will cause */
+                                                       /* a reset of the no frame xmit'd timeout */
+
+#define MAC_DMA_RPGTO_ADDRESS                     0x00000050  /* MAC receive frame gap timeout */
+#define MAC_DMA_RPGTO_MASK                        0x000003FF /* Mask for receive frame gap timeout */
+
+#define MAC_DMA_RPCNT_ADDRESS                     0x00000054  /* MAC receive frame count limit */
+#define MAC_DMA_RPCNT_MASK                        0x0000001F /* Mask for receive frame count limit */
+
+#define MAC_DMA_MACMISC_ADDRESS                   0x00000058  /* MAC miscellaneous control/status register */
+#define MAC_DMA_MACMISC_DMA_OBS_MASK              0x000001E0 /* Mask for DMA observation bus mux select */
+#define MAC_DMA_MACMISC_DMA_OBS_LSB               5          /* Shift for DMA observation bus mux select */
+#define MAC_DMA_MACMISC_MISC_OBS                  0x00000E00 /* Mask for MISC observation bus mux select */
+#define MAC_DMA_MACMISC_MISC_OBS_LSB              9          /* Shift for MISC observation bus mux select */
+#define MAC_DMA_MACMISC_MAC_OBS_BUS_LSB           0x00007000 /* Mask for MAC observation bus mux select (lsb) */
+#define MAC_DMA_MACMISC_MAC_OBS_BUS_LSB_LSB       12         /* Shift for MAC observation bus mux select (lsb) */
+#define MAC_DMA_MACMISC_MAC_OBS_BUS_MSB           0x00038000 /* Mask for MAC observation bus mux select (msb) */
+#define MAC_DMA_MACMISC_MAC_OBS_BUS_MSB_LSB       15         /* Shift for MAC observation bus mux select (msb) */
+
+
+#define MAC_DMA_ISR_ADDRESS                        0x00000080  /* MAC Primary interrupt status register */
+/*
+ * Interrupt Status Registers
+ *
+ * Only the bits in the ISR_P register and the IMR_P registers
+ * control whether the MAC's INTA# output is asserted.  The bits in
+ * the secondary interrupt status/mask registers control what bits
+ * are set in the primary interrupt status register; however the
+ * IMR_S* registers DO NOT determine whether INTA# is asserted.
+ * That is INTA# is asserted only when the logical AND of ISR_P
+ * and IMR_P is non-zero.  The secondary interrupt mask/status
+ * registers affect what bits are set in ISR_P but they do not
+ * directly affect whether INTA# is asserted.
+ */
+#define MAC_DMA_ISR_RXOK_MASK                    0x00000001 /* At least one frame received sans errors */
+#define MAC_DMA_ISR_RXDESC_MASK                  0x00000002 /* Receive interrupt request */
+#define MAC_DMA_ISR_RXERR_MASK                   0x00000004 /* Receive error interrupt */
+#define MAC_DMA_ISR_RXNOPKT_MASK                 0x00000008 /* No frame received within timeout clock */
+#define MAC_DMA_ISR_RXEOL_MASK                   0x00000010 /* Received descriptor empty interrupt */
+#define MAC_DMA_ISR_RXORN_MASK                   0x00000020 /* Receive FIFO overrun interrupt */
+#define MAC_DMA_ISR_TXOK_MASK                    0x00000040 /* Transmit okay interrupt */
+#define MAC_DMA_ISR_TXDESC_MASK                  0x00000080 /* Transmit interrupt request */
+#define MAC_DMA_ISR_TXERR_MASK                   0x00000100 /* Transmit error interrupt */
+#define MAC_DMA_ISR_TXNOPKT_MASK                 0x00000200 /* No frame transmitted interrupt */
+#define MAC_DMA_ISR_TXEOL_MASK                   0x00000400 /* Transmit descriptor empty interrupt */
+#define MAC_DMA_ISR_TXURN_MASK                   0x00000800 /* Transmit FIFO underrun interrupt */
+#define MAC_DMA_ISR_MIB_MASK                     0x00001000 /* MIB interrupt - see MIBC */
+#define MAC_DMA_ISR_SWI_MASK                     0x00002000 /* Software interrupt */
+#define MAC_DMA_ISR_RXPHY_MASK                   0x00004000 /* PHY receive error interrupt */
+#define MAC_DMA_ISR_RXKCM_MASK                   0x00008000 /* Key-cache miss interrupt */
+#define MAC_DMA_ISR_BRSSI_HI_MASK                0x00010000 /* Beacon rssi high threshold interrupt */
+#define MAC_DMA_ISR_BRSSI_LO_MASK                0x00020000 /* Beacon threshold interrupt */
+#define MAC_DMA_ISR_BMISS_MASK                   0x00040000 /* Beacon missed interrupt */
+#define MAC_DMA_ISR_TXMINTR_MASK                 0x00080000 /* Maximum transmit interrupt rate */
+#define MAC_DMA_ISR_BNR_MASK                     0x00100000 /* Beacon not ready interrupt */
+#define MAC_DMA_ISR_HIUERR_MASK                  0x00200000 /* An unexpected bus error has occurred */
+#define MAC_DMA_ISR_BCNMISC_MASK                 0x00800000 /* 'or' of TIM, CABEND, DTIMSYNC, BCNTO */
+#define MAC_DMA_ISR_RXMINTR_MASK                 0x01000000 /* Maximum receive interrupt rate */
+#define MAC_DMA_ISR_QCBROVF_MASK                 0x02000000 /* QCU CBR overflow interrupt */
+#define MAC_DMA_ISR_QCBRURN_MASK                 0x04000000 /* QCU CBR underrun interrupt */
+#define MAC_DMA_ISR_QTRIG_MASK                   0x08000000 /* QCU scheduling trigger interrupt */
+#define MAC_DMA_ISR_TIMER_MASK                   0x10000000 /* GENTMR interrupt */
+#define MAC_DMA_ISR_HCFTO_MASK                   0x20000000 /* HCFTO interrupt   */
+#define MAC_DMA_ISR_TXINTM_MASK                  0x40000000 /* Transmit completion mitigation interrupt */
+#define MAC_DMA_ISR_RXINTM_MASK                  0x80000000 /* Receive completion mitigation interrupt */
+
+#define MAC_DMA_ISR_S0_ADDRESS                   0x00000084  /* MAC Secondary interrupt status register 0 */
+#define MAC_DMA_ISR_S0_QCU_TXOK_MASK             0x000003FF /* Mask for TXOK (QCU 0-9) */
+#define MAC_DMA_ISR_S0_QCU_TXOK_LSB              0
+#define MAC_DMA_ISR_S0_QCU_TXDESC_MASK           0x03FF0000 /* Mask for TXDESC (QCU 0-9) */
+#define MAC_DMA_ISR_S0_QCU_TXDESC_LSB            16
+
+#define MAC_DMA_ISR_S1_ADDRESS                   0x00000088  /* MAC Secondary interrupt status register 1 */
+#define MAC_DMA_ISR_S1_QCU_TXERR_MASK            0x000003FF /* Mask for TXERR (QCU 0-9) */
+#define MAC_DMA_ISR_S1_QCU_TXERR_LSB             0
+#define MAC_DMA_ISR_S1_QCU_TXEOL_MASK            0x03FF0000 /* Mask for TXEOL (QCU 0-9) */
+#define MAC_DMA_ISR_S1_QCU_TXEOL_LSB             16
+
+#define MAC_DMA_ISR_S2_ADDRESS                      0x0000008c  /* MAC Secondary interrupt status register 2 */
+#define MAC_DMA_ISR_S2_QCU_TXURN_MASK               0x000003FF /* Mask for TXURN (QCU 0-9) */
+#define MAC_DMA_ISR_S2_QCU_TXURN_LSB                0 /* Shift for TXURN (QCU 0-9) */
+#define MAC_DMA_ISR_S2_RX_INT_MASK			        0x00000800
+#define MAC_DMA_ISR_S2_WL_STOMPED_MASK		        0x00001000
+#define MAC_DMA_ISR_S2_RX_PTR_BAD_MASK		        0x00002000
+#define MAC_DMA_ISR_S2_BT_LOW_PRIORITY_RISING_MASK  0x00004000
+#define MAC_DMA_ISR_S2_BT_LOW_PRIORITY_FALLING_MASK	0x00008000
+#define MAC_DMA_ISR_S2_BB_PANIC_IRQ_MASK            0x00010000
+#define MAC_DMA_ISR_S2_BT_STOMPED_MASK		        0x00020000
+#define MAC_DMA_ISR_S2_BT_ACTIVE_RISING_MASK	    0x00040000
+#define MAC_DMA_ISR_S2_BT_ACTIVE_FALLING_MASK	    0x00080000
+#define MAC_DMA_ISR_S2_BT_PRIORITY_RISING_MASK	    0x00100000
+#define MAC_DMA_ISR_S2_BT_PRIORITY_FALLING_MASK	    0x00200000
+#define MAC_DMA_ISR_S2_CST_MASK			            0x00400000
+#define MAC_DMA_ISR_S2_GTT_MASK			            0x00800000
+#define MAC_DMA_ISR_S2_TIM_MASK                     0x01000000 /* TIM */
+#define MAC_DMA_ISR_S2_CABEND_MASK                  0x02000000 /* CABEND */
+#define MAC_DMA_ISR_S2_DTIMSYNC_MASK                0x04000000 /* DTIMSYNC */
+#define MAC_DMA_ISR_S2_BCNTO_MASK                   0x08000000 /* BCNTO */
+#define MAC_DMA_ISR_S2_CABTO_MASK                   0x10000000 /* CABTO */
+#define MAC_DMA_ISR_S2_DTIM_MASK                    0x20000000 /* DTIM */
+#define MAC_DMA_ISR_S2_TSFOOR_MASK                  0x40000000 /* TSFOOR */
+
+#define MAC_DMA_ISR_S3_ADDRESS                   0x00000090  /* MAC Secondary interrupt status register 3 */
+#define MAC_DMA_ISR_S3_QCU_QCBROVF_MASK          0x000003FF /* Mask for QCBROVF (QCU 0-9) */
+#define MAC_DMA_ISR_S3_QCU_QCBRURN_MASK          0x03FF0000 /* Mask for QCBRURN (QCU 0-9) */
+
+#define MAC_DMA_ISR_S4_ADDRESS                   0x00000094  /* MAC Secondary interrupt status register 4 */
+#define MAC_DMA_ISR_S4_QCU_QTRIG_MASK            0x000003FF /* Mask for QTRIG (QCU 0-9) */
+
+#define MAC_DMA_ISR_S5_ADDRESS                   0x00000098  /* MAC Secondary interrupt status register 5 */
+#define MAC_DMA_ISR_S5_TBTT_TIMER_TRIGGER_MASK   0x00000001
+#define MAC_DMA_ISR_S5_DBA_TIMER_TRIGGER_MASK    0x00000002
+#define MAC_DMA_ISR_S5_SBA_TIMER_TRIGGER_MASK    0x00000004
+#define MAC_DMA_ISR_S5_HCF_TIMER_TRIGGER_MASK    0x00000008
+#define MAC_DMA_ISR_S5_TIM_TIMER_TRIGGER_MASK    0x00000010
+#define MAC_DMA_ISR_S5_DTIM_TIMER_TRIGGER_MASK   0x00000020
+#define MAC_DMA_ISR_S5_QUIET_TIMER_TRIGGER_MASK  0x00000040
+#define MAC_DMA_ISR_S5_NDP_TIMER_TRIGGER_MASK    0x00000080
+#define MAC_DMA_ISR_S5_GENERIC_TIMER2_TRIGGER_MASK 0x0000FF00
+#define MAC_DMA_ISR_S5_GENERIC_TIMER2_TRIGGER_LSB 8 
+#define MAC_DMA_ISR_S5_GENERIC_TIMER2_TRIGGER(_i) (0x00000100 << (_i))
+#define MAC_DMA_ISR_S5_TIMER_OVERFLOW_MASK       0x00010000
+#define MAC_DMA_ISR_S5_DBA_TIMER_THRESHOLD_MASK  0x00020000
+#define MAC_DMA_ISR_S5_SBA_TIMER_THRESHOLD_MASK  0x00040000
+#define MAC_DMA_ISR_S5_HCF_TIMER_THRESHOLD_MASK  0x00080000
+#define MAC_DMA_ISR_S5_TIM_TIMER_THRESHOLD_MASK  0x00100000
+#define MAC_DMA_ISR_S5_DTIM_TIMER_THRESHOLD_MASK  0x00200000
+#define MAC_DMA_ISR_S5_QUIET_TIMER_THRESHOLD_MASK 0x00400000
+#define MAC_DMA_ISR_S5_NDP_TIMER_THRESHOLD_MASK   0x00800000
+#define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD_MASK 0xFF000000
+#define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD_LSB  24 
+#define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD(_i) (0x01000000 << (_i))
+
+#define MAC_DMA_IMR_ADDRESS                      0x000000A0  /* MAC Primary interrupt mask register */
+/*
+ * Interrupt Mask Registers
+ *
+ * Only the bits in the IMR control whether the MAC's INTA#
+ * output will be asserted.  The bits in the secondary interrupt
+ * mask registers control what bits get set in the primary
+ * interrupt status register; however the IMR_S* registers
+ * DO NOT determine whether INTA# is asserted.
+ */
+#define MAC_DMA_IMR_RXOK_MASK                    0x00000001 /* At least one frame received sans errors */
+#define MAC_DMA_IMR_RXDESC_MASK                  0x00000002 /* Receive interrupt request */
+#define MAC_DMA_IMR_RXERR_MASK                   0x00000004 /* Receive error interrupt */
+#define MAC_DMA_IMR_RXNOPKT_MASK                 0x00000008 /* No frame received within timeout clock */
+#define MAC_DMA_IMR_RXEOL_MASK                   0x00000010 /* Received descriptor empty interrupt */
+#define MAC_DMA_IMR_RXORN_MASK                   0x00000020 /* Receive FIFO overrun interrupt */
+#define MAC_DMA_IMR_TXOK_MASK                    0x00000040 /* Transmit okay interrupt */
+#define MAC_DMA_IMR_TXDESC_MASK                  0x00000080 /* Transmit interrupt request */
+#define MAC_DMA_IMR_TXERR_MASK                   0x00000100 /* Transmit error interrupt */
+#define MAC_DMA_IMR_TXNOPKT_MASK                 0x00000200 /* No frame transmitted interrupt */
+#define MAC_DMA_IMR_TXEOL_MASK                   0x00000400 /* Transmit descriptor empty interrupt */
+#define MAC_DMA_IMR_TXURN_MASK                   0x00000800 /* Transmit FIFO underrun interrupt */
+#define MAC_DMA_IMR_MIB_MASK                     0x00001000 /* MIB interrupt - see MIBC */
+#define MAC_DMA_IMR_SWI_MASK                     0x00002000 /* Software interrupt */
+#define MAC_DMA_IMR_RXPHY_MASK                   0x00004000 /* PHY receive error interrupt */
+#define MAC_DMA_IMR_RXKCM_MASK                   0x00008000 /* Key-cache miss interrupt */
+#define MAC_DMA_IMR_BRSSI_HI_MASK                0x00010000 /* Beacon rssi hi threshold interrupt */
+#define MAC_DMA_IMR_BRSSI_LO_MASK                0x00020000 /* Beacon rssi lo threshold interrupt */
+#define MAC_DMA_IMR_BMISS_MASK                   0x00040000 /* Beacon missed interrupt */
+#define MAC_DMA_IMR_TXMINTR_MASK                 0x00080000 /* Maximum transmit interrupt rate */
+#define MAC_DMA_IMR_BNR_MASK                     0x00100000 /* BNR interrupt */
+#define MAC_DMA_IMR_HIUERR_MASK                  0x00200000 /* An unexpected bus error has occurred */
+#define MAC_DMA_IMR_BCNMISC_MASK                 0x00800000 /* Beacon Misc */
+#define MAC_DMA_IMR_RXMINTR_MASK                 0x01000000 /* Maximum receive interrupt rate */
+#define MAC_DMA_IMR_QCBROVF_MASK                 0x02000000 /* QCU CBR overflow interrupt */
+#define MAC_DMA_IMR_QCBRURN_MASK                 0x04000000 /* QCU CBR underrun interrupt */
+#define MAC_DMA_IMR_QTRIG_MASK                   0x08000000 /* QCU scheduling trigger interrupt */
+#define MAC_DMA_IMR_TIMER_MASK                   0x10000000 /* GENTMR interrupt */
+#define MAC_DMA_IMR_HCFTO_MASK                   0x20000000 /* HCFTO interrupt*/
+#define MAC_DMA_IMR_TXINTM_MASK                  0x40000000 /* Transmit completion mitigation interrupt */
+#define MAC_DMA_IMR_RXINTM_MASK                  0x80000000 /* Receive completion mitigation interrupt */
+
+#define MAC_DMA_IMR_S0_ADDRESS                   0x000000A4  /* MAC Secondary interrupt mask register 0 */
+#define MAC_DMA_IMR_S0_QCU_TXOK_MASK             0x000003FF /* TXOK (QCU 0-9) */
+#define MAC_DMA_IMR_S0_QCU_TXOK_LSB              0
+#define MAC_DMA_IMR_S0_QCU_TXDESC_MASK           0x03FF0000 /* TXDESC (QCU 0-9) */
+#define MAC_DMA_IMR_S0_QCU_TXDESC_LSB            16
+
+#define MAC_DMA_IMR_S1_ADDRESS                   0x000000A8  /* MAC Secondary interrupt mask register 1 */
+#define MAC_DMA_IMR_S1_QCU_TXERR_MASK            0x000003FF /* TXERR (QCU 0-9) */
+#define MAC_DMA_IMR_S1_QCU_TXERR_LSB             0
+#define MAC_DMA_IMR_S1_QCU_TXEOL_MASK            0x03FF0000 /* TXEOL (QCU 0-9) */
+#define MAC_DMA_IMR_S1_QCU_TXEOL_LSB             16
+
+#define MAC_DMA_IMR_S2_ADDRESS                      0x000000AC  /* MAC Secondary interrupt mask register 2 */
+#define MAC_DMA_IMR_S2_QCU_TXURN_MASK               0x000003FF /* Mask for TXURN (QCU 0-9) */
+#define MAC_DMA_IMR_S2_QCU_TXURN_LSB                0
+#define MAC_DMA_IMR_S2_RX_INT_MASK			        0x00000800
+#define MAC_DMA_IMR_S2_WL_STOMPED_MASK		        0x00001000
+#define MAC_DMA_IMR_S2_RX_PTR_BAD_MASK		        0x00002000
+#define MAC_DMA_IMR_S2_BT_LOW_PRIORITY_RISING_MASK  0x00004000
+#define MAC_DMA_IMR_S2_BT_LOW_PRIORITY_FALLING_MASK	0x00008000
+#define MAC_DMA_IMR_S2_BB_PANIC_IRQ_MASK            0x00010000
+#define MAC_DMA_IMR_S2_BT_STOMPED_MASK		        0x00020000
+#define MAC_DMA_IMR_S2_BT_ACTIVE_RISING_MASK	    0x00040000
+#define MAC_DMA_IMR_S2_BT_ACTIVE_FALLING_MASK	    0x00080000
+#define MAC_DMA_IMR_S2_BT_PRIORITY_RISING_MASK	    0x00100000
+#define MAC_DMA_IMR_S2_BT_PRIORITY_FALLING_MASK	    0x00200000
+#define MAC_DMA_IMR_S2_CST_MASK			            0x00400000
+#define MAC_DMA_IMR_S2_GTT_MASK			            0x00800000
+#define MAC_DMA_IMR_S2_TIM_MASK                     0x01000000 /* TIM */
+#define MAC_DMA_IMR_S2_CABEND_MASK                  0x02000000 /* CABEND */
+#define MAC_DMA_IMR_S2_DTIMSYNC_MASK                0x04000000 /* DTIMSYNC */
+#define MAC_DMA_IMR_S2_BCNTO_MASK                   0x08000000 /* BCNTO */
+#define MAC_DMA_IMR_S2_CABTO_MASK                   0x10000000 /* CABTO */
+#define MAC_DMA_IMR_S2_DTIM_MASK                    0x20000000 /* DTIM */
+#define MAC_DMA_IMR_S2_TSFOOR_MASK                  0x40000000 /* TSFOOR */
+
+#define MAC_DMA_IMR_S3_ADDRESS                   0x000000B0  /* MAC Secondary interrupt mask register 3 */
+#define MAC_DMA_IMR_S3_QCU_QCBROVF_MASK          0x000003FF /* Mask for QCBROVF (QCU 0-9) */
+#define MAC_DMA_IMR_S3_QCU_QCBRURN_MASK          0x03FF0000 /* Mask for QCBRURN (QCU 0-9) */
+#define MAC_DMA_IMR_S3_QCU_QCBRURN_LSB           16 
+
+#define MAC_DMA_IMR_S4_ADDRESS                   0x000000B4  /* MAC Secondary interrupt mask register 4 */
+#define MAC_DMA_IMR_S4_QCU_QTRIG_MASK            0x000003FF /* Mask for QTRIG (QCU 0-9) */
+
+#define MAC_DMA_IMR_S5_ADDRESS                   0x000000B8  /* MAC Secondary interrupt mask register 5 */
+#define MAC_DMA_IMR_S5_TBTT_TIMER_TRIGGER_MASK   0x00000001
+#define MAC_DMA_IMR_S5_DBA_TIMER_TRIGGER_MASK    0x00000002
+#define MAC_DMA_IMR_S5_SBA_TIMER_TRIGGER_MASK    0x00000004
+#define MAC_DMA_IMR_S5_HCF_TIMER_TRIGGER_MASK    0x00000008
+#define MAC_DMA_IMR_S5_TIM_TIMER_TRIGGER_MASK    0x00000010
+#define MAC_DMA_IMR_S5_DTIM_TIMER_TRIGGER_MASK   0x00000020
+#define MAC_DMA_IMR_S5_QUIET_TIMER_TRIGGER_MASK  0x00000040
+#define MAC_DMA_IMR_S5_NDP_TIMER_TRIGGER_MASK    0x00000080
+#define MAC_DMA_IMR_S5_GENERIC_TIMER2_TRIGGER_MASK 0x0000FF00
+#define MAC_DMA_IMR_S5_GENERIC_TIMER2_TRIGGER_LSB 8 
+#define MAC_DMA_IMR_S5_GENERIC_TIMER2_TRIGGER(_i)    (0x100 << (_i))
+#define MAC_DMA_IMR_S5_TIMER_OVERFLOW_MASK       0x00010000
+#define MAC_DMA_IMR_S5_DBA_TIMER_THRESHOLD_MASK  0x00020000
+#define MAC_DMA_IMR_S5_SBA_TIMER_THRESHOLD_MASK  0x00040000
+#define MAC_DMA_IMR_S5_HCF_TIMER_THRESHOLD_MASK  0x00080000
+#define MAC_DMA_IMR_S5_TIM_TIMER_THRESHOLD_MASK  0x00100000
+#define MAC_DMA_IMR_S5_DTIM_TIMER_THRESHOLD_MASK 0x00200000
+#define MAC_DMA_IMR_S5_QUIET_TIMER_THRESHOLD_MASK 0000400000
+#define MAC_DMA_IMR_S5_NDP_TIMER_THRESHOLD_MASK  0x00800000
+#define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD_MASK 0xFF000000
+#define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD_LSB  24 
+#define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD(_i) (0x01000000 << (_i))
+
+#define MAC_DMA_ISR_RAC_ADDRESS                  0x000000C0  /* ISR read-and-clear access */
+
+/* Shadow copies with read-and-clear access */
+#define MAC_DMA_ISR_S0_S_ADDRESS                 0x000000C4  /* ISR_S0 shadow copy */
+#define MAC_DMA_ISR_S1_S_ADDRESS                 0x000000C8  /* ISR_S1 shadow copy */
+#define MAC_DMA_ISR_S2_S_ADDRESS                 0x000000Cc  /* ISR_S2 shadow copy */
+#define MAC_DMA_ISR_S3_S_ADDRESS                 0x000000D0  /* ISR_S3 shadow copy */
+#define MAC_DMA_ISR_S4_S_ADDRESS                 0x000000D4  /* ISR_S4 shadow copy */
+#define MAC_DMA_ISR_S5_S_ADDRESS                 0x000000D8  /* ISR_S5 shadow copy */
+
+#define MAC_DMA_Q0_TXDP_ADDRESS                  0x00000800  /* MAC Transmit Queue descriptor pointer */
+#define MAC_DMA_Q1_TXDP_ADDRESS                  0x00000804  /* MAC Transmit Queue descriptor pointer */
+#define MAC_DMA_Q2_TXDP_ADDRESS                  0x00000808  /* MAC Transmit Queue descriptor pointer */
+#define MAC_DMA_Q3_TXDP_ADDRESS                  0x0000080C  /* MAC Transmit Queue descriptor pointer */
+#define MAC_DMA_Q4_TXDP_ADDRESS                  0x00000810  /* MAC Transmit Queue descriptor pointer */
+#define MAC_DMA_Q5_TXDP_ADDRESS                  0x00000814  /* MAC Transmit Queue descriptor pointer */
+#define MAC_DMA_Q6_TXDP_ADDRESS                  0x00000818  /* MAC Transmit Queue descriptor pointer */
+#define MAC_DMA_Q7_TXDP_ADDRESS                  0x0000081C  /* MAC Transmit Queue descriptor pointer */
+#define MAC_DMA_Q8_TXDP_ADDRESS                  0x00000820  /* MAC Transmit Queue descriptor pointer */
+#define MAC_DMA_Q9_TXDP_ADDRESS                  0x00000824  /* MAC Transmit Queue descriptor pointer */
+#define MAC_DMA_QTXDP_ADDRESS(_i)                (MAC_DMA_Q0_TXDP_ADDRESS + ((_i)<<2))
+
+#define MAC_DMA_Q_TXE_ADDRESS                    0x00000840  /* MAC Transmit Queue enable */
+#define MAC_DMA_Q_TXD_ADDRESS                    0x00000880  /* MAC Transmit Queue disable */
+/* QCU registers */
+
+#define MAC_DMA_Q0_CBRCFG_ADDRESS                0x000008C0  /* MAC CBR configuration */
+#define MAC_DMA_Q1_CBRCFG_ADDRESS                0x000008C4  /* MAC CBR configuration */
+#define MAC_DMA_Q2_CBRCFG_ADDRESS                0x000008C8  /* MAC CBR configuration */
+#define MAC_DMA_Q3_CBRCFG_ADDRESS                0x000008CC  /* MAC CBR configuration */
+#define MAC_DMA_Q4_CBRCFG_ADDRESS                0x000008D0  /* MAC CBR configuration */
+#define MAC_DMA_Q5_CBRCFG_ADDRESS                0x000008D4  /* MAC CBR configuration */
+#define MAC_DMA_Q6_CBRCFG_ADDRESS                0x000008D8  /* MAC CBR configuration */
+#define MAC_DMA_Q7_CBRCFG_ADDRESS                0x000008DC  /* MAC CBR configuration */
+#define MAC_DMA_Q8_CBRCFG_ADDRESS                0x000008E0  /* MAC CBR configuration */
+#define MAC_DMA_Q9_CBRCFG_ADDRESS                0x000008E4  /* MAC CBR configuration */
+#define MAC_DMA_QCBRCFG_ADDRESS(_i)             (MAC_DMA_Q0_CBRCFG_ADDRESS + ((_i)<<2))
+
+#define MAC_DMA_Q_CBRCFG_CBR_INTERVAL_MASK        0x00FFFFFF /* Mask for CBR interval (us) */
+#define MAC_DMA_Q_CBRCFG_CBR_INTERVAL_LSB         0   /* Shift for CBR interval */
+#define MAC_DMA_Q_CBRCFG_CBR_OVF_THRESH_MASK      0xFF000000 /* Mask for CBR overflow threshold */
+#define MAC_DMA_Q_CBRCFG_CBR_OVF_THRESH_LSB       24  /* Shift for CBR overflow thresh */
+
+
+#define MAC_DMA_Q0_RDYTIMECFG_ADDRESS             0x00000900  /* MAC ReadyTime configuration */
+#define MAC_DMA_Q1_RDYTIMECFG_ADDRESS             0x00000904  /* MAC ReadyTime configuration */
+#define MAC_DMA_Q2_RDYTIMECFG_ADDRESS             0x00000908  /* MAC ReadyTime configuration */
+#define MAC_DMA_Q3_RDYTIMECFG_ADDRESS             0x0000090C  /* MAC ReadyTime configuration */
+#define MAC_DMA_Q4_RDYTIMECFG_ADDRESS             0x00000910  /* MAC ReadyTime configuration */
+#define MAC_DMA_Q5_RDYTIMECFG_ADDRESS             0x00000914  /* MAC ReadyTime configuration */
+#define MAC_DMA_Q6_RDYTIMECFG_ADDRESS             0x00000918  /* MAC ReadyTime configuration */
+#define MAC_DMA_Q7_RDYTIMECFG_ADDRESS             0x0000091C  /* MAC ReadyTime configuration */
+#define MAC_DMA_Q8_RDYTIMECFG_ADDRESS             0x00000920  /* MAC ReadyTime configuration */
+#define MAC_DMA_Q9_RDYTIMECFG_ADDRESS             0x00000924  /* MAC ReadyTime configuration */
+#define MAC_DMA_QRDYTIMECFG_ADDRESS(_i)           (MAC_DMA_Q0_RDYTIMECFG_ADDRESS + ((_i)<<2))
+
+#define MAC_DMA_Q_RDYTIMECFG_INT_MASK             0x00FFFFFF /* CBR interval (us) */
+#define MAC_DMA_Q_RDYTIMECFG_INT_LSB              0  /* Shift for ReadyTime Interval (us) */
+#define MAC_DMA_Q_RDYTIMECFG_ENA_MASK             0x01000000 /* CBR enable */
+
+#define MAC_DMA_Q_ONESHOTMAC_DMAM_SC_ADDRESS      0x00000940  /* MAC OneShotArm set control */
+#define MAC_DMA_Q_ONESHOTMAC_DMAM_CC_ADDRESS      0x00000980  /* MAC OneShotArm clear control */
+
+#define MAC_DMA_Q0_MISC_ADDRESS                   0x000009C0  /* MAC Miscellaneous QCU settings */
+#define MAC_DMA_Q1_MISC_ADDRESS                   0x000009C4  /* MAC Miscellaneous QCU settings */
+#define MAC_DMA_Q2_MISC_ADDRESS                   0x000009C8  /* MAC Miscellaneous QCU settings */
+#define MAC_DMA_Q3_MISC_ADDRESS                   0x000009CC  /* MAC Miscellaneous QCU settings */
+#define MAC_DMA_Q4_MISC_ADDRESS                   0x000009D0  /* MAC Miscellaneous QCU settings */
+#define MAC_DMA_Q5_MISC_ADDRESS                   0x000009D4  /* MAC Miscellaneous QCU settings */
+#define MAC_DMA_Q6_MISC_ADDRESS                   0x000009D8  /* MAC Miscellaneous QCU settings */
+#define MAC_DMA_Q7_MISC_ADDRESS                   0x000009DC  /* MAC Miscellaneous QCU settings */
+#define MAC_DMA_Q8_MISC_ADDRESS                   0x000009E0  /* MAC Miscellaneous QCU settings */
+#define MAC_DMA_Q9_MISC_ADDRESS                   0x000009E4  /* MAC Miscellaneous QCU settings */
+#define MAC_DMA_QMISC_ADDRESS(_i)                 (MAC_DMA_Q0_MISC_ADDRESS + ((_i)<<2))
+
+#define MAC_DMA_Q_MISC_FSP_MASK                   0x0000000F /* Frame Scheduling Policy mask */
+#define MAC_DMA_Q_MISC_FSP_ASAP                   0   /* ASAP */
+#define MAC_DMA_Q_MISC_FSP_CBR                    1   /* CBR */
+#define MAC_DMA_Q_MISC_FSP_DBA_GATED              2   /* DMA Beacon Alert gated */
+#define MAC_DMA_Q_MISC_FSP_TIM_GATED              3   /* TIM gated */
+#define MAC_DMA_Q_MISC_FSP_BEACON_SENT_GATED      4   /* Beacon-sent-gated */
+#define MAC_DMA_Q_MISC_ONE_SHOT_EN_MASK           0x00000010 /* OneShot enable */
+#define MAC_DMA_Q_MISC_CBR_INCR_DIS1_MASK         0x00000020 /* Disable CBR expired counter incr
+                                                        (empty q) */
+#define MAC_DMA_Q_MISC_CBR_INCR_DIS0_MASK         0x00000040 /* Disable CBR expired counter incr
+                                                        (empty beacon q) */
+#define MAC_DMA_Q_MISC_BEACON_USE_MASK            0x00000080 /* Beacon use indication */
+#define MAC_DMA_Q_MISC_CBR_EXP_CNTR_LIMIT_MASK    0x00000100 /* CBR expired counter limit enable */
+#define MAC_DMA_Q_MISC_RDYTIME_EXP_POLICY_MASK    0x00000200 /* Enable TXE cleared on ReadyTime expired or VEOL */
+#define MAC_DMA_Q_MISC_RESET_CBR_EXP_CTR_MASK     0x00000400 /* Reset CBR expired counter */
+#define MAC_DMA_Q_MISC_DCU_EARLY_TERM_REQ_MASK    0x00000800 /* DCU frame early termination request control */
+
+#define MAC_DMA_Q0_STS_ADDRESS                   0x00000A00  /* MAC Miscellaneous QCU status */
+#define MAC_DMA_Q1_STS_ADDRESS                   0x00000A04  /* MAC Miscellaneous QCU status */
+#define MAC_DMA_Q2_STS_ADDRESS                   0x00000A08  /* MAC Miscellaneous QCU status */
+#define MAC_DMA_Q3_STS_ADDRESS                   0x00000A0C  /* MAC Miscellaneous QCU status */
+#define MAC_DMA_Q4_STS_ADDRESS                   0x00000A10  /* MAC Miscellaneous QCU status */
+#define MAC_DMA_Q5_STS_ADDRESS                   0x00000A14  /* MAC Miscellaneous QCU status */
+#define MAC_DMA_Q6_STS_ADDRESS                   0x00000A18  /* MAC Miscellaneous QCU status */
+#define MAC_DMA_Q7_STS_ADDRESS                   0x00000A1C  /* MAC Miscellaneous QCU status */
+#define MAC_DMA_Q8_STS_ADDRESS                   0x00000A20  /* MAC Miscellaneous QCU status */
+#define MAC_DMA_Q9_STS_ADDRESS                   0x00000A24  /* MAC Miscellaneous QCU status */
+#define MAC_DMA_QSTS_ADDRESS(_i)                 (MAC_DMA_Q0_STS_ADDRESS + ((_i)<<2))
+
+#define MAC_DMA_Q_STS_PEND_FR_CNT_MASK           0x00000003 /* Mask for Pending Frame Count */
+#define MAC_DMA_Q_STS_CBR_EXP_CNT_MASK           0x0000FF00 /* Mask for CBR expired counter */
+
+#define MAC_DMA_Q_RDYTIMESHDN_ADDRESS            0x00000A40  /* MAC ReadyTimeShutdown status */
+
+/* DCU registers */
+
+#define MAC_DMA_D0_QCUMASK_ADDRESS               0x00001000  /* MAC QCU Mask */
+#define MAC_DMA_D1_QCUMASK_ADDRESS               0x00001004  /* MAC QCU Mask */
+#define MAC_DMA_D2_QCUMASK_ADDRESS               0x00001008  /* MAC QCU Mask */
+#define MAC_DMA_D3_QCUMASK_ADDRESS               0x0000100C  /* MAC QCU Mask */
+#define MAC_DMA_D4_QCUMASK_ADDRESS               0x00001010  /* MAC QCU Mask */
+#define MAC_DMA_D5_QCUMASK_ADDRESS               0x00001014  /* MAC QCU Mask */
+#define MAC_DMA_D6_QCUMASK_ADDRESS               0x00001018  /* MAC QCU Mask */
+#define MAC_DMA_D7_QCUMASK_ADDRESS               0x0000101C  /* MAC QCU Mask */
+#define MAC_DMA_D8_QCUMASK_ADDRESS               0x00001020  /* MAC QCU Mask */
+#define MAC_DMA_D9_QCUMASK_ADDRESS               0x00001024  /* MAC QCU Mask */
+#define MAC_DMA_DQCUMASK_ADDRESS(_i)             (MAC_DMA_D0_QCUMASK_ADDRESS + ((_i)<<2))
+
+#define MAC_DMA_D_QCUMASK_MASK                   0x000003FF /* Mask for QCU Mask (QCU 0-9) */
+
+#define MAC_DMA_D_GBL_IFS_SIFS_ADDRESS           0x00001030  /* DCU global SIFS settings */
+
+
+#define MAC_DMA_D0_LCL_IFS_ADDRESS               0x00001040  /* MAC DCU-specific IFS settings */
+#define MAC_DMA_D1_LCL_IFS_ADDRESS               0x00001044  /* MAC DCU-specific IFS settings */
+#define MAC_DMA_D2_LCL_IFS_ADDRESS               0x00001048  /* MAC DCU-specific IFS settings */
+#define MAC_DMA_D3_LCL_IFS_ADDRESS               0x0000104C  /* MAC DCU-specific IFS settings */
+#define MAC_DMA_D4_LCL_IFS_ADDRESS               0x00001050  /* MAC DCU-specific IFS settings */
+#define MAC_DMA_D5_LCL_IFS_ADDRESS               0x00001054  /* MAC DCU-specific IFS settings */
+#define MAC_DMA_D6_LCL_IFS_ADDRESS               0x00001058  /* MAC DCU-specific IFS settings */
+#define MAC_DMA_D7_LCL_IFS_ADDRESS               0x0000105C  /* MAC DCU-specific IFS settings */
+#define MAC_DMA_D8_LCL_IFS_ADDRESS               0x00001060  /* MAC DCU-specific IFS settings */
+#define MAC_DMA_D9_LCL_IFS_ADDRESS               0x00001064  /* MAC DCU-specific IFS settings */
+#define MAC_DMA_DLCL_IFS_ADDRESS(_i)             (MAC_DMA_D0_LCL_IFS_ADDRESS + ((_i)<<2))
+#define MAC_DMA_D_LCL_IFS_CWMIN_MASK             0x000003FF /* Mask for CW_MIN */
+#define MAC_DMA_D_LCL_IFS_CWMIN_LSB              0
+#define MAC_DMA_D_LCL_IFS_CWMAX_MASK             0x000FFC00 /* Mask for CW_MAX */
+#define MAC_DMA_D_LCL_IFS_CWMAX_LSB              10
+#define MAC_DMA_D_LCL_IFS_AIFS_MASK              0x0FF00000 /* Mask for AIFS */
+#define MAC_DMA_D_LCL_IFS_AIFS_LSB               20
+/*
+ *  Note:  even though this field is 8 bits wide the
+ *  maximum supported AIFS value is 0xFc.  Setting the AIFS value
+ *  to 0xFd 0xFe, or 0xFf will not work correctly and will cause
+ *  the DCU to hang.
+ */
+#define MAC_DMA_D_GBL_IFS_SLOT_ADDRESS           0x00001070  /* DC global slot interval */
+
+#define MAC_DMA_D0_RETRY_LIMIT_ADDRESS           0x00001080  /* MAC Retry limits */
+#define MAC_DMA_D1_RETRY_LIMIT_ADDRESS           0x00001084  /* MAC Retry limits */
+#define MAC_DMA_D2_RETRY_LIMIT_ADDRESS           0x00001088  /* MAC Retry limits */
+#define MAC_DMA_D3_RETRY_LIMIT_ADDRESS           0x0000108C  /* MAC Retry limits */
+#define MAC_DMA_D4_RETRY_LIMIT_ADDRESS           0x00001090  /* MAC Retry limits */
+#define MAC_DMA_D5_RETRY_LIMIT_ADDRESS           0x00001094  /* MAC Retry limits */
+#define MAC_DMA_D6_RETRY_LIMIT_ADDRESS           0x00001098  /* MAC Retry limits */
+#define MAC_DMA_D7_RETRY_LIMIT_ADDRESS           0x0000109C  /* MAC Retry limits */
+#define MAC_DMA_D8_RETRY_LIMIT_ADDRESS           0x000010A0  /* MAC Retry limits */
+#define MAC_DMA_D9_RETRY_LIMIT_ADDRESS           0x000010A4  /* MAC Retry limits */
+#define MAC_DMA_DRETRY_LIMIT_ADDRESS(_i)         (MAC_DMA_D0_RETRY_LIMIT_ADDRESS + ((_i)<<2))
+
+#define MAC_DMA_D_RETRY_LIMIT_FR_RTS_MASK        0x0000000F /* frame RTS failure limit */
+#define MAC_DMA_D_RETRY_LIMIT_FR_RTS_LSB         0
+#define MAC_DMA_D_RETRY_LIMIT_STA_RTS_MASK       0x00003F00 /* station RTS failure limit */
+#define MAC_DMA_D_RETRY_LIMIT_STA_RTS_LSB        8
+#define MAC_DMA_D_RETRY_LIMIT_STA_DATA_MASK      0x000FC000 /* station short retry limit */
+#define MAC_DMA_D_RETRY_LIMIT_STA_DATA_LSB       14
+
+#define MAC_DMA_D_GBL_IFS_EIFS_ADDRESS           0x000010B0  /* DCU global EIFS setting */
+
+#define MAC_DMA_D0_CHNTIME_ADDRESS               0x000010C0  /* MAC ChannelTime settings */
+#define MAC_DMA_D1_CHNTIME_ADDRESS               0x000010C4  /* MAC ChannelTime settings */
+#define MAC_DMA_D2_CHNTIME_ADDRESS               0x000010C8  /* MAC ChannelTime settings */
+#define MAC_DMA_D3_CHNTIME_ADDRESS               0x000010CC  /* MAC ChannelTime settings */
+#define MAC_DMA_D4_CHNTIME_ADDRESS               0x000010D0  /* MAC ChannelTime settings */
+#define MAC_DMA_D5_CHNTIME_ADDRESS               0x000010D4  /* MAC ChannelTime settings */
+#define MAC_DMA_D6_CHNTIME_ADDRESS               0x000010D8  /* MAC ChannelTime settings */
+#define MAC_DMA_D7_CHNTIME_ADDRESS               0x000010DC  /* MAC ChannelTime settings */
+#define MAC_DMA_D8_CHNTIME_ADDRESS               0x000010E0  /* MAC ChannelTime settings */
+#define MAC_DMA_D9_CHNTIME_ADDRESS               0x000010E4  /* MAC ChannelTime settings */
+#define MAC_DMA_DCHNTIME_ADDRESS(_i)             (MAC_DMA_D0_CHNTIME_ADDRESS + ((_i)<<2))
+
+#define MAC_DMA_D_CHNTIME_DUR_MASK               0x000FFFFF /* ChannelTime duration (us) */
+#define MAC_DMA_D_CHNTIME_DUR_LSB                0 /* Shift for ChannelTime duration */
+#define MAC_DMA_D_CHNTIME_EN_MASK                0x00100000 /* ChannelTime enable */
+
+#define MAC_DMA_D_GBL_IFS_MISC_ADDRESS           0x000010f0  /* DCU global misc. IFS settings */
+#define MAC_DMA_D_GBL_IFS_MISC_LFSR_SLICE_SEL_MASK 0x00000007 /* LFSR slice select */
+#define MAC_DMA_D_GBL_IFS_MISC_TURBO_MODE_MASK     0x00000008 /* Turbo mode indication */
+#define MAC_DMA_D_GBL_IFS_MISC_DCU_ARBITER_DLY_MASK 0x00300000 /* DCU arbiter delay */
+#define MAC_DMA_D_GBL_IFS_IGNORE_BACKOFF_MASK      0x10000000
+
+#define MAC_DMA_D0_MISC_ADDRESS                  0x00001100  /* MAC Miscellaneous DCU-specific settings */
+#define MAC_DMA_D1_MISC_ADDRESS                  0x00001104  /* MAC Miscellaneous DCU-specific settings */
+#define MAC_DMA_D2_MISC_ADDRESS                  0x00001108  /* MAC Miscellaneous DCU-specific settings */
+#define MAC_DMA_D3_MISC_ADDRESS                  0x0000110C  /* MAC Miscellaneous DCU-specific settings */
+#define MAC_DMA_D4_MISC_ADDRESS                  0x00001110  /* MAC Miscellaneous DCU-specific settings */
+#define MAC_DMA_D5_MISC_ADDRESS                  0x00001114  /* MAC Miscellaneous DCU-specific settings */
+#define MAC_DMA_D6_MISC_ADDRESS                  0x00001118  /* MAC Miscellaneous DCU-specific settings */
+#define MAC_DMA_D7_MISC_ADDRESS                  0x0000111C  /* MAC Miscellaneous DCU-specific settings */
+#define MAC_DMA_D8_MISC_ADDRESS                  0x00001120  /* MAC Miscellaneous DCU-specific settings */
+#define MAC_DMA_D9_MISC_ADDRESS                  0x00001124  /* MAC Miscellaneous DCU-specific settings */
+#define MAC_DMA_DMISC_ADDRESS(_i)                (MAC_DMA_D0_MISC_ADDRESS + ((_i)<<2))
+
+#define MAC_DMA_D0_EOL_ADDRESS                  0x00001180
+#define MAC_DMA_D1_EOL_ADDRESS                  0x00001184
+#define MAC_DMA_D2_EOL_ADDRESS                  0x00001188
+#define MAC_DMA_D3_EOL_ADDRESS                  0x0000118C
+#define MAC_DMA_D4_EOL_ADDRESS                  0x00001190
+#define MAC_DMA_D5_EOL_ADDRESS                  0x00001194
+#define MAC_DMA_D6_EOL_ADDRESS                  0x00001198
+#define MAC_DMA_D7_EOL_ADDRESS                  0x0000119C
+#define MAC_DMA_D8_EOL_ADDRESS                  0x00001200
+#define MAC_DMA_D9_EOL_ADDRESS                  0x00001204
+#define MAC_DMA_DEOL_ADDRESS(_i)                (MAC_DMA_D0_EOL_ADDRESS + ((_i)<<2))
+
+#define MAC_DMA_D_MISC_BKOFF_THRESH_MASK         0x0000003F /* Backoff threshold */
+#define MAC_DMA_D_MISC_BACK_OFF_THRESH_LSB       0
+#define MAC_DMA_D_MISC_ETS_RTS_MASK              0x00000040 /* End of transmission series
+                                                          station RTS/data failure
+                                                          count reset policy */
+#define MAC_DMA_D_MISC_ETS_CW_MASK               0x00000080 /* End of transmission series
+                                                          CW reset policy */
+#define MAC_DMA_D_MISC_FRAG_WAIT_EN_MASK         0x00000100  /* Fragment Starvation Policy */
+
+#define MAC_DMA_D_MISC_FRAG_BKOFF_EN_MASK        0x00000200 /* Backoff during a frag burst */
+#define MAC_DMA_D_MISC_HCF_POLL_EN_MASK          0x00000800 /* HFC poll enable */
+#define MAC_DMA_D_MISC_BKOFF_PERSISTENCE_MASK    0x00001000 /* Backoff persistence factor
+                                                          setting */
+#define MAC_DMA_D_MISC_VIR_COL_HANDLING_MASK     0x0000C000 /* Mask for Virtual collision
+                                                          handling policy */
+#define MAC_DMA_D_MISC_VIR_COL_HANDLING_LSB      14
+#define MAC_DMA_D_MISC_VIR_COL_HANDLING_DEFAULT  0   /* Normal */
+#define MAC_DMA_D_MISC_VIR_COL_HANDLING_IGNORE   1   /* Ignore */
+#define MAC_DMA_D_MISC_BEACON_USE_MASK           0x00010000 /*  Beacon use indication */
+#define MAC_DMA_D_MISC_ARB_LOCKOUT_CNTRL_MASK 0x00060000 /*  Mask for DCU arbiter lockout control */
+#define MAC_DMA_D_MISC_ARB_LOCKOUT_CNTRL_LSB  17
+#define MAC_DMA_D_MISC_ARB_LOCKOUT_CNTRL_NONE     0        /*  No lockout*/
+#define MAC_DMA_D_MISC_ARB_LOCKOUT_CNTRL_INTRA_FR 1        /*  Intra-frame*/
+#define MAC_DMA_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL   2        /*  Global */
+#define MAC_DMA_D_MISC_ARB_LOCKOUT_IGNORE_MASK 0x00080000 /*  DCU arbiter lockout ignore control */
+#define MAC_DMA_D_MISC_SEQ_NUM_INCR_DIS_MASK    0x00100000 /* Sequence number increment disable */
+#define MAC_DMA_D_MISC_POST_FR_BKOFF_DIS_MASK   0x00200000 /* Post-frame backoff disable */
+#define MAC_DMA_D_MISC_VIRT_COLL_POLICY_MASK    0x00400000 /* Virtual coll. handling policy */
+#define MAC_DMA_D_MISC_BLOWN_IFS_POLICY_MASK    0x00800000 /* Blown IFS handling policy */
+
+#define MAC_DMA_D_SEQNUM_ADDRESS                0x00001140  /* MAC Frame sequence number */
+
+
+
+#define MAC_DMA_D_FPCTL_ADDRESS                  0x00001230      /* DCU frame prefetch settings */
+#define MAC_DMA_D_TXPSE_ADDRESS                  0x00001270      /* DCU transmit pause control/status */
+
+#endif /* _AR6000_DMMAEG_H_ */
diff --git a/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/mac_pcu_reg.h b/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/mac_pcu_reg.h
new file mode 100644
index 00000000000..6ccb08c5dab
--- /dev/null
+++ b/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/mac_pcu_reg.h
@@ -0,0 +1,3065 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _MAC_PCU_REG_H_
+#define _MAC_PCU_REG_H_
+
+#define MAC_PCU_STA_ADDR_L32_ADDRESS             0x00008000
+#define MAC_PCU_STA_ADDR_L32_OFFSET              0x00000000
+#define MAC_PCU_STA_ADDR_L32_ADDR_31_0_MSB       31
+#define MAC_PCU_STA_ADDR_L32_ADDR_31_0_LSB       0
+#define MAC_PCU_STA_ADDR_L32_ADDR_31_0_MASK      0xffffffff
+#define MAC_PCU_STA_ADDR_L32_ADDR_31_0_GET(x)    (((x) & MAC_PCU_STA_ADDR_L32_ADDR_31_0_MASK) >> MAC_PCU_STA_ADDR_L32_ADDR_31_0_LSB)
+#define MAC_PCU_STA_ADDR_L32_ADDR_31_0_SET(x)    (((x) << MAC_PCU_STA_ADDR_L32_ADDR_31_0_LSB) & MAC_PCU_STA_ADDR_L32_ADDR_31_0_MASK)
+
+#define MAC_PCU_STA_ADDR_U16_ADDRESS             0x00008004
+#define MAC_PCU_STA_ADDR_U16_OFFSET              0x00000004
+#define MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_MSB 31
+#define MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_LSB 31
+#define MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_MASK 0x80000000
+#define MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_MASK) >> MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_LSB)
+#define MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_LSB) & MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_MASK)
+#define MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_MSB    30
+#define MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_LSB    30
+#define MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_MASK   0x40000000
+#define MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_MASK) >> MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_LSB)
+#define MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_LSB) & MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_MASK)
+#define MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_MSB 29
+#define MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_LSB 29
+#define MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_MASK 0x20000000
+#define MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_MASK) >> MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_LSB)
+#define MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_LSB) & MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_MASK)
+#define MAC_PCU_STA_ADDR_U16_KSRCH_MODE_MSB      28
+#define MAC_PCU_STA_ADDR_U16_KSRCH_MODE_LSB      28
+#define MAC_PCU_STA_ADDR_U16_KSRCH_MODE_MASK     0x10000000
+#define MAC_PCU_STA_ADDR_U16_KSRCH_MODE_GET(x)   (((x) & MAC_PCU_STA_ADDR_U16_KSRCH_MODE_MASK) >> MAC_PCU_STA_ADDR_U16_KSRCH_MODE_LSB)
+#define MAC_PCU_STA_ADDR_U16_KSRCH_MODE_SET(x)   (((x) << MAC_PCU_STA_ADDR_U16_KSRCH_MODE_LSB) & MAC_PCU_STA_ADDR_U16_KSRCH_MODE_MASK)
+#define MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_MSB 27
+#define MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_LSB 27
+#define MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_MASK 0x08000000
+#define MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_MASK) >> MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_LSB)
+#define MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_LSB) & MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_MASK)
+#define MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_MSB 26
+#define MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_LSB 26
+#define MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_MASK 0x04000000
+#define MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_MASK) >> MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_LSB)
+#define MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_LSB) & MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_MASK)
+#define MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_MSB   25
+#define MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_LSB   25
+#define MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_MASK  0x02000000
+#define MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_MASK) >> MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_LSB)
+#define MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_LSB) & MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_MASK)
+#define MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_MSB      24
+#define MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_LSB      24
+#define MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_MASK     0x01000000
+#define MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_GET(x)   (((x) & MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_MASK) >> MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_LSB)
+#define MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_SET(x)   (((x) << MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_LSB) & MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_MASK)
+#define MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_MSB     23
+#define MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_LSB     23
+#define MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_MASK    0x00800000
+#define MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_GET(x)  (((x) & MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_MASK) >> MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_LSB)
+#define MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_SET(x)  (((x) << MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_LSB) & MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_MASK)
+#define MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_MSB   22
+#define MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_LSB   22
+#define MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_MASK  0x00400000
+#define MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_MASK) >> MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_LSB)
+#define MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_LSB) & MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_MASK)
+#define MAC_PCU_STA_ADDR_U16_USE_DEFANT_MSB      21
+#define MAC_PCU_STA_ADDR_U16_USE_DEFANT_LSB      21
+#define MAC_PCU_STA_ADDR_U16_USE_DEFANT_MASK     0x00200000
+#define MAC_PCU_STA_ADDR_U16_USE_DEFANT_GET(x)   (((x) & MAC_PCU_STA_ADDR_U16_USE_DEFANT_MASK) >> MAC_PCU_STA_ADDR_U16_USE_DEFANT_LSB)
+#define MAC_PCU_STA_ADDR_U16_USE_DEFANT_SET(x)   (((x) << MAC_PCU_STA_ADDR_U16_USE_DEFANT_LSB) & MAC_PCU_STA_ADDR_U16_USE_DEFANT_MASK)
+#define MAC_PCU_STA_ADDR_U16_PCF_MSB             20
+#define MAC_PCU_STA_ADDR_U16_PCF_LSB             20
+#define MAC_PCU_STA_ADDR_U16_PCF_MASK            0x00100000
+#define MAC_PCU_STA_ADDR_U16_PCF_GET(x)          (((x) & MAC_PCU_STA_ADDR_U16_PCF_MASK) >> MAC_PCU_STA_ADDR_U16_PCF_LSB)
+#define MAC_PCU_STA_ADDR_U16_PCF_SET(x)          (((x) << MAC_PCU_STA_ADDR_U16_PCF_LSB) & MAC_PCU_STA_ADDR_U16_PCF_MASK)
+#define MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_MSB     19
+#define MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_LSB     19
+#define MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_MASK    0x00080000
+#define MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_GET(x)  (((x) & MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_MASK) >> MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_LSB)
+#define MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_SET(x)  (((x) << MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_LSB) & MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_MASK)
+#define MAC_PCU_STA_ADDR_U16_PW_SAVE_MSB         18
+#define MAC_PCU_STA_ADDR_U16_PW_SAVE_LSB         18
+#define MAC_PCU_STA_ADDR_U16_PW_SAVE_MASK        0x00040000
+#define MAC_PCU_STA_ADDR_U16_PW_SAVE_GET(x)      (((x) & MAC_PCU_STA_ADDR_U16_PW_SAVE_MASK) >> MAC_PCU_STA_ADDR_U16_PW_SAVE_LSB)
+#define MAC_PCU_STA_ADDR_U16_PW_SAVE_SET(x)      (((x) << MAC_PCU_STA_ADDR_U16_PW_SAVE_LSB) & MAC_PCU_STA_ADDR_U16_PW_SAVE_MASK)
+#define MAC_PCU_STA_ADDR_U16_ADHOC_MSB           17
+#define MAC_PCU_STA_ADDR_U16_ADHOC_LSB           17
+#define MAC_PCU_STA_ADDR_U16_ADHOC_MASK          0x00020000
+#define MAC_PCU_STA_ADDR_U16_ADHOC_GET(x)        (((x) & MAC_PCU_STA_ADDR_U16_ADHOC_MASK) >> MAC_PCU_STA_ADDR_U16_ADHOC_LSB)
+#define MAC_PCU_STA_ADDR_U16_ADHOC_SET(x)        (((x) << MAC_PCU_STA_ADDR_U16_ADHOC_LSB) & MAC_PCU_STA_ADDR_U16_ADHOC_MASK)
+#define MAC_PCU_STA_ADDR_U16_STA_AP_MSB          16
+#define MAC_PCU_STA_ADDR_U16_STA_AP_LSB          16
+#define MAC_PCU_STA_ADDR_U16_STA_AP_MASK         0x00010000
+#define MAC_PCU_STA_ADDR_U16_STA_AP_GET(x)       (((x) & MAC_PCU_STA_ADDR_U16_STA_AP_MASK) >> MAC_PCU_STA_ADDR_U16_STA_AP_LSB)
+#define MAC_PCU_STA_ADDR_U16_STA_AP_SET(x)       (((x) << MAC_PCU_STA_ADDR_U16_STA_AP_LSB) & MAC_PCU_STA_ADDR_U16_STA_AP_MASK)
+#define MAC_PCU_STA_ADDR_U16_ADDR_47_32_MSB      15
+#define MAC_PCU_STA_ADDR_U16_ADDR_47_32_LSB      0
+#define MAC_PCU_STA_ADDR_U16_ADDR_47_32_MASK     0x0000ffff
+#define MAC_PCU_STA_ADDR_U16_ADDR_47_32_GET(x)   (((x) & MAC_PCU_STA_ADDR_U16_ADDR_47_32_MASK) >> MAC_PCU_STA_ADDR_U16_ADDR_47_32_LSB)
+#define MAC_PCU_STA_ADDR_U16_ADDR_47_32_SET(x)   (((x) << MAC_PCU_STA_ADDR_U16_ADDR_47_32_LSB) & MAC_PCU_STA_ADDR_U16_ADDR_47_32_MASK)
+
+#define MAC_PCU_BSSID_L32_ADDRESS                0x00008008
+#define MAC_PCU_BSSID_L32_OFFSET                 0x00000008
+#define MAC_PCU_BSSID_L32_ADDR_MSB               31
+#define MAC_PCU_BSSID_L32_ADDR_LSB               0
+#define MAC_PCU_BSSID_L32_ADDR_MASK              0xffffffff
+#define MAC_PCU_BSSID_L32_ADDR_GET(x)            (((x) & MAC_PCU_BSSID_L32_ADDR_MASK) >> MAC_PCU_BSSID_L32_ADDR_LSB)
+#define MAC_PCU_BSSID_L32_ADDR_SET(x)            (((x) << MAC_PCU_BSSID_L32_ADDR_LSB) & MAC_PCU_BSSID_L32_ADDR_MASK)
+
+#define MAC_PCU_BSSID_U16_ADDRESS                0x0000800c
+#define MAC_PCU_BSSID_U16_OFFSET                 0x0000000c
+#define MAC_PCU_BSSID_U16_AID_MSB                26
+#define MAC_PCU_BSSID_U16_AID_LSB                16
+#define MAC_PCU_BSSID_U16_AID_MASK               0x07ff0000
+#define MAC_PCU_BSSID_U16_AID_GET(x)             (((x) & MAC_PCU_BSSID_U16_AID_MASK) >> MAC_PCU_BSSID_U16_AID_LSB)
+#define MAC_PCU_BSSID_U16_AID_SET(x)             (((x) << MAC_PCU_BSSID_U16_AID_LSB) & MAC_PCU_BSSID_U16_AID_MASK)
+#define MAC_PCU_BSSID_U16_ADDR_MSB               15
+#define MAC_PCU_BSSID_U16_ADDR_LSB               0
+#define MAC_PCU_BSSID_U16_ADDR_MASK              0x0000ffff
+#define MAC_PCU_BSSID_U16_ADDR_GET(x)            (((x) & MAC_PCU_BSSID_U16_ADDR_MASK) >> MAC_PCU_BSSID_U16_ADDR_LSB)
+#define MAC_PCU_BSSID_U16_ADDR_SET(x)            (((x) << MAC_PCU_BSSID_U16_ADDR_LSB) & MAC_PCU_BSSID_U16_ADDR_MASK)
+
+#define MAC_PCU_BCN_RSSI_AVE_ADDRESS             0x00008010
+#define MAC_PCU_BCN_RSSI_AVE_OFFSET              0x00000010
+#define MAC_PCU_BCN_RSSI_AVE_VALUE_MSB           11
+#define MAC_PCU_BCN_RSSI_AVE_VALUE_LSB           0
+#define MAC_PCU_BCN_RSSI_AVE_VALUE_MASK          0x00000fff
+#define MAC_PCU_BCN_RSSI_AVE_VALUE_GET(x)        (((x) & MAC_PCU_BCN_RSSI_AVE_VALUE_MASK) >> MAC_PCU_BCN_RSSI_AVE_VALUE_LSB)
+#define MAC_PCU_BCN_RSSI_AVE_VALUE_SET(x)        (((x) << MAC_PCU_BCN_RSSI_AVE_VALUE_LSB) & MAC_PCU_BCN_RSSI_AVE_VALUE_MASK)
+
+#define MAC_PCU_ACK_CTS_TIMEOUT_ADDRESS          0x00008014
+#define MAC_PCU_ACK_CTS_TIMEOUT_OFFSET           0x00000014
+#define MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_MSB  29
+#define MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_LSB  16
+#define MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_MASK 0x3fff0000
+#define MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_GET(x) (((x) & MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_MASK) >> MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_LSB)
+#define MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_SET(x) (((x) << MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_LSB) & MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_MASK)
+#define MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_MSB  13
+#define MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_LSB  0
+#define MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_MASK 0x00003fff
+#define MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_GET(x) (((x) & MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_MASK) >> MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_LSB)
+#define MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_SET(x) (((x) << MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_LSB) & MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_MASK)
+
+#define MAC_PCU_BCN_RSSI_CTL_ADDRESS             0x00008018
+#define MAC_PCU_BCN_RSSI_CTL_OFFSET              0x00000018
+#define MAC_PCU_BCN_RSSI_CTL_RESET_MSB           29
+#define MAC_PCU_BCN_RSSI_CTL_RESET_LSB           29
+#define MAC_PCU_BCN_RSSI_CTL_RESET_MASK          0x20000000
+#define MAC_PCU_BCN_RSSI_CTL_RESET_GET(x)        (((x) & MAC_PCU_BCN_RSSI_CTL_RESET_MASK) >> MAC_PCU_BCN_RSSI_CTL_RESET_LSB)
+#define MAC_PCU_BCN_RSSI_CTL_RESET_SET(x)        (((x) << MAC_PCU_BCN_RSSI_CTL_RESET_LSB) & MAC_PCU_BCN_RSSI_CTL_RESET_MASK)
+#define MAC_PCU_BCN_RSSI_CTL_WEIGHT_MSB          28
+#define MAC_PCU_BCN_RSSI_CTL_WEIGHT_LSB          24
+#define MAC_PCU_BCN_RSSI_CTL_WEIGHT_MASK         0x1f000000
+#define MAC_PCU_BCN_RSSI_CTL_WEIGHT_GET(x)       (((x) & MAC_PCU_BCN_RSSI_CTL_WEIGHT_MASK) >> MAC_PCU_BCN_RSSI_CTL_WEIGHT_LSB)
+#define MAC_PCU_BCN_RSSI_CTL_WEIGHT_SET(x)       (((x) << MAC_PCU_BCN_RSSI_CTL_WEIGHT_LSB) & MAC_PCU_BCN_RSSI_CTL_WEIGHT_MASK)
+#define MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_MSB 23
+#define MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_LSB 16
+#define MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_MASK 0x00ff0000
+#define MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_GET(x) (((x) & MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_MASK) >> MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_LSB)
+#define MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_SET(x) (((x) << MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_LSB) & MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_MASK)
+#define MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_MSB     15
+#define MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_LSB     8
+#define MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_MASK    0x0000ff00
+#define MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_GET(x)  (((x) & MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_MASK) >> MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_LSB)
+#define MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_SET(x)  (((x) << MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_LSB) & MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_MASK)
+#define MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_MSB 7
+#define MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_LSB 0
+#define MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_MASK 0x000000ff
+#define MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_GET(x) (((x) & MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_MASK) >> MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_LSB)
+#define MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_SET(x) (((x) << MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_LSB) & MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_MASK)
+
+#define MAC_PCU_USEC_LATENCY_ADDRESS             0x0000801c
+#define MAC_PCU_USEC_LATENCY_OFFSET              0x0000001c
+#define MAC_PCU_USEC_LATENCY_RX_LATENCY_MSB      28
+#define MAC_PCU_USEC_LATENCY_RX_LATENCY_LSB      23
+#define MAC_PCU_USEC_LATENCY_RX_LATENCY_MASK     0x1f800000
+#define MAC_PCU_USEC_LATENCY_RX_LATENCY_GET(x)   (((x) & MAC_PCU_USEC_LATENCY_RX_LATENCY_MASK) >> MAC_PCU_USEC_LATENCY_RX_LATENCY_LSB)
+#define MAC_PCU_USEC_LATENCY_RX_LATENCY_SET(x)   (((x) << MAC_PCU_USEC_LATENCY_RX_LATENCY_LSB) & MAC_PCU_USEC_LATENCY_RX_LATENCY_MASK)
+#define MAC_PCU_USEC_LATENCY_TX_LATENCY_MSB      22
+#define MAC_PCU_USEC_LATENCY_TX_LATENCY_LSB      14
+#define MAC_PCU_USEC_LATENCY_TX_LATENCY_MASK     0x007fc000
+#define MAC_PCU_USEC_LATENCY_TX_LATENCY_GET(x)   (((x) & MAC_PCU_USEC_LATENCY_TX_LATENCY_MASK) >> MAC_PCU_USEC_LATENCY_TX_LATENCY_LSB)
+#define MAC_PCU_USEC_LATENCY_TX_LATENCY_SET(x)   (((x) << MAC_PCU_USEC_LATENCY_TX_LATENCY_LSB) & MAC_PCU_USEC_LATENCY_TX_LATENCY_MASK)
+#define MAC_PCU_USEC_LATENCY_USEC_MSB            7
+#define MAC_PCU_USEC_LATENCY_USEC_LSB            0
+#define MAC_PCU_USEC_LATENCY_USEC_MASK           0x000000ff
+#define MAC_PCU_USEC_LATENCY_USEC_GET(x)         (((x) & MAC_PCU_USEC_LATENCY_USEC_MASK) >> MAC_PCU_USEC_LATENCY_USEC_LSB)
+#define MAC_PCU_USEC_LATENCY_USEC_SET(x)         (((x) << MAC_PCU_USEC_LATENCY_USEC_LSB) & MAC_PCU_USEC_LATENCY_USEC_MASK)
+
+#define PCU_MAX_CFP_DUR_ADDRESS                  0x00008020
+#define PCU_MAX_CFP_DUR_OFFSET                   0x00000020
+#define PCU_MAX_CFP_DUR_VALUE_MSB                15
+#define PCU_MAX_CFP_DUR_VALUE_LSB                0
+#define PCU_MAX_CFP_DUR_VALUE_MASK               0x0000ffff
+#define PCU_MAX_CFP_DUR_VALUE_GET(x)             (((x) & PCU_MAX_CFP_DUR_VALUE_MASK) >> PCU_MAX_CFP_DUR_VALUE_LSB)
+#define PCU_MAX_CFP_DUR_VALUE_SET(x)             (((x) << PCU_MAX_CFP_DUR_VALUE_LSB) & PCU_MAX_CFP_DUR_VALUE_MASK)
+
+#define MAC_PCU_RX_FILTER_ADDRESS                0x00008024
+#define MAC_PCU_RX_FILTER_OFFSET                 0x00000024
+#define MAC_PCU_RX_FILTER_GENERIC_FILTER_MSB     25
+#define MAC_PCU_RX_FILTER_GENERIC_FILTER_LSB     24
+#define MAC_PCU_RX_FILTER_GENERIC_FILTER_MASK    0x03000000
+#define MAC_PCU_RX_FILTER_GENERIC_FILTER_GET(x)  (((x) & MAC_PCU_RX_FILTER_GENERIC_FILTER_MASK) >> MAC_PCU_RX_FILTER_GENERIC_FILTER_LSB)
+#define MAC_PCU_RX_FILTER_GENERIC_FILTER_SET(x)  (((x) << MAC_PCU_RX_FILTER_GENERIC_FILTER_LSB) & MAC_PCU_RX_FILTER_GENERIC_FILTER_MASK)
+#define MAC_PCU_RX_FILTER_GENERIC_FTYPE_MSB      23
+#define MAC_PCU_RX_FILTER_GENERIC_FTYPE_LSB      18
+#define MAC_PCU_RX_FILTER_GENERIC_FTYPE_MASK     0x00fc0000
+#define MAC_PCU_RX_FILTER_GENERIC_FTYPE_GET(x)   (((x) & MAC_PCU_RX_FILTER_GENERIC_FTYPE_MASK) >> MAC_PCU_RX_FILTER_GENERIC_FTYPE_LSB)
+#define MAC_PCU_RX_FILTER_GENERIC_FTYPE_SET(x)   (((x) << MAC_PCU_RX_FILTER_GENERIC_FTYPE_LSB) & MAC_PCU_RX_FILTER_GENERIC_FTYPE_MASK)
+#define MAC_PCU_RX_FILTER_FROM_TO_DS_MSB         17
+#define MAC_PCU_RX_FILTER_FROM_TO_DS_LSB         17
+#define MAC_PCU_RX_FILTER_FROM_TO_DS_MASK        0x00020000
+#define MAC_PCU_RX_FILTER_FROM_TO_DS_GET(x)      (((x) & MAC_PCU_RX_FILTER_FROM_TO_DS_MASK) >> MAC_PCU_RX_FILTER_FROM_TO_DS_LSB)
+#define MAC_PCU_RX_FILTER_FROM_TO_DS_SET(x)      (((x) << MAC_PCU_RX_FILTER_FROM_TO_DS_LSB) & MAC_PCU_RX_FILTER_FROM_TO_DS_MASK)
+#define MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_MSB 16
+#define MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_LSB 16
+#define MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_MASK 0x00010000
+#define MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_GET(x) (((x) & MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_MASK) >> MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_LSB)
+#define MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_SET(x) (((x) << MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_LSB) & MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_MASK)
+#define MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_MSB    15
+#define MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_LSB    15
+#define MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_MASK   0x00008000
+#define MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_GET(x) (((x) & MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_MASK) >> MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_LSB)
+#define MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_SET(x) (((x) << MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_LSB) & MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_MASK)
+#define MAC_PCU_RX_FILTER_PS_POLL_MSB            14
+#define MAC_PCU_RX_FILTER_PS_POLL_LSB            14
+#define MAC_PCU_RX_FILTER_PS_POLL_MASK           0x00004000
+#define MAC_PCU_RX_FILTER_PS_POLL_GET(x)         (((x) & MAC_PCU_RX_FILTER_PS_POLL_MASK) >> MAC_PCU_RX_FILTER_PS_POLL_LSB)
+#define MAC_PCU_RX_FILTER_PS_POLL_SET(x)         (((x) << MAC_PCU_RX_FILTER_PS_POLL_LSB) & MAC_PCU_RX_FILTER_PS_POLL_MASK)
+#define MAC_PCU_RX_FILTER_ASSUME_RADAR_MSB       13
+#define MAC_PCU_RX_FILTER_ASSUME_RADAR_LSB       13
+#define MAC_PCU_RX_FILTER_ASSUME_RADAR_MASK      0x00002000
+#define MAC_PCU_RX_FILTER_ASSUME_RADAR_GET(x)    (((x) & MAC_PCU_RX_FILTER_ASSUME_RADAR_MASK) >> MAC_PCU_RX_FILTER_ASSUME_RADAR_LSB)
+#define MAC_PCU_RX_FILTER_ASSUME_RADAR_SET(x)    (((x) << MAC_PCU_RX_FILTER_ASSUME_RADAR_LSB) & MAC_PCU_RX_FILTER_ASSUME_RADAR_MASK)
+#define MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_MSB 12
+#define MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_LSB 12
+#define MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_MASK 0x00001000
+#define MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_GET(x) (((x) & MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_MASK) >> MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_LSB)
+#define MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_SET(x) (((x) << MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_LSB) & MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_MASK)
+#define MAC_PCU_RX_FILTER_COMPRESSED_BA_MSB      11
+#define MAC_PCU_RX_FILTER_COMPRESSED_BA_LSB      11
+#define MAC_PCU_RX_FILTER_COMPRESSED_BA_MASK     0x00000800
+#define MAC_PCU_RX_FILTER_COMPRESSED_BA_GET(x)   (((x) & MAC_PCU_RX_FILTER_COMPRESSED_BA_MASK) >> MAC_PCU_RX_FILTER_COMPRESSED_BA_LSB)
+#define MAC_PCU_RX_FILTER_COMPRESSED_BA_SET(x)   (((x) << MAC_PCU_RX_FILTER_COMPRESSED_BA_LSB) & MAC_PCU_RX_FILTER_COMPRESSED_BA_MASK)
+#define MAC_PCU_RX_FILTER_COMPRESSED_BAR_MSB     10
+#define MAC_PCU_RX_FILTER_COMPRESSED_BAR_LSB     10
+#define MAC_PCU_RX_FILTER_COMPRESSED_BAR_MASK    0x00000400
+#define MAC_PCU_RX_FILTER_COMPRESSED_BAR_GET(x)  (((x) & MAC_PCU_RX_FILTER_COMPRESSED_BAR_MASK) >> MAC_PCU_RX_FILTER_COMPRESSED_BAR_LSB)
+#define MAC_PCU_RX_FILTER_COMPRESSED_BAR_SET(x)  (((x) << MAC_PCU_RX_FILTER_COMPRESSED_BAR_LSB) & MAC_PCU_RX_FILTER_COMPRESSED_BAR_MASK)
+#define MAC_PCU_RX_FILTER_MY_BEACON_MSB          9
+#define MAC_PCU_RX_FILTER_MY_BEACON_LSB          9
+#define MAC_PCU_RX_FILTER_MY_BEACON_MASK         0x00000200
+#define MAC_PCU_RX_FILTER_MY_BEACON_GET(x)       (((x) & MAC_PCU_RX_FILTER_MY_BEACON_MASK) >> MAC_PCU_RX_FILTER_MY_BEACON_LSB)
+#define MAC_PCU_RX_FILTER_MY_BEACON_SET(x)       (((x) << MAC_PCU_RX_FILTER_MY_BEACON_LSB) & MAC_PCU_RX_FILTER_MY_BEACON_MASK)
+#define MAC_PCU_RX_FILTER_SYNC_FRAME_MSB         8
+#define MAC_PCU_RX_FILTER_SYNC_FRAME_LSB         8
+#define MAC_PCU_RX_FILTER_SYNC_FRAME_MASK        0x00000100
+#define MAC_PCU_RX_FILTER_SYNC_FRAME_GET(x)      (((x) & MAC_PCU_RX_FILTER_SYNC_FRAME_MASK) >> MAC_PCU_RX_FILTER_SYNC_FRAME_LSB)
+#define MAC_PCU_RX_FILTER_SYNC_FRAME_SET(x)      (((x) << MAC_PCU_RX_FILTER_SYNC_FRAME_LSB) & MAC_PCU_RX_FILTER_SYNC_FRAME_MASK)
+#define MAC_PCU_RX_FILTER_PROBE_REQ_MSB          7
+#define MAC_PCU_RX_FILTER_PROBE_REQ_LSB          7
+#define MAC_PCU_RX_FILTER_PROBE_REQ_MASK         0x00000080
+#define MAC_PCU_RX_FILTER_PROBE_REQ_GET(x)       (((x) & MAC_PCU_RX_FILTER_PROBE_REQ_MASK) >> MAC_PCU_RX_FILTER_PROBE_REQ_LSB)
+#define MAC_PCU_RX_FILTER_PROBE_REQ_SET(x)       (((x) << MAC_PCU_RX_FILTER_PROBE_REQ_LSB) & MAC_PCU_RX_FILTER_PROBE_REQ_MASK)
+#define MAC_PCU_RX_FILTER_XR_POLL_MSB            6
+#define MAC_PCU_RX_FILTER_XR_POLL_LSB            6
+#define MAC_PCU_RX_FILTER_XR_POLL_MASK           0x00000040
+#define MAC_PCU_RX_FILTER_XR_POLL_GET(x)         (((x) & MAC_PCU_RX_FILTER_XR_POLL_MASK) >> MAC_PCU_RX_FILTER_XR_POLL_LSB)
+#define MAC_PCU_RX_FILTER_XR_POLL_SET(x)         (((x) << MAC_PCU_RX_FILTER_XR_POLL_LSB) & MAC_PCU_RX_FILTER_XR_POLL_MASK)
+#define MAC_PCU_RX_FILTER_PROMISCUOUS_MSB        5
+#define MAC_PCU_RX_FILTER_PROMISCUOUS_LSB        5
+#define MAC_PCU_RX_FILTER_PROMISCUOUS_MASK       0x00000020
+#define MAC_PCU_RX_FILTER_PROMISCUOUS_GET(x)     (((x) & MAC_PCU_RX_FILTER_PROMISCUOUS_MASK) >> MAC_PCU_RX_FILTER_PROMISCUOUS_LSB)
+#define MAC_PCU_RX_FILTER_PROMISCUOUS_SET(x)     (((x) << MAC_PCU_RX_FILTER_PROMISCUOUS_LSB) & MAC_PCU_RX_FILTER_PROMISCUOUS_MASK)
+#define MAC_PCU_RX_FILTER_BEACON_MSB             4
+#define MAC_PCU_RX_FILTER_BEACON_LSB             4
+#define MAC_PCU_RX_FILTER_BEACON_MASK            0x00000010
+#define MAC_PCU_RX_FILTER_BEACON_GET(x)          (((x) & MAC_PCU_RX_FILTER_BEACON_MASK) >> MAC_PCU_RX_FILTER_BEACON_LSB)
+#define MAC_PCU_RX_FILTER_BEACON_SET(x)          (((x) << MAC_PCU_RX_FILTER_BEACON_LSB) & MAC_PCU_RX_FILTER_BEACON_MASK)
+#define MAC_PCU_RX_FILTER_CONTROL_MSB            3
+#define MAC_PCU_RX_FILTER_CONTROL_LSB            3
+#define MAC_PCU_RX_FILTER_CONTROL_MASK           0x00000008
+#define MAC_PCU_RX_FILTER_CONTROL_GET(x)         (((x) & MAC_PCU_RX_FILTER_CONTROL_MASK) >> MAC_PCU_RX_FILTER_CONTROL_LSB)
+#define MAC_PCU_RX_FILTER_CONTROL_SET(x)         (((x) << MAC_PCU_RX_FILTER_CONTROL_LSB) & MAC_PCU_RX_FILTER_CONTROL_MASK)
+#define MAC_PCU_RX_FILTER_BROADCAST_MSB          2
+#define MAC_PCU_RX_FILTER_BROADCAST_LSB          2
+#define MAC_PCU_RX_FILTER_BROADCAST_MASK         0x00000004
+#define MAC_PCU_RX_FILTER_BROADCAST_GET(x)       (((x) & MAC_PCU_RX_FILTER_BROADCAST_MASK) >> MAC_PCU_RX_FILTER_BROADCAST_LSB)
+#define MAC_PCU_RX_FILTER_BROADCAST_SET(x)       (((x) << MAC_PCU_RX_FILTER_BROADCAST_LSB) & MAC_PCU_RX_FILTER_BROADCAST_MASK)
+#define MAC_PCU_RX_FILTER_MULTICAST_MSB          1
+#define MAC_PCU_RX_FILTER_MULTICAST_LSB          1
+#define MAC_PCU_RX_FILTER_MULTICAST_MASK         0x00000002
+#define MAC_PCU_RX_FILTER_MULTICAST_GET(x)       (((x) & MAC_PCU_RX_FILTER_MULTICAST_MASK) >> MAC_PCU_RX_FILTER_MULTICAST_LSB)
+#define MAC_PCU_RX_FILTER_MULTICAST_SET(x)       (((x) << MAC_PCU_RX_FILTER_MULTICAST_LSB) & MAC_PCU_RX_FILTER_MULTICAST_MASK)
+#define MAC_PCU_RX_FILTER_UNICAST_MSB            0
+#define MAC_PCU_RX_FILTER_UNICAST_LSB            0
+#define MAC_PCU_RX_FILTER_UNICAST_MASK           0x00000001
+#define MAC_PCU_RX_FILTER_UNICAST_GET(x)         (((x) & MAC_PCU_RX_FILTER_UNICAST_MASK) >> MAC_PCU_RX_FILTER_UNICAST_LSB)
+#define MAC_PCU_RX_FILTER_UNICAST_SET(x)         (((x) << MAC_PCU_RX_FILTER_UNICAST_LSB) & MAC_PCU_RX_FILTER_UNICAST_MASK)
+
+#define MAC_PCU_MCAST_FILTER_L32_ADDRESS         0x00008028
+#define MAC_PCU_MCAST_FILTER_L32_OFFSET          0x00000028
+#define MAC_PCU_MCAST_FILTER_L32_VALUE_MSB       31
+#define MAC_PCU_MCAST_FILTER_L32_VALUE_LSB       0
+#define MAC_PCU_MCAST_FILTER_L32_VALUE_MASK      0xffffffff
+#define MAC_PCU_MCAST_FILTER_L32_VALUE_GET(x)    (((x) & MAC_PCU_MCAST_FILTER_L32_VALUE_MASK) >> MAC_PCU_MCAST_FILTER_L32_VALUE_LSB)
+#define MAC_PCU_MCAST_FILTER_L32_VALUE_SET(x)    (((x) << MAC_PCU_MCAST_FILTER_L32_VALUE_LSB) & MAC_PCU_MCAST_FILTER_L32_VALUE_MASK)
+
+#define MAC_PCU_MCAST_FILTER_U32_ADDRESS         0x0000802c
+#define MAC_PCU_MCAST_FILTER_U32_OFFSET          0x0000002c
+#define MAC_PCU_MCAST_FILTER_U32_VALUE_MSB       31
+#define MAC_PCU_MCAST_FILTER_U32_VALUE_LSB       0
+#define MAC_PCU_MCAST_FILTER_U32_VALUE_MASK      0xffffffff
+#define MAC_PCU_MCAST_FILTER_U32_VALUE_GET(x)    (((x) & MAC_PCU_MCAST_FILTER_U32_VALUE_MASK) >> MAC_PCU_MCAST_FILTER_U32_VALUE_LSB)
+#define MAC_PCU_MCAST_FILTER_U32_VALUE_SET(x)    (((x) << MAC_PCU_MCAST_FILTER_U32_VALUE_LSB) & MAC_PCU_MCAST_FILTER_U32_VALUE_MASK)
+
+#define MAC_PCU_DIAG_SW_ADDRESS                  0x00008030
+#define MAC_PCU_DIAG_SW_OFFSET                   0x00000030
+#define MAC_PCU_DIAG_SW_DEBUG_MODE_MSB           31
+#define MAC_PCU_DIAG_SW_DEBUG_MODE_LSB           30
+#define MAC_PCU_DIAG_SW_DEBUG_MODE_MASK          0xc0000000
+#define MAC_PCU_DIAG_SW_DEBUG_MODE_GET(x)        (((x) & MAC_PCU_DIAG_SW_DEBUG_MODE_MASK) >> MAC_PCU_DIAG_SW_DEBUG_MODE_LSB)
+#define MAC_PCU_DIAG_SW_DEBUG_MODE_SET(x)        (((x) << MAC_PCU_DIAG_SW_DEBUG_MODE_LSB) & MAC_PCU_DIAG_SW_DEBUG_MODE_MASK)
+#define MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_MSB     29
+#define MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_LSB     29
+#define MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_MASK    0x20000000
+#define MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_GET(x)  (((x) & MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_MASK) >> MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_LSB)
+#define MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_SET(x)  (((x) << MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_LSB) & MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_MASK)
+#define MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_MSB     28
+#define MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_LSB     28
+#define MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_MASK    0x10000000
+#define MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_GET(x)  (((x) & MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_MASK) >> MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_LSB)
+#define MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_SET(x)  (((x) << MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_LSB) & MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_MASK)
+#define MAC_PCU_DIAG_SW_OBS_SEL_2_MSB            27
+#define MAC_PCU_DIAG_SW_OBS_SEL_2_LSB            27
+#define MAC_PCU_DIAG_SW_OBS_SEL_2_MASK           0x08000000
+#define MAC_PCU_DIAG_SW_OBS_SEL_2_GET(x)         (((x) & MAC_PCU_DIAG_SW_OBS_SEL_2_MASK) >> MAC_PCU_DIAG_SW_OBS_SEL_2_LSB)
+#define MAC_PCU_DIAG_SW_OBS_SEL_2_SET(x)         (((x) << MAC_PCU_DIAG_SW_OBS_SEL_2_LSB) & MAC_PCU_DIAG_SW_OBS_SEL_2_MASK)
+#define MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_MSB   26
+#define MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_LSB   26
+#define MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_MASK  0x04000000
+#define MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_GET(x) (((x) & MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_MASK) >> MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_LSB)
+#define MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_SET(x) (((x) << MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_LSB) & MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_MASK)
+#define MAC_PCU_DIAG_SW_FORCE_RX_ABORT_MSB       25
+#define MAC_PCU_DIAG_SW_FORCE_RX_ABORT_LSB       25
+#define MAC_PCU_DIAG_SW_FORCE_RX_ABORT_MASK      0x02000000
+#define MAC_PCU_DIAG_SW_FORCE_RX_ABORT_GET(x)    (((x) & MAC_PCU_DIAG_SW_FORCE_RX_ABORT_MASK) >> MAC_PCU_DIAG_SW_FORCE_RX_ABORT_LSB)
+#define MAC_PCU_DIAG_SW_FORCE_RX_ABORT_SET(x)    (((x) << MAC_PCU_DIAG_SW_FORCE_RX_ABORT_LSB) & MAC_PCU_DIAG_SW_FORCE_RX_ABORT_MASK)
+#define MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_MSB 24
+#define MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_LSB 24
+#define MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_MASK 0x01000000
+#define MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_GET(x) (((x) & MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_MASK) >> MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_LSB)
+#define MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_SET(x) (((x) << MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_LSB) & MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_MASK)
+#define MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_MSB 23
+#define MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_LSB 23
+#define MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_MASK 0x00800000
+#define MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_GET(x) (((x) & MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_MASK) >> MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_LSB)
+#define MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_SET(x) (((x) << MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_LSB) & MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_MASK)
+#define MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_MSB       22
+#define MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_LSB       22
+#define MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_MASK      0x00400000
+#define MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_GET(x)    (((x) & MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_MASK) >> MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_LSB)
+#define MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_SET(x)    (((x) << MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_LSB) & MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_MASK)
+#define MAC_PCU_DIAG_SW_IGNORE_NAV_MSB           21
+#define MAC_PCU_DIAG_SW_IGNORE_NAV_LSB           21
+#define MAC_PCU_DIAG_SW_IGNORE_NAV_MASK          0x00200000
+#define MAC_PCU_DIAG_SW_IGNORE_NAV_GET(x)        (((x) & MAC_PCU_DIAG_SW_IGNORE_NAV_MASK) >> MAC_PCU_DIAG_SW_IGNORE_NAV_LSB)
+#define MAC_PCU_DIAG_SW_IGNORE_NAV_SET(x)        (((x) << MAC_PCU_DIAG_SW_IGNORE_NAV_LSB) & MAC_PCU_DIAG_SW_IGNORE_NAV_MASK)
+#define MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_MSB        20
+#define MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_LSB        20
+#define MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_MASK       0x00100000
+#define MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_GET(x)     (((x) & MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_MASK) >> MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_LSB)
+#define MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_SET(x)     (((x) << MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_LSB) & MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_MASK)
+#define MAC_PCU_DIAG_SW_OBS_SEL_1_0_MSB          19
+#define MAC_PCU_DIAG_SW_OBS_SEL_1_0_LSB          18
+#define MAC_PCU_DIAG_SW_OBS_SEL_1_0_MASK         0x000c0000
+#define MAC_PCU_DIAG_SW_OBS_SEL_1_0_GET(x)       (((x) & MAC_PCU_DIAG_SW_OBS_SEL_1_0_MASK) >> MAC_PCU_DIAG_SW_OBS_SEL_1_0_LSB)
+#define MAC_PCU_DIAG_SW_OBS_SEL_1_0_SET(x)       (((x) << MAC_PCU_DIAG_SW_OBS_SEL_1_0_LSB) & MAC_PCU_DIAG_SW_OBS_SEL_1_0_MASK)
+#define MAC_PCU_DIAG_SW_ACCEPT_NON_V0_MSB        17
+#define MAC_PCU_DIAG_SW_ACCEPT_NON_V0_LSB        17
+#define MAC_PCU_DIAG_SW_ACCEPT_NON_V0_MASK       0x00020000
+#define MAC_PCU_DIAG_SW_ACCEPT_NON_V0_GET(x)     (((x) & MAC_PCU_DIAG_SW_ACCEPT_NON_V0_MASK) >> MAC_PCU_DIAG_SW_ACCEPT_NON_V0_LSB)
+#define MAC_PCU_DIAG_SW_ACCEPT_NON_V0_SET(x)     (((x) << MAC_PCU_DIAG_SW_ACCEPT_NON_V0_LSB) & MAC_PCU_DIAG_SW_ACCEPT_NON_V0_MASK)
+#define MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_MSB       8
+#define MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_LSB       8
+#define MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_MASK      0x00000100
+#define MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_GET(x)    (((x) & MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_MASK) >> MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_LSB)
+#define MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_SET(x)    (((x) << MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_LSB) & MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_MASK)
+#define MAC_PCU_DIAG_SW_CORRUPT_FCS_MSB          7
+#define MAC_PCU_DIAG_SW_CORRUPT_FCS_LSB          7
+#define MAC_PCU_DIAG_SW_CORRUPT_FCS_MASK         0x00000080
+#define MAC_PCU_DIAG_SW_CORRUPT_FCS_GET(x)       (((x) & MAC_PCU_DIAG_SW_CORRUPT_FCS_MASK) >> MAC_PCU_DIAG_SW_CORRUPT_FCS_LSB)
+#define MAC_PCU_DIAG_SW_CORRUPT_FCS_SET(x)       (((x) << MAC_PCU_DIAG_SW_CORRUPT_FCS_LSB) & MAC_PCU_DIAG_SW_CORRUPT_FCS_MASK)
+#define MAC_PCU_DIAG_SW_LOOP_BACK_MSB            6
+#define MAC_PCU_DIAG_SW_LOOP_BACK_LSB            6
+#define MAC_PCU_DIAG_SW_LOOP_BACK_MASK           0x00000040
+#define MAC_PCU_DIAG_SW_LOOP_BACK_GET(x)         (((x) & MAC_PCU_DIAG_SW_LOOP_BACK_MASK) >> MAC_PCU_DIAG_SW_LOOP_BACK_LSB)
+#define MAC_PCU_DIAG_SW_LOOP_BACK_SET(x)         (((x) << MAC_PCU_DIAG_SW_LOOP_BACK_LSB) & MAC_PCU_DIAG_SW_LOOP_BACK_MASK)
+#define MAC_PCU_DIAG_SW_HALT_RX_MSB              5
+#define MAC_PCU_DIAG_SW_HALT_RX_LSB              5
+#define MAC_PCU_DIAG_SW_HALT_RX_MASK             0x00000020
+#define MAC_PCU_DIAG_SW_HALT_RX_GET(x)           (((x) & MAC_PCU_DIAG_SW_HALT_RX_MASK) >> MAC_PCU_DIAG_SW_HALT_RX_LSB)
+#define MAC_PCU_DIAG_SW_HALT_RX_SET(x)           (((x) << MAC_PCU_DIAG_SW_HALT_RX_LSB) & MAC_PCU_DIAG_SW_HALT_RX_MASK)
+#define MAC_PCU_DIAG_SW_NO_DECRYPT_MSB           4
+#define MAC_PCU_DIAG_SW_NO_DECRYPT_LSB           4
+#define MAC_PCU_DIAG_SW_NO_DECRYPT_MASK          0x00000010
+#define MAC_PCU_DIAG_SW_NO_DECRYPT_GET(x)        (((x) & MAC_PCU_DIAG_SW_NO_DECRYPT_MASK) >> MAC_PCU_DIAG_SW_NO_DECRYPT_LSB)
+#define MAC_PCU_DIAG_SW_NO_DECRYPT_SET(x)        (((x) << MAC_PCU_DIAG_SW_NO_DECRYPT_LSB) & MAC_PCU_DIAG_SW_NO_DECRYPT_MASK)
+#define MAC_PCU_DIAG_SW_NO_ENCRYPT_MSB           3
+#define MAC_PCU_DIAG_SW_NO_ENCRYPT_LSB           3
+#define MAC_PCU_DIAG_SW_NO_ENCRYPT_MASK          0x00000008
+#define MAC_PCU_DIAG_SW_NO_ENCRYPT_GET(x)        (((x) & MAC_PCU_DIAG_SW_NO_ENCRYPT_MASK) >> MAC_PCU_DIAG_SW_NO_ENCRYPT_LSB)
+#define MAC_PCU_DIAG_SW_NO_ENCRYPT_SET(x)        (((x) << MAC_PCU_DIAG_SW_NO_ENCRYPT_LSB) & MAC_PCU_DIAG_SW_NO_ENCRYPT_MASK)
+#define MAC_PCU_DIAG_SW_NO_CTS_MSB               2
+#define MAC_PCU_DIAG_SW_NO_CTS_LSB               2
+#define MAC_PCU_DIAG_SW_NO_CTS_MASK              0x00000004
+#define MAC_PCU_DIAG_SW_NO_CTS_GET(x)            (((x) & MAC_PCU_DIAG_SW_NO_CTS_MASK) >> MAC_PCU_DIAG_SW_NO_CTS_LSB)
+#define MAC_PCU_DIAG_SW_NO_CTS_SET(x)            (((x) << MAC_PCU_DIAG_SW_NO_CTS_LSB) & MAC_PCU_DIAG_SW_NO_CTS_MASK)
+#define MAC_PCU_DIAG_SW_NO_ACK_MSB               1
+#define MAC_PCU_DIAG_SW_NO_ACK_LSB               1
+#define MAC_PCU_DIAG_SW_NO_ACK_MASK              0x00000002
+#define MAC_PCU_DIAG_SW_NO_ACK_GET(x)            (((x) & MAC_PCU_DIAG_SW_NO_ACK_MASK) >> MAC_PCU_DIAG_SW_NO_ACK_LSB)
+#define MAC_PCU_DIAG_SW_NO_ACK_SET(x)            (((x) << MAC_PCU_DIAG_SW_NO_ACK_LSB) & MAC_PCU_DIAG_SW_NO_ACK_MASK)
+#define MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_MSB   0
+#define MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_LSB   0
+#define MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_MASK  0x00000001
+#define MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_GET(x) (((x) & MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_MASK) >> MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_LSB)
+#define MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_SET(x) (((x) << MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_LSB) & MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_MASK)
+
+#define MAC_PCU_TST_ADDAC_ADDRESS                0x00008034
+#define MAC_PCU_TST_ADDAC_OFFSET                 0x00000034
+#define MAC_PCU_TST_ADDAC_TEST_ARM_MSB           20
+#define MAC_PCU_TST_ADDAC_TEST_ARM_LSB           20
+#define MAC_PCU_TST_ADDAC_TEST_ARM_MASK          0x00100000
+#define MAC_PCU_TST_ADDAC_TEST_ARM_GET(x)        (((x) & MAC_PCU_TST_ADDAC_TEST_ARM_MASK) >> MAC_PCU_TST_ADDAC_TEST_ARM_LSB)
+#define MAC_PCU_TST_ADDAC_TEST_ARM_SET(x)        (((x) << MAC_PCU_TST_ADDAC_TEST_ARM_LSB) & MAC_PCU_TST_ADDAC_TEST_ARM_MASK)
+#define MAC_PCU_TST_ADDAC_TEST_CAPTURE_MSB       19
+#define MAC_PCU_TST_ADDAC_TEST_CAPTURE_LSB       19
+#define MAC_PCU_TST_ADDAC_TEST_CAPTURE_MASK      0x00080000
+#define MAC_PCU_TST_ADDAC_TEST_CAPTURE_GET(x)    (((x) & MAC_PCU_TST_ADDAC_TEST_CAPTURE_MASK) >> MAC_PCU_TST_ADDAC_TEST_CAPTURE_LSB)
+#define MAC_PCU_TST_ADDAC_TEST_CAPTURE_SET(x)    (((x) << MAC_PCU_TST_ADDAC_TEST_CAPTURE_LSB) & MAC_PCU_TST_ADDAC_TEST_CAPTURE_MASK)
+#define MAC_PCU_TST_ADDAC_CONT_TEST_MSB          18
+#define MAC_PCU_TST_ADDAC_CONT_TEST_LSB          18
+#define MAC_PCU_TST_ADDAC_CONT_TEST_MASK         0x00040000
+#define MAC_PCU_TST_ADDAC_CONT_TEST_GET(x)       (((x) & MAC_PCU_TST_ADDAC_CONT_TEST_MASK) >> MAC_PCU_TST_ADDAC_CONT_TEST_LSB)
+#define MAC_PCU_TST_ADDAC_CONT_TEST_SET(x)       (((x) << MAC_PCU_TST_ADDAC_CONT_TEST_LSB) & MAC_PCU_TST_ADDAC_CONT_TEST_MASK)
+#define MAC_PCU_TST_ADDAC_TRIG_POLARITY_MSB      17
+#define MAC_PCU_TST_ADDAC_TRIG_POLARITY_LSB      17
+#define MAC_PCU_TST_ADDAC_TRIG_POLARITY_MASK     0x00020000
+#define MAC_PCU_TST_ADDAC_TRIG_POLARITY_GET(x)   (((x) & MAC_PCU_TST_ADDAC_TRIG_POLARITY_MASK) >> MAC_PCU_TST_ADDAC_TRIG_POLARITY_LSB)
+#define MAC_PCU_TST_ADDAC_TRIG_POLARITY_SET(x)   (((x) << MAC_PCU_TST_ADDAC_TRIG_POLARITY_LSB) & MAC_PCU_TST_ADDAC_TRIG_POLARITY_MASK)
+#define MAC_PCU_TST_ADDAC_TRIG_SEL_MSB           16
+#define MAC_PCU_TST_ADDAC_TRIG_SEL_LSB           16
+#define MAC_PCU_TST_ADDAC_TRIG_SEL_MASK          0x00010000
+#define MAC_PCU_TST_ADDAC_TRIG_SEL_GET(x)        (((x) & MAC_PCU_TST_ADDAC_TRIG_SEL_MASK) >> MAC_PCU_TST_ADDAC_TRIG_SEL_LSB)
+#define MAC_PCU_TST_ADDAC_TRIG_SEL_SET(x)        (((x) << MAC_PCU_TST_ADDAC_TRIG_SEL_LSB) & MAC_PCU_TST_ADDAC_TRIG_SEL_MASK)
+#define MAC_PCU_TST_ADDAC_UPPER_8B_MSB           14
+#define MAC_PCU_TST_ADDAC_UPPER_8B_LSB           14
+#define MAC_PCU_TST_ADDAC_UPPER_8B_MASK          0x00004000
+#define MAC_PCU_TST_ADDAC_UPPER_8B_GET(x)        (((x) & MAC_PCU_TST_ADDAC_UPPER_8B_MASK) >> MAC_PCU_TST_ADDAC_UPPER_8B_LSB)
+#define MAC_PCU_TST_ADDAC_UPPER_8B_SET(x)        (((x) << MAC_PCU_TST_ADDAC_UPPER_8B_LSB) & MAC_PCU_TST_ADDAC_UPPER_8B_MASK)
+#define MAC_PCU_TST_ADDAC_LOOP_LEN_MSB           13
+#define MAC_PCU_TST_ADDAC_LOOP_LEN_LSB           3
+#define MAC_PCU_TST_ADDAC_LOOP_LEN_MASK          0x00003ff8
+#define MAC_PCU_TST_ADDAC_LOOP_LEN_GET(x)        (((x) & MAC_PCU_TST_ADDAC_LOOP_LEN_MASK) >> MAC_PCU_TST_ADDAC_LOOP_LEN_LSB)
+#define MAC_PCU_TST_ADDAC_LOOP_LEN_SET(x)        (((x) << MAC_PCU_TST_ADDAC_LOOP_LEN_LSB) & MAC_PCU_TST_ADDAC_LOOP_LEN_MASK)
+#define MAC_PCU_TST_ADDAC_LOOP_MSB               2
+#define MAC_PCU_TST_ADDAC_LOOP_LSB               2
+#define MAC_PCU_TST_ADDAC_LOOP_MASK              0x00000004
+#define MAC_PCU_TST_ADDAC_LOOP_GET(x)            (((x) & MAC_PCU_TST_ADDAC_LOOP_MASK) >> MAC_PCU_TST_ADDAC_LOOP_LSB)
+#define MAC_PCU_TST_ADDAC_LOOP_SET(x)            (((x) << MAC_PCU_TST_ADDAC_LOOP_LSB) & MAC_PCU_TST_ADDAC_LOOP_MASK)
+#define MAC_PCU_TST_ADDAC_TESTMODE_MSB           1
+#define MAC_PCU_TST_ADDAC_TESTMODE_LSB           1
+#define MAC_PCU_TST_ADDAC_TESTMODE_MASK          0x00000002
+#define MAC_PCU_TST_ADDAC_TESTMODE_GET(x)        (((x) & MAC_PCU_TST_ADDAC_TESTMODE_MASK) >> MAC_PCU_TST_ADDAC_TESTMODE_LSB)
+#define MAC_PCU_TST_ADDAC_TESTMODE_SET(x)        (((x) << MAC_PCU_TST_ADDAC_TESTMODE_LSB) & MAC_PCU_TST_ADDAC_TESTMODE_MASK)
+#define MAC_PCU_TST_ADDAC_CONT_TX_MSB            0
+#define MAC_PCU_TST_ADDAC_CONT_TX_LSB            0
+#define MAC_PCU_TST_ADDAC_CONT_TX_MASK           0x00000001
+#define MAC_PCU_TST_ADDAC_CONT_TX_GET(x)         (((x) & MAC_PCU_TST_ADDAC_CONT_TX_MASK) >> MAC_PCU_TST_ADDAC_CONT_TX_LSB)
+#define MAC_PCU_TST_ADDAC_CONT_TX_SET(x)         (((x) << MAC_PCU_TST_ADDAC_CONT_TX_LSB) & MAC_PCU_TST_ADDAC_CONT_TX_MASK)
+
+#define MAC_PCU_DEF_ANTENNA_ADDRESS              0x00008038
+#define MAC_PCU_DEF_ANTENNA_OFFSET               0x00000038
+#define MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_MSB 28
+#define MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_LSB 28
+#define MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_MASK 0x10000000
+#define MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_GET(x) (((x) & MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_MASK) >> MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_LSB)
+#define MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_SET(x) (((x) << MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_LSB) & MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_MASK)
+#define MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_MSB   24
+#define MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_LSB   24
+#define MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_MASK  0x01000000
+#define MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_GET(x) (((x) & MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_MASK) >> MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_LSB)
+#define MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_SET(x) (((x) << MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_LSB) & MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_MASK)
+#define MAC_PCU_DEF_ANTENNA_VALUE_MSB            23
+#define MAC_PCU_DEF_ANTENNA_VALUE_LSB            0
+#define MAC_PCU_DEF_ANTENNA_VALUE_MASK           0x00ffffff
+#define MAC_PCU_DEF_ANTENNA_VALUE_GET(x)         (((x) & MAC_PCU_DEF_ANTENNA_VALUE_MASK) >> MAC_PCU_DEF_ANTENNA_VALUE_LSB)
+#define MAC_PCU_DEF_ANTENNA_VALUE_SET(x)         (((x) << MAC_PCU_DEF_ANTENNA_VALUE_LSB) & MAC_PCU_DEF_ANTENNA_VALUE_MASK)
+
+#define MAC_PCU_AES_MUTE_MASK_0_ADDRESS          0x0000803c
+#define MAC_PCU_AES_MUTE_MASK_0_OFFSET           0x0000003c
+#define MAC_PCU_AES_MUTE_MASK_0_QOS_MSB          31
+#define MAC_PCU_AES_MUTE_MASK_0_QOS_LSB          16
+#define MAC_PCU_AES_MUTE_MASK_0_QOS_MASK         0xffff0000
+#define MAC_PCU_AES_MUTE_MASK_0_QOS_GET(x)       (((x) & MAC_PCU_AES_MUTE_MASK_0_QOS_MASK) >> MAC_PCU_AES_MUTE_MASK_0_QOS_LSB)
+#define MAC_PCU_AES_MUTE_MASK_0_QOS_SET(x)       (((x) << MAC_PCU_AES_MUTE_MASK_0_QOS_LSB) & MAC_PCU_AES_MUTE_MASK_0_QOS_MASK)
+#define MAC_PCU_AES_MUTE_MASK_0_FC_MSB           15
+#define MAC_PCU_AES_MUTE_MASK_0_FC_LSB           0
+#define MAC_PCU_AES_MUTE_MASK_0_FC_MASK          0x0000ffff
+#define MAC_PCU_AES_MUTE_MASK_0_FC_GET(x)        (((x) & MAC_PCU_AES_MUTE_MASK_0_FC_MASK) >> MAC_PCU_AES_MUTE_MASK_0_FC_LSB)
+#define MAC_PCU_AES_MUTE_MASK_0_FC_SET(x)        (((x) << MAC_PCU_AES_MUTE_MASK_0_FC_LSB) & MAC_PCU_AES_MUTE_MASK_0_FC_MASK)
+
+#define MAC_PCU_AES_MUTE_MASK_1_ADDRESS          0x00008040
+#define MAC_PCU_AES_MUTE_MASK_1_OFFSET           0x00000040
+#define MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_MSB      31
+#define MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_LSB      16
+#define MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_MASK     0xffff0000
+#define MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_GET(x)   (((x) & MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_MASK) >> MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_LSB)
+#define MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_SET(x)   (((x) << MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_LSB) & MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_MASK)
+#define MAC_PCU_AES_MUTE_MASK_1_SEQ_MSB          15
+#define MAC_PCU_AES_MUTE_MASK_1_SEQ_LSB          0
+#define MAC_PCU_AES_MUTE_MASK_1_SEQ_MASK         0x0000ffff
+#define MAC_PCU_AES_MUTE_MASK_1_SEQ_GET(x)       (((x) & MAC_PCU_AES_MUTE_MASK_1_SEQ_MASK) >> MAC_PCU_AES_MUTE_MASK_1_SEQ_LSB)
+#define MAC_PCU_AES_MUTE_MASK_1_SEQ_SET(x)       (((x) << MAC_PCU_AES_MUTE_MASK_1_SEQ_LSB) & MAC_PCU_AES_MUTE_MASK_1_SEQ_MASK)
+
+#define MAC_PCU_GATED_CLKS_ADDRESS               0x00008044
+#define MAC_PCU_GATED_CLKS_OFFSET                0x00000044
+#define MAC_PCU_GATED_CLKS_GATED_REG_MSB         3
+#define MAC_PCU_GATED_CLKS_GATED_REG_LSB         3
+#define MAC_PCU_GATED_CLKS_GATED_REG_MASK        0x00000008
+#define MAC_PCU_GATED_CLKS_GATED_REG_GET(x)      (((x) & MAC_PCU_GATED_CLKS_GATED_REG_MASK) >> MAC_PCU_GATED_CLKS_GATED_REG_LSB)
+#define MAC_PCU_GATED_CLKS_GATED_REG_SET(x)      (((x) << MAC_PCU_GATED_CLKS_GATED_REG_LSB) & MAC_PCU_GATED_CLKS_GATED_REG_MASK)
+#define MAC_PCU_GATED_CLKS_GATED_RX_MSB          2
+#define MAC_PCU_GATED_CLKS_GATED_RX_LSB          2
+#define MAC_PCU_GATED_CLKS_GATED_RX_MASK         0x00000004
+#define MAC_PCU_GATED_CLKS_GATED_RX_GET(x)       (((x) & MAC_PCU_GATED_CLKS_GATED_RX_MASK) >> MAC_PCU_GATED_CLKS_GATED_RX_LSB)
+#define MAC_PCU_GATED_CLKS_GATED_RX_SET(x)       (((x) << MAC_PCU_GATED_CLKS_GATED_RX_LSB) & MAC_PCU_GATED_CLKS_GATED_RX_MASK)
+#define MAC_PCU_GATED_CLKS_GATED_TX_MSB          1
+#define MAC_PCU_GATED_CLKS_GATED_TX_LSB          1
+#define MAC_PCU_GATED_CLKS_GATED_TX_MASK         0x00000002
+#define MAC_PCU_GATED_CLKS_GATED_TX_GET(x)       (((x) & MAC_PCU_GATED_CLKS_GATED_TX_MASK) >> MAC_PCU_GATED_CLKS_GATED_TX_LSB)
+#define MAC_PCU_GATED_CLKS_GATED_TX_SET(x)       (((x) << MAC_PCU_GATED_CLKS_GATED_TX_LSB) & MAC_PCU_GATED_CLKS_GATED_TX_MASK)
+
+#define MAC_PCU_OBS_BUS_2_ADDRESS                0x00008048
+#define MAC_PCU_OBS_BUS_2_OFFSET                 0x00000048
+#define MAC_PCU_OBS_BUS_2_VALUE_MSB              17
+#define MAC_PCU_OBS_BUS_2_VALUE_LSB              0
+#define MAC_PCU_OBS_BUS_2_VALUE_MASK             0x0003ffff
+#define MAC_PCU_OBS_BUS_2_VALUE_GET(x)           (((x) & MAC_PCU_OBS_BUS_2_VALUE_MASK) >> MAC_PCU_OBS_BUS_2_VALUE_LSB)
+#define MAC_PCU_OBS_BUS_2_VALUE_SET(x)           (((x) << MAC_PCU_OBS_BUS_2_VALUE_LSB) & MAC_PCU_OBS_BUS_2_VALUE_MASK)
+
+#define MAC_PCU_OBS_BUS_1_ADDRESS                0x0000804c
+#define MAC_PCU_OBS_BUS_1_OFFSET                 0x0000004c
+#define MAC_PCU_OBS_BUS_1_TX_STATE_MSB           30
+#define MAC_PCU_OBS_BUS_1_TX_STATE_LSB           25
+#define MAC_PCU_OBS_BUS_1_TX_STATE_MASK          0x7e000000
+#define MAC_PCU_OBS_BUS_1_TX_STATE_GET(x)        (((x) & MAC_PCU_OBS_BUS_1_TX_STATE_MASK) >> MAC_PCU_OBS_BUS_1_TX_STATE_LSB)
+#define MAC_PCU_OBS_BUS_1_TX_STATE_SET(x)        (((x) << MAC_PCU_OBS_BUS_1_TX_STATE_LSB) & MAC_PCU_OBS_BUS_1_TX_STATE_MASK)
+#define MAC_PCU_OBS_BUS_1_RX_STATE_MSB           24
+#define MAC_PCU_OBS_BUS_1_RX_STATE_LSB           20
+#define MAC_PCU_OBS_BUS_1_RX_STATE_MASK          0x01f00000
+#define MAC_PCU_OBS_BUS_1_RX_STATE_GET(x)        (((x) & MAC_PCU_OBS_BUS_1_RX_STATE_MASK) >> MAC_PCU_OBS_BUS_1_RX_STATE_LSB)
+#define MAC_PCU_OBS_BUS_1_RX_STATE_SET(x)        (((x) << MAC_PCU_OBS_BUS_1_RX_STATE_LSB) & MAC_PCU_OBS_BUS_1_RX_STATE_MASK)
+#define MAC_PCU_OBS_BUS_1_WEP_STATE_MSB          17
+#define MAC_PCU_OBS_BUS_1_WEP_STATE_LSB          12
+#define MAC_PCU_OBS_BUS_1_WEP_STATE_MASK         0x0003f000
+#define MAC_PCU_OBS_BUS_1_WEP_STATE_GET(x)       (((x) & MAC_PCU_OBS_BUS_1_WEP_STATE_MASK) >> MAC_PCU_OBS_BUS_1_WEP_STATE_LSB)
+#define MAC_PCU_OBS_BUS_1_WEP_STATE_SET(x)       (((x) << MAC_PCU_OBS_BUS_1_WEP_STATE_LSB) & MAC_PCU_OBS_BUS_1_WEP_STATE_MASK)
+#define MAC_PCU_OBS_BUS_1_RX_CLEAR_MSB           11
+#define MAC_PCU_OBS_BUS_1_RX_CLEAR_LSB           11
+#define MAC_PCU_OBS_BUS_1_RX_CLEAR_MASK          0x00000800
+#define MAC_PCU_OBS_BUS_1_RX_CLEAR_GET(x)        (((x) & MAC_PCU_OBS_BUS_1_RX_CLEAR_MASK) >> MAC_PCU_OBS_BUS_1_RX_CLEAR_LSB)
+#define MAC_PCU_OBS_BUS_1_RX_CLEAR_SET(x)        (((x) << MAC_PCU_OBS_BUS_1_RX_CLEAR_LSB) & MAC_PCU_OBS_BUS_1_RX_CLEAR_MASK)
+#define MAC_PCU_OBS_BUS_1_RX_FRAME_MSB           10
+#define MAC_PCU_OBS_BUS_1_RX_FRAME_LSB           10
+#define MAC_PCU_OBS_BUS_1_RX_FRAME_MASK          0x00000400
+#define MAC_PCU_OBS_BUS_1_RX_FRAME_GET(x)        (((x) & MAC_PCU_OBS_BUS_1_RX_FRAME_MASK) >> MAC_PCU_OBS_BUS_1_RX_FRAME_LSB)
+#define MAC_PCU_OBS_BUS_1_RX_FRAME_SET(x)        (((x) << MAC_PCU_OBS_BUS_1_RX_FRAME_LSB) & MAC_PCU_OBS_BUS_1_RX_FRAME_MASK)
+#define MAC_PCU_OBS_BUS_1_TX_FRAME_MSB           9
+#define MAC_PCU_OBS_BUS_1_TX_FRAME_LSB           9
+#define MAC_PCU_OBS_BUS_1_TX_FRAME_MASK          0x00000200
+#define MAC_PCU_OBS_BUS_1_TX_FRAME_GET(x)        (((x) & MAC_PCU_OBS_BUS_1_TX_FRAME_MASK) >> MAC_PCU_OBS_BUS_1_TX_FRAME_LSB)
+#define MAC_PCU_OBS_BUS_1_TX_FRAME_SET(x)        (((x) << MAC_PCU_OBS_BUS_1_TX_FRAME_LSB) & MAC_PCU_OBS_BUS_1_TX_FRAME_MASK)
+#define MAC_PCU_OBS_BUS_1_TX_HOLD_MSB            8
+#define MAC_PCU_OBS_BUS_1_TX_HOLD_LSB            8
+#define MAC_PCU_OBS_BUS_1_TX_HOLD_MASK           0x00000100
+#define MAC_PCU_OBS_BUS_1_TX_HOLD_GET(x)         (((x) & MAC_PCU_OBS_BUS_1_TX_HOLD_MASK) >> MAC_PCU_OBS_BUS_1_TX_HOLD_LSB)
+#define MAC_PCU_OBS_BUS_1_TX_HOLD_SET(x)         (((x) << MAC_PCU_OBS_BUS_1_TX_HOLD_LSB) & MAC_PCU_OBS_BUS_1_TX_HOLD_MASK)
+#define MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_MSB   7
+#define MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_LSB   7
+#define MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_MASK  0x00000080
+#define MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_GET(x) (((x) & MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_MASK) >> MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_LSB)
+#define MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_SET(x) (((x) << MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_LSB) & MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_MASK)
+#define MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_MSB      6
+#define MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_LSB      6
+#define MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_MASK     0x00000040
+#define MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_GET(x)   (((x) & MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_MASK) >> MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_LSB)
+#define MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_SET(x)   (((x) << MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_LSB) & MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_MASK)
+#define MAC_PCU_OBS_BUS_1_TX_HCF_MSB             5
+#define MAC_PCU_OBS_BUS_1_TX_HCF_LSB             5
+#define MAC_PCU_OBS_BUS_1_TX_HCF_MASK            0x00000020
+#define MAC_PCU_OBS_BUS_1_TX_HCF_GET(x)          (((x) & MAC_PCU_OBS_BUS_1_TX_HCF_MASK) >> MAC_PCU_OBS_BUS_1_TX_HCF_LSB)
+#define MAC_PCU_OBS_BUS_1_TX_HCF_SET(x)          (((x) << MAC_PCU_OBS_BUS_1_TX_HCF_LSB) & MAC_PCU_OBS_BUS_1_TX_HCF_MASK)
+#define MAC_PCU_OBS_BUS_1_FILTER_PASS_MSB        4
+#define MAC_PCU_OBS_BUS_1_FILTER_PASS_LSB        4
+#define MAC_PCU_OBS_BUS_1_FILTER_PASS_MASK       0x00000010
+#define MAC_PCU_OBS_BUS_1_FILTER_PASS_GET(x)     (((x) & MAC_PCU_OBS_BUS_1_FILTER_PASS_MASK) >> MAC_PCU_OBS_BUS_1_FILTER_PASS_LSB)
+#define MAC_PCU_OBS_BUS_1_FILTER_PASS_SET(x)     (((x) << MAC_PCU_OBS_BUS_1_FILTER_PASS_LSB) & MAC_PCU_OBS_BUS_1_FILTER_PASS_MASK)
+#define MAC_PCU_OBS_BUS_1_RX_MY_BEACON_MSB       3
+#define MAC_PCU_OBS_BUS_1_RX_MY_BEACON_LSB       3
+#define MAC_PCU_OBS_BUS_1_RX_MY_BEACON_MASK      0x00000008
+#define MAC_PCU_OBS_BUS_1_RX_MY_BEACON_GET(x)    (((x) & MAC_PCU_OBS_BUS_1_RX_MY_BEACON_MASK) >> MAC_PCU_OBS_BUS_1_RX_MY_BEACON_LSB)
+#define MAC_PCU_OBS_BUS_1_RX_MY_BEACON_SET(x)    (((x) << MAC_PCU_OBS_BUS_1_RX_MY_BEACON_LSB) & MAC_PCU_OBS_BUS_1_RX_MY_BEACON_MASK)
+#define MAC_PCU_OBS_BUS_1_RX_WEP_MSB             2
+#define MAC_PCU_OBS_BUS_1_RX_WEP_LSB             2
+#define MAC_PCU_OBS_BUS_1_RX_WEP_MASK            0x00000004
+#define MAC_PCU_OBS_BUS_1_RX_WEP_GET(x)          (((x) & MAC_PCU_OBS_BUS_1_RX_WEP_MASK) >> MAC_PCU_OBS_BUS_1_RX_WEP_LSB)
+#define MAC_PCU_OBS_BUS_1_RX_WEP_SET(x)          (((x) << MAC_PCU_OBS_BUS_1_RX_WEP_LSB) & MAC_PCU_OBS_BUS_1_RX_WEP_MASK)
+#define MAC_PCU_OBS_BUS_1_PCU_RX_END_MSB         1
+#define MAC_PCU_OBS_BUS_1_PCU_RX_END_LSB         1
+#define MAC_PCU_OBS_BUS_1_PCU_RX_END_MASK        0x00000002
+#define MAC_PCU_OBS_BUS_1_PCU_RX_END_GET(x)      (((x) & MAC_PCU_OBS_BUS_1_PCU_RX_END_MASK) >> MAC_PCU_OBS_BUS_1_PCU_RX_END_LSB)
+#define MAC_PCU_OBS_BUS_1_PCU_RX_END_SET(x)      (((x) << MAC_PCU_OBS_BUS_1_PCU_RX_END_LSB) & MAC_PCU_OBS_BUS_1_PCU_RX_END_MASK)
+#define MAC_PCU_OBS_BUS_1_PCU_DIRECTED_MSB       0
+#define MAC_PCU_OBS_BUS_1_PCU_DIRECTED_LSB       0
+#define MAC_PCU_OBS_BUS_1_PCU_DIRECTED_MASK      0x00000001
+#define MAC_PCU_OBS_BUS_1_PCU_DIRECTED_GET(x)    (((x) & MAC_PCU_OBS_BUS_1_PCU_DIRECTED_MASK) >> MAC_PCU_OBS_BUS_1_PCU_DIRECTED_LSB)
+#define MAC_PCU_OBS_BUS_1_PCU_DIRECTED_SET(x)    (((x) << MAC_PCU_OBS_BUS_1_PCU_DIRECTED_LSB) & MAC_PCU_OBS_BUS_1_PCU_DIRECTED_MASK)
+
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_ADDRESS        0x00008050
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_OFFSET         0x00000050
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_MSB 10
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_LSB 8
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_MASK 0x00000700
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_GET(x) (((x) & MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_MASK) >> MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_LSB)
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_SET(x) (((x) << MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_LSB) & MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_MASK)
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_MSB 6
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_LSB 4
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_MASK 0x00000070
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_GET(x) (((x) & MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_MASK) >> MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_LSB)
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_SET(x) (((x) << MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_LSB) & MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_MASK)
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_MSB 2
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_LSB 2
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_MASK 0x00000004
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_GET(x) (((x) & MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_MASK) >> MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_LSB)
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_SET(x) (((x) << MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_LSB) & MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_MASK)
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_MSB 1
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_LSB 1
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_MASK 0x00000002
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_GET(x) (((x) & MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_MASK) >> MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_LSB)
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_SET(x) (((x) << MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_LSB) & MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_MASK)
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_MSB 0
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_LSB 0
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_MASK 0x00000001
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_GET(x) (((x) & MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_MASK) >> MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_LSB)
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_SET(x) (((x) << MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_LSB) & MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_MASK)
+
+#define MAC_PCU_LAST_BEACON_TSF_ADDRESS          0x00008054
+#define MAC_PCU_LAST_BEACON_TSF_OFFSET           0x00000054
+#define MAC_PCU_LAST_BEACON_TSF_VALUE_MSB        31
+#define MAC_PCU_LAST_BEACON_TSF_VALUE_LSB        0
+#define MAC_PCU_LAST_BEACON_TSF_VALUE_MASK       0xffffffff
+#define MAC_PCU_LAST_BEACON_TSF_VALUE_GET(x)     (((x) & MAC_PCU_LAST_BEACON_TSF_VALUE_MASK) >> MAC_PCU_LAST_BEACON_TSF_VALUE_LSB)
+#define MAC_PCU_LAST_BEACON_TSF_VALUE_SET(x)     (((x) << MAC_PCU_LAST_BEACON_TSF_VALUE_LSB) & MAC_PCU_LAST_BEACON_TSF_VALUE_MASK)
+
+#define MAC_PCU_NAV_ADDRESS                      0x00008058
+#define MAC_PCU_NAV_OFFSET                       0x00000058
+#define MAC_PCU_NAV_VALUE_MSB                    25
+#define MAC_PCU_NAV_VALUE_LSB                    0
+#define MAC_PCU_NAV_VALUE_MASK                   0x03ffffff
+#define MAC_PCU_NAV_VALUE_GET(x)                 (((x) & MAC_PCU_NAV_VALUE_MASK) >> MAC_PCU_NAV_VALUE_LSB)
+#define MAC_PCU_NAV_VALUE_SET(x)                 (((x) << MAC_PCU_NAV_VALUE_LSB) & MAC_PCU_NAV_VALUE_MASK)
+
+#define MAC_PCU_RTS_SUCCESS_CNT_ADDRESS          0x0000805c
+#define MAC_PCU_RTS_SUCCESS_CNT_OFFSET           0x0000005c
+#define MAC_PCU_RTS_SUCCESS_CNT_VALUE_MSB        15
+#define MAC_PCU_RTS_SUCCESS_CNT_VALUE_LSB        0
+#define MAC_PCU_RTS_SUCCESS_CNT_VALUE_MASK       0x0000ffff
+#define MAC_PCU_RTS_SUCCESS_CNT_VALUE_GET(x)     (((x) & MAC_PCU_RTS_SUCCESS_CNT_VALUE_MASK) >> MAC_PCU_RTS_SUCCESS_CNT_VALUE_LSB)
+#define MAC_PCU_RTS_SUCCESS_CNT_VALUE_SET(x)     (((x) << MAC_PCU_RTS_SUCCESS_CNT_VALUE_LSB) & MAC_PCU_RTS_SUCCESS_CNT_VALUE_MASK)
+
+#define MAC_PCU_RTS_FAIL_CNT_ADDRESS             0x00008060
+#define MAC_PCU_RTS_FAIL_CNT_OFFSET              0x00000060
+#define MAC_PCU_RTS_FAIL_CNT_VALUE_MSB           15
+#define MAC_PCU_RTS_FAIL_CNT_VALUE_LSB           0
+#define MAC_PCU_RTS_FAIL_CNT_VALUE_MASK          0x0000ffff
+#define MAC_PCU_RTS_FAIL_CNT_VALUE_GET(x)        (((x) & MAC_PCU_RTS_FAIL_CNT_VALUE_MASK) >> MAC_PCU_RTS_FAIL_CNT_VALUE_LSB)
+#define MAC_PCU_RTS_FAIL_CNT_VALUE_SET(x)        (((x) << MAC_PCU_RTS_FAIL_CNT_VALUE_LSB) & MAC_PCU_RTS_FAIL_CNT_VALUE_MASK)
+
+#define MAC_PCU_ACK_FAIL_CNT_ADDRESS             0x00008064
+#define MAC_PCU_ACK_FAIL_CNT_OFFSET              0x00000064
+#define MAC_PCU_ACK_FAIL_CNT_VALUE_MSB           15
+#define MAC_PCU_ACK_FAIL_CNT_VALUE_LSB           0
+#define MAC_PCU_ACK_FAIL_CNT_VALUE_MASK          0x0000ffff
+#define MAC_PCU_ACK_FAIL_CNT_VALUE_GET(x)        (((x) & MAC_PCU_ACK_FAIL_CNT_VALUE_MASK) >> MAC_PCU_ACK_FAIL_CNT_VALUE_LSB)
+#define MAC_PCU_ACK_FAIL_CNT_VALUE_SET(x)        (((x) << MAC_PCU_ACK_FAIL_CNT_VALUE_LSB) & MAC_PCU_ACK_FAIL_CNT_VALUE_MASK)
+
+#define MAC_PCU_FCS_FAIL_CNT_ADDRESS             0x00008068
+#define MAC_PCU_FCS_FAIL_CNT_OFFSET              0x00000068
+#define MAC_PCU_FCS_FAIL_CNT_VALUE_MSB           15
+#define MAC_PCU_FCS_FAIL_CNT_VALUE_LSB           0
+#define MAC_PCU_FCS_FAIL_CNT_VALUE_MASK          0x0000ffff
+#define MAC_PCU_FCS_FAIL_CNT_VALUE_GET(x)        (((x) & MAC_PCU_FCS_FAIL_CNT_VALUE_MASK) >> MAC_PCU_FCS_FAIL_CNT_VALUE_LSB)
+#define MAC_PCU_FCS_FAIL_CNT_VALUE_SET(x)        (((x) << MAC_PCU_FCS_FAIL_CNT_VALUE_LSB) & MAC_PCU_FCS_FAIL_CNT_VALUE_MASK)
+
+#define MAC_PCU_BEACON_CNT_ADDRESS               0x0000806c
+#define MAC_PCU_BEACON_CNT_OFFSET                0x0000006c
+#define MAC_PCU_BEACON_CNT_VALUE_MSB             15
+#define MAC_PCU_BEACON_CNT_VALUE_LSB             0
+#define MAC_PCU_BEACON_CNT_VALUE_MASK            0x0000ffff
+#define MAC_PCU_BEACON_CNT_VALUE_GET(x)          (((x) & MAC_PCU_BEACON_CNT_VALUE_MASK) >> MAC_PCU_BEACON_CNT_VALUE_LSB)
+#define MAC_PCU_BEACON_CNT_VALUE_SET(x)          (((x) << MAC_PCU_BEACON_CNT_VALUE_LSB) & MAC_PCU_BEACON_CNT_VALUE_MASK)
+
+#define MAC_PCU_XRMODE_ADDRESS                   0x00008070
+#define MAC_PCU_XRMODE_OFFSET                    0x00000070
+#define MAC_PCU_XRMODE_FRAME_HOLD_MSB            31
+#define MAC_PCU_XRMODE_FRAME_HOLD_LSB            20
+#define MAC_PCU_XRMODE_FRAME_HOLD_MASK           0xfff00000
+#define MAC_PCU_XRMODE_FRAME_HOLD_GET(x)         (((x) & MAC_PCU_XRMODE_FRAME_HOLD_MASK) >> MAC_PCU_XRMODE_FRAME_HOLD_LSB)
+#define MAC_PCU_XRMODE_FRAME_HOLD_SET(x)         (((x) << MAC_PCU_XRMODE_FRAME_HOLD_LSB) & MAC_PCU_XRMODE_FRAME_HOLD_MASK)
+#define MAC_PCU_XRMODE_WAIT_FOR_POLL_MSB         7
+#define MAC_PCU_XRMODE_WAIT_FOR_POLL_LSB         7
+#define MAC_PCU_XRMODE_WAIT_FOR_POLL_MASK        0x00000080
+#define MAC_PCU_XRMODE_WAIT_FOR_POLL_GET(x)      (((x) & MAC_PCU_XRMODE_WAIT_FOR_POLL_MASK) >> MAC_PCU_XRMODE_WAIT_FOR_POLL_LSB)
+#define MAC_PCU_XRMODE_WAIT_FOR_POLL_SET(x)      (((x) << MAC_PCU_XRMODE_WAIT_FOR_POLL_LSB) & MAC_PCU_XRMODE_WAIT_FOR_POLL_MASK)
+#define MAC_PCU_XRMODE_POLL_TYPE_MSB             5
+#define MAC_PCU_XRMODE_POLL_TYPE_LSB             0
+#define MAC_PCU_XRMODE_POLL_TYPE_MASK            0x0000003f
+#define MAC_PCU_XRMODE_POLL_TYPE_GET(x)          (((x) & MAC_PCU_XRMODE_POLL_TYPE_MASK) >> MAC_PCU_XRMODE_POLL_TYPE_LSB)
+#define MAC_PCU_XRMODE_POLL_TYPE_SET(x)          (((x) << MAC_PCU_XRMODE_POLL_TYPE_LSB) & MAC_PCU_XRMODE_POLL_TYPE_MASK)
+
+#define MAC_PCU_XRDEL_ADDRESS                    0x00008074
+#define MAC_PCU_XRDEL_OFFSET                     0x00000074
+#define MAC_PCU_XRDEL_CHIRP_DATA_DELAY_MSB       31
+#define MAC_PCU_XRDEL_CHIRP_DATA_DELAY_LSB       16
+#define MAC_PCU_XRDEL_CHIRP_DATA_DELAY_MASK      0xffff0000
+#define MAC_PCU_XRDEL_CHIRP_DATA_DELAY_GET(x)    (((x) & MAC_PCU_XRDEL_CHIRP_DATA_DELAY_MASK) >> MAC_PCU_XRDEL_CHIRP_DATA_DELAY_LSB)
+#define MAC_PCU_XRDEL_CHIRP_DATA_DELAY_SET(x)    (((x) << MAC_PCU_XRDEL_CHIRP_DATA_DELAY_LSB) & MAC_PCU_XRDEL_CHIRP_DATA_DELAY_MASK)
+#define MAC_PCU_XRDEL_SLOT_DELAY_MSB             15
+#define MAC_PCU_XRDEL_SLOT_DELAY_LSB             0
+#define MAC_PCU_XRDEL_SLOT_DELAY_MASK            0x0000ffff
+#define MAC_PCU_XRDEL_SLOT_DELAY_GET(x)          (((x) & MAC_PCU_XRDEL_SLOT_DELAY_MASK) >> MAC_PCU_XRDEL_SLOT_DELAY_LSB)
+#define MAC_PCU_XRDEL_SLOT_DELAY_SET(x)          (((x) << MAC_PCU_XRDEL_SLOT_DELAY_LSB) & MAC_PCU_XRDEL_SLOT_DELAY_MASK)
+
+#define MAC_PCU_XRTO_ADDRESS                     0x00008078
+#define MAC_PCU_XRTO_OFFSET                      0x00000078
+#define MAC_PCU_XRTO_POLL_TIMEOUT_MSB            31
+#define MAC_PCU_XRTO_POLL_TIMEOUT_LSB            16
+#define MAC_PCU_XRTO_POLL_TIMEOUT_MASK           0xffff0000
+#define MAC_PCU_XRTO_POLL_TIMEOUT_GET(x)         (((x) & MAC_PCU_XRTO_POLL_TIMEOUT_MASK) >> MAC_PCU_XRTO_POLL_TIMEOUT_LSB)
+#define MAC_PCU_XRTO_POLL_TIMEOUT_SET(x)         (((x) << MAC_PCU_XRTO_POLL_TIMEOUT_LSB) & MAC_PCU_XRTO_POLL_TIMEOUT_MASK)
+#define MAC_PCU_XRTO_CHIRP_TIMEOUT_MSB           15
+#define MAC_PCU_XRTO_CHIRP_TIMEOUT_LSB           0
+#define MAC_PCU_XRTO_CHIRP_TIMEOUT_MASK          0x0000ffff
+#define MAC_PCU_XRTO_CHIRP_TIMEOUT_GET(x)        (((x) & MAC_PCU_XRTO_CHIRP_TIMEOUT_MASK) >> MAC_PCU_XRTO_CHIRP_TIMEOUT_LSB)
+#define MAC_PCU_XRTO_CHIRP_TIMEOUT_SET(x)        (((x) << MAC_PCU_XRTO_CHIRP_TIMEOUT_LSB) & MAC_PCU_XRTO_CHIRP_TIMEOUT_MASK)
+
+#define MAC_PCU_XRCRP_ADDRESS                    0x0000807c
+#define MAC_PCU_XRCRP_OFFSET                     0x0000007c
+#define MAC_PCU_XRCRP_CHIRP_GAP_MSB              31
+#define MAC_PCU_XRCRP_CHIRP_GAP_LSB              16
+#define MAC_PCU_XRCRP_CHIRP_GAP_MASK             0xffff0000
+#define MAC_PCU_XRCRP_CHIRP_GAP_GET(x)           (((x) & MAC_PCU_XRCRP_CHIRP_GAP_MASK) >> MAC_PCU_XRCRP_CHIRP_GAP_LSB)
+#define MAC_PCU_XRCRP_CHIRP_GAP_SET(x)           (((x) << MAC_PCU_XRCRP_CHIRP_GAP_LSB) & MAC_PCU_XRCRP_CHIRP_GAP_MASK)
+#define MAC_PCU_XRCRP_SEND_CHIRP_MSB             0
+#define MAC_PCU_XRCRP_SEND_CHIRP_LSB             0
+#define MAC_PCU_XRCRP_SEND_CHIRP_MASK            0x00000001
+#define MAC_PCU_XRCRP_SEND_CHIRP_GET(x)          (((x) & MAC_PCU_XRCRP_SEND_CHIRP_MASK) >> MAC_PCU_XRCRP_SEND_CHIRP_LSB)
+#define MAC_PCU_XRCRP_SEND_CHIRP_SET(x)          (((x) << MAC_PCU_XRCRP_SEND_CHIRP_LSB) & MAC_PCU_XRCRP_SEND_CHIRP_MASK)
+
+#define MAC_PCU_XRSTMP_ADDRESS                   0x00008080
+#define MAC_PCU_XRSTMP_OFFSET                    0x00000080
+#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_MSB  23
+#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_LSB  16
+#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_MASK 0x00ff0000
+#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_GET(x) (((x) & MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_MASK) >> MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_LSB)
+#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_SET(x) (((x) << MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_LSB) & MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_MASK)
+#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_MSB  15
+#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_LSB  8
+#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_MASK 0x0000ff00
+#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_GET(x) (((x) & MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_MASK) >> MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_LSB)
+#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_SET(x) (((x) << MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_LSB) & MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_MASK)
+#define MAC_PCU_XRSTMP_RX_ABORT_DATA_MSB         5
+#define MAC_PCU_XRSTMP_RX_ABORT_DATA_LSB         5
+#define MAC_PCU_XRSTMP_RX_ABORT_DATA_MASK        0x00000020
+#define MAC_PCU_XRSTMP_RX_ABORT_DATA_GET(x)      (((x) & MAC_PCU_XRSTMP_RX_ABORT_DATA_MASK) >> MAC_PCU_XRSTMP_RX_ABORT_DATA_LSB)
+#define MAC_PCU_XRSTMP_RX_ABORT_DATA_SET(x)      (((x) << MAC_PCU_XRSTMP_RX_ABORT_DATA_LSB) & MAC_PCU_XRSTMP_RX_ABORT_DATA_MASK)
+#define MAC_PCU_XRSTMP_TX_STOMP_DATA_MSB         4
+#define MAC_PCU_XRSTMP_TX_STOMP_DATA_LSB         4
+#define MAC_PCU_XRSTMP_TX_STOMP_DATA_MASK        0x00000010
+#define MAC_PCU_XRSTMP_TX_STOMP_DATA_GET(x)      (((x) & MAC_PCU_XRSTMP_TX_STOMP_DATA_MASK) >> MAC_PCU_XRSTMP_TX_STOMP_DATA_LSB)
+#define MAC_PCU_XRSTMP_TX_STOMP_DATA_SET(x)      (((x) << MAC_PCU_XRSTMP_TX_STOMP_DATA_LSB) & MAC_PCU_XRSTMP_TX_STOMP_DATA_MASK)
+#define MAC_PCU_XRSTMP_TX_STOMP_BSSID_MSB        3
+#define MAC_PCU_XRSTMP_TX_STOMP_BSSID_LSB        3
+#define MAC_PCU_XRSTMP_TX_STOMP_BSSID_MASK       0x00000008
+#define MAC_PCU_XRSTMP_TX_STOMP_BSSID_GET(x)     (((x) & MAC_PCU_XRSTMP_TX_STOMP_BSSID_MASK) >> MAC_PCU_XRSTMP_TX_STOMP_BSSID_LSB)
+#define MAC_PCU_XRSTMP_TX_STOMP_BSSID_SET(x)     (((x) << MAC_PCU_XRSTMP_TX_STOMP_BSSID_LSB) & MAC_PCU_XRSTMP_TX_STOMP_BSSID_MASK)
+#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_MSB         2
+#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_LSB         2
+#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_MASK        0x00000004
+#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_GET(x)      (((x) & MAC_PCU_XRSTMP_TX_STOMP_RSSI_MASK) >> MAC_PCU_XRSTMP_TX_STOMP_RSSI_LSB)
+#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_SET(x)      (((x) << MAC_PCU_XRSTMP_TX_STOMP_RSSI_LSB) & MAC_PCU_XRSTMP_TX_STOMP_RSSI_MASK)
+#define MAC_PCU_XRSTMP_RX_ABORT_BSSID_MSB        1
+#define MAC_PCU_XRSTMP_RX_ABORT_BSSID_LSB        1
+#define MAC_PCU_XRSTMP_RX_ABORT_BSSID_MASK       0x00000002
+#define MAC_PCU_XRSTMP_RX_ABORT_BSSID_GET(x)     (((x) & MAC_PCU_XRSTMP_RX_ABORT_BSSID_MASK) >> MAC_PCU_XRSTMP_RX_ABORT_BSSID_LSB)
+#define MAC_PCU_XRSTMP_RX_ABORT_BSSID_SET(x)     (((x) << MAC_PCU_XRSTMP_RX_ABORT_BSSID_LSB) & MAC_PCU_XRSTMP_RX_ABORT_BSSID_MASK)
+#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_MSB         0
+#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_LSB         0
+#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_MASK        0x00000001
+#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_GET(x)      (((x) & MAC_PCU_XRSTMP_RX_ABORT_RSSI_MASK) >> MAC_PCU_XRSTMP_RX_ABORT_RSSI_LSB)
+#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_SET(x)      (((x) << MAC_PCU_XRSTMP_RX_ABORT_RSSI_LSB) & MAC_PCU_XRSTMP_RX_ABORT_RSSI_MASK)
+
+#define MAC_PCU_ADDR1_MASK_L32_ADDRESS           0x00008084
+#define MAC_PCU_ADDR1_MASK_L32_OFFSET            0x00000084
+#define MAC_PCU_ADDR1_MASK_L32_VALUE_MSB         31
+#define MAC_PCU_ADDR1_MASK_L32_VALUE_LSB         0
+#define MAC_PCU_ADDR1_MASK_L32_VALUE_MASK        0xffffffff
+#define MAC_PCU_ADDR1_MASK_L32_VALUE_GET(x)      (((x) & MAC_PCU_ADDR1_MASK_L32_VALUE_MASK) >> MAC_PCU_ADDR1_MASK_L32_VALUE_LSB)
+#define MAC_PCU_ADDR1_MASK_L32_VALUE_SET(x)      (((x) << MAC_PCU_ADDR1_MASK_L32_VALUE_LSB) & MAC_PCU_ADDR1_MASK_L32_VALUE_MASK)
+
+#define MAC_PCU_ADDR1_MASK_U16_ADDRESS           0x00008088
+#define MAC_PCU_ADDR1_MASK_U16_OFFSET            0x00000088
+#define MAC_PCU_ADDR1_MASK_U16_VALUE_MSB         15
+#define MAC_PCU_ADDR1_MASK_U16_VALUE_LSB         0
+#define MAC_PCU_ADDR1_MASK_U16_VALUE_MASK        0x0000ffff
+#define MAC_PCU_ADDR1_MASK_U16_VALUE_GET(x)      (((x) & MAC_PCU_ADDR1_MASK_U16_VALUE_MASK) >> MAC_PCU_ADDR1_MASK_U16_VALUE_LSB)
+#define MAC_PCU_ADDR1_MASK_U16_VALUE_SET(x)      (((x) << MAC_PCU_ADDR1_MASK_U16_VALUE_LSB) & MAC_PCU_ADDR1_MASK_U16_VALUE_MASK)
+
+#define MAC_PCU_TPC_ADDRESS                      0x0000808c
+#define MAC_PCU_TPC_OFFSET                       0x0000008c
+#define MAC_PCU_TPC_CHIRP_PWR_MSB                21
+#define MAC_PCU_TPC_CHIRP_PWR_LSB                16
+#define MAC_PCU_TPC_CHIRP_PWR_MASK               0x003f0000
+#define MAC_PCU_TPC_CHIRP_PWR_GET(x)             (((x) & MAC_PCU_TPC_CHIRP_PWR_MASK) >> MAC_PCU_TPC_CHIRP_PWR_LSB)
+#define MAC_PCU_TPC_CHIRP_PWR_SET(x)             (((x) << MAC_PCU_TPC_CHIRP_PWR_LSB) & MAC_PCU_TPC_CHIRP_PWR_MASK)
+#define MAC_PCU_TPC_CTS_PWR_MSB                  13
+#define MAC_PCU_TPC_CTS_PWR_LSB                  8
+#define MAC_PCU_TPC_CTS_PWR_MASK                 0x00003f00
+#define MAC_PCU_TPC_CTS_PWR_GET(x)               (((x) & MAC_PCU_TPC_CTS_PWR_MASK) >> MAC_PCU_TPC_CTS_PWR_LSB)
+#define MAC_PCU_TPC_CTS_PWR_SET(x)               (((x) << MAC_PCU_TPC_CTS_PWR_LSB) & MAC_PCU_TPC_CTS_PWR_MASK)
+#define MAC_PCU_TPC_ACK_PWR_MSB                  5
+#define MAC_PCU_TPC_ACK_PWR_LSB                  0
+#define MAC_PCU_TPC_ACK_PWR_MASK                 0x0000003f
+#define MAC_PCU_TPC_ACK_PWR_GET(x)               (((x) & MAC_PCU_TPC_ACK_PWR_MASK) >> MAC_PCU_TPC_ACK_PWR_LSB)
+#define MAC_PCU_TPC_ACK_PWR_SET(x)               (((x) << MAC_PCU_TPC_ACK_PWR_LSB) & MAC_PCU_TPC_ACK_PWR_MASK)
+
+#define MAC_PCU_TX_FRAME_CNT_ADDRESS             0x00008090
+#define MAC_PCU_TX_FRAME_CNT_OFFSET              0x00000090
+#define MAC_PCU_TX_FRAME_CNT_VALUE_MSB           31
+#define MAC_PCU_TX_FRAME_CNT_VALUE_LSB           0
+#define MAC_PCU_TX_FRAME_CNT_VALUE_MASK          0xffffffff
+#define MAC_PCU_TX_FRAME_CNT_VALUE_GET(x)        (((x) & MAC_PCU_TX_FRAME_CNT_VALUE_MASK) >> MAC_PCU_TX_FRAME_CNT_VALUE_LSB)
+#define MAC_PCU_TX_FRAME_CNT_VALUE_SET(x)        (((x) << MAC_PCU_TX_FRAME_CNT_VALUE_LSB) & MAC_PCU_TX_FRAME_CNT_VALUE_MASK)
+
+#define MAC_PCU_RX_FRAME_CNT_ADDRESS             0x00008094
+#define MAC_PCU_RX_FRAME_CNT_OFFSET              0x00000094
+#define MAC_PCU_RX_FRAME_CNT_VALUE_MSB           31
+#define MAC_PCU_RX_FRAME_CNT_VALUE_LSB           0
+#define MAC_PCU_RX_FRAME_CNT_VALUE_MASK          0xffffffff
+#define MAC_PCU_RX_FRAME_CNT_VALUE_GET(x)        (((x) & MAC_PCU_RX_FRAME_CNT_VALUE_MASK) >> MAC_PCU_RX_FRAME_CNT_VALUE_LSB)
+#define MAC_PCU_RX_FRAME_CNT_VALUE_SET(x)        (((x) << MAC_PCU_RX_FRAME_CNT_VALUE_LSB) & MAC_PCU_RX_FRAME_CNT_VALUE_MASK)
+
+#define MAC_PCU_RX_CLEAR_CNT_ADDRESS             0x00008098
+#define MAC_PCU_RX_CLEAR_CNT_OFFSET              0x00000098
+#define MAC_PCU_RX_CLEAR_CNT_VALUE_MSB           31
+#define MAC_PCU_RX_CLEAR_CNT_VALUE_LSB           0
+#define MAC_PCU_RX_CLEAR_CNT_VALUE_MASK          0xffffffff
+#define MAC_PCU_RX_CLEAR_CNT_VALUE_GET(x)        (((x) & MAC_PCU_RX_CLEAR_CNT_VALUE_MASK) >> MAC_PCU_RX_CLEAR_CNT_VALUE_LSB)
+#define MAC_PCU_RX_CLEAR_CNT_VALUE_SET(x)        (((x) << MAC_PCU_RX_CLEAR_CNT_VALUE_LSB) & MAC_PCU_RX_CLEAR_CNT_VALUE_MASK)
+
+#define MAC_PCU_CYCLE_CNT_ADDRESS                0x0000809c
+#define MAC_PCU_CYCLE_CNT_OFFSET                 0x0000009c
+#define MAC_PCU_CYCLE_CNT_VALUE_MSB              31
+#define MAC_PCU_CYCLE_CNT_VALUE_LSB              0
+#define MAC_PCU_CYCLE_CNT_VALUE_MASK             0xffffffff
+#define MAC_PCU_CYCLE_CNT_VALUE_GET(x)           (((x) & MAC_PCU_CYCLE_CNT_VALUE_MASK) >> MAC_PCU_CYCLE_CNT_VALUE_LSB)
+#define MAC_PCU_CYCLE_CNT_VALUE_SET(x)           (((x) << MAC_PCU_CYCLE_CNT_VALUE_LSB) & MAC_PCU_CYCLE_CNT_VALUE_MASK)
+
+#define MAC_PCU_QUIET_TIME_1_ADDRESS             0x000080a0
+#define MAC_PCU_QUIET_TIME_1_OFFSET              0x000000a0
+#define MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_MSB  17
+#define MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_LSB  17
+#define MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_MASK 0x00020000
+#define MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_GET(x) (((x) & MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_MASK) >> MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_LSB)
+#define MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_SET(x) (((x) << MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_LSB) & MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_MASK)
+
+#define MAC_PCU_QUIET_TIME_2_ADDRESS             0x000080a4
+#define MAC_PCU_QUIET_TIME_2_OFFSET              0x000000a4
+#define MAC_PCU_QUIET_TIME_2_DURATION_MSB        31
+#define MAC_PCU_QUIET_TIME_2_DURATION_LSB        16
+#define MAC_PCU_QUIET_TIME_2_DURATION_MASK       0xffff0000
+#define MAC_PCU_QUIET_TIME_2_DURATION_GET(x)     (((x) & MAC_PCU_QUIET_TIME_2_DURATION_MASK) >> MAC_PCU_QUIET_TIME_2_DURATION_LSB)
+#define MAC_PCU_QUIET_TIME_2_DURATION_SET(x)     (((x) << MAC_PCU_QUIET_TIME_2_DURATION_LSB) & MAC_PCU_QUIET_TIME_2_DURATION_MASK)
+
+#define MAC_PCU_QOS_NO_ACK_ADDRESS               0x000080a8
+#define MAC_PCU_QOS_NO_ACK_OFFSET                0x000000a8
+#define MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_MSB       8
+#define MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_LSB       7
+#define MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_MASK      0x00000180
+#define MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_GET(x)    (((x) & MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_MASK) >> MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_LSB)
+#define MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_SET(x)    (((x) << MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_LSB) & MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_MASK)
+#define MAC_PCU_QOS_NO_ACK_BIT_OFFSET_MSB        6
+#define MAC_PCU_QOS_NO_ACK_BIT_OFFSET_LSB        4
+#define MAC_PCU_QOS_NO_ACK_BIT_OFFSET_MASK       0x00000070
+#define MAC_PCU_QOS_NO_ACK_BIT_OFFSET_GET(x)     (((x) & MAC_PCU_QOS_NO_ACK_BIT_OFFSET_MASK) >> MAC_PCU_QOS_NO_ACK_BIT_OFFSET_LSB)
+#define MAC_PCU_QOS_NO_ACK_BIT_OFFSET_SET(x)     (((x) << MAC_PCU_QOS_NO_ACK_BIT_OFFSET_LSB) & MAC_PCU_QOS_NO_ACK_BIT_OFFSET_MASK)
+#define MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_MSB    3
+#define MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_LSB    0
+#define MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_MASK   0x0000000f
+#define MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_GET(x) (((x) & MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_MASK) >> MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_LSB)
+#define MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_SET(x) (((x) << MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_LSB) & MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_MASK)
+
+#define MAC_PCU_PHY_ERROR_MASK_ADDRESS           0x000080ac
+#define MAC_PCU_PHY_ERROR_MASK_OFFSET            0x000000ac
+#define MAC_PCU_PHY_ERROR_MASK_VALUE_MSB         31
+#define MAC_PCU_PHY_ERROR_MASK_VALUE_LSB         0
+#define MAC_PCU_PHY_ERROR_MASK_VALUE_MASK        0xffffffff
+#define MAC_PCU_PHY_ERROR_MASK_VALUE_GET(x)      (((x) & MAC_PCU_PHY_ERROR_MASK_VALUE_MASK) >> MAC_PCU_PHY_ERROR_MASK_VALUE_LSB)
+#define MAC_PCU_PHY_ERROR_MASK_VALUE_SET(x)      (((x) << MAC_PCU_PHY_ERROR_MASK_VALUE_LSB) & MAC_PCU_PHY_ERROR_MASK_VALUE_MASK)
+
+#define MAC_PCU_XRLAT_ADDRESS                    0x000080b0
+#define MAC_PCU_XRLAT_OFFSET                     0x000000b0
+#define MAC_PCU_XRLAT_VALUE_MSB                  11
+#define MAC_PCU_XRLAT_VALUE_LSB                  0
+#define MAC_PCU_XRLAT_VALUE_MASK                 0x00000fff
+#define MAC_PCU_XRLAT_VALUE_GET(x)               (((x) & MAC_PCU_XRLAT_VALUE_MASK) >> MAC_PCU_XRLAT_VALUE_LSB)
+#define MAC_PCU_XRLAT_VALUE_SET(x)               (((x) << MAC_PCU_XRLAT_VALUE_LSB) & MAC_PCU_XRLAT_VALUE_MASK)
+
+#define MAC_PCU_RXBUF_ADDRESS                    0x000080b4
+#define MAC_PCU_RXBUF_OFFSET                     0x000000b4
+#define MAC_PCU_RXBUF_REG_RD_ENABLE_MSB          11
+#define MAC_PCU_RXBUF_REG_RD_ENABLE_LSB          11
+#define MAC_PCU_RXBUF_REG_RD_ENABLE_MASK         0x00000800
+#define MAC_PCU_RXBUF_REG_RD_ENABLE_GET(x)       (((x) & MAC_PCU_RXBUF_REG_RD_ENABLE_MASK) >> MAC_PCU_RXBUF_REG_RD_ENABLE_LSB)
+#define MAC_PCU_RXBUF_REG_RD_ENABLE_SET(x)       (((x) << MAC_PCU_RXBUF_REG_RD_ENABLE_LSB) & MAC_PCU_RXBUF_REG_RD_ENABLE_MASK)
+#define MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_MSB   10
+#define MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_LSB   0
+#define MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_MASK  0x000007ff
+#define MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_GET(x) (((x) & MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_MASK) >> MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_LSB)
+#define MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_SET(x) (((x) << MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_LSB) & MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_MASK)
+
+#define MAC_PCU_MIC_QOS_CONTROL_ADDRESS          0x000080b8
+#define MAC_PCU_MIC_QOS_CONTROL_OFFSET           0x000000b8
+#define MAC_PCU_MIC_QOS_CONTROL_ENABLE_MSB       16
+#define MAC_PCU_MIC_QOS_CONTROL_ENABLE_LSB       16
+#define MAC_PCU_MIC_QOS_CONTROL_ENABLE_MASK      0x00010000
+#define MAC_PCU_MIC_QOS_CONTROL_ENABLE_GET(x)    (((x) & MAC_PCU_MIC_QOS_CONTROL_ENABLE_MASK) >> MAC_PCU_MIC_QOS_CONTROL_ENABLE_LSB)
+#define MAC_PCU_MIC_QOS_CONTROL_ENABLE_SET(x)    (((x) << MAC_PCU_MIC_QOS_CONTROL_ENABLE_LSB) & MAC_PCU_MIC_QOS_CONTROL_ENABLE_MASK)
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_7_MSB      15
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_7_LSB      14
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_7_MASK     0x0000c000
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_7_GET(x)   (((x) & MAC_PCU_MIC_QOS_CONTROL_VALUE_7_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_7_LSB)
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_7_SET(x)   (((x) << MAC_PCU_MIC_QOS_CONTROL_VALUE_7_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_7_MASK)
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_6_MSB      13
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_6_LSB      12
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_6_MASK     0x00003000
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_6_GET(x)   (((x) & MAC_PCU_MIC_QOS_CONTROL_VALUE_6_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_6_LSB)
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_6_SET(x)   (((x) << MAC_PCU_MIC_QOS_CONTROL_VALUE_6_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_6_MASK)
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_5_MSB      11
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_5_LSB      10
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_5_MASK     0x00000c00
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_5_GET(x)   (((x) & MAC_PCU_MIC_QOS_CONTROL_VALUE_5_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_5_LSB)
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_5_SET(x)   (((x) << MAC_PCU_MIC_QOS_CONTROL_VALUE_5_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_5_MASK)
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_4_MSB      9
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_4_LSB      8
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_4_MASK     0x00000300
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_4_GET(x)   (((x) & MAC_PCU_MIC_QOS_CONTROL_VALUE_4_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_4_LSB)
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_4_SET(x)   (((x) << MAC_PCU_MIC_QOS_CONTROL_VALUE_4_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_4_MASK)
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_3_MSB      7
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_3_LSB      6
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_3_MASK     0x000000c0
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_3_GET(x)   (((x) & MAC_PCU_MIC_QOS_CONTROL_VALUE_3_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_3_LSB)
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_3_SET(x)   (((x) << MAC_PCU_MIC_QOS_CONTROL_VALUE_3_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_3_MASK)
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_2_MSB      5
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_2_LSB      4
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_2_MASK     0x00000030
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_2_GET(x)   (((x) & MAC_PCU_MIC_QOS_CONTROL_VALUE_2_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_2_LSB)
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_2_SET(x)   (((x) << MAC_PCU_MIC_QOS_CONTROL_VALUE_2_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_2_MASK)
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_1_MSB      3
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_1_LSB      2
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_1_MASK     0x0000000c
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_1_GET(x)   (((x) & MAC_PCU_MIC_QOS_CONTROL_VALUE_1_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_1_LSB)
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_1_SET(x)   (((x) << MAC_PCU_MIC_QOS_CONTROL_VALUE_1_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_1_MASK)
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_0_MSB      1
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_0_LSB      0
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_0_MASK     0x00000003
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_0_GET(x)   (((x) & MAC_PCU_MIC_QOS_CONTROL_VALUE_0_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_0_LSB)
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_0_SET(x)   (((x) << MAC_PCU_MIC_QOS_CONTROL_VALUE_0_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_0_MASK)
+
+#define MAC_PCU_MIC_QOS_SELECT_ADDRESS           0x000080bc
+#define MAC_PCU_MIC_QOS_SELECT_OFFSET            0x000000bc
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_7_MSB       31
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_7_LSB       28
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_7_MASK      0xf0000000
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_7_GET(x)    (((x) & MAC_PCU_MIC_QOS_SELECT_VALUE_7_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_7_LSB)
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_7_SET(x)    (((x) << MAC_PCU_MIC_QOS_SELECT_VALUE_7_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_7_MASK)
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_6_MSB       27
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_6_LSB       24
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_6_MASK      0x0f000000
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_6_GET(x)    (((x) & MAC_PCU_MIC_QOS_SELECT_VALUE_6_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_6_LSB)
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_6_SET(x)    (((x) << MAC_PCU_MIC_QOS_SELECT_VALUE_6_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_6_MASK)
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_5_MSB       23
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_5_LSB       20
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_5_MASK      0x00f00000
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_5_GET(x)    (((x) & MAC_PCU_MIC_QOS_SELECT_VALUE_5_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_5_LSB)
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_5_SET(x)    (((x) << MAC_PCU_MIC_QOS_SELECT_VALUE_5_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_5_MASK)
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_4_MSB       19
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_4_LSB       16
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_4_MASK      0x000f0000
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_4_GET(x)    (((x) & MAC_PCU_MIC_QOS_SELECT_VALUE_4_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_4_LSB)
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_4_SET(x)    (((x) << MAC_PCU_MIC_QOS_SELECT_VALUE_4_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_4_MASK)
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_3_MSB       15
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_3_LSB       12
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_3_MASK      0x0000f000
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_3_GET(x)    (((x) & MAC_PCU_MIC_QOS_SELECT_VALUE_3_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_3_LSB)
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_3_SET(x)    (((x) << MAC_PCU_MIC_QOS_SELECT_VALUE_3_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_3_MASK)
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_2_MSB       11
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_2_LSB       8
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_2_MASK      0x00000f00
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_2_GET(x)    (((x) & MAC_PCU_MIC_QOS_SELECT_VALUE_2_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_2_LSB)
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_2_SET(x)    (((x) << MAC_PCU_MIC_QOS_SELECT_VALUE_2_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_2_MASK)
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_1_MSB       7
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_1_LSB       4
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_1_MASK      0x000000f0
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_1_GET(x)    (((x) & MAC_PCU_MIC_QOS_SELECT_VALUE_1_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_1_LSB)
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_1_SET(x)    (((x) << MAC_PCU_MIC_QOS_SELECT_VALUE_1_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_1_MASK)
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_0_MSB       3
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_0_LSB       0
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_0_MASK      0x0000000f
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_0_GET(x)    (((x) & MAC_PCU_MIC_QOS_SELECT_VALUE_0_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_0_LSB)
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_0_SET(x)    (((x) << MAC_PCU_MIC_QOS_SELECT_VALUE_0_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_0_MASK)
+
+#define MAC_PCU_MISC_MODE_ADDRESS                0x000080c0
+#define MAC_PCU_MISC_MODE_OFFSET                 0x000000c0
+#define MAC_PCU_MISC_MODE_DEBUG_MODE_MSB         31
+#define MAC_PCU_MISC_MODE_DEBUG_MODE_LSB         30
+#define MAC_PCU_MISC_MODE_DEBUG_MODE_MASK        0xc0000000
+#define MAC_PCU_MISC_MODE_DEBUG_MODE_GET(x)      (((x) & MAC_PCU_MISC_MODE_DEBUG_MODE_MASK) >> MAC_PCU_MISC_MODE_DEBUG_MODE_LSB)
+#define MAC_PCU_MISC_MODE_DEBUG_MODE_SET(x)      (((x) << MAC_PCU_MISC_MODE_DEBUG_MODE_LSB) & MAC_PCU_MISC_MODE_DEBUG_MODE_MASK)
+#define MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_MSB 29
+#define MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_LSB 29
+#define MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_MASK 0x20000000
+#define MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_GET(x) (((x) & MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_MASK) >> MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_LSB)
+#define MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_SET(x) (((x) << MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_LSB) & MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_MASK)
+#define MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_MSB 28
+#define MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_LSB 28
+#define MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_MASK 0x10000000
+#define MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_GET(x) (((x) & MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_MASK) >> MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_LSB)
+#define MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_SET(x) (((x) << MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_LSB) & MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_MASK)
+#define MAC_PCU_MISC_MODE_SEL_EVM_MSB            27
+#define MAC_PCU_MISC_MODE_SEL_EVM_LSB            27
+#define MAC_PCU_MISC_MODE_SEL_EVM_MASK           0x08000000
+#define MAC_PCU_MISC_MODE_SEL_EVM_GET(x)         (((x) & MAC_PCU_MISC_MODE_SEL_EVM_MASK) >> MAC_PCU_MISC_MODE_SEL_EVM_LSB)
+#define MAC_PCU_MISC_MODE_SEL_EVM_SET(x)         (((x) << MAC_PCU_MISC_MODE_SEL_EVM_LSB) & MAC_PCU_MISC_MODE_SEL_EVM_MASK)
+#define MAC_PCU_MISC_MODE_CLEAR_BA_VALID_MSB     26
+#define MAC_PCU_MISC_MODE_CLEAR_BA_VALID_LSB     26
+#define MAC_PCU_MISC_MODE_CLEAR_BA_VALID_MASK    0x04000000
+#define MAC_PCU_MISC_MODE_CLEAR_BA_VALID_GET(x)  (((x) & MAC_PCU_MISC_MODE_CLEAR_BA_VALID_MASK) >> MAC_PCU_MISC_MODE_CLEAR_BA_VALID_LSB)
+#define MAC_PCU_MISC_MODE_CLEAR_BA_VALID_SET(x)  (((x) << MAC_PCU_MISC_MODE_CLEAR_BA_VALID_LSB) & MAC_PCU_MISC_MODE_CLEAR_BA_VALID_MASK)
+#define MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_MSB    25
+#define MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_LSB    25
+#define MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_MASK   0x02000000
+#define MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_GET(x) (((x) & MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_MASK) >> MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_LSB)
+#define MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_SET(x) (((x) << MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_LSB) & MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_MASK)
+#define MAC_PCU_MISC_MODE_CLEAR_VMF_MSB          24
+#define MAC_PCU_MISC_MODE_CLEAR_VMF_LSB          24
+#define MAC_PCU_MISC_MODE_CLEAR_VMF_MASK         0x01000000
+#define MAC_PCU_MISC_MODE_CLEAR_VMF_GET(x)       (((x) & MAC_PCU_MISC_MODE_CLEAR_VMF_MASK) >> MAC_PCU_MISC_MODE_CLEAR_VMF_LSB)
+#define MAC_PCU_MISC_MODE_CLEAR_VMF_SET(x)       (((x) << MAC_PCU_MISC_MODE_CLEAR_VMF_LSB) & MAC_PCU_MISC_MODE_CLEAR_VMF_MASK)
+#define MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_MSB 23
+#define MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_LSB 23
+#define MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_MASK 0x00800000
+#define MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_GET(x) (((x) & MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_MASK) >> MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_LSB)
+#define MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_SET(x) (((x) << MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_LSB) & MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_MASK)
+#define MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_MSB 22
+#define MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_LSB 22
+#define MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_MASK 0x00400000
+#define MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_GET(x) (((x) & MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_MASK) >> MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_LSB)
+#define MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_SET(x) (((x) << MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_LSB) & MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_MASK)
+#define MAC_PCU_MISC_MODE_TBTT_PROTECT_MSB       21
+#define MAC_PCU_MISC_MODE_TBTT_PROTECT_LSB       21
+#define MAC_PCU_MISC_MODE_TBTT_PROTECT_MASK      0x00200000
+#define MAC_PCU_MISC_MODE_TBTT_PROTECT_GET(x)    (((x) & MAC_PCU_MISC_MODE_TBTT_PROTECT_MASK) >> MAC_PCU_MISC_MODE_TBTT_PROTECT_LSB)
+#define MAC_PCU_MISC_MODE_TBTT_PROTECT_SET(x)    (((x) << MAC_PCU_MISC_MODE_TBTT_PROTECT_LSB) & MAC_PCU_MISC_MODE_TBTT_PROTECT_MASK)
+#define MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_MSB 20
+#define MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_LSB 20
+#define MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_MASK 0x00100000
+#define MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_GET(x) (((x) & MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_MASK) >> MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_LSB)
+#define MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_SET(x) (((x) << MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_LSB) & MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_MASK)
+#define MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_MSB 18
+#define MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_LSB 18
+#define MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_MASK 0x00040000
+#define MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_GET(x) (((x) & MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_MASK) >> MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_LSB)
+#define MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_SET(x) (((x) << MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_LSB) & MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_MASK)
+#define MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_MSB 14
+#define MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_LSB 14
+#define MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_MASK 0x00004000
+#define MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_GET(x) (((x) & MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_MASK) >> MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_LSB)
+#define MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_SET(x) (((x) << MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_LSB) & MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_MASK)
+#define MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_MSB 12
+#define MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_LSB 12
+#define MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_MASK 0x00001000
+#define MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_GET(x) (((x) & MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_MASK) >> MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_LSB)
+#define MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_SET(x) (((x) << MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_LSB) & MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_MASK)
+#define MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_MSB   11
+#define MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_LSB   11
+#define MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_MASK  0x00000800
+#define MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_GET(x) (((x) & MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_MASK) >> MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_LSB)
+#define MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_SET(x) (((x) << MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_LSB) & MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_MASK)
+#define MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_MSB    10
+#define MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_LSB    10
+#define MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_MASK   0x00000400
+#define MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_GET(x) (((x) & MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_MASK) >> MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_LSB)
+#define MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_SET(x) (((x) << MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_LSB) & MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_MASK)
+#define MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_MSB 9
+#define MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_LSB 9
+#define MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_MASK 0x00000200
+#define MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_GET(x) (((x) & MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_MASK) >> MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_LSB)
+#define MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_SET(x) (((x) << MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_LSB) & MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_MASK)
+#define MAC_PCU_MISC_MODE_CCK_SIFS_MODE_MSB      4
+#define MAC_PCU_MISC_MODE_CCK_SIFS_MODE_LSB      4
+#define MAC_PCU_MISC_MODE_CCK_SIFS_MODE_MASK     0x00000010
+#define MAC_PCU_MISC_MODE_CCK_SIFS_MODE_GET(x)   (((x) & MAC_PCU_MISC_MODE_CCK_SIFS_MODE_MASK) >> MAC_PCU_MISC_MODE_CCK_SIFS_MODE_LSB)
+#define MAC_PCU_MISC_MODE_CCK_SIFS_MODE_SET(x)   (((x) << MAC_PCU_MISC_MODE_CCK_SIFS_MODE_LSB) & MAC_PCU_MISC_MODE_CCK_SIFS_MODE_MASK)
+#define MAC_PCU_MISC_MODE_TX_ADD_TSF_MSB         3
+#define MAC_PCU_MISC_MODE_TX_ADD_TSF_LSB         3
+#define MAC_PCU_MISC_MODE_TX_ADD_TSF_MASK        0x00000008
+#define MAC_PCU_MISC_MODE_TX_ADD_TSF_GET(x)      (((x) & MAC_PCU_MISC_MODE_TX_ADD_TSF_MASK) >> MAC_PCU_MISC_MODE_TX_ADD_TSF_LSB)
+#define MAC_PCU_MISC_MODE_TX_ADD_TSF_SET(x)      (((x) << MAC_PCU_MISC_MODE_TX_ADD_TSF_LSB) & MAC_PCU_MISC_MODE_TX_ADD_TSF_MASK)
+#define MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_MSB 2
+#define MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_LSB 2
+#define MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_MASK 0x00000004
+#define MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_GET(x) (((x) & MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_MASK) >> MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_LSB)
+#define MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_SET(x) (((x) << MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_LSB) & MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_MASK)
+#define MAC_PCU_MISC_MODE_DEBUG_MODE_AD_MSB      1
+#define MAC_PCU_MISC_MODE_DEBUG_MODE_AD_LSB      1
+#define MAC_PCU_MISC_MODE_DEBUG_MODE_AD_MASK     0x00000002
+#define MAC_PCU_MISC_MODE_DEBUG_MODE_AD_GET(x)   (((x) & MAC_PCU_MISC_MODE_DEBUG_MODE_AD_MASK) >> MAC_PCU_MISC_MODE_DEBUG_MODE_AD_LSB)
+#define MAC_PCU_MISC_MODE_DEBUG_MODE_AD_SET(x)   (((x) << MAC_PCU_MISC_MODE_DEBUG_MODE_AD_LSB) & MAC_PCU_MISC_MODE_DEBUG_MODE_AD_MASK)
+#define MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_MSB  0
+#define MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_LSB  0
+#define MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_MASK 0x00000001
+#define MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_GET(x) (((x) & MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_MASK) >> MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_LSB)
+#define MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_SET(x) (((x) << MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_LSB) & MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_MASK)
+
+#define MAC_PCU_FILTER_OFDM_CNT_ADDRESS          0x000080c4
+#define MAC_PCU_FILTER_OFDM_CNT_OFFSET           0x000000c4
+#define MAC_PCU_FILTER_OFDM_CNT_VALUE_MSB        23
+#define MAC_PCU_FILTER_OFDM_CNT_VALUE_LSB        0
+#define MAC_PCU_FILTER_OFDM_CNT_VALUE_MASK       0x00ffffff
+#define MAC_PCU_FILTER_OFDM_CNT_VALUE_GET(x)     (((x) & MAC_PCU_FILTER_OFDM_CNT_VALUE_MASK) >> MAC_PCU_FILTER_OFDM_CNT_VALUE_LSB)
+#define MAC_PCU_FILTER_OFDM_CNT_VALUE_SET(x)     (((x) << MAC_PCU_FILTER_OFDM_CNT_VALUE_LSB) & MAC_PCU_FILTER_OFDM_CNT_VALUE_MASK)
+
+#define MAC_PCU_FILTER_CCK_CNT_ADDRESS           0x000080c8
+#define MAC_PCU_FILTER_CCK_CNT_OFFSET            0x000000c8
+#define MAC_PCU_FILTER_CCK_CNT_VALUE_MSB         23
+#define MAC_PCU_FILTER_CCK_CNT_VALUE_LSB         0
+#define MAC_PCU_FILTER_CCK_CNT_VALUE_MASK        0x00ffffff
+#define MAC_PCU_FILTER_CCK_CNT_VALUE_GET(x)      (((x) & MAC_PCU_FILTER_CCK_CNT_VALUE_MASK) >> MAC_PCU_FILTER_CCK_CNT_VALUE_LSB)
+#define MAC_PCU_FILTER_CCK_CNT_VALUE_SET(x)      (((x) << MAC_PCU_FILTER_CCK_CNT_VALUE_LSB) & MAC_PCU_FILTER_CCK_CNT_VALUE_MASK)
+
+#define MAC_PCU_PHY_ERR_CNT_1_ADDRESS            0x000080cc
+#define MAC_PCU_PHY_ERR_CNT_1_OFFSET             0x000000cc
+#define MAC_PCU_PHY_ERR_CNT_1_VALUE_MSB          23
+#define MAC_PCU_PHY_ERR_CNT_1_VALUE_LSB          0
+#define MAC_PCU_PHY_ERR_CNT_1_VALUE_MASK         0x00ffffff
+#define MAC_PCU_PHY_ERR_CNT_1_VALUE_GET(x)       (((x) & MAC_PCU_PHY_ERR_CNT_1_VALUE_MASK) >> MAC_PCU_PHY_ERR_CNT_1_VALUE_LSB)
+#define MAC_PCU_PHY_ERR_CNT_1_VALUE_SET(x)       (((x) << MAC_PCU_PHY_ERR_CNT_1_VALUE_LSB) & MAC_PCU_PHY_ERR_CNT_1_VALUE_MASK)
+
+#define MAC_PCU_PHY_ERR_CNT_1_MASK_ADDRESS       0x000080d0
+#define MAC_PCU_PHY_ERR_CNT_1_MASK_OFFSET        0x000000d0
+#define MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_MSB     31
+#define MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_LSB     0
+#define MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_MASK    0xffffffff
+#define MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_GET(x)  (((x) & MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_MASK) >> MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_LSB)
+#define MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_SET(x)  (((x) << MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_LSB) & MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_MASK)
+
+#define MAC_PCU_PHY_ERR_CNT_2_ADDRESS            0x000080d4
+#define MAC_PCU_PHY_ERR_CNT_2_OFFSET             0x000000d4
+#define MAC_PCU_PHY_ERR_CNT_2_VALUE_MSB          23
+#define MAC_PCU_PHY_ERR_CNT_2_VALUE_LSB          0
+#define MAC_PCU_PHY_ERR_CNT_2_VALUE_MASK         0x00ffffff
+#define MAC_PCU_PHY_ERR_CNT_2_VALUE_GET(x)       (((x) & MAC_PCU_PHY_ERR_CNT_2_VALUE_MASK) >> MAC_PCU_PHY_ERR_CNT_2_VALUE_LSB)
+#define MAC_PCU_PHY_ERR_CNT_2_VALUE_SET(x)       (((x) << MAC_PCU_PHY_ERR_CNT_2_VALUE_LSB) & MAC_PCU_PHY_ERR_CNT_2_VALUE_MASK)
+
+#define MAC_PCU_PHY_ERR_CNT_2_MASK_ADDRESS       0x000080d8
+#define MAC_PCU_PHY_ERR_CNT_2_MASK_OFFSET        0x000000d8
+#define MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_MSB     31
+#define MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_LSB     0
+#define MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_MASK    0xffffffff
+#define MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_GET(x)  (((x) & MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_MASK) >> MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_LSB)
+#define MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_SET(x)  (((x) << MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_LSB) & MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_MASK)
+
+#define MAC_PCU_TSF_THRESHOLD_ADDRESS            0x000080dc
+#define MAC_PCU_TSF_THRESHOLD_OFFSET             0x000000dc
+#define MAC_PCU_TSF_THRESHOLD_VALUE_MSB          15
+#define MAC_PCU_TSF_THRESHOLD_VALUE_LSB          0
+#define MAC_PCU_TSF_THRESHOLD_VALUE_MASK         0x0000ffff
+#define MAC_PCU_TSF_THRESHOLD_VALUE_GET(x)       (((x) & MAC_PCU_TSF_THRESHOLD_VALUE_MASK) >> MAC_PCU_TSF_THRESHOLD_VALUE_LSB)
+#define MAC_PCU_TSF_THRESHOLD_VALUE_SET(x)       (((x) << MAC_PCU_TSF_THRESHOLD_VALUE_LSB) & MAC_PCU_TSF_THRESHOLD_VALUE_MASK)
+
+#define MAC_PCU_PHY_ERROR_EIFS_MASK_ADDRESS      0x000080e0
+#define MAC_PCU_PHY_ERROR_EIFS_MASK_OFFSET       0x000000e0
+#define MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_MSB    31
+#define MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_LSB    0
+#define MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_MASK   0xffffffff
+#define MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_MASK) >> MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_LSB)
+#define MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_LSB) & MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_MASK)
+
+#define MAC_PCU_PHY_ERR_CNT_3_ADDRESS            0x000080e4
+#define MAC_PCU_PHY_ERR_CNT_3_OFFSET             0x000000e4
+#define MAC_PCU_PHY_ERR_CNT_3_VALUE_MSB          23
+#define MAC_PCU_PHY_ERR_CNT_3_VALUE_LSB          0
+#define MAC_PCU_PHY_ERR_CNT_3_VALUE_MASK         0x00ffffff
+#define MAC_PCU_PHY_ERR_CNT_3_VALUE_GET(x)       (((x) & MAC_PCU_PHY_ERR_CNT_3_VALUE_MASK) >> MAC_PCU_PHY_ERR_CNT_3_VALUE_LSB)
+#define MAC_PCU_PHY_ERR_CNT_3_VALUE_SET(x)       (((x) << MAC_PCU_PHY_ERR_CNT_3_VALUE_LSB) & MAC_PCU_PHY_ERR_CNT_3_VALUE_MASK)
+
+#define MAC_PCU_PHY_ERR_CNT_3_MASK_ADDRESS       0x000080e8
+#define MAC_PCU_PHY_ERR_CNT_3_MASK_OFFSET        0x000000e8
+#define MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_MSB     31
+#define MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_LSB     0
+#define MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_MASK    0xffffffff
+#define MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_GET(x)  (((x) & MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_MASK) >> MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_LSB)
+#define MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_SET(x)  (((x) << MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_LSB) & MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_MASK)
+
+#define MAC_PCU_BLUETOOTH_MODE_ADDRESS           0x000080ec
+#define MAC_PCU_BLUETOOTH_MODE_OFFSET            0x000000ec
+#define MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_MSB 31
+#define MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_LSB 24
+#define MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_MASK 0xff000000
+#define MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_MASK) >> MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_LSB)
+#define MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_LSB) & MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_MASK)
+#define MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_MSB 23
+#define MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_LSB 18
+#define MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_MASK 0x00fc0000
+#define MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_MASK) >> MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_LSB)
+#define MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_LSB) & MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_MASK)
+#define MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_MSB 17
+#define MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_LSB 17
+#define MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_MASK 0x00020000
+#define MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_MASK) >> MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_LSB)
+#define MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_LSB) & MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_MASK)
+#define MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_MSB    16
+#define MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_LSB    13
+#define MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_MASK   0x0001e000
+#define MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_MASK) >> MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_LSB)
+#define MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_LSB) & MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_MASK)
+#define MAC_PCU_BLUETOOTH_MODE_QUIET_MSB         12
+#define MAC_PCU_BLUETOOTH_MODE_QUIET_LSB         12
+#define MAC_PCU_BLUETOOTH_MODE_QUIET_MASK        0x00001000
+#define MAC_PCU_BLUETOOTH_MODE_QUIET_GET(x)      (((x) & MAC_PCU_BLUETOOTH_MODE_QUIET_MASK) >> MAC_PCU_BLUETOOTH_MODE_QUIET_LSB)
+#define MAC_PCU_BLUETOOTH_MODE_QUIET_SET(x)      (((x) << MAC_PCU_BLUETOOTH_MODE_QUIET_LSB) & MAC_PCU_BLUETOOTH_MODE_QUIET_MASK)
+#define MAC_PCU_BLUETOOTH_MODE_MODE_MSB          11
+#define MAC_PCU_BLUETOOTH_MODE_MODE_LSB          10
+#define MAC_PCU_BLUETOOTH_MODE_MODE_MASK         0x00000c00
+#define MAC_PCU_BLUETOOTH_MODE_MODE_GET(x)       (((x) & MAC_PCU_BLUETOOTH_MODE_MODE_MASK) >> MAC_PCU_BLUETOOTH_MODE_MODE_LSB)
+#define MAC_PCU_BLUETOOTH_MODE_MODE_SET(x)       (((x) << MAC_PCU_BLUETOOTH_MODE_MODE_LSB) & MAC_PCU_BLUETOOTH_MODE_MODE_MASK)
+#define MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_MSB 9
+#define MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_LSB 9
+#define MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_MASK 0x00000200
+#define MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_MASK) >> MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_LSB)
+#define MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_LSB) & MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_MASK)
+#define MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_MSB 8
+#define MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_LSB 8
+#define MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_MASK 0x00000100
+#define MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_MASK) >> MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_LSB)
+#define MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_LSB) & MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_MASK)
+#define MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_MSB   7
+#define MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_LSB   0
+#define MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_MASK  0x000000ff
+#define MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_MASK) >> MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_LSB)
+#define MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_LSB) & MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_MASK)
+
+#define MAC_PCU_BLUETOOTH_WEIGHTS_ADDRESS        0x000080f0
+#define MAC_PCU_BLUETOOTH_WEIGHTS_OFFSET         0x000000f0
+#define MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_MSB  31
+#define MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_LSB  16
+#define MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_MASK 0xffff0000
+#define MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_GET(x) (((x) & MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_MASK) >> MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_LSB)
+#define MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_SET(x) (((x) << MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_LSB) & MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_MASK)
+#define MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_MSB  15
+#define MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_LSB  0
+#define MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_MASK 0x0000ffff
+#define MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_GET(x) (((x) & MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_MASK) >> MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_LSB)
+#define MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_SET(x) (((x) << MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_LSB) & MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_MASK)
+
+#define MAC_PCU_BLUETOOTH_MODE2_ADDRESS          0x000080f4
+#define MAC_PCU_BLUETOOTH_MODE2_OFFSET           0x000000f4
+#define MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_MSB 31
+#define MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_LSB 31
+#define MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_MASK 0x80000000
+#define MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_MASK) >> MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_LSB)
+#define MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_LSB) & MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_MASK)
+#define MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_MSB 30
+#define MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_LSB 30
+#define MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_MASK 0x40000000
+#define MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_MASK) >> MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_LSB)
+#define MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_LSB) & MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_MASK)
+#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_MSB 29
+#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_LSB 28
+#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_MASK 0x30000000
+#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_MASK) >> MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_LSB)
+#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_LSB) & MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_MASK)
+#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_MSB 27
+#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_LSB 26
+#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_MASK 0x0c000000
+#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_MASK) >> MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_LSB)
+#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_LSB) & MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_MASK)
+#define MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_MSB 25
+#define MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_LSB 25
+#define MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_MASK 0x02000000
+#define MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_MASK) >> MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_LSB)
+#define MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_LSB) & MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_MASK)
+#define MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_MSB 24
+#define MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_LSB 24
+#define MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_MASK 0x01000000
+#define MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_MASK) >> MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_LSB)
+#define MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_LSB) & MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_MASK)
+#define MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_MSB 23
+#define MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_LSB 22
+#define MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_MASK 0x00c00000
+#define MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_MASK) >> MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_LSB)
+#define MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_LSB) & MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_MASK)
+#define MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_MSB 21
+#define MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_LSB 21
+#define MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_MASK 0x00200000
+#define MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_MASK) >> MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_LSB)
+#define MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_LSB) & MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_MASK)
+#define MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_MSB 20
+#define MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_LSB 20
+#define MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_MASK 0x00100000
+#define MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_MASK) >> MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_LSB)
+#define MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_LSB) & MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_MASK)
+#define MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_MSB 19
+#define MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_LSB 19
+#define MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_MASK 0x00080000
+#define MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_MASK) >> MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_LSB)
+#define MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_LSB) & MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_MASK)
+#define MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_MSB 17
+#define MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_LSB 17
+#define MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_MASK 0x00020000
+#define MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_MASK) >> MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_LSB)
+#define MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_LSB) & MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_MASK)
+#define MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_MSB 16
+#define MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_LSB 16
+#define MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_MASK 0x00010000
+#define MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_MASK) >> MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_LSB)
+#define MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_LSB) & MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_MASK)
+#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_MSB 15
+#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_LSB 8
+#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_MASK 0x0000ff00
+#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_MASK) >> MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_LSB)
+#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_LSB) & MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_MASK)
+#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_MSB 7
+#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_LSB 0
+#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_MASK 0x000000ff
+#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_MASK) >> MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_LSB)
+#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_LSB) & MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_MASK)
+
+#define MAC_PCU_TXSIFS_ADDRESS                   0x000080f8
+#define MAC_PCU_TXSIFS_OFFSET                    0x000000f8
+#define MAC_PCU_TXSIFS_ACK_SHIFT_MSB             14
+#define MAC_PCU_TXSIFS_ACK_SHIFT_LSB             12
+#define MAC_PCU_TXSIFS_ACK_SHIFT_MASK            0x00007000
+#define MAC_PCU_TXSIFS_ACK_SHIFT_GET(x)          (((x) & MAC_PCU_TXSIFS_ACK_SHIFT_MASK) >> MAC_PCU_TXSIFS_ACK_SHIFT_LSB)
+#define MAC_PCU_TXSIFS_ACK_SHIFT_SET(x)          (((x) << MAC_PCU_TXSIFS_ACK_SHIFT_LSB) & MAC_PCU_TXSIFS_ACK_SHIFT_MASK)
+#define MAC_PCU_TXSIFS_TX_LATENCY_MSB            11
+#define MAC_PCU_TXSIFS_TX_LATENCY_LSB            8
+#define MAC_PCU_TXSIFS_TX_LATENCY_MASK           0x00000f00
+#define MAC_PCU_TXSIFS_TX_LATENCY_GET(x)         (((x) & MAC_PCU_TXSIFS_TX_LATENCY_MASK) >> MAC_PCU_TXSIFS_TX_LATENCY_LSB)
+#define MAC_PCU_TXSIFS_TX_LATENCY_SET(x)         (((x) << MAC_PCU_TXSIFS_TX_LATENCY_LSB) & MAC_PCU_TXSIFS_TX_LATENCY_MASK)
+#define MAC_PCU_TXSIFS_SIFS_TIME_MSB             7
+#define MAC_PCU_TXSIFS_SIFS_TIME_LSB             0
+#define MAC_PCU_TXSIFS_SIFS_TIME_MASK            0x000000ff
+#define MAC_PCU_TXSIFS_SIFS_TIME_GET(x)          (((x) & MAC_PCU_TXSIFS_SIFS_TIME_MASK) >> MAC_PCU_TXSIFS_SIFS_TIME_LSB)
+#define MAC_PCU_TXSIFS_SIFS_TIME_SET(x)          (((x) << MAC_PCU_TXSIFS_SIFS_TIME_LSB) & MAC_PCU_TXSIFS_SIFS_TIME_MASK)
+
+#define MAC_PCU_TXOP_X_ADDRESS                   0x000080fc
+#define MAC_PCU_TXOP_X_OFFSET                    0x000000fc
+#define MAC_PCU_TXOP_X_VALUE_MSB                 7
+#define MAC_PCU_TXOP_X_VALUE_LSB                 0
+#define MAC_PCU_TXOP_X_VALUE_MASK                0x000000ff
+#define MAC_PCU_TXOP_X_VALUE_GET(x)              (((x) & MAC_PCU_TXOP_X_VALUE_MASK) >> MAC_PCU_TXOP_X_VALUE_LSB)
+#define MAC_PCU_TXOP_X_VALUE_SET(x)              (((x) << MAC_PCU_TXOP_X_VALUE_LSB) & MAC_PCU_TXOP_X_VALUE_MASK)
+
+#define MAC_PCU_TXOP_0_3_ADDRESS                 0x00008100
+#define MAC_PCU_TXOP_0_3_OFFSET                  0x00000100
+#define MAC_PCU_TXOP_0_3_VALUE_3_MSB             31
+#define MAC_PCU_TXOP_0_3_VALUE_3_LSB             24
+#define MAC_PCU_TXOP_0_3_VALUE_3_MASK            0xff000000
+#define MAC_PCU_TXOP_0_3_VALUE_3_GET(x)          (((x) & MAC_PCU_TXOP_0_3_VALUE_3_MASK) >> MAC_PCU_TXOP_0_3_VALUE_3_LSB)
+#define MAC_PCU_TXOP_0_3_VALUE_3_SET(x)          (((x) << MAC_PCU_TXOP_0_3_VALUE_3_LSB) & MAC_PCU_TXOP_0_3_VALUE_3_MASK)
+#define MAC_PCU_TXOP_0_3_VALUE_2_MSB             23
+#define MAC_PCU_TXOP_0_3_VALUE_2_LSB             16
+#define MAC_PCU_TXOP_0_3_VALUE_2_MASK            0x00ff0000
+#define MAC_PCU_TXOP_0_3_VALUE_2_GET(x)          (((x) & MAC_PCU_TXOP_0_3_VALUE_2_MASK) >> MAC_PCU_TXOP_0_3_VALUE_2_LSB)
+#define MAC_PCU_TXOP_0_3_VALUE_2_SET(x)          (((x) << MAC_PCU_TXOP_0_3_VALUE_2_LSB) & MAC_PCU_TXOP_0_3_VALUE_2_MASK)
+#define MAC_PCU_TXOP_0_3_VALUE_1_MSB             15
+#define MAC_PCU_TXOP_0_3_VALUE_1_LSB             8
+#define MAC_PCU_TXOP_0_3_VALUE_1_MASK            0x0000ff00
+#define MAC_PCU_TXOP_0_3_VALUE_1_GET(x)          (((x) & MAC_PCU_TXOP_0_3_VALUE_1_MASK) >> MAC_PCU_TXOP_0_3_VALUE_1_LSB)
+#define MAC_PCU_TXOP_0_3_VALUE_1_SET(x)          (((x) << MAC_PCU_TXOP_0_3_VALUE_1_LSB) & MAC_PCU_TXOP_0_3_VALUE_1_MASK)
+#define MAC_PCU_TXOP_0_3_VALUE_0_MSB             7
+#define MAC_PCU_TXOP_0_3_VALUE_0_LSB             0
+#define MAC_PCU_TXOP_0_3_VALUE_0_MASK            0x000000ff
+#define MAC_PCU_TXOP_0_3_VALUE_0_GET(x)          (((x) & MAC_PCU_TXOP_0_3_VALUE_0_MASK) >> MAC_PCU_TXOP_0_3_VALUE_0_LSB)
+#define MAC_PCU_TXOP_0_3_VALUE_0_SET(x)          (((x) << MAC_PCU_TXOP_0_3_VALUE_0_LSB) & MAC_PCU_TXOP_0_3_VALUE_0_MASK)
+
+#define MAC_PCU_TXOP_4_7_ADDRESS                 0x00008104
+#define MAC_PCU_TXOP_4_7_OFFSET                  0x00000104
+#define MAC_PCU_TXOP_4_7_VALUE_7_MSB             31
+#define MAC_PCU_TXOP_4_7_VALUE_7_LSB             24
+#define MAC_PCU_TXOP_4_7_VALUE_7_MASK            0xff000000
+#define MAC_PCU_TXOP_4_7_VALUE_7_GET(x)          (((x) & MAC_PCU_TXOP_4_7_VALUE_7_MASK) >> MAC_PCU_TXOP_4_7_VALUE_7_LSB)
+#define MAC_PCU_TXOP_4_7_VALUE_7_SET(x)          (((x) << MAC_PCU_TXOP_4_7_VALUE_7_LSB) & MAC_PCU_TXOP_4_7_VALUE_7_MASK)
+#define MAC_PCU_TXOP_4_7_VALUE_6_MSB             23
+#define MAC_PCU_TXOP_4_7_VALUE_6_LSB             16
+#define MAC_PCU_TXOP_4_7_VALUE_6_MASK            0x00ff0000
+#define MAC_PCU_TXOP_4_7_VALUE_6_GET(x)          (((x) & MAC_PCU_TXOP_4_7_VALUE_6_MASK) >> MAC_PCU_TXOP_4_7_VALUE_6_LSB)
+#define MAC_PCU_TXOP_4_7_VALUE_6_SET(x)          (((x) << MAC_PCU_TXOP_4_7_VALUE_6_LSB) & MAC_PCU_TXOP_4_7_VALUE_6_MASK)
+#define MAC_PCU_TXOP_4_7_VALUE_5_MSB             15
+#define MAC_PCU_TXOP_4_7_VALUE_5_LSB             8
+#define MAC_PCU_TXOP_4_7_VALUE_5_MASK            0x0000ff00
+#define MAC_PCU_TXOP_4_7_VALUE_5_GET(x)          (((x) & MAC_PCU_TXOP_4_7_VALUE_5_MASK) >> MAC_PCU_TXOP_4_7_VALUE_5_LSB)
+#define MAC_PCU_TXOP_4_7_VALUE_5_SET(x)          (((x) << MAC_PCU_TXOP_4_7_VALUE_5_LSB) & MAC_PCU_TXOP_4_7_VALUE_5_MASK)
+#define MAC_PCU_TXOP_4_7_VALUE_4_MSB             7
+#define MAC_PCU_TXOP_4_7_VALUE_4_LSB             0
+#define MAC_PCU_TXOP_4_7_VALUE_4_MASK            0x000000ff
+#define MAC_PCU_TXOP_4_7_VALUE_4_GET(x)          (((x) & MAC_PCU_TXOP_4_7_VALUE_4_MASK) >> MAC_PCU_TXOP_4_7_VALUE_4_LSB)
+#define MAC_PCU_TXOP_4_7_VALUE_4_SET(x)          (((x) << MAC_PCU_TXOP_4_7_VALUE_4_LSB) & MAC_PCU_TXOP_4_7_VALUE_4_MASK)
+
+#define MAC_PCU_TXOP_8_11_ADDRESS                0x00008108
+#define MAC_PCU_TXOP_8_11_OFFSET                 0x00000108
+#define MAC_PCU_TXOP_8_11_VALUE_11_MSB           31
+#define MAC_PCU_TXOP_8_11_VALUE_11_LSB           24
+#define MAC_PCU_TXOP_8_11_VALUE_11_MASK          0xff000000
+#define MAC_PCU_TXOP_8_11_VALUE_11_GET(x)        (((x) & MAC_PCU_TXOP_8_11_VALUE_11_MASK) >> MAC_PCU_TXOP_8_11_VALUE_11_LSB)
+#define MAC_PCU_TXOP_8_11_VALUE_11_SET(x)        (((x) << MAC_PCU_TXOP_8_11_VALUE_11_LSB) & MAC_PCU_TXOP_8_11_VALUE_11_MASK)
+#define MAC_PCU_TXOP_8_11_VALUE_10_MSB           23
+#define MAC_PCU_TXOP_8_11_VALUE_10_LSB           16
+#define MAC_PCU_TXOP_8_11_VALUE_10_MASK          0x00ff0000
+#define MAC_PCU_TXOP_8_11_VALUE_10_GET(x)        (((x) & MAC_PCU_TXOP_8_11_VALUE_10_MASK) >> MAC_PCU_TXOP_8_11_VALUE_10_LSB)
+#define MAC_PCU_TXOP_8_11_VALUE_10_SET(x)        (((x) << MAC_PCU_TXOP_8_11_VALUE_10_LSB) & MAC_PCU_TXOP_8_11_VALUE_10_MASK)
+#define MAC_PCU_TXOP_8_11_VALUE_9_MSB            15
+#define MAC_PCU_TXOP_8_11_VALUE_9_LSB            8
+#define MAC_PCU_TXOP_8_11_VALUE_9_MASK           0x0000ff00
+#define MAC_PCU_TXOP_8_11_VALUE_9_GET(x)         (((x) & MAC_PCU_TXOP_8_11_VALUE_9_MASK) >> MAC_PCU_TXOP_8_11_VALUE_9_LSB)
+#define MAC_PCU_TXOP_8_11_VALUE_9_SET(x)         (((x) << MAC_PCU_TXOP_8_11_VALUE_9_LSB) & MAC_PCU_TXOP_8_11_VALUE_9_MASK)
+#define MAC_PCU_TXOP_8_11_VALUE_8_MSB            7
+#define MAC_PCU_TXOP_8_11_VALUE_8_LSB            0
+#define MAC_PCU_TXOP_8_11_VALUE_8_MASK           0x000000ff
+#define MAC_PCU_TXOP_8_11_VALUE_8_GET(x)         (((x) & MAC_PCU_TXOP_8_11_VALUE_8_MASK) >> MAC_PCU_TXOP_8_11_VALUE_8_LSB)
+#define MAC_PCU_TXOP_8_11_VALUE_8_SET(x)         (((x) << MAC_PCU_TXOP_8_11_VALUE_8_LSB) & MAC_PCU_TXOP_8_11_VALUE_8_MASK)
+
+#define MAC_PCU_TXOP_12_15_ADDRESS               0x0000810c
+#define MAC_PCU_TXOP_12_15_OFFSET                0x0000010c
+#define MAC_PCU_TXOP_12_15_VALUE_15_MSB          31
+#define MAC_PCU_TXOP_12_15_VALUE_15_LSB          24
+#define MAC_PCU_TXOP_12_15_VALUE_15_MASK         0xff000000
+#define MAC_PCU_TXOP_12_15_VALUE_15_GET(x)       (((x) & MAC_PCU_TXOP_12_15_VALUE_15_MASK) >> MAC_PCU_TXOP_12_15_VALUE_15_LSB)
+#define MAC_PCU_TXOP_12_15_VALUE_15_SET(x)       (((x) << MAC_PCU_TXOP_12_15_VALUE_15_LSB) & MAC_PCU_TXOP_12_15_VALUE_15_MASK)
+#define MAC_PCU_TXOP_12_15_VALUE_14_MSB          23
+#define MAC_PCU_TXOP_12_15_VALUE_14_LSB          16
+#define MAC_PCU_TXOP_12_15_VALUE_14_MASK         0x00ff0000
+#define MAC_PCU_TXOP_12_15_VALUE_14_GET(x)       (((x) & MAC_PCU_TXOP_12_15_VALUE_14_MASK) >> MAC_PCU_TXOP_12_15_VALUE_14_LSB)
+#define MAC_PCU_TXOP_12_15_VALUE_14_SET(x)       (((x) << MAC_PCU_TXOP_12_15_VALUE_14_LSB) & MAC_PCU_TXOP_12_15_VALUE_14_MASK)
+#define MAC_PCU_TXOP_12_15_VALUE_13_MSB          15
+#define MAC_PCU_TXOP_12_15_VALUE_13_LSB          8
+#define MAC_PCU_TXOP_12_15_VALUE_13_MASK         0x0000ff00
+#define MAC_PCU_TXOP_12_15_VALUE_13_GET(x)       (((x) & MAC_PCU_TXOP_12_15_VALUE_13_MASK) >> MAC_PCU_TXOP_12_15_VALUE_13_LSB)
+#define MAC_PCU_TXOP_12_15_VALUE_13_SET(x)       (((x) << MAC_PCU_TXOP_12_15_VALUE_13_LSB) & MAC_PCU_TXOP_12_15_VALUE_13_MASK)
+#define MAC_PCU_TXOP_12_15_VALUE_12_MSB          7
+#define MAC_PCU_TXOP_12_15_VALUE_12_LSB          0
+#define MAC_PCU_TXOP_12_15_VALUE_12_MASK         0x000000ff
+#define MAC_PCU_TXOP_12_15_VALUE_12_GET(x)       (((x) & MAC_PCU_TXOP_12_15_VALUE_12_MASK) >> MAC_PCU_TXOP_12_15_VALUE_12_LSB)
+#define MAC_PCU_TXOP_12_15_VALUE_12_SET(x)       (((x) << MAC_PCU_TXOP_12_15_VALUE_12_LSB) & MAC_PCU_TXOP_12_15_VALUE_12_MASK)
+
+#define MAC_PCU_LOGIC_ANALYZER_ADDRESS           0x00008110
+#define MAC_PCU_LOGIC_ANALYZER_OFFSET            0x00000110
+#define MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_MSB     31
+#define MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_LSB     18
+#define MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_MASK    0xfffc0000
+#define MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_GET(x)  (((x) & MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_MASK) >> MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_LSB)
+#define MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_SET(x)  (((x) << MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_LSB) & MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_MASK)
+#define MAC_PCU_LOGIC_ANALYZER_INT_ADDR_MSB      17
+#define MAC_PCU_LOGIC_ANALYZER_INT_ADDR_LSB      8
+#define MAC_PCU_LOGIC_ANALYZER_INT_ADDR_MASK     0x0003ff00
+#define MAC_PCU_LOGIC_ANALYZER_INT_ADDR_GET(x)   (((x) & MAC_PCU_LOGIC_ANALYZER_INT_ADDR_MASK) >> MAC_PCU_LOGIC_ANALYZER_INT_ADDR_LSB)
+#define MAC_PCU_LOGIC_ANALYZER_INT_ADDR_SET(x)   (((x) << MAC_PCU_LOGIC_ANALYZER_INT_ADDR_LSB) & MAC_PCU_LOGIC_ANALYZER_INT_ADDR_MASK)
+#define MAC_PCU_LOGIC_ANALYZER_QCU_SEL_MSB       7
+#define MAC_PCU_LOGIC_ANALYZER_QCU_SEL_LSB       4
+#define MAC_PCU_LOGIC_ANALYZER_QCU_SEL_MASK      0x000000f0
+#define MAC_PCU_LOGIC_ANALYZER_QCU_SEL_GET(x)    (((x) & MAC_PCU_LOGIC_ANALYZER_QCU_SEL_MASK) >> MAC_PCU_LOGIC_ANALYZER_QCU_SEL_LSB)
+#define MAC_PCU_LOGIC_ANALYZER_QCU_SEL_SET(x)    (((x) << MAC_PCU_LOGIC_ANALYZER_QCU_SEL_LSB) & MAC_PCU_LOGIC_ANALYZER_QCU_SEL_MASK)
+#define MAC_PCU_LOGIC_ANALYZER_ENABLE_MSB        3
+#define MAC_PCU_LOGIC_ANALYZER_ENABLE_LSB        3
+#define MAC_PCU_LOGIC_ANALYZER_ENABLE_MASK       0x00000008
+#define MAC_PCU_LOGIC_ANALYZER_ENABLE_GET(x)     (((x) & MAC_PCU_LOGIC_ANALYZER_ENABLE_MASK) >> MAC_PCU_LOGIC_ANALYZER_ENABLE_LSB)
+#define MAC_PCU_LOGIC_ANALYZER_ENABLE_SET(x)     (((x) << MAC_PCU_LOGIC_ANALYZER_ENABLE_LSB) & MAC_PCU_LOGIC_ANALYZER_ENABLE_MASK)
+#define MAC_PCU_LOGIC_ANALYZER_STATE_MSB         2
+#define MAC_PCU_LOGIC_ANALYZER_STATE_LSB         2
+#define MAC_PCU_LOGIC_ANALYZER_STATE_MASK        0x00000004
+#define MAC_PCU_LOGIC_ANALYZER_STATE_GET(x)      (((x) & MAC_PCU_LOGIC_ANALYZER_STATE_MASK) >> MAC_PCU_LOGIC_ANALYZER_STATE_LSB)
+#define MAC_PCU_LOGIC_ANALYZER_STATE_SET(x)      (((x) << MAC_PCU_LOGIC_ANALYZER_STATE_LSB) & MAC_PCU_LOGIC_ANALYZER_STATE_MASK)
+#define MAC_PCU_LOGIC_ANALYZER_CLEAR_MSB         1
+#define MAC_PCU_LOGIC_ANALYZER_CLEAR_LSB         1
+#define MAC_PCU_LOGIC_ANALYZER_CLEAR_MASK        0x00000002
+#define MAC_PCU_LOGIC_ANALYZER_CLEAR_GET(x)      (((x) & MAC_PCU_LOGIC_ANALYZER_CLEAR_MASK) >> MAC_PCU_LOGIC_ANALYZER_CLEAR_LSB)
+#define MAC_PCU_LOGIC_ANALYZER_CLEAR_SET(x)      (((x) << MAC_PCU_LOGIC_ANALYZER_CLEAR_LSB) & MAC_PCU_LOGIC_ANALYZER_CLEAR_MASK)
+#define MAC_PCU_LOGIC_ANALYZER_HOLD_MSB          0
+#define MAC_PCU_LOGIC_ANALYZER_HOLD_LSB          0
+#define MAC_PCU_LOGIC_ANALYZER_HOLD_MASK         0x00000001
+#define MAC_PCU_LOGIC_ANALYZER_HOLD_GET(x)       (((x) & MAC_PCU_LOGIC_ANALYZER_HOLD_MASK) >> MAC_PCU_LOGIC_ANALYZER_HOLD_LSB)
+#define MAC_PCU_LOGIC_ANALYZER_HOLD_SET(x)       (((x) << MAC_PCU_LOGIC_ANALYZER_HOLD_LSB) & MAC_PCU_LOGIC_ANALYZER_HOLD_MASK)
+
+#define MAC_PCU_LOGIC_ANALYZER_32L_ADDRESS       0x00008114
+#define MAC_PCU_LOGIC_ANALYZER_32L_OFFSET        0x00000114
+#define MAC_PCU_LOGIC_ANALYZER_32L_MASK_MSB      31
+#define MAC_PCU_LOGIC_ANALYZER_32L_MASK_LSB      0
+#define MAC_PCU_LOGIC_ANALYZER_32L_MASK_MASK     0xffffffff
+#define MAC_PCU_LOGIC_ANALYZER_32L_MASK_GET(x)   (((x) & MAC_PCU_LOGIC_ANALYZER_32L_MASK_MASK) >> MAC_PCU_LOGIC_ANALYZER_32L_MASK_LSB)
+#define MAC_PCU_LOGIC_ANALYZER_32L_MASK_SET(x)   (((x) << MAC_PCU_LOGIC_ANALYZER_32L_MASK_LSB) & MAC_PCU_LOGIC_ANALYZER_32L_MASK_MASK)
+
+#define MAC_PCU_LOGIC_ANALYZER_16U_ADDRESS       0x00008118
+#define MAC_PCU_LOGIC_ANALYZER_16U_OFFSET        0x00000118
+#define MAC_PCU_LOGIC_ANALYZER_16U_MASK_MSB      15
+#define MAC_PCU_LOGIC_ANALYZER_16U_MASK_LSB      0
+#define MAC_PCU_LOGIC_ANALYZER_16U_MASK_MASK     0x0000ffff
+#define MAC_PCU_LOGIC_ANALYZER_16U_MASK_GET(x)   (((x) & MAC_PCU_LOGIC_ANALYZER_16U_MASK_MASK) >> MAC_PCU_LOGIC_ANALYZER_16U_MASK_LSB)
+#define MAC_PCU_LOGIC_ANALYZER_16U_MASK_SET(x)   (((x) << MAC_PCU_LOGIC_ANALYZER_16U_MASK_LSB) & MAC_PCU_LOGIC_ANALYZER_16U_MASK_MASK)
+
+#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_ADDRESS    0x0000811c
+#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_OFFSET     0x0000011c
+#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_MSB  23
+#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_LSB  16
+#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_MASK 0x00ff0000
+#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_GET(x) (((x) & MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_MASK) >> MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_LSB)
+#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_SET(x) (((x) << MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_LSB) & MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_MASK)
+#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_MSB  15
+#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_LSB  8
+#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_MASK 0x0000ff00
+#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_GET(x) (((x) & MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_MASK) >> MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_LSB)
+#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_SET(x) (((x) << MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_LSB) & MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_MASK)
+#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_MSB  7
+#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_LSB  0
+#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_MASK 0x000000ff
+#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_GET(x) (((x) & MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_MASK) >> MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_LSB)
+#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_SET(x) (((x) << MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_LSB) & MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_MASK)
+
+#define MAC_PCU_AZIMUTH_MODE_ADDRESS             0x00008120
+#define MAC_PCU_AZIMUTH_MODE_OFFSET              0x00000120
+#define MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_MSB     7
+#define MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_LSB     7
+#define MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_MASK    0x00000080
+#define MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_GET(x)  (((x) & MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_MASK) >> MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_LSB)
+#define MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_SET(x)  (((x) << MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_LSB) & MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_MASK)
+#define MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_MSB 6
+#define MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_LSB 6
+#define MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_MASK 0x00000040
+#define MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_GET(x) (((x) & MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_MASK) >> MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_LSB)
+#define MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_SET(x) (((x) << MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_LSB) & MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_MASK)
+#define MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_MSB      5
+#define MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_LSB      5
+#define MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_MASK     0x00000020
+#define MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_GET(x)   (((x) & MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_MASK) >> MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_LSB)
+#define MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_SET(x)   (((x) << MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_LSB) & MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_MASK)
+#define MAC_PCU_AZIMUTH_MODE_CLK_EN_MSB          4
+#define MAC_PCU_AZIMUTH_MODE_CLK_EN_LSB          4
+#define MAC_PCU_AZIMUTH_MODE_CLK_EN_MASK         0x00000010
+#define MAC_PCU_AZIMUTH_MODE_CLK_EN_GET(x)       (((x) & MAC_PCU_AZIMUTH_MODE_CLK_EN_MASK) >> MAC_PCU_AZIMUTH_MODE_CLK_EN_LSB)
+#define MAC_PCU_AZIMUTH_MODE_CLK_EN_SET(x)       (((x) << MAC_PCU_AZIMUTH_MODE_CLK_EN_LSB) & MAC_PCU_AZIMUTH_MODE_CLK_EN_MASK)
+#define MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_MSB 3
+#define MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_LSB 3
+#define MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_MASK 0x00000008
+#define MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_GET(x) (((x) & MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_MASK) >> MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_LSB)
+#define MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_SET(x) (((x) << MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_LSB) & MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_MASK)
+#define MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_MSB 2
+#define MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_LSB 2
+#define MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_MASK 0x00000004
+#define MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_GET(x) (((x) & MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_MASK) >> MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_LSB)
+#define MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_SET(x) (((x) << MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_LSB) & MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_MASK)
+#define MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_MSB  1
+#define MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_LSB  1
+#define MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_MASK 0x00000002
+#define MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_GET(x) (((x) & MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_MASK) >> MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_LSB)
+#define MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_SET(x) (((x) << MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_LSB) & MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_MASK)
+#define MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_MSB 0
+#define MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_LSB 0
+#define MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_MASK 0x00000001
+#define MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_GET(x) (((x) & MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_MASK) >> MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_LSB)
+#define MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_SET(x) (((x) << MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_LSB) & MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_MASK)
+
+#define MAC_PCU_20_40_MODE_ADDRESS               0x00008124
+#define MAC_PCU_20_40_MODE_OFFSET                0x00000124
+#define MAC_PCU_20_40_MODE_PIFS_CYCLES_MSB       15
+#define MAC_PCU_20_40_MODE_PIFS_CYCLES_LSB       4
+#define MAC_PCU_20_40_MODE_PIFS_CYCLES_MASK      0x0000fff0
+#define MAC_PCU_20_40_MODE_PIFS_CYCLES_GET(x)    (((x) & MAC_PCU_20_40_MODE_PIFS_CYCLES_MASK) >> MAC_PCU_20_40_MODE_PIFS_CYCLES_LSB)
+#define MAC_PCU_20_40_MODE_PIFS_CYCLES_SET(x)    (((x) << MAC_PCU_20_40_MODE_PIFS_CYCLES_LSB) & MAC_PCU_20_40_MODE_PIFS_CYCLES_MASK)
+#define MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_MSB 3
+#define MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_LSB 3
+#define MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_MASK 0x00000008
+#define MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_GET(x) (((x) & MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_MASK) >> MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_LSB)
+#define MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_SET(x) (((x) << MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_LSB) & MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_MASK)
+#define MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_MSB 2
+#define MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_LSB 2
+#define MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_MASK 0x00000004
+#define MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_GET(x) (((x) & MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_MASK) >> MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_LSB)
+#define MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_SET(x) (((x) << MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_LSB) & MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_MASK)
+#define MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_MSB   1
+#define MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_LSB   1
+#define MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_MASK  0x00000002
+#define MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_GET(x) (((x) & MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_MASK) >> MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_LSB)
+#define MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_SET(x) (((x) << MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_LSB) & MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_MASK)
+#define MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_MSB   0
+#define MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_LSB   0
+#define MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_MASK  0x00000001
+#define MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_GET(x) (((x) & MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_MASK) >> MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_LSB)
+#define MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_SET(x) (((x) << MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_LSB) & MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_MASK)
+
+#define MAC_PCU_RX_CLEAR_DIFF_CNT_ADDRESS        0x00008128
+#define MAC_PCU_RX_CLEAR_DIFF_CNT_OFFSET         0x00000128
+#define MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_MSB      31
+#define MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_LSB      0
+#define MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_MASK     0xffffffff
+#define MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_GET(x)   (((x) & MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_MASK) >> MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_LSB)
+#define MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_SET(x)   (((x) << MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_LSB) & MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_MASK)
+
+#define MAC_PCU_SELF_GEN_ANTENNA_MASK_ADDRESS    0x0000812c
+#define MAC_PCU_SELF_GEN_ANTENNA_MASK_OFFSET     0x0000012c
+#define MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_MSB  2
+#define MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_LSB  0
+#define MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_MASK 0x00000007
+#define MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_GET(x) (((x) & MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_MASK) >> MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_LSB)
+#define MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_SET(x) (((x) << MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_LSB) & MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_MASK)
+
+#define MAC_PCU_BA_BAR_CONTROL_ADDRESS           0x00008130
+#define MAC_PCU_BA_BAR_CONTROL_OFFSET            0x00000130
+#define MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_MSB 12
+#define MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_LSB 12
+#define MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_MASK 0x00001000
+#define MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_GET(x) (((x) & MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_MASK) >> MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_LSB)
+#define MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_SET(x) (((x) << MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_LSB) & MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_MASK)
+#define MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_MSB 11
+#define MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_LSB 11
+#define MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_MASK 0x00000800
+#define MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_GET(x) (((x) & MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_MASK) >> MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_LSB)
+#define MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_SET(x) (((x) << MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_LSB) & MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_MASK)
+#define MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_MSB 10
+#define MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_LSB 10
+#define MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_MASK 0x00000400
+#define MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_GET(x) (((x) & MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_MASK) >> MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_LSB)
+#define MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_SET(x) (((x) << MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_LSB) & MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_MASK)
+#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_MSB 9
+#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_LSB 9
+#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_MASK 0x00000200
+#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_GET(x) (((x) & MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_MASK) >> MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_LSB)
+#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_SET(x) (((x) << MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_LSB) & MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_MASK)
+#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_MSB 8
+#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_LSB 8
+#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_MASK 0x00000100
+#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_GET(x) (((x) & MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_MASK) >> MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_LSB)
+#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_SET(x) (((x) << MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_LSB) & MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_MASK)
+#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_MSB 7
+#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_LSB 4
+#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_MASK 0x000000f0
+#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_GET(x) (((x) & MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_MASK) >> MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_LSB)
+#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_SET(x) (((x) << MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_LSB) & MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_MASK)
+#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_MSB 3
+#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_LSB 0
+#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_MASK 0x0000000f
+#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_GET(x) (((x) & MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_MASK) >> MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_LSB)
+#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_SET(x) (((x) << MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_LSB) & MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_MASK)
+
+#define MAC_PCU_LEGACY_PLCP_SPOOF_ADDRESS        0x00008134
+#define MAC_PCU_LEGACY_PLCP_SPOOF_OFFSET         0x00000134
+#define MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_MSB 12
+#define MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_LSB 8
+#define MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_MASK 0x00001f00
+#define MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_GET(x) (((x) & MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_MASK) >> MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_LSB)
+#define MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_SET(x) (((x) << MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_LSB) & MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_MASK)
+#define MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_MSB 7
+#define MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_LSB 0
+#define MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_MASK 0x000000ff
+#define MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_GET(x) (((x) & MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_MASK) >> MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_LSB)
+#define MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_SET(x) (((x) << MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_LSB) & MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_MASK)
+
+#define MAC_PCU_PHY_ERROR_MASK_CONT_ADDRESS      0x00008138
+#define MAC_PCU_PHY_ERROR_MASK_CONT_OFFSET       0x00000138
+#define MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_MSB 23
+#define MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_LSB 16
+#define MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_MASK 0x00ff0000
+#define MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_MASK) >> MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_LSB)
+#define MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_LSB) & MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_MASK)
+#define MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_MSB 7
+#define MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_LSB 0
+#define MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_MASK 0x000000ff
+#define MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_MASK) >> MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_LSB)
+#define MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_LSB) & MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_MASK)
+
+#define MAC_PCU_TX_TIMER_ADDRESS                 0x0000813c
+#define MAC_PCU_TX_TIMER_OFFSET                  0x0000013c
+#define MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_MSB  25
+#define MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_LSB  25
+#define MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_MASK 0x02000000
+#define MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_GET(x) (((x) & MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_MASK) >> MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_LSB)
+#define MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_SET(x) (((x) << MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_LSB) & MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_MASK)
+#define MAC_PCU_TX_TIMER_QUIET_TIMER_MSB         24
+#define MAC_PCU_TX_TIMER_QUIET_TIMER_LSB         20
+#define MAC_PCU_TX_TIMER_QUIET_TIMER_MASK        0x01f00000
+#define MAC_PCU_TX_TIMER_QUIET_TIMER_GET(x)      (((x) & MAC_PCU_TX_TIMER_QUIET_TIMER_MASK) >> MAC_PCU_TX_TIMER_QUIET_TIMER_LSB)
+#define MAC_PCU_TX_TIMER_QUIET_TIMER_SET(x)      (((x) << MAC_PCU_TX_TIMER_QUIET_TIMER_LSB) & MAC_PCU_TX_TIMER_QUIET_TIMER_MASK)
+#define MAC_PCU_TX_TIMER_RIFS_TIMER_MSB          19
+#define MAC_PCU_TX_TIMER_RIFS_TIMER_LSB          16
+#define MAC_PCU_TX_TIMER_RIFS_TIMER_MASK         0x000f0000
+#define MAC_PCU_TX_TIMER_RIFS_TIMER_GET(x)       (((x) & MAC_PCU_TX_TIMER_RIFS_TIMER_MASK) >> MAC_PCU_TX_TIMER_RIFS_TIMER_LSB)
+#define MAC_PCU_TX_TIMER_RIFS_TIMER_SET(x)       (((x) << MAC_PCU_TX_TIMER_RIFS_TIMER_LSB) & MAC_PCU_TX_TIMER_RIFS_TIMER_MASK)
+#define MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_MSB     15
+#define MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_LSB     15
+#define MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_MASK    0x00008000
+#define MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_GET(x)  (((x) & MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_MASK) >> MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_LSB)
+#define MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_SET(x)  (((x) << MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_LSB) & MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_MASK)
+#define MAC_PCU_TX_TIMER_TX_TIMER_MSB            14
+#define MAC_PCU_TX_TIMER_TX_TIMER_LSB            0
+#define MAC_PCU_TX_TIMER_TX_TIMER_MASK           0x00007fff
+#define MAC_PCU_TX_TIMER_TX_TIMER_GET(x)         (((x) & MAC_PCU_TX_TIMER_TX_TIMER_MASK) >> MAC_PCU_TX_TIMER_TX_TIMER_LSB)
+#define MAC_PCU_TX_TIMER_TX_TIMER_SET(x)         (((x) << MAC_PCU_TX_TIMER_TX_TIMER_LSB) & MAC_PCU_TX_TIMER_TX_TIMER_MASK)
+
+#define MAC_PCU_TXBUF_CTRL_ADDRESS               0x00008140
+#define MAC_PCU_TXBUF_CTRL_OFFSET                0x00000140
+#define MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_MSB 16
+#define MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_LSB 16
+#define MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_MASK 0x00010000
+#define MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_GET(x) (((x) & MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_MASK) >> MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_LSB)
+#define MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_SET(x) (((x) << MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_LSB) & MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_MASK)
+#define MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_MSB    11
+#define MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_LSB    0
+#define MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_MASK   0x00000fff
+#define MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_GET(x) (((x) & MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_MASK) >> MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_LSB)
+#define MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_SET(x) (((x) << MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_LSB) & MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_MASK)
+
+#define MAC_PCU_MISC_MODE2_ADDRESS               0x00008144
+#define MAC_PCU_MISC_MODE2_OFFSET                0x00000144
+#define MAC_PCU_MISC_MODE2_RESERVED_1_MSB        31
+#define MAC_PCU_MISC_MODE2_RESERVED_1_LSB        28
+#define MAC_PCU_MISC_MODE2_RESERVED_1_MASK       0xf0000000
+#define MAC_PCU_MISC_MODE2_RESERVED_1_GET(x)     (((x) & MAC_PCU_MISC_MODE2_RESERVED_1_MASK) >> MAC_PCU_MISC_MODE2_RESERVED_1_LSB)
+#define MAC_PCU_MISC_MODE2_RESERVED_1_SET(x)     (((x) << MAC_PCU_MISC_MODE2_RESERVED_1_LSB) & MAC_PCU_MISC_MODE2_RESERVED_1_MASK)
+#define MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_MSB 27
+#define MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_LSB 27
+#define MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_MASK 0x08000000
+#define MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_GET(x) (((x) & MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_MASK) >> MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_LSB)
+#define MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_SET(x) (((x) << MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_LSB) & MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_MASK)
+#define MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_MSB 26
+#define MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_LSB 26
+#define MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_MASK 0x04000000
+#define MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_GET(x) (((x) & MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_MASK) >> MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_LSB)
+#define MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_SET(x) (((x) << MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_LSB) & MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_MASK)
+#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_MSB 25
+#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_LSB 25
+#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_MASK 0x02000000
+#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_GET(x) (((x) & MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_MASK) >> MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_LSB)
+#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_SET(x) (((x) << MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_LSB) & MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_MASK)
+#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_MSB  24
+#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_LSB  24
+#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_MASK 0x01000000
+#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_GET(x) (((x) & MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_MASK) >> MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_LSB)
+#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_SET(x) (((x) << MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_LSB) & MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_MASK)
+#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_MSB 23
+#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_LSB 23
+#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_MASK 0x00800000
+#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_GET(x) (((x) & MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_MASK) >> MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_LSB)
+#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_SET(x) (((x) << MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_LSB) & MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_MASK)
+#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_MSB 22
+#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_LSB 22
+#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_MASK 0x00400000
+#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_GET(x) (((x) & MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_MASK) >> MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_LSB)
+#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_SET(x) (((x) << MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_LSB) & MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_MASK)
+#define MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_MSB   21
+#define MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_LSB   21
+#define MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_MASK  0x00200000
+#define MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_GET(x) (((x) & MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_MASK) >> MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_LSB)
+#define MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_SET(x) (((x) << MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_LSB) & MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_MASK)
+#define MAC_PCU_MISC_MODE2_BUG_28676_MSB         20
+#define MAC_PCU_MISC_MODE2_BUG_28676_LSB         20
+#define MAC_PCU_MISC_MODE2_BUG_28676_MASK        0x00100000
+#define MAC_PCU_MISC_MODE2_BUG_28676_GET(x)      (((x) & MAC_PCU_MISC_MODE2_BUG_28676_MASK) >> MAC_PCU_MISC_MODE2_BUG_28676_LSB)
+#define MAC_PCU_MISC_MODE2_BUG_28676_SET(x)      (((x) << MAC_PCU_MISC_MODE2_BUG_28676_LSB) & MAC_PCU_MISC_MODE2_BUG_28676_MASK)
+#define MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_MSB 19
+#define MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_LSB 19
+#define MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_MASK 0x00080000
+#define MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_GET(x) (((x) & MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_MASK) >> MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_LSB)
+#define MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_SET(x) (((x) << MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_LSB) & MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_MASK)
+#define MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_MSB   18
+#define MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_LSB   18
+#define MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_MASK  0x00040000
+#define MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_GET(x) (((x) & MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_MASK) >> MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_LSB)
+#define MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_SET(x) (((x) << MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_LSB) & MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_MASK)
+#define MAC_PCU_MISC_MODE2_AGG_WEP_MSB           17
+#define MAC_PCU_MISC_MODE2_AGG_WEP_LSB           17
+#define MAC_PCU_MISC_MODE2_AGG_WEP_MASK          0x00020000
+#define MAC_PCU_MISC_MODE2_AGG_WEP_GET(x)        (((x) & MAC_PCU_MISC_MODE2_AGG_WEP_MASK) >> MAC_PCU_MISC_MODE2_AGG_WEP_LSB)
+#define MAC_PCU_MISC_MODE2_AGG_WEP_SET(x)        (((x) << MAC_PCU_MISC_MODE2_AGG_WEP_LSB) & MAC_PCU_MISC_MODE2_AGG_WEP_MASK)
+#define MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_MSB 16
+#define MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_LSB 16
+#define MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_MASK 0x00010000
+#define MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_GET(x) (((x) & MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_MASK) >> MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_LSB)
+#define MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_SET(x) (((x) << MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_LSB) & MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_MASK)
+#define MAC_PCU_MISC_MODE2_MGMT_QOS_MSB          15
+#define MAC_PCU_MISC_MODE2_MGMT_QOS_LSB          8
+#define MAC_PCU_MISC_MODE2_MGMT_QOS_MASK         0x0000ff00
+#define MAC_PCU_MISC_MODE2_MGMT_QOS_GET(x)       (((x) & MAC_PCU_MISC_MODE2_MGMT_QOS_MASK) >> MAC_PCU_MISC_MODE2_MGMT_QOS_LSB)
+#define MAC_PCU_MISC_MODE2_MGMT_QOS_SET(x)       (((x) << MAC_PCU_MISC_MODE2_MGMT_QOS_LSB) & MAC_PCU_MISC_MODE2_MGMT_QOS_MASK)
+#define MAC_PCU_MISC_MODE2_CFP_IGNORE_MSB        7
+#define MAC_PCU_MISC_MODE2_CFP_IGNORE_LSB        7
+#define MAC_PCU_MISC_MODE2_CFP_IGNORE_MASK       0x00000080
+#define MAC_PCU_MISC_MODE2_CFP_IGNORE_GET(x)     (((x) & MAC_PCU_MISC_MODE2_CFP_IGNORE_MASK) >> MAC_PCU_MISC_MODE2_CFP_IGNORE_LSB)
+#define MAC_PCU_MISC_MODE2_CFP_IGNORE_SET(x)     (((x) << MAC_PCU_MISC_MODE2_CFP_IGNORE_LSB) & MAC_PCU_MISC_MODE2_CFP_IGNORE_MASK)
+#define MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_MSB 6
+#define MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_LSB 6
+#define MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_MASK 0x00000040
+#define MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_GET(x) (((x) & MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_MASK) >> MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_LSB)
+#define MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_SET(x) (((x) << MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_LSB) & MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_MASK)
+#define MAC_PCU_MISC_MODE2_RESERVED_2_MSB        5
+#define MAC_PCU_MISC_MODE2_RESERVED_2_LSB        5
+#define MAC_PCU_MISC_MODE2_RESERVED_2_MASK       0x00000020
+#define MAC_PCU_MISC_MODE2_RESERVED_2_GET(x)     (((x) & MAC_PCU_MISC_MODE2_RESERVED_2_MASK) >> MAC_PCU_MISC_MODE2_RESERVED_2_LSB)
+#define MAC_PCU_MISC_MODE2_RESERVED_2_SET(x)     (((x) << MAC_PCU_MISC_MODE2_RESERVED_2_LSB) & MAC_PCU_MISC_MODE2_RESERVED_2_MASK)
+#define MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_MSB 4
+#define MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_LSB 4
+#define MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_MASK 0x00000010
+#define MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_GET(x) (((x) & MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_MASK) >> MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_LSB)
+#define MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_SET(x) (((x) << MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_LSB) & MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_MASK)
+#define MAC_PCU_MISC_MODE2_RESERVED_0_MSB        3
+#define MAC_PCU_MISC_MODE2_RESERVED_0_LSB        3
+#define MAC_PCU_MISC_MODE2_RESERVED_0_MASK       0x00000008
+#define MAC_PCU_MISC_MODE2_RESERVED_0_GET(x)     (((x) & MAC_PCU_MISC_MODE2_RESERVED_0_MASK) >> MAC_PCU_MISC_MODE2_RESERVED_0_LSB)
+#define MAC_PCU_MISC_MODE2_RESERVED_0_SET(x)     (((x) << MAC_PCU_MISC_MODE2_RESERVED_0_LSB) & MAC_PCU_MISC_MODE2_RESERVED_0_MASK)
+#define MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_MSB 2
+#define MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_LSB 2
+#define MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_MASK 0x00000004
+#define MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_GET(x) (((x) & MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_MASK) >> MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_LSB)
+#define MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_SET(x) (((x) << MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_LSB) & MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_MASK)
+#define MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_MSB 1
+#define MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_LSB 1
+#define MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_MASK 0x00000002
+#define MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_GET(x) (((x) & MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_MASK) >> MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_LSB)
+#define MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_SET(x) (((x) << MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_LSB) & MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_MASK)
+#define MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_MSB 0
+#define MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_LSB 0
+#define MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_MASK 0x00000001
+#define MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_GET(x) (((x) & MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_MASK) >> MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_LSB)
+#define MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_SET(x) (((x) << MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_LSB) & MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_MASK)
+
+#define MAC_PCU_ALT_AES_MUTE_MASK_ADDRESS        0x00008148
+#define MAC_PCU_ALT_AES_MUTE_MASK_OFFSET         0x00000148
+#define MAC_PCU_ALT_AES_MUTE_MASK_QOS_MSB        31
+#define MAC_PCU_ALT_AES_MUTE_MASK_QOS_LSB        16
+#define MAC_PCU_ALT_AES_MUTE_MASK_QOS_MASK       0xffff0000
+#define MAC_PCU_ALT_AES_MUTE_MASK_QOS_GET(x)     (((x) & MAC_PCU_ALT_AES_MUTE_MASK_QOS_MASK) >> MAC_PCU_ALT_AES_MUTE_MASK_QOS_LSB)
+#define MAC_PCU_ALT_AES_MUTE_MASK_QOS_SET(x)     (((x) << MAC_PCU_ALT_AES_MUTE_MASK_QOS_LSB) & MAC_PCU_ALT_AES_MUTE_MASK_QOS_MASK)
+
+#define MAC_PCU_AZIMUTH_TIME_STAMP_ADDRESS       0x0000814c
+#define MAC_PCU_AZIMUTH_TIME_STAMP_OFFSET        0x0000014c
+#define MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_MSB     31
+#define MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_LSB     0
+#define MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_MASK    0xffffffff
+#define MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_GET(x)  (((x) & MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_MASK) >> MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_LSB)
+#define MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_SET(x)  (((x) << MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_LSB) & MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_MASK)
+
+#define MAC_PCU_MAX_CFP_DUR_ADDRESS              0x00008150
+#define MAC_PCU_MAX_CFP_DUR_OFFSET               0x00000150
+#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_MSB 7
+#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_LSB 4
+#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_MASK 0x000000f0
+#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_GET(x) (((x) & MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_MASK) >> MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_LSB)
+#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_SET(x) (((x) << MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_LSB) & MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_MASK)
+#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_MSB 3
+#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_LSB 0
+#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_MASK 0x0000000f
+#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_GET(x) (((x) & MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_MASK) >> MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_LSB)
+#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_SET(x) (((x) << MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_LSB) & MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_MASK)
+
+#define MAC_PCU_HCF_TIMEOUT_ADDRESS              0x00008154
+#define MAC_PCU_HCF_TIMEOUT_OFFSET               0x00000154
+#define MAC_PCU_HCF_TIMEOUT_VALUE_MSB            15
+#define MAC_PCU_HCF_TIMEOUT_VALUE_LSB            0
+#define MAC_PCU_HCF_TIMEOUT_VALUE_MASK           0x0000ffff
+#define MAC_PCU_HCF_TIMEOUT_VALUE_GET(x)         (((x) & MAC_PCU_HCF_TIMEOUT_VALUE_MASK) >> MAC_PCU_HCF_TIMEOUT_VALUE_LSB)
+#define MAC_PCU_HCF_TIMEOUT_VALUE_SET(x)         (((x) << MAC_PCU_HCF_TIMEOUT_VALUE_LSB) & MAC_PCU_HCF_TIMEOUT_VALUE_MASK)
+
+#define MAC_PCU_BLUETOOTH_WEIGHTS2_ADDRESS       0x00008158
+#define MAC_PCU_BLUETOOTH_WEIGHTS2_OFFSET        0x00000158
+#define MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_MSB 31
+#define MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_LSB 16
+#define MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_MASK 0xffff0000
+#define MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_GET(x) (((x) & MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_MASK) >> MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_LSB)
+#define MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_SET(x) (((x) << MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_LSB) & MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_MASK)
+
+#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_ADDRESS  0x0000815c
+#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_OFFSET   0x0000015c
+#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_MSB 31
+#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_LSB 0
+#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_MASK 0xffffffff
+#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_GET(x) (((x) & MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_MASK) >> MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_LSB)
+#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_SET(x) (((x) << MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_LSB) & MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_MASK)
+
+#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_ADDRESS 0x00008160
+#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_OFFSET 0x00000160
+#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_MSB 31
+#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_LSB 0
+#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_MASK 0xffffffff
+#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_GET(x) (((x) & MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_MASK) >> MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_LSB)
+#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_SET(x) (((x) << MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_LSB) & MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_MASK)
+
+#define MAC_PCU_BLUETOOTH_MODE3_ADDRESS          0x00008164
+#define MAC_PCU_BLUETOOTH_MODE3_OFFSET           0x00000164
+#define MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_MSB 31
+#define MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_LSB 28
+#define MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_MASK 0xf0000000
+#define MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_MASK) >> MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_LSB)
+#define MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_LSB) & MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_MASK)
+#define MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_MSB  27
+#define MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_LSB  27
+#define MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_MASK 0x08000000
+#define MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_MASK) >> MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_LSB)
+#define MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_LSB) & MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_MASK)
+#define MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_MSB    26
+#define MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_LSB    25
+#define MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_MASK   0x06000000
+#define MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_MASK) >> MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_LSB)
+#define MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_LSB) & MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_MASK)
+#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_MSB 24
+#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_LSB 24
+#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_MASK 0x01000000
+#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_MASK) >> MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_LSB)
+#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_LSB) & MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_MASK)
+#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_MSB 23
+#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_LSB 23
+#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_MASK 0x00800000
+#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_MASK) >> MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_LSB)
+#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_LSB) & MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_MASK)
+#define MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_MSB 22
+#define MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_LSB 22
+#define MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_MASK 0x00400000
+#define MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_MASK) >> MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_LSB)
+#define MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_LSB) & MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_MASK)
+#define MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_MSB 21
+#define MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_LSB 21
+#define MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_MASK 0x00200000
+#define MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_MASK) >> MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_LSB)
+#define MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_LSB) & MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_MASK)
+#define MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_MSB    20
+#define MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_LSB    20
+#define MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_MASK   0x00100000
+#define MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_MASK) >> MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_LSB)
+#define MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_LSB) & MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_MASK)
+#define MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_MSB 19
+#define MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_LSB 16
+#define MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_MASK 0x000f0000
+#define MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_MASK) >> MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_LSB)
+#define MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_LSB) & MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_MASK)
+#define MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_MSB   15
+#define MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_LSB   8
+#define MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_MASK  0x0000ff00
+#define MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_MASK) >> MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_LSB)
+#define MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_LSB) & MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_MASK)
+#define MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_MSB 7
+#define MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_LSB 0
+#define MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_MASK 0x000000ff
+#define MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_MASK) >> MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_LSB)
+#define MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_LSB) & MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_MASK)
+
+#define MAC_PCU_BLUETOOTH_MODE4_ADDRESS          0x00008168
+#define MAC_PCU_BLUETOOTH_MODE4_OFFSET           0x00000168
+#define MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_MSB 31
+#define MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_LSB 16
+#define MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_MASK 0xffff0000
+#define MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_MASK) >> MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_LSB)
+#define MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_LSB) & MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_MASK)
+#define MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_MSB 15
+#define MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_LSB 0
+#define MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_MASK 0x0000ffff
+#define MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_MASK) >> MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_LSB)
+#define MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_LSB) & MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_MASK)
+
+#define MAC_PCU_BT_BT_ADDRESS                    0x00008200
+#define MAC_PCU_BT_BT_OFFSET                     0x00000200
+#define MAC_PCU_BT_BT_WEIGHT_MSB                 31
+#define MAC_PCU_BT_BT_WEIGHT_LSB                 0
+#define MAC_PCU_BT_BT_WEIGHT_MASK                0xffffffff
+#define MAC_PCU_BT_BT_WEIGHT_GET(x)              (((x) & MAC_PCU_BT_BT_WEIGHT_MASK) >> MAC_PCU_BT_BT_WEIGHT_LSB)
+#define MAC_PCU_BT_BT_WEIGHT_SET(x)              (((x) << MAC_PCU_BT_BT_WEIGHT_LSB) & MAC_PCU_BT_BT_WEIGHT_MASK)
+
+#define MAC_PCU_BT_BT_ASYNC_ADDRESS              0x00008300
+#define MAC_PCU_BT_BT_ASYNC_OFFSET               0x00000300
+#define MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_MSB      15
+#define MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_LSB      12
+#define MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_MASK     0x0000f000
+#define MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_GET(x)   (((x) & MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_MASK) >> MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_LSB)
+#define MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_SET(x)   (((x) << MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_LSB) & MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_MASK)
+#define MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_MSB      11
+#define MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_LSB      8
+#define MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_MASK     0x00000f00
+#define MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_GET(x)   (((x) & MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_MASK) >> MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_LSB)
+#define MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_SET(x)   (((x) << MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_LSB) & MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_MASK)
+#define MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_MSB      7
+#define MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_LSB      4
+#define MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_MASK     0x000000f0
+#define MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_GET(x)   (((x) & MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_MASK) >> MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_LSB)
+#define MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_SET(x)   (((x) << MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_LSB) & MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_MASK)
+#define MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_MSB      3
+#define MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_LSB      0
+#define MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_MASK     0x0000000f
+#define MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_GET(x)   (((x) & MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_MASK) >> MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_LSB)
+#define MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_SET(x)   (((x) << MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_LSB) & MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_MASK)
+
+#define MAC_PCU_BT_WL_1_ADDRESS                  0x00008304
+#define MAC_PCU_BT_WL_1_OFFSET                   0x00000304
+#define MAC_PCU_BT_WL_1_WEIGHT_MSB               31
+#define MAC_PCU_BT_WL_1_WEIGHT_LSB               0
+#define MAC_PCU_BT_WL_1_WEIGHT_MASK              0xffffffff
+#define MAC_PCU_BT_WL_1_WEIGHT_GET(x)            (((x) & MAC_PCU_BT_WL_1_WEIGHT_MASK) >> MAC_PCU_BT_WL_1_WEIGHT_LSB)
+#define MAC_PCU_BT_WL_1_WEIGHT_SET(x)            (((x) << MAC_PCU_BT_WL_1_WEIGHT_LSB) & MAC_PCU_BT_WL_1_WEIGHT_MASK)
+
+#define MAC_PCU_BT_WL_2_ADDRESS                  0x00008308
+#define MAC_PCU_BT_WL_2_OFFSET                   0x00000308
+#define MAC_PCU_BT_WL_2_WEIGHT_MSB               31
+#define MAC_PCU_BT_WL_2_WEIGHT_LSB               0
+#define MAC_PCU_BT_WL_2_WEIGHT_MASK              0xffffffff
+#define MAC_PCU_BT_WL_2_WEIGHT_GET(x)            (((x) & MAC_PCU_BT_WL_2_WEIGHT_MASK) >> MAC_PCU_BT_WL_2_WEIGHT_LSB)
+#define MAC_PCU_BT_WL_2_WEIGHT_SET(x)            (((x) << MAC_PCU_BT_WL_2_WEIGHT_LSB) & MAC_PCU_BT_WL_2_WEIGHT_MASK)
+
+#define MAC_PCU_BT_WL_3_ADDRESS                  0x0000830c
+#define MAC_PCU_BT_WL_3_OFFSET                   0x0000030c
+#define MAC_PCU_BT_WL_3_WEIGHT_MSB               31
+#define MAC_PCU_BT_WL_3_WEIGHT_LSB               0
+#define MAC_PCU_BT_WL_3_WEIGHT_MASK              0xffffffff
+#define MAC_PCU_BT_WL_3_WEIGHT_GET(x)            (((x) & MAC_PCU_BT_WL_3_WEIGHT_MASK) >> MAC_PCU_BT_WL_3_WEIGHT_LSB)
+#define MAC_PCU_BT_WL_3_WEIGHT_SET(x)            (((x) << MAC_PCU_BT_WL_3_WEIGHT_LSB) & MAC_PCU_BT_WL_3_WEIGHT_MASK)
+
+#define MAC_PCU_BT_WL_4_ADDRESS                  0x00008310
+#define MAC_PCU_BT_WL_4_OFFSET                   0x00000310
+#define MAC_PCU_BT_WL_4_WEIGHT_MSB               31
+#define MAC_PCU_BT_WL_4_WEIGHT_LSB               0
+#define MAC_PCU_BT_WL_4_WEIGHT_MASK              0xffffffff
+#define MAC_PCU_BT_WL_4_WEIGHT_GET(x)            (((x) & MAC_PCU_BT_WL_4_WEIGHT_MASK) >> MAC_PCU_BT_WL_4_WEIGHT_LSB)
+#define MAC_PCU_BT_WL_4_WEIGHT_SET(x)            (((x) << MAC_PCU_BT_WL_4_WEIGHT_LSB) & MAC_PCU_BT_WL_4_WEIGHT_MASK)
+
+#define MAC_PCU_COEX_EPTA_ADDRESS                0x00008314
+#define MAC_PCU_COEX_EPTA_OFFSET                 0x00000314
+#define MAC_PCU_COEX_EPTA_WT_IDX_MSB             12
+#define MAC_PCU_COEX_EPTA_WT_IDX_LSB             6
+#define MAC_PCU_COEX_EPTA_WT_IDX_MASK            0x00001fc0
+#define MAC_PCU_COEX_EPTA_WT_IDX_GET(x)          (((x) & MAC_PCU_COEX_EPTA_WT_IDX_MASK) >> MAC_PCU_COEX_EPTA_WT_IDX_LSB)
+#define MAC_PCU_COEX_EPTA_WT_IDX_SET(x)          (((x) << MAC_PCU_COEX_EPTA_WT_IDX_LSB) & MAC_PCU_COEX_EPTA_WT_IDX_MASK)
+#define MAC_PCU_COEX_EPTA_LINKID_MSB             5
+#define MAC_PCU_COEX_EPTA_LINKID_LSB             0
+#define MAC_PCU_COEX_EPTA_LINKID_MASK            0x0000003f
+#define MAC_PCU_COEX_EPTA_LINKID_GET(x)          (((x) & MAC_PCU_COEX_EPTA_LINKID_MASK) >> MAC_PCU_COEX_EPTA_LINKID_LSB)
+#define MAC_PCU_COEX_EPTA_LINKID_SET(x)          (((x) << MAC_PCU_COEX_EPTA_LINKID_LSB) & MAC_PCU_COEX_EPTA_LINKID_MASK)
+
+#define MAC_PCU_COEX_LNAMAXGAIN1_ADDRESS         0x00008318
+#define MAC_PCU_COEX_LNAMAXGAIN1_OFFSET          0x00000318
+#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_MSB    31
+#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_LSB    24
+#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_MASK   0xff000000
+#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_MASK) >> MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_LSB)
+#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_LSB) & MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_MASK)
+#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_MSB    23
+#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_LSB    16
+#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_MASK   0x00ff0000
+#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_MASK) >> MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_LSB)
+#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_LSB) & MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_MASK)
+#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_MSB    15
+#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_LSB    8
+#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_MASK   0x0000ff00
+#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_MASK) >> MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_LSB)
+#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_LSB) & MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_MASK)
+#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_MSB    7
+#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_LSB    0
+#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_MASK   0x000000ff
+#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_MASK) >> MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_LSB)
+#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_LSB) & MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_MASK)
+
+#define MAC_PCU_COEX_LNAMAXGAIN2_ADDRESS         0x0000831c
+#define MAC_PCU_COEX_LNAMAXGAIN2_OFFSET          0x0000031c
+#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_MSB    31
+#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_LSB    24
+#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_MASK   0xff000000
+#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_MASK) >> MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_LSB)
+#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_LSB) & MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_MASK)
+#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_MSB    23
+#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_LSB    16
+#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_MASK   0x00ff0000
+#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_MASK) >> MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_LSB)
+#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_LSB) & MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_MASK)
+#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_MSB    15
+#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_LSB    8
+#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_MASK   0x0000ff00
+#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_MASK) >> MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_LSB)
+#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_LSB) & MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_MASK)
+#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_MSB    7
+#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_LSB    0
+#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_MASK   0x000000ff
+#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_MASK) >> MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_LSB)
+#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_LSB) & MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_MASK)
+
+#define MAC_PCU_COEX_LNAMAXGAIN3_ADDRESS         0x00008320
+#define MAC_PCU_COEX_LNAMAXGAIN3_OFFSET          0x00000320
+#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_MSB    31
+#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_LSB    24
+#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_MASK   0xff000000
+#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_MASK) >> MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_LSB)
+#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_LSB) & MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_MASK)
+#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_MSB    23
+#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_LSB    16
+#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_MASK   0x00ff0000
+#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_MASK) >> MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_LSB)
+#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_LSB) & MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_MASK)
+#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_MSB    15
+#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_LSB    8
+#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_MASK   0x0000ff00
+#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_MASK) >> MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_LSB)
+#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_LSB) & MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_MASK)
+#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_MSB    7
+#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_LSB    0
+#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_MASK   0x000000ff
+#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_MASK) >> MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_LSB)
+#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_LSB) & MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_MASK)
+
+#define MAC_PCU_COEX_LNAMAXGAIN4_ADDRESS         0x00008324
+#define MAC_PCU_COEX_LNAMAXGAIN4_OFFSET          0x00000324
+#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_MSB    31
+#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_LSB    24
+#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_MASK   0xff000000
+#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_MASK) >> MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_LSB)
+#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_LSB) & MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_MASK)
+#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_MSB    23
+#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_LSB    16
+#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_MASK   0x00ff0000
+#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_MASK) >> MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_LSB)
+#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_LSB) & MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_MASK)
+#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_MSB    15
+#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_LSB    8
+#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_MASK   0x0000ff00
+#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_MASK) >> MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_LSB)
+#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_LSB) & MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_MASK)
+#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_MSB    7
+#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_LSB    0
+#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_MASK   0x000000ff
+#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_MASK) >> MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_LSB)
+#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_LSB) & MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_MASK)
+
+#define MAC_PCU_BASIC_RATE_SET0_ADDRESS          0x00008328
+#define MAC_PCU_BASIC_RATE_SET0_OFFSET           0x00000328
+#define MAC_PCU_BASIC_RATE_SET0_VALUE_MSB        29
+#define MAC_PCU_BASIC_RATE_SET0_VALUE_LSB        0
+#define MAC_PCU_BASIC_RATE_SET0_VALUE_MASK       0x3fffffff
+#define MAC_PCU_BASIC_RATE_SET0_VALUE_GET(x)     (((x) & MAC_PCU_BASIC_RATE_SET0_VALUE_MASK) >> MAC_PCU_BASIC_RATE_SET0_VALUE_LSB)
+#define MAC_PCU_BASIC_RATE_SET0_VALUE_SET(x)     (((x) << MAC_PCU_BASIC_RATE_SET0_VALUE_LSB) & MAC_PCU_BASIC_RATE_SET0_VALUE_MASK)
+
+#define MAC_PCU_BASIC_RATE_SET1_ADDRESS          0x0000832c
+#define MAC_PCU_BASIC_RATE_SET1_OFFSET           0x0000032c
+#define MAC_PCU_BASIC_RATE_SET1_VALUE_MSB        29
+#define MAC_PCU_BASIC_RATE_SET1_VALUE_LSB        0
+#define MAC_PCU_BASIC_RATE_SET1_VALUE_MASK       0x3fffffff
+#define MAC_PCU_BASIC_RATE_SET1_VALUE_GET(x)     (((x) & MAC_PCU_BASIC_RATE_SET1_VALUE_MASK) >> MAC_PCU_BASIC_RATE_SET1_VALUE_LSB)
+#define MAC_PCU_BASIC_RATE_SET1_VALUE_SET(x)     (((x) << MAC_PCU_BASIC_RATE_SET1_VALUE_LSB) & MAC_PCU_BASIC_RATE_SET1_VALUE_MASK)
+
+#define MAC_PCU_BASIC_RATE_SET2_ADDRESS          0x00008330
+#define MAC_PCU_BASIC_RATE_SET2_OFFSET           0x00000330
+#define MAC_PCU_BASIC_RATE_SET2_VALUE_MSB        29
+#define MAC_PCU_BASIC_RATE_SET2_VALUE_LSB        0
+#define MAC_PCU_BASIC_RATE_SET2_VALUE_MASK       0x3fffffff
+#define MAC_PCU_BASIC_RATE_SET2_VALUE_GET(x)     (((x) & MAC_PCU_BASIC_RATE_SET2_VALUE_MASK) >> MAC_PCU_BASIC_RATE_SET2_VALUE_LSB)
+#define MAC_PCU_BASIC_RATE_SET2_VALUE_SET(x)     (((x) << MAC_PCU_BASIC_RATE_SET2_VALUE_LSB) & MAC_PCU_BASIC_RATE_SET2_VALUE_MASK)
+
+#define MAC_PCU_BASIC_RATE_SET3_ADDRESS          0x00008334
+#define MAC_PCU_BASIC_RATE_SET3_OFFSET           0x00000334
+#define MAC_PCU_BASIC_RATE_SET3_VALUE_MSB        24
+#define MAC_PCU_BASIC_RATE_SET3_VALUE_LSB        0
+#define MAC_PCU_BASIC_RATE_SET3_VALUE_MASK       0x01ffffff
+#define MAC_PCU_BASIC_RATE_SET3_VALUE_GET(x)     (((x) & MAC_PCU_BASIC_RATE_SET3_VALUE_MASK) >> MAC_PCU_BASIC_RATE_SET3_VALUE_LSB)
+#define MAC_PCU_BASIC_RATE_SET3_VALUE_SET(x)     (((x) << MAC_PCU_BASIC_RATE_SET3_VALUE_LSB) & MAC_PCU_BASIC_RATE_SET3_VALUE_MASK)
+
+#define MAC_PCU_RX_INT_STATUS0_ADDRESS           0x00008338
+#define MAC_PCU_RX_INT_STATUS0_OFFSET            0x00000338
+#define MAC_PCU_RX_INT_STATUS0_DURATION_H_MSB    31
+#define MAC_PCU_RX_INT_STATUS0_DURATION_H_LSB    24
+#define MAC_PCU_RX_INT_STATUS0_DURATION_H_MASK   0xff000000
+#define MAC_PCU_RX_INT_STATUS0_DURATION_H_GET(x) (((x) & MAC_PCU_RX_INT_STATUS0_DURATION_H_MASK) >> MAC_PCU_RX_INT_STATUS0_DURATION_H_LSB)
+#define MAC_PCU_RX_INT_STATUS0_DURATION_H_SET(x) (((x) << MAC_PCU_RX_INT_STATUS0_DURATION_H_LSB) & MAC_PCU_RX_INT_STATUS0_DURATION_H_MASK)
+#define MAC_PCU_RX_INT_STATUS0_DURATION_L_MSB    23
+#define MAC_PCU_RX_INT_STATUS0_DURATION_L_LSB    16
+#define MAC_PCU_RX_INT_STATUS0_DURATION_L_MASK   0x00ff0000
+#define MAC_PCU_RX_INT_STATUS0_DURATION_L_GET(x) (((x) & MAC_PCU_RX_INT_STATUS0_DURATION_L_MASK) >> MAC_PCU_RX_INT_STATUS0_DURATION_L_LSB)
+#define MAC_PCU_RX_INT_STATUS0_DURATION_L_SET(x) (((x) << MAC_PCU_RX_INT_STATUS0_DURATION_L_LSB) & MAC_PCU_RX_INT_STATUS0_DURATION_L_MASK)
+#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_MSB 15
+#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_LSB 8
+#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_MASK 0x0000ff00
+#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_GET(x) (((x) & MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_MASK) >> MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_LSB)
+#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_SET(x) (((x) << MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_LSB) & MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_MASK)
+#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_MSB 7
+#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_LSB 0
+#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_MASK 0x000000ff
+#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_GET(x) (((x) & MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_MASK) >> MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_LSB)
+#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_SET(x) (((x) << MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_LSB) & MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_MASK)
+
+#define MAC_PCU_RX_INT_STATUS1_ADDRESS           0x0000833c
+#define MAC_PCU_RX_INT_STATUS1_OFFSET            0x0000033c
+#define MAC_PCU_RX_INT_STATUS1_VALUE_MSB         17
+#define MAC_PCU_RX_INT_STATUS1_VALUE_LSB         0
+#define MAC_PCU_RX_INT_STATUS1_VALUE_MASK        0x0003ffff
+#define MAC_PCU_RX_INT_STATUS1_VALUE_GET(x)      (((x) & MAC_PCU_RX_INT_STATUS1_VALUE_MASK) >> MAC_PCU_RX_INT_STATUS1_VALUE_LSB)
+#define MAC_PCU_RX_INT_STATUS1_VALUE_SET(x)      (((x) << MAC_PCU_RX_INT_STATUS1_VALUE_LSB) & MAC_PCU_RX_INT_STATUS1_VALUE_MASK)
+
+#define MAC_PCU_RX_INT_STATUS2_ADDRESS           0x00008340
+#define MAC_PCU_RX_INT_STATUS2_OFFSET            0x00000340
+#define MAC_PCU_RX_INT_STATUS2_VALUE_MSB         26
+#define MAC_PCU_RX_INT_STATUS2_VALUE_LSB         0
+#define MAC_PCU_RX_INT_STATUS2_VALUE_MASK        0x07ffffff
+#define MAC_PCU_RX_INT_STATUS2_VALUE_GET(x)      (((x) & MAC_PCU_RX_INT_STATUS2_VALUE_MASK) >> MAC_PCU_RX_INT_STATUS2_VALUE_LSB)
+#define MAC_PCU_RX_INT_STATUS2_VALUE_SET(x)      (((x) << MAC_PCU_RX_INT_STATUS2_VALUE_LSB) & MAC_PCU_RX_INT_STATUS2_VALUE_MASK)
+
+#define MAC_PCU_RX_INT_STATUS3_ADDRESS           0x00008344
+#define MAC_PCU_RX_INT_STATUS3_OFFSET            0x00000344
+#define MAC_PCU_RX_INT_STATUS3_VALUE_MSB         23
+#define MAC_PCU_RX_INT_STATUS3_VALUE_LSB         0
+#define MAC_PCU_RX_INT_STATUS3_VALUE_MASK        0x00ffffff
+#define MAC_PCU_RX_INT_STATUS3_VALUE_GET(x)      (((x) & MAC_PCU_RX_INT_STATUS3_VALUE_MASK) >> MAC_PCU_RX_INT_STATUS3_VALUE_LSB)
+#define MAC_PCU_RX_INT_STATUS3_VALUE_SET(x)      (((x) << MAC_PCU_RX_INT_STATUS3_VALUE_LSB) & MAC_PCU_RX_INT_STATUS3_VALUE_MASK)
+
+#define HT_HALF_GI_RATE1_ADDRESS                 0x00008348
+#define HT_HALF_GI_RATE1_OFFSET                  0x00000348
+#define HT_HALF_GI_RATE1_MCS3_MSB                31
+#define HT_HALF_GI_RATE1_MCS3_LSB                24
+#define HT_HALF_GI_RATE1_MCS3_MASK               0xff000000
+#define HT_HALF_GI_RATE1_MCS3_GET(x)             (((x) & HT_HALF_GI_RATE1_MCS3_MASK) >> HT_HALF_GI_RATE1_MCS3_LSB)
+#define HT_HALF_GI_RATE1_MCS3_SET(x)             (((x) << HT_HALF_GI_RATE1_MCS3_LSB) & HT_HALF_GI_RATE1_MCS3_MASK)
+#define HT_HALF_GI_RATE1_MCS2_MSB                23
+#define HT_HALF_GI_RATE1_MCS2_LSB                16
+#define HT_HALF_GI_RATE1_MCS2_MASK               0x00ff0000
+#define HT_HALF_GI_RATE1_MCS2_GET(x)             (((x) & HT_HALF_GI_RATE1_MCS2_MASK) >> HT_HALF_GI_RATE1_MCS2_LSB)
+#define HT_HALF_GI_RATE1_MCS2_SET(x)             (((x) << HT_HALF_GI_RATE1_MCS2_LSB) & HT_HALF_GI_RATE1_MCS2_MASK)
+#define HT_HALF_GI_RATE1_MCS1_MSB                15
+#define HT_HALF_GI_RATE1_MCS1_LSB                8
+#define HT_HALF_GI_RATE1_MCS1_MASK               0x0000ff00
+#define HT_HALF_GI_RATE1_MCS1_GET(x)             (((x) & HT_HALF_GI_RATE1_MCS1_MASK) >> HT_HALF_GI_RATE1_MCS1_LSB)
+#define HT_HALF_GI_RATE1_MCS1_SET(x)             (((x) << HT_HALF_GI_RATE1_MCS1_LSB) & HT_HALF_GI_RATE1_MCS1_MASK)
+#define HT_HALF_GI_RATE1_MCS0_MSB                7
+#define HT_HALF_GI_RATE1_MCS0_LSB                0
+#define HT_HALF_GI_RATE1_MCS0_MASK               0x000000ff
+#define HT_HALF_GI_RATE1_MCS0_GET(x)             (((x) & HT_HALF_GI_RATE1_MCS0_MASK) >> HT_HALF_GI_RATE1_MCS0_LSB)
+#define HT_HALF_GI_RATE1_MCS0_SET(x)             (((x) << HT_HALF_GI_RATE1_MCS0_LSB) & HT_HALF_GI_RATE1_MCS0_MASK)
+
+#define HT_HALF_GI_RATE2_ADDRESS                 0x0000834c
+#define HT_HALF_GI_RATE2_OFFSET                  0x0000034c
+#define HT_HALF_GI_RATE2_MCS7_MSB                31
+#define HT_HALF_GI_RATE2_MCS7_LSB                24
+#define HT_HALF_GI_RATE2_MCS7_MASK               0xff000000
+#define HT_HALF_GI_RATE2_MCS7_GET(x)             (((x) & HT_HALF_GI_RATE2_MCS7_MASK) >> HT_HALF_GI_RATE2_MCS7_LSB)
+#define HT_HALF_GI_RATE2_MCS7_SET(x)             (((x) << HT_HALF_GI_RATE2_MCS7_LSB) & HT_HALF_GI_RATE2_MCS7_MASK)
+#define HT_HALF_GI_RATE2_MCS6_MSB                23
+#define HT_HALF_GI_RATE2_MCS6_LSB                16
+#define HT_HALF_GI_RATE2_MCS6_MASK               0x00ff0000
+#define HT_HALF_GI_RATE2_MCS6_GET(x)             (((x) & HT_HALF_GI_RATE2_MCS6_MASK) >> HT_HALF_GI_RATE2_MCS6_LSB)
+#define HT_HALF_GI_RATE2_MCS6_SET(x)             (((x) << HT_HALF_GI_RATE2_MCS6_LSB) & HT_HALF_GI_RATE2_MCS6_MASK)
+#define HT_HALF_GI_RATE2_MCS5_MSB                15
+#define HT_HALF_GI_RATE2_MCS5_LSB                8
+#define HT_HALF_GI_RATE2_MCS5_MASK               0x0000ff00
+#define HT_HALF_GI_RATE2_MCS5_GET(x)             (((x) & HT_HALF_GI_RATE2_MCS5_MASK) >> HT_HALF_GI_RATE2_MCS5_LSB)
+#define HT_HALF_GI_RATE2_MCS5_SET(x)             (((x) << HT_HALF_GI_RATE2_MCS5_LSB) & HT_HALF_GI_RATE2_MCS5_MASK)
+#define HT_HALF_GI_RATE2_MCS4_MSB                7
+#define HT_HALF_GI_RATE2_MCS4_LSB                0
+#define HT_HALF_GI_RATE2_MCS4_MASK               0x000000ff
+#define HT_HALF_GI_RATE2_MCS4_GET(x)             (((x) & HT_HALF_GI_RATE2_MCS4_MASK) >> HT_HALF_GI_RATE2_MCS4_LSB)
+#define HT_HALF_GI_RATE2_MCS4_SET(x)             (((x) << HT_HALF_GI_RATE2_MCS4_LSB) & HT_HALF_GI_RATE2_MCS4_MASK)
+
+#define HT_FULL_GI_RATE1_ADDRESS                 0x00008350
+#define HT_FULL_GI_RATE1_OFFSET                  0x00000350
+#define HT_FULL_GI_RATE1_MCS3_MSB                31
+#define HT_FULL_GI_RATE1_MCS3_LSB                24
+#define HT_FULL_GI_RATE1_MCS3_MASK               0xff000000
+#define HT_FULL_GI_RATE1_MCS3_GET(x)             (((x) & HT_FULL_GI_RATE1_MCS3_MASK) >> HT_FULL_GI_RATE1_MCS3_LSB)
+#define HT_FULL_GI_RATE1_MCS3_SET(x)             (((x) << HT_FULL_GI_RATE1_MCS3_LSB) & HT_FULL_GI_RATE1_MCS3_MASK)
+#define HT_FULL_GI_RATE1_MCS2_MSB                23
+#define HT_FULL_GI_RATE1_MCS2_LSB                16
+#define HT_FULL_GI_RATE1_MCS2_MASK               0x00ff0000
+#define HT_FULL_GI_RATE1_MCS2_GET(x)             (((x) & HT_FULL_GI_RATE1_MCS2_MASK) >> HT_FULL_GI_RATE1_MCS2_LSB)
+#define HT_FULL_GI_RATE1_MCS2_SET(x)             (((x) << HT_FULL_GI_RATE1_MCS2_LSB) & HT_FULL_GI_RATE1_MCS2_MASK)
+#define HT_FULL_GI_RATE1_MCS1_MSB                15
+#define HT_FULL_GI_RATE1_MCS1_LSB                8
+#define HT_FULL_GI_RATE1_MCS1_MASK               0x0000ff00
+#define HT_FULL_GI_RATE1_MCS1_GET(x)             (((x) & HT_FULL_GI_RATE1_MCS1_MASK) >> HT_FULL_GI_RATE1_MCS1_LSB)
+#define HT_FULL_GI_RATE1_MCS1_SET(x)             (((x) << HT_FULL_GI_RATE1_MCS1_LSB) & HT_FULL_GI_RATE1_MCS1_MASK)
+#define HT_FULL_GI_RATE1_MCS0_MSB                7
+#define HT_FULL_GI_RATE1_MCS0_LSB                0
+#define HT_FULL_GI_RATE1_MCS0_MASK               0x000000ff
+#define HT_FULL_GI_RATE1_MCS0_GET(x)             (((x) & HT_FULL_GI_RATE1_MCS0_MASK) >> HT_FULL_GI_RATE1_MCS0_LSB)
+#define HT_FULL_GI_RATE1_MCS0_SET(x)             (((x) << HT_FULL_GI_RATE1_MCS0_LSB) & HT_FULL_GI_RATE1_MCS0_MASK)
+
+#define HT_FULL_GI_RATE2_ADDRESS                 0x00008354
+#define HT_FULL_GI_RATE2_OFFSET                  0x00000354
+#define HT_FULL_GI_RATE2_MCS7_MSB                31
+#define HT_FULL_GI_RATE2_MCS7_LSB                24
+#define HT_FULL_GI_RATE2_MCS7_MASK               0xff000000
+#define HT_FULL_GI_RATE2_MCS7_GET(x)             (((x) & HT_FULL_GI_RATE2_MCS7_MASK) >> HT_FULL_GI_RATE2_MCS7_LSB)
+#define HT_FULL_GI_RATE2_MCS7_SET(x)             (((x) << HT_FULL_GI_RATE2_MCS7_LSB) & HT_FULL_GI_RATE2_MCS7_MASK)
+#define HT_FULL_GI_RATE2_MCS6_MSB                23
+#define HT_FULL_GI_RATE2_MCS6_LSB                16
+#define HT_FULL_GI_RATE2_MCS6_MASK               0x00ff0000
+#define HT_FULL_GI_RATE2_MCS6_GET(x)             (((x) & HT_FULL_GI_RATE2_MCS6_MASK) >> HT_FULL_GI_RATE2_MCS6_LSB)
+#define HT_FULL_GI_RATE2_MCS6_SET(x)             (((x) << HT_FULL_GI_RATE2_MCS6_LSB) & HT_FULL_GI_RATE2_MCS6_MASK)
+#define HT_FULL_GI_RATE2_MCS5_MSB                15
+#define HT_FULL_GI_RATE2_MCS5_LSB                8
+#define HT_FULL_GI_RATE2_MCS5_MASK               0x0000ff00
+#define HT_FULL_GI_RATE2_MCS5_GET(x)             (((x) & HT_FULL_GI_RATE2_MCS5_MASK) >> HT_FULL_GI_RATE2_MCS5_LSB)
+#define HT_FULL_GI_RATE2_MCS5_SET(x)             (((x) << HT_FULL_GI_RATE2_MCS5_LSB) & HT_FULL_GI_RATE2_MCS5_MASK)
+#define HT_FULL_GI_RATE2_MCS4_MSB                7
+#define HT_FULL_GI_RATE2_MCS4_LSB                0
+#define HT_FULL_GI_RATE2_MCS4_MASK               0x000000ff
+#define HT_FULL_GI_RATE2_MCS4_GET(x)             (((x) & HT_FULL_GI_RATE2_MCS4_MASK) >> HT_FULL_GI_RATE2_MCS4_LSB)
+#define HT_FULL_GI_RATE2_MCS4_SET(x)             (((x) << HT_FULL_GI_RATE2_MCS4_LSB) & HT_FULL_GI_RATE2_MCS4_MASK)
+
+#define LEGACY_RATE1_ADDRESS                     0x00008358
+#define LEGACY_RATE1_OFFSET                      0x00000358
+#define LEGACY_RATE1_RATE12_MSB                  29
+#define LEGACY_RATE1_RATE12_LSB                  24
+#define LEGACY_RATE1_RATE12_MASK                 0x3f000000
+#define LEGACY_RATE1_RATE12_GET(x)               (((x) & LEGACY_RATE1_RATE12_MASK) >> LEGACY_RATE1_RATE12_LSB)
+#define LEGACY_RATE1_RATE12_SET(x)               (((x) << LEGACY_RATE1_RATE12_LSB) & LEGACY_RATE1_RATE12_MASK)
+#define LEGACY_RATE1_RATE11_MSB                  23
+#define LEGACY_RATE1_RATE11_LSB                  18
+#define LEGACY_RATE1_RATE11_MASK                 0x00fc0000
+#define LEGACY_RATE1_RATE11_GET(x)               (((x) & LEGACY_RATE1_RATE11_MASK) >> LEGACY_RATE1_RATE11_LSB)
+#define LEGACY_RATE1_RATE11_SET(x)               (((x) << LEGACY_RATE1_RATE11_LSB) & LEGACY_RATE1_RATE11_MASK)
+#define LEGACY_RATE1_RATE10_MSB                  17
+#define LEGACY_RATE1_RATE10_LSB                  12
+#define LEGACY_RATE1_RATE10_MASK                 0x0003f000
+#define LEGACY_RATE1_RATE10_GET(x)               (((x) & LEGACY_RATE1_RATE10_MASK) >> LEGACY_RATE1_RATE10_LSB)
+#define LEGACY_RATE1_RATE10_SET(x)               (((x) << LEGACY_RATE1_RATE10_LSB) & LEGACY_RATE1_RATE10_MASK)
+#define LEGACY_RATE1_RATE9_MSB                   11
+#define LEGACY_RATE1_RATE9_LSB                   6
+#define LEGACY_RATE1_RATE9_MASK                  0x00000fc0
+#define LEGACY_RATE1_RATE9_GET(x)                (((x) & LEGACY_RATE1_RATE9_MASK) >> LEGACY_RATE1_RATE9_LSB)
+#define LEGACY_RATE1_RATE9_SET(x)                (((x) << LEGACY_RATE1_RATE9_LSB) & LEGACY_RATE1_RATE9_MASK)
+#define LEGACY_RATE1_RATE8_MSB                   5
+#define LEGACY_RATE1_RATE8_LSB                   0
+#define LEGACY_RATE1_RATE8_MASK                  0x0000003f
+#define LEGACY_RATE1_RATE8_GET(x)                (((x) & LEGACY_RATE1_RATE8_MASK) >> LEGACY_RATE1_RATE8_LSB)
+#define LEGACY_RATE1_RATE8_SET(x)                (((x) << LEGACY_RATE1_RATE8_LSB) & LEGACY_RATE1_RATE8_MASK)
+
+#define LEGACY_RATE2_ADDRESS                     0x0000835c
+#define LEGACY_RATE2_OFFSET                      0x0000035c
+#define LEGACY_RATE2_RATE25_MSB                  29
+#define LEGACY_RATE2_RATE25_LSB                  24
+#define LEGACY_RATE2_RATE25_MASK                 0x3f000000
+#define LEGACY_RATE2_RATE25_GET(x)               (((x) & LEGACY_RATE2_RATE25_MASK) >> LEGACY_RATE2_RATE25_LSB)
+#define LEGACY_RATE2_RATE25_SET(x)               (((x) << LEGACY_RATE2_RATE25_LSB) & LEGACY_RATE2_RATE25_MASK)
+#define LEGACY_RATE2_RATE24_MSB                  23
+#define LEGACY_RATE2_RATE24_LSB                  18
+#define LEGACY_RATE2_RATE24_MASK                 0x00fc0000
+#define LEGACY_RATE2_RATE24_GET(x)               (((x) & LEGACY_RATE2_RATE24_MASK) >> LEGACY_RATE2_RATE24_LSB)
+#define LEGACY_RATE2_RATE24_SET(x)               (((x) << LEGACY_RATE2_RATE24_LSB) & LEGACY_RATE2_RATE24_MASK)
+#define LEGACY_RATE2_RATE15_MSB                  17
+#define LEGACY_RATE2_RATE15_LSB                  12
+#define LEGACY_RATE2_RATE15_MASK                 0x0003f000
+#define LEGACY_RATE2_RATE15_GET(x)               (((x) & LEGACY_RATE2_RATE15_MASK) >> LEGACY_RATE2_RATE15_LSB)
+#define LEGACY_RATE2_RATE15_SET(x)               (((x) << LEGACY_RATE2_RATE15_LSB) & LEGACY_RATE2_RATE15_MASK)
+#define LEGACY_RATE2_RATE14_MSB                  11
+#define LEGACY_RATE2_RATE14_LSB                  6
+#define LEGACY_RATE2_RATE14_MASK                 0x00000fc0
+#define LEGACY_RATE2_RATE14_GET(x)               (((x) & LEGACY_RATE2_RATE14_MASK) >> LEGACY_RATE2_RATE14_LSB)
+#define LEGACY_RATE2_RATE14_SET(x)               (((x) << LEGACY_RATE2_RATE14_LSB) & LEGACY_RATE2_RATE14_MASK)
+#define LEGACY_RATE2_RATE13_MSB                  5
+#define LEGACY_RATE2_RATE13_LSB                  0
+#define LEGACY_RATE2_RATE13_MASK                 0x0000003f
+#define LEGACY_RATE2_RATE13_GET(x)               (((x) & LEGACY_RATE2_RATE13_MASK) >> LEGACY_RATE2_RATE13_LSB)
+#define LEGACY_RATE2_RATE13_SET(x)               (((x) << LEGACY_RATE2_RATE13_LSB) & LEGACY_RATE2_RATE13_MASK)
+
+#define LEGACY_RATE3_ADDRESS                     0x00008360
+#define LEGACY_RATE3_OFFSET                      0x00000360
+#define LEGACY_RATE3_RATE30_MSB                  29
+#define LEGACY_RATE3_RATE30_LSB                  24
+#define LEGACY_RATE3_RATE30_MASK                 0x3f000000
+#define LEGACY_RATE3_RATE30_GET(x)               (((x) & LEGACY_RATE3_RATE30_MASK) >> LEGACY_RATE3_RATE30_LSB)
+#define LEGACY_RATE3_RATE30_SET(x)               (((x) << LEGACY_RATE3_RATE30_LSB) & LEGACY_RATE3_RATE30_MASK)
+#define LEGACY_RATE3_RATE29_MSB                  23
+#define LEGACY_RATE3_RATE29_LSB                  18
+#define LEGACY_RATE3_RATE29_MASK                 0x00fc0000
+#define LEGACY_RATE3_RATE29_GET(x)               (((x) & LEGACY_RATE3_RATE29_MASK) >> LEGACY_RATE3_RATE29_LSB)
+#define LEGACY_RATE3_RATE29_SET(x)               (((x) << LEGACY_RATE3_RATE29_LSB) & LEGACY_RATE3_RATE29_MASK)
+#define LEGACY_RATE3_RATE28_MSB                  17
+#define LEGACY_RATE3_RATE28_LSB                  12
+#define LEGACY_RATE3_RATE28_MASK                 0x0003f000
+#define LEGACY_RATE3_RATE28_GET(x)               (((x) & LEGACY_RATE3_RATE28_MASK) >> LEGACY_RATE3_RATE28_LSB)
+#define LEGACY_RATE3_RATE28_SET(x)               (((x) << LEGACY_RATE3_RATE28_LSB) & LEGACY_RATE3_RATE28_MASK)
+#define LEGACY_RATE3_RATE27_MSB                  11
+#define LEGACY_RATE3_RATE27_LSB                  6
+#define LEGACY_RATE3_RATE27_MASK                 0x00000fc0
+#define LEGACY_RATE3_RATE27_GET(x)               (((x) & LEGACY_RATE3_RATE27_MASK) >> LEGACY_RATE3_RATE27_LSB)
+#define LEGACY_RATE3_RATE27_SET(x)               (((x) << LEGACY_RATE3_RATE27_LSB) & LEGACY_RATE3_RATE27_MASK)
+#define LEGACY_RATE3_RATE26_MSB                  5
+#define LEGACY_RATE3_RATE26_LSB                  0
+#define LEGACY_RATE3_RATE26_MASK                 0x0000003f
+#define LEGACY_RATE3_RATE26_GET(x)               (((x) & LEGACY_RATE3_RATE26_MASK) >> LEGACY_RATE3_RATE26_LSB)
+#define LEGACY_RATE3_RATE26_SET(x)               (((x) << LEGACY_RATE3_RATE26_LSB) & LEGACY_RATE3_RATE26_MASK)
+
+#define RX_INT_FILTER_ADDRESS                    0x00008364
+#define RX_INT_FILTER_OFFSET                     0x00000364
+#define RX_INT_FILTER_BEACON_MSB                 17
+#define RX_INT_FILTER_BEACON_LSB                 17
+#define RX_INT_FILTER_BEACON_MASK                0x00020000
+#define RX_INT_FILTER_BEACON_GET(x)              (((x) & RX_INT_FILTER_BEACON_MASK) >> RX_INT_FILTER_BEACON_LSB)
+#define RX_INT_FILTER_BEACON_SET(x)              (((x) << RX_INT_FILTER_BEACON_LSB) & RX_INT_FILTER_BEACON_MASK)
+#define RX_INT_FILTER_AMPDU_MSB                  16
+#define RX_INT_FILTER_AMPDU_LSB                  16
+#define RX_INT_FILTER_AMPDU_MASK                 0x00010000
+#define RX_INT_FILTER_AMPDU_GET(x)               (((x) & RX_INT_FILTER_AMPDU_MASK) >> RX_INT_FILTER_AMPDU_LSB)
+#define RX_INT_FILTER_AMPDU_SET(x)               (((x) << RX_INT_FILTER_AMPDU_LSB) & RX_INT_FILTER_AMPDU_MASK)
+#define RX_INT_FILTER_EOSP_MSB                   15
+#define RX_INT_FILTER_EOSP_LSB                   15
+#define RX_INT_FILTER_EOSP_MASK                  0x00008000
+#define RX_INT_FILTER_EOSP_GET(x)                (((x) & RX_INT_FILTER_EOSP_MASK) >> RX_INT_FILTER_EOSP_LSB)
+#define RX_INT_FILTER_EOSP_SET(x)                (((x) << RX_INT_FILTER_EOSP_LSB) & RX_INT_FILTER_EOSP_MASK)
+#define RX_INT_FILTER_LENGTH_LOW_MSB             14
+#define RX_INT_FILTER_LENGTH_LOW_LSB             14
+#define RX_INT_FILTER_LENGTH_LOW_MASK            0x00004000
+#define RX_INT_FILTER_LENGTH_LOW_GET(x)          (((x) & RX_INT_FILTER_LENGTH_LOW_MASK) >> RX_INT_FILTER_LENGTH_LOW_LSB)
+#define RX_INT_FILTER_LENGTH_LOW_SET(x)          (((x) << RX_INT_FILTER_LENGTH_LOW_LSB) & RX_INT_FILTER_LENGTH_LOW_MASK)
+#define RX_INT_FILTER_LENGTH_HIGH_MSB            13
+#define RX_INT_FILTER_LENGTH_HIGH_LSB            13
+#define RX_INT_FILTER_LENGTH_HIGH_MASK           0x00002000
+#define RX_INT_FILTER_LENGTH_HIGH_GET(x)         (((x) & RX_INT_FILTER_LENGTH_HIGH_MASK) >> RX_INT_FILTER_LENGTH_HIGH_LSB)
+#define RX_INT_FILTER_LENGTH_HIGH_SET(x)         (((x) << RX_INT_FILTER_LENGTH_HIGH_LSB) & RX_INT_FILTER_LENGTH_HIGH_MASK)
+#define RX_INT_FILTER_RSSI_MSB                   12
+#define RX_INT_FILTER_RSSI_LSB                   12
+#define RX_INT_FILTER_RSSI_MASK                  0x00001000
+#define RX_INT_FILTER_RSSI_GET(x)                (((x) & RX_INT_FILTER_RSSI_MASK) >> RX_INT_FILTER_RSSI_LSB)
+#define RX_INT_FILTER_RSSI_SET(x)                (((x) << RX_INT_FILTER_RSSI_LSB) & RX_INT_FILTER_RSSI_MASK)
+#define RX_INT_FILTER_RATE_LOW_MSB               11
+#define RX_INT_FILTER_RATE_LOW_LSB               11
+#define RX_INT_FILTER_RATE_LOW_MASK              0x00000800
+#define RX_INT_FILTER_RATE_LOW_GET(x)            (((x) & RX_INT_FILTER_RATE_LOW_MASK) >> RX_INT_FILTER_RATE_LOW_LSB)
+#define RX_INT_FILTER_RATE_LOW_SET(x)            (((x) << RX_INT_FILTER_RATE_LOW_LSB) & RX_INT_FILTER_RATE_LOW_MASK)
+#define RX_INT_FILTER_RATE_HIGH_MSB              10
+#define RX_INT_FILTER_RATE_HIGH_LSB              10
+#define RX_INT_FILTER_RATE_HIGH_MASK             0x00000400
+#define RX_INT_FILTER_RATE_HIGH_GET(x)           (((x) & RX_INT_FILTER_RATE_HIGH_MASK) >> RX_INT_FILTER_RATE_HIGH_LSB)
+#define RX_INT_FILTER_RATE_HIGH_SET(x)           (((x) << RX_INT_FILTER_RATE_HIGH_LSB) & RX_INT_FILTER_RATE_HIGH_MASK)
+#define RX_INT_FILTER_MORE_FRAG_MSB              9
+#define RX_INT_FILTER_MORE_FRAG_LSB              9
+#define RX_INT_FILTER_MORE_FRAG_MASK             0x00000200
+#define RX_INT_FILTER_MORE_FRAG_GET(x)           (((x) & RX_INT_FILTER_MORE_FRAG_MASK) >> RX_INT_FILTER_MORE_FRAG_LSB)
+#define RX_INT_FILTER_MORE_FRAG_SET(x)           (((x) << RX_INT_FILTER_MORE_FRAG_LSB) & RX_INT_FILTER_MORE_FRAG_MASK)
+#define RX_INT_FILTER_MORE_DATA_MSB              8
+#define RX_INT_FILTER_MORE_DATA_LSB              8
+#define RX_INT_FILTER_MORE_DATA_MASK             0x00000100
+#define RX_INT_FILTER_MORE_DATA_GET(x)           (((x) & RX_INT_FILTER_MORE_DATA_MASK) >> RX_INT_FILTER_MORE_DATA_LSB)
+#define RX_INT_FILTER_MORE_DATA_SET(x)           (((x) << RX_INT_FILTER_MORE_DATA_LSB) & RX_INT_FILTER_MORE_DATA_MASK)
+#define RX_INT_FILTER_RETRY_MSB                  7
+#define RX_INT_FILTER_RETRY_LSB                  7
+#define RX_INT_FILTER_RETRY_MASK                 0x00000080
+#define RX_INT_FILTER_RETRY_GET(x)               (((x) & RX_INT_FILTER_RETRY_MASK) >> RX_INT_FILTER_RETRY_LSB)
+#define RX_INT_FILTER_RETRY_SET(x)               (((x) << RX_INT_FILTER_RETRY_LSB) & RX_INT_FILTER_RETRY_MASK)
+#define RX_INT_FILTER_CTS_MSB                    6
+#define RX_INT_FILTER_CTS_LSB                    6
+#define RX_INT_FILTER_CTS_MASK                   0x00000040
+#define RX_INT_FILTER_CTS_GET(x)                 (((x) & RX_INT_FILTER_CTS_MASK) >> RX_INT_FILTER_CTS_LSB)
+#define RX_INT_FILTER_CTS_SET(x)                 (((x) << RX_INT_FILTER_CTS_LSB) & RX_INT_FILTER_CTS_MASK)
+#define RX_INT_FILTER_ACK_MSB                    5
+#define RX_INT_FILTER_ACK_LSB                    5
+#define RX_INT_FILTER_ACK_MASK                   0x00000020
+#define RX_INT_FILTER_ACK_GET(x)                 (((x) & RX_INT_FILTER_ACK_MASK) >> RX_INT_FILTER_ACK_LSB)
+#define RX_INT_FILTER_ACK_SET(x)                 (((x) << RX_INT_FILTER_ACK_LSB) & RX_INT_FILTER_ACK_MASK)
+#define RX_INT_FILTER_RTS_MSB                    4
+#define RX_INT_FILTER_RTS_LSB                    4
+#define RX_INT_FILTER_RTS_MASK                   0x00000010
+#define RX_INT_FILTER_RTS_GET(x)                 (((x) & RX_INT_FILTER_RTS_MASK) >> RX_INT_FILTER_RTS_LSB)
+#define RX_INT_FILTER_RTS_SET(x)                 (((x) << RX_INT_FILTER_RTS_LSB) & RX_INT_FILTER_RTS_MASK)
+#define RX_INT_FILTER_MCAST_MSB                  3
+#define RX_INT_FILTER_MCAST_LSB                  3
+#define RX_INT_FILTER_MCAST_MASK                 0x00000008
+#define RX_INT_FILTER_MCAST_GET(x)               (((x) & RX_INT_FILTER_MCAST_MASK) >> RX_INT_FILTER_MCAST_LSB)
+#define RX_INT_FILTER_MCAST_SET(x)               (((x) << RX_INT_FILTER_MCAST_LSB) & RX_INT_FILTER_MCAST_MASK)
+#define RX_INT_FILTER_BCAST_MSB                  2
+#define RX_INT_FILTER_BCAST_LSB                  2
+#define RX_INT_FILTER_BCAST_MASK                 0x00000004
+#define RX_INT_FILTER_BCAST_GET(x)               (((x) & RX_INT_FILTER_BCAST_MASK) >> RX_INT_FILTER_BCAST_LSB)
+#define RX_INT_FILTER_BCAST_SET(x)               (((x) << RX_INT_FILTER_BCAST_LSB) & RX_INT_FILTER_BCAST_MASK)
+#define RX_INT_FILTER_DIRECTED_MSB               1
+#define RX_INT_FILTER_DIRECTED_LSB               1
+#define RX_INT_FILTER_DIRECTED_MASK              0x00000002
+#define RX_INT_FILTER_DIRECTED_GET(x)            (((x) & RX_INT_FILTER_DIRECTED_MASK) >> RX_INT_FILTER_DIRECTED_LSB)
+#define RX_INT_FILTER_DIRECTED_SET(x)            (((x) << RX_INT_FILTER_DIRECTED_LSB) & RX_INT_FILTER_DIRECTED_MASK)
+#define RX_INT_FILTER_ENABLE_MSB                 0
+#define RX_INT_FILTER_ENABLE_LSB                 0
+#define RX_INT_FILTER_ENABLE_MASK                0x00000001
+#define RX_INT_FILTER_ENABLE_GET(x)              (((x) & RX_INT_FILTER_ENABLE_MASK) >> RX_INT_FILTER_ENABLE_LSB)
+#define RX_INT_FILTER_ENABLE_SET(x)              (((x) << RX_INT_FILTER_ENABLE_LSB) & RX_INT_FILTER_ENABLE_MASK)
+
+#define RX_INT_OVERFLOW_ADDRESS                  0x00008368
+#define RX_INT_OVERFLOW_OFFSET                   0x00000368
+#define RX_INT_OVERFLOW_STATUS_MSB               0
+#define RX_INT_OVERFLOW_STATUS_LSB               0
+#define RX_INT_OVERFLOW_STATUS_MASK              0x00000001
+#define RX_INT_OVERFLOW_STATUS_GET(x)            (((x) & RX_INT_OVERFLOW_STATUS_MASK) >> RX_INT_OVERFLOW_STATUS_LSB)
+#define RX_INT_OVERFLOW_STATUS_SET(x)            (((x) << RX_INT_OVERFLOW_STATUS_LSB) & RX_INT_OVERFLOW_STATUS_MASK)
+
+#define RX_FILTER_THRESH_ADDRESS                 0x0000836c
+#define RX_FILTER_THRESH_OFFSET                  0x0000036c
+#define RX_FILTER_THRESH_RSSI_LOW_MSB            23
+#define RX_FILTER_THRESH_RSSI_LOW_LSB            16
+#define RX_FILTER_THRESH_RSSI_LOW_MASK           0x00ff0000
+#define RX_FILTER_THRESH_RSSI_LOW_GET(x)         (((x) & RX_FILTER_THRESH_RSSI_LOW_MASK) >> RX_FILTER_THRESH_RSSI_LOW_LSB)
+#define RX_FILTER_THRESH_RSSI_LOW_SET(x)         (((x) << RX_FILTER_THRESH_RSSI_LOW_LSB) & RX_FILTER_THRESH_RSSI_LOW_MASK)
+#define RX_FILTER_THRESH_RATE_LOW_MSB            15
+#define RX_FILTER_THRESH_RATE_LOW_LSB            8
+#define RX_FILTER_THRESH_RATE_LOW_MASK           0x0000ff00
+#define RX_FILTER_THRESH_RATE_LOW_GET(x)         (((x) & RX_FILTER_THRESH_RATE_LOW_MASK) >> RX_FILTER_THRESH_RATE_LOW_LSB)
+#define RX_FILTER_THRESH_RATE_LOW_SET(x)         (((x) << RX_FILTER_THRESH_RATE_LOW_LSB) & RX_FILTER_THRESH_RATE_LOW_MASK)
+#define RX_FILTER_THRESH_RATE_HIGH_MSB           7
+#define RX_FILTER_THRESH_RATE_HIGH_LSB           0
+#define RX_FILTER_THRESH_RATE_HIGH_MASK          0x000000ff
+#define RX_FILTER_THRESH_RATE_HIGH_GET(x)        (((x) & RX_FILTER_THRESH_RATE_HIGH_MASK) >> RX_FILTER_THRESH_RATE_HIGH_LSB)
+#define RX_FILTER_THRESH_RATE_HIGH_SET(x)        (((x) << RX_FILTER_THRESH_RATE_HIGH_LSB) & RX_FILTER_THRESH_RATE_HIGH_MASK)
+
+#define RX_FILTER_THRESH1_ADDRESS                0x00008370
+#define RX_FILTER_THRESH1_OFFSET                 0x00000370
+#define RX_FILTER_THRESH1_LENGTH_LOW_MSB         23
+#define RX_FILTER_THRESH1_LENGTH_LOW_LSB         12
+#define RX_FILTER_THRESH1_LENGTH_LOW_MASK        0x00fff000
+#define RX_FILTER_THRESH1_LENGTH_LOW_GET(x)      (((x) & RX_FILTER_THRESH1_LENGTH_LOW_MASK) >> RX_FILTER_THRESH1_LENGTH_LOW_LSB)
+#define RX_FILTER_THRESH1_LENGTH_LOW_SET(x)      (((x) << RX_FILTER_THRESH1_LENGTH_LOW_LSB) & RX_FILTER_THRESH1_LENGTH_LOW_MASK)
+#define RX_FILTER_THRESH1_LENGTH_HIGH_MSB        11
+#define RX_FILTER_THRESH1_LENGTH_HIGH_LSB        0
+#define RX_FILTER_THRESH1_LENGTH_HIGH_MASK       0x00000fff
+#define RX_FILTER_THRESH1_LENGTH_HIGH_GET(x)     (((x) & RX_FILTER_THRESH1_LENGTH_HIGH_MASK) >> RX_FILTER_THRESH1_LENGTH_HIGH_LSB)
+#define RX_FILTER_THRESH1_LENGTH_HIGH_SET(x)     (((x) << RX_FILTER_THRESH1_LENGTH_HIGH_LSB) & RX_FILTER_THRESH1_LENGTH_HIGH_MASK)
+
+#define RX_PRIORITY_THRESH0_ADDRESS              0x00008374
+#define RX_PRIORITY_THRESH0_OFFSET               0x00000374
+#define RX_PRIORITY_THRESH0_RSSI_LOW_MSB         31
+#define RX_PRIORITY_THRESH0_RSSI_LOW_LSB         24
+#define RX_PRIORITY_THRESH0_RSSI_LOW_MASK        0xff000000
+#define RX_PRIORITY_THRESH0_RSSI_LOW_GET(x)      (((x) & RX_PRIORITY_THRESH0_RSSI_LOW_MASK) >> RX_PRIORITY_THRESH0_RSSI_LOW_LSB)
+#define RX_PRIORITY_THRESH0_RSSI_LOW_SET(x)      (((x) << RX_PRIORITY_THRESH0_RSSI_LOW_LSB) & RX_PRIORITY_THRESH0_RSSI_LOW_MASK)
+#define RX_PRIORITY_THRESH0_RSSI_HIGH_MSB        23
+#define RX_PRIORITY_THRESH0_RSSI_HIGH_LSB        16
+#define RX_PRIORITY_THRESH0_RSSI_HIGH_MASK       0x00ff0000
+#define RX_PRIORITY_THRESH0_RSSI_HIGH_GET(x)     (((x) & RX_PRIORITY_THRESH0_RSSI_HIGH_MASK) >> RX_PRIORITY_THRESH0_RSSI_HIGH_LSB)
+#define RX_PRIORITY_THRESH0_RSSI_HIGH_SET(x)     (((x) << RX_PRIORITY_THRESH0_RSSI_HIGH_LSB) & RX_PRIORITY_THRESH0_RSSI_HIGH_MASK)
+#define RX_PRIORITY_THRESH0_RATE_LOW_MSB         15
+#define RX_PRIORITY_THRESH0_RATE_LOW_LSB         8
+#define RX_PRIORITY_THRESH0_RATE_LOW_MASK        0x0000ff00
+#define RX_PRIORITY_THRESH0_RATE_LOW_GET(x)      (((x) & RX_PRIORITY_THRESH0_RATE_LOW_MASK) >> RX_PRIORITY_THRESH0_RATE_LOW_LSB)
+#define RX_PRIORITY_THRESH0_RATE_LOW_SET(x)      (((x) << RX_PRIORITY_THRESH0_RATE_LOW_LSB) & RX_PRIORITY_THRESH0_RATE_LOW_MASK)
+#define RX_PRIORITY_THRESH0_RATE_HIGH_MSB        7
+#define RX_PRIORITY_THRESH0_RATE_HIGH_LSB        0
+#define RX_PRIORITY_THRESH0_RATE_HIGH_MASK       0x000000ff
+#define RX_PRIORITY_THRESH0_RATE_HIGH_GET(x)     (((x) & RX_PRIORITY_THRESH0_RATE_HIGH_MASK) >> RX_PRIORITY_THRESH0_RATE_HIGH_LSB)
+#define RX_PRIORITY_THRESH0_RATE_HIGH_SET(x)     (((x) << RX_PRIORITY_THRESH0_RATE_HIGH_LSB) & RX_PRIORITY_THRESH0_RATE_HIGH_MASK)
+
+#define RX_PRIORITY_THRESH1_ADDRESS              0x00008378
+#define RX_PRIORITY_THRESH1_OFFSET               0x00000378
+#define RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_MSB  31
+#define RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_LSB  24
+#define RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_MASK 0xff000000
+#define RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_MASK) >> RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_LSB)
+#define RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_LSB) & RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_MASK)
+#define RX_PRIORITY_THRESH1_LENGTH_LOW_MSB       23
+#define RX_PRIORITY_THRESH1_LENGTH_LOW_LSB       12
+#define RX_PRIORITY_THRESH1_LENGTH_LOW_MASK      0x00fff000
+#define RX_PRIORITY_THRESH1_LENGTH_LOW_GET(x)    (((x) & RX_PRIORITY_THRESH1_LENGTH_LOW_MASK) >> RX_PRIORITY_THRESH1_LENGTH_LOW_LSB)
+#define RX_PRIORITY_THRESH1_LENGTH_LOW_SET(x)    (((x) << RX_PRIORITY_THRESH1_LENGTH_LOW_LSB) & RX_PRIORITY_THRESH1_LENGTH_LOW_MASK)
+#define RX_PRIORITY_THRESH1_LENGTH_HIGH_MSB      11
+#define RX_PRIORITY_THRESH1_LENGTH_HIGH_LSB      0
+#define RX_PRIORITY_THRESH1_LENGTH_HIGH_MASK     0x00000fff
+#define RX_PRIORITY_THRESH1_LENGTH_HIGH_GET(x)   (((x) & RX_PRIORITY_THRESH1_LENGTH_HIGH_MASK) >> RX_PRIORITY_THRESH1_LENGTH_HIGH_LSB)
+#define RX_PRIORITY_THRESH1_LENGTH_HIGH_SET(x)   (((x) << RX_PRIORITY_THRESH1_LENGTH_HIGH_LSB) & RX_PRIORITY_THRESH1_LENGTH_HIGH_MASK)
+
+#define RX_PRIORITY_THRESH2_ADDRESS              0x0000837c
+#define RX_PRIORITY_THRESH2_OFFSET               0x0000037c
+#define RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_MSB   31
+#define RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_LSB   24
+#define RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_MASK  0xff000000
+#define RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_MASK) >> RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_LSB)
+#define RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_LSB) & RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_MASK)
+#define RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_MSB 23
+#define RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_LSB 16
+#define RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_MASK 0x00ff0000
+#define RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_MASK) >> RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_LSB)
+#define RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_LSB) & RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_MASK)
+#define RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_MSB   15
+#define RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_LSB   8
+#define RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_MASK  0x0000ff00
+#define RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_MASK) >> RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_LSB)
+#define RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_LSB) & RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_MASK)
+#define RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_MSB  7
+#define RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_LSB  0
+#define RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_MASK 0x000000ff
+#define RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_MASK) >> RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_LSB)
+#define RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_LSB) & RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_MASK)
+
+#define RX_PRIORITY_THRESH3_ADDRESS              0x00008380
+#define RX_PRIORITY_THRESH3_OFFSET               0x00000380
+#define RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_MSB 15
+#define RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_LSB 8
+#define RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_MASK 0x0000ff00
+#define RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_MASK) >> RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_LSB)
+#define RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_LSB) & RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_MASK)
+#define RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_MSB   7
+#define RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_LSB   0
+#define RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_MASK  0x000000ff
+#define RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_MASK) >> RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_LSB)
+#define RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_LSB) & RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_MASK)
+
+#define RX_PRIORITY_OFFSET0_ADDRESS              0x00008384
+#define RX_PRIORITY_OFFSET0_OFFSET               0x00000384
+#define RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_MSB  29
+#define RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_LSB  24
+#define RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_MASK 0x3f000000
+#define RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_MASK) >> RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_LSB)
+#define RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_LSB) & RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_MASK)
+#define RX_PRIORITY_OFFSET0_RSSI_LOW_MSB         23
+#define RX_PRIORITY_OFFSET0_RSSI_LOW_LSB         18
+#define RX_PRIORITY_OFFSET0_RSSI_LOW_MASK        0x00fc0000
+#define RX_PRIORITY_OFFSET0_RSSI_LOW_GET(x)      (((x) & RX_PRIORITY_OFFSET0_RSSI_LOW_MASK) >> RX_PRIORITY_OFFSET0_RSSI_LOW_LSB)
+#define RX_PRIORITY_OFFSET0_RSSI_LOW_SET(x)      (((x) << RX_PRIORITY_OFFSET0_RSSI_LOW_LSB) & RX_PRIORITY_OFFSET0_RSSI_LOW_MASK)
+#define RX_PRIORITY_OFFSET0_RSSI_HIGH_MSB        17
+#define RX_PRIORITY_OFFSET0_RSSI_HIGH_LSB        12
+#define RX_PRIORITY_OFFSET0_RSSI_HIGH_MASK       0x0003f000
+#define RX_PRIORITY_OFFSET0_RSSI_HIGH_GET(x)     (((x) & RX_PRIORITY_OFFSET0_RSSI_HIGH_MASK) >> RX_PRIORITY_OFFSET0_RSSI_HIGH_LSB)
+#define RX_PRIORITY_OFFSET0_RSSI_HIGH_SET(x)     (((x) << RX_PRIORITY_OFFSET0_RSSI_HIGH_LSB) & RX_PRIORITY_OFFSET0_RSSI_HIGH_MASK)
+#define RX_PRIORITY_OFFSET0_PHY_RATE_LOW_MSB     11
+#define RX_PRIORITY_OFFSET0_PHY_RATE_LOW_LSB     6
+#define RX_PRIORITY_OFFSET0_PHY_RATE_LOW_MASK    0x00000fc0
+#define RX_PRIORITY_OFFSET0_PHY_RATE_LOW_GET(x)  (((x) & RX_PRIORITY_OFFSET0_PHY_RATE_LOW_MASK) >> RX_PRIORITY_OFFSET0_PHY_RATE_LOW_LSB)
+#define RX_PRIORITY_OFFSET0_PHY_RATE_LOW_SET(x)  (((x) << RX_PRIORITY_OFFSET0_PHY_RATE_LOW_LSB) & RX_PRIORITY_OFFSET0_PHY_RATE_LOW_MASK)
+#define RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_MSB    5
+#define RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_LSB    0
+#define RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_MASK   0x0000003f
+#define RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_MASK) >> RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_LSB)
+#define RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_LSB) & RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_MASK)
+
+#define RX_PRIORITY_OFFSET1_ADDRESS              0x00008388
+#define RX_PRIORITY_OFFSET1_OFFSET               0x00000388
+#define RX_PRIORITY_OFFSET1_RTS_MSB              29
+#define RX_PRIORITY_OFFSET1_RTS_LSB              24
+#define RX_PRIORITY_OFFSET1_RTS_MASK             0x3f000000
+#define RX_PRIORITY_OFFSET1_RTS_GET(x)           (((x) & RX_PRIORITY_OFFSET1_RTS_MASK) >> RX_PRIORITY_OFFSET1_RTS_LSB)
+#define RX_PRIORITY_OFFSET1_RTS_SET(x)           (((x) << RX_PRIORITY_OFFSET1_RTS_LSB) & RX_PRIORITY_OFFSET1_RTS_MASK)
+#define RX_PRIORITY_OFFSET1_RETX_MSB             23
+#define RX_PRIORITY_OFFSET1_RETX_LSB             18
+#define RX_PRIORITY_OFFSET1_RETX_MASK            0x00fc0000
+#define RX_PRIORITY_OFFSET1_RETX_GET(x)          (((x) & RX_PRIORITY_OFFSET1_RETX_MASK) >> RX_PRIORITY_OFFSET1_RETX_LSB)
+#define RX_PRIORITY_OFFSET1_RETX_SET(x)          (((x) << RX_PRIORITY_OFFSET1_RETX_LSB) & RX_PRIORITY_OFFSET1_RETX_MASK)
+#define RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_MSB  17
+#define RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_LSB  12
+#define RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_MASK 0x0003f000
+#define RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_MASK) >> RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_LSB)
+#define RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_LSB) & RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_MASK)
+#define RX_PRIORITY_OFFSET1_LENGTH_LOW_MSB       11
+#define RX_PRIORITY_OFFSET1_LENGTH_LOW_LSB       6
+#define RX_PRIORITY_OFFSET1_LENGTH_LOW_MASK      0x00000fc0
+#define RX_PRIORITY_OFFSET1_LENGTH_LOW_GET(x)    (((x) & RX_PRIORITY_OFFSET1_LENGTH_LOW_MASK) >> RX_PRIORITY_OFFSET1_LENGTH_LOW_LSB)
+#define RX_PRIORITY_OFFSET1_LENGTH_LOW_SET(x)    (((x) << RX_PRIORITY_OFFSET1_LENGTH_LOW_LSB) & RX_PRIORITY_OFFSET1_LENGTH_LOW_MASK)
+#define RX_PRIORITY_OFFSET1_LENGTH_HIGH_MSB      5
+#define RX_PRIORITY_OFFSET1_LENGTH_HIGH_LSB      0
+#define RX_PRIORITY_OFFSET1_LENGTH_HIGH_MASK     0x0000003f
+#define RX_PRIORITY_OFFSET1_LENGTH_HIGH_GET(x)   (((x) & RX_PRIORITY_OFFSET1_LENGTH_HIGH_MASK) >> RX_PRIORITY_OFFSET1_LENGTH_HIGH_LSB)
+#define RX_PRIORITY_OFFSET1_LENGTH_HIGH_SET(x)   (((x) << RX_PRIORITY_OFFSET1_LENGTH_HIGH_LSB) & RX_PRIORITY_OFFSET1_LENGTH_HIGH_MASK)
+
+#define RX_PRIORITY_OFFSET2_ADDRESS              0x0000838c
+#define RX_PRIORITY_OFFSET2_OFFSET               0x0000038c
+#define RX_PRIORITY_OFFSET2_BEACON_MSB           29
+#define RX_PRIORITY_OFFSET2_BEACON_LSB           24
+#define RX_PRIORITY_OFFSET2_BEACON_MASK          0x3f000000
+#define RX_PRIORITY_OFFSET2_BEACON_GET(x)        (((x) & RX_PRIORITY_OFFSET2_BEACON_MASK) >> RX_PRIORITY_OFFSET2_BEACON_LSB)
+#define RX_PRIORITY_OFFSET2_BEACON_SET(x)        (((x) << RX_PRIORITY_OFFSET2_BEACON_LSB) & RX_PRIORITY_OFFSET2_BEACON_MASK)
+#define RX_PRIORITY_OFFSET2_MGMT_MSB             23
+#define RX_PRIORITY_OFFSET2_MGMT_LSB             18
+#define RX_PRIORITY_OFFSET2_MGMT_MASK            0x00fc0000
+#define RX_PRIORITY_OFFSET2_MGMT_GET(x)          (((x) & RX_PRIORITY_OFFSET2_MGMT_MASK) >> RX_PRIORITY_OFFSET2_MGMT_LSB)
+#define RX_PRIORITY_OFFSET2_MGMT_SET(x)          (((x) << RX_PRIORITY_OFFSET2_MGMT_LSB) & RX_PRIORITY_OFFSET2_MGMT_MASK)
+#define RX_PRIORITY_OFFSET2_ATIM_MSB             17
+#define RX_PRIORITY_OFFSET2_ATIM_LSB             12
+#define RX_PRIORITY_OFFSET2_ATIM_MASK            0x0003f000
+#define RX_PRIORITY_OFFSET2_ATIM_GET(x)          (((x) & RX_PRIORITY_OFFSET2_ATIM_MASK) >> RX_PRIORITY_OFFSET2_ATIM_LSB)
+#define RX_PRIORITY_OFFSET2_ATIM_SET(x)          (((x) << RX_PRIORITY_OFFSET2_ATIM_LSB) & RX_PRIORITY_OFFSET2_ATIM_MASK)
+#define RX_PRIORITY_OFFSET2_PRESP_MSB            11
+#define RX_PRIORITY_OFFSET2_PRESP_LSB            6
+#define RX_PRIORITY_OFFSET2_PRESP_MASK           0x00000fc0
+#define RX_PRIORITY_OFFSET2_PRESP_GET(x)         (((x) & RX_PRIORITY_OFFSET2_PRESP_MASK) >> RX_PRIORITY_OFFSET2_PRESP_LSB)
+#define RX_PRIORITY_OFFSET2_PRESP_SET(x)         (((x) << RX_PRIORITY_OFFSET2_PRESP_LSB) & RX_PRIORITY_OFFSET2_PRESP_MASK)
+#define RX_PRIORITY_OFFSET2_XCAST_MSB            5
+#define RX_PRIORITY_OFFSET2_XCAST_LSB            0
+#define RX_PRIORITY_OFFSET2_XCAST_MASK           0x0000003f
+#define RX_PRIORITY_OFFSET2_XCAST_GET(x)         (((x) & RX_PRIORITY_OFFSET2_XCAST_MASK) >> RX_PRIORITY_OFFSET2_XCAST_LSB)
+#define RX_PRIORITY_OFFSET2_XCAST_SET(x)         (((x) << RX_PRIORITY_OFFSET2_XCAST_LSB) & RX_PRIORITY_OFFSET2_XCAST_MASK)
+
+#define RX_PRIORITY_OFFSET3_ADDRESS              0x00008390
+#define RX_PRIORITY_OFFSET3_OFFSET               0x00000390
+#define RX_PRIORITY_OFFSET3_PS_POLL_MSB          29
+#define RX_PRIORITY_OFFSET3_PS_POLL_LSB          24
+#define RX_PRIORITY_OFFSET3_PS_POLL_MASK         0x3f000000
+#define RX_PRIORITY_OFFSET3_PS_POLL_GET(x)       (((x) & RX_PRIORITY_OFFSET3_PS_POLL_MASK) >> RX_PRIORITY_OFFSET3_PS_POLL_LSB)
+#define RX_PRIORITY_OFFSET3_PS_POLL_SET(x)       (((x) << RX_PRIORITY_OFFSET3_PS_POLL_LSB) & RX_PRIORITY_OFFSET3_PS_POLL_MASK)
+#define RX_PRIORITY_OFFSET3_AMSDU_MSB            23
+#define RX_PRIORITY_OFFSET3_AMSDU_LSB            18
+#define RX_PRIORITY_OFFSET3_AMSDU_MASK           0x00fc0000
+#define RX_PRIORITY_OFFSET3_AMSDU_GET(x)         (((x) & RX_PRIORITY_OFFSET3_AMSDU_MASK) >> RX_PRIORITY_OFFSET3_AMSDU_LSB)
+#define RX_PRIORITY_OFFSET3_AMSDU_SET(x)         (((x) << RX_PRIORITY_OFFSET3_AMSDU_LSB) & RX_PRIORITY_OFFSET3_AMSDU_MASK)
+#define RX_PRIORITY_OFFSET3_AMPDU_MSB            17
+#define RX_PRIORITY_OFFSET3_AMPDU_LSB            12
+#define RX_PRIORITY_OFFSET3_AMPDU_MASK           0x0003f000
+#define RX_PRIORITY_OFFSET3_AMPDU_GET(x)         (((x) & RX_PRIORITY_OFFSET3_AMPDU_MASK) >> RX_PRIORITY_OFFSET3_AMPDU_LSB)
+#define RX_PRIORITY_OFFSET3_AMPDU_SET(x)         (((x) << RX_PRIORITY_OFFSET3_AMPDU_LSB) & RX_PRIORITY_OFFSET3_AMPDU_MASK)
+#define RX_PRIORITY_OFFSET3_EOSP_MSB             11
+#define RX_PRIORITY_OFFSET3_EOSP_LSB             6
+#define RX_PRIORITY_OFFSET3_EOSP_MASK            0x00000fc0
+#define RX_PRIORITY_OFFSET3_EOSP_GET(x)          (((x) & RX_PRIORITY_OFFSET3_EOSP_MASK) >> RX_PRIORITY_OFFSET3_EOSP_LSB)
+#define RX_PRIORITY_OFFSET3_EOSP_SET(x)          (((x) << RX_PRIORITY_OFFSET3_EOSP_LSB) & RX_PRIORITY_OFFSET3_EOSP_MASK)
+#define RX_PRIORITY_OFFSET3_MORE_MSB             5
+#define RX_PRIORITY_OFFSET3_MORE_LSB             0
+#define RX_PRIORITY_OFFSET3_MORE_MASK            0x0000003f
+#define RX_PRIORITY_OFFSET3_MORE_GET(x)          (((x) & RX_PRIORITY_OFFSET3_MORE_MASK) >> RX_PRIORITY_OFFSET3_MORE_LSB)
+#define RX_PRIORITY_OFFSET3_MORE_SET(x)          (((x) << RX_PRIORITY_OFFSET3_MORE_LSB) & RX_PRIORITY_OFFSET3_MORE_MASK)
+
+#define RX_PRIORITY_OFFSET4_ADDRESS              0x00008394
+#define RX_PRIORITY_OFFSET4_OFFSET               0x00000394
+#define RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_MSB 29
+#define RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_LSB 24
+#define RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_MASK 0x3f000000
+#define RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_MASK) >> RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_LSB)
+#define RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_LSB) & RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_MASK)
+#define RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_MSB   23
+#define RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_LSB   18
+#define RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_MASK  0x00fc0000
+#define RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_MASK) >> RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_LSB)
+#define RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_LSB) & RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_MASK)
+#define RX_PRIORITY_OFFSET4_BEACON_SSID_MSB      17
+#define RX_PRIORITY_OFFSET4_BEACON_SSID_LSB      12
+#define RX_PRIORITY_OFFSET4_BEACON_SSID_MASK     0x0003f000
+#define RX_PRIORITY_OFFSET4_BEACON_SSID_GET(x)   (((x) & RX_PRIORITY_OFFSET4_BEACON_SSID_MASK) >> RX_PRIORITY_OFFSET4_BEACON_SSID_LSB)
+#define RX_PRIORITY_OFFSET4_BEACON_SSID_SET(x)   (((x) << RX_PRIORITY_OFFSET4_BEACON_SSID_LSB) & RX_PRIORITY_OFFSET4_BEACON_SSID_MASK)
+#define RX_PRIORITY_OFFSET4_NULL_MSB             11
+#define RX_PRIORITY_OFFSET4_NULL_LSB             6
+#define RX_PRIORITY_OFFSET4_NULL_MASK            0x00000fc0
+#define RX_PRIORITY_OFFSET4_NULL_GET(x)          (((x) & RX_PRIORITY_OFFSET4_NULL_MASK) >> RX_PRIORITY_OFFSET4_NULL_LSB)
+#define RX_PRIORITY_OFFSET4_NULL_SET(x)          (((x) << RX_PRIORITY_OFFSET4_NULL_LSB) & RX_PRIORITY_OFFSET4_NULL_MASK)
+#define RX_PRIORITY_OFFSET4_PREQ_MSB             5
+#define RX_PRIORITY_OFFSET4_PREQ_LSB             0
+#define RX_PRIORITY_OFFSET4_PREQ_MASK            0x0000003f
+#define RX_PRIORITY_OFFSET4_PREQ_GET(x)          (((x) & RX_PRIORITY_OFFSET4_PREQ_MASK) >> RX_PRIORITY_OFFSET4_PREQ_LSB)
+#define RX_PRIORITY_OFFSET4_PREQ_SET(x)          (((x) << RX_PRIORITY_OFFSET4_PREQ_LSB) & RX_PRIORITY_OFFSET4_PREQ_MASK)
+
+#define RX_PRIORITY_OFFSET5_ADDRESS              0x00008398
+#define RX_PRIORITY_OFFSET5_OFFSET               0x00000398
+#define RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_MSB 17
+#define RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_LSB 12
+#define RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_MASK 0x0003f000
+#define RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_MASK) >> RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_LSB)
+#define RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_LSB) & RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_MASK)
+#define RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_MSB   11
+#define RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_LSB   6
+#define RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_MASK  0x00000fc0
+#define RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_MASK) >> RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_LSB)
+#define RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_LSB) & RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_MASK)
+#define RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_MSB   5
+#define RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_LSB   0
+#define RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_MASK  0x0000003f
+#define RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_MASK) >> RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_LSB)
+#define RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_LSB) & RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_MASK)
+
+#define MAC_PCU_BSSID2_L32_ADDRESS               0x0000839c
+#define MAC_PCU_BSSID2_L32_OFFSET                0x0000039c
+#define MAC_PCU_BSSID2_L32_ADDR_MSB              31
+#define MAC_PCU_BSSID2_L32_ADDR_LSB              0
+#define MAC_PCU_BSSID2_L32_ADDR_MASK             0xffffffff
+#define MAC_PCU_BSSID2_L32_ADDR_GET(x)           (((x) & MAC_PCU_BSSID2_L32_ADDR_MASK) >> MAC_PCU_BSSID2_L32_ADDR_LSB)
+#define MAC_PCU_BSSID2_L32_ADDR_SET(x)           (((x) << MAC_PCU_BSSID2_L32_ADDR_LSB) & MAC_PCU_BSSID2_L32_ADDR_MASK)
+
+#define MAC_PCU_BSSID2_U16_ADDRESS               0x000083a0
+#define MAC_PCU_BSSID2_U16_OFFSET                0x000003a0
+#define MAC_PCU_BSSID2_U16_ENABLE_MSB            16
+#define MAC_PCU_BSSID2_U16_ENABLE_LSB            16
+#define MAC_PCU_BSSID2_U16_ENABLE_MASK           0x00010000
+#define MAC_PCU_BSSID2_U16_ENABLE_GET(x)         (((x) & MAC_PCU_BSSID2_U16_ENABLE_MASK) >> MAC_PCU_BSSID2_U16_ENABLE_LSB)
+#define MAC_PCU_BSSID2_U16_ENABLE_SET(x)         (((x) << MAC_PCU_BSSID2_U16_ENABLE_LSB) & MAC_PCU_BSSID2_U16_ENABLE_MASK)
+#define MAC_PCU_BSSID2_U16_ADDR_MSB              15
+#define MAC_PCU_BSSID2_U16_ADDR_LSB              0
+#define MAC_PCU_BSSID2_U16_ADDR_MASK             0x0000ffff
+#define MAC_PCU_BSSID2_U16_ADDR_GET(x)           (((x) & MAC_PCU_BSSID2_U16_ADDR_MASK) >> MAC_PCU_BSSID2_U16_ADDR_LSB)
+#define MAC_PCU_BSSID2_U16_ADDR_SET(x)           (((x) << MAC_PCU_BSSID2_U16_ADDR_LSB) & MAC_PCU_BSSID2_U16_ADDR_MASK)
+
+#define MAC_PCU_TSF1_STATUS_L32_ADDRESS          0x000083a4
+#define MAC_PCU_TSF1_STATUS_L32_OFFSET           0x000003a4
+#define MAC_PCU_TSF1_STATUS_L32_VALUE_MSB        31
+#define MAC_PCU_TSF1_STATUS_L32_VALUE_LSB        0
+#define MAC_PCU_TSF1_STATUS_L32_VALUE_MASK       0xffffffff
+#define MAC_PCU_TSF1_STATUS_L32_VALUE_GET(x)     (((x) & MAC_PCU_TSF1_STATUS_L32_VALUE_MASK) >> MAC_PCU_TSF1_STATUS_L32_VALUE_LSB)
+#define MAC_PCU_TSF1_STATUS_L32_VALUE_SET(x)     (((x) << MAC_PCU_TSF1_STATUS_L32_VALUE_LSB) & MAC_PCU_TSF1_STATUS_L32_VALUE_MASK)
+
+#define MAC_PCU_TSF1_STATUS_U32_ADDRESS          0x000083a8
+#define MAC_PCU_TSF1_STATUS_U32_OFFSET           0x000003a8
+#define MAC_PCU_TSF1_STATUS_U32_VALUE_MSB        31
+#define MAC_PCU_TSF1_STATUS_U32_VALUE_LSB        0
+#define MAC_PCU_TSF1_STATUS_U32_VALUE_MASK       0xffffffff
+#define MAC_PCU_TSF1_STATUS_U32_VALUE_GET(x)     (((x) & MAC_PCU_TSF1_STATUS_U32_VALUE_MASK) >> MAC_PCU_TSF1_STATUS_U32_VALUE_LSB)
+#define MAC_PCU_TSF1_STATUS_U32_VALUE_SET(x)     (((x) << MAC_PCU_TSF1_STATUS_U32_VALUE_LSB) & MAC_PCU_TSF1_STATUS_U32_VALUE_MASK)
+
+#define MAC_PCU_TSF2_STATUS_L32_ADDRESS          0x000083ac
+#define MAC_PCU_TSF2_STATUS_L32_OFFSET           0x000003ac
+#define MAC_PCU_TSF2_STATUS_L32_VALUE_MSB        31
+#define MAC_PCU_TSF2_STATUS_L32_VALUE_LSB        0
+#define MAC_PCU_TSF2_STATUS_L32_VALUE_MASK       0xffffffff
+#define MAC_PCU_TSF2_STATUS_L32_VALUE_GET(x)     (((x) & MAC_PCU_TSF2_STATUS_L32_VALUE_MASK) >> MAC_PCU_TSF2_STATUS_L32_VALUE_LSB)
+#define MAC_PCU_TSF2_STATUS_L32_VALUE_SET(x)     (((x) << MAC_PCU_TSF2_STATUS_L32_VALUE_LSB) & MAC_PCU_TSF2_STATUS_L32_VALUE_MASK)
+
+#define MAC_PCU_TSF2_STATUS_U32_ADDRESS          0x000083b0
+#define MAC_PCU_TSF2_STATUS_U32_OFFSET           0x000003b0
+#define MAC_PCU_TSF2_STATUS_U32_VALUE_MSB        31
+#define MAC_PCU_TSF2_STATUS_U32_VALUE_LSB        0
+#define MAC_PCU_TSF2_STATUS_U32_VALUE_MASK       0xffffffff
+#define MAC_PCU_TSF2_STATUS_U32_VALUE_GET(x)     (((x) & MAC_PCU_TSF2_STATUS_U32_VALUE_MASK) >> MAC_PCU_TSF2_STATUS_U32_VALUE_LSB)
+#define MAC_PCU_TSF2_STATUS_U32_VALUE_SET(x)     (((x) << MAC_PCU_TSF2_STATUS_U32_VALUE_LSB) & MAC_PCU_TSF2_STATUS_U32_VALUE_MASK)
+
+#define MAC_PCU_TXBUF_BA_ADDRESS                 0x00008400
+#define MAC_PCU_TXBUF_BA_OFFSET                  0x00000400
+#define MAC_PCU_TXBUF_BA_DATA_MSB                31
+#define MAC_PCU_TXBUF_BA_DATA_LSB                0
+#define MAC_PCU_TXBUF_BA_DATA_MASK               0xffffffff
+#define MAC_PCU_TXBUF_BA_DATA_GET(x)             (((x) & MAC_PCU_TXBUF_BA_DATA_MASK) >> MAC_PCU_TXBUF_BA_DATA_LSB)
+#define MAC_PCU_TXBUF_BA_DATA_SET(x)             (((x) << MAC_PCU_TXBUF_BA_DATA_LSB) & MAC_PCU_TXBUF_BA_DATA_MASK)
+
+#define MAC_PCU_KEY_CACHE_1_ADDRESS              0x00008800
+#define MAC_PCU_KEY_CACHE_1_OFFSET               0x00000800
+#define MAC_PCU_KEY_CACHE_1_DATA_MSB             31
+#define MAC_PCU_KEY_CACHE_1_DATA_LSB             0
+#define MAC_PCU_KEY_CACHE_1_DATA_MASK            0xffffffff
+#define MAC_PCU_KEY_CACHE_1_DATA_GET(x)          (((x) & MAC_PCU_KEY_CACHE_1_DATA_MASK) >> MAC_PCU_KEY_CACHE_1_DATA_LSB)
+#define MAC_PCU_KEY_CACHE_1_DATA_SET(x)          (((x) << MAC_PCU_KEY_CACHE_1_DATA_LSB) & MAC_PCU_KEY_CACHE_1_DATA_MASK)
+
+#define MAC_PCU_BASEBAND_0_ADDRESS               0x00009800
+#define MAC_PCU_BASEBAND_0_OFFSET                0x00001800
+#define MAC_PCU_BASEBAND_0_DATA_MSB              31
+#define MAC_PCU_BASEBAND_0_DATA_LSB              0
+#define MAC_PCU_BASEBAND_0_DATA_MASK             0xffffffff
+#define MAC_PCU_BASEBAND_0_DATA_GET(x)           (((x) & MAC_PCU_BASEBAND_0_DATA_MASK) >> MAC_PCU_BASEBAND_0_DATA_LSB)
+#define MAC_PCU_BASEBAND_0_DATA_SET(x)           (((x) << MAC_PCU_BASEBAND_0_DATA_LSB) & MAC_PCU_BASEBAND_0_DATA_MASK)
+
+#define MAC_PCU_BASEBAND_1_ADDRESS               0x0000a000
+#define MAC_PCU_BASEBAND_1_OFFSET                0x00002000
+#define MAC_PCU_BASEBAND_1_DATA_MSB              31
+#define MAC_PCU_BASEBAND_1_DATA_LSB              0
+#define MAC_PCU_BASEBAND_1_DATA_MASK             0xffffffff
+#define MAC_PCU_BASEBAND_1_DATA_GET(x)           (((x) & MAC_PCU_BASEBAND_1_DATA_MASK) >> MAC_PCU_BASEBAND_1_DATA_LSB)
+#define MAC_PCU_BASEBAND_1_DATA_SET(x)           (((x) << MAC_PCU_BASEBAND_1_DATA_LSB) & MAC_PCU_BASEBAND_1_DATA_MASK)
+
+#define MAC_PCU_BASEBAND_2_ADDRESS               0x0000c000
+#define MAC_PCU_BASEBAND_2_OFFSET                0x00004000
+#define MAC_PCU_BASEBAND_2_DATA_MSB              31
+#define MAC_PCU_BASEBAND_2_DATA_LSB              0
+#define MAC_PCU_BASEBAND_2_DATA_MASK             0xffffffff
+#define MAC_PCU_BASEBAND_2_DATA_GET(x)           (((x) & MAC_PCU_BASEBAND_2_DATA_MASK) >> MAC_PCU_BASEBAND_2_DATA_LSB)
+#define MAC_PCU_BASEBAND_2_DATA_SET(x)           (((x) << MAC_PCU_BASEBAND_2_DATA_LSB) & MAC_PCU_BASEBAND_2_DATA_MASK)
+
+#define MAC_PCU_BASEBAND_3_ADDRESS               0x0000d000
+#define MAC_PCU_BASEBAND_3_OFFSET                0x00005000
+#define MAC_PCU_BASEBAND_3_DATA_MSB              31
+#define MAC_PCU_BASEBAND_3_DATA_LSB              0
+#define MAC_PCU_BASEBAND_3_DATA_MASK             0xffffffff
+#define MAC_PCU_BASEBAND_3_DATA_GET(x)           (((x) & MAC_PCU_BASEBAND_3_DATA_MASK) >> MAC_PCU_BASEBAND_3_DATA_LSB)
+#define MAC_PCU_BASEBAND_3_DATA_SET(x)           (((x) << MAC_PCU_BASEBAND_3_DATA_LSB) & MAC_PCU_BASEBAND_3_DATA_MASK)
+
+#define MAC_PCU_BUF_ADDRESS                      0x0000e000
+#define MAC_PCU_BUF_OFFSET                       0x00006000
+#define MAC_PCU_BUF_DATA_MSB                     31
+#define MAC_PCU_BUF_DATA_LSB                     0
+#define MAC_PCU_BUF_DATA_MASK                    0xffffffff
+#define MAC_PCU_BUF_DATA_GET(x)                  (((x) & MAC_PCU_BUF_DATA_MASK) >> MAC_PCU_BUF_DATA_LSB)
+#define MAC_PCU_BUF_DATA_SET(x)                  (((x) << MAC_PCU_BUF_DATA_LSB) & MAC_PCU_BUF_DATA_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct mac_pcu_reg_s {
+  volatile unsigned int mac_pcu_sta_addr_l32;
+  volatile unsigned int mac_pcu_sta_addr_u16;
+  volatile unsigned int mac_pcu_bssid_l32;
+  volatile unsigned int mac_pcu_bssid_u16;
+  volatile unsigned int mac_pcu_bcn_rssi_ave;
+  volatile unsigned int mac_pcu_ack_cts_timeout;
+  volatile unsigned int mac_pcu_bcn_rssi_ctl;
+  volatile unsigned int mac_pcu_usec_latency;
+  volatile unsigned int pcu_max_cfp_dur;
+  volatile unsigned int mac_pcu_rx_filter;
+  volatile unsigned int mac_pcu_mcast_filter_l32;
+  volatile unsigned int mac_pcu_mcast_filter_u32;
+  volatile unsigned int mac_pcu_diag_sw;
+  volatile unsigned int mac_pcu_tst_addac;
+  volatile unsigned int mac_pcu_def_antenna;
+  volatile unsigned int mac_pcu_aes_mute_mask_0;
+  volatile unsigned int mac_pcu_aes_mute_mask_1;
+  volatile unsigned int mac_pcu_gated_clks;
+  volatile unsigned int mac_pcu_obs_bus_2;
+  volatile unsigned int mac_pcu_obs_bus_1;
+  volatile unsigned int mac_pcu_dym_mimo_pwr_save;
+  volatile unsigned int mac_pcu_last_beacon_tsf;
+  volatile unsigned int mac_pcu_nav;
+  volatile unsigned int mac_pcu_rts_success_cnt;
+  volatile unsigned int mac_pcu_rts_fail_cnt;
+  volatile unsigned int mac_pcu_ack_fail_cnt;
+  volatile unsigned int mac_pcu_fcs_fail_cnt;
+  volatile unsigned int mac_pcu_beacon_cnt;
+  volatile unsigned int mac_pcu_xrmode;
+  volatile unsigned int mac_pcu_xrdel;
+  volatile unsigned int mac_pcu_xrto;
+  volatile unsigned int mac_pcu_xrcrp;
+  volatile unsigned int mac_pcu_xrstmp;
+  volatile unsigned int mac_pcu_addr1_mask_l32;
+  volatile unsigned int mac_pcu_addr1_mask_u16;
+  volatile unsigned int mac_pcu_tpc;
+  volatile unsigned int mac_pcu_tx_frame_cnt;
+  volatile unsigned int mac_pcu_rx_frame_cnt;
+  volatile unsigned int mac_pcu_rx_clear_cnt;
+  volatile unsigned int mac_pcu_cycle_cnt;
+  volatile unsigned int mac_pcu_quiet_time_1;
+  volatile unsigned int mac_pcu_quiet_time_2;
+  volatile unsigned int mac_pcu_qos_no_ack;
+  volatile unsigned int mac_pcu_phy_error_mask;
+  volatile unsigned int mac_pcu_xrlat;
+  volatile unsigned int mac_pcu_rxbuf;
+  volatile unsigned int mac_pcu_mic_qos_control;
+  volatile unsigned int mac_pcu_mic_qos_select;
+  volatile unsigned int mac_pcu_misc_mode;
+  volatile unsigned int mac_pcu_filter_ofdm_cnt;
+  volatile unsigned int mac_pcu_filter_cck_cnt;
+  volatile unsigned int mac_pcu_phy_err_cnt_1;
+  volatile unsigned int mac_pcu_phy_err_cnt_1_mask;
+  volatile unsigned int mac_pcu_phy_err_cnt_2;
+  volatile unsigned int mac_pcu_phy_err_cnt_2_mask;
+  volatile unsigned int mac_pcu_tsf_threshold;
+  volatile unsigned int mac_pcu_phy_error_eifs_mask;
+  volatile unsigned int mac_pcu_phy_err_cnt_3;
+  volatile unsigned int mac_pcu_phy_err_cnt_3_mask;
+  volatile unsigned int mac_pcu_bluetooth_mode;
+  volatile unsigned int mac_pcu_bluetooth_weights;
+  volatile unsigned int mac_pcu_bluetooth_mode2;
+  volatile unsigned int mac_pcu_txsifs;
+  volatile unsigned int mac_pcu_txop_x;
+  volatile unsigned int mac_pcu_txop_0_3;
+  volatile unsigned int mac_pcu_txop_4_7;
+  volatile unsigned int mac_pcu_txop_8_11;
+  volatile unsigned int mac_pcu_txop_12_15;
+  volatile unsigned int mac_pcu_logic_analyzer;
+  volatile unsigned int mac_pcu_logic_analyzer_32l;
+  volatile unsigned int mac_pcu_logic_analyzer_16u;
+  volatile unsigned int mac_pcu_phy_err_cnt_mask_cont;
+  volatile unsigned int mac_pcu_azimuth_mode;
+  volatile unsigned int mac_pcu_20_40_mode;
+  volatile unsigned int mac_pcu_rx_clear_diff_cnt;
+  volatile unsigned int mac_pcu_self_gen_antenna_mask;
+  volatile unsigned int mac_pcu_ba_bar_control;
+  volatile unsigned int mac_pcu_legacy_plcp_spoof;
+  volatile unsigned int mac_pcu_phy_error_mask_cont;
+  volatile unsigned int mac_pcu_tx_timer;
+  volatile unsigned int mac_pcu_txbuf_ctrl;
+  volatile unsigned int mac_pcu_misc_mode2;
+  volatile unsigned int mac_pcu_alt_aes_mute_mask;
+  volatile unsigned int mac_pcu_azimuth_time_stamp;
+  volatile unsigned int mac_pcu_max_cfp_dur;
+  volatile unsigned int mac_pcu_hcf_timeout;
+  volatile unsigned int mac_pcu_bluetooth_weights2;
+  volatile unsigned int mac_pcu_bluetooth_tsf_bt_active;
+  volatile unsigned int mac_pcu_bluetooth_tsf_bt_priority;
+  volatile unsigned int mac_pcu_bluetooth_mode3;
+  volatile unsigned int mac_pcu_bluetooth_mode4;
+  unsigned char pad0[148]; /* pad to 0x200 */
+  volatile unsigned int mac_pcu_bt_bt[64];
+  volatile unsigned int mac_pcu_bt_bt_async;
+  volatile unsigned int mac_pcu_bt_wl_1;
+  volatile unsigned int mac_pcu_bt_wl_2;
+  volatile unsigned int mac_pcu_bt_wl_3;
+  volatile unsigned int mac_pcu_bt_wl_4;
+  volatile unsigned int mac_pcu_coex_epta;
+  volatile unsigned int mac_pcu_coex_lnamaxgain1;
+  volatile unsigned int mac_pcu_coex_lnamaxgain2;
+  volatile unsigned int mac_pcu_coex_lnamaxgain3;
+  volatile unsigned int mac_pcu_coex_lnamaxgain4;
+  volatile unsigned int mac_pcu_basic_rate_set0;
+  volatile unsigned int mac_pcu_basic_rate_set1;
+  volatile unsigned int mac_pcu_basic_rate_set2;
+  volatile unsigned int mac_pcu_basic_rate_set3;
+  volatile unsigned int mac_pcu_rx_int_status0;
+  volatile unsigned int mac_pcu_rx_int_status1;
+  volatile unsigned int mac_pcu_rx_int_status2;
+  volatile unsigned int mac_pcu_rx_int_status3;
+  volatile unsigned int ht_half_gi_rate1;
+  volatile unsigned int ht_half_gi_rate2;
+  volatile unsigned int ht_full_gi_rate1;
+  volatile unsigned int ht_full_gi_rate2;
+  volatile unsigned int legacy_rate1;
+  volatile unsigned int legacy_rate2;
+  volatile unsigned int legacy_rate3;
+  volatile unsigned int rx_int_filter;
+  volatile unsigned int rx_int_overflow;
+  volatile unsigned int rx_filter_thresh;
+  volatile unsigned int rx_filter_thresh1;
+  volatile unsigned int rx_priority_thresh0;
+  volatile unsigned int rx_priority_thresh1;
+  volatile unsigned int rx_priority_thresh2;
+  volatile unsigned int rx_priority_thresh3;
+  volatile unsigned int rx_priority_offset0;
+  volatile unsigned int rx_priority_offset1;
+  volatile unsigned int rx_priority_offset2;
+  volatile unsigned int rx_priority_offset3;
+  volatile unsigned int rx_priority_offset4;
+  volatile unsigned int rx_priority_offset5;
+  volatile unsigned int mac_pcu_bssid2_l32;
+  volatile unsigned int mac_pcu_bssid2_u16;
+  volatile unsigned int mac_pcu_tsf1_status_l32;
+  volatile unsigned int mac_pcu_tsf1_status_u32;
+  volatile unsigned int mac_pcu_tsf2_status_l32;
+  volatile unsigned int mac_pcu_tsf2_status_u32;
+  unsigned char pad1[76]; /* pad to 0x400 */
+  volatile unsigned int mac_pcu_txbuf_ba[64];
+  unsigned char pad2[768]; /* pad to 0x800 */
+  volatile unsigned int mac_pcu_key_cache_1[256];
+  unsigned char pad3[3072]; /* pad to 0x1800 */
+  volatile unsigned int mac_pcu_baseband_0[512];
+  volatile unsigned int mac_pcu_baseband_1[2048];
+  volatile unsigned int mac_pcu_baseband_2[1024];
+  volatile unsigned int mac_pcu_baseband_3[1024];
+  volatile unsigned int mac_pcu_buf[512];
+} mac_pcu_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _MAC_PCU_H_ */
diff --git a/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/mbox_host_reg.h b/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/mbox_host_reg.h
new file mode 100644
index 00000000000..3af562156f6
--- /dev/null
+++ b/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/mbox_host_reg.h
@@ -0,0 +1,37 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifdef WLAN_HEADERS
+
+#include "mbox_wlan_host_reg.h"
+
+
+#ifndef BT_HEADERS
+
+
+
+#endif
+#endif
+
+
+
diff --git a/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/mbox_reg.h b/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/mbox_reg.h
new file mode 100644
index 00000000000..cc67585e2e8
--- /dev/null
+++ b/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/mbox_reg.h
@@ -0,0 +1,560 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifdef WLAN_HEADERS
+
+#include "mbox_wlan_reg.h"
+
+
+#ifndef BT_HEADERS
+
+#define MBOX_FIFO_ADDRESS WLAN_MBOX_FIFO_ADDRESS
+#define MBOX_FIFO_OFFSET WLAN_MBOX_FIFO_OFFSET
+#define MBOX_FIFO_DATA_MSB WLAN_MBOX_FIFO_DATA_MSB
+#define MBOX_FIFO_DATA_LSB WLAN_MBOX_FIFO_DATA_LSB
+#define MBOX_FIFO_DATA_MASK WLAN_MBOX_FIFO_DATA_MASK
+#define MBOX_FIFO_DATA_GET(x) WLAN_MBOX_FIFO_DATA_GET(x)
+#define MBOX_FIFO_DATA_SET(x) WLAN_MBOX_FIFO_DATA_SET(x)
+#define MBOX_FIFO_STATUS_ADDRESS WLAN_MBOX_FIFO_STATUS_ADDRESS
+#define MBOX_FIFO_STATUS_OFFSET WLAN_MBOX_FIFO_STATUS_OFFSET
+#define MBOX_FIFO_STATUS_EMPTY_MSB WLAN_MBOX_FIFO_STATUS_EMPTY_MSB
+#define MBOX_FIFO_STATUS_EMPTY_LSB WLAN_MBOX_FIFO_STATUS_EMPTY_LSB
+#define MBOX_FIFO_STATUS_EMPTY_MASK WLAN_MBOX_FIFO_STATUS_EMPTY_MASK
+#define MBOX_FIFO_STATUS_EMPTY_GET(x) WLAN_MBOX_FIFO_STATUS_EMPTY_GET(x)
+#define MBOX_FIFO_STATUS_EMPTY_SET(x) WLAN_MBOX_FIFO_STATUS_EMPTY_SET(x)
+#define MBOX_FIFO_STATUS_FULL_MSB WLAN_MBOX_FIFO_STATUS_FULL_MSB
+#define MBOX_FIFO_STATUS_FULL_LSB WLAN_MBOX_FIFO_STATUS_FULL_LSB
+#define MBOX_FIFO_STATUS_FULL_MASK WLAN_MBOX_FIFO_STATUS_FULL_MASK
+#define MBOX_FIFO_STATUS_FULL_GET(x) WLAN_MBOX_FIFO_STATUS_FULL_GET(x)
+#define MBOX_FIFO_STATUS_FULL_SET(x) WLAN_MBOX_FIFO_STATUS_FULL_SET(x)
+#define MBOX_DMA_POLICY_ADDRESS WLAN_MBOX_DMA_POLICY_ADDRESS
+#define MBOX_DMA_POLICY_OFFSET WLAN_MBOX_DMA_POLICY_OFFSET
+#define MBOX_DMA_POLICY_TX_QUANTUM_MSB WLAN_MBOX_DMA_POLICY_TX_QUANTUM_MSB
+#define MBOX_DMA_POLICY_TX_QUANTUM_LSB WLAN_MBOX_DMA_POLICY_TX_QUANTUM_LSB
+#define MBOX_DMA_POLICY_TX_QUANTUM_MASK WLAN_MBOX_DMA_POLICY_TX_QUANTUM_MASK
+#define MBOX_DMA_POLICY_TX_QUANTUM_GET(x) WLAN_MBOX_DMA_POLICY_TX_QUANTUM_GET(x)
+#define MBOX_DMA_POLICY_TX_QUANTUM_SET(x) WLAN_MBOX_DMA_POLICY_TX_QUANTUM_SET(x)
+#define MBOX_DMA_POLICY_TX_ORDER_MSB WLAN_MBOX_DMA_POLICY_TX_ORDER_MSB
+#define MBOX_DMA_POLICY_TX_ORDER_LSB WLAN_MBOX_DMA_POLICY_TX_ORDER_LSB
+#define MBOX_DMA_POLICY_TX_ORDER_MASK WLAN_MBOX_DMA_POLICY_TX_ORDER_MASK
+#define MBOX_DMA_POLICY_TX_ORDER_GET(x) WLAN_MBOX_DMA_POLICY_TX_ORDER_GET(x)
+#define MBOX_DMA_POLICY_TX_ORDER_SET(x) WLAN_MBOX_DMA_POLICY_TX_ORDER_SET(x)
+#define MBOX_DMA_POLICY_RX_QUANTUM_MSB WLAN_MBOX_DMA_POLICY_RX_QUANTUM_MSB
+#define MBOX_DMA_POLICY_RX_QUANTUM_LSB WLAN_MBOX_DMA_POLICY_RX_QUANTUM_LSB
+#define MBOX_DMA_POLICY_RX_QUANTUM_MASK WLAN_MBOX_DMA_POLICY_RX_QUANTUM_MASK
+#define MBOX_DMA_POLICY_RX_QUANTUM_GET(x) WLAN_MBOX_DMA_POLICY_RX_QUANTUM_GET(x)
+#define MBOX_DMA_POLICY_RX_QUANTUM_SET(x) WLAN_MBOX_DMA_POLICY_RX_QUANTUM_SET(x)
+#define MBOX_DMA_POLICY_RX_ORDER_MSB WLAN_MBOX_DMA_POLICY_RX_ORDER_MSB
+#define MBOX_DMA_POLICY_RX_ORDER_LSB WLAN_MBOX_DMA_POLICY_RX_ORDER_LSB
+#define MBOX_DMA_POLICY_RX_ORDER_MASK WLAN_MBOX_DMA_POLICY_RX_ORDER_MASK
+#define MBOX_DMA_POLICY_RX_ORDER_GET(x) WLAN_MBOX_DMA_POLICY_RX_ORDER_GET(x)
+#define MBOX_DMA_POLICY_RX_ORDER_SET(x) WLAN_MBOX_DMA_POLICY_RX_ORDER_SET(x)
+#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS
+#define MBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET
+#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB
+#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB
+#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK
+#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x)
+#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x)
+#define MBOX0_DMA_RX_CONTROL_ADDRESS WLAN_MBOX0_DMA_RX_CONTROL_ADDRESS
+#define MBOX0_DMA_RX_CONTROL_OFFSET WLAN_MBOX0_DMA_RX_CONTROL_OFFSET
+#define MBOX0_DMA_RX_CONTROL_RESUME_MSB WLAN_MBOX0_DMA_RX_CONTROL_RESUME_MSB
+#define MBOX0_DMA_RX_CONTROL_RESUME_LSB WLAN_MBOX0_DMA_RX_CONTROL_RESUME_LSB
+#define MBOX0_DMA_RX_CONTROL_RESUME_MASK WLAN_MBOX0_DMA_RX_CONTROL_RESUME_MASK
+#define MBOX0_DMA_RX_CONTROL_RESUME_GET(x) WLAN_MBOX0_DMA_RX_CONTROL_RESUME_GET(x)
+#define MBOX0_DMA_RX_CONTROL_RESUME_SET(x) WLAN_MBOX0_DMA_RX_CONTROL_RESUME_SET(x)
+#define MBOX0_DMA_RX_CONTROL_START_MSB WLAN_MBOX0_DMA_RX_CONTROL_START_MSB
+#define MBOX0_DMA_RX_CONTROL_START_LSB WLAN_MBOX0_DMA_RX_CONTROL_START_LSB
+#define MBOX0_DMA_RX_CONTROL_START_MASK WLAN_MBOX0_DMA_RX_CONTROL_START_MASK
+#define MBOX0_DMA_RX_CONTROL_START_GET(x) WLAN_MBOX0_DMA_RX_CONTROL_START_GET(x)
+#define MBOX0_DMA_RX_CONTROL_START_SET(x) WLAN_MBOX0_DMA_RX_CONTROL_START_SET(x)
+#define MBOX0_DMA_RX_CONTROL_STOP_MSB WLAN_MBOX0_DMA_RX_CONTROL_STOP_MSB
+#define MBOX0_DMA_RX_CONTROL_STOP_LSB WLAN_MBOX0_DMA_RX_CONTROL_STOP_LSB
+#define MBOX0_DMA_RX_CONTROL_STOP_MASK WLAN_MBOX0_DMA_RX_CONTROL_STOP_MASK
+#define MBOX0_DMA_RX_CONTROL_STOP_GET(x) WLAN_MBOX0_DMA_RX_CONTROL_STOP_GET(x)
+#define MBOX0_DMA_RX_CONTROL_STOP_SET(x) WLAN_MBOX0_DMA_RX_CONTROL_STOP_SET(x)
+#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS
+#define MBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET
+#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB
+#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB
+#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK
+#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x)
+#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x)
+#define MBOX0_DMA_TX_CONTROL_ADDRESS WLAN_MBOX0_DMA_TX_CONTROL_ADDRESS
+#define MBOX0_DMA_TX_CONTROL_OFFSET WLAN_MBOX0_DMA_TX_CONTROL_OFFSET
+#define MBOX0_DMA_TX_CONTROL_RESUME_MSB WLAN_MBOX0_DMA_TX_CONTROL_RESUME_MSB
+#define MBOX0_DMA_TX_CONTROL_RESUME_LSB WLAN_MBOX0_DMA_TX_CONTROL_RESUME_LSB
+#define MBOX0_DMA_TX_CONTROL_RESUME_MASK WLAN_MBOX0_DMA_TX_CONTROL_RESUME_MASK
+#define MBOX0_DMA_TX_CONTROL_RESUME_GET(x) WLAN_MBOX0_DMA_TX_CONTROL_RESUME_GET(x)
+#define MBOX0_DMA_TX_CONTROL_RESUME_SET(x) WLAN_MBOX0_DMA_TX_CONTROL_RESUME_SET(x)
+#define MBOX0_DMA_TX_CONTROL_START_MSB WLAN_MBOX0_DMA_TX_CONTROL_START_MSB
+#define MBOX0_DMA_TX_CONTROL_START_LSB WLAN_MBOX0_DMA_TX_CONTROL_START_LSB
+#define MBOX0_DMA_TX_CONTROL_START_MASK WLAN_MBOX0_DMA_TX_CONTROL_START_MASK
+#define MBOX0_DMA_TX_CONTROL_START_GET(x) WLAN_MBOX0_DMA_TX_CONTROL_START_GET(x)
+#define MBOX0_DMA_TX_CONTROL_START_SET(x) WLAN_MBOX0_DMA_TX_CONTROL_START_SET(x)
+#define MBOX0_DMA_TX_CONTROL_STOP_MSB WLAN_MBOX0_DMA_TX_CONTROL_STOP_MSB
+#define MBOX0_DMA_TX_CONTROL_STOP_LSB WLAN_MBOX0_DMA_TX_CONTROL_STOP_LSB
+#define MBOX0_DMA_TX_CONTROL_STOP_MASK WLAN_MBOX0_DMA_TX_CONTROL_STOP_MASK
+#define MBOX0_DMA_TX_CONTROL_STOP_GET(x) WLAN_MBOX0_DMA_TX_CONTROL_STOP_GET(x)
+#define MBOX0_DMA_TX_CONTROL_STOP_SET(x) WLAN_MBOX0_DMA_TX_CONTROL_STOP_SET(x)
+#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS
+#define MBOX1_DMA_RX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_OFFSET
+#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB
+#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB
+#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK
+#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x)
+#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x)
+#define MBOX1_DMA_RX_CONTROL_ADDRESS WLAN_MBOX1_DMA_RX_CONTROL_ADDRESS
+#define MBOX1_DMA_RX_CONTROL_OFFSET WLAN_MBOX1_DMA_RX_CONTROL_OFFSET
+#define MBOX1_DMA_RX_CONTROL_RESUME_MSB WLAN_MBOX1_DMA_RX_CONTROL_RESUME_MSB
+#define MBOX1_DMA_RX_CONTROL_RESUME_LSB WLAN_MBOX1_DMA_RX_CONTROL_RESUME_LSB
+#define MBOX1_DMA_RX_CONTROL_RESUME_MASK WLAN_MBOX1_DMA_RX_CONTROL_RESUME_MASK
+#define MBOX1_DMA_RX_CONTROL_RESUME_GET(x) WLAN_MBOX1_DMA_RX_CONTROL_RESUME_GET(x)
+#define MBOX1_DMA_RX_CONTROL_RESUME_SET(x) WLAN_MBOX1_DMA_RX_CONTROL_RESUME_SET(x)
+#define MBOX1_DMA_RX_CONTROL_START_MSB WLAN_MBOX1_DMA_RX_CONTROL_START_MSB
+#define MBOX1_DMA_RX_CONTROL_START_LSB WLAN_MBOX1_DMA_RX_CONTROL_START_LSB
+#define MBOX1_DMA_RX_CONTROL_START_MASK WLAN_MBOX1_DMA_RX_CONTROL_START_MASK
+#define MBOX1_DMA_RX_CONTROL_START_GET(x) WLAN_MBOX1_DMA_RX_CONTROL_START_GET(x)
+#define MBOX1_DMA_RX_CONTROL_START_SET(x) WLAN_MBOX1_DMA_RX_CONTROL_START_SET(x)
+#define MBOX1_DMA_RX_CONTROL_STOP_MSB WLAN_MBOX1_DMA_RX_CONTROL_STOP_MSB
+#define MBOX1_DMA_RX_CONTROL_STOP_LSB WLAN_MBOX1_DMA_RX_CONTROL_STOP_LSB
+#define MBOX1_DMA_RX_CONTROL_STOP_MASK WLAN_MBOX1_DMA_RX_CONTROL_STOP_MASK
+#define MBOX1_DMA_RX_CONTROL_STOP_GET(x) WLAN_MBOX1_DMA_RX_CONTROL_STOP_GET(x)
+#define MBOX1_DMA_RX_CONTROL_STOP_SET(x) WLAN_MBOX1_DMA_RX_CONTROL_STOP_SET(x)
+#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS
+#define MBOX1_DMA_TX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_OFFSET
+#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB
+#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB
+#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK
+#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x)
+#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x)
+#define MBOX1_DMA_TX_CONTROL_ADDRESS WLAN_MBOX1_DMA_TX_CONTROL_ADDRESS
+#define MBOX1_DMA_TX_CONTROL_OFFSET WLAN_MBOX1_DMA_TX_CONTROL_OFFSET
+#define MBOX1_DMA_TX_CONTROL_RESUME_MSB WLAN_MBOX1_DMA_TX_CONTROL_RESUME_MSB
+#define MBOX1_DMA_TX_CONTROL_RESUME_LSB WLAN_MBOX1_DMA_TX_CONTROL_RESUME_LSB
+#define MBOX1_DMA_TX_CONTROL_RESUME_MASK WLAN_MBOX1_DMA_TX_CONTROL_RESUME_MASK
+#define MBOX1_DMA_TX_CONTROL_RESUME_GET(x) WLAN_MBOX1_DMA_TX_CONTROL_RESUME_GET(x)
+#define MBOX1_DMA_TX_CONTROL_RESUME_SET(x) WLAN_MBOX1_DMA_TX_CONTROL_RESUME_SET(x)
+#define MBOX1_DMA_TX_CONTROL_START_MSB WLAN_MBOX1_DMA_TX_CONTROL_START_MSB
+#define MBOX1_DMA_TX_CONTROL_START_LSB WLAN_MBOX1_DMA_TX_CONTROL_START_LSB
+#define MBOX1_DMA_TX_CONTROL_START_MASK WLAN_MBOX1_DMA_TX_CONTROL_START_MASK
+#define MBOX1_DMA_TX_CONTROL_START_GET(x) WLAN_MBOX1_DMA_TX_CONTROL_START_GET(x)
+#define MBOX1_DMA_TX_CONTROL_START_SET(x) WLAN_MBOX1_DMA_TX_CONTROL_START_SET(x)
+#define MBOX1_DMA_TX_CONTROL_STOP_MSB WLAN_MBOX1_DMA_TX_CONTROL_STOP_MSB
+#define MBOX1_DMA_TX_CONTROL_STOP_LSB WLAN_MBOX1_DMA_TX_CONTROL_STOP_LSB
+#define MBOX1_DMA_TX_CONTROL_STOP_MASK WLAN_MBOX1_DMA_TX_CONTROL_STOP_MASK
+#define MBOX1_DMA_TX_CONTROL_STOP_GET(x) WLAN_MBOX1_DMA_TX_CONTROL_STOP_GET(x)
+#define MBOX1_DMA_TX_CONTROL_STOP_SET(x) WLAN_MBOX1_DMA_TX_CONTROL_STOP_SET(x)
+#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS
+#define MBOX2_DMA_RX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_OFFSET
+#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB
+#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB
+#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK
+#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x)
+#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x)
+#define MBOX2_DMA_RX_CONTROL_ADDRESS WLAN_MBOX2_DMA_RX_CONTROL_ADDRESS
+#define MBOX2_DMA_RX_CONTROL_OFFSET WLAN_MBOX2_DMA_RX_CONTROL_OFFSET
+#define MBOX2_DMA_RX_CONTROL_RESUME_MSB WLAN_MBOX2_DMA_RX_CONTROL_RESUME_MSB
+#define MBOX2_DMA_RX_CONTROL_RESUME_LSB WLAN_MBOX2_DMA_RX_CONTROL_RESUME_LSB
+#define MBOX2_DMA_RX_CONTROL_RESUME_MASK WLAN_MBOX2_DMA_RX_CONTROL_RESUME_MASK
+#define MBOX2_DMA_RX_CONTROL_RESUME_GET(x) WLAN_MBOX2_DMA_RX_CONTROL_RESUME_GET(x)
+#define MBOX2_DMA_RX_CONTROL_RESUME_SET(x) WLAN_MBOX2_DMA_RX_CONTROL_RESUME_SET(x)
+#define MBOX2_DMA_RX_CONTROL_START_MSB WLAN_MBOX2_DMA_RX_CONTROL_START_MSB
+#define MBOX2_DMA_RX_CONTROL_START_LSB WLAN_MBOX2_DMA_RX_CONTROL_START_LSB
+#define MBOX2_DMA_RX_CONTROL_START_MASK WLAN_MBOX2_DMA_RX_CONTROL_START_MASK
+#define MBOX2_DMA_RX_CONTROL_START_GET(x) WLAN_MBOX2_DMA_RX_CONTROL_START_GET(x)
+#define MBOX2_DMA_RX_CONTROL_START_SET(x) WLAN_MBOX2_DMA_RX_CONTROL_START_SET(x)
+#define MBOX2_DMA_RX_CONTROL_STOP_MSB WLAN_MBOX2_DMA_RX_CONTROL_STOP_MSB
+#define MBOX2_DMA_RX_CONTROL_STOP_LSB WLAN_MBOX2_DMA_RX_CONTROL_STOP_LSB
+#define MBOX2_DMA_RX_CONTROL_STOP_MASK WLAN_MBOX2_DMA_RX_CONTROL_STOP_MASK
+#define MBOX2_DMA_RX_CONTROL_STOP_GET(x) WLAN_MBOX2_DMA_RX_CONTROL_STOP_GET(x)
+#define MBOX2_DMA_RX_CONTROL_STOP_SET(x) WLAN_MBOX2_DMA_RX_CONTROL_STOP_SET(x)
+#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS
+#define MBOX2_DMA_TX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_OFFSET
+#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB
+#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB
+#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK
+#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x)
+#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x)
+#define MBOX2_DMA_TX_CONTROL_ADDRESS WLAN_MBOX2_DMA_TX_CONTROL_ADDRESS
+#define MBOX2_DMA_TX_CONTROL_OFFSET WLAN_MBOX2_DMA_TX_CONTROL_OFFSET
+#define MBOX2_DMA_TX_CONTROL_RESUME_MSB WLAN_MBOX2_DMA_TX_CONTROL_RESUME_MSB
+#define MBOX2_DMA_TX_CONTROL_RESUME_LSB WLAN_MBOX2_DMA_TX_CONTROL_RESUME_LSB
+#define MBOX2_DMA_TX_CONTROL_RESUME_MASK WLAN_MBOX2_DMA_TX_CONTROL_RESUME_MASK
+#define MBOX2_DMA_TX_CONTROL_RESUME_GET(x) WLAN_MBOX2_DMA_TX_CONTROL_RESUME_GET(x)
+#define MBOX2_DMA_TX_CONTROL_RESUME_SET(x) WLAN_MBOX2_DMA_TX_CONTROL_RESUME_SET(x)
+#define MBOX2_DMA_TX_CONTROL_START_MSB WLAN_MBOX2_DMA_TX_CONTROL_START_MSB
+#define MBOX2_DMA_TX_CONTROL_START_LSB WLAN_MBOX2_DMA_TX_CONTROL_START_LSB
+#define MBOX2_DMA_TX_CONTROL_START_MASK WLAN_MBOX2_DMA_TX_CONTROL_START_MASK
+#define MBOX2_DMA_TX_CONTROL_START_GET(x) WLAN_MBOX2_DMA_TX_CONTROL_START_GET(x)
+#define MBOX2_DMA_TX_CONTROL_START_SET(x) WLAN_MBOX2_DMA_TX_CONTROL_START_SET(x)
+#define MBOX2_DMA_TX_CONTROL_STOP_MSB WLAN_MBOX2_DMA_TX_CONTROL_STOP_MSB
+#define MBOX2_DMA_TX_CONTROL_STOP_LSB WLAN_MBOX2_DMA_TX_CONTROL_STOP_LSB
+#define MBOX2_DMA_TX_CONTROL_STOP_MASK WLAN_MBOX2_DMA_TX_CONTROL_STOP_MASK
+#define MBOX2_DMA_TX_CONTROL_STOP_GET(x) WLAN_MBOX2_DMA_TX_CONTROL_STOP_GET(x)
+#define MBOX2_DMA_TX_CONTROL_STOP_SET(x) WLAN_MBOX2_DMA_TX_CONTROL_STOP_SET(x)
+#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS
+#define MBOX3_DMA_RX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_OFFSET
+#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB
+#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB
+#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK
+#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x)
+#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x)
+#define MBOX3_DMA_RX_CONTROL_ADDRESS WLAN_MBOX3_DMA_RX_CONTROL_ADDRESS
+#define MBOX3_DMA_RX_CONTROL_OFFSET WLAN_MBOX3_DMA_RX_CONTROL_OFFSET
+#define MBOX3_DMA_RX_CONTROL_RESUME_MSB WLAN_MBOX3_DMA_RX_CONTROL_RESUME_MSB
+#define MBOX3_DMA_RX_CONTROL_RESUME_LSB WLAN_MBOX3_DMA_RX_CONTROL_RESUME_LSB
+#define MBOX3_DMA_RX_CONTROL_RESUME_MASK WLAN_MBOX3_DMA_RX_CONTROL_RESUME_MASK
+#define MBOX3_DMA_RX_CONTROL_RESUME_GET(x) WLAN_MBOX3_DMA_RX_CONTROL_RESUME_GET(x)
+#define MBOX3_DMA_RX_CONTROL_RESUME_SET(x) WLAN_MBOX3_DMA_RX_CONTROL_RESUME_SET(x)
+#define MBOX3_DMA_RX_CONTROL_START_MSB WLAN_MBOX3_DMA_RX_CONTROL_START_MSB
+#define MBOX3_DMA_RX_CONTROL_START_LSB WLAN_MBOX3_DMA_RX_CONTROL_START_LSB
+#define MBOX3_DMA_RX_CONTROL_START_MASK WLAN_MBOX3_DMA_RX_CONTROL_START_MASK
+#define MBOX3_DMA_RX_CONTROL_START_GET(x) WLAN_MBOX3_DMA_RX_CONTROL_START_GET(x)
+#define MBOX3_DMA_RX_CONTROL_START_SET(x) WLAN_MBOX3_DMA_RX_CONTROL_START_SET(x)
+#define MBOX3_DMA_RX_CONTROL_STOP_MSB WLAN_MBOX3_DMA_RX_CONTROL_STOP_MSB
+#define MBOX3_DMA_RX_CONTROL_STOP_LSB WLAN_MBOX3_DMA_RX_CONTROL_STOP_LSB
+#define MBOX3_DMA_RX_CONTROL_STOP_MASK WLAN_MBOX3_DMA_RX_CONTROL_STOP_MASK
+#define MBOX3_DMA_RX_CONTROL_STOP_GET(x) WLAN_MBOX3_DMA_RX_CONTROL_STOP_GET(x)
+#define MBOX3_DMA_RX_CONTROL_STOP_SET(x) WLAN_MBOX3_DMA_RX_CONTROL_STOP_SET(x)
+#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS
+#define MBOX3_DMA_TX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_OFFSET
+#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB
+#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB
+#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK
+#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x)
+#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x)
+#define MBOX3_DMA_TX_CONTROL_ADDRESS WLAN_MBOX3_DMA_TX_CONTROL_ADDRESS
+#define MBOX3_DMA_TX_CONTROL_OFFSET WLAN_MBOX3_DMA_TX_CONTROL_OFFSET
+#define MBOX3_DMA_TX_CONTROL_RESUME_MSB WLAN_MBOX3_DMA_TX_CONTROL_RESUME_MSB
+#define MBOX3_DMA_TX_CONTROL_RESUME_LSB WLAN_MBOX3_DMA_TX_CONTROL_RESUME_LSB
+#define MBOX3_DMA_TX_CONTROL_RESUME_MASK WLAN_MBOX3_DMA_TX_CONTROL_RESUME_MASK
+#define MBOX3_DMA_TX_CONTROL_RESUME_GET(x) WLAN_MBOX3_DMA_TX_CONTROL_RESUME_GET(x)
+#define MBOX3_DMA_TX_CONTROL_RESUME_SET(x) WLAN_MBOX3_DMA_TX_CONTROL_RESUME_SET(x)
+#define MBOX3_DMA_TX_CONTROL_START_MSB WLAN_MBOX3_DMA_TX_CONTROL_START_MSB
+#define MBOX3_DMA_TX_CONTROL_START_LSB WLAN_MBOX3_DMA_TX_CONTROL_START_LSB
+#define MBOX3_DMA_TX_CONTROL_START_MASK WLAN_MBOX3_DMA_TX_CONTROL_START_MASK
+#define MBOX3_DMA_TX_CONTROL_START_GET(x) WLAN_MBOX3_DMA_TX_CONTROL_START_GET(x)
+#define MBOX3_DMA_TX_CONTROL_START_SET(x) WLAN_MBOX3_DMA_TX_CONTROL_START_SET(x)
+#define MBOX3_DMA_TX_CONTROL_STOP_MSB WLAN_MBOX3_DMA_TX_CONTROL_STOP_MSB
+#define MBOX3_DMA_TX_CONTROL_STOP_LSB WLAN_MBOX3_DMA_TX_CONTROL_STOP_LSB
+#define MBOX3_DMA_TX_CONTROL_STOP_MASK WLAN_MBOX3_DMA_TX_CONTROL_STOP_MASK
+#define MBOX3_DMA_TX_CONTROL_STOP_GET(x) WLAN_MBOX3_DMA_TX_CONTROL_STOP_GET(x)
+#define MBOX3_DMA_TX_CONTROL_STOP_SET(x) WLAN_MBOX3_DMA_TX_CONTROL_STOP_SET(x)
+#define MBOX_INT_STATUS_ADDRESS WLAN_MBOX_INT_STATUS_ADDRESS
+#define MBOX_INT_STATUS_OFFSET WLAN_MBOX_INT_STATUS_OFFSET
+#define MBOX_INT_STATUS_RX_DMA_COMPLETE_MSB WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_MSB
+#define MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB
+#define MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK
+#define MBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x)
+#define MBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x)
+#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB
+#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB
+#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK
+#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x)
+#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x)
+#define MBOX_INT_STATUS_TX_DMA_COMPLETE_MSB WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_MSB
+#define MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB
+#define MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK
+#define MBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x)
+#define MBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x)
+#define MBOX_INT_STATUS_TX_OVERFLOW_MSB WLAN_MBOX_INT_STATUS_TX_OVERFLOW_MSB
+#define MBOX_INT_STATUS_TX_OVERFLOW_LSB WLAN_MBOX_INT_STATUS_TX_OVERFLOW_LSB
+#define MBOX_INT_STATUS_TX_OVERFLOW_MASK WLAN_MBOX_INT_STATUS_TX_OVERFLOW_MASK
+#define MBOX_INT_STATUS_TX_OVERFLOW_GET(x) WLAN_MBOX_INT_STATUS_TX_OVERFLOW_GET(x)
+#define MBOX_INT_STATUS_TX_OVERFLOW_SET(x) WLAN_MBOX_INT_STATUS_TX_OVERFLOW_SET(x)
+#define MBOX_INT_STATUS_RX_UNDERFLOW_MSB WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_MSB
+#define MBOX_INT_STATUS_RX_UNDERFLOW_LSB WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_LSB
+#define MBOX_INT_STATUS_RX_UNDERFLOW_MASK WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_MASK
+#define MBOX_INT_STATUS_RX_UNDERFLOW_GET(x) WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_GET(x)
+#define MBOX_INT_STATUS_RX_UNDERFLOW_SET(x) WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_SET(x)
+#define MBOX_INT_STATUS_TX_NOT_EMPTY_MSB WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_MSB
+#define MBOX_INT_STATUS_TX_NOT_EMPTY_LSB WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_LSB
+#define MBOX_INT_STATUS_TX_NOT_EMPTY_MASK WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_MASK
+#define MBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_GET(x)
+#define MBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_SET(x)
+#define MBOX_INT_STATUS_RX_NOT_FULL_MSB WLAN_MBOX_INT_STATUS_RX_NOT_FULL_MSB
+#define MBOX_INT_STATUS_RX_NOT_FULL_LSB WLAN_MBOX_INT_STATUS_RX_NOT_FULL_LSB
+#define MBOX_INT_STATUS_RX_NOT_FULL_MASK WLAN_MBOX_INT_STATUS_RX_NOT_FULL_MASK
+#define MBOX_INT_STATUS_RX_NOT_FULL_GET(x) WLAN_MBOX_INT_STATUS_RX_NOT_FULL_GET(x)
+#define MBOX_INT_STATUS_RX_NOT_FULL_SET(x) WLAN_MBOX_INT_STATUS_RX_NOT_FULL_SET(x)
+#define MBOX_INT_STATUS_HOST_MSB WLAN_MBOX_INT_STATUS_HOST_MSB
+#define MBOX_INT_STATUS_HOST_LSB WLAN_MBOX_INT_STATUS_HOST_LSB
+#define MBOX_INT_STATUS_HOST_MASK WLAN_MBOX_INT_STATUS_HOST_MASK
+#define MBOX_INT_STATUS_HOST_GET(x) WLAN_MBOX_INT_STATUS_HOST_GET(x)
+#define MBOX_INT_STATUS_HOST_SET(x) WLAN_MBOX_INT_STATUS_HOST_SET(x)
+#define MBOX_INT_ENABLE_ADDRESS WLAN_MBOX_INT_ENABLE_ADDRESS
+#define MBOX_INT_ENABLE_OFFSET WLAN_MBOX_INT_ENABLE_OFFSET
+#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB
+#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB
+#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK
+#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x)
+#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x)
+#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB
+#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB
+#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK
+#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x)
+#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x)
+#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB
+#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB
+#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK
+#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x)
+#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x)
+#define MBOX_INT_ENABLE_TX_OVERFLOW_MSB WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_MSB
+#define MBOX_INT_ENABLE_TX_OVERFLOW_LSB WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_LSB
+#define MBOX_INT_ENABLE_TX_OVERFLOW_MASK WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_MASK
+#define MBOX_INT_ENABLE_TX_OVERFLOW_GET(x) WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_GET(x)
+#define MBOX_INT_ENABLE_TX_OVERFLOW_SET(x) WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_SET(x)
+#define MBOX_INT_ENABLE_RX_UNDERFLOW_MSB WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_MSB
+#define MBOX_INT_ENABLE_RX_UNDERFLOW_LSB WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_LSB
+#define MBOX_INT_ENABLE_RX_UNDERFLOW_MASK WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_MASK
+#define MBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_GET(x)
+#define MBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_SET(x)
+#define MBOX_INT_ENABLE_TX_NOT_EMPTY_MSB WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_MSB
+#define MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB
+#define MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK
+#define MBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x)
+#define MBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x)
+#define MBOX_INT_ENABLE_RX_NOT_FULL_MSB WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_MSB
+#define MBOX_INT_ENABLE_RX_NOT_FULL_LSB WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_LSB
+#define MBOX_INT_ENABLE_RX_NOT_FULL_MASK WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_MASK
+#define MBOX_INT_ENABLE_RX_NOT_FULL_GET(x) WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_GET(x)
+#define MBOX_INT_ENABLE_RX_NOT_FULL_SET(x) WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_SET(x)
+#define MBOX_INT_ENABLE_HOST_MSB WLAN_MBOX_INT_ENABLE_HOST_MSB
+#define MBOX_INT_ENABLE_HOST_LSB WLAN_MBOX_INT_ENABLE_HOST_LSB
+#define MBOX_INT_ENABLE_HOST_MASK WLAN_MBOX_INT_ENABLE_HOST_MASK
+#define MBOX_INT_ENABLE_HOST_GET(x) WLAN_MBOX_INT_ENABLE_HOST_GET(x)
+#define MBOX_INT_ENABLE_HOST_SET(x) WLAN_MBOX_INT_ENABLE_HOST_SET(x)
+#define INT_HOST_ADDRESS WLAN_INT_HOST_ADDRESS
+#define INT_HOST_OFFSET WLAN_INT_HOST_OFFSET
+#define INT_HOST_VECTOR_MSB WLAN_INT_HOST_VECTOR_MSB
+#define INT_HOST_VECTOR_LSB WLAN_INT_HOST_VECTOR_LSB
+#define INT_HOST_VECTOR_MASK WLAN_INT_HOST_VECTOR_MASK
+#define INT_HOST_VECTOR_GET(x) WLAN_INT_HOST_VECTOR_GET(x)
+#define INT_HOST_VECTOR_SET(x) WLAN_INT_HOST_VECTOR_SET(x)
+#define LOCAL_COUNT_ADDRESS WLAN_LOCAL_COUNT_ADDRESS
+#define LOCAL_COUNT_OFFSET WLAN_LOCAL_COUNT_OFFSET
+#define LOCAL_COUNT_VALUE_MSB WLAN_LOCAL_COUNT_VALUE_MSB
+#define LOCAL_COUNT_VALUE_LSB WLAN_LOCAL_COUNT_VALUE_LSB
+#define LOCAL_COUNT_VALUE_MASK WLAN_LOCAL_COUNT_VALUE_MASK
+#define LOCAL_COUNT_VALUE_GET(x) WLAN_LOCAL_COUNT_VALUE_GET(x)
+#define LOCAL_COUNT_VALUE_SET(x) WLAN_LOCAL_COUNT_VALUE_SET(x)
+#define COUNT_INC_ADDRESS WLAN_COUNT_INC_ADDRESS
+#define COUNT_INC_OFFSET WLAN_COUNT_INC_OFFSET
+#define COUNT_INC_VALUE_MSB WLAN_COUNT_INC_VALUE_MSB
+#define COUNT_INC_VALUE_LSB WLAN_COUNT_INC_VALUE_LSB
+#define COUNT_INC_VALUE_MASK WLAN_COUNT_INC_VALUE_MASK
+#define COUNT_INC_VALUE_GET(x) WLAN_COUNT_INC_VALUE_GET(x)
+#define COUNT_INC_VALUE_SET(x) WLAN_COUNT_INC_VALUE_SET(x)
+#define LOCAL_SCRATCH_ADDRESS WLAN_LOCAL_SCRATCH_ADDRESS
+#define LOCAL_SCRATCH_OFFSET WLAN_LOCAL_SCRATCH_OFFSET
+#define LOCAL_SCRATCH_VALUE_MSB WLAN_LOCAL_SCRATCH_VALUE_MSB
+#define LOCAL_SCRATCH_VALUE_LSB WLAN_LOCAL_SCRATCH_VALUE_LSB
+#define LOCAL_SCRATCH_VALUE_MASK WLAN_LOCAL_SCRATCH_VALUE_MASK
+#define LOCAL_SCRATCH_VALUE_GET(x) WLAN_LOCAL_SCRATCH_VALUE_GET(x)
+#define LOCAL_SCRATCH_VALUE_SET(x) WLAN_LOCAL_SCRATCH_VALUE_SET(x)
+#define USE_LOCAL_BUS_ADDRESS WLAN_USE_LOCAL_BUS_ADDRESS
+#define USE_LOCAL_BUS_OFFSET WLAN_USE_LOCAL_BUS_OFFSET
+#define USE_LOCAL_BUS_PIN_INIT_MSB WLAN_USE_LOCAL_BUS_PIN_INIT_MSB
+#define USE_LOCAL_BUS_PIN_INIT_LSB WLAN_USE_LOCAL_BUS_PIN_INIT_LSB
+#define USE_LOCAL_BUS_PIN_INIT_MASK WLAN_USE_LOCAL_BUS_PIN_INIT_MASK
+#define USE_LOCAL_BUS_PIN_INIT_GET(x) WLAN_USE_LOCAL_BUS_PIN_INIT_GET(x)
+#define USE_LOCAL_BUS_PIN_INIT_SET(x) WLAN_USE_LOCAL_BUS_PIN_INIT_SET(x)
+#define SDIO_CONFIG_ADDRESS WLAN_SDIO_CONFIG_ADDRESS
+#define SDIO_CONFIG_OFFSET WLAN_SDIO_CONFIG_OFFSET
+#define SDIO_CONFIG_CCCR_IOR1_MSB WLAN_SDIO_CONFIG_CCCR_IOR1_MSB
+#define SDIO_CONFIG_CCCR_IOR1_LSB WLAN_SDIO_CONFIG_CCCR_IOR1_LSB
+#define SDIO_CONFIG_CCCR_IOR1_MASK WLAN_SDIO_CONFIG_CCCR_IOR1_MASK
+#define SDIO_CONFIG_CCCR_IOR1_GET(x) WLAN_SDIO_CONFIG_CCCR_IOR1_GET(x)
+#define SDIO_CONFIG_CCCR_IOR1_SET(x) WLAN_SDIO_CONFIG_CCCR_IOR1_SET(x)
+#define MBOX_DEBUG_ADDRESS WLAN_MBOX_DEBUG_ADDRESS
+#define MBOX_DEBUG_OFFSET WLAN_MBOX_DEBUG_OFFSET
+#define MBOX_DEBUG_SEL_MSB WLAN_MBOX_DEBUG_SEL_MSB
+#define MBOX_DEBUG_SEL_LSB WLAN_MBOX_DEBUG_SEL_LSB
+#define MBOX_DEBUG_SEL_MASK WLAN_MBOX_DEBUG_SEL_MASK
+#define MBOX_DEBUG_SEL_GET(x) WLAN_MBOX_DEBUG_SEL_GET(x)
+#define MBOX_DEBUG_SEL_SET(x) WLAN_MBOX_DEBUG_SEL_SET(x)
+#define MBOX_FIFO_RESET_ADDRESS WLAN_MBOX_FIFO_RESET_ADDRESS
+#define MBOX_FIFO_RESET_OFFSET WLAN_MBOX_FIFO_RESET_OFFSET
+#define MBOX_FIFO_RESET_INIT_MSB WLAN_MBOX_FIFO_RESET_INIT_MSB
+#define MBOX_FIFO_RESET_INIT_LSB WLAN_MBOX_FIFO_RESET_INIT_LSB
+#define MBOX_FIFO_RESET_INIT_MASK WLAN_MBOX_FIFO_RESET_INIT_MASK
+#define MBOX_FIFO_RESET_INIT_GET(x) WLAN_MBOX_FIFO_RESET_INIT_GET(x)
+#define MBOX_FIFO_RESET_INIT_SET(x) WLAN_MBOX_FIFO_RESET_INIT_SET(x)
+#define MBOX_TXFIFO_POP_ADDRESS WLAN_MBOX_TXFIFO_POP_ADDRESS
+#define MBOX_TXFIFO_POP_OFFSET WLAN_MBOX_TXFIFO_POP_OFFSET
+#define MBOX_TXFIFO_POP_DATA_MSB WLAN_MBOX_TXFIFO_POP_DATA_MSB
+#define MBOX_TXFIFO_POP_DATA_LSB WLAN_MBOX_TXFIFO_POP_DATA_LSB
+#define MBOX_TXFIFO_POP_DATA_MASK WLAN_MBOX_TXFIFO_POP_DATA_MASK
+#define MBOX_TXFIFO_POP_DATA_GET(x) WLAN_MBOX_TXFIFO_POP_DATA_GET(x)
+#define MBOX_TXFIFO_POP_DATA_SET(x) WLAN_MBOX_TXFIFO_POP_DATA_SET(x)
+#define MBOX_RXFIFO_POP_ADDRESS WLAN_MBOX_RXFIFO_POP_ADDRESS
+#define MBOX_RXFIFO_POP_OFFSET WLAN_MBOX_RXFIFO_POP_OFFSET
+#define MBOX_RXFIFO_POP_DATA_MSB WLAN_MBOX_RXFIFO_POP_DATA_MSB
+#define MBOX_RXFIFO_POP_DATA_LSB WLAN_MBOX_RXFIFO_POP_DATA_LSB
+#define MBOX_RXFIFO_POP_DATA_MASK WLAN_MBOX_RXFIFO_POP_DATA_MASK
+#define MBOX_RXFIFO_POP_DATA_GET(x) WLAN_MBOX_RXFIFO_POP_DATA_GET(x)
+#define MBOX_RXFIFO_POP_DATA_SET(x) WLAN_MBOX_RXFIFO_POP_DATA_SET(x)
+#define SDIO_DEBUG_ADDRESS WLAN_SDIO_DEBUG_ADDRESS
+#define SDIO_DEBUG_OFFSET WLAN_SDIO_DEBUG_OFFSET
+#define SDIO_DEBUG_SEL_MSB WLAN_SDIO_DEBUG_SEL_MSB
+#define SDIO_DEBUG_SEL_LSB WLAN_SDIO_DEBUG_SEL_LSB
+#define SDIO_DEBUG_SEL_MASK WLAN_SDIO_DEBUG_SEL_MASK
+#define SDIO_DEBUG_SEL_GET(x) WLAN_SDIO_DEBUG_SEL_GET(x)
+#define SDIO_DEBUG_SEL_SET(x) WLAN_SDIO_DEBUG_SEL_SET(x)
+#define GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS
+#define GMBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET
+#define GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB
+#define GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB
+#define GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK
+#define GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x)
+#define GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x)
+#define GMBOX0_DMA_RX_CONTROL_ADDRESS WLAN_GMBOX0_DMA_RX_CONTROL_ADDRESS
+#define GMBOX0_DMA_RX_CONTROL_OFFSET WLAN_GMBOX0_DMA_RX_CONTROL_OFFSET
+#define GMBOX0_DMA_RX_CONTROL_RESUME_MSB WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_MSB
+#define GMBOX0_DMA_RX_CONTROL_RESUME_LSB WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_LSB
+#define GMBOX0_DMA_RX_CONTROL_RESUME_MASK WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_MASK
+#define GMBOX0_DMA_RX_CONTROL_RESUME_GET(x) WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_GET(x)
+#define GMBOX0_DMA_RX_CONTROL_RESUME_SET(x) WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_SET(x)
+#define GMBOX0_DMA_RX_CONTROL_START_MSB WLAN_GMBOX0_DMA_RX_CONTROL_START_MSB
+#define GMBOX0_DMA_RX_CONTROL_START_LSB WLAN_GMBOX0_DMA_RX_CONTROL_START_LSB
+#define GMBOX0_DMA_RX_CONTROL_START_MASK WLAN_GMBOX0_DMA_RX_CONTROL_START_MASK
+#define GMBOX0_DMA_RX_CONTROL_START_GET(x) WLAN_GMBOX0_DMA_RX_CONTROL_START_GET(x)
+#define GMBOX0_DMA_RX_CONTROL_START_SET(x) WLAN_GMBOX0_DMA_RX_CONTROL_START_SET(x)
+#define GMBOX0_DMA_RX_CONTROL_STOP_MSB WLAN_GMBOX0_DMA_RX_CONTROL_STOP_MSB
+#define GMBOX0_DMA_RX_CONTROL_STOP_LSB WLAN_GMBOX0_DMA_RX_CONTROL_STOP_LSB
+#define GMBOX0_DMA_RX_CONTROL_STOP_MASK WLAN_GMBOX0_DMA_RX_CONTROL_STOP_MASK
+#define GMBOX0_DMA_RX_CONTROL_STOP_GET(x) WLAN_GMBOX0_DMA_RX_CONTROL_STOP_GET(x)
+#define GMBOX0_DMA_RX_CONTROL_STOP_SET(x) WLAN_GMBOX0_DMA_RX_CONTROL_STOP_SET(x)
+#define GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS
+#define GMBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET
+#define GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB
+#define GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB
+#define GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK
+#define GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x)
+#define GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x)
+#define GMBOX0_DMA_TX_CONTROL_ADDRESS WLAN_GMBOX0_DMA_TX_CONTROL_ADDRESS
+#define GMBOX0_DMA_TX_CONTROL_OFFSET WLAN_GMBOX0_DMA_TX_CONTROL_OFFSET
+#define GMBOX0_DMA_TX_CONTROL_RESUME_MSB WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_MSB
+#define GMBOX0_DMA_TX_CONTROL_RESUME_LSB WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_LSB
+#define GMBOX0_DMA_TX_CONTROL_RESUME_MASK WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_MASK
+#define GMBOX0_DMA_TX_CONTROL_RESUME_GET(x) WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_GET(x)
+#define GMBOX0_DMA_TX_CONTROL_RESUME_SET(x) WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_SET(x)
+#define GMBOX0_DMA_TX_CONTROL_START_MSB WLAN_GMBOX0_DMA_TX_CONTROL_START_MSB
+#define GMBOX0_DMA_TX_CONTROL_START_LSB WLAN_GMBOX0_DMA_TX_CONTROL_START_LSB
+#define GMBOX0_DMA_TX_CONTROL_START_MASK WLAN_GMBOX0_DMA_TX_CONTROL_START_MASK
+#define GMBOX0_DMA_TX_CONTROL_START_GET(x) WLAN_GMBOX0_DMA_TX_CONTROL_START_GET(x)
+#define GMBOX0_DMA_TX_CONTROL_START_SET(x) WLAN_GMBOX0_DMA_TX_CONTROL_START_SET(x)
+#define GMBOX0_DMA_TX_CONTROL_STOP_MSB WLAN_GMBOX0_DMA_TX_CONTROL_STOP_MSB
+#define GMBOX0_DMA_TX_CONTROL_STOP_LSB WLAN_GMBOX0_DMA_TX_CONTROL_STOP_LSB
+#define GMBOX0_DMA_TX_CONTROL_STOP_MASK WLAN_GMBOX0_DMA_TX_CONTROL_STOP_MASK
+#define GMBOX0_DMA_TX_CONTROL_STOP_GET(x) WLAN_GMBOX0_DMA_TX_CONTROL_STOP_GET(x)
+#define GMBOX0_DMA_TX_CONTROL_STOP_SET(x) WLAN_GMBOX0_DMA_TX_CONTROL_STOP_SET(x)
+#define GMBOX_INT_STATUS_ADDRESS WLAN_GMBOX_INT_STATUS_ADDRESS
+#define GMBOX_INT_STATUS_OFFSET WLAN_GMBOX_INT_STATUS_OFFSET
+#define GMBOX_INT_STATUS_TX_OVERFLOW_MSB WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_MSB
+#define GMBOX_INT_STATUS_TX_OVERFLOW_LSB WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_LSB
+#define GMBOX_INT_STATUS_TX_OVERFLOW_MASK WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_MASK
+#define GMBOX_INT_STATUS_TX_OVERFLOW_GET(x) WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_GET(x)
+#define GMBOX_INT_STATUS_TX_OVERFLOW_SET(x) WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_SET(x)
+#define GMBOX_INT_STATUS_RX_UNDERFLOW_MSB WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_MSB
+#define GMBOX_INT_STATUS_RX_UNDERFLOW_LSB WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_LSB
+#define GMBOX_INT_STATUS_RX_UNDERFLOW_MASK WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_MASK
+#define GMBOX_INT_STATUS_RX_UNDERFLOW_GET(x) WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_GET(x)
+#define GMBOX_INT_STATUS_RX_UNDERFLOW_SET(x) WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_SET(x)
+#define GMBOX_INT_STATUS_RX_DMA_COMPLETE_MSB WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_MSB
+#define GMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB
+#define GMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK
+#define GMBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x)
+#define GMBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x)
+#define GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB
+#define GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB
+#define GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK
+#define GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x)
+#define GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x)
+#define GMBOX_INT_STATUS_TX_DMA_COMPLETE_MSB WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_MSB
+#define GMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB
+#define GMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK
+#define GMBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x)
+#define GMBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x)
+#define GMBOX_INT_STATUS_TX_NOT_EMPTY_MSB WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_MSB
+#define GMBOX_INT_STATUS_TX_NOT_EMPTY_LSB WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_LSB
+#define GMBOX_INT_STATUS_TX_NOT_EMPTY_MASK WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_MASK
+#define GMBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_GET(x)
+#define GMBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_SET(x)
+#define GMBOX_INT_STATUS_RX_NOT_FULL_MSB WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_MSB
+#define GMBOX_INT_STATUS_RX_NOT_FULL_LSB WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_LSB
+#define GMBOX_INT_STATUS_RX_NOT_FULL_MASK WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_MASK
+#define GMBOX_INT_STATUS_RX_NOT_FULL_GET(x) WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_GET(x)
+#define GMBOX_INT_STATUS_RX_NOT_FULL_SET(x) WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_SET(x)
+#define GMBOX_INT_ENABLE_ADDRESS WLAN_GMBOX_INT_ENABLE_ADDRESS
+#define GMBOX_INT_ENABLE_OFFSET WLAN_GMBOX_INT_ENABLE_OFFSET
+#define GMBOX_INT_ENABLE_TX_OVERFLOW_MSB WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_MSB
+#define GMBOX_INT_ENABLE_TX_OVERFLOW_LSB WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_LSB
+#define GMBOX_INT_ENABLE_TX_OVERFLOW_MASK WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_MASK
+#define GMBOX_INT_ENABLE_TX_OVERFLOW_GET(x) WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_GET(x)
+#define GMBOX_INT_ENABLE_TX_OVERFLOW_SET(x) WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_SET(x)
+#define GMBOX_INT_ENABLE_RX_UNDERFLOW_MSB WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_MSB
+#define GMBOX_INT_ENABLE_RX_UNDERFLOW_LSB WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_LSB
+#define GMBOX_INT_ENABLE_RX_UNDERFLOW_MASK WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_MASK
+#define GMBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_GET(x)
+#define GMBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_SET(x)
+#define GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB
+#define GMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB
+#define GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK
+#define GMBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x)
+#define GMBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x)
+#define GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB
+#define GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB
+#define GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK
+#define GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x)
+#define GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x)
+#define GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB
+#define GMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB
+#define GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK
+#define GMBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x)
+#define GMBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x)
+#define GMBOX_INT_ENABLE_TX_NOT_EMPTY_MSB WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_MSB
+#define GMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB
+#define GMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK
+#define GMBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x)
+#define GMBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x)
+#define GMBOX_INT_ENABLE_RX_NOT_FULL_MSB WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_MSB
+#define GMBOX_INT_ENABLE_RX_NOT_FULL_LSB WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_LSB
+#define GMBOX_INT_ENABLE_RX_NOT_FULL_MASK WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_MASK
+#define GMBOX_INT_ENABLE_RX_NOT_FULL_GET(x) WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_GET(x)
+#define GMBOX_INT_ENABLE_RX_NOT_FULL_SET(x) WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_SET(x)
+#define HOST_IF_WINDOW_ADDRESS WLAN_HOST_IF_WINDOW_ADDRESS
+#define HOST_IF_WINDOW_OFFSET WLAN_HOST_IF_WINDOW_OFFSET
+#define HOST_IF_WINDOW_DATA_MSB WLAN_HOST_IF_WINDOW_DATA_MSB
+#define HOST_IF_WINDOW_DATA_LSB WLAN_HOST_IF_WINDOW_DATA_LSB
+#define HOST_IF_WINDOW_DATA_MASK WLAN_HOST_IF_WINDOW_DATA_MASK
+#define HOST_IF_WINDOW_DATA_GET(x) WLAN_HOST_IF_WINDOW_DATA_GET(x)
+#define HOST_IF_WINDOW_DATA_SET(x) WLAN_HOST_IF_WINDOW_DATA_SET(x)
+
+
+#endif
+#endif
+
+
+
diff --git a/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/mbox_wlan_host_reg.h b/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/mbox_wlan_host_reg.h
new file mode 100644
index 00000000000..60855021c2b
--- /dev/null
+++ b/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/mbox_wlan_host_reg.h
@@ -0,0 +1,522 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _MBOX_WLAN_HOST_REG_REG_H_
+#define _MBOX_WLAN_HOST_REG_REG_H_
+
+#define HOST_INT_STATUS_ADDRESS                  0x00000400
+#define HOST_INT_STATUS_OFFSET                   0x00000400
+#define HOST_INT_STATUS_ERROR_MSB                7
+#define HOST_INT_STATUS_ERROR_LSB                7
+#define HOST_INT_STATUS_ERROR_MASK               0x00000080
+#define HOST_INT_STATUS_ERROR_GET(x)             (((x) & HOST_INT_STATUS_ERROR_MASK) >> HOST_INT_STATUS_ERROR_LSB)
+#define HOST_INT_STATUS_ERROR_SET(x)             (((x) << HOST_INT_STATUS_ERROR_LSB) & HOST_INT_STATUS_ERROR_MASK)
+#define HOST_INT_STATUS_CPU_MSB                  6
+#define HOST_INT_STATUS_CPU_LSB                  6
+#define HOST_INT_STATUS_CPU_MASK                 0x00000040
+#define HOST_INT_STATUS_CPU_GET(x)               (((x) & HOST_INT_STATUS_CPU_MASK) >> HOST_INT_STATUS_CPU_LSB)
+#define HOST_INT_STATUS_CPU_SET(x)               (((x) << HOST_INT_STATUS_CPU_LSB) & HOST_INT_STATUS_CPU_MASK)
+#define HOST_INT_STATUS_INT_MSB                  5
+#define HOST_INT_STATUS_INT_LSB                  5
+#define HOST_INT_STATUS_INT_MASK                 0x00000020
+#define HOST_INT_STATUS_INT_GET(x)               (((x) & HOST_INT_STATUS_INT_MASK) >> HOST_INT_STATUS_INT_LSB)
+#define HOST_INT_STATUS_INT_SET(x)               (((x) << HOST_INT_STATUS_INT_LSB) & HOST_INT_STATUS_INT_MASK)
+#define HOST_INT_STATUS_COUNTER_MSB              4
+#define HOST_INT_STATUS_COUNTER_LSB              4
+#define HOST_INT_STATUS_COUNTER_MASK             0x00000010
+#define HOST_INT_STATUS_COUNTER_GET(x)           (((x) & HOST_INT_STATUS_COUNTER_MASK) >> HOST_INT_STATUS_COUNTER_LSB)
+#define HOST_INT_STATUS_COUNTER_SET(x)           (((x) << HOST_INT_STATUS_COUNTER_LSB) & HOST_INT_STATUS_COUNTER_MASK)
+#define HOST_INT_STATUS_MBOX_DATA_MSB            3
+#define HOST_INT_STATUS_MBOX_DATA_LSB            0
+#define HOST_INT_STATUS_MBOX_DATA_MASK           0x0000000f
+#define HOST_INT_STATUS_MBOX_DATA_GET(x)         (((x) & HOST_INT_STATUS_MBOX_DATA_MASK) >> HOST_INT_STATUS_MBOX_DATA_LSB)
+#define HOST_INT_STATUS_MBOX_DATA_SET(x)         (((x) << HOST_INT_STATUS_MBOX_DATA_LSB) & HOST_INT_STATUS_MBOX_DATA_MASK)
+
+#define CPU_INT_STATUS_ADDRESS                   0x00000401
+#define CPU_INT_STATUS_OFFSET                    0x00000401
+#define CPU_INT_STATUS_BIT_MSB                   7
+#define CPU_INT_STATUS_BIT_LSB                   0
+#define CPU_INT_STATUS_BIT_MASK                  0x000000ff
+#define CPU_INT_STATUS_BIT_GET(x)                (((x) & CPU_INT_STATUS_BIT_MASK) >> CPU_INT_STATUS_BIT_LSB)
+#define CPU_INT_STATUS_BIT_SET(x)                (((x) << CPU_INT_STATUS_BIT_LSB) & CPU_INT_STATUS_BIT_MASK)
+
+#define ERROR_INT_STATUS_ADDRESS                 0x00000402
+#define ERROR_INT_STATUS_OFFSET                  0x00000402
+#define ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_MSB 6
+#define ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_LSB 6
+#define ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_MASK 0x00000040
+#define ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_GET(x) (((x) & ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_MASK) >> ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_LSB)
+#define ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_SET(x) (((x) << ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_LSB) & ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_MASK)
+#define ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_MSB 5
+#define ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_LSB 5
+#define ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_MASK 0x00000020
+#define ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_GET(x) (((x) & ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_MASK) >> ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_LSB)
+#define ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_SET(x) (((x) << ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_LSB) & ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_MASK)
+#define ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_MSB 4
+#define ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_LSB 4
+#define ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_MASK 0x00000010
+#define ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_GET(x) (((x) & ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_MASK) >> ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_LSB)
+#define ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_SET(x) (((x) << ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_LSB) & ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_MASK)
+#define ERROR_INT_STATUS_SPI_MSB                 3
+#define ERROR_INT_STATUS_SPI_LSB                 3
+#define ERROR_INT_STATUS_SPI_MASK                0x00000008
+#define ERROR_INT_STATUS_SPI_GET(x)              (((x) & ERROR_INT_STATUS_SPI_MASK) >> ERROR_INT_STATUS_SPI_LSB)
+#define ERROR_INT_STATUS_SPI_SET(x)              (((x) << ERROR_INT_STATUS_SPI_LSB) & ERROR_INT_STATUS_SPI_MASK)
+#define ERROR_INT_STATUS_WAKEUP_MSB              2
+#define ERROR_INT_STATUS_WAKEUP_LSB              2
+#define ERROR_INT_STATUS_WAKEUP_MASK             0x00000004
+#define ERROR_INT_STATUS_WAKEUP_GET(x)           (((x) & ERROR_INT_STATUS_WAKEUP_MASK) >> ERROR_INT_STATUS_WAKEUP_LSB)
+#define ERROR_INT_STATUS_WAKEUP_SET(x)           (((x) << ERROR_INT_STATUS_WAKEUP_LSB) & ERROR_INT_STATUS_WAKEUP_MASK)
+#define ERROR_INT_STATUS_RX_UNDERFLOW_MSB        1
+#define ERROR_INT_STATUS_RX_UNDERFLOW_LSB        1
+#define ERROR_INT_STATUS_RX_UNDERFLOW_MASK       0x00000002
+#define ERROR_INT_STATUS_RX_UNDERFLOW_GET(x)     (((x) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK) >> ERROR_INT_STATUS_RX_UNDERFLOW_LSB)
+#define ERROR_INT_STATUS_RX_UNDERFLOW_SET(x)     (((x) << ERROR_INT_STATUS_RX_UNDERFLOW_LSB) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK)
+#define ERROR_INT_STATUS_TX_OVERFLOW_MSB         0
+#define ERROR_INT_STATUS_TX_OVERFLOW_LSB         0
+#define ERROR_INT_STATUS_TX_OVERFLOW_MASK        0x00000001
+#define ERROR_INT_STATUS_TX_OVERFLOW_GET(x)      (((x) & ERROR_INT_STATUS_TX_OVERFLOW_MASK) >> ERROR_INT_STATUS_TX_OVERFLOW_LSB)
+#define ERROR_INT_STATUS_TX_OVERFLOW_SET(x)      (((x) << ERROR_INT_STATUS_TX_OVERFLOW_LSB) & ERROR_INT_STATUS_TX_OVERFLOW_MASK)
+
+#define COUNTER_INT_STATUS_ADDRESS               0x00000403
+#define COUNTER_INT_STATUS_OFFSET                0x00000403
+#define COUNTER_INT_STATUS_COUNTER_MSB           7
+#define COUNTER_INT_STATUS_COUNTER_LSB           0
+#define COUNTER_INT_STATUS_COUNTER_MASK          0x000000ff
+#define COUNTER_INT_STATUS_COUNTER_GET(x)        (((x) & COUNTER_INT_STATUS_COUNTER_MASK) >> COUNTER_INT_STATUS_COUNTER_LSB)
+#define COUNTER_INT_STATUS_COUNTER_SET(x)        (((x) << COUNTER_INT_STATUS_COUNTER_LSB) & COUNTER_INT_STATUS_COUNTER_MASK)
+
+#define MBOX_FRAME_ADDRESS                       0x00000404
+#define MBOX_FRAME_OFFSET                        0x00000404
+#define MBOX_FRAME_RX_EOM_MSB                    7
+#define MBOX_FRAME_RX_EOM_LSB                    4
+#define MBOX_FRAME_RX_EOM_MASK                   0x000000f0
+#define MBOX_FRAME_RX_EOM_GET(x)                 (((x) & MBOX_FRAME_RX_EOM_MASK) >> MBOX_FRAME_RX_EOM_LSB)
+#define MBOX_FRAME_RX_EOM_SET(x)                 (((x) << MBOX_FRAME_RX_EOM_LSB) & MBOX_FRAME_RX_EOM_MASK)
+#define MBOX_FRAME_RX_SOM_MSB                    3
+#define MBOX_FRAME_RX_SOM_LSB                    0
+#define MBOX_FRAME_RX_SOM_MASK                   0x0000000f
+#define MBOX_FRAME_RX_SOM_GET(x)                 (((x) & MBOX_FRAME_RX_SOM_MASK) >> MBOX_FRAME_RX_SOM_LSB)
+#define MBOX_FRAME_RX_SOM_SET(x)                 (((x) << MBOX_FRAME_RX_SOM_LSB) & MBOX_FRAME_RX_SOM_MASK)
+
+#define RX_LOOKAHEAD_VALID_ADDRESS               0x00000405
+#define RX_LOOKAHEAD_VALID_OFFSET                0x00000405
+#define RX_LOOKAHEAD_VALID_MBOX_MSB              3
+#define RX_LOOKAHEAD_VALID_MBOX_LSB              0
+#define RX_LOOKAHEAD_VALID_MBOX_MASK             0x0000000f
+#define RX_LOOKAHEAD_VALID_MBOX_GET(x)           (((x) & RX_LOOKAHEAD_VALID_MBOX_MASK) >> RX_LOOKAHEAD_VALID_MBOX_LSB)
+#define RX_LOOKAHEAD_VALID_MBOX_SET(x)           (((x) << RX_LOOKAHEAD_VALID_MBOX_LSB) & RX_LOOKAHEAD_VALID_MBOX_MASK)
+
+#define HOST_INT_STATUS2_ADDRESS                 0x00000406
+#define HOST_INT_STATUS2_OFFSET                  0x00000406
+#define HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_MSB  2
+#define HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_LSB  2
+#define HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_MASK 0x00000004
+#define HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_GET(x) (((x) & HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_MASK) >> HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_LSB)
+#define HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_SET(x) (((x) << HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_LSB) & HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_MASK)
+#define HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_MSB   1
+#define HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_LSB   1
+#define HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_MASK  0x00000002
+#define HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_GET(x) (((x) & HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_MASK) >> HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_LSB)
+#define HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_SET(x) (((x) << HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_LSB) & HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_MASK)
+#define HOST_INT_STATUS2_GMBOX_DATA_MSB          0
+#define HOST_INT_STATUS2_GMBOX_DATA_LSB          0
+#define HOST_INT_STATUS2_GMBOX_DATA_MASK         0x00000001
+#define HOST_INT_STATUS2_GMBOX_DATA_GET(x)       (((x) & HOST_INT_STATUS2_GMBOX_DATA_MASK) >> HOST_INT_STATUS2_GMBOX_DATA_LSB)
+#define HOST_INT_STATUS2_GMBOX_DATA_SET(x)       (((x) << HOST_INT_STATUS2_GMBOX_DATA_LSB) & HOST_INT_STATUS2_GMBOX_DATA_MASK)
+
+#define GMBOX_RX_AVAIL_ADDRESS                   0x00000407
+#define GMBOX_RX_AVAIL_OFFSET                    0x00000407
+#define GMBOX_RX_AVAIL_BYTE_MSB                  6
+#define GMBOX_RX_AVAIL_BYTE_LSB                  0
+#define GMBOX_RX_AVAIL_BYTE_MASK                 0x0000007f
+#define GMBOX_RX_AVAIL_BYTE_GET(x)               (((x) & GMBOX_RX_AVAIL_BYTE_MASK) >> GMBOX_RX_AVAIL_BYTE_LSB)
+#define GMBOX_RX_AVAIL_BYTE_SET(x)               (((x) << GMBOX_RX_AVAIL_BYTE_LSB) & GMBOX_RX_AVAIL_BYTE_MASK)
+
+#define RX_LOOKAHEAD0_ADDRESS                    0x00000408
+#define RX_LOOKAHEAD0_OFFSET                     0x00000408
+#define RX_LOOKAHEAD0_DATA_MSB                   7
+#define RX_LOOKAHEAD0_DATA_LSB                   0
+#define RX_LOOKAHEAD0_DATA_MASK                  0x000000ff
+#define RX_LOOKAHEAD0_DATA_GET(x)                (((x) & RX_LOOKAHEAD0_DATA_MASK) >> RX_LOOKAHEAD0_DATA_LSB)
+#define RX_LOOKAHEAD0_DATA_SET(x)                (((x) << RX_LOOKAHEAD0_DATA_LSB) & RX_LOOKAHEAD0_DATA_MASK)
+
+#define RX_LOOKAHEAD1_ADDRESS                    0x0000040c
+#define RX_LOOKAHEAD1_OFFSET                     0x0000040c
+#define RX_LOOKAHEAD1_DATA_MSB                   7
+#define RX_LOOKAHEAD1_DATA_LSB                   0
+#define RX_LOOKAHEAD1_DATA_MASK                  0x000000ff
+#define RX_LOOKAHEAD1_DATA_GET(x)                (((x) & RX_LOOKAHEAD1_DATA_MASK) >> RX_LOOKAHEAD1_DATA_LSB)
+#define RX_LOOKAHEAD1_DATA_SET(x)                (((x) << RX_LOOKAHEAD1_DATA_LSB) & RX_LOOKAHEAD1_DATA_MASK)
+
+#define RX_LOOKAHEAD2_ADDRESS                    0x00000410
+#define RX_LOOKAHEAD2_OFFSET                     0x00000410
+#define RX_LOOKAHEAD2_DATA_MSB                   7
+#define RX_LOOKAHEAD2_DATA_LSB                   0
+#define RX_LOOKAHEAD2_DATA_MASK                  0x000000ff
+#define RX_LOOKAHEAD2_DATA_GET(x)                (((x) & RX_LOOKAHEAD2_DATA_MASK) >> RX_LOOKAHEAD2_DATA_LSB)
+#define RX_LOOKAHEAD2_DATA_SET(x)                (((x) << RX_LOOKAHEAD2_DATA_LSB) & RX_LOOKAHEAD2_DATA_MASK)
+
+#define RX_LOOKAHEAD3_ADDRESS                    0x00000414
+#define RX_LOOKAHEAD3_OFFSET                     0x00000414
+#define RX_LOOKAHEAD3_DATA_MSB                   7
+#define RX_LOOKAHEAD3_DATA_LSB                   0
+#define RX_LOOKAHEAD3_DATA_MASK                  0x000000ff
+#define RX_LOOKAHEAD3_DATA_GET(x)                (((x) & RX_LOOKAHEAD3_DATA_MASK) >> RX_LOOKAHEAD3_DATA_LSB)
+#define RX_LOOKAHEAD3_DATA_SET(x)                (((x) << RX_LOOKAHEAD3_DATA_LSB) & RX_LOOKAHEAD3_DATA_MASK)
+
+#define INT_STATUS_ENABLE_ADDRESS                0x00000418
+#define INT_STATUS_ENABLE_OFFSET                 0x00000418
+#define INT_STATUS_ENABLE_ERROR_MSB              7
+#define INT_STATUS_ENABLE_ERROR_LSB              7
+#define INT_STATUS_ENABLE_ERROR_MASK             0x00000080
+#define INT_STATUS_ENABLE_ERROR_GET(x)           (((x) & INT_STATUS_ENABLE_ERROR_MASK) >> INT_STATUS_ENABLE_ERROR_LSB)
+#define INT_STATUS_ENABLE_ERROR_SET(x)           (((x) << INT_STATUS_ENABLE_ERROR_LSB) & INT_STATUS_ENABLE_ERROR_MASK)
+#define INT_STATUS_ENABLE_CPU_MSB                6
+#define INT_STATUS_ENABLE_CPU_LSB                6
+#define INT_STATUS_ENABLE_CPU_MASK               0x00000040
+#define INT_STATUS_ENABLE_CPU_GET(x)             (((x) & INT_STATUS_ENABLE_CPU_MASK) >> INT_STATUS_ENABLE_CPU_LSB)
+#define INT_STATUS_ENABLE_CPU_SET(x)             (((x) << INT_STATUS_ENABLE_CPU_LSB) & INT_STATUS_ENABLE_CPU_MASK)
+#define INT_STATUS_ENABLE_INT_MSB                5
+#define INT_STATUS_ENABLE_INT_LSB                5
+#define INT_STATUS_ENABLE_INT_MASK               0x00000020
+#define INT_STATUS_ENABLE_INT_GET(x)             (((x) & INT_STATUS_ENABLE_INT_MASK) >> INT_STATUS_ENABLE_INT_LSB)
+#define INT_STATUS_ENABLE_INT_SET(x)             (((x) << INT_STATUS_ENABLE_INT_LSB) & INT_STATUS_ENABLE_INT_MASK)
+#define INT_STATUS_ENABLE_COUNTER_MSB            4
+#define INT_STATUS_ENABLE_COUNTER_LSB            4
+#define INT_STATUS_ENABLE_COUNTER_MASK           0x00000010
+#define INT_STATUS_ENABLE_COUNTER_GET(x)         (((x) & INT_STATUS_ENABLE_COUNTER_MASK) >> INT_STATUS_ENABLE_COUNTER_LSB)
+#define INT_STATUS_ENABLE_COUNTER_SET(x)         (((x) << INT_STATUS_ENABLE_COUNTER_LSB) & INT_STATUS_ENABLE_COUNTER_MASK)
+#define INT_STATUS_ENABLE_MBOX_DATA_MSB          3
+#define INT_STATUS_ENABLE_MBOX_DATA_LSB          0
+#define INT_STATUS_ENABLE_MBOX_DATA_MASK         0x0000000f
+#define INT_STATUS_ENABLE_MBOX_DATA_GET(x)       (((x) & INT_STATUS_ENABLE_MBOX_DATA_MASK) >> INT_STATUS_ENABLE_MBOX_DATA_LSB)
+#define INT_STATUS_ENABLE_MBOX_DATA_SET(x)       (((x) << INT_STATUS_ENABLE_MBOX_DATA_LSB) & INT_STATUS_ENABLE_MBOX_DATA_MASK)
+
+#define CPU_INT_STATUS_ENABLE_ADDRESS            0x00000419
+#define CPU_INT_STATUS_ENABLE_OFFSET             0x00000419
+#define CPU_INT_STATUS_ENABLE_BIT_MSB            7
+#define CPU_INT_STATUS_ENABLE_BIT_LSB            0
+#define CPU_INT_STATUS_ENABLE_BIT_MASK           0x000000ff
+#define CPU_INT_STATUS_ENABLE_BIT_GET(x)         (((x) & CPU_INT_STATUS_ENABLE_BIT_MASK) >> CPU_INT_STATUS_ENABLE_BIT_LSB)
+#define CPU_INT_STATUS_ENABLE_BIT_SET(x)         (((x) << CPU_INT_STATUS_ENABLE_BIT_LSB) & CPU_INT_STATUS_ENABLE_BIT_MASK)
+
+#define ERROR_STATUS_ENABLE_ADDRESS              0x0000041a
+#define ERROR_STATUS_ENABLE_OFFSET               0x0000041a
+#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_MSB 6
+#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_LSB 6
+#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_MASK 0x00000040
+#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_GET(x) (((x) & ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_MASK) >> ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_LSB)
+#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_SET(x) (((x) << ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_LSB) & ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_MASK)
+#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_MSB 5
+#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_LSB 5
+#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_MASK 0x00000020
+#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_MASK) >> ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_LSB)
+#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_LSB) & ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_MASK)
+#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_MSB 4
+#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_LSB 4
+#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_MASK 0x00000010
+#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_MASK) >> ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_LSB)
+#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_LSB) & ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_MASK)
+#define ERROR_STATUS_ENABLE_WAKEUP_MSB           2
+#define ERROR_STATUS_ENABLE_WAKEUP_LSB           2
+#define ERROR_STATUS_ENABLE_WAKEUP_MASK          0x00000004
+#define ERROR_STATUS_ENABLE_WAKEUP_GET(x)        (((x) & ERROR_STATUS_ENABLE_WAKEUP_MASK) >> ERROR_STATUS_ENABLE_WAKEUP_LSB)
+#define ERROR_STATUS_ENABLE_WAKEUP_SET(x)        (((x) << ERROR_STATUS_ENABLE_WAKEUP_LSB) & ERROR_STATUS_ENABLE_WAKEUP_MASK)
+#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MSB     1
+#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB     1
+#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK    0x00000002
+#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_GET(x)  (((x) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK) >> ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB)
+#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_SET(x)  (((x) << ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK)
+#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MSB      0
+#define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB      0
+#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK     0x00000001
+#define ERROR_STATUS_ENABLE_TX_OVERFLOW_GET(x)   (((x) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK) >> ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB)
+#define ERROR_STATUS_ENABLE_TX_OVERFLOW_SET(x)   (((x) << ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK)
+
+#define COUNTER_INT_STATUS_ENABLE_ADDRESS        0x0000041b
+#define COUNTER_INT_STATUS_ENABLE_OFFSET         0x0000041b
+#define COUNTER_INT_STATUS_ENABLE_BIT_MSB        7
+#define COUNTER_INT_STATUS_ENABLE_BIT_LSB        0
+#define COUNTER_INT_STATUS_ENABLE_BIT_MASK       0x000000ff
+#define COUNTER_INT_STATUS_ENABLE_BIT_GET(x)     (((x) & COUNTER_INT_STATUS_ENABLE_BIT_MASK) >> COUNTER_INT_STATUS_ENABLE_BIT_LSB)
+#define COUNTER_INT_STATUS_ENABLE_BIT_SET(x)     (((x) << COUNTER_INT_STATUS_ENABLE_BIT_LSB) & COUNTER_INT_STATUS_ENABLE_BIT_MASK)
+
+#define COUNT_ADDRESS                            0x00000420
+#define COUNT_OFFSET                             0x00000420
+#define COUNT_VALUE_MSB                          7
+#define COUNT_VALUE_LSB                          0
+#define COUNT_VALUE_MASK                         0x000000ff
+#define COUNT_VALUE_GET(x)                       (((x) & COUNT_VALUE_MASK) >> COUNT_VALUE_LSB)
+#define COUNT_VALUE_SET(x)                       (((x) << COUNT_VALUE_LSB) & COUNT_VALUE_MASK)
+
+#define COUNT_DEC_ADDRESS                        0x00000440
+#define COUNT_DEC_OFFSET                         0x00000440
+#define COUNT_DEC_VALUE_MSB                      7
+#define COUNT_DEC_VALUE_LSB                      0
+#define COUNT_DEC_VALUE_MASK                     0x000000ff
+#define COUNT_DEC_VALUE_GET(x)                   (((x) & COUNT_DEC_VALUE_MASK) >> COUNT_DEC_VALUE_LSB)
+#define COUNT_DEC_VALUE_SET(x)                   (((x) << COUNT_DEC_VALUE_LSB) & COUNT_DEC_VALUE_MASK)
+
+#define SCRATCH_ADDRESS                          0x00000460
+#define SCRATCH_OFFSET                           0x00000460
+#define SCRATCH_VALUE_MSB                        7
+#define SCRATCH_VALUE_LSB                        0
+#define SCRATCH_VALUE_MASK                       0x000000ff
+#define SCRATCH_VALUE_GET(x)                     (((x) & SCRATCH_VALUE_MASK) >> SCRATCH_VALUE_LSB)
+#define SCRATCH_VALUE_SET(x)                     (((x) << SCRATCH_VALUE_LSB) & SCRATCH_VALUE_MASK)
+
+#define FIFO_TIMEOUT_ADDRESS                     0x00000468
+#define FIFO_TIMEOUT_OFFSET                      0x00000468
+#define FIFO_TIMEOUT_VALUE_MSB                   7
+#define FIFO_TIMEOUT_VALUE_LSB                   0
+#define FIFO_TIMEOUT_VALUE_MASK                  0x000000ff
+#define FIFO_TIMEOUT_VALUE_GET(x)                (((x) & FIFO_TIMEOUT_VALUE_MASK) >> FIFO_TIMEOUT_VALUE_LSB)
+#define FIFO_TIMEOUT_VALUE_SET(x)                (((x) << FIFO_TIMEOUT_VALUE_LSB) & FIFO_TIMEOUT_VALUE_MASK)
+
+#define FIFO_TIMEOUT_ENABLE_ADDRESS              0x00000469
+#define FIFO_TIMEOUT_ENABLE_OFFSET               0x00000469
+#define FIFO_TIMEOUT_ENABLE_SET_MSB              0
+#define FIFO_TIMEOUT_ENABLE_SET_LSB              0
+#define FIFO_TIMEOUT_ENABLE_SET_MASK             0x00000001
+#define FIFO_TIMEOUT_ENABLE_SET_GET(x)           (((x) & FIFO_TIMEOUT_ENABLE_SET_MASK) >> FIFO_TIMEOUT_ENABLE_SET_LSB)
+#define FIFO_TIMEOUT_ENABLE_SET_SET(x)           (((x) << FIFO_TIMEOUT_ENABLE_SET_LSB) & FIFO_TIMEOUT_ENABLE_SET_MASK)
+
+#define DISABLE_SLEEP_ADDRESS                    0x0000046a
+#define DISABLE_SLEEP_OFFSET                     0x0000046a
+#define DISABLE_SLEEP_FOR_INT_MSB                1
+#define DISABLE_SLEEP_FOR_INT_LSB                1
+#define DISABLE_SLEEP_FOR_INT_MASK               0x00000002
+#define DISABLE_SLEEP_FOR_INT_GET(x)             (((x) & DISABLE_SLEEP_FOR_INT_MASK) >> DISABLE_SLEEP_FOR_INT_LSB)
+#define DISABLE_SLEEP_FOR_INT_SET(x)             (((x) << DISABLE_SLEEP_FOR_INT_LSB) & DISABLE_SLEEP_FOR_INT_MASK)
+#define DISABLE_SLEEP_ON_MSB                     0
+#define DISABLE_SLEEP_ON_LSB                     0
+#define DISABLE_SLEEP_ON_MASK                    0x00000001
+#define DISABLE_SLEEP_ON_GET(x)                  (((x) & DISABLE_SLEEP_ON_MASK) >> DISABLE_SLEEP_ON_LSB)
+#define DISABLE_SLEEP_ON_SET(x)                  (((x) << DISABLE_SLEEP_ON_LSB) & DISABLE_SLEEP_ON_MASK)
+
+#define LOCAL_BUS_ADDRESS                        0x00000470
+#define LOCAL_BUS_OFFSET                         0x00000470
+#define LOCAL_BUS_STATE_MSB                      1
+#define LOCAL_BUS_STATE_LSB                      0
+#define LOCAL_BUS_STATE_MASK                     0x00000003
+#define LOCAL_BUS_STATE_GET(x)                   (((x) & LOCAL_BUS_STATE_MASK) >> LOCAL_BUS_STATE_LSB)
+#define LOCAL_BUS_STATE_SET(x)                   (((x) << LOCAL_BUS_STATE_LSB) & LOCAL_BUS_STATE_MASK)
+
+#define INT_WLAN_ADDRESS                         0x00000472
+#define INT_WLAN_OFFSET                          0x00000472
+#define INT_WLAN_VECTOR_MSB                      7
+#define INT_WLAN_VECTOR_LSB                      0
+#define INT_WLAN_VECTOR_MASK                     0x000000ff
+#define INT_WLAN_VECTOR_GET(x)                   (((x) & INT_WLAN_VECTOR_MASK) >> INT_WLAN_VECTOR_LSB)
+#define INT_WLAN_VECTOR_SET(x)                   (((x) << INT_WLAN_VECTOR_LSB) & INT_WLAN_VECTOR_MASK)
+
+#define WINDOW_DATA_ADDRESS                      0x00000474
+#define WINDOW_DATA_OFFSET                       0x00000474
+#define WINDOW_DATA_DATA_MSB                     7
+#define WINDOW_DATA_DATA_LSB                     0
+#define WINDOW_DATA_DATA_MASK                    0x000000ff
+#define WINDOW_DATA_DATA_GET(x)                  (((x) & WINDOW_DATA_DATA_MASK) >> WINDOW_DATA_DATA_LSB)
+#define WINDOW_DATA_DATA_SET(x)                  (((x) << WINDOW_DATA_DATA_LSB) & WINDOW_DATA_DATA_MASK)
+
+#define WINDOW_WRITE_ADDR_ADDRESS                0x00000478
+#define WINDOW_WRITE_ADDR_OFFSET                 0x00000478
+#define WINDOW_WRITE_ADDR_ADDR_MSB               7
+#define WINDOW_WRITE_ADDR_ADDR_LSB               0
+#define WINDOW_WRITE_ADDR_ADDR_MASK              0x000000ff
+#define WINDOW_WRITE_ADDR_ADDR_GET(x)            (((x) & WINDOW_WRITE_ADDR_ADDR_MASK) >> WINDOW_WRITE_ADDR_ADDR_LSB)
+#define WINDOW_WRITE_ADDR_ADDR_SET(x)            (((x) << WINDOW_WRITE_ADDR_ADDR_LSB) & WINDOW_WRITE_ADDR_ADDR_MASK)
+
+#define WINDOW_READ_ADDR_ADDRESS                 0x0000047c
+#define WINDOW_READ_ADDR_OFFSET                  0x0000047c
+#define WINDOW_READ_ADDR_ADDR_MSB                7
+#define WINDOW_READ_ADDR_ADDR_LSB                0
+#define WINDOW_READ_ADDR_ADDR_MASK               0x000000ff
+#define WINDOW_READ_ADDR_ADDR_GET(x)             (((x) & WINDOW_READ_ADDR_ADDR_MASK) >> WINDOW_READ_ADDR_ADDR_LSB)
+#define WINDOW_READ_ADDR_ADDR_SET(x)             (((x) << WINDOW_READ_ADDR_ADDR_LSB) & WINDOW_READ_ADDR_ADDR_MASK)
+
+#define HOST_CTRL_SPI_CONFIG_ADDRESS             0x00000480
+#define HOST_CTRL_SPI_CONFIG_OFFSET              0x00000480
+#define HOST_CTRL_SPI_CONFIG_SPI_RESET_MSB       4
+#define HOST_CTRL_SPI_CONFIG_SPI_RESET_LSB       4
+#define HOST_CTRL_SPI_CONFIG_SPI_RESET_MASK      0x00000010
+#define HOST_CTRL_SPI_CONFIG_SPI_RESET_GET(x)    (((x) & HOST_CTRL_SPI_CONFIG_SPI_RESET_MASK) >> HOST_CTRL_SPI_CONFIG_SPI_RESET_LSB)
+#define HOST_CTRL_SPI_CONFIG_SPI_RESET_SET(x)    (((x) << HOST_CTRL_SPI_CONFIG_SPI_RESET_LSB) & HOST_CTRL_SPI_CONFIG_SPI_RESET_MASK)
+#define HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_MSB 3
+#define HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_LSB 3
+#define HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_MASK 0x00000008
+#define HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_GET(x) (((x) & HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_MASK) >> HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_LSB)
+#define HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_SET(x) (((x) << HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_LSB) & HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_MASK)
+#define HOST_CTRL_SPI_CONFIG_TEST_MODE_MSB       2
+#define HOST_CTRL_SPI_CONFIG_TEST_MODE_LSB       2
+#define HOST_CTRL_SPI_CONFIG_TEST_MODE_MASK      0x00000004
+#define HOST_CTRL_SPI_CONFIG_TEST_MODE_GET(x)    (((x) & HOST_CTRL_SPI_CONFIG_TEST_MODE_MASK) >> HOST_CTRL_SPI_CONFIG_TEST_MODE_LSB)
+#define HOST_CTRL_SPI_CONFIG_TEST_MODE_SET(x)    (((x) << HOST_CTRL_SPI_CONFIG_TEST_MODE_LSB) & HOST_CTRL_SPI_CONFIG_TEST_MODE_MASK)
+#define HOST_CTRL_SPI_CONFIG_DATA_SIZE_MSB       1
+#define HOST_CTRL_SPI_CONFIG_DATA_SIZE_LSB       0
+#define HOST_CTRL_SPI_CONFIG_DATA_SIZE_MASK      0x00000003
+#define HOST_CTRL_SPI_CONFIG_DATA_SIZE_GET(x)    (((x) & HOST_CTRL_SPI_CONFIG_DATA_SIZE_MASK) >> HOST_CTRL_SPI_CONFIG_DATA_SIZE_LSB)
+#define HOST_CTRL_SPI_CONFIG_DATA_SIZE_SET(x)    (((x) << HOST_CTRL_SPI_CONFIG_DATA_SIZE_LSB) & HOST_CTRL_SPI_CONFIG_DATA_SIZE_MASK)
+
+#define HOST_CTRL_SPI_STATUS_ADDRESS             0x00000481
+#define HOST_CTRL_SPI_STATUS_OFFSET              0x00000481
+#define HOST_CTRL_SPI_STATUS_ADDR_ERR_MSB        3
+#define HOST_CTRL_SPI_STATUS_ADDR_ERR_LSB        3
+#define HOST_CTRL_SPI_STATUS_ADDR_ERR_MASK       0x00000008
+#define HOST_CTRL_SPI_STATUS_ADDR_ERR_GET(x)     (((x) & HOST_CTRL_SPI_STATUS_ADDR_ERR_MASK) >> HOST_CTRL_SPI_STATUS_ADDR_ERR_LSB)
+#define HOST_CTRL_SPI_STATUS_ADDR_ERR_SET(x)     (((x) << HOST_CTRL_SPI_STATUS_ADDR_ERR_LSB) & HOST_CTRL_SPI_STATUS_ADDR_ERR_MASK)
+#define HOST_CTRL_SPI_STATUS_RD_ERR_MSB          2
+#define HOST_CTRL_SPI_STATUS_RD_ERR_LSB          2
+#define HOST_CTRL_SPI_STATUS_RD_ERR_MASK         0x00000004
+#define HOST_CTRL_SPI_STATUS_RD_ERR_GET(x)       (((x) & HOST_CTRL_SPI_STATUS_RD_ERR_MASK) >> HOST_CTRL_SPI_STATUS_RD_ERR_LSB)
+#define HOST_CTRL_SPI_STATUS_RD_ERR_SET(x)       (((x) << HOST_CTRL_SPI_STATUS_RD_ERR_LSB) & HOST_CTRL_SPI_STATUS_RD_ERR_MASK)
+#define HOST_CTRL_SPI_STATUS_WR_ERR_MSB          1
+#define HOST_CTRL_SPI_STATUS_WR_ERR_LSB          1
+#define HOST_CTRL_SPI_STATUS_WR_ERR_MASK         0x00000002
+#define HOST_CTRL_SPI_STATUS_WR_ERR_GET(x)       (((x) & HOST_CTRL_SPI_STATUS_WR_ERR_MASK) >> HOST_CTRL_SPI_STATUS_WR_ERR_LSB)
+#define HOST_CTRL_SPI_STATUS_WR_ERR_SET(x)       (((x) << HOST_CTRL_SPI_STATUS_WR_ERR_LSB) & HOST_CTRL_SPI_STATUS_WR_ERR_MASK)
+#define HOST_CTRL_SPI_STATUS_READY_MSB           0
+#define HOST_CTRL_SPI_STATUS_READY_LSB           0
+#define HOST_CTRL_SPI_STATUS_READY_MASK          0x00000001
+#define HOST_CTRL_SPI_STATUS_READY_GET(x)        (((x) & HOST_CTRL_SPI_STATUS_READY_MASK) >> HOST_CTRL_SPI_STATUS_READY_LSB)
+#define HOST_CTRL_SPI_STATUS_READY_SET(x)        (((x) << HOST_CTRL_SPI_STATUS_READY_LSB) & HOST_CTRL_SPI_STATUS_READY_MASK)
+
+#define NON_ASSOC_SLEEP_EN_ADDRESS               0x00000482
+#define NON_ASSOC_SLEEP_EN_OFFSET                0x00000482
+#define NON_ASSOC_SLEEP_EN_BIT_MSB               0
+#define NON_ASSOC_SLEEP_EN_BIT_LSB               0
+#define NON_ASSOC_SLEEP_EN_BIT_MASK              0x00000001
+#define NON_ASSOC_SLEEP_EN_BIT_GET(x)            (((x) & NON_ASSOC_SLEEP_EN_BIT_MASK) >> NON_ASSOC_SLEEP_EN_BIT_LSB)
+#define NON_ASSOC_SLEEP_EN_BIT_SET(x)            (((x) << NON_ASSOC_SLEEP_EN_BIT_LSB) & NON_ASSOC_SLEEP_EN_BIT_MASK)
+
+#define CPU_DBG_SEL_ADDRESS                      0x00000483
+#define CPU_DBG_SEL_OFFSET                       0x00000483
+#define CPU_DBG_SEL_BIT_MSB                      5
+#define CPU_DBG_SEL_BIT_LSB                      0
+#define CPU_DBG_SEL_BIT_MASK                     0x0000003f
+#define CPU_DBG_SEL_BIT_GET(x)                   (((x) & CPU_DBG_SEL_BIT_MASK) >> CPU_DBG_SEL_BIT_LSB)
+#define CPU_DBG_SEL_BIT_SET(x)                   (((x) << CPU_DBG_SEL_BIT_LSB) & CPU_DBG_SEL_BIT_MASK)
+
+#define CPU_DBG_ADDRESS                          0x00000484
+#define CPU_DBG_OFFSET                           0x00000484
+#define CPU_DBG_DATA_MSB                         7
+#define CPU_DBG_DATA_LSB                         0
+#define CPU_DBG_DATA_MASK                        0x000000ff
+#define CPU_DBG_DATA_GET(x)                      (((x) & CPU_DBG_DATA_MASK) >> CPU_DBG_DATA_LSB)
+#define CPU_DBG_DATA_SET(x)                      (((x) << CPU_DBG_DATA_LSB) & CPU_DBG_DATA_MASK)
+
+#define INT_STATUS2_ENABLE_ADDRESS               0x00000488
+#define INT_STATUS2_ENABLE_OFFSET                0x00000488
+#define INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_MSB 2
+#define INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_LSB 2
+#define INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_MASK 0x00000004
+#define INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_GET(x) (((x) & INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_MASK) >> INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_LSB)
+#define INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_SET(x) (((x) << INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_LSB) & INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_MASK)
+#define INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_MSB 1
+#define INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_LSB 1
+#define INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_MASK 0x00000002
+#define INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_GET(x) (((x) & INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_MASK) >> INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_LSB)
+#define INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_SET(x) (((x) << INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_LSB) & INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_MASK)
+#define INT_STATUS2_ENABLE_GMBOX_DATA_MSB        0
+#define INT_STATUS2_ENABLE_GMBOX_DATA_LSB        0
+#define INT_STATUS2_ENABLE_GMBOX_DATA_MASK       0x00000001
+#define INT_STATUS2_ENABLE_GMBOX_DATA_GET(x)     (((x) & INT_STATUS2_ENABLE_GMBOX_DATA_MASK) >> INT_STATUS2_ENABLE_GMBOX_DATA_LSB)
+#define INT_STATUS2_ENABLE_GMBOX_DATA_SET(x)     (((x) << INT_STATUS2_ENABLE_GMBOX_DATA_LSB) & INT_STATUS2_ENABLE_GMBOX_DATA_MASK)
+
+#define GMBOX_RX_LOOKAHEAD_ADDRESS               0x00000490
+#define GMBOX_RX_LOOKAHEAD_OFFSET                0x00000490
+#define GMBOX_RX_LOOKAHEAD_DATA_MSB              7
+#define GMBOX_RX_LOOKAHEAD_DATA_LSB              0
+#define GMBOX_RX_LOOKAHEAD_DATA_MASK             0x000000ff
+#define GMBOX_RX_LOOKAHEAD_DATA_GET(x)           (((x) & GMBOX_RX_LOOKAHEAD_DATA_MASK) >> GMBOX_RX_LOOKAHEAD_DATA_LSB)
+#define GMBOX_RX_LOOKAHEAD_DATA_SET(x)           (((x) << GMBOX_RX_LOOKAHEAD_DATA_LSB) & GMBOX_RX_LOOKAHEAD_DATA_MASK)
+
+#define GMBOX_RX_LOOKAHEAD_MUX_ADDRESS           0x00000498
+#define GMBOX_RX_LOOKAHEAD_MUX_OFFSET            0x00000498
+#define GMBOX_RX_LOOKAHEAD_MUX_SEL_MSB           0
+#define GMBOX_RX_LOOKAHEAD_MUX_SEL_LSB           0
+#define GMBOX_RX_LOOKAHEAD_MUX_SEL_MASK          0x00000001
+#define GMBOX_RX_LOOKAHEAD_MUX_SEL_GET(x)        (((x) & GMBOX_RX_LOOKAHEAD_MUX_SEL_MASK) >> GMBOX_RX_LOOKAHEAD_MUX_SEL_LSB)
+#define GMBOX_RX_LOOKAHEAD_MUX_SEL_SET(x)        (((x) << GMBOX_RX_LOOKAHEAD_MUX_SEL_LSB) & GMBOX_RX_LOOKAHEAD_MUX_SEL_MASK)
+
+#define CIS_WINDOW_ADDRESS                       0x00000600
+#define CIS_WINDOW_OFFSET                        0x00000600
+#define CIS_WINDOW_DATA_MSB                      7
+#define CIS_WINDOW_DATA_LSB                      0
+#define CIS_WINDOW_DATA_MASK                     0x000000ff
+#define CIS_WINDOW_DATA_GET(x)                   (((x) & CIS_WINDOW_DATA_MASK) >> CIS_WINDOW_DATA_LSB)
+#define CIS_WINDOW_DATA_SET(x)                   (((x) << CIS_WINDOW_DATA_LSB) & CIS_WINDOW_DATA_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct mbox_wlan_host_reg_reg_s {
+  unsigned char pad0[1024]; /* pad to 0x400 */
+  volatile unsigned char host_int_status;
+  volatile unsigned char cpu_int_status;
+  volatile unsigned char error_int_status;
+  volatile unsigned char counter_int_status;
+  volatile unsigned char mbox_frame;
+  volatile unsigned char rx_lookahead_valid;
+  volatile unsigned char host_int_status2;
+  volatile unsigned char gmbox_rx_avail;
+  volatile unsigned char rx_lookahead0[4];
+  volatile unsigned char rx_lookahead1[4];
+  volatile unsigned char rx_lookahead2[4];
+  volatile unsigned char rx_lookahead3[4];
+  volatile unsigned char int_status_enable;
+  volatile unsigned char cpu_int_status_enable;
+  volatile unsigned char error_status_enable;
+  volatile unsigned char counter_int_status_enable;
+  unsigned char pad1[4]; /* pad to 0x420 */
+  volatile unsigned char count[8];
+  unsigned char pad2[24]; /* pad to 0x440 */
+  volatile unsigned char count_dec[32];
+  volatile unsigned char scratch[8];
+  volatile unsigned char fifo_timeout;
+  volatile unsigned char fifo_timeout_enable;
+  volatile unsigned char disable_sleep;
+  unsigned char pad3[5]; /* pad to 0x470 */
+  volatile unsigned char local_bus;
+  unsigned char pad4[1]; /* pad to 0x472 */
+  volatile unsigned char int_wlan;
+  unsigned char pad5[1]; /* pad to 0x474 */
+  volatile unsigned char window_data[4];
+  volatile unsigned char window_write_addr[4];
+  volatile unsigned char window_read_addr[4];
+  volatile unsigned char host_ctrl_spi_config;
+  volatile unsigned char host_ctrl_spi_status;
+  volatile unsigned char non_assoc_sleep_en;
+  volatile unsigned char cpu_dbg_sel;
+  volatile unsigned char cpu_dbg[4];
+  volatile unsigned char int_status2_enable;
+  unsigned char pad6[7]; /* pad to 0x490 */
+  volatile unsigned char gmbox_rx_lookahead[8];
+  volatile unsigned char gmbox_rx_lookahead_mux;
+  unsigned char pad7[359]; /* pad to 0x600 */
+  volatile unsigned char cis_window[512];
+} mbox_wlan_host_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _MBOX_WLAN_HOST_REG_H_ */
diff --git a/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/mbox_wlan_reg.h b/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/mbox_wlan_reg.h
new file mode 100644
index 00000000000..e00270fc145
--- /dev/null
+++ b/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/mbox_wlan_reg.h
@@ -0,0 +1,638 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _MBOX_WLAN_REG_REG_H_
+#define _MBOX_WLAN_REG_REG_H_
+
+#define WLAN_MBOX_FIFO_ADDRESS                   0x00000000
+#define WLAN_MBOX_FIFO_OFFSET                    0x00000000
+#define WLAN_MBOX_FIFO_DATA_MSB                  19
+#define WLAN_MBOX_FIFO_DATA_LSB                  0
+#define WLAN_MBOX_FIFO_DATA_MASK                 0x000fffff
+#define WLAN_MBOX_FIFO_DATA_GET(x)               (((x) & WLAN_MBOX_FIFO_DATA_MASK) >> WLAN_MBOX_FIFO_DATA_LSB)
+#define WLAN_MBOX_FIFO_DATA_SET(x)               (((x) << WLAN_MBOX_FIFO_DATA_LSB) & WLAN_MBOX_FIFO_DATA_MASK)
+
+#define WLAN_MBOX_FIFO_STATUS_ADDRESS            0x00000010
+#define WLAN_MBOX_FIFO_STATUS_OFFSET             0x00000010
+#define WLAN_MBOX_FIFO_STATUS_EMPTY_MSB          19
+#define WLAN_MBOX_FIFO_STATUS_EMPTY_LSB          16
+#define WLAN_MBOX_FIFO_STATUS_EMPTY_MASK         0x000f0000
+#define WLAN_MBOX_FIFO_STATUS_EMPTY_GET(x)       (((x) & WLAN_MBOX_FIFO_STATUS_EMPTY_MASK) >> WLAN_MBOX_FIFO_STATUS_EMPTY_LSB)
+#define WLAN_MBOX_FIFO_STATUS_EMPTY_SET(x)       (((x) << WLAN_MBOX_FIFO_STATUS_EMPTY_LSB) & WLAN_MBOX_FIFO_STATUS_EMPTY_MASK)
+#define WLAN_MBOX_FIFO_STATUS_FULL_MSB           15
+#define WLAN_MBOX_FIFO_STATUS_FULL_LSB           12
+#define WLAN_MBOX_FIFO_STATUS_FULL_MASK          0x0000f000
+#define WLAN_MBOX_FIFO_STATUS_FULL_GET(x)        (((x) & WLAN_MBOX_FIFO_STATUS_FULL_MASK) >> WLAN_MBOX_FIFO_STATUS_FULL_LSB)
+#define WLAN_MBOX_FIFO_STATUS_FULL_SET(x)        (((x) << WLAN_MBOX_FIFO_STATUS_FULL_LSB) & WLAN_MBOX_FIFO_STATUS_FULL_MASK)
+
+#define WLAN_MBOX_DMA_POLICY_ADDRESS             0x00000014
+#define WLAN_MBOX_DMA_POLICY_OFFSET              0x00000014
+#define WLAN_MBOX_DMA_POLICY_TX_QUANTUM_MSB      3
+#define WLAN_MBOX_DMA_POLICY_TX_QUANTUM_LSB      3
+#define WLAN_MBOX_DMA_POLICY_TX_QUANTUM_MASK     0x00000008
+#define WLAN_MBOX_DMA_POLICY_TX_QUANTUM_GET(x)   (((x) & WLAN_MBOX_DMA_POLICY_TX_QUANTUM_MASK) >> WLAN_MBOX_DMA_POLICY_TX_QUANTUM_LSB)
+#define WLAN_MBOX_DMA_POLICY_TX_QUANTUM_SET(x)   (((x) << WLAN_MBOX_DMA_POLICY_TX_QUANTUM_LSB) & WLAN_MBOX_DMA_POLICY_TX_QUANTUM_MASK)
+#define WLAN_MBOX_DMA_POLICY_TX_ORDER_MSB        2
+#define WLAN_MBOX_DMA_POLICY_TX_ORDER_LSB        2
+#define WLAN_MBOX_DMA_POLICY_TX_ORDER_MASK       0x00000004
+#define WLAN_MBOX_DMA_POLICY_TX_ORDER_GET(x)     (((x) & WLAN_MBOX_DMA_POLICY_TX_ORDER_MASK) >> WLAN_MBOX_DMA_POLICY_TX_ORDER_LSB)
+#define WLAN_MBOX_DMA_POLICY_TX_ORDER_SET(x)     (((x) << WLAN_MBOX_DMA_POLICY_TX_ORDER_LSB) & WLAN_MBOX_DMA_POLICY_TX_ORDER_MASK)
+#define WLAN_MBOX_DMA_POLICY_RX_QUANTUM_MSB      1
+#define WLAN_MBOX_DMA_POLICY_RX_QUANTUM_LSB      1
+#define WLAN_MBOX_DMA_POLICY_RX_QUANTUM_MASK     0x00000002
+#define WLAN_MBOX_DMA_POLICY_RX_QUANTUM_GET(x)   (((x) & WLAN_MBOX_DMA_POLICY_RX_QUANTUM_MASK) >> WLAN_MBOX_DMA_POLICY_RX_QUANTUM_LSB)
+#define WLAN_MBOX_DMA_POLICY_RX_QUANTUM_SET(x)   (((x) << WLAN_MBOX_DMA_POLICY_RX_QUANTUM_LSB) & WLAN_MBOX_DMA_POLICY_RX_QUANTUM_MASK)
+#define WLAN_MBOX_DMA_POLICY_RX_ORDER_MSB        0
+#define WLAN_MBOX_DMA_POLICY_RX_ORDER_LSB        0
+#define WLAN_MBOX_DMA_POLICY_RX_ORDER_MASK       0x00000001
+#define WLAN_MBOX_DMA_POLICY_RX_ORDER_GET(x)     (((x) & WLAN_MBOX_DMA_POLICY_RX_ORDER_MASK) >> WLAN_MBOX_DMA_POLICY_RX_ORDER_LSB)
+#define WLAN_MBOX_DMA_POLICY_RX_ORDER_SET(x)     (((x) << WLAN_MBOX_DMA_POLICY_RX_ORDER_LSB) & WLAN_MBOX_DMA_POLICY_RX_ORDER_MASK)
+
+#define WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000018
+#define WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000018
+#define WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define WLAN_MBOX0_DMA_RX_CONTROL_ADDRESS        0x0000001c
+#define WLAN_MBOX0_DMA_RX_CONTROL_OFFSET         0x0000001c
+#define WLAN_MBOX0_DMA_RX_CONTROL_RESUME_MSB     2
+#define WLAN_MBOX0_DMA_RX_CONTROL_RESUME_LSB     2
+#define WLAN_MBOX0_DMA_RX_CONTROL_RESUME_MASK    0x00000004
+#define WLAN_MBOX0_DMA_RX_CONTROL_RESUME_GET(x)  (((x) & WLAN_MBOX0_DMA_RX_CONTROL_RESUME_MASK) >> WLAN_MBOX0_DMA_RX_CONTROL_RESUME_LSB)
+#define WLAN_MBOX0_DMA_RX_CONTROL_RESUME_SET(x)  (((x) << WLAN_MBOX0_DMA_RX_CONTROL_RESUME_LSB) & WLAN_MBOX0_DMA_RX_CONTROL_RESUME_MASK)
+#define WLAN_MBOX0_DMA_RX_CONTROL_START_MSB      1
+#define WLAN_MBOX0_DMA_RX_CONTROL_START_LSB      1
+#define WLAN_MBOX0_DMA_RX_CONTROL_START_MASK     0x00000002
+#define WLAN_MBOX0_DMA_RX_CONTROL_START_GET(x)   (((x) & WLAN_MBOX0_DMA_RX_CONTROL_START_MASK) >> WLAN_MBOX0_DMA_RX_CONTROL_START_LSB)
+#define WLAN_MBOX0_DMA_RX_CONTROL_START_SET(x)   (((x) << WLAN_MBOX0_DMA_RX_CONTROL_START_LSB) & WLAN_MBOX0_DMA_RX_CONTROL_START_MASK)
+#define WLAN_MBOX0_DMA_RX_CONTROL_STOP_MSB       0
+#define WLAN_MBOX0_DMA_RX_CONTROL_STOP_LSB       0
+#define WLAN_MBOX0_DMA_RX_CONTROL_STOP_MASK      0x00000001
+#define WLAN_MBOX0_DMA_RX_CONTROL_STOP_GET(x)    (((x) & WLAN_MBOX0_DMA_RX_CONTROL_STOP_MASK) >> WLAN_MBOX0_DMA_RX_CONTROL_STOP_LSB)
+#define WLAN_MBOX0_DMA_RX_CONTROL_STOP_SET(x)    (((x) << WLAN_MBOX0_DMA_RX_CONTROL_STOP_LSB) & WLAN_MBOX0_DMA_RX_CONTROL_STOP_MASK)
+
+#define WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000020
+#define WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000020
+#define WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define WLAN_MBOX0_DMA_TX_CONTROL_ADDRESS        0x00000024
+#define WLAN_MBOX0_DMA_TX_CONTROL_OFFSET         0x00000024
+#define WLAN_MBOX0_DMA_TX_CONTROL_RESUME_MSB     2
+#define WLAN_MBOX0_DMA_TX_CONTROL_RESUME_LSB     2
+#define WLAN_MBOX0_DMA_TX_CONTROL_RESUME_MASK    0x00000004
+#define WLAN_MBOX0_DMA_TX_CONTROL_RESUME_GET(x)  (((x) & WLAN_MBOX0_DMA_TX_CONTROL_RESUME_MASK) >> WLAN_MBOX0_DMA_TX_CONTROL_RESUME_LSB)
+#define WLAN_MBOX0_DMA_TX_CONTROL_RESUME_SET(x)  (((x) << WLAN_MBOX0_DMA_TX_CONTROL_RESUME_LSB) & WLAN_MBOX0_DMA_TX_CONTROL_RESUME_MASK)
+#define WLAN_MBOX0_DMA_TX_CONTROL_START_MSB      1
+#define WLAN_MBOX0_DMA_TX_CONTROL_START_LSB      1
+#define WLAN_MBOX0_DMA_TX_CONTROL_START_MASK     0x00000002
+#define WLAN_MBOX0_DMA_TX_CONTROL_START_GET(x)   (((x) & WLAN_MBOX0_DMA_TX_CONTROL_START_MASK) >> WLAN_MBOX0_DMA_TX_CONTROL_START_LSB)
+#define WLAN_MBOX0_DMA_TX_CONTROL_START_SET(x)   (((x) << WLAN_MBOX0_DMA_TX_CONTROL_START_LSB) & WLAN_MBOX0_DMA_TX_CONTROL_START_MASK)
+#define WLAN_MBOX0_DMA_TX_CONTROL_STOP_MSB       0
+#define WLAN_MBOX0_DMA_TX_CONTROL_STOP_LSB       0
+#define WLAN_MBOX0_DMA_TX_CONTROL_STOP_MASK      0x00000001
+#define WLAN_MBOX0_DMA_TX_CONTROL_STOP_GET(x)    (((x) & WLAN_MBOX0_DMA_TX_CONTROL_STOP_MASK) >> WLAN_MBOX0_DMA_TX_CONTROL_STOP_LSB)
+#define WLAN_MBOX0_DMA_TX_CONTROL_STOP_SET(x)    (((x) << WLAN_MBOX0_DMA_TX_CONTROL_STOP_LSB) & WLAN_MBOX0_DMA_TX_CONTROL_STOP_MASK)
+
+#define WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000028
+#define WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000028
+#define WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define WLAN_MBOX1_DMA_RX_CONTROL_ADDRESS        0x0000002c
+#define WLAN_MBOX1_DMA_RX_CONTROL_OFFSET         0x0000002c
+#define WLAN_MBOX1_DMA_RX_CONTROL_RESUME_MSB     2
+#define WLAN_MBOX1_DMA_RX_CONTROL_RESUME_LSB     2
+#define WLAN_MBOX1_DMA_RX_CONTROL_RESUME_MASK    0x00000004
+#define WLAN_MBOX1_DMA_RX_CONTROL_RESUME_GET(x)  (((x) & WLAN_MBOX1_DMA_RX_CONTROL_RESUME_MASK) >> WLAN_MBOX1_DMA_RX_CONTROL_RESUME_LSB)
+#define WLAN_MBOX1_DMA_RX_CONTROL_RESUME_SET(x)  (((x) << WLAN_MBOX1_DMA_RX_CONTROL_RESUME_LSB) & WLAN_MBOX1_DMA_RX_CONTROL_RESUME_MASK)
+#define WLAN_MBOX1_DMA_RX_CONTROL_START_MSB      1
+#define WLAN_MBOX1_DMA_RX_CONTROL_START_LSB      1
+#define WLAN_MBOX1_DMA_RX_CONTROL_START_MASK     0x00000002
+#define WLAN_MBOX1_DMA_RX_CONTROL_START_GET(x)   (((x) & WLAN_MBOX1_DMA_RX_CONTROL_START_MASK) >> WLAN_MBOX1_DMA_RX_CONTROL_START_LSB)
+#define WLAN_MBOX1_DMA_RX_CONTROL_START_SET(x)   (((x) << WLAN_MBOX1_DMA_RX_CONTROL_START_LSB) & WLAN_MBOX1_DMA_RX_CONTROL_START_MASK)
+#define WLAN_MBOX1_DMA_RX_CONTROL_STOP_MSB       0
+#define WLAN_MBOX1_DMA_RX_CONTROL_STOP_LSB       0
+#define WLAN_MBOX1_DMA_RX_CONTROL_STOP_MASK      0x00000001
+#define WLAN_MBOX1_DMA_RX_CONTROL_STOP_GET(x)    (((x) & WLAN_MBOX1_DMA_RX_CONTROL_STOP_MASK) >> WLAN_MBOX1_DMA_RX_CONTROL_STOP_LSB)
+#define WLAN_MBOX1_DMA_RX_CONTROL_STOP_SET(x)    (((x) << WLAN_MBOX1_DMA_RX_CONTROL_STOP_LSB) & WLAN_MBOX1_DMA_RX_CONTROL_STOP_MASK)
+
+#define WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000030
+#define WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000030
+#define WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define WLAN_MBOX1_DMA_TX_CONTROL_ADDRESS        0x00000034
+#define WLAN_MBOX1_DMA_TX_CONTROL_OFFSET         0x00000034
+#define WLAN_MBOX1_DMA_TX_CONTROL_RESUME_MSB     2
+#define WLAN_MBOX1_DMA_TX_CONTROL_RESUME_LSB     2
+#define WLAN_MBOX1_DMA_TX_CONTROL_RESUME_MASK    0x00000004
+#define WLAN_MBOX1_DMA_TX_CONTROL_RESUME_GET(x)  (((x) & WLAN_MBOX1_DMA_TX_CONTROL_RESUME_MASK) >> WLAN_MBOX1_DMA_TX_CONTROL_RESUME_LSB)
+#define WLAN_MBOX1_DMA_TX_CONTROL_RESUME_SET(x)  (((x) << WLAN_MBOX1_DMA_TX_CONTROL_RESUME_LSB) & WLAN_MBOX1_DMA_TX_CONTROL_RESUME_MASK)
+#define WLAN_MBOX1_DMA_TX_CONTROL_START_MSB      1
+#define WLAN_MBOX1_DMA_TX_CONTROL_START_LSB      1
+#define WLAN_MBOX1_DMA_TX_CONTROL_START_MASK     0x00000002
+#define WLAN_MBOX1_DMA_TX_CONTROL_START_GET(x)   (((x) & WLAN_MBOX1_DMA_TX_CONTROL_START_MASK) >> WLAN_MBOX1_DMA_TX_CONTROL_START_LSB)
+#define WLAN_MBOX1_DMA_TX_CONTROL_START_SET(x)   (((x) << WLAN_MBOX1_DMA_TX_CONTROL_START_LSB) & WLAN_MBOX1_DMA_TX_CONTROL_START_MASK)
+#define WLAN_MBOX1_DMA_TX_CONTROL_STOP_MSB       0
+#define WLAN_MBOX1_DMA_TX_CONTROL_STOP_LSB       0
+#define WLAN_MBOX1_DMA_TX_CONTROL_STOP_MASK      0x00000001
+#define WLAN_MBOX1_DMA_TX_CONTROL_STOP_GET(x)    (((x) & WLAN_MBOX1_DMA_TX_CONTROL_STOP_MASK) >> WLAN_MBOX1_DMA_TX_CONTROL_STOP_LSB)
+#define WLAN_MBOX1_DMA_TX_CONTROL_STOP_SET(x)    (((x) << WLAN_MBOX1_DMA_TX_CONTROL_STOP_LSB) & WLAN_MBOX1_DMA_TX_CONTROL_STOP_MASK)
+
+#define WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000038
+#define WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000038
+#define WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define WLAN_MBOX2_DMA_RX_CONTROL_ADDRESS        0x0000003c
+#define WLAN_MBOX2_DMA_RX_CONTROL_OFFSET         0x0000003c
+#define WLAN_MBOX2_DMA_RX_CONTROL_RESUME_MSB     2
+#define WLAN_MBOX2_DMA_RX_CONTROL_RESUME_LSB     2
+#define WLAN_MBOX2_DMA_RX_CONTROL_RESUME_MASK    0x00000004
+#define WLAN_MBOX2_DMA_RX_CONTROL_RESUME_GET(x)  (((x) & WLAN_MBOX2_DMA_RX_CONTROL_RESUME_MASK) >> WLAN_MBOX2_DMA_RX_CONTROL_RESUME_LSB)
+#define WLAN_MBOX2_DMA_RX_CONTROL_RESUME_SET(x)  (((x) << WLAN_MBOX2_DMA_RX_CONTROL_RESUME_LSB) & WLAN_MBOX2_DMA_RX_CONTROL_RESUME_MASK)
+#define WLAN_MBOX2_DMA_RX_CONTROL_START_MSB      1
+#define WLAN_MBOX2_DMA_RX_CONTROL_START_LSB      1
+#define WLAN_MBOX2_DMA_RX_CONTROL_START_MASK     0x00000002
+#define WLAN_MBOX2_DMA_RX_CONTROL_START_GET(x)   (((x) & WLAN_MBOX2_DMA_RX_CONTROL_START_MASK) >> WLAN_MBOX2_DMA_RX_CONTROL_START_LSB)
+#define WLAN_MBOX2_DMA_RX_CONTROL_START_SET(x)   (((x) << WLAN_MBOX2_DMA_RX_CONTROL_START_LSB) & WLAN_MBOX2_DMA_RX_CONTROL_START_MASK)
+#define WLAN_MBOX2_DMA_RX_CONTROL_STOP_MSB       0
+#define WLAN_MBOX2_DMA_RX_CONTROL_STOP_LSB       0
+#define WLAN_MBOX2_DMA_RX_CONTROL_STOP_MASK      0x00000001
+#define WLAN_MBOX2_DMA_RX_CONTROL_STOP_GET(x)    (((x) & WLAN_MBOX2_DMA_RX_CONTROL_STOP_MASK) >> WLAN_MBOX2_DMA_RX_CONTROL_STOP_LSB)
+#define WLAN_MBOX2_DMA_RX_CONTROL_STOP_SET(x)    (((x) << WLAN_MBOX2_DMA_RX_CONTROL_STOP_LSB) & WLAN_MBOX2_DMA_RX_CONTROL_STOP_MASK)
+
+#define WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000040
+#define WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000040
+#define WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define WLAN_MBOX2_DMA_TX_CONTROL_ADDRESS        0x00000044
+#define WLAN_MBOX2_DMA_TX_CONTROL_OFFSET         0x00000044
+#define WLAN_MBOX2_DMA_TX_CONTROL_RESUME_MSB     2
+#define WLAN_MBOX2_DMA_TX_CONTROL_RESUME_LSB     2
+#define WLAN_MBOX2_DMA_TX_CONTROL_RESUME_MASK    0x00000004
+#define WLAN_MBOX2_DMA_TX_CONTROL_RESUME_GET(x)  (((x) & WLAN_MBOX2_DMA_TX_CONTROL_RESUME_MASK) >> WLAN_MBOX2_DMA_TX_CONTROL_RESUME_LSB)
+#define WLAN_MBOX2_DMA_TX_CONTROL_RESUME_SET(x)  (((x) << WLAN_MBOX2_DMA_TX_CONTROL_RESUME_LSB) & WLAN_MBOX2_DMA_TX_CONTROL_RESUME_MASK)
+#define WLAN_MBOX2_DMA_TX_CONTROL_START_MSB      1
+#define WLAN_MBOX2_DMA_TX_CONTROL_START_LSB      1
+#define WLAN_MBOX2_DMA_TX_CONTROL_START_MASK     0x00000002
+#define WLAN_MBOX2_DMA_TX_CONTROL_START_GET(x)   (((x) & WLAN_MBOX2_DMA_TX_CONTROL_START_MASK) >> WLAN_MBOX2_DMA_TX_CONTROL_START_LSB)
+#define WLAN_MBOX2_DMA_TX_CONTROL_START_SET(x)   (((x) << WLAN_MBOX2_DMA_TX_CONTROL_START_LSB) & WLAN_MBOX2_DMA_TX_CONTROL_START_MASK)
+#define WLAN_MBOX2_DMA_TX_CONTROL_STOP_MSB       0
+#define WLAN_MBOX2_DMA_TX_CONTROL_STOP_LSB       0
+#define WLAN_MBOX2_DMA_TX_CONTROL_STOP_MASK      0x00000001
+#define WLAN_MBOX2_DMA_TX_CONTROL_STOP_GET(x)    (((x) & WLAN_MBOX2_DMA_TX_CONTROL_STOP_MASK) >> WLAN_MBOX2_DMA_TX_CONTROL_STOP_LSB)
+#define WLAN_MBOX2_DMA_TX_CONTROL_STOP_SET(x)    (((x) << WLAN_MBOX2_DMA_TX_CONTROL_STOP_LSB) & WLAN_MBOX2_DMA_TX_CONTROL_STOP_MASK)
+
+#define WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000048
+#define WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000048
+#define WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define WLAN_MBOX3_DMA_RX_CONTROL_ADDRESS        0x0000004c
+#define WLAN_MBOX3_DMA_RX_CONTROL_OFFSET         0x0000004c
+#define WLAN_MBOX3_DMA_RX_CONTROL_RESUME_MSB     2
+#define WLAN_MBOX3_DMA_RX_CONTROL_RESUME_LSB     2
+#define WLAN_MBOX3_DMA_RX_CONTROL_RESUME_MASK    0x00000004
+#define WLAN_MBOX3_DMA_RX_CONTROL_RESUME_GET(x)  (((x) & WLAN_MBOX3_DMA_RX_CONTROL_RESUME_MASK) >> WLAN_MBOX3_DMA_RX_CONTROL_RESUME_LSB)
+#define WLAN_MBOX3_DMA_RX_CONTROL_RESUME_SET(x)  (((x) << WLAN_MBOX3_DMA_RX_CONTROL_RESUME_LSB) & WLAN_MBOX3_DMA_RX_CONTROL_RESUME_MASK)
+#define WLAN_MBOX3_DMA_RX_CONTROL_START_MSB      1
+#define WLAN_MBOX3_DMA_RX_CONTROL_START_LSB      1
+#define WLAN_MBOX3_DMA_RX_CONTROL_START_MASK     0x00000002
+#define WLAN_MBOX3_DMA_RX_CONTROL_START_GET(x)   (((x) & WLAN_MBOX3_DMA_RX_CONTROL_START_MASK) >> WLAN_MBOX3_DMA_RX_CONTROL_START_LSB)
+#define WLAN_MBOX3_DMA_RX_CONTROL_START_SET(x)   (((x) << WLAN_MBOX3_DMA_RX_CONTROL_START_LSB) & WLAN_MBOX3_DMA_RX_CONTROL_START_MASK)
+#define WLAN_MBOX3_DMA_RX_CONTROL_STOP_MSB       0
+#define WLAN_MBOX3_DMA_RX_CONTROL_STOP_LSB       0
+#define WLAN_MBOX3_DMA_RX_CONTROL_STOP_MASK      0x00000001
+#define WLAN_MBOX3_DMA_RX_CONTROL_STOP_GET(x)    (((x) & WLAN_MBOX3_DMA_RX_CONTROL_STOP_MASK) >> WLAN_MBOX3_DMA_RX_CONTROL_STOP_LSB)
+#define WLAN_MBOX3_DMA_RX_CONTROL_STOP_SET(x)    (((x) << WLAN_MBOX3_DMA_RX_CONTROL_STOP_LSB) & WLAN_MBOX3_DMA_RX_CONTROL_STOP_MASK)
+
+#define WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000050
+#define WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000050
+#define WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define WLAN_MBOX3_DMA_TX_CONTROL_ADDRESS        0x00000054
+#define WLAN_MBOX3_DMA_TX_CONTROL_OFFSET         0x00000054
+#define WLAN_MBOX3_DMA_TX_CONTROL_RESUME_MSB     2
+#define WLAN_MBOX3_DMA_TX_CONTROL_RESUME_LSB     2
+#define WLAN_MBOX3_DMA_TX_CONTROL_RESUME_MASK    0x00000004
+#define WLAN_MBOX3_DMA_TX_CONTROL_RESUME_GET(x)  (((x) & WLAN_MBOX3_DMA_TX_CONTROL_RESUME_MASK) >> WLAN_MBOX3_DMA_TX_CONTROL_RESUME_LSB)
+#define WLAN_MBOX3_DMA_TX_CONTROL_RESUME_SET(x)  (((x) << WLAN_MBOX3_DMA_TX_CONTROL_RESUME_LSB) & WLAN_MBOX3_DMA_TX_CONTROL_RESUME_MASK)
+#define WLAN_MBOX3_DMA_TX_CONTROL_START_MSB      1
+#define WLAN_MBOX3_DMA_TX_CONTROL_START_LSB      1
+#define WLAN_MBOX3_DMA_TX_CONTROL_START_MASK     0x00000002
+#define WLAN_MBOX3_DMA_TX_CONTROL_START_GET(x)   (((x) & WLAN_MBOX3_DMA_TX_CONTROL_START_MASK) >> WLAN_MBOX3_DMA_TX_CONTROL_START_LSB)
+#define WLAN_MBOX3_DMA_TX_CONTROL_START_SET(x)   (((x) << WLAN_MBOX3_DMA_TX_CONTROL_START_LSB) & WLAN_MBOX3_DMA_TX_CONTROL_START_MASK)
+#define WLAN_MBOX3_DMA_TX_CONTROL_STOP_MSB       0
+#define WLAN_MBOX3_DMA_TX_CONTROL_STOP_LSB       0
+#define WLAN_MBOX3_DMA_TX_CONTROL_STOP_MASK      0x00000001
+#define WLAN_MBOX3_DMA_TX_CONTROL_STOP_GET(x)    (((x) & WLAN_MBOX3_DMA_TX_CONTROL_STOP_MASK) >> WLAN_MBOX3_DMA_TX_CONTROL_STOP_LSB)
+#define WLAN_MBOX3_DMA_TX_CONTROL_STOP_SET(x)    (((x) << WLAN_MBOX3_DMA_TX_CONTROL_STOP_LSB) & WLAN_MBOX3_DMA_TX_CONTROL_STOP_MASK)
+
+#define WLAN_MBOX_INT_STATUS_ADDRESS             0x00000058
+#define WLAN_MBOX_INT_STATUS_OFFSET              0x00000058
+#define WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_MSB 31
+#define WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB 28
+#define WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK 0xf0000000
+#define WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) (((x) & WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK) >> WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB)
+#define WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) (((x) << WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB) & WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK)
+#define WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB 27
+#define WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB 24
+#define WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK 0x0f000000
+#define WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) (((x) & WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK) >> WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB)
+#define WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) (((x) << WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB) & WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK)
+#define WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_MSB 23
+#define WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB 20
+#define WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK 0x00f00000
+#define WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) (((x) & WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK) >> WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB)
+#define WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) (((x) << WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB) & WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK)
+#define WLAN_MBOX_INT_STATUS_TX_OVERFLOW_MSB     17
+#define WLAN_MBOX_INT_STATUS_TX_OVERFLOW_LSB     17
+#define WLAN_MBOX_INT_STATUS_TX_OVERFLOW_MASK    0x00020000
+#define WLAN_MBOX_INT_STATUS_TX_OVERFLOW_GET(x)  (((x) & WLAN_MBOX_INT_STATUS_TX_OVERFLOW_MASK) >> WLAN_MBOX_INT_STATUS_TX_OVERFLOW_LSB)
+#define WLAN_MBOX_INT_STATUS_TX_OVERFLOW_SET(x)  (((x) << WLAN_MBOX_INT_STATUS_TX_OVERFLOW_LSB) & WLAN_MBOX_INT_STATUS_TX_OVERFLOW_MASK)
+#define WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_MSB    16
+#define WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_LSB    16
+#define WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_MASK   0x00010000
+#define WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_GET(x) (((x) & WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_MASK) >> WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_LSB)
+#define WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_SET(x) (((x) << WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_LSB) & WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_MASK)
+#define WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_MSB    15
+#define WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_LSB    12
+#define WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_MASK   0x0000f000
+#define WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) (((x) & WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_MASK) >> WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_LSB)
+#define WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) (((x) << WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_LSB) & WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_MASK)
+#define WLAN_MBOX_INT_STATUS_RX_NOT_FULL_MSB     11
+#define WLAN_MBOX_INT_STATUS_RX_NOT_FULL_LSB     8
+#define WLAN_MBOX_INT_STATUS_RX_NOT_FULL_MASK    0x00000f00
+#define WLAN_MBOX_INT_STATUS_RX_NOT_FULL_GET(x)  (((x) & WLAN_MBOX_INT_STATUS_RX_NOT_FULL_MASK) >> WLAN_MBOX_INT_STATUS_RX_NOT_FULL_LSB)
+#define WLAN_MBOX_INT_STATUS_RX_NOT_FULL_SET(x)  (((x) << WLAN_MBOX_INT_STATUS_RX_NOT_FULL_LSB) & WLAN_MBOX_INT_STATUS_RX_NOT_FULL_MASK)
+#define WLAN_MBOX_INT_STATUS_HOST_MSB            7
+#define WLAN_MBOX_INT_STATUS_HOST_LSB            0
+#define WLAN_MBOX_INT_STATUS_HOST_MASK           0x000000ff
+#define WLAN_MBOX_INT_STATUS_HOST_GET(x)         (((x) & WLAN_MBOX_INT_STATUS_HOST_MASK) >> WLAN_MBOX_INT_STATUS_HOST_LSB)
+#define WLAN_MBOX_INT_STATUS_HOST_SET(x)         (((x) << WLAN_MBOX_INT_STATUS_HOST_LSB) & WLAN_MBOX_INT_STATUS_HOST_MASK)
+
+#define WLAN_MBOX_INT_ENABLE_ADDRESS             0x0000005c
+#define WLAN_MBOX_INT_ENABLE_OFFSET              0x0000005c
+#define WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB 31
+#define WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB 28
+#define WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK 0xf0000000
+#define WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK) >> WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB)
+#define WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB) & WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK)
+#define WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB 27
+#define WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB 24
+#define WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK 0x0f000000
+#define WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK) >> WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB)
+#define WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB) & WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK)
+#define WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB 23
+#define WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB 20
+#define WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK 0x00f00000
+#define WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK) >> WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB)
+#define WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB) & WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK)
+#define WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_MSB     17
+#define WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_LSB     17
+#define WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_MASK    0x00020000
+#define WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_GET(x)  (((x) & WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_MASK) >> WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_LSB)
+#define WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_SET(x)  (((x) << WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_LSB) & WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_MASK)
+#define WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_MSB    16
+#define WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_LSB    16
+#define WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_MASK   0x00010000
+#define WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_MASK) >> WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_LSB)
+#define WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_LSB) & WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_MASK)
+#define WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_MSB    15
+#define WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB    12
+#define WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK   0x0000f000
+#define WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK) >> WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB)
+#define WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB) & WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK)
+#define WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_MSB     11
+#define WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_LSB     8
+#define WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_MASK    0x00000f00
+#define WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_GET(x)  (((x) & WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_MASK) >> WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_LSB)
+#define WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_SET(x)  (((x) << WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_LSB) & WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_MASK)
+#define WLAN_MBOX_INT_ENABLE_HOST_MSB            7
+#define WLAN_MBOX_INT_ENABLE_HOST_LSB            0
+#define WLAN_MBOX_INT_ENABLE_HOST_MASK           0x000000ff
+#define WLAN_MBOX_INT_ENABLE_HOST_GET(x)         (((x) & WLAN_MBOX_INT_ENABLE_HOST_MASK) >> WLAN_MBOX_INT_ENABLE_HOST_LSB)
+#define WLAN_MBOX_INT_ENABLE_HOST_SET(x)         (((x) << WLAN_MBOX_INT_ENABLE_HOST_LSB) & WLAN_MBOX_INT_ENABLE_HOST_MASK)
+
+#define WLAN_INT_HOST_ADDRESS                    0x00000060
+#define WLAN_INT_HOST_OFFSET                     0x00000060
+#define WLAN_INT_HOST_VECTOR_MSB                 7
+#define WLAN_INT_HOST_VECTOR_LSB                 0
+#define WLAN_INT_HOST_VECTOR_MASK                0x000000ff
+#define WLAN_INT_HOST_VECTOR_GET(x)              (((x) & WLAN_INT_HOST_VECTOR_MASK) >> WLAN_INT_HOST_VECTOR_LSB)
+#define WLAN_INT_HOST_VECTOR_SET(x)              (((x) << WLAN_INT_HOST_VECTOR_LSB) & WLAN_INT_HOST_VECTOR_MASK)
+
+#define WLAN_LOCAL_COUNT_ADDRESS                 0x00000080
+#define WLAN_LOCAL_COUNT_OFFSET                  0x00000080
+#define WLAN_LOCAL_COUNT_VALUE_MSB               7
+#define WLAN_LOCAL_COUNT_VALUE_LSB               0
+#define WLAN_LOCAL_COUNT_VALUE_MASK              0x000000ff
+#define WLAN_LOCAL_COUNT_VALUE_GET(x)            (((x) & WLAN_LOCAL_COUNT_VALUE_MASK) >> WLAN_LOCAL_COUNT_VALUE_LSB)
+#define WLAN_LOCAL_COUNT_VALUE_SET(x)            (((x) << WLAN_LOCAL_COUNT_VALUE_LSB) & WLAN_LOCAL_COUNT_VALUE_MASK)
+
+#define WLAN_COUNT_INC_ADDRESS                   0x000000a0
+#define WLAN_COUNT_INC_OFFSET                    0x000000a0
+#define WLAN_COUNT_INC_VALUE_MSB                 7
+#define WLAN_COUNT_INC_VALUE_LSB                 0
+#define WLAN_COUNT_INC_VALUE_MASK                0x000000ff
+#define WLAN_COUNT_INC_VALUE_GET(x)              (((x) & WLAN_COUNT_INC_VALUE_MASK) >> WLAN_COUNT_INC_VALUE_LSB)
+#define WLAN_COUNT_INC_VALUE_SET(x)              (((x) << WLAN_COUNT_INC_VALUE_LSB) & WLAN_COUNT_INC_VALUE_MASK)
+
+#define WLAN_LOCAL_SCRATCH_ADDRESS               0x000000c0
+#define WLAN_LOCAL_SCRATCH_OFFSET                0x000000c0
+#define WLAN_LOCAL_SCRATCH_VALUE_MSB             7
+#define WLAN_LOCAL_SCRATCH_VALUE_LSB             0
+#define WLAN_LOCAL_SCRATCH_VALUE_MASK            0x000000ff
+#define WLAN_LOCAL_SCRATCH_VALUE_GET(x)          (((x) & WLAN_LOCAL_SCRATCH_VALUE_MASK) >> WLAN_LOCAL_SCRATCH_VALUE_LSB)
+#define WLAN_LOCAL_SCRATCH_VALUE_SET(x)          (((x) << WLAN_LOCAL_SCRATCH_VALUE_LSB) & WLAN_LOCAL_SCRATCH_VALUE_MASK)
+
+#define WLAN_USE_LOCAL_BUS_ADDRESS               0x000000e0
+#define WLAN_USE_LOCAL_BUS_OFFSET                0x000000e0
+#define WLAN_USE_LOCAL_BUS_PIN_INIT_MSB          0
+#define WLAN_USE_LOCAL_BUS_PIN_INIT_LSB          0
+#define WLAN_USE_LOCAL_BUS_PIN_INIT_MASK         0x00000001
+#define WLAN_USE_LOCAL_BUS_PIN_INIT_GET(x)       (((x) & WLAN_USE_LOCAL_BUS_PIN_INIT_MASK) >> WLAN_USE_LOCAL_BUS_PIN_INIT_LSB)
+#define WLAN_USE_LOCAL_BUS_PIN_INIT_SET(x)       (((x) << WLAN_USE_LOCAL_BUS_PIN_INIT_LSB) & WLAN_USE_LOCAL_BUS_PIN_INIT_MASK)
+
+#define WLAN_SDIO_CONFIG_ADDRESS                 0x000000e4
+#define WLAN_SDIO_CONFIG_OFFSET                  0x000000e4
+#define WLAN_SDIO_CONFIG_CCCR_IOR1_MSB           0
+#define WLAN_SDIO_CONFIG_CCCR_IOR1_LSB           0
+#define WLAN_SDIO_CONFIG_CCCR_IOR1_MASK          0x00000001
+#define WLAN_SDIO_CONFIG_CCCR_IOR1_GET(x)        (((x) & WLAN_SDIO_CONFIG_CCCR_IOR1_MASK) >> WLAN_SDIO_CONFIG_CCCR_IOR1_LSB)
+#define WLAN_SDIO_CONFIG_CCCR_IOR1_SET(x)        (((x) << WLAN_SDIO_CONFIG_CCCR_IOR1_LSB) & WLAN_SDIO_CONFIG_CCCR_IOR1_MASK)
+
+#define WLAN_MBOX_DEBUG_ADDRESS                  0x000000e8
+#define WLAN_MBOX_DEBUG_OFFSET                   0x000000e8
+#define WLAN_MBOX_DEBUG_SEL_MSB                  2
+#define WLAN_MBOX_DEBUG_SEL_LSB                  0
+#define WLAN_MBOX_DEBUG_SEL_MASK                 0x00000007
+#define WLAN_MBOX_DEBUG_SEL_GET(x)               (((x) & WLAN_MBOX_DEBUG_SEL_MASK) >> WLAN_MBOX_DEBUG_SEL_LSB)
+#define WLAN_MBOX_DEBUG_SEL_SET(x)               (((x) << WLAN_MBOX_DEBUG_SEL_LSB) & WLAN_MBOX_DEBUG_SEL_MASK)
+
+#define WLAN_MBOX_FIFO_RESET_ADDRESS             0x000000ec
+#define WLAN_MBOX_FIFO_RESET_OFFSET              0x000000ec
+#define WLAN_MBOX_FIFO_RESET_INIT_MSB            0
+#define WLAN_MBOX_FIFO_RESET_INIT_LSB            0
+#define WLAN_MBOX_FIFO_RESET_INIT_MASK           0x00000001
+#define WLAN_MBOX_FIFO_RESET_INIT_GET(x)         (((x) & WLAN_MBOX_FIFO_RESET_INIT_MASK) >> WLAN_MBOX_FIFO_RESET_INIT_LSB)
+#define WLAN_MBOX_FIFO_RESET_INIT_SET(x)         (((x) << WLAN_MBOX_FIFO_RESET_INIT_LSB) & WLAN_MBOX_FIFO_RESET_INIT_MASK)
+
+#define WLAN_MBOX_TXFIFO_POP_ADDRESS             0x000000f0
+#define WLAN_MBOX_TXFIFO_POP_OFFSET              0x000000f0
+#define WLAN_MBOX_TXFIFO_POP_DATA_MSB            0
+#define WLAN_MBOX_TXFIFO_POP_DATA_LSB            0
+#define WLAN_MBOX_TXFIFO_POP_DATA_MASK           0x00000001
+#define WLAN_MBOX_TXFIFO_POP_DATA_GET(x)         (((x) & WLAN_MBOX_TXFIFO_POP_DATA_MASK) >> WLAN_MBOX_TXFIFO_POP_DATA_LSB)
+#define WLAN_MBOX_TXFIFO_POP_DATA_SET(x)         (((x) << WLAN_MBOX_TXFIFO_POP_DATA_LSB) & WLAN_MBOX_TXFIFO_POP_DATA_MASK)
+
+#define WLAN_MBOX_RXFIFO_POP_ADDRESS             0x00000100
+#define WLAN_MBOX_RXFIFO_POP_OFFSET              0x00000100
+#define WLAN_MBOX_RXFIFO_POP_DATA_MSB            0
+#define WLAN_MBOX_RXFIFO_POP_DATA_LSB            0
+#define WLAN_MBOX_RXFIFO_POP_DATA_MASK           0x00000001
+#define WLAN_MBOX_RXFIFO_POP_DATA_GET(x)         (((x) & WLAN_MBOX_RXFIFO_POP_DATA_MASK) >> WLAN_MBOX_RXFIFO_POP_DATA_LSB)
+#define WLAN_MBOX_RXFIFO_POP_DATA_SET(x)         (((x) << WLAN_MBOX_RXFIFO_POP_DATA_LSB) & WLAN_MBOX_RXFIFO_POP_DATA_MASK)
+
+#define WLAN_SDIO_DEBUG_ADDRESS                  0x00000110
+#define WLAN_SDIO_DEBUG_OFFSET                   0x00000110
+#define WLAN_SDIO_DEBUG_SEL_MSB                  3
+#define WLAN_SDIO_DEBUG_SEL_LSB                  0
+#define WLAN_SDIO_DEBUG_SEL_MASK                 0x0000000f
+#define WLAN_SDIO_DEBUG_SEL_GET(x)               (((x) & WLAN_SDIO_DEBUG_SEL_MASK) >> WLAN_SDIO_DEBUG_SEL_LSB)
+#define WLAN_SDIO_DEBUG_SEL_SET(x)               (((x) << WLAN_SDIO_DEBUG_SEL_LSB) & WLAN_SDIO_DEBUG_SEL_MASK)
+
+#define WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000114
+#define WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000114
+#define WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define WLAN_GMBOX0_DMA_RX_CONTROL_ADDRESS       0x00000118
+#define WLAN_GMBOX0_DMA_RX_CONTROL_OFFSET        0x00000118
+#define WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_MSB    2
+#define WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_LSB    2
+#define WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_MASK   0x00000004
+#define WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_GET(x) (((x) & WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_MASK) >> WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_LSB)
+#define WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_SET(x) (((x) << WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_LSB) & WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_MASK)
+#define WLAN_GMBOX0_DMA_RX_CONTROL_START_MSB     1
+#define WLAN_GMBOX0_DMA_RX_CONTROL_START_LSB     1
+#define WLAN_GMBOX0_DMA_RX_CONTROL_START_MASK    0x00000002
+#define WLAN_GMBOX0_DMA_RX_CONTROL_START_GET(x)  (((x) & WLAN_GMBOX0_DMA_RX_CONTROL_START_MASK) >> WLAN_GMBOX0_DMA_RX_CONTROL_START_LSB)
+#define WLAN_GMBOX0_DMA_RX_CONTROL_START_SET(x)  (((x) << WLAN_GMBOX0_DMA_RX_CONTROL_START_LSB) & WLAN_GMBOX0_DMA_RX_CONTROL_START_MASK)
+#define WLAN_GMBOX0_DMA_RX_CONTROL_STOP_MSB      0
+#define WLAN_GMBOX0_DMA_RX_CONTROL_STOP_LSB      0
+#define WLAN_GMBOX0_DMA_RX_CONTROL_STOP_MASK     0x00000001
+#define WLAN_GMBOX0_DMA_RX_CONTROL_STOP_GET(x)   (((x) & WLAN_GMBOX0_DMA_RX_CONTROL_STOP_MASK) >> WLAN_GMBOX0_DMA_RX_CONTROL_STOP_LSB)
+#define WLAN_GMBOX0_DMA_RX_CONTROL_STOP_SET(x)   (((x) << WLAN_GMBOX0_DMA_RX_CONTROL_STOP_LSB) & WLAN_GMBOX0_DMA_RX_CONTROL_STOP_MASK)
+
+#define WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x0000011c
+#define WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x0000011c
+#define WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define WLAN_GMBOX0_DMA_TX_CONTROL_ADDRESS       0x00000120
+#define WLAN_GMBOX0_DMA_TX_CONTROL_OFFSET        0x00000120
+#define WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_MSB    2
+#define WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_LSB    2
+#define WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_MASK   0x00000004
+#define WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_GET(x) (((x) & WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_MASK) >> WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_LSB)
+#define WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_SET(x) (((x) << WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_LSB) & WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_MASK)
+#define WLAN_GMBOX0_DMA_TX_CONTROL_START_MSB     1
+#define WLAN_GMBOX0_DMA_TX_CONTROL_START_LSB     1
+#define WLAN_GMBOX0_DMA_TX_CONTROL_START_MASK    0x00000002
+#define WLAN_GMBOX0_DMA_TX_CONTROL_START_GET(x)  (((x) & WLAN_GMBOX0_DMA_TX_CONTROL_START_MASK) >> WLAN_GMBOX0_DMA_TX_CONTROL_START_LSB)
+#define WLAN_GMBOX0_DMA_TX_CONTROL_START_SET(x)  (((x) << WLAN_GMBOX0_DMA_TX_CONTROL_START_LSB) & WLAN_GMBOX0_DMA_TX_CONTROL_START_MASK)
+#define WLAN_GMBOX0_DMA_TX_CONTROL_STOP_MSB      0
+#define WLAN_GMBOX0_DMA_TX_CONTROL_STOP_LSB      0
+#define WLAN_GMBOX0_DMA_TX_CONTROL_STOP_MASK     0x00000001
+#define WLAN_GMBOX0_DMA_TX_CONTROL_STOP_GET(x)   (((x) & WLAN_GMBOX0_DMA_TX_CONTROL_STOP_MASK) >> WLAN_GMBOX0_DMA_TX_CONTROL_STOP_LSB)
+#define WLAN_GMBOX0_DMA_TX_CONTROL_STOP_SET(x)   (((x) << WLAN_GMBOX0_DMA_TX_CONTROL_STOP_LSB) & WLAN_GMBOX0_DMA_TX_CONTROL_STOP_MASK)
+
+#define WLAN_GMBOX_INT_STATUS_ADDRESS            0x00000124
+#define WLAN_GMBOX_INT_STATUS_OFFSET             0x00000124
+#define WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_MSB    6
+#define WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_LSB    6
+#define WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_MASK   0x00000040
+#define WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_GET(x) (((x) & WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_MASK) >> WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_LSB)
+#define WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_SET(x) (((x) << WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_LSB) & WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_MASK)
+#define WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_MSB   5
+#define WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_LSB   5
+#define WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_MASK  0x00000020
+#define WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_GET(x) (((x) & WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_MASK) >> WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_LSB)
+#define WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_SET(x) (((x) << WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_LSB) & WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_MASK)
+#define WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_MSB 4
+#define WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB 4
+#define WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK 0x00000010
+#define WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) (((x) & WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK) >> WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB)
+#define WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) (((x) << WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB) & WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK)
+#define WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB 3
+#define WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB 3
+#define WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK 0x00000008
+#define WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) (((x) & WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK) >> WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB)
+#define WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) (((x) << WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB) & WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK)
+#define WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_MSB 2
+#define WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB 2
+#define WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK 0x00000004
+#define WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) (((x) & WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK) >> WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB)
+#define WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) (((x) << WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB) & WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK)
+#define WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_MSB   1
+#define WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_LSB   1
+#define WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_MASK  0x00000002
+#define WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) (((x) & WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_MASK) >> WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_LSB)
+#define WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) (((x) << WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_LSB) & WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_MASK)
+#define WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_MSB    0
+#define WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_LSB    0
+#define WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_MASK   0x00000001
+#define WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_GET(x) (((x) & WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_MASK) >> WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_LSB)
+#define WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_SET(x) (((x) << WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_LSB) & WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_MASK)
+
+#define WLAN_GMBOX_INT_ENABLE_ADDRESS            0x00000128
+#define WLAN_GMBOX_INT_ENABLE_OFFSET             0x00000128
+#define WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_MSB    6
+#define WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_LSB    6
+#define WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_MASK   0x00000040
+#define WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_GET(x) (((x) & WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_MASK) >> WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_LSB)
+#define WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_SET(x) (((x) << WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_LSB) & WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_MASK)
+#define WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_MSB   5
+#define WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_LSB   5
+#define WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_MASK  0x00000020
+#define WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) (((x) & WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_MASK) >> WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_LSB)
+#define WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) (((x) << WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_LSB) & WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_MASK)
+#define WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB 4
+#define WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB 4
+#define WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK 0x00000010
+#define WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) (((x) & WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK) >> WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB)
+#define WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) (((x) << WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB) & WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK)
+#define WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB 3
+#define WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB 3
+#define WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK 0x00000008
+#define WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) (((x) & WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK) >> WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB)
+#define WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) (((x) << WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB) & WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK)
+#define WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB 2
+#define WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB 2
+#define WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK 0x00000004
+#define WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) (((x) & WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK) >> WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB)
+#define WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) (((x) << WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB) & WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK)
+#define WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_MSB   1
+#define WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB   1
+#define WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK  0x00000002
+#define WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) (((x) & WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK) >> WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB)
+#define WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) (((x) << WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB) & WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK)
+#define WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_MSB    0
+#define WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_LSB    0
+#define WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_MASK   0x00000001
+#define WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_GET(x) (((x) & WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_MASK) >> WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_LSB)
+#define WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_SET(x) (((x) << WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_LSB) & WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_MASK)
+
+#define WLAN_HOST_IF_WINDOW_ADDRESS              0x00002000
+#define WLAN_HOST_IF_WINDOW_OFFSET               0x00002000
+#define WLAN_HOST_IF_WINDOW_DATA_MSB             7
+#define WLAN_HOST_IF_WINDOW_DATA_LSB             0
+#define WLAN_HOST_IF_WINDOW_DATA_MASK            0x000000ff
+#define WLAN_HOST_IF_WINDOW_DATA_GET(x)          (((x) & WLAN_HOST_IF_WINDOW_DATA_MASK) >> WLAN_HOST_IF_WINDOW_DATA_LSB)
+#define WLAN_HOST_IF_WINDOW_DATA_SET(x)          (((x) << WLAN_HOST_IF_WINDOW_DATA_LSB) & WLAN_HOST_IF_WINDOW_DATA_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct mbox_wlan_reg_reg_s {
+  volatile unsigned int wlan_mbox_fifo[4];
+  volatile unsigned int wlan_mbox_fifo_status;
+  volatile unsigned int wlan_mbox_dma_policy;
+  volatile unsigned int wlan_mbox0_dma_rx_descriptor_base;
+  volatile unsigned int wlan_mbox0_dma_rx_control;
+  volatile unsigned int wlan_mbox0_dma_tx_descriptor_base;
+  volatile unsigned int wlan_mbox0_dma_tx_control;
+  volatile unsigned int wlan_mbox1_dma_rx_descriptor_base;
+  volatile unsigned int wlan_mbox1_dma_rx_control;
+  volatile unsigned int wlan_mbox1_dma_tx_descriptor_base;
+  volatile unsigned int wlan_mbox1_dma_tx_control;
+  volatile unsigned int wlan_mbox2_dma_rx_descriptor_base;
+  volatile unsigned int wlan_mbox2_dma_rx_control;
+  volatile unsigned int wlan_mbox2_dma_tx_descriptor_base;
+  volatile unsigned int wlan_mbox2_dma_tx_control;
+  volatile unsigned int wlan_mbox3_dma_rx_descriptor_base;
+  volatile unsigned int wlan_mbox3_dma_rx_control;
+  volatile unsigned int wlan_mbox3_dma_tx_descriptor_base;
+  volatile unsigned int wlan_mbox3_dma_tx_control;
+  volatile unsigned int wlan_mbox_int_status;
+  volatile unsigned int wlan_mbox_int_enable;
+  volatile unsigned int wlan_int_host;
+  unsigned char pad0[28]; /* pad to 0x80 */
+  volatile unsigned int wlan_local_count[8];
+  volatile unsigned int wlan_count_inc[8];
+  volatile unsigned int wlan_local_scratch[8];
+  volatile unsigned int wlan_use_local_bus;
+  volatile unsigned int wlan_sdio_config;
+  volatile unsigned int wlan_mbox_debug;
+  volatile unsigned int wlan_mbox_fifo_reset;
+  volatile unsigned int wlan_mbox_txfifo_pop[4];
+  volatile unsigned int wlan_mbox_rxfifo_pop[4];
+  volatile unsigned int wlan_sdio_debug;
+  volatile unsigned int wlan_gmbox0_dma_rx_descriptor_base;
+  volatile unsigned int wlan_gmbox0_dma_rx_control;
+  volatile unsigned int wlan_gmbox0_dma_tx_descriptor_base;
+  volatile unsigned int wlan_gmbox0_dma_tx_control;
+  volatile unsigned int wlan_gmbox_int_status;
+  volatile unsigned int wlan_gmbox_int_enable;
+  unsigned char pad1[7892]; /* pad to 0x2000 */
+  volatile unsigned int wlan_host_if_window[2048];
+} mbox_wlan_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _MBOX_WLAN_REG_H_ */
diff --git a/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/rdma_reg.h b/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/rdma_reg.h
new file mode 100644
index 00000000000..56ffda5b1a3
--- /dev/null
+++ b/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/rdma_reg.h
@@ -0,0 +1,564 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _RDMA_REG_REG_H_
+#define _RDMA_REG_REG_H_
+
+#define DMA_CONFIG_ADDRESS                       0x00000000
+#define DMA_CONFIG_OFFSET                        0x00000000
+#define DMA_CONFIG_WLBB_PWD_EN_MSB               4
+#define DMA_CONFIG_WLBB_PWD_EN_LSB               4
+#define DMA_CONFIG_WLBB_PWD_EN_MASK              0x00000010
+#define DMA_CONFIG_WLBB_PWD_EN_GET(x)            (((x) & DMA_CONFIG_WLBB_PWD_EN_MASK) >> DMA_CONFIG_WLBB_PWD_EN_LSB)
+#define DMA_CONFIG_WLBB_PWD_EN_SET(x)            (((x) << DMA_CONFIG_WLBB_PWD_EN_LSB) & DMA_CONFIG_WLBB_PWD_EN_MASK)
+#define DMA_CONFIG_WLMAC_PWD_EN_MSB              3
+#define DMA_CONFIG_WLMAC_PWD_EN_LSB              3
+#define DMA_CONFIG_WLMAC_PWD_EN_MASK             0x00000008
+#define DMA_CONFIG_WLMAC_PWD_EN_GET(x)           (((x) & DMA_CONFIG_WLMAC_PWD_EN_MASK) >> DMA_CONFIG_WLMAC_PWD_EN_LSB)
+#define DMA_CONFIG_WLMAC_PWD_EN_SET(x)           (((x) << DMA_CONFIG_WLMAC_PWD_EN_LSB) & DMA_CONFIG_WLMAC_PWD_EN_MASK)
+#define DMA_CONFIG_ENABLE_RETENTION_MSB          2
+#define DMA_CONFIG_ENABLE_RETENTION_LSB          2
+#define DMA_CONFIG_ENABLE_RETENTION_MASK         0x00000004
+#define DMA_CONFIG_ENABLE_RETENTION_GET(x)       (((x) & DMA_CONFIG_ENABLE_RETENTION_MASK) >> DMA_CONFIG_ENABLE_RETENTION_LSB)
+#define DMA_CONFIG_ENABLE_RETENTION_SET(x)       (((x) << DMA_CONFIG_ENABLE_RETENTION_LSB) & DMA_CONFIG_ENABLE_RETENTION_MASK)
+#define DMA_CONFIG_RTC_PRIORITY_MSB              1
+#define DMA_CONFIG_RTC_PRIORITY_LSB              1
+#define DMA_CONFIG_RTC_PRIORITY_MASK             0x00000002
+#define DMA_CONFIG_RTC_PRIORITY_GET(x)           (((x) & DMA_CONFIG_RTC_PRIORITY_MASK) >> DMA_CONFIG_RTC_PRIORITY_LSB)
+#define DMA_CONFIG_RTC_PRIORITY_SET(x)           (((x) << DMA_CONFIG_RTC_PRIORITY_LSB) & DMA_CONFIG_RTC_PRIORITY_MASK)
+#define DMA_CONFIG_DMA_TYPE_MSB                  0
+#define DMA_CONFIG_DMA_TYPE_LSB                  0
+#define DMA_CONFIG_DMA_TYPE_MASK                 0x00000001
+#define DMA_CONFIG_DMA_TYPE_GET(x)               (((x) & DMA_CONFIG_DMA_TYPE_MASK) >> DMA_CONFIG_DMA_TYPE_LSB)
+#define DMA_CONFIG_DMA_TYPE_SET(x)               (((x) << DMA_CONFIG_DMA_TYPE_LSB) & DMA_CONFIG_DMA_TYPE_MASK)
+
+#define DMA_CONTROL_ADDRESS                      0x00000004
+#define DMA_CONTROL_OFFSET                       0x00000004
+#define DMA_CONTROL_START_MSB                    1
+#define DMA_CONTROL_START_LSB                    1
+#define DMA_CONTROL_START_MASK                   0x00000002
+#define DMA_CONTROL_START_GET(x)                 (((x) & DMA_CONTROL_START_MASK) >> DMA_CONTROL_START_LSB)
+#define DMA_CONTROL_START_SET(x)                 (((x) << DMA_CONTROL_START_LSB) & DMA_CONTROL_START_MASK)
+#define DMA_CONTROL_STOP_MSB                     0
+#define DMA_CONTROL_STOP_LSB                     0
+#define DMA_CONTROL_STOP_MASK                    0x00000001
+#define DMA_CONTROL_STOP_GET(x)                  (((x) & DMA_CONTROL_STOP_MASK) >> DMA_CONTROL_STOP_LSB)
+#define DMA_CONTROL_STOP_SET(x)                  (((x) << DMA_CONTROL_STOP_LSB) & DMA_CONTROL_STOP_MASK)
+
+#define DMA_SRC_ADDRESS                          0x00000008
+#define DMA_SRC_OFFSET                           0x00000008
+#define DMA_SRC_ADDR_MSB                         31
+#define DMA_SRC_ADDR_LSB                         2
+#define DMA_SRC_ADDR_MASK                        0xfffffffc
+#define DMA_SRC_ADDR_GET(x)                      (((x) & DMA_SRC_ADDR_MASK) >> DMA_SRC_ADDR_LSB)
+#define DMA_SRC_ADDR_SET(x)                      (((x) << DMA_SRC_ADDR_LSB) & DMA_SRC_ADDR_MASK)
+
+#define DMA_DEST_ADDRESS                         0x0000000c
+#define DMA_DEST_OFFSET                          0x0000000c
+#define DMA_DEST_ADDR_MSB                        31
+#define DMA_DEST_ADDR_LSB                        2
+#define DMA_DEST_ADDR_MASK                       0xfffffffc
+#define DMA_DEST_ADDR_GET(x)                     (((x) & DMA_DEST_ADDR_MASK) >> DMA_DEST_ADDR_LSB)
+#define DMA_DEST_ADDR_SET(x)                     (((x) << DMA_DEST_ADDR_LSB) & DMA_DEST_ADDR_MASK)
+
+#define DMA_LENGTH_ADDRESS                       0x00000010
+#define DMA_LENGTH_OFFSET                        0x00000010
+#define DMA_LENGTH_WORDS_MSB                     11
+#define DMA_LENGTH_WORDS_LSB                     0
+#define DMA_LENGTH_WORDS_MASK                    0x00000fff
+#define DMA_LENGTH_WORDS_GET(x)                  (((x) & DMA_LENGTH_WORDS_MASK) >> DMA_LENGTH_WORDS_LSB)
+#define DMA_LENGTH_WORDS_SET(x)                  (((x) << DMA_LENGTH_WORDS_LSB) & DMA_LENGTH_WORDS_MASK)
+
+#define VMC_BASE_ADDRESS                         0x00000014
+#define VMC_BASE_OFFSET                          0x00000014
+#define VMC_BASE_ADDR_MSB                        31
+#define VMC_BASE_ADDR_LSB                        2
+#define VMC_BASE_ADDR_MASK                       0xfffffffc
+#define VMC_BASE_ADDR_GET(x)                     (((x) & VMC_BASE_ADDR_MASK) >> VMC_BASE_ADDR_LSB)
+#define VMC_BASE_ADDR_SET(x)                     (((x) << VMC_BASE_ADDR_LSB) & VMC_BASE_ADDR_MASK)
+
+#define INDIRECT_REG_ADDRESS                     0x00000018
+#define INDIRECT_REG_OFFSET                      0x00000018
+#define INDIRECT_REG_ID_MSB                      31
+#define INDIRECT_REG_ID_LSB                      2
+#define INDIRECT_REG_ID_MASK                     0xfffffffc
+#define INDIRECT_REG_ID_GET(x)                   (((x) & INDIRECT_REG_ID_MASK) >> INDIRECT_REG_ID_LSB)
+#define INDIRECT_REG_ID_SET(x)                   (((x) << INDIRECT_REG_ID_LSB) & INDIRECT_REG_ID_MASK)
+
+#define INDIRECT_RETURN_ADDRESS                  0x0000001c
+#define INDIRECT_RETURN_OFFSET                   0x0000001c
+#define INDIRECT_RETURN_ADDR_MSB                 31
+#define INDIRECT_RETURN_ADDR_LSB                 2
+#define INDIRECT_RETURN_ADDR_MASK                0xfffffffc
+#define INDIRECT_RETURN_ADDR_GET(x)              (((x) & INDIRECT_RETURN_ADDR_MASK) >> INDIRECT_RETURN_ADDR_LSB)
+#define INDIRECT_RETURN_ADDR_SET(x)              (((x) << INDIRECT_RETURN_ADDR_LSB) & INDIRECT_RETURN_ADDR_MASK)
+
+#define RDMA_REGION_0__ADDRESS                   0x00000020
+#define RDMA_REGION_0__OFFSET                    0x00000020
+#define RDMA_REGION_0__ADDR_MSB                  31
+#define RDMA_REGION_0__ADDR_LSB                  13
+#define RDMA_REGION_0__ADDR_MASK                 0xffffe000
+#define RDMA_REGION_0__ADDR_GET(x)               (((x) & RDMA_REGION_0__ADDR_MASK) >> RDMA_REGION_0__ADDR_LSB)
+#define RDMA_REGION_0__ADDR_SET(x)               (((x) << RDMA_REGION_0__ADDR_LSB) & RDMA_REGION_0__ADDR_MASK)
+#define RDMA_REGION_0__LENGTH_MSB                12
+#define RDMA_REGION_0__LENGTH_LSB                2
+#define RDMA_REGION_0__LENGTH_MASK               0x00001ffc
+#define RDMA_REGION_0__LENGTH_GET(x)             (((x) & RDMA_REGION_0__LENGTH_MASK) >> RDMA_REGION_0__LENGTH_LSB)
+#define RDMA_REGION_0__LENGTH_SET(x)             (((x) << RDMA_REGION_0__LENGTH_LSB) & RDMA_REGION_0__LENGTH_MASK)
+#define RDMA_REGION_0__INDI_MSB                  1
+#define RDMA_REGION_0__INDI_LSB                  1
+#define RDMA_REGION_0__INDI_MASK                 0x00000002
+#define RDMA_REGION_0__INDI_GET(x)               (((x) & RDMA_REGION_0__INDI_MASK) >> RDMA_REGION_0__INDI_LSB)
+#define RDMA_REGION_0__INDI_SET(x)               (((x) << RDMA_REGION_0__INDI_LSB) & RDMA_REGION_0__INDI_MASK)
+#define RDMA_REGION_0__NEXT_MSB                  0
+#define RDMA_REGION_0__NEXT_LSB                  0
+#define RDMA_REGION_0__NEXT_MASK                 0x00000001
+#define RDMA_REGION_0__NEXT_GET(x)               (((x) & RDMA_REGION_0__NEXT_MASK) >> RDMA_REGION_0__NEXT_LSB)
+#define RDMA_REGION_0__NEXT_SET(x)               (((x) << RDMA_REGION_0__NEXT_LSB) & RDMA_REGION_0__NEXT_MASK)
+
+#define RDMA_REGION_1__ADDRESS                   0x00000024
+#define RDMA_REGION_1__OFFSET                    0x00000024
+#define RDMA_REGION_1__ADDR_MSB                  31
+#define RDMA_REGION_1__ADDR_LSB                  13
+#define RDMA_REGION_1__ADDR_MASK                 0xffffe000
+#define RDMA_REGION_1__ADDR_GET(x)               (((x) & RDMA_REGION_1__ADDR_MASK) >> RDMA_REGION_1__ADDR_LSB)
+#define RDMA_REGION_1__ADDR_SET(x)               (((x) << RDMA_REGION_1__ADDR_LSB) & RDMA_REGION_1__ADDR_MASK)
+#define RDMA_REGION_1__LENGTH_MSB                12
+#define RDMA_REGION_1__LENGTH_LSB                2
+#define RDMA_REGION_1__LENGTH_MASK               0x00001ffc
+#define RDMA_REGION_1__LENGTH_GET(x)             (((x) & RDMA_REGION_1__LENGTH_MASK) >> RDMA_REGION_1__LENGTH_LSB)
+#define RDMA_REGION_1__LENGTH_SET(x)             (((x) << RDMA_REGION_1__LENGTH_LSB) & RDMA_REGION_1__LENGTH_MASK)
+#define RDMA_REGION_1__INDI_MSB                  1
+#define RDMA_REGION_1__INDI_LSB                  1
+#define RDMA_REGION_1__INDI_MASK                 0x00000002
+#define RDMA_REGION_1__INDI_GET(x)               (((x) & RDMA_REGION_1__INDI_MASK) >> RDMA_REGION_1__INDI_LSB)
+#define RDMA_REGION_1__INDI_SET(x)               (((x) << RDMA_REGION_1__INDI_LSB) & RDMA_REGION_1__INDI_MASK)
+#define RDMA_REGION_1__NEXT_MSB                  0
+#define RDMA_REGION_1__NEXT_LSB                  0
+#define RDMA_REGION_1__NEXT_MASK                 0x00000001
+#define RDMA_REGION_1__NEXT_GET(x)               (((x) & RDMA_REGION_1__NEXT_MASK) >> RDMA_REGION_1__NEXT_LSB)
+#define RDMA_REGION_1__NEXT_SET(x)               (((x) << RDMA_REGION_1__NEXT_LSB) & RDMA_REGION_1__NEXT_MASK)
+
+#define RDMA_REGION_2__ADDRESS                   0x00000028
+#define RDMA_REGION_2__OFFSET                    0x00000028
+#define RDMA_REGION_2__ADDR_MSB                  31
+#define RDMA_REGION_2__ADDR_LSB                  13
+#define RDMA_REGION_2__ADDR_MASK                 0xffffe000
+#define RDMA_REGION_2__ADDR_GET(x)               (((x) & RDMA_REGION_2__ADDR_MASK) >> RDMA_REGION_2__ADDR_LSB)
+#define RDMA_REGION_2__ADDR_SET(x)               (((x) << RDMA_REGION_2__ADDR_LSB) & RDMA_REGION_2__ADDR_MASK)
+#define RDMA_REGION_2__LENGTH_MSB                12
+#define RDMA_REGION_2__LENGTH_LSB                2
+#define RDMA_REGION_2__LENGTH_MASK               0x00001ffc
+#define RDMA_REGION_2__LENGTH_GET(x)             (((x) & RDMA_REGION_2__LENGTH_MASK) >> RDMA_REGION_2__LENGTH_LSB)
+#define RDMA_REGION_2__LENGTH_SET(x)             (((x) << RDMA_REGION_2__LENGTH_LSB) & RDMA_REGION_2__LENGTH_MASK)
+#define RDMA_REGION_2__INDI_MSB                  1
+#define RDMA_REGION_2__INDI_LSB                  1
+#define RDMA_REGION_2__INDI_MASK                 0x00000002
+#define RDMA_REGION_2__INDI_GET(x)               (((x) & RDMA_REGION_2__INDI_MASK) >> RDMA_REGION_2__INDI_LSB)
+#define RDMA_REGION_2__INDI_SET(x)               (((x) << RDMA_REGION_2__INDI_LSB) & RDMA_REGION_2__INDI_MASK)
+#define RDMA_REGION_2__NEXT_MSB                  0
+#define RDMA_REGION_2__NEXT_LSB                  0
+#define RDMA_REGION_2__NEXT_MASK                 0x00000001
+#define RDMA_REGION_2__NEXT_GET(x)               (((x) & RDMA_REGION_2__NEXT_MASK) >> RDMA_REGION_2__NEXT_LSB)
+#define RDMA_REGION_2__NEXT_SET(x)               (((x) << RDMA_REGION_2__NEXT_LSB) & RDMA_REGION_2__NEXT_MASK)
+
+#define RDMA_REGION_3__ADDRESS                   0x0000002c
+#define RDMA_REGION_3__OFFSET                    0x0000002c
+#define RDMA_REGION_3__ADDR_MSB                  31
+#define RDMA_REGION_3__ADDR_LSB                  13
+#define RDMA_REGION_3__ADDR_MASK                 0xffffe000
+#define RDMA_REGION_3__ADDR_GET(x)               (((x) & RDMA_REGION_3__ADDR_MASK) >> RDMA_REGION_3__ADDR_LSB)
+#define RDMA_REGION_3__ADDR_SET(x)               (((x) << RDMA_REGION_3__ADDR_LSB) & RDMA_REGION_3__ADDR_MASK)
+#define RDMA_REGION_3__LENGTH_MSB                12
+#define RDMA_REGION_3__LENGTH_LSB                2
+#define RDMA_REGION_3__LENGTH_MASK               0x00001ffc
+#define RDMA_REGION_3__LENGTH_GET(x)             (((x) & RDMA_REGION_3__LENGTH_MASK) >> RDMA_REGION_3__LENGTH_LSB)
+#define RDMA_REGION_3__LENGTH_SET(x)             (((x) << RDMA_REGION_3__LENGTH_LSB) & RDMA_REGION_3__LENGTH_MASK)
+#define RDMA_REGION_3__INDI_MSB                  1
+#define RDMA_REGION_3__INDI_LSB                  1
+#define RDMA_REGION_3__INDI_MASK                 0x00000002
+#define RDMA_REGION_3__INDI_GET(x)               (((x) & RDMA_REGION_3__INDI_MASK) >> RDMA_REGION_3__INDI_LSB)
+#define RDMA_REGION_3__INDI_SET(x)               (((x) << RDMA_REGION_3__INDI_LSB) & RDMA_REGION_3__INDI_MASK)
+#define RDMA_REGION_3__NEXT_MSB                  0
+#define RDMA_REGION_3__NEXT_LSB                  0
+#define RDMA_REGION_3__NEXT_MASK                 0x00000001
+#define RDMA_REGION_3__NEXT_GET(x)               (((x) & RDMA_REGION_3__NEXT_MASK) >> RDMA_REGION_3__NEXT_LSB)
+#define RDMA_REGION_3__NEXT_SET(x)               (((x) << RDMA_REGION_3__NEXT_LSB) & RDMA_REGION_3__NEXT_MASK)
+
+#define RDMA_REGION_4__ADDRESS                   0x00000030
+#define RDMA_REGION_4__OFFSET                    0x00000030
+#define RDMA_REGION_4__ADDR_MSB                  31
+#define RDMA_REGION_4__ADDR_LSB                  13
+#define RDMA_REGION_4__ADDR_MASK                 0xffffe000
+#define RDMA_REGION_4__ADDR_GET(x)               (((x) & RDMA_REGION_4__ADDR_MASK) >> RDMA_REGION_4__ADDR_LSB)
+#define RDMA_REGION_4__ADDR_SET(x)               (((x) << RDMA_REGION_4__ADDR_LSB) & RDMA_REGION_4__ADDR_MASK)
+#define RDMA_REGION_4__LENGTH_MSB                12
+#define RDMA_REGION_4__LENGTH_LSB                2
+#define RDMA_REGION_4__LENGTH_MASK               0x00001ffc
+#define RDMA_REGION_4__LENGTH_GET(x)             (((x) & RDMA_REGION_4__LENGTH_MASK) >> RDMA_REGION_4__LENGTH_LSB)
+#define RDMA_REGION_4__LENGTH_SET(x)             (((x) << RDMA_REGION_4__LENGTH_LSB) & RDMA_REGION_4__LENGTH_MASK)
+#define RDMA_REGION_4__INDI_MSB                  1
+#define RDMA_REGION_4__INDI_LSB                  1
+#define RDMA_REGION_4__INDI_MASK                 0x00000002
+#define RDMA_REGION_4__INDI_GET(x)               (((x) & RDMA_REGION_4__INDI_MASK) >> RDMA_REGION_4__INDI_LSB)
+#define RDMA_REGION_4__INDI_SET(x)               (((x) << RDMA_REGION_4__INDI_LSB) & RDMA_REGION_4__INDI_MASK)
+#define RDMA_REGION_4__NEXT_MSB                  0
+#define RDMA_REGION_4__NEXT_LSB                  0
+#define RDMA_REGION_4__NEXT_MASK                 0x00000001
+#define RDMA_REGION_4__NEXT_GET(x)               (((x) & RDMA_REGION_4__NEXT_MASK) >> RDMA_REGION_4__NEXT_LSB)
+#define RDMA_REGION_4__NEXT_SET(x)               (((x) << RDMA_REGION_4__NEXT_LSB) & RDMA_REGION_4__NEXT_MASK)
+
+#define RDMA_REGION_5__ADDRESS                   0x00000034
+#define RDMA_REGION_5__OFFSET                    0x00000034
+#define RDMA_REGION_5__ADDR_MSB                  31
+#define RDMA_REGION_5__ADDR_LSB                  13
+#define RDMA_REGION_5__ADDR_MASK                 0xffffe000
+#define RDMA_REGION_5__ADDR_GET(x)               (((x) & RDMA_REGION_5__ADDR_MASK) >> RDMA_REGION_5__ADDR_LSB)
+#define RDMA_REGION_5__ADDR_SET(x)               (((x) << RDMA_REGION_5__ADDR_LSB) & RDMA_REGION_5__ADDR_MASK)
+#define RDMA_REGION_5__LENGTH_MSB                12
+#define RDMA_REGION_5__LENGTH_LSB                2
+#define RDMA_REGION_5__LENGTH_MASK               0x00001ffc
+#define RDMA_REGION_5__LENGTH_GET(x)             (((x) & RDMA_REGION_5__LENGTH_MASK) >> RDMA_REGION_5__LENGTH_LSB)
+#define RDMA_REGION_5__LENGTH_SET(x)             (((x) << RDMA_REGION_5__LENGTH_LSB) & RDMA_REGION_5__LENGTH_MASK)
+#define RDMA_REGION_5__INDI_MSB                  1
+#define RDMA_REGION_5__INDI_LSB                  1
+#define RDMA_REGION_5__INDI_MASK                 0x00000002
+#define RDMA_REGION_5__INDI_GET(x)               (((x) & RDMA_REGION_5__INDI_MASK) >> RDMA_REGION_5__INDI_LSB)
+#define RDMA_REGION_5__INDI_SET(x)               (((x) << RDMA_REGION_5__INDI_LSB) & RDMA_REGION_5__INDI_MASK)
+#define RDMA_REGION_5__NEXT_MSB                  0
+#define RDMA_REGION_5__NEXT_LSB                  0
+#define RDMA_REGION_5__NEXT_MASK                 0x00000001
+#define RDMA_REGION_5__NEXT_GET(x)               (((x) & RDMA_REGION_5__NEXT_MASK) >> RDMA_REGION_5__NEXT_LSB)
+#define RDMA_REGION_5__NEXT_SET(x)               (((x) << RDMA_REGION_5__NEXT_LSB) & RDMA_REGION_5__NEXT_MASK)
+
+#define RDMA_REGION_6__ADDRESS                   0x00000038
+#define RDMA_REGION_6__OFFSET                    0x00000038
+#define RDMA_REGION_6__ADDR_MSB                  31
+#define RDMA_REGION_6__ADDR_LSB                  13
+#define RDMA_REGION_6__ADDR_MASK                 0xffffe000
+#define RDMA_REGION_6__ADDR_GET(x)               (((x) & RDMA_REGION_6__ADDR_MASK) >> RDMA_REGION_6__ADDR_LSB)
+#define RDMA_REGION_6__ADDR_SET(x)               (((x) << RDMA_REGION_6__ADDR_LSB) & RDMA_REGION_6__ADDR_MASK)
+#define RDMA_REGION_6__LENGTH_MSB                12
+#define RDMA_REGION_6__LENGTH_LSB                2
+#define RDMA_REGION_6__LENGTH_MASK               0x00001ffc
+#define RDMA_REGION_6__LENGTH_GET(x)             (((x) & RDMA_REGION_6__LENGTH_MASK) >> RDMA_REGION_6__LENGTH_LSB)
+#define RDMA_REGION_6__LENGTH_SET(x)             (((x) << RDMA_REGION_6__LENGTH_LSB) & RDMA_REGION_6__LENGTH_MASK)
+#define RDMA_REGION_6__INDI_MSB                  1
+#define RDMA_REGION_6__INDI_LSB                  1
+#define RDMA_REGION_6__INDI_MASK                 0x00000002
+#define RDMA_REGION_6__INDI_GET(x)               (((x) & RDMA_REGION_6__INDI_MASK) >> RDMA_REGION_6__INDI_LSB)
+#define RDMA_REGION_6__INDI_SET(x)               (((x) << RDMA_REGION_6__INDI_LSB) & RDMA_REGION_6__INDI_MASK)
+#define RDMA_REGION_6__NEXT_MSB                  0
+#define RDMA_REGION_6__NEXT_LSB                  0
+#define RDMA_REGION_6__NEXT_MASK                 0x00000001
+#define RDMA_REGION_6__NEXT_GET(x)               (((x) & RDMA_REGION_6__NEXT_MASK) >> RDMA_REGION_6__NEXT_LSB)
+#define RDMA_REGION_6__NEXT_SET(x)               (((x) << RDMA_REGION_6__NEXT_LSB) & RDMA_REGION_6__NEXT_MASK)
+
+#define RDMA_REGION_7__ADDRESS                   0x0000003c
+#define RDMA_REGION_7__OFFSET                    0x0000003c
+#define RDMA_REGION_7__ADDR_MSB                  31
+#define RDMA_REGION_7__ADDR_LSB                  13
+#define RDMA_REGION_7__ADDR_MASK                 0xffffe000
+#define RDMA_REGION_7__ADDR_GET(x)               (((x) & RDMA_REGION_7__ADDR_MASK) >> RDMA_REGION_7__ADDR_LSB)
+#define RDMA_REGION_7__ADDR_SET(x)               (((x) << RDMA_REGION_7__ADDR_LSB) & RDMA_REGION_7__ADDR_MASK)
+#define RDMA_REGION_7__LENGTH_MSB                12
+#define RDMA_REGION_7__LENGTH_LSB                2
+#define RDMA_REGION_7__LENGTH_MASK               0x00001ffc
+#define RDMA_REGION_7__LENGTH_GET(x)             (((x) & RDMA_REGION_7__LENGTH_MASK) >> RDMA_REGION_7__LENGTH_LSB)
+#define RDMA_REGION_7__LENGTH_SET(x)             (((x) << RDMA_REGION_7__LENGTH_LSB) & RDMA_REGION_7__LENGTH_MASK)
+#define RDMA_REGION_7__INDI_MSB                  1
+#define RDMA_REGION_7__INDI_LSB                  1
+#define RDMA_REGION_7__INDI_MASK                 0x00000002
+#define RDMA_REGION_7__INDI_GET(x)               (((x) & RDMA_REGION_7__INDI_MASK) >> RDMA_REGION_7__INDI_LSB)
+#define RDMA_REGION_7__INDI_SET(x)               (((x) << RDMA_REGION_7__INDI_LSB) & RDMA_REGION_7__INDI_MASK)
+#define RDMA_REGION_7__NEXT_MSB                  0
+#define RDMA_REGION_7__NEXT_LSB                  0
+#define RDMA_REGION_7__NEXT_MASK                 0x00000001
+#define RDMA_REGION_7__NEXT_GET(x)               (((x) & RDMA_REGION_7__NEXT_MASK) >> RDMA_REGION_7__NEXT_LSB)
+#define RDMA_REGION_7__NEXT_SET(x)               (((x) << RDMA_REGION_7__NEXT_LSB) & RDMA_REGION_7__NEXT_MASK)
+
+#define RDMA_REGION_8__ADDRESS                   0x00000040
+#define RDMA_REGION_8__OFFSET                    0x00000040
+#define RDMA_REGION_8__ADDR_MSB                  31
+#define RDMA_REGION_8__ADDR_LSB                  13
+#define RDMA_REGION_8__ADDR_MASK                 0xffffe000
+#define RDMA_REGION_8__ADDR_GET(x)               (((x) & RDMA_REGION_8__ADDR_MASK) >> RDMA_REGION_8__ADDR_LSB)
+#define RDMA_REGION_8__ADDR_SET(x)               (((x) << RDMA_REGION_8__ADDR_LSB) & RDMA_REGION_8__ADDR_MASK)
+#define RDMA_REGION_8__LENGTH_MSB                12
+#define RDMA_REGION_8__LENGTH_LSB                2
+#define RDMA_REGION_8__LENGTH_MASK               0x00001ffc
+#define RDMA_REGION_8__LENGTH_GET(x)             (((x) & RDMA_REGION_8__LENGTH_MASK) >> RDMA_REGION_8__LENGTH_LSB)
+#define RDMA_REGION_8__LENGTH_SET(x)             (((x) << RDMA_REGION_8__LENGTH_LSB) & RDMA_REGION_8__LENGTH_MASK)
+#define RDMA_REGION_8__INDI_MSB                  1
+#define RDMA_REGION_8__INDI_LSB                  1
+#define RDMA_REGION_8__INDI_MASK                 0x00000002
+#define RDMA_REGION_8__INDI_GET(x)               (((x) & RDMA_REGION_8__INDI_MASK) >> RDMA_REGION_8__INDI_LSB)
+#define RDMA_REGION_8__INDI_SET(x)               (((x) << RDMA_REGION_8__INDI_LSB) & RDMA_REGION_8__INDI_MASK)
+#define RDMA_REGION_8__NEXT_MSB                  0
+#define RDMA_REGION_8__NEXT_LSB                  0
+#define RDMA_REGION_8__NEXT_MASK                 0x00000001
+#define RDMA_REGION_8__NEXT_GET(x)               (((x) & RDMA_REGION_8__NEXT_MASK) >> RDMA_REGION_8__NEXT_LSB)
+#define RDMA_REGION_8__NEXT_SET(x)               (((x) << RDMA_REGION_8__NEXT_LSB) & RDMA_REGION_8__NEXT_MASK)
+
+#define RDMA_REGION_9__ADDRESS                   0x00000044
+#define RDMA_REGION_9__OFFSET                    0x00000044
+#define RDMA_REGION_9__ADDR_MSB                  31
+#define RDMA_REGION_9__ADDR_LSB                  13
+#define RDMA_REGION_9__ADDR_MASK                 0xffffe000
+#define RDMA_REGION_9__ADDR_GET(x)               (((x) & RDMA_REGION_9__ADDR_MASK) >> RDMA_REGION_9__ADDR_LSB)
+#define RDMA_REGION_9__ADDR_SET(x)               (((x) << RDMA_REGION_9__ADDR_LSB) & RDMA_REGION_9__ADDR_MASK)
+#define RDMA_REGION_9__LENGTH_MSB                12
+#define RDMA_REGION_9__LENGTH_LSB                2
+#define RDMA_REGION_9__LENGTH_MASK               0x00001ffc
+#define RDMA_REGION_9__LENGTH_GET(x)             (((x) & RDMA_REGION_9__LENGTH_MASK) >> RDMA_REGION_9__LENGTH_LSB)
+#define RDMA_REGION_9__LENGTH_SET(x)             (((x) << RDMA_REGION_9__LENGTH_LSB) & RDMA_REGION_9__LENGTH_MASK)
+#define RDMA_REGION_9__INDI_MSB                  1
+#define RDMA_REGION_9__INDI_LSB                  1
+#define RDMA_REGION_9__INDI_MASK                 0x00000002
+#define RDMA_REGION_9__INDI_GET(x)               (((x) & RDMA_REGION_9__INDI_MASK) >> RDMA_REGION_9__INDI_LSB)
+#define RDMA_REGION_9__INDI_SET(x)               (((x) << RDMA_REGION_9__INDI_LSB) & RDMA_REGION_9__INDI_MASK)
+#define RDMA_REGION_9__NEXT_MSB                  0
+#define RDMA_REGION_9__NEXT_LSB                  0
+#define RDMA_REGION_9__NEXT_MASK                 0x00000001
+#define RDMA_REGION_9__NEXT_GET(x)               (((x) & RDMA_REGION_9__NEXT_MASK) >> RDMA_REGION_9__NEXT_LSB)
+#define RDMA_REGION_9__NEXT_SET(x)               (((x) << RDMA_REGION_9__NEXT_LSB) & RDMA_REGION_9__NEXT_MASK)
+
+#define RDMA_REGION_10__ADDRESS                  0x00000048
+#define RDMA_REGION_10__OFFSET                   0x00000048
+#define RDMA_REGION_10__ADDR_MSB                 31
+#define RDMA_REGION_10__ADDR_LSB                 13
+#define RDMA_REGION_10__ADDR_MASK                0xffffe000
+#define RDMA_REGION_10__ADDR_GET(x)              (((x) & RDMA_REGION_10__ADDR_MASK) >> RDMA_REGION_10__ADDR_LSB)
+#define RDMA_REGION_10__ADDR_SET(x)              (((x) << RDMA_REGION_10__ADDR_LSB) & RDMA_REGION_10__ADDR_MASK)
+#define RDMA_REGION_10__LENGTH_MSB               12
+#define RDMA_REGION_10__LENGTH_LSB               2
+#define RDMA_REGION_10__LENGTH_MASK              0x00001ffc
+#define RDMA_REGION_10__LENGTH_GET(x)            (((x) & RDMA_REGION_10__LENGTH_MASK) >> RDMA_REGION_10__LENGTH_LSB)
+#define RDMA_REGION_10__LENGTH_SET(x)            (((x) << RDMA_REGION_10__LENGTH_LSB) & RDMA_REGION_10__LENGTH_MASK)
+#define RDMA_REGION_10__INDI_MSB                 1
+#define RDMA_REGION_10__INDI_LSB                 1
+#define RDMA_REGION_10__INDI_MASK                0x00000002
+#define RDMA_REGION_10__INDI_GET(x)              (((x) & RDMA_REGION_10__INDI_MASK) >> RDMA_REGION_10__INDI_LSB)
+#define RDMA_REGION_10__INDI_SET(x)              (((x) << RDMA_REGION_10__INDI_LSB) & RDMA_REGION_10__INDI_MASK)
+#define RDMA_REGION_10__NEXT_MSB                 0
+#define RDMA_REGION_10__NEXT_LSB                 0
+#define RDMA_REGION_10__NEXT_MASK                0x00000001
+#define RDMA_REGION_10__NEXT_GET(x)              (((x) & RDMA_REGION_10__NEXT_MASK) >> RDMA_REGION_10__NEXT_LSB)
+#define RDMA_REGION_10__NEXT_SET(x)              (((x) << RDMA_REGION_10__NEXT_LSB) & RDMA_REGION_10__NEXT_MASK)
+
+#define RDMA_REGION_11__ADDRESS                  0x0000004c
+#define RDMA_REGION_11__OFFSET                   0x0000004c
+#define RDMA_REGION_11__ADDR_MSB                 31
+#define RDMA_REGION_11__ADDR_LSB                 13
+#define RDMA_REGION_11__ADDR_MASK                0xffffe000
+#define RDMA_REGION_11__ADDR_GET(x)              (((x) & RDMA_REGION_11__ADDR_MASK) >> RDMA_REGION_11__ADDR_LSB)
+#define RDMA_REGION_11__ADDR_SET(x)              (((x) << RDMA_REGION_11__ADDR_LSB) & RDMA_REGION_11__ADDR_MASK)
+#define RDMA_REGION_11__LENGTH_MSB               12
+#define RDMA_REGION_11__LENGTH_LSB               2
+#define RDMA_REGION_11__LENGTH_MASK              0x00001ffc
+#define RDMA_REGION_11__LENGTH_GET(x)            (((x) & RDMA_REGION_11__LENGTH_MASK) >> RDMA_REGION_11__LENGTH_LSB)
+#define RDMA_REGION_11__LENGTH_SET(x)            (((x) << RDMA_REGION_11__LENGTH_LSB) & RDMA_REGION_11__LENGTH_MASK)
+#define RDMA_REGION_11__INDI_MSB                 1
+#define RDMA_REGION_11__INDI_LSB                 1
+#define RDMA_REGION_11__INDI_MASK                0x00000002
+#define RDMA_REGION_11__INDI_GET(x)              (((x) & RDMA_REGION_11__INDI_MASK) >> RDMA_REGION_11__INDI_LSB)
+#define RDMA_REGION_11__INDI_SET(x)              (((x) << RDMA_REGION_11__INDI_LSB) & RDMA_REGION_11__INDI_MASK)
+#define RDMA_REGION_11__NEXT_MSB                 0
+#define RDMA_REGION_11__NEXT_LSB                 0
+#define RDMA_REGION_11__NEXT_MASK                0x00000001
+#define RDMA_REGION_11__NEXT_GET(x)              (((x) & RDMA_REGION_11__NEXT_MASK) >> RDMA_REGION_11__NEXT_LSB)
+#define RDMA_REGION_11__NEXT_SET(x)              (((x) << RDMA_REGION_11__NEXT_LSB) & RDMA_REGION_11__NEXT_MASK)
+
+#define RDMA_REGION_12__ADDRESS                  0x00000050
+#define RDMA_REGION_12__OFFSET                   0x00000050
+#define RDMA_REGION_12__ADDR_MSB                 31
+#define RDMA_REGION_12__ADDR_LSB                 13
+#define RDMA_REGION_12__ADDR_MASK                0xffffe000
+#define RDMA_REGION_12__ADDR_GET(x)              (((x) & RDMA_REGION_12__ADDR_MASK) >> RDMA_REGION_12__ADDR_LSB)
+#define RDMA_REGION_12__ADDR_SET(x)              (((x) << RDMA_REGION_12__ADDR_LSB) & RDMA_REGION_12__ADDR_MASK)
+#define RDMA_REGION_12__LENGTH_MSB               12
+#define RDMA_REGION_12__LENGTH_LSB               2
+#define RDMA_REGION_12__LENGTH_MASK              0x00001ffc
+#define RDMA_REGION_12__LENGTH_GET(x)            (((x) & RDMA_REGION_12__LENGTH_MASK) >> RDMA_REGION_12__LENGTH_LSB)
+#define RDMA_REGION_12__LENGTH_SET(x)            (((x) << RDMA_REGION_12__LENGTH_LSB) & RDMA_REGION_12__LENGTH_MASK)
+#define RDMA_REGION_12__INDI_MSB                 1
+#define RDMA_REGION_12__INDI_LSB                 1
+#define RDMA_REGION_12__INDI_MASK                0x00000002
+#define RDMA_REGION_12__INDI_GET(x)              (((x) & RDMA_REGION_12__INDI_MASK) >> RDMA_REGION_12__INDI_LSB)
+#define RDMA_REGION_12__INDI_SET(x)              (((x) << RDMA_REGION_12__INDI_LSB) & RDMA_REGION_12__INDI_MASK)
+#define RDMA_REGION_12__NEXT_MSB                 0
+#define RDMA_REGION_12__NEXT_LSB                 0
+#define RDMA_REGION_12__NEXT_MASK                0x00000001
+#define RDMA_REGION_12__NEXT_GET(x)              (((x) & RDMA_REGION_12__NEXT_MASK) >> RDMA_REGION_12__NEXT_LSB)
+#define RDMA_REGION_12__NEXT_SET(x)              (((x) << RDMA_REGION_12__NEXT_LSB) & RDMA_REGION_12__NEXT_MASK)
+
+#define RDMA_REGION_13__ADDRESS                  0x00000054
+#define RDMA_REGION_13__OFFSET                   0x00000054
+#define RDMA_REGION_13__ADDR_MSB                 31
+#define RDMA_REGION_13__ADDR_LSB                 13
+#define RDMA_REGION_13__ADDR_MASK                0xffffe000
+#define RDMA_REGION_13__ADDR_GET(x)              (((x) & RDMA_REGION_13__ADDR_MASK) >> RDMA_REGION_13__ADDR_LSB)
+#define RDMA_REGION_13__ADDR_SET(x)              (((x) << RDMA_REGION_13__ADDR_LSB) & RDMA_REGION_13__ADDR_MASK)
+#define RDMA_REGION_13__LENGTH_MSB               12
+#define RDMA_REGION_13__LENGTH_LSB               2
+#define RDMA_REGION_13__LENGTH_MASK              0x00001ffc
+#define RDMA_REGION_13__LENGTH_GET(x)            (((x) & RDMA_REGION_13__LENGTH_MASK) >> RDMA_REGION_13__LENGTH_LSB)
+#define RDMA_REGION_13__LENGTH_SET(x)            (((x) << RDMA_REGION_13__LENGTH_LSB) & RDMA_REGION_13__LENGTH_MASK)
+#define RDMA_REGION_13__INDI_MSB                 1
+#define RDMA_REGION_13__INDI_LSB                 1
+#define RDMA_REGION_13__INDI_MASK                0x00000002
+#define RDMA_REGION_13__INDI_GET(x)              (((x) & RDMA_REGION_13__INDI_MASK) >> RDMA_REGION_13__INDI_LSB)
+#define RDMA_REGION_13__INDI_SET(x)              (((x) << RDMA_REGION_13__INDI_LSB) & RDMA_REGION_13__INDI_MASK)
+#define RDMA_REGION_13__NEXT_MSB                 0
+#define RDMA_REGION_13__NEXT_LSB                 0
+#define RDMA_REGION_13__NEXT_MASK                0x00000001
+#define RDMA_REGION_13__NEXT_GET(x)              (((x) & RDMA_REGION_13__NEXT_MASK) >> RDMA_REGION_13__NEXT_LSB)
+#define RDMA_REGION_13__NEXT_SET(x)              (((x) << RDMA_REGION_13__NEXT_LSB) & RDMA_REGION_13__NEXT_MASK)
+
+#define RDMA_REGION_14__ADDRESS                  0x00000058
+#define RDMA_REGION_14__OFFSET                   0x00000058
+#define RDMA_REGION_14__ADDR_MSB                 31
+#define RDMA_REGION_14__ADDR_LSB                 13
+#define RDMA_REGION_14__ADDR_MASK                0xffffe000
+#define RDMA_REGION_14__ADDR_GET(x)              (((x) & RDMA_REGION_14__ADDR_MASK) >> RDMA_REGION_14__ADDR_LSB)
+#define RDMA_REGION_14__ADDR_SET(x)              (((x) << RDMA_REGION_14__ADDR_LSB) & RDMA_REGION_14__ADDR_MASK)
+#define RDMA_REGION_14__LENGTH_MSB               12
+#define RDMA_REGION_14__LENGTH_LSB               2
+#define RDMA_REGION_14__LENGTH_MASK              0x00001ffc
+#define RDMA_REGION_14__LENGTH_GET(x)            (((x) & RDMA_REGION_14__LENGTH_MASK) >> RDMA_REGION_14__LENGTH_LSB)
+#define RDMA_REGION_14__LENGTH_SET(x)            (((x) << RDMA_REGION_14__LENGTH_LSB) & RDMA_REGION_14__LENGTH_MASK)
+#define RDMA_REGION_14__INDI_MSB                 1
+#define RDMA_REGION_14__INDI_LSB                 1
+#define RDMA_REGION_14__INDI_MASK                0x00000002
+#define RDMA_REGION_14__INDI_GET(x)              (((x) & RDMA_REGION_14__INDI_MASK) >> RDMA_REGION_14__INDI_LSB)
+#define RDMA_REGION_14__INDI_SET(x)              (((x) << RDMA_REGION_14__INDI_LSB) & RDMA_REGION_14__INDI_MASK)
+#define RDMA_REGION_14__NEXT_MSB                 0
+#define RDMA_REGION_14__NEXT_LSB                 0
+#define RDMA_REGION_14__NEXT_MASK                0x00000001
+#define RDMA_REGION_14__NEXT_GET(x)              (((x) & RDMA_REGION_14__NEXT_MASK) >> RDMA_REGION_14__NEXT_LSB)
+#define RDMA_REGION_14__NEXT_SET(x)              (((x) << RDMA_REGION_14__NEXT_LSB) & RDMA_REGION_14__NEXT_MASK)
+
+#define RDMA_REGION_15__ADDRESS                  0x0000005c
+#define RDMA_REGION_15__OFFSET                   0x0000005c
+#define RDMA_REGION_15__ADDR_MSB                 31
+#define RDMA_REGION_15__ADDR_LSB                 13
+#define RDMA_REGION_15__ADDR_MASK                0xffffe000
+#define RDMA_REGION_15__ADDR_GET(x)              (((x) & RDMA_REGION_15__ADDR_MASK) >> RDMA_REGION_15__ADDR_LSB)
+#define RDMA_REGION_15__ADDR_SET(x)              (((x) << RDMA_REGION_15__ADDR_LSB) & RDMA_REGION_15__ADDR_MASK)
+#define RDMA_REGION_15__LENGTH_MSB               12
+#define RDMA_REGION_15__LENGTH_LSB               2
+#define RDMA_REGION_15__LENGTH_MASK              0x00001ffc
+#define RDMA_REGION_15__LENGTH_GET(x)            (((x) & RDMA_REGION_15__LENGTH_MASK) >> RDMA_REGION_15__LENGTH_LSB)
+#define RDMA_REGION_15__LENGTH_SET(x)            (((x) << RDMA_REGION_15__LENGTH_LSB) & RDMA_REGION_15__LENGTH_MASK)
+#define RDMA_REGION_15__INDI_MSB                 1
+#define RDMA_REGION_15__INDI_LSB                 1
+#define RDMA_REGION_15__INDI_MASK                0x00000002
+#define RDMA_REGION_15__INDI_GET(x)              (((x) & RDMA_REGION_15__INDI_MASK) >> RDMA_REGION_15__INDI_LSB)
+#define RDMA_REGION_15__INDI_SET(x)              (((x) << RDMA_REGION_15__INDI_LSB) & RDMA_REGION_15__INDI_MASK)
+#define RDMA_REGION_15__NEXT_MSB                 0
+#define RDMA_REGION_15__NEXT_LSB                 0
+#define RDMA_REGION_15__NEXT_MASK                0x00000001
+#define RDMA_REGION_15__NEXT_GET(x)              (((x) & RDMA_REGION_15__NEXT_MASK) >> RDMA_REGION_15__NEXT_LSB)
+#define RDMA_REGION_15__NEXT_SET(x)              (((x) << RDMA_REGION_15__NEXT_LSB) & RDMA_REGION_15__NEXT_MASK)
+
+#define DMA_STATUS_ADDRESS                       0x00000060
+#define DMA_STATUS_OFFSET                        0x00000060
+#define DMA_STATUS_ERROR_CODE_MSB                14
+#define DMA_STATUS_ERROR_CODE_LSB                4
+#define DMA_STATUS_ERROR_CODE_MASK               0x00007ff0
+#define DMA_STATUS_ERROR_CODE_GET(x)             (((x) & DMA_STATUS_ERROR_CODE_MASK) >> DMA_STATUS_ERROR_CODE_LSB)
+#define DMA_STATUS_ERROR_CODE_SET(x)             (((x) << DMA_STATUS_ERROR_CODE_LSB) & DMA_STATUS_ERROR_CODE_MASK)
+#define DMA_STATUS_ERROR_MSB                     3
+#define DMA_STATUS_ERROR_LSB                     3
+#define DMA_STATUS_ERROR_MASK                    0x00000008
+#define DMA_STATUS_ERROR_GET(x)                  (((x) & DMA_STATUS_ERROR_MASK) >> DMA_STATUS_ERROR_LSB)
+#define DMA_STATUS_ERROR_SET(x)                  (((x) << DMA_STATUS_ERROR_LSB) & DMA_STATUS_ERROR_MASK)
+#define DMA_STATUS_DONE_MSB                      2
+#define DMA_STATUS_DONE_LSB                      2
+#define DMA_STATUS_DONE_MASK                     0x00000004
+#define DMA_STATUS_DONE_GET(x)                   (((x) & DMA_STATUS_DONE_MASK) >> DMA_STATUS_DONE_LSB)
+#define DMA_STATUS_DONE_SET(x)                   (((x) << DMA_STATUS_DONE_LSB) & DMA_STATUS_DONE_MASK)
+#define DMA_STATUS_STOPPED_MSB                   1
+#define DMA_STATUS_STOPPED_LSB                   1
+#define DMA_STATUS_STOPPED_MASK                  0x00000002
+#define DMA_STATUS_STOPPED_GET(x)                (((x) & DMA_STATUS_STOPPED_MASK) >> DMA_STATUS_STOPPED_LSB)
+#define DMA_STATUS_STOPPED_SET(x)                (((x) << DMA_STATUS_STOPPED_LSB) & DMA_STATUS_STOPPED_MASK)
+#define DMA_STATUS_RUNNING_MSB                   0
+#define DMA_STATUS_RUNNING_LSB                   0
+#define DMA_STATUS_RUNNING_MASK                  0x00000001
+#define DMA_STATUS_RUNNING_GET(x)                (((x) & DMA_STATUS_RUNNING_MASK) >> DMA_STATUS_RUNNING_LSB)
+#define DMA_STATUS_RUNNING_SET(x)                (((x) << DMA_STATUS_RUNNING_LSB) & DMA_STATUS_RUNNING_MASK)
+
+#define DMA_INT_EN_ADDRESS                       0x00000064
+#define DMA_INT_EN_OFFSET                        0x00000064
+#define DMA_INT_EN_ERROR_ENA_MSB                 3
+#define DMA_INT_EN_ERROR_ENA_LSB                 3
+#define DMA_INT_EN_ERROR_ENA_MASK                0x00000008
+#define DMA_INT_EN_ERROR_ENA_GET(x)              (((x) & DMA_INT_EN_ERROR_ENA_MASK) >> DMA_INT_EN_ERROR_ENA_LSB)
+#define DMA_INT_EN_ERROR_ENA_SET(x)              (((x) << DMA_INT_EN_ERROR_ENA_LSB) & DMA_INT_EN_ERROR_ENA_MASK)
+#define DMA_INT_EN_DONE_ENA_MSB                  2
+#define DMA_INT_EN_DONE_ENA_LSB                  2
+#define DMA_INT_EN_DONE_ENA_MASK                 0x00000004
+#define DMA_INT_EN_DONE_ENA_GET(x)               (((x) & DMA_INT_EN_DONE_ENA_MASK) >> DMA_INT_EN_DONE_ENA_LSB)
+#define DMA_INT_EN_DONE_ENA_SET(x)               (((x) << DMA_INT_EN_DONE_ENA_LSB) & DMA_INT_EN_DONE_ENA_MASK)
+#define DMA_INT_EN_STOPPED_ENA_MSB               1
+#define DMA_INT_EN_STOPPED_ENA_LSB               1
+#define DMA_INT_EN_STOPPED_ENA_MASK              0x00000002
+#define DMA_INT_EN_STOPPED_ENA_GET(x)            (((x) & DMA_INT_EN_STOPPED_ENA_MASK) >> DMA_INT_EN_STOPPED_ENA_LSB)
+#define DMA_INT_EN_STOPPED_ENA_SET(x)            (((x) << DMA_INT_EN_STOPPED_ENA_LSB) & DMA_INT_EN_STOPPED_ENA_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct rdma_reg_reg_s {
+  volatile unsigned int dma_config;
+  volatile unsigned int dma_control;
+  volatile unsigned int dma_src;
+  volatile unsigned int dma_dest;
+  volatile unsigned int dma_length;
+  volatile unsigned int vmc_base;
+  volatile unsigned int indirect_reg;
+  volatile unsigned int indirect_return;
+  volatile unsigned int rdma_region_0_;
+  volatile unsigned int rdma_region_1_;
+  volatile unsigned int rdma_region_2_;
+  volatile unsigned int rdma_region_3_;
+  volatile unsigned int rdma_region_4_;
+  volatile unsigned int rdma_region_5_;
+  volatile unsigned int rdma_region_6_;
+  volatile unsigned int rdma_region_7_;
+  volatile unsigned int rdma_region_8_;
+  volatile unsigned int rdma_region_9_;
+  volatile unsigned int rdma_region_10_;
+  volatile unsigned int rdma_region_11_;
+  volatile unsigned int rdma_region_12_;
+  volatile unsigned int rdma_region_13_;
+  volatile unsigned int rdma_region_14_;
+  volatile unsigned int rdma_region_15_;
+  volatile unsigned int dma_status;
+  volatile unsigned int dma_int_en;
+} rdma_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _RDMA_REG_H_ */
diff --git a/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/rtc_reg.h b/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/rtc_reg.h
new file mode 100644
index 00000000000..0855de5f140
--- /dev/null
+++ b/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/rtc_reg.h
@@ -0,0 +1,975 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifdef WLAN_HEADERS
+
+#include "rtc_wlan_reg.h"
+
+
+#ifndef BT_HEADERS
+
+#define RESET_CONTROL_ADDRESS WLAN_RESET_CONTROL_ADDRESS
+#define RESET_CONTROL_OFFSET WLAN_RESET_CONTROL_OFFSET
+#define RESET_CONTROL_DEBUG_UART_RST_MSB WLAN_RESET_CONTROL_DEBUG_UART_RST_MSB
+#define RESET_CONTROL_DEBUG_UART_RST_LSB WLAN_RESET_CONTROL_DEBUG_UART_RST_LSB
+#define RESET_CONTROL_DEBUG_UART_RST_MASK WLAN_RESET_CONTROL_DEBUG_UART_RST_MASK
+#define RESET_CONTROL_DEBUG_UART_RST_GET(x) WLAN_RESET_CONTROL_DEBUG_UART_RST_GET(x)
+#define RESET_CONTROL_DEBUG_UART_RST_SET(x) WLAN_RESET_CONTROL_DEBUG_UART_RST_SET(x)
+#define RESET_CONTROL_BB_COLD_RST_MSB WLAN_RESET_CONTROL_BB_COLD_RST_MSB
+#define RESET_CONTROL_BB_COLD_RST_LSB WLAN_RESET_CONTROL_BB_COLD_RST_LSB
+#define RESET_CONTROL_BB_COLD_RST_MASK WLAN_RESET_CONTROL_BB_COLD_RST_MASK
+#define RESET_CONTROL_BB_COLD_RST_GET(x) WLAN_RESET_CONTROL_BB_COLD_RST_GET(x)
+#define RESET_CONTROL_BB_COLD_RST_SET(x) WLAN_RESET_CONTROL_BB_COLD_RST_SET(x)
+#define RESET_CONTROL_BB_WARM_RST_MSB WLAN_RESET_CONTROL_BB_WARM_RST_MSB
+#define RESET_CONTROL_BB_WARM_RST_LSB WLAN_RESET_CONTROL_BB_WARM_RST_LSB
+#define RESET_CONTROL_BB_WARM_RST_MASK WLAN_RESET_CONTROL_BB_WARM_RST_MASK
+#define RESET_CONTROL_BB_WARM_RST_GET(x) WLAN_RESET_CONTROL_BB_WARM_RST_GET(x)
+#define RESET_CONTROL_BB_WARM_RST_SET(x) WLAN_RESET_CONTROL_BB_WARM_RST_SET(x)
+#define RESET_CONTROL_CPU_INIT_RESET_MSB WLAN_RESET_CONTROL_CPU_INIT_RESET_MSB
+#define RESET_CONTROL_CPU_INIT_RESET_LSB WLAN_RESET_CONTROL_CPU_INIT_RESET_LSB
+#define RESET_CONTROL_CPU_INIT_RESET_MASK WLAN_RESET_CONTROL_CPU_INIT_RESET_MASK
+#define RESET_CONTROL_CPU_INIT_RESET_GET(x) WLAN_RESET_CONTROL_CPU_INIT_RESET_GET(x)
+#define RESET_CONTROL_CPU_INIT_RESET_SET(x) WLAN_RESET_CONTROL_CPU_INIT_RESET_SET(x)
+#define RESET_CONTROL_VMC_REMAP_RESET_MSB WLAN_RESET_CONTROL_VMC_REMAP_RESET_MSB
+#define RESET_CONTROL_VMC_REMAP_RESET_LSB WLAN_RESET_CONTROL_VMC_REMAP_RESET_LSB
+#define RESET_CONTROL_VMC_REMAP_RESET_MASK WLAN_RESET_CONTROL_VMC_REMAP_RESET_MASK
+#define RESET_CONTROL_VMC_REMAP_RESET_GET(x) WLAN_RESET_CONTROL_VMC_REMAP_RESET_GET(x)
+#define RESET_CONTROL_VMC_REMAP_RESET_SET(x) WLAN_RESET_CONTROL_VMC_REMAP_RESET_SET(x)
+#define RESET_CONTROL_RST_OUT_MSB WLAN_RESET_CONTROL_RST_OUT_MSB
+#define RESET_CONTROL_RST_OUT_LSB WLAN_RESET_CONTROL_RST_OUT_LSB
+#define RESET_CONTROL_RST_OUT_MASK WLAN_RESET_CONTROL_RST_OUT_MASK
+#define RESET_CONTROL_RST_OUT_GET(x) WLAN_RESET_CONTROL_RST_OUT_GET(x)
+#define RESET_CONTROL_RST_OUT_SET(x) WLAN_RESET_CONTROL_RST_OUT_SET(x)
+#define RESET_CONTROL_COLD_RST_MSB WLAN_RESET_CONTROL_COLD_RST_MSB
+#define RESET_CONTROL_COLD_RST_LSB WLAN_RESET_CONTROL_COLD_RST_LSB
+#define RESET_CONTROL_COLD_RST_MASK WLAN_RESET_CONTROL_COLD_RST_MASK
+#define RESET_CONTROL_COLD_RST_GET(x) WLAN_RESET_CONTROL_COLD_RST_GET(x)
+#define RESET_CONTROL_COLD_RST_SET(x) WLAN_RESET_CONTROL_COLD_RST_SET(x)
+#define RESET_CONTROL_WARM_RST_MSB WLAN_RESET_CONTROL_WARM_RST_MSB
+#define RESET_CONTROL_WARM_RST_LSB WLAN_RESET_CONTROL_WARM_RST_LSB
+#define RESET_CONTROL_WARM_RST_MASK WLAN_RESET_CONTROL_WARM_RST_MASK
+#define RESET_CONTROL_WARM_RST_GET(x) WLAN_RESET_CONTROL_WARM_RST_GET(x)
+#define RESET_CONTROL_WARM_RST_SET(x) WLAN_RESET_CONTROL_WARM_RST_SET(x)
+#define RESET_CONTROL_CPU_WARM_RST_MSB WLAN_RESET_CONTROL_CPU_WARM_RST_MSB
+#define RESET_CONTROL_CPU_WARM_RST_LSB WLAN_RESET_CONTROL_CPU_WARM_RST_LSB
+#define RESET_CONTROL_CPU_WARM_RST_MASK WLAN_RESET_CONTROL_CPU_WARM_RST_MASK
+#define RESET_CONTROL_CPU_WARM_RST_GET(x) WLAN_RESET_CONTROL_CPU_WARM_RST_GET(x)
+#define RESET_CONTROL_CPU_WARM_RST_SET(x) WLAN_RESET_CONTROL_CPU_WARM_RST_SET(x)
+#define RESET_CONTROL_MAC_COLD_RST_MSB WLAN_RESET_CONTROL_MAC_COLD_RST_MSB
+#define RESET_CONTROL_MAC_COLD_RST_LSB WLAN_RESET_CONTROL_MAC_COLD_RST_LSB
+#define RESET_CONTROL_MAC_COLD_RST_MASK WLAN_RESET_CONTROL_MAC_COLD_RST_MASK
+#define RESET_CONTROL_MAC_COLD_RST_GET(x) WLAN_RESET_CONTROL_MAC_COLD_RST_GET(x)
+#define RESET_CONTROL_MAC_COLD_RST_SET(x) WLAN_RESET_CONTROL_MAC_COLD_RST_SET(x)
+#define RESET_CONTROL_MAC_WARM_RST_MSB WLAN_RESET_CONTROL_MAC_WARM_RST_MSB
+#define RESET_CONTROL_MAC_WARM_RST_LSB WLAN_RESET_CONTROL_MAC_WARM_RST_LSB
+#define RESET_CONTROL_MAC_WARM_RST_MASK WLAN_RESET_CONTROL_MAC_WARM_RST_MASK
+#define RESET_CONTROL_MAC_WARM_RST_GET(x) WLAN_RESET_CONTROL_MAC_WARM_RST_GET(x)
+#define RESET_CONTROL_MAC_WARM_RST_SET(x) WLAN_RESET_CONTROL_MAC_WARM_RST_SET(x)
+#define RESET_CONTROL_MBOX_RST_MSB WLAN_RESET_CONTROL_MBOX_RST_MSB
+#define RESET_CONTROL_MBOX_RST_LSB WLAN_RESET_CONTROL_MBOX_RST_LSB
+#define RESET_CONTROL_MBOX_RST_MASK WLAN_RESET_CONTROL_MBOX_RST_MASK
+#define RESET_CONTROL_MBOX_RST_GET(x) WLAN_RESET_CONTROL_MBOX_RST_GET(x)
+#define RESET_CONTROL_MBOX_RST_SET(x) WLAN_RESET_CONTROL_MBOX_RST_SET(x)
+#define RESET_CONTROL_UART_RST_MSB WLAN_RESET_CONTROL_UART_RST_MSB
+#define RESET_CONTROL_UART_RST_LSB WLAN_RESET_CONTROL_UART_RST_LSB
+#define RESET_CONTROL_UART_RST_MASK WLAN_RESET_CONTROL_UART_RST_MASK
+#define RESET_CONTROL_UART_RST_GET(x) WLAN_RESET_CONTROL_UART_RST_GET(x)
+#define RESET_CONTROL_UART_RST_SET(x) WLAN_RESET_CONTROL_UART_RST_SET(x)
+#define RESET_CONTROL_SI0_RST_MSB WLAN_RESET_CONTROL_SI0_RST_MSB
+#define RESET_CONTROL_SI0_RST_LSB WLAN_RESET_CONTROL_SI0_RST_LSB
+#define RESET_CONTROL_SI0_RST_MASK WLAN_RESET_CONTROL_SI0_RST_MASK
+#define RESET_CONTROL_SI0_RST_GET(x) WLAN_RESET_CONTROL_SI0_RST_GET(x)
+#define RESET_CONTROL_SI0_RST_SET(x) WLAN_RESET_CONTROL_SI0_RST_SET(x)
+#define XTAL_CONTROL_ADDRESS WLAN_XTAL_CONTROL_ADDRESS
+#define XTAL_CONTROL_OFFSET WLAN_XTAL_CONTROL_OFFSET
+#define XTAL_CONTROL_TCXO_MSB WLAN_XTAL_CONTROL_TCXO_MSB
+#define XTAL_CONTROL_TCXO_LSB WLAN_XTAL_CONTROL_TCXO_LSB
+#define XTAL_CONTROL_TCXO_MASK WLAN_XTAL_CONTROL_TCXO_MASK
+#define XTAL_CONTROL_TCXO_GET(x) WLAN_XTAL_CONTROL_TCXO_GET(x)
+#define XTAL_CONTROL_TCXO_SET(x) WLAN_XTAL_CONTROL_TCXO_SET(x)
+#define TCXO_DETECT_ADDRESS WLAN_TCXO_DETECT_ADDRESS
+#define TCXO_DETECT_OFFSET WLAN_TCXO_DETECT_OFFSET
+#define TCXO_DETECT_PRESENT_MSB WLAN_TCXO_DETECT_PRESENT_MSB
+#define TCXO_DETECT_PRESENT_LSB WLAN_TCXO_DETECT_PRESENT_LSB
+#define TCXO_DETECT_PRESENT_MASK WLAN_TCXO_DETECT_PRESENT_MASK
+#define TCXO_DETECT_PRESENT_GET(x) WLAN_TCXO_DETECT_PRESENT_GET(x)
+#define TCXO_DETECT_PRESENT_SET(x) WLAN_TCXO_DETECT_PRESENT_SET(x)
+#define XTAL_TEST_ADDRESS WLAN_XTAL_TEST_ADDRESS
+#define XTAL_TEST_OFFSET WLAN_XTAL_TEST_OFFSET
+#define XTAL_TEST_NOTCXODET_MSB WLAN_XTAL_TEST_NOTCXODET_MSB
+#define XTAL_TEST_NOTCXODET_LSB WLAN_XTAL_TEST_NOTCXODET_LSB
+#define XTAL_TEST_NOTCXODET_MASK WLAN_XTAL_TEST_NOTCXODET_MASK
+#define XTAL_TEST_NOTCXODET_GET(x) WLAN_XTAL_TEST_NOTCXODET_GET(x)
+#define XTAL_TEST_NOTCXODET_SET(x) WLAN_XTAL_TEST_NOTCXODET_SET(x)
+#define QUADRATURE_ADDRESS WLAN_QUADRATURE_ADDRESS
+#define QUADRATURE_OFFSET WLAN_QUADRATURE_OFFSET
+#define QUADRATURE_ADC_MSB WLAN_QUADRATURE_ADC_MSB
+#define QUADRATURE_ADC_LSB WLAN_QUADRATURE_ADC_LSB
+#define QUADRATURE_ADC_MASK WLAN_QUADRATURE_ADC_MASK
+#define QUADRATURE_ADC_GET(x) WLAN_QUADRATURE_ADC_GET(x)
+#define QUADRATURE_ADC_SET(x) WLAN_QUADRATURE_ADC_SET(x)
+#define QUADRATURE_SEL_MSB WLAN_QUADRATURE_SEL_MSB
+#define QUADRATURE_SEL_LSB WLAN_QUADRATURE_SEL_LSB
+#define QUADRATURE_SEL_MASK WLAN_QUADRATURE_SEL_MASK
+#define QUADRATURE_SEL_GET(x) WLAN_QUADRATURE_SEL_GET(x)
+#define QUADRATURE_SEL_SET(x) WLAN_QUADRATURE_SEL_SET(x)
+#define QUADRATURE_DAC_MSB WLAN_QUADRATURE_DAC_MSB
+#define QUADRATURE_DAC_LSB WLAN_QUADRATURE_DAC_LSB
+#define QUADRATURE_DAC_MASK WLAN_QUADRATURE_DAC_MASK
+#define QUADRATURE_DAC_GET(x) WLAN_QUADRATURE_DAC_GET(x)
+#define QUADRATURE_DAC_SET(x) WLAN_QUADRATURE_DAC_SET(x)
+#define PLL_CONTROL_ADDRESS WLAN_PLL_CONTROL_ADDRESS
+#define PLL_CONTROL_OFFSET WLAN_PLL_CONTROL_OFFSET
+#define PLL_CONTROL_DIG_TEST_CLK_MSB WLAN_PLL_CONTROL_DIG_TEST_CLK_MSB
+#define PLL_CONTROL_DIG_TEST_CLK_LSB WLAN_PLL_CONTROL_DIG_TEST_CLK_LSB
+#define PLL_CONTROL_DIG_TEST_CLK_MASK WLAN_PLL_CONTROL_DIG_TEST_CLK_MASK
+#define PLL_CONTROL_DIG_TEST_CLK_GET(x) WLAN_PLL_CONTROL_DIG_TEST_CLK_GET(x)
+#define PLL_CONTROL_DIG_TEST_CLK_SET(x) WLAN_PLL_CONTROL_DIG_TEST_CLK_SET(x)
+#define PLL_CONTROL_MAC_OVERRIDE_MSB WLAN_PLL_CONTROL_MAC_OVERRIDE_MSB
+#define PLL_CONTROL_MAC_OVERRIDE_LSB WLAN_PLL_CONTROL_MAC_OVERRIDE_LSB
+#define PLL_CONTROL_MAC_OVERRIDE_MASK WLAN_PLL_CONTROL_MAC_OVERRIDE_MASK
+#define PLL_CONTROL_MAC_OVERRIDE_GET(x) WLAN_PLL_CONTROL_MAC_OVERRIDE_GET(x)
+#define PLL_CONTROL_MAC_OVERRIDE_SET(x) WLAN_PLL_CONTROL_MAC_OVERRIDE_SET(x)
+#define PLL_CONTROL_NOPWD_MSB WLAN_PLL_CONTROL_NOPWD_MSB
+#define PLL_CONTROL_NOPWD_LSB WLAN_PLL_CONTROL_NOPWD_LSB
+#define PLL_CONTROL_NOPWD_MASK WLAN_PLL_CONTROL_NOPWD_MASK
+#define PLL_CONTROL_NOPWD_GET(x) WLAN_PLL_CONTROL_NOPWD_GET(x)
+#define PLL_CONTROL_NOPWD_SET(x) WLAN_PLL_CONTROL_NOPWD_SET(x)
+#define PLL_CONTROL_UPDATING_MSB WLAN_PLL_CONTROL_UPDATING_MSB
+#define PLL_CONTROL_UPDATING_LSB WLAN_PLL_CONTROL_UPDATING_LSB
+#define PLL_CONTROL_UPDATING_MASK WLAN_PLL_CONTROL_UPDATING_MASK
+#define PLL_CONTROL_UPDATING_GET(x) WLAN_PLL_CONTROL_UPDATING_GET(x)
+#define PLL_CONTROL_UPDATING_SET(x) WLAN_PLL_CONTROL_UPDATING_SET(x)
+#define PLL_CONTROL_BYPASS_MSB WLAN_PLL_CONTROL_BYPASS_MSB
+#define PLL_CONTROL_BYPASS_LSB WLAN_PLL_CONTROL_BYPASS_LSB
+#define PLL_CONTROL_BYPASS_MASK WLAN_PLL_CONTROL_BYPASS_MASK
+#define PLL_CONTROL_BYPASS_GET(x) WLAN_PLL_CONTROL_BYPASS_GET(x)
+#define PLL_CONTROL_BYPASS_SET(x) WLAN_PLL_CONTROL_BYPASS_SET(x)
+#define PLL_CONTROL_REFDIV_MSB WLAN_PLL_CONTROL_REFDIV_MSB
+#define PLL_CONTROL_REFDIV_LSB WLAN_PLL_CONTROL_REFDIV_LSB
+#define PLL_CONTROL_REFDIV_MASK WLAN_PLL_CONTROL_REFDIV_MASK
+#define PLL_CONTROL_REFDIV_GET(x) WLAN_PLL_CONTROL_REFDIV_GET(x)
+#define PLL_CONTROL_REFDIV_SET(x) WLAN_PLL_CONTROL_REFDIV_SET(x)
+#define PLL_CONTROL_DIV_MSB WLAN_PLL_CONTROL_DIV_MSB
+#define PLL_CONTROL_DIV_LSB WLAN_PLL_CONTROL_DIV_LSB
+#define PLL_CONTROL_DIV_MASK WLAN_PLL_CONTROL_DIV_MASK
+#define PLL_CONTROL_DIV_GET(x) WLAN_PLL_CONTROL_DIV_GET(x)
+#define PLL_CONTROL_DIV_SET(x) WLAN_PLL_CONTROL_DIV_SET(x)
+#define PLL_SETTLE_ADDRESS WLAN_PLL_SETTLE_ADDRESS
+#define PLL_SETTLE_OFFSET WLAN_PLL_SETTLE_OFFSET
+#define PLL_SETTLE_TIME_MSB WLAN_PLL_SETTLE_TIME_MSB
+#define PLL_SETTLE_TIME_LSB WLAN_PLL_SETTLE_TIME_LSB
+#define PLL_SETTLE_TIME_MASK WLAN_PLL_SETTLE_TIME_MASK
+#define PLL_SETTLE_TIME_GET(x) WLAN_PLL_SETTLE_TIME_GET(x)
+#define PLL_SETTLE_TIME_SET(x) WLAN_PLL_SETTLE_TIME_SET(x)
+#define XTAL_SETTLE_ADDRESS WLAN_XTAL_SETTLE_ADDRESS
+#define XTAL_SETTLE_OFFSET WLAN_XTAL_SETTLE_OFFSET
+#define XTAL_SETTLE_TIME_MSB WLAN_XTAL_SETTLE_TIME_MSB
+#define XTAL_SETTLE_TIME_LSB WLAN_XTAL_SETTLE_TIME_LSB
+#define XTAL_SETTLE_TIME_MASK WLAN_XTAL_SETTLE_TIME_MASK
+#define XTAL_SETTLE_TIME_GET(x) WLAN_XTAL_SETTLE_TIME_GET(x)
+#define XTAL_SETTLE_TIME_SET(x) WLAN_XTAL_SETTLE_TIME_SET(x)
+#define CPU_CLOCK_ADDRESS WLAN_CPU_CLOCK_ADDRESS
+#define CPU_CLOCK_OFFSET WLAN_CPU_CLOCK_OFFSET
+#define CPU_CLOCK_STANDARD_MSB WLAN_CPU_CLOCK_STANDARD_MSB
+#define CPU_CLOCK_STANDARD_LSB WLAN_CPU_CLOCK_STANDARD_LSB
+#define CPU_CLOCK_STANDARD_MASK WLAN_CPU_CLOCK_STANDARD_MASK
+#define CPU_CLOCK_STANDARD_GET(x) WLAN_CPU_CLOCK_STANDARD_GET(x)
+#define CPU_CLOCK_STANDARD_SET(x) WLAN_CPU_CLOCK_STANDARD_SET(x)
+#define CLOCK_OUT_ADDRESS WLAN_CLOCK_OUT_ADDRESS
+#define CLOCK_OUT_OFFSET WLAN_CLOCK_OUT_OFFSET
+#define CLOCK_OUT_SELECT_MSB WLAN_CLOCK_OUT_SELECT_MSB
+#define CLOCK_OUT_SELECT_LSB WLAN_CLOCK_OUT_SELECT_LSB
+#define CLOCK_OUT_SELECT_MASK WLAN_CLOCK_OUT_SELECT_MASK
+#define CLOCK_OUT_SELECT_GET(x) WLAN_CLOCK_OUT_SELECT_GET(x)
+#define CLOCK_OUT_SELECT_SET(x) WLAN_CLOCK_OUT_SELECT_SET(x)
+#define CLOCK_CONTROL_ADDRESS WLAN_CLOCK_CONTROL_ADDRESS
+#define CLOCK_CONTROL_OFFSET WLAN_CLOCK_CONTROL_OFFSET
+#define CLOCK_CONTROL_LF_CLK32_MSB WLAN_CLOCK_CONTROL_LF_CLK32_MSB
+#define CLOCK_CONTROL_LF_CLK32_LSB WLAN_CLOCK_CONTROL_LF_CLK32_LSB
+#define CLOCK_CONTROL_LF_CLK32_MASK WLAN_CLOCK_CONTROL_LF_CLK32_MASK
+#define CLOCK_CONTROL_LF_CLK32_GET(x) WLAN_CLOCK_CONTROL_LF_CLK32_GET(x)
+#define CLOCK_CONTROL_LF_CLK32_SET(x) WLAN_CLOCK_CONTROL_LF_CLK32_SET(x)
+#define CLOCK_CONTROL_SI0_CLK_MSB WLAN_CLOCK_CONTROL_SI0_CLK_MSB
+#define CLOCK_CONTROL_SI0_CLK_LSB WLAN_CLOCK_CONTROL_SI0_CLK_LSB
+#define CLOCK_CONTROL_SI0_CLK_MASK WLAN_CLOCK_CONTROL_SI0_CLK_MASK
+#define CLOCK_CONTROL_SI0_CLK_GET(x) WLAN_CLOCK_CONTROL_SI0_CLK_GET(x)
+#define CLOCK_CONTROL_SI0_CLK_SET(x) WLAN_CLOCK_CONTROL_SI0_CLK_SET(x)
+#define BIAS_OVERRIDE_ADDRESS WLAN_BIAS_OVERRIDE_ADDRESS
+#define BIAS_OVERRIDE_OFFSET WLAN_BIAS_OVERRIDE_OFFSET
+#define BIAS_OVERRIDE_ON_MSB WLAN_BIAS_OVERRIDE_ON_MSB
+#define BIAS_OVERRIDE_ON_LSB WLAN_BIAS_OVERRIDE_ON_LSB
+#define BIAS_OVERRIDE_ON_MASK WLAN_BIAS_OVERRIDE_ON_MASK
+#define BIAS_OVERRIDE_ON_GET(x) WLAN_BIAS_OVERRIDE_ON_GET(x)
+#define BIAS_OVERRIDE_ON_SET(x) WLAN_BIAS_OVERRIDE_ON_SET(x)
+#define WDT_CONTROL_ADDRESS WLAN_WDT_CONTROL_ADDRESS
+#define WDT_CONTROL_OFFSET WLAN_WDT_CONTROL_OFFSET
+#define WDT_CONTROL_ACTION_MSB WLAN_WDT_CONTROL_ACTION_MSB
+#define WDT_CONTROL_ACTION_LSB WLAN_WDT_CONTROL_ACTION_LSB
+#define WDT_CONTROL_ACTION_MASK WLAN_WDT_CONTROL_ACTION_MASK
+#define WDT_CONTROL_ACTION_GET(x) WLAN_WDT_CONTROL_ACTION_GET(x)
+#define WDT_CONTROL_ACTION_SET(x) WLAN_WDT_CONTROL_ACTION_SET(x)
+#define WDT_STATUS_ADDRESS WLAN_WDT_STATUS_ADDRESS
+#define WDT_STATUS_OFFSET WLAN_WDT_STATUS_OFFSET
+#define WDT_STATUS_INTERRUPT_MSB WLAN_WDT_STATUS_INTERRUPT_MSB
+#define WDT_STATUS_INTERRUPT_LSB WLAN_WDT_STATUS_INTERRUPT_LSB
+#define WDT_STATUS_INTERRUPT_MASK WLAN_WDT_STATUS_INTERRUPT_MASK
+#define WDT_STATUS_INTERRUPT_GET(x) WLAN_WDT_STATUS_INTERRUPT_GET(x)
+#define WDT_STATUS_INTERRUPT_SET(x) WLAN_WDT_STATUS_INTERRUPT_SET(x)
+#define WDT_ADDRESS WLAN_WDT_ADDRESS
+#define WDT_OFFSET WLAN_WDT_OFFSET
+#define WDT_TARGET_MSB WLAN_WDT_TARGET_MSB
+#define WDT_TARGET_LSB WLAN_WDT_TARGET_LSB
+#define WDT_TARGET_MASK WLAN_WDT_TARGET_MASK
+#define WDT_TARGET_GET(x) WLAN_WDT_TARGET_GET(x)
+#define WDT_TARGET_SET(x) WLAN_WDT_TARGET_SET(x)
+#define WDT_COUNT_ADDRESS WLAN_WDT_COUNT_ADDRESS
+#define WDT_COUNT_OFFSET WLAN_WDT_COUNT_OFFSET
+#define WDT_COUNT_VALUE_MSB WLAN_WDT_COUNT_VALUE_MSB
+#define WDT_COUNT_VALUE_LSB WLAN_WDT_COUNT_VALUE_LSB
+#define WDT_COUNT_VALUE_MASK WLAN_WDT_COUNT_VALUE_MASK
+#define WDT_COUNT_VALUE_GET(x) WLAN_WDT_COUNT_VALUE_GET(x)
+#define WDT_COUNT_VALUE_SET(x) WLAN_WDT_COUNT_VALUE_SET(x)
+#define WDT_RESET_ADDRESS WLAN_WDT_RESET_ADDRESS
+#define WDT_RESET_OFFSET WLAN_WDT_RESET_OFFSET
+#define WDT_RESET_VALUE_MSB WLAN_WDT_RESET_VALUE_MSB
+#define WDT_RESET_VALUE_LSB WLAN_WDT_RESET_VALUE_LSB
+#define WDT_RESET_VALUE_MASK WLAN_WDT_RESET_VALUE_MASK
+#define WDT_RESET_VALUE_GET(x) WLAN_WDT_RESET_VALUE_GET(x)
+#define WDT_RESET_VALUE_SET(x) WLAN_WDT_RESET_VALUE_SET(x)
+#define INT_STATUS_ADDRESS WLAN_INT_STATUS_ADDRESS
+#define INT_STATUS_OFFSET WLAN_INT_STATUS_OFFSET
+#define INT_STATUS_HCI_UART_MSB WLAN_INT_STATUS_HCI_UART_MSB
+#define INT_STATUS_HCI_UART_LSB WLAN_INT_STATUS_HCI_UART_LSB
+#define INT_STATUS_HCI_UART_MASK WLAN_INT_STATUS_HCI_UART_MASK
+#define INT_STATUS_HCI_UART_GET(x) WLAN_INT_STATUS_HCI_UART_GET(x)
+#define INT_STATUS_HCI_UART_SET(x) WLAN_INT_STATUS_HCI_UART_SET(x)
+#define INT_STATUS_THERM_MSB WLAN_INT_STATUS_THERM_MSB
+#define INT_STATUS_THERM_LSB WLAN_INT_STATUS_THERM_LSB
+#define INT_STATUS_THERM_MASK WLAN_INT_STATUS_THERM_MASK
+#define INT_STATUS_THERM_GET(x) WLAN_INT_STATUS_THERM_GET(x)
+#define INT_STATUS_THERM_SET(x) WLAN_INT_STATUS_THERM_SET(x)
+#define INT_STATUS_EFUSE_OVERWRITE_MSB WLAN_INT_STATUS_EFUSE_OVERWRITE_MSB
+#define INT_STATUS_EFUSE_OVERWRITE_LSB WLAN_INT_STATUS_EFUSE_OVERWRITE_LSB
+#define INT_STATUS_EFUSE_OVERWRITE_MASK WLAN_INT_STATUS_EFUSE_OVERWRITE_MASK
+#define INT_STATUS_EFUSE_OVERWRITE_GET(x) WLAN_INT_STATUS_EFUSE_OVERWRITE_GET(x)
+#define INT_STATUS_EFUSE_OVERWRITE_SET(x) WLAN_INT_STATUS_EFUSE_OVERWRITE_SET(x)
+#define INT_STATUS_UART_MBOX_MSB WLAN_INT_STATUS_UART_MBOX_MSB
+#define INT_STATUS_UART_MBOX_LSB WLAN_INT_STATUS_UART_MBOX_LSB
+#define INT_STATUS_UART_MBOX_MASK WLAN_INT_STATUS_UART_MBOX_MASK
+#define INT_STATUS_UART_MBOX_GET(x) WLAN_INT_STATUS_UART_MBOX_GET(x)
+#define INT_STATUS_UART_MBOX_SET(x) WLAN_INT_STATUS_UART_MBOX_SET(x)
+#define INT_STATUS_GENERIC_MBOX_MSB WLAN_INT_STATUS_GENERIC_MBOX_MSB
+#define INT_STATUS_GENERIC_MBOX_LSB WLAN_INT_STATUS_GENERIC_MBOX_LSB
+#define INT_STATUS_GENERIC_MBOX_MASK WLAN_INT_STATUS_GENERIC_MBOX_MASK
+#define INT_STATUS_GENERIC_MBOX_GET(x) WLAN_INT_STATUS_GENERIC_MBOX_GET(x)
+#define INT_STATUS_GENERIC_MBOX_SET(x) WLAN_INT_STATUS_GENERIC_MBOX_SET(x)
+#define INT_STATUS_RDMA_MSB WLAN_INT_STATUS_RDMA_MSB
+#define INT_STATUS_RDMA_LSB WLAN_INT_STATUS_RDMA_LSB
+#define INT_STATUS_RDMA_MASK WLAN_INT_STATUS_RDMA_MASK
+#define INT_STATUS_RDMA_GET(x) WLAN_INT_STATUS_RDMA_GET(x)
+#define INT_STATUS_RDMA_SET(x) WLAN_INT_STATUS_RDMA_SET(x)
+#define INT_STATUS_BTCOEX_MSB WLAN_INT_STATUS_BTCOEX_MSB
+#define INT_STATUS_BTCOEX_LSB WLAN_INT_STATUS_BTCOEX_LSB
+#define INT_STATUS_BTCOEX_MASK WLAN_INT_STATUS_BTCOEX_MASK
+#define INT_STATUS_BTCOEX_GET(x) WLAN_INT_STATUS_BTCOEX_GET(x)
+#define INT_STATUS_BTCOEX_SET(x) WLAN_INT_STATUS_BTCOEX_SET(x)
+#define INT_STATUS_RTC_POWER_MSB WLAN_INT_STATUS_RTC_POWER_MSB
+#define INT_STATUS_RTC_POWER_LSB WLAN_INT_STATUS_RTC_POWER_LSB
+#define INT_STATUS_RTC_POWER_MASK WLAN_INT_STATUS_RTC_POWER_MASK
+#define INT_STATUS_RTC_POWER_GET(x) WLAN_INT_STATUS_RTC_POWER_GET(x)
+#define INT_STATUS_RTC_POWER_SET(x) WLAN_INT_STATUS_RTC_POWER_SET(x)
+#define INT_STATUS_MAC_MSB WLAN_INT_STATUS_MAC_MSB
+#define INT_STATUS_MAC_LSB WLAN_INT_STATUS_MAC_LSB
+#define INT_STATUS_MAC_MASK WLAN_INT_STATUS_MAC_MASK
+#define INT_STATUS_MAC_GET(x) WLAN_INT_STATUS_MAC_GET(x)
+#define INT_STATUS_MAC_SET(x) WLAN_INT_STATUS_MAC_SET(x)
+#define INT_STATUS_MAILBOX_MSB WLAN_INT_STATUS_MAILBOX_MSB
+#define INT_STATUS_MAILBOX_LSB WLAN_INT_STATUS_MAILBOX_LSB
+#define INT_STATUS_MAILBOX_MASK WLAN_INT_STATUS_MAILBOX_MASK
+#define INT_STATUS_MAILBOX_GET(x) WLAN_INT_STATUS_MAILBOX_GET(x)
+#define INT_STATUS_MAILBOX_SET(x) WLAN_INT_STATUS_MAILBOX_SET(x)
+#define INT_STATUS_RTC_ALARM_MSB WLAN_INT_STATUS_RTC_ALARM_MSB
+#define INT_STATUS_RTC_ALARM_LSB WLAN_INT_STATUS_RTC_ALARM_LSB
+#define INT_STATUS_RTC_ALARM_MASK WLAN_INT_STATUS_RTC_ALARM_MASK
+#define INT_STATUS_RTC_ALARM_GET(x) WLAN_INT_STATUS_RTC_ALARM_GET(x)
+#define INT_STATUS_RTC_ALARM_SET(x) WLAN_INT_STATUS_RTC_ALARM_SET(x)
+#define INT_STATUS_HF_TIMER_MSB WLAN_INT_STATUS_HF_TIMER_MSB
+#define INT_STATUS_HF_TIMER_LSB WLAN_INT_STATUS_HF_TIMER_LSB
+#define INT_STATUS_HF_TIMER_MASK WLAN_INT_STATUS_HF_TIMER_MASK
+#define INT_STATUS_HF_TIMER_GET(x) WLAN_INT_STATUS_HF_TIMER_GET(x)
+#define INT_STATUS_HF_TIMER_SET(x) WLAN_INT_STATUS_HF_TIMER_SET(x)
+#define INT_STATUS_LF_TIMER3_MSB WLAN_INT_STATUS_LF_TIMER3_MSB
+#define INT_STATUS_LF_TIMER3_LSB WLAN_INT_STATUS_LF_TIMER3_LSB
+#define INT_STATUS_LF_TIMER3_MASK WLAN_INT_STATUS_LF_TIMER3_MASK
+#define INT_STATUS_LF_TIMER3_GET(x) WLAN_INT_STATUS_LF_TIMER3_GET(x)
+#define INT_STATUS_LF_TIMER3_SET(x) WLAN_INT_STATUS_LF_TIMER3_SET(x)
+#define INT_STATUS_LF_TIMER2_MSB WLAN_INT_STATUS_LF_TIMER2_MSB
+#define INT_STATUS_LF_TIMER2_LSB WLAN_INT_STATUS_LF_TIMER2_LSB
+#define INT_STATUS_LF_TIMER2_MASK WLAN_INT_STATUS_LF_TIMER2_MASK
+#define INT_STATUS_LF_TIMER2_GET(x) WLAN_INT_STATUS_LF_TIMER2_GET(x)
+#define INT_STATUS_LF_TIMER2_SET(x) WLAN_INT_STATUS_LF_TIMER2_SET(x)
+#define INT_STATUS_LF_TIMER1_MSB WLAN_INT_STATUS_LF_TIMER1_MSB
+#define INT_STATUS_LF_TIMER1_LSB WLAN_INT_STATUS_LF_TIMER1_LSB
+#define INT_STATUS_LF_TIMER1_MASK WLAN_INT_STATUS_LF_TIMER1_MASK
+#define INT_STATUS_LF_TIMER1_GET(x) WLAN_INT_STATUS_LF_TIMER1_GET(x)
+#define INT_STATUS_LF_TIMER1_SET(x) WLAN_INT_STATUS_LF_TIMER1_SET(x)
+#define INT_STATUS_LF_TIMER0_MSB WLAN_INT_STATUS_LF_TIMER0_MSB
+#define INT_STATUS_LF_TIMER0_LSB WLAN_INT_STATUS_LF_TIMER0_LSB
+#define INT_STATUS_LF_TIMER0_MASK WLAN_INT_STATUS_LF_TIMER0_MASK
+#define INT_STATUS_LF_TIMER0_GET(x) WLAN_INT_STATUS_LF_TIMER0_GET(x)
+#define INT_STATUS_LF_TIMER0_SET(x) WLAN_INT_STATUS_LF_TIMER0_SET(x)
+#define INT_STATUS_KEYPAD_MSB WLAN_INT_STATUS_KEYPAD_MSB
+#define INT_STATUS_KEYPAD_LSB WLAN_INT_STATUS_KEYPAD_LSB
+#define INT_STATUS_KEYPAD_MASK WLAN_INT_STATUS_KEYPAD_MASK
+#define INT_STATUS_KEYPAD_GET(x) WLAN_INT_STATUS_KEYPAD_GET(x)
+#define INT_STATUS_KEYPAD_SET(x) WLAN_INT_STATUS_KEYPAD_SET(x)
+#define INT_STATUS_SI_MSB WLAN_INT_STATUS_SI_MSB
+#define INT_STATUS_SI_LSB WLAN_INT_STATUS_SI_LSB
+#define INT_STATUS_SI_MASK WLAN_INT_STATUS_SI_MASK
+#define INT_STATUS_SI_GET(x) WLAN_INT_STATUS_SI_GET(x)
+#define INT_STATUS_SI_SET(x) WLAN_INT_STATUS_SI_SET(x)
+#define INT_STATUS_GPIO_MSB WLAN_INT_STATUS_GPIO_MSB
+#define INT_STATUS_GPIO_LSB WLAN_INT_STATUS_GPIO_LSB
+#define INT_STATUS_GPIO_MASK WLAN_INT_STATUS_GPIO_MASK
+#define INT_STATUS_GPIO_GET(x) WLAN_INT_STATUS_GPIO_GET(x)
+#define INT_STATUS_GPIO_SET(x) WLAN_INT_STATUS_GPIO_SET(x)
+#define INT_STATUS_UART_MSB WLAN_INT_STATUS_UART_MSB
+#define INT_STATUS_UART_LSB WLAN_INT_STATUS_UART_LSB
+#define INT_STATUS_UART_MASK WLAN_INT_STATUS_UART_MASK
+#define INT_STATUS_UART_GET(x) WLAN_INT_STATUS_UART_GET(x)
+#define INT_STATUS_UART_SET(x) WLAN_INT_STATUS_UART_SET(x)
+#define INT_STATUS_ERROR_MSB WLAN_INT_STATUS_ERROR_MSB
+#define INT_STATUS_ERROR_LSB WLAN_INT_STATUS_ERROR_LSB
+#define INT_STATUS_ERROR_MASK WLAN_INT_STATUS_ERROR_MASK
+#define INT_STATUS_ERROR_GET(x) WLAN_INT_STATUS_ERROR_GET(x)
+#define INT_STATUS_ERROR_SET(x) WLAN_INT_STATUS_ERROR_SET(x)
+#define INT_STATUS_WDT_INT_MSB WLAN_INT_STATUS_WDT_INT_MSB
+#define INT_STATUS_WDT_INT_LSB WLAN_INT_STATUS_WDT_INT_LSB
+#define INT_STATUS_WDT_INT_MASK WLAN_INT_STATUS_WDT_INT_MASK
+#define INT_STATUS_WDT_INT_GET(x) WLAN_INT_STATUS_WDT_INT_GET(x)
+#define INT_STATUS_WDT_INT_SET(x) WLAN_INT_STATUS_WDT_INT_SET(x)
+#define LF_TIMER0_ADDRESS WLAN_LF_TIMER0_ADDRESS
+#define LF_TIMER0_OFFSET WLAN_LF_TIMER0_OFFSET
+#define LF_TIMER0_TARGET_MSB WLAN_LF_TIMER0_TARGET_MSB
+#define LF_TIMER0_TARGET_LSB WLAN_LF_TIMER0_TARGET_LSB
+#define LF_TIMER0_TARGET_MASK WLAN_LF_TIMER0_TARGET_MASK
+#define LF_TIMER0_TARGET_GET(x) WLAN_LF_TIMER0_TARGET_GET(x)
+#define LF_TIMER0_TARGET_SET(x) WLAN_LF_TIMER0_TARGET_SET(x)
+#define LF_TIMER_COUNT0_ADDRESS WLAN_LF_TIMER_COUNT0_ADDRESS
+#define LF_TIMER_COUNT0_OFFSET WLAN_LF_TIMER_COUNT0_OFFSET
+#define LF_TIMER_COUNT0_VALUE_MSB WLAN_LF_TIMER_COUNT0_VALUE_MSB
+#define LF_TIMER_COUNT0_VALUE_LSB WLAN_LF_TIMER_COUNT0_VALUE_LSB
+#define LF_TIMER_COUNT0_VALUE_MASK WLAN_LF_TIMER_COUNT0_VALUE_MASK
+#define LF_TIMER_COUNT0_VALUE_GET(x) WLAN_LF_TIMER_COUNT0_VALUE_GET(x)
+#define LF_TIMER_COUNT0_VALUE_SET(x) WLAN_LF_TIMER_COUNT0_VALUE_SET(x)
+#define LF_TIMER_CONTROL0_ADDRESS WLAN_LF_TIMER_CONTROL0_ADDRESS
+#define LF_TIMER_CONTROL0_OFFSET WLAN_LF_TIMER_CONTROL0_OFFSET
+#define LF_TIMER_CONTROL0_ENABLE_MSB WLAN_LF_TIMER_CONTROL0_ENABLE_MSB
+#define LF_TIMER_CONTROL0_ENABLE_LSB WLAN_LF_TIMER_CONTROL0_ENABLE_LSB
+#define LF_TIMER_CONTROL0_ENABLE_MASK WLAN_LF_TIMER_CONTROL0_ENABLE_MASK
+#define LF_TIMER_CONTROL0_ENABLE_GET(x) WLAN_LF_TIMER_CONTROL0_ENABLE_GET(x)
+#define LF_TIMER_CONTROL0_ENABLE_SET(x) WLAN_LF_TIMER_CONTROL0_ENABLE_SET(x)
+#define LF_TIMER_CONTROL0_AUTO_RESTART_MSB WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_MSB
+#define LF_TIMER_CONTROL0_AUTO_RESTART_LSB WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_LSB
+#define LF_TIMER_CONTROL0_AUTO_RESTART_MASK WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_MASK
+#define LF_TIMER_CONTROL0_AUTO_RESTART_GET(x) WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_GET(x)
+#define LF_TIMER_CONTROL0_AUTO_RESTART_SET(x) WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_SET(x)
+#define LF_TIMER_CONTROL0_RESET_MSB WLAN_LF_TIMER_CONTROL0_RESET_MSB
+#define LF_TIMER_CONTROL0_RESET_LSB WLAN_LF_TIMER_CONTROL0_RESET_LSB
+#define LF_TIMER_CONTROL0_RESET_MASK WLAN_LF_TIMER_CONTROL0_RESET_MASK
+#define LF_TIMER_CONTROL0_RESET_GET(x) WLAN_LF_TIMER_CONTROL0_RESET_GET(x)
+#define LF_TIMER_CONTROL0_RESET_SET(x) WLAN_LF_TIMER_CONTROL0_RESET_SET(x)
+#define LF_TIMER_STATUS0_ADDRESS WLAN_LF_TIMER_STATUS0_ADDRESS
+#define LF_TIMER_STATUS0_OFFSET WLAN_LF_TIMER_STATUS0_OFFSET
+#define LF_TIMER_STATUS0_INTERRUPT_MSB WLAN_LF_TIMER_STATUS0_INTERRUPT_MSB
+#define LF_TIMER_STATUS0_INTERRUPT_LSB WLAN_LF_TIMER_STATUS0_INTERRUPT_LSB
+#define LF_TIMER_STATUS0_INTERRUPT_MASK WLAN_LF_TIMER_STATUS0_INTERRUPT_MASK
+#define LF_TIMER_STATUS0_INTERRUPT_GET(x) WLAN_LF_TIMER_STATUS0_INTERRUPT_GET(x)
+#define LF_TIMER_STATUS0_INTERRUPT_SET(x) WLAN_LF_TIMER_STATUS0_INTERRUPT_SET(x)
+#define LF_TIMER1_ADDRESS WLAN_LF_TIMER1_ADDRESS
+#define LF_TIMER1_OFFSET WLAN_LF_TIMER1_OFFSET
+#define LF_TIMER1_TARGET_MSB WLAN_LF_TIMER1_TARGET_MSB
+#define LF_TIMER1_TARGET_LSB WLAN_LF_TIMER1_TARGET_LSB
+#define LF_TIMER1_TARGET_MASK WLAN_LF_TIMER1_TARGET_MASK
+#define LF_TIMER1_TARGET_GET(x) WLAN_LF_TIMER1_TARGET_GET(x)
+#define LF_TIMER1_TARGET_SET(x) WLAN_LF_TIMER1_TARGET_SET(x)
+#define LF_TIMER_COUNT1_ADDRESS WLAN_LF_TIMER_COUNT1_ADDRESS
+#define LF_TIMER_COUNT1_OFFSET WLAN_LF_TIMER_COUNT1_OFFSET
+#define LF_TIMER_COUNT1_VALUE_MSB WLAN_LF_TIMER_COUNT1_VALUE_MSB
+#define LF_TIMER_COUNT1_VALUE_LSB WLAN_LF_TIMER_COUNT1_VALUE_LSB
+#define LF_TIMER_COUNT1_VALUE_MASK WLAN_LF_TIMER_COUNT1_VALUE_MASK
+#define LF_TIMER_COUNT1_VALUE_GET(x) WLAN_LF_TIMER_COUNT1_VALUE_GET(x)
+#define LF_TIMER_COUNT1_VALUE_SET(x) WLAN_LF_TIMER_COUNT1_VALUE_SET(x)
+#define LF_TIMER_CONTROL1_ADDRESS WLAN_LF_TIMER_CONTROL1_ADDRESS
+#define LF_TIMER_CONTROL1_OFFSET WLAN_LF_TIMER_CONTROL1_OFFSET
+#define LF_TIMER_CONTROL1_ENABLE_MSB WLAN_LF_TIMER_CONTROL1_ENABLE_MSB
+#define LF_TIMER_CONTROL1_ENABLE_LSB WLAN_LF_TIMER_CONTROL1_ENABLE_LSB
+#define LF_TIMER_CONTROL1_ENABLE_MASK WLAN_LF_TIMER_CONTROL1_ENABLE_MASK
+#define LF_TIMER_CONTROL1_ENABLE_GET(x) WLAN_LF_TIMER_CONTROL1_ENABLE_GET(x)
+#define LF_TIMER_CONTROL1_ENABLE_SET(x) WLAN_LF_TIMER_CONTROL1_ENABLE_SET(x)
+#define LF_TIMER_CONTROL1_AUTO_RESTART_MSB WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_MSB
+#define LF_TIMER_CONTROL1_AUTO_RESTART_LSB WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_LSB
+#define LF_TIMER_CONTROL1_AUTO_RESTART_MASK WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_MASK
+#define LF_TIMER_CONTROL1_AUTO_RESTART_GET(x) WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_GET(x)
+#define LF_TIMER_CONTROL1_AUTO_RESTART_SET(x) WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_SET(x)
+#define LF_TIMER_CONTROL1_RESET_MSB WLAN_LF_TIMER_CONTROL1_RESET_MSB
+#define LF_TIMER_CONTROL1_RESET_LSB WLAN_LF_TIMER_CONTROL1_RESET_LSB
+#define LF_TIMER_CONTROL1_RESET_MASK WLAN_LF_TIMER_CONTROL1_RESET_MASK
+#define LF_TIMER_CONTROL1_RESET_GET(x) WLAN_LF_TIMER_CONTROL1_RESET_GET(x)
+#define LF_TIMER_CONTROL1_RESET_SET(x) WLAN_LF_TIMER_CONTROL1_RESET_SET(x)
+#define LF_TIMER_STATUS1_ADDRESS WLAN_LF_TIMER_STATUS1_ADDRESS
+#define LF_TIMER_STATUS1_OFFSET WLAN_LF_TIMER_STATUS1_OFFSET
+#define LF_TIMER_STATUS1_INTERRUPT_MSB WLAN_LF_TIMER_STATUS1_INTERRUPT_MSB
+#define LF_TIMER_STATUS1_INTERRUPT_LSB WLAN_LF_TIMER_STATUS1_INTERRUPT_LSB
+#define LF_TIMER_STATUS1_INTERRUPT_MASK WLAN_LF_TIMER_STATUS1_INTERRUPT_MASK
+#define LF_TIMER_STATUS1_INTERRUPT_GET(x) WLAN_LF_TIMER_STATUS1_INTERRUPT_GET(x)
+#define LF_TIMER_STATUS1_INTERRUPT_SET(x) WLAN_LF_TIMER_STATUS1_INTERRUPT_SET(x)
+#define LF_TIMER2_ADDRESS WLAN_LF_TIMER2_ADDRESS
+#define LF_TIMER2_OFFSET WLAN_LF_TIMER2_OFFSET
+#define LF_TIMER2_TARGET_MSB WLAN_LF_TIMER2_TARGET_MSB
+#define LF_TIMER2_TARGET_LSB WLAN_LF_TIMER2_TARGET_LSB
+#define LF_TIMER2_TARGET_MASK WLAN_LF_TIMER2_TARGET_MASK
+#define LF_TIMER2_TARGET_GET(x) WLAN_LF_TIMER2_TARGET_GET(x)
+#define LF_TIMER2_TARGET_SET(x) WLAN_LF_TIMER2_TARGET_SET(x)
+#define LF_TIMER_COUNT2_ADDRESS WLAN_LF_TIMER_COUNT2_ADDRESS
+#define LF_TIMER_COUNT2_OFFSET WLAN_LF_TIMER_COUNT2_OFFSET
+#define LF_TIMER_COUNT2_VALUE_MSB WLAN_LF_TIMER_COUNT2_VALUE_MSB
+#define LF_TIMER_COUNT2_VALUE_LSB WLAN_LF_TIMER_COUNT2_VALUE_LSB
+#define LF_TIMER_COUNT2_VALUE_MASK WLAN_LF_TIMER_COUNT2_VALUE_MASK
+#define LF_TIMER_COUNT2_VALUE_GET(x) WLAN_LF_TIMER_COUNT2_VALUE_GET(x)
+#define LF_TIMER_COUNT2_VALUE_SET(x) WLAN_LF_TIMER_COUNT2_VALUE_SET(x)
+#define LF_TIMER_CONTROL2_ADDRESS WLAN_LF_TIMER_CONTROL2_ADDRESS
+#define LF_TIMER_CONTROL2_OFFSET WLAN_LF_TIMER_CONTROL2_OFFSET
+#define LF_TIMER_CONTROL2_ENABLE_MSB WLAN_LF_TIMER_CONTROL2_ENABLE_MSB
+#define LF_TIMER_CONTROL2_ENABLE_LSB WLAN_LF_TIMER_CONTROL2_ENABLE_LSB
+#define LF_TIMER_CONTROL2_ENABLE_MASK WLAN_LF_TIMER_CONTROL2_ENABLE_MASK
+#define LF_TIMER_CONTROL2_ENABLE_GET(x) WLAN_LF_TIMER_CONTROL2_ENABLE_GET(x)
+#define LF_TIMER_CONTROL2_ENABLE_SET(x) WLAN_LF_TIMER_CONTROL2_ENABLE_SET(x)
+#define LF_TIMER_CONTROL2_AUTO_RESTART_MSB WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_MSB
+#define LF_TIMER_CONTROL2_AUTO_RESTART_LSB WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_LSB
+#define LF_TIMER_CONTROL2_AUTO_RESTART_MASK WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_MASK
+#define LF_TIMER_CONTROL2_AUTO_RESTART_GET(x) WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_GET(x)
+#define LF_TIMER_CONTROL2_AUTO_RESTART_SET(x) WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_SET(x)
+#define LF_TIMER_CONTROL2_RESET_MSB WLAN_LF_TIMER_CONTROL2_RESET_MSB
+#define LF_TIMER_CONTROL2_RESET_LSB WLAN_LF_TIMER_CONTROL2_RESET_LSB
+#define LF_TIMER_CONTROL2_RESET_MASK WLAN_LF_TIMER_CONTROL2_RESET_MASK
+#define LF_TIMER_CONTROL2_RESET_GET(x) WLAN_LF_TIMER_CONTROL2_RESET_GET(x)
+#define LF_TIMER_CONTROL2_RESET_SET(x) WLAN_LF_TIMER_CONTROL2_RESET_SET(x)
+#define LF_TIMER_STATUS2_ADDRESS WLAN_LF_TIMER_STATUS2_ADDRESS
+#define LF_TIMER_STATUS2_OFFSET WLAN_LF_TIMER_STATUS2_OFFSET
+#define LF_TIMER_STATUS2_INTERRUPT_MSB WLAN_LF_TIMER_STATUS2_INTERRUPT_MSB
+#define LF_TIMER_STATUS2_INTERRUPT_LSB WLAN_LF_TIMER_STATUS2_INTERRUPT_LSB
+#define LF_TIMER_STATUS2_INTERRUPT_MASK WLAN_LF_TIMER_STATUS2_INTERRUPT_MASK
+#define LF_TIMER_STATUS2_INTERRUPT_GET(x) WLAN_LF_TIMER_STATUS2_INTERRUPT_GET(x)
+#define LF_TIMER_STATUS2_INTERRUPT_SET(x) WLAN_LF_TIMER_STATUS2_INTERRUPT_SET(x)
+#define LF_TIMER3_ADDRESS WLAN_LF_TIMER3_ADDRESS
+#define LF_TIMER3_OFFSET WLAN_LF_TIMER3_OFFSET
+#define LF_TIMER3_TARGET_MSB WLAN_LF_TIMER3_TARGET_MSB
+#define LF_TIMER3_TARGET_LSB WLAN_LF_TIMER3_TARGET_LSB
+#define LF_TIMER3_TARGET_MASK WLAN_LF_TIMER3_TARGET_MASK
+#define LF_TIMER3_TARGET_GET(x) WLAN_LF_TIMER3_TARGET_GET(x)
+#define LF_TIMER3_TARGET_SET(x) WLAN_LF_TIMER3_TARGET_SET(x)
+#define LF_TIMER_COUNT3_ADDRESS WLAN_LF_TIMER_COUNT3_ADDRESS
+#define LF_TIMER_COUNT3_OFFSET WLAN_LF_TIMER_COUNT3_OFFSET
+#define LF_TIMER_COUNT3_VALUE_MSB WLAN_LF_TIMER_COUNT3_VALUE_MSB
+#define LF_TIMER_COUNT3_VALUE_LSB WLAN_LF_TIMER_COUNT3_VALUE_LSB
+#define LF_TIMER_COUNT3_VALUE_MASK WLAN_LF_TIMER_COUNT3_VALUE_MASK
+#define LF_TIMER_COUNT3_VALUE_GET(x) WLAN_LF_TIMER_COUNT3_VALUE_GET(x)
+#define LF_TIMER_COUNT3_VALUE_SET(x) WLAN_LF_TIMER_COUNT3_VALUE_SET(x)
+#define LF_TIMER_CONTROL3_ADDRESS WLAN_LF_TIMER_CONTROL3_ADDRESS
+#define LF_TIMER_CONTROL3_OFFSET WLAN_LF_TIMER_CONTROL3_OFFSET
+#define LF_TIMER_CONTROL3_ENABLE_MSB WLAN_LF_TIMER_CONTROL3_ENABLE_MSB
+#define LF_TIMER_CONTROL3_ENABLE_LSB WLAN_LF_TIMER_CONTROL3_ENABLE_LSB
+#define LF_TIMER_CONTROL3_ENABLE_MASK WLAN_LF_TIMER_CONTROL3_ENABLE_MASK
+#define LF_TIMER_CONTROL3_ENABLE_GET(x) WLAN_LF_TIMER_CONTROL3_ENABLE_GET(x)
+#define LF_TIMER_CONTROL3_ENABLE_SET(x) WLAN_LF_TIMER_CONTROL3_ENABLE_SET(x)
+#define LF_TIMER_CONTROL3_AUTO_RESTART_MSB WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_MSB
+#define LF_TIMER_CONTROL3_AUTO_RESTART_LSB WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_LSB
+#define LF_TIMER_CONTROL3_AUTO_RESTART_MASK WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_MASK
+#define LF_TIMER_CONTROL3_AUTO_RESTART_GET(x) WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_GET(x)
+#define LF_TIMER_CONTROL3_AUTO_RESTART_SET(x) WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_SET(x)
+#define LF_TIMER_CONTROL3_RESET_MSB WLAN_LF_TIMER_CONTROL3_RESET_MSB
+#define LF_TIMER_CONTROL3_RESET_LSB WLAN_LF_TIMER_CONTROL3_RESET_LSB
+#define LF_TIMER_CONTROL3_RESET_MASK WLAN_LF_TIMER_CONTROL3_RESET_MASK
+#define LF_TIMER_CONTROL3_RESET_GET(x) WLAN_LF_TIMER_CONTROL3_RESET_GET(x)
+#define LF_TIMER_CONTROL3_RESET_SET(x) WLAN_LF_TIMER_CONTROL3_RESET_SET(x)
+#define LF_TIMER_STATUS3_ADDRESS WLAN_LF_TIMER_STATUS3_ADDRESS
+#define LF_TIMER_STATUS3_OFFSET WLAN_LF_TIMER_STATUS3_OFFSET
+#define LF_TIMER_STATUS3_INTERRUPT_MSB WLAN_LF_TIMER_STATUS3_INTERRUPT_MSB
+#define LF_TIMER_STATUS3_INTERRUPT_LSB WLAN_LF_TIMER_STATUS3_INTERRUPT_LSB
+#define LF_TIMER_STATUS3_INTERRUPT_MASK WLAN_LF_TIMER_STATUS3_INTERRUPT_MASK
+#define LF_TIMER_STATUS3_INTERRUPT_GET(x) WLAN_LF_TIMER_STATUS3_INTERRUPT_GET(x)
+#define LF_TIMER_STATUS3_INTERRUPT_SET(x) WLAN_LF_TIMER_STATUS3_INTERRUPT_SET(x)
+#define HF_TIMER_ADDRESS WLAN_HF_TIMER_ADDRESS
+#define HF_TIMER_OFFSET WLAN_HF_TIMER_OFFSET
+#define HF_TIMER_TARGET_MSB WLAN_HF_TIMER_TARGET_MSB
+#define HF_TIMER_TARGET_LSB WLAN_HF_TIMER_TARGET_LSB
+#define HF_TIMER_TARGET_MASK WLAN_HF_TIMER_TARGET_MASK
+#define HF_TIMER_TARGET_GET(x) WLAN_HF_TIMER_TARGET_GET(x)
+#define HF_TIMER_TARGET_SET(x) WLAN_HF_TIMER_TARGET_SET(x)
+#define HF_TIMER_COUNT_ADDRESS WLAN_HF_TIMER_COUNT_ADDRESS
+#define HF_TIMER_COUNT_OFFSET WLAN_HF_TIMER_COUNT_OFFSET
+#define HF_TIMER_COUNT_VALUE_MSB WLAN_HF_TIMER_COUNT_VALUE_MSB
+#define HF_TIMER_COUNT_VALUE_LSB WLAN_HF_TIMER_COUNT_VALUE_LSB
+#define HF_TIMER_COUNT_VALUE_MASK WLAN_HF_TIMER_COUNT_VALUE_MASK
+#define HF_TIMER_COUNT_VALUE_GET(x) WLAN_HF_TIMER_COUNT_VALUE_GET(x)
+#define HF_TIMER_COUNT_VALUE_SET(x) WLAN_HF_TIMER_COUNT_VALUE_SET(x)
+#define HF_LF_COUNT_ADDRESS WLAN_HF_LF_COUNT_ADDRESS
+#define HF_LF_COUNT_OFFSET WLAN_HF_LF_COUNT_OFFSET
+#define HF_LF_COUNT_VALUE_MSB WLAN_HF_LF_COUNT_VALUE_MSB
+#define HF_LF_COUNT_VALUE_LSB WLAN_HF_LF_COUNT_VALUE_LSB
+#define HF_LF_COUNT_VALUE_MASK WLAN_HF_LF_COUNT_VALUE_MASK
+#define HF_LF_COUNT_VALUE_GET(x) WLAN_HF_LF_COUNT_VALUE_GET(x)
+#define HF_LF_COUNT_VALUE_SET(x) WLAN_HF_LF_COUNT_VALUE_SET(x)
+#define HF_TIMER_CONTROL_ADDRESS WLAN_HF_TIMER_CONTROL_ADDRESS
+#define HF_TIMER_CONTROL_OFFSET WLAN_HF_TIMER_CONTROL_OFFSET
+#define HF_TIMER_CONTROL_ENABLE_MSB WLAN_HF_TIMER_CONTROL_ENABLE_MSB
+#define HF_TIMER_CONTROL_ENABLE_LSB WLAN_HF_TIMER_CONTROL_ENABLE_LSB
+#define HF_TIMER_CONTROL_ENABLE_MASK WLAN_HF_TIMER_CONTROL_ENABLE_MASK
+#define HF_TIMER_CONTROL_ENABLE_GET(x) WLAN_HF_TIMER_CONTROL_ENABLE_GET(x)
+#define HF_TIMER_CONTROL_ENABLE_SET(x) WLAN_HF_TIMER_CONTROL_ENABLE_SET(x)
+#define HF_TIMER_CONTROL_ON_MSB WLAN_HF_TIMER_CONTROL_ON_MSB
+#define HF_TIMER_CONTROL_ON_LSB WLAN_HF_TIMER_CONTROL_ON_LSB
+#define HF_TIMER_CONTROL_ON_MASK WLAN_HF_TIMER_CONTROL_ON_MASK
+#define HF_TIMER_CONTROL_ON_GET(x) WLAN_HF_TIMER_CONTROL_ON_GET(x)
+#define HF_TIMER_CONTROL_ON_SET(x) WLAN_HF_TIMER_CONTROL_ON_SET(x)
+#define HF_TIMER_CONTROL_AUTO_RESTART_MSB WLAN_HF_TIMER_CONTROL_AUTO_RESTART_MSB
+#define HF_TIMER_CONTROL_AUTO_RESTART_LSB WLAN_HF_TIMER_CONTROL_AUTO_RESTART_LSB
+#define HF_TIMER_CONTROL_AUTO_RESTART_MASK WLAN_HF_TIMER_CONTROL_AUTO_RESTART_MASK
+#define HF_TIMER_CONTROL_AUTO_RESTART_GET(x) WLAN_HF_TIMER_CONTROL_AUTO_RESTART_GET(x)
+#define HF_TIMER_CONTROL_AUTO_RESTART_SET(x) WLAN_HF_TIMER_CONTROL_AUTO_RESTART_SET(x)
+#define HF_TIMER_CONTROL_RESET_MSB WLAN_HF_TIMER_CONTROL_RESET_MSB
+#define HF_TIMER_CONTROL_RESET_LSB WLAN_HF_TIMER_CONTROL_RESET_LSB
+#define HF_TIMER_CONTROL_RESET_MASK WLAN_HF_TIMER_CONTROL_RESET_MASK
+#define HF_TIMER_CONTROL_RESET_GET(x) WLAN_HF_TIMER_CONTROL_RESET_GET(x)
+#define HF_TIMER_CONTROL_RESET_SET(x) WLAN_HF_TIMER_CONTROL_RESET_SET(x)
+#define HF_TIMER_STATUS_ADDRESS WLAN_HF_TIMER_STATUS_ADDRESS
+#define HF_TIMER_STATUS_OFFSET WLAN_HF_TIMER_STATUS_OFFSET
+#define HF_TIMER_STATUS_INTERRUPT_MSB WLAN_HF_TIMER_STATUS_INTERRUPT_MSB
+#define HF_TIMER_STATUS_INTERRUPT_LSB WLAN_HF_TIMER_STATUS_INTERRUPT_LSB
+#define HF_TIMER_STATUS_INTERRUPT_MASK WLAN_HF_TIMER_STATUS_INTERRUPT_MASK
+#define HF_TIMER_STATUS_INTERRUPT_GET(x) WLAN_HF_TIMER_STATUS_INTERRUPT_GET(x)
+#define HF_TIMER_STATUS_INTERRUPT_SET(x) WLAN_HF_TIMER_STATUS_INTERRUPT_SET(x)
+#define RTC_CONTROL_ADDRESS WLAN_RTC_CONTROL_ADDRESS
+#define RTC_CONTROL_OFFSET WLAN_RTC_CONTROL_OFFSET
+#define RTC_CONTROL_ENABLE_MSB WLAN_RTC_CONTROL_ENABLE_MSB
+#define RTC_CONTROL_ENABLE_LSB WLAN_RTC_CONTROL_ENABLE_LSB
+#define RTC_CONTROL_ENABLE_MASK WLAN_RTC_CONTROL_ENABLE_MASK
+#define RTC_CONTROL_ENABLE_GET(x) WLAN_RTC_CONTROL_ENABLE_GET(x)
+#define RTC_CONTROL_ENABLE_SET(x) WLAN_RTC_CONTROL_ENABLE_SET(x)
+#define RTC_CONTROL_LOAD_RTC_MSB WLAN_RTC_CONTROL_LOAD_RTC_MSB
+#define RTC_CONTROL_LOAD_RTC_LSB WLAN_RTC_CONTROL_LOAD_RTC_LSB
+#define RTC_CONTROL_LOAD_RTC_MASK WLAN_RTC_CONTROL_LOAD_RTC_MASK
+#define RTC_CONTROL_LOAD_RTC_GET(x) WLAN_RTC_CONTROL_LOAD_RTC_GET(x)
+#define RTC_CONTROL_LOAD_RTC_SET(x) WLAN_RTC_CONTROL_LOAD_RTC_SET(x)
+#define RTC_CONTROL_LOAD_ALARM_MSB WLAN_RTC_CONTROL_LOAD_ALARM_MSB
+#define RTC_CONTROL_LOAD_ALARM_LSB WLAN_RTC_CONTROL_LOAD_ALARM_LSB
+#define RTC_CONTROL_LOAD_ALARM_MASK WLAN_RTC_CONTROL_LOAD_ALARM_MASK
+#define RTC_CONTROL_LOAD_ALARM_GET(x) WLAN_RTC_CONTROL_LOAD_ALARM_GET(x)
+#define RTC_CONTROL_LOAD_ALARM_SET(x) WLAN_RTC_CONTROL_LOAD_ALARM_SET(x)
+#define RTC_TIME_ADDRESS WLAN_RTC_TIME_ADDRESS
+#define RTC_TIME_OFFSET WLAN_RTC_TIME_OFFSET
+#define RTC_TIME_WEEK_DAY_MSB WLAN_RTC_TIME_WEEK_DAY_MSB
+#define RTC_TIME_WEEK_DAY_LSB WLAN_RTC_TIME_WEEK_DAY_LSB
+#define RTC_TIME_WEEK_DAY_MASK WLAN_RTC_TIME_WEEK_DAY_MASK
+#define RTC_TIME_WEEK_DAY_GET(x) WLAN_RTC_TIME_WEEK_DAY_GET(x)
+#define RTC_TIME_WEEK_DAY_SET(x) WLAN_RTC_TIME_WEEK_DAY_SET(x)
+#define RTC_TIME_HOUR_MSB WLAN_RTC_TIME_HOUR_MSB
+#define RTC_TIME_HOUR_LSB WLAN_RTC_TIME_HOUR_LSB
+#define RTC_TIME_HOUR_MASK WLAN_RTC_TIME_HOUR_MASK
+#define RTC_TIME_HOUR_GET(x) WLAN_RTC_TIME_HOUR_GET(x)
+#define RTC_TIME_HOUR_SET(x) WLAN_RTC_TIME_HOUR_SET(x)
+#define RTC_TIME_MINUTE_MSB WLAN_RTC_TIME_MINUTE_MSB
+#define RTC_TIME_MINUTE_LSB WLAN_RTC_TIME_MINUTE_LSB
+#define RTC_TIME_MINUTE_MASK WLAN_RTC_TIME_MINUTE_MASK
+#define RTC_TIME_MINUTE_GET(x) WLAN_RTC_TIME_MINUTE_GET(x)
+#define RTC_TIME_MINUTE_SET(x) WLAN_RTC_TIME_MINUTE_SET(x)
+#define RTC_TIME_SECOND_MSB WLAN_RTC_TIME_SECOND_MSB
+#define RTC_TIME_SECOND_LSB WLAN_RTC_TIME_SECOND_LSB
+#define RTC_TIME_SECOND_MASK WLAN_RTC_TIME_SECOND_MASK
+#define RTC_TIME_SECOND_GET(x) WLAN_RTC_TIME_SECOND_GET(x)
+#define RTC_TIME_SECOND_SET(x) WLAN_RTC_TIME_SECOND_SET(x)
+#define RTC_DATE_ADDRESS WLAN_RTC_DATE_ADDRESS
+#define RTC_DATE_OFFSET WLAN_RTC_DATE_OFFSET
+#define RTC_DATE_YEAR_MSB WLAN_RTC_DATE_YEAR_MSB
+#define RTC_DATE_YEAR_LSB WLAN_RTC_DATE_YEAR_LSB
+#define RTC_DATE_YEAR_MASK WLAN_RTC_DATE_YEAR_MASK
+#define RTC_DATE_YEAR_GET(x) WLAN_RTC_DATE_YEAR_GET(x)
+#define RTC_DATE_YEAR_SET(x) WLAN_RTC_DATE_YEAR_SET(x)
+#define RTC_DATE_MONTH_MSB WLAN_RTC_DATE_MONTH_MSB
+#define RTC_DATE_MONTH_LSB WLAN_RTC_DATE_MONTH_LSB
+#define RTC_DATE_MONTH_MASK WLAN_RTC_DATE_MONTH_MASK
+#define RTC_DATE_MONTH_GET(x) WLAN_RTC_DATE_MONTH_GET(x)
+#define RTC_DATE_MONTH_SET(x) WLAN_RTC_DATE_MONTH_SET(x)
+#define RTC_DATE_MONTH_DAY_MSB WLAN_RTC_DATE_MONTH_DAY_MSB
+#define RTC_DATE_MONTH_DAY_LSB WLAN_RTC_DATE_MONTH_DAY_LSB
+#define RTC_DATE_MONTH_DAY_MASK WLAN_RTC_DATE_MONTH_DAY_MASK
+#define RTC_DATE_MONTH_DAY_GET(x) WLAN_RTC_DATE_MONTH_DAY_GET(x)
+#define RTC_DATE_MONTH_DAY_SET(x) WLAN_RTC_DATE_MONTH_DAY_SET(x)
+#define RTC_SET_TIME_ADDRESS WLAN_RTC_SET_TIME_ADDRESS
+#define RTC_SET_TIME_OFFSET WLAN_RTC_SET_TIME_OFFSET
+#define RTC_SET_TIME_WEEK_DAY_MSB WLAN_RTC_SET_TIME_WEEK_DAY_MSB
+#define RTC_SET_TIME_WEEK_DAY_LSB WLAN_RTC_SET_TIME_WEEK_DAY_LSB
+#define RTC_SET_TIME_WEEK_DAY_MASK WLAN_RTC_SET_TIME_WEEK_DAY_MASK
+#define RTC_SET_TIME_WEEK_DAY_GET(x) WLAN_RTC_SET_TIME_WEEK_DAY_GET(x)
+#define RTC_SET_TIME_WEEK_DAY_SET(x) WLAN_RTC_SET_TIME_WEEK_DAY_SET(x)
+#define RTC_SET_TIME_HOUR_MSB WLAN_RTC_SET_TIME_HOUR_MSB
+#define RTC_SET_TIME_HOUR_LSB WLAN_RTC_SET_TIME_HOUR_LSB
+#define RTC_SET_TIME_HOUR_MASK WLAN_RTC_SET_TIME_HOUR_MASK
+#define RTC_SET_TIME_HOUR_GET(x) WLAN_RTC_SET_TIME_HOUR_GET(x)
+#define RTC_SET_TIME_HOUR_SET(x) WLAN_RTC_SET_TIME_HOUR_SET(x)
+#define RTC_SET_TIME_MINUTE_MSB WLAN_RTC_SET_TIME_MINUTE_MSB
+#define RTC_SET_TIME_MINUTE_LSB WLAN_RTC_SET_TIME_MINUTE_LSB
+#define RTC_SET_TIME_MINUTE_MASK WLAN_RTC_SET_TIME_MINUTE_MASK
+#define RTC_SET_TIME_MINUTE_GET(x) WLAN_RTC_SET_TIME_MINUTE_GET(x)
+#define RTC_SET_TIME_MINUTE_SET(x) WLAN_RTC_SET_TIME_MINUTE_SET(x)
+#define RTC_SET_TIME_SECOND_MSB WLAN_RTC_SET_TIME_SECOND_MSB
+#define RTC_SET_TIME_SECOND_LSB WLAN_RTC_SET_TIME_SECOND_LSB
+#define RTC_SET_TIME_SECOND_MASK WLAN_RTC_SET_TIME_SECOND_MASK
+#define RTC_SET_TIME_SECOND_GET(x) WLAN_RTC_SET_TIME_SECOND_GET(x)
+#define RTC_SET_TIME_SECOND_SET(x) WLAN_RTC_SET_TIME_SECOND_SET(x)
+#define RTC_SET_DATE_ADDRESS WLAN_RTC_SET_DATE_ADDRESS
+#define RTC_SET_DATE_OFFSET WLAN_RTC_SET_DATE_OFFSET
+#define RTC_SET_DATE_YEAR_MSB WLAN_RTC_SET_DATE_YEAR_MSB
+#define RTC_SET_DATE_YEAR_LSB WLAN_RTC_SET_DATE_YEAR_LSB
+#define RTC_SET_DATE_YEAR_MASK WLAN_RTC_SET_DATE_YEAR_MASK
+#define RTC_SET_DATE_YEAR_GET(x) WLAN_RTC_SET_DATE_YEAR_GET(x)
+#define RTC_SET_DATE_YEAR_SET(x) WLAN_RTC_SET_DATE_YEAR_SET(x)
+#define RTC_SET_DATE_MONTH_MSB WLAN_RTC_SET_DATE_MONTH_MSB
+#define RTC_SET_DATE_MONTH_LSB WLAN_RTC_SET_DATE_MONTH_LSB
+#define RTC_SET_DATE_MONTH_MASK WLAN_RTC_SET_DATE_MONTH_MASK
+#define RTC_SET_DATE_MONTH_GET(x) WLAN_RTC_SET_DATE_MONTH_GET(x)
+#define RTC_SET_DATE_MONTH_SET(x) WLAN_RTC_SET_DATE_MONTH_SET(x)
+#define RTC_SET_DATE_MONTH_DAY_MSB WLAN_RTC_SET_DATE_MONTH_DAY_MSB
+#define RTC_SET_DATE_MONTH_DAY_LSB WLAN_RTC_SET_DATE_MONTH_DAY_LSB
+#define RTC_SET_DATE_MONTH_DAY_MASK WLAN_RTC_SET_DATE_MONTH_DAY_MASK
+#define RTC_SET_DATE_MONTH_DAY_GET(x) WLAN_RTC_SET_DATE_MONTH_DAY_GET(x)
+#define RTC_SET_DATE_MONTH_DAY_SET(x) WLAN_RTC_SET_DATE_MONTH_DAY_SET(x)
+#define RTC_SET_ALARM_ADDRESS WLAN_RTC_SET_ALARM_ADDRESS
+#define RTC_SET_ALARM_OFFSET WLAN_RTC_SET_ALARM_OFFSET
+#define RTC_SET_ALARM_HOUR_MSB WLAN_RTC_SET_ALARM_HOUR_MSB
+#define RTC_SET_ALARM_HOUR_LSB WLAN_RTC_SET_ALARM_HOUR_LSB
+#define RTC_SET_ALARM_HOUR_MASK WLAN_RTC_SET_ALARM_HOUR_MASK
+#define RTC_SET_ALARM_HOUR_GET(x) WLAN_RTC_SET_ALARM_HOUR_GET(x)
+#define RTC_SET_ALARM_HOUR_SET(x) WLAN_RTC_SET_ALARM_HOUR_SET(x)
+#define RTC_SET_ALARM_MINUTE_MSB WLAN_RTC_SET_ALARM_MINUTE_MSB
+#define RTC_SET_ALARM_MINUTE_LSB WLAN_RTC_SET_ALARM_MINUTE_LSB
+#define RTC_SET_ALARM_MINUTE_MASK WLAN_RTC_SET_ALARM_MINUTE_MASK
+#define RTC_SET_ALARM_MINUTE_GET(x) WLAN_RTC_SET_ALARM_MINUTE_GET(x)
+#define RTC_SET_ALARM_MINUTE_SET(x) WLAN_RTC_SET_ALARM_MINUTE_SET(x)
+#define RTC_SET_ALARM_SECOND_MSB WLAN_RTC_SET_ALARM_SECOND_MSB
+#define RTC_SET_ALARM_SECOND_LSB WLAN_RTC_SET_ALARM_SECOND_LSB
+#define RTC_SET_ALARM_SECOND_MASK WLAN_RTC_SET_ALARM_SECOND_MASK
+#define RTC_SET_ALARM_SECOND_GET(x) WLAN_RTC_SET_ALARM_SECOND_GET(x)
+#define RTC_SET_ALARM_SECOND_SET(x) WLAN_RTC_SET_ALARM_SECOND_SET(x)
+#define RTC_CONFIG_ADDRESS WLAN_RTC_CONFIG_ADDRESS
+#define RTC_CONFIG_OFFSET WLAN_RTC_CONFIG_OFFSET
+#define RTC_CONFIG_BCD_MSB WLAN_RTC_CONFIG_BCD_MSB
+#define RTC_CONFIG_BCD_LSB WLAN_RTC_CONFIG_BCD_LSB
+#define RTC_CONFIG_BCD_MASK WLAN_RTC_CONFIG_BCD_MASK
+#define RTC_CONFIG_BCD_GET(x) WLAN_RTC_CONFIG_BCD_GET(x)
+#define RTC_CONFIG_BCD_SET(x) WLAN_RTC_CONFIG_BCD_SET(x)
+#define RTC_CONFIG_TWELVE_HOUR_MSB WLAN_RTC_CONFIG_TWELVE_HOUR_MSB
+#define RTC_CONFIG_TWELVE_HOUR_LSB WLAN_RTC_CONFIG_TWELVE_HOUR_LSB
+#define RTC_CONFIG_TWELVE_HOUR_MASK WLAN_RTC_CONFIG_TWELVE_HOUR_MASK
+#define RTC_CONFIG_TWELVE_HOUR_GET(x) WLAN_RTC_CONFIG_TWELVE_HOUR_GET(x)
+#define RTC_CONFIG_TWELVE_HOUR_SET(x) WLAN_RTC_CONFIG_TWELVE_HOUR_SET(x)
+#define RTC_CONFIG_DSE_MSB WLAN_RTC_CONFIG_DSE_MSB
+#define RTC_CONFIG_DSE_LSB WLAN_RTC_CONFIG_DSE_LSB
+#define RTC_CONFIG_DSE_MASK WLAN_RTC_CONFIG_DSE_MASK
+#define RTC_CONFIG_DSE_GET(x) WLAN_RTC_CONFIG_DSE_GET(x)
+#define RTC_CONFIG_DSE_SET(x) WLAN_RTC_CONFIG_DSE_SET(x)
+#define RTC_ALARM_STATUS_ADDRESS WLAN_RTC_ALARM_STATUS_ADDRESS
+#define RTC_ALARM_STATUS_OFFSET WLAN_RTC_ALARM_STATUS_OFFSET
+#define RTC_ALARM_STATUS_ENABLE_MSB WLAN_RTC_ALARM_STATUS_ENABLE_MSB
+#define RTC_ALARM_STATUS_ENABLE_LSB WLAN_RTC_ALARM_STATUS_ENABLE_LSB
+#define RTC_ALARM_STATUS_ENABLE_MASK WLAN_RTC_ALARM_STATUS_ENABLE_MASK
+#define RTC_ALARM_STATUS_ENABLE_GET(x) WLAN_RTC_ALARM_STATUS_ENABLE_GET(x)
+#define RTC_ALARM_STATUS_ENABLE_SET(x) WLAN_RTC_ALARM_STATUS_ENABLE_SET(x)
+#define RTC_ALARM_STATUS_INTERRUPT_MSB WLAN_RTC_ALARM_STATUS_INTERRUPT_MSB
+#define RTC_ALARM_STATUS_INTERRUPT_LSB WLAN_RTC_ALARM_STATUS_INTERRUPT_LSB
+#define RTC_ALARM_STATUS_INTERRUPT_MASK WLAN_RTC_ALARM_STATUS_INTERRUPT_MASK
+#define RTC_ALARM_STATUS_INTERRUPT_GET(x) WLAN_RTC_ALARM_STATUS_INTERRUPT_GET(x)
+#define RTC_ALARM_STATUS_INTERRUPT_SET(x) WLAN_RTC_ALARM_STATUS_INTERRUPT_SET(x)
+#define UART_WAKEUP_ADDRESS WLAN_UART_WAKEUP_ADDRESS
+#define UART_WAKEUP_OFFSET WLAN_UART_WAKEUP_OFFSET
+#define UART_WAKEUP_ENABLE_MSB WLAN_UART_WAKEUP_ENABLE_MSB
+#define UART_WAKEUP_ENABLE_LSB WLAN_UART_WAKEUP_ENABLE_LSB
+#define UART_WAKEUP_ENABLE_MASK WLAN_UART_WAKEUP_ENABLE_MASK
+#define UART_WAKEUP_ENABLE_GET(x) WLAN_UART_WAKEUP_ENABLE_GET(x)
+#define UART_WAKEUP_ENABLE_SET(x) WLAN_UART_WAKEUP_ENABLE_SET(x)
+#define RESET_CAUSE_ADDRESS WLAN_RESET_CAUSE_ADDRESS
+#define RESET_CAUSE_OFFSET WLAN_RESET_CAUSE_OFFSET
+#define RESET_CAUSE_LAST_MSB WLAN_RESET_CAUSE_LAST_MSB
+#define RESET_CAUSE_LAST_LSB WLAN_RESET_CAUSE_LAST_LSB
+#define RESET_CAUSE_LAST_MASK WLAN_RESET_CAUSE_LAST_MASK
+#define RESET_CAUSE_LAST_GET(x) WLAN_RESET_CAUSE_LAST_GET(x)
+#define RESET_CAUSE_LAST_SET(x) WLAN_RESET_CAUSE_LAST_SET(x)
+#define SYSTEM_SLEEP_ADDRESS WLAN_SYSTEM_SLEEP_ADDRESS
+#define SYSTEM_SLEEP_OFFSET WLAN_SYSTEM_SLEEP_OFFSET
+#define SYSTEM_SLEEP_HOST_IF_MSB WLAN_SYSTEM_SLEEP_HOST_IF_MSB
+#define SYSTEM_SLEEP_HOST_IF_LSB WLAN_SYSTEM_SLEEP_HOST_IF_LSB
+#define SYSTEM_SLEEP_HOST_IF_MASK WLAN_SYSTEM_SLEEP_HOST_IF_MASK
+#define SYSTEM_SLEEP_HOST_IF_GET(x) WLAN_SYSTEM_SLEEP_HOST_IF_GET(x)
+#define SYSTEM_SLEEP_HOST_IF_SET(x) WLAN_SYSTEM_SLEEP_HOST_IF_SET(x)
+#define SYSTEM_SLEEP_MBOX_MSB WLAN_SYSTEM_SLEEP_MBOX_MSB
+#define SYSTEM_SLEEP_MBOX_LSB WLAN_SYSTEM_SLEEP_MBOX_LSB
+#define SYSTEM_SLEEP_MBOX_MASK WLAN_SYSTEM_SLEEP_MBOX_MASK
+#define SYSTEM_SLEEP_MBOX_GET(x) WLAN_SYSTEM_SLEEP_MBOX_GET(x)
+#define SYSTEM_SLEEP_MBOX_SET(x) WLAN_SYSTEM_SLEEP_MBOX_SET(x)
+#define SYSTEM_SLEEP_MAC_IF_MSB WLAN_SYSTEM_SLEEP_MAC_IF_MSB
+#define SYSTEM_SLEEP_MAC_IF_LSB WLAN_SYSTEM_SLEEP_MAC_IF_LSB
+#define SYSTEM_SLEEP_MAC_IF_MASK WLAN_SYSTEM_SLEEP_MAC_IF_MASK
+#define SYSTEM_SLEEP_MAC_IF_GET(x) WLAN_SYSTEM_SLEEP_MAC_IF_GET(x)
+#define SYSTEM_SLEEP_MAC_IF_SET(x) WLAN_SYSTEM_SLEEP_MAC_IF_SET(x)
+#define SYSTEM_SLEEP_LIGHT_MSB WLAN_SYSTEM_SLEEP_LIGHT_MSB
+#define SYSTEM_SLEEP_LIGHT_LSB WLAN_SYSTEM_SLEEP_LIGHT_LSB
+#define SYSTEM_SLEEP_LIGHT_MASK WLAN_SYSTEM_SLEEP_LIGHT_MASK
+#define SYSTEM_SLEEP_LIGHT_GET(x) WLAN_SYSTEM_SLEEP_LIGHT_GET(x)
+#define SYSTEM_SLEEP_LIGHT_SET(x) WLAN_SYSTEM_SLEEP_LIGHT_SET(x)
+#define SYSTEM_SLEEP_DISABLE_MSB WLAN_SYSTEM_SLEEP_DISABLE_MSB
+#define SYSTEM_SLEEP_DISABLE_LSB WLAN_SYSTEM_SLEEP_DISABLE_LSB
+#define SYSTEM_SLEEP_DISABLE_MASK WLAN_SYSTEM_SLEEP_DISABLE_MASK
+#define SYSTEM_SLEEP_DISABLE_GET(x) WLAN_SYSTEM_SLEEP_DISABLE_GET(x)
+#define SYSTEM_SLEEP_DISABLE_SET(x) WLAN_SYSTEM_SLEEP_DISABLE_SET(x)
+#define SDIO_WRAPPER_ADDRESS WLAN_SDIO_WRAPPER_ADDRESS
+#define SDIO_WRAPPER_OFFSET WLAN_SDIO_WRAPPER_OFFSET
+#define SDIO_WRAPPER_SLEEP_MSB WLAN_SDIO_WRAPPER_SLEEP_MSB
+#define SDIO_WRAPPER_SLEEP_LSB WLAN_SDIO_WRAPPER_SLEEP_LSB
+#define SDIO_WRAPPER_SLEEP_MASK WLAN_SDIO_WRAPPER_SLEEP_MASK
+#define SDIO_WRAPPER_SLEEP_GET(x) WLAN_SDIO_WRAPPER_SLEEP_GET(x)
+#define SDIO_WRAPPER_SLEEP_SET(x) WLAN_SDIO_WRAPPER_SLEEP_SET(x)
+#define SDIO_WRAPPER_WAKEUP_MSB WLAN_SDIO_WRAPPER_WAKEUP_MSB
+#define SDIO_WRAPPER_WAKEUP_LSB WLAN_SDIO_WRAPPER_WAKEUP_LSB
+#define SDIO_WRAPPER_WAKEUP_MASK WLAN_SDIO_WRAPPER_WAKEUP_MASK
+#define SDIO_WRAPPER_WAKEUP_GET(x) WLAN_SDIO_WRAPPER_WAKEUP_GET(x)
+#define SDIO_WRAPPER_WAKEUP_SET(x) WLAN_SDIO_WRAPPER_WAKEUP_SET(x)
+#define SDIO_WRAPPER_SOC_ON_MSB WLAN_SDIO_WRAPPER_SOC_ON_MSB
+#define SDIO_WRAPPER_SOC_ON_LSB WLAN_SDIO_WRAPPER_SOC_ON_LSB
+#define SDIO_WRAPPER_SOC_ON_MASK WLAN_SDIO_WRAPPER_SOC_ON_MASK
+#define SDIO_WRAPPER_SOC_ON_GET(x) WLAN_SDIO_WRAPPER_SOC_ON_GET(x)
+#define SDIO_WRAPPER_SOC_ON_SET(x) WLAN_SDIO_WRAPPER_SOC_ON_SET(x)
+#define SDIO_WRAPPER_ON_MSB WLAN_SDIO_WRAPPER_ON_MSB
+#define SDIO_WRAPPER_ON_LSB WLAN_SDIO_WRAPPER_ON_LSB
+#define SDIO_WRAPPER_ON_MASK WLAN_SDIO_WRAPPER_ON_MASK
+#define SDIO_WRAPPER_ON_GET(x) WLAN_SDIO_WRAPPER_ON_GET(x)
+#define SDIO_WRAPPER_ON_SET(x) WLAN_SDIO_WRAPPER_ON_SET(x)
+#define MAC_SLEEP_CONTROL_ADDRESS WLAN_MAC_SLEEP_CONTROL_ADDRESS
+#define MAC_SLEEP_CONTROL_OFFSET WLAN_MAC_SLEEP_CONTROL_OFFSET
+#define MAC_SLEEP_CONTROL_ENABLE_MSB WLAN_MAC_SLEEP_CONTROL_ENABLE_MSB
+#define MAC_SLEEP_CONTROL_ENABLE_LSB WLAN_MAC_SLEEP_CONTROL_ENABLE_LSB
+#define MAC_SLEEP_CONTROL_ENABLE_MASK WLAN_MAC_SLEEP_CONTROL_ENABLE_MASK
+#define MAC_SLEEP_CONTROL_ENABLE_GET(x) WLAN_MAC_SLEEP_CONTROL_ENABLE_GET(x)
+#define MAC_SLEEP_CONTROL_ENABLE_SET(x) WLAN_MAC_SLEEP_CONTROL_ENABLE_SET(x)
+#define KEEP_AWAKE_ADDRESS WLAN_KEEP_AWAKE_ADDRESS
+#define KEEP_AWAKE_OFFSET WLAN_KEEP_AWAKE_OFFSET
+#define KEEP_AWAKE_COUNT_MSB WLAN_KEEP_AWAKE_COUNT_MSB
+#define KEEP_AWAKE_COUNT_LSB WLAN_KEEP_AWAKE_COUNT_LSB
+#define KEEP_AWAKE_COUNT_MASK WLAN_KEEP_AWAKE_COUNT_MASK
+#define KEEP_AWAKE_COUNT_GET(x) WLAN_KEEP_AWAKE_COUNT_GET(x)
+#define KEEP_AWAKE_COUNT_SET(x) WLAN_KEEP_AWAKE_COUNT_SET(x)
+#define LPO_CAL_TIME_ADDRESS WLAN_LPO_CAL_TIME_ADDRESS
+#define LPO_CAL_TIME_OFFSET WLAN_LPO_CAL_TIME_OFFSET
+#define LPO_CAL_TIME_LENGTH_MSB WLAN_LPO_CAL_TIME_LENGTH_MSB
+#define LPO_CAL_TIME_LENGTH_LSB WLAN_LPO_CAL_TIME_LENGTH_LSB
+#define LPO_CAL_TIME_LENGTH_MASK WLAN_LPO_CAL_TIME_LENGTH_MASK
+#define LPO_CAL_TIME_LENGTH_GET(x) WLAN_LPO_CAL_TIME_LENGTH_GET(x)
+#define LPO_CAL_TIME_LENGTH_SET(x) WLAN_LPO_CAL_TIME_LENGTH_SET(x)
+#define LPO_INIT_DIVIDEND_INT_ADDRESS WLAN_LPO_INIT_DIVIDEND_INT_ADDRESS
+#define LPO_INIT_DIVIDEND_INT_OFFSET WLAN_LPO_INIT_DIVIDEND_INT_OFFSET
+#define LPO_INIT_DIVIDEND_INT_VALUE_MSB WLAN_LPO_INIT_DIVIDEND_INT_VALUE_MSB
+#define LPO_INIT_DIVIDEND_INT_VALUE_LSB WLAN_LPO_INIT_DIVIDEND_INT_VALUE_LSB
+#define LPO_INIT_DIVIDEND_INT_VALUE_MASK WLAN_LPO_INIT_DIVIDEND_INT_VALUE_MASK
+#define LPO_INIT_DIVIDEND_INT_VALUE_GET(x) WLAN_LPO_INIT_DIVIDEND_INT_VALUE_GET(x)
+#define LPO_INIT_DIVIDEND_INT_VALUE_SET(x) WLAN_LPO_INIT_DIVIDEND_INT_VALUE_SET(x)
+#define LPO_INIT_DIVIDEND_FRACTION_ADDRESS WLAN_LPO_INIT_DIVIDEND_FRACTION_ADDRESS
+#define LPO_INIT_DIVIDEND_FRACTION_OFFSET WLAN_LPO_INIT_DIVIDEND_FRACTION_OFFSET
+#define LPO_INIT_DIVIDEND_FRACTION_VALUE_MSB WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_MSB
+#define LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB
+#define LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK
+#define LPO_INIT_DIVIDEND_FRACTION_VALUE_GET(x) WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_GET(x)
+#define LPO_INIT_DIVIDEND_FRACTION_VALUE_SET(x) WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_SET(x)
+#define LPO_CAL_ADDRESS WLAN_LPO_CAL_ADDRESS
+#define LPO_CAL_OFFSET WLAN_LPO_CAL_OFFSET
+#define LPO_CAL_ENABLE_MSB WLAN_LPO_CAL_ENABLE_MSB
+#define LPO_CAL_ENABLE_LSB WLAN_LPO_CAL_ENABLE_LSB
+#define LPO_CAL_ENABLE_MASK WLAN_LPO_CAL_ENABLE_MASK
+#define LPO_CAL_ENABLE_GET(x) WLAN_LPO_CAL_ENABLE_GET(x)
+#define LPO_CAL_ENABLE_SET(x) WLAN_LPO_CAL_ENABLE_SET(x)
+#define LPO_CAL_COUNT_MSB WLAN_LPO_CAL_COUNT_MSB
+#define LPO_CAL_COUNT_LSB WLAN_LPO_CAL_COUNT_LSB
+#define LPO_CAL_COUNT_MASK WLAN_LPO_CAL_COUNT_MASK
+#define LPO_CAL_COUNT_GET(x) WLAN_LPO_CAL_COUNT_GET(x)
+#define LPO_CAL_COUNT_SET(x) WLAN_LPO_CAL_COUNT_SET(x)
+#define LPO_CAL_TEST_CONTROL_ADDRESS WLAN_LPO_CAL_TEST_CONTROL_ADDRESS
+#define LPO_CAL_TEST_CONTROL_OFFSET WLAN_LPO_CAL_TEST_CONTROL_OFFSET
+#define LPO_CAL_TEST_CONTROL_ENABLE_MSB WLAN_LPO_CAL_TEST_CONTROL_ENABLE_MSB
+#define LPO_CAL_TEST_CONTROL_ENABLE_LSB WLAN_LPO_CAL_TEST_CONTROL_ENABLE_LSB
+#define LPO_CAL_TEST_CONTROL_ENABLE_MASK WLAN_LPO_CAL_TEST_CONTROL_ENABLE_MASK
+#define LPO_CAL_TEST_CONTROL_ENABLE_GET(x) WLAN_LPO_CAL_TEST_CONTROL_ENABLE_GET(x)
+#define LPO_CAL_TEST_CONTROL_ENABLE_SET(x) WLAN_LPO_CAL_TEST_CONTROL_ENABLE_SET(x)
+#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_MSB WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_MSB
+#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB
+#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK
+#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_GET(x) WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_GET(x)
+#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_SET(x) WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_SET(x)
+#define LPO_CAL_TEST_STATUS_ADDRESS WLAN_LPO_CAL_TEST_STATUS_ADDRESS
+#define LPO_CAL_TEST_STATUS_OFFSET WLAN_LPO_CAL_TEST_STATUS_OFFSET
+#define LPO_CAL_TEST_STATUS_READY_MSB WLAN_LPO_CAL_TEST_STATUS_READY_MSB
+#define LPO_CAL_TEST_STATUS_READY_LSB WLAN_LPO_CAL_TEST_STATUS_READY_LSB
+#define LPO_CAL_TEST_STATUS_READY_MASK WLAN_LPO_CAL_TEST_STATUS_READY_MASK
+#define LPO_CAL_TEST_STATUS_READY_GET(x) WLAN_LPO_CAL_TEST_STATUS_READY_GET(x)
+#define LPO_CAL_TEST_STATUS_READY_SET(x) WLAN_LPO_CAL_TEST_STATUS_READY_SET(x)
+#define LPO_CAL_TEST_STATUS_COUNT_MSB WLAN_LPO_CAL_TEST_STATUS_COUNT_MSB
+#define LPO_CAL_TEST_STATUS_COUNT_LSB WLAN_LPO_CAL_TEST_STATUS_COUNT_LSB
+#define LPO_CAL_TEST_STATUS_COUNT_MASK WLAN_LPO_CAL_TEST_STATUS_COUNT_MASK
+#define LPO_CAL_TEST_STATUS_COUNT_GET(x) WLAN_LPO_CAL_TEST_STATUS_COUNT_GET(x)
+#define LPO_CAL_TEST_STATUS_COUNT_SET(x) WLAN_LPO_CAL_TEST_STATUS_COUNT_SET(x)
+#define CHIP_ID_ADDRESS WLAN_CHIP_ID_ADDRESS
+#define CHIP_ID_OFFSET WLAN_CHIP_ID_OFFSET
+#define CHIP_ID_DEVICE_ID_MSB WLAN_CHIP_ID_DEVICE_ID_MSB
+#define CHIP_ID_DEVICE_ID_LSB WLAN_CHIP_ID_DEVICE_ID_LSB
+#define CHIP_ID_DEVICE_ID_MASK WLAN_CHIP_ID_DEVICE_ID_MASK
+#define CHIP_ID_DEVICE_ID_GET(x) WLAN_CHIP_ID_DEVICE_ID_GET(x)
+#define CHIP_ID_DEVICE_ID_SET(x) WLAN_CHIP_ID_DEVICE_ID_SET(x)
+#define CHIP_ID_CONFIG_ID_MSB WLAN_CHIP_ID_CONFIG_ID_MSB
+#define CHIP_ID_CONFIG_ID_LSB WLAN_CHIP_ID_CONFIG_ID_LSB
+#define CHIP_ID_CONFIG_ID_MASK WLAN_CHIP_ID_CONFIG_ID_MASK
+#define CHIP_ID_CONFIG_ID_GET(x) WLAN_CHIP_ID_CONFIG_ID_GET(x)
+#define CHIP_ID_CONFIG_ID_SET(x) WLAN_CHIP_ID_CONFIG_ID_SET(x)
+#define CHIP_ID_VERSION_ID_MSB WLAN_CHIP_ID_VERSION_ID_MSB
+#define CHIP_ID_VERSION_ID_LSB WLAN_CHIP_ID_VERSION_ID_LSB
+#define CHIP_ID_VERSION_ID_MASK WLAN_CHIP_ID_VERSION_ID_MASK
+#define CHIP_ID_VERSION_ID_GET(x) WLAN_CHIP_ID_VERSION_ID_GET(x)
+#define CHIP_ID_VERSION_ID_SET(x) WLAN_CHIP_ID_VERSION_ID_SET(x)
+#define DERIVED_RTC_CLK_ADDRESS WLAN_DERIVED_RTC_CLK_ADDRESS
+#define DERIVED_RTC_CLK_OFFSET WLAN_DERIVED_RTC_CLK_OFFSET
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MSB WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MSB
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_GET(x) WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_GET(x)
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_SET(x) WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_SET(x)
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_MSB WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_MSB
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_GET(x) WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_GET(x)
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_SET(x) WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_SET(x)
+#define DERIVED_RTC_CLK_FORCE_MSB WLAN_DERIVED_RTC_CLK_FORCE_MSB
+#define DERIVED_RTC_CLK_FORCE_LSB WLAN_DERIVED_RTC_CLK_FORCE_LSB
+#define DERIVED_RTC_CLK_FORCE_MASK WLAN_DERIVED_RTC_CLK_FORCE_MASK
+#define DERIVED_RTC_CLK_FORCE_GET(x) WLAN_DERIVED_RTC_CLK_FORCE_GET(x)
+#define DERIVED_RTC_CLK_FORCE_SET(x) WLAN_DERIVED_RTC_CLK_FORCE_SET(x)
+#define DERIVED_RTC_CLK_PERIOD_MSB WLAN_DERIVED_RTC_CLK_PERIOD_MSB
+#define DERIVED_RTC_CLK_PERIOD_LSB WLAN_DERIVED_RTC_CLK_PERIOD_LSB
+#define DERIVED_RTC_CLK_PERIOD_MASK WLAN_DERIVED_RTC_CLK_PERIOD_MASK
+#define DERIVED_RTC_CLK_PERIOD_GET(x) WLAN_DERIVED_RTC_CLK_PERIOD_GET(x)
+#define DERIVED_RTC_CLK_PERIOD_SET(x) WLAN_DERIVED_RTC_CLK_PERIOD_SET(x)
+#define POWER_REG_ADDRESS WLAN_POWER_REG_ADDRESS
+#define POWER_REG_OFFSET WLAN_POWER_REG_OFFSET
+#define POWER_REG_SLEEP_MAKE_N_BREAK_EN_MSB WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_MSB
+#define POWER_REG_SLEEP_MAKE_N_BREAK_EN_LSB WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_LSB
+#define POWER_REG_SLEEP_MAKE_N_BREAK_EN_MASK WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_MASK
+#define POWER_REG_SLEEP_MAKE_N_BREAK_EN_GET(x) WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_GET(x)
+#define POWER_REG_SLEEP_MAKE_N_BREAK_EN_SET(x) WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_SET(x)
+#define POWER_REG_DEBUG_EN_MSB WLAN_POWER_REG_DEBUG_EN_MSB
+#define POWER_REG_DEBUG_EN_LSB WLAN_POWER_REG_DEBUG_EN_LSB
+#define POWER_REG_DEBUG_EN_MASK WLAN_POWER_REG_DEBUG_EN_MASK
+#define POWER_REG_DEBUG_EN_GET(x) WLAN_POWER_REG_DEBUG_EN_GET(x)
+#define POWER_REG_DEBUG_EN_SET(x) WLAN_POWER_REG_DEBUG_EN_SET(x)
+#define POWER_REG_WLAN_BB_PWD_EN_MSB WLAN_POWER_REG_WLAN_BB_PWD_EN_MSB
+#define POWER_REG_WLAN_BB_PWD_EN_LSB WLAN_POWER_REG_WLAN_BB_PWD_EN_LSB
+#define POWER_REG_WLAN_BB_PWD_EN_MASK WLAN_POWER_REG_WLAN_BB_PWD_EN_MASK
+#define POWER_REG_WLAN_BB_PWD_EN_GET(x) WLAN_POWER_REG_WLAN_BB_PWD_EN_GET(x)
+#define POWER_REG_WLAN_BB_PWD_EN_SET(x) WLAN_POWER_REG_WLAN_BB_PWD_EN_SET(x)
+#define POWER_REG_WLAN_MAC_PWD_EN_MSB WLAN_POWER_REG_WLAN_MAC_PWD_EN_MSB
+#define POWER_REG_WLAN_MAC_PWD_EN_LSB WLAN_POWER_REG_WLAN_MAC_PWD_EN_LSB
+#define POWER_REG_WLAN_MAC_PWD_EN_MASK WLAN_POWER_REG_WLAN_MAC_PWD_EN_MASK
+#define POWER_REG_WLAN_MAC_PWD_EN_GET(x) WLAN_POWER_REG_WLAN_MAC_PWD_EN_GET(x)
+#define POWER_REG_WLAN_MAC_PWD_EN_SET(x) WLAN_POWER_REG_WLAN_MAC_PWD_EN_SET(x)
+#define POWER_REG_VLVL_MSB WLAN_POWER_REG_VLVL_MSB
+#define POWER_REG_VLVL_LSB WLAN_POWER_REG_VLVL_LSB
+#define POWER_REG_VLVL_MASK WLAN_POWER_REG_VLVL_MASK
+#define POWER_REG_VLVL_GET(x) WLAN_POWER_REG_VLVL_GET(x)
+#define POWER_REG_VLVL_SET(x) WLAN_POWER_REG_VLVL_SET(x)
+#define POWER_REG_CPU_INT_ENABLE_MSB WLAN_POWER_REG_CPU_INT_ENABLE_MSB
+#define POWER_REG_CPU_INT_ENABLE_LSB WLAN_POWER_REG_CPU_INT_ENABLE_LSB
+#define POWER_REG_CPU_INT_ENABLE_MASK WLAN_POWER_REG_CPU_INT_ENABLE_MASK
+#define POWER_REG_CPU_INT_ENABLE_GET(x) WLAN_POWER_REG_CPU_INT_ENABLE_GET(x)
+#define POWER_REG_CPU_INT_ENABLE_SET(x) WLAN_POWER_REG_CPU_INT_ENABLE_SET(x)
+#define POWER_REG_WLAN_ISO_DIS_MSB WLAN_POWER_REG_WLAN_ISO_DIS_MSB
+#define POWER_REG_WLAN_ISO_DIS_LSB WLAN_POWER_REG_WLAN_ISO_DIS_LSB
+#define POWER_REG_WLAN_ISO_DIS_MASK WLAN_POWER_REG_WLAN_ISO_DIS_MASK
+#define POWER_REG_WLAN_ISO_DIS_GET(x) WLAN_POWER_REG_WLAN_ISO_DIS_GET(x)
+#define POWER_REG_WLAN_ISO_DIS_SET(x) WLAN_POWER_REG_WLAN_ISO_DIS_SET(x)
+#define POWER_REG_WLAN_ISO_CNTL_MSB WLAN_POWER_REG_WLAN_ISO_CNTL_MSB
+#define POWER_REG_WLAN_ISO_CNTL_LSB WLAN_POWER_REG_WLAN_ISO_CNTL_LSB
+#define POWER_REG_WLAN_ISO_CNTL_MASK WLAN_POWER_REG_WLAN_ISO_CNTL_MASK
+#define POWER_REG_WLAN_ISO_CNTL_GET(x) WLAN_POWER_REG_WLAN_ISO_CNTL_GET(x)
+#define POWER_REG_WLAN_ISO_CNTL_SET(x) WLAN_POWER_REG_WLAN_ISO_CNTL_SET(x)
+#define POWER_REG_RADIO_PWD_EN_MSB WLAN_POWER_REG_RADIO_PWD_EN_MSB
+#define POWER_REG_RADIO_PWD_EN_LSB WLAN_POWER_REG_RADIO_PWD_EN_LSB
+#define POWER_REG_RADIO_PWD_EN_MASK WLAN_POWER_REG_RADIO_PWD_EN_MASK
+#define POWER_REG_RADIO_PWD_EN_GET(x) WLAN_POWER_REG_RADIO_PWD_EN_GET(x)
+#define POWER_REG_RADIO_PWD_EN_SET(x) WLAN_POWER_REG_RADIO_PWD_EN_SET(x)
+#define POWER_REG_SOC_ISO_EN_MSB WLAN_POWER_REG_SOC_ISO_EN_MSB
+#define POWER_REG_SOC_ISO_EN_LSB WLAN_POWER_REG_SOC_ISO_EN_LSB
+#define POWER_REG_SOC_ISO_EN_MASK WLAN_POWER_REG_SOC_ISO_EN_MASK
+#define POWER_REG_SOC_ISO_EN_GET(x) WLAN_POWER_REG_SOC_ISO_EN_GET(x)
+#define POWER_REG_SOC_ISO_EN_SET(x) WLAN_POWER_REG_SOC_ISO_EN_SET(x)
+#define POWER_REG_WLAN_ISO_EN_MSB WLAN_POWER_REG_WLAN_ISO_EN_MSB
+#define POWER_REG_WLAN_ISO_EN_LSB WLAN_POWER_REG_WLAN_ISO_EN_LSB
+#define POWER_REG_WLAN_ISO_EN_MASK WLAN_POWER_REG_WLAN_ISO_EN_MASK
+#define POWER_REG_WLAN_ISO_EN_GET(x) WLAN_POWER_REG_WLAN_ISO_EN_GET(x)
+#define POWER_REG_WLAN_ISO_EN_SET(x) WLAN_POWER_REG_WLAN_ISO_EN_SET(x)
+#define POWER_REG_WLAN_PWD_EN_MSB WLAN_POWER_REG_WLAN_PWD_EN_MSB
+#define POWER_REG_WLAN_PWD_EN_LSB WLAN_POWER_REG_WLAN_PWD_EN_LSB
+#define POWER_REG_WLAN_PWD_EN_MASK WLAN_POWER_REG_WLAN_PWD_EN_MASK
+#define POWER_REG_WLAN_PWD_EN_GET(x) WLAN_POWER_REG_WLAN_PWD_EN_GET(x)
+#define POWER_REG_WLAN_PWD_EN_SET(x) WLAN_POWER_REG_WLAN_PWD_EN_SET(x)
+#define POWER_REG_POWER_EN_MSB WLAN_POWER_REG_POWER_EN_MSB
+#define POWER_REG_POWER_EN_LSB WLAN_POWER_REG_POWER_EN_LSB
+#define POWER_REG_POWER_EN_MASK WLAN_POWER_REG_POWER_EN_MASK
+#define POWER_REG_POWER_EN_GET(x) WLAN_POWER_REG_POWER_EN_GET(x)
+#define POWER_REG_POWER_EN_SET(x) WLAN_POWER_REG_POWER_EN_SET(x)
+#define CORE_CLK_CTRL_ADDRESS WLAN_CORE_CLK_CTRL_ADDRESS
+#define CORE_CLK_CTRL_OFFSET WLAN_CORE_CLK_CTRL_OFFSET
+#define CORE_CLK_CTRL_DIV_MSB WLAN_CORE_CLK_CTRL_DIV_MSB
+#define CORE_CLK_CTRL_DIV_LSB WLAN_CORE_CLK_CTRL_DIV_LSB
+#define CORE_CLK_CTRL_DIV_MASK WLAN_CORE_CLK_CTRL_DIV_MASK
+#define CORE_CLK_CTRL_DIV_GET(x) WLAN_CORE_CLK_CTRL_DIV_GET(x)
+#define CORE_CLK_CTRL_DIV_SET(x) WLAN_CORE_CLK_CTRL_DIV_SET(x)
+#define GPIO_WAKEUP_CONTROL_ADDRESS WLAN_GPIO_WAKEUP_CONTROL_ADDRESS
+#define GPIO_WAKEUP_CONTROL_OFFSET WLAN_GPIO_WAKEUP_CONTROL_OFFSET
+#define GPIO_WAKEUP_CONTROL_ENABLE_MSB WLAN_GPIO_WAKEUP_CONTROL_ENABLE_MSB
+#define GPIO_WAKEUP_CONTROL_ENABLE_LSB WLAN_GPIO_WAKEUP_CONTROL_ENABLE_LSB
+#define GPIO_WAKEUP_CONTROL_ENABLE_MASK WLAN_GPIO_WAKEUP_CONTROL_ENABLE_MASK
+#define GPIO_WAKEUP_CONTROL_ENABLE_GET(x) WLAN_GPIO_WAKEUP_CONTROL_ENABLE_GET(x)
+#define GPIO_WAKEUP_CONTROL_ENABLE_SET(x) WLAN_GPIO_WAKEUP_CONTROL_ENABLE_SET(x)
+
+
+#endif
+#endif
+
+
+
diff --git a/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/rtc_wlan_reg.h b/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/rtc_wlan_reg.h
new file mode 100644
index 00000000000..abf87265005
--- /dev/null
+++ b/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/rtc_wlan_reg.h
@@ -0,0 +1,2065 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _RTC_WLAN_REG_REG_H_
+#define _RTC_WLAN_REG_REG_H_
+
+#define WLAN_RESET_CONTROL_ADDRESS               0x00000000
+#define WLAN_RESET_CONTROL_OFFSET                0x00000000
+#define WLAN_RESET_CONTROL_DEBUG_UART_RST_MSB    14
+#define WLAN_RESET_CONTROL_DEBUG_UART_RST_LSB    14
+#define WLAN_RESET_CONTROL_DEBUG_UART_RST_MASK   0x00004000
+#define WLAN_RESET_CONTROL_DEBUG_UART_RST_GET(x) (((x) & WLAN_RESET_CONTROL_DEBUG_UART_RST_MASK) >> WLAN_RESET_CONTROL_DEBUG_UART_RST_LSB)
+#define WLAN_RESET_CONTROL_DEBUG_UART_RST_SET(x) (((x) << WLAN_RESET_CONTROL_DEBUG_UART_RST_LSB) & WLAN_RESET_CONTROL_DEBUG_UART_RST_MASK)
+#define WLAN_RESET_CONTROL_BB_COLD_RST_MSB       13
+#define WLAN_RESET_CONTROL_BB_COLD_RST_LSB       13
+#define WLAN_RESET_CONTROL_BB_COLD_RST_MASK      0x00002000
+#define WLAN_RESET_CONTROL_BB_COLD_RST_GET(x)    (((x) & WLAN_RESET_CONTROL_BB_COLD_RST_MASK) >> WLAN_RESET_CONTROL_BB_COLD_RST_LSB)
+#define WLAN_RESET_CONTROL_BB_COLD_RST_SET(x)    (((x) << WLAN_RESET_CONTROL_BB_COLD_RST_LSB) & WLAN_RESET_CONTROL_BB_COLD_RST_MASK)
+#define WLAN_RESET_CONTROL_BB_WARM_RST_MSB       12
+#define WLAN_RESET_CONTROL_BB_WARM_RST_LSB       12
+#define WLAN_RESET_CONTROL_BB_WARM_RST_MASK      0x00001000
+#define WLAN_RESET_CONTROL_BB_WARM_RST_GET(x)    (((x) & WLAN_RESET_CONTROL_BB_WARM_RST_MASK) >> WLAN_RESET_CONTROL_BB_WARM_RST_LSB)
+#define WLAN_RESET_CONTROL_BB_WARM_RST_SET(x)    (((x) << WLAN_RESET_CONTROL_BB_WARM_RST_LSB) & WLAN_RESET_CONTROL_BB_WARM_RST_MASK)
+#define WLAN_RESET_CONTROL_CPU_INIT_RESET_MSB    11
+#define WLAN_RESET_CONTROL_CPU_INIT_RESET_LSB    11
+#define WLAN_RESET_CONTROL_CPU_INIT_RESET_MASK   0x00000800
+#define WLAN_RESET_CONTROL_CPU_INIT_RESET_GET(x) (((x) & WLAN_RESET_CONTROL_CPU_INIT_RESET_MASK) >> WLAN_RESET_CONTROL_CPU_INIT_RESET_LSB)
+#define WLAN_RESET_CONTROL_CPU_INIT_RESET_SET(x) (((x) << WLAN_RESET_CONTROL_CPU_INIT_RESET_LSB) & WLAN_RESET_CONTROL_CPU_INIT_RESET_MASK)
+#define WLAN_RESET_CONTROL_VMC_REMAP_RESET_MSB   10
+#define WLAN_RESET_CONTROL_VMC_REMAP_RESET_LSB   10
+#define WLAN_RESET_CONTROL_VMC_REMAP_RESET_MASK  0x00000400
+#define WLAN_RESET_CONTROL_VMC_REMAP_RESET_GET(x) (((x) & WLAN_RESET_CONTROL_VMC_REMAP_RESET_MASK) >> WLAN_RESET_CONTROL_VMC_REMAP_RESET_LSB)
+#define WLAN_RESET_CONTROL_VMC_REMAP_RESET_SET(x) (((x) << WLAN_RESET_CONTROL_VMC_REMAP_RESET_LSB) & WLAN_RESET_CONTROL_VMC_REMAP_RESET_MASK)
+#define WLAN_RESET_CONTROL_RST_OUT_MSB           9
+#define WLAN_RESET_CONTROL_RST_OUT_LSB           9
+#define WLAN_RESET_CONTROL_RST_OUT_MASK          0x00000200
+#define WLAN_RESET_CONTROL_RST_OUT_GET(x)        (((x) & WLAN_RESET_CONTROL_RST_OUT_MASK) >> WLAN_RESET_CONTROL_RST_OUT_LSB)
+#define WLAN_RESET_CONTROL_RST_OUT_SET(x)        (((x) << WLAN_RESET_CONTROL_RST_OUT_LSB) & WLAN_RESET_CONTROL_RST_OUT_MASK)
+#define WLAN_RESET_CONTROL_COLD_RST_MSB          8
+#define WLAN_RESET_CONTROL_COLD_RST_LSB          8
+#define WLAN_RESET_CONTROL_COLD_RST_MASK         0x00000100
+#define WLAN_RESET_CONTROL_COLD_RST_GET(x)       (((x) & WLAN_RESET_CONTROL_COLD_RST_MASK) >> WLAN_RESET_CONTROL_COLD_RST_LSB)
+#define WLAN_RESET_CONTROL_COLD_RST_SET(x)       (((x) << WLAN_RESET_CONTROL_COLD_RST_LSB) & WLAN_RESET_CONTROL_COLD_RST_MASK)
+#define WLAN_RESET_CONTROL_WARM_RST_MSB          7
+#define WLAN_RESET_CONTROL_WARM_RST_LSB          7
+#define WLAN_RESET_CONTROL_WARM_RST_MASK         0x00000080
+#define WLAN_RESET_CONTROL_WARM_RST_GET(x)       (((x) & WLAN_RESET_CONTROL_WARM_RST_MASK) >> WLAN_RESET_CONTROL_WARM_RST_LSB)
+#define WLAN_RESET_CONTROL_WARM_RST_SET(x)       (((x) << WLAN_RESET_CONTROL_WARM_RST_LSB) & WLAN_RESET_CONTROL_WARM_RST_MASK)
+#define WLAN_RESET_CONTROL_CPU_WARM_RST_MSB      6
+#define WLAN_RESET_CONTROL_CPU_WARM_RST_LSB      6
+#define WLAN_RESET_CONTROL_CPU_WARM_RST_MASK     0x00000040
+#define WLAN_RESET_CONTROL_CPU_WARM_RST_GET(x)   (((x) & WLAN_RESET_CONTROL_CPU_WARM_RST_MASK) >> WLAN_RESET_CONTROL_CPU_WARM_RST_LSB)
+#define WLAN_RESET_CONTROL_CPU_WARM_RST_SET(x)   (((x) << WLAN_RESET_CONTROL_CPU_WARM_RST_LSB) & WLAN_RESET_CONTROL_CPU_WARM_RST_MASK)
+#define WLAN_RESET_CONTROL_MAC_COLD_RST_MSB      5
+#define WLAN_RESET_CONTROL_MAC_COLD_RST_LSB      5
+#define WLAN_RESET_CONTROL_MAC_COLD_RST_MASK     0x00000020
+#define WLAN_RESET_CONTROL_MAC_COLD_RST_GET(x)   (((x) & WLAN_RESET_CONTROL_MAC_COLD_RST_MASK) >> WLAN_RESET_CONTROL_MAC_COLD_RST_LSB)
+#define WLAN_RESET_CONTROL_MAC_COLD_RST_SET(x)   (((x) << WLAN_RESET_CONTROL_MAC_COLD_RST_LSB) & WLAN_RESET_CONTROL_MAC_COLD_RST_MASK)
+#define WLAN_RESET_CONTROL_MAC_WARM_RST_MSB      4
+#define WLAN_RESET_CONTROL_MAC_WARM_RST_LSB      4
+#define WLAN_RESET_CONTROL_MAC_WARM_RST_MASK     0x00000010
+#define WLAN_RESET_CONTROL_MAC_WARM_RST_GET(x)   (((x) & WLAN_RESET_CONTROL_MAC_WARM_RST_MASK) >> WLAN_RESET_CONTROL_MAC_WARM_RST_LSB)
+#define WLAN_RESET_CONTROL_MAC_WARM_RST_SET(x)   (((x) << WLAN_RESET_CONTROL_MAC_WARM_RST_LSB) & WLAN_RESET_CONTROL_MAC_WARM_RST_MASK)
+#define WLAN_RESET_CONTROL_MBOX_RST_MSB          2
+#define WLAN_RESET_CONTROL_MBOX_RST_LSB          2
+#define WLAN_RESET_CONTROL_MBOX_RST_MASK         0x00000004
+#define WLAN_RESET_CONTROL_MBOX_RST_GET(x)       (((x) & WLAN_RESET_CONTROL_MBOX_RST_MASK) >> WLAN_RESET_CONTROL_MBOX_RST_LSB)
+#define WLAN_RESET_CONTROL_MBOX_RST_SET(x)       (((x) << WLAN_RESET_CONTROL_MBOX_RST_LSB) & WLAN_RESET_CONTROL_MBOX_RST_MASK)
+#define WLAN_RESET_CONTROL_UART_RST_MSB          1
+#define WLAN_RESET_CONTROL_UART_RST_LSB          1
+#define WLAN_RESET_CONTROL_UART_RST_MASK         0x00000002
+#define WLAN_RESET_CONTROL_UART_RST_GET(x)       (((x) & WLAN_RESET_CONTROL_UART_RST_MASK) >> WLAN_RESET_CONTROL_UART_RST_LSB)
+#define WLAN_RESET_CONTROL_UART_RST_SET(x)       (((x) << WLAN_RESET_CONTROL_UART_RST_LSB) & WLAN_RESET_CONTROL_UART_RST_MASK)
+#define WLAN_RESET_CONTROL_SI0_RST_MSB           0
+#define WLAN_RESET_CONTROL_SI0_RST_LSB           0
+#define WLAN_RESET_CONTROL_SI0_RST_MASK          0x00000001
+#define WLAN_RESET_CONTROL_SI0_RST_GET(x)        (((x) & WLAN_RESET_CONTROL_SI0_RST_MASK) >> WLAN_RESET_CONTROL_SI0_RST_LSB)
+#define WLAN_RESET_CONTROL_SI0_RST_SET(x)        (((x) << WLAN_RESET_CONTROL_SI0_RST_LSB) & WLAN_RESET_CONTROL_SI0_RST_MASK)
+
+#define WLAN_XTAL_CONTROL_ADDRESS                0x00000004
+#define WLAN_XTAL_CONTROL_OFFSET                 0x00000004
+#define WLAN_XTAL_CONTROL_TCXO_MSB               0
+#define WLAN_XTAL_CONTROL_TCXO_LSB               0
+#define WLAN_XTAL_CONTROL_TCXO_MASK              0x00000001
+#define WLAN_XTAL_CONTROL_TCXO_GET(x)            (((x) & WLAN_XTAL_CONTROL_TCXO_MASK) >> WLAN_XTAL_CONTROL_TCXO_LSB)
+#define WLAN_XTAL_CONTROL_TCXO_SET(x)            (((x) << WLAN_XTAL_CONTROL_TCXO_LSB) & WLAN_XTAL_CONTROL_TCXO_MASK)
+
+#define WLAN_TCXO_DETECT_ADDRESS                 0x00000008
+#define WLAN_TCXO_DETECT_OFFSET                  0x00000008
+#define WLAN_TCXO_DETECT_PRESENT_MSB             0
+#define WLAN_TCXO_DETECT_PRESENT_LSB             0
+#define WLAN_TCXO_DETECT_PRESENT_MASK            0x00000001
+#define WLAN_TCXO_DETECT_PRESENT_GET(x)          (((x) & WLAN_TCXO_DETECT_PRESENT_MASK) >> WLAN_TCXO_DETECT_PRESENT_LSB)
+#define WLAN_TCXO_DETECT_PRESENT_SET(x)          (((x) << WLAN_TCXO_DETECT_PRESENT_LSB) & WLAN_TCXO_DETECT_PRESENT_MASK)
+
+#define WLAN_XTAL_TEST_ADDRESS                   0x0000000c
+#define WLAN_XTAL_TEST_OFFSET                    0x0000000c
+#define WLAN_XTAL_TEST_NOTCXODET_MSB             0
+#define WLAN_XTAL_TEST_NOTCXODET_LSB             0
+#define WLAN_XTAL_TEST_NOTCXODET_MASK            0x00000001
+#define WLAN_XTAL_TEST_NOTCXODET_GET(x)          (((x) & WLAN_XTAL_TEST_NOTCXODET_MASK) >> WLAN_XTAL_TEST_NOTCXODET_LSB)
+#define WLAN_XTAL_TEST_NOTCXODET_SET(x)          (((x) << WLAN_XTAL_TEST_NOTCXODET_LSB) & WLAN_XTAL_TEST_NOTCXODET_MASK)
+
+#define WLAN_QUADRATURE_ADDRESS                  0x00000010
+#define WLAN_QUADRATURE_OFFSET                   0x00000010
+#define WLAN_QUADRATURE_ADC_MSB                  7
+#define WLAN_QUADRATURE_ADC_LSB                  4
+#define WLAN_QUADRATURE_ADC_MASK                 0x000000f0
+#define WLAN_QUADRATURE_ADC_GET(x)               (((x) & WLAN_QUADRATURE_ADC_MASK) >> WLAN_QUADRATURE_ADC_LSB)
+#define WLAN_QUADRATURE_ADC_SET(x)               (((x) << WLAN_QUADRATURE_ADC_LSB) & WLAN_QUADRATURE_ADC_MASK)
+#define WLAN_QUADRATURE_SEL_MSB                  2
+#define WLAN_QUADRATURE_SEL_LSB                  2
+#define WLAN_QUADRATURE_SEL_MASK                 0x00000004
+#define WLAN_QUADRATURE_SEL_GET(x)               (((x) & WLAN_QUADRATURE_SEL_MASK) >> WLAN_QUADRATURE_SEL_LSB)
+#define WLAN_QUADRATURE_SEL_SET(x)               (((x) << WLAN_QUADRATURE_SEL_LSB) & WLAN_QUADRATURE_SEL_MASK)
+#define WLAN_QUADRATURE_DAC_MSB                  1
+#define WLAN_QUADRATURE_DAC_LSB                  0
+#define WLAN_QUADRATURE_DAC_MASK                 0x00000003
+#define WLAN_QUADRATURE_DAC_GET(x)               (((x) & WLAN_QUADRATURE_DAC_MASK) >> WLAN_QUADRATURE_DAC_LSB)
+#define WLAN_QUADRATURE_DAC_SET(x)               (((x) << WLAN_QUADRATURE_DAC_LSB) & WLAN_QUADRATURE_DAC_MASK)
+
+#define WLAN_PLL_CONTROL_ADDRESS                 0x00000014
+#define WLAN_PLL_CONTROL_OFFSET                  0x00000014
+#define WLAN_PLL_CONTROL_DIG_TEST_CLK_MSB        20
+#define WLAN_PLL_CONTROL_DIG_TEST_CLK_LSB        20
+#define WLAN_PLL_CONTROL_DIG_TEST_CLK_MASK       0x00100000
+#define WLAN_PLL_CONTROL_DIG_TEST_CLK_GET(x)     (((x) & WLAN_PLL_CONTROL_DIG_TEST_CLK_MASK) >> WLAN_PLL_CONTROL_DIG_TEST_CLK_LSB)
+#define WLAN_PLL_CONTROL_DIG_TEST_CLK_SET(x)     (((x) << WLAN_PLL_CONTROL_DIG_TEST_CLK_LSB) & WLAN_PLL_CONTROL_DIG_TEST_CLK_MASK)
+#define WLAN_PLL_CONTROL_MAC_OVERRIDE_MSB        19
+#define WLAN_PLL_CONTROL_MAC_OVERRIDE_LSB        19
+#define WLAN_PLL_CONTROL_MAC_OVERRIDE_MASK       0x00080000
+#define WLAN_PLL_CONTROL_MAC_OVERRIDE_GET(x)     (((x) & WLAN_PLL_CONTROL_MAC_OVERRIDE_MASK) >> WLAN_PLL_CONTROL_MAC_OVERRIDE_LSB)
+#define WLAN_PLL_CONTROL_MAC_OVERRIDE_SET(x)     (((x) << WLAN_PLL_CONTROL_MAC_OVERRIDE_LSB) & WLAN_PLL_CONTROL_MAC_OVERRIDE_MASK)
+#define WLAN_PLL_CONTROL_NOPWD_MSB               18
+#define WLAN_PLL_CONTROL_NOPWD_LSB               18
+#define WLAN_PLL_CONTROL_NOPWD_MASK              0x00040000
+#define WLAN_PLL_CONTROL_NOPWD_GET(x)            (((x) & WLAN_PLL_CONTROL_NOPWD_MASK) >> WLAN_PLL_CONTROL_NOPWD_LSB)
+#define WLAN_PLL_CONTROL_NOPWD_SET(x)            (((x) << WLAN_PLL_CONTROL_NOPWD_LSB) & WLAN_PLL_CONTROL_NOPWD_MASK)
+#define WLAN_PLL_CONTROL_UPDATING_MSB            17
+#define WLAN_PLL_CONTROL_UPDATING_LSB            17
+#define WLAN_PLL_CONTROL_UPDATING_MASK           0x00020000
+#define WLAN_PLL_CONTROL_UPDATING_GET(x)         (((x) & WLAN_PLL_CONTROL_UPDATING_MASK) >> WLAN_PLL_CONTROL_UPDATING_LSB)
+#define WLAN_PLL_CONTROL_UPDATING_SET(x)         (((x) << WLAN_PLL_CONTROL_UPDATING_LSB) & WLAN_PLL_CONTROL_UPDATING_MASK)
+#define WLAN_PLL_CONTROL_BYPASS_MSB              16
+#define WLAN_PLL_CONTROL_BYPASS_LSB              16
+#define WLAN_PLL_CONTROL_BYPASS_MASK             0x00010000
+#define WLAN_PLL_CONTROL_BYPASS_GET(x)           (((x) & WLAN_PLL_CONTROL_BYPASS_MASK) >> WLAN_PLL_CONTROL_BYPASS_LSB)
+#define WLAN_PLL_CONTROL_BYPASS_SET(x)           (((x) << WLAN_PLL_CONTROL_BYPASS_LSB) & WLAN_PLL_CONTROL_BYPASS_MASK)
+#define WLAN_PLL_CONTROL_REFDIV_MSB              15
+#define WLAN_PLL_CONTROL_REFDIV_LSB              12
+#define WLAN_PLL_CONTROL_REFDIV_MASK             0x0000f000
+#define WLAN_PLL_CONTROL_REFDIV_GET(x)           (((x) & WLAN_PLL_CONTROL_REFDIV_MASK) >> WLAN_PLL_CONTROL_REFDIV_LSB)
+#define WLAN_PLL_CONTROL_REFDIV_SET(x)           (((x) << WLAN_PLL_CONTROL_REFDIV_LSB) & WLAN_PLL_CONTROL_REFDIV_MASK)
+#define WLAN_PLL_CONTROL_DIV_MSB                 9
+#define WLAN_PLL_CONTROL_DIV_LSB                 0
+#define WLAN_PLL_CONTROL_DIV_MASK                0x000003ff
+#define WLAN_PLL_CONTROL_DIV_GET(x)              (((x) & WLAN_PLL_CONTROL_DIV_MASK) >> WLAN_PLL_CONTROL_DIV_LSB)
+#define WLAN_PLL_CONTROL_DIV_SET(x)              (((x) << WLAN_PLL_CONTROL_DIV_LSB) & WLAN_PLL_CONTROL_DIV_MASK)
+
+#define WLAN_PLL_SETTLE_ADDRESS                  0x00000018
+#define WLAN_PLL_SETTLE_OFFSET                   0x00000018
+#define WLAN_PLL_SETTLE_TIME_MSB                 11
+#define WLAN_PLL_SETTLE_TIME_LSB                 0
+#define WLAN_PLL_SETTLE_TIME_MASK                0x00000fff
+#define WLAN_PLL_SETTLE_TIME_GET(x)              (((x) & WLAN_PLL_SETTLE_TIME_MASK) >> WLAN_PLL_SETTLE_TIME_LSB)
+#define WLAN_PLL_SETTLE_TIME_SET(x)              (((x) << WLAN_PLL_SETTLE_TIME_LSB) & WLAN_PLL_SETTLE_TIME_MASK)
+
+#define WLAN_XTAL_SETTLE_ADDRESS                 0x0000001c
+#define WLAN_XTAL_SETTLE_OFFSET                  0x0000001c
+#define WLAN_XTAL_SETTLE_TIME_MSB                7
+#define WLAN_XTAL_SETTLE_TIME_LSB                0
+#define WLAN_XTAL_SETTLE_TIME_MASK               0x000000ff
+#define WLAN_XTAL_SETTLE_TIME_GET(x)             (((x) & WLAN_XTAL_SETTLE_TIME_MASK) >> WLAN_XTAL_SETTLE_TIME_LSB)
+#define WLAN_XTAL_SETTLE_TIME_SET(x)             (((x) << WLAN_XTAL_SETTLE_TIME_LSB) & WLAN_XTAL_SETTLE_TIME_MASK)
+
+#define WLAN_CPU_CLOCK_ADDRESS                   0x00000020
+#define WLAN_CPU_CLOCK_OFFSET                    0x00000020
+#define WLAN_CPU_CLOCK_STANDARD_MSB              1
+#define WLAN_CPU_CLOCK_STANDARD_LSB              0
+#define WLAN_CPU_CLOCK_STANDARD_MASK             0x00000003
+#define WLAN_CPU_CLOCK_STANDARD_GET(x)           (((x) & WLAN_CPU_CLOCK_STANDARD_MASK) >> WLAN_CPU_CLOCK_STANDARD_LSB)
+#define WLAN_CPU_CLOCK_STANDARD_SET(x)           (((x) << WLAN_CPU_CLOCK_STANDARD_LSB) & WLAN_CPU_CLOCK_STANDARD_MASK)
+
+#define WLAN_CLOCK_OUT_ADDRESS                   0x00000024
+#define WLAN_CLOCK_OUT_OFFSET                    0x00000024
+#define WLAN_CLOCK_OUT_SELECT_MSB                3
+#define WLAN_CLOCK_OUT_SELECT_LSB                0
+#define WLAN_CLOCK_OUT_SELECT_MASK               0x0000000f
+#define WLAN_CLOCK_OUT_SELECT_GET(x)             (((x) & WLAN_CLOCK_OUT_SELECT_MASK) >> WLAN_CLOCK_OUT_SELECT_LSB)
+#define WLAN_CLOCK_OUT_SELECT_SET(x)             (((x) << WLAN_CLOCK_OUT_SELECT_LSB) & WLAN_CLOCK_OUT_SELECT_MASK)
+
+#define WLAN_CLOCK_CONTROL_ADDRESS               0x00000028
+#define WLAN_CLOCK_CONTROL_OFFSET                0x00000028
+#define WLAN_CLOCK_CONTROL_LF_CLK32_MSB          2
+#define WLAN_CLOCK_CONTROL_LF_CLK32_LSB          2
+#define WLAN_CLOCK_CONTROL_LF_CLK32_MASK         0x00000004
+#define WLAN_CLOCK_CONTROL_LF_CLK32_GET(x)       (((x) & WLAN_CLOCK_CONTROL_LF_CLK32_MASK) >> WLAN_CLOCK_CONTROL_LF_CLK32_LSB)
+#define WLAN_CLOCK_CONTROL_LF_CLK32_SET(x)       (((x) << WLAN_CLOCK_CONTROL_LF_CLK32_LSB) & WLAN_CLOCK_CONTROL_LF_CLK32_MASK)
+#define WLAN_CLOCK_CONTROL_SI0_CLK_MSB           0
+#define WLAN_CLOCK_CONTROL_SI0_CLK_LSB           0
+#define WLAN_CLOCK_CONTROL_SI0_CLK_MASK          0x00000001
+#define WLAN_CLOCK_CONTROL_SI0_CLK_GET(x)        (((x) & WLAN_CLOCK_CONTROL_SI0_CLK_MASK) >> WLAN_CLOCK_CONTROL_SI0_CLK_LSB)
+#define WLAN_CLOCK_CONTROL_SI0_CLK_SET(x)        (((x) << WLAN_CLOCK_CONTROL_SI0_CLK_LSB) & WLAN_CLOCK_CONTROL_SI0_CLK_MASK)
+
+#define WLAN_BIAS_OVERRIDE_ADDRESS               0x0000002c
+#define WLAN_BIAS_OVERRIDE_OFFSET                0x0000002c
+#define WLAN_BIAS_OVERRIDE_ON_MSB                0
+#define WLAN_BIAS_OVERRIDE_ON_LSB                0
+#define WLAN_BIAS_OVERRIDE_ON_MASK               0x00000001
+#define WLAN_BIAS_OVERRIDE_ON_GET(x)             (((x) & WLAN_BIAS_OVERRIDE_ON_MASK) >> WLAN_BIAS_OVERRIDE_ON_LSB)
+#define WLAN_BIAS_OVERRIDE_ON_SET(x)             (((x) << WLAN_BIAS_OVERRIDE_ON_LSB) & WLAN_BIAS_OVERRIDE_ON_MASK)
+
+#define WLAN_WDT_CONTROL_ADDRESS                 0x00000030
+#define WLAN_WDT_CONTROL_OFFSET                  0x00000030
+#define WLAN_WDT_CONTROL_ACTION_MSB              2
+#define WLAN_WDT_CONTROL_ACTION_LSB              0
+#define WLAN_WDT_CONTROL_ACTION_MASK             0x00000007
+#define WLAN_WDT_CONTROL_ACTION_GET(x)           (((x) & WLAN_WDT_CONTROL_ACTION_MASK) >> WLAN_WDT_CONTROL_ACTION_LSB)
+#define WLAN_WDT_CONTROL_ACTION_SET(x)           (((x) << WLAN_WDT_CONTROL_ACTION_LSB) & WLAN_WDT_CONTROL_ACTION_MASK)
+
+#define WLAN_WDT_STATUS_ADDRESS                  0x00000034
+#define WLAN_WDT_STATUS_OFFSET                   0x00000034
+#define WLAN_WDT_STATUS_INTERRUPT_MSB            0
+#define WLAN_WDT_STATUS_INTERRUPT_LSB            0
+#define WLAN_WDT_STATUS_INTERRUPT_MASK           0x00000001
+#define WLAN_WDT_STATUS_INTERRUPT_GET(x)         (((x) & WLAN_WDT_STATUS_INTERRUPT_MASK) >> WLAN_WDT_STATUS_INTERRUPT_LSB)
+#define WLAN_WDT_STATUS_INTERRUPT_SET(x)         (((x) << WLAN_WDT_STATUS_INTERRUPT_LSB) & WLAN_WDT_STATUS_INTERRUPT_MASK)
+
+#define WLAN_WDT_ADDRESS                         0x00000038
+#define WLAN_WDT_OFFSET                          0x00000038
+#define WLAN_WDT_TARGET_MSB                      21
+#define WLAN_WDT_TARGET_LSB                      0
+#define WLAN_WDT_TARGET_MASK                     0x003fffff
+#define WLAN_WDT_TARGET_GET(x)                   (((x) & WLAN_WDT_TARGET_MASK) >> WLAN_WDT_TARGET_LSB)
+#define WLAN_WDT_TARGET_SET(x)                   (((x) << WLAN_WDT_TARGET_LSB) & WLAN_WDT_TARGET_MASK)
+
+#define WLAN_WDT_COUNT_ADDRESS                   0x0000003c
+#define WLAN_WDT_COUNT_OFFSET                    0x0000003c
+#define WLAN_WDT_COUNT_VALUE_MSB                 21
+#define WLAN_WDT_COUNT_VALUE_LSB                 0
+#define WLAN_WDT_COUNT_VALUE_MASK                0x003fffff
+#define WLAN_WDT_COUNT_VALUE_GET(x)              (((x) & WLAN_WDT_COUNT_VALUE_MASK) >> WLAN_WDT_COUNT_VALUE_LSB)
+#define WLAN_WDT_COUNT_VALUE_SET(x)              (((x) << WLAN_WDT_COUNT_VALUE_LSB) & WLAN_WDT_COUNT_VALUE_MASK)
+
+#define WLAN_WDT_RESET_ADDRESS                   0x00000040
+#define WLAN_WDT_RESET_OFFSET                    0x00000040
+#define WLAN_WDT_RESET_VALUE_MSB                 0
+#define WLAN_WDT_RESET_VALUE_LSB                 0
+#define WLAN_WDT_RESET_VALUE_MASK                0x00000001
+#define WLAN_WDT_RESET_VALUE_GET(x)              (((x) & WLAN_WDT_RESET_VALUE_MASK) >> WLAN_WDT_RESET_VALUE_LSB)
+#define WLAN_WDT_RESET_VALUE_SET(x)              (((x) << WLAN_WDT_RESET_VALUE_LSB) & WLAN_WDT_RESET_VALUE_MASK)
+
+#define WLAN_INT_STATUS_ADDRESS                  0x00000044
+#define WLAN_INT_STATUS_OFFSET                   0x00000044
+#define WLAN_INT_STATUS_HCI_UART_MSB             21
+#define WLAN_INT_STATUS_HCI_UART_LSB             21
+#define WLAN_INT_STATUS_HCI_UART_MASK            0x00200000
+#define WLAN_INT_STATUS_HCI_UART_GET(x)          (((x) & WLAN_INT_STATUS_HCI_UART_MASK) >> WLAN_INT_STATUS_HCI_UART_LSB)
+#define WLAN_INT_STATUS_HCI_UART_SET(x)          (((x) << WLAN_INT_STATUS_HCI_UART_LSB) & WLAN_INT_STATUS_HCI_UART_MASK)
+#define WLAN_INT_STATUS_THERM_MSB                20
+#define WLAN_INT_STATUS_THERM_LSB                20
+#define WLAN_INT_STATUS_THERM_MASK               0x00100000
+#define WLAN_INT_STATUS_THERM_GET(x)             (((x) & WLAN_INT_STATUS_THERM_MASK) >> WLAN_INT_STATUS_THERM_LSB)
+#define WLAN_INT_STATUS_THERM_SET(x)             (((x) << WLAN_INT_STATUS_THERM_LSB) & WLAN_INT_STATUS_THERM_MASK)
+#define WLAN_INT_STATUS_EFUSE_OVERWRITE_MSB      19
+#define WLAN_INT_STATUS_EFUSE_OVERWRITE_LSB      19
+#define WLAN_INT_STATUS_EFUSE_OVERWRITE_MASK     0x00080000
+#define WLAN_INT_STATUS_EFUSE_OVERWRITE_GET(x)   (((x) & WLAN_INT_STATUS_EFUSE_OVERWRITE_MASK) >> WLAN_INT_STATUS_EFUSE_OVERWRITE_LSB)
+#define WLAN_INT_STATUS_EFUSE_OVERWRITE_SET(x)   (((x) << WLAN_INT_STATUS_EFUSE_OVERWRITE_LSB) & WLAN_INT_STATUS_EFUSE_OVERWRITE_MASK)
+#define WLAN_INT_STATUS_UART_MBOX_MSB            18
+#define WLAN_INT_STATUS_UART_MBOX_LSB            18
+#define WLAN_INT_STATUS_UART_MBOX_MASK           0x00040000
+#define WLAN_INT_STATUS_UART_MBOX_GET(x)         (((x) & WLAN_INT_STATUS_UART_MBOX_MASK) >> WLAN_INT_STATUS_UART_MBOX_LSB)
+#define WLAN_INT_STATUS_UART_MBOX_SET(x)         (((x) << WLAN_INT_STATUS_UART_MBOX_LSB) & WLAN_INT_STATUS_UART_MBOX_MASK)
+#define WLAN_INT_STATUS_GENERIC_MBOX_MSB         17
+#define WLAN_INT_STATUS_GENERIC_MBOX_LSB         17
+#define WLAN_INT_STATUS_GENERIC_MBOX_MASK        0x00020000
+#define WLAN_INT_STATUS_GENERIC_MBOX_GET(x)      (((x) & WLAN_INT_STATUS_GENERIC_MBOX_MASK) >> WLAN_INT_STATUS_GENERIC_MBOX_LSB)
+#define WLAN_INT_STATUS_GENERIC_MBOX_SET(x)      (((x) << WLAN_INT_STATUS_GENERIC_MBOX_LSB) & WLAN_INT_STATUS_GENERIC_MBOX_MASK)
+#define WLAN_INT_STATUS_RDMA_MSB                 16
+#define WLAN_INT_STATUS_RDMA_LSB                 16
+#define WLAN_INT_STATUS_RDMA_MASK                0x00010000
+#define WLAN_INT_STATUS_RDMA_GET(x)              (((x) & WLAN_INT_STATUS_RDMA_MASK) >> WLAN_INT_STATUS_RDMA_LSB)
+#define WLAN_INT_STATUS_RDMA_SET(x)              (((x) << WLAN_INT_STATUS_RDMA_LSB) & WLAN_INT_STATUS_RDMA_MASK)
+#define WLAN_INT_STATUS_BTCOEX_MSB               15
+#define WLAN_INT_STATUS_BTCOEX_LSB               15
+#define WLAN_INT_STATUS_BTCOEX_MASK              0x00008000
+#define WLAN_INT_STATUS_BTCOEX_GET(x)            (((x) & WLAN_INT_STATUS_BTCOEX_MASK) >> WLAN_INT_STATUS_BTCOEX_LSB)
+#define WLAN_INT_STATUS_BTCOEX_SET(x)            (((x) << WLAN_INT_STATUS_BTCOEX_LSB) & WLAN_INT_STATUS_BTCOEX_MASK)
+#define WLAN_INT_STATUS_RTC_POWER_MSB            14
+#define WLAN_INT_STATUS_RTC_POWER_LSB            14
+#define WLAN_INT_STATUS_RTC_POWER_MASK           0x00004000
+#define WLAN_INT_STATUS_RTC_POWER_GET(x)         (((x) & WLAN_INT_STATUS_RTC_POWER_MASK) >> WLAN_INT_STATUS_RTC_POWER_LSB)
+#define WLAN_INT_STATUS_RTC_POWER_SET(x)         (((x) << WLAN_INT_STATUS_RTC_POWER_LSB) & WLAN_INT_STATUS_RTC_POWER_MASK)
+#define WLAN_INT_STATUS_MAC_MSB                  13
+#define WLAN_INT_STATUS_MAC_LSB                  13
+#define WLAN_INT_STATUS_MAC_MASK                 0x00002000
+#define WLAN_INT_STATUS_MAC_GET(x)               (((x) & WLAN_INT_STATUS_MAC_MASK) >> WLAN_INT_STATUS_MAC_LSB)
+#define WLAN_INT_STATUS_MAC_SET(x)               (((x) << WLAN_INT_STATUS_MAC_LSB) & WLAN_INT_STATUS_MAC_MASK)
+#define WLAN_INT_STATUS_MAILBOX_MSB              12
+#define WLAN_INT_STATUS_MAILBOX_LSB              12
+#define WLAN_INT_STATUS_MAILBOX_MASK             0x00001000
+#define WLAN_INT_STATUS_MAILBOX_GET(x)           (((x) & WLAN_INT_STATUS_MAILBOX_MASK) >> WLAN_INT_STATUS_MAILBOX_LSB)
+#define WLAN_INT_STATUS_MAILBOX_SET(x)           (((x) << WLAN_INT_STATUS_MAILBOX_LSB) & WLAN_INT_STATUS_MAILBOX_MASK)
+#define WLAN_INT_STATUS_RTC_ALARM_MSB            11
+#define WLAN_INT_STATUS_RTC_ALARM_LSB            11
+#define WLAN_INT_STATUS_RTC_ALARM_MASK           0x00000800
+#define WLAN_INT_STATUS_RTC_ALARM_GET(x)         (((x) & WLAN_INT_STATUS_RTC_ALARM_MASK) >> WLAN_INT_STATUS_RTC_ALARM_LSB)
+#define WLAN_INT_STATUS_RTC_ALARM_SET(x)         (((x) << WLAN_INT_STATUS_RTC_ALARM_LSB) & WLAN_INT_STATUS_RTC_ALARM_MASK)
+#define WLAN_INT_STATUS_HF_TIMER_MSB             10
+#define WLAN_INT_STATUS_HF_TIMER_LSB             10
+#define WLAN_INT_STATUS_HF_TIMER_MASK            0x00000400
+#define WLAN_INT_STATUS_HF_TIMER_GET(x)          (((x) & WLAN_INT_STATUS_HF_TIMER_MASK) >> WLAN_INT_STATUS_HF_TIMER_LSB)
+#define WLAN_INT_STATUS_HF_TIMER_SET(x)          (((x) << WLAN_INT_STATUS_HF_TIMER_LSB) & WLAN_INT_STATUS_HF_TIMER_MASK)
+#define WLAN_INT_STATUS_LF_TIMER3_MSB            9
+#define WLAN_INT_STATUS_LF_TIMER3_LSB            9
+#define WLAN_INT_STATUS_LF_TIMER3_MASK           0x00000200
+#define WLAN_INT_STATUS_LF_TIMER3_GET(x)         (((x) & WLAN_INT_STATUS_LF_TIMER3_MASK) >> WLAN_INT_STATUS_LF_TIMER3_LSB)
+#define WLAN_INT_STATUS_LF_TIMER3_SET(x)         (((x) << WLAN_INT_STATUS_LF_TIMER3_LSB) & WLAN_INT_STATUS_LF_TIMER3_MASK)
+#define WLAN_INT_STATUS_LF_TIMER2_MSB            8
+#define WLAN_INT_STATUS_LF_TIMER2_LSB            8
+#define WLAN_INT_STATUS_LF_TIMER2_MASK           0x00000100
+#define WLAN_INT_STATUS_LF_TIMER2_GET(x)         (((x) & WLAN_INT_STATUS_LF_TIMER2_MASK) >> WLAN_INT_STATUS_LF_TIMER2_LSB)
+#define WLAN_INT_STATUS_LF_TIMER2_SET(x)         (((x) << WLAN_INT_STATUS_LF_TIMER2_LSB) & WLAN_INT_STATUS_LF_TIMER2_MASK)
+#define WLAN_INT_STATUS_LF_TIMER1_MSB            7
+#define WLAN_INT_STATUS_LF_TIMER1_LSB            7
+#define WLAN_INT_STATUS_LF_TIMER1_MASK           0x00000080
+#define WLAN_INT_STATUS_LF_TIMER1_GET(x)         (((x) & WLAN_INT_STATUS_LF_TIMER1_MASK) >> WLAN_INT_STATUS_LF_TIMER1_LSB)
+#define WLAN_INT_STATUS_LF_TIMER1_SET(x)         (((x) << WLAN_INT_STATUS_LF_TIMER1_LSB) & WLAN_INT_STATUS_LF_TIMER1_MASK)
+#define WLAN_INT_STATUS_LF_TIMER0_MSB            6
+#define WLAN_INT_STATUS_LF_TIMER0_LSB            6
+#define WLAN_INT_STATUS_LF_TIMER0_MASK           0x00000040
+#define WLAN_INT_STATUS_LF_TIMER0_GET(x)         (((x) & WLAN_INT_STATUS_LF_TIMER0_MASK) >> WLAN_INT_STATUS_LF_TIMER0_LSB)
+#define WLAN_INT_STATUS_LF_TIMER0_SET(x)         (((x) << WLAN_INT_STATUS_LF_TIMER0_LSB) & WLAN_INT_STATUS_LF_TIMER0_MASK)
+#define WLAN_INT_STATUS_KEYPAD_MSB               5
+#define WLAN_INT_STATUS_KEYPAD_LSB               5
+#define WLAN_INT_STATUS_KEYPAD_MASK              0x00000020
+#define WLAN_INT_STATUS_KEYPAD_GET(x)            (((x) & WLAN_INT_STATUS_KEYPAD_MASK) >> WLAN_INT_STATUS_KEYPAD_LSB)
+#define WLAN_INT_STATUS_KEYPAD_SET(x)            (((x) << WLAN_INT_STATUS_KEYPAD_LSB) & WLAN_INT_STATUS_KEYPAD_MASK)
+#define WLAN_INT_STATUS_SI_MSB                   4
+#define WLAN_INT_STATUS_SI_LSB                   4
+#define WLAN_INT_STATUS_SI_MASK                  0x00000010
+#define WLAN_INT_STATUS_SI_GET(x)                (((x) & WLAN_INT_STATUS_SI_MASK) >> WLAN_INT_STATUS_SI_LSB)
+#define WLAN_INT_STATUS_SI_SET(x)                (((x) << WLAN_INT_STATUS_SI_LSB) & WLAN_INT_STATUS_SI_MASK)
+#define WLAN_INT_STATUS_GPIO_MSB                 3
+#define WLAN_INT_STATUS_GPIO_LSB                 3
+#define WLAN_INT_STATUS_GPIO_MASK                0x00000008
+#define WLAN_INT_STATUS_GPIO_GET(x)              (((x) & WLAN_INT_STATUS_GPIO_MASK) >> WLAN_INT_STATUS_GPIO_LSB)
+#define WLAN_INT_STATUS_GPIO_SET(x)              (((x) << WLAN_INT_STATUS_GPIO_LSB) & WLAN_INT_STATUS_GPIO_MASK)
+#define WLAN_INT_STATUS_UART_MSB                 2
+#define WLAN_INT_STATUS_UART_LSB                 2
+#define WLAN_INT_STATUS_UART_MASK                0x00000004
+#define WLAN_INT_STATUS_UART_GET(x)              (((x) & WLAN_INT_STATUS_UART_MASK) >> WLAN_INT_STATUS_UART_LSB)
+#define WLAN_INT_STATUS_UART_SET(x)              (((x) << WLAN_INT_STATUS_UART_LSB) & WLAN_INT_STATUS_UART_MASK)
+#define WLAN_INT_STATUS_ERROR_MSB                1
+#define WLAN_INT_STATUS_ERROR_LSB                1
+#define WLAN_INT_STATUS_ERROR_MASK               0x00000002
+#define WLAN_INT_STATUS_ERROR_GET(x)             (((x) & WLAN_INT_STATUS_ERROR_MASK) >> WLAN_INT_STATUS_ERROR_LSB)
+#define WLAN_INT_STATUS_ERROR_SET(x)             (((x) << WLAN_INT_STATUS_ERROR_LSB) & WLAN_INT_STATUS_ERROR_MASK)
+#define WLAN_INT_STATUS_WDT_INT_MSB              0
+#define WLAN_INT_STATUS_WDT_INT_LSB              0
+#define WLAN_INT_STATUS_WDT_INT_MASK             0x00000001
+#define WLAN_INT_STATUS_WDT_INT_GET(x)           (((x) & WLAN_INT_STATUS_WDT_INT_MASK) >> WLAN_INT_STATUS_WDT_INT_LSB)
+#define WLAN_INT_STATUS_WDT_INT_SET(x)           (((x) << WLAN_INT_STATUS_WDT_INT_LSB) & WLAN_INT_STATUS_WDT_INT_MASK)
+
+#define WLAN_LF_TIMER0_ADDRESS                   0x00000048
+#define WLAN_LF_TIMER0_OFFSET                    0x00000048
+#define WLAN_LF_TIMER0_TARGET_MSB                31
+#define WLAN_LF_TIMER0_TARGET_LSB                0
+#define WLAN_LF_TIMER0_TARGET_MASK               0xffffffff
+#define WLAN_LF_TIMER0_TARGET_GET(x)             (((x) & WLAN_LF_TIMER0_TARGET_MASK) >> WLAN_LF_TIMER0_TARGET_LSB)
+#define WLAN_LF_TIMER0_TARGET_SET(x)             (((x) << WLAN_LF_TIMER0_TARGET_LSB) & WLAN_LF_TIMER0_TARGET_MASK)
+
+#define WLAN_LF_TIMER_COUNT0_ADDRESS             0x0000004c
+#define WLAN_LF_TIMER_COUNT0_OFFSET              0x0000004c
+#define WLAN_LF_TIMER_COUNT0_VALUE_MSB           31
+#define WLAN_LF_TIMER_COUNT0_VALUE_LSB           0
+#define WLAN_LF_TIMER_COUNT0_VALUE_MASK          0xffffffff
+#define WLAN_LF_TIMER_COUNT0_VALUE_GET(x)        (((x) & WLAN_LF_TIMER_COUNT0_VALUE_MASK) >> WLAN_LF_TIMER_COUNT0_VALUE_LSB)
+#define WLAN_LF_TIMER_COUNT0_VALUE_SET(x)        (((x) << WLAN_LF_TIMER_COUNT0_VALUE_LSB) & WLAN_LF_TIMER_COUNT0_VALUE_MASK)
+
+#define WLAN_LF_TIMER_CONTROL0_ADDRESS           0x00000050
+#define WLAN_LF_TIMER_CONTROL0_OFFSET            0x00000050
+#define WLAN_LF_TIMER_CONTROL0_ENABLE_MSB        2
+#define WLAN_LF_TIMER_CONTROL0_ENABLE_LSB        2
+#define WLAN_LF_TIMER_CONTROL0_ENABLE_MASK       0x00000004
+#define WLAN_LF_TIMER_CONTROL0_ENABLE_GET(x)     (((x) & WLAN_LF_TIMER_CONTROL0_ENABLE_MASK) >> WLAN_LF_TIMER_CONTROL0_ENABLE_LSB)
+#define WLAN_LF_TIMER_CONTROL0_ENABLE_SET(x)     (((x) << WLAN_LF_TIMER_CONTROL0_ENABLE_LSB) & WLAN_LF_TIMER_CONTROL0_ENABLE_MASK)
+#define WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_MSB  1
+#define WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_LSB  1
+#define WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_MASK 0x00000002
+#define WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_GET(x) (((x) & WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_MASK) >> WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_LSB)
+#define WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_SET(x) (((x) << WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_LSB) & WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_MASK)
+#define WLAN_LF_TIMER_CONTROL0_RESET_MSB         0
+#define WLAN_LF_TIMER_CONTROL0_RESET_LSB         0
+#define WLAN_LF_TIMER_CONTROL0_RESET_MASK        0x00000001
+#define WLAN_LF_TIMER_CONTROL0_RESET_GET(x)      (((x) & WLAN_LF_TIMER_CONTROL0_RESET_MASK) >> WLAN_LF_TIMER_CONTROL0_RESET_LSB)
+#define WLAN_LF_TIMER_CONTROL0_RESET_SET(x)      (((x) << WLAN_LF_TIMER_CONTROL0_RESET_LSB) & WLAN_LF_TIMER_CONTROL0_RESET_MASK)
+
+#define WLAN_LF_TIMER_STATUS0_ADDRESS            0x00000054
+#define WLAN_LF_TIMER_STATUS0_OFFSET             0x00000054
+#define WLAN_LF_TIMER_STATUS0_INTERRUPT_MSB      0
+#define WLAN_LF_TIMER_STATUS0_INTERRUPT_LSB      0
+#define WLAN_LF_TIMER_STATUS0_INTERRUPT_MASK     0x00000001
+#define WLAN_LF_TIMER_STATUS0_INTERRUPT_GET(x)   (((x) & WLAN_LF_TIMER_STATUS0_INTERRUPT_MASK) >> WLAN_LF_TIMER_STATUS0_INTERRUPT_LSB)
+#define WLAN_LF_TIMER_STATUS0_INTERRUPT_SET(x)   (((x) << WLAN_LF_TIMER_STATUS0_INTERRUPT_LSB) & WLAN_LF_TIMER_STATUS0_INTERRUPT_MASK)
+
+#define WLAN_LF_TIMER1_ADDRESS                   0x00000058
+#define WLAN_LF_TIMER1_OFFSET                    0x00000058
+#define WLAN_LF_TIMER1_TARGET_MSB                31
+#define WLAN_LF_TIMER1_TARGET_LSB                0
+#define WLAN_LF_TIMER1_TARGET_MASK               0xffffffff
+#define WLAN_LF_TIMER1_TARGET_GET(x)             (((x) & WLAN_LF_TIMER1_TARGET_MASK) >> WLAN_LF_TIMER1_TARGET_LSB)
+#define WLAN_LF_TIMER1_TARGET_SET(x)             (((x) << WLAN_LF_TIMER1_TARGET_LSB) & WLAN_LF_TIMER1_TARGET_MASK)
+
+#define WLAN_LF_TIMER_COUNT1_ADDRESS             0x0000005c
+#define WLAN_LF_TIMER_COUNT1_OFFSET              0x0000005c
+#define WLAN_LF_TIMER_COUNT1_VALUE_MSB           31
+#define WLAN_LF_TIMER_COUNT1_VALUE_LSB           0
+#define WLAN_LF_TIMER_COUNT1_VALUE_MASK          0xffffffff
+#define WLAN_LF_TIMER_COUNT1_VALUE_GET(x)        (((x) & WLAN_LF_TIMER_COUNT1_VALUE_MASK) >> WLAN_LF_TIMER_COUNT1_VALUE_LSB)
+#define WLAN_LF_TIMER_COUNT1_VALUE_SET(x)        (((x) << WLAN_LF_TIMER_COUNT1_VALUE_LSB) & WLAN_LF_TIMER_COUNT1_VALUE_MASK)
+
+#define WLAN_LF_TIMER_CONTROL1_ADDRESS           0x00000060
+#define WLAN_LF_TIMER_CONTROL1_OFFSET            0x00000060
+#define WLAN_LF_TIMER_CONTROL1_ENABLE_MSB        2
+#define WLAN_LF_TIMER_CONTROL1_ENABLE_LSB        2
+#define WLAN_LF_TIMER_CONTROL1_ENABLE_MASK       0x00000004
+#define WLAN_LF_TIMER_CONTROL1_ENABLE_GET(x)     (((x) & WLAN_LF_TIMER_CONTROL1_ENABLE_MASK) >> WLAN_LF_TIMER_CONTROL1_ENABLE_LSB)
+#define WLAN_LF_TIMER_CONTROL1_ENABLE_SET(x)     (((x) << WLAN_LF_TIMER_CONTROL1_ENABLE_LSB) & WLAN_LF_TIMER_CONTROL1_ENABLE_MASK)
+#define WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_MSB  1
+#define WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_LSB  1
+#define WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_MASK 0x00000002
+#define WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_GET(x) (((x) & WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_MASK) >> WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_LSB)
+#define WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_SET(x) (((x) << WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_LSB) & WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_MASK)
+#define WLAN_LF_TIMER_CONTROL1_RESET_MSB         0
+#define WLAN_LF_TIMER_CONTROL1_RESET_LSB         0
+#define WLAN_LF_TIMER_CONTROL1_RESET_MASK        0x00000001
+#define WLAN_LF_TIMER_CONTROL1_RESET_GET(x)      (((x) & WLAN_LF_TIMER_CONTROL1_RESET_MASK) >> WLAN_LF_TIMER_CONTROL1_RESET_LSB)
+#define WLAN_LF_TIMER_CONTROL1_RESET_SET(x)      (((x) << WLAN_LF_TIMER_CONTROL1_RESET_LSB) & WLAN_LF_TIMER_CONTROL1_RESET_MASK)
+
+#define WLAN_LF_TIMER_STATUS1_ADDRESS            0x00000064
+#define WLAN_LF_TIMER_STATUS1_OFFSET             0x00000064
+#define WLAN_LF_TIMER_STATUS1_INTERRUPT_MSB      0
+#define WLAN_LF_TIMER_STATUS1_INTERRUPT_LSB      0
+#define WLAN_LF_TIMER_STATUS1_INTERRUPT_MASK     0x00000001
+#define WLAN_LF_TIMER_STATUS1_INTERRUPT_GET(x)   (((x) & WLAN_LF_TIMER_STATUS1_INTERRUPT_MASK) >> WLAN_LF_TIMER_STATUS1_INTERRUPT_LSB)
+#define WLAN_LF_TIMER_STATUS1_INTERRUPT_SET(x)   (((x) << WLAN_LF_TIMER_STATUS1_INTERRUPT_LSB) & WLAN_LF_TIMER_STATUS1_INTERRUPT_MASK)
+
+#define WLAN_LF_TIMER2_ADDRESS                   0x00000068
+#define WLAN_LF_TIMER2_OFFSET                    0x00000068
+#define WLAN_LF_TIMER2_TARGET_MSB                31
+#define WLAN_LF_TIMER2_TARGET_LSB                0
+#define WLAN_LF_TIMER2_TARGET_MASK               0xffffffff
+#define WLAN_LF_TIMER2_TARGET_GET(x)             (((x) & WLAN_LF_TIMER2_TARGET_MASK) >> WLAN_LF_TIMER2_TARGET_LSB)
+#define WLAN_LF_TIMER2_TARGET_SET(x)             (((x) << WLAN_LF_TIMER2_TARGET_LSB) & WLAN_LF_TIMER2_TARGET_MASK)
+
+#define WLAN_LF_TIMER_COUNT2_ADDRESS             0x0000006c
+#define WLAN_LF_TIMER_COUNT2_OFFSET              0x0000006c
+#define WLAN_LF_TIMER_COUNT2_VALUE_MSB           31
+#define WLAN_LF_TIMER_COUNT2_VALUE_LSB           0
+#define WLAN_LF_TIMER_COUNT2_VALUE_MASK          0xffffffff
+#define WLAN_LF_TIMER_COUNT2_VALUE_GET(x)        (((x) & WLAN_LF_TIMER_COUNT2_VALUE_MASK) >> WLAN_LF_TIMER_COUNT2_VALUE_LSB)
+#define WLAN_LF_TIMER_COUNT2_VALUE_SET(x)        (((x) << WLAN_LF_TIMER_COUNT2_VALUE_LSB) & WLAN_LF_TIMER_COUNT2_VALUE_MASK)
+
+#define WLAN_LF_TIMER_CONTROL2_ADDRESS           0x00000070
+#define WLAN_LF_TIMER_CONTROL2_OFFSET            0x00000070
+#define WLAN_LF_TIMER_CONTROL2_ENABLE_MSB        2
+#define WLAN_LF_TIMER_CONTROL2_ENABLE_LSB        2
+#define WLAN_LF_TIMER_CONTROL2_ENABLE_MASK       0x00000004
+#define WLAN_LF_TIMER_CONTROL2_ENABLE_GET(x)     (((x) & WLAN_LF_TIMER_CONTROL2_ENABLE_MASK) >> WLAN_LF_TIMER_CONTROL2_ENABLE_LSB)
+#define WLAN_LF_TIMER_CONTROL2_ENABLE_SET(x)     (((x) << WLAN_LF_TIMER_CONTROL2_ENABLE_LSB) & WLAN_LF_TIMER_CONTROL2_ENABLE_MASK)
+#define WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_MSB  1
+#define WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_LSB  1
+#define WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_MASK 0x00000002
+#define WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_GET(x) (((x) & WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_MASK) >> WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_LSB)
+#define WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_SET(x) (((x) << WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_LSB) & WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_MASK)
+#define WLAN_LF_TIMER_CONTROL2_RESET_MSB         0
+#define WLAN_LF_TIMER_CONTROL2_RESET_LSB         0
+#define WLAN_LF_TIMER_CONTROL2_RESET_MASK        0x00000001
+#define WLAN_LF_TIMER_CONTROL2_RESET_GET(x)      (((x) & WLAN_LF_TIMER_CONTROL2_RESET_MASK) >> WLAN_LF_TIMER_CONTROL2_RESET_LSB)
+#define WLAN_LF_TIMER_CONTROL2_RESET_SET(x)      (((x) << WLAN_LF_TIMER_CONTROL2_RESET_LSB) & WLAN_LF_TIMER_CONTROL2_RESET_MASK)
+
+#define WLAN_LF_TIMER_STATUS2_ADDRESS            0x00000074
+#define WLAN_LF_TIMER_STATUS2_OFFSET             0x00000074
+#define WLAN_LF_TIMER_STATUS2_INTERRUPT_MSB      0
+#define WLAN_LF_TIMER_STATUS2_INTERRUPT_LSB      0
+#define WLAN_LF_TIMER_STATUS2_INTERRUPT_MASK     0x00000001
+#define WLAN_LF_TIMER_STATUS2_INTERRUPT_GET(x)   (((x) & WLAN_LF_TIMER_STATUS2_INTERRUPT_MASK) >> WLAN_LF_TIMER_STATUS2_INTERRUPT_LSB)
+#define WLAN_LF_TIMER_STATUS2_INTERRUPT_SET(x)   (((x) << WLAN_LF_TIMER_STATUS2_INTERRUPT_LSB) & WLAN_LF_TIMER_STATUS2_INTERRUPT_MASK)
+
+#define WLAN_LF_TIMER3_ADDRESS                   0x00000078
+#define WLAN_LF_TIMER3_OFFSET                    0x00000078
+#define WLAN_LF_TIMER3_TARGET_MSB                31
+#define WLAN_LF_TIMER3_TARGET_LSB                0
+#define WLAN_LF_TIMER3_TARGET_MASK               0xffffffff
+#define WLAN_LF_TIMER3_TARGET_GET(x)             (((x) & WLAN_LF_TIMER3_TARGET_MASK) >> WLAN_LF_TIMER3_TARGET_LSB)
+#define WLAN_LF_TIMER3_TARGET_SET(x)             (((x) << WLAN_LF_TIMER3_TARGET_LSB) & WLAN_LF_TIMER3_TARGET_MASK)
+
+#define WLAN_LF_TIMER_COUNT3_ADDRESS             0x0000007c
+#define WLAN_LF_TIMER_COUNT3_OFFSET              0x0000007c
+#define WLAN_LF_TIMER_COUNT3_VALUE_MSB           31
+#define WLAN_LF_TIMER_COUNT3_VALUE_LSB           0
+#define WLAN_LF_TIMER_COUNT3_VALUE_MASK          0xffffffff
+#define WLAN_LF_TIMER_COUNT3_VALUE_GET(x)        (((x) & WLAN_LF_TIMER_COUNT3_VALUE_MASK) >> WLAN_LF_TIMER_COUNT3_VALUE_LSB)
+#define WLAN_LF_TIMER_COUNT3_VALUE_SET(x)        (((x) << WLAN_LF_TIMER_COUNT3_VALUE_LSB) & WLAN_LF_TIMER_COUNT3_VALUE_MASK)
+
+#define WLAN_LF_TIMER_CONTROL3_ADDRESS           0x00000080
+#define WLAN_LF_TIMER_CONTROL3_OFFSET            0x00000080
+#define WLAN_LF_TIMER_CONTROL3_ENABLE_MSB        2
+#define WLAN_LF_TIMER_CONTROL3_ENABLE_LSB        2
+#define WLAN_LF_TIMER_CONTROL3_ENABLE_MASK       0x00000004
+#define WLAN_LF_TIMER_CONTROL3_ENABLE_GET(x)     (((x) & WLAN_LF_TIMER_CONTROL3_ENABLE_MASK) >> WLAN_LF_TIMER_CONTROL3_ENABLE_LSB)
+#define WLAN_LF_TIMER_CONTROL3_ENABLE_SET(x)     (((x) << WLAN_LF_TIMER_CONTROL3_ENABLE_LSB) & WLAN_LF_TIMER_CONTROL3_ENABLE_MASK)
+#define WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_MSB  1
+#define WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_LSB  1
+#define WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_MASK 0x00000002
+#define WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_GET(x) (((x) & WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_MASK) >> WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_LSB)
+#define WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_SET(x) (((x) << WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_LSB) & WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_MASK)
+#define WLAN_LF_TIMER_CONTROL3_RESET_MSB         0
+#define WLAN_LF_TIMER_CONTROL3_RESET_LSB         0
+#define WLAN_LF_TIMER_CONTROL3_RESET_MASK        0x00000001
+#define WLAN_LF_TIMER_CONTROL3_RESET_GET(x)      (((x) & WLAN_LF_TIMER_CONTROL3_RESET_MASK) >> WLAN_LF_TIMER_CONTROL3_RESET_LSB)
+#define WLAN_LF_TIMER_CONTROL3_RESET_SET(x)      (((x) << WLAN_LF_TIMER_CONTROL3_RESET_LSB) & WLAN_LF_TIMER_CONTROL3_RESET_MASK)
+
+#define WLAN_LF_TIMER_STATUS3_ADDRESS            0x00000084
+#define WLAN_LF_TIMER_STATUS3_OFFSET             0x00000084
+#define WLAN_LF_TIMER_STATUS3_INTERRUPT_MSB      0
+#define WLAN_LF_TIMER_STATUS3_INTERRUPT_LSB      0
+#define WLAN_LF_TIMER_STATUS3_INTERRUPT_MASK     0x00000001
+#define WLAN_LF_TIMER_STATUS3_INTERRUPT_GET(x)   (((x) & WLAN_LF_TIMER_STATUS3_INTERRUPT_MASK) >> WLAN_LF_TIMER_STATUS3_INTERRUPT_LSB)
+#define WLAN_LF_TIMER_STATUS3_INTERRUPT_SET(x)   (((x) << WLAN_LF_TIMER_STATUS3_INTERRUPT_LSB) & WLAN_LF_TIMER_STATUS3_INTERRUPT_MASK)
+
+#define WLAN_HF_TIMER_ADDRESS                    0x00000088
+#define WLAN_HF_TIMER_OFFSET                     0x00000088
+#define WLAN_HF_TIMER_TARGET_MSB                 31
+#define WLAN_HF_TIMER_TARGET_LSB                 12
+#define WLAN_HF_TIMER_TARGET_MASK                0xfffff000
+#define WLAN_HF_TIMER_TARGET_GET(x)              (((x) & WLAN_HF_TIMER_TARGET_MASK) >> WLAN_HF_TIMER_TARGET_LSB)
+#define WLAN_HF_TIMER_TARGET_SET(x)              (((x) << WLAN_HF_TIMER_TARGET_LSB) & WLAN_HF_TIMER_TARGET_MASK)
+
+#define WLAN_HF_TIMER_COUNT_ADDRESS              0x0000008c
+#define WLAN_HF_TIMER_COUNT_OFFSET               0x0000008c
+#define WLAN_HF_TIMER_COUNT_VALUE_MSB            31
+#define WLAN_HF_TIMER_COUNT_VALUE_LSB            12
+#define WLAN_HF_TIMER_COUNT_VALUE_MASK           0xfffff000
+#define WLAN_HF_TIMER_COUNT_VALUE_GET(x)         (((x) & WLAN_HF_TIMER_COUNT_VALUE_MASK) >> WLAN_HF_TIMER_COUNT_VALUE_LSB)
+#define WLAN_HF_TIMER_COUNT_VALUE_SET(x)         (((x) << WLAN_HF_TIMER_COUNT_VALUE_LSB) & WLAN_HF_TIMER_COUNT_VALUE_MASK)
+
+#define WLAN_HF_LF_COUNT_ADDRESS                 0x00000090
+#define WLAN_HF_LF_COUNT_OFFSET                  0x00000090
+#define WLAN_HF_LF_COUNT_VALUE_MSB               31
+#define WLAN_HF_LF_COUNT_VALUE_LSB               0
+#define WLAN_HF_LF_COUNT_VALUE_MASK              0xffffffff
+#define WLAN_HF_LF_COUNT_VALUE_GET(x)            (((x) & WLAN_HF_LF_COUNT_VALUE_MASK) >> WLAN_HF_LF_COUNT_VALUE_LSB)
+#define WLAN_HF_LF_COUNT_VALUE_SET(x)            (((x) << WLAN_HF_LF_COUNT_VALUE_LSB) & WLAN_HF_LF_COUNT_VALUE_MASK)
+
+#define WLAN_HF_TIMER_CONTROL_ADDRESS            0x00000094
+#define WLAN_HF_TIMER_CONTROL_OFFSET             0x00000094
+#define WLAN_HF_TIMER_CONTROL_ENABLE_MSB         3
+#define WLAN_HF_TIMER_CONTROL_ENABLE_LSB         3
+#define WLAN_HF_TIMER_CONTROL_ENABLE_MASK        0x00000008
+#define WLAN_HF_TIMER_CONTROL_ENABLE_GET(x)      (((x) & WLAN_HF_TIMER_CONTROL_ENABLE_MASK) >> WLAN_HF_TIMER_CONTROL_ENABLE_LSB)
+#define WLAN_HF_TIMER_CONTROL_ENABLE_SET(x)      (((x) << WLAN_HF_TIMER_CONTROL_ENABLE_LSB) & WLAN_HF_TIMER_CONTROL_ENABLE_MASK)
+#define WLAN_HF_TIMER_CONTROL_ON_MSB             2
+#define WLAN_HF_TIMER_CONTROL_ON_LSB             2
+#define WLAN_HF_TIMER_CONTROL_ON_MASK            0x00000004
+#define WLAN_HF_TIMER_CONTROL_ON_GET(x)          (((x) & WLAN_HF_TIMER_CONTROL_ON_MASK) >> WLAN_HF_TIMER_CONTROL_ON_LSB)
+#define WLAN_HF_TIMER_CONTROL_ON_SET(x)          (((x) << WLAN_HF_TIMER_CONTROL_ON_LSB) & WLAN_HF_TIMER_CONTROL_ON_MASK)
+#define WLAN_HF_TIMER_CONTROL_AUTO_RESTART_MSB   1
+#define WLAN_HF_TIMER_CONTROL_AUTO_RESTART_LSB   1
+#define WLAN_HF_TIMER_CONTROL_AUTO_RESTART_MASK  0x00000002
+#define WLAN_HF_TIMER_CONTROL_AUTO_RESTART_GET(x) (((x) & WLAN_HF_TIMER_CONTROL_AUTO_RESTART_MASK) >> WLAN_HF_TIMER_CONTROL_AUTO_RESTART_LSB)
+#define WLAN_HF_TIMER_CONTROL_AUTO_RESTART_SET(x) (((x) << WLAN_HF_TIMER_CONTROL_AUTO_RESTART_LSB) & WLAN_HF_TIMER_CONTROL_AUTO_RESTART_MASK)
+#define WLAN_HF_TIMER_CONTROL_RESET_MSB          0
+#define WLAN_HF_TIMER_CONTROL_RESET_LSB          0
+#define WLAN_HF_TIMER_CONTROL_RESET_MASK         0x00000001
+#define WLAN_HF_TIMER_CONTROL_RESET_GET(x)       (((x) & WLAN_HF_TIMER_CONTROL_RESET_MASK) >> WLAN_HF_TIMER_CONTROL_RESET_LSB)
+#define WLAN_HF_TIMER_CONTROL_RESET_SET(x)       (((x) << WLAN_HF_TIMER_CONTROL_RESET_LSB) & WLAN_HF_TIMER_CONTROL_RESET_MASK)
+
+#define WLAN_HF_TIMER_STATUS_ADDRESS             0x00000098
+#define WLAN_HF_TIMER_STATUS_OFFSET              0x00000098
+#define WLAN_HF_TIMER_STATUS_INTERRUPT_MSB       0
+#define WLAN_HF_TIMER_STATUS_INTERRUPT_LSB       0
+#define WLAN_HF_TIMER_STATUS_INTERRUPT_MASK      0x00000001
+#define WLAN_HF_TIMER_STATUS_INTERRUPT_GET(x)    (((x) & WLAN_HF_TIMER_STATUS_INTERRUPT_MASK) >> WLAN_HF_TIMER_STATUS_INTERRUPT_LSB)
+#define WLAN_HF_TIMER_STATUS_INTERRUPT_SET(x)    (((x) << WLAN_HF_TIMER_STATUS_INTERRUPT_LSB) & WLAN_HF_TIMER_STATUS_INTERRUPT_MASK)
+
+#define WLAN_RTC_CONTROL_ADDRESS                 0x0000009c
+#define WLAN_RTC_CONTROL_OFFSET                  0x0000009c
+#define WLAN_RTC_CONTROL_ENABLE_MSB              2
+#define WLAN_RTC_CONTROL_ENABLE_LSB              2
+#define WLAN_RTC_CONTROL_ENABLE_MASK             0x00000004
+#define WLAN_RTC_CONTROL_ENABLE_GET(x)           (((x) & WLAN_RTC_CONTROL_ENABLE_MASK) >> WLAN_RTC_CONTROL_ENABLE_LSB)
+#define WLAN_RTC_CONTROL_ENABLE_SET(x)           (((x) << WLAN_RTC_CONTROL_ENABLE_LSB) & WLAN_RTC_CONTROL_ENABLE_MASK)
+#define WLAN_RTC_CONTROL_LOAD_RTC_MSB            1
+#define WLAN_RTC_CONTROL_LOAD_RTC_LSB            1
+#define WLAN_RTC_CONTROL_LOAD_RTC_MASK           0x00000002
+#define WLAN_RTC_CONTROL_LOAD_RTC_GET(x)         (((x) & WLAN_RTC_CONTROL_LOAD_RTC_MASK) >> WLAN_RTC_CONTROL_LOAD_RTC_LSB)
+#define WLAN_RTC_CONTROL_LOAD_RTC_SET(x)         (((x) << WLAN_RTC_CONTROL_LOAD_RTC_LSB) & WLAN_RTC_CONTROL_LOAD_RTC_MASK)
+#define WLAN_RTC_CONTROL_LOAD_ALARM_MSB          0
+#define WLAN_RTC_CONTROL_LOAD_ALARM_LSB          0
+#define WLAN_RTC_CONTROL_LOAD_ALARM_MASK         0x00000001
+#define WLAN_RTC_CONTROL_LOAD_ALARM_GET(x)       (((x) & WLAN_RTC_CONTROL_LOAD_ALARM_MASK) >> WLAN_RTC_CONTROL_LOAD_ALARM_LSB)
+#define WLAN_RTC_CONTROL_LOAD_ALARM_SET(x)       (((x) << WLAN_RTC_CONTROL_LOAD_ALARM_LSB) & WLAN_RTC_CONTROL_LOAD_ALARM_MASK)
+
+#define WLAN_RTC_TIME_ADDRESS                    0x000000a0
+#define WLAN_RTC_TIME_OFFSET                     0x000000a0
+#define WLAN_RTC_TIME_WEEK_DAY_MSB               26
+#define WLAN_RTC_TIME_WEEK_DAY_LSB               24
+#define WLAN_RTC_TIME_WEEK_DAY_MASK              0x07000000
+#define WLAN_RTC_TIME_WEEK_DAY_GET(x)            (((x) & WLAN_RTC_TIME_WEEK_DAY_MASK) >> WLAN_RTC_TIME_WEEK_DAY_LSB)
+#define WLAN_RTC_TIME_WEEK_DAY_SET(x)            (((x) << WLAN_RTC_TIME_WEEK_DAY_LSB) & WLAN_RTC_TIME_WEEK_DAY_MASK)
+#define WLAN_RTC_TIME_HOUR_MSB                   21
+#define WLAN_RTC_TIME_HOUR_LSB                   16
+#define WLAN_RTC_TIME_HOUR_MASK                  0x003f0000
+#define WLAN_RTC_TIME_HOUR_GET(x)                (((x) & WLAN_RTC_TIME_HOUR_MASK) >> WLAN_RTC_TIME_HOUR_LSB)
+#define WLAN_RTC_TIME_HOUR_SET(x)                (((x) << WLAN_RTC_TIME_HOUR_LSB) & WLAN_RTC_TIME_HOUR_MASK)
+#define WLAN_RTC_TIME_MINUTE_MSB                 14
+#define WLAN_RTC_TIME_MINUTE_LSB                 8
+#define WLAN_RTC_TIME_MINUTE_MASK                0x00007f00
+#define WLAN_RTC_TIME_MINUTE_GET(x)              (((x) & WLAN_RTC_TIME_MINUTE_MASK) >> WLAN_RTC_TIME_MINUTE_LSB)
+#define WLAN_RTC_TIME_MINUTE_SET(x)              (((x) << WLAN_RTC_TIME_MINUTE_LSB) & WLAN_RTC_TIME_MINUTE_MASK)
+#define WLAN_RTC_TIME_SECOND_MSB                 6
+#define WLAN_RTC_TIME_SECOND_LSB                 0
+#define WLAN_RTC_TIME_SECOND_MASK                0x0000007f
+#define WLAN_RTC_TIME_SECOND_GET(x)              (((x) & WLAN_RTC_TIME_SECOND_MASK) >> WLAN_RTC_TIME_SECOND_LSB)
+#define WLAN_RTC_TIME_SECOND_SET(x)              (((x) << WLAN_RTC_TIME_SECOND_LSB) & WLAN_RTC_TIME_SECOND_MASK)
+
+#define WLAN_RTC_DATE_ADDRESS                    0x000000a4
+#define WLAN_RTC_DATE_OFFSET                     0x000000a4
+#define WLAN_RTC_DATE_YEAR_MSB                   23
+#define WLAN_RTC_DATE_YEAR_LSB                   16
+#define WLAN_RTC_DATE_YEAR_MASK                  0x00ff0000
+#define WLAN_RTC_DATE_YEAR_GET(x)                (((x) & WLAN_RTC_DATE_YEAR_MASK) >> WLAN_RTC_DATE_YEAR_LSB)
+#define WLAN_RTC_DATE_YEAR_SET(x)                (((x) << WLAN_RTC_DATE_YEAR_LSB) & WLAN_RTC_DATE_YEAR_MASK)
+#define WLAN_RTC_DATE_MONTH_MSB                  12
+#define WLAN_RTC_DATE_MONTH_LSB                  8
+#define WLAN_RTC_DATE_MONTH_MASK                 0x00001f00
+#define WLAN_RTC_DATE_MONTH_GET(x)               (((x) & WLAN_RTC_DATE_MONTH_MASK) >> WLAN_RTC_DATE_MONTH_LSB)
+#define WLAN_RTC_DATE_MONTH_SET(x)               (((x) << WLAN_RTC_DATE_MONTH_LSB) & WLAN_RTC_DATE_MONTH_MASK)
+#define WLAN_RTC_DATE_MONTH_DAY_MSB              5
+#define WLAN_RTC_DATE_MONTH_DAY_LSB              0
+#define WLAN_RTC_DATE_MONTH_DAY_MASK             0x0000003f
+#define WLAN_RTC_DATE_MONTH_DAY_GET(x)           (((x) & WLAN_RTC_DATE_MONTH_DAY_MASK) >> WLAN_RTC_DATE_MONTH_DAY_LSB)
+#define WLAN_RTC_DATE_MONTH_DAY_SET(x)           (((x) << WLAN_RTC_DATE_MONTH_DAY_LSB) & WLAN_RTC_DATE_MONTH_DAY_MASK)
+
+#define WLAN_RTC_SET_TIME_ADDRESS                0x000000a8
+#define WLAN_RTC_SET_TIME_OFFSET                 0x000000a8
+#define WLAN_RTC_SET_TIME_WEEK_DAY_MSB           26
+#define WLAN_RTC_SET_TIME_WEEK_DAY_LSB           24
+#define WLAN_RTC_SET_TIME_WEEK_DAY_MASK          0x07000000
+#define WLAN_RTC_SET_TIME_WEEK_DAY_GET(x)        (((x) & WLAN_RTC_SET_TIME_WEEK_DAY_MASK) >> WLAN_RTC_SET_TIME_WEEK_DAY_LSB)
+#define WLAN_RTC_SET_TIME_WEEK_DAY_SET(x)        (((x) << WLAN_RTC_SET_TIME_WEEK_DAY_LSB) & WLAN_RTC_SET_TIME_WEEK_DAY_MASK)
+#define WLAN_RTC_SET_TIME_HOUR_MSB               21
+#define WLAN_RTC_SET_TIME_HOUR_LSB               16
+#define WLAN_RTC_SET_TIME_HOUR_MASK              0x003f0000
+#define WLAN_RTC_SET_TIME_HOUR_GET(x)            (((x) & WLAN_RTC_SET_TIME_HOUR_MASK) >> WLAN_RTC_SET_TIME_HOUR_LSB)
+#define WLAN_RTC_SET_TIME_HOUR_SET(x)            (((x) << WLAN_RTC_SET_TIME_HOUR_LSB) & WLAN_RTC_SET_TIME_HOUR_MASK)
+#define WLAN_RTC_SET_TIME_MINUTE_MSB             14
+#define WLAN_RTC_SET_TIME_MINUTE_LSB             8
+#define WLAN_RTC_SET_TIME_MINUTE_MASK            0x00007f00
+#define WLAN_RTC_SET_TIME_MINUTE_GET(x)          (((x) & WLAN_RTC_SET_TIME_MINUTE_MASK) >> WLAN_RTC_SET_TIME_MINUTE_LSB)
+#define WLAN_RTC_SET_TIME_MINUTE_SET(x)          (((x) << WLAN_RTC_SET_TIME_MINUTE_LSB) & WLAN_RTC_SET_TIME_MINUTE_MASK)
+#define WLAN_RTC_SET_TIME_SECOND_MSB             6
+#define WLAN_RTC_SET_TIME_SECOND_LSB             0
+#define WLAN_RTC_SET_TIME_SECOND_MASK            0x0000007f
+#define WLAN_RTC_SET_TIME_SECOND_GET(x)          (((x) & WLAN_RTC_SET_TIME_SECOND_MASK) >> WLAN_RTC_SET_TIME_SECOND_LSB)
+#define WLAN_RTC_SET_TIME_SECOND_SET(x)          (((x) << WLAN_RTC_SET_TIME_SECOND_LSB) & WLAN_RTC_SET_TIME_SECOND_MASK)
+
+#define WLAN_RTC_SET_DATE_ADDRESS                0x000000ac
+#define WLAN_RTC_SET_DATE_OFFSET                 0x000000ac
+#define WLAN_RTC_SET_DATE_YEAR_MSB               23
+#define WLAN_RTC_SET_DATE_YEAR_LSB               16
+#define WLAN_RTC_SET_DATE_YEAR_MASK              0x00ff0000
+#define WLAN_RTC_SET_DATE_YEAR_GET(x)            (((x) & WLAN_RTC_SET_DATE_YEAR_MASK) >> WLAN_RTC_SET_DATE_YEAR_LSB)
+#define WLAN_RTC_SET_DATE_YEAR_SET(x)            (((x) << WLAN_RTC_SET_DATE_YEAR_LSB) & WLAN_RTC_SET_DATE_YEAR_MASK)
+#define WLAN_RTC_SET_DATE_MONTH_MSB              12
+#define WLAN_RTC_SET_DATE_MONTH_LSB              8
+#define WLAN_RTC_SET_DATE_MONTH_MASK             0x00001f00
+#define WLAN_RTC_SET_DATE_MONTH_GET(x)           (((x) & WLAN_RTC_SET_DATE_MONTH_MASK) >> WLAN_RTC_SET_DATE_MONTH_LSB)
+#define WLAN_RTC_SET_DATE_MONTH_SET(x)           (((x) << WLAN_RTC_SET_DATE_MONTH_LSB) & WLAN_RTC_SET_DATE_MONTH_MASK)
+#define WLAN_RTC_SET_DATE_MONTH_DAY_MSB          5
+#define WLAN_RTC_SET_DATE_MONTH_DAY_LSB          0
+#define WLAN_RTC_SET_DATE_MONTH_DAY_MASK         0x0000003f
+#define WLAN_RTC_SET_DATE_MONTH_DAY_GET(x)       (((x) & WLAN_RTC_SET_DATE_MONTH_DAY_MASK) >> WLAN_RTC_SET_DATE_MONTH_DAY_LSB)
+#define WLAN_RTC_SET_DATE_MONTH_DAY_SET(x)       (((x) << WLAN_RTC_SET_DATE_MONTH_DAY_LSB) & WLAN_RTC_SET_DATE_MONTH_DAY_MASK)
+
+#define WLAN_RTC_SET_ALARM_ADDRESS               0x000000b0
+#define WLAN_RTC_SET_ALARM_OFFSET                0x000000b0
+#define WLAN_RTC_SET_ALARM_HOUR_MSB              21
+#define WLAN_RTC_SET_ALARM_HOUR_LSB              16
+#define WLAN_RTC_SET_ALARM_HOUR_MASK             0x003f0000
+#define WLAN_RTC_SET_ALARM_HOUR_GET(x)           (((x) & WLAN_RTC_SET_ALARM_HOUR_MASK) >> WLAN_RTC_SET_ALARM_HOUR_LSB)
+#define WLAN_RTC_SET_ALARM_HOUR_SET(x)           (((x) << WLAN_RTC_SET_ALARM_HOUR_LSB) & WLAN_RTC_SET_ALARM_HOUR_MASK)
+#define WLAN_RTC_SET_ALARM_MINUTE_MSB            14
+#define WLAN_RTC_SET_ALARM_MINUTE_LSB            8
+#define WLAN_RTC_SET_ALARM_MINUTE_MASK           0x00007f00
+#define WLAN_RTC_SET_ALARM_MINUTE_GET(x)         (((x) & WLAN_RTC_SET_ALARM_MINUTE_MASK) >> WLAN_RTC_SET_ALARM_MINUTE_LSB)
+#define WLAN_RTC_SET_ALARM_MINUTE_SET(x)         (((x) << WLAN_RTC_SET_ALARM_MINUTE_LSB) & WLAN_RTC_SET_ALARM_MINUTE_MASK)
+#define WLAN_RTC_SET_ALARM_SECOND_MSB            6
+#define WLAN_RTC_SET_ALARM_SECOND_LSB            0
+#define WLAN_RTC_SET_ALARM_SECOND_MASK           0x0000007f
+#define WLAN_RTC_SET_ALARM_SECOND_GET(x)         (((x) & WLAN_RTC_SET_ALARM_SECOND_MASK) >> WLAN_RTC_SET_ALARM_SECOND_LSB)
+#define WLAN_RTC_SET_ALARM_SECOND_SET(x)         (((x) << WLAN_RTC_SET_ALARM_SECOND_LSB) & WLAN_RTC_SET_ALARM_SECOND_MASK)
+
+#define WLAN_RTC_CONFIG_ADDRESS                  0x000000b4
+#define WLAN_RTC_CONFIG_OFFSET                   0x000000b4
+#define WLAN_RTC_CONFIG_BCD_MSB                  2
+#define WLAN_RTC_CONFIG_BCD_LSB                  2
+#define WLAN_RTC_CONFIG_BCD_MASK                 0x00000004
+#define WLAN_RTC_CONFIG_BCD_GET(x)               (((x) & WLAN_RTC_CONFIG_BCD_MASK) >> WLAN_RTC_CONFIG_BCD_LSB)
+#define WLAN_RTC_CONFIG_BCD_SET(x)               (((x) << WLAN_RTC_CONFIG_BCD_LSB) & WLAN_RTC_CONFIG_BCD_MASK)
+#define WLAN_RTC_CONFIG_TWELVE_HOUR_MSB          1
+#define WLAN_RTC_CONFIG_TWELVE_HOUR_LSB          1
+#define WLAN_RTC_CONFIG_TWELVE_HOUR_MASK         0x00000002
+#define WLAN_RTC_CONFIG_TWELVE_HOUR_GET(x)       (((x) & WLAN_RTC_CONFIG_TWELVE_HOUR_MASK) >> WLAN_RTC_CONFIG_TWELVE_HOUR_LSB)
+#define WLAN_RTC_CONFIG_TWELVE_HOUR_SET(x)       (((x) << WLAN_RTC_CONFIG_TWELVE_HOUR_LSB) & WLAN_RTC_CONFIG_TWELVE_HOUR_MASK)
+#define WLAN_RTC_CONFIG_DSE_MSB                  0
+#define WLAN_RTC_CONFIG_DSE_LSB                  0
+#define WLAN_RTC_CONFIG_DSE_MASK                 0x00000001
+#define WLAN_RTC_CONFIG_DSE_GET(x)               (((x) & WLAN_RTC_CONFIG_DSE_MASK) >> WLAN_RTC_CONFIG_DSE_LSB)
+#define WLAN_RTC_CONFIG_DSE_SET(x)               (((x) << WLAN_RTC_CONFIG_DSE_LSB) & WLAN_RTC_CONFIG_DSE_MASK)
+
+#define WLAN_RTC_ALARM_STATUS_ADDRESS            0x000000b8
+#define WLAN_RTC_ALARM_STATUS_OFFSET             0x000000b8
+#define WLAN_RTC_ALARM_STATUS_ENABLE_MSB         1
+#define WLAN_RTC_ALARM_STATUS_ENABLE_LSB         1
+#define WLAN_RTC_ALARM_STATUS_ENABLE_MASK        0x00000002
+#define WLAN_RTC_ALARM_STATUS_ENABLE_GET(x)      (((x) & WLAN_RTC_ALARM_STATUS_ENABLE_MASK) >> WLAN_RTC_ALARM_STATUS_ENABLE_LSB)
+#define WLAN_RTC_ALARM_STATUS_ENABLE_SET(x)      (((x) << WLAN_RTC_ALARM_STATUS_ENABLE_LSB) & WLAN_RTC_ALARM_STATUS_ENABLE_MASK)
+#define WLAN_RTC_ALARM_STATUS_INTERRUPT_MSB      0
+#define WLAN_RTC_ALARM_STATUS_INTERRUPT_LSB      0
+#define WLAN_RTC_ALARM_STATUS_INTERRUPT_MASK     0x00000001
+#define WLAN_RTC_ALARM_STATUS_INTERRUPT_GET(x)   (((x) & WLAN_RTC_ALARM_STATUS_INTERRUPT_MASK) >> WLAN_RTC_ALARM_STATUS_INTERRUPT_LSB)
+#define WLAN_RTC_ALARM_STATUS_INTERRUPT_SET(x)   (((x) << WLAN_RTC_ALARM_STATUS_INTERRUPT_LSB) & WLAN_RTC_ALARM_STATUS_INTERRUPT_MASK)
+
+#define WLAN_UART_WAKEUP_ADDRESS                 0x000000bc
+#define WLAN_UART_WAKEUP_OFFSET                  0x000000bc
+#define WLAN_UART_WAKEUP_ENABLE_MSB              0
+#define WLAN_UART_WAKEUP_ENABLE_LSB              0
+#define WLAN_UART_WAKEUP_ENABLE_MASK             0x00000001
+#define WLAN_UART_WAKEUP_ENABLE_GET(x)           (((x) & WLAN_UART_WAKEUP_ENABLE_MASK) >> WLAN_UART_WAKEUP_ENABLE_LSB)
+#define WLAN_UART_WAKEUP_ENABLE_SET(x)           (((x) << WLAN_UART_WAKEUP_ENABLE_LSB) & WLAN_UART_WAKEUP_ENABLE_MASK)
+
+#define WLAN_RESET_CAUSE_ADDRESS                 0x000000c0
+#define WLAN_RESET_CAUSE_OFFSET                  0x000000c0
+#define WLAN_RESET_CAUSE_LAST_MSB                2
+#define WLAN_RESET_CAUSE_LAST_LSB                0
+#define WLAN_RESET_CAUSE_LAST_MASK               0x00000007
+#define WLAN_RESET_CAUSE_LAST_GET(x)             (((x) & WLAN_RESET_CAUSE_LAST_MASK) >> WLAN_RESET_CAUSE_LAST_LSB)
+#define WLAN_RESET_CAUSE_LAST_SET(x)             (((x) << WLAN_RESET_CAUSE_LAST_LSB) & WLAN_RESET_CAUSE_LAST_MASK)
+
+#define WLAN_SYSTEM_SLEEP_ADDRESS                0x000000c4
+#define WLAN_SYSTEM_SLEEP_OFFSET                 0x000000c4
+#define WLAN_SYSTEM_SLEEP_HOST_IF_MSB            4
+#define WLAN_SYSTEM_SLEEP_HOST_IF_LSB            4
+#define WLAN_SYSTEM_SLEEP_HOST_IF_MASK           0x00000010
+#define WLAN_SYSTEM_SLEEP_HOST_IF_GET(x)         (((x) & WLAN_SYSTEM_SLEEP_HOST_IF_MASK) >> WLAN_SYSTEM_SLEEP_HOST_IF_LSB)
+#define WLAN_SYSTEM_SLEEP_HOST_IF_SET(x)         (((x) << WLAN_SYSTEM_SLEEP_HOST_IF_LSB) & WLAN_SYSTEM_SLEEP_HOST_IF_MASK)
+#define WLAN_SYSTEM_SLEEP_MBOX_MSB               3
+#define WLAN_SYSTEM_SLEEP_MBOX_LSB               3
+#define WLAN_SYSTEM_SLEEP_MBOX_MASK              0x00000008
+#define WLAN_SYSTEM_SLEEP_MBOX_GET(x)            (((x) & WLAN_SYSTEM_SLEEP_MBOX_MASK) >> WLAN_SYSTEM_SLEEP_MBOX_LSB)
+#define WLAN_SYSTEM_SLEEP_MBOX_SET(x)            (((x) << WLAN_SYSTEM_SLEEP_MBOX_LSB) & WLAN_SYSTEM_SLEEP_MBOX_MASK)
+#define WLAN_SYSTEM_SLEEP_MAC_IF_MSB             2
+#define WLAN_SYSTEM_SLEEP_MAC_IF_LSB             2
+#define WLAN_SYSTEM_SLEEP_MAC_IF_MASK            0x00000004
+#define WLAN_SYSTEM_SLEEP_MAC_IF_GET(x)          (((x) & WLAN_SYSTEM_SLEEP_MAC_IF_MASK) >> WLAN_SYSTEM_SLEEP_MAC_IF_LSB)
+#define WLAN_SYSTEM_SLEEP_MAC_IF_SET(x)          (((x) << WLAN_SYSTEM_SLEEP_MAC_IF_LSB) & WLAN_SYSTEM_SLEEP_MAC_IF_MASK)
+#define WLAN_SYSTEM_SLEEP_LIGHT_MSB              1
+#define WLAN_SYSTEM_SLEEP_LIGHT_LSB              1
+#define WLAN_SYSTEM_SLEEP_LIGHT_MASK             0x00000002
+#define WLAN_SYSTEM_SLEEP_LIGHT_GET(x)           (((x) & WLAN_SYSTEM_SLEEP_LIGHT_MASK) >> WLAN_SYSTEM_SLEEP_LIGHT_LSB)
+#define WLAN_SYSTEM_SLEEP_LIGHT_SET(x)           (((x) << WLAN_SYSTEM_SLEEP_LIGHT_LSB) & WLAN_SYSTEM_SLEEP_LIGHT_MASK)
+#define WLAN_SYSTEM_SLEEP_DISABLE_MSB            0
+#define WLAN_SYSTEM_SLEEP_DISABLE_LSB            0
+#define WLAN_SYSTEM_SLEEP_DISABLE_MASK           0x00000001
+#define WLAN_SYSTEM_SLEEP_DISABLE_GET(x)         (((x) & WLAN_SYSTEM_SLEEP_DISABLE_MASK) >> WLAN_SYSTEM_SLEEP_DISABLE_LSB)
+#define WLAN_SYSTEM_SLEEP_DISABLE_SET(x)         (((x) << WLAN_SYSTEM_SLEEP_DISABLE_LSB) & WLAN_SYSTEM_SLEEP_DISABLE_MASK)
+
+#define WLAN_SDIO_WRAPPER_ADDRESS                0x000000c8
+#define WLAN_SDIO_WRAPPER_OFFSET                 0x000000c8
+#define WLAN_SDIO_WRAPPER_SLEEP_MSB              3
+#define WLAN_SDIO_WRAPPER_SLEEP_LSB              3
+#define WLAN_SDIO_WRAPPER_SLEEP_MASK             0x00000008
+#define WLAN_SDIO_WRAPPER_SLEEP_GET(x)           (((x) & WLAN_SDIO_WRAPPER_SLEEP_MASK) >> WLAN_SDIO_WRAPPER_SLEEP_LSB)
+#define WLAN_SDIO_WRAPPER_SLEEP_SET(x)           (((x) << WLAN_SDIO_WRAPPER_SLEEP_LSB) & WLAN_SDIO_WRAPPER_SLEEP_MASK)
+#define WLAN_SDIO_WRAPPER_WAKEUP_MSB             2
+#define WLAN_SDIO_WRAPPER_WAKEUP_LSB             2
+#define WLAN_SDIO_WRAPPER_WAKEUP_MASK            0x00000004
+#define WLAN_SDIO_WRAPPER_WAKEUP_GET(x)          (((x) & WLAN_SDIO_WRAPPER_WAKEUP_MASK) >> WLAN_SDIO_WRAPPER_WAKEUP_LSB)
+#define WLAN_SDIO_WRAPPER_WAKEUP_SET(x)          (((x) << WLAN_SDIO_WRAPPER_WAKEUP_LSB) & WLAN_SDIO_WRAPPER_WAKEUP_MASK)
+#define WLAN_SDIO_WRAPPER_SOC_ON_MSB             1
+#define WLAN_SDIO_WRAPPER_SOC_ON_LSB             1
+#define WLAN_SDIO_WRAPPER_SOC_ON_MASK            0x00000002
+#define WLAN_SDIO_WRAPPER_SOC_ON_GET(x)          (((x) & WLAN_SDIO_WRAPPER_SOC_ON_MASK) >> WLAN_SDIO_WRAPPER_SOC_ON_LSB)
+#define WLAN_SDIO_WRAPPER_SOC_ON_SET(x)          (((x) << WLAN_SDIO_WRAPPER_SOC_ON_LSB) & WLAN_SDIO_WRAPPER_SOC_ON_MASK)
+#define WLAN_SDIO_WRAPPER_ON_MSB                 0
+#define WLAN_SDIO_WRAPPER_ON_LSB                 0
+#define WLAN_SDIO_WRAPPER_ON_MASK                0x00000001
+#define WLAN_SDIO_WRAPPER_ON_GET(x)              (((x) & WLAN_SDIO_WRAPPER_ON_MASK) >> WLAN_SDIO_WRAPPER_ON_LSB)
+#define WLAN_SDIO_WRAPPER_ON_SET(x)              (((x) << WLAN_SDIO_WRAPPER_ON_LSB) & WLAN_SDIO_WRAPPER_ON_MASK)
+
+#define WLAN_MAC_SLEEP_CONTROL_ADDRESS           0x000000cc
+#define WLAN_MAC_SLEEP_CONTROL_OFFSET            0x000000cc
+#define WLAN_MAC_SLEEP_CONTROL_ENABLE_MSB        1
+#define WLAN_MAC_SLEEP_CONTROL_ENABLE_LSB        0
+#define WLAN_MAC_SLEEP_CONTROL_ENABLE_MASK       0x00000003
+#define WLAN_MAC_SLEEP_CONTROL_ENABLE_GET(x)     (((x) & WLAN_MAC_SLEEP_CONTROL_ENABLE_MASK) >> WLAN_MAC_SLEEP_CONTROL_ENABLE_LSB)
+#define WLAN_MAC_SLEEP_CONTROL_ENABLE_SET(x)     (((x) << WLAN_MAC_SLEEP_CONTROL_ENABLE_LSB) & WLAN_MAC_SLEEP_CONTROL_ENABLE_MASK)
+
+#define WLAN_KEEP_AWAKE_ADDRESS                  0x000000d0
+#define WLAN_KEEP_AWAKE_OFFSET                   0x000000d0
+#define WLAN_KEEP_AWAKE_COUNT_MSB                7
+#define WLAN_KEEP_AWAKE_COUNT_LSB                0
+#define WLAN_KEEP_AWAKE_COUNT_MASK               0x000000ff
+#define WLAN_KEEP_AWAKE_COUNT_GET(x)             (((x) & WLAN_KEEP_AWAKE_COUNT_MASK) >> WLAN_KEEP_AWAKE_COUNT_LSB)
+#define WLAN_KEEP_AWAKE_COUNT_SET(x)             (((x) << WLAN_KEEP_AWAKE_COUNT_LSB) & WLAN_KEEP_AWAKE_COUNT_MASK)
+
+#define WLAN_LPO_CAL_TIME_ADDRESS                0x000000d4
+#define WLAN_LPO_CAL_TIME_OFFSET                 0x000000d4
+#define WLAN_LPO_CAL_TIME_LENGTH_MSB             13
+#define WLAN_LPO_CAL_TIME_LENGTH_LSB             0
+#define WLAN_LPO_CAL_TIME_LENGTH_MASK            0x00003fff
+#define WLAN_LPO_CAL_TIME_LENGTH_GET(x)          (((x) & WLAN_LPO_CAL_TIME_LENGTH_MASK) >> WLAN_LPO_CAL_TIME_LENGTH_LSB)
+#define WLAN_LPO_CAL_TIME_LENGTH_SET(x)          (((x) << WLAN_LPO_CAL_TIME_LENGTH_LSB) & WLAN_LPO_CAL_TIME_LENGTH_MASK)
+
+#define WLAN_LPO_INIT_DIVIDEND_INT_ADDRESS       0x000000d8
+#define WLAN_LPO_INIT_DIVIDEND_INT_OFFSET        0x000000d8
+#define WLAN_LPO_INIT_DIVIDEND_INT_VALUE_MSB     23
+#define WLAN_LPO_INIT_DIVIDEND_INT_VALUE_LSB     0
+#define WLAN_LPO_INIT_DIVIDEND_INT_VALUE_MASK    0x00ffffff
+#define WLAN_LPO_INIT_DIVIDEND_INT_VALUE_GET(x)  (((x) & WLAN_LPO_INIT_DIVIDEND_INT_VALUE_MASK) >> WLAN_LPO_INIT_DIVIDEND_INT_VALUE_LSB)
+#define WLAN_LPO_INIT_DIVIDEND_INT_VALUE_SET(x)  (((x) << WLAN_LPO_INIT_DIVIDEND_INT_VALUE_LSB) & WLAN_LPO_INIT_DIVIDEND_INT_VALUE_MASK)
+
+#define WLAN_LPO_INIT_DIVIDEND_FRACTION_ADDRESS  0x000000dc
+#define WLAN_LPO_INIT_DIVIDEND_FRACTION_OFFSET   0x000000dc
+#define WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_MSB 10
+#define WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB 0
+#define WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK 0x000007ff
+#define WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_GET(x) (((x) & WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK) >> WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB)
+#define WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_SET(x) (((x) << WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB) & WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK)
+
+#define WLAN_LPO_CAL_ADDRESS                     0x000000e0
+#define WLAN_LPO_CAL_OFFSET                      0x000000e0
+#define WLAN_LPO_CAL_ENABLE_MSB                  20
+#define WLAN_LPO_CAL_ENABLE_LSB                  20
+#define WLAN_LPO_CAL_ENABLE_MASK                 0x00100000
+#define WLAN_LPO_CAL_ENABLE_GET(x)               (((x) & WLAN_LPO_CAL_ENABLE_MASK) >> WLAN_LPO_CAL_ENABLE_LSB)
+#define WLAN_LPO_CAL_ENABLE_SET(x)               (((x) << WLAN_LPO_CAL_ENABLE_LSB) & WLAN_LPO_CAL_ENABLE_MASK)
+#define WLAN_LPO_CAL_COUNT_MSB                   19
+#define WLAN_LPO_CAL_COUNT_LSB                   0
+#define WLAN_LPO_CAL_COUNT_MASK                  0x000fffff
+#define WLAN_LPO_CAL_COUNT_GET(x)                (((x) & WLAN_LPO_CAL_COUNT_MASK) >> WLAN_LPO_CAL_COUNT_LSB)
+#define WLAN_LPO_CAL_COUNT_SET(x)                (((x) << WLAN_LPO_CAL_COUNT_LSB) & WLAN_LPO_CAL_COUNT_MASK)
+
+#define WLAN_LPO_CAL_TEST_CONTROL_ADDRESS        0x000000e4
+#define WLAN_LPO_CAL_TEST_CONTROL_OFFSET         0x000000e4
+#define WLAN_LPO_CAL_TEST_CONTROL_ENABLE_MSB     5
+#define WLAN_LPO_CAL_TEST_CONTROL_ENABLE_LSB     5
+#define WLAN_LPO_CAL_TEST_CONTROL_ENABLE_MASK    0x00000020
+#define WLAN_LPO_CAL_TEST_CONTROL_ENABLE_GET(x)  (((x) & WLAN_LPO_CAL_TEST_CONTROL_ENABLE_MASK) >> WLAN_LPO_CAL_TEST_CONTROL_ENABLE_LSB)
+#define WLAN_LPO_CAL_TEST_CONTROL_ENABLE_SET(x)  (((x) << WLAN_LPO_CAL_TEST_CONTROL_ENABLE_LSB) & WLAN_LPO_CAL_TEST_CONTROL_ENABLE_MASK)
+#define WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_MSB 4
+#define WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB 0
+#define WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK 0x0000001f
+#define WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_GET(x) (((x) & WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK) >> WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB)
+#define WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_SET(x) (((x) << WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB) & WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK)
+
+#define WLAN_LPO_CAL_TEST_STATUS_ADDRESS         0x000000e8
+#define WLAN_LPO_CAL_TEST_STATUS_OFFSET          0x000000e8
+#define WLAN_LPO_CAL_TEST_STATUS_READY_MSB       16
+#define WLAN_LPO_CAL_TEST_STATUS_READY_LSB       16
+#define WLAN_LPO_CAL_TEST_STATUS_READY_MASK      0x00010000
+#define WLAN_LPO_CAL_TEST_STATUS_READY_GET(x)    (((x) & WLAN_LPO_CAL_TEST_STATUS_READY_MASK) >> WLAN_LPO_CAL_TEST_STATUS_READY_LSB)
+#define WLAN_LPO_CAL_TEST_STATUS_READY_SET(x)    (((x) << WLAN_LPO_CAL_TEST_STATUS_READY_LSB) & WLAN_LPO_CAL_TEST_STATUS_READY_MASK)
+#define WLAN_LPO_CAL_TEST_STATUS_COUNT_MSB       15
+#define WLAN_LPO_CAL_TEST_STATUS_COUNT_LSB       0
+#define WLAN_LPO_CAL_TEST_STATUS_COUNT_MASK      0x0000ffff
+#define WLAN_LPO_CAL_TEST_STATUS_COUNT_GET(x)    (((x) & WLAN_LPO_CAL_TEST_STATUS_COUNT_MASK) >> WLAN_LPO_CAL_TEST_STATUS_COUNT_LSB)
+#define WLAN_LPO_CAL_TEST_STATUS_COUNT_SET(x)    (((x) << WLAN_LPO_CAL_TEST_STATUS_COUNT_LSB) & WLAN_LPO_CAL_TEST_STATUS_COUNT_MASK)
+
+#define WLAN_CHIP_ID_ADDRESS                     0x000000ec
+#define WLAN_CHIP_ID_OFFSET                      0x000000ec
+#define WLAN_CHIP_ID_DEVICE_ID_MSB               31
+#define WLAN_CHIP_ID_DEVICE_ID_LSB               16
+#define WLAN_CHIP_ID_DEVICE_ID_MASK              0xffff0000
+#define WLAN_CHIP_ID_DEVICE_ID_GET(x)            (((x) & WLAN_CHIP_ID_DEVICE_ID_MASK) >> WLAN_CHIP_ID_DEVICE_ID_LSB)
+#define WLAN_CHIP_ID_DEVICE_ID_SET(x)            (((x) << WLAN_CHIP_ID_DEVICE_ID_LSB) & WLAN_CHIP_ID_DEVICE_ID_MASK)
+#define WLAN_CHIP_ID_CONFIG_ID_MSB               15
+#define WLAN_CHIP_ID_CONFIG_ID_LSB               4
+#define WLAN_CHIP_ID_CONFIG_ID_MASK              0x0000fff0
+#define WLAN_CHIP_ID_CONFIG_ID_GET(x)            (((x) & WLAN_CHIP_ID_CONFIG_ID_MASK) >> WLAN_CHIP_ID_CONFIG_ID_LSB)
+#define WLAN_CHIP_ID_CONFIG_ID_SET(x)            (((x) << WLAN_CHIP_ID_CONFIG_ID_LSB) & WLAN_CHIP_ID_CONFIG_ID_MASK)
+#define WLAN_CHIP_ID_VERSION_ID_MSB              3
+#define WLAN_CHIP_ID_VERSION_ID_LSB              0
+#define WLAN_CHIP_ID_VERSION_ID_MASK             0x0000000f
+#define WLAN_CHIP_ID_VERSION_ID_GET(x)           (((x) & WLAN_CHIP_ID_VERSION_ID_MASK) >> WLAN_CHIP_ID_VERSION_ID_LSB)
+#define WLAN_CHIP_ID_VERSION_ID_SET(x)           (((x) << WLAN_CHIP_ID_VERSION_ID_LSB) & WLAN_CHIP_ID_VERSION_ID_MASK)
+
+#define WLAN_DERIVED_RTC_CLK_ADDRESS             0x000000f0
+#define WLAN_DERIVED_RTC_CLK_OFFSET              0x000000f0
+#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MSB 20
+#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB 20
+#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK 0x00100000
+#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_GET(x) (((x) & WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK) >> WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB)
+#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_SET(x) (((x) << WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB) & WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK)
+#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_MSB 18
+#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB 18
+#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK 0x00040000
+#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_GET(x) (((x) & WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK) >> WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB)
+#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_SET(x) (((x) << WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB) & WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK)
+#define WLAN_DERIVED_RTC_CLK_FORCE_MSB           17
+#define WLAN_DERIVED_RTC_CLK_FORCE_LSB           16
+#define WLAN_DERIVED_RTC_CLK_FORCE_MASK          0x00030000
+#define WLAN_DERIVED_RTC_CLK_FORCE_GET(x)        (((x) & WLAN_DERIVED_RTC_CLK_FORCE_MASK) >> WLAN_DERIVED_RTC_CLK_FORCE_LSB)
+#define WLAN_DERIVED_RTC_CLK_FORCE_SET(x)        (((x) << WLAN_DERIVED_RTC_CLK_FORCE_LSB) & WLAN_DERIVED_RTC_CLK_FORCE_MASK)
+#define WLAN_DERIVED_RTC_CLK_PERIOD_MSB          15
+#define WLAN_DERIVED_RTC_CLK_PERIOD_LSB          1
+#define WLAN_DERIVED_RTC_CLK_PERIOD_MASK         0x0000fffe
+#define WLAN_DERIVED_RTC_CLK_PERIOD_GET(x)       (((x) & WLAN_DERIVED_RTC_CLK_PERIOD_MASK) >> WLAN_DERIVED_RTC_CLK_PERIOD_LSB)
+#define WLAN_DERIVED_RTC_CLK_PERIOD_SET(x)       (((x) << WLAN_DERIVED_RTC_CLK_PERIOD_LSB) & WLAN_DERIVED_RTC_CLK_PERIOD_MASK)
+
+#define MAC_PCU_SLP32_MODE_ADDRESS               0x000000f4
+#define MAC_PCU_SLP32_MODE_OFFSET                0x000000f4
+#define MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_MSB 24
+#define MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_LSB 24
+#define MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_MASK 0x01000000
+#define MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_GET(x) (((x) & MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_MASK) >> MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_LSB)
+#define MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_SET(x) (((x) << MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_LSB) & MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_MASK)
+#define MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_MSB 23
+#define MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_LSB 23
+#define MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_MASK 0x00800000
+#define MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_GET(x) (((x) & MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_MASK) >> MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_LSB)
+#define MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_SET(x) (((x) << MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_LSB) & MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_MASK)
+#define MAC_PCU_SLP32_MODE_DISABLE_32KHZ_MSB     22
+#define MAC_PCU_SLP32_MODE_DISABLE_32KHZ_LSB     22
+#define MAC_PCU_SLP32_MODE_DISABLE_32KHZ_MASK    0x00400000
+#define MAC_PCU_SLP32_MODE_DISABLE_32KHZ_GET(x)  (((x) & MAC_PCU_SLP32_MODE_DISABLE_32KHZ_MASK) >> MAC_PCU_SLP32_MODE_DISABLE_32KHZ_LSB)
+#define MAC_PCU_SLP32_MODE_DISABLE_32KHZ_SET(x)  (((x) << MAC_PCU_SLP32_MODE_DISABLE_32KHZ_LSB) & MAC_PCU_SLP32_MODE_DISABLE_32KHZ_MASK)
+#define MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_MSB  21
+#define MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_LSB  21
+#define MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_MASK 0x00200000
+#define MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_GET(x) (((x) & MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_MASK) >> MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_LSB)
+#define MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_SET(x) (((x) << MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_LSB) & MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_MASK)
+#define MAC_PCU_SLP32_MODE_ENABLE_MSB            20
+#define MAC_PCU_SLP32_MODE_ENABLE_LSB            20
+#define MAC_PCU_SLP32_MODE_ENABLE_MASK           0x00100000
+#define MAC_PCU_SLP32_MODE_ENABLE_GET(x)         (((x) & MAC_PCU_SLP32_MODE_ENABLE_MASK) >> MAC_PCU_SLP32_MODE_ENABLE_LSB)
+#define MAC_PCU_SLP32_MODE_ENABLE_SET(x)         (((x) << MAC_PCU_SLP32_MODE_ENABLE_LSB) & MAC_PCU_SLP32_MODE_ENABLE_MASK)
+#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MSB  19
+#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_LSB  0
+#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MASK 0x000fffff
+#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_GET(x) (((x) & MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MASK) >> MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_LSB)
+#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_SET(x) (((x) << MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_LSB) & MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MASK)
+
+#define MAC_PCU_SLP32_WAKE_ADDRESS               0x000000f8
+#define MAC_PCU_SLP32_WAKE_OFFSET                0x000000f8
+#define MAC_PCU_SLP32_WAKE_XTL_TIME_MSB          15
+#define MAC_PCU_SLP32_WAKE_XTL_TIME_LSB          0
+#define MAC_PCU_SLP32_WAKE_XTL_TIME_MASK         0x0000ffff
+#define MAC_PCU_SLP32_WAKE_XTL_TIME_GET(x)       (((x) & MAC_PCU_SLP32_WAKE_XTL_TIME_MASK) >> MAC_PCU_SLP32_WAKE_XTL_TIME_LSB)
+#define MAC_PCU_SLP32_WAKE_XTL_TIME_SET(x)       (((x) << MAC_PCU_SLP32_WAKE_XTL_TIME_LSB) & MAC_PCU_SLP32_WAKE_XTL_TIME_MASK)
+
+#define MAC_PCU_SLP32_INC_ADDRESS                0x000000fc
+#define MAC_PCU_SLP32_INC_OFFSET                 0x000000fc
+#define MAC_PCU_SLP32_INC_TSF_INC_MSB            19
+#define MAC_PCU_SLP32_INC_TSF_INC_LSB            0
+#define MAC_PCU_SLP32_INC_TSF_INC_MASK           0x000fffff
+#define MAC_PCU_SLP32_INC_TSF_INC_GET(x)         (((x) & MAC_PCU_SLP32_INC_TSF_INC_MASK) >> MAC_PCU_SLP32_INC_TSF_INC_LSB)
+#define MAC_PCU_SLP32_INC_TSF_INC_SET(x)         (((x) << MAC_PCU_SLP32_INC_TSF_INC_LSB) & MAC_PCU_SLP32_INC_TSF_INC_MASK)
+
+#define MAC_PCU_SLP_MIB1_ADDRESS                 0x00000100
+#define MAC_PCU_SLP_MIB1_OFFSET                  0x00000100
+#define MAC_PCU_SLP_MIB1_SLEEP_CNT_MSB           31
+#define MAC_PCU_SLP_MIB1_SLEEP_CNT_LSB           0
+#define MAC_PCU_SLP_MIB1_SLEEP_CNT_MASK          0xffffffff
+#define MAC_PCU_SLP_MIB1_SLEEP_CNT_GET(x)        (((x) & MAC_PCU_SLP_MIB1_SLEEP_CNT_MASK) >> MAC_PCU_SLP_MIB1_SLEEP_CNT_LSB)
+#define MAC_PCU_SLP_MIB1_SLEEP_CNT_SET(x)        (((x) << MAC_PCU_SLP_MIB1_SLEEP_CNT_LSB) & MAC_PCU_SLP_MIB1_SLEEP_CNT_MASK)
+
+#define MAC_PCU_SLP_MIB2_ADDRESS                 0x00000104
+#define MAC_PCU_SLP_MIB2_OFFSET                  0x00000104
+#define MAC_PCU_SLP_MIB2_CYCLE_CNT_MSB           31
+#define MAC_PCU_SLP_MIB2_CYCLE_CNT_LSB           0
+#define MAC_PCU_SLP_MIB2_CYCLE_CNT_MASK          0xffffffff
+#define MAC_PCU_SLP_MIB2_CYCLE_CNT_GET(x)        (((x) & MAC_PCU_SLP_MIB2_CYCLE_CNT_MASK) >> MAC_PCU_SLP_MIB2_CYCLE_CNT_LSB)
+#define MAC_PCU_SLP_MIB2_CYCLE_CNT_SET(x)        (((x) << MAC_PCU_SLP_MIB2_CYCLE_CNT_LSB) & MAC_PCU_SLP_MIB2_CYCLE_CNT_MASK)
+
+#define MAC_PCU_SLP_MIB3_ADDRESS                 0x00000108
+#define MAC_PCU_SLP_MIB3_OFFSET                  0x00000108
+#define MAC_PCU_SLP_MIB3_PENDING_MSB             1
+#define MAC_PCU_SLP_MIB3_PENDING_LSB             1
+#define MAC_PCU_SLP_MIB3_PENDING_MASK            0x00000002
+#define MAC_PCU_SLP_MIB3_PENDING_GET(x)          (((x) & MAC_PCU_SLP_MIB3_PENDING_MASK) >> MAC_PCU_SLP_MIB3_PENDING_LSB)
+#define MAC_PCU_SLP_MIB3_PENDING_SET(x)          (((x) << MAC_PCU_SLP_MIB3_PENDING_LSB) & MAC_PCU_SLP_MIB3_PENDING_MASK)
+#define MAC_PCU_SLP_MIB3_CLR_CNT_MSB             0
+#define MAC_PCU_SLP_MIB3_CLR_CNT_LSB             0
+#define MAC_PCU_SLP_MIB3_CLR_CNT_MASK            0x00000001
+#define MAC_PCU_SLP_MIB3_CLR_CNT_GET(x)          (((x) & MAC_PCU_SLP_MIB3_CLR_CNT_MASK) >> MAC_PCU_SLP_MIB3_CLR_CNT_LSB)
+#define MAC_PCU_SLP_MIB3_CLR_CNT_SET(x)          (((x) << MAC_PCU_SLP_MIB3_CLR_CNT_LSB) & MAC_PCU_SLP_MIB3_CLR_CNT_MASK)
+
+#define WLAN_POWER_REG_ADDRESS                   0x0000010c
+#define WLAN_POWER_REG_OFFSET                    0x0000010c
+#define WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_MSB 15
+#define WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_LSB 15
+#define WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_MASK 0x00008000
+#define WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_GET(x) (((x) & WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_MASK) >> WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_LSB)
+#define WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_SET(x) (((x) << WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_LSB) & WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_MASK)
+#define WLAN_POWER_REG_DEBUG_EN_MSB              14
+#define WLAN_POWER_REG_DEBUG_EN_LSB              14
+#define WLAN_POWER_REG_DEBUG_EN_MASK             0x00004000
+#define WLAN_POWER_REG_DEBUG_EN_GET(x)           (((x) & WLAN_POWER_REG_DEBUG_EN_MASK) >> WLAN_POWER_REG_DEBUG_EN_LSB)
+#define WLAN_POWER_REG_DEBUG_EN_SET(x)           (((x) << WLAN_POWER_REG_DEBUG_EN_LSB) & WLAN_POWER_REG_DEBUG_EN_MASK)
+#define WLAN_POWER_REG_WLAN_BB_PWD_EN_MSB        13
+#define WLAN_POWER_REG_WLAN_BB_PWD_EN_LSB        13
+#define WLAN_POWER_REG_WLAN_BB_PWD_EN_MASK       0x00002000
+#define WLAN_POWER_REG_WLAN_BB_PWD_EN_GET(x)     (((x) & WLAN_POWER_REG_WLAN_BB_PWD_EN_MASK) >> WLAN_POWER_REG_WLAN_BB_PWD_EN_LSB)
+#define WLAN_POWER_REG_WLAN_BB_PWD_EN_SET(x)     (((x) << WLAN_POWER_REG_WLAN_BB_PWD_EN_LSB) & WLAN_POWER_REG_WLAN_BB_PWD_EN_MASK)
+#define WLAN_POWER_REG_WLAN_MAC_PWD_EN_MSB       12
+#define WLAN_POWER_REG_WLAN_MAC_PWD_EN_LSB       12
+#define WLAN_POWER_REG_WLAN_MAC_PWD_EN_MASK      0x00001000
+#define WLAN_POWER_REG_WLAN_MAC_PWD_EN_GET(x)    (((x) & WLAN_POWER_REG_WLAN_MAC_PWD_EN_MASK) >> WLAN_POWER_REG_WLAN_MAC_PWD_EN_LSB)
+#define WLAN_POWER_REG_WLAN_MAC_PWD_EN_SET(x)    (((x) << WLAN_POWER_REG_WLAN_MAC_PWD_EN_LSB) & WLAN_POWER_REG_WLAN_MAC_PWD_EN_MASK)
+#define WLAN_POWER_REG_VLVL_MSB                  11
+#define WLAN_POWER_REG_VLVL_LSB                  8
+#define WLAN_POWER_REG_VLVL_MASK                 0x00000f00
+#define WLAN_POWER_REG_VLVL_GET(x)               (((x) & WLAN_POWER_REG_VLVL_MASK) >> WLAN_POWER_REG_VLVL_LSB)
+#define WLAN_POWER_REG_VLVL_SET(x)               (((x) << WLAN_POWER_REG_VLVL_LSB) & WLAN_POWER_REG_VLVL_MASK)
+#define WLAN_POWER_REG_CPU_INT_ENABLE_MSB        7
+#define WLAN_POWER_REG_CPU_INT_ENABLE_LSB        7
+#define WLAN_POWER_REG_CPU_INT_ENABLE_MASK       0x00000080
+#define WLAN_POWER_REG_CPU_INT_ENABLE_GET(x)     (((x) & WLAN_POWER_REG_CPU_INT_ENABLE_MASK) >> WLAN_POWER_REG_CPU_INT_ENABLE_LSB)
+#define WLAN_POWER_REG_CPU_INT_ENABLE_SET(x)     (((x) << WLAN_POWER_REG_CPU_INT_ENABLE_LSB) & WLAN_POWER_REG_CPU_INT_ENABLE_MASK)
+#define WLAN_POWER_REG_WLAN_ISO_DIS_MSB          6
+#define WLAN_POWER_REG_WLAN_ISO_DIS_LSB          6
+#define WLAN_POWER_REG_WLAN_ISO_DIS_MASK         0x00000040
+#define WLAN_POWER_REG_WLAN_ISO_DIS_GET(x)       (((x) & WLAN_POWER_REG_WLAN_ISO_DIS_MASK) >> WLAN_POWER_REG_WLAN_ISO_DIS_LSB)
+#define WLAN_POWER_REG_WLAN_ISO_DIS_SET(x)       (((x) << WLAN_POWER_REG_WLAN_ISO_DIS_LSB) & WLAN_POWER_REG_WLAN_ISO_DIS_MASK)
+#define WLAN_POWER_REG_WLAN_ISO_CNTL_MSB         5
+#define WLAN_POWER_REG_WLAN_ISO_CNTL_LSB         5
+#define WLAN_POWER_REG_WLAN_ISO_CNTL_MASK        0x00000020
+#define WLAN_POWER_REG_WLAN_ISO_CNTL_GET(x)      (((x) & WLAN_POWER_REG_WLAN_ISO_CNTL_MASK) >> WLAN_POWER_REG_WLAN_ISO_CNTL_LSB)
+#define WLAN_POWER_REG_WLAN_ISO_CNTL_SET(x)      (((x) << WLAN_POWER_REG_WLAN_ISO_CNTL_LSB) & WLAN_POWER_REG_WLAN_ISO_CNTL_MASK)
+#define WLAN_POWER_REG_RADIO_PWD_EN_MSB          4
+#define WLAN_POWER_REG_RADIO_PWD_EN_LSB          4
+#define WLAN_POWER_REG_RADIO_PWD_EN_MASK         0x00000010
+#define WLAN_POWER_REG_RADIO_PWD_EN_GET(x)       (((x) & WLAN_POWER_REG_RADIO_PWD_EN_MASK) >> WLAN_POWER_REG_RADIO_PWD_EN_LSB)
+#define WLAN_POWER_REG_RADIO_PWD_EN_SET(x)       (((x) << WLAN_POWER_REG_RADIO_PWD_EN_LSB) & WLAN_POWER_REG_RADIO_PWD_EN_MASK)
+#define WLAN_POWER_REG_SOC_ISO_EN_MSB            3
+#define WLAN_POWER_REG_SOC_ISO_EN_LSB            3
+#define WLAN_POWER_REG_SOC_ISO_EN_MASK           0x00000008
+#define WLAN_POWER_REG_SOC_ISO_EN_GET(x)         (((x) & WLAN_POWER_REG_SOC_ISO_EN_MASK) >> WLAN_POWER_REG_SOC_ISO_EN_LSB)
+#define WLAN_POWER_REG_SOC_ISO_EN_SET(x)         (((x) << WLAN_POWER_REG_SOC_ISO_EN_LSB) & WLAN_POWER_REG_SOC_ISO_EN_MASK)
+#define WLAN_POWER_REG_WLAN_ISO_EN_MSB           2
+#define WLAN_POWER_REG_WLAN_ISO_EN_LSB           2
+#define WLAN_POWER_REG_WLAN_ISO_EN_MASK          0x00000004
+#define WLAN_POWER_REG_WLAN_ISO_EN_GET(x)        (((x) & WLAN_POWER_REG_WLAN_ISO_EN_MASK) >> WLAN_POWER_REG_WLAN_ISO_EN_LSB)
+#define WLAN_POWER_REG_WLAN_ISO_EN_SET(x)        (((x) << WLAN_POWER_REG_WLAN_ISO_EN_LSB) & WLAN_POWER_REG_WLAN_ISO_EN_MASK)
+#define WLAN_POWER_REG_WLAN_PWD_EN_MSB           1
+#define WLAN_POWER_REG_WLAN_PWD_EN_LSB           1
+#define WLAN_POWER_REG_WLAN_PWD_EN_MASK          0x00000002
+#define WLAN_POWER_REG_WLAN_PWD_EN_GET(x)        (((x) & WLAN_POWER_REG_WLAN_PWD_EN_MASK) >> WLAN_POWER_REG_WLAN_PWD_EN_LSB)
+#define WLAN_POWER_REG_WLAN_PWD_EN_SET(x)        (((x) << WLAN_POWER_REG_WLAN_PWD_EN_LSB) & WLAN_POWER_REG_WLAN_PWD_EN_MASK)
+#define WLAN_POWER_REG_POWER_EN_MSB              0
+#define WLAN_POWER_REG_POWER_EN_LSB              0
+#define WLAN_POWER_REG_POWER_EN_MASK             0x00000001
+#define WLAN_POWER_REG_POWER_EN_GET(x)           (((x) & WLAN_POWER_REG_POWER_EN_MASK) >> WLAN_POWER_REG_POWER_EN_LSB)
+#define WLAN_POWER_REG_POWER_EN_SET(x)           (((x) << WLAN_POWER_REG_POWER_EN_LSB) & WLAN_POWER_REG_POWER_EN_MASK)
+
+#define WLAN_CORE_CLK_CTRL_ADDRESS               0x00000110
+#define WLAN_CORE_CLK_CTRL_OFFSET                0x00000110
+#define WLAN_CORE_CLK_CTRL_DIV_MSB               2
+#define WLAN_CORE_CLK_CTRL_DIV_LSB               0
+#define WLAN_CORE_CLK_CTRL_DIV_MASK              0x00000007
+#define WLAN_CORE_CLK_CTRL_DIV_GET(x)            (((x) & WLAN_CORE_CLK_CTRL_DIV_MASK) >> WLAN_CORE_CLK_CTRL_DIV_LSB)
+#define WLAN_CORE_CLK_CTRL_DIV_SET(x)            (((x) << WLAN_CORE_CLK_CTRL_DIV_LSB) & WLAN_CORE_CLK_CTRL_DIV_MASK)
+
+#define WLAN_GPIO_WAKEUP_CONTROL_ADDRESS         0x00000114
+#define WLAN_GPIO_WAKEUP_CONTROL_OFFSET          0x00000114
+#define WLAN_GPIO_WAKEUP_CONTROL_ENABLE_MSB      0
+#define WLAN_GPIO_WAKEUP_CONTROL_ENABLE_LSB      0
+#define WLAN_GPIO_WAKEUP_CONTROL_ENABLE_MASK     0x00000001
+#define WLAN_GPIO_WAKEUP_CONTROL_ENABLE_GET(x)   (((x) & WLAN_GPIO_WAKEUP_CONTROL_ENABLE_MASK) >> WLAN_GPIO_WAKEUP_CONTROL_ENABLE_LSB)
+#define WLAN_GPIO_WAKEUP_CONTROL_ENABLE_SET(x)   (((x) << WLAN_GPIO_WAKEUP_CONTROL_ENABLE_LSB) & WLAN_GPIO_WAKEUP_CONTROL_ENABLE_MASK)
+
+#define HT_ADDRESS                               0x00000118
+#define HT_OFFSET                                0x00000118
+#define HT_MODE_MSB                              0
+#define HT_MODE_LSB                              0
+#define HT_MODE_MASK                             0x00000001
+#define HT_MODE_GET(x)                           (((x) & HT_MODE_MASK) >> HT_MODE_LSB)
+#define HT_MODE_SET(x)                           (((x) << HT_MODE_LSB) & HT_MODE_MASK)
+
+#define MAC_PCU_TSF_L32_ADDRESS                  0x0000011c
+#define MAC_PCU_TSF_L32_OFFSET                   0x0000011c
+#define MAC_PCU_TSF_L32_VALUE_MSB                31
+#define MAC_PCU_TSF_L32_VALUE_LSB                0
+#define MAC_PCU_TSF_L32_VALUE_MASK               0xffffffff
+#define MAC_PCU_TSF_L32_VALUE_GET(x)             (((x) & MAC_PCU_TSF_L32_VALUE_MASK) >> MAC_PCU_TSF_L32_VALUE_LSB)
+#define MAC_PCU_TSF_L32_VALUE_SET(x)             (((x) << MAC_PCU_TSF_L32_VALUE_LSB) & MAC_PCU_TSF_L32_VALUE_MASK)
+
+#define MAC_PCU_TSF_U32_ADDRESS                  0x00000120
+#define MAC_PCU_TSF_U32_OFFSET                   0x00000120
+#define MAC_PCU_TSF_U32_VALUE_MSB                31
+#define MAC_PCU_TSF_U32_VALUE_LSB                0
+#define MAC_PCU_TSF_U32_VALUE_MASK               0xffffffff
+#define MAC_PCU_TSF_U32_VALUE_GET(x)             (((x) & MAC_PCU_TSF_U32_VALUE_MASK) >> MAC_PCU_TSF_U32_VALUE_LSB)
+#define MAC_PCU_TSF_U32_VALUE_SET(x)             (((x) << MAC_PCU_TSF_U32_VALUE_LSB) & MAC_PCU_TSF_U32_VALUE_MASK)
+
+#define MAC_PCU_WBTIMER_ADDRESS                  0x00000124
+#define MAC_PCU_WBTIMER_OFFSET                   0x00000124
+#define MAC_PCU_WBTIMER_VALUE_MSB                31
+#define MAC_PCU_WBTIMER_VALUE_LSB                0
+#define MAC_PCU_WBTIMER_VALUE_MASK               0xffffffff
+#define MAC_PCU_WBTIMER_VALUE_GET(x)             (((x) & MAC_PCU_WBTIMER_VALUE_MASK) >> MAC_PCU_WBTIMER_VALUE_LSB)
+#define MAC_PCU_WBTIMER_VALUE_SET(x)             (((x) << MAC_PCU_WBTIMER_VALUE_LSB) & MAC_PCU_WBTIMER_VALUE_MASK)
+
+#define MAC_PCU_GENERIC_TIMERS_ADDRESS           0x00000140
+#define MAC_PCU_GENERIC_TIMERS_OFFSET            0x00000140
+#define MAC_PCU_GENERIC_TIMERS_DATA_MSB          31
+#define MAC_PCU_GENERIC_TIMERS_DATA_LSB          0
+#define MAC_PCU_GENERIC_TIMERS_DATA_MASK         0xffffffff
+#define MAC_PCU_GENERIC_TIMERS_DATA_GET(x)       (((x) & MAC_PCU_GENERIC_TIMERS_DATA_MASK) >> MAC_PCU_GENERIC_TIMERS_DATA_LSB)
+#define MAC_PCU_GENERIC_TIMERS_DATA_SET(x)       (((x) << MAC_PCU_GENERIC_TIMERS_DATA_LSB) & MAC_PCU_GENERIC_TIMERS_DATA_MASK)
+
+#define MAC_PCU_GENERIC_TIMERS_MODE_ADDRESS      0x00000180
+#define MAC_PCU_GENERIC_TIMERS_MODE_OFFSET       0x00000180
+#define MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_MSB   15
+#define MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_LSB   0
+#define MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_MASK  0x0000ffff
+#define MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_GET(x) (((x) & MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_MASK) >> MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_LSB)
+#define MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_SET(x) (((x) << MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_LSB) & MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_MASK)
+
+#define MAC_PCU_GENERIC_TIMERS2_ADDRESS          0x000001c0
+#define MAC_PCU_GENERIC_TIMERS2_OFFSET           0x000001c0
+#define MAC_PCU_GENERIC_TIMERS2_DATA_MSB         31
+#define MAC_PCU_GENERIC_TIMERS2_DATA_LSB         0
+#define MAC_PCU_GENERIC_TIMERS2_DATA_MASK        0xffffffff
+#define MAC_PCU_GENERIC_TIMERS2_DATA_GET(x)      (((x) & MAC_PCU_GENERIC_TIMERS2_DATA_MASK) >> MAC_PCU_GENERIC_TIMERS2_DATA_LSB)
+#define MAC_PCU_GENERIC_TIMERS2_DATA_SET(x)      (((x) << MAC_PCU_GENERIC_TIMERS2_DATA_LSB) & MAC_PCU_GENERIC_TIMERS2_DATA_MASK)
+
+#define MAC_PCU_GENERIC_TIMERS_MODE2_ADDRESS     0x00000200
+#define MAC_PCU_GENERIC_TIMERS_MODE2_OFFSET      0x00000200
+#define MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_MSB  15
+#define MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_LSB  0
+#define MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_MASK 0x0000ffff
+#define MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_GET(x) (((x) & MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_MASK) >> MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_LSB)
+#define MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_SET(x) (((x) << MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_LSB) & MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_MASK)
+
+#define MAC_PCU_SLP1_ADDRESS                     0x00000204
+#define MAC_PCU_SLP1_OFFSET                      0x00000204
+#define MAC_PCU_SLP1_ASSUME_DTIM_MSB             19
+#define MAC_PCU_SLP1_ASSUME_DTIM_LSB             19
+#define MAC_PCU_SLP1_ASSUME_DTIM_MASK            0x00080000
+#define MAC_PCU_SLP1_ASSUME_DTIM_GET(x)          (((x) & MAC_PCU_SLP1_ASSUME_DTIM_MASK) >> MAC_PCU_SLP1_ASSUME_DTIM_LSB)
+#define MAC_PCU_SLP1_ASSUME_DTIM_SET(x)          (((x) << MAC_PCU_SLP1_ASSUME_DTIM_LSB) & MAC_PCU_SLP1_ASSUME_DTIM_MASK)
+#define MAC_PCU_SLP1_CAB_TIMEOUT_MSB             15
+#define MAC_PCU_SLP1_CAB_TIMEOUT_LSB             0
+#define MAC_PCU_SLP1_CAB_TIMEOUT_MASK            0x0000ffff
+#define MAC_PCU_SLP1_CAB_TIMEOUT_GET(x)          (((x) & MAC_PCU_SLP1_CAB_TIMEOUT_MASK) >> MAC_PCU_SLP1_CAB_TIMEOUT_LSB)
+#define MAC_PCU_SLP1_CAB_TIMEOUT_SET(x)          (((x) << MAC_PCU_SLP1_CAB_TIMEOUT_LSB) & MAC_PCU_SLP1_CAB_TIMEOUT_MASK)
+
+#define MAC_PCU_SLP2_ADDRESS                     0x00000208
+#define MAC_PCU_SLP2_OFFSET                      0x00000208
+#define MAC_PCU_SLP2_BEACON_TIMEOUT_MSB          15
+#define MAC_PCU_SLP2_BEACON_TIMEOUT_LSB          0
+#define MAC_PCU_SLP2_BEACON_TIMEOUT_MASK         0x0000ffff
+#define MAC_PCU_SLP2_BEACON_TIMEOUT_GET(x)       (((x) & MAC_PCU_SLP2_BEACON_TIMEOUT_MASK) >> MAC_PCU_SLP2_BEACON_TIMEOUT_LSB)
+#define MAC_PCU_SLP2_BEACON_TIMEOUT_SET(x)       (((x) << MAC_PCU_SLP2_BEACON_TIMEOUT_LSB) & MAC_PCU_SLP2_BEACON_TIMEOUT_MASK)
+
+#define MAC_PCU_RESET_TSF_ADDRESS                0x0000020c
+#define MAC_PCU_RESET_TSF_OFFSET                 0x0000020c
+#define MAC_PCU_RESET_TSF_ONE_SHOT2_MSB          25
+#define MAC_PCU_RESET_TSF_ONE_SHOT2_LSB          25
+#define MAC_PCU_RESET_TSF_ONE_SHOT2_MASK         0x02000000
+#define MAC_PCU_RESET_TSF_ONE_SHOT2_GET(x)       (((x) & MAC_PCU_RESET_TSF_ONE_SHOT2_MASK) >> MAC_PCU_RESET_TSF_ONE_SHOT2_LSB)
+#define MAC_PCU_RESET_TSF_ONE_SHOT2_SET(x)       (((x) << MAC_PCU_RESET_TSF_ONE_SHOT2_LSB) & MAC_PCU_RESET_TSF_ONE_SHOT2_MASK)
+#define MAC_PCU_RESET_TSF_ONE_SHOT_MSB           24
+#define MAC_PCU_RESET_TSF_ONE_SHOT_LSB           24
+#define MAC_PCU_RESET_TSF_ONE_SHOT_MASK          0x01000000
+#define MAC_PCU_RESET_TSF_ONE_SHOT_GET(x)        (((x) & MAC_PCU_RESET_TSF_ONE_SHOT_MASK) >> MAC_PCU_RESET_TSF_ONE_SHOT_LSB)
+#define MAC_PCU_RESET_TSF_ONE_SHOT_SET(x)        (((x) << MAC_PCU_RESET_TSF_ONE_SHOT_LSB) & MAC_PCU_RESET_TSF_ONE_SHOT_MASK)
+
+#define MAC_PCU_TSF_ADD_PLL_ADDRESS              0x00000210
+#define MAC_PCU_TSF_ADD_PLL_OFFSET               0x00000210
+#define MAC_PCU_TSF_ADD_PLL_VALUE_MSB            7
+#define MAC_PCU_TSF_ADD_PLL_VALUE_LSB            0
+#define MAC_PCU_TSF_ADD_PLL_VALUE_MASK           0x000000ff
+#define MAC_PCU_TSF_ADD_PLL_VALUE_GET(x)         (((x) & MAC_PCU_TSF_ADD_PLL_VALUE_MASK) >> MAC_PCU_TSF_ADD_PLL_VALUE_LSB)
+#define MAC_PCU_TSF_ADD_PLL_VALUE_SET(x)         (((x) << MAC_PCU_TSF_ADD_PLL_VALUE_LSB) & MAC_PCU_TSF_ADD_PLL_VALUE_MASK)
+
+#define SLEEP_RETENTION_ADDRESS                  0x00000214
+#define SLEEP_RETENTION_OFFSET                   0x00000214
+#define SLEEP_RETENTION_TIME_MSB                 9
+#define SLEEP_RETENTION_TIME_LSB                 2
+#define SLEEP_RETENTION_TIME_MASK                0x000003fc
+#define SLEEP_RETENTION_TIME_GET(x)              (((x) & SLEEP_RETENTION_TIME_MASK) >> SLEEP_RETENTION_TIME_LSB)
+#define SLEEP_RETENTION_TIME_SET(x)              (((x) << SLEEP_RETENTION_TIME_LSB) & SLEEP_RETENTION_TIME_MASK)
+#define SLEEP_RETENTION_MODE_MSB                 1
+#define SLEEP_RETENTION_MODE_LSB                 1
+#define SLEEP_RETENTION_MODE_MASK                0x00000002
+#define SLEEP_RETENTION_MODE_GET(x)              (((x) & SLEEP_RETENTION_MODE_MASK) >> SLEEP_RETENTION_MODE_LSB)
+#define SLEEP_RETENTION_MODE_SET(x)              (((x) << SLEEP_RETENTION_MODE_LSB) & SLEEP_RETENTION_MODE_MASK)
+#define SLEEP_RETENTION_ENABLE_MSB               0
+#define SLEEP_RETENTION_ENABLE_LSB               0
+#define SLEEP_RETENTION_ENABLE_MASK              0x00000001
+#define SLEEP_RETENTION_ENABLE_GET(x)            (((x) & SLEEP_RETENTION_ENABLE_MASK) >> SLEEP_RETENTION_ENABLE_LSB)
+#define SLEEP_RETENTION_ENABLE_SET(x)            (((x) << SLEEP_RETENTION_ENABLE_LSB) & SLEEP_RETENTION_ENABLE_MASK)
+
+#define BTCOEXCTRL_ADDRESS                       0x00000218
+#define BTCOEXCTRL_OFFSET                        0x00000218
+#define BTCOEXCTRL_WBTIMER_ENABLE_MSB            26
+#define BTCOEXCTRL_WBTIMER_ENABLE_LSB            26
+#define BTCOEXCTRL_WBTIMER_ENABLE_MASK           0x04000000
+#define BTCOEXCTRL_WBTIMER_ENABLE_GET(x)         (((x) & BTCOEXCTRL_WBTIMER_ENABLE_MASK) >> BTCOEXCTRL_WBTIMER_ENABLE_LSB)
+#define BTCOEXCTRL_WBTIMER_ENABLE_SET(x)         (((x) << BTCOEXCTRL_WBTIMER_ENABLE_LSB) & BTCOEXCTRL_WBTIMER_ENABLE_MASK)
+#define BTCOEXCTRL_WBSYNC_ON_BEACON_MSB          25
+#define BTCOEXCTRL_WBSYNC_ON_BEACON_LSB          25
+#define BTCOEXCTRL_WBSYNC_ON_BEACON_MASK         0x02000000
+#define BTCOEXCTRL_WBSYNC_ON_BEACON_GET(x)       (((x) & BTCOEXCTRL_WBSYNC_ON_BEACON_MASK) >> BTCOEXCTRL_WBSYNC_ON_BEACON_LSB)
+#define BTCOEXCTRL_WBSYNC_ON_BEACON_SET(x)       (((x) << BTCOEXCTRL_WBSYNC_ON_BEACON_LSB) & BTCOEXCTRL_WBSYNC_ON_BEACON_MASK)
+#define BTCOEXCTRL_PTA_MODE_MSB                  24
+#define BTCOEXCTRL_PTA_MODE_LSB                  23
+#define BTCOEXCTRL_PTA_MODE_MASK                 0x01800000
+#define BTCOEXCTRL_PTA_MODE_GET(x)               (((x) & BTCOEXCTRL_PTA_MODE_MASK) >> BTCOEXCTRL_PTA_MODE_LSB)
+#define BTCOEXCTRL_PTA_MODE_SET(x)               (((x) << BTCOEXCTRL_PTA_MODE_LSB) & BTCOEXCTRL_PTA_MODE_MASK)
+#define BTCOEXCTRL_FREQ_TIME_MSB                 22
+#define BTCOEXCTRL_FREQ_TIME_LSB                 18
+#define BTCOEXCTRL_FREQ_TIME_MASK                0x007c0000
+#define BTCOEXCTRL_FREQ_TIME_GET(x)              (((x) & BTCOEXCTRL_FREQ_TIME_MASK) >> BTCOEXCTRL_FREQ_TIME_LSB)
+#define BTCOEXCTRL_FREQ_TIME_SET(x)              (((x) << BTCOEXCTRL_FREQ_TIME_LSB) & BTCOEXCTRL_FREQ_TIME_MASK)
+#define BTCOEXCTRL_PRIORITY_TIME_MSB             17
+#define BTCOEXCTRL_PRIORITY_TIME_LSB             12
+#define BTCOEXCTRL_PRIORITY_TIME_MASK            0x0003f000
+#define BTCOEXCTRL_PRIORITY_TIME_GET(x)          (((x) & BTCOEXCTRL_PRIORITY_TIME_MASK) >> BTCOEXCTRL_PRIORITY_TIME_LSB)
+#define BTCOEXCTRL_PRIORITY_TIME_SET(x)          (((x) << BTCOEXCTRL_PRIORITY_TIME_LSB) & BTCOEXCTRL_PRIORITY_TIME_MASK)
+#define BTCOEXCTRL_SYNC_DET_EN_MSB               11
+#define BTCOEXCTRL_SYNC_DET_EN_LSB               11
+#define BTCOEXCTRL_SYNC_DET_EN_MASK              0x00000800
+#define BTCOEXCTRL_SYNC_DET_EN_GET(x)            (((x) & BTCOEXCTRL_SYNC_DET_EN_MASK) >> BTCOEXCTRL_SYNC_DET_EN_LSB)
+#define BTCOEXCTRL_SYNC_DET_EN_SET(x)            (((x) << BTCOEXCTRL_SYNC_DET_EN_LSB) & BTCOEXCTRL_SYNC_DET_EN_MASK)
+#define BTCOEXCTRL_IDLE_CNT_EN_MSB               10
+#define BTCOEXCTRL_IDLE_CNT_EN_LSB               10
+#define BTCOEXCTRL_IDLE_CNT_EN_MASK              0x00000400
+#define BTCOEXCTRL_IDLE_CNT_EN_GET(x)            (((x) & BTCOEXCTRL_IDLE_CNT_EN_MASK) >> BTCOEXCTRL_IDLE_CNT_EN_LSB)
+#define BTCOEXCTRL_IDLE_CNT_EN_SET(x)            (((x) << BTCOEXCTRL_IDLE_CNT_EN_LSB) & BTCOEXCTRL_IDLE_CNT_EN_MASK)
+#define BTCOEXCTRL_FRAME_CNT_EN_MSB              9
+#define BTCOEXCTRL_FRAME_CNT_EN_LSB              9
+#define BTCOEXCTRL_FRAME_CNT_EN_MASK             0x00000200
+#define BTCOEXCTRL_FRAME_CNT_EN_GET(x)           (((x) & BTCOEXCTRL_FRAME_CNT_EN_MASK) >> BTCOEXCTRL_FRAME_CNT_EN_LSB)
+#define BTCOEXCTRL_FRAME_CNT_EN_SET(x)           (((x) << BTCOEXCTRL_FRAME_CNT_EN_LSB) & BTCOEXCTRL_FRAME_CNT_EN_MASK)
+#define BTCOEXCTRL_CLK_CNT_EN_MSB                8
+#define BTCOEXCTRL_CLK_CNT_EN_LSB                8
+#define BTCOEXCTRL_CLK_CNT_EN_MASK               0x00000100
+#define BTCOEXCTRL_CLK_CNT_EN_GET(x)             (((x) & BTCOEXCTRL_CLK_CNT_EN_MASK) >> BTCOEXCTRL_CLK_CNT_EN_LSB)
+#define BTCOEXCTRL_CLK_CNT_EN_SET(x)             (((x) << BTCOEXCTRL_CLK_CNT_EN_LSB) & BTCOEXCTRL_CLK_CNT_EN_MASK)
+#define BTCOEXCTRL_GAP_MSB                       7
+#define BTCOEXCTRL_GAP_LSB                       0
+#define BTCOEXCTRL_GAP_MASK                      0x000000ff
+#define BTCOEXCTRL_GAP_GET(x)                    (((x) & BTCOEXCTRL_GAP_MASK) >> BTCOEXCTRL_GAP_LSB)
+#define BTCOEXCTRL_GAP_SET(x)                    (((x) << BTCOEXCTRL_GAP_LSB) & BTCOEXCTRL_GAP_MASK)
+
+#define WBSYNC_PRIORITY1_ADDRESS                 0x0000021c
+#define WBSYNC_PRIORITY1_OFFSET                  0x0000021c
+#define WBSYNC_PRIORITY1_BITMAP_MSB              31
+#define WBSYNC_PRIORITY1_BITMAP_LSB              0
+#define WBSYNC_PRIORITY1_BITMAP_MASK             0xffffffff
+#define WBSYNC_PRIORITY1_BITMAP_GET(x)           (((x) & WBSYNC_PRIORITY1_BITMAP_MASK) >> WBSYNC_PRIORITY1_BITMAP_LSB)
+#define WBSYNC_PRIORITY1_BITMAP_SET(x)           (((x) << WBSYNC_PRIORITY1_BITMAP_LSB) & WBSYNC_PRIORITY1_BITMAP_MASK)
+
+#define WBSYNC_PRIORITY2_ADDRESS                 0x00000220
+#define WBSYNC_PRIORITY2_OFFSET                  0x00000220
+#define WBSYNC_PRIORITY2_BITMAP_MSB              31
+#define WBSYNC_PRIORITY2_BITMAP_LSB              0
+#define WBSYNC_PRIORITY2_BITMAP_MASK             0xffffffff
+#define WBSYNC_PRIORITY2_BITMAP_GET(x)           (((x) & WBSYNC_PRIORITY2_BITMAP_MASK) >> WBSYNC_PRIORITY2_BITMAP_LSB)
+#define WBSYNC_PRIORITY2_BITMAP_SET(x)           (((x) << WBSYNC_PRIORITY2_BITMAP_LSB) & WBSYNC_PRIORITY2_BITMAP_MASK)
+
+#define WBSYNC_PRIORITY3_ADDRESS                 0x00000224
+#define WBSYNC_PRIORITY3_OFFSET                  0x00000224
+#define WBSYNC_PRIORITY3_BITMAP_MSB              31
+#define WBSYNC_PRIORITY3_BITMAP_LSB              0
+#define WBSYNC_PRIORITY3_BITMAP_MASK             0xffffffff
+#define WBSYNC_PRIORITY3_BITMAP_GET(x)           (((x) & WBSYNC_PRIORITY3_BITMAP_MASK) >> WBSYNC_PRIORITY3_BITMAP_LSB)
+#define WBSYNC_PRIORITY3_BITMAP_SET(x)           (((x) << WBSYNC_PRIORITY3_BITMAP_LSB) & WBSYNC_PRIORITY3_BITMAP_MASK)
+
+#define BTCOEX0_ADDRESS                          0x00000228
+#define BTCOEX0_OFFSET                           0x00000228
+#define BTCOEX0_SYNC_DUR_MSB                     7
+#define BTCOEX0_SYNC_DUR_LSB                     0
+#define BTCOEX0_SYNC_DUR_MASK                    0x000000ff
+#define BTCOEX0_SYNC_DUR_GET(x)                  (((x) & BTCOEX0_SYNC_DUR_MASK) >> BTCOEX0_SYNC_DUR_LSB)
+#define BTCOEX0_SYNC_DUR_SET(x)                  (((x) << BTCOEX0_SYNC_DUR_LSB) & BTCOEX0_SYNC_DUR_MASK)
+
+#define BTCOEX1_ADDRESS                          0x0000022c
+#define BTCOEX1_OFFSET                           0x0000022c
+#define BTCOEX1_CLK_THRES_MSB                    20
+#define BTCOEX1_CLK_THRES_LSB                    0
+#define BTCOEX1_CLK_THRES_MASK                   0x001fffff
+#define BTCOEX1_CLK_THRES_GET(x)                 (((x) & BTCOEX1_CLK_THRES_MASK) >> BTCOEX1_CLK_THRES_LSB)
+#define BTCOEX1_CLK_THRES_SET(x)                 (((x) << BTCOEX1_CLK_THRES_LSB) & BTCOEX1_CLK_THRES_MASK)
+
+#define BTCOEX2_ADDRESS                          0x00000230
+#define BTCOEX2_OFFSET                           0x00000230
+#define BTCOEX2_FRAME_THRES_MSB                  7
+#define BTCOEX2_FRAME_THRES_LSB                  0
+#define BTCOEX2_FRAME_THRES_MASK                 0x000000ff
+#define BTCOEX2_FRAME_THRES_GET(x)               (((x) & BTCOEX2_FRAME_THRES_MASK) >> BTCOEX2_FRAME_THRES_LSB)
+#define BTCOEX2_FRAME_THRES_SET(x)               (((x) << BTCOEX2_FRAME_THRES_LSB) & BTCOEX2_FRAME_THRES_MASK)
+
+#define BTCOEX3_ADDRESS                          0x00000234
+#define BTCOEX3_OFFSET                           0x00000234
+#define BTCOEX3_CLK_CNT_MSB                      20
+#define BTCOEX3_CLK_CNT_LSB                      0
+#define BTCOEX3_CLK_CNT_MASK                     0x001fffff
+#define BTCOEX3_CLK_CNT_GET(x)                   (((x) & BTCOEX3_CLK_CNT_MASK) >> BTCOEX3_CLK_CNT_LSB)
+#define BTCOEX3_CLK_CNT_SET(x)                   (((x) << BTCOEX3_CLK_CNT_LSB) & BTCOEX3_CLK_CNT_MASK)
+
+#define BTCOEX4_ADDRESS                          0x00000238
+#define BTCOEX4_OFFSET                           0x00000238
+#define BTCOEX4_FRAME_CNT_MSB                    7
+#define BTCOEX4_FRAME_CNT_LSB                    0
+#define BTCOEX4_FRAME_CNT_MASK                   0x000000ff
+#define BTCOEX4_FRAME_CNT_GET(x)                 (((x) & BTCOEX4_FRAME_CNT_MASK) >> BTCOEX4_FRAME_CNT_LSB)
+#define BTCOEX4_FRAME_CNT_SET(x)                 (((x) << BTCOEX4_FRAME_CNT_LSB) & BTCOEX4_FRAME_CNT_MASK)
+
+#define BTCOEX5_ADDRESS                          0x0000023c
+#define BTCOEX5_OFFSET                           0x0000023c
+#define BTCOEX5_IDLE_CNT_MSB                     15
+#define BTCOEX5_IDLE_CNT_LSB                     0
+#define BTCOEX5_IDLE_CNT_MASK                    0x0000ffff
+#define BTCOEX5_IDLE_CNT_GET(x)                  (((x) & BTCOEX5_IDLE_CNT_MASK) >> BTCOEX5_IDLE_CNT_LSB)
+#define BTCOEX5_IDLE_CNT_SET(x)                  (((x) << BTCOEX5_IDLE_CNT_LSB) & BTCOEX5_IDLE_CNT_MASK)
+
+#define BTCOEX6_ADDRESS                          0x00000240
+#define BTCOEX6_OFFSET                           0x00000240
+#define BTCOEX6_IDLE_RESET_LVL_BITMAP_MSB        31
+#define BTCOEX6_IDLE_RESET_LVL_BITMAP_LSB        0
+#define BTCOEX6_IDLE_RESET_LVL_BITMAP_MASK       0xffffffff
+#define BTCOEX6_IDLE_RESET_LVL_BITMAP_GET(x)     (((x) & BTCOEX6_IDLE_RESET_LVL_BITMAP_MASK) >> BTCOEX6_IDLE_RESET_LVL_BITMAP_LSB)
+#define BTCOEX6_IDLE_RESET_LVL_BITMAP_SET(x)     (((x) << BTCOEX6_IDLE_RESET_LVL_BITMAP_LSB) & BTCOEX6_IDLE_RESET_LVL_BITMAP_MASK)
+
+#define LOCK_ADDRESS                             0x00000244
+#define LOCK_OFFSET                              0x00000244
+#define LOCK_TLOCK_SLAVE_MSB                     31
+#define LOCK_TLOCK_SLAVE_LSB                     24
+#define LOCK_TLOCK_SLAVE_MASK                    0xff000000
+#define LOCK_TLOCK_SLAVE_GET(x)                  (((x) & LOCK_TLOCK_SLAVE_MASK) >> LOCK_TLOCK_SLAVE_LSB)
+#define LOCK_TLOCK_SLAVE_SET(x)                  (((x) << LOCK_TLOCK_SLAVE_LSB) & LOCK_TLOCK_SLAVE_MASK)
+#define LOCK_TUNLOCK_SLAVE_MSB                   23
+#define LOCK_TUNLOCK_SLAVE_LSB                   16
+#define LOCK_TUNLOCK_SLAVE_MASK                  0x00ff0000
+#define LOCK_TUNLOCK_SLAVE_GET(x)                (((x) & LOCK_TUNLOCK_SLAVE_MASK) >> LOCK_TUNLOCK_SLAVE_LSB)
+#define LOCK_TUNLOCK_SLAVE_SET(x)                (((x) << LOCK_TUNLOCK_SLAVE_LSB) & LOCK_TUNLOCK_SLAVE_MASK)
+#define LOCK_TLOCK_MASTER_MSB                    15
+#define LOCK_TLOCK_MASTER_LSB                    8
+#define LOCK_TLOCK_MASTER_MASK                   0x0000ff00
+#define LOCK_TLOCK_MASTER_GET(x)                 (((x) & LOCK_TLOCK_MASTER_MASK) >> LOCK_TLOCK_MASTER_LSB)
+#define LOCK_TLOCK_MASTER_SET(x)                 (((x) << LOCK_TLOCK_MASTER_LSB) & LOCK_TLOCK_MASTER_MASK)
+#define LOCK_TUNLOCK_MASTER_MSB                  7
+#define LOCK_TUNLOCK_MASTER_LSB                  0
+#define LOCK_TUNLOCK_MASTER_MASK                 0x000000ff
+#define LOCK_TUNLOCK_MASTER_GET(x)               (((x) & LOCK_TUNLOCK_MASTER_MASK) >> LOCK_TUNLOCK_MASTER_LSB)
+#define LOCK_TUNLOCK_MASTER_SET(x)               (((x) << LOCK_TUNLOCK_MASTER_LSB) & LOCK_TUNLOCK_MASTER_MASK)
+
+#define NOLOCK_PRIORITY_ADDRESS                  0x00000248
+#define NOLOCK_PRIORITY_OFFSET                   0x00000248
+#define NOLOCK_PRIORITY_BITMAP_MSB               31
+#define NOLOCK_PRIORITY_BITMAP_LSB               0
+#define NOLOCK_PRIORITY_BITMAP_MASK              0xffffffff
+#define NOLOCK_PRIORITY_BITMAP_GET(x)            (((x) & NOLOCK_PRIORITY_BITMAP_MASK) >> NOLOCK_PRIORITY_BITMAP_LSB)
+#define NOLOCK_PRIORITY_BITMAP_SET(x)            (((x) << NOLOCK_PRIORITY_BITMAP_LSB) & NOLOCK_PRIORITY_BITMAP_MASK)
+
+#define WBSYNC_ADDRESS                           0x0000024c
+#define WBSYNC_OFFSET                            0x0000024c
+#define WBSYNC_BTCLOCK_MSB                       31
+#define WBSYNC_BTCLOCK_LSB                       0
+#define WBSYNC_BTCLOCK_MASK                      0xffffffff
+#define WBSYNC_BTCLOCK_GET(x)                    (((x) & WBSYNC_BTCLOCK_MASK) >> WBSYNC_BTCLOCK_LSB)
+#define WBSYNC_BTCLOCK_SET(x)                    (((x) << WBSYNC_BTCLOCK_LSB) & WBSYNC_BTCLOCK_MASK)
+
+#define WBSYNC1_ADDRESS                          0x00000250
+#define WBSYNC1_OFFSET                           0x00000250
+#define WBSYNC1_BTCLOCK_MSB                      31
+#define WBSYNC1_BTCLOCK_LSB                      0
+#define WBSYNC1_BTCLOCK_MASK                     0xffffffff
+#define WBSYNC1_BTCLOCK_GET(x)                   (((x) & WBSYNC1_BTCLOCK_MASK) >> WBSYNC1_BTCLOCK_LSB)
+#define WBSYNC1_BTCLOCK_SET(x)                   (((x) << WBSYNC1_BTCLOCK_LSB) & WBSYNC1_BTCLOCK_MASK)
+
+#define WBSYNC2_ADDRESS                          0x00000254
+#define WBSYNC2_OFFSET                           0x00000254
+#define WBSYNC2_BTCLOCK_MSB                      31
+#define WBSYNC2_BTCLOCK_LSB                      0
+#define WBSYNC2_BTCLOCK_MASK                     0xffffffff
+#define WBSYNC2_BTCLOCK_GET(x)                   (((x) & WBSYNC2_BTCLOCK_MASK) >> WBSYNC2_BTCLOCK_LSB)
+#define WBSYNC2_BTCLOCK_SET(x)                   (((x) << WBSYNC2_BTCLOCK_LSB) & WBSYNC2_BTCLOCK_MASK)
+
+#define WBSYNC3_ADDRESS                          0x00000258
+#define WBSYNC3_OFFSET                           0x00000258
+#define WBSYNC3_BTCLOCK_MSB                      31
+#define WBSYNC3_BTCLOCK_LSB                      0
+#define WBSYNC3_BTCLOCK_MASK                     0xffffffff
+#define WBSYNC3_BTCLOCK_GET(x)                   (((x) & WBSYNC3_BTCLOCK_MASK) >> WBSYNC3_BTCLOCK_LSB)
+#define WBSYNC3_BTCLOCK_SET(x)                   (((x) << WBSYNC3_BTCLOCK_LSB) & WBSYNC3_BTCLOCK_MASK)
+
+#define WB_TIMER_TARGET_ADDRESS                  0x0000025c
+#define WB_TIMER_TARGET_OFFSET                   0x0000025c
+#define WB_TIMER_TARGET_VALUE_MSB                31
+#define WB_TIMER_TARGET_VALUE_LSB                0
+#define WB_TIMER_TARGET_VALUE_MASK               0xffffffff
+#define WB_TIMER_TARGET_VALUE_GET(x)             (((x) & WB_TIMER_TARGET_VALUE_MASK) >> WB_TIMER_TARGET_VALUE_LSB)
+#define WB_TIMER_TARGET_VALUE_SET(x)             (((x) << WB_TIMER_TARGET_VALUE_LSB) & WB_TIMER_TARGET_VALUE_MASK)
+
+#define WB_TIMER_SLOP_ADDRESS                    0x00000260
+#define WB_TIMER_SLOP_OFFSET                     0x00000260
+#define WB_TIMER_SLOP_VALUE_MSB                  9
+#define WB_TIMER_SLOP_VALUE_LSB                  0
+#define WB_TIMER_SLOP_VALUE_MASK                 0x000003ff
+#define WB_TIMER_SLOP_VALUE_GET(x)               (((x) & WB_TIMER_SLOP_VALUE_MASK) >> WB_TIMER_SLOP_VALUE_LSB)
+#define WB_TIMER_SLOP_VALUE_SET(x)               (((x) << WB_TIMER_SLOP_VALUE_LSB) & WB_TIMER_SLOP_VALUE_MASK)
+
+#define BTCOEX_INT_EN_ADDRESS                    0x00000264
+#define BTCOEX_INT_EN_OFFSET                     0x00000264
+#define BTCOEX_INT_EN_I2C_RECV_OVERFLOW_MSB      11
+#define BTCOEX_INT_EN_I2C_RECV_OVERFLOW_LSB      11
+#define BTCOEX_INT_EN_I2C_RECV_OVERFLOW_MASK     0x00000800
+#define BTCOEX_INT_EN_I2C_RECV_OVERFLOW_GET(x)   (((x) & BTCOEX_INT_EN_I2C_RECV_OVERFLOW_MASK) >> BTCOEX_INT_EN_I2C_RECV_OVERFLOW_LSB)
+#define BTCOEX_INT_EN_I2C_RECV_OVERFLOW_SET(x)   (((x) << BTCOEX_INT_EN_I2C_RECV_OVERFLOW_LSB) & BTCOEX_INT_EN_I2C_RECV_OVERFLOW_MASK)
+#define BTCOEX_INT_EN_I2C_TX_FAILED_MSB          10
+#define BTCOEX_INT_EN_I2C_TX_FAILED_LSB          10
+#define BTCOEX_INT_EN_I2C_TX_FAILED_MASK         0x00000400
+#define BTCOEX_INT_EN_I2C_TX_FAILED_GET(x)       (((x) & BTCOEX_INT_EN_I2C_TX_FAILED_MASK) >> BTCOEX_INT_EN_I2C_TX_FAILED_LSB)
+#define BTCOEX_INT_EN_I2C_TX_FAILED_SET(x)       (((x) << BTCOEX_INT_EN_I2C_TX_FAILED_LSB) & BTCOEX_INT_EN_I2C_TX_FAILED_MASK)
+#define BTCOEX_INT_EN_I2C_MESG_SENT_MSB          9
+#define BTCOEX_INT_EN_I2C_MESG_SENT_LSB          9
+#define BTCOEX_INT_EN_I2C_MESG_SENT_MASK         0x00000200
+#define BTCOEX_INT_EN_I2C_MESG_SENT_GET(x)       (((x) & BTCOEX_INT_EN_I2C_MESG_SENT_MASK) >> BTCOEX_INT_EN_I2C_MESG_SENT_LSB)
+#define BTCOEX_INT_EN_I2C_MESG_SENT_SET(x)       (((x) << BTCOEX_INT_EN_I2C_MESG_SENT_LSB) & BTCOEX_INT_EN_I2C_MESG_SENT_MASK)
+#define BTCOEX_INT_EN_ST_MESG_RECV_MSB           8
+#define BTCOEX_INT_EN_ST_MESG_RECV_LSB           8
+#define BTCOEX_INT_EN_ST_MESG_RECV_MASK          0x00000100
+#define BTCOEX_INT_EN_ST_MESG_RECV_GET(x)        (((x) & BTCOEX_INT_EN_ST_MESG_RECV_MASK) >> BTCOEX_INT_EN_ST_MESG_RECV_LSB)
+#define BTCOEX_INT_EN_ST_MESG_RECV_SET(x)        (((x) << BTCOEX_INT_EN_ST_MESG_RECV_LSB) & BTCOEX_INT_EN_ST_MESG_RECV_MASK)
+#define BTCOEX_INT_EN_WB_TIMER_MSB               7
+#define BTCOEX_INT_EN_WB_TIMER_LSB               7
+#define BTCOEX_INT_EN_WB_TIMER_MASK              0x00000080
+#define BTCOEX_INT_EN_WB_TIMER_GET(x)            (((x) & BTCOEX_INT_EN_WB_TIMER_MASK) >> BTCOEX_INT_EN_WB_TIMER_LSB)
+#define BTCOEX_INT_EN_WB_TIMER_SET(x)            (((x) << BTCOEX_INT_EN_WB_TIMER_LSB) & BTCOEX_INT_EN_WB_TIMER_MASK)
+#define BTCOEX_INT_EN_NOSYNC_MSB                 4
+#define BTCOEX_INT_EN_NOSYNC_LSB                 4
+#define BTCOEX_INT_EN_NOSYNC_MASK                0x00000010
+#define BTCOEX_INT_EN_NOSYNC_GET(x)              (((x) & BTCOEX_INT_EN_NOSYNC_MASK) >> BTCOEX_INT_EN_NOSYNC_LSB)
+#define BTCOEX_INT_EN_NOSYNC_SET(x)              (((x) << BTCOEX_INT_EN_NOSYNC_LSB) & BTCOEX_INT_EN_NOSYNC_MASK)
+#define BTCOEX_INT_EN_SYNC_MSB                   3
+#define BTCOEX_INT_EN_SYNC_LSB                   3
+#define BTCOEX_INT_EN_SYNC_MASK                  0x00000008
+#define BTCOEX_INT_EN_SYNC_GET(x)                (((x) & BTCOEX_INT_EN_SYNC_MASK) >> BTCOEX_INT_EN_SYNC_LSB)
+#define BTCOEX_INT_EN_SYNC_SET(x)                (((x) << BTCOEX_INT_EN_SYNC_LSB) & BTCOEX_INT_EN_SYNC_MASK)
+#define BTCOEX_INT_EN_END_MSB                    2
+#define BTCOEX_INT_EN_END_LSB                    2
+#define BTCOEX_INT_EN_END_MASK                   0x00000004
+#define BTCOEX_INT_EN_END_GET(x)                 (((x) & BTCOEX_INT_EN_END_MASK) >> BTCOEX_INT_EN_END_LSB)
+#define BTCOEX_INT_EN_END_SET(x)                 (((x) << BTCOEX_INT_EN_END_LSB) & BTCOEX_INT_EN_END_MASK)
+#define BTCOEX_INT_EN_FRAME_CNT_MSB              1
+#define BTCOEX_INT_EN_FRAME_CNT_LSB              1
+#define BTCOEX_INT_EN_FRAME_CNT_MASK             0x00000002
+#define BTCOEX_INT_EN_FRAME_CNT_GET(x)           (((x) & BTCOEX_INT_EN_FRAME_CNT_MASK) >> BTCOEX_INT_EN_FRAME_CNT_LSB)
+#define BTCOEX_INT_EN_FRAME_CNT_SET(x)           (((x) << BTCOEX_INT_EN_FRAME_CNT_LSB) & BTCOEX_INT_EN_FRAME_CNT_MASK)
+#define BTCOEX_INT_EN_CLK_CNT_MSB                0
+#define BTCOEX_INT_EN_CLK_CNT_LSB                0
+#define BTCOEX_INT_EN_CLK_CNT_MASK               0x00000001
+#define BTCOEX_INT_EN_CLK_CNT_GET(x)             (((x) & BTCOEX_INT_EN_CLK_CNT_MASK) >> BTCOEX_INT_EN_CLK_CNT_LSB)
+#define BTCOEX_INT_EN_CLK_CNT_SET(x)             (((x) << BTCOEX_INT_EN_CLK_CNT_LSB) & BTCOEX_INT_EN_CLK_CNT_MASK)
+
+#define BTCOEX_INT_STAT_ADDRESS                  0x00000268
+#define BTCOEX_INT_STAT_OFFSET                   0x00000268
+#define BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_MSB    11
+#define BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_LSB    11
+#define BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_MASK   0x00000800
+#define BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_GET(x) (((x) & BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_MASK) >> BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_LSB)
+#define BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_SET(x) (((x) << BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_LSB) & BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_MASK)
+#define BTCOEX_INT_STAT_I2C_TX_FAILED_MSB        10
+#define BTCOEX_INT_STAT_I2C_TX_FAILED_LSB        10
+#define BTCOEX_INT_STAT_I2C_TX_FAILED_MASK       0x00000400
+#define BTCOEX_INT_STAT_I2C_TX_FAILED_GET(x)     (((x) & BTCOEX_INT_STAT_I2C_TX_FAILED_MASK) >> BTCOEX_INT_STAT_I2C_TX_FAILED_LSB)
+#define BTCOEX_INT_STAT_I2C_TX_FAILED_SET(x)     (((x) << BTCOEX_INT_STAT_I2C_TX_FAILED_LSB) & BTCOEX_INT_STAT_I2C_TX_FAILED_MASK)
+#define BTCOEX_INT_STAT_I2C_MESG_SENT_MSB        9
+#define BTCOEX_INT_STAT_I2C_MESG_SENT_LSB        9
+#define BTCOEX_INT_STAT_I2C_MESG_SENT_MASK       0x00000200
+#define BTCOEX_INT_STAT_I2C_MESG_SENT_GET(x)     (((x) & BTCOEX_INT_STAT_I2C_MESG_SENT_MASK) >> BTCOEX_INT_STAT_I2C_MESG_SENT_LSB)
+#define BTCOEX_INT_STAT_I2C_MESG_SENT_SET(x)     (((x) << BTCOEX_INT_STAT_I2C_MESG_SENT_LSB) & BTCOEX_INT_STAT_I2C_MESG_SENT_MASK)
+#define BTCOEX_INT_STAT_I2C_MESG_RECV_MSB        8
+#define BTCOEX_INT_STAT_I2C_MESG_RECV_LSB        8
+#define BTCOEX_INT_STAT_I2C_MESG_RECV_MASK       0x00000100
+#define BTCOEX_INT_STAT_I2C_MESG_RECV_GET(x)     (((x) & BTCOEX_INT_STAT_I2C_MESG_RECV_MASK) >> BTCOEX_INT_STAT_I2C_MESG_RECV_LSB)
+#define BTCOEX_INT_STAT_I2C_MESG_RECV_SET(x)     (((x) << BTCOEX_INT_STAT_I2C_MESG_RECV_LSB) & BTCOEX_INT_STAT_I2C_MESG_RECV_MASK)
+#define BTCOEX_INT_STAT_WB_TIMER_MSB             7
+#define BTCOEX_INT_STAT_WB_TIMER_LSB             7
+#define BTCOEX_INT_STAT_WB_TIMER_MASK            0x00000080
+#define BTCOEX_INT_STAT_WB_TIMER_GET(x)          (((x) & BTCOEX_INT_STAT_WB_TIMER_MASK) >> BTCOEX_INT_STAT_WB_TIMER_LSB)
+#define BTCOEX_INT_STAT_WB_TIMER_SET(x)          (((x) << BTCOEX_INT_STAT_WB_TIMER_LSB) & BTCOEX_INT_STAT_WB_TIMER_MASK)
+#define BTCOEX_INT_STAT_BTPRIORITY_STOMP_MSB     6
+#define BTCOEX_INT_STAT_BTPRIORITY_STOMP_LSB     6
+#define BTCOEX_INT_STAT_BTPRIORITY_STOMP_MASK    0x00000040
+#define BTCOEX_INT_STAT_BTPRIORITY_STOMP_GET(x)  (((x) & BTCOEX_INT_STAT_BTPRIORITY_STOMP_MASK) >> BTCOEX_INT_STAT_BTPRIORITY_STOMP_LSB)
+#define BTCOEX_INT_STAT_BTPRIORITY_STOMP_SET(x)  (((x) << BTCOEX_INT_STAT_BTPRIORITY_STOMP_LSB) & BTCOEX_INT_STAT_BTPRIORITY_STOMP_MASK)
+#define BTCOEX_INT_STAT_BTPRIORITY_MSB           5
+#define BTCOEX_INT_STAT_BTPRIORITY_LSB           5
+#define BTCOEX_INT_STAT_BTPRIORITY_MASK          0x00000020
+#define BTCOEX_INT_STAT_BTPRIORITY_GET(x)        (((x) & BTCOEX_INT_STAT_BTPRIORITY_MASK) >> BTCOEX_INT_STAT_BTPRIORITY_LSB)
+#define BTCOEX_INT_STAT_BTPRIORITY_SET(x)        (((x) << BTCOEX_INT_STAT_BTPRIORITY_LSB) & BTCOEX_INT_STAT_BTPRIORITY_MASK)
+#define BTCOEX_INT_STAT_NOSYNC_MSB               4
+#define BTCOEX_INT_STAT_NOSYNC_LSB               4
+#define BTCOEX_INT_STAT_NOSYNC_MASK              0x00000010
+#define BTCOEX_INT_STAT_NOSYNC_GET(x)            (((x) & BTCOEX_INT_STAT_NOSYNC_MASK) >> BTCOEX_INT_STAT_NOSYNC_LSB)
+#define BTCOEX_INT_STAT_NOSYNC_SET(x)            (((x) << BTCOEX_INT_STAT_NOSYNC_LSB) & BTCOEX_INT_STAT_NOSYNC_MASK)
+#define BTCOEX_INT_STAT_SYNC_MSB                 3
+#define BTCOEX_INT_STAT_SYNC_LSB                 3
+#define BTCOEX_INT_STAT_SYNC_MASK                0x00000008
+#define BTCOEX_INT_STAT_SYNC_GET(x)              (((x) & BTCOEX_INT_STAT_SYNC_MASK) >> BTCOEX_INT_STAT_SYNC_LSB)
+#define BTCOEX_INT_STAT_SYNC_SET(x)              (((x) << BTCOEX_INT_STAT_SYNC_LSB) & BTCOEX_INT_STAT_SYNC_MASK)
+#define BTCOEX_INT_STAT_END_MSB                  2
+#define BTCOEX_INT_STAT_END_LSB                  2
+#define BTCOEX_INT_STAT_END_MASK                 0x00000004
+#define BTCOEX_INT_STAT_END_GET(x)               (((x) & BTCOEX_INT_STAT_END_MASK) >> BTCOEX_INT_STAT_END_LSB)
+#define BTCOEX_INT_STAT_END_SET(x)               (((x) << BTCOEX_INT_STAT_END_LSB) & BTCOEX_INT_STAT_END_MASK)
+#define BTCOEX_INT_STAT_FRAME_CNT_MSB            1
+#define BTCOEX_INT_STAT_FRAME_CNT_LSB            1
+#define BTCOEX_INT_STAT_FRAME_CNT_MASK           0x00000002
+#define BTCOEX_INT_STAT_FRAME_CNT_GET(x)         (((x) & BTCOEX_INT_STAT_FRAME_CNT_MASK) >> BTCOEX_INT_STAT_FRAME_CNT_LSB)
+#define BTCOEX_INT_STAT_FRAME_CNT_SET(x)         (((x) << BTCOEX_INT_STAT_FRAME_CNT_LSB) & BTCOEX_INT_STAT_FRAME_CNT_MASK)
+#define BTCOEX_INT_STAT_CLK_CNT_MSB              0
+#define BTCOEX_INT_STAT_CLK_CNT_LSB              0
+#define BTCOEX_INT_STAT_CLK_CNT_MASK             0x00000001
+#define BTCOEX_INT_STAT_CLK_CNT_GET(x)           (((x) & BTCOEX_INT_STAT_CLK_CNT_MASK) >> BTCOEX_INT_STAT_CLK_CNT_LSB)
+#define BTCOEX_INT_STAT_CLK_CNT_SET(x)           (((x) << BTCOEX_INT_STAT_CLK_CNT_LSB) & BTCOEX_INT_STAT_CLK_CNT_MASK)
+
+#define BTPRIORITY_INT_EN_ADDRESS                0x0000026c
+#define BTPRIORITY_INT_EN_OFFSET                 0x0000026c
+#define BTPRIORITY_INT_EN_BITMAP_MSB             31
+#define BTPRIORITY_INT_EN_BITMAP_LSB             0
+#define BTPRIORITY_INT_EN_BITMAP_MASK            0xffffffff
+#define BTPRIORITY_INT_EN_BITMAP_GET(x)          (((x) & BTPRIORITY_INT_EN_BITMAP_MASK) >> BTPRIORITY_INT_EN_BITMAP_LSB)
+#define BTPRIORITY_INT_EN_BITMAP_SET(x)          (((x) << BTPRIORITY_INT_EN_BITMAP_LSB) & BTPRIORITY_INT_EN_BITMAP_MASK)
+
+#define BTPRIORITY_INT_STAT_ADDRESS              0x00000270
+#define BTPRIORITY_INT_STAT_OFFSET               0x00000270
+#define BTPRIORITY_INT_STAT_BITMAP_MSB           31
+#define BTPRIORITY_INT_STAT_BITMAP_LSB           0
+#define BTPRIORITY_INT_STAT_BITMAP_MASK          0xffffffff
+#define BTPRIORITY_INT_STAT_BITMAP_GET(x)        (((x) & BTPRIORITY_INT_STAT_BITMAP_MASK) >> BTPRIORITY_INT_STAT_BITMAP_LSB)
+#define BTPRIORITY_INT_STAT_BITMAP_SET(x)        (((x) << BTPRIORITY_INT_STAT_BITMAP_LSB) & BTPRIORITY_INT_STAT_BITMAP_MASK)
+
+#define BTPRIORITY_STOMP_INT_EN_ADDRESS          0x00000274
+#define BTPRIORITY_STOMP_INT_EN_OFFSET           0x00000274
+#define BTPRIORITY_STOMP_INT_EN_BITMAP_MSB       31
+#define BTPRIORITY_STOMP_INT_EN_BITMAP_LSB       0
+#define BTPRIORITY_STOMP_INT_EN_BITMAP_MASK      0xffffffff
+#define BTPRIORITY_STOMP_INT_EN_BITMAP_GET(x)    (((x) & BTPRIORITY_STOMP_INT_EN_BITMAP_MASK) >> BTPRIORITY_STOMP_INT_EN_BITMAP_LSB)
+#define BTPRIORITY_STOMP_INT_EN_BITMAP_SET(x)    (((x) << BTPRIORITY_STOMP_INT_EN_BITMAP_LSB) & BTPRIORITY_STOMP_INT_EN_BITMAP_MASK)
+
+#define BTPRIORITY_STOMP_INT_STAT_ADDRESS        0x00000278
+#define BTPRIORITY_STOMP_INT_STAT_OFFSET         0x00000278
+#define BTPRIORITY_STOMP_INT_STAT_BITMAP_MSB     31
+#define BTPRIORITY_STOMP_INT_STAT_BITMAP_LSB     0
+#define BTPRIORITY_STOMP_INT_STAT_BITMAP_MASK    0xffffffff
+#define BTPRIORITY_STOMP_INT_STAT_BITMAP_GET(x)  (((x) & BTPRIORITY_STOMP_INT_STAT_BITMAP_MASK) >> BTPRIORITY_STOMP_INT_STAT_BITMAP_LSB)
+#define BTPRIORITY_STOMP_INT_STAT_BITMAP_SET(x)  (((x) << BTPRIORITY_STOMP_INT_STAT_BITMAP_LSB) & BTPRIORITY_STOMP_INT_STAT_BITMAP_MASK)
+
+#define MAC_PCU_BMISS_TIMEOUT_ADDRESS            0x0000027c
+#define MAC_PCU_BMISS_TIMEOUT_OFFSET             0x0000027c
+#define MAC_PCU_BMISS_TIMEOUT_ENABLE_MSB         24
+#define MAC_PCU_BMISS_TIMEOUT_ENABLE_LSB         24
+#define MAC_PCU_BMISS_TIMEOUT_ENABLE_MASK        0x01000000
+#define MAC_PCU_BMISS_TIMEOUT_ENABLE_GET(x)      (((x) & MAC_PCU_BMISS_TIMEOUT_ENABLE_MASK) >> MAC_PCU_BMISS_TIMEOUT_ENABLE_LSB)
+#define MAC_PCU_BMISS_TIMEOUT_ENABLE_SET(x)      (((x) << MAC_PCU_BMISS_TIMEOUT_ENABLE_LSB) & MAC_PCU_BMISS_TIMEOUT_ENABLE_MASK)
+#define MAC_PCU_BMISS_TIMEOUT_VALUE_MSB          23
+#define MAC_PCU_BMISS_TIMEOUT_VALUE_LSB          0
+#define MAC_PCU_BMISS_TIMEOUT_VALUE_MASK         0x00ffffff
+#define MAC_PCU_BMISS_TIMEOUT_VALUE_GET(x)       (((x) & MAC_PCU_BMISS_TIMEOUT_VALUE_MASK) >> MAC_PCU_BMISS_TIMEOUT_VALUE_LSB)
+#define MAC_PCU_BMISS_TIMEOUT_VALUE_SET(x)       (((x) << MAC_PCU_BMISS_TIMEOUT_VALUE_LSB) & MAC_PCU_BMISS_TIMEOUT_VALUE_MASK)
+
+#define MAC_PCU_CAB_AWAKE_ADDRESS                0x00000280
+#define MAC_PCU_CAB_AWAKE_OFFSET                 0x00000280
+#define MAC_PCU_CAB_AWAKE_ENABLE_MSB             16
+#define MAC_PCU_CAB_AWAKE_ENABLE_LSB             16
+#define MAC_PCU_CAB_AWAKE_ENABLE_MASK            0x00010000
+#define MAC_PCU_CAB_AWAKE_ENABLE_GET(x)          (((x) & MAC_PCU_CAB_AWAKE_ENABLE_MASK) >> MAC_PCU_CAB_AWAKE_ENABLE_LSB)
+#define MAC_PCU_CAB_AWAKE_ENABLE_SET(x)          (((x) << MAC_PCU_CAB_AWAKE_ENABLE_LSB) & MAC_PCU_CAB_AWAKE_ENABLE_MASK)
+#define MAC_PCU_CAB_AWAKE_DURATION_MSB           15
+#define MAC_PCU_CAB_AWAKE_DURATION_LSB           0
+#define MAC_PCU_CAB_AWAKE_DURATION_MASK          0x0000ffff
+#define MAC_PCU_CAB_AWAKE_DURATION_GET(x)        (((x) & MAC_PCU_CAB_AWAKE_DURATION_MASK) >> MAC_PCU_CAB_AWAKE_DURATION_LSB)
+#define MAC_PCU_CAB_AWAKE_DURATION_SET(x)        (((x) << MAC_PCU_CAB_AWAKE_DURATION_LSB) & MAC_PCU_CAB_AWAKE_DURATION_MASK)
+
+#define LP_PERF_COUNTER_ADDRESS                  0x00000284
+#define LP_PERF_COUNTER_OFFSET                   0x00000284
+#define LP_PERF_COUNTER_EN_MSB                   0
+#define LP_PERF_COUNTER_EN_LSB                   0
+#define LP_PERF_COUNTER_EN_MASK                  0x00000001
+#define LP_PERF_COUNTER_EN_GET(x)                (((x) & LP_PERF_COUNTER_EN_MASK) >> LP_PERF_COUNTER_EN_LSB)
+#define LP_PERF_COUNTER_EN_SET(x)                (((x) << LP_PERF_COUNTER_EN_LSB) & LP_PERF_COUNTER_EN_MASK)
+
+#define LP_PERF_LIGHT_SLEEP_ADDRESS              0x00000288
+#define LP_PERF_LIGHT_SLEEP_OFFSET               0x00000288
+#define LP_PERF_LIGHT_SLEEP_CNT_MSB              31
+#define LP_PERF_LIGHT_SLEEP_CNT_LSB              0
+#define LP_PERF_LIGHT_SLEEP_CNT_MASK             0xffffffff
+#define LP_PERF_LIGHT_SLEEP_CNT_GET(x)           (((x) & LP_PERF_LIGHT_SLEEP_CNT_MASK) >> LP_PERF_LIGHT_SLEEP_CNT_LSB)
+#define LP_PERF_LIGHT_SLEEP_CNT_SET(x)           (((x) << LP_PERF_LIGHT_SLEEP_CNT_LSB) & LP_PERF_LIGHT_SLEEP_CNT_MASK)
+
+#define LP_PERF_DEEP_SLEEP_ADDRESS               0x0000028c
+#define LP_PERF_DEEP_SLEEP_OFFSET                0x0000028c
+#define LP_PERF_DEEP_SLEEP_CNT_MSB               31
+#define LP_PERF_DEEP_SLEEP_CNT_LSB               0
+#define LP_PERF_DEEP_SLEEP_CNT_MASK              0xffffffff
+#define LP_PERF_DEEP_SLEEP_CNT_GET(x)            (((x) & LP_PERF_DEEP_SLEEP_CNT_MASK) >> LP_PERF_DEEP_SLEEP_CNT_LSB)
+#define LP_PERF_DEEP_SLEEP_CNT_SET(x)            (((x) << LP_PERF_DEEP_SLEEP_CNT_LSB) & LP_PERF_DEEP_SLEEP_CNT_MASK)
+
+#define LP_PERF_ON_ADDRESS                       0x00000290
+#define LP_PERF_ON_OFFSET                        0x00000290
+#define LP_PERF_ON_CNT_MSB                       31
+#define LP_PERF_ON_CNT_LSB                       0
+#define LP_PERF_ON_CNT_MASK                      0xffffffff
+#define LP_PERF_ON_CNT_GET(x)                    (((x) & LP_PERF_ON_CNT_MASK) >> LP_PERF_ON_CNT_LSB)
+#define LP_PERF_ON_CNT_SET(x)                    (((x) << LP_PERF_ON_CNT_LSB) & LP_PERF_ON_CNT_MASK)
+
+#define ST_64_BIT_ADDRESS                        0x00000294
+#define ST_64_BIT_OFFSET                         0x00000294
+#define ST_64_BIT_TIMEOUT_MSB                    26
+#define ST_64_BIT_TIMEOUT_LSB                    9
+#define ST_64_BIT_TIMEOUT_MASK                   0x07fffe00
+#define ST_64_BIT_TIMEOUT_GET(x)                 (((x) & ST_64_BIT_TIMEOUT_MASK) >> ST_64_BIT_TIMEOUT_LSB)
+#define ST_64_BIT_TIMEOUT_SET(x)                 (((x) << ST_64_BIT_TIMEOUT_LSB) & ST_64_BIT_TIMEOUT_MASK)
+#define ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_MSB    8
+#define ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_LSB    8
+#define ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_MASK   0x00000100
+#define ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_GET(x) (((x) & ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_MASK) >> ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_LSB)
+#define ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_SET(x) (((x) << ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_LSB) & ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_MASK)
+#define ST_64_BIT_DRIVE_MODE_MSB                 7
+#define ST_64_BIT_DRIVE_MODE_LSB                 7
+#define ST_64_BIT_DRIVE_MODE_MASK                0x00000080
+#define ST_64_BIT_DRIVE_MODE_GET(x)              (((x) & ST_64_BIT_DRIVE_MODE_MASK) >> ST_64_BIT_DRIVE_MODE_LSB)
+#define ST_64_BIT_DRIVE_MODE_SET(x)              (((x) << ST_64_BIT_DRIVE_MODE_LSB) & ST_64_BIT_DRIVE_MODE_MASK)
+#define ST_64_BIT_CLOCK_GATE_MSB                 6
+#define ST_64_BIT_CLOCK_GATE_LSB                 6
+#define ST_64_BIT_CLOCK_GATE_MASK                0x00000040
+#define ST_64_BIT_CLOCK_GATE_GET(x)              (((x) & ST_64_BIT_CLOCK_GATE_MASK) >> ST_64_BIT_CLOCK_GATE_LSB)
+#define ST_64_BIT_CLOCK_GATE_SET(x)              (((x) << ST_64_BIT_CLOCK_GATE_LSB) & ST_64_BIT_CLOCK_GATE_MASK)
+#define ST_64_BIT_SOC_CLK_DIVIDE_RATIO_MSB       5
+#define ST_64_BIT_SOC_CLK_DIVIDE_RATIO_LSB       1
+#define ST_64_BIT_SOC_CLK_DIVIDE_RATIO_MASK      0x0000003e
+#define ST_64_BIT_SOC_CLK_DIVIDE_RATIO_GET(x)    (((x) & ST_64_BIT_SOC_CLK_DIVIDE_RATIO_MASK) >> ST_64_BIT_SOC_CLK_DIVIDE_RATIO_LSB)
+#define ST_64_BIT_SOC_CLK_DIVIDE_RATIO_SET(x)    (((x) << ST_64_BIT_SOC_CLK_DIVIDE_RATIO_LSB) & ST_64_BIT_SOC_CLK_DIVIDE_RATIO_MASK)
+#define ST_64_BIT_MODE_MSB                       0
+#define ST_64_BIT_MODE_LSB                       0
+#define ST_64_BIT_MODE_MASK                      0x00000001
+#define ST_64_BIT_MODE_GET(x)                    (((x) & ST_64_BIT_MODE_MASK) >> ST_64_BIT_MODE_LSB)
+#define ST_64_BIT_MODE_SET(x)                    (((x) << ST_64_BIT_MODE_LSB) & ST_64_BIT_MODE_MASK)
+
+#define MESSAGE_WR_ADDRESS                       0x00000298
+#define MESSAGE_WR_OFFSET                        0x00000298
+#define MESSAGE_WR_TYPE_MSB                      31
+#define MESSAGE_WR_TYPE_LSB                      0
+#define MESSAGE_WR_TYPE_MASK                     0xffffffff
+#define MESSAGE_WR_TYPE_GET(x)                   (((x) & MESSAGE_WR_TYPE_MASK) >> MESSAGE_WR_TYPE_LSB)
+#define MESSAGE_WR_TYPE_SET(x)                   (((x) << MESSAGE_WR_TYPE_LSB) & MESSAGE_WR_TYPE_MASK)
+
+#define MESSAGE_WR_P_ADDRESS                     0x0000029c
+#define MESSAGE_WR_P_OFFSET                      0x0000029c
+#define MESSAGE_WR_P_PARAMETER_MSB               31
+#define MESSAGE_WR_P_PARAMETER_LSB               0
+#define MESSAGE_WR_P_PARAMETER_MASK              0xffffffff
+#define MESSAGE_WR_P_PARAMETER_GET(x)            (((x) & MESSAGE_WR_P_PARAMETER_MASK) >> MESSAGE_WR_P_PARAMETER_LSB)
+#define MESSAGE_WR_P_PARAMETER_SET(x)            (((x) << MESSAGE_WR_P_PARAMETER_LSB) & MESSAGE_WR_P_PARAMETER_MASK)
+
+#define MESSAGE_RD_ADDRESS                       0x000002a0
+#define MESSAGE_RD_OFFSET                        0x000002a0
+#define MESSAGE_RD_TYPE_MSB                      31
+#define MESSAGE_RD_TYPE_LSB                      0
+#define MESSAGE_RD_TYPE_MASK                     0xffffffff
+#define MESSAGE_RD_TYPE_GET(x)                   (((x) & MESSAGE_RD_TYPE_MASK) >> MESSAGE_RD_TYPE_LSB)
+#define MESSAGE_RD_TYPE_SET(x)                   (((x) << MESSAGE_RD_TYPE_LSB) & MESSAGE_RD_TYPE_MASK)
+
+#define MESSAGE_RD_P_ADDRESS                     0x000002a4
+#define MESSAGE_RD_P_OFFSET                      0x000002a4
+#define MESSAGE_RD_P_PARAMETER_MSB               31
+#define MESSAGE_RD_P_PARAMETER_LSB               0
+#define MESSAGE_RD_P_PARAMETER_MASK              0xffffffff
+#define MESSAGE_RD_P_PARAMETER_GET(x)            (((x) & MESSAGE_RD_P_PARAMETER_MASK) >> MESSAGE_RD_P_PARAMETER_LSB)
+#define MESSAGE_RD_P_PARAMETER_SET(x)            (((x) << MESSAGE_RD_P_PARAMETER_LSB) & MESSAGE_RD_P_PARAMETER_MASK)
+
+#define CHIP_MODE_ADDRESS                        0x000002a8
+#define CHIP_MODE_OFFSET                         0x000002a8
+#define CHIP_MODE_BIT_MSB                        1
+#define CHIP_MODE_BIT_LSB                        0
+#define CHIP_MODE_BIT_MASK                       0x00000003
+#define CHIP_MODE_BIT_GET(x)                     (((x) & CHIP_MODE_BIT_MASK) >> CHIP_MODE_BIT_LSB)
+#define CHIP_MODE_BIT_SET(x)                     (((x) << CHIP_MODE_BIT_LSB) & CHIP_MODE_BIT_MASK)
+
+#define CLK_REQ_FALL_EDGE_ADDRESS                0x000002ac
+#define CLK_REQ_FALL_EDGE_OFFSET                 0x000002ac
+#define CLK_REQ_FALL_EDGE_EN_MSB                 31
+#define CLK_REQ_FALL_EDGE_EN_LSB                 31
+#define CLK_REQ_FALL_EDGE_EN_MASK                0x80000000
+#define CLK_REQ_FALL_EDGE_EN_GET(x)              (((x) & CLK_REQ_FALL_EDGE_EN_MASK) >> CLK_REQ_FALL_EDGE_EN_LSB)
+#define CLK_REQ_FALL_EDGE_EN_SET(x)              (((x) << CLK_REQ_FALL_EDGE_EN_LSB) & CLK_REQ_FALL_EDGE_EN_MASK)
+#define CLK_REQ_FALL_EDGE_DELAY_MSB              7
+#define CLK_REQ_FALL_EDGE_DELAY_LSB              0
+#define CLK_REQ_FALL_EDGE_DELAY_MASK             0x000000ff
+#define CLK_REQ_FALL_EDGE_DELAY_GET(x)           (((x) & CLK_REQ_FALL_EDGE_DELAY_MASK) >> CLK_REQ_FALL_EDGE_DELAY_LSB)
+#define CLK_REQ_FALL_EDGE_DELAY_SET(x)           (((x) << CLK_REQ_FALL_EDGE_DELAY_LSB) & CLK_REQ_FALL_EDGE_DELAY_MASK)
+
+#define OTP_ADDRESS                              0x000002b0
+#define OTP_OFFSET                               0x000002b0
+#define OTP_LDO25_EN_MSB                         1
+#define OTP_LDO25_EN_LSB                         1
+#define OTP_LDO25_EN_MASK                        0x00000002
+#define OTP_LDO25_EN_GET(x)                      (((x) & OTP_LDO25_EN_MASK) >> OTP_LDO25_EN_LSB)
+#define OTP_LDO25_EN_SET(x)                      (((x) << OTP_LDO25_EN_LSB) & OTP_LDO25_EN_MASK)
+#define OTP_VDD12_EN_MSB                         0
+#define OTP_VDD12_EN_LSB                         0
+#define OTP_VDD12_EN_MASK                        0x00000001
+#define OTP_VDD12_EN_GET(x)                      (((x) & OTP_VDD12_EN_MASK) >> OTP_VDD12_EN_LSB)
+#define OTP_VDD12_EN_SET(x)                      (((x) << OTP_VDD12_EN_LSB) & OTP_VDD12_EN_MASK)
+
+#define OTP_STATUS_ADDRESS                       0x000002b4
+#define OTP_STATUS_OFFSET                        0x000002b4
+#define OTP_STATUS_LDO25_EN_READY_MSB            1
+#define OTP_STATUS_LDO25_EN_READY_LSB            1
+#define OTP_STATUS_LDO25_EN_READY_MASK           0x00000002
+#define OTP_STATUS_LDO25_EN_READY_GET(x)         (((x) & OTP_STATUS_LDO25_EN_READY_MASK) >> OTP_STATUS_LDO25_EN_READY_LSB)
+#define OTP_STATUS_LDO25_EN_READY_SET(x)         (((x) << OTP_STATUS_LDO25_EN_READY_LSB) & OTP_STATUS_LDO25_EN_READY_MASK)
+#define OTP_STATUS_VDD12_EN_READY_MSB            0
+#define OTP_STATUS_VDD12_EN_READY_LSB            0
+#define OTP_STATUS_VDD12_EN_READY_MASK           0x00000001
+#define OTP_STATUS_VDD12_EN_READY_GET(x)         (((x) & OTP_STATUS_VDD12_EN_READY_MASK) >> OTP_STATUS_VDD12_EN_READY_LSB)
+#define OTP_STATUS_VDD12_EN_READY_SET(x)         (((x) << OTP_STATUS_VDD12_EN_READY_LSB) & OTP_STATUS_VDD12_EN_READY_MASK)
+
+#define PMU_ADDRESS                              0x000002b8
+#define PMU_OFFSET                               0x000002b8
+#define PMU_REG_WAKEUP_TIME_SEL_MSB              1
+#define PMU_REG_WAKEUP_TIME_SEL_LSB              0
+#define PMU_REG_WAKEUP_TIME_SEL_MASK             0x00000003
+#define PMU_REG_WAKEUP_TIME_SEL_GET(x)           (((x) & PMU_REG_WAKEUP_TIME_SEL_MASK) >> PMU_REG_WAKEUP_TIME_SEL_LSB)
+#define PMU_REG_WAKEUP_TIME_SEL_SET(x)           (((x) << PMU_REG_WAKEUP_TIME_SEL_LSB) & PMU_REG_WAKEUP_TIME_SEL_MASK)
+
+#define PMU_CONFIG_ADDRESS                       0x000002c0
+#define PMU_CONFIG_OFFSET                        0x000002c0
+#define PMU_CONFIG_VALUE_MSB                     15
+#define PMU_CONFIG_VALUE_LSB                     0
+#define PMU_CONFIG_VALUE_MASK                    0x0000ffff
+#define PMU_CONFIG_VALUE_GET(x)                  (((x) & PMU_CONFIG_VALUE_MASK) >> PMU_CONFIG_VALUE_LSB)
+#define PMU_CONFIG_VALUE_SET(x)                  (((x) << PMU_CONFIG_VALUE_LSB) & PMU_CONFIG_VALUE_MASK)
+
+#define PMU_BYPASS_ADDRESS                       0x000002c8
+#define PMU_BYPASS_OFFSET                        0x000002c8
+#define PMU_BYPASS_SWREG_MSB                     2
+#define PMU_BYPASS_SWREG_LSB                     2
+#define PMU_BYPASS_SWREG_MASK                    0x00000004
+#define PMU_BYPASS_SWREG_GET(x)                  (((x) & PMU_BYPASS_SWREG_MASK) >> PMU_BYPASS_SWREG_LSB)
+#define PMU_BYPASS_SWREG_SET(x)                  (((x) << PMU_BYPASS_SWREG_LSB) & PMU_BYPASS_SWREG_MASK)
+#define PMU_BYPASS_DREG_MSB                      1
+#define PMU_BYPASS_DREG_LSB                      1
+#define PMU_BYPASS_DREG_MASK                     0x00000002
+#define PMU_BYPASS_DREG_GET(x)                   (((x) & PMU_BYPASS_DREG_MASK) >> PMU_BYPASS_DREG_LSB)
+#define PMU_BYPASS_DREG_SET(x)                   (((x) << PMU_BYPASS_DREG_LSB) & PMU_BYPASS_DREG_MASK)
+#define PMU_BYPASS_PAREG_MSB                     0
+#define PMU_BYPASS_PAREG_LSB                     0
+#define PMU_BYPASS_PAREG_MASK                    0x00000001
+#define PMU_BYPASS_PAREG_GET(x)                  (((x) & PMU_BYPASS_PAREG_MASK) >> PMU_BYPASS_PAREG_LSB)
+#define PMU_BYPASS_PAREG_SET(x)                  (((x) << PMU_BYPASS_PAREG_LSB) & PMU_BYPASS_PAREG_MASK)
+
+#define MAC_PCU_TSF2_L32_ADDRESS                 0x000002cc
+#define MAC_PCU_TSF2_L32_OFFSET                  0x000002cc
+#define MAC_PCU_TSF2_L32_VALUE_MSB               31
+#define MAC_PCU_TSF2_L32_VALUE_LSB               0
+#define MAC_PCU_TSF2_L32_VALUE_MASK              0xffffffff
+#define MAC_PCU_TSF2_L32_VALUE_GET(x)            (((x) & MAC_PCU_TSF2_L32_VALUE_MASK) >> MAC_PCU_TSF2_L32_VALUE_LSB)
+#define MAC_PCU_TSF2_L32_VALUE_SET(x)            (((x) << MAC_PCU_TSF2_L32_VALUE_LSB) & MAC_PCU_TSF2_L32_VALUE_MASK)
+
+#define MAC_PCU_TSF2_U32_ADDRESS                 0x000002d0
+#define MAC_PCU_TSF2_U32_OFFSET                  0x000002d0
+#define MAC_PCU_TSF2_U32_VALUE_MSB               31
+#define MAC_PCU_TSF2_U32_VALUE_LSB               0
+#define MAC_PCU_TSF2_U32_VALUE_MASK              0xffffffff
+#define MAC_PCU_TSF2_U32_VALUE_GET(x)            (((x) & MAC_PCU_TSF2_U32_VALUE_MASK) >> MAC_PCU_TSF2_U32_VALUE_LSB)
+#define MAC_PCU_TSF2_U32_VALUE_SET(x)            (((x) << MAC_PCU_TSF2_U32_VALUE_LSB) & MAC_PCU_TSF2_U32_VALUE_MASK)
+
+#define MAC_PCU_GENERIC_TIMERS_MODE3_ADDRESS     0x000002d4
+#define MAC_PCU_GENERIC_TIMERS_MODE3_OFFSET      0x000002d4
+#define MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_MSB 27
+#define MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_LSB 24
+#define MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_MASK 0x0f000000
+#define MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_GET(x) (((x) & MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_MASK) >> MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_LSB)
+#define MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_SET(x) (((x) << MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_LSB) & MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_MASK)
+#define MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_MSB  19
+#define MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_LSB  0
+#define MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_MASK 0x000fffff
+#define MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_GET(x) (((x) & MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_MASK) >> MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_LSB)
+#define MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_SET(x) (((x) << MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_LSB) & MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_MASK)
+
+#define MAC_PCU_DIRECT_CONNECT_ADDRESS           0x000002d8
+#define MAC_PCU_DIRECT_CONNECT_OFFSET            0x000002d8
+#define MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_MSB 2
+#define MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_LSB 2
+#define MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_MASK 0x00000004
+#define MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_GET(x) (((x) & MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_MASK) >> MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_LSB)
+#define MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_SET(x) (((x) << MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_LSB) & MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_MASK)
+#define MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_MSB 1
+#define MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_LSB 1
+#define MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_MASK 0x00000002
+#define MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_GET(x) (((x) & MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_MASK) >> MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_LSB)
+#define MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_SET(x) (((x) << MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_LSB) & MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_MASK)
+#define MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_MSB 0
+#define MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_LSB 0
+#define MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_MASK 0x00000001
+#define MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_GET(x) (((x) & MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_MASK) >> MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_LSB)
+#define MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_SET(x) (((x) << MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_LSB) & MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_MASK)
+
+#define THERM_CTRL1_ADDRESS                      0x000002dc
+#define THERM_CTRL1_OFFSET                       0x000002dc
+#define THERM_CTRL1_BYPASS_MSB                   16
+#define THERM_CTRL1_BYPASS_LSB                   16
+#define THERM_CTRL1_BYPASS_MASK                  0x00010000
+#define THERM_CTRL1_BYPASS_GET(x)                (((x) & THERM_CTRL1_BYPASS_MASK) >> THERM_CTRL1_BYPASS_LSB)
+#define THERM_CTRL1_BYPASS_SET(x)                (((x) << THERM_CTRL1_BYPASS_LSB) & THERM_CTRL1_BYPASS_MASK)
+#define THERM_CTRL1_WIDTH_ARBITOR_MSB            15
+#define THERM_CTRL1_WIDTH_ARBITOR_LSB            12
+#define THERM_CTRL1_WIDTH_ARBITOR_MASK           0x0000f000
+#define THERM_CTRL1_WIDTH_ARBITOR_GET(x)         (((x) & THERM_CTRL1_WIDTH_ARBITOR_MASK) >> THERM_CTRL1_WIDTH_ARBITOR_LSB)
+#define THERM_CTRL1_WIDTH_ARBITOR_SET(x)         (((x) << THERM_CTRL1_WIDTH_ARBITOR_LSB) & THERM_CTRL1_WIDTH_ARBITOR_MASK)
+#define THERM_CTRL1_WIDTH_MSB                    11
+#define THERM_CTRL1_WIDTH_LSB                    5
+#define THERM_CTRL1_WIDTH_MASK                   0x00000fe0
+#define THERM_CTRL1_WIDTH_GET(x)                 (((x) & THERM_CTRL1_WIDTH_MASK) >> THERM_CTRL1_WIDTH_LSB)
+#define THERM_CTRL1_WIDTH_SET(x)                 (((x) << THERM_CTRL1_WIDTH_LSB) & THERM_CTRL1_WIDTH_MASK)
+#define THERM_CTRL1_TYPE_MSB                     4
+#define THERM_CTRL1_TYPE_LSB                     3
+#define THERM_CTRL1_TYPE_MASK                    0x00000018
+#define THERM_CTRL1_TYPE_GET(x)                  (((x) & THERM_CTRL1_TYPE_MASK) >> THERM_CTRL1_TYPE_LSB)
+#define THERM_CTRL1_TYPE_SET(x)                  (((x) << THERM_CTRL1_TYPE_LSB) & THERM_CTRL1_TYPE_MASK)
+#define THERM_CTRL1_MEASURE_MSB                  2
+#define THERM_CTRL1_MEASURE_LSB                  2
+#define THERM_CTRL1_MEASURE_MASK                 0x00000004
+#define THERM_CTRL1_MEASURE_GET(x)               (((x) & THERM_CTRL1_MEASURE_MASK) >> THERM_CTRL1_MEASURE_LSB)
+#define THERM_CTRL1_MEASURE_SET(x)               (((x) << THERM_CTRL1_MEASURE_LSB) & THERM_CTRL1_MEASURE_MASK)
+#define THERM_CTRL1_INT_EN_MSB                   1
+#define THERM_CTRL1_INT_EN_LSB                   1
+#define THERM_CTRL1_INT_EN_MASK                  0x00000002
+#define THERM_CTRL1_INT_EN_GET(x)                (((x) & THERM_CTRL1_INT_EN_MASK) >> THERM_CTRL1_INT_EN_LSB)
+#define THERM_CTRL1_INT_EN_SET(x)                (((x) << THERM_CTRL1_INT_EN_LSB) & THERM_CTRL1_INT_EN_MASK)
+#define THERM_CTRL1_INT_STATUS_MSB               0
+#define THERM_CTRL1_INT_STATUS_LSB               0
+#define THERM_CTRL1_INT_STATUS_MASK              0x00000001
+#define THERM_CTRL1_INT_STATUS_GET(x)            (((x) & THERM_CTRL1_INT_STATUS_MASK) >> THERM_CTRL1_INT_STATUS_LSB)
+#define THERM_CTRL1_INT_STATUS_SET(x)            (((x) << THERM_CTRL1_INT_STATUS_LSB) & THERM_CTRL1_INT_STATUS_MASK)
+
+#define THERM_CTRL2_ADDRESS                      0x000002e0
+#define THERM_CTRL2_OFFSET                       0x000002e0
+#define THERM_CTRL2_ADC_OFF_MSB                  25
+#define THERM_CTRL2_ADC_OFF_LSB                  25
+#define THERM_CTRL2_ADC_OFF_MASK                 0x02000000
+#define THERM_CTRL2_ADC_OFF_GET(x)               (((x) & THERM_CTRL2_ADC_OFF_MASK) >> THERM_CTRL2_ADC_OFF_LSB)
+#define THERM_CTRL2_ADC_OFF_SET(x)               (((x) << THERM_CTRL2_ADC_OFF_LSB) & THERM_CTRL2_ADC_OFF_MASK)
+#define THERM_CTRL2_ADC_ON_MSB                   24
+#define THERM_CTRL2_ADC_ON_LSB                   24
+#define THERM_CTRL2_ADC_ON_MASK                  0x01000000
+#define THERM_CTRL2_ADC_ON_GET(x)                (((x) & THERM_CTRL2_ADC_ON_MASK) >> THERM_CTRL2_ADC_ON_LSB)
+#define THERM_CTRL2_ADC_ON_SET(x)                (((x) << THERM_CTRL2_ADC_ON_LSB) & THERM_CTRL2_ADC_ON_MASK)
+#define THERM_CTRL2_SAMPLE_MSB                   23
+#define THERM_CTRL2_SAMPLE_LSB                   16
+#define THERM_CTRL2_SAMPLE_MASK                  0x00ff0000
+#define THERM_CTRL2_SAMPLE_GET(x)                (((x) & THERM_CTRL2_SAMPLE_MASK) >> THERM_CTRL2_SAMPLE_LSB)
+#define THERM_CTRL2_SAMPLE_SET(x)                (((x) << THERM_CTRL2_SAMPLE_LSB) & THERM_CTRL2_SAMPLE_MASK)
+#define THERM_CTRL2_HIGH_MSB                     15
+#define THERM_CTRL2_HIGH_LSB                     8
+#define THERM_CTRL2_HIGH_MASK                    0x0000ff00
+#define THERM_CTRL2_HIGH_GET(x)                  (((x) & THERM_CTRL2_HIGH_MASK) >> THERM_CTRL2_HIGH_LSB)
+#define THERM_CTRL2_HIGH_SET(x)                  (((x) << THERM_CTRL2_HIGH_LSB) & THERM_CTRL2_HIGH_MASK)
+#define THERM_CTRL2_LOW_MSB                      7
+#define THERM_CTRL2_LOW_LSB                      0
+#define THERM_CTRL2_LOW_MASK                     0x000000ff
+#define THERM_CTRL2_LOW_GET(x)                   (((x) & THERM_CTRL2_LOW_MASK) >> THERM_CTRL2_LOW_LSB)
+#define THERM_CTRL2_LOW_SET(x)                   (((x) << THERM_CTRL2_LOW_LSB) & THERM_CTRL2_LOW_MASK)
+
+#define THERM_CTRL3_ADDRESS                      0x000002e4
+#define THERM_CTRL3_OFFSET                       0x000002e4
+#define THERM_CTRL3_ADC_GAIN_MSB                 16
+#define THERM_CTRL3_ADC_GAIN_LSB                 8
+#define THERM_CTRL3_ADC_GAIN_MASK                0x0001ff00
+#define THERM_CTRL3_ADC_GAIN_GET(x)              (((x) & THERM_CTRL3_ADC_GAIN_MASK) >> THERM_CTRL3_ADC_GAIN_LSB)
+#define THERM_CTRL3_ADC_GAIN_SET(x)              (((x) << THERM_CTRL3_ADC_GAIN_LSB) & THERM_CTRL3_ADC_GAIN_MASK)
+#define THERM_CTRL3_ADC_OFFSET_MSB               7
+#define THERM_CTRL3_ADC_OFFSET_LSB               0
+#define THERM_CTRL3_ADC_OFFSET_MASK              0x000000ff
+#define THERM_CTRL3_ADC_OFFSET_GET(x)            (((x) & THERM_CTRL3_ADC_OFFSET_MASK) >> THERM_CTRL3_ADC_OFFSET_LSB)
+#define THERM_CTRL3_ADC_OFFSET_SET(x)            (((x) << THERM_CTRL3_ADC_OFFSET_LSB) & THERM_CTRL3_ADC_OFFSET_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct rtc_wlan_reg_reg_s {
+  volatile unsigned int wlan_reset_control;
+  volatile unsigned int wlan_xtal_control;
+  volatile unsigned int wlan_tcxo_detect;
+  volatile unsigned int wlan_xtal_test;
+  volatile unsigned int wlan_quadrature;
+  volatile unsigned int wlan_pll_control;
+  volatile unsigned int wlan_pll_settle;
+  volatile unsigned int wlan_xtal_settle;
+  volatile unsigned int wlan_cpu_clock;
+  volatile unsigned int wlan_clock_out;
+  volatile unsigned int wlan_clock_control;
+  volatile unsigned int wlan_bias_override;
+  volatile unsigned int wlan_wdt_control;
+  volatile unsigned int wlan_wdt_status;
+  volatile unsigned int wlan_wdt;
+  volatile unsigned int wlan_wdt_count;
+  volatile unsigned int wlan_wdt_reset;
+  volatile unsigned int wlan_int_status;
+  volatile unsigned int wlan_lf_timer0;
+  volatile unsigned int wlan_lf_timer_count0;
+  volatile unsigned int wlan_lf_timer_control0;
+  volatile unsigned int wlan_lf_timer_status0;
+  volatile unsigned int wlan_lf_timer1;
+  volatile unsigned int wlan_lf_timer_count1;
+  volatile unsigned int wlan_lf_timer_control1;
+  volatile unsigned int wlan_lf_timer_status1;
+  volatile unsigned int wlan_lf_timer2;
+  volatile unsigned int wlan_lf_timer_count2;
+  volatile unsigned int wlan_lf_timer_control2;
+  volatile unsigned int wlan_lf_timer_status2;
+  volatile unsigned int wlan_lf_timer3;
+  volatile unsigned int wlan_lf_timer_count3;
+  volatile unsigned int wlan_lf_timer_control3;
+  volatile unsigned int wlan_lf_timer_status3;
+  volatile unsigned int wlan_hf_timer;
+  volatile unsigned int wlan_hf_timer_count;
+  volatile unsigned int wlan_hf_lf_count;
+  volatile unsigned int wlan_hf_timer_control;
+  volatile unsigned int wlan_hf_timer_status;
+  volatile unsigned int wlan_rtc_control;
+  volatile unsigned int wlan_rtc_time;
+  volatile unsigned int wlan_rtc_date;
+  volatile unsigned int wlan_rtc_set_time;
+  volatile unsigned int wlan_rtc_set_date;
+  volatile unsigned int wlan_rtc_set_alarm;
+  volatile unsigned int wlan_rtc_config;
+  volatile unsigned int wlan_rtc_alarm_status;
+  volatile unsigned int wlan_uart_wakeup;
+  volatile unsigned int wlan_reset_cause;
+  volatile unsigned int wlan_system_sleep;
+  volatile unsigned int wlan_sdio_wrapper;
+  volatile unsigned int wlan_mac_sleep_control;
+  volatile unsigned int wlan_keep_awake;
+  volatile unsigned int wlan_lpo_cal_time;
+  volatile unsigned int wlan_lpo_init_dividend_int;
+  volatile unsigned int wlan_lpo_init_dividend_fraction;
+  volatile unsigned int wlan_lpo_cal;
+  volatile unsigned int wlan_lpo_cal_test_control;
+  volatile unsigned int wlan_lpo_cal_test_status;
+  volatile unsigned int wlan_chip_id;
+  volatile unsigned int wlan_derived_rtc_clk;
+  volatile unsigned int mac_pcu_slp32_mode;
+  volatile unsigned int mac_pcu_slp32_wake;
+  volatile unsigned int mac_pcu_slp32_inc;
+  volatile unsigned int mac_pcu_slp_mib1;
+  volatile unsigned int mac_pcu_slp_mib2;
+  volatile unsigned int mac_pcu_slp_mib3;
+  volatile unsigned int wlan_power_reg;
+  volatile unsigned int wlan_core_clk_ctrl;
+  volatile unsigned int wlan_gpio_wakeup_control;
+  volatile unsigned int ht;
+  volatile unsigned int mac_pcu_tsf_l32;
+  volatile unsigned int mac_pcu_tsf_u32;
+  volatile unsigned int mac_pcu_wbtimer;
+  unsigned char pad0[24]; /* pad to 0x140 */
+  volatile unsigned int mac_pcu_generic_timers[16];
+  volatile unsigned int mac_pcu_generic_timers_mode;
+  unsigned char pad1[60]; /* pad to 0x1c0 */
+  volatile unsigned int mac_pcu_generic_timers2[16];
+  volatile unsigned int mac_pcu_generic_timers_mode2;
+  volatile unsigned int mac_pcu_slp1;
+  volatile unsigned int mac_pcu_slp2;
+  volatile unsigned int mac_pcu_reset_tsf;
+  volatile unsigned int mac_pcu_tsf_add_pll;
+  volatile unsigned int sleep_retention;
+  volatile unsigned int btcoexctrl;
+  volatile unsigned int wbsync_priority1;
+  volatile unsigned int wbsync_priority2;
+  volatile unsigned int wbsync_priority3;
+  volatile unsigned int btcoex0;
+  volatile unsigned int btcoex1;
+  volatile unsigned int btcoex2;
+  volatile unsigned int btcoex3;
+  volatile unsigned int btcoex4;
+  volatile unsigned int btcoex5;
+  volatile unsigned int btcoex6;
+  volatile unsigned int lock;
+  volatile unsigned int nolock_priority;
+  volatile unsigned int wbsync;
+  volatile unsigned int wbsync1;
+  volatile unsigned int wbsync2;
+  volatile unsigned int wbsync3;
+  volatile unsigned int wb_timer_target;
+  volatile unsigned int wb_timer_slop;
+  volatile unsigned int btcoex_int_en;
+  volatile unsigned int btcoex_int_stat;
+  volatile unsigned int btpriority_int_en;
+  volatile unsigned int btpriority_int_stat;
+  volatile unsigned int btpriority_stomp_int_en;
+  volatile unsigned int btpriority_stomp_int_stat;
+  volatile unsigned int mac_pcu_bmiss_timeout;
+  volatile unsigned int mac_pcu_cab_awake;
+  volatile unsigned int lp_perf_counter;
+  volatile unsigned int lp_perf_light_sleep;
+  volatile unsigned int lp_perf_deep_sleep;
+  volatile unsigned int lp_perf_on;
+  volatile unsigned int st_64_bit;
+  volatile unsigned int message_wr;
+  volatile unsigned int message_wr_p;
+  volatile unsigned int message_rd;
+  volatile unsigned int message_rd_p;
+  volatile unsigned int chip_mode;
+  volatile unsigned int clk_req_fall_edge;
+  volatile unsigned int otp;
+  volatile unsigned int otp_status;
+  volatile unsigned int pmu;
+  unsigned char pad2[4]; /* pad to 0x2c0 */
+  volatile unsigned int pmu_config[2];
+  volatile unsigned int pmu_bypass;
+  volatile unsigned int mac_pcu_tsf2_l32;
+  volatile unsigned int mac_pcu_tsf2_u32;
+  volatile unsigned int mac_pcu_generic_timers_mode3;
+  volatile unsigned int mac_pcu_direct_connect;
+  volatile unsigned int therm_ctrl1;
+  volatile unsigned int therm_ctrl2;
+  volatile unsigned int therm_ctrl3;
+} rtc_wlan_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _RTC_WLAN_REG_H_ */
diff --git a/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/si_reg.h b/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/si_reg.h
new file mode 100644
index 00000000000..2cd2e3cadbb
--- /dev/null
+++ b/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/si_reg.h
@@ -0,0 +1,209 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _SI_REG_REG_H_
+#define _SI_REG_REG_H_
+
+#define SI_CONFIG_ADDRESS                        0x00000000
+#define SI_CONFIG_OFFSET                         0x00000000
+#define SI_CONFIG_ERR_INT_MSB                    19
+#define SI_CONFIG_ERR_INT_LSB                    19
+#define SI_CONFIG_ERR_INT_MASK                   0x00080000
+#define SI_CONFIG_ERR_INT_GET(x)                 (((x) & SI_CONFIG_ERR_INT_MASK) >> SI_CONFIG_ERR_INT_LSB)
+#define SI_CONFIG_ERR_INT_SET(x)                 (((x) << SI_CONFIG_ERR_INT_LSB) & SI_CONFIG_ERR_INT_MASK)
+#define SI_CONFIG_BIDIR_OD_DATA_MSB              18
+#define SI_CONFIG_BIDIR_OD_DATA_LSB              18
+#define SI_CONFIG_BIDIR_OD_DATA_MASK             0x00040000
+#define SI_CONFIG_BIDIR_OD_DATA_GET(x)           (((x) & SI_CONFIG_BIDIR_OD_DATA_MASK) >> SI_CONFIG_BIDIR_OD_DATA_LSB)
+#define SI_CONFIG_BIDIR_OD_DATA_SET(x)           (((x) << SI_CONFIG_BIDIR_OD_DATA_LSB) & SI_CONFIG_BIDIR_OD_DATA_MASK)
+#define SI_CONFIG_I2C_MSB                        16
+#define SI_CONFIG_I2C_LSB                        16
+#define SI_CONFIG_I2C_MASK                       0x00010000
+#define SI_CONFIG_I2C_GET(x)                     (((x) & SI_CONFIG_I2C_MASK) >> SI_CONFIG_I2C_LSB)
+#define SI_CONFIG_I2C_SET(x)                     (((x) << SI_CONFIG_I2C_LSB) & SI_CONFIG_I2C_MASK)
+#define SI_CONFIG_POS_SAMPLE_MSB                 7
+#define SI_CONFIG_POS_SAMPLE_LSB                 7
+#define SI_CONFIG_POS_SAMPLE_MASK                0x00000080
+#define SI_CONFIG_POS_SAMPLE_GET(x)              (((x) & SI_CONFIG_POS_SAMPLE_MASK) >> SI_CONFIG_POS_SAMPLE_LSB)
+#define SI_CONFIG_POS_SAMPLE_SET(x)              (((x) << SI_CONFIG_POS_SAMPLE_LSB) & SI_CONFIG_POS_SAMPLE_MASK)
+#define SI_CONFIG_POS_DRIVE_MSB                  6
+#define SI_CONFIG_POS_DRIVE_LSB                  6
+#define SI_CONFIG_POS_DRIVE_MASK                 0x00000040
+#define SI_CONFIG_POS_DRIVE_GET(x)               (((x) & SI_CONFIG_POS_DRIVE_MASK) >> SI_CONFIG_POS_DRIVE_LSB)
+#define SI_CONFIG_POS_DRIVE_SET(x)               (((x) << SI_CONFIG_POS_DRIVE_LSB) & SI_CONFIG_POS_DRIVE_MASK)
+#define SI_CONFIG_INACTIVE_DATA_MSB              5
+#define SI_CONFIG_INACTIVE_DATA_LSB              5
+#define SI_CONFIG_INACTIVE_DATA_MASK             0x00000020
+#define SI_CONFIG_INACTIVE_DATA_GET(x)           (((x) & SI_CONFIG_INACTIVE_DATA_MASK) >> SI_CONFIG_INACTIVE_DATA_LSB)
+#define SI_CONFIG_INACTIVE_DATA_SET(x)           (((x) << SI_CONFIG_INACTIVE_DATA_LSB) & SI_CONFIG_INACTIVE_DATA_MASK)
+#define SI_CONFIG_INACTIVE_CLK_MSB               4
+#define SI_CONFIG_INACTIVE_CLK_LSB               4
+#define SI_CONFIG_INACTIVE_CLK_MASK              0x00000010
+#define SI_CONFIG_INACTIVE_CLK_GET(x)            (((x) & SI_CONFIG_INACTIVE_CLK_MASK) >> SI_CONFIG_INACTIVE_CLK_LSB)
+#define SI_CONFIG_INACTIVE_CLK_SET(x)            (((x) << SI_CONFIG_INACTIVE_CLK_LSB) & SI_CONFIG_INACTIVE_CLK_MASK)
+#define SI_CONFIG_DIVIDER_MSB                    3
+#define SI_CONFIG_DIVIDER_LSB                    0
+#define SI_CONFIG_DIVIDER_MASK                   0x0000000f
+#define SI_CONFIG_DIVIDER_GET(x)                 (((x) & SI_CONFIG_DIVIDER_MASK) >> SI_CONFIG_DIVIDER_LSB)
+#define SI_CONFIG_DIVIDER_SET(x)                 (((x) << SI_CONFIG_DIVIDER_LSB) & SI_CONFIG_DIVIDER_MASK)
+
+#define SI_CS_ADDRESS                            0x00000004
+#define SI_CS_OFFSET                             0x00000004
+#define SI_CS_BIT_CNT_IN_LAST_BYTE_MSB           13
+#define SI_CS_BIT_CNT_IN_LAST_BYTE_LSB           11
+#define SI_CS_BIT_CNT_IN_LAST_BYTE_MASK          0x00003800
+#define SI_CS_BIT_CNT_IN_LAST_BYTE_GET(x)        (((x) & SI_CS_BIT_CNT_IN_LAST_BYTE_MASK) >> SI_CS_BIT_CNT_IN_LAST_BYTE_LSB)
+#define SI_CS_BIT_CNT_IN_LAST_BYTE_SET(x)        (((x) << SI_CS_BIT_CNT_IN_LAST_BYTE_LSB) & SI_CS_BIT_CNT_IN_LAST_BYTE_MASK)
+#define SI_CS_DONE_ERR_MSB                       10
+#define SI_CS_DONE_ERR_LSB                       10
+#define SI_CS_DONE_ERR_MASK                      0x00000400
+#define SI_CS_DONE_ERR_GET(x)                    (((x) & SI_CS_DONE_ERR_MASK) >> SI_CS_DONE_ERR_LSB)
+#define SI_CS_DONE_ERR_SET(x)                    (((x) << SI_CS_DONE_ERR_LSB) & SI_CS_DONE_ERR_MASK)
+#define SI_CS_DONE_INT_MSB                       9
+#define SI_CS_DONE_INT_LSB                       9
+#define SI_CS_DONE_INT_MASK                      0x00000200
+#define SI_CS_DONE_INT_GET(x)                    (((x) & SI_CS_DONE_INT_MASK) >> SI_CS_DONE_INT_LSB)
+#define SI_CS_DONE_INT_SET(x)                    (((x) << SI_CS_DONE_INT_LSB) & SI_CS_DONE_INT_MASK)
+#define SI_CS_START_MSB                          8
+#define SI_CS_START_LSB                          8
+#define SI_CS_START_MASK                         0x00000100
+#define SI_CS_START_GET(x)                       (((x) & SI_CS_START_MASK) >> SI_CS_START_LSB)
+#define SI_CS_START_SET(x)                       (((x) << SI_CS_START_LSB) & SI_CS_START_MASK)
+#define SI_CS_RX_CNT_MSB                         7
+#define SI_CS_RX_CNT_LSB                         4
+#define SI_CS_RX_CNT_MASK                        0x000000f0
+#define SI_CS_RX_CNT_GET(x)                      (((x) & SI_CS_RX_CNT_MASK) >> SI_CS_RX_CNT_LSB)
+#define SI_CS_RX_CNT_SET(x)                      (((x) << SI_CS_RX_CNT_LSB) & SI_CS_RX_CNT_MASK)
+#define SI_CS_TX_CNT_MSB                         3
+#define SI_CS_TX_CNT_LSB                         0
+#define SI_CS_TX_CNT_MASK                        0x0000000f
+#define SI_CS_TX_CNT_GET(x)                      (((x) & SI_CS_TX_CNT_MASK) >> SI_CS_TX_CNT_LSB)
+#define SI_CS_TX_CNT_SET(x)                      (((x) << SI_CS_TX_CNT_LSB) & SI_CS_TX_CNT_MASK)
+
+#define SI_TX_DATA0_ADDRESS                      0x00000008
+#define SI_TX_DATA0_OFFSET                       0x00000008
+#define SI_TX_DATA0_DATA3_MSB                    31
+#define SI_TX_DATA0_DATA3_LSB                    24
+#define SI_TX_DATA0_DATA3_MASK                   0xff000000
+#define SI_TX_DATA0_DATA3_GET(x)                 (((x) & SI_TX_DATA0_DATA3_MASK) >> SI_TX_DATA0_DATA3_LSB)
+#define SI_TX_DATA0_DATA3_SET(x)                 (((x) << SI_TX_DATA0_DATA3_LSB) & SI_TX_DATA0_DATA3_MASK)
+#define SI_TX_DATA0_DATA2_MSB                    23
+#define SI_TX_DATA0_DATA2_LSB                    16
+#define SI_TX_DATA0_DATA2_MASK                   0x00ff0000
+#define SI_TX_DATA0_DATA2_GET(x)                 (((x) & SI_TX_DATA0_DATA2_MASK) >> SI_TX_DATA0_DATA2_LSB)
+#define SI_TX_DATA0_DATA2_SET(x)                 (((x) << SI_TX_DATA0_DATA2_LSB) & SI_TX_DATA0_DATA2_MASK)
+#define SI_TX_DATA0_DATA1_MSB                    15
+#define SI_TX_DATA0_DATA1_LSB                    8
+#define SI_TX_DATA0_DATA1_MASK                   0x0000ff00
+#define SI_TX_DATA0_DATA1_GET(x)                 (((x) & SI_TX_DATA0_DATA1_MASK) >> SI_TX_DATA0_DATA1_LSB)
+#define SI_TX_DATA0_DATA1_SET(x)                 (((x) << SI_TX_DATA0_DATA1_LSB) & SI_TX_DATA0_DATA1_MASK)
+#define SI_TX_DATA0_DATA0_MSB                    7
+#define SI_TX_DATA0_DATA0_LSB                    0
+#define SI_TX_DATA0_DATA0_MASK                   0x000000ff
+#define SI_TX_DATA0_DATA0_GET(x)                 (((x) & SI_TX_DATA0_DATA0_MASK) >> SI_TX_DATA0_DATA0_LSB)
+#define SI_TX_DATA0_DATA0_SET(x)                 (((x) << SI_TX_DATA0_DATA0_LSB) & SI_TX_DATA0_DATA0_MASK)
+
+#define SI_TX_DATA1_ADDRESS                      0x0000000c
+#define SI_TX_DATA1_OFFSET                       0x0000000c
+#define SI_TX_DATA1_DATA7_MSB                    31
+#define SI_TX_DATA1_DATA7_LSB                    24
+#define SI_TX_DATA1_DATA7_MASK                   0xff000000
+#define SI_TX_DATA1_DATA7_GET(x)                 (((x) & SI_TX_DATA1_DATA7_MASK) >> SI_TX_DATA1_DATA7_LSB)
+#define SI_TX_DATA1_DATA7_SET(x)                 (((x) << SI_TX_DATA1_DATA7_LSB) & SI_TX_DATA1_DATA7_MASK)
+#define SI_TX_DATA1_DATA6_MSB                    23
+#define SI_TX_DATA1_DATA6_LSB                    16
+#define SI_TX_DATA1_DATA6_MASK                   0x00ff0000
+#define SI_TX_DATA1_DATA6_GET(x)                 (((x) & SI_TX_DATA1_DATA6_MASK) >> SI_TX_DATA1_DATA6_LSB)
+#define SI_TX_DATA1_DATA6_SET(x)                 (((x) << SI_TX_DATA1_DATA6_LSB) & SI_TX_DATA1_DATA6_MASK)
+#define SI_TX_DATA1_DATA5_MSB                    15
+#define SI_TX_DATA1_DATA5_LSB                    8
+#define SI_TX_DATA1_DATA5_MASK                   0x0000ff00
+#define SI_TX_DATA1_DATA5_GET(x)                 (((x) & SI_TX_DATA1_DATA5_MASK) >> SI_TX_DATA1_DATA5_LSB)
+#define SI_TX_DATA1_DATA5_SET(x)                 (((x) << SI_TX_DATA1_DATA5_LSB) & SI_TX_DATA1_DATA5_MASK)
+#define SI_TX_DATA1_DATA4_MSB                    7
+#define SI_TX_DATA1_DATA4_LSB                    0
+#define SI_TX_DATA1_DATA4_MASK                   0x000000ff
+#define SI_TX_DATA1_DATA4_GET(x)                 (((x) & SI_TX_DATA1_DATA4_MASK) >> SI_TX_DATA1_DATA4_LSB)
+#define SI_TX_DATA1_DATA4_SET(x)                 (((x) << SI_TX_DATA1_DATA4_LSB) & SI_TX_DATA1_DATA4_MASK)
+
+#define SI_RX_DATA0_ADDRESS                      0x00000010
+#define SI_RX_DATA0_OFFSET                       0x00000010
+#define SI_RX_DATA0_DATA3_MSB                    31
+#define SI_RX_DATA0_DATA3_LSB                    24
+#define SI_RX_DATA0_DATA3_MASK                   0xff000000
+#define SI_RX_DATA0_DATA3_GET(x)                 (((x) & SI_RX_DATA0_DATA3_MASK) >> SI_RX_DATA0_DATA3_LSB)
+#define SI_RX_DATA0_DATA3_SET(x)                 (((x) << SI_RX_DATA0_DATA3_LSB) & SI_RX_DATA0_DATA3_MASK)
+#define SI_RX_DATA0_DATA2_MSB                    23
+#define SI_RX_DATA0_DATA2_LSB                    16
+#define SI_RX_DATA0_DATA2_MASK                   0x00ff0000
+#define SI_RX_DATA0_DATA2_GET(x)                 (((x) & SI_RX_DATA0_DATA2_MASK) >> SI_RX_DATA0_DATA2_LSB)
+#define SI_RX_DATA0_DATA2_SET(x)                 (((x) << SI_RX_DATA0_DATA2_LSB) & SI_RX_DATA0_DATA2_MASK)
+#define SI_RX_DATA0_DATA1_MSB                    15
+#define SI_RX_DATA0_DATA1_LSB                    8
+#define SI_RX_DATA0_DATA1_MASK                   0x0000ff00
+#define SI_RX_DATA0_DATA1_GET(x)                 (((x) & SI_RX_DATA0_DATA1_MASK) >> SI_RX_DATA0_DATA1_LSB)
+#define SI_RX_DATA0_DATA1_SET(x)                 (((x) << SI_RX_DATA0_DATA1_LSB) & SI_RX_DATA0_DATA1_MASK)
+#define SI_RX_DATA0_DATA0_MSB                    7
+#define SI_RX_DATA0_DATA0_LSB                    0
+#define SI_RX_DATA0_DATA0_MASK                   0x000000ff
+#define SI_RX_DATA0_DATA0_GET(x)                 (((x) & SI_RX_DATA0_DATA0_MASK) >> SI_RX_DATA0_DATA0_LSB)
+#define SI_RX_DATA0_DATA0_SET(x)                 (((x) << SI_RX_DATA0_DATA0_LSB) & SI_RX_DATA0_DATA0_MASK)
+
+#define SI_RX_DATA1_ADDRESS                      0x00000014
+#define SI_RX_DATA1_OFFSET                       0x00000014
+#define SI_RX_DATA1_DATA7_MSB                    31
+#define SI_RX_DATA1_DATA7_LSB                    24
+#define SI_RX_DATA1_DATA7_MASK                   0xff000000
+#define SI_RX_DATA1_DATA7_GET(x)                 (((x) & SI_RX_DATA1_DATA7_MASK) >> SI_RX_DATA1_DATA7_LSB)
+#define SI_RX_DATA1_DATA7_SET(x)                 (((x) << SI_RX_DATA1_DATA7_LSB) & SI_RX_DATA1_DATA7_MASK)
+#define SI_RX_DATA1_DATA6_MSB                    23
+#define SI_RX_DATA1_DATA6_LSB                    16
+#define SI_RX_DATA1_DATA6_MASK                   0x00ff0000
+#define SI_RX_DATA1_DATA6_GET(x)                 (((x) & SI_RX_DATA1_DATA6_MASK) >> SI_RX_DATA1_DATA6_LSB)
+#define SI_RX_DATA1_DATA6_SET(x)                 (((x) << SI_RX_DATA1_DATA6_LSB) & SI_RX_DATA1_DATA6_MASK)
+#define SI_RX_DATA1_DATA5_MSB                    15
+#define SI_RX_DATA1_DATA5_LSB                    8
+#define SI_RX_DATA1_DATA5_MASK                   0x0000ff00
+#define SI_RX_DATA1_DATA5_GET(x)                 (((x) & SI_RX_DATA1_DATA5_MASK) >> SI_RX_DATA1_DATA5_LSB)
+#define SI_RX_DATA1_DATA5_SET(x)                 (((x) << SI_RX_DATA1_DATA5_LSB) & SI_RX_DATA1_DATA5_MASK)
+#define SI_RX_DATA1_DATA4_MSB                    7
+#define SI_RX_DATA1_DATA4_LSB                    0
+#define SI_RX_DATA1_DATA4_MASK                   0x000000ff
+#define SI_RX_DATA1_DATA4_GET(x)                 (((x) & SI_RX_DATA1_DATA4_MASK) >> SI_RX_DATA1_DATA4_LSB)
+#define SI_RX_DATA1_DATA4_SET(x)                 (((x) << SI_RX_DATA1_DATA4_LSB) & SI_RX_DATA1_DATA4_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct si_reg_reg_s {
+  volatile unsigned int si_config;
+  volatile unsigned int si_cs;
+  volatile unsigned int si_tx_data0;
+  volatile unsigned int si_tx_data1;
+  volatile unsigned int si_rx_data0;
+  volatile unsigned int si_rx_data1;
+} si_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _SI_REG_H_ */
diff --git a/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/uart_reg.h b/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/uart_reg.h
new file mode 100644
index 00000000000..a8eccaf6d74
--- /dev/null
+++ b/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/uart_reg.h
@@ -0,0 +1,260 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _UART_REG_REG_H_
+#define _UART_REG_REG_H_
+
+#define UART_DATA_ADDRESS                        0x00000000
+#define UART_DATA_OFFSET                         0x00000000
+#define UART_DATA_TX_CSR_MSB                     9
+#define UART_DATA_TX_CSR_LSB                     9
+#define UART_DATA_TX_CSR_MASK                    0x00000200
+#define UART_DATA_TX_CSR_GET(x)                  (((x) & UART_DATA_TX_CSR_MASK) >> UART_DATA_TX_CSR_LSB)
+#define UART_DATA_TX_CSR_SET(x)                  (((x) << UART_DATA_TX_CSR_LSB) & UART_DATA_TX_CSR_MASK)
+#define UART_DATA_RX_CSR_MSB                     8
+#define UART_DATA_RX_CSR_LSB                     8
+#define UART_DATA_RX_CSR_MASK                    0x00000100
+#define UART_DATA_RX_CSR_GET(x)                  (((x) & UART_DATA_RX_CSR_MASK) >> UART_DATA_RX_CSR_LSB)
+#define UART_DATA_RX_CSR_SET(x)                  (((x) << UART_DATA_RX_CSR_LSB) & UART_DATA_RX_CSR_MASK)
+#define UART_DATA_TXRX_DATA_MSB                  7
+#define UART_DATA_TXRX_DATA_LSB                  0
+#define UART_DATA_TXRX_DATA_MASK                 0x000000ff
+#define UART_DATA_TXRX_DATA_GET(x)               (((x) & UART_DATA_TXRX_DATA_MASK) >> UART_DATA_TXRX_DATA_LSB)
+#define UART_DATA_TXRX_DATA_SET(x)               (((x) << UART_DATA_TXRX_DATA_LSB) & UART_DATA_TXRX_DATA_MASK)
+
+#define UART_CONTROL_ADDRESS                     0x00000004
+#define UART_CONTROL_OFFSET                      0x00000004
+#define UART_CONTROL_RX_BUSY_MSB                 15
+#define UART_CONTROL_RX_BUSY_LSB                 15
+#define UART_CONTROL_RX_BUSY_MASK                0x00008000
+#define UART_CONTROL_RX_BUSY_GET(x)              (((x) & UART_CONTROL_RX_BUSY_MASK) >> UART_CONTROL_RX_BUSY_LSB)
+#define UART_CONTROL_RX_BUSY_SET(x)              (((x) << UART_CONTROL_RX_BUSY_LSB) & UART_CONTROL_RX_BUSY_MASK)
+#define UART_CONTROL_TX_BUSY_MSB                 14
+#define UART_CONTROL_TX_BUSY_LSB                 14
+#define UART_CONTROL_TX_BUSY_MASK                0x00004000
+#define UART_CONTROL_TX_BUSY_GET(x)              (((x) & UART_CONTROL_TX_BUSY_MASK) >> UART_CONTROL_TX_BUSY_LSB)
+#define UART_CONTROL_TX_BUSY_SET(x)              (((x) << UART_CONTROL_TX_BUSY_LSB) & UART_CONTROL_TX_BUSY_MASK)
+#define UART_CONTROL_HOST_INT_ENABLE_MSB         13
+#define UART_CONTROL_HOST_INT_ENABLE_LSB         13
+#define UART_CONTROL_HOST_INT_ENABLE_MASK        0x00002000
+#define UART_CONTROL_HOST_INT_ENABLE_GET(x)      (((x) & UART_CONTROL_HOST_INT_ENABLE_MASK) >> UART_CONTROL_HOST_INT_ENABLE_LSB)
+#define UART_CONTROL_HOST_INT_ENABLE_SET(x)      (((x) << UART_CONTROL_HOST_INT_ENABLE_LSB) & UART_CONTROL_HOST_INT_ENABLE_MASK)
+#define UART_CONTROL_HOST_INT_MSB                12
+#define UART_CONTROL_HOST_INT_LSB                12
+#define UART_CONTROL_HOST_INT_MASK               0x00001000
+#define UART_CONTROL_HOST_INT_GET(x)             (((x) & UART_CONTROL_HOST_INT_MASK) >> UART_CONTROL_HOST_INT_LSB)
+#define UART_CONTROL_HOST_INT_SET(x)             (((x) << UART_CONTROL_HOST_INT_LSB) & UART_CONTROL_HOST_INT_MASK)
+#define UART_CONTROL_TX_BREAK_MSB                11
+#define UART_CONTROL_TX_BREAK_LSB                11
+#define UART_CONTROL_TX_BREAK_MASK               0x00000800
+#define UART_CONTROL_TX_BREAK_GET(x)             (((x) & UART_CONTROL_TX_BREAK_MASK) >> UART_CONTROL_TX_BREAK_LSB)
+#define UART_CONTROL_TX_BREAK_SET(x)             (((x) << UART_CONTROL_TX_BREAK_LSB) & UART_CONTROL_TX_BREAK_MASK)
+#define UART_CONTROL_RX_BREAK_MSB                10
+#define UART_CONTROL_RX_BREAK_LSB                10
+#define UART_CONTROL_RX_BREAK_MASK               0x00000400
+#define UART_CONTROL_RX_BREAK_GET(x)             (((x) & UART_CONTROL_RX_BREAK_MASK) >> UART_CONTROL_RX_BREAK_LSB)
+#define UART_CONTROL_RX_BREAK_SET(x)             (((x) << UART_CONTROL_RX_BREAK_LSB) & UART_CONTROL_RX_BREAK_MASK)
+#define UART_CONTROL_SERIAL_TX_READY_MSB         9
+#define UART_CONTROL_SERIAL_TX_READY_LSB         9
+#define UART_CONTROL_SERIAL_TX_READY_MASK        0x00000200
+#define UART_CONTROL_SERIAL_TX_READY_GET(x)      (((x) & UART_CONTROL_SERIAL_TX_READY_MASK) >> UART_CONTROL_SERIAL_TX_READY_LSB)
+#define UART_CONTROL_SERIAL_TX_READY_SET(x)      (((x) << UART_CONTROL_SERIAL_TX_READY_LSB) & UART_CONTROL_SERIAL_TX_READY_MASK)
+#define UART_CONTROL_TX_READY_ORIDE_MSB          8
+#define UART_CONTROL_TX_READY_ORIDE_LSB          8
+#define UART_CONTROL_TX_READY_ORIDE_MASK         0x00000100
+#define UART_CONTROL_TX_READY_ORIDE_GET(x)       (((x) & UART_CONTROL_TX_READY_ORIDE_MASK) >> UART_CONTROL_TX_READY_ORIDE_LSB)
+#define UART_CONTROL_TX_READY_ORIDE_SET(x)       (((x) << UART_CONTROL_TX_READY_ORIDE_LSB) & UART_CONTROL_TX_READY_ORIDE_MASK)
+#define UART_CONTROL_RX_READY_ORIDE_MSB          7
+#define UART_CONTROL_RX_READY_ORIDE_LSB          7
+#define UART_CONTROL_RX_READY_ORIDE_MASK         0x00000080
+#define UART_CONTROL_RX_READY_ORIDE_GET(x)       (((x) & UART_CONTROL_RX_READY_ORIDE_MASK) >> UART_CONTROL_RX_READY_ORIDE_LSB)
+#define UART_CONTROL_RX_READY_ORIDE_SET(x)       (((x) << UART_CONTROL_RX_READY_ORIDE_LSB) & UART_CONTROL_RX_READY_ORIDE_MASK)
+#define UART_CONTROL_DMA_ENABLE_MSB              6
+#define UART_CONTROL_DMA_ENABLE_LSB              6
+#define UART_CONTROL_DMA_ENABLE_MASK             0x00000040
+#define UART_CONTROL_DMA_ENABLE_GET(x)           (((x) & UART_CONTROL_DMA_ENABLE_MASK) >> UART_CONTROL_DMA_ENABLE_LSB)
+#define UART_CONTROL_DMA_ENABLE_SET(x)           (((x) << UART_CONTROL_DMA_ENABLE_LSB) & UART_CONTROL_DMA_ENABLE_MASK)
+#define UART_CONTROL_FLOW_ENABLE_MSB             5
+#define UART_CONTROL_FLOW_ENABLE_LSB             5
+#define UART_CONTROL_FLOW_ENABLE_MASK            0x00000020
+#define UART_CONTROL_FLOW_ENABLE_GET(x)          (((x) & UART_CONTROL_FLOW_ENABLE_MASK) >> UART_CONTROL_FLOW_ENABLE_LSB)
+#define UART_CONTROL_FLOW_ENABLE_SET(x)          (((x) << UART_CONTROL_FLOW_ENABLE_LSB) & UART_CONTROL_FLOW_ENABLE_MASK)
+#define UART_CONTROL_FLOW_INVERT_MSB             4
+#define UART_CONTROL_FLOW_INVERT_LSB             4
+#define UART_CONTROL_FLOW_INVERT_MASK            0x00000010
+#define UART_CONTROL_FLOW_INVERT_GET(x)          (((x) & UART_CONTROL_FLOW_INVERT_MASK) >> UART_CONTROL_FLOW_INVERT_LSB)
+#define UART_CONTROL_FLOW_INVERT_SET(x)          (((x) << UART_CONTROL_FLOW_INVERT_LSB) & UART_CONTROL_FLOW_INVERT_MASK)
+#define UART_CONTROL_IFC_ENABLE_MSB              3
+#define UART_CONTROL_IFC_ENABLE_LSB              3
+#define UART_CONTROL_IFC_ENABLE_MASK             0x00000008
+#define UART_CONTROL_IFC_ENABLE_GET(x)           (((x) & UART_CONTROL_IFC_ENABLE_MASK) >> UART_CONTROL_IFC_ENABLE_LSB)
+#define UART_CONTROL_IFC_ENABLE_SET(x)           (((x) << UART_CONTROL_IFC_ENABLE_LSB) & UART_CONTROL_IFC_ENABLE_MASK)
+#define UART_CONTROL_IFC_DCE_MSB                 2
+#define UART_CONTROL_IFC_DCE_LSB                 2
+#define UART_CONTROL_IFC_DCE_MASK                0x00000004
+#define UART_CONTROL_IFC_DCE_GET(x)              (((x) & UART_CONTROL_IFC_DCE_MASK) >> UART_CONTROL_IFC_DCE_LSB)
+#define UART_CONTROL_IFC_DCE_SET(x)              (((x) << UART_CONTROL_IFC_DCE_LSB) & UART_CONTROL_IFC_DCE_MASK)
+#define UART_CONTROL_PARITY_ENABLE_MSB           1
+#define UART_CONTROL_PARITY_ENABLE_LSB           1
+#define UART_CONTROL_PARITY_ENABLE_MASK          0x00000002
+#define UART_CONTROL_PARITY_ENABLE_GET(x)        (((x) & UART_CONTROL_PARITY_ENABLE_MASK) >> UART_CONTROL_PARITY_ENABLE_LSB)
+#define UART_CONTROL_PARITY_ENABLE_SET(x)        (((x) << UART_CONTROL_PARITY_ENABLE_LSB) & UART_CONTROL_PARITY_ENABLE_MASK)
+#define UART_CONTROL_PARITY_EVEN_MSB             0
+#define UART_CONTROL_PARITY_EVEN_LSB             0
+#define UART_CONTROL_PARITY_EVEN_MASK            0x00000001
+#define UART_CONTROL_PARITY_EVEN_GET(x)          (((x) & UART_CONTROL_PARITY_EVEN_MASK) >> UART_CONTROL_PARITY_EVEN_LSB)
+#define UART_CONTROL_PARITY_EVEN_SET(x)          (((x) << UART_CONTROL_PARITY_EVEN_LSB) & UART_CONTROL_PARITY_EVEN_MASK)
+
+#define UART_CLKDIV_ADDRESS                      0x00000008
+#define UART_CLKDIV_OFFSET                       0x00000008
+#define UART_CLKDIV_CLK_SCALE_MSB                23
+#define UART_CLKDIV_CLK_SCALE_LSB                16
+#define UART_CLKDIV_CLK_SCALE_MASK               0x00ff0000
+#define UART_CLKDIV_CLK_SCALE_GET(x)             (((x) & UART_CLKDIV_CLK_SCALE_MASK) >> UART_CLKDIV_CLK_SCALE_LSB)
+#define UART_CLKDIV_CLK_SCALE_SET(x)             (((x) << UART_CLKDIV_CLK_SCALE_LSB) & UART_CLKDIV_CLK_SCALE_MASK)
+#define UART_CLKDIV_CLK_STEP_MSB                 15
+#define UART_CLKDIV_CLK_STEP_LSB                 0
+#define UART_CLKDIV_CLK_STEP_MASK                0x0000ffff
+#define UART_CLKDIV_CLK_STEP_GET(x)              (((x) & UART_CLKDIV_CLK_STEP_MASK) >> UART_CLKDIV_CLK_STEP_LSB)
+#define UART_CLKDIV_CLK_STEP_SET(x)              (((x) << UART_CLKDIV_CLK_STEP_LSB) & UART_CLKDIV_CLK_STEP_MASK)
+
+#define UART_INT_ADDRESS                         0x0000000c
+#define UART_INT_OFFSET                          0x0000000c
+#define UART_INT_TX_EMPTY_INT_MSB                9
+#define UART_INT_TX_EMPTY_INT_LSB                9
+#define UART_INT_TX_EMPTY_INT_MASK               0x00000200
+#define UART_INT_TX_EMPTY_INT_GET(x)             (((x) & UART_INT_TX_EMPTY_INT_MASK) >> UART_INT_TX_EMPTY_INT_LSB)
+#define UART_INT_TX_EMPTY_INT_SET(x)             (((x) << UART_INT_TX_EMPTY_INT_LSB) & UART_INT_TX_EMPTY_INT_MASK)
+#define UART_INT_RX_FULL_INT_MSB                 8
+#define UART_INT_RX_FULL_INT_LSB                 8
+#define UART_INT_RX_FULL_INT_MASK                0x00000100
+#define UART_INT_RX_FULL_INT_GET(x)              (((x) & UART_INT_RX_FULL_INT_MASK) >> UART_INT_RX_FULL_INT_LSB)
+#define UART_INT_RX_FULL_INT_SET(x)              (((x) << UART_INT_RX_FULL_INT_LSB) & UART_INT_RX_FULL_INT_MASK)
+#define UART_INT_RX_BREAK_OFF_INT_MSB            7
+#define UART_INT_RX_BREAK_OFF_INT_LSB            7
+#define UART_INT_RX_BREAK_OFF_INT_MASK           0x00000080
+#define UART_INT_RX_BREAK_OFF_INT_GET(x)         (((x) & UART_INT_RX_BREAK_OFF_INT_MASK) >> UART_INT_RX_BREAK_OFF_INT_LSB)
+#define UART_INT_RX_BREAK_OFF_INT_SET(x)         (((x) << UART_INT_RX_BREAK_OFF_INT_LSB) & UART_INT_RX_BREAK_OFF_INT_MASK)
+#define UART_INT_RX_BREAK_ON_INT_MSB             6
+#define UART_INT_RX_BREAK_ON_INT_LSB             6
+#define UART_INT_RX_BREAK_ON_INT_MASK            0x00000040
+#define UART_INT_RX_BREAK_ON_INT_GET(x)          (((x) & UART_INT_RX_BREAK_ON_INT_MASK) >> UART_INT_RX_BREAK_ON_INT_LSB)
+#define UART_INT_RX_BREAK_ON_INT_SET(x)          (((x) << UART_INT_RX_BREAK_ON_INT_LSB) & UART_INT_RX_BREAK_ON_INT_MASK)
+#define UART_INT_RX_PARITY_ERR_INT_MSB           5
+#define UART_INT_RX_PARITY_ERR_INT_LSB           5
+#define UART_INT_RX_PARITY_ERR_INT_MASK          0x00000020
+#define UART_INT_RX_PARITY_ERR_INT_GET(x)        (((x) & UART_INT_RX_PARITY_ERR_INT_MASK) >> UART_INT_RX_PARITY_ERR_INT_LSB)
+#define UART_INT_RX_PARITY_ERR_INT_SET(x)        (((x) << UART_INT_RX_PARITY_ERR_INT_LSB) & UART_INT_RX_PARITY_ERR_INT_MASK)
+#define UART_INT_TX_OFLOW_ERR_INT_MSB            4
+#define UART_INT_TX_OFLOW_ERR_INT_LSB            4
+#define UART_INT_TX_OFLOW_ERR_INT_MASK           0x00000010
+#define UART_INT_TX_OFLOW_ERR_INT_GET(x)         (((x) & UART_INT_TX_OFLOW_ERR_INT_MASK) >> UART_INT_TX_OFLOW_ERR_INT_LSB)
+#define UART_INT_TX_OFLOW_ERR_INT_SET(x)         (((x) << UART_INT_TX_OFLOW_ERR_INT_LSB) & UART_INT_TX_OFLOW_ERR_INT_MASK)
+#define UART_INT_RX_OFLOW_ERR_INT_MSB            3
+#define UART_INT_RX_OFLOW_ERR_INT_LSB            3
+#define UART_INT_RX_OFLOW_ERR_INT_MASK           0x00000008
+#define UART_INT_RX_OFLOW_ERR_INT_GET(x)         (((x) & UART_INT_RX_OFLOW_ERR_INT_MASK) >> UART_INT_RX_OFLOW_ERR_INT_LSB)
+#define UART_INT_RX_OFLOW_ERR_INT_SET(x)         (((x) << UART_INT_RX_OFLOW_ERR_INT_LSB) & UART_INT_RX_OFLOW_ERR_INT_MASK)
+#define UART_INT_RX_FRAMING_ERR_INT_MSB          2
+#define UART_INT_RX_FRAMING_ERR_INT_LSB          2
+#define UART_INT_RX_FRAMING_ERR_INT_MASK         0x00000004
+#define UART_INT_RX_FRAMING_ERR_INT_GET(x)       (((x) & UART_INT_RX_FRAMING_ERR_INT_MASK) >> UART_INT_RX_FRAMING_ERR_INT_LSB)
+#define UART_INT_RX_FRAMING_ERR_INT_SET(x)       (((x) << UART_INT_RX_FRAMING_ERR_INT_LSB) & UART_INT_RX_FRAMING_ERR_INT_MASK)
+#define UART_INT_TX_READY_INT_MSB                1
+#define UART_INT_TX_READY_INT_LSB                1
+#define UART_INT_TX_READY_INT_MASK               0x00000002
+#define UART_INT_TX_READY_INT_GET(x)             (((x) & UART_INT_TX_READY_INT_MASK) >> UART_INT_TX_READY_INT_LSB)
+#define UART_INT_TX_READY_INT_SET(x)             (((x) << UART_INT_TX_READY_INT_LSB) & UART_INT_TX_READY_INT_MASK)
+#define UART_INT_RX_VALID_INT_MSB                0
+#define UART_INT_RX_VALID_INT_LSB                0
+#define UART_INT_RX_VALID_INT_MASK               0x00000001
+#define UART_INT_RX_VALID_INT_GET(x)             (((x) & UART_INT_RX_VALID_INT_MASK) >> UART_INT_RX_VALID_INT_LSB)
+#define UART_INT_RX_VALID_INT_SET(x)             (((x) << UART_INT_RX_VALID_INT_LSB) & UART_INT_RX_VALID_INT_MASK)
+
+#define UART_INT_EN_ADDRESS                      0x00000010
+#define UART_INT_EN_OFFSET                       0x00000010
+#define UART_INT_EN_TX_EMPTY_INT_EN_MSB          9
+#define UART_INT_EN_TX_EMPTY_INT_EN_LSB          9
+#define UART_INT_EN_TX_EMPTY_INT_EN_MASK         0x00000200
+#define UART_INT_EN_TX_EMPTY_INT_EN_GET(x)       (((x) & UART_INT_EN_TX_EMPTY_INT_EN_MASK) >> UART_INT_EN_TX_EMPTY_INT_EN_LSB)
+#define UART_INT_EN_TX_EMPTY_INT_EN_SET(x)       (((x) << UART_INT_EN_TX_EMPTY_INT_EN_LSB) & UART_INT_EN_TX_EMPTY_INT_EN_MASK)
+#define UART_INT_EN_RX_FULL_INT_EN_MSB           8
+#define UART_INT_EN_RX_FULL_INT_EN_LSB           8
+#define UART_INT_EN_RX_FULL_INT_EN_MASK          0x00000100
+#define UART_INT_EN_RX_FULL_INT_EN_GET(x)        (((x) & UART_INT_EN_RX_FULL_INT_EN_MASK) >> UART_INT_EN_RX_FULL_INT_EN_LSB)
+#define UART_INT_EN_RX_FULL_INT_EN_SET(x)        (((x) << UART_INT_EN_RX_FULL_INT_EN_LSB) & UART_INT_EN_RX_FULL_INT_EN_MASK)
+#define UART_INT_EN_RX_BREAK_OFF_INT_EN_MSB      7
+#define UART_INT_EN_RX_BREAK_OFF_INT_EN_LSB      7
+#define UART_INT_EN_RX_BREAK_OFF_INT_EN_MASK     0x00000080
+#define UART_INT_EN_RX_BREAK_OFF_INT_EN_GET(x)   (((x) & UART_INT_EN_RX_BREAK_OFF_INT_EN_MASK) >> UART_INT_EN_RX_BREAK_OFF_INT_EN_LSB)
+#define UART_INT_EN_RX_BREAK_OFF_INT_EN_SET(x)   (((x) << UART_INT_EN_RX_BREAK_OFF_INT_EN_LSB) & UART_INT_EN_RX_BREAK_OFF_INT_EN_MASK)
+#define UART_INT_EN_RX_BREAK_ON_INT_EN_MSB       6
+#define UART_INT_EN_RX_BREAK_ON_INT_EN_LSB       6
+#define UART_INT_EN_RX_BREAK_ON_INT_EN_MASK      0x00000040
+#define UART_INT_EN_RX_BREAK_ON_INT_EN_GET(x)    (((x) & UART_INT_EN_RX_BREAK_ON_INT_EN_MASK) >> UART_INT_EN_RX_BREAK_ON_INT_EN_LSB)
+#define UART_INT_EN_RX_BREAK_ON_INT_EN_SET(x)    (((x) << UART_INT_EN_RX_BREAK_ON_INT_EN_LSB) & UART_INT_EN_RX_BREAK_ON_INT_EN_MASK)
+#define UART_INT_EN_RX_PARITY_ERR_INT_EN_MSB     5
+#define UART_INT_EN_RX_PARITY_ERR_INT_EN_LSB     5
+#define UART_INT_EN_RX_PARITY_ERR_INT_EN_MASK    0x00000020
+#define UART_INT_EN_RX_PARITY_ERR_INT_EN_GET(x)  (((x) & UART_INT_EN_RX_PARITY_ERR_INT_EN_MASK) >> UART_INT_EN_RX_PARITY_ERR_INT_EN_LSB)
+#define UART_INT_EN_RX_PARITY_ERR_INT_EN_SET(x)  (((x) << UART_INT_EN_RX_PARITY_ERR_INT_EN_LSB) & UART_INT_EN_RX_PARITY_ERR_INT_EN_MASK)
+#define UART_INT_EN_TX_OFLOW_ERR_INT_EN_MSB      4
+#define UART_INT_EN_TX_OFLOW_ERR_INT_EN_LSB      4
+#define UART_INT_EN_TX_OFLOW_ERR_INT_EN_MASK     0x00000010
+#define UART_INT_EN_TX_OFLOW_ERR_INT_EN_GET(x)   (((x) & UART_INT_EN_TX_OFLOW_ERR_INT_EN_MASK) >> UART_INT_EN_TX_OFLOW_ERR_INT_EN_LSB)
+#define UART_INT_EN_TX_OFLOW_ERR_INT_EN_SET(x)   (((x) << UART_INT_EN_TX_OFLOW_ERR_INT_EN_LSB) & UART_INT_EN_TX_OFLOW_ERR_INT_EN_MASK)
+#define UART_INT_EN_RX_OFLOW_ERR_INT_EN_MSB      3
+#define UART_INT_EN_RX_OFLOW_ERR_INT_EN_LSB      3
+#define UART_INT_EN_RX_OFLOW_ERR_INT_EN_MASK     0x00000008
+#define UART_INT_EN_RX_OFLOW_ERR_INT_EN_GET(x)   (((x) & UART_INT_EN_RX_OFLOW_ERR_INT_EN_MASK) >> UART_INT_EN_RX_OFLOW_ERR_INT_EN_LSB)
+#define UART_INT_EN_RX_OFLOW_ERR_INT_EN_SET(x)   (((x) << UART_INT_EN_RX_OFLOW_ERR_INT_EN_LSB) & UART_INT_EN_RX_OFLOW_ERR_INT_EN_MASK)
+#define UART_INT_EN_RX_FRAMING_ERR_INT_EN_MSB    2
+#define UART_INT_EN_RX_FRAMING_ERR_INT_EN_LSB    2
+#define UART_INT_EN_RX_FRAMING_ERR_INT_EN_MASK   0x00000004
+#define UART_INT_EN_RX_FRAMING_ERR_INT_EN_GET(x) (((x) & UART_INT_EN_RX_FRAMING_ERR_INT_EN_MASK) >> UART_INT_EN_RX_FRAMING_ERR_INT_EN_LSB)
+#define UART_INT_EN_RX_FRAMING_ERR_INT_EN_SET(x) (((x) << UART_INT_EN_RX_FRAMING_ERR_INT_EN_LSB) & UART_INT_EN_RX_FRAMING_ERR_INT_EN_MASK)
+#define UART_INT_EN_TX_READY_INT_EN_MSB          1
+#define UART_INT_EN_TX_READY_INT_EN_LSB          1
+#define UART_INT_EN_TX_READY_INT_EN_MASK         0x00000002
+#define UART_INT_EN_TX_READY_INT_EN_GET(x)       (((x) & UART_INT_EN_TX_READY_INT_EN_MASK) >> UART_INT_EN_TX_READY_INT_EN_LSB)
+#define UART_INT_EN_TX_READY_INT_EN_SET(x)       (((x) << UART_INT_EN_TX_READY_INT_EN_LSB) & UART_INT_EN_TX_READY_INT_EN_MASK)
+#define UART_INT_EN_RX_VALID_INT_EN_MSB          0
+#define UART_INT_EN_RX_VALID_INT_EN_LSB          0
+#define UART_INT_EN_RX_VALID_INT_EN_MASK         0x00000001
+#define UART_INT_EN_RX_VALID_INT_EN_GET(x)       (((x) & UART_INT_EN_RX_VALID_INT_EN_MASK) >> UART_INT_EN_RX_VALID_INT_EN_LSB)
+#define UART_INT_EN_RX_VALID_INT_EN_SET(x)       (((x) << UART_INT_EN_RX_VALID_INT_EN_LSB) & UART_INT_EN_RX_VALID_INT_EN_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct uart_reg_reg_s {
+  volatile unsigned int uart_data;
+  volatile unsigned int uart_control;
+  volatile unsigned int uart_clkdiv;
+  volatile unsigned int uart_int;
+  volatile unsigned int uart_int_en;
+} uart_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _UART_REG_H_ */
diff --git a/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/umbox_reg.h b/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/umbox_reg.h
new file mode 100644
index 00000000000..b233cbc513b
--- /dev/null
+++ b/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/umbox_reg.h
@@ -0,0 +1,37 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifdef WLAN_HEADERS
+
+#include "umbox_wlan_reg.h"
+
+
+#ifndef BT_HEADERS
+
+
+
+#endif
+#endif
+
+
+
diff --git a/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/umbox_wlan_reg.h b/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/umbox_wlan_reg.h
new file mode 100644
index 00000000000..4737a2805b2
--- /dev/null
+++ b/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/umbox_wlan_reg.h
@@ -0,0 +1,322 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _UMBOX_WLAN_REG_REG_H_
+#define _UMBOX_WLAN_REG_REG_H_
+
+#define UMBOX_FIFO_ADDRESS                       0x00000000
+#define UMBOX_FIFO_OFFSET                        0x00000000
+#define UMBOX_FIFO_DATA_MSB                      8
+#define UMBOX_FIFO_DATA_LSB                      0
+#define UMBOX_FIFO_DATA_MASK                     0x000001ff
+#define UMBOX_FIFO_DATA_GET(x)                   (((x) & UMBOX_FIFO_DATA_MASK) >> UMBOX_FIFO_DATA_LSB)
+#define UMBOX_FIFO_DATA_SET(x)                   (((x) << UMBOX_FIFO_DATA_LSB) & UMBOX_FIFO_DATA_MASK)
+
+#define UMBOX_FIFO_STATUS_ADDRESS                0x00000008
+#define UMBOX_FIFO_STATUS_OFFSET                 0x00000008
+#define UMBOX_FIFO_STATUS_TX_EMPTY_MSB           3
+#define UMBOX_FIFO_STATUS_TX_EMPTY_LSB           3
+#define UMBOX_FIFO_STATUS_TX_EMPTY_MASK          0x00000008
+#define UMBOX_FIFO_STATUS_TX_EMPTY_GET(x)        (((x) & UMBOX_FIFO_STATUS_TX_EMPTY_MASK) >> UMBOX_FIFO_STATUS_TX_EMPTY_LSB)
+#define UMBOX_FIFO_STATUS_TX_EMPTY_SET(x)        (((x) << UMBOX_FIFO_STATUS_TX_EMPTY_LSB) & UMBOX_FIFO_STATUS_TX_EMPTY_MASK)
+#define UMBOX_FIFO_STATUS_TX_FULL_MSB            2
+#define UMBOX_FIFO_STATUS_TX_FULL_LSB            2
+#define UMBOX_FIFO_STATUS_TX_FULL_MASK           0x00000004
+#define UMBOX_FIFO_STATUS_TX_FULL_GET(x)         (((x) & UMBOX_FIFO_STATUS_TX_FULL_MASK) >> UMBOX_FIFO_STATUS_TX_FULL_LSB)
+#define UMBOX_FIFO_STATUS_TX_FULL_SET(x)         (((x) << UMBOX_FIFO_STATUS_TX_FULL_LSB) & UMBOX_FIFO_STATUS_TX_FULL_MASK)
+#define UMBOX_FIFO_STATUS_RX_EMPTY_MSB           1
+#define UMBOX_FIFO_STATUS_RX_EMPTY_LSB           1
+#define UMBOX_FIFO_STATUS_RX_EMPTY_MASK          0x00000002
+#define UMBOX_FIFO_STATUS_RX_EMPTY_GET(x)        (((x) & UMBOX_FIFO_STATUS_RX_EMPTY_MASK) >> UMBOX_FIFO_STATUS_RX_EMPTY_LSB)
+#define UMBOX_FIFO_STATUS_RX_EMPTY_SET(x)        (((x) << UMBOX_FIFO_STATUS_RX_EMPTY_LSB) & UMBOX_FIFO_STATUS_RX_EMPTY_MASK)
+#define UMBOX_FIFO_STATUS_RX_FULL_MSB            0
+#define UMBOX_FIFO_STATUS_RX_FULL_LSB            0
+#define UMBOX_FIFO_STATUS_RX_FULL_MASK           0x00000001
+#define UMBOX_FIFO_STATUS_RX_FULL_GET(x)         (((x) & UMBOX_FIFO_STATUS_RX_FULL_MASK) >> UMBOX_FIFO_STATUS_RX_FULL_LSB)
+#define UMBOX_FIFO_STATUS_RX_FULL_SET(x)         (((x) << UMBOX_FIFO_STATUS_RX_FULL_LSB) & UMBOX_FIFO_STATUS_RX_FULL_MASK)
+
+#define UMBOX_DMA_POLICY_ADDRESS                 0x0000000c
+#define UMBOX_DMA_POLICY_OFFSET                  0x0000000c
+#define UMBOX_DMA_POLICY_TX_QUANTUM_MSB          3
+#define UMBOX_DMA_POLICY_TX_QUANTUM_LSB          3
+#define UMBOX_DMA_POLICY_TX_QUANTUM_MASK         0x00000008
+#define UMBOX_DMA_POLICY_TX_QUANTUM_GET(x)       (((x) & UMBOX_DMA_POLICY_TX_QUANTUM_MASK) >> UMBOX_DMA_POLICY_TX_QUANTUM_LSB)
+#define UMBOX_DMA_POLICY_TX_QUANTUM_SET(x)       (((x) << UMBOX_DMA_POLICY_TX_QUANTUM_LSB) & UMBOX_DMA_POLICY_TX_QUANTUM_MASK)
+#define UMBOX_DMA_POLICY_TX_ORDER_MSB            2
+#define UMBOX_DMA_POLICY_TX_ORDER_LSB            2
+#define UMBOX_DMA_POLICY_TX_ORDER_MASK           0x00000004
+#define UMBOX_DMA_POLICY_TX_ORDER_GET(x)         (((x) & UMBOX_DMA_POLICY_TX_ORDER_MASK) >> UMBOX_DMA_POLICY_TX_ORDER_LSB)
+#define UMBOX_DMA_POLICY_TX_ORDER_SET(x)         (((x) << UMBOX_DMA_POLICY_TX_ORDER_LSB) & UMBOX_DMA_POLICY_TX_ORDER_MASK)
+#define UMBOX_DMA_POLICY_RX_QUANTUM_MSB          1
+#define UMBOX_DMA_POLICY_RX_QUANTUM_LSB          1
+#define UMBOX_DMA_POLICY_RX_QUANTUM_MASK         0x00000002
+#define UMBOX_DMA_POLICY_RX_QUANTUM_GET(x)       (((x) & UMBOX_DMA_POLICY_RX_QUANTUM_MASK) >> UMBOX_DMA_POLICY_RX_QUANTUM_LSB)
+#define UMBOX_DMA_POLICY_RX_QUANTUM_SET(x)       (((x) << UMBOX_DMA_POLICY_RX_QUANTUM_LSB) & UMBOX_DMA_POLICY_RX_QUANTUM_MASK)
+#define UMBOX_DMA_POLICY_RX_ORDER_MSB            0
+#define UMBOX_DMA_POLICY_RX_ORDER_LSB            0
+#define UMBOX_DMA_POLICY_RX_ORDER_MASK           0x00000001
+#define UMBOX_DMA_POLICY_RX_ORDER_GET(x)         (((x) & UMBOX_DMA_POLICY_RX_ORDER_MASK) >> UMBOX_DMA_POLICY_RX_ORDER_LSB)
+#define UMBOX_DMA_POLICY_RX_ORDER_SET(x)         (((x) << UMBOX_DMA_POLICY_RX_ORDER_LSB) & UMBOX_DMA_POLICY_RX_ORDER_MASK)
+
+#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS    0x00000010
+#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET     0x00000010
+#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define UMBOX0_DMA_RX_CONTROL_ADDRESS            0x00000014
+#define UMBOX0_DMA_RX_CONTROL_OFFSET             0x00000014
+#define UMBOX0_DMA_RX_CONTROL_RESUME_MSB         2
+#define UMBOX0_DMA_RX_CONTROL_RESUME_LSB         2
+#define UMBOX0_DMA_RX_CONTROL_RESUME_MASK        0x00000004
+#define UMBOX0_DMA_RX_CONTROL_RESUME_GET(x)      (((x) & UMBOX0_DMA_RX_CONTROL_RESUME_MASK) >> UMBOX0_DMA_RX_CONTROL_RESUME_LSB)
+#define UMBOX0_DMA_RX_CONTROL_RESUME_SET(x)      (((x) << UMBOX0_DMA_RX_CONTROL_RESUME_LSB) & UMBOX0_DMA_RX_CONTROL_RESUME_MASK)
+#define UMBOX0_DMA_RX_CONTROL_START_MSB          1
+#define UMBOX0_DMA_RX_CONTROL_START_LSB          1
+#define UMBOX0_DMA_RX_CONTROL_START_MASK         0x00000002
+#define UMBOX0_DMA_RX_CONTROL_START_GET(x)       (((x) & UMBOX0_DMA_RX_CONTROL_START_MASK) >> UMBOX0_DMA_RX_CONTROL_START_LSB)
+#define UMBOX0_DMA_RX_CONTROL_START_SET(x)       (((x) << UMBOX0_DMA_RX_CONTROL_START_LSB) & UMBOX0_DMA_RX_CONTROL_START_MASK)
+#define UMBOX0_DMA_RX_CONTROL_STOP_MSB           0
+#define UMBOX0_DMA_RX_CONTROL_STOP_LSB           0
+#define UMBOX0_DMA_RX_CONTROL_STOP_MASK          0x00000001
+#define UMBOX0_DMA_RX_CONTROL_STOP_GET(x)        (((x) & UMBOX0_DMA_RX_CONTROL_STOP_MASK) >> UMBOX0_DMA_RX_CONTROL_STOP_LSB)
+#define UMBOX0_DMA_RX_CONTROL_STOP_SET(x)        (((x) << UMBOX0_DMA_RX_CONTROL_STOP_LSB) & UMBOX0_DMA_RX_CONTROL_STOP_MASK)
+
+#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS    0x00000018
+#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET     0x00000018
+#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define UMBOX0_DMA_TX_CONTROL_ADDRESS            0x0000001c
+#define UMBOX0_DMA_TX_CONTROL_OFFSET             0x0000001c
+#define UMBOX0_DMA_TX_CONTROL_RESUME_MSB         2
+#define UMBOX0_DMA_TX_CONTROL_RESUME_LSB         2
+#define UMBOX0_DMA_TX_CONTROL_RESUME_MASK        0x00000004
+#define UMBOX0_DMA_TX_CONTROL_RESUME_GET(x)      (((x) & UMBOX0_DMA_TX_CONTROL_RESUME_MASK) >> UMBOX0_DMA_TX_CONTROL_RESUME_LSB)
+#define UMBOX0_DMA_TX_CONTROL_RESUME_SET(x)      (((x) << UMBOX0_DMA_TX_CONTROL_RESUME_LSB) & UMBOX0_DMA_TX_CONTROL_RESUME_MASK)
+#define UMBOX0_DMA_TX_CONTROL_START_MSB          1
+#define UMBOX0_DMA_TX_CONTROL_START_LSB          1
+#define UMBOX0_DMA_TX_CONTROL_START_MASK         0x00000002
+#define UMBOX0_DMA_TX_CONTROL_START_GET(x)       (((x) & UMBOX0_DMA_TX_CONTROL_START_MASK) >> UMBOX0_DMA_TX_CONTROL_START_LSB)
+#define UMBOX0_DMA_TX_CONTROL_START_SET(x)       (((x) << UMBOX0_DMA_TX_CONTROL_START_LSB) & UMBOX0_DMA_TX_CONTROL_START_MASK)
+#define UMBOX0_DMA_TX_CONTROL_STOP_MSB           0
+#define UMBOX0_DMA_TX_CONTROL_STOP_LSB           0
+#define UMBOX0_DMA_TX_CONTROL_STOP_MASK          0x00000001
+#define UMBOX0_DMA_TX_CONTROL_STOP_GET(x)        (((x) & UMBOX0_DMA_TX_CONTROL_STOP_MASK) >> UMBOX0_DMA_TX_CONTROL_STOP_LSB)
+#define UMBOX0_DMA_TX_CONTROL_STOP_SET(x)        (((x) << UMBOX0_DMA_TX_CONTROL_STOP_LSB) & UMBOX0_DMA_TX_CONTROL_STOP_MASK)
+
+#define UMBOX_FIFO_TIMEOUT_ADDRESS               0x00000020
+#define UMBOX_FIFO_TIMEOUT_OFFSET                0x00000020
+#define UMBOX_FIFO_TIMEOUT_ENABLE_SET_MSB        8
+#define UMBOX_FIFO_TIMEOUT_ENABLE_SET_LSB        8
+#define UMBOX_FIFO_TIMEOUT_ENABLE_SET_MASK       0x00000100
+#define UMBOX_FIFO_TIMEOUT_ENABLE_SET_GET(x)     (((x) & UMBOX_FIFO_TIMEOUT_ENABLE_SET_MASK) >> UMBOX_FIFO_TIMEOUT_ENABLE_SET_LSB)
+#define UMBOX_FIFO_TIMEOUT_ENABLE_SET_SET(x)     (((x) << UMBOX_FIFO_TIMEOUT_ENABLE_SET_LSB) & UMBOX_FIFO_TIMEOUT_ENABLE_SET_MASK)
+#define UMBOX_FIFO_TIMEOUT_VALUE_MSB             7
+#define UMBOX_FIFO_TIMEOUT_VALUE_LSB             0
+#define UMBOX_FIFO_TIMEOUT_VALUE_MASK            0x000000ff
+#define UMBOX_FIFO_TIMEOUT_VALUE_GET(x)          (((x) & UMBOX_FIFO_TIMEOUT_VALUE_MASK) >> UMBOX_FIFO_TIMEOUT_VALUE_LSB)
+#define UMBOX_FIFO_TIMEOUT_VALUE_SET(x)          (((x) << UMBOX_FIFO_TIMEOUT_VALUE_LSB) & UMBOX_FIFO_TIMEOUT_VALUE_MASK)
+
+#define UMBOX_INT_STATUS_ADDRESS                 0x00000024
+#define UMBOX_INT_STATUS_OFFSET                  0x00000024
+#define UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_MSB 9
+#define UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_LSB 9
+#define UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_MASK 0x00000200
+#define UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_GET(x) (((x) & UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_MASK) >> UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_LSB)
+#define UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_SET(x) (((x) << UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_LSB) & UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_MASK)
+#define UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_MSB 8
+#define UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_LSB 8
+#define UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_MASK 0x00000100
+#define UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_GET(x) (((x) & UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_MASK) >> UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_LSB)
+#define UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_SET(x) (((x) << UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_LSB) & UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_MASK)
+#define UMBOX_INT_STATUS_RX_DMA_COMPLETE_MSB     7
+#define UMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB     7
+#define UMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK    0x00000080
+#define UMBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x)  (((x) & UMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK) >> UMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB)
+#define UMBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x)  (((x) << UMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB) & UMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK)
+#define UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB 6
+#define UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB 6
+#define UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK 0x00000040
+#define UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) (((x) & UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK) >> UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB)
+#define UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) (((x) << UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB) & UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK)
+#define UMBOX_INT_STATUS_TX_DMA_COMPLETE_MSB     5
+#define UMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB     5
+#define UMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK    0x00000020
+#define UMBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x)  (((x) & UMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK) >> UMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB)
+#define UMBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x)  (((x) << UMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB) & UMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK)
+#define UMBOX_INT_STATUS_HCI_SYNC_ERROR_MSB      4
+#define UMBOX_INT_STATUS_HCI_SYNC_ERROR_LSB      4
+#define UMBOX_INT_STATUS_HCI_SYNC_ERROR_MASK     0x00000010
+#define UMBOX_INT_STATUS_HCI_SYNC_ERROR_GET(x)   (((x) & UMBOX_INT_STATUS_HCI_SYNC_ERROR_MASK) >> UMBOX_INT_STATUS_HCI_SYNC_ERROR_LSB)
+#define UMBOX_INT_STATUS_HCI_SYNC_ERROR_SET(x)   (((x) << UMBOX_INT_STATUS_HCI_SYNC_ERROR_LSB) & UMBOX_INT_STATUS_HCI_SYNC_ERROR_MASK)
+#define UMBOX_INT_STATUS_TX_OVERFLOW_MSB         3
+#define UMBOX_INT_STATUS_TX_OVERFLOW_LSB         3
+#define UMBOX_INT_STATUS_TX_OVERFLOW_MASK        0x00000008
+#define UMBOX_INT_STATUS_TX_OVERFLOW_GET(x)      (((x) & UMBOX_INT_STATUS_TX_OVERFLOW_MASK) >> UMBOX_INT_STATUS_TX_OVERFLOW_LSB)
+#define UMBOX_INT_STATUS_TX_OVERFLOW_SET(x)      (((x) << UMBOX_INT_STATUS_TX_OVERFLOW_LSB) & UMBOX_INT_STATUS_TX_OVERFLOW_MASK)
+#define UMBOX_INT_STATUS_RX_UNDERFLOW_MSB        2
+#define UMBOX_INT_STATUS_RX_UNDERFLOW_LSB        2
+#define UMBOX_INT_STATUS_RX_UNDERFLOW_MASK       0x00000004
+#define UMBOX_INT_STATUS_RX_UNDERFLOW_GET(x)     (((x) & UMBOX_INT_STATUS_RX_UNDERFLOW_MASK) >> UMBOX_INT_STATUS_RX_UNDERFLOW_LSB)
+#define UMBOX_INT_STATUS_RX_UNDERFLOW_SET(x)     (((x) << UMBOX_INT_STATUS_RX_UNDERFLOW_LSB) & UMBOX_INT_STATUS_RX_UNDERFLOW_MASK)
+#define UMBOX_INT_STATUS_TX_NOT_EMPTY_MSB        1
+#define UMBOX_INT_STATUS_TX_NOT_EMPTY_LSB        1
+#define UMBOX_INT_STATUS_TX_NOT_EMPTY_MASK       0x00000002
+#define UMBOX_INT_STATUS_TX_NOT_EMPTY_GET(x)     (((x) & UMBOX_INT_STATUS_TX_NOT_EMPTY_MASK) >> UMBOX_INT_STATUS_TX_NOT_EMPTY_LSB)
+#define UMBOX_INT_STATUS_TX_NOT_EMPTY_SET(x)     (((x) << UMBOX_INT_STATUS_TX_NOT_EMPTY_LSB) & UMBOX_INT_STATUS_TX_NOT_EMPTY_MASK)
+#define UMBOX_INT_STATUS_RX_NOT_FULL_MSB         0
+#define UMBOX_INT_STATUS_RX_NOT_FULL_LSB         0
+#define UMBOX_INT_STATUS_RX_NOT_FULL_MASK        0x00000001
+#define UMBOX_INT_STATUS_RX_NOT_FULL_GET(x)      (((x) & UMBOX_INT_STATUS_RX_NOT_FULL_MASK) >> UMBOX_INT_STATUS_RX_NOT_FULL_LSB)
+#define UMBOX_INT_STATUS_RX_NOT_FULL_SET(x)      (((x) << UMBOX_INT_STATUS_RX_NOT_FULL_LSB) & UMBOX_INT_STATUS_RX_NOT_FULL_MASK)
+
+#define UMBOX_INT_ENABLE_ADDRESS                 0x00000028
+#define UMBOX_INT_ENABLE_OFFSET                  0x00000028
+#define UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_MSB 9
+#define UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_LSB 9
+#define UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_MASK 0x00000200
+#define UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_GET(x) (((x) & UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_MASK) >> UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_LSB)
+#define UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_SET(x) (((x) << UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_LSB) & UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_MASK)
+#define UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_MSB 8
+#define UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_LSB 8
+#define UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_MASK 0x00000100
+#define UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_GET(x) (((x) & UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_MASK) >> UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_LSB)
+#define UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_SET(x) (((x) << UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_LSB) & UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_MASK)
+#define UMBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB     7
+#define UMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB     7
+#define UMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK    0x00000080
+#define UMBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x)  (((x) & UMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK) >> UMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB)
+#define UMBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x)  (((x) << UMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB) & UMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK)
+#define UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB 6
+#define UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB 6
+#define UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK 0x00000040
+#define UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) (((x) & UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK) >> UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB)
+#define UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) (((x) << UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB) & UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK)
+#define UMBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB     5
+#define UMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB     5
+#define UMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK    0x00000020
+#define UMBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x)  (((x) & UMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK) >> UMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB)
+#define UMBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x)  (((x) << UMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB) & UMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK)
+#define UMBOX_INT_ENABLE_HCI_SYNC_ERROR_MSB      4
+#define UMBOX_INT_ENABLE_HCI_SYNC_ERROR_LSB      4
+#define UMBOX_INT_ENABLE_HCI_SYNC_ERROR_MASK     0x00000010
+#define UMBOX_INT_ENABLE_HCI_SYNC_ERROR_GET(x)   (((x) & UMBOX_INT_ENABLE_HCI_SYNC_ERROR_MASK) >> UMBOX_INT_ENABLE_HCI_SYNC_ERROR_LSB)
+#define UMBOX_INT_ENABLE_HCI_SYNC_ERROR_SET(x)   (((x) << UMBOX_INT_ENABLE_HCI_SYNC_ERROR_LSB) & UMBOX_INT_ENABLE_HCI_SYNC_ERROR_MASK)
+#define UMBOX_INT_ENABLE_TX_OVERFLOW_MSB         3
+#define UMBOX_INT_ENABLE_TX_OVERFLOW_LSB         3
+#define UMBOX_INT_ENABLE_TX_OVERFLOW_MASK        0x00000008
+#define UMBOX_INT_ENABLE_TX_OVERFLOW_GET(x)      (((x) & UMBOX_INT_ENABLE_TX_OVERFLOW_MASK) >> UMBOX_INT_ENABLE_TX_OVERFLOW_LSB)
+#define UMBOX_INT_ENABLE_TX_OVERFLOW_SET(x)      (((x) << UMBOX_INT_ENABLE_TX_OVERFLOW_LSB) & UMBOX_INT_ENABLE_TX_OVERFLOW_MASK)
+#define UMBOX_INT_ENABLE_RX_UNDERFLOW_MSB        2
+#define UMBOX_INT_ENABLE_RX_UNDERFLOW_LSB        2
+#define UMBOX_INT_ENABLE_RX_UNDERFLOW_MASK       0x00000004
+#define UMBOX_INT_ENABLE_RX_UNDERFLOW_GET(x)     (((x) & UMBOX_INT_ENABLE_RX_UNDERFLOW_MASK) >> UMBOX_INT_ENABLE_RX_UNDERFLOW_LSB)
+#define UMBOX_INT_ENABLE_RX_UNDERFLOW_SET(x)     (((x) << UMBOX_INT_ENABLE_RX_UNDERFLOW_LSB) & UMBOX_INT_ENABLE_RX_UNDERFLOW_MASK)
+#define UMBOX_INT_ENABLE_TX_NOT_EMPTY_MSB        1
+#define UMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB        1
+#define UMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK       0x00000002
+#define UMBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x)     (((x) & UMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK) >> UMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB)
+#define UMBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x)     (((x) << UMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB) & UMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK)
+#define UMBOX_INT_ENABLE_RX_NOT_FULL_MSB         0
+#define UMBOX_INT_ENABLE_RX_NOT_FULL_LSB         0
+#define UMBOX_INT_ENABLE_RX_NOT_FULL_MASK        0x00000001
+#define UMBOX_INT_ENABLE_RX_NOT_FULL_GET(x)      (((x) & UMBOX_INT_ENABLE_RX_NOT_FULL_MASK) >> UMBOX_INT_ENABLE_RX_NOT_FULL_LSB)
+#define UMBOX_INT_ENABLE_RX_NOT_FULL_SET(x)      (((x) << UMBOX_INT_ENABLE_RX_NOT_FULL_LSB) & UMBOX_INT_ENABLE_RX_NOT_FULL_MASK)
+
+#define UMBOX_DEBUG_ADDRESS                      0x0000002c
+#define UMBOX_DEBUG_OFFSET                       0x0000002c
+#define UMBOX_DEBUG_SEL_MSB                      2
+#define UMBOX_DEBUG_SEL_LSB                      0
+#define UMBOX_DEBUG_SEL_MASK                     0x00000007
+#define UMBOX_DEBUG_SEL_GET(x)                   (((x) & UMBOX_DEBUG_SEL_MASK) >> UMBOX_DEBUG_SEL_LSB)
+#define UMBOX_DEBUG_SEL_SET(x)                   (((x) << UMBOX_DEBUG_SEL_LSB) & UMBOX_DEBUG_SEL_MASK)
+
+#define UMBOX_FIFO_RESET_ADDRESS                 0x00000030
+#define UMBOX_FIFO_RESET_OFFSET                  0x00000030
+#define UMBOX_FIFO_RESET_INIT_MSB                0
+#define UMBOX_FIFO_RESET_INIT_LSB                0
+#define UMBOX_FIFO_RESET_INIT_MASK               0x00000001
+#define UMBOX_FIFO_RESET_INIT_GET(x)             (((x) & UMBOX_FIFO_RESET_INIT_MASK) >> UMBOX_FIFO_RESET_INIT_LSB)
+#define UMBOX_FIFO_RESET_INIT_SET(x)             (((x) << UMBOX_FIFO_RESET_INIT_LSB) & UMBOX_FIFO_RESET_INIT_MASK)
+
+#define UMBOX_HCI_FRAMER_ADDRESS                 0x00000034
+#define UMBOX_HCI_FRAMER_OFFSET                  0x00000034
+#define UMBOX_HCI_FRAMER_CRC_OVERRIDE_MSB        6
+#define UMBOX_HCI_FRAMER_CRC_OVERRIDE_LSB        6
+#define UMBOX_HCI_FRAMER_CRC_OVERRIDE_MASK       0x00000040
+#define UMBOX_HCI_FRAMER_CRC_OVERRIDE_GET(x)     (((x) & UMBOX_HCI_FRAMER_CRC_OVERRIDE_MASK) >> UMBOX_HCI_FRAMER_CRC_OVERRIDE_LSB)
+#define UMBOX_HCI_FRAMER_CRC_OVERRIDE_SET(x)     (((x) << UMBOX_HCI_FRAMER_CRC_OVERRIDE_LSB) & UMBOX_HCI_FRAMER_CRC_OVERRIDE_MASK)
+#define UMBOX_HCI_FRAMER_ENABLE_MSB              5
+#define UMBOX_HCI_FRAMER_ENABLE_LSB              5
+#define UMBOX_HCI_FRAMER_ENABLE_MASK             0x00000020
+#define UMBOX_HCI_FRAMER_ENABLE_GET(x)           (((x) & UMBOX_HCI_FRAMER_ENABLE_MASK) >> UMBOX_HCI_FRAMER_ENABLE_LSB)
+#define UMBOX_HCI_FRAMER_ENABLE_SET(x)           (((x) << UMBOX_HCI_FRAMER_ENABLE_LSB) & UMBOX_HCI_FRAMER_ENABLE_MASK)
+#define UMBOX_HCI_FRAMER_SYNC_ERROR_MSB          4
+#define UMBOX_HCI_FRAMER_SYNC_ERROR_LSB          4
+#define UMBOX_HCI_FRAMER_SYNC_ERROR_MASK         0x00000010
+#define UMBOX_HCI_FRAMER_SYNC_ERROR_GET(x)       (((x) & UMBOX_HCI_FRAMER_SYNC_ERROR_MASK) >> UMBOX_HCI_FRAMER_SYNC_ERROR_LSB)
+#define UMBOX_HCI_FRAMER_SYNC_ERROR_SET(x)       (((x) << UMBOX_HCI_FRAMER_SYNC_ERROR_LSB) & UMBOX_HCI_FRAMER_SYNC_ERROR_MASK)
+#define UMBOX_HCI_FRAMER_UNDERFLOW_MSB           3
+#define UMBOX_HCI_FRAMER_UNDERFLOW_LSB           3
+#define UMBOX_HCI_FRAMER_UNDERFLOW_MASK          0x00000008
+#define UMBOX_HCI_FRAMER_UNDERFLOW_GET(x)        (((x) & UMBOX_HCI_FRAMER_UNDERFLOW_MASK) >> UMBOX_HCI_FRAMER_UNDERFLOW_LSB)
+#define UMBOX_HCI_FRAMER_UNDERFLOW_SET(x)        (((x) << UMBOX_HCI_FRAMER_UNDERFLOW_LSB) & UMBOX_HCI_FRAMER_UNDERFLOW_MASK)
+#define UMBOX_HCI_FRAMER_OVERFLOW_MSB            2
+#define UMBOX_HCI_FRAMER_OVERFLOW_LSB            2
+#define UMBOX_HCI_FRAMER_OVERFLOW_MASK           0x00000004
+#define UMBOX_HCI_FRAMER_OVERFLOW_GET(x)         (((x) & UMBOX_HCI_FRAMER_OVERFLOW_MASK) >> UMBOX_HCI_FRAMER_OVERFLOW_LSB)
+#define UMBOX_HCI_FRAMER_OVERFLOW_SET(x)         (((x) << UMBOX_HCI_FRAMER_OVERFLOW_LSB) & UMBOX_HCI_FRAMER_OVERFLOW_MASK)
+#define UMBOX_HCI_FRAMER_CONFIG_MODE_MSB         1
+#define UMBOX_HCI_FRAMER_CONFIG_MODE_LSB         0
+#define UMBOX_HCI_FRAMER_CONFIG_MODE_MASK        0x00000003
+#define UMBOX_HCI_FRAMER_CONFIG_MODE_GET(x)      (((x) & UMBOX_HCI_FRAMER_CONFIG_MODE_MASK) >> UMBOX_HCI_FRAMER_CONFIG_MODE_LSB)
+#define UMBOX_HCI_FRAMER_CONFIG_MODE_SET(x)      (((x) << UMBOX_HCI_FRAMER_CONFIG_MODE_LSB) & UMBOX_HCI_FRAMER_CONFIG_MODE_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct umbox_wlan_reg_reg_s {
+  volatile unsigned int umbox_fifo[2];
+  volatile unsigned int umbox_fifo_status;
+  volatile unsigned int umbox_dma_policy;
+  volatile unsigned int umbox0_dma_rx_descriptor_base;
+  volatile unsigned int umbox0_dma_rx_control;
+  volatile unsigned int umbox0_dma_tx_descriptor_base;
+  volatile unsigned int umbox0_dma_tx_control;
+  volatile unsigned int umbox_fifo_timeout;
+  volatile unsigned int umbox_int_status;
+  volatile unsigned int umbox_int_enable;
+  volatile unsigned int umbox_debug;
+  volatile unsigned int umbox_fifo_reset;
+  volatile unsigned int umbox_hci_framer;
+} umbox_wlan_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _UMBOX_WLAN_REG_H_ */
diff --git a/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/vmc_reg.h b/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/vmc_reg.h
new file mode 100644
index 00000000000..c3d8088a555
--- /dev/null
+++ b/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/vmc_reg.h
@@ -0,0 +1,167 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifdef WLAN_HEADERS
+
+#include "vmc_wlan_reg.h"
+
+
+#ifndef BT_HEADERS
+
+#define MC_BCAM_VALID_ADDRESS WLAN_MC_BCAM_VALID_ADDRESS
+#define MC_BCAM_VALID_OFFSET WLAN_MC_BCAM_VALID_OFFSET
+#define MC_BCAM_VALID_BIT_MSB WLAN_MC_BCAM_VALID_BIT_MSB
+#define MC_BCAM_VALID_BIT_LSB WLAN_MC_BCAM_VALID_BIT_LSB
+#define MC_BCAM_VALID_BIT_MASK WLAN_MC_BCAM_VALID_BIT_MASK
+#define MC_BCAM_VALID_BIT_GET(x) WLAN_MC_BCAM_VALID_BIT_GET(x)
+#define MC_BCAM_VALID_BIT_SET(x) WLAN_MC_BCAM_VALID_BIT_SET(x)
+#define MC_BCAM_COMPARE_ADDRESS WLAN_MC_BCAM_COMPARE_ADDRESS
+#define MC_BCAM_COMPARE_OFFSET WLAN_MC_BCAM_COMPARE_OFFSET
+#define MC_BCAM_COMPARE_KEY_MSB WLAN_MC_BCAM_COMPARE_KEY_MSB
+#define MC_BCAM_COMPARE_KEY_LSB WLAN_MC_BCAM_COMPARE_KEY_LSB
+#define MC_BCAM_COMPARE_KEY_MASK WLAN_MC_BCAM_COMPARE_KEY_MASK
+#define MC_BCAM_COMPARE_KEY_GET(x) WLAN_MC_BCAM_COMPARE_KEY_GET(x)
+#define MC_BCAM_COMPARE_KEY_SET(x) WLAN_MC_BCAM_COMPARE_KEY_SET(x)
+#define MC_BCAM_TARGET_ADDRESS WLAN_MC_BCAM_TARGET_ADDRESS
+#define MC_BCAM_TARGET_OFFSET WLAN_MC_BCAM_TARGET_OFFSET
+#define MC_BCAM_TARGET_INST_MSB WLAN_MC_BCAM_TARGET_INST_MSB
+#define MC_BCAM_TARGET_INST_LSB WLAN_MC_BCAM_TARGET_INST_LSB
+#define MC_BCAM_TARGET_INST_MASK WLAN_MC_BCAM_TARGET_INST_MASK
+#define MC_BCAM_TARGET_INST_GET(x) WLAN_MC_BCAM_TARGET_INST_GET(x)
+#define MC_BCAM_TARGET_INST_SET(x) WLAN_MC_BCAM_TARGET_INST_SET(x)
+#define APB_ADDR_ERROR_CONTROL_ADDRESS WLAN_APB_ADDR_ERROR_CONTROL_ADDRESS
+#define APB_ADDR_ERROR_CONTROL_OFFSET WLAN_APB_ADDR_ERROR_CONTROL_OFFSET
+#define APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MSB WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MSB
+#define APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB
+#define APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK
+#define APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_GET(x) WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_GET(x)
+#define APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_SET(x) WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_SET(x)
+#define APB_ADDR_ERROR_CONTROL_ENABLE_MSB WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_MSB
+#define APB_ADDR_ERROR_CONTROL_ENABLE_LSB WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_LSB
+#define APB_ADDR_ERROR_CONTROL_ENABLE_MASK WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_MASK
+#define APB_ADDR_ERROR_CONTROL_ENABLE_GET(x) WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_GET(x)
+#define APB_ADDR_ERROR_CONTROL_ENABLE_SET(x) WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_SET(x)
+#define APB_ADDR_ERROR_STATUS_ADDRESS WLAN_APB_ADDR_ERROR_STATUS_ADDRESS
+#define APB_ADDR_ERROR_STATUS_OFFSET WLAN_APB_ADDR_ERROR_STATUS_OFFSET
+#define APB_ADDR_ERROR_STATUS_WRITE_MSB WLAN_APB_ADDR_ERROR_STATUS_WRITE_MSB
+#define APB_ADDR_ERROR_STATUS_WRITE_LSB WLAN_APB_ADDR_ERROR_STATUS_WRITE_LSB
+#define APB_ADDR_ERROR_STATUS_WRITE_MASK WLAN_APB_ADDR_ERROR_STATUS_WRITE_MASK
+#define APB_ADDR_ERROR_STATUS_WRITE_GET(x) WLAN_APB_ADDR_ERROR_STATUS_WRITE_GET(x)
+#define APB_ADDR_ERROR_STATUS_WRITE_SET(x) WLAN_APB_ADDR_ERROR_STATUS_WRITE_SET(x)
+#define APB_ADDR_ERROR_STATUS_ADDRESS_MSB WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_MSB
+#define APB_ADDR_ERROR_STATUS_ADDRESS_LSB WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_LSB
+#define APB_ADDR_ERROR_STATUS_ADDRESS_MASK WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_MASK
+#define APB_ADDR_ERROR_STATUS_ADDRESS_GET(x) WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_GET(x)
+#define APB_ADDR_ERROR_STATUS_ADDRESS_SET(x) WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_SET(x)
+#define AHB_ADDR_ERROR_CONTROL_ADDRESS WLAN_AHB_ADDR_ERROR_CONTROL_ADDRESS
+#define AHB_ADDR_ERROR_CONTROL_OFFSET WLAN_AHB_ADDR_ERROR_CONTROL_OFFSET
+#define AHB_ADDR_ERROR_CONTROL_ENABLE_MSB WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_MSB
+#define AHB_ADDR_ERROR_CONTROL_ENABLE_LSB WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_LSB
+#define AHB_ADDR_ERROR_CONTROL_ENABLE_MASK WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_MASK
+#define AHB_ADDR_ERROR_CONTROL_ENABLE_GET(x) WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_GET(x)
+#define AHB_ADDR_ERROR_CONTROL_ENABLE_SET(x) WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_SET(x)
+#define AHB_ADDR_ERROR_STATUS_ADDRESS WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS
+#define AHB_ADDR_ERROR_STATUS_OFFSET WLAN_AHB_ADDR_ERROR_STATUS_OFFSET
+#define AHB_ADDR_ERROR_STATUS_MAC_MSB WLAN_AHB_ADDR_ERROR_STATUS_MAC_MSB
+#define AHB_ADDR_ERROR_STATUS_MAC_LSB WLAN_AHB_ADDR_ERROR_STATUS_MAC_LSB
+#define AHB_ADDR_ERROR_STATUS_MAC_MASK WLAN_AHB_ADDR_ERROR_STATUS_MAC_MASK
+#define AHB_ADDR_ERROR_STATUS_MAC_GET(x) WLAN_AHB_ADDR_ERROR_STATUS_MAC_GET(x)
+#define AHB_ADDR_ERROR_STATUS_MAC_SET(x) WLAN_AHB_ADDR_ERROR_STATUS_MAC_SET(x)
+#define AHB_ADDR_ERROR_STATUS_MBOX_MSB WLAN_AHB_ADDR_ERROR_STATUS_MBOX_MSB
+#define AHB_ADDR_ERROR_STATUS_MBOX_LSB WLAN_AHB_ADDR_ERROR_STATUS_MBOX_LSB
+#define AHB_ADDR_ERROR_STATUS_MBOX_MASK WLAN_AHB_ADDR_ERROR_STATUS_MBOX_MASK
+#define AHB_ADDR_ERROR_STATUS_MBOX_GET(x) WLAN_AHB_ADDR_ERROR_STATUS_MBOX_GET(x)
+#define AHB_ADDR_ERROR_STATUS_MBOX_SET(x) WLAN_AHB_ADDR_ERROR_STATUS_MBOX_SET(x)
+#define AHB_ADDR_ERROR_STATUS_ADDRESS_MSB WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_MSB
+#define AHB_ADDR_ERROR_STATUS_ADDRESS_LSB WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_LSB
+#define AHB_ADDR_ERROR_STATUS_ADDRESS_MASK WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_MASK
+#define AHB_ADDR_ERROR_STATUS_ADDRESS_GET(x) WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_GET(x)
+#define AHB_ADDR_ERROR_STATUS_ADDRESS_SET(x) WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_SET(x)
+#define BCAM_CONFLICT_ERROR_ADDRESS WLAN_BCAM_CONFLICT_ERROR_ADDRESS
+#define BCAM_CONFLICT_ERROR_OFFSET WLAN_BCAM_CONFLICT_ERROR_OFFSET
+#define BCAM_CONFLICT_ERROR_IPORT_FLAG_MSB WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_MSB
+#define BCAM_CONFLICT_ERROR_IPORT_FLAG_LSB WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_LSB
+#define BCAM_CONFLICT_ERROR_IPORT_FLAG_MASK WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_MASK
+#define BCAM_CONFLICT_ERROR_IPORT_FLAG_GET(x) WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_GET(x)
+#define BCAM_CONFLICT_ERROR_IPORT_FLAG_SET(x) WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_SET(x)
+#define BCAM_CONFLICT_ERROR_DPORT_FLAG_MSB WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_MSB
+#define BCAM_CONFLICT_ERROR_DPORT_FLAG_LSB WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_LSB
+#define BCAM_CONFLICT_ERROR_DPORT_FLAG_MASK WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_MASK
+#define BCAM_CONFLICT_ERROR_DPORT_FLAG_GET(x) WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_GET(x)
+#define BCAM_CONFLICT_ERROR_DPORT_FLAG_SET(x) WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_SET(x)
+#define CPU_PERF_CNT_ADDRESS WLAN_CPU_PERF_CNT_ADDRESS
+#define CPU_PERF_CNT_OFFSET WLAN_CPU_PERF_CNT_OFFSET
+#define CPU_PERF_CNT_EN_MSB WLAN_CPU_PERF_CNT_EN_MSB
+#define CPU_PERF_CNT_EN_LSB WLAN_CPU_PERF_CNT_EN_LSB
+#define CPU_PERF_CNT_EN_MASK WLAN_CPU_PERF_CNT_EN_MASK
+#define CPU_PERF_CNT_EN_GET(x) WLAN_CPU_PERF_CNT_EN_GET(x)
+#define CPU_PERF_CNT_EN_SET(x) WLAN_CPU_PERF_CNT_EN_SET(x)
+#define CPU_INST_FETCH_ADDRESS WLAN_CPU_INST_FETCH_ADDRESS
+#define CPU_INST_FETCH_OFFSET WLAN_CPU_INST_FETCH_OFFSET
+#define CPU_INST_FETCH_CNT_MSB WLAN_CPU_INST_FETCH_CNT_MSB
+#define CPU_INST_FETCH_CNT_LSB WLAN_CPU_INST_FETCH_CNT_LSB
+#define CPU_INST_FETCH_CNT_MASK WLAN_CPU_INST_FETCH_CNT_MASK
+#define CPU_INST_FETCH_CNT_GET(x) WLAN_CPU_INST_FETCH_CNT_GET(x)
+#define CPU_INST_FETCH_CNT_SET(x) WLAN_CPU_INST_FETCH_CNT_SET(x)
+#define CPU_DATA_FETCH_ADDRESS WLAN_CPU_DATA_FETCH_ADDRESS
+#define CPU_DATA_FETCH_OFFSET WLAN_CPU_DATA_FETCH_OFFSET
+#define CPU_DATA_FETCH_CNT_MSB WLAN_CPU_DATA_FETCH_CNT_MSB
+#define CPU_DATA_FETCH_CNT_LSB WLAN_CPU_DATA_FETCH_CNT_LSB
+#define CPU_DATA_FETCH_CNT_MASK WLAN_CPU_DATA_FETCH_CNT_MASK
+#define CPU_DATA_FETCH_CNT_GET(x) WLAN_CPU_DATA_FETCH_CNT_GET(x)
+#define CPU_DATA_FETCH_CNT_SET(x) WLAN_CPU_DATA_FETCH_CNT_SET(x)
+#define CPU_RAM1_CONFLICT_ADDRESS WLAN_CPU_RAM1_CONFLICT_ADDRESS
+#define CPU_RAM1_CONFLICT_OFFSET WLAN_CPU_RAM1_CONFLICT_OFFSET
+#define CPU_RAM1_CONFLICT_CNT_MSB WLAN_CPU_RAM1_CONFLICT_CNT_MSB
+#define CPU_RAM1_CONFLICT_CNT_LSB WLAN_CPU_RAM1_CONFLICT_CNT_LSB
+#define CPU_RAM1_CONFLICT_CNT_MASK WLAN_CPU_RAM1_CONFLICT_CNT_MASK
+#define CPU_RAM1_CONFLICT_CNT_GET(x) WLAN_CPU_RAM1_CONFLICT_CNT_GET(x)
+#define CPU_RAM1_CONFLICT_CNT_SET(x) WLAN_CPU_RAM1_CONFLICT_CNT_SET(x)
+#define CPU_RAM2_CONFLICT_ADDRESS WLAN_CPU_RAM2_CONFLICT_ADDRESS
+#define CPU_RAM2_CONFLICT_OFFSET WLAN_CPU_RAM2_CONFLICT_OFFSET
+#define CPU_RAM2_CONFLICT_CNT_MSB WLAN_CPU_RAM2_CONFLICT_CNT_MSB
+#define CPU_RAM2_CONFLICT_CNT_LSB WLAN_CPU_RAM2_CONFLICT_CNT_LSB
+#define CPU_RAM2_CONFLICT_CNT_MASK WLAN_CPU_RAM2_CONFLICT_CNT_MASK
+#define CPU_RAM2_CONFLICT_CNT_GET(x) WLAN_CPU_RAM2_CONFLICT_CNT_GET(x)
+#define CPU_RAM2_CONFLICT_CNT_SET(x) WLAN_CPU_RAM2_CONFLICT_CNT_SET(x)
+#define CPU_RAM3_CONFLICT_ADDRESS WLAN_CPU_RAM3_CONFLICT_ADDRESS
+#define CPU_RAM3_CONFLICT_OFFSET WLAN_CPU_RAM3_CONFLICT_OFFSET
+#define CPU_RAM3_CONFLICT_CNT_MSB WLAN_CPU_RAM3_CONFLICT_CNT_MSB
+#define CPU_RAM3_CONFLICT_CNT_LSB WLAN_CPU_RAM3_CONFLICT_CNT_LSB
+#define CPU_RAM3_CONFLICT_CNT_MASK WLAN_CPU_RAM3_CONFLICT_CNT_MASK
+#define CPU_RAM3_CONFLICT_CNT_GET(x) WLAN_CPU_RAM3_CONFLICT_CNT_GET(x)
+#define CPU_RAM3_CONFLICT_CNT_SET(x) WLAN_CPU_RAM3_CONFLICT_CNT_SET(x)
+#define CPU_RAM4_CONFLICT_ADDRESS WLAN_CPU_RAM4_CONFLICT_ADDRESS
+#define CPU_RAM4_CONFLICT_OFFSET WLAN_CPU_RAM4_CONFLICT_OFFSET
+#define CPU_RAM4_CONFLICT_CNT_MSB WLAN_CPU_RAM4_CONFLICT_CNT_MSB
+#define CPU_RAM4_CONFLICT_CNT_LSB WLAN_CPU_RAM4_CONFLICT_CNT_LSB
+#define CPU_RAM4_CONFLICT_CNT_MASK WLAN_CPU_RAM4_CONFLICT_CNT_MASK
+#define CPU_RAM4_CONFLICT_CNT_GET(x) WLAN_CPU_RAM4_CONFLICT_CNT_GET(x)
+#define CPU_RAM4_CONFLICT_CNT_SET(x) WLAN_CPU_RAM4_CONFLICT_CNT_SET(x)
+
+
+#endif
+#endif
+
+
+
diff --git a/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/vmc_wlan_reg.h b/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/vmc_wlan_reg.h
new file mode 100644
index 00000000000..d28de3938b2
--- /dev/null
+++ b/drivers/net/ath6kl/include/common/AR6002/hw4.0/hw/vmc_wlan_reg.h
@@ -0,0 +1,195 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _VMC_WLAN_REG_REG_H_
+#define _VMC_WLAN_REG_REG_H_
+
+#define WLAN_MC_BCAM_VALID_ADDRESS               0x00000000
+#define WLAN_MC_BCAM_VALID_OFFSET                0x00000000
+#define WLAN_MC_BCAM_VALID_BIT_MSB               0
+#define WLAN_MC_BCAM_VALID_BIT_LSB               0
+#define WLAN_MC_BCAM_VALID_BIT_MASK              0x00000001
+#define WLAN_MC_BCAM_VALID_BIT_GET(x)            (((x) & WLAN_MC_BCAM_VALID_BIT_MASK) >> WLAN_MC_BCAM_VALID_BIT_LSB)
+#define WLAN_MC_BCAM_VALID_BIT_SET(x)            (((x) << WLAN_MC_BCAM_VALID_BIT_LSB) & WLAN_MC_BCAM_VALID_BIT_MASK)
+
+#define WLAN_MC_BCAM_COMPARE_ADDRESS             0x00000200
+#define WLAN_MC_BCAM_COMPARE_OFFSET              0x00000200
+#define WLAN_MC_BCAM_COMPARE_KEY_MSB             19
+#define WLAN_MC_BCAM_COMPARE_KEY_LSB             2
+#define WLAN_MC_BCAM_COMPARE_KEY_MASK            0x000ffffc
+#define WLAN_MC_BCAM_COMPARE_KEY_GET(x)          (((x) & WLAN_MC_BCAM_COMPARE_KEY_MASK) >> WLAN_MC_BCAM_COMPARE_KEY_LSB)
+#define WLAN_MC_BCAM_COMPARE_KEY_SET(x)          (((x) << WLAN_MC_BCAM_COMPARE_KEY_LSB) & WLAN_MC_BCAM_COMPARE_KEY_MASK)
+
+#define WLAN_MC_BCAM_TARGET_ADDRESS              0x00000400
+#define WLAN_MC_BCAM_TARGET_OFFSET               0x00000400
+#define WLAN_MC_BCAM_TARGET_INST_MSB             31
+#define WLAN_MC_BCAM_TARGET_INST_LSB             0
+#define WLAN_MC_BCAM_TARGET_INST_MASK            0xffffffff
+#define WLAN_MC_BCAM_TARGET_INST_GET(x)          (((x) & WLAN_MC_BCAM_TARGET_INST_MASK) >> WLAN_MC_BCAM_TARGET_INST_LSB)
+#define WLAN_MC_BCAM_TARGET_INST_SET(x)          (((x) << WLAN_MC_BCAM_TARGET_INST_LSB) & WLAN_MC_BCAM_TARGET_INST_MASK)
+
+#define WLAN_APB_ADDR_ERROR_CONTROL_ADDRESS      0x00000600
+#define WLAN_APB_ADDR_ERROR_CONTROL_OFFSET       0x00000600
+#define WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MSB 1
+#define WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB 1
+#define WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK 0x00000002
+#define WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_GET(x) (((x) & WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK) >> WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB)
+#define WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_SET(x) (((x) << WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB) & WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK)
+#define WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_MSB   0
+#define WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_LSB   0
+#define WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_MASK  0x00000001
+#define WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_GET(x) (((x) & WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_MASK) >> WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_LSB)
+#define WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_SET(x) (((x) << WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_LSB) & WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_MASK)
+
+#define WLAN_APB_ADDR_ERROR_STATUS_ADDRESS       0x00000604
+#define WLAN_APB_ADDR_ERROR_STATUS_OFFSET        0x00000604
+#define WLAN_APB_ADDR_ERROR_STATUS_WRITE_MSB     25
+#define WLAN_APB_ADDR_ERROR_STATUS_WRITE_LSB     25
+#define WLAN_APB_ADDR_ERROR_STATUS_WRITE_MASK    0x02000000
+#define WLAN_APB_ADDR_ERROR_STATUS_WRITE_GET(x)  (((x) & WLAN_APB_ADDR_ERROR_STATUS_WRITE_MASK) >> WLAN_APB_ADDR_ERROR_STATUS_WRITE_LSB)
+#define WLAN_APB_ADDR_ERROR_STATUS_WRITE_SET(x)  (((x) << WLAN_APB_ADDR_ERROR_STATUS_WRITE_LSB) & WLAN_APB_ADDR_ERROR_STATUS_WRITE_MASK)
+#define WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_MSB   24
+#define WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_LSB   0
+#define WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_MASK  0x01ffffff
+#define WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_GET(x) (((x) & WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_MASK) >> WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_LSB)
+#define WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_SET(x) (((x) << WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_LSB) & WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_MASK)
+
+#define WLAN_AHB_ADDR_ERROR_CONTROL_ADDRESS      0x00000608
+#define WLAN_AHB_ADDR_ERROR_CONTROL_OFFSET       0x00000608
+#define WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_MSB   0
+#define WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_LSB   0
+#define WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_MASK  0x00000001
+#define WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_GET(x) (((x) & WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_MASK) >> WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_LSB)
+#define WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_SET(x) (((x) << WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_LSB) & WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_MASK)
+
+#define WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS       0x0000060c
+#define WLAN_AHB_ADDR_ERROR_STATUS_OFFSET        0x0000060c
+#define WLAN_AHB_ADDR_ERROR_STATUS_MAC_MSB       31
+#define WLAN_AHB_ADDR_ERROR_STATUS_MAC_LSB       31
+#define WLAN_AHB_ADDR_ERROR_STATUS_MAC_MASK      0x80000000
+#define WLAN_AHB_ADDR_ERROR_STATUS_MAC_GET(x)    (((x) & WLAN_AHB_ADDR_ERROR_STATUS_MAC_MASK) >> WLAN_AHB_ADDR_ERROR_STATUS_MAC_LSB)
+#define WLAN_AHB_ADDR_ERROR_STATUS_MAC_SET(x)    (((x) << WLAN_AHB_ADDR_ERROR_STATUS_MAC_LSB) & WLAN_AHB_ADDR_ERROR_STATUS_MAC_MASK)
+#define WLAN_AHB_ADDR_ERROR_STATUS_MBOX_MSB      30
+#define WLAN_AHB_ADDR_ERROR_STATUS_MBOX_LSB      30
+#define WLAN_AHB_ADDR_ERROR_STATUS_MBOX_MASK     0x40000000
+#define WLAN_AHB_ADDR_ERROR_STATUS_MBOX_GET(x)   (((x) & WLAN_AHB_ADDR_ERROR_STATUS_MBOX_MASK) >> WLAN_AHB_ADDR_ERROR_STATUS_MBOX_LSB)
+#define WLAN_AHB_ADDR_ERROR_STATUS_MBOX_SET(x)   (((x) << WLAN_AHB_ADDR_ERROR_STATUS_MBOX_LSB) & WLAN_AHB_ADDR_ERROR_STATUS_MBOX_MASK)
+#define WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_MSB   23
+#define WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_LSB   0
+#define WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_MASK  0x00ffffff
+#define WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_GET(x) (((x) & WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_MASK) >> WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_LSB)
+#define WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_SET(x) (((x) << WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_LSB) & WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_MASK)
+
+#define WLAN_BCAM_CONFLICT_ERROR_ADDRESS         0x00000610
+#define WLAN_BCAM_CONFLICT_ERROR_OFFSET          0x00000610
+#define WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_MSB  1
+#define WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_LSB  1
+#define WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_MASK 0x00000002
+#define WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_GET(x) (((x) & WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_MASK) >> WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_LSB)
+#define WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_SET(x) (((x) << WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_LSB) & WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_MASK)
+#define WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_MSB  0
+#define WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_LSB  0
+#define WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_MASK 0x00000001
+#define WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_GET(x) (((x) & WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_MASK) >> WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_LSB)
+#define WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_SET(x) (((x) << WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_LSB) & WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_MASK)
+
+#define WLAN_CPU_PERF_CNT_ADDRESS                0x00000614
+#define WLAN_CPU_PERF_CNT_OFFSET                 0x00000614
+#define WLAN_CPU_PERF_CNT_EN_MSB                 0
+#define WLAN_CPU_PERF_CNT_EN_LSB                 0
+#define WLAN_CPU_PERF_CNT_EN_MASK                0x00000001
+#define WLAN_CPU_PERF_CNT_EN_GET(x)              (((x) & WLAN_CPU_PERF_CNT_EN_MASK) >> WLAN_CPU_PERF_CNT_EN_LSB)
+#define WLAN_CPU_PERF_CNT_EN_SET(x)              (((x) << WLAN_CPU_PERF_CNT_EN_LSB) & WLAN_CPU_PERF_CNT_EN_MASK)
+
+#define WLAN_CPU_INST_FETCH_ADDRESS              0x00000618
+#define WLAN_CPU_INST_FETCH_OFFSET               0x00000618
+#define WLAN_CPU_INST_FETCH_CNT_MSB              31
+#define WLAN_CPU_INST_FETCH_CNT_LSB              0
+#define WLAN_CPU_INST_FETCH_CNT_MASK             0xffffffff
+#define WLAN_CPU_INST_FETCH_CNT_GET(x)           (((x) & WLAN_CPU_INST_FETCH_CNT_MASK) >> WLAN_CPU_INST_FETCH_CNT_LSB)
+#define WLAN_CPU_INST_FETCH_CNT_SET(x)           (((x) << WLAN_CPU_INST_FETCH_CNT_LSB) & WLAN_CPU_INST_FETCH_CNT_MASK)
+
+#define WLAN_CPU_DATA_FETCH_ADDRESS              0x0000061c
+#define WLAN_CPU_DATA_FETCH_OFFSET               0x0000061c
+#define WLAN_CPU_DATA_FETCH_CNT_MSB              31
+#define WLAN_CPU_DATA_FETCH_CNT_LSB              0
+#define WLAN_CPU_DATA_FETCH_CNT_MASK             0xffffffff
+#define WLAN_CPU_DATA_FETCH_CNT_GET(x)           (((x) & WLAN_CPU_DATA_FETCH_CNT_MASK) >> WLAN_CPU_DATA_FETCH_CNT_LSB)
+#define WLAN_CPU_DATA_FETCH_CNT_SET(x)           (((x) << WLAN_CPU_DATA_FETCH_CNT_LSB) & WLAN_CPU_DATA_FETCH_CNT_MASK)
+
+#define WLAN_CPU_RAM1_CONFLICT_ADDRESS           0x00000620
+#define WLAN_CPU_RAM1_CONFLICT_OFFSET            0x00000620
+#define WLAN_CPU_RAM1_CONFLICT_CNT_MSB           11
+#define WLAN_CPU_RAM1_CONFLICT_CNT_LSB           0
+#define WLAN_CPU_RAM1_CONFLICT_CNT_MASK          0x00000fff
+#define WLAN_CPU_RAM1_CONFLICT_CNT_GET(x)        (((x) & WLAN_CPU_RAM1_CONFLICT_CNT_MASK) >> WLAN_CPU_RAM1_CONFLICT_CNT_LSB)
+#define WLAN_CPU_RAM1_CONFLICT_CNT_SET(x)        (((x) << WLAN_CPU_RAM1_CONFLICT_CNT_LSB) & WLAN_CPU_RAM1_CONFLICT_CNT_MASK)
+
+#define WLAN_CPU_RAM2_CONFLICT_ADDRESS           0x00000624
+#define WLAN_CPU_RAM2_CONFLICT_OFFSET            0x00000624
+#define WLAN_CPU_RAM2_CONFLICT_CNT_MSB           11
+#define WLAN_CPU_RAM2_CONFLICT_CNT_LSB           0
+#define WLAN_CPU_RAM2_CONFLICT_CNT_MASK          0x00000fff
+#define WLAN_CPU_RAM2_CONFLICT_CNT_GET(x)        (((x) & WLAN_CPU_RAM2_CONFLICT_CNT_MASK) >> WLAN_CPU_RAM2_CONFLICT_CNT_LSB)
+#define WLAN_CPU_RAM2_CONFLICT_CNT_SET(x)        (((x) << WLAN_CPU_RAM2_CONFLICT_CNT_LSB) & WLAN_CPU_RAM2_CONFLICT_CNT_MASK)
+
+#define WLAN_CPU_RAM3_CONFLICT_ADDRESS           0x00000628
+#define WLAN_CPU_RAM3_CONFLICT_OFFSET            0x00000628
+#define WLAN_CPU_RAM3_CONFLICT_CNT_MSB           11
+#define WLAN_CPU_RAM3_CONFLICT_CNT_LSB           0
+#define WLAN_CPU_RAM3_CONFLICT_CNT_MASK          0x00000fff
+#define WLAN_CPU_RAM3_CONFLICT_CNT_GET(x)        (((x) & WLAN_CPU_RAM3_CONFLICT_CNT_MASK) >> WLAN_CPU_RAM3_CONFLICT_CNT_LSB)
+#define WLAN_CPU_RAM3_CONFLICT_CNT_SET(x)        (((x) << WLAN_CPU_RAM3_CONFLICT_CNT_LSB) & WLAN_CPU_RAM3_CONFLICT_CNT_MASK)
+
+#define WLAN_CPU_RAM4_CONFLICT_ADDRESS           0x0000062c
+#define WLAN_CPU_RAM4_CONFLICT_OFFSET            0x0000062c
+#define WLAN_CPU_RAM4_CONFLICT_CNT_MSB           11
+#define WLAN_CPU_RAM4_CONFLICT_CNT_LSB           0
+#define WLAN_CPU_RAM4_CONFLICT_CNT_MASK          0x00000fff
+#define WLAN_CPU_RAM4_CONFLICT_CNT_GET(x)        (((x) & WLAN_CPU_RAM4_CONFLICT_CNT_MASK) >> WLAN_CPU_RAM4_CONFLICT_CNT_LSB)
+#define WLAN_CPU_RAM4_CONFLICT_CNT_SET(x)        (((x) << WLAN_CPU_RAM4_CONFLICT_CNT_LSB) & WLAN_CPU_RAM4_CONFLICT_CNT_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct vmc_wlan_reg_reg_s {
+  volatile unsigned int wlan_mc_bcam_valid[128];
+  volatile unsigned int wlan_mc_bcam_compare[128];
+  volatile unsigned int wlan_mc_bcam_target[128];
+  volatile unsigned int wlan_apb_addr_error_control;
+  volatile unsigned int wlan_apb_addr_error_status;
+  volatile unsigned int wlan_ahb_addr_error_control;
+  volatile unsigned int wlan_ahb_addr_error_status;
+  volatile unsigned int wlan_bcam_conflict_error;
+  volatile unsigned int wlan_cpu_perf_cnt;
+  volatile unsigned int wlan_cpu_inst_fetch;
+  volatile unsigned int wlan_cpu_data_fetch;
+  volatile unsigned int wlan_cpu_ram1_conflict;
+  volatile unsigned int wlan_cpu_ram2_conflict;
+  volatile unsigned int wlan_cpu_ram3_conflict;
+  volatile unsigned int wlan_cpu_ram4_conflict;
+} vmc_wlan_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _VMC_WLAN_REG_H_ */
diff --git a/drivers/net/ath6kl/include/common/a_hci.h b/drivers/net/ath6kl/include/common/a_hci.h
new file mode 100644
index 00000000000..f2943466339
--- /dev/null
+++ b/drivers/net/ath6kl/include/common/a_hci.h
@@ -0,0 +1,682 @@
+//-
+// Copyright (c) 2009-2010 Atheros Communications Inc.
+// All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//
+//
+
+
+#ifndef __A_HCI_H__
+#define __A_HCI_H__
+
+#define HCI_CMD_OGF_MASK            0x3F
+#define HCI_CMD_OGF_SHIFT           10
+#define HCI_CMD_GET_OGF(opcode)     ((opcode >> HCI_CMD_OGF_SHIFT) & HCI_CMD_OGF_MASK)
+
+#define HCI_CMD_OCF_MASK            0x3FF
+#define HCI_CMD_OCF_SHIFT           0 
+#define HCI_CMD_GET_OCF(opcode)     (((opcode) >> HCI_CMD_OCF_SHIFT) & HCI_CMD_OCF_MASK)
+
+#define HCI_FORM_OPCODE(ocf, ogf)    ((ocf & HCI_CMD_OCF_MASK) << HCI_CMD_OCF_SHIFT | \
+                                          (ogf & HCI_CMD_OGF_MASK) << HCI_CMD_OGF_SHIFT)
+
+
+/*======== HCI Opcode groups ===============*/
+#define OGF_NOP                         0x00
+#define OGF_LINK_CONTROL                0x01
+#define OGF_LINK_POLICY                 0x03
+#define OGF_INFO_PARAMS                 0x04
+#define OGF_STATUS                      0x05
+#define OGF_TESTING                     0x06
+#define OGF_BLUETOOTH                   0x3E
+#define OGF_VENDOR_DEBUG                0x3F
+
+
+
+#define OCF_NOP                         0x00
+
+
+/*===== Link Control Commands Opcode===================*/
+#define OCF_HCI_Create_Physical_Link                0x35
+#define OCF_HCI_Accept_Physical_Link_Req            0x36
+#define OCF_HCI_Disconnect_Physical_Link            0x37
+#define OCF_HCI_Create_Logical_Link                 0x38
+#define OCF_HCI_Accept_Logical_Link                 0x39
+#define OCF_HCI_Disconnect_Logical_Link             0x3A
+#define OCF_HCI_Logical_Link_Cancel                 0x3B
+#define OCF_HCI_Flow_Spec_Modify                    0x3C
+
+
+
+/*===== Link Policy Commands Opcode====================*/
+#define OCF_HCI_Set_Event_Mask                      0x01
+#define OCF_HCI_Reset                               0x03
+#define OCF_HCI_Read_Conn_Accept_Timeout            0x15
+#define OCF_HCI_Write_Conn_Accept_Timeout           0x16
+#define OCF_HCI_Read_Link_Supervision_Timeout       0x36
+#define OCF_HCI_Write_Link_Supervision_Timeout      0x37
+#define OCF_HCI_Enhanced_Flush                      0x5F
+#define OCF_HCI_Read_Logical_Link_Accept_Timeout    0x61
+#define OCF_HCI_Write_Logical_Link_Accept_Timeout   0x62
+#define OCF_HCI_Set_Event_Mask_Page_2               0x63
+#define OCF_HCI_Read_Location_Data                  0x64
+#define OCF_HCI_Write_Location_Data                 0x65
+#define OCF_HCI_Read_Flow_Control_Mode              0x66
+#define OCF_HCI_Write_Flow_Control_Mode             0x67
+#define OCF_HCI_Read_BE_Flush_Timeout               0x69
+#define OCF_HCI_Write_BE_Flush_Timeout              0x6A
+#define OCF_HCI_Short_Range_Mode                    0x6B
+
+
+/*======== Info Commands Opcode========================*/
+#define OCF_HCI_Read_Local_Ver_Info                 0x01
+#define OCF_HCI_Read_Local_Supported_Cmds           0x02
+#define OCF_HCI_Read_Data_Block_Size                0x0A
+/*======== Status Commands Opcode======================*/
+#define OCF_HCI_Read_Failed_Contact_Counter         0x01
+#define OCF_HCI_Reset_Failed_Contact_Counter        0x02
+#define OCF_HCI_Read_Link_Quality                   0x03
+#define OCF_HCI_Read_RSSI                           0x05
+#define OCF_HCI_Read_Local_AMP_Info                 0x09    
+#define OCF_HCI_Read_Local_AMP_ASSOC                0x0A
+#define OCF_HCI_Write_Remote_AMP_ASSOC              0x0B
+
+
+/*======= AMP_ASSOC Specific TLV tags =================*/
+#define AMP_ASSOC_MAC_ADDRESS_INFO_TYPE             0x1
+#define AMP_ASSOC_PREF_CHAN_LIST                    0x2
+#define AMP_ASSOC_CONNECTED_CHAN                    0x3
+#define AMP_ASSOC_PAL_CAPABILITIES                  0x4
+#define AMP_ASSOC_PAL_VERSION                       0x5
+
+
+/*========= PAL Events =================================*/
+#define PAL_COMMAND_COMPLETE_EVENT                  0x0E
+#define PAL_COMMAND_STATUS_EVENT                    0x0F
+#define PAL_HARDWARE_ERROR_EVENT                    0x10
+#define PAL_FLUSH_OCCURRED_EVENT                    0x11
+#define PAL_LOOPBACK_EVENT                          0x19
+#define PAL_BUFFER_OVERFLOW_EVENT                   0x1A
+#define PAL_QOS_VIOLATION_EVENT                     0x1E
+#define PAL_ENHANCED_FLUSH_COMPLT_EVENT             0x39
+#define PAL_PHYSICAL_LINK_COMPL_EVENT               0x40
+#define PAL_CHANNEL_SELECT_EVENT                    0x41
+#define PAL_DISCONNECT_PHYSICAL_LINK_EVENT          0x42
+#define PAL_PHY_LINK_EARLY_LOSS_WARNING_EVENT       0x43
+#define PAL_PHY_LINK_RECOVERY_EVENT                 0x44
+#define PAL_LOGICAL_LINK_COMPL_EVENT                0x45
+#define PAL_DISCONNECT_LOGICAL_LINK_COMPL_EVENT     0x46
+#define PAL_FLOW_SPEC_MODIFY_COMPL_EVENT            0x47
+#define PAL_NUM_COMPL_DATA_BLOCK_EVENT              0x48
+#define PAL_SHORT_RANGE_MODE_CHANGE_COMPL_EVENT     0x4C
+#define PAL_AMP_STATUS_CHANGE_EVENT                 0x4D
+/*======== End of PAL events definiton =================*/
+
+
+/*======== Timeouts (not part of HCI cmd, but input to PAL engine) =========*/
+#define Timer_Conn_Accept_TO                        0x01
+#define Timer_Link_Supervision_TO                   0x02
+
+#define NUM_HCI_COMMAND_PKTS                0x1
+
+
+/*====== NOP Cmd ============================*/
+#define HCI_CMD_NOP                     HCI_FORM_OPCODE(OCF_NOP, OGF_NOP)
+
+
+/*===== Link Control Commands================*/
+#define HCI_Create_Physical_Link        HCI_FORM_OPCODE(OCF_HCI_Create_Physical_Link, OGF_LINK_CONTROL)
+#define HCI_Accept_Physical_Link_Req    HCI_FORM_OPCODE(OCF_HCI_Accept_Physical_Link_Req, OGF_LINK_CONTROL)
+#define HCI_Disconnect_Physical_Link    HCI_FORM_OPCODE(OCF_HCI_Disconnect_Physical_Link, OGF_LINK_CONTROL)
+#define HCI_Create_Logical_Link         HCI_FORM_OPCODE(OCF_HCI_Create_Logical_Link, OGF_LINK_CONTROL)
+#define HCI_Accept_Logical_Link         HCI_FORM_OPCODE(OCF_HCI_Accept_Logical_Link, OGF_LINK_CONTROL)
+#define HCI_Disconnect_Logical_Link     HCI_FORM_OPCODE(OCF_HCI_Disconnect_Logical_Link, OGF_LINK_CONTROL)
+#define HCI_Logical_Link_Cancel         HCI_FORM_OPCODE(OCF_HCI_Logical_Link_Cancel, OGF_LINK_CONTROL)
+#define HCI_Flow_Spec_Modify            HCI_FORM_OPCODE(OCF_HCI_Flow_Spec_Modify, OGF_LINK_CONTROL)
+
+
+/*===== Link Policy Commands ================*/
+#define HCI_Set_Event_Mask              HCI_FORM_OPCODE(OCF_HCI_Set_Event_Mask, OGF_LINK_POLICY)
+#define HCI_Reset                       HCI_FORM_OPCODE(OCF_HCI_Reset, OGF_LINK_POLICY)
+#define HCI_Enhanced_Flush              HCI_FORM_OPCODE(OCF_HCI_Enhanced_Flush, OGF_LINK_POLICY)
+#define HCI_Read_Conn_Accept_Timeout    HCI_FORM_OPCODE(OCF_HCI_Read_Conn_Accept_Timeout, OGF_LINK_POLICY)
+#define HCI_Write_Conn_Accept_Timeout   HCI_FORM_OPCODE(OCF_HCI_Write_Conn_Accept_Timeout, OGF_LINK_POLICY)
+#define HCI_Read_Logical_Link_Accept_Timeout    HCI_FORM_OPCODE(OCF_HCI_Read_Logical_Link_Accept_Timeout, OGF_LINK_POLICY)
+#define HCI_Write_Logical_Link_Accept_Timeout   HCI_FORM_OPCODE(OCF_HCI_Write_Logical_Link_Accept_Timeout, OGF_LINK_POLICY)
+#define HCI_Read_Link_Supervision_Timeout       HCI_FORM_OPCODE(OCF_HCI_Read_Link_Supervision_Timeout, OGF_LINK_POLICY)
+#define HCI_Write_Link_Supervision_Timeout      HCI_FORM_OPCODE(OCF_HCI_Write_Link_Supervision_Timeout, OGF_LINK_POLICY)
+#define HCI_Read_Location_Data          HCI_FORM_OPCODE(OCF_HCI_Read_Location_Data, OGF_LINK_POLICY)
+#define HCI_Write_Location_Data         HCI_FORM_OPCODE(OCF_HCI_Write_Location_Data, OGF_LINK_POLICY)
+#define HCI_Set_Event_Mask_Page_2       HCI_FORM_OPCODE(OCF_HCI_Set_Event_Mask_Page_2, OGF_LINK_POLICY)
+#define HCI_Read_Flow_Control_Mode      HCI_FORM_OPCODE(OCF_HCI_Read_Flow_Control_Mode, OGF_LINK_POLICY)
+#define HCI_Write_Flow_Control_Mode     HCI_FORM_OPCODE(OCF_HCI_Write_Flow_Control_Mode, OGF_LINK_POLICY)
+#define HCI_Write_BE_Flush_Timeout      HCI_FORM_OPCODE(OCF_HCI_Write_BE_Flush_Timeout, OGF_LINK_POLICY)
+#define HCI_Read_BE_Flush_Timeout       HCI_FORM_OPCODE(OCF_HCI_Read_BE_Flush_Timeout, OGF_LINK_POLICY)
+#define HCI_Short_Range_Mode            HCI_FORM_OPCODE(OCF_HCI_Short_Range_Mode, OGF_LINK_POLICY)            
+
+
+/*===== Info Commands =====================*/
+#define HCI_Read_Local_Ver_Info         HCI_FORM_OPCODE(OCF_HCI_Read_Local_Ver_Info,  OGF_INFO_PARAMS)
+#define HCI_Read_Local_Supported_Cmds   HCI_FORM_OPCODE(OCF_HCI_Read_Local_Supported_Cmds, OGF_INFO_PARAMS)
+#define HCI_Read_Data_Block_Size        HCI_FORM_OPCODE(OCF_HCI_Read_Data_Block_Size, OGF_INFO_PARAMS)
+
+/*===== Status Commands =====================*/
+#define HCI_Read_Link_Quality           HCI_FORM_OPCODE(OCF_HCI_Read_Link_Quality, OGF_STATUS)
+#define HCI_Read_RSSI                   HCI_FORM_OPCODE(OCF_HCI_Read_RSSI, OGF_STATUS)
+#define HCI_Read_Local_AMP_Info         HCI_FORM_OPCODE(OCF_HCI_Read_Local_AMP_Info, OGF_STATUS)
+#define HCI_Read_Local_AMP_ASSOC        HCI_FORM_OPCODE(OCF_HCI_Read_Local_AMP_ASSOC, OGF_STATUS)
+#define HCI_Write_Remote_AMP_ASSOC      HCI_FORM_OPCODE(OCF_HCI_Write_Remote_AMP_ASSOC, OGF_STATUS)
+
+/*====== End of cmd definitions =============*/
+
+
+
+/*===== Timeouts(private - can't come from HCI)=================*/
+#define Conn_Accept_TO                  HCI_FORM_OPCODE(Timer_Conn_Accept_TO, OGF_VENDOR_DEBUG)
+#define Link_Supervision_TO             HCI_FORM_OPCODE(Timer_Link_Supervision_TO, OGF_VENDOR_DEBUG)
+
+/*----- PAL Constants (Sec 6 of Doc)------------------------*/
+#define Max80211_PAL_PDU_Size      1492
+#define Max80211_AMP_ASSOC_Len      672
+#define MinGUserPrio                4
+#define MaxGUserPrio                7
+#define BEUserPrio0                 0
+#define BEUserPrio1                 3
+#define Max80211BeaconPeriod        2000    /* in millisec */
+#define ShortRangeModePowerMax      4       /* dBm */
+
+/*------ PAL Protocol Identifiers (Sec5.1) ------------------*/
+typedef enum {
+    ACL_DATA = 0x01,
+    ACTIVITY_REPORT,
+    SECURED_FRAMES,
+    LINK_SUPERVISION_REQ,
+    LINK_SUPERVISION_RESP,
+}PAL_PROTOCOL_IDENTIFIERS;
+
+#define HCI_CMD_HDR_SZ          3
+#define HCI_EVENT_HDR_SIZE      2
+#define MAX_EVT_PKT_SZ          255
+#define AMP_ASSOC_MAX_FRAG_SZ   248
+#define AMP_MAX_GUARANTEED_BW   20000
+
+#define DEFAULT_CONN_ACCPT_TO   5000
+#define DEFAULT_LL_ACCPT_TO     5000
+#define DEFAULT_LSTO            10000
+
+#define PACKET_BASED_FLOW_CONTROL_MODE      0x00
+#define DATA_BLK_BASED_FLOW_CONTROL_MODE    0x01
+
+#define SERVICE_TYPE_BEST_EFFORT    0x01
+#define SERVICE_TYPE_GUARANTEED     0x02
+
+#define MAC_ADDR_LEN            6
+#define LINK_KEY_LEN            32
+
+typedef enum  {
+    ACL_DATA_PB_1ST_NON_AUTOMATICALLY_FLUSHABLE = 0x00,
+    ACL_DATA_PB_CONTINUING_FRAGMENT = 0x01,
+    ACL_DATA_PB_1ST_AUTOMATICALLY_FLUSHABLE = 0x02,
+    ACL_DATA_PB_COMPLETE_PDU = 0x03,
+} ACL_DATA_PB_FLAGS;
+#define ACL_DATA_PB_FLAGS_SHIFT     12
+
+typedef enum {
+    ACL_DATA_BC_POINT_TO_POINT = 0x00,
+} ACL_DATA_BC_FLAGS;
+#define ACL_DATA_BC_FLAGS_SHIFT     14
+
+/* Command pkt */
+typedef struct  hci_cmd_pkt_t {
+    A_UINT16    opcode;
+    A_UINT8     param_length;
+    A_UINT8     params[255];
+} POSTPACK HCI_CMD_PKT;
+
+#define ACL_DATA_HDR_SIZE   4   /* hdl_and flags + data_len */
+/* Data pkt */
+typedef struct  hci_acl_data_pkt_t {
+    A_UINT16    hdl_and_flags;
+    A_UINT16    data_len;
+    A_UINT8     data[Max80211_PAL_PDU_Size];
+} POSTPACK HCI_ACL_DATA_PKT;
+
+/* Event pkt */
+typedef struct  hci_event_pkt_t {
+    A_UINT8     event_code;
+    A_UINT8     param_len;
+    A_UINT8     params[256];
+} POSTPACK HCI_EVENT_PKT;
+
+
+/*============== HCI Command definitions ======================= */
+typedef struct hci_cmd_phy_link_t {
+    A_UINT16    opcode;
+    A_UINT8     param_length;
+    A_UINT8     phy_link_hdl;
+    A_UINT8     link_key_len;
+    A_UINT8     link_key_type;
+    A_UINT8     link_key[LINK_KEY_LEN];
+} POSTPACK HCI_CMD_PHY_LINK;
+
+typedef struct  hci_cmd_write_rem_amp_assoc_t {
+    A_UINT16    opcode;
+    A_UINT8     param_length;
+    A_UINT8     phy_link_hdl;
+    A_UINT16    len_so_far;
+    A_UINT16    amp_assoc_remaining_len;
+    A_UINT8     amp_assoc_frag[AMP_ASSOC_MAX_FRAG_SZ];
+} POSTPACK HCI_CMD_WRITE_REM_AMP_ASSOC;
+
+
+typedef struct  hci_cmd_opcode_hdl_t {
+    A_UINT16    opcode;
+    A_UINT8     param_length;
+    A_UINT16    hdl;
+} POSTPACK HCI_CMD_READ_LINK_QUAL,
+           HCI_CMD_FLUSH,
+           HCI_CMD_READ_LINK_SUPERVISION_TIMEOUT;
+
+typedef struct  hci_cmd_read_local_amp_assoc_t {
+    A_UINT16    opcode;
+    A_UINT8     param_length;
+    A_UINT8     phy_link_hdl;
+    A_UINT16    len_so_far;
+    A_UINT16    max_rem_amp_assoc_len;
+} POSTPACK HCI_CMD_READ_LOCAL_AMP_ASSOC;
+
+
+typedef struct hci_cmd_set_event_mask_t {
+    A_UINT16    opcode;
+    A_UINT8     param_length;
+    A_UINT64    mask;
+}POSTPACK HCI_CMD_SET_EVT_MASK, HCI_CMD_SET_EVT_MASK_PG_2;
+
+
+typedef struct  hci_cmd_enhanced_flush_t{
+    A_UINT16    opcode;
+    A_UINT8     param_length;
+    A_UINT16    hdl;
+    A_UINT8     type;
+} POSTPACK HCI_CMD_ENHANCED_FLUSH;
+
+
+typedef struct  hci_cmd_write_timeout_t {
+    A_UINT16    opcode;
+    A_UINT8     param_length;
+    A_UINT16    timeout;
+} POSTPACK  HCI_CMD_WRITE_TIMEOUT;
+
+typedef struct  hci_cmd_write_link_supervision_timeout_t {
+    A_UINT16    opcode;
+    A_UINT8     param_length;
+    A_UINT16    hdl;
+    A_UINT16    timeout;
+} POSTPACK HCI_CMD_WRITE_LINK_SUPERVISION_TIMEOUT;
+
+typedef struct  hci_cmd_write_flow_control_t {
+    A_UINT16    opcode;
+    A_UINT8     param_length;
+    A_UINT8     mode;
+} POSTPACK  HCI_CMD_WRITE_FLOW_CONTROL;
+
+typedef struct  location_data_cfg_t {
+    A_UINT8     reg_domain_aware;
+    A_UINT8     reg_domain[3];
+    A_UINT8     reg_options;
+} POSTPACK LOCATION_DATA_CFG;
+
+typedef struct  hci_cmd_write_location_data_t {
+    A_UINT16    opcode;
+    A_UINT8     param_length;
+    LOCATION_DATA_CFG   cfg;
+} POSTPACK  HCI_CMD_WRITE_LOCATION_DATA;
+
+
+typedef struct  flow_spec_t {
+    A_UINT8     id;
+    A_UINT8     service_type;
+    A_UINT16    max_sdu;
+    A_UINT32    sdu_inter_arrival_time;
+    A_UINT32    access_latency;
+    A_UINT32    flush_timeout;
+} POSTPACK FLOW_SPEC;
+
+
+typedef struct  hci_cmd_create_logical_link_t {
+    A_UINT16    opcode;
+    A_UINT8     param_length;
+    A_UINT8     phy_link_hdl;
+    FLOW_SPEC   tx_flow_spec;
+    FLOW_SPEC   rx_flow_spec;
+} POSTPACK HCI_CMD_CREATE_LOGICAL_LINK;
+
+typedef struct  hci_cmd_flow_spec_modify_t {
+    A_UINT16    opcode;
+    A_UINT8     param_length;
+    A_UINT16    hdl;
+    FLOW_SPEC   tx_flow_spec;
+    FLOW_SPEC   rx_flow_spec;
+} POSTPACK HCI_CMD_FLOW_SPEC_MODIFY;
+
+typedef struct hci_cmd_logical_link_cancel_t {
+    A_UINT16    opcode;
+    A_UINT8     param_length;
+    A_UINT8     phy_link_hdl;
+    A_UINT8     tx_flow_spec_id;
+} POSTPACK HCI_CMD_LOGICAL_LINK_CANCEL;
+
+typedef struct  hci_cmd_disconnect_logical_link_t {
+    A_UINT16    opcode;
+    A_UINT8     param_length;
+    A_UINT16    logical_link_hdl;
+} POSTPACK HCI_CMD_DISCONNECT_LOGICAL_LINK;
+
+typedef struct  hci_cmd_disconnect_phy_link_t {
+    A_UINT16    opcode;
+    A_UINT8     param_length;
+    A_UINT8     phy_link_hdl;
+} POSTPACK HCI_CMD_DISCONNECT_PHY_LINK;
+
+typedef struct  hci_cmd_srm_t {
+    A_UINT16    opcode;
+    A_UINT8     param_length;
+    A_UINT8     phy_link_hdl;
+    A_UINT8     mode;
+} POSTPACK HCI_CMD_SHORT_RANGE_MODE;
+/*============== HCI Command definitions end ======================= */
+
+
+
+/*============== HCI Event definitions ============================= */
+
+/* Command complete event */
+typedef struct  hci_event_cmd_complete_t {
+    A_UINT8     event_code;
+    A_UINT8     param_len;
+    A_UINT8     num_hci_cmd_pkts;
+    A_UINT16    opcode;
+    A_UINT8     params[255];
+} POSTPACK HCI_EVENT_CMD_COMPLETE;
+
+
+/* Command status event */
+typedef struct  hci_event_cmd_status_t {
+    A_UINT8     event_code;
+    A_UINT8     param_len;
+    A_UINT8     status;
+    A_UINT8     num_hci_cmd_pkts;
+    A_UINT16    opcode;
+} POSTPACK HCI_EVENT_CMD_STATUS;
+
+/* Hardware Error event */
+typedef struct  hci_event_hw_err_t {
+    A_UINT8     event_code;
+    A_UINT8     param_len;
+    A_UINT8     hw_err_code;
+} POSTPACK HCI_EVENT_HW_ERR;
+
+/* Flush occured event */
+/* Qos Violation event */
+typedef struct  hci_event_handle_t {
+    A_UINT8     event_code;
+    A_UINT8     param_len;
+    A_UINT16    handle;
+} POSTPACK HCI_EVENT_FLUSH_OCCRD,
+           HCI_EVENT_QOS_VIOLATION;
+
+/* Loopback command event */
+typedef struct hci_loopback_cmd_t {
+    A_UINT8     event_code;
+    A_UINT8     param_len;
+    A_UINT8     params[252];
+} POSTPACK HCI_EVENT_LOOPBACK_CMD;
+
+/* Data buffer overflow event */
+typedef struct  hci_data_buf_overflow_t {
+    A_UINT8     event_code;
+    A_UINT8     param_len;
+    A_UINT8     link_type;
+} POSTPACK  HCI_EVENT_DATA_BUF_OVERFLOW;
+
+/* Enhanced Flush complete event */
+typedef struct hci_enhanced_flush_complt_t{
+    A_UINT8     event_code;
+    A_UINT8     param_len;
+    A_UINT16    hdl;
+} POSTPACK  HCI_EVENT_ENHANCED_FLUSH_COMPLT;
+
+/* Channel select event */
+typedef struct  hci_event_chan_select_t {
+    A_UINT8     event_code;
+    A_UINT8     param_len;
+    A_UINT8     phy_link_hdl;
+} POSTPACK HCI_EVENT_CHAN_SELECT;
+
+/* Physical Link Complete event */
+typedef struct  hci_event_phy_link_complete_event_t {
+    A_UINT8     event_code;
+    A_UINT8     param_len;
+    A_UINT8     status;
+    A_UINT8     phy_link_hdl;
+} POSTPACK HCI_EVENT_PHY_LINK_COMPLETE;
+
+/* Logical Link complete event */
+typedef struct hci_event_logical_link_complete_event_t {
+    A_UINT8     event_code;
+    A_UINT8     param_len;
+    A_UINT8     status;
+    A_UINT16    logical_link_hdl;
+    A_UINT8     phy_hdl;
+    A_UINT8     tx_flow_id;
+} POSTPACK HCI_EVENT_LOGICAL_LINK_COMPLETE_EVENT;
+
+/* Disconnect Logical Link complete event */
+typedef struct hci_event_disconnect_logical_link_event_t {
+    A_UINT8     event_code;
+    A_UINT8     param_len;
+    A_UINT8     status;
+    A_UINT16    logical_link_hdl;
+    A_UINT8     reason;
+} POSTPACK HCI_EVENT_DISCONNECT_LOGICAL_LINK_EVENT;
+
+/* Disconnect Physical Link complete event */
+typedef struct hci_event_disconnect_phy_link_complete_t {
+    A_UINT8     event_code;
+    A_UINT8     param_len;
+    A_UINT8     status;
+    A_UINT8     phy_link_hdl;
+    A_UINT8     reason;
+} POSTPACK HCI_EVENT_DISCONNECT_PHY_LINK_COMPLETE;
+
+typedef struct hci_event_physical_link_loss_early_warning_t{
+    A_UINT8     event_code;
+    A_UINT8     param_len;
+    A_UINT8     phy_hdl;
+    A_UINT8     reason;
+} POSTPACK HCI_EVENT_PHY_LINK_LOSS_EARLY_WARNING;
+
+typedef struct hci_event_physical_link_recovery_t{
+    A_UINT8     event_code;
+    A_UINT8     param_len;
+    A_UINT8     phy_hdl;
+} POSTPACK HCI_EVENT_PHY_LINK_RECOVERY;
+
+
+/* Flow spec modify complete event */
+/* Flush event */
+typedef struct hci_event_status_handle_t {
+    A_UINT8     event_code;
+    A_UINT8     param_len;
+    A_UINT8     status;
+    A_UINT16    handle;
+} POSTPACK HCI_EVENT_FLOW_SPEC_MODIFY,
+           HCI_EVENT_FLUSH;
+
+
+/* Num of completed data blocks event */
+typedef struct hci_event_num_of_compl_data_blks_t {
+    A_UINT8     event_code;
+    A_UINT8     param_len;
+    A_UINT16    num_data_blks;
+    A_UINT8     num_handles;
+    A_UINT8     params[255];
+} POSTPACK HCI_EVENT_NUM_COMPL_DATA_BLKS;
+
+/* Short range mode change complete event */
+typedef struct  hci_srm_cmpl_t {
+    A_UINT8     event_code;
+    A_UINT8     param_len;
+    A_UINT8     status;
+    A_UINT8     phy_link;
+    A_UINT8     state;
+} POSTPACK HCI_EVENT_SRM_COMPL;
+
+typedef struct hci_event_amp_status_change_t{
+    A_UINT8     event_code;
+    A_UINT8     param_len;
+    A_UINT8     status;
+    A_UINT8     amp_status;
+} POSTPACK HCI_EVENT_AMP_STATUS_CHANGE;
+
+/*============== Event definitions end =========================== */
+
+
+typedef struct  local_amp_info_resp_t {
+    A_UINT8     status;
+    A_UINT8     amp_status;
+    A_UINT32    total_bw;           /* kbps */
+    A_UINT32    max_guranteed_bw;   /* kbps */
+    A_UINT32    min_latency;
+    A_UINT32    max_pdu_size;
+    A_UINT8     amp_type;
+    A_UINT16    pal_capabilities;
+    A_UINT16    amp_assoc_len;
+    A_UINT32    max_flush_timeout;  /* in ms */
+    A_UINT32    be_flush_timeout;   /* in ms */
+} POSTPACK  LOCAL_AMP_INFO;
+
+typedef struct  amp_assoc_cmd_resp_t{
+    A_UINT8     status;
+    A_UINT8     phy_hdl;
+    A_UINT16    amp_assoc_len;
+    A_UINT8     amp_assoc_frag[AMP_ASSOC_MAX_FRAG_SZ];
+}POSTPACK AMP_ASSOC_CMD_RESP;
+
+
+enum PAL_HCI_CMD_STATUS {
+    PAL_HCI_CMD_PROCESSED,
+    PAL_HCI_CMD_IGNORED
+}; 
+
+
+/*============= HCI Error Codes =======================*/
+#define HCI_SUCCESS                             0x00
+#define HCI_ERR_UNKNOW_CMD                      0x01
+#define HCI_ERR_UNKNOWN_CONN_ID                 0x02
+#define HCI_ERR_HW_FAILURE                      0x03
+#define HCI_ERR_PAGE_TIMEOUT                    0x04
+#define HCI_ERR_AUTH_FAILURE                    0x05
+#define HCI_ERR_KEY_MISSING                     0x06
+#define HCI_ERR_MEM_CAP_EXECED                  0x07
+#define HCI_ERR_CON_TIMEOUT                     0x08
+#define HCI_ERR_CON_LIMIT_EXECED                0x09
+#define	HCI_ERR_ACL_CONN_ALRDY_EXISTS	        0x0B
+#define	HCI_ERR_COMMAND_DISALLOWED		        0x0C
+#define HCI_ERR_CONN_REJ_BY_LIMIT_RES           0x0D
+#define HCI_ERR_CONN_REJ_BY_SEC                 0x0E
+#define HCI_ERR_CONN_REJ_BY_BAD_ADDR            0x0F
+#define HCI_ERR_CONN_ACCPT_TIMEOUT              0x10
+#define HCI_ERR_UNSUPPORT_FEATURE               0x11
+#define HCI_ERR_INVALID_HCI_CMD_PARAMS          0x12
+#define HCI_ERR_REMOTE_USER_TERMINATE_CONN      0x13
+#define HCI_ERR_CON_TERM_BY_HOST                0x16
+#define HCI_ERR_UNSPECIFIED_ERROR               0x1F
+#define HCI_ERR_ENCRYPTION_MODE_NOT_SUPPORT     0x25
+#define HCI_ERR_REQUESTED_QOS_NOT_SUPPORT       0x27
+#define HCI_ERR_QOS_UNACCEPTABLE_PARM           0x2C
+#define HCI_ERR_QOS_REJECTED                    0x2D
+#define HCI_ERR_CONN_REJ_NO_SUITABLE_CHAN       0x39
+
+/*============= HCI Error Codes End =======================*/
+
+
+/* Following are event return parameters.. part of HCI events 
+ */
+typedef struct  timeout_read_t {
+    A_UINT8     status;
+    A_UINT16    timeout;
+}POSTPACK TIMEOUT_INFO;
+
+typedef struct  link_supervision_timeout_read_t {
+    A_UINT8     status;
+    A_UINT16    hdl;
+    A_UINT16    timeout;
+}POSTPACK LINK_SUPERVISION_TIMEOUT_INFO;
+
+typedef struct  status_hdl_t {
+    A_UINT8     status;
+    A_UINT16    hdl;
+}POSTPACK INFO_STATUS_HDL;
+
+typedef struct write_remote_amp_assoc_t{
+    A_UINT8     status;
+    A_UINT8     hdl;
+}POSTPACK WRITE_REMOTE_AMP_ASSOC_INFO;
+
+typedef struct  read_loc_info_t {
+    A_UINT8             status;
+    LOCATION_DATA_CFG   loc;
+}POSTPACK READ_LOC_INFO;
+
+typedef struct  read_flow_ctrl_mode_t {
+    A_UINT8     status;
+    A_UINT8     mode;
+}POSTPACK READ_FLWCTRL_INFO;
+
+typedef struct  read_data_blk_size_t {
+    A_UINT8     status;
+    A_UINT16    max_acl_data_pkt_len;
+    A_UINT16    data_block_len;
+    A_UINT16    total_num_data_blks;
+}POSTPACK READ_DATA_BLK_SIZE_INFO;
+
+/* Read Link quality info */
+typedef struct link_qual_t {
+    A_UINT8     status;
+    A_UINT16    hdl;
+    A_UINT8     link_qual;
+} POSTPACK READ_LINK_QUAL_INFO,
+            READ_RSSI_INFO;
+
+typedef struct ll_cancel_resp_t {
+    A_UINT8 status;
+    A_UINT8 phy_link_hdl;
+    A_UINT8 tx_flow_spec_id;
+} POSTPACK LL_CANCEL_RESP;
+
+typedef struct read_local_ver_info_t {
+    A_UINT8     status;
+    A_UINT8     hci_version;
+    A_UINT16    hci_revision;
+    A_UINT8     pal_version;
+    A_UINT16    manf_name;
+    A_UINT16    pal_sub_ver;
+} POSTPACK READ_LOCAL_VER_INFO;
+
+
+#endif  /* __A_HCI_H__ */
diff --git a/drivers/net/ath6kl/include/common/athdefs.h b/drivers/net/ath6kl/include/common/athdefs.h
new file mode 100644
index 00000000000..b59bfd3af0a
--- /dev/null
+++ b/drivers/net/ath6kl/include/common/athdefs.h
@@ -0,0 +1,84 @@
+//------------------------------------------------------------------------------
+// <copyright file="athdefs.h" company="Atheros">
+//    Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef __ATHDEFS_H__
+#define __ATHDEFS_H__
+
+/*
+ * This file contains definitions that may be used across both
+ * Host and Target software.  Nothing here is module-dependent
+ * or platform-dependent.
+ */
+
+/*
+ * Generic error codes that can be used by hw, sta, ap, sim, dk
+ * and any other environments. Since these are enums, feel free to
+ * add any more codes that you need.
+ */
+
+typedef enum {
+    A_ERROR = -1,               /* Generic error return */
+    A_OK = 0,                   /* success */
+                                /* Following values start at 1 */
+    A_DEVICE_NOT_FOUND,         /* not able to find PCI device */
+    A_NO_MEMORY,                /* not able to allocate memory, not available */
+    A_MEMORY_NOT_AVAIL,         /* memory region is not free for mapping */
+    A_NO_FREE_DESC,             /* no free descriptors available */
+    A_BAD_ADDRESS,              /* address does not match descriptor */
+    A_WIN_DRIVER_ERROR,         /* used in NT_HW version, if problem at init */
+    A_REGS_NOT_MAPPED,          /* registers not correctly mapped */
+    A_EPERM,                    /* Not superuser */
+    A_EACCES,                   /* Access denied */
+    A_ENOENT,                   /* No such entry, search failed, etc. */
+    A_EEXIST,                   /* The object already exists (can't create) */
+    A_EFAULT,                   /* Bad address fault */
+    A_EBUSY,                    /* Object is busy */
+    A_EINVAL,                   /* Invalid parameter */
+    A_EMSGSIZE,                 /* Inappropriate message buffer length */
+    A_ECANCELED,                /* Operation canceled */
+    A_ENOTSUP,                  /* Operation not supported */
+    A_ECOMM,                    /* Communication error on send */
+    A_EPROTO,                   /* Protocol error */
+    A_ENODEV,                   /* No such device */
+    A_EDEVNOTUP,                /* device is not UP */
+    A_NO_RESOURCE,              /* No resources for requested operation */
+    A_HARDWARE,                 /* Hardware failure */
+    A_PENDING,                  /* Asynchronous routine; will send up results la
+ter (typically in callback) */
+    A_EBADCHANNEL,              /* The channel cannot be used */
+    A_DECRYPT_ERROR,            /* Decryption error */
+    A_PHY_ERROR,                /* RX PHY error */
+    A_CONSUMED                  /* Object was consumed */
+} A_STATUS;
+
+#define A_SUCCESS(x)        (x == A_OK)
+#define A_FAILED(x)         (!A_SUCCESS(x))
+
+#ifndef TRUE
+#define TRUE 1
+#endif
+
+#ifndef FALSE
+#define FALSE 0
+#endif
+
+#endif /* __ATHDEFS_H__ */
diff --git a/drivers/net/ath6kl/include/common/bmi_msg.h b/drivers/net/ath6kl/include/common/bmi_msg.h
new file mode 100644
index 00000000000..f9687d325b2
--- /dev/null
+++ b/drivers/net/ath6kl/include/common/bmi_msg.h
@@ -0,0 +1,241 @@
+//------------------------------------------------------------------------------
+// Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+//
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//
+// Author(s): ="Atheros"
+//------------------------------------------------------------------------------
+
+#ifndef __BMI_MSG_H__
+#define __BMI_MSG_H__
+
+#ifndef ATH_TARGET
+#include "athstartpack.h"
+#endif
+
+/*
+ * Bootloader Messaging Interface (BMI)
+ *
+ * BMI is a very simple messaging interface used during initialization
+ * to read memory, write memory, execute code, and to define an
+ * application entry PC.
+ *
+ * It is used to download an application to AR6K, to provide
+ * patches to code that is already resident on AR6K, and generally
+ * to examine and modify state.  The Host has an opportunity to use
+ * BMI only once during bootup.  Once the Host issues a BMI_DONE
+ * command, this opportunity ends.
+ *
+ * The Host writes BMI requests to mailbox0, and reads BMI responses
+ * from mailbox0.   BMI requests all begin with a command
+ * (see below for specific commands), and are followed by
+ * command-specific data.
+ *
+ * Flow control:
+ * The Host can only issue a command once the Target gives it a
+ * "BMI Command Credit", using AR6K Counter #4.  As soon as the
+ * Target has completed a command, it issues another BMI Command
+ * Credit (so the Host can issue the next command).
+ *
+ * BMI handles all required Target-side cache flushing.
+ */
+
+
+/* Maximum data size used for BMI transfers */
+#define BMI_DATASZ_MAX                      256
+
+/* BMI Commands */
+
+#define BMI_NO_COMMAND                      0
+
+#define BMI_DONE                            1
+        /*
+         * Semantics: Host is done using BMI
+         * Request format:
+         *    A_UINT32      command (BMI_DONE)
+         * Response format: none
+         */
+
+#define BMI_READ_MEMORY                     2
+        /*
+         * Semantics: Host reads AR6K memory
+         * Request format:
+         *    A_UINT32      command (BMI_READ_MEMORY)
+         *    A_UINT32      address
+         *    A_UINT32      length, at most BMI_DATASZ_MAX
+         * Response format:
+         *    A_UINT8       data[length]
+         */
+
+#define BMI_WRITE_MEMORY                    3
+        /*
+         * Semantics: Host writes AR6K memory
+         * Request format:
+         *    A_UINT32       command (BMI_WRITE_MEMORY)
+         *    A_UINT32      address
+         *    A_UINT32      length, at most BMI_DATASZ_MAX
+         *    A_UINT8       data[length]
+         * Response format: none
+         */
+
+#define BMI_EXECUTE                         4
+        /*
+         * Semantics: Causes AR6K to execute code
+         * Request format:
+         *    A_UINT32      command (BMI_EXECUTE)
+         *    A_UINT32      address
+         *    A_UINT32      parameter
+         * Response format:
+         *    A_UINT32      return value
+         */
+
+#define BMI_SET_APP_START                   5
+        /*
+         * Semantics: Set Target application starting address
+         * Request format:
+         *    A_UINT32      command (BMI_SET_APP_START)
+         *    A_UINT32      address
+         * Response format: none
+         */
+
+#define BMI_READ_SOC_REGISTER               6
+        /*
+         * Semantics: Read a 32-bit Target SOC register.
+         * Request format:
+         *    A_UINT32      command (BMI_READ_REGISTER)
+         *    A_UINT32      address
+         * Response format: 
+         *    A_UINT32      value
+         */
+
+#define BMI_WRITE_SOC_REGISTER              7
+        /*
+         * Semantics: Write a 32-bit Target SOC register.
+         * Request format:
+         *    A_UINT32      command (BMI_WRITE_REGISTER)
+         *    A_UINT32      address
+         *    A_UINT32      value
+         *
+         * Response format: none
+         */
+
+#define BMI_GET_TARGET_ID                  8
+#define BMI_GET_TARGET_INFO                8
+        /*
+         * Semantics: Fetch the 4-byte Target information
+         * Request format:
+         *    A_UINT32      command (BMI_GET_TARGET_ID/INFO)
+         * Response format1 (old firmware):
+         *    A_UINT32      TargetVersionID
+         * Response format2 (newer firmware):
+         *    A_UINT32      TARGET_VERSION_SENTINAL
+         *    struct bmi_target_info;
+         */
+
+PREPACK struct bmi_target_info {
+    A_UINT32 target_info_byte_count; /* size of this structure */
+    A_UINT32 target_ver;             /* Target Version ID */
+    A_UINT32 target_type;            /* Target type */
+} POSTPACK;
+#define TARGET_VERSION_SENTINAL 0xffffffff
+#define TARGET_TYPE_AR6001 1
+#define TARGET_TYPE_AR6002 2
+#define TARGET_TYPE_AR6003 3
+
+
+#define BMI_ROMPATCH_INSTALL               9
+        /*
+         * Semantics: Install a ROM Patch.
+         * Request format:
+         *    A_UINT32      command (BMI_ROMPATCH_INSTALL)
+         *    A_UINT32      Target ROM Address
+         *    A_UINT32      Target RAM Address or Value (depending on Target Type)
+         *    A_UINT32      Size, in bytes
+         *    A_UINT32      Activate? 1-->activate;
+         *                            0-->install but do not activate
+         * Response format:
+         *    A_UINT32      PatchID
+         */
+
+#define BMI_ROMPATCH_UNINSTALL             10
+        /*
+         * Semantics: Uninstall a previously-installed ROM Patch,
+         * automatically deactivating, if necessary.
+         * Request format:
+         *    A_UINT32      command (BMI_ROMPATCH_UNINSTALL)
+         *    A_UINT32      PatchID
+         *
+         * Response format: none
+         */
+
+#define BMI_ROMPATCH_ACTIVATE              11
+        /*
+         * Semantics: Activate a list of previously-installed ROM Patches.
+         * Request format:
+         *    A_UINT32      command (BMI_ROMPATCH_ACTIVATE)
+         *    A_UINT32      rompatch_count
+         *    A_UINT32      PatchID[rompatch_count]
+         *
+         * Response format: none
+         */
+
+#define BMI_ROMPATCH_DEACTIVATE            12
+        /*
+         * Semantics: Deactivate a list of active ROM Patches.
+         * Request format:
+         *    A_UINT32      command (BMI_ROMPATCH_DEACTIVATE)
+         *    A_UINT32      rompatch_count
+         *    A_UINT32      PatchID[rompatch_count]
+         *
+         * Response format: none
+         */
+
+
+#define BMI_LZ_STREAM_START                13
+        /*
+         * Semantics: Begin an LZ-compressed stream of input
+         * which is to be uncompressed by the Target to an
+         * output buffer at address.  The output buffer must
+         * be sufficiently large to hold the uncompressed
+         * output from the compressed input stream.  This BMI
+         * command should be followed by a series of 1 or more
+         * BMI_LZ_DATA commands.
+         *    A_UINT32      command (BMI_LZ_STREAM_START)
+         *    A_UINT32      address
+         * Note: Not supported on all versions of ROM firmware.
+         */
+
+#define BMI_LZ_DATA                        14
+        /*
+         * Semantics: Host writes AR6K memory with LZ-compressed
+         * data which is uncompressed by the Target.  This command
+         * must be preceded by a BMI_LZ_STREAM_START command. A series
+         * of BMI_LZ_DATA commands are considered part of a single
+         * input stream until another BMI_LZ_STREAM_START is issued.
+         * Request format:
+         *    A_UINT32      command (BMI_LZ_DATA)
+         *    A_UINT32      length (of compressed data),
+         *                  at most BMI_DATASZ_MAX
+         *    A_UINT8       CompressedData[length]
+         * Response format: none
+         * Note: Not supported on all versions of ROM firmware.
+         */
+
+#ifndef ATH_TARGET
+#include "athendpack.h"
+#endif
+
+#endif /* __BMI_MSG_H__ */
diff --git a/drivers/net/ath6kl/include/common/btcoexGpio.h b/drivers/net/ath6kl/include/common/btcoexGpio.h
new file mode 100644
index 00000000000..bc067f557ea
--- /dev/null
+++ b/drivers/net/ath6kl/include/common/btcoexGpio.h
@@ -0,0 +1,86 @@
+// Copyright (c) 2010 Atheros Communications Inc.
+// All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+
+#ifndef BTCOEX_GPIO_H_
+#define BTCOEX_GPIO_H_
+
+
+
+#ifdef FPGA
+#define GPIO_A      (15)
+#define GPIO_B      (16)
+#define GPIO_C      (17)
+#define GPIO_D      (18)
+#define GPIO_E      (19)
+#define GPIO_F      (21)
+#define GPIO_G      (21)
+#else
+#define GPIO_A      (0)
+#define GPIO_B      (5)
+#define GPIO_C      (6)
+#define GPIO_D      (7)
+#define GPIO_E      (7)
+#define GPIO_F      (7)
+#define GPIO_G      (7)
+#endif
+
+
+
+
+
+#define GPIO_DEBUG_WORD_1                                 (1<<GPIO_A)
+#define GPIO_DEBUG_WORD_2                   (1<<GPIO_B)
+#define GPIO_DEBUG_WORD_3                  ((1<<GPIO_B) | (1<<GPIO_A))
+#define GPIO_DEBUG_WORD_4     (1<<GPIO_C)
+#define GPIO_DEBUG_WORD_5    ((1<<GPIO_C) |               (1<<GPIO_A))
+#define GPIO_DEBUG_WORD_6    ((1<<GPIO_C) | (1<<GPIO_B))
+#define GPIO_DEBUG_WORD_7    ((1<<GPIO_C) | (1<<GPIO_B) | (1<<GPIO_A))
+
+#define GPIO_DEBUG_WORD_8     (1<<GPIO_D)
+#define GPIO_DEBUG_WORD_9    ((1<<GPIO_D) | GPIO_DEBUG_WORD_1)
+#define GPIO_DEBUG_WORD_10   ((1<<GPIO_D) | GPIO_DEBUG_WORD_2)
+#define GPIO_DEBUG_WORD_11   ((1<<GPIO_D) | GPIO_DEBUG_WORD_3)
+#define GPIO_DEBUG_WORD_12   ((1<<GPIO_D) | GPIO_DEBUG_WORD_4)
+#define GPIO_DEBUG_WORD_13   ((1<<GPIO_D) | GPIO_DEBUG_WORD_5)
+#define GPIO_DEBUG_WORD_14   ((1<<GPIO_D) | GPIO_DEBUG_WORD_6)
+#define GPIO_DEBUG_WORD_15   ((1<<GPIO_D) | GPIO_DEBUG_WORD_7)
+
+#define GPIO_DEBUG_WORD_16   (1<<GPIO_E)
+#define GPIO_DEBUG_WORD_17    ((1<<GPIO_E) | GPIO_DEBUG_WORD_1)
+#define GPIO_DEBUG_WORD_18   ((1<<GPIO_E) | GPIO_DEBUG_WORD_2)
+#define GPIO_DEBUG_WORD_19   ((1<<GPIO_E) | GPIO_DEBUG_WORD_3)
+#define GPIO_DEBUG_WORD_20   ((1<<GPIO_E) | GPIO_DEBUG_WORD_4)
+#define GPIO_DEBUG_WORD_21   ((1<<GPIO_E) | GPIO_DEBUG_WORD_5)
+#define GPIO_DEBUG_WORD_22   ((1<<GPIO_E) | GPIO_DEBUG_WORD_6)
+#define GPIO_DEBUG_WORD_23   ((1<<GPIO_E) | GPIO_DEBUG_WORD_7)
+
+
+
+extern void btcoexDbgPulseWord(A_UINT32 gpioPinMask);
+extern void btcoexDbgPulse(A_UINT32 pin);
+
+#ifdef CONFIG_BTCOEX_ENABLE_GPIO_DEBUG
+#define BTCOEX_DBG_PULSE_WORD(gpioPinMask)  (btcoexDbgPulseWord(gpioPinMask))
+#define BTCOEX_DBG_PULSE(pin)               (btcoexDbgPulse(pin))
+#else
+#define BTCOEX_DBG_PULSE_WORD(gpioPinMask)
+#define BTCOEX_DBG_PULSE(pin)
+
+#endif
+#endif
+
diff --git a/drivers/net/ath6kl/include/common/cnxmgmt.h b/drivers/net/ath6kl/include/common/cnxmgmt.h
new file mode 100644
index 00000000000..7a902cb5483
--- /dev/null
+++ b/drivers/net/ath6kl/include/common/cnxmgmt.h
@@ -0,0 +1,36 @@
+//------------------------------------------------------------------------------
+// <copyright file="cnxmgmt.h" company="Atheros">
+//    Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+#ifndef _CNXMGMT_H_
+#define _CNXMGMT_H_
+
+typedef enum {
+    CM_CONNECT_WITHOUT_SCAN             = 0x0001,
+    CM_CONNECT_ASSOC_POLICY_USER        = 0x0002,
+    CM_CONNECT_SEND_REASSOC             = 0x0004,
+    CM_CONNECT_WITHOUT_ROAMTABLE_UPDATE = 0x0008,
+    CM_CONNECT_DO_WPA_OFFLOAD           = 0x0010,
+    CM_CONNECT_DO_NOT_DEAUTH            = 0x0020,
+} CM_CONNECT_TYPE;
+
+#endif  /* _CNXMGMT_H_ */
diff --git a/drivers/net/ath6kl/include/common/dbglog.h b/drivers/net/ath6kl/include/common/dbglog.h
new file mode 100644
index 00000000000..382d9a2dd4e
--- /dev/null
+++ b/drivers/net/ath6kl/include/common/dbglog.h
@@ -0,0 +1,134 @@
+//------------------------------------------------------------------------------
+// <copyright file="dbglog.h" company="Atheros">
+//    Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+#ifndef _DBGLOG_H_
+#define _DBGLOG_H_
+
+#ifndef ATH_TARGET
+#include "athstartpack.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define DBGLOG_TIMESTAMP_OFFSET          0
+#define DBGLOG_TIMESTAMP_MASK            0x0000FFFF /* Bit 0-15. Contains bit
+                                                       8-23 of the LF0 timer */
+#define DBGLOG_DBGID_OFFSET              16
+#define DBGLOG_DBGID_MASK                0x03FF0000 /* Bit 16-25 */
+#define DBGLOG_DBGID_NUM_MAX             256 /* Upper limit is width of mask */
+
+#define DBGLOG_MODULEID_OFFSET           26
+#define DBGLOG_MODULEID_MASK             0x3C000000 /* Bit 26-29 */
+#define DBGLOG_MODULEID_NUM_MAX          16 /* Upper limit is width of mask */
+
+/*
+ * Please ensure that the definition of any new module intrduced is captured
+ * between the DBGLOG_MODULEID_START and DBGLOG_MODULEID_END defines. The 
+ * structure is required for the parser to correctly pick up the values for
+ * different modules.
+ */
+#define DBGLOG_MODULEID_START
+#define DBGLOG_MODULEID_INF                   0
+#define DBGLOG_MODULEID_WMI                   1
+#define DBGLOG_MODULEID_MISC                  2
+#define DBGLOG_MODULEID_PM                    3
+#define DBGLOG_MODULEID_TXRX_MGMTBUF          4
+#define DBGLOG_MODULEID_TXRX_TXBUF            5
+#define DBGLOG_MODULEID_TXRX_RXBUF            6
+#define DBGLOG_MODULEID_WOW                   7
+#define DBGLOG_MODULEID_WHAL                  8
+#define DBGLOG_MODULEID_DC                    9
+#define DBGLOG_MODULEID_CO                    10
+#define DBGLOG_MODULEID_RO                    11
+#define DBGLOG_MODULEID_CM                    12
+#define DBGLOG_MODULEID_MGMT                  13
+#define DBGLOG_MODULEID_TMR                   14
+#define DBGLOG_MODULEID_BTCOEX                15
+#define DBGLOG_MODULEID_END
+
+#define DBGLOG_NUM_ARGS_OFFSET             30
+#define DBGLOG_NUM_ARGS_MASK               0xC0000000 /* Bit 30-31 */
+#define DBGLOG_NUM_ARGS_MAX                2 /* Upper limit is width of mask */
+
+#define DBGLOG_MODULE_LOG_ENABLE_OFFSET    0
+#define DBGLOG_MODULE_LOG_ENABLE_MASK      0x0000FFFF
+
+#define DBGLOG_REPORTING_ENABLED_OFFSET    16
+#define DBGLOG_REPORTING_ENABLED_MASK      0x00010000
+
+#define DBGLOG_TIMESTAMP_RESOLUTION_OFFSET 17
+#define DBGLOG_TIMESTAMP_RESOLUTION_MASK   0x000E0000
+
+#define DBGLOG_REPORT_SIZE_OFFSET          20
+#define DBGLOG_REPORT_SIZE_MASK            0x3FF00000
+
+#define DBGLOG_LOG_BUFFER_SIZE             1500
+#define DBGLOG_DBGID_DEFINITION_LEN_MAX    90
+
+PREPACK struct dbglog_buf_s {
+    struct dbglog_buf_s *next;
+    A_UINT8             *buffer;
+    A_UINT32             bufsize;
+    A_UINT32             length;
+    A_UINT32             count;
+    A_UINT32             free;
+} POSTPACK;
+
+PREPACK struct dbglog_hdr_s {
+    struct dbglog_buf_s *dbuf;
+    A_UINT32             dropped;
+} POSTPACK;
+
+PREPACK struct dbglog_config_s {
+    A_UINT32                    cfgvalid; /* Mask with valid config bits */
+    union {
+        /* TODO: Take care of endianness */
+        struct {
+            A_UINT32            mmask:16; /* Mask of modules with logging on */
+            A_UINT32            rep:1; /* Reporting enabled or not */
+            A_UINT32            tsr:3; /* Time stamp resolution. Def: 1 ms */
+            A_UINT32            size:10; /* Report size in number of messages */
+            A_UINT32            reserved:2;
+        } dbglog_config;
+
+        A_UINT32                value;
+    } u;
+} POSTPACK;
+
+#define cfgmmask                   u.dbglog_config.mmask
+#define cfgrep                     u.dbglog_config.rep
+#define cfgtsr                     u.dbglog_config.tsr
+#define cfgsize                    u.dbglog_config.size
+#define cfgvalue                   u.value
+
+#ifdef __cplusplus
+}
+#endif
+
+#ifndef ATH_TARGET
+#include "athendpack.h"
+#endif
+
+#endif /* _DBGLOG_H_ */
diff --git a/drivers/net/ath6kl/include/common/dbglog_id.h b/drivers/net/ath6kl/include/common/dbglog_id.h
new file mode 100644
index 00000000000..15ef829cab2
--- /dev/null
+++ b/drivers/net/ath6kl/include/common/dbglog_id.h
@@ -0,0 +1,558 @@
+//------------------------------------------------------------------------------
+// <copyright file="dbglog_id.h" company="Atheros">
+//    Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+#ifndef _DBGLOG_ID_H_
+#define _DBGLOG_ID_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* 
+ * The nomenclature for the debug identifiers is MODULE_DESCRIPTION.
+ * Please ensure that the definition of any new debugid introduced is captured
+ * between the <MODULE>_DBGID_DEFINITION_START and 
+ * <MODULE>_DBGID_DEFINITION_END defines. The structure is required for the 
+ * parser to correctly pick up the values for different debug identifiers.
+ */
+
+/* INF debug identifier definitions */
+#define INF_DBGID_DEFINITION_START
+#define INF_ASSERTION_FAILED                          1
+#define INF_TARGET_ID                                 2
+#define INF_DBGID_DEFINITION_END
+
+/* WMI debug identifier definitions */
+#define WMI_DBGID_DEFINITION_START
+#define WMI_CMD_RX_XTND_PKT_TOO_SHORT                 1
+#define WMI_EXTENDED_CMD_NOT_HANDLED                  2
+#define WMI_CMD_RX_PKT_TOO_SHORT                      3
+#define WMI_CALLING_WMI_EXTENSION_FN                  4
+#define WMI_CMD_NOT_HANDLED                           5
+#define WMI_IN_SYNC                                   6
+#define WMI_TARGET_WMI_SYNC_CMD                       7
+#define WMI_SET_SNR_THRESHOLD_PARAMS                  8
+#define WMI_SET_RSSI_THRESHOLD_PARAMS                 9
+#define WMI_SET_LQ_TRESHOLD_PARAMS                   10
+#define WMI_TARGET_CREATE_PSTREAM_CMD                11
+#define WMI_WI_DTM_INUSE                             12
+#define WMI_TARGET_DELETE_PSTREAM_CMD                13
+#define WMI_TARGET_IMPLICIT_DELETE_PSTREAM_CMD       14
+#define WMI_TARGET_GET_BIT_RATE_CMD                  15
+#define WMI_GET_RATE_MASK_CMD_FIX_RATE_MASK_IS       16
+#define WMI_TARGET_GET_AVAILABLE_CHANNELS_CMD        17
+#define WMI_TARGET_GET_TX_PWR_CMD                    18
+#define WMI_FREE_EVBUF_WMIBUF                        19
+#define WMI_FREE_EVBUF_DATABUF                       20
+#define WMI_FREE_EVBUF_BADFLAG                       21
+#define WMI_HTC_RX_ERROR_DATA_PACKET                 22
+#define WMI_HTC_RX_SYNC_PAUSING_FOR_MBOX             23
+#define WMI_INCORRECT_WMI_DATA_HDR_DROPPING_PKT      24
+#define WMI_SENDING_READY_EVENT                      25
+#define WMI_SETPOWER_MDOE_TO_MAXPERF                 26
+#define WMI_SETPOWER_MDOE_TO_REC                     27
+#define WMI_BSSINFO_EVENT_FROM                       28
+#define WMI_TARGET_GET_STATS_CMD                     29
+#define WMI_SENDING_SCAN_COMPLETE_EVENT              30
+#define WMI_SENDING_RSSI_INDB_THRESHOLD_EVENT        31
+#define WMI_SENDING_RSSI_INDBM_THRESHOLD_EVENT       32
+#define WMI_SENDING_LINK_QUALITY_THRESHOLD_EVENT     33
+#define WMI_SENDING_ERROR_REPORT_EVENT               34
+#define WMI_SENDING_CAC_EVENT                        35
+#define WMI_TARGET_GET_ROAM_TABLE_CMD                36
+#define WMI_TARGET_GET_ROAM_DATA_CMD                 37
+#define WMI_SENDING_GPIO_INTR_EVENT                  38
+#define WMI_SENDING_GPIO_ACK_EVENT                   39
+#define WMI_SENDING_GPIO_DATA_EVENT                  40
+#define WMI_CMD_RX                                   41
+#define WMI_CMD_RX_XTND                              42
+#define WMI_EVENT_SEND                               43
+#define WMI_EVENT_SEND_XTND                          44
+#define WMI_CMD_PARAMS_DUMP_START                    45
+#define WMI_CMD_PARAMS_DUMP_END                      46
+#define WMI_CMD_PARAMS                               47
+#define WMI_DBGID_DEFINITION_END
+
+/* MISC debug identifier definitions */
+#define MISC_DBGID_DEFINITION_START
+#define MISC_WLAN_SCHEDULER_EVENT_REGISTER_ERROR     1
+#define TLPM_INIT                                    2
+#define TLPM_FILTER_POWER_STATE                      3
+#define TLPM_NOTIFY_NOT_IDLE                         4
+#define TLPM_TIMEOUT_IDLE_HANDLER                    5
+#define TLPM_TIMEOUT_WAKEUP_HANDLER                  6
+#define TLPM_WAKEUP_SIGNAL_HANDLER                   7
+#define TLPM_UNEXPECTED_GPIO_INTR_ERROR              8
+#define TLPM_BREAK_ON_NOT_RECEIVED_ERROR             9
+#define TLPM_BREAK_OFF_NOT_RECIVED_ERROR             10
+#define TLPM_ACK_GPIO_INTR                           11
+#define TLPM_ON                                      12
+#define TLPM_OFF                                     13
+#define TLPM_WAKEUP_FROM_HOST                        14
+#define TLPM_WAKEUP_FROM_BT                          15 
+#define TLPM_TX_BREAK_RECIVED                        16
+#define TLPM_IDLE_TIMER_NOT_RUNNING                  17
+#define MISC_DBGID_DEFINITION_END
+    
+/* TXRX debug identifier definitions */
+#define TXRX_TXBUF_DBGID_DEFINITION_START
+#define TXRX_TXBUF_ALLOCATE_BUF                      1
+#define TXRX_TXBUF_QUEUE_BUF_TO_MBOX                 2
+#define TXRX_TXBUF_QUEUE_BUF_TO_TXQ                  3
+#define TXRX_TXBUF_TXQ_DEPTH                         4   
+#define TXRX_TXBUF_IBSS_QUEUE_TO_SFQ                 5
+#define TXRX_TXBUF_IBSS_QUEUE_TO_TXQ_FRM_SFQ         6
+#define TXRX_TXBUF_INITIALIZE_TIMER                  7
+#define TXRX_TXBUF_ARM_TIMER                         8
+#define TXRX_TXBUF_DISARM_TIMER                      9
+#define TXRX_TXBUF_UNINITIALIZE_TIMER                10
+#define TXRX_TXBUF_DBGID_DEFINITION_END
+ 
+#define TXRX_RXBUF_DBGID_DEFINITION_START    
+#define TXRX_RXBUF_ALLOCATE_BUF                      1
+#define TXRX_RXBUF_QUEUE_TO_HOST                     2
+#define TXRX_RXBUF_QUEUE_TO_WLAN                     3
+#define TXRX_RXBUF_ZERO_LEN_BUF                      4
+#define TXRX_RXBUF_QUEUE_TO_HOST_LASTBUF_IN_RXCHAIN  5
+#define TXRX_RXBUF_LASTBUF_IN_RXCHAIN_ZEROBUF        6
+#define TXRX_RXBUF_QUEUE_EMPTY_QUEUE_TO_WLAN         7
+#define TXRX_RXBUF_SEND_TO_RECV_MGMT                 8
+#define TXRX_RXBUF_SEND_TO_IEEE_LAYER                9
+#define TXRX_RXBUF_REQUEUE_ERROR                     10
+#define TXRX_RXBUF_DBGID_DEFINITION_END
+
+#define TXRX_MGMTBUF_DBGID_DEFINITION_START 
+#define TXRX_MGMTBUF_ALLOCATE_BUF                    1
+#define TXRX_MGMTBUF_ALLOCATE_SM_BUF                 2    
+#define TXRX_MGMTBUF_ALLOCATE_RMBUF                  3
+#define TXRX_MGMTBUF_GET_BUF                         4
+#define TXRX_MGMTBUF_GET_SM_BUF                      5
+#define TXRX_MGMTBUF_QUEUE_BUF_TO_TXQ                6
+#define TXRX_MGMTBUF_REAPED_BUF                      7
+#define TXRX_MGMTBUF_REAPED_SM_BUF                   8
+#define TXRX_MGMTBUF_WAIT_FOR_TXQ_DRAIN              9
+#define TXRX_MGMTBUF_WAIT_FOR_TXQ_SFQ_DRAIN          10
+#define TXRX_MGMTBUF_ENQUEUE_INTO_DATA_SFQ           11
+#define TXRX_MGMTBUF_DEQUEUE_FROM_DATA_SFQ           12
+#define TXRX_MGMTBUF_PAUSE_DATA_TXQ                  13
+#define TXRX_MGMTBUF_RESUME_DATA_TXQ                 14
+#define TXRX_MGMTBUF_WAIT_FORTXQ_DRAIN_TIMEOUT       15
+#define TXRX_MGMTBUF_DRAINQ                          16
+#define TXRX_MGMTBUF_INDICATE_Q_DRAINED              17
+#define TXRX_MGMTBUF_ENQUEUE_INTO_HW_SFQ             18
+#define TXRX_MGMTBUF_DEQUEUE_FROM_HW_SFQ             19
+#define TXRX_MGMTBUF_PAUSE_HW_TXQ                    20
+#define TXRX_MGMTBUF_RESUME_HW_TXQ                   21
+#define TXRX_MGMTBUF_TEAR_DOWN_BA                    22
+#define TXRX_MGMTBUF_PROCESS_ADDBA_REQ               23
+#define TXRX_MGMTBUF_PROCESS_DELBA                   24
+#define TXRX_MGMTBUF_PERFORM_BA                      25
+#define TXRX_MGMTBUF_WLAN_RESET_ON_ERROR             26 
+#define TXRX_MGMTBUF_DBGID_DEFINITION_END
+
+/* PM (Power Module) debug identifier definitions */
+#define PM_DBGID_DEFINITION_START
+#define PM_INIT                                      1
+#define PM_ENABLE                                    2
+#define PM_SET_STATE                                 3
+#define PM_SET_POWERMODE                             4
+#define PM_CONN_NOTIFY                               5
+#define PM_REF_COUNT_NEGATIVE                        6
+#define PM_INFRA_STA_APSD_ENABLE                     7
+#define PM_INFRA_STA_UPDATE_APSD_STATE               8
+#define PM_CHAN_OP_REQ                               9
+#define PM_SET_MY_BEACON_POLICY                      10
+#define PM_SET_ALL_BEACON_POLICY                     11
+#define PM_INFRA_STA_SET_PM_PARAMS1                  12
+#define PM_INFRA_STA_SET_PM_PARAMS2                  13
+#define PM_ADHOC_SET_PM_CAPS_FAIL                    14
+#define PM_ADHOC_UNKNOWN_IBSS_ATTRIB_ID              15
+#define PM_ADHOC_SET_PM_PARAMS                       16
+#define PM_ADHOC_STATE1                              18
+#define PM_ADHOC_STATE2                              19
+#define PM_ADHOC_CONN_MAP                            20 
+#define PM_FAKE_SLEEP                                21
+#define PM_AP_STATE1                                 22
+#define PM_AP_SET_PM_PARAMS                          23
+#define PM_DBGID_DEFINITION_END
+
+/* Wake on Wireless debug identifier definitions */
+#define WOW_DBGID_DEFINITION_START
+#define WOW_INIT                                        1
+#define WOW_GET_CONFIG_DSET                             2   
+#define WOW_NO_CONFIG_DSET                              3
+#define WOW_INVALID_CONFIG_DSET                         4
+#define WOW_USE_DEFAULT_CONFIG                          5
+#define WOW_SETUP_GPIO                                  6
+#define WOW_INIT_DONE                                   7
+#define WOW_SET_GPIO_PIN                                8
+#define WOW_CLEAR_GPIO_PIN                              9
+#define WOW_SET_WOW_MODE_CMD                            10
+#define WOW_SET_HOST_MODE_CMD                           11  
+#define WOW_ADD_WOW_PATTERN_CMD                         12    
+#define WOW_NEW_WOW_PATTERN_AT_INDEX                    13    
+#define WOW_DEL_WOW_PATTERN_CMD                         14    
+#define WOW_LIST_CONTAINS_PATTERNS                      15    
+#define WOW_GET_WOW_LIST_CMD                            16 
+#define WOW_INVALID_FILTER_ID                           17
+#define WOW_INVALID_FILTER_LISTID                       18
+#define WOW_NO_VALID_FILTER_AT_ID                       19
+#define WOW_NO_VALID_LIST_AT_ID                         20
+#define WOW_NUM_PATTERNS_EXCEEDED                       21
+#define WOW_NUM_LISTS_EXCEEDED                          22
+#define WOW_GET_WOW_STATS                               23
+#define WOW_CLEAR_WOW_STATS                             24
+#define WOW_WAKEUP_HOST                                 25
+#define WOW_EVENT_WAKEUP_HOST                           26
+#define WOW_EVENT_DISCARD                               27
+#define WOW_PATTERN_MATCH                               28
+#define WOW_PATTERN_NOT_MATCH                           29
+#define WOW_PATTERN_NOT_MATCH_OFFSET                    30
+#define WOW_DISABLED_HOST_ASLEEP                        31
+#define WOW_ENABLED_HOST_ASLEEP_NO_PATTERNS             32
+#define WOW_ENABLED_HOST_ASLEEP_NO_MATCH_FOUND          33
+#define WOW_DBGID_DEFINITION_END
+
+/* WHAL debug identifier definitions */
+#define WHAL_DBGID_DEFINITION_START
+#define WHAL_ERROR_ANI_CONTROL                      1
+#define WHAL_ERROR_CHIP_TEST1                       2
+#define WHAL_ERROR_CHIP_TEST2                       3
+#define WHAL_ERROR_EEPROM_CHECKSUM                  4
+#define WHAL_ERROR_EEPROM_MACADDR                   5
+#define WHAL_ERROR_INTERRUPT_HIU                    6
+#define WHAL_ERROR_KEYCACHE_RESET                   7
+#define WHAL_ERROR_KEYCACHE_SET                     8 
+#define WHAL_ERROR_KEYCACHE_TYPE                    9
+#define WHAL_ERROR_KEYCACHE_TKIPENTRY              10
+#define WHAL_ERROR_KEYCACHE_WEPLENGTH              11
+#define WHAL_ERROR_PHY_INVALID_CHANNEL             12
+#define WHAL_ERROR_POWER_AWAKE                     13
+#define WHAL_ERROR_POWER_SET                       14
+#define WHAL_ERROR_RECV_STOPDMA                    15
+#define WHAL_ERROR_RECV_STOPPCU                    16
+#define WHAL_ERROR_RESET_CHANNF1                   17
+#define WHAL_ERROR_RESET_CHANNF2                   18
+#define WHAL_ERROR_RESET_PM                        19
+#define WHAL_ERROR_RESET_OFFSETCAL                 20
+#define WHAL_ERROR_RESET_RFGRANT                   21
+#define WHAL_ERROR_RESET_RXFRAME                   22
+#define WHAL_ERROR_RESET_STOPDMA                   23
+#define WHAL_ERROR_RESET_RECOVER                   24
+#define WHAL_ERROR_XMIT_COMPUTE                    25
+#define WHAL_ERROR_XMIT_NOQUEUE                    26
+#define WHAL_ERROR_XMIT_ACTIVEQUEUE                27
+#define WHAL_ERROR_XMIT_BADTYPE                    28
+#define WHAL_ERROR_XMIT_STOPDMA                    29
+#define WHAL_ERROR_INTERRUPT_BB_PANIC              30 
+#define WHAL_ERROR_RESET_TXIQCAL                   31 
+#define WHAL_ERROR_PAPRD_MAXGAIN_ABOVE_WINDOW      32 
+#define WHAL_DBGID_DEFINITION_END
+
+/* DC debug identifier definitions */
+#define DC_DBGID_DEFINITION_START
+#define DC_SCAN_CHAN_START                          1
+#define DC_SCAN_CHAN_FINISH                         2
+#define DC_BEACON_RECEIVE7                          3
+#define DC_SSID_PROBE_CB                            4
+#define DC_SEND_NEXT_SSID_PROBE                     5
+#define DC_START_SEARCH                             6
+#define DC_CANCEL_SEARCH_CB                         7
+#define DC_STOP_SEARCH                              8
+#define DC_END_SEARCH                               9
+#define DC_MIN_CHDWELL_TIMEOUT                     10
+#define DC_START_SEARCH_CANCELED                   11
+#define DC_SET_POWER_MODE                          12
+#define DC_INIT                                    13
+#define DC_SEARCH_OPPORTUNITY                      14
+#define DC_RECEIVED_ANY_BEACON                     15
+#define DC_RECEIVED_MY_BEACON                      16
+#define DC_PROFILE_IS_ADHOC_BUT_BSS_IS_INFRA       17
+#define DC_PS_ENABLED_BUT_ATHEROS_IE_ABSENT        18
+#define DC_BSS_ADHOC_CHANNEL_NOT_ALLOWED           19
+#define DC_SET_BEACON_UPDATE                       20
+#define DC_BEACON_UPDATE_COMPLETE                  21
+#define DC_END_SEARCH_BEACON_UPDATE_COMP_CB        22
+#define DC_BSSINFO_EVENT_DROPPED                   23
+#define DC_IEEEPS_ENABLED_BUT_ATIM_ABSENT          24 
+#define DC_DBGID_DEFINITION_END
+
+/* CO debug identifier definitions */
+#define CO_DBGID_DEFINITION_START
+#define CO_INIT                                     1
+#define CO_ACQUIRE_LOCK                             2
+#define CO_START_OP1                                3
+#define CO_START_OP2                                4
+#define CO_DRAIN_TX_COMPLETE_CB                     5
+#define CO_CHANGE_CHANNEL_CB                        6
+#define CO_RETURN_TO_HOME_CHANNEL                   7
+#define CO_FINISH_OP_TIMEOUT                        8
+#define CO_OP_END                                   9
+#define CO_CANCEL_OP                               10
+#define CO_CHANGE_CHANNEL                          11
+#define CO_RELEASE_LOCK                            12
+#define CO_CHANGE_STATE                            13
+#define CO_DBGID_DEFINITION_END
+
+/* RO debug identifier definitions */
+#define RO_DBGID_DEFINITION_START
+#define RO_REFRESH_ROAM_TABLE                       1
+#define RO_UPDATE_ROAM_CANDIDATE                    2
+#define RO_UPDATE_ROAM_CANDIDATE_CB                 3
+#define RO_UPDATE_ROAM_CANDIDATE_FINISH             4
+#define RO_REFRESH_ROAM_TABLE_DONE                  5
+#define RO_PERIODIC_SEARCH_CB                       6
+#define RO_PERIODIC_SEARCH_TIMEOUT                  7
+#define RO_INIT                                     8
+#define RO_BMISS_STATE1                             9
+#define RO_BMISS_STATE2                            10
+#define RO_SET_PERIODIC_SEARCH_ENABLE              11
+#define RO_SET_PERIODIC_SEARCH_DISABLE             12
+#define RO_ENABLE_SQ_THRESHOLD                     13
+#define RO_DISABLE_SQ_THRESHOLD                    14
+#define RO_ADD_BSS_TO_ROAM_TABLE                   15
+#define RO_SET_PERIODIC_SEARCH_MODE                16
+#define RO_CONFIGURE_SQ_THRESHOLD1                 17
+#define RO_CONFIGURE_SQ_THRESHOLD2                 18
+#define RO_CONFIGURE_SQ_PARAMS                     19
+#define RO_LOW_SIGNAL_QUALITY_EVENT                20
+#define RO_HIGH_SIGNAL_QUALITY_EVENT               21
+#define RO_REMOVE_BSS_FROM_ROAM_TABLE              22
+#define RO_UPDATE_CONNECTION_STATE_METRIC          23
+#define RO_DBGID_DEFINITION_END
+
+/* CM debug identifier definitions */
+#define CM_DBGID_DEFINITION_START
+#define CM_INITIATE_HANDOFF                         1
+#define CM_INITIATE_HANDOFF_CB                      2
+#define CM_CONNECT_EVENT                            3
+#define CM_DISCONNECT_EVENT                         4
+#define CM_INIT                                     5
+#define CM_HANDOFF_SOURCE                           6
+#define CM_SET_HANDOFF_TRIGGERS                     7
+#define CM_CONNECT_REQUEST                          8
+#define CM_CONNECT_REQUEST_CB                       9
+#define CM_CONTINUE_SCAN_CB                         10 
+#define CM_DBGID_DEFINITION_END
+
+
+/* mgmt debug identifier definitions */
+#define MGMT_DBGID_DEFINITION_START
+#define KEYMGMT_CONNECTION_INIT                     1
+#define KEYMGMT_CONNECTION_COMPLETE                 2
+#define KEYMGMT_CONNECTION_CLOSE                    3
+#define KEYMGMT_ADD_KEY                             4
+#define MLME_NEW_STATE                              5
+#define MLME_CONN_INIT                              6
+#define MLME_CONN_COMPLETE                          7
+#define MLME_CONN_CLOSE                             8 
+#define MGMT_DBGID_DEFINITION_END
+
+/* TMR debug identifier definitions */
+#define TMR_DBGID_DEFINITION_START
+#define TMR_HANG_DETECTED                           1
+#define TMR_WDT_TRIGGERED                           2
+#define TMR_WDT_RESET                               3
+#define TMR_HANDLER_ENTRY                           4
+#define TMR_HANDLER_EXIT                            5
+#define TMR_SAVED_START                             6
+#define TMR_SAVED_END                               7
+#define TMR_DBGID_DEFINITION_END
+
+/* BTCOEX debug identifier definitions */
+#define BTCOEX_DBGID_DEFINITION_START
+#define BTCOEX_STATUS_CMD                           1
+#define BTCOEX_PARAMS_CMD                           2
+#define BTCOEX_ANT_CONFIG                           3
+#define BTCOEX_COLOCATED_BT_DEVICE                  4
+#define BTCOEX_CLOSE_RANGE_SCO_ON                   5
+#define BTCOEX_CLOSE_RANGE_SCO_OFF                  6
+#define BTCOEX_CLOSE_RANGE_A2DP_ON                  7
+#define BTCOEX_CLOSE_RANGE_A2DP_OFF                 8
+#define BTCOEX_A2DP_PROTECT_ON                      9
+#define BTCOEX_A2DP_PROTECT_OFF                     10
+#define BTCOEX_SCO_PROTECT_ON                       11
+#define BTCOEX_SCO_PROTECT_OFF                      12
+#define BTCOEX_CLOSE_RANGE_DETECTOR_START           13
+#define BTCOEX_CLOSE_RANGE_DETECTOR_STOP            14
+#define BTCOEX_CLOSE_RANGE_TOGGLE                   15
+#define BTCOEX_CLOSE_RANGE_TOGGLE_RSSI_LRCNT        16
+#define BTCOEX_CLOSE_RANGE_RSSI_THRESH              17
+#define BTCOEX_CLOSE_RANGE_LOW_RATE_THRESH          18
+#define BTCOEX_PTA_PRI_INTR_HANDLER  		        19
+#define BTCOEX_PSPOLL_QUEUED						20
+#define BTCOEX_PSPOLL_COMPLETE						21
+#define BTCOEX_DBG_PM_AWAKE							22
+#define BTCOEX_DBG_PM_SLEEP							23
+#define BTCOEX_DBG_SCO_COEX_ON						24
+#define BTCOEX_SCO_DATARECEIVE						25
+#define BTCOEX_INTR_INIT							26
+#define BTCOEX_PTA_PRI_DIFF							27
+#define BTCOEX_TIM_NOTIFICATION						28
+#define BTCOEX_SCO_WAKEUP_ON_DATA					29
+#define BTCOEX_SCO_SLEEP							30
+#define BTCOEX_SET_WEIGHTS							31
+#define BTCOEX_SCO_DATARECEIVE_LATENCY_VAL			32
+#define BTCOEX_SCO_MEASURE_TIME_DIFF				33
+#define BTCOEX_SET_EOL_VAL							34
+#define BTCOEX_OPT_DETECT_HANDLER					35
+#define BTCOEX_SCO_TOGGLE_STATE						36
+#define BTCOEX_SCO_STOMP							37
+#define BTCOEX_NULL_COMP_CALLBACK					38
+#define BTCOEX_RX_INCOMING							39
+#define BTCOEX_RX_INCOMING_CTL						40
+#define BTCOEX_RX_INCOMING_MGMT						41
+#define BTCOEX_RX_INCOMING_DATA						42
+#define BTCOEX_RTS_RECEPTION						43
+#define BTCOEX_FRAME_PRI_LOW_RATE_THRES				44
+#define BTCOEX_PM_FAKE_SLEEP						45
+#define BTCOEX_ACL_COEX_STATUS						46
+#define BTCOEX_ACL_COEX_DETECTION					47
+#define BTCOEX_A2DP_COEX_STATUS						48
+#define BTCOEX_SCO_STATUS							49
+#define BTCOEX_WAKEUP_ON_DATA						50
+#define BTCOEX_DATARECEIVE							51
+#define BTCOEX_GET_MAX_AGGR_SIZE					53
+#define BTCOEX_MAX_AGGR_AVAIL_TIME					54
+#define BTCOEX_DBG_WBTIMER_INTR						55
+#define BTCOEX_DBG_SCO_SYNC                         57
+#define BTCOEX_UPLINK_QUEUED_RATE  					59
+#define BTCOEX_DBG_UPLINK_ENABLE_EOL				60
+#define BTCOEX_UPLINK_FRAME_DURATION				61
+#define BTCOEX_UPLINK_SET_EOL						62
+#define BTCOEX_DBG_EOL_EXPIRED						63
+#define BTCOEX_DBG_DATA_COMPLETE					64
+#define BTCOEX_UPLINK_QUEUED_TIMESTAMP				65
+#define BTCOEX_DBG_DATA_COMPLETE_TIME				66
+#define BTCOEX_DBG_A2DP_ROLE_IS_SLAVE               67
+#define BTCOEX_DBG_A2DP_ROLE_IS_MASTER              68
+#define BTCOEX_DBG_UPLINK_SEQ_NUM					69
+#define BTCOEX_UPLINK_AGGR_SEQ						70
+#define BTCOEX_DBG_TX_COMP_SEQ_NO					71
+#define BTCOEX_DBG_MAX_AGGR_PAUSE_STATE				72
+#define BTCOEX_DBG_ACL_TRAFFIC                      73
+#define BTCOEX_CURR_AGGR_PROP						74
+#define BTCOEX_DBG_SCO_GET_PER_TIME_DIFF 			75
+#define BTCOEX_PSPOLL_PROCESS						76
+#define BTCOEX_RETURN_FROM_MAC						77
+#define BTCOEX_FREED_REQUEUED_CNT					78
+#define BTCOEX_DBG_TOGGLE_LOW_RATES					79
+#define BTCOEX_MAC_GOES_TO_SLEEP    				80
+#define BTCOEX_DBG_A2DP_NO_SYNC                     81
+#define BTCOEX_RETURN_FROM_MAC_HOLD_Q_INFO			82
+#define BTCOEX_RETURN_FROM_MAC_AC					83
+#define BTCOEX_DBG_DTIM_RECV                        84
+#define BTCOEX_IS_PRE_UPDATE						86
+#define BTCOEX_ENQUEUED_BIT_MAP						87
+#define BTCOEX_TX_COMPLETE_FIRST_DESC_STATS			88
+#define BTCOEX_UPLINK_DESC							89
+#define BTCOEX_SCO_GET_PER_FIRST_FRM_TIMESTAMP		90
+#define BTCOEX_DBG_RECV_ACK							94
+#define BTCOEX_DBG_ADDBA_INDICATION                 95
+#define BTCOEX_TX_COMPLETE_EOL_FAILED				96
+#define BTCOEX_DBG_A2DP_USAGE_COMPLETE  			97
+#define BTCOEX_DBG_A2DP_STOMP_FOR_BCN_HANDLER		98
+#define BTCOEX_DBG_A2DP_SYNC_INTR                   99
+#define BTCOEX_DBG_A2DP_STOMP_FOR_BCN_RECEPTION	   100
+#define BTCOEX_FORM_AGGR_CURR_AGGR				   101
+#define BTCOEX_DBG_TOGGLE_A2DP_BURST_CNT           102
+#define BTCOEX_DBG_BT_TRAFFIC   				   103
+#define BTCOEX_DBG_STOMP_BT_TRAFFIC 			   104
+#define BTCOEX_RECV_NULL                           105
+#define BTCOEX_DBG_A2DP_MASTER_BT_END			   106
+#define BTCOEX_DBG_A2DP_BT_START				   107
+#define BTCOEX_DBG_A2DP_SLAVE_BT_END			   108
+#define BTCOEX_DBG_A2DP_STOMP_BT				   109
+#define BTCOEX_DBG_GO_TO_SLEEP					   110
+#define BTCOEX_DBG_A2DP_PKT						   111
+#define BTCOEX_DBG_A2DP_PSPOLL_DATA_RECV		   112
+#define BTCOEX_DBG_A2DP_NULL					   113
+#define BTCOEX_DBG_UPLINK_DATA					   114
+#define BTCOEX_DBG_A2DP_STOMP_LOW_PRIO_NULL		   115
+#define BTCOEX_DBG_ADD_BA_RESP_TIMEOUT			   116
+#define BTCOEX_DBG_TXQ_STATE					   117
+#define BTCOEX_DBG_ALLOW_SCAN					   118
+#define BTCOEX_DBG_SCAN_REQUEST					   119
+#define BTCOEX_A2DP_SLEEP						   127
+#define BTCOEX_DBG_DATA_ACTIV_TIMEOUT			   128
+#define BTCOEX_DBG_SWITCH_TO_PSPOLL_ON_MODE		   129
+#define BTCOEX_DBG_SWITCH_TO_PSPOLL_OFF_MODE 	   130
+#define BTCOEX_DATARECEIVE_AGGR					   131
+#define BTCOEX_DBG_DATA_RECV_SLEEPING_PENDING	   132
+#define BTCOEX_DBG_DATARESP_TIMEOUT				   133
+#define BTCOEX_BDG_BMISS						   134
+#define BTCOEX_DBG_DATA_RECV_WAKEUP_TIM			   135
+#define BTCOEX_DBG_SECOND_BMISS					   136
+#define BTCOEX_DBG_SET_WLAN_STATE				   138
+#define BTCOEX_BDG_FIRST_BMISS					   139
+#define BTCOEX_DBG_A2DP_CHAN_OP					   140
+#define BTCOEX_DBG_A2DP_INTR					   141
+#define BTCOEX_DBG_BT_INQUIRY					   142
+#define BTCOEX_DBG_BT_INQUIRY_DATA_FETCH		   143
+#define BTCOEX_DBG_POST_INQUIRY_FINISH			   144
+#define BTCOEX_DBG_SCO_OPT_MODE_TIMER_HANDLER	   145
+#define BTCOEX_DBG_NULL_FRAME_SLEEP				   146
+#define BTCOEX_DBG_NULL_FRAME_AWAKE				   147
+#define BTCOEX_DBG_SET_AGGR_SIZE				   152
+#define BTCOEX_DBG_TEAR_BA_TIMEOUT				   153
+#define BTCOEX_DBG_MGMT_FRAME_SEQ_NO			   154
+#define BTCOEX_DBG_SCO_STOMP_HIGH_PRI			   155
+#define BTCOEX_DBG_COLOCATED_BT_DEV				   156
+#define BTCOEX_DBG_FE_ANT_TYPE				       157
+#define BTCOEX_DBG_BT_INQUIRY_CMD				   158
+#define BTCOEX_DBG_SCO_CONFIG					   159
+#define BTCOEX_DBG_SCO_PSPOLL_CONFIG			   160
+#define BTCOEX_DBG_SCO_OPTMODE_CONFIG		       161
+#define BTCOEX_DBG_A2DP_CONFIG				       162
+#define BTCOEX_DBG_A2DP_PSPOLL_CONFIG		       163
+#define BTCOEX_DBG_A2DP_OPTMODE_CONFIG		       164
+#define BTCOEX_DBG_ACLCOEX_CONFIG			       165
+#define BTCOEX_DBG_ACLCOEX_PSPOLL_CONFIG		   166
+#define BTCOEX_DBG_ACLCOEX_OPTMODE_CONFIG	       167
+#define BTCOEX_DBG_DEBUG_CMD					   168
+#define BTCOEX_DBG_SET_BT_OPERATING_STATUS		   169
+#define BTCOEX_DBG_GET_CONFIG					   170
+#define BTCOEX_DBG_GET_STATS					   171
+#define BTCOEX_DBG_BT_OPERATING_STATUS			   172
+#define BTCOEX_DBG_PERFORM_RECONNECT               173
+#define BTCOEX_DBG_ACL_WLAN_MED                    175
+#define BTCOEX_DBG_ACL_BT_MED                      176
+#define BTCOEX_DBG_WLAN_CONNECT                    177
+#define BTCOEX_DBG_A2DP_DUAL_START                 178
+#define BTCOEX_DBG_PMAWAKE_NOTIFY                  179
+#define BTCOEX_DBG_BEACON_SCAN_ENABLE              180
+#define BTCOEX_DBG_BEACON_SCAN_DISABLE             181
+#define BTCOEX_DBG_RX_NOTIFY                       182
+#define BTCOEX_SCO_GET_PER_SECOND_FRM_TIMESTAMP    183
+#define BTCOEX_DBG_TXQ_DETAILS                     184
+#define BTCOEX_DBG_SCO_STOMP_LOW_PRI               185
+#define BTCOEX_DBG_A2DP_FORCE_SCAN                 186
+#define BTCOEX_DBG_DTIM_STOMP_COMP                 187
+#define BTCOEX_ACL_PRESENCE_TIMER                  188
+#define BTCOEX_DBGID_DEFINITION_END
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DBGLOG_ID_H_ */
diff --git a/drivers/net/ath6kl/include/common/discovery.h b/drivers/net/ath6kl/include/common/discovery.h
new file mode 100644
index 00000000000..da1b3324506
--- /dev/null
+++ b/drivers/net/ath6kl/include/common/discovery.h
@@ -0,0 +1,75 @@
+//------------------------------------------------------------------------------
+// <copyright file="discovery.h" company="Atheros">
+//    Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+#ifndef _DISCOVERY_H_
+#define _DISCOVERY_H_
+
+/*
+ * DC_SCAN_PRIORITY is an 8-bit bitmap of the scan priority of a channel
+ */
+typedef enum {
+    DEFAULT_SCPRI = 0x01,
+    POPULAR_SCPRI = 0x02,
+    SSIDS_SCPRI   = 0x04,
+    PROF_SCPRI    = 0x08,
+} DC_SCAN_PRIORITY;
+
+/* The following search type construct can be used to manipulate the behavior of the search module based on different bits set */
+typedef enum {
+    SCAN_RESET                     = 0,
+    SCAN_ALL                       = (DEFAULT_SCPRI | POPULAR_SCPRI |  \
+                                      SSIDS_SCPRI | PROF_SCPRI),
+
+    SCAN_POPULAR                   = (POPULAR_SCPRI | SSIDS_SCPRI | PROF_SCPRI),
+    SCAN_SSIDS                     = (SSIDS_SCPRI | PROF_SCPRI),
+    SCAN_PROF_MASK                 = (PROF_SCPRI),
+    SCAN_MULTI_CHANNEL             = 0x000100,
+    SCAN_DETERMINISTIC             = 0x000200,
+    SCAN_PROFILE_MATCH_TERMINATED  = 0x000400,
+    SCAN_HOME_CHANNEL_SKIP         = 0x000800,
+    SCAN_CHANNEL_LIST_CONTINUE     = 0x001000,
+    SCAN_CURRENT_SSID_SKIP         = 0x002000,
+    SCAN_ACTIVE_PROBE_DISABLE      = 0x004000,
+    SCAN_CHANNEL_HINT_ONLY         = 0x008000,
+    SCAN_ACTIVE_CHANNELS_ONLY      = 0x010000,
+    SCAN_UNUSED1                   = 0x020000, /* unused */
+    SCAN_PERIODIC                  = 0x040000,
+    SCAN_FIXED_DURATION            = 0x080000,
+    SCAN_AP_ASSISTED               = 0x100000,
+} DC_SCAN_TYPE;
+
+typedef enum {
+    BSS_REPORTING_DEFAULT = 0x0,
+    EXCLUDE_NON_SCAN_RESULTS = 0x1, /* Exclude results outside of scan */
+} DC_BSS_REPORTING_POLICY;
+
+typedef enum {
+    DC_IGNORE_WPAx_GROUP_CIPHER = 0x01,
+    DC_PROFILE_MATCH_DONE = 0x02,
+    DC_IGNORE_AAC_BEACON = 0x04, 
+    DC_CSA_FOLLOW_BSS = 0x08,
+} DC_PROFILE_FILTER;
+
+#define DEFAULT_DC_PROFILE_FILTER   (DC_CSA_FOLLOW_BSS)
+
+#endif  /* _DISCOVERY_H_ */
diff --git a/drivers/net/ath6kl/include/common/dset_internal.h b/drivers/net/ath6kl/include/common/dset_internal.h
new file mode 100644
index 00000000000..2460f0ecf12
--- /dev/null
+++ b/drivers/net/ath6kl/include/common/dset_internal.h
@@ -0,0 +1,63 @@
+//------------------------------------------------------------------------------
+// <copyright file="dset_internal.h" company="Atheros">
+//    Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+
+#ifndef __DSET_INTERNAL_H__
+#define __DSET_INTERNAL_H__
+
+#ifndef ATH_TARGET
+#include "athstartpack.h"
+#endif
+
+/*
+ * Internal dset definitions, common for DataSet layer.
+ */
+
+#define DSET_TYPE_STANDARD      0
+#define DSET_TYPE_BPATCHED      1
+#define DSET_TYPE_COMPRESSED    2
+
+/* Dataset descriptor */
+
+typedef PREPACK struct dset_descriptor_s {
+  struct dset_descriptor_s  *next;         /* List link. NULL only at the last
+                                              descriptor */
+  A_UINT16                   id;           /* Dset ID */
+  A_UINT16                   size;         /* Dset size. */
+  void                      *DataPtr;      /* Pointer to raw data for standard
+                                              DataSet or pointer to original
+                                              dset_descriptor for patched
+                                              DataSet */
+  A_UINT32                   data_type;    /* DSET_TYPE_*, above */
+
+  void                      *AuxPtr;       /* Additional data that might
+                                              needed for data_type. For
+                                              example, pointer to patch
+                                              Dataset descriptor for BPatch. */
+} POSTPACK dset_descriptor_t;
+
+#ifndef ATH_TARGET
+#include "athendpack.h"
+#endif
+
+#endif /* __DSET_INTERNAL_H__ */
diff --git a/drivers/net/ath6kl/include/common/dsetid.h b/drivers/net/ath6kl/include/common/dsetid.h
new file mode 100644
index 00000000000..d08fdeb39ec
--- /dev/null
+++ b/drivers/net/ath6kl/include/common/dsetid.h
@@ -0,0 +1,134 @@
+//------------------------------------------------------------------------------
+// <copyright file="dsetid.h" company="Atheros">
+//    Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+
+#ifndef __DSETID_H__
+#define __DSETID_H__
+
+#ifndef ATH_TARGET
+#include "athstartpack.h"
+#endif
+
+/* Well-known DataSet IDs */
+#define DSETID_UNUSED                     0x00000000
+#define DSETID_BOARD_DATA                 0x00000001 /* Cal and board data */
+#define DSETID_REGDB                      0x00000002 /* Regulatory Database */
+#define DSETID_POWER_CONTROL              0x00000003 /* TX Pwr Lim & Ant Gain */
+#define DSETID_USER_CONFIG                0x00000004 /* User Configuration */
+
+#define DSETID_ANALOG_CONTROL_DATA_START  0x00000005
+#define DSETID_ANALOG_CONTROL_DATA_END    0x00000025
+/*
+ * Get DSETID for various reference clock speeds.
+ * For each speed there are three DataSets that correspond
+ * to the three columns of bank6 data (addr, 11a, 11b/g).
+ * This macro returns the dsetid of the first of those
+ * three DataSets.
+ */
+#define ANALOG_CONTROL_DATA_DSETID(refclk) \
+        (DSETID_ANALOG_CONTROL_DATA_START + 3*refclk)
+
+/*
+ * There are TWO STARTUP_PATCH DataSets.
+ * DSETID_STARTUP_PATCH is historical, and was applied before BMI on
+ * earlier systems.  On AR6002, it is applied after BMI, just like
+ * DSETID_STARTUP_PATCH2.
+ */
+#define DSETID_STARTUP_PATCH              0x00000026
+#define DSETID_GPIO_CONFIG_PATCH          0x00000027
+#define DSETID_WLANREGS                   0x00000028 /* override wlan regs */
+#define DSETID_STARTUP_PATCH2             0x00000029
+
+#define DSETID_WOW_CONFIG                 0x00000090 /* WoW Configuration */
+
+/* Add WHAL_INI_DATA_ID to DSETID_INI_DATA for a specific WHAL INI table. */
+#define DSETID_INI_DATA                   0x00000100
+/* Reserved for WHAL INI Tables: 0x100..0x11f */
+#define DSETID_INI_DATA_END               0x0000011f
+
+#define DSETID_VENDOR_START               0x00010000 /* Vendor-defined DataSets */
+
+#define DSETID_INDEX_END                  0xfffffffe /* Reserved to indicate the
+                                                        end of a memory-based
+                                                        DataSet Index */
+#define DSETID_INDEX_FREE                 0xffffffff /* An unused index entry */
+
+/* 
+ * PATCH DataSet format:
+ * A list of patches, terminated by a patch with
+ * address=PATCH_END.
+ *
+ * This allows for patches to be stored in flash.
+ */
+PREPACK struct patch_s {
+    A_UINT32 *address;
+    A_UINT32  data;
+} POSTPACK ;
+
+/*
+ * Skip some patches.  Can be used to erase a single patch in a
+ * patch DataSet without having to re-write the DataSet.  May
+ * also be used to embed information for use by subsequent
+ * patch code.  The "data" in a PATCH_SKIP tells how many
+ * bytes of length "patch_s" to skip.
+ */
+#define PATCH_SKIP      ((A_UINT32 *)0x00000000)
+
+/*
+ * Execute code at the address specified by "data".
+ * The address of the patch structure is passed as
+ * the one parameter.
+ */
+#define PATCH_CODE_ABS  ((A_UINT32 *)0x00000001)
+
+/*
+ * Same as PATCH_CODE_ABS, but treat "data" as an
+ * offset from the start of the patch word.
+ */
+#define PATCH_CODE_REL  ((A_UINT32 *)0x00000002)
+
+/* Mark the end of this patch DataSet. */
+#define PATCH_END       ((A_UINT32 *)0xffffffff)
+
+/*
+ * A DataSet which contains a Binary Patch to some other DataSet
+ * uses the original dsetid with the DSETID_BPATCH_FLAG bit set.
+ * Such a BPatch DataSet consists of BPatch metadata followed by
+ * the bdiff bytes.  BPatch metadata consists of a single 32-bit
+ * word that contains the size of the BPatched final image.
+ *
+ * To create a suitable bdiff DataSet, use bdiff in host/tools/bdiff
+ * to create "diffs":
+ *  bdiff -q -O -nooldmd5 -nonewmd5 -d ORIGfile NEWfile diffs
+ * Then add BPatch metadata to the start of "diffs".
+ *
+ * NB: There are some implementation-induced restrictions
+ * on which DataSets can be BPatched.
+ */
+#define DSETID_BPATCH_FLAG                0x80000000
+
+#ifndef ATH_TARGET
+#include "athendpack.h"
+#endif
+
+#endif /* __DSETID_H__ */
diff --git a/drivers/net/ath6kl/include/common/epping_test.h b/drivers/net/ath6kl/include/common/epping_test.h
new file mode 100644
index 00000000000..f8aeb3f657e
--- /dev/null
+++ b/drivers/net/ath6kl/include/common/epping_test.h
@@ -0,0 +1,120 @@
+//------------------------------------------------------------------------------
+// Copyright (c) 2009-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//
+
+/* This file contains shared definitions for the host/target endpoint ping test */
+
+#ifndef EPPING_TEST_H_
+#define EPPING_TEST_H_
+
+#ifndef ATH_TARGET
+#include "athstartpack.h"
+#endif
+
+    /* alignment to 4-bytes */
+#define EPPING_ALIGNMENT_PAD  (((sizeof(HTC_FRAME_HDR) + 3) & (~0x3)) - sizeof(HTC_FRAME_HDR))
+
+#ifndef A_OFFSETOF
+#define A_OFFSETOF(type,field) (int)(&(((type *)NULL)->field))
+#endif
+
+#define EPPING_RSVD_FILL                  0xCC
+
+#define HCI_RSVD_EXPECTED_PKT_TYPE_RECV_OFFSET  7 
+  
+typedef PREPACK struct {    
+    A_UINT8     _HCIRsvd[8];           /* reserved for HCI packet header (GMBOX) testing */
+    A_UINT8     StreamEcho_h;          /* stream no. to echo this packet on (filled by host) */
+    A_UINT8     StreamEchoSent_t;      /* stream no. packet was echoed to (filled by target)
+                                          When echoed: StreamEchoSent_t == StreamEcho_h */
+    A_UINT8     StreamRecv_t;          /* stream no. that target received this packet on (filled by target) */
+    A_UINT8     StreamNo_h;            /* stream number to send on (filled by host) */   
+    A_UINT8     Magic_h[4];            /* magic number to filter for this packet on the host*/
+    A_UINT8     _rsvd[6];              /* reserved fields that must be set to a "reserved" value
+                                          since this packet maps to a 14-byte ethernet frame we want 
+                                          to make sure ethertype field is set to something unknown */
+                                          
+    A_UINT8     _pad[2];               /* padding for alignment */                      
+    A_UINT8     TimeStamp[8];          /* timestamp of packet (host or target) */
+    A_UINT32    HostContext_h;         /* 4 byte host context, target echos this back */
+    A_UINT32    SeqNo;                 /* sequence number (set by host or target) */   
+    A_UINT16    Cmd_h;                 /* ping command (filled by host) */  
+    A_UINT16    CmdFlags_h;            /* optional flags */
+    A_UINT8     CmdBuffer_h[8];        /* buffer for command (host -> target) */
+    A_UINT8     CmdBuffer_t[8];        /* buffer for command (target -> host) */  
+    A_UINT16    DataLength;            /* length of data */
+    A_UINT16    DataCRC;               /* 16 bit CRC of data */
+    A_UINT16    HeaderCRC;             /* header CRC (fields : StreamNo_h to end, minus HeaderCRC) */                       
+} POSTPACK EPPING_HEADER;
+
+#define EPPING_PING_MAGIC_0               0xAA
+#define EPPING_PING_MAGIC_1               0x55
+#define EPPING_PING_MAGIC_2               0xCE
+#define EPPING_PING_MAGIC_3               0xEC
+
+
+
+#define IS_EPPING_PACKET(pPkt)   (((pPkt)->Magic_h[0] == EPPING_PING_MAGIC_0) && \
+                                  ((pPkt)->Magic_h[1] == EPPING_PING_MAGIC_1) && \
+                                  ((pPkt)->Magic_h[2] == EPPING_PING_MAGIC_2) && \
+                                  ((pPkt)->Magic_h[3] == EPPING_PING_MAGIC_3))
+
+#define SET_EPPING_PACKET_MAGIC(pPkt) { (pPkt)->Magic_h[0] = EPPING_PING_MAGIC_0; \
+                                        (pPkt)->Magic_h[1] = EPPING_PING_MAGIC_1; \
+                                        (pPkt)->Magic_h[2] = EPPING_PING_MAGIC_2; \
+                                        (pPkt)->Magic_h[3] = EPPING_PING_MAGIC_3;}
+                                                                            
+#define CMD_FLAGS_DATA_CRC            (1 << 0)  /* DataCRC field is valid */
+#define CMD_FLAGS_DELAY_ECHO          (1 << 1)  /* delay the echo of the packet */
+#define CMD_FLAGS_NO_DROP             (1 << 2)  /* do not drop at HTC layer no matter what the stream is */
+
+#define IS_EPING_PACKET_NO_DROP(pPkt)  ((pPkt)->CmdFlags_h & CMD_FLAGS_NO_DROP)
+
+#define EPPING_CMD_ECHO_PACKET          1   /* echo packet test */
+#define EPPING_CMD_RESET_RECV_CNT       2   /* reset recv count */
+#define EPPING_CMD_CAPTURE_RECV_CNT     3   /* fetch recv count, 4-byte count returned in CmdBuffer_t */
+#define EPPING_CMD_NO_ECHO              4   /* non-echo packet test (tx-only) */
+#define EPPING_CMD_CONT_RX_START        5   /* continous RX packets, parameters are in CmdBuffer_h */
+#define EPPING_CMD_CONT_RX_STOP         6   /* stop continuous RX packet transmission */
+
+    /* test command parameters may be no more than 8 bytes */
+typedef PREPACK struct {    
+    A_UINT16  BurstCnt;       /* number of packets to burst together (for HTC 2.1 testing) */
+    A_UINT16  PacketLength;   /* length of packet to generate including header */      
+    A_UINT16  Flags;          /* flags */
+
+#define EPPING_CONT_RX_DATA_CRC     (1 << 0)  /* Add CRC to all data */
+#define EPPING_CONT_RX_RANDOM_DATA  (1 << 1)  /* randomize the data pattern */
+#define EPPING_CONT_RX_RANDOM_LEN   (1 << 2)  /* randomize the packet lengths */          
+} POSTPACK EPPING_CONT_RX_PARAMS;
+
+#define EPPING_HDR_CRC_OFFSET    A_OFFSETOF(EPPING_HEADER,StreamNo_h)
+#define EPPING_HDR_BYTES_CRC     (sizeof(EPPING_HEADER) - EPPING_HDR_CRC_OFFSET - (sizeof(A_UINT16)))
+
+#define HCI_TRANSPORT_STREAM_NUM  16  /* this number is higher than the define WMM AC classes so we
+                                         can use this to distinguish packets */
+
+#ifndef ATH_TARGET
+#include "athendpack.h"
+#endif
+    
+    
+#endif /*EPPING_TEST_H_*/
diff --git a/drivers/net/ath6kl/include/common/gmboxif.h b/drivers/net/ath6kl/include/common/gmboxif.h
new file mode 100644
index 00000000000..4d8d85fd2e7
--- /dev/null
+++ b/drivers/net/ath6kl/include/common/gmboxif.h
@@ -0,0 +1,78 @@
+//------------------------------------------------------------------------------
+// Copyright (c) 2009-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+#ifndef __GMBOXIF_H__
+#define __GMBOXIF_H__
+
+#ifndef ATH_TARGET
+#include "athstartpack.h"
+#endif
+
+/* GMBOX interface definitions */
+    
+#define AR6K_GMBOX_CREDIT_COUNTER       1   /* we use credit counter 1 to track credits */
+#define AR6K_GMBOX_CREDIT_SIZE_COUNTER  2   /* credit counter 2 is used to pass the size of each credit */
+
+
+    /* HCI UART transport definitions when used over GMBOX interface */
+#define HCI_UART_COMMAND_PKT 0x01
+#define HCI_UART_ACL_PKT     0x02
+#define HCI_UART_SCO_PKT     0x03
+#define HCI_UART_EVENT_PKT   0x04
+
+    /* definitions for BT HCI packets */
+typedef PREPACK struct {
+    A_UINT16 Flags_ConnHandle;
+    A_UINT16 Length;
+} POSTPACK BT_HCI_ACL_HEADER;
+
+typedef PREPACK struct {
+    A_UINT16 Flags_ConnHandle;
+    A_UINT8  Length;
+} POSTPACK BT_HCI_SCO_HEADER;
+
+typedef PREPACK struct {
+    A_UINT16 OpCode;
+    A_UINT8  ParamLength;
+} POSTPACK BT_HCI_COMMAND_HEADER;
+
+typedef PREPACK struct {
+    A_UINT8  EventCode;
+    A_UINT8  ParamLength;
+} POSTPACK BT_HCI_EVENT_HEADER;
+
+/* MBOX host interrupt signal assignments */
+
+#define MBOX_SIG_HCI_BRIDGE_MAX      8
+#define MBOX_SIG_HCI_BRIDGE_BT_ON    0
+#define MBOX_SIG_HCI_BRIDGE_BT_OFF   1
+#define MBOX_SIG_HCI_BRIDGE_BAUD_SET 2
+#define MBOX_SIG_HCI_BRIDGE_PWR_SAV_ON    3
+#define MBOX_SIG_HCI_BRIDGE_PWR_SAV_OFF   4
+
+
+#ifndef ATH_TARGET
+#include "athendpack.h"
+#endif
+
+#endif /* __GMBOXIF_H__ */
+
diff --git a/drivers/net/ath6kl/include/common/gpio.h b/drivers/net/ath6kl/include/common/gpio.h
new file mode 100644
index 00000000000..f7230667dd6
--- /dev/null
+++ b/drivers/net/ath6kl/include/common/gpio.h
@@ -0,0 +1,45 @@
+//------------------------------------------------------------------------------
+// Copyright (c) 2005-2010 Atheros Corporation.  All rights reserved.
+//
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//
+// Author(s): ="Atheros"
+//------------------------------------------------------------------------------
+
+#define AR6001_GPIO_PIN_COUNT 18
+#define AR6002_GPIO_PIN_COUNT 18
+#define AR6003_GPIO_PIN_COUNT 28
+
+/*
+ * Possible values for WMIX_GPIO_SET_REGISTER_CMDID.
+ * NB: These match hardware order, so that addresses can
+ * easily be computed.
+ */
+#define GPIO_ID_OUT             0x00000000
+#define GPIO_ID_OUT_W1TS        0x00000001
+#define GPIO_ID_OUT_W1TC        0x00000002
+#define GPIO_ID_ENABLE          0x00000003
+#define GPIO_ID_ENABLE_W1TS     0x00000004
+#define GPIO_ID_ENABLE_W1TC     0x00000005
+#define GPIO_ID_IN              0x00000006
+#define GPIO_ID_STATUS          0x00000007
+#define GPIO_ID_STATUS_W1TS     0x00000008
+#define GPIO_ID_STATUS_W1TC     0x00000009
+#define GPIO_ID_PIN0            0x0000000a
+#define GPIO_ID_PIN(n)          (GPIO_ID_PIN0+(n))
+
+#define GPIO_LAST_REGISTER_ID   GPIO_ID_PIN(17)
+#define GPIO_ID_NONE            0xffffffff
diff --git a/drivers/net/ath6kl/include/common/htc.h b/drivers/net/ath6kl/include/common/htc.h
new file mode 100644
index 00000000000..f96cf7db7e0
--- /dev/null
+++ b/drivers/net/ath6kl/include/common/htc.h
@@ -0,0 +1,236 @@
+//------------------------------------------------------------------------------
+// <copyright file="htc.h" company="Atheros">
+//    Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+#ifndef __HTC_H__
+#define __HTC_H__
+
+#ifndef ATH_TARGET
+#include "athstartpack.h"
+#endif
+
+#define A_OFFSETOF(type,field) (unsigned long)(&(((type *)NULL)->field))
+
+#define ASSEMBLE_UNALIGNED_UINT16(p,highbyte,lowbyte) \
+        (((A_UINT16)(((A_UINT8 *)(p))[(highbyte)])) << 8 | (A_UINT16)(((A_UINT8 *)(p))[(lowbyte)]))
+        
+/* alignment independent macros (little-endian) to fetch UINT16s or UINT8s from a 
+ * structure using only the type and field name.
+ * Use these macros if there is the potential for unaligned buffer accesses. */
+#define A_GET_UINT16_FIELD(p,type,field) \
+    ASSEMBLE_UNALIGNED_UINT16(p,\
+                              A_OFFSETOF(type,field) + 1, \
+                              A_OFFSETOF(type,field))
+
+#define A_SET_UINT16_FIELD(p,type,field,value) \
+{                                              \
+    ((A_UINT8 *)(p))[A_OFFSETOF(type,field)] = (A_UINT8)(value);        \
+    ((A_UINT8 *)(p))[A_OFFSETOF(type,field) + 1] = (A_UINT8)((value) >> 8); \
+}
+  
+#define A_GET_UINT8_FIELD(p,type,field) \
+            ((A_UINT8 *)(p))[A_OFFSETOF(type,field)]
+            
+#define A_SET_UINT8_FIELD(p,type,field,value) \
+    ((A_UINT8 *)(p))[A_OFFSETOF(type,field)] = (value)
+
+/****** DANGER DANGER ***************
+ * 
+ *   The frame header length and message formats defined herein were
+ *   selected to accommodate optimal alignment for target processing.  This reduces code
+ *   size and improves performance.
+ * 
+ *   Any changes to the header length may alter the alignment and cause exceptions
+ *   on the target. When adding to the message structures insure that fields are
+ *   properly aligned.
+ * 
+ */
+
+/* HTC frame header */
+typedef PREPACK struct _HTC_FRAME_HDR{
+        /* do not remove or re-arrange these fields, these are minimally required
+         * to take advantage of 4-byte lookaheads in some hardware implementations */
+    A_UINT8   EndpointID;
+    A_UINT8   Flags;
+    A_UINT16  PayloadLen;       /* length of data (including trailer) that follows the header */
+    
+    /***** end of 4-byte lookahead ****/
+    
+    A_UINT8   ControlBytes[2];
+    
+    /* message payload starts after the header */
+    
+} POSTPACK HTC_FRAME_HDR;
+
+/* frame header flags */
+
+    /* send direction */
+#define HTC_FLAGS_NEED_CREDIT_UPDATE (1 << 0)
+#define HTC_FLAGS_SEND_BUNDLE        (1 << 1)  /* start or part of bundle */
+    /* receive direction */
+#define HTC_FLAGS_RECV_UNUSED_0      (1 << 0)  /* bit 0 unused */    
+#define HTC_FLAGS_RECV_TRAILER       (1 << 1)  /* bit 1 trailer data present */
+#define HTC_FLAGS_RECV_UNUSED_2      (1 << 0)  /* bit 2 unused */
+#define HTC_FLAGS_RECV_UNUSED_3      (1 << 0)  /* bit 3 unused */
+#define HTC_FLAGS_RECV_BUNDLE_CNT_MASK (0xF0)  /* bits 7..4  */
+#define HTC_FLAGS_RECV_BUNDLE_CNT_SHIFT 4
+
+#define HTC_HDR_LENGTH  (sizeof(HTC_FRAME_HDR))
+#define HTC_MAX_TRAILER_LENGTH   255
+#define HTC_MAX_PAYLOAD_LENGTH   (4096 - sizeof(HTC_FRAME_HDR))
+
+/* HTC control message IDs */
+
+#define HTC_MSG_READY_ID                    1
+#define HTC_MSG_CONNECT_SERVICE_ID          2
+#define HTC_MSG_CONNECT_SERVICE_RESPONSE_ID 3   
+#define HTC_MSG_SETUP_COMPLETE_ID           4
+#define HTC_MSG_SETUP_COMPLETE_EX_ID        5
+
+#define HTC_MAX_CONTROL_MESSAGE_LENGTH  256
+         
+/* base message ID header */
+typedef PREPACK struct {
+    A_UINT16 MessageID;    
+} POSTPACK HTC_UNKNOWN_MSG;
+                                                     
+/* HTC ready message
+ * direction : target-to-host  */
+typedef PREPACK struct {
+    A_UINT16  MessageID;    /* ID */
+    A_UINT16  CreditCount;  /* number of credits the target can offer */       
+    A_UINT16  CreditSize;   /* size of each credit */
+    A_UINT8   MaxEndpoints; /* maximum number of endpoints the target has resources for */
+    A_UINT8   _Pad1;
+} POSTPACK HTC_READY_MSG;
+
+    /* extended HTC ready message */
+typedef PREPACK struct {
+    HTC_READY_MSG   Version2_0_Info;   /* legacy version 2.0 information at the front... */
+    /* extended information */
+    A_UINT8         HTCVersion;
+    A_UINT8         MaxMsgsPerHTCBundle;
+} POSTPACK HTC_READY_EX_MSG;
+
+#define HTC_VERSION_2P0  0x00  
+#define HTC_VERSION_2P1  0x01  /* HTC 2.1 */
+
+#define HTC_SERVICE_META_DATA_MAX_LENGTH 128
+
+/* connect service
+ * direction : host-to-target */
+typedef PREPACK struct {
+    A_UINT16  MessageID;
+    A_UINT16  ServiceID;           /* service ID of the service to connect to */       
+    A_UINT16  ConnectionFlags;     /* connection flags */
+
+#define HTC_CONNECT_FLAGS_REDUCE_CREDIT_DRIBBLE (1 << 2)  /* reduce credit dribbling when 
+                                                             the host needs credits */  
+#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_MASK             (0x3)  
+#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_FOURTH        0x0
+#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_HALF          0x1
+#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_THREE_FOURTHS     0x2
+#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_UNITY             0x3
+                                                             
+    A_UINT8   ServiceMetaLength;   /* length of meta data that follows */
+    A_UINT8   _Pad1;
+    
+    /* service-specific meta data starts after the header */
+    
+} POSTPACK HTC_CONNECT_SERVICE_MSG;
+
+/* connect response
+ * direction : target-to-host */
+typedef PREPACK struct {
+    A_UINT16  MessageID;
+    A_UINT16  ServiceID;            /* service ID that the connection request was made */
+    A_UINT8   Status;               /* service connection status */ 
+    A_UINT8   EndpointID;           /* assigned endpoint ID */
+    A_UINT16  MaxMsgSize;           /* maximum expected message size on this endpoint */
+    A_UINT8   ServiceMetaLength;    /* length of meta data that follows */
+    A_UINT8   _Pad1;               
+    
+    /* service-specific meta data starts after the header */
+    
+} POSTPACK HTC_CONNECT_SERVICE_RESPONSE_MSG;
+
+typedef PREPACK struct {
+    A_UINT16  MessageID;
+    /* currently, no other fields */
+} POSTPACK HTC_SETUP_COMPLETE_MSG;
+
+    /* extended setup completion message */
+typedef PREPACK struct {
+    A_UINT16  MessageID;
+    A_UINT32  SetupFlags;
+    A_UINT8   MaxMsgsPerBundledRecv;
+    A_UINT8   Rsvd[3];
+} POSTPACK HTC_SETUP_COMPLETE_EX_MSG;
+
+#define HTC_SETUP_COMPLETE_FLAGS_ENABLE_BUNDLE_RECV     (1 << 0)
+
+/* connect response status codes */
+#define HTC_SERVICE_SUCCESS      0  /* success */
+#define HTC_SERVICE_NOT_FOUND    1  /* service could not be found */
+#define HTC_SERVICE_FAILED       2  /* specific service failed the connect */
+#define HTC_SERVICE_NO_RESOURCES 3  /* no resources (i.e. no more endpoints) */  
+#define HTC_SERVICE_NO_MORE_EP   4  /* specific service is not allowing any more 
+                                       endpoints */
+
+/* report record IDs */
+
+#define HTC_RECORD_NULL             0
+#define HTC_RECORD_CREDITS          1
+#define HTC_RECORD_LOOKAHEAD        2
+#define HTC_RECORD_LOOKAHEAD_BUNDLE 3
+
+typedef PREPACK struct {
+    A_UINT8 RecordID;     /* Record ID */
+    A_UINT8 Length;       /* Length of record */
+} POSTPACK HTC_RECORD_HDR;
+
+typedef PREPACK struct {
+    A_UINT8 EndpointID;     /* Endpoint that owns these credits */
+    A_UINT8 Credits;        /* credits to report since last report */
+} POSTPACK HTC_CREDIT_REPORT;
+
+typedef PREPACK struct {    
+    A_UINT8 PreValid;         /* pre valid guard */
+    A_UINT8 LookAhead[4];     /* 4 byte lookahead */
+    A_UINT8 PostValid;        /* post valid guard */
+    
+   /* NOTE: the LookAhead array is guarded by a PreValid and Post Valid guard bytes.
+    * The PreValid bytes must equal the inverse of the PostValid byte */
+    
+} POSTPACK HTC_LOOKAHEAD_REPORT;
+
+typedef PREPACK struct {    
+    A_UINT8 LookAhead[4];     /* 4 byte lookahead */    
+} POSTPACK HTC_BUNDLED_LOOKAHEAD_REPORT;
+
+#ifndef ATH_TARGET
+#include "athendpack.h"
+#endif
+
+
+#endif /* __HTC_H__ */
+
diff --git a/drivers/net/ath6kl/include/common/htc_services.h b/drivers/net/ath6kl/include/common/htc_services.h
new file mode 100644
index 00000000000..fb22268a8d8
--- /dev/null
+++ b/drivers/net/ath6kl/include/common/htc_services.h
@@ -0,0 +1,52 @@
+//------------------------------------------------------------------------------
+// <copyright file="htc_services.h" company="Atheros">
+//    Copyright (c) 2007 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+#ifndef __HTC_SERVICES_H__
+#define __HTC_SERVICES_H__
+
+/* Current service IDs */
+
+typedef enum {
+    RSVD_SERVICE_GROUP  = 0,
+    WMI_SERVICE_GROUP   = 1, 
+    
+    HTC_TEST_GROUP = 254,
+    HTC_SERVICE_GROUP_LAST = 255
+}HTC_SERVICE_GROUP_IDS;
+
+#define MAKE_SERVICE_ID(group,index) \
+            (int)(((int)group << 8) | (int)(index))
+
+/* NOTE: service ID of 0x0000 is reserved and should never be used */
+#define HTC_CTRL_RSVD_SVC MAKE_SERVICE_ID(RSVD_SERVICE_GROUP,1)
+#define WMI_CONTROL_SVC   MAKE_SERVICE_ID(WMI_SERVICE_GROUP,0)
+#define WMI_DATA_BE_SVC   MAKE_SERVICE_ID(WMI_SERVICE_GROUP,1)
+#define WMI_DATA_BK_SVC   MAKE_SERVICE_ID(WMI_SERVICE_GROUP,2)
+#define WMI_DATA_VI_SVC   MAKE_SERVICE_ID(WMI_SERVICE_GROUP,3)
+#define WMI_DATA_VO_SVC   MAKE_SERVICE_ID(WMI_SERVICE_GROUP,4)
+#define WMI_MAX_SERVICES  5
+
+/* raw stream service (i.e. flash, tcmd, calibration apps) */
+#define HTC_RAW_STREAMS_SVC MAKE_SERVICE_ID(HTC_TEST_GROUP,0)
+
+#endif /*HTC_SERVICES_H_*/
diff --git a/drivers/net/ath6kl/include/common/ini_dset.h b/drivers/net/ath6kl/include/common/ini_dset.h
new file mode 100644
index 00000000000..8cf1af834bd
--- /dev/null
+++ b/drivers/net/ath6kl/include/common/ini_dset.h
@@ -0,0 +1,82 @@
+//------------------------------------------------------------------------------
+// Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+//
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//
+// Author(s): ="Atheros"
+//------------------------------------------------------------------------------
+
+#ifndef _INI_DSET_H_
+#define _INI_DSET_H_
+
+/*
+ * Each of these represents a WHAL INI table, which consists
+ * of an "address column" followed by 1 or more "value columns".
+ *
+ * Software uses the base WHAL_INI_DATA_ID+column to access a
+ * DataSet that holds a particular column of data.
+ */
+typedef enum {
+#if defined(AR6002_REV4) || defined(AR6003)
+/* Add these definitions for compatability  */
+#define WHAL_INI_DATA_ID_BB_RFGAIN_LNA1 WHAL_INI_DATA_ID_BB_RFGAIN
+#define WHAL_INI_DATA_ID_BB_RFGAIN_LNA2 WHAL_INI_DATA_ID_BB_RFGAIN
+    WHAL_INI_DATA_ID_NULL               =0,
+    WHAL_INI_DATA_ID_MODE_SPECIFIC      =1,  /* 2,3,4,5 */
+    WHAL_INI_DATA_ID_COMMON             =6,  /* 7 */
+    WHAL_INI_DATA_ID_BB_RFGAIN          =8,  /* 9,10 */
+#ifdef FPGA
+    WHAL_INI_DATA_ID_ANALOG_BANK0       =11, /* 12 */
+    WHAL_INI_DATA_ID_ANALOG_BANK1       =13, /* 14 */
+    WHAL_INI_DATA_ID_ANALOG_BANK2       =15, /* 16 */
+    WHAL_INI_DATA_ID_ANALOG_BANK3       =17, /* 18, 19 */
+    WHAL_INI_DATA_ID_ANALOG_BANK6       =20, /* 21,22 */
+    WHAL_INI_DATA_ID_ANALOG_BANK7       =23, /* 24 */
+    WHAL_INI_DATA_ID_ADDAC              =25, /* 26 */
+#else
+    WHAL_INI_DATA_ID_ANALOG_COMMON      =11, /* 12 */ 
+    WHAL_INI_DATA_ID_ANALOG_MODE_SPECIFIC=13, /* 14,15 */ 
+    WHAL_INI_DATA_ID_ANALOG_BANK6       =16, /* 17,18 */
+    WHAL_INI_DATA_ID_MODE_OVERRIDES     =19, /* 20,21,22,23 */
+    WHAL_INI_DATA_ID_COMMON_OVERRIDES   =24, /* 25 */
+    WHAL_INI_DATA_ID_ANALOG_OVERRIDES   =26, /* 27,28 */
+#endif /* FPGA */
+#else
+    WHAL_INI_DATA_ID_NULL               =0,
+    WHAL_INI_DATA_ID_MODE_SPECIFIC      =1,  /* 2,3 */
+    WHAL_INI_DATA_ID_COMMON             =4,  /* 5 */
+    WHAL_INI_DATA_ID_BB_RFGAIN          =6,  /* 7,8 */
+#define WHAL_INI_DATA_ID_BB_RFGAIN_LNA1 WHAL_INI_DATA_ID_BB_RFGAIN
+    WHAL_INI_DATA_ID_ANALOG_BANK1       =9,  /* 10 */
+    WHAL_INI_DATA_ID_ANALOG_BANK2       =11, /* 12 */
+    WHAL_INI_DATA_ID_ANALOG_BANK3       =13, /* 14, 15 */
+    WHAL_INI_DATA_ID_ANALOG_BANK6       =16, /* 17, 18 */
+    WHAL_INI_DATA_ID_ANALOG_BANK7       =19, /* 20 */
+    WHAL_INI_DATA_ID_MODE_OVERRIDES     =21, /* 22,23 */
+    WHAL_INI_DATA_ID_COMMON_OVERRIDES   =24, /* 25 */
+    WHAL_INI_DATA_ID_ANALOG_OVERRIDES   =26, /* 27,28 */
+    WHAL_INI_DATA_ID_BB_RFGAIN_LNA2     =29, /* 30,31 */
+#endif
+    WHAL_INI_DATA_ID_MAX                =31
+} WHAL_INI_DATA_ID;
+
+typedef PREPACK struct {
+    A_UINT16 freqIndex; // 1 - A mode 2 - B or G mode 0 - common
+    A_UINT16 offset;
+    A_UINT32 newValue;
+} POSTPACK INI_DSET_REG_OVERRIDE;
+
+#endif
diff --git a/drivers/net/ath6kl/include/common/pkt_log.h b/drivers/net/ath6kl/include/common/pkt_log.h
new file mode 100644
index 00000000000..331cc04edad
--- /dev/null
+++ b/drivers/net/ath6kl/include/common/pkt_log.h
@@ -0,0 +1,45 @@
+//------------------------------------------------------------------------------
+// Copyright (c) 2005-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+#ifndef __PKT_LOG_H__
+#define __PKT_LOG_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* Pkt log info */
+typedef PREPACK struct pkt_log_t {
+    struct info_t {
+        A_UINT16    st;
+        A_UINT16    end;
+        A_UINT16    cur;
+    }info[4096];
+    A_UINT16    last_idx;
+}POSTPACK PACKET_LOG;
+
+
+#ifdef __cplusplus
+}
+#endif
+#endif  /* __PKT_LOG_H__ */
diff --git a/drivers/net/ath6kl/include/common/regDb.h b/drivers/net/ath6kl/include/common/regDb.h
new file mode 100644
index 00000000000..f8245f10452
--- /dev/null
+++ b/drivers/net/ath6kl/include/common/regDb.h
@@ -0,0 +1,29 @@
+//------------------------------------------------------------------------------
+// Copyright (c) 2005-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+#ifndef __REG_DB_H__
+#define __REG_DB_H__
+
+#include "./regulatory/reg_dbschema.h"
+#include "./regulatory/reg_dbvalues.h"
+
+#endif  /* __REG_DB_H__ */
diff --git a/drivers/net/ath6kl/include/common/regdump.h b/drivers/net/ath6kl/include/common/regdump.h
new file mode 100644
index 00000000000..ff79b4846e6
--- /dev/null
+++ b/drivers/net/ath6kl/include/common/regdump.h
@@ -0,0 +1,59 @@
+//------------------------------------------------------------------------------
+// <copyright file="regdump.h" company="Atheros">
+//    Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+#ifndef __REGDUMP_H__
+#define __REGDUMP_H__
+
+#ifndef ATH_TARGET
+#include "athstartpack.h"
+#endif
+
+#if defined(AR6001)
+#include "AR6001/AR6001_regdump.h"
+#endif
+#if defined(AR6002)
+#include "AR6002/AR6002_regdump.h"
+#endif
+
+#if !defined(__ASSEMBLER__)
+/*
+ * Target CPU state at the time of failure is reflected
+ * in a register dump, which the Host can fetch through
+ * the diagnostic window.
+ */
+PREPACK struct register_dump_s {
+    A_UINT32 target_id;               /* Target ID */
+    A_UINT32 assline;                 /* Line number (if assertion failure) */
+    A_UINT32 pc;                      /* Program Counter at time of exception */
+    A_UINT32 badvaddr;                /* Virtual address causing exception */
+    CPU_exception_frame_t exc_frame;  /* CPU-specific exception info */
+
+    /* Could copy top of stack here, too.... */
+} POSTPACK;
+#endif /* __ASSEMBLER__ */
+
+#ifndef ATH_TARGET
+#include "athendpack.h"
+#endif
+
+#endif /* __REGDUMP_H__ */
diff --git a/drivers/net/ath6kl/include/common/regulatory/reg_dbschema.h b/drivers/net/ath6kl/include/common/regulatory/reg_dbschema.h
new file mode 100644
index 00000000000..c6844d69fe4
--- /dev/null
+++ b/drivers/net/ath6kl/include/common/regulatory/reg_dbschema.h
@@ -0,0 +1,237 @@
+//------------------------------------------------------------------------------
+// Copyright (c) 2005-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+#ifndef __REG_DBSCHEMA_H__
+#define __REG_DBSCHEMA_H__
+
+/*
+ * This file describes the regulatory DB schema, which is common between the
+ * 'generator' and 'parser'. The 'generator' runs on a host(typically a x86
+ * Linux) and spits outs two binary files, which follow the DB file
+ * format(described below). The resultant output "regulatoryData_AG.bin"
+ * is binary file which has information regarding A and G regulatory
+ * information, while the "regulatoryData_G.bin" consists of G-ONLY regulatory
+ * information. This binary file is parsed in the target for extracting
+ * regulatory information.
+ * 
+ * The DB values used to populate the regulatory DB are defined in
+ * reg_dbvalues.h
+ *
+ */
+
+/* Binary data file - Representation of Regulatory DB*/
+#define REG_DATA_FILE_AG    "./regulatoryData_AG.bin"
+#define REG_DATA_FILE_G     "./regulatoryData_G.bin"
+
+
+/* Table tags used to encode different tables in the database */
+enum data_tags_t{
+    REG_DMN_PAIR_MAPPING_TAG = 0,
+    REG_COUNTRY_CODE_TO_ENUM_RD_TAG,
+    REG_DMN_FREQ_BAND_regDmn5GhzFreq_TAG,
+    REG_DMN_FREQ_BAND_regDmn2Ghz11_BG_Freq_TAG,
+    REG_DOMAIN_TAG,
+    MAX_DB_TABLE_TAGS
+    };
+
+
+
+/*
+ ****************************************************************************
+ * Regulatory DB file format :
+ * 4-bytes : "RGDB" (Magic Key)
+ * 4-bytes : version (Default is 5379(my extn))
+ * 4-bytes : length of file
+ * dbType(4)
+ * TAG(4)
+ * Entries(1)entrySize(1)searchType(1)reserved[3]tableSize(2)"0xdeadbeef"(4)struct_data....
+ * TAG(4)
+ * Entries(1)entrySize(1)searchType(1)reserved[3]tableSize(2)"0xdeadbeef"(4)struct_data....
+ * TAG(4)
+ * Entries(1)entrySize(1)searchType(1)reserved[3]tableSize(2)"0xdeadbeef"(4)struct_data....
+ * ...
+ * ...
+ ****************************************************************************
+ *
+ */
+
+/*
+ * Length of the file would be filled in when the file is created and
+ * it would include the header size.
+ */
+
+#define REG_DB_KEY          "RGDB" /* Should be EXACTLY 4-bytes */
+#define REG_DB_VER           7802  /* Between 0-9999 */
+/*  REG_DB_VER history in reverse chronological order: 
+ *  7802: 78 (ASCII code of N) + 02 (minor version number) - updated 10/21/09 
+ *  7801: 78 (ASCII code of N) + 01 (minor version number, increment on further changes)
+ *  1178: '11N' = 11 + ASCII code of N(78)
+ *  5379: initial version, no 11N support
+ */
+#define MAGIC_KEY_OFFSET    0
+#define VERSION_OFFSET      4
+#define FILE_SZ_OFFSET      8
+#define DB_TYPE_OFFSET      12
+
+#define MAGIC_KEY_SZ        4
+#define VERSION_SZ          4
+#define FILE_SZ_SZ          4
+#define DB_TYPE_SZ          4
+#define DB_TAG_SZ           4
+
+#define REGDB_GET_MAGICKEY(x)     ((char *)x + MAGIC_KEY_OFFSET) 
+#define REGDB_GET_VERSION(x)      ((char *)x + VERSION_OFFSET)
+#define REGDB_GET_FILESIZE(x)     *((unsigned int *)((char *)x + FILE_SZ_OFFSET))
+#define REGDB_GET_DBTYPE(x)       *((char *)x + DB_TYPE_OFFSET)
+
+#define REGDB_SET_FILESIZE(x, sz_) *((unsigned int *)((char *)x + FILE_SZ_OFFSET)) = (sz_)
+#define REGDB_IS_EOF(cur, begin)  ( REGDB_GET_FILESIZE(begin) > ((cur) - (begin)) )
+
+
+/* A Table can be search based on key as a parameter or accessed directly
+ * by giving its index in to the table.
+ */
+enum searchType {
+    KEY_BASED_TABLE_SEARCH = 1,
+    INDEX_BASED_TABLE_ACCESS
+    };
+
+
+/* Data is organised as different tables. There is a Master table, which
+ * holds information regarding all the tables. It does not have any
+ * knowledge about the attributes of the table it is holding
+ * but has external view of the same(for ex, how many entries, record size,
+ * how to search the table, total table size and reference to the data
+ * instance of table).
+ */
+typedef PREPACK struct dbMasterTable_t {    /* Hold ptrs to Table data structures */
+    A_UCHAR     numOfEntries;
+    A_CHAR      entrySize;      /* Entry size per table row */
+    A_CHAR      searchType;     /* Index based access or key based */
+    A_CHAR      reserved[3];    /* for alignment */
+    A_UINT16    tableSize;      /* Size of this table */
+    A_CHAR      *dataPtr;       /* Ptr to the actual Table */
+} POSTPACK dbMasterTable;    /* Master table - table of tables */
+
+
+/* used to get the number of rows in a table */
+#define REGDB_NUM_OF_ROWS(a)    (sizeof (a) / sizeof (a[0]))
+
+/* 
+ * Used to set the RegDomain bitmask which chooses which frequency
+ * band specs are used.
+ */
+
+#define BMLEN 2         /* Use 2 32-bit uint for channel bitmask */
+#define BMZERO {0,0}    /* BMLEN zeros */
+
+#define BM(_fa, _fb, _fc, _fd, _fe, _ff, _fg, _fh) \
+      {((((_fa >= 0) && (_fa < 32)) ? (((A_UINT32) 1) << _fa) : 0) | \
+    (((_fb >= 0) && (_fb < 32)) ? (((A_UINT32) 1) << _fb) : 0) | \
+    (((_fc >= 0) && (_fc < 32)) ? (((A_UINT32) 1) << _fc) : 0) | \
+    (((_fd >= 0) && (_fd < 32)) ? (((A_UINT32) 1) << _fd) : 0) | \
+    (((_fe >= 0) && (_fe < 32)) ? (((A_UINT32) 1) << _fe) : 0) | \
+    (((_ff >= 0) && (_ff < 32)) ? (((A_UINT32) 1) << _ff) : 0) | \
+    (((_fg >= 0) && (_fg < 32)) ? (((A_UINT32) 1) << _fg) : 0) | \
+    (((_fh >= 0) && (_fh < 32)) ? (((A_UINT32) 1) << _fh) : 0)), \
+       ((((_fa > 31) && (_fa < 64)) ? (((A_UINT32) 1) << (_fa - 32)) : 0) | \
+        (((_fb > 31) && (_fb < 64)) ? (((A_UINT32) 1) << (_fb - 32)) : 0) | \
+        (((_fc > 31) && (_fc < 64)) ? (((A_UINT32) 1) << (_fc - 32)) : 0) | \
+        (((_fd > 31) && (_fd < 64)) ? (((A_UINT32) 1) << (_fd - 32)) : 0) | \
+        (((_fe > 31) && (_fe < 64)) ? (((A_UINT32) 1) << (_fe - 32)) : 0) | \
+        (((_ff > 31) && (_ff < 64)) ? (((A_UINT32) 1) << (_ff - 32)) : 0) | \
+        (((_fg > 31) && (_fg < 64)) ? (((A_UINT32) 1) << (_fg - 32)) : 0) | \
+        (((_fh > 31) && (_fh < 64)) ? (((A_UINT32) 1) << (_fh - 32)) : 0))}
+
+
+/*
+ * THE following table is the mapping of regdomain pairs specified by
+ * a regdomain value to the individual unitary reg domains
+ */
+
+typedef PREPACK struct reg_dmn_pair_mapping {
+    A_UINT16 regDmnEnum;    /* 16 bit reg domain pair */
+    A_UINT16 regDmn5GHz;    /* 5GHz reg domain */
+    A_UINT16 regDmn2GHz;    /* 2GHz reg domain */
+    A_UINT8  flags5GHz;     /* Requirements flags (AdHoc disallow etc) */
+    A_UINT8  flags2GHz;     /* Requirements flags (AdHoc disallow etc) */
+    A_UINT32 pscanMask;     /* Passive Scan flags which can override unitary domain passive scan
+                                   flags.  This value is used as a mask on the unitary flags*/
+} POSTPACK REG_DMN_PAIR_MAPPING;
+
+#define OFDM_YES (1 << 0)
+#define OFDM_NO  (0 << 0)
+#define MCS_HT20_YES   (1 << 1)
+#define MCS_HT20_NO    (0 << 1)
+#define MCS_HT40_A_YES (1 << 2)
+#define MCS_HT40_A_NO  (0 << 2)
+#define MCS_HT40_G_YES (1 << 3)
+#define MCS_HT40_G_NO  (0 << 3)
+
+typedef PREPACK struct {
+    A_UINT16    countryCode;       
+    A_UINT16    regDmnEnum;
+    A_CHAR      isoName[3];
+    A_CHAR      allowMode;  /* what mode is allowed - bit 0: OFDM; bit 1: MCS_HT20; bit 2: MCS_HT40_A; bit 3: MCS_HT40_G */
+} POSTPACK COUNTRY_CODE_TO_ENUM_RD;
+
+/* lower 16 bits of ht40ChanMask */
+#define NO_FREQ_HT40    0x0     /* no freq is HT40 capable */
+#define F1_TO_F4_HT40   0xF     /* freq 1 to 4 in the block is ht40 capable */
+#define F2_TO_F3_HT40   0x6     /* freq 2 to 3 in the block is ht40 capable */
+#define F1_TO_F10_HT40  0x3FF   /* freq 1 to 10 in the block is ht40 capable */
+#define F3_TO_F11_HT40  0x7FC   /* freq 3 to 11 in the block is ht40 capable */
+#define F3_TO_F9_HT40   0x1FC   /* freq 3 to 9 in the block is ht40 capable */
+#define F1_TO_F8_HT40   0xFF    /* freq 1 to 8 in the block is ht40 capable */
+#define F1_TO_F4_F9_TO_F10_HT40   0x30F    /* freq 1 to 4, 9 to 10 in the block is ht40 capable */
+
+/* upper 16 bits of ht40ChanMask */
+#define FREQ_HALF_RATE      0x10000
+#define FREQ_QUARTER_RATE   0x20000
+
+typedef PREPACK struct RegDmnFreqBand {
+    A_UINT16    lowChannel;     /* Low channel center in MHz */
+    A_UINT16    highChannel;    /* High Channel center in MHz */
+    A_UINT8     power;          /* Max power (dBm) for channel range */
+    A_UINT8     channelSep;     /* Channel separation within the band */
+    A_UINT8     useDfs;         /* Use DFS in the RegDomain if corresponding bit is set */
+    A_UINT8     mode;           /* Mode of operation */
+    A_UINT32    usePassScan;    /* Use Passive Scan in the RegDomain if corresponding bit is set */
+    A_UINT32    ht40ChanMask;   /* lower 16 bits: indicate which frequencies in the block is HT40 capable 
+                                   upper 16 bits: what rate (half/quarter) the channel is  */
+} POSTPACK REG_DMN_FREQ_BAND;
+
+
+
+typedef PREPACK struct regDomain {
+    A_UINT16    regDmnEnum;     /* value from EnumRd table */
+    A_UINT8     rdCTL;
+    A_UINT8     maxAntGain;
+    A_UINT8     dfsMask;        /* DFS bitmask for 5Ghz tables */
+    A_UINT8     flags;          /* Requirement flags (AdHoc disallow etc) */
+    A_UINT16    reserved;       /* for alignment */
+    A_UINT32    pscan;          /* Bitmask for passive scan */
+    A_UINT32    chan11a[BMLEN]; /* 64 bit bitmask for channel/band selection */
+    A_UINT32    chan11bg[BMLEN];/* 64 bit bitmask for channel/band selection */
+} POSTPACK REG_DOMAIN;
+
+#endif /* __REG_DBSCHEMA_H__ */
diff --git a/drivers/net/ath6kl/include/common/regulatory/reg_dbvalues.h b/drivers/net/ath6kl/include/common/regulatory/reg_dbvalues.h
new file mode 100644
index 00000000000..278f90346b5
--- /dev/null
+++ b/drivers/net/ath6kl/include/common/regulatory/reg_dbvalues.h
@@ -0,0 +1,504 @@
+//------------------------------------------------------------------------------
+// Copyright (c) 2005-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+
+#ifndef __REG_DBVALUE_H__
+#define __REG_DBVALUE_H__
+
+/*
+ * Numbering from ISO 3166
+ */
+enum CountryCode {
+    CTRY_ALBANIA              = 8,       /* Albania */
+    CTRY_ALGERIA              = 12,      /* Algeria */
+    CTRY_ARGENTINA            = 32,      /* Argentina */
+    CTRY_ARMENIA              = 51,      /* Armenia */
+    CTRY_ARUBA                = 533,     /* Aruba */
+    CTRY_AUSTRALIA            = 36,      /* Australia (for STA) */
+    CTRY_AUSTRALIA_AP         = 5000,    /* Australia (for AP) */
+    CTRY_AUSTRIA              = 40,      /* Austria */
+    CTRY_AZERBAIJAN           = 31,      /* Azerbaijan */
+    CTRY_BAHRAIN              = 48,      /* Bahrain */
+    CTRY_BANGLADESH           = 50,      /* Bangladesh */
+    CTRY_BARBADOS             = 52,      /* Barbados */
+    CTRY_BELARUS              = 112,     /* Belarus */
+    CTRY_BELGIUM              = 56,      /* Belgium */
+    CTRY_BELIZE               = 84,      /* Belize */
+    CTRY_BOLIVIA              = 68,      /* Bolivia */
+    CTRY_BOSNIA_HERZEGOWANIA  = 70,      /* Bosnia & Herzegowania */
+    CTRY_BRAZIL               = 76,      /* Brazil */
+    CTRY_BRUNEI_DARUSSALAM    = 96,      /* Brunei Darussalam */
+    CTRY_BULGARIA             = 100,     /* Bulgaria */
+    CTRY_CAMBODIA             = 116,     /* Cambodia */
+    CTRY_CANADA               = 124,     /* Canada (for STA) */
+    CTRY_CANADA_AP            = 5001,    /* Canada (for AP) */
+    CTRY_CHILE                = 152,     /* Chile */
+    CTRY_CHINA                = 156,     /* People's Republic of China */
+    CTRY_COLOMBIA             = 170,     /* Colombia */
+    CTRY_COSTA_RICA           = 188,     /* Costa Rica */
+    CTRY_CROATIA              = 191,     /* Croatia */
+    CTRY_CYPRUS               = 196,
+    CTRY_CZECH                = 203,     /* Czech Republic */
+    CTRY_DENMARK              = 208,     /* Denmark */
+    CTRY_DOMINICAN_REPUBLIC   = 214,     /* Dominican Republic */
+    CTRY_ECUADOR              = 218,     /* Ecuador */
+    CTRY_EGYPT                = 818,     /* Egypt */
+    CTRY_EL_SALVADOR          = 222,     /* El Salvador */
+    CTRY_ESTONIA              = 233,     /* Estonia */
+    CTRY_FAEROE_ISLANDS       = 234,     /* Faeroe Islands */
+    CTRY_FINLAND              = 246,     /* Finland */
+    CTRY_FRANCE               = 250,     /* France */
+    CTRY_FRANCE2              = 255,     /* France2 */
+    CTRY_GEORGIA              = 268,     /* Georgia */
+    CTRY_GERMANY              = 276,     /* Germany */
+    CTRY_GREECE               = 300,     /* Greece */
+    CTRY_GREENLAND            = 304,     /* Greenland */
+    CTRY_GRENADA              = 308,     /* Grenada */
+    CTRY_GUAM                 = 316,     /* Guam */
+    CTRY_GUATEMALA            = 320,     /* Guatemala */
+    CTRY_HAITI                = 332,     /* Haiti */
+    CTRY_HONDURAS             = 340,     /* Honduras */
+    CTRY_HONG_KONG            = 344,     /* Hong Kong S.A.R., P.R.C. */
+    CTRY_HUNGARY              = 348,     /* Hungary */
+    CTRY_ICELAND              = 352,     /* Iceland */
+    CTRY_INDIA                = 356,     /* India */
+    CTRY_INDONESIA            = 360,     /* Indonesia */
+    CTRY_IRAN                 = 364,     /* Iran */
+    CTRY_IRAQ                 = 368,     /* Iraq */
+    CTRY_IRELAND              = 372,     /* Ireland */
+    CTRY_ISRAEL               = 376,     /* Israel */
+    CTRY_ITALY                = 380,     /* Italy */
+    CTRY_JAMAICA              = 388,     /* Jamaica */
+    CTRY_JAPAN                = 392,     /* Japan */
+    CTRY_JAPAN1               = 393,     /* Japan (JP1) */
+    CTRY_JAPAN2               = 394,     /* Japan (JP0) */
+    CTRY_JAPAN3               = 395,     /* Japan (JP1-1) */
+    CTRY_JAPAN4               = 396,     /* Japan (JE1) */
+    CTRY_JAPAN5               = 397,     /* Japan (JE2) */
+    CTRY_JAPAN6               = 399,     /* Japan (JP6) */
+    CTRY_JORDAN               = 400,     /* Jordan */
+    CTRY_KAZAKHSTAN           = 398,     /* Kazakhstan */
+    CTRY_KENYA                = 404,     /* Kenya */
+    CTRY_KOREA_NORTH          = 408,     /* North Korea */
+    CTRY_KOREA_ROC            = 410,     /* South Korea (for STA) */
+    CTRY_KOREA_ROC2           = 411,     /* South Korea */
+    CTRY_KOREA_ROC3           = 412,     /* South Korea (for AP) */
+    CTRY_KUWAIT               = 414,     /* Kuwait */
+    CTRY_LATVIA               = 428,     /* Latvia */
+    CTRY_LEBANON              = 422,     /* Lebanon */
+    CTRY_LIBYA                = 434,     /* Libya */
+    CTRY_LIECHTENSTEIN        = 438,     /* Liechtenstein */
+    CTRY_LITHUANIA            = 440,     /* Lithuania */
+    CTRY_LUXEMBOURG           = 442,     /* Luxembourg */
+    CTRY_MACAU                = 446,     /* Macau */
+    CTRY_MACEDONIA            = 807,     /* the Former Yugoslav Republic of Macedonia */
+    CTRY_MALAYSIA             = 458,     /* Malaysia */
+    CTRY_MALTA                = 470,     /* Malta */
+    CTRY_MEXICO               = 484,     /* Mexico */
+    CTRY_MONACO               = 492,     /* Principality of Monaco */
+    CTRY_MOROCCO              = 504,     /* Morocco */
+    CTRY_NEPAL                = 524,     /* Nepal */   
+    CTRY_NETHERLANDS          = 528,     /* Netherlands */
+    CTRY_NETHERLAND_ANTILLES  = 530,     /* Netherlands-Antilles */
+    CTRY_NEW_ZEALAND          = 554,     /* New Zealand */
+    CTRY_NICARAGUA            = 558,     /* Nicaragua */
+    CTRY_NORWAY               = 578,     /* Norway */
+    CTRY_OMAN                 = 512,     /* Oman */
+    CTRY_PAKISTAN             = 586,     /* Islamic Republic of Pakistan */
+    CTRY_PANAMA               = 591,     /* Panama */
+    CTRY_PARAGUAY             = 600,     /* Paraguay */
+    CTRY_PERU                 = 604,     /* Peru */
+    CTRY_PHILIPPINES          = 608,     /* Republic of the Philippines */
+    CTRY_POLAND               = 616,     /* Poland */
+    CTRY_PORTUGAL             = 620,     /* Portugal */
+    CTRY_PUERTO_RICO          = 630,     /* Puerto Rico */
+    CTRY_QATAR                = 634,     /* Qatar */
+    CTRY_ROMANIA              = 642,     /* Romania */
+    CTRY_RUSSIA               = 643,     /* Russia */
+    CTRY_SAUDI_ARABIA         = 682,     /* Saudi Arabia */
+    CTRY_MONTENEGRO           = 891,     /* Montenegro */
+    CTRY_SINGAPORE            = 702,     /* Singapore */
+    CTRY_SLOVAKIA             = 703,     /* Slovak Republic */
+    CTRY_SLOVENIA             = 705,     /* Slovenia */
+    CTRY_SOUTH_AFRICA         = 710,     /* South Africa */
+    CTRY_SPAIN                = 724,     /* Spain */
+    CTRY_SRILANKA             = 144,     /* Sri Lanka */
+    CTRY_SWEDEN               = 752,     /* Sweden */
+    CTRY_SWITZERLAND          = 756,     /* Switzerland */
+    CTRY_SYRIA                = 760,     /* Syria */
+    CTRY_TAIWAN               = 158,     /* Taiwan */
+    CTRY_THAILAND             = 764,     /* Thailand */
+    CTRY_TRINIDAD_Y_TOBAGO    = 780,     /* Trinidad y Tobago */
+    CTRY_TUNISIA              = 788,     /* Tunisia */
+    CTRY_TURKEY               = 792,     /* Turkey */
+    CTRY_UAE                  = 784,     /* U.A.E. */
+    CTRY_UKRAINE              = 804,     /* Ukraine */
+    CTRY_UNITED_KINGDOM       = 826,     /* United Kingdom */
+    CTRY_UNITED_STATES        = 840,     /* United States (for STA) */
+    CTRY_UNITED_STATES_AP     = 841,     /* United States (for AP) */
+    CTRY_UNITED_STATES_PS     = 842,     /* United States - public safety */
+    CTRY_URUGUAY              = 858,     /* Uruguay */
+    CTRY_UZBEKISTAN           = 860,     /* Uzbekistan */
+    CTRY_VENEZUELA            = 862,     /* Venezuela */
+    CTRY_VIET_NAM             = 704,     /* Viet Nam */
+    CTRY_YEMEN                = 887,     /* Yemen */
+    CTRY_ZIMBABWE             = 716      /* Zimbabwe */
+};
+
+#define CTRY_DEBUG      0
+#define CTRY_DEFAULT    0x1ff
+
+/*
+ * The following regulatory domain definitions are
+ * found in the EEPROM. Each regulatory domain
+ * can operate in either a 5GHz or 2.4GHz wireless mode or
+ * both 5GHz and 2.4GHz wireless modes.
+ * In general, the value holds no special
+ * meaning and is used to decode into either specific
+ * 2.4GHz or 5GHz wireless mode for that particular
+ * regulatory domain.
+ *
+ * Enumerated Regulatory Domain Information 8 bit values indicate that
+ * the regdomain is really a pair of unitary regdomains.  12 bit values
+ * are the real unitary regdomains and are the only ones which have the
+ * frequency bitmasks and flags set.
+ */
+
+enum EnumRd {
+    NO_ENUMRD   = 0x00,
+    NULL1_WORLD = 0x03,     /* For 11b-only countries (no 11a allowed) */
+    NULL1_ETSIB = 0x07,     /* Israel */
+    NULL1_ETSIC = 0x08,
+
+    FCC1_FCCA   = 0x10,     /* USA */
+    FCC1_WORLD  = 0x11,     /* Hong Kong */
+    FCC2_FCCA   = 0x20,     /* Canada */
+    FCC2_WORLD  = 0x21,     /* Australia & HK */
+    FCC2_ETSIC  = 0x22,
+    FCC3_FCCA   = 0x3A,     /* USA & Canada w/5470 band, 11h, DFS enabled */
+    FCC3_WORLD  = 0x3B,     /* USA & Canada w/5470 band, 11h, DFS enabled */
+    FCC4_FCCA   = 0x12,     /* FCC public safety plus UNII bands */
+    FCC5_FCCA   = 0x13,     /* US with no DFS */
+    FCC5_WORLD  = 0x16,     /* US with no DFS */
+    FCC6_FCCA   = 0x14,     /* Same as FCC2_FCCA but with 5600-5650MHz channels disabled for US & Canada APs */
+    FCC6_WORLD  = 0x23,     /* Same as FCC2_FCCA but with 5600-5650MHz channels disabled for Australia APs */
+
+    ETSI1_WORLD = 0x37,
+
+    ETSI2_WORLD = 0x35,     /* Hungary & others */
+    ETSI3_WORLD = 0x36,     /* France & others */
+    ETSI4_WORLD = 0x30,
+    ETSI4_ETSIC = 0x38,
+    ETSI5_WORLD = 0x39,
+    ETSI6_WORLD = 0x34,     /* Bulgaria */
+    ETSI_RESERVED   = 0x33,     /* Reserved (Do not used) */
+    FRANCE_RES  = 0x31,     /* Legacy France for OEM */
+
+    APL6_WORLD  = 0x5B,     /* Singapore */
+    APL4_WORLD  = 0x42,     /* Singapore */
+    APL3_FCCA   = 0x50,
+    APL_RESERVED    = 0x44,     /* Reserved (Do not used)  */
+    APL2_WORLD  = 0x45,     /* Korea */
+    APL2_APLC   = 0x46,
+    APL3_WORLD  = 0x47,
+    APL2_APLD   = 0x49,     /* Korea with 2.3G channels */
+    APL2_FCCA   = 0x4D,     /* Specific Mobile Customer */
+    APL1_WORLD  = 0x52,     /* Latin America */
+    APL1_FCCA   = 0x53,
+    APL1_ETSIC  = 0x55,
+    APL2_ETSIC  = 0x56,     /* Venezuela */
+    APL5_WORLD  = 0x58,     /* Chile */
+    APL7_FCCA   = 0x5C,
+    APL8_WORLD  = 0x5D,
+    APL9_WORLD  = 0x5E,
+    APL10_WORLD = 0x5F,     /* Korea 5GHz for STA */
+
+
+    MKK5_MKKA   = 0x99, /* This is a temporary value. MG and DQ have to give official one */
+    MKK5_FCCA   = 0x9A, /* This is a temporary value. MG and DQ have to give official one */
+    MKK5_MKKC   = 0x88,
+    MKK11_MKKA  = 0xD4,
+    MKK11_FCCA  = 0xD5,
+    MKK11_MKKC  = 0xD7,
+
+    /*
+     * World mode SKUs
+     */
+    WOR0_WORLD  = 0x60,     /* World0 (WO0 SKU) */
+    WOR1_WORLD  = 0x61,     /* World1 (WO1 SKU) */
+    WOR2_WORLD  = 0x62,     /* World2 (WO2 SKU) */
+    WOR3_WORLD  = 0x63,     /* World3 (WO3 SKU) */
+    WOR4_WORLD  = 0x64,     /* World4 (WO4 SKU) */  
+    WOR5_ETSIC  = 0x65,     /* World5 (WO5 SKU) */    
+
+    WOR01_WORLD = 0x66,     /* World0-1 (WW0-1 SKU) */
+    WOR02_WORLD = 0x67,     /* World0-2 (WW0-2 SKU) */
+    EU1_WORLD   = 0x68,     /* Same as World0-2 (WW0-2 SKU), except active scan ch1-13. No ch14 */
+
+    WOR9_WORLD  = 0x69,     /* World9 (WO9 SKU) */  
+    WORA_WORLD  = 0x6A,     /* WorldA (WOA SKU) */  
+    WORB_WORLD  = 0x6B,     /* WorldB (WOA SKU) */  
+    WORC_WORLD  = 0x6C,     /* WorldC (WOA SKU) */  
+
+    /*
+     * Regulator domains ending in a number (e.g. APL1,
+     * MK1, ETSI4, etc) apply to 5GHz channel and power
+     * information.  Regulator domains ending in a letter
+     * (e.g. APLA, FCCA, etc) apply to 2.4GHz channel and
+     * power information.
+     */
+    APL1        = 0x0150,   /* LAT & Asia */
+    APL2        = 0x0250,   /* LAT & Asia */
+    APL3        = 0x0350,   /* Taiwan */
+    APL4        = 0x0450,   /* Jordan */
+    APL5        = 0x0550,   /* Chile */
+    APL6        = 0x0650,   /* Singapore */
+    APL7        = 0x0750,   /* Taiwan */
+    APL8        = 0x0850,   /* Malaysia */
+    APL9        = 0x0950,   /* Korea */
+    APL10       = 0x1050,   /* Korea 5GHz */
+
+    ETSI1       = 0x0130,   /* Europe & others */
+    ETSI2       = 0x0230,   /* Europe & others */
+    ETSI3       = 0x0330,   /* Europe & others */
+    ETSI4       = 0x0430,   /* Europe & others */
+    ETSI5       = 0x0530,   /* Europe & others */
+    ETSI6       = 0x0630,   /* Europe & others */
+    ETSIB       = 0x0B30,   /* Israel */
+    ETSIC       = 0x0C30,   /* Latin America */
+
+    FCC1        = 0x0110,   /* US & others */
+    FCC2        = 0x0120,   /* Canada, Australia & New Zealand */
+    FCC3        = 0x0160,   /* US w/new middle band & DFS */    
+    FCC4        = 0x0165,
+    FCC5        = 0x0180,
+    FCC6        = 0x0610,
+    FCCA        = 0x0A10,    
+
+    APLD        = 0x0D50,   /* South Korea */
+
+    MKK1        = 0x0140,   /* Japan */
+    MKK2        = 0x0240,   /* Japan Extended */
+    MKK3        = 0x0340,   /* Japan new 5GHz */
+    MKK4        = 0x0440,   /* Japan new 5GHz */
+    MKK5        = 0x0540,   /* Japan new 5GHz */
+    MKK6        = 0x0640,   /* Japan new 5GHz */
+    MKK7        = 0x0740,   /* Japan new 5GHz */
+    MKK8        = 0x0840,   /* Japan new 5GHz */
+    MKK9        = 0x0940,   /* Japan new 5GHz */
+    MKK10       = 0x1040,   /* Japan new 5GHz */
+    MKK11       = 0x1140,   /* Japan new 5GHz */
+    MKK12       = 0x1240,   /* Japan new 5GHz */
+
+    MKKA        = 0x0A40,   /* Japan */
+    MKKC        = 0x0A50,
+
+    NULL1       = 0x0198,
+    WORLD       = 0x0199,
+    DEBUG_REG_DMN   = 0x01ff,
+    UNINIT_REG_DMN  = 0x0fff,
+};
+
+enum {                  /* conformance test limits */
+    FCC = 0x10,
+    MKK = 0x40,
+    ETSI    = 0x30,
+    NO_CTL  = 0xff,
+    CTL_11B = 1,
+    CTL_11G = 2
+};
+
+
+/*
+ * The following are flags for different requirements per reg domain.
+ * These requirements are either inhereted from the reg domain pair or
+ * from the unitary reg domain if the reg domain pair flags value is
+ * 0
+ */
+
+enum {
+    NO_REQ              = 0x00,
+    DISALLOW_ADHOC_11A  = 0x01,
+    ADHOC_PER_11D       = 0x02,
+    ADHOC_NO_11A        = 0x04,
+    DISALLOW_ADHOC_11G  = 0x08
+};
+
+
+
+
+/*
+ * The following describe the bit masks for different passive scan
+ * capability/requirements per regdomain.
+ */
+#define NO_PSCAN        0x00000000
+#define PSCAN_FCC       0x00000001
+#define PSCAN_ETSI      0x00000002
+#define PSCAN_MKK       0x00000004
+#define PSCAN_ETSIB     0x00000008
+#define PSCAN_ETSIC     0x00000010
+#define PSCAN_WWR       0x00000020
+#define PSCAN_DEFER     0xFFFFFFFF
+
+/* Bit masks for DFS per regdomain */
+
+enum {
+    NO_DFS   = 0x00,
+    DFS_FCC3 = 0x01,
+    DFS_ETSI = 0x02,
+    DFS_MKK  = 0x04
+};
+
+
+#define DEF_REGDMN      FCC1_FCCA
+
+/* 
+ * The following table is the master list for all different freqeuncy
+ * bands with the complete matrix of all possible flags and settings
+ * for each band if it is used in ANY reg domain.
+ *
+ * The table of frequency bands is indexed by a bitmask.  The ordering
+ * must be consistent with the enum below.  When adding a new
+ * frequency band, be sure to match the location in the enum with the
+ * comments 
+ */
+
+/*
+ * These frequency values are as per channel tags and regulatory domain
+ * info. Please update them as database is updated.
+ */
+#define A_FREQ_MIN              4920
+#define A_FREQ_MAX              5825
+
+#define A_CHAN0_FREQ            5000
+#define A_CHAN_MAX              ((A_FREQ_MAX - A_CHAN0_FREQ)/5)
+
+#define BG_FREQ_MIN             2412
+#define BG_FREQ_MAX             2484
+
+#define BG_CHAN0_FREQ           2407
+#define BG_CHAN_MIN             ((BG_FREQ_MIN - BG_CHAN0_FREQ)/5)
+#define BG_CHAN_MAX             14      /* corresponding to 2484 MHz */
+
+#define A_20MHZ_BAND_FREQ_MAX   5000
+
+
+/*
+ * 5GHz 11A channel tags
+ */
+
+enum {
+    F1_4920_4980,
+    F1_5040_5080,
+
+    F1_5120_5240,
+
+    F1_5180_5240,
+    F2_5180_5240,
+    F3_5180_5240,
+    F4_5180_5240,
+    F5_5180_5240,
+    F6_5180_5240,
+    F7_5180_5240,
+
+    F1_5260_5280,
+
+    F1_5260_5320,
+    F2_5260_5320,
+    F3_5260_5320,
+    F4_5260_5320,
+    F5_5260_5320,
+    F6_5260_5320,
+
+    F1_5260_5700,
+
+    F1_5280_5320,
+
+    F1_5500_5620,
+
+    F1_5500_5700,
+    F2_5500_5700,
+    F3_5500_5700,
+    F4_5500_5700,
+    F5_5500_5700,
+    F6_5500_5700,
+    F7_5500_5700,
+
+    F1_5745_5805,
+    F2_5745_5805,
+
+    F1_5745_5825,
+    F2_5745_5825,
+    F3_5745_5825,
+    F4_5745_5825,
+    F5_5745_5825,
+    F6_5745_5825,
+
+    W1_4920_4980,
+    W1_5040_5080,
+    W1_5170_5230,
+    W1_5180_5240,
+    W1_5260_5320,
+    W1_5745_5825,
+    W1_5500_5700,
+};
+
+
+/* 2.4 GHz table - for 11b and 11g info */
+enum {
+    BG1_2312_2372,
+    BG2_2312_2372,
+
+    BG1_2412_2472,
+    BG2_2412_2472,
+    BG3_2412_2472,
+    BG4_2412_2472,
+
+    BG1_2412_2462,
+    BG2_2412_2462,
+
+    BG1_2432_2442,
+
+    BG1_2457_2472,
+
+    BG1_2467_2472,
+
+    BG1_2484_2484, /* No G */
+    BG2_2484_2484, /* No G */
+
+    BG1_2512_2732,
+
+    WBG1_2312_2372,
+    WBG1_2412_2412,
+    WBG1_2417_2432,
+    WBG1_2437_2442,
+    WBG1_2447_2457,
+    WBG1_2462_2462,
+    WBG1_2467_2467,
+    WBG2_2467_2467,
+    WBG1_2472_2472,
+    WBG2_2472_2472,
+    WBG1_2484_2484, /* No G */
+    WBG2_2484_2484, /* No G */
+};
+    
+#endif /* __REG_DBVALUE_H__ */
diff --git a/drivers/net/ath6kl/include/common/roaming.h b/drivers/net/ath6kl/include/common/roaming.h
new file mode 100644
index 00000000000..8019850a057
--- /dev/null
+++ b/drivers/net/ath6kl/include/common/roaming.h
@@ -0,0 +1,41 @@
+//------------------------------------------------------------------------------
+// <copyright file="roaming.h" company="Atheros">
+//    Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+#ifndef _ROAMING_H_
+#define _ROAMING_H_
+
+/* 
+ * The signal quality could be in terms of either snr or rssi. We should 
+ * have an enum for both of them. For the time being, we are going to move 
+ * it to wmi.h that is shared by both host and the target, since we are 
+ * repartitioning the code to the host 
+ */
+#define SIGNAL_QUALITY_NOISE_FLOOR        -96
+#define SIGNAL_QUALITY_METRICS_NUM_MAX    2
+typedef enum {
+    SIGNAL_QUALITY_METRICS_SNR = 0,
+    SIGNAL_QUALITY_METRICS_RSSI,
+    SIGNAL_QUALITY_METRICS_ALL,
+} SIGNAL_QUALITY_METRICS_TYPE;
+
+#endif  /* _ROAMING_H_ */
diff --git a/drivers/net/ath6kl/include/common/targaddrs.h b/drivers/net/ath6kl/include/common/targaddrs.h
new file mode 100644
index 00000000000..e8cf70354d2
--- /dev/null
+++ b/drivers/net/ath6kl/include/common/targaddrs.h
@@ -0,0 +1,245 @@
+//------------------------------------------------------------------------------
+// Copyright (c) 2010 Atheros Corporation.  All rights reserved.
+//
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//
+// Author(s): ="Atheros"
+//------------------------------------------------------------------------------
+
+#ifndef __TARGADDRS_H__
+#define __TARGADDRS_H__
+
+#ifndef ATH_TARGET
+#include "athstartpack.h"
+#endif
+
+#if defined(AR6002)
+#include "AR6002/addrs.h"
+#endif
+
+/*
+ * AR6K option bits, to enable/disable various features.
+ * By default, all option bits are 0.
+ * These bits can be set in LOCAL_SCRATCH register 0.
+ */
+#define AR6K_OPTION_BMI_DISABLE      0x01 /* Disable BMI comm with Host */
+#define AR6K_OPTION_SERIAL_ENABLE    0x02 /* Enable serial port msgs */
+#define AR6K_OPTION_WDT_DISABLE      0x04 /* WatchDog Timer override */
+#define AR6K_OPTION_SLEEP_DISABLE    0x08 /* Disable system sleep */
+#define AR6K_OPTION_STOP_BOOT        0x10 /* Stop boot processes (for ATE) */
+#define AR6K_OPTION_ENABLE_NOANI     0x20 /* Operate without ANI */
+#define AR6K_OPTION_DSET_DISABLE     0x40 /* Ignore DataSets */
+#define AR6K_OPTION_IGNORE_FLASH     0x80 /* Ignore flash during bootup */
+
+/*
+ * xxx_HOST_INTEREST_ADDRESS is the address in Target RAM of the
+ * host_interest structure.  It must match the address of the _host_interest
+ * symbol (see linker script).
+ *
+ * Host Interest is shared between Host and Target in order to coordinate
+ * between the two, and is intended to remain constant (with additions only
+ * at the end) across software releases.
+ *
+ * All addresses are available here so that it's possible to
+ * write a single binary that works with all Target Types.
+ * May be used in assembler code as well as C.
+ */
+#define AR6002_HOST_INTEREST_ADDRESS    0x00500400
+#define AR6003_HOST_INTEREST_ADDRESS    0x00540600
+
+
+#define HOST_INTEREST_MAX_SIZE          0x100
+
+#if !defined(__ASSEMBLER__)
+struct register_dump_s;
+struct dbglog_hdr_s;
+
+/*
+ * These are items that the Host may need to access
+ * via BMI or via the Diagnostic Window. The position
+ * of items in this structure must remain constant
+ * across firmware revisions!
+ *
+ * Types for each item must be fixed size across
+ * target and host platforms.
+ *
+ * More items may be added at the end.
+ */
+PREPACK struct host_interest_s {
+    /*
+     * Pointer to application-defined area, if any.
+     * Set by Target application during startup.
+     */
+    A_UINT32               hi_app_host_interest;                      /* 0x00 */
+
+    /* Pointer to register dump area, valid after Target crash. */
+    A_UINT32               hi_failure_state;                          /* 0x04 */
+
+    /* Pointer to debug logging header */
+    A_UINT32               hi_dbglog_hdr;                             /* 0x08 */
+
+    /* Indicates whether or not flash is present on Target.
+     * NB: flash_is_present indicator is here not just
+     * because it might be of interest to the Host; but
+     * also because it's set early on by Target's startup
+     * asm code and we need it to have a special RAM address
+     * so that it doesn't get reinitialized with the rest
+     * of data.
+     */
+    A_UINT32               hi_flash_is_present;                       /* 0x0c */
+
+    /*
+     * General-purpose flag bits, similar to AR6000_OPTION_* flags.
+     * Can be used by application rather than by OS.
+     */
+    A_UINT32               hi_option_flag;                            /* 0x10 */
+
+    /*
+     * Boolean that determines whether or not to
+     * display messages on the serial port.
+     */
+    A_UINT32               hi_serial_enable;                          /* 0x14 */
+
+    /* Start address of Flash DataSet index, if any */
+    A_UINT32               hi_dset_list_head;                         /* 0x18 */
+
+    /* Override Target application start address */
+    A_UINT32               hi_app_start;                              /* 0x1c */
+
+    /* Clock and voltage tuning */
+    A_UINT32               hi_skip_clock_init;                        /* 0x20 */
+    A_UINT32               hi_core_clock_setting;                     /* 0x24 */
+    A_UINT32               hi_cpu_clock_setting;                      /* 0x28 */
+    A_UINT32               hi_system_sleep_setting;                   /* 0x2c */
+    A_UINT32               hi_xtal_control_setting;                   /* 0x30 */
+    A_UINT32               hi_pll_ctrl_setting_24ghz;                 /* 0x34 */
+    A_UINT32               hi_pll_ctrl_setting_5ghz;                  /* 0x38 */
+    A_UINT32               hi_ref_voltage_trim_setting;               /* 0x3c */
+    A_UINT32               hi_clock_info;                             /* 0x40 */
+
+    /*
+     * Flash configuration overrides, used only
+     * when firmware is not executing from flash.
+     * (When using flash, modify the global variables
+     * with equivalent names.)
+     */
+    A_UINT32               hi_bank0_addr_value;                       /* 0x44 */
+    A_UINT32               hi_bank0_read_value;                       /* 0x48 */
+    A_UINT32               hi_bank0_write_value;                      /* 0x4c */
+    A_UINT32               hi_bank0_config_value;                     /* 0x50 */
+
+    /* Pointer to Board Data  */
+    A_UINT32               hi_board_data;                             /* 0x54 */
+    A_UINT32               hi_board_data_initialized;                 /* 0x58 */
+
+    A_UINT32               hi_dset_RAM_index_table;                   /* 0x5c */
+
+    A_UINT32               hi_desired_baud_rate;                      /* 0x60 */
+    A_UINT32               hi_dbglog_config;                          /* 0x64 */
+    A_UINT32               hi_end_RAM_reserve_sz;                     /* 0x68 */
+    A_UINT32               hi_mbox_io_block_sz;                       /* 0x6c */
+
+    A_UINT32               hi_num_bpatch_streams;                     /* 0x70 -- unused */
+    A_UINT32               hi_mbox_isr_yield_limit;                   /* 0x74 */
+
+    A_UINT32               hi_refclk_hz;                              /* 0x78 */
+    A_UINT32               hi_ext_clk_detected;                       /* 0x7c */
+    A_UINT32               hi_dbg_uart_txpin;                         /* 0x80 */
+    A_UINT32               hi_dbg_uart_rxpin;                         /* 0x84 */
+    A_UINT32               hi_hci_uart_baud;                          /* 0x88 */
+    A_UINT32               hi_hci_uart_pin_assignments;               /* 0x8C */
+        /* NOTE: byte [0] = tx pin, [1] = rx pin, [2] = rts pin, [3] = cts pin */
+    A_UINT32               hi_hci_uart_baud_scale_val;                /* 0x90 */
+    A_UINT32               hi_hci_uart_baud_step_val;                 /* 0x94 */
+
+    A_UINT32               hi_allocram_start;                         /* 0x98 */
+    A_UINT32               hi_allocram_sz;                            /* 0x9c */
+    A_UINT32               hi_hci_bridge_flags;                       /* 0xa0 */
+    A_UINT32               hi_hci_uart_support_pins;                  /* 0xa4 */
+        /* NOTE: byte [0] = RESET pin (bit 7 is polarity), bytes[1]..bytes[3] are for future use */
+    A_UINT32               hi_hci_uart_pwr_mgmt_params;               /* 0xa8 */
+        /* 0xa8 - [0]: 1 = enable, 0 = disable
+         *        [1]: 0 = UART FC active low, 1 = UART FC active high
+         * 0xa9 - [7:0]: wakeup timeout in ms
+         * 0xaa, 0xab - [15:0]: idle timeout in ms
+         */       
+    /* Pointer to extended board Data  */
+    A_UINT32               hi_board_ext_data;                         /* 0xac */
+    A_UINT32               hi_board_ext_data_initialized;             /* 0xb0 */
+} POSTPACK;
+
+/* Bits defined in hi_option_flag */
+#define HI_OPTION_TIMER_WAR       0x01 /* Enable timer workaround */
+#define HI_OPTION_BMI_CRED_LIMIT  0x02 /* Limit BMI command credits */
+#define HI_OPTION_RELAY_DOT11_HDR 0x04 /* Relay Dot11 hdr to/from host */
+#define HI_OPTION_FW_MODE_LSB     0x08 /* low bit of MODE (see below) */
+#define HI_OPTION_FW_MODE_MSB     0x10 /* high bit of MODE (see below) */
+#define HI_OPTION_ENABLE_PROFILE  0x20 /* Enable CPU profiling */
+#define HI_OPTION_DISABLE_DBGLOG  0x40 /* Disable debug logging */
+#define HI_OPTION_SKIP_ERA_TRACKING  0x80 /* Skip Era Tracking */
+#define HI_OPTION_PAPRD_DISABLE      0x100 /* Disable PAPRD (debug) */
+
+/* 2 bits of hi_option_flag are used to represent 3 modes */
+#define HI_OPTION_FW_MODE_IBSS    0x0 /* IBSS Mode */
+#define HI_OPTION_FW_MODE_BSS_STA 0x1 /* STA Mode */
+#define HI_OPTION_FW_MODE_AP      0x2 /* AP Mode */
+
+/* Fw Mode Mask */
+#define HI_OPTION_FW_MODE_MASK    0x3
+#define HI_OPTION_FW_MODE_SHIFT   0x3
+
+/*
+ * Intended for use by Host software, this macro returns the Target RAM
+ * address of any item in the host_interest structure.
+ * Example: target_addr = AR6002_HOST_INTEREST_ITEM_ADDRESS(hi_board_data);
+ */
+#define AR6002_HOST_INTEREST_ITEM_ADDRESS(item) \
+    (A_UINT32)((unsigned long)&((((struct host_interest_s *)(AR6002_HOST_INTEREST_ADDRESS))->item)))
+
+#define AR6003_HOST_INTEREST_ITEM_ADDRESS(item) \
+    (A_UINT32)((unsigned long)&((((struct host_interest_s *)(AR6003_HOST_INTEREST_ADDRESS))->item)))
+
+#define HOST_INTEREST_DBGLOG_IS_ENABLED() \
+        (!(HOST_INTEREST->hi_option_flag & HI_OPTION_DISABLE_DBGLOG))
+
+#define HOST_INTEREST_PROFILE_IS_ENABLED() \
+        (HOST_INTEREST->hi_option_flag & HI_OPTION_ENABLE_PROFILE)
+
+/* Convert a Target virtual address into a Target physical address */
+#define AR6002_VTOP(vaddr) ((vaddr) & 0x001fffff)
+#define AR6003_VTOP(vaddr) ((vaddr) & 0x001fffff)
+#define TARG_VTOP(TargetType, vaddr) \
+        (((TargetType) == TARGET_TYPE_AR6002) ? AR6002_VTOP(vaddr) : AR6003_VTOP(vaddr))
+
+/* override REV2 ROM's app start address */
+#define AR6002_REV2_APP_START_OVERRIDE    0x911A00
+#define AR6003_REV1_APP_START_OVERRIDE    0x944c00
+#define AR6003_REV1_OTP_DATA_ADDRESS      0x542800
+#define AR6003_REV2_APP_START_OVERRIDE    0x945000
+#define AR6003_REV2_OTP_DATA_ADDRESS      0x543800
+#define AR6003_BOARD_EXT_DATA_ADDRESS     0x57E600
+
+
+/* # of A_UINT32 entries in targregs, used by DIAG_FETCH_TARG_REGS */
+#define AR6003_FETCH_TARG_REGS_COUNT 64
+
+#endif /* !__ASSEMBLER__ */
+
+#ifndef ATH_TARGET
+#include "athendpack.h"
+#endif
+
+#endif /* __TARGADDRS_H__ */
diff --git a/drivers/net/ath6kl/include/common/testcmd.h b/drivers/net/ath6kl/include/common/testcmd.h
new file mode 100644
index 00000000000..d6616f0fab7
--- /dev/null
+++ b/drivers/net/ath6kl/include/common/testcmd.h
@@ -0,0 +1,185 @@
+//------------------------------------------------------------------------------
+// <copyright file="testcmd.h" company="Atheros">
+//    Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+#ifndef  TESTCMD_H_
+#define  TESTCMD_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef AR6002_REV2
+#define TCMD_MAX_RATES 12
+#else
+#define TCMD_MAX_RATES 28
+#endif
+
+typedef enum {
+    ZEROES_PATTERN = 0,
+    ONES_PATTERN,
+    REPEATING_10,
+    PN7_PATTERN,
+    PN9_PATTERN,
+    PN15_PATTERN
+}TX_DATA_PATTERN;
+
+/* Continous tx
+   mode : TCMD_CONT_TX_OFF - Disabling continous tx
+          TCMD_CONT_TX_SINE - Enable continuous unmodulated tx
+          TCMD_CONT_TX_FRAME- Enable continuous modulated tx
+   freq : Channel freq in Mhz. (e.g 2412 for channel 1 in 11 g)
+dataRate: 0 - 1 Mbps
+          1 - 2 Mbps
+          2 - 5.5 Mbps
+          3 - 11 Mbps
+          4 - 6 Mbps
+          5 - 9 Mbps
+          6 - 12 Mbps
+          7 - 18 Mbps
+          8 - 24 Mbps
+          9 - 36 Mbps
+         10 - 28 Mbps
+         11 - 54 Mbps
+  txPwr: Tx power in dBm[5 -11] for unmod Tx, [5-14] for mod Tx
+antenna:  1 - one antenna
+          2 - two antenna
+Note : Enable/disable continuous tx test cmd works only when target is awake.
+*/
+
+typedef enum {
+    TCMD_CONT_TX_OFF = 0,
+    TCMD_CONT_TX_SINE,
+    TCMD_CONT_TX_FRAME,
+    TCMD_CONT_TX_TX99,
+    TCMD_CONT_TX_TX100
+} TCMD_CONT_TX_MODE;
+
+typedef enum {
+    TCMD_WLAN_MODE_NOHT = 0,
+    TCMD_WLAN_MODE_HT20 = 1,
+    TCMD_WLAN_MODE_HT40PLUS = 2,
+    TCMD_WLAN_MODE_HT40MINUS = 3,
+} TCMD_WLAN_MODE;
+
+typedef PREPACK struct {
+    A_UINT32                testCmdId;
+    A_UINT32                mode;
+    A_UINT32                freq;
+    A_UINT32                dataRate;
+    A_INT32                 txPwr;
+    A_UINT32                antenna;
+    A_UINT32                enANI;
+    A_UINT32                scramblerOff;
+    A_UINT32                aifsn;
+    A_UINT16                pktSz;
+    A_UINT16                txPattern;
+    A_UINT32                shortGuard;
+    A_UINT32                numPackets;
+    A_UINT32                wlanMode;
+} POSTPACK TCMD_CONT_TX;
+
+#define TCMD_TXPATTERN_ZERONE                 0x1
+#define TCMD_TXPATTERN_ZERONE_DIS_SCRAMBLE    0x2
+
+/* Continuous Rx
+ act: TCMD_CONT_RX_PROMIS - promiscuous mode (accept all incoming frames)
+      TCMD_CONT_RX_FILTER - filter mode (accept only frames with dest
+                                             address equal specified
+                                             mac address (set via act =3)
+      TCMD_CONT_RX_REPORT  off mode  (disable cont rx mode and get the
+                                          report from the last cont
+                                          Rx test)
+
+     TCMD_CONT_RX_SETMAC - set MacAddr mode (sets the MAC address for the
+                                                 target. This Overrides
+                                                 the default MAC address.)
+
+*/
+typedef enum {
+    TCMD_CONT_RX_PROMIS =0,
+    TCMD_CONT_RX_FILTER,
+    TCMD_CONT_RX_REPORT,
+    TCMD_CONT_RX_SETMAC,
+    TCMD_CONT_RX_SET_ANT_SWITCH_TABLE
+} TCMD_CONT_RX_ACT;
+
+typedef PREPACK struct {
+    A_UINT32         testCmdId;
+    A_UINT32        act;
+    A_UINT32        enANI;
+    PREPACK union {
+        struct PREPACK TCMD_CONT_RX_PARA {
+            A_UINT32    freq;
+            A_UINT32    antenna;
+            A_UINT32    wlanMode;
+        } POSTPACK para;
+        struct PREPACK TCMD_CONT_RX_REPORT {
+            A_UINT32    totalPkt;
+            A_INT32     rssiInDBm;
+            A_UINT32    crcErrPkt;
+            A_UINT32    secErrPkt;
+            A_UINT16    rateCnt[TCMD_MAX_RATES];
+            A_UINT16    rateCntShortGuard[TCMD_MAX_RATES];
+        } POSTPACK report;
+        struct PREPACK TCMD_CONT_RX_MAC {
+            A_UCHAR    addr[ATH_MAC_LEN];
+        } POSTPACK mac;
+        struct PREPACK TCMD_CONT_RX_ANT_SWITCH_TABLE {
+            A_UINT32                antswitch1;
+            A_UINT32                antswitch2;
+        }POSTPACK antswitchtable;
+    } POSTPACK u;
+} POSTPACK TCMD_CONT_RX;
+
+/* Force sleep/wake  test cmd
+ mode: TCMD_PM_WAKEUP - Wakeup the target
+       TCMD_PM_SLEEP - Force the target to sleep.
+ */
+typedef enum {
+    TCMD_PM_WAKEUP = 1, /* be consistent with target */
+    TCMD_PM_SLEEP,
+    TCMD_PM_DEEPSLEEP
+} TCMD_PM_MODE;
+
+typedef PREPACK struct {
+    A_UINT32  testCmdId;
+    A_UINT32  mode;
+} POSTPACK TCMD_PM;
+
+typedef enum {
+    TCMD_CONT_TX_ID,
+    TCMD_CONT_RX_ID,
+    TCMD_PM_ID
+} TCMD_ID;
+
+typedef PREPACK union {
+          TCMD_CONT_TX contTx;
+          TCMD_CONT_RX contRx;
+          TCMD_PM pm;
+} POSTPACK TEST_CMD;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* TESTCMD_H_ */
diff --git a/drivers/net/ath6kl/include/common/tlpm.h b/drivers/net/ath6kl/include/common/tlpm.h
new file mode 100644
index 00000000000..659b1c07ba9
--- /dev/null
+++ b/drivers/net/ath6kl/include/common/tlpm.h
@@ -0,0 +1,38 @@
+//------------------------------------------------------------------------------
+// Copyright (c) 2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+#ifndef __TLPM_H__
+#define __TLPM_H__
+
+/* idle timeout in 16-bit value as in HOST_INTEREST hi_hci_uart_pwr_mgmt_params */
+#define TLPM_DEFAULT_IDLE_TIMEOUT_MS         1000
+/* hex in LSB and MSB for HCI command */
+#define TLPM_DEFAULT_IDLE_TIMEOUT_LSB        0xE8
+#define TLPM_DEFAULT_IDLE_TIMEOUT_MSB        0x3
+
+/* wakeup timeout in 8-bit value as in HOST_INTEREST hi_hci_uart_pwr_mgmt_params */
+#define TLPM_DEFAULT_WAKEUP_TIMEOUT_MS       10
+
+/* default UART FC polarity is low */
+#define TLPM_DEFAULT_UART_FC_POLARITY        0
+
+#endif
diff --git a/drivers/net/ath6kl/include/common/wlan_defs.h b/drivers/net/ath6kl/include/common/wlan_defs.h
new file mode 100644
index 00000000000..03e4d23788c
--- /dev/null
+++ b/drivers/net/ath6kl/include/common/wlan_defs.h
@@ -0,0 +1,79 @@
+//------------------------------------------------------------------------------
+// <copyright file="wlan_defs.h" company="Atheros">
+//    Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef __WLAN_DEFS_H__
+#define __WLAN_DEFS_H__
+
+/*
+ * This file contains WLAN definitions that may be used across both
+ * Host and Target software.  
+ */
+
+typedef enum {
+    MODE_11A        = 0,   /* 11a Mode */
+    MODE_11G        = 1,   /* 11b/g Mode */
+    MODE_11B        = 2,   /* 11b Mode */
+    MODE_11GONLY    = 3,   /* 11g only Mode */
+#ifdef SUPPORT_11N
+    MODE_11NA_HT20   = 4,  /* 11a HT20 mode */
+    MODE_11NG_HT20   = 5,  /* 11g HT20 mode */
+    MODE_11NA_HT40   = 6,  /* 11a HT40 mode */
+    MODE_11NG_HT40   = 7,  /* 11g HT40 mode */
+    MODE_UNKNOWN    = 8,
+    MODE_MAX        = 8
+#else
+    MODE_UNKNOWN    = 4,
+    MODE_MAX        = 4
+#endif
+} WLAN_PHY_MODE;
+
+typedef enum {
+    WLAN_11A_CAPABILITY   = 1,
+    WLAN_11G_CAPABILITY   = 2,
+    WLAN_11AG_CAPABILITY  = 3,
+}WLAN_CAPABILITY;
+
+#ifdef SUPPORT_11N
+typedef unsigned long A_RATEMASK;
+#else
+typedef unsigned short A_RATEMASK;
+#endif
+
+#ifdef SUPPORT_11N
+#define IS_MODE_11A(mode)       (((mode) == MODE_11A) || \
+                                 ((mode) == MODE_11NA_HT20) || \
+                                 ((mode) == MODE_11NA_HT40))
+#define IS_MODE_11B(mode)       ((mode) == MODE_11B)
+#define IS_MODE_11G(mode)       (((mode) == MODE_11G) || \
+                                 ((mode) == MODE_11GONLY) || \
+                                 ((mode) == MODE_11NG_HT20) || \
+                                 ((mode) == MODE_11NG_HT40))
+#define IS_MODE_11GONLY(mode)   ((mode) == MODE_11GONLY)
+#else
+#define IS_MODE_11A(mode)       ((mode) == MODE_11A)
+#define IS_MODE_11B(mode)       ((mode) == MODE_11B)
+#define IS_MODE_11G(mode)       (((mode) == MODE_11G) || \
+                                 ((mode) == MODE_11GONLY))
+#define IS_MODE_11GONLY(mode)   ((mode) == MODE_11GONLY)
+#endif /* SUPPORT_11N */
+
+#endif /* __WLANDEFS_H__ */
diff --git a/drivers/net/ath6kl/include/common/wlan_dset.h b/drivers/net/ath6kl/include/common/wlan_dset.h
new file mode 100644
index 00000000000..864a60cedf1
--- /dev/null
+++ b/drivers/net/ath6kl/include/common/wlan_dset.h
@@ -0,0 +1,33 @@
+//------------------------------------------------------------------------------
+// Copyright (c) 2007-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+#ifndef __WLAN_DSET_H__
+#define __WLAN_DSET_H__
+
+typedef PREPACK struct wow_config_dset {
+
+    A_UINT8 valid_dset;
+    A_UINT8 gpio_enable;
+    A_UINT16 gpio_pin;
+} POSTPACK WOW_CONFIG_DSET;
+
+#endif
diff --git a/drivers/net/ath6kl/include/common/wmi.h b/drivers/net/ath6kl/include/common/wmi.h
new file mode 100644
index 00000000000..c75d310c37a
--- /dev/null
+++ b/drivers/net/ath6kl/include/common/wmi.h
@@ -0,0 +1,3119 @@
+//------------------------------------------------------------------------------
+// Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+//
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//
+// Author(s): ="Atheros"
+//------------------------------------------------------------------------------
+
+/*
+ * This file contains the definitions of the WMI protocol specified in the
+ * Wireless Module Interface (WMI).  It includes definitions of all the
+ * commands and events. Commands are messages from the host to the WM.
+ * Events and Replies are messages from the WM to the host.
+ *
+ * Ownership of correctness in regards to commands
+ * belongs to the host driver and the WMI is not required to validate
+ * parameters for value, proper range, or any other checking.
+ *
+ */
+
+#ifndef _WMI_H_
+#define _WMI_H_
+
+#ifndef ATH_TARGET
+#include "athstartpack.h"
+#endif
+
+#include "wmix.h"
+#include "wlan_defs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define HTC_PROTOCOL_VERSION    0x0002
+#define HTC_PROTOCOL_REVISION   0x0000
+
+#define WMI_PROTOCOL_VERSION    0x0002
+#define WMI_PROTOCOL_REVISION   0x0000
+
+#define ATH_MAC_LEN             6               /* length of mac in bytes */
+#define WMI_CMD_MAX_LEN         100
+#define WMI_CONTROL_MSG_MAX_LEN     256
+#define WMI_OPT_CONTROL_MSG_MAX_LEN 1536
+#define IS_ETHERTYPE(_typeOrLen)        ((_typeOrLen) >= 0x0600)
+#define RFC1042OUI      {0x00, 0x00, 0x00}
+
+#define IP_ETHERTYPE 0x0800
+
+#define WMI_IMPLICIT_PSTREAM 0xFF
+#define WMI_MAX_THINSTREAM 15
+
+#ifdef AR6002_REV2
+#define IBSS_MAX_NUM_STA          4
+#else
+#define IBSS_MAX_NUM_STA          8
+#endif
+
+PREPACK struct host_app_area_s {
+    A_UINT32 wmi_protocol_ver;
+} POSTPACK;
+
+/*
+ * Data Path
+ */
+typedef PREPACK struct {
+    A_UINT8     dstMac[ATH_MAC_LEN];
+    A_UINT8     srcMac[ATH_MAC_LEN];
+    A_UINT16    typeOrLen;
+} POSTPACK ATH_MAC_HDR;
+
+typedef PREPACK struct {
+    A_UINT8     dsap;
+    A_UINT8     ssap;
+    A_UINT8     cntl;
+    A_UINT8     orgCode[3];
+    A_UINT16    etherType;
+} POSTPACK ATH_LLC_SNAP_HDR;
+
+typedef enum {
+    DATA_MSGTYPE = 0x0,
+    CNTL_MSGTYPE,
+    SYNC_MSGTYPE,
+    OPT_MSGTYPE,
+} WMI_MSG_TYPE;
+
+
+/*
+ * Macros for operating on WMI_DATA_HDR (info) field
+ */
+
+#define WMI_DATA_HDR_MSG_TYPE_MASK  0x03
+#define WMI_DATA_HDR_MSG_TYPE_SHIFT 0
+#define WMI_DATA_HDR_UP_MASK        0x07
+#define WMI_DATA_HDR_UP_SHIFT       2
+/* In AP mode, the same bit (b5) is used to indicate Power save state in
+ * the Rx dir and More data bit state in the tx direction.
+ */
+#define WMI_DATA_HDR_PS_MASK        0x1
+#define WMI_DATA_HDR_PS_SHIFT       5
+
+#define WMI_DATA_HDR_MORE_MASK      0x1
+#define WMI_DATA_HDR_MORE_SHIFT     5
+
+typedef enum {
+    WMI_DATA_HDR_DATA_TYPE_802_3 = 0,
+    WMI_DATA_HDR_DATA_TYPE_802_11,
+    WMI_DATA_HDR_DATA_TYPE_ACL,
+} WMI_DATA_HDR_DATA_TYPE;
+
+#define WMI_DATA_HDR_DATA_TYPE_MASK     0x3
+#define WMI_DATA_HDR_DATA_TYPE_SHIFT    6
+
+#define WMI_DATA_HDR_SET_MORE_BIT(h) ((h)->info |= (WMI_DATA_HDR_MORE_MASK << WMI_DATA_HDR_MORE_SHIFT))
+
+#define WMI_DATA_HDR_IS_MSG_TYPE(h, t)  (((h)->info & (WMI_DATA_HDR_MSG_TYPE_MASK)) == (t))
+#define WMI_DATA_HDR_SET_MSG_TYPE(h, t) (h)->info = (((h)->info & ~(WMI_DATA_HDR_MSG_TYPE_MASK << WMI_DATA_HDR_MSG_TYPE_SHIFT)) | (t << WMI_DATA_HDR_MSG_TYPE_SHIFT))
+#define WMI_DATA_HDR_GET_UP(h)    (((h)->info >> WMI_DATA_HDR_UP_SHIFT) & WMI_DATA_HDR_UP_MASK)
+#define WMI_DATA_HDR_SET_UP(h, p) (h)->info = (((h)->info & ~(WMI_DATA_HDR_UP_MASK << WMI_DATA_HDR_UP_SHIFT)) | (p << WMI_DATA_HDR_UP_SHIFT))
+
+#define WMI_DATA_HDR_GET_DATA_TYPE(h)   (((h)->info >> WMI_DATA_HDR_DATA_TYPE_SHIFT) & WMI_DATA_HDR_DATA_TYPE_MASK)
+#define WMI_DATA_HDR_SET_DATA_TYPE(h, p) (h)->info = (((h)->info & ~(WMI_DATA_HDR_DATA_TYPE_MASK << WMI_DATA_HDR_DATA_TYPE_SHIFT)) | ((p) << WMI_DATA_HDR_DATA_TYPE_SHIFT))
+
+#define WMI_DATA_HDR_GET_DOT11(h)   (WMI_DATA_HDR_GET_DATA_TYPE((h)) == WMI_DATA_HDR_DATA_TYPE_802_11)
+#define WMI_DATA_HDR_SET_DOT11(h, p) WMI_DATA_HDR_SET_DATA_TYPE((h), (p))
+
+/* Macros for operating on WMI_DATA_HDR (info2) field */
+#define WMI_DATA_HDR_SEQNO_MASK     0xFFF
+#define WMI_DATA_HDR_SEQNO_SHIFT    0
+
+#define WMI_DATA_HDR_AMSDU_MASK     0x1
+#define WMI_DATA_HDR_AMSDU_SHIFT    12
+
+#define WMI_DATA_HDR_META_MASK      0x7
+#define WMI_DATA_HDR_META_SHIFT     13
+
+#define GET_SEQ_NO(_v)                  ((_v) & WMI_DATA_HDR_SEQNO_MASK)
+#define GET_ISMSDU(_v)                  ((_v) & WMI_DATA_HDR_AMSDU_MASK)
+
+#define WMI_DATA_HDR_GET_SEQNO(h)        GET_SEQ_NO((h)->info2 >> WMI_DATA_HDR_SEQNO_SHIFT)
+#define WMI_DATA_HDR_SET_SEQNO(h, _v)   ((h)->info2 = ((h)->info2 & ~(WMI_DATA_HDR_SEQNO_MASK << WMI_DATA_HDR_SEQNO_SHIFT)) | (GET_SEQ_NO(_v) << WMI_DATA_HDR_SEQNO_SHIFT))
+
+#define WMI_DATA_HDR_IS_AMSDU(h)        GET_ISMSDU((h)->info2 >> WMI_DATA_HDR_AMSDU_SHIFT)
+#define WMI_DATA_HDR_SET_AMSDU(h, _v)   ((h)->info2 = ((h)->info2 & ~(WMI_DATA_HDR_AMSDU_MASK << WMI_DATA_HDR_AMSDU_SHIFT)) | (GET_ISMSDU(_v) << WMI_DATA_HDR_AMSDU_SHIFT))
+
+#define WMI_DATA_HDR_GET_META(h)        (((h)->info2 >> WMI_DATA_HDR_META_SHIFT) & WMI_DATA_HDR_META_MASK)
+#define WMI_DATA_HDR_SET_META(h, _v)    ((h)->info2 = ((h)->info2 & ~(WMI_DATA_HDR_META_MASK << WMI_DATA_HDR_META_SHIFT)) | ((_v) << WMI_DATA_HDR_META_SHIFT))
+
+typedef PREPACK struct {
+    A_INT8      rssi;
+    A_UINT8     info;               /* usage of 'info' field(8-bit):
+                                     *  b1:b0       - WMI_MSG_TYPE
+                                     *  b4:b3:b2    - UP(tid)
+                                     *  b5          - Used in AP mode. More-data in tx dir, PS in rx.
+                                     *  b7:b6       -  Dot3 header(0),
+                                     *                 Dot11 Header(1),
+                                     *                 ACL data(2)
+                                     */
+
+    A_UINT16    info2;              /* usage of 'info2' field(16-bit):
+                                     * b11:b0       - seq_no
+                                     * b12          - A-MSDU?
+                                     * b15:b13      - META_DATA_VERSION 0 - 7
+                                     */
+    A_UINT16    reserved;
+} POSTPACK WMI_DATA_HDR;
+
+/*
+ *  TX META VERSION DEFINITIONS
+ */
+#define WMI_MAX_TX_META_SZ  (12)
+#define WMI_MAX_TX_META_VERSION (7)
+#define WMI_META_VERSION_1 (0x01)
+#define WMI_META_VERSION_2 (0X02)
+
+#define WMI_ACL_TO_DOT11_HEADROOM   36
+
+#if 0 /* removed to prevent compile errors for WM.. */
+typedef PREPACK struct {
+/* intentionally empty. Default version is no meta data. */
+} POSTPACK WMI_TX_META_V0;
+#endif
+
+typedef PREPACK struct {
+    A_UINT8     pktID;           /* The packet ID to identify the tx request */
+    A_UINT8     ratePolicyID;    /* The rate policy to be used for the tx of this frame */
+} POSTPACK WMI_TX_META_V1;
+
+
+#define WMI_CSUM_DIR_TX (0x1)
+#define TX_CSUM_CALC_FILL (0x1)
+typedef PREPACK struct {
+    A_UINT8    csumStart;       /*Offset from start of the WMI header for csum calculation to begin */
+    A_UINT8    csumDest;        /*Offset from start of WMI header where final csum goes*/
+    A_UINT8     csumFlags;    /*number of bytes over which csum is calculated*/
+} POSTPACK WMI_TX_META_V2;
+
+
+/*
+ *  RX META VERSION DEFINITIONS
+ */
+/* if RX meta data is present at all then the meta data field
+ *  will consume WMI_MAX_RX_META_SZ bytes of space between the
+ *  WMI_DATA_HDR and the payload. How much of the available
+ *  Meta data is actually used depends on which meta data
+ *  version is active. */
+#define WMI_MAX_RX_META_SZ  (12)
+#define WMI_MAX_RX_META_VERSION (7)
+
+#define WMI_RX_STATUS_OK            0 /* success */
+#define WMI_RX_STATUS_DECRYPT_ERR   1 /* decrypt error */
+#define WMI_RX_STATUS_MIC_ERR       2 /* tkip MIC error */
+#define WMI_RX_STATUS_ERR           3 /* undefined error */
+
+#define WMI_RX_FLAGS_AGGR           0x0001 /* part of AGGR */
+#define WMI_RX_FlAGS_STBC           0x0002 /* used STBC */
+#define WMI_RX_FLAGS_SGI            0x0004 /* used SGI */
+#define WMI_RX_FLAGS_HT             0x0008 /* is HT packet */
+/* the flags field is also used to store the CRYPTO_TYPE of the frame
+ * that value is shifted by WMI_RX_FLAGS_CRYPTO_SHIFT */
+#define WMI_RX_FLAGS_CRYPTO_SHIFT   4
+#define WMI_RX_FLAGS_CRYPTO_MASK    0x1f
+#define WMI_RX_META_GET_CRYPTO(flags) (((flags) >> WMI_RX_FLAGS_CRYPTO_SHIFT) & WMI_RX_FLAGS_CRYPTO_MASK)
+
+#if 0 /* removed to prevent compile errors for WM.. */
+typedef PREPACK struct {
+/* intentionally empty. Default version is no meta data. */
+} POSTPACK WMI_RX_META_VERSION_0;
+#endif
+
+typedef PREPACK struct {
+    A_UINT8     status; /* one of WMI_RX_STATUS_... */
+    A_UINT8     rix;    /* rate index mapped to rate at which this packet was received. */
+    A_UINT8     rssi;   /* rssi of packet */
+    A_UINT8     channel;/* rf channel during packet reception */
+    A_UINT16    flags;  /* a combination of WMI_RX_FLAGS_... */
+} POSTPACK WMI_RX_META_V1;
+
+#define RX_CSUM_VALID_FLAG (0x1)
+typedef PREPACK struct {
+    A_UINT16    csum;
+    A_UINT8     csumFlags;/* bit 0 set -partial csum valid
+                             bit 1 set -test mode */
+} POSTPACK WMI_RX_META_V2;
+
+
+
+#define WMI_GET_DEVICE_ID(info1) ((info1) & 0xF)
+
+/*
+ * Control Path
+ */
+typedef PREPACK struct {
+    A_UINT16    commandId;
+/*
+ * info1 - 16 bits
+ * b03:b00 - id
+ * b15:b04 - unused
+ */
+    A_UINT16    info1;
+
+    A_UINT16    reserved;      /* For alignment */
+} POSTPACK WMI_CMD_HDR;        /* used for commands and events */
+
+/*
+ * List of Commnands
+ */
+typedef enum {
+    WMI_CONNECT_CMDID           = 0x0001,
+    WMI_RECONNECT_CMDID,
+    WMI_DISCONNECT_CMDID,
+    WMI_SYNCHRONIZE_CMDID,
+    WMI_CREATE_PSTREAM_CMDID,
+    WMI_DELETE_PSTREAM_CMDID,
+    WMI_START_SCAN_CMDID,
+    WMI_SET_SCAN_PARAMS_CMDID,
+    WMI_SET_BSS_FILTER_CMDID,
+    WMI_SET_PROBED_SSID_CMDID,               /* 10 */
+    WMI_SET_LISTEN_INT_CMDID,
+    WMI_SET_BMISS_TIME_CMDID,
+    WMI_SET_DISC_TIMEOUT_CMDID,
+    WMI_GET_CHANNEL_LIST_CMDID,
+    WMI_SET_BEACON_INT_CMDID,
+    WMI_GET_STATISTICS_CMDID,
+    WMI_SET_CHANNEL_PARAMS_CMDID,
+    WMI_SET_POWER_MODE_CMDID,
+    WMI_SET_IBSS_PM_CAPS_CMDID,
+    WMI_SET_POWER_PARAMS_CMDID,              /* 20 */
+    WMI_SET_POWERSAVE_TIMERS_POLICY_CMDID,
+    WMI_ADD_CIPHER_KEY_CMDID,
+    WMI_DELETE_CIPHER_KEY_CMDID,
+    WMI_ADD_KRK_CMDID,
+    WMI_DELETE_KRK_CMDID,
+    WMI_SET_PMKID_CMDID,
+    WMI_SET_TX_PWR_CMDID,
+    WMI_GET_TX_PWR_CMDID,
+    WMI_SET_ASSOC_INFO_CMDID,
+    WMI_ADD_BAD_AP_CMDID,                    /* 30 */
+    WMI_DELETE_BAD_AP_CMDID,
+    WMI_SET_TKIP_COUNTERMEASURES_CMDID,
+    WMI_RSSI_THRESHOLD_PARAMS_CMDID,
+    WMI_TARGET_ERROR_REPORT_BITMASK_CMDID,
+    WMI_SET_ACCESS_PARAMS_CMDID,
+    WMI_SET_RETRY_LIMITS_CMDID,
+    WMI_SET_OPT_MODE_CMDID,
+    WMI_OPT_TX_FRAME_CMDID,
+    WMI_SET_VOICE_PKT_SIZE_CMDID,
+    WMI_SET_MAX_SP_LEN_CMDID,                /* 40 */
+    WMI_SET_ROAM_CTRL_CMDID,
+    WMI_GET_ROAM_TBL_CMDID,
+    WMI_GET_ROAM_DATA_CMDID,
+    WMI_ENABLE_RM_CMDID,
+    WMI_SET_MAX_OFFHOME_DURATION_CMDID,
+    WMI_EXTENSION_CMDID,                        /* Non-wireless extensions */
+    WMI_SNR_THRESHOLD_PARAMS_CMDID,
+    WMI_LQ_THRESHOLD_PARAMS_CMDID,
+    WMI_SET_LPREAMBLE_CMDID,
+    WMI_SET_RTS_CMDID,                       /* 50 */
+    WMI_CLR_RSSI_SNR_CMDID,
+    WMI_SET_FIXRATES_CMDID,
+    WMI_GET_FIXRATES_CMDID,
+    WMI_SET_AUTH_MODE_CMDID,
+    WMI_SET_REASSOC_MODE_CMDID,
+    WMI_SET_WMM_CMDID,
+    WMI_SET_WMM_TXOP_CMDID,
+    WMI_TEST_CMDID,
+    /* COEX AR6002 only*/
+    WMI_SET_BT_STATUS_CMDID,                
+    WMI_SET_BT_PARAMS_CMDID,                /* 60 */
+
+    WMI_SET_KEEPALIVE_CMDID,
+    WMI_GET_KEEPALIVE_CMDID,
+    WMI_SET_APPIE_CMDID,
+    WMI_GET_APPIE_CMDID,
+    WMI_SET_WSC_STATUS_CMDID,
+
+    /* Wake on Wireless */
+    WMI_SET_HOST_SLEEP_MODE_CMDID,
+    WMI_SET_WOW_MODE_CMDID,
+    WMI_GET_WOW_LIST_CMDID,
+    WMI_ADD_WOW_PATTERN_CMDID,
+    WMI_DEL_WOW_PATTERN_CMDID,               /* 70 */
+
+    WMI_SET_FRAMERATES_CMDID,
+    WMI_SET_AP_PS_CMDID,
+    WMI_SET_QOS_SUPP_CMDID,
+    /* WMI_THIN_RESERVED_... mark the start and end
+     * values for WMI_THIN_RESERVED command IDs. These
+     * command IDs can be found in wmi_thin.h */
+    WMI_THIN_RESERVED_START = 0x8000,
+    WMI_THIN_RESERVED_END = 0x8fff,
+    /*
+     * Developer commands starts at 0xF000
+     */
+    WMI_SET_BITRATE_CMDID = 0xF000,
+    WMI_GET_BITRATE_CMDID,
+    WMI_SET_WHALPARAM_CMDID,
+
+
+    /*Should add the new command to the tail for compatible with
+     * etna.
+     */
+    WMI_SET_MAC_ADDRESS_CMDID,
+    WMI_SET_AKMP_PARAMS_CMDID,
+    WMI_SET_PMKID_LIST_CMDID,
+    WMI_GET_PMKID_LIST_CMDID,
+    WMI_ABORT_SCAN_CMDID,
+    WMI_SET_TARGET_EVENT_REPORT_CMDID,
+
+    // Unused
+    WMI_UNUSED1,
+    WMI_UNUSED2,
+
+    /*
+     * AP mode commands
+     */
+    WMI_AP_HIDDEN_SSID_CMDID,
+    WMI_AP_SET_NUM_STA_CMDID,
+    WMI_AP_ACL_POLICY_CMDID,
+    WMI_AP_ACL_MAC_LIST_CMDID,
+    WMI_AP_CONFIG_COMMIT_CMDID,
+    WMI_AP_SET_MLME_CMDID,
+    WMI_AP_SET_PVB_CMDID,
+    WMI_AP_CONN_INACT_CMDID,
+    WMI_AP_PROT_SCAN_TIME_CMDID,
+    WMI_AP_SET_COUNTRY_CMDID,
+    WMI_AP_SET_DTIM_CMDID,
+    WMI_AP_MODE_STAT_CMDID,
+
+    WMI_SET_IP_CMDID,
+    WMI_SET_PARAMS_CMDID,
+    WMI_SET_MCAST_FILTER_CMDID,
+    WMI_DEL_MCAST_FILTER_CMDID,
+
+    WMI_ALLOW_AGGR_CMDID,
+    WMI_ADDBA_REQ_CMDID,
+    WMI_DELBA_REQ_CMDID,
+    WMI_SET_HT_CAP_CMDID,
+    WMI_SET_HT_OP_CMDID,
+    WMI_SET_TX_SELECT_RATES_CMDID,
+    WMI_SET_TX_SGI_PARAM_CMDID,
+    WMI_SET_RATE_POLICY_CMDID,
+
+    WMI_HCI_CMD_CMDID,
+    WMI_RX_FRAME_FORMAT_CMDID,
+    WMI_SET_THIN_MODE_CMDID,
+    WMI_SET_BT_WLAN_CONN_PRECEDENCE_CMDID,
+
+    WMI_AP_SET_11BG_RATESET_CMDID,
+    WMI_SET_PMK_CMDID,
+    WMI_MCAST_FILTER_CMDID,
+	/* COEX CMDID AR6003*/
+	WMI_SET_BTCOEX_FE_ANT_CMDID,
+	WMI_SET_BTCOEX_COLOCATED_BT_DEV_CMDID,
+	WMI_SET_BTCOEX_SCO_CONFIG_CMDID,
+	WMI_SET_BTCOEX_A2DP_CONFIG_CMDID,
+	WMI_SET_BTCOEX_ACLCOEX_CONFIG_CMDID,
+	WMI_SET_BTCOEX_BTINQUIRY_PAGE_CONFIG_CMDID,
+	WMI_SET_BTCOEX_DEBUG_CMDID,
+	WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMDID,
+	WMI_GET_BTCOEX_STATS_CMDID,
+	WMI_GET_BTCOEX_CONFIG_CMDID,
+} WMI_COMMAND_ID;
+
+/*
+ * Frame Types
+ */
+typedef enum {
+    WMI_FRAME_BEACON        =   0,
+    WMI_FRAME_PROBE_REQ,
+    WMI_FRAME_PROBE_RESP,
+    WMI_FRAME_ASSOC_REQ,
+    WMI_FRAME_ASSOC_RESP,
+    WMI_NUM_MGMT_FRAME
+} WMI_MGMT_FRAME_TYPE;
+
+/*
+ * Connect Command
+ */
+typedef enum {
+    INFRA_NETWORK       = 0x01,
+    ADHOC_NETWORK       = 0x02,
+    ADHOC_CREATOR       = 0x04,
+    AP_NETWORK          = 0x10,
+} NETWORK_TYPE;
+
+typedef enum {
+    OPEN_AUTH           = 0x01,
+    SHARED_AUTH         = 0x02,
+    LEAP_AUTH           = 0x04,  /* different from IEEE_AUTH_MODE definitions */
+} DOT11_AUTH_MODE;
+
+typedef enum {
+    NONE_AUTH           = 0x01,
+    WPA_AUTH            = 0x02,
+    WPA2_AUTH           = 0x04,
+    WPA_PSK_AUTH        = 0x08,
+    WPA2_PSK_AUTH       = 0x10,
+    WPA_AUTH_CCKM       = 0x20,
+    WPA2_AUTH_CCKM      = 0x40,
+} AUTH_MODE;
+
+typedef enum {
+    NONE_CRYPT          = 0x01,
+    WEP_CRYPT           = 0x02,
+    TKIP_CRYPT          = 0x04,
+    AES_CRYPT           = 0x08,
+#ifdef WAPI_ENABLE
+    WAPI_CRYPT          = 0x10,
+#endif /*WAPI_ENABLE*/
+} CRYPTO_TYPE;
+
+#define WMI_MIN_CRYPTO_TYPE NONE_CRYPT
+#define WMI_MAX_CRYPTO_TYPE (AES_CRYPT + 1)
+
+#ifdef WAPI_ENABLE
+#undef WMI_MAX_CRYPTO_TYPE
+#define WMI_MAX_CRYPTO_TYPE (WAPI_CRYPT + 1)
+#endif /* WAPI_ENABLE */
+
+#ifdef WAPI_ENABLE
+#define IW_ENCODE_ALG_SM4       0x20
+#define IW_AUTH_WAPI_ENABLED    0x20
+#endif
+
+#define WMI_MIN_KEY_INDEX   0
+#define WMI_MAX_KEY_INDEX   3
+
+#ifdef WAPI_ENABLE
+#undef WMI_MAX_KEY_INDEX
+#define WMI_MAX_KEY_INDEX   7 /* wapi grpKey 0-3, prwKey 4-7 */
+#endif /* WAPI_ENABLE */
+
+#define WMI_MAX_KEY_LEN     32
+
+#define WMI_MAX_SSID_LEN    32
+
+typedef enum {
+    CONNECT_ASSOC_POLICY_USER           = 0x0001,
+    CONNECT_SEND_REASSOC                = 0x0002,
+    CONNECT_IGNORE_WPAx_GROUP_CIPHER    = 0x0004,
+    CONNECT_PROFILE_MATCH_DONE          = 0x0008,
+    CONNECT_IGNORE_AAC_BEACON           = 0x0010,
+    CONNECT_CSA_FOLLOW_BSS              = 0x0020,
+    CONNECT_DO_WPA_OFFLOAD              = 0x0040,
+    CONNECT_DO_NOT_DEAUTH               = 0x0080,
+} WMI_CONNECT_CTRL_FLAGS_BITS;
+
+#define DEFAULT_CONNECT_CTRL_FLAGS    (CONNECT_CSA_FOLLOW_BSS)
+
+typedef PREPACK struct {
+    A_UINT8     networkType;
+    A_UINT8     dot11AuthMode;
+    A_UINT8     authMode;
+    A_UINT8     pairwiseCryptoType;
+    A_UINT8     pairwiseCryptoLen;
+    A_UINT8     groupCryptoType;
+    A_UINT8     groupCryptoLen;
+    A_UINT8     ssidLength;
+    A_UCHAR     ssid[WMI_MAX_SSID_LEN];
+    A_UINT16    channel;
+    A_UINT8     bssid[ATH_MAC_LEN];
+    A_UINT32    ctrl_flags;
+} POSTPACK WMI_CONNECT_CMD;
+
+/*
+ * WMI_RECONNECT_CMDID
+ */
+typedef PREPACK struct {
+    A_UINT16    channel;                    /* hint */
+    A_UINT8     bssid[ATH_MAC_LEN];         /* mandatory if set */
+} POSTPACK WMI_RECONNECT_CMD;
+
+#define WMI_PMK_LEN     32
+typedef PREPACK struct {
+    A_UINT8 pmk[WMI_PMK_LEN];
+} POSTPACK WMI_SET_PMK_CMD;
+
+/*
+ * WMI_ADD_CIPHER_KEY_CMDID
+ */
+typedef enum {
+    PAIRWISE_USAGE      = 0x00,
+    GROUP_USAGE         = 0x01,
+    TX_USAGE            = 0x02,     /* default Tx Key - Static WEP only */
+} KEY_USAGE;
+
+/*
+ * Bit Flag
+ * Bit 0 - Initialise TSC - default is Initialize
+ */
+#define KEY_OP_INIT_TSC       0x01
+#define KEY_OP_INIT_RSC       0x02
+#ifdef WAPI_ENABLE
+#define KEY_OP_INIT_WAPIPN    0x10
+#endif /* WAPI_ENABLE */
+
+#define KEY_OP_INIT_VAL     0x03     /* Default Initialise the TSC & RSC */
+#define KEY_OP_VALID_MASK   0x03
+
+typedef PREPACK struct {
+    A_UINT8     keyIndex;
+    A_UINT8     keyType;
+    A_UINT8     keyUsage;           /* KEY_USAGE */
+    A_UINT8     keyLength;
+    A_UINT8     keyRSC[8];          /* key replay sequence counter */
+    A_UINT8     key[WMI_MAX_KEY_LEN];
+    A_UINT8     key_op_ctrl;       /* Additional Key Control information */
+    A_UINT8    key_macaddr[ATH_MAC_LEN];
+} POSTPACK WMI_ADD_CIPHER_KEY_CMD;
+
+/*
+ * WMI_DELETE_CIPHER_KEY_CMDID
+ */
+typedef PREPACK struct {
+    A_UINT8     keyIndex;
+} POSTPACK WMI_DELETE_CIPHER_KEY_CMD;
+
+#define WMI_KRK_LEN     16
+/*
+ * WMI_ADD_KRK_CMDID
+ */
+typedef PREPACK struct {
+    A_UINT8     krk[WMI_KRK_LEN];
+} POSTPACK WMI_ADD_KRK_CMD;
+
+/*
+ * WMI_SET_TKIP_COUNTERMEASURES_CMDID
+ */
+typedef enum {
+    WMI_TKIP_CM_DISABLE = 0x0,
+    WMI_TKIP_CM_ENABLE  = 0x1,
+} WMI_TKIP_CM_CONTROL;
+
+typedef PREPACK struct {
+    A_UINT8  cm_en;                     /* WMI_TKIP_CM_CONTROL */
+} POSTPACK WMI_SET_TKIP_COUNTERMEASURES_CMD;
+
+/*
+ * WMI_SET_PMKID_CMDID
+ */
+
+#define WMI_PMKID_LEN 16
+
+typedef enum {
+   PMKID_DISABLE = 0,
+   PMKID_ENABLE  = 1,
+} PMKID_ENABLE_FLG;
+
+typedef PREPACK struct {
+    A_UINT8     bssid[ATH_MAC_LEN];
+    A_UINT8     enable;                 /* PMKID_ENABLE_FLG */
+    A_UINT8     pmkid[WMI_PMKID_LEN];
+} POSTPACK WMI_SET_PMKID_CMD;
+
+/*
+ * WMI_START_SCAN_CMD
+ */
+typedef enum {
+    WMI_LONG_SCAN  = 0,
+    WMI_SHORT_SCAN = 1,
+} WMI_SCAN_TYPE;
+
+typedef PREPACK struct {
+    A_BOOL   forceFgScan;
+    A_BOOL   isLegacy;        /* For Legacy Cisco AP compatibility */
+    A_UINT32 homeDwellTime;   /* Maximum duration in the home channel(milliseconds) */
+    A_UINT32 forceScanInterval;    /* Time interval between scans (milliseconds)*/
+    A_UINT8  scanType;           /* WMI_SCAN_TYPE */
+    A_UINT8  numChannels;            /* how many channels follow */
+    A_UINT16 channelList[1];         /* channels in Mhz */
+} POSTPACK WMI_START_SCAN_CMD;
+
+/*
+ * WMI_SET_SCAN_PARAMS_CMDID
+ */
+#define WMI_SHORTSCANRATIO_DEFAULT      3
+/* 
+ *  Warning: ScanCtrlFlag value of 0xFF is used to disable all flags in WMI_SCAN_PARAMS_CMD 
+ *  Do not add any more flags to WMI_SCAN_CTRL_FLAG_BITS
+ */
+typedef enum {
+    CONNECT_SCAN_CTRL_FLAGS = 0x01,    /* set if can scan in the Connect cmd */
+    SCAN_CONNECTED_CTRL_FLAGS = 0x02,  /* set if scan for the SSID it is */
+                                       /* already connected to */
+    ACTIVE_SCAN_CTRL_FLAGS = 0x04,     /* set if enable active scan */
+    ROAM_SCAN_CTRL_FLAGS = 0x08,       /* set if enable roam scan when bmiss and lowrssi */
+    REPORT_BSSINFO_CTRL_FLAGS = 0x10,   /* set if follows customer BSSINFO reporting rule */
+    ENABLE_AUTO_CTRL_FLAGS = 0x20,      /* if disabled, target doesn't
+                                          scan after a disconnect event  */
+    ENABLE_SCAN_ABORT_EVENT = 0x40      /* Scan complete event with canceled status will be generated when a scan is prempted before it gets completed */
+} WMI_SCAN_CTRL_FLAGS_BITS;
+
+#define CAN_SCAN_IN_CONNECT(flags)      (flags & CONNECT_SCAN_CTRL_FLAGS)
+#define CAN_SCAN_CONNECTED(flags)       (flags & SCAN_CONNECTED_CTRL_FLAGS)
+#define ENABLE_ACTIVE_SCAN(flags)       (flags & ACTIVE_SCAN_CTRL_FLAGS)
+#define ENABLE_ROAM_SCAN(flags)         (flags & ROAM_SCAN_CTRL_FLAGS)
+#define CONFIG_REPORT_BSSINFO(flags)     (flags & REPORT_BSSINFO_CTRL_FLAGS)
+#define IS_AUTO_SCAN_ENABLED(flags)      (flags & ENABLE_AUTO_CTRL_FLAGS)
+#define SCAN_ABORT_EVENT_ENABLED(flags) (flags & ENABLE_SCAN_ABORT_EVENT)
+
+#define DEFAULT_SCAN_CTRL_FLAGS         (CONNECT_SCAN_CTRL_FLAGS| SCAN_CONNECTED_CTRL_FLAGS| ACTIVE_SCAN_CTRL_FLAGS| ROAM_SCAN_CTRL_FLAGS | ENABLE_AUTO_CTRL_FLAGS)
+
+
+typedef PREPACK struct {
+    A_UINT16    fg_start_period;        /* seconds */
+    A_UINT16    fg_end_period;          /* seconds */
+    A_UINT16    bg_period;              /* seconds */
+    A_UINT16    maxact_chdwell_time;    /* msec */
+    A_UINT16    pas_chdwell_time;       /* msec */
+    A_UINT8     shortScanRatio;         /* how many shorts scan for one long */
+    A_UINT8     scanCtrlFlags;
+    A_UINT16    minact_chdwell_time;    /* msec */
+    A_UINT16    maxact_scan_per_ssid;   /* max active scans per ssid */
+    A_UINT32    max_dfsch_act_time;  /* msecs */
+} POSTPACK WMI_SCAN_PARAMS_CMD;
+
+/*
+ * WMI_SET_BSS_FILTER_CMDID
+ */
+typedef enum {
+    NONE_BSS_FILTER = 0x0,              /* no beacons forwarded */
+    ALL_BSS_FILTER,                     /* all beacons forwarded */
+    PROFILE_FILTER,                     /* only beacons matching profile */
+    ALL_BUT_PROFILE_FILTER,             /* all but beacons matching profile */
+    CURRENT_BSS_FILTER,                 /* only beacons matching current BSS */
+    ALL_BUT_BSS_FILTER,                 /* all but beacons matching BSS */
+    PROBED_SSID_FILTER,                 /* beacons matching probed ssid */
+    LAST_BSS_FILTER,                    /* marker only */
+} WMI_BSS_FILTER;
+
+typedef PREPACK struct {
+    A_UINT8    bssFilter;                      /* see WMI_BSS_FILTER */
+    A_UINT8    reserved1;                      /* For alignment */
+    A_UINT16   reserved2;                      /* For alignment */
+    A_UINT32   ieMask;
+} POSTPACK WMI_BSS_FILTER_CMD;
+
+/*
+ * WMI_SET_PROBED_SSID_CMDID
+ */
+#define MAX_PROBED_SSID_INDEX   9
+
+typedef enum {
+    DISABLE_SSID_FLAG  = 0,                  /* disables entry */
+    SPECIFIC_SSID_FLAG = 0x01,               /* probes specified ssid */
+    ANY_SSID_FLAG      = 0x02,               /* probes for any ssid */
+} WMI_SSID_FLAG;
+
+typedef PREPACK struct {
+    A_UINT8     entryIndex;                     /* 0 to MAX_PROBED_SSID_INDEX */
+    A_UINT8     flag;                           /* WMI_SSID_FLG */
+    A_UINT8     ssidLength;
+    A_UINT8     ssid[32];
+} POSTPACK WMI_PROBED_SSID_CMD;
+
+/*
+ * WMI_SET_LISTEN_INT_CMDID
+ * The Listen interval is between 15 and 3000 TUs
+ */
+#define MIN_LISTEN_INTERVAL 15
+#define MAX_LISTEN_INTERVAL 5000
+#define MIN_LISTEN_BEACONS 1
+#define MAX_LISTEN_BEACONS 50
+
+typedef PREPACK struct {
+    A_UINT16     listenInterval;
+    A_UINT16     numBeacons;
+} POSTPACK WMI_LISTEN_INT_CMD;
+
+/*
+ * WMI_SET_BEACON_INT_CMDID
+ */
+typedef PREPACK struct {
+    A_UINT16     beaconInterval;
+} POSTPACK WMI_BEACON_INT_CMD;
+
+/*
+ * WMI_SET_BMISS_TIME_CMDID
+ * valid values are between 1000 and 5000 TUs
+ */
+
+#define MIN_BMISS_TIME     1000
+#define MAX_BMISS_TIME     5000
+#define MIN_BMISS_BEACONS  1
+#define MAX_BMISS_BEACONS  50
+
+typedef PREPACK struct {
+    A_UINT16     bmissTime;
+    A_UINT16     numBeacons;
+} POSTPACK WMI_BMISS_TIME_CMD;
+
+/*
+ * WMI_SET_POWER_MODE_CMDID
+ */
+typedef enum {
+    REC_POWER = 0x01,
+    MAX_PERF_POWER,
+} WMI_POWER_MODE;
+
+typedef PREPACK struct {
+    A_UINT8     powerMode;      /* WMI_POWER_MODE */
+} POSTPACK WMI_POWER_MODE_CMD;
+
+typedef PREPACK struct {
+    A_INT8 status;      /* WMI_SET_PARAMS_REPLY */
+} POSTPACK WMI_SET_PARAMS_REPLY;
+
+typedef PREPACK struct {
+    A_UINT32 opcode;
+    A_UINT32 length;
+    A_CHAR buffer[1];      /* WMI_SET_PARAMS */
+} POSTPACK WMI_SET_PARAMS_CMD;
+
+typedef PREPACK struct {
+    A_UINT8 multicast_mac[ATH_MAC_LEN];      /* WMI_SET_MCAST_FILTER */
+} POSTPACK WMI_SET_MCAST_FILTER_CMD;
+
+typedef PREPACK struct {
+    A_UINT8 enable;      /* WMI_MCAST_FILTER */
+} POSTPACK WMI_MCAST_FILTER_CMD;
+
+/*
+ * WMI_SET_POWER_PARAMS_CMDID
+ */
+typedef enum {
+    IGNORE_DTIM = 0x01,
+    NORMAL_DTIM = 0x02,
+    STICK_DTIM  = 0x03,
+    AUTO_DTIM   = 0x04,
+} WMI_DTIM_POLICY;
+
+/* Policy to determnine whether TX should wakeup WLAN if sleeping */
+typedef enum {
+    TX_WAKEUP_UPON_SLEEP = 1,
+    TX_DONT_WAKEUP_UPON_SLEEP = 2
+} WMI_TX_WAKEUP_POLICY_UPON_SLEEP;
+
+/*
+ * Policy to determnine whether power save failure event should be sent to
+ * host during scanning
+ */
+typedef enum {
+    SEND_POWER_SAVE_FAIL_EVENT_ALWAYS = 1,
+    IGNORE_POWER_SAVE_FAIL_EVENT_DURING_SCAN = 2,
+} POWER_SAVE_FAIL_EVENT_POLICY;
+
+typedef PREPACK struct {
+    A_UINT16    idle_period;             /* msec */
+    A_UINT16    pspoll_number;
+    A_UINT16    dtim_policy;
+    A_UINT16    tx_wakeup_policy;
+    A_UINT16    num_tx_to_wakeup;
+    A_UINT16    ps_fail_event_policy;
+} POSTPACK WMI_POWER_PARAMS_CMD;
+
+/* Adhoc power save types */
+typedef enum {
+    ADHOC_PS_DISABLE=1,
+    ADHOC_PS_ATH=2,
+    ADHOC_PS_IEEE=3,
+    ADHOC_PS_OTHER=4,
+} WMI_ADHOC_PS_TYPE;
+
+typedef PREPACK struct {
+    A_UINT8    power_saving;
+    A_UINT8    ttl; /* number of beacon periods */
+    A_UINT16   atim_windows;          /* msec */
+    A_UINT16   timeout_value;         /* msec */
+} POSTPACK WMI_IBSS_PM_CAPS_CMD;
+
+/* AP power save types */
+typedef enum {
+    AP_PS_DISABLE=1,
+    AP_PS_ATH=2,
+} WMI_AP_PS_TYPE;
+
+typedef PREPACK struct {
+    A_UINT32   idle_time;   /* in msec */
+    A_UINT32   ps_period;   /* in usec */
+    A_UINT8    sleep_period; /* in ps periods */
+    A_UINT8    psType;
+} POSTPACK WMI_AP_PS_CMD;
+
+/*
+ * WMI_SET_POWERSAVE_TIMERS_POLICY_CMDID
+ */
+typedef enum {
+    IGNORE_TIM_ALL_QUEUES_APSD = 0,
+    PROCESS_TIM_ALL_QUEUES_APSD = 1,
+    IGNORE_TIM_SIMULATED_APSD = 2,
+    PROCESS_TIM_SIMULATED_APSD = 3,
+} APSD_TIM_POLICY;
+
+typedef PREPACK struct {
+    A_UINT16    psPollTimeout;          /* msec */
+    A_UINT16    triggerTimeout;         /* msec */
+    A_UINT32    apsdTimPolicy;      /* TIM behavior with  ques APSD enabled. Default is IGNORE_TIM_ALL_QUEUES_APSD */
+    A_UINT32    simulatedAPSDTimPolicy;      /* TIM behavior with  simulated APSD enabled. Default is PROCESS_TIM_SIMULATED_APSD */
+} POSTPACK WMI_POWERSAVE_TIMERS_POLICY_CMD;
+
+/*
+ * WMI_SET_VOICE_PKT_SIZE_CMDID
+ */
+typedef PREPACK struct {
+    A_UINT16    voicePktSize;
+} POSTPACK WMI_SET_VOICE_PKT_SIZE_CMD;
+
+/*
+ * WMI_SET_MAX_SP_LEN_CMDID
+ */
+typedef enum {
+    DELIVER_ALL_PKT = 0x0,
+    DELIVER_2_PKT = 0x1,
+    DELIVER_4_PKT = 0x2,
+    DELIVER_6_PKT = 0x3,
+} APSD_SP_LEN_TYPE;
+
+typedef PREPACK struct {
+    A_UINT8    maxSPLen;
+} POSTPACK WMI_SET_MAX_SP_LEN_CMD;
+
+/*
+ * WMI_SET_DISC_TIMEOUT_CMDID
+ */
+typedef PREPACK struct {
+    A_UINT8     disconnectTimeout;          /* seconds */
+} POSTPACK WMI_DISC_TIMEOUT_CMD;
+
+typedef enum {
+    UPLINK_TRAFFIC = 0,
+    DNLINK_TRAFFIC = 1,
+    BIDIR_TRAFFIC = 2,
+} DIR_TYPE;
+
+typedef enum {
+    DISABLE_FOR_THIS_AC = 0,
+    ENABLE_FOR_THIS_AC  = 1,
+    ENABLE_FOR_ALL_AC   = 2,
+} VOICEPS_CAP_TYPE;
+
+typedef enum {
+    TRAFFIC_TYPE_APERIODIC = 0,
+    TRAFFIC_TYPE_PERIODIC = 1,
+}TRAFFIC_TYPE;
+
+/*
+ * WMI_SYNCHRONIZE_CMDID
+ */
+typedef PREPACK struct {
+    A_UINT8 dataSyncMap;
+} POSTPACK WMI_SYNC_CMD;
+
+/*
+ * WMI_CREATE_PSTREAM_CMDID
+ */
+typedef PREPACK struct {
+    A_UINT32        minServiceInt;           /* in milli-sec */
+    A_UINT32        maxServiceInt;           /* in milli-sec */
+    A_UINT32        inactivityInt;           /* in milli-sec */
+    A_UINT32        suspensionInt;           /* in milli-sec */
+    A_UINT32        serviceStartTime;
+    A_UINT32        minDataRate;             /* in bps */
+    A_UINT32        meanDataRate;            /* in bps */
+    A_UINT32        peakDataRate;            /* in bps */
+    A_UINT32        maxBurstSize;
+    A_UINT32        delayBound;
+    A_UINT32        minPhyRate;              /* in bps */
+    A_UINT32        sba;
+    A_UINT32        mediumTime;
+    A_UINT16        nominalMSDU;             /* in octects */
+    A_UINT16        maxMSDU;                 /* in octects */
+    A_UINT8         trafficClass;
+    A_UINT8         trafficDirection;        /* DIR_TYPE */
+    A_UINT8         rxQueueNum;
+    A_UINT8         trafficType;             /* TRAFFIC_TYPE */
+    A_UINT8         voicePSCapability;       /* VOICEPS_CAP_TYPE */
+    A_UINT8         tsid;
+    A_UINT8         userPriority;            /* 802.1D user priority */
+    A_UINT8         nominalPHY;              /* nominal phy rate */
+} POSTPACK WMI_CREATE_PSTREAM_CMD;
+
+/*
+ * WMI_DELETE_PSTREAM_CMDID
+ */
+typedef PREPACK struct {
+    A_UINT8     txQueueNumber;
+    A_UINT8     rxQueueNumber;
+    A_UINT8     trafficDirection;
+    A_UINT8     trafficClass;
+    A_UINT8     tsid;
+} POSTPACK WMI_DELETE_PSTREAM_CMD;
+
+/*
+ * WMI_SET_CHANNEL_PARAMS_CMDID
+ */
+typedef enum {
+    WMI_11A_MODE  = 0x1,
+    WMI_11G_MODE  = 0x2,
+    WMI_11AG_MODE = 0x3,
+    WMI_11B_MODE  = 0x4,
+    WMI_11GONLY_MODE = 0x5,    
+} WMI_PHY_MODE;
+
+#define WMI_MAX_CHANNELS        32
+
+typedef PREPACK struct {
+    A_UINT8     reserved1;
+    A_UINT8     scanParam;              /* set if enable scan */
+    A_UINT8     phyMode;                /* see WMI_PHY_MODE */
+    A_UINT8     numChannels;            /* how many channels follow */
+    A_UINT16    channelList[1];         /* channels in Mhz */
+} POSTPACK WMI_CHANNEL_PARAMS_CMD;
+
+
+/*
+ *  WMI_RSSI_THRESHOLD_PARAMS_CMDID
+ *  Setting the polltime to 0 would disable polling.
+ *  Threshold values are in the ascending order, and should agree to:
+ *  (lowThreshold_lowerVal < lowThreshold_upperVal < highThreshold_lowerVal
+ *      < highThreshold_upperVal)
+ */
+
+typedef PREPACK struct WMI_RSSI_THRESHOLD_PARAMS{
+    A_UINT32    pollTime;               /* Polling time as a factor of LI */
+    A_INT16     thresholdAbove1_Val;          /* lowest of upper */
+    A_INT16     thresholdAbove2_Val;
+    A_INT16     thresholdAbove3_Val;
+    A_INT16     thresholdAbove4_Val;
+    A_INT16     thresholdAbove5_Val;
+    A_INT16     thresholdAbove6_Val;          /* highest of upper */
+    A_INT16     thresholdBelow1_Val;         /* lowest of bellow */
+    A_INT16     thresholdBelow2_Val;
+    A_INT16     thresholdBelow3_Val;
+    A_INT16     thresholdBelow4_Val;
+    A_INT16     thresholdBelow5_Val;
+    A_INT16     thresholdBelow6_Val;         /* highest of bellow */
+    A_UINT8     weight;                  /* "alpha" */
+    A_UINT8     reserved[3];
+} POSTPACK  WMI_RSSI_THRESHOLD_PARAMS_CMD;
+
+/*
+ *  WMI_SNR_THRESHOLD_PARAMS_CMDID
+ *  Setting the polltime to 0 would disable polling.
+ */
+
+typedef PREPACK struct WMI_SNR_THRESHOLD_PARAMS{
+    A_UINT32    pollTime;               /* Polling time as a factor of LI */
+    A_UINT8     weight;                  /* "alpha" */
+    A_UINT8     thresholdAbove1_Val;      /* lowest of uppper*/
+    A_UINT8     thresholdAbove2_Val;
+    A_UINT8     thresholdAbove3_Val;
+    A_UINT8     thresholdAbove4_Val;      /* highest of upper */
+    A_UINT8     thresholdBelow1_Val;     /* lowest of bellow */
+    A_UINT8     thresholdBelow2_Val;
+    A_UINT8     thresholdBelow3_Val;
+    A_UINT8     thresholdBelow4_Val;     /* highest of bellow */
+    A_UINT8     reserved[3];
+} POSTPACK WMI_SNR_THRESHOLD_PARAMS_CMD;
+
+/*
+ *  WMI_LQ_THRESHOLD_PARAMS_CMDID
+ */
+typedef PREPACK struct WMI_LQ_THRESHOLD_PARAMS {
+    A_UINT8     enable;
+    A_UINT8     thresholdAbove1_Val;
+    A_UINT8     thresholdAbove2_Val;
+    A_UINT8     thresholdAbove3_Val;
+    A_UINT8     thresholdAbove4_Val;
+    A_UINT8     thresholdBelow1_Val;
+    A_UINT8     thresholdBelow2_Val;
+    A_UINT8     thresholdBelow3_Val;
+    A_UINT8     thresholdBelow4_Val;
+    A_UINT8     reserved[3];
+} POSTPACK  WMI_LQ_THRESHOLD_PARAMS_CMD;
+
+typedef enum {
+    WMI_LPREAMBLE_DISABLED = 0,
+    WMI_LPREAMBLE_ENABLED
+} WMI_LPREAMBLE_STATUS;
+
+typedef enum {
+    WMI_IGNORE_BARKER_IN_ERP = 0,
+    WMI_DONOT_IGNORE_BARKER_IN_ERP
+} WMI_PREAMBLE_POLICY;
+
+typedef PREPACK struct {
+    A_UINT8     status;
+    A_UINT8     preamblePolicy;
+}POSTPACK WMI_SET_LPREAMBLE_CMD;
+
+typedef PREPACK struct {
+    A_UINT16    threshold;
+}POSTPACK WMI_SET_RTS_CMD;
+
+/*
+ *  WMI_TARGET_ERROR_REPORT_BITMASK_CMDID
+ *  Sets the error reporting event bitmask in target. Target clears it
+ *  upon an error. Subsequent errors are counted, but not reported
+ *  via event, unless the bitmask is set again.
+ */
+typedef PREPACK struct {
+    A_UINT32    bitmask;
+} POSTPACK  WMI_TARGET_ERROR_REPORT_BITMASK;
+
+/*
+ * WMI_SET_TX_PWR_CMDID
+ */
+typedef PREPACK struct {
+    A_UINT8     dbM;                  /* in dbM units */
+} POSTPACK WMI_SET_TX_PWR_CMD, WMI_TX_PWR_REPLY;
+
+/*
+ * WMI_SET_ASSOC_INFO_CMDID
+ *
+ * A maximum of 2 private IEs can be sent in the [Re]Assoc request.
+ * A 3rd one, the CCX version IE can also be set from the host.
+ */
+#define WMI_MAX_ASSOC_INFO_TYPE    2
+#define WMI_CCX_VER_IE             2 /* ieType to set CCX Version IE */
+
+#define WMI_MAX_ASSOC_INFO_LEN     240
+
+typedef PREPACK struct {
+    A_UINT8     ieType;
+    A_UINT8     bufferSize;
+    A_UINT8     assocInfo[1];       /* up to WMI_MAX_ASSOC_INFO_LEN */
+} POSTPACK WMI_SET_ASSOC_INFO_CMD;
+
+
+/*
+ * WMI_GET_TX_PWR_CMDID does not take any parameters
+ */
+
+/*
+ * WMI_ADD_BAD_AP_CMDID
+ */
+#define WMI_MAX_BAD_AP_INDEX      1
+
+typedef PREPACK struct {
+    A_UINT8     badApIndex;         /* 0 to WMI_MAX_BAD_AP_INDEX */
+    A_UINT8     bssid[ATH_MAC_LEN];
+} POSTPACK WMI_ADD_BAD_AP_CMD;
+
+/*
+ * WMI_DELETE_BAD_AP_CMDID
+ */
+typedef PREPACK struct {
+    A_UINT8     badApIndex;         /* 0 to WMI_MAX_BAD_AP_INDEX */
+} POSTPACK WMI_DELETE_BAD_AP_CMD;
+
+/*
+ * WMI_SET_ACCESS_PARAMS_CMDID
+ */
+#define WMI_DEFAULT_TXOP_ACPARAM    0       /* implies one MSDU */
+#define WMI_DEFAULT_ECWMIN_ACPARAM  4       /* corresponds to CWmin of 15 */
+#define WMI_DEFAULT_ECWMAX_ACPARAM  10      /* corresponds to CWmax of 1023 */
+#define WMI_MAX_CW_ACPARAM          15      /* maximum eCWmin or eCWmax */
+#define WMI_DEFAULT_AIFSN_ACPARAM   2
+#define WMI_MAX_AIFSN_ACPARAM       15
+typedef PREPACK struct {
+    A_UINT16 txop;                      /* in units of 32 usec */
+    A_UINT8  eCWmin;
+    A_UINT8  eCWmax;
+    A_UINT8  aifsn;
+    A_UINT8  ac;
+} POSTPACK WMI_SET_ACCESS_PARAMS_CMD;
+
+
+/*
+ * WMI_SET_RETRY_LIMITS_CMDID
+ *
+ * This command is used to customize the number of retries the
+ * wlan device will perform on a given frame.
+ */
+#define WMI_MIN_RETRIES 2
+#define WMI_MAX_RETRIES 13
+typedef enum {
+    MGMT_FRAMETYPE    = 0,
+    CONTROL_FRAMETYPE = 1,
+    DATA_FRAMETYPE    = 2
+} WMI_FRAMETYPE;
+
+typedef PREPACK struct {
+    A_UINT8 frameType;                      /* WMI_FRAMETYPE */
+    A_UINT8 trafficClass;                   /* applies only to DATA_FRAMETYPE */
+    A_UINT8 maxRetries;
+    A_UINT8 enableNotify;
+} POSTPACK WMI_SET_RETRY_LIMITS_CMD;
+
+/*
+ * WMI_SET_ROAM_CTRL_CMDID
+ *
+ * This command is used to influence the Roaming behaviour
+ * Set the host biases of the BSSs before setting the roam mode as bias
+ * based.
+ */
+
+/*
+ * Different types of Roam Control
+ */
+
+typedef enum {
+        WMI_FORCE_ROAM          = 1,      /* Roam to the specified BSSID */
+        WMI_SET_ROAM_MODE       = 2,      /* default ,progd bias, no roam */
+        WMI_SET_HOST_BIAS       = 3,     /* Set the Host Bias */
+        WMI_SET_LOWRSSI_SCAN_PARAMS = 4, /* Set lowrssi Scan parameters */
+} WMI_ROAM_CTRL_TYPE;
+
+#define WMI_MIN_ROAM_CTRL_TYPE WMI_FORCE_ROAM
+#define WMI_MAX_ROAM_CTRL_TYPE WMI_SET_LOWRSSI_SCAN_PARAMS
+
+/*
+ * ROAM MODES
+ */
+
+typedef enum {
+        WMI_DEFAULT_ROAM_MODE   = 1,  /* RSSI based ROAM */
+        WMI_HOST_BIAS_ROAM_MODE = 2, /* HOST BIAS based ROAM */
+        WMI_LOCK_BSS_MODE  = 3  /* Lock to the Current BSS - no Roam */
+} WMI_ROAM_MODE;
+
+/*
+ * BSS HOST BIAS INFO
+ */
+
+typedef PREPACK struct {
+        A_UINT8 bssid[ATH_MAC_LEN];
+        A_INT8  bias;
+} POSTPACK WMI_BSS_BIAS;
+
+typedef PREPACK struct {
+        A_UINT8 numBss;
+        WMI_BSS_BIAS bssBias[1];
+} POSTPACK WMI_BSS_BIAS_INFO;
+
+typedef PREPACK struct WMI_LOWRSSI_SCAN_PARAMS {
+        A_UINT16 lowrssi_scan_period;
+        A_INT16  lowrssi_scan_threshold;
+        A_INT16  lowrssi_roam_threshold;
+        A_UINT8  roam_rssi_floor;
+        A_UINT8  reserved[1];              /* For alignment */
+} POSTPACK WMI_LOWRSSI_SCAN_PARAMS;
+
+typedef PREPACK struct {
+    PREPACK union {
+        A_UINT8 bssid[ATH_MAC_LEN]; /* WMI_FORCE_ROAM */
+        A_UINT8 roamMode;           /* WMI_SET_ROAM_MODE  */
+        WMI_BSS_BIAS_INFO bssBiasInfo; /* WMI_SET_HOST_BIAS */
+        WMI_LOWRSSI_SCAN_PARAMS lrScanParams;
+    } POSTPACK info;
+    A_UINT8   roamCtrlType ;
+} POSTPACK WMI_SET_ROAM_CTRL_CMD;
+
+/*
+ * WMI_SET_BT_WLAN_CONN_PRECEDENCE_CMDID
+ */
+typedef enum {
+    BT_WLAN_CONN_PRECDENCE_WLAN=0,  /* Default */
+    BT_WLAN_CONN_PRECDENCE_PAL,
+} BT_WLAN_CONN_PRECEDENCE;
+
+typedef PREPACK struct {
+    A_UINT8 precedence;
+} POSTPACK WMI_SET_BT_WLAN_CONN_PRECEDENCE;
+
+/*
+ * WMI_ENABLE_RM_CMDID
+ */
+typedef PREPACK struct {
+        A_BOOL enable_radio_measurements;
+} POSTPACK WMI_ENABLE_RM_CMD;
+
+/*
+ * WMI_SET_MAX_OFFHOME_DURATION_CMDID
+ */
+typedef PREPACK struct {
+        A_UINT8 max_offhome_duration;
+} POSTPACK WMI_SET_MAX_OFFHOME_DURATION_CMD;
+
+typedef PREPACK struct {
+    A_UINT32 frequency;
+    A_UINT8  threshold;
+} POSTPACK WMI_SET_HB_CHALLENGE_RESP_PARAMS_CMD;
+/*---------------------- BTCOEX RELATED -------------------------------------*/
+/*----------------------COMMON to AR6002 and AR6003 -------------------------*/
+typedef enum {
+    BT_STREAM_UNDEF = 0,
+    BT_STREAM_SCO,             /* SCO stream */
+    BT_STREAM_A2DP,            /* A2DP stream */
+    BT_STREAM_SCAN,            /* BT Discovery or Page */
+    BT_STREAM_ESCO,
+    BT_STREAM_MAX
+} BT_STREAM_TYPE;
+
+typedef enum {
+    BT_PARAM_SCO_PSPOLL_LATENCY_ONE_FOURTH =1,
+    BT_PARAM_SCO_PSPOLL_LATENCY_HALF,
+    BT_PARAM_SCO_PSPOLL_LATENCY_THREE_FOURTH,
+} BT_PARAMS_SCO_PSPOLL_LATENCY;
+
+typedef enum {
+    BT_PARAMS_SCO_STOMP_SCO_NEVER =1,
+    BT_PARAMS_SCO_STOMP_SCO_ALWAYS,
+    BT_PARAMS_SCO_STOMP_SCO_IN_LOWRSSI,
+} BT_PARAMS_SCO_STOMP_RULES;
+
+typedef enum {
+    BT_STATUS_UNDEF = 0,
+    BT_STATUS_ON,
+    BT_STATUS_OFF,
+    BT_STATUS_MAX
+} BT_STREAM_STATUS;
+
+typedef PREPACK struct {
+    A_UINT8 streamType;
+    A_UINT8 status;
+} POSTPACK WMI_SET_BT_STATUS_CMD;
+
+typedef enum {
+    BT_ANT_TYPE_UNDEF=0,
+    BT_ANT_TYPE_DUAL,
+    BT_ANT_TYPE_SPLITTER,
+    BT_ANT_TYPE_SWITCH,
+    BT_ANT_TYPE_HIGH_ISO_DUAL
+} BT_ANT_FRONTEND_CONFIG;
+
+typedef enum {
+    BT_COLOCATED_DEV_BTS4020=0,
+    BT_COLCATED_DEV_CSR ,
+    BT_COLOCATED_DEV_VALKYRIE
+} BT_COLOCATED_DEV_TYPE;
+
+/*********************** Applicable to AR6002 ONLY ******************************/
+
+typedef enum {
+    BT_PARAM_SCO = 1,         /* SCO stream parameters */
+    BT_PARAM_A2DP ,
+    BT_PARAM_ANTENNA_CONFIG,
+    BT_PARAM_COLOCATED_BT_DEVICE,
+    BT_PARAM_ACLCOEX,
+    BT_PARAM_11A_SEPARATE_ANT,
+    BT_PARAM_MAX
+} BT_PARAM_TYPE;
+
+
+#define BT_SCO_ALLOW_CLOSE_RANGE_OPT    (1 << 0)
+#define BT_SCO_FORCE_AWAKE_OPT          (1 << 1)
+#define BT_SCO_SET_RSSI_OVERRIDE(flags)        ((flags) |= (1 << 2))
+#define BT_SCO_GET_RSSI_OVERRIDE(flags)        (((flags) >> 2) & 0x1)
+#define BT_SCO_SET_RTS_OVERRIDE(flags)   ((flags) |= (1 << 3))
+#define BT_SCO_GET_RTS_OVERRIDE(flags)   (((flags) >> 3) & 0x1)
+#define BT_SCO_GET_MIN_LOW_RATE_CNT(flags)     (((flags) >> 8) & 0xFF)
+#define BT_SCO_GET_MAX_LOW_RATE_CNT(flags)     (((flags) >> 16) & 0xFF)
+#define BT_SCO_SET_MIN_LOW_RATE_CNT(flags,val) (flags) |= (((val) & 0xFF) << 8)
+#define BT_SCO_SET_MAX_LOW_RATE_CNT(flags,val) (flags) |= (((val) & 0xFF) << 16)
+
+typedef PREPACK struct {
+    A_UINT32 numScoCyclesForceTrigger;  /* Number SCO cycles after which
+                                           force a pspoll. default = 10 */
+    A_UINT32 dataResponseTimeout;       /* Timeout Waiting for Downlink pkt
+                                           in response for ps-poll,
+                                           default = 10 msecs */
+    A_UINT32  stompScoRules;
+    A_UINT32 scoOptFlags;               /* SCO Options Flags :
+                                            bits:     meaning:
+                                             0        Allow Close Range Optimization
+                                             1        Force awake during close range
+                                             2        If set use host supplied RSSI for OPT
+                                             3        If set use host supplied RTS COUNT for OPT
+                                             4..7     Unused
+                                             8..15    Low Data Rate Min Cnt
+                                             16..23   Low Data Rate Max Cnt
+                                        */
+
+    A_UINT8 stompDutyCyleVal;           /* Sco cycles to limit ps-poll queuing
+                                           if stomped */
+    A_UINT8 stompDutyCyleMaxVal;        /*firm ware increases stomp duty cycle
+                                          gradually uptill this value on need basis*/
+    A_UINT8 psPollLatencyFraction;      /* Fraction of idle
+                                           period, within which
+                                           additional ps-polls
+                                           can be queued */
+    A_UINT8 noSCOSlots;                 /* Number of SCO Tx/Rx slots.
+                                           HVx, EV3, 2EV3 = 2 */
+    A_UINT8 noIdleSlots;                /* Number of Bluetooth idle slots between
+                                           consecutive SCO Tx/Rx slots
+                                           HVx, EV3 = 4
+                                           2EV3 = 10 */
+    A_UINT8 scoOptOffRssi;/*RSSI value below which we go to ps poll*/
+    A_UINT8 scoOptOnRssi; /*RSSI value above which we reenter opt mode*/
+    A_UINT8 scoOptRtsCount;
+} POSTPACK BT_PARAMS_SCO;
+
+#define BT_A2DP_ALLOW_CLOSE_RANGE_OPT  (1 << 0)
+#define BT_A2DP_FORCE_AWAKE_OPT        (1 << 1)
+#define BT_A2DP_SET_RSSI_OVERRIDE(flags)        ((flags) |= (1 << 2))
+#define BT_A2DP_GET_RSSI_OVERRIDE(flags)        (((flags) >> 2) & 0x1)
+#define BT_A2DP_SET_RTS_OVERRIDE(flags)   ((flags) |= (1 << 3))
+#define BT_A2DP_GET_RTS_OVERRIDE(flags)   (((flags) >> 3) & 0x1)
+#define BT_A2DP_GET_MIN_LOW_RATE_CNT(flags)     (((flags) >> 8) & 0xFF)
+#define BT_A2DP_GET_MAX_LOW_RATE_CNT(flags)     (((flags) >> 16) & 0xFF)
+#define BT_A2DP_SET_MIN_LOW_RATE_CNT(flags,val) (flags) |= (((val) & 0xFF) << 8)
+#define BT_A2DP_SET_MAX_LOW_RATE_CNT(flags,val) (flags) |= (((val) & 0xFF) << 16)
+
+typedef PREPACK struct {
+    A_UINT32 a2dpWlanUsageLimit; /* MAX time firmware uses the medium for
+                                    wlan, after it identifies the idle time
+                                    default (30 msecs) */
+    A_UINT32 a2dpBurstCntMin;   /* Minimum number of bluetooth data frames
+                                   to replenish Wlan Usage  limit (default 3) */
+    A_UINT32 a2dpDataRespTimeout;
+    A_UINT32 a2dpOptFlags;      /* A2DP Option flags:
+                                       bits:    meaning:
+                                        0       Allow Close Range Optimization
+                                        1       Force awake during close range
+                                        2        If set use host supplied RSSI for OPT
+                                        3        If set use host supplied RTS COUNT for OPT
+                                        4..7    Unused
+                                        8..15   Low Data Rate Min Cnt
+                                        16..23  Low Data Rate Max Cnt
+                                 */
+    A_UINT8 isCoLocatedBtRoleMaster;
+    A_UINT8 a2dpOptOffRssi;/*RSSI value below which we go to ps poll*/
+    A_UINT8 a2dpOptOnRssi; /*RSSI value above which we reenter opt mode*/
+    A_UINT8 a2dpOptRtsCount;
+}POSTPACK BT_PARAMS_A2DP;
+
+/* During BT ftp/ BT OPP or any another data based acl profile on bluetooth
+   (non a2dp).*/
+typedef PREPACK struct {
+    A_UINT32 aclWlanMediumUsageTime;  /* Wlan usage time during Acl (non-a2dp)
+                                       coexistence (default 30 msecs) */
+    A_UINT32 aclBtMediumUsageTime;   /* Bt usage time during acl coexistence
+                                       (default 30 msecs)*/
+    A_UINT32 aclDataRespTimeout;
+    A_UINT32 aclDetectTimeout;      /* ACL coexistence enabled if we get
+                                       10 Pkts in X msec(default 100 msecs) */
+    A_UINT32 aclmaxPktCnt;          /* No of ACL pkts to receive before
+                                         enabling ACL coex */
+
+}POSTPACK BT_PARAMS_ACLCOEX;
+
+typedef PREPACK struct {
+    PREPACK union {
+        BT_PARAMS_SCO scoParams;
+        BT_PARAMS_A2DP a2dpParams;
+        BT_PARAMS_ACLCOEX  aclCoexParams;
+        A_UINT8 antType;         /* 0 -Disabled (default)
+                                     1 - BT_ANT_TYPE_DUAL
+                                     2 - BT_ANT_TYPE_SPLITTER
+                                     3 - BT_ANT_TYPE_SWITCH */
+        A_UINT8 coLocatedBtDev;  /* 0 - BT_COLOCATED_DEV_BTS4020 (default)
+                                     1 - BT_COLCATED_DEV_CSR
+                                     2 - BT_COLOCATED_DEV_VALKYRIe
+                                   */
+    } POSTPACK info;
+    A_UINT8 paramType ;
+} POSTPACK WMI_SET_BT_PARAMS_CMD;
+
+/************************ END AR6002 BTCOEX *******************************/
+/*-----------------------AR6003 BTCOEX -----------------------------------*/
+
+/*  ---------------WMI_SET_BTCOEX_FE_ANT_CMDID --------------------------*/
+/* Indicates front end antenna configuration. This command needs to be issued
+ * right after initialization and after WMI_SET_BTCOEX_COLOCATED_BT_DEV_CMDID.
+ * AR6003 enables coexistence and antenna switching based on the configuration.
+ */
+typedef enum {
+    WMI_BTCOEX_NOT_ENABLED = 0,
+    WMI_BTCOEX_FE_ANT_SINGLE =1,
+    WMI_BTCOEX_FE_ANT_DUAL=2,
+    WMI_BTCOEX_FE_ANT_DUAL_HIGH_ISO=3,
+    WMI_BTCOEX_FE_ANT_TYPE_MAX
+}WMI_BTCOEX_FE_ANT_TYPE;
+
+typedef PREPACK struct {
+	A_UINT8 btcoexFeAntType; /* 1 - WMI_BTCOEX_FE_ANT_SINGLE for single antenna front end
+                                2 - WMI_BTCOEX_FE_ANT_DUAL for dual antenna front end
+                                    (for isolations less 35dB, for higher isolation there
+                                    is not need to pass this command).
+                                    (not implemented)
+                              */
+}POSTPACK WMI_SET_BTCOEX_FE_ANT_CMD;
+
+/* -------------WMI_SET_BTCOEX_COLOCATED_BT_DEV_CMDID ----------------*/
+/* Indicate the bluetooth chip to the firmware. Firmware can have different algorithm based
+ * bluetooth chip type.Based on bluetooth device, different coexistence protocol would be used.
+ */
+typedef PREPACK struct {
+	A_UINT8	btcoexCoLocatedBTdev; /*1 - Qcom BT (3 -wire PTA)
+                                    2 - CSR BT  (3 wire PTA)
+                                    3 - Atheros 3001 BT (3 wire PTA)
+                                    4 - STE bluetooth (4-wire ePTA)
+                                    5 - Atheros 3002 BT (4-wire MCI)
+                                    defaults= 3 (Atheros 3001 BT )
+                                    */
+}POSTPACK WMI_SET_BTCOEX_COLOCATED_BT_DEV_CMD;
+
+/* -------------WMI_SET_BTCOEX_BTINQUIRY_PAGE_CONFIG_CMDID ------------*/
+/* Configuration parameters during bluetooth inquiry and page. Page configuration
+ * is applicable only on interfaces which can distinguish page (applicable only for ePTA -
+ * STE bluetooth).
+ * Bluetooth inquiry start and end is indicated via WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMDID.
+ * During this the station will be  power-save mode.
+ */
+typedef PREPACK struct {
+	A_UINT32 btInquiryDataFetchFrequency;/* The frequency of querying the AP for data
+                                            (via pspoll) is configured by this parameter.
+                                            "default = 10 ms" */
+
+	A_UINT32 protectBmissDurPostBtInquiry;/* The firmware will continue to be in inquiry state
+                                             for configured duration, after inquiry completion
+                                             . This is to ensure other bluetooth transactions
+                                             (RDP, SDP profiles, link key exchange ...etc)
+                                             goes through smoothly without wifi stomping.
+                                             default = 10 secs*/
+
+	A_UINT32 maxpageStomp;                 /*Applicable only for STE-BT interface. Currently not
+                                             used */
+	A_UINT32 btInquiryPageFlag;           /* Not used */
+}POSTPACK WMI_SET_BTCOEX_BTINQUIRY_PAGE_CONFIG_CMD;
+
+/*---------------------WMI_SET_BTCOEX_SCO_CONFIG_CMDID ---------------*/
+/* Configure  SCO parameters. These parameters would be used whenever firmware is indicated
+ * of (e)SCO profile on bluetooth ( via WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMDID).
+ * Configration of BTCOEX_SCO_CONFIG data structure are common configuration and applies
+ * ps-poll mode and opt mode.
+ * Ps-poll Mode - Station is in power-save and retrieves downlink data between sco gaps.
+ * Opt Mode - station is in awake state and access point can send data to station any time.
+ * BTCOEX_PSPOLLMODE_SCO_CONFIG - Configuration applied only during ps-poll mode.
+ * BTCOEX_OPTMODE_SCO_CONFIG - Configuration applied only during opt mode.
+ */
+#define WMI_SCO_CONFIG_FLAG_ALLOW_OPTIMIZATION   (1 << 0)
+#define WMI_SCO_CONFIG_FLAG_IS_EDR_CAPABLE       (1 << 1)
+#define WMI_SCO_CONFIG_FLAG_IS_BT_MASTER         (1 << 2)
+#define WMI_SCO_CONFIG_FLAG_FW_DETECT_OF_PER     (1 << 3)
+typedef PREPACK struct {
+	A_UINT32 scoSlots;					/* Number of SCO Tx/Rx slots.
+										   HVx, EV3, 2EV3 = 2 */
+	A_UINT32 scoIdleSlots;				/* Number of Bluetooth idle slots between
+										   consecutive SCO Tx/Rx slots
+										   HVx, EV3 = 4
+										   2EV3 = 10
+                                         */
+ 	A_UINT32 scoFlags;				   /* SCO Options Flags :
+										  bits:	   meaning:
+ 										  0   Allow Close Range Optimization
+ 										  1   Is EDR capable or Not
+ 										  2   IS Co-located Bt role Master
+                                          3   Firmware determines the periodicity of SCO.
+							  			 */
+
+    A_UINT32 linkId;                      /* applicable to STE-BT - not used */
+}POSTPACK BTCOEX_SCO_CONFIG;
+
+typedef PREPACK struct {
+	A_UINT32  scoCyclesForceTrigger;	/* Number SCO cycles after which
+											force a pspoll. default = 10 */
+    A_UINT32 scoDataResponseTimeout;	 /* Timeout Waiting for Downlink pkt
+											in response for ps-poll,
+											default = 20 msecs */
+
+	A_UINT32 scoStompDutyCyleVal;		 /* not implemented */
+
+	A_UINT32 scoStompDutyCyleMaxVal;     /*Not implemented */
+
+	A_UINT32 scoPsPollLatencyFraction; 	 /* Fraction of idle
+											period, within which
+											additional ps-polls can be queued
+                                            1 - 1/4 of idle duration
+                                            2 - 1/2 of idle duration
+                                            3 - 3/4 of idle duration
+                                            default =2 (1/2)
+                                           */
+}POSTPACK BTCOEX_PSPOLLMODE_SCO_CONFIG;
+
+typedef PREPACK struct {
+	A_UINT32 scoStompCntIn100ms;/*max number of SCO stomp in 100ms allowed in
+                                   opt mode. If exceeds the configured value,
+                                   switch to ps-poll mode
+                                  default = 3 */
+
+	A_UINT32 scoContStompMax;   /* max number of continous stomp allowed in opt mode.
+                                   if excedded switch to pspoll mode
+                                    default = 3 */
+
+	A_UINT32 scoMinlowRateMbps; /* Low rate threshold */
+
+	A_UINT32 scoLowRateCnt;     /* number of low rate pkts (< scoMinlowRateMbps) allowed in 100 ms.
+                                   If exceeded switch/stay to ps-poll mode, lower stay in opt mode.
+                                   default = 36
+                                 */
+
+	A_UINT32 scoHighPktRatio;   /*(Total Rx pkts in 100 ms + 1)/
+                                  ((Total tx pkts in 100 ms - No of high rate pkts in 100 ms) + 1) in 100 ms,
+                                  if exceeded switch/stay in opt mode and if lower switch/stay in  pspoll mode.
+                                  default = 5 (80% of high rates)
+                                 */
+
+	A_UINT32 scoMaxAggrSize;    /* Max number of Rx subframes allowed in this mode. (Firmware re-negogiates
+                                   max number of aggregates if it was negogiated to higher value
+                                   default = 1
+                                   Recommended value Basic rate headsets = 1, EDR (2-EV3)  =4.
+                                 */
+}POSTPACK BTCOEX_OPTMODE_SCO_CONFIG;
+
+typedef PREPACK struct {
+    A_UINT32 scanInterval;
+    A_UINT32 maxScanStompCnt;
+}POSTPACK BTCOEX_WLANSCAN_SCO_CONFIG;
+
+typedef PREPACK struct {
+	BTCOEX_SCO_CONFIG scoConfig;
+	BTCOEX_PSPOLLMODE_SCO_CONFIG scoPspollConfig;
+	BTCOEX_OPTMODE_SCO_CONFIG scoOptModeConfig;
+	BTCOEX_WLANSCAN_SCO_CONFIG scoWlanScanConfig;
+}POSTPACK WMI_SET_BTCOEX_SCO_CONFIG_CMD;
+
+/* ------------------WMI_SET_BTCOEX_A2DP_CONFIG_CMDID -------------------*/
+/* Configure A2DP profile parameters. These parameters would be used whenver firmware is indicated
+ * of A2DP profile on bluetooth ( via WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMDID).
+ * Configuration of BTCOEX_A2DP_CONFIG data structure are common configuration and applies to
+ * ps-poll mode and opt mode.
+ * Ps-poll Mode - Station is in power-save and retrieves downlink data between a2dp data bursts.
+ * Opt Mode - station is in power save during a2dp bursts and awake in the gaps.
+ * BTCOEX_PSPOLLMODE_A2DP_CONFIG - Configuration applied only during ps-poll mode.
+ * BTCOEX_OPTMODE_A2DP_CONFIG - Configuration applied only during opt mode.
+ */
+
+#define WMI_A2DP_CONFIG_FLAG_ALLOW_OPTIMIZATION    (1 << 0)
+#define WMI_A2DP_CONFIG_FLAG_IS_EDR_CAPABLE        (1 << 1)
+#define WMI_A2DP_CONFIG_FLAG_IS_BT_ROLE_MASTER     (1 << 2)
+#define WMI_A2DP_CONFIG_FLAG_IS_A2DP_HIGH_PRI      (1 << 3)
+#define WMI_A2DP_CONFIG_FLAG_FIND_BT_ROLE          (1 << 4)
+
+typedef PREPACK struct {
+    A_UINT32 a2dpFlags;      /* A2DP Option flags:
+		                        bits:    meaning:
+               		            0       Allow Close Range Optimization
+       	                     	1       IS EDR capable
+       	                     	2       IS Co-located Bt role Master
+                                3       a2dp traffic is high priority
+                                4       Fw detect the role of bluetooth.
+                             */
+	A_UINT32 linkId;         /* Applicable only to STE-BT - not used */
+
+}POSTPACK BTCOEX_A2DP_CONFIG;
+
+typedef PREPACK struct {
+    A_UINT32 a2dpWlanMaxDur; /* MAX time firmware uses the medium for
+                      			wlan, after it identifies the idle time
+                                default (30 msecs) */
+
+    A_UINT32 a2dpMinBurstCnt;   /* Minimum number of bluetooth data frames
+                  				to replenish Wlan Usage  limit (default 3) */
+
+    A_UINT32 a2dpDataRespTimeout; /* Max duration firmware waits for downlink
+                                     by stomping on  bluetooth
+                                     after ps-poll is acknowledged.
+                                     default = 20 ms
+                                   */
+}POSTPACK BTCOEX_PSPOLLMODE_A2DP_CONFIG;
+
+typedef PREPACK struct {
+	A_UINT32 a2dpMinlowRateMbps;  /* Low rate threshold */
+
+	A_UINT32 a2dpLowRateCnt;    /* number of low rate pkts (< a2dpMinlowRateMbps) allowed in 100 ms.
+                                   If exceeded switch/stay to ps-poll mode, lower stay in opt mode.
+                                   default = 36
+                                 */
+
+	A_UINT32 a2dpHighPktRatio;   /*(Total Rx pkts in 100 ms + 1)/
+                                  ((Total tx pkts in 100 ms - No of high rate pkts in 100 ms) + 1) in 100 ms,
+                                  if exceeded switch/stay in opt mode and if lower switch/stay in  pspoll mode.
+                                  default = 5 (80% of high rates)
+                                 */
+
+	A_UINT32 a2dpMaxAggrSize;    /* Max number of Rx subframes allowed in this mode. (Firmware re-negogiates
+                                   max number of aggregates if it was negogiated to higher value
+                                   default = 1
+                                  Recommended value Basic rate headsets = 1, EDR (2-EV3)  =8.
+                                 */
+	A_UINT32 a2dpPktStompCnt;    /*number of a2dp pkts that can be stomped per burst.
+                                   default = 6*/
+
+}POSTPACK BTCOEX_OPTMODE_A2DP_CONFIG;
+
+typedef PREPACK struct {
+	BTCOEX_A2DP_CONFIG a2dpConfig;
+	BTCOEX_PSPOLLMODE_A2DP_CONFIG a2dppspollConfig;
+	BTCOEX_OPTMODE_A2DP_CONFIG a2dpOptConfig;
+}POSTPACK WMI_SET_BTCOEX_A2DP_CONFIG_CMD;
+
+/*------------ WMI_SET_BTCOEX_ACLCOEX_CONFIG_CMDID---------------------*/
+/* Configure non-A2dp ACL profile parameters.The starts of ACL profile can either be
+ * indicated via WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMDID orenabled via firmware detection
+ *  which is configured via "aclCoexFlags".
+ * Configration of BTCOEX_ACLCOEX_CONFIG data structure are common configuration and applies
+ * ps-poll mode and opt mode.
+ * Ps-poll Mode - Station is in power-save and retrieves downlink data during wlan medium.
+ * Opt Mode - station is in power save during bluetooth medium time and awake during wlan duration.
+ *             (Not implemented yet)
+ *
+ * BTCOEX_PSPOLLMODE_ACLCOEX_CONFIG - Configuration applied only during ps-poll mode.
+ * BTCOEX_OPTMODE_ACLCOEX_CONFIG - Configuration applied only during opt mode.
+ */
+
+#define WMI_ACLCOEX_FLAGS_ALLOW_OPTIMIZATION   (1 << 0)
+#define WMI_ACLCOEX_FLAGS_DISABLE_FW_DETECTION (1 << 1)
+
+typedef PREPACK struct {
+    A_UINT32 aclWlanMediumDur; 	    /* Wlan usage time during Acl (non-a2dp)
+                     					coexistence (default 30 msecs)
+                                    */
+
+    A_UINT32 aclBtMediumDur; 	   /* Bt usage time during acl coexistence
+					                     (default 30 msecs)
+                                   */
+
+	A_UINT32 aclDetectTimeout;	   /* BT activity observation time limit.
+									  In this time duration, number of bt pkts are counted.
+									  If the Cnt reaches "aclPktCntLowerLimit" value
+									  for "aclIterToEnableCoex" iteration continuously,
+									  firmware gets into ACL coexistence mode.
+									  Similarly, if bt traffic count during ACL coexistence
+									  has not reached "aclPktCntLowerLimit" continuously
+									  for "aclIterToEnableCoex", then ACL coexistence is
+									  disabled.
+    								  -default 100 msecs
+                                    */
+
+	 A_UINT32 aclPktCntLowerLimit;   /* Acl Pkt Cnt to be received in duration of
+										"aclDetectTimeout" for
+										"aclIterForEnDis" times to enabling ACL coex.
+                                        Similar logic is used to disable acl coexistence.
+                                        (If "aclPktCntLowerLimit"  cnt of acl pkts
+                                         are not seen by the for "aclIterForEnDis"
+                                         then acl coexistence is disabled).
+                                        default = 10
+                                   */
+
+	 A_UINT32 aclIterForEnDis;      /* number of Iteration of "aclPktCntLowerLimit" for Enabling and
+                                       Disabling Acl Coexistence.
+                                       default = 3
+                                     */
+
+	 A_UINT32 aclPktCntUpperLimit; /* This is upperBound limit, if there is more than
+									  "aclPktCntUpperLimit" seen in "aclDetectTimeout",
+									  ACL coexistence is enabled right away.
+									  - default 15*/
+
+	A_UINT32 aclCoexFlags;			/* A2DP Option flags:
+		  	                          bits:    meaning:
+       		                          0       Allow Close Range Optimization
+                    		          1       disable Firmware detection
+                                      (Currently supported configuration is aclCoexFlags =0)
+                      			 	*/
+	A_UINT32 linkId;                /* Applicable only for STE-BT - not used */
+
+}POSTPACK BTCOEX_ACLCOEX_CONFIG;
+
+typedef PREPACK struct {
+    A_UINT32 aclDataRespTimeout;   /* Max duration firmware waits for downlink
+                                      by stomping on  bluetooth
+                                      after ps-poll is acknowledged.
+                                     default = 20 ms */
+
+}POSTPACK BTCOEX_PSPOLLMODE_ACLCOEX_CONFIG;
+
+
+/* Not implemented yet*/
+typedef PREPACK struct {
+	A_UINT32 aclCoexMinlowRateMbps;
+	A_UINT32 aclCoexLowRateCnt;
+	A_UINT32 aclCoexHighPktRatio;
+	A_UINT32 aclCoexMaxAggrSize;
+	A_UINT32 aclPktStompCnt;
+}POSTPACK BTCOEX_OPTMODE_ACLCOEX_CONFIG;
+
+typedef PREPACK struct {
+	BTCOEX_ACLCOEX_CONFIG aclCoexConfig;
+	BTCOEX_PSPOLLMODE_ACLCOEX_CONFIG aclCoexPspollConfig;
+	BTCOEX_OPTMODE_ACLCOEX_CONFIG aclCoexOptConfig;
+}POSTPACK WMI_SET_BTCOEX_ACLCOEX_CONFIG_CMD;
+
+/* -----------WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMDID ------------------*/
+typedef enum {
+	WMI_BTCOEX_BT_PROFILE_SCO =1,
+	WMI_BTCOEX_BT_PROFILE_A2DP,
+	WMI_BTCOEX_BT_PROFILE_INQUIRY_PAGE,
+	WMI_BTCOEX_BT_PROFILE_ACLCOEX,
+}WMI_BTCOEX_BT_PROFILE;
+
+typedef PREPACK struct {
+	A_UINT32 btProfileType;
+	A_UINT32 btOperatingStatus;
+	A_UINT32 btLinkId;
+}WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMD;
+
+/*--------------------- WMI_SET_BTCOEX_DEBUG_CMDID ---------------------*/
+/* Used for firmware development and debugging */
+typedef PREPACK struct {
+	A_UINT32 btcoexDbgParam1;
+	A_UINT32 btcoexDbgParam2;
+	A_UINT32 btcoexDbgParam3;
+	A_UINT32 btcoexDbgParam4;
+	A_UINT32 btcoexDbgParam5;
+}WMI_SET_BTCOEX_DEBUG_CMD;
+
+/*---------------------WMI_GET_BTCOEX_CONFIG_CMDID --------------------- */
+/* Command to firmware to get configuration parameters of the bt profile
+ * reported via WMI_BTCOEX_CONFIG_EVENTID */
+typedef PREPACK struct {
+	A_UINT32 btProfileType; /* 1 - SCO
+                               2 - A2DP
+                               3 - INQUIRY_PAGE
+                               4 - ACLCOEX
+                            */
+	A_UINT32 linkId;    /* not used */
+}WMI_GET_BTCOEX_CONFIG_CMD;
+
+/*------------------WMI_REPORT_BTCOEX_CONFIG_EVENTID------------------- */
+/* Event from firmware to host, sent in response to WMI_GET_BTCOEX_CONFIG_CMDID
+ * */
+typedef PREPACK struct {
+	A_UINT32 btProfileType;
+	A_UINT32 linkId; /* not used */
+	PREPACK union {
+		WMI_SET_BTCOEX_SCO_CONFIG_CMD scoConfigCmd;
+		WMI_SET_BTCOEX_A2DP_CONFIG_CMD a2dpConfigCmd;
+		WMI_SET_BTCOEX_ACLCOEX_CONFIG_CMD aclcoexConfig;
+        WMI_SET_BTCOEX_BTINQUIRY_PAGE_CONFIG_CMD btinquiryPageConfigCmd;
+    } POSTPACK info;
+} POSTPACK WMI_BTCOEX_CONFIG_EVENT;
+
+/*------------- WMI_REPORT_BTCOEX_BTCOEX_STATS_EVENTID--------------------*/
+/* Used for firmware development and debugging*/
+typedef PREPACK struct {
+	A_UINT32 highRatePktCnt;
+	A_UINT32 firstBmissCnt;
+	A_UINT32 psPollFailureCnt;
+	A_UINT32 nullFrameFailureCnt;
+	A_UINT32 optModeTransitionCnt;
+}BTCOEX_GENERAL_STATS;
+
+typedef PREPACK struct {
+	A_UINT32	scoStompCntAvg;
+	A_UINT32	scoStompIn100ms;
+	A_UINT32 	scoMaxContStomp;
+	A_UINT32	scoAvgNoRetries;
+	A_UINT32	scoMaxNoRetriesIn100ms;
+}BTCOEX_SCO_STATS;
+
+typedef PREPACK struct {
+	A_UINT32  	a2dpBurstCnt;
+	A_UINT32	a2dpMaxBurstCnt;
+	A_UINT32	a2dpAvgIdletimeIn100ms;
+	A_UINT32	a2dpAvgStompCnt;
+}BTCOEX_A2DP_STATS;
+
+typedef PREPACK struct {
+	A_UINT32	aclPktCntInBtTime;
+	A_UINT32	aclStompCntInWlanTime;
+	A_UINT32	aclPktCntIn100ms;
+}BTCOEX_ACLCOEX_STATS;
+
+typedef PREPACK struct {
+	BTCOEX_GENERAL_STATS coexStats;
+	BTCOEX_SCO_STATS scoStats;
+	BTCOEX_A2DP_STATS a2dpStats;
+	BTCOEX_ACLCOEX_STATS aclCoexStats;
+}WMI_BTCOEX_STATS_EVENT;
+
+
+/*--------------------------END OF BTCOEX -------------------------------------*/
+typedef PREPACK struct {
+    A_UINT32 sleepState;
+}WMI_REPORT_SLEEP_STATE_EVENT;
+
+typedef enum {
+    WMI_REPORT_SLEEP_STATUS_IS_DEEP_SLEEP =0,
+    WMI_REPORT_SLEEP_STATUS_IS_AWAKE
+} WMI_REPORT_SLEEP_STATUS;
+typedef enum {
+    DISCONN_EVT_IN_RECONN = 0,  /* default */
+    NO_DISCONN_EVT_IN_RECONN
+} TARGET_EVENT_REPORT_CONFIG;
+
+typedef PREPACK struct {
+    A_UINT32 evtConfig;
+} POSTPACK WMI_SET_TARGET_EVENT_REPORT_CMD;
+
+
+typedef PREPACK struct {
+    A_UINT16    cmd_buf_sz;     /* HCI cmd buffer size */
+    A_UINT8     buf[1];         /* Absolute HCI cmd */
+} POSTPACK WMI_HCI_CMD;
+
+/*
+ * Command Replies
+ */
+
+/*
+ * WMI_GET_CHANNEL_LIST_CMDID reply
+ */
+typedef PREPACK struct {
+    A_UINT8     reserved1;
+    A_UINT8     numChannels;            /* number of channels in reply */
+    A_UINT16    channelList[1];         /* channel in Mhz */
+} POSTPACK WMI_CHANNEL_LIST_REPLY;
+
+typedef enum {
+    A_SUCCEEDED = A_OK,
+    A_FAILED_DELETE_STREAM_DOESNOT_EXIST=250,
+    A_SUCCEEDED_MODIFY_STREAM=251,
+    A_FAILED_INVALID_STREAM = 252,
+    A_FAILED_MAX_THINSTREAMS = 253,
+    A_FAILED_CREATE_REMOVE_PSTREAM_FIRST = 254,
+} PSTREAM_REPLY_STATUS;
+
+typedef PREPACK struct {
+    A_UINT8     status;                 /* PSTREAM_REPLY_STATUS */
+    A_UINT8     txQueueNumber;
+    A_UINT8     rxQueueNumber;
+    A_UINT8     trafficClass;
+    A_UINT8     trafficDirection;       /* DIR_TYPE */
+} POSTPACK WMI_CRE_PRIORITY_STREAM_REPLY;
+
+typedef PREPACK struct {
+    A_UINT8     status;                 /* PSTREAM_REPLY_STATUS */
+    A_UINT8     txQueueNumber;
+    A_UINT8     rxQueueNumber;
+    A_UINT8     trafficDirection;       /* DIR_TYPE */
+    A_UINT8     trafficClass;
+} POSTPACK WMI_DEL_PRIORITY_STREAM_REPLY;
+
+/*
+ * List of Events (target to host)
+ */
+typedef enum {
+    WMI_READY_EVENTID           = 0x1001,
+    WMI_CONNECT_EVENTID,
+    WMI_DISCONNECT_EVENTID,
+    WMI_BSSINFO_EVENTID,
+    WMI_CMDERROR_EVENTID,
+    WMI_REGDOMAIN_EVENTID,
+    WMI_PSTREAM_TIMEOUT_EVENTID,
+    WMI_NEIGHBOR_REPORT_EVENTID,
+    WMI_TKIP_MICERR_EVENTID,
+    WMI_SCAN_COMPLETE_EVENTID,           /* 0x100a */
+    WMI_REPORT_STATISTICS_EVENTID,
+    WMI_RSSI_THRESHOLD_EVENTID,
+    WMI_ERROR_REPORT_EVENTID,
+    WMI_OPT_RX_FRAME_EVENTID,
+    WMI_REPORT_ROAM_TBL_EVENTID,
+    WMI_EXTENSION_EVENTID,
+    WMI_CAC_EVENTID,
+    WMI_SNR_THRESHOLD_EVENTID,
+    WMI_LQ_THRESHOLD_EVENTID,
+    WMI_TX_RETRY_ERR_EVENTID,            /* 0x1014 */
+    WMI_REPORT_ROAM_DATA_EVENTID,
+    WMI_TEST_EVENTID,
+    WMI_APLIST_EVENTID,
+    WMI_GET_WOW_LIST_EVENTID,
+    WMI_GET_PMKID_LIST_EVENTID,
+    WMI_CHANNEL_CHANGE_EVENTID,
+    WMI_PEER_NODE_EVENTID,
+    WMI_PSPOLL_EVENTID,
+    WMI_DTIMEXPIRY_EVENTID,
+    WMI_WLAN_VERSION_EVENTID,
+    WMI_SET_PARAMS_REPLY_EVENTID,
+    WMI_ADDBA_REQ_EVENTID,              /*0x1020 */
+    WMI_ADDBA_RESP_EVENTID,
+    WMI_DELBA_REQ_EVENTID,
+    WMI_TX_COMPLETE_EVENTID,
+    WMI_HCI_EVENT_EVENTID,
+    WMI_ACL_DATA_EVENTID,
+    WMI_REPORT_SLEEP_STATE_EVENTID,
+#ifdef WAPI_ENABLE
+    WMI_WAPI_REKEY_EVENTID,
+#endif
+    WMI_REPORT_BTCOEX_STATS_EVENTID,
+    WMI_REPORT_BTCOEX_CONFIG_EVENTID,
+    WMI_ACM_REJECT_EVENTID,
+    WMI_THIN_RESERVED_START_EVENTID = 0x8000,
+    /* Events in this range are reserved for thinmode 
+     * See wmi_thin.h for actual definitions */
+    WMI_THIN_RESERVED_END_EVENTID = 0x8fff,
+
+} WMI_EVENT_ID;
+
+
+typedef enum {
+    WMI_11A_CAPABILITY   = 1,
+    WMI_11G_CAPABILITY   = 2,
+    WMI_11AG_CAPABILITY  = 3,
+    WMI_11NA_CAPABILITY  = 4,
+    WMI_11NG_CAPABILITY  = 5,
+    WMI_11NAG_CAPABILITY = 6,
+    // END CAPABILITY
+    WMI_11N_CAPABILITY_OFFSET = (WMI_11NA_CAPABILITY - WMI_11A_CAPABILITY),
+} WMI_PHY_CAPABILITY;
+
+typedef PREPACK struct {
+    A_UINT8     macaddr[ATH_MAC_LEN];
+    A_UINT8     phyCapability;              /* WMI_PHY_CAPABILITY */
+} POSTPACK WMI_READY_EVENT_1;
+
+typedef PREPACK struct {
+    A_UINT32    sw_version;
+    A_UINT32    abi_version;
+    A_UINT8     macaddr[ATH_MAC_LEN];
+    A_UINT8     phyCapability;              /* WMI_PHY_CAPABILITY */
+} POSTPACK WMI_READY_EVENT_2;
+
+#if defined(ATH_TARGET)
+#ifdef AR6002_REV2
+#define WMI_READY_EVENT WMI_READY_EVENT_1  /* AR6002_REV2 target code */
+#else
+#define WMI_READY_EVENT WMI_READY_EVENT_2  /* AR6001, AR6002_REV4, AR6002_REV5 */
+#endif
+#else
+#define WMI_READY_EVENT WMI_READY_EVENT_2 /* host code */
+#endif
+
+
+/*
+ * Connect Event
+ */
+typedef PREPACK struct {
+    A_UINT16    channel;
+    A_UINT8     bssid[ATH_MAC_LEN];
+    A_UINT16    listenInterval;
+    A_UINT16    beaconInterval;
+    A_UINT32    networkType;
+    A_UINT8     beaconIeLen;
+    A_UINT8     assocReqLen;
+    A_UINT8     assocRespLen;
+    A_UINT8     assocInfo[1];
+} POSTPACK WMI_CONNECT_EVENT;
+
+/*
+ * Disconnect Event
+ */
+typedef enum {
+    NO_NETWORK_AVAIL   = 0x01,
+    LOST_LINK          = 0x02,     /* bmiss */
+    DISCONNECT_CMD     = 0x03,
+    BSS_DISCONNECTED   = 0x04,
+    AUTH_FAILED        = 0x05,
+    ASSOC_FAILED       = 0x06,
+    NO_RESOURCES_AVAIL = 0x07,
+    CSERV_DISCONNECT   = 0x08,
+    INVALID_PROFILE    = 0x0a,
+    DOT11H_CHANNEL_SWITCH = 0x0b,
+    PROFILE_MISMATCH   = 0x0c,
+    CONNECTION_EVICTED = 0x0d,
+    IBSS_MERGE         = 0xe,
+} WMI_DISCONNECT_REASON;
+
+typedef PREPACK struct {
+    A_UINT16    protocolReasonStatus;  /* reason code, see 802.11 spec. */
+    A_UINT8     bssid[ATH_MAC_LEN];    /* set if known */
+    A_UINT8     disconnectReason ;      /* see WMI_DISCONNECT_REASON */
+    A_UINT8     assocRespLen;
+    A_UINT8     assocInfo[1];
+} POSTPACK WMI_DISCONNECT_EVENT;
+
+/*
+ * BSS Info Event.
+ * Mechanism used to inform host of the presence and characteristic of
+ * wireless networks present.  Consists of bss info header followed by
+ * the beacon or probe-response frame body.  The 802.11 header is not included.
+ */
+typedef enum {
+    BEACON_FTYPE = 0x1,
+    PROBERESP_FTYPE,
+    ACTION_MGMT_FTYPE,
+    PROBEREQ_FTYPE,
+} WMI_BI_FTYPE;
+
+enum {
+    BSS_ELEMID_CHANSWITCH = 0x01,
+    BSS_ELEMID_ATHEROS = 0x02,
+};
+
+typedef PREPACK struct {
+    A_UINT16    channel;
+    A_UINT8     frameType;          /* see WMI_BI_FTYPE */
+    A_UINT8     snr;
+    A_INT16     rssi;
+    A_UINT8     bssid[ATH_MAC_LEN];
+    A_UINT32    ieMask;
+} POSTPACK WMI_BSS_INFO_HDR;
+
+/*
+ * BSS INFO HDR version 2.0
+ * With 6 bytes HTC header and 6 bytes of WMI header
+ * WMI_BSS_INFO_HDR cannot be accomodated in the removed 802.11 management
+ * header space.
+ * - Reduce the ieMask to 2 bytes as only two bit flags are used
+ * - Remove rssi and compute it on the host. rssi = snr - 95
+ */
+typedef PREPACK struct {
+    A_UINT16    channel;
+    A_UINT8     frameType;          /* see WMI_BI_FTYPE */
+    A_UINT8     snr;
+    A_UINT8     bssid[ATH_MAC_LEN];
+    A_UINT16    ieMask;
+} POSTPACK WMI_BSS_INFO_HDR2;
+
+/*
+ * Command Error Event
+ */
+typedef enum {
+    INVALID_PARAM  = 0x01,
+    ILLEGAL_STATE  = 0x02,
+    INTERNAL_ERROR = 0x03,
+} WMI_ERROR_CODE;
+
+typedef PREPACK struct {
+    A_UINT16    commandId;
+    A_UINT8     errorCode;
+} POSTPACK WMI_CMD_ERROR_EVENT;
+
+/*
+ * New Regulatory Domain Event
+ */
+typedef PREPACK struct {
+    A_UINT32    regDomain;
+} POSTPACK WMI_REG_DOMAIN_EVENT;
+
+typedef PREPACK struct {
+    A_UINT8     txQueueNumber;
+    A_UINT8     rxQueueNumber;
+    A_UINT8     trafficDirection;
+    A_UINT8     trafficClass;
+} POSTPACK WMI_PSTREAM_TIMEOUT_EVENT;
+
+typedef PREPACK struct {
+    A_UINT8     reserve1;
+    A_UINT8     reserve2;
+    A_UINT8     reserve3;
+    A_UINT8     trafficClass;
+} POSTPACK WMI_ACM_REJECT_EVENT;
+
+/*
+ * The WMI_NEIGHBOR_REPORT Event is generated by the target to inform
+ * the host of BSS's it has found that matches the current profile.
+ * It can be used by the host to cache PMKs and/to initiate pre-authentication
+ * if the BSS supports it.  The first bssid is always the current associated
+ * BSS.
+ * The bssid and bssFlags information repeats according to the number
+ * or APs reported.
+ */
+typedef enum {
+    WMI_DEFAULT_BSS_FLAGS   = 0x00,
+    WMI_PREAUTH_CAPABLE_BSS = 0x01,
+    WMI_PMKID_VALID_BSS     = 0x02,
+} WMI_BSS_FLAGS;
+
+typedef PREPACK struct {
+    A_UINT8     bssid[ATH_MAC_LEN];
+    A_UINT8     bssFlags;            /* see WMI_BSS_FLAGS */
+} POSTPACK WMI_NEIGHBOR_INFO;
+
+typedef PREPACK struct {
+    A_INT8      numberOfAps;
+    WMI_NEIGHBOR_INFO neighbor[1];
+} POSTPACK WMI_NEIGHBOR_REPORT_EVENT;
+
+/*
+ * TKIP MIC Error Event
+ */
+typedef PREPACK struct {
+    A_UINT8 keyid;
+    A_UINT8 ismcast;
+} POSTPACK WMI_TKIP_MICERR_EVENT;
+
+/*
+ * WMI_SCAN_COMPLETE_EVENTID - no parameters (old), staus parameter (new)
+ */
+typedef PREPACK struct {
+    A_INT32 status;
+} POSTPACK WMI_SCAN_COMPLETE_EVENT;
+
+#define MAX_OPT_DATA_LEN 1400
+
+/*
+ * WMI_SET_ADHOC_BSSID_CMDID
+ */
+typedef PREPACK struct {
+    A_UINT8     bssid[ATH_MAC_LEN];
+} POSTPACK WMI_SET_ADHOC_BSSID_CMD;
+
+/*
+ * WMI_SET_OPT_MODE_CMDID
+ */
+typedef enum {
+    SPECIAL_OFF,
+    SPECIAL_ON,
+} OPT_MODE_TYPE;
+
+typedef PREPACK struct {
+    A_UINT8     optMode;
+} POSTPACK WMI_SET_OPT_MODE_CMD;
+
+/*
+ * WMI_TX_OPT_FRAME_CMDID
+ */
+typedef enum {
+    OPT_PROBE_REQ   = 0x01,
+    OPT_PROBE_RESP  = 0x02,
+    OPT_CPPP_START  = 0x03,
+    OPT_CPPP_STOP   = 0x04,
+} WMI_OPT_FTYPE;
+
+typedef PREPACK struct {
+    A_UINT16    optIEDataLen;
+    A_UINT8     frmType;
+    A_UINT8     dstAddr[ATH_MAC_LEN];
+    A_UINT8     bssid[ATH_MAC_LEN];
+    A_UINT8     reserved;               /* For alignment */
+    A_UINT8     optIEData[1];
+} POSTPACK WMI_OPT_TX_FRAME_CMD;
+
+/*
+ * Special frame receive Event.
+ * Mechanism used to inform host of the receiption of the special frames.
+ * Consists of special frame info header followed by special frame body.
+ * The 802.11 header is not included.
+ */
+typedef PREPACK struct {
+    A_UINT16    channel;
+    A_UINT8     frameType;          /* see WMI_OPT_FTYPE */
+    A_INT8      snr;
+    A_UINT8     srcAddr[ATH_MAC_LEN];
+    A_UINT8     bssid[ATH_MAC_LEN];
+} POSTPACK WMI_OPT_RX_INFO_HDR;
+
+/*
+ * Reporting statistics.
+ */
+typedef PREPACK struct {
+    A_UINT32   tx_packets;
+    A_UINT32   tx_bytes;
+    A_UINT32   tx_unicast_pkts;
+    A_UINT32   tx_unicast_bytes;
+    A_UINT32   tx_multicast_pkts;
+    A_UINT32   tx_multicast_bytes;
+    A_UINT32   tx_broadcast_pkts;
+    A_UINT32   tx_broadcast_bytes;
+    A_UINT32   tx_rts_success_cnt;
+    A_UINT32   tx_packet_per_ac[4];
+    A_UINT32   tx_errors_per_ac[4];
+
+    A_UINT32   tx_errors;
+    A_UINT32   tx_failed_cnt;
+    A_UINT32   tx_retry_cnt;
+    A_UINT32   tx_mult_retry_cnt;
+    A_UINT32   tx_rts_fail_cnt;
+    A_INT32    tx_unicast_rate;
+}POSTPACK tx_stats_t;
+
+typedef PREPACK struct {
+    A_UINT32   rx_packets;
+    A_UINT32   rx_bytes;
+    A_UINT32   rx_unicast_pkts;
+    A_UINT32   rx_unicast_bytes;
+    A_UINT32   rx_multicast_pkts;
+    A_UINT32   rx_multicast_bytes;
+    A_UINT32   rx_broadcast_pkts;
+    A_UINT32   rx_broadcast_bytes;
+    A_UINT32   rx_fragment_pkt;
+
+    A_UINT32   rx_errors;
+    A_UINT32   rx_crcerr;
+    A_UINT32   rx_key_cache_miss;
+    A_UINT32   rx_decrypt_err;
+    A_UINT32   rx_duplicate_frames;
+    A_INT32    rx_unicast_rate;
+}POSTPACK rx_stats_t;
+
+typedef PREPACK struct {
+    A_UINT32   tkip_local_mic_failure;
+    A_UINT32   tkip_counter_measures_invoked;
+    A_UINT32   tkip_replays;
+    A_UINT32   tkip_format_errors;
+    A_UINT32   ccmp_format_errors;
+    A_UINT32   ccmp_replays;
+}POSTPACK tkip_ccmp_stats_t;
+
+typedef PREPACK struct {
+    A_UINT32   power_save_failure_cnt;
+    A_UINT16   stop_tx_failure_cnt;
+    A_UINT16   atim_tx_failure_cnt;
+    A_UINT16   atim_rx_failure_cnt;
+    A_UINT16   bcn_rx_failure_cnt;
+}POSTPACK pm_stats_t;
+
+typedef PREPACK struct {
+    A_UINT32    cs_bmiss_cnt;
+    A_UINT32    cs_lowRssi_cnt;
+    A_UINT16    cs_connect_cnt;
+    A_UINT16    cs_disconnect_cnt;
+    A_INT16     cs_aveBeacon_rssi;
+    A_UINT16    cs_roam_count;
+    A_INT16     cs_rssi;
+    A_UINT8     cs_snr;
+    A_UINT8     cs_aveBeacon_snr;
+    A_UINT8     cs_lastRoam_msec;
+} POSTPACK cserv_stats_t;
+
+typedef PREPACK struct {
+    tx_stats_t          tx_stats;
+    rx_stats_t          rx_stats;
+    tkip_ccmp_stats_t   tkipCcmpStats;
+}POSTPACK wlan_net_stats_t;
+
+typedef PREPACK struct {
+    A_UINT32    arp_received;
+    A_UINT32    arp_matched;
+    A_UINT32    arp_replied;
+} POSTPACK arp_stats_t;
+
+typedef PREPACK struct {
+    A_UINT32    wow_num_pkts_dropped;
+    A_UINT16    wow_num_events_discarded;
+    A_UINT8     wow_num_host_pkt_wakeups;
+    A_UINT8     wow_num_host_event_wakeups;
+} POSTPACK wlan_wow_stats_t;
+
+typedef PREPACK struct {
+    A_UINT32            lqVal;
+    A_INT32             noise_floor_calibation;
+    pm_stats_t          pmStats;
+    wlan_net_stats_t    txrxStats;
+    wlan_wow_stats_t    wowStats;
+    arp_stats_t         arpStats;
+    cserv_stats_t       cservStats;
+} POSTPACK WMI_TARGET_STATS;
+
+/*
+ * WMI_RSSI_THRESHOLD_EVENTID.
+ * Indicate the RSSI events to host. Events are indicated when we breach a
+ * thresold value.
+ */
+typedef enum{
+    WMI_RSSI_THRESHOLD1_ABOVE = 0,
+    WMI_RSSI_THRESHOLD2_ABOVE,
+    WMI_RSSI_THRESHOLD3_ABOVE,
+    WMI_RSSI_THRESHOLD4_ABOVE,
+    WMI_RSSI_THRESHOLD5_ABOVE,
+    WMI_RSSI_THRESHOLD6_ABOVE,
+    WMI_RSSI_THRESHOLD1_BELOW,
+    WMI_RSSI_THRESHOLD2_BELOW,
+    WMI_RSSI_THRESHOLD3_BELOW,
+    WMI_RSSI_THRESHOLD4_BELOW,
+    WMI_RSSI_THRESHOLD5_BELOW,
+    WMI_RSSI_THRESHOLD6_BELOW
+}WMI_RSSI_THRESHOLD_VAL;
+
+typedef PREPACK struct {
+    A_INT16 rssi;
+    A_UINT8 range;
+}POSTPACK WMI_RSSI_THRESHOLD_EVENT;
+
+/*
+ *  WMI_ERROR_REPORT_EVENTID
+ */
+typedef enum{
+    WMI_TARGET_PM_ERR_FAIL      = 0x00000001,
+    WMI_TARGET_KEY_NOT_FOUND    = 0x00000002,
+    WMI_TARGET_DECRYPTION_ERR   = 0x00000004,
+    WMI_TARGET_BMISS            = 0x00000008,
+    WMI_PSDISABLE_NODE_JOIN     = 0x00000010,
+    WMI_TARGET_COM_ERR          = 0x00000020,
+    WMI_TARGET_FATAL_ERR        = 0x00000040
+} WMI_TARGET_ERROR_VAL;
+
+typedef PREPACK struct {
+    A_UINT32 errorVal;
+}POSTPACK  WMI_TARGET_ERROR_REPORT_EVENT;
+
+typedef PREPACK struct {
+    A_UINT8 retrys;
+}POSTPACK  WMI_TX_RETRY_ERR_EVENT;
+
+typedef enum{
+    WMI_SNR_THRESHOLD1_ABOVE = 1,
+    WMI_SNR_THRESHOLD1_BELOW,
+    WMI_SNR_THRESHOLD2_ABOVE,
+    WMI_SNR_THRESHOLD2_BELOW,
+    WMI_SNR_THRESHOLD3_ABOVE,
+    WMI_SNR_THRESHOLD3_BELOW,
+    WMI_SNR_THRESHOLD4_ABOVE,
+    WMI_SNR_THRESHOLD4_BELOW
+} WMI_SNR_THRESHOLD_VAL;
+
+typedef PREPACK struct {
+    A_UINT8 range;  /* WMI_SNR_THRESHOLD_VAL */
+    A_UINT8 snr;
+}POSTPACK  WMI_SNR_THRESHOLD_EVENT;
+
+typedef enum{
+    WMI_LQ_THRESHOLD1_ABOVE = 1,
+    WMI_LQ_THRESHOLD1_BELOW,
+    WMI_LQ_THRESHOLD2_ABOVE,
+    WMI_LQ_THRESHOLD2_BELOW,
+    WMI_LQ_THRESHOLD3_ABOVE,
+    WMI_LQ_THRESHOLD3_BELOW,
+    WMI_LQ_THRESHOLD4_ABOVE,
+    WMI_LQ_THRESHOLD4_BELOW
+} WMI_LQ_THRESHOLD_VAL;
+
+typedef PREPACK struct {
+    A_INT32 lq;
+    A_UINT8 range;  /* WMI_LQ_THRESHOLD_VAL */
+}POSTPACK  WMI_LQ_THRESHOLD_EVENT;
+/*
+ * WMI_REPORT_ROAM_TBL_EVENTID
+ */
+#define MAX_ROAM_TBL_CAND   5
+
+typedef PREPACK struct {
+    A_INT32 roam_util;
+    A_UINT8 bssid[ATH_MAC_LEN];
+    A_INT8  rssi;
+    A_INT8  rssidt;
+    A_INT8  last_rssi;
+    A_INT8  util;
+    A_INT8  bias;
+    A_UINT8 reserved; /* For alignment */
+} POSTPACK WMI_BSS_ROAM_INFO;
+
+
+typedef PREPACK struct {
+    A_UINT16  roamMode;
+    A_UINT16  numEntries;
+    WMI_BSS_ROAM_INFO bssRoamInfo[1];
+} POSTPACK WMI_TARGET_ROAM_TBL;
+
+/*
+ * WMI_HCI_EVENT_EVENTID
+ */
+typedef PREPACK struct {
+    A_UINT16    evt_buf_sz;     /* HCI event buffer size */
+    A_UINT8     buf[1];         /* HCI  event */
+} POSTPACK WMI_HCI_EVENT;
+
+/*
+ *  WMI_CAC_EVENTID
+ */
+typedef enum {
+    CAC_INDICATION_ADMISSION = 0x00,
+    CAC_INDICATION_ADMISSION_RESP = 0x01,
+    CAC_INDICATION_DELETE = 0x02,
+    CAC_INDICATION_NO_RESP = 0x03,
+}CAC_INDICATION;
+
+#define WMM_TSPEC_IE_LEN   63
+
+typedef PREPACK struct {
+    A_UINT8 ac;
+    A_UINT8 cac_indication;
+    A_UINT8 statusCode;
+    A_UINT8 tspecSuggestion[WMM_TSPEC_IE_LEN];
+}POSTPACK  WMI_CAC_EVENT;
+
+/*
+ * WMI_APLIST_EVENTID
+ */
+
+typedef enum {
+    APLIST_VER1 = 1,
+} APLIST_VER;
+
+typedef PREPACK struct {
+    A_UINT8     bssid[ATH_MAC_LEN];
+    A_UINT16    channel;
+} POSTPACK  WMI_AP_INFO_V1;
+
+typedef PREPACK union {
+    WMI_AP_INFO_V1  apInfoV1;
+} POSTPACK WMI_AP_INFO;
+
+typedef PREPACK struct {
+    A_UINT8     apListVer;
+    A_UINT8     numAP;
+    WMI_AP_INFO apList[1];
+} POSTPACK WMI_APLIST_EVENT;
+
+/*
+ * developer commands
+ */
+
+/*
+ * WMI_SET_BITRATE_CMDID
+ *
+ * Get bit rate cmd uses same definition as set bit rate cmd
+ */
+typedef enum {
+    RATE_AUTO   = -1,
+    RATE_1Mb    = 0,
+    RATE_2Mb    = 1,
+    RATE_5_5Mb  = 2,
+    RATE_11Mb   = 3,
+    RATE_6Mb    = 4,
+    RATE_9Mb    = 5,
+    RATE_12Mb   = 6,
+    RATE_18Mb   = 7,
+    RATE_24Mb   = 8,
+    RATE_36Mb   = 9,
+    RATE_48Mb   = 10,
+    RATE_54Mb   = 11,
+    RATE_MCS_0_20 = 12,
+    RATE_MCS_1_20 = 13,
+    RATE_MCS_2_20 = 14,
+    RATE_MCS_3_20 = 15,
+    RATE_MCS_4_20 = 16,
+    RATE_MCS_5_20 = 17,
+    RATE_MCS_6_20 = 18,
+    RATE_MCS_7_20 = 19,
+    RATE_MCS_0_40 = 20,
+    RATE_MCS_1_40 = 21,
+    RATE_MCS_2_40 = 22,
+    RATE_MCS_3_40 = 23,
+    RATE_MCS_4_40 = 24,
+    RATE_MCS_5_40 = 25,
+    RATE_MCS_6_40 = 26,
+    RATE_MCS_7_40 = 27,
+} WMI_BIT_RATE;
+
+typedef PREPACK struct {
+    A_INT8      rateIndex;          /* see WMI_BIT_RATE */
+    A_INT8      mgmtRateIndex;
+    A_INT8      ctlRateIndex;
+} POSTPACK WMI_BIT_RATE_CMD;
+
+
+typedef PREPACK struct {
+    A_INT8      rateIndex;          /* see WMI_BIT_RATE */
+} POSTPACK  WMI_BIT_RATE_REPLY;
+
+
+/*
+ * WMI_SET_FIXRATES_CMDID
+ *
+ * Get fix rates cmd uses same definition as set fix rates cmd
+ */
+#define FIX_RATE_1Mb            ((A_UINT32)0x1)
+#define FIX_RATE_2Mb            ((A_UINT32)0x2)
+#define FIX_RATE_5_5Mb          ((A_UINT32)0x4)
+#define FIX_RATE_11Mb           ((A_UINT32)0x8)
+#define FIX_RATE_6Mb            ((A_UINT32)0x10)
+#define FIX_RATE_9Mb            ((A_UINT32)0x20)
+#define FIX_RATE_12Mb           ((A_UINT32)0x40)
+#define FIX_RATE_18Mb           ((A_UINT32)0x80)
+#define FIX_RATE_24Mb           ((A_UINT32)0x100)
+#define FIX_RATE_36Mb           ((A_UINT32)0x200)
+#define FIX_RATE_48Mb           ((A_UINT32)0x400)
+#define FIX_RATE_54Mb           ((A_UINT32)0x800)
+#define FIX_RATE_MCS_0_20       ((A_UINT32)0x1000)
+#define FIX_RATE_MCS_1_20       ((A_UINT32)0x2000)
+#define FIX_RATE_MCS_2_20       ((A_UINT32)0x4000)
+#define FIX_RATE_MCS_3_20       ((A_UINT32)0x8000)
+#define FIX_RATE_MCS_4_20       ((A_UINT32)0x10000)
+#define FIX_RATE_MCS_5_20       ((A_UINT32)0x20000)
+#define FIX_RATE_MCS_6_20       ((A_UINT32)0x40000)
+#define FIX_RATE_MCS_7_20       ((A_UINT32)0x80000)
+#define FIX_RATE_MCS_0_40       ((A_UINT32)0x100000)
+#define FIX_RATE_MCS_1_40       ((A_UINT32)0x200000)
+#define FIX_RATE_MCS_2_40       ((A_UINT32)0x400000)
+#define FIX_RATE_MCS_3_40       ((A_UINT32)0x800000)
+#define FIX_RATE_MCS_4_40       ((A_UINT32)0x1000000)
+#define FIX_RATE_MCS_5_40       ((A_UINT32)0x2000000)
+#define FIX_RATE_MCS_6_40       ((A_UINT32)0x4000000)
+#define FIX_RATE_MCS_7_40       ((A_UINT32)0x8000000)
+
+typedef PREPACK struct {
+    A_UINT32      fixRateMask;          /* see WMI_BIT_RATE */
+} POSTPACK WMI_FIX_RATES_CMD, WMI_FIX_RATES_REPLY;
+
+typedef PREPACK struct {
+    A_UINT8        bEnableMask;
+    A_UINT8        frameType;               /*type and subtype*/
+    A_UINT32     frameRateMask;          /* see WMI_BIT_RATE */
+} POSTPACK WMI_FRAME_RATES_CMD, WMI_FRAME_RATES_REPLY;
+
+/*
+ * WMI_SET_RECONNECT_AUTH_MODE_CMDID
+ *
+ * Set authentication mode
+ */
+typedef enum {
+    RECONN_DO_AUTH = 0x00,
+    RECONN_NOT_AUTH = 0x01
+} WMI_AUTH_MODE;
+
+typedef PREPACK struct {
+    A_UINT8 mode;
+} POSTPACK WMI_SET_AUTH_MODE_CMD;
+
+/*
+ * WMI_SET_REASSOC_MODE_CMDID
+ *
+ * Set authentication mode
+ */
+typedef enum {
+    REASSOC_DO_DISASSOC = 0x00,
+    REASSOC_DONOT_DISASSOC = 0x01
+} WMI_REASSOC_MODE;
+
+typedef PREPACK struct {
+    A_UINT8 mode;
+}POSTPACK WMI_SET_REASSOC_MODE_CMD;
+
+typedef enum {
+    ROAM_DATA_TIME = 1,            /* Get The Roam Time Data */
+} ROAM_DATA_TYPE;
+
+typedef PREPACK struct {
+    A_UINT32        disassoc_time;
+    A_UINT32        no_txrx_time;
+    A_UINT32        assoc_time;
+    A_UINT32        allow_txrx_time;
+    A_UINT8         disassoc_bssid[ATH_MAC_LEN];
+    A_INT8          disassoc_bss_rssi;
+    A_UINT8         assoc_bssid[ATH_MAC_LEN];
+    A_INT8          assoc_bss_rssi;
+} POSTPACK WMI_TARGET_ROAM_TIME;
+
+typedef PREPACK struct {
+    PREPACK union {
+        WMI_TARGET_ROAM_TIME roamTime;
+    } POSTPACK u;
+    A_UINT8 roamDataType ;
+} POSTPACK WMI_TARGET_ROAM_DATA;
+
+typedef enum {
+    WMI_WMM_DISABLED = 0,
+    WMI_WMM_ENABLED
+} WMI_WMM_STATUS;
+
+typedef PREPACK struct {
+    A_UINT8    status;
+}POSTPACK WMI_SET_WMM_CMD;
+
+typedef PREPACK struct {
+    A_UINT8    status;
+}POSTPACK WMI_SET_QOS_SUPP_CMD;
+
+typedef enum {
+    WMI_TXOP_DISABLED = 0,
+    WMI_TXOP_ENABLED
+} WMI_TXOP_CFG;
+
+typedef PREPACK struct {
+    A_UINT8    txopEnable;
+}POSTPACK WMI_SET_WMM_TXOP_CMD;
+
+typedef PREPACK struct {
+    A_UINT8 keepaliveInterval;
+} POSTPACK WMI_SET_KEEPALIVE_CMD;
+
+typedef PREPACK struct {
+    A_BOOL configured;
+    A_UINT8 keepaliveInterval;
+} POSTPACK WMI_GET_KEEPALIVE_CMD;
+
+/*
+ * Add Application specified IE to a management frame
+ */
+#define WMI_MAX_IE_LEN  255
+
+typedef PREPACK struct {
+    A_UINT8 mgmtFrmType;  /* one of WMI_MGMT_FRAME_TYPE */
+    A_UINT8 ieLen;    /* Length  of the IE that should be added to the MGMT frame */
+    A_UINT8 ieInfo[1];
+} POSTPACK WMI_SET_APPIE_CMD;
+
+/*
+ * Notify the WSC registration status to the target
+ */
+#define WSC_REG_ACTIVE     1
+#define WSC_REG_INACTIVE   0
+/* Generic Hal Interface for setting hal paramters. */
+/* Add new Set HAL Param cmdIds here for newer params */
+typedef enum {
+   WHAL_SETCABTO_CMDID = 1,
+}WHAL_CMDID;
+
+typedef PREPACK struct {
+    A_UINT8 cabTimeOut;
+} POSTPACK WHAL_SETCABTO_PARAM;
+
+typedef PREPACK struct {
+    A_UINT8  whalCmdId;
+    A_UINT8 data[1];
+} POSTPACK WHAL_PARAMCMD;
+
+
+#define WOW_MAX_FILTER_LISTS 1 /*4*/
+#define WOW_MAX_FILTERS_PER_LIST 4
+#define WOW_PATTERN_SIZE 64
+#define WOW_MASK_SIZE 64
+
+#define MAC_MAX_FILTERS_PER_LIST 4
+
+typedef PREPACK struct {
+    A_UINT8 wow_valid_filter;
+    A_UINT8 wow_filter_id;
+    A_UINT8 wow_filter_size;
+    A_UINT8 wow_filter_offset;
+    A_UINT8 wow_filter_mask[WOW_MASK_SIZE];
+    A_UINT8 wow_filter_pattern[WOW_PATTERN_SIZE];
+} POSTPACK WOW_FILTER;
+
+
+typedef PREPACK struct {
+    A_UINT8 wow_valid_list;
+    A_UINT8 wow_list_id;
+    A_UINT8 wow_num_filters;
+    A_UINT8 wow_total_list_size;
+    WOW_FILTER list[WOW_MAX_FILTERS_PER_LIST];
+} POSTPACK WOW_FILTER_LIST;
+
+typedef PREPACK struct {
+    A_UINT8 valid_filter;
+    A_UINT8 mac_addr[ATH_MAC_LEN];
+} POSTPACK MAC_FILTER;
+
+
+typedef PREPACK struct {
+    A_UINT8 total_list_size;
+    A_UINT8 enable;
+    MAC_FILTER list[MAC_MAX_FILTERS_PER_LIST];
+} POSTPACK MAC_FILTER_LIST;
+
+#define MAX_IP_ADDRS  2
+typedef PREPACK struct {
+    A_UINT32 ips[MAX_IP_ADDRS];  /* IP in Network Byte Order */
+} POSTPACK WMI_SET_IP_CMD;
+
+typedef PREPACK struct {
+    A_BOOL awake;
+    A_BOOL asleep;
+} POSTPACK WMI_SET_HOST_SLEEP_MODE_CMD;
+
+typedef enum {
+    WOW_FILTER_SSID = 0x1
+} WMI_WOW_FILTER;
+
+typedef PREPACK struct {
+    A_BOOL enable_wow;
+    WMI_WOW_FILTER filter;
+    A_UINT16 hostReqDelay;
+} POSTPACK WMI_SET_WOW_MODE_CMD;
+
+typedef PREPACK struct {
+    A_UINT8 filter_list_id;
+} POSTPACK WMI_GET_WOW_LIST_CMD;
+
+/*
+ * WMI_GET_WOW_LIST_CMD reply
+ */
+typedef PREPACK struct {
+    A_UINT8     num_filters;     /* number of patterns in reply */
+    A_UINT8     this_filter_num; /*  this is filter # x of total num_filters */
+    A_UINT8     wow_mode;
+    A_UINT8     host_mode;
+    WOW_FILTER  wow_filters[1];
+} POSTPACK WMI_GET_WOW_LIST_REPLY;
+
+typedef PREPACK struct {
+    A_UINT8 filter_list_id;
+    A_UINT8 filter_size;
+    A_UINT8 filter_offset;
+    A_UINT8 filter[1];
+} POSTPACK WMI_ADD_WOW_PATTERN_CMD;
+
+typedef PREPACK struct {
+    A_UINT16 filter_list_id;
+    A_UINT16 filter_id;
+} POSTPACK WMI_DEL_WOW_PATTERN_CMD;
+
+typedef PREPACK struct {
+    A_UINT8 macaddr[ATH_MAC_LEN];
+} POSTPACK WMI_SET_MAC_ADDRESS_CMD;
+
+/*
+ * WMI_SET_AKMP_PARAMS_CMD
+ */
+
+#define WMI_AKMP_MULTI_PMKID_EN   0x000001
+
+typedef PREPACK struct {
+    A_UINT32    akmpInfo;
+} POSTPACK WMI_SET_AKMP_PARAMS_CMD;
+
+typedef PREPACK struct {
+    A_UINT8 pmkid[WMI_PMKID_LEN];
+} POSTPACK WMI_PMKID;
+
+/*
+ * WMI_SET_PMKID_LIST_CMD
+ */
+#define WMI_MAX_PMKID_CACHE   8
+
+typedef PREPACK struct {
+    A_UINT32    numPMKID;
+    WMI_PMKID   pmkidList[WMI_MAX_PMKID_CACHE];
+} POSTPACK WMI_SET_PMKID_LIST_CMD;
+
+/*
+ * WMI_GET_PMKID_LIST_CMD  Reply
+ * Following the Number of PMKIDs is the list of PMKIDs
+ */
+typedef PREPACK struct {
+    A_UINT32    numPMKID;
+    A_UINT8     bssidList[ATH_MAC_LEN][1];
+    WMI_PMKID   pmkidList[1];
+} POSTPACK WMI_PMKID_LIST_REPLY;
+
+typedef PREPACK struct {
+    A_UINT16 oldChannel;
+    A_UINT32 newChannel;
+} POSTPACK WMI_CHANNEL_CHANGE_EVENT;
+
+typedef PREPACK struct {
+    A_UINT32 version;
+} POSTPACK WMI_WLAN_VERSION_EVENT;
+
+
+/* WMI_ADDBA_REQ_EVENTID */
+typedef PREPACK struct {
+    A_UINT8     tid;
+    A_UINT8     win_sz;
+    A_UINT16    st_seq_no;
+    A_UINT8     status;         /* f/w response for ADDBA Req; OK(0) or failure(!=0) */
+} POSTPACK WMI_ADDBA_REQ_EVENT;
+
+/* WMI_ADDBA_RESP_EVENTID */
+typedef PREPACK struct {
+    A_UINT8     tid;
+    A_UINT8     status;         /* OK(0), failure (!=0) */
+    A_UINT16    amsdu_sz;       /* Three values: Not supported(0), 3839, 8k */
+} POSTPACK WMI_ADDBA_RESP_EVENT;
+
+/* WMI_DELBA_EVENTID
+ * f/w received a DELBA for peer and processed it.
+ * Host is notified of this
+ */
+typedef PREPACK struct {
+    A_UINT8     tid;
+    A_UINT8     is_peer_initiator;
+    A_UINT16    reason_code;
+} POSTPACK WMI_DELBA_EVENT;
+
+
+#ifdef WAPI_ENABLE
+#define WAPI_REKEY_UCAST    1
+#define WAPI_REKEY_MCAST    2
+typedef PREPACK struct {
+    A_UINT8     type;
+    A_UINT8     macAddr[ATH_MAC_LEN];
+} POSTPACK WMI_WAPIREKEY_EVENT;
+#endif
+
+
+/* WMI_ALLOW_AGGR_CMDID
+ * Configures tid's to allow ADDBA negotiations
+ * on each tid, in each direction
+ */
+typedef PREPACK struct {
+    A_UINT16    tx_allow_aggr;  /* 16-bit mask to allow uplink ADDBA negotiation - bit position indicates tid*/
+    A_UINT16    rx_allow_aggr;  /* 16-bit mask to allow donwlink ADDBA negotiation - bit position indicates tid*/
+} POSTPACK WMI_ALLOW_AGGR_CMD;
+
+/* WMI_ADDBA_REQ_CMDID
+ * f/w starts performing ADDBA negotiations with peer
+ * on the given tid
+ */
+typedef PREPACK struct {
+    A_UINT8     tid;
+} POSTPACK WMI_ADDBA_REQ_CMD;
+
+/* WMI_DELBA_REQ_CMDID
+ * f/w would teardown BA with peer.
+ * is_send_initiator indicates if it's or tx or rx side
+ */
+typedef PREPACK struct {
+    A_UINT8     tid;
+    A_UINT8     is_sender_initiator;
+
+} POSTPACK WMI_DELBA_REQ_CMD;
+
+#define PEER_NODE_JOIN_EVENT 0x00
+#define PEER_NODE_LEAVE_EVENT 0x01
+#define PEER_FIRST_NODE_JOIN_EVENT 0x10
+#define PEER_LAST_NODE_LEAVE_EVENT 0x11
+typedef PREPACK struct {
+    A_UINT8 eventCode;
+    A_UINT8 peerMacAddr[ATH_MAC_LEN];
+} POSTPACK WMI_PEER_NODE_EVENT;
+
+#define IEEE80211_FRAME_TYPE_MGT          0x00
+#define IEEE80211_FRAME_TYPE_CTL          0x04
+
+/*
+ * Transmit complete event data structure(s)
+ */
+
+
+typedef PREPACK struct {
+#define TX_COMPLETE_STATUS_SUCCESS 0
+#define TX_COMPLETE_STATUS_RETRIES 1
+#define TX_COMPLETE_STATUS_NOLINK  2
+#define TX_COMPLETE_STATUS_TIMEOUT 3
+#define TX_COMPLETE_STATUS_OTHER   4
+
+    A_UINT8 status; /* one of TX_COMPLETE_STATUS_... */
+    A_UINT8 pktID; /* packet ID to identify parent packet */
+    A_UINT8 rateIdx; /* rate index on successful transmission */
+    A_UINT8 ackFailures; /* number of ACK failures in tx attempt */
+#if 0 /* optional params currently ommitted. */
+    A_UINT32 queueDelay; // usec delay measured Tx Start time - host delivery time
+    A_UINT32 mediaDelay; // usec delay measured ACK rx time - host delivery time
+#endif
+} POSTPACK TX_COMPLETE_MSG_V1; /* version 1 of tx complete msg */
+
+typedef PREPACK struct {
+    A_UINT8 numMessages; /* number of tx comp msgs following this struct */
+    A_UINT8 msgLen; /* length in bytes for each individual msg following this struct */
+    A_UINT8 msgType; /* version of tx complete msg data following this struct */
+    A_UINT8 reserved; /* individual messages follow this header */
+} POSTPACK WMI_TX_COMPLETE_EVENT;
+
+#define WMI_TXCOMPLETE_VERSION_1 (0x01)
+
+
+/*
+ * ------- AP Mode definitions --------------
+ */
+
+/*
+ * !!! Warning !!!
+ * -Changing the following values needs compilation of both driver and firmware
+ */
+#ifdef AR6002_REV2
+#define AP_MAX_NUM_STA          4
+#else
+#define AP_MAX_NUM_STA          8
+#endif
+#define AP_ACL_SIZE             10
+#define IEEE80211_MAX_IE        256
+#define MCAST_AID               0xFF /* Spl. AID used to set DTIM flag in the beacons */
+#define DEF_AP_COUNTRY_CODE     "US "
+#define DEF_AP_WMODE_G          WMI_11G_MODE
+#define DEF_AP_WMODE_AG         WMI_11AG_MODE
+#define DEF_AP_DTIM             5
+#define DEF_BEACON_INTERVAL     100
+
+/* AP mode disconnect reasons */
+#define AP_DISCONNECT_STA_LEFT      101
+#define AP_DISCONNECT_FROM_HOST     102
+#define AP_DISCONNECT_COMM_TIMEOUT  103
+
+/*
+ * Used with WMI_AP_HIDDEN_SSID_CMDID
+ */
+#define HIDDEN_SSID_FALSE   0
+#define HIDDEN_SSID_TRUE    1
+typedef PREPACK struct {
+    A_UINT8     hidden_ssid;
+} POSTPACK WMI_AP_HIDDEN_SSID_CMD;
+
+/*
+ * Used with WMI_AP_ACL_POLICY_CMDID
+ */
+#define AP_ACL_DISABLE          0x00
+#define AP_ACL_ALLOW_MAC        0x01
+#define AP_ACL_DENY_MAC         0x02
+#define AP_ACL_RETAIN_LIST_MASK 0x80
+typedef PREPACK struct {
+    A_UINT8     policy;
+} POSTPACK WMI_AP_ACL_POLICY_CMD;
+
+/*
+ * Used with WMI_AP_ACL_MAC_LIST_CMDID
+ */
+#define ADD_MAC_ADDR    1
+#define DEL_MAC_ADDR    2
+typedef PREPACK struct {
+    A_UINT8     action;
+    A_UINT8     index;
+    A_UINT8     mac[ATH_MAC_LEN];
+    A_UINT8     wildcard;
+} POSTPACK WMI_AP_ACL_MAC_CMD;
+
+typedef PREPACK struct {
+    A_UINT16    index;
+    A_UINT8     acl_mac[AP_ACL_SIZE][ATH_MAC_LEN];
+    A_UINT8     wildcard[AP_ACL_SIZE];
+    A_UINT8     policy;
+} POSTPACK WMI_AP_ACL;
+
+/*
+ * Used with WMI_AP_SET_NUM_STA_CMDID
+ */
+typedef PREPACK struct {
+    A_UINT8     num_sta;
+} POSTPACK WMI_AP_SET_NUM_STA_CMD;
+
+/*
+ * Used with WMI_AP_SET_MLME_CMDID
+ */
+typedef PREPACK struct {
+    A_UINT8    mac[ATH_MAC_LEN];
+    A_UINT16   reason;              /* 802.11 reason code */
+    A_UINT8    cmd;                 /* operation to perform */
+#define WMI_AP_MLME_ASSOC       1   /* associate station */
+#define WMI_AP_DISASSOC         2   /* disassociate station */
+#define WMI_AP_DEAUTH           3   /* deauthenticate station */
+#define WMI_AP_MLME_AUTHORIZE   4   /* authorize station */
+#define WMI_AP_MLME_UNAUTHORIZE 5   /* unauthorize station */
+} POSTPACK WMI_AP_SET_MLME_CMD;
+
+typedef PREPACK struct {
+    A_UINT32 period;
+} POSTPACK WMI_AP_CONN_INACT_CMD;
+
+typedef PREPACK struct {
+    A_UINT32 period_min;
+    A_UINT32 dwell_ms;
+} POSTPACK WMI_AP_PROT_SCAN_TIME_CMD;
+
+typedef PREPACK struct {
+    A_BOOL flag;
+    A_UINT16 aid;
+} POSTPACK WMI_AP_SET_PVB_CMD;
+
+#define WMI_DISABLE_REGULATORY_CODE "FF"
+
+typedef PREPACK struct {
+    A_UCHAR countryCode[3];
+} POSTPACK WMI_AP_SET_COUNTRY_CMD;
+
+typedef PREPACK struct {
+    A_UINT8 dtim;
+} POSTPACK WMI_AP_SET_DTIM_CMD;
+
+typedef PREPACK struct {
+    A_UINT8  band; /* specifies which band to apply these values */
+    A_UINT8  enable; /* allows 11n to be disabled on a per band basis */    
+    A_UINT8  chan_width_40M_supported;
+    A_UINT8  short_GI_20MHz;
+    A_UINT8  short_GI_40MHz;
+    A_UINT8  intolerance_40MHz;
+    A_UINT8  max_ampdu_len_exp;
+} POSTPACK WMI_SET_HT_CAP_CMD;
+
+typedef PREPACK struct {
+    A_UINT8   sta_chan_width;
+} POSTPACK WMI_SET_HT_OP_CMD;
+
+typedef PREPACK struct {
+    A_UINT32 rateMasks[8];
+} POSTPACK WMI_SET_TX_SELECT_RATES_CMD;
+
+typedef PREPACK struct {
+    A_UINT32    sgiMask;
+    A_UINT8     sgiPERThreshold;
+} POSTPACK WMI_SET_TX_SGI_PARAM_CMD;
+
+#define DEFAULT_SGI_MASK 0x08080000
+#define DEFAULT_SGI_PER 10
+
+typedef PREPACK struct {
+    A_UINT32 rateField; /* 1 bit per rate corresponding to index */
+    A_UINT8 id;
+    A_UINT8 shortTrys;
+    A_UINT8 longTrys;
+    A_UINT8 reserved; /* padding */
+} POSTPACK WMI_SET_RATE_POLICY_CMD;
+
+typedef PREPACK struct {
+    A_UINT8 metaVersion; /* version of meta data for rx packets <0 = default> (0-7 = valid) */
+    A_UINT8 dot11Hdr; /* 1 == leave .11 header intact , 0 == replace .11 header with .3 <default> */
+    A_UINT8 defragOnHost; /* 1 == defragmentation is performed by host, 0 == performed by target <default> */
+    A_UINT8 reserved[1]; /* alignment */
+} POSTPACK WMI_RX_FRAME_FORMAT_CMD;
+
+
+typedef PREPACK struct {
+    A_UINT8 enable;     /* 1 == device operates in thin mode , 0 == normal mode <default> */
+    A_UINT8 reserved[3];
+} POSTPACK WMI_SET_THIN_MODE_CMD;
+
+/* AP mode events */
+/* WMI_PS_POLL_EVENT */
+typedef PREPACK struct {
+    A_UINT16 aid;
+} POSTPACK WMI_PSPOLL_EVENT;
+
+typedef PREPACK struct {
+    A_UINT32 tx_bytes;
+    A_UINT32 tx_pkts;
+    A_UINT32 tx_error;
+    A_UINT32 tx_discard;
+    A_UINT32 rx_bytes;
+    A_UINT32 rx_pkts;
+    A_UINT32 rx_error;
+    A_UINT32 rx_discard;
+    A_UINT32 aid;
+} POSTPACK WMI_PER_STA_STAT;
+
+#define AP_GET_STATS    0
+#define AP_CLEAR_STATS  1
+
+typedef PREPACK struct {
+    A_UINT32            action;
+    WMI_PER_STA_STAT    sta[AP_MAX_NUM_STA+1];
+} POSTPACK WMI_AP_MODE_STAT;
+#define WMI_AP_MODE_STAT_SIZE(numSta) (sizeof(A_UINT32) + ((numSta + 1) * sizeof(WMI_PER_STA_STAT)))
+
+#define AP_11BG_RATESET1        1
+#define AP_11BG_RATESET2        2
+#define DEF_AP_11BG_RATESET     AP_11BG_RATESET1
+typedef PREPACK struct {
+    A_UINT8 rateset;
+} POSTPACK WMI_AP_SET_11BG_RATESET_CMD;
+/*
+ * End of AP mode definitions
+ */
+
+#ifndef ATH_TARGET
+#include "athendpack.h"
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _WMI_H_ */
diff --git a/drivers/net/ath6kl/include/common/wmi_thin.h b/drivers/net/ath6kl/include/common/wmi_thin.h
new file mode 100644
index 00000000000..35391edd20a
--- /dev/null
+++ b/drivers/net/ath6kl/include/common/wmi_thin.h
@@ -0,0 +1,347 @@
+//------------------------------------------------------------------------------
+// <copyright file="wmi_thin.h" company="Atheros">
+//    Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+/*
+ * This file contains the definitions of the WMI protocol specified in the
+ * Wireless Module Interface (WMI).  It includes definitions of all the
+ * commands and events. Commands are messages from the host to the WM.
+ * Events and Replies are messages from the WM to the host.
+ *
+ * Ownership of correctness in regards to WMI commands
+ * belongs to the host driver and the WM is not required to validate
+ * parameters for value, proper range, or any other checking.
+ *
+ */
+
+#ifndef _WMI_THIN_H_
+#define _WMI_THIN_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+typedef enum {
+    WMI_THIN_CONFIG_CMDID =  0x8000, // WMI_THIN_RESERVED_START 
+    WMI_THIN_SET_MIB_CMDID,
+    WMI_THIN_GET_MIB_CMDID,
+    WMI_THIN_JOIN_CMDID,
+    /* add new CMDID's here */
+    WMI_THIN_RESERVED_END_CMDID = 0x8fff // WMI_THIN_RESERVED_END
+} WMI_THIN_COMMAND_ID;
+
+typedef enum{
+    TEMPLATE_FRM_FIRST = 0,
+    TEMPLATE_FRM_PROBE_REQ =TEMPLATE_FRM_FIRST,
+    TEMPLATE_FRM_BEACON,
+    TEMPLATE_FRM_PROBE_RESP,
+    TEMPLATE_FRM_NULL,
+    TEMPLATE_FRM_QOS_NULL,
+    TEMPLATE_FRM_PSPOLL,
+    TEMPLATE_FRM_MAX
+}WMI_TEMPLATE_FRM_TYPE;
+
+/* TEMPLATE_FRM_LEN... represent the maximum allowable
+ * data lengths (bytes) for each frame type */
+#define TEMPLATE_FRM_LEN_PROBE_REQ  (256) /* Symbian dictates a minimum of 256 for these 3 frame types */
+#define TEMPLATE_FRM_LEN_BEACON     (256)
+#define TEMPLATE_FRM_LEN_PROBE_RESP (256)
+#define TEMPLATE_FRM_LEN_NULL       (32)
+#define TEMPLATE_FRM_LEN_QOS_NULL   (32)
+#define TEMPLATE_FRM_LEN_PSPOLL     (32)
+#define TEMPLATE_FRM_LEN_SUM (TEMPLATE_FRM_LEN_PROBE_REQ + TEMPLATE_FRM_LEN_BEACON + TEMPLATE_FRM_LEN_PROBE_RESP + \
+            TEMPLATE_FRM_LEN_NULL + TEMPLATE_FRM_LEN_QOS_NULL + TEMPLATE_FRM_LEN_PSPOLL)
+
+
+/* MAC Header Build Rules */
+/*  These values allow the host to configure the 
+ *  target code that is responsible for constructing
+ *  the MAC header.  In cases where the MAC header
+ *  is provided by the host framework, the target
+ *  has a diminished responsibility over what fields
+ *  it must write. This will vary from framework to framework.
+ *  Symbian requires different behavior from MAC80211 which
+ *  requires different behavior from MS Native Wifi. */
+#define WMI_WRT_VER_TYPE    0x00000001
+#define WMI_WRT_DURATION    0x00000002
+#define WMI_WRT_DIRECTION   0x00000004
+#define WMI_WRT_POWER       0x00000008
+#define WMI_WRT_WEP         0x00000010
+#define WMI_WRT_MORE        0x00000020
+#define WMI_WRT_BSSID       0x00000040
+#define WMI_WRT_QOS         0x00000080
+#define WMI_WRT_SEQNO       0x00000100
+#define WMI_GUARD_TX        0x00000200 /* prevents TX ops that are not allowed for a current state */
+#define WMI_WRT_DEFAULT_CONFIG  (WMI_WRT_VER_TYPE | WMI_WRT_DURATION | WMI_WRT_DIRECTION | \
+                                 WMI_WRT_POWER | WMI_WRT_MORE | WMI_WRT_WEP | WMI_WRT_BSSID | \
+                                 WMI_WRT_QOS | WMI_WRT_SEQNO | WMI_GUARD_TX)
+
+/* WMI_THIN_CONFIG_TXCOMPLETE -- Used to configure the params and content for 
+ *  TX Complete messages the will come from the Target.  these messages are 
+ *  disabled by default but can be enabled using this structure and the 
+ *  WMI_THIN_CONFIG_CMDID. */
+typedef PREPACK struct {
+    A_UINT8     version; /* the versioned type of messages to use or 0 to disable */
+    A_UINT8     countThreshold; /* msg count threshold triggering a tx complete message */
+    A_UINT16    timeThreshold; /* timeout interval in MSEC triggering a tx complete message */       
+} POSTPACK WMI_THIN_CONFIG_TXCOMPLETE;
+
+/* WMI_THIN_CONFIG_DECRYPT_ERR -- Used to configure behavior for received frames 
+ *  that have decryption errors.  The default behavior is to discard the frame
+ *  without notification. Alternately, the MAC Header is forwarded to the host 
+ *  with the failed status. */
+typedef PREPACK struct {
+    A_UINT8     enable; /* 1 == send decrypt errors to the host, 0 == don't */
+    A_UINT8     reserved[3]; /* align padding */
+} POSTPACK WMI_THIN_CONFIG_DECRYPT_ERR;
+
+/* WMI_THIN_CONFIG_TX_MAC_RULES -- Used to configure behavior for transmitted
+ *  frames that require partial MAC header construction. These rules 
+ *  are used by the target to indicate which fields need to be written. */
+typedef PREPACK struct {
+    A_UINT32    rules; /* combination of WMI_WRT_... values */     
+} POSTPACK WMI_THIN_CONFIG_TX_MAC_RULES;
+
+/* WMI_THIN_CONFIG_RX_FILTER_RULES -- Used to configure behavior for received
+ *  frames as to which frames should get forwarded to the host and which
+ *  should get processed internally. */
+typedef PREPACK struct {
+    A_UINT32    rules; /* combination of WMI_FILT_... values */     
+} POSTPACK WMI_THIN_CONFIG_RX_FILTER_RULES;
+
+/* WMI_THIN_CONFIG_CMD -- Used to contain some combination of the above
+ *  WMI_THIN_CONFIG_... structures. The actual combination is indicated 
+ *  by the value of cfgField. Each bit in this field corresponds to 
+ *  one of the above structures. */
+typedef PREPACK struct {
+#define WMI_THIN_CFG_TXCOMP         0x00000001
+#define WMI_THIN_CFG_DECRYPT        0x00000002
+#define WMI_THIN_CFG_MAC_RULES      0x00000004
+#define WMI_THIN_CFG_FILTER_RULES   0x00000008
+    A_UINT32    cfgField;   /* combination of WMI_THIN_CFG_... describes contents of config command */
+    A_UINT16    length;     /* length in bytes of appended sub-commands */        
+    A_UINT8     reserved[2];   /* align padding */
+} POSTPACK WMI_THIN_CONFIG_CMD;
+
+/* MIB Access Identifiers tailored for Symbian. */
+enum {
+    MIB_ID_STA_MAC = 1,             // [READONLY]
+    MIB_ID_RX_LIFE_TIME,            // [NOT IMPLEMENTED]
+    MIB_ID_SLOT_TIME,               // [READ/WRITE]
+    MIB_ID_RTS_THRESHOLD,           // [READ/WRITE]
+    MIB_ID_CTS_TO_SELF,             // [READ/WRITE]
+    MIB_ID_TEMPLATE_FRAME,          // [WRITE ONLY]
+    MIB_ID_RXFRAME_FILTER,          // [READ/WRITE]
+    MIB_ID_BEACON_FILTER_TABLE,     // [WRITE ONLY]
+    MIB_ID_BEACON_FILTER,           // [READ/WRITE]
+    MIB_ID_BEACON_LOST_COUNT,       // [WRITE ONLY]
+    MIB_ID_RSSI_THRESHOLD,          // [WRITE ONLY]
+    MIB_ID_HT_CAP,                  // [NOT IMPLEMENTED]
+    MIB_ID_HT_OP,                   // [NOT IMPLEMENTED]
+    MIB_ID_HT_2ND_BEACON,           // [NOT IMPLEMENTED]
+    MIB_ID_HT_BLOCK_ACK,            // [NOT IMPLEMENTED]
+    MIB_ID_PREAMBLE,                // [READ/WRITE]
+    /*MIB_ID_GROUP_ADDR_TABLE,*/
+    /*MIB_ID_WEP_DEFAULT_KEY_ID */
+    /*MIB_ID_TX_POWER */
+    /*MIB_ID_ARP_IP_TABLE */
+    /*MIB_ID_SLEEP_MODE */
+    /*MIB_ID_WAKE_INTERVAL*/
+    /*MIB_ID_STAT_TABLE*/
+    /*MIB_ID_IBSS_PWR_SAVE*/
+    /*MIB_ID_COUNTERS_TABLE*/
+    /*MIB_ID_ETHERTYPE_FILTER*/
+    /*MIB_ID_BC_UDP_FILTER*/
+       
+};
+
+typedef PREPACK struct {
+    A_UINT8 addr[ATH_MAC_LEN];
+} POSTPACK WMI_THIN_MIB_STA_MAC;
+
+typedef PREPACK struct {
+    A_UINT32 time; // units == msec
+} POSTPACK WMI_THIN_MIB_RX_LIFE_TIME;
+
+typedef PREPACK struct {
+    A_UINT8 enable; //1 = on, 0 = off
+} POSTPACK WMI_THIN_MIB_CTS_TO_SELF;
+
+typedef PREPACK struct {
+    A_UINT32 time; // units == usec
+} POSTPACK WMI_THIN_MIB_SLOT_TIME;
+
+typedef PREPACK struct {
+    A_UINT16 length; //units == bytes
+} POSTPACK WMI_THIN_MIB_RTS_THRESHOLD;
+
+typedef PREPACK struct {
+    A_UINT8 type; // type of frame
+    A_UINT8 rate; // tx rate to be used (one of WMI_BIT_RATE)
+    A_UINT16 length; // num bytes following this structure as the template data
+} POSTPACK WMI_THIN_MIB_TEMPLATE_FRAME;
+
+typedef PREPACK struct {
+#define FRAME_FILTER_PROMISCUOUS 0x00000001
+#define FRAME_FILTER_BSSID       0x00000002
+    A_UINT32 filterMask; 
+} POSTPACK WMI_THIN_MIB_RXFRAME_FILTER;
+
+
+#define IE_FILTER_TREATMENT_CHANGE 1
+#define IE_FILTER_TREATMENT_APPEAR 2
+
+typedef PREPACK struct {
+    A_UINT8 ie;
+    A_UINT8 treatment;
+} POSTPACK WMI_THIN_MIB_BEACON_FILTER_TABLE;
+
+typedef PREPACK struct {
+    A_UINT8 ie;
+    A_UINT8 treatment;
+    A_UINT8 oui[3];
+    A_UINT8 type;
+    A_UINT16 version;
+} POSTPACK WMI_THIN_MIB_BEACON_FILTER_TABLE_OUI;
+
+typedef PREPACK struct {
+    A_UINT16 numElements;
+    A_UINT8 entrySize; // sizeof(WMI_THIN_MIB_BEACON_FILTER_TABLE) on host cpu may be 2 may be 4
+    A_UINT8 reserved;
+} POSTPACK WMI_THIN_MIB_BEACON_FILTER_TABLE_HEADER; 
+
+typedef PREPACK struct {
+    A_UINT32 count; /* num beacons between deliveries */
+    A_UINT8 enable;
+    A_UINT8 reserved[3];
+} POSTPACK WMI_THIN_MIB_BEACON_FILTER;
+
+typedef PREPACK struct {
+    A_UINT32 count; /* num consec lost beacons after which send event */
+} POSTPACK WMI_THIN_MIB_BEACON_LOST_COUNT;
+
+typedef PREPACK struct {
+    A_UINT8 rssi; /* the low threshold which can trigger an event warning */
+    A_UINT8 tolerance; /* the range above and below the threshold to prevent event flooding to the host. */
+    A_UINT8 count; /* the sample count of consecutive frames necessary to trigger an event. */
+    A_UINT8 reserved[1]; /* padding */
+} POSTPACK WMI_THIN_MIB_RSSI_THRESHOLD;
+
+
+typedef PREPACK struct {
+    A_UINT32 cap;
+    A_UINT32 rxRateField;
+    A_UINT32 beamForming;
+    A_UINT8 addr[ATH_MAC_LEN];
+    A_UINT8 enable;        
+    A_UINT8 stbc;
+    A_UINT8 maxAMPDU;    
+    A_UINT8 msduSpacing;
+    A_UINT8 mcsFeedback;   
+    A_UINT8 antennaSelCap;    
+} POSTPACK WMI_THIN_MIB_HT_CAP;
+
+typedef PREPACK struct {
+    A_UINT32 infoField;
+    A_UINT32 basicRateField;
+    A_UINT8 protection;
+    A_UINT8 secondChanneloffset;
+    A_UINT8 channelWidth;
+    A_UINT8 reserved;
+} POSTPACK WMI_THIN_MIB_HT_OP;
+
+typedef PREPACK struct {
+#define SECOND_BEACON_PRIMARY   1
+#define SECOND_BEACON_EITHER    2
+#define SECOND_BEACON_SECONDARY 3
+    A_UINT8 cfg;
+    A_UINT8 reserved[3]; /* padding */
+} POSTPACK WMI_THIN_MIB_HT_2ND_BEACON;
+
+typedef PREPACK struct {
+    A_UINT8 txTIDField;
+    A_UINT8 rxTIDField;
+    A_UINT8 reserved[2]; /* padding */
+} POSTPACK WMI_THIN_MIB_HT_BLOCK_ACK;
+
+typedef PREPACK struct {
+    A_UINT8 enableLong; // 1 == long preamble, 0 == short preamble
+    A_UINT8 reserved[3];
+} POSTPACK WMI_THIN_MIB_PREAMBLE;
+
+typedef PREPACK struct {    
+    A_UINT16    length;     /* the length in bytes of the appended MIB data */
+    A_UINT8     mibID;      /* the ID of the MIB element being set */
+    A_UINT8     reserved; /* align padding */
+} POSTPACK WMI_THIN_SET_MIB_CMD;
+
+typedef PREPACK struct {    
+    A_UINT8     mibID;      /* the ID of the MIB element being set */
+    A_UINT8     reserved[3]; /* align padding */
+} POSTPACK WMI_THIN_GET_MIB_CMD;
+
+typedef PREPACK struct {
+    A_UINT32    basicRateMask; /* bit mask of basic rates */
+    A_UINT32    beaconIntval; /* TUs */
+    A_UINT16    atimWindow; /* TUs */
+    A_UINT16    channel; /* frequency in Mhz */
+    A_UINT8     networkType; /* INFRA_NETWORK | ADHOC_NETWORK */
+    A_UINT8     ssidLength; /* 0 - 32 */
+    A_UINT8     probe;      /* != 0 : issue probe req at start */
+    A_UINT8     reserved;   /* alignment */    
+    A_UCHAR     ssid[WMI_MAX_SSID_LEN];    
+    A_UINT8     bssid[ATH_MAC_LEN];
+} POSTPACK WMI_THIN_JOIN_CMD;
+
+typedef PREPACK struct {
+    A_UINT16 dtim; /* dtim interval in num beacons */
+    A_UINT16 aid; /* 80211 AID from Assoc resp */   
+} POSTPACK WMI_THIN_POST_ASSOC_CMD;
+
+typedef enum {
+    WMI_THIN_EVENTID_RESERVED_START           = 0x8000,
+    WMI_THIN_GET_MIB_EVENTID,
+    WMI_THIN_JOIN_EVENTID,
+    
+    /* Add new THIN EVENTID's here */
+    WMI_THIN_EVENTID_RESERVED_END           = 0x8fff    
+} WMI_THIN_EVENT_ID;
+
+/* Possible values for WMI_THIN_JOIN_EVENT.result */
+typedef enum {
+    WMI_THIN_JOIN_RES_SUCCESS = 0, // device has joined the network
+    WMI_THIN_JOIN_RES_FAIL, // device failed for unspecified reason
+    WMI_THIN_JOIN_RES_TIMEOUT, // device failed due to no beacon rx in time limit
+    WMI_THIN_JOIN_RES_BAD_PARAM, // device failed due to bad cmd param.
+}WMI_THIN_JOIN_RESULT;
+
+typedef PREPACK struct {
+    A_UINT8 result; /* the result of the join cmd. one of WMI_THIN_JOIN_RESULT */
+    A_UINT8 reserved[3]; /* alignment */
+} POSTPACK WMI_THIN_JOIN_EVENT;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _WMI_THIN_H_ */
diff --git a/drivers/net/ath6kl/include/common/wmix.h b/drivers/net/ath6kl/include/common/wmix.h
new file mode 100644
index 00000000000..87046e364ba
--- /dev/null
+++ b/drivers/net/ath6kl/include/common/wmix.h
@@ -0,0 +1,279 @@
+//------------------------------------------------------------------------------
+// <copyright file="wmix.h" company="Atheros">
+//    Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+/*
+ * This file contains extensions of the WMI protocol specified in the
+ * Wireless Module Interface (WMI).  It includes definitions of all
+ * extended commands and events.  Extensions include useful commands
+ * that are not directly related to wireless activities.  They may
+ * be hardware-specific, and they might not be supported on all
+ * implementations.
+ *
+ * Extended WMIX commands are encapsulated in a WMI message with
+ * cmd=WMI_EXTENSION_CMD.
+ */
+
+#ifndef _WMIX_H_
+#define _WMIX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef ATH_TARGET
+#include "athstartpack.h"
+#endif
+
+#include "dbglog.h"
+
+/*
+ * Extended WMI commands are those that are needed during wireless
+ * operation, but which are not really wireless commands.  This allows,
+ * for instance, platform-specific commands.  Extended WMI commands are
+ * embedded in a WMI command message with WMI_COMMAND_ID=WMI_EXTENSION_CMDID.
+ * Extended WMI events are similarly embedded in a WMI event message with
+ * WMI_EVENT_ID=WMI_EXTENSION_EVENTID.
+ */
+typedef PREPACK struct {
+    A_UINT32    commandId;
+} POSTPACK WMIX_CMD_HDR;
+
+typedef enum {
+    WMIX_DSETOPEN_REPLY_CMDID           = 0x2001,
+    WMIX_DSETDATA_REPLY_CMDID,
+    WMIX_GPIO_OUTPUT_SET_CMDID,
+    WMIX_GPIO_INPUT_GET_CMDID,
+    WMIX_GPIO_REGISTER_SET_CMDID,
+    WMIX_GPIO_REGISTER_GET_CMDID,
+    WMIX_GPIO_INTR_ACK_CMDID,
+    WMIX_HB_CHALLENGE_RESP_CMDID,
+    WMIX_DBGLOG_CFG_MODULE_CMDID,
+    WMIX_PROF_CFG_CMDID,                 /* 0x200a */
+    WMIX_PROF_ADDR_SET_CMDID,
+    WMIX_PROF_START_CMDID,
+    WMIX_PROF_STOP_CMDID,
+    WMIX_PROF_COUNT_GET_CMDID,
+} WMIX_COMMAND_ID;
+
+typedef enum {
+    WMIX_DSETOPENREQ_EVENTID            = 0x3001,
+    WMIX_DSETCLOSE_EVENTID,
+    WMIX_DSETDATAREQ_EVENTID,
+    WMIX_GPIO_INTR_EVENTID,
+    WMIX_GPIO_DATA_EVENTID,
+    WMIX_GPIO_ACK_EVENTID,
+    WMIX_HB_CHALLENGE_RESP_EVENTID,
+    WMIX_DBGLOG_EVENTID,
+    WMIX_PROF_COUNT_EVENTID,
+} WMIX_EVENT_ID;
+
+/*
+ * =============DataSet support=================
+ */
+
+/*
+ * WMIX_DSETOPENREQ_EVENTID
+ * DataSet Open Request Event
+ */
+typedef PREPACK struct {
+    A_UINT32 dset_id;
+    A_UINT32 targ_dset_handle;  /* echo'ed, not used by Host, */
+    A_UINT32 targ_reply_fn;     /* echo'ed, not used by Host, */
+    A_UINT32 targ_reply_arg;    /* echo'ed, not used by Host, */
+} POSTPACK WMIX_DSETOPENREQ_EVENT;
+
+/*
+ * WMIX_DSETCLOSE_EVENTID
+ * DataSet Close Event
+ */
+typedef PREPACK struct {
+    A_UINT32 access_cookie;
+} POSTPACK WMIX_DSETCLOSE_EVENT;
+
+/*
+ * WMIX_DSETDATAREQ_EVENTID
+ * DataSet Data Request Event
+ */
+typedef PREPACK struct {
+    A_UINT32 access_cookie;
+    A_UINT32 offset;
+    A_UINT32 length;
+    A_UINT32 targ_buf;         /* echo'ed, not used by Host, */
+    A_UINT32 targ_reply_fn;    /* echo'ed, not used by Host, */
+    A_UINT32 targ_reply_arg;   /* echo'ed, not used by Host, */
+} POSTPACK WMIX_DSETDATAREQ_EVENT;
+
+typedef PREPACK struct {
+    A_UINT32              status;
+    A_UINT32              targ_dset_handle;
+    A_UINT32              targ_reply_fn;
+    A_UINT32              targ_reply_arg;
+    A_UINT32              access_cookie;
+    A_UINT32              size;
+    A_UINT32              version;
+} POSTPACK WMIX_DSETOPEN_REPLY_CMD;
+
+typedef PREPACK struct {
+    A_UINT32              status;
+    A_UINT32              targ_buf;
+    A_UINT32              targ_reply_fn;
+    A_UINT32              targ_reply_arg;
+    A_UINT32              length;
+    A_UINT8               buf[1];
+} POSTPACK WMIX_DSETDATA_REPLY_CMD;
+
+
+/* 
+ * =============GPIO support=================
+ * All masks are 18-bit masks with bit N operating on GPIO pin N.
+ */
+
+#include "gpio.h"
+
+/*
+ * Set GPIO pin output state.
+ * In order for output to be driven, a pin must be enabled for output.
+ * This can be done during initialization through the GPIO Configuration
+ * DataSet, or during operation with the enable_mask.
+ *
+ * If a request is made to simultaneously set/clear or set/disable or
+ * clear/disable or disable/enable, results are undefined.
+ */
+typedef PREPACK struct {
+    A_UINT32              set_mask;             /* pins to set */
+    A_UINT32              clear_mask;           /* pins to clear */
+    A_UINT32              enable_mask;          /* pins to enable for output */
+    A_UINT32              disable_mask;         /* pins to disable/tristate */
+} POSTPACK WMIX_GPIO_OUTPUT_SET_CMD;
+
+/* 
+ * Set a GPIO register.  For debug/exceptional cases.
+ * Values for gpioreg_id are GPIO_REGISTER_IDs, defined in a
+ * platform-dependent header.
+ */
+typedef PREPACK struct {
+    A_UINT32              gpioreg_id;           /* GPIO register ID */
+    A_UINT32              value;                /* value to write */
+} POSTPACK WMIX_GPIO_REGISTER_SET_CMD;
+
+/* Get a GPIO register.  For debug/exceptional cases. */
+typedef PREPACK struct {
+    A_UINT32              gpioreg_id;           /* GPIO register to read */
+} POSTPACK WMIX_GPIO_REGISTER_GET_CMD;
+
+/*
+ * Host acknowledges and re-arms GPIO interrupts.  A single
+ * message should be used to acknowledge all interrupts that
+ * were delivered in an earlier WMIX_GPIO_INTR_EVENT message.
+ */
+typedef PREPACK struct {
+    A_UINT32              ack_mask;             /* interrupts to acknowledge */
+} POSTPACK WMIX_GPIO_INTR_ACK_CMD;
+
+/*
+ * Target informs Host of GPIO interrupts that have ocurred since the
+ * last WMIX_GIPO_INTR_ACK_CMD was received.  Additional information --
+ * the current GPIO input values is provided -- in order to support
+ * use of a GPIO interrupt as a Data Valid signal for other GPIO pins.
+ */
+typedef PREPACK struct {
+    A_UINT32              intr_mask;            /* pending GPIO interrupts */
+    A_UINT32              input_values;         /* recent GPIO input values */
+} POSTPACK WMIX_GPIO_INTR_EVENT;
+
+/*
+ * Target responds to Host's earlier WMIX_GPIO_INPUT_GET_CMDID request
+ * using a GPIO_DATA_EVENT with
+ *   value set to the mask of GPIO pin inputs and
+ *   reg_id set to GPIO_ID_NONE
+ * 
+ *
+ * Target responds to Hosts's earlier WMIX_GPIO_REGISTER_GET_CMDID request
+ * using a GPIO_DATA_EVENT with
+ *   value set to the value of the requested register and
+ *   reg_id identifying the register (reflects the original request)
+ * NB: reg_id supports the future possibility of unsolicited
+ * WMIX_GPIO_DATA_EVENTs (for polling GPIO input), and it may
+ * simplify Host GPIO support.
+ */
+typedef PREPACK struct {
+    A_UINT32              value;
+    A_UINT32              reg_id;
+} POSTPACK WMIX_GPIO_DATA_EVENT;
+
+/*
+ * =============Error Detection support=================
+ */
+
+/*
+ * WMIX_HB_CHALLENGE_RESP_CMDID
+ * Heartbeat Challenge Response command
+ */
+typedef PREPACK struct {
+    A_UINT32              cookie;
+    A_UINT32              source;
+} POSTPACK WMIX_HB_CHALLENGE_RESP_CMD;
+
+/*
+ * WMIX_HB_CHALLENGE_RESP_EVENTID
+ * Heartbeat Challenge Response Event
+ */
+#define WMIX_HB_CHALLENGE_RESP_EVENT WMIX_HB_CHALLENGE_RESP_CMD
+
+typedef PREPACK struct {
+    struct dbglog_config_s config;
+} POSTPACK WMIX_DBGLOG_CFG_MODULE_CMD;
+
+/*
+ * =============Target Profiling support=================
+ */
+
+typedef PREPACK struct {
+    A_UINT32 period; /* Time (in 30.5us ticks) between samples */
+    A_UINT32 nbins;
+} POSTPACK WMIX_PROF_CFG_CMD;
+
+typedef PREPACK struct {
+    A_UINT32 addr;
+} POSTPACK WMIX_PROF_ADDR_SET_CMD;
+
+/*
+ * Target responds to Hosts's earlier WMIX_PROF_COUNT_GET_CMDID request
+ * using a WMIX_PROF_COUNT_EVENT with
+ *   addr set to the next address
+ *   count set to the corresponding count
+ */
+typedef PREPACK struct {
+    A_UINT32              addr;
+    A_UINT32              count;
+} POSTPACK WMIX_PROF_COUNT_EVENT;
+
+#ifndef ATH_TARGET
+#include "athendpack.h"
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _WMIX_H_ */
diff --git a/drivers/net/ath6kl/include/common_drv.h b/drivers/net/ath6kl/include/common_drv.h
new file mode 100644
index 00000000000..8ebb93d5f3c
--- /dev/null
+++ b/drivers/net/ath6kl/include/common_drv.h
@@ -0,0 +1,108 @@
+//------------------------------------------------------------------------------
+// Copyright (c) 2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef COMMON_DRV_H_
+#define COMMON_DRV_H_
+
+#include "hif.h"
+#include "htc_packet.h"
+#include "htc_api.h"
+
+/* structure that is the state information for the default credit distribution callback
+ * drivers should instantiate (zero-init as well) this structure in their driver instance
+ * and pass it as a context to the HTC credit distribution functions */
+typedef struct _COMMON_CREDIT_STATE_INFO {
+    int TotalAvailableCredits;      /* total credits in the system at startup */
+    int CurrentFreeCredits;         /* credits available in the pool that have not been
+                                       given out to endpoints */
+    HTC_ENDPOINT_CREDIT_DIST *pLowestPriEpDist;  /* pointer to the lowest priority endpoint dist struct */
+} COMMON_CREDIT_STATE_INFO;
+
+typedef struct {
+    A_INT32 (*setupTransport)(void *ar);
+    void (*cleanupTransport)(void *ar);
+} HCI_TRANSPORT_CALLBACKS;
+
+typedef struct {
+   void *netDevice;
+   void *hifDevice;
+   void *htcHandle;
+} HCI_TRANSPORT_MISC_HANDLES;
+
+/* HTC TX packet tagging definitions */
+#define AR6K_CONTROL_PKT_TAG    HTC_TX_PACKET_TAG_USER_DEFINED
+#define AR6K_DATA_PKT_TAG       (AR6K_CONTROL_PKT_TAG + 1)
+
+#define AR6002_VERSION_REV1     0x20000086
+#define AR6002_VERSION_REV2     0x20000188
+#define AR6003_VERSION_REV1     0x300002ba
+#define AR6003_VERSION_REV2     0x30000384
+
+#define AR6002_CUST_DATA_SIZE 112
+#define AR6003_CUST_DATA_SIZE 16
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* OS-independent APIs */
+A_STATUS ar6000_setup_credit_dist(HTC_HANDLE HTCHandle, COMMON_CREDIT_STATE_INFO *pCredInfo);
+
+A_STATUS ar6000_ReadRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data);
+
+A_STATUS ar6000_WriteRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data);
+
+A_STATUS ar6000_ReadDataDiag(HIF_DEVICE *hifDevice, A_UINT32 address,  A_UCHAR *data, A_UINT32 length);
+
+A_STATUS ar6000_reset_device(HIF_DEVICE *hifDevice, A_UINT32 TargetType, A_BOOL waitForCompletion, A_BOOL coldReset);
+
+void ar6000_dump_target_assert_info(HIF_DEVICE *hifDevice, A_UINT32 TargetType);
+
+A_STATUS ar6000_set_htc_params(HIF_DEVICE *hifDevice,
+                               A_UINT32    TargetType,
+                               A_UINT32    MboxIsrYieldValue,
+                               A_UINT8     HtcControlBuffers);
+
+A_STATUS ar6000_prepare_target(HIF_DEVICE *hifDevice,
+                               A_UINT32    TargetType,
+                               A_UINT32    TargetVersion);
+
+A_STATUS ar6000_set_hci_bridge_flags(HIF_DEVICE *hifDevice,
+                                     A_UINT32    TargetType,
+                                     A_UINT32    Flags);
+
+void ar6000_copy_cust_data_from_target(HIF_DEVICE *hifDevice, A_UINT32 TargetType);
+
+A_UINT8 *ar6000_get_cust_data_buffer(A_UINT32 TargetType);
+
+A_STATUS ar6000_setBTState(void *context, A_UINT8 *pInBuf, A_UINT32 InBufSize);
+
+A_STATUS ar6000_setDevicePowerState(void *context, A_UINT8 *pInBuf, A_UINT32 InBufSize);
+
+A_STATUS ar6000_setWowMode(void *context, A_UINT8 *pInBuf, A_UINT32 InBufSize);
+
+A_STATUS ar6000_setHostMode(void *context, A_UINT8 *pInBuf, A_UINT32 InBufSize);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*COMMON_DRV_H_*/
diff --git a/drivers/net/ath6kl/include/dbglog_api.h b/drivers/net/ath6kl/include/dbglog_api.h
new file mode 100644
index 00000000000..a53aed316e3
--- /dev/null
+++ b/drivers/net/ath6kl/include/dbglog_api.h
@@ -0,0 +1,52 @@
+//------------------------------------------------------------------------------
+// <copyright file="dbglog_api.h" company="Atheros">
+//    Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// This file contains host side debug primitives.
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _DBGLOG_API_H_
+#define _DBGLOG_API_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "dbglog.h"
+
+#define DBGLOG_HOST_LOG_BUFFER_SIZE            DBGLOG_LOG_BUFFER_SIZE
+
+#define DBGLOG_GET_DBGID(arg) \
+    ((arg & DBGLOG_DBGID_MASK) >> DBGLOG_DBGID_OFFSET)
+
+#define DBGLOG_GET_MODULEID(arg) \
+    ((arg & DBGLOG_MODULEID_MASK) >> DBGLOG_MODULEID_OFFSET)
+
+#define DBGLOG_GET_NUMARGS(arg) \
+    ((arg & DBGLOG_NUM_ARGS_MASK) >> DBGLOG_NUM_ARGS_OFFSET)
+
+#define DBGLOG_GET_TIMESTAMP(arg) \
+    ((arg & DBGLOG_TIMESTAMP_MASK) >> DBGLOG_TIMESTAMP_OFFSET)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DBGLOG_API_H_ */
diff --git a/drivers/net/ath6kl/include/dl_list.h b/drivers/net/ath6kl/include/dl_list.h
new file mode 100644
index 00000000000..110e1d8b047
--- /dev/null
+++ b/drivers/net/ath6kl/include/dl_list.h
@@ -0,0 +1,153 @@
+//------------------------------------------------------------------------------
+// <copyright file="dl_list.h" company="Atheros">
+//    Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Double-link list definitions (adapted from Atheros SDIO stack)
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef __DL_LIST_H___
+#define __DL_LIST_H___
+
+#include "a_osapi.h"
+
+#define A_CONTAINING_STRUCT(address, struct_type, field_name)\
+            ((struct_type *)((unsigned long)(address) - (unsigned long)(&((struct_type *)0)->field_name)))
+         
+/* list functions */
+/* pointers for the list */
+typedef struct _DL_LIST {
+    struct _DL_LIST *pPrev;
+    struct _DL_LIST *pNext;
+}DL_LIST, *PDL_LIST;
+/*
+ * DL_LIST_INIT , initialize doubly linked list
+*/
+#define DL_LIST_INIT(pList)\
+    {(pList)->pPrev = pList; (pList)->pNext = pList;}
+
+/* faster macro to init list and add a single item */    
+#define DL_LIST_INIT_AND_ADD(pList,pItem) \
+{   (pList)->pPrev = (pItem); \
+    (pList)->pNext = (pItem); \
+    (pItem)->pNext = (pList); \
+    (pItem)->pPrev = (pList); \
+}
+    
+#define DL_LIST_IS_EMPTY(pList) (((pList)->pPrev == (pList)) && ((pList)->pNext == (pList)))
+#define DL_LIST_GET_ITEM_AT_HEAD(pList) (pList)->pNext
+#define DL_LIST_GET_ITEM_AT_TAIL(pList) (pList)->pPrev
+/*
+ * ITERATE_OVER_LIST pStart is the list, pTemp is a temp list member
+ * NOT: do not use this function if the items in the list are deleted inside the
+ * iteration loop
+*/
+#define ITERATE_OVER_LIST(pStart, pTemp) \
+    for((pTemp) =(pStart)->pNext; pTemp != (pStart); (pTemp) = (pTemp)->pNext)
+
+
+/* safe iterate macro that allows the item to be removed from the list
+ * the iteration continues to the next item in the list
+ */
+#define ITERATE_OVER_LIST_ALLOW_REMOVE(pStart,pItem,st,offset)  \
+{                                                       \
+    PDL_LIST  pTemp;                                     \
+    pTemp = (pStart)->pNext;                            \
+    while (pTemp != (pStart)) {                         \
+        (pItem) = A_CONTAINING_STRUCT(pTemp,st,offset);   \
+         pTemp = pTemp->pNext;                          \
+
+#define ITERATE_END }}
+
+/*
+ * DL_ListInsertTail - insert pAdd to the end of the list
+*/
+static INLINE PDL_LIST DL_ListInsertTail(PDL_LIST pList, PDL_LIST pAdd) {
+        /* insert at tail */
+    pAdd->pPrev = pList->pPrev;
+    pAdd->pNext = pList;
+    pList->pPrev->pNext = pAdd;
+    pList->pPrev = pAdd;
+    return pAdd;
+}
+
+/*
+ * DL_ListInsertHead - insert pAdd into the head of the list
+*/
+static INLINE PDL_LIST DL_ListInsertHead(PDL_LIST pList, PDL_LIST pAdd) {
+        /* insert at head */
+    pAdd->pPrev = pList;
+    pAdd->pNext = pList->pNext;
+    pList->pNext->pPrev = pAdd;
+    pList->pNext = pAdd;
+    return pAdd;
+}
+
+#define DL_ListAdd(pList,pItem) DL_ListInsertHead((pList),(pItem))
+/*
+ * DL_ListRemove - remove pDel from list
+*/
+static INLINE PDL_LIST DL_ListRemove(PDL_LIST pDel) {
+    pDel->pNext->pPrev = pDel->pPrev;
+    pDel->pPrev->pNext = pDel->pNext;
+        /* point back to itself just to be safe, incase remove is called again */
+    pDel->pNext = pDel;
+    pDel->pPrev = pDel;
+    return pDel;
+}
+
+/*
+ * DL_ListRemoveItemFromHead - get a list item from the head
+*/
+static INLINE PDL_LIST DL_ListRemoveItemFromHead(PDL_LIST pList) {
+    PDL_LIST pItem = NULL;
+    if (pList->pNext != pList) {
+        pItem = pList->pNext;
+            /* remove the first item from head */
+        DL_ListRemove(pItem);
+    }
+    return pItem;
+}
+
+static INLINE PDL_LIST DL_ListRemoveItemFromTail(PDL_LIST pList) {
+    PDL_LIST pItem = NULL;
+    if (pList->pPrev != pList) {
+        pItem = pList->pPrev;
+            /* remove the item from tail */
+        DL_ListRemove(pItem);
+    }
+    return pItem;
+}
+
+/* transfer src list items to the tail of the destination list */
+static INLINE void DL_ListTransferItemsToTail(PDL_LIST pDest, PDL_LIST pSrc) {
+        /* only concatenate if src is not empty */
+    if (!DL_LIST_IS_EMPTY(pSrc)) {
+            /* cut out circular list in src and re-attach to end of dest */
+        pSrc->pPrev->pNext = pDest;
+        pSrc->pNext->pPrev = pDest->pPrev;
+        pDest->pPrev->pNext = pSrc->pNext; 
+        pDest->pPrev = pSrc->pPrev;
+            /* terminate src list, it is now empty */      
+        pSrc->pPrev = pSrc;
+        pSrc->pNext = pSrc;
+    }
+}
+
+#endif /* __DL_LIST_H___ */
diff --git a/drivers/net/ath6kl/include/dset_api.h b/drivers/net/ath6kl/include/dset_api.h
new file mode 100644
index 00000000000..0cc121fd25a
--- /dev/null
+++ b/drivers/net/ath6kl/include/dset_api.h
@@ -0,0 +1,65 @@
+//------------------------------------------------------------------------------
+// <copyright file="dset_api.h" company="Atheros">
+//    Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Host-side DataSet API.
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _DSET_API_H_
+#define _DSET_API_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/*
+ * Host-side DataSet support is optional, and is not
+ * currently required for correct operation.  To disable
+ * Host-side DataSet support, set this to 0.
+ */
+#ifndef CONFIG_HOST_DSET_SUPPORT
+#define CONFIG_HOST_DSET_SUPPORT 1
+#endif
+
+/* Called to send a DataSet Open Reply back to the Target. */
+A_STATUS wmi_dset_open_reply(struct wmi_t *wmip,
+                             A_UINT32 status,
+                             A_UINT32 access_cookie,
+                             A_UINT32 size,
+                             A_UINT32 version,
+                             A_UINT32 targ_handle,
+                             A_UINT32 targ_reply_fn,
+                             A_UINT32 targ_reply_arg);
+
+/* Called to send a DataSet Data Reply back to the Target. */
+A_STATUS wmi_dset_data_reply(struct wmi_t *wmip,
+                             A_UINT32 status,
+                             A_UINT8 *host_buf,
+                             A_UINT32 length,
+                             A_UINT32 targ_buf,
+                             A_UINT32 targ_reply_fn,
+                             A_UINT32 targ_reply_arg);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+
+#endif /* _DSET_API_H_ */
diff --git a/drivers/net/ath6kl/include/gpio_api.h b/drivers/net/ath6kl/include/gpio_api.h
new file mode 100644
index 00000000000..96a15038335
--- /dev/null
+++ b/drivers/net/ath6kl/include/gpio_api.h
@@ -0,0 +1,59 @@
+//------------------------------------------------------------------------------
+// <copyright file="gpio_api.h" company="Atheros">
+//    Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Host-side General Purpose I/O API.
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _GPIO_API_H_
+#define _GPIO_API_H_
+
+/*
+ * Send a command to the Target in order to change output on GPIO pins.
+ */
+A_STATUS wmi_gpio_output_set(struct wmi_t *wmip,
+                             A_UINT32 set_mask,
+                             A_UINT32 clear_mask,
+                             A_UINT32 enable_mask,
+                             A_UINT32 disable_mask);
+
+/*
+ * Send a command to the Target requesting input state of GPIO pins.
+ */
+A_STATUS wmi_gpio_input_get(struct wmi_t *wmip);
+
+/*
+ * Send a command to the Target to change the value of a GPIO register.
+ */
+A_STATUS wmi_gpio_register_set(struct wmi_t *wmip,
+                               A_UINT32 gpioreg_id,
+                               A_UINT32 value);
+
+/*
+ * Send a command to the Target to fetch the value of a GPIO register.
+ */
+A_STATUS wmi_gpio_register_get(struct wmi_t *wmip, A_UINT32 gpioreg_id);
+
+/*
+ * Send a command to the Target, acknowledging some GPIO interrupts.
+ */
+A_STATUS wmi_gpio_intr_ack(struct wmi_t *wmip, A_UINT32 ack_mask);
+
+#endif /* _GPIO_API_H_ */
diff --git a/drivers/net/ath6kl/include/hci_transport_api.h b/drivers/net/ath6kl/include/hci_transport_api.h
new file mode 100644
index 00000000000..b5157ea5d9e
--- /dev/null
+++ b/drivers/net/ath6kl/include/hci_transport_api.h
@@ -0,0 +1,259 @@
+//------------------------------------------------------------------------------
+// Copyright (c) 2009-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _HCI_TRANSPORT_API_H_
+#define _HCI_TRANSPORT_API_H_
+
+    /* Bluetooth HCI packets are stored in HTC packet containers */
+#include "htc_packet.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+typedef void *HCI_TRANSPORT_HANDLE;
+
+typedef HTC_ENDPOINT_ID HCI_TRANSPORT_PACKET_TYPE; 
+
+    /* we map each HCI packet class to a static Endpoint ID */
+#define HCI_COMMAND_TYPE   ENDPOINT_1
+#define HCI_EVENT_TYPE     ENDPOINT_2
+#define HCI_ACL_TYPE       ENDPOINT_3
+#define HCI_PACKET_INVALID ENDPOINT_MAX
+
+#define HCI_GET_PACKET_TYPE(pP)    (pP)->Endpoint
+#define HCI_SET_PACKET_TYPE(pP,s)  (pP)->Endpoint = (s)
+
+/* callback when an HCI packet was completely sent */
+typedef void   (*HCI_TRANSPORT_SEND_PKT_COMPLETE)(void *, HTC_PACKET *);
+/* callback when an HCI packet is received */
+typedef void   (*HCI_TRANSPORT_RECV_PKT)(void *, HTC_PACKET *);
+/* Optional receive buffer re-fill callback,
+ * On some OSes (like Linux) packets are allocated from a global pool and indicated up
+ * to the network stack.  The driver never gets the packets back from the OS.  For these OSes
+ * a refill callback can be used to allocate and re-queue buffers into HTC.
+ * A refill callback is used for the reception of ACL and EVENT packets.  The caller must
+ * set the watermark trigger point to cause a refill.
+ */
+typedef void   (*HCI_TRANSPORT_RECV_REFILL)(void *, HCI_TRANSPORT_PACKET_TYPE Type, int BuffersAvailable);
+/* Optional receive packet refill
+ * On some systems packet buffers are an extremely limited resource.  Rather than
+ * queue largest-possible-sized buffers to the HCI bridge, some systems would rather
+ * allocate a specific size as the packet is received.  The trade off is
+ * slightly more processing (callback invoked for each RX packet)
+ * for the benefit of committing fewer buffer resources into the bridge.
+ *
+ * The callback is provided the length of the pending packet to fetch. This includes the
+ * full transport header, HCI header, plus the length of payload.  The callback can return a pointer to
+ * the allocated HTC packet for immediate use.
+ *
+ * NOTE*** This callback is mutually exclusive with the the refill callback above.
+ *
+ * */
+typedef HTC_PACKET *(*HCI_TRANSPORT_RECV_ALLOC)(void *, HCI_TRANSPORT_PACKET_TYPE Type, int Length);
+
+typedef enum _HCI_SEND_FULL_ACTION {
+    HCI_SEND_FULL_KEEP = 0,  /* packet that overflowed should be kept in the queue */
+    HCI_SEND_FULL_DROP = 1,  /* packet that overflowed should be dropped */
+} HCI_SEND_FULL_ACTION;
+
+/* callback when an HCI send queue exceeds the caller's MaxSendQueueDepth threshold,
+ * the callback must return the send full action to take (either DROP or KEEP) */
+typedef HCI_SEND_FULL_ACTION  (*HCI_TRANSPORT_SEND_FULL)(void *, HTC_PACKET *);
+
+typedef struct {
+    int    HeadRoom;      /* number of bytes in front of HCI packet for header space */
+    int    TailRoom;      /* number of bytes at the end of the HCI packet for tail space */
+    int    IOBlockPad;    /* I/O block padding required (always a power of 2) */
+} HCI_TRANSPORT_PROPERTIES;
+
+typedef struct _HCI_TRANSPORT_CONFIG_INFO {
+    int      ACLRecvBufferWaterMark;     /* low watermark to trigger recv refill */
+    int      EventRecvBufferWaterMark;   /* low watermark to trigger recv refill */  
+    int      MaxSendQueueDepth;          /* max number of packets in the single send queue */
+    void     *pContext;                  /* context for all callbacks */
+    void     (*TransportFailure)(void *pContext, A_STATUS Status); /* transport failure callback */
+    A_STATUS (*TransportReady)(HCI_TRANSPORT_HANDLE, HCI_TRANSPORT_PROPERTIES *,void *pContext); /* transport is ready */
+    void     (*TransportRemoved)(void *pContext);                  /* transport was removed */
+        /* packet processing callbacks */
+    HCI_TRANSPORT_SEND_PKT_COMPLETE    pHCISendComplete;
+    HCI_TRANSPORT_RECV_PKT             pHCIPktRecv;
+    HCI_TRANSPORT_RECV_REFILL          pHCIPktRecvRefill;
+    HCI_TRANSPORT_RECV_ALLOC           pHCIPktRecvAlloc;
+    HCI_TRANSPORT_SEND_FULL            pHCISendFull;
+} HCI_TRANSPORT_CONFIG_INFO;
+
+/* ------ Function Prototypes ------ */
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+  @desc: Attach to the HCI transport module
+  @function name: HCI_TransportAttach
+  @input:  HTCHandle - HTC handle (see HTC apis)
+           pInfo - initialization information
+  @output:
+  @return: HCI_TRANSPORT_HANDLE on success, NULL on failure
+  @notes:    The HTC module provides HCI transport services.
+  @example:
+  @see also: HCI_TransportDetach
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+HCI_TRANSPORT_HANDLE HCI_TransportAttach(void *HTCHandle, HCI_TRANSPORT_CONFIG_INFO *pInfo);
+
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+  @desc: Detach from the HCI transport module
+  @function name: HCI_TransportDetach
+  @input:  HciTrans - HCI transport handle
+           pInfo - initialization information
+  @output:
+  @return: 
+  @notes:  
+  @example:
+  @see also: 
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+void HCI_TransportDetach(HCI_TRANSPORT_HANDLE HciTrans);
+
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+  @desc: Add receive packets to the HCI transport
+  @function name: HCI_TransportAddReceivePkts
+  @input:  HciTrans - HCI transport handle
+           pQueue - a queue holding one or more packets
+  @output:
+  @return: A_OK on success
+  @notes:  user must supply HTC packets for capturing incomming HCI packets.  The caller
+           must initialize each HTC packet using the SET_HTC_PACKET_INFO_RX_REFILL()
+           macro. Each packet in the queue must be of the same type and length 
+  @example:
+  @see also:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+A_STATUS    HCI_TransportAddReceivePkts(HCI_TRANSPORT_HANDLE HciTrans, HTC_PACKET_QUEUE *pQueue);
+
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+  @desc: Send an HCI packet packet
+  @function name: HCI_TransportSendPkt
+  @input:  HciTrans - HCI transport handle
+           pPacket - packet to send
+           Synchronous - send the packet synchronously (blocking)
+  @output:
+  @return: A_OK
+  @notes:  Caller must initialize packet using SET_HTC_PACKET_INFO_TX() and
+           HCI_SET_PACKET_TYPE() macros to prepare the packet. 
+           If Synchronous is set to FALSE the call is fully asynchronous.  On error or completion, 
+           the registered send complete callback will be called.
+           If Synchronous is set to TRUE, the call will block until the packet is sent, if the
+           interface cannot send the packet within a 2 second timeout, the function will return 
+           the failure code : A_EBUSY.
+           
+           Synchronous Mode should only be used at start-up to initialize the HCI device using 
+           custom HCI commands.  It should NOT be mixed with Asynchronous operations.  Mixed synchronous
+           and asynchronous operation behavior is undefined.
+           
+  @example:
+  @see also: 
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+A_STATUS    HCI_TransportSendPkt(HCI_TRANSPORT_HANDLE HciTrans, HTC_PACKET *pPacket, A_BOOL Synchronous);
+
+
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+  @desc: Stop HCI transport
+  @function name: HCI_TransportStop
+  @input:  HciTrans - hci transport handle 
+  @output:
+  @return:
+  @notes: HCI transport communication will be halted.  All receive and pending TX packets will
+          be flushed.
+  @example:
+  @see also:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+void        HCI_TransportStop(HCI_TRANSPORT_HANDLE HciTrans);
+
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+  @desc: Start the HCI transport
+  @function name: HCI_TransportStart
+  @input:  HciTrans - hci transport handle 
+  @output:
+  @return: A_OK on success
+  @notes: HCI transport communication will begin, the caller can expect the arrival
+          of HCI recv packets as soon as this call returns.
+  @example:
+  @see also:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+A_STATUS    HCI_TransportStart(HCI_TRANSPORT_HANDLE HciTrans);
+
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+  @desc: Enable or Disable Asynchronous Recv
+  @function name: HCI_TransportEnableDisableAsyncRecv
+  @input:  HciTrans - hci transport handle 
+           Enable - enable or disable asynchronous recv
+  @output:
+  @return: A_OK on success
+  @notes: This API must be called when HCI recv is handled synchronously
+  @example:
+  @see also:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+A_STATUS    HCI_TransportEnableDisableAsyncRecv(HCI_TRANSPORT_HANDLE HciTrans, A_BOOL Enable);
+
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+  @desc: Receive an event packet from the HCI transport synchronously using polling
+  @function name: HCI_TransportRecvHCIEventSync
+  @input:  HciTrans - hci transport handle 
+           pPacket - HTC packet to hold the recv data
+           MaxPollMS - maximum polling duration in Milliseconds;
+  @output: 
+  @return: A_OK on success
+  @notes: This API should be used only during HCI device initialization, the caller must call
+          HCI_TransportEnableDisableAsyncRecv with Enable=FALSE prior to using this API. 
+          This API will only capture HCI Event packets.
+  @example:
+  @see also: HCI_TransportEnableDisableAsyncRecv
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+A_STATUS    HCI_TransportRecvHCIEventSync(HCI_TRANSPORT_HANDLE HciTrans, 
+                                          HTC_PACKET           *pPacket,
+                                          int                  MaxPollMS);
+
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+  @desc: Set the desired baud rate for the underlying transport layer
+  @function name: HCI_TransportSetBaudRate
+  @input:  HciTrans - hci transport handle 
+           Baud - baud rate in bps
+  @output: 
+  @return: A_OK on success
+  @notes: This API should be used only after HCI device initialization
+  @example:
+  @see also: 
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+A_STATUS    HCI_TransportSetBaudRate(HCI_TRANSPORT_HANDLE HciTrans, A_UINT32 Baud);
+
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+  @desc: Enable/Disable HCI Transport Power Management
+  @function name: HCI_TransportEnablePowerMgmt
+  @input:  HciTrans - hci transport handle 
+           Enable - 1 = Enable, 0 = Disable
+  @output: 
+  @return: A_OK on success
+  @notes: 
+  @example:
+  @see also: 
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+A_STATUS HCI_TransportEnablePowerMgmt(HCI_TRANSPORT_HANDLE HciTrans, A_BOOL Enable);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HCI_TRANSPORT_API_H_ */
diff --git a/drivers/net/ath6kl/include/hif.h b/drivers/net/ath6kl/include/hif.h
new file mode 100644
index 00000000000..2a082678512
--- /dev/null
+++ b/drivers/net/ath6kl/include/hif.h
@@ -0,0 +1,458 @@
+//------------------------------------------------------------------------------
+// <copyright file="hif.h" company="Atheros">
+//    Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// HIF specific declarations and prototypes
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _HIF_H_
+#define _HIF_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* Header files */
+#include "a_config.h"
+#include "athdefs.h"
+#include "a_types.h"
+#include "a_osapi.h"
+#include "dl_list.h"
+
+
+typedef struct htc_callbacks HTC_CALLBACKS;
+typedef struct hif_device HIF_DEVICE;
+
+/*
+ * direction - Direction of transfer (HIF_READ/HIF_WRITE).
+ */
+#define HIF_READ                    0x00000001
+#define HIF_WRITE                   0x00000002
+#define HIF_DIR_MASK                (HIF_READ | HIF_WRITE)
+
+/*
+ *     type - An interface may support different kind of read/write commands.
+ *            For example: SDIO supports CMD52/CMD53s. In case of MSIO it
+ *            translates to using different kinds of TPCs. The command type
+ *            is thus divided into a basic and an extended command and can
+ *            be specified using HIF_BASIC_IO/HIF_EXTENDED_IO.
+ */
+#define HIF_BASIC_IO                0x00000004
+#define HIF_EXTENDED_IO             0x00000008
+#define HIF_TYPE_MASK               (HIF_BASIC_IO | HIF_EXTENDED_IO)
+
+/*
+ *     emode - This indicates the whether the command is to be executed in a
+ *             blocking or non-blocking fashion (HIF_SYNCHRONOUS/
+ *             HIF_ASYNCHRONOUS). The read/write data paths in HTC have been
+ *             implemented using the asynchronous mode allowing the the bus
+ *             driver to indicate the completion of operation through the
+ *             registered callback routine. The requirement primarily comes
+ *             from the contexts these operations get called from (a driver's
+ *             transmit context or the ISR context in case of receive).
+ *             Support for both of these modes is essential.
+ */
+#define HIF_SYNCHRONOUS             0x00000010
+#define HIF_ASYNCHRONOUS            0x00000020
+#define HIF_EMODE_MASK              (HIF_SYNCHRONOUS | HIF_ASYNCHRONOUS)
+
+/*
+ *     dmode - An interface may support different kinds of commands based on
+ *             the tradeoff between the amount of data it can carry and the
+ *             setup time. Byte and Block modes are supported (HIF_BYTE_BASIS/
+ *             HIF_BLOCK_BASIS). In case of latter, the data is rounded off
+ *             to the nearest block size by padding. The size of the block is
+ *             configurable at compile time using the HIF_BLOCK_SIZE and is
+ *             negotiated with the target during initialization after the
+ *             AR6000 interrupts are enabled.
+ */
+#define HIF_BYTE_BASIS              0x00000040
+#define HIF_BLOCK_BASIS             0x00000080
+#define HIF_DMODE_MASK              (HIF_BYTE_BASIS | HIF_BLOCK_BASIS)
+
+/*
+ *     amode - This indicates if the address has to be incremented on AR6000 
+ *             after every read/write operation (HIF?FIXED_ADDRESS/
+ *             HIF_INCREMENTAL_ADDRESS).
+ */
+#define HIF_FIXED_ADDRESS           0x00000100
+#define HIF_INCREMENTAL_ADDRESS     0x00000200
+#define HIF_AMODE_MASK              (HIF_FIXED_ADDRESS | HIF_INCREMENTAL_ADDRESS)
+
+#define HIF_WR_ASYNC_BYTE_FIX   \
+    (HIF_WRITE | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_FIXED_ADDRESS)
+#define HIF_WR_ASYNC_BYTE_INC   \
+    (HIF_WRITE | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS)
+#define HIF_WR_ASYNC_BLOCK_INC  \
+    (HIF_WRITE | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS)
+#define HIF_WR_SYNC_BYTE_FIX    \
+    (HIF_WRITE | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_FIXED_ADDRESS)
+#define HIF_WR_SYNC_BYTE_INC    \
+    (HIF_WRITE | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS)
+#define HIF_WR_SYNC_BLOCK_INC  \
+    (HIF_WRITE | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS)
+#define HIF_WR_ASYNC_BLOCK_FIX \
+    (HIF_WRITE | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_FIXED_ADDRESS)
+#define HIF_WR_SYNC_BLOCK_FIX  \
+    (HIF_WRITE | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_FIXED_ADDRESS)
+#define HIF_RD_SYNC_BYTE_INC    \
+    (HIF_READ | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS)
+#define HIF_RD_SYNC_BYTE_FIX    \
+    (HIF_READ | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_FIXED_ADDRESS)
+#define HIF_RD_ASYNC_BYTE_FIX   \
+    (HIF_READ | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_FIXED_ADDRESS)
+#define HIF_RD_ASYNC_BLOCK_FIX  \
+    (HIF_READ | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_FIXED_ADDRESS)
+#define HIF_RD_ASYNC_BYTE_INC   \
+    (HIF_READ | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS)
+#define HIF_RD_ASYNC_BLOCK_INC  \
+    (HIF_READ | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS)
+#define HIF_RD_SYNC_BLOCK_INC  \
+    (HIF_READ | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS)
+#define HIF_RD_SYNC_BLOCK_FIX  \
+    (HIF_READ | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_FIXED_ADDRESS)
+    
+typedef enum {
+    HIF_DEVICE_POWER_STATE = 0,
+    HIF_DEVICE_GET_MBOX_BLOCK_SIZE,
+    HIF_DEVICE_GET_MBOX_ADDR,
+    HIF_DEVICE_GET_PENDING_EVENTS_FUNC,
+    HIF_DEVICE_GET_IRQ_PROC_MODE,
+    HIF_DEVICE_GET_RECV_EVENT_MASK_UNMASK_FUNC,
+    HIF_DEVICE_POWER_STATE_CHANGE,
+    HIF_DEVICE_GET_IRQ_YIELD_PARAMS,
+    HIF_CONFIGURE_QUERY_SCATTER_REQUEST_SUPPORT,
+    HIF_DEVICE_GET_OS_DEVICE,
+    HIF_DEVICE_DEBUG_BUS_STATE,
+} HIF_DEVICE_CONFIG_OPCODE;
+
+/*
+ * HIF CONFIGURE definitions:
+ *
+ *   HIF_DEVICE_GET_MBOX_BLOCK_SIZE
+ *   input : none
+ *   output : array of 4 A_UINT32s
+ *   notes: block size is returned for each mailbox (4)
+ *
+ *   HIF_DEVICE_GET_MBOX_ADDR
+ *   input : none
+ *   output : HIF_DEVICE_MBOX_INFO
+ *   notes: 
+ *
+ *   HIF_DEVICE_GET_PENDING_EVENTS_FUNC
+ *   input : none
+ *   output: HIF_PENDING_EVENTS_FUNC function pointer
+ *   notes: this is optional for the HIF layer, if the request is
+ *          not handled then it indicates that the upper layer can use
+ *          the standard device methods to get pending events (IRQs, mailbox messages etc..)
+ *          otherwise it can call the function pointer to check pending events.
+ *
+ *   HIF_DEVICE_GET_IRQ_PROC_MODE
+ *   input : none
+ *   output : HIF_DEVICE_IRQ_PROCESSING_MODE (interrupt processing mode)
+ *   note: the hif layer interfaces with the underlying OS-specific bus driver. The HIF
+ *         layer can report whether IRQ processing is requires synchronous behavior or
+ *         can be processed using asynchronous bus requests (typically faster).
+ *
+ *   HIF_DEVICE_GET_RECV_EVENT_MASK_UNMASK_FUNC
+ *   input :
+ *   output : HIF_MASK_UNMASK_RECV_EVENT function pointer
+ *   notes: this is optional for the HIF layer.  The HIF layer may require a special mechanism
+ *          to mask receive message events.  The upper layer can call this pointer when it needs
+ *          to mask/unmask receive events (in case it runs out of buffers).
+ *
+ *   HIF_DEVICE_POWER_STATE_CHANGE
+ *
+ *   input : HIF_DEVICE_POWER_CHANGE_TYPE
+ *   output : none
+ *   note: this is optional for the HIF layer.  The HIF layer can handle power on/off state change
+ *         requests in an interconnect specific way.  This is highly OS and bus driver dependent.
+ *         The caller must guarantee that no HIF read/write requests will be made after the device
+ *         is powered down.
+ *
+ *   HIF_DEVICE_GET_IRQ_YIELD_PARAMS
+ * 
+ *   input : none
+ *   output : HIF_DEVICE_IRQ_YIELD_PARAMS
+ *   note: This query checks if the HIF layer wishes to impose a processing yield count for the DSR handler.
+ *   The DSR callback handler will exit after a fixed number of RX packets or events are processed.  
+ *   This query is only made if the device reports an IRQ processing mode of HIF_DEVICE_IRQ_SYNC_ONLY. 
+ *   The HIF implementation can ignore this command if it does not desire the DSR callback to yield.
+ *   The HIF layer can indicate the maximum number of IRQ processing units (RX packets) before the
+ *   DSR handler callback must yield and return control back to the HIF layer.  When a yield limit is 
+ *   used the DSR callback will not call HIFAckInterrupts() as it would normally do before returning.  
+ *   The HIF implementation that requires a yield count must call HIFAckInterrupt() when it is prepared
+ *   to process interrupts again.
+ *   
+ *   HIF_CONFIGURE_QUERY_SCATTER_REQUEST_SUPPORT
+ *   input : none
+ *   output : HIF_DEVICE_SCATTER_SUPPORT_INFO
+ *   note:  This query checks if the HIF layer implements the SCATTER request interface.  Scatter requests
+ *   allows upper layers to submit mailbox I/O operations using a list of buffers.  This is useful for
+ *   multi-message transfers that can better utilize the bus interconnect.
+ * 
+ * 
+ *   HIF_DEVICE_GET_OS_DEVICE
+ *   intput : none
+ *   output : HIF_DEVICE_OS_DEVICE_INFO;
+ *   note: On some operating systems, the HIF layer has a parent device object for the bus.  This object
+ *         may be required to register certain types of logical devices.
+ * 
+ *   HIF_DEVICE_DEBUG_BUS_STATE
+ *   input : none
+ *   output : none
+ *   note: This configure option triggers the HIF interface to dump as much bus interface state.  This 
+ *   configuration request is optional (No-OP on some HIF implementations)
+ * 
+ */
+
+typedef struct {
+    A_UINT32    ExtendedAddress;  /* extended address for larger writes */  
+    A_UINT32    ExtendedSize;
+} HIF_MBOX_PROPERTIES;
+
+#define HIF_MBOX_FLAG_NO_BUNDLING   (1 << 0)   /* do not allow bundling over the mailbox */
+
+typedef enum _MBOX_BUF_IF_TYPE {
+    MBOX_BUS_IF_SDIO = 0,
+    MBOX_BUS_IF_SPI = 1,    
+} MBOX_BUF_IF_TYPE;
+
+typedef struct {
+    A_UINT32 MboxAddresses[4];  /* must be first element for legacy HIFs that return the address in  
+                                   and ARRAY of 32-bit words */
+    
+        /* the following describe extended mailbox properties */
+    HIF_MBOX_PROPERTIES MboxProp[4];
+        /* if the HIF supports the GMbox extended address region it can report it
+         * here, some interfaces cannot support the GMBOX address range and not set this */
+    A_UINT32 GMboxAddress;  
+    A_UINT32 GMboxSize;
+    A_UINT32 Flags;             /* flags to describe mbox behavior or usage */
+    MBOX_BUF_IF_TYPE MboxBusIFType;   /* mailbox bus interface type */
+} HIF_DEVICE_MBOX_INFO;
+
+typedef enum {
+    HIF_DEVICE_IRQ_SYNC_ONLY,   /* for HIF implementations that require the DSR to process all
+                                   interrupts before returning */
+    HIF_DEVICE_IRQ_ASYNC_SYNC,  /* for HIF implementations that allow DSR to process interrupts
+                                   using ASYNC I/O (that is HIFAckInterrupt can be called at a
+                                   later time */
+} HIF_DEVICE_IRQ_PROCESSING_MODE;
+
+typedef enum {
+    HIF_DEVICE_POWER_UP,    /* HIF layer should power up interface and/or module */
+    HIF_DEVICE_POWER_DOWN,  /* HIF layer should initiate bus-specific measures to minimize power */
+    HIF_DEVICE_POWER_CUT    /* HIF layer should initiate bus-specific AND/OR platform-specific measures
+                               to completely power-off the module and associated hardware (i.e. cut power supplies)
+                            */
+} HIF_DEVICE_POWER_CHANGE_TYPE;
+
+typedef struct {
+    int     RecvPacketYieldCount; /* max number of packets to force DSR to return */
+} HIF_DEVICE_IRQ_YIELD_PARAMS;
+
+
+typedef struct _HIF_SCATTER_ITEM {
+    A_UINT8     *pBuffer;             /* CPU accessible address of buffer */
+    int          Length;              /* length of transfer to/from this buffer */
+    void        *pCallerContexts[2];  /* space for caller to insert a context associated with this item */
+} HIF_SCATTER_ITEM;
+
+struct _HIF_SCATTER_REQ;
+
+typedef void ( *HIF_SCATTER_COMP_CB)(struct _HIF_SCATTER_REQ *);
+
+typedef enum _HIF_SCATTER_METHOD {
+    HIF_SCATTER_NONE = 0,
+    HIF_SCATTER_DMA_REAL,              /* Real SG support no restrictions */
+    HIF_SCATTER_DMA_BOUNCE,            /* Uses SG DMA but HIF layer uses an internal bounce buffer */    
+} HIF_SCATTER_METHOD;
+
+typedef struct _HIF_SCATTER_REQ {
+    DL_LIST             ListLink;           /* link management */
+    A_UINT32            Address;            /* address for the read/write operation */
+    A_UINT32            Request;            /* request flags */
+    A_UINT32            TotalLength;        /* total length of entire transfer */
+    A_UINT32            CallerFlags;        /* caller specific flags can be stored here */
+    HIF_SCATTER_COMP_CB CompletionRoutine;  /* completion routine set by caller */
+    A_STATUS            CompletionStatus;   /* status of completion */
+    void                *Context;           /* caller context for this request */
+    int                 ValidScatterEntries;  /* number of valid entries set by caller */
+    HIF_SCATTER_METHOD  ScatterMethod;        /* scatter method handled by HIF */  
+    void                *HIFPrivate[4];     /* HIF private area */
+    A_UINT8             *pScatterBounceBuffer;  /* bounce buffer for upper layers to copy to/from */
+    HIF_SCATTER_ITEM    ScatterList[1];     /* start of scatter list */
+} HIF_SCATTER_REQ;
+
+typedef HIF_SCATTER_REQ * ( *HIF_ALLOCATE_SCATTER_REQUEST)(HIF_DEVICE *device);
+typedef void ( *HIF_FREE_SCATTER_REQUEST)(HIF_DEVICE *device, HIF_SCATTER_REQ *request);
+typedef A_STATUS ( *HIF_READWRITE_SCATTER)(HIF_DEVICE *device, HIF_SCATTER_REQ *request);
+
+typedef struct _HIF_DEVICE_SCATTER_SUPPORT_INFO {
+        /* information returned from HIF layer */
+    HIF_ALLOCATE_SCATTER_REQUEST    pAllocateReqFunc;
+    HIF_FREE_SCATTER_REQUEST        pFreeReqFunc;
+    HIF_READWRITE_SCATTER           pReadWriteScatterFunc;    
+    int                             MaxScatterEntries;
+    int                             MaxTransferSizePerScatterReq;
+} HIF_DEVICE_SCATTER_SUPPORT_INFO;
+                      
+typedef struct {
+    void    *pOSDevice;
+} HIF_DEVICE_OS_DEVICE_INFO;
+                      
+#define HIF_MAX_DEVICES                 1
+
+struct htc_callbacks {
+    void      *context;     /* context to pass to the dsrhandler
+                               note : rwCompletionHandler is provided the context passed to HIFReadWrite  */
+    A_STATUS (* rwCompletionHandler)(void *rwContext, A_STATUS status);
+    A_STATUS (* dsrHandler)(void *context);
+};
+
+typedef struct osdrv_callbacks {
+    void      *context;     /* context to pass for all callbacks except deviceRemovedHandler 
+                               the deviceRemovedHandler is only called if the device is claimed */
+    A_STATUS (* deviceInsertedHandler)(void *context, void *hif_handle);
+    A_STATUS (* deviceRemovedHandler)(void *claimedContext, void *hif_handle);
+    A_STATUS (* deviceSuspendHandler)(void *context);
+    A_STATUS (* deviceResumeHandler)(void *context);
+    A_STATUS (* deviceWakeupHandler)(void *context);  
+    A_STATUS (* devicePowerChangeHandler)(void *context, HIF_DEVICE_POWER_CHANGE_TYPE config);  
+} OSDRV_CALLBACKS;
+
+#define HIF_OTHER_EVENTS     (1 << 0)   /* other interrupts (non-Recv) are pending, host
+                                           needs to read the register table to figure out what */
+#define HIF_RECV_MSG_AVAIL   (1 << 1)   /* pending recv packet */
+
+typedef struct _HIF_PENDING_EVENTS_INFO {
+    A_UINT32 Events;
+    A_UINT32 LookAhead;
+    A_UINT32 AvailableRecvBytes;
+#ifdef THREAD_X
+    A_UINT32 Polling;
+    A_UINT32 INT_CAUSE_REG;
+#endif
+} HIF_PENDING_EVENTS_INFO;
+
+    /* function to get pending events , some HIF modules use special mechanisms
+     * to detect packet available and other interrupts */
+typedef A_STATUS ( *HIF_PENDING_EVENTS_FUNC)(HIF_DEVICE              *device,
+                                             HIF_PENDING_EVENTS_INFO *pEvents,
+                                             void                    *AsyncContext);
+
+#define HIF_MASK_RECV    TRUE
+#define HIF_UNMASK_RECV  FALSE
+    /* function to mask recv events */
+typedef A_STATUS ( *HIF_MASK_UNMASK_RECV_EVENT)(HIF_DEVICE  *device,
+                                                A_BOOL      Mask,
+                                                void        *AsyncContext);
+
+
+/*
+ * This API is used to perform any global initialization of the HIF layer
+ * and to set OS driver callbacks (i.e. insertion/removal) to the HIF layer
+ * 
+ */
+A_STATUS HIFInit(OSDRV_CALLBACKS *callbacks);
+
+/* This API claims the HIF device and provides a context for handling removal.
+ * The device removal callback is only called when the OSDRV layer claims
+ * a device.  The claimed context must be non-NULL */
+void HIFClaimDevice(HIF_DEVICE *device, void *claimedContext);
+/* release the claimed device */
+void HIFReleaseDevice(HIF_DEVICE *device);
+
+/* This API allows the HTC layer to attach to the HIF device */
+A_STATUS HIFAttachHTC(HIF_DEVICE *device, HTC_CALLBACKS *callbacks);
+/* This API detaches the HTC layer from the HIF device */
+void     HIFDetachHTC(HIF_DEVICE *device);
+
+/*
+ * This API is used to provide the read/write interface over the specific bus
+ * interface.
+ * address - Starting address in the AR6000's address space. For mailbox
+ *           writes, it refers to the start of the mbox boundary. It should
+ *           be ensured that the last byte falls on the mailbox's EOM. For
+ *           mailbox reads, it refers to the end of the mbox boundary.
+ * buffer - Pointer to the buffer containg the data to be transmitted or
+ *          received.
+ * length - Amount of data to be transmitted or received.
+ * request - Characterizes the attributes of the command.
+ */
+A_STATUS
+HIFReadWrite(HIF_DEVICE    *device,
+             A_UINT32       address,
+             A_UCHAR       *buffer,
+             A_UINT32       length,
+             A_UINT32       request,
+             void          *context);
+
+/*
+ * This can be initiated from the unload driver context when the OSDRV layer has no more use for
+ * the device.
+ */
+void HIFShutDownDevice(HIF_DEVICE *device);
+
+/*
+ * This should translate to an acknowledgment to the bus driver indicating that
+ * the previous interrupt request has been serviced and the all the relevant
+ * sources have been cleared. HTC is ready to process more interrupts.
+ * This should prevent the bus driver from raising an interrupt unless the
+ * previous one has been serviced and acknowledged using the previous API.
+ */
+void HIFAckInterrupt(HIF_DEVICE *device);
+
+void HIFMaskInterrupt(HIF_DEVICE *device);
+
+void HIFUnMaskInterrupt(HIF_DEVICE *device);
+ 
+#ifdef THREAD_X
+/*
+ * This set of functions are to be used by the bus driver to notify
+ * the HIF module about various events.
+ * These are not implemented if the bus driver provides an alternative
+ * way for this notification though callbacks for instance.
+ */
+int HIFInsertEventNotify(void);
+
+int HIFRemoveEventNotify(void);
+
+int HIFIRQEventNotify(void);
+
+int HIFRWCompleteEventNotify(void);
+#endif
+
+A_STATUS
+HIFConfigureDevice(HIF_DEVICE *device, HIF_DEVICE_CONFIG_OPCODE opcode,
+                   void *config, A_UINT32 configLen);
+
+/* 
+ * This API wait for the remaining MBOX messages to be drained
+ * This should be moved to HTC AR6K layer
+ */
+A_STATUS hifWaitForPendingRecv(HIF_DEVICE *device);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HIF_H_ */
diff --git a/drivers/net/ath6kl/include/host_version.h b/drivers/net/ath6kl/include/host_version.h
new file mode 100644
index 00000000000..74f1982c681
--- /dev/null
+++ b/drivers/net/ath6kl/include/host_version.h
@@ -0,0 +1,52 @@
+//------------------------------------------------------------------------------
+// <copyright file="host_version.h" company="Atheros">
+//    Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// This file contains version information for the sample host driver for the
+// AR6000 chip
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _HOST_VERSION_H_
+#define _HOST_VERSION_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <AR6002/AR6K_version.h>
+
+/*
+ * The version number is made up of major, minor, patch and build
+ * numbers. These are 16 bit numbers.  The build and release script will
+ * set the build number using a Perforce counter.  Here the build number is
+ * set to 9999 so that builds done without the build-release script are easily
+ * identifiable.
+ */
+
+#define ATH_SW_VER_MAJOR      __VER_MAJOR_
+#define ATH_SW_VER_MINOR      __VER_MINOR_
+#define ATH_SW_VER_PATCH      __VER_PATCH_
+#define ATH_SW_VER_BUILD      __BUILD_NUMBER_ 
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HOST_VERSION_H_ */
diff --git a/drivers/net/ath6kl/include/htc_api.h b/drivers/net/ath6kl/include/htc_api.h
new file mode 100644
index 00000000000..b007051e055
--- /dev/null
+++ b/drivers/net/ath6kl/include/htc_api.h
@@ -0,0 +1,575 @@
+//------------------------------------------------------------------------------
+// <copyright file="htc_api.h" company="Atheros">
+//    Copyright (c) 2007-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _HTC_API_H_
+#define _HTC_API_H_
+
+#include "htc_packet.h"
+#include <htc.h>
+#include <htc_services.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* TODO.. for BMI */
+#define ENDPOINT1 0
+// TODO -remove me, but we have to fix BMI first
+#define HTC_MAILBOX_NUM_MAX    4
+
+/* this is the amount of header room required by users of HTC */
+#define HTC_HEADER_LEN         HTC_HDR_LENGTH
+
+typedef void *HTC_HANDLE;
+
+typedef A_UINT16 HTC_SERVICE_ID;
+
+typedef struct _HTC_INIT_INFO {
+    void   *pContext;           /* context for target failure notification */
+    void   (*TargetFailure)(void *Instance, A_STATUS Status);
+} HTC_INIT_INFO;
+
+/* per service connection send completion */
+typedef void   (*HTC_EP_SEND_PKT_COMPLETE)(void *,HTC_PACKET *);
+/* per service connection callback when a plurality of packets have been sent
+ * The HTC_PACKET_QUEUE is a temporary queue object (e.g. freed on return from the callback)
+ * to hold a list of completed send packets.
+ * If the handler cannot fully traverse the packet queue before returning, it should
+ * transfer the items of the queue into the caller's private queue using:
+ *   HTC_PACKET_ENQUEUE() */
+typedef void   (*HTC_EP_SEND_PKT_COMP_MULTIPLE)(void *,HTC_PACKET_QUEUE *);
+/* per service connection pkt received */
+typedef void   (*HTC_EP_RECV_PKT)(void *,HTC_PACKET *);
+/* per service connection callback when a plurality of packets are received
+ * The HTC_PACKET_QUEUE is a temporary queue object (e.g. freed on return from the callback)
+ * to hold a list of recv packets.
+ * If the handler cannot fully traverse the packet queue before returning, it should
+ * transfer the items of the queue into the caller's private queue using:
+ *   HTC_PACKET_ENQUEUE() */
+typedef void   (*HTC_EP_RECV_PKT_MULTIPLE)(void *,HTC_PACKET_QUEUE *);
+
+/* Optional per service connection receive buffer re-fill callback,
+ * On some OSes (like Linux) packets are allocated from a global pool and indicated up
+ * to the network stack.  The driver never gets the packets back from the OS.  For these OSes
+ * a refill callback can be used to allocate and re-queue buffers into HTC.
+ *
+ * On other OSes, the network stack can call into the driver's OS-specifc "return_packet" handler and
+ * the driver can re-queue these buffers into HTC. In this regard a refill callback is
+ * unnecessary */
+typedef void   (*HTC_EP_RECV_REFILL)(void *, HTC_ENDPOINT_ID Endpoint);
+
+/* Optional per service connection receive buffer allocation callback.
+ * On some systems packet buffers are an extremely limited resource.  Rather than
+ * queue largest-possible-sized buffers to HTC, some systems would rather
+ * allocate a specific size as the packet is received.  The trade off is
+ * slightly more processing (callback invoked for each RX packet)
+ * for the benefit of committing fewer buffer resources into HTC.
+ *
+ * The callback is provided the length of the pending packet to fetch. This includes the
+ * HTC header length plus the length of payload.  The callback can return a pointer to
+ * the allocated HTC packet for immediate use.
+ *
+ * Alternatively a variant of this handler can be used to allocate large receive packets as needed.  
+ * For example an application can use the refill mechanism for normal packets and the recv-alloc mechanism to 
+ * handle the case where a large packet buffer is required.  This can significantly reduce the
+ * amount of "committed" memory used to receive packets.
+ *  
+ * */
+typedef HTC_PACKET *(*HTC_EP_RECV_ALLOC)(void *, HTC_ENDPOINT_ID Endpoint, int Length);
+
+typedef enum _HTC_SEND_FULL_ACTION {
+    HTC_SEND_FULL_KEEP = 0,  /* packet that overflowed should be kept in the queue */
+    HTC_SEND_FULL_DROP = 1,  /* packet that overflowed should be dropped */
+} HTC_SEND_FULL_ACTION;
+
+/* Optional per service connection callback when a send queue is full. This can occur if the
+ * host continues queueing up TX packets faster than credits can arrive
+ * To prevent the host (on some Oses like Linux) from continuously queueing packets
+ * and consuming resources, this callback is provided so that that the host
+ * can disable TX in the subsystem (i.e. network stack).
+ * This callback is invoked for each packet that "overflows" the HTC queue. The callback can
+ * determine whether the new packet that overflowed the queue can be kept (HTC_SEND_FULL_KEEP) or
+ * dropped (HTC_SEND_FULL_DROP).  If a packet is dropped, the EpTxComplete handler will be called
+ * and the packet's status field will be set to A_NO_RESOURCE.
+ * Other OSes require a "per-packet" indication for each completed TX packet, this
+ * closed loop mechanism will prevent the network stack from overunning the NIC
+ * The packet to keep or drop is passed for inspection to the registered handler the handler
+ * must ONLY inspect the packet, it may not free or reclaim the packet. */
+typedef HTC_SEND_FULL_ACTION (*HTC_EP_SEND_QUEUE_FULL)(void *, HTC_PACKET *pPacket);
+
+typedef struct _HTC_EP_CALLBACKS {
+    void                     *pContext;     /* context for each callback */
+    HTC_EP_SEND_PKT_COMPLETE EpTxComplete;  /* tx completion callback for connected endpoint */
+    HTC_EP_RECV_PKT          EpRecv;        /* receive callback for connected endpoint */
+    HTC_EP_RECV_REFILL       EpRecvRefill;  /* OPTIONAL receive re-fill callback for connected endpoint */
+    HTC_EP_SEND_QUEUE_FULL   EpSendFull;    /* OPTIONAL send full callback */
+    HTC_EP_RECV_ALLOC        EpRecvAlloc;   /* OPTIONAL recv allocation callback */
+    HTC_EP_RECV_ALLOC        EpRecvAllocThresh;  /* OPTIONAL recv allocation callback based on a threshold */
+    HTC_EP_SEND_PKT_COMP_MULTIPLE EpTxCompleteMultiple; /* OPTIONAL completion handler for multiple complete
+                                                             indications (EpTxComplete must be NULL) */
+    HTC_EP_RECV_PKT_MULTIPLE      EpRecvPktMultiple;      /* OPTIONAL completion handler for multiple
+                                                             recv packet indications (EpRecv must be NULL) */           
+    int                      RecvAllocThreshold;    /* if EpRecvAllocThresh is non-NULL, HTC will compare the 
+                                                       threshold value to the current recv packet length and invoke
+                                                       the EpRecvAllocThresh callback to acquire a packet buffer */
+    int                      RecvRefillWaterMark;   /* if a EpRecvRefill handler is provided, this value
+                                                       can be used to set a trigger refill callback 
+                                                       when the recv queue drops below this value 
+                                                       if set to 0, the refill is only called when packets 
+                                                       are empty */
+} HTC_EP_CALLBACKS;
+
+/* service connection information */
+typedef struct _HTC_SERVICE_CONNECT_REQ {
+    HTC_SERVICE_ID   ServiceID;                 /* service ID to connect to */
+    A_UINT16         ConnectionFlags;           /* connection flags, see htc protocol definition */
+    A_UINT8         *pMetaData;                 /* ptr to optional service-specific meta-data */
+    A_UINT8          MetaDataLength;            /* optional meta data length */
+    HTC_EP_CALLBACKS EpCallbacks;               /* endpoint callbacks */
+    int              MaxSendQueueDepth;         /* maximum depth of any send queue */
+    A_UINT32         LocalConnectionFlags;      /* HTC flags for the host-side (local) connection */
+    unsigned int     MaxSendMsgSize;            /* override max message size in send direction */
+} HTC_SERVICE_CONNECT_REQ;
+
+#define HTC_LOCAL_CONN_FLAGS_ENABLE_SEND_BUNDLE_PADDING (1 << 0)  /* enable send bundle padding for this endpoint */
+
+/* service connection response information */
+typedef struct _HTC_SERVICE_CONNECT_RESP {
+    A_UINT8         *pMetaData;         /* caller supplied buffer to optional meta-data */
+    A_UINT8         BufferLength;       /* length of caller supplied buffer */
+    A_UINT8         ActualLength;       /* actual length of meta data */
+    HTC_ENDPOINT_ID Endpoint;           /* endpoint to communicate over */
+    unsigned int    MaxMsgLength;       /* max length of all messages over this endpoint */
+    A_UINT8         ConnectRespCode;    /* connect response code from target */
+} HTC_SERVICE_CONNECT_RESP;
+
+/* endpoint distribution structure */
+typedef struct _HTC_ENDPOINT_CREDIT_DIST {
+    struct _HTC_ENDPOINT_CREDIT_DIST *pNext;
+    struct _HTC_ENDPOINT_CREDIT_DIST *pPrev;
+    HTC_SERVICE_ID      ServiceID;          /* Service ID (set by HTC) */
+    HTC_ENDPOINT_ID     Endpoint;           /* endpoint for this distribution struct (set by HTC) */
+    A_UINT32            DistFlags;          /* distribution flags, distribution function can
+                                               set default activity using SET_EP_ACTIVE() macro */
+    int                 TxCreditsNorm;      /* credits for normal operation, anything above this
+                                               indicates the endpoint is over-subscribed, this field
+                                               is only relevant to the credit distribution function */
+    int                 TxCreditsMin;       /* floor for credit distribution, this field is
+                                               only relevant to the credit distribution function */
+    int                 TxCreditsAssigned;  /* number of credits assigned to this EP, this field
+                                               is only relevant to the credit dist function */
+    int                 TxCredits;          /* current credits available, this field is used by
+                                               HTC to determine whether a message can be sent or
+                                               must be queued */
+    int                 TxCreditsToDist;    /* pending credits to distribute on this endpoint, this
+                                               is set by HTC when credit reports arrive.
+                                               The credit distribution functions sets this to zero
+                                               when it distributes the credits */
+    int                 TxCreditsSeek;      /* this is the number of credits that the current pending TX
+                                               packet needs to transmit.  This is set by HTC when
+                                               and endpoint needs credits in order to transmit */
+    int                 TxCreditSize;       /* size in bytes of each credit (set by HTC) */
+    int                 TxCreditsPerMaxMsg; /* credits required for a maximum sized messages (set by HTC) */
+    void                *pHTCReserved;      /* reserved for HTC use */    
+    int                 TxQueueDepth;       /* current depth of TX queue , i.e. messages waiting for credits
+                                               This field is valid only when HTC_CREDIT_DIST_ACTIVITY_CHANGE
+                                               or HTC_CREDIT_DIST_SEND_COMPLETE is indicated on an endpoint
+                                               that has non-zero credits to recover
+                                              */
+} HTC_ENDPOINT_CREDIT_DIST;
+
+#define HTC_EP_ACTIVE                            ((A_UINT32) (1u << 31))
+
+/* macro to check if an endpoint has gone active, useful for credit
+ * distributions */
+#define IS_EP_ACTIVE(epDist)  ((epDist)->DistFlags & HTC_EP_ACTIVE)
+#define SET_EP_ACTIVE(epDist) (epDist)->DistFlags |= HTC_EP_ACTIVE
+
+    /* credit distibution code that is passed into the distrbution function,
+     * there are mandatory and optional codes that must be handled */
+typedef enum _HTC_CREDIT_DIST_REASON {
+    HTC_CREDIT_DIST_SEND_COMPLETE = 0,     /* credits available as a result of completed
+                                              send operations (MANDATORY) resulting in credit reports */
+    HTC_CREDIT_DIST_ACTIVITY_CHANGE = 1,   /* a change in endpoint activity occured (OPTIONAL) */
+    HTC_CREDIT_DIST_SEEK_CREDITS,          /* an endpoint needs to "seek" credits (OPTIONAL) */
+    HTC_DUMP_CREDIT_STATE                  /* for debugging, dump any state information that is kept by
+                                              the distribution function */
+} HTC_CREDIT_DIST_REASON;
+
+typedef void (*HTC_CREDIT_DIST_CALLBACK)(void                     *Context,
+                                         HTC_ENDPOINT_CREDIT_DIST *pEPList,
+                                         HTC_CREDIT_DIST_REASON   Reason);
+
+typedef void (*HTC_CREDIT_INIT_CALLBACK)(void *Context,
+                                         HTC_ENDPOINT_CREDIT_DIST *pEPList,
+                                         int                      TotalCredits);
+
+    /* endpoint statistics action */
+typedef enum _HTC_ENDPOINT_STAT_ACTION {
+    HTC_EP_STAT_SAMPLE = 0,                /* only read statistics */
+    HTC_EP_STAT_SAMPLE_AND_CLEAR = 1,      /* sample and immediately clear statistics */
+    HTC_EP_STAT_CLEAR                      /* clear only */
+} HTC_ENDPOINT_STAT_ACTION;
+
+    /* endpoint statistics */
+typedef struct _HTC_ENDPOINT_STATS {
+    A_UINT32  TxCreditLowIndications;  /* number of times the host set the credit-low flag in a send message on
+                                        this endpoint */
+    A_UINT32  TxIssued;               /* running count of total TX packets issued */
+    A_UINT32  TxPacketsBundled;       /* running count of TX packets that were issued in bundles */
+    A_UINT32  TxBundles;              /* running count of TX bundles that were issued */
+    A_UINT32  TxDropped;              /* tx packets that were dropped */
+    A_UINT32  TxCreditRpts;           /* running count of total credit reports received for this endpoint */
+    A_UINT32  TxCreditRptsFromRx;     /* credit reports received from this endpoint's RX packets */
+    A_UINT32  TxCreditRptsFromOther;  /* credit reports received from RX packets of other endpoints */
+    A_UINT32  TxCreditRptsFromEp0;    /* credit reports received from endpoint 0 RX packets */
+    A_UINT32  TxCreditsFromRx;        /* count of credits received via Rx packets on this endpoint */
+    A_UINT32  TxCreditsFromOther;     /* count of credits received via another endpoint */
+    A_UINT32  TxCreditsFromEp0;       /* count of credits received via another endpoint */
+    A_UINT32  TxCreditsConsummed;     /* count of consummed credits */
+    A_UINT32  TxCreditsReturned;      /* count of credits returned */
+    A_UINT32  RxReceived;             /* count of RX packets received */
+    A_UINT32  RxLookAheads;           /* count of lookahead records
+                                         found in messages received on this endpoint */
+    A_UINT32  RxPacketsBundled;       /* count of recv packets received in a bundle */                                     
+    A_UINT32  RxBundleLookAheads;     /* count of number of bundled lookaheads */
+    A_UINT32  RxBundleIndFromHdr;     /* count of the number of bundle indications from the HTC header */
+    A_UINT32  RxAllocThreshHit;       /* count of the number of times the recv allocation threshhold was hit */
+    A_UINT32  RxAllocThreshBytes;     /* total number of bytes */
+} HTC_ENDPOINT_STATS;
+
+/* ------ Function Prototypes ------ */
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+  @desc: Create an instance of HTC over the underlying HIF device
+  @function name: HTCCreate
+  @input:  HifDevice - hif device handle,
+           pInfo - initialization information
+  @output:
+  @return: HTC_HANDLE on success, NULL on failure
+  @notes: 
+  @example:
+  @see also: HTCDestroy
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+HTC_HANDLE HTCCreate(void *HifDevice, HTC_INIT_INFO *pInfo);
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+  @desc: Get the underlying HIF device handle
+  @function name: HTCGetHifDevice
+  @input:  HTCHandle - handle passed into the AddInstance callback
+  @output:
+  @return: opaque HIF device handle usable in HIF API calls.
+  @notes:
+  @example:
+  @see also:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+void       *HTCGetHifDevice(HTC_HANDLE HTCHandle);
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+  @desc: Set credit distribution parameters
+  @function name: HTCSetCreditDistribution
+  @input:  HTCHandle - HTC handle
+           pCreditDistCont - caller supplied context to pass into distribution functions
+           CreditDistFunc - Distribution function callback
+           CreditDistInit - Credit Distribution initialization callback
+           ServicePriorityOrder - Array containing list of service IDs, lowest index is highest
+                                  priority
+           ListLength - number of elements in ServicePriorityOrder
+  @output:
+  @return:
+  @notes:  The user can set a custom credit distribution function to handle special requirements
+           for each endpoint.  A default credit distribution routine can be used by setting
+           CreditInitFunc to NULL.  The default credit distribution is only provided for simple
+           "fair" credit distribution without regard to any prioritization.
+
+  @example:
+  @see also:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+void        HTCSetCreditDistribution(HTC_HANDLE               HTCHandle,
+                                     void                     *pCreditDistContext,
+                                     HTC_CREDIT_DIST_CALLBACK CreditDistFunc,
+                                     HTC_CREDIT_INIT_CALLBACK CreditInitFunc,
+                                     HTC_SERVICE_ID           ServicePriorityOrder[],
+                                     int                      ListLength);
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+  @desc: Wait for the target to indicate the HTC layer is ready
+  @function name: HTCWaitTarget
+  @input:  HTCHandle - HTC handle
+  @output:
+  @return:
+  @notes:  This API blocks until the target responds with an HTC ready message.
+           The caller should not connect services until the target has indicated it is
+           ready.
+  @example:
+  @see also: HTCConnectService
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+A_STATUS    HTCWaitTarget(HTC_HANDLE HTCHandle);
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+  @desc: Start target service communications
+  @function name: HTCStart
+  @input:  HTCHandle - HTC handle
+  @output:
+  @return:
+  @notes: This API indicates to the target that the service connection phase is complete
+          and the target can freely start all connected services.  This API should only be
+          called AFTER all service connections have been made.  TCStart will issue a
+          SETUP_COMPLETE message to the target to indicate that all service connections
+          have been made and the target can start communicating over the endpoints.
+  @example:
+  @see also: HTCConnectService
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+A_STATUS    HTCStart(HTC_HANDLE HTCHandle);
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+  @desc: Add receive packet to HTC
+  @function name: HTCAddReceivePkt
+  @input:  HTCHandle - HTC handle
+           pPacket - HTC receive packet to add
+  @output:
+  @return: A_OK on success
+  @notes:  user must supply HTC packets for capturing incomming HTC frames.  The caller
+           must initialize each HTC packet using the SET_HTC_PACKET_INFO_RX_REFILL()
+           macro.
+  @example:
+  @see also:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+A_STATUS    HTCAddReceivePkt(HTC_HANDLE HTCHandle, HTC_PACKET *pPacket);
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+  @desc: Connect to an HTC service
+  @function name: HTCConnectService
+  @input:  HTCHandle - HTC handle
+           pReq - connection details
+  @output: pResp - connection response
+  @return:
+  @notes:  Service connections must be performed before HTCStart.  User provides callback handlers
+           for various endpoint events.
+  @example:
+  @see also: HTCStart
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+A_STATUS    HTCConnectService(HTC_HANDLE HTCHandle,
+                              HTC_SERVICE_CONNECT_REQ  *pReq,
+                              HTC_SERVICE_CONNECT_RESP *pResp);
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+  @desc: Send an HTC packet
+  @function name: HTCSendPkt
+  @input:  HTCHandle - HTC handle
+           pPacket - packet to send
+  @output:
+  @return: A_OK
+  @notes:  Caller must initialize packet using SET_HTC_PACKET_INFO_TX() macro.
+           This interface is fully asynchronous.  On error, HTC SendPkt will
+           call the registered Endpoint callback to cleanup the packet.
+  @example:
+  @see also: HTCFlushEndpoint
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+A_STATUS    HTCSendPkt(HTC_HANDLE HTCHandle, HTC_PACKET *pPacket);
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+  @desc: Stop HTC service communications
+  @function name: HTCStop
+  @input:  HTCHandle - HTC handle
+  @output:
+  @return:
+  @notes: HTC communications is halted.  All receive and pending TX packets will
+          be flushed.
+  @example:
+  @see also:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+void        HTCStop(HTC_HANDLE HTCHandle);
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+  @desc: Destory HTC service
+  @function name: HTCDestroy
+  @input: HTCHandle 
+  @output:
+  @return:
+  @notes:  This cleans up all resources allocated by HTCCreate().
+  @example:
+  @see also: HTCCreate
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+void        HTCDestroy(HTC_HANDLE HTCHandle);
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+  @desc: Flush pending TX packets
+  @function name: HTCFlushEndpoint
+  @input:  HTCHandle - HTC handle
+           Endpoint - Endpoint to flush
+           Tag - flush tag
+  @output:
+  @return:
+  @notes:  The Tag parameter is used to selectively flush packets with matching tags.
+           The value of 0 forces all packets to be flush regardless of tag.
+  @example:
+  @see also: HTCSendPkt
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+void        HTCFlushEndpoint(HTC_HANDLE HTCHandle, HTC_ENDPOINT_ID Endpoint, HTC_TX_TAG Tag);
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+  @desc: Dump credit distribution state
+  @function name: HTCDumpCreditStates
+  @input:  HTCHandle - HTC handle
+  @output:
+  @return:
+  @notes:  This dumps all credit distribution information to the debugger
+  @example:
+  @see also:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+void        HTCDumpCreditStates(HTC_HANDLE HTCHandle);
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+  @desc: Indicate a traffic activity change on an endpoint
+  @function name: HTCIndicateActivityChange
+  @input:  HTCHandle - HTC handle
+           Endpoint - endpoint in which activity has changed
+           Active - TRUE if active, FALSE if it has become inactive
+  @output:
+  @return:
+  @notes:  This triggers the registered credit distribution function to
+           re-adjust credits for active/inactive endpoints.
+  @example:
+  @see also:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+void        HTCIndicateActivityChange(HTC_HANDLE      HTCHandle,
+                                      HTC_ENDPOINT_ID Endpoint,
+                                      A_BOOL          Active);
+
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+  @desc: Get endpoint statistics
+  @function name: HTCGetEndpointStatistics
+  @input:  HTCHandle - HTC handle
+           Endpoint - Endpoint identifier
+           Action - action to take with statistics
+  @output:
+           pStats - statistics that were sampled (can be NULL if Action is HTC_EP_STAT_CLEAR)
+
+  @return: TRUE if statistics profiling is enabled, otherwise FALSE.
+
+  @notes:  Statistics is a compile-time option and this function may return FALSE
+           if HTC is not compiled with profiling.
+
+           The caller can specify the statistic "action" to take when sampling
+           the statistics.  This includes:
+
+           HTC_EP_STAT_SAMPLE: The pStats structure is filled with the current values.
+           HTC_EP_STAT_SAMPLE_AND_CLEAR: The structure is filled and the current statistics
+                             are cleared.
+           HTC_EP_STAT_CLEA : the statistics are cleared, the called can pass a NULL value for
+                   pStats
+
+  @example:
+  @see also:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+A_BOOL       HTCGetEndpointStatistics(HTC_HANDLE               HTCHandle,
+                                      HTC_ENDPOINT_ID          Endpoint,
+                                      HTC_ENDPOINT_STAT_ACTION Action,
+                                      HTC_ENDPOINT_STATS       *pStats);
+
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+  @desc: Unblock HTC message reception
+  @function name: HTCUnblockRecv
+  @input:  HTCHandle - HTC handle
+  @output:
+  @return:
+  @notes:
+           HTC will block the receiver if the EpRecvAlloc callback fails to provide a packet.
+           The caller can use this API to indicate to HTC when resources (buffers) are available
+           such that the  receiver can be unblocked and HTC may re-attempt fetching the pending message.
+
+           This API is not required if the user uses the EpRecvRefill callback or uses the HTCAddReceivePacket()
+           API to recycle or provide receive packets to HTC.
+
+  @example:
+  @see also:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+void HTCUnblockRecv(HTC_HANDLE HTCHandle);
+
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+  @desc: send a series of HTC packets  
+  @function name: HTCSendPktsMultiple
+  @input:  HTCHandle - HTC handle
+           pPktQueue - local queue holding packets to send
+  @output:
+  @return: A_OK
+  @notes:  Caller must initialize each packet using SET_HTC_PACKET_INFO_TX() macro.
+           The queue must only contain packets directed at the same endpoint.
+           Caller supplies a pointer to an HTC_PACKET_QUEUE structure holding the TX packets in FIFO order.
+           This API will remove the packets from the pkt queue and place them into the HTC Tx Queue
+           and bundle messages where possible.
+           The caller may allocate the pkt queue on the stack to hold the packets.           
+           This interface is fully asynchronous.  On error, HTCSendPkts will
+           call the registered Endpoint callback to cleanup the packet.
+  @example:
+  @see also: HTCFlushEndpoint
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+A_STATUS    HTCSendPktsMultiple(HTC_HANDLE HTCHandle, HTC_PACKET_QUEUE *pPktQueue);
+
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+  @desc: Add multiple receive packets to HTC
+  @function name: HTCAddReceivePktMultiple
+  @input:  HTCHandle - HTC handle
+           pPktQueue - HTC receive packet queue holding packets to add
+  @output:
+  @return: A_OK on success
+  @notes:  user must supply HTC packets for capturing incomming HTC frames.  The caller
+           must initialize each HTC packet using the SET_HTC_PACKET_INFO_RX_REFILL()
+           macro. The queue must only contain recv packets for the same endpoint.
+           Caller supplies a pointer to an HTC_PACKET_QUEUE structure holding the recv packet.
+           This API will remove the packets from the pkt queue and place them into internal
+           recv packet list.
+           The caller may allocate the pkt queue on the stack to hold the packets.           
+  @example:
+  @see also:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+A_STATUS    HTCAddReceivePktMultiple(HTC_HANDLE HTCHandle, HTC_PACKET_QUEUE *pPktQueue);
+
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+  @desc: Check if an endpoint is marked active
+  @function name: HTCIsEndpointActive
+  @input:  HTCHandle - HTC handle
+           Endpoint - endpoint to check for active state
+  @output:
+  @return: returns TRUE if Endpoint is Active
+  @notes:  
+  @example:
+  @see also:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+A_BOOL      HTCIsEndpointActive(HTC_HANDLE      HTCHandle,
+                                HTC_ENDPOINT_ID Endpoint);
+
+
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+  @desc: Get the number of recv buffers currently queued into an HTC endpoint
+  @function name: HTCGetNumRecvBuffers
+  @input:  HTCHandle - HTC handle
+           Endpoint - endpoint to check
+  @output:
+  @return: returns number of buffers in queue
+  @notes:  
+  @example:
+  @see also:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+int         HTCGetNumRecvBuffers(HTC_HANDLE      HTCHandle,
+                                 HTC_ENDPOINT_ID Endpoint);
+                                                                      
+/* internally used functions for testing... */
+void HTCEnableRecv(HTC_HANDLE HTCHandle);
+void HTCDisableRecv(HTC_HANDLE HTCHandle);
+A_STATUS HTCWaitForPendingRecv(HTC_HANDLE   HTCHandle,
+                               A_UINT32     TimeoutInMs,
+                               A_BOOL      *pbIsRecvPending);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HTC_API_H_ */
diff --git a/drivers/net/ath6kl/include/htc_packet.h b/drivers/net/ath6kl/include/htc_packet.h
new file mode 100644
index 00000000000..15175cff2f2
--- /dev/null
+++ b/drivers/net/ath6kl/include/htc_packet.h
@@ -0,0 +1,227 @@
+//------------------------------------------------------------------------------
+// <copyright file="htc_packet.h" company="Atheros">
+//    Copyright (c) 2007-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef HTC_PACKET_H_
+#define HTC_PACKET_H_
+
+
+#include "dl_list.h"
+
+/* ------ Endpoint IDS ------ */
+typedef enum
+{
+    ENDPOINT_UNUSED = -1,
+    ENDPOINT_0 = 0,
+    ENDPOINT_1 = 1,
+    ENDPOINT_2 = 2,
+    ENDPOINT_3,
+    ENDPOINT_4,
+    ENDPOINT_5,
+    ENDPOINT_6,
+    ENDPOINT_7,
+    ENDPOINT_8,
+    ENDPOINT_MAX,
+} HTC_ENDPOINT_ID;
+
+struct _HTC_PACKET;
+
+typedef void (* HTC_PACKET_COMPLETION)(void *,struct _HTC_PACKET *);
+
+typedef A_UINT16 HTC_TX_TAG;
+
+typedef struct _HTC_TX_PACKET_INFO {
+    HTC_TX_TAG    Tag;            /* tag used to selective flush packets */
+    int           CreditsUsed;    /* number of credits used for this TX packet (HTC internal) */
+    A_UINT8       SendFlags;      /* send flags (HTC internal) */
+    int           SeqNo;          /* internal seq no for debugging (HTC internal) */
+} HTC_TX_PACKET_INFO;
+
+#define HTC_TX_PACKET_TAG_ALL          0    /* a tag of zero is reserved and used to flush ALL packets */
+#define HTC_TX_PACKET_TAG_INTERNAL     1                                /* internal tags start here */
+#define HTC_TX_PACKET_TAG_USER_DEFINED (HTC_TX_PACKET_TAG_INTERNAL + 9) /* user-defined tags start here */
+
+typedef struct _HTC_RX_PACKET_INFO {
+    A_UINT32    ExpectedHdr;        /* HTC internal use */
+    A_UINT32    HTCRxFlags;         /* HTC internal use */
+    A_UINT32    IndicationFlags;    /* indication flags set on each RX packet indication */
+} HTC_RX_PACKET_INFO;
+
+#define HTC_RX_FLAGS_INDICATE_MORE_PKTS  (1 << 0)   /* more packets on this endpoint are being fetched */
+
+/* wrapper around endpoint-specific packets */
+typedef struct _HTC_PACKET {
+    DL_LIST         ListLink;       /* double link */
+    void            *pPktContext;   /* caller's per packet specific context */
+
+    A_UINT8         *pBufferStart;  /* the true buffer start , the caller can
+                                       store the real buffer start here.  In
+                                       receive callbacks, the HTC layer sets pBuffer
+                                       to the start of the payload past the header. This
+                                       field allows the caller to reset pBuffer when it
+                                       recycles receive packets back to HTC */
+    /*
+     * Pointer to the start of the buffer. In the transmit
+     * direction this points to the start of the payload. In the
+     * receive direction, however, the buffer when queued up
+     * points to the start of the HTC header but when returned
+     * to the caller points to the start of the payload
+     */
+    A_UINT8         *pBuffer;       /* payload start (RX/TX) */
+    A_UINT32        BufferLength;   /* length of buffer */
+    A_UINT32        ActualLength;   /* actual length of payload */
+    HTC_ENDPOINT_ID Endpoint;       /* endpoint that this packet was sent/recv'd from */
+    A_STATUS        Status;         /* completion status */
+    union {
+        HTC_TX_PACKET_INFO  AsTx;   /* Tx Packet specific info */
+        HTC_RX_PACKET_INFO  AsRx;   /* Rx Packet specific info */
+    } PktInfo;
+
+    /* the following fields are for internal HTC use */
+    HTC_PACKET_COMPLETION Completion;   /* completion */
+    void                  *pContext;    /* HTC private completion context */
+} HTC_PACKET;
+
+
+
+#define COMPLETE_HTC_PACKET(p,status)        \
+{                                            \
+    (p)->Status = (status);                  \
+    (p)->Completion((p)->pContext,(p));      \
+}
+
+#define INIT_HTC_PACKET_INFO(p,b,len)             \
+{                                                 \
+    (p)->pBufferStart = (b);                      \
+    (p)->BufferLength = (len);                    \
+}
+
+/* macro to set an initial RX packet for refilling HTC */
+#define SET_HTC_PACKET_INFO_RX_REFILL(p,c,b,len,ep) \
+{                                                 \
+    (p)->pPktContext = (c);                       \
+    (p)->pBuffer = (b);                           \
+    (p)->pBufferStart = (b);                      \
+    (p)->BufferLength = (len);                    \
+    (p)->Endpoint = (ep);                         \
+}
+
+/* fast macro to recycle an RX packet that will be re-queued to HTC */
+#define HTC_PACKET_RESET_RX(p)              \
+    { (p)->pBuffer = (p)->pBufferStart; (p)->ActualLength = 0; }  
+
+/* macro to set packet parameters for TX */
+#define SET_HTC_PACKET_INFO_TX(p,c,b,len,ep,tag)  \
+{                                                 \
+    (p)->pPktContext = (c);                       \
+    (p)->pBuffer = (b);                           \
+    (p)->ActualLength = (len);                    \
+    (p)->Endpoint = (ep);                         \
+    (p)->PktInfo.AsTx.Tag = (tag);                \
+}
+
+/* HTC Packet Queueing Macros */
+typedef struct _HTC_PACKET_QUEUE {
+    DL_LIST     QueueHead;
+    int         Depth;    
+} HTC_PACKET_QUEUE;
+ 
+/* initialize queue */
+#define INIT_HTC_PACKET_QUEUE(pQ)   \
+{                                   \
+    DL_LIST_INIT(&(pQ)->QueueHead); \
+    (pQ)->Depth = 0;                \
+}
+
+/* enqueue HTC packet to the tail of the queue */
+#define HTC_PACKET_ENQUEUE(pQ,p)                        \
+{   DL_ListInsertTail(&(pQ)->QueueHead,&(p)->ListLink); \
+    (pQ)->Depth++;                                      \
+}
+
+/* enqueue HTC packet to the tail of the queue */
+#define HTC_PACKET_ENQUEUE_TO_HEAD(pQ,p)                \
+{   DL_ListInsertHead(&(pQ)->QueueHead,&(p)->ListLink); \
+    (pQ)->Depth++;                                      \
+}
+/* test if a queue is empty */
+#define HTC_QUEUE_EMPTY(pQ)       ((pQ)->Depth == 0)
+/* get packet at head without removing it */
+static INLINE HTC_PACKET *HTC_GET_PKT_AT_HEAD(HTC_PACKET_QUEUE *queue)   {
+    if (queue->Depth == 0) {
+        return NULL; 
+    }  
+    return A_CONTAINING_STRUCT((DL_LIST_GET_ITEM_AT_HEAD(&queue->QueueHead)),HTC_PACKET,ListLink);
+}
+/* remove a packet from a queue, where-ever it is in the queue */
+#define HTC_PACKET_REMOVE(pQ,p)     \
+{                                   \
+    DL_ListRemove(&(p)->ListLink);  \
+    (pQ)->Depth--;                  \
+}
+
+/* dequeue an HTC packet from the head of the queue */
+static INLINE HTC_PACKET *HTC_PACKET_DEQUEUE(HTC_PACKET_QUEUE *queue) {
+    DL_LIST    *pItem = DL_ListRemoveItemFromHead(&queue->QueueHead);
+    if (pItem != NULL) {
+        queue->Depth--;
+        return A_CONTAINING_STRUCT(pItem, HTC_PACKET, ListLink);
+    }
+    return NULL;
+}
+
+/* dequeue an HTC packet from the tail of the queue */
+static INLINE HTC_PACKET *HTC_PACKET_DEQUEUE_TAIL(HTC_PACKET_QUEUE *queue) {
+    DL_LIST    *pItem = DL_ListRemoveItemFromTail(&queue->QueueHead);
+    if (pItem != NULL) {
+        queue->Depth--;
+        return A_CONTAINING_STRUCT(pItem, HTC_PACKET, ListLink);
+    }
+    return NULL;
+}
+
+#define HTC_PACKET_QUEUE_DEPTH(pQ) (pQ)->Depth
+
+
+#define HTC_GET_ENDPOINT_FROM_PKT(p) (p)->Endpoint
+#define HTC_GET_TAG_FROM_PKT(p)      (p)->PktInfo.AsTx.Tag
+
+    /* transfer the packets from one queue to the tail of another queue */
+#define HTC_PACKET_QUEUE_TRANSFER_TO_TAIL(pQDest,pQSrc) \
+{                                                                           \
+    DL_ListTransferItemsToTail(&(pQDest)->QueueHead,&(pQSrc)->QueueHead);   \
+    (pQDest)->Depth += (pQSrc)->Depth;                                      \
+    (pQSrc)->Depth = 0;                                                     \
+}
+
+    /* fast version to init and add a single packet to a queue */
+#define INIT_HTC_PACKET_QUEUE_AND_ADD(pQ,pP) \
+{                                            \
+    DL_LIST_INIT_AND_ADD(&(pQ)->QueueHead,&(pP)->ListLink)  \
+    (pQ)->Depth = 1;                                        \
+}
+    
+#define HTC_PACKET_QUEUE_ITERATE_ALLOW_REMOVE(pQ, pPTemp) \
+    ITERATE_OVER_LIST_ALLOW_REMOVE(&(pQ)->QueueHead,(pPTemp), HTC_PACKET, ListLink) 
+
+#define HTC_PACKET_QUEUE_ITERATE_END ITERATE_END
+        
+#endif /*HTC_PACKET_H_*/
diff --git a/drivers/net/ath6kl/include/target_reg_table.h b/drivers/net/ath6kl/include/target_reg_table.h
new file mode 100644
index 00000000000..901f923bee3
--- /dev/null
+++ b/drivers/net/ath6kl/include/target_reg_table.h
@@ -0,0 +1,244 @@
+//------------------------------------------------------------------------------
+// <copyright file="target_reg_table.h" company="Atheros">
+//    Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Target register table macros and structure definitions
+//
+// Author(s): ="Atheros"
+//==============================================================================
+
+#ifndef TARGET_REG_TABLE_H_
+#define TARGET_REG_TABLE_H_
+
+#include "targaddrs.h"
+
+/*** WARNING : Add to the end of the TABLE! do not change the order ****/
+typedef struct targetdef_s {
+    A_UINT32 d_RTC_BASE_ADDRESS;
+    A_UINT32 d_SYSTEM_SLEEP_OFFSET;
+    A_UINT32 d_SYSTEM_SLEEP_DISABLE_LSB;
+    A_UINT32 d_SYSTEM_SLEEP_DISABLE_MASK;
+    A_UINT32 d_CLOCK_CONTROL_OFFSET;
+    A_UINT32 d_CLOCK_CONTROL_SI0_CLK_MASK;
+    A_UINT32 d_RESET_CONTROL_OFFSET;
+    A_UINT32 d_RESET_CONTROL_SI0_RST_MASK;
+    A_UINT32 d_GPIO_BASE_ADDRESS;
+    A_UINT32 d_GPIO_PIN0_OFFSET;
+    A_UINT32 d_GPIO_PIN1_OFFSET;
+    A_UINT32 d_GPIO_PIN0_CONFIG_MASK;
+    A_UINT32 d_GPIO_PIN1_CONFIG_MASK;
+    A_UINT32 d_SI_CONFIG_BIDIR_OD_DATA_LSB;
+    A_UINT32 d_SI_CONFIG_BIDIR_OD_DATA_MASK;
+    A_UINT32 d_SI_CONFIG_I2C_LSB;
+    A_UINT32 d_SI_CONFIG_I2C_MASK;
+    A_UINT32 d_SI_CONFIG_POS_SAMPLE_LSB;
+    A_UINT32 d_SI_CONFIG_POS_SAMPLE_MASK;
+    A_UINT32 d_SI_CONFIG_INACTIVE_CLK_LSB;
+    A_UINT32 d_SI_CONFIG_INACTIVE_CLK_MASK;
+    A_UINT32 d_SI_CONFIG_INACTIVE_DATA_LSB;
+    A_UINT32 d_SI_CONFIG_INACTIVE_DATA_MASK;
+    A_UINT32 d_SI_CONFIG_DIVIDER_LSB;
+    A_UINT32 d_SI_CONFIG_DIVIDER_MASK;
+    A_UINT32 d_SI_BASE_ADDRESS;
+    A_UINT32 d_SI_CONFIG_OFFSET;
+    A_UINT32 d_SI_TX_DATA0_OFFSET;
+    A_UINT32 d_SI_TX_DATA1_OFFSET;
+    A_UINT32 d_SI_RX_DATA0_OFFSET;
+    A_UINT32 d_SI_RX_DATA1_OFFSET;
+    A_UINT32 d_SI_CS_OFFSET;
+    A_UINT32 d_SI_CS_DONE_ERR_MASK;
+    A_UINT32 d_SI_CS_DONE_INT_MASK;
+    A_UINT32 d_SI_CS_START_LSB;
+    A_UINT32 d_SI_CS_START_MASK;
+    A_UINT32 d_SI_CS_RX_CNT_LSB;
+    A_UINT32 d_SI_CS_RX_CNT_MASK;
+    A_UINT32 d_SI_CS_TX_CNT_LSB;
+    A_UINT32 d_SI_CS_TX_CNT_MASK;
+    A_UINT32 d_BOARD_DATA_SZ;
+    A_UINT32 d_BOARD_EXT_DATA_SZ;
+} TARGET_REGISTER_TABLE;
+
+#define BOARD_DATA_SZ_MAX 2048
+
+#if defined(MY_TARGET_DEF) /* { */
+
+#ifdef ATH_REG_TABLE_DIRECT_ASSIGN
+
+static struct targetdef_s my_target_def = {
+    RTC_BASE_ADDRESS,
+    SYSTEM_SLEEP_OFFSET,
+    SYSTEM_SLEEP_DISABLE_LSB,
+    SYSTEM_SLEEP_DISABLE_MASK,
+    CLOCK_CONTROL_OFFSET,
+    CLOCK_CONTROL_SI0_CLK_MASK,
+    RESET_CONTROL_OFFSET,
+    RESET_CONTROL_SI0_RST_MASK,
+    GPIO_BASE_ADDRESS,
+    GPIO_PIN0_OFFSET,
+    GPIO_PIN0_CONFIG_MASK,
+    GPIO_PIN1_OFFSET,
+    GPIO_PIN1_CONFIG_MASK,
+    SI_CONFIG_BIDIR_OD_DATA_LSB,
+    SI_CONFIG_BIDIR_OD_DATA_MASK,
+    SI_CONFIG_I2C_LSB,
+    SI_CONFIG_I2C_MASK,
+    SI_CONFIG_POS_SAMPLE_LSB,
+    SI_CONFIG_POS_SAMPLE_MASK,
+    SI_CONFIG_INACTIVE_CLK_LSB,
+    SI_CONFIG_INACTIVE_CLK_MASK,
+    SI_CONFIG_INACTIVE_DATA_LSB,
+    SI_CONFIG_INACTIVE_DATA_MASK,
+    SI_CONFIG_DIVIDER_LSB,
+    SI_CONFIG_DIVIDER_MASK,
+    SI_BASE_ADDRESS,
+    SI_CONFIG_OFFSET,
+    SI_TX_DATA0_OFFSET,
+    SI_TX_DATA1_OFFSET,
+    SI_RX_DATA0_OFFSET,
+    SI_RX_DATA1_OFFSET,
+    SI_CS_OFFSET,
+    SI_CS_DONE_ERR_MASK,
+    SI_CS_DONE_INT_MASK,
+    SI_CS_START_LSB,
+    SI_CS_START_MASK,
+    SI_CS_RX_CNT_LSB,
+    SI_CS_RX_CNT_MASK,
+    SI_CS_TX_CNT_LSB,
+    SI_CS_TX_CNT_MASK,
+    MY_TARGET_BOARD_DATA_SZ,
+    MY_TARGET_BOARD_EXT_DATA_SZ,
+};
+
+#else
+
+static struct targetdef_s my_target_def = {
+    .d_RTC_BASE_ADDRESS = RTC_BASE_ADDRESS,
+    .d_SYSTEM_SLEEP_OFFSET = SYSTEM_SLEEP_OFFSET,
+    .d_SYSTEM_SLEEP_DISABLE_LSB = SYSTEM_SLEEP_DISABLE_LSB,
+    .d_SYSTEM_SLEEP_DISABLE_MASK = SYSTEM_SLEEP_DISABLE_MASK,
+    .d_CLOCK_CONTROL_OFFSET = CLOCK_CONTROL_OFFSET,
+    .d_CLOCK_CONTROL_SI0_CLK_MASK = CLOCK_CONTROL_SI0_CLK_MASK,
+    .d_RESET_CONTROL_OFFSET = RESET_CONTROL_OFFSET,
+    .d_RESET_CONTROL_SI0_RST_MASK = RESET_CONTROL_SI0_RST_MASK,
+    .d_GPIO_BASE_ADDRESS = GPIO_BASE_ADDRESS,
+    .d_GPIO_PIN0_OFFSET = GPIO_PIN0_OFFSET,
+    .d_GPIO_PIN0_CONFIG_MASK = GPIO_PIN0_CONFIG_MASK,
+    .d_GPIO_PIN1_OFFSET = GPIO_PIN1_OFFSET,
+    .d_GPIO_PIN1_CONFIG_MASK = GPIO_PIN1_CONFIG_MASK,
+    .d_SI_CONFIG_BIDIR_OD_DATA_LSB = SI_CONFIG_BIDIR_OD_DATA_LSB,
+    .d_SI_CONFIG_BIDIR_OD_DATA_MASK = SI_CONFIG_BIDIR_OD_DATA_MASK,
+    .d_SI_CONFIG_I2C_LSB = SI_CONFIG_I2C_LSB,
+    .d_SI_CONFIG_I2C_MASK = SI_CONFIG_I2C_MASK,
+    .d_SI_CONFIG_POS_SAMPLE_LSB = SI_CONFIG_POS_SAMPLE_LSB,
+    .d_SI_CONFIG_POS_SAMPLE_MASK = SI_CONFIG_POS_SAMPLE_MASK,
+    .d_SI_CONFIG_INACTIVE_CLK_LSB = SI_CONFIG_INACTIVE_CLK_LSB,
+    .d_SI_CONFIG_INACTIVE_CLK_MASK = SI_CONFIG_INACTIVE_CLK_MASK,
+    .d_SI_CONFIG_INACTIVE_DATA_LSB = SI_CONFIG_INACTIVE_DATA_LSB,
+    .d_SI_CONFIG_INACTIVE_DATA_MASK = SI_CONFIG_INACTIVE_DATA_MASK,
+    .d_SI_CONFIG_DIVIDER_LSB = SI_CONFIG_DIVIDER_LSB,
+    .d_SI_CONFIG_DIVIDER_MASK = SI_CONFIG_DIVIDER_MASK,
+    .d_SI_BASE_ADDRESS = SI_BASE_ADDRESS,
+    .d_SI_CONFIG_OFFSET = SI_CONFIG_OFFSET,
+    .d_SI_TX_DATA0_OFFSET = SI_TX_DATA0_OFFSET,
+    .d_SI_TX_DATA1_OFFSET = SI_TX_DATA1_OFFSET,
+    .d_SI_RX_DATA0_OFFSET = SI_RX_DATA0_OFFSET,
+    .d_SI_RX_DATA1_OFFSET = SI_RX_DATA1_OFFSET,
+    .d_SI_CS_OFFSET = SI_CS_OFFSET,
+    .d_SI_CS_DONE_ERR_MASK = SI_CS_DONE_ERR_MASK,
+    .d_SI_CS_DONE_INT_MASK = SI_CS_DONE_INT_MASK,
+    .d_SI_CS_START_LSB = SI_CS_START_LSB,
+    .d_SI_CS_START_MASK = SI_CS_START_MASK,
+    .d_SI_CS_RX_CNT_LSB = SI_CS_RX_CNT_LSB,
+    .d_SI_CS_RX_CNT_MASK = SI_CS_RX_CNT_MASK,
+    .d_SI_CS_TX_CNT_LSB = SI_CS_TX_CNT_LSB,
+    .d_SI_CS_TX_CNT_MASK = SI_CS_TX_CNT_MASK,
+    .d_BOARD_DATA_SZ = MY_TARGET_BOARD_DATA_SZ,
+    .d_BOARD_EXT_DATA_SZ = MY_TARGET_BOARD_EXT_DATA_SZ,
+};
+
+#endif
+
+#if MY_TARGET_BOARD_DATA_SZ > BOARD_DATA_SZ_MAX
+#error "BOARD_DATA_SZ_MAX is too small"
+#endif
+
+struct targetdef_s *MY_TARGET_DEF = &my_target_def;
+
+#else /* } { */
+
+#define RTC_BASE_ADDRESS (targetdef->d_RTC_BASE_ADDRESS)
+#define SYSTEM_SLEEP_OFFSET (targetdef->d_SYSTEM_SLEEP_OFFSET)
+#define SYSTEM_SLEEP_DISABLE_LSB (targetdef->d_SYSTEM_SLEEP_DISABLE_LSB)
+#define SYSTEM_SLEEP_DISABLE_MASK (targetdef->d_SYSTEM_SLEEP_DISABLE_MASK)
+#define CLOCK_CONTROL_OFFSET (targetdef->d_CLOCK_CONTROL_OFFSET)
+#define CLOCK_CONTROL_SI0_CLK_MASK (targetdef->d_CLOCK_CONTROL_SI0_CLK_MASK)
+#define RESET_CONTROL_OFFSET (targetdef->d_RESET_CONTROL_OFFSET)
+#define RESET_CONTROL_SI0_RST_MASK (targetdef->d_RESET_CONTROL_SI0_RST_MASK)
+#define GPIO_BASE_ADDRESS (targetdef->d_GPIO_BASE_ADDRESS)
+#define GPIO_PIN0_OFFSET (targetdef->d_GPIO_PIN0_OFFSET)
+#define GPIO_PIN0_CONFIG_MASK (targetdef->d_GPIO_PIN0_CONFIG_MASK)
+#define GPIO_PIN1_OFFSET (targetdef->d_GPIO_PIN1_OFFSET)
+#define GPIO_PIN1_CONFIG_MASK (targetdef->d_GPIO_PIN1_CONFIG_MASK)
+#define SI_CONFIG_BIDIR_OD_DATA_LSB (targetdef->d_SI_CONFIG_BIDIR_OD_DATA_LSB)
+#define SI_CONFIG_BIDIR_OD_DATA_MASK (targetdef->d_SI_CONFIG_BIDIR_OD_DATA_MASK)
+#define SI_CONFIG_I2C_LSB (targetdef->d_SI_CONFIG_I2C_LSB)
+#define SI_CONFIG_I2C_MASK (targetdef->d_SI_CONFIG_I2C_MASK)
+#define SI_CONFIG_POS_SAMPLE_LSB (targetdef->d_SI_CONFIG_POS_SAMPLE_LSB)
+#define SI_CONFIG_POS_SAMPLE_MASK (targetdef->d_SI_CONFIG_POS_SAMPLE_MASK)
+#define SI_CONFIG_INACTIVE_CLK_LSB (targetdef->d_SI_CONFIG_INACTIVE_CLK_LSB)
+#define SI_CONFIG_INACTIVE_CLK_MASK (targetdef->d_SI_CONFIG_INACTIVE_CLK_MASK)
+#define SI_CONFIG_INACTIVE_DATA_LSB (targetdef->d_SI_CONFIG_INACTIVE_DATA_LSB)
+#define SI_CONFIG_INACTIVE_DATA_MASK (targetdef->d_SI_CONFIG_INACTIVE_DATA_MASK)
+#define SI_CONFIG_DIVIDER_LSB (targetdef->d_SI_CONFIG_DIVIDER_LSB)
+#define SI_CONFIG_DIVIDER_MASK (targetdef->d_SI_CONFIG_DIVIDER_MASK)
+#define SI_BASE_ADDRESS (targetdef->d_SI_BASE_ADDRESS)
+#define SI_CONFIG_OFFSET (targetdef->d_SI_CONFIG_OFFSET)
+#define SI_TX_DATA0_OFFSET (targetdef->d_SI_TX_DATA0_OFFSET)
+#define SI_TX_DATA1_OFFSET (targetdef->d_SI_TX_DATA1_OFFSET)
+#define SI_RX_DATA0_OFFSET (targetdef->d_SI_RX_DATA0_OFFSET)
+#define SI_RX_DATA1_OFFSET (targetdef->d_SI_RX_DATA1_OFFSET)
+#define SI_CS_OFFSET (targetdef->d_SI_CS_OFFSET)
+#define SI_CS_DONE_ERR_MASK (targetdef->d_SI_CS_DONE_ERR_MASK)
+#define SI_CS_DONE_INT_MASK (targetdef->d_SI_CS_DONE_INT_MASK)
+#define SI_CS_START_LSB (targetdef->d_SI_CS_START_LSB)
+#define SI_CS_START_MASK (targetdef->d_SI_CS_START_MASK)
+#define SI_CS_RX_CNT_LSB (targetdef->d_SI_CS_RX_CNT_LSB)
+#define SI_CS_RX_CNT_MASK (targetdef->d_SI_CS_RX_CNT_MASK)
+#define SI_CS_TX_CNT_LSB (targetdef->d_SI_CS_TX_CNT_LSB)
+#define SI_CS_TX_CNT_MASK (targetdef->d_SI_CS_TX_CNT_MASK)
+#define EEPROM_SZ (targetdef->d_BOARD_DATA_SZ)
+#define EEPROM_EXT_SZ (targetdef->d_BOARD_EXT_DATA_SZ)
+
+/* SET macros */
+#define SYSTEM_SLEEP_DISABLE_SET(x)              (((x) << SYSTEM_SLEEP_DISABLE_LSB) & SYSTEM_SLEEP_DISABLE_MASK)
+#define SI_CONFIG_BIDIR_OD_DATA_SET(x) (((x) << SI_CONFIG_BIDIR_OD_DATA_LSB) & SI_CONFIG_BIDIR_OD_DATA_MASK)
+#define SI_CONFIG_I2C_SET(x) (((x) << SI_CONFIG_I2C_LSB) & SI_CONFIG_I2C_MASK)
+#define SI_CONFIG_POS_SAMPLE_SET(x) (((x) << SI_CONFIG_POS_SAMPLE_LSB) & SI_CONFIG_POS_SAMPLE_MASK)
+#define SI_CONFIG_INACTIVE_CLK_SET(x) (((x) << SI_CONFIG_INACTIVE_CLK_LSB) & SI_CONFIG_INACTIVE_CLK_MASK)
+#define SI_CONFIG_INACTIVE_DATA_SET(x) (((x) << SI_CONFIG_INACTIVE_DATA_LSB) & SI_CONFIG_INACTIVE_DATA_MASK)
+#define SI_CONFIG_DIVIDER_SET(x) (((x) << SI_CONFIG_DIVIDER_LSB) & SI_CONFIG_DIVIDER_MASK)
+#define SI_CS_START_SET(x) (((x) << SI_CS_START_LSB) & SI_CS_START_MASK)
+#define SI_CS_RX_CNT_SET(x) (((x) << SI_CS_RX_CNT_LSB) & SI_CS_RX_CNT_MASK)
+#define SI_CS_TX_CNT_SET(x) (((x) << SI_CS_TX_CNT_LSB) & SI_CS_TX_CNT_MASK)
+
+#endif /* } */
+
+#endif /*TARGET_REG_TABLE_H_*/
+
+
diff --git a/drivers/net/ath6kl/include/wlan_api.h b/drivers/net/ath6kl/include/wlan_api.h
new file mode 100644
index 00000000000..f55a6454a6b
--- /dev/null
+++ b/drivers/net/ath6kl/include/wlan_api.h
@@ -0,0 +1,128 @@
+//------------------------------------------------------------------------------
+// Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// This file contains the API for the host wlan module
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _HOST_WLAN_API_H_
+#define _HOST_WLAN_API_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <a_osapi.h>
+
+struct ieee80211_node_table;
+struct ieee80211_frame;
+
+struct ieee80211_common_ie {
+    A_UINT16    ie_chan;
+    A_UINT8     *ie_tstamp;
+    A_UINT8     *ie_ssid;
+    A_UINT8     *ie_rates;
+    A_UINT8     *ie_xrates;
+    A_UINT8     *ie_country;
+    A_UINT8     *ie_wpa;
+    A_UINT8     *ie_rsn;
+    A_UINT8     *ie_wmm;
+    A_UINT8     *ie_ath;
+    A_UINT16    ie_capInfo;
+    A_UINT16    ie_beaconInt;
+    A_UINT8     *ie_tim;
+    A_UINT8     *ie_chswitch;
+    A_UINT8     ie_erp;
+    A_UINT8     *ie_wsc;
+    A_UINT8     *ie_htcap;
+    A_UINT8     *ie_htop;
+#ifdef WAPI_ENABLE
+    A_UINT8     *ie_wapi;
+#endif
+};
+
+typedef struct bss {
+    A_UINT8                      ni_macaddr[6];
+    A_UINT8                      ni_snr;
+    A_INT16                      ni_rssi;
+    struct bss                   *ni_list_next;
+    struct bss                   *ni_list_prev;
+    struct bss                   *ni_hash_next;
+    struct bss                   *ni_hash_prev;
+    struct ieee80211_common_ie   ni_cie;
+    A_UINT8                     *ni_buf;
+    A_UINT16                     ni_framelen;
+    struct ieee80211_node_table *ni_table;
+    A_UINT32                     ni_refcnt;
+    int                          ni_scangen;
+
+    A_UINT32                     ni_tstamp;
+    A_UINT32                     ni_actcnt;
+#ifdef OS_ROAM_MANAGEMENT
+    A_UINT32                     ni_si_gen;
+#endif
+} bss_t;
+
+typedef void wlan_node_iter_func(void *arg, bss_t *);
+
+bss_t *wlan_node_alloc(struct ieee80211_node_table *nt, int wh_size);
+void wlan_node_free(bss_t *ni);
+void wlan_setup_node(struct ieee80211_node_table *nt, bss_t *ni,
+                const A_UINT8 *macaddr);
+bss_t *wlan_find_node(struct ieee80211_node_table *nt, const A_UINT8 *macaddr);
+void wlan_node_reclaim(struct ieee80211_node_table *nt, bss_t *ni);
+void wlan_free_allnodes(struct ieee80211_node_table *nt);
+void wlan_iterate_nodes(struct ieee80211_node_table *nt, wlan_node_iter_func *f,
+                        void *arg);
+
+void wlan_node_table_init(void *wmip, struct ieee80211_node_table *nt);
+void wlan_node_table_reset(struct ieee80211_node_table *nt);
+void wlan_node_table_cleanup(struct ieee80211_node_table *nt);
+
+A_STATUS wlan_parse_beacon(A_UINT8 *buf, int framelen,
+                           struct ieee80211_common_ie *cie);
+
+A_UINT16 wlan_ieee2freq(int chan);
+A_UINT32 wlan_freq2ieee(A_UINT16 freq);
+
+void wlan_set_nodeage(struct ieee80211_node_table *nt, A_UINT32 nodeAge);
+
+void
+wlan_refresh_inactive_nodes (struct ieee80211_node_table *nt);
+
+bss_t *
+wlan_find_Ssidnode (struct ieee80211_node_table *nt, A_UCHAR *pSsid,
+                    A_UINT32 ssidLength, A_BOOL bIsWPA2, A_BOOL bMatchSSID);
+
+void
+wlan_node_return (struct ieee80211_node_table *nt, bss_t *ni);
+
+bss_t *wlan_node_remove(struct ieee80211_node_table *nt, A_UINT8 *bssid);
+
+bss_t *
+wlan_find_matching_Ssidnode (struct ieee80211_node_table *nt, A_UCHAR *pSsid,
+                    A_UINT32 ssidLength, A_UINT32 dot11AuthMode, A_UINT32 authMode,
+                   A_UINT32 pairwiseCryptoType, A_UINT32 grpwiseCryptoTyp);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HOST_WLAN_API_H_ */
diff --git a/drivers/net/ath6kl/include/wmi_api.h b/drivers/net/ath6kl/include/wmi_api.h
new file mode 100644
index 00000000000..4a9154316a3
--- /dev/null
+++ b/drivers/net/ath6kl/include/wmi_api.h
@@ -0,0 +1,441 @@
+//------------------------------------------------------------------------------
+// <copyright file="wmi_api.h" company="Atheros">
+//    Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// This file contains the definitions for the Wireless Module Interface (WMI).
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _WMI_API_H_
+#define _WMI_API_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+    /* WMI converts a dix frame with an ethernet payload (up to 1500 bytes) 
+     * to an 802.3 frame (adds SNAP header) and adds on a WMI data header */
+#define WMI_MAX_TX_DATA_FRAME_LENGTH (1500 + sizeof(WMI_DATA_HDR) + sizeof(ATH_MAC_HDR) + sizeof(ATH_LLC_SNAP_HDR))
+
+    /* A normal WMI data frame */
+#define WMI_MAX_NORMAL_RX_DATA_FRAME_LENGTH (1500 + sizeof(WMI_DATA_HDR) + sizeof(ATH_MAC_HDR) + sizeof(ATH_LLC_SNAP_HDR))
+    
+    /* An AMSDU frame */ /* The MAX AMSDU length of AR6003 is 3839 */
+#define WMI_MAX_AMSDU_RX_DATA_FRAME_LENGTH  (3840 + sizeof(WMI_DATA_HDR) + sizeof(ATH_MAC_HDR) + sizeof(ATH_LLC_SNAP_HDR))
+
+/*
+ * IP QoS Field definitions according to 802.1p
+ */
+#define BEST_EFFORT_PRI         0
+#define BACKGROUND_PRI          1
+#define EXCELLENT_EFFORT_PRI    3
+#define CONTROLLED_LOAD_PRI     4
+#define VIDEO_PRI               5
+#define VOICE_PRI               6
+#define NETWORK_CONTROL_PRI     7
+#define MAX_NUM_PRI             8
+
+#define UNDEFINED_PRI           (0xff)
+
+#define WMI_IMPLICIT_PSTREAM_INACTIVITY_INT 5000 /* 5 seconds */
+
+#define A_ROUND_UP(x, y)  ((((x) + ((y) - 1)) / (y)) * (y))
+
+typedef enum {
+    ATHEROS_COMPLIANCE = 0x1,
+}TSPEC_PARAM_COMPLIANCE;
+
+struct wmi_t;
+
+void *wmi_init(void *devt);
+
+void wmi_qos_state_init(struct wmi_t *wmip);
+void wmi_shutdown(struct wmi_t *wmip);
+HTC_ENDPOINT_ID wmi_get_control_ep(struct wmi_t * wmip);
+void wmi_set_control_ep(struct wmi_t * wmip, HTC_ENDPOINT_ID eid);
+A_UINT16  wmi_get_mapped_qos_queue(struct wmi_t *, A_UINT8);
+A_STATUS wmi_dix_2_dot3(struct wmi_t *wmip, void *osbuf);
+A_STATUS wmi_data_hdr_add(struct wmi_t *wmip, void *osbuf, A_UINT8 msgType, A_BOOL bMoreData, WMI_DATA_HDR_DATA_TYPE data_type,A_UINT8 metaVersion, void *pTxMetaS);
+A_STATUS wmi_dot3_2_dix(void *osbuf);
+
+A_STATUS wmi_dot11_hdr_remove (struct wmi_t *wmip, void *osbuf);
+A_STATUS wmi_dot11_hdr_add(struct wmi_t *wmip, void *osbuf, NETWORK_TYPE mode);
+
+A_STATUS wmi_data_hdr_remove(struct wmi_t *wmip, void *osbuf);
+A_STATUS wmi_syncpoint(struct wmi_t *wmip);
+A_STATUS wmi_syncpoint_reset(struct wmi_t *wmip);
+A_UINT8 wmi_implicit_create_pstream(struct wmi_t *wmip, void *osbuf, A_UINT32 layer2Priority, A_BOOL wmmEnabled);
+
+A_UINT8 wmi_determine_userPriority (A_UINT8 *pkt, A_UINT32 layer2Pri);
+
+A_STATUS wmi_control_rx(struct wmi_t *wmip, void *osbuf);
+void wmi_iterate_nodes(struct wmi_t *wmip, wlan_node_iter_func *f, void *arg);
+void wmi_free_allnodes(struct wmi_t *wmip);
+bss_t *wmi_find_node(struct wmi_t *wmip, const A_UINT8 *macaddr);
+void wmi_free_node(struct wmi_t *wmip, const A_UINT8 *macaddr);
+
+
+typedef enum {
+    NO_SYNC_WMIFLAG = 0,
+    SYNC_BEFORE_WMIFLAG,            /* transmit all queued data before cmd */
+    SYNC_AFTER_WMIFLAG,             /* any new data waits until cmd execs */
+    SYNC_BOTH_WMIFLAG,
+    END_WMIFLAG                     /* end marker */
+} WMI_SYNC_FLAG;
+
+A_STATUS wmi_cmd_send(struct wmi_t *wmip, void *osbuf, WMI_COMMAND_ID cmdId,
+                      WMI_SYNC_FLAG flag);
+
+A_STATUS wmi_connect_cmd(struct wmi_t *wmip,
+                         NETWORK_TYPE netType,
+                         DOT11_AUTH_MODE dot11AuthMode,
+                         AUTH_MODE authMode,
+                         CRYPTO_TYPE pairwiseCrypto,
+                         A_UINT8 pairwiseCryptoLen,
+                         CRYPTO_TYPE groupCrypto,
+                         A_UINT8 groupCryptoLen,
+                         int ssidLength,
+                         A_UCHAR *ssid,
+                         A_UINT8 *bssid,
+                         A_UINT16 channel,
+                         A_UINT32 ctrl_flags);
+
+A_STATUS wmi_reconnect_cmd(struct wmi_t *wmip,
+                           A_UINT8 *bssid,
+                           A_UINT16 channel);
+A_STATUS wmi_disconnect_cmd(struct wmi_t *wmip);
+A_STATUS wmi_getrev_cmd(struct wmi_t *wmip);
+A_STATUS wmi_startscan_cmd(struct wmi_t *wmip, WMI_SCAN_TYPE scanType,
+                           A_BOOL forceFgScan, A_BOOL isLegacy,
+                           A_UINT32 homeDwellTime, A_UINT32 forceScanInterval,
+                           A_INT8 numChan, A_UINT16 *channelList);
+A_STATUS wmi_scanparams_cmd(struct wmi_t *wmip, A_UINT16 fg_start_sec,
+                            A_UINT16 fg_end_sec, A_UINT16 bg_sec,
+                            A_UINT16 minact_chdw_msec,
+                            A_UINT16 maxact_chdw_msec, A_UINT16 pas_chdw_msec,
+                            A_UINT8 shScanRatio, A_UINT8 scanCtrlFlags,
+                            A_UINT32 max_dfsch_act_time,
+                            A_UINT16 maxact_scan_per_ssid);
+A_STATUS wmi_bssfilter_cmd(struct wmi_t *wmip, A_UINT8 filter, A_UINT32 ieMask);
+A_STATUS wmi_probedSsid_cmd(struct wmi_t *wmip, A_UINT8 index, A_UINT8 flag,
+                            A_UINT8 ssidLength, A_UCHAR *ssid);
+A_STATUS wmi_listeninterval_cmd(struct wmi_t *wmip, A_UINT16 listenInterval, A_UINT16 listenBeacons);
+A_STATUS wmi_bmisstime_cmd(struct wmi_t *wmip, A_UINT16 bmisstime, A_UINT16 bmissbeacons);
+A_STATUS wmi_associnfo_cmd(struct wmi_t *wmip, A_UINT8 ieType,
+                           A_UINT8 ieLen, A_UINT8 *ieInfo);
+A_STATUS wmi_powermode_cmd(struct wmi_t *wmip, A_UINT8 powerMode);
+A_STATUS wmi_ibsspmcaps_cmd(struct wmi_t *wmip, A_UINT8 pmEnable, A_UINT8 ttl,
+                            A_UINT16 atim_windows, A_UINT16 timeout_value);
+A_STATUS wmi_apps_cmd(struct wmi_t *wmip, A_UINT8 psType, A_UINT32 idle_time,
+                   A_UINT32 ps_period, A_UINT8 sleep_period);
+A_STATUS wmi_pmparams_cmd(struct wmi_t *wmip, A_UINT16 idlePeriod,
+                           A_UINT16 psPollNum, A_UINT16 dtimPolicy,
+                           A_UINT16 wakup_tx_policy, A_UINT16 num_tx_to_wakeup,
+                           A_UINT16 ps_fail_event_policy);
+A_STATUS wmi_disctimeout_cmd(struct wmi_t *wmip, A_UINT8 timeout);
+A_STATUS wmi_sync_cmd(struct wmi_t *wmip, A_UINT8 syncNumber);
+A_STATUS wmi_create_pstream_cmd(struct wmi_t *wmip, WMI_CREATE_PSTREAM_CMD *pstream);
+A_STATUS wmi_delete_pstream_cmd(struct wmi_t *wmip, A_UINT8 trafficClass, A_UINT8 streamID);
+A_STATUS wmi_set_framerate_cmd(struct wmi_t *wmip, A_UINT8 bEnable, A_UINT8 type, A_UINT8 subType, A_UINT16 rateMask);
+A_STATUS wmi_set_bitrate_cmd(struct wmi_t *wmip, A_INT32 dataRate, A_INT32 mgmtRate, A_INT32 ctlRate);
+A_STATUS wmi_get_bitrate_cmd(struct wmi_t *wmip);
+A_INT8   wmi_validate_bitrate(struct wmi_t *wmip, A_INT32 rate, A_INT8 *rate_idx);
+A_STATUS wmi_get_regDomain_cmd(struct wmi_t *wmip);
+A_STATUS wmi_get_channelList_cmd(struct wmi_t *wmip);
+A_STATUS wmi_set_channelParams_cmd(struct wmi_t *wmip, A_UINT8 scanParam,
+                                   WMI_PHY_MODE mode, A_INT8 numChan,
+                                   A_UINT16 *channelList);
+
+A_STATUS wmi_set_snr_threshold_params(struct wmi_t *wmip,
+                                       WMI_SNR_THRESHOLD_PARAMS_CMD *snrCmd);
+A_STATUS wmi_set_rssi_threshold_params(struct wmi_t *wmip,
+                                        WMI_RSSI_THRESHOLD_PARAMS_CMD *rssiCmd);
+A_STATUS wmi_clr_rssi_snr(struct wmi_t *wmip);
+A_STATUS wmi_set_lq_threshold_params(struct wmi_t *wmip,
+                                      WMI_LQ_THRESHOLD_PARAMS_CMD *lqCmd);
+A_STATUS wmi_set_rts_cmd(struct wmi_t *wmip, A_UINT16 threshold);
+A_STATUS wmi_set_lpreamble_cmd(struct wmi_t *wmip, A_UINT8 status, A_UINT8 preamblePolicy);
+
+A_STATUS wmi_set_error_report_bitmask(struct wmi_t *wmip, A_UINT32 bitmask);
+
+A_STATUS wmi_get_challenge_resp_cmd(struct wmi_t *wmip, A_UINT32 cookie,
+                                    A_UINT32 source);
+
+A_STATUS wmi_config_debug_module_cmd(struct wmi_t *wmip, A_UINT16 mmask,
+                                     A_UINT16 tsr, A_BOOL rep, A_UINT16 size,
+                                     A_UINT32 valid);
+
+A_STATUS wmi_get_stats_cmd(struct wmi_t *wmip);
+
+A_STATUS wmi_addKey_cmd(struct wmi_t *wmip, A_UINT8 keyIndex,
+                        CRYPTO_TYPE keyType, A_UINT8 keyUsage,
+                        A_UINT8 keyLength,A_UINT8 *keyRSC,
+                        A_UINT8 *keyMaterial, A_UINT8 key_op_ctrl, A_UINT8 *mac,
+                        WMI_SYNC_FLAG sync_flag);
+A_STATUS wmi_add_krk_cmd(struct wmi_t *wmip, A_UINT8 *krk);
+A_STATUS wmi_delete_krk_cmd(struct wmi_t *wmip);
+A_STATUS wmi_deleteKey_cmd(struct wmi_t *wmip, A_UINT8 keyIndex);
+A_STATUS wmi_set_akmp_params_cmd(struct wmi_t *wmip,
+                                 WMI_SET_AKMP_PARAMS_CMD *akmpParams);
+A_STATUS wmi_get_pmkid_list_cmd(struct wmi_t *wmip);
+A_STATUS wmi_set_pmkid_list_cmd(struct wmi_t *wmip,
+                                WMI_SET_PMKID_LIST_CMD *pmkInfo);
+A_STATUS wmi_abort_scan_cmd(struct wmi_t *wmip);
+A_STATUS wmi_set_txPwr_cmd(struct wmi_t *wmip, A_UINT8 dbM);
+A_STATUS wmi_get_txPwr_cmd(struct wmi_t *wmip);
+A_STATUS wmi_addBadAp_cmd(struct wmi_t *wmip, A_UINT8 apIndex, A_UINT8 *bssid);
+A_STATUS wmi_deleteBadAp_cmd(struct wmi_t *wmip, A_UINT8 apIndex);
+A_STATUS wmi_set_tkip_countermeasures_cmd(struct wmi_t *wmip, A_BOOL en);
+A_STATUS wmi_setPmkid_cmd(struct wmi_t *wmip, A_UINT8 *bssid, A_UINT8 *pmkId,
+                          A_BOOL set);
+A_STATUS wmi_set_access_params_cmd(struct wmi_t *wmip, A_UINT8 ac, A_UINT16 txop,
+                                   A_UINT8 eCWmin, A_UINT8 eCWmax,
+                                   A_UINT8 aifsn);
+A_STATUS wmi_set_retry_limits_cmd(struct wmi_t *wmip, A_UINT8 frameType,
+                                  A_UINT8 trafficClass, A_UINT8 maxRetries,
+                                  A_UINT8 enableNotify);
+
+void wmi_get_current_bssid(struct wmi_t *wmip, A_UINT8 *bssid);
+
+A_STATUS wmi_get_roam_tbl_cmd(struct wmi_t *wmip);
+A_STATUS wmi_get_roam_data_cmd(struct wmi_t *wmip, A_UINT8 roamDataType);
+A_STATUS wmi_set_roam_ctrl_cmd(struct wmi_t *wmip, WMI_SET_ROAM_CTRL_CMD *p,
+                               A_UINT8 size);
+A_STATUS wmi_set_powersave_timers_cmd(struct wmi_t *wmip,
+                            WMI_POWERSAVE_TIMERS_POLICY_CMD *pCmd,
+                            A_UINT8 size);
+
+A_STATUS wmi_set_opt_mode_cmd(struct wmi_t *wmip, A_UINT8 optMode);
+A_STATUS wmi_opt_tx_frame_cmd(struct wmi_t *wmip,
+                              A_UINT8 frmType,
+                              A_UINT8 *dstMacAddr,
+                              A_UINT8 *bssid,
+                              A_UINT16 optIEDataLen,
+                              A_UINT8 *optIEData);
+
+A_STATUS wmi_set_adhoc_bconIntvl_cmd(struct wmi_t *wmip, A_UINT16 intvl);
+A_STATUS wmi_set_voice_pkt_size_cmd(struct wmi_t *wmip, A_UINT16 voicePktSize);
+A_STATUS wmi_set_max_sp_len_cmd(struct wmi_t *wmip, A_UINT8 maxSpLen);
+A_UINT8  convert_userPriority_to_trafficClass(A_UINT8 userPriority);
+A_UINT8 wmi_get_power_mode_cmd(struct wmi_t *wmip);
+A_STATUS wmi_verify_tspec_params(WMI_CREATE_PSTREAM_CMD *pCmd, A_BOOL tspecCompliance);
+
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+A_STATUS wmi_test_cmd(struct wmi_t *wmip, A_UINT8 *buf, A_UINT32  len);
+#endif
+
+A_STATUS wmi_set_bt_status_cmd(struct wmi_t *wmip, A_UINT8 streamType, A_UINT8 status);
+A_STATUS wmi_set_bt_params_cmd(struct wmi_t *wmip, WMI_SET_BT_PARAMS_CMD* cmd);
+
+A_STATUS wmi_set_btcoex_fe_ant_cmd(struct wmi_t *wmip, WMI_SET_BTCOEX_FE_ANT_CMD * cmd);
+
+A_STATUS wmi_set_btcoex_colocated_bt_dev_cmd(struct wmi_t *wmip,
+		                                WMI_SET_BTCOEX_COLOCATED_BT_DEV_CMD * cmd);
+
+A_STATUS wmi_set_btcoex_btinquiry_page_config_cmd(struct wmi_t *wmip,
+                               			WMI_SET_BTCOEX_BTINQUIRY_PAGE_CONFIG_CMD *cmd);
+
+A_STATUS wmi_set_btcoex_sco_config_cmd(struct wmi_t *wmip,
+                   		              WMI_SET_BTCOEX_SCO_CONFIG_CMD * cmd);
+
+A_STATUS wmi_set_btcoex_a2dp_config_cmd(struct wmi_t *wmip,
+		                                 WMI_SET_BTCOEX_A2DP_CONFIG_CMD* cmd);
+
+
+A_STATUS wmi_set_btcoex_aclcoex_config_cmd(struct wmi_t *wmip, WMI_SET_BTCOEX_ACLCOEX_CONFIG_CMD* cmd);
+
+A_STATUS wmi_set_btcoex_debug_cmd(struct wmi_t *wmip, WMI_SET_BTCOEX_DEBUG_CMD * cmd);
+
+A_STATUS wmi_set_btcoex_bt_operating_status_cmd(struct wmi_t * wmip,
+							WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMD * cmd);
+
+A_STATUS wmi_get_btcoex_config_cmd(struct wmi_t * wmip, WMI_GET_BTCOEX_CONFIG_CMD * cmd);
+
+A_STATUS wmi_get_btcoex_stats_cmd(struct wmi_t * wmip);
+
+A_STATUS wmi_SGI_cmd(struct wmi_t *wmip, A_UINT32 sgiMask, A_UINT8 sgiPERThreshold);
+
+/*
+ *  This function is used to configure the fix rates mask to the target.
+ */
+A_STATUS wmi_set_fixrates_cmd(struct wmi_t *wmip, A_UINT32 fixRatesMask);
+A_STATUS wmi_get_ratemask_cmd(struct wmi_t *wmip);
+
+A_STATUS wmi_set_authmode_cmd(struct wmi_t *wmip, A_UINT8 mode);
+
+A_STATUS wmi_set_reassocmode_cmd(struct wmi_t *wmip, A_UINT8 mode);
+
+A_STATUS wmi_set_qos_supp_cmd(struct wmi_t *wmip,A_UINT8 status);
+A_STATUS wmi_set_wmm_cmd(struct wmi_t *wmip, WMI_WMM_STATUS status);
+A_STATUS wmi_set_wmm_txop(struct wmi_t *wmip, WMI_TXOP_CFG txEnable);
+A_STATUS wmi_set_country(struct wmi_t *wmip, A_UCHAR *countryCode);
+
+A_STATUS wmi_get_keepalive_configured(struct wmi_t *wmip);
+A_UINT8 wmi_get_keepalive_cmd(struct wmi_t *wmip);
+A_STATUS wmi_set_keepalive_cmd(struct wmi_t *wmip, A_UINT8 keepaliveInterval);
+
+A_STATUS wmi_set_appie_cmd(struct wmi_t *wmip, A_UINT8 mgmtFrmType,
+                           A_UINT8 ieLen,A_UINT8 *ieInfo);
+
+A_STATUS wmi_set_halparam_cmd(struct wmi_t *wmip, A_UINT8 *cmd, A_UINT16 dataLen);
+
+A_INT32 wmi_get_rate(A_INT8 rateindex);
+
+A_STATUS wmi_set_ip_cmd(struct wmi_t *wmip, WMI_SET_IP_CMD *cmd);
+
+/*Wake on Wireless WMI commands*/
+A_STATUS wmi_set_host_sleep_mode_cmd(struct wmi_t *wmip, WMI_SET_HOST_SLEEP_MODE_CMD *cmd);
+A_STATUS wmi_set_wow_mode_cmd(struct wmi_t *wmip, WMI_SET_WOW_MODE_CMD *cmd);
+A_STATUS wmi_get_wow_list_cmd(struct wmi_t *wmip, WMI_GET_WOW_LIST_CMD *cmd);
+A_STATUS wmi_add_wow_pattern_cmd(struct wmi_t *wmip,
+                                 WMI_ADD_WOW_PATTERN_CMD *cmd, A_UINT8* pattern, A_UINT8* mask, A_UINT8 pattern_size);
+A_STATUS wmi_del_wow_pattern_cmd(struct wmi_t *wmip,
+                                 WMI_DEL_WOW_PATTERN_CMD *cmd);
+A_STATUS wmi_set_wsc_status_cmd(struct wmi_t *wmip, A_UINT32 status);
+
+A_STATUS
+wmi_set_params_cmd(struct wmi_t *wmip, A_UINT32 opcode, A_UINT32 length, A_CHAR* buffer);
+
+A_STATUS
+wmi_set_mcast_filter_cmd(struct wmi_t *wmip, A_UINT8 dot1, A_UINT8 dot2, A_UINT8 dot3, A_UINT8 dot4);
+
+A_STATUS
+wmi_del_mcast_filter_cmd(struct wmi_t *wmip, A_UINT8 dot1, A_UINT8 dot2, A_UINT8 dot3, A_UINT8 dot4);
+
+A_STATUS
+wmi_mcast_filter_cmd(struct wmi_t *wmip, A_UINT8 enable);
+
+bss_t *
+wmi_find_Ssidnode (struct wmi_t *wmip, A_UCHAR *pSsid,
+                   A_UINT32 ssidLength, A_BOOL bIsWPA2, A_BOOL bMatchSSID);
+
+
+void
+wmi_node_return (struct wmi_t *wmip, bss_t *bss);
+
+void
+wmi_set_nodeage(struct wmi_t *wmip, A_UINT32 nodeAge);
+
+#if defined(CONFIG_TARGET_PROFILE_SUPPORT)
+A_STATUS wmi_prof_cfg_cmd(struct wmi_t *wmip, A_UINT32 period, A_UINT32 nbins);
+A_STATUS wmi_prof_addr_set_cmd(struct wmi_t *wmip, A_UINT32 addr);
+A_STATUS wmi_prof_start_cmd(struct wmi_t *wmip);
+A_STATUS wmi_prof_stop_cmd(struct wmi_t *wmip);
+A_STATUS wmi_prof_count_get_cmd(struct wmi_t *wmip);
+#endif /* CONFIG_TARGET_PROFILE_SUPPORT */
+#ifdef OS_ROAM_MANAGEMENT
+void wmi_scan_indication (struct wmi_t *wmip);
+#endif
+
+A_STATUS
+wmi_set_target_event_report_cmd(struct wmi_t *wmip, WMI_SET_TARGET_EVENT_REPORT_CMD* cmd);
+
+bss_t   *wmi_rm_current_bss (struct wmi_t *wmip, A_UINT8 *id);
+A_STATUS wmi_add_current_bss (struct wmi_t *wmip, A_UINT8 *id, bss_t *bss);
+
+
+/*
+ * AP mode
+ */
+A_STATUS
+wmi_ap_profile_commit(struct wmi_t *wmip, WMI_CONNECT_CMD *p);
+
+A_STATUS
+wmi_ap_set_hidden_ssid(struct wmi_t *wmip, A_UINT8 hidden_ssid);
+
+A_STATUS
+wmi_ap_set_num_sta(struct wmi_t *wmip, A_UINT8 num_sta);
+
+A_STATUS
+wmi_ap_set_acl_policy(struct wmi_t *wmip, A_UINT8 policy);
+
+A_STATUS
+wmi_ap_acl_mac_list(struct wmi_t *wmip, WMI_AP_ACL_MAC_CMD *a);
+
+A_UINT8
+acl_add_del_mac(WMI_AP_ACL *a, WMI_AP_ACL_MAC_CMD *acl);
+
+A_STATUS
+wmi_ap_set_mlme(struct wmi_t *wmip, A_UINT8 cmd, A_UINT8 *mac, A_UINT16 reason);
+
+A_STATUS
+wmi_set_pvb_cmd(struct wmi_t *wmip, A_UINT16 aid, A_BOOL flag);
+
+A_STATUS
+wmi_ap_conn_inact_time(struct wmi_t *wmip, A_UINT32 period);
+
+A_STATUS
+wmi_ap_bgscan_time(struct wmi_t *wmip, A_UINT32 period, A_UINT32 dwell);
+
+A_STATUS
+wmi_ap_set_dtim(struct wmi_t *wmip, A_UINT8 dtim);
+
+A_STATUS
+wmi_ap_set_rateset(struct wmi_t *wmip, A_UINT8 rateset);
+
+A_STATUS
+wmi_set_ht_cap_cmd(struct wmi_t *wmip, WMI_SET_HT_CAP_CMD *cmd);
+
+A_STATUS
+wmi_set_ht_op_cmd(struct wmi_t *wmip, A_UINT8 sta_chan_width);
+
+A_STATUS
+wmi_send_hci_cmd(struct wmi_t *wmip, A_UINT8 *buf, A_UINT16 sz);
+
+A_STATUS
+wmi_set_tx_select_rates_cmd(struct wmi_t *wmip, A_UINT32 *pMaskArray);
+
+A_STATUS
+wmi_setup_aggr_cmd(struct wmi_t *wmip, A_UINT8 tid);
+
+A_STATUS
+wmi_delete_aggr_cmd(struct wmi_t *wmip, A_UINT8 tid, A_BOOL uplink);
+
+A_STATUS
+wmi_allow_aggr_cmd(struct wmi_t *wmip, A_UINT16 tx_tidmask, A_UINT16 rx_tidmask);
+
+A_STATUS 
+wmi_set_rx_frame_format_cmd(struct wmi_t *wmip, A_UINT8 rxMetaVersion, A_BOOL rxDot11Hdr, A_BOOL defragOnHost);
+
+A_STATUS 
+wmi_set_thin_mode_cmd(struct wmi_t *wmip, A_BOOL bThinMode);
+
+A_STATUS
+wmi_set_wlan_conn_precedence_cmd(struct wmi_t *wmip, BT_WLAN_CONN_PRECEDENCE precedence);
+
+A_STATUS
+wmi_set_pmk_cmd(struct wmi_t *wmip, A_UINT8 *pmk);
+
+A_UINT16
+wmi_ieee2freq (int chan);
+
+A_UINT32
+wmi_freq2ieee (A_UINT16 freq);
+
+bss_t *
+wmi_find_matching_Ssidnode (struct wmi_t *wmip, A_UCHAR *pSsid,
+                   A_UINT32 ssidLength,
+                   A_UINT32 dot11AuthMode, A_UINT32 authMode,
+                   A_UINT32 pairwiseCryptoType, A_UINT32 grpwiseCryptoTyp);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _WMI_API_H_ */
diff --git a/drivers/net/ath6kl/miscdrv/ar3kconfig.c b/drivers/net/ath6kl/miscdrv/ar3kconfig.c
new file mode 100644
index 00000000000..83bc5be3ef1
--- /dev/null
+++ b/drivers/net/ath6kl/miscdrv/ar3kconfig.c
@@ -0,0 +1,566 @@
+//------------------------------------------------------------------------------
+// Copyright (c) 2009-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// AR3K configuration implementation
+//
+// Author(s): ="Atheros"
+//==============================================================================
+
+#include "a_config.h"
+#include "athdefs.h"
+#include "a_types.h"
+#include "a_osapi.h"
+#define ATH_MODULE_NAME misc
+#include "a_debug.h"
+#include "common_drv.h"
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+#include "export_hci_transport.h"
+#else
+#include "hci_transport_api.h"
+#endif
+#include "ar3kconfig.h"
+#include "tlpm.h"
+
+#define BAUD_CHANGE_COMMAND_STATUS_OFFSET   5
+#define HCI_EVENT_RESP_TIMEOUTMS            3000
+#define HCI_CMD_OPCODE_BYTE_LOW_OFFSET      0
+#define HCI_CMD_OPCODE_BYTE_HI_OFFSET       1
+#define HCI_EVENT_OPCODE_BYTE_LOW           3
+#define HCI_EVENT_OPCODE_BYTE_HI            4
+#define HCI_CMD_COMPLETE_EVENT_CODE         0xE
+#define HCI_MAX_EVT_RECV_LENGTH             257
+#define EXIT_MIN_BOOT_COMMAND_STATUS_OFFSET  5
+
+A_STATUS AthPSInitialize(AR3K_CONFIG_INFO *hdev);
+
+static A_STATUS SendHCICommand(AR3K_CONFIG_INFO *pConfig,
+                               A_UINT8          *pBuffer,
+                               int              Length)
+{
+    HTC_PACKET  *pPacket = NULL;
+    A_STATUS    status = A_OK;
+       
+    do {   
+        
+        pPacket = (HTC_PACKET *)A_MALLOC(sizeof(HTC_PACKET));     
+        if (NULL == pPacket) {
+            status = A_NO_MEMORY;
+            break;    
+        }       
+        
+        A_MEMZERO(pPacket,sizeof(HTC_PACKET));      
+        SET_HTC_PACKET_INFO_TX(pPacket,
+                               NULL,
+                               pBuffer, 
+                               Length,
+                               HCI_COMMAND_TYPE, 
+                               AR6K_CONTROL_PKT_TAG);
+        
+            /* issue synchronously */                                      
+        status = HCI_TransportSendPkt(pConfig->pHCIDev,pPacket,TRUE);   
+        
+    } while (FALSE);
+   
+    if (pPacket != NULL) {
+        A_FREE(pPacket);
+    }
+        
+    return status;
+}
+
+static A_STATUS RecvHCIEvent(AR3K_CONFIG_INFO *pConfig,
+                             A_UINT8          *pBuffer,
+                             int              *pLength)
+{
+    A_STATUS    status = A_OK; 
+    HTC_PACKET  *pRecvPacket = NULL;
+    
+    do {
+                 
+        pRecvPacket = (HTC_PACKET *)A_MALLOC(sizeof(HTC_PACKET));
+        if (NULL == pRecvPacket) {
+            status = A_NO_MEMORY;
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Failed to alloc HTC struct \n"));
+            break;    
+        }     
+        
+        A_MEMZERO(pRecvPacket,sizeof(HTC_PACKET)); 
+         
+        SET_HTC_PACKET_INFO_RX_REFILL(pRecvPacket,NULL,pBuffer,*pLength,HCI_EVENT_TYPE);
+        
+        status = HCI_TransportRecvHCIEventSync(pConfig->pHCIDev,
+                                               pRecvPacket,
+                                               HCI_EVENT_RESP_TIMEOUTMS);
+        if (A_FAILED(status)) {
+            break;    
+        }
+
+        *pLength = pRecvPacket->ActualLength;
+        
+    } while (FALSE);
+       
+    if (pRecvPacket != NULL) {
+        A_FREE(pRecvPacket);    
+    }
+    
+    return status;
+} 
+    
+A_STATUS SendHCICommandWaitCommandComplete(AR3K_CONFIG_INFO *pConfig,
+                                           A_UINT8          *pHCICommand,
+                                           int              CmdLength,
+                                           A_UINT8          **ppEventBuffer,
+                                           A_UINT8          **ppBufferToFree)
+{
+    A_STATUS    status = A_OK;   
+    A_UINT8     *pBuffer = NULL;
+    A_UINT8     *pTemp;
+    int         length;
+    A_BOOL      commandComplete = FALSE;
+    A_UINT8     opCodeBytes[2];
+                               
+    do {
+        
+        length = max(HCI_MAX_EVT_RECV_LENGTH,CmdLength);
+        length += pConfig->pHCIProps->HeadRoom + pConfig->pHCIProps->TailRoom;
+        length += pConfig->pHCIProps->IOBlockPad;
+                                     
+        pBuffer = (A_UINT8 *)A_MALLOC(length);        
+        if (NULL == pBuffer) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR3K Config: Failed to allocate bt buffer \n"));
+            status = A_NO_MEMORY;
+            break;    
+        }
+        
+            /* get the opcodes to check the command complete event */
+        opCodeBytes[0] = pHCICommand[HCI_CMD_OPCODE_BYTE_LOW_OFFSET];
+        opCodeBytes[1] = pHCICommand[HCI_CMD_OPCODE_BYTE_HI_OFFSET];
+        
+            /* copy HCI command */
+        A_MEMCPY(pBuffer + pConfig->pHCIProps->HeadRoom,pHCICommand,CmdLength);         
+            /* send command */
+        status = SendHCICommand(pConfig,
+                                pBuffer + pConfig->pHCIProps->HeadRoom,
+                                CmdLength);
+        if (A_FAILED(status)) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR3K Config: Failed to send HCI Command (%d) \n", status));
+            AR_DEBUG_PRINTBUF(pHCICommand,CmdLength,"HCI Bridge Failed HCI Command");
+            break;    
+        }   
+        
+            /* reuse buffer to capture command complete event */
+        A_MEMZERO(pBuffer,length);
+        status = RecvHCIEvent(pConfig,pBuffer,&length);        
+        if (A_FAILED(status)) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR3K Config: HCI event recv failed \n"));
+            AR_DEBUG_PRINTBUF(pHCICommand,CmdLength,"HCI Bridge Failed HCI Command");
+            break;    
+        }
+        
+        pTemp = pBuffer + pConfig->pHCIProps->HeadRoom;        
+        if (pTemp[0] == HCI_CMD_COMPLETE_EVENT_CODE) {
+            if ((pTemp[HCI_EVENT_OPCODE_BYTE_LOW] == opCodeBytes[0]) &&
+                (pTemp[HCI_EVENT_OPCODE_BYTE_HI] == opCodeBytes[1])) {
+                commandComplete = TRUE;    
+            }
+        }
+        
+        if (!commandComplete) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR3K Config: Unexpected HCI event : %d \n",pTemp[0]));
+            AR_DEBUG_PRINTBUF(pTemp,pTemp[1],"Unexpected HCI event");
+            status = A_ECOMM;
+            break;    
+        }       
+        
+        if (ppEventBuffer != NULL) {
+                /* caller wants to look at the event */
+            *ppEventBuffer = pTemp;
+            if (ppBufferToFree == NULL) {
+                status = A_EINVAL;
+                break;        
+            }
+                /* caller must free the buffer */
+            *ppBufferToFree = pBuffer;
+            pBuffer = NULL;            
+        }
+        
+    } while (FALSE);
+
+    if (pBuffer != NULL) {
+        A_FREE(pBuffer);    
+    }
+    
+    return status;    
+}
+
+static A_STATUS AR3KConfigureHCIBaud(AR3K_CONFIG_INFO *pConfig)
+{
+    A_STATUS    status = A_OK;
+    A_UINT8     hciBaudChangeCommand[] =  {0x0c,0xfc,0x2,0,0};
+    A_UINT16    baudVal; 
+    A_UINT8     *pEvent = NULL;
+    A_UINT8     *pBufferToFree = NULL;
+    
+    do {
+        
+        if (pConfig->Flags & AR3K_CONFIG_FLAG_SET_AR3K_BAUD) {
+            baudVal = (A_UINT16)(pConfig->AR3KBaudRate / 100);
+            hciBaudChangeCommand[3] = (A_UINT8)baudVal;
+            hciBaudChangeCommand[4] = (A_UINT8)(baudVal >> 8);
+            
+            status = SendHCICommandWaitCommandComplete(pConfig,
+                                                       hciBaudChangeCommand,
+                                                       sizeof(hciBaudChangeCommand),
+                                                       &pEvent,
+                                                       &pBufferToFree);          
+            if (A_FAILED(status)) {
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR3K Config: Baud rate change failed! \n"));  
+                break;    
+            }
+            
+            if (pEvent[BAUD_CHANGE_COMMAND_STATUS_OFFSET] != 0) {
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                    ("AR3K Config: Baud change command event status failed: %d \n", 
+                                pEvent[BAUD_CHANGE_COMMAND_STATUS_OFFSET]));
+                status = A_ECOMM; 
+                break;           
+            } 
+            
+            AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
+                    ("AR3K Config: Baud Changed to %d \n",pConfig->AR3KBaudRate));  
+        }
+        
+        if (pConfig->Flags & AR3K_CONFIG_FLAG_AR3K_BAUD_CHANGE_DELAY) {
+                /* some versions of AR3K do not switch baud immediately, up to 300MS */
+            A_MDELAY(325);
+        }
+        
+        if (pConfig->Flags & AR3K_CONFIG_FLAG_SET_AR6K_SCALE_STEP) {
+            /* Tell target to change UART baud rate for AR6K */
+            status = HCI_TransportSetBaudRate(pConfig->pHCIDev, pConfig->AR3KBaudRate);
+
+            if (A_FAILED(status)) {
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                    ("AR3K Config: failed to set scale and step values: %d \n", status));
+                break;    
+            }
+    
+            AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
+                    ("AR3K Config: Baud changed to %d for AR6K\n", pConfig->AR3KBaudRate));            
+        }
+                
+    } while (FALSE);
+                        
+    if (pBufferToFree != NULL) {
+        A_FREE(pBufferToFree);    
+    }
+        
+    return status;
+}
+
+static A_STATUS AR3KExitMinBoot(AR3K_CONFIG_INFO *pConfig)
+{
+    A_STATUS  status;
+    A_CHAR    exitMinBootCmd[] = {0x25,0xFC,0x0c,0x03,0x00,0x00,0x00,0x00,0x00,0x00,
+                                  0x00,0x00,0x00,0x00,0x00};
+    A_UINT8   *pEvent = NULL;
+    A_UINT8   *pBufferToFree = NULL;
+    
+    status = SendHCICommandWaitCommandComplete(pConfig,
+                                               exitMinBootCmd,
+                                               sizeof(exitMinBootCmd),
+                                               &pEvent,
+                                               &pBufferToFree);
+    
+    if (A_SUCCESS(status)) {
+        if (pEvent[EXIT_MIN_BOOT_COMMAND_STATUS_OFFSET] != 0) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                ("AR3K Config: MinBoot exit command event status failed: %d \n", 
+                            pEvent[EXIT_MIN_BOOT_COMMAND_STATUS_OFFSET]));
+            status = A_ECOMM;            
+        } else {
+            AR_DEBUG_PRINTF(ATH_DEBUG_INFO, 
+                                ("AR3K Config: MinBoot Exit Command Complete (Success) \n"));
+            A_MDELAY(1);
+        }
+    } else {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR3K Config: MinBoot Exit Failed! \n"));    
+    }
+    
+    if (pBufferToFree != NULL) {
+        A_FREE(pBufferToFree);    
+    }
+    
+    return status;                                              
+}
+                                 
+static A_STATUS AR3KConfigureSendHCIReset(AR3K_CONFIG_INFO *pConfig)
+{
+    A_STATUS status = A_OK;
+    A_UINT8 hciResetCommand[] = {0x03,0x0c,0x0};
+    A_UINT8 *pEvent = NULL;
+    A_UINT8 *pBufferToFree = NULL;
+
+    status = SendHCICommandWaitCommandComplete( pConfig,
+                                                hciResetCommand,
+                                                sizeof(hciResetCommand),
+                                                &pEvent,
+                                                &pBufferToFree );
+
+    if (A_FAILED(status)) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR3K Config: HCI reset failed! \n"));
+    }
+
+    if (pBufferToFree != NULL) {
+        A_FREE(pBufferToFree);
+    }
+
+    return status;
+}
+
+static A_STATUS AR3KEnableTLPM(AR3K_CONFIG_INFO *pConfig)
+{
+    A_STATUS  status;
+    /* AR3K vendor specific command for Host Wakeup Config */
+    A_CHAR    hostWakeupConfig[] = {0x31,0xFC,0x18,
+                                    0x02,0x00,0x00,0x00,
+                                    0x01,0x00,0x00,0x00,
+                                    TLPM_DEFAULT_IDLE_TIMEOUT_LSB,TLPM_DEFAULT_IDLE_TIMEOUT_MSB,0x00,0x00,    //idle timeout in ms
+                                    0x00,0x00,0x00,0x00,
+                                    TLPM_DEFAULT_WAKEUP_TIMEOUT_MS,0x00,0x00,0x00,    //wakeup timeout in ms
+                                    0x00,0x00,0x00,0x00};
+    /* AR3K vendor specific command for Target Wakeup Config */
+    A_CHAR    targetWakeupConfig[] = {0x31,0xFC,0x18,
+                                      0x04,0x00,0x00,0x00,
+                                      0x01,0x00,0x00,0x00,
+                                      TLPM_DEFAULT_IDLE_TIMEOUT_LSB,TLPM_DEFAULT_IDLE_TIMEOUT_MSB,0x00,0x00,  //idle timeout in ms
+                                      0x00,0x00,0x00,0x00,
+                                      TLPM_DEFAULT_WAKEUP_TIMEOUT_MS,0x00,0x00,0x00,  //wakeup timeout in ms
+                                      0x00,0x00,0x00,0x00};
+    /* AR3K vendor specific command for Host Wakeup Enable */
+    A_CHAR    hostWakeupEnable[] = {0x31,0xFC,0x4,
+                                    0x01,0x00,0x00,0x00};
+    /* AR3K vendor specific command for Target Wakeup Enable */
+    A_CHAR    targetWakeupEnable[] = {0x31,0xFC,0x4,
+                                      0x06,0x00,0x00,0x00};
+    /* AR3K vendor specific command for Sleep Enable */
+    A_CHAR    sleepEnable[] = {0x4,0xFC,0x1,
+                               0x1};
+    A_UINT8   *pEvent = NULL;
+    A_UINT8   *pBufferToFree = NULL;
+    
+    if (0 != pConfig->IdleTimeout) {
+        A_UINT8 idle_lsb = pConfig->IdleTimeout & 0xFF;
+        A_UINT8 idle_msb = (pConfig->IdleTimeout & 0xFF00) >> 8;
+        hostWakeupConfig[11] = targetWakeupConfig[11] = idle_lsb;
+        hostWakeupConfig[12] = targetWakeupConfig[12] = idle_msb;
+    }
+
+    if (0 != pConfig->WakeupTimeout) {
+        hostWakeupConfig[19] = targetWakeupConfig[19] = (pConfig->WakeupTimeout & 0xFF);
+    }
+
+    status = SendHCICommandWaitCommandComplete(pConfig,
+                                               hostWakeupConfig,
+                                               sizeof(hostWakeupConfig),
+                                               &pEvent,
+                                               &pBufferToFree);
+    if (pBufferToFree != NULL) {
+        A_FREE(pBufferToFree);    
+    }
+    if (A_FAILED(status)) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("HostWakeup Config Failed! \n"));    
+        return status;
+    }
+    
+    pEvent = NULL;
+    pBufferToFree = NULL;
+    status = SendHCICommandWaitCommandComplete(pConfig,
+                                               targetWakeupConfig,
+                                               sizeof(targetWakeupConfig),
+                                               &pEvent,
+                                               &pBufferToFree);
+    if (pBufferToFree != NULL) {
+        A_FREE(pBufferToFree);    
+    }
+    if (A_FAILED(status)) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Target Wakeup Config Failed! \n"));    
+        return status;
+    }
+
+    pEvent = NULL;
+    pBufferToFree = NULL;
+    status = SendHCICommandWaitCommandComplete(pConfig,
+                                               hostWakeupEnable,
+                                               sizeof(hostWakeupEnable),
+                                               &pEvent,
+                                               &pBufferToFree);
+    if (pBufferToFree != NULL) {
+        A_FREE(pBufferToFree);    
+    }
+    if (A_FAILED(status)) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("HostWakeup Enable Failed! \n"));    
+        return status;
+    }
+
+    pEvent = NULL;
+    pBufferToFree = NULL;
+    status = SendHCICommandWaitCommandComplete(pConfig,
+                                               targetWakeupEnable,
+                                               sizeof(targetWakeupEnable),
+                                               &pEvent,
+                                               &pBufferToFree);
+    if (pBufferToFree != NULL) {
+        A_FREE(pBufferToFree);    
+    }
+    if (A_FAILED(status)) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Target Wakeup Enable Failed! \n"));    
+        return status;
+    }
+
+    pEvent = NULL;
+    pBufferToFree = NULL;
+    status = SendHCICommandWaitCommandComplete(pConfig,
+                                               sleepEnable,
+                                               sizeof(sleepEnable),
+                                               &pEvent,
+                                               &pBufferToFree);
+    if (pBufferToFree != NULL) {
+        A_FREE(pBufferToFree);    
+    }
+    if (A_FAILED(status)) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Sleep Enable Failed! \n"));    
+    }
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR3K Config: Enable TLPM Completed (status = %d) \n",status));
+
+    return status;                                              
+}
+
+A_STATUS AR3KConfigure(AR3K_CONFIG_INFO *pConfig)
+{
+    A_STATUS        status = A_OK; 
+        
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("AR3K Config: Configuring AR3K ...\n"));
+                                
+    do {
+        
+        if ((pConfig->pHCIDev == NULL) || (pConfig->pHCIProps == NULL) || (pConfig->pHIFDevice == NULL)) {
+            status = A_EINVAL;
+            break;    
+        }
+        
+            /* disable asynchronous recv while we issue commands and receive events synchronously */
+        status = HCI_TransportEnableDisableAsyncRecv(pConfig->pHCIDev,FALSE);
+        if (A_FAILED(status)) {
+            break;    
+        }
+      
+        if (pConfig->Flags & AR3K_CONFIG_FLAG_FORCE_MINBOOT_EXIT) {
+            status =  AR3KExitMinBoot(pConfig);   
+            if (A_FAILED(status)) {
+                break;    
+            }    
+        }
+        
+       
+        /* Load patching and PST file if available*/
+        if (A_OK != AthPSInitialize(pConfig)) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Patch Download Failed!\n"));
+        }
+
+        /* Send HCI reset to make PS tags take effect*/
+        AR3KConfigureSendHCIReset(pConfig);
+
+ 	if (pConfig->Flags & 
+                (AR3K_CONFIG_FLAG_SET_AR3K_BAUD | AR3K_CONFIG_FLAG_SET_AR6K_SCALE_STEP)) {
+            status = AR3KConfigureHCIBaud(pConfig);      
+            if (A_FAILED(status)) {
+                break;    
+            }
+        }     
+
+
+
+        if (pConfig->PwrMgmtEnabled) {
+            /* the delay is required after the previous HCI reset before further
+             * HCI commands can be issued
+             */
+            A_MDELAY(200);
+            AR3KEnableTLPM(pConfig);
+        }
+               
+           /* re-enable asynchronous recv */
+        status = HCI_TransportEnableDisableAsyncRecv(pConfig->pHCIDev,TRUE);
+        if (A_FAILED(status)) {
+            break;    
+        }     
+    
+    
+    } while (FALSE);   
+    
+  
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("AR3K Config: Configuration Complete (status = %d) \n",status));
+    
+    return status;
+}
+
+A_STATUS AR3KConfigureExit(void *config)
+{
+    A_STATUS        status = A_OK; 
+    AR3K_CONFIG_INFO *pConfig = (AR3K_CONFIG_INFO *)config;
+        
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("AR3K Config: Cleaning up AR3K ...\n"));
+                                
+    do {
+        
+        if ((pConfig->pHCIDev == NULL) || (pConfig->pHCIProps == NULL) || (pConfig->pHIFDevice == NULL)) {
+            status = A_EINVAL;
+            break;    
+        }
+        
+            /* disable asynchronous recv while we issue commands and receive events synchronously */
+        status = HCI_TransportEnableDisableAsyncRecv(pConfig->pHCIDev,FALSE);
+        if (A_FAILED(status)) {
+            break;    
+        }
+      
+        if (pConfig->Flags & 
+                (AR3K_CONFIG_FLAG_SET_AR3K_BAUD | AR3K_CONFIG_FLAG_SET_AR6K_SCALE_STEP)) {
+            status = AR3KConfigureHCIBaud(pConfig);      
+            if (A_FAILED(status)) {
+                break;    
+            }
+        }
+
+           /* re-enable asynchronous recv */
+        status = HCI_TransportEnableDisableAsyncRecv(pConfig->pHCIDev,TRUE);
+        if (A_FAILED(status)) {
+            break;    
+        }     
+    
+    
+    } while (FALSE);   
+    
+  
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("AR3K Config: Cleanup Complete (status = %d) \n",status));
+    
+    return status;
+}
+
diff --git a/drivers/net/ath6kl/miscdrv/ar3kps/ar3kpsconfig.c b/drivers/net/ath6kl/miscdrv/ar3kps/ar3kpsconfig.c
new file mode 100644
index 00000000000..29b8ab44ea4
--- /dev/null
+++ b/drivers/net/ath6kl/miscdrv/ar3kps/ar3kpsconfig.c
@@ -0,0 +1,572 @@
+/*
+ * Copyright (c) 2004-2010 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ * This file implements the Atheros PS and patch downloaded for HCI UART Transport driver.
+ * This file can be used for HCI SDIO transport implementation for AR6002 with HCI_TRANSPORT_SDIO
+ * defined.
+ *
+ *
+ * ar3kcpsconfig.c
+ *
+ *
+ *
+ * The software source and binaries included in this development package are
+ * licensed, not sold. You, or your company, received the package under one
+ * or more license agreements. The rights granted to you are specifically
+ * listed in these license agreement(s). All other rights remain with Atheros
+ * Communications, Inc., its subsidiaries, or the respective owner including
+ * those listed on the included copyright notices..  Distribution of any
+ * portion of this package must be in strict compliance with the license
+ * agreement(s) terms.
+ *
+ *
+ *
+ */
+
+
+
+#include "ar3kpsconfig.h"
+#ifndef HCI_TRANSPORT_SDIO
+#include "hci_ath.h"
+#include "hci_uart.h"
+#endif /* #ifndef HCI_TRANSPORT_SDIO */
+
+#define MAX_FW_PATH_LEN             50
+#define MAX_BDADDR_FORMAT_LENGTH    30
+
+/*
+ *  Structure used to send HCI packet, hci packet length and device info 
+ *  together as parameter to PSThread.
+ */
+typedef struct {
+
+    PSCmdPacket *HciCmdList;
+    A_UINT32  num_packets;
+    AR3K_CONFIG_INFO *dev;
+}HciCommandListParam;
+
+A_STATUS SendHCICommandWaitCommandComplete(AR3K_CONFIG_INFO *pConfig,
+                                           A_UINT8          *pHCICommand,
+                                           int              CmdLength,
+                                           A_UINT8          **ppEventBuffer,
+                                           A_UINT8          **ppBufferToFree);
+
+A_UINT32  Rom_Version;
+A_UINT32  Build_Version;
+extern A_BOOL BDADDR;
+
+A_STATUS getDeviceType(AR3K_CONFIG_INFO *pConfig, A_UINT32 * code);
+A_STATUS ReadVersionInfo(AR3K_CONFIG_INFO *pConfig);
+#ifndef HCI_TRANSPORT_SDIO
+
+DECLARE_WAIT_QUEUE_HEAD(PsCompleteEvent);
+DECLARE_WAIT_QUEUE_HEAD(HciEvent);
+A_UCHAR *HciEventpacket;
+rwlock_t syncLock;
+wait_queue_t Eventwait;
+
+int PSHciWritepacket(struct hci_dev*,A_UCHAR* Data, A_UINT32 len);
+extern char *bdaddr;
+#endif /* HCI_TRANSPORT_SDIO */
+
+A_STATUS write_bdaddr(AR3K_CONFIG_INFO *pConfig,A_UCHAR *bdaddr,int type);
+
+int PSSendOps(void *arg);
+
+#ifdef BT_PS_DEBUG
+void Hci_log(A_UCHAR * log_string,A_UCHAR *data,A_UINT32 len)
+{
+    int i;
+    AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("%s : ",log_string));
+    for (i = 0; i < len; i++) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("0x%02x ", data[i]));
+    }
+    AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("\n...................................\n"));
+}
+#else
+#define Hci_log(string,data,len)
+#endif /* BT_PS_DEBUG */
+
+
+
+
+A_STATUS AthPSInitialize(AR3K_CONFIG_INFO *hdev)
+{
+    A_STATUS status = A_OK;
+    if(hdev == NULL) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Invalid Device handle received\n"));
+        return A_ERROR;
+    }
+
+#ifndef HCI_TRANSPORT_SDIO
+    DECLARE_WAITQUEUE(wait, current);
+#endif /* HCI_TRANSPORT_SDIO */
+    
+
+#ifdef HCI_TRANSPORT_SDIO
+    status = PSSendOps((void*)hdev);
+#else
+    if(InitPSState(hdev) == -1) {
+        return A_ERROR;
+    }
+    allow_signal(SIGKILL);
+    add_wait_queue(&PsCompleteEvent,&wait);
+    set_current_state(TASK_INTERRUPTIBLE);
+    if(!kernel_thread(PSSendOps,(void*)hdev,CLONE_FS|CLONE_FILES|CLONE_SIGHAND|SIGCHLD)) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Kthread Failed\n"));
+        remove_wait_queue(&PsCompleteEvent,&wait);
+        return A_ERROR;
+    }
+    wait_event_interruptible(PsCompleteEvent,(PSTagMode == FALSE));
+    set_current_state(TASK_RUNNING);
+    remove_wait_queue(&PsCompleteEvent,&wait);
+
+#endif /* HCI_TRANSPORT_SDIO */
+
+
+    return status;
+    
+}
+
+int PSSendOps(void *arg) 
+{
+    int i;
+    int status = 0;
+    PSCmdPacket *HciCmdList; /* List storing the commands */
+    const struct firmware* firmware;
+    A_UINT32 numCmds;
+    A_UINT8 *event;
+    A_UINT8 *bufferToFree;
+    struct hci_dev *device;
+    A_UCHAR *buffer;
+    A_UINT32 len;
+    A_UINT32 DevType;
+    A_UCHAR *PsFileName;
+    A_UCHAR *patchFileName;
+    A_UCHAR *path = NULL;
+    A_UCHAR *config_path = NULL;
+    A_UCHAR config_bdaddr[MAX_BDADDR_FORMAT_LENGTH];
+    AR3K_CONFIG_INFO *hdev = (AR3K_CONFIG_INFO*)arg;
+    struct device *firmwareDev = NULL;
+    status = 0;
+    HciCmdList = NULL;
+#ifdef HCI_TRANSPORT_SDIO
+    device = hdev->pBtStackHCIDev; 
+    firmwareDev = device->parent;
+#else 
+    device = hdev;
+    firmwareDev = &device->dev;
+    AthEnableSyncCommandOp(TRUE);    
+#endif /* HCI_TRANSPORT_SDIO */
+    /* First verify if the controller is an FPGA or ASIC, so depending on the device type the PS file to be written will be different.
+     */
+
+    path =(A_UCHAR *)A_MALLOC(MAX_FW_PATH_LEN);
+    if(path == NULL) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Malloc failed to allocate %d bytes for path\n", MAX_FW_PATH_LEN));
+        goto complete;
+    }
+    config_path = (A_UCHAR *) A_MALLOC(MAX_FW_PATH_LEN);
+    if(config_path == NULL) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Malloc failed to allocate %d bytes for config_path\n", MAX_FW_PATH_LEN));
+        goto complete;
+    }
+
+    if(A_ERROR == getDeviceType(hdev,&DevType)) {
+        status = 1;
+        goto complete;
+    }
+    if(A_ERROR == ReadVersionInfo(hdev)) {
+        status = 1;
+        goto complete;
+    }
+
+    patchFileName = PATCH_FILE;
+    snprintf(path, MAX_FW_PATH_LEN, "%s/%xcoex/",CONFIG_PATH,Rom_Version);
+    if(DevType){
+        if(DevType == 0xdeadc0de){
+	        PsFileName =  PS_ASIC_FILE;
+	    } else{
+    		AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" FPGA Test Image : %x %x  \n",Rom_Version,Build_Version));
+                if((Rom_Version == 0x99999999) && (Build_Version == 1)){
+                        
+    			AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("FPGA Test Image : Skipping Patch File load\n"));
+    			patchFileName = NULL;
+		}
+	        PsFileName =  PS_FPGA_FILE;
+	    }
+    }
+    else{
+	    PsFileName =  PS_ASIC_FILE;
+    }
+
+    snprintf(config_path, MAX_FW_PATH_LEN, "%s%s",path,PsFileName);
+    AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("%x: FPGA/ASIC PS File Name %s\n", DevType,config_path));
+    /* Read the PS file to a dynamically allocated buffer */
+    if(A_REQUEST_FIRMWARE(&firmware,config_path,firmwareDev) < 0) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("%s: firmware file open error\n", __FUNCTION__ ));
+        status = 1;
+        goto complete;
+
+    }
+    if(NULL == firmware || firmware->size == 0) {
+        status = 1;
+        goto complete;
+    }
+    buffer = (A_UCHAR *)A_MALLOC(firmware->size);
+    if(buffer != NULL) {
+    /* Copy the read file to a local Dynamic buffer */
+        memcpy(buffer,firmware->data,firmware->size);
+        len = firmware->size;
+        A_RELEASE_FIRMWARE(firmware);
+        /* Parse the PS buffer to a global variable */
+        status = AthDoParsePS(buffer,len);
+        A_FREE(buffer);
+    } else {
+        A_RELEASE_FIRMWARE(firmware);
+    }
+
+
+    /* Read the patch file to a dynamically allocated buffer */
+	if(patchFileName != NULL)
+                snprintf(config_path,
+                         MAX_FW_PATH_LEN, "%s%s",path,patchFileName);
+	else {
+        	status = 0;
+	}
+    AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Patch File Name %s\n", config_path));
+    if((patchFileName == NULL) || (A_REQUEST_FIRMWARE(&firmware,config_path,firmwareDev) < 0)) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("%s: firmware file open error\n", __FUNCTION__ ));
+        /* 
+         *  It is not necessary that Patch file be available, continue with PS Operations if.
+         *  failed.
+         */
+        status = 0;
+
+    } else {
+        if(NULL == firmware || firmware->size == 0) {
+            status = 0;
+        } else {
+            buffer = (A_UCHAR *)A_MALLOC(firmware->size);
+            if(buffer != NULL) {
+                /* Copy the read file to a local Dynamic buffer */
+                memcpy(buffer,firmware->data,firmware->size);
+                len = firmware->size;
+                A_RELEASE_FIRMWARE(firmware);
+                /* parse and store the Patch file contents to a global variables */
+                status = AthDoParsePatch(buffer,len);
+                A_FREE(buffer);
+            } else {
+                A_RELEASE_FIRMWARE(firmware);
+            }
+        }
+    }
+
+    /* Create an HCI command list from the parsed PS and patch information */
+    AthCreateCommandList(&HciCmdList,&numCmds);
+
+    /* Form the parameter for PSSendOps() API */
+ 
+
+    /*
+     * First Send the CRC packet, 
+     * We have to continue with the PS operations only if the CRC packet has been replied with 
+     * a Command complete event with status Error.
+     */
+
+    if(SendHCICommandWaitCommandComplete
+    (hdev,
+    HciCmdList[0].Hcipacket,
+    HciCmdList[0].packetLen,
+    &event,
+    &bufferToFree) == A_OK) {
+        if(ReadPSEvent(event) == A_OK) { /* Exit if the status is success */
+            if(bufferToFree != NULL) {
+                A_FREE(bufferToFree);
+                }
+	
+#ifndef HCI_TRANSPORT_SDIO
+			if(bdaddr && bdaddr[0] !='\0') {
+				write_bdaddr(hdev,bdaddr,BDADDR_TYPE_STRING);
+			}
+#endif 
+               status = 1;
+               goto complete;
+        }
+        if(bufferToFree != NULL) {
+               A_FREE(bufferToFree);
+        }
+    } else {
+        status = 0;
+        goto complete;
+    }
+ 
+    for(i = 1; i <numCmds; i++) {
+    
+        if(SendHCICommandWaitCommandComplete
+        (hdev,
+        HciCmdList[i].Hcipacket,
+        HciCmdList[i].packetLen,
+        &event,
+        &bufferToFree) == A_OK) {
+            if(ReadPSEvent(event) != A_OK) { /* Exit if the status is success */
+                if(bufferToFree != NULL) {
+                    A_FREE(bufferToFree);
+                    }
+                   status = 1;
+                    goto complete;
+            }
+            if(bufferToFree != NULL) {
+                   A_FREE(bufferToFree);
+            }
+        } else {
+            status = 0;
+            goto complete;
+        }
+    }
+#ifdef HCI_TRANSPORT_SDIO
+	if(BDADDR == FALSE)
+		if(hdev->bdaddr[0] !=0x00 ||
+		   hdev->bdaddr[1] !=0x00 ||
+		   hdev->bdaddr[2] !=0x00 ||
+		   hdev->bdaddr[3] !=0x00 ||
+		   hdev->bdaddr[4] !=0x00 ||
+		   hdev->bdaddr[5] !=0x00)
+			write_bdaddr(hdev,hdev->bdaddr,BDADDR_TYPE_HEX);
+
+#ifndef HCI_TRANSPORT_SDIO
+
+	if(bdaddr && bdaddr[0] != '\0') {
+		write_bdaddr(hdev,bdaddr,BDADDR_TYPE_STRING);
+	} else
+#endif /* HCI_TRANSPORT_SDIO */
+    /* Write BDADDR Read from OTP here */
+
+
+
+#endif
+
+	{
+		 /* Read Contents of BDADDR file if user has not provided any option */
+        snprintf(config_path,MAX_FW_PATH_LEN, "%s%s",path,BDADDR_FILE);
+    	AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Patch File Name %s\n", config_path));
+    	if(A_REQUEST_FIRMWARE(&firmware,config_path,firmwareDev) < 0) {
+        	AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("%s: firmware file open error\n", __FUNCTION__ ));
+        	status = 1;
+        	goto complete;
+    	}
+    	if(NULL == firmware || firmware->size == 0) {
+        	status = 1;
+        	goto complete;
+    	}
+	len = min(firmware->size, MAX_BDADDR_FORMAT_LENGTH - 1);
+	memcpy(config_bdaddr, firmware->data, len);
+	config_bdaddr[len] = '\0';
+	write_bdaddr(hdev,config_bdaddr,BDADDR_TYPE_STRING);
+       	A_RELEASE_FIRMWARE(firmware);
+	}
+complete:
+#ifndef HCI_TRANSPORT_SDIO
+    AthEnableSyncCommandOp(FALSE);    
+    PSTagMode = FALSE;
+    wake_up_interruptible(&PsCompleteEvent);
+#endif /* HCI_TRANSPORT_SDIO */
+    if(NULL != HciCmdList) {
+        AthFreeCommandList(&HciCmdList,numCmds);
+    }
+    if(path) {
+        A_FREE(path);
+    }
+    if(config_path) {
+        A_FREE(config_path);
+    }
+    return status;
+}
+#ifndef HCI_TRANSPORT_SDIO
+/*
+ *  This API is used to send the HCI command to controller and return
+ *  with a HCI Command Complete event.
+ *  For HCI SDIO transport, this will be internally defined. 
+ */
+A_STATUS SendHCICommandWaitCommandComplete(AR3K_CONFIG_INFO *pConfig,
+                                           A_UINT8          *pHCICommand,
+                                           int              CmdLength,
+                                           A_UINT8          **ppEventBuffer,
+                                           A_UINT8          **ppBufferToFree)
+{
+    if(CmdLength == 0) {
+        return A_ERROR;
+    }
+    Hci_log("COM Write -->",pHCICommand,CmdLength);
+    PSAcked = FALSE;
+    if(PSHciWritepacket(pConfig,pHCICommand,CmdLength) == 0) {
+        /* If the controller is not available, return Error */
+        return A_ERROR;
+    }
+    //add_timer(&psCmdTimer);
+    wait_event_interruptible(HciEvent,(PSAcked == TRUE));
+    if(NULL != HciEventpacket) {
+        *ppEventBuffer = HciEventpacket;
+        *ppBufferToFree = HciEventpacket;
+    } else {
+        /* Did not get an event from controller. return error */
+        *ppBufferToFree = NULL;
+        return A_ERROR;
+    }
+
+    return A_OK;
+}
+#endif /* HCI_TRANSPORT_SDIO */
+
+A_STATUS ReadPSEvent(A_UCHAR* Data){
+    AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" PS Event %x %x %x\n",Data[4],Data[5],Data[3]));
+                                
+    if(Data[4] == 0xFC && Data[5] == 0x00)
+    {
+         switch(Data[3]){
+             case 0x0B:
+                     return A_OK;
+                 break;
+                 case 0x0C:
+                    /* Change Baudrate */
+                        return A_OK;    
+                 break;  
+                 case 0x04:
+                     return A_OK;
+                 break;  
+		case 0x1E:
+			Rom_Version = Data[9];
+			Rom_Version = ((Rom_Version << 8) |Data[8]);
+			Rom_Version = ((Rom_Version << 8) |Data[7]);
+			Rom_Version = ((Rom_Version << 8) |Data[6]);
+
+			Build_Version = Data[13];
+			Build_Version = ((Build_Version << 8) |Data[12]);
+			Build_Version = ((Build_Version << 8) |Data[11]);
+			Build_Version = ((Build_Version << 8) |Data[10]);
+			return A_OK;
+		break;
+
+        
+                }
+    }                       
+        
+    return A_ERROR;           
+}
+int str2ba(unsigned char *str_bdaddr,unsigned char *bdaddr)
+{
+	unsigned char bdbyte[3];
+	unsigned char *str_byte = str_bdaddr;
+	int i,j;
+	unsigned char colon_present = 0;
+
+	if(NULL != strstr(str_bdaddr,":")) {
+		colon_present = 1;
+	}
+
+
+	bdbyte[2] = '\0';
+
+	for( i = 0,j = 5; i < 6; i++, j--) {
+		bdbyte[0] = str_byte[0];
+		bdbyte[1] = str_byte[1];
+		bdaddr[j] = A_STRTOL(bdbyte,NULL,16);
+		if(colon_present == 1) {
+			str_byte+=3;
+		} else {
+			str_byte+=2;
+		}
+	}
+	return 0; 
+}
+
+A_STATUS write_bdaddr(AR3K_CONFIG_INFO *pConfig,A_UCHAR *bdaddr,int type)
+{
+	A_UCHAR bdaddr_cmd[] = { 0x0B, 0xFC, 0x0A, 0x01, 0x01, 
+							0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
+
+    A_UINT8 *event;
+    A_UINT8 *bufferToFree = NULL;
+    A_STATUS result = A_ERROR;
+	int inc,outc;
+
+	if (type == BDADDR_TYPE_STRING)
+		str2ba(bdaddr,&bdaddr_cmd[7]);
+	else {
+		/* Bdaddr has to be sent as LAP first */
+		for(inc = 5 ,outc = 7; inc >=0; inc--, outc++)
+			bdaddr_cmd[outc] = bdaddr[inc];
+	}
+
+    if(A_OK == SendHCICommandWaitCommandComplete(pConfig,bdaddr_cmd,
+												sizeof(bdaddr_cmd),
+												&event,&bufferToFree)) {
+
+        if(event[4] == 0xFC && event[5] == 0x00){
+               if(event[3] == 0x0B){
+                result = A_OK;
+            }
+        }
+
+    }
+    if(bufferToFree != NULL) {
+        A_FREE(bufferToFree);
+   }
+    return result;
+
+}
+A_STATUS ReadVersionInfo(AR3K_CONFIG_INFO *pConfig)
+{
+    A_UINT8   hciCommand[] =  {0x1E,0xfc,0x00};
+    A_UINT8 *event;
+    A_UINT8 *bufferToFree = NULL;
+    A_STATUS result = A_ERROR;
+    if(A_OK == SendHCICommandWaitCommandComplete(pConfig,hciCommand,sizeof(hciCommand),&event,&bufferToFree)) {
+	result = ReadPSEvent(event);
+
+    }
+    if(bufferToFree != NULL) {
+        A_FREE(bufferToFree);
+   }
+    return result;
+}
+A_STATUS getDeviceType(AR3K_CONFIG_INFO *pConfig, A_UINT32 * code)
+{
+    A_UINT8   hciCommand[] =  {0x05,0xfc,0x05,0x00,0x00,0x00,0x00,0x04};
+    A_UINT8 *event;
+    A_UINT8 *bufferToFree = NULL;
+    A_UINT32 reg;
+    A_STATUS result = A_ERROR;
+    *code = 0;
+    hciCommand[3] = (A_UINT8)(FPGA_REGISTER & 0xFF);
+    hciCommand[4] = (A_UINT8)((FPGA_REGISTER >> 8) & 0xFF);
+    hciCommand[5] = (A_UINT8)((FPGA_REGISTER >> 16) & 0xFF);
+    hciCommand[6] = (A_UINT8)((FPGA_REGISTER >> 24) & 0xFF); 
+    if(A_OK == SendHCICommandWaitCommandComplete(pConfig,hciCommand,sizeof(hciCommand),&event,&bufferToFree)) {
+
+        if(event[4] == 0xFC && event[5] == 0x00){
+               switch(event[3]){
+                case 0x05:
+                reg = event[9];
+                reg = ((reg << 8) |event[8]);
+                reg = ((reg << 8) |event[7]);
+                reg = ((reg << 8) |event[6]);
+                *code = reg;
+                result = A_OK;
+
+                break;
+                case 0x06:
+                    //Sleep(500);
+                break;
+            }
+        }
+
+    }
+    if(bufferToFree != NULL) {
+        A_FREE(bufferToFree);
+   }
+    return result;
+}
+
+
diff --git a/drivers/net/ath6kl/miscdrv/ar3kps/ar3kpsconfig.h b/drivers/net/ath6kl/miscdrv/ar3kps/ar3kpsconfig.h
new file mode 100644
index 00000000000..4e5b7bfc0ea
--- /dev/null
+++ b/drivers/net/ath6kl/miscdrv/ar3kps/ar3kpsconfig.h
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2004-2010 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ * This file defines the symbols exported by Atheros PS and patch download module.
+ * define the constant HCI_TRANSPORT_SDIO if the module is being used for HCI SDIO transport.
+ * defined.
+ *
+ *
+ * ar3kcpsconfig.h
+ *
+ *
+ *
+ * The software source and binaries included in this development package are
+ * licensed, not sold. You, or your company, received the package under one
+ * or more license agreements. The rights granted to you are specifically
+ * listed in these license agreement(s). All other rights remain with Atheros
+ * Communications, Inc., its subsidiaries, or the respective owner including
+ * those listed on the included copyright notices..  Distribution of any
+ * portion of this package must be in strict compliance with the license
+ * agreement(s) terms.
+ *
+ *
+ *
+ */
+
+
+
+#ifndef __AR3KPSCONFIG_H
+#define __AR3KPSCONFIG_H
+
+/* 
+ * Define the flag HCI_TRANSPORT_SDIO and undefine HCI_TRANSPORT_UART if the transport being used is SDIO.
+ */
+#undef HCI_TRANSPORT_UART
+
+#include <linux/fs.h>
+#include <linux/errno.h>
+#include <linux/signal.h>
+
+
+#include <linux/ioctl.h>
+#include <linux/firmware.h>
+
+
+#include <net/bluetooth/bluetooth.h>
+#include <net/bluetooth/hci_core.h>
+
+#include "ar3kpsparser.h"
+
+#define FPGA_REGISTER	0x4FFC
+#define BDADDR_TYPE_STRING	0
+#define BDADDR_TYPE_HEX		1
+#define CONFIG_PATH	  "ar3k"
+
+#define PS_ASIC_FILE      "PS_ASIC.pst"
+#define PS_FPGA_FILE      "PS_FPGA.pst"
+
+#define PATCH_FILE      "RamPatch.txt"
+#define BDADDR_FILE "ar3kbdaddr.pst"
+
+#define ROM_VER_AR3001_3_1_0	30000
+#define ROM_VER_AR3001_3_1_1	30101	
+
+
+#ifndef HCI_TRANSPORT_SDIO
+#define AR3K_CONFIG_INFO        struct hci_dev
+extern wait_queue_head_t HciEvent;
+extern wait_queue_t Eventwait;
+extern A_UCHAR *HciEventpacket;
+#endif /* #ifndef HCI_TRANSPORT_SDIO */
+
+A_STATUS AthPSInitialize(AR3K_CONFIG_INFO *hdev);
+A_STATUS ReadPSEvent(A_UCHAR* Data);
+#endif /* __AR3KPSCONFIG_H */
diff --git a/drivers/net/ath6kl/miscdrv/ar3kps/ar3kpsparser.c b/drivers/net/ath6kl/miscdrv/ar3kps/ar3kpsparser.c
new file mode 100644
index 00000000000..8dce0542282
--- /dev/null
+++ b/drivers/net/ath6kl/miscdrv/ar3kps/ar3kpsparser.c
@@ -0,0 +1,969 @@
+/*
+ * Copyright (c) 2004-2010 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ * This file implements the Atheros PS and patch parser.
+ * It implements APIs to parse data buffer with patch and PS information and convert it to HCI commands.
+ *
+ *
+ *
+ * ar3kpsparser.c
+ *
+ *
+ *
+ * The software source and binaries included in this development package are
+ * licensed, not sold. You, or your company, received the package under one
+ * or more license agreements. The rights granted to you are specifically
+ * listed in these license agreement(s). All other rights remain with Atheros
+ * Communications, Inc., its subsidiaries, or the respective owner including
+ * those listed on the included copyright notices..  Distribution of any
+ * portion of this package must be in strict compliance with the license
+ * agreement(s) terms.
+ *
+ *
+ *
+ */
+
+
+#include "ar3kpsparser.h"
+
+#include <linux/ctype.h>
+#include <linux/kernel.h>
+
+#define BD_ADDR_SIZE            6
+#define WRITE_PATCH             8
+#define ENABLE_PATCH            11
+#define PS_RESET                2
+#define PS_WRITE                1
+#define PS_VERIFY_CRC           9
+#define CHANGE_BDADDR           15
+
+#define HCI_COMMAND_HEADER      7
+
+#define HCI_EVENT_SIZE          7
+
+#define WRITE_PATCH_COMMAND_STATUS_OFFSET 5
+
+#define PS_RAM_SIZE	2048
+
+#define RAM_PS_REGION           (1<<0)
+#define RAM_PATCH_REGION        (1<<1)
+#define RAMPS_MAX_PS_DATA_PER_TAG         20000
+#define MAX_RADIO_CFG_TABLE_SIZE  244
+#define RAMPS_MAX_PS_TAGS_PER_FILE        50
+
+#define PS_MAX_LEN                        500 
+#define LINE_SIZE_MAX                     (PS_MAX_LEN *2) 
+
+/* Constant values used by parser */
+#define BYTES_OF_PS_DATA_PER_LINE         16
+#define RAMPS_MAX_PS_DATA_PER_TAG         20000
+
+
+/* Number pf PS/Patch entries in an HCI packet */
+#define MAX_BYTE_LENGTH                   244
+
+#define SKIP_BLANKS(str) while (*str == ' ') str++
+
+enum MinBootFileFormatE
+{
+   MB_FILEFORMAT_RADIOTBL,
+   MB_FILEFORMAT_PATCH,
+   MB_FILEFORMAT_COEXCONFIG
+};
+
+enum RamPsSection
+{
+   RAM_PS_SECTION,
+   RAM_PATCH_SECTION,
+   RAM_DYN_MEM_SECTION
+};
+
+enum eType {
+   eHex,
+   edecimal
+};
+
+
+typedef struct tPsTagEntry
+{
+   A_UINT32   TagId;
+   A_UINT32   TagLen;
+   A_UINT8    *TagData;
+} tPsTagEntry, *tpPsTagEntry;
+
+typedef struct tRamPatch
+{
+   A_UINT16   Len;
+   A_UINT8    * Data;
+} tRamPatch, *ptRamPatch;
+
+
+
+typedef struct ST_PS_DATA_FORMAT {
+   enum eType   eDataType;
+   A_BOOL    bIsArray;
+}ST_PS_DATA_FORMAT;
+
+typedef struct ST_READ_STATUS {
+    unsigned uTagID;
+    unsigned uSection;
+    unsigned uLineCount;
+    unsigned uCharCount;
+    unsigned uByteCount;
+}ST_READ_STATUS;
+
+
+/* Stores the number of PS Tags */
+static A_UINT32 Tag_Count = 0;
+
+/* Stores the number of patch commands */
+static A_UINT32 Patch_Count = 0;
+static A_UINT32 Total_tag_lenght = 0;
+A_BOOL BDADDR = FALSE;
+A_UINT32      StartTagId;
+
+tPsTagEntry PsTagEntry[RAMPS_MAX_PS_TAGS_PER_FILE];
+tRamPatch   RamPatch[MAX_NUM_PATCH_ENTRY];
+
+
+A_STATUS AthParseFilesUnified(A_UCHAR *srcbuffer,A_UINT32 srclen, int FileFormat);
+char AthReadChar(A_UCHAR *buffer, A_UINT32 len,A_UINT32 *pos);
+char * AthGetLine(char * buffer, int maxlen, A_UCHAR *srcbuffer,A_UINT32 len,A_UINT32 *pos);
+static A_STATUS AthPSCreateHCICommand(A_UCHAR Opcode, A_UINT32 Param1,PSCmdPacket *PSPatchPacket,A_UINT32 *index);
+
+/* Function to reads the next character from the input buffer */
+char AthReadChar(A_UCHAR *buffer, A_UINT32 len,A_UINT32 *pos) 
+{
+    char Ch;
+    if(buffer == NULL || *pos >=len )
+    {
+        return '\0';
+    } else {
+        Ch = buffer[*pos];
+        (*pos)++;
+        return Ch;
+    }
+}
+/* PS parser helper function */
+unsigned int uGetInputDataFormat(char* pCharLine, ST_PS_DATA_FORMAT *pstFormat) 
+{
+    if(pCharLine[0] != '[') {
+        pstFormat->eDataType = eHex;
+        pstFormat->bIsArray = true;
+        return 0;
+    }
+    switch(pCharLine[1]) {
+        case 'H':
+        case 'h':
+        if(pCharLine[2]==':') {
+            if((pCharLine[3]== 'a') || (pCharLine[3]== 'A')) {
+                if(pCharLine[4] == ']') {
+                    pstFormat->eDataType = eHex;
+                    pstFormat->bIsArray = true;
+                    pCharLine += 5;
+                    return 0;
+                }
+                else {
+                       AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Illegal Data format\n")); //[H:A
+                    return 1;
+                }
+            }
+            if((pCharLine[3]== 'S') || (pCharLine[3]== 's')) {
+                if(pCharLine[4] == ']') {
+                    pstFormat->eDataType = eHex;
+                    pstFormat->bIsArray = false;
+                    pCharLine += 5;
+                    return 0;
+                }
+                else {
+                       AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Illegal Data format\n")); //[H:A
+                    return 1;
+                }
+            }
+            else if(pCharLine[3] == ']') {         //[H:]
+                pstFormat->eDataType = eHex;
+                pstFormat->bIsArray = true;
+                pCharLine += 4;
+                return 0;
+            }
+            else {                            //[H:
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Illegal Data format\n"));
+                return 1;                    
+            }
+        }
+        else if(pCharLine[2]==']') {    //[H]
+            pstFormat->eDataType = eHex;
+            pstFormat->bIsArray = true;
+            pCharLine += 3;
+            return 0;
+        }
+        else {                      //[H
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Illegal Data format\n"));
+            return 1;            
+        }
+        break;
+
+        case 'A':
+        case 'a':
+        if(pCharLine[2]==':') {
+            if((pCharLine[3]== 'h') || (pCharLine[3]== 'H')) {
+                if(pCharLine[4] == ']') {
+                    pstFormat->eDataType = eHex;
+                    pstFormat->bIsArray = true;
+                    pCharLine += 5;
+                    return 0;
+                }
+                else {
+                    AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Illegal Data format 1\n")); //[A:H
+                    return 1;
+                }
+             }
+            else if(pCharLine[3]== ']') {         //[A:]
+                pstFormat->eDataType = eHex;
+                pstFormat->bIsArray = true;
+                pCharLine += 4;
+                return 0;
+            }
+            else {                            //[A:
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Illegal Data format 2\n"));
+                return 1;                    
+            }
+        }
+        else if(pCharLine[2]==']') {    //[H]
+            pstFormat->eDataType = eHex;
+            pstFormat->bIsArray = true;
+            pCharLine += 3;
+            return 0;
+        }
+        else {                      //[H
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Illegal Data format 3\n"));
+            return 1;            
+        }
+        break;
+
+        case 'S':
+        case 's':
+        if(pCharLine[2]==':') {
+            if((pCharLine[3]== 'h') || (pCharLine[3]== 'H')) {
+                if(pCharLine[4] == ']') {
+                    pstFormat->eDataType = eHex;
+                    pstFormat->bIsArray = true;
+                    pCharLine += 5;
+                    return 0;
+                }
+                else {
+                    AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Illegal Data format 5\n")); //[A:H
+                    return 1;
+                }
+             }
+            else if(pCharLine[3]== ']') {         //[A:]
+                pstFormat->eDataType = eHex;
+                pstFormat->bIsArray = true;
+                pCharLine += 4;
+                return 0;
+            }
+            else {                            //[A:
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Illegal Data format 6\n"));
+                return 1;                    
+            }
+        }
+        else if(pCharLine[2]==']') {    //[H]
+            pstFormat->eDataType = eHex;
+            pstFormat->bIsArray = true;
+            pCharLine += 3;
+            return 0;
+        }
+        else {                      //[H
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Illegal Data format 7\n"));
+            return 1;            
+        }
+        break;
+    
+        default:
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Illegal Data format 8\n"));
+        return 1;
+    }
+}
+
+unsigned int uReadDataInSection(char *pCharLine, ST_PS_DATA_FORMAT stPS_DataFormat)
+{
+    char *pTokenPtr = pCharLine;
+
+    if(pTokenPtr[0] == '[') {
+        while(pTokenPtr[0] != ']' && pTokenPtr[0] != '\0') {
+            pTokenPtr++;
+        }
+        if(pTokenPtr[0] == '\0') {
+            return (0x0FFF);
+        }
+        pTokenPtr++;
+            
+
+    }
+    if(stPS_DataFormat.eDataType == eHex) {
+        if(stPS_DataFormat.bIsArray == true) {
+            //Not implemented
+            return (0x0FFF);
+        }
+        else {
+            return (A_STRTOL(pTokenPtr, NULL, 16));
+        }
+    }
+    else {
+        //Not implemented
+        return (0x0FFF);
+    }
+}
+A_STATUS AthParseFilesUnified(A_UCHAR *srcbuffer,A_UINT32 srclen, int FileFormat)
+{
+   char     *Buffer;
+   char     *pCharLine;
+   A_UINT8    TagCount;
+   A_UINT16   ByteCount;
+   A_UINT8    ParseSection=RAM_PS_SECTION;
+   A_UINT32 pos;
+
+
+
+   int uReadCount;
+   ST_PS_DATA_FORMAT stPS_DataFormat;
+   ST_READ_STATUS   stReadStatus = {0, 0, 0,0};
+   pos = 0;
+   Buffer = NULL;
+
+   if (srcbuffer == NULL || srclen == 0)
+   {
+      AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Could not open .\n"));
+      return A_ERROR;
+   }
+   TagCount = 0;
+   ByteCount = 0;
+   Buffer = A_MALLOC(LINE_SIZE_MAX + 1);
+   if(NULL == Buffer) {
+       return A_ERROR;
+   }
+   if (FileFormat == MB_FILEFORMAT_PATCH)
+   {
+      int LineRead = 0;
+      while((pCharLine = AthGetLine(Buffer, LINE_SIZE_MAX, srcbuffer,srclen,&pos)) != NULL)
+      {
+
+         SKIP_BLANKS(pCharLine);
+
+         // Comment line or empty line
+         if ((pCharLine[0] == '/') && (pCharLine[1] == '/'))
+         {
+            continue;
+         }
+         
+         if ((pCharLine[0] == '#')) { 
+             if (stReadStatus.uSection != 0)
+             {
+                 AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("error\n"));
+                 if(Buffer != NULL) {
+                     A_FREE(Buffer);
+                 }
+                 return A_ERROR;
+             }
+             else {
+                 stReadStatus.uSection = 1;
+                 continue;
+             }
+         }
+         if ((pCharLine[0] == '/') && (pCharLine[1] == '*'))
+         {
+            pCharLine+=2;
+            SKIP_BLANKS(pCharLine);
+
+            if(!strncmp(pCharLine,"PA",2)||!strncmp(pCharLine,"Pa",2)||!strncmp(pCharLine,"pa",2))
+                ParseSection=RAM_PATCH_SECTION;
+
+            if(!strncmp(pCharLine,"DY",2)||!strncmp(pCharLine,"Dy",2)||!strncmp(pCharLine,"dy",2))
+                ParseSection=RAM_DYN_MEM_SECTION;
+
+            if(!strncmp(pCharLine,"PS",2)||!strncmp(pCharLine,"Ps",2)||!strncmp(pCharLine,"ps",2))
+                ParseSection=RAM_PS_SECTION;
+
+            LineRead = 0;
+            stReadStatus.uSection = 0;
+
+            continue;
+    }
+         
+         switch(ParseSection)
+         {
+             case RAM_PS_SECTION:
+             {
+                 if (stReadStatus.uSection == 1)  //TagID
+                 {
+                    SKIP_BLANKS(pCharLine);
+                    if(uGetInputDataFormat(pCharLine, &stPS_DataFormat)) {
+                        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("uGetInputDataFormat fail\n"));
+                     if(Buffer != NULL) {
+                             A_FREE(Buffer);
+                     }
+                        return A_ERROR;
+                    }    
+                    //pCharLine +=5;
+                    PsTagEntry[TagCount].TagId = uReadDataInSection(pCharLine, stPS_DataFormat);                            
+                    AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" TAG ID %d \n",PsTagEntry[TagCount].TagId));
+
+                    //AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("tag # %x\n", PsTagEntry[TagCount].TagId);
+                    if (TagCount == 0)
+                    {
+                       StartTagId = PsTagEntry[TagCount].TagId;
+                    }
+                    stReadStatus.uSection = 2;
+                 }
+                 else if (stReadStatus.uSection == 2) //TagLength
+                 {
+            
+                    if(uGetInputDataFormat(pCharLine, &stPS_DataFormat)) {
+                        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("uGetInputDataFormat fail \n"));
+                     if(Buffer != NULL) {
+                             A_FREE(Buffer);
+                     }
+                        return A_ERROR;
+                    }
+                    //pCharLine +=5;
+                    ByteCount = uReadDataInSection(pCharLine, stPS_DataFormat);
+
+                    //AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("tag length %x\n", ByteCount));
+                    if (ByteCount > LINE_SIZE_MAX/2)
+                    {
+                     if(Buffer != NULL) {
+                             A_FREE(Buffer);
+                     }
+                       return A_ERROR;
+                    }
+                    PsTagEntry[TagCount].TagLen = ByteCount;
+                    PsTagEntry[TagCount].TagData = (A_UINT8*)A_MALLOC(ByteCount);
+                    AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" TAG Length %d  Tag Index %d \n",PsTagEntry[TagCount].TagLen,TagCount));
+                    stReadStatus.uSection = 3;
+                    stReadStatus.uLineCount = 0;
+                 }
+                 else if( stReadStatus.uSection == 3) {  //Data
+
+                    if(stReadStatus.uLineCount == 0) {
+                        if(uGetInputDataFormat(pCharLine,&stPS_DataFormat)) {
+                            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("uGetInputDataFormat Fail\n"));
+                            if(Buffer != NULL) {
+                                 A_FREE(Buffer);
+                         }
+                            return A_ERROR;
+                        }
+                        //pCharLine +=5;
+                    }
+           SKIP_BLANKS(pCharLine);
+                    stReadStatus.uCharCount = 0;
+            if(pCharLine[stReadStatus.uCharCount] == '[') {
+            while(pCharLine[stReadStatus.uCharCount] != ']' && pCharLine[stReadStatus.uCharCount] != '\0' ) {
+                            stReadStatus.uCharCount++;
+            }
+            if(pCharLine[stReadStatus.uCharCount] == ']' ) {
+                            stReadStatus.uCharCount++;
+            } else {
+                            stReadStatus.uCharCount = 0;
+            }
+            }
+                    uReadCount = (ByteCount > BYTES_OF_PS_DATA_PER_LINE)? BYTES_OF_PS_DATA_PER_LINE: ByteCount;
+                    //AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" "));
+                    if((stPS_DataFormat.eDataType == eHex) && stPS_DataFormat.bIsArray == true) {
+                       while(uReadCount > 0) {
+                           PsTagEntry[TagCount].TagData[stReadStatus.uByteCount] =
+                                                     (A_UINT8)(hex_to_bin(pCharLine[stReadStatus.uCharCount]) << 4)
+                                                     | (A_UINT8)(hex_to_bin(pCharLine[stReadStatus.uCharCount + 1]));
+
+                           PsTagEntry[TagCount].TagData[stReadStatus.uByteCount+1] =
+                                                     (A_UINT8)(hex_to_bin(pCharLine[stReadStatus.uCharCount + 3]) << 4)
+                                                     | (A_UINT8)(hex_to_bin(pCharLine[stReadStatus.uCharCount + 4]));
+
+                           stReadStatus.uCharCount += 6; // read two bytes, plus a space;
+                           stReadStatus.uByteCount += 2;
+                           uReadCount -= 2;
+                       }
+                       if(ByteCount > BYTES_OF_PS_DATA_PER_LINE) {
+                              ByteCount -= BYTES_OF_PS_DATA_PER_LINE;
+                       }
+                       else {
+                          ByteCount = 0;
+                       }
+                    }
+                    else {
+                        //to be implemented
+                    }
+
+                    stReadStatus.uLineCount++;
+                    
+                    if(ByteCount == 0) {
+                        stReadStatus.uSection = 0;
+                        stReadStatus.uCharCount = 0;
+                        stReadStatus.uLineCount = 0;
+                        stReadStatus.uByteCount = 0;
+                    }
+                    else { 
+                        stReadStatus.uCharCount = 0;
+                    }
+
+                    if((stReadStatus.uSection == 0)&&(++TagCount == RAMPS_MAX_PS_TAGS_PER_FILE))
+                    {
+                       AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("\n Buffer over flow PS File too big!!!"));
+                       if(Buffer != NULL) {
+                           A_FREE(Buffer);
+                       }
+                       return A_ERROR;
+                       //Sleep (3000);
+                       //exit(1);
+                    }
+        
+                 }
+             }
+
+             break;
+             default:
+             {
+                   if(Buffer != NULL) {
+                       A_FREE(Buffer);
+                   }
+                   return A_ERROR;
+             }
+             break;
+         }
+         LineRead++;
+      }
+      Tag_Count = TagCount;
+      AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Number of Tags %d\n", Tag_Count));
+   }
+
+
+   if (TagCount > RAMPS_MAX_PS_TAGS_PER_FILE)
+   {
+
+      if(Buffer != NULL) {
+           A_FREE(Buffer);
+      }
+      return A_ERROR;
+   }
+
+   if(Buffer != NULL) {
+        A_FREE(Buffer);
+   }
+   return A_OK;
+
+}
+
+
+
+/********************/
+
+
+A_STATUS GetNextTwoChar(A_UCHAR *srcbuffer,A_UINT32 len, A_UINT32 *pos, char * buffer)
+{
+    unsigned char ch;
+
+    ch = AthReadChar(srcbuffer,len,pos);
+    if(ch != '\0' && isxdigit(ch)) {
+        buffer[0] =  ch;
+    } else 
+    {
+        return A_ERROR;
+    }
+    ch = AthReadChar(srcbuffer,len,pos);
+    if(ch != '\0' && isxdigit(ch)) {
+        buffer[1] =  ch;
+    } else 
+    {
+        return A_ERROR;
+    }
+    return A_OK;
+}
+
+A_STATUS AthDoParsePatch(A_UCHAR *patchbuffer, A_UINT32 patchlen)
+{
+
+    char  Byte[3];
+    char   Line[MAX_BYTE_LENGTH + 1];
+    int    ByteCount,ByteCount_Org;
+    int count;
+    int i,j,k;
+    int data;
+    A_UINT32 filepos;
+    Byte[2] = '\0';
+    j = 0;
+    filepos = 0;
+    Patch_Count = 0;
+
+    while(NULL != AthGetLine(Line,MAX_BYTE_LENGTH,patchbuffer,patchlen,&filepos)) {
+        if(strlen(Line) <= 1 || !isxdigit(Line[0])) {
+            continue;
+        } else {
+            break;
+        }
+    }
+    ByteCount = A_STRTOL(Line, NULL, 16);
+    ByteCount_Org = ByteCount;
+
+    while(ByteCount > MAX_BYTE_LENGTH){
+
+        /* Handle case when the number of patch buffer is more than the 20K */
+        if(MAX_NUM_PATCH_ENTRY == Patch_Count) {
+            for(i = 0; i < Patch_Count; i++) {
+                A_FREE(RamPatch[i].Data);
+            }
+            return A_ERROR;
+        }
+        RamPatch[Patch_Count].Len= MAX_BYTE_LENGTH;
+        RamPatch[Patch_Count].Data = (A_UINT8*)A_MALLOC(MAX_BYTE_LENGTH);
+        Patch_Count ++;
+
+
+        ByteCount= ByteCount - MAX_BYTE_LENGTH;
+    }
+
+    RamPatch[Patch_Count].Len= (ByteCount & 0xFF);
+    if(ByteCount != 0) {
+        RamPatch[Patch_Count].Data = (A_UINT8*)A_MALLOC(ByteCount);
+        Patch_Count ++;
+    }
+    count = 0;
+    while(ByteCount_Org > MAX_BYTE_LENGTH){
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" Index [%d]\n",j));
+        for (i = 0,k=0; i < MAX_BYTE_LENGTH*2; i += 2,k++,count +=2) {
+            if(GetNextTwoChar(patchbuffer,patchlen,&filepos,Byte) == A_ERROR) {
+                return A_ERROR;
+            }
+            data = A_STRTOUL(&Byte[0], NULL, 16);
+            RamPatch[j].Data[k] = (data & 0xFF);
+
+
+        }
+        j++;
+        ByteCount_Org = ByteCount_Org - MAX_BYTE_LENGTH;
+    }
+    if(j == 0){
+        j++;
+    }
+    AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" Index [%d]\n",j));
+    for (k=0; k < ByteCount_Org; i += 2,k++,count+=2) {
+        if(GetNextTwoChar(patchbuffer,patchlen,&filepos,Byte) == A_ERROR) {
+            return A_ERROR;
+        }
+        data = A_STRTOUL(Byte, NULL, 16);
+        RamPatch[j].Data[k] = (data & 0xFF);
+
+
+    }
+    return A_OK;
+}
+
+
+/********************/
+A_STATUS AthDoParsePS(A_UCHAR *srcbuffer, A_UINT32 srclen)
+{
+    A_STATUS status;
+    int i;
+    A_BOOL BDADDR_Present = A_ERROR;
+
+    Tag_Count = 0;
+
+    Total_tag_lenght = 0;
+    BDADDR = FALSE;
+
+
+    status = A_ERROR;
+
+    if(NULL != srcbuffer && srclen != 0)
+    {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("File Open Operation Successful\n"));
+
+        status = AthParseFilesUnified(srcbuffer,srclen,MB_FILEFORMAT_PATCH); 
+    }
+    
+
+
+        if(Tag_Count == 0){
+                Total_tag_lenght = 10;
+
+        }
+        else{
+                for(i=0; i<Tag_Count; i++){
+                        if(PsTagEntry[i].TagId == 1){
+                                BDADDR_Present = A_OK;
+                                AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BD ADDR is present in Patch File \r\n"));
+
+                        }
+                        if(PsTagEntry[i].TagLen % 2 == 1){
+                                Total_tag_lenght = Total_tag_lenght + PsTagEntry[i].TagLen + 1;
+                        }
+                        else{
+                                Total_tag_lenght = Total_tag_lenght + PsTagEntry[i].TagLen;
+                        }
+
+                }
+        }
+
+        if(Tag_Count > 0 && !BDADDR_Present){
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BD ADDR is not present adding 10 extra bytes \r\n"));
+                Total_tag_lenght=Total_tag_lenght + 10;
+        }
+        Total_tag_lenght = Total_tag_lenght+ 10 + (Tag_Count*4);
+    AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("** Total Length %d\n",Total_tag_lenght));
+
+
+    return status;
+}
+char * AthGetLine(char * buffer, int maxlen, A_UCHAR *srcbuffer,A_UINT32 len,A_UINT32 *pos)
+{
+
+    int count;
+    static short flag;
+    char CharRead;
+    count = 0;
+    flag = A_ERROR;
+
+    do
+    {
+        CharRead = AthReadChar(srcbuffer,len,pos);
+        if( CharRead == '\0' ) {
+            buffer[count+1] = '\0';
+            if(count == 0) {
+                return NULL;
+            }
+            else {
+                return buffer;
+            }
+        }
+
+        if(CharRead == 13) {
+        } else if(CharRead == 10) {
+            buffer[count] ='\0';  
+            flag = A_ERROR;
+            return buffer;
+        }else {
+            buffer[count++] = CharRead;
+        }
+
+    }
+    while(count < maxlen-1 && CharRead != '\0');
+    buffer[count] = '\0';
+
+    return buffer;
+}
+
+static void LoadHeader(A_UCHAR *HCI_PS_Command,A_UCHAR opcode,int length,int index){
+
+        HCI_PS_Command[0]= 0x0B;
+        HCI_PS_Command[1]= 0xFC;
+        HCI_PS_Command[2]= length + 4;
+        HCI_PS_Command[3]= opcode;
+        HCI_PS_Command[4]= (index & 0xFF);
+        HCI_PS_Command[5]= ((index>>8) & 0xFF);
+        HCI_PS_Command[6]= length;
+}
+
+/////////////////////////
+//
+int AthCreateCommandList(PSCmdPacket **HciPacketList, A_UINT32 *numPackets)
+{
+
+    A_UINT8 count;
+    A_UINT32 NumcmdEntry = 0; 
+
+    A_UINT32 Crc = 0;
+    *numPackets = 0;
+
+
+    if(Patch_Count > 0)
+            Crc |= RAM_PATCH_REGION;
+    if(Tag_Count > 0)
+            Crc |= RAM_PS_REGION;
+    AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("PS Thread Started CRC %x Patch Count %d  Tag Count %d \n",Crc,Patch_Count,Tag_Count));
+    
+    if(Patch_Count || Tag_Count ){
+    NumcmdEntry+=(2 + Patch_Count + Tag_Count); /* CRC Packet + PS Reset Packet  + Patch List + PS List*/
+        if(Patch_Count > 0) {
+            NumcmdEntry++; /* Patch Enable Command */
+        }
+           AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Num Cmd Entries %d Size  %d  \r\n",NumcmdEntry,(A_UINT32)sizeof(PSCmdPacket) * NumcmdEntry));
+        (*HciPacketList) = A_MALLOC(sizeof(PSCmdPacket) * NumcmdEntry);
+    if(NULL == *HciPacketList) {
+               AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("memory allocation failed  \r\n"));
+        }
+        AthPSCreateHCICommand(PS_VERIFY_CRC,Crc,*HciPacketList,numPackets);
+        if(Patch_Count > 0){
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("*** Write Patch**** \r\n"));
+                AthPSCreateHCICommand(WRITE_PATCH,Patch_Count,*HciPacketList,numPackets);
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("*** Enable Patch**** \r\n"));
+                AthPSCreateHCICommand(ENABLE_PATCH,0,*HciPacketList,numPackets);
+        }
+
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("*** PS Reset**** %d[0x%x] \r\n",PS_RAM_SIZE,PS_RAM_SIZE));
+		AthPSCreateHCICommand(PS_RESET,PS_RAM_SIZE,*HciPacketList,numPackets);
+        if(Tag_Count > 0){
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("*** PS Write**** \r\n"));
+                AthPSCreateHCICommand(PS_WRITE,Tag_Count,*HciPacketList,numPackets);
+        }    
+    }
+    if(!BDADDR){
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BD ADDR not present \r\n"));
+    
+    }
+    for(count = 0; count < Patch_Count; count++) {
+
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Freeing Patch Buffer %d \r\n",count));
+        A_FREE(RamPatch[Patch_Count].Data);
+    }
+
+    for(count = 0; count < Tag_Count; count++) {
+
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Freeing PS Buffer %d \r\n",count));
+        A_FREE(PsTagEntry[count].TagData);
+    }
+
+/* 
+ *  SDIO Transport uses synchronous mode of data transfer 
+ *  So, AthPSOperations() call returns only after receiving the 
+ *  command complete event.
+ */
+    return *numPackets;
+}
+
+
+////////////////////////
+
+/////////////
+static A_STATUS AthPSCreateHCICommand(A_UCHAR Opcode, A_UINT32 Param1,PSCmdPacket *PSPatchPacket,A_UINT32 *index)
+{
+    A_UCHAR *HCI_PS_Command;
+    A_UINT32 Length;
+    int i,j;
+    
+    switch(Opcode)
+    {
+    case WRITE_PATCH:
+
+
+         for(i=0;i< Param1;i++){
+
+             HCI_PS_Command = (A_UCHAR *) A_MALLOC(RamPatch[i].Len+HCI_COMMAND_HEADER);
+             AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Allocated Buffer Size %d\n",RamPatch[i].Len+HCI_COMMAND_HEADER));
+                 if(HCI_PS_Command == NULL){
+                     AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("MALLOC Failed\r\n"));
+                         return A_ERROR;
+                 }
+                 memset (HCI_PS_Command, 0, RamPatch[i].Len+HCI_COMMAND_HEADER);
+                 LoadHeader(HCI_PS_Command,Opcode,RamPatch[i].Len,i);
+                 for(j=0;j<RamPatch[i].Len;j++){
+                        HCI_PS_Command[HCI_COMMAND_HEADER+j]=RamPatch[i].Data[j];
+                 }
+                 PSPatchPacket[*index].Hcipacket = HCI_PS_Command;
+                 PSPatchPacket[*index].packetLen = RamPatch[i].Len+HCI_COMMAND_HEADER;
+                 (*index)++;
+
+          
+         }
+
+    break;
+
+    case ENABLE_PATCH:
+
+
+         Length = 0;
+         i= 0;
+         HCI_PS_Command = (A_UCHAR *) A_MALLOC(Length+HCI_COMMAND_HEADER);
+         if(HCI_PS_Command == NULL){
+             AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("MALLOC Failed\r\n"));
+            return A_ERROR;
+         }
+
+         memset (HCI_PS_Command, 0, Length+HCI_COMMAND_HEADER);
+         LoadHeader(HCI_PS_Command,Opcode,Length,i);
+         PSPatchPacket[*index].Hcipacket = HCI_PS_Command;
+         PSPatchPacket[*index].packetLen = Length+HCI_COMMAND_HEADER;
+         (*index)++;
+
+    break;
+
+    case PS_RESET:
+                        Length = 0x06;
+                        i=0;
+                        HCI_PS_Command = (A_UCHAR *) A_MALLOC(Length+HCI_COMMAND_HEADER);
+                        if(HCI_PS_Command == NULL){
+                                AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("MALLOC Failed\r\n"));
+                                return A_ERROR;
+                        }
+                        memset (HCI_PS_Command, 0, Length+HCI_COMMAND_HEADER);
+                        LoadHeader(HCI_PS_Command,Opcode,Length,i);
+                        HCI_PS_Command[7]= 0x00;
+                        HCI_PS_Command[Length+HCI_COMMAND_HEADER -2]= (Param1 & 0xFF);
+                        HCI_PS_Command[Length+HCI_COMMAND_HEADER -1]= ((Param1 >>  8) & 0xFF);
+                 PSPatchPacket[*index].Hcipacket = HCI_PS_Command;
+                 PSPatchPacket[*index].packetLen = Length+HCI_COMMAND_HEADER;
+                 (*index)++;
+
+    break;
+
+    case PS_WRITE:
+                       for(i=0;i< Param1;i++){
+                                if(PsTagEntry[i].TagId ==1)
+                                        BDADDR = TRUE;
+
+                                HCI_PS_Command = (A_UCHAR *) A_MALLOC(PsTagEntry[i].TagLen+HCI_COMMAND_HEADER);
+                                if(HCI_PS_Command == NULL){
+                                        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("MALLOC Failed\r\n"));
+                                        return A_ERROR;
+                                }
+
+                                memset (HCI_PS_Command, 0, PsTagEntry[i].TagLen+HCI_COMMAND_HEADER);
+                                LoadHeader(HCI_PS_Command,Opcode,PsTagEntry[i].TagLen,PsTagEntry[i].TagId);
+
+                                for(j=0;j<PsTagEntry[i].TagLen;j++){
+                                        HCI_PS_Command[HCI_COMMAND_HEADER+j]=PsTagEntry[i].TagData[j];
+                                }
+
+                     PSPatchPacket[*index].Hcipacket = HCI_PS_Command;
+                     PSPatchPacket[*index].packetLen = PsTagEntry[i].TagLen+HCI_COMMAND_HEADER;
+                     (*index)++;
+
+                        }
+
+    break;
+
+
+    case PS_VERIFY_CRC:
+                        Length = 0x0;
+
+                        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("VALUE of CRC:%d At index %d\r\n",Param1,*index));
+
+                        HCI_PS_Command = (A_UCHAR *) A_MALLOC(Length+HCI_COMMAND_HEADER);
+                        if(HCI_PS_Command == NULL){
+                                AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("MALLOC Failed\r\n"));
+                                return A_ERROR;
+                        }
+                        memset (HCI_PS_Command, 0, Length+HCI_COMMAND_HEADER);
+                        LoadHeader(HCI_PS_Command,Opcode,Length,Param1);
+
+                 PSPatchPacket[*index].Hcipacket = HCI_PS_Command;
+                 PSPatchPacket[*index].packetLen = Length+HCI_COMMAND_HEADER;
+                 (*index)++;
+
+    break;
+
+    case CHANGE_BDADDR:
+    break;
+    }
+    return A_OK;
+}
+A_STATUS AthFreeCommandList(PSCmdPacket **HciPacketList, A_UINT32 numPackets)
+{
+    int i;
+    if(*HciPacketList == NULL) {
+        return A_ERROR;
+    }
+    for(i = 0; i < numPackets;i++) {
+        A_FREE((*HciPacketList)[i].Hcipacket);
+    }  
+    A_FREE(*HciPacketList);
+    return A_OK;
+}
diff --git a/drivers/net/ath6kl/miscdrv/ar3kps/ar3kpsparser.h b/drivers/net/ath6kl/miscdrv/ar3kps/ar3kpsparser.h
new file mode 100644
index 00000000000..007b0eb950d
--- /dev/null
+++ b/drivers/net/ath6kl/miscdrv/ar3kps/ar3kpsparser.h
@@ -0,0 +1,127 @@
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//
+// This file is the include file for Atheros PS and patch parser.
+// It implements APIs to parse data buffer with patch and PS information and convert it to HCI commands.
+//
+
+#ifndef __AR3KPSPARSER_H
+#define __AR3KPSPARSER_H
+
+
+
+
+#include <linux/fs.h>
+#include <linux/slab.h>
+#include "athdefs.h"
+#ifdef HCI_TRANSPORT_SDIO
+#include "a_config.h"
+#include "a_types.h"
+#include "a_osapi.h"
+#define ATH_MODULE_NAME misc
+#include "a_debug.h"
+#include "common_drv.h"
+#include "hci_transport_api.h"
+#include "ar3kconfig.h"
+#else
+#ifndef A_PRINTF
+#define A_PRINTF(args...)     printk(KERN_ALERT args)
+#endif /* A_PRINTF */
+#include "debug_linux.h"
+
+/* Helper data type declaration */
+
+#ifndef A_UINT32
+#define A_UCHAR                 unsigned char
+#define A_UINT32                unsigned long
+#define A_UINT16                unsigned short
+#define A_UINT8                 unsigned char
+#define A_BOOL                  unsigned char
+#endif /* A_UINT32 */
+
+#define ATH_DEBUG_ERR          (1 << 0)
+#define ATH_DEBUG_WARN         (1 << 1)
+#define ATH_DEBUG_INFO         (1 << 2)
+
+
+
+#define FALSE   0
+#define TRUE    1
+
+#ifndef A_MALLOC
+#define A_MALLOC(size)  kmalloc((size),GFP_KERNEL)
+#endif /* A_MALLOC */
+
+
+#ifndef A_FREE
+#define A_FREE(addr)  kfree((addr))
+#endif /* A_MALLOC */
+#endif /* HCI_TRANSPORT_UART */
+
+/* String manipulation APIs */
+#ifndef A_STRTOUL
+#define A_STRTOUL               simple_strtoul
+#endif  /* A_STRTOL */
+
+#ifndef A_STRTOL 
+#define A_STRTOL                simple_strtol
+#endif /* A_STRTOL */
+
+
+/* The maximum number of bytes possible in a patch entry */
+#define MAX_PATCH_SIZE                    20000
+
+/* Maximum HCI packets that will be formed from the Patch file */
+#define MAX_NUM_PATCH_ENTRY               (MAX_PATCH_SIZE/MAX_BYTE_LENGTH) + 1
+
+
+
+
+
+
+
+typedef struct PSCmdPacket
+{
+    A_UCHAR *Hcipacket;
+    int packetLen;
+} PSCmdPacket;
+
+/* Parses a Patch information buffer and store it in global structure */
+A_STATUS AthDoParsePatch(A_UCHAR *, A_UINT32);
+
+/* parses a PS information buffer and stores it in a global structure */
+A_STATUS AthDoParsePS(A_UCHAR *, A_UINT32);
+
+/* 
+ *  Uses the output of Both AthDoParsePS and AthDoParsePatch APIs to form HCI command array with
+ *  all the PS and patch commands.
+ *  The list will have the below mentioned commands in order.
+ *  CRC command packet
+ *  Download patch command(s)
+ *  Enable patch Command
+ *  PS Reset Command
+ *  PS Tag Command(s)
+ *
+ */  
+int AthCreateCommandList(PSCmdPacket **, A_UINT32 *);
+
+/* Cleanup the dynamically allicated HCI command list */
+A_STATUS AthFreeCommandList(PSCmdPacket **HciPacketList, A_UINT32 numPackets);
+#endif /* __AR3KPSPARSER_H */
diff --git a/drivers/net/ath6kl/miscdrv/common_drv.c b/drivers/net/ath6kl/miscdrv/common_drv.c
new file mode 100644
index 00000000000..6754fde467d
--- /dev/null
+++ b/drivers/net/ath6kl/miscdrv/common_drv.c
@@ -0,0 +1,1027 @@
+//------------------------------------------------------------------------------
+// <copyright file="common_drv.c" company="Atheros">
+//    Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+#include "a_config.h"
+#include "athdefs.h"
+#include "a_types.h"
+
+#include "AR6002/hw2.0/hw/mbox_host_reg.h"
+#include "AR6002/hw2.0/hw/apb_map.h"
+#include "AR6002/hw2.0/hw/si_reg.h"
+#include "AR6002/hw2.0/hw/gpio_reg.h"
+#include "AR6002/hw2.0/hw/rtc_reg.h"
+#include "AR6002/hw2.0/hw/vmc_reg.h"
+#include "AR6002/hw2.0/hw/mbox_reg.h"
+
+#include "a_osapi.h"
+#include "targaddrs.h"
+#include "hif.h"
+#include "htc_api.h"
+#include "wmi.h"
+#include "bmi.h"
+#include "bmi_msg.h"
+#include "common_drv.h"
+#define ATH_MODULE_NAME misc
+#include "a_debug.h"
+#include "ar6000_diag.h"
+
+static ATH_DEBUG_MODULE_DBG_INFO *g_pModuleInfoHead = NULL;
+static A_MUTEX_T                 g_ModuleListLock;
+static A_BOOL                    g_ModuleDebugInit = FALSE;
+
+#ifdef ATH_DEBUG_MODULE
+
+ATH_DEBUG_INSTANTIATE_MODULE_VAR(misc,
+                                 "misc",
+                                 "Common and misc APIs",
+                                 ATH_DEBUG_MASK_DEFAULTS,
+                                 0,
+                                 NULL);
+
+#endif
+
+#define HOST_INTEREST_ITEM_ADDRESS(target, item) \
+        ((((target) == TARGET_TYPE_AR6002) ? AR6002_HOST_INTEREST_ITEM_ADDRESS(item) : \
+         (((target) == TARGET_TYPE_AR6003) ? AR6003_HOST_INTEREST_ITEM_ADDRESS(item) : 0)))
+
+
+#define AR6001_LOCAL_COUNT_ADDRESS 0x0c014080
+#define AR6002_LOCAL_COUNT_ADDRESS 0x00018080
+#define AR6003_LOCAL_COUNT_ADDRESS 0x00018080
+#define CPU_DBG_SEL_ADDRESS                      0x00000483
+#define CPU_DBG_ADDRESS                          0x00000484
+
+static A_UINT8 custDataAR6002[AR6002_CUST_DATA_SIZE];
+static A_UINT8 custDataAR6003[AR6003_CUST_DATA_SIZE];
+
+/* Compile the 4BYTE version of the window register setup routine,
+ * This mitigates host interconnect issues with non-4byte aligned bus requests, some
+ * interconnects use bus adapters that impose strict limitations.
+ * Since diag window access is not intended for performance critical operations, the 4byte mode should
+ * be satisfactory even though it generates 4X the bus activity. */
+
+#ifdef USE_4BYTE_REGISTER_ACCESS
+
+    /* set the window address register (using 4-byte register access ). */
+A_STATUS ar6000_SetAddressWindowRegister(HIF_DEVICE *hifDevice, A_UINT32 RegisterAddr, A_UINT32 Address)
+{
+    A_STATUS status;
+    A_UINT8 addrValue[4];
+    A_INT32 i;
+
+        /* write bytes 1,2,3 of the register to set the upper address bytes, the LSB is written
+         * last to initiate the access cycle */
+
+    for (i = 1; i <= 3; i++) {
+            /* fill the buffer with the address byte value we want to hit 4 times*/
+        addrValue[0] = ((A_UINT8 *)&Address)[i];
+        addrValue[1] = addrValue[0];
+        addrValue[2] = addrValue[0];
+        addrValue[3] = addrValue[0];
+
+            /* hit each byte of the register address with a 4-byte write operation to the same address,
+             * this is a harmless operation */
+        status = HIFReadWrite(hifDevice,
+                              RegisterAddr+i,
+                              addrValue,
+                              4,
+                              HIF_WR_SYNC_BYTE_FIX,
+                              NULL);
+        if (status != A_OK) {
+            break;
+        }
+    }
+
+    if (status != A_OK) {
+        AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write initial bytes of 0x%x to window reg: 0x%X \n",
+            Address, RegisterAddr));
+        return status;
+    }
+
+        /* write the address register again, this time write the whole 4-byte value.
+         * The effect here is that the LSB write causes the cycle to start, the extra
+         * 3 byte write to bytes 1,2,3 has no effect since we are writing the same values again */
+    status = HIFReadWrite(hifDevice,
+                          RegisterAddr,
+                          (A_UCHAR *)(&Address),
+                          4,
+                          HIF_WR_SYNC_BYTE_INC,
+                          NULL);
+
+    if (status != A_OK) {
+        AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write 0x%x to window reg: 0x%X \n",
+            Address, RegisterAddr));
+        return status;
+    }
+
+    return A_OK;
+
+
+
+}
+
+
+#else
+
+    /* set the window address register */
+A_STATUS ar6000_SetAddressWindowRegister(HIF_DEVICE *hifDevice, A_UINT32 RegisterAddr, A_UINT32 Address)
+{
+    A_STATUS status;
+
+        /* write bytes 1,2,3 of the register to set the upper address bytes, the LSB is written
+         * last to initiate the access cycle */
+    status = HIFReadWrite(hifDevice,
+                          RegisterAddr+1,  /* write upper 3 bytes */
+                          ((A_UCHAR *)(&Address))+1,
+                          sizeof(A_UINT32)-1,
+                          HIF_WR_SYNC_BYTE_INC,
+                          NULL);
+
+    if (status != A_OK) {
+        AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write initial bytes of 0x%x to window reg: 0x%X \n",
+             RegisterAddr, Address));
+        return status;
+    }
+
+        /* write the LSB of the register, this initiates the operation */
+    status = HIFReadWrite(hifDevice,
+                          RegisterAddr,
+                          (A_UCHAR *)(&Address),
+                          sizeof(A_UINT8),
+                          HIF_WR_SYNC_BYTE_INC,
+                          NULL);
+
+    if (status != A_OK) {
+        AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write 0x%x to window reg: 0x%X \n",
+            RegisterAddr, Address));
+        return status;
+    }
+
+    return A_OK;
+}
+
+#endif
+
+/*
+ * Read from the AR6000 through its diagnostic window.
+ * No cooperation from the Target is required for this.
+ */
+A_STATUS
+ar6000_ReadRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data)
+{
+    A_STATUS status;
+
+        /* set window register to start read cycle */
+    status = ar6000_SetAddressWindowRegister(hifDevice,
+                                             WINDOW_READ_ADDR_ADDRESS,
+                                             *address);
+
+    if (status != A_OK) {
+        return status;
+    }
+
+        /* read the data */
+    status = HIFReadWrite(hifDevice,
+                          WINDOW_DATA_ADDRESS,
+                          (A_UCHAR *)data,
+                          sizeof(A_UINT32),
+                          HIF_RD_SYNC_BYTE_INC,
+                          NULL);
+    if (status != A_OK) {
+        AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot read from WINDOW_DATA_ADDRESS\n"));
+        return status;
+    }
+
+    return status;
+}
+
+
+/*
+ * Write to the AR6000 through its diagnostic window.
+ * No cooperation from the Target is required for this.
+ */
+A_STATUS
+ar6000_WriteRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data)
+{
+    A_STATUS status;
+
+        /* set write data */
+    status = HIFReadWrite(hifDevice,
+                          WINDOW_DATA_ADDRESS,
+                          (A_UCHAR *)data,
+                          sizeof(A_UINT32),
+                          HIF_WR_SYNC_BYTE_INC,
+                          NULL);
+    if (status != A_OK) {
+        AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write 0x%x to WINDOW_DATA_ADDRESS\n", *data));
+        return status;
+    }
+
+        /* set window register, which starts the write cycle */
+    return ar6000_SetAddressWindowRegister(hifDevice,
+                                           WINDOW_WRITE_ADDR_ADDRESS,
+                                           *address);
+    }
+
+A_STATUS
+ar6000_ReadDataDiag(HIF_DEVICE *hifDevice, A_UINT32 address,
+                    A_UCHAR *data, A_UINT32 length)
+{
+    A_UINT32 count;
+    A_STATUS status = A_OK;
+
+    for (count = 0; count < length; count += 4, address += 4) {
+        if ((status = ar6000_ReadRegDiag(hifDevice, &address,
+                                         (A_UINT32 *)&data[count])) != A_OK)
+        {
+            break;
+        }
+    }
+
+    return status;
+}
+
+A_STATUS
+ar6000_WriteDataDiag(HIF_DEVICE *hifDevice, A_UINT32 address,
+                    A_UCHAR *data, A_UINT32 length)
+{
+    A_UINT32 count;
+    A_STATUS status = A_OK;
+
+    for (count = 0; count < length; count += 4, address += 4) {
+        if ((status = ar6000_WriteRegDiag(hifDevice, &address,
+                                         (A_UINT32 *)&data[count])) != A_OK)
+        {
+            break;
+        }
+    }
+
+    return status;
+}
+
+A_STATUS
+ar6k_ReadTargetRegister(HIF_DEVICE *hifDevice, int regsel, A_UINT32 *regval)
+{
+    A_STATUS status;
+    A_UCHAR vals[4];
+    A_UCHAR register_selection[4];
+
+    register_selection[0] = register_selection[1] = register_selection[2] = register_selection[3] = (regsel & 0xff);
+    status = HIFReadWrite(hifDevice,
+                          CPU_DBG_SEL_ADDRESS,
+                          register_selection,
+                          4,
+                          HIF_WR_SYNC_BYTE_FIX,
+                          NULL);
+
+    if (status != A_OK) {
+        AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write CPU_DBG_SEL (%d)\n", regsel));
+        return status;
+    }
+
+    status = HIFReadWrite(hifDevice,
+                          CPU_DBG_ADDRESS,
+                          (A_UCHAR *)vals,
+                          sizeof(vals),
+                          HIF_RD_SYNC_BYTE_INC,
+                          NULL);
+    if (status != A_OK) {
+        AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot read from CPU_DBG_ADDRESS\n"));
+        return status;
+    }
+
+    *regval = vals[0]<<0 | vals[1]<<8 | vals[2]<<16 | vals[3]<<24;
+
+    return status;
+}
+
+void
+ar6k_FetchTargetRegs(HIF_DEVICE *hifDevice, A_UINT32 *targregs)
+{
+    int i;
+    A_UINT32 val;
+
+    for (i=0; i<AR6003_FETCH_TARG_REGS_COUNT; i++) {
+        val=0xffffffff;
+        (void)ar6k_ReadTargetRegister(hifDevice, i, &val);
+        targregs[i] = val;
+    }
+}
+
+#if 0
+static A_STATUS
+_do_write_diag(HIF_DEVICE *hifDevice, A_UINT32 addr, A_UINT32 value)
+{
+    A_STATUS status;
+
+    status = ar6000_WriteRegDiag(hifDevice, &addr, &value);
+    if (status != A_OK)
+    {
+        AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot force Target to execute ROM!\n"));
+    }
+
+    return status;
+}
+#endif
+
+
+/*
+ * Delay up to wait_msecs millisecs to allow Target to enter BMI phase,
+ * which is a good sign that it's alive and well.  This is used after
+ * explicitly forcing the Target to reset.
+ *
+ * The wait_msecs time should be sufficiently long to cover any reasonable
+ * boot-time delay.  For instance, AR6001 firmware allow one second for a
+ * low frequency crystal to settle before it calibrates the refclk frequency.
+ *
+ * TBD: Might want to add special handling for AR6K_OPTION_BMI_DISABLE.
+ */
+#if 0
+static A_STATUS
+_delay_until_target_alive(HIF_DEVICE *hifDevice, A_INT32 wait_msecs, A_UINT32 TargetType)
+{
+    A_INT32 actual_wait;
+    A_INT32 i;
+    A_UINT32 address;
+
+    actual_wait = 0;
+
+    /* Hardcode the address of LOCAL_COUNT_ADDRESS based on the target type */
+    if (TargetType == TARGET_TYPE_AR6002) {
+       address = AR6002_LOCAL_COUNT_ADDRESS;
+    } else if (TargetType == TARGET_TYPE_AR6003) {
+       address = AR6003_LOCAL_COUNT_ADDRESS;
+    } else {
+       A_ASSERT(0);
+    }
+    address += 0x10;
+    for (i=0; actual_wait < wait_msecs; i++) {
+        A_UINT32 data;
+
+        A_MDELAY(100);
+        actual_wait += 100;
+
+        data = 0;
+        if (ar6000_ReadRegDiag(hifDevice, &address, &data) != A_OK) {
+            return A_ERROR;
+        }
+
+        if (data != 0) {
+            /* No need to wait longer -- we have a BMI credit */
+            return A_OK;
+        }
+    }
+    return A_ERROR; /* timed out */
+}
+#endif
+
+#define AR6001_RESET_CONTROL_ADDRESS 0x0C000000
+#define AR6002_RESET_CONTROL_ADDRESS 0x00004000
+#define AR6003_RESET_CONTROL_ADDRESS 0x00004000
+/* reset device */
+A_STATUS ar6000_reset_device(HIF_DEVICE *hifDevice, A_UINT32 TargetType, A_BOOL waitForCompletion, A_BOOL coldReset)
+{
+    A_STATUS status = A_OK;
+    A_UINT32 address;
+    A_UINT32 data;
+
+    do {
+// Workaround BEGIN
+        // address = RESET_CONTROL_ADDRESS;
+    	
+    	if (coldReset) {
+            data = RESET_CONTROL_COLD_RST_MASK;
+    	}
+    	else {
+            data = RESET_CONTROL_MBOX_RST_MASK;
+    	}
+
+          /* Hardcode the address of RESET_CONTROL_ADDRESS based on the target type */
+        if (TargetType == TARGET_TYPE_AR6002) {
+            address = AR6002_RESET_CONTROL_ADDRESS;
+        } else if (TargetType == TARGET_TYPE_AR6003) {
+            address = AR6003_RESET_CONTROL_ADDRESS;
+        } else {
+            A_ASSERT(0);
+        }
+
+
+        status = ar6000_WriteRegDiag(hifDevice, &address, &data);
+
+        if (A_FAILED(status)) {
+            break;
+        }
+
+        if (!waitForCompletion) {
+            break;
+        }
+
+#if 0
+        /* Up to 2 second delay to allow things to settle down */
+        (void)_delay_until_target_alive(hifDevice, 2000, TargetType);
+
+        /*
+         * Read back the RESET CAUSE register to ensure that the cold reset
+         * went through.
+         */
+
+        // address = RESET_CAUSE_ADDRESS;
+        /* Hardcode the address of RESET_CAUSE_ADDRESS based on the target type */
+        if (TargetType == TARGET_TYPE_AR6002) {
+            address = 0x000040C0;
+        } else if (TargetType == TARGET_TYPE_AR6003) {
+            address = 0x000040C0;
+        } else {
+            A_ASSERT(0);
+        }
+
+        data = 0;
+        status = ar6000_ReadRegDiag(hifDevice, &address, &data);
+
+        if (A_FAILED(status)) {
+            break;
+        }
+
+        AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Reset Cause readback: 0x%X \n",data));
+        data &= RESET_CAUSE_LAST_MASK;
+        if (data != 2) {
+            AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Unable to cold reset the target \n"));
+        }
+#endif
+// Workaroud END
+
+    } while (FALSE);
+
+    if (A_FAILED(status)) {
+        AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Failed to reset target \n"));
+    }
+
+    return A_OK;
+}
+
+/* This should be called in BMI phase after firmware is downloaded */
+void
+ar6000_copy_cust_data_from_target(HIF_DEVICE *hifDevice, A_UINT32 TargetType)
+{
+    A_UINT32 eepHeaderAddr;
+    A_UINT8 AR6003CustDataShadow[AR6003_CUST_DATA_SIZE+4];
+    A_INT32 i;
+
+    if (BMIReadMemory(hifDevice,
+            HOST_INTEREST_ITEM_ADDRESS(TargetType, hi_board_data),
+            (A_UCHAR *)&eepHeaderAddr,
+            4)!= A_OK)
+    {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("BMIReadMemory for reading board data address failed \n"));
+        return;
+    }
+
+    if (TargetType == TARGET_TYPE_AR6003) {
+        eepHeaderAddr += 36;  /* AR6003 customer data section offset is 37 */
+
+        for (i=0; i<AR6003_CUST_DATA_SIZE+4; i+=4){
+            if (BMIReadSOCRegister(hifDevice, eepHeaderAddr, (A_UINT32 *)&AR6003CustDataShadow[i])!= A_OK) {
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("BMIReadSOCRegister () failed \n"));
+                return ;
+            }  
+            eepHeaderAddr +=4;
+        }
+
+        memcpy(custDataAR6003, AR6003CustDataShadow+1, AR6003_CUST_DATA_SIZE);
+    }
+
+    if (TargetType == TARGET_TYPE_AR6002) {
+        eepHeaderAddr += 64;  /* AR6002 customer data sectioin offset is 64 */
+
+        for (i=0; i<AR6002_CUST_DATA_SIZE; i+=4){
+            if (BMIReadSOCRegister(hifDevice, eepHeaderAddr, (A_UINT32 *)&custDataAR6002[i])!= A_OK) {
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("BMIReadSOCRegister () failed \n"));
+                return ;
+            }  
+            eepHeaderAddr +=4;
+        }
+    }
+
+    return;
+}
+
+/* This is the function to call when need to use the cust data */
+A_UINT8 *
+ar6000_get_cust_data_buffer(A_UINT32 TargetType)
+{
+    if (TargetType == TARGET_TYPE_AR6003)
+        return custDataAR6003;
+
+    if (TargetType == TARGET_TYPE_AR6002)
+        return custDataAR6002;
+
+    return NULL;
+}
+
+#define REG_DUMP_COUNT_AR6001   38  /* WORDs, derived from AR600x_regdump.h */
+#define REG_DUMP_COUNT_AR6002   60
+#define REG_DUMP_COUNT_AR6003   60
+#define REGISTER_DUMP_LEN_MAX   60
+#if REG_DUMP_COUNT_AR6001 > REGISTER_DUMP_LEN_MAX
+#error "REG_DUMP_COUNT_AR6001 too large"
+#endif
+#if REG_DUMP_COUNT_AR6002 > REGISTER_DUMP_LEN_MAX
+#error "REG_DUMP_COUNT_AR6002 too large"
+#endif
+#if REG_DUMP_COUNT_AR6003 > REGISTER_DUMP_LEN_MAX
+#error "REG_DUMP_COUNT_AR6003 too large"
+#endif
+
+
+void ar6000_dump_target_assert_info(HIF_DEVICE *hifDevice, A_UINT32 TargetType)
+{
+    A_UINT32 address;
+    A_UINT32 regDumpArea = 0;
+    A_STATUS status;
+    A_UINT32 regDumpValues[REGISTER_DUMP_LEN_MAX];
+    A_UINT32 regDumpCount = 0;
+    A_UINT32 i;
+
+    do {
+
+            /* the reg dump pointer is copied to the host interest area */
+        address = HOST_INTEREST_ITEM_ADDRESS(TargetType, hi_failure_state);
+        address = TARG_VTOP(TargetType, address);
+
+        if (TargetType == TARGET_TYPE_AR6002) {
+            regDumpCount = REG_DUMP_COUNT_AR6002;
+        } else  if (TargetType == TARGET_TYPE_AR6003) {
+            regDumpCount = REG_DUMP_COUNT_AR6003;
+        } else {
+            A_ASSERT(0);
+        }
+
+            /* read RAM location through diagnostic window */
+        status = ar6000_ReadRegDiag(hifDevice, &address, &regDumpArea);
+
+        if (A_FAILED(status)) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR6K: Failed to get ptr to register dump area \n"));
+            break;
+        }
+
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR6K: Location of register dump data: 0x%X \n",regDumpArea));
+
+        if (regDumpArea == 0) {
+                /* no reg dump */
+            break;
+        }
+
+        regDumpArea = TARG_VTOP(TargetType, regDumpArea);
+
+            /* fetch register dump data */
+        status = ar6000_ReadDataDiag(hifDevice,
+                                     regDumpArea,
+                                     (A_UCHAR *)&regDumpValues[0],
+                                     regDumpCount * (sizeof(A_UINT32)));
+
+        if (A_FAILED(status)) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR6K: Failed to get register dump \n"));
+            break;
+        }
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR6K: Register Dump: \n"));
+
+        for (i = 0; i < regDumpCount; i++) {
+            //ATHR_DISPLAY_MSG (_T(" %d :  0x%8.8X \n"), i, regDumpValues[i]);
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" %d :  0x%8.8X \n",i, regDumpValues[i]));
+
+#ifdef UNDER_CE
+        /*
+         * For Every logPrintf() Open the File so that in case of Crashes
+         * We will have until the Last Message Flushed on to the File
+         * So use logPrintf Sparingly..!!
+         */
+        tgtassertPrintf (ATH_DEBUG_TRC," %d:  0x%8.8X \n",i, regDumpValues[i]);
+#endif
+        }
+
+    } while (FALSE);
+
+}
+
+/* set HTC/Mbox operational parameters, this can only be called when the target is in the
+ * BMI phase */
+A_STATUS ar6000_set_htc_params(HIF_DEVICE *hifDevice,
+                               A_UINT32    TargetType,
+                               A_UINT32    MboxIsrYieldValue,
+                               A_UINT8     HtcControlBuffers)
+{
+    A_STATUS status;
+    A_UINT32 blocksizes[HTC_MAILBOX_NUM_MAX];
+
+    do {
+            /* get the block sizes */
+        status = HIFConfigureDevice(hifDevice, HIF_DEVICE_GET_MBOX_BLOCK_SIZE,
+                                    blocksizes, sizeof(blocksizes));
+
+        if (A_FAILED(status)) {
+            AR_DEBUG_PRINTF(ATH_LOG_ERR,("Failed to get block size info from HIF layer...\n"));
+            break;
+        }
+            /* note: we actually get the block size for mailbox 1, for SDIO the block
+             * size on mailbox 0 is artificially set to 1 */
+            /* must be a power of 2 */
+        A_ASSERT((blocksizes[1] & (blocksizes[1] - 1)) == 0);
+
+        if (HtcControlBuffers != 0) {
+                /* set override for number of control buffers to use */
+            blocksizes[1] |=  ((A_UINT32)HtcControlBuffers) << 16;
+        }
+
+            /* set the host interest area for the block size */
+        status = BMIWriteMemory(hifDevice,
+                                HOST_INTEREST_ITEM_ADDRESS(TargetType, hi_mbox_io_block_sz),
+                                (A_UCHAR *)&blocksizes[1],
+                                4);
+
+        if (A_FAILED(status)) {
+            AR_DEBUG_PRINTF(ATH_LOG_ERR,("BMIWriteMemory for IO block size failed \n"));
+            break;
+        }
+
+        AR_DEBUG_PRINTF(ATH_LOG_INF,("Block Size Set: %d (target address:0x%X)\n",
+                blocksizes[1], HOST_INTEREST_ITEM_ADDRESS(TargetType, hi_mbox_io_block_sz)));
+
+        if (MboxIsrYieldValue != 0) {
+                /* set the host interest area for the mbox ISR yield limit */
+            status = BMIWriteMemory(hifDevice,
+                                    HOST_INTEREST_ITEM_ADDRESS(TargetType, hi_mbox_isr_yield_limit),
+                                    (A_UCHAR *)&MboxIsrYieldValue,
+                                    4);
+
+            if (A_FAILED(status)) {
+                AR_DEBUG_PRINTF(ATH_LOG_ERR,("BMIWriteMemory for yield limit failed \n"));
+                break;
+            }
+        }
+
+    } while (FALSE);
+
+    return status;
+}
+
+
+static A_STATUS prepare_ar6002(HIF_DEVICE *hifDevice, A_UINT32 TargetVersion)
+{
+    A_STATUS status = A_OK;
+
+    /* placeholder */
+
+    return status;
+}
+
+static A_STATUS prepare_ar6003(HIF_DEVICE *hifDevice, A_UINT32 TargetVersion)
+{
+    A_STATUS status = A_OK;
+
+    /* placeholder */
+
+    return status;
+}
+
+/* this function assumes the caller has already initialized the BMI APIs */
+A_STATUS ar6000_prepare_target(HIF_DEVICE *hifDevice,
+                               A_UINT32    TargetType,
+                               A_UINT32    TargetVersion)
+{
+    if (TargetType == TARGET_TYPE_AR6002) {
+            /* do any preparations for AR6002 devices */
+        return prepare_ar6002(hifDevice,TargetVersion);
+    } else if (TargetType == TARGET_TYPE_AR6003) {
+        return prepare_ar6003(hifDevice,TargetVersion);
+    }
+
+    return A_OK;
+}
+
+#if defined(CONFIG_AR6002_REV1_FORCE_HOST)
+/*
+ * Call this function just before the call to BMIInit
+ * in order to force* AR6002 rev 1.x firmware to detect a Host.
+ * THIS IS FOR USE ONLY WITH AR6002 REV 1.x.
+ * TBDXXX: Remove this function when REV 1.x is desupported.
+ */
+A_STATUS
+ar6002_REV1_reset_force_host (HIF_DEVICE *hifDevice)
+{
+    A_INT32 i;
+    struct forceROM_s {
+        A_UINT32 addr;
+        A_UINT32 data;
+    };
+    struct forceROM_s *ForceROM;
+    A_INT32 szForceROM;
+    A_STATUS status = A_OK;
+    A_UINT32 address;
+    A_UINT32 data;
+
+    /* Force AR6002 REV1.x to recognize Host presence.
+     *
+     * Note: Use RAM at 0x52df80..0x52dfa0 with ROM Remap entry 0
+     * so that this workaround functions with AR6002.war1.sh.  We
+     * could fold that entire workaround into this one, but it's not
+     * worth the effort at this point.  This workaround cannot be
+     * merged into the other workaround because this must be done
+     * before BMI.
+     */
+
+    static struct forceROM_s ForceROM_NEW[] = {
+        {0x52df80, 0x20f31c07},
+        {0x52df84, 0x92374420},
+        {0x52df88, 0x1d120c03},
+        {0x52df8c, 0xff8216f0},
+        {0x52df90, 0xf01d120c},
+        {0x52df94, 0x81004136},
+        {0x52df98, 0xbc9100bd},
+        {0x52df9c, 0x00bba100},
+
+        {0x00008000|MC_TCAM_TARGET_ADDRESS, 0x0012dfe0}, /* Use remap entry 0 */
+        {0x00008000|MC_TCAM_COMPARE_ADDRESS, 0x000e2380},
+        {0x00008000|MC_TCAM_MASK_ADDRESS, 0x00000000},
+        {0x00008000|MC_TCAM_VALID_ADDRESS, 0x00000001},
+
+        {0x00018000|(LOCAL_COUNT_ADDRESS+0x10), 0}, /* clear BMI credit counter */
+
+        {0x00004000|AR6002_RESET_CONTROL_ADDRESS, RESET_CONTROL_WARM_RST_MASK},
+    };
+
+    address = 0x004ed4b0; /* REV1 target software ID is stored here */
+    status = ar6000_ReadRegDiag(hifDevice, &address, &data);
+    if (A_FAILED(status) || (data != AR6002_VERSION_REV1)) {
+        return A_ERROR; /* Not AR6002 REV1 */
+    }
+
+    ForceROM = ForceROM_NEW;
+    szForceROM = sizeof(ForceROM_NEW)/sizeof(*ForceROM);
+
+    ATH_DEBUG_PRINTF (DBG_MISC_DRV, ATH_DEBUG_TRC, ("Force Target to recognize Host....\n"));
+    for (i = 0; i < szForceROM; i++)
+    {
+        if (ar6000_WriteRegDiag(hifDevice,
+                                &ForceROM[i].addr,
+                                &ForceROM[i].data) != A_OK)
+        {
+            ATH_DEBUG_PRINTF (DBG_MISC_DRV, ATH_DEBUG_TRC, ("Cannot force Target to recognize Host!\n"));
+            return A_ERROR;
+        }
+    }
+
+    A_MDELAY(1000);
+
+    return A_OK;
+}
+
+#endif /* CONFIG_AR6002_REV1_FORCE_HOST */
+
+void DebugDumpBytes(A_UCHAR *buffer, A_UINT16 length, char *pDescription)
+{
+    A_CHAR stream[60];
+    A_CHAR byteOffsetStr[10];
+    A_UINT32 i;
+    A_UINT16 offset, count, byteOffset;
+
+    A_PRINTF("<---------Dumping %d Bytes : %s ------>\n", length, pDescription);
+
+    count = 0;
+    offset = 0;
+    byteOffset = 0;
+    for(i = 0; i < length; i++) {
+        A_SPRINTF(stream + offset, "%2.2X ", buffer[i]);
+        count ++;
+        offset += 3;
+
+        if(count == 16) {
+            count = 0;
+            offset = 0;
+            A_SPRINTF(byteOffsetStr,"%4.4X",byteOffset);
+            A_PRINTF("[%s]: %s\n", byteOffsetStr, stream);
+            A_MEMZERO(stream, 60);
+            byteOffset += 16;
+        }
+    }
+
+    if(offset != 0) {
+        A_SPRINTF(byteOffsetStr,"%4.4X",byteOffset);
+        A_PRINTF("[%s]: %s\n", byteOffsetStr, stream);
+    }
+
+    A_PRINTF("<------------------------------------------------->\n");
+}
+
+void a_dump_module_debug_info(ATH_DEBUG_MODULE_DBG_INFO *pInfo)
+{
+    int                         i;
+    ATH_DEBUG_MASK_DESCRIPTION *pDesc;
+
+    if (pInfo == NULL) {
+        return;
+    }
+
+    pDesc = pInfo->pMaskDescriptions;
+
+    A_PRINTF("========================================================\n\n");
+    A_PRINTF("Module Debug Info => Name   : %s    \n", pInfo->ModuleName);
+    A_PRINTF("                  => Descr. : %s \n", pInfo->ModuleDescription);
+    A_PRINTF("\n  Current mask    => 0x%8.8X \n", pInfo->CurrentMask);
+    A_PRINTF("\n  Avail. Debug Masks :\n\n");
+
+    for (i = 0; i < pInfo->MaxDescriptions; i++,pDesc++) {
+        A_PRINTF("                  => 0x%8.8X -- %s \n", pDesc->Mask, pDesc->Description);
+    }
+
+    if (0 == i) {
+        A_PRINTF("                  => * none defined * \n");
+    }
+
+    A_PRINTF("\n  Standard Debug Masks :\n\n");
+        /* print standard masks */
+    A_PRINTF("                  => 0x%8.8X -- Errors \n", ATH_DEBUG_ERR);
+    A_PRINTF("                  => 0x%8.8X -- Warnings \n", ATH_DEBUG_WARN);
+    A_PRINTF("                  => 0x%8.8X -- Informational \n", ATH_DEBUG_INFO);
+    A_PRINTF("                  => 0x%8.8X -- Tracing \n", ATH_DEBUG_TRC);
+    A_PRINTF("\n========================================================\n");
+
+}
+
+
+static ATH_DEBUG_MODULE_DBG_INFO *FindModule(A_CHAR *module_name)
+{
+    ATH_DEBUG_MODULE_DBG_INFO *pInfo = g_pModuleInfoHead;
+
+    if (!g_ModuleDebugInit) {
+        return NULL;
+    }
+
+    while (pInfo != NULL) {
+            /* TODO: need to use something other than strlen */
+        if (A_MEMCMP(pInfo->ModuleName,module_name,strlen(module_name)) == 0) {
+            break;
+        }
+        pInfo = pInfo->pNext;
+    }
+
+    return pInfo;
+}
+
+
+void a_register_module_debug_info(ATH_DEBUG_MODULE_DBG_INFO *pInfo)
+{
+    if (!g_ModuleDebugInit) {
+        return;
+    }
+
+    A_MUTEX_LOCK(&g_ModuleListLock);
+
+    if (!(pInfo->Flags & ATH_DEBUG_INFO_FLAGS_REGISTERED)) {
+        if (g_pModuleInfoHead == NULL) {
+            g_pModuleInfoHead = pInfo;
+        } else {
+           pInfo->pNext = g_pModuleInfoHead;
+           g_pModuleInfoHead = pInfo;
+        }
+        pInfo->Flags |= ATH_DEBUG_INFO_FLAGS_REGISTERED;
+    }
+
+    A_MUTEX_UNLOCK(&g_ModuleListLock);
+}
+
+void a_dump_module_debug_info_by_name(A_CHAR *module_name)
+{
+    ATH_DEBUG_MODULE_DBG_INFO *pInfo = g_pModuleInfoHead;
+
+    if (!g_ModuleDebugInit) {
+        return;
+    }
+
+    if (A_MEMCMP(module_name,"all",3) == 0) {
+            /* dump all */
+        while (pInfo != NULL) {
+            a_dump_module_debug_info(pInfo);
+            pInfo = pInfo->pNext;
+        }
+        return;
+    }
+
+    pInfo = FindModule(module_name);
+
+    if (pInfo != NULL) {
+         a_dump_module_debug_info(pInfo);
+    }
+
+}
+
+A_STATUS a_get_module_mask(A_CHAR *module_name, A_UINT32 *pMask)
+{
+    ATH_DEBUG_MODULE_DBG_INFO *pInfo = FindModule(module_name);
+
+    if (NULL == pInfo) {
+        return A_ERROR;
+    }
+
+    *pMask = pInfo->CurrentMask;
+    return A_OK;
+}
+
+A_STATUS a_set_module_mask(A_CHAR *module_name, A_UINT32 Mask)
+{
+    ATH_DEBUG_MODULE_DBG_INFO *pInfo = FindModule(module_name);
+
+    if (NULL == pInfo) {
+        return A_ERROR;
+    }
+
+    pInfo->CurrentMask = Mask;
+    A_PRINTF("Module %s,  new mask: 0x%8.8X \n",module_name,pInfo->CurrentMask);
+    return A_OK;
+}
+
+
+void a_module_debug_support_init(void)
+{
+    if (g_ModuleDebugInit) {
+        return;
+    }
+    A_MUTEX_INIT(&g_ModuleListLock);
+    g_pModuleInfoHead = NULL;
+    g_ModuleDebugInit = TRUE;
+    A_REGISTER_MODULE_DEBUG_INFO(misc);
+}
+
+void a_module_debug_support_cleanup(void)
+{
+    ATH_DEBUG_MODULE_DBG_INFO *pInfo = g_pModuleInfoHead;
+    ATH_DEBUG_MODULE_DBG_INFO *pCur;
+
+    if (!g_ModuleDebugInit) {
+        return;
+    }
+
+    g_ModuleDebugInit = FALSE;
+
+    A_MUTEX_LOCK(&g_ModuleListLock);
+
+    while (pInfo != NULL) {
+        pCur = pInfo;
+        pInfo = pInfo->pNext;
+        pCur->pNext = NULL;
+            /* clear registered flag */
+        pCur->Flags &= ~ATH_DEBUG_INFO_FLAGS_REGISTERED;
+    }
+
+    A_MUTEX_UNLOCK(&g_ModuleListLock);
+
+    A_MUTEX_DELETE(&g_ModuleListLock);
+    g_pModuleInfoHead = NULL;
+}
+
+    /* can only be called during bmi init stage */
+A_STATUS ar6000_set_hci_bridge_flags(HIF_DEVICE *hifDevice,
+                                     A_UINT32    TargetType,
+                                     A_UINT32    Flags)
+{
+    A_STATUS status = A_OK;
+
+    do {
+
+        if (TargetType != TARGET_TYPE_AR6003) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_WARN, ("Target Type:%d, does not support HCI bridging! \n",
+                TargetType));
+            break;
+        }
+
+            /* set hci bridge flags */
+        status = BMIWriteMemory(hifDevice,
+                                HOST_INTEREST_ITEM_ADDRESS(TargetType, hi_hci_bridge_flags),
+                                (A_UCHAR *)&Flags,
+                                4);
+
+
+    } while (FALSE);
+
+    return status;
+}
+
diff --git a/drivers/net/ath6kl/miscdrv/credit_dist.c b/drivers/net/ath6kl/miscdrv/credit_dist.c
new file mode 100644
index 00000000000..91316e0b109
--- /dev/null
+++ b/drivers/net/ath6kl/miscdrv/credit_dist.c
@@ -0,0 +1,418 @@
+//------------------------------------------------------------------------------
+// <copyright file="credit_dist.c" company="Atheros">
+//    Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+#include "a_config.h"
+#include "athdefs.h"
+#include "a_types.h"
+#include "a_osapi.h"
+#define ATH_MODULE_NAME misc
+#include "a_debug.h"
+#include "htc_api.h"
+#include "common_drv.h"
+
+/********* CREDIT DISTRIBUTION FUNCTIONS ******************************************/
+
+#define NO_VO_SERVICE 1 /* currently WMI only uses 3 data streams, so we leave VO service inactive */
+#define CONFIG_GIVE_LOW_PRIORITY_STREAMS_MIN_CREDITS 1
+
+#ifdef NO_VO_SERVICE
+#define DATA_SVCS_USED 3
+#else
+#define DATA_SVCS_USED 4
+#endif
+
+static void RedistributeCredits(COMMON_CREDIT_STATE_INFO *pCredInfo,
+                                HTC_ENDPOINT_CREDIT_DIST *pEPDistList);
+
+static void SeekCredits(COMMON_CREDIT_STATE_INFO *pCredInfo,
+                        HTC_ENDPOINT_CREDIT_DIST *pEPDistList);
+
+/* reduce an ep's credits back to a set limit */
+static INLINE void ReduceCredits(COMMON_CREDIT_STATE_INFO *pCredInfo,
+                                HTC_ENDPOINT_CREDIT_DIST  *pEpDist,
+                                int                       Limit)
+{
+    int credits;
+
+        /* set the new limit */
+    pEpDist->TxCreditsAssigned = Limit;
+
+    if (pEpDist->TxCredits <= Limit) {
+        return;
+    }
+
+        /* figure out how much to take away */
+    credits = pEpDist->TxCredits - Limit;
+        /* take them away */
+    pEpDist->TxCredits -= credits;
+    pCredInfo->CurrentFreeCredits += credits;
+}
+
+/* give an endpoint some credits from the free credit pool */
+#define GiveCredits(pCredInfo,pEpDist,credits)      \
+{                                                   \
+    (pEpDist)->TxCredits += (credits);              \
+    (pEpDist)->TxCreditsAssigned += (credits);      \
+    (pCredInfo)->CurrentFreeCredits -= (credits);   \
+}
+
+
+/* default credit init callback.
+ * This function is called in the context of HTCStart() to setup initial (application-specific)
+ * credit distributions */
+static void ar6000_credit_init(void                     *Context,
+                               HTC_ENDPOINT_CREDIT_DIST *pEPList,
+                               int                      TotalCredits)
+{
+    HTC_ENDPOINT_CREDIT_DIST *pCurEpDist;
+    int                      count;
+    COMMON_CREDIT_STATE_INFO *pCredInfo = (COMMON_CREDIT_STATE_INFO *)Context;
+
+    pCredInfo->CurrentFreeCredits = TotalCredits;
+    pCredInfo->TotalAvailableCredits = TotalCredits;
+
+    pCurEpDist = pEPList;
+
+        /* run through the list and initialize */
+    while (pCurEpDist != NULL) {
+
+            /* set minimums for each endpoint */
+        pCurEpDist->TxCreditsMin = pCurEpDist->TxCreditsPerMaxMsg;
+
+#ifdef CONFIG_GIVE_LOW_PRIORITY_STREAMS_MIN_CREDITS
+ 
+      if (TotalCredits > 4)
+      {
+          if ((pCurEpDist->ServiceID == WMI_DATA_BK_SVC)  || (pCurEpDist->ServiceID == WMI_DATA_BE_SVC)){
+                    /* assign at least min credits to lower than VO priority services */
+                GiveCredits(pCredInfo,pCurEpDist,pCurEpDist->TxCreditsMin);
+                    /* force active */
+                SET_EP_ACTIVE(pCurEpDist);
+          }
+      }
+ 
+#endif
+
+        if (pCurEpDist->ServiceID == WMI_CONTROL_SVC) {
+                /* give control service some credits */
+            GiveCredits(pCredInfo,pCurEpDist,pCurEpDist->TxCreditsMin);
+                /* control service is always marked active, it never goes inactive EVER */
+            SET_EP_ACTIVE(pCurEpDist);
+        } else if (pCurEpDist->ServiceID == WMI_DATA_BK_SVC) {
+                /* this is the lowest priority data endpoint, save this off for easy access */
+            pCredInfo->pLowestPriEpDist = pCurEpDist;
+        }
+
+        /* Streams have to be created (explicit | implicit)for all kinds
+         * of traffic. BE endpoints are also inactive in the beginning.
+         * When BE traffic starts it creates implicit streams that
+         * redistributes credits.
+         */
+
+        /* note, all other endpoints have minimums set but are initially given NO credits.
+         * Credits will be distributed as traffic activity demands */
+        pCurEpDist = pCurEpDist->pNext;
+    }
+
+    if (pCredInfo->CurrentFreeCredits <= 0) {
+        AR_DEBUG_PRINTF(ATH_LOG_INF, ("Not enough credits (%d) to do credit distributions \n", TotalCredits));
+        A_ASSERT(FALSE);
+        return;
+    }
+
+        /* reset list */
+    pCurEpDist = pEPList;
+        /* now run through the list and set max operating credit limits for everyone */
+    while (pCurEpDist != NULL) {
+        if (pCurEpDist->ServiceID == WMI_CONTROL_SVC) {
+                /* control service max is just 1 max message */
+            pCurEpDist->TxCreditsNorm = pCurEpDist->TxCreditsPerMaxMsg;
+        } else {
+                /* for the remaining data endpoints, we assume that each TxCreditsPerMaxMsg are
+                 * the same.
+                 * We use a simple calculation here, we take the remaining credits and
+                 * determine how many max messages this can cover and then set each endpoint's
+                 * normal value equal to 3/4 this amount.
+                 * */
+            count = (pCredInfo->CurrentFreeCredits/pCurEpDist->TxCreditsPerMaxMsg) * pCurEpDist->TxCreditsPerMaxMsg;
+            count = (count * 3) >> 2;
+            count = max(count,pCurEpDist->TxCreditsPerMaxMsg);
+                /* set normal */
+            pCurEpDist->TxCreditsNorm = count;
+
+        }
+        pCurEpDist = pCurEpDist->pNext;
+    }
+
+}
+
+
+/* default credit distribution callback
+ * This callback is invoked whenever endpoints require credit distributions.
+ * A lock is held while this function is invoked, this function shall NOT block.
+ * The pEPDistList is a list of distribution structures in prioritized order as
+ * defined by the call to the HTCSetCreditDistribution() api.
+ *
+ */
+static void ar6000_credit_distribute(void                     *Context,
+                                     HTC_ENDPOINT_CREDIT_DIST *pEPDistList,
+                                     HTC_CREDIT_DIST_REASON   Reason)
+{
+    HTC_ENDPOINT_CREDIT_DIST *pCurEpDist;
+    COMMON_CREDIT_STATE_INFO *pCredInfo = (COMMON_CREDIT_STATE_INFO *)Context;
+
+    switch (Reason) {
+        case HTC_CREDIT_DIST_SEND_COMPLETE :
+            pCurEpDist = pEPDistList;
+                /* we are given the start of the endpoint distribution list.
+                 * There may be one or more endpoints to service.
+                 * Run through the list and distribute credits */
+            while (pCurEpDist != NULL) {
+
+                if (pCurEpDist->TxCreditsToDist > 0) {
+                        /* return the credits back to the endpoint */
+                    pCurEpDist->TxCredits += pCurEpDist->TxCreditsToDist;
+                        /* always zero out when we are done */
+                    pCurEpDist->TxCreditsToDist = 0;
+
+                    if (pCurEpDist->TxCredits > pCurEpDist->TxCreditsAssigned) {
+                            /* reduce to the assigned limit, previous credit reductions
+                             * could have caused the limit to change */
+                        ReduceCredits(pCredInfo, pCurEpDist, pCurEpDist->TxCreditsAssigned);
+                    }
+
+                    if (pCurEpDist->TxCredits > pCurEpDist->TxCreditsNorm) {
+                            /* oversubscribed endpoints need to reduce back to normal */
+                        ReduceCredits(pCredInfo, pCurEpDist, pCurEpDist->TxCreditsNorm);
+                    }
+                
+                    if (!IS_EP_ACTIVE(pCurEpDist)) {
+                            /* endpoint is inactive, now check for messages waiting for credits */
+                        if (pCurEpDist->TxQueueDepth == 0) {
+                                /* EP is inactive and there are no pending messages, 
+                                 * reduce credits back to zero to recover credits */
+                            ReduceCredits(pCredInfo, pCurEpDist, 0);
+                        }
+                    }
+                }
+
+                pCurEpDist = pCurEpDist->pNext;
+            }
+
+            break;
+
+        case HTC_CREDIT_DIST_ACTIVITY_CHANGE :
+            RedistributeCredits(pCredInfo,pEPDistList);
+            break;
+        case HTC_CREDIT_DIST_SEEK_CREDITS :
+            SeekCredits(pCredInfo,pEPDistList);
+            break;
+        case HTC_DUMP_CREDIT_STATE :
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Credit Distribution, total : %d, free : %d\n",
+            								pCredInfo->TotalAvailableCredits, pCredInfo->CurrentFreeCredits));
+            break;
+        default:
+            break;
+
+    }
+
+        /* sanity checks done after each distribution action */
+    A_ASSERT(pCredInfo->CurrentFreeCredits <= pCredInfo->TotalAvailableCredits);
+    A_ASSERT(pCredInfo->CurrentFreeCredits >= 0);
+
+}
+
+/* redistribute credits based on activity change */
+static void RedistributeCredits(COMMON_CREDIT_STATE_INFO *pCredInfo,
+                                HTC_ENDPOINT_CREDIT_DIST *pEPDistList)
+{
+    HTC_ENDPOINT_CREDIT_DIST *pCurEpDist = pEPDistList;
+
+        /* walk through the list and remove credits from inactive endpoints */
+    while (pCurEpDist != NULL) {
+
+#ifdef CONFIG_GIVE_LOW_PRIORITY_STREAMS_MIN_CREDITS
+
+        if ((pCurEpDist->ServiceID == WMI_DATA_BK_SVC)  || (pCurEpDist->ServiceID == WMI_DATA_BE_SVC)) {
+              /* force low priority streams to always be active to retain their minimum credit distribution */
+             SET_EP_ACTIVE(pCurEpDist);
+        }
+#endif
+
+        if (pCurEpDist->ServiceID != WMI_CONTROL_SVC) {
+            if (!IS_EP_ACTIVE(pCurEpDist)) {
+                if (pCurEpDist->TxQueueDepth == 0) {
+                        /* EP is inactive and there are no pending messages, reduce credits back to zero */
+                    ReduceCredits(pCredInfo, pCurEpDist, 0);
+                } else {
+                        /* we cannot zero the credits assigned to this EP, but to keep
+                         * the credits available for these leftover packets, reduce to
+                         * a minimum */
+                    ReduceCredits(pCredInfo, pCurEpDist, pCurEpDist->TxCreditsMin);
+                }
+            }
+        }
+
+        /* NOTE in the active case, we do not need to do anything further,
+         * when an EP goes active and needs credits, HTC will call into
+         * our distribution function using a reason code of HTC_CREDIT_DIST_SEEK_CREDITS  */
+
+        pCurEpDist = pCurEpDist->pNext;
+    }
+
+}
+
+/* HTC has an endpoint that needs credits, pEPDist is the endpoint in question */
+static void SeekCredits(COMMON_CREDIT_STATE_INFO *pCredInfo,
+                        HTC_ENDPOINT_CREDIT_DIST *pEPDist)
+{
+    HTC_ENDPOINT_CREDIT_DIST *pCurEpDist;
+    int                      credits = 0;
+    int                      need;
+
+    do {
+
+        if (pEPDist->ServiceID == WMI_CONTROL_SVC) {
+                /* we never oversubscribe on the control service, this is not
+                 * a high performance path and the target never holds onto control
+                 * credits for too long */
+            break;
+        }
+
+#ifdef CONFIG_GIVE_LOW_PRIORITY_STREAMS_MIN_CREDITS
+        if (pEPDist->ServiceID == WMI_DATA_VI_SVC) {
+            if ((pEPDist->TxCreditsAssigned >= pEPDist->TxCreditsNorm)) {
+                 /* limit VI service from oversubscribing */
+                 break;
+            }
+        }
+ 
+        if (pEPDist->ServiceID == WMI_DATA_VO_SVC) {
+            if ((pEPDist->TxCreditsAssigned >= pEPDist->TxCreditsNorm)) {
+                 /* limit VO service from oversubscribing */
+                break;
+            }
+        }
+#else
+        if (pEPDist->ServiceID == WMI_DATA_VI_SVC) {
+            if ((pEPDist->TxCreditsAssigned >= pEPDist->TxCreditsNorm) ||
+                (pCredInfo->CurrentFreeCredits <= pEPDist->TxCreditsPerMaxMsg)) {
+                 /* limit VI service from oversubscribing */
+                 /* at least one free credit will not be used by VI */
+                 break;
+            }
+        }
+ 
+        if (pEPDist->ServiceID == WMI_DATA_VO_SVC) {
+            if ((pEPDist->TxCreditsAssigned >= pEPDist->TxCreditsNorm) ||
+                (pCredInfo->CurrentFreeCredits <= pEPDist->TxCreditsPerMaxMsg)) {
+                 /* limit VO service from oversubscribing */
+                 /* at least one free credit will not be used by VO */
+                break;
+            }
+        }
+#endif
+
+        /* for all other services, we follow a simple algorithm of
+         * 1. checking the free pool for credits
+         * 2. checking lower priority endpoints for credits to take */
+
+            /* give what we can */
+        credits = min(pCredInfo->CurrentFreeCredits,pEPDist->TxCreditsSeek);
+
+        if (credits >= pEPDist->TxCreditsSeek) {
+                /* we found some to fullfill the seek request */
+            break;
+        }
+
+        /* we don't have enough in the free pool, try taking away from lower priority services
+         *
+         * The rule for taking away credits:
+         *   1. Only take from lower priority endpoints
+         *   2. Only take what is allocated above the minimum (never starve an endpoint completely)
+         *   3. Only take what you need.
+         *
+         * */
+
+            /* starting at the lowest priority */
+        pCurEpDist = pCredInfo->pLowestPriEpDist;
+
+            /* work backwards until we hit the endpoint again */
+        while (pCurEpDist != pEPDist) {
+                /* calculate how many we need so far */
+            need = pEPDist->TxCreditsSeek - pCredInfo->CurrentFreeCredits;
+
+            if ((pCurEpDist->TxCreditsAssigned - need) >= pCurEpDist->TxCreditsMin) {
+                    /* the current one has been allocated more than it's minimum and it
+                     * has enough credits assigned above it's minimum to fullfill our need
+                     * try to take away just enough to fullfill our need */
+                ReduceCredits(pCredInfo,
+                              pCurEpDist,
+                              pCurEpDist->TxCreditsAssigned - need);
+
+                if (pCredInfo->CurrentFreeCredits >= pEPDist->TxCreditsSeek) {
+                        /* we have enough */
+                    break;
+                }
+            }
+
+            pCurEpDist = pCurEpDist->pPrev;
+        }
+
+            /* return what we can get */
+        credits = min(pCredInfo->CurrentFreeCredits,pEPDist->TxCreditsSeek);
+
+    } while (FALSE);
+
+        /* did we find some credits? */
+    if (credits) {
+            /* give what we can */
+        GiveCredits(pCredInfo, pEPDist, credits);
+    }
+
+}
+
+/* initialize and setup credit distribution */
+A_STATUS ar6000_setup_credit_dist(HTC_HANDLE HTCHandle, COMMON_CREDIT_STATE_INFO *pCredInfo)
+{
+    HTC_SERVICE_ID servicepriority[5];
+
+    A_MEMZERO(pCredInfo,sizeof(COMMON_CREDIT_STATE_INFO));
+
+    servicepriority[0] = WMI_CONTROL_SVC;  /* highest */
+    servicepriority[1] = WMI_DATA_VO_SVC;
+    servicepriority[2] = WMI_DATA_VI_SVC;
+    servicepriority[3] = WMI_DATA_BE_SVC;
+    servicepriority[4] = WMI_DATA_BK_SVC; /* lowest */
+
+        /* set callbacks and priority list */
+    HTCSetCreditDistribution(HTCHandle,
+                             pCredInfo,
+                             ar6000_credit_distribute,
+                             ar6000_credit_init,
+                             servicepriority,
+                             5);
+
+    return A_OK;
+}
+
diff --git a/drivers/net/ath6kl/miscdrv/miscdrv.h b/drivers/net/ath6kl/miscdrv/miscdrv.h
new file mode 100644
index 00000000000..ae24b728c4a
--- /dev/null
+++ b/drivers/net/ath6kl/miscdrv/miscdrv.h
@@ -0,0 +1,42 @@
+//------------------------------------------------------------------------------
+// <copyright file="miscdrv.h" company="Atheros">
+//    Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _MISCDRV_H
+#define _MISCDRV_H
+
+
+#define HOST_INTEREST_ITEM_ADDRESS(target, item)    \
+   AR6002_HOST_INTEREST_ITEM_ADDRESS(item)
+
+A_UINT32 ar6kRev2Array[][128]   = {
+                                    {0xFFFF, 0xFFFF},      // No Patches
+                               };
+
+#define CFG_REV2_ITEMS                0     // no patches so far
+#define AR6K_RESET_ADDR               0x4000
+#define AR6K_RESET_VAL                0x100
+
+#define EEPROM_SZ                     768
+#define EEPROM_WAIT_LIMIT             4
+
+#endif
+
diff --git a/drivers/net/ath6kl/os/linux/ar6000_android.c b/drivers/net/ath6kl/os/linux/ar6000_android.c
new file mode 100644
index 00000000000..a588825b9da
--- /dev/null
+++ b/drivers/net/ath6kl/os/linux/ar6000_android.c
@@ -0,0 +1,413 @@
+//------------------------------------------------------------------------------
+// Copyright (c) 2004-2010 Atheros Communications Inc.
+// All rights reserved.
+//
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//
+// Author(s): ="Atheros"
+//------------------------------------------------------------------------------
+#include "ar6000_drv.h"
+#include "htc.h"
+#include <linux/vmalloc.h>
+#include <linux/fs.h>
+
+#ifdef CONFIG_HAS_WAKELOCK
+#include <linux/wakelock.h>
+#endif
+#ifdef CONFIG_HAS_EARLYSUSPEND
+#include <linux/earlysuspend.h>
+#endif
+
+A_BOOL enable_mmc_host_detect_change = 0;
+static void ar6000_enable_mmchost_detect_change(int enable);
+
+
+char fwpath[256] = "/system/wifi";
+int wowledon;
+unsigned int enablelogcat;
+
+extern int bmienable;
+extern struct net_device *ar6000_devices[];
+extern char ifname[];
+
+#ifdef CONFIG_HAS_WAKELOCK
+extern struct wake_lock ar6k_wow_wake_lock;
+struct wake_lock ar6k_init_wake_lock;
+#endif
+
+const char def_ifname[] = "wlan0";
+module_param_string(fwpath, fwpath, sizeof(fwpath), 0644);
+module_param(enablelogcat, uint, 0644);
+module_param(wowledon, int, 0644);
+
+#ifdef CONFIG_HAS_EARLYSUSPEND
+static int screen_is_off;
+static struct early_suspend ar6k_early_suspend;
+#endif
+
+static A_STATUS (*ar6000_avail_ev_p)(void *, void *);
+
+#if defined(CONFIG_ANDROID_LOGGER) && (!defined(CONFIG_MMC_MSM))
+int logger_write(const enum logidx index,
+                const unsigned char prio,
+                const char __kernel * const tag,
+                const char __kernel * const fmt,
+                ...)
+{
+    int ret = 0;
+    va_list vargs;
+    struct file *filp = (struct file *)-ENOENT;
+    mm_segment_t oldfs;
+    struct iovec vec[3];
+    int tag_bytes = strlen(tag) + 1, msg_bytes;
+    char *msg;      
+    va_start(vargs, fmt);
+    msg = kvasprintf(GFP_ATOMIC, fmt, vargs);
+    va_end(vargs);
+    if (!msg)
+        return -ENOMEM;
+    if (in_interrupt()) {
+        /* we have no choice since aio_write may be blocked */
+        printk(KERN_ALERT "%s", msg);
+        goto out_free_message;
+    }
+    msg_bytes = strlen(msg) + 1;
+    if (msg_bytes <= 1) /* empty message? */
+        goto out_free_message; /* don't bother, then */
+    if ((msg_bytes + tag_bytes + 1) > 2048) {
+        ret = -E2BIG;
+        goto out_free_message;
+    }
+            
+    vec[0].iov_base  = (unsigned char *) &prio;
+    vec[0].iov_len    = 1;
+    vec[1].iov_base   = (void *) tag;
+    vec[1].iov_len    = strlen(tag) + 1;
+    vec[2].iov_base   = (void *) msg;
+    vec[2].iov_len    = strlen(msg) + 1; 
+
+    oldfs = get_fs();
+    set_fs(KERNEL_DS);
+    do {
+        filp = filp_open("/dev/log/main", O_WRONLY, S_IRUSR);
+        if (IS_ERR(filp) || !filp->f_op) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: filp_open /dev/log/main error\n", __FUNCTION__));
+            ret = -ENOENT;
+            break;
+        }
+
+        if (filp->f_op->aio_write) {
+            int nr_segs = sizeof(vec) / sizeof(vec[0]);
+            int len = vec[0].iov_len + vec[1].iov_len + vec[2].iov_len;
+            struct kiocb kiocb;
+            init_sync_kiocb(&kiocb, filp);
+            kiocb.ki_pos = 0;
+            kiocb.ki_left = len;
+            kiocb.ki_nbytes = len;
+            ret = filp->f_op->aio_write(&kiocb, vec, nr_segs, kiocb.ki_pos);
+        }
+        
+    } while (0);
+
+    if (!IS_ERR(filp)) {
+        filp_close(filp, NULL);
+    }
+    set_fs(oldfs);
+out_free_message:
+    if (msg) {
+        kfree(msg);
+    }
+    return ret;
+}
+#endif
+
+int android_logger_lv(void *module, int mask)
+{
+    switch (mask) {
+    case ATH_DEBUG_ERR:
+        return 6;
+    case ATH_DEBUG_INFO:
+        return 4;
+    case ATH_DEBUG_WARN:
+        return 5; 
+    case ATH_DEBUG_TRC:        
+        return 3; 
+    default:
+#ifdef DEBUG
+        if (!module) {
+            return 3;
+        } else if (module == &GET_ATH_MODULE_DEBUG_VAR_NAME(driver)) {
+            return (mask <=ATH_DEBUG_MAKE_MODULE_MASK(3)) ? 3 : 2;
+        } else if (module == &GET_ATH_MODULE_DEBUG_VAR_NAME(htc)) {
+            return 2;
+        } else {
+            return 3;
+        }
+#else
+        return 3; /* DEBUG */
+#endif
+    }
+}
+
+static int android_readwrite_file(const A_CHAR *filename, A_CHAR *rbuf, const A_CHAR *wbuf, size_t length)
+{
+    int ret = 0;
+    struct file *filp = (struct file *)-ENOENT;
+    mm_segment_t oldfs;
+    oldfs = get_fs();
+    set_fs(KERNEL_DS);
+    do {
+        int mode = (wbuf) ? O_RDWR : O_RDONLY;
+        filp = filp_open(filename, mode, S_IRUSR);
+        if (IS_ERR(filp) || !filp->f_op) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: file %s filp_open error\n", __FUNCTION__, filename));
+            ret = -ENOENT;
+            break;
+        }
+    
+        if (length==0) {
+            /* Read the length of the file only */
+            struct inode    *inode;
+
+            inode = GET_INODE_FROM_FILEP(filp);
+            if (!inode) {
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Get inode from %s failed\n", __FUNCTION__, filename));
+                ret = -ENOENT;
+                break;
+            }
+            ret = i_size_read(inode->i_mapping->host);
+            break;
+        }
+
+        if (wbuf) {
+            if ( (ret=filp->f_op->write(filp, wbuf, length, &filp->f_pos)) < 0) {
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Write %u bytes to file %s error %d\n", __FUNCTION__, 
+                                length, filename, ret));
+                break;
+            }
+        } else {
+            if ( (ret=filp->f_op->read(filp, rbuf, length, &filp->f_pos)) < 0) {
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Read %u bytes from file %s error %d\n", __FUNCTION__,
+                                length, filename, ret));
+                break;
+            }
+        }
+    } while (0);
+
+    if (!IS_ERR(filp)) {
+        filp_close(filp, NULL);
+    }
+    set_fs(oldfs);
+
+    return ret;
+}
+
+int android_request_firmware(const struct firmware **firmware_p, const char *name,
+                     struct device *device)
+{
+    int ret = 0;
+    struct firmware *firmware;
+    char filename[256];
+    const char *raw_filename = name;
+	*firmware_p = firmware = kzalloc(sizeof(*firmware), GFP_KERNEL);
+    if (!firmware) 
+		return -ENOMEM;
+	sprintf(filename, "%s/%s", fwpath, raw_filename);
+    do {
+        size_t length, bufsize, bmisize;
+
+        if ( (ret=android_readwrite_file(filename, NULL, NULL, 0)) < 0) {
+            break;
+        } else {
+            length = ret;
+        }
+    
+        bufsize = ALIGN(length, PAGE_SIZE);
+        bmisize = A_ROUND_UP(length, 4);
+        bufsize = max(bmisize, bufsize);
+        firmware->data = vmalloc(bufsize);
+        firmware->size = length;
+        if (!firmware->data) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("%s: Cannot allocate buffer for firmware\n", __FUNCTION__));
+            ret = -ENOMEM;
+            break;
+        }
+    
+        if ( (ret=android_readwrite_file(filename, (char*)firmware->data, NULL, length)) != length) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("%s: file read error, ret %d request %d\n", __FUNCTION__, ret, length));
+            ret = -1;
+            break;
+        }
+    
+    } while (0);
+
+    if (ret<0) {
+        if (firmware) {
+            if (firmware->data)
+                vfree(firmware->data);
+            kfree(firmware);
+        }
+        *firmware_p = NULL;
+    } else {
+        ret = 0;
+    }
+    return ret;    
+}
+
+void android_release_firmware(const struct firmware *firmware)
+{
+	if (firmware) {
+        if (firmware->data)
+            vfree(firmware->data);
+        kfree(firmware);
+    }
+}
+
+static A_STATUS ar6000_android_avail_ev(void *context, void *hif_handle)
+{
+    A_STATUS ret;    
+#ifdef CONFIG_HAS_WAKELOCK
+    wake_lock(&ar6k_init_wake_lock);
+#endif
+    ar6000_enable_mmchost_detect_change(0);
+    ret = ar6000_avail_ev_p(context, hif_handle);
+#ifdef CONFIG_HAS_WAKELOCK
+    wake_unlock(&ar6k_init_wake_lock);
+#endif
+    return ret;
+}
+
+/* Useful for qualcom platform to detect our wlan card for mmc stack */
+static void ar6000_enable_mmchost_detect_change(int enable)
+{
+#ifdef CONFIG_MMC_MSM
+#define MMC_MSM_DEV "msm_sdcc.1"
+    char buf[3];
+    int length;
+
+    if (!enable_mmc_host_detect_change) {
+        return;
+    }
+    length = snprintf(buf, sizeof(buf), "%d\n", enable ? 1 : 0);
+    if (android_readwrite_file("/sys/devices/platform/" MMC_MSM_DEV "/detect_change", 
+                               NULL, buf, length) < 0) {
+        /* fall back to polling */
+        android_readwrite_file("/sys/devices/platform/" MMC_MSM_DEV "/polling", NULL, buf, length);
+    }
+#endif
+}
+
+#ifdef CONFIG_HAS_EARLYSUSPEND
+static void android_early_suspend(struct early_suspend *h)
+{
+    screen_is_off = 1;
+}
+
+static void android_late_resume(struct early_suspend *h)
+{
+    screen_is_off = 0;
+}
+#endif
+
+void android_module_init(OSDRV_CALLBACKS *osdrvCallbacks)
+{
+    bmienable = 1;
+    if (ifname[0] == '\0')
+        strcpy(ifname, def_ifname);
+#ifdef CONFIG_HAS_WAKELOCK
+    wake_lock_init(&ar6k_init_wake_lock, WAKE_LOCK_SUSPEND, "ar6k_init");
+#endif
+#ifdef CONFIG_HAS_EARLYSUSPEND
+    ar6k_early_suspend.suspend = android_early_suspend;
+    ar6k_early_suspend.resume  = android_late_resume;
+    ar6k_early_suspend.level   = EARLY_SUSPEND_LEVEL_BLANK_SCREEN;
+    register_early_suspend(&ar6k_early_suspend);
+#endif
+
+    ar6000_avail_ev_p = osdrvCallbacks->deviceInsertedHandler;
+    osdrvCallbacks->deviceInsertedHandler = ar6000_android_avail_ev;
+
+    ar6000_enable_mmchost_detect_change(1);
+}
+
+void android_module_exit(void)
+{
+#ifdef CONFIG_HAS_EARLYSUSPEND
+    unregister_early_suspend(&ar6k_early_suspend);
+#endif
+#ifdef CONFIG_HAS_WAKELOCK
+    wake_lock_destroy(&ar6k_init_wake_lock);
+#endif
+    ar6000_enable_mmchost_detect_change(1);
+}
+
+#ifdef CONFIG_PM
+void android_ar6k_check_wow_status(AR_SOFTC_T *ar, struct sk_buff *skb, A_BOOL isEvent)
+{
+    if (
+#ifdef CONFIG_HAS_EARLYSUSPEND
+        screen_is_off && 
+#endif 
+            skb && ar->arConnected) {
+        A_BOOL needWake = FALSE;
+        if (isEvent) {
+            if (A_NETBUF_LEN(skb) >= sizeof(A_UINT16)) {
+                A_UINT16 cmd = *(const A_UINT16 *)A_NETBUF_DATA(skb);
+                switch (cmd) {
+                case WMI_CONNECT_EVENTID:
+                case WMI_DISCONNECT_EVENTID:
+                    needWake = TRUE;
+                    break;
+                default:
+                    /* dont wake lock the system for other event */
+                    break;
+                }
+            }
+        } else if (A_NETBUF_LEN(skb) >= sizeof(ATH_MAC_HDR)) {
+            ATH_MAC_HDR *datap = (ATH_MAC_HDR *)A_NETBUF_DATA(skb);
+            if (!IEEE80211_IS_MULTICAST(datap->dstMac)) {
+                switch (A_BE2CPU16(datap->typeOrLen)) {
+                case 0x0800: /* IP */
+                case 0x888e: /* EAPOL */
+                case 0x88c7: /* RSN_PREAUTH */
+                case 0x88b4: /* WAPI */
+                     needWake = TRUE;
+                     break;
+                case 0x0806: /* ARP is not important to hold wake lock */
+                default:
+                    break;
+                }
+            }
+        }
+        if (needWake) {
+            /* keep host wake up if there is any event and packate comming in*/
+#ifdef CONFIG_HAS_WAKELOCK
+            wake_lock_timeout(&ar6k_wow_wake_lock, 3*HZ);
+#endif
+            if (wowledon) {
+                char buf[32];
+                int len = sprintf(buf, "on");
+                android_readwrite_file("/sys/power/state", NULL, buf, len);
+
+                len = sprintf(buf, "%d", 127);
+                android_readwrite_file("/sys/class/leds/lcd-backlight/brightness",
+                                       NULL, buf,len);
+            }
+        }
+    }
+}
+#endif /* CONFIG_PM */
diff --git a/drivers/net/ath6kl/os/linux/ar6000_drv.c b/drivers/net/ath6kl/os/linux/ar6000_drv.c
new file mode 100644
index 00000000000..126a36a2daa
--- /dev/null
+++ b/drivers/net/ath6kl/os/linux/ar6000_drv.c
@@ -0,0 +1,6444 @@
+//------------------------------------------------------------------------------
+// Copyright (c) 2004-2010 Atheros Communications Inc.
+// All rights reserved.
+//
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//
+// Author(s): ="Atheros"
+//------------------------------------------------------------------------------
+
+/*
+ * This driver is a pseudo ethernet driver to access the Atheros AR6000
+ * WLAN Device
+ */
+
+#include "ar6000_drv.h"
+#ifdef ATH6K_CONFIG_CFG80211
+#include "cfg80211.h"
+#endif /* ATH6K_CONFIG_CFG80211 */
+#include "htc.h"
+#include "wmi_filter_linux.h"
+#include "epping_test.h"
+#include "wlan_config.h"
+#include "ar3kconfig.h"
+#include "ar6k_pal.h"
+#include "AR6002/addrs.h"
+
+
+/* LINUX_HACK_FUDGE_FACTOR -- this is used to provide a workaround for linux behavior.  When
+ *  the meta data was added to the header it was found that linux did not correctly provide
+ *  enough headroom.  However when more headroom was requested beyond what was truly needed
+ *  Linux gave the requested headroom. Therefore to get the necessary headroom from Linux
+ *  the driver requests more than is needed by the amount = LINUX_HACK_FUDGE_FACTOR */
+#define LINUX_HACK_FUDGE_FACTOR 16
+#define BDATA_BDADDR_OFFSET     28
+
+A_UINT8 bcast_mac[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+A_UINT8 null_mac[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+
+#ifdef DEBUG
+
+#define  ATH_DEBUG_DBG_LOG       ATH_DEBUG_MAKE_MODULE_MASK(0)
+#define  ATH_DEBUG_WLAN_CONNECT  ATH_DEBUG_MAKE_MODULE_MASK(1)
+#define  ATH_DEBUG_WLAN_SCAN     ATH_DEBUG_MAKE_MODULE_MASK(2)
+#define  ATH_DEBUG_WLAN_TX       ATH_DEBUG_MAKE_MODULE_MASK(3)
+#define  ATH_DEBUG_WLAN_RX       ATH_DEBUG_MAKE_MODULE_MASK(4)
+#define  ATH_DEBUG_HTC_RAW       ATH_DEBUG_MAKE_MODULE_MASK(5)
+#define  ATH_DEBUG_HCI_BRIDGE    ATH_DEBUG_MAKE_MODULE_MASK(6)
+
+static ATH_DEBUG_MASK_DESCRIPTION driver_debug_desc[] = {
+    { ATH_DEBUG_DBG_LOG      , "Target Debug Logs"},
+    { ATH_DEBUG_WLAN_CONNECT , "WLAN connect"},
+    { ATH_DEBUG_WLAN_SCAN    , "WLAN scan"},
+    { ATH_DEBUG_WLAN_TX      , "WLAN Tx"},
+    { ATH_DEBUG_WLAN_RX      , "WLAN Rx"},
+    { ATH_DEBUG_HTC_RAW      , "HTC Raw IF tracing"},
+    { ATH_DEBUG_HCI_BRIDGE   , "HCI Bridge Setup"},
+    { ATH_DEBUG_HCI_RECV     , "HCI Recv tracing"},
+    { ATH_DEBUG_HCI_DUMP     , "HCI Packet dumps"},
+};
+
+ATH_DEBUG_INSTANTIATE_MODULE_VAR(driver,
+                                 "driver",
+                                 "Linux Driver Interface",
+                                 ATH_DEBUG_MASK_DEFAULTS | ATH_DEBUG_WLAN_SCAN |
+                                 ATH_DEBUG_HCI_BRIDGE,
+                                 ATH_DEBUG_DESCRIPTION_COUNT(driver_debug_desc),
+                                 driver_debug_desc);
+
+#endif
+
+
+#define IS_MAC_NULL(mac) (mac[0]==0 && mac[1]==0 && mac[2]==0 && mac[3]==0 && mac[4]==0 && mac[5]==0)
+#define IS_MAC_BCAST(mac) (*mac==0xff)
+
+#define DESCRIPTION "Driver to access the Atheros AR600x Device, version " __stringify(__VER_MAJOR_) "." __stringify(__VER_MINOR_) "." __stringify(__VER_PATCH_) "." __stringify(__BUILD_NUMBER_)
+
+MODULE_AUTHOR("Atheros Communications, Inc.");
+MODULE_DESCRIPTION(DESCRIPTION);
+MODULE_LICENSE("Dual BSD/GPL");
+
+#ifndef REORG_APTC_HEURISTICS
+#undef ADAPTIVE_POWER_THROUGHPUT_CONTROL
+#endif /* REORG_APTC_HEURISTICS */
+
+#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL
+#define APTC_TRAFFIC_SAMPLING_INTERVAL     100  /* msec */
+#define APTC_UPPER_THROUGHPUT_THRESHOLD    3000 /* Kbps */
+#define APTC_LOWER_THROUGHPUT_THRESHOLD    2000 /* Kbps */
+
+typedef struct aptc_traffic_record {
+    A_BOOL timerScheduled;
+    struct timeval samplingTS;
+    unsigned long bytesReceived;
+    unsigned long bytesTransmitted;
+} APTC_TRAFFIC_RECORD;
+
+A_TIMER aptcTimer;
+APTC_TRAFFIC_RECORD aptcTR;
+#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */
+
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+// callbacks registered by HCI transport driver
+HCI_TRANSPORT_CALLBACKS ar6kHciTransCallbacks = { NULL };
+#endif
+
+unsigned int processDot11Hdr = 0;
+int bmienable = BMIENABLE_DEFAULT;
+
+char ifname[IFNAMSIZ] = {0,};
+
+int wlaninitmode = WLAN_INIT_MODE_DEFAULT;
+unsigned int bypasswmi = 0;
+unsigned int debuglevel = 0;
+int tspecCompliance = ATHEROS_COMPLIANCE;
+unsigned int busspeedlow = 0;
+unsigned int onebitmode = 0;
+unsigned int skipflash = 0;
+unsigned int wmitimeout = 2;
+unsigned int wlanNodeCaching = 1;
+unsigned int enableuartprint = ENABLEUARTPRINT_DEFAULT;
+unsigned int logWmiRawMsgs = 0;
+unsigned int enabletimerwar = 0;
+unsigned int fwmode = 1;
+unsigned int mbox_yield_limit = 99;
+unsigned int enablerssicompensation = 0;
+int reduce_credit_dribble = 1 + HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_HALF;
+int allow_trace_signal = 0;
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+unsigned int testmode =0;
+#endif
+
+unsigned int irqprocmode = HIF_DEVICE_IRQ_SYNC_ONLY;//HIF_DEVICE_IRQ_ASYNC_SYNC;
+unsigned int panic_on_assert = 1;
+unsigned int nohifscattersupport = NOHIFSCATTERSUPPORT_DEFAULT;
+
+unsigned int setuphci = SETUPHCI_DEFAULT;
+unsigned int setuphcipal = SETUPHCIPAL_DEFAULT;
+unsigned int loghci = 0;
+unsigned int setupbtdev = SETUPBTDEV_DEFAULT;
+#ifndef EXPORT_HCI_BRIDGE_INTERFACE
+unsigned int ar3khcibaud = AR3KHCIBAUD_DEFAULT;
+unsigned int hciuartscale = HCIUARTSCALE_DEFAULT;
+unsigned int hciuartstep = HCIUARTSTEP_DEFAULT;
+#endif
+#ifdef CONFIG_CHECKSUM_OFFLOAD
+unsigned int csumOffload=0;
+unsigned int csumOffloadTest=0;
+#endif
+unsigned int eppingtest=0;
+
+module_param_string(ifname, ifname, sizeof(ifname), 0644);
+module_param(wlaninitmode, int, 0644);
+module_param(bmienable, int, 0644);
+module_param(bypasswmi, uint, 0644);
+module_param(debuglevel, uint, 0644);
+module_param(tspecCompliance, int, 0644);
+module_param(onebitmode, uint, 0644);
+module_param(busspeedlow, uint, 0644);
+module_param(skipflash, uint, 0644);
+module_param(wmitimeout, uint, 0644);
+module_param(wlanNodeCaching, uint, 0644);
+module_param(logWmiRawMsgs, uint, 0644);
+module_param(enableuartprint, uint, 0644);
+module_param(enabletimerwar, uint, 0644);
+module_param(fwmode, uint, 0644);
+module_param(mbox_yield_limit, uint, 0644);
+module_param(reduce_credit_dribble, int, 0644);
+module_param(allow_trace_signal, int, 0644);
+module_param(enablerssicompensation, uint, 0644);
+module_param(processDot11Hdr, uint, 0644);
+#ifdef CONFIG_CHECKSUM_OFFLOAD
+module_param(csumOffload, uint, 0644);
+#endif
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+module_param(testmode, uint, 0644);
+#endif
+module_param(irqprocmode, uint, 0644);
+module_param(nohifscattersupport, uint, 0644);
+module_param(panic_on_assert, uint, 0644);
+module_param(setuphci, uint, 0644);
+module_param(setuphcipal, uint, 0644);
+module_param(loghci, uint, 0644);
+module_param(setupbtdev, uint, 0644);
+#ifndef EXPORT_HCI_BRIDGE_INTERFACE
+module_param(ar3khcibaud, uint, 0644);
+module_param(hciuartscale, uint, 0644);
+module_param(hciuartstep, uint, 0644);
+#endif
+module_param(eppingtest, uint, 0644);
+
+/* in 2.6.10 and later this is now a pointer to a uint */
+unsigned int _mboxnum = HTC_MAILBOX_NUM_MAX;
+#define mboxnum &_mboxnum
+
+#ifdef DEBUG
+A_UINT32 g_dbg_flags = DBG_DEFAULTS;
+unsigned int debugflags = 0;
+int debugdriver = 0;
+unsigned int debughtc = 0;
+unsigned int debugbmi = 0;
+unsigned int debughif = 0;
+unsigned int txcreditsavailable[HTC_MAILBOX_NUM_MAX] = {0};
+unsigned int txcreditsconsumed[HTC_MAILBOX_NUM_MAX] = {0};
+unsigned int txcreditintrenable[HTC_MAILBOX_NUM_MAX] = {0};
+unsigned int txcreditintrenableaggregate[HTC_MAILBOX_NUM_MAX] = {0};
+module_param(debugflags, uint, 0644);
+module_param(debugdriver, int, 0644);
+module_param(debughtc, uint, 0644);
+module_param(debugbmi, uint, 0644);
+module_param(debughif, uint, 0644);
+module_param_array(txcreditsavailable, uint, mboxnum, 0644);
+module_param_array(txcreditsconsumed, uint, mboxnum, 0644);
+module_param_array(txcreditintrenable, uint, mboxnum, 0644);
+module_param_array(txcreditintrenableaggregate, uint, mboxnum, 0644);
+
+#endif /* DEBUG */
+
+unsigned int resetok = 1;
+unsigned int tx_attempt[HTC_MAILBOX_NUM_MAX] = {0};
+unsigned int tx_post[HTC_MAILBOX_NUM_MAX] = {0};
+unsigned int tx_complete[HTC_MAILBOX_NUM_MAX] = {0};
+unsigned int hifBusRequestNumMax = 40;
+unsigned int war23838_disabled = 0;
+#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL
+unsigned int enableAPTCHeuristics = 1;
+#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */
+module_param_array(tx_attempt, uint, mboxnum, 0644);
+module_param_array(tx_post, uint, mboxnum, 0644);
+module_param_array(tx_complete, uint, mboxnum, 0644);
+module_param(hifBusRequestNumMax, uint, 0644);
+module_param(war23838_disabled, uint, 0644);
+module_param(resetok, uint, 0644);
+#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL
+module_param(enableAPTCHeuristics, uint, 0644);
+#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */
+
+#ifdef BLOCK_TX_PATH_FLAG
+int blocktx = 0;
+module_param(blocktx, int, 0644);
+#endif /* BLOCK_TX_PATH_FLAG */
+
+typedef struct user_rssi_compensation_t {
+    A_UINT16         customerID;
+    union {
+    A_UINT16         a_enable;
+    A_UINT16         bg_enable;
+    A_UINT16         enable;
+    };
+    A_INT16          bg_param_a;
+    A_INT16          bg_param_b;
+    A_INT16          a_param_a;
+    A_INT16          a_param_b;
+    A_UINT32         reserved;
+} USER_RSSI_CPENSATION;
+
+static USER_RSSI_CPENSATION rssi_compensation_param;
+
+static A_INT16 rssi_compensation_table[96];
+
+int reconnect_flag = 0;
+static ar6k_pal_config_t ar6k_pal_config_g;
+
+/* Function declarations */
+static int ar6000_init_module(void);
+static void ar6000_cleanup_module(void);
+
+int ar6000_init(struct net_device *dev);
+static int ar6000_open(struct net_device *dev);
+static int ar6000_close(struct net_device *dev);
+static void ar6000_init_control_info(AR_SOFTC_T *ar);
+static int ar6000_data_tx(struct sk_buff *skb, struct net_device *dev);
+
+void ar6000_destroy(struct net_device *dev, unsigned int unregister);
+static void ar6000_detect_error(unsigned long ptr);
+static void	ar6000_set_multicast_list(struct net_device *dev);
+static struct net_device_stats *ar6000_get_stats(struct net_device *dev);
+static struct iw_statistics *ar6000_get_iwstats(struct net_device * dev);
+
+static void disconnect_timer_handler(unsigned long ptr);
+
+void read_rssi_compensation_param(AR_SOFTC_T *ar);
+
+    /* for android builds we call external APIs that handle firmware download and configuration */
+#ifdef ANDROID_ENV
+/* !!!! Interim android support to make it easier to patch the default driver for
+ * android use. You must define an external source file ar6000_android.c that handles the following
+ * APIs */
+extern void android_module_init(OSDRV_CALLBACKS *osdrvCallbacks);
+extern void android_module_exit(void);
+#endif
+/*
+ * HTC service connection handlers
+ */
+static A_STATUS ar6000_avail_ev(void *context, void *hif_handle);
+
+static A_STATUS ar6000_unavail_ev(void *context, void *hif_handle);
+
+A_STATUS ar6000_configure_target(AR_SOFTC_T *ar);
+
+static void ar6000_target_failure(void *Instance, A_STATUS Status);
+
+static void ar6000_rx(void *Context, HTC_PACKET *pPacket);
+
+static void ar6000_rx_refill(void *Context,HTC_ENDPOINT_ID Endpoint);
+
+static void ar6000_tx_complete(void *Context, HTC_PACKET_QUEUE *pPackets);
+
+static HTC_SEND_FULL_ACTION ar6000_tx_queue_full(void *Context, HTC_PACKET *pPacket);
+
+#ifdef ATH_AR6K_11N_SUPPORT
+static void ar6000_alloc_netbufs(A_NETBUF_QUEUE_T *q, A_UINT16 num);
+#endif
+static void ar6000_deliver_frames_to_nw_stack(void * dev, void *osbuf);
+//static void ar6000_deliver_frames_to_bt_stack(void * dev, void *osbuf);
+
+static HTC_PACKET *ar6000_alloc_amsdu_rxbuf(void *Context, HTC_ENDPOINT_ID Endpoint, int Length);
+
+static void ar6000_refill_amsdu_rxbufs(AR_SOFTC_T *ar, int Count);
+
+static void ar6000_cleanup_amsdu_rxbufs(AR_SOFTC_T *ar);
+
+static ssize_t
+ar6000_sysfs_bmi_read(struct file *fp, struct kobject *kobj,
+                      struct bin_attribute *bin_attr,
+                      char *buf, loff_t pos, size_t count);
+
+static ssize_t
+ar6000_sysfs_bmi_write(struct file *fp, struct kobject *kobj,
+                       struct bin_attribute *bin_attr,
+                       char *buf, loff_t pos, size_t count);
+
+static A_STATUS
+ar6000_sysfs_bmi_init(AR_SOFTC_T *ar);
+
+/* HCI PAL callback function declarations */
+A_STATUS ar6k_setup_hci_pal(AR_SOFTC_T *ar);
+void  ar6k_cleanup_hci_pal(AR_SOFTC_T *ar);
+
+static void
+ar6000_sysfs_bmi_deinit(AR_SOFTC_T *ar);
+
+A_STATUS
+ar6000_sysfs_bmi_get_config(AR_SOFTC_T *ar, A_UINT32 mode);
+
+/*
+ * Static variables
+ */
+
+struct net_device *ar6000_devices[MAX_AR6000];
+static int is_netdev_registered;
+extern struct iw_handler_def ath_iw_handler_def;
+DECLARE_WAIT_QUEUE_HEAD(arEvent);
+static void ar6000_cookie_init(AR_SOFTC_T *ar);
+static void ar6000_cookie_cleanup(AR_SOFTC_T *ar);
+static void ar6000_free_cookie(AR_SOFTC_T *ar, struct ar_cookie * cookie);
+static struct ar_cookie *ar6000_alloc_cookie(AR_SOFTC_T *ar);
+
+#ifdef USER_KEYS
+static A_STATUS ar6000_reinstall_keys(AR_SOFTC_T *ar,A_UINT8 key_op_ctrl);
+#endif
+
+#ifdef CONFIG_AP_VIRTUAL_ADAPTER_SUPPORT
+struct net_device *arApNetDev;
+#endif /* CONFIG_AP_VIRTUAL_ADAPTER_SUPPORT */
+
+static struct ar_cookie s_ar_cookie_mem[MAX_COOKIE_NUM];
+
+#define HOST_INTEREST_ITEM_ADDRESS(ar, item) \
+        (((ar)->arTargetType == TARGET_TYPE_AR6002) ? AR6002_HOST_INTEREST_ITEM_ADDRESS(item) : \
+        (((ar)->arTargetType == TARGET_TYPE_AR6003) ? AR6003_HOST_INTEREST_ITEM_ADDRESS(item) : 0))
+
+
+static struct net_device_ops ar6000_netdev_ops = {
+    .ndo_init               = NULL,
+    .ndo_open               = ar6000_open,
+    .ndo_stop               = ar6000_close,
+    .ndo_get_stats          = ar6000_get_stats,
+    .ndo_do_ioctl           = ar6000_ioctl,
+    .ndo_start_xmit         = ar6000_data_tx,
+    .ndo_set_multicast_list = ar6000_set_multicast_list,
+};
+
+/* Debug log support */
+
+/*
+ * Flag to govern whether the debug logs should be parsed in the kernel
+ * or reported to the application.
+ */
+#define REPORT_DEBUG_LOGS_TO_APP
+
+A_STATUS
+ar6000_set_host_app_area(AR_SOFTC_T *ar)
+{
+    A_UINT32 address, data;
+    struct host_app_area_s host_app_area;
+
+    /* Fetch the address of the host_app_area_s instance in the host interest area */
+    address = TARG_VTOP(ar->arTargetType, HOST_INTEREST_ITEM_ADDRESS(ar, hi_app_host_interest));
+    if (ar6000_ReadRegDiag(ar->arHifDevice, &address, &data) != A_OK) {
+        return A_ERROR;
+    }
+    address = TARG_VTOP(ar->arTargetType, data);
+    host_app_area.wmi_protocol_ver = WMI_PROTOCOL_VERSION;
+    if (ar6000_WriteDataDiag(ar->arHifDevice, address,
+                             (A_UCHAR *)&host_app_area,
+                             sizeof(struct host_app_area_s)) != A_OK)
+    {
+        return A_ERROR;
+    }
+
+    return A_OK;
+}
+
+A_UINT32
+dbglog_get_debug_hdr_ptr(AR_SOFTC_T *ar)
+{
+    A_UINT32 param;
+    A_UINT32 address;
+    A_STATUS status;
+
+    address = TARG_VTOP(ar->arTargetType, HOST_INTEREST_ITEM_ADDRESS(ar, hi_dbglog_hdr));
+    if ((status = ar6000_ReadDataDiag(ar->arHifDevice, address,
+                                      (A_UCHAR *)&param, 4)) != A_OK)
+    {
+        param = 0;
+    }
+
+    return param;
+}
+
+/*
+ * The dbglog module has been initialized. Its ok to access the relevant
+ * data stuctures over the diagnostic window.
+ */
+void
+ar6000_dbglog_init_done(AR_SOFTC_T *ar)
+{
+    ar->dbglog_init_done = TRUE;
+}
+
+A_UINT32
+dbglog_get_debug_fragment(A_INT8 *datap, A_UINT32 len, A_UINT32 limit)
+{
+    A_INT32 *buffer;
+    A_UINT32 count;
+    A_UINT32 numargs;
+    A_UINT32 length;
+    A_UINT32 fraglen;
+
+    count = fraglen = 0;
+    buffer = (A_INT32 *)datap;
+    length = (limit >> 2);
+
+    if (len <= limit) {
+        fraglen = len;
+    } else {
+        while (count < length) {
+            numargs = DBGLOG_GET_NUMARGS(buffer[count]);
+            fraglen = (count << 2);
+            count += numargs + 1;
+        }
+    }
+
+    return fraglen;
+}
+
+void
+dbglog_parse_debug_logs(A_INT8 *datap, A_UINT32 len)
+{
+    A_INT32 *buffer;
+    A_UINT32 count;
+    A_UINT32 timestamp;
+    A_UINT32 debugid;
+    A_UINT32 moduleid;
+    A_UINT32 numargs;
+    A_UINT32 length;
+
+    count = 0;
+    buffer = (A_INT32 *)datap;
+    length = (len >> 2);
+    while (count < length) {
+        debugid = DBGLOG_GET_DBGID(buffer[count]);
+        moduleid = DBGLOG_GET_MODULEID(buffer[count]);
+        numargs = DBGLOG_GET_NUMARGS(buffer[count]);
+        timestamp = DBGLOG_GET_TIMESTAMP(buffer[count]);
+        switch (numargs) {
+            case 0:
+            AR_DEBUG_PRINTF(ATH_DEBUG_DBG_LOG,("%d %d (%d)\n", moduleid, debugid, timestamp));
+            break;
+
+            case 1:
+            AR_DEBUG_PRINTF(ATH_DEBUG_DBG_LOG,("%d %d (%d): 0x%x\n", moduleid, debugid,
+                            timestamp, buffer[count+1]));
+            break;
+
+            case 2:
+            AR_DEBUG_PRINTF(ATH_DEBUG_DBG_LOG,("%d %d (%d): 0x%x, 0x%x\n", moduleid, debugid,
+                            timestamp, buffer[count+1], buffer[count+2]));
+            break;
+
+            default:
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Invalid args: %d\n", numargs));
+        }
+        count += numargs + 1;
+    }
+}
+
+int
+ar6000_dbglog_get_debug_logs(AR_SOFTC_T *ar)
+{
+    A_UINT32 data[8]; /* Should be able to accomodate struct dbglog_buf_s */
+    A_UINT32 address;
+    A_UINT32 length;
+    A_UINT32 dropped;
+    A_UINT32 firstbuf;
+    A_UINT32 debug_hdr_ptr;
+
+    if (!ar->dbglog_init_done) return A_ERROR;
+
+
+    AR6000_SPIN_LOCK(&ar->arLock, 0);
+
+    if (ar->dbgLogFetchInProgress) {
+        AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+        return A_EBUSY;
+    }
+
+        /* block out others */
+    ar->dbgLogFetchInProgress = TRUE;
+
+    AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+
+    debug_hdr_ptr = dbglog_get_debug_hdr_ptr(ar);
+    printk("debug_hdr_ptr: 0x%x\n", debug_hdr_ptr);
+
+    /* Get the contents of the ring buffer */
+    if (debug_hdr_ptr) {
+        address = TARG_VTOP(ar->arTargetType, debug_hdr_ptr);
+        length = 4 /* sizeof(dbuf) */ + 4 /* sizeof(dropped) */;
+        A_MEMZERO(data, sizeof(data));
+        ar6000_ReadDataDiag(ar->arHifDevice, address, (A_UCHAR *)data, length);
+        address = TARG_VTOP(ar->arTargetType, data[0] /* dbuf */);
+        firstbuf = address;
+        dropped = data[1]; /* dropped */
+        length = 4 /* sizeof(next) */ + 4 /* sizeof(buffer) */ + 4 /* sizeof(bufsize) */ + 4 /* sizeof(length) */ + 4 /* sizeof(count) */ + 4 /* sizeof(free) */;
+        A_MEMZERO(data, sizeof(data));
+        ar6000_ReadDataDiag(ar->arHifDevice, address, (A_UCHAR *)&data, length);
+
+        do {
+            address = TARG_VTOP(ar->arTargetType, data[1] /* buffer*/);
+            length = data[3]; /* length */
+            if ((length) && (length <= data[2] /* bufsize*/)) {
+                /* Rewind the index if it is about to overrun the buffer */
+                if (ar->log_cnt > (DBGLOG_HOST_LOG_BUFFER_SIZE - length)) {
+                    ar->log_cnt = 0;
+                }
+                if(A_OK != ar6000_ReadDataDiag(ar->arHifDevice, address,
+                                    (A_UCHAR *)&ar->log_buffer[ar->log_cnt], length))
+                {
+                    break;
+                }
+                ar6000_dbglog_event(ar, dropped, (A_INT8*)&ar->log_buffer[ar->log_cnt], length);
+                ar->log_cnt += length;
+            } else {
+                AR_DEBUG_PRINTF(ATH_DEBUG_DBG_LOG,("Length: %d (Total size: %d)\n",
+                                data[3], data[2]));
+            }
+
+            address = TARG_VTOP(ar->arTargetType, data[0] /* next */);
+            length = 4 /* sizeof(next) */ + 4 /* sizeof(buffer) */ + 4 /* sizeof(bufsize) */ + 4 /* sizeof(length) */ + 4 /* sizeof(count) */ + 4 /* sizeof(free) */;
+            A_MEMZERO(data, sizeof(data));
+            if(A_OK != ar6000_ReadDataDiag(ar->arHifDevice, address,
+                                (A_UCHAR *)&data, length))
+            {
+                break;
+            }
+
+        } while (address != firstbuf);
+    }
+
+    ar->dbgLogFetchInProgress = FALSE;
+
+    return A_OK;
+}
+
+void
+ar6000_dbglog_event(AR_SOFTC_T *ar, A_UINT32 dropped,
+                    A_INT8 *buffer, A_UINT32 length)
+{
+#ifdef REPORT_DEBUG_LOGS_TO_APP
+    #define MAX_WIRELESS_EVENT_SIZE 252
+    /*
+     * Break it up into chunks of MAX_WIRELESS_EVENT_SIZE bytes of messages.
+     * There seems to be a limitation on the length of message that could be
+     * transmitted to the user app via this mechanism.
+     */
+    A_UINT32 send, sent;
+
+    sent = 0;
+    send = dbglog_get_debug_fragment(&buffer[sent], length - sent,
+                                     MAX_WIRELESS_EVENT_SIZE);
+    while (send) {
+        ar6000_send_event_to_app(ar, WMIX_DBGLOG_EVENTID, (A_UINT8*)&buffer[sent], send);
+        sent += send;
+        send = dbglog_get_debug_fragment(&buffer[sent], length - sent,
+                                         MAX_WIRELESS_EVENT_SIZE);
+    }
+#else
+    AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Dropped logs: 0x%x\nDebug info length: %d\n",
+                    dropped, length));
+
+    /* Interpret the debug logs */
+    dbglog_parse_debug_logs((A_INT8*)buffer, length);
+#endif /* REPORT_DEBUG_LOGS_TO_APP */
+}
+
+
+static int __init
+ar6000_init_module(void)
+{
+    static int probed = 0;
+    A_STATUS status;
+    OSDRV_CALLBACKS osdrvCallbacks;
+
+    a_module_debug_support_init();
+
+#ifdef DEBUG
+        /* check for debug mask overrides */
+    if (debughtc != 0) {
+        ATH_DEBUG_SET_DEBUG_MASK(htc,debughtc);
+    }
+    if (debugbmi != 0) {
+        ATH_DEBUG_SET_DEBUG_MASK(bmi,debugbmi);
+    }
+    if (debughif != 0) {
+        ATH_DEBUG_SET_DEBUG_MASK(hif,debughif);
+    }
+    if (debugdriver != 0) {
+        ATH_DEBUG_SET_DEBUG_MASK(driver,debugdriver);
+    }
+
+#endif
+
+    A_REGISTER_MODULE_DEBUG_INFO(driver);
+
+    A_MEMZERO(&osdrvCallbacks,sizeof(osdrvCallbacks));
+    osdrvCallbacks.deviceInsertedHandler = ar6000_avail_ev;
+    osdrvCallbacks.deviceRemovedHandler = ar6000_unavail_ev;
+#ifdef CONFIG_PM
+    osdrvCallbacks.deviceSuspendHandler = ar6000_suspend_ev;
+    osdrvCallbacks.deviceResumeHandler = ar6000_resume_ev;
+    osdrvCallbacks.devicePowerChangeHandler = ar6000_power_change_ev;
+#endif
+
+    ar6000_pm_init();
+
+#ifdef ANDROID_ENV
+    android_module_init(&osdrvCallbacks);
+#endif
+
+#ifdef DEBUG
+    /* Set the debug flags if specified at load time */
+    if(debugflags != 0)
+    {
+        g_dbg_flags = debugflags;
+    }
+#endif
+
+    if (probed) {
+        return -ENODEV;
+    }
+    probed++;
+
+#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL
+    memset(&aptcTR, 0, sizeof(APTC_TRAFFIC_RECORD));
+#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */
+
+#ifdef CONFIG_HOST_GPIO_SUPPORT
+    ar6000_gpio_init();
+#endif /* CONFIG_HOST_GPIO_SUPPORT */
+
+    status = HIFInit(&osdrvCallbacks);
+    if(status != A_OK)
+        return -ENODEV;
+
+    return 0;
+}
+
+static void __exit
+ar6000_cleanup_module(void)
+{
+    int i = 0;
+    struct net_device *ar6000_netdev;
+
+#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL
+    /* Delete the Adaptive Power Control timer */
+    if (timer_pending(&aptcTimer)) {
+        del_timer_sync(&aptcTimer);
+    }
+#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */
+
+    for (i=0; i < MAX_AR6000; i++) {
+        if (ar6000_devices[i] != NULL) {
+            ar6000_netdev = ar6000_devices[i];
+            ar6000_devices[i] = NULL;
+            ar6000_destroy(ar6000_netdev, 1);
+        }
+    }
+
+    HIFShutDownDevice(NULL);
+
+    a_module_debug_support_cleanup();
+
+    ar6000_pm_exit();
+
+#ifdef ANDROID_ENV    
+    android_module_exit();
+#endif
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("ar6000_cleanup: success\n"));
+}
+
+#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL
+void
+aptcTimerHandler(unsigned long arg)
+{
+    A_UINT32 numbytes;
+    A_UINT32 throughput;
+    AR_SOFTC_T *ar;
+    A_STATUS status;
+
+    ar = (AR_SOFTC_T *)arg;
+    A_ASSERT(ar != NULL);
+    A_ASSERT(!timer_pending(&aptcTimer));
+
+    AR6000_SPIN_LOCK(&ar->arLock, 0);
+
+    /* Get the number of bytes transferred */
+    numbytes = aptcTR.bytesTransmitted + aptcTR.bytesReceived;
+    aptcTR.bytesTransmitted = aptcTR.bytesReceived = 0;
+
+    /* Calculate and decide based on throughput thresholds */
+    throughput = ((numbytes * 8)/APTC_TRAFFIC_SAMPLING_INTERVAL); /* Kbps */
+    if (throughput < APTC_LOWER_THROUGHPUT_THRESHOLD) {
+        /* Enable Sleep and delete the timer */
+        A_ASSERT(ar->arWmiReady == TRUE);
+        AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+        status = wmi_powermode_cmd(ar->arWmi, REC_POWER);
+        AR6000_SPIN_LOCK(&ar->arLock, 0);
+        A_ASSERT(status == A_OK);
+        aptcTR.timerScheduled = FALSE;
+    } else {
+        A_TIMEOUT_MS(&aptcTimer, APTC_TRAFFIC_SAMPLING_INTERVAL, 0);
+    }
+
+    AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+}
+#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */
+
+#ifdef ATH_AR6K_11N_SUPPORT
+static void
+ar6000_alloc_netbufs(A_NETBUF_QUEUE_T *q, A_UINT16 num)
+{
+    void * osbuf;
+
+    while(num) {
+        if((osbuf = A_NETBUF_ALLOC(AR6000_BUFFER_SIZE))) {
+            A_NETBUF_ENQUEUE(q, osbuf);
+        } else {
+            break;
+        }
+        num--;
+    }
+
+    if(num) {
+        A_PRINTF("%s(), allocation of netbuf failed", __func__);
+    }
+}
+#endif
+
+static struct bin_attribute bmi_attr = {
+    .attr = {.name = "bmi", .mode = 0600},
+    .read = ar6000_sysfs_bmi_read,
+    .write = ar6000_sysfs_bmi_write,
+};
+
+static ssize_t
+ar6000_sysfs_bmi_read(struct file *fp, struct kobject *kobj,
+                      struct bin_attribute *bin_attr,
+                      char *buf, loff_t pos, size_t count)
+{
+    int index;
+    AR_SOFTC_T *ar;
+    HIF_DEVICE_OS_DEVICE_INFO   *osDevInfo;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("BMI: Read %d bytes\n", (A_UINT32)count));
+    for (index=0; index < MAX_AR6000; index++) {
+        ar = (AR_SOFTC_T *)ar6k_priv(ar6000_devices[index]);
+        osDevInfo = &ar->osDevInfo;
+        if (kobj == (&(((struct device *)osDevInfo->pOSDevice)->kobj))) {
+            break;
+        }
+    }
+
+    if (index == MAX_AR6000) return 0;
+
+    if ((BMIRawRead(ar->arHifDevice, (A_UCHAR*)buf, count, TRUE)) != A_OK) {
+        return 0;
+    }
+
+    return count;
+}
+
+static ssize_t
+ar6000_sysfs_bmi_write(struct file *fp, struct kobject *kobj,
+                       struct bin_attribute *bin_attr,
+                       char *buf, loff_t pos, size_t count)
+{
+    int index;
+    AR_SOFTC_T *ar;
+    HIF_DEVICE_OS_DEVICE_INFO   *osDevInfo;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("BMI: Write %d bytes\n", (A_UINT32)count));
+    for (index=0; index < MAX_AR6000; index++) {
+        ar = (AR_SOFTC_T *)ar6k_priv(ar6000_devices[index]);
+        osDevInfo = &ar->osDevInfo;
+        if (kobj == (&(((struct device *)osDevInfo->pOSDevice)->kobj))) {
+            break;
+        }
+    }
+
+    if (index == MAX_AR6000) return 0;
+
+    if ((BMIRawWrite(ar->arHifDevice, (A_UCHAR*)buf, count)) != A_OK) {
+        return 0;
+    }
+
+    return count;
+}
+
+static A_STATUS
+ar6000_sysfs_bmi_init(AR_SOFTC_T *ar)
+{
+    A_STATUS status;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("BMI: Creating sysfs entry\n"));
+    A_MEMZERO(&ar->osDevInfo, sizeof(HIF_DEVICE_OS_DEVICE_INFO));
+
+    /* Get the underlying OS device */
+    status = HIFConfigureDevice(ar->arHifDevice,
+                                HIF_DEVICE_GET_OS_DEVICE,
+                                &ar->osDevInfo,
+                                sizeof(HIF_DEVICE_OS_DEVICE_INFO));
+
+    if (A_FAILED(status)) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("BMI: Failed to get OS device info from HIF\n"));
+        return A_ERROR;
+    }
+
+    /* Create a bmi entry in the sysfs filesystem */
+    if ((sysfs_create_bin_file(&(((struct device *)ar->osDevInfo.pOSDevice)->kobj), &bmi_attr)) < 0)
+    {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BMI: Failed to create entry for bmi in sysfs filesystem\n"));
+        return A_ERROR;
+    }
+
+    return A_OK;
+}
+
+static void
+ar6000_sysfs_bmi_deinit(AR_SOFTC_T *ar)
+{
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("BMI: Deleting sysfs entry\n"));
+
+    sysfs_remove_bin_file(&(((struct device *)ar->osDevInfo.pOSDevice)->kobj), &bmi_attr);
+}
+
+#define bmifn(fn) do { \
+    if ((fn) < A_OK) { \
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("BMI operation failed: %d\n", __LINE__)); \
+        return A_ERROR; \
+    } \
+} while(0)
+
+#ifdef INIT_MODE_DRV_ENABLED
+
+#ifdef SOFTMAC_FILE_USED
+#define AR6002_MAC_ADDRESS_OFFSET     0x0A
+#define AR6003_MAC_ADDRESS_OFFSET     0x16
+static
+void calculate_crc(A_UINT32 TargetType, A_UCHAR *eeprom_data)
+{
+    A_UINT16        *ptr_crc;
+    A_UINT16        *ptr16_eeprom;
+    A_UINT16        checksum;
+    A_UINT32        i;
+    A_UINT32        eeprom_size;
+
+    if (TargetType == TARGET_TYPE_AR6001)
+    {
+        eeprom_size = 512;
+        ptr_crc = (A_UINT16 *)eeprom_data;
+    }
+    else if (TargetType == TARGET_TYPE_AR6003)
+    {
+        eeprom_size = 1024;
+        ptr_crc = (A_UINT16 *)((A_UCHAR *)eeprom_data + 0x04);
+    }
+    else
+    {
+        eeprom_size = 768;
+        ptr_crc = (A_UINT16 *)((A_UCHAR *)eeprom_data + 0x04);
+    }
+
+
+    // Clear the crc
+    *ptr_crc = 0;
+
+    // Recalculate new CRC
+    checksum = 0;
+    ptr16_eeprom = (A_UINT16 *)eeprom_data;
+    for (i = 0;i < eeprom_size; i += 2)
+    {
+        checksum = checksum ^ (*ptr16_eeprom);
+        ptr16_eeprom++;
+    }
+    checksum = 0xFFFF ^ checksum;
+    *ptr_crc = checksum;
+}
+
+static void 
+ar6000_softmac_update(AR_SOFTC_T *ar, A_UCHAR *eeprom_data, size_t size)
+{
+    const char *source = "random generated";
+    const struct firmware *softmac_entry;
+    A_UCHAR *ptr_mac;
+    switch (ar->arTargetType) {
+    case TARGET_TYPE_AR6002:
+        ptr_mac = (A_UINT8 *)((A_UCHAR *)eeprom_data + AR6002_MAC_ADDRESS_OFFSET);
+        break;
+    case TARGET_TYPE_AR6003:
+        ptr_mac = (A_UINT8 *)((A_UCHAR *)eeprom_data + AR6003_MAC_ADDRESS_OFFSET);
+        break;
+    default:
+	AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Invalid Target Type\n"));
+        return;
+    }
+	printk(KERN_DEBUG "MAC from EEPROM %pM\n", ptr_mac);
+
+    /* create a random MAC in case we cannot read file from system */
+    ptr_mac[0] = 0;
+    ptr_mac[1] = 0x03;
+    ptr_mac[2] = 0x7F;
+    ptr_mac[3] = random32() & 0xff; 
+    ptr_mac[4] = random32() & 0xff; 
+    ptr_mac[5] = random32() & 0xff; 
+    if ((A_REQUEST_FIRMWARE(&softmac_entry, "softmac", ((struct device *)ar->osDevInfo.pOSDevice))) == 0)
+    {
+        A_CHAR *macbuf = A_MALLOC_NOWAIT(softmac_entry->size+1);
+        if (macbuf) {            
+            unsigned int softmac[6];
+            memcpy(macbuf, softmac_entry->data, softmac_entry->size);
+            macbuf[softmac_entry->size] = '\0';
+            if (sscanf(macbuf, "%02x:%02x:%02x:%02x:%02x:%02x", 
+                        &softmac[0], &softmac[1], &softmac[2],
+                        &softmac[3], &softmac[4], &softmac[5])==6) {
+                int i;
+                for (i=0; i<6; ++i) {
+                    ptr_mac[i] = softmac[i] & 0xff;
+                }
+                source = "softmac file";
+            }
+            A_FREE(macbuf);
+        }
+        A_RELEASE_FIRMWARE(softmac_entry);
+    }
+	printk(KERN_DEBUG "MAC from %s %pM\n", source, ptr_mac);
+   calculate_crc(ar->arTargetType, eeprom_data);
+}
+#endif /* SOFTMAC_FILE_USED */
+
+static A_STATUS
+ar6000_transfer_bin_file(AR_SOFTC_T *ar, AR6K_BIN_FILE file, A_UINT32 address, A_BOOL compressed)
+{
+    A_STATUS status;
+    const char *filename;
+    const struct firmware *fw_entry;
+    A_UINT32 fw_entry_size;
+
+    switch (file) {
+        case AR6K_OTP_FILE:
+            if (ar->arVersion.target_ver == AR6003_REV1_VERSION) {
+                filename = AR6003_REV1_OTP_FILE;
+            } else if (ar->arVersion.target_ver == AR6003_REV2_VERSION) {
+                filename = AR6003_REV2_OTP_FILE;
+            } else {
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unknown firmware revision: %d\n", ar->arVersion.target_ver));
+                return A_ERROR;
+            }
+            break;
+
+        case AR6K_FIRMWARE_FILE:
+            if (ar->arVersion.target_ver == AR6003_REV1_VERSION) {
+                filename = AR6003_REV1_FIRMWARE_FILE;
+            } else if (ar->arVersion.target_ver == AR6003_REV2_VERSION) {
+                filename = AR6003_REV2_FIRMWARE_FILE;
+            } else {
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unknown firmware revision: %d\n", ar->arVersion.target_ver));
+                return A_ERROR;
+            }
+            
+            if (eppingtest) {
+                bypasswmi = TRUE;    
+                if (ar->arVersion.target_ver == AR6003_REV1_VERSION) {
+                    filename = AR6003_REV1_EPPING_FIRMWARE_FILE;
+                } else if (ar->arVersion.target_ver == AR6003_REV2_VERSION) {
+                    filename = AR6003_REV2_EPPING_FIRMWARE_FILE;
+                } else {
+                    AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("eppingtest : unsupported firmware revision: %d\n", 
+                        ar->arVersion.target_ver));
+                    return A_ERROR;
+                }
+                compressed = 0;
+            }
+            
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+            if(testmode) {
+                if (ar->arVersion.target_ver == AR6003_REV1_VERSION) {
+                    filename = AR6003_REV1_TCMD_FIRMWARE_FILE;
+                } else if (ar->arVersion.target_ver == AR6003_REV2_VERSION) {
+                    filename = AR6003_REV2_TCMD_FIRMWARE_FILE;
+                } else {
+                    AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unknown firmware revision: %d\n", ar->arVersion.target_ver));
+                    return A_ERROR;
+                }
+                compressed = 0;
+            }
+#endif 
+#ifdef HTC_RAW_INTERFACE
+            if (!eppingtest && bypasswmi) {
+                if (ar->arVersion.target_ver == AR6003_REV1_VERSION) {
+                    filename = AR6003_REV1_ART_FIRMWARE_FILE;
+                } else if (ar->arVersion.target_ver == AR6003_REV2_VERSION) {
+                    filename = AR6003_REV2_ART_FIRMWARE_FILE;
+                } else {
+                    AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unknown firmware revision: %d\n", ar->arVersion.target_ver));
+                    return A_ERROR;
+                }
+                compressed = 0;                
+            }
+#endif 
+            break;
+
+        case AR6K_PATCH_FILE:
+            if (ar->arVersion.target_ver == AR6003_REV1_VERSION) {
+                filename = AR6003_REV1_PATCH_FILE;
+            } else if (ar->arVersion.target_ver == AR6003_REV2_VERSION) {
+                filename = AR6003_REV2_PATCH_FILE;
+            } else {
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unknown firmware revision: %d\n", ar->arVersion.target_ver));
+                return A_ERROR;
+            }
+            break;
+
+        case AR6K_BOARD_DATA_FILE:
+            if (ar->arVersion.target_ver == AR6003_REV1_VERSION) {
+                filename = AR6003_REV1_BOARD_DATA_FILE;
+            } else if (ar->arVersion.target_ver == AR6003_REV2_VERSION) {
+                filename = AR6003_REV2_BOARD_DATA_FILE;
+            } else {
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unknown firmware revision: %d\n", ar->arVersion.target_ver));
+                return A_ERROR;
+            }
+            break;
+
+        default:
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unknown file type: %d\n", file));
+            return A_ERROR;
+    }
+    if ((A_REQUEST_FIRMWARE(&fw_entry, filename, ((struct device *)ar->osDevInfo.pOSDevice))) != 0)
+    {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to get %s\n", filename));
+        return A_ENOENT;
+    }
+
+#ifdef SOFTMAC_FILE_USED
+    if (file==AR6K_BOARD_DATA_FILE && fw_entry->data) {
+        ar6000_softmac_update(ar, (A_UCHAR *)fw_entry->data, fw_entry->size);
+    }
+#endif 
+
+
+    fw_entry_size = fw_entry->size;
+
+    /* Load extended board data for AR6003 */
+    if ((file==AR6K_BOARD_DATA_FILE) && (fw_entry->data)) {
+        A_UINT32 board_ext_address;
+        A_UINT32 board_ext_data_size;
+        A_UINT32 board_data_size;
+
+        board_ext_data_size = (((ar)->arTargetType == TARGET_TYPE_AR6002) ? AR6002_BOARD_EXT_DATA_SZ : \
+                               (((ar)->arTargetType == TARGET_TYPE_AR6003) ? AR6003_BOARD_EXT_DATA_SZ : 0));
+
+        board_data_size = (((ar)->arTargetType == TARGET_TYPE_AR6002) ? AR6002_BOARD_DATA_SZ : \
+                          (((ar)->arTargetType == TARGET_TYPE_AR6003) ? AR6003_BOARD_DATA_SZ : 0));
+        
+        /* Determine where in Target RAM to write Board Data */
+        bmifn(BMIReadMemory(ar->arHifDevice, HOST_INTEREST_ITEM_ADDRESS(ar, hi_board_ext_data), (A_UCHAR *)&board_ext_address, 4));
+        AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("Board extended Data download address: 0x%x\n", board_ext_address));
+
+        /* check whether the target has allocated memory for extended board data and file contains extended board data */
+        if ((board_ext_address) && (fw_entry->size == (board_data_size + board_ext_data_size))) {
+            A_UINT32 param;
+
+            status = BMIWriteMemory(ar->arHifDevice, board_ext_address, (A_UCHAR *)(fw_entry->data + board_data_size), board_ext_data_size);
+
+            if (status != A_OK) {
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("BMI operation failed: %d\n", __LINE__));
+                A_RELEASE_FIRMWARE(fw_entry);
+                return A_ERROR;
+            }
+
+            /* Record the fact that extended board Data IS initialized */
+            param = 1;
+            bmifn(BMIWriteMemory(ar->arHifDevice, HOST_INTEREST_ITEM_ADDRESS(ar, hi_board_ext_data_initialized), (A_UCHAR *)&param, 4));
+        }
+        fw_entry_size = board_data_size;
+    }
+
+    if (compressed) {
+        status = BMIFastDownload(ar->arHifDevice, address, (A_UCHAR *)fw_entry->data, fw_entry_size);
+    } else {
+        status = BMIWriteMemory(ar->arHifDevice, address, (A_UCHAR *)fw_entry->data, fw_entry_size);
+    }
+
+    if (status != A_OK) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("BMI operation failed: %d\n", __LINE__));
+        A_RELEASE_FIRMWARE(fw_entry);
+        return A_ERROR;
+    }
+    A_RELEASE_FIRMWARE(fw_entry);
+    return A_OK;
+}
+#endif /* INIT_MODE_DRV_ENABLED */
+
+A_STATUS
+ar6000_update_bdaddr(AR_SOFTC_T *ar)
+{
+
+        if (setupbtdev != 0) {
+            A_UINT32 address;
+
+           if (BMIReadMemory(ar->arHifDevice,
+           	HOST_INTEREST_ITEM_ADDRESS(ar, hi_board_data), (A_UCHAR *)&address, 4) != A_OK)
+           {
+    	      	AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BMIReadMemory for hi_board_data failed\n"));
+           	return A_ERROR;
+           }
+
+           if (BMIReadMemory(ar->arHifDevice, address + BDATA_BDADDR_OFFSET, (A_UCHAR *)ar->bdaddr, 6) != A_OK)
+           {
+    	    	AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BMIReadMemory for BD address failed\n"));
+           	return A_ERROR;
+           }
+	   AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BDADDR 0x%x:0x%x:0x%x:0x%x:0x%x:0x%x\n", ar->bdaddr[0],
+								ar->bdaddr[1], ar->bdaddr[2], ar->bdaddr[3],
+								ar->bdaddr[4], ar->bdaddr[5]));
+        }
+
+return A_OK;
+}
+
+A_STATUS
+ar6000_sysfs_bmi_get_config(AR_SOFTC_T *ar, A_UINT32 mode)
+{
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("BMI: Requesting device specific configuration\n"));
+
+    if (mode == WLAN_INIT_MODE_UDEV) {
+        A_CHAR version[16];
+        const struct firmware *fw_entry;
+
+        /* Get config using udev through a script in user space */
+        sprintf(version, "%2.2x", ar->arVersion.target_ver);
+        if ((A_REQUEST_FIRMWARE(&fw_entry, version, ((struct device *)ar->osDevInfo.pOSDevice))) != 0)
+        {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("BMI: Failure to get configuration for target version: %s\n", version));
+            return A_ERROR;
+        }
+
+        A_RELEASE_FIRMWARE(fw_entry);
+#ifdef INIT_MODE_DRV_ENABLED
+    } else {
+        /* The config is contained within the driver itself */
+        A_STATUS status;
+        A_UINT32 param, options, sleep, address;
+
+        /* Temporarily disable system sleep */
+        address = MBOX_BASE_ADDRESS + LOCAL_SCRATCH_ADDRESS;
+        bmifn(BMIReadSOCRegister(ar->arHifDevice, address, &param));
+        options = param;
+        param |= AR6K_OPTION_SLEEP_DISABLE;
+        bmifn(BMIWriteSOCRegister(ar->arHifDevice, address, param));
+
+        address = RTC_BASE_ADDRESS + SYSTEM_SLEEP_ADDRESS;
+        bmifn(BMIReadSOCRegister(ar->arHifDevice, address, &param));
+        sleep = param;
+        param |= WLAN_SYSTEM_SLEEP_DISABLE_SET(1);
+        bmifn(BMIWriteSOCRegister(ar->arHifDevice, address, param));
+        AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("old options: %d, old sleep: %d\n", options, sleep));
+
+        if (ar->arTargetType == TARGET_TYPE_AR6003) {
+            /* Program analog PLL register */
+            bmifn(BMIWriteSOCRegister(ar->arHifDevice, ANALOG_INTF_BASE_ADDRESS + 0x284, 0xF9104001));
+            /* Run at 80/88MHz by default */
+            param = CPU_CLOCK_STANDARD_SET(1);
+        } else {
+            /* Run at 40/44MHz by default */
+            param = CPU_CLOCK_STANDARD_SET(0);
+        }
+        address = RTC_BASE_ADDRESS + CPU_CLOCK_ADDRESS;
+        bmifn(BMIWriteSOCRegister(ar->arHifDevice, address, param));
+
+        param = 0;
+        if (ar->arTargetType == TARGET_TYPE_AR6002) {
+            bmifn(BMIReadMemory(ar->arHifDevice, HOST_INTEREST_ITEM_ADDRESS(ar, hi_ext_clk_detected), (A_UCHAR *)&param, 4));
+        }
+
+        /* LPO_CAL.ENABLE = 1 if no external clk is detected */
+        if (param != 1) {
+            address = RTC_BASE_ADDRESS + LPO_CAL_ADDRESS;
+            param = LPO_CAL_ENABLE_SET(1);
+            bmifn(BMIWriteSOCRegister(ar->arHifDevice, address, param));
+        }
+
+        /* Venus2.0: Lower SDIO pad drive strength,
+         * temporary WAR to avoid SDIO CRC error */
+        if (ar->arVersion.target_ver == AR6003_REV2_VERSION) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("AR6K: Temporary WAR to avoid SDIO CRC error\n"));
+            param = 0x20;
+            address = GPIO_BASE_ADDRESS + GPIO_PIN10_ADDRESS;
+            bmifn(BMIWriteSOCRegister(ar->arHifDevice, address, param));
+
+            address = GPIO_BASE_ADDRESS + GPIO_PIN11_ADDRESS;
+            bmifn(BMIWriteSOCRegister(ar->arHifDevice, address, param));
+
+            address = GPIO_BASE_ADDRESS + GPIO_PIN12_ADDRESS;
+            bmifn(BMIWriteSOCRegister(ar->arHifDevice, address, param));
+
+            address = GPIO_BASE_ADDRESS + GPIO_PIN13_ADDRESS;
+            bmifn(BMIWriteSOCRegister(ar->arHifDevice, address, param));
+        }
+
+#ifdef FORCE_INTERNAL_CLOCK
+        /* Ignore external clock, if any, and force use of internal clock */
+        if (ar->arTargetType == TARGET_TYPE_AR6003) {
+            /* hi_ext_clk_detected = 0 */
+            param = 0;
+            bmifn(BMIWriteMemory(ar->arHifDevice, HOST_INTEREST_ITEM_ADDRESS(ar, hi_ext_clk_detected), (A_UCHAR *)&param, 4));
+
+            /* CLOCK_CONTROL &= ~LF_CLK32 */
+            address = RTC_BASE_ADDRESS + CLOCK_CONTROL_ADDRESS;
+            bmifn(BMIReadSOCRegister(ar->arHifDevice, address, &param));
+            param &= (~CLOCK_CONTROL_LF_CLK32_SET(1));
+            bmifn(BMIWriteSOCRegister(ar->arHifDevice, address, param));
+        }
+#endif /* FORCE_INTERNAL_CLOCK */
+
+        /* Transfer Board Data from Target EEPROM to Target RAM */
+        if (ar->arTargetType == TARGET_TYPE_AR6003) {
+            /* Determine where in Target RAM to write Board Data */
+            bmifn(BMIReadMemory(ar->arHifDevice, HOST_INTEREST_ITEM_ADDRESS(ar, hi_board_data), (A_UCHAR *)&address, 4));
+            AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("Board Data download address: 0x%x\n", address));
+
+            /* Write EEPROM data to Target RAM */
+            if ((ar6000_transfer_bin_file(ar, AR6K_BOARD_DATA_FILE, address, FALSE)) != A_OK) {
+                return A_ERROR;
+            }
+
+            /* Record the fact that Board Data IS initialized */
+            param = 1;
+            bmifn(BMIWriteMemory(ar->arHifDevice, HOST_INTEREST_ITEM_ADDRESS(ar, hi_board_data_initialized), (A_UCHAR *)&param, 4));
+
+            /* Transfer One time Programmable data */
+            AR6K_DATA_DOWNLOAD_ADDRESS(address, ar->arVersion.target_ver);
+            status = ar6000_transfer_bin_file(ar, AR6K_OTP_FILE, address, TRUE);
+            if (status == A_OK) {
+                /* Execute the OTP code */
+                param = 0;
+                AR6K_APP_START_OVERRIDE_ADDRESS(address, ar->arVersion.target_ver);
+                bmifn(BMIExecute(ar->arHifDevice, address, &param));
+            } else if (status != A_ENOENT) {
+                return A_ERROR;
+            } 
+        } else {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Programming of board data for chip %d not supported\n", ar->arTargetType));
+            return A_ERROR;
+        }
+
+        /* Download Target firmware */
+        AR6K_DATA_DOWNLOAD_ADDRESS(address, ar->arVersion.target_ver);
+        if ((ar6000_transfer_bin_file(ar, AR6K_FIRMWARE_FILE, address, TRUE)) != A_OK) {
+            return A_ERROR;
+        }
+
+        /* Set starting address for firmware */
+        AR6K_APP_START_OVERRIDE_ADDRESS(address, ar->arVersion.target_ver);
+        bmifn(BMISetAppStart(ar->arHifDevice, address));
+
+        /* Apply the patches */
+        AR6K_PATCH_DOWNLOAD_ADDRESS(address, ar->arVersion.target_ver);
+        if ((ar6000_transfer_bin_file(ar, AR6K_PATCH_FILE, address, FALSE)) != A_OK) {
+            return A_ERROR;
+        }
+
+        param = address;
+        bmifn(BMIWriteMemory(ar->arHifDevice, HOST_INTEREST_ITEM_ADDRESS(ar, hi_dset_list_head), (A_UCHAR *)&param, 4));
+
+        if (ar->arTargetType == TARGET_TYPE_AR6003) {
+            if (ar->arVersion.target_ver == AR6003_REV1_VERSION) {
+                /* Reserve 5.5K of RAM */
+                param = 5632;
+            } else { /* AR6003_REV2_VERSION */
+                /* Reserve 6.5K of RAM */
+                param = 6656;
+            }
+            bmifn(BMIWriteMemory(ar->arHifDevice, HOST_INTEREST_ITEM_ADDRESS(ar, hi_end_RAM_reserve_sz), (A_UCHAR *)&param, 4));
+        }
+
+        /* Restore system sleep */
+        address = RTC_BASE_ADDRESS + SYSTEM_SLEEP_ADDRESS;
+        bmifn(BMIWriteSOCRegister(ar->arHifDevice, address, sleep));
+
+        address = MBOX_BASE_ADDRESS + LOCAL_SCRATCH_ADDRESS;
+        param = options | 0x20;
+        bmifn(BMIWriteSOCRegister(ar->arHifDevice, address, param));
+
+        if (ar->arTargetType == TARGET_TYPE_AR6003) {
+            /* Configure GPIO AR6003 UART */
+#ifndef CONFIG_AR600x_DEBUG_UART_TX_PIN
+#define CONFIG_AR600x_DEBUG_UART_TX_PIN 8
+#endif
+            param = CONFIG_AR600x_DEBUG_UART_TX_PIN;
+            bmifn(BMIWriteMemory(ar->arHifDevice, HOST_INTEREST_ITEM_ADDRESS(ar, hi_dbg_uart_txpin), (A_UCHAR *)&param, 4));
+
+#if (CONFIG_AR600x_DEBUG_UART_TX_PIN == 23)
+            {
+                address = GPIO_BASE_ADDRESS + CLOCK_GPIO_ADDRESS;
+                bmifn(BMIReadSOCRegister(ar->arHifDevice, address, &param));
+                param |= CLOCK_GPIO_BT_CLK_OUT_EN_SET(1);
+                bmifn(BMIWriteSOCRegister(ar->arHifDevice, address, param));
+            }
+#endif
+
+            /* Configure GPIO for BT Reset */
+#ifdef ATH6KL_CONFIG_GPIO_BT_RESET
+#define CONFIG_AR600x_BT_RESET_PIN	0x16
+            param = CONFIG_AR600x_BT_RESET_PIN;
+            bmifn(BMIWriteMemory(ar->arHifDevice, HOST_INTEREST_ITEM_ADDRESS(ar, hi_hci_uart_support_pins), (A_UCHAR *)&param, 4));
+#endif /* ATH6KL_CONFIG_GPIO_BT_RESET */
+
+            /* Configure UART flow control polarity */
+#ifndef CONFIG_ATH6KL_BT_UART_FC_POLARITY
+#define CONFIG_ATH6KL_BT_UART_FC_POLARITY 0
+#endif
+
+#if (CONFIG_ATH6KL_BT_UART_FC_POLARITY == 1)
+            if (ar->arVersion.target_ver == AR6003_REV2_VERSION) {
+                param = ((CONFIG_ATH6KL_BT_UART_FC_POLARITY << 1) & 0x2);
+                bmifn(BMIWriteMemory(ar->arHifDevice, HOST_INTEREST_ITEM_ADDRESS(ar, hi_hci_uart_pwr_mgmt_params), (A_UCHAR *)&param, 4));
+            }
+#endif /* CONFIG_ATH6KL_BT_UART_FC_POLARITY */
+        }
+
+#ifdef HTC_RAW_INTERFACE
+        if (!eppingtest && bypasswmi) {
+            /* Don't run BMIDone for ART mode and force resetok=0 */
+            resetok = 0;
+            msleep(1000);
+        }
+#endif /* HTC_RAW_INTERFACE */
+
+#endif /* INIT_MODE_DRV_ENABLED */
+    }
+
+    return A_OK;
+}
+
+A_STATUS
+ar6000_configure_target(AR_SOFTC_T *ar)
+{
+    A_UINT32 param;
+    if (enableuartprint) {
+        param = 1;
+        if (BMIWriteMemory(ar->arHifDevice,
+                           HOST_INTEREST_ITEM_ADDRESS(ar, hi_serial_enable),
+                           (A_UCHAR *)&param,
+                           4)!= A_OK)
+        {
+             AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BMIWriteMemory for enableuartprint failed \n"));
+             return A_ERROR;
+        }
+        AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("Serial console prints enabled\n"));
+    }
+
+    /* Tell target which HTC version it is used*/
+    param = HTC_PROTOCOL_VERSION;
+    if (BMIWriteMemory(ar->arHifDevice,
+                       HOST_INTEREST_ITEM_ADDRESS(ar, hi_app_host_interest),
+                       (A_UCHAR *)&param,
+                       4)!= A_OK)
+    {
+         AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BMIWriteMemory for htc version failed \n"));
+         return A_ERROR;
+    }
+
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+    if(testmode) {
+        ar->arTargetMode = AR6000_TCMD_MODE;
+    }else {
+        ar->arTargetMode = AR6000_WLAN_MODE;
+    }
+#endif
+    if (enabletimerwar) {
+        A_UINT32 param;
+
+        if (BMIReadMemory(ar->arHifDevice,
+            HOST_INTEREST_ITEM_ADDRESS(ar, hi_option_flag),
+            (A_UCHAR *)&param,
+            4)!= A_OK)
+        {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BMIReadMemory for enabletimerwar failed \n"));
+            return A_ERROR;
+        }
+
+        param |= HI_OPTION_TIMER_WAR;
+
+        if (BMIWriteMemory(ar->arHifDevice,
+            HOST_INTEREST_ITEM_ADDRESS(ar, hi_option_flag),
+            (A_UCHAR *)&param,
+            4) != A_OK)
+        {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BMIWriteMemory for enabletimerwar failed \n"));
+            return A_ERROR;
+        }
+        AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("Timer WAR enabled\n"));
+    }
+
+    /* set the firmware mode to STA/IBSS/AP */
+    {
+        A_UINT32 param;
+
+        if (BMIReadMemory(ar->arHifDevice,
+            HOST_INTEREST_ITEM_ADDRESS(ar, hi_option_flag),
+            (A_UCHAR *)&param,
+            4)!= A_OK)
+        {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BMIReadMemory for setting fwmode failed \n"));
+            return A_ERROR;
+        }
+
+        param |= (fwmode << HI_OPTION_FW_MODE_SHIFT);
+
+        if (BMIWriteMemory(ar->arHifDevice,
+            HOST_INTEREST_ITEM_ADDRESS(ar, hi_option_flag),
+            (A_UCHAR *)&param,
+            4) != A_OK)
+        {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BMIWriteMemory for setting fwmode failed \n"));
+            return A_ERROR;
+        }
+        AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("Firmware mode set\n"));
+    }
+
+#ifdef ATH6KL_DISABLE_TARGET_DBGLOGS
+    {
+        A_UINT32 param;
+
+        if (BMIReadMemory(ar->arHifDevice,
+            HOST_INTEREST_ITEM_ADDRESS(ar, hi_option_flag),
+            (A_UCHAR *)&param,
+            4)!= A_OK)
+        {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BMIReadMemory for disabling debug logs failed\n"));
+            return A_ERROR;
+        }
+
+        param |= HI_OPTION_DISABLE_DBGLOG;
+
+        if (BMIWriteMemory(ar->arHifDevice,
+            HOST_INTEREST_ITEM_ADDRESS(ar, hi_option_flag),
+            (A_UCHAR *)&param,
+            4) != A_OK)
+        {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BMIWriteMemory for HI_OPTION_DISABLE_DBGLOG\n"));
+            return A_ERROR;
+        }
+        AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("Firmware mode set\n"));
+    }
+#endif /* ATH6KL_DISABLE_TARGET_DBGLOGS */
+
+    /* 
+     * Hardcode the address use for the extended board data 
+     * Ideally this should be pre-allocate by the OS at boot time
+     * But since it is a new feature and board data is loaded 
+     * at init time, we have to workaround this from host.
+     * It is difficult to patch the firmware boot code,
+     * but possible in theory.
+     */
+    if (ar->arTargetType == TARGET_TYPE_AR6003) {
+        param = AR6003_BOARD_EXT_DATA_ADDRESS; 
+        if (BMIWriteMemory(ar->arHifDevice,
+            HOST_INTEREST_ITEM_ADDRESS(ar, hi_board_ext_data),
+            (A_UCHAR *)&param,
+            4) != A_OK)
+        {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BMIWriteMemory for hi_board_ext_data failed \n"));
+            return A_ERROR;
+        }
+    }
+
+
+        /* since BMIInit is called in the driver layer, we have to set the block
+         * size here for the target */
+
+    if (A_FAILED(ar6000_set_htc_params(ar->arHifDevice,
+                                       ar->arTargetType,
+                                       mbox_yield_limit,
+                                       0 /* use default number of control buffers */
+                                       ))) {
+        return A_ERROR;
+    }
+
+    if (setupbtdev != 0) {
+        if (A_FAILED(ar6000_set_hci_bridge_flags(ar->arHifDevice,
+                                                 ar->arTargetType,
+                                                 setupbtdev))) {
+            return A_ERROR;
+        }
+    }
+    return A_OK;
+}
+
+static void
+init_netdev(struct net_device *dev, char *name)
+{
+    dev->netdev_ops = &ar6000_netdev_ops;
+    dev->watchdog_timeo = AR6000_TX_TIMEOUT;
+    dev->wireless_handlers = &ath_iw_handler_def;
+
+    ath_iw_handler_def.get_wireless_stats = ar6000_get_iwstats; /*Displayed via proc fs */
+
+   /*
+    * We need the OS to provide us with more headroom in order to
+    * perform dix to 802.3, WMI header encap, and the HTC header
+    */
+    if (processDot11Hdr) {
+        dev->hard_header_len = sizeof(struct ieee80211_qosframe) + sizeof(ATH_LLC_SNAP_HDR) + sizeof(WMI_DATA_HDR) + HTC_HEADER_LEN + WMI_MAX_TX_META_SZ + LINUX_HACK_FUDGE_FACTOR;
+    } else {
+        dev->hard_header_len = ETH_HLEN + sizeof(ATH_LLC_SNAP_HDR) +
+            sizeof(WMI_DATA_HDR) + HTC_HEADER_LEN + WMI_MAX_TX_META_SZ + LINUX_HACK_FUDGE_FACTOR;
+    }
+
+    if (name[0])
+    {
+        strcpy(dev->name, name);
+    }
+
+#ifdef SET_MODULE_OWNER
+    SET_MODULE_OWNER(dev);
+#endif
+
+#ifdef CONFIG_CHECKSUM_OFFLOAD
+    if(csumOffload){
+        dev->features |= NETIF_F_IP_CSUM; /*advertise kernel capability to do TCP/UDP CSUM offload for IPV4*/
+    }
+#endif
+
+    return;
+}
+
+/*
+ * HTC Event handlers
+ */
+static A_STATUS
+ar6000_avail_ev(void *context, void *hif_handle)
+{
+    int i;
+    struct net_device *dev;
+    void *ar_netif;
+    AR_SOFTC_T *ar;
+    int device_index = 0;
+    HTC_INIT_INFO  htcInfo;
+#ifdef ATH6K_CONFIG_CFG80211
+    struct wireless_dev *wdev;
+#endif /* ATH6K_CONFIG_CFG80211 */
+    A_STATUS init_status = A_OK;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("ar6000_available\n"));
+
+    for (i=0; i < MAX_AR6000; i++) {
+        if (ar6000_devices[i] == NULL) {
+            break;
+        }
+    }
+
+    if (i == MAX_AR6000) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("ar6000_available: max devices reached\n"));
+        return A_ERROR;
+    }
+
+    /* Save this. It gives a bit better readability especially since */
+    /* we use another local "i" variable below.                      */
+    device_index = i;
+
+#ifdef ATH6K_CONFIG_CFG80211
+    wdev = ar6k_cfg80211_init(NULL);
+    if (IS_ERR(wdev)) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: ar6k_cfg80211_init failed\n", __func__));
+        return A_ERROR;
+    }
+    ar_netif = wdev_priv(wdev);
+#else
+    dev = alloc_etherdev(sizeof(AR_SOFTC_T));
+    if (dev == NULL) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("ar6000_available: can't alloc etherdev\n"));
+        return A_ERROR;
+    }
+    ether_setup(dev);
+    ar_netif = ar6k_priv(dev);
+#endif /* ATH6K_CONFIG_CFG80211 */
+
+    if (ar_netif == NULL) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Can't allocate ar6k priv memory\n", __func__));
+        return A_ERROR;
+    }
+
+    A_MEMZERO(ar_netif, sizeof(AR_SOFTC_T));
+    ar = (AR_SOFTC_T *)ar_netif;
+
+#ifdef ATH6K_CONFIG_CFG80211
+    ar->wdev = wdev;
+    wdev->iftype = NL80211_IFTYPE_STATION;
+
+    dev = alloc_netdev_mq(0, "wlan%d", ether_setup, 1);
+    if (!dev) {
+        printk(KERN_CRIT "AR6K: no memory for network device instance\n");
+        ar6k_cfg80211_deinit(ar);
+        return A_ERROR;
+    }
+
+    dev->ieee80211_ptr = wdev;
+    SET_NETDEV_DEV(dev, wiphy_dev(wdev->wiphy));
+    wdev->netdev = dev;
+    ar->arNetworkType = INFRA_NETWORK;
+#endif /* ATH6K_CONFIG_CFG80211 */
+
+    init_netdev(dev, ifname);
+
+#ifdef SET_NETDEV_DEV
+    if (ar_netif) { 
+        HIF_DEVICE_OS_DEVICE_INFO osDevInfo;
+        A_MEMZERO(&osDevInfo, sizeof(osDevInfo));
+        if ( A_SUCCESS( HIFConfigureDevice(hif_handle, HIF_DEVICE_GET_OS_DEVICE,
+                        &osDevInfo, sizeof(osDevInfo))) ) {
+            SET_NETDEV_DEV(dev, osDevInfo.pOSDevice);
+        }
+    }
+#endif 
+
+    ar->arNetDev             = dev;
+    ar->arHifDevice          = hif_handle;
+    ar->arWlanState          = WLAN_ENABLED;
+    ar->arDeviceIndex        = device_index;
+
+    ar->arWlanPowerState     = WLAN_POWER_STATE_ON;
+    ar->arWlanOff            = FALSE;   /* We are in ON state */
+#ifdef CONFIG_PM
+    ar->arWowState           = WLAN_WOW_STATE_NONE;
+    ar->arBTOff              = TRUE;   /* BT chip assumed to be OFF */
+    ar->arBTSharing          = WLAN_CONFIG_BT_SHARING; 
+    ar->arWlanOffConfig      = WLAN_CONFIG_WLAN_OFF;
+    ar->arSuspendConfig      = WLAN_CONFIG_PM_SUSPEND;
+    ar->arWow2Config         = WLAN_CONFIG_PM_WOW2;
+#endif /* CONFIG_PM */
+
+    A_INIT_TIMER(&ar->arHBChallengeResp.timer, ar6000_detect_error, dev);
+    ar->arHBChallengeResp.seqNum = 0;
+    ar->arHBChallengeResp.outstanding = FALSE;
+    ar->arHBChallengeResp.missCnt = 0;
+    ar->arHBChallengeResp.frequency = AR6000_HB_CHALLENGE_RESP_FREQ_DEFAULT;
+    ar->arHBChallengeResp.missThres = AR6000_HB_CHALLENGE_RESP_MISS_THRES_DEFAULT;
+
+    ar6000_init_control_info(ar);
+    init_waitqueue_head(&arEvent);
+    sema_init(&ar->arSem, 1);
+    ar->bIsDestroyProgress = FALSE;
+
+    INIT_HTC_PACKET_QUEUE(&ar->amsdu_rx_buffer_queue);
+
+#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL
+    A_INIT_TIMER(&aptcTimer, aptcTimerHandler, ar);
+#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */
+
+    A_INIT_TIMER(&ar->disconnect_timer, disconnect_timer_handler, dev);
+
+    BMIInit();
+
+    if (bmienable) {
+        ar6000_sysfs_bmi_init(ar);
+    }
+
+    {
+        struct bmi_target_info targ_info;
+
+        if (BMIGetTargetInfo(ar->arHifDevice, &targ_info) != A_OK) {
+            init_status = A_ERROR;
+            goto avail_ev_failed;
+        }
+
+        ar->arVersion.target_ver = targ_info.target_ver;
+        ar->arTargetType = targ_info.target_type;
+
+            /* do any target-specific preparation that can be done through BMI */
+        if (ar6000_prepare_target(ar->arHifDevice,
+                                  targ_info.target_type,
+                                  targ_info.target_ver) != A_OK) {
+            init_status = A_ERROR;
+            goto avail_ev_failed;
+        }
+
+    }
+
+    if (ar6000_configure_target(ar) != A_OK) {
+            init_status = A_ERROR;
+            goto avail_ev_failed;
+    }
+
+    A_MEMZERO(&htcInfo,sizeof(htcInfo));
+    htcInfo.pContext = ar;
+    htcInfo.TargetFailure = ar6000_target_failure;
+
+    ar->arHtcTarget = HTCCreate(ar->arHifDevice,&htcInfo);
+
+    if (ar->arHtcTarget == NULL) {
+        init_status = A_ERROR;
+        goto avail_ev_failed;
+    }
+
+    spin_lock_init(&ar->arLock);
+
+#ifdef WAPI_ENABLE
+    ar->arWapiEnable = 0;
+#endif
+
+
+#ifdef CONFIG_CHECKSUM_OFFLOAD
+    if(csumOffload){
+        /*if external frame work is also needed, change and use an extended rxMetaVerion*/
+        ar->rxMetaVersion=WMI_META_VERSION_2;
+    }
+#endif
+
+#ifdef ATH_AR6K_11N_SUPPORT
+    if((ar->aggr_cntxt = aggr_init(ar6000_alloc_netbufs)) == NULL) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("%s() Failed to initialize aggr.\n", __func__));
+            init_status = A_ERROR;
+            goto avail_ev_failed;
+    }
+
+    aggr_register_rx_dispatcher(ar->aggr_cntxt, (void *)dev, ar6000_deliver_frames_to_nw_stack);
+#endif
+
+    HIFClaimDevice(ar->arHifDevice, ar);
+
+    /* We only register the device in the global list if we succeed. */
+    /* If the device is in the global list, it will be destroyed     */
+    /* when the module is unloaded.                                  */
+    ar6000_devices[device_index] = dev;
+
+    /* Don't install the init function if BMI is requested */
+    if (!bmienable) {
+        ar6000_netdev_ops.ndo_init = ar6000_init;
+    } else {
+        AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("BMI enabled: %d\n", wlaninitmode));
+        if ((wlaninitmode == WLAN_INIT_MODE_UDEV) ||
+            (wlaninitmode == WLAN_INIT_MODE_DRV))
+        {
+            A_STATUS status = A_OK;
+            do {
+                if ((status = ar6000_sysfs_bmi_get_config(ar, wlaninitmode)) != A_OK)
+                {
+                    AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("ar6000_avail: ar6000_sysfs_bmi_get_config failed\n"));
+                    break;
+                }
+#ifdef HTC_RAW_INTERFACE
+                break; /* Don't call ar6000_init for ART */
+#endif 
+                rtnl_lock();
+                status = (ar6000_init(dev)==0) ? A_OK : A_ERROR;
+                rtnl_unlock();
+                if (status != A_OK) {
+                    AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("ar6000_avail: ar6000_init\n"));
+                }
+            } while (FALSE);
+
+            if (status != A_OK) {
+                init_status = status;
+                goto avail_ev_failed;
+            }
+        }
+    }
+
+    /* This runs the init function if registered */
+    if (register_netdev(dev)) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("ar6000_avail: register_netdev failed\n"));
+        ar6000_destroy(dev, 0);
+        return A_ERROR;
+    }
+
+	is_netdev_registered = 1;
+
+#ifdef CONFIG_AP_VIRTUAL_ADAPTER_SUPPORT
+    arApNetDev = NULL;
+#endif /* CONFIG_AP_VIRTUAL_ADAPTER_SUPPORT */
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("ar6000_avail: name=%s hifdevice=0x%lx, dev=0x%lx (%d), ar=0x%lx\n",
+                    dev->name, (unsigned long)ar->arHifDevice, (unsigned long)dev, device_index,
+                    (unsigned long)ar));
+
+avail_ev_failed :
+    if (A_FAILED(init_status)) {
+        if (bmienable) { 
+            ar6000_sysfs_bmi_deinit(ar);  
+        }
+    }
+
+    return init_status;
+}
+
+static void ar6000_target_failure(void *Instance, A_STATUS Status)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)Instance;
+    WMI_TARGET_ERROR_REPORT_EVENT errEvent;
+    static A_BOOL sip = FALSE;
+
+    if (Status != A_OK) {
+
+        printk(KERN_ERR "ar6000_target_failure: target asserted \n");
+
+        if (timer_pending(&ar->arHBChallengeResp.timer)) {
+            A_UNTIMEOUT(&ar->arHBChallengeResp.timer);
+        }
+
+        /* try dumping target assertion information (if any) */
+        ar6000_dump_target_assert_info(ar->arHifDevice,ar->arTargetType);
+
+        /*
+         * Fetch the logs from the target via the diagnostic
+         * window.
+         */
+        ar6000_dbglog_get_debug_logs(ar);
+
+        /* Report the error only once */
+        if (!sip) {
+            sip = TRUE;
+            errEvent.errorVal = WMI_TARGET_COM_ERR |
+                                WMI_TARGET_FATAL_ERR;
+            ar6000_send_event_to_app(ar, WMI_ERROR_REPORT_EVENTID,
+                                     (A_UINT8 *)&errEvent,
+                                     sizeof(WMI_TARGET_ERROR_REPORT_EVENT));
+        }
+    }
+}
+
+static A_STATUS
+ar6000_unavail_ev(void *context, void *hif_handle)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)context;
+        /* NULL out it's entry in the global list */
+    ar6000_devices[ar->arDeviceIndex] = NULL;
+    ar6000_destroy(ar->arNetDev, 1);
+
+    return A_OK;
+}
+
+void
+ar6000_restart_endpoint(struct net_device *dev)
+{
+    A_STATUS status = A_OK;
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+    BMIInit();
+    do {
+        if ( (status=ar6000_configure_target(ar))!=A_OK)
+            break;
+        if ( (status=ar6000_sysfs_bmi_get_config(ar, wlaninitmode)) != A_OK)
+        {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("ar6000_avail: ar6000_sysfs_bmi_get_config failed\n"));
+            break;
+        }
+        rtnl_lock();
+        status = (ar6000_init(dev)==0) ? A_OK : A_ERROR;
+        rtnl_unlock();
+
+        if (status!=A_OK) {
+            break;
+        }
+        if (ar->arSsidLen && ar->arWlanState == WLAN_ENABLED) {
+            ar6000_connect_to_ap(ar);
+        }  
+    } while (0);
+
+    if (status==A_OK) {
+        return;
+    }
+
+    ar6000_devices[ar->arDeviceIndex] = NULL;
+    ar6000_destroy(ar->arNetDev, 1);
+}
+
+void
+ar6000_stop_endpoint(struct net_device *dev, A_BOOL keepprofile, A_BOOL getdbglogs)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+    /* Stop the transmit queues */
+    netif_stop_queue(dev);
+
+    /* Disable the target and the interrupts associated with it */
+    if (ar->arWmiReady == TRUE)
+    {
+        if (!bypasswmi)
+        {
+            if (ar->arConnected == TRUE || ar->arConnectPending == TRUE)
+            {
+                AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("%s(): Disconnect\n", __func__));
+                if (!keepprofile) {
+                    AR6000_SPIN_LOCK(&ar->arLock, 0);
+                    ar6000_init_profile_info(ar);
+                    AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+                }
+                wmi_disconnect_cmd(ar->arWmi);
+            }
+
+            A_UNTIMEOUT(&ar->disconnect_timer);
+
+            if (getdbglogs) {
+                ar6000_dbglog_get_debug_logs(ar);
+            }
+
+            ar->arWmiReady  = FALSE;
+            wmi_shutdown(ar->arWmi);
+            ar->arWmiEnabled = FALSE;
+            ar->arWmi = NULL;
+            /* 
+             * After wmi_shudown all WMI events will be dropped.
+             * We need to cleanup the buffers allocated in AP mode
+             * and give disconnect notification to stack, which usually
+             * happens in the disconnect_event. 
+             * Simulate the disconnect_event by calling the function directly.
+             * Sometimes disconnect_event will be received when the debug logs 
+             * are collected.
+             */
+            if (ar->arConnected == TRUE || ar->arConnectPending == TRUE) {
+                if(ar->arNetworkType & AP_NETWORK) {
+                    ar6000_disconnect_event(ar, DISCONNECT_CMD, bcast_mac, 0, NULL, 0);
+                } else {
+                    ar6000_disconnect_event(ar, DISCONNECT_CMD, ar->arBssid, 0, NULL, 0);
+                }
+                ar->arConnected = FALSE;
+                ar->arConnectPending = FALSE;
+            }
+#ifdef USER_KEYS
+            ar->user_savedkeys_stat = USER_SAVEDKEYS_STAT_INIT;
+            ar->user_key_ctrl      = 0;
+#endif
+        }
+
+         AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("%s(): WMI stopped\n", __func__));
+    }
+    else
+    {
+        AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("%s(): WMI not ready 0x%lx 0x%lx\n",
+            __func__, (unsigned long) ar, (unsigned long) ar->arWmi));
+
+        /* Shut down WMI if we have started it */
+        if(ar->arWmiEnabled == TRUE)
+        {
+            AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("%s(): Shut down WMI\n", __func__));
+            wmi_shutdown(ar->arWmi);
+            ar->arWmiEnabled = FALSE;
+            ar->arWmi = NULL;
+        }
+    }
+
+    if (ar->arHtcTarget != NULL) {
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+        if (NULL != ar6kHciTransCallbacks.cleanupTransport) {
+            ar6kHciTransCallbacks.cleanupTransport(NULL);
+        }
+#else
+        // FIXME: workaround to reset BT's UART baud rate to default
+        if (NULL != ar->exitCallback) {
+            AR3K_CONFIG_INFO ar3kconfig;
+            A_STATUS status;
+
+            A_MEMZERO(&ar3kconfig,sizeof(ar3kconfig));
+            ar6000_set_default_ar3kconfig(ar, (void *)&ar3kconfig);
+            status = ar->exitCallback(&ar3kconfig);
+            if (A_OK != status) {
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Failed to reset AR3K baud rate! \n"));
+            }
+        }
+        // END workaround
+        if (setuphci)
+        	ar6000_cleanup_hci(ar);
+#endif
+#ifdef EXPORT_HCI_PAL_INTERFACE
+        if (setuphcipal && (NULL != ar6kHciPalCallbacks_g.cleanupTransport)) {
+           ar6kHciPalCallbacks_g.cleanupTransport(ar);
+        }
+#else
+				/* cleanup hci pal driver data structures */
+        if(setuphcipal)
+          ar6k_cleanup_hci_pal(ar);
+#endif
+        AR_DEBUG_PRINTF(ATH_DEBUG_INFO,(" Shutting down HTC .... \n"));
+        /* stop HTC */
+        HTCStop(ar->arHtcTarget);
+    }
+
+    if (resetok) {
+        /* try to reset the device if we can
+         * The driver may have been configure NOT to reset the target during
+         * a debug session */
+        AR_DEBUG_PRINTF(ATH_DEBUG_INFO,(" Attempting to reset target on instance destroy.... \n"));
+        if (ar->arHifDevice != NULL) {
+            A_BOOL coldReset = (ar->arTargetType == TARGET_TYPE_AR6003) ? TRUE: FALSE;
+            ar6000_reset_device(ar->arHifDevice, ar->arTargetType, TRUE, coldReset);
+        }
+    } else {
+        AR_DEBUG_PRINTF(ATH_DEBUG_INFO,(" Host does not want target reset. \n"));
+    }
+       /* Done with cookies */
+    ar6000_cookie_cleanup(ar);
+}
+/*
+ * We need to differentiate between the surprise and planned removal of the
+ * device because of the following consideration:
+ * - In case of surprise removal, the hcd already frees up the pending
+ *   for the device and hence there is no need to unregister the function
+ *   driver inorder to get these requests. For planned removal, the function
+ *   driver has to explictly unregister itself to have the hcd return all the
+ *   pending requests before the data structures for the devices are freed up.
+ *   Note that as per the current implementation, the function driver will
+ *   end up releasing all the devices since there is no API to selectively
+ *   release a particular device.
+ * - Certain commands issued to the target can be skipped for surprise
+ *   removal since they will anyway not go through.
+ */
+void
+ar6000_destroy(struct net_device *dev, unsigned int unregister)
+{
+    AR_SOFTC_T *ar;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("+ar6000_destroy \n"));
+    
+    if((dev == NULL) || ((ar = ar6k_priv(dev)) == NULL))
+    {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("%s(): Failed to get device structure.\n", __func__));
+        return;
+    }
+
+    ar->bIsDestroyProgress = TRUE;
+
+    if (down_interruptible(&ar->arSem)) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("%s(): down_interruptible failed \n", __func__));
+        return;
+    }
+
+    if (ar->arWlanPowerState != WLAN_POWER_STATE_CUT_PWR) {
+        /* only stop endpoint if we are not stop it in suspend_ev */
+        ar6000_stop_endpoint(dev, FALSE, TRUE);
+    } else {
+        /* clear up the platform power state before rmmod */
+        plat_setup_power(1,0);
+    }
+
+    ar->arWlanState = WLAN_DISABLED;
+    if (ar->arHtcTarget != NULL) {
+        /* destroy HTC */
+        HTCDestroy(ar->arHtcTarget);
+    }
+    if (ar->arHifDevice != NULL) {
+        /*release the device so we do not get called back on remove incase we
+         * we're explicity destroyed by module unload */
+        HIFReleaseDevice(ar->arHifDevice);
+        HIFShutDownDevice(ar->arHifDevice);
+    }
+#ifdef ATH_AR6K_11N_SUPPORT
+    aggr_module_destroy(ar->aggr_cntxt);
+#endif
+
+       /* Done with cookies */
+    ar6000_cookie_cleanup(ar);
+
+        /* cleanup any allocated AMSDU buffers */
+    ar6000_cleanup_amsdu_rxbufs(ar);
+
+    if (bmienable) {
+        ar6000_sysfs_bmi_deinit(ar);
+    }
+
+    /* Cleanup BMI */
+    BMICleanup();
+
+    /* Clear the tx counters */
+    memset(tx_attempt, 0, sizeof(tx_attempt));
+    memset(tx_post, 0, sizeof(tx_post));
+    memset(tx_complete, 0, sizeof(tx_complete));
+
+#ifdef HTC_RAW_INTERFACE
+    if (ar->arRawHtc) {
+        A_FREE(ar->arRawHtc);
+        ar->arRawHtc = NULL;
+    }
+#endif 
+    /* Free up the device data structure */
+    if (unregister && is_netdev_registered) {		
+        unregister_netdev(dev);
+        is_netdev_registered = 0;
+    }
+    free_netdev(dev);
+
+#ifdef ATH6K_CONFIG_CFG80211
+    ar6k_cfg80211_deinit(ar);
+#endif /* ATH6K_CONFIG_CFG80211 */
+
+#ifdef CONFIG_AP_VIRTUL_ADAPTER_SUPPORT
+    ar6000_remove_ap_interface();
+#endif /*CONFIG_AP_VIRTUAL_ADAPTER_SUPPORT */
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("-ar6000_destroy \n"));
+}
+
+static void disconnect_timer_handler(unsigned long ptr)
+{
+    struct net_device *dev = (struct net_device *)ptr;
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+    A_UNTIMEOUT(&ar->disconnect_timer);
+
+    ar6000_init_profile_info(ar);
+    wmi_disconnect_cmd(ar->arWmi);
+}
+
+static void ar6000_detect_error(unsigned long ptr)
+{
+    struct net_device *dev = (struct net_device *)ptr;
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    WMI_TARGET_ERROR_REPORT_EVENT errEvent;
+
+    AR6000_SPIN_LOCK(&ar->arLock, 0);
+
+    if (ar->arHBChallengeResp.outstanding) {
+        ar->arHBChallengeResp.missCnt++;
+    } else {
+        ar->arHBChallengeResp.missCnt = 0;
+    }
+
+    if (ar->arHBChallengeResp.missCnt > ar->arHBChallengeResp.missThres) {
+        /* Send Error Detect event to the application layer and do not reschedule the error detection module timer */
+        ar->arHBChallengeResp.missCnt = 0;
+        ar->arHBChallengeResp.seqNum = 0;
+        errEvent.errorVal = WMI_TARGET_COM_ERR | WMI_TARGET_FATAL_ERR;
+        AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+        ar6000_send_event_to_app(ar, WMI_ERROR_REPORT_EVENTID,
+                                 (A_UINT8 *)&errEvent,
+                                 sizeof(WMI_TARGET_ERROR_REPORT_EVENT));
+        return;
+    }
+
+    /* Generate the sequence number for the next challenge */
+    ar->arHBChallengeResp.seqNum++;
+    ar->arHBChallengeResp.outstanding = TRUE;
+
+    AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+
+    /* Send the challenge on the control channel */
+    if (wmi_get_challenge_resp_cmd(ar->arWmi, ar->arHBChallengeResp.seqNum, DRV_HB_CHALLENGE) != A_OK) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Unable to send heart beat challenge\n"));
+    }
+
+
+    /* Reschedule the timer for the next challenge */
+    A_TIMEOUT_MS(&ar->arHBChallengeResp.timer, ar->arHBChallengeResp.frequency * 1000, 0);
+}
+
+void ar6000_init_profile_info(AR_SOFTC_T *ar)
+{
+    ar->arSsidLen            = 0;
+    A_MEMZERO(ar->arSsid, sizeof(ar->arSsid));
+
+    switch(fwmode) {
+        case HI_OPTION_FW_MODE_IBSS:
+            ar->arNetworkType = ar->arNextMode = ADHOC_NETWORK;
+            break;
+        case HI_OPTION_FW_MODE_BSS_STA:
+            ar->arNetworkType = ar->arNextMode = INFRA_NETWORK;
+            break;
+        case HI_OPTION_FW_MODE_AP:
+            ar->arNetworkType = ar->arNextMode = AP_NETWORK;
+            break;
+    }
+
+    ar->arDot11AuthMode      = OPEN_AUTH;
+    ar->arAuthMode           = NONE_AUTH;
+    ar->arPairwiseCrypto     = NONE_CRYPT;
+    ar->arPairwiseCryptoLen  = 0;
+    ar->arGroupCrypto        = NONE_CRYPT;
+    ar->arGroupCryptoLen     = 0;
+    A_MEMZERO(ar->arWepKeyList, sizeof(ar->arWepKeyList));
+    A_MEMZERO(ar->arReqBssid, sizeof(ar->arReqBssid));
+    A_MEMZERO(ar->arBssid, sizeof(ar->arBssid));
+    ar->arBssChannel = 0;
+    ar->arConnected = FALSE;
+}
+
+static void
+ar6000_init_control_info(AR_SOFTC_T *ar)
+{
+    ar->arWmiEnabled         = FALSE;
+    ar6000_init_profile_info(ar);
+    ar->arDefTxKeyIndex      = 0;
+    A_MEMZERO(ar->arWepKeyList, sizeof(ar->arWepKeyList));
+    ar->arChannelHint        = 0;
+    ar->arListenIntervalT    = A_DEFAULT_LISTEN_INTERVAL;
+    ar->arListenIntervalB    = 0;
+    ar->arVersion.host_ver   = AR6K_SW_VERSION;
+    ar->arRssi               = 0;
+    ar->arTxPwr              = 0;
+    ar->arTxPwrSet           = FALSE;
+    ar->arSkipScan           = 0;
+    ar->arBeaconInterval     = 0;
+    ar->arBitRate            = 0;
+    ar->arMaxRetries         = 0;
+    ar->arWmmEnabled         = TRUE;
+    ar->intra_bss            = 1;
+    ar->scan_triggered       = 0;
+    A_MEMZERO(&ar->scParams, sizeof(ar->scParams));
+    ar->scParams.shortScanRatio = WMI_SHORTSCANRATIO_DEFAULT;
+    ar->scParams.scanCtrlFlags = DEFAULT_SCAN_CTRL_FLAGS;
+
+    /* Initialize the AP mode state info */
+    {
+        A_UINT8 ctr;
+        A_MEMZERO((A_UINT8 *)ar->sta_list, AP_MAX_NUM_STA * sizeof(sta_t));
+
+        /* init the Mutexes */
+        A_MUTEX_INIT(&ar->mcastpsqLock);
+
+        /* Init the PS queues */
+        for (ctr=0; ctr < AP_MAX_NUM_STA ; ctr++) {
+            A_MUTEX_INIT(&ar->sta_list[ctr].psqLock);
+            A_NETBUF_QUEUE_INIT(&ar->sta_list[ctr].psq);
+        }
+
+        ar->ap_profile_flag = 0;
+        A_NETBUF_QUEUE_INIT(&ar->mcastpsq);
+
+        A_MEMCPY(ar->ap_country_code, DEF_AP_COUNTRY_CODE, 3);
+        ar->ap_wmode = DEF_AP_WMODE_G;
+        ar->ap_dtim_period = DEF_AP_DTIM;
+        ar->ap_beacon_interval = DEF_BEACON_INTERVAL;
+    }
+}
+
+static int
+ar6000_open(struct net_device *dev)
+{
+    unsigned long  flags;
+    AR_SOFTC_T    *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+    spin_lock_irqsave(&ar->arLock, flags);
+
+#ifdef ATH6K_CONFIG_CFG80211
+    if(ar->arWlanState == WLAN_DISABLED) {
+        ar->arWlanState = WLAN_ENABLED;
+    }
+#endif /* ATH6K_CONFIG_CFG80211 */
+
+    if( ar->arConnected || bypasswmi) {
+        netif_carrier_on(dev);
+        /* Wake up the queues */
+        netif_wake_queue(dev);
+    }
+    else
+        netif_carrier_off(dev);
+
+    spin_unlock_irqrestore(&ar->arLock, flags);
+    return 0;
+}
+
+static int
+ar6000_close(struct net_device *dev)
+{
+#ifdef ATH6K_CONFIG_CFG80211
+    AR_SOFTC_T    *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+#endif /* ATH6K_CONFIG_CFG80211 */
+    netif_stop_queue(dev);
+
+#ifdef ATH6K_CONFIG_CFG80211
+    AR6000_SPIN_LOCK(&ar->arLock, 0);
+    if (ar->arConnected == TRUE || ar->arConnectPending == TRUE) {
+        AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+        wmi_disconnect_cmd(ar->arWmi);
+    } else {
+        AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+    }
+
+    if(ar->arWmiReady == TRUE) {
+        if (wmi_scanparams_cmd(ar->arWmi, 0xFFFF, 0,
+                               0, 0, 0, 0, 0, 0, 0, 0) != A_OK) {
+            return -EIO;
+        }
+        ar->arWlanState = WLAN_DISABLED;
+    }
+#endif /* ATH6K_CONFIG_CFG80211 */
+
+    return 0;
+}
+
+/* connect to a service */
+static A_STATUS ar6000_connectservice(AR_SOFTC_T               *ar,
+                                      HTC_SERVICE_CONNECT_REQ  *pConnect,
+                                      char                     *pDesc)
+{
+    A_STATUS                 status;
+    HTC_SERVICE_CONNECT_RESP response;
+
+    do {
+
+        A_MEMZERO(&response,sizeof(response));
+
+        status = HTCConnectService(ar->arHtcTarget,
+                                   pConnect,
+                                   &response);
+
+        if (A_FAILED(status)) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" Failed to connect to %s service status:%d \n",
+                              pDesc, status));
+            break;
+        }
+        switch (pConnect->ServiceID) {
+            case WMI_CONTROL_SVC :
+                if (ar->arWmiEnabled) {
+                        /* set control endpoint for WMI use */
+                    wmi_set_control_ep(ar->arWmi, response.Endpoint);
+                }
+                    /* save EP for fast lookup */
+                ar->arControlEp = response.Endpoint;
+                break;
+            case WMI_DATA_BE_SVC :
+                arSetAc2EndpointIDMap(ar, WMM_AC_BE, response.Endpoint);
+                break;
+            case WMI_DATA_BK_SVC :
+                arSetAc2EndpointIDMap(ar, WMM_AC_BK, response.Endpoint);
+                break;
+            case WMI_DATA_VI_SVC :
+                arSetAc2EndpointIDMap(ar, WMM_AC_VI, response.Endpoint);
+                 break;
+           case WMI_DATA_VO_SVC :
+                arSetAc2EndpointIDMap(ar, WMM_AC_VO, response.Endpoint);
+                break;
+           default:
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("ServiceID not mapped %d\n", pConnect->ServiceID));
+                status = A_EINVAL;
+            break;
+        }
+
+    } while (FALSE);
+
+    return status;
+}
+
+void ar6000_TxDataCleanup(AR_SOFTC_T *ar)
+{
+        /* flush all the data (non-control) streams
+         * we only flush packets that are tagged as data, we leave any control packets that
+         * were in the TX queues alone */
+    HTCFlushEndpoint(ar->arHtcTarget,
+                     arAc2EndpointID(ar, WMM_AC_BE),
+                     AR6K_DATA_PKT_TAG);
+    HTCFlushEndpoint(ar->arHtcTarget,
+                     arAc2EndpointID(ar, WMM_AC_BK),
+                     AR6K_DATA_PKT_TAG);
+    HTCFlushEndpoint(ar->arHtcTarget,
+                     arAc2EndpointID(ar, WMM_AC_VI),
+                     AR6K_DATA_PKT_TAG);
+    HTCFlushEndpoint(ar->arHtcTarget,
+                     arAc2EndpointID(ar, WMM_AC_VO),
+                     AR6K_DATA_PKT_TAG);
+}
+
+HTC_ENDPOINT_ID
+ar6000_ac2_endpoint_id ( void * devt, A_UINT8 ac)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *) devt;
+    return(arAc2EndpointID(ar, ac));
+}
+
+A_UINT8
+ar6000_endpoint_id2_ac(void * devt, HTC_ENDPOINT_ID ep )
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *) devt;
+    return(arEndpoint2Ac(ar, ep ));
+}
+
+/* This function does one time initialization for the lifetime of the device */
+int ar6000_init(struct net_device *dev)
+{
+    AR_SOFTC_T *ar;
+    A_STATUS    status;
+    A_INT32     timeleft;
+    A_INT16     i;
+    int         ret = 0;
+#if defined(INIT_MODE_DRV_ENABLED) && defined(ENABLE_COEXISTENCE)
+    WMI_SET_BTCOEX_COLOCATED_BT_DEV_CMD sbcb_cmd;
+    WMI_SET_BTCOEX_FE_ANT_CMD sbfa_cmd;
+#endif /* INIT_MODE_DRV_ENABLED && ENABLE_COEXISTENCE */
+
+    if((ar = ar6k_priv(dev)) == NULL)
+    {
+        return -EIO;
+    }
+
+    if (wlaninitmode == WLAN_INIT_MODE_USR || wlaninitmode == WLAN_INIT_MODE_DRV) {
+    
+        ar6000_update_bdaddr(ar);
+
+        if (enablerssicompensation) {
+            ar6000_copy_cust_data_from_target(ar->arHifDevice, ar->arTargetType);
+            read_rssi_compensation_param(ar);
+            for (i=-95; i<=0; i++) {
+                rssi_compensation_table[0-i] = rssi_compensation_calc(ar,i);
+            }
+        }
+    }
+
+    dev_hold(dev);
+    rtnl_unlock();
+
+    /* Do we need to finish the BMI phase */
+    if ((wlaninitmode == WLAN_INIT_MODE_USR || wlaninitmode == WLAN_INIT_MODE_DRV) && 
+        (BMIDone(ar->arHifDevice) != A_OK))
+    {
+        ret = -EIO;
+        goto ar6000_init_done;
+    }
+
+    if (!bypasswmi)
+    {
+#if 0 /* TBDXXX */
+        if (ar->arVersion.host_ver != ar->arVersion.target_ver) {
+            A_PRINTF("WARNING: Host version 0x%x does not match Target "
+                    " version 0x%x!\n",
+                    ar->arVersion.host_ver, ar->arVersion.target_ver);
+        }
+#endif
+
+        /* Indicate that WMI is enabled (although not ready yet) */
+        ar->arWmiEnabled = TRUE;
+        if ((ar->arWmi = wmi_init((void *) ar)) == NULL)
+        {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("%s() Failed to initialize WMI.\n", __func__));
+            ret = -EIO;
+            goto ar6000_init_done;
+        }
+
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("%s() Got WMI @ 0x%lx.\n", __func__,
+            (unsigned long) ar->arWmi));
+    }
+
+    do {
+        HTC_SERVICE_CONNECT_REQ connect;
+
+            /* the reason we have to wait for the target here is that the driver layer
+             * has to init BMI in order to set the host block size,
+             */
+        status = HTCWaitTarget(ar->arHtcTarget);
+
+        if (A_FAILED(status)) {
+            break;
+        }
+
+        A_MEMZERO(&connect,sizeof(connect));
+            /* meta data is unused for now */
+        connect.pMetaData = NULL;
+        connect.MetaDataLength = 0;
+            /* these fields are the same for all service endpoints */
+        connect.EpCallbacks.pContext = ar;
+        connect.EpCallbacks.EpTxCompleteMultiple = ar6000_tx_complete;
+        connect.EpCallbacks.EpRecv = ar6000_rx;
+        connect.EpCallbacks.EpRecvRefill = ar6000_rx_refill;
+        connect.EpCallbacks.EpSendFull = ar6000_tx_queue_full;
+            /* set the max queue depth so that our ar6000_tx_queue_full handler gets called.
+             * Linux has the peculiarity of not providing flow control between the
+             * NIC and the network stack. There is no API to indicate that a TX packet
+             * was sent which could provide some back pressure to the network stack.
+             * Under linux you would have to wait till the network stack consumed all sk_buffs
+             * before any back-flow kicked in. Which isn't very friendly.
+             * So we have to manage this ourselves */
+        connect.MaxSendQueueDepth = MAX_DEFAULT_SEND_QUEUE_DEPTH;
+        connect.EpCallbacks.RecvRefillWaterMark = AR6000_MAX_RX_BUFFERS / 4; /* set to 25 % */
+        if (0 == connect.EpCallbacks.RecvRefillWaterMark) {
+            connect.EpCallbacks.RecvRefillWaterMark++;
+        }
+            /* connect to control service */
+        connect.ServiceID = WMI_CONTROL_SVC;
+        status = ar6000_connectservice(ar,
+                                       &connect,
+                                       "WMI CONTROL");
+        if (A_FAILED(status)) {
+            break;
+        }
+
+        connect.LocalConnectionFlags |= HTC_LOCAL_CONN_FLAGS_ENABLE_SEND_BUNDLE_PADDING;
+            /* limit the HTC message size on the send path, although we can receive A-MSDU frames of
+             * 4K, we will only send ethernet-sized (802.3) frames on the send path. */
+        connect.MaxSendMsgSize = WMI_MAX_TX_DATA_FRAME_LENGTH;
+
+            /* to reduce the amount of committed memory for larger A_MSDU frames, use the recv-alloc threshold
+             * mechanism for larger packets */
+        connect.EpCallbacks.RecvAllocThreshold = AR6000_BUFFER_SIZE;
+        connect.EpCallbacks.EpRecvAllocThresh = ar6000_alloc_amsdu_rxbuf;
+
+            /* for the remaining data services set the connection flag to reduce dribbling,
+             * if configured to do so */
+        if (reduce_credit_dribble) {
+            connect.ConnectionFlags |= HTC_CONNECT_FLAGS_REDUCE_CREDIT_DRIBBLE;
+            /* the credit dribble trigger threshold is (reduce_credit_dribble - 1) for a value
+             * of 0-3 */
+            connect.ConnectionFlags &= ~HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_MASK;
+            connect.ConnectionFlags |=
+                        ((A_UINT16)reduce_credit_dribble - 1) & HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_MASK;
+        }
+            /* connect to best-effort service */
+        connect.ServiceID = WMI_DATA_BE_SVC;
+
+        status = ar6000_connectservice(ar,
+                                       &connect,
+                                       "WMI DATA BE");
+        if (A_FAILED(status)) {
+            break;
+        }
+
+            /* connect to back-ground
+             * map this to WMI LOW_PRI */
+        connect.ServiceID = WMI_DATA_BK_SVC;
+        status = ar6000_connectservice(ar,
+                                       &connect,
+                                       "WMI DATA BK");
+        if (A_FAILED(status)) {
+            break;
+        }
+
+            /* connect to Video service, map this to
+             * to HI PRI */
+        connect.ServiceID = WMI_DATA_VI_SVC;
+        status = ar6000_connectservice(ar,
+                                       &connect,
+                                       "WMI DATA VI");
+        if (A_FAILED(status)) {
+            break;
+        }
+
+            /* connect to VO service, this is currently not
+             * mapped to a WMI priority stream due to historical reasons.
+             * WMI originally defined 3 priorities over 3 mailboxes
+             * We can change this when WMI is reworked so that priorities are not
+             * dependent on mailboxes */
+        connect.ServiceID = WMI_DATA_VO_SVC;
+        status = ar6000_connectservice(ar,
+                                       &connect,
+                                       "WMI DATA VO");
+        if (A_FAILED(status)) {
+            break;
+        }
+
+        A_ASSERT(arAc2EndpointID(ar,WMM_AC_BE) != 0);
+        A_ASSERT(arAc2EndpointID(ar,WMM_AC_BK) != 0);
+        A_ASSERT(arAc2EndpointID(ar,WMM_AC_VI) != 0);
+        A_ASSERT(arAc2EndpointID(ar,WMM_AC_VO) != 0);
+
+            /* setup access class priority mappings */
+        ar->arAcStreamPriMap[WMM_AC_BK] = 0; /* lowest  */
+        ar->arAcStreamPriMap[WMM_AC_BE] = 1; /*         */
+        ar->arAcStreamPriMap[WMM_AC_VI] = 2; /*         */
+        ar->arAcStreamPriMap[WMM_AC_VO] = 3; /* highest */
+
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+        if (setuphci && (NULL != ar6kHciTransCallbacks.setupTransport)) {
+            HCI_TRANSPORT_MISC_HANDLES hciHandles;
+
+            hciHandles.netDevice = ar->arNetDev;
+            hciHandles.hifDevice = ar->arHifDevice;
+            hciHandles.htcHandle = ar->arHtcTarget;
+            status = (A_STATUS)(ar6kHciTransCallbacks.setupTransport(&hciHandles));
+        }
+#else
+        if (setuphci) {
+                /* setup HCI */
+            status = ar6000_setup_hci(ar);
+        }
+#endif
+#ifdef EXPORT_HCI_PAL_INTERFACE
+        if (setuphcipal && (NULL != ar6kHciPalCallbacks_g.setupTransport))
+          status = ar6kHciPalCallbacks_g.setupTransport(ar);
+#else
+        if(setuphcipal)
+          status = ar6k_setup_hci_pal(ar);
+#endif
+
+    } while (FALSE);
+
+    if (A_FAILED(status)) {
+        ret = -EIO;
+        goto ar6000_init_done;
+    }
+
+    /*
+     * give our connected endpoints some buffers
+     */
+
+    ar6000_rx_refill(ar, ar->arControlEp);
+    ar6000_rx_refill(ar, arAc2EndpointID(ar,WMM_AC_BE));
+
+    /*
+     * We will post the receive buffers only for SPE or endpoint ping testing so we are
+     * making it conditional on the 'bypasswmi' flag.
+     */
+    if (bypasswmi) {
+        ar6000_rx_refill(ar,arAc2EndpointID(ar,WMM_AC_BK));
+        ar6000_rx_refill(ar,arAc2EndpointID(ar,WMM_AC_VI));
+        ar6000_rx_refill(ar,arAc2EndpointID(ar,WMM_AC_VO));
+    }
+
+    /* allocate some buffers that handle larger AMSDU frames */
+    ar6000_refill_amsdu_rxbufs(ar,AR6000_MAX_AMSDU_RX_BUFFERS);
+
+        /* setup credit distribution */
+    ar6000_setup_credit_dist(ar->arHtcTarget, &ar->arCreditStateInfo);
+
+    /* Since cookies are used for HTC transports, they should be */
+    /* initialized prior to enabling HTC.                        */
+    ar6000_cookie_init(ar);
+
+    /* start HTC */
+    status = HTCStart(ar->arHtcTarget);
+
+    if (status != A_OK) {
+        if (ar->arWmiEnabled == TRUE) {
+            wmi_shutdown(ar->arWmi);
+            ar->arWmiEnabled = FALSE;
+            ar->arWmi = NULL;
+        }
+        ar6000_cookie_cleanup(ar);
+        ret = -EIO;
+        goto ar6000_init_done;
+    }
+
+    if (!bypasswmi) {
+        /* Wait for Wmi event to be ready */
+        timeleft = wait_event_interruptible_timeout(arEvent,
+            (ar->arWmiReady == TRUE), wmitimeout * HZ);
+
+        if (ar->arVersion.abi_ver != AR6K_ABI_VERSION) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("ABI Version mismatch: Host(0x%x), Target(0x%x)\n", AR6K_ABI_VERSION, ar->arVersion.abi_ver));
+#ifndef ATH6K_SKIP_ABI_VERSION_CHECK
+            ret = -EIO;
+            goto ar6000_init_done;
+#endif /* ATH6K_SKIP_ABI_VERSION_CHECK */
+        }
+
+        if(!timeleft || signal_pending(current))
+        {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("WMI is not ready or wait was interrupted\n"));
+            ret = -EIO;
+            goto ar6000_init_done;
+        }
+
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("%s() WMI is ready\n", __func__));
+
+        /* Communicate the wmi protocol verision to the target */
+        if ((ar6000_set_host_app_area(ar)) != A_OK) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Unable to set the host app area\n"));
+        }
+
+        /* configure the device for rx dot11 header rules 0,0 are the default values
+         * therefore this command can be skipped if the inputs are 0,FALSE,FALSE.Required
+         if checksum offload is needed. Set RxMetaVersion to 2*/
+        if ((wmi_set_rx_frame_format_cmd(ar->arWmi,ar->rxMetaVersion, processDot11Hdr, processDot11Hdr)) != A_OK) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Unable to set the rx frame format.\n"));
+        }
+
+#if defined(INIT_MODE_DRV_ENABLED) && defined(ENABLE_COEXISTENCE)
+        /* Configure the type of BT collocated with WLAN */
+        A_MEMZERO(&sbcb_cmd, sizeof(WMI_SET_BTCOEX_COLOCATED_BT_DEV_CMD));
+#ifdef CONFIG_AR600x_BT_QCOM
+        sbcb_cmd.btcoexCoLocatedBTdev = 1;
+#elif defined(CONFIG_AR600x_BT_CSR)
+        sbcb_cmd.btcoexCoLocatedBTdev = 2;
+#elif defined(CONFIG_AR600x_BT_AR3001)
+        sbcb_cmd.btcoexCoLocatedBTdev = 3;
+#else
+#error Unsupported Bluetooth Type
+#endif /* Collocated Bluetooth Type */
+
+        if ((wmi_set_btcoex_colocated_bt_dev_cmd(ar->arWmi, &sbcb_cmd)) != A_OK)
+        {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Unable to set collocated BT type\n"));
+        }
+
+        /* Configure the type of BT collocated with WLAN */
+        A_MEMZERO(&sbfa_cmd, sizeof(WMI_SET_BTCOEX_FE_ANT_CMD));
+#ifdef CONFIG_AR600x_DUAL_ANTENNA
+        sbfa_cmd.btcoexFeAntType = 2;
+#elif defined(CONFIG_AR600x_SINGLE_ANTENNA)
+        sbfa_cmd.btcoexFeAntType = 1;
+#else
+#error Unsupported Front-End Antenna Configuration
+#endif /* AR600x Front-End Antenna Configuration */
+
+        if ((wmi_set_btcoex_fe_ant_cmd(ar->arWmi, &sbfa_cmd)) != A_OK) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Unable to set fornt end antenna configuration\n"));
+        }
+#endif /* INIT_MODE_DRV_ENABLED && ENABLE_COEXISTENCE */
+    }
+
+    ar->arNumDataEndPts = 1;
+
+    if (bypasswmi) {
+            /* for tests like endpoint ping, the MAC address needs to be non-zero otherwise
+             * the data path through a raw socket is disabled */
+        dev->dev_addr[0] = 0x00;
+        dev->dev_addr[1] = 0x01;
+        dev->dev_addr[2] = 0x02;
+        dev->dev_addr[3] = 0xAA;
+        dev->dev_addr[4] = 0xBB;
+        dev->dev_addr[5] = 0xCC;
+    }
+
+ar6000_init_done:
+    rtnl_lock();
+    dev_put(dev);
+
+    return ret;
+}
+
+
+void
+ar6000_bitrate_rx(void *devt, A_INT32 rateKbps)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)devt;
+
+    ar->arBitRate = rateKbps;
+    wake_up(&arEvent);
+}
+
+void
+ar6000_ratemask_rx(void *devt, A_UINT32 ratemask)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)devt;
+
+    ar->arRateMask = ratemask;
+    wake_up(&arEvent);
+}
+
+void
+ar6000_txPwr_rx(void *devt, A_UINT8 txPwr)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)devt;
+
+    ar->arTxPwr = txPwr;
+    wake_up(&arEvent);
+}
+
+
+void
+ar6000_channelList_rx(void *devt, A_INT8 numChan, A_UINT16 *chanList)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)devt;
+
+    A_MEMCPY(ar->arChannelList, chanList, numChan * sizeof (A_UINT16));
+    ar->arNumChannels = numChan;
+
+    wake_up(&arEvent);
+}
+
+A_UINT8
+ar6000_ibss_map_epid(struct sk_buff *skb, struct net_device *dev, A_UINT32 * mapNo)
+{
+    AR_SOFTC_T      *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    A_UINT8         *datap;
+    ATH_MAC_HDR     *macHdr;
+    A_UINT32         i, eptMap;
+
+    (*mapNo) = 0;
+    datap = A_NETBUF_DATA(skb);
+    macHdr = (ATH_MAC_HDR *)(datap + sizeof(WMI_DATA_HDR));
+    if (IEEE80211_IS_MULTICAST(macHdr->dstMac)) {
+        return ENDPOINT_2;
+    }
+
+    eptMap = -1;
+    for (i = 0; i < ar->arNodeNum; i ++) {
+        if (IEEE80211_ADDR_EQ(macHdr->dstMac, ar->arNodeMap[i].macAddress)) {
+            (*mapNo) = i + 1;
+            ar->arNodeMap[i].txPending ++;
+            return ar->arNodeMap[i].epId;
+        }
+
+        if ((eptMap == -1) && !ar->arNodeMap[i].txPending) {
+            eptMap = i;
+        }
+    }
+
+    if (eptMap == -1) {
+        eptMap = ar->arNodeNum;
+        ar->arNodeNum ++;
+        A_ASSERT(ar->arNodeNum <= MAX_NODE_NUM);
+    }
+
+    A_MEMCPY(ar->arNodeMap[eptMap].macAddress, macHdr->dstMac, IEEE80211_ADDR_LEN);
+
+    for (i = ENDPOINT_2; i <= ENDPOINT_5; i ++) {
+        if (!ar->arTxPending[i]) {
+            ar->arNodeMap[eptMap].epId = i;
+            break;
+        }
+        // No free endpoint is available, start redistribution on the inuse endpoints.
+        if (i == ENDPOINT_5) {
+            ar->arNodeMap[eptMap].epId = ar->arNexEpId;
+            ar->arNexEpId ++;
+            if (ar->arNexEpId > ENDPOINT_5) {
+                ar->arNexEpId = ENDPOINT_2;
+            }
+        }
+    }
+
+    (*mapNo) = eptMap + 1;
+    ar->arNodeMap[eptMap].txPending ++;
+
+    return ar->arNodeMap[eptMap].epId;
+}
+
+#ifdef DEBUG
+static void ar6000_dump_skb(struct sk_buff *skb)
+{
+   u_char *ch;
+   for (ch = A_NETBUF_DATA(skb);
+        (unsigned long)ch < ((unsigned long)A_NETBUF_DATA(skb) +
+        A_NETBUF_LEN(skb)); ch++)
+    {
+         AR_DEBUG_PRINTF(ATH_DEBUG_WARN,("%2.2x ", *ch));
+    }
+    AR_DEBUG_PRINTF(ATH_DEBUG_WARN,("\n"));
+}
+#endif
+
+#ifdef HTC_TEST_SEND_PKTS
+static void DoHTCSendPktsTest(AR_SOFTC_T *ar, int MapNo, HTC_ENDPOINT_ID eid, struct sk_buff *skb);
+#endif
+
+static int
+ar6000_data_tx(struct sk_buff *skb, struct net_device *dev)
+{
+#define AC_NOT_MAPPED   99
+    AR_SOFTC_T        *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    A_UINT8            ac = AC_NOT_MAPPED;
+    HTC_ENDPOINT_ID    eid = ENDPOINT_UNUSED;
+    A_UINT32          mapNo = 0;
+    int               len;
+    struct ar_cookie *cookie;
+    A_BOOL            checkAdHocPsMapping = FALSE,bMoreData = FALSE;
+    HTC_TX_TAG        htc_tag = AR6K_DATA_PKT_TAG;
+    A_UINT8           dot11Hdr = processDot11Hdr;
+#ifdef CONFIG_PM
+    if (ar->arWowState != WLAN_WOW_STATE_NONE) {
+        A_NETBUF_FREE(skb);
+        return 0;
+    }
+#endif /* CONFIG_PM */
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_TX,("ar6000_data_tx start - skb=0x%lx, data=0x%lx, len=0x%x\n",
+                     (unsigned long)skb, (unsigned long)A_NETBUF_DATA(skb),
+                     A_NETBUF_LEN(skb)));
+
+    /* If target is not associated */
+    if( (!ar->arConnected && !bypasswmi)
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+     /* TCMD doesnt support any data, free the buf and return */
+    || (ar->arTargetMode == AR6000_TCMD_MODE)
+#endif
+                                            ) {
+        A_NETBUF_FREE(skb);
+        return 0;
+    }
+
+    do {
+
+        if (ar->arWmiReady == FALSE && bypasswmi == 0) {
+            break;
+        }
+
+#ifdef BLOCK_TX_PATH_FLAG
+        if (blocktx) {
+            break;
+        }
+#endif /* BLOCK_TX_PATH_FLAG */
+
+        /* AP mode Power save processing */
+        /* If the dst STA is in sleep state, queue the pkt in its PS queue */
+
+        if (ar->arNetworkType == AP_NETWORK) {
+            ATH_MAC_HDR *datap = (ATH_MAC_HDR *)A_NETBUF_DATA(skb);
+            sta_t *conn = NULL;
+
+            /* If the dstMac is a Multicast address & atleast one of the
+             * associated STA is in PS mode, then queue the pkt to the
+             * mcastq
+             */
+            if (IEEE80211_IS_MULTICAST(datap->dstMac)) {
+                A_UINT8 ctr=0;
+                A_BOOL qMcast=FALSE;
+
+
+                for (ctr=0; ctr<AP_MAX_NUM_STA; ctr++) {
+                    if (STA_IS_PWR_SLEEP((&ar->sta_list[ctr]))) {
+                        qMcast = TRUE;
+                    }
+                }
+                if(qMcast) {
+
+                    /* If this transmit is not because of a Dtim Expiry q it */
+                    if (ar->DTIMExpired == FALSE) {
+                        A_BOOL isMcastqEmpty = FALSE;
+
+                        A_MUTEX_LOCK(&ar->mcastpsqLock);
+                        isMcastqEmpty = A_NETBUF_QUEUE_EMPTY(&ar->mcastpsq);
+                        A_NETBUF_ENQUEUE(&ar->mcastpsq, skb);
+                        A_MUTEX_UNLOCK(&ar->mcastpsqLock);
+
+                        /* If this is the first Mcast pkt getting queued
+                         * indicate to the target to set the BitmapControl LSB
+                         * of the TIM IE.
+                         */
+                        if (isMcastqEmpty) {
+                             wmi_set_pvb_cmd(ar->arWmi, MCAST_AID, 1);
+                        }
+                        return 0;
+                    } else {
+                     /* This transmit is because of Dtim expiry. Determine if
+                      * MoreData bit has to be set.
+                      */
+                         A_MUTEX_LOCK(&ar->mcastpsqLock);
+                         if(!A_NETBUF_QUEUE_EMPTY(&ar->mcastpsq)) {
+                             bMoreData = TRUE;
+                         }
+                         A_MUTEX_UNLOCK(&ar->mcastpsqLock);
+                    }
+                }
+            } else {
+                conn = ieee80211_find_conn(ar, datap->dstMac);
+                if (conn) {
+                    if (STA_IS_PWR_SLEEP(conn)) {
+                        /* If this transmit is not because of a PsPoll q it*/
+                        if (!STA_IS_PS_POLLED(conn)) {
+                            A_BOOL isPsqEmpty = FALSE;
+                            /* Queue the frames if the STA is sleeping */
+                            A_MUTEX_LOCK(&conn->psqLock);
+                            isPsqEmpty = A_NETBUF_QUEUE_EMPTY(&conn->psq);
+                            A_NETBUF_ENQUEUE(&conn->psq, skb);
+                            A_MUTEX_UNLOCK(&conn->psqLock);
+
+                            /* If this is the first pkt getting queued
+                             * for this STA, update the PVB for this STA
+                             */
+                            if (isPsqEmpty) {
+                                wmi_set_pvb_cmd(ar->arWmi, conn->aid, 1);
+                            }
+
+                            return 0;
+                         } else {
+                         /* This tx is because of a PsPoll. Determine if
+                          * MoreData bit has to be set
+                          */
+                             A_MUTEX_LOCK(&conn->psqLock);
+                             if (!A_NETBUF_QUEUE_EMPTY(&conn->psq)) {
+                                 bMoreData = TRUE;
+                             }
+                             A_MUTEX_UNLOCK(&conn->psqLock);
+                         }
+                    }
+                } else {
+
+                    /* non existent STA. drop the frame */
+                    A_NETBUF_FREE(skb);
+                    return 0;
+                }
+            }
+        }
+
+        if (ar->arWmiEnabled) {
+#ifdef CONFIG_CHECKSUM_OFFLOAD
+        A_UINT8 csumStart=0;
+        A_UINT8 csumDest=0;
+        A_UINT8 csum=skb->ip_summed;
+        if(csumOffload && (csum==CHECKSUM_PARTIAL)){
+            csumStart = (skb->head + skb->csum_start - skb_network_header(skb) +
+			 sizeof(ATH_LLC_SNAP_HDR));
+            csumDest=skb->csum_offset+csumStart;
+        }
+#endif
+            if (A_NETBUF_HEADROOM(skb) < dev->hard_header_len - LINUX_HACK_FUDGE_FACTOR) {
+                struct sk_buff  *newbuf;
+
+                /*
+                 * We really should have gotten enough headroom but sometimes
+                 * we still get packets with not enough headroom.  Copy the packet.
+                 */
+                len = A_NETBUF_LEN(skb);
+                newbuf = A_NETBUF_ALLOC(len);
+                if (newbuf == NULL) {
+                    break;
+                }
+                A_NETBUF_PUT(newbuf, len);
+                A_MEMCPY(A_NETBUF_DATA(newbuf), A_NETBUF_DATA(skb), len);
+                A_NETBUF_FREE(skb);
+                skb = newbuf;
+                /* fall through and assemble header */
+            }
+
+            if (dot11Hdr) {
+                if (wmi_dot11_hdr_add(ar->arWmi,skb,ar->arNetworkType) != A_OK) {
+                    AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("ar6000_data_tx-wmi_dot11_hdr_add failed\n"));
+                    break;
+                }
+            } else {
+                if (wmi_dix_2_dot3(ar->arWmi, skb) != A_OK) {
+                    AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("ar6000_data_tx - wmi_dix_2_dot3 failed\n"));
+                    break;
+                }
+            }
+#ifdef CONFIG_CHECKSUM_OFFLOAD
+            if(csumOffload && (csum ==CHECKSUM_PARTIAL)){
+                WMI_TX_META_V2  metaV2;
+                metaV2.csumStart =csumStart;
+                metaV2.csumDest = csumDest;
+                metaV2.csumFlags = 0x1;/*instruct target to calculate checksum*/
+                if (wmi_data_hdr_add(ar->arWmi, skb, DATA_MSGTYPE, bMoreData, dot11Hdr,
+                                        WMI_META_VERSION_2,&metaV2) != A_OK) {
+                    AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("ar6000_data_tx - wmi_data_hdr_add failed\n"));
+                    break;
+                }
+
+            }
+            else
+#endif
+            {
+                if (wmi_data_hdr_add(ar->arWmi, skb, DATA_MSGTYPE, bMoreData, dot11Hdr,0,NULL) != A_OK) {
+                    AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("ar6000_data_tx - wmi_data_hdr_add failed\n"));
+                    break;
+                }
+            }
+
+
+            if ((ar->arNetworkType == ADHOC_NETWORK) &&
+                ar->arIbssPsEnable && ar->arConnected) {
+                    /* flag to check adhoc mapping once we take the lock below: */
+                checkAdHocPsMapping = TRUE;
+
+            } else {
+                    /* get the stream mapping */
+                ac  =  wmi_implicit_create_pstream(ar->arWmi, skb, 0, ar->arWmmEnabled);
+            }
+
+        } else {
+            EPPING_HEADER    *eppingHdr;
+
+            eppingHdr = A_NETBUF_DATA(skb);
+
+            if (IS_EPPING_PACKET(eppingHdr)) {
+                    /* the stream ID is mapped to an access class */
+                ac = eppingHdr->StreamNo_h;
+                    /* some EPPING packets cannot be dropped no matter what access class it was
+                     * sent on.  We can change the packet tag to guarantee it will not get dropped */
+                if (IS_EPING_PACKET_NO_DROP(eppingHdr)) {
+                    htc_tag = AR6K_CONTROL_PKT_TAG;
+                }
+
+                if (ac == HCI_TRANSPORT_STREAM_NUM) {
+                        /* pass this to HCI */
+#ifndef EXPORT_HCI_BRIDGE_INTERFACE
+                    if (A_SUCCESS(hci_test_send(ar,skb))) {
+                        return 0;
+                    }
+#endif
+                        /* set AC to discard this skb */
+                    ac = AC_NOT_MAPPED;
+                } else {
+                    /* a quirk of linux, the payload of the frame is 32-bit aligned and thus the addition
+                     * of the HTC header will mis-align the start of the HTC frame, so we add some
+                     * padding which will be stripped off in the target */
+                    if (EPPING_ALIGNMENT_PAD > 0) {
+                        A_NETBUF_PUSH(skb, EPPING_ALIGNMENT_PAD);
+                    }
+                }
+
+            } else {
+                    /* not a ping packet, drop it */
+                ac = AC_NOT_MAPPED;
+            }
+        }
+
+    } while (FALSE);
+
+        /* did we succeed ? */
+    if ((ac == AC_NOT_MAPPED) && !checkAdHocPsMapping) {
+            /* cleanup and exit */
+        A_NETBUF_FREE(skb);
+        AR6000_STAT_INC(ar, tx_dropped);
+        AR6000_STAT_INC(ar, tx_aborted_errors);
+        return 0;
+    }
+
+    cookie = NULL;
+
+        /* take the lock to protect driver data */
+    AR6000_SPIN_LOCK(&ar->arLock, 0);
+
+    do {
+
+        if (checkAdHocPsMapping) {
+            eid = ar6000_ibss_map_epid(skb, dev, &mapNo);
+        }else {
+            eid = arAc2EndpointID (ar, ac);
+        }
+            /* validate that the endpoint is connected */
+        if (eid == 0 || eid == ENDPOINT_UNUSED ) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" eid %d is NOT mapped!\n", eid));
+            break;
+        }
+            /* allocate resource for this packet */
+        cookie = ar6000_alloc_cookie(ar);
+
+        if (cookie != NULL) {
+                /* update counts while the lock is held */
+            ar->arTxPending[eid]++;
+            ar->arTotalTxDataPending++;
+        }
+
+    } while (FALSE);
+
+    AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+
+    if (cookie != NULL) {
+        cookie->arc_bp[0] = (unsigned long)skb;
+        cookie->arc_bp[1] = mapNo;
+        SET_HTC_PACKET_INFO_TX(&cookie->HtcPkt,
+                               cookie,
+                               A_NETBUF_DATA(skb),
+                               A_NETBUF_LEN(skb),
+                               eid,
+                               htc_tag);
+
+#ifdef DEBUG
+        if (debugdriver >= 3) {
+            ar6000_dump_skb(skb);
+        }
+#endif
+#ifdef HTC_TEST_SEND_PKTS
+        DoHTCSendPktsTest(ar,mapNo,eid,skb);
+#endif
+            /* HTC interface is asynchronous, if this fails, cleanup will happen in
+             * the ar6000_tx_complete callback */
+        HTCSendPkt(ar->arHtcTarget, &cookie->HtcPkt);
+    } else {
+            /* no packet to send, cleanup */
+        A_NETBUF_FREE(skb);
+        AR6000_STAT_INC(ar, tx_dropped);
+        AR6000_STAT_INC(ar, tx_aborted_errors);
+    }
+
+    return 0;
+}
+
+int
+ar6000_acl_data_tx(struct sk_buff *skb, struct net_device *dev)
+{
+    AR_SOFTC_T        *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    struct ar_cookie *cookie;
+    HTC_ENDPOINT_ID    eid = ENDPOINT_UNUSED;
+
+    cookie = NULL;
+    AR6000_SPIN_LOCK(&ar->arLock, 0);
+
+        /* For now we send ACL on BE endpoint: We can also have a dedicated EP */
+        eid = arAc2EndpointID (ar, 0);
+        /* allocate resource for this packet */
+        cookie = ar6000_alloc_cookie(ar);
+
+        if (cookie != NULL) {
+            /* update counts while the lock is held */
+            ar->arTxPending[eid]++;
+            ar->arTotalTxDataPending++;
+        }
+
+
+    AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+
+        if (cookie != NULL) {
+            cookie->arc_bp[0] = (unsigned long)skb;
+            cookie->arc_bp[1] = 0;
+            SET_HTC_PACKET_INFO_TX(&cookie->HtcPkt,
+                            cookie,
+                            A_NETBUF_DATA(skb),
+                            A_NETBUF_LEN(skb),
+                            eid,
+                            AR6K_DATA_PKT_TAG);
+
+            /* HTC interface is asynchronous, if this fails, cleanup will happen in
+             * the ar6000_tx_complete callback */
+            HTCSendPkt(ar->arHtcTarget, &cookie->HtcPkt);
+        } else {
+            /* no packet to send, cleanup */
+            A_NETBUF_FREE(skb);
+            AR6000_STAT_INC(ar, tx_dropped);
+            AR6000_STAT_INC(ar, tx_aborted_errors);
+        }
+    return 0;
+}
+
+
+#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL
+static void
+tvsub(register struct timeval *out, register struct timeval *in)
+{
+    if((out->tv_usec -= in->tv_usec) < 0) {
+        out->tv_sec--;
+        out->tv_usec += 1000000;
+    }
+    out->tv_sec -= in->tv_sec;
+}
+
+void
+applyAPTCHeuristics(AR_SOFTC_T *ar)
+{
+    A_UINT32 duration;
+    A_UINT32 numbytes;
+    A_UINT32 throughput;
+    struct timeval ts;
+    A_STATUS status;
+
+    AR6000_SPIN_LOCK(&ar->arLock, 0);
+
+    if ((enableAPTCHeuristics) && (!aptcTR.timerScheduled)) {
+        do_gettimeofday(&ts);
+        tvsub(&ts, &aptcTR.samplingTS);
+        duration = ts.tv_sec * 1000 + ts.tv_usec / 1000; /* ms */
+        numbytes = aptcTR.bytesTransmitted + aptcTR.bytesReceived;
+
+        if (duration > APTC_TRAFFIC_SAMPLING_INTERVAL) {
+            /* Initialize the time stamp and byte count */
+            aptcTR.bytesTransmitted = aptcTR.bytesReceived = 0;
+            do_gettimeofday(&aptcTR.samplingTS);
+
+            /* Calculate and decide based on throughput thresholds */
+            throughput = ((numbytes * 8) / duration);
+            if (throughput > APTC_UPPER_THROUGHPUT_THRESHOLD) {
+                /* Disable Sleep and schedule a timer */
+                A_ASSERT(ar->arWmiReady == TRUE);
+                AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+                status = wmi_powermode_cmd(ar->arWmi, MAX_PERF_POWER);
+                AR6000_SPIN_LOCK(&ar->arLock, 0);
+                A_TIMEOUT_MS(&aptcTimer, APTC_TRAFFIC_SAMPLING_INTERVAL, 0);
+                aptcTR.timerScheduled = TRUE;
+            }
+        }
+    }
+
+    AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+}
+#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */
+
+static HTC_SEND_FULL_ACTION ar6000_tx_queue_full(void *Context, HTC_PACKET *pPacket)
+{
+    AR_SOFTC_T     *ar = (AR_SOFTC_T *)Context;
+    HTC_SEND_FULL_ACTION    action = HTC_SEND_FULL_KEEP;
+    A_BOOL                  stopNet = FALSE;
+    HTC_ENDPOINT_ID         Endpoint = HTC_GET_ENDPOINT_FROM_PKT(pPacket);
+
+    do {
+
+        if (bypasswmi) {
+            int accessClass;
+
+            if (HTC_GET_TAG_FROM_PKT(pPacket) == AR6K_CONTROL_PKT_TAG) {
+                    /* don't drop special control packets */
+                break;
+            }
+
+            accessClass = arEndpoint2Ac(ar,Endpoint);
+                /* for endpoint ping testing drop Best Effort and Background */
+            if ((accessClass == WMM_AC_BE) || (accessClass == WMM_AC_BK)) {
+                action = HTC_SEND_FULL_DROP;
+                stopNet = FALSE;
+            } else {
+                    /* keep but stop the netqueues */
+                stopNet = TRUE;
+            }
+            break;
+        }
+
+        if (Endpoint == ar->arControlEp) {
+                /* under normal WMI if this is getting full, then something is running rampant
+                 * the host should not be exhausting the WMI queue with too many commands
+                 * the only exception to this is during testing using endpointping */
+            AR6000_SPIN_LOCK(&ar->arLock, 0);
+                /* set flag to handle subsequent messages */
+            ar->arWMIControlEpFull = TRUE;
+            AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("WMI Control Endpoint is FULL!!! \n"));
+                /* no need to stop the network */
+            stopNet = FALSE;
+            break;
+        }
+
+        /* if we get here, we are dealing with data endpoints getting full */
+
+        if (HTC_GET_TAG_FROM_PKT(pPacket) == AR6K_CONTROL_PKT_TAG) {
+            /* don't drop control packets issued on ANY data endpoint */
+            break;
+        }
+
+        if (ar->arNetworkType == ADHOC_NETWORK) {
+            /* in adhoc mode, we cannot differentiate traffic priorities so there is no need to
+             * continue, however we should stop the network */
+            stopNet = TRUE;
+            break;
+        }
+        /* the last MAX_HI_COOKIE_NUM "batch" of cookies are reserved for the highest
+         * active stream */
+        if (ar->arAcStreamPriMap[arEndpoint2Ac(ar,Endpoint)] < ar->arHiAcStreamActivePri &&
+            ar->arCookieCount <= MAX_HI_COOKIE_NUM) {
+                /* this stream's priority is less than the highest active priority, we
+                 * give preference to the highest priority stream by directing
+                 * HTC to drop the packet that overflowed */
+            action = HTC_SEND_FULL_DROP;
+                /* since we are dropping packets, no need to stop the network */
+            stopNet = FALSE;
+            break;
+        }
+
+    } while (FALSE);
+
+    if (stopNet) {
+        AR6000_SPIN_LOCK(&ar->arLock, 0);
+        ar->arNetQueueStopped = TRUE;
+        AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+        /* one of the data endpoints queues is getting full..need to stop network stack
+         * the queue will resume in ar6000_tx_complete() */
+        netif_stop_queue(ar->arNetDev);
+    }
+
+    return action;
+}
+
+
+static void
+ar6000_tx_complete(void *Context, HTC_PACKET_QUEUE *pPacketQueue)
+{
+    AR_SOFTC_T     *ar = (AR_SOFTC_T *)Context;
+    A_UINT32        mapNo = 0;
+    A_STATUS        status;
+    struct ar_cookie * ar_cookie;
+    HTC_ENDPOINT_ID   eid;
+    A_BOOL          wakeEvent = FALSE;
+    struct sk_buff_head  skb_queue;
+    HTC_PACKET      *pPacket;
+    struct sk_buff  *pktSkb;
+    A_BOOL          flushing = FALSE;
+
+    skb_queue_head_init(&skb_queue);
+
+        /* lock the driver as we update internal state */
+    AR6000_SPIN_LOCK(&ar->arLock, 0);
+
+        /* reap completed packets */
+    while (!HTC_QUEUE_EMPTY(pPacketQueue)) {
+
+        pPacket = HTC_PACKET_DEQUEUE(pPacketQueue);
+
+        ar_cookie = (struct ar_cookie *)pPacket->pPktContext;
+        A_ASSERT(ar_cookie);
+
+        status = pPacket->Status;
+        pktSkb = (struct sk_buff *)ar_cookie->arc_bp[0];
+        eid = pPacket->Endpoint;
+        mapNo = ar_cookie->arc_bp[1];
+
+        A_ASSERT(pktSkb);
+        A_ASSERT(pPacket->pBuffer == A_NETBUF_DATA(pktSkb));
+
+            /* add this to the list, use faster non-lock API */
+        __skb_queue_tail(&skb_queue,pktSkb);
+
+        if (A_SUCCESS(status)) {
+            A_ASSERT(pPacket->ActualLength == A_NETBUF_LEN(pktSkb));
+        }
+
+        AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_TX,("ar6000_tx_complete skb=0x%lx data=0x%lx len=0x%x eid=%d ",
+                         (unsigned long)pktSkb, (unsigned long)pPacket->pBuffer,
+                         pPacket->ActualLength,
+                         eid));
+
+        ar->arTxPending[eid]--;
+
+        if ((eid  != ar->arControlEp) || bypasswmi) {
+            ar->arTotalTxDataPending--;
+        }
+
+        if (eid == ar->arControlEp)
+        {
+            if (ar->arWMIControlEpFull) {
+                    /* since this packet completed, the WMI EP is no longer full */
+                ar->arWMIControlEpFull = FALSE;
+            }
+
+            if (ar->arTxPending[eid] == 0) {
+                wakeEvent = TRUE;
+            }
+        }
+
+        if (A_FAILED(status)) {
+            if (status == A_ECANCELED) {
+                    /* a packet was flushed  */
+                flushing = TRUE;
+            }
+            AR6000_STAT_INC(ar, tx_errors);
+            if (status != A_NO_RESOURCE) {
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("%s() -TX ERROR, status: 0x%x\n", __func__,
+                            status));
+            }
+        } else {
+            AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_TX,("OK\n"));
+            flushing = FALSE;
+            AR6000_STAT_INC(ar, tx_packets);
+            ar->arNetStats.tx_bytes += A_NETBUF_LEN(pktSkb);
+#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL
+            aptcTR.bytesTransmitted += a_netbuf_to_len(pktSkb);
+            applyAPTCHeuristics(ar);
+#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */
+        }
+
+        // TODO this needs to be looked at
+        if ((ar->arNetworkType == ADHOC_NETWORK) && ar->arIbssPsEnable
+            && (eid != ar->arControlEp) && mapNo)
+        {
+            mapNo --;
+            ar->arNodeMap[mapNo].txPending --;
+
+            if (!ar->arNodeMap[mapNo].txPending && (mapNo == (ar->arNodeNum - 1))) {
+                A_UINT32 i;
+                for (i = ar->arNodeNum; i > 0; i --) {
+                    if (!ar->arNodeMap[i - 1].txPending) {
+                        A_MEMZERO(&ar->arNodeMap[i - 1], sizeof(struct ar_node_mapping));
+                        ar->arNodeNum --;
+                    } else {
+                        break;
+                    }
+                }
+            }
+        }
+
+        ar6000_free_cookie(ar, ar_cookie);
+
+        if (ar->arNetQueueStopped) {
+            ar->arNetQueueStopped = FALSE;
+        }
+    }
+
+    AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+
+    /* lock is released, we can freely call other kernel APIs */
+
+        /* free all skbs in our local list */
+    while (!skb_queue_empty(&skb_queue)) {
+            /* use non-lock version */
+        pktSkb = __skb_dequeue(&skb_queue);
+        A_NETBUF_FREE(pktSkb);
+    }
+
+    if ((ar->arConnected == TRUE) || (bypasswmi)) {
+        if (!flushing) {
+                /* don't wake the queue if we are flushing, other wise it will just
+                 * keep queueing packets, which will keep failing */
+            netif_wake_queue(ar->arNetDev);
+        }
+    }
+
+    if (wakeEvent) {
+        wake_up(&arEvent);
+    }
+
+}
+
+sta_t *
+ieee80211_find_conn(AR_SOFTC_T *ar, A_UINT8 *node_addr)
+{
+    sta_t *conn = NULL;
+    A_UINT8 i, max_conn;
+
+    switch(ar->arNetworkType) {
+        case AP_NETWORK:
+            max_conn = AP_MAX_NUM_STA;
+            break;
+        default:
+            max_conn=0;
+            break;
+    }
+
+    for (i = 0; i < max_conn; i++) {
+        if (IEEE80211_ADDR_EQ(node_addr, ar->sta_list[i].mac)) {
+            conn = &ar->sta_list[i];
+            break;
+        }
+    }
+
+    return conn;
+}
+
+sta_t *ieee80211_find_conn_for_aid(AR_SOFTC_T *ar, A_UINT8 aid)
+{
+    sta_t *conn = NULL;
+    A_UINT8 ctr;
+
+    for (ctr = 0; ctr < AP_MAX_NUM_STA; ctr++) {
+        if (ar->sta_list[ctr].aid == aid) {
+            conn = &ar->sta_list[ctr];
+            break;
+        }
+    }
+    return conn;
+}
+
+/*
+ * Receive event handler.  This is called by HTC when a packet is received
+ */
+int pktcount;
+static void
+ar6000_rx(void *Context, HTC_PACKET *pPacket)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)Context;
+    struct sk_buff *skb = (struct sk_buff *)pPacket->pPktContext;
+    int minHdrLen;
+    A_UINT8 containsDot11Hdr = 0;
+    A_STATUS        status = pPacket->Status;
+    HTC_ENDPOINT_ID   ept = pPacket->Endpoint;
+
+    A_ASSERT((status != A_OK) ||
+             (pPacket->pBuffer == (A_NETBUF_DATA(skb) + HTC_HEADER_LEN)));
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_RX,("ar6000_rx ar=0x%lx eid=%d, skb=0x%lx, data=0x%lx, len=0x%x status:%d",
+                    (unsigned long)ar, ept, (unsigned long)skb, (unsigned long)pPacket->pBuffer,
+                    pPacket->ActualLength, status));
+    if (status != A_OK) {
+        if (status != A_ECANCELED) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("RX ERR (%d) \n",status));
+        }
+    }
+
+        /* take lock to protect buffer counts
+         * and adaptive power throughput state */
+    AR6000_SPIN_LOCK(&ar->arLock, 0);
+
+    if (A_SUCCESS(status)) {
+        AR6000_STAT_INC(ar, rx_packets);
+        ar->arNetStats.rx_bytes += pPacket->ActualLength;
+#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL
+        aptcTR.bytesReceived += a_netbuf_to_len(skb);
+        applyAPTCHeuristics(ar);
+#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */
+
+        A_NETBUF_PUT(skb, pPacket->ActualLength +  HTC_HEADER_LEN);
+        A_NETBUF_PULL(skb, HTC_HEADER_LEN);
+
+#ifdef DEBUG
+        if (debugdriver >= 2) {
+            ar6000_dump_skb(skb);
+        }
+#endif /* DEBUG */
+    }
+
+    AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+
+    skb->dev = ar->arNetDev;
+    if (status != A_OK) {
+        AR6000_STAT_INC(ar, rx_errors);
+        A_NETBUF_FREE(skb);
+    } else if (ar->arWmiEnabled == TRUE) {
+        if (ept == ar->arControlEp) {
+           /*
+            * this is a wmi control msg
+            */
+#ifdef CONFIG_PM 
+            ar6000_check_wow_status(ar, skb, TRUE);
+#endif /* CONFIG_PM */
+            wmi_control_rx(ar->arWmi, skb);
+        } else {
+                WMI_DATA_HDR *dhdr = (WMI_DATA_HDR *)A_NETBUF_DATA(skb);
+                A_UINT8 is_amsdu, tid, is_acl_data_frame;
+                is_acl_data_frame = WMI_DATA_HDR_GET_DATA_TYPE(dhdr) == WMI_DATA_HDR_DATA_TYPE_ACL;
+#ifdef CONFIG_PM 
+                ar6000_check_wow_status(ar, NULL, FALSE);
+#endif /* CONFIG_PM */
+                /*
+                 * this is a wmi data packet
+                 */
+                 // NWF
+
+                if (processDot11Hdr) {
+                    minHdrLen = sizeof(WMI_DATA_HDR) + sizeof(struct ieee80211_frame) + sizeof(ATH_LLC_SNAP_HDR);
+                } else {
+                    minHdrLen = sizeof (WMI_DATA_HDR) + sizeof(ATH_MAC_HDR) +
+                          sizeof(ATH_LLC_SNAP_HDR);
+                }
+
+                /* In the case of AP mode we may receive NULL data frames
+                 * that do not have LLC hdr. They are 16 bytes in size.
+                 * Allow these frames in the AP mode.
+                 * ACL data frames don't follow ethernet frame bounds for
+                 * min length
+                 */
+                if (ar->arNetworkType != AP_NETWORK &&  !is_acl_data_frame &&
+                    ((pPacket->ActualLength < minHdrLen) ||
+                    (pPacket->ActualLength > AR6000_MAX_RX_MESSAGE_SIZE)))
+                {
+                    /*
+                     * packet is too short or too long
+                     */
+                    AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("TOO SHORT or TOO LONG\n"));
+                    AR6000_STAT_INC(ar, rx_errors);
+                    AR6000_STAT_INC(ar, rx_length_errors);
+                    A_NETBUF_FREE(skb);
+                } else {
+                    A_UINT16 seq_no;
+                    A_UINT8 meta_type;
+
+#if 0
+                    /* Access RSSI values here */
+                    AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("RSSI %d\n",
+                        ((WMI_DATA_HDR *) A_NETBUF_DATA(skb))->rssi));
+#endif
+                    /* Get the Power save state of the STA */
+                    if (ar->arNetworkType == AP_NETWORK) {
+                        sta_t *conn = NULL;
+                        A_UINT8 psState=0,prevPsState;
+                        ATH_MAC_HDR *datap=NULL;
+                        A_UINT16 offset;
+
+                        meta_type = WMI_DATA_HDR_GET_META(dhdr);
+
+                        psState = (((WMI_DATA_HDR *)A_NETBUF_DATA(skb))->info
+                                     >> WMI_DATA_HDR_PS_SHIFT) & WMI_DATA_HDR_PS_MASK;
+
+                        offset = sizeof(WMI_DATA_HDR);
+
+                        switch (meta_type) {
+                            case 0:
+                                break;
+                            case WMI_META_VERSION_1:
+                                offset += sizeof(WMI_RX_META_V1);
+                                break;
+#ifdef CONFIG_CHECKSUM_OFFLOAD
+                            case WMI_META_VERSION_2:
+                                offset += sizeof(WMI_RX_META_V2);
+                                break;
+#endif
+                            default:
+                                break;
+                        }
+
+                        datap = (ATH_MAC_HDR *)(A_NETBUF_DATA(skb)+offset);
+                        conn = ieee80211_find_conn(ar, datap->srcMac);
+
+                        if (conn) {
+                            /* if there is a change in PS state of the STA,
+                             * take appropriate steps.
+                             * 1. If Sleep-->Awake, flush the psq for the STA
+                             *    Clear the PVB for the STA.
+                             * 2. If Awake-->Sleep, Starting queueing frames
+                             * the STA.
+                             */
+                            prevPsState = STA_IS_PWR_SLEEP(conn);
+                            if (psState) {
+                                STA_SET_PWR_SLEEP(conn);
+                            } else {
+                                STA_CLR_PWR_SLEEP(conn);
+                            }
+
+                            if (prevPsState ^ STA_IS_PWR_SLEEP(conn)) {
+
+                                if (!STA_IS_PWR_SLEEP(conn)) {
+
+                                    A_MUTEX_LOCK(&conn->psqLock);
+                                    while (!A_NETBUF_QUEUE_EMPTY(&conn->psq)) {
+                                        struct sk_buff *skb=NULL;
+
+                                        skb = A_NETBUF_DEQUEUE(&conn->psq);
+                                        A_MUTEX_UNLOCK(&conn->psqLock);
+                                        ar6000_data_tx(skb,ar->arNetDev);
+                                        A_MUTEX_LOCK(&conn->psqLock);
+                                    }
+                                    A_MUTEX_UNLOCK(&conn->psqLock);
+                                    /* Clear the PVB for this STA */
+                                    wmi_set_pvb_cmd(ar->arWmi, conn->aid, 0);
+                                }
+                            }
+                        } else {
+                            /* This frame is from a STA that is not associated*/
+                            A_ASSERT(FALSE);
+                        }
+
+                        /* Drop NULL data frames here */
+                        if((pPacket->ActualLength < minHdrLen) ||
+                                (pPacket->ActualLength > AR6000_MAX_RX_MESSAGE_SIZE)) {
+                            A_NETBUF_FREE(skb);
+                            goto rx_done;
+                        }
+                    }
+
+                    is_amsdu = WMI_DATA_HDR_IS_AMSDU(dhdr);
+                    tid = WMI_DATA_HDR_GET_UP(dhdr);
+                    seq_no = WMI_DATA_HDR_GET_SEQNO(dhdr);
+                    meta_type = WMI_DATA_HDR_GET_META(dhdr);
+                    containsDot11Hdr = WMI_DATA_HDR_GET_DOT11(dhdr);
+
+                    wmi_data_hdr_remove(ar->arWmi, skb);
+
+                    switch (meta_type) {
+                        case WMI_META_VERSION_1:
+                            {
+                                WMI_RX_META_V1 *pMeta = (WMI_RX_META_V1 *)A_NETBUF_DATA(skb);
+                                A_PRINTF("META %d %d %d %d %x\n", pMeta->status, pMeta->rix, pMeta->rssi, pMeta->channel, pMeta->flags);
+                                A_NETBUF_PULL((void*)skb, sizeof(WMI_RX_META_V1));
+                                break;
+                            }
+#ifdef CONFIG_CHECKSUM_OFFLOAD
+                        case WMI_META_VERSION_2:
+                            {
+                                WMI_RX_META_V2 *pMeta = (WMI_RX_META_V2 *)A_NETBUF_DATA(skb);
+                                if(pMeta->csumFlags & 0x1){
+                                    skb->ip_summed=CHECKSUM_COMPLETE;
+                                    skb->csum=(pMeta->csum);
+                                }
+                                A_NETBUF_PULL((void*)skb, sizeof(WMI_RX_META_V2));
+                                break;
+                            }
+#endif
+                        default:
+                            break;
+                    }
+
+                    A_ASSERT(status == A_OK);
+
+                    /* NWF: print the 802.11 hdr bytes */
+                    if(containsDot11Hdr) {
+                        status = wmi_dot11_hdr_remove(ar->arWmi,skb);
+                    } else if(!is_amsdu && !is_acl_data_frame) {
+                        status = wmi_dot3_2_dix(skb);
+                    }
+
+                    if (status != A_OK) {
+                        /* Drop frames that could not be processed (lack of memory, etc.) */
+                        A_NETBUF_FREE(skb);
+                        goto rx_done;
+                    }
+
+                    if (is_acl_data_frame) {
+                        A_NETBUF_PUSH(skb, sizeof(int));
+                        *((short *)A_NETBUF_DATA(skb)) = WMI_ACL_DATA_EVENTID;
+	                /* send the data packet to PAL driver */
+			if(ar6k_pal_config_g.fpar6k_pal_recv_pkt) {
+				if((*ar6k_pal_config_g.fpar6k_pal_recv_pkt)(ar->hcipal_info, skb) == TRUE)
+					goto rx_done;
+			}
+                    }
+
+                    if ((ar->arNetDev->flags & IFF_UP) == IFF_UP) {
+                        if (ar->arNetworkType == AP_NETWORK) {
+                            struct sk_buff *skb1 = NULL;
+                            ATH_MAC_HDR *datap;
+
+                            datap = (ATH_MAC_HDR *)A_NETBUF_DATA(skb);
+                            if (IEEE80211_IS_MULTICAST(datap->dstMac)) {
+                                /* Bcast/Mcast frames should be sent to the OS
+                                 * stack as well as on the air.
+                                 */
+                                skb1 = skb_copy(skb,GFP_ATOMIC);
+                            } else {
+                                /* Search for a connected STA with dstMac as
+                                 * the Mac address. If found send the frame to
+                                 * it on the air else send the frame up the
+                                 * stack
+                                 */
+                                sta_t *conn = NULL;
+                                conn = ieee80211_find_conn(ar, datap->dstMac);
+
+                                if (conn && ar->intra_bss) {
+                                    skb1 = skb;
+                                    skb = NULL;
+                                } else if(conn && !ar->intra_bss) {
+                                    A_NETBUF_FREE(skb);
+                                    skb = NULL;
+                                }
+                            }
+                            if (skb1) {
+                                ar6000_data_tx(skb1, ar->arNetDev);
+                            }
+                        }
+                    }
+#ifdef ATH_AR6K_11N_SUPPORT
+                    aggr_process_recv_frm(ar->aggr_cntxt, tid, seq_no, is_amsdu, (void **)&skb);
+#endif
+                    ar6000_deliver_frames_to_nw_stack((void *) ar->arNetDev, (void *)skb);
+                }
+            }
+    } else {
+        if (EPPING_ALIGNMENT_PAD > 0) {
+            A_NETBUF_PULL(skb, EPPING_ALIGNMENT_PAD);
+        }
+        ar6000_deliver_frames_to_nw_stack((void *)ar->arNetDev, (void *)skb);
+    }
+
+rx_done:
+
+    return;
+}
+
+static void
+ar6000_deliver_frames_to_nw_stack(void *dev, void *osbuf)
+{
+    struct sk_buff *skb = (struct sk_buff *)osbuf;
+
+    if(skb) {
+        skb->dev = dev;
+        if ((skb->dev->flags & IFF_UP) == IFF_UP) {
+#ifdef CONFIG_PM 
+            ar6000_check_wow_status((AR_SOFTC_T *)ar6k_priv(dev), skb, FALSE);   
+#endif /* CONFIG_PM */
+            skb->protocol = eth_type_trans(skb, skb->dev);
+        /*
+         * If this routine is called on a ISR (Hard IRQ) or DSR (Soft IRQ)
+         * or tasklet use the netif_rx to deliver the packet to the stack
+         * netif_rx will queue the packet onto the receive queue and mark
+         * the softirq thread has a pending action to complete. Kernel will 
+         * schedule the softIrq kernel thread after processing the DSR.
+         *
+         * If this routine is called on a process context, use netif_rx_ni
+         * which will schedle the softIrq kernel thread after queuing the packet.
+         */
+            if (in_interrupt()) {
+                netif_rx(skb);
+            } else {
+                netif_rx_ni(skb);
+            }
+        } else {
+            A_NETBUF_FREE(skb);
+        }
+    }
+}
+
+#if 0
+static void
+ar6000_deliver_frames_to_bt_stack(void *dev, void *osbuf)
+{
+    struct sk_buff *skb = (struct sk_buff *)osbuf;
+
+    if(skb) {
+        skb->dev = dev;
+        if ((skb->dev->flags & IFF_UP) == IFF_UP) {
+            skb->protocol = htons(ETH_P_CONTROL);
+            netif_rx(skb);
+        } else {
+            A_NETBUF_FREE(skb);
+        }
+    }
+}
+#endif
+
+static void
+ar6000_rx_refill(void *Context, HTC_ENDPOINT_ID Endpoint)
+{
+    AR_SOFTC_T  *ar = (AR_SOFTC_T *)Context;
+    void        *osBuf;
+    int         RxBuffers;
+    int         buffersToRefill;
+    HTC_PACKET  *pPacket;
+    HTC_PACKET_QUEUE queue;
+
+    buffersToRefill = (int)AR6000_MAX_RX_BUFFERS -
+                                    HTCGetNumRecvBuffers(ar->arHtcTarget, Endpoint);
+
+    if (buffersToRefill <= 0) {
+            /* fast return, nothing to fill */
+        return;
+    }
+
+    INIT_HTC_PACKET_QUEUE(&queue);
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_RX,("ar6000_rx_refill: providing htc with %d buffers at eid=%d\n",
+                    buffersToRefill, Endpoint));
+
+    for (RxBuffers = 0; RxBuffers < buffersToRefill; RxBuffers++) {
+        osBuf = A_NETBUF_ALLOC(AR6000_BUFFER_SIZE);
+        if (NULL == osBuf) {
+            break;
+        }
+            /* the HTC packet wrapper is at the head of the reserved area
+             * in the skb */
+        pPacket = (HTC_PACKET *)(A_NETBUF_HEAD(osBuf));
+            /* set re-fill info */
+        SET_HTC_PACKET_INFO_RX_REFILL(pPacket,osBuf,A_NETBUF_DATA(osBuf),AR6000_BUFFER_SIZE,Endpoint);
+            /* add to queue */
+        HTC_PACKET_ENQUEUE(&queue,pPacket);
+    }
+
+    if (!HTC_QUEUE_EMPTY(&queue)) {
+            /* add packets */
+        HTCAddReceivePktMultiple(ar->arHtcTarget, &queue);
+    }
+
+}
+
+  /* clean up our amsdu buffer list */
+static void ar6000_cleanup_amsdu_rxbufs(AR_SOFTC_T *ar)
+{
+    HTC_PACKET  *pPacket;
+    void        *osBuf;
+
+        /* empty AMSDU buffer queue and free OS bufs */
+    while (TRUE) {
+
+        AR6000_SPIN_LOCK(&ar->arLock, 0);
+        pPacket = HTC_PACKET_DEQUEUE(&ar->amsdu_rx_buffer_queue);
+        AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+
+        if (NULL == pPacket) {
+            break;
+        }
+
+        osBuf = pPacket->pPktContext;
+        if (NULL == osBuf) {
+            A_ASSERT(FALSE);
+            break;
+        }
+
+        A_NETBUF_FREE(osBuf);
+    }
+
+}
+
+
+    /* refill the amsdu buffer list */
+static void ar6000_refill_amsdu_rxbufs(AR_SOFTC_T *ar, int Count)
+{
+    HTC_PACKET  *pPacket;
+    void        *osBuf;
+
+    while (Count > 0) {
+        osBuf = A_NETBUF_ALLOC(AR6000_AMSDU_BUFFER_SIZE);
+        if (NULL == osBuf) {
+            break;
+        }
+            /* the HTC packet wrapper is at the head of the reserved area
+             * in the skb */
+        pPacket = (HTC_PACKET *)(A_NETBUF_HEAD(osBuf));
+            /* set re-fill info */
+        SET_HTC_PACKET_INFO_RX_REFILL(pPacket,osBuf,A_NETBUF_DATA(osBuf),AR6000_AMSDU_BUFFER_SIZE,0);
+
+        AR6000_SPIN_LOCK(&ar->arLock, 0);
+            /* put it in the list */
+        HTC_PACKET_ENQUEUE(&ar->amsdu_rx_buffer_queue,pPacket);
+        AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+        Count--;
+    }
+
+}
+
+    /* callback to allocate a large receive buffer for a pending packet.  This function is called when
+     * an HTC packet arrives whose length exceeds a threshold value
+     *
+     * We use a pre-allocated list of buffers of maximum AMSDU size (4K).  Under linux it is more optimal to
+     * keep the allocation size the same to optimize cached-slab allocations.
+     *
+     * */
+static HTC_PACKET *ar6000_alloc_amsdu_rxbuf(void *Context, HTC_ENDPOINT_ID Endpoint, int Length)
+{
+    HTC_PACKET  *pPacket = NULL;
+    AR_SOFTC_T  *ar = (AR_SOFTC_T *)Context;
+    int         refillCount = 0;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_RX,("ar6000_alloc_amsdu_rxbuf: eid=%d, Length:%d\n",Endpoint,Length));
+
+    do {
+
+        if (Length <= AR6000_BUFFER_SIZE) {
+                /* shouldn't be getting called on normal sized packets */
+            A_ASSERT(FALSE);
+            break;
+        }
+
+        if (Length > AR6000_AMSDU_BUFFER_SIZE) {
+            A_ASSERT(FALSE);
+            break;
+        }
+
+        AR6000_SPIN_LOCK(&ar->arLock, 0);
+            /* allocate a packet from the list */
+        pPacket = HTC_PACKET_DEQUEUE(&ar->amsdu_rx_buffer_queue);
+            /* see if we need to refill again */
+        refillCount = AR6000_MAX_AMSDU_RX_BUFFERS - HTC_PACKET_QUEUE_DEPTH(&ar->amsdu_rx_buffer_queue);
+        AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+
+        if (NULL == pPacket) {
+            break;
+        }
+            /* set actual endpoint ID */
+        pPacket->Endpoint = Endpoint;
+
+    } while (FALSE);
+
+    if (refillCount >= AR6000_AMSDU_REFILL_THRESHOLD) {
+        ar6000_refill_amsdu_rxbufs(ar,refillCount);
+    }
+
+    return pPacket;
+}
+
+static void	
+ar6000_set_multicast_list(struct net_device *dev)
+{
+    AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("ar6000: Multicast filter not supported\n"));
+}
+
+static struct net_device_stats *
+ar6000_get_stats(struct net_device *dev)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    return &ar->arNetStats;
+}
+
+static struct iw_statistics *
+ar6000_get_iwstats(struct net_device * dev)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    TARGET_STATS *pStats = &ar->arTargetStats;
+    struct iw_statistics * pIwStats = &ar->arIwStats;
+    int rtnllocked;
+
+    if (ar->bIsDestroyProgress || ar->arWmiReady == FALSE || ar->arWlanState == WLAN_DISABLED)
+    {
+        pIwStats->status = 0;
+        pIwStats->qual.qual = 0;
+        pIwStats->qual.level =0;
+        pIwStats->qual.noise = 0;
+        pIwStats->discard.code =0;
+        pIwStats->discard.retries=0;
+        pIwStats->miss.beacon =0;
+        return pIwStats;
+    }
+
+    /*
+     * The in_atomic function is used to determine if the scheduling is
+     * allowed in the current context or not. This was introduced in 2.6
+     * From what I have read on the differences between 2.4 and 2.6, the
+     * 2.4 kernel did not support preemption and so this check might not
+     * be required for 2.4 kernels.
+     */
+    if (in_atomic())
+    {
+        wmi_get_stats_cmd(ar->arWmi);
+
+        pIwStats->status = 1 ;
+        pIwStats->qual.qual = pStats->cs_aveBeacon_rssi - 161;
+        pIwStats->qual.level =pStats->cs_aveBeacon_rssi; /* noise is -95 dBm */
+        pIwStats->qual.noise = pStats->noise_floor_calibation;
+        pIwStats->discard.code = pStats->rx_decrypt_err;
+        pIwStats->discard.retries = pStats->tx_retry_cnt;
+        pIwStats->miss.beacon = pStats->cs_bmiss_cnt;
+        return pIwStats;
+    }
+
+    dev_hold(dev);   
+    rtnllocked = rtnl_is_locked();
+    if (rtnllocked) {
+        rtnl_unlock();
+    }
+    pIwStats->status = 0;
+
+    if (down_interruptible(&ar->arSem)) {
+        goto err_exit;
+    }
+    
+    do {
+
+        if (ar->bIsDestroyProgress || ar->arWlanState == WLAN_DISABLED) {
+            break;
+        }
+    
+        ar->statsUpdatePending = TRUE;
+    
+        if(wmi_get_stats_cmd(ar->arWmi) != A_OK) {
+            break;
+        }
+    
+        wait_event_interruptible_timeout(arEvent, ar->statsUpdatePending == FALSE, wmitimeout * HZ);
+        if (signal_pending(current)) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("ar6000 : WMI get stats timeout \n"));
+            break;
+        }
+        pIwStats->status = 1 ;
+        pIwStats->qual.qual = pStats->cs_aveBeacon_rssi - 161;
+        pIwStats->qual.level =pStats->cs_aveBeacon_rssi;  /* noise is -95 dBm */
+        pIwStats->qual.noise = pStats->noise_floor_calibation;
+        pIwStats->discard.code = pStats->rx_decrypt_err;
+        pIwStats->discard.retries = pStats->tx_retry_cnt;
+        pIwStats->miss.beacon = pStats->cs_bmiss_cnt;
+    } while (0);
+    up(&ar->arSem);
+
+err_exit:
+    if (rtnllocked) {
+        rtnl_lock();
+    }
+    dev_put(dev);
+    return pIwStats;
+}
+
+void
+ar6000_ready_event(void *devt, A_UINT8 *datap, A_UINT8 phyCap, A_UINT32 sw_ver, A_UINT32 abi_ver)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)devt;
+    struct net_device *dev = ar->arNetDev;
+
+    A_MEMCPY(dev->dev_addr, datap, AR6000_ETH_ADDR_LEN);
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("mac address = %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n",
+        dev->dev_addr[0], dev->dev_addr[1],
+        dev->dev_addr[2], dev->dev_addr[3],
+        dev->dev_addr[4], dev->dev_addr[5]));
+
+    ar->arPhyCapability = phyCap;
+    ar->arVersion.wlan_ver = sw_ver;
+    ar->arVersion.abi_ver = abi_ver;
+
+    /* Indicate to the waiting thread that the ready event was received */
+    ar->arWmiReady = TRUE;
+    wake_up(&arEvent);
+
+#if WLAN_CONFIG_IGNORE_POWER_SAVE_FAIL_EVENT_DURING_SCAN
+    wmi_pmparams_cmd(ar->arWmi, 0, 1, 0, 0, 1, IGNORE_POWER_SAVE_FAIL_EVENT_DURING_SCAN);
+#endif
+#if WLAN_CONFIG_DONOT_IGNORE_BARKER_IN_ERP
+    wmi_set_lpreamble_cmd(ar->arWmi, 0, WMI_DONOT_IGNORE_BARKER_IN_ERP);
+#endif
+    wmi_set_keepalive_cmd(ar->arWmi, WLAN_CONFIG_KEEP_ALIVE_INTERVAL);
+#if WLAN_CONFIG_DISABLE_11N
+    {
+        WMI_SET_HT_CAP_CMD htCap;
+
+        A_MEMZERO(&htCap, sizeof(WMI_SET_HT_CAP_CMD));
+        htCap.band = 0;
+        wmi_set_ht_cap_cmd(ar->arWmi, &htCap);
+
+        htCap.band = 1;
+        wmi_set_ht_cap_cmd(ar->arWmi, &htCap);
+    }
+#endif /* WLAN_CONFIG_DISABLE_11N */
+
+#ifdef ATH6K_CONFIG_OTA_MODE
+    wmi_powermode_cmd(ar->arWmi, MAX_PERF_POWER);
+#endif
+    wmi_disctimeout_cmd(ar->arWmi, WLAN_CONFIG_DISCONNECT_TIMEOUT);
+}
+
+void
+add_new_sta(AR_SOFTC_T *ar, A_UINT8 *mac, A_UINT16 aid, A_UINT8 *wpaie,
+            A_UINT8 ielen, A_UINT8 keymgmt, A_UINT8 ucipher, A_UINT8 auth)
+{
+    A_UINT8    free_slot=aid-1;
+
+        A_MEMCPY(ar->sta_list[free_slot].mac, mac, ATH_MAC_LEN);
+        A_MEMCPY(ar->sta_list[free_slot].wpa_ie, wpaie, ielen);
+        ar->sta_list[free_slot].aid = aid;
+        ar->sta_list[free_slot].keymgmt = keymgmt;
+        ar->sta_list[free_slot].ucipher = ucipher;
+        ar->sta_list[free_slot].auth = auth;
+        ar->sta_list_index = ar->sta_list_index | (1 << free_slot);
+    ar->arAPStats.sta[free_slot].aid = aid;
+}
+
+void
+ar6000_connect_event(AR_SOFTC_T *ar, A_UINT16 channel, A_UINT8 *bssid,
+                     A_UINT16 listenInterval, A_UINT16 beaconInterval,
+                     NETWORK_TYPE networkType, A_UINT8 beaconIeLen,
+                     A_UINT8 assocReqLen, A_UINT8 assocRespLen,
+                     A_UINT8 *assocInfo)
+{
+    union iwreq_data wrqu;
+    int i, beacon_ie_pos, assoc_resp_ie_pos, assoc_req_ie_pos;
+    static const char *tag1 = "ASSOCINFO(ReqIEs=";
+    static const char *tag2 = "ASSOCRESPIE=";
+    static const char *beaconIetag = "BEACONIE=";
+    char buf[WMI_CONTROL_MSG_MAX_LEN * 2 + strlen(tag1) + 1];
+    char *pos;
+    A_UINT8 key_op_ctrl;
+    unsigned long flags;
+    struct ieee80211req_key *ik;
+    CRYPTO_TYPE keyType = NONE_CRYPT;
+
+    if(ar->arNetworkType & AP_NETWORK) {
+        struct net_device *dev = ar->arNetDev;
+        if(A_MEMCMP(dev->dev_addr, bssid, ATH_MAC_LEN)==0) {
+            ar->arACS = channel;
+            ik = &ar->ap_mode_bkey;
+
+            switch(ar->arAuthMode) {
+            case NONE_AUTH:
+                if(ar->arPairwiseCrypto == WEP_CRYPT) {
+                    ar6000_install_static_wep_keys(ar);
+                }
+#ifdef WAPI_ENABLE
+                else if(ar->arPairwiseCrypto == WAPI_CRYPT) {
+                    ap_set_wapi_key(ar, ik);
+                }
+#endif
+                break;
+            case WPA_PSK_AUTH:
+            case WPA2_PSK_AUTH:
+            case (WPA_PSK_AUTH|WPA2_PSK_AUTH):
+                switch (ik->ik_type) {
+                    case IEEE80211_CIPHER_TKIP:
+                        keyType = TKIP_CRYPT;
+                        break;
+                    case IEEE80211_CIPHER_AES_CCM:
+                        keyType = AES_CRYPT;
+                        break;
+                    default:
+                       goto skip_key;
+                }
+                wmi_addKey_cmd(ar->arWmi, ik->ik_keyix, keyType, GROUP_USAGE,
+                                ik->ik_keylen, (A_UINT8 *)&ik->ik_keyrsc,
+                                ik->ik_keydata, KEY_OP_INIT_VAL, ik->ik_macaddr,
+                                SYNC_BOTH_WMIFLAG);
+
+                break;
+            }
+skip_key:
+            ar->arConnected  = TRUE;
+            return;
+        }
+
+        A_PRINTF("NEW STA %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x \n "
+            " AID=%d \n", bssid[0], bssid[1], bssid[2],
+             bssid[3], bssid[4], bssid[5], channel);
+        switch ((listenInterval>>8)&0xFF) {
+            case OPEN_AUTH:
+                A_PRINTF("AUTH: OPEN\n");
+                break;
+            case SHARED_AUTH:
+                A_PRINTF("AUTH: SHARED\n");
+                break;
+            default:
+                A_PRINTF("AUTH: Unknown\n");
+                break;
+        };
+        switch (listenInterval&0xFF) {
+            case WPA_PSK_AUTH:
+                A_PRINTF("KeyMgmt: WPA-PSK\n");
+                break;
+            case WPA2_PSK_AUTH:
+                A_PRINTF("KeyMgmt: WPA2-PSK\n");
+                break;
+            default:
+                A_PRINTF("KeyMgmt: NONE\n");
+                break;
+        };
+        switch (beaconInterval) {
+            case AES_CRYPT:
+                A_PRINTF("Cipher: AES\n");
+                break;
+            case TKIP_CRYPT:
+                A_PRINTF("Cipher: TKIP\n");
+                break;
+            case WEP_CRYPT:
+                A_PRINTF("Cipher: WEP\n");
+                break;
+#ifdef WAPI_ENABLE
+            case WAPI_CRYPT:
+                A_PRINTF("Cipher: WAPI\n");
+                break;
+#endif
+            default:
+                A_PRINTF("Cipher: NONE\n");
+                break;
+        };
+
+        add_new_sta(ar, bssid, channel /*aid*/,
+            assocInfo /* WPA IE */, assocRespLen /* IE len */,
+            listenInterval&0xFF /* Keymgmt */, beaconInterval /* cipher */,
+            (listenInterval>>8)&0xFF /* auth alg */);
+
+        /* Send event to application */
+        A_MEMZERO(&wrqu, sizeof(wrqu));
+        A_MEMCPY(wrqu.addr.sa_data, bssid, ATH_MAC_LEN);
+        wireless_send_event(ar->arNetDev, IWEVREGISTERED, &wrqu, NULL);
+        /* In case the queue is stopped when we switch modes, this will
+         * wake it up
+         */
+        netif_wake_queue(ar->arNetDev);
+        return;
+    }
+
+#ifdef ATH6K_CONFIG_CFG80211
+    ar6k_cfg80211_connect_event(ar, channel, bssid,
+                                listenInterval, beaconInterval,
+                                networkType, beaconIeLen,
+                                assocReqLen, assocRespLen,
+                                assocInfo);
+#endif /* ATH6K_CONFIG_CFG80211 */
+
+    A_MEMCPY(ar->arBssid, bssid, sizeof(ar->arBssid));
+    ar->arBssChannel = channel;
+
+    A_PRINTF("AR6000 connected event on freq %d ", channel);
+    A_PRINTF("with bssid %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x "
+            " listenInterval=%d, beaconInterval = %d, beaconIeLen = %d assocReqLen=%d"
+            " assocRespLen =%d\n",
+             bssid[0], bssid[1], bssid[2],
+             bssid[3], bssid[4], bssid[5],
+             listenInterval, beaconInterval,
+             beaconIeLen, assocReqLen, assocRespLen);
+    if (networkType & ADHOC_NETWORK) {
+        if (networkType & ADHOC_CREATOR) {
+            A_PRINTF("Network: Adhoc (Creator)\n");
+        } else {
+            A_PRINTF("Network: Adhoc (Joiner)\n");
+        }
+    } else {
+        A_PRINTF("Network: Infrastructure\n");
+    }
+
+    if ((ar->arNetworkType == INFRA_NETWORK)) {
+        wmi_listeninterval_cmd(ar->arWmi, ar->arListenIntervalT, ar->arListenIntervalB);
+    }
+
+    if (beaconIeLen && (sizeof(buf) > (9 + beaconIeLen * 2))) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("\nBeaconIEs= "));
+
+        beacon_ie_pos = 0;
+        A_MEMZERO(buf, sizeof(buf));
+        sprintf(buf, "%s", beaconIetag);
+        pos = buf + 9;
+        for (i = beacon_ie_pos; i < beacon_ie_pos + beaconIeLen; i++) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("%2.2x ", assocInfo[i]));
+            sprintf(pos, "%2.2x", assocInfo[i]);
+            pos += 2;
+        }
+        AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("\n"));
+
+        A_MEMZERO(&wrqu, sizeof(wrqu));
+        wrqu.data.length = strlen(buf);
+        wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf);
+    }
+
+    if (assocRespLen && (sizeof(buf) > (12 + (assocRespLen * 2))))
+    {
+        assoc_resp_ie_pos = beaconIeLen + assocReqLen +
+                            sizeof(A_UINT16)  +  /* capinfo*/
+                            sizeof(A_UINT16)  +  /* status Code */
+                            sizeof(A_UINT16)  ;  /* associd */
+        A_MEMZERO(buf, sizeof(buf));
+        sprintf(buf, "%s", tag2);
+        pos = buf + 12;
+        AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("\nAssocRespIEs= "));
+        /*
+         * The Association Response Frame w.o. the WLAN header is delivered to
+         * the host, so skip over to the IEs
+         */
+        for (i = assoc_resp_ie_pos; i < assoc_resp_ie_pos + assocRespLen - 6; i++)
+        {
+            AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("%2.2x ", assocInfo[i]));
+            sprintf(pos, "%2.2x", assocInfo[i]);
+            pos += 2;
+        }
+        AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("\n"));
+
+        A_MEMZERO(&wrqu, sizeof(wrqu));
+        wrqu.data.length = strlen(buf);
+        wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf);
+    }
+
+    if (assocReqLen && (sizeof(buf) > (17 + (assocReqLen * 2)))) {
+        /*
+         * assoc Request includes capability and listen interval. Skip these.
+         */
+        assoc_req_ie_pos =  beaconIeLen +
+                            sizeof(A_UINT16)  +  /* capinfo*/
+                            sizeof(A_UINT16);    /* listen interval */
+
+        A_MEMZERO(buf, sizeof(buf));
+        sprintf(buf, "%s", tag1);
+        pos = buf + 17;
+        AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("AssocReqIEs= "));
+        for (i = assoc_req_ie_pos; i < assoc_req_ie_pos + assocReqLen - 4; i++) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("%2.2x ", assocInfo[i]));
+            sprintf(pos, "%2.2x", assocInfo[i]);
+            pos += 2;
+        }
+        AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("\n"));
+
+        A_MEMZERO(&wrqu, sizeof(wrqu));
+        wrqu.data.length = strlen(buf);
+        wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf);
+    }
+
+#ifdef USER_KEYS
+    if (ar->user_savedkeys_stat == USER_SAVEDKEYS_STAT_RUN &&
+        ar->user_saved_keys.keyOk == TRUE)
+    {
+        key_op_ctrl = KEY_OP_VALID_MASK & ~KEY_OP_INIT_TSC;
+
+        if (ar->user_key_ctrl & AR6000_USER_SETKEYS_RSC_UNCHANGED) {
+            key_op_ctrl &= ~KEY_OP_INIT_RSC;
+        } else {
+            key_op_ctrl |= KEY_OP_INIT_RSC;
+        }
+        ar6000_reinstall_keys(ar, key_op_ctrl);
+    }
+#endif /* USER_KEYS */
+
+    netif_wake_queue(ar->arNetDev);
+
+    /* For CFG80211 the key configuration and the default key comes in after connect so no point in plumbing invalid keys */
+#ifndef ATH6K_CONFIG_CFG80211
+    if ((networkType & ADHOC_NETWORK)      &&
+        (OPEN_AUTH == ar->arDot11AuthMode) &&
+        (NONE_AUTH == ar->arAuthMode)      &&
+        (WEP_CRYPT == ar->arPairwiseCrypto))
+    {
+        if (!ar->arConnected) {
+            wmi_addKey_cmd(ar->arWmi,
+                           ar->arDefTxKeyIndex,
+                           WEP_CRYPT,
+                           GROUP_USAGE | TX_USAGE,
+                           ar->arWepKeyList[ar->arDefTxKeyIndex].arKeyLen,
+                           NULL,
+                           ar->arWepKeyList[ar->arDefTxKeyIndex].arKey, KEY_OP_INIT_VAL, NULL,
+                           NO_SYNC_WMIFLAG);
+        }
+    }
+#endif /* ATH6K_CONFIG_CFG80211 */
+
+    /* Update connect & link status atomically */
+    spin_lock_irqsave(&ar->arLock, flags);
+    ar->arConnected  = TRUE;
+    ar->arConnectPending = FALSE;
+    netif_carrier_on(ar->arNetDev);
+    spin_unlock_irqrestore(&ar->arLock, flags);
+    /* reset the rx aggr state */
+    aggr_reset_state(ar->aggr_cntxt);
+    reconnect_flag = 0;
+
+    A_MEMZERO(&wrqu, sizeof(wrqu));
+    A_MEMCPY(wrqu.addr.sa_data, bssid, IEEE80211_ADDR_LEN);
+    wrqu.addr.sa_family = ARPHRD_ETHER;
+    wireless_send_event(ar->arNetDev, SIOCGIWAP, &wrqu, NULL);
+    if ((ar->arNetworkType == ADHOC_NETWORK) && ar->arIbssPsEnable) {
+        A_MEMZERO(ar->arNodeMap, sizeof(ar->arNodeMap));
+        ar->arNodeNum = 0;
+        ar->arNexEpId = ENDPOINT_2;
+    }
+   if (!ar->arUserBssFilter) {
+        wmi_bssfilter_cmd(ar->arWmi, NONE_BSS_FILTER, 0);
+   }
+
+}
+
+void ar6000_set_numdataendpts(AR_SOFTC_T *ar, A_UINT32 num)
+{
+    A_ASSERT(num <= (HTC_MAILBOX_NUM_MAX - 1));
+    ar->arNumDataEndPts = num;
+}
+
+void
+sta_cleanup(AR_SOFTC_T *ar, A_UINT8 i)
+{
+    struct sk_buff *skb;
+
+    /* empty the queued pkts in the PS queue if any */
+    A_MUTEX_LOCK(&ar->sta_list[i].psqLock);
+    while (!A_NETBUF_QUEUE_EMPTY(&ar->sta_list[i].psq)) {
+        skb = A_NETBUF_DEQUEUE(&ar->sta_list[i].psq);
+        A_NETBUF_FREE(skb);
+    }
+    A_MUTEX_UNLOCK(&ar->sta_list[i].psqLock);
+
+    /* Zero out the state fields */
+    A_MEMZERO(&ar->arAPStats.sta[ar->sta_list[i].aid-1], sizeof(WMI_PER_STA_STAT));
+    A_MEMZERO(&ar->sta_list[i].mac, ATH_MAC_LEN);
+    A_MEMZERO(&ar->sta_list[i].wpa_ie, IEEE80211_MAX_IE);
+    ar->sta_list[i].aid = 0;
+    ar->sta_list[i].flags = 0;
+
+    ar->sta_list_index = ar->sta_list_index & ~(1 << i);
+
+}
+
+A_UINT8
+remove_sta(AR_SOFTC_T *ar, A_UINT8 *mac, A_UINT16 reason)
+{
+    A_UINT8 i, removed=0;
+
+    if(IS_MAC_NULL(mac)) {
+        return removed;
+    }
+
+    if(IS_MAC_BCAST(mac)) {
+        A_PRINTF("DEL ALL STA\n");
+        for(i=0; i < AP_MAX_NUM_STA; i++) {
+            if(!IS_MAC_NULL(ar->sta_list[i].mac)) {
+                sta_cleanup(ar, i);
+                removed = 1;
+            }
+        }
+    } else {
+        for(i=0; i < AP_MAX_NUM_STA; i++) {
+            if(A_MEMCMP(ar->sta_list[i].mac, mac, ATH_MAC_LEN)==0) {
+                A_PRINTF("DEL STA %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x "
+                " aid=%d REASON=%d\n", mac[0], mac[1], mac[2],
+                 mac[3], mac[4], mac[5], ar->sta_list[i].aid, reason);
+
+                sta_cleanup(ar, i);
+                removed = 1;
+                break;
+            }
+        }
+    }
+    return removed;
+}
+
+void
+ar6000_disconnect_event(AR_SOFTC_T *ar, A_UINT8 reason, A_UINT8 *bssid,
+                        A_UINT8 assocRespLen, A_UINT8 *assocInfo, A_UINT16 protocolReasonStatus)
+{
+    A_UINT8 i;
+    unsigned long flags;
+    union iwreq_data wrqu;
+
+    if(ar->arNetworkType & AP_NETWORK) {
+        union iwreq_data wrqu;
+        struct sk_buff *skb;
+
+        if(!remove_sta(ar, bssid, protocolReasonStatus)) {
+            return;
+        }
+
+        /* If there are no more associated STAs, empty the mcast PS q */
+        if (ar->sta_list_index == 0) {
+            A_MUTEX_LOCK(&ar->mcastpsqLock);
+            while (!A_NETBUF_QUEUE_EMPTY(&ar->mcastpsq)) {
+                skb = A_NETBUF_DEQUEUE(&ar->mcastpsq);
+                A_NETBUF_FREE(skb);
+            }
+            A_MUTEX_UNLOCK(&ar->mcastpsqLock);
+
+            /* Clear the LSB of the BitMapCtl field of the TIM IE */
+            if (ar->arWmiReady) {
+                wmi_set_pvb_cmd(ar->arWmi, MCAST_AID, 0);
+            }
+        }
+
+        if(!IS_MAC_BCAST(bssid)) {
+            /* Send event to application */
+            A_MEMZERO(&wrqu, sizeof(wrqu));
+            A_MEMCPY(wrqu.addr.sa_data, bssid, ATH_MAC_LEN);
+            wireless_send_event(ar->arNetDev, IWEVEXPIRED, &wrqu, NULL);
+        }
+        return;
+    }
+
+#ifdef ATH6K_CONFIG_CFG80211
+    ar6k_cfg80211_disconnect_event(ar, reason, bssid,
+                                   assocRespLen, assocInfo,
+                                   protocolReasonStatus);
+#endif /* ATH6K_CONFIG_CFG80211 */
+
+    /* Send disconnect event to supplicant */
+    A_MEMZERO(&wrqu, sizeof(wrqu));
+    wrqu.addr.sa_family = ARPHRD_ETHER;
+    wireless_send_event(ar->arNetDev, SIOCGIWAP, &wrqu, NULL);
+
+    /* it is necessary to clear the host-side rx aggregation state */
+    aggr_reset_state(ar->aggr_cntxt);
+
+    A_UNTIMEOUT(&ar->disconnect_timer);
+
+    A_PRINTF("AR6000 disconnected");
+    if (bssid[0] || bssid[1] || bssid[2] || bssid[3] || bssid[4] || bssid[5]) {
+        A_PRINTF(" from %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x ",
+                 bssid[0], bssid[1], bssid[2], bssid[3], bssid[4], bssid[5]);
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("\nDisconnect Reason is %d", reason));
+    AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("\nProtocol Reason/Status Code is %d", protocolReasonStatus));
+    AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("\nAssocResp Frame = %s",
+                    assocRespLen ? " " : "NULL"));
+    for (i = 0; i < assocRespLen; i++) {
+        if (!(i % 0x10)) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("\n"));
+        }
+        AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("%2.2x ", assocInfo[i]));
+    }
+    AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("\n"));
+    /*
+     * If the event is due to disconnect cmd from the host, only they the target
+     * would stop trying to connect. Under any other condition, target would
+     * keep trying to connect.
+     *
+     */
+    if( reason == DISCONNECT_CMD)
+    {
+        ar->arConnectPending = FALSE;
+        if ((!ar->arUserBssFilter) && (ar->arWmiReady)) {
+            wmi_bssfilter_cmd(ar->arWmi, NONE_BSS_FILTER, 0);
+        }
+    } else {
+        ar->arConnectPending = TRUE;
+        if (((reason == ASSOC_FAILED) && (protocolReasonStatus == 0x11)) ||
+            ((reason == ASSOC_FAILED) && (protocolReasonStatus == 0x0) && (reconnect_flag == 1))) {
+            ar->arConnected = TRUE;
+            return;
+        }
+    }
+
+    if ((reason == NO_NETWORK_AVAIL) && (ar->arWmiReady)) 
+    {
+        bss_t *pWmiSsidnode = NULL;
+
+        /* remove the current associated bssid node */
+        wmi_free_node (ar->arWmi, bssid);
+
+        /*
+         * In case any other same SSID nodes are present
+         * remove it, since those nodes also not available now
+         */
+        do
+        {
+            /*
+             * Find the nodes based on SSID and remove it
+             * NOTE :: This case will not work out for Hidden-SSID
+             */
+            pWmiSsidnode = wmi_find_Ssidnode (ar->arWmi, ar->arSsid, ar->arSsidLen, FALSE, TRUE);
+
+            if (pWmiSsidnode)
+            {
+                wmi_free_node (ar->arWmi, pWmiSsidnode->ni_macaddr);
+            }
+
+        } while (pWmiSsidnode);
+    }
+
+    /* Update connect & link status atomically */
+    spin_lock_irqsave(&ar->arLock, flags);
+    ar->arConnected = FALSE;
+    netif_carrier_off(ar->arNetDev);
+    spin_unlock_irqrestore(&ar->arLock, flags);
+
+    if( (reason != CSERV_DISCONNECT) || (reconnect_flag != 1) ) {
+        reconnect_flag = 0;
+    }
+
+#ifdef USER_KEYS
+    if (reason != CSERV_DISCONNECT)
+    {
+        ar->user_savedkeys_stat = USER_SAVEDKEYS_STAT_INIT;
+        ar->user_key_ctrl      = 0;
+    }
+#endif /* USER_KEYS */
+
+    netif_stop_queue(ar->arNetDev);
+    A_MEMZERO(ar->arBssid, sizeof(ar->arBssid));
+    ar->arBssChannel = 0;
+    ar->arBeaconInterval = 0;
+
+    ar6000_TxDataCleanup(ar);
+}
+
+void
+ar6000_regDomain_event(AR_SOFTC_T *ar, A_UINT32 regCode)
+{
+    A_PRINTF("AR6000 Reg Code = 0x%x\n", regCode);
+    ar->arRegCode = regCode;
+}
+
+#ifdef ATH_AR6K_11N_SUPPORT
+void
+ar6000_aggr_rcv_addba_req_evt(AR_SOFTC_T *ar, WMI_ADDBA_REQ_EVENT *evt)
+{
+    if(evt->status == 0) {
+        aggr_recv_addba_req_evt(ar->aggr_cntxt, evt->tid, evt->st_seq_no, evt->win_sz);
+    }
+}
+
+void
+ar6000_aggr_rcv_addba_resp_evt(AR_SOFTC_T *ar, WMI_ADDBA_RESP_EVENT *evt)
+{
+    A_PRINTF("ADDBA RESP. tid %d status %d, sz %d\n", evt->tid, evt->status, evt->amsdu_sz);
+    if(evt->status == 0) {
+    }
+}
+
+void
+ar6000_aggr_rcv_delba_req_evt(AR_SOFTC_T *ar, WMI_DELBA_EVENT *evt)
+{
+    aggr_recv_delba_req_evt(ar->aggr_cntxt, evt->tid);
+}
+#endif
+
+void register_pal_cb(ar6k_pal_config_t *palConfig_p)
+{
+  ar6k_pal_config_g = *palConfig_p;
+}
+
+void
+ar6000_hci_event_rcv_evt(struct ar6_softc *ar, WMI_HCI_EVENT *cmd)
+{
+    void *osbuf = NULL;
+    A_INT8 i;
+    A_UINT8 size, *buf;
+    A_STATUS ret = A_OK;
+
+    size = cmd->evt_buf_sz + 4;
+    osbuf = A_NETBUF_ALLOC(size);
+    if (osbuf == NULL) {
+       ret = A_NO_MEMORY;
+       A_PRINTF("Error in allocating netbuf \n");
+       return;
+    }
+
+    A_NETBUF_PUT(osbuf, size);
+    buf = (A_UINT8 *)A_NETBUF_DATA(osbuf);
+    /* First 2-bytes carry HCI event/ACL data type
+     * the next 2 are free
+     */
+    *((short *)buf) = WMI_HCI_EVENT_EVENTID;
+    buf += sizeof(int);
+    A_MEMCPY(buf, cmd->buf, cmd->evt_buf_sz);
+
+    if(ar6k_pal_config_g.fpar6k_pal_recv_pkt)
+    {
+      /* pass the cmd packet to PAL driver */
+      if((*ar6k_pal_config_g.fpar6k_pal_recv_pkt)(ar->hcipal_info, osbuf) == TRUE)
+        return;
+    }
+    ar6000_deliver_frames_to_nw_stack(ar->arNetDev, osbuf);
+    if(loghci) {
+        A_PRINTF_LOG("HCI Event From PAL <-- \n");
+        for(i = 0; i < cmd->evt_buf_sz; i++) {
+           A_PRINTF_LOG("0x%02x ", cmd->buf[i]);
+           if((i % 10) == 0) {
+               A_PRINTF_LOG("\n");
+           }
+        }
+        A_PRINTF_LOG("\n");
+        A_PRINTF_LOG("==================================\n");
+    }
+}
+
+void
+ar6000_neighborReport_event(AR_SOFTC_T *ar, int numAps, WMI_NEIGHBOR_INFO *info)
+{
+#if WIRELESS_EXT >= 18
+    struct iw_pmkid_cand *pmkcand;
+#else /* WIRELESS_EXT >= 18 */
+    static const char *tag = "PRE-AUTH";
+    char buf[128];
+#endif /* WIRELESS_EXT >= 18 */
+
+    union iwreq_data wrqu;
+    int i;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_SCAN,("AR6000 Neighbor Report Event\n"));
+    for (i=0; i < numAps; info++, i++) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_SCAN,("bssid %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x ",
+            info->bssid[0], info->bssid[1], info->bssid[2],
+            info->bssid[3], info->bssid[4], info->bssid[5]));
+        if (info->bssFlags & WMI_PREAUTH_CAPABLE_BSS) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_SCAN,("preauth-cap"));
+        }
+        if (info->bssFlags & WMI_PMKID_VALID_BSS) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_SCAN,(" pmkid-valid\n"));
+            continue;           /* we skip bss if the pmkid is already valid */
+        }
+        AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_SCAN,("\n"));
+        A_MEMZERO(&wrqu, sizeof(wrqu));
+#if WIRELESS_EXT >= 18
+        pmkcand = A_MALLOC_NOWAIT(sizeof(struct iw_pmkid_cand));
+        A_MEMZERO(pmkcand, sizeof(struct iw_pmkid_cand));
+        pmkcand->index = i;
+        pmkcand->flags = info->bssFlags;
+        A_MEMCPY(pmkcand->bssid.sa_data, info->bssid, ATH_MAC_LEN);
+        wrqu.data.length = sizeof(struct iw_pmkid_cand);
+        wireless_send_event(ar->arNetDev, IWEVPMKIDCAND, &wrqu, (char *)pmkcand);
+        A_FREE(pmkcand);
+#else /* WIRELESS_EXT >= 18 */
+        snprintf(buf, sizeof(buf), "%s%2.2x%2.2x%2.2x%2.2x%2.2x%2.2x%2.2x%2.2x",
+                 tag,
+                 info->bssid[0], info->bssid[1], info->bssid[2],
+                 info->bssid[3], info->bssid[4], info->bssid[5],
+                 i, info->bssFlags);
+        wrqu.data.length = strlen(buf);
+        wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf);
+#endif /* WIRELESS_EXT >= 18 */
+    }
+}
+
+void
+ar6000_tkip_micerr_event(AR_SOFTC_T *ar, A_UINT8 keyid, A_BOOL ismcast)
+{
+    static const char *tag = "MLME-MICHAELMICFAILURE.indication";
+    char buf[128];
+    union iwreq_data wrqu;
+
+    /*
+     * For AP case, keyid will have aid of STA which sent pkt with
+     * MIC error. Use this aid to get MAC & send it to hostapd.
+     */
+    if (ar->arNetworkType == AP_NETWORK) {
+        sta_t *s = ieee80211_find_conn_for_aid(ar, (keyid >> 2));
+        if(!s){
+            A_PRINTF("AP TKIP MIC error received from Invalid aid / STA not found =%d\n", keyid);
+            return;
+        }
+        A_PRINTF("AP TKIP MIC error received from aid=%d\n", keyid);
+        snprintf(buf,sizeof(buf), "%s addr=%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x",
+            tag, s->mac[0],s->mac[1],s->mac[2],s->mac[3],s->mac[4],s->mac[5]);
+    } else {
+
+#ifdef ATH6K_CONFIG_CFG80211
+    ar6k_cfg80211_tkip_micerr_event(ar, keyid, ismcast);
+#endif /* ATH6K_CONFIG_CFG80211 */
+
+        A_PRINTF("AR6000 TKIP MIC error received for keyid %d %scast\n",
+             keyid & 0x3, ismcast ? "multi": "uni");
+        snprintf(buf, sizeof(buf), "%s(keyid=%d %sicast)", tag, keyid & 0x3,
+             ismcast ? "mult" : "un");
+    }
+
+    memset(&wrqu, 0, sizeof(wrqu));
+    wrqu.data.length = strlen(buf);
+    wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf);
+}
+
+void
+ar6000_scanComplete_event(AR_SOFTC_T *ar, A_STATUS status)
+{
+
+#ifdef ATH6K_CONFIG_CFG80211
+    ar6k_cfg80211_scanComplete_event(ar, status);
+#endif /* ATH6K_CONFIG_CFG80211 */
+
+    if (!ar->arUserBssFilter) {
+        wmi_bssfilter_cmd(ar->arWmi, NONE_BSS_FILTER, 0);
+    }
+    if (ar->scan_triggered) {
+        if (status==A_OK) {
+            union iwreq_data wrqu;
+            A_MEMZERO(&wrqu, sizeof(wrqu));
+            wireless_send_event(ar->arNetDev, SIOCGIWSCAN, &wrqu, NULL);
+        }
+        ar->scan_triggered = 0;
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_SCAN,( "AR6000 scan complete: %d\n", status));
+}
+
+void
+ar6000_targetStats_event(AR_SOFTC_T *ar,  A_UINT8 *ptr, A_UINT32 len)
+{
+    A_UINT8 ac;
+
+    if(ar->arNetworkType == AP_NETWORK) {
+        WMI_AP_MODE_STAT *p = (WMI_AP_MODE_STAT *)ptr;
+        WMI_AP_MODE_STAT *ap = &ar->arAPStats;
+
+        if (len < sizeof(*p)) {
+            return;
+        }
+
+        for(ac=0;ac<AP_MAX_NUM_STA;ac++) {
+            ap->sta[ac].tx_bytes   += p->sta[ac].tx_bytes;
+            ap->sta[ac].tx_pkts    += p->sta[ac].tx_pkts;
+            ap->sta[ac].tx_error   += p->sta[ac].tx_error;
+            ap->sta[ac].tx_discard += p->sta[ac].tx_discard;
+            ap->sta[ac].rx_bytes   += p->sta[ac].rx_bytes;
+            ap->sta[ac].rx_pkts    += p->sta[ac].rx_pkts;
+            ap->sta[ac].rx_error   += p->sta[ac].rx_error;
+            ap->sta[ac].rx_discard += p->sta[ac].rx_discard;
+        }
+
+    } else {
+        WMI_TARGET_STATS *pTarget = (WMI_TARGET_STATS *)ptr;
+         TARGET_STATS *pStats = &ar->arTargetStats;
+
+        if (len < sizeof(*pTarget)) {
+            return;
+        }
+
+        // Update the RSSI of the connected bss.
+        if (ar->arConnected) {
+            bss_t *pConnBss = NULL;
+
+            pConnBss = wmi_find_node(ar->arWmi,ar->arBssid);
+            if (pConnBss)
+            {
+                pConnBss->ni_rssi = pTarget->cservStats.cs_aveBeacon_rssi;
+                pConnBss->ni_snr = pTarget->cservStats.cs_aveBeacon_snr;
+                wmi_node_return(ar->arWmi, pConnBss);
+            }
+        }
+
+        AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("AR6000 updating target stats\n"));
+        pStats->tx_packets          += pTarget->txrxStats.tx_stats.tx_packets;
+        pStats->tx_bytes            += pTarget->txrxStats.tx_stats.tx_bytes;
+        pStats->tx_unicast_pkts     += pTarget->txrxStats.tx_stats.tx_unicast_pkts;
+        pStats->tx_unicast_bytes    += pTarget->txrxStats.tx_stats.tx_unicast_bytes;
+        pStats->tx_multicast_pkts   += pTarget->txrxStats.tx_stats.tx_multicast_pkts;
+        pStats->tx_multicast_bytes  += pTarget->txrxStats.tx_stats.tx_multicast_bytes;
+        pStats->tx_broadcast_pkts   += pTarget->txrxStats.tx_stats.tx_broadcast_pkts;
+        pStats->tx_broadcast_bytes  += pTarget->txrxStats.tx_stats.tx_broadcast_bytes;
+        pStats->tx_rts_success_cnt  += pTarget->txrxStats.tx_stats.tx_rts_success_cnt;
+        for(ac = 0; ac < WMM_NUM_AC; ac++)
+            pStats->tx_packet_per_ac[ac] += pTarget->txrxStats.tx_stats.tx_packet_per_ac[ac];
+        pStats->tx_errors           += pTarget->txrxStats.tx_stats.tx_errors;
+        pStats->tx_failed_cnt       += pTarget->txrxStats.tx_stats.tx_failed_cnt;
+        pStats->tx_retry_cnt        += pTarget->txrxStats.tx_stats.tx_retry_cnt;
+        pStats->tx_mult_retry_cnt   += pTarget->txrxStats.tx_stats.tx_mult_retry_cnt;
+        pStats->tx_rts_fail_cnt     += pTarget->txrxStats.tx_stats.tx_rts_fail_cnt;
+        pStats->tx_unicast_rate      = wmi_get_rate(pTarget->txrxStats.tx_stats.tx_unicast_rate);
+
+        pStats->rx_packets          += pTarget->txrxStats.rx_stats.rx_packets;
+        pStats->rx_bytes            += pTarget->txrxStats.rx_stats.rx_bytes;
+        pStats->rx_unicast_pkts     += pTarget->txrxStats.rx_stats.rx_unicast_pkts;
+        pStats->rx_unicast_bytes    += pTarget->txrxStats.rx_stats.rx_unicast_bytes;
+        pStats->rx_multicast_pkts   += pTarget->txrxStats.rx_stats.rx_multicast_pkts;
+        pStats->rx_multicast_bytes  += pTarget->txrxStats.rx_stats.rx_multicast_bytes;
+        pStats->rx_broadcast_pkts   += pTarget->txrxStats.rx_stats.rx_broadcast_pkts;
+        pStats->rx_broadcast_bytes  += pTarget->txrxStats.rx_stats.rx_broadcast_bytes;
+        pStats->rx_fragment_pkt     += pTarget->txrxStats.rx_stats.rx_fragment_pkt;
+        pStats->rx_errors           += pTarget->txrxStats.rx_stats.rx_errors;
+        pStats->rx_crcerr           += pTarget->txrxStats.rx_stats.rx_crcerr;
+        pStats->rx_key_cache_miss   += pTarget->txrxStats.rx_stats.rx_key_cache_miss;
+        pStats->rx_decrypt_err      += pTarget->txrxStats.rx_stats.rx_decrypt_err;
+        pStats->rx_duplicate_frames += pTarget->txrxStats.rx_stats.rx_duplicate_frames;
+        pStats->rx_unicast_rate      = wmi_get_rate(pTarget->txrxStats.rx_stats.rx_unicast_rate);
+
+
+        pStats->tkip_local_mic_failure
+                                += pTarget->txrxStats.tkipCcmpStats.tkip_local_mic_failure;
+        pStats->tkip_counter_measures_invoked
+                                += pTarget->txrxStats.tkipCcmpStats.tkip_counter_measures_invoked;
+        pStats->tkip_replays        += pTarget->txrxStats.tkipCcmpStats.tkip_replays;
+        pStats->tkip_format_errors  += pTarget->txrxStats.tkipCcmpStats.tkip_format_errors;
+        pStats->ccmp_format_errors  += pTarget->txrxStats.tkipCcmpStats.ccmp_format_errors;
+        pStats->ccmp_replays        += pTarget->txrxStats.tkipCcmpStats.ccmp_replays;
+
+        pStats->power_save_failure_cnt += pTarget->pmStats.power_save_failure_cnt;
+        pStats->noise_floor_calibation = pTarget->noise_floor_calibation;
+
+        pStats->cs_bmiss_cnt        += pTarget->cservStats.cs_bmiss_cnt;
+        pStats->cs_lowRssi_cnt      += pTarget->cservStats.cs_lowRssi_cnt;
+        pStats->cs_connect_cnt      += pTarget->cservStats.cs_connect_cnt;
+        pStats->cs_disconnect_cnt   += pTarget->cservStats.cs_disconnect_cnt;
+        pStats->cs_aveBeacon_snr    = pTarget->cservStats.cs_aveBeacon_snr;
+        pStats->cs_aveBeacon_rssi   = pTarget->cservStats.cs_aveBeacon_rssi;
+
+        if (enablerssicompensation) {
+            pStats->cs_aveBeacon_rssi =
+                    rssi_compensation_calc(ar, pStats->cs_aveBeacon_rssi);
+        }
+        pStats->cs_lastRoam_msec    = pTarget->cservStats.cs_lastRoam_msec;
+        pStats->cs_snr              = pTarget->cservStats.cs_snr;
+        pStats->cs_rssi             = pTarget->cservStats.cs_rssi;
+
+        pStats->lq_val              = pTarget->lqVal;
+
+        pStats->wow_num_pkts_dropped += pTarget->wowStats.wow_num_pkts_dropped;
+        pStats->wow_num_host_pkt_wakeups += pTarget->wowStats.wow_num_host_pkt_wakeups;
+        pStats->wow_num_host_event_wakeups += pTarget->wowStats.wow_num_host_event_wakeups;
+        pStats->wow_num_events_discarded += pTarget->wowStats.wow_num_events_discarded;
+        pStats->arp_received += pTarget->arpStats.arp_received;
+        pStats->arp_matched  += pTarget->arpStats.arp_matched;
+        pStats->arp_replied  += pTarget->arpStats.arp_replied;
+
+        if (ar->statsUpdatePending) {
+            ar->statsUpdatePending = FALSE;
+            wake_up(&arEvent);
+        }
+    }
+}
+
+void
+ar6000_rssiThreshold_event(AR_SOFTC_T *ar,  WMI_RSSI_THRESHOLD_VAL newThreshold, A_INT16 rssi)
+{
+    USER_RSSI_THOLD userRssiThold;
+
+    rssi = rssi + SIGNAL_QUALITY_NOISE_FLOOR;
+
+    if (enablerssicompensation) {
+        rssi = rssi_compensation_calc(ar, rssi);
+    }
+
+    /* Send an event to the app */
+    userRssiThold.tag = ar->rssi_map[newThreshold].tag;
+    userRssiThold.rssi = rssi;
+    A_PRINTF("rssi Threshold range = %d tag = %d  rssi = %d\n", newThreshold,
+             userRssiThold.tag, userRssiThold.rssi);
+
+    ar6000_send_event_to_app(ar, WMI_RSSI_THRESHOLD_EVENTID,(A_UINT8 *)&userRssiThold, sizeof(USER_RSSI_THOLD));
+}
+
+
+void
+ar6000_hbChallengeResp_event(AR_SOFTC_T *ar, A_UINT32 cookie, A_UINT32 source)
+{
+    if (source == APP_HB_CHALLENGE) {
+        /* Report it to the app in case it wants a positive acknowledgement */
+        ar6000_send_event_to_app(ar, WMIX_HB_CHALLENGE_RESP_EVENTID,
+                                 (A_UINT8 *)&cookie, sizeof(cookie));
+    } else {
+        /* This would ignore the replys that come in after their due time */
+        if (cookie == ar->arHBChallengeResp.seqNum) {
+            ar->arHBChallengeResp.outstanding = FALSE;
+        }
+    }
+}
+
+
+void
+ar6000_reportError_event(AR_SOFTC_T *ar, WMI_TARGET_ERROR_VAL errorVal)
+{
+	static const char * const errString[] = {
+		[WMI_TARGET_PM_ERR_FAIL]    "WMI_TARGET_PM_ERR_FAIL",
+		[WMI_TARGET_KEY_NOT_FOUND]  "WMI_TARGET_KEY_NOT_FOUND",
+		[WMI_TARGET_DECRYPTION_ERR] "WMI_TARGET_DECRYPTION_ERR",
+		[WMI_TARGET_BMISS]          "WMI_TARGET_BMISS",
+		[WMI_PSDISABLE_NODE_JOIN]   "WMI_PSDISABLE_NODE_JOIN"
+	};
+
+    A_PRINTF("AR6000 Error on Target. Error = 0x%x\n", errorVal);
+
+    /* One error is reported at a time, and errorval is a bitmask */
+    if(errorVal & (errorVal - 1))
+       return;
+
+    A_PRINTF("AR6000 Error type = ");
+    switch(errorVal)
+    {
+        case WMI_TARGET_PM_ERR_FAIL:
+        case WMI_TARGET_KEY_NOT_FOUND:
+        case WMI_TARGET_DECRYPTION_ERR:
+        case WMI_TARGET_BMISS:
+        case WMI_PSDISABLE_NODE_JOIN:
+            A_PRINTF("%s\n", errString[errorVal]);
+            break;
+        default:
+            A_PRINTF("INVALID\n");
+            break;
+    }
+
+}
+
+
+void
+ar6000_cac_event(AR_SOFTC_T *ar, A_UINT8 ac, A_UINT8 cacIndication,
+                 A_UINT8 statusCode, A_UINT8 *tspecSuggestion)
+{
+    WMM_TSPEC_IE    *tspecIe;
+
+    /*
+     * This is the TSPEC IE suggestion from AP.
+     * Suggestion provided by AP under some error
+     * cases, could be helpful for the host app.
+     * Check documentation.
+     */
+    tspecIe = (WMM_TSPEC_IE *)tspecSuggestion;
+
+    /*
+     * What do we do, if we get TSPEC rejection? One thought
+     * that comes to mind is implictly delete the pstream...
+     */
+    A_PRINTF("AR6000 CAC notification. "
+                "AC = %d, cacIndication = 0x%x, statusCode = 0x%x\n",
+                 ac, cacIndication, statusCode);
+}
+
+void
+ar6000_channel_change_event(AR_SOFTC_T *ar, A_UINT16 oldChannel,
+                            A_UINT16 newChannel)
+{
+    A_PRINTF("Channel Change notification\nOld Channel: %d, New Channel: %d\n",
+             oldChannel, newChannel);
+}
+
+#define AR6000_PRINT_BSSID(_pBss)  do {     \
+        A_PRINTF("%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x ",\
+                 (_pBss)[0],(_pBss)[1],(_pBss)[2],(_pBss)[3],\
+                 (_pBss)[4],(_pBss)[5]);  \
+} while(0)
+
+void
+ar6000_roam_tbl_event(AR_SOFTC_T *ar, WMI_TARGET_ROAM_TBL *pTbl)
+{
+    A_UINT8 i;
+
+    A_PRINTF("ROAM TABLE NO OF ENTRIES is %d ROAM MODE is %d\n",
+              pTbl->numEntries, pTbl->roamMode);
+    for (i= 0; i < pTbl->numEntries; i++) {
+        A_PRINTF("[%d]bssid %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x ", i,
+            pTbl->bssRoamInfo[i].bssid[0], pTbl->bssRoamInfo[i].bssid[1],
+            pTbl->bssRoamInfo[i].bssid[2],
+            pTbl->bssRoamInfo[i].bssid[3],
+            pTbl->bssRoamInfo[i].bssid[4],
+            pTbl->bssRoamInfo[i].bssid[5]);
+        A_PRINTF("RSSI %d RSSIDT %d LAST RSSI %d UTIL %d ROAM_UTIL %d"
+                 " BIAS %d\n",
+            pTbl->bssRoamInfo[i].rssi,
+            pTbl->bssRoamInfo[i].rssidt,
+            pTbl->bssRoamInfo[i].last_rssi,
+            pTbl->bssRoamInfo[i].util,
+            pTbl->bssRoamInfo[i].roam_util,
+            pTbl->bssRoamInfo[i].bias);
+    }
+}
+
+void
+ar6000_wow_list_event(struct ar6_softc *ar, A_UINT8 num_filters, WMI_GET_WOW_LIST_REPLY *wow_reply)
+{
+    A_UINT8 i,j;
+
+    /*Each event now contains exactly one filter, see bug 26613*/
+    A_PRINTF("WOW pattern %d of %d patterns\n", wow_reply->this_filter_num,                 wow_reply->num_filters);
+    A_PRINTF("wow mode = %s host mode = %s\n",
+            (wow_reply->wow_mode == 0? "disabled":"enabled"),
+            (wow_reply->host_mode == 1 ? "awake":"asleep"));
+
+
+    /*If there are no patterns, the reply will only contain generic
+      WoW information. Pattern information will exist only if there are
+      patterns present. Bug 26716*/
+
+   /* If this event contains pattern information, display it*/
+    if (wow_reply->this_filter_num) {
+        i=0;
+        A_PRINTF("id=%d size=%d offset=%d\n",
+                    wow_reply->wow_filters[i].wow_filter_id,
+                    wow_reply->wow_filters[i].wow_filter_size,
+                    wow_reply->wow_filters[i].wow_filter_offset);
+       A_PRINTF("wow pattern = ");
+       for (j=0; j< wow_reply->wow_filters[i].wow_filter_size; j++) {
+             A_PRINTF("%2.2x",wow_reply->wow_filters[i].wow_filter_pattern[j]);
+        }
+
+        A_PRINTF("\nwow mask = ");
+        for (j=0; j< wow_reply->wow_filters[i].wow_filter_size; j++) {
+            A_PRINTF("%2.2x",wow_reply->wow_filters[i].wow_filter_mask[j]);
+        }
+        A_PRINTF("\n");
+    }
+}
+
+/*
+ * Report the Roaming related data collected on the target
+ */
+void
+ar6000_display_roam_time(WMI_TARGET_ROAM_TIME *p)
+{
+    A_PRINTF("Disconnect Data : BSSID: ");
+    AR6000_PRINT_BSSID(p->disassoc_bssid);
+    A_PRINTF(" RSSI %d DISASSOC Time %d NO_TXRX_TIME %d\n",
+             p->disassoc_bss_rssi,p->disassoc_time,
+             p->no_txrx_time);
+    A_PRINTF("Connect Data: BSSID: ");
+    AR6000_PRINT_BSSID(p->assoc_bssid);
+    A_PRINTF(" RSSI %d ASSOC Time %d TXRX_TIME %d\n",
+             p->assoc_bss_rssi,p->assoc_time,
+             p->allow_txrx_time);
+}
+
+void
+ar6000_roam_data_event(AR_SOFTC_T *ar, WMI_TARGET_ROAM_DATA *p)
+{
+    switch (p->roamDataType) {
+        case ROAM_DATA_TIME:
+            ar6000_display_roam_time(&p->u.roamTime);
+            break;
+        default:
+            break;
+    }
+}
+
+void
+ar6000_bssInfo_event_rx(AR_SOFTC_T *ar, A_UINT8 *datap, int len)
+{
+    struct sk_buff *skb;
+    WMI_BSS_INFO_HDR *bih = (WMI_BSS_INFO_HDR *)datap;
+
+
+    if (!ar->arMgmtFilter) {
+        return;
+    }
+    if (((ar->arMgmtFilter & IEEE80211_FILTER_TYPE_BEACON) &&
+        (bih->frameType != BEACON_FTYPE))  ||
+        ((ar->arMgmtFilter & IEEE80211_FILTER_TYPE_PROBE_RESP) &&
+        (bih->frameType != PROBERESP_FTYPE)))
+    {
+        return;
+    }
+
+    if ((skb = A_NETBUF_ALLOC_RAW(len)) != NULL) {
+
+        A_NETBUF_PUT(skb, len);
+        A_MEMCPY(A_NETBUF_DATA(skb), datap, len);
+        skb->dev = ar->arNetDev;
+        A_MEMCPY(skb_mac_header(skb), A_NETBUF_DATA(skb), 6);
+        skb->ip_summed = CHECKSUM_NONE;
+        skb->pkt_type = PACKET_OTHERHOST;
+        skb->protocol = __constant_htons(0x0019);
+        netif_rx(skb);
+    }
+}
+
+A_UINT32 wmiSendCmdNum;
+
+A_STATUS
+ar6000_control_tx(void *devt, void *osbuf, HTC_ENDPOINT_ID eid)
+{
+    AR_SOFTC_T       *ar = (AR_SOFTC_T *)devt;
+    A_STATUS         status = A_OK;
+    struct ar_cookie *cookie = NULL;
+    int i;
+#ifdef CONFIG_PM
+    if (ar->arWowState != WLAN_WOW_STATE_NONE) {
+        A_NETBUF_FREE(osbuf);
+        return A_EACCES;
+    }
+#endif /* CONFIG_PM */
+        /* take lock to protect ar6000_alloc_cookie() */
+    AR6000_SPIN_LOCK(&ar->arLock, 0);
+
+    do {
+
+        AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_TX,("ar_contrstatus = ol_tx: skb=0x%lx, len=0x%x eid =%d\n",
+                         (unsigned long)osbuf, A_NETBUF_LEN(osbuf), eid));
+
+        if (ar->arWMIControlEpFull && (eid == ar->arControlEp)) {
+                /* control endpoint is full, don't allocate resources, we
+                 * are just going to drop this packet */
+            cookie = NULL;
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" WMI Control EP full, dropping packet : 0x%lX, len:%d \n",
+                    (unsigned long)osbuf, A_NETBUF_LEN(osbuf)));
+        } else {
+            cookie = ar6000_alloc_cookie(ar);
+        }
+
+        if (cookie == NULL) {
+            status = A_NO_MEMORY;
+            break;
+        }
+
+        if(logWmiRawMsgs) {
+            A_PRINTF("WMI cmd send, msgNo %d :", wmiSendCmdNum);
+            for(i = 0; i < a_netbuf_to_len(osbuf); i++)
+                A_PRINTF("%x ", ((A_UINT8 *)a_netbuf_to_data(osbuf))[i]);
+            A_PRINTF("\n");
+        }
+
+        wmiSendCmdNum++;
+
+    } while (FALSE);
+
+    if (cookie != NULL) {
+            /* got a structure to send it out on */
+        ar->arTxPending[eid]++;
+
+        if (eid != ar->arControlEp) {
+            ar->arTotalTxDataPending++;
+        }
+    }
+
+    AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+
+    if (cookie != NULL) {
+        cookie->arc_bp[0] = (unsigned long)osbuf;
+        cookie->arc_bp[1] = 0;
+        SET_HTC_PACKET_INFO_TX(&cookie->HtcPkt,
+                               cookie,
+                               A_NETBUF_DATA(osbuf),
+                               A_NETBUF_LEN(osbuf),
+                               eid,
+                               AR6K_CONTROL_PKT_TAG);
+            /* this interface is asynchronous, if there is an error, cleanup will happen in the
+             * TX completion callback */
+        HTCSendPkt(ar->arHtcTarget, &cookie->HtcPkt);
+        status = A_OK;
+    }
+
+    if (status != A_OK) {
+        A_NETBUF_FREE(osbuf);
+    }
+    return status;
+}
+
+/* indicate tx activity or inactivity on a WMI stream */
+void ar6000_indicate_tx_activity(void *devt, A_UINT8 TrafficClass, A_BOOL Active)
+{
+    AR_SOFTC_T  *ar = (AR_SOFTC_T *)devt;
+    HTC_ENDPOINT_ID eid ;
+    int i;
+
+    if (ar->arWmiEnabled) {
+        eid = arAc2EndpointID(ar, TrafficClass);
+
+        AR6000_SPIN_LOCK(&ar->arLock, 0);
+
+        ar->arAcStreamActive[TrafficClass] = Active;
+
+        if (Active) {
+            /* when a stream goes active, keep track of the active stream with the highest priority */
+
+            if (ar->arAcStreamPriMap[TrafficClass] > ar->arHiAcStreamActivePri) {
+                    /* set the new highest active priority */
+                ar->arHiAcStreamActivePri = ar->arAcStreamPriMap[TrafficClass];
+            }
+
+        } else {
+            /* when a stream goes inactive, we may have to search for the next active stream
+             * that is the highest priority */
+
+            if (ar->arHiAcStreamActivePri == ar->arAcStreamPriMap[TrafficClass]) {
+
+                /* the highest priority stream just went inactive */
+
+                    /* reset and search for the "next" highest "active" priority stream */
+                ar->arHiAcStreamActivePri = 0;
+                for (i = 0; i < WMM_NUM_AC; i++) {
+                    if (ar->arAcStreamActive[i]) {
+                        if (ar->arAcStreamPriMap[i] > ar->arHiAcStreamActivePri) {
+                            /* set the new highest active priority */
+                            ar->arHiAcStreamActivePri = ar->arAcStreamPriMap[i];
+                        }
+                    }
+                }
+            }
+        }
+
+        AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+
+    } else {
+            /* for mbox ping testing, the traffic class is mapped directly as a stream ID,
+             * see handling of AR6000_XIOCTL_TRAFFIC_ACTIVITY_CHANGE in ioctl.c
+             * convert the stream ID to a endpoint */
+        eid = arAc2EndpointID(ar, TrafficClass);
+    }
+
+        /* notify HTC, this may cause credit distribution changes */
+
+    HTCIndicateActivityChange(ar->arHtcTarget,
+                              eid,
+                              Active);
+
+}
+
+void
+ar6000_btcoex_config_event(struct ar6_softc *ar,  A_UINT8 *ptr, A_UINT32 len)
+{
+
+    WMI_BTCOEX_CONFIG_EVENT *pBtcoexConfig = (WMI_BTCOEX_CONFIG_EVENT *)ptr;
+    WMI_BTCOEX_CONFIG_EVENT *pArbtcoexConfig =&ar->arBtcoexConfig;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("AR6000 BTCOEX CONFIG EVENT \n"));
+
+    A_PRINTF("received config event\n");
+    pArbtcoexConfig->btProfileType = pBtcoexConfig->btProfileType;
+    pArbtcoexConfig->linkId = pBtcoexConfig->linkId;
+
+    switch (pBtcoexConfig->btProfileType) {
+        case WMI_BTCOEX_BT_PROFILE_SCO:
+            A_MEMCPY(&pArbtcoexConfig->info.scoConfigCmd, &pBtcoexConfig->info.scoConfigCmd,
+                                        sizeof(WMI_SET_BTCOEX_SCO_CONFIG_CMD));
+            break;
+        case WMI_BTCOEX_BT_PROFILE_A2DP:
+            A_MEMCPY(&pArbtcoexConfig->info.a2dpConfigCmd, &pBtcoexConfig->info.a2dpConfigCmd,
+                                        sizeof(WMI_SET_BTCOEX_A2DP_CONFIG_CMD));
+            break;
+        case WMI_BTCOEX_BT_PROFILE_ACLCOEX:
+            A_MEMCPY(&pArbtcoexConfig->info.aclcoexConfig, &pBtcoexConfig->info.aclcoexConfig,
+                                        sizeof(WMI_SET_BTCOEX_ACLCOEX_CONFIG_CMD));
+            break;
+        case WMI_BTCOEX_BT_PROFILE_INQUIRY_PAGE:
+           A_MEMCPY(&pArbtcoexConfig->info.btinquiryPageConfigCmd, &pBtcoexConfig->info.btinquiryPageConfigCmd,
+                                        sizeof(WMI_SET_BTCOEX_ACLCOEX_CONFIG_CMD));
+            break;
+    }
+    if (ar->statsUpdatePending) {
+         ar->statsUpdatePending = FALSE;
+          wake_up(&arEvent);
+    }
+}
+
+void
+ar6000_btcoex_stats_event(struct ar6_softc *ar,  A_UINT8 *ptr, A_UINT32 len)
+{
+    WMI_BTCOEX_STATS_EVENT *pBtcoexStats = (WMI_BTCOEX_STATS_EVENT *)ptr;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("AR6000 BTCOEX CONFIG EVENT \n"));
+
+    A_MEMCPY(&ar->arBtcoexStats, pBtcoexStats, sizeof(WMI_BTCOEX_STATS_EVENT));
+
+    if (ar->statsUpdatePending) {
+         ar->statsUpdatePending = FALSE;
+        wake_up(&arEvent);
+    }
+
+}
+module_init(ar6000_init_module);
+module_exit(ar6000_cleanup_module);
+
+/* Init cookie queue */
+static void
+ar6000_cookie_init(AR_SOFTC_T *ar)
+{
+    A_UINT32    i;
+
+    ar->arCookieList = NULL;
+    ar->arCookieCount = 0;
+
+    A_MEMZERO(s_ar_cookie_mem, sizeof(s_ar_cookie_mem));
+
+    for (i = 0; i < MAX_COOKIE_NUM; i++) {
+        ar6000_free_cookie(ar, &s_ar_cookie_mem[i]);
+    }
+}
+
+/* cleanup cookie queue */
+static void
+ar6000_cookie_cleanup(AR_SOFTC_T *ar)
+{
+    /* It is gone .... */
+    ar->arCookieList = NULL;
+    ar->arCookieCount = 0;
+}
+
+/* Init cookie queue */
+static void
+ar6000_free_cookie(AR_SOFTC_T *ar, struct ar_cookie * cookie)
+{
+    /* Insert first */
+    A_ASSERT(ar != NULL);
+    A_ASSERT(cookie != NULL);
+
+    cookie->arc_list_next = ar->arCookieList;
+    ar->arCookieList = cookie;
+    ar->arCookieCount++;
+}
+
+/* cleanup cookie queue */
+static struct ar_cookie *
+ar6000_alloc_cookie(AR_SOFTC_T  *ar)
+{
+    struct ar_cookie   *cookie;
+
+    cookie = ar->arCookieList;
+    if(cookie != NULL)
+    {
+        ar->arCookieList = cookie->arc_list_next;
+        ar->arCookieCount--;
+    }
+
+    return cookie;
+}
+
+#ifdef SEND_EVENT_TO_APP
+/*
+ * This function is used to send event which come from taget to
+ * the application. The buf which send to application is include
+ * the event ID and event content.
+ */
+#define EVENT_ID_LEN   2
+void ar6000_send_event_to_app(AR_SOFTC_T *ar, A_UINT16 eventId,
+                              A_UINT8 *datap, int len)
+{
+
+#if (WIRELESS_EXT >= 15)
+
+/* note: IWEVCUSTOM only exists in wireless extensions after version 15 */
+
+    char *buf;
+    A_UINT16 size;
+    union iwreq_data wrqu;
+
+    size = len + EVENT_ID_LEN;
+
+    if (size > IW_CUSTOM_MAX) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("WMI event ID : 0x%4.4X, len = %d too big for IWEVCUSTOM (max=%d) \n",
+                eventId, size, IW_CUSTOM_MAX));
+        return;
+    }
+
+    buf = A_MALLOC_NOWAIT(size);
+    if (NULL == buf){
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("%s: failed to allocate %d bytes\n", __func__, size));
+        return;
+    }
+
+    A_MEMZERO(buf, size);
+    A_MEMCPY(buf, &eventId, EVENT_ID_LEN);
+    A_MEMCPY(buf+EVENT_ID_LEN, datap, len);
+
+    //AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("event ID = %d,len = %d\n",*(A_UINT16*)buf, size));
+    A_MEMZERO(&wrqu, sizeof(wrqu));
+    wrqu.data.length = size;
+    wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf);
+    A_FREE(buf);
+#endif
+
+
+}
+
+/*
+ * This function is used to send events larger than 256 bytes
+ * to the application. The buf which is sent to application
+ * includes the event ID and event content.
+ */
+void ar6000_send_generic_event_to_app(AR_SOFTC_T *ar, A_UINT16 eventId,
+                                      A_UINT8 *datap, int len)
+{
+
+#if (WIRELESS_EXT >= 18)
+
+/* IWEVGENIE exists in wireless extensions version 18 onwards */
+
+    char *buf;
+    A_UINT16 size;
+    union iwreq_data wrqu;
+
+    size = len + EVENT_ID_LEN;
+
+    if (size > IW_GENERIC_IE_MAX) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("WMI event ID : 0x%4.4X, len = %d too big for IWEVGENIE (max=%d) \n",
+                        eventId, size, IW_GENERIC_IE_MAX));
+        return;
+    }
+
+    buf = A_MALLOC_NOWAIT(size);
+    if (NULL == buf){
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("%s: failed to allocate %d bytes\n", __func__, size));
+        return;
+    }
+
+    A_MEMZERO(buf, size);
+    A_MEMCPY(buf, &eventId, EVENT_ID_LEN);
+    A_MEMCPY(buf+EVENT_ID_LEN, datap, len);
+
+    A_MEMZERO(&wrqu, sizeof(wrqu));
+    wrqu.data.length = size;
+    wireless_send_event(ar->arNetDev, IWEVGENIE, &wrqu, buf);
+
+    A_FREE(buf);
+
+#endif /* (WIRELESS_EXT >= 18) */
+
+}
+#endif /* SEND_EVENT_TO_APP */
+
+
+void
+ar6000_tx_retry_err_event(void *devt)
+{
+    AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Tx retries reach maximum!\n"));
+}
+
+void
+ar6000_snrThresholdEvent_rx(void *devt, WMI_SNR_THRESHOLD_VAL newThreshold, A_UINT8 snr)
+{
+    WMI_SNR_THRESHOLD_EVENT event;
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)devt;
+
+    event.range = newThreshold;
+    event.snr = snr;
+
+    ar6000_send_event_to_app(ar, WMI_SNR_THRESHOLD_EVENTID, (A_UINT8 *)&event,
+                             sizeof(WMI_SNR_THRESHOLD_EVENT));
+}
+
+void
+ar6000_lqThresholdEvent_rx(void *devt, WMI_LQ_THRESHOLD_VAL newThreshold, A_UINT8 lq)
+{
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("lq threshold range %d, lq %d\n", newThreshold, lq));
+}
+
+
+
+A_UINT32
+a_copy_to_user(void *to, const void *from, A_UINT32 n)
+{
+    return(copy_to_user(to, from, n));
+}
+
+A_UINT32
+a_copy_from_user(void *to, const void *from, A_UINT32 n)
+{
+    return(copy_from_user(to, from, n));
+}
+
+
+A_STATUS
+ar6000_get_driver_cfg(struct net_device *dev,
+                        A_UINT16 cfgParam,
+                        void *result)
+{
+
+    A_STATUS    ret = 0;
+
+    switch(cfgParam)
+    {
+        case AR6000_DRIVER_CFG_GET_WLANNODECACHING:
+           *((A_UINT32 *)result) = wlanNodeCaching;
+           break;
+        case AR6000_DRIVER_CFG_LOG_RAW_WMI_MSGS:
+           *((A_UINT32 *)result) = logWmiRawMsgs;
+            break;
+        default:
+           ret = EINVAL;
+           break;
+    }
+
+    return ret;
+}
+
+void
+ar6000_keepalive_rx(void *devt, A_UINT8 configured)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)devt;
+
+    ar->arKeepaliveConfigured = configured;
+    wake_up(&arEvent);
+}
+
+void
+ar6000_pmkid_list_event(void *devt, A_UINT8 numPMKID, WMI_PMKID *pmkidList,
+                        A_UINT8 *bssidList)
+{
+    A_UINT8 i, j;
+
+    A_PRINTF("Number of Cached PMKIDs is %d\n", numPMKID);
+
+    for (i = 0; i < numPMKID; i++) {
+        A_PRINTF("\nBSSID %d ", i);
+            for (j = 0; j < ATH_MAC_LEN; j++) {
+                A_PRINTF("%2.2x", bssidList[j]);
+            }
+        bssidList += (ATH_MAC_LEN + WMI_PMKID_LEN);
+        A_PRINTF("\nPMKID %d ", i);
+            for (j = 0; j < WMI_PMKID_LEN; j++) {
+                A_PRINTF("%2.2x", pmkidList->pmkid[j]);
+            }
+        pmkidList = (WMI_PMKID *)((A_UINT8 *)pmkidList + ATH_MAC_LEN +
+                                  WMI_PMKID_LEN);
+    }
+}
+
+void ar6000_pspoll_event(AR_SOFTC_T *ar,A_UINT8 aid)
+{
+    sta_t *conn=NULL;
+    A_BOOL isPsqEmpty = FALSE;
+
+    conn = ieee80211_find_conn_for_aid(ar, aid);
+
+    /* If the PS q for this STA is not empty, dequeue and send a pkt from
+     * the head of the q. Also update the More data bit in the WMI_DATA_HDR
+     * if there are more pkts for this STA in the PS q. If there are no more
+     * pkts for this STA, update the PVB for this STA.
+     */
+    A_MUTEX_LOCK(&conn->psqLock);
+    isPsqEmpty  = A_NETBUF_QUEUE_EMPTY(&conn->psq);
+    A_MUTEX_UNLOCK(&conn->psqLock);
+
+    if (isPsqEmpty) {
+        /* TODO:No buffered pkts for this STA. Send out a NULL data frame */
+    } else {
+        struct sk_buff *skb = NULL;
+
+        A_MUTEX_LOCK(&conn->psqLock);
+        skb = A_NETBUF_DEQUEUE(&conn->psq);
+        A_MUTEX_UNLOCK(&conn->psqLock);
+        /* Set the STA flag to PSPolled, so that the frame will go out */
+        STA_SET_PS_POLLED(conn);
+        ar6000_data_tx(skb, ar->arNetDev);
+        STA_CLR_PS_POLLED(conn);
+
+        /* Clear the PVB for this STA if the queue has become empty */
+        A_MUTEX_LOCK(&conn->psqLock);
+        isPsqEmpty  = A_NETBUF_QUEUE_EMPTY(&conn->psq);
+        A_MUTEX_UNLOCK(&conn->psqLock);
+
+        if (isPsqEmpty) {
+            wmi_set_pvb_cmd(ar->arWmi, conn->aid, 0);
+        }
+    }
+}
+
+void ar6000_dtimexpiry_event(AR_SOFTC_T *ar)
+{
+    A_BOOL isMcastQueued = FALSE;
+    struct sk_buff *skb = NULL;
+
+    /* If there are no associated STAs, ignore the DTIM expiry event.
+     * There can be potential race conditions where the last associated
+     * STA may disconnect & before the host could clear the 'Indicate DTIM'
+     * request to the firmware, the firmware would have just indicated a DTIM
+     * expiry event. The race is between 'clear DTIM expiry cmd' going
+     * from the host to the firmware & the DTIM expiry event happening from
+     * the firmware to the host.
+     */
+    if (ar->sta_list_index == 0) {
+        return;
+    }
+
+    A_MUTEX_LOCK(&ar->mcastpsqLock);
+    isMcastQueued = A_NETBUF_QUEUE_EMPTY(&ar->mcastpsq);
+    A_MUTEX_UNLOCK(&ar->mcastpsqLock);
+
+    A_ASSERT(isMcastQueued == FALSE);
+
+    /* Flush the mcast psq to the target */
+    /* Set the STA flag to DTIMExpired, so that the frame will go out */
+    ar->DTIMExpired = TRUE;
+
+    A_MUTEX_LOCK(&ar->mcastpsqLock);
+    while (!A_NETBUF_QUEUE_EMPTY(&ar->mcastpsq)) {
+        skb = A_NETBUF_DEQUEUE(&ar->mcastpsq);
+        A_MUTEX_UNLOCK(&ar->mcastpsqLock);
+
+        ar6000_data_tx(skb, ar->arNetDev);
+
+        A_MUTEX_LOCK(&ar->mcastpsqLock);
+    }
+    A_MUTEX_UNLOCK(&ar->mcastpsqLock);
+
+    /* Reset the DTIMExpired flag back to 0 */
+    ar->DTIMExpired = FALSE;
+
+    /* Clear the LSB of the BitMapCtl field of the TIM IE */
+    wmi_set_pvb_cmd(ar->arWmi, MCAST_AID, 0);
+}
+
+void
+read_rssi_compensation_param(AR_SOFTC_T *ar)
+{
+    A_UINT8 *cust_data_ptr;
+
+//#define RSSICOMPENSATION_PRINT
+
+#ifdef RSSICOMPENSATION_PRINT
+    A_INT16 i;
+    cust_data_ptr = ar6000_get_cust_data_buffer(ar->arTargetType);
+    for (i=0; i<16; i++) {
+        A_PRINTF("cust_data_%d = %x \n", i, *(A_UINT8 *)cust_data_ptr);
+        cust_data_ptr += 1;
+    }
+#endif
+
+    cust_data_ptr = ar6000_get_cust_data_buffer(ar->arTargetType);
+
+    rssi_compensation_param.customerID = *(A_UINT16 *)cust_data_ptr & 0xffff;
+    rssi_compensation_param.enable = *(A_UINT16 *)(cust_data_ptr+2) & 0xffff;
+    rssi_compensation_param.bg_param_a = *(A_UINT16 *)(cust_data_ptr+4) & 0xffff;
+    rssi_compensation_param.bg_param_b = *(A_UINT16 *)(cust_data_ptr+6) & 0xffff;
+    rssi_compensation_param.a_param_a = *(A_UINT16 *)(cust_data_ptr+8) & 0xffff;
+    rssi_compensation_param.a_param_b = *(A_UINT16 *)(cust_data_ptr+10) &0xffff;
+    rssi_compensation_param.reserved = *(A_UINT32 *)(cust_data_ptr+12);
+
+#ifdef RSSICOMPENSATION_PRINT
+    A_PRINTF("customerID = 0x%x \n", rssi_compensation_param.customerID);
+    A_PRINTF("enable = 0x%x \n", rssi_compensation_param.enable);
+    A_PRINTF("bg_param_a = 0x%x and %d \n", rssi_compensation_param.bg_param_a, rssi_compensation_param.bg_param_a);
+    A_PRINTF("bg_param_b = 0x%x and %d \n", rssi_compensation_param.bg_param_b, rssi_compensation_param.bg_param_b);
+    A_PRINTF("a_param_a = 0x%x and %d \n", rssi_compensation_param.a_param_a, rssi_compensation_param.a_param_a);
+    A_PRINTF("a_param_b = 0x%x and %d \n", rssi_compensation_param.a_param_b, rssi_compensation_param.a_param_b);
+    A_PRINTF("Last 4 bytes = 0x%x \n", rssi_compensation_param.reserved);
+#endif
+
+    if (rssi_compensation_param.enable != 0x1) {
+        rssi_compensation_param.enable = 0;
+    }
+
+   return;
+}
+
+A_INT32
+rssi_compensation_calc_tcmd(A_UINT32 freq, A_INT32 rssi, A_UINT32 totalPkt)
+{
+
+    if (freq > 5000)
+    {
+        if (rssi_compensation_param.enable)
+        {
+            AR_DEBUG_PRINTF(ATH_DEBUG_INFO, (">>> 11a\n"));
+            AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("rssi before compensation  = %d, totalPkt = %d\n", rssi,totalPkt));
+            rssi = rssi * rssi_compensation_param.a_param_a + totalPkt * rssi_compensation_param.a_param_b;
+            rssi = (rssi-50) /100;
+            AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("rssi after compensation = %d\n", rssi));
+        }
+    }
+    else
+    {
+        if (rssi_compensation_param.enable)
+        {
+            AR_DEBUG_PRINTF(ATH_DEBUG_INFO, (">>> 11bg\n"));
+            AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("rssi before compensation  = %d, totalPkt = %d\n", rssi,totalPkt));
+            rssi = rssi * rssi_compensation_param.bg_param_a + totalPkt * rssi_compensation_param.bg_param_b;
+            rssi = (rssi-50) /100;
+            AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("rssi after compensation = %d\n", rssi));
+        }
+    }
+
+    return rssi;
+}
+
+A_INT16
+rssi_compensation_calc(AR_SOFTC_T *ar, A_INT16 rssi)
+{
+    if (ar->arBssChannel > 5000)
+    {
+        if (rssi_compensation_param.enable)
+        {
+            AR_DEBUG_PRINTF(ATH_DEBUG_INFO, (">>> 11a\n"));
+            AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("rssi before compensation  = %d\n", rssi));
+            rssi = rssi * rssi_compensation_param.a_param_a + rssi_compensation_param.a_param_b;
+            rssi = (rssi-50) /100;
+            AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("rssi after compensation = %d\n", rssi));
+        }
+    }
+    else
+    {
+        if (rssi_compensation_param.enable)
+        {
+            AR_DEBUG_PRINTF(ATH_DEBUG_INFO, (">>> 11bg\n"));
+            AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("rssi before compensation  = %d\n", rssi));
+            rssi = rssi * rssi_compensation_param.bg_param_a + rssi_compensation_param.bg_param_b;
+            rssi = (rssi-50) /100;
+            AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("rssi after compensation = %d\n", rssi));
+        }
+    }
+
+    return rssi;
+}
+
+A_INT16
+rssi_compensation_reverse_calc(AR_SOFTC_T *ar, A_INT16 rssi, A_BOOL Above)
+{
+    A_INT16 i;
+
+    if (ar->arBssChannel > 5000)
+    {
+        if (rssi_compensation_param.enable)
+        {
+            AR_DEBUG_PRINTF(ATH_DEBUG_INFO, (">>> 11a\n"));
+            AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("rssi before rev compensation  = %d\n", rssi));
+            rssi = rssi * 100;
+            rssi = (rssi - rssi_compensation_param.a_param_b) / rssi_compensation_param.a_param_a;
+            AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("rssi after rev compensation = %d\n", rssi));
+        }
+    }
+    else
+    {
+        if (rssi_compensation_param.enable)
+        {
+            AR_DEBUG_PRINTF(ATH_DEBUG_INFO, (">>> 11bg\n"));
+            AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("rssi before rev compensation  = %d\n", rssi));
+
+            if (Above) {
+                for (i=95; i>=0; i--) {
+                    if (rssi <=  rssi_compensation_table[i]) {
+                        rssi = 0 - i;
+                        break;
+                    }
+                }
+            } else {
+                for (i=0; i<=95; i++) {
+                    if (rssi >=  rssi_compensation_table[i]) {
+                        rssi = 0 - i;
+                        break;
+                    }
+                }
+            }
+            AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("rssi after rev compensation = %d\n", rssi));
+        }
+    }
+
+    return rssi;
+}
+
+#ifdef WAPI_ENABLE
+void ap_wapi_rekey_event(AR_SOFTC_T *ar, A_UINT8 type, A_UINT8 *mac)
+{
+    union iwreq_data wrqu;
+    A_CHAR buf[20];
+
+    A_MEMZERO(buf, sizeof(buf));
+
+    strcpy(buf, "WAPI_REKEY");
+    buf[10] = type;
+    A_MEMCPY(&buf[11], mac, ATH_MAC_LEN);
+
+    A_MEMZERO(&wrqu, sizeof(wrqu));
+    wrqu.data.length = 10+1+ATH_MAC_LEN;
+    wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf);
+
+    A_PRINTF("WAPI REKEY - %d - %02x:%02x\n", type, mac[4], mac[5]);
+}
+#endif
+
+#ifdef USER_KEYS
+static A_STATUS
+
+ar6000_reinstall_keys(AR_SOFTC_T *ar, A_UINT8 key_op_ctrl)
+{
+    A_STATUS status = A_OK;
+    struct ieee80211req_key *uik = &ar->user_saved_keys.ucast_ik;
+    struct ieee80211req_key *bik = &ar->user_saved_keys.bcast_ik;
+    CRYPTO_TYPE  keyType = ar->user_saved_keys.keyType;
+
+    if (IEEE80211_CIPHER_CCKM_KRK != uik->ik_type) {
+        if (NONE_CRYPT == keyType) {
+            goto _reinstall_keys_out;
+        }
+
+        if (uik->ik_keylen) {
+            status = wmi_addKey_cmd(ar->arWmi, uik->ik_keyix,
+                    ar->user_saved_keys.keyType, PAIRWISE_USAGE,
+                    uik->ik_keylen, (A_UINT8 *)&uik->ik_keyrsc,
+                    uik->ik_keydata, key_op_ctrl, uik->ik_macaddr, SYNC_BEFORE_WMIFLAG);
+        }
+
+    } else {
+        status = wmi_add_krk_cmd(ar->arWmi, uik->ik_keydata);
+    }
+
+    if (IEEE80211_CIPHER_CCKM_KRK != bik->ik_type) {
+        if (NONE_CRYPT == keyType) {
+            goto _reinstall_keys_out;
+        }
+
+        if (bik->ik_keylen) {
+            status = wmi_addKey_cmd(ar->arWmi, bik->ik_keyix,
+                    ar->user_saved_keys.keyType, GROUP_USAGE,
+                    bik->ik_keylen, (A_UINT8 *)&bik->ik_keyrsc,
+                    bik->ik_keydata, key_op_ctrl, bik->ik_macaddr, NO_SYNC_WMIFLAG);
+        }
+    } else {
+        status = wmi_add_krk_cmd(ar->arWmi, bik->ik_keydata);
+    }
+
+_reinstall_keys_out:
+    ar->user_savedkeys_stat = USER_SAVEDKEYS_STAT_INIT;
+    ar->user_key_ctrl      = 0;
+
+    return status;
+}
+#endif /* USER_KEYS */
+
+
+void
+ar6000_dset_open_req(
+    void *context,
+    A_UINT32 id,
+    A_UINT32 targHandle,
+    A_UINT32 targReplyFn,
+    A_UINT32 targReplyArg)
+{
+}
+
+void
+ar6000_dset_close(
+    void *context,
+    A_UINT32 access_cookie)
+{
+    return;
+}
+
+void
+ar6000_dset_data_req(
+   void *context,
+   A_UINT32 accessCookie,
+   A_UINT32 offset,
+   A_UINT32 length,
+   A_UINT32 targBuf,
+   A_UINT32 targReplyFn,
+   A_UINT32 targReplyArg)
+{
+}
+
+int
+ar6000_ap_mode_profile_commit(struct ar6_softc *ar)
+{
+    WMI_CONNECT_CMD p;
+    unsigned long  flags;
+
+    /* No change in AP's profile configuration */
+    if(ar->ap_profile_flag==0) {
+        A_PRINTF("COMMIT: No change in profile!!!\n");
+        return -ENODATA;
+    }
+
+    if(!ar->arSsidLen) {
+        A_PRINTF("SSID not set!!!\n");
+        return -ECHRNG;
+    }
+
+    switch(ar->arAuthMode) {
+    case NONE_AUTH:
+        if((ar->arPairwiseCrypto != NONE_CRYPT) &&
+#ifdef WAPI_ENABLE
+           (ar->arPairwiseCrypto != WAPI_CRYPT) &&
+#endif
+           (ar->arPairwiseCrypto != WEP_CRYPT)) {
+            A_PRINTF("Cipher not supported in AP mode Open auth\n");
+            return -EOPNOTSUPP;
+        }
+        break;
+    case WPA_PSK_AUTH:
+    case WPA2_PSK_AUTH:
+    case (WPA_PSK_AUTH|WPA2_PSK_AUTH):
+        break;
+    default:
+        A_PRINTF("This key mgmt type not supported in AP mode\n");
+        return -EOPNOTSUPP;
+    }
+
+    /* Update the arNetworkType */
+    ar->arNetworkType = ar->arNextMode;
+
+    A_MEMZERO(&p,sizeof(p));
+    p.ssidLength = ar->arSsidLen;
+    A_MEMCPY(p.ssid,ar->arSsid,p.ssidLength);
+    p.channel = ar->arChannelHint;
+    p.networkType = ar->arNetworkType;
+
+    p.dot11AuthMode = ar->arDot11AuthMode;
+    p.authMode = ar->arAuthMode;
+    p.pairwiseCryptoType = ar->arPairwiseCrypto;
+    p.pairwiseCryptoLen = ar->arPairwiseCryptoLen;
+    p.groupCryptoType = ar->arGroupCrypto;
+    p.groupCryptoLen = ar->arGroupCryptoLen;
+    p.ctrl_flags = ar->arConnectCtrlFlags;
+
+    ar->arConnected = FALSE;
+
+    wmi_ap_profile_commit(ar->arWmi, &p);
+    spin_lock_irqsave(&ar->arLock, flags);
+    ar->arConnected  = TRUE;
+    netif_carrier_on(ar->arNetDev);
+    spin_unlock_irqrestore(&ar->arLock, flags);
+    ar->ap_profile_flag = 0;
+    return 0;
+}
+
+A_STATUS
+ar6000_connect_to_ap(struct ar6_softc *ar)
+{
+    /* The ssid length check prevents second "essid off" from the user,
+       to be treated as a connect cmd. The second "essid off" is ignored.
+    */
+    if((ar->arWmiReady == TRUE) && (ar->arSsidLen > 0) && ar->arNetworkType!=AP_NETWORK)
+    {
+        A_STATUS status;
+        if((ADHOC_NETWORK != ar->arNetworkType) &&
+           (NONE_AUTH==ar->arAuthMode)          &&
+           (WEP_CRYPT==ar->arPairwiseCrypto)) {
+                ar6000_install_static_wep_keys(ar);
+        }
+
+        if (!ar->arUserBssFilter) {
+            if (wmi_bssfilter_cmd(ar->arWmi, ALL_BSS_FILTER, 0) != A_OK) {
+                return -EIO;
+            }
+        }
+#ifdef WAPI_ENABLE
+        if (ar->arWapiEnable)  {
+            ar->arPairwiseCrypto = WAPI_CRYPT;
+            ar->arPairwiseCryptoLen = 0;
+            ar->arGroupCrypto = WAPI_CRYPT;
+            ar->arGroupCryptoLen = 0;
+            ar->arAuthMode = NONE_AUTH;
+            ar->arConnectCtrlFlags |= CONNECT_IGNORE_WPAx_GROUP_CIPHER;
+        }
+#endif
+        AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("Connect called with authmode %d dot11 auth %d"\
+                        " PW crypto %d PW crypto Len %d GRP crypto %d"\
+                        " GRP crypto Len %d\n",
+                        ar->arAuthMode, ar->arDot11AuthMode,
+                        ar->arPairwiseCrypto, ar->arPairwiseCryptoLen,
+                        ar->arGroupCrypto, ar->arGroupCryptoLen));
+        reconnect_flag = 0;
+        /* Set the listen interval into 1000TUs or more. This value will be indicated to Ap in the conn.
+           later set it back locally at the STA to 100/1000 TUs depending on the power mode */
+        if ((ar->arNetworkType == INFRA_NETWORK)) {
+            wmi_listeninterval_cmd(ar->arWmi, max(ar->arListenIntervalT, (A_UINT16)A_MAX_WOW_LISTEN_INTERVAL), 0);
+        }
+        status = wmi_connect_cmd(ar->arWmi, ar->arNetworkType,
+                                 ar->arDot11AuthMode, ar->arAuthMode,
+                                 ar->arPairwiseCrypto, ar->arPairwiseCryptoLen,
+                                 ar->arGroupCrypto,ar->arGroupCryptoLen,
+                                 ar->arSsidLen, ar->arSsid,
+                                 ar->arReqBssid, ar->arChannelHint,
+                                 ar->arConnectCtrlFlags);
+        if (status != A_OK) {
+            wmi_listeninterval_cmd(ar->arWmi, ar->arListenIntervalT, ar->arListenIntervalB);
+            if (!ar->arUserBssFilter) {
+                wmi_bssfilter_cmd(ar->arWmi, NONE_BSS_FILTER, 0);
+            }
+            return status;
+        }
+
+        if ((!(ar->arConnectCtrlFlags & CONNECT_DO_WPA_OFFLOAD)) &&
+            ((WPA_PSK_AUTH == ar->arAuthMode) || (WPA2_PSK_AUTH == ar->arAuthMode)))
+        {
+            A_TIMEOUT_MS(&ar->disconnect_timer, A_DISCONNECT_TIMER_INTERVAL, 0);
+        }
+
+        ar->arConnectCtrlFlags &= ~CONNECT_DO_WPA_OFFLOAD;
+        
+        ar->arConnectPending = TRUE;
+        return status;    
+    }
+    return A_ERROR;
+}
+
+A_STATUS
+ar6000_ap_mode_get_wpa_ie(struct ar6_softc *ar, struct ieee80211req_wpaie *wpaie)
+{
+    sta_t *conn = NULL;
+    conn = ieee80211_find_conn(ar, wpaie->wpa_macaddr);
+
+    A_MEMZERO(wpaie->wpa_ie, IEEE80211_MAX_IE);
+    A_MEMZERO(wpaie->rsn_ie, IEEE80211_MAX_IE);
+
+    if(conn) {
+        A_MEMCPY(wpaie->wpa_ie, conn->wpa_ie, IEEE80211_MAX_IE);
+    }
+
+    return 0;
+}
+
+A_STATUS
+is_iwioctl_allowed(A_UINT8 mode, A_UINT16 cmd)
+{
+    if(cmd >= SIOCSIWCOMMIT && cmd <= SIOCGIWPOWER) {
+        cmd -= SIOCSIWCOMMIT;
+        if(sioctl_filter[cmd] == 0xFF) return A_OK;
+        if(sioctl_filter[cmd] & mode) return A_OK;
+    } else if(cmd >= SIOCIWFIRSTPRIV && cmd <= (SIOCIWFIRSTPRIV+30)) {
+        cmd -= SIOCIWFIRSTPRIV;
+        if(pioctl_filter[cmd] == 0xFF) return A_OK;
+        if(pioctl_filter[cmd] & mode) return A_OK;
+    } else {
+        return A_ERROR;
+    }
+    return A_ENOTSUP;
+}
+
+A_STATUS
+is_xioctl_allowed(A_UINT8 mode, int cmd)
+{
+    if(sizeof(xioctl_filter)-1 < cmd) {
+        A_PRINTF("Filter for this cmd=%d not defined\n",cmd);
+        return 0;
+    }
+    if(xioctl_filter[cmd] == 0xFF) return A_OK;
+    if(xioctl_filter[cmd] & mode) return A_OK;
+    return A_ERROR;
+}
+
+#ifdef WAPI_ENABLE
+int
+ap_set_wapi_key(struct ar6_softc *ar, void *ikey)
+{
+    struct ieee80211req_key *ik = (struct ieee80211req_key *)ikey;
+    KEY_USAGE   keyUsage = 0;
+    A_STATUS    status;
+
+    if (A_MEMCMP(ik->ik_macaddr, bcast_mac, IEEE80211_ADDR_LEN) == 0) {
+        keyUsage = GROUP_USAGE;
+    } else {
+        keyUsage = PAIRWISE_USAGE;
+    }
+    A_PRINTF("WAPI_KEY: Type:%d ix:%d mac:%02x:%02x len:%d\n",
+        keyUsage, ik->ik_keyix, ik->ik_macaddr[4], ik->ik_macaddr[5],
+        ik->ik_keylen);
+
+    status = wmi_addKey_cmd(ar->arWmi, ik->ik_keyix, WAPI_CRYPT, keyUsage,
+                            ik->ik_keylen, (A_UINT8 *)&ik->ik_keyrsc,
+                            ik->ik_keydata, KEY_OP_INIT_VAL, ik->ik_macaddr,
+                            SYNC_BOTH_WMIFLAG);
+
+    if (A_OK != status) {
+        return -EIO;
+    }
+    return 0;
+}
+#endif
+
+void ar6000_peer_event(
+    void *context,
+    A_UINT8 eventCode,
+    A_UINT8 *macAddr)
+{
+    A_UINT8 pos;
+
+    for (pos=0;pos<6;pos++)
+        printk("%02x: ",*(macAddr+pos));
+    printk("\n");
+}
+
+#ifdef HTC_TEST_SEND_PKTS
+#define HTC_TEST_DUPLICATE 8
+static void DoHTCSendPktsTest(AR_SOFTC_T *ar, int MapNo, HTC_ENDPOINT_ID eid, struct sk_buff *dupskb)
+{
+    struct ar_cookie *cookie;
+    struct ar_cookie *cookieArray[HTC_TEST_DUPLICATE];
+    struct sk_buff   *new_skb;
+    int    i;
+    int    pkts = 0;
+    HTC_PACKET_QUEUE pktQueue;
+    EPPING_HEADER    *eppingHdr;
+
+    eppingHdr = A_NETBUF_DATA(dupskb);
+
+    if (eppingHdr->Cmd_h == EPPING_CMD_NO_ECHO) {
+        /* skip test if this is already a tx perf test */
+        return;
+    }
+
+    for (i = 0; i < HTC_TEST_DUPLICATE; i++,pkts++) {
+        AR6000_SPIN_LOCK(&ar->arLock, 0);
+        cookie = ar6000_alloc_cookie(ar);
+        if (cookie != NULL) {
+            ar->arTxPending[eid]++;
+            ar->arTotalTxDataPending++;
+        }
+
+        AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+
+        if (NULL == cookie) {
+            break;
+        }
+
+        new_skb = A_NETBUF_ALLOC(A_NETBUF_LEN(dupskb));
+
+        if (new_skb == NULL) {
+            AR6000_SPIN_LOCK(&ar->arLock, 0);
+            ar6000_free_cookie(ar,cookie);
+            AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+            break;
+        }
+
+        A_NETBUF_PUT_DATA(new_skb, A_NETBUF_DATA(dupskb), A_NETBUF_LEN(dupskb));
+        cookie->arc_bp[0] = (unsigned long)new_skb;
+        cookie->arc_bp[1] = MapNo;
+        SET_HTC_PACKET_INFO_TX(&cookie->HtcPkt,
+                               cookie,
+                               A_NETBUF_DATA(new_skb),
+                               A_NETBUF_LEN(new_skb),
+                               eid,
+                               AR6K_DATA_PKT_TAG);
+
+        cookieArray[i] = cookie;
+
+        {
+            EPPING_HEADER *pHdr = (EPPING_HEADER *)A_NETBUF_DATA(new_skb);
+            pHdr->Cmd_h = EPPING_CMD_NO_ECHO;  /* do not echo the packet */
+        }
+    }
+
+    if (pkts == 0) {
+        return;
+    }
+
+    INIT_HTC_PACKET_QUEUE(&pktQueue);
+
+    for (i = 0; i < pkts; i++) {
+        HTC_PACKET_ENQUEUE(&pktQueue,&cookieArray[i]->HtcPkt);
+    }
+
+    HTCSendPktsMultiple(ar->arHtcTarget, &pktQueue);
+
+}
+#endif
+
+#ifdef CONFIG_AP_VIRTUAL_ADAPTER_SUPPORT
+/*
+ * Add support for adding and removing a virtual adapter for soft AP.
+ * Some OS requires different adapters names for station and soft AP mode.
+ * To support these requirement, create and destory a netdevice  instance
+ * when the AP mode is operational. A full fledged support for virual device
+ * is not implemented. Rather a virtual interface is created and is linked
+ * with the existing physical device instance during the operation of the 
+ * AP mode.
+ */
+
+A_STATUS ar6000_start_ap_interface(AR_SOFTC_T *ar)
+{
+    AR_VIRTUAL_INTERFACE_T *arApDev;
+
+    /* Change net_device to point to AP instance */
+    arApDev = (AR_VIRTUAL_INTERFACE_T *)ar->arApDev;
+    ar->arNetDev = arApDev->arNetDev;
+
+    return A_OK;
+}
+
+A_STATUS ar6000_stop_ap_interface(AR_SOFTC_T *ar)
+{
+    AR_VIRTUAL_INTERFACE_T *arApDev;
+
+    /* Change net_device to point to sta instance */
+    arApDev = (AR_VIRTUAL_INTERFACE_T *)ar->arApDev;
+    if (arApDev) {
+        ar->arNetDev = arApDev->arStaNetDev;
+    }
+
+    return A_OK;
+}
+
+
+A_STATUS ar6000_create_ap_interface(AR_SOFTC_T *ar, char *ap_ifname) 
+{
+    struct net_device *dev;
+    AR_VIRTUAL_INTERFACE_T *arApDev;
+
+    dev = alloc_etherdev(sizeof(AR_VIRTUAL_INTERFACE_T));
+    if (dev == NULL) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("ar6000_create_ap_interface: can't alloc etherdev\n"));
+        return A_ERROR;
+    } 
+    
+    ether_setup(dev);
+    init_netdev(dev, ap_ifname);
+
+    if (register_netdev(dev)) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("ar6000_create_ap_interface: register_netdev failed\n"));
+        return A_ERROR;
+    }
+
+    arApDev = netdev_priv(dev);
+    arApDev->arDev = ar;
+    arApDev->arNetDev = dev;
+    arApDev->arStaNetDev = ar->arNetDev;
+
+    ar->arApDev = arApDev;
+    arApNetDev = dev;
+
+    /* Copy the MAC address */
+    A_MEMCPY(dev->dev_addr, ar->arNetDev->dev_addr, AR6000_ETH_ADDR_LEN);
+
+    return A_OK;
+}
+
+A_STATUS ar6000_add_ap_interface(AR_SOFTC_T *ar, char *ap_ifname) 
+{
+    /* Interface already added, need not proceed further */
+    if (ar->arApDev != NULL) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("ar6000_add_ap_interface: interface already present \n"));
+        return A_OK;
+    }
+
+    if (ar6000_create_ap_interface(ar, ap_ifname) != A_OK) {
+        return A_ERROR;
+    }
+
+    A_PRINTF("Add AP interface %s \n",ap_ifname);
+
+    return ar6000_start_ap_interface(ar);
+}
+
+A_STATUS ar6000_remove_ap_interface(AR_SOFTC_T *ar)
+{
+    if (arApNetDev) {
+        ar6000_stop_ap_interface(ar);
+
+        unregister_netdev(arApNetDev);
+        free_netdev(apApNetDev);
+
+        A_PRINTF("Remove AP interface\n");
+    }
+    ar->arApDev = NULL;
+    arApNetDev = NULL;
+
+    
+    return A_OK;
+}
+#endif /* CONFIG_AP_VIRTUAL_ADAPTER_SUPPORT */
+
+
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+EXPORT_SYMBOL(setupbtdev);
+#endif
diff --git a/drivers/net/ath6kl/os/linux/ar6000_pm.c b/drivers/net/ath6kl/os/linux/ar6000_pm.c
new file mode 100644
index 00000000000..b937df9c0cb
--- /dev/null
+++ b/drivers/net/ath6kl/os/linux/ar6000_pm.c
@@ -0,0 +1,731 @@
+/*
+ *
+ * Copyright (c) 2004-2010 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ * 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+ *
+ */
+
+/*
+ * Implementation of system power management
+ */
+
+#include "ar6000_drv.h"
+#include <linux/inetdevice.h>
+#include <linux/platform_device.h>
+#include "wlan_config.h"
+
+#ifdef CONFIG_HAS_WAKELOCK
+#include <linux/wakelock.h>
+#endif
+
+#define WOW_ENABLE_MAX_INTERVAL 0
+#define WOW_SET_SCAN_PARAMS     0
+
+extern unsigned int wmitimeout;
+extern wait_queue_head_t arEvent;
+
+#ifdef CONFIG_PM
+#ifdef CONFIG_HAS_WAKELOCK
+struct wake_lock ar6k_suspend_wake_lock;
+struct wake_lock ar6k_wow_wake_lock;
+#endif
+#endif /* CONFIG_PM */
+
+#ifdef ANDROID_ENV
+extern void android_ar6k_check_wow_status(AR_SOFTC_T *ar, struct sk_buff *skb, A_BOOL isEvent);
+#endif
+#undef ATH_MODULE_NAME
+#define ATH_MODULE_NAME pm
+#define  ATH_DEBUG_PM       ATH_DEBUG_MAKE_MODULE_MASK(0)
+
+#ifdef DEBUG
+static ATH_DEBUG_MASK_DESCRIPTION pm_debug_desc[] = {
+    { ATH_DEBUG_PM     , "System power management"},
+};
+
+ATH_DEBUG_INSTANTIATE_MODULE_VAR(pm,
+                                 "pm",
+                                 "System Power Management",
+                                 ATH_DEBUG_MASK_DEFAULTS | ATH_DEBUG_PM,
+                                 ATH_DEBUG_DESCRIPTION_COUNT(pm_debug_desc),
+                                 pm_debug_desc);
+
+#endif /* DEBUG */
+
+A_STATUS ar6000_exit_cut_power_state(AR_SOFTC_T *ar);
+
+#ifdef CONFIG_PM
+static void ar6k_send_asleep_event_to_app(AR_SOFTC_T *ar, A_BOOL asleep)
+{
+    char buf[128];
+    union iwreq_data wrqu;
+
+    snprintf(buf, sizeof(buf), "HOST_ASLEEP=%s", asleep ? "asleep" : "awake");
+    A_MEMZERO(&wrqu, sizeof(wrqu));
+    wrqu.data.length = strlen(buf);
+    wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf);
+}
+
+static void ar6000_wow_resume(AR_SOFTC_T *ar)
+{
+    if (ar->arWowState!= WLAN_WOW_STATE_NONE) {
+        A_UINT16 fg_start_period = (ar->scParams.fg_start_period==0) ? 1 : ar->scParams.fg_start_period;
+        A_UINT16 bg_period = (ar->scParams.bg_period==0) ? 60 : ar->scParams.bg_period;
+        WMI_SET_HOST_SLEEP_MODE_CMD hostSleepMode = {TRUE, FALSE};
+        ar->arWowState = WLAN_WOW_STATE_NONE;
+#ifdef CONFIG_HAS_WAKELOCK
+        wake_lock_timeout(&ar6k_wow_wake_lock, 3*HZ);
+#endif
+        if (wmi_set_host_sleep_mode_cmd(ar->arWmi, &hostSleepMode)!=A_OK) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Fail to setup restore host awake\n"));
+        }
+#if WOW_SET_SCAN_PARAMS
+        wmi_scanparams_cmd(ar->arWmi, fg_start_period,
+                                   ar->scParams.fg_end_period,
+                                   bg_period,
+                                   ar->scParams.minact_chdwell_time,
+                                   ar->scParams.maxact_chdwell_time,
+                                   ar->scParams.pas_chdwell_time,
+                                   ar->scParams.shortScanRatio,
+                                   ar->scParams.scanCtrlFlags,
+                                   ar->scParams.max_dfsch_act_time,
+                                   ar->scParams.maxact_scan_per_ssid);
+#else
+       (void)fg_start_period;
+       (void)bg_period;
+#endif
+
+
+#if WOW_ENABLE_MAX_INTERVAL /* we don't do it if the power consumption is already good enough. */
+        if (wmi_listeninterval_cmd(ar->arWmi, ar->arListenIntervalT, ar->arListenIntervalB) == A_OK) {
+        }
+#endif
+        ar6k_send_asleep_event_to_app(ar, FALSE);
+        AR_DEBUG_PRINTF(ATH_DEBUG_PM, ("Resume WoW successfully\n"));
+    } else {
+        AR_DEBUG_PRINTF(ATH_DEBUG_PM, ("WoW does not invoked. skip resume"));
+    }
+    ar->arWlanPowerState = WLAN_POWER_STATE_ON;
+}
+
+static void ar6000_wow_suspend(AR_SOFTC_T *ar)
+{
+#define WOW_LIST_ID 1
+    if (ar->arNetworkType != AP_NETWORK) {
+        /* Setup WoW for unicast & Arp request for our own IP
+        disable background scan. Set listen interval into 1000 TUs
+        Enable keepliave for 110 seconds
+        */
+        struct in_ifaddr **ifap = NULL;
+        struct in_ifaddr *ifa = NULL;
+        struct in_device *in_dev;
+        A_UINT8 macMask[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
+        A_STATUS status;
+        WMI_ADD_WOW_PATTERN_CMD addWowCmd = { .filter = { 0 } };
+        WMI_DEL_WOW_PATTERN_CMD delWowCmd;
+        WMI_SET_HOST_SLEEP_MODE_CMD hostSleepMode = {FALSE, TRUE};
+        WMI_SET_WOW_MODE_CMD wowMode = {    .enable_wow = TRUE,
+                                            .hostReqDelay = 500 };/*500 ms delay*/
+
+        if (ar->arWowState!= WLAN_WOW_STATE_NONE) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("System already go into wow mode!\n"));
+            return;
+        }
+
+        ar6000_TxDataCleanup(ar); /* IMPORTANT, otherwise there will be 11mA after listen interval as 1000*/
+
+#if WOW_ENABLE_MAX_INTERVAL /* we don't do it if the power consumption is already good enough. */
+        if (wmi_listeninterval_cmd(ar->arWmi, A_MAX_WOW_LISTEN_INTERVAL, 0) == A_OK) {
+        }
+#endif
+
+#if WOW_SET_SCAN_PARAMS
+        status = wmi_scanparams_cmd(ar->arWmi, 0xFFFF, 0, 0xFFFF, 0, 0, 0, 0, 0, 0, 0);
+#endif
+        /* clear up our WoW pattern first */
+        delWowCmd.filter_list_id = WOW_LIST_ID;
+        delWowCmd.filter_id = 0;
+        wmi_del_wow_pattern_cmd(ar->arWmi, &delWowCmd);
+
+        /* setup unicast packet pattern for WoW */
+        if (ar->arNetDev->dev_addr[1]) {
+            addWowCmd.filter_list_id = WOW_LIST_ID;
+            addWowCmd.filter_size = 6; /* MAC address */
+            addWowCmd.filter_offset = 0;
+            status = wmi_add_wow_pattern_cmd(ar->arWmi, &addWowCmd, ar->arNetDev->dev_addr, macMask, addWowCmd.filter_size);
+            if (status != A_OK) {
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Fail to add WoW pattern\n"));
+            }
+        }
+        /* setup ARP request for our own IP */
+        if ((in_dev = __in_dev_get_rtnl(ar->arNetDev)) != NULL) {
+            for (ifap = &in_dev->ifa_list; (ifa = *ifap) != NULL; ifap = &ifa->ifa_next) {
+                if (!strcmp(ar->arNetDev->name, ifa->ifa_label)) {
+                    break; /* found */
+                }
+            }
+        }
+        if (ifa && ifa->ifa_local) {
+            WMI_SET_IP_CMD ipCmd;
+            memset(&ipCmd, 0, sizeof(ipCmd));
+            ipCmd.ips[0] = ifa->ifa_local;
+            status = wmi_set_ip_cmd(ar->arWmi, &ipCmd);
+            if (status != A_OK) {
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Fail to setup IP for ARP agent\n"));
+            }
+        }
+
+#ifndef ATH6K_CONFIG_OTA_MODE
+        wmi_powermode_cmd(ar->arWmi, REC_POWER);
+#endif
+
+        status = wmi_set_wow_mode_cmd(ar->arWmi, &wowMode);
+        if (status != A_OK) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Fail to enable wow mode\n"));
+        }
+        ar6k_send_asleep_event_to_app(ar, TRUE);
+
+        status = wmi_set_host_sleep_mode_cmd(ar->arWmi, &hostSleepMode);
+        if (status != A_OK) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Fail to set host asleep\n"));
+        }
+
+        ar->arWowState = WLAN_WOW_STATE_SUSPENDING;
+        if (ar->arTxPending[ar->arControlEp]) {
+            A_UINT32 timeleft = wait_event_interruptible_timeout(arEvent,
+            ar->arTxPending[ar->arControlEp] == 0, wmitimeout * HZ);
+            if (!timeleft || signal_pending(current)) {
+               /* what can I do? wow resume at once */
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Fail to setup WoW. Pending wmi control data %d\n", ar->arTxPending[ar->arControlEp]));
+            }
+        }
+
+        status = hifWaitForPendingRecv(ar->arHifDevice);
+
+        ar->arWowState = WLAN_WOW_STATE_SUSPENDED;
+        ar->arWlanPowerState = WLAN_POWER_STATE_WOW;
+    } else {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Not allowed to go to WOW at this moment.\n"));
+    }
+}
+
+A_STATUS ar6000_suspend_ev(void *context)
+{
+    A_STATUS status = A_OK;
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)context;
+    A_INT16 pmmode = ar->arSuspendConfig;
+wow_not_connected:
+    switch (pmmode) {
+    case WLAN_SUSPEND_WOW:
+        if (ar->arWmiReady && ar->arWlanState==WLAN_ENABLED && ar->arConnected) {
+            ar6000_wow_suspend(ar);
+            AR_DEBUG_PRINTF(ATH_DEBUG_PM,("%s:Suspend for wow mode %d\n", __func__, ar->arWlanPowerState));
+        } else {
+            pmmode = ar->arWow2Config;
+            goto wow_not_connected;
+        }
+        break;
+    case WLAN_SUSPEND_CUT_PWR:
+        /* fall through */
+    case WLAN_SUSPEND_CUT_PWR_IF_BT_OFF:
+        /* fall through */
+    case WLAN_SUSPEND_DEEP_SLEEP:
+        /* fall through */
+    default:
+        status = ar6000_update_wlan_pwr_state(ar, WLAN_DISABLED, TRUE);
+        if (ar->arWlanPowerState==WLAN_POWER_STATE_ON ||
+            ar->arWlanPowerState==WLAN_POWER_STATE_WOW) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_PM, ("Strange suspend state for not wow mode %d", ar->arWlanPowerState));
+        }
+        AR_DEBUG_PRINTF(ATH_DEBUG_PM,("%s:Suspend for %d mode pwr %d status %d\n", __func__, pmmode, ar->arWlanPowerState, status));
+        status = (ar->arWlanPowerState == WLAN_POWER_STATE_CUT_PWR) ? A_OK : A_EBUSY;
+        break;
+    }
+
+    ar->scan_triggered = 0;
+    return status;
+}
+
+A_STATUS ar6000_resume_ev(void *context)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)context;
+    A_UINT16 powerState = ar->arWlanPowerState;
+
+#ifdef CONFIG_HAS_WAKELOCK
+    wake_lock(&ar6k_suspend_wake_lock);
+#endif
+    AR_DEBUG_PRINTF(ATH_DEBUG_PM, ("%s: enter previous state %d wowState %d\n", __func__, powerState, ar->arWowState));
+    switch (powerState) {
+    case WLAN_POWER_STATE_WOW:
+        ar6000_wow_resume(ar);
+        break;
+    case WLAN_POWER_STATE_CUT_PWR:
+        /* fall through */
+    case WLAN_POWER_STATE_DEEP_SLEEP:
+        ar6000_update_wlan_pwr_state(ar, WLAN_ENABLED, TRUE);
+        AR_DEBUG_PRINTF(ATH_DEBUG_PM,("%s:Resume for %d mode pwr %d\n", __func__, powerState, ar->arWlanPowerState));
+        break;
+    case WLAN_POWER_STATE_ON:
+        break;
+    default:
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Strange SDIO bus power mode!!\n"));
+        break;
+    }
+#ifdef CONFIG_HAS_WAKELOCK
+    wake_unlock(&ar6k_suspend_wake_lock);
+#endif
+    return A_OK;
+}
+
+void ar6000_check_wow_status(AR_SOFTC_T *ar, struct sk_buff *skb, A_BOOL isEvent)
+{
+    if (ar->arWowState!=WLAN_WOW_STATE_NONE) {
+        if (ar->arWowState==WLAN_WOW_STATE_SUSPENDING) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_PM,("\n%s: Received IRQ while we are wow suspending!!!\n\n", __func__));
+            return;
+        }
+        /* Wow resume from irq interrupt */
+        AR_DEBUG_PRINTF(ATH_DEBUG_PM, ("%s: WoW resume from irq thread status %d\n", __func__, ar->arWlanPowerState));
+        ar6000_wow_resume(ar);
+    } else {
+#ifdef ANDROID_ENV
+        android_ar6k_check_wow_status(ar, skb, isEvent);
+#endif
+    }
+}
+
+A_STATUS ar6000_power_change_ev(void *context, A_UINT32 config)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)context;
+    A_STATUS status = A_OK;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_PM, ("%s: power change event callback %d \n", __func__, config));
+    switch (config) {
+       case HIF_DEVICE_POWER_UP:
+            ar6000_restart_endpoint(ar->arNetDev);
+            status = A_OK;
+            break;
+       case HIF_DEVICE_POWER_DOWN:
+       case HIF_DEVICE_POWER_CUT:
+            status = A_OK;
+            break;
+    }
+    return status;
+}
+
+static int ar6000_pm_probe(struct platform_device *pdev)
+{
+    plat_setup_power(1,1);
+    return 0;
+}
+
+static int ar6000_pm_remove(struct platform_device *pdev)
+{
+    plat_setup_power(0,1);
+    return 0;
+}
+
+static int ar6000_pm_suspend(struct platform_device *pdev, pm_message_t state)
+{
+    return 0;
+}
+
+static int ar6000_pm_resume(struct platform_device *pdev)
+{
+    return 0;
+}
+
+static struct platform_driver ar6000_pm_device = {
+    .probe      = ar6000_pm_probe,
+    .remove     = ar6000_pm_remove,
+    .suspend    = ar6000_pm_suspend,
+    .resume     = ar6000_pm_resume,
+    .driver     = {
+        .name = "wlan_ar6000_pm",
+    },
+};
+#endif /* CONFIG_PM */
+
+A_STATUS
+ar6000_setup_cut_power_state(struct ar6_softc *ar,  AR6000_WLAN_STATE state)
+{
+    A_STATUS                      status = A_OK;
+    HIF_DEVICE_POWER_CHANGE_TYPE  config;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_PM, ("%s: Cut power %d %d \n", __func__,state, ar->arWlanPowerState));
+#ifdef CONFIG_PM
+    AR_DEBUG_PRINTF(ATH_DEBUG_PM, ("Wlan OFF %d BT OFf %d \n", ar->arWlanOff, ar->arBTOff));
+#endif
+    do {
+        if (state == WLAN_ENABLED) {
+            /* Not in cut power state.. exit */
+            if (ar->arWlanPowerState != WLAN_POWER_STATE_CUT_PWR) {
+                break;
+            }
+
+            plat_setup_power(1,0);
+
+            /* Change the state to ON */
+            ar->arWlanPowerState = WLAN_POWER_STATE_ON;
+
+
+            /* Indicate POWER_UP to HIF */
+            config = HIF_DEVICE_POWER_UP;
+            status = HIFConfigureDevice(ar->arHifDevice,
+                                HIF_DEVICE_POWER_STATE_CHANGE,
+                                &config,
+                                sizeof(HIF_DEVICE_POWER_CHANGE_TYPE));
+
+            if (status == A_PENDING) {
+#ifdef ANDROID_ENV
+                 /* Wait for WMI ready event */
+                A_UINT32 timeleft = wait_event_interruptible_timeout(arEvent,
+                            (ar->arWmiReady == TRUE), wmitimeout * HZ);
+                if (!timeleft || signal_pending(current)) {
+                    AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("ar6000 : Failed to get wmi ready \n"));
+                    status = A_ERROR;
+                    break;
+                }
+#endif
+                status = A_OK;
+            } else if (status == A_OK) {
+                ar6000_restart_endpoint(ar->arNetDev);
+                status = A_OK;
+            }
+        } else if (state == WLAN_DISABLED) {
+
+
+            /* Already in cut power state.. exit */
+            if (ar->arWlanPowerState == WLAN_POWER_STATE_CUT_PWR) {
+                break;
+            }
+            ar6000_stop_endpoint(ar->arNetDev, TRUE, FALSE);
+
+            config = HIF_DEVICE_POWER_CUT;
+            status = HIFConfigureDevice(ar->arHifDevice,
+                                HIF_DEVICE_POWER_STATE_CHANGE,
+                                &config,
+                                sizeof(HIF_DEVICE_POWER_CHANGE_TYPE));
+
+            plat_setup_power(0,0);
+
+            ar->arWlanPowerState = WLAN_POWER_STATE_CUT_PWR;
+        }
+    } while (0);
+
+    return status;
+}
+
+A_STATUS
+ar6000_setup_deep_sleep_state(struct ar6_softc *ar, AR6000_WLAN_STATE state)
+{
+    A_STATUS status = A_OK;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_PM, ("%s: Deep sleep %d %d \n", __func__,state, ar->arWlanPowerState));
+#ifdef CONFIG_PM
+    AR_DEBUG_PRINTF(ATH_DEBUG_PM, ("Wlan OFF %d BT OFf %d \n", ar->arWlanOff, ar->arBTOff));
+#endif
+    do {
+        WMI_SET_HOST_SLEEP_MODE_CMD hostSleepMode;
+
+        if (state == WLAN_ENABLED) {
+            A_UINT16 fg_start_period;
+
+            /* Not in deep sleep state.. exit */
+            if (ar->arWlanPowerState != WLAN_POWER_STATE_DEEP_SLEEP) {
+                if (ar->arWlanPowerState != WLAN_POWER_STATE_ON) {
+                    AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Strange state when we resume from deep sleep %d\n", ar->arWlanPowerState));
+                }
+                break;
+            }
+
+            fg_start_period = (ar->scParams.fg_start_period==0) ? 1 : ar->scParams.fg_start_period;
+            hostSleepMode.awake = TRUE;
+            hostSleepMode.asleep = FALSE;
+
+            if ((status=wmi_set_host_sleep_mode_cmd(ar->arWmi, &hostSleepMode)) != A_OK) {
+                break;
+            }
+
+            /* Change the state to ON */
+            ar->arWlanPowerState = WLAN_POWER_STATE_ON;
+
+                /* Enable foreground scanning */
+                if ((status=wmi_scanparams_cmd(ar->arWmi, fg_start_period,
+                                        ar->scParams.fg_end_period,
+                                        ar->scParams.bg_period,
+                                        ar->scParams.minact_chdwell_time,
+                                        ar->scParams.maxact_chdwell_time,
+                                        ar->scParams.pas_chdwell_time,
+                                        ar->scParams.shortScanRatio,
+                                        ar->scParams.scanCtrlFlags,
+                                        ar->scParams.max_dfsch_act_time,
+                                        ar->scParams.maxact_scan_per_ssid)) != A_OK)
+                {
+                    break;
+                }
+
+            if (ar->arNetworkType != AP_NETWORK)
+            {
+                if (ar->arSsidLen) {
+                    if (ar6000_connect_to_ap(ar) != A_OK) {
+                        /* no need to report error if connection failed */
+                        break;
+                    }
+                }
+            }
+        } else if (state == WLAN_DISABLED){
+            WMI_SET_WOW_MODE_CMD wowMode = { .enable_wow = FALSE };
+
+            /* Already in deep sleep state.. exit */
+            if (ar->arWlanPowerState != WLAN_POWER_STATE_ON) {
+                if (ar->arWlanPowerState != WLAN_POWER_STATE_DEEP_SLEEP) {
+                    AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Strange state when we suspend for deep sleep %d\n", ar->arWlanPowerState));
+                }
+                break;
+            }
+
+            if (ar->arNetworkType != AP_NETWORK)
+            {
+                /* Disconnect from the AP and disable foreground scanning */
+                AR6000_SPIN_LOCK(&ar->arLock, 0);
+                if (ar->arConnected == TRUE || ar->arConnectPending == TRUE) {
+                    AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+                    wmi_disconnect_cmd(ar->arWmi);
+                } else {
+                    AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+                }
+            }
+
+            ar->scan_triggered = 0;
+
+            if ((status=wmi_scanparams_cmd(ar->arWmi, 0xFFFF, 0, 0, 0, 0, 0, 0, 0, 0, 0)) != A_OK) {
+                break;
+            }
+
+            /* make sure we disable wow for deep sleep */
+            if ((status=wmi_set_wow_mode_cmd(ar->arWmi, &wowMode))!=A_OK)
+            {
+                break;
+            }
+
+            ar6000_TxDataCleanup(ar);
+#ifndef ATH6K_CONFIG_OTA_MODE
+            wmi_powermode_cmd(ar->arWmi, REC_POWER);
+#endif
+
+            hostSleepMode.awake = FALSE;
+            hostSleepMode.asleep = TRUE;
+            if ((status=wmi_set_host_sleep_mode_cmd(ar->arWmi, &hostSleepMode))!=A_OK) {
+                break;
+            }
+            if (ar->arTxPending[ar->arControlEp]) {
+                A_UINT32 timeleft = wait_event_interruptible_timeout(arEvent,
+                                ar->arTxPending[ar->arControlEp] == 0, wmitimeout * HZ);
+                if (!timeleft || signal_pending(current)) {
+                    status = A_ERROR;
+                    break;
+                }
+            }
+            status = hifWaitForPendingRecv(ar->arHifDevice);
+
+            ar->arWlanPowerState = WLAN_POWER_STATE_DEEP_SLEEP;
+        }
+    } while (0);
+
+    if (status!=A_OK) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Fail to enter/exit deep sleep %d\n", state));
+    }
+
+    return status;
+}
+
+A_STATUS
+ar6000_update_wlan_pwr_state(struct ar6_softc *ar, AR6000_WLAN_STATE state, A_BOOL pmEvent)
+{
+    A_STATUS status = A_OK;
+    A_UINT16 powerState, oldPowerState;
+    AR6000_WLAN_STATE oldstate = ar->arWlanState;
+    A_BOOL wlanOff = ar->arWlanOff;
+#ifdef CONFIG_PM
+    A_BOOL btOff = ar->arBTOff;
+#endif /* CONFIG_PM */
+
+    if ((state!=WLAN_DISABLED && state!=WLAN_ENABLED)) {
+        return A_ERROR;
+    }
+
+    if (ar->bIsDestroyProgress) {
+        return A_EBUSY;
+    }
+
+    if (down_interruptible(&ar->arSem)) {
+        return A_ERROR;
+    }
+
+    if (ar->bIsDestroyProgress) {
+        up(&ar->arSem);
+        return A_EBUSY;
+    }
+
+    ar->arWlanState = wlanOff ? WLAN_DISABLED : state;
+    oldPowerState = ar->arWlanPowerState;
+    if (state == WLAN_ENABLED) {
+        powerState = ar->arWlanPowerState;
+        AR_DEBUG_PRINTF(ATH_DEBUG_PM, ("WLAN PWR set to ENABLE^^\n"));
+        if (!wlanOff) {
+            if (powerState == WLAN_POWER_STATE_DEEP_SLEEP) {
+                status = ar6000_setup_deep_sleep_state(ar, WLAN_ENABLED);
+            } else if (powerState == WLAN_POWER_STATE_CUT_PWR) {
+                status = ar6000_setup_cut_power_state(ar, WLAN_ENABLED);
+            }
+        }
+#ifdef CONFIG_PM
+        else if (pmEvent && wlanOff) {
+            A_BOOL allowCutPwr = ((!ar->arBTSharing) || btOff);
+            if ((powerState==WLAN_POWER_STATE_CUT_PWR) && (!allowCutPwr)) {
+                /* Come out of cut power */
+                ar6000_setup_cut_power_state(ar, WLAN_ENABLED);
+                status = ar6000_setup_deep_sleep_state(ar, WLAN_DISABLED);
+            }
+        }
+#endif /* CONFIG_PM */
+    } else if (state == WLAN_DISABLED) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_PM, ("WLAN PWR set to DISABLED~\n"));
+        powerState = WLAN_POWER_STATE_DEEP_SLEEP;
+#ifdef CONFIG_PM
+        if (pmEvent) {  /* disable due to suspend */
+            A_BOOL suspendCutPwr = (ar->arSuspendConfig == WLAN_SUSPEND_CUT_PWR ||
+                                    (ar->arSuspendConfig == WLAN_SUSPEND_WOW &&
+                                        ar->arWow2Config==WLAN_SUSPEND_CUT_PWR));
+            A_BOOL suspendCutIfBtOff = ((ar->arSuspendConfig ==
+                                            WLAN_SUSPEND_CUT_PWR_IF_BT_OFF ||
+                                        (ar->arSuspendConfig == WLAN_SUSPEND_WOW &&
+                                         ar->arWow2Config==WLAN_SUSPEND_CUT_PWR_IF_BT_OFF)) &&
+                                        (!ar->arBTSharing || btOff));
+            if ((suspendCutPwr) ||
+                (suspendCutIfBtOff) ||
+                (ar->arWlanState==WLAN_POWER_STATE_CUT_PWR))
+            {
+                powerState = WLAN_POWER_STATE_CUT_PWR;
+            }
+        } else {
+            if ((wlanOff) &&
+                (ar->arWlanOffConfig == WLAN_OFF_CUT_PWR) &&
+                (!ar->arBTSharing || btOff))
+            {
+                /* For BT clock sharing designs, CUT_POWER depend on BT state */
+                powerState = WLAN_POWER_STATE_CUT_PWR;
+            }
+        }
+#endif /* CONFIG_PM */
+
+        if (powerState == WLAN_POWER_STATE_DEEP_SLEEP) {
+            if (ar->arWlanPowerState == WLAN_POWER_STATE_CUT_PWR) {
+                AR_DEBUG_PRINTF(ATH_DEBUG_PM, ("Load firmware before set to deep sleep\n"));
+                ar6000_setup_cut_power_state(ar, WLAN_ENABLED);
+            }
+            status = ar6000_setup_deep_sleep_state(ar, WLAN_DISABLED);
+        } else if (powerState == WLAN_POWER_STATE_CUT_PWR) {
+            status = ar6000_setup_cut_power_state(ar, WLAN_DISABLED);
+        }
+
+    }
+
+    if (status!=A_OK) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Fail to setup WLAN state %d\n", ar->arWlanState));
+        ar->arWlanState = oldstate;
+    } else if (status == A_OK) {
+        WMI_REPORT_SLEEP_STATE_EVENT  wmiSleepEvent, *pSleepEvent = NULL;
+        if ((ar->arWlanPowerState == WLAN_POWER_STATE_ON) && (oldPowerState != WLAN_POWER_STATE_ON)) {
+            wmiSleepEvent.sleepState = WMI_REPORT_SLEEP_STATUS_IS_AWAKE;
+            pSleepEvent = &wmiSleepEvent;
+        } else if ((ar->arWlanPowerState != WLAN_POWER_STATE_ON) && (oldPowerState == WLAN_POWER_STATE_ON)) {
+            wmiSleepEvent.sleepState = WMI_REPORT_SLEEP_STATUS_IS_DEEP_SLEEP;
+            pSleepEvent = &wmiSleepEvent;
+        }
+        if (pSleepEvent) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_PM, ("SENT WLAN Sleep Event %d\n", wmiSleepEvent.sleepState));
+            ar6000_send_event_to_app(ar, WMI_REPORT_SLEEP_STATE_EVENTID, (A_UINT8*)pSleepEvent,
+                                     sizeof(WMI_REPORT_SLEEP_STATE_EVENTID));
+        }
+    }
+    up(&ar->arSem);
+    return status;
+}
+
+A_STATUS
+ar6000_set_bt_hw_state(struct ar6_softc *ar, A_UINT32 enable)
+{
+#ifdef CONFIG_PM
+    A_BOOL off = (enable == 0);
+    A_STATUS status;
+    if (ar->arBTOff == off) {
+        return A_OK;
+    }
+    ar->arBTOff = off;
+    status = ar6000_update_wlan_pwr_state(ar, ar->arWlanOff ? WLAN_DISABLED : WLAN_ENABLED, FALSE);
+    return status;
+#else
+    return A_OK;
+#endif
+}
+
+A_STATUS
+ar6000_set_wlan_state(struct ar6_softc *ar, AR6000_WLAN_STATE state)
+{
+    A_STATUS status;
+    A_BOOL off = (state == WLAN_DISABLED);
+    if (ar->arWlanOff == off) {
+        return A_OK;
+    }
+    ar->arWlanOff = off;
+    status = ar6000_update_wlan_pwr_state(ar, state, FALSE);
+    return status;
+}
+
+void ar6000_pm_init()
+{
+    A_REGISTER_MODULE_DEBUG_INFO(pm);
+#ifdef CONFIG_PM
+#ifdef CONFIG_HAS_WAKELOCK
+    wake_lock_init(&ar6k_suspend_wake_lock, WAKE_LOCK_SUSPEND, "ar6k_suspend");
+    wake_lock_init(&ar6k_wow_wake_lock, WAKE_LOCK_SUSPEND, "ar6k_wow");
+#endif
+    /*
+     * Register ar6000_pm_device into system.
+     * We should also add platform_device into the first item of array
+     * of devices[] in file arch/xxx/mach-xxx/board-xxxx.c
+     */
+    if (platform_driver_register(&ar6000_pm_device)) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("ar6000: fail to register the power control driver.\n"));
+    }
+#endif /* CONFIG_PM */
+}
+
+void ar6000_pm_exit()
+{
+#ifdef CONFIG_PM
+    platform_driver_unregister(&ar6000_pm_device);
+#ifdef CONFIG_HAS_WAKELOCK
+    wake_lock_destroy(&ar6k_suspend_wake_lock);
+    wake_lock_destroy(&ar6k_wow_wake_lock);
+#endif
+#endif /* CONFIG_PM */
+}
diff --git a/drivers/net/ath6kl/os/linux/ar6000_raw_if.c b/drivers/net/ath6kl/os/linux/ar6000_raw_if.c
new file mode 100644
index 00000000000..6b8eeea475c
--- /dev/null
+++ b/drivers/net/ath6kl/os/linux/ar6000_raw_if.c
@@ -0,0 +1,455 @@
+//------------------------------------------------------------------------------
+// Copyright (c) 2004-2010 Atheros Communications Inc.
+// All rights reserved.
+//
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//
+// Author(s): ="Atheros"
+//------------------------------------------------------------------------------
+
+#include "ar6000_drv.h"
+
+#ifdef HTC_RAW_INTERFACE
+
+static void
+ar6000_htc_raw_read_cb(void *Context, HTC_PACKET *pPacket)
+{
+    AR_SOFTC_T        *ar = (AR_SOFTC_T *)Context;
+    raw_htc_buffer    *busy;
+    HTC_RAW_STREAM_ID streamID; 
+    AR_RAW_HTC_T *arRaw = ar->arRawHtc;
+
+    busy = (raw_htc_buffer *)pPacket->pPktContext;
+    A_ASSERT(busy != NULL);
+
+    if (pPacket->Status == A_ECANCELED) {
+        /*
+         * HTC provides A_ECANCELED status when it doesn't want to be refilled
+         * (probably due to a shutdown)
+         */
+        return;
+    }
+
+    streamID = arEndpoint2RawStreamID(ar,pPacket->Endpoint);
+    A_ASSERT(streamID != HTC_RAW_STREAM_NOT_MAPPED);
+    
+#ifdef CF
+   if (down_trylock(&arRaw->raw_htc_read_sem[streamID])) {
+#else
+    if (down_interruptible(&arRaw->raw_htc_read_sem[streamID])) {
+#endif /* CF */
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Unable to down the semaphore\n"));
+    }
+
+    A_ASSERT((pPacket->Status != A_OK) || 
+             (pPacket->pBuffer == (busy->data + HTC_HEADER_LEN)));
+
+    busy->length = pPacket->ActualLength + HTC_HEADER_LEN;
+    busy->currPtr = HTC_HEADER_LEN;
+    arRaw->read_buffer_available[streamID] = TRUE;
+    //AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("raw read cb:  0x%X 0x%X \n", busy->currPtr,busy->length);
+    up(&arRaw->raw_htc_read_sem[streamID]);
+
+    /* Signal the waiting process */
+    AR_DEBUG_PRINTF(ATH_DEBUG_HTC_RAW,("Waking up the StreamID(%d) read process\n", streamID));
+    wake_up_interruptible(&arRaw->raw_htc_read_queue[streamID]);
+}
+
+static void
+ar6000_htc_raw_write_cb(void *Context, HTC_PACKET *pPacket)
+{
+    AR_SOFTC_T          *ar = (AR_SOFTC_T  *)Context;
+    raw_htc_buffer      *free;
+    HTC_RAW_STREAM_ID   streamID;
+    AR_RAW_HTC_T *arRaw = ar->arRawHtc;
+    
+    free = (raw_htc_buffer *)pPacket->pPktContext;
+    A_ASSERT(free != NULL);
+
+    if (pPacket->Status == A_ECANCELED) {
+        /*
+         * HTC provides A_ECANCELED status when it doesn't want to be refilled
+         * (probably due to a shutdown)
+         */
+        return;
+    }
+
+    streamID = arEndpoint2RawStreamID(ar,pPacket->Endpoint);
+    A_ASSERT(streamID != HTC_RAW_STREAM_NOT_MAPPED);
+    
+#ifdef CF
+    if (down_trylock(&arRaw->raw_htc_write_sem[streamID])) {
+#else
+    if (down_interruptible(&arRaw->raw_htc_write_sem[streamID])) {
+#endif
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Unable to down the semaphore\n"));
+    }
+
+    A_ASSERT(pPacket->pBuffer == (free->data + HTC_HEADER_LEN));
+
+    free->length = 0;
+    arRaw->write_buffer_available[streamID] = TRUE;
+    up(&arRaw->raw_htc_write_sem[streamID]);
+
+    /* Signal the waiting process */
+    AR_DEBUG_PRINTF(ATH_DEBUG_HTC_RAW,("Waking up the StreamID(%d) write process\n", streamID));
+    wake_up_interruptible(&arRaw->raw_htc_write_queue[streamID]);
+}
+
+/* connect to a service */
+static A_STATUS ar6000_connect_raw_service(AR_SOFTC_T        *ar,
+                                           HTC_RAW_STREAM_ID StreamID)
+{
+    A_STATUS                 status;
+    HTC_SERVICE_CONNECT_RESP response;
+    A_UINT8                  streamNo;
+    HTC_SERVICE_CONNECT_REQ  connect;
+    
+    do {      
+        
+        A_MEMZERO(&connect,sizeof(connect));
+            /* pass the stream ID as meta data to the RAW streams service */
+        streamNo = (A_UINT8)StreamID;
+        connect.pMetaData = &streamNo;
+        connect.MetaDataLength = sizeof(A_UINT8);
+            /* these fields are the same for all endpoints */
+        connect.EpCallbacks.pContext = ar;
+        connect.EpCallbacks.EpTxComplete = ar6000_htc_raw_write_cb;   
+        connect.EpCallbacks.EpRecv = ar6000_htc_raw_read_cb;   
+            /* simple interface, we don't need these optional callbacks */      
+        connect.EpCallbacks.EpRecvRefill = NULL;
+        connect.EpCallbacks.EpSendFull = NULL;
+        connect.MaxSendQueueDepth = RAW_HTC_WRITE_BUFFERS_NUM;  
+        
+            /* connect to the raw streams service, we may be able to get 1 or more
+             * connections, depending on WHAT is running on the target */
+        connect.ServiceID = HTC_RAW_STREAMS_SVC;
+        
+        A_MEMZERO(&response,sizeof(response));
+        
+            /* try to connect to the raw stream, it is okay if this fails with 
+             * status HTC_SERVICE_NO_MORE_EP */
+        status = HTCConnectService(ar->arHtcTarget, 
+                                   &connect,
+                                   &response);
+        
+        if (A_FAILED(status)) {
+            if (response.ConnectRespCode == HTC_SERVICE_NO_MORE_EP) {
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("HTC RAW , No more streams allowed \n"));
+                status = A_OK;    
+            }
+            break;    
+        }
+
+            /* set endpoint mapping for the RAW HTC streams */
+        arSetRawStream2EndpointIDMap(ar,StreamID,response.Endpoint);
+
+        AR_DEBUG_PRINTF(ATH_DEBUG_HTC_RAW,("HTC RAW : stream ID: %d, endpoint: %d\n", 
+                        StreamID, arRawStream2EndpointID(ar,StreamID)));
+        
+    } while (FALSE);
+    
+    return status;
+}
+
+int ar6000_htc_raw_open(AR_SOFTC_T *ar)
+{
+    A_STATUS status;
+    int streamID, endPt, count2;
+    raw_htc_buffer *buffer;
+    HTC_SERVICE_ID servicepriority;
+    AR_RAW_HTC_T *arRaw = ar->arRawHtc;
+    if (!arRaw) {
+        arRaw = ar->arRawHtc = A_MALLOC(sizeof(AR_RAW_HTC_T));
+        if (arRaw) {
+            A_MEMZERO(arRaw, sizeof(AR_RAW_HTC_T));
+        }
+    }
+    A_ASSERT(ar->arHtcTarget != NULL);
+    if (!arRaw) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Faile to allocate memory for HTC RAW interface\n"));
+        return -ENOMEM;
+    }
+    /* wait for target */
+    status = HTCWaitTarget(ar->arHtcTarget);
+        
+    if (A_FAILED(status)) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("HTCWaitTarget failed (%d)\n", status));
+        return -ENODEV;  
+    }
+    
+    for (endPt = 0; endPt < ENDPOINT_MAX; endPt++) {
+        arRaw->arEp2RawMapping[endPt] = HTC_RAW_STREAM_NOT_MAPPED;
+    }
+        
+    for (streamID = HTC_RAW_STREAM_0; streamID < HTC_RAW_STREAM_NUM_MAX; streamID++) {
+        /* Initialize the data structures */
+	sema_init(&arRaw->raw_htc_read_sem[streamID], 1);
+	sema_init(&arRaw->raw_htc_write_sem[streamID], 1);
+        init_waitqueue_head(&arRaw->raw_htc_read_queue[streamID]);
+        init_waitqueue_head(&arRaw->raw_htc_write_queue[streamID]);
+
+            /* try to connect to the raw service */
+        status = ar6000_connect_raw_service(ar,streamID);
+        
+        if (A_FAILED(status)) {
+            break;    
+        }
+        
+        if (arRawStream2EndpointID(ar,streamID) == 0) {
+            break;    
+        }
+        
+        for (count2 = 0; count2 < RAW_HTC_READ_BUFFERS_NUM; count2 ++) {
+            /* Initialize the receive buffers */
+            buffer = &arRaw->raw_htc_write_buffer[streamID][count2];
+            memset(buffer, 0, sizeof(raw_htc_buffer));
+            buffer = &arRaw->raw_htc_read_buffer[streamID][count2];
+            memset(buffer, 0, sizeof(raw_htc_buffer));
+            
+            SET_HTC_PACKET_INFO_RX_REFILL(&buffer->HTCPacket,
+                                          buffer,
+                                          buffer->data,
+                                          HTC_RAW_BUFFER_SIZE,
+                                          arRawStream2EndpointID(ar,streamID));
+            
+            /* Queue buffers to HTC for receive */
+            if ((status = HTCAddReceivePkt(ar->arHtcTarget, &buffer->HTCPacket)) != A_OK)
+            {
+                BMIInit();
+                return -EIO;
+            }
+        }
+
+        for (count2 = 0; count2 < RAW_HTC_WRITE_BUFFERS_NUM; count2 ++) {
+            /* Initialize the receive buffers */
+            buffer = &arRaw->raw_htc_write_buffer[streamID][count2];
+            memset(buffer, 0, sizeof(raw_htc_buffer));
+        }
+
+        arRaw->read_buffer_available[streamID] = FALSE;
+        arRaw->write_buffer_available[streamID] = TRUE;
+    }
+    
+    if (A_FAILED(status)) {
+        return -EIO;    
+    }
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("HTC RAW, number of streams the target supports: %d \n", streamID));
+            
+    servicepriority = HTC_RAW_STREAMS_SVC;  /* only 1 */
+    
+        /* set callbacks and priority list */
+    HTCSetCreditDistribution(ar->arHtcTarget,
+                             ar,
+                             NULL,  /* use default */
+                             NULL,  /* use default */
+                             &servicepriority,
+                             1);
+
+    /* Start the HTC component */
+    if ((status = HTCStart(ar->arHtcTarget)) != A_OK) {
+        BMIInit();
+        return -EIO;
+    }
+
+    (ar)->arRawIfInit = TRUE;
+    
+    return 0;
+}
+
+int ar6000_htc_raw_close(AR_SOFTC_T *ar)
+{
+    A_PRINTF("ar6000_htc_raw_close called \n");
+    HTCStop(ar->arHtcTarget);
+    
+        /* reset the device */
+    ar6000_reset_device(ar->arHifDevice, ar->arTargetType, TRUE, FALSE);
+    /* Initialize the BMI component */
+    BMIInit();
+
+    return 0;
+}
+
+raw_htc_buffer *
+get_filled_buffer(AR_SOFTC_T *ar, HTC_RAW_STREAM_ID StreamID)
+{
+    int count;
+    raw_htc_buffer *busy;
+    AR_RAW_HTC_T *arRaw = ar->arRawHtc;
+
+    /* Check for data */
+    for (count = 0; count < RAW_HTC_READ_BUFFERS_NUM; count ++) {
+        busy = &arRaw->raw_htc_read_buffer[StreamID][count];
+        if (busy->length) {
+            break;
+        }
+    }
+    if (busy->length) {
+        arRaw->read_buffer_available[StreamID] = TRUE;
+    } else {
+        arRaw->read_buffer_available[StreamID] = FALSE;
+    }
+
+    return busy;
+}
+
+ssize_t ar6000_htc_raw_read(AR_SOFTC_T *ar, HTC_RAW_STREAM_ID StreamID, 
+                            char __user *buffer, size_t length)
+{
+    int readPtr;
+    raw_htc_buffer *busy;
+    AR_RAW_HTC_T *arRaw = ar->arRawHtc;
+
+    if (arRawStream2EndpointID(ar,StreamID) == 0) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("StreamID(%d) not connected! \n", StreamID));
+        return -EFAULT;    
+    }
+    
+    if (down_interruptible(&arRaw->raw_htc_read_sem[StreamID])) {
+        return -ERESTARTSYS;
+    }
+
+    busy = get_filled_buffer(ar,StreamID);
+    while (!arRaw->read_buffer_available[StreamID]) {
+        up(&arRaw->raw_htc_read_sem[StreamID]);
+
+        /* Wait for the data */
+        AR_DEBUG_PRINTF(ATH_DEBUG_HTC_RAW,("Sleeping StreamID(%d) read process\n", StreamID));
+        if (wait_event_interruptible(arRaw->raw_htc_read_queue[StreamID],
+                                     arRaw->read_buffer_available[StreamID]))
+        {
+            return -EINTR;
+        }
+        if (down_interruptible(&arRaw->raw_htc_read_sem[StreamID])) {
+            return -ERESTARTSYS;
+        }
+        busy = get_filled_buffer(ar,StreamID);
+    }
+
+    /* Read the data */
+    readPtr = busy->currPtr;
+    if (length > busy->length - HTC_HEADER_LEN) {
+        length = busy->length - HTC_HEADER_LEN;
+    }
+    if (copy_to_user(buffer, &busy->data[readPtr], length)) {
+        up(&arRaw->raw_htc_read_sem[StreamID]);
+        return -EFAULT;
+    }
+
+    busy->currPtr += length;
+        
+    if (busy->currPtr == busy->length)
+    {    
+        busy->currPtr = 0;
+        busy->length = 0;        
+        HTC_PACKET_RESET_RX(&busy->HTCPacket);                                          
+        //AR_DEBUG_PRINTF(ATH_DEBUG_HTC_RAW,("raw read ioctl:  ep for packet:%d \n", busy->HTCPacket.Endpoint));
+        HTCAddReceivePkt(ar->arHtcTarget, &busy->HTCPacket);
+    }
+    arRaw->read_buffer_available[StreamID] = FALSE;
+    up(&arRaw->raw_htc_read_sem[StreamID]);
+
+    return length;
+}
+
+static raw_htc_buffer *
+get_free_buffer(AR_SOFTC_T *ar, HTC_ENDPOINT_ID StreamID)
+{
+    int count;
+    raw_htc_buffer *free;
+    AR_RAW_HTC_T *arRaw = ar->arRawHtc;
+
+    free = NULL;
+    for (count = 0; count < RAW_HTC_WRITE_BUFFERS_NUM; count ++) {
+        free = &arRaw->raw_htc_write_buffer[StreamID][count];
+        if (free->length == 0) {
+            break;
+        }
+    }
+    if (!free->length) {
+        arRaw->write_buffer_available[StreamID] = TRUE;
+    } else {
+        arRaw->write_buffer_available[StreamID] = FALSE;
+    }
+
+    return free;
+}
+
+ssize_t ar6000_htc_raw_write(AR_SOFTC_T *ar, HTC_RAW_STREAM_ID StreamID,
+                     char __user *buffer, size_t length)
+{
+    int writePtr;
+    raw_htc_buffer *free;
+    AR_RAW_HTC_T *arRaw = ar->arRawHtc;
+    if (arRawStream2EndpointID(ar,StreamID) == 0) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("StreamID(%d) not connected! \n", StreamID));
+        return -EFAULT;    
+    }
+    
+    if (down_interruptible(&arRaw->raw_htc_write_sem[StreamID])) {
+        return -ERESTARTSYS;
+    }
+
+    /* Search for a free buffer */
+    free = get_free_buffer(ar,StreamID);
+
+    /* Check if there is space to write else wait */
+    while (!arRaw->write_buffer_available[StreamID]) {
+        up(&arRaw->raw_htc_write_sem[StreamID]);
+
+        /* Wait for buffer to become free */
+        AR_DEBUG_PRINTF(ATH_DEBUG_HTC_RAW,("Sleeping StreamID(%d) write process\n", StreamID));
+        if (wait_event_interruptible(arRaw->raw_htc_write_queue[StreamID],
+                                     arRaw->write_buffer_available[StreamID]))
+        {
+            return -EINTR;
+        }
+        if (down_interruptible(&arRaw->raw_htc_write_sem[StreamID])) {
+            return -ERESTARTSYS;
+        }
+        free = get_free_buffer(ar,StreamID);
+    }
+
+    /* Send the data */
+    writePtr = HTC_HEADER_LEN;
+    if (length > (HTC_RAW_BUFFER_SIZE - HTC_HEADER_LEN)) {
+        length = HTC_RAW_BUFFER_SIZE - HTC_HEADER_LEN;
+    }
+
+    if (copy_from_user(&free->data[writePtr], buffer, length)) {
+        up(&arRaw->raw_htc_read_sem[StreamID]);
+        return -EFAULT;
+    }
+
+    free->length = length;
+        
+    SET_HTC_PACKET_INFO_TX(&free->HTCPacket,
+                           free,
+                           &free->data[writePtr],
+                           length,
+                           arRawStream2EndpointID(ar,StreamID),
+                           AR6K_DATA_PKT_TAG);
+    
+    HTCSendPkt(ar->arHtcTarget,&free->HTCPacket);
+    
+    arRaw->write_buffer_available[StreamID] = FALSE;
+    up(&arRaw->raw_htc_write_sem[StreamID]);
+
+    return length;
+}
+#endif /* HTC_RAW_INTERFACE */
diff --git a/drivers/net/ath6kl/os/linux/ar6k_pal.c b/drivers/net/ath6kl/os/linux/ar6k_pal.c
new file mode 100644
index 00000000000..6c98a8817ae
--- /dev/null
+++ b/drivers/net/ath6kl/os/linux/ar6k_pal.c
@@ -0,0 +1,481 @@
+//------------------------------------------------------------------------------
+// Copyright (c) 2004-2010 Atheros Communications Inc.
+// All rights reserved.
+//
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//
+// Author(s): ="Atheros"
+//------------------------------------------------------------------------------
+
+#include "ar6000_drv.h"
+#ifdef AR6K_ENABLE_HCI_PAL
+#include <net/bluetooth/bluetooth.h>
+#include <net/bluetooth/hci_core.h>
+#include <ar6k_pal.h>
+
+extern unsigned int setupbtdev;
+#define bt_check_bit(val, bit) (val & bit)
+#define bt_set_bit(val, bit) (val |= bit)
+#define bt_clear_bit(val, bit) (val &= ~bit)
+
+/* export ATH_AR6K_DEBUG_HCI_PAL=yes in host/localmake.linux.inc
+ * to enable debug information */
+#ifdef HCIPAL_DEBUG
+#define PRIN_LOG(format, args...) printk(KERN_ALERT "%s:%d - %s Msg:" format "\n",__FUNCTION__, __LINE__, __FILE__, ## args) 
+#else
+#define PRIN_LOG(format, args...)
+#endif
+
+/**********************************
+ * HCI PAL private info structure 
+ *********************************/
+typedef struct ar6k_hci_pal_info_s{
+
+	unsigned long ulFlags;
+#define HCI_NORMAL_MODE (1)
+#define HCI_REGISTERED (1<<1)
+	struct hci_dev *hdev;            /* BT Stack HCI dev */
+	AR_SOFTC_T *ar;
+
+}ar6k_hci_pal_info_t;
+
+/*** BT Stack Entrypoints *******/
+/***************************************
+ * bt_open - open a handle to the device
+ ***************************************/
+static int bt_open(struct hci_dev *hdev)
+{
+	PRIN_LOG("HCI PAL: bt_open - enter - x\n");
+	set_bit(HCI_RUNNING, &hdev->flags);
+	set_bit(HCI_UP, &hdev->flags);
+	set_bit(HCI_INIT, &hdev->flags);         
+	return 0;
+}
+
+/***************************************
+ * bt_close - close handle to the device
+ ***************************************/
+static int bt_close(struct hci_dev *hdev)
+{
+	PRIN_LOG("HCI PAL: bt_close - enter\n");
+	clear_bit(HCI_RUNNING, &hdev->flags);
+	return 0;
+}
+
+/*****************************
+ * bt_ioctl - ioctl processing
+ *****************************/
+static int bt_ioctl(struct hci_dev *hdev, unsigned int cmd, unsigned long arg)
+{
+	PRIN_LOG("HCI PAL: bt_ioctl - enter\n");
+	return -ENOIOCTLCMD;
+}
+
+/**************************************
+ * bt_flush - flush outstanding packets
+ **************************************/
+static int bt_flush(struct hci_dev *hdev)
+{
+	PRIN_LOG("HCI PAL: bt_flush - enter\n");
+	return 0;
+}
+
+/***************
+ * bt_destruct  
+ ***************/
+static void bt_destruct(struct hci_dev *hdev)
+{
+	PRIN_LOG("HCI PAL: bt_destruct - enter\n");
+	/* nothing to do here */
+}
+
+/****************************************************
+ * Invoked from bluetooth stack via hdev->send()
+ * to send the packet out via ar6k to PAL firmware.
+ *
+ * For HCI command packet wmi_send_hci_cmd() is invoked.
+ * wmi_send_hci_cmd adds WMI_CMD_HDR and sends the packet
+ * to PAL firmware.
+ *
+ * For HCI ACL data packet wmi_data_hdr_add is invoked 
+ * to add WMI_DATA_HDR to the packet.  ar6000_acl_data_tx 
+ * is then invoked to send the packet to PAL firmware.
+ ******************************************************/
+static int btpal_send_frame(struct sk_buff *skb)
+{
+	struct hci_dev *hdev = (struct hci_dev *)skb->dev;
+	HCI_TRANSPORT_PACKET_TYPE type;
+	ar6k_hci_pal_info_t *pHciPalInfo;
+	A_STATUS status = A_OK;
+	struct sk_buff *txSkb = NULL;
+	AR_SOFTC_T *ar;
+
+	if (!hdev) {
+		PRIN_LOG("HCI PAL: btpal_send_frame - no device\n");
+		return -ENODEV;
+	}
+
+	if (!test_bit(HCI_RUNNING, &hdev->flags)) {
+		PRIN_LOG("HCI PAL: btpal_send_frame - not open\n");
+		return -EBUSY;
+	}
+
+	pHciPalInfo = (ar6k_hci_pal_info_t *)hdev->driver_data;   
+	A_ASSERT(pHciPalInfo != NULL);
+	ar = pHciPalInfo->ar;
+
+	PRIN_LOG("+btpal_send_frame type: %d \n",bt_cb(skb)->pkt_type);
+	type = HCI_COMMAND_TYPE;
+
+	switch (bt_cb(skb)->pkt_type) {
+		case HCI_COMMAND_PKT:
+			type = HCI_COMMAND_TYPE;
+			hdev->stat.cmd_tx++;
+			break;
+
+		case HCI_ACLDATA_PKT:
+			type = HCI_ACL_TYPE;
+			hdev->stat.acl_tx++;
+			break;
+
+		case HCI_SCODATA_PKT:
+			/* we don't support SCO over the pal */
+			kfree_skb(skb);
+			return 0;
+		default:
+			A_ASSERT(FALSE);
+			kfree_skb(skb);
+			return 0;
+	} 
+
+	if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_HCI_DUMP)) {
+		A_PRINTF(">>> Send HCI %s packet len: %d\n",
+				(type == HCI_COMMAND_TYPE) ? "COMMAND" : "ACL",
+				skb->len);
+		if (type == HCI_COMMAND_TYPE) {
+			PRIN_LOG("    HCI Command: OGF:0x%X OCF:0x%X \r\n", 
+					HCI_GET_OP_CODE(skb-data) >> 10, HCI_GET_OP_CODE(skb-data) & 0x3FF);
+		}
+		AR_DEBUG_PRINTBUF(skb->data,skb->len,"BT HCI SEND Packet Dump");
+	}
+
+	do {
+		if(type == HCI_COMMAND_TYPE)
+		{
+			PRIN_LOG("HCI command");
+
+			if (ar->arWmiReady == FALSE)
+			{
+				PRIN_LOG("WMI not ready ");
+				break;
+			}
+
+			if (wmi_send_hci_cmd(ar->arWmi, skb->data, skb->len) != A_OK)
+			{
+				PRIN_LOG("send hci cmd error");
+				break;
+			}
+		}
+		else if(type == HCI_ACL_TYPE)
+		{
+			void *osbuf;
+
+			PRIN_LOG("ACL data");
+			if (ar->arWmiReady == FALSE)
+			{
+				PRIN_LOG("WMI not ready");
+				break;
+			}
+
+			/* need to add WMI header so allocate a skb with more space */
+			txSkb = bt_skb_alloc(TX_PACKET_RSV_OFFSET + WMI_MAX_TX_META_SZ + 
+					sizeof(WMI_DATA_HDR) + skb->len, 
+					GFP_ATOMIC);
+
+			if (txSkb == NULL) {
+				status = A_NO_MEMORY;
+				PRIN_LOG("No memory");
+				break;
+			}
+
+			bt_cb(txSkb)->pkt_type = bt_cb(skb)->pkt_type;
+			txSkb->dev = (void *)pHciPalInfo->hdev;
+			skb_reserve(txSkb, TX_PACKET_RSV_OFFSET + WMI_MAX_TX_META_SZ + sizeof(WMI_DATA_HDR));
+			A_MEMCPY(txSkb->data, skb->data, skb->len);
+			skb_put(txSkb,skb->len);
+			/* Add WMI packet type */
+			osbuf = (void *)txSkb;
+
+			if (wmi_data_hdr_add(ar->arWmi, osbuf, DATA_MSGTYPE, 0, WMI_DATA_HDR_DATA_TYPE_ACL,0,NULL) != A_OK) {
+				PRIN_LOG("XIOCTL_ACL_DATA - wmi_data_hdr_add failed\n");
+			} else {
+				/* Send data buffer over HTC */
+				PRIN_LOG("acl data tx");
+				ar6000_acl_data_tx(osbuf, ar->arNetDev);
+			}
+			txSkb = NULL;
+		}
+	} while (FALSE);
+
+	if (txSkb != NULL) {
+		PRIN_LOG("Free skb");
+		kfree_skb(txSkb);    
+	}
+	kfree_skb(skb);        
+	return 0;
+}
+
+
+/***********************************************
+ * Unregister HCI device and free HCI device info
+ ***********************************************/
+static void bt_cleanup_hci_pal(ar6k_hci_pal_info_t *pHciPalInfo)
+{   
+	int err;      
+
+	if (bt_check_bit(pHciPalInfo->ulFlags, HCI_REGISTERED)) {
+		bt_clear_bit(pHciPalInfo->ulFlags, HCI_REGISTERED);
+		clear_bit(HCI_RUNNING, &pHciPalInfo->hdev->flags);
+		clear_bit(HCI_UP, &pHciPalInfo->hdev->flags);
+		clear_bit(HCI_INIT, &pHciPalInfo->hdev->flags);   
+		A_ASSERT(pHciPalInfo->hdev != NULL);
+		/* unregister */
+		PRIN_LOG("Unregister PAL device");
+		if ((err = hci_unregister_dev(pHciPalInfo->hdev)) < 0) {
+			PRIN_LOG("HCI PAL: failed to unregister with bluetooth %d\n",err);
+		}          
+	}
+
+	if (pHciPalInfo->hdev != NULL) {
+		kfree(pHciPalInfo->hdev);
+		pHciPalInfo->hdev = NULL;
+	}
+}
+
+/*********************************************************
+ * Allocate HCI device and store in PAL private info structure.
+ *********************************************************/
+static A_STATUS bt_setup_hci_pal(ar6k_hci_pal_info_t *pHciPalInfo)
+{
+	A_STATUS status = A_OK;
+	struct hci_dev *pHciDev = NULL;
+
+	if (!setupbtdev) {
+		return A_OK;    
+	} 
+
+	do {
+		/* allocate a BT HCI struct for this device */
+		pHciDev = hci_alloc_dev();
+		if (NULL == pHciDev) {
+			PRIN_LOG("HCI PAL driver - failed to allocate BT HCI struct \n");
+			status = A_NO_MEMORY;
+			break;
+		}    
+
+		/* save the device, we'll register this later */
+		pHciPalInfo->hdev = pHciDev;       
+                SET_HCI_BUS_TYPE(pHciDev, HCI_VIRTUAL, HCI_80211);
+		pHciDev->driver_data = pHciPalInfo;
+		pHciDev->open     = bt_open;
+		pHciDev->close    = bt_close;
+		pHciDev->send     = btpal_send_frame;
+		pHciDev->ioctl    = bt_ioctl;
+		pHciDev->flush    = bt_flush;
+		pHciDev->destruct = bt_destruct;
+		pHciDev->owner = THIS_MODULE; 
+		/* driver is running in normal BT mode */
+		PRIN_LOG("Normal mode enabled");
+		bt_set_bit(pHciPalInfo->ulFlags, HCI_NORMAL_MODE);
+
+	} while (FALSE);
+
+	if (A_FAILED(status)) {
+		bt_cleanup_hci_pal(pHciPalInfo);    
+	}
+	return status;
+}
+
+/**********************************************
+ * Cleanup HCI device and free HCI PAL private info
+ *********************************************/
+void ar6k_cleanup_hci_pal(void *ar_p)
+{
+	AR_SOFTC_T *ar = (AR_SOFTC_T *)ar_p;
+	ar6k_hci_pal_info_t *pHciPalInfo = (ar6k_hci_pal_info_t *)ar->hcipal_info;
+
+	if (pHciPalInfo != NULL) {
+		bt_cleanup_hci_pal(pHciPalInfo);   
+		A_FREE(pHciPalInfo);
+		ar->hcipal_info = NULL;
+	}
+}
+
+/****************************
+ *  Register HCI device
+ ****************************/
+static A_BOOL ar6k_pal_transport_ready(void *pHciPal)
+{
+	ar6k_hci_pal_info_t *pHciPalInfo = (ar6k_hci_pal_info_t *)pHciPal;
+
+	PRIN_LOG("HCI device transport ready");
+	if(pHciPalInfo == NULL)
+		return FALSE;
+
+	if (hci_register_dev(pHciPalInfo->hdev) < 0) {
+		PRIN_LOG("Can't register HCI device");
+		hci_free_dev(pHciPalInfo->hdev);
+		return FALSE;
+	}
+	PRIN_LOG("HCI device registered");
+	pHciPalInfo->ulFlags |= HCI_REGISTERED;
+	return TRUE;
+}
+
+/**************************************************
+ * Called from ar6k driver when command or ACL data 
+ * packet is received. Pass the packet to bluetooth
+ * stack via hci_recv_frame.
+ **************************************************/
+A_BOOL ar6k_pal_recv_pkt(void *pHciPal, void *osbuf)
+{
+	struct sk_buff *skb = (struct sk_buff *)osbuf;
+	ar6k_hci_pal_info_t *pHciPalInfo;
+	A_BOOL success = FALSE;
+	A_UINT8 btType = 0;
+	pHciPalInfo = (ar6k_hci_pal_info_t *)pHciPal;
+
+	do {
+
+		/* if normal mode is not enabled pass on to the stack
+		 * by returning failure */
+		if(!(pHciPalInfo->ulFlags & HCI_NORMAL_MODE))
+		{
+			PRIN_LOG("Normal mode not enabled");
+			break;
+		}
+
+		if (!test_bit(HCI_RUNNING, &pHciPalInfo->hdev->flags)) {
+			PRIN_LOG("HCI PAL: HCI - not running\n");
+			break;
+		}
+
+		if(*((short *)A_NETBUF_DATA(skb)) == WMI_ACL_DATA_EVENTID)
+			btType = HCI_ACLDATA_PKT;
+		else
+			btType = HCI_EVENT_PKT;
+		/* pull 4 bytes which contains WMI packet type */
+		A_NETBUF_PULL(skb, sizeof(int));
+		bt_cb(skb)->pkt_type = btType;
+		skb->dev = (void *)pHciPalInfo->hdev;
+
+		/* pass the received event packet up the stack */    
+		if (hci_recv_frame(skb) != 0) {
+			PRIN_LOG("HCI PAL: hci_recv_frame failed \n");
+			break;
+		} else {
+			PRIN_LOG("HCI PAL: Indicated RCV of type:%d, Length:%d \n",HCI_EVENT_PKT, skb->len);
+		}
+		PRIN_LOG("hci recv success");
+		success = TRUE;
+	}while(FALSE);
+	return success;
+}
+
+/**********************************************************
+ * HCI PAL init function called from ar6k when it is loaded..
+ * Allocates PAL private info, stores the same in ar6k private info.
+ * Registers a HCI device.
+ * Registers packet receive callback function with ar6k 
+ **********************************************************/
+A_STATUS ar6k_setup_hci_pal(void *ar_p)
+{
+	A_STATUS status = A_OK;
+	ar6k_hci_pal_info_t *pHciPalInfo;
+	ar6k_pal_config_t ar6k_pal_config;
+	AR_SOFTC_T *ar = (AR_SOFTC_T *)ar_p;
+
+	do {
+
+		pHciPalInfo = (ar6k_hci_pal_info_t *)A_MALLOC(sizeof(ar6k_hci_pal_info_t));
+
+		if (NULL == pHciPalInfo) {
+			status = A_NO_MEMORY;
+			break;    
+		}
+
+		A_MEMZERO(pHciPalInfo, sizeof(ar6k_hci_pal_info_t));
+		ar->hcipal_info = pHciPalInfo;
+		pHciPalInfo->ar = ar;
+
+		status = bt_setup_hci_pal(pHciPalInfo);
+		if (A_FAILED(status)) {
+			break;    
+		}
+
+		if(bt_check_bit(pHciPalInfo->ulFlags, HCI_NORMAL_MODE))
+			PRIN_LOG("HCI PAL: running in normal mode... \n");    
+		else 
+			PRIN_LOG("HCI PAL: running in test mode... \n");     
+
+		ar6k_pal_config.fpar6k_pal_recv_pkt = ar6k_pal_recv_pkt;
+		register_pal_cb(&ar6k_pal_config);
+		ar6k_pal_transport_ready(ar->hcipal_info);
+	} while (FALSE);
+
+	if (A_FAILED(status)) {
+		ar6k_cleanup_hci_pal(ar);    
+	}
+	return status;
+}
+#else  /* AR6K_ENABLE_HCI_PAL */
+A_STATUS ar6k_setup_hci_pal(void *ar_p)
+{
+	return A_OK;
+}
+void ar6k_cleanup_hci_pal(void *ar_p)
+{
+}
+#endif /* AR6K_ENABLE_HCI_PAL */
+
+#ifdef EXPORT_HCI_PAL_INTERFACE
+/*****************************************************
+ * Register init and callback function with ar6k
+ * when PAL driver is a separate kernel module.
+ ****************************************************/
+A_STATUS ar6k_register_hci_pal(HCI_TRANSPORT_CALLBACKS *hciTransCallbacks);
+static int __init pal_init_module(void)
+{
+	HCI_TRANSPORT_CALLBACKS hciTransCallbacks;
+
+	hciTransCallbacks.setupTransport = ar6k_setup_hci_pal;
+	hciTransCallbacks.cleanupTransport = ar6k_cleanup_hci_pal;
+
+	if(ar6k_register_hci_pal(&hciTransCallbacks) != A_OK)
+		return -ENODEV;
+
+	return 0;
+}
+
+static void __exit pal_cleanup_module(void)
+{
+}
+
+module_init(pal_init_module);
+module_exit(pal_cleanup_module);
+MODULE_LICENSE("Dual BSD/GPL");
+#endif
diff --git a/drivers/net/ath6kl/os/linux/cfg80211.c b/drivers/net/ath6kl/os/linux/cfg80211.c
new file mode 100644
index 00000000000..7269d0a1d61
--- /dev/null
+++ b/drivers/net/ath6kl/os/linux/cfg80211.c
@@ -0,0 +1,1471 @@
+//------------------------------------------------------------------------------
+// Copyright (c) 2004-2010 Atheros Communications Inc.
+// All rights reserved.
+//
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//
+// Author(s): ="Atheros"
+//------------------------------------------------------------------------------
+
+#include <linux/wireless.h>
+#include <linux/ieee80211.h>
+#include <net/cfg80211.h>
+
+#include "ar6000_drv.h"
+
+
+extern A_WAITQUEUE_HEAD arEvent;
+extern unsigned int wmitimeout;
+extern int reconnect_flag;
+
+
+#define RATETAB_ENT(_rate, _rateid, _flags) {   \
+    .bitrate    = (_rate),                  \
+    .flags      = (_flags),                 \
+    .hw_value   = (_rateid),                \
+}
+
+#define CHAN2G(_channel, _freq, _flags) {   \
+    .band           = IEEE80211_BAND_2GHZ,  \
+    .hw_value       = (_channel),           \
+    .center_freq    = (_freq),              \
+    .flags          = (_flags),             \
+    .max_antenna_gain   = 0,                \
+    .max_power      = 30,                   \
+}
+
+#define CHAN5G(_channel, _flags) {              \
+    .band           = IEEE80211_BAND_5GHZ,      \
+    .hw_value       = (_channel),               \
+    .center_freq    = 5000 + (5 * (_channel)),  \
+    .flags          = (_flags),                 \
+    .max_antenna_gain   = 0,                    \
+    .max_power      = 30,                       \
+}
+
+static struct
+ieee80211_rate ar6k_rates[] = {
+    RATETAB_ENT(10,  0x1,   0),
+    RATETAB_ENT(20,  0x2,   0),
+    RATETAB_ENT(55,  0x4,   0),
+    RATETAB_ENT(110, 0x8,   0),
+    RATETAB_ENT(60,  0x10,  0),
+    RATETAB_ENT(90,  0x20,  0),
+    RATETAB_ENT(120, 0x40,  0),
+    RATETAB_ENT(180, 0x80,  0),
+    RATETAB_ENT(240, 0x100, 0),
+    RATETAB_ENT(360, 0x200, 0),
+    RATETAB_ENT(480, 0x400, 0),
+    RATETAB_ENT(540, 0x800, 0),
+};
+
+#define ar6k_a_rates     (ar6k_rates + 4)
+#define ar6k_a_rates_size    8
+#define ar6k_g_rates     (ar6k_rates + 0)
+#define ar6k_g_rates_size    12
+
+static struct
+ieee80211_channel ar6k_2ghz_channels[] = {
+    CHAN2G(1, 2412, 0),
+    CHAN2G(2, 2417, 0),
+    CHAN2G(3, 2422, 0),
+    CHAN2G(4, 2427, 0),
+    CHAN2G(5, 2432, 0),
+    CHAN2G(6, 2437, 0),
+    CHAN2G(7, 2442, 0),
+    CHAN2G(8, 2447, 0),
+    CHAN2G(9, 2452, 0),
+    CHAN2G(10, 2457, 0),
+    CHAN2G(11, 2462, 0),
+    CHAN2G(12, 2467, 0),
+    CHAN2G(13, 2472, 0),
+    CHAN2G(14, 2484, 0),
+};
+
+static struct
+ieee80211_channel ar6k_5ghz_a_channels[] = {
+    CHAN5G(34, 0),      CHAN5G(36, 0),
+    CHAN5G(38, 0),      CHAN5G(40, 0),
+    CHAN5G(42, 0),      CHAN5G(44, 0),
+    CHAN5G(46, 0),      CHAN5G(48, 0),
+    CHAN5G(52, 0),      CHAN5G(56, 0),
+    CHAN5G(60, 0),      CHAN5G(64, 0),
+    CHAN5G(100, 0),     CHAN5G(104, 0),
+    CHAN5G(108, 0),     CHAN5G(112, 0),
+    CHAN5G(116, 0),     CHAN5G(120, 0),
+    CHAN5G(124, 0),     CHAN5G(128, 0),
+    CHAN5G(132, 0),     CHAN5G(136, 0),
+    CHAN5G(140, 0),     CHAN5G(149, 0),
+    CHAN5G(153, 0),     CHAN5G(157, 0),
+    CHAN5G(161, 0),     CHAN5G(165, 0),
+    CHAN5G(184, 0),     CHAN5G(188, 0),
+    CHAN5G(192, 0),     CHAN5G(196, 0),
+    CHAN5G(200, 0),     CHAN5G(204, 0),
+    CHAN5G(208, 0),     CHAN5G(212, 0),
+    CHAN5G(216, 0),
+};
+
+static struct
+ieee80211_supported_band ar6k_band_2ghz = {
+    .n_channels = ARRAY_SIZE(ar6k_2ghz_channels),
+    .channels = ar6k_2ghz_channels,
+    .n_bitrates = ar6k_g_rates_size,
+    .bitrates = ar6k_g_rates,
+};
+
+static struct
+ieee80211_supported_band ar6k_band_5ghz = {
+    .n_channels = ARRAY_SIZE(ar6k_5ghz_a_channels),
+    .channels = ar6k_5ghz_a_channels,
+    .n_bitrates = ar6k_a_rates_size,
+    .bitrates = ar6k_a_rates,
+};
+
+static int
+ar6k_set_wpa_version(AR_SOFTC_T *ar, enum nl80211_wpa_versions wpa_version)
+{
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: %u\n", __func__, wpa_version));
+
+    if (!wpa_version) {
+        ar->arAuthMode = NONE_AUTH;
+    } else if (wpa_version & NL80211_WPA_VERSION_1) {
+        ar->arAuthMode = WPA_AUTH;
+    } else if (wpa_version & NL80211_WPA_VERSION_2) {
+        ar->arAuthMode = WPA2_AUTH;
+    } else {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                        ("%s: %u not spported\n", __func__, wpa_version));
+        return -ENOTSUPP;
+    }
+
+    return A_OK;
+}
+
+static int
+ar6k_set_auth_type(AR_SOFTC_T *ar, enum nl80211_auth_type auth_type)
+{
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: 0x%x\n", __func__, auth_type));
+
+    switch (auth_type) {
+    case NL80211_AUTHTYPE_OPEN_SYSTEM:
+        ar->arDot11AuthMode = OPEN_AUTH;
+        break;
+    case NL80211_AUTHTYPE_SHARED_KEY:
+        ar->arDot11AuthMode = SHARED_AUTH;
+        break;
+    case NL80211_AUTHTYPE_NETWORK_EAP:
+        ar->arDot11AuthMode = LEAP_AUTH;
+        break;
+    default:
+        ar->arDot11AuthMode = OPEN_AUTH;
+        AR_DEBUG_PRINTF(ATH_DEBUG_INFO,
+                        ("%s: 0x%x not spported\n", __func__, auth_type));
+        return -ENOTSUPP;
+    }
+
+    return A_OK;
+}
+
+static int
+ar6k_set_cipher(AR_SOFTC_T *ar, A_UINT32 cipher, A_BOOL ucast)
+{
+    A_UINT8  *ar_cipher = ucast ? &ar->arPairwiseCrypto :
+                                &ar->arGroupCrypto;
+    A_UINT8  *ar_cipher_len = ucast ? &ar->arPairwiseCryptoLen :
+                                    &ar->arGroupCryptoLen;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO,
+                    ("%s: cipher 0x%x, ucast %u\n", __func__, cipher, ucast));
+
+    switch (cipher) {
+    case 0:
+    case IW_AUTH_CIPHER_NONE:
+        *ar_cipher = NONE_CRYPT;
+        *ar_cipher_len = 0;
+        break;
+    case WLAN_CIPHER_SUITE_WEP40:
+        *ar_cipher = WEP_CRYPT;
+        *ar_cipher_len = 5;
+        break;
+    case WLAN_CIPHER_SUITE_WEP104:
+        *ar_cipher = WEP_CRYPT;
+        *ar_cipher_len = 13;
+        break;
+    case WLAN_CIPHER_SUITE_TKIP:
+        *ar_cipher = TKIP_CRYPT;
+        *ar_cipher_len = 0;
+        break;
+    case WLAN_CIPHER_SUITE_CCMP:
+        *ar_cipher = AES_CRYPT;
+        *ar_cipher_len = 0;
+        break;
+    default:
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                        ("%s: cipher 0x%x not supported\n", __func__, cipher));
+        return -ENOTSUPP;
+    }
+
+    return A_OK;
+}
+
+static void
+ar6k_set_key_mgmt(AR_SOFTC_T *ar, A_UINT32 key_mgmt)
+{
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: 0x%x\n", __func__, key_mgmt));
+
+    if (WLAN_AKM_SUITE_PSK == key_mgmt) {
+        if (WPA_AUTH == ar->arAuthMode) {
+            ar->arAuthMode = WPA_PSK_AUTH;
+        } else if (WPA2_AUTH == ar->arAuthMode) {
+            ar->arAuthMode = WPA2_PSK_AUTH;
+        }
+    } else if (WLAN_AKM_SUITE_8021X != key_mgmt) {
+        ar->arAuthMode = NONE_AUTH;
+    }
+}
+
+static int
+ar6k_cfg80211_connect(struct wiphy *wiphy, struct net_device *dev,
+                      struct cfg80211_connect_params *sme)
+{
+    AR_SOFTC_T *ar = ar6k_priv(dev);
+    A_STATUS status;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: \n", __func__));
+
+    if(ar->arWmiReady == FALSE) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wmi not ready yet\n", __func__));
+        return -EIO;
+    }
+
+    if(ar->arWlanState == WLAN_DISABLED) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wlan disabled\n", __func__));
+        return -EIO;
+    }
+
+    if(ar->bIsDestroyProgress) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: destroy in progress\n", __func__));
+        return -EBUSY;
+    }
+
+    if(!sme->ssid_len || IEEE80211_MAX_SSID_LEN < sme->ssid_len) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: ssid invalid\n", __func__));
+        return -EINVAL;
+    }
+
+    if(ar->arSkipScan == TRUE &&
+       ((sme->channel && sme->channel->center_freq == 0) ||
+        (sme->bssid && !sme->bssid[0] && !sme->bssid[1] && !sme->bssid[2] &&
+         !sme->bssid[3] && !sme->bssid[4] && !sme->bssid[5])))
+    {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s:SkipScan: channel or bssid invalid\n", __func__));
+        return -EINVAL;
+    }
+
+    if(down_interruptible(&ar->arSem)) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: busy, couldn't get access\n", __func__));
+        return -ERESTARTSYS;
+    }
+
+    if(ar->bIsDestroyProgress) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: busy, destroy in progress\n", __func__));
+        up(&ar->arSem);
+        return -EBUSY;
+    }
+
+    if(ar->arTxPending[wmi_get_control_ep(ar->arWmi)]) {
+        /*
+        * sleep until the command queue drains
+        */
+        wait_event_interruptible_timeout(arEvent,
+        ar->arTxPending[wmi_get_control_ep(ar->arWmi)] == 0, wmitimeout * HZ);
+        if (signal_pending(current)) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: cmd queue drain timeout\n", __func__));
+            up(&ar->arSem);
+            return -EINTR;
+        }
+    }
+
+    if(ar->arConnected == TRUE &&
+       ar->arSsidLen == sme->ssid_len &&
+       !A_MEMCMP(ar->arSsid, sme->ssid, ar->arSsidLen)) {
+        reconnect_flag = TRUE;
+        status = wmi_reconnect_cmd(ar->arWmi,
+                                   ar->arReqBssid,
+                                   ar->arChannelHint);
+
+        up(&ar->arSem);
+        if (status != A_OK) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: wmi_reconnect_cmd failed\n", __func__));
+            return -EIO;
+        }
+        return 0;
+    } else if(ar->arSsidLen == sme->ssid_len &&
+              !A_MEMCMP(ar->arSsid, sme->ssid, ar->arSsidLen)) {
+	    wmi_disconnect_cmd(ar->arWmi);
+    }
+
+    A_MEMZERO(ar->arSsid, sizeof(ar->arSsid));
+    ar->arSsidLen = sme->ssid_len;
+    A_MEMCPY(ar->arSsid, sme->ssid, sme->ssid_len);
+
+    if(sme->channel){
+        ar->arChannelHint = sme->channel->center_freq;
+    }
+
+    A_MEMZERO(ar->arReqBssid, sizeof(ar->arReqBssid));
+    if(sme->bssid){
+        if(A_MEMCMP(&sme->bssid, bcast_mac, AR6000_ETH_ADDR_LEN)) {
+            A_MEMCPY(ar->arReqBssid, sme->bssid, sizeof(ar->arReqBssid));
+        }
+    }
+
+    ar6k_set_wpa_version(ar, sme->crypto.wpa_versions);
+    ar6k_set_auth_type(ar, sme->auth_type);
+
+    if(sme->crypto.n_ciphers_pairwise) {
+        ar6k_set_cipher(ar, sme->crypto.ciphers_pairwise[0], true);
+    } else {
+        ar6k_set_cipher(ar, IW_AUTH_CIPHER_NONE, true);
+    }
+    ar6k_set_cipher(ar, sme->crypto.cipher_group, false);
+
+    if(sme->crypto.n_akm_suites) {
+        ar6k_set_key_mgmt(ar, sme->crypto.akm_suites[0]);
+    }
+
+    if((sme->key_len) &&
+       (NONE_AUTH == ar->arAuthMode) &&
+        (WEP_CRYPT == ar->arPairwiseCrypto)) {
+        struct ar_key *key = NULL;
+
+        if(sme->key_idx < WMI_MIN_KEY_INDEX || sme->key_idx > WMI_MAX_KEY_INDEX) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                            ("%s: key index %d out of bounds\n", __func__, sme->key_idx));
+            up(&ar->arSem);
+            return -ENOENT;
+        }
+
+        key = &ar->keys[sme->key_idx];
+        key->key_len = sme->key_len;
+        A_MEMCPY(key->key, sme->key, key->key_len);
+        key->cipher = ar->arPairwiseCrypto;
+        ar->arDefTxKeyIndex = sme->key_idx;
+
+        wmi_addKey_cmd(ar->arWmi, sme->key_idx,
+                    ar->arPairwiseCrypto,
+                    GROUP_USAGE | TX_USAGE,
+                    key->key_len,
+                    NULL,
+                    key->key, KEY_OP_INIT_VAL, NULL,
+                    NO_SYNC_WMIFLAG);
+    }
+
+    if (!ar->arUserBssFilter) {
+        if (wmi_bssfilter_cmd(ar->arWmi, ALL_BSS_FILTER, 0) != A_OK) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Couldn't set bss filtering\n", __func__));
+            up(&ar->arSem);
+            return -EIO;
+        }
+    }
+
+    ar->arNetworkType = ar->arNextMode;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: Connect called with authmode %d dot11 auth %d"\
+                    " PW crypto %d PW crypto Len %d GRP crypto %d"\
+                    " GRP crypto Len %d channel hint %u\n",
+                    __func__, ar->arAuthMode, ar->arDot11AuthMode,
+                    ar->arPairwiseCrypto, ar->arPairwiseCryptoLen,
+                    ar->arGroupCrypto, ar->arGroupCryptoLen, ar->arChannelHint));
+
+    reconnect_flag = 0;
+    status = wmi_connect_cmd(ar->arWmi, ar->arNetworkType,
+                            ar->arDot11AuthMode, ar->arAuthMode,
+                            ar->arPairwiseCrypto, ar->arPairwiseCryptoLen,
+                            ar->arGroupCrypto,ar->arGroupCryptoLen,
+                            ar->arSsidLen, ar->arSsid,
+                            ar->arReqBssid, ar->arChannelHint,
+                            ar->arConnectCtrlFlags);
+
+    up(&ar->arSem);
+
+    if (A_EINVAL == status) {
+        A_MEMZERO(ar->arSsid, sizeof(ar->arSsid));
+        ar->arSsidLen = 0;
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Invalid request\n", __func__));
+        return -ENOENT;
+    } else if (status != A_OK) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: wmi_connect_cmd failed\n", __func__));
+        return -EIO;
+    }
+
+    if ((!(ar->arConnectCtrlFlags & CONNECT_DO_WPA_OFFLOAD)) &&
+        ((WPA_PSK_AUTH == ar->arAuthMode) || (WPA2_PSK_AUTH == ar->arAuthMode)))
+    {
+        A_TIMEOUT_MS(&ar->disconnect_timer, A_DISCONNECT_TIMER_INTERVAL, 0);
+    }
+
+    ar->arConnectCtrlFlags &= ~CONNECT_DO_WPA_OFFLOAD;
+    ar->arConnectPending = TRUE;
+
+    return 0;
+}
+
+void
+ar6k_cfg80211_connect_event(AR_SOFTC_T *ar, A_UINT16 channel,
+                A_UINT8 *bssid, A_UINT16 listenInterval,
+                A_UINT16 beaconInterval,NETWORK_TYPE networkType,
+                A_UINT8 beaconIeLen, A_UINT8 assocReqLen,
+                A_UINT8 assocRespLen, A_UINT8 *assocInfo)
+{
+    A_UINT16 size = 0;
+    A_UINT16 capability = 0;
+    struct cfg80211_bss *bss = NULL;
+    struct ieee80211_mgmt *mgmt = NULL;
+    struct ieee80211_channel *ibss_channel = NULL;
+    s32 signal = 50 * 100;
+    A_UINT8 ie_buf_len = 0;
+    unsigned char ie_buf[256];
+    unsigned char *ptr_ie_buf = ie_buf;
+    unsigned char *ieeemgmtbuf = NULL;
+    A_UINT8 source_mac[ATH_MAC_LEN];
+
+    A_UINT8 assocReqIeOffset = sizeof(A_UINT16)  +  /* capinfo*/
+                               sizeof(A_UINT16);    /* listen interval */
+    A_UINT8 assocRespIeOffset = sizeof(A_UINT16) +  /* capinfo*/
+                                sizeof(A_UINT16) +  /* status Code */
+                                sizeof(A_UINT16);   /* associd */
+    A_UINT8 *assocReqIe = assocInfo + beaconIeLen + assocReqIeOffset;
+    A_UINT8 *assocRespIe = assocInfo + beaconIeLen + assocReqLen + assocRespIeOffset;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: \n", __func__));
+
+    assocReqLen -= assocReqIeOffset;
+    assocRespLen -= assocRespIeOffset;
+
+    if((ADHOC_NETWORK & networkType)) {
+        if(NL80211_IFTYPE_ADHOC != ar->wdev->iftype) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_INFO,
+                            ("%s: ath6k not in ibss mode\n", __func__));
+            return;
+        }
+    }
+
+    if((INFRA_NETWORK & networkType)) {
+        if(NL80211_IFTYPE_STATION != ar->wdev->iftype) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_INFO,
+                            ("%s: ath6k not in station mode\n", __func__));
+            return;
+        }
+    }
+
+    /* Before informing the join/connect event, make sure that
+     * bss entry is present in scan list, if it not present
+     * construct and insert into scan list, otherwise that
+     * event will be dropped on the way by cfg80211, due to
+     * this keys will not be plumbed in case of WEP and
+     * application will not be aware of join/connect status. */
+    bss = cfg80211_get_bss(ar->wdev->wiphy, NULL, bssid,
+                           ar->wdev->ssid, ar->wdev->ssid_len,
+                           ((ADHOC_NETWORK & networkType) ? WLAN_CAPABILITY_IBSS : WLAN_CAPABILITY_ESS),
+                           ((ADHOC_NETWORK & networkType) ? WLAN_CAPABILITY_IBSS : WLAN_CAPABILITY_ESS));
+
+    if(!bss) {
+        if (ADHOC_NETWORK & networkType) {
+            /* construct 802.11 mgmt beacon */
+            if(ptr_ie_buf) {
+                *ptr_ie_buf++ = WLAN_EID_SSID;
+                *ptr_ie_buf++ = ar->arSsidLen;
+                A_MEMCPY(ptr_ie_buf, ar->arSsid, ar->arSsidLen);
+                ptr_ie_buf +=ar->arSsidLen;
+
+                *ptr_ie_buf++ = WLAN_EID_IBSS_PARAMS;
+                *ptr_ie_buf++ = 2; /* length */
+                *ptr_ie_buf++ = 0; /* ATIM window */
+                *ptr_ie_buf++ = 0; /* ATIM window */
+
+                /* TODO: update ibss params and include supported rates,
+                 * DS param set, extened support rates, wmm. */
+
+                ie_buf_len = ptr_ie_buf - ie_buf;
+            }
+
+            capability |= IEEE80211_CAPINFO_IBSS;
+            if(WEP_CRYPT == ar->arPairwiseCrypto) {
+                capability |= IEEE80211_CAPINFO_PRIVACY;
+            }
+            A_MEMCPY(source_mac, ar->arNetDev->dev_addr, ATH_MAC_LEN);
+            ptr_ie_buf = ie_buf;
+        } else {
+            capability = *(A_UINT16 *)(&assocInfo[beaconIeLen]);
+            A_MEMCPY(source_mac, bssid, ATH_MAC_LEN);
+            ptr_ie_buf = assocReqIe;
+            ie_buf_len = assocReqLen;
+        }
+
+        size = offsetof(struct ieee80211_mgmt, u)
+             + sizeof(mgmt->u.beacon)
+             + ie_buf_len;
+
+        ieeemgmtbuf = A_MALLOC_NOWAIT(size);
+        if(!ieeemgmtbuf) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                            ("%s: ieeeMgmtbuf alloc error\n", __func__));
+            return;
+        }
+
+        A_MEMZERO(ieeemgmtbuf, size);
+        mgmt = (struct ieee80211_mgmt *)ieeemgmtbuf;
+        mgmt->frame_control = (IEEE80211_FTYPE_MGMT | IEEE80211_STYPE_BEACON);
+        A_MEMCPY(mgmt->da, bcast_mac, ATH_MAC_LEN);
+        A_MEMCPY(mgmt->sa, source_mac, ATH_MAC_LEN);
+        A_MEMCPY(mgmt->bssid, bssid, ATH_MAC_LEN);
+        mgmt->u.beacon.beacon_int = beaconInterval;
+        mgmt->u.beacon.capab_info = capability;
+        A_MEMCPY(mgmt->u.beacon.variable, ptr_ie_buf, ie_buf_len);
+
+        ibss_channel = ieee80211_get_channel(ar->wdev->wiphy, (int)channel);
+
+	AR_DEBUG_PRINTF(ATH_DEBUG_INFO,
+		("%s: inform bss with bssid %pM channel %d beaconInterval %d "
+			"capability 0x%x\n", __func__, mgmt->bssid,
+			ibss_channel->hw_value, beaconInterval, capability));
+
+        bss = cfg80211_inform_bss_frame(ar->wdev->wiphy,
+                                        ibss_channel, mgmt,
+                                        le16_to_cpu(size),
+                                        signal, GFP_KERNEL);
+        A_FREE(ieeemgmtbuf);
+        cfg80211_put_bss(bss);
+    }
+
+    if((ADHOC_NETWORK & networkType)) {
+        cfg80211_ibss_joined(ar->arNetDev, bssid, GFP_KERNEL);
+        return;
+    }
+
+    if (FALSE == ar->arConnected) {
+        /* inform connect result to cfg80211 */
+        cfg80211_connect_result(ar->arNetDev, bssid,
+                                assocReqIe, assocReqLen,
+                                assocRespIe, assocRespLen,
+                                WLAN_STATUS_SUCCESS, GFP_KERNEL);
+    } else {
+        /* inform roam event to cfg80211 */
+        cfg80211_roamed(ar->arNetDev, bssid,
+                        assocReqIe, assocReqLen,
+                        assocRespIe, assocRespLen,
+                        GFP_KERNEL);
+    }
+}
+
+static int
+ar6k_cfg80211_disconnect(struct wiphy *wiphy, struct net_device *dev,
+                        A_UINT16 reason_code)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: reason=%u\n", __func__, reason_code));
+
+    if(ar->arWmiReady == FALSE) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wmi not ready\n", __func__));
+        return -EIO;
+    }
+
+    if(ar->arWlanState == WLAN_DISABLED) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wlan disabled\n", __func__));
+        return -EIO;
+    }
+
+    if(ar->bIsDestroyProgress) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: busy, destroy in progress\n", __func__));
+        return -EBUSY;
+    }
+
+    if(down_interruptible(&ar->arSem)) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: busy, couldn't get access\n", __func__));
+        return -ERESTARTSYS;
+    }
+
+    reconnect_flag = 0;
+    wmi_disconnect_cmd(ar->arWmi);
+    A_MEMZERO(ar->arSsid, sizeof(ar->arSsid));
+    ar->arSsidLen = 0;
+
+    if (ar->arSkipScan == FALSE) {
+        A_MEMZERO(ar->arReqBssid, sizeof(ar->arReqBssid));
+    }
+
+    up(&ar->arSem);
+
+    return 0;
+}
+
+void
+ar6k_cfg80211_disconnect_event(AR_SOFTC_T *ar, A_UINT8 reason,
+                               A_UINT8 *bssid, A_UINT8 assocRespLen,
+                               A_UINT8 *assocInfo, A_UINT16 protocolReasonStatus)
+{
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: reason=%u\n", __func__, reason));
+
+    if((ADHOC_NETWORK & ar->arNetworkType)) {
+        if(NL80211_IFTYPE_ADHOC != ar->wdev->iftype) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_INFO,
+                            ("%s: ath6k not in ibss mode\n", __func__));
+            return;
+        }
+        A_MEMZERO(bssid, ETH_ALEN);
+        cfg80211_ibss_joined(ar->arNetDev, bssid, GFP_KERNEL);
+        return;
+    }
+
+    if((INFRA_NETWORK & ar->arNetworkType)) {
+        if(NL80211_IFTYPE_STATION != ar->wdev->iftype) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_INFO,
+                            ("%s: ath6k not in station mode\n", __func__));
+            return;
+        }
+    }
+
+    if(FALSE == ar->arConnected) {
+        if(NO_NETWORK_AVAIL == reason) {
+            /* connect cmd failed */
+            cfg80211_connect_result(ar->arNetDev, bssid,
+                                    NULL, 0,
+                                    NULL, 0,
+                                    WLAN_STATUS_UNSPECIFIED_FAILURE,
+                                    GFP_KERNEL);
+        }
+    } else {
+        /* connection loss due to disconnect cmd or low rssi */
+        cfg80211_disconnected(ar->arNetDev, reason, NULL, 0, GFP_KERNEL);
+    }
+}
+
+void
+ar6k_cfg80211_scan_node(void *arg, bss_t *ni)
+{
+    struct wiphy *wiphy = (struct wiphy *)arg;
+    A_UINT16 size;
+    unsigned char *ieeemgmtbuf = NULL;
+    struct ieee80211_mgmt *mgmt;
+    struct ieee80211_channel *channel;
+    struct ieee80211_supported_band *band;
+    struct ieee80211_common_ie  *cie;
+    s32 signal;
+    int freq;
+
+    cie = &ni->ni_cie;
+
+#define CHAN_IS_11A(x)  (!((x >= 2412) && (x <= 2484)))
+    if(CHAN_IS_11A(cie->ie_chan)) {
+        /* 11a */
+        band = wiphy->bands[IEEE80211_BAND_5GHZ];
+    } else if((cie->ie_erp) || (cie->ie_xrates)) {
+        /* 11g */
+        band = wiphy->bands[IEEE80211_BAND_2GHZ];
+    } else {
+        /* 11b */
+        band = wiphy->bands[IEEE80211_BAND_2GHZ];
+    }
+
+    size = ni->ni_framelen + offsetof(struct ieee80211_mgmt, u);
+    ieeemgmtbuf = A_MALLOC_NOWAIT(size);
+    if(!ieeemgmtbuf)
+    {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: ieeeMgmtbuf alloc error\n", __func__));
+        return;
+    }
+
+    /* Note:
+       TODO: Update target to include 802.11 mac header while sending bss info.
+       Target removes 802.11 mac header while sending the bss info to host,
+       cfg80211 needs it, for time being just filling the da, sa and bssid fields alone.
+    */
+    mgmt = (struct ieee80211_mgmt *)ieeemgmtbuf;
+    A_MEMCPY(mgmt->da, bcast_mac, ATH_MAC_LEN);
+    A_MEMCPY(mgmt->sa, ni->ni_macaddr, ATH_MAC_LEN);
+    A_MEMCPY(mgmt->bssid, ni->ni_macaddr, ATH_MAC_LEN);
+    A_MEMCPY(ieeemgmtbuf + offsetof(struct ieee80211_mgmt, u),
+             ni->ni_buf, ni->ni_framelen);
+
+    freq    = cie->ie_chan;
+    channel = ieee80211_get_channel(wiphy, freq);
+    signal  = ni->ni_snr * 100;
+
+	AR_DEBUG_PRINTF(ATH_DEBUG_INFO,
+		("%s: bssid %pM channel %d freq %d size %d\n", __func__,
+			mgmt->bssid, channel->hw_value, freq, size));
+    cfg80211_inform_bss_frame(wiphy, channel, mgmt,
+                              le16_to_cpu(size),
+                              signal, GFP_KERNEL);
+
+    A_FREE (ieeemgmtbuf);
+}
+
+static int
+ar6k_cfg80211_scan(struct wiphy *wiphy, struct net_device *ndev,
+                   struct cfg80211_scan_request *request)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(ndev);
+    int ret = 0;
+    A_BOOL forceFgScan = FALSE;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: \n", __func__));
+
+    if(ar->arWmiReady == FALSE) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wmi not ready\n", __func__));
+        return -EIO;
+    }
+
+    if(ar->arWlanState == WLAN_DISABLED) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wlan disabled\n", __func__));
+        return -EIO;
+    }
+
+    if (!ar->arUserBssFilter) {
+        if (wmi_bssfilter_cmd(ar->arWmi,
+                             (ar->arConnected ? ALL_BUT_BSS_FILTER : ALL_BSS_FILTER),
+                             0) != A_OK) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Couldn't set bss filtering\n", __func__));
+            return -EIO;
+        }
+    }
+
+    if(request->n_ssids &&
+       request->ssids[0].ssid_len) {
+        A_UINT8 i;
+
+        if(request->n_ssids > MAX_PROBED_SSID_INDEX) {
+            request->n_ssids = MAX_PROBED_SSID_INDEX;
+        }
+
+        for (i = 0; i < request->n_ssids; i++) {
+            wmi_probedSsid_cmd(ar->arWmi, i, SPECIFIC_SSID_FLAG,
+                               request->ssids[i].ssid_len,
+                               request->ssids[i].ssid);
+        }
+    }
+
+    if(ar->arConnected) {
+        forceFgScan = TRUE;
+    }
+
+    if(wmi_startscan_cmd(ar->arWmi, WMI_LONG_SCAN, forceFgScan, FALSE, \
+                         0, 0, 0, NULL) != A_OK) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: wmi_startscan_cmd failed\n", __func__));
+        ret = -EIO;
+    }
+
+    ar->scan_request = request;
+
+    return ret;
+}
+
+void
+ar6k_cfg80211_scanComplete_event(AR_SOFTC_T *ar, A_STATUS status)
+{
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: status %d\n", __func__, status));
+
+    if(ar->scan_request)
+    {
+        /* Translate data to cfg80211 mgmt format */
+        wmi_iterate_nodes(ar->arWmi, ar6k_cfg80211_scan_node, ar->wdev->wiphy);
+
+        cfg80211_scan_done(ar->scan_request,
+                          (status & A_ECANCELED) ? true : false);
+
+        if(ar->scan_request->n_ssids &&
+           ar->scan_request->ssids[0].ssid_len) {
+            A_UINT8 i;
+
+            for (i = 0; i < ar->scan_request->n_ssids; i++) {
+                wmi_probedSsid_cmd(ar->arWmi, i, DISABLE_SSID_FLAG,
+                                   0, NULL);
+            }
+        }
+        ar->scan_request = NULL;
+    }
+}
+
+static int
+ar6k_cfg80211_add_key(struct wiphy *wiphy, struct net_device *ndev,
+                      A_UINT8 key_index, bool pairwise, const A_UINT8 *mac_addr,
+                      struct key_params *params)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(ndev);
+    struct ar_key *key = NULL;
+    A_UINT8 key_usage;
+    A_UINT8 key_type;
+    A_STATUS status = 0;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s:\n", __func__));
+
+    if(ar->arWmiReady == FALSE) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wmi not ready\n", __func__));
+        return -EIO;
+    }
+
+    if(ar->arWlanState == WLAN_DISABLED) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wlan disabled\n", __func__));
+        return -EIO;
+    }
+
+    if(key_index < WMI_MIN_KEY_INDEX || key_index > WMI_MAX_KEY_INDEX) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_INFO,
+                        ("%s: key index %d out of bounds\n", __func__, key_index));
+        return -ENOENT;
+    }
+
+    key = &ar->keys[key_index];
+    A_MEMZERO(key, sizeof(struct ar_key));
+
+    if(!mac_addr || is_broadcast_ether_addr(mac_addr)) {
+        key_usage = GROUP_USAGE;
+    } else {
+        key_usage = PAIRWISE_USAGE;
+    }
+
+    if(params) {
+        if(params->key_len > WLAN_MAX_KEY_LEN ||
+            params->seq_len > IW_ENCODE_SEQ_MAX_SIZE)
+            return -EINVAL;
+
+        key->key_len = params->key_len;
+        A_MEMCPY(key->key, params->key, key->key_len);
+        key->seq_len = params->seq_len;
+        A_MEMCPY(key->seq, params->seq, key->seq_len);
+        key->cipher = params->cipher;
+    }
+
+    switch (key->cipher) {
+    case WLAN_CIPHER_SUITE_WEP40:
+    case WLAN_CIPHER_SUITE_WEP104:
+        key_type = WEP_CRYPT;
+        break;
+
+    case WLAN_CIPHER_SUITE_TKIP:
+        key_type = TKIP_CRYPT;
+        break;
+
+    case WLAN_CIPHER_SUITE_CCMP:
+        key_type = AES_CRYPT;
+        break;
+
+    default:
+        return -ENOTSUPP;
+    }
+
+    if (((WPA_PSK_AUTH == ar->arAuthMode) || (WPA2_PSK_AUTH == ar->arAuthMode)) &&
+        (GROUP_USAGE & key_usage))
+    {
+        A_UNTIMEOUT(&ar->disconnect_timer);
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO,
+                    ("%s: index %d, key_len %d, key_type 0x%x,"\
+                    " key_usage 0x%x, seq_len %d\n",
+                    __func__, key_index, key->key_len, key_type,
+                    key_usage, key->seq_len));
+
+    ar->arDefTxKeyIndex = key_index;
+    status = wmi_addKey_cmd(ar->arWmi, ar->arDefTxKeyIndex, key_type, key_usage,
+                    key->key_len, key->seq, key->key, KEY_OP_INIT_VAL,
+                    (A_UINT8*)mac_addr, SYNC_BOTH_WMIFLAG);
+
+
+    if(status != A_OK) {
+        return -EIO;
+    }
+
+    return 0;
+}
+
+static int
+ar6k_cfg80211_del_key(struct wiphy *wiphy, struct net_device *ndev,
+                      A_UINT8 key_index, bool pairwise, const A_UINT8 *mac_addr)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(ndev);
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: index %d\n", __func__, key_index));
+
+    if(ar->arWmiReady == FALSE) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wmi not ready\n", __func__));
+        return -EIO;
+    }
+
+    if(ar->arWlanState == WLAN_DISABLED) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wlan disabled\n", __func__));
+        return -EIO;
+    }
+
+    if(key_index < WMI_MIN_KEY_INDEX || key_index > WMI_MAX_KEY_INDEX) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_INFO,
+                        ("%s: key index %d out of bounds\n", __func__, key_index));
+        return -ENOENT;
+    }
+
+    if(!ar->keys[key_index].key_len) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: index %d is empty\n", __func__, key_index));
+        return 0;
+    }
+
+    ar->keys[key_index].key_len = 0;
+
+    return wmi_deleteKey_cmd(ar->arWmi, key_index);
+}
+
+
+static int
+ar6k_cfg80211_get_key(struct wiphy *wiphy, struct net_device *ndev,
+                      A_UINT8 key_index, bool pairwise, const A_UINT8 *mac_addr,
+                      void *cookie,
+                      void (*callback)(void *cookie, struct key_params*))
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(ndev);
+    struct ar_key *key = NULL;
+    struct key_params params;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: index %d\n", __func__, key_index));
+
+    if(ar->arWmiReady == FALSE) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wmi not ready\n", __func__));
+        return -EIO;
+    }
+
+    if(ar->arWlanState == WLAN_DISABLED) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wlan disabled\n", __func__));
+        return -EIO;
+    }
+
+    if(key_index < WMI_MIN_KEY_INDEX || key_index > WMI_MAX_KEY_INDEX) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_INFO,
+                        ("%s: key index %d out of bounds\n", __func__, key_index));
+        return -ENOENT;
+    }
+
+    key = &ar->keys[key_index];
+    A_MEMZERO(&params, sizeof(params));
+    params.cipher = key->cipher;
+    params.key_len = key->key_len;
+    params.seq_len = key->seq_len;
+    params.seq = key->seq;
+    params.key = key->key;
+
+    callback(cookie, &params);
+
+    return key->key_len ? 0 : -ENOENT;
+}
+
+
+static int
+ar6k_cfg80211_set_default_key(struct wiphy *wiphy, struct net_device *ndev,
+                              A_UINT8 key_index)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(ndev);
+    struct ar_key *key = NULL;
+    A_STATUS status = A_OK;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: index %d\n", __func__, key_index));
+
+    if(ar->arWmiReady == FALSE) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wmi not ready\n", __func__));
+        return -EIO;
+    }
+
+    if(ar->arWlanState == WLAN_DISABLED) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wlan disabled\n", __func__));
+        return -EIO;
+    }
+
+    if(key_index < WMI_MIN_KEY_INDEX || key_index > WMI_MAX_KEY_INDEX) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_INFO,
+                        ("%s: key index %d out of bounds\n",
+                        __func__, key_index));
+        return -ENOENT;
+    }
+
+    if(!ar->keys[key_index].key_len) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: invalid key index %d\n",
+                        __func__, key_index));
+        return -EINVAL;
+    }
+
+    ar->arDefTxKeyIndex = key_index;
+    key = &ar->keys[ar->arDefTxKeyIndex];
+    status = wmi_addKey_cmd(ar->arWmi, ar->arDefTxKeyIndex,
+                            ar->arPairwiseCrypto, GROUP_USAGE | TX_USAGE,
+                            key->key_len, key->seq, key->key, KEY_OP_INIT_VAL,
+                            NULL, SYNC_BOTH_WMIFLAG);
+    if (status != A_OK) {
+        return -EIO;
+    }
+
+    return 0;
+}
+
+static int
+ar6k_cfg80211_set_default_mgmt_key(struct wiphy *wiphy, struct net_device *ndev,
+                                   A_UINT8 key_index)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(ndev);
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: index %d\n", __func__, key_index));
+
+    if(ar->arWmiReady == FALSE) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wmi not ready\n", __func__));
+        return -EIO;
+    }
+
+    if(ar->arWlanState == WLAN_DISABLED) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wlan disabled\n", __func__));
+        return -EIO;
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: not supported\n", __func__));
+    return -ENOTSUPP;
+}
+
+void
+ar6k_cfg80211_tkip_micerr_event(AR_SOFTC_T *ar, A_UINT8 keyid, A_BOOL ismcast)
+{
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO,
+                    ("%s: keyid %d, ismcast %d\n", __func__, keyid, ismcast));
+
+    cfg80211_michael_mic_failure(ar->arNetDev, ar->arBssid,
+                                 (ismcast ? NL80211_KEYTYPE_GROUP : NL80211_KEYTYPE_PAIRWISE),
+                                 keyid, NULL, GFP_KERNEL);
+}
+
+static int
+ar6k_cfg80211_set_wiphy_params(struct wiphy *wiphy, A_UINT32 changed)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)wiphy_priv(wiphy);
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: changed 0x%x\n", __func__, changed));
+
+    if(ar->arWmiReady == FALSE) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wmi not ready\n", __func__));
+        return -EIO;
+    }
+
+    if(ar->arWlanState == WLAN_DISABLED) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wlan disabled\n", __func__));
+        return -EIO;
+    }
+
+    if (changed & WIPHY_PARAM_RTS_THRESHOLD) {
+        if (wmi_set_rts_cmd(ar->arWmi,wiphy->rts_threshold) != A_OK){
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: wmi_set_rts_cmd failed\n", __func__));
+            return -EIO;
+        }
+    }
+
+    return 0;
+}
+
+static int
+ar6k_cfg80211_set_bitrate_mask(struct wiphy *wiphy, struct net_device *dev,
+                               const A_UINT8 *peer,
+                               const struct cfg80211_bitrate_mask *mask)
+{
+    AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Setting rates: Not supported\n"));
+    return -EIO;
+}
+
+/* The type nl80211_tx_power_setting replaces the following data type from 2.6.36 onwards */
+static int
+ar6k_cfg80211_set_txpower(struct wiphy *wiphy, enum nl80211_tx_power_setting type, int dbm)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)wiphy_priv(wiphy);
+    A_UINT8 ar_dbm;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: type 0x%x, dbm %d\n", __func__, type, dbm));
+
+    if(ar->arWmiReady == FALSE) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wmi not ready\n", __func__));
+        return -EIO;
+    }
+
+    if(ar->arWlanState == WLAN_DISABLED) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wlan disabled\n", __func__));
+        return -EIO;
+    }
+
+    ar->arTxPwrSet = FALSE;
+    switch(type) {
+    case NL80211_TX_POWER_AUTOMATIC:
+        return 0;
+    case NL80211_TX_POWER_LIMITED:
+        ar->arTxPwr = ar_dbm = dbm;
+        ar->arTxPwrSet = TRUE;
+        break;
+    default:
+        AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: type 0x%x not supported\n", __func__, type));
+        return -EOPNOTSUPP;
+    }
+
+    wmi_set_txPwr_cmd(ar->arWmi, ar_dbm);
+
+    return 0;
+}
+
+static int
+ar6k_cfg80211_get_txpower(struct wiphy *wiphy, int *dbm)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)wiphy_priv(wiphy);
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: \n", __func__));
+
+    if(ar->arWmiReady == FALSE) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wmi not ready\n", __func__));
+        return -EIO;
+    }
+
+    if(ar->arWlanState == WLAN_DISABLED) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wlan disabled\n", __func__));
+        return -EIO;
+    }
+
+    if((ar->arConnected == TRUE)) {
+        ar->arTxPwr = 0;
+
+        if(wmi_get_txPwr_cmd(ar->arWmi) != A_OK) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: wmi_get_txPwr_cmd failed\n", __func__));
+            return -EIO;
+        }
+
+        wait_event_interruptible_timeout(arEvent, ar->arTxPwr != 0, 5 * HZ);
+
+        if(signal_pending(current)) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Target did not respond\n", __func__));
+            return -EINTR;
+        }
+    }
+
+    *dbm = ar->arTxPwr;
+    return 0;
+}
+
+static int
+ar6k_cfg80211_set_power_mgmt(struct wiphy *wiphy,
+                             struct net_device *dev,
+                             bool pmgmt, int timeout)
+{
+    AR_SOFTC_T *ar = ar6k_priv(dev);
+    WMI_POWER_MODE_CMD pwrMode;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: pmgmt %d, timeout %d\n", __func__, pmgmt, timeout));
+
+    if(ar->arWmiReady == FALSE) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wmi not ready\n", __func__));
+        return -EIO;
+    }
+
+    if(ar->arWlanState == WLAN_DISABLED) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wlan disabled\n", __func__));
+        return -EIO;
+    }
+
+    if(pmgmt) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: Max Perf\n", __func__));
+        pwrMode.powerMode = MAX_PERF_POWER;
+    } else {
+        AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: Rec Power\n", __func__));
+        pwrMode.powerMode = REC_POWER;
+    }
+
+    if(wmi_powermode_cmd(ar->arWmi, pwrMode.powerMode) != A_OK) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: wmi_powermode_cmd failed\n", __func__));
+        return -EIO;
+    }
+
+    return 0;
+}
+
+static int
+ar6k_cfg80211_add_virtual_intf(struct wiphy *wiphy, char *name,
+            				    enum nl80211_iftype type, u32 *flags,
+            				    struct vif_params *params)
+{
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: not supported\n", __func__));
+
+    /* Multiple virtual interface is not supported.
+     * The default interface supports STA and IBSS type
+     */
+    return -EOPNOTSUPP;
+}
+
+static int
+ar6k_cfg80211_del_virtual_intf(struct wiphy *wiphy, struct net_device *dev)
+{
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: not supported\n", __func__));
+
+    /* Multiple virtual interface is not supported.
+     * The default interface supports STA and IBSS type
+     */
+    return -EOPNOTSUPP;
+}
+
+static int
+ar6k_cfg80211_change_iface(struct wiphy *wiphy, struct net_device *ndev,
+                           enum nl80211_iftype type, u32 *flags,
+                           struct vif_params *params)
+{
+    AR_SOFTC_T *ar = ar6k_priv(ndev);
+    struct wireless_dev *wdev = ar->wdev;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: type %u\n", __func__, type));
+
+    if(ar->arWmiReady == FALSE) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wmi not ready\n", __func__));
+        return -EIO;
+    }
+
+    if(ar->arWlanState == WLAN_DISABLED) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wlan disabled\n", __func__));
+        return -EIO;
+    }
+
+    switch (type) {
+    case NL80211_IFTYPE_STATION:
+        ar->arNextMode = INFRA_NETWORK;
+        break;
+    case NL80211_IFTYPE_ADHOC:
+        ar->arNextMode = ADHOC_NETWORK;
+        break;
+    default:
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: type %u\n", __func__, type));
+        return -EOPNOTSUPP;
+    }
+
+    wdev->iftype = type;
+
+    return 0;
+}
+
+static int
+ar6k_cfg80211_join_ibss(struct wiphy *wiphy, struct net_device *dev,
+                        struct cfg80211_ibss_params *ibss_param)
+{
+    AR_SOFTC_T *ar = ar6k_priv(dev);
+    A_STATUS status;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: \n", __func__));
+
+    if(ar->arWmiReady == FALSE) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wmi not ready\n", __func__));
+        return -EIO;
+    }
+
+    if(ar->arWlanState == WLAN_DISABLED) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wlan disabled\n", __func__));
+        return -EIO;
+    }
+
+    if(!ibss_param->ssid_len || IEEE80211_MAX_SSID_LEN < ibss_param->ssid_len) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: ssid invalid\n", __func__));
+        return -EINVAL;
+    }
+
+    ar->arSsidLen = ibss_param->ssid_len;
+    A_MEMCPY(ar->arSsid, ibss_param->ssid, ar->arSsidLen);
+
+    if(ibss_param->channel) {
+        ar->arChannelHint = ibss_param->channel->center_freq;
+    }
+
+    if(ibss_param->channel_fixed) {
+        /* TODO: channel_fixed: The channel should be fixed, do not search for
+         * IBSSs to join on other channels. Target firmware does not support this
+         * feature, needs to be updated.*/
+    }
+
+    A_MEMZERO(ar->arReqBssid, sizeof(ar->arReqBssid));
+    if(ibss_param->bssid) {
+        if(A_MEMCMP(&ibss_param->bssid, bcast_mac, AR6000_ETH_ADDR_LEN)) {
+            A_MEMCPY(ar->arReqBssid, ibss_param->bssid, sizeof(ar->arReqBssid));
+        }
+    }
+
+    ar6k_set_wpa_version(ar, 0);
+    ar6k_set_auth_type(ar, NL80211_AUTHTYPE_OPEN_SYSTEM);
+
+    if(ibss_param->privacy) {
+        ar6k_set_cipher(ar, WLAN_CIPHER_SUITE_WEP40, true);
+        ar6k_set_cipher(ar, WLAN_CIPHER_SUITE_WEP40, false);
+    } else {
+        ar6k_set_cipher(ar, IW_AUTH_CIPHER_NONE, true);
+        ar6k_set_cipher(ar, IW_AUTH_CIPHER_NONE, false);
+    }
+
+    ar->arNetworkType = ar->arNextMode;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: Connect called with authmode %d dot11 auth %d"\
+                    " PW crypto %d PW crypto Len %d GRP crypto %d"\
+                    " GRP crypto Len %d channel hint %u\n",
+                    __func__, ar->arAuthMode, ar->arDot11AuthMode,
+                    ar->arPairwiseCrypto, ar->arPairwiseCryptoLen,
+                    ar->arGroupCrypto, ar->arGroupCryptoLen, ar->arChannelHint));
+
+    status = wmi_connect_cmd(ar->arWmi, ar->arNetworkType,
+                            ar->arDot11AuthMode, ar->arAuthMode,
+                            ar->arPairwiseCrypto, ar->arPairwiseCryptoLen,
+                            ar->arGroupCrypto,ar->arGroupCryptoLen,
+                            ar->arSsidLen, ar->arSsid,
+                            ar->arReqBssid, ar->arChannelHint,
+                            ar->arConnectCtrlFlags);
+
+    return 0;
+}
+
+static int
+ar6k_cfg80211_leave_ibss(struct wiphy *wiphy, struct net_device *dev)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: \n", __func__));
+
+    if(ar->arWmiReady == FALSE) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wmi not ready\n", __func__));
+        return -EIO;
+    }
+
+    if(ar->arWlanState == WLAN_DISABLED) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wlan disabled\n", __func__));
+        return -EIO;
+    }
+
+    wmi_disconnect_cmd(ar->arWmi);
+    A_MEMZERO(ar->arSsid, sizeof(ar->arSsid));
+    ar->arSsidLen = 0;
+
+    return 0;
+}
+
+
+static const
+A_UINT32 cipher_suites[] = {
+    WLAN_CIPHER_SUITE_WEP40,
+    WLAN_CIPHER_SUITE_WEP104,
+    WLAN_CIPHER_SUITE_TKIP,
+    WLAN_CIPHER_SUITE_CCMP,
+};
+
+static struct
+cfg80211_ops ar6k_cfg80211_ops = {
+    .change_virtual_intf = ar6k_cfg80211_change_iface,
+    .add_virtual_intf = ar6k_cfg80211_add_virtual_intf,
+    .del_virtual_intf = ar6k_cfg80211_del_virtual_intf,
+    .scan = ar6k_cfg80211_scan,
+    .connect = ar6k_cfg80211_connect,
+    .disconnect = ar6k_cfg80211_disconnect,
+    .add_key = ar6k_cfg80211_add_key,
+    .get_key = ar6k_cfg80211_get_key,
+    .del_key = ar6k_cfg80211_del_key,
+    .set_default_key = ar6k_cfg80211_set_default_key,
+    .set_default_mgmt_key = ar6k_cfg80211_set_default_mgmt_key,
+    .set_wiphy_params = ar6k_cfg80211_set_wiphy_params,
+    .set_bitrate_mask = ar6k_cfg80211_set_bitrate_mask,
+    .set_tx_power = ar6k_cfg80211_set_txpower,
+    .get_tx_power = ar6k_cfg80211_get_txpower,
+    .set_power_mgmt = ar6k_cfg80211_set_power_mgmt,
+    .join_ibss = ar6k_cfg80211_join_ibss,
+    .leave_ibss = ar6k_cfg80211_leave_ibss,
+};
+
+struct wireless_dev *
+ar6k_cfg80211_init(struct device *dev)
+{
+    int ret = 0;
+    struct wireless_dev *wdev;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: \n", __func__));
+
+    wdev = kzalloc(sizeof(struct wireless_dev), GFP_KERNEL);
+    if(!wdev) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                        ("%s: Couldn't allocate wireless device\n", __func__));
+        return ERR_PTR(-ENOMEM);
+    }
+
+    /* create a new wiphy for use with cfg80211 */
+    wdev->wiphy = wiphy_new(&ar6k_cfg80211_ops, sizeof(AR_SOFTC_T));
+    if(!wdev->wiphy) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                        ("%s: Couldn't allocate wiphy device\n", __func__));
+        kfree(wdev);
+        return ERR_PTR(-ENOMEM);
+    }
+
+    /* set device pointer for wiphy */
+    set_wiphy_dev(wdev->wiphy, dev);
+
+    wdev->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) |
+                                   BIT(NL80211_IFTYPE_ADHOC);
+    /* max num of ssids that can be probed during scanning */
+    wdev->wiphy->max_scan_ssids = MAX_PROBED_SSID_INDEX;
+    wdev->wiphy->bands[IEEE80211_BAND_2GHZ] = &ar6k_band_2ghz;
+    wdev->wiphy->bands[IEEE80211_BAND_5GHZ] = &ar6k_band_5ghz;
+    wdev->wiphy->signal_type = CFG80211_SIGNAL_TYPE_MBM;
+
+    wdev->wiphy->cipher_suites = cipher_suites;
+    wdev->wiphy->n_cipher_suites = ARRAY_SIZE(cipher_suites);
+
+    ret = wiphy_register(wdev->wiphy);
+    if(ret < 0) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                        ("%s: Couldn't register wiphy device\n", __func__));
+        wiphy_free(wdev->wiphy);
+        return ERR_PTR(ret);
+    }
+
+    return wdev;
+}
+
+void
+ar6k_cfg80211_deinit(AR_SOFTC_T *ar)
+{
+    struct wireless_dev *wdev = ar->wdev;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: \n", __func__));
+
+    if(ar->scan_request) {
+        cfg80211_scan_done(ar->scan_request, true);
+        ar->scan_request = NULL;
+    }
+
+    if(!wdev)
+        return;
+
+    wiphy_unregister(wdev->wiphy);
+    wiphy_free(wdev->wiphy);
+    kfree(wdev);
+}
+
+
+
+
+
+
+
diff --git a/drivers/net/ath6kl/os/linux/eeprom.c b/drivers/net/ath6kl/os/linux/eeprom.c
new file mode 100644
index 00000000000..be77fb87ebf
--- /dev/null
+++ b/drivers/net/ath6kl/os/linux/eeprom.c
@@ -0,0 +1,574 @@
+//------------------------------------------------------------------------------
+// Copyright (c) 2004-2010 Atheros Communications Inc.
+// All rights reserved.
+//
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//
+// Author(s): ="Atheros"
+//------------------------------------------------------------------------------
+
+
+#include "ar6000_drv.h"
+#include "htc.h"
+#include <linux/fs.h>
+
+#include "AR6002/hw2.0/hw/gpio_reg.h"
+#include "AR6002/hw2.0/hw/si_reg.h"
+
+//
+// defines
+//
+
+#define MAX_FILENAME 1023
+#define EEPROM_WAIT_LIMIT 16 
+
+#define HOST_INTEREST_ITEM_ADDRESS(item)          \
+        (AR6002_HOST_INTEREST_ITEM_ADDRESS(item))
+
+#define EEPROM_SZ 768
+
+/* soft mac */
+#define ATH_MAC_LEN                         6
+#define ATH_SOFT_MAC_TMP_BUF_LEN            64
+unsigned char mac_addr[ATH_MAC_LEN];
+unsigned char soft_mac_tmp_buf[ATH_SOFT_MAC_TMP_BUF_LEN];
+char *p_mac = NULL;
+/* soft mac */
+
+//
+// static variables
+//
+
+static A_UCHAR eeprom_data[EEPROM_SZ];
+static A_UINT32 sys_sleep_reg;
+static HIF_DEVICE *p_bmi_device;
+
+//
+// Functions
+//
+
+/* soft mac */
+static int
+wmic_ether_aton(const char *orig, A_UINT8 *eth)
+{
+  const char *bufp;
+  int i;
+
+  i = 0;
+  for(bufp = orig; *bufp != '\0'; ++bufp) {
+    unsigned int val;
+	int h, l;
+
+	h = hex_to_bin(*bufp++);
+
+	if (h < 0) {
+		printk("%s: MAC value is invalid\n", __FUNCTION__);
+		break;
+	}
+
+	l = hex_to_bin(*bufp++);
+	if (l < 0) {
+		printk("%s: MAC value is invalid\n", __FUNCTION__);
+		break;
+	}
+
+	val = (h << 4) | l;
+
+    eth[i] = (unsigned char) (val & 0377);
+    if(++i == ATH_MAC_LEN) {
+	    /* That's it.  Any trailing junk? */
+	    if (*bufp != '\0') {
+		    return 0;
+	    }
+	    return 1;
+    }
+    if (*bufp != ':')
+	    break;
+  }
+  return 0;
+}
+
+static void
+update_mac(unsigned char* eeprom, int size, unsigned char* macaddr)
+{
+	int i;
+	A_UINT16* ptr = (A_UINT16*)(eeprom+4);
+	A_UINT16  checksum = 0;
+
+	memcpy(eeprom+10,macaddr,6);
+
+	*ptr = 0;
+	ptr = (A_UINT16*)eeprom;
+
+	for (i=0; i<size; i+=2) {
+		checksum ^= *ptr++;
+	}
+	checksum = ~checksum;
+
+	ptr = (A_UINT16*)(eeprom+4);
+	*ptr = checksum;
+	return;
+}
+/* soft mac */
+
+/* Read a Target register and return its value. */
+inline void
+BMI_read_reg(A_UINT32 address, A_UINT32 *pvalue)
+{
+    BMIReadSOCRegister(p_bmi_device, address, pvalue);
+}
+
+/* Write a value to a Target register. */
+inline void
+BMI_write_reg(A_UINT32 address, A_UINT32 value)
+{
+    BMIWriteSOCRegister(p_bmi_device, address, value);
+}
+
+/* Read Target memory word and return its value. */
+inline void
+BMI_read_mem(A_UINT32 address, A_UINT32 *pvalue)
+{
+    BMIReadMemory(p_bmi_device, address, (A_UCHAR*)(pvalue), 4);
+}
+
+/* Write a word to a Target memory. */
+inline void
+BMI_write_mem(A_UINT32 address, A_UINT8 *p_data, A_UINT32 sz)
+{
+    BMIWriteMemory(p_bmi_device, address, (A_UCHAR*)(p_data), sz); 
+}
+
+/*
+ * Enable and configure the Target's Serial Interface
+ * so we can access the EEPROM.
+ */
+static void
+enable_SI(HIF_DEVICE *p_device)
+{
+    A_UINT32 regval;
+
+    printk("%s\n", __FUNCTION__);
+
+    p_bmi_device = p_device;
+
+    BMI_read_reg(RTC_BASE_ADDRESS+SYSTEM_SLEEP_OFFSET, &sys_sleep_reg);
+    BMI_write_reg(RTC_BASE_ADDRESS+SYSTEM_SLEEP_OFFSET, SYSTEM_SLEEP_DISABLE_SET(1)); //disable system sleep temporarily
+
+    BMI_read_reg(RTC_BASE_ADDRESS+CLOCK_CONTROL_OFFSET, &regval);
+    regval &= ~CLOCK_CONTROL_SI0_CLK_MASK;
+    BMI_write_reg(RTC_BASE_ADDRESS+CLOCK_CONTROL_OFFSET, regval);
+
+    BMI_read_reg(RTC_BASE_ADDRESS+RESET_CONTROL_OFFSET, &regval);
+    regval &= ~RESET_CONTROL_SI0_RST_MASK;
+    BMI_write_reg(RTC_BASE_ADDRESS+RESET_CONTROL_OFFSET, regval);
+
+
+    BMI_read_reg(GPIO_BASE_ADDRESS+GPIO_PIN0_OFFSET, &regval);
+    regval &= ~GPIO_PIN0_CONFIG_MASK;
+    BMI_write_reg(GPIO_BASE_ADDRESS+GPIO_PIN0_OFFSET, regval);
+
+    BMI_read_reg(GPIO_BASE_ADDRESS+GPIO_PIN1_OFFSET, &regval);
+    regval &= ~GPIO_PIN1_CONFIG_MASK;
+    BMI_write_reg(GPIO_BASE_ADDRESS+GPIO_PIN1_OFFSET, regval);
+
+    /* SI_CONFIG = 0x500a6; */
+    regval =    SI_CONFIG_BIDIR_OD_DATA_SET(1)  |
+                SI_CONFIG_I2C_SET(1)            |
+                SI_CONFIG_POS_SAMPLE_SET(1)     |
+                SI_CONFIG_INACTIVE_CLK_SET(1)   |
+                SI_CONFIG_INACTIVE_DATA_SET(1)   |
+                SI_CONFIG_DIVIDER_SET(6);
+    BMI_write_reg(SI_BASE_ADDRESS+SI_CONFIG_OFFSET, regval);
+    
+}
+
+static void
+disable_SI(void)
+{
+    A_UINT32 regval;
+    
+    printk("%s\n", __FUNCTION__);
+
+    BMI_write_reg(RTC_BASE_ADDRESS+RESET_CONTROL_OFFSET, RESET_CONTROL_SI0_RST_MASK);
+    BMI_read_reg(RTC_BASE_ADDRESS+CLOCK_CONTROL_OFFSET, &regval);
+    regval |= CLOCK_CONTROL_SI0_CLK_MASK;
+    BMI_write_reg(RTC_BASE_ADDRESS+CLOCK_CONTROL_OFFSET, regval);//Gate SI0 clock
+    BMI_write_reg(RTC_BASE_ADDRESS+SYSTEM_SLEEP_OFFSET, sys_sleep_reg); //restore system sleep setting
+}
+
+/*
+ * Tell the Target to start an 8-byte read from EEPROM,
+ * putting the results in Target RX_DATA registers.
+ */
+static void
+request_8byte_read(int offset)
+{
+    A_UINT32 regval;
+
+//    printk("%s: request_8byte_read from offset 0x%x\n", __FUNCTION__, offset);
+
+    
+    /* SI_TX_DATA0 = read from offset */
+        regval =(0xa1<<16)|
+                ((offset & 0xff)<<8)    |
+                (0xa0 | ((offset & 0xff00)>>7));
+    
+        BMI_write_reg(SI_BASE_ADDRESS+SI_TX_DATA0_OFFSET, regval);
+
+        regval = SI_CS_START_SET(1)      |
+                SI_CS_RX_CNT_SET(8)     |
+                SI_CS_TX_CNT_SET(3);
+        BMI_write_reg(SI_BASE_ADDRESS+SI_CS_OFFSET, regval);
+}
+
+/*
+ * Tell the Target to start a 4-byte write to EEPROM,
+ * writing values from Target TX_DATA registers.
+ */
+static void
+request_4byte_write(int offset, A_UINT32 data)
+{
+    A_UINT32 regval;
+
+    printk("%s: request_4byte_write (0x%x) to offset 0x%x\n", __FUNCTION__, data, offset);
+
+        /* SI_TX_DATA0 = write data to offset */
+        regval =    ((data & 0xffff) <<16)    |
+                ((offset & 0xff)<<8)    |
+                (0xa0 | ((offset & 0xff00)>>7));
+        BMI_write_reg(SI_BASE_ADDRESS+SI_TX_DATA0_OFFSET, regval);
+
+        regval =    data >> 16;
+        BMI_write_reg(SI_BASE_ADDRESS+SI_TX_DATA1_OFFSET, regval);
+
+        regval =    SI_CS_START_SET(1)      |
+                SI_CS_RX_CNT_SET(0)     |
+                SI_CS_TX_CNT_SET(6);
+        BMI_write_reg(SI_BASE_ADDRESS+SI_CS_OFFSET, regval);
+}
+
+/*
+ * Check whether or not an EEPROM request that was started
+ * earlier has completed yet.
+ */
+static A_BOOL
+request_in_progress(void)
+{
+    A_UINT32 regval;
+
+    /* Wait for DONE_INT in SI_CS */
+    BMI_read_reg(SI_BASE_ADDRESS+SI_CS_OFFSET, &regval);
+
+//    printk("%s: request in progress SI_CS=0x%x\n", __FUNCTION__, regval);
+    if (regval & SI_CS_DONE_ERR_MASK) {
+        printk("%s: EEPROM signaled ERROR (0x%x)\n", __FUNCTION__, regval);
+    }
+
+    return (!(regval & SI_CS_DONE_INT_MASK));
+}
+
+/*
+ * try to detect the type of EEPROM,16bit address or 8bit address
+ */
+
+static void eeprom_type_detect(void)
+{
+    A_UINT32 regval;
+    A_UINT8 i = 0;
+
+    request_8byte_read(0x100);
+   /* Wait for DONE_INT in SI_CS */
+    do{
+        BMI_read_reg(SI_BASE_ADDRESS+SI_CS_OFFSET, &regval);
+        if (regval & SI_CS_DONE_ERR_MASK) {
+            printk("%s: ERROR : address type was wrongly set\n", __FUNCTION__);     
+            break;
+        }
+        if (i++ == EEPROM_WAIT_LIMIT) {
+            printk("%s: EEPROM not responding\n", __FUNCTION__);
+        }
+    } while(!(regval & SI_CS_DONE_INT_MASK));
+}
+
+/*
+ * Extract the results of a completed EEPROM Read request
+ * and return them to the caller.
+ */
+inline void
+read_8byte_results(A_UINT32 *data)
+{
+    /* Read SI_RX_DATA0 and SI_RX_DATA1 */
+    BMI_read_reg(SI_BASE_ADDRESS+SI_RX_DATA0_OFFSET, &data[0]);
+    BMI_read_reg(SI_BASE_ADDRESS+SI_RX_DATA1_OFFSET, &data[1]);
+}
+
+
+/*
+ * Wait for a previously started command to complete.
+ * Timeout if the command is takes "too long".
+ */
+static void
+wait_for_eeprom_completion(void)
+{
+    int i=0;
+
+    while (request_in_progress()) {
+        if (i++ == EEPROM_WAIT_LIMIT) {
+            printk("%s: EEPROM not responding\n", __FUNCTION__);
+        }
+    }
+}
+
+/*
+ * High-level function which starts an 8-byte read,
+ * waits for it to complete, and returns the result.
+ */
+static void
+fetch_8bytes(int offset, A_UINT32 *data)
+{
+    request_8byte_read(offset);
+    wait_for_eeprom_completion();
+    read_8byte_results(data);
+
+    /* Clear any pending intr */
+    BMI_write_reg(SI_BASE_ADDRESS+SI_CS_OFFSET, SI_CS_DONE_INT_MASK);
+}
+
+/*
+ * High-level function which starts a 4-byte write,
+ * and waits for it to complete.
+ */
+inline void
+commit_4bytes(int offset, A_UINT32 data)
+{
+    request_4byte_write(offset, data);
+    wait_for_eeprom_completion();
+}
+/* ATHENV */
+#ifdef ANDROID_ENV
+void eeprom_ar6000_transfer(HIF_DEVICE *device, char *fake_file, char *p_mac)
+{
+    A_UINT32 first_word;
+    A_UINT32 board_data_addr;
+    int i;
+
+    printk("%s: Enter\n", __FUNCTION__);
+
+    enable_SI(device);
+    eeprom_type_detect();
+
+    if (fake_file) {
+        /*
+         * Transfer from file to Target RAM.
+         * Fetch source data from file.
+         */
+        mm_segment_t		oldfs;
+        struct file		*filp;
+        struct inode		*inode = NULL;
+        int			length;
+
+        /* open file */
+        oldfs = get_fs();
+        set_fs(KERNEL_DS);
+        filp = filp_open(fake_file, O_RDONLY, S_IRUSR);
+
+        if (IS_ERR(filp)) {
+            printk("%s: file %s filp_open error\n", __FUNCTION__, fake_file);
+            set_fs(oldfs);
+            return;
+        }
+
+        if (!filp->f_op) {
+            printk("%s: File Operation Method Error\n", __FUNCTION__);
+            filp_close(filp, NULL);
+            set_fs(oldfs);
+            return;
+        }
+
+        inode = GET_INODE_FROM_FILEP(filep);
+        if (!inode) {
+            printk("%s: Get inode from filp failed\n", __FUNCTION__);
+            filp_close(filp, NULL);
+            set_fs(oldfs);
+            return;
+        }
+
+        printk("%s file offset opsition: %xh\n", __FUNCTION__, (unsigned)filp->f_pos);
+
+        /* file's size */
+        length = i_size_read(inode->i_mapping->host);
+        printk("%s: length=%d\n", __FUNCTION__, length);
+        if (length != EEPROM_SZ) {
+            printk("%s: The file's size is not as expected\n", __FUNCTION__);
+            filp_close(filp, NULL);
+            set_fs(oldfs);
+            return;
+        }
+
+        /* read data */
+        if (filp->f_op->read(filp, eeprom_data, length, &filp->f_pos) != length) {
+            printk("%s: file read error\n", __FUNCTION__);
+            filp_close(filp, NULL);
+            set_fs(oldfs);
+            return;
+        }
+
+        /* read data out successfully */
+        filp_close(filp, NULL);
+        set_fs(oldfs);
+    } else {
+        /*
+         * Read from EEPROM to file OR transfer from EEPROM to Target RAM.
+         * Fetch EEPROM_SZ Bytes of Board Data, 8 bytes at a time.
+         */
+
+        fetch_8bytes(0, (A_UINT32 *)(&eeprom_data[0]));
+
+        /* Check the first word of EEPROM for validity */
+        first_word = *((A_UINT32 *)eeprom_data);
+
+        if ((first_word == 0) || (first_word == 0xffffffff)) {
+            printk("Did not find EEPROM with valid Board Data.\n");
+        }
+
+        for (i=8; i<EEPROM_SZ; i+=8) {
+            fetch_8bytes(i, (A_UINT32 *)(&eeprom_data[i]));
+        }
+    }
+
+    /* soft mac */
+    if (p_mac) {
+
+        mm_segment_t		oldfs;
+        struct file		*filp;
+        struct inode		*inode = NULL;
+        int			length;
+        
+        /* open file */
+        oldfs = get_fs();
+        set_fs(KERNEL_DS);
+        filp = filp_open(p_mac, O_RDONLY, S_IRUSR);
+        
+        printk("%s try to open file %s\n", __FUNCTION__, p_mac);
+
+        if (IS_ERR(filp)) {
+            printk("%s: file %s filp_open error\n", __FUNCTION__, p_mac);
+            set_fs(oldfs);
+            return;
+        }
+        
+        if (!filp->f_op) {
+            printk("%s: File Operation Method Error\n", __FUNCTION__);
+            filp_close(filp, NULL);
+            set_fs(oldfs);
+            return;
+        }
+        
+        inode = GET_INODE_FROM_FILEP(filep);
+        if (!inode) {
+            printk("%s: Get inode from filp failed\n", __FUNCTION__);
+            filp_close(filp, NULL);
+            set_fs(oldfs);
+            return;
+        }
+        
+        printk("%s file offset opsition: %xh\n", __FUNCTION__, (unsigned)filp->f_pos);
+        
+        /* file's size */
+        length = i_size_read(inode->i_mapping->host);
+        printk("%s: length=%d\n", __FUNCTION__, length);
+        if (length > ATH_SOFT_MAC_TMP_BUF_LEN) {
+            printk("%s: MAC file's size is not as expected\n", __FUNCTION__);
+            filp_close(filp, NULL);
+            set_fs(oldfs);
+            return;
+        }
+        
+        /* read data */
+        if (filp->f_op->read(filp, soft_mac_tmp_buf, length, &filp->f_pos) != length) {
+            printk("%s: file read error\n", __FUNCTION__);
+            filp_close(filp, NULL);
+            set_fs(oldfs);
+            return;
+        }
+
+#if 0
+        /* the data we just read */
+        printk("%s: mac address from the file:\n", __FUNCTION__);
+        for (i = 0; i < length; i++)
+            printk("[%c(0x%x)],", soft_mac_tmp_buf[i], soft_mac_tmp_buf[i]);
+        printk("\n");
+#endif
+
+        /* read data out successfully */
+        filp_close(filp, NULL);
+        set_fs(oldfs);
+
+        /* convert mac address */
+        if (!wmic_ether_aton(soft_mac_tmp_buf, mac_addr)) {
+            printk("%s: convert mac value fail\n", __FUNCTION__);
+            return;
+        }
+
+#if 0
+        /* the converted mac address */
+        printk("%s: the converted mac value\n", __FUNCTION__);
+        for (i = 0; i < ATH_MAC_LEN; i++)
+            printk("[0x%x],", mac_addr[i]);
+        printk("\n");
+#endif
+    }
+    /* soft mac */
+
+    /* Determine where in Target RAM to write Board Data */
+    BMI_read_mem( HOST_INTEREST_ITEM_ADDRESS(hi_board_data), &board_data_addr);
+    if (board_data_addr == 0) {
+        printk("hi_board_data is zero\n");
+    }
+
+    /* soft mac */
+#if 1
+    /* Update MAC address in RAM */
+    if (p_mac) {
+	    update_mac(eeprom_data, EEPROM_SZ, mac_addr);
+    }
+#endif
+#if 0
+    /* mac address in eeprom array */
+    printk("%s: mac values in eeprom array\n", __FUNCTION__);
+    for (i = 10; i < 10 + 6; i++)
+        printk("[0x%x],", eeprom_data[i]);
+    printk("\n");
+#endif
+    /* soft mac */
+
+    /* Write EEPROM data to Target RAM */
+    BMI_write_mem(board_data_addr, ((A_UINT8 *)eeprom_data), EEPROM_SZ);
+
+    /* Record the fact that Board Data IS initialized */
+    {
+       A_UINT32 one = 1;
+       BMI_write_mem(HOST_INTEREST_ITEM_ADDRESS(hi_board_data_initialized),
+                     (A_UINT8 *)&one, sizeof(A_UINT32));
+    }
+
+    disable_SI();
+}
+#endif
+/* ATHENV */
+
diff --git a/drivers/net/ath6kl/os/linux/export_hci_transport.c b/drivers/net/ath6kl/os/linux/export_hci_transport.c
new file mode 100644
index 00000000000..ffbf3d229a5
--- /dev/null
+++ b/drivers/net/ath6kl/os/linux/export_hci_transport.c
@@ -0,0 +1,125 @@
+//------------------------------------------------------------------------------
+// Copyright (c) 2009-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// HCI bridge implementation
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#include <a_config.h>
+#include <athdefs.h>
+#include "a_types.h"
+#include "a_osapi.h"
+#include "htc_api.h"
+#include "a_drv.h"
+#include "hif.h"
+#include "common_drv.h"
+#include "a_debug.h"
+#include "hci_transport_api.h"
+
+#include "AR6002/hw4.0/hw/apb_athr_wlan_map.h"
+#include "AR6002/hw4.0/hw/uart_reg.h"
+#include "AR6002/hw4.0/hw/rtc_wlan_reg.h"
+
+HCI_TRANSPORT_HANDLE (*_HCI_TransportAttach)(void *HTCHandle, HCI_TRANSPORT_CONFIG_INFO *pInfo);
+void (*_HCI_TransportDetach)(HCI_TRANSPORT_HANDLE HciTrans);
+A_STATUS    (*_HCI_TransportAddReceivePkts)(HCI_TRANSPORT_HANDLE HciTrans, HTC_PACKET_QUEUE *pQueue);
+A_STATUS    (*_HCI_TransportSendPkt)(HCI_TRANSPORT_HANDLE HciTrans, HTC_PACKET *pPacket, A_BOOL Synchronous);
+void        (*_HCI_TransportStop)(HCI_TRANSPORT_HANDLE HciTrans);
+A_STATUS    (*_HCI_TransportStart)(HCI_TRANSPORT_HANDLE HciTrans);
+A_STATUS    (*_HCI_TransportEnableDisableAsyncRecv)(HCI_TRANSPORT_HANDLE HciTrans, A_BOOL Enable);
+A_STATUS    (*_HCI_TransportRecvHCIEventSync)(HCI_TRANSPORT_HANDLE HciTrans, 
+                                          HTC_PACKET           *pPacket,
+                                          int                  MaxPollMS);
+A_STATUS    (*_HCI_TransportSetBaudRate)(HCI_TRANSPORT_HANDLE HciTrans, A_UINT32 Baud);
+A_STATUS    (*_HCI_TransportEnablePowerMgmt)(HCI_TRANSPORT_HANDLE HciTrans, A_BOOL Enable);
+
+extern HCI_TRANSPORT_CALLBACKS ar6kHciTransCallbacks;
+
+A_STATUS ar6000_register_hci_transport(HCI_TRANSPORT_CALLBACKS *hciTransCallbacks)
+{
+    ar6kHciTransCallbacks = *hciTransCallbacks;
+
+    _HCI_TransportAttach = HCI_TransportAttach;
+    _HCI_TransportDetach = HCI_TransportDetach;
+    _HCI_TransportAddReceivePkts = HCI_TransportAddReceivePkts;
+    _HCI_TransportSendPkt = HCI_TransportSendPkt;
+    _HCI_TransportStop = HCI_TransportStop;
+    _HCI_TransportStart = HCI_TransportStart;
+    _HCI_TransportEnableDisableAsyncRecv = HCI_TransportEnableDisableAsyncRecv;
+    _HCI_TransportRecvHCIEventSync = HCI_TransportRecvHCIEventSync;
+    _HCI_TransportSetBaudRate = HCI_TransportSetBaudRate;
+    _HCI_TransportEnablePowerMgmt = HCI_TransportEnablePowerMgmt;
+
+    return A_OK;
+}
+
+A_STATUS
+ar6000_get_hif_dev(HIF_DEVICE *device, void *config)
+{
+    A_STATUS status;
+
+    status = HIFConfigureDevice(device,
+                                HIF_DEVICE_GET_OS_DEVICE,
+                                (HIF_DEVICE_OS_DEVICE_INFO *)config, 
+                                sizeof(HIF_DEVICE_OS_DEVICE_INFO));
+    return status;
+}
+
+A_STATUS ar6000_set_uart_config(HIF_DEVICE *hifDevice, 
+                                A_UINT32 scale, 
+                                A_UINT32 step)
+{
+    A_UINT32 regAddress;
+    A_UINT32 regVal;
+    A_STATUS status;
+
+    regAddress = WLAN_UART_BASE_ADDRESS | UART_CLKDIV_ADDRESS;
+    regVal = ((A_UINT32)scale << 16) | step;
+    /* change the HCI UART scale/step values through the diagnostic window */
+    status = ar6000_WriteRegDiag(hifDevice, &regAddress, &regVal);                     
+
+    return status;
+}
+
+A_STATUS ar6000_get_core_clock_config(HIF_DEVICE *hifDevice, A_UINT32 *data)
+{
+    A_UINT32 regAddress;
+    A_STATUS status;
+
+    regAddress = WLAN_RTC_BASE_ADDRESS | WLAN_CPU_CLOCK_ADDRESS;
+    /* read CPU clock settings*/
+    status = ar6000_ReadRegDiag(hifDevice, &regAddress, data);
+
+    return status;
+}
+
+EXPORT_SYMBOL(ar6000_register_hci_transport);
+EXPORT_SYMBOL(ar6000_get_hif_dev);
+EXPORT_SYMBOL(ar6000_set_uart_config);
+EXPORT_SYMBOL(ar6000_get_core_clock_config);
+EXPORT_SYMBOL(_HCI_TransportAttach);
+EXPORT_SYMBOL(_HCI_TransportDetach);
+EXPORT_SYMBOL(_HCI_TransportAddReceivePkts);
+EXPORT_SYMBOL(_HCI_TransportSendPkt);
+EXPORT_SYMBOL(_HCI_TransportStop);
+EXPORT_SYMBOL(_HCI_TransportStart);
+EXPORT_SYMBOL(_HCI_TransportEnableDisableAsyncRecv);
+EXPORT_SYMBOL(_HCI_TransportRecvHCIEventSync);
+EXPORT_SYMBOL(_HCI_TransportSetBaudRate);
+EXPORT_SYMBOL(_HCI_TransportEnablePowerMgmt);
diff --git a/drivers/net/ath6kl/os/linux/hci_bridge.c b/drivers/net/ath6kl/os/linux/hci_bridge.c
new file mode 100644
index 00000000000..5cdc3b85a6f
--- /dev/null
+++ b/drivers/net/ath6kl/os/linux/hci_bridge.c
@@ -0,0 +1,1144 @@
+//------------------------------------------------------------------------------
+// Copyright (c) 2009-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// HCI bridge implementation
+//
+// Author(s): ="Atheros"
+//==============================================================================
+
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+#include <linux/etherdevice.h>
+#include <a_config.h>
+#include <athdefs.h>
+#include "a_types.h"
+#include "a_osapi.h"
+#include "htc_api.h"
+#include "wmi.h"
+#include "a_drv.h"
+#include "hif.h"
+#include "common_drv.h"
+#include "a_debug.h"
+#define  ATH_DEBUG_HCI_BRIDGE    ATH_DEBUG_MAKE_MODULE_MASK(6)
+#define  ATH_DEBUG_HCI_RECV      ATH_DEBUG_MAKE_MODULE_MASK(7)
+#define  ATH_DEBUG_HCI_SEND      ATH_DEBUG_MAKE_MODULE_MASK(8)
+#define  ATH_DEBUG_HCI_DUMP      ATH_DEBUG_MAKE_MODULE_MASK(9)
+#else
+#include "ar6000_drv.h"
+#endif  /* EXPORT_HCI_BRIDGE_INTERFACE */
+
+#ifdef ATH_AR6K_ENABLE_GMBOX
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+#include "export_hci_transport.h"
+#else
+#include "hci_transport_api.h"
+#endif
+#include "epping_test.h"
+#include "gmboxif.h"
+#include "ar3kconfig.h"
+#include <net/bluetooth/bluetooth.h>
+#include <net/bluetooth/hci_core.h>
+
+    /* only build on newer kernels which have BT configured */
+#if defined(CONFIG_BT_MODULE) || defined(CONFIG_BT)
+#define CONFIG_BLUEZ_HCI_BRIDGE  
+#endif
+
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+unsigned int ar3khcibaud = 0;
+unsigned int hciuartscale = 0;
+unsigned int hciuartstep = 0;
+
+module_param(ar3khcibaud, int, 0644);
+module_param(hciuartscale, int, 0644);
+module_param(hciuartstep, int, 0644);
+#else
+extern unsigned int ar3khcibaud;
+extern unsigned int hciuartscale;
+extern unsigned int hciuartstep;
+#endif /* EXPORT_HCI_BRIDGE_INTERFACE */
+
+typedef struct {
+    void                    *pHCIDev;          /* HCI bridge device */
+    HCI_TRANSPORT_PROPERTIES HCIProps;         /* HCI bridge props */
+    struct hci_dev          *pBtStackHCIDev;   /* BT Stack HCI dev */
+    A_BOOL                  HciNormalMode;     /* Actual HCI mode enabled (non-TEST)*/
+    A_BOOL                  HciRegistered;     /* HCI device registered with stack */
+    HTC_PACKET_QUEUE        HTCPacketStructHead;
+    A_UINT8                 *pHTCStructAlloc;
+    spinlock_t              BridgeLock;
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+    HCI_TRANSPORT_MISC_HANDLES    HCITransHdl; 
+#else
+    AR_SOFTC_T              *ar;
+#endif /* EXPORT_HCI_BRIDGE_INTERFACE */
+} AR6K_HCI_BRIDGE_INFO;
+
+#define MAX_ACL_RECV_BUFS           16
+#define MAX_EVT_RECV_BUFS           8
+#define MAX_HCI_WRITE_QUEUE_DEPTH   32
+#define MAX_ACL_RECV_LENGTH         1200
+#define MAX_EVT_RECV_LENGTH         257
+#define TX_PACKET_RSV_OFFSET        32
+#define NUM_HTC_PACKET_STRUCTS     ((MAX_ACL_RECV_BUFS + MAX_EVT_RECV_BUFS + MAX_HCI_WRITE_QUEUE_DEPTH) * 2)
+
+#define HCI_GET_OP_CODE(p)          (((A_UINT16)((p)[1])) << 8) | ((A_UINT16)((p)[0]))
+
+extern unsigned int setupbtdev;
+AR3K_CONFIG_INFO      ar3kconfig;
+
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+AR6K_HCI_BRIDGE_INFO *g_pHcidevInfo;
+#endif
+
+static A_STATUS bt_setup_hci(AR6K_HCI_BRIDGE_INFO *pHcidevInfo);
+static void     bt_cleanup_hci(AR6K_HCI_BRIDGE_INFO *pHcidevInfo);
+static A_STATUS bt_register_hci(AR6K_HCI_BRIDGE_INFO *pHcidevInfo);
+static A_BOOL   bt_indicate_recv(AR6K_HCI_BRIDGE_INFO      *pHcidevInfo, 
+                                 HCI_TRANSPORT_PACKET_TYPE Type, 
+                                 struct sk_buff            *skb);
+static struct sk_buff *bt_alloc_buffer(AR6K_HCI_BRIDGE_INFO *pHcidevInfo, int Length);
+static void     bt_free_buffer(AR6K_HCI_BRIDGE_INFO *pHcidevInfo, struct sk_buff *skb);   
+                               
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+A_STATUS ar6000_setup_hci(void *ar);
+void     ar6000_cleanup_hci(void *ar);
+A_STATUS hci_test_send(void *ar, struct sk_buff *skb);
+#else
+A_STATUS ar6000_setup_hci(AR_SOFTC_T *ar);
+void     ar6000_cleanup_hci(AR_SOFTC_T *ar);
+/* HCI bridge testing */
+A_STATUS hci_test_send(AR_SOFTC_T *ar, struct sk_buff *skb);
+#endif /* EXPORT_HCI_BRIDGE_INTERFACE */
+
+#define LOCK_BRIDGE(dev)   spin_lock_bh(&(dev)->BridgeLock)
+#define UNLOCK_BRIDGE(dev) spin_unlock_bh(&(dev)->BridgeLock)
+
+static inline void FreeBtOsBuf(AR6K_HCI_BRIDGE_INFO *pHcidevInfo, void *osbuf)
+{    
+    if (pHcidevInfo->HciNormalMode) {
+        bt_free_buffer(pHcidevInfo, (struct sk_buff *)osbuf);
+    } else {
+            /* in test mode, these are just ordinary netbuf allocations */
+        A_NETBUF_FREE(osbuf);
+    }
+}
+
+static void FreeHTCStruct(AR6K_HCI_BRIDGE_INFO *pHcidevInfo, HTC_PACKET *pPacket)
+{
+    LOCK_BRIDGE(pHcidevInfo);
+    HTC_PACKET_ENQUEUE(&pHcidevInfo->HTCPacketStructHead,pPacket);
+    UNLOCK_BRIDGE(pHcidevInfo);  
+}
+
+static HTC_PACKET * AllocHTCStruct(AR6K_HCI_BRIDGE_INFO *pHcidevInfo)
+{
+    HTC_PACKET  *pPacket = NULL;
+    LOCK_BRIDGE(pHcidevInfo);
+    pPacket = HTC_PACKET_DEQUEUE(&pHcidevInfo->HTCPacketStructHead);
+    UNLOCK_BRIDGE(pHcidevInfo);  
+    return pPacket;
+}
+
+#define BLOCK_ROUND_UP_PWR2(x, align)    (((int) (x) + ((align)-1)) & ~((align)-1))
+
+static void RefillRecvBuffers(AR6K_HCI_BRIDGE_INFO      *pHcidevInfo, 
+                              HCI_TRANSPORT_PACKET_TYPE Type, 
+                              int                       NumBuffers)
+{
+    int                 length, i;
+    void                *osBuf = NULL;
+    HTC_PACKET_QUEUE    queue;
+    HTC_PACKET          *pPacket;
+
+    INIT_HTC_PACKET_QUEUE(&queue);
+    
+    if (Type == HCI_ACL_TYPE) {     
+        if (pHcidevInfo->HciNormalMode) {  
+            length = HCI_MAX_FRAME_SIZE;
+        } else {
+            length = MAX_ACL_RECV_LENGTH;    
+        }
+    } else {
+        length = MAX_EVT_RECV_LENGTH;
+    }
+    
+        /* add on transport head and tail room */ 
+    length += pHcidevInfo->HCIProps.HeadRoom + pHcidevInfo->HCIProps.TailRoom;
+        /* round up to the required I/O padding */      
+    length = BLOCK_ROUND_UP_PWR2(length,pHcidevInfo->HCIProps.IOBlockPad);
+             
+    for (i = 0; i < NumBuffers; i++) {   
+           
+        if (pHcidevInfo->HciNormalMode) {   
+            osBuf = bt_alloc_buffer(pHcidevInfo,length);       
+        } else {
+            osBuf = A_NETBUF_ALLOC(length);  
+        }
+          
+        if (NULL == osBuf) {
+            break;    
+        }            
+         
+        pPacket = AllocHTCStruct(pHcidevInfo);
+        if (NULL == pPacket) {
+            FreeBtOsBuf(pHcidevInfo,osBuf);
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Failed to alloc HTC struct \n"));
+            break;    
+        }     
+        
+        SET_HTC_PACKET_INFO_RX_REFILL(pPacket,osBuf,A_NETBUF_DATA(osBuf),length,Type);
+            /* add to queue */
+        HTC_PACKET_ENQUEUE(&queue,pPacket);
+    }
+    
+    if (i > 0) {
+        HCI_TransportAddReceivePkts(pHcidevInfo->pHCIDev, &queue);    
+    }
+}
+
+#define HOST_INTEREST_ITEM_ADDRESS(ar, item) \
+        (((ar)->arTargetType == TARGET_TYPE_AR6002) ? AR6002_HOST_INTEREST_ITEM_ADDRESS(item) : \
+        (((ar)->arTargetType == TARGET_TYPE_AR6003) ? AR6003_HOST_INTEREST_ITEM_ADDRESS(item) : 0))
+static A_STATUS ar6000_hci_transport_ready(HCI_TRANSPORT_HANDLE     HCIHandle, 
+                                           HCI_TRANSPORT_PROPERTIES *pProps, 
+                                           void                     *pContext)
+{
+    AR6K_HCI_BRIDGE_INFO *pHcidevInfo = (AR6K_HCI_BRIDGE_INFO *)pContext;
+    A_STATUS              status;
+    A_UINT32 address, hci_uart_pwr_mgmt_params;
+//    AR3K_CONFIG_INFO      ar3kconfig;
+    
+    pHcidevInfo->pHCIDev = HCIHandle;
+    
+    A_MEMCPY(&pHcidevInfo->HCIProps,pProps,sizeof(*pProps));
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_HCI_BRIDGE,("HCI ready (hci:0x%lX, headroom:%d, tailroom:%d blockpad:%d) \n", 
+            (unsigned long)HCIHandle, 
+            pHcidevInfo->HCIProps.HeadRoom, 
+            pHcidevInfo->HCIProps.TailRoom,
+            pHcidevInfo->HCIProps.IOBlockPad));
+    
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+    A_ASSERT((pProps->HeadRoom + pProps->TailRoom) <= (struct net_device *)(pHcidevInfo->HCITransHdl.netDevice)->hard_header_len);
+#else
+    A_ASSERT((pProps->HeadRoom + pProps->TailRoom) <= pHcidevInfo->ar->arNetDev->hard_header_len);
+#endif
+                             
+        /* provide buffers */
+    RefillRecvBuffers(pHcidevInfo, HCI_ACL_TYPE, MAX_ACL_RECV_BUFS);
+    RefillRecvBuffers(pHcidevInfo, HCI_EVENT_TYPE, MAX_EVT_RECV_BUFS);
+   
+    do {
+            /* start transport */
+        status = HCI_TransportStart(pHcidevInfo->pHCIDev);
+         
+        if (A_FAILED(status)) {
+            break;    
+        }
+        
+        if (!pHcidevInfo->HciNormalMode) {
+                /* in test mode, no need to go any further */
+            break;    
+        }
+
+        // The delay is required when AR6K is driving the BT reset line
+        // where time is needed after the BT chip is out of reset (HCI_TransportStart)
+        // and before the first HCI command is issued (AR3KConfigure)
+        // FIXME
+        // The delay should be configurable and be only applied when AR6K driving the BT
+        // reset line. This could be done by some module parameter or based on some HW config
+        // info. For now apply 100ms delay blindly
+        A_MDELAY(100);
+        
+        A_MEMZERO(&ar3kconfig,sizeof(ar3kconfig));
+        ar3kconfig.pHCIDev = pHcidevInfo->pHCIDev;
+        ar3kconfig.pHCIProps = &pHcidevInfo->HCIProps;
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+        ar3kconfig.pHIFDevice = (HIF_DEVICE *)(pHcidevInfo->HCITransHdl.hifDevice);
+#else
+        ar3kconfig.pHIFDevice = pHcidevInfo->ar->arHifDevice;
+#endif
+        ar3kconfig.pBtStackHCIDev = pHcidevInfo->pBtStackHCIDev;
+        
+        if (ar3khcibaud != 0) {
+                /* user wants ar3k baud rate change */
+            ar3kconfig.Flags |= AR3K_CONFIG_FLAG_SET_AR3K_BAUD;
+            ar3kconfig.Flags |= AR3K_CONFIG_FLAG_AR3K_BAUD_CHANGE_DELAY;
+            ar3kconfig.AR3KBaudRate = ar3khcibaud;    
+        }
+        
+        if ((hciuartscale != 0) || (hciuartstep != 0)) {   
+                /* user wants to tune HCI bridge UART scale/step values */
+            ar3kconfig.AR6KScale = (A_UINT16)hciuartscale;
+            ar3kconfig.AR6KStep = (A_UINT16)hciuartstep;           
+            ar3kconfig.Flags |= AR3K_CONFIG_FLAG_SET_AR6K_SCALE_STEP;
+        }
+        
+        /* Fetch the address of the hi_hci_uart_pwr_mgmt_params instance in the host interest area */
+        address = TARG_VTOP(pHcidevInfo->ar->arTargetType, 
+                            HOST_INTEREST_ITEM_ADDRESS(pHcidevInfo->ar, hi_hci_uart_pwr_mgmt_params));
+        status = ar6000_ReadRegDiag(pHcidevInfo->ar->arHifDevice, &address, &hci_uart_pwr_mgmt_params);
+        if (A_OK == status) {
+            ar3kconfig.PwrMgmtEnabled = (hci_uart_pwr_mgmt_params & 0x1);
+            ar3kconfig.IdleTimeout = (hci_uart_pwr_mgmt_params & 0xFFFF0000) >> 16;
+            ar3kconfig.WakeupTimeout = (hci_uart_pwr_mgmt_params & 0xFF00) >> 8;
+        } else {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("HCI Bridge: failed to read hci_uart_pwr_mgmt_params! \n"));
+        }
+        /* configure the AR3K device */         
+		memcpy(ar3kconfig.bdaddr,pHcidevInfo->ar->bdaddr,6);
+        status = AR3KConfigure(&ar3kconfig);
+        if (A_FAILED(status)) {
+            break; 
+        }
+
+        /* Make sure both AR6K and AR3K have power management enabled */
+        if (ar3kconfig.PwrMgmtEnabled) {
+            status = HCI_TransportEnablePowerMgmt(pHcidevInfo->pHCIDev, TRUE);
+            if (A_FAILED(status)) {
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("HCI Bridge: failed to enable TLPM for AR6K! \n"));
+            }
+        }
+        
+        status = bt_register_hci(pHcidevInfo);
+        
+    } while (FALSE);
+
+    return status; 
+}
+
+static void ar6000_hci_transport_failure(void *pContext, A_STATUS Status)
+{
+    AR6K_HCI_BRIDGE_INFO *pHcidevInfo = (AR6K_HCI_BRIDGE_INFO *)pContext;
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("HCI Bridge: transport failure! \n"));
+    
+    if (pHcidevInfo->HciNormalMode) {
+        /* TODO .. */    
+    }
+}
+
+static void ar6000_hci_transport_removed(void *pContext)
+{
+    AR6K_HCI_BRIDGE_INFO *pHcidevInfo = (AR6K_HCI_BRIDGE_INFO *)pContext;
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_HCI_BRIDGE, ("HCI Bridge: transport removed. \n"));
+    
+    A_ASSERT(pHcidevInfo->pHCIDev != NULL);
+        
+    HCI_TransportDetach(pHcidevInfo->pHCIDev);
+    bt_cleanup_hci(pHcidevInfo);
+    pHcidevInfo->pHCIDev = NULL;
+}
+
+static void ar6000_hci_send_complete(void *pContext, HTC_PACKET *pPacket)
+{
+    AR6K_HCI_BRIDGE_INFO *pHcidevInfo = (AR6K_HCI_BRIDGE_INFO *)pContext;
+    void                 *osbuf = pPacket->pPktContext;
+    A_ASSERT(osbuf != NULL);
+    A_ASSERT(pHcidevInfo != NULL);
+    
+    if (A_FAILED(pPacket->Status)) {
+        if ((pPacket->Status != A_ECANCELED) && (pPacket->Status != A_NO_RESOURCE)) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("HCI Bridge: Send Packet Failed: %d \n",pPacket->Status)); 
+        }   
+    }
+            
+    FreeHTCStruct(pHcidevInfo,pPacket);    
+    FreeBtOsBuf(pHcidevInfo,osbuf);
+    
+}
+
+static void ar6000_hci_pkt_recv(void *pContext, HTC_PACKET *pPacket)
+{
+    AR6K_HCI_BRIDGE_INFO *pHcidevInfo = (AR6K_HCI_BRIDGE_INFO *)pContext;
+    struct sk_buff       *skb;
+    
+    A_ASSERT(pHcidevInfo != NULL);
+    skb = (struct sk_buff *)pPacket->pPktContext;
+    A_ASSERT(skb != NULL);
+          
+    do {
+        
+        if (A_FAILED(pPacket->Status)) {
+            break;
+        }
+  
+        AR_DEBUG_PRINTF(ATH_DEBUG_HCI_RECV, 
+                        ("HCI Bridge, packet received type : %d len:%d \n",
+                        HCI_GET_PACKET_TYPE(pPacket),pPacket->ActualLength));
+    
+            /* set the actual buffer position in the os buffer, HTC recv buffers posted to HCI are set
+             * to fill the front of the buffer */
+        A_NETBUF_PUT(skb,pPacket->ActualLength + pHcidevInfo->HCIProps.HeadRoom);
+        A_NETBUF_PULL(skb,pHcidevInfo->HCIProps.HeadRoom);
+        
+        if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_HCI_DUMP)) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ANY,("<<< Recv HCI %s packet len:%d \n",
+                        (HCI_GET_PACKET_TYPE(pPacket) == HCI_EVENT_TYPE) ? "EVENT" : "ACL",
+                        skb->len));
+            AR_DEBUG_PRINTBUF(skb->data, skb->len,"BT HCI RECV Packet Dump");
+        }
+        
+        if (pHcidevInfo->HciNormalMode) {
+                /* indicate the packet */         
+            if (bt_indicate_recv(pHcidevInfo,HCI_GET_PACKET_TYPE(pPacket),skb)) {
+                    /* bt stack accepted the packet */
+                skb = NULL;
+            }  
+            break;
+        }
+        
+            /* for testing, indicate packet to the network stack */ 
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+        skb->dev = (struct net_device *)(pHcidevInfo->HCITransHdl.netDevice);        
+        if ((((struct net_device *)pHcidevInfo->HCITransHdl.netDevice)->flags & IFF_UP) == IFF_UP) {
+            skb->protocol = eth_type_trans(skb, (struct net_device *)(pHcidevInfo->HCITransHdl.netDevice));
+#else
+        skb->dev = pHcidevInfo->ar->arNetDev;        
+        if ((pHcidevInfo->ar->arNetDev->flags & IFF_UP) == IFF_UP) {
+            skb->protocol = eth_type_trans(skb, pHcidevInfo->ar->arNetDev);
+#endif
+            netif_rx(skb);
+            skb = NULL;
+        } 
+        
+    } while (FALSE);
+    
+    FreeHTCStruct(pHcidevInfo,pPacket);
+    
+    if (skb != NULL) {
+            /* packet was not accepted, free it */
+        FreeBtOsBuf(pHcidevInfo,skb);       
+    }
+    
+}
+
+static void  ar6000_hci_pkt_refill(void *pContext, HCI_TRANSPORT_PACKET_TYPE Type, int BuffersAvailable)
+{
+    AR6K_HCI_BRIDGE_INFO *pHcidevInfo = (AR6K_HCI_BRIDGE_INFO *)pContext;
+    int                  refillCount;
+
+    if (Type == HCI_ACL_TYPE) {
+        refillCount =  MAX_ACL_RECV_BUFS - BuffersAvailable;   
+    } else {
+        refillCount =  MAX_EVT_RECV_BUFS - BuffersAvailable;     
+    }
+    
+    if (refillCount > 0) {
+        RefillRecvBuffers(pHcidevInfo,Type,refillCount);
+    }
+    
+}
+
+static HCI_SEND_FULL_ACTION  ar6000_hci_pkt_send_full(void *pContext, HTC_PACKET *pPacket)
+{
+    AR6K_HCI_BRIDGE_INFO    *pHcidevInfo = (AR6K_HCI_BRIDGE_INFO *)pContext;
+    HCI_SEND_FULL_ACTION    action = HCI_SEND_FULL_KEEP;
+    
+    if (!pHcidevInfo->HciNormalMode) {
+            /* for epping testing, check packet tag, some epping packets are
+             * special and cannot be dropped */
+        if (HTC_GET_TAG_FROM_PKT(pPacket) == AR6K_DATA_PKT_TAG) {
+            action = HCI_SEND_FULL_DROP;     
+        }
+    }
+    
+    return action;
+}
+
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+A_STATUS ar6000_setup_hci(void *ar)
+#else
+A_STATUS ar6000_setup_hci(AR_SOFTC_T *ar)
+#endif
+{
+    HCI_TRANSPORT_CONFIG_INFO config;
+    A_STATUS                  status = A_OK;
+    int                       i;
+    HTC_PACKET                *pPacket;
+    AR6K_HCI_BRIDGE_INFO      *pHcidevInfo;
+        
+       
+    do {
+        
+        pHcidevInfo = (AR6K_HCI_BRIDGE_INFO *)A_MALLOC(sizeof(AR6K_HCI_BRIDGE_INFO));
+        
+        if (NULL == pHcidevInfo) {
+            status = A_NO_MEMORY;
+            break;    
+        }
+        
+        A_MEMZERO(pHcidevInfo, sizeof(AR6K_HCI_BRIDGE_INFO));
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+        g_pHcidevInfo = pHcidevInfo;
+        pHcidevInfo->HCITransHdl = *(HCI_TRANSPORT_MISC_HANDLES *)ar;
+#else
+        ar->hcidev_info = pHcidevInfo;
+        pHcidevInfo->ar = ar;
+#endif
+        spin_lock_init(&pHcidevInfo->BridgeLock);
+        INIT_HTC_PACKET_QUEUE(&pHcidevInfo->HTCPacketStructHead);
+
+        ar->exitCallback = AR3KConfigureExit;
+    
+        status = bt_setup_hci(pHcidevInfo);
+        if (A_FAILED(status)) {
+            break;    
+        }
+        
+        if (pHcidevInfo->HciNormalMode) {      
+            AR_DEBUG_PRINTF(ATH_DEBUG_HCI_BRIDGE, ("HCI Bridge: running in normal mode... \n"));    
+        } else {
+            AR_DEBUG_PRINTF(ATH_DEBUG_HCI_BRIDGE, ("HCI Bridge: running in test mode... \n"));     
+        }
+        
+        pHcidevInfo->pHTCStructAlloc = (A_UINT8 *)A_MALLOC((sizeof(HTC_PACKET)) * NUM_HTC_PACKET_STRUCTS);
+        
+        if (NULL == pHcidevInfo->pHTCStructAlloc) {
+            status = A_NO_MEMORY;
+            break;    
+        }
+        
+        pPacket = (HTC_PACKET *)pHcidevInfo->pHTCStructAlloc;
+        for (i = 0; i < NUM_HTC_PACKET_STRUCTS; i++,pPacket++) {
+            FreeHTCStruct(pHcidevInfo,pPacket);                
+        }
+        
+        A_MEMZERO(&config,sizeof(HCI_TRANSPORT_CONFIG_INFO));        
+        config.ACLRecvBufferWaterMark = MAX_ACL_RECV_BUFS / 2;
+        config.EventRecvBufferWaterMark = MAX_EVT_RECV_BUFS / 2;
+        config.MaxSendQueueDepth = MAX_HCI_WRITE_QUEUE_DEPTH;
+        config.pContext = pHcidevInfo;    
+        config.TransportFailure = ar6000_hci_transport_failure;
+        config.TransportReady = ar6000_hci_transport_ready;
+        config.TransportRemoved = ar6000_hci_transport_removed;
+        config.pHCISendComplete = ar6000_hci_send_complete;
+        config.pHCIPktRecv = ar6000_hci_pkt_recv;
+        config.pHCIPktRecvRefill = ar6000_hci_pkt_refill;
+        config.pHCISendFull = ar6000_hci_pkt_send_full;
+       
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+        pHcidevInfo->pHCIDev = HCI_TransportAttach(pHcidevInfo->HCITransHdl.htcHandle, &config);
+#else
+        pHcidevInfo->pHCIDev = HCI_TransportAttach(ar->arHtcTarget, &config);
+#endif
+
+        if (NULL == pHcidevInfo->pHCIDev) {
+            status = A_ERROR;      
+        }
+    
+    } while (FALSE);
+    
+    if (A_FAILED(status)) {
+        if (pHcidevInfo != NULL) {
+            if (NULL == pHcidevInfo->pHCIDev) {
+                /* GMBOX may not be present in older chips */
+                /* just return success */ 
+                status = A_OK;
+            }
+        }
+        ar6000_cleanup_hci(ar);    
+    }
+    
+    return status;
+}
+
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+void  ar6000_cleanup_hci(void *ar)
+#else
+void  ar6000_cleanup_hci(AR_SOFTC_T *ar)
+#endif
+{
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+    AR6K_HCI_BRIDGE_INFO *pHcidevInfo = g_pHcidevInfo;
+#else
+    AR6K_HCI_BRIDGE_INFO *pHcidevInfo = (AR6K_HCI_BRIDGE_INFO *)ar->hcidev_info;
+#endif
+    
+    if (pHcidevInfo != NULL) {
+        bt_cleanup_hci(pHcidevInfo);   
+        
+        if (pHcidevInfo->pHCIDev != NULL) {
+            HCI_TransportStop(pHcidevInfo->pHCIDev);
+            HCI_TransportDetach(pHcidevInfo->pHCIDev);
+            pHcidevInfo->pHCIDev = NULL;
+        } 
+        
+        if (pHcidevInfo->pHTCStructAlloc != NULL) {
+            A_FREE(pHcidevInfo->pHTCStructAlloc);
+            pHcidevInfo->pHTCStructAlloc = NULL;    
+        }
+        
+        A_FREE(pHcidevInfo);
+#ifndef EXPORT_HCI_BRIDGE_INTERFACE
+        ar->hcidev_info = NULL;
+#endif
+    }
+    
+    
+}
+
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+A_STATUS hci_test_send(void *ar, struct sk_buff *skb)
+#else
+A_STATUS hci_test_send(AR_SOFTC_T *ar, struct sk_buff *skb)
+#endif
+{
+    int              status = A_OK;
+    int              length;
+    EPPING_HEADER    *pHeader;
+    HTC_PACKET       *pPacket;   
+    HTC_TX_TAG       htc_tag = AR6K_DATA_PKT_TAG;
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+    AR6K_HCI_BRIDGE_INFO *pHcidevInfo = g_pHcidevInfo;
+#else
+    AR6K_HCI_BRIDGE_INFO *pHcidevInfo = (AR6K_HCI_BRIDGE_INFO *)ar->hcidev_info;
+#endif
+            
+    do {
+        
+        if (NULL == pHcidevInfo) {
+            status = A_ERROR;
+            break;    
+        }
+        
+        if (NULL == pHcidevInfo->pHCIDev) {
+            status = A_ERROR;
+            break;    
+        }
+        
+        if (pHcidevInfo->HciNormalMode) {
+                /* this interface cannot run when normal WMI is running */
+            status = A_ERROR;
+            break;    
+        }
+        
+        pHeader = (EPPING_HEADER *)A_NETBUF_DATA(skb);
+        
+        if (!IS_EPPING_PACKET(pHeader)) {
+            status = A_EINVAL;
+            break;
+        }
+                       
+        if (IS_EPING_PACKET_NO_DROP(pHeader)) {
+            htc_tag = AR6K_CONTROL_PKT_TAG;   
+        }
+        
+        length = sizeof(EPPING_HEADER) + pHeader->DataLength;
+                
+        pPacket = AllocHTCStruct(pHcidevInfo);
+        if (NULL == pPacket) {        
+            status = A_NO_MEMORY;
+            break;
+        } 
+     
+        SET_HTC_PACKET_INFO_TX(pPacket,
+                               skb,
+                               A_NETBUF_DATA(skb),
+                               length,
+                               HCI_ACL_TYPE,  /* send every thing out as ACL */
+                               htc_tag);
+             
+        HCI_TransportSendPkt(pHcidevInfo->pHCIDev,pPacket,FALSE);                           
+        pPacket = NULL;
+            
+    } while (FALSE);
+            
+    return status;
+}
+
+void ar6000_set_default_ar3kconfig(AR_SOFTC_T *ar, void *ar3kconfig)
+{
+    AR6K_HCI_BRIDGE_INFO *pHcidevInfo = (AR6K_HCI_BRIDGE_INFO *)ar->hcidev_info;
+    AR3K_CONFIG_INFO *config = (AR3K_CONFIG_INFO *)ar3kconfig;
+
+    config->pHCIDev = pHcidevInfo->pHCIDev;
+    config->pHCIProps = &pHcidevInfo->HCIProps;
+    config->pHIFDevice = ar->arHifDevice;
+    config->pBtStackHCIDev = pHcidevInfo->pBtStackHCIDev;
+    config->Flags |= AR3K_CONFIG_FLAG_SET_AR3K_BAUD;
+    config->AR3KBaudRate = 115200;    
+}
+
+#ifdef CONFIG_BLUEZ_HCI_BRIDGE   
+/*** BT Stack Entrypoints *******/
+
+/*
+ * bt_open - open a handle to the device
+*/
+static int bt_open(struct hci_dev *hdev)
+{
+ 
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HCI Bridge: bt_open - enter - x\n"));
+    set_bit(HCI_RUNNING, &hdev->flags);
+    set_bit(HCI_UP, &hdev->flags);
+    set_bit(HCI_INIT, &hdev->flags);         
+    return 0;
+}
+
+/*
+ * bt_close - close handle to the device
+*/
+static int bt_close(struct hci_dev *hdev)
+{
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HCI Bridge: bt_close - enter\n"));
+    clear_bit(HCI_RUNNING, &hdev->flags);
+    return 0;
+}
+
+/*
+ * bt_send_frame - send data frames
+*/
+static int bt_send_frame(struct sk_buff *skb)
+{
+    struct hci_dev             *hdev = (struct hci_dev *)skb->dev;
+    HCI_TRANSPORT_PACKET_TYPE  type;
+    AR6K_HCI_BRIDGE_INFO       *pHcidevInfo;
+    HTC_PACKET                 *pPacket;
+    A_STATUS                   status = A_OK;
+    struct sk_buff             *txSkb = NULL;
+    
+    if (!hdev) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_WARN, ("HCI Bridge: bt_send_frame - no device\n"));
+        return -ENODEV;
+    }
+      
+    if (!test_bit(HCI_RUNNING, &hdev->flags)) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HCI Bridge: bt_send_frame - not open\n"));
+        return -EBUSY;
+    }
+  
+    pHcidevInfo = (AR6K_HCI_BRIDGE_INFO *)hdev->driver_data;   
+    A_ASSERT(pHcidevInfo != NULL);
+      
+    AR_DEBUG_PRINTF(ATH_DEBUG_HCI_SEND, ("+bt_send_frame type: %d \n",bt_cb(skb)->pkt_type));
+    type = HCI_COMMAND_TYPE;
+    
+    switch (bt_cb(skb)->pkt_type) {
+        case HCI_COMMAND_PKT:
+            type = HCI_COMMAND_TYPE;
+            hdev->stat.cmd_tx++;
+            break;
+ 
+        case HCI_ACLDATA_PKT:
+            type = HCI_ACL_TYPE;
+            hdev->stat.acl_tx++;
+            break;
+
+        case HCI_SCODATA_PKT:
+            /* we don't support SCO over the bridge */
+            kfree_skb(skb);
+            return 0;
+        default:
+            A_ASSERT(FALSE);
+            kfree_skb(skb);
+            return 0;
+    } 
+
+    if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_HCI_DUMP)) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ANY,(">>> Send HCI %s packet len: %d\n",
+                        (type == HCI_COMMAND_TYPE) ? "COMMAND" : "ACL",
+                        skb->len));
+        if (type == HCI_COMMAND_TYPE) {
+            A_UINT16 opcode = HCI_GET_OP_CODE(skb->data);
+            AR_DEBUG_PRINTF(ATH_DEBUG_ANY,("    HCI Command: OGF:0x%X OCF:0x%X \r\n", 
+                  opcode >> 10, opcode & 0x3FF));
+        }
+        AR_DEBUG_PRINTBUF(skb->data,skb->len,"BT HCI SEND Packet Dump");
+    }
+    
+    do {
+        
+        txSkb = bt_skb_alloc(TX_PACKET_RSV_OFFSET + pHcidevInfo->HCIProps.HeadRoom + 
+                             pHcidevInfo->HCIProps.TailRoom + skb->len, 
+                             GFP_ATOMIC);
+
+        if (txSkb == NULL) {
+            status = A_NO_MEMORY;
+            break;    
+        }
+        
+        bt_cb(txSkb)->pkt_type = bt_cb(skb)->pkt_type;
+        txSkb->dev = (void *)pHcidevInfo->pBtStackHCIDev;
+        skb_reserve(txSkb, TX_PACKET_RSV_OFFSET + pHcidevInfo->HCIProps.HeadRoom);
+        A_MEMCPY(txSkb->data, skb->data, skb->len);
+        skb_put(txSkb,skb->len);
+        
+        pPacket = AllocHTCStruct(pHcidevInfo);        
+        if (NULL == pPacket) {
+            status = A_NO_MEMORY;
+            break;    
+        }       
+              
+        /* HCI packet length here doesn't include the 1-byte transport header which
+         * will be handled by the HCI transport layer. Enough headroom has already
+         * been reserved above for the transport header
+         */
+        SET_HTC_PACKET_INFO_TX(pPacket,
+                               txSkb,
+                               txSkb->data,
+                               txSkb->len,
+                               type, 
+                               AR6K_CONTROL_PKT_TAG); /* HCI packets cannot be dropped */
+        
+        AR_DEBUG_PRINTF(ATH_DEBUG_HCI_SEND, ("HCI Bridge: bt_send_frame skb:0x%lX \n",(unsigned long)txSkb));
+        AR_DEBUG_PRINTF(ATH_DEBUG_HCI_SEND, ("HCI Bridge: type:%d, Total Length:%d Bytes \n",
+                                      type, txSkb->len));
+                                      
+        status = HCI_TransportSendPkt(pHcidevInfo->pHCIDev,pPacket,FALSE);   
+        pPacket = NULL;
+        txSkb = NULL;
+        
+    } while (FALSE);
+   
+    if (txSkb != NULL) {
+        kfree_skb(txSkb);    
+    }
+    
+    kfree_skb(skb);        
+       
+    AR_DEBUG_PRINTF(ATH_DEBUG_HCI_SEND, ("-bt_send_frame  \n"));
+    return 0;
+}
+
+/*
+ * bt_ioctl - ioctl processing
+*/
+static int bt_ioctl(struct hci_dev *hdev, unsigned int cmd, unsigned long arg)
+{
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HCI Bridge: bt_ioctl - enter\n"));
+    return -ENOIOCTLCMD;
+}
+
+/*
+ * bt_flush - flush outstandingbpackets
+*/
+static int bt_flush(struct hci_dev *hdev)
+{
+    AR6K_HCI_BRIDGE_INFO    *pHcidevInfo; 
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HCI Bridge: bt_flush - enter\n"));
+    
+    pHcidevInfo = (AR6K_HCI_BRIDGE_INFO *)hdev->driver_data;   
+    
+    /* TODO??? */   
+    
+    return 0;
+}
+
+
+/*
+ * bt_destruct - 
+*/
+static void bt_destruct(struct hci_dev *hdev)
+{
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HCI Bridge: bt_destruct - enter\n"));
+    /* nothing to do here */
+}
+
+static A_STATUS bt_setup_hci(AR6K_HCI_BRIDGE_INFO *pHcidevInfo)
+{
+    A_STATUS                    status = A_OK;
+    struct hci_dev              *pHciDev = NULL;
+    HIF_DEVICE_OS_DEVICE_INFO   osDevInfo;
+    
+    if (!setupbtdev) {
+        return A_OK;    
+    } 
+        
+    do {
+            
+        A_MEMZERO(&osDevInfo,sizeof(osDevInfo));
+            /* get the underlying OS device */
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+        status = ar6000_get_hif_dev((HIF_DEVICE *)(pHcidevInfo->HCITransHdl.hifDevice), 
+                                    &osDevInfo);
+#else
+        status = HIFConfigureDevice(pHcidevInfo->ar->arHifDevice, 
+                                    HIF_DEVICE_GET_OS_DEVICE,
+                                    &osDevInfo, 
+                                    sizeof(osDevInfo));
+#endif
+                                    
+        if (A_FAILED(status)) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Failed to OS device info from HIF\n"));
+            break;
+        }
+        
+            /* allocate a BT HCI struct for this device */
+        pHciDev = hci_alloc_dev();
+        if (NULL == pHciDev) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("HCI Bridge - failed to allocate bt struct \n"));
+            status = A_NO_MEMORY;
+            break;
+        }    
+            /* save the device, we'll register this later */
+        pHcidevInfo->pBtStackHCIDev = pHciDev;       
+        SET_HCIDEV_DEV(pHciDev,osDevInfo.pOSDevice);          
+        SET_HCI_BUS_TYPE(pHciDev, HCI_VIRTUAL, HCI_BREDR);
+        pHciDev->driver_data = pHcidevInfo;
+        pHciDev->open     = bt_open;
+        pHciDev->close    = bt_close;
+        pHciDev->send     = bt_send_frame;
+        pHciDev->ioctl    = bt_ioctl;
+        pHciDev->flush    = bt_flush;
+        pHciDev->destruct = bt_destruct;
+        pHciDev->owner = THIS_MODULE; 
+            /* driver is running in normal BT mode */
+        pHcidevInfo->HciNormalMode = TRUE;  
+        
+    } while (FALSE);
+    
+    if (A_FAILED(status)) {
+        bt_cleanup_hci(pHcidevInfo);    
+    }
+    
+    return status;
+}
+
+static void bt_cleanup_hci(AR6K_HCI_BRIDGE_INFO *pHcidevInfo)
+{   
+    int   err;      
+        
+    if (pHcidevInfo->HciRegistered) {
+        pHcidevInfo->HciRegistered = FALSE;
+        clear_bit(HCI_RUNNING, &pHcidevInfo->pBtStackHCIDev->flags);
+        clear_bit(HCI_UP, &pHcidevInfo->pBtStackHCIDev->flags);
+        clear_bit(HCI_INIT, &pHcidevInfo->pBtStackHCIDev->flags);   
+        A_ASSERT(pHcidevInfo->pBtStackHCIDev != NULL);
+            /* unregister */
+        if ((err = hci_unregister_dev(pHcidevInfo->pBtStackHCIDev)) < 0) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("HCI Bridge: failed to unregister with bluetooth %d\n",err));
+        }          
+    }   
+    
+    if (pHcidevInfo->pBtStackHCIDev != NULL) {
+        kfree(pHcidevInfo->pBtStackHCIDev);
+        pHcidevInfo->pBtStackHCIDev = NULL;
+    }  
+}
+
+static A_STATUS bt_register_hci(AR6K_HCI_BRIDGE_INFO *pHcidevInfo)
+{
+    int       err;
+    A_STATUS  status = A_OK;
+    
+    do {          
+        AR_DEBUG_PRINTF(ATH_DEBUG_HCI_BRIDGE, ("HCI Bridge: registering HCI... \n"));
+        A_ASSERT(pHcidevInfo->pBtStackHCIDev != NULL);
+             /* mark that we are registered */
+        pHcidevInfo->HciRegistered = TRUE;
+        if ((err = hci_register_dev(pHcidevInfo->pBtStackHCIDev)) < 0) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("HCI Bridge: failed to register with bluetooth %d\n",err));
+            pHcidevInfo->HciRegistered = FALSE;
+            status = A_ERROR;
+            break;
+        }
+    
+        AR_DEBUG_PRINTF(ATH_DEBUG_HCI_BRIDGE, ("HCI Bridge: HCI registered \n"));
+        
+    } while (FALSE);
+    
+    return status;
+}
+
+static A_BOOL bt_indicate_recv(AR6K_HCI_BRIDGE_INFO      *pHcidevInfo, 
+                               HCI_TRANSPORT_PACKET_TYPE Type, 
+                               struct                    sk_buff *skb)
+{
+    A_UINT8               btType;
+    int                   len;
+    A_BOOL                success = FALSE;
+    BT_HCI_EVENT_HEADER   *pEvent;
+    
+    do {
+             
+        if (!test_bit(HCI_RUNNING, &pHcidevInfo->pBtStackHCIDev->flags)) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_WARN, ("HCI Bridge: bt_indicate_recv - not running\n"));
+            break;
+        }
+    
+        switch (Type) {
+            case HCI_ACL_TYPE:
+                btType = HCI_ACLDATA_PKT;
+                break;
+            case HCI_EVENT_TYPE:  
+                btType = HCI_EVENT_PKT;  
+                break;
+            default:
+                btType = 0;
+                A_ASSERT(FALSE);
+                break;
+        } 
+        
+        if (0 == btType) {
+            break;    
+        }
+        
+            /* set the final type */
+        bt_cb(skb)->pkt_type = btType;
+            /* set dev */
+        skb->dev = (void *)pHcidevInfo->pBtStackHCIDev;
+        len = skb->len;
+        
+        if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_HCI_RECV)) {
+            if (bt_cb(skb)->pkt_type == HCI_EVENT_PKT) {                
+                pEvent = (BT_HCI_EVENT_HEADER *)skb->data; 
+                AR_DEBUG_PRINTF(ATH_DEBUG_HCI_RECV, ("BT HCI EventCode: %d, len:%d \n", 
+                        pEvent->EventCode, pEvent->ParamLength));
+            } 
+        }
+        
+            /* pass receive packet up the stack */    
+        if (hci_recv_frame(skb) != 0) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("HCI Bridge: hci_recv_frame failed \n"));
+            break;
+        } else {
+            AR_DEBUG_PRINTF(ATH_DEBUG_HCI_RECV, 
+                    ("HCI Bridge: Indicated RCV of type:%d, Length:%d \n",btType,len));
+        }
+            
+        success = TRUE;
+    
+    } while (FALSE); 
+    
+    return success;
+}
+
+static struct sk_buff* bt_alloc_buffer(AR6K_HCI_BRIDGE_INFO *pHcidevInfo, int Length) 
+{ 
+    struct sk_buff *skb;         
+        /* in normal HCI mode we need to alloc from the bt core APIs */
+    skb = bt_skb_alloc(Length, GFP_ATOMIC);
+    if (NULL == skb) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Failed to alloc bt sk_buff \n"));
+    }
+    return skb;
+}
+
+static void bt_free_buffer(AR6K_HCI_BRIDGE_INFO *pHcidevInfo, struct sk_buff *skb)
+{
+    kfree_skb(skb);    
+}
+
+#else // { CONFIG_BLUEZ_HCI_BRIDGE
+
+    /* stubs when we only want to test the HCI bridging Interface without the HT stack */
+static A_STATUS bt_setup_hci(AR6K_HCI_BRIDGE_INFO *pHcidevInfo)
+{
+    return A_OK;    
+}
+static void bt_cleanup_hci(AR6K_HCI_BRIDGE_INFO *pHcidevInfo)
+{   
+     
+}
+static A_STATUS bt_register_hci(AR6K_HCI_BRIDGE_INFO *pHcidevInfo)
+{
+    A_ASSERT(FALSE);
+    return A_ERROR;    
+}
+
+static A_BOOL bt_indicate_recv(AR6K_HCI_BRIDGE_INFO      *pHcidevInfo, 
+                               HCI_TRANSPORT_PACKET_TYPE Type, 
+                               struct                    sk_buff *skb)
+{
+    A_ASSERT(FALSE);
+    return FALSE;    
+}
+
+static struct sk_buff* bt_alloc_buffer(AR6K_HCI_BRIDGE_INFO *pHcidevInfo, int Length) 
+{
+    A_ASSERT(FALSE);
+    return NULL;
+}
+static void bt_free_buffer(AR6K_HCI_BRIDGE_INFO *pHcidevInfo, struct sk_buff *skb)
+{
+    A_ASSERT(FALSE);
+}
+
+#endif // } CONFIG_BLUEZ_HCI_BRIDGE
+
+#else  // { ATH_AR6K_ENABLE_GMBOX
+
+    /* stubs when GMBOX support is not needed */
+    
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+A_STATUS ar6000_setup_hci(void *ar)
+#else
+A_STATUS ar6000_setup_hci(AR_SOFTC_T *ar)
+#endif
+{
+    return A_OK;   
+}
+
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+void ar6000_cleanup_hci(void *ar)
+#else
+void ar6000_cleanup_hci(AR_SOFTC_T *ar)
+#endif
+{
+    return;    
+}
+
+#ifndef EXPORT_HCI_BRIDGE_INTERFACE
+void ar6000_set_default_ar3kconfig(AR_SOFTC_T *ar, void *ar3kconfig)
+{
+    return;
+}
+#endif
+
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+int hci_test_send(void *ar, struct sk_buff *skb)
+#else
+int hci_test_send(AR_SOFTC_T *ar, struct sk_buff *skb)
+#endif
+{
+    return -EOPNOTSUPP;
+}
+
+#endif // } ATH_AR6K_ENABLE_GMBOX
+
+
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+static int __init
+hcibridge_init_module(void)
+{
+    A_STATUS status;
+    HCI_TRANSPORT_CALLBACKS hciTransCallbacks;
+
+    hciTransCallbacks.setupTransport = ar6000_setup_hci;
+    hciTransCallbacks.cleanupTransport = ar6000_cleanup_hci;
+
+    status = ar6000_register_hci_transport(&hciTransCallbacks);
+    if(status != A_OK)
+        return -ENODEV;
+
+    return 0;
+}
+
+static void __exit
+hcibridge_cleanup_module(void)
+{
+}
+
+module_init(hcibridge_init_module);
+module_exit(hcibridge_cleanup_module);
+MODULE_LICENSE("Dual BSD/GPL");
+#endif
diff --git a/drivers/net/ath6kl/os/linux/include/ar6000_drv.h b/drivers/net/ath6kl/os/linux/include/ar6000_drv.h
new file mode 100644
index 00000000000..e6248830b7e
--- /dev/null
+++ b/drivers/net/ath6kl/os/linux/include/ar6000_drv.h
@@ -0,0 +1,762 @@
+//------------------------------------------------------------------------------
+// Copyright (c) 2004-2010 Atheros Communications Inc.
+// All rights reserved.
+//
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//
+// Author(s): ="Atheros"
+//------------------------------------------------------------------------------
+
+#ifndef _AR6000_H_
+#define _AR6000_H_
+
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/spinlock.h>
+#include <linux/if_ether.h>
+#include <linux/etherdevice.h>
+#include <net/iw_handler.h>
+#include <linux/if_arp.h>
+#include <linux/ip.h>
+#include <linux/wireless.h>
+#ifdef ATH6K_CONFIG_CFG80211
+#include <net/cfg80211.h>
+#endif /* ATH6K_CONFIG_CFG80211 */
+#include <linux/module.h>
+#include <asm/io.h>
+
+#include <a_config.h>
+#include <athdefs.h>
+#include "a_types.h"
+#include "a_osapi.h"
+#include "htc_api.h"
+#include "wmi.h"
+#include "a_drv.h"
+#include "bmi.h"
+#include <ieee80211.h>
+#include <ieee80211_ioctl.h>
+#include <wlan_api.h>
+#include <wmi_api.h>
+#include "gpio_api.h"
+#include "gpio.h"
+#include "pkt_log.h"
+#include "aggr_recv_api.h"
+#include <host_version.h>
+#include <linux/rtnetlink.h>
+#include <linux/init.h>
+#include <linux/moduleparam.h>
+#include "ar6000_api.h"
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+#include <testcmd.h>
+#endif
+#include <linux/firmware.h>
+
+#include "targaddrs.h"
+#include "dbglog_api.h"
+#include "ar6000_diag.h"
+#include "common_drv.h"
+#include "roaming.h"
+#include "hci_transport_api.h"
+#define ATH_MODULE_NAME driver
+#include "a_debug.h"
+#include "hw/apb_map.h"
+#include "hw/rtc_reg.h"
+#include "hw/mbox_reg.h"
+#include "hw/gpio_reg.h"
+
+#define  ATH_DEBUG_DBG_LOG       ATH_DEBUG_MAKE_MODULE_MASK(0)
+#define  ATH_DEBUG_WLAN_CONNECT  ATH_DEBUG_MAKE_MODULE_MASK(1)
+#define  ATH_DEBUG_WLAN_SCAN     ATH_DEBUG_MAKE_MODULE_MASK(2)
+#define  ATH_DEBUG_WLAN_TX       ATH_DEBUG_MAKE_MODULE_MASK(3)
+#define  ATH_DEBUG_WLAN_RX       ATH_DEBUG_MAKE_MODULE_MASK(4)
+#define  ATH_DEBUG_HTC_RAW       ATH_DEBUG_MAKE_MODULE_MASK(5)
+#define  ATH_DEBUG_HCI_BRIDGE    ATH_DEBUG_MAKE_MODULE_MASK(6)
+#define  ATH_DEBUG_HCI_RECV      ATH_DEBUG_MAKE_MODULE_MASK(7)
+#define  ATH_DEBUG_HCI_SEND      ATH_DEBUG_MAKE_MODULE_MASK(8)
+#define  ATH_DEBUG_HCI_DUMP      ATH_DEBUG_MAKE_MODULE_MASK(9)
+
+#ifndef  __dev_put
+#define  __dev_put(dev) dev_put(dev)
+#endif
+
+
+#ifdef USER_KEYS
+
+#define USER_SAVEDKEYS_STAT_INIT     0
+#define USER_SAVEDKEYS_STAT_RUN      1
+
+// TODO this needs to move into the AR_SOFTC struct
+struct USER_SAVEDKEYS {
+    struct ieee80211req_key   ucast_ik;
+    struct ieee80211req_key   bcast_ik;
+    CRYPTO_TYPE               keyType;
+    A_BOOL                    keyOk;
+};
+#endif
+
+#define DBG_INFO        0x00000001
+#define DBG_ERROR       0x00000002
+#define DBG_WARNING     0x00000004
+#define DBG_SDIO        0x00000008
+#define DBG_HIF         0x00000010
+#define DBG_HTC         0x00000020
+#define DBG_WMI         0x00000040
+#define DBG_WMI2        0x00000080
+#define DBG_DRIVER      0x00000100
+
+#define DBG_DEFAULTS    (DBG_ERROR|DBG_WARNING)
+
+
+A_STATUS ar6000_ReadRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data);
+A_STATUS ar6000_WriteRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data);
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define MAX_AR6000                        1
+#define AR6000_MAX_RX_BUFFERS             16
+#define AR6000_BUFFER_SIZE                1664
+#define AR6000_MAX_AMSDU_RX_BUFFERS       4
+#define AR6000_AMSDU_REFILL_THRESHOLD     3
+#define AR6000_AMSDU_BUFFER_SIZE          (WMI_MAX_AMSDU_RX_DATA_FRAME_LENGTH + 128)
+#define AR6000_MAX_RX_MESSAGE_SIZE        (max(WMI_MAX_NORMAL_RX_DATA_FRAME_LENGTH,WMI_MAX_AMSDU_RX_DATA_FRAME_LENGTH))
+
+#define AR6000_TX_TIMEOUT                 10
+#define AR6000_ETH_ADDR_LEN               6
+#define AR6000_MAX_ENDPOINTS              4
+#define MAX_NODE_NUM                      15
+/* MAX_HI_COOKIE_NUM are reserved for high priority traffic */
+#define MAX_DEF_COOKIE_NUM                180
+#define MAX_HI_COOKIE_NUM                 18 /* 10% of MAX_COOKIE_NUM */
+#define MAX_COOKIE_NUM                    (MAX_DEF_COOKIE_NUM + MAX_HI_COOKIE_NUM)
+
+/* MAX_DEFAULT_SEND_QUEUE_DEPTH is used to set the default queue depth for the
+ * WMM send queues.  If a queue exceeds this depth htc will query back to the
+ * OS specific layer by calling EpSendFull().  This gives the OS layer the
+ * opportunity to drop the packet if desired.  Therefore changing
+ * MAX_DEFAULT_SEND_QUEUE_DEPTH does not affect resource utilization but
+ * does impact the threshold used to identify if a packet should be
+ * dropped. */
+#define MAX_DEFAULT_SEND_QUEUE_DEPTH      (MAX_DEF_COOKIE_NUM / WMM_NUM_AC)
+
+#define AR6000_HB_CHALLENGE_RESP_FREQ_DEFAULT        1
+#define AR6000_HB_CHALLENGE_RESP_MISS_THRES_DEFAULT  1
+#define A_DISCONNECT_TIMER_INTERVAL       10 * 1000
+#define A_DEFAULT_LISTEN_INTERVAL         100
+#define A_MAX_WOW_LISTEN_INTERVAL         1000
+
+enum {
+    DRV_HB_CHALLENGE = 0,
+    APP_HB_CHALLENGE
+};
+
+enum {
+    WLAN_INIT_MODE_NONE = 0,
+    WLAN_INIT_MODE_USR,
+    WLAN_INIT_MODE_UDEV,
+    WLAN_INIT_MODE_DRV
+};
+
+/* Suspend - configuration */
+enum {
+    WLAN_SUSPEND_CUT_PWR = 0,
+    WLAN_SUSPEND_DEEP_SLEEP,
+    WLAN_SUSPEND_WOW,
+    WLAN_SUSPEND_CUT_PWR_IF_BT_OFF
+};
+
+/* WiFi OFF - configuration */
+enum {
+    WLAN_OFF_CUT_PWR = 0,
+    WLAN_OFF_DEEP_SLEEP,
+};
+
+/* WLAN low power state */
+enum {
+    WLAN_POWER_STATE_ON = 0,
+    WLAN_POWER_STATE_CUT_PWR = 1,
+    WLAN_POWER_STATE_DEEP_SLEEP,
+    WLAN_POWER_STATE_WOW
+};
+
+/* WLAN WoW State */
+enum {
+    WLAN_WOW_STATE_NONE = 0,
+    WLAN_WOW_STATE_SUSPENDED,
+    WLAN_WOW_STATE_SUSPENDING
+};
+
+
+typedef enum _AR6K_BIN_FILE {
+    AR6K_OTP_FILE,
+    AR6K_FIRMWARE_FILE,
+    AR6K_PATCH_FILE,
+    AR6K_BOARD_DATA_FILE,
+} AR6K_BIN_FILE;
+
+#ifdef SETUPHCI_ENABLED
+#define SETUPHCI_DEFAULT           1
+#else
+#define SETUPHCI_DEFAULT           0
+#endif /* SETUPHCI_ENABLED */
+
+#ifdef SETUPHCIPAL_ENABLED
+#define SETUPHCIPAL_DEFAULT           1
+#else
+#define SETUPHCIPAL_DEFAULT           0
+#endif /* SETUPHCIPAL_ENABLED */
+
+#ifdef SETUPBTDEV_ENABLED
+#define SETUPBTDEV_DEFAULT         1
+#else
+#define SETUPBTDEV_DEFAULT         0
+#endif /* SETUPBTDEV_ENABLED */
+
+#ifdef BMIENABLE_SET
+#define BMIENABLE_DEFAULT          1
+#else
+#define BMIENABLE_DEFAULT          0
+#endif /* BMIENABLE_SET */
+
+#ifdef ENABLEUARTPRINT_SET
+#define ENABLEUARTPRINT_DEFAULT    1
+#else
+#define ENABLEUARTPRINT_DEFAULT    0
+#endif /* ENABLEARTPRINT_SET */
+
+#ifdef ATH6K_CONFIG_HIF_VIRTUAL_SCATTER
+#define NOHIFSCATTERSUPPORT_DEFAULT    1
+#else /* ATH6K_CONFIG_HIF_VIRTUAL_SCATTER */
+#define NOHIFSCATTERSUPPORT_DEFAULT    0
+#endif /* ATH6K_CONFIG_HIF_VIRTUAL_SCATTER */
+
+#ifdef AR600x_BT_AR3001
+#define AR3KHCIBAUD_DEFAULT        3000000
+#define HCIUARTSCALE_DEFAULT       1
+#define HCIUARTSTEP_DEFAULT        8937
+#else
+#define AR3KHCIBAUD_DEFAULT        0
+#define HCIUARTSCALE_DEFAULT       0
+#define HCIUARTSTEP_DEFAULT        0
+#endif /* AR600x_BT_AR3001 */
+
+#ifdef INIT_MODE_DRV_ENABLED
+#define WLAN_INIT_MODE_DEFAULT     WLAN_INIT_MODE_DRV
+#else
+#define WLAN_INIT_MODE_DEFAULT     WLAN_INIT_MODE_USR
+#endif /* INIT_MODE_DRV_ENABLED */
+
+#define AR6K_PATCH_DOWNLOAD_ADDRESS(_param, _ver) do { \
+    if ((_ver) == AR6003_REV1_VERSION) { \
+        (_param) = AR6003_REV1_PATCH_DOWNLOAD_ADDRESS; \
+    } else if ((_ver) == AR6003_REV2_VERSION) { \
+        (_param) = AR6003_REV2_PATCH_DOWNLOAD_ADDRESS; \
+    } else { \
+       AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unknown Version: %d\n", _ver)); \
+       A_ASSERT(0); \
+    } \
+} while (0)
+
+#define AR6K_DATA_DOWNLOAD_ADDRESS(_param, _ver) do { \
+    if ((_ver) == AR6003_REV1_VERSION) { \
+        (_param) = AR6003_REV1_DATA_DOWNLOAD_ADDRESS; \
+    } else if ((_ver) == AR6003_REV2_VERSION) { \
+        (_param) = AR6003_REV2_DATA_DOWNLOAD_ADDRESS; \
+    } else { \
+       AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unknown Version: %d\n", _ver)); \
+       A_ASSERT(0); \
+    } \
+} while (0)
+
+#define AR6K_APP_START_OVERRIDE_ADDRESS(_param, _ver) do { \
+    if ((_ver) == AR6003_REV1_VERSION) { \
+        (_param) = AR6003_REV1_APP_START_OVERRIDE; \
+    } else if ((_ver) == AR6003_REV2_VERSION) { \
+        (_param) = AR6003_REV2_APP_START_OVERRIDE; \
+    } else { \
+       AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unknown Version: %d\n", _ver)); \
+       A_ASSERT(0); \
+    } \
+} while (0)
+
+/* AR6003 1.0 definitions */
+#define AR6003_REV1_VERSION                 0x300002ba
+#define AR6003_REV1_DATA_DOWNLOAD_ADDRESS   AR6003_REV1_OTP_DATA_ADDRESS
+#define AR6003_REV1_PATCH_DOWNLOAD_ADDRESS  0x57ea6c
+#define AR6003_REV1_OTP_FILE                "ath6k/AR6003/hw1.0/otp.bin.z77"
+#define AR6003_REV1_FIRMWARE_FILE           "ath6k/AR6003/hw1.0/athwlan.bin.z77"
+#define AR6003_REV1_TCMD_FIRMWARE_FILE      "ath6k/AR6003/hw1.0/athtcmd_ram.bin"
+#define AR6003_REV1_ART_FIRMWARE_FILE       "ath6k/AR6003/hw1.0/device.bin"
+#define AR6003_REV1_PATCH_FILE              "ath6k/AR6003/hw1.0/data.patch.bin"
+#define AR6003_REV1_EPPING_FIRMWARE_FILE    "ath6k/AR6003/hw1.0/endpointping.bin"
+#ifdef AR600x_SD31_XXX
+#define AR6003_REV1_BOARD_DATA_FILE         "ath6k/AR6003/hw1.0/bdata.SD31.bin"
+#elif defined(AR600x_SD32_XXX)
+#define AR6003_REV1_BOARD_DATA_FILE         "ath6k/AR6003/hw1.0/bdata.SD32.bin"
+#elif defined(AR600x_WB31_XXX)
+#define AR6003_REV1_BOARD_DATA_FILE         "ath6k/AR6003/hw1.0/bdata.WB31.bin"
+#else
+#define AR6003_REV1_BOARD_DATA_FILE         "ath6k/AR6003/hw1.0/bdata.CUSTOM.bin"
+#endif /* Board Data File */
+
+/* AR6003 2.0 definitions */
+#define AR6003_REV2_VERSION                 0x30000384 
+#define AR6003_REV2_DATA_DOWNLOAD_ADDRESS   AR6003_REV2_OTP_DATA_ADDRESS
+#define AR6003_REV2_PATCH_DOWNLOAD_ADDRESS  0x57e910
+#define AR6003_REV2_OTP_FILE                "ath6k/AR6003/hw2.0/otp.bin.z77"
+#define AR6003_REV2_FIRMWARE_FILE           "ath6k/AR6003/hw2.0/athwlan.bin.z77"
+#define AR6003_REV2_TCMD_FIRMWARE_FILE      "ath6k/AR6003/hw2.0/athtcmd_ram.bin"
+#define AR6003_REV2_ART_FIRMWARE_FILE       "ath6k/AR6003/hw2.0/device.bin"
+#define AR6003_REV2_PATCH_FILE              "ath6k/AR6003/hw2.0/data.patch.bin"
+#define AR6003_REV2_EPPING_FIRMWARE_FILE    "ath6k/AR6003/hw2.0/endpointping.bin"
+#ifdef AR600x_SD31_XXX
+#define AR6003_REV2_BOARD_DATA_FILE         "ath6k/AR6003/hw2.0/bdata.SD31.bin"
+#elif defined(AR600x_SD32_XXX)
+#define AR6003_REV2_BOARD_DATA_FILE         "ath6k/AR6003/hw2.0/bdata.SD32.bin"
+#elif defined(AR600x_WB31_XXX)
+#define AR6003_REV2_BOARD_DATA_FILE         "ath6k/AR6003/hw2.0/bdata.WB31.bin"
+#else
+#define AR6003_REV2_BOARD_DATA_FILE         "ath6k/AR6003/hw2.0/bdata.CUSTOM.bin"
+#endif /* Board Data File */
+
+/* Power states */
+enum {
+    WLAN_PWR_CTRL_UP = 0,
+    WLAN_PWR_CTRL_CUT_PWR,
+    WLAN_PWR_CTRL_DEEP_SLEEP,
+    WLAN_PWR_CTRL_WOW,
+    WLAN_PWR_CTRL_DEEP_SLEEP_DISABLED
+};
+
+/* HTC RAW streams */
+typedef enum _HTC_RAW_STREAM_ID {
+    HTC_RAW_STREAM_NOT_MAPPED = -1,
+    HTC_RAW_STREAM_0 = 0,
+    HTC_RAW_STREAM_1 = 1,
+    HTC_RAW_STREAM_2 = 2,
+    HTC_RAW_STREAM_3 = 3,
+    HTC_RAW_STREAM_NUM_MAX
+} HTC_RAW_STREAM_ID;
+
+#define RAW_HTC_READ_BUFFERS_NUM    4
+#define RAW_HTC_WRITE_BUFFERS_NUM   4
+
+#define HTC_RAW_BUFFER_SIZE  1664
+
+typedef struct {
+    int currPtr;
+    int length;
+    unsigned char data[HTC_RAW_BUFFER_SIZE];
+    HTC_PACKET    HTCPacket;
+} raw_htc_buffer;
+
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+/*
+ *  add TCMD_MODE besides wmi and bypasswmi
+ *  in TCMD_MODE, only few TCMD releated wmi commands
+ *  counld be hanlder
+ */
+enum {
+    AR6000_WMI_MODE = 0,
+    AR6000_BYPASS_MODE,
+    AR6000_TCMD_MODE,
+    AR6000_WLAN_MODE
+};
+#endif /* CONFIG_HOST_TCMD_SUPPORT */
+
+struct ar_wep_key {
+    A_UINT8                 arKeyIndex;
+    A_UINT8                 arKeyLen;
+    A_UINT8                 arKey[64];
+} ;
+
+#ifdef ATH6K_CONFIG_CFG80211
+struct ar_key {
+    A_UINT8     key[WLAN_MAX_KEY_LEN];
+    A_UINT8     key_len;
+    A_UINT8     seq[IW_ENCODE_SEQ_MAX_SIZE];
+    A_UINT8     seq_len;
+    A_UINT32    cipher;
+};
+#endif /* ATH6K_CONFIG_CFG80211 */
+
+
+struct ar_node_mapping {
+    A_UINT8                 macAddress[6];
+    A_UINT8                 epId;
+    A_UINT8                 txPending;
+};
+
+struct ar_cookie {
+    unsigned long          arc_bp[2];    /* Must be first field */
+    HTC_PACKET             HtcPkt;       /* HTC packet wrapper */
+    struct ar_cookie *arc_list_next;
+};
+
+struct ar_hb_chlng_resp {
+    A_TIMER                 timer;
+    A_UINT32                frequency;
+    A_UINT32                seqNum;
+    A_BOOL                  outstanding;
+    A_UINT8                 missCnt;
+    A_UINT8                 missThres;
+};
+
+/* Per STA data, used in AP mode */
+/*TODO: All this should move to OS independent dir */
+
+#define STA_PWR_MGMT_MASK 0x1
+#define STA_PWR_MGMT_SHIFT 0x0
+#define STA_PWR_MGMT_AWAKE 0x0
+#define STA_PWR_MGMT_SLEEP 0x1
+
+#define STA_SET_PWR_SLEEP(sta) (sta->flags |= (STA_PWR_MGMT_MASK << STA_PWR_MGMT_SHIFT))
+#define STA_CLR_PWR_SLEEP(sta) (sta->flags &= ~(STA_PWR_MGMT_MASK << STA_PWR_MGMT_SHIFT))
+#define STA_IS_PWR_SLEEP(sta) ((sta->flags >> STA_PWR_MGMT_SHIFT) & STA_PWR_MGMT_MASK)
+
+#define STA_PS_POLLED_MASK 0x1
+#define STA_PS_POLLED_SHIFT 0x1
+#define STA_SET_PS_POLLED(sta) (sta->flags |= (STA_PS_POLLED_MASK << STA_PS_POLLED_SHIFT))
+#define STA_CLR_PS_POLLED(sta) (sta->flags &= ~(STA_PS_POLLED_MASK << STA_PS_POLLED_SHIFT))
+#define STA_IS_PS_POLLED(sta) (sta->flags & (STA_PS_POLLED_MASK << STA_PS_POLLED_SHIFT))
+
+typedef struct {
+    A_UINT16                flags;
+    A_UINT8                 mac[ATH_MAC_LEN];
+    A_UINT8                 aid;
+    A_UINT8                 keymgmt;
+    A_UINT8                 ucipher;
+    A_UINT8                 auth;
+    A_UINT8                 wpa_ie[IEEE80211_MAX_IE];
+    A_NETBUF_QUEUE_T        psq;    /* power save q */
+    A_MUTEX_T               psqLock;
+} sta_t;
+
+typedef struct ar6_raw_htc {
+    HTC_ENDPOINT_ID         arRaw2EpMapping[HTC_RAW_STREAM_NUM_MAX];
+    HTC_RAW_STREAM_ID       arEp2RawMapping[ENDPOINT_MAX];
+    struct semaphore        raw_htc_read_sem[HTC_RAW_STREAM_NUM_MAX];
+    struct semaphore        raw_htc_write_sem[HTC_RAW_STREAM_NUM_MAX];
+    wait_queue_head_t       raw_htc_read_queue[HTC_RAW_STREAM_NUM_MAX];
+    wait_queue_head_t       raw_htc_write_queue[HTC_RAW_STREAM_NUM_MAX];
+    raw_htc_buffer          raw_htc_read_buffer[HTC_RAW_STREAM_NUM_MAX][RAW_HTC_READ_BUFFERS_NUM];
+    raw_htc_buffer          raw_htc_write_buffer[HTC_RAW_STREAM_NUM_MAX][RAW_HTC_WRITE_BUFFERS_NUM];
+    A_BOOL                  write_buffer_available[HTC_RAW_STREAM_NUM_MAX];
+    A_BOOL                  read_buffer_available[HTC_RAW_STREAM_NUM_MAX];
+} AR_RAW_HTC_T;
+
+typedef struct ar6_softc {
+    struct net_device       *arNetDev;    /* net_device pointer */
+    void                    *arWmi;
+    int                     arTxPending[ENDPOINT_MAX];
+    int                     arTotalTxDataPending;
+    A_UINT8                 arNumDataEndPts;
+    A_BOOL                  arWmiEnabled;
+    A_BOOL                  arWmiReady;
+    A_BOOL                  arConnected;
+    HTC_HANDLE              arHtcTarget;
+    void                    *arHifDevice;
+    spinlock_t              arLock;
+    struct semaphore        arSem;
+    int                     arSsidLen;
+    u_char                  arSsid[32];
+    A_UINT8                 arNextMode;
+    A_UINT8                 arNetworkType;
+    A_UINT8                 arDot11AuthMode;
+    A_UINT8                 arAuthMode;
+    A_UINT8                 arPairwiseCrypto;
+    A_UINT8                 arPairwiseCryptoLen;
+    A_UINT8                 arGroupCrypto;
+    A_UINT8                 arGroupCryptoLen;
+    A_UINT8                 arDefTxKeyIndex;
+    struct ar_wep_key       arWepKeyList[WMI_MAX_KEY_INDEX + 1];
+    A_UINT8                 arBssid[6];
+    A_UINT8                 arReqBssid[6];
+    A_UINT16                arChannelHint;
+    A_UINT16                arBssChannel;
+    A_UINT16                arListenIntervalB;
+    A_UINT16                arListenIntervalT;
+    struct ar6000_version   arVersion;
+    A_UINT32                arTargetType;
+    A_INT8                  arRssi;
+    A_UINT8                 arTxPwr;
+    A_BOOL                  arTxPwrSet;
+    A_INT32                 arBitRate;
+    struct net_device_stats arNetStats;
+    struct iw_statistics    arIwStats;
+    A_INT8                  arNumChannels;
+    A_UINT16                arChannelList[32];
+    A_UINT32                arRegCode;
+    A_BOOL                  statsUpdatePending;
+    TARGET_STATS            arTargetStats;
+    A_INT8                  arMaxRetries;
+    A_UINT8                 arPhyCapability;
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+    A_UINT8                 tcmdRxReport;
+    A_UINT32                tcmdRxTotalPkt;
+    A_INT32                 tcmdRxRssi;
+    A_UINT32                tcmdPm;
+    A_UINT32                arTargetMode;
+    A_UINT32                tcmdRxcrcErrPkt;
+    A_UINT32                tcmdRxsecErrPkt;
+    A_UINT16                tcmdRateCnt[TCMD_MAX_RATES];
+    A_UINT16                tcmdRateCntShortGuard[TCMD_MAX_RATES];
+#endif
+    AR6000_WLAN_STATE       arWlanState;
+    struct ar_node_mapping  arNodeMap[MAX_NODE_NUM];
+    A_UINT8                 arIbssPsEnable;
+    A_UINT8                 arNodeNum;
+    A_UINT8                 arNexEpId;
+    struct ar_cookie        *arCookieList;
+    A_UINT32                arCookieCount;
+    A_UINT32                arRateMask;
+    A_UINT8                 arSkipScan;
+    A_UINT16                arBeaconInterval;
+    A_BOOL                  arConnectPending;
+    A_BOOL                  arWmmEnabled;
+    struct ar_hb_chlng_resp arHBChallengeResp;
+    A_UINT8                 arKeepaliveConfigured;
+    A_UINT32                arMgmtFilter;
+    HTC_ENDPOINT_ID         arAc2EpMapping[WMM_NUM_AC];
+    A_BOOL                  arAcStreamActive[WMM_NUM_AC];
+    A_UINT8                 arAcStreamPriMap[WMM_NUM_AC];
+    A_UINT8                 arHiAcStreamActivePri;
+    A_UINT8                 arEp2AcMapping[ENDPOINT_MAX];
+    HTC_ENDPOINT_ID         arControlEp;
+#ifdef HTC_RAW_INTERFACE
+    AR_RAW_HTC_T            *arRawHtc;
+#endif
+    A_BOOL                  arNetQueueStopped;
+    A_BOOL                  arRawIfInit;
+    int                     arDeviceIndex;
+    COMMON_CREDIT_STATE_INFO arCreditStateInfo;
+    A_BOOL                  arWMIControlEpFull;
+    A_BOOL                  dbgLogFetchInProgress;
+    A_UCHAR                 log_buffer[DBGLOG_HOST_LOG_BUFFER_SIZE];
+    A_UINT32                log_cnt;
+    A_UINT32                dbglog_init_done;
+    A_UINT32                arConnectCtrlFlags;
+#ifdef USER_KEYS
+    A_INT32                 user_savedkeys_stat;
+    A_UINT32                user_key_ctrl;
+    struct USER_SAVEDKEYS   user_saved_keys;
+#endif
+    USER_RSSI_THOLD rssi_map[12];
+    A_UINT8                arUserBssFilter;
+    A_UINT16                ap_profile_flag;    /* AP mode */
+    WMI_AP_ACL              g_acl;              /* AP mode */
+    sta_t                   sta_list[AP_MAX_NUM_STA]; /* AP mode */
+    A_UINT8                 sta_list_index;     /* AP mode */
+    struct ieee80211req_key ap_mode_bkey;           /* AP mode */
+    A_NETBUF_QUEUE_T        mcastpsq;    /* power save q for Mcast frames */
+    A_MUTEX_T               mcastpsqLock;
+    A_BOOL                  DTIMExpired; /* flag to indicate DTIM expired */
+    A_UINT8                 intra_bss;   /* enable/disable intra bss data forward */
+    void                    *aggr_cntxt;
+#ifndef EXPORT_HCI_BRIDGE_INTERFACE
+    void                    *hcidev_info;
+#endif
+    void                    *hcipal_info;
+    WMI_AP_MODE_STAT        arAPStats;
+    A_UINT8                 ap_hidden_ssid;
+    A_UINT8                 ap_country_code[3];
+    A_UINT8                 ap_wmode;
+    A_UINT8                 ap_dtim_period;
+    A_UINT16                ap_beacon_interval;
+    A_UINT16                arRTS;
+    A_UINT16                arACS; /* AP mode - Auto Channel Selection */
+    HTC_PACKET_QUEUE        amsdu_rx_buffer_queue;
+    A_BOOL                  bIsDestroyProgress; /* flag to indicate ar6k destroy is in progress */
+    A_TIMER                 disconnect_timer;
+    A_UINT8		    rxMetaVersion;
+#ifdef WAPI_ENABLE
+    A_UINT8                 arWapiEnable;
+#endif
+	WMI_BTCOEX_CONFIG_EVENT arBtcoexConfig;
+	WMI_BTCOEX_STATS_EVENT  arBtcoexStats;
+    A_INT32                 (*exitCallback)(void *config);  /* generic callback at AR6K exit */
+    HIF_DEVICE_OS_DEVICE_INFO   osDevInfo;
+#ifdef ATH6K_CONFIG_CFG80211
+    struct wireless_dev *wdev;
+    struct cfg80211_scan_request    *scan_request;
+    struct ar_key   keys[WMI_MAX_KEY_INDEX + 1];
+#endif /* ATH6K_CONFIG_CFG80211 */
+    A_UINT16                arWlanPowerState;
+    A_BOOL                  arWlanOff;
+#ifdef CONFIG_PM
+    A_UINT16                arWowState;
+    A_BOOL                  arBTOff;
+    A_BOOL                  arBTSharing;
+    A_UINT16                arSuspendConfig;
+    A_UINT16                arWlanOffConfig;
+    A_UINT16                arWow2Config;
+#endif
+    A_UINT8                 scan_triggered;
+    WMI_SCAN_PARAMS_CMD     scParams;
+#define AR_MCAST_FILTER_MAC_ADDR_SIZE  4
+    A_UINT8                 mcast_filters[MAC_MAX_FILTERS_PER_LIST][AR_MCAST_FILTER_MAC_ADDR_SIZE];
+    A_UINT8                 bdaddr[6];
+    A_BOOL                  scanSpecificSsid;
+#ifdef CONFIG_AP_VIRTUAL_ADAPTER_SUPPORT
+    void                    *arApDev;
+#endif
+} AR_SOFTC_T;
+
+#ifdef CONFIG_AP_VIRTUAL_ADAPTER_SUPPORT
+typedef struct {
+    struct net_device       *arNetDev;    /* net_device pointer */
+    AR_SOFTC_T              *arDev;       /* ar device pointer */
+    struct net_device       *arStaNetDev; /* net_device pointer */
+} AR_VIRTUAL_INTERFACE_T;
+#endif /* CONFIG_AP_VIRTUAL_ADAPTER_SUPPORT */
+
+#ifdef ATH6K_CONFIG_CFG80211
+static inline void *ar6k_priv(struct net_device *dev)
+{
+    return (wdev_priv(dev->ieee80211_ptr));
+}
+#else
+#ifdef CONFIG_AP_VIRTUAL_ADAPTER_SUPPORT
+static inline void *ar6k_priv(struct net_device *dev)
+{
+    extern struct net_device *arApNetDev;
+
+    if (arApNetDev == dev) {
+        /* return arDev saved in virtual interface context */
+        AR_VIRTUAL_INTERFACE_T *arVirDev;
+        arVirDev = netdev_priv(dev);
+        return arVirDev->arDev;   
+    } else {
+        return netdev_priv(dev);
+    }
+}
+#else
+#define ar6k_priv   netdev_priv
+#endif /* CONFIG_AP_VIRTUAL_ADAPTER_SUPPORT */
+#endif /* ATH6K_CONFIG_CFG80211 */
+
+#define SET_HCI_BUS_TYPE(pHciDev, __bus, __type) do { \
+    (pHciDev)->bus = (__bus); \
+    (pHciDev)->dev_type = (__type); \
+} while(0)
+
+#define GET_INODE_FROM_FILEP(filp) \
+    (filp)->f_path.dentry->d_inode
+
+#define arAc2EndpointID(ar,ac)          (ar)->arAc2EpMapping[(ac)]
+#define arSetAc2EndpointIDMap(ar,ac,ep)  \
+{  (ar)->arAc2EpMapping[(ac)] = (ep); \
+   (ar)->arEp2AcMapping[(ep)] = (ac); }
+#define arEndpoint2Ac(ar,ep)           (ar)->arEp2AcMapping[(ep)]
+
+#define arRawIfEnabled(ar) (ar)->arRawIfInit
+#define arRawStream2EndpointID(ar,raw)          (ar)->arRawHtc->arRaw2EpMapping[(raw)]
+#define arSetRawStream2EndpointIDMap(ar,raw,ep)  \
+{  (ar)->arRawHtc->arRaw2EpMapping[(raw)] = (ep); \
+   (ar)->arRawHtc->arEp2RawMapping[(ep)] = (raw); }
+#define arEndpoint2RawStreamID(ar,ep)           (ar)->arRawHtc->arEp2RawMapping[(ep)]
+
+struct ar_giwscan_param {
+    char    *current_ev;
+    char    *end_buf;
+    A_UINT32 bytes_needed;
+    struct iw_request_info *info;
+};
+
+#define AR6000_STAT_INC(ar, stat)       (ar->arNetStats.stat++)
+
+#define AR6000_SPIN_LOCK(lock, param)   do {                            \
+    if (irqs_disabled()) {                                              \
+        AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("IRQs disabled:AR6000_LOCK\n"));                 \
+    }                                                                   \
+    spin_lock_bh(lock);                                                 \
+} while (0)
+
+#define AR6000_SPIN_UNLOCK(lock, param) do {                            \
+    if (irqs_disabled()) {                                              \
+        AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("IRQs disabled: AR6000_UNLOCK\n"));              \
+    }                                                                   \
+    spin_unlock_bh(lock);                                               \
+} while (0)
+
+int ar6000_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
+int ar6000_ioctl_dispatcher(struct net_device *dev, struct ifreq *rq, int cmd);
+void ar6000_gpio_init(void);
+void ar6000_init_profile_info(AR_SOFTC_T *ar);
+void ar6000_install_static_wep_keys(AR_SOFTC_T *ar);
+int ar6000_init(struct net_device *dev);
+int ar6000_dbglog_get_debug_logs(AR_SOFTC_T *ar);
+void ar6000_TxDataCleanup(AR_SOFTC_T *ar);
+int ar6000_acl_data_tx(struct sk_buff *skb, struct net_device *dev);
+void ar6000_restart_endpoint(struct net_device *dev);
+void ar6000_stop_endpoint(struct net_device *dev, A_BOOL keepprofile, A_BOOL getdbglogs);
+
+#ifdef HTC_RAW_INTERFACE
+
+#ifndef __user
+#define __user
+#endif
+
+int ar6000_htc_raw_open(AR_SOFTC_T *ar);
+int ar6000_htc_raw_close(AR_SOFTC_T *ar);
+ssize_t ar6000_htc_raw_read(AR_SOFTC_T *ar,
+                            HTC_RAW_STREAM_ID StreamID,
+                            char __user *buffer, size_t count);
+ssize_t ar6000_htc_raw_write(AR_SOFTC_T *ar,
+                             HTC_RAW_STREAM_ID StreamID,
+                             char __user *buffer, size_t count);
+
+#endif /* HTC_RAW_INTERFACE */
+
+/* AP mode */
+/*TODO: These routines should be moved to a file that is common across OS */
+sta_t *
+ieee80211_find_conn(AR_SOFTC_T *ar, A_UINT8 *node_addr);
+
+sta_t *
+ieee80211_find_conn_for_aid(AR_SOFTC_T *ar, A_UINT8 aid);
+
+A_UINT8
+remove_sta(AR_SOFTC_T *ar, A_UINT8 *mac, A_UINT16 reason);
+
+/* HCI support */
+
+#ifndef EXPORT_HCI_BRIDGE_INTERFACE
+A_STATUS ar6000_setup_hci(AR_SOFTC_T *ar);
+void     ar6000_cleanup_hci(AR_SOFTC_T *ar);
+void     ar6000_set_default_ar3kconfig(AR_SOFTC_T *ar, void *ar3kconfig);
+
+/* HCI bridge testing */
+A_STATUS hci_test_send(AR_SOFTC_T *ar, struct sk_buff *skb);
+#endif
+
+ATH_DEBUG_DECLARE_EXTERN(htc);
+ATH_DEBUG_DECLARE_EXTERN(wmi);
+ATH_DEBUG_DECLARE_EXTERN(bmi);
+ATH_DEBUG_DECLARE_EXTERN(hif);
+ATH_DEBUG_DECLARE_EXTERN(wlan);
+ATH_DEBUG_DECLARE_EXTERN(misc);
+
+extern A_UINT8 bcast_mac[];
+extern A_UINT8 null_mac[];
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _AR6000_H_ */
diff --git a/drivers/net/ath6kl/os/linux/include/ar6k_pal.h b/drivers/net/ath6kl/os/linux/include/ar6k_pal.h
new file mode 100644
index 00000000000..a9a29a624a1
--- /dev/null
+++ b/drivers/net/ath6kl/os/linux/include/ar6k_pal.h
@@ -0,0 +1,36 @@
+//------------------------------------------------------------------------------
+// Copyright (c) 2009-2010 Atheros Corporation.  All rights reserved.
+// 
+// The software source and binaries included in this development package are
+// licensed, not sold. You, or your company, received the package under one
+// or more license agreements. The rights granted to you are specifically
+// listed in these license agreement(s). All other rights remain with Atheros
+// Communications, Inc., its subsidiaries, or the respective owner including
+// those listed on the included copyright notices.  Distribution of any
+// portion of this package must be in strict compliance with the license
+// agreement(s) terms.
+// </copyright>
+// 
+// <summary>
+// 	PAL driver for AR6003
+// </summary>
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _AR6K_PAL_H_
+#define _AR6K_PAL_H_
+#define HCI_GET_OP_CODE(p)          (((A_UINT16)((p)[1])) << 8) | ((A_UINT16)((p)[0]))
+
+/* transmit packet reserve offset */
+#define TX_PACKET_RSV_OFFSET        32
+/* pal specific config structure */
+typedef A_BOOL (*ar6k_pal_recv_pkt_t)(void *pHciPalInfo, void *skb);
+typedef struct ar6k_pal_config_s
+{
+	ar6k_pal_recv_pkt_t fpar6k_pal_recv_pkt;
+}ar6k_pal_config_t;
+
+void register_pal_cb(ar6k_pal_config_t *palConfig_p);
+#endif /* _AR6K_PAL_H_ */
diff --git a/drivers/net/ath6kl/os/linux/include/ar6xapi_linux.h b/drivers/net/ath6kl/os/linux/include/ar6xapi_linux.h
new file mode 100644
index 00000000000..ea2d181dcfe
--- /dev/null
+++ b/drivers/net/ath6kl/os/linux/include/ar6xapi_linux.h
@@ -0,0 +1,197 @@
+//------------------------------------------------------------------------------
+// Copyright (c) 2004-2010 Atheros Communications Inc.
+// All rights reserved.
+//
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//
+// Author(s): ="Atheros"
+//------------------------------------------------------------------------------
+
+#ifndef _AR6XAPI_LINUX_H
+#define _AR6XAPI_LINUX_H
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct ar6_softc;
+
+void ar6000_ready_event(void *devt, A_UINT8 *datap, A_UINT8 phyCap,
+                        A_UINT32 sw_ver, A_UINT32 abi_ver);
+A_STATUS ar6000_control_tx(void *devt, void *osbuf, HTC_ENDPOINT_ID eid);
+void ar6000_connect_event(struct ar6_softc *ar, A_UINT16 channel,
+                          A_UINT8 *bssid, A_UINT16 listenInterval,
+                          A_UINT16 beaconInterval, NETWORK_TYPE networkType,
+                          A_UINT8 beaconIeLen, A_UINT8 assocReqLen,
+                          A_UINT8 assocRespLen,A_UINT8 *assocInfo);
+void ar6000_disconnect_event(struct ar6_softc *ar, A_UINT8 reason,
+                             A_UINT8 *bssid, A_UINT8 assocRespLen,
+                             A_UINT8 *assocInfo, A_UINT16 protocolReasonStatus);
+void ar6000_tkip_micerr_event(struct ar6_softc *ar, A_UINT8 keyid,
+                              A_BOOL ismcast);
+void ar6000_bitrate_rx(void *devt, A_INT32 rateKbps);
+void ar6000_channelList_rx(void *devt, A_INT8 numChan, A_UINT16 *chanList);
+void ar6000_regDomain_event(struct ar6_softc *ar, A_UINT32 regCode);
+void ar6000_txPwr_rx(void *devt, A_UINT8 txPwr);
+void ar6000_keepalive_rx(void *devt, A_UINT8 configured);
+void ar6000_neighborReport_event(struct ar6_softc *ar, int numAps,
+                                 WMI_NEIGHBOR_INFO *info);
+void ar6000_set_numdataendpts(struct ar6_softc *ar, A_UINT32 num);
+void ar6000_scanComplete_event(struct ar6_softc *ar, A_STATUS status);
+void ar6000_targetStats_event(struct ar6_softc *ar,  A_UINT8 *ptr, A_UINT32 len);
+void ar6000_rssiThreshold_event(struct ar6_softc *ar,
+                                WMI_RSSI_THRESHOLD_VAL newThreshold,
+                                A_INT16 rssi);
+void ar6000_reportError_event(struct ar6_softc *, WMI_TARGET_ERROR_VAL errorVal);
+void ar6000_cac_event(struct ar6_softc *ar, A_UINT8 ac, A_UINT8 cac_indication,
+                                A_UINT8 statusCode, A_UINT8 *tspecSuggestion);
+void ar6000_channel_change_event(struct ar6_softc *ar, A_UINT16 oldChannel, A_UINT16 newChannel);
+void ar6000_hbChallengeResp_event(struct ar6_softc *, A_UINT32 cookie, A_UINT32 source);
+void
+ar6000_roam_tbl_event(struct ar6_softc *ar, WMI_TARGET_ROAM_TBL *pTbl);
+
+void
+ar6000_roam_data_event(struct ar6_softc *ar, WMI_TARGET_ROAM_DATA *p);
+
+void
+ar6000_wow_list_event(struct ar6_softc *ar, A_UINT8 num_filters,
+                      WMI_GET_WOW_LIST_REPLY *wow_reply);
+
+void ar6000_pmkid_list_event(void *devt, A_UINT8 numPMKID,
+                             WMI_PMKID *pmkidList, A_UINT8 *bssidList);
+
+void ar6000_gpio_intr_rx(A_UINT32 intr_mask, A_UINT32 input_values);
+void ar6000_gpio_data_rx(A_UINT32 reg_id, A_UINT32 value);
+void ar6000_gpio_ack_rx(void);
+
+A_INT32 rssi_compensation_calc_tcmd(A_UINT32 freq, A_INT32 rssi, A_UINT32 totalPkt);
+A_INT16 rssi_compensation_calc(struct ar6_softc *ar, A_INT16 rssi);
+A_INT16 rssi_compensation_reverse_calc(struct ar6_softc *ar, A_INT16 rssi, A_BOOL Above);
+
+void ar6000_dbglog_init_done(struct ar6_softc *ar);
+
+#ifdef SEND_EVENT_TO_APP
+void ar6000_send_event_to_app(struct ar6_softc *ar, A_UINT16 eventId, A_UINT8 *datap, int len);
+void ar6000_send_generic_event_to_app(struct ar6_softc *ar, A_UINT16 eventId, A_UINT8 *datap, int len);
+#endif
+
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+void ar6000_tcmd_rx_report_event(void *devt, A_UINT8 * results, int len);
+#endif
+
+void ar6000_tx_retry_err_event(void *devt);
+
+void ar6000_snrThresholdEvent_rx(void *devt,
+                                 WMI_SNR_THRESHOLD_VAL newThreshold,
+                                 A_UINT8 snr);
+
+void ar6000_lqThresholdEvent_rx(void *devt, WMI_LQ_THRESHOLD_VAL range, A_UINT8 lqVal);
+
+
+void ar6000_ratemask_rx(void *devt, A_UINT32 ratemask);
+
+A_STATUS ar6000_get_driver_cfg(struct net_device *dev,
+                                A_UINT16 cfgParam,
+                                void *result);
+void ar6000_bssInfo_event_rx(struct ar6_softc *ar, A_UINT8 *data, int len);
+
+void ar6000_dbglog_event(struct ar6_softc *ar, A_UINT32 dropped,
+                         A_INT8 *buffer, A_UINT32 length);
+
+int ar6000_dbglog_get_debug_logs(struct ar6_softc *ar);
+
+void ar6000_peer_event(void *devt, A_UINT8 eventCode, A_UINT8 *bssid);
+
+void ar6000_indicate_tx_activity(void *devt, A_UINT8 trafficClass, A_BOOL Active);
+HTC_ENDPOINT_ID  ar6000_ac2_endpoint_id ( void * devt, A_UINT8 ac);
+A_UINT8 ar6000_endpoint_id2_ac (void * devt, HTC_ENDPOINT_ID ep );
+
+void ar6000_btcoex_config_event(struct ar6_softc *ar,  A_UINT8 *ptr, A_UINT32 len);
+
+void ar6000_btcoex_stats_event(struct ar6_softc *ar,  A_UINT8 *ptr, A_UINT32 len) ;
+
+void ar6000_dset_open_req(void *devt,
+                          A_UINT32 id,
+                          A_UINT32 targ_handle,
+                          A_UINT32 targ_reply_fn,
+                          A_UINT32 targ_reply_arg);
+void ar6000_dset_close(void *devt, A_UINT32 access_cookie);
+void ar6000_dset_data_req(void *devt,
+                          A_UINT32 access_cookie,
+                          A_UINT32 offset,
+                          A_UINT32 length,
+                          A_UINT32 targ_buf,
+                          A_UINT32 targ_reply_fn,
+                          A_UINT32 targ_reply_arg);
+
+
+#if defined(CONFIG_TARGET_PROFILE_SUPPORT)
+void prof_count_rx(unsigned int addr, unsigned int count);
+#endif
+
+A_UINT32 ar6000_getnodeAge (void);
+
+A_UINT32 ar6000_getclkfreq (void);
+
+int ar6000_ap_mode_profile_commit(struct ar6_softc *ar);
+
+struct ieee80211req_wpaie;
+A_STATUS
+ar6000_ap_mode_get_wpa_ie(struct ar6_softc *ar, struct ieee80211req_wpaie *wpaie);
+
+A_STATUS is_iwioctl_allowed(A_UINT8 mode, A_UINT16 cmd);
+
+A_STATUS is_xioctl_allowed(A_UINT8 mode, int cmd);
+
+void ar6000_pspoll_event(struct ar6_softc *ar,A_UINT8 aid);
+
+void ar6000_dtimexpiry_event(struct ar6_softc *ar);
+
+void ar6000_aggr_rcv_addba_req_evt(struct ar6_softc *ar, WMI_ADDBA_REQ_EVENT *cmd);
+void ar6000_aggr_rcv_addba_resp_evt(struct ar6_softc *ar, WMI_ADDBA_RESP_EVENT *cmd);
+void ar6000_aggr_rcv_delba_req_evt(struct ar6_softc *ar, WMI_DELBA_EVENT *cmd);
+void ar6000_hci_event_rcv_evt(struct ar6_softc *ar, WMI_HCI_EVENT *cmd);
+
+#ifdef WAPI_ENABLE
+int ap_set_wapi_key(struct ar6_softc *ar, void *ik);
+void ap_wapi_rekey_event(struct ar6_softc *ar, A_UINT8 type, A_UINT8 *mac);
+#endif
+
+A_STATUS ar6000_connect_to_ap(struct ar6_softc *ar);
+A_STATUS ar6000_update_wlan_pwr_state(struct ar6_softc *ar, AR6000_WLAN_STATE state, A_BOOL suspending);
+A_STATUS ar6000_set_wlan_state(struct ar6_softc *ar, AR6000_WLAN_STATE state);
+A_STATUS ar6000_set_bt_hw_state(struct ar6_softc *ar, A_UINT32 state);
+
+#ifdef CONFIG_PM
+A_STATUS ar6000_suspend_ev(void *context);
+A_STATUS ar6000_resume_ev(void *context);
+A_STATUS ar6000_power_change_ev(void *context, A_UINT32 config);
+void ar6000_check_wow_status(struct ar6_softc *ar, struct sk_buff *skb, A_BOOL isEvent);
+#endif
+
+void ar6000_pm_init(void);
+void ar6000_pm_exit(void);
+
+#ifdef CONFIG_AP_VIRTUAL_ADAPTER_SUPPORT
+A_STATUS ar6000_add_ap_interface(struct ar6_softc *ar, char *ifname);
+A_STATUS ar6000_remove_ap_interface(struct ar6_softc *ar);
+#endif /* CONFIG_AP_VIRTUAL_ADAPTER_SUPPORT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/drivers/net/ath6kl/os/linux/include/athdrv_linux.h b/drivers/net/ath6kl/os/linux/include/athdrv_linux.h
new file mode 100644
index 00000000000..53bbb4837d3
--- /dev/null
+++ b/drivers/net/ath6kl/os/linux/include/athdrv_linux.h
@@ -0,0 +1,1219 @@
+//------------------------------------------------------------------------------
+// Copyright (c) 2004-2010 Atheros Communications Inc.
+// All rights reserved.
+//
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//
+// Author(s): ="Atheros"
+//------------------------------------------------------------------------------
+
+#ifndef _ATHDRV_LINUX_H
+#define _ATHDRV_LINUX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/*
+ * There are two types of ioctl's here: Standard ioctls and
+ * eXtended ioctls.  All extended ioctls (XIOCTL) are multiplexed
+ * off of the single ioctl command, AR6000_IOCTL_EXTENDED.  The
+ * arguments for every XIOCTL starts with a 32-bit command word
+ * that is used to select which extended ioctl is in use.  After
+ * the command word are command-specific arguments.
+ */
+
+/* Linux standard Wireless Extensions, private ioctl interfaces */
+#define IEEE80211_IOCTL_SETPARAM             (SIOCIWFIRSTPRIV+0)
+#define IEEE80211_IOCTL_SETKEY               (SIOCIWFIRSTPRIV+1)
+#define IEEE80211_IOCTL_DELKEY               (SIOCIWFIRSTPRIV+2)
+#define IEEE80211_IOCTL_SETMLME              (SIOCIWFIRSTPRIV+3)
+#define IEEE80211_IOCTL_ADDPMKID             (SIOCIWFIRSTPRIV+4)
+#define IEEE80211_IOCTL_SETOPTIE             (SIOCIWFIRSTPRIV+5)
+//#define IEEE80211_IOCTL_GETPARAM             (SIOCIWFIRSTPRIV+6)
+//#define IEEE80211_IOCTL_SETWMMPARAMS         (SIOCIWFIRSTPRIV+7)
+//#define IEEE80211_IOCTL_GETWMMPARAMS         (SIOCIWFIRSTPRIV+8)
+//#define IEEE80211_IOCTL_GETOPTIE             (SIOCIWFIRSTPRIV+9)
+//#define IEEE80211_IOCTL_SETAUTHALG           (SIOCIWFIRSTPRIV+10)
+#define IEEE80211_IOCTL_LASTONE              (SIOCIWFIRSTPRIV+10)
+
+
+
+/*                      ====WMI Ioctls====                                    */
+/*
+ *
+ * Many ioctls simply provide WMI services to application code:
+ * an application makes such an ioctl call with a set of arguments
+ * that are packaged into the corresponding WMI message, and sent
+ * to the Target.
+ */
+
+#define AR6000_IOCTL_WMI_GETREV              (SIOCIWFIRSTPRIV+11)
+/*
+ * arguments:
+ *   ar6000_version *revision
+ */
+
+#define AR6000_IOCTL_WMI_SETPWR              (SIOCIWFIRSTPRIV+12)
+/*
+ * arguments:
+ *   WMI_POWER_MODE_CMD pwrModeCmd (see include/wmi.h)
+ * uses: WMI_SET_POWER_MODE_CMDID
+ */
+
+#define AR6000_IOCTL_WMI_SETSCAN             (SIOCIWFIRSTPRIV+13)
+/*
+ * arguments:
+ *   WMI_SCAN_PARAMS_CMD scanParams (see include/wmi.h)
+ * uses: WMI_SET_SCAN_PARAMS_CMDID
+ */
+
+#define AR6000_IOCTL_WMI_SETLISTENINT        (SIOCIWFIRSTPRIV+14)
+/*
+ * arguments:
+ *   UINT32 listenInterval
+ * uses: WMI_SET_LISTEN_INT_CMDID
+ */
+
+#define AR6000_IOCTL_WMI_SETBSSFILTER        (SIOCIWFIRSTPRIV+15)
+/*
+ * arguments:
+ *   WMI_BSS_FILTER filter (see include/wmi.h)
+ * uses: WMI_SET_BSS_FILTER_CMDID
+ */
+
+#define AR6000_IOCTL_WMI_SET_CHANNELPARAMS   (SIOCIWFIRSTPRIV+16)
+/*
+ * arguments:
+ *   WMI_CHANNEL_PARAMS_CMD chParams
+ * uses: WMI_SET_CHANNEL_PARAMS_CMDID
+ */
+
+#define AR6000_IOCTL_WMI_SET_PROBEDSSID      (SIOCIWFIRSTPRIV+17)
+/*
+ * arguments:
+ *   WMI_PROBED_SSID_CMD probedSsids (see include/wmi.h)
+ * uses: WMI_SETPROBED_SSID_CMDID
+ */
+
+#define AR6000_IOCTL_WMI_SET_PMPARAMS        (SIOCIWFIRSTPRIV+18)
+/*
+ * arguments:
+ *   WMI_POWER_PARAMS_CMD powerParams (see include/wmi.h)
+ * uses: WMI_SET_POWER_PARAMS_CMDID
+ */
+
+#define AR6000_IOCTL_WMI_SET_BADAP           (SIOCIWFIRSTPRIV+19)
+/*
+ * arguments:
+ *   WMI_ADD_BAD_AP_CMD badAPs (see include/wmi.h)
+ * uses: WMI_ADD_BAD_AP_CMDID
+ */
+
+#define AR6000_IOCTL_WMI_GET_QOS_QUEUE       (SIOCIWFIRSTPRIV+20)
+/*
+ * arguments:
+ *   ar6000_queuereq queueRequest (see below)
+ */
+
+#define AR6000_IOCTL_WMI_CREATE_QOS          (SIOCIWFIRSTPRIV+21)
+/*
+ * arguments:
+ *   WMI_CREATE_PSTREAM createPstreamCmd (see include/wmi.h)
+ * uses: WMI_CREATE_PSTREAM_CMDID
+ */
+
+#define AR6000_IOCTL_WMI_DELETE_QOS          (SIOCIWFIRSTPRIV+22)
+/*
+ * arguments:
+ *   WMI_DELETE_PSTREAM_CMD deletePstreamCmd (see include/wmi.h)
+ * uses: WMI_DELETE_PSTREAM_CMDID
+ */
+
+#define AR6000_IOCTL_WMI_SET_SNRTHRESHOLD   (SIOCIWFIRSTPRIV+23)
+/*
+ * arguments:
+ *   WMI_SNR_THRESHOLD_PARAMS_CMD thresholdParams (see include/wmi.h)
+ * uses: WMI_SNR_THRESHOLD_PARAMS_CMDID
+ */
+
+#define AR6000_IOCTL_WMI_SET_ERROR_REPORT_BITMASK (SIOCIWFIRSTPRIV+24)
+/*
+ * arguments:
+ *   WMI_TARGET_ERROR_REPORT_BITMASK errorReportBitMask (see include/wmi.h)
+ * uses: WMI_TARGET_ERROR_REPORT_BITMASK_CMDID
+ */
+
+#define AR6000_IOCTL_WMI_GET_TARGET_STATS    (SIOCIWFIRSTPRIV+25)
+/*
+ * arguments:
+ *   TARGET_STATS *targetStats (see below)
+ * uses: WMI_GET_STATISTICS_CMDID
+ */
+
+#define AR6000_IOCTL_WMI_SET_ASSOC_INFO      (SIOCIWFIRSTPRIV+26)
+/*
+ * arguments:
+ *   WMI_SET_ASSOC_INFO_CMD setAssocInfoCmd
+ * uses: WMI_SET_ASSOC_INFO_CMDID
+ */
+
+#define AR6000_IOCTL_WMI_SET_ACCESS_PARAMS   (SIOCIWFIRSTPRIV+27)
+/*
+ * arguments:
+ *   WMI_SET_ACCESS_PARAMS_CMD setAccessParams (see include/wmi.h)
+ * uses: WMI_SET_ACCESS_PARAMS_CMDID
+ */
+
+#define AR6000_IOCTL_WMI_SET_BMISS_TIME      (SIOCIWFIRSTPRIV+28)
+/*
+ * arguments:
+ *   UINT32 beaconMissTime
+ * uses: WMI_SET_BMISS_TIME_CMDID
+ */
+
+#define AR6000_IOCTL_WMI_SET_DISC_TIMEOUT    (SIOCIWFIRSTPRIV+29)
+/*
+ * arguments:
+ *   WMI_DISC_TIMEOUT_CMD disconnectTimeoutCmd (see include/wmi.h)
+ * uses: WMI_SET_DISC_TIMEOUT_CMDID
+ */
+
+#define AR6000_IOCTL_WMI_SET_IBSS_PM_CAPS    (SIOCIWFIRSTPRIV+30)
+/*
+ * arguments:
+ *   WMI_IBSS_PM_CAPS_CMD ibssPowerMgmtCapsCmd
+ * uses: WMI_SET_IBSS_PM_CAPS_CMDID
+ */
+
+/*
+ * There is a very small space available for driver-private
+ * wireless ioctls.  In order to circumvent this limitation,
+ * we multiplex a bunch of ioctls (XIOCTLs) on top of a
+ * single AR6000_IOCTL_EXTENDED ioctl.
+ */
+#define AR6000_IOCTL_EXTENDED                (SIOCIWFIRSTPRIV+31)
+
+
+/*                         ====BMI Extended Ioctls====                        */
+
+#define AR6000_XIOCTL_BMI_DONE                                  1
+/*
+ * arguments:
+ *   UINT32 cmd (AR6000_XIOCTL_BMI_DONE)
+ * uses: BMI_DONE
+ */
+
+#define AR6000_XIOCTL_BMI_READ_MEMORY                           2
+/*
+ * arguments:
+ *   union {
+ *     struct {
+ *       UINT32 cmd (AR6000_XIOCTL_BMI_READ_MEMORY)
+ *       UINT32 address
+ *       UINT32 length
+ *     }
+ *     char results[length]
+ *   }
+ * uses: BMI_READ_MEMORY
+ */
+
+#define AR6000_XIOCTL_BMI_WRITE_MEMORY                          3
+/*
+ * arguments:
+ *   UINT32 cmd (AR6000_XIOCTL_BMI_WRITE_MEMORY)
+ *   UINT32 address
+ *   UINT32 length
+ *   char data[length]
+ * uses: BMI_WRITE_MEMORY
+ */
+
+#define AR6000_XIOCTL_BMI_EXECUTE                               4
+/*
+ * arguments:
+ *   UINT32 cmd (AR6000_XIOCTL_BMI_EXECUTE)
+ *   UINT32 TargetAddress
+ *   UINT32 parameter
+ * uses: BMI_EXECUTE
+ */
+
+#define AR6000_XIOCTL_BMI_SET_APP_START                         5
+/*
+ * arguments:
+ *   UINT32 cmd (AR6000_XIOCTL_BMI_SET_APP_START)
+ *   UINT32 TargetAddress
+ * uses: BMI_SET_APP_START
+ */
+
+#define AR6000_XIOCTL_BMI_READ_SOC_REGISTER                     6
+/*
+ * arguments:
+ *   union {
+ *     struct {
+ *       UINT32 cmd (AR6000_XIOCTL_BMI_READ_SOC_REGISTER)
+ *       UINT32 TargetAddress, 32-bit aligned
+ *     }
+ *     UINT32 result
+ *   }
+ * uses: BMI_READ_SOC_REGISTER
+ */
+
+#define AR6000_XIOCTL_BMI_WRITE_SOC_REGISTER                    7
+/*
+ * arguments:
+ *     struct {
+ *       UINT32 cmd (AR6000_XIOCTL_BMI_WRITE_SOC_REGISTER)
+ *       UINT32 TargetAddress, 32-bit aligned
+ *       UINT32 newValue
+ *     }
+ * uses: BMI_WRITE_SOC_REGISTER
+ */
+
+#define AR6000_XIOCTL_BMI_TEST                                  8
+/*
+ * arguments:
+ *   UINT32 cmd (AR6000_XIOCTL_BMI_TEST)
+ *   UINT32 address
+ *   UINT32 length
+ *   UINT32 count
+ */
+
+
+
+/* Historical Host-side DataSet support */
+#define AR6000_XIOCTL_UNUSED9                                   9
+#define AR6000_XIOCTL_UNUSED10                                  10
+#define AR6000_XIOCTL_UNUSED11                                  11
+
+/*                      ====Misc Extended Ioctls====                          */
+
+#define AR6000_XIOCTL_FORCE_TARGET_RESET                        12
+/*
+ * arguments:
+ *   UINT32 cmd (AR6000_XIOCTL_FORCE_TARGET_RESET)
+ */
+
+
+#ifdef HTC_RAW_INTERFACE
+/* HTC Raw Interface Ioctls */
+#define AR6000_XIOCTL_HTC_RAW_OPEN                              13
+/*
+ * arguments:
+ *   UINT32 cmd (AR6000_XIOCTL_HTC_RAW_OPEN)
+ */
+
+#define AR6000_XIOCTL_HTC_RAW_CLOSE                             14
+/*
+ * arguments:
+ *   UINT32 cmd (AR6000_XIOCTL_HTC_RAW_CLOSE)
+ */
+
+#define AR6000_XIOCTL_HTC_RAW_READ                              15
+/*
+ * arguments:
+ *   union {
+ *     struct {
+ *       UINT32 cmd (AR6000_XIOCTL_HTC_RAW_READ)
+ *       UINT32 mailboxID
+ *       UINT32 length
+ *     }
+ *     results[length]
+ *   }
+ */
+
+#define AR6000_XIOCTL_HTC_RAW_WRITE                             16
+/*
+ * arguments:
+ *   UINT32 cmd (AR6000_XIOCTL_HTC_RAW_WRITE)
+ *   UINT32 mailboxID
+ *   UINT32 length
+ *   char buffer[length]
+ */
+#endif /* HTC_RAW_INTERFACE */
+
+#define AR6000_XIOCTL_CHECK_TARGET_READY                        17
+/*
+ * arguments:
+ *   UINT32 cmd (AR6000_XIOCTL_CHECK_TARGET_READY)
+ */
+
+
+
+/*                ====GPIO (General Purpose I/O) Extended Ioctls====          */
+
+#define AR6000_XIOCTL_GPIO_OUTPUT_SET                           18
+/*
+ * arguments:
+ *   UINT32 cmd (AR6000_XIOCTL_GPIO_OUTPUT_SET)
+ *   ar6000_gpio_output_set_cmd_s (see below)
+ * uses: WMIX_GPIO_OUTPUT_SET_CMDID
+ */
+
+#define AR6000_XIOCTL_GPIO_INPUT_GET                            19
+/*
+ * arguments:
+ *   UINT32 cmd (AR6000_XIOCTL_GPIO_INPUT_GET)
+ * uses: WMIX_GPIO_INPUT_GET_CMDID
+ */
+
+#define AR6000_XIOCTL_GPIO_REGISTER_SET                         20
+/*
+ * arguments:
+ *   UINT32 cmd (AR6000_XIOCTL_GPIO_REGISTER_SET)
+ *   ar6000_gpio_register_cmd_s (see below)
+ * uses: WMIX_GPIO_REGISTER_SET_CMDID
+ */
+
+#define AR6000_XIOCTL_GPIO_REGISTER_GET                         21
+/*
+ * arguments:
+ *   UINT32 cmd (AR6000_XIOCTL_GPIO_REGISTER_GET)
+ *   ar6000_gpio_register_cmd_s (see below)
+ * uses: WMIX_GPIO_REGISTER_GET_CMDID
+ */
+
+#define AR6000_XIOCTL_GPIO_INTR_ACK                             22
+/*
+ * arguments:
+ *   UINT32 cmd (AR6000_XIOCTL_GPIO_INTR_ACK)
+ *   ar6000_cpio_intr_ack_cmd_s (see below)
+ * uses: WMIX_GPIO_INTR_ACK_CMDID
+ */
+
+#define AR6000_XIOCTL_GPIO_INTR_WAIT                            23
+/*
+ * arguments:
+ *   UINT32 cmd (AR6000_XIOCTL_GPIO_INTR_WAIT)
+ */
+
+
+
+/*                    ====more wireless commands====                          */
+
+#define AR6000_XIOCTL_SET_ADHOC_BSSID                           24
+/*
+ * arguments:
+ *   UINT32 cmd (AR6000_XIOCTL_SET_ADHOC_BSSID)
+ *   WMI_SET_ADHOC_BSSID_CMD setAdHocBssidCmd (see include/wmi.h)
+ */
+
+#define AR6000_XIOCTL_SET_OPT_MODE                              25
+/*
+ * arguments:
+ *   UINT32 cmd (AR6000_XIOCTL_SET_OPT_MODE)
+ *   WMI_SET_OPT_MODE_CMD setOptModeCmd (see include/wmi.h)
+ * uses: WMI_SET_OPT_MODE_CMDID
+ */
+
+#define AR6000_XIOCTL_OPT_SEND_FRAME                            26
+/*
+ * arguments:
+ *   UINT32 cmd (AR6000_XIOCTL_OPT_SEND_FRAME)
+ *   WMI_OPT_TX_FRAME_CMD optTxFrameCmd (see include/wmi.h)
+ * uses: WMI_OPT_TX_FRAME_CMDID
+ */
+
+#define AR6000_XIOCTL_SET_BEACON_INTVAL                         27
+/*
+ * arguments:
+ *   UINT32 cmd (AR6000_XIOCTL_SET_BEACON_INTVAL)
+ *   WMI_BEACON_INT_CMD beaconIntCmd (see include/wmi.h)
+ * uses: WMI_SET_BEACON_INT_CMDID
+ */
+
+
+#define IEEE80211_IOCTL_SETAUTHALG                              28
+
+
+#define AR6000_XIOCTL_SET_VOICE_PKT_SIZE                        29
+/*
+ * arguments:
+ *   UINT32 cmd (AR6000_XIOCTL_SET_VOICE_PKT_SIZE)
+ *   WMI_SET_VOICE_PKT_SIZE_CMD setVoicePktSizeCmd (see include/wmi.h)
+ * uses: WMI_SET_VOICE_PKT_SIZE_CMDID
+ */
+
+
+#define AR6000_XIOCTL_SET_MAX_SP                                30
+/*
+ * arguments:
+ *   UINT32 cmd (AR6000_XIOCTL_SET_MAX_SP)
+ *   WMI_SET_MAX_SP_LEN_CMD maxSPLen(see include/wmi.h)
+ * uses: WMI_SET_MAX_SP_LEN_CMDID
+ */
+
+#define AR6000_XIOCTL_WMI_GET_ROAM_TBL                          31
+
+#define AR6000_XIOCTL_WMI_SET_ROAM_CTRL                         32
+
+#define AR6000_XIOCTRL_WMI_SET_POWERSAVE_TIMERS                 33
+
+
+/*
+ * arguments:
+ *   UINT32 cmd (AR6000_XIOCTRL_WMI_SET_POWERSAVE_TIMERS)
+ *   WMI_SET_POWERSAVE_TIMERS_CMD powerSaveTimers(see include/wmi.h)
+ *   WMI_SET_POWERSAVE_TIMERS_CMDID
+ */
+
+#define AR6000_XIOCTRL_WMI_GET_POWER_MODE                        34
+/*
+ * arguments:
+ *   UINT32 cmd (AR6000_XIOCTRL_WMI_GET_POWER_MODE)
+ */
+
+#define AR6000_XIOCTRL_WMI_SET_WLAN_STATE                       35
+typedef enum {
+    WLAN_DISABLED,
+    WLAN_ENABLED
+} AR6000_WLAN_STATE;
+/*
+ * arguments:
+ * enable/disable
+ */
+
+#define AR6000_XIOCTL_WMI_GET_ROAM_DATA                         36
+
+#define AR6000_XIOCTL_WMI_SETRETRYLIMITS                37
+/*
+ * arguments:
+ *   WMI_SET_RETRY_LIMITS_CMD ibssSetRetryLimitsCmd
+ * uses: WMI_SET_RETRY_LIMITS_CMDID
+ */
+
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+/*       ====extended commands for radio test ====                          */
+
+#define AR6000_XIOCTL_TCMD_CONT_TX                      38
+/*
+ * arguments:
+ *   UINT32 cmd (AR6000_XIOCTL_TCMD_CONT_TX)
+ *   WMI_TCMD_CONT_TX_CMD contTxCmd (see include/wmi.h)
+ * uses: WMI_TCMD_CONT_TX_CMDID
+ */
+
+#define AR6000_XIOCTL_TCMD_CONT_RX                      39
+/*
+ * arguments:
+ *   UINT32 cmd (AR6000_XIOCTL_TCMD_CONT_RX)
+ *   WMI_TCMD_CONT_RX_CMD rxCmd (see include/wmi.h)
+ * uses: WMI_TCMD_CONT_RX_CMDID
+ */
+
+#define AR6000_XIOCTL_TCMD_PM                           40
+/*
+ * arguments:
+ *   UINT32 cmd (AR6000_XIOCTL_TCMD_PM)
+ *   WMI_TCMD_PM_CMD pmCmd (see include/wmi.h)
+ * uses: WMI_TCMD_PM_CMDID
+ */
+
+#endif /* CONFIG_HOST_TCMD_SUPPORT */
+
+#define AR6000_XIOCTL_WMI_STARTSCAN                     41
+/*
+ * arguments:
+ *   UINT32 cmd (AR6000_XIOCTL_WMI_STARTSCAN)
+ *   UINT8  scanType
+ *   UINT8  scanConnected
+ *   A_BOOL forceFgScan
+ * uses: WMI_START_SCAN_CMDID
+ */
+
+#define AR6000_XIOCTL_WMI_SETFIXRATES                   42
+
+#define AR6000_XIOCTL_WMI_GETFIXRATES                   43
+
+
+#define AR6000_XIOCTL_WMI_SET_RSSITHRESHOLD             44
+/*
+ * arguments:
+ *   WMI_RSSI_THRESHOLD_PARAMS_CMD thresholdParams (see include/wmi.h)
+ * uses: WMI_RSSI_THRESHOLD_PARAMS_CMDID
+ */
+
+#define AR6000_XIOCTL_WMI_CLR_RSSISNR                   45
+/*
+ * arguments:
+ *   WMI_CLR_RSSISNR_CMD thresholdParams (see include/wmi.h)
+ * uses: WMI_CLR_RSSISNR_CMDID
+ */
+
+#define AR6000_XIOCTL_WMI_SET_LQTHRESHOLD               46
+/*
+ * arguments:
+ *   WMI_LQ_THRESHOLD_PARAMS_CMD thresholdParams (see include/wmi.h)
+ * uses: WMI_LQ_THRESHOLD_PARAMS_CMDID
+ */
+
+#define AR6000_XIOCTL_WMI_SET_RTS                        47
+/*
+ * arguments:
+ *   WMI_SET_RTS_MODE_CMD (see include/wmi.h)
+ * uses: WMI_SET_RTS_MODE_CMDID
+ */
+
+#define AR6000_XIOCTL_WMI_SET_LPREAMBLE                 48
+
+#define AR6000_XIOCTL_WMI_SET_AUTHMODE                  49
+/*
+ * arguments:
+ *   UINT32 cmd (AR6000_XIOCTL_WMI_SET_AUTHMODE)
+ *   UINT8  mode
+ * uses: WMI_SET_RECONNECT_AUTH_MODE_CMDID
+ */
+
+#define AR6000_XIOCTL_WMI_SET_REASSOCMODE               50
+
+/*
+ * arguments:
+ *   UINT32 cmd (AR6000_XIOCTL_WMI_SET_WMM)
+ *   UINT8  mode
+ * uses: WMI_SET_WMM_CMDID
+ */
+#define AR6000_XIOCTL_WMI_SET_WMM                       51
+
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_WMI_SET_HB_CHALLENGE_RESP_PARAMS)
+ * UINT32 frequency
+ * UINT8  threshold
+ */
+#define AR6000_XIOCTL_WMI_SET_HB_CHALLENGE_RESP_PARAMS  52
+
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_WMI_GET_HB_CHALLENGE_RESP)
+ * UINT32 cookie
+ */
+#define AR6000_XIOCTL_WMI_GET_HB_CHALLENGE_RESP         53
+
+/*
+ * arguments:
+ *   UINT32 cmd (AR6000_XIOCTL_WMI_GET_RD)
+ *   UINT32 regDomain
+ */
+#define AR6000_XIOCTL_WMI_GET_RD                        54
+
+#define AR6000_XIOCTL_DIAG_READ                         55
+
+#define AR6000_XIOCTL_DIAG_WRITE                        56
+
+/*
+ * arguments cmd (AR6000_XIOCTL_SET_TXOP)
+ * WMI_TXOP_CFG  txopEnable
+ */
+#define AR6000_XIOCTL_WMI_SET_TXOP                      57
+
+#ifdef USER_KEYS
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_USER_SETKEYS)
+ * UINT32 keyOpCtrl
+ * uses AR6000_USER_SETKEYS_INFO
+ */
+#define AR6000_XIOCTL_USER_SETKEYS                      58
+#endif /* USER_KEYS */
+
+#define AR6000_XIOCTL_WMI_SET_KEEPALIVE                 59
+/*
+ * arguments:
+ *   UINT8 cmd (AR6000_XIOCTL_WMI_SET_KEEPALIVE)
+ *   UINT8 keepaliveInterval
+ * uses: WMI_SET_KEEPALIVE_CMDID
+ */
+
+#define AR6000_XIOCTL_WMI_GET_KEEPALIVE                 60
+/*
+ * arguments:
+ *   UINT8 cmd (AR6000_XIOCTL_WMI_GET_KEEPALIVE)
+ *   UINT8 keepaliveInterval
+ *   A_BOOL configured
+ * uses: WMI_GET_KEEPALIVE_CMDID
+ */
+
+/*               ====ROM Patching Extended Ioctls====                       */
+
+#define AR6000_XIOCTL_BMI_ROMPATCH_INSTALL              61
+/*
+ * arguments:
+ *     union {
+ *       struct {
+ *         UINT32 cmd (AR6000_XIOCTL_BMI_ROMPATCH_INSTALL)
+ *         UINT32 ROM Address
+ *         UINT32 RAM Address
+ *         UINT32 number of bytes
+ *         UINT32 activate? (0 or 1)
+ *       }
+ *       A_UINT32 resulting rompatch ID
+ *     }
+ * uses: BMI_ROMPATCH_INSTALL
+ */
+
+#define AR6000_XIOCTL_BMI_ROMPATCH_UNINSTALL            62
+/*
+ * arguments:
+ *     struct {
+ *       UINT32 cmd (AR6000_XIOCTL_BMI_ROMPATCH_UNINSTALL)
+ *       UINT32 rompatch ID
+ *     }
+ * uses: BMI_ROMPATCH_UNINSTALL
+ */
+
+#define AR6000_XIOCTL_BMI_ROMPATCH_ACTIVATE             63
+/*
+ * arguments:
+ *     struct {
+ *       UINT32 cmd (AR6000_XIOCTL_BMI_ROMPATCH_ACTIVATE)
+ *       UINT32 rompatch count
+ *       UINT32 rompatch IDs[rompatch count]
+ *     }
+ * uses: BMI_ROMPATCH_ACTIVATE
+ */
+
+#define AR6000_XIOCTL_BMI_ROMPATCH_DEACTIVATE           64
+/*
+ * arguments:
+ *     struct {
+ *       UINT32 cmd (AR6000_XIOCTL_BMI_ROMPATCH_DEACTIVATE)
+ *       UINT32 rompatch count
+ *       UINT32 rompatch IDs[rompatch count]
+ *     }
+ * uses: BMI_ROMPATCH_DEACTIVATE
+ */
+
+#define AR6000_XIOCTL_WMI_SET_APPIE             65
+/*
+ * arguments:
+ *      struct {
+ *          UINT32 cmd (AR6000_XIOCTL_WMI_SET_APPIE)
+ *          UINT32  app_frmtype;
+ *          UINT32  app_buflen;
+ *          UINT8   app_buf[];
+ *      }
+ */
+#define AR6000_XIOCTL_WMI_SET_MGMT_FRM_RX_FILTER    66
+/*
+ * arguments:
+ *      A_UINT32 filter_type;
+ */
+
+#define AR6000_XIOCTL_DBGLOG_CFG_MODULE             67
+
+#define AR6000_XIOCTL_DBGLOG_GET_DEBUG_LOGS         68
+
+#define AR6000_XIOCTL_WMI_SET_WSC_STATUS            70
+/*
+ * arguments:
+ *      A_UINT32 wsc_status;
+ *            (WSC_REG_INACTIVE or WSC_REG_ACTIVE)
+ */
+
+/*
+ * arguments:
+ *      struct {
+ *          A_UINT8 streamType;
+ *          A_UINT8 status;
+ *      }
+ * uses: WMI_SET_BT_STATUS_CMDID
+ */
+#define AR6000_XIOCTL_WMI_SET_BT_STATUS             71
+
+/*
+ * arguments:
+ *      struct {
+ *           A_UINT8 paramType;
+ *           union {
+ *               A_UINT8 noSCOPkts;
+ *               BT_PARAMS_A2DP a2dpParams;
+ *               BT_COEX_REGS regs;
+ *           };
+ *      }
+ * uses: WMI_SET_BT_PARAM_CMDID
+ */
+#define AR6000_XIOCTL_WMI_SET_BT_PARAMS             72
+
+#define AR6000_XIOCTL_WMI_SET_HOST_SLEEP_MODE       73
+#define AR6000_XIOCTL_WMI_SET_WOW_MODE              74
+#define AR6000_XIOCTL_WMI_GET_WOW_LIST              75
+#define AR6000_XIOCTL_WMI_ADD_WOW_PATTERN           76
+#define AR6000_XIOCTL_WMI_DEL_WOW_PATTERN           77
+
+
+
+#define AR6000_XIOCTL_TARGET_INFO                   78
+/*
+ * arguments:
+ *   UINT32 cmd (AR6000_XIOCTL_TARGET_INFO)
+ *   A_UINT32 TargetVersion (returned)
+ *   A_UINT32 TargetType    (returned)
+ * (See also bmi_msg.h target_ver and target_type)
+ */
+
+#define AR6000_XIOCTL_DUMP_HTC_CREDIT_STATE         79
+/*
+ * arguments:
+ *      none
+ */
+
+#define AR6000_XIOCTL_TRAFFIC_ACTIVITY_CHANGE       80
+/*
+ * This ioctl is used to emulate traffic activity
+ * timeouts.  Activity/inactivity will trigger the driver
+ * to re-balance credits.
+ *
+ * arguments:
+ *      ar6000_traffic_activity_change
+ */
+
+#define AR6000_XIOCTL_WMI_SET_CONNECT_CTRL_FLAGS    81
+/*
+ * This ioctl is used to set the connect control flags
+ *
+ * arguments:
+ *      A_UINT32 connectCtrlFlags
+ */
+
+#define AR6000_XIOCTL_WMI_SET_AKMP_PARAMS              82
+/*
+ * This IOCTL sets any Authentication,Key Management and Protection
+ * related parameters. This is used along with the information set in
+ * Connect Command.
+ * Currently this enables Multiple PMKIDs to an AP.
+ *
+ * arguments:
+ *      struct {
+ *          A_UINT32    akmpInfo;
+ *      }
+ * uses: WMI_SET_AKMP_PARAMS_CMD
+ */
+
+#define AR6000_XIOCTL_WMI_GET_PMKID_LIST            83
+
+#define AR6000_XIOCTL_WMI_SET_PMKID_LIST            84
+/*
+ * This IOCTL is used to set a list of PMKIDs. This list of
+ * PMKIDs is used in the [Re]AssocReq Frame. This list is used
+ * only if the MultiPMKID option is enabled via the
+ * AR6000_XIOCTL_WMI_SET_AKMP_PARAMS  IOCTL.
+ *
+ * arguments:
+ *      struct {
+ *          A_UINT32    numPMKID;
+ *          WMI_PMKID   pmkidList[WMI_MAX_PMKID_CACHE];
+ *      }
+ * uses: WMI_SET_PMKIDLIST_CMD
+ */
+
+#define AR6000_XIOCTL_WMI_SET_PARAMS                85
+#define AR6000_XIOCTL_WMI_SET_MCAST_FILTER     86
+#define AR6000_XIOCTL_WMI_DEL_MCAST_FILTER     87
+
+
+/* Historical DSETPATCH support for INI patches */
+#define AR6000_XIOCTL_UNUSED90                      90
+
+
+/* Support LZ-compressed firmware download */
+#define AR6000_XIOCTL_BMI_LZ_STREAM_START           91
+/*
+ * arguments:
+ *   UINT32 cmd (AR6000_XIOCTL_BMI_LZ_STREAM_START)
+ *   UINT32 address
+ * uses: BMI_LZ_STREAM_START
+ */
+
+#define AR6000_XIOCTL_BMI_LZ_DATA                   92
+/*
+ * arguments:
+ *   UINT32 cmd (AR6000_XIOCTL_BMI_LZ_DATA)
+ *   UINT32 length
+ *   char data[length]
+ * uses: BMI_LZ_DATA
+ */
+
+#define AR6000_XIOCTL_PROF_CFG                      93
+/*
+ * arguments:
+ *   A_UINT32 period
+ *   A_UINT32 nbins
+ */
+
+#define AR6000_XIOCTL_PROF_ADDR_SET                 94
+/*
+ * arguments:
+ *   A_UINT32 Target address
+ */
+
+#define AR6000_XIOCTL_PROF_START                    95
+
+#define AR6000_XIOCTL_PROF_STOP                     96
+
+#define AR6000_XIOCTL_PROF_COUNT_GET                97
+
+#define AR6000_XIOCTL_WMI_ABORT_SCAN                98
+
+/*
+ * AP mode
+ */
+#define AR6000_XIOCTL_AP_GET_STA_LIST               99
+
+#define AR6000_XIOCTL_AP_HIDDEN_SSID                100
+
+#define AR6000_XIOCTL_AP_SET_NUM_STA                101
+
+#define AR6000_XIOCTL_AP_SET_ACL_MAC                102
+
+#define AR6000_XIOCTL_AP_GET_ACL_LIST               103
+
+#define AR6000_XIOCTL_AP_COMMIT_CONFIG              104
+
+#define IEEE80211_IOCTL_GETWPAIE                    105
+
+#define AR6000_XIOCTL_AP_CONN_INACT_TIME            106
+
+#define AR6000_XIOCTL_AP_PROT_SCAN_TIME             107
+
+#define AR6000_XIOCTL_AP_SET_COUNTRY                108
+
+#define AR6000_XIOCTL_AP_SET_DTIM                   109
+
+
+
+
+#define AR6000_XIOCTL_WMI_TARGET_EVENT_REPORT       110
+
+#define AR6000_XIOCTL_SET_IP                        111
+
+#define AR6000_XIOCTL_AP_SET_ACL_POLICY             112
+
+#define AR6000_XIOCTL_AP_INTRA_BSS_COMM             113
+
+#define AR6000_XIOCTL_DUMP_MODULE_DEBUG_INFO        114
+
+#define AR6000_XIOCTL_MODULE_DEBUG_SET_MASK         115
+
+#define AR6000_XIOCTL_MODULE_DEBUG_GET_MASK         116
+
+#define AR6000_XIOCTL_DUMP_RCV_AGGR_STATS           117
+
+#define AR6000_XIOCTL_SET_HT_CAP                    118
+
+#define AR6000_XIOCTL_SET_HT_OP                     119
+
+#define AR6000_XIOCTL_AP_GET_STAT                   120
+
+#define AR6000_XIOCTL_SET_TX_SELECT_RATES           121
+
+#define AR6000_XIOCTL_SETUP_AGGR                    122
+
+#define AR6000_XIOCTL_ALLOW_AGGR                    123
+
+#define AR6000_XIOCTL_AP_GET_HIDDEN_SSID            124
+
+#define AR6000_XIOCTL_AP_GET_COUNTRY                125
+
+#define AR6000_XIOCTL_AP_GET_WMODE                  126
+
+#define AR6000_XIOCTL_AP_GET_DTIM                   127
+
+#define AR6000_XIOCTL_AP_GET_BINTVL                 128
+
+#define AR6000_XIOCTL_AP_GET_RTS                    129
+
+#define AR6000_XIOCTL_DELE_AGGR                     130
+
+#define AR6000_XIOCTL_FETCH_TARGET_REGS             131
+
+#define AR6000_XIOCTL_HCI_CMD                       132
+
+#define AR6000_XIOCTL_ACL_DATA                      133
+
+#define AR6000_XIOCTL_WLAN_CONN_PRECEDENCE          134
+
+#define AR6000_XIOCTL_AP_SET_11BG_RATESET           135
+
+/*
+ * arguments:
+ *   WMI_AP_PS_CMD apPsCmd
+ * uses: WMI_AP_PS_CMDID
+ */
+
+#define AR6000_XIOCTL_WMI_SET_AP_PS                 136
+
+#define AR6000_XIOCTL_WMI_MCAST_FILTER              137
+
+#define AR6000_XIOCTL_WMI_SET_BTCOEX_FE_ANT					138
+
+#define AR6000_XIOCTL_WMI_SET_BTCOEX_COLOCATED_BT_DEV			139
+
+#define AR6000_XIOCTL_WMI_SET_BTCOEX_BTINQUIRY_PAGE_CONFIG 	140
+
+#define AR6000_XIOCTL_WMI_SET_BTCOEX_SCO_CONFIG				141
+
+#define AR6000_XIOCTL_WMI_SET_BTCOEX_A2DP_CONFIG				142
+
+#define AR6000_XIOCTL_WMI_SET_BTCOEX_ACLCOEX_CONFIG			143
+
+#define AR6000_XIOCTL_WMI_SET_BTCOEX_DEBUG						144
+
+#define AR6000_XIOCTL_WMI_SET_BT_OPERATING_STATUS   			145
+
+#define AR6000_XIOCTL_WMI_GET_BTCOEX_CONFIG					146
+
+#define AR6000_XIOCTL_WMI_GET_BTCOEX_STATS						147
+/*
+ * arguments:
+ *   UINT32 cmd (AR6000_XIOCTL_WMI_SET_QOS_SUPP)
+ *   UINT8  mode
+ * uses: WMI_SET_QOS_SUPP_CMDID
+ */
+#define AR6000_XIOCTL_WMI_SET_QOS_SUPP                  148 
+
+#define AR6000_XIOCTL_GET_WLAN_SLEEP_STATE              149
+
+#define AR6000_XIOCTL_SET_BT_HW_POWER_STATE             150 
+
+#define AR6000_XIOCTL_GET_BT_HW_POWER_STATE             151
+
+#define AR6000_XIOCTL_ADD_AP_INTERFACE                  152
+
+#define AR6000_XIOCTL_REMOVE_AP_INTERFACE               153
+
+#define AR6000_XIOCTL_WMI_SET_TX_SGI_PARAM              154
+
+
+/* used by AR6000_IOCTL_WMI_GETREV */
+struct ar6000_version {
+    A_UINT32        host_ver;
+    A_UINT32        target_ver;
+    A_UINT32        wlan_ver;
+    A_UINT32        abi_ver;
+};
+
+/* used by AR6000_IOCTL_WMI_GET_QOS_QUEUE */
+struct ar6000_queuereq {
+    A_UINT8         trafficClass;
+    A_UINT16        activeTsids;
+};
+
+/* used by AR6000_IOCTL_WMI_GET_TARGET_STATS */
+typedef struct targetStats_t {
+    A_UINT64    tx_packets;
+    A_UINT64    tx_bytes;
+    A_UINT64    tx_unicast_pkts;
+    A_UINT64    tx_unicast_bytes;
+    A_UINT64    tx_multicast_pkts;
+    A_UINT64    tx_multicast_bytes;
+    A_UINT64    tx_broadcast_pkts;
+    A_UINT64    tx_broadcast_bytes;
+    A_UINT64    tx_rts_success_cnt;
+    A_UINT64    tx_packet_per_ac[4];
+
+    A_UINT64    tx_errors;
+    A_UINT64    tx_failed_cnt;
+    A_UINT64    tx_retry_cnt;
+    A_UINT64    tx_mult_retry_cnt;
+    A_UINT64    tx_rts_fail_cnt;
+
+    A_UINT64    rx_packets;
+    A_UINT64    rx_bytes;
+    A_UINT64    rx_unicast_pkts;
+    A_UINT64    rx_unicast_bytes;
+    A_UINT64    rx_multicast_pkts;
+    A_UINT64    rx_multicast_bytes;
+    A_UINT64    rx_broadcast_pkts;
+    A_UINT64    rx_broadcast_bytes;
+    A_UINT64    rx_fragment_pkt;
+
+    A_UINT64    rx_errors;
+    A_UINT64    rx_crcerr;
+    A_UINT64    rx_key_cache_miss;
+    A_UINT64    rx_decrypt_err;
+    A_UINT64    rx_duplicate_frames;
+
+    A_UINT64    tkip_local_mic_failure;
+    A_UINT64    tkip_counter_measures_invoked;
+    A_UINT64    tkip_replays;
+    A_UINT64    tkip_format_errors;
+    A_UINT64    ccmp_format_errors;
+    A_UINT64    ccmp_replays;
+
+    A_UINT64    power_save_failure_cnt;
+
+    A_UINT64    cs_bmiss_cnt;
+    A_UINT64    cs_lowRssi_cnt;
+    A_UINT64    cs_connect_cnt;
+    A_UINT64    cs_disconnect_cnt;
+
+    A_INT32     tx_unicast_rate;
+    A_INT32     rx_unicast_rate;
+
+    A_UINT32    lq_val;
+
+    A_UINT32    wow_num_pkts_dropped;
+    A_UINT16    wow_num_events_discarded;
+
+    A_INT16     noise_floor_calibation;
+    A_INT16     cs_rssi;
+    A_INT16     cs_aveBeacon_rssi;
+    A_UINT8     cs_aveBeacon_snr;
+    A_UINT8     cs_lastRoam_msec;
+    A_UINT8     cs_snr;
+
+    A_UINT8     wow_num_host_pkt_wakeups;
+    A_UINT8     wow_num_host_event_wakeups;
+
+    A_UINT32   arp_received;
+    A_UINT32   arp_matched;
+    A_UINT32   arp_replied;
+}TARGET_STATS;
+
+typedef struct targetStats_cmd_t {
+    TARGET_STATS targetStats;
+    int clearStats;
+} TARGET_STATS_CMD;
+
+/* used by AR6000_XIOCTL_USER_SETKEYS */
+
+/*
+ * Setting this bit to 1 doesnot initialize the RSC on the firmware
+ */
+#define AR6000_XIOCTL_USER_SETKEYS_RSC_CTRL    1
+#define AR6000_USER_SETKEYS_RSC_UNCHANGED     0x00000002
+
+typedef struct {
+    A_UINT32  keyOpCtrl;  /* Bit Map of Key Mgmt Ctrl Flags */
+} AR6000_USER_SETKEYS_INFO;
+
+
+/* used by AR6000_XIOCTL_GPIO_OUTPUT_SET */
+struct ar6000_gpio_output_set_cmd_s {
+    A_UINT32 set_mask;
+    A_UINT32 clear_mask;
+    A_UINT32 enable_mask;
+    A_UINT32 disable_mask;
+};
+
+/*
+ * used by AR6000_XIOCTL_GPIO_REGISTER_GET and AR6000_XIOCTL_GPIO_REGISTER_SET
+ */
+struct ar6000_gpio_register_cmd_s {
+    A_UINT32 gpioreg_id;
+    A_UINT32 value;
+};
+
+/* used by AR6000_XIOCTL_GPIO_INTR_ACK */
+struct ar6000_gpio_intr_ack_cmd_s {
+    A_UINT32 ack_mask;
+};
+
+/* used by AR6000_XIOCTL_GPIO_INTR_WAIT */
+struct ar6000_gpio_intr_wait_cmd_s {
+    A_UINT32 intr_mask;
+    A_UINT32 input_values;
+};
+
+/* used by the AR6000_XIOCTL_DBGLOG_CFG_MODULE */
+typedef struct ar6000_dbglog_module_config_s {
+    A_UINT32 valid;
+    A_UINT16 mmask;
+    A_UINT16 tsr;
+    A_BOOL   rep;
+    A_UINT16 size;
+} DBGLOG_MODULE_CONFIG;
+
+typedef struct user_rssi_thold_t {
+    A_INT16     tag;
+    A_INT16     rssi;
+} USER_RSSI_THOLD;
+
+typedef struct user_rssi_params_t {
+    A_UINT8            weight;
+    A_UINT32           pollTime;
+    USER_RSSI_THOLD    tholds[12];
+} USER_RSSI_PARAMS;
+
+typedef struct ar6000_get_btcoex_config_cmd_t{
+	A_UINT32 btProfileType;
+	A_UINT32 linkId;
+ }AR6000_GET_BTCOEX_CONFIG_CMD;
+
+typedef struct ar6000_btcoex_config_t {
+    AR6000_GET_BTCOEX_CONFIG_CMD  configCmd;
+    A_UINT32 * configEvent;
+} AR6000_BTCOEX_CONFIG;
+
+typedef struct ar6000_btcoex_stats_t {
+    A_UINT32 * statsEvent;
+ }AR6000_BTCOEX_STATS;
+/*
+ * Host driver may have some config parameters. Typically, these
+ * config params are one time config parameters. These could
+ * correspond to any of the underlying modules. Host driver exposes
+ * an api for the underlying modules to get this config.
+ */
+#define AR6000_DRIVER_CFG_BASE                  0x8000
+
+/* Should driver perform wlan node caching? */
+#define AR6000_DRIVER_CFG_GET_WLANNODECACHING   0x8001
+/*Should we log raw WMI msgs */
+#define AR6000_DRIVER_CFG_LOG_RAW_WMI_MSGS      0x8002
+
+/* used by AR6000_XIOCTL_DIAG_READ & AR6000_XIOCTL_DIAG_WRITE */
+struct ar6000_diag_window_cmd_s {
+    unsigned int addr;
+    unsigned int value;
+};
+
+
+struct ar6000_traffic_activity_change {
+    A_UINT32    StreamID;   /* stream ID to indicate activity change */
+    A_UINT32    Active;     /* active (1) or inactive (0) */
+};
+
+/* Used with AR6000_XIOCTL_PROF_COUNT_GET */
+struct prof_count_s {
+    A_UINT32    addr;       /* bin start address */
+    A_UINT32    count;      /* hit count */
+};
+
+
+/* used by AR6000_XIOCTL_MODULE_DEBUG_SET_MASK */
+/*         AR6000_XIOCTL_MODULE_DEBUG_GET_MASK */
+/*         AR6000_XIOCTL_DUMP_MODULE_DEBUG_INFO */
+struct drv_debug_module_s {
+    A_CHAR      modulename[128];   /* name of module */
+    A_UINT32    mask;              /* new mask to set .. or .. current mask */
+};
+
+
+/* All HCI related rx events are sent up to the host app
+ * via a wmi event id. It can contain ACL data or HCI event, 
+ * based on which it will be de-multiplexed.
+ */
+typedef enum {
+    PAL_HCI_EVENT = 0,
+    PAL_HCI_RX_DATA,
+} WMI_PAL_EVENT_INFO;
+
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/drivers/net/ath6kl/os/linux/include/athtypes_linux.h b/drivers/net/ath6kl/os/linux/include/athtypes_linux.h
new file mode 100644
index 00000000000..9d9ecbb2a4d
--- /dev/null
+++ b/drivers/net/ath6kl/os/linux/include/athtypes_linux.h
@@ -0,0 +1,53 @@
+//------------------------------------------------------------------------------
+//
+// This file contains the definitions of the basic atheros data types.
+// It is used to map the data types in atheros files to a platform specific
+// type.
+// Copyright (c) 2004-2010 Atheros Communications Inc.
+// All rights reserved.
+//
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//
+// Author(s): ="Atheros"
+//------------------------------------------------------------------------------
+
+#ifndef _ATHTYPES_LINUX_H_
+#define _ATHTYPES_LINUX_H_
+
+#ifdef __KERNEL__
+#include <linux/types.h>
+#else
+#include <sys/types.h>
+#endif
+
+typedef int8_t      A_INT8;
+typedef int16_t     A_INT16;
+typedef int32_t     A_INT32;
+typedef int64_t     A_INT64;
+
+typedef u_int8_t     A_UINT8;
+typedef u_int16_t    A_UINT16;
+typedef u_int32_t    A_UINT32;
+typedef u_int64_t    A_UINT64;
+
+typedef int             A_BOOL;
+typedef char            A_CHAR;
+typedef unsigned char   A_UCHAR;
+typedef unsigned long   A_ATH_TIMER;
+
+
+#endif /* _ATHTYPES_LINUX_H_ */
diff --git a/drivers/net/ath6kl/os/linux/include/cfg80211.h b/drivers/net/ath6kl/os/linux/include/cfg80211.h
new file mode 100644
index 00000000000..b60e8acf493
--- /dev/null
+++ b/drivers/net/ath6kl/os/linux/include/cfg80211.h
@@ -0,0 +1,50 @@
+//------------------------------------------------------------------------------
+// Copyright (c) 2004-2010 Atheros Communications Inc.
+// All rights reserved.
+//
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//
+// Author(s): ="Atheros"
+//------------------------------------------------------------------------------
+
+#ifndef _AR6K_CFG80211_H_
+#define _AR6K_CFG80211_H_
+
+struct wireless_dev *ar6k_cfg80211_init(struct device *dev);
+void ar6k_cfg80211_deinit(AR_SOFTC_T *ar);
+
+void ar6k_cfg80211_scanComplete_event(AR_SOFTC_T *ar, A_STATUS status);
+
+void ar6k_cfg80211_connect_event(AR_SOFTC_T *ar, A_UINT16 channel,
+                                A_UINT8 *bssid, A_UINT16 listenInterval,
+                                A_UINT16 beaconInterval,NETWORK_TYPE networkType,
+                                A_UINT8 beaconIeLen, A_UINT8 assocReqLen,
+                                A_UINT8 assocRespLen, A_UINT8 *assocInfo);
+
+void ar6k_cfg80211_disconnect_event(AR_SOFTC_T *ar, A_UINT8 reason,
+                                    A_UINT8 *bssid, A_UINT8 assocRespLen,
+                                    A_UINT8 *assocInfo, A_UINT16 protocolReasonStatus);
+
+void ar6k_cfg80211_tkip_micerr_event(AR_SOFTC_T *ar, A_UINT8 keyid, A_BOOL ismcast);
+
+#endif /* _AR6K_CFG80211_H_ */
+
+
+
+
+
+
diff --git a/drivers/net/ath6kl/os/linux/include/config_linux.h b/drivers/net/ath6kl/os/linux/include/config_linux.h
new file mode 100644
index 00000000000..50f53d36104
--- /dev/null
+++ b/drivers/net/ath6kl/os/linux/include/config_linux.h
@@ -0,0 +1,60 @@
+//------------------------------------------------------------------------------
+// Copyright (c) 2004-2010 Atheros Communications Inc.
+// All rights reserved.
+//
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//
+// Author(s): ="Atheros"
+//------------------------------------------------------------------------------
+
+#ifndef _CONFIG_LINUX_H_
+#define _CONFIG_LINUX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <linux/version.h>
+
+/*
+ * Host-side GPIO support is optional.
+ * If run-time access to GPIO pins is not required, then
+ * this should be changed to #undef.
+ */
+#define CONFIG_HOST_GPIO_SUPPORT
+
+/*
+ * Host side Test Command support
+ */
+#define CONFIG_HOST_TCMD_SUPPORT
+
+#define USE_4BYTE_REGISTER_ACCESS
+
+/* Host-side support for Target-side profiling */
+#undef CONFIG_TARGET_PROFILE_SUPPORT
+
+/* IP/TCP checksum offload */
+/* Checksum offload is currently not supported for 64 bit platforms */
+#ifndef __LP64__
+#define CONFIG_CHECKSUM_OFFLOAD
+#endif /* __LP64__ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/drivers/net/ath6kl/os/linux/include/debug_linux.h b/drivers/net/ath6kl/os/linux/include/debug_linux.h
new file mode 100644
index 00000000000..b8dba52badc
--- /dev/null
+++ b/drivers/net/ath6kl/os/linux/include/debug_linux.h
@@ -0,0 +1,50 @@
+//------------------------------------------------------------------------------
+// Copyright (c) 2004-2010 Atheros Communications Inc.
+// All rights reserved.
+//
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//
+// Author(s): ="Atheros"
+//------------------------------------------------------------------------------
+
+#ifndef _DEBUG_LINUX_H_
+#define _DEBUG_LINUX_H_
+
+    /* macro to remove parens */
+#define ATH_PRINTX_ARG(arg...) arg
+
+#ifdef DEBUG
+    /* NOTE: the AR_DEBUG_PRINTF macro is defined here to handle special handling of variable arg macros
+     * which may be compiler dependent. */
+#define AR_DEBUG_PRINTF(mask, args) do {        \
+    if (GET_ATH_MODULE_DEBUG_VAR_MASK(ATH_MODULE_NAME) & (mask)) {                    \
+        A_LOGGER(mask, ATH_MODULE_NAME, ATH_PRINTX_ARG args);    \
+    }                                            \
+} while (0)
+#else
+    /* on non-debug builds, keep in error and warning messages in the driver, all other
+     * message tracing will get compiled out */
+#define AR_DEBUG_PRINTF(mask, args) \
+    if ((mask) & (ATH_DEBUG_ERR | ATH_DEBUG_WARN)) { A_PRINTF(ATH_PRINTX_ARG args); }
+
+#endif
+
+    /* compile specific macro to get the function name string */
+#define _A_FUNCNAME_  __func__
+
+
+#endif /* _DEBUG_LINUX_H_ */
diff --git a/drivers/net/ath6kl/os/linux/include/export_hci_transport.h b/drivers/net/ath6kl/os/linux/include/export_hci_transport.h
new file mode 100644
index 00000000000..c1506805a4d
--- /dev/null
+++ b/drivers/net/ath6kl/os/linux/include/export_hci_transport.h
@@ -0,0 +1,76 @@
+//------------------------------------------------------------------------------
+// Copyright (c) 2009-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// HCI bridge implementation
+//
+// Author(s): ="Atheros"
+//==============================================================================
+
+#include "hci_transport_api.h"
+#include "common_drv.h"
+
+extern HCI_TRANSPORT_HANDLE (*_HCI_TransportAttach)(void *HTCHandle, HCI_TRANSPORT_CONFIG_INFO *pInfo);
+extern void (*_HCI_TransportDetach)(HCI_TRANSPORT_HANDLE HciTrans);
+extern A_STATUS    (*_HCI_TransportAddReceivePkts)(HCI_TRANSPORT_HANDLE HciTrans, HTC_PACKET_QUEUE *pQueue);
+extern A_STATUS    (*_HCI_TransportSendPkt)(HCI_TRANSPORT_HANDLE HciTrans, HTC_PACKET *pPacket, A_BOOL Synchronous);
+extern void        (*_HCI_TransportStop)(HCI_TRANSPORT_HANDLE HciTrans);
+extern A_STATUS    (*_HCI_TransportStart)(HCI_TRANSPORT_HANDLE HciTrans);
+extern A_STATUS    (*_HCI_TransportEnableDisableAsyncRecv)(HCI_TRANSPORT_HANDLE HciTrans, A_BOOL Enable);
+extern A_STATUS    (*_HCI_TransportRecvHCIEventSync)(HCI_TRANSPORT_HANDLE HciTrans, 
+                                          HTC_PACKET           *pPacket,
+                                          int                  MaxPollMS);
+extern A_STATUS    (*_HCI_TransportSetBaudRate)(HCI_TRANSPORT_HANDLE HciTrans, A_UINT32 Baud);
+extern A_STATUS    (*_HCI_TransportEnablePowerMgmt)(HCI_TRANSPORT_HANDLE HciTrans, A_BOOL Enable);
+
+
+#define HCI_TransportAttach(HTCHandle, pInfo)   \
+            _HCI_TransportAttach((HTCHandle), (pInfo))
+#define HCI_TransportDetach(HciTrans)    \
+            _HCI_TransportDetach(HciTrans)
+#define HCI_TransportAddReceivePkts(HciTrans, pQueue)   \
+            _HCI_TransportAddReceivePkts((HciTrans), (pQueue))
+#define HCI_TransportSendPkt(HciTrans, pPacket, Synchronous)  \
+            _HCI_TransportSendPkt((HciTrans), (pPacket), (Synchronous))
+#define HCI_TransportStop(HciTrans)  \
+            _HCI_TransportStop((HciTrans))
+#define HCI_TransportStart(HciTrans)  \
+            _HCI_TransportStart((HciTrans))
+#define HCI_TransportEnableDisableAsyncRecv(HciTrans, Enable)   \
+            _HCI_TransportEnableDisableAsyncRecv((HciTrans), (Enable))
+#define HCI_TransportRecvHCIEventSync(HciTrans, pPacket, MaxPollMS)   \
+            _HCI_TransportRecvHCIEventSync((HciTrans), (pPacket), (MaxPollMS))
+#define HCI_TransportSetBaudRate(HciTrans, Baud)    \
+            _HCI_TransportSetBaudRate((HciTrans), (Baud))
+#define HCI_TransportEnablePowerMgmt(HciTrans, Enable)    \
+            _HCI_TransportEnablePowerMgmt((HciTrans), (Enable))
+
+
+extern A_STATUS ar6000_register_hci_transport(HCI_TRANSPORT_CALLBACKS *hciTransCallbacks);
+
+extern A_STATUS ar6000_get_hif_dev(HIF_DEVICE *device, void *config);
+
+extern A_STATUS ar6000_set_uart_config(HIF_DEVICE *hifDevice, A_UINT32 scale, A_UINT32 step);
+
+/* get core clock register settings
+ * data: 0 - 40/44MHz
+ *       1 - 80/88MHz
+ *       where (5G band/2.4G band)
+ * assume 2.4G band for now
+ */
+extern A_STATUS ar6000_get_core_clock_config(HIF_DEVICE *hifDevice, A_UINT32 *data);
diff --git a/drivers/net/ath6kl/os/linux/include/ieee80211_ioctl.h b/drivers/net/ath6kl/os/linux/include/ieee80211_ioctl.h
new file mode 100644
index 00000000000..769a4801431
--- /dev/null
+++ b/drivers/net/ath6kl/os/linux/include/ieee80211_ioctl.h
@@ -0,0 +1,179 @@
+//------------------------------------------------------------------------------
+// Copyright (c) 2004-2010 Atheros Communications Inc.
+// All rights reserved.
+//
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//
+// Author(s): ="Atheros"
+//------------------------------------------------------------------------------
+
+#ifndef _IEEE80211_IOCTL_H_
+#define _IEEE80211_IOCTL_H_
+
+#include <linux/version.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Extracted from the MADWIFI net80211/ieee80211_ioctl.h
+ */
+
+/*
+ * WPA/RSN get/set key request.  Specify the key/cipher
+ * type and whether the key is to be used for sending and/or
+ * receiving.  The key index should be set only when working
+ * with global keys (use IEEE80211_KEYIX_NONE for ``no index'').
+ * Otherwise a unicast/pairwise key is specified by the bssid
+ * (on a station) or mac address (on an ap).  They key length
+ * must include any MIC key data; otherwise it should be no
+ more than IEEE80211_KEYBUF_SIZE.
+ */
+struct ieee80211req_key {
+    u_int8_t    ik_type;    /* key/cipher type */
+    u_int8_t    ik_pad;
+    u_int16_t   ik_keyix;   /* key index */
+    u_int8_t    ik_keylen;  /* key length in bytes */
+    u_int8_t    ik_flags;
+#define IEEE80211_KEY_XMIT  0x01
+#define IEEE80211_KEY_RECV  0x02
+#define IEEE80211_KEY_DEFAULT   0x80    /* default xmit key */
+    u_int8_t    ik_macaddr[IEEE80211_ADDR_LEN];
+    u_int64_t   ik_keyrsc;  /* key receive sequence counter */
+    u_int64_t   ik_keytsc;  /* key transmit sequence counter */
+    u_int8_t    ik_keydata[IEEE80211_KEYBUF_SIZE+IEEE80211_MICBUF_SIZE];
+};
+/*
+ * Delete a key either by index or address.  Set the index
+ * to IEEE80211_KEYIX_NONE when deleting a unicast key.
+ */
+struct ieee80211req_del_key {
+    u_int8_t    idk_keyix;  /* key index */
+    u_int8_t    idk_macaddr[IEEE80211_ADDR_LEN];
+};
+/*
+ * MLME state manipulation request.  IEEE80211_MLME_ASSOC
+ * only makes sense when operating as a station.  The other
+ * requests can be used when operating as a station or an
+ * ap (to effect a station).
+ */
+struct ieee80211req_mlme {
+    u_int8_t    im_op;      /* operation to perform */
+#define IEEE80211_MLME_ASSOC        1   /* associate station */
+#define IEEE80211_MLME_DISASSOC     2   /* disassociate station */
+#define IEEE80211_MLME_DEAUTH       3   /* deauthenticate station */
+#define IEEE80211_MLME_AUTHORIZE    4   /* authorize station */
+#define IEEE80211_MLME_UNAUTHORIZE  5   /* unauthorize station */
+    u_int16_t   im_reason;  /* 802.11 reason code */
+    u_int8_t    im_macaddr[IEEE80211_ADDR_LEN];
+};
+
+struct ieee80211req_addpmkid {
+    u_int8_t    pi_bssid[IEEE80211_ADDR_LEN];
+    u_int8_t    pi_enable;
+    u_int8_t    pi_pmkid[16];
+};
+
+#define AUTH_ALG_OPEN_SYSTEM    0x01
+#define AUTH_ALG_SHARED_KEY 0x02
+#define AUTH_ALG_LEAP       0x04
+
+struct ieee80211req_authalg {
+   u_int8_t auth_alg;
+};  
+
+/* 
+ * Request to add an IE to a Management Frame
+ */
+enum{
+    IEEE80211_APPIE_FRAME_BEACON     = 0,
+    IEEE80211_APPIE_FRAME_PROBE_REQ  = 1,
+    IEEE80211_APPIE_FRAME_PROBE_RESP = 2,
+    IEEE80211_APPIE_FRAME_ASSOC_REQ  = 3,
+    IEEE80211_APPIE_FRAME_ASSOC_RESP = 4,
+    IEEE80211_APPIE_NUM_OF_FRAME     = 5
+};
+
+/*
+ * The Maximum length of the IE that can be added to a Management frame
+ */
+#define IEEE80211_APPIE_FRAME_MAX_LEN  200
+
+struct ieee80211req_getset_appiebuf {
+    u_int32_t app_frmtype; /* management frame type for which buffer is added */
+    u_int32_t app_buflen;  /*application supplied buffer length */
+    u_int8_t  app_buf[];
+};
+
+/* 
+ * The following definitions are used by an application to set filter
+ * for receiving management frames 
+ */
+enum {
+     IEEE80211_FILTER_TYPE_BEACON      =   0x1,
+     IEEE80211_FILTER_TYPE_PROBE_REQ   =   0x2,
+     IEEE80211_FILTER_TYPE_PROBE_RESP  =   0x4,
+     IEEE80211_FILTER_TYPE_ASSOC_REQ   =   0x8,
+     IEEE80211_FILTER_TYPE_ASSOC_RESP  =   0x10,
+     IEEE80211_FILTER_TYPE_AUTH        =   0x20,
+     IEEE80211_FILTER_TYPE_DEAUTH      =   0x40,
+     IEEE80211_FILTER_TYPE_DISASSOC    =   0x80,
+     IEEE80211_FILTER_TYPE_ALL         =   0xFF  /* used to check the valid filter bits */
+};
+
+struct ieee80211req_set_filter {
+      u_int32_t app_filterype; /* management frame filter type */
+};
+
+enum {
+    IEEE80211_PARAM_AUTHMODE = 3,   /* Authentication Mode */
+    IEEE80211_PARAM_MCASTCIPHER = 5,
+    IEEE80211_PARAM_MCASTKEYLEN = 6,    /* multicast key length */
+    IEEE80211_PARAM_UCASTCIPHER = 8,
+    IEEE80211_PARAM_UCASTKEYLEN = 9,    /* unicast key length */
+    IEEE80211_PARAM_WPA     = 10,   /* WPA mode (0,1,2) */
+    IEEE80211_PARAM_ROAMING     = 12,   /* roaming mode */
+    IEEE80211_PARAM_PRIVACY     = 13,   /* privacy invoked */
+    IEEE80211_PARAM_COUNTERMEASURES = 14,   /* WPA/TKIP countermeasures */
+    IEEE80211_PARAM_DROPUNENCRYPTED = 15,   /* discard unencrypted frames */
+    IEEE80211_PARAM_WAPI = 16,   /* WAPI policy from wapid */        
+};
+
+/*
+ * Values for IEEE80211_PARAM_WPA
+ */
+#define WPA_MODE_WPA1   1
+#define WPA_MODE_WPA2   2
+#define WPA_MODE_AUTO   3
+#define WPA_MODE_NONE   4
+
+struct ieee80211req_wpaie {
+    u_int8_t    wpa_macaddr[IEEE80211_ADDR_LEN];
+    u_int8_t    wpa_ie[IEEE80211_MAX_IE];
+    u_int8_t    rsn_ie[IEEE80211_MAX_IE];
+};
+
+#ifndef IW_ENCODE_ALG_PMK
+#define IW_ENCODE_ALG_PMK       4
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _IEEE80211_IOCTL_H_ */
diff --git a/drivers/net/ath6kl/os/linux/include/osapi_linux.h b/drivers/net/ath6kl/os/linux/include/osapi_linux.h
new file mode 100644
index 00000000000..dd3f81e4e5b
--- /dev/null
+++ b/drivers/net/ath6kl/os/linux/include/osapi_linux.h
@@ -0,0 +1,387 @@
+//------------------------------------------------------------------------------
+// This file contains the definitions of the basic atheros data types.
+// It is used to map the data types in atheros files to a platform specific
+// type.
+// Copyright (c) 2004-2010 Atheros Communications Inc.
+// All rights reserved.
+//
+//
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//
+// Author(s): ="Atheros"
+//------------------------------------------------------------------------------
+
+#ifndef _OSAPI_LINUX_H_
+#define _OSAPI_LINUX_H_
+
+#ifdef __KERNEL__
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/skbuff.h>
+#include <linux/netdevice.h>
+#include <linux/jiffies.h>
+#include <linux/timer.h>
+#include <linux/delay.h>
+#include <linux/wait.h>
+#include <linux/semaphore.h>
+#include <linux/cache.h>
+
+#ifdef __GNUC__
+#define __ATTRIB_PACK           __attribute__ ((packed))
+#define __ATTRIB_PRINTF         __attribute__ ((format (printf, 1, 2)))
+#define __ATTRIB_NORETURN       __attribute__ ((noreturn))
+#ifndef INLINE
+#define INLINE                  __inline__
+#endif
+#else /* Not GCC */
+#define __ATTRIB_PACK
+#define __ATTRIB_PRINTF
+#define __ATTRIB_NORETURN
+#ifndef INLINE
+#define INLINE                  __inline
+#endif
+#endif /* End __GNUC__ */
+
+#define PREPACK
+#define POSTPACK                __ATTRIB_PACK
+
+/*
+ * Endianes macros
+ */
+#define A_BE2CPU8(x)       ntohb(x)
+#define A_BE2CPU16(x)      ntohs(x)
+#define A_BE2CPU32(x)      ntohl(x)
+
+#define A_LE2CPU8(x)       (x)
+#define A_LE2CPU16(x)      (x)
+#define A_LE2CPU32(x)      (x)
+
+#define A_CPU2BE8(x)       htonb(x)
+#define A_CPU2BE16(x)      htons(x)
+#define A_CPU2BE32(x)      htonl(x)
+
+#define A_MEMCPY(dst, src, len)         memcpy((A_UINT8 *)(dst), (src), (len))
+#define A_MEMZERO(addr, len)            memset(addr, 0, len)
+#define A_MEMCMP(addr1, addr2, len)     memcmp((addr1), (addr2), (len))
+#define A_MALLOC(size)                  kmalloc((size), GFP_KERNEL)
+#define A_MALLOC_NOWAIT(size)           kmalloc((size), GFP_ATOMIC)
+#define A_FREE(addr)                    kfree(addr)
+
+#if defined(ANDROID_ENV) && defined(CONFIG_ANDROID_LOGGER)
+extern unsigned int enablelogcat;
+extern int android_logger_lv(void* module, int mask);
+enum logidx { LOG_MAIN_IDX = 0 };
+extern int logger_write(const enum logidx idx,
+                const unsigned char prio,
+                const char __kernel * const tag,
+                const char __kernel * const fmt,
+                ...);
+#define A_ANDROID_PRINTF(mask, module, tags, args...) do {  \
+    if (enablelogcat) \
+        logger_write(LOG_MAIN_IDX, android_logger_lv(module, mask), tags, args); \
+    else \
+        printk(KERN_ALERT args); \
+} while (0)
+#ifdef DEBUG
+#define A_LOGGER_MODULE_NAME(x) #x
+#define A_LOGGER(mask, mod, args...) \
+    A_ANDROID_PRINTF(mask, &GET_ATH_MODULE_DEBUG_VAR_NAME(mod), "ar6k_" A_LOGGER_MODULE_NAME(mod), args);
+#endif
+#define A_PRINTF(args...) A_ANDROID_PRINTF(ATH_DEBUG_INFO, NULL, "ar6k_driver", args)
+#else
+#define A_LOGGER(mask, mod, args...)    printk(KERN_ALERT args)
+#define A_PRINTF(args...)               printk(KERN_ALERT args)
+#endif /* ANDROID */
+#define A_PRINTF_LOG(args...)           printk(args)
+#define A_SPRINTF(buf, args...)			sprintf (buf, args)
+
+/* Mutual Exclusion */
+typedef spinlock_t                      A_MUTEX_T;
+#define A_MUTEX_INIT(mutex)             spin_lock_init(mutex)
+#define A_MUTEX_LOCK(mutex)             spin_lock_bh(mutex)
+#define A_MUTEX_UNLOCK(mutex)           spin_unlock_bh(mutex)
+#define A_IS_MUTEX_VALID(mutex)         TRUE  /* okay to return true, since A_MUTEX_DELETE does nothing */
+#define A_MUTEX_DELETE(mutex)           /* spin locks are not kernel resources so nothing to free.. */
+
+/* Get current time in ms adding a constant offset (in ms) */
+#define A_GET_MS(offset)    \
+	(jiffies + ((offset) / 1000) * HZ)
+
+/*
+ * Timer Functions
+ */
+#define A_MDELAY(msecs)                 mdelay(msecs)
+typedef struct timer_list               A_TIMER;
+
+#define A_INIT_TIMER(pTimer, pFunction, pArg) do {              \
+    init_timer(pTimer);                                         \
+    (pTimer)->function = (pFunction);                           \
+    (pTimer)->data   = (unsigned long)(pArg);                   \
+} while (0)
+
+/*
+ * Start a Timer that elapses after 'periodMSec' milli-seconds
+ * Support is provided for a one-shot timer. The 'repeatFlag' is
+ * ignored.
+ */
+#define A_TIMEOUT_MS(pTimer, periodMSec, repeatFlag) do {                   \
+    if (repeatFlag) {                                                       \
+        printk("\n" __FILE__ ":%d: Timer Repeat requested\n",__LINE__);     \
+        panic("Timer Repeat");                                              \
+    }                                                                       \
+    mod_timer((pTimer), jiffies + HZ * (periodMSec) / 1000);                \
+} while (0)
+
+/*
+ * Cancel the Timer.
+ */
+#define A_UNTIMEOUT(pTimer) do {                                \
+    del_timer((pTimer));                                        \
+} while (0)
+
+#define A_DELETE_TIMER(pTimer) do {                             \
+} while (0)
+
+/*
+ * Wait Queue related functions
+ */
+typedef wait_queue_head_t               A_WAITQUEUE_HEAD;
+#define A_INIT_WAITQUEUE_HEAD(head)     init_waitqueue_head(head)
+#ifndef wait_event_interruptible_timeout
+#define __wait_event_interruptible_timeout(wq, condition, ret)          \
+do {                                                                    \
+        wait_queue_t __wait;                                            \
+        init_waitqueue_entry(&__wait, current);                         \
+                                                                        \
+        add_wait_queue(&wq, &__wait);                                   \
+        for (;;) {                                                      \
+                set_current_state(TASK_INTERRUPTIBLE);                  \
+                if (condition)                                          \
+                        break;                                          \
+                if (!signal_pending(current)) {                         \
+                        ret = schedule_timeout(ret);                    \
+                        if (!ret)                                       \
+                                break;                                  \
+                        continue;                                       \
+                }                                                       \
+                ret = -ERESTARTSYS;                                     \
+                break;                                                  \
+        }                                                               \
+        current->state = TASK_RUNNING;                                  \
+        remove_wait_queue(&wq, &__wait);                                \
+} while (0)
+
+#define wait_event_interruptible_timeout(wq, condition, timeout)        \
+({                                                                      \
+        long __ret = timeout;                                           \
+        if (!(condition))                                               \
+                __wait_event_interruptible_timeout(wq, condition, __ret); \
+        __ret;                                                          \
+})
+#endif /* wait_event_interruptible_timeout */
+
+#define A_WAIT_EVENT_INTERRUPTIBLE_TIMEOUT(head, condition, timeout) do { \
+    wait_event_interruptible_timeout(head, condition, timeout); \
+} while (0)
+
+#define A_WAKE_UP(head)                 wake_up(head)
+
+#ifdef DEBUG
+extern unsigned int panic_on_assert;
+#define A_ASSERT(expr)  \
+    if (!(expr)) {   \
+        printk(KERN_ALERT"Debug Assert Caught, File %s, Line: %d, Test:%s \n",__FILE__, __LINE__,#expr); \
+        if (panic_on_assert) panic(#expr);                                                               \
+    }
+#else
+#define A_ASSERT(expr)
+#endif /* DEBUG */
+
+#ifdef ANDROID_ENV
+struct firmware;
+int android_request_firmware(const struct firmware **firmware_p, const char *filename,
+                     struct device *device);
+void android_release_firmware(const struct firmware *firmware);
+#define A_REQUEST_FIRMWARE(_ppf, _pfile, _dev) android_request_firmware(_ppf, _pfile, _dev)
+#define A_RELEASE_FIRMWARE(_pf) android_release_firmware(_pf)
+#else
+#define A_REQUEST_FIRMWARE(_ppf, _pfile, _dev) request_firmware(_ppf, _pfile, _dev)
+#define A_RELEASE_FIRMWARE(_pf) release_firmware(_pf)
+#endif
+
+/*
+ * Initialization of the network buffer subsystem
+ */
+#define A_NETBUF_INIT()
+
+/*
+ * Network buffer queue support
+ */
+typedef struct sk_buff_head A_NETBUF_QUEUE_T;
+
+#define A_NETBUF_QUEUE_INIT(q)  \
+    a_netbuf_queue_init(q)
+
+#define A_NETBUF_ENQUEUE(q, pkt) \
+    a_netbuf_enqueue((q), (pkt))
+#define A_NETBUF_PREQUEUE(q, pkt) \
+    a_netbuf_prequeue((q), (pkt))
+#define A_NETBUF_DEQUEUE(q) \
+    (a_netbuf_dequeue(q))
+#define A_NETBUF_QUEUE_SIZE(q)  \
+    a_netbuf_queue_size(q)
+#define A_NETBUF_QUEUE_EMPTY(q) \
+    a_netbuf_queue_empty(q)
+
+/*
+ * Network buffer support
+ */
+#define A_NETBUF_ALLOC(size) \
+    a_netbuf_alloc(size)
+#define A_NETBUF_ALLOC_RAW(size) \
+    a_netbuf_alloc_raw(size)
+#define A_NETBUF_FREE(bufPtr) \
+    a_netbuf_free(bufPtr)
+#define A_NETBUF_DATA(bufPtr) \
+    a_netbuf_to_data(bufPtr)
+#define A_NETBUF_LEN(bufPtr) \
+    a_netbuf_to_len(bufPtr)
+#define A_NETBUF_PUSH(bufPtr, len) \
+    a_netbuf_push(bufPtr, len)
+#define A_NETBUF_PUT(bufPtr, len) \
+    a_netbuf_put(bufPtr, len)
+#define A_NETBUF_TRIM(bufPtr,len) \
+    a_netbuf_trim(bufPtr, len)
+#define A_NETBUF_PULL(bufPtr, len) \
+    a_netbuf_pull(bufPtr, len)
+#define A_NETBUF_HEADROOM(bufPtr)\
+    a_netbuf_headroom(bufPtr)
+#define A_NETBUF_SETLEN(bufPtr,len) \
+    a_netbuf_setlen(bufPtr, len)
+
+/* Add data to end of a buffer  */
+#define A_NETBUF_PUT_DATA(bufPtr, srcPtr,  len) \
+    a_netbuf_put_data(bufPtr, srcPtr, len)
+
+/* Add data to start of the  buffer */
+#define A_NETBUF_PUSH_DATA(bufPtr, srcPtr,  len) \
+    a_netbuf_push_data(bufPtr, srcPtr, len)
+
+/* Remove data at start of the buffer */
+#define A_NETBUF_PULL_DATA(bufPtr, dstPtr, len) \
+    a_netbuf_pull_data(bufPtr, dstPtr, len)
+
+/* Remove data from the end of the buffer */
+#define A_NETBUF_TRIM_DATA(bufPtr, dstPtr, len) \
+    a_netbuf_trim_data(bufPtr, dstPtr, len)
+
+/* View data as "size" contiguous bytes of type "t" */
+#define A_NETBUF_VIEW_DATA(bufPtr, t, size) \
+    (t )( ((struct skbuf *)(bufPtr))->data)
+
+/* return the beginning of the headroom for the buffer */
+#define A_NETBUF_HEAD(bufPtr) \
+        ((((struct sk_buff *)(bufPtr))->head))
+
+/*
+ * OS specific network buffer access routines
+ */
+void *a_netbuf_alloc(int size);
+void *a_netbuf_alloc_raw(int size);
+void a_netbuf_free(void *bufPtr);
+void *a_netbuf_to_data(void *bufPtr);
+A_UINT32 a_netbuf_to_len(void *bufPtr);
+A_STATUS a_netbuf_push(void *bufPtr, A_INT32 len);
+A_STATUS a_netbuf_push_data(void *bufPtr, char *srcPtr, A_INT32 len);
+A_STATUS a_netbuf_put(void *bufPtr, A_INT32 len);
+A_STATUS a_netbuf_put_data(void *bufPtr, char *srcPtr, A_INT32 len);
+A_STATUS a_netbuf_pull(void *bufPtr, A_INT32 len);
+A_STATUS a_netbuf_pull_data(void *bufPtr, char *dstPtr, A_INT32 len);
+A_STATUS a_netbuf_trim(void *bufPtr, A_INT32 len);
+A_STATUS a_netbuf_trim_data(void *bufPtr, char *dstPtr, A_INT32 len);
+A_STATUS a_netbuf_setlen(void *bufPtr, A_INT32 len);
+A_INT32 a_netbuf_headroom(void *bufPtr);
+void a_netbuf_enqueue(A_NETBUF_QUEUE_T *q, void *pkt);
+void a_netbuf_prequeue(A_NETBUF_QUEUE_T *q, void *pkt);
+void *a_netbuf_dequeue(A_NETBUF_QUEUE_T *q);
+int a_netbuf_queue_size(A_NETBUF_QUEUE_T *q);
+int a_netbuf_queue_empty(A_NETBUF_QUEUE_T *q);
+int a_netbuf_queue_empty(A_NETBUF_QUEUE_T *q);
+void a_netbuf_queue_init(A_NETBUF_QUEUE_T *q);
+
+/*
+ * Kernel v.s User space functions
+ */
+A_UINT32 a_copy_to_user(void *to, const void *from, A_UINT32 n);
+A_UINT32 a_copy_from_user(void *to, const void *from, A_UINT32 n);
+
+/* In linux, WLAN Rx and Tx run in different contexts, so no need to check
+ * for any commands/data queued for WLAN */
+#define A_CHECK_DRV_TX()
+
+#define A_GET_CACHE_LINE_BYTES()    L1_CACHE_BYTES
+
+#define A_CACHE_LINE_PAD            128
+
+static inline void *A_ALIGN_TO_CACHE_LINE(void *ptr) {
+    return (void *)L1_CACHE_ALIGN((unsigned long)ptr);
+}
+
+#else /* __KERNEL__ */
+
+#ifdef __GNUC__
+#define __ATTRIB_PACK           __attribute__ ((packed))
+#define __ATTRIB_PRINTF         __attribute__ ((format (printf, 1, 2)))
+#define __ATTRIB_NORETURN       __attribute__ ((noreturn))
+#ifndef INLINE
+#define INLINE                  __inline__
+#endif
+#else /* Not GCC */
+#define __ATTRIB_PACK
+#define __ATTRIB_PRINTF
+#define __ATTRIB_NORETURN
+#ifndef INLINE
+#define INLINE                  __inline
+#endif
+#endif /* End __GNUC__ */
+
+#define PREPACK
+#define POSTPACK                __ATTRIB_PACK
+
+#define A_MEMCPY(dst, src, len)         memcpy((dst), (src), (len))
+#define A_MEMZERO(addr, len)            memset((addr), 0, (len))
+#define A_MEMCMP(addr1, addr2, len)     memcmp((addr1), (addr2), (len))
+#define A_MALLOC(size)                  malloc(size)
+#define A_FREE(addr)                    free(addr)
+
+#ifdef ANDROID
+#ifndef err
+#include <errno.h>
+#define err(_s, args...) do { \
+    fprintf(stderr, "%s: line %d ", __FILE__, __LINE__); \
+    fprintf(stderr, args); fprintf(stderr, ": %d\n", errno); \
+    exit(_s); } while (0)
+#endif
+#else
+#include <err.h>
+#endif
+
+#endif /* __KERNEL__ */
+
+#endif /* _OSAPI_LINUX_H_ */
diff --git a/drivers/net/ath6kl/os/linux/include/wlan_config.h b/drivers/net/ath6kl/os/linux/include/wlan_config.h
new file mode 100644
index 00000000000..f7d04872222
--- /dev/null
+++ b/drivers/net/ath6kl/os/linux/include/wlan_config.h
@@ -0,0 +1,111 @@
+//------------------------------------------------------------------------------
+// Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// This file contains the tunable configuration items for the WLAN module
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _HOST_WLAN_CONFIG_H_
+#define _HOST_WLAN_CONFIG_H_
+
+/* Include definitions here that can be used to tune the WLAN module behavior.
+ * Different customers can tune the behavior as per their needs, here. 
+ */
+
+/* This configuration item when defined will consider the barker preamble 
+ * mentioned in the ERP IE of the beacons from the AP to determine the short 
+ * preamble support sent in the (Re)Assoc request frames.
+ */
+#define WLAN_CONFIG_DONOT_IGNORE_BARKER_IN_ERP 0
+
+/* This config item when defined will not send the power module state transition
+ * failure events that happen during scan, to the host. 
+ */
+#define WLAN_CONFIG_IGNORE_POWER_SAVE_FAIL_EVENT_DURING_SCAN 0
+
+/*
+ * This configuration item enable/disable keepalive support.
+ * Keepalive support: In the absence of any data traffic to AP, null 
+ * frames will be sent to the AP at periodic interval, to keep the association
+ * active. This configuration item defines the periodic interval.
+ * Use value of zero to disable keepalive support
+ * Default: 60 seconds
+ */
+#define WLAN_CONFIG_KEEP_ALIVE_INTERVAL 60 
+
+/*
+ * This configuration item sets the value of disconnect timeout
+ * Firmware delays sending the disconnec event to the host for this
+ * timeout after is gets disconnected from the current AP.
+ * If the firmware successly roams within the disconnect timeout
+ * it sends a new connect event
+ */
+#ifdef ANDROID_ENV
+#define WLAN_CONFIG_DISCONNECT_TIMEOUT 3
+#else
+#define WLAN_CONFIG_DISCONNECT_TIMEOUT 10
+#endif /* ANDROID_ENV */ 
+
+/*
+ * This configuration item disables 11n support. 
+ * 0 - Enable
+ * 1 - Disable
+ */
+#define WLAN_CONFIG_DISABLE_11N         0
+
+/*
+ * This configuration item enable BT clock sharing support
+ * 1 - Enable
+ * 0 - Disable (Default)
+ */
+#define WLAN_CONFIG_BT_SHARING          0
+
+/*
+ * This configuration item sets WIFI OFF policy
+ * 0 - CUT_POWER
+ * 1 - DEEP_SLEEP (Default)
+ */
+#define WLAN_CONFIG_WLAN_OFF                1
+
+/*
+ * This configuration item sets suspend policy
+ * 0 - CUT_POWER (Default)
+ * 1 - DEEP_SLEEP
+ * 2 - WoW
+ * 3 - CUT_POWER if BT OFF (clock sharing designs only)
+ */
+#define WLAN_CONFIG_PM_SUSPEND              0
+
+/*
+ * This configuration item sets suspend policy to use if PM_SUSPEND is
+ * set to WoW and device is not connected at the time of suspend
+ * 0 - CUT_POWER (Default)
+ * 1 - DEEP_SLEEP
+ * 2 - WoW
+ * 3 - CUT_POWER if BT OFF (clock sharing designs only)
+ */
+#define WLAN_CONFIG_PM_WOW2                 0
+
+/*
+ * Platform specific function to power ON/OFF AR6000 
+ * and enable/disable SDIO card detection
+ */
+#define plat_setup_power(on, detect)
+
+#endif /* _HOST_WLAN_CONFIG_H_ */
diff --git a/drivers/net/ath6kl/os/linux/include/wmi_filter_linux.h b/drivers/net/ath6kl/os/linux/include/wmi_filter_linux.h
new file mode 100644
index 00000000000..77e4ec6fea3
--- /dev/null
+++ b/drivers/net/ath6kl/os/linux/include/wmi_filter_linux.h
@@ -0,0 +1,293 @@
+//------------------------------------------------------------------------------
+// Copyright (c) 2004-2010 Atheros Communications Inc.
+// All rights reserved.
+//
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//
+// Author(s): ="Atheros"
+//------------------------------------------------------------------------------
+
+#ifndef _WMI_FILTER_LINUX_H_
+#define  _WMI_FILTER_LINUX_H_
+
+/*
+ * sioctl_filter - Standard ioctl
+ * pioctl_filter - Priv ioctl
+ * xioctl_filter - eXtended ioctl
+ *
+ * ---- Possible values for the WMI filter ---------------
+ * (0) - Block this cmd always (or) not implemented
+ * (INFRA_NETWORK) - Allow this cmd only in STA mode
+ * (ADHOC_NETWORK) - Allow this cmd only in IBSS mode
+ * (AP_NETWORK) -    Allow this cmd only in AP mode
+ * (INFRA_NETWORK | ADHOC_NETWORK) - Block this cmd in AP mode
+ * (ADHOC_NETWORK | AP_NETWORK) -    Block this cmd in STA mode
+ * (INFRA_NETWORK | AP_NETWORK) -    Block this cmd in IBSS mode
+ * (INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK)- allow only when mode is set
+ * (0xFF) - Allow this cmd always irrespective of mode
+ */
+
+A_UINT8 sioctl_filter[] = {
+(AP_NETWORK),                                   /* SIOCSIWCOMMIT   0x8B00   */
+(0xFF),                                         /* SIOCGIWNAME     0x8B01   */
+(0),                                            /* SIOCSIWNWID     0x8B02   */
+(0),                                            /* SIOCGIWNWID     0x8B03   */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK),   /* SIOCSIWFREQ     0x8B04   */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK),   /* SIOCGIWFREQ     0x8B05   */
+(0xFF),                                         /* SIOCSIWMODE     0x8B06   */
+(0xFF),                                         /* SIOCGIWMODE     0x8B07   */
+(0),                                            /* SIOCSIWSENS     0x8B08   */
+(0),                                            /* SIOCGIWSENS     0x8B09   */
+(0),                                            /* SIOCSIWRANGE    0x8B0A   */
+(0xFF),                                         /* SIOCGIWRANGE    0x8B0B   */
+(0),                                            /* SIOCSIWPRIV     0x8B0C   */
+(0),                                            /* SIOCGIWPRIV     0x8B0D   */
+(0),                                            /* SIOCSIWSTATS    0x8B0E   */
+(0),                                            /* SIOCGIWSTATS    0x8B0F   */
+(0),                                            /* SIOCSIWSPY      0x8B10   */
+(0),                                            /* SIOCGIWSPY      0x8B11   */
+(0),                                            /* SIOCSIWTHRSPY   0x8B12   */
+(0),                                            /* SIOCGIWTHRSPY   0x8B13   */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK),   /* SIOCSIWAP       0x8B14   */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK),   /* SIOCGIWAP       0x8B15   */
+#if (WIRELESS_EXT >= 18)
+(INFRA_NETWORK | ADHOC_NETWORK),                /* SIOCSIWMLME     0X8B16   */
+#else
+(0),                                            /* Dummy           0        */
+#endif /* WIRELESS_EXT */
+(0),                                            /* SIOCGIWAPLIST   0x8B17   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* SIOCSIWSCAN     0x8B18   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* SIOCGIWSCAN     0x8B19   */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK),   /* SIOCSIWESSID    0x8B1A   */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK),   /* SIOCGIWESSID    0x8B1B   */
+(0),                                            /* SIOCSIWNICKN    0x8B1C   */
+(0),                                            /* SIOCGIWNICKN    0x8B1D   */
+(0),                                            /* Dummy           0        */
+(0),                                            /* Dummy           0        */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK),   /* SIOCSIWRATE     0x8B20   */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK),   /* SIOCGIWRATE     0x8B21   */
+(0),                                            /* SIOCSIWRTS      0x8B22   */
+(0),                                            /* SIOCGIWRTS      0x8B23   */
+(0),                                            /* SIOCSIWFRAG     0x8B24   */
+(0),                                            /* SIOCGIWFRAG     0x8B25   */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK),   /* SIOCSIWTXPOW    0x8B26   */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK),   /* SIOCGIWTXPOW    0x8B27   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* SIOCSIWRETRY    0x8B28   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* SIOCGIWRETRY    0x8B29   */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK),   /* SIOCSIWENCODE   0x8B2A   */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK),   /* SIOCGIWENCODE   0x8B2B   */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK),   /* SIOCSIWPOWER    0x8B2C   */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK),   /* SIOCGIWPOWER    0x8B2D   */
+};
+
+
+
+A_UINT8 pioctl_filter[] = {
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK),   /* IEEE80211_IOCTL_SETPARAM             (SIOCIWFIRSTPRIV+0)     */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK),   /* IEEE80211_IOCTL_SETKEY               (SIOCIWFIRSTPRIV+1)     */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK),   /* IEEE80211_IOCTL_DELKEY               (SIOCIWFIRSTPRIV+2)     */
+(AP_NETWORK),                                   /* IEEE80211_IOCTL_SETMLME              (SIOCIWFIRSTPRIV+3)     */
+(INFRA_NETWORK),                                /* IEEE80211_IOCTL_ADDPMKID             (SIOCIWFIRSTPRIV+4)     */
+(0),                                            /* IEEE80211_IOCTL_SETOPTIE             (SIOCIWFIRSTPRIV+5)     */
+(0),                                            /*                                      (SIOCIWFIRSTPRIV+6)     */
+(0),                                            /*                                      (SIOCIWFIRSTPRIV+7)     */
+(0),                                            /*                                      (SIOCIWFIRSTPRIV+8)     */
+(0),                                            /*                                      (SIOCIWFIRSTPRIV+9)     */
+(0),                                            /* IEEE80211_IOCTL_LASTONE              (SIOCIWFIRSTPRIV+10)    */
+(0xFF),                                         /* AR6000_IOCTL_WMI_GETREV              (SIOCIWFIRSTPRIV+11)    */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK),   /* AR6000_IOCTL_WMI_SETPWR              (SIOCIWFIRSTPRIV+12)    */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_IOCTL_WMI_SETSCAN             (SIOCIWFIRSTPRIV+13)    */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_IOCTL_WMI_SETLISTENINT        (SIOCIWFIRSTPRIV+14)    */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_IOCTL_WMI_SETBSSFILTER        (SIOCIWFIRSTPRIV+15)    */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK),   /* AR6000_IOCTL_WMI_SET_CHANNELPARAMS   (SIOCIWFIRSTPRIV+16)    */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_IOCTL_WMI_SET_PROBEDSSID      (SIOCIWFIRSTPRIV+17)    */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_IOCTL_WMI_SET_PMPARAMS        (SIOCIWFIRSTPRIV+18)    */
+(INFRA_NETWORK),                                /* AR6000_IOCTL_WMI_SET_BADAP           (SIOCIWFIRSTPRIV+19)    */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_IOCTL_WMI_GET_QOS_QUEUE       (SIOCIWFIRSTPRIV+20)    */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_IOCTL_WMI_CREATE_QOS          (SIOCIWFIRSTPRIV+21)    */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_IOCTL_WMI_DELETE_QOS          (SIOCIWFIRSTPRIV+22)    */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_IOCTL_WMI_SET_SNRTHRESHOLD    (SIOCIWFIRSTPRIV+23)    */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_IOCTL_WMI_SET_ERROR_REPORT_BITMASK (SIOCIWFIRSTPRIV+24)*/
+(0xFF),                                         /* AR6000_IOCTL_WMI_GET_TARGET_STATS    (SIOCIWFIRSTPRIV+25)    */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_IOCTL_WMI_SET_ASSOC_INFO      (SIOCIWFIRSTPRIV+26)    */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_IOCTL_WMI_SET_ACCESS_PARAMS   (SIOCIWFIRSTPRIV+27)    */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_IOCTL_WMI_SET_BMISS_TIME      (SIOCIWFIRSTPRIV+28)    */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_IOCTL_WMI_SET_DISC_TIMEOUT    (SIOCIWFIRSTPRIV+29)    */
+(ADHOC_NETWORK),                                /* AR6000_IOCTL_WMI_SET_IBSS_PM_CAPS    (SIOCIWFIRSTPRIV+30)    */
+};
+
+
+
+A_UINT8 xioctl_filter[] = {
+(0xFF),                                         /* Dummy                                           0    */
+(0xFF),                                         /* AR6000_XIOCTL_BMI_DONE                          1    */
+(0xFF),                                         /* AR6000_XIOCTL_BMI_READ_MEMORY                   2    */
+(0xFF),                                         /* AR6000_XIOCTL_BMI_WRITE_MEMORY                  3    */
+(0xFF),                                         /* AR6000_XIOCTL_BMI_EXECUTE                       4    */
+(0xFF),                                         /* AR6000_XIOCTL_BMI_SET_APP_START                 5    */
+(0xFF),                                         /* AR6000_XIOCTL_BMI_READ_SOC_REGISTER             6    */
+(0xFF),                                         /* AR6000_XIOCTL_BMI_WRITE_SOC_REGISTER            7    */
+(0xFF),                                         /* AR6000_XIOCTL_BMI_TEST                          8    */
+(0xFF),                                         /* AR6000_XIOCTL_UNUSED9                           9    */
+(0xFF),                                         /* AR6000_XIOCTL_UNUSED10                          10   */
+(0xFF),                                         /* AR6000_XIOCTL_UNUSED11                          11   */
+(0xFF),                                         /* AR6000_XIOCTL_FORCE_TARGET_RESET                12   */
+(0xFF),                                         /* AR6000_XIOCTL_HTC_RAW_OPEN                      13   */
+(0xFF),                                         /* AR6000_XIOCTL_HTC_RAW_CLOSE                     14   */
+(0xFF),                                         /* AR6000_XIOCTL_HTC_RAW_READ                      15   */
+(0xFF),                                         /* AR6000_XIOCTL_HTC_RAW_WRITE                     16   */
+(0xFF),                                         /* AR6000_XIOCTL_CHECK_TARGET_READY                17   */
+(0xFF),                                         /* AR6000_XIOCTL_GPIO_OUTPUT_SET                   18   */
+(0xFF),                                         /* AR6000_XIOCTL_GPIO_INPUT_GET                    19   */
+(0xFF),                                         /* AR6000_XIOCTL_GPIO_REGISTER_SET                 20   */
+(0xFF),                                         /* AR6000_XIOCTL_GPIO_REGISTER_GET                 21   */
+(0xFF),                                         /* AR6000_XIOCTL_GPIO_INTR_ACK                     22   */
+(0xFF),                                         /* AR6000_XIOCTL_GPIO_INTR_WAIT                    23   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_SET_ADHOC_BSSID                   24   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_SET_OPT_MODE                      25   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_OPT_SEND_FRAME                    26   */
+(ADHOC_NETWORK | AP_NETWORK),                   /* AR6000_XIOCTL_SET_BEACON_INTVAL                 27   */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK),   /* IEEE80211_IOCTL_SETAUTHALG                      28   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_SET_VOICE_PKT_SIZE                29   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_SET_MAX_SP                        30   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_WMI_GET_ROAM_TBL                  31   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_WMI_SET_ROAM_CTRL                 32   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTRL_WMI_SET_POWERSAVE_TIMERS         33   */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK),   /* AR6000_XIOCTRL_WMI_GET_POWER_MODE               34   */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK),   /* AR6000_XIOCTRL_WMI_SET_WLAN_STATE               35   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_WMI_GET_ROAM_DATA                 36   */
+(0xFF),                                         /* AR6000_XIOCTL_WMI_SETRETRYLIMITS                37   */
+(0xFF),                                         /* AR6000_XIOCTL_TCMD_CONT_TX                      38   */
+(0xFF),                                         /* AR6000_XIOCTL_TCMD_CONT_RX                      39   */
+(0xFF),                                         /* AR6000_XIOCTL_TCMD_PM                           40   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_WMI_STARTSCAN                     41   */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK),   /* AR6000_XIOCTL_WMI_SETFIXRATES                   42   */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK),   /* AR6000_XIOCTL_WMI_GETFIXRATES                   43   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_WMI_SET_RSSITHRESHOLD             44   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_WMI_CLR_RSSISNR                   45   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_WMI_SET_LQTHRESHOLD               46   */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK),   /* AR6000_XIOCTL_WMI_SET_RTS                       47   */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK),   /* AR6000_XIOCTL_WMI_SET_LPREAMBLE                 48   */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK),   /* AR6000_XIOCTL_WMI_SET_AUTHMODE                  49   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_WMI_SET_REASSOCMODE               50   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_WMI_SET_WMM                       51   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_WMI_SET_HB_CHALLENGE_RESP_PARAMS  52   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_WMI_GET_HB_CHALLENGE_RESP         53   */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK),   /* AR6000_XIOCTL_WMI_GET_RD                        54   */
+(0xFF),                                         /* AR6000_XIOCTL_DIAG_READ                         55   */
+(0xFF),                                         /* AR6000_XIOCTL_DIAG_WRITE                        56   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_WMI_SET_TXOP                      57   */
+(INFRA_NETWORK),                                /* AR6000_XIOCTL_USER_SETKEYS                      58   */
+(INFRA_NETWORK),                                /* AR6000_XIOCTL_WMI_SET_KEEPALIVE                 59   */
+(INFRA_NETWORK),                                /* AR6000_XIOCTL_WMI_GET_KEEPALIVE                 60   */
+(0xFF),                                         /* AR6000_XIOCTL_BMI_ROMPATCH_INSTALL              61   */
+(0xFF),                                         /* AR6000_XIOCTL_BMI_ROMPATCH_UNINSTALL            62   */
+(0xFF),                                         /* AR6000_XIOCTL_BMI_ROMPATCH_ACTIVATE             63   */
+(0xFF),                                         /* AR6000_XIOCTL_BMI_ROMPATCH_DEACTIVATE           64   */
+(0xFF),                                         /* AR6000_XIOCTL_WMI_SET_APPIE                     65   */
+(0xFF),                                         /* AR6000_XIOCTL_WMI_SET_MGMT_FRM_RX_FILTER        66   */
+(0xFF),                                         /* AR6000_XIOCTL_DBGLOG_CFG_MODULE                 67   */
+(0xFF),                                         /* AR6000_XIOCTL_DBGLOG_GET_DEBUG_LOGS             68   */
+(0xFF),                                         /* Dummy                                           69   */
+(0xFF),                                         /* AR6000_XIOCTL_WMI_SET_WSC_STATUS                70   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_WMI_SET_BT_STATUS                 71   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_WMI_SET_BT_PARAMS                 72   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_WMI_SET_HOST_SLEEP_MODE           73   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_WMI_SET_WOW_MODE                  74   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_WMI_GET_WOW_LIST                  75   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_WMI_ADD_WOW_PATTERN               76   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_WMI_DEL_WOW_PATTERN               77   */
+(0xFF),                                         /* AR6000_XIOCTL_TARGET_INFO                       78   */
+(0xFF),                                         /* AR6000_XIOCTL_DUMP_HTC_CREDIT_STATE             79   */
+(0xFF),                                         /* AR6000_XIOCTL_TRAFFIC_ACTIVITY_CHANGE           80   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_WMI_SET_CONNECT_CTRL_FLAGS        81   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_WMI_SET_AKMP_PARAMS               82   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_WMI_GET_PMKID_LIST                83   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_WMI_SET_PMKID_LIST                84   */
+(0xFF),                                         /* Dummy                                           85   */
+(0xFF),                                         /* Dummy                                           86   */
+(0xFF),                                         /* Dummy                                           87   */
+(0xFF),                                         /* Dummy                                           88   */
+(0xFF),                                         /* Dummy                                           89   */
+(0xFF),                                         /* AR6000_XIOCTL_UNUSED90                          90   */
+(0xFF),                                         /* AR6000_XIOCTL_BMI_LZ_STREAM_START               91   */
+(0xFF),                                         /* AR6000_XIOCTL_BMI_LZ_DATA                       92   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_PROF_CFG                          93   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_PROF_ADDR_SET                     94   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_PROF_START                        95   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_PROF_STOP                         96   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_PROF_COUNT_GET                    97   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_WMI_ABORT_SCAN                    98   */
+(AP_NETWORK),                                   /* AR6000_XIOCTL_AP_GET_STA_LIST                   99   */
+(AP_NETWORK),                                   /* AR6000_XIOCTL_AP_HIDDEN_SSID                    100  */
+(AP_NETWORK),                                   /* AR6000_XIOCTL_AP_SET_NUM_STA                    101  */
+(AP_NETWORK),                                   /* AR6000_XIOCTL_AP_SET_ACL_MAC                    102  */
+(AP_NETWORK),                                   /* AR6000_XIOCTL_AP_GET_ACL_LIST                   103  */
+(AP_NETWORK),                                   /* AR6000_XIOCTL_AP_COMMIT_CONFIG                  104  */
+(AP_NETWORK),                                   /* IEEE80211_IOCTL_GETWPAIE                        105  */
+(AP_NETWORK),                                   /* AR6000_XIOCTL_AP_CONN_INACT_TIME                106  */
+(AP_NETWORK),                                   /* AR6000_XIOCTL_AP_PROT_SCAN_TIME                 107  */
+(AP_NETWORK),                                   /* AR6000_XIOCTL_WMI_SET_COUNTRY                   108  */
+(AP_NETWORK),                                   /* AR6000_XIOCTL_AP_SET_DTIM                       109  */
+(0xFF),                                         /* AR6000_XIOCTL_WMI_TARGET_EVENT_REPORT           110  */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_SET_IP                            111  */
+(AP_NETWORK),                                   /* AR6000_XIOCTL_AP_SET_ACL_POLICY                 112  */
+(AP_NETWORK),                                   /* AR6000_XIOCTL_AP_INTRA_BSS_COMM                 113  */
+(0xFF),                                         /* AR6000_XIOCTL_DUMP_MODULE_DEBUG_INFO            114  */
+(0xFF),                                         /* AR6000_XIOCTL_MODULE_DEBUG_SET_MASK             115  */
+(0xFF),                                         /* AR6000_XIOCTL_MODULE_DEBUG_GET_MASK             116  */
+(0xFF),                                         /* AR6000_XIOCTL_DUMP_RCV_AGGR_STATS               117  */
+(0xFF),                                         /* AR6000_XIOCTL_SET_HT_CAP                        118  */
+(0xFF),                                         /* AR6000_XIOCTL_SET_HT_OP                         119  */
+(AP_NETWORK),                                   /* AR6000_XIOCTL_AP_GET_STAT                       120  */
+(0xFF),                                         /* AR6000_XIOCTL_SET_TX_SELECT_RATES               121  */
+(0xFF),                                         /* AR6000_XIOCTL_SETUP_AGGR                        122  */
+(0xFF),                                         /* AR6000_XIOCTL_ALLOW_AGGR                        123  */
+(AP_NETWORK),                                   /* AR6000_XIOCTL_AP_GET_HIDDEN_SSID                124  */
+(AP_NETWORK),                                   /* AR6000_XIOCTL_AP_GET_COUNTRY                    125  */
+(AP_NETWORK),                                   /* AR6000_XIOCTL_AP_GET_WMODE                      126  */
+(AP_NETWORK),                                   /* AR6000_XIOCTL_AP_GET_DTIM                       127  */
+(AP_NETWORK | ADHOC_NETWORK),                   /* AR6000_XIOCTL_AP_GET_BINTVL                     128  */
+(0xFF),                                         /* AR6000_XIOCTL_AP_GET_RTS                        129  */
+(0xFF),                                         /* AR6000_XIOCTL_DELE_AGGR                         130  */
+(0xFF),                                         /* AR6000_XIOCTL_FETCH_TARGET_REGS                 131  */
+(0xFF),                                         /* AR6000_XIOCTL_HCI_CMD                           132  */
+(0xFF),                                         /* AR6000_XIOCTL_ACL_DATA                          133  */
+(0xFF),                                         /* AR6000_XIOCTL_WLAN_CONN_PRECEDENCE              134  */
+(AP_NETWORK),                                   /* AR6000_XIOCTL_AP_SET_11BG_RATESET               135  */
+(0xFF),
+(0xFF),
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_WMI_SET_BTCOEX_FE_ANT             138  */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_WMI_SET_BTCOEX_COLOCATED_BT_DEV   139  */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_WMI_SET_BTCOEX_BTINQUIRY_PAGE_CONFIG  140  */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_WMI_SET_BTCOEX_SCO_CONFIG         141  */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_WMI_SET_BTCOEX_A2DP_CONFIG        142  */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_WMI_SET_BTCOEX_ACLCOEX_CONFIG     143  */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_WMI_SET_BTCOEX_DEBUG              144  */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_WMI_SET_BT_OPERATING_STATUS       145  */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_WMI_GET_BTCOEX_CONFIG             146  */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_WMI_GET_BTCOEX_GET_STATS          147  */
+(0xFF),                                         /* AR6000_XIOCTL_WMI_SET_QOS_SUPP                  148  */
+(0xFF),                                         /* AR6000_XIOCTL_GET_WLAN_SLEEP_STATE              149  */
+(0xFF),                                         /* AR6000_XIOCTL_SET_BT_HW_POWER_STATE             150  */
+(0xFF),                                         /* AR6000_XIOCTL_GET_BT_HW_POWER_STATE             151  */
+(0xFF),                                         /* AR6000_XIOCTL_ADD_AP_INTERFACE                  152  */
+(0xFF),                                         /* AR6000_XIOCTL_REMOVE_AP_INTERFACE               153  */
+(0xFF),                                         /* AR6000_XIOCTL_WMI_SET_TX_SGI_PARAM              154  */
+};
+
+#endif /*_WMI_FILTER_LINUX_H_*/
diff --git a/drivers/net/ath6kl/os/linux/ioctl.c b/drivers/net/ath6kl/os/linux/ioctl.c
new file mode 100644
index 00000000000..d5f7ac08ab9
--- /dev/null
+++ b/drivers/net/ath6kl/os/linux/ioctl.c
@@ -0,0 +1,4733 @@
+//------------------------------------------------------------------------------
+// Copyright (c) 2004-2010 Atheros Communications Inc.
+// All rights reserved.
+//
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//
+// Author(s): ="Atheros"
+//------------------------------------------------------------------------------
+
+#include "ar6000_drv.h"
+#include "ieee80211_ioctl.h"
+#include "ar6kap_common.h"
+#include "targaddrs.h"
+#include "a_hci.h"
+#include "wlan_config.h"
+
+extern int enablerssicompensation;
+A_UINT32 tcmdRxFreq;
+extern unsigned int wmitimeout;
+extern A_WAITQUEUE_HEAD arEvent;
+extern int tspecCompliance;
+extern int bmienable;
+extern int bypasswmi;
+extern int loghci;
+
+static int
+ar6000_ioctl_get_roam_tbl(struct net_device *dev, struct ifreq *rq)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+    if(wmi_get_roam_tbl_cmd(ar->arWmi) != A_OK) {
+        return -EIO;
+    }
+
+    return 0;
+}
+
+static int
+ar6000_ioctl_get_roam_data(struct net_device *dev, struct ifreq *rq)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+
+    /* currently assume only roam times are required */
+    if(wmi_get_roam_data_cmd(ar->arWmi, ROAM_DATA_TIME) != A_OK) {
+        return -EIO;
+    }
+
+
+    return 0;
+}
+
+static int
+ar6000_ioctl_set_roam_ctrl(struct net_device *dev, char *userdata)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    WMI_SET_ROAM_CTRL_CMD cmd;
+    A_UINT8 size = sizeof(cmd);
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+
+    if (copy_from_user(&cmd, userdata, size)) {
+        return -EFAULT;
+    }
+
+    if (cmd.roamCtrlType == WMI_SET_HOST_BIAS) {
+        if (cmd.info.bssBiasInfo.numBss > 1) {
+            size += (cmd.info.bssBiasInfo.numBss - 1) * sizeof(WMI_BSS_BIAS);
+        }
+    }
+
+    if (copy_from_user(&cmd, userdata, size)) {
+        return -EFAULT;
+    }
+
+    if(wmi_set_roam_ctrl_cmd(ar->arWmi, &cmd, size) != A_OK) {
+        return -EIO;
+    }
+
+    return 0;
+}
+
+static int
+ar6000_ioctl_set_powersave_timers(struct net_device *dev, char *userdata)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    WMI_POWERSAVE_TIMERS_POLICY_CMD cmd;
+    A_UINT8 size = sizeof(cmd);
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+    if (copy_from_user(&cmd, userdata, size)) {
+        return -EFAULT;
+    }
+
+    if (copy_from_user(&cmd, userdata, size)) {
+        return -EFAULT;
+    }
+
+    if(wmi_set_powersave_timers_cmd(ar->arWmi, &cmd, size) != A_OK) {
+        return -EIO;
+    }
+
+    return 0;
+}
+
+static int
+ar6000_ioctl_set_qos_supp(struct net_device *dev, struct ifreq *rq)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    WMI_SET_QOS_SUPP_CMD cmd;
+    A_STATUS ret;
+
+    if ((dev->flags & IFF_UP) != IFF_UP) {
+        return -EIO;
+    }
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+    if (copy_from_user(&cmd, (char *)((unsigned int*)rq->ifr_data + 1),
+                                sizeof(cmd)))
+    {
+        return -EFAULT;
+    }
+
+    ret = wmi_set_qos_supp_cmd(ar->arWmi, cmd.status);
+
+    switch (ret) {
+        case A_OK:
+            return 0;
+        case A_EBUSY :
+            return -EBUSY;
+        case A_NO_MEMORY:
+            return -ENOMEM;
+        case A_EINVAL:
+        default:
+            return -EFAULT;
+    }
+}
+
+static int
+ar6000_ioctl_set_wmm(struct net_device *dev, struct ifreq *rq)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    WMI_SET_WMM_CMD cmd;
+    A_STATUS ret;
+
+    if ((dev->flags & IFF_UP) != IFF_UP) {
+        return -EIO;
+    }
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+    if (copy_from_user(&cmd, (char *)((unsigned int*)rq->ifr_data + 1),
+                                sizeof(cmd)))
+    {
+        return -EFAULT;
+    }
+
+    if (cmd.status == WMI_WMM_ENABLED) {
+        ar->arWmmEnabled = TRUE;
+    } else {
+        ar->arWmmEnabled = FALSE;
+    }
+
+    ret = wmi_set_wmm_cmd(ar->arWmi, cmd.status);
+
+    switch (ret) {
+        case A_OK:
+            return 0;
+        case A_EBUSY :
+            return -EBUSY;
+        case A_NO_MEMORY:
+            return -ENOMEM;
+        case A_EINVAL:
+        default:
+            return -EFAULT;
+    }
+}
+
+static int
+ar6000_ioctl_set_txop(struct net_device *dev, struct ifreq *rq)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    WMI_SET_WMM_TXOP_CMD cmd;
+    A_STATUS ret;
+
+    if ((dev->flags & IFF_UP) != IFF_UP) {
+        return -EIO;
+    }
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+    if (copy_from_user(&cmd, (char *)((unsigned int*)rq->ifr_data + 1),
+                                sizeof(cmd)))
+    {
+        return -EFAULT;
+    }
+
+    ret = wmi_set_wmm_txop(ar->arWmi, cmd.txopEnable);
+
+    switch (ret) {
+        case A_OK:
+            return 0;
+        case A_EBUSY :
+            return -EBUSY;
+        case A_NO_MEMORY:
+            return -ENOMEM;
+        case A_EINVAL:
+        default:
+            return -EFAULT;
+    }
+}
+
+static int
+ar6000_ioctl_get_rd(struct net_device *dev, struct ifreq *rq)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    A_STATUS ret = 0;
+
+    if ((dev->flags & IFF_UP) != IFF_UP || ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+    if(copy_to_user((char *)((unsigned int*)rq->ifr_data + 1),
+                            &ar->arRegCode, sizeof(ar->arRegCode)))
+        ret = -EFAULT;
+
+    return ret;
+}
+
+static int
+ar6000_ioctl_set_country(struct net_device *dev, struct ifreq *rq)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    WMI_AP_SET_COUNTRY_CMD cmd;
+    A_STATUS ret;
+
+    if ((dev->flags & IFF_UP) != IFF_UP) {
+        return -EIO;
+    }
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+    if (copy_from_user(&cmd, (char *)((unsigned int*)rq->ifr_data + 1),
+                                sizeof(cmd)))
+    {
+        return -EFAULT;
+    }
+
+    ar->ap_profile_flag = 1; /* There is a change in profile */
+
+    ret = wmi_set_country(ar->arWmi, cmd.countryCode);
+    A_MEMCPY(ar->ap_country_code, cmd.countryCode, 3);
+
+    switch (ret) {
+        case A_OK:
+            return 0;
+        case A_EBUSY :
+            return -EBUSY;
+        case A_NO_MEMORY:
+            return -ENOMEM;
+        case A_EINVAL:
+        default:
+            return -EFAULT;
+    }
+}
+
+
+/* Get power mode command */
+static int
+ar6000_ioctl_get_power_mode(struct net_device *dev, struct ifreq *rq)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    WMI_POWER_MODE_CMD power_mode;
+    int ret = 0;
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+    power_mode.powerMode = wmi_get_power_mode_cmd(ar->arWmi);
+    if (copy_to_user(rq->ifr_data, &power_mode, sizeof(WMI_POWER_MODE_CMD))) {
+        ret = -EFAULT;
+    }
+
+    return ret;
+}
+
+
+static int
+ar6000_ioctl_set_channelParams(struct net_device *dev, struct ifreq *rq)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    WMI_CHANNEL_PARAMS_CMD cmd, *cmdp;
+    int ret = 0;
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+
+    if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
+        return -EFAULT;
+    }
+
+    if( (ar->arNextMode == AP_NETWORK) && (cmd.numChannels || cmd.scanParam) ) {
+        A_PRINTF("ERROR: Only wmode is allowed in AP mode\n");
+        return -EIO;
+    }
+
+    if (cmd.numChannels > 1) {
+        cmdp = A_MALLOC(130);
+        if (copy_from_user(cmdp, rq->ifr_data,
+                           sizeof (*cmdp) +
+                           ((cmd.numChannels - 1) * sizeof(A_UINT16))))
+        {
+            kfree(cmdp);
+            return -EFAULT;
+        }
+    } else {
+        cmdp = &cmd;
+    }
+
+    if ((ar->arPhyCapability == WMI_11G_CAPABILITY) &&
+        ((cmdp->phyMode == WMI_11A_MODE) || (cmdp->phyMode == WMI_11AG_MODE)))
+    {
+        ret = -EINVAL;
+    }
+
+    if (!ret &&
+        (wmi_set_channelParams_cmd(ar->arWmi, cmdp->scanParam, cmdp->phyMode,
+                                   cmdp->numChannels, cmdp->channelList)
+         != A_OK))
+    {
+        ret = -EIO;
+    }
+
+    if (cmd.numChannels > 1) {
+        kfree(cmdp);
+    }
+
+    ar->ap_wmode = cmdp->phyMode;
+    /* Set the profile change flag to allow a commit cmd */
+    ar->ap_profile_flag = 1;
+
+    return ret;
+}
+
+
+static int
+ar6000_ioctl_set_snr_threshold(struct net_device *dev, struct ifreq *rq)
+{
+
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    WMI_SNR_THRESHOLD_PARAMS_CMD cmd;
+    int ret = 0;
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+    if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
+        return -EFAULT;
+    }
+
+    if( wmi_set_snr_threshold_params(ar->arWmi, &cmd) != A_OK ) {
+        ret = -EIO;
+    }
+
+    return ret;
+}
+
+static int
+ar6000_ioctl_set_rssi_threshold(struct net_device *dev, struct ifreq *rq)
+{
+#define SWAP_THOLD(thold1, thold2) do { \
+    USER_RSSI_THOLD tmpThold;           \
+    tmpThold.tag = thold1.tag;          \
+    tmpThold.rssi = thold1.rssi;        \
+    thold1.tag = thold2.tag;            \
+    thold1.rssi = thold2.rssi;          \
+    thold2.tag = tmpThold.tag;          \
+    thold2.rssi = tmpThold.rssi;        \
+} while (0)
+
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    WMI_RSSI_THRESHOLD_PARAMS_CMD cmd;
+    USER_RSSI_PARAMS rssiParams;
+    A_INT32 i, j;
+    int ret = 0;
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+    if (copy_from_user((char *)&rssiParams, (char *)((unsigned int *)rq->ifr_data + 1), sizeof(USER_RSSI_PARAMS))) {
+        return -EFAULT;
+    }
+    cmd.weight = rssiParams.weight;
+    cmd.pollTime = rssiParams.pollTime;
+
+    A_MEMCPY(ar->rssi_map, &rssiParams.tholds, sizeof(ar->rssi_map));
+    /*
+     *  only 6 elements, so use bubble sorting, in ascending order
+     */
+    for (i = 5; i > 0; i--) {
+        for (j = 0; j < i; j++) { /* above tholds */
+            if (ar->rssi_map[j+1].rssi < ar->rssi_map[j].rssi) {
+                SWAP_THOLD(ar->rssi_map[j+1], ar->rssi_map[j]);
+            } else if (ar->rssi_map[j+1].rssi == ar->rssi_map[j].rssi) {
+                return EFAULT;
+            }
+        }
+    }
+    for (i = 11; i > 6; i--) {
+        for (j = 6; j < i; j++) { /* below tholds */
+            if (ar->rssi_map[j+1].rssi < ar->rssi_map[j].rssi) {
+                SWAP_THOLD(ar->rssi_map[j+1], ar->rssi_map[j]);
+            } else if (ar->rssi_map[j+1].rssi == ar->rssi_map[j].rssi) {
+                return EFAULT;
+            }
+        }
+    }
+
+#ifdef DEBUG
+    for (i = 0; i < 12; i++) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("thold[%d].tag: %d, thold[%d].rssi: %d \n",
+                i, ar->rssi_map[i].tag, i, ar->rssi_map[i].rssi));
+    }
+#endif
+
+    if (enablerssicompensation) {
+        for (i = 0; i < 6; i++)
+            ar->rssi_map[i].rssi = rssi_compensation_reverse_calc(ar, ar->rssi_map[i].rssi, TRUE);
+        for (i = 6; i < 12; i++)
+            ar->rssi_map[i].rssi = rssi_compensation_reverse_calc(ar, ar->rssi_map[i].rssi, FALSE);
+    }
+
+    cmd.thresholdAbove1_Val = ar->rssi_map[0].rssi;
+    cmd.thresholdAbove2_Val = ar->rssi_map[1].rssi;
+    cmd.thresholdAbove3_Val = ar->rssi_map[2].rssi;
+    cmd.thresholdAbove4_Val = ar->rssi_map[3].rssi;
+    cmd.thresholdAbove5_Val = ar->rssi_map[4].rssi;
+    cmd.thresholdAbove6_Val = ar->rssi_map[5].rssi;
+    cmd.thresholdBelow1_Val = ar->rssi_map[6].rssi;
+    cmd.thresholdBelow2_Val = ar->rssi_map[7].rssi;
+    cmd.thresholdBelow3_Val = ar->rssi_map[8].rssi;
+    cmd.thresholdBelow4_Val = ar->rssi_map[9].rssi;
+    cmd.thresholdBelow5_Val = ar->rssi_map[10].rssi;
+    cmd.thresholdBelow6_Val = ar->rssi_map[11].rssi;
+
+    if( wmi_set_rssi_threshold_params(ar->arWmi, &cmd) != A_OK ) {
+        ret = -EIO;
+    }
+
+    return ret;
+}
+
+static int
+ar6000_ioctl_set_lq_threshold(struct net_device *dev, struct ifreq *rq)
+{
+
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    WMI_LQ_THRESHOLD_PARAMS_CMD cmd;
+    int ret = 0;
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+    if (copy_from_user(&cmd, (char *)((unsigned int *)rq->ifr_data + 1), sizeof(cmd))) {
+        return -EFAULT;
+    }
+
+    if( wmi_set_lq_threshold_params(ar->arWmi, &cmd) != A_OK ) {
+        ret = -EIO;
+    }
+
+    return ret;
+}
+
+
+static int
+ar6000_ioctl_set_probedSsid(struct net_device *dev, struct ifreq *rq)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    WMI_PROBED_SSID_CMD cmd;
+    int ret = 0;
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+    if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
+        return -EFAULT;
+    }
+
+    if (wmi_probedSsid_cmd(ar->arWmi, cmd.entryIndex, cmd.flag, cmd.ssidLength,
+                                  cmd.ssid) != A_OK)
+    {
+        ret = -EIO;
+    }
+
+    return ret;
+}
+
+static int
+ar6000_ioctl_set_badAp(struct net_device *dev, struct ifreq *rq)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    WMI_ADD_BAD_AP_CMD cmd;
+    int ret = 0;
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+
+    if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
+        return -EFAULT;
+    }
+
+    if (cmd.badApIndex > WMI_MAX_BAD_AP_INDEX) {
+        return -EIO;
+    }
+
+    if (A_MEMCMP(cmd.bssid, null_mac, AR6000_ETH_ADDR_LEN) == 0) {
+        /*
+         * This is a delete badAP.
+         */
+        if (wmi_deleteBadAp_cmd(ar->arWmi, cmd.badApIndex) != A_OK) {
+            ret = -EIO;
+        }
+    } else {
+        if (wmi_addBadAp_cmd(ar->arWmi, cmd.badApIndex, cmd.bssid) != A_OK) {
+            ret = -EIO;
+        }
+    }
+
+    return ret;
+}
+
+static int
+ar6000_ioctl_create_qos(struct net_device *dev, struct ifreq *rq)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    WMI_CREATE_PSTREAM_CMD cmd;
+    A_STATUS ret;
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+
+    if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
+        return -EFAULT;
+    }
+
+    ret = wmi_verify_tspec_params(&cmd, tspecCompliance);
+    if (ret == A_OK)
+        ret = wmi_create_pstream_cmd(ar->arWmi, &cmd);
+
+    switch (ret) {
+        case A_OK:
+            return 0;
+        case A_EBUSY :
+            return -EBUSY;
+        case A_NO_MEMORY:
+            return -ENOMEM;
+        case A_EINVAL:
+        default:
+            return -EFAULT;
+    }
+}
+
+static int
+ar6000_ioctl_delete_qos(struct net_device *dev, struct ifreq *rq)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    WMI_DELETE_PSTREAM_CMD cmd;
+    int ret = 0;
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+    if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
+        return -EFAULT;
+    }
+
+    ret = wmi_delete_pstream_cmd(ar->arWmi, cmd.trafficClass, cmd.tsid);
+
+    switch (ret) {
+        case A_OK:
+            return 0;
+        case A_EBUSY :
+            return -EBUSY;
+        case A_NO_MEMORY:
+            return -ENOMEM;
+        case A_EINVAL:
+        default:
+            return -EFAULT;
+    }
+}
+
+static int
+ar6000_ioctl_get_qos_queue(struct net_device *dev, struct ifreq *rq)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    struct ar6000_queuereq qreq;
+    int ret = 0;
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+    if( copy_from_user(&qreq, rq->ifr_data,
+                  sizeof(struct ar6000_queuereq)))
+        return -EFAULT;
+
+    qreq.activeTsids = wmi_get_mapped_qos_queue(ar->arWmi, qreq.trafficClass);
+
+    if (copy_to_user(rq->ifr_data, &qreq,
+                 sizeof(struct ar6000_queuereq)))
+    {
+        ret = -EFAULT;
+    }
+
+    return ret;
+}
+
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+static A_STATUS
+ar6000_ioctl_tcmd_get_rx_report(struct net_device *dev,
+                                 struct ifreq *rq, A_UINT8 *data, A_UINT32 len)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    A_UINT32    buf[4+TCMD_MAX_RATES];
+    int ret = 0;
+
+    if (ar->bIsDestroyProgress) {
+        return -EBUSY;
+    }
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+    if (down_interruptible(&ar->arSem)) {
+        return -ERESTARTSYS;
+    }
+
+    if (ar->bIsDestroyProgress) {
+        up(&ar->arSem);
+        return -EBUSY;
+    }
+
+    ar->tcmdRxReport = 0;
+    if (wmi_test_cmd(ar->arWmi, data, len) != A_OK) {
+        up(&ar->arSem);
+        return -EIO;
+    }
+
+    wait_event_interruptible_timeout(arEvent, ar->tcmdRxReport != 0, wmitimeout * HZ);
+
+    if (signal_pending(current)) {
+        ret = -EINTR;
+    }
+
+    buf[0] = ar->tcmdRxTotalPkt;
+    buf[1] = ar->tcmdRxRssi;
+    buf[2] = ar->tcmdRxcrcErrPkt;
+    buf[3] = ar->tcmdRxsecErrPkt;
+    A_MEMCPY(((A_UCHAR *)buf)+(4*sizeof(A_UINT32)), ar->tcmdRateCnt, sizeof(ar->tcmdRateCnt));
+    A_MEMCPY(((A_UCHAR *)buf)+(4*sizeof(A_UINT32))+(TCMD_MAX_RATES *sizeof(A_UINT16)), ar->tcmdRateCntShortGuard, sizeof(ar->tcmdRateCntShortGuard));
+
+    if (!ret && copy_to_user(rq->ifr_data, buf, sizeof(buf))) {
+        ret = -EFAULT;
+    }
+
+    up(&ar->arSem);
+
+    return ret;
+}
+
+void
+ar6000_tcmd_rx_report_event(void *devt, A_UINT8 * results, int len)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)devt;
+    TCMD_CONT_RX * rx_rep = (TCMD_CONT_RX *)results;
+
+    if (enablerssicompensation) {
+        rx_rep->u.report.rssiInDBm = rssi_compensation_calc_tcmd(tcmdRxFreq, rx_rep->u.report.rssiInDBm,rx_rep->u.report.totalPkt);
+    }
+
+
+    ar->tcmdRxTotalPkt = rx_rep->u.report.totalPkt;
+    ar->tcmdRxRssi = rx_rep->u.report.rssiInDBm;
+    ar->tcmdRxcrcErrPkt = rx_rep->u.report.crcErrPkt;
+    ar->tcmdRxsecErrPkt = rx_rep->u.report.secErrPkt;
+    ar->tcmdRxReport = 1;
+    A_MEMZERO(ar->tcmdRateCnt,  sizeof(ar->tcmdRateCnt));
+    A_MEMZERO(ar->tcmdRateCntShortGuard,  sizeof(ar->tcmdRateCntShortGuard));
+    A_MEMCPY(ar->tcmdRateCnt, rx_rep->u.report.rateCnt, sizeof(ar->tcmdRateCnt));
+    A_MEMCPY(ar->tcmdRateCntShortGuard, rx_rep->u.report.rateCntShortGuard, sizeof(ar->tcmdRateCntShortGuard));
+
+    wake_up(&arEvent);
+}
+#endif /* CONFIG_HOST_TCMD_SUPPORT*/
+
+static int
+ar6000_ioctl_set_error_report_bitmask(struct net_device *dev, struct ifreq *rq)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    WMI_TARGET_ERROR_REPORT_BITMASK cmd;
+    int ret = 0;
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+    if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
+        return -EFAULT;
+    }
+
+    ret = wmi_set_error_report_bitmask(ar->arWmi, cmd.bitmask);
+
+    return  (ret==0 ? ret : -EINVAL);
+}
+
+static int
+ar6000_clear_target_stats(struct net_device *dev)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    TARGET_STATS *pStats = &ar->arTargetStats;
+    int ret = 0;
+
+    if (ar->arWmiReady == FALSE) {
+       return -EIO;
+    }
+    AR6000_SPIN_LOCK(&ar->arLock, 0);
+    A_MEMZERO(pStats, sizeof(TARGET_STATS));
+    AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+    return ret;
+}
+
+static int
+ar6000_ioctl_get_target_stats(struct net_device *dev, struct ifreq *rq)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    TARGET_STATS_CMD cmd;
+    TARGET_STATS *pStats = &ar->arTargetStats;
+    int ret = 0;
+
+    if (ar->bIsDestroyProgress) {
+        return -EBUSY;
+    }
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+    if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
+        return -EFAULT;
+    }
+    if (down_interruptible(&ar->arSem)) {
+        return -ERESTARTSYS;
+    }
+    if (ar->bIsDestroyProgress) {
+        up(&ar->arSem);
+        return -EBUSY;
+    }
+
+    ar->statsUpdatePending = TRUE;
+
+    if(wmi_get_stats_cmd(ar->arWmi) != A_OK) {
+        up(&ar->arSem);
+        return -EIO;
+    }
+
+    wait_event_interruptible_timeout(arEvent, ar->statsUpdatePending == FALSE, wmitimeout * HZ);
+
+    if (signal_pending(current)) {
+        ret = -EINTR;
+    }
+
+    if (!ret && copy_to_user(rq->ifr_data, pStats, sizeof(*pStats))) {
+        ret = -EFAULT;
+    }
+
+    if (cmd.clearStats == 1) {
+        ret = ar6000_clear_target_stats(dev);
+    }
+
+    up(&ar->arSem);
+
+    return ret;
+}
+
+static int
+ar6000_ioctl_get_ap_stats(struct net_device *dev, struct ifreq *rq)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    A_UINT32 action; /* Allocating only the desired space on the frame. Declaring is as a WMI_AP_MODE_STAT variable results in exceeding the compiler imposed limit on the maximum frame size */
+    WMI_AP_MODE_STAT *pStats = &ar->arAPStats;
+    int ret = 0;
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+    if (copy_from_user(&action, (char *)((unsigned int*)rq->ifr_data + 1),
+                                sizeof(A_UINT32)))
+    {
+        return -EFAULT;
+    }
+    if (action == AP_CLEAR_STATS) {
+        A_UINT8 i;
+        AR6000_SPIN_LOCK(&ar->arLock, 0);
+        for(i = 0; i < AP_MAX_NUM_STA; i++) {
+            pStats->sta[i].tx_bytes = 0;
+            pStats->sta[i].tx_pkts = 0;
+            pStats->sta[i].tx_error = 0;
+            pStats->sta[i].tx_discard = 0;
+            pStats->sta[i].rx_bytes = 0;
+            pStats->sta[i].rx_pkts = 0;
+            pStats->sta[i].rx_error = 0;
+            pStats->sta[i].rx_discard = 0;
+        }
+        AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+        return ret;
+    }
+
+    if (down_interruptible(&ar->arSem)) {
+        return -ERESTARTSYS;
+    }
+
+    ar->statsUpdatePending = TRUE;
+
+    if(wmi_get_stats_cmd(ar->arWmi) != A_OK) {
+        up(&ar->arSem);
+        return -EIO;
+    }
+
+    wait_event_interruptible_timeout(arEvent, ar->statsUpdatePending == FALSE, wmitimeout * HZ);
+
+    if (signal_pending(current)) {
+        ret = -EINTR;
+    }
+
+    if (!ret && copy_to_user(rq->ifr_data, pStats, sizeof(*pStats))) {
+        ret = -EFAULT;
+    }
+
+    up(&ar->arSem);
+
+    return ret;
+}
+
+static int
+ar6000_ioctl_set_access_params(struct net_device *dev, struct ifreq *rq)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    WMI_SET_ACCESS_PARAMS_CMD cmd;
+    int ret = 0;
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+    if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
+        return -EFAULT;
+    }
+
+    if (wmi_set_access_params_cmd(ar->arWmi, cmd.ac, cmd.txop, cmd.eCWmin, cmd.eCWmax,
+                                  cmd.aifsn) == A_OK)
+    {
+        ret = 0;
+    } else {
+        ret = -EINVAL;
+    }
+
+    return (ret);
+}
+
+static int
+ar6000_ioctl_set_disconnect_timeout(struct net_device *dev, struct ifreq *rq)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    WMI_DISC_TIMEOUT_CMD cmd;
+    int ret = 0;
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+    if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
+        return -EFAULT;
+    }
+
+    if (wmi_disctimeout_cmd(ar->arWmi, cmd.disconnectTimeout) == A_OK)
+    {
+        ret = 0;
+    } else {
+        ret = -EINVAL;
+    }
+
+    return (ret);
+}
+
+static int
+ar6000_xioctl_set_voice_pkt_size(struct net_device *dev, char * userdata)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    WMI_SET_VOICE_PKT_SIZE_CMD cmd;
+    int ret = 0;
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+    if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
+        return -EFAULT;
+    }
+
+    if (wmi_set_voice_pkt_size_cmd(ar->arWmi, cmd.voicePktSize) == A_OK)
+    {
+        ret = 0;
+    } else {
+        ret = -EINVAL;
+    }
+
+
+    return (ret);
+}
+
+static int
+ar6000_xioctl_set_max_sp_len(struct net_device *dev, char * userdata)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    WMI_SET_MAX_SP_LEN_CMD cmd;
+    int ret = 0;
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+    if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
+        return -EFAULT;
+    }
+
+    if (wmi_set_max_sp_len_cmd(ar->arWmi, cmd.maxSPLen) == A_OK)
+    {
+        ret = 0;
+    } else {
+        ret = -EINVAL;
+    }
+
+    return (ret);
+}
+
+
+static int
+ar6000_xioctl_set_bt_status_cmd(struct net_device *dev, char * userdata)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    WMI_SET_BT_STATUS_CMD cmd;
+    int ret = 0;
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+    if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
+        return -EFAULT;
+    }
+
+    if (wmi_set_bt_status_cmd(ar->arWmi, cmd.streamType, cmd.status) == A_OK)
+    {
+        ret = 0;
+    } else {
+        ret = -EINVAL;
+    }
+
+    return (ret);
+}
+
+static int
+ar6000_xioctl_set_bt_params_cmd(struct net_device *dev, char * userdata)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    WMI_SET_BT_PARAMS_CMD cmd;
+    int ret = 0;
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+    if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
+        return -EFAULT;
+    }
+
+    if (wmi_set_bt_params_cmd(ar->arWmi, &cmd) == A_OK)
+    {
+        ret = 0;
+    } else {
+        ret = -EINVAL;
+    }
+
+    return (ret);
+}
+
+static int
+ar6000_xioctl_set_btcoex_fe_ant_cmd(struct net_device * dev, char * userdata)
+{
+	AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+	WMI_SET_BTCOEX_FE_ANT_CMD cmd;
+    int ret = 0;
+
+	if (ar->arWmiReady == FALSE) {
+		return -EIO;
+	}
+	if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
+		return -EFAULT;
+	}
+
+    if (wmi_set_btcoex_fe_ant_cmd(ar->arWmi, &cmd) == A_OK)
+    {
+        ret = 0;
+    } else {
+        ret = -EINVAL;
+    }
+
+	return(ret);
+}
+
+static int
+ar6000_xioctl_set_btcoex_colocated_bt_dev_cmd(struct net_device * dev, char * userdata)
+{
+	AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+	WMI_SET_BTCOEX_COLOCATED_BT_DEV_CMD cmd;
+    int ret = 0;
+
+	if (ar->arWmiReady == FALSE) {
+		return -EIO;
+	}
+
+	if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
+		return -EFAULT;
+	}
+
+    if (wmi_set_btcoex_colocated_bt_dev_cmd(ar->arWmi, &cmd) == A_OK)
+    {
+        ret = 0;
+    } else {
+        ret = -EINVAL;
+    }
+
+	return(ret);
+}
+
+static int
+ar6000_xioctl_set_btcoex_btinquiry_page_config_cmd(struct net_device * dev,  char * userdata)
+{
+	AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+	WMI_SET_BTCOEX_BTINQUIRY_PAGE_CONFIG_CMD cmd;
+    int ret = 0;
+
+	if (ar->arWmiReady == FALSE) {
+		return -EIO;
+	}
+
+	if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
+		return -EFAULT;
+	}
+
+    if (wmi_set_btcoex_btinquiry_page_config_cmd(ar->arWmi, &cmd) == A_OK)
+    {
+        ret = 0;
+    } else {
+        ret = -EINVAL;
+    }
+
+	return(ret);
+}
+
+static int
+ar6000_xioctl_set_btcoex_sco_config_cmd(struct net_device * dev, char * userdata)
+{
+	AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+	WMI_SET_BTCOEX_SCO_CONFIG_CMD cmd;
+    int ret = 0;
+
+	if (ar->arWmiReady == FALSE) {
+		return -EIO;
+	}
+
+	if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
+		return -EFAULT;
+	}
+
+    if (wmi_set_btcoex_sco_config_cmd(ar->arWmi, &cmd) == A_OK)
+    {
+        ret = 0;
+    } else {
+        ret = -EINVAL;
+    }
+
+	return(ret);
+}
+
+static int
+ar6000_xioctl_set_btcoex_a2dp_config_cmd(struct net_device * dev,
+														char * userdata)
+{
+	AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+	WMI_SET_BTCOEX_A2DP_CONFIG_CMD cmd;
+    int ret = 0;
+
+	if (ar->arWmiReady == FALSE) {
+		return -EIO;
+	}
+
+	if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
+		return -EFAULT;
+	}
+
+    if (wmi_set_btcoex_a2dp_config_cmd(ar->arWmi, &cmd) == A_OK)
+    {
+        ret = 0;
+    } else {
+        ret = -EINVAL;
+    }
+
+	return(ret);
+}
+
+static int
+ar6000_xioctl_set_btcoex_aclcoex_config_cmd(struct net_device * dev, char * userdata)
+{
+	AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+	WMI_SET_BTCOEX_ACLCOEX_CONFIG_CMD cmd;
+    int ret = 0;
+
+	if (ar->arWmiReady == FALSE) {
+		return -EIO;
+	}
+
+	if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
+		return -EFAULT;
+	}
+
+    if (wmi_set_btcoex_aclcoex_config_cmd(ar->arWmi, &cmd) == A_OK)
+    {
+        ret = 0;
+    } else {
+        ret = -EINVAL;
+    }
+
+	return(ret);
+}
+
+static int
+ar60000_xioctl_set_btcoex_debug_cmd(struct net_device * dev, char * userdata)
+{
+	AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+	WMI_SET_BTCOEX_DEBUG_CMD cmd;
+    int ret = 0;
+
+	if (ar->arWmiReady == FALSE) {
+		return -EIO;
+	}
+
+	if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
+		return -EFAULT;
+	}
+
+    if (wmi_set_btcoex_debug_cmd(ar->arWmi, &cmd) == A_OK)
+    {
+        ret = 0;
+    } else {
+        ret = -EINVAL;
+    }
+
+	return(ret);
+}
+
+static int
+ar6000_xioctl_set_btcoex_bt_operating_status_cmd(struct net_device * dev, char * userdata)
+{
+     AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+     WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMD cmd;
+     int ret = 0;
+
+    if (ar->arWmiReady == FALSE) {
+	return -EIO;
+    }
+
+    if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
+	return -EFAULT;
+    }
+
+    if (wmi_set_btcoex_bt_operating_status_cmd(ar->arWmi, &cmd) == A_OK)
+    {
+        ret = 0;
+    } else {
+        ret = -EINVAL;
+    }
+    return(ret);
+}
+
+static int
+ar6000_xioctl_get_btcoex_config_cmd(struct net_device * dev, char * userdata,
+											struct ifreq *rq)
+{
+
+	AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    AR6000_BTCOEX_CONFIG btcoexConfig;
+    WMI_BTCOEX_CONFIG_EVENT *pbtcoexConfigEv = &ar->arBtcoexConfig;
+
+    int ret = 0;
+
+    if (ar->bIsDestroyProgress) {
+            return -EBUSY;
+    }
+    if (ar->arWmiReady == FALSE) {
+            return -EIO;
+    }
+	if (copy_from_user(&btcoexConfig.configCmd, userdata, sizeof(AR6000_BTCOEX_CONFIG))) {
+		return -EFAULT;
+	}
+    if (down_interruptible(&ar->arSem)) {
+        return -ERESTARTSYS;
+    }
+
+    if (wmi_get_btcoex_config_cmd(ar->arWmi, (WMI_GET_BTCOEX_CONFIG_CMD *)&btcoexConfig.configCmd) != A_OK)
+    {
+    	up(&ar->arSem);
+    	return -EIO;
+    }
+
+    ar->statsUpdatePending = TRUE;
+
+    wait_event_interruptible_timeout(arEvent, ar->statsUpdatePending == FALSE, wmitimeout * HZ);
+
+    if (signal_pending(current)) {
+       ret = -EINTR;
+    }
+
+    if (!ret && copy_to_user(btcoexConfig.configEvent, pbtcoexConfigEv, sizeof(WMI_BTCOEX_CONFIG_EVENT))) {
+            ret = -EFAULT;
+    }
+    up(&ar->arSem);
+    return ret;
+}
+
+static int
+ar6000_xioctl_get_btcoex_stats_cmd(struct net_device * dev, char * userdata, struct ifreq *rq)
+{
+	AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    AR6000_BTCOEX_STATS btcoexStats;
+    WMI_BTCOEX_STATS_EVENT *pbtcoexStats = &ar->arBtcoexStats;
+    int ret = 0;
+
+    if (ar->bIsDestroyProgress) {
+            return -EBUSY;
+    }
+    if (ar->arWmiReady == FALSE) {
+            return -EIO;
+    }
+
+    if (down_interruptible(&ar->arSem)) {
+        return -ERESTARTSYS;
+    }
+
+	if (copy_from_user(&btcoexStats.statsEvent, userdata, sizeof(AR6000_BTCOEX_CONFIG))) {
+		return -EFAULT;
+	}
+
+    if (wmi_get_btcoex_stats_cmd(ar->arWmi) != A_OK)
+    {
+    	up(&ar->arSem);
+    	return -EIO;
+    }
+
+    ar->statsUpdatePending = TRUE;
+
+    wait_event_interruptible_timeout(arEvent, ar->statsUpdatePending == FALSE, wmitimeout * HZ);
+
+    if (signal_pending(current)) {
+       ret = -EINTR;
+    }
+
+    if (!ret && copy_to_user(btcoexStats.statsEvent, pbtcoexStats, sizeof(WMI_BTCOEX_STATS_EVENT))) {
+            ret = -EFAULT;
+    }
+
+
+    up(&ar->arSem);
+
+	return(ret);
+}
+
+#ifdef CONFIG_HOST_GPIO_SUPPORT
+struct ar6000_gpio_intr_wait_cmd_s  gpio_intr_results;
+/* gpio_reg_results and gpio_data_available are protected by arSem */
+static struct ar6000_gpio_register_cmd_s gpio_reg_results;
+static A_BOOL gpio_data_available; /* Requested GPIO data available */
+static A_BOOL gpio_intr_available; /* GPIO interrupt info available */
+static A_BOOL gpio_ack_received;   /* GPIO ack was received */
+
+/* Host-side initialization for General Purpose I/O support */
+void ar6000_gpio_init(void)
+{
+    gpio_intr_available = FALSE;
+    gpio_data_available = FALSE;
+    gpio_ack_received   = FALSE;
+}
+
+/*
+ * Called when a GPIO interrupt is received from the Target.
+ * intr_values shows which GPIO pins have interrupted.
+ * input_values shows a recent value of GPIO pins.
+ */
+void
+ar6000_gpio_intr_rx(A_UINT32 intr_mask, A_UINT32 input_values)
+{
+    gpio_intr_results.intr_mask = intr_mask;
+    gpio_intr_results.input_values = input_values;
+    *((volatile A_BOOL *)&gpio_intr_available) = TRUE;
+    wake_up(&arEvent);
+}
+
+/*
+ * This is called when a response is received from the Target
+ * for a previous or ar6000_gpio_input_get or ar6000_gpio_register_get
+ * call.
+ */
+void
+ar6000_gpio_data_rx(A_UINT32 reg_id, A_UINT32 value)
+{
+    gpio_reg_results.gpioreg_id = reg_id;
+    gpio_reg_results.value = value;
+    *((volatile A_BOOL *)&gpio_data_available) = TRUE;
+    wake_up(&arEvent);
+}
+
+/*
+ * This is called when an acknowledgement is received from the Target
+ * for a previous or ar6000_gpio_output_set or ar6000_gpio_register_set
+ * call.
+ */
+void
+ar6000_gpio_ack_rx(void)
+{
+    gpio_ack_received = TRUE;
+    wake_up(&arEvent);
+}
+
+A_STATUS
+ar6000_gpio_output_set(struct net_device *dev,
+                       A_UINT32 set_mask,
+                       A_UINT32 clear_mask,
+                       A_UINT32 enable_mask,
+                       A_UINT32 disable_mask)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+    gpio_ack_received = FALSE;
+    return wmi_gpio_output_set(ar->arWmi,
+                set_mask, clear_mask, enable_mask, disable_mask);
+}
+
+static A_STATUS
+ar6000_gpio_input_get(struct net_device *dev)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+    *((volatile A_BOOL *)&gpio_data_available) = FALSE;
+    return wmi_gpio_input_get(ar->arWmi);
+}
+
+static A_STATUS
+ar6000_gpio_register_set(struct net_device *dev,
+                         A_UINT32 gpioreg_id,
+                         A_UINT32 value)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+    gpio_ack_received = FALSE;
+    return wmi_gpio_register_set(ar->arWmi, gpioreg_id, value);
+}
+
+static A_STATUS
+ar6000_gpio_register_get(struct net_device *dev,
+                         A_UINT32 gpioreg_id)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+    *((volatile A_BOOL *)&gpio_data_available) = FALSE;
+    return wmi_gpio_register_get(ar->arWmi, gpioreg_id);
+}
+
+static A_STATUS
+ar6000_gpio_intr_ack(struct net_device *dev,
+                     A_UINT32 ack_mask)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+    gpio_intr_available = FALSE;
+    return wmi_gpio_intr_ack(ar->arWmi, ack_mask);
+}
+#endif /* CONFIG_HOST_GPIO_SUPPORT */
+
+#if defined(CONFIG_TARGET_PROFILE_SUPPORT)
+static struct prof_count_s prof_count_results;
+static A_BOOL prof_count_available; /* Requested GPIO data available */
+
+static A_STATUS
+prof_count_get(struct net_device *dev)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+    *((volatile A_BOOL *)&prof_count_available) = FALSE;
+    return wmi_prof_count_get_cmd(ar->arWmi);
+}
+
+/*
+ * This is called when a response is received from the Target
+ * for a previous prof_count_get call.
+ */
+void
+prof_count_rx(A_UINT32 addr, A_UINT32 count)
+{
+    prof_count_results.addr = addr;
+    prof_count_results.count = count;
+    *((volatile A_BOOL *)&prof_count_available) = TRUE;
+    wake_up(&arEvent);
+}
+#endif /* CONFIG_TARGET_PROFILE_SUPPORT */
+
+
+static A_STATUS
+ar6000_create_acl_data_osbuf(struct net_device *dev, A_UINT8 *userdata, void **p_osbuf)
+{
+    void *osbuf = NULL;
+    A_UINT8 tmp_space[8];
+    HCI_ACL_DATA_PKT *acl;
+    A_UINT8 hdr_size, *datap=NULL;
+    A_STATUS ret = A_OK;
+
+    /* ACL is in data path. There is a need to create pool
+     * mechanism for allocating and freeing NETBUFs - ToDo later.
+     */
+
+    *p_osbuf = NULL;
+    acl = (HCI_ACL_DATA_PKT *)tmp_space;
+    hdr_size = sizeof(acl->hdl_and_flags) + sizeof(acl->data_len);
+
+    do {
+        if (a_copy_from_user(acl, userdata, hdr_size)) {
+            ret = A_EFAULT;
+            break;
+        }
+
+        osbuf = A_NETBUF_ALLOC(hdr_size + acl->data_len);
+        if (osbuf == NULL) {
+           ret = A_NO_MEMORY;
+           break;
+        }
+        A_NETBUF_PUT(osbuf, hdr_size + acl->data_len);
+        datap = (A_UINT8 *)A_NETBUF_DATA(osbuf);
+
+        /* Real copy to osbuf */
+        acl = (HCI_ACL_DATA_PKT *)(datap);
+        A_MEMCPY(acl, tmp_space, hdr_size);
+        if (a_copy_from_user(acl->data, userdata + hdr_size, acl->data_len)) {
+            ret = A_EFAULT;
+            break;
+        }
+    } while(FALSE);
+
+    if (ret == A_OK) {
+        *p_osbuf = osbuf;
+    } else {
+        A_NETBUF_FREE(osbuf);
+    }
+    return ret;
+}
+
+
+
+int
+ar6000_ioctl_ap_setparam(AR_SOFTC_T *ar, int param, int value)
+{
+    int ret=0;
+
+    switch(param) {
+        case IEEE80211_PARAM_WPA:
+            switch (value) {
+                case WPA_MODE_WPA1:
+                    ar->arAuthMode = WPA_AUTH;
+                    break;
+                case WPA_MODE_WPA2:
+                    ar->arAuthMode = WPA2_AUTH;
+                    break;
+                case WPA_MODE_AUTO:
+                    ar->arAuthMode = WPA_AUTH | WPA2_AUTH;
+                    break;
+                case WPA_MODE_NONE:
+                    ar->arAuthMode = NONE_AUTH;
+                    break;
+            }
+            break;
+        case IEEE80211_PARAM_AUTHMODE:
+            if(value == IEEE80211_AUTH_WPA_PSK) {
+                if (WPA_AUTH == ar->arAuthMode) {
+                    ar->arAuthMode = WPA_PSK_AUTH;
+                } else if (WPA2_AUTH == ar->arAuthMode) {
+                    ar->arAuthMode = WPA2_PSK_AUTH;
+                } else if ((WPA_AUTH | WPA2_AUTH) == ar->arAuthMode) {
+                    ar->arAuthMode = WPA_PSK_AUTH | WPA2_PSK_AUTH;
+                } else {
+                    AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Error -  Setting PSK "\
+                        "mode when WPA param was set to %d\n",
+                        ar->arAuthMode));
+                    ret = -EIO;
+                }
+            }
+            break;
+        case IEEE80211_PARAM_UCASTCIPHER:
+            ar->arPairwiseCrypto = 0;
+            if(value & (1<<IEEE80211_CIPHER_AES_CCM)) {
+                ar->arPairwiseCrypto |= AES_CRYPT;
+            }
+            if(value & (1<<IEEE80211_CIPHER_TKIP)) {
+                ar->arPairwiseCrypto |= TKIP_CRYPT;
+            }
+            if(!ar->arPairwiseCrypto) {
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                           ("Error - Invalid cipher in WPA \n"));
+                ret = -EIO;
+            }
+            break;
+        case IEEE80211_PARAM_PRIVACY:
+            if(value == 0) {
+                ar->arDot11AuthMode      = OPEN_AUTH;
+                ar->arAuthMode           = NONE_AUTH;
+                ar->arPairwiseCrypto     = NONE_CRYPT;
+                ar->arPairwiseCryptoLen  = 0;
+                ar->arGroupCrypto        = NONE_CRYPT;
+                ar->arGroupCryptoLen     = 0;
+            }
+            break;
+#ifdef WAPI_ENABLE
+        case IEEE80211_PARAM_WAPI:
+            A_PRINTF("WAPI Policy: %d\n", value);
+            ar->arDot11AuthMode      = OPEN_AUTH;
+            ar->arAuthMode           = NONE_AUTH;
+            if(value & 0x1) {
+                ar->arPairwiseCrypto     = WAPI_CRYPT;
+                ar->arGroupCrypto        = WAPI_CRYPT;
+            } else {
+                ar->arPairwiseCrypto     = NONE_CRYPT;
+                ar->arGroupCrypto        = NONE_CRYPT;
+            }
+            break;
+#endif
+    }
+    return ret;
+}
+
+int
+ar6000_ioctl_setparam(AR_SOFTC_T *ar, int param, int value)
+{
+    A_BOOL profChanged = FALSE;
+    int ret=0;
+
+    if(ar->arNextMode == AP_NETWORK) {
+        ar->ap_profile_flag = 1; /* There is a change in profile */
+        switch (param) {
+            case IEEE80211_PARAM_WPA:
+            case IEEE80211_PARAM_AUTHMODE:
+            case IEEE80211_PARAM_UCASTCIPHER:
+            case IEEE80211_PARAM_PRIVACY:
+            case IEEE80211_PARAM_WAPI:
+                ret = ar6000_ioctl_ap_setparam(ar, param, value);
+                return ret;
+        }
+    }
+
+    switch (param) {
+        case IEEE80211_PARAM_WPA:
+            switch (value) {
+                case WPA_MODE_WPA1:
+                    ar->arAuthMode = WPA_AUTH;
+                    profChanged    = TRUE;
+                    break;
+                case WPA_MODE_WPA2:
+                    ar->arAuthMode = WPA2_AUTH;
+                    profChanged    = TRUE;
+                    break;
+                case WPA_MODE_NONE:
+                    ar->arAuthMode = NONE_AUTH;
+                    profChanged    = TRUE;
+                    break;
+            }
+            break;
+        case IEEE80211_PARAM_AUTHMODE:
+            switch(value) {
+                case IEEE80211_AUTH_WPA_PSK:
+                    if (WPA_AUTH == ar->arAuthMode) {
+                        ar->arAuthMode = WPA_PSK_AUTH;
+                        profChanged    = TRUE;
+                    } else if (WPA2_AUTH == ar->arAuthMode) {
+                        ar->arAuthMode = WPA2_PSK_AUTH;
+                        profChanged    = TRUE;
+                    } else {
+                        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Error -  Setting PSK "\
+                            "mode when WPA param was set to %d\n",
+                            ar->arAuthMode));
+                        ret = -EIO;
+                    }
+                    break;
+                case IEEE80211_AUTH_WPA_CCKM:
+                    if (WPA2_AUTH == ar->arAuthMode) {
+                        ar->arAuthMode = WPA2_AUTH_CCKM;
+                    } else {
+                        ar->arAuthMode = WPA_AUTH_CCKM;
+                    }
+                    break;
+                default:
+                    break;
+            }
+            break;
+        case IEEE80211_PARAM_UCASTCIPHER:
+            switch (value) {
+                case IEEE80211_CIPHER_AES_CCM:
+                    ar->arPairwiseCrypto = AES_CRYPT;
+                    profChanged          = TRUE;
+                    break;
+                case IEEE80211_CIPHER_TKIP:
+                    ar->arPairwiseCrypto = TKIP_CRYPT;
+                    profChanged          = TRUE;
+                    break;
+                case IEEE80211_CIPHER_WEP:
+                    ar->arPairwiseCrypto = WEP_CRYPT;
+                    profChanged          = TRUE;
+                    break;
+                case IEEE80211_CIPHER_NONE:
+                    ar->arPairwiseCrypto = NONE_CRYPT;
+                    profChanged          = TRUE;
+                    break;
+            }
+            break;
+        case IEEE80211_PARAM_UCASTKEYLEN:
+            if (!IEEE80211_IS_VALID_WEP_CIPHER_LEN(value)) {
+                ret = -EIO;
+            } else {
+                ar->arPairwiseCryptoLen = value;
+            }
+            break;
+        case IEEE80211_PARAM_MCASTCIPHER:
+            switch (value) {
+                case IEEE80211_CIPHER_AES_CCM:
+                    ar->arGroupCrypto = AES_CRYPT;
+                    profChanged       = TRUE;
+                    break;
+                case IEEE80211_CIPHER_TKIP:
+                    ar->arGroupCrypto = TKIP_CRYPT;
+                    profChanged       = TRUE;
+                    break;
+                case IEEE80211_CIPHER_WEP:
+                    ar->arGroupCrypto = WEP_CRYPT;
+                    profChanged       = TRUE;
+                    break;
+                case IEEE80211_CIPHER_NONE:
+                    ar->arGroupCrypto = NONE_CRYPT;
+                    profChanged       = TRUE;
+                    break;
+            }
+            break;
+        case IEEE80211_PARAM_MCASTKEYLEN:
+            if (!IEEE80211_IS_VALID_WEP_CIPHER_LEN(value)) {
+                ret = -EIO;
+            } else {
+                ar->arGroupCryptoLen = value;
+            }
+            break;
+        case IEEE80211_PARAM_COUNTERMEASURES:
+            if (ar->arWmiReady == FALSE) {
+                return -EIO;
+            }
+            wmi_set_tkip_countermeasures_cmd(ar->arWmi, value);
+            break;
+        default:
+            break;
+    }
+    if ((ar->arNextMode != AP_NETWORK) && (profChanged == TRUE)) {
+        /*
+         * profile has changed.  Erase ssid to signal change
+         */
+        A_MEMZERO(ar->arSsid, sizeof(ar->arSsid));
+    }
+
+    return ret;
+}
+
+int
+ar6000_ioctl_setkey(AR_SOFTC_T *ar, struct ieee80211req_key *ik)
+{
+    KEY_USAGE keyUsage;
+    A_STATUS status;
+    CRYPTO_TYPE keyType = NONE_CRYPT;
+
+#ifdef USER_KEYS
+    ar->user_saved_keys.keyOk = FALSE;
+#endif
+    if ( (0 == memcmp(ik->ik_macaddr, null_mac, IEEE80211_ADDR_LEN)) ||
+         (0 == memcmp(ik->ik_macaddr, bcast_mac, IEEE80211_ADDR_LEN)) ) {
+        keyUsage = GROUP_USAGE;
+        if(ar->arNextMode == AP_NETWORK) {
+            A_MEMCPY(&ar->ap_mode_bkey, ik,
+                     sizeof(struct ieee80211req_key));
+#ifdef WAPI_ENABLE
+            if(ar->arPairwiseCrypto == WAPI_CRYPT) {
+                return ap_set_wapi_key(ar, ik);
+            }
+#endif
+        }
+#ifdef USER_KEYS
+        A_MEMCPY(&ar->user_saved_keys.bcast_ik, ik,
+                 sizeof(struct ieee80211req_key));
+#endif
+    } else {
+        keyUsage = PAIRWISE_USAGE;
+#ifdef USER_KEYS
+        A_MEMCPY(&ar->user_saved_keys.ucast_ik, ik,
+                 sizeof(struct ieee80211req_key));
+#endif
+#ifdef WAPI_ENABLE
+        if(ar->arNextMode == AP_NETWORK) {
+            if(ar->arPairwiseCrypto == WAPI_CRYPT) {
+                return ap_set_wapi_key(ar, ik);
+            }
+        }
+#endif
+    }
+
+    switch (ik->ik_type) {
+        case IEEE80211_CIPHER_WEP:
+            keyType = WEP_CRYPT;
+            break;
+        case IEEE80211_CIPHER_TKIP:
+            keyType = TKIP_CRYPT;
+            break;
+        case IEEE80211_CIPHER_AES_CCM:
+            keyType = AES_CRYPT;
+            break;
+        default:
+            break;
+    }
+#ifdef USER_KEYS
+    ar->user_saved_keys.keyType = keyType;
+#endif
+    if (IEEE80211_CIPHER_CCKM_KRK != ik->ik_type) {
+        if (NONE_CRYPT == keyType) {
+            return -EIO;
+        }
+
+        if ((WEP_CRYPT == keyType)&&(!ar->arConnected)) {
+             int index = ik->ik_keyix;
+
+            if (!IEEE80211_IS_VALID_WEP_CIPHER_LEN(ik->ik_keylen)) {
+                return -EIO;
+            }
+
+            A_MEMZERO(ar->arWepKeyList[index].arKey,
+                            sizeof(ar->arWepKeyList[index].arKey));
+            A_MEMCPY(ar->arWepKeyList[index].arKey, ik->ik_keydata, ik->ik_keylen);
+            ar->arWepKeyList[index].arKeyLen = ik->ik_keylen;
+
+            if(ik->ik_flags & IEEE80211_KEY_DEFAULT){
+                ar->arDefTxKeyIndex = index;
+            }
+
+            return 0;
+        }
+
+        if (((WPA_PSK_AUTH == ar->arAuthMode) || (WPA2_PSK_AUTH == ar->arAuthMode)) &&
+            (GROUP_USAGE & keyUsage))
+        {
+            A_UNTIMEOUT(&ar->disconnect_timer);
+        }
+
+        status = wmi_addKey_cmd(ar->arWmi, ik->ik_keyix, keyType, keyUsage,
+                                ik->ik_keylen, (A_UINT8 *)&ik->ik_keyrsc,
+                                ik->ik_keydata, KEY_OP_INIT_VAL, ik->ik_macaddr,
+                                SYNC_BOTH_WMIFLAG);
+
+        if (status != A_OK) {
+            return -EIO;
+        }
+    } else {
+        status = wmi_add_krk_cmd(ar->arWmi, ik->ik_keydata);
+    }
+
+#ifdef USER_KEYS
+    ar->user_saved_keys.keyOk = TRUE;
+#endif
+
+    return 0;
+}
+
+int ar6000_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    HIF_DEVICE *hifDevice = ar->arHifDevice;
+    int ret = 0, param;
+    unsigned int address = 0;
+    unsigned int length = 0;
+    unsigned char *buffer;
+    char *userdata;
+    A_UINT32 connectCtrlFlags;
+
+
+    WMI_SET_AKMP_PARAMS_CMD  akmpParams;
+    WMI_SET_PMKID_LIST_CMD   pmkidInfo;
+
+    WMI_SET_HT_CAP_CMD htCap;
+    WMI_SET_HT_OP_CMD htOp;
+
+    /*
+     * ioctl operations may have to wait for the Target, so we cannot hold rtnl.
+     * Prevent the device from disappearing under us and release the lock during
+     * the ioctl operation.
+     */
+    dev_hold(dev);
+    rtnl_unlock();
+
+    if (cmd == AR6000_IOCTL_EXTENDED) {
+        /*
+         * This allows for many more wireless ioctls than would otherwise
+         * be available.  Applications embed the actual ioctl command in
+         * the first word of the parameter block, and use the command
+         * AR6000_IOCTL_EXTENDED_CMD on the ioctl call.
+         */
+	if (get_user(cmd, (int *)rq->ifr_data)) {
+	    ret = -EFAULT;
+	    goto ioctl_done;
+	}
+        userdata = (char *)(((unsigned int *)rq->ifr_data)+1);
+        if(is_xioctl_allowed(ar->arNextMode, cmd) != A_OK) {
+            A_PRINTF("xioctl: cmd=%d not allowed in this mode\n",cmd);
+            ret = -EOPNOTSUPP;
+            goto ioctl_done;
+    }
+    } else {
+        A_STATUS ret = is_iwioctl_allowed(ar->arNextMode, cmd);
+        if(ret == A_ENOTSUP) {
+            A_PRINTF("iwioctl: cmd=0x%x not allowed in this mode\n", cmd);
+            ret = -EOPNOTSUPP;
+            goto ioctl_done;
+        } else if (ret == A_ERROR) {
+            /* It is not our ioctl (out of range ioctl) */
+            ret = -EOPNOTSUPP;
+            goto ioctl_done;
+        }
+        userdata = (char *)rq->ifr_data;
+    }
+
+    if ((ar->arWlanState == WLAN_DISABLED) &&
+        ((cmd != AR6000_XIOCTRL_WMI_SET_WLAN_STATE) &&
+         (cmd != AR6000_XIOCTL_GET_WLAN_SLEEP_STATE) &&
+         (cmd != AR6000_XIOCTL_DIAG_READ) &&
+         (cmd != AR6000_XIOCTL_DIAG_WRITE) &&
+         (cmd != AR6000_XIOCTL_SET_BT_HW_POWER_STATE) &&
+         (cmd != AR6000_XIOCTL_GET_BT_HW_POWER_STATE) &&
+         (cmd != AR6000_XIOCTL_ADD_AP_INTERFACE) &&
+         (cmd != AR6000_XIOCTL_REMOVE_AP_INTERFACE) &&
+         (cmd != AR6000_IOCTL_WMI_GETREV)))
+    {
+        ret = -EIO;
+        goto ioctl_done;
+    }
+
+    ret = 0;
+    switch(cmd)
+    {
+        case IEEE80211_IOCTL_SETPARAM:
+        {
+            int param, value;
+            int *ptr = (int *)rq->ifr_ifru.ifru_newname;
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else {
+                param = *ptr++;
+                value = *ptr;
+                ret = ar6000_ioctl_setparam(ar,param,value);
+            }
+            break;
+        }
+        case IEEE80211_IOCTL_SETKEY:
+        {
+            struct ieee80211req_key keydata;
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&keydata, userdata,
+                            sizeof(struct ieee80211req_key))) {
+                ret = -EFAULT;
+            } else {
+                ar6000_ioctl_setkey(ar, &keydata);
+            }
+            break;
+        }
+        case IEEE80211_IOCTL_DELKEY:
+        case IEEE80211_IOCTL_SETOPTIE:
+        {
+            //ret = -EIO;
+            break;
+        }
+        case IEEE80211_IOCTL_SETMLME:
+        {
+            struct ieee80211req_mlme mlme;
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&mlme, userdata,
+                            sizeof(struct ieee80211req_mlme))) {
+                ret = -EFAULT;
+            } else {
+                switch (mlme.im_op) {
+                    case IEEE80211_MLME_AUTHORIZE:
+                        A_PRINTF("setmlme AUTHORIZE %02X:%02X\n",
+                            mlme.im_macaddr[4], mlme.im_macaddr[5]);
+                        break;
+                    case IEEE80211_MLME_UNAUTHORIZE:
+                        A_PRINTF("setmlme UNAUTHORIZE %02X:%02X\n",
+                            mlme.im_macaddr[4], mlme.im_macaddr[5]);
+                        break;
+                    case IEEE80211_MLME_DEAUTH:
+                        A_PRINTF("setmlme DEAUTH %02X:%02X\n",
+                            mlme.im_macaddr[4], mlme.im_macaddr[5]);
+                        //remove_sta(ar, mlme.im_macaddr);
+                        break;
+                    case IEEE80211_MLME_DISASSOC:
+                        A_PRINTF("setmlme DISASSOC %02X:%02X\n",
+                            mlme.im_macaddr[4], mlme.im_macaddr[5]);
+                        //remove_sta(ar, mlme.im_macaddr);
+                        break;
+                    default:
+                        ret = 0;
+                        goto ioctl_done;
+                }
+
+                wmi_ap_set_mlme(ar->arWmi, mlme.im_op, mlme.im_macaddr,
+                                mlme.im_reason);
+            }
+            break;
+        }
+        case IEEE80211_IOCTL_ADDPMKID:
+        {
+            struct ieee80211req_addpmkid  req;
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&req, userdata, sizeof(struct ieee80211req_addpmkid))) {
+                ret = -EFAULT;
+            } else {
+                A_STATUS status;
+
+                AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("Add pmkid for %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x en=%d\n",
+                    req.pi_bssid[0], req.pi_bssid[1], req.pi_bssid[2],
+                    req.pi_bssid[3], req.pi_bssid[4], req.pi_bssid[5],
+                    req.pi_enable));
+
+                status = wmi_setPmkid_cmd(ar->arWmi, req.pi_bssid, req.pi_pmkid,
+                              req.pi_enable);
+
+                if (status != A_OK) {
+                    ret = -EIO;
+                    goto ioctl_done;
+                }
+            }
+            break;
+        }
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+        case AR6000_XIOCTL_TCMD_CONT_TX:
+            {
+                TCMD_CONT_TX txCmd;
+
+                if ((ar->tcmdPm == TCMD_PM_SLEEP) ||
+                    (ar->tcmdPm == TCMD_PM_DEEPSLEEP))
+                {
+                    A_PRINTF("Can NOT send tx tcmd when target is asleep! \n");
+                    ret = -EFAULT;
+                    goto ioctl_done;
+                }
+
+                if(copy_from_user(&txCmd, userdata, sizeof(TCMD_CONT_TX))) {
+                    ret = -EFAULT;
+                    goto ioctl_done;
+                } else {
+                    wmi_test_cmd(ar->arWmi,(A_UINT8 *)&txCmd, sizeof(TCMD_CONT_TX));
+                }
+            }
+            break;
+        case AR6000_XIOCTL_TCMD_CONT_RX:
+            {
+                TCMD_CONT_RX rxCmd;
+
+                if ((ar->tcmdPm == TCMD_PM_SLEEP) ||
+                    (ar->tcmdPm == TCMD_PM_DEEPSLEEP))
+                {
+                    A_PRINTF("Can NOT send rx tcmd when target is asleep! \n");
+                    ret = -EFAULT;
+                    goto ioctl_done;
+                }
+                if(copy_from_user(&rxCmd, userdata, sizeof(TCMD_CONT_RX))) {
+                    ret = -EFAULT;
+                    goto ioctl_done;
+                }
+
+                switch(rxCmd.act)
+                {
+                    case TCMD_CONT_RX_PROMIS:
+                    case TCMD_CONT_RX_FILTER:
+                    case TCMD_CONT_RX_SETMAC:
+                    case TCMD_CONT_RX_SET_ANT_SWITCH_TABLE:
+                         wmi_test_cmd(ar->arWmi,(A_UINT8 *)&rxCmd,
+                                                sizeof(TCMD_CONT_RX));
+                         tcmdRxFreq = rxCmd.u.para.freq;
+                         break;
+                    case TCMD_CONT_RX_REPORT:
+                         ar6000_ioctl_tcmd_get_rx_report(dev, rq,
+                         (A_UINT8 *)&rxCmd, sizeof(TCMD_CONT_RX));
+                         break;
+                    default:
+                         A_PRINTF("Unknown Cont Rx mode: %d\n",rxCmd.act);
+                         ret = -EINVAL;
+                         goto ioctl_done;
+                }
+            }
+            break;
+        case AR6000_XIOCTL_TCMD_PM:
+            {
+                TCMD_PM pmCmd;
+
+                if(copy_from_user(&pmCmd, userdata, sizeof(TCMD_PM))) {
+                    ret = -EFAULT;
+                    goto ioctl_done;
+                }
+                ar->tcmdPm = pmCmd.mode;
+                wmi_test_cmd(ar->arWmi, (A_UINT8*)&pmCmd, sizeof(TCMD_PM));
+            }
+            break;
+#endif /* CONFIG_HOST_TCMD_SUPPORT */
+
+        case AR6000_XIOCTL_BMI_DONE:
+            if(bmienable)
+            {
+                rtnl_lock(); /* ar6000_init expects to be called holding rtnl lock */
+                ret = ar6000_init(dev);
+                rtnl_unlock();
+            }
+            else
+            {
+                ret = BMIDone(hifDevice);
+            }
+            break;
+
+        case AR6000_XIOCTL_BMI_READ_MEMORY:
+	     if (get_user(address, (unsigned int *)userdata) ||
+		get_user(length, (unsigned int *)userdata + 1)) {
+		ret = -EFAULT;
+		break;
+	    }
+
+            AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("Read Memory (address: 0x%x, length: %d)\n",
+                             address, length));
+            if ((buffer = (unsigned char *)A_MALLOC(length)) != NULL) {
+                A_MEMZERO(buffer, length);
+                ret = BMIReadMemory(hifDevice, address, buffer, length);
+                if (copy_to_user(rq->ifr_data, buffer, length)) {
+                    ret = -EFAULT;
+                }
+                A_FREE(buffer);
+            } else {
+                ret = -ENOMEM;
+            }
+            break;
+
+        case AR6000_XIOCTL_BMI_WRITE_MEMORY:
+	     if (get_user(address, (unsigned int *)userdata) ||
+		get_user(length, (unsigned int *)userdata + 1)) {
+		ret = -EFAULT;
+		break;
+	    }
+            AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("Write Memory (address: 0x%x, length: %d)\n",
+                             address, length));
+            if ((buffer = (unsigned char *)A_MALLOC(length)) != NULL) {
+                A_MEMZERO(buffer, length);
+                if (copy_from_user(buffer, &userdata[sizeof(address) +
+                                   sizeof(length)], length))
+                {
+                    ret = -EFAULT;
+                } else {
+                    ret = BMIWriteMemory(hifDevice, address, buffer, length);
+                }
+                A_FREE(buffer);
+            } else {
+                ret = -ENOMEM;
+            }
+            break;
+
+        case AR6000_XIOCTL_BMI_TEST:
+           AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("No longer supported\n"));
+           ret = -EOPNOTSUPP;
+           break;
+
+        case AR6000_XIOCTL_BMI_EXECUTE:
+	     if (get_user(address, (unsigned int *)userdata) ||
+		get_user(param, (unsigned int *)userdata + 1)) {
+		ret = -EFAULT;
+		break;
+	    }
+            AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("Execute (address: 0x%x, param: %d)\n",
+                             address, param));
+            ret = BMIExecute(hifDevice, address, (A_UINT32*)&param);
+	    /* return value */
+	    if (put_user(param, (unsigned int *)rq->ifr_data)) {
+		ret = -EFAULT;
+		break;
+	    }
+            break;
+
+        case AR6000_XIOCTL_BMI_SET_APP_START:
+	    if (get_user(address, (unsigned int *)userdata)) {
+		ret = -EFAULT;
+		break;
+	    }
+            AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("Set App Start (address: 0x%x)\n", address));
+            ret = BMISetAppStart(hifDevice, address);
+            break;
+
+        case AR6000_XIOCTL_BMI_READ_SOC_REGISTER:
+	    if (get_user(address, (unsigned int *)userdata)) {
+		ret = -EFAULT;
+		break;
+	    }
+            ret = BMIReadSOCRegister(hifDevice, address, (A_UINT32*)&param);
+	    /* return value */
+	    if (put_user(param, (unsigned int *)rq->ifr_data)) {
+		ret = -EFAULT;
+		break;
+	    }
+            break;
+
+        case AR6000_XIOCTL_BMI_WRITE_SOC_REGISTER:
+	    if (get_user(address, (unsigned int *)userdata) ||
+		get_user(param, (unsigned int *)userdata + 1)) {
+		ret = -EFAULT;
+		break;
+	    }
+            ret = BMIWriteSOCRegister(hifDevice, address, param);
+            break;
+
+#ifdef HTC_RAW_INTERFACE
+        case AR6000_XIOCTL_HTC_RAW_OPEN:
+            ret = A_OK;
+            if (!arRawIfEnabled(ar)) {
+                /* make sure block size is set in case the target was reset since last
+                  * BMI phase (i.e. flashup downloads) */
+                ret = ar6000_set_htc_params(ar->arHifDevice,
+                                            ar->arTargetType,
+                                            0,  /* use default yield */
+                                            0   /* use default number of HTC ctrl buffers */
+                                            );
+                if (A_FAILED(ret)) {
+                    break;
+                }
+                /* Terminate the BMI phase */
+                ret = BMIDone(hifDevice);
+                if (ret == A_OK) {
+                    ret = ar6000_htc_raw_open(ar);
+                }
+            }
+            break;
+
+        case AR6000_XIOCTL_HTC_RAW_CLOSE:
+            if (arRawIfEnabled(ar)) {
+                ret = ar6000_htc_raw_close(ar);
+                arRawIfEnabled(ar) = FALSE;
+            } else {
+                ret = A_ERROR;
+            }
+            break;
+
+        case AR6000_XIOCTL_HTC_RAW_READ:
+            if (arRawIfEnabled(ar)) {
+                unsigned int streamID;
+		if (get_user(streamID, (unsigned int *)userdata) ||
+		    get_user(length, (unsigned int *)userdata + 1)) {
+		    ret = -EFAULT;
+		    break;
+		}
+                buffer = (unsigned char*)rq->ifr_data + sizeof(length);
+                ret = ar6000_htc_raw_read(ar, (HTC_RAW_STREAM_ID)streamID,
+                                          (char*)buffer, length);
+		if (put_user(ret, (unsigned int *)rq->ifr_data)) {
+		    ret = -EFAULT;
+		    break;
+		}
+            } else {
+                ret = A_ERROR;
+            }
+            break;
+
+        case AR6000_XIOCTL_HTC_RAW_WRITE:
+            if (arRawIfEnabled(ar)) {
+                unsigned int streamID;
+		if (get_user(streamID, (unsigned int *)userdata) ||
+		    get_user(length, (unsigned int *)userdata + 1)) {
+		    ret = -EFAULT;
+		    break;
+		}
+                buffer = (unsigned char*)userdata + sizeof(streamID) + sizeof(length);
+                ret = ar6000_htc_raw_write(ar, (HTC_RAW_STREAM_ID)streamID,
+                                           (char*)buffer, length);
+		if (put_user(ret, (unsigned int *)rq->ifr_data)) {
+		    ret = -EFAULT;
+		    break;
+		}
+            } else {
+                ret = A_ERROR;
+            }
+            break;
+#endif /* HTC_RAW_INTERFACE */
+
+        case AR6000_XIOCTL_BMI_LZ_STREAM_START:
+	    if (get_user(address, (unsigned int *)userdata)) {
+		ret = -EFAULT;
+		break;
+	    }
+            AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("Start Compressed Stream (address: 0x%x)\n", address));
+            ret = BMILZStreamStart(hifDevice, address);
+            break;
+
+        case AR6000_XIOCTL_BMI_LZ_DATA:
+	    if (get_user(length, (unsigned int *)userdata)) {
+		ret = -EFAULT;
+		break;
+	    }
+            AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("Send Compressed Data (length: %d)\n", length));
+            if ((buffer = (unsigned char *)A_MALLOC(length)) != NULL) {
+                A_MEMZERO(buffer, length);
+                if (copy_from_user(buffer, &userdata[sizeof(length)], length))
+                {
+                    ret = -EFAULT;
+                } else {
+                    ret = BMILZData(hifDevice, buffer, length);
+                }
+                A_FREE(buffer);
+            } else {
+                ret = -ENOMEM;
+            }
+            break;
+
+#if defined(CONFIG_TARGET_PROFILE_SUPPORT)
+        /*
+         * Optional support for Target-side profiling.
+         * Not needed in production.
+         */
+
+        /* Configure Target-side profiling */
+        case AR6000_XIOCTL_PROF_CFG:
+        {
+            A_UINT32 period;
+            A_UINT32 nbins;
+	    if (get_user(period, (unsigned int *)userdata) ||
+		get_user(nbins, (unsigned int *)userdata + 1)) {
+		ret = -EFAULT;
+		break;
+	    }
+
+            if (wmi_prof_cfg_cmd(ar->arWmi, period, nbins) != A_OK) {
+                ret = -EIO;
+            }
+
+            break;
+        }
+
+        /* Start a profiling bucket/bin at the specified address */
+        case AR6000_XIOCTL_PROF_ADDR_SET:
+        {
+            A_UINT32 addr;
+	    if (get_user(addr, (unsigned int *)userdata)) {
+		ret = -EFAULT;
+		break;
+	    }
+
+            if (wmi_prof_addr_set_cmd(ar->arWmi, addr) != A_OK) {
+                ret = -EIO;
+            }
+
+            break;
+        }
+
+        /* START Target-side profiling */
+        case AR6000_XIOCTL_PROF_START:
+            wmi_prof_start_cmd(ar->arWmi);
+            break;
+
+        /* STOP Target-side profiling */
+        case AR6000_XIOCTL_PROF_STOP:
+            wmi_prof_stop_cmd(ar->arWmi);
+            break;
+        case AR6000_XIOCTL_PROF_COUNT_GET:
+        {
+            if (ar->bIsDestroyProgress) {
+                ret = -EBUSY;
+                goto ioctl_done;
+            }
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+                goto ioctl_done;
+            }
+            if (down_interruptible(&ar->arSem)) {
+                ret = -ERESTARTSYS;
+                goto ioctl_done;
+            }
+            if (ar->bIsDestroyProgress) {
+                up(&ar->arSem);
+                ret = -EBUSY;
+                goto ioctl_done;
+            }
+
+            prof_count_available = FALSE;
+            ret = prof_count_get(dev);
+            if (ret != A_OK) {
+                up(&ar->arSem);
+                ret = -EIO;
+                goto ioctl_done;
+            }
+
+            /* Wait for Target to respond. */
+            wait_event_interruptible(arEvent, prof_count_available);
+            if (signal_pending(current)) {
+                ret = -EINTR;
+            } else {
+                if (copy_to_user(userdata, &prof_count_results,
+                                 sizeof(prof_count_results)))
+                {
+                    ret = -EFAULT;
+                }
+            }
+            up(&ar->arSem);
+            break;
+        }
+#endif /* CONFIG_TARGET_PROFILE_SUPPORT */
+
+        case AR6000_IOCTL_WMI_GETREV:
+        {
+            if (copy_to_user(rq->ifr_data, &ar->arVersion,
+                             sizeof(ar->arVersion)))
+            {
+                ret = -EFAULT;
+            }
+            break;
+        }
+        case AR6000_IOCTL_WMI_SETPWR:
+        {
+            WMI_POWER_MODE_CMD pwrModeCmd;
+
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&pwrModeCmd, userdata,
+                                   sizeof(pwrModeCmd)))
+            {
+                ret = -EFAULT;
+            } else {
+                if (wmi_powermode_cmd(ar->arWmi, pwrModeCmd.powerMode)
+                       != A_OK)
+                {
+                    ret = -EIO;
+                }
+            }
+            break;
+        }
+        case AR6000_IOCTL_WMI_SET_IBSS_PM_CAPS:
+        {
+            WMI_IBSS_PM_CAPS_CMD ibssPmCaps;
+
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&ibssPmCaps, userdata,
+                                   sizeof(ibssPmCaps)))
+            {
+                ret = -EFAULT;
+            } else {
+                if (wmi_ibsspmcaps_cmd(ar->arWmi, ibssPmCaps.power_saving, ibssPmCaps.ttl,
+                    ibssPmCaps.atim_windows, ibssPmCaps.timeout_value) != A_OK)
+                {
+                    ret = -EIO;
+                }
+                AR6000_SPIN_LOCK(&ar->arLock, 0);
+                ar->arIbssPsEnable = ibssPmCaps.power_saving;
+                AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+            }
+            break;
+        }
+        case AR6000_XIOCTL_WMI_SET_AP_PS:
+        {
+            WMI_AP_PS_CMD apPsCmd;
+
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&apPsCmd, userdata,
+                                   sizeof(apPsCmd)))
+            {
+                ret = -EFAULT;
+            } else {
+                if (wmi_apps_cmd(ar->arWmi, apPsCmd.psType, apPsCmd.idle_time,
+                    apPsCmd.ps_period, apPsCmd.sleep_period) != A_OK)
+                {
+                    ret = -EIO;
+                }
+            }
+            break;
+        }
+        case AR6000_IOCTL_WMI_SET_PMPARAMS:
+        {
+            WMI_POWER_PARAMS_CMD pmParams;
+
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&pmParams, userdata,
+                                      sizeof(pmParams)))
+            {
+                ret = -EFAULT;
+            } else {
+                if (wmi_pmparams_cmd(ar->arWmi, pmParams.idle_period,
+                                     pmParams.pspoll_number,
+                                     pmParams.dtim_policy,
+                                     pmParams.tx_wakeup_policy,
+                                     pmParams.num_tx_to_wakeup,
+#if WLAN_CONFIG_IGNORE_POWER_SAVE_FAIL_EVENT_DURING_SCAN
+                                     IGNORE_POWER_SAVE_FAIL_EVENT_DURING_SCAN 
+#else
+                                     SEND_POWER_SAVE_FAIL_EVENT_ALWAYS
+#endif
+                                     ) != A_OK)
+                {
+                    ret = -EIO;
+                }
+            }
+            break;
+        }
+        case AR6000_IOCTL_WMI_SETSCAN:
+        {
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&ar->scParams, userdata,
+                                      sizeof(ar->scParams)))
+            {
+                ret = -EFAULT;
+            } else {
+                if (CAN_SCAN_IN_CONNECT(ar->scParams.scanCtrlFlags)) {
+                    ar->arSkipScan = FALSE;
+                } else {
+                    ar->arSkipScan = TRUE;
+                }
+
+                if (wmi_scanparams_cmd(ar->arWmi, ar->scParams.fg_start_period,
+                                       ar->scParams.fg_end_period,
+                                       ar->scParams.bg_period,
+                                       ar->scParams.minact_chdwell_time,
+                                       ar->scParams.maxact_chdwell_time,
+                                       ar->scParams.pas_chdwell_time,
+                                       ar->scParams.shortScanRatio,
+                                       ar->scParams.scanCtrlFlags,
+                                       ar->scParams.max_dfsch_act_time,
+                                       ar->scParams.maxact_scan_per_ssid) != A_OK)
+                {
+                    ret = -EIO;
+                }
+            }
+            break;
+        }
+        case AR6000_IOCTL_WMI_SETLISTENINT:
+        {
+            WMI_LISTEN_INT_CMD listenCmd;
+
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&listenCmd, userdata,
+                                      sizeof(listenCmd)))
+            {
+                ret = -EFAULT;
+            } else {
+                    if (wmi_listeninterval_cmd(ar->arWmi, listenCmd.listenInterval, listenCmd.numBeacons) != A_OK) {
+                        ret = -EIO;
+                    } else {
+                        AR6000_SPIN_LOCK(&ar->arLock, 0);
+                        ar->arListenIntervalT = listenCmd.listenInterval;
+                        ar->arListenIntervalB = listenCmd.numBeacons;
+                        AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+                    }
+
+                }
+            break;
+        }
+        case AR6000_IOCTL_WMI_SET_BMISS_TIME:
+        {
+            WMI_BMISS_TIME_CMD bmissCmd;
+
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&bmissCmd, userdata,
+                                      sizeof(bmissCmd)))
+            {
+                ret = -EFAULT;
+            } else {
+                if (wmi_bmisstime_cmd(ar->arWmi, bmissCmd.bmissTime, bmissCmd.numBeacons) != A_OK) {
+                    ret = -EIO;
+                }
+            }
+            break;
+        }
+        case AR6000_IOCTL_WMI_SETBSSFILTER:
+        {
+            WMI_BSS_FILTER_CMD filt;
+
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&filt, userdata,
+                                   sizeof(filt)))
+            {
+                ret = -EFAULT;
+            } else {
+                if (wmi_bssfilter_cmd(ar->arWmi, filt.bssFilter, filt.ieMask)
+                        != A_OK) {
+                    ret = -EIO;
+                } else {
+                    ar->arUserBssFilter = param;
+                }
+            }
+            break;
+        }
+
+        case AR6000_IOCTL_WMI_SET_SNRTHRESHOLD:
+        {
+            ret = ar6000_ioctl_set_snr_threshold(dev, rq);
+            break;
+        }
+        case AR6000_XIOCTL_WMI_SET_RSSITHRESHOLD:
+        {
+            ret = ar6000_ioctl_set_rssi_threshold(dev, rq);
+            break;
+        }
+        case AR6000_XIOCTL_WMI_CLR_RSSISNR:
+        {
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            }
+            ret = wmi_clr_rssi_snr(ar->arWmi);
+            break;
+        }
+        case AR6000_XIOCTL_WMI_SET_LQTHRESHOLD:
+        {
+            ret = ar6000_ioctl_set_lq_threshold(dev, rq);
+            break;
+        }
+        case AR6000_XIOCTL_WMI_SET_LPREAMBLE:
+        {
+            WMI_SET_LPREAMBLE_CMD setLpreambleCmd;
+
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&setLpreambleCmd, userdata,
+                                   sizeof(setLpreambleCmd)))
+            {
+                ret = -EFAULT;
+            } else {
+                if (wmi_set_lpreamble_cmd(ar->arWmi, setLpreambleCmd.status,
+#if WLAN_CONFIG_DONOT_IGNORE_BARKER_IN_ERP 
+                           WMI_DONOT_IGNORE_BARKER_IN_ERP
+#else
+                           WMI_IGNORE_BARKER_IN_ERP
+#endif
+                ) != A_OK)
+                {
+                    ret = -EIO;
+                }
+            }
+
+            break;
+        }
+        case AR6000_XIOCTL_WMI_SET_RTS:
+        {
+            WMI_SET_RTS_CMD rtsCmd;
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&rtsCmd, userdata,
+                                   sizeof(rtsCmd)))
+            {
+                ret = -EFAULT;
+            } else {
+                ar->arRTS = rtsCmd.threshold;
+                if (wmi_set_rts_cmd(ar->arWmi, rtsCmd.threshold)
+                       != A_OK)
+                {
+                    ret = -EIO;
+                }
+            }
+
+            break;
+        }
+        case AR6000_XIOCTL_WMI_SET_WMM:
+        {
+            ret = ar6000_ioctl_set_wmm(dev, rq);
+            break;
+        }
+       case AR6000_XIOCTL_WMI_SET_QOS_SUPP:
+        {
+            ret = ar6000_ioctl_set_qos_supp(dev, rq);
+            break;
+        }
+        case AR6000_XIOCTL_WMI_SET_TXOP:
+        {
+            ret = ar6000_ioctl_set_txop(dev, rq);
+            break;
+        }
+        case AR6000_XIOCTL_WMI_GET_RD:
+        {
+            ret = ar6000_ioctl_get_rd(dev, rq);
+            break;
+        }
+        case AR6000_IOCTL_WMI_SET_CHANNELPARAMS:
+        {
+            ret = ar6000_ioctl_set_channelParams(dev, rq);
+            break;
+        }
+        case AR6000_IOCTL_WMI_SET_PROBEDSSID:
+        {
+            ret = ar6000_ioctl_set_probedSsid(dev, rq);
+            break;
+        }
+        case AR6000_IOCTL_WMI_SET_BADAP:
+        {
+            ret = ar6000_ioctl_set_badAp(dev, rq);
+            break;
+        }
+        case AR6000_IOCTL_WMI_CREATE_QOS:
+        {
+            ret = ar6000_ioctl_create_qos(dev, rq);
+            break;
+        }
+        case AR6000_IOCTL_WMI_DELETE_QOS:
+        {
+            ret = ar6000_ioctl_delete_qos(dev, rq);
+            break;
+        }
+        case AR6000_IOCTL_WMI_GET_QOS_QUEUE:
+        {
+            ret = ar6000_ioctl_get_qos_queue(dev, rq);
+            break;
+        }
+        case AR6000_IOCTL_WMI_GET_TARGET_STATS:
+        {
+            ret = ar6000_ioctl_get_target_stats(dev, rq);
+            break;
+        }
+        case AR6000_IOCTL_WMI_SET_ERROR_REPORT_BITMASK:
+        {
+            ret = ar6000_ioctl_set_error_report_bitmask(dev, rq);
+            break;
+        }
+        case AR6000_IOCTL_WMI_SET_ASSOC_INFO:
+        {
+            WMI_SET_ASSOC_INFO_CMD cmd;
+            A_UINT8 assocInfo[WMI_MAX_ASSOC_INFO_LEN];
+
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+		break;
+	    }
+
+	    if (get_user(cmd.ieType, userdata)) {
+		ret = -EFAULT;
+		break;
+	    }
+	    if (cmd.ieType >= WMI_MAX_ASSOC_INFO_TYPE) {
+		ret = -EIO;
+		break;
+	    }
+
+	    if (get_user(cmd.bufferSize, userdata + 1) ||
+		(cmd.bufferSize > WMI_MAX_ASSOC_INFO_LEN) ||
+		copy_from_user(assocInfo, userdata + 2, cmd.bufferSize)) {
+		ret = -EFAULT;
+		break;
+	    }
+	    if (wmi_associnfo_cmd(ar->arWmi, cmd.ieType,
+				  cmd.bufferSize, assocInfo) != A_OK) {
+		ret = -EIO;
+		break;
+	    }
+            break;
+        }
+        case AR6000_IOCTL_WMI_SET_ACCESS_PARAMS:
+        {
+            ret = ar6000_ioctl_set_access_params(dev, rq);
+            break;
+        }
+        case AR6000_IOCTL_WMI_SET_DISC_TIMEOUT:
+        {
+            ret = ar6000_ioctl_set_disconnect_timeout(dev, rq);
+            break;
+        }
+        case AR6000_XIOCTL_FORCE_TARGET_RESET:
+        {
+            if (ar->arHtcTarget)
+            {
+//                HTCForceReset(htcTarget);
+            }
+            else
+            {
+                AR_DEBUG_PRINTF(ATH_DEBUG_WARN,("ar6000_ioctl cannot attempt reset.\n"));
+            }
+            break;
+        }
+        case AR6000_XIOCTL_TARGET_INFO:
+        case AR6000_XIOCTL_CHECK_TARGET_READY: /* backwards compatibility */
+        {
+            /* If we made it to here, then the Target exists and is ready. */
+
+            if (cmd == AR6000_XIOCTL_TARGET_INFO) {
+                if (copy_to_user((A_UINT32 *)rq->ifr_data, &ar->arVersion.target_ver,
+                                 sizeof(ar->arVersion.target_ver)))
+                {
+                    ret = -EFAULT;
+                }
+                if (copy_to_user(((A_UINT32 *)rq->ifr_data)+1, &ar->arTargetType,
+                                 sizeof(ar->arTargetType)))
+                {
+                    ret = -EFAULT;
+                }
+            }
+            break;
+        }
+        case AR6000_XIOCTL_WMI_SET_HB_CHALLENGE_RESP_PARAMS:
+        {
+            WMI_SET_HB_CHALLENGE_RESP_PARAMS_CMD hbparam;
+
+            if (copy_from_user(&hbparam, userdata, sizeof(hbparam)))
+            {
+                ret = -EFAULT;
+            } else {
+                AR6000_SPIN_LOCK(&ar->arLock, 0);
+                /* Start a cyclic timer with the parameters provided. */
+                if (hbparam.frequency) {
+                    ar->arHBChallengeResp.frequency = hbparam.frequency;
+                }
+                if (hbparam.threshold) {
+                    ar->arHBChallengeResp.missThres = hbparam.threshold;
+                }
+
+                /* Delete the pending timer and start a new one */
+                if (timer_pending(&ar->arHBChallengeResp.timer)) {
+                    A_UNTIMEOUT(&ar->arHBChallengeResp.timer);
+                }
+                A_TIMEOUT_MS(&ar->arHBChallengeResp.timer, ar->arHBChallengeResp.frequency * 1000, 0);
+                AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+            }
+            break;
+        }
+        case AR6000_XIOCTL_WMI_GET_HB_CHALLENGE_RESP:
+        {
+            A_UINT32 cookie;
+
+            if (copy_from_user(&cookie, userdata, sizeof(cookie))) {
+                ret = -EFAULT;
+                goto ioctl_done;
+            }
+
+            /* Send the challenge on the control channel */
+            if (wmi_get_challenge_resp_cmd(ar->arWmi, cookie, APP_HB_CHALLENGE) != A_OK) {
+                ret = -EIO;
+                goto ioctl_done;
+            }
+            break;
+        }
+#ifdef USER_KEYS
+        case AR6000_XIOCTL_USER_SETKEYS:
+        {
+
+            ar->user_savedkeys_stat = USER_SAVEDKEYS_STAT_RUN;
+
+            if (copy_from_user(&ar->user_key_ctrl, userdata,
+                               sizeof(ar->user_key_ctrl)))
+            {
+                ret = -EFAULT;
+                goto ioctl_done;
+            }
+
+            A_PRINTF("ar6000 USER set key %x\n", ar->user_key_ctrl);
+            break;
+        }
+#endif /* USER_KEYS */
+
+#ifdef CONFIG_HOST_GPIO_SUPPORT
+        case AR6000_XIOCTL_GPIO_OUTPUT_SET:
+        {
+            struct ar6000_gpio_output_set_cmd_s gpio_output_set_cmd;
+
+            if (ar->bIsDestroyProgress) {
+                ret = -EBUSY;
+                goto ioctl_done;
+            }
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+                goto ioctl_done;
+            }
+            if (down_interruptible(&ar->arSem)) {
+                ret = -ERESTARTSYS;
+                goto ioctl_done;
+            }
+            if (ar->bIsDestroyProgress) {
+                up(&ar->arSem);
+                ret = -EBUSY;
+                goto ioctl_done;
+            }
+
+            if (copy_from_user(&gpio_output_set_cmd, userdata,
+                                sizeof(gpio_output_set_cmd)))
+            {
+                ret = -EFAULT;
+            } else {
+                ret = ar6000_gpio_output_set(dev,
+                                             gpio_output_set_cmd.set_mask,
+                                             gpio_output_set_cmd.clear_mask,
+                                             gpio_output_set_cmd.enable_mask,
+                                             gpio_output_set_cmd.disable_mask);
+                if (ret != A_OK) {
+                    ret = EIO;
+                }
+            }
+            up(&ar->arSem);
+            break;
+        }
+        case AR6000_XIOCTL_GPIO_INPUT_GET:
+        {
+            if (ar->bIsDestroyProgress) {
+                ret = -EBUSY;
+                goto ioctl_done;
+            }
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+                goto ioctl_done;
+            }
+            if (down_interruptible(&ar->arSem)) {
+                ret = -ERESTARTSYS;
+                goto ioctl_done;
+            }
+            if (ar->bIsDestroyProgress) {
+                up(&ar->arSem);
+                ret = -EBUSY;
+                goto ioctl_done;
+            }
+
+            ret = ar6000_gpio_input_get(dev);
+            if (ret != A_OK) {
+                up(&ar->arSem);
+                ret = -EIO;
+                goto ioctl_done;
+            }
+
+            /* Wait for Target to respond. */
+            wait_event_interruptible(arEvent, gpio_data_available);
+            if (signal_pending(current)) {
+                ret = -EINTR;
+            } else {
+                A_ASSERT(gpio_reg_results.gpioreg_id == GPIO_ID_NONE);
+
+                if (copy_to_user(userdata, &gpio_reg_results.value,
+                                 sizeof(gpio_reg_results.value)))
+                {
+                    ret = -EFAULT;
+                }
+            }
+            up(&ar->arSem);
+            break;
+        }
+        case AR6000_XIOCTL_GPIO_REGISTER_SET:
+        {
+            struct ar6000_gpio_register_cmd_s gpio_register_cmd;
+
+            if (ar->bIsDestroyProgress) {
+                ret = -EBUSY;
+                goto ioctl_done;
+            }
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+                goto ioctl_done;
+            }
+            if (down_interruptible(&ar->arSem)) {
+                ret = -ERESTARTSYS;
+                goto ioctl_done;
+            }
+            if (ar->bIsDestroyProgress) {
+                up(&ar->arSem);
+                ret = -EBUSY;
+                goto ioctl_done;
+            }
+
+            if (copy_from_user(&gpio_register_cmd, userdata,
+                                sizeof(gpio_register_cmd)))
+            {
+                ret = -EFAULT;
+            } else {
+                ret = ar6000_gpio_register_set(dev,
+                                               gpio_register_cmd.gpioreg_id,
+                                               gpio_register_cmd.value);
+                if (ret != A_OK) {
+                    ret = EIO;
+                }
+
+                /* Wait for acknowledgement from Target */
+                wait_event_interruptible(arEvent, gpio_ack_received);
+                if (signal_pending(current)) {
+                    ret = -EINTR;
+                }
+            }
+            up(&ar->arSem);
+            break;
+        }
+        case AR6000_XIOCTL_GPIO_REGISTER_GET:
+        {
+            struct ar6000_gpio_register_cmd_s gpio_register_cmd;
+
+            if (ar->bIsDestroyProgress) {
+                ret = -EBUSY;
+                goto ioctl_done;
+            }
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+                goto ioctl_done;
+            }
+            if (down_interruptible(&ar->arSem)) {
+                ret = -ERESTARTSYS;
+                goto ioctl_done;
+            }
+            if (ar->bIsDestroyProgress) {
+                up(&ar->arSem);
+                ret = -EBUSY;
+                goto ioctl_done;
+            }
+
+            if (copy_from_user(&gpio_register_cmd, userdata,
+                                sizeof(gpio_register_cmd)))
+            {
+                ret = -EFAULT;
+            } else {
+                ret = ar6000_gpio_register_get(dev, gpio_register_cmd.gpioreg_id);
+                if (ret != A_OK) {
+                    up(&ar->arSem);
+                    ret = -EIO;
+                    goto ioctl_done;
+                }
+
+                /* Wait for Target to respond. */
+                wait_event_interruptible(arEvent, gpio_data_available);
+                if (signal_pending(current)) {
+                    ret = -EINTR;
+                } else {
+                    A_ASSERT(gpio_register_cmd.gpioreg_id == gpio_reg_results.gpioreg_id);
+                    if (copy_to_user(userdata, &gpio_reg_results,
+                                     sizeof(gpio_reg_results)))
+                    {
+                        ret = -EFAULT;
+                    }
+                }
+            }
+            up(&ar->arSem);
+            break;
+        }
+        case AR6000_XIOCTL_GPIO_INTR_ACK:
+        {
+            struct ar6000_gpio_intr_ack_cmd_s gpio_intr_ack_cmd;
+
+            if (ar->bIsDestroyProgress) {
+                ret = -EBUSY;
+                goto ioctl_done;
+            }
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+                goto ioctl_done;
+            }
+            if (down_interruptible(&ar->arSem)) {
+                ret = -ERESTARTSYS;
+                goto ioctl_done;
+            }
+            if (ar->bIsDestroyProgress) {
+                up(&ar->arSem);
+                ret = -EBUSY;
+                goto ioctl_done;
+            }
+
+            if (copy_from_user(&gpio_intr_ack_cmd, userdata,
+                                sizeof(gpio_intr_ack_cmd)))
+            {
+                ret = -EFAULT;
+            } else {
+                ret = ar6000_gpio_intr_ack(dev, gpio_intr_ack_cmd.ack_mask);
+                if (ret != A_OK) {
+                    ret = EIO;
+                }
+            }
+            up(&ar->arSem);
+            break;
+        }
+        case AR6000_XIOCTL_GPIO_INTR_WAIT:
+        {
+            /* Wait for Target to report an interrupt. */
+            wait_event_interruptible(arEvent, gpio_intr_available);
+
+            if (signal_pending(current)) {
+                ret = -EINTR;
+            } else {
+                if (copy_to_user(userdata, &gpio_intr_results,
+                                 sizeof(gpio_intr_results)))
+                {
+                    ret = -EFAULT;
+                }
+            }
+            break;
+        }
+#endif /* CONFIG_HOST_GPIO_SUPPORT */
+
+        case AR6000_XIOCTL_DBGLOG_CFG_MODULE:
+        {
+            struct ar6000_dbglog_module_config_s config;
+
+            if (copy_from_user(&config, userdata, sizeof(config))) {
+                ret = -EFAULT;
+                goto ioctl_done;
+            }
+
+            /* Send the challenge on the control channel */
+            if (wmi_config_debug_module_cmd(ar->arWmi, config.mmask,
+                                            config.tsr, config.rep,
+                                            config.size, config.valid) != A_OK)
+            {
+                ret = -EIO;
+                goto ioctl_done;
+            }
+            break;
+        }
+
+        case AR6000_XIOCTL_DBGLOG_GET_DEBUG_LOGS:
+        {
+            /* Send the challenge on the control channel */
+            if (ar6000_dbglog_get_debug_logs(ar) != A_OK)
+            {
+                ret = -EIO;
+                goto ioctl_done;
+            }
+            break;
+        }
+
+        case AR6000_XIOCTL_SET_ADHOC_BSSID:
+        {
+            WMI_SET_ADHOC_BSSID_CMD adhocBssid;
+
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&adhocBssid, userdata,
+                                      sizeof(adhocBssid)))
+            {
+                ret = -EFAULT;
+            } else if (A_MEMCMP(adhocBssid.bssid, bcast_mac,
+                                AR6000_ETH_ADDR_LEN) == 0)
+            {
+                ret = -EFAULT;
+            } else {
+
+                A_MEMCPY(ar->arReqBssid, adhocBssid.bssid, sizeof(ar->arReqBssid));
+        }
+            break;
+        }
+
+        case AR6000_XIOCTL_SET_OPT_MODE:
+        {
+        WMI_SET_OPT_MODE_CMD optModeCmd;
+            AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&optModeCmd, userdata,
+                                      sizeof(optModeCmd)))
+            {
+                ret = -EFAULT;
+            } else if (ar->arConnected && optModeCmd.optMode == SPECIAL_ON) {
+                ret = -EFAULT;
+
+            } else if (wmi_set_opt_mode_cmd(ar->arWmi, optModeCmd.optMode)
+                       != A_OK)
+            {
+                ret = -EIO;
+            }
+            break;
+        }
+
+        case AR6000_XIOCTL_OPT_SEND_FRAME:
+        {
+        WMI_OPT_TX_FRAME_CMD optTxFrmCmd;
+            A_UINT8 data[MAX_OPT_DATA_LEN];
+
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&optTxFrmCmd, userdata,
+                                      sizeof(optTxFrmCmd)))
+            {
+                ret = -EFAULT;
+            } else if (copy_from_user(data,
+                                      userdata+sizeof(WMI_OPT_TX_FRAME_CMD)-1,
+                                      optTxFrmCmd.optIEDataLen))
+            {
+                ret = -EFAULT;
+            } else {
+                ret = wmi_opt_tx_frame_cmd(ar->arWmi,
+                                           optTxFrmCmd.frmType,
+                                           optTxFrmCmd.dstAddr,
+                                           optTxFrmCmd.bssid,
+                                           optTxFrmCmd.optIEDataLen,
+                                           data);
+            }
+
+            break;
+        }
+        case AR6000_XIOCTL_WMI_SETRETRYLIMITS:
+        {
+            WMI_SET_RETRY_LIMITS_CMD setRetryParams;
+
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&setRetryParams, userdata,
+                                      sizeof(setRetryParams)))
+            {
+                ret = -EFAULT;
+            } else {
+                if (wmi_set_retry_limits_cmd(ar->arWmi, setRetryParams.frameType,
+                                          setRetryParams.trafficClass,
+                                          setRetryParams.maxRetries,
+                                          setRetryParams.enableNotify) != A_OK)
+                {
+                    ret = -EIO;
+                }
+                AR6000_SPIN_LOCK(&ar->arLock, 0);
+                ar->arMaxRetries = setRetryParams.maxRetries;
+                AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+            }
+            break;
+        }
+
+        case AR6000_XIOCTL_SET_BEACON_INTVAL:
+        {
+            WMI_BEACON_INT_CMD bIntvlCmd;
+
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&bIntvlCmd, userdata,
+                       sizeof(bIntvlCmd)))
+            {
+                ret = -EFAULT;
+            } else if (wmi_set_adhoc_bconIntvl_cmd(ar->arWmi, bIntvlCmd.beaconInterval)
+                        != A_OK)
+            {
+                ret = -EIO;
+            }
+            if(ret == 0) {
+                ar->ap_beacon_interval = bIntvlCmd.beaconInterval;
+                ar->ap_profile_flag = 1; /* There is a change in profile */
+            }
+            break;
+        }
+        case IEEE80211_IOCTL_SETAUTHALG:
+        {
+            AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+            struct ieee80211req_authalg req;
+
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&req, userdata,
+                       sizeof(struct ieee80211req_authalg)))
+            {
+                ret = -EFAULT;
+            } else {
+                if (req.auth_alg & AUTH_ALG_OPEN_SYSTEM) {
+                    ar->arDot11AuthMode  |= OPEN_AUTH;
+                    ar->arPairwiseCrypto  = NONE_CRYPT;
+                    ar->arGroupCrypto     = NONE_CRYPT;
+                }
+                if (req.auth_alg & AUTH_ALG_SHARED_KEY) {
+                    ar->arDot11AuthMode  |= SHARED_AUTH;
+                    ar->arPairwiseCrypto  = WEP_CRYPT;
+                    ar->arGroupCrypto     = WEP_CRYPT;
+                    ar->arAuthMode        = NONE_AUTH;
+                }
+                if (req.auth_alg == AUTH_ALG_LEAP) {
+                    ar->arDot11AuthMode   = LEAP_AUTH;
+                }
+            }
+            break;
+        }
+
+        case AR6000_XIOCTL_SET_VOICE_PKT_SIZE:
+            ret = ar6000_xioctl_set_voice_pkt_size(dev, userdata);
+            break;
+
+        case AR6000_XIOCTL_SET_MAX_SP:
+            ret = ar6000_xioctl_set_max_sp_len(dev, userdata);
+            break;
+
+        case AR6000_XIOCTL_WMI_GET_ROAM_TBL:
+            ret = ar6000_ioctl_get_roam_tbl(dev, rq);
+            break;
+        case AR6000_XIOCTL_WMI_SET_ROAM_CTRL:
+            ret = ar6000_ioctl_set_roam_ctrl(dev, userdata);
+            break;
+        case AR6000_XIOCTRL_WMI_SET_POWERSAVE_TIMERS:
+            ret = ar6000_ioctl_set_powersave_timers(dev, userdata);
+            break;
+        case AR6000_XIOCTRL_WMI_GET_POWER_MODE:
+            ret = ar6000_ioctl_get_power_mode(dev, rq);
+            break;
+        case AR6000_XIOCTRL_WMI_SET_WLAN_STATE:
+        {
+            AR6000_WLAN_STATE state;
+	    if (get_user(state, (unsigned int *)userdata))
+		ret = -EFAULT;
+	    else if (ar6000_set_wlan_state(ar, state) != A_OK)
+                ret = -EIO;
+            break;
+        }
+        case AR6000_XIOCTL_WMI_GET_ROAM_DATA:
+            ret = ar6000_ioctl_get_roam_data(dev, rq);
+            break;
+
+        case AR6000_XIOCTL_WMI_SET_BT_STATUS:
+            ret = ar6000_xioctl_set_bt_status_cmd(dev, userdata);
+            break;
+
+        case AR6000_XIOCTL_WMI_SET_BT_PARAMS:
+            ret = ar6000_xioctl_set_bt_params_cmd(dev, userdata);
+            break;
+
+		case AR6000_XIOCTL_WMI_SET_BTCOEX_FE_ANT:
+			ret = ar6000_xioctl_set_btcoex_fe_ant_cmd(dev, userdata);
+			break;
+
+		case AR6000_XIOCTL_WMI_SET_BTCOEX_COLOCATED_BT_DEV:
+			ret = ar6000_xioctl_set_btcoex_colocated_bt_dev_cmd(dev, userdata);
+			break;
+
+		case AR6000_XIOCTL_WMI_SET_BTCOEX_BTINQUIRY_PAGE_CONFIG:
+			ret = ar6000_xioctl_set_btcoex_btinquiry_page_config_cmd(dev, userdata);
+			break;
+
+		case AR6000_XIOCTL_WMI_SET_BTCOEX_SCO_CONFIG:
+			ret = ar6000_xioctl_set_btcoex_sco_config_cmd( dev, userdata);
+			break;
+
+		case AR6000_XIOCTL_WMI_SET_BTCOEX_A2DP_CONFIG:
+			ret = ar6000_xioctl_set_btcoex_a2dp_config_cmd(dev, userdata);
+			break;
+
+		case AR6000_XIOCTL_WMI_SET_BTCOEX_ACLCOEX_CONFIG:
+			ret = ar6000_xioctl_set_btcoex_aclcoex_config_cmd(dev, userdata);
+			break;
+
+		case AR6000_XIOCTL_WMI_SET_BTCOEX_DEBUG:
+			ret = ar60000_xioctl_set_btcoex_debug_cmd(dev, userdata);
+			break;
+
+		case AR6000_XIOCTL_WMI_SET_BT_OPERATING_STATUS:
+			ret = ar6000_xioctl_set_btcoex_bt_operating_status_cmd(dev, userdata);
+			break;
+
+		case AR6000_XIOCTL_WMI_GET_BTCOEX_CONFIG:
+			ret = ar6000_xioctl_get_btcoex_config_cmd(dev, userdata, rq);
+			break;
+
+		case AR6000_XIOCTL_WMI_GET_BTCOEX_STATS:
+			ret = ar6000_xioctl_get_btcoex_stats_cmd(dev, userdata, rq);
+			break;
+
+        case AR6000_XIOCTL_WMI_STARTSCAN:
+        {
+            WMI_START_SCAN_CMD setStartScanCmd, *cmdp;
+
+            if (ar->arWmiReady == FALSE) {
+                    ret = -EIO;
+                } else if (copy_from_user(&setStartScanCmd, userdata,
+                                          sizeof(setStartScanCmd)))
+                {
+                    ret = -EFAULT;
+                } else {
+                    if (setStartScanCmd.numChannels > 1) {
+                        cmdp = A_MALLOC(130);
+                        if (copy_from_user(cmdp, userdata,
+                                           sizeof (*cmdp) +
+                                           ((setStartScanCmd.numChannels - 1) *
+                                           sizeof(A_UINT16))))
+                        {
+                            kfree(cmdp);
+                            ret = -EFAULT;
+                            goto ioctl_done;
+                        }
+                    } else {
+                        cmdp = &setStartScanCmd;
+                    }
+
+                    if (wmi_startscan_cmd(ar->arWmi, cmdp->scanType,
+                                          cmdp->forceFgScan,
+                                          cmdp->isLegacy,
+                                          cmdp->homeDwellTime,
+                                          cmdp->forceScanInterval,
+                                          cmdp->numChannels,
+                                          cmdp->channelList) != A_OK)
+                    {
+                        ret = -EIO;
+                    }
+                }
+            break;
+        }
+        case AR6000_XIOCTL_WMI_SETFIXRATES:
+        {
+            WMI_FIX_RATES_CMD setFixRatesCmd;
+            A_STATUS returnStatus;
+
+            if (ar->arWmiReady == FALSE) {
+                    ret = -EIO;
+                } else if (copy_from_user(&setFixRatesCmd, userdata,
+                                          sizeof(setFixRatesCmd)))
+                {
+                    ret = -EFAULT;
+                } else {
+                    returnStatus = wmi_set_fixrates_cmd(ar->arWmi, setFixRatesCmd.fixRateMask);
+                    if (returnStatus == A_EINVAL) {
+                        ret = -EINVAL;
+                    } else if(returnStatus != A_OK) {
+                        ret = -EIO;
+                    } else {
+                        ar->ap_profile_flag = 1; /* There is a change in profile */
+                    }
+                }
+            break;
+        }
+
+        case AR6000_XIOCTL_WMI_GETFIXRATES:
+        {
+            WMI_FIX_RATES_CMD getFixRatesCmd;
+            AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+            int ret = 0;
+
+            if (ar->bIsDestroyProgress) {
+                ret = -EBUSY;
+                goto ioctl_done;
+            }
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+                goto ioctl_done;
+            }
+
+            if (down_interruptible(&ar->arSem)) {
+                ret = -ERESTARTSYS;
+                goto ioctl_done;
+            }
+            if (ar->bIsDestroyProgress) {
+                up(&ar->arSem);
+                ret = -EBUSY;
+                goto ioctl_done;
+            }
+            /* Used copy_from_user/copy_to_user to access user space data */
+            if (copy_from_user(&getFixRatesCmd, userdata, sizeof(getFixRatesCmd))) {
+                ret = -EFAULT;
+            } else {
+                ar->arRateMask = 0xFFFFFFFF;
+
+                if (wmi_get_ratemask_cmd(ar->arWmi) != A_OK) {
+                    up(&ar->arSem);
+                    ret = -EIO;
+                    goto ioctl_done;
+                }
+
+                wait_event_interruptible_timeout(arEvent, ar->arRateMask != 0xFFFFFFFF, wmitimeout * HZ);
+
+                if (signal_pending(current)) {
+                    ret = -EINTR;
+                }
+
+                if (!ret) {
+                    getFixRatesCmd.fixRateMask = ar->arRateMask;
+                }
+
+                if(copy_to_user(userdata, &getFixRatesCmd, sizeof(getFixRatesCmd))) {
+                   ret = -EFAULT;
+                }
+
+                up(&ar->arSem);
+            }
+            break;
+        }
+        case AR6000_XIOCTL_WMI_SET_AUTHMODE:
+        {
+            WMI_SET_AUTH_MODE_CMD setAuthMode;
+
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&setAuthMode, userdata,
+                                      sizeof(setAuthMode)))
+            {
+                ret = -EFAULT;
+            } else {
+                if (wmi_set_authmode_cmd(ar->arWmi, setAuthMode.mode) != A_OK)
+                {
+                    ret = -EIO;
+                }
+            }
+            break;
+        }
+        case AR6000_XIOCTL_WMI_SET_REASSOCMODE:
+        {
+            WMI_SET_REASSOC_MODE_CMD setReassocMode;
+
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&setReassocMode, userdata,
+                                      sizeof(setReassocMode)))
+            {
+                ret = -EFAULT;
+            } else {
+                if (wmi_set_reassocmode_cmd(ar->arWmi, setReassocMode.mode) != A_OK)
+                {
+                    ret = -EIO;
+                }
+            }
+            break;
+        }
+        case AR6000_XIOCTL_DIAG_READ:
+        {
+            A_UINT32 addr, data;
+	    if (get_user(addr, (unsigned int *)userdata)) {
+		ret = -EFAULT;
+		break;
+	    }
+            addr = TARG_VTOP(ar->arTargetType, addr);
+            if (ar6000_ReadRegDiag(ar->arHifDevice, &addr, &data) != A_OK) {
+                ret = -EIO;
+            }
+	    if (put_user(data, (unsigned int *)userdata + 1)) {
+		ret = -EFAULT;
+		break;
+	    }
+            break;
+        }
+        case AR6000_XIOCTL_DIAG_WRITE:
+        {
+            A_UINT32 addr, data;
+	    if (get_user(addr, (unsigned int *)userdata) ||
+		get_user(data, (unsigned int *)userdata + 1)) {
+		ret = -EFAULT;
+		break;
+	    }
+            addr = TARG_VTOP(ar->arTargetType, addr);
+            if (ar6000_WriteRegDiag(ar->arHifDevice, &addr, &data) != A_OK) {
+                ret = -EIO;
+            }
+            break;
+        }
+        case AR6000_XIOCTL_WMI_SET_KEEPALIVE:
+        {
+             WMI_SET_KEEPALIVE_CMD setKeepAlive;
+             if (ar->arWmiReady == FALSE) {
+                 ret = -EIO;
+                 goto ioctl_done;
+             } else if (copy_from_user(&setKeepAlive, userdata,
+                        sizeof(setKeepAlive))){
+                 ret = -EFAULT;
+             } else {
+                 if (wmi_set_keepalive_cmd(ar->arWmi, setKeepAlive.keepaliveInterval) != A_OK) {
+                     ret = -EIO;
+               }
+             }
+             break;
+        }
+        case AR6000_XIOCTL_WMI_SET_PARAMS:
+        {
+             WMI_SET_PARAMS_CMD cmd;
+             if (ar->arWmiReady == FALSE) {
+                 ret = -EIO;
+                 goto ioctl_done;
+             } else if (copy_from_user(&cmd, userdata,
+                        sizeof(cmd))){
+                 ret = -EFAULT;
+             } else if (copy_from_user(&cmd, userdata,
+                        sizeof(cmd) + cmd.length))
+            {
+                ret = -EFAULT;
+            } else {
+                 if (wmi_set_params_cmd(ar->arWmi, cmd.opcode, cmd.length, cmd.buffer) != A_OK) {
+                     ret = -EIO;
+               }
+             }
+             break;
+        }
+        case AR6000_XIOCTL_WMI_SET_MCAST_FILTER:
+        {
+             WMI_SET_MCAST_FILTER_CMD cmd;
+             if (ar->arWmiReady == FALSE) {
+                 ret = -EIO;
+                 goto ioctl_done;
+             } else if (copy_from_user(&cmd, userdata,
+                        sizeof(cmd))){
+                 ret = -EFAULT;
+             } else {
+                 if (wmi_set_mcast_filter_cmd(ar->arWmi, cmd.multicast_mac[0],
+                                                                                     cmd.multicast_mac[1],
+                                                                                     cmd.multicast_mac[2],
+                                                                                     cmd.multicast_mac[3]) != A_OK) {
+                     ret = -EIO;
+               }
+             }
+             break;
+        }
+        case AR6000_XIOCTL_WMI_DEL_MCAST_FILTER:
+        {
+             WMI_SET_MCAST_FILTER_CMD cmd;
+             if (ar->arWmiReady == FALSE) {
+                 ret = -EIO;
+                 goto ioctl_done;
+             } else if (copy_from_user(&cmd, userdata,
+                        sizeof(cmd))){
+                 ret = -EFAULT;
+             } else {
+                 if (wmi_del_mcast_filter_cmd(ar->arWmi, cmd.multicast_mac[0],
+                                                                                     cmd.multicast_mac[1],
+                                                                                     cmd.multicast_mac[2],
+                                                                                     cmd.multicast_mac[3]) != A_OK) {
+                     ret = -EIO;
+               }
+             }
+             break;
+        }
+        case AR6000_XIOCTL_WMI_MCAST_FILTER:
+        {
+             WMI_MCAST_FILTER_CMD cmd;
+             if (ar->arWmiReady == FALSE) {
+                 ret = -EIO;
+                 goto ioctl_done;
+             } else if (copy_from_user(&cmd, userdata,
+                        sizeof(cmd))){
+                 ret = -EFAULT;
+             } else {
+                 if (wmi_mcast_filter_cmd(ar->arWmi, cmd.enable)  != A_OK) {
+                     ret = -EIO;
+               }
+             }
+             break;
+        }
+        case AR6000_XIOCTL_WMI_GET_KEEPALIVE:
+        {
+            AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+            WMI_GET_KEEPALIVE_CMD getKeepAlive;
+            int ret = 0;
+            if (ar->bIsDestroyProgress) {
+                ret =-EBUSY;
+                goto ioctl_done;
+            }
+            if (ar->arWmiReady == FALSE) {
+               ret = -EIO;
+               goto ioctl_done;
+            }
+            if (down_interruptible(&ar->arSem)) {
+                ret = -ERESTARTSYS;
+                goto ioctl_done;
+            }
+            if (ar->bIsDestroyProgress) {
+                up(&ar->arSem);
+                ret = -EBUSY;
+                goto ioctl_done;
+            }
+            if (copy_from_user(&getKeepAlive, userdata,sizeof(getKeepAlive))) {
+               ret = -EFAULT;
+            } else {
+            getKeepAlive.keepaliveInterval = wmi_get_keepalive_cmd(ar->arWmi);
+            ar->arKeepaliveConfigured = 0xFF;
+            if (wmi_get_keepalive_configured(ar->arWmi) != A_OK){
+                up(&ar->arSem);
+                ret = -EIO;
+                goto ioctl_done;
+            }
+            wait_event_interruptible_timeout(arEvent, ar->arKeepaliveConfigured != 0xFF, wmitimeout * HZ);
+            if (signal_pending(current)) {
+                ret = -EINTR;
+            }
+
+            if (!ret) {
+                getKeepAlive.configured = ar->arKeepaliveConfigured;
+            }
+            if (copy_to_user(userdata, &getKeepAlive, sizeof(getKeepAlive))) {
+               ret = -EFAULT;
+            }
+            up(&ar->arSem);
+            }
+            break;
+        }
+        case AR6000_XIOCTL_WMI_SET_APPIE:
+        {
+            WMI_SET_APPIE_CMD appIEcmd;
+            A_UINT8           appIeInfo[IEEE80211_APPIE_FRAME_MAX_LEN];
+            A_UINT32            fType,ieLen;
+
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+                goto ioctl_done;
+            }
+	    if (get_user(fType, (A_UINT32 *)userdata)) {
+		ret = -EFAULT;
+		break;
+	    }
+            appIEcmd.mgmtFrmType = fType;
+            if (appIEcmd.mgmtFrmType >= IEEE80211_APPIE_NUM_OF_FRAME) {
+                ret = -EIO;
+            } else {
+		if (get_user(ieLen, (A_UINT32 *)(userdata + 4))) {
+		    ret = -EFAULT;
+		    break;
+		}
+                appIEcmd.ieLen = ieLen;
+                A_PRINTF("WPSIE: Type-%d, Len-%d\n",appIEcmd.mgmtFrmType, appIEcmd.ieLen);
+                if (appIEcmd.ieLen > IEEE80211_APPIE_FRAME_MAX_LEN) {
+                    ret = -EIO;
+                    break;
+                }
+                if (copy_from_user(appIeInfo, userdata + 8, appIEcmd.ieLen)) {
+                    ret = -EFAULT;
+                } else {
+                    if (wmi_set_appie_cmd(ar->arWmi, appIEcmd.mgmtFrmType,
+                                          appIEcmd.ieLen,  appIeInfo) != A_OK)
+                    {
+                        ret = -EIO;
+                    }
+                }
+            }
+            break;
+        }
+        case AR6000_XIOCTL_WMI_SET_MGMT_FRM_RX_FILTER:
+        {
+            WMI_BSS_FILTER_CMD cmd;
+            A_UINT32    filterType;
+
+            if (copy_from_user(&filterType, userdata, sizeof(A_UINT32)))
+            {
+                ret = -EFAULT;
+                goto ioctl_done;
+            }
+            if (filterType & (IEEE80211_FILTER_TYPE_BEACON |
+                                    IEEE80211_FILTER_TYPE_PROBE_RESP))
+            {
+                cmd.bssFilter = ALL_BSS_FILTER;
+            } else {
+                cmd.bssFilter = NONE_BSS_FILTER;
+            }
+            if (wmi_bssfilter_cmd(ar->arWmi, cmd.bssFilter, 0) != A_OK) {
+                ret = -EIO;
+            } else {
+                ar->arUserBssFilter = cmd.bssFilter;
+            }
+
+            AR6000_SPIN_LOCK(&ar->arLock, 0);
+            ar->arMgmtFilter = filterType;
+            AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+            break;
+        }
+        case AR6000_XIOCTL_WMI_SET_WSC_STATUS:
+        {
+            A_UINT32    wsc_status;
+
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+                goto ioctl_done;
+            } else if (copy_from_user(&wsc_status, userdata, sizeof(A_UINT32)))
+            {
+                ret = -EFAULT;
+                goto ioctl_done;
+            }
+            if (wmi_set_wsc_status_cmd(ar->arWmi, wsc_status) != A_OK) {
+                ret = -EIO;
+            }
+            break;
+        }
+        case AR6000_XIOCTL_BMI_ROMPATCH_INSTALL:
+        {
+            A_UINT32 ROM_addr;
+            A_UINT32 RAM_addr;
+            A_UINT32 nbytes;
+            A_UINT32 do_activate;
+            A_UINT32 rompatch_id;
+
+	    if (get_user(ROM_addr, (A_UINT32 *)userdata) ||
+		get_user(RAM_addr, (A_UINT32 *)userdata + 1) ||
+		get_user(nbytes, (A_UINT32 *)userdata + 2) ||
+		get_user(do_activate, (A_UINT32 *)userdata + 3)) {
+		ret = -EFAULT;
+		break;
+	    }
+            AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("Install rompatch from ROM: 0x%x to RAM: 0x%x  length: %d\n",
+                             ROM_addr, RAM_addr, nbytes));
+            ret = BMIrompatchInstall(hifDevice, ROM_addr, RAM_addr,
+                                        nbytes, do_activate, &rompatch_id);
+            if (ret == A_OK) {
+		/* return value */
+		if (put_user(rompatch_id, (unsigned int *)rq->ifr_data)) {
+		    ret = -EFAULT;
+		    break;
+		}
+            }
+            break;
+        }
+
+        case AR6000_XIOCTL_BMI_ROMPATCH_UNINSTALL:
+        {
+            A_UINT32 rompatch_id;
+
+	    if (get_user(rompatch_id, (A_UINT32 *)userdata)) {
+		ret = -EFAULT;
+		break;
+	    }
+            AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("UNinstall rompatch_id %d\n", rompatch_id));
+            ret = BMIrompatchUninstall(hifDevice, rompatch_id);
+            break;
+        }
+
+        case AR6000_XIOCTL_BMI_ROMPATCH_ACTIVATE:
+        case AR6000_XIOCTL_BMI_ROMPATCH_DEACTIVATE:
+        {
+            A_UINT32 rompatch_count;
+
+	    if (get_user(rompatch_count, (A_UINT32 *)userdata)) {
+		ret = -EFAULT;
+		break;
+	    }
+            AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("Change rompatch activation count=%d\n", rompatch_count));
+            length = sizeof(A_UINT32) * rompatch_count;
+            if ((buffer = (unsigned char *)A_MALLOC(length)) != NULL) {
+                A_MEMZERO(buffer, length);
+                if (copy_from_user(buffer, &userdata[sizeof(rompatch_count)], length))
+                {
+                    ret = -EFAULT;
+                } else {
+                    if (cmd == AR6000_XIOCTL_BMI_ROMPATCH_ACTIVATE) {
+                        ret = BMIrompatchActivate(hifDevice, rompatch_count, (A_UINT32 *)buffer);
+                    } else {
+                        ret = BMIrompatchDeactivate(hifDevice, rompatch_count, (A_UINT32 *)buffer);
+                    }
+                }
+                A_FREE(buffer);
+            } else {
+                ret = -ENOMEM;
+            }
+
+            break;
+        }
+        case AR6000_XIOCTL_SET_IP:
+        {
+            WMI_SET_IP_CMD setIP;
+
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&setIP, userdata,
+                                      sizeof(setIP)))
+            {
+                ret = -EFAULT;
+            } else {
+                if (wmi_set_ip_cmd(ar->arWmi,
+                                &setIP) != A_OK)
+                {
+                    ret = -EIO;
+                }
+            }
+            break;
+        }
+
+        case AR6000_XIOCTL_WMI_SET_HOST_SLEEP_MODE:
+        {
+            WMI_SET_HOST_SLEEP_MODE_CMD setHostSleepMode;
+
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&setHostSleepMode, userdata,
+                                      sizeof(setHostSleepMode)))
+            {
+                ret = -EFAULT;
+            } else {
+                if (wmi_set_host_sleep_mode_cmd(ar->arWmi,
+                                &setHostSleepMode) != A_OK)
+                {
+                    ret = -EIO;
+                }
+            }
+            break;
+        }
+        case AR6000_XIOCTL_WMI_SET_WOW_MODE:
+        {
+            WMI_SET_WOW_MODE_CMD setWowMode;
+
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&setWowMode, userdata,
+                                      sizeof(setWowMode)))
+            {
+                ret = -EFAULT;
+            } else {
+                if (wmi_set_wow_mode_cmd(ar->arWmi,
+                                &setWowMode) != A_OK)
+                {
+                    ret = -EIO;
+                }
+            }
+            break;
+        }
+        case AR6000_XIOCTL_WMI_GET_WOW_LIST:
+        {
+            WMI_GET_WOW_LIST_CMD getWowList;
+
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&getWowList, userdata,
+                                      sizeof(getWowList)))
+            {
+                ret = -EFAULT;
+            } else {
+                if (wmi_get_wow_list_cmd(ar->arWmi,
+                                &getWowList) != A_OK)
+                {
+                    ret = -EIO;
+                }
+            }
+            break;
+        }
+        case AR6000_XIOCTL_WMI_ADD_WOW_PATTERN:
+        {
+#define WOW_PATTERN_SIZE 64
+#define WOW_MASK_SIZE 64
+
+            WMI_ADD_WOW_PATTERN_CMD cmd;
+            A_UINT8 mask_data[WOW_PATTERN_SIZE]={0};
+            A_UINT8 pattern_data[WOW_PATTERN_SIZE]={0};
+
+            do {
+                if (ar->arWmiReady == FALSE) {
+                    ret = -EIO;
+                    break;        
+                } 
+                if(copy_from_user(&cmd, userdata,
+                            sizeof(WMI_ADD_WOW_PATTERN_CMD))) 
+                {
+                    ret = -EFAULT;
+                    break;        
+                }
+                if (copy_from_user(pattern_data,
+                                      userdata + 3,
+                                      cmd.filter_size)) 
+                {
+                    ret = -EFAULT;
+                    break;        
+                }
+                if (copy_from_user(mask_data,
+                                  (userdata + 3 + cmd.filter_size),
+                                  cmd.filter_size))
+                {
+                    ret = -EFAULT;
+                    break;
+                }
+                if (wmi_add_wow_pattern_cmd(ar->arWmi,
+                            &cmd, pattern_data, mask_data, cmd.filter_size) != A_OK)
+                {
+                    ret = -EIO;
+                }
+            } while(FALSE);
+#undef WOW_PATTERN_SIZE
+#undef WOW_MASK_SIZE
+            break;
+        }
+        case AR6000_XIOCTL_WMI_DEL_WOW_PATTERN:
+        {
+            WMI_DEL_WOW_PATTERN_CMD delWowPattern;
+
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&delWowPattern, userdata,
+                                      sizeof(delWowPattern)))
+            {
+                ret = -EFAULT;
+            } else {
+                if (wmi_del_wow_pattern_cmd(ar->arWmi,
+                                &delWowPattern) != A_OK)
+                {
+                    ret = -EIO;
+                }
+            }
+            break;
+        }
+        case AR6000_XIOCTL_DUMP_HTC_CREDIT_STATE:
+            if (ar->arHtcTarget != NULL) {
+#ifdef ATH_DEBUG_MODULE
+                HTCDumpCreditStates(ar->arHtcTarget);
+#endif /* ATH_DEBUG_MODULE */
+#ifdef HTC_EP_STAT_PROFILING
+                {
+                    HTC_ENDPOINT_STATS stats;
+                    int i;
+
+                    for (i = 0; i < 5; i++) {
+                        if (HTCGetEndpointStatistics(ar->arHtcTarget,
+                                                     i,
+                                                     HTC_EP_STAT_SAMPLE_AND_CLEAR,
+                                                     &stats)) {
+                            A_PRINTF(KERN_ALERT"------- Profiling Endpoint : %d \n", i);
+                            A_PRINTF(KERN_ALERT"TxCreditLowIndications : %d \n", stats.TxCreditLowIndications);
+                            A_PRINTF(KERN_ALERT"TxIssued : %d \n", stats.TxIssued);
+                            A_PRINTF(KERN_ALERT"TxDropped: %d \n", stats.TxDropped);
+                            A_PRINTF(KERN_ALERT"TxPacketsBundled : %d \n", stats.TxPacketsBundled);
+                            A_PRINTF(KERN_ALERT"TxBundles : %d \n", stats.TxBundles);
+                            A_PRINTF(KERN_ALERT"TxCreditRpts : %d \n", stats.TxCreditRpts);
+                            A_PRINTF(KERN_ALERT"TxCreditsRptsFromRx : %d \n", stats.TxCreditRptsFromRx);
+                            A_PRINTF(KERN_ALERT"TxCreditsRptsFromOther : %d \n", stats.TxCreditRptsFromOther);
+                            A_PRINTF(KERN_ALERT"TxCreditsRptsFromEp0 : %d \n", stats.TxCreditRptsFromEp0);
+                            A_PRINTF(KERN_ALERT"TxCreditsFromRx : %d \n", stats.TxCreditsFromRx);
+                            A_PRINTF(KERN_ALERT"TxCreditsFromOther : %d \n", stats.TxCreditsFromOther);
+                            A_PRINTF(KERN_ALERT"TxCreditsFromEp0 : %d \n", stats.TxCreditsFromEp0);
+                            A_PRINTF(KERN_ALERT"TxCreditsConsummed : %d \n", stats.TxCreditsConsummed);
+                            A_PRINTF(KERN_ALERT"TxCreditsReturned : %d \n", stats.TxCreditsReturned);
+                            A_PRINTF(KERN_ALERT"RxReceived : %d \n", stats.RxReceived);
+                            A_PRINTF(KERN_ALERT"RxPacketsBundled : %d \n", stats.RxPacketsBundled);
+                            A_PRINTF(KERN_ALERT"RxLookAheads : %d \n", stats.RxLookAheads);
+                            A_PRINTF(KERN_ALERT"RxBundleLookAheads : %d \n", stats.RxBundleLookAheads);
+                            A_PRINTF(KERN_ALERT"RxBundleIndFromHdr : %d \n", stats.RxBundleIndFromHdr);
+                            A_PRINTF(KERN_ALERT"RxAllocThreshHit : %d \n", stats.RxAllocThreshHit);
+                            A_PRINTF(KERN_ALERT"RxAllocThreshBytes : %d \n", stats.RxAllocThreshBytes);
+                            A_PRINTF(KERN_ALERT"---- \n");
+
+                        }
+            }
+                }
+#endif
+            }
+            break;
+        case AR6000_XIOCTL_TRAFFIC_ACTIVITY_CHANGE:
+            if (ar->arHtcTarget != NULL) {
+                struct ar6000_traffic_activity_change data;
+
+                if (copy_from_user(&data, userdata, sizeof(data)))
+                {
+                    ret = -EFAULT;
+                    goto ioctl_done;
+                }
+                    /* note, this is used for testing (mbox ping testing), indicate activity
+                     * change using the stream ID as the traffic class */
+                ar6000_indicate_tx_activity(ar,
+                                            (A_UINT8)data.StreamID,
+                                            data.Active ? TRUE : FALSE);
+            }
+            break;
+        case AR6000_XIOCTL_WMI_SET_CONNECT_CTRL_FLAGS:
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&connectCtrlFlags, userdata,
+                                      sizeof(connectCtrlFlags)))
+            {
+                ret = -EFAULT;
+            } else {
+                ar->arConnectCtrlFlags = connectCtrlFlags;
+            }
+            break;
+        case AR6000_XIOCTL_WMI_SET_AKMP_PARAMS:
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&akmpParams, userdata,
+                                      sizeof(WMI_SET_AKMP_PARAMS_CMD)))
+            {
+                ret = -EFAULT;
+            } else {
+                if (wmi_set_akmp_params_cmd(ar->arWmi, &akmpParams) != A_OK) {
+                    ret = -EIO;
+                }
+            }
+            break;
+        case AR6000_XIOCTL_WMI_SET_PMKID_LIST:
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else {
+                if (copy_from_user(&pmkidInfo.numPMKID, userdata,
+                                      sizeof(pmkidInfo.numPMKID)))
+                {
+                    ret = -EFAULT;
+                    break;
+                }
+                if (copy_from_user(&pmkidInfo.pmkidList,
+                                   userdata + sizeof(pmkidInfo.numPMKID),
+                                   pmkidInfo.numPMKID * sizeof(WMI_PMKID)))
+                {
+                    ret = -EFAULT;
+                    break;
+                }
+                if (wmi_set_pmkid_list_cmd(ar->arWmi, &pmkidInfo) != A_OK) {
+                    ret = -EIO;
+                }
+            }
+            break;
+        case AR6000_XIOCTL_WMI_GET_PMKID_LIST:
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else  {
+                if (wmi_get_pmkid_list_cmd(ar->arWmi) != A_OK) {
+                    ret = -EIO;
+                }
+            }
+            break;
+        case AR6000_XIOCTL_WMI_ABORT_SCAN:
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            }
+            ret = wmi_abort_scan_cmd(ar->arWmi);
+            break;
+        case AR6000_XIOCTL_AP_HIDDEN_SSID:
+        {
+            A_UINT8    hidden_ssid;
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&hidden_ssid, userdata, sizeof(hidden_ssid))) {
+                ret = -EFAULT;
+            } else {
+                wmi_ap_set_hidden_ssid(ar->arWmi, hidden_ssid);
+                ar->ap_hidden_ssid = hidden_ssid;
+                ar->ap_profile_flag = 1; /* There is a change in profile */
+            }
+            break;
+        }
+        case AR6000_XIOCTL_AP_GET_STA_LIST:
+        {
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else {
+                A_UINT8 i;
+                ap_get_sta_t temp;
+                A_MEMZERO(&temp, sizeof(temp));
+                for(i=0;i<AP_MAX_NUM_STA;i++) {
+                    A_MEMCPY(temp.sta[i].mac, ar->sta_list[i].mac, ATH_MAC_LEN);
+                    temp.sta[i].aid = ar->sta_list[i].aid;
+                    temp.sta[i].keymgmt = ar->sta_list[i].keymgmt;
+                    temp.sta[i].ucipher = ar->sta_list[i].ucipher;
+                    temp.sta[i].auth = ar->sta_list[i].auth;
+                }
+                if(copy_to_user((ap_get_sta_t *)rq->ifr_data, &temp,
+                                 sizeof(ar->sta_list))) {
+                    ret = -EFAULT;
+                }
+            }
+            break;
+        }
+        case AR6000_XIOCTL_AP_SET_NUM_STA:
+        {
+            A_UINT8    num_sta;
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&num_sta, userdata, sizeof(num_sta))) {
+                ret = -EFAULT;
+            } else if(num_sta > AP_MAX_NUM_STA) {
+                /* value out of range */
+                ret = -EINVAL;
+            } else {
+                wmi_ap_set_num_sta(ar->arWmi, num_sta);
+            }
+            break;
+        }
+        case AR6000_XIOCTL_AP_SET_ACL_POLICY:
+        {
+            A_UINT8    policy;
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&policy, userdata, sizeof(policy))) {
+                ret = -EFAULT;
+            } else if(policy == ar->g_acl.policy) {
+                /* No change in policy */
+            } else {
+                if(!(policy & AP_ACL_RETAIN_LIST_MASK)) {
+                    /* clear ACL list */
+                    memset(&ar->g_acl,0,sizeof(WMI_AP_ACL));
+                }
+                ar->g_acl.policy = policy;
+                wmi_ap_set_acl_policy(ar->arWmi, policy);
+            }
+            break;
+        }
+        case AR6000_XIOCTL_AP_SET_ACL_MAC:
+        {
+            WMI_AP_ACL_MAC_CMD    acl;
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&acl, userdata, sizeof(acl))) {
+                ret = -EFAULT;
+            } else {
+                if(acl_add_del_mac(&ar->g_acl, &acl)) {
+                    wmi_ap_acl_mac_list(ar->arWmi, &acl);
+                } else {
+                    A_PRINTF("ACL list error\n");
+                    ret = -EIO;
+                }
+            }
+            break;
+        }
+        case AR6000_XIOCTL_AP_GET_ACL_LIST:
+        {
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if(copy_to_user((WMI_AP_ACL *)rq->ifr_data, &ar->g_acl,
+                                 sizeof(WMI_AP_ACL))) {
+                    ret = -EFAULT;
+            }
+            break;
+        }
+        case AR6000_XIOCTL_AP_COMMIT_CONFIG:
+        {
+            ret = ar6000_ap_mode_profile_commit(ar);
+            break;
+        }
+        case IEEE80211_IOCTL_GETWPAIE:
+        {
+            struct ieee80211req_wpaie wpaie;
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&wpaie, userdata, sizeof(wpaie))) {
+                ret = -EFAULT;
+            } else if (ar6000_ap_mode_get_wpa_ie(ar, &wpaie)) {
+                ret = -EFAULT;
+            } else if(copy_to_user(userdata, &wpaie, sizeof(wpaie))) {
+                ret = -EFAULT;
+            }
+            break;
+        }
+        case AR6000_XIOCTL_AP_CONN_INACT_TIME:
+        {
+            A_UINT32    period;
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&period, userdata, sizeof(period))) {
+                ret = -EFAULT;
+            } else {
+                wmi_ap_conn_inact_time(ar->arWmi, period);
+            }
+            break;
+        }
+        case AR6000_XIOCTL_AP_PROT_SCAN_TIME:
+        {
+            WMI_AP_PROT_SCAN_TIME_CMD  bgscan;
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&bgscan, userdata, sizeof(bgscan))) {
+                ret = -EFAULT;
+            } else {
+                wmi_ap_bgscan_time(ar->arWmi, bgscan.period_min, bgscan.dwell_ms);
+            }
+            break;
+        }
+        case AR6000_XIOCTL_AP_SET_COUNTRY:
+        {
+            ret = ar6000_ioctl_set_country(dev, rq);
+            break;
+        }
+        case AR6000_XIOCTL_AP_SET_DTIM:
+        {
+            WMI_AP_SET_DTIM_CMD  d;
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&d, userdata, sizeof(d))) {
+                ret = -EFAULT;
+            } else {
+                if(d.dtim > 0 && d.dtim < 11) {
+                    ar->ap_dtim_period = d.dtim;
+                    wmi_ap_set_dtim(ar->arWmi, d.dtim);
+                    ar->ap_profile_flag = 1; /* There is a change in profile */
+                } else {
+                    A_PRINTF("DTIM out of range. Valid range is [1-10]\n");
+                    ret = -EIO;
+                }
+            }
+            break;
+        }
+        case AR6000_XIOCTL_WMI_TARGET_EVENT_REPORT:
+        {
+            WMI_SET_TARGET_EVENT_REPORT_CMD evtCfgCmd;
+
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            }
+            if (copy_from_user(&evtCfgCmd, userdata,
+                               sizeof(evtCfgCmd))) {
+                ret = -EFAULT;
+                break;
+            }
+            ret = wmi_set_target_event_report_cmd(ar->arWmi, &evtCfgCmd);
+            break;
+        }
+        case AR6000_XIOCTL_AP_INTRA_BSS_COMM:
+        {
+            A_UINT8    intra=0;
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&intra, userdata, sizeof(intra))) {
+                ret = -EFAULT;
+            } else {
+                ar->intra_bss = (intra?1:0);
+            }
+            break;
+        }
+        case AR6000_XIOCTL_DUMP_MODULE_DEBUG_INFO:
+        {
+            struct drv_debug_module_s moduleinfo;
+
+            if (copy_from_user(&moduleinfo, userdata, sizeof(moduleinfo))) {
+                ret = -EFAULT;
+                break;
+            }
+
+            a_dump_module_debug_info_by_name(moduleinfo.modulename);
+            ret = 0;
+            break;
+        }
+        case AR6000_XIOCTL_MODULE_DEBUG_SET_MASK:
+        {
+            struct drv_debug_module_s moduleinfo;
+
+            if (copy_from_user(&moduleinfo, userdata, sizeof(moduleinfo))) {
+                ret = -EFAULT;
+                break;
+            }
+
+            if (A_FAILED(a_set_module_mask(moduleinfo.modulename, moduleinfo.mask))) {
+                ret = -EFAULT;
+            }
+
+            break;
+        }
+        case AR6000_XIOCTL_MODULE_DEBUG_GET_MASK:
+        {
+            struct drv_debug_module_s moduleinfo;
+
+            if (copy_from_user(&moduleinfo, userdata, sizeof(moduleinfo))) {
+                ret = -EFAULT;
+                break;
+            }
+
+            if (A_FAILED(a_get_module_mask(moduleinfo.modulename, &moduleinfo.mask))) {
+                ret = -EFAULT;
+                break;
+            }
+
+            if (copy_to_user(userdata, &moduleinfo, sizeof(moduleinfo))) {
+                ret = -EFAULT;
+                break;
+            }
+
+            break;
+        }
+#ifdef ATH_AR6K_11N_SUPPORT
+        case AR6000_XIOCTL_DUMP_RCV_AGGR_STATS:
+        {
+            PACKET_LOG *copy_of_pkt_log;
+
+            aggr_dump_stats(ar->aggr_cntxt, &copy_of_pkt_log);
+            if (copy_to_user(rq->ifr_data, copy_of_pkt_log, sizeof(PACKET_LOG))) {
+                ret = -EFAULT;
+            }
+            break;
+        }
+        case AR6000_XIOCTL_SETUP_AGGR:
+        {
+            WMI_ADDBA_REQ_CMD cmd;
+
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
+                ret = -EFAULT;
+            } else {
+                wmi_setup_aggr_cmd(ar->arWmi, cmd.tid);
+            }
+        }
+        break;
+
+        case AR6000_XIOCTL_DELE_AGGR:
+        {
+            WMI_DELBA_REQ_CMD cmd;
+
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
+                ret = -EFAULT;
+            } else {
+                wmi_delete_aggr_cmd(ar->arWmi, cmd.tid, cmd.is_sender_initiator);
+            }
+        }
+        break;
+
+        case AR6000_XIOCTL_ALLOW_AGGR:
+        {
+            WMI_ALLOW_AGGR_CMD cmd;
+
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
+                ret = -EFAULT;
+            } else {
+                wmi_allow_aggr_cmd(ar->arWmi, cmd.tx_allow_aggr, cmd.rx_allow_aggr);
+            }
+        }
+        break;
+
+        case AR6000_XIOCTL_SET_HT_CAP:
+        {
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&htCap, userdata,
+                                      sizeof(htCap)))
+            {
+                ret = -EFAULT;
+            } else {
+
+                if (wmi_set_ht_cap_cmd(ar->arWmi, &htCap) != A_OK)
+                {
+                    ret = -EIO;
+                }
+            }
+            break;
+        }
+        case AR6000_XIOCTL_SET_HT_OP:
+        {
+             if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&htOp, userdata,
+                                      sizeof(htOp)))
+            {
+                 ret = -EFAULT;
+             } else {
+
+                if (wmi_set_ht_op_cmd(ar->arWmi, htOp.sta_chan_width) != A_OK)
+                {
+                     ret = -EIO;
+               }
+             }
+             break;
+        }
+#endif
+        case AR6000_XIOCTL_ACL_DATA:
+        {
+            void *osbuf = NULL;
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (ar6000_create_acl_data_osbuf(dev, (A_UINT8*)userdata, &osbuf) != A_OK) {
+                     ret = -EIO;
+            } else {
+                if (wmi_data_hdr_add(ar->arWmi, osbuf, DATA_MSGTYPE, 0, WMI_DATA_HDR_DATA_TYPE_ACL,0,NULL) != A_OK) {
+                    AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("XIOCTL_ACL_DATA - wmi_data_hdr_add failed\n"));
+                } else {
+                    /* Send data buffer over HTC */
+                    ar6000_acl_data_tx(osbuf, ar->arNetDev);
+                }
+            }
+            break;
+        }
+        case AR6000_XIOCTL_HCI_CMD:
+        {
+            char tmp_buf[512];
+            A_INT8 i;
+            WMI_HCI_CMD *cmd = (WMI_HCI_CMD *)tmp_buf;
+            A_UINT8 size;
+
+            size = sizeof(cmd->cmd_buf_sz);
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(cmd, userdata, size)) {
+                 ret = -EFAULT;
+            } else if(copy_from_user(cmd->buf, userdata + size, cmd->cmd_buf_sz)) {
+                    ret = -EFAULT;
+            } else {
+                if (wmi_send_hci_cmd(ar->arWmi, cmd->buf, cmd->cmd_buf_sz) != A_OK) {
+                     ret = -EIO;
+                }else if(loghci) {
+                    A_PRINTF_LOG("HCI Command To PAL --> \n");
+                    for(i = 0; i < cmd->cmd_buf_sz; i++) {
+                        A_PRINTF_LOG("0x%02x ",cmd->buf[i]);
+                        if((i % 10) == 0) {
+                            A_PRINTF_LOG("\n");
+                        }
+                    }
+                    A_PRINTF_LOG("\n");
+                    A_PRINTF_LOG("==================================\n");
+                }
+            }
+            break;
+        }
+        case AR6000_XIOCTL_WLAN_CONN_PRECEDENCE:
+        {
+            WMI_SET_BT_WLAN_CONN_PRECEDENCE cmd;
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
+                ret = -EFAULT;
+            } else {
+                if (cmd.precedence == BT_WLAN_CONN_PRECDENCE_WLAN ||
+                            cmd.precedence == BT_WLAN_CONN_PRECDENCE_PAL) {
+                    if ( wmi_set_wlan_conn_precedence_cmd(ar->arWmi, cmd.precedence) != A_OK) {
+                        ret = -EIO;
+                    }
+                } else {
+                    ret = -EINVAL;
+                }
+            }
+            break;
+        }
+        case AR6000_XIOCTL_AP_GET_STAT:
+        {
+            ret = ar6000_ioctl_get_ap_stats(dev, rq);
+            break;
+        }
+        case AR6000_XIOCTL_SET_TX_SELECT_RATES:
+        {
+            WMI_SET_TX_SELECT_RATES_CMD masks;
+
+             if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&masks, userdata,
+                                      sizeof(masks)))
+            {
+                 ret = -EFAULT;
+             } else {
+
+                if (wmi_set_tx_select_rates_cmd(ar->arWmi, masks.rateMasks) != A_OK)
+                {
+                     ret = -EIO;
+               }
+             }
+             break;
+        }
+        case AR6000_XIOCTL_AP_GET_HIDDEN_SSID:
+        {
+            WMI_AP_HIDDEN_SSID_CMD ssid;
+            ssid.hidden_ssid = ar->ap_hidden_ssid;
+
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if(copy_to_user((WMI_AP_HIDDEN_SSID_CMD *)rq->ifr_data,
+                                    &ssid, sizeof(WMI_AP_HIDDEN_SSID_CMD))) {
+                    ret = -EFAULT;
+            }
+            break;
+        }
+        case AR6000_XIOCTL_AP_GET_COUNTRY:
+        {
+            WMI_AP_SET_COUNTRY_CMD cty;
+            A_MEMCPY(cty.countryCode, ar->ap_country_code, 3);
+
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if(copy_to_user((WMI_AP_SET_COUNTRY_CMD *)rq->ifr_data,
+                                    &cty, sizeof(WMI_AP_SET_COUNTRY_CMD))) {
+                    ret = -EFAULT;
+            }
+            break;
+        }
+        case AR6000_XIOCTL_AP_GET_WMODE:
+        {
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if(copy_to_user((A_UINT8 *)rq->ifr_data,
+                                    &ar->ap_wmode, sizeof(A_UINT8))) {
+                    ret = -EFAULT;
+            }
+            break;
+        }
+        case AR6000_XIOCTL_AP_GET_DTIM:
+        {
+            WMI_AP_SET_DTIM_CMD dtim;
+            dtim.dtim = ar->ap_dtim_period;
+
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if(copy_to_user((WMI_AP_SET_DTIM_CMD *)rq->ifr_data,
+                                    &dtim, sizeof(WMI_AP_SET_DTIM_CMD))) {
+                    ret = -EFAULT;
+            }
+            break;
+        }
+        case AR6000_XIOCTL_AP_GET_BINTVL:
+        {
+            WMI_BEACON_INT_CMD bi;
+            bi.beaconInterval = ar->ap_beacon_interval;
+
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if(copy_to_user((WMI_BEACON_INT_CMD *)rq->ifr_data,
+                                    &bi, sizeof(WMI_BEACON_INT_CMD))) {
+                    ret = -EFAULT;
+            }
+            break;
+        }
+        case AR6000_XIOCTL_AP_GET_RTS:
+        {
+            WMI_SET_RTS_CMD rts;
+            rts.threshold = ar->arRTS;
+	     
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if(copy_to_user((WMI_SET_RTS_CMD *)rq->ifr_data,
+                                    &rts, sizeof(WMI_SET_RTS_CMD))) {
+                    ret = -EFAULT;
+            }
+            break;
+        }
+        case AR6000_XIOCTL_FETCH_TARGET_REGS:
+        {
+            A_UINT32 targregs[AR6003_FETCH_TARG_REGS_COUNT];
+
+            if (ar->arTargetType == TARGET_TYPE_AR6003) {
+                ar6k_FetchTargetRegs(hifDevice, targregs);
+                if (copy_to_user((A_UINT32 *)rq->ifr_data, &targregs, sizeof(targregs)))
+                {
+                    ret = -EFAULT;
+                }
+            } else {
+                ret = -EOPNOTSUPP;
+            }
+            break;
+        }
+        case AR6000_XIOCTL_AP_SET_11BG_RATESET:
+        {
+            WMI_AP_SET_11BG_RATESET_CMD  rate;
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&rate, userdata, sizeof(rate))) {
+                ret = -EFAULT;
+            } else {
+                wmi_ap_set_rateset(ar->arWmi, rate.rateset);
+            }
+            break;
+        }
+        case AR6000_XIOCTL_GET_WLAN_SLEEP_STATE:
+        {
+            WMI_REPORT_SLEEP_STATE_EVENT  wmiSleepEvent ;
+
+            if (ar->arWlanState == WLAN_ENABLED) {
+                wmiSleepEvent.sleepState = WMI_REPORT_SLEEP_STATUS_IS_AWAKE;
+            } else {
+                wmiSleepEvent.sleepState = WMI_REPORT_SLEEP_STATUS_IS_DEEP_SLEEP;
+            }
+            rq->ifr_ifru.ifru_ivalue = ar->arWlanState; /* return value */
+
+            ar6000_send_event_to_app(ar, WMI_REPORT_SLEEP_STATE_EVENTID, (A_UINT8*)&wmiSleepEvent,
+                                     sizeof(WMI_REPORT_SLEEP_STATE_EVENTID));
+            break;
+        }
+#ifdef CONFIG_PM
+        case AR6000_XIOCTL_SET_BT_HW_POWER_STATE:
+        {
+            unsigned int state;
+	    if (get_user(state, (unsigned int *)userdata)) {
+		ret = -EFAULT;
+		break;
+	    }
+            if (ar6000_set_bt_hw_state(ar, state)!=A_OK) {
+                ret = -EIO;
+            }       
+        }
+            break;
+        case AR6000_XIOCTL_GET_BT_HW_POWER_STATE:
+            rq->ifr_ifru.ifru_ivalue = !ar->arBTOff; /* return value */
+            break;
+#endif
+
+        case AR6000_XIOCTL_WMI_SET_TX_SGI_PARAM:
+        {
+             WMI_SET_TX_SGI_PARAM_CMD SGICmd;
+
+             if (ar->arWmiReady == FALSE) {
+                 ret = -EIO;
+             } else if (copy_from_user(&SGICmd, userdata,
+                                       sizeof(SGICmd))){
+                 ret = -EFAULT;
+             } else{
+                     if (wmi_SGI_cmd(ar->arWmi, SGICmd.sgiMask, SGICmd.sgiPERThreshold) != A_OK) {
+                         ret = -EIO;
+                     }
+
+             }
+             break;
+        }
+
+        case AR6000_XIOCTL_ADD_AP_INTERFACE:
+#ifdef CONFIG_AP_VIRTUAL_ADAPTER_SUPPORT
+        {
+            char ap_ifname[IFNAMSIZ] = {0,};
+            if (copy_from_user(ap_ifname, userdata, IFNAMSIZ)) {
+                ret = -EFAULT;
+            } else {
+                if (ar6000_add_ap_interface(ar, ap_ifname) != A_OK) {
+                    ret = -EIO;
+                } 
+            }
+        }
+#else
+            ret = -EOPNOTSUPP;
+#endif
+            break;
+        case AR6000_XIOCTL_REMOVE_AP_INTERFACE:
+#ifdef CONFIG_AP_VIRTUAL_ADAPTER_SUPPORT
+            if (ar6000_remove_ap_interface(ar) != A_OK) {
+                ret = -EIO;
+            } 
+#else
+            ret = -EOPNOTSUPP;
+#endif
+            break;
+
+        default:
+            ret = -EOPNOTSUPP;
+    }
+
+ioctl_done:
+    rtnl_lock(); /* restore rtnl state */
+    dev_put(dev);
+
+    return ret;
+}
+
+A_UINT8 mac_cmp_wild(A_UINT8 *mac, A_UINT8 *new_mac, A_UINT8 wild, A_UINT8 new_wild)
+{
+    A_UINT8 i;
+
+    for(i=0;i<ATH_MAC_LEN;i++) {
+        if((wild & 1<<i) && (new_wild & 1<<i)) continue;
+        if(mac[i] != new_mac[i]) return 1;
+    }
+    if((A_MEMCMP(new_mac, null_mac, 6)==0) && new_wild &&
+        (wild != new_wild)) {
+        return 1;
+    }
+
+    return 0;
+}
+
+A_UINT8    acl_add_del_mac(WMI_AP_ACL *a, WMI_AP_ACL_MAC_CMD *acl)
+{
+    A_INT8    already_avail=-1, free_slot=-1, i;
+
+    /* To check whether this mac is already there in our list */
+    for(i=AP_ACL_SIZE-1;i>=0;i--)
+    {
+        if(mac_cmp_wild(a->acl_mac[i], acl->mac, a->wildcard[i],
+            acl->wildcard)==0)
+                already_avail = i;
+
+        if(!((1 << i) & a->index))
+            free_slot = i;
+    }
+
+    if(acl->action == ADD_MAC_ADDR)
+    {
+        /* Dont add mac if it is already available */
+        if((already_avail >= 0) || (free_slot == -1))
+            return 0;
+
+        A_MEMCPY(a->acl_mac[free_slot], acl->mac, ATH_MAC_LEN);
+        a->index = a->index | (1 << free_slot);
+        acl->index = free_slot;
+        a->wildcard[free_slot] = acl->wildcard;
+        return 1;
+    }
+    else if(acl->action == DEL_MAC_ADDR)
+    {
+        if(acl->index > AP_ACL_SIZE)
+            return 0;
+
+        if(!(a->index & (1 << acl->index)))
+            return 0;
+
+        A_MEMZERO(a->acl_mac[acl->index],ATH_MAC_LEN);
+        a->index = a->index & ~(1 << acl->index);
+        a->wildcard[acl->index] = 0;
+        return 1;
+    }
+
+    return 0;
+}
diff --git a/drivers/net/ath6kl/os/linux/netbuf.c b/drivers/net/ath6kl/os/linux/netbuf.c
new file mode 100644
index 00000000000..15e5d047520
--- /dev/null
+++ b/drivers/net/ath6kl/os/linux/netbuf.c
@@ -0,0 +1,234 @@
+//------------------------------------------------------------------------------
+// Copyright (c) 2004-2010 Atheros Communications Inc.
+// All rights reserved.
+//
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//
+// Author(s): ="Atheros"
+//------------------------------------------------------------------------------
+#include <a_config.h>
+#include "athdefs.h"
+#include "a_types.h"
+#include "a_osapi.h"
+#include "htc_packet.h"
+
+#define AR6000_DATA_OFFSET    64
+
+void a_netbuf_enqueue(A_NETBUF_QUEUE_T *q, void *pkt)
+{
+    skb_queue_tail((struct sk_buff_head *) q, (struct sk_buff *) pkt);
+}
+
+void a_netbuf_prequeue(A_NETBUF_QUEUE_T *q, void *pkt)
+{
+    skb_queue_head((struct sk_buff_head *) q, (struct sk_buff *) pkt);
+}
+
+void *a_netbuf_dequeue(A_NETBUF_QUEUE_T *q)
+{
+    return((void *) skb_dequeue((struct sk_buff_head *) q));
+}
+
+int a_netbuf_queue_size(A_NETBUF_QUEUE_T *q)
+{
+    return(skb_queue_len((struct sk_buff_head *) q));
+}
+
+int a_netbuf_queue_empty(A_NETBUF_QUEUE_T *q)
+{
+    return(skb_queue_empty((struct sk_buff_head *) q));
+}
+
+void a_netbuf_queue_init(A_NETBUF_QUEUE_T *q)
+{
+    skb_queue_head_init((struct sk_buff_head *) q);
+}
+
+void *
+a_netbuf_alloc(int size)
+{
+    struct sk_buff *skb;
+    size += 2 * (A_GET_CACHE_LINE_BYTES()); /* add some cacheline space at front and back of buffer */
+    skb = dev_alloc_skb(AR6000_DATA_OFFSET + sizeof(HTC_PACKET) + size);
+    skb_reserve(skb, AR6000_DATA_OFFSET + sizeof(HTC_PACKET) + A_GET_CACHE_LINE_BYTES());    
+    return ((void *)skb);
+}
+
+/*
+ * Allocate an SKB w.o. any encapsulation requirement.
+ */
+void *
+a_netbuf_alloc_raw(int size)
+{
+    struct sk_buff *skb;
+
+    skb = dev_alloc_skb(size);
+
+    return ((void *)skb);
+}
+
+void
+a_netbuf_free(void *bufPtr)
+{
+    struct sk_buff *skb = (struct sk_buff *)bufPtr;
+
+    dev_kfree_skb(skb);
+}
+
+A_UINT32
+a_netbuf_to_len(void *bufPtr)
+{
+    return (((struct sk_buff *)bufPtr)->len);
+}
+
+void *
+a_netbuf_to_data(void *bufPtr)
+{
+    return (((struct sk_buff *)bufPtr)->data);
+}
+
+/*
+ * Add len # of bytes to the beginning of the network buffer
+ * pointed to by bufPtr
+ */
+A_STATUS
+a_netbuf_push(void *bufPtr, A_INT32 len)
+{
+    skb_push((struct sk_buff *)bufPtr, len);
+
+    return A_OK;
+}
+
+/*
+ * Add len # of bytes to the beginning of the network buffer
+ * pointed to by bufPtr and also fill with data
+ */
+A_STATUS
+a_netbuf_push_data(void *bufPtr, char *srcPtr, A_INT32 len)
+{
+    skb_push((struct sk_buff *) bufPtr, len);
+    A_MEMCPY(((struct sk_buff *)bufPtr)->data, srcPtr, len);
+
+    return A_OK;
+}
+
+/*
+ * Add len # of bytes to the end of the network buffer
+ * pointed to by bufPtr
+ */
+A_STATUS
+a_netbuf_put(void *bufPtr, A_INT32 len)
+{
+    skb_put((struct sk_buff *)bufPtr, len);
+
+    return A_OK;
+}
+
+/*
+ * Add len # of bytes to the end of the network buffer
+ * pointed to by bufPtr and also fill with data
+ */
+A_STATUS
+a_netbuf_put_data(void *bufPtr, char *srcPtr, A_INT32 len)
+{
+    char *start = (char*)(((struct sk_buff *)bufPtr)->data +
+        ((struct sk_buff *)bufPtr)->len);
+    skb_put((struct sk_buff *)bufPtr, len);
+    A_MEMCPY(start, srcPtr, len);
+
+    return A_OK;
+}
+
+
+/*
+ * Trim the network buffer pointed to by bufPtr to len # of bytes 
+ */
+A_STATUS
+a_netbuf_setlen(void *bufPtr, A_INT32 len)
+{
+    skb_trim((struct sk_buff *)bufPtr, len);
+
+    return A_OK;
+}
+
+/*
+ * Chop of len # of bytes from the end of the buffer.
+ */
+A_STATUS
+a_netbuf_trim(void *bufPtr, A_INT32 len)
+{
+    skb_trim((struct sk_buff *)bufPtr, ((struct sk_buff *)bufPtr)->len - len);
+
+    return A_OK;
+}
+
+/*
+ * Chop of len # of bytes from the end of the buffer and return the data.
+ */
+A_STATUS
+a_netbuf_trim_data(void *bufPtr, char *dstPtr, A_INT32 len)
+{
+    char *start = (char*)(((struct sk_buff *)bufPtr)->data +
+        (((struct sk_buff *)bufPtr)->len - len));
+    
+    A_MEMCPY(dstPtr, start, len);
+    skb_trim((struct sk_buff *)bufPtr, ((struct sk_buff *)bufPtr)->len - len);
+
+    return A_OK;
+}
+
+
+/*
+ * Returns the number of bytes available to a a_netbuf_push()
+ */
+A_INT32
+a_netbuf_headroom(void *bufPtr)
+{
+    return (skb_headroom((struct sk_buff *)bufPtr));
+}
+
+/*
+ * Removes specified number of bytes from the beginning of the buffer
+ */
+A_STATUS
+a_netbuf_pull(void *bufPtr, A_INT32 len)
+{
+    skb_pull((struct sk_buff *)bufPtr, len);
+
+    return A_OK;
+}
+
+/*
+ * Removes specified number of bytes from the beginning of the buffer
+ * and return the data
+ */
+A_STATUS
+a_netbuf_pull_data(void *bufPtr, char *dstPtr, A_INT32 len)
+{
+    A_MEMCPY(dstPtr, ((struct sk_buff *)bufPtr)->data, len);
+    skb_pull((struct sk_buff *)bufPtr, len);
+
+    return A_OK;
+}
+
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+EXPORT_SYMBOL(a_netbuf_to_data);
+EXPORT_SYMBOL(a_netbuf_put);
+EXPORT_SYMBOL(a_netbuf_pull);
+EXPORT_SYMBOL(a_netbuf_alloc);
+EXPORT_SYMBOL(a_netbuf_free);
+#endif
diff --git a/drivers/net/ath6kl/os/linux/wireless_ext.c b/drivers/net/ath6kl/os/linux/wireless_ext.c
new file mode 100644
index 00000000000..bb6de0f404f
--- /dev/null
+++ b/drivers/net/ath6kl/os/linux/wireless_ext.c
@@ -0,0 +1,2725 @@
+//------------------------------------------------------------------------------
+// Copyright (c) 2004-2010 Atheros Communications Inc.
+// All rights reserved.
+//
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//
+// Author(s): ="Atheros"
+//------------------------------------------------------------------------------
+
+#include "ar6000_drv.h"
+
+#define IWE_STREAM_ADD_EVENT(p1, p2, p3, p4, p5) \
+    iwe_stream_add_event((p1), (p2), (p3), (p4), (p5))
+
+#define IWE_STREAM_ADD_POINT(p1, p2, p3, p4, p5) \
+    iwe_stream_add_point((p1), (p2), (p3), (p4), (p5))
+
+#define IWE_STREAM_ADD_VALUE(p1, p2, p3, p4, p5, p6) \
+    iwe_stream_add_value((p1), (p2), (p3), (p4), (p5), (p6))
+
+static void ar6000_set_quality(struct iw_quality *iq, A_INT8 rssi);
+extern unsigned int wmitimeout;
+extern A_WAITQUEUE_HEAD arEvent;
+
+#if WIRELESS_EXT > 14
+/*
+ * Encode a WPA or RSN information element as a custom
+ * element using the hostap format.
+ */
+static u_int
+encode_ie(void *buf, size_t bufsize,
+    const u_int8_t *ie, size_t ielen,
+    const char *leader, size_t leader_len)
+{
+    u_int8_t *p;
+    int i;
+
+    if (bufsize < leader_len)
+        return 0;
+    p = buf;
+    memcpy(p, leader, leader_len);
+    bufsize -= leader_len;
+    p += leader_len;
+    for (i = 0; i < ielen && bufsize > 2; i++)
+    {
+        p += sprintf((char*)p, "%02x", ie[i]);
+        bufsize -= 2;
+    }
+    return (i == ielen ? p - (u_int8_t *)buf : 0);
+}
+#endif /* WIRELESS_EXT > 14 */
+
+static A_UINT8
+get_bss_phy_capability(bss_t *bss)
+{
+    A_UINT8 capability = 0;
+    struct ieee80211_common_ie *cie = &bss->ni_cie;
+#define CHAN_IS_11A(x)              (!((x >= 2412) && (x <= 2484)))
+    if (CHAN_IS_11A(cie->ie_chan)) {
+        if (cie->ie_htcap) {
+            capability = WMI_11NA_CAPABILITY;
+        } else {
+            capability = WMI_11A_CAPABILITY;
+        }
+    } else if ((cie->ie_erp) || (cie->ie_xrates)) {
+        if (cie->ie_htcap) {
+            capability = WMI_11NG_CAPABILITY;
+        } else {
+            capability = WMI_11G_CAPABILITY;
+        }
+    }
+    return capability;
+}
+
+void
+ar6000_scan_node(void *arg, bss_t *ni)
+{
+    struct iw_event iwe;
+#if WIRELESS_EXT > 14
+    char buf[256];
+#endif
+    struct ar_giwscan_param *param;
+    A_CHAR *current_ev;
+    A_CHAR *end_buf;
+    struct ieee80211_common_ie  *cie;
+    A_CHAR *current_val;
+    A_INT32 j;
+    A_UINT32 rate_len, data_len = 0;
+
+    param = (struct ar_giwscan_param *)arg;
+
+    current_ev = param->current_ev;
+    end_buf = param->end_buf;
+
+    cie = &ni->ni_cie;
+
+    if ((end_buf - current_ev) > IW_EV_ADDR_LEN)
+    {
+        A_MEMZERO(&iwe, sizeof(iwe));
+        iwe.cmd = SIOCGIWAP;
+        iwe.u.ap_addr.sa_family = ARPHRD_ETHER;
+        A_MEMCPY(iwe.u.ap_addr.sa_data, ni->ni_macaddr, 6);
+        current_ev = IWE_STREAM_ADD_EVENT(param->info, current_ev, end_buf,
+                                          &iwe, IW_EV_ADDR_LEN);
+    }
+    param->bytes_needed += IW_EV_ADDR_LEN;
+
+    data_len = cie->ie_ssid[1] + IW_EV_POINT_LEN;
+    if ((end_buf - current_ev) > data_len)
+    {
+        A_MEMZERO(&iwe, sizeof(iwe));
+        iwe.cmd = SIOCGIWESSID;
+        iwe.u.data.flags = 1;
+        iwe.u.data.length = cie->ie_ssid[1];
+        current_ev = IWE_STREAM_ADD_POINT(param->info, current_ev, end_buf,
+                                          &iwe, (char*)&cie->ie_ssid[2]);
+    }
+    param->bytes_needed += data_len;
+
+    if (cie->ie_capInfo & (IEEE80211_CAPINFO_ESS|IEEE80211_CAPINFO_IBSS)) {
+        if ((end_buf - current_ev) > IW_EV_UINT_LEN)
+        {
+            A_MEMZERO(&iwe, sizeof(iwe));
+            iwe.cmd = SIOCGIWMODE;
+            iwe.u.mode = cie->ie_capInfo & IEEE80211_CAPINFO_ESS ?
+                         IW_MODE_MASTER : IW_MODE_ADHOC;
+            current_ev = IWE_STREAM_ADD_EVENT(param->info, current_ev, end_buf,
+                                              &iwe, IW_EV_UINT_LEN);
+        }
+        param->bytes_needed += IW_EV_UINT_LEN;
+    }
+
+    if ((end_buf - current_ev) > IW_EV_FREQ_LEN)
+    {
+        A_MEMZERO(&iwe, sizeof(iwe));
+        iwe.cmd = SIOCGIWFREQ;
+        iwe.u.freq.m = cie->ie_chan * 100000;
+        iwe.u.freq.e = 1;
+        current_ev = IWE_STREAM_ADD_EVENT(param->info, current_ev, end_buf,
+                                          &iwe, IW_EV_FREQ_LEN);
+    }
+    param->bytes_needed += IW_EV_FREQ_LEN;
+
+    if ((end_buf - current_ev) > IW_EV_QUAL_LEN)
+    {
+        A_MEMZERO(&iwe, sizeof(iwe));
+        iwe.cmd = IWEVQUAL;
+        ar6000_set_quality(&iwe.u.qual, ni->ni_snr);
+        current_ev = IWE_STREAM_ADD_EVENT(param->info, current_ev, end_buf,
+                                          &iwe, IW_EV_QUAL_LEN);
+    }
+    param->bytes_needed += IW_EV_QUAL_LEN;
+
+    if ((end_buf - current_ev) > IW_EV_POINT_LEN)
+    {
+        A_MEMZERO(&iwe, sizeof(iwe));
+        iwe.cmd = SIOCGIWENCODE;
+        if (cie->ie_capInfo & IEEE80211_CAPINFO_PRIVACY) {
+            iwe.u.data.flags = IW_ENCODE_ENABLED | IW_ENCODE_NOKEY;
+        } else {
+            iwe.u.data.flags = IW_ENCODE_DISABLED;
+        }
+        iwe.u.data.length = 0;
+        current_ev = IWE_STREAM_ADD_POINT(param->info, current_ev, end_buf,
+                                          &iwe, "");
+    }
+    param->bytes_needed += IW_EV_POINT_LEN;
+
+    /* supported bit rate */
+    A_MEMZERO(&iwe, sizeof(iwe));
+    iwe.cmd = SIOCGIWRATE;
+    iwe.u.bitrate.fixed = 0;
+    iwe.u.bitrate.disabled = 0;
+    iwe.u.bitrate.value = 0;
+    current_val = current_ev + IW_EV_LCP_LEN;
+    param->bytes_needed += IW_EV_LCP_LEN;
+
+    if (cie->ie_rates != NULL) {
+        rate_len = cie->ie_rates[1];
+        data_len = (rate_len * (IW_EV_PARAM_LEN - IW_EV_LCP_LEN));
+        if ((end_buf - current_ev) > data_len)
+        {
+            for (j = 0; j < rate_len; j++) {
+                    unsigned char val;
+                    val = cie->ie_rates[2 + j];
+                    iwe.u.bitrate.value =
+                        (val >= 0x80)? ((val - 0x80) * 500000): (val * 500000);
+                    current_val = IWE_STREAM_ADD_VALUE(param->info, current_ev,
+                                                       current_val, end_buf,
+                                                       &iwe, IW_EV_PARAM_LEN);
+            }
+        }
+        param->bytes_needed += data_len;
+    }
+
+    if (cie->ie_xrates != NULL) {
+        rate_len = cie->ie_xrates[1];
+        data_len = (rate_len * (IW_EV_PARAM_LEN - IW_EV_LCP_LEN));
+        if ((end_buf - current_ev) > data_len)
+        {
+            for (j = 0; j < rate_len; j++) {
+                    unsigned char val;
+                    val = cie->ie_xrates[2 + j];
+                    iwe.u.bitrate.value =
+                        (val >= 0x80)? ((val - 0x80) * 500000): (val * 500000);
+                    current_val = IWE_STREAM_ADD_VALUE(param->info, current_ev,
+                                                       current_val, end_buf,
+                                                       &iwe, IW_EV_PARAM_LEN);
+            }
+        }
+        param->bytes_needed += data_len;
+    }
+    /* remove fixed header if no rates were added */
+    if ((current_val - current_ev) > IW_EV_LCP_LEN)
+        current_ev = current_val;
+
+#if WIRELESS_EXT >= 18
+    /* IE */
+    if (cie->ie_wpa != NULL) {
+        data_len = cie->ie_wpa[1] + 2 + IW_EV_POINT_LEN;
+        if ((end_buf - current_ev) > data_len)
+        {
+            A_MEMZERO(&iwe, sizeof(iwe));
+            iwe.cmd = IWEVGENIE;
+            iwe.u.data.length = cie->ie_wpa[1] + 2;
+            current_ev = IWE_STREAM_ADD_POINT(param->info, current_ev, end_buf,
+                                              &iwe, (char*)cie->ie_wpa);
+        }
+        param->bytes_needed += data_len;
+    }
+
+    if (cie->ie_rsn != NULL && cie->ie_rsn[0] == IEEE80211_ELEMID_RSN) {
+        data_len = cie->ie_rsn[1] + 2 + IW_EV_POINT_LEN;
+        if ((end_buf - current_ev) > data_len)
+        {
+            A_MEMZERO(&iwe, sizeof(iwe));
+            iwe.cmd = IWEVGENIE;
+            iwe.u.data.length = cie->ie_rsn[1] + 2;
+            current_ev = IWE_STREAM_ADD_POINT(param->info, current_ev, end_buf,
+                                              &iwe, (char*)cie->ie_rsn);
+        }
+        param->bytes_needed += data_len;
+    }
+
+#endif /* WIRELESS_EXT >= 18 */
+
+    if ((end_buf - current_ev) > IW_EV_CHAR_LEN)
+    {
+        /* protocol */
+        A_MEMZERO(&iwe, sizeof(iwe));
+        iwe.cmd = SIOCGIWNAME;
+        switch (get_bss_phy_capability(ni)) {
+        case WMI_11A_CAPABILITY:
+            snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11a");
+            break;
+        case WMI_11G_CAPABILITY:
+            snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11g");
+            break;
+        case WMI_11NA_CAPABILITY:
+            snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11na");
+            break;
+        case WMI_11NG_CAPABILITY:
+            snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11ng");
+            break;
+        default:
+            snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11b");
+            break;
+        }
+        current_ev = IWE_STREAM_ADD_EVENT(param->info, current_ev, end_buf,
+                                          &iwe, IW_EV_CHAR_LEN);
+    }
+    param->bytes_needed += IW_EV_CHAR_LEN;
+
+#if WIRELESS_EXT > 14
+    A_MEMZERO(&iwe, sizeof(iwe));
+    iwe.cmd = IWEVCUSTOM;
+    iwe.u.data.length = snprintf(buf, sizeof(buf), "bcn_int=%d", cie->ie_beaconInt);
+    data_len = iwe.u.data.length + IW_EV_POINT_LEN;
+    if ((end_buf - current_ev) > data_len)
+    {
+        current_ev = IWE_STREAM_ADD_POINT(param->info, current_ev, end_buf,
+                                          &iwe, buf);
+    }
+    param->bytes_needed += data_len;
+
+#if WIRELESS_EXT < 18
+    if (cie->ie_wpa != NULL) {
+        static const char wpa_leader[] = "wpa_ie=";
+        data_len = (sizeof(wpa_leader) - 1) + ((cie->ie_wpa[1]+2) * 2) + IW_EV_POINT_LEN;
+        if ((end_buf - current_ev) > data_len)
+        {
+            A_MEMZERO(&iwe, sizeof(iwe));
+            iwe.cmd = IWEVCUSTOM;
+            iwe.u.data.length = encode_ie(buf, sizeof(buf), cie->ie_wpa,
+                                          cie->ie_wpa[1]+2,
+                                          wpa_leader, sizeof(wpa_leader)-1);
+
+            if (iwe.u.data.length != 0) {
+                current_ev = IWE_STREAM_ADD_POINT(param->info, current_ev, 
+                                                  end_buf, &iwe, buf);
+            }
+        }
+        param->bytes_needed += data_len;
+    }
+
+    if (cie->ie_rsn != NULL && cie->ie_rsn[0] == IEEE80211_ELEMID_RSN) {
+        static const char rsn_leader[] = "rsn_ie=";
+        data_len = (sizeof(rsn_leader) - 1) + ((cie->ie_rsn[1]+2) * 2) + IW_EV_POINT_LEN;
+        if ((end_buf - current_ev) > data_len)
+        {
+            A_MEMZERO(&iwe, sizeof(iwe));
+            iwe.cmd = IWEVCUSTOM;
+            iwe.u.data.length = encode_ie(buf, sizeof(buf), cie->ie_rsn,
+                                          cie->ie_rsn[1]+2,
+                                          rsn_leader, sizeof(rsn_leader)-1);
+
+            if (iwe.u.data.length != 0) {
+                current_ev = IWE_STREAM_ADD_POINT(param->info, current_ev, 
+                                                  end_buf, &iwe, buf);
+            }
+        }
+        param->bytes_needed += data_len;
+    }
+#endif /* WIRELESS_EXT < 18 */
+
+    if (cie->ie_wmm != NULL) {
+        static const char wmm_leader[] = "wmm_ie=";
+        data_len = (sizeof(wmm_leader) - 1) + ((cie->ie_wmm[1]+2) * 2) + IW_EV_POINT_LEN;
+        if ((end_buf - current_ev) > data_len)
+        {
+            A_MEMZERO(&iwe, sizeof(iwe));
+            iwe.cmd = IWEVCUSTOM;
+            iwe.u.data.length = encode_ie(buf, sizeof(buf), cie->ie_wmm,
+                                          cie->ie_wmm[1]+2,
+                                          wmm_leader, sizeof(wmm_leader)-1);
+            if (iwe.u.data.length != 0) {
+                current_ev = IWE_STREAM_ADD_POINT(param->info, current_ev,
+                                                  end_buf, &iwe, buf);
+            }
+        }
+        param->bytes_needed += data_len;
+    }
+
+    if (cie->ie_ath != NULL) {
+        static const char ath_leader[] = "ath_ie=";
+        data_len = (sizeof(ath_leader) - 1) + ((cie->ie_ath[1]+2) * 2) + IW_EV_POINT_LEN;
+        if ((end_buf - current_ev) > data_len)
+        {
+            A_MEMZERO(&iwe, sizeof(iwe));
+            iwe.cmd = IWEVCUSTOM;
+            iwe.u.data.length = encode_ie(buf, sizeof(buf), cie->ie_ath,
+                                          cie->ie_ath[1]+2,
+                                          ath_leader, sizeof(ath_leader)-1);
+            if (iwe.u.data.length != 0) {
+                current_ev = IWE_STREAM_ADD_POINT(param->info, current_ev,
+                                                  end_buf, &iwe, buf);
+            }
+        }
+        param->bytes_needed += data_len;
+    }
+
+#ifdef WAPI_ENABLE
+    if (cie->ie_wapi != NULL) {
+        static const char wapi_leader[] = "wapi_ie=";
+        data_len = (sizeof(wapi_leader) - 1) + ((cie->ie_wapi[1] + 2) * 2) + IW_EV_POINT_LEN;
+        if ((end_buf - current_ev) > data_len) {
+            A_MEMZERO(&iwe, sizeof(iwe));
+            iwe.cmd = IWEVCUSTOM;
+            iwe.u.data.length = encode_ie(buf, sizeof(buf), cie->ie_wapi,
+                                      cie->ie_wapi[1] + 2,
+                                      wapi_leader, sizeof(wapi_leader) - 1);
+            if (iwe.u.data.length != 0) {
+                current_ev = IWE_STREAM_ADD_POINT(param->info, current_ev,
+                                                  end_buf, &iwe, buf);
+            }
+        }
+        param->bytes_needed += data_len;
+    }
+#endif /* WAPI_ENABLE */
+
+#endif /* WIRELESS_EXT > 14 */
+
+#if WIRELESS_EXT >= 18
+    if (cie->ie_wsc != NULL) {
+        data_len = (cie->ie_wsc[1] + 2) + IW_EV_POINT_LEN;
+        if ((end_buf - current_ev) > data_len)
+        {
+            A_MEMZERO(&iwe, sizeof(iwe));
+            iwe.cmd = IWEVGENIE;
+            iwe.u.data.length = cie->ie_wsc[1] + 2;
+            current_ev = IWE_STREAM_ADD_POINT(param->info, current_ev, end_buf,
+                                              &iwe, (char*)cie->ie_wsc);
+        }
+        param->bytes_needed += data_len;
+    }
+#endif /* WIRELESS_EXT >= 18 */
+
+    param->current_ev = current_ev;
+}
+
+int
+ar6000_ioctl_giwscan(struct net_device *dev,
+            struct iw_request_info *info,
+            struct iw_point *data, char *extra)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    struct ar_giwscan_param param;
+
+    if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) {
+        A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
+        return -EOPNOTSUPP;
+    }
+
+    if (ar->arWlanState == WLAN_DISABLED) {
+        return -EIO;
+    }
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+    param.current_ev = extra;
+    param.end_buf = extra + data->length;
+    param.bytes_needed = 0;
+    param.info = info;
+
+    /* Translate data to WE format */
+    wmi_iterate_nodes(ar->arWmi, ar6000_scan_node, &param);
+
+    /* check if bytes needed is greater than bytes consumed */
+    if (param.bytes_needed > (param.current_ev - extra))
+    {
+        /* Request one byte more than needed, because when "data->length" equals bytes_needed,
+        it is not possible to add the last event data as all iwe_stream_add_xxxxx() functions
+        checks whether (cur_ptr + ev_len) < end_ptr, due to this one more retry would happen*/
+        data->length = param.bytes_needed + 1;
+
+        return -E2BIG;
+    }
+
+    return 0;
+}
+
+extern int reconnect_flag;
+/* SIOCSIWESSID */
+static int
+ar6000_ioctl_siwessid(struct net_device *dev,
+                     struct iw_request_info *info,
+                     struct iw_point *data, char *ssid)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    A_STATUS status;
+    A_UINT8     arNetworkType;
+    A_UINT8 prevMode = ar->arNetworkType;
+
+    if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) {
+        A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
+        return -EOPNOTSUPP;
+    }
+
+    if (ar->bIsDestroyProgress) {
+        return -EBUSY;
+    }
+
+    if (ar->arWlanState == WLAN_DISABLED) {
+        return -EIO;
+    }
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+#if defined(WIRELESS_EXT)
+    if (WIRELESS_EXT >= 20) {
+        data->length += 1;
+    }
+#endif
+
+    /*
+     * iwconfig passes a null terminated string with length including this
+     * so we need to account for this
+     */
+    if (data->flags && (!data->length || (data->length == 1) ||
+        ((data->length - 1) > sizeof(ar->arSsid))))
+    {
+        /*
+         * ssid is invalid
+         */
+        return -EINVAL;
+    }
+
+    if (ar->arNextMode == AP_NETWORK) {
+        /* SSID change for AP network - Will take effect on commit */
+        if(A_MEMCMP(ar->arSsid,ssid,32) != 0) {
+             ar->arSsidLen = data->length - 1;
+            A_MEMCPY(ar->arSsid, ssid, ar->arSsidLen);
+            ar->ap_profile_flag = 1; /* There is a change in profile */
+        }
+        return 0;
+    } else if(ar->arNetworkType == AP_NETWORK) {
+        A_UINT8 ctr;
+        struct sk_buff *skb;
+
+        /* We are switching from AP to STA | IBSS mode, cleanup the AP state */
+        for (ctr=0; ctr < AP_MAX_NUM_STA; ctr++) {
+            remove_sta(ar, ar->sta_list[ctr].mac, 0);
+        }
+        A_MUTEX_LOCK(&ar->mcastpsqLock);
+        while (!A_NETBUF_QUEUE_EMPTY(&ar->mcastpsq)) {
+            skb = A_NETBUF_DEQUEUE(&ar->mcastpsq);
+            A_NETBUF_FREE(skb);
+        }
+        A_MUTEX_UNLOCK(&ar->mcastpsqLock);
+    }
+
+    /* Added for bug 25178, return an IOCTL error instead of target returning
+       Illegal parameter error when either the BSSID or channel is missing
+       and we cannot scan during connect.
+     */
+    if (data->flags) {
+        if (ar->arSkipScan == TRUE &&
+            (ar->arChannelHint == 0 ||
+             (!ar->arReqBssid[0] && !ar->arReqBssid[1] && !ar->arReqBssid[2] &&
+              !ar->arReqBssid[3] && !ar->arReqBssid[4] && !ar->arReqBssid[5])))
+        {
+            return -EINVAL;
+        }
+    }
+
+    if (down_interruptible(&ar->arSem)) {
+        return -ERESTARTSYS;
+    }
+
+    if (ar->bIsDestroyProgress || ar->arWlanState == WLAN_DISABLED) {
+        up(&ar->arSem);
+        return -EBUSY;
+    }
+
+    if (ar->arTxPending[wmi_get_control_ep(ar->arWmi)]) {
+        /*
+         * sleep until the command queue drains
+         */
+        wait_event_interruptible_timeout(arEvent,
+            ar->arTxPending[wmi_get_control_ep(ar->arWmi)] == 0, wmitimeout * HZ);
+        if (signal_pending(current)) {
+            return -EINTR;
+        }
+    }
+
+    if (!data->flags) {
+        arNetworkType = ar->arNetworkType;
+#ifdef ATH6K_CONFIG_CFG80211
+        if (ar->arConnected) {
+#endif /* ATH6K_CONFIG_CFG80211 */
+            ar6000_init_profile_info(ar);
+#ifdef ATH6K_CONFIG_CFG80211
+        }
+#endif /* ATH6K_CONFIG_CFG80211 */
+        ar->arNetworkType = arNetworkType;
+    }
+
+    /* Update the arNetworkType */
+    ar->arNetworkType = ar->arNextMode;
+
+
+    if ((prevMode != AP_NETWORK) &&
+        ((ar->arSsidLen) || ((ar->arSsidLen == 0) && ar->arConnected) || (!data->flags)))
+    {
+        if ((!data->flags) ||
+            (A_MEMCMP(ar->arSsid, ssid, ar->arSsidLen) != 0) ||
+            (ar->arSsidLen != (data->length - 1)))
+        {
+            /*
+             * SSID set previously or essid off has been issued.
+             *
+             * Disconnect Command is issued in two cases after wmi is ready
+             * (1) ssid is different from the previous setting
+             * (2) essid off has been issued
+             *
+             */
+            if (ar->arWmiReady == TRUE) {
+                reconnect_flag = 0;
+                status = wmi_setPmkid_cmd(ar->arWmi, ar->arBssid, NULL, 0);
+                status = wmi_disconnect_cmd(ar->arWmi);
+                A_MEMZERO(ar->arSsid, sizeof(ar->arSsid));
+                ar->arSsidLen = 0;
+                if (ar->arSkipScan == FALSE) {
+                    A_MEMZERO(ar->arReqBssid, sizeof(ar->arReqBssid));
+                }
+                if (!data->flags) {
+                    up(&ar->arSem);
+                    return 0;
+                }
+            } else {
+                 up(&ar->arSem);
+            }
+        }
+        else
+        {
+            /*
+             * SSID is same, so we assume profile hasn't changed.
+             * If the interface is up and wmi is ready, we issue
+             * a reconnect cmd. Issue a reconnect only we are already
+             * connected.
+             */
+            if((ar->arConnected == TRUE) && (ar->arWmiReady == TRUE))
+            {
+                reconnect_flag = TRUE;
+                status = wmi_reconnect_cmd(ar->arWmi,ar->arReqBssid,
+                                           ar->arChannelHint);
+                up(&ar->arSem);
+                if (status != A_OK) {
+                    return -EIO;
+                }
+                return 0;
+            }
+            else{
+                /*
+                 * Dont return if connect is pending.
+                 */
+                if(!(ar->arConnectPending)) {
+                    up(&ar->arSem);
+                    return 0;
+                }
+            }
+        }
+    }
+
+    ar->arSsidLen = data->length - 1;
+    A_MEMCPY(ar->arSsid, ssid, ar->arSsidLen);
+
+    if (ar6000_connect_to_ap(ar)!= A_OK) {
+        up(&ar->arSem);
+        return -EIO;
+    }else{
+      up(&ar->arSem);
+    }
+    return 0;
+}
+
+/* SIOCGIWESSID */
+static int
+ar6000_ioctl_giwessid(struct net_device *dev,
+                     struct iw_request_info *info,
+                     struct iw_point *data, char *essid)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+    if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) {
+        A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
+        return -EOPNOTSUPP;
+    }
+
+    if (ar->arWlanState == WLAN_DISABLED) {
+        return -EIO;
+    }
+
+    if (!ar->arSsidLen) {
+        return -EINVAL;
+    }
+
+    data->flags = 1;
+    data->length = ar->arSsidLen;
+    A_MEMCPY(essid, ar->arSsid, ar->arSsidLen);
+
+    return 0;
+}
+
+
+void ar6000_install_static_wep_keys(AR_SOFTC_T *ar)
+{
+    A_UINT8 index;
+    A_UINT8 keyUsage;
+
+    for (index = WMI_MIN_KEY_INDEX; index <= WMI_MAX_KEY_INDEX; index++) {
+        if (ar->arWepKeyList[index].arKeyLen) {
+            keyUsage = GROUP_USAGE;
+            if (index == ar->arDefTxKeyIndex) {
+                keyUsage |= TX_USAGE;
+            }
+            wmi_addKey_cmd(ar->arWmi,
+                           index,
+                           WEP_CRYPT,
+                           keyUsage,
+                           ar->arWepKeyList[index].arKeyLen,
+                           NULL,
+                           ar->arWepKeyList[index].arKey, KEY_OP_INIT_VAL, NULL,
+                           NO_SYNC_WMIFLAG);
+        }
+    }
+}
+
+/*
+ * SIOCSIWRATE
+ */
+int
+ar6000_ioctl_siwrate(struct net_device *dev,
+            struct iw_request_info *info,
+            struct iw_param *rrq, char *extra)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    A_UINT32  kbps;
+    A_INT8  rate_idx;
+
+    if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) {
+        A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
+        return -EOPNOTSUPP;
+    }
+
+    if (rrq->fixed) {
+        kbps = rrq->value / 1000;           /* rrq->value is in bps */
+    } else {
+        kbps = -1;                          /* -1 indicates auto rate */
+    }
+    if(kbps != -1 && wmi_validate_bitrate(ar->arWmi, kbps, &rate_idx) != A_OK)
+    {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BitRate is not Valid %d\n", kbps));
+        return -EINVAL;
+    }
+    ar->arBitRate = kbps;
+    if(ar->arWmiReady == TRUE)
+    {
+        if (wmi_set_bitrate_cmd(ar->arWmi, kbps, -1, -1) != A_OK) {
+            return -EINVAL;
+        }
+    }
+    return 0;
+}
+
+/*
+ * SIOCGIWRATE
+ */
+int
+ar6000_ioctl_giwrate(struct net_device *dev,
+            struct iw_request_info *info,
+            struct iw_param *rrq, char *extra)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    int ret = 0;
+
+    if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) {
+        A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
+        return -EOPNOTSUPP;
+    }
+
+    if (ar->bIsDestroyProgress) {
+        return -EBUSY;
+    }
+
+    if (ar->arWlanState == WLAN_DISABLED) {
+        return -EIO;
+    }
+
+    if ((ar->arNextMode != AP_NETWORK && !ar->arConnected) || ar->arWmiReady == FALSE) {
+        rrq->value = 1000 * 1000;       
+        return 0;
+    }
+
+    if (down_interruptible(&ar->arSem)) {
+        return -ERESTARTSYS;
+    }
+
+    if (ar->bIsDestroyProgress || ar->arWlanState == WLAN_DISABLED) {
+        up(&ar->arSem);
+        return -EBUSY;
+    }
+
+    ar->arBitRate = 0xFFFF;
+    if (wmi_get_bitrate_cmd(ar->arWmi) != A_OK) {
+        up(&ar->arSem);
+        return -EIO;
+    }
+    wait_event_interruptible_timeout(arEvent, ar->arBitRate != 0xFFFF, wmitimeout * HZ);
+    if (signal_pending(current)) {
+        ret = -EINTR;
+    }
+    /* If the interface is down or wmi is not ready or the target is not
+       connected - return the value stored in the device structure */
+    if (!ret) {
+        if (ar->arBitRate == -1) {
+            rrq->fixed = TRUE;
+            rrq->value = 0;
+        } else {
+            rrq->value = ar->arBitRate * 1000;
+        }
+    }
+
+    up(&ar->arSem);
+
+    return ret;
+}
+
+/*
+ * SIOCSIWTXPOW
+ */
+static int
+ar6000_ioctl_siwtxpow(struct net_device *dev,
+             struct iw_request_info *info,
+             struct iw_param *rrq, char *extra)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    A_UINT8 dbM;
+
+    if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) {
+        A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
+        return -EOPNOTSUPP;
+    }
+
+    if (ar->arWlanState == WLAN_DISABLED) {
+        return -EIO;
+    }
+
+    if (rrq->disabled) {
+        return -EOPNOTSUPP;
+    }
+
+    if (rrq->fixed) {
+        if (rrq->flags != IW_TXPOW_DBM) {
+            return -EOPNOTSUPP;
+        }
+        ar->arTxPwr= dbM = rrq->value;
+        ar->arTxPwrSet = TRUE;
+    } else {
+        ar->arTxPwr = dbM = 0;
+        ar->arTxPwrSet = FALSE;
+    }
+    if(ar->arWmiReady == TRUE)
+    {
+        AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_TX,("Set tx pwr cmd %d dbM\n", dbM));
+        wmi_set_txPwr_cmd(ar->arWmi, dbM);
+    }
+    return 0;
+}
+
+/*
+ * SIOCGIWTXPOW
+ */
+int
+ar6000_ioctl_giwtxpow(struct net_device *dev,
+            struct iw_request_info *info,
+            struct iw_param *rrq, char *extra)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    int ret = 0;
+
+    if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) {
+        A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
+        return -EOPNOTSUPP;
+    }
+
+    if (ar->bIsDestroyProgress) {
+        return -EBUSY;
+    }
+
+    if (ar->arWlanState == WLAN_DISABLED) {
+        return -EIO;
+    }
+
+    if (down_interruptible(&ar->arSem)) {
+        return -ERESTARTSYS;
+    }
+
+    if (ar->bIsDestroyProgress) {
+        up(&ar->arSem);
+        return -EBUSY;
+    }
+
+    if((ar->arWmiReady == TRUE) && (ar->arConnected == TRUE))
+    {
+        ar->arTxPwr = 0;
+
+        if (wmi_get_txPwr_cmd(ar->arWmi) != A_OK) {
+            up(&ar->arSem);
+            return -EIO;
+        }
+
+        wait_event_interruptible_timeout(arEvent, ar->arTxPwr != 0, wmitimeout * HZ);
+
+        if (signal_pending(current)) {
+            ret = -EINTR;
+         }
+    }
+   /* If the interace is down or wmi is not ready or target is not connected
+      then return value stored in the device structure */
+
+    if (!ret) {
+         if (ar->arTxPwrSet == TRUE) {
+            rrq->fixed = TRUE;
+        }
+        rrq->value = ar->arTxPwr;
+        rrq->flags = IW_TXPOW_DBM;
+        //
+        // IWLIST need this flag to get TxPower
+        //
+        rrq->disabled = 0;
+    }
+
+    up(&ar->arSem);
+
+    return ret;
+}
+
+/*
+ * SIOCSIWRETRY
+ * since iwconfig only provides us with one max retry value, we use it
+ * to apply to data frames of the BE traffic class.
+ */
+static int
+ar6000_ioctl_siwretry(struct net_device *dev,
+             struct iw_request_info *info,
+             struct iw_param *rrq, char *extra)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+    if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) {
+        A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
+        return -EOPNOTSUPP;
+    }
+
+    if (ar->arWlanState == WLAN_DISABLED) {
+        return -EIO;
+    }
+
+    if (rrq->disabled) {
+        return -EOPNOTSUPP;
+    }
+
+    if ((rrq->flags & IW_RETRY_TYPE) != IW_RETRY_LIMIT) {
+        return -EOPNOTSUPP;
+    }
+
+    if ( !(rrq->value >= WMI_MIN_RETRIES) || !(rrq->value <= WMI_MAX_RETRIES)) {
+            return - EINVAL;
+    }
+    if(ar->arWmiReady == TRUE)
+    {
+        if (wmi_set_retry_limits_cmd(ar->arWmi, DATA_FRAMETYPE, WMM_AC_BE,
+                                     rrq->value, 0) != A_OK){
+            return -EINVAL;
+        }
+    }
+    ar->arMaxRetries = rrq->value;
+    return 0;
+}
+
+/*
+ * SIOCGIWRETRY
+ */
+static int
+ar6000_ioctl_giwretry(struct net_device *dev,
+             struct iw_request_info *info,
+             struct iw_param *rrq, char *extra)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+    if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) {
+        A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
+        return -EOPNOTSUPP;
+    }
+
+    if (ar->arWlanState == WLAN_DISABLED) {
+        return -EIO;
+    }
+
+    rrq->disabled = 0;
+    switch (rrq->flags & IW_RETRY_TYPE) {
+    case IW_RETRY_LIFETIME:
+        return -EOPNOTSUPP;
+        break;
+    case IW_RETRY_LIMIT:
+        rrq->flags = IW_RETRY_LIMIT;
+        switch (rrq->flags & IW_RETRY_MODIFIER) {
+        case IW_RETRY_MIN:
+            rrq->flags |= IW_RETRY_MIN;
+            rrq->value = WMI_MIN_RETRIES;
+            break;
+        case IW_RETRY_MAX:
+            rrq->flags |= IW_RETRY_MAX;
+            rrq->value = ar->arMaxRetries;
+            break;
+        }
+        break;
+    }
+    return 0;
+}
+
+/*
+ * SIOCSIWENCODE
+ */
+static int
+ar6000_ioctl_siwencode(struct net_device *dev,
+              struct iw_request_info *info,
+              struct iw_point *erq, char *keybuf)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    int index;
+    A_INT32 auth = 0;
+
+    if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) {
+        A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
+        return -EOPNOTSUPP;
+    }
+
+    if(ar->arNextMode != AP_NETWORK) {
+    /*
+     *  Static WEP Keys should be configured before setting the SSID
+     */
+    if (ar->arSsid[0] && erq->length) {
+        return -EIO;
+    }
+    }
+
+    if (ar->arWlanState == WLAN_DISABLED) {
+        return -EIO;
+    }
+
+    index = erq->flags & IW_ENCODE_INDEX;
+
+    if (index && (((index - 1) < WMI_MIN_KEY_INDEX) ||
+                  ((index - 1) > WMI_MAX_KEY_INDEX)))
+    {
+        return -EIO;
+    }
+
+    if (erq->flags & IW_ENCODE_DISABLED) {
+        /*
+         * Encryption disabled
+         */
+        if (index) {
+            /*
+             * If key index was specified then clear the specified key
+             */
+            index--;
+            A_MEMZERO(ar->arWepKeyList[index].arKey,
+                      sizeof(ar->arWepKeyList[index].arKey));
+            ar->arWepKeyList[index].arKeyLen = 0;
+        }
+        ar->arDot11AuthMode       = OPEN_AUTH;
+        ar->arPairwiseCrypto      = NONE_CRYPT;
+        ar->arGroupCrypto         = NONE_CRYPT;
+        ar->arAuthMode            = NONE_AUTH;
+    } else {
+        /*
+         * Enabling WEP encryption
+         */
+        if (index) {
+            index--;                /* keyindex is off base 1 in iwconfig */
+        }
+
+        if (erq->flags & IW_ENCODE_OPEN) {
+            auth |= OPEN_AUTH;
+            ar->arDefTxKeyIndex = index;
+        }
+        if (erq->flags & IW_ENCODE_RESTRICTED) {
+            auth |= SHARED_AUTH;
+        }
+
+        if (!auth) {
+            auth = OPEN_AUTH;
+        }
+
+        if (erq->length) {
+            if (!IEEE80211_IS_VALID_WEP_CIPHER_LEN(erq->length)) {
+                return -EIO;
+            }
+
+            A_MEMZERO(ar->arWepKeyList[index].arKey,
+                      sizeof(ar->arWepKeyList[index].arKey));
+            A_MEMCPY(ar->arWepKeyList[index].arKey, keybuf, erq->length);
+            ar->arWepKeyList[index].arKeyLen = erq->length;
+            ar->arDot11AuthMode       = auth;
+        } else {
+            if (ar->arWepKeyList[index].arKeyLen == 0) {
+                return -EIO;
+            }
+            ar->arDefTxKeyIndex = index;
+
+            if(ar->arSsidLen && ar->arWepKeyList[index].arKeyLen) {
+                wmi_addKey_cmd(ar->arWmi,
+                               index,
+                               WEP_CRYPT,
+                               GROUP_USAGE | TX_USAGE,
+                               ar->arWepKeyList[index].arKeyLen,
+                               NULL,
+                               ar->arWepKeyList[index].arKey, KEY_OP_INIT_VAL, NULL,
+                               NO_SYNC_WMIFLAG);
+            }
+        }
+
+        ar->arPairwiseCrypto      = WEP_CRYPT;
+        ar->arGroupCrypto         = WEP_CRYPT;
+        ar->arAuthMode            = NONE_AUTH;
+    }
+
+    if(ar->arNextMode != AP_NETWORK) {
+    /*
+     * profile has changed.  Erase ssid to signal change
+     */
+        A_MEMZERO(ar->arSsid, sizeof(ar->arSsid));
+        ar->arSsidLen = 0;
+    }
+    ar->ap_profile_flag = 1; /* There is a change in profile */
+    return 0;
+}
+
+static int
+ar6000_ioctl_giwencode(struct net_device *dev,
+              struct iw_request_info *info,
+              struct iw_point *erq, char *key)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    A_UINT8 keyIndex;
+    struct ar_wep_key *wk;
+
+    if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) {
+        A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
+        return -EOPNOTSUPP;
+    }
+
+    if (ar->arWlanState == WLAN_DISABLED) {
+        return -EIO;
+    }
+
+    if (ar->arPairwiseCrypto == NONE_CRYPT) {
+        erq->length = 0;
+        erq->flags = IW_ENCODE_DISABLED;
+    } else {
+        if (ar->arPairwiseCrypto == WEP_CRYPT) {
+            /* get the keyIndex */
+            keyIndex = erq->flags & IW_ENCODE_INDEX;
+            if (0 == keyIndex) {
+                keyIndex = ar->arDefTxKeyIndex;
+            } else if ((keyIndex - 1 < WMI_MIN_KEY_INDEX) ||
+                       (keyIndex - 1 > WMI_MAX_KEY_INDEX))
+            {
+                keyIndex = WMI_MIN_KEY_INDEX;
+            } else {
+                keyIndex--;
+            }
+            erq->flags = keyIndex + 1;
+            erq->flags &= ~IW_ENCODE_DISABLED;
+            wk = &ar->arWepKeyList[keyIndex];
+            if (erq->length > wk->arKeyLen) {
+                erq->length = wk->arKeyLen;
+            }
+            if (wk->arKeyLen) {
+                A_MEMCPY(key, wk->arKey, erq->length);
+            }
+        } else {
+            erq->flags &= ~IW_ENCODE_DISABLED;
+            if (ar->user_saved_keys.keyOk) {
+                erq->length = ar->user_saved_keys.ucast_ik.ik_keylen;
+                if (erq->length) {
+                    A_MEMCPY(key, ar->user_saved_keys.ucast_ik.ik_keydata, erq->length);
+                }
+            } else {
+                erq->length = 1;    // not really printing any key but let iwconfig know enc is on
+            }
+        }
+
+        if (ar->arDot11AuthMode & OPEN_AUTH) {
+            erq->flags |= IW_ENCODE_OPEN;
+        }
+        if (ar->arDot11AuthMode & SHARED_AUTH) {
+            erq->flags |= IW_ENCODE_RESTRICTED;
+        }
+    }
+
+    return 0;
+}
+
+#if WIRELESS_EXT >= 18
+/*
+ * SIOCSIWGENIE
+ */
+static int
+ar6000_ioctl_siwgenie(struct net_device *dev,
+              struct iw_request_info *info,
+              struct iw_point *erq, char *extra)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+#ifdef WAPI_ENABLE
+    A_UINT8    *ie = erq->pointer;
+    A_UINT8    ie_type = ie[0];
+    A_UINT16   ie_length = erq->length;
+    A_UINT8    wapi_ie[128];
+#endif
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+#ifdef WAPI_ENABLE
+    if (ie_type == IEEE80211_ELEMID_WAPI) {
+        if (ie_length > 0) {
+            if (copy_from_user(wapi_ie, ie, ie_length)) {
+                return -EIO;
+            }
+        }
+        wmi_set_appie_cmd(ar->arWmi, WMI_FRAME_ASSOC_REQ, ie_length, wapi_ie);
+    } else if (ie_length == 0) {
+        wmi_set_appie_cmd(ar->arWmi, WMI_FRAME_ASSOC_REQ, ie_length, wapi_ie);
+    }
+#endif
+    return 0;
+}
+
+
+/*
+ * SIOCGIWGENIE
+ */
+static int
+ar6000_ioctl_giwgenie(struct net_device *dev,
+              struct iw_request_info *info,
+              struct iw_point *erq, char *extra)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+    erq->length = 0;
+    erq->flags = 0;
+
+    return 0;
+}
+
+/*
+ * SIOCSIWAUTH
+ */
+static int
+ar6000_ioctl_siwauth(struct net_device *dev,
+              struct iw_request_info *info,
+              struct iw_param *data, char *extra)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+    A_BOOL profChanged;
+    A_UINT16 param;
+    A_INT32 ret;
+    A_INT32 value;
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+    if (ar->arWlanState == WLAN_DISABLED) {
+        return -EIO;
+    }
+
+    param = data->flags & IW_AUTH_INDEX;
+    value = data->value;
+    profChanged = TRUE;
+    ret = 0;
+
+    switch (param) {
+        case IW_AUTH_WPA_VERSION:
+            if (value & IW_AUTH_WPA_VERSION_DISABLED) {
+                ar->arAuthMode = NONE_AUTH;
+            } else if (value & IW_AUTH_WPA_VERSION_WPA) {
+                    ar->arAuthMode = WPA_AUTH;
+            } else if (value & IW_AUTH_WPA_VERSION_WPA2) {
+                    ar->arAuthMode = WPA2_AUTH;
+            } else {
+                ret = -1;
+                profChanged    = FALSE;
+            }
+            break;
+        case IW_AUTH_CIPHER_PAIRWISE:
+            if (value & IW_AUTH_CIPHER_NONE) {
+                ar->arPairwiseCrypto = NONE_CRYPT;
+                ar->arPairwiseCryptoLen = 0;
+            } else if (value & IW_AUTH_CIPHER_WEP40) {
+                ar->arPairwiseCrypto = WEP_CRYPT;
+                ar->arPairwiseCryptoLen = 5;
+            } else if (value & IW_AUTH_CIPHER_TKIP) {
+                ar->arPairwiseCrypto = TKIP_CRYPT;
+                ar->arPairwiseCryptoLen = 0;
+            } else if (value & IW_AUTH_CIPHER_CCMP) {
+                ar->arPairwiseCrypto = AES_CRYPT;
+                ar->arPairwiseCryptoLen = 0;
+            } else if (value & IW_AUTH_CIPHER_WEP104) {
+                ar->arPairwiseCrypto = WEP_CRYPT;
+                ar->arPairwiseCryptoLen = 13;
+            } else {
+                ret = -1;
+                profChanged    = FALSE;
+            }
+            break;
+        case IW_AUTH_CIPHER_GROUP:
+            if (value & IW_AUTH_CIPHER_NONE) {
+                ar->arGroupCrypto = NONE_CRYPT;
+                ar->arGroupCryptoLen = 0;
+            } else if (value & IW_AUTH_CIPHER_WEP40) {
+                ar->arGroupCrypto = WEP_CRYPT;
+                ar->arGroupCryptoLen = 5;
+            } else if (value & IW_AUTH_CIPHER_TKIP) {
+                ar->arGroupCrypto = TKIP_CRYPT;
+                ar->arGroupCryptoLen = 0;
+            } else if (value & IW_AUTH_CIPHER_CCMP) {
+                ar->arGroupCrypto = AES_CRYPT;
+                ar->arGroupCryptoLen = 0;
+            } else if (value & IW_AUTH_CIPHER_WEP104) {
+                ar->arGroupCrypto = WEP_CRYPT;
+                ar->arGroupCryptoLen = 13;
+            } else {
+                ret = -1;
+                profChanged    = FALSE;
+            }
+            break;
+        case IW_AUTH_KEY_MGMT:
+            if (value & IW_AUTH_KEY_MGMT_PSK) {
+                if (WPA_AUTH == ar->arAuthMode) {
+                    ar->arAuthMode = WPA_PSK_AUTH;
+                } else if (WPA2_AUTH == ar->arAuthMode) {
+                    ar->arAuthMode = WPA2_PSK_AUTH;
+                } else {
+                    ret = -1;
+                }
+            } else if (!(value & IW_AUTH_KEY_MGMT_802_1X)) {
+                ar->arAuthMode = NONE_AUTH;
+            }
+            break;
+        case IW_AUTH_TKIP_COUNTERMEASURES:
+            wmi_set_tkip_countermeasures_cmd(ar->arWmi, value);
+            profChanged    = FALSE;
+            break;
+        case IW_AUTH_DROP_UNENCRYPTED:
+            profChanged    = FALSE;
+            break;
+        case IW_AUTH_80211_AUTH_ALG:
+            ar->arDot11AuthMode = 0;
+            if (value & IW_AUTH_ALG_OPEN_SYSTEM) {
+                ar->arDot11AuthMode  |= OPEN_AUTH;
+            }
+            if (value & IW_AUTH_ALG_SHARED_KEY) {
+                ar->arDot11AuthMode  |= SHARED_AUTH;
+            }
+            if (value & IW_AUTH_ALG_LEAP) {
+                ar->arDot11AuthMode   = LEAP_AUTH;
+            }
+            if(ar->arDot11AuthMode == 0) {
+                ret = -1;
+                profChanged    = FALSE;
+            }
+            break;
+        case IW_AUTH_WPA_ENABLED:
+            if (!value) {
+                ar->arAuthMode = NONE_AUTH;
+                /* when the supplicant is stopped, it calls this
+                 * handler with value=0. The followings need to be
+                 * reset if the STA were to connect again
+                 * without security
+                 */
+                ar->arDot11AuthMode = OPEN_AUTH;
+                ar->arPairwiseCrypto = NONE_CRYPT;
+                ar->arPairwiseCryptoLen = 0;
+                ar->arGroupCrypto = NONE_CRYPT;
+                ar->arGroupCryptoLen = 0;
+            }
+            break;
+        case IW_AUTH_RX_UNENCRYPTED_EAPOL:
+            profChanged    = FALSE;
+            break;
+        case IW_AUTH_ROAMING_CONTROL:
+            profChanged    = FALSE;
+            break;
+        case IW_AUTH_PRIVACY_INVOKED:
+            if (!value) {
+                ar->arPairwiseCrypto = NONE_CRYPT;
+                ar->arPairwiseCryptoLen = 0;
+                ar->arGroupCrypto = NONE_CRYPT;
+                ar->arGroupCryptoLen = 0;
+            }
+            break;
+#ifdef WAPI_ENABLE
+        case IW_AUTH_WAPI_ENABLED:
+            ar->arWapiEnable = value;
+            break;
+#endif
+        default:
+           ret = -1;
+           profChanged    = FALSE;
+           break;
+    }
+
+    if (profChanged == TRUE) {
+        /*
+         * profile has changed.  Erase ssid to signal change
+         */
+        A_MEMZERO(ar->arSsid, sizeof(ar->arSsid));
+        ar->arSsidLen = 0;
+    }
+
+    return ret;
+}
+
+
+/*
+ * SIOCGIWAUTH
+ */
+static int
+ar6000_ioctl_giwauth(struct net_device *dev,
+              struct iw_request_info *info,
+              struct iw_param *data, char *extra)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    A_UINT16 param;
+    A_INT32 ret;
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+    if (ar->arWlanState == WLAN_DISABLED) {
+        return -EIO;
+    }
+
+    param = data->flags & IW_AUTH_INDEX;
+    ret = 0;
+    data->value = 0;
+
+
+    switch (param) {
+        case IW_AUTH_WPA_VERSION:
+            if (ar->arAuthMode == NONE_AUTH) {
+                data->value |= IW_AUTH_WPA_VERSION_DISABLED;
+            } else if (ar->arAuthMode == WPA_AUTH) {
+                data->value |= IW_AUTH_WPA_VERSION_WPA;
+            } else if (ar->arAuthMode == WPA2_AUTH) {
+                data->value |= IW_AUTH_WPA_VERSION_WPA2;
+            } else {
+                ret = -1;
+            }
+            break;
+        case IW_AUTH_CIPHER_PAIRWISE:
+            if (ar->arPairwiseCrypto == NONE_CRYPT) {
+                data->value |= IW_AUTH_CIPHER_NONE;
+            } else if (ar->arPairwiseCrypto == WEP_CRYPT) {
+                if (ar->arPairwiseCryptoLen == 13) {
+                    data->value |= IW_AUTH_CIPHER_WEP104;
+                } else {
+                    data->value |= IW_AUTH_CIPHER_WEP40;
+                }
+            } else if (ar->arPairwiseCrypto == TKIP_CRYPT) {
+                data->value |= IW_AUTH_CIPHER_TKIP;
+            } else if (ar->arPairwiseCrypto == AES_CRYPT) {
+                data->value |= IW_AUTH_CIPHER_CCMP;
+            } else {
+                ret = -1;
+            }
+            break;
+        case IW_AUTH_CIPHER_GROUP:
+            if (ar->arGroupCrypto == NONE_CRYPT) {
+                    data->value |= IW_AUTH_CIPHER_NONE;
+            } else if (ar->arGroupCrypto == WEP_CRYPT) {
+                if (ar->arGroupCryptoLen == 13) {
+                    data->value |= IW_AUTH_CIPHER_WEP104;
+                } else {
+                    data->value |= IW_AUTH_CIPHER_WEP40;
+                }
+            } else if (ar->arGroupCrypto == TKIP_CRYPT) {
+                data->value |= IW_AUTH_CIPHER_TKIP;
+            } else if (ar->arGroupCrypto == AES_CRYPT) {
+                data->value |= IW_AUTH_CIPHER_CCMP;
+            } else {
+                ret = -1;
+            }
+            break;
+        case IW_AUTH_KEY_MGMT:
+            if ((ar->arAuthMode == WPA_PSK_AUTH) ||
+                (ar->arAuthMode == WPA2_PSK_AUTH)) {
+                data->value |= IW_AUTH_KEY_MGMT_PSK;
+            } else if ((ar->arAuthMode == WPA_AUTH) ||
+                       (ar->arAuthMode == WPA2_AUTH)) {
+                data->value |= IW_AUTH_KEY_MGMT_802_1X;
+            }
+            break;
+        case IW_AUTH_TKIP_COUNTERMEASURES:
+            // TODO. Save countermeassure enable/disable
+            data->value = 0;
+            break;
+        case IW_AUTH_DROP_UNENCRYPTED:
+            break;
+        case IW_AUTH_80211_AUTH_ALG:
+            if (ar->arDot11AuthMode == OPEN_AUTH) {
+                data->value |= IW_AUTH_ALG_OPEN_SYSTEM;
+            } else if (ar->arDot11AuthMode == SHARED_AUTH) {
+                data->value |= IW_AUTH_ALG_SHARED_KEY;
+            } else if (ar->arDot11AuthMode == LEAP_AUTH) {
+                data->value |= IW_AUTH_ALG_LEAP;
+            } else {
+                ret = -1;
+            }
+            break;
+        case IW_AUTH_WPA_ENABLED:
+            if (ar->arAuthMode == NONE_AUTH) {
+                data->value = 0;
+            } else {
+                data->value = 1;
+            }
+            break;
+        case IW_AUTH_RX_UNENCRYPTED_EAPOL:
+            break;
+        case IW_AUTH_ROAMING_CONTROL:
+            break;
+        case IW_AUTH_PRIVACY_INVOKED:
+            if (ar->arPairwiseCrypto == NONE_CRYPT) {
+                data->value = 0;
+            } else {
+                data->value = 1;
+            }
+            break;
+#ifdef WAPI_ENABLE
+        case IW_AUTH_WAPI_ENABLED:
+            data->value = ar->arWapiEnable;
+            break;
+#endif
+        default:
+           ret = -1;
+           break;
+    }
+
+    return 0;
+}
+
+/*
+ * SIOCSIWPMKSA
+ */
+static int
+ar6000_ioctl_siwpmksa(struct net_device *dev,
+              struct iw_request_info *info,
+              struct iw_point *data, char *extra)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    A_INT32 ret;
+    A_STATUS status;
+    struct iw_pmksa *pmksa;
+
+    pmksa = (struct iw_pmksa *)extra;
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+    ret = 0;
+    status = A_OK;
+
+    switch (pmksa->cmd) {
+        case IW_PMKSA_ADD:
+            status = wmi_setPmkid_cmd(ar->arWmi, (A_UINT8*)pmksa->bssid.sa_data, pmksa->pmkid, TRUE);
+            break;
+        case IW_PMKSA_REMOVE:
+            status = wmi_setPmkid_cmd(ar->arWmi, (A_UINT8*)pmksa->bssid.sa_data, pmksa->pmkid, FALSE);
+            break;
+        case IW_PMKSA_FLUSH:
+            if (ar->arConnected == TRUE) {
+                status = wmi_setPmkid_cmd(ar->arWmi, ar->arBssid, NULL, 0);
+            }
+            break;
+        default:
+            ret=-1;
+            break;
+    }
+    if (status != A_OK) {
+        ret = -1;
+    }
+
+    return ret;
+}
+
+#ifdef WAPI_ENABLE
+
+#define PN_INIT 0x5c365c36
+
+static int ar6000_set_wapi_key(struct net_device *dev,
+              struct iw_request_info *info,
+              struct iw_point *erq, char *extra)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    struct iw_encode_ext *ext = (struct iw_encode_ext *)extra;
+    KEY_USAGE   keyUsage = 0;
+    A_INT32     keyLen;
+    A_UINT8     *keyData;
+    A_INT32     index;
+    A_UINT32    *PN;
+    A_INT32     i;
+    A_STATUS    status;
+    A_UINT8     wapiKeyRsc[16];
+    CRYPTO_TYPE keyType = WAPI_CRYPT;
+    const A_UINT8 broadcastMac[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+
+    index = erq->flags & IW_ENCODE_INDEX;
+    if (index && (((index - 1) < WMI_MIN_KEY_INDEX) ||
+                ((index - 1) > WMI_MAX_KEY_INDEX))) {
+        return -EIO;
+    }
+
+    index--;
+    if (index < 0 || index > 4) {
+        return -EIO;
+    }
+    keyData = (A_UINT8 *)(ext + 1);
+    keyLen = erq->length - sizeof(struct iw_encode_ext);
+    A_MEMCPY(wapiKeyRsc, ext->tx_seq, sizeof(wapiKeyRsc));
+
+    if (A_MEMCMP(ext->addr.sa_data, broadcastMac, sizeof(broadcastMac)) == 0) {
+        keyUsage |= GROUP_USAGE;
+        PN = (A_UINT32 *)wapiKeyRsc;
+        for (i = 0; i < 4; i++) {
+            PN[i] = PN_INIT;
+        }
+    } else {
+        keyUsage |= PAIRWISE_USAGE;
+    }
+    status = wmi_addKey_cmd(ar->arWmi,
+                            index,
+                            keyType,
+                            keyUsage,
+                            keyLen,
+                            wapiKeyRsc,
+                            keyData,
+                            KEY_OP_INIT_WAPIPN,
+                            NULL,
+                            SYNC_BEFORE_WMIFLAG);
+    if (A_OK != status) {
+        return -EIO;
+    }
+    return 0;
+}
+
+#endif
+
+/*
+ * SIOCSIWENCODEEXT
+ */
+static int
+ar6000_ioctl_siwencodeext(struct net_device *dev,
+              struct iw_request_info *info,
+              struct iw_point *erq, char *extra)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    A_INT32 index;
+    struct iw_encode_ext *ext;
+    KEY_USAGE keyUsage;
+    A_INT32 keyLen;
+    A_UINT8 *keyData;
+    A_UINT8 keyRsc[8];
+    A_STATUS status;
+    CRYPTO_TYPE keyType;
+#ifdef USER_KEYS
+    struct ieee80211req_key ik;
+#endif /* USER_KEYS */
+
+    if (ar->arWlanState == WLAN_DISABLED) {
+        return -EIO;
+    }
+
+#ifdef USER_KEYS
+    ar->user_saved_keys.keyOk = FALSE;
+#endif /* USER_KEYS */
+
+    index = erq->flags & IW_ENCODE_INDEX;
+
+    if (index && (((index - 1) < WMI_MIN_KEY_INDEX) ||
+                  ((index - 1) > WMI_MAX_KEY_INDEX)))
+    {
+        return -EIO;
+    }
+
+    ext = (struct iw_encode_ext *)extra;
+    if (erq->flags & IW_ENCODE_DISABLED) {
+        /*
+         * Encryption disabled
+         */
+        if (index) {
+            /*
+             * If key index was specified then clear the specified key
+             */
+            index--;
+            A_MEMZERO(ar->arWepKeyList[index].arKey,
+                      sizeof(ar->arWepKeyList[index].arKey));
+            ar->arWepKeyList[index].arKeyLen = 0;
+        }
+    } else {
+        /*
+         * Enabling WEP encryption
+         */
+        if (index) {
+            index--;                /* keyindex is off base 1 in iwconfig */
+        }
+
+        keyUsage = 0;
+        keyLen = erq->length - sizeof(struct iw_encode_ext);
+
+        if (ext->ext_flags & IW_ENCODE_EXT_SET_TX_KEY) {
+            keyUsage = TX_USAGE;
+            ar->arDefTxKeyIndex = index;
+            // Just setting the key index
+            if (keyLen == 0) {
+                return 0;
+            }
+        }
+
+        if (keyLen <= 0) {
+            return -EIO;
+        }
+
+        /* key follows iw_encode_ext */
+        keyData = (A_UINT8 *)(ext + 1);
+
+        switch (ext->alg) {
+            case IW_ENCODE_ALG_WEP:
+                keyType = WEP_CRYPT;
+#ifdef USER_KEYS
+                ik.ik_type = IEEE80211_CIPHER_WEP;
+#endif /* USER_KEYS */
+                if (!IEEE80211_IS_VALID_WEP_CIPHER_LEN(keyLen)) {
+                    return -EIO;
+                }
+
+                /* Check whether it is static wep. */
+                if (!ar->arConnected) {
+                    A_MEMZERO(ar->arWepKeyList[index].arKey,
+                          sizeof(ar->arWepKeyList[index].arKey));
+                    A_MEMCPY(ar->arWepKeyList[index].arKey, keyData, keyLen);
+                    ar->arWepKeyList[index].arKeyLen = keyLen;
+
+                    return 0;
+                }
+                break;
+            case IW_ENCODE_ALG_TKIP:
+                keyType = TKIP_CRYPT;
+#ifdef USER_KEYS
+                ik.ik_type = IEEE80211_CIPHER_TKIP;
+#endif /* USER_KEYS */
+                break;
+            case IW_ENCODE_ALG_CCMP:
+                keyType = AES_CRYPT;
+#ifdef USER_KEYS
+                ik.ik_type = IEEE80211_CIPHER_AES_CCM;
+#endif /* USER_KEYS */
+                break;
+#ifdef WAPI_ENABLE
+            case IW_ENCODE_ALG_SM4:
+                if (ar->arWapiEnable) {
+                    return ar6000_set_wapi_key(dev, info, erq, extra);
+                } else {
+                    return -EIO;
+                }
+#endif
+            case IW_ENCODE_ALG_PMK:
+                ar->arConnectCtrlFlags |= CONNECT_DO_WPA_OFFLOAD;
+                return wmi_set_pmk_cmd(ar->arWmi, keyData);
+            default:
+                return -EIO;
+        }
+
+
+        if (ext->ext_flags & IW_ENCODE_EXT_GROUP_KEY) {
+            keyUsage |= GROUP_USAGE;
+        } else {
+            keyUsage |= PAIRWISE_USAGE;
+        }
+
+        if (ext->ext_flags & IW_ENCODE_EXT_RX_SEQ_VALID) {
+            A_MEMCPY(keyRsc, ext->rx_seq, sizeof(keyRsc));
+        } else {
+            A_MEMZERO(keyRsc, sizeof(keyRsc));
+        }
+
+        if (((WPA_PSK_AUTH == ar->arAuthMode) || (WPA2_PSK_AUTH == ar->arAuthMode)) &&
+            (GROUP_USAGE & keyUsage))
+        {
+            A_UNTIMEOUT(&ar->disconnect_timer);
+        }
+
+         status = wmi_addKey_cmd(ar->arWmi, index, keyType, keyUsage,
+                            keyLen, keyRsc,
+                            keyData, KEY_OP_INIT_VAL,
+                            (A_UINT8*)ext->addr.sa_data,
+                            SYNC_BOTH_WMIFLAG);
+         if (status != A_OK) {
+            return -EIO;
+         }
+
+#ifdef USER_KEYS
+        ik.ik_keyix = index;
+        ik.ik_keylen = keyLen;
+        memcpy(ik.ik_keydata, keyData, keyLen);
+        memcpy(&ik.ik_keyrsc, keyRsc, sizeof(keyRsc));
+        memcpy(ik.ik_macaddr, ext->addr.sa_data, ETH_ALEN);
+        if (ext->ext_flags & IW_ENCODE_EXT_GROUP_KEY) {
+            memcpy(&ar->user_saved_keys.bcast_ik, &ik,
+                       sizeof(struct ieee80211req_key));
+        } else {
+            memcpy(&ar->user_saved_keys.ucast_ik, &ik,
+                      sizeof(struct ieee80211req_key));
+        }
+        ar->user_saved_keys.keyOk = TRUE;
+#endif /* USER_KEYS */
+    }
+
+
+    return 0;
+}
+
+/*
+ * SIOCGIWENCODEEXT
+ */
+static int
+ar6000_ioctl_giwencodeext(struct net_device *dev,
+              struct iw_request_info *info,
+              struct iw_point *erq, char *extra)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+    if (ar->arWlanState == WLAN_DISABLED) {
+        return -EIO;
+    }
+
+    if (ar->arPairwiseCrypto == NONE_CRYPT) {
+        erq->length = 0;
+        erq->flags = IW_ENCODE_DISABLED;
+    } else {
+        erq->length = 0;
+    }
+
+    return 0;
+}
+#endif // WIRELESS_EXT >= 18
+
+#if WIRELESS_EXT > 20
+static int ar6000_ioctl_siwpower(struct net_device *dev,
+                 struct iw_request_info *info,
+                 union iwreq_data *wrqu, char *extra)
+{
+#ifndef ATH6K_CONFIG_OTA_MODE
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    WMI_POWER_MODE power_mode;
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+    if (ar->arWlanState == WLAN_DISABLED) {
+        return -EIO;
+    }
+
+    if (wrqu->power.disabled)
+        power_mode = MAX_PERF_POWER;
+    else
+        power_mode = REC_POWER;
+
+    if (wmi_powermode_cmd(ar->arWmi, power_mode) < 0)
+        return -EIO;
+#endif
+    return 0;
+}
+
+static int ar6000_ioctl_giwpower(struct net_device *dev,
+                 struct iw_request_info *info,
+                 union iwreq_data *wrqu, char *extra)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    WMI_POWER_MODE power_mode;
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+    if (ar->arWlanState == WLAN_DISABLED) {
+        return -EIO;
+    }
+
+    power_mode = wmi_get_power_mode_cmd(ar->arWmi);
+
+    if (power_mode == MAX_PERF_POWER)
+        wrqu->power.disabled = 1;
+    else
+        wrqu->power.disabled = 0;
+
+    return 0;
+}
+#endif // WIRELESS_EXT > 20
+
+/*
+ * SIOCGIWNAME
+ */
+int
+ar6000_ioctl_giwname(struct net_device *dev,
+           struct iw_request_info *info,
+           char *name, char *extra)
+{
+    A_UINT8 capability;
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+    if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) {
+        A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
+        return -EOPNOTSUPP;
+    }
+
+    if (ar->arWlanState == WLAN_DISABLED) {
+        return -EIO;
+    }
+
+    capability = ar->arPhyCapability;
+    if(ar->arNetworkType == INFRA_NETWORK && ar->arConnected) {
+        bss_t *bss = wmi_find_node(ar->arWmi, ar->arBssid);
+        if (bss) {
+            capability = get_bss_phy_capability(bss);
+            wmi_node_return(ar->arWmi, bss);
+        }
+    }
+    switch (capability) {
+    case (WMI_11A_CAPABILITY):
+        strncpy(name, "AR6000 802.11a", IFNAMSIZ);
+        break;
+    case (WMI_11G_CAPABILITY):
+        strncpy(name, "AR6000 802.11g", IFNAMSIZ);
+        break;
+    case (WMI_11AG_CAPABILITY):
+        strncpy(name, "AR6000 802.11ag", IFNAMSIZ);
+        break;
+    case (WMI_11NA_CAPABILITY):
+        strncpy(name, "AR6000 802.11na", IFNAMSIZ);
+        break;
+    case (WMI_11NG_CAPABILITY):
+        strncpy(name, "AR6000 802.11ng", IFNAMSIZ);
+        break;
+    case (WMI_11NAG_CAPABILITY):
+        strncpy(name, "AR6000 802.11nag", IFNAMSIZ);
+        break;
+    default:
+        strncpy(name, "AR6000 802.11b", IFNAMSIZ);
+        break;
+    }
+
+    return 0;
+}
+
+/*
+ * SIOCSIWFREQ
+ */
+int
+ar6000_ioctl_siwfreq(struct net_device *dev,
+            struct iw_request_info *info,
+            struct iw_freq *freq, char *extra)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+    if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) {
+        A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
+        return -EOPNOTSUPP;
+    }
+
+    if (ar->arWlanState == WLAN_DISABLED) {
+        return -EIO;
+    }
+
+    /*
+     * We support limiting the channels via wmiconfig.
+     *
+     * We use this command to configure the channel hint for the connect cmd
+     * so it is possible the target will end up connecting to a different
+     * channel.
+     */
+    if (freq->e > 1) {
+        return -EINVAL;
+    } else if (freq->e == 1) {
+        ar->arChannelHint = freq->m / 100000;
+    } else {
+        if(freq->m) {
+            ar->arChannelHint = wlan_ieee2freq(freq->m);
+        } else {
+            /* Auto Channel Selection */
+            ar->arChannelHint = 0;
+        }
+    }
+
+    ar->ap_profile_flag = 1; /* There is a change in profile */
+
+    A_PRINTF("channel hint set to %d\n", ar->arChannelHint);
+    return 0;
+}
+
+/*
+ * SIOCGIWFREQ
+ */
+int
+ar6000_ioctl_giwfreq(struct net_device *dev,
+                struct iw_request_info *info,
+                struct iw_freq *freq, char *extra)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+    if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) {
+        A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
+        return -EOPNOTSUPP;
+    }
+
+    if (ar->arWlanState == WLAN_DISABLED) {
+        return -EIO;
+    }
+
+    if (ar->arNetworkType == AP_NETWORK) {
+        if(ar->arChannelHint) {
+            freq->m = ar->arChannelHint * 100000;
+        } else if(ar->arACS) {
+            freq->m = ar->arACS * 100000;
+        } else {
+            return -EINVAL;
+        }
+    } else {
+        if (ar->arConnected != TRUE) {
+            return -EINVAL;
+        } else {
+            freq->m = ar->arBssChannel * 100000;
+        }
+    }
+
+    freq->e = 1;
+
+    return 0;
+}
+
+/*
+ * SIOCSIWMODE
+ */
+int
+ar6000_ioctl_siwmode(struct net_device *dev,
+            struct iw_request_info *info,
+            __u32 *mode, char *extra)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+    if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) {
+        A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
+        return -EOPNOTSUPP;
+    }
+
+    if (ar->arWlanState == WLAN_DISABLED) {
+        return -EIO;
+    }
+
+    /*
+     * clear SSID during mode switch in connected state
+     */
+    if(!(ar->arNetworkType == (((*mode) == IW_MODE_INFRA) ? INFRA_NETWORK : ADHOC_NETWORK)) && (ar->arConnected == TRUE) ){
+        A_MEMZERO(ar->arSsid, sizeof(ar->arSsid));
+        ar->arSsidLen = 0;
+    }
+
+    switch (*mode) {
+    case IW_MODE_INFRA:
+        ar->arNextMode = INFRA_NETWORK;
+        break;
+    case IW_MODE_ADHOC:
+        ar->arNextMode = ADHOC_NETWORK;
+        break;
+    case IW_MODE_MASTER:
+        ar->arNextMode = AP_NETWORK;
+        break;
+    default:
+        return -EINVAL;
+    }
+
+    /* clear all shared parameters between AP and STA|IBSS modes when we
+     * switch between them. Switch between STA & IBSS modes does'nt clear
+     * the shared profile. This is as per the original design for switching
+     * between STA & IBSS.
+     */
+    if (ar->arNetworkType == AP_NETWORK || ar->arNextMode == AP_NETWORK) {
+        ar->arDot11AuthMode      = OPEN_AUTH;
+        ar->arAuthMode           = NONE_AUTH;
+        ar->arPairwiseCrypto     = NONE_CRYPT;
+        ar->arPairwiseCryptoLen  = 0;
+        ar->arGroupCrypto        = NONE_CRYPT;
+        ar->arGroupCryptoLen     = 0;
+        ar->arChannelHint        = 0;
+        ar->arBssChannel         = 0;
+        A_MEMZERO(ar->arBssid, sizeof(ar->arBssid));
+        A_MEMZERO(ar->arSsid, sizeof(ar->arSsid));
+        ar->arSsidLen = 0;
+    }
+
+    /* SSID has to be cleared to trigger a profile change while switching
+     * between STA & IBSS modes having the same SSID
+     */
+    if (ar->arNetworkType != ar->arNextMode) {
+        A_MEMZERO(ar->arSsid, sizeof(ar->arSsid));
+        ar->arSsidLen = 0;
+    }
+
+    return 0;
+}
+
+/*
+ * SIOCGIWMODE
+ */
+int
+ar6000_ioctl_giwmode(struct net_device *dev,
+            struct iw_request_info *info,
+            __u32 *mode, char *extra)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+    if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) {
+        A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
+        return -EOPNOTSUPP;
+    }
+
+    if (ar->arWlanState == WLAN_DISABLED) {
+        return -EIO;
+    }
+
+    switch (ar->arNetworkType) {
+    case INFRA_NETWORK:
+        *mode = IW_MODE_INFRA;
+        break;
+    case ADHOC_NETWORK:
+        *mode = IW_MODE_ADHOC;
+        break;
+    case AP_NETWORK:
+        *mode = IW_MODE_MASTER;
+        break;
+    default:
+        return -EIO;
+    }
+    return 0;
+}
+
+/*
+ * SIOCSIWSENS
+ */
+int
+ar6000_ioctl_siwsens(struct net_device *dev,
+            struct iw_request_info *info,
+            struct iw_param *sens, char *extra)
+{
+    return 0;
+}
+
+/*
+ * SIOCGIWSENS
+ */
+int
+ar6000_ioctl_giwsens(struct net_device *dev,
+            struct iw_request_info *info,
+            struct iw_param *sens, char *extra)
+{
+    sens->value = 0;
+    sens->fixed = 1;
+
+    return 0;
+}
+
+/*
+ * SIOCGIWRANGE
+ */
+int
+ar6000_ioctl_giwrange(struct net_device *dev,
+             struct iw_request_info *info,
+             struct iw_point *data, char *extra)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    struct iw_range *range = (struct iw_range *) extra;
+    int i, ret = 0;
+
+    if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) {
+        A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
+        return -EOPNOTSUPP;
+    }
+
+    if (ar->bIsDestroyProgress) {
+        return -EBUSY;
+    }
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+    if (down_interruptible(&ar->arSem)) {
+        return -ERESTARTSYS;
+    }
+
+    if (ar->bIsDestroyProgress) {
+        up(&ar->arSem);
+        return -EBUSY;
+    }
+
+    ar->arNumChannels = -1;
+    A_MEMZERO(ar->arChannelList, sizeof (ar->arChannelList));
+
+    if (wmi_get_channelList_cmd(ar->arWmi) != A_OK) {
+        up(&ar->arSem);
+        return -EIO;
+    }
+
+    wait_event_interruptible_timeout(arEvent, ar->arNumChannels != -1, wmitimeout * HZ);
+
+    if (signal_pending(current)) {
+        up(&ar->arSem);
+        return -EINTR;
+    }
+
+    data->length = sizeof(struct iw_range);
+    A_MEMZERO(range, sizeof(struct iw_range));
+
+    range->txpower_capa = 0;
+
+    range->min_pmp = 1 * 1024;
+    range->max_pmp = 65535 * 1024;
+    range->min_pmt = 1 * 1024;
+    range->max_pmt = 1000 * 1024;
+    range->pmp_flags = IW_POWER_PERIOD;
+    range->pmt_flags = IW_POWER_TIMEOUT;
+    range->pm_capa = 0;
+
+    range->we_version_compiled = WIRELESS_EXT;
+    range->we_version_source = 13;
+
+    range->retry_capa = IW_RETRY_LIMIT;
+    range->retry_flags = IW_RETRY_LIMIT;
+    range->min_retry = 0;
+    range->max_retry = 255;
+
+    range->num_frequency = range->num_channels = ar->arNumChannels;
+    for (i = 0; i < ar->arNumChannels; i++) {
+        range->freq[i].i = wlan_freq2ieee(ar->arChannelList[i]);
+        range->freq[i].m = ar->arChannelList[i] * 100000;
+        range->freq[i].e = 1;
+         /*
+         * Linux supports max of 32 channels, bail out once you
+         * reach the max.
+         */
+        if (i == IW_MAX_FREQUENCIES) {
+            break;
+        }
+    }
+
+    /* Max quality is max field value minus noise floor */
+    range->max_qual.qual  = 0xff - 161;
+
+    /*
+     * In order to use dBm measurements, 'level' must be lower
+     * than any possible measurement (see iw_print_stats() in
+     * wireless tools).  It's unclear how this is meant to be
+     * done, but setting zero in these values forces dBm and
+     * the actual numbers are not used.
+     */
+    range->max_qual.level = 0;
+    range->max_qual.noise = 0;
+
+    range->sensitivity = 3;
+
+    range->max_encoding_tokens = 4;
+    /* XXX query driver to find out supported key sizes */
+    range->num_encoding_sizes = 3;
+    range->encoding_size[0] = 5;        /* 40-bit */
+    range->encoding_size[1] = 13;       /* 104-bit */
+    range->encoding_size[2] = 16;       /* 128-bit */
+
+    range->num_bitrates = 0;
+
+    /* estimated maximum TCP throughput values (bps) */
+    range->throughput = 22000000;
+
+    range->min_rts = 0;
+    range->max_rts = 2347;
+    range->min_frag = 256;
+    range->max_frag = 2346;
+
+    up(&ar->arSem);
+
+    return ret;
+}
+
+
+/*
+ * SIOCSIWAP
+ * This ioctl is used to set the desired bssid for the connect command.
+ */
+int
+ar6000_ioctl_siwap(struct net_device *dev,
+              struct iw_request_info *info,
+              struct sockaddr *ap_addr, char *extra)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+    if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) {
+        A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
+        return -EOPNOTSUPP;
+    }
+
+    if (ar->arWlanState == WLAN_DISABLED) {
+        return -EIO;
+    }
+
+    if (ap_addr->sa_family != ARPHRD_ETHER) {
+        return -EIO;
+    }
+
+    if (A_MEMCMP(&ap_addr->sa_data, bcast_mac, AR6000_ETH_ADDR_LEN) == 0) {
+        A_MEMZERO(ar->arReqBssid, sizeof(ar->arReqBssid));
+    } else {
+        A_MEMCPY(ar->arReqBssid, &ap_addr->sa_data,  sizeof(ar->arReqBssid));
+    }
+
+    return 0;
+}
+
+/*
+ * SIOCGIWAP
+ */
+int
+ar6000_ioctl_giwap(struct net_device *dev,
+              struct iw_request_info *info,
+              struct sockaddr *ap_addr, char *extra)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+    if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) {
+        A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
+        return -EOPNOTSUPP;
+    }
+
+    if (ar->arWlanState == WLAN_DISABLED) {
+        return -EIO;
+    }
+
+    if (ar->arNetworkType == AP_NETWORK) {
+        A_MEMCPY(&ap_addr->sa_data, dev->dev_addr, ATH_MAC_LEN);
+        ap_addr->sa_family = ARPHRD_ETHER;
+        return 0;
+    }
+
+    if (ar->arConnected != TRUE) {
+        return -EINVAL;
+    }
+
+    A_MEMCPY(&ap_addr->sa_data, ar->arBssid, sizeof(ar->arBssid));
+    ap_addr->sa_family = ARPHRD_ETHER;
+
+    return 0;
+}
+
+#if (WIRELESS_EXT >= 18)
+/*
+ * SIOCSIWMLME
+ */
+int
+ar6000_ioctl_siwmlme(struct net_device *dev,
+            struct iw_request_info *info,
+            struct iw_point *data, char *extra)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+    if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) {
+        A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
+        return -EOPNOTSUPP;
+    }
+
+    if (ar->bIsDestroyProgress) {
+        return -EBUSY;
+    }
+
+    if (ar->arWlanState == WLAN_DISABLED) {
+        return -EIO;
+    }
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+    if (down_interruptible(&ar->arSem)) {
+        return -ERESTARTSYS;
+    }
+
+    if (data->pointer && data->length == sizeof(struct iw_mlme)) {
+
+        A_UINT8 arNetworkType;
+        struct iw_mlme mlme;
+
+        if (copy_from_user(&mlme, data->pointer, sizeof(struct iw_mlme)))
+            return -EIO;
+
+        switch (mlme.cmd) {
+
+            case IW_MLME_DEAUTH:
+                /* fall through */
+            case IW_MLME_DISASSOC:
+                if ((ar->arConnected != TRUE) ||
+                    (memcmp(ar->arBssid, mlme.addr.sa_data, 6) != 0)) {
+
+                    up(&ar->arSem);
+                    return -EINVAL;
+                }
+                wmi_setPmkid_cmd(ar->arWmi, ar->arBssid, NULL, 0);
+                arNetworkType = ar->arNetworkType;
+                ar6000_init_profile_info(ar);
+                ar->arNetworkType = arNetworkType;
+                reconnect_flag = 0;
+                wmi_disconnect_cmd(ar->arWmi);
+                A_MEMZERO(ar->arSsid, sizeof(ar->arSsid));
+                ar->arSsidLen = 0;
+                if (ar->arSkipScan == FALSE) {
+                    A_MEMZERO(ar->arReqBssid, sizeof(ar->arReqBssid));
+                }
+                break;
+
+            case IW_MLME_AUTH:
+                /* fall through */
+            case IW_MLME_ASSOC:
+                /* fall through */
+            default:
+                up(&ar->arSem);
+                return -EOPNOTSUPP;
+        }
+    }
+
+    up(&ar->arSem);
+    return 0;
+}
+#endif /* WIRELESS_EXT >= 18 */
+
+/*
+ * SIOCGIWAPLIST
+ */
+int
+ar6000_ioctl_iwaplist(struct net_device *dev,
+            struct iw_request_info *info,
+            struct iw_point *data, char *extra)
+{
+    return -EIO;            /* for now */
+}
+
+/*
+ * SIOCSIWSCAN
+ */
+int
+ar6000_ioctl_siwscan(struct net_device *dev,
+                     struct iw_request_info *info,
+                     struct iw_point *data, char *extra)
+{
+#define ACT_DWELLTIME_DEFAULT   105
+#define HOME_TXDRAIN_TIME       100
+#define SCAN_INT                HOME_TXDRAIN_TIME + ACT_DWELLTIME_DEFAULT
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    int ret = 0;
+
+    if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) {
+        A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
+        return -EOPNOTSUPP;
+    }
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+    if (ar->arWlanState == WLAN_DISABLED) {
+        return -EIO;
+    }
+
+    /* If scan is issued in the middle of ongoing scan or connect,
+       dont issue another one */
+    if ( ar->scan_triggered > 0 ) {
+        ++ar->scan_triggered;
+        if (ar->scan_triggered < 5) {
+            return 0;
+        } else {
+            AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_SCAN,("Scan request is triggered over 5 times. Not scan complete event\n"));
+        }
+    } 
+
+    if (!ar->arUserBssFilter) {
+        if (wmi_bssfilter_cmd(ar->arWmi, ALL_BSS_FILTER, 0) != A_OK) {
+            return -EIO;
+        }
+    }
+
+    if (ar->arConnected) {
+        if  (wmi_get_stats_cmd(ar->arWmi) != A_OK) {
+            return -EIO;
+        }
+    }
+
+#ifdef ANDROID_ENV
+#if WIRELESS_EXT >= 18
+    if (data->pointer && (data->length == sizeof(struct iw_scan_req)))
+    {
+        if ((data->flags & IW_SCAN_THIS_ESSID) == IW_SCAN_THIS_ESSID)
+        {
+            struct iw_scan_req req;
+            if (copy_from_user(&req, data->pointer, sizeof(struct iw_scan_req)))
+                return -EIO;
+            if (wmi_probedSsid_cmd(ar->arWmi, 1, SPECIFIC_SSID_FLAG, req.essid_len, req.essid) != A_OK)
+                return -EIO;
+            ar->scanSpecificSsid = 1;
+        }
+        else
+        {
+            if (ar->scanSpecificSsid) {
+                if (wmi_probedSsid_cmd(ar->arWmi, 1, DISABLE_SSID_FLAG, 0, NULL) != A_OK)
+                    return -EIO;
+                 ar->scanSpecificSsid = 0;
+            }
+        }
+    }
+    else
+    {
+        if (ar->scanSpecificSsid) {
+            if (wmi_probedSsid_cmd(ar->arWmi, 1, DISABLE_SSID_FLAG, 0, NULL) != A_OK)
+                return -EIO;
+             ar->scanSpecificSsid = 0;
+        }
+    }
+#endif
+#endif /* ANDROID_ENV */
+
+    if (wmi_startscan_cmd(ar->arWmi, WMI_LONG_SCAN, FALSE, FALSE, \
+                          0, 0, 0, NULL) != A_OK) {
+        ret = -EIO;
+    }
+
+    if (ret == 0) {
+        ar->scan_triggered = 1;
+    }
+
+    return ret;
+#undef  ACT_DWELLTIME_DEFAULT
+#undef HOME_TXDRAIN_TIME
+#undef SCAN_INT
+}
+
+
+/*
+ * Units are in db above the noise floor. That means the
+ * rssi values reported in the tx/rx descriptors in the
+ * driver are the SNR expressed in db.
+ *
+ * If you assume that the noise floor is -95, which is an
+ * excellent assumption 99.5 % of the time, then you can
+ * derive the absolute signal level (i.e. -95 + rssi).
+ * There are some other slight factors to take into account
+ * depending on whether the rssi measurement is from 11b,
+ * 11g, or 11a.   These differences are at most 2db and
+ * can be documented.
+ *
+ * NB: various calculations are based on the orinoco/wavelan
+ *     drivers for compatibility
+ */
+static void
+ar6000_set_quality(struct iw_quality *iq, A_INT8 rssi)
+{
+    if (rssi < 0) {
+        iq->qual = 0;
+    } else {
+        iq->qual = rssi;
+    }
+
+    /* NB: max is 94 because noise is hardcoded to 161 */
+    if (iq->qual > 94)
+        iq->qual = 94;
+
+    iq->noise = 161;        /* -95dBm */
+    iq->level = iq->noise + iq->qual;
+    iq->updated = 7;
+}
+
+
+int
+ar6000_ioctl_siwcommit(struct net_device *dev,
+                     struct iw_request_info *info,
+                     struct iw_point *data, char *extra)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+    if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) {
+        A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
+        return -EOPNOTSUPP;
+    }
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+    if (ar->arWlanState == WLAN_DISABLED) {
+        return -EIO;
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("AP: SSID %s freq %d authmode %d dot11 auth %d"\
+                    " PW crypto %d GRP crypto %d\n",
+                    ar->arSsid, ar->arChannelHint,
+                    ar->arAuthMode, ar->arDot11AuthMode,
+                    ar->arPairwiseCrypto, ar->arGroupCrypto));
+
+    ar6000_ap_mode_profile_commit(ar);
+
+    /* if there is a profile switch from STA|IBSS mode to AP mode,
+     * update the host driver association state for the STA|IBSS mode.
+     */
+    if (ar->arNetworkType != AP_NETWORK && ar->arNextMode == AP_NETWORK) {
+        ar->arConnectPending = FALSE;
+        ar->arConnected = FALSE;
+        /* Stop getting pkts from upper stack */
+        netif_stop_queue(ar->arNetDev);
+        A_MEMZERO(ar->arBssid, sizeof(ar->arBssid));
+        ar->arBssChannel = 0;
+        ar->arBeaconInterval = 0;
+
+        /* Flush the Tx queues */
+        ar6000_TxDataCleanup(ar);
+
+        /* Start getting pkts from upper stack */
+        netif_wake_queue(ar->arNetDev);
+    }
+
+    return 0;
+}
+
+#define W_PROTO(_x) wait_ ## _x
+#define WAIT_HANDLER_IMPL(_x, type) \
+int wait_ ## _x (struct net_device *dev, struct iw_request_info *info, type wrqu, char *extra) {\
+    int ret; \
+    dev_hold(dev); \
+    rtnl_unlock(); \
+    ret = _x(dev, info, wrqu, extra); \
+    rtnl_lock(); \
+    dev_put(dev); \
+    return ret;\
+}
+
+WAIT_HANDLER_IMPL(ar6000_ioctl_siwessid, struct iw_point *)
+WAIT_HANDLER_IMPL(ar6000_ioctl_giwrate, struct iw_param *)
+WAIT_HANDLER_IMPL(ar6000_ioctl_giwtxpow, struct iw_param *)
+WAIT_HANDLER_IMPL(ar6000_ioctl_giwrange, struct iw_point*)
+
+/* Structures to export the Wireless Handlers */
+static const iw_handler ath_handlers[] = {
+    (iw_handler) ar6000_ioctl_siwcommit,        /* SIOCSIWCOMMIT */
+    (iw_handler) ar6000_ioctl_giwname,          /* SIOCGIWNAME */
+    (iw_handler) NULL,                          /* SIOCSIWNWID */
+    (iw_handler) NULL,                          /* SIOCGIWNWID */
+    (iw_handler) ar6000_ioctl_siwfreq,          /* SIOCSIWFREQ */
+    (iw_handler) ar6000_ioctl_giwfreq,          /* SIOCGIWFREQ */
+    (iw_handler) ar6000_ioctl_siwmode,          /* SIOCSIWMODE */
+    (iw_handler) ar6000_ioctl_giwmode,          /* SIOCGIWMODE */
+    (iw_handler) ar6000_ioctl_siwsens,          /* SIOCSIWSENS */
+    (iw_handler) ar6000_ioctl_giwsens,          /* SIOCGIWSENS */
+    (iw_handler) NULL /* not _used */,          /* SIOCSIWRANGE */
+    (iw_handler) W_PROTO(ar6000_ioctl_giwrange),/* SIOCGIWRANGE */
+    (iw_handler) NULL /* not used */,           /* SIOCSIWPRIV */
+    (iw_handler) NULL /* kernel code */,        /* SIOCGIWPRIV */
+    (iw_handler) NULL /* not used */,           /* SIOCSIWSTATS */
+    (iw_handler) NULL /* kernel code */,        /* SIOCGIWSTATS */
+    (iw_handler) NULL,                          /* SIOCSIWSPY */
+    (iw_handler) NULL,                          /* SIOCGIWSPY */
+    (iw_handler) NULL,                          /* SIOCSIWTHRSPY */
+    (iw_handler) NULL,                          /* SIOCGIWTHRSPY */
+    (iw_handler) ar6000_ioctl_siwap,            /* SIOCSIWAP */
+    (iw_handler) ar6000_ioctl_giwap,            /* SIOCGIWAP */
+#if (WIRELESS_EXT >= 18)
+    (iw_handler) ar6000_ioctl_siwmlme,          /* SIOCSIWMLME */
+#else
+    (iw_handler) NULL,                          /* -- hole -- */
+#endif  /* WIRELESS_EXT >= 18 */
+    (iw_handler) ar6000_ioctl_iwaplist,         /* SIOCGIWAPLIST */
+    (iw_handler) ar6000_ioctl_siwscan,          /* SIOCSIWSCAN */
+    (iw_handler) ar6000_ioctl_giwscan,          /* SIOCGIWSCAN */
+    (iw_handler) W_PROTO(ar6000_ioctl_siwessid),/* SIOCSIWESSID */
+    (iw_handler) ar6000_ioctl_giwessid,         /* SIOCGIWESSID */
+    (iw_handler) NULL,                          /* SIOCSIWNICKN */
+    (iw_handler) NULL,                          /* SIOCGIWNICKN */
+    (iw_handler) NULL,                          /* -- hole -- */
+    (iw_handler) NULL,                          /* -- hole -- */
+    (iw_handler) ar6000_ioctl_siwrate,          /* SIOCSIWRATE */
+    (iw_handler) W_PROTO(ar6000_ioctl_giwrate), /* SIOCGIWRATE */
+    (iw_handler) NULL,                          /* SIOCSIWRTS */
+    (iw_handler) NULL,                          /* SIOCGIWRTS */
+    (iw_handler) NULL,                          /* SIOCSIWFRAG */
+    (iw_handler) NULL,                          /* SIOCGIWFRAG */
+    (iw_handler) ar6000_ioctl_siwtxpow,         /* SIOCSIWTXPOW */
+    (iw_handler) W_PROTO(ar6000_ioctl_giwtxpow),/* SIOCGIWTXPOW */
+    (iw_handler) ar6000_ioctl_siwretry,         /* SIOCSIWRETRY */
+    (iw_handler) ar6000_ioctl_giwretry,         /* SIOCGIWRETRY */
+    (iw_handler) ar6000_ioctl_siwencode,        /* SIOCSIWENCODE */
+    (iw_handler) ar6000_ioctl_giwencode,        /* SIOCGIWENCODE */
+#if WIRELESS_EXT > 20
+    (iw_handler) ar6000_ioctl_siwpower,         /* SIOCSIWPOWER */
+    (iw_handler) ar6000_ioctl_giwpower,         /* SIOCGIWPOWER */
+#endif // WIRELESS_EXT > 20
+#if WIRELESS_EXT >= 18
+    (iw_handler) NULL,                          /* -- hole -- */
+    (iw_handler) NULL,                          /* -- hole -- */
+    (iw_handler) ar6000_ioctl_siwgenie,         /* SIOCSIWGENIE */
+    (iw_handler) ar6000_ioctl_giwgenie,         /* SIOCGIWGENIE */
+    (iw_handler) ar6000_ioctl_siwauth,          /* SIOCSIWAUTH */
+    (iw_handler) ar6000_ioctl_giwauth,          /* SIOCGIWAUTH */
+    (iw_handler) ar6000_ioctl_siwencodeext,     /* SIOCSIWENCODEEXT */
+    (iw_handler) ar6000_ioctl_giwencodeext,     /* SIOCGIWENCODEEXT */
+    (iw_handler) ar6000_ioctl_siwpmksa,         /* SIOCSIWPMKSA */
+#endif // WIRELESS_EXT >= 18
+};
+
+struct iw_handler_def ath_iw_handler_def = {
+    .standard         = (iw_handler *)ath_handlers,
+    .num_standard     = ARRAY_SIZE(ath_handlers),
+    .private          = NULL,
+    .num_private      = 0,
+};
diff --git a/drivers/net/ath6kl/reorder/aggr_rx_internal.h b/drivers/net/ath6kl/reorder/aggr_rx_internal.h
new file mode 100644
index 00000000000..5dbf8f86f71
--- /dev/null
+++ b/drivers/net/ath6kl/reorder/aggr_rx_internal.h
@@ -0,0 +1,116 @@
+/*
+ *
+ * Copyright (c) 2004-2010 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ * 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+ *
+ */
+
+#ifndef __AGGR_RX_INTERNAL_H__
+#define __AGGR_RX_INTERNAL_H__
+
+#include "a_osapi.h"
+#include "aggr_recv_api.h"
+
+#define AGGR_WIN_IDX(x, y)          ((x) % (y))
+#define AGGR_INCR_IDX(x, y)         AGGR_WIN_IDX(((x)+1), (y))
+#define AGGR_DCRM_IDX(x, y)         AGGR_WIN_IDX(((x)-1), (y))
+#define IEEE80211_MAX_SEQ_NO        0xFFF
+#define IEEE80211_NEXT_SEQ_NO(x)    (((x) + 1) & IEEE80211_MAX_SEQ_NO)
+
+
+#define NUM_OF_TIDS         8
+#define AGGR_SZ_DEFAULT     8
+
+#define AGGR_WIN_SZ_MIN     2
+#define AGGR_WIN_SZ_MAX     8
+/* TID Window sz is double of what is negotiated. Derive TID_WINDOW_SZ from win_sz, per tid */
+#define TID_WINDOW_SZ(_x)   ((_x) << 1)
+
+#define AGGR_NUM_OF_FREE_NETBUFS    16
+
+#define AGGR_GET_RXTID_STATS(_p, _x)    (&(_p->stat[(_x)]))
+#define AGGR_GET_RXTID(_p, _x)    (&(_p->RxTid[(_x)]))
+
+/* Hold q is a function of win_sz, which is negotiated per tid */
+#define HOLD_Q_SZ(_x)   (TID_WINDOW_SZ((_x))*sizeof(OSBUF_HOLD_Q))
+/* AGGR_RX_TIMEOUT value is important as a (too) small value can cause frames to be 
+ * delivered out of order and a (too) large value can cause undesirable latency in
+ * certain situations. */
+#define AGGR_RX_TIMEOUT     400  /* Timeout(in ms) for delivery of frames, if they are stuck */
+
+typedef enum {
+    ALL_SEQNO = 0,
+    CONTIGUOUS_SEQNO = 1,
+}DELIVERY_ORDER;
+
+typedef struct {
+    void        *osbuf;
+    A_BOOL      is_amsdu;
+    A_UINT16    seq_no;
+}OSBUF_HOLD_Q;
+
+
+#if 0
+typedef struct {
+    A_UINT16    seqno_st;
+    A_UINT16    seqno_end;
+}WINDOW_SNAPSHOT;
+#endif
+
+typedef struct {
+    A_BOOL              aggr;       /* is it ON or OFF */
+    A_BOOL              progress;   /* TRUE when frames have arrived after a timer start */
+    A_BOOL              timerMon;   /* TRUE if the timer started for the sake of this TID */
+    A_UINT16            win_sz;     /* negotiated window size */
+    A_UINT16            seq_next;   /* Next seq no, in current window */
+    A_UINT32            hold_q_sz;  /* Num of frames that can be held in hold q */
+    OSBUF_HOLD_Q        *hold_q;    /* Hold q for re-order */
+#if 0    
+    WINDOW_SNAPSHOT     old_win;    /* Sliding window snapshot - for timeout */
+#endif    
+    A_NETBUF_QUEUE_T    q;          /* q head for enqueuing frames for dispatch */
+    A_MUTEX_T           lock;
+}RXTID;
+
+typedef struct {
+    A_UINT32    num_into_aggr;      /* hitting at the input of this module */
+    A_UINT32    num_dups;           /* duplicate */
+    A_UINT32    num_oow;            /* out of window */
+    A_UINT32    num_mpdu;           /* single payload 802.3/802.11 frame */
+    A_UINT32    num_amsdu;          /* AMSDU */
+    A_UINT32    num_delivered;      /* frames delivered to IP stack */
+    A_UINT32    num_timeouts;       /* num of timeouts, during which frames delivered */
+    A_UINT32    num_hole;           /* frame not present, when window moved over */
+    A_UINT32    num_bar;            /* num of resets of seq_num, via BAR */
+}RXTID_STATS;
+
+typedef struct {
+    A_UINT8             aggr_sz;            /* config value of aggregation size */    
+    A_UINT8             timerScheduled;
+    A_TIMER             timer;              /* timer for returning held up pkts in re-order que */    
+    void                *dev;               /* dev handle */
+    RX_CALLBACK         rx_fn;              /* callback function to return frames; to upper layer */
+    RXTID               RxTid[NUM_OF_TIDS]; /* Per tid window */
+    ALLOC_NETBUFS       netbuf_allocator;   /* OS netbuf alloc fn */
+    A_NETBUF_QUEUE_T    freeQ;              /* pre-allocated buffers - for A_MSDU slicing */
+    RXTID_STATS         stat[NUM_OF_TIDS];  /* Tid based statistics */
+    PACKET_LOG          pkt_log;            /* Log info of the packets */
+}AGGR_INFO;
+
+#endif /* __AGGR_RX_INTERNAL_H__ */
diff --git a/drivers/net/ath6kl/reorder/rcv_aggr.c b/drivers/net/ath6kl/reorder/rcv_aggr.c
new file mode 100644
index 00000000000..092bb3007c5
--- /dev/null
+++ b/drivers/net/ath6kl/reorder/rcv_aggr.c
@@ -0,0 +1,666 @@
+/*
+ *
+ * Copyright (c) 2010 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ * 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+ *
+ */
+
+#ifdef  ATH_AR6K_11N_SUPPORT
+
+#include <a_config.h>
+#include <athdefs.h>
+#include <a_types.h>
+#include <a_osapi.h>
+#include <a_debug.h>
+#include "pkt_log.h"
+#include "aggr_recv_api.h"
+#include "aggr_rx_internal.h"
+#include "wmi.h"
+
+extern A_STATUS
+wmi_dot3_2_dix(void *osbuf);
+
+static void
+aggr_slice_amsdu(AGGR_INFO *p_aggr, RXTID *rxtid, void **osbuf);
+
+static void
+aggr_timeout(A_ATH_TIMER arg);
+
+static void
+aggr_deque_frms(AGGR_INFO *p_aggr, A_UINT8 tid, A_UINT16 seq_no, A_UINT8 order);
+
+static void
+aggr_dispatch_frames(AGGR_INFO *p_aggr, A_NETBUF_QUEUE_T *q);
+
+static void *
+aggr_get_osbuf(AGGR_INFO *p_aggr);
+
+void *
+aggr_init(ALLOC_NETBUFS netbuf_allocator)
+{
+    AGGR_INFO   *p_aggr = NULL;
+    RXTID *rxtid;
+    A_UINT8 i;
+    A_STATUS status = A_OK;
+
+    A_PRINTF("In aggr_init..\n");
+
+    do {
+        p_aggr = A_MALLOC(sizeof(AGGR_INFO));
+        if(!p_aggr) {
+            A_PRINTF("Failed to allocate memory for aggr_node\n");
+            status = A_ERROR;
+            break;
+        }
+
+        /* Init timer and data structures */
+        A_MEMZERO(p_aggr, sizeof(AGGR_INFO));
+        p_aggr->aggr_sz = AGGR_SZ_DEFAULT;
+        A_INIT_TIMER(&p_aggr->timer, aggr_timeout, p_aggr);
+        p_aggr->timerScheduled = FALSE;
+        A_NETBUF_QUEUE_INIT(&p_aggr->freeQ);
+
+        p_aggr->netbuf_allocator = netbuf_allocator;
+        p_aggr->netbuf_allocator(&p_aggr->freeQ, AGGR_NUM_OF_FREE_NETBUFS);
+
+        for(i = 0; i < NUM_OF_TIDS; i++) {
+            rxtid = AGGR_GET_RXTID(p_aggr, i);
+            rxtid->aggr = FALSE;
+            rxtid->progress = FALSE;
+            rxtid->timerMon = FALSE;
+            A_NETBUF_QUEUE_INIT(&rxtid->q);
+            A_MUTEX_INIT(&rxtid->lock);
+        }
+    }while(FALSE);
+
+    A_PRINTF("going out of aggr_init..status %s\n",
+                    (status == A_OK) ? "OK":"Error");
+
+    if(status != A_OK) {
+        /* Cleanup */
+        aggr_module_destroy(p_aggr);
+    }
+    return ((status == A_OK) ? p_aggr : NULL);
+}
+
+/* utility function to clear rx hold_q for a tid */
+static void
+aggr_delete_tid_state(AGGR_INFO *p_aggr, A_UINT8 tid)
+{
+    RXTID *rxtid;
+    RXTID_STATS *stats;
+
+    A_ASSERT(tid < NUM_OF_TIDS && p_aggr);
+
+    rxtid = AGGR_GET_RXTID(p_aggr, tid);
+    stats = AGGR_GET_RXTID_STATS(p_aggr, tid);
+
+    if(rxtid->aggr) {
+        aggr_deque_frms(p_aggr, tid, 0, ALL_SEQNO);
+    }
+
+    rxtid->aggr = FALSE;
+    rxtid->progress = FALSE;
+    rxtid->timerMon = FALSE;
+    rxtid->win_sz = 0;
+    rxtid->seq_next = 0;
+    rxtid->hold_q_sz = 0;
+
+    if(rxtid->hold_q) {
+        A_FREE(rxtid->hold_q);
+        rxtid->hold_q = NULL;
+    }
+
+    A_MEMZERO(stats, sizeof(RXTID_STATS));
+}
+
+void
+aggr_module_destroy(void *cntxt)
+{
+    AGGR_INFO *p_aggr = (AGGR_INFO *)cntxt;
+    RXTID *rxtid;
+    A_UINT8 i, k;
+    A_PRINTF("%s(): aggr = %p\n",_A_FUNCNAME_, p_aggr);
+    A_ASSERT(p_aggr);
+
+    if(p_aggr) {
+        if(p_aggr->timerScheduled) {
+            A_UNTIMEOUT(&p_aggr->timer);
+            p_aggr->timerScheduled = FALSE;
+        }
+
+        for(i = 0; i < NUM_OF_TIDS; i++) {
+            rxtid = AGGR_GET_RXTID(p_aggr, i);
+            /* Free the hold q contents and hold_q*/
+            if(rxtid->hold_q) {
+                for(k = 0; k< rxtid->hold_q_sz; k++) {
+                    if(rxtid->hold_q[k].osbuf) {
+                        A_NETBUF_FREE(rxtid->hold_q[k].osbuf);
+                    }
+                }
+                A_FREE(rxtid->hold_q);
+            }
+            /* Free the dispatch q contents*/
+            while(A_NETBUF_QUEUE_SIZE(&rxtid->q)) {
+                A_NETBUF_FREE(A_NETBUF_DEQUEUE(&rxtid->q));
+            }
+            if (A_IS_MUTEX_VALID(&rxtid->lock)) {
+                A_MUTEX_DELETE(&rxtid->lock);
+            }
+        }
+        /* free the freeQ and its contents*/
+        while(A_NETBUF_QUEUE_SIZE(&p_aggr->freeQ)) {
+            A_NETBUF_FREE(A_NETBUF_DEQUEUE(&p_aggr->freeQ));
+        }
+        A_FREE(p_aggr);
+    }
+    A_PRINTF("out aggr_module_destroy\n");
+}
+
+
+void
+aggr_register_rx_dispatcher(void *cntxt, void * dev, RX_CALLBACK fn)
+{
+    AGGR_INFO *p_aggr = (AGGR_INFO *)cntxt;
+
+    A_ASSERT(p_aggr && fn && dev);
+
+    p_aggr->rx_fn = fn;
+    p_aggr->dev = dev;
+}
+
+
+void
+aggr_process_bar(void *cntxt, A_UINT8 tid, A_UINT16 seq_no)
+{
+    AGGR_INFO *p_aggr = (AGGR_INFO *)cntxt;
+    RXTID_STATS *stats;
+
+    A_ASSERT(p_aggr);
+    stats = AGGR_GET_RXTID_STATS(p_aggr, tid);
+    stats->num_bar++;
+
+    aggr_deque_frms(p_aggr, tid, seq_no, ALL_SEQNO);
+}
+
+
+void
+aggr_recv_addba_req_evt(void *cntxt, A_UINT8 tid, A_UINT16 seq_no, A_UINT8 win_sz)
+{
+    AGGR_INFO *p_aggr = (AGGR_INFO *)cntxt;
+    RXTID *rxtid;
+    RXTID_STATS *stats;
+
+    A_ASSERT(p_aggr);
+    rxtid = AGGR_GET_RXTID(p_aggr, tid);
+    stats = AGGR_GET_RXTID_STATS(p_aggr, tid);
+
+    A_PRINTF("%s(): win_sz = %d aggr %d\n", _A_FUNCNAME_, win_sz, rxtid->aggr);
+    if(win_sz < AGGR_WIN_SZ_MIN || win_sz > AGGR_WIN_SZ_MAX) {
+        A_PRINTF("win_sz %d, tid %d\n", win_sz, tid);
+    }
+
+    if(rxtid->aggr) {
+        /* Just go and  deliver all the frames up from this
+         * queue, as if we got DELBA and re-initialize the queue
+         */
+        aggr_delete_tid_state(p_aggr, tid);
+    }
+
+    rxtid->seq_next = seq_no;
+    /* create these queues, only upon receiving of ADDBA for a
+     * tid, reducing memory requirement
+     */
+    rxtid->hold_q = A_MALLOC(HOLD_Q_SZ(win_sz));
+    if((rxtid->hold_q == NULL)) {
+        A_PRINTF("Failed to allocate memory, tid = %d\n", tid);
+        A_ASSERT(0);
+    }
+    A_MEMZERO(rxtid->hold_q, HOLD_Q_SZ(win_sz));
+
+    /* Update rxtid for the window sz */
+    rxtid->win_sz = win_sz;
+    /* hold_q_sz inicates the depth of holding q - which  is
+     * a factor of win_sz. Compute once, as it will be used often
+     */
+    rxtid->hold_q_sz = TID_WINDOW_SZ(win_sz);
+    /* There should be no frames on q - even when second ADDBA comes in.
+     * If aggr was previously ON on this tid, we would have cleaned up
+     * the q
+     */
+    if(A_NETBUF_QUEUE_SIZE(&rxtid->q) != 0) {
+        A_PRINTF("ERROR: Frames still on queue ?\n");
+        A_ASSERT(0);
+    }
+
+    rxtid->aggr = TRUE;
+}
+
+void
+aggr_recv_delba_req_evt(void *cntxt, A_UINT8 tid)
+{
+    AGGR_INFO *p_aggr = (AGGR_INFO *)cntxt;
+    RXTID *rxtid;
+
+    A_ASSERT(p_aggr);
+    A_PRINTF("%s(): tid %d\n", _A_FUNCNAME_, tid);
+
+    rxtid = AGGR_GET_RXTID(p_aggr, tid);
+
+    if(rxtid->aggr) {
+        aggr_delete_tid_state(p_aggr, tid);
+    }
+}
+
+static void
+aggr_deque_frms(AGGR_INFO *p_aggr, A_UINT8 tid, A_UINT16 seq_no, A_UINT8 order)
+{
+    RXTID *rxtid;
+    OSBUF_HOLD_Q *node;
+    A_UINT16 idx, idx_end, seq_end;
+    RXTID_STATS *stats;
+
+    A_ASSERT(p_aggr);
+    rxtid = AGGR_GET_RXTID(p_aggr, tid);
+    stats = AGGR_GET_RXTID_STATS(p_aggr, tid);
+
+    /* idx is absolute location for first frame */
+    idx = AGGR_WIN_IDX(rxtid->seq_next, rxtid->hold_q_sz);
+
+    /* idx_end is typically the last possible frame in the window,
+     * but changes to 'the' seq_no, when BAR comes. If seq_no
+     * is non-zero, we will go up to that and stop.
+     * Note: last seq no in current window will occupy the same
+     * index position as index that is just previous to start.
+     * An imp point : if win_sz is 7, for seq_no space of 4095,
+     * then, there would be holes when sequence wrap around occurs.
+     * Target should judiciously choose the win_sz, based on
+     * this condition. For 4095, (TID_WINDOW_SZ = 2 x win_sz
+     * 2, 4, 8, 16 win_sz works fine).
+     * We must deque from "idx" to "idx_end", including both.
+     */
+    seq_end = (seq_no) ? seq_no : rxtid->seq_next;
+    idx_end = AGGR_WIN_IDX(seq_end, rxtid->hold_q_sz);
+
+    /* Critical section begins */
+    A_MUTEX_LOCK(&rxtid->lock);
+    do {
+
+        node = &rxtid->hold_q[idx];
+
+        if((order == CONTIGUOUS_SEQNO) && (!node->osbuf))
+            break;
+
+        /* chain frames and deliver frames bcos:
+         *  1. either the frames are in order and window is contiguous, OR
+         *  2. we need to deque frames, irrespective of holes
+         */
+        if(node->osbuf) {
+            if(node->is_amsdu) {
+                aggr_slice_amsdu(p_aggr, rxtid, &node->osbuf);
+            } else {
+                A_NETBUF_ENQUEUE(&rxtid->q, node->osbuf);
+            }
+            node->osbuf = NULL;
+        } else {
+            stats->num_hole++;
+        }
+
+        /* window is moving */
+        rxtid->seq_next = IEEE80211_NEXT_SEQ_NO(rxtid->seq_next);
+        idx = AGGR_WIN_IDX(rxtid->seq_next, rxtid->hold_q_sz);
+    } while(idx != idx_end);
+    /* Critical section ends */
+    A_MUTEX_UNLOCK(&rxtid->lock);
+
+    stats->num_delivered += A_NETBUF_QUEUE_SIZE(&rxtid->q);
+    aggr_dispatch_frames(p_aggr, &rxtid->q);
+}
+
+static void *
+aggr_get_osbuf(AGGR_INFO *p_aggr)
+{
+    void *buf = NULL;
+
+    /* Starving for buffers?  get more from OS
+     *  check for low netbuffers( < 1/4 AGGR_NUM_OF_FREE_NETBUFS) :
+     *      re-allocate bufs if so
+     * allocate a free buf from freeQ
+     */
+    if (A_NETBUF_QUEUE_SIZE(&p_aggr->freeQ) < (AGGR_NUM_OF_FREE_NETBUFS >> 2)) {
+        p_aggr->netbuf_allocator(&p_aggr->freeQ, AGGR_NUM_OF_FREE_NETBUFS);
+    }
+
+    if (A_NETBUF_QUEUE_SIZE(&p_aggr->freeQ)) {
+        buf = A_NETBUF_DEQUEUE(&p_aggr->freeQ);
+    }
+
+    return buf;
+}
+
+
+static void
+aggr_slice_amsdu(AGGR_INFO *p_aggr, RXTID *rxtid, void **osbuf)
+{
+    void *new_buf;
+    A_UINT16 frame_8023_len, payload_8023_len, mac_hdr_len, amsdu_len;
+    A_UINT8 *framep;
+
+    /* Frame format at this point:
+     *  [DIX hdr | 802.3 | 802.3 | ... | 802.3]
+     *
+     * Strip the DIX header.
+     * Iterate through the osbuf and do:
+     *  grab a free netbuf from freeQ
+     *  find the start and end of a frame
+     *  copy it to netbuf(Vista can do better here)
+     *  convert all msdu's(802.3) frames to upper layer format - os routine
+     *      -for now lets convert from 802.3 to dix
+     *  enque this to dispatch q of tid
+     * repeat
+     * free the osbuf - to OS. It's been sliced.
+     */
+
+    mac_hdr_len = sizeof(ATH_MAC_HDR);
+    framep = A_NETBUF_DATA(*osbuf) + mac_hdr_len;
+    amsdu_len = A_NETBUF_LEN(*osbuf) - mac_hdr_len;
+
+    while(amsdu_len > mac_hdr_len) {
+        /* Begin of a 802.3 frame */
+        payload_8023_len = A_BE2CPU16(((ATH_MAC_HDR *)framep)->typeOrLen);
+#define MAX_MSDU_SUBFRAME_PAYLOAD_LEN 1508
+#define MIN_MSDU_SUBFRAME_PAYLOAD_LEN 46
+        if(payload_8023_len < MIN_MSDU_SUBFRAME_PAYLOAD_LEN || payload_8023_len > MAX_MSDU_SUBFRAME_PAYLOAD_LEN) {
+            A_PRINTF("802.3 AMSDU frame bound check failed. len %d\n", payload_8023_len);
+            break;
+        }
+        frame_8023_len = payload_8023_len + mac_hdr_len;
+        new_buf = aggr_get_osbuf(p_aggr);
+        if(new_buf == NULL) {
+            A_PRINTF("No buffer available \n");
+            break;
+        }
+
+        A_MEMCPY(A_NETBUF_DATA(new_buf), framep, frame_8023_len);
+        A_NETBUF_PUT(new_buf, frame_8023_len);
+        if (wmi_dot3_2_dix(new_buf) != A_OK) {
+            A_PRINTF("dot3_2_dix err..\n");
+            A_NETBUF_FREE(new_buf);
+            break;
+        }
+
+        A_NETBUF_ENQUEUE(&rxtid->q, new_buf);
+
+        /* Is this the last subframe within this aggregate ? */
+        if ((amsdu_len - frame_8023_len) == 0) {
+            break;
+        }
+
+        /* Add the length of A-MSDU subframe padding bytes -
+         * Round to nearest word.
+         */
+        frame_8023_len = ((frame_8023_len + 3) & ~3);
+
+        framep += frame_8023_len;
+        amsdu_len -= frame_8023_len;
+    }
+
+    A_NETBUF_FREE(*osbuf);
+    *osbuf = NULL;
+}
+
+void
+aggr_process_recv_frm(void *cntxt, A_UINT8 tid, A_UINT16 seq_no, A_BOOL is_amsdu, void **osbuf)
+{
+    AGGR_INFO *p_aggr = (AGGR_INFO *)cntxt;
+    RXTID *rxtid;
+    RXTID_STATS *stats;
+    A_UINT16 idx, st, cur, end;
+    A_UINT16 *log_idx;
+    OSBUF_HOLD_Q *node;
+    PACKET_LOG *log;
+
+    A_ASSERT(p_aggr);
+    A_ASSERT(tid < NUM_OF_TIDS);
+
+    rxtid = AGGR_GET_RXTID(p_aggr, tid);
+    stats = AGGR_GET_RXTID_STATS(p_aggr, tid);
+
+    stats->num_into_aggr++;
+
+    if(!rxtid->aggr) {
+        if(is_amsdu) {
+            aggr_slice_amsdu(p_aggr, rxtid, osbuf);
+            stats->num_amsdu++;
+            aggr_dispatch_frames(p_aggr, &rxtid->q);
+        }
+        return;
+    }
+
+    /* Check the incoming sequence no, if it's in the window */
+    st = rxtid->seq_next;
+    cur = seq_no;
+    end = (st + rxtid->hold_q_sz-1) & IEEE80211_MAX_SEQ_NO;
+    /* Log the pkt info for future analysis */
+    log = &p_aggr->pkt_log;
+    log_idx = &log->last_idx;
+    log->info[*log_idx].cur = cur;
+    log->info[*log_idx].st = st;
+    log->info[*log_idx].end = end;
+    *log_idx = IEEE80211_NEXT_SEQ_NO(*log_idx);
+
+    if(((st < end) && (cur < st || cur > end)) ||
+      ((st > end) && (cur > end) && (cur < st))) {
+        /* the cur frame is outside the window. Since we know
+         * our target would not do this without reason it must
+         * be assumed that the window has moved for some valid reason.
+         * Therefore, we dequeue all frames and start fresh.
+         */
+        A_UINT16 extended_end;
+
+        extended_end = (end + rxtid->hold_q_sz-1) & IEEE80211_MAX_SEQ_NO;
+
+        if(((end < extended_end) && (cur < end || cur > extended_end)) ||
+           ((end > extended_end) && (cur > extended_end) && (cur < end))) {
+            // dequeue all frames in queue and shift window to new frame
+            aggr_deque_frms(p_aggr, tid, 0, ALL_SEQNO);
+            //set window start so that new frame is last frame in window
+            if(cur >= rxtid->hold_q_sz-1) {
+                rxtid->seq_next = cur - (rxtid->hold_q_sz-1);
+            }else{
+                rxtid->seq_next = IEEE80211_MAX_SEQ_NO - (rxtid->hold_q_sz-2 - cur);
+            }
+        } else {
+            // dequeue only those frames that are outside the new shifted window
+            if(cur >= rxtid->hold_q_sz-1) {
+                st = cur - (rxtid->hold_q_sz-1);
+            }else{
+                st = IEEE80211_MAX_SEQ_NO - (rxtid->hold_q_sz-2 - cur);
+            }
+
+            aggr_deque_frms(p_aggr, tid, st, ALL_SEQNO);
+        }
+
+        stats->num_oow++;
+    }
+
+    idx = AGGR_WIN_IDX(seq_no, rxtid->hold_q_sz);
+
+    /*enque the frame, in hold_q */
+    node = &rxtid->hold_q[idx];
+
+    A_MUTEX_LOCK(&rxtid->lock);
+    if(node->osbuf) {
+        /* Is the cur frame duplicate or something beyond our
+         * window(hold_q -> which is 2x, already)?
+         * 1. Duplicate is easy - drop incoming frame.
+         * 2. Not falling in current sliding window.
+         *  2a. is the frame_seq_no preceding current tid_seq_no?
+         *      -> drop the frame. perhaps sender did not get our ACK.
+         *         this is taken care of above.
+         *  2b. is the frame_seq_no beyond window(st, TID_WINDOW_SZ);
+         *      -> Taken care of it above, by moving window forward.
+         *
+         */
+        A_NETBUF_FREE(node->osbuf);
+        stats->num_dups++;
+    }
+
+    node->osbuf = *osbuf;
+    node->is_amsdu = is_amsdu;
+    node->seq_no = seq_no;
+    if(node->is_amsdu) {
+        stats->num_amsdu++;
+    } else {
+        stats->num_mpdu++;
+    }
+    A_MUTEX_UNLOCK(&rxtid->lock);
+
+    *osbuf = NULL;
+    aggr_deque_frms(p_aggr, tid, 0, CONTIGUOUS_SEQNO);
+
+    if(p_aggr->timerScheduled) {
+        rxtid->progress = TRUE;
+    }else{
+        for(idx=0 ; idx<rxtid->hold_q_sz ; idx++) {
+            if(rxtid->hold_q[idx].osbuf) {
+                /* there is a frame in the queue and no timer so
+                 * start a timer to ensure that the frame doesn't remain
+                 * stuck forever. */
+                p_aggr->timerScheduled = TRUE;
+                A_TIMEOUT_MS(&p_aggr->timer, AGGR_RX_TIMEOUT, 0);
+                rxtid->progress = FALSE;
+                rxtid->timerMon = TRUE;
+                break;
+            }
+        }
+    }
+}
+
+/*
+ * aggr_reset_state -- Called when it is deemed necessary to clear the aggregate
+ *  hold Q state.  Examples include when a Connect event or disconnect event is
+ *  received.
+ */
+void
+aggr_reset_state(void *cntxt)
+{
+    A_UINT8 tid;
+    AGGR_INFO *p_aggr = (AGGR_INFO *)cntxt;
+
+    A_ASSERT(p_aggr);
+
+    for(tid=0 ; tid<NUM_OF_TIDS ; tid++) {
+        aggr_delete_tid_state(p_aggr, tid);
+    }
+}
+
+
+static void
+aggr_timeout(A_ATH_TIMER arg)
+{
+    A_UINT8 i,j;
+    AGGR_INFO *p_aggr = (AGGR_INFO *)arg;
+    RXTID   *rxtid;
+    RXTID_STATS *stats;
+    /*
+     * If the q for which the timer was originally started has
+     * not progressed then it is necessary to dequeue all the
+     * contained frames so that they are not held forever.
+     */
+    for(i = 0; i < NUM_OF_TIDS; i++) {
+        rxtid = AGGR_GET_RXTID(p_aggr, i);
+        stats = AGGR_GET_RXTID_STATS(p_aggr, i);
+
+        if(rxtid->aggr == FALSE ||
+           rxtid->timerMon == FALSE ||
+           rxtid->progress == TRUE) {
+            continue;
+        }
+        // dequeue all frames in for this tid
+        stats->num_timeouts++;
+        A_PRINTF("TO: st %d end %d\n", rxtid->seq_next, ((rxtid->seq_next + rxtid->hold_q_sz-1) & IEEE80211_MAX_SEQ_NO));
+        aggr_deque_frms(p_aggr, i, 0, ALL_SEQNO);
+    }
+
+    p_aggr->timerScheduled = FALSE;
+    // determine whether a new timer should be started.
+    for(i = 0; i < NUM_OF_TIDS; i++) {
+        rxtid = AGGR_GET_RXTID(p_aggr, i);
+
+        if(rxtid->aggr == TRUE && rxtid->hold_q) {
+            for(j = 0 ; j < rxtid->hold_q_sz ; j++)
+            {
+                if(rxtid->hold_q[j].osbuf)
+                {
+                    p_aggr->timerScheduled = TRUE;
+                    rxtid->timerMon = TRUE;
+                    rxtid->progress = FALSE;
+                    break;
+                }
+            }
+
+            if(j >= rxtid->hold_q_sz) {
+                rxtid->timerMon = FALSE;
+            }
+        }
+    }
+
+    if(p_aggr->timerScheduled) {
+        /* Rearm the timer*/
+        A_TIMEOUT_MS(&p_aggr->timer, AGGR_RX_TIMEOUT, 0);
+    }
+
+}
+
+static void
+aggr_dispatch_frames(AGGR_INFO *p_aggr, A_NETBUF_QUEUE_T *q)
+{
+    void *osbuf;
+
+    while((osbuf = A_NETBUF_DEQUEUE(q))) {
+        p_aggr->rx_fn(p_aggr->dev, osbuf);
+    }
+}
+
+void
+aggr_dump_stats(void *cntxt, PACKET_LOG **log_buf)
+{
+    AGGR_INFO *p_aggr = (AGGR_INFO *)cntxt;
+    RXTID   *rxtid;
+    RXTID_STATS *stats;
+    A_UINT8 i;
+
+    *log_buf = &p_aggr->pkt_log;
+    A_PRINTF("\n\n================================================\n");
+    A_PRINTF("tid: num_into_aggr, dups, oow, mpdu, amsdu, delivered, timeouts, holes, bar, seq_next\n");
+    for(i = 0; i < NUM_OF_TIDS; i++) {
+        stats = AGGR_GET_RXTID_STATS(p_aggr, i);
+        rxtid = AGGR_GET_RXTID(p_aggr, i);
+        A_PRINTF("%d: %d %d %d %d %d %d %d %d %d : %d\n", i, stats->num_into_aggr, stats->num_dups,
+                    stats->num_oow, stats->num_mpdu,
+                    stats->num_amsdu, stats->num_delivered, stats->num_timeouts,
+                    stats->num_hole, stats->num_bar,
+                    rxtid->seq_next);
+    }
+    A_PRINTF("================================================\n\n");
+
+}
+
+#endif  /* ATH_AR6K_11N_SUPPORT */
diff --git a/drivers/net/ath6kl/wlan/include/ieee80211.h b/drivers/net/ath6kl/wlan/include/ieee80211.h
new file mode 100644
index 00000000000..c4fd13fe0a9
--- /dev/null
+++ b/drivers/net/ath6kl/wlan/include/ieee80211.h
@@ -0,0 +1,401 @@
+//------------------------------------------------------------------------------
+// <copyright file="ieee80211.h" company="Atheros">
+//    Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _NET80211_IEEE80211_H_
+#define _NET80211_IEEE80211_H_
+
+#include "athstartpack.h"
+
+/*
+ * 802.11 protocol definitions.
+ */
+#define IEEE80211_WEP_KEYLEN        5   /* 40bit */
+#define IEEE80211_WEP_IVLEN         3   /* 24bit */
+#define IEEE80211_WEP_KIDLEN        1   /* 1 octet */
+#define IEEE80211_WEP_CRCLEN        4   /* CRC-32 */
+#define IEEE80211_WEP_NKID          4   /* number of key ids */
+
+/*
+ * 802.11i defines an extended IV for use with non-WEP ciphers.
+ * When the EXTIV bit is set in the key id byte an additional
+ * 4 bytes immediately follow the IV for TKIP.  For CCMP the
+ * EXTIV bit is likewise set but the 8 bytes represent the
+ * CCMP header rather than IV+extended-IV.
+ */
+#define IEEE80211_WEP_EXTIV         0x20
+#define IEEE80211_WEP_EXTIVLEN      4   /* extended IV length */
+#define IEEE80211_WEP_MICLEN        8   /* trailing MIC */
+
+#define IEEE80211_CRC_LEN           4
+
+#ifdef WAPI_ENABLE
+#define IEEE80211_WAPI_EXTIVLEN      10   /* extended IV length */
+#endif /* WAPI ENABLE */
+
+
+#define IEEE80211_ADDR_LEN  6       /* size of 802.11 address */
+/* is 802.11 address multicast/broadcast? */
+#define IEEE80211_IS_MULTICAST(_a)  (*(_a) & 0x01)
+#define IEEE80211_IS_BROADCAST(_a)  (*(_a) == 0xFF)
+#define WEP_HEADER (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN)
+#define WEP_TRAILER IEEE80211_WEP_CRCLEN
+#define CCMP_HEADER (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + \
+                    IEEE80211_WEP_EXTIVLEN)
+#define CCMP_TRAILER IEEE80211_WEP_MICLEN
+#define TKIP_HEADER (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + \
+                    IEEE80211_WEP_EXTIVLEN)
+#define TKIP_TRAILER IEEE80211_WEP_CRCLEN
+#define TKIP_MICLEN  IEEE80211_WEP_MICLEN
+
+
+#define IEEE80211_ADDR_EQ(addr1, addr2)     \
+    (A_MEMCMP(addr1, addr2, IEEE80211_ADDR_LEN) == 0)
+
+#define IEEE80211_ADDR_COPY(dst,src)    A_MEMCPY(dst,src,IEEE80211_ADDR_LEN)
+
+#define IEEE80211_KEYBUF_SIZE 16
+#define IEEE80211_MICBUF_SIZE (8+8)  /* space for both tx and rx */
+
+/*
+ * NB: these values are ordered carefully; there are lots of
+ * of implications in any reordering.  In particular beware
+ * that 4 is not used to avoid conflicting with IEEE80211_F_PRIVACY.
+ */
+#define IEEE80211_CIPHER_WEP            0
+#define IEEE80211_CIPHER_TKIP           1
+#define IEEE80211_CIPHER_AES_OCB        2
+#define IEEE80211_CIPHER_AES_CCM        3
+#define IEEE80211_CIPHER_CKIP           5
+#define IEEE80211_CIPHER_CCKM_KRK       6
+#define IEEE80211_CIPHER_NONE           7       /* pseudo value */
+
+#define IEEE80211_CIPHER_MAX            (IEEE80211_CIPHER_NONE+1)
+
+#define IEEE80211_IS_VALID_WEP_CIPHER_LEN(len) \
+        (((len) == 5) || ((len) == 13) || ((len) == 16))
+
+
+
+/*
+ * generic definitions for IEEE 802.11 frames
+ */
+PREPACK struct ieee80211_frame {
+    A_UINT8    i_fc[2];
+    A_UINT8    i_dur[2];
+    A_UINT8    i_addr1[IEEE80211_ADDR_LEN];
+    A_UINT8    i_addr2[IEEE80211_ADDR_LEN];
+    A_UINT8    i_addr3[IEEE80211_ADDR_LEN];
+    A_UINT8    i_seq[2];
+    /* possibly followed by addr4[IEEE80211_ADDR_LEN]; */
+    /* see below */
+} POSTPACK;
+
+PREPACK struct ieee80211_qosframe {
+    A_UINT8 i_fc[2];
+    A_UINT8 i_dur[2];
+    A_UINT8 i_addr1[IEEE80211_ADDR_LEN];
+    A_UINT8 i_addr2[IEEE80211_ADDR_LEN];
+    A_UINT8 i_addr3[IEEE80211_ADDR_LEN];
+    A_UINT8 i_seq[2];
+    A_UINT8 i_qos[2];
+} POSTPACK;
+
+#define IEEE80211_FC0_VERSION_MASK          0x03
+#define IEEE80211_FC0_VERSION_SHIFT         0
+#define IEEE80211_FC0_VERSION_0             0x00
+#define IEEE80211_FC0_TYPE_MASK             0x0c
+#define IEEE80211_FC0_TYPE_SHIFT            2
+#define IEEE80211_FC0_TYPE_MGT              0x00
+#define IEEE80211_FC0_TYPE_CTL              0x04
+#define IEEE80211_FC0_TYPE_DATA             0x08
+
+#define IEEE80211_FC0_SUBTYPE_MASK          0xf0
+#define IEEE80211_FC0_SUBTYPE_SHIFT         4
+/* for TYPE_MGT */
+#define IEEE80211_FC0_SUBTYPE_ASSOC_REQ     0x00
+#define IEEE80211_FC0_SUBTYPE_ASSOC_RESP    0x10
+#define IEEE80211_FC0_SUBTYPE_REASSOC_REQ   0x20
+#define IEEE80211_FC0_SUBTYPE_REASSOC_RESP  0x30
+#define IEEE80211_FC0_SUBTYPE_PROBE_REQ     0x40
+#define IEEE80211_FC0_SUBTYPE_PROBE_RESP    0x50
+#define IEEE80211_FC0_SUBTYPE_BEACON        0x80
+#define IEEE80211_FC0_SUBTYPE_ATIM          0x90
+#define IEEE80211_FC0_SUBTYPE_DISASSOC      0xa0
+#define IEEE80211_FC0_SUBTYPE_AUTH          0xb0
+#define IEEE80211_FC0_SUBTYPE_DEAUTH        0xc0
+/* for TYPE_CTL */
+#define IEEE80211_FC0_SUBTYPE_PS_POLL       0xa0
+#define IEEE80211_FC0_SUBTYPE_RTS           0xb0
+#define IEEE80211_FC0_SUBTYPE_CTS           0xc0
+#define IEEE80211_FC0_SUBTYPE_ACK           0xd0
+#define IEEE80211_FC0_SUBTYPE_CF_END        0xe0
+#define IEEE80211_FC0_SUBTYPE_CF_END_ACK    0xf0
+/* for TYPE_DATA (bit combination) */
+#define IEEE80211_FC0_SUBTYPE_DATA          0x00
+#define IEEE80211_FC0_SUBTYPE_CF_ACK        0x10
+#define IEEE80211_FC0_SUBTYPE_CF_POLL       0x20
+#define IEEE80211_FC0_SUBTYPE_CF_ACPL       0x30
+#define IEEE80211_FC0_SUBTYPE_NODATA        0x40
+#define IEEE80211_FC0_SUBTYPE_CFACK         0x50
+#define IEEE80211_FC0_SUBTYPE_CFPOLL        0x60
+#define IEEE80211_FC0_SUBTYPE_CF_ACK_CF_ACK 0x70
+#define IEEE80211_FC0_SUBTYPE_QOS           0x80
+#define IEEE80211_FC0_SUBTYPE_QOS_NULL      0xc0
+
+#define IEEE80211_FC1_DIR_MASK              0x03
+#define IEEE80211_FC1_DIR_NODS              0x00    /* STA->STA */
+#define IEEE80211_FC1_DIR_TODS              0x01    /* STA->AP  */
+#define IEEE80211_FC1_DIR_FROMDS            0x02    /* AP ->STA */
+#define IEEE80211_FC1_DIR_DSTODS            0x03    /* AP ->AP  */
+
+#define IEEE80211_FC1_MORE_FRAG             0x04
+#define IEEE80211_FC1_RETRY                 0x08
+#define IEEE80211_FC1_PWR_MGT               0x10
+#define IEEE80211_FC1_MORE_DATA             0x20
+#define IEEE80211_FC1_WEP                   0x40
+#define IEEE80211_FC1_ORDER                 0x80
+
+#define IEEE80211_SEQ_FRAG_MASK             0x000f
+#define IEEE80211_SEQ_FRAG_SHIFT            0
+#define IEEE80211_SEQ_SEQ_MASK              0xfff0
+#define IEEE80211_SEQ_SEQ_SHIFT             4
+
+#define IEEE80211_NWID_LEN                  32
+
+/*
+ * 802.11 rate set.
+ */
+#define IEEE80211_RATE_SIZE     8       /* 802.11 standard */
+#define IEEE80211_RATE_MAXSIZE  15      /* max rates we'll handle */
+
+#define WMM_NUM_AC                  4   /* 4 AC categories */
+
+#define WMM_PARAM_ACI_M         0x60    /* Mask for ACI field */
+#define WMM_PARAM_ACI_S         5   /* Shift for ACI field */
+#define WMM_PARAM_ACM_M         0x10    /* Mask for ACM bit */
+#define WMM_PARAM_ACM_S         4       /* Shift for ACM bit */
+#define WMM_PARAM_AIFSN_M       0x0f    /* Mask for aifsn field */
+#define WMM_PARAM_LOGCWMIN_M    0x0f    /* Mask for CwMin field (in log) */
+#define WMM_PARAM_LOGCWMAX_M    0xf0    /* Mask for CwMax field (in log) */
+#define WMM_PARAM_LOGCWMAX_S    4   /* Shift for CwMax field */
+
+#define WMM_AC_TO_TID(_ac) (       \
+    ((_ac) == WMM_AC_VO) ? 6 : \
+    ((_ac) == WMM_AC_VI) ? 5 : \
+    ((_ac) == WMM_AC_BK) ? 1 : \
+    0)
+
+#define TID_TO_WMM_AC(_tid) (      \
+    ((_tid) < 1) ? WMM_AC_BE : \
+    ((_tid) < 3) ? WMM_AC_BK : \
+    ((_tid) < 6) ? WMM_AC_VI : \
+    WMM_AC_VO)
+/*
+ * Management information element payloads.
+ */
+
+enum {
+    IEEE80211_ELEMID_SSID       = 0,
+    IEEE80211_ELEMID_RATES      = 1,
+    IEEE80211_ELEMID_FHPARMS    = 2,
+    IEEE80211_ELEMID_DSPARMS    = 3,
+    IEEE80211_ELEMID_CFPARMS    = 4,
+    IEEE80211_ELEMID_TIM        = 5,
+    IEEE80211_ELEMID_IBSSPARMS  = 6,
+    IEEE80211_ELEMID_COUNTRY    = 7,
+    IEEE80211_ELEMID_CHALLENGE  = 16,
+    /* 17-31 reserved for challenge text extension */
+    IEEE80211_ELEMID_PWRCNSTR   = 32,
+    IEEE80211_ELEMID_PWRCAP     = 33,
+    IEEE80211_ELEMID_TPCREQ     = 34,
+    IEEE80211_ELEMID_TPCREP     = 35,
+    IEEE80211_ELEMID_SUPPCHAN   = 36,
+    IEEE80211_ELEMID_CHANSWITCH = 37,
+    IEEE80211_ELEMID_MEASREQ    = 38,
+    IEEE80211_ELEMID_MEASREP    = 39,
+    IEEE80211_ELEMID_QUIET      = 40,
+    IEEE80211_ELEMID_IBSSDFS    = 41,
+    IEEE80211_ELEMID_ERP        = 42,
+    IEEE80211_ELEMID_HTCAP_ANA  = 45,   /* Address ANA, and non-ANA story, for interop. CL#171733 */
+    IEEE80211_ELEMID_RSN        = 48,
+    IEEE80211_ELEMID_XRATES     = 50,
+    IEEE80211_ELEMID_HTINFO_ANA = 61,
+#ifdef WAPI_ENABLE
+    IEEE80211_ELEMID_WAPI       = 68,
+#endif
+    IEEE80211_ELEMID_TPC        = 150,
+    IEEE80211_ELEMID_CCKM       = 156,
+    IEEE80211_ELEMID_VENDOR     = 221,  /* vendor private */
+};
+
+#define ATH_OUI             0x7f0300        /* Atheros OUI */
+#define ATH_OUI_TYPE        0x01
+#define ATH_OUI_SUBTYPE     0x01
+#define ATH_OUI_VERSION     0x00
+
+#define WPA_OUI             0xf25000
+#define WPA_OUI_TYPE        0x01
+#define WPA_VERSION         1          /* current supported version */
+
+#define WPA_CSE_NULL        0x00
+#define WPA_CSE_WEP40       0x01
+#define WPA_CSE_TKIP        0x02
+#define WPA_CSE_CCMP        0x04
+#define WPA_CSE_WEP104      0x05
+
+#define WPA_ASE_NONE        0x00
+#define WPA_ASE_8021X_UNSPEC    0x01
+#define WPA_ASE_8021X_PSK   0x02
+
+#define RSN_OUI         0xac0f00
+#define RSN_VERSION     1       /* current supported version */
+
+#define RSN_CSE_NULL        0x00
+#define RSN_CSE_WEP40       0x01
+#define RSN_CSE_TKIP        0x02
+#define RSN_CSE_WRAP        0x03
+#define RSN_CSE_CCMP        0x04
+#define RSN_CSE_WEP104      0x05
+
+#define RSN_ASE_NONE            0x00
+#define RSN_ASE_8021X_UNSPEC    0x01
+#define RSN_ASE_8021X_PSK       0x02
+
+#define RSN_CAP_PREAUTH         0x01
+
+#define WMM_OUI                 0xf25000
+#define WMM_OUI_TYPE            0x02
+#define WMM_INFO_OUI_SUBTYPE    0x00
+#define WMM_PARAM_OUI_SUBTYPE   0x01
+#define WMM_VERSION             1
+
+/* WMM stream classes */
+#define WMM_NUM_AC  4
+#define WMM_AC_BE   0       /* best effort */
+#define WMM_AC_BK   1       /* background */
+#define WMM_AC_VI   2       /* video */
+#define WMM_AC_VO   3       /* voice */
+
+/* TSPEC related */
+#define ACTION_CATEGORY_CODE_TSPEC                 17
+#define ACTION_CODE_TSPEC_ADDTS                    0
+#define ACTION_CODE_TSPEC_ADDTS_RESP               1
+#define ACTION_CODE_TSPEC_DELTS                    2
+
+typedef enum {
+    TSPEC_STATUS_CODE_ADMISSION_ACCEPTED = 0,
+    TSPEC_STATUS_CODE_ADDTS_INVALID_PARAMS = 0x1,
+    TSPEC_STATUS_CODE_ADDTS_REQUEST_REFUSED = 0x3,
+    TSPEC_STATUS_CODE_UNSPECIFIED_QOS_RELATED_FAILURE = 0xC8,
+    TSPEC_STATUS_CODE_REQUESTED_REFUSED_POLICY_CONFIGURATION = 0xC9,
+    TSPEC_STATUS_CODE_INSUFFCIENT_BANDWIDTH = 0xCA,
+    TSPEC_STATUS_CODE_INVALID_PARAMS = 0xCB,
+    TSPEC_STATUS_CODE_DELTS_SENT    = 0x30,
+    TSPEC_STATUS_CODE_DELTS_RECV    = 0x31,
+} TSPEC_STATUS_CODE;
+
+#define TSPEC_TSID_MASK             0xF
+#define TSPEC_TSID_S                1
+
+/*
+ * WMM/802.11e Tspec Element
+ */
+typedef PREPACK struct wmm_tspec_ie_t {
+    A_UINT8     elementId;
+    A_UINT8     len;
+    A_UINT8     oui[3];
+    A_UINT8     ouiType;
+    A_UINT8     ouiSubType;
+    A_UINT8     version;
+    A_UINT16    tsInfo_info;
+    A_UINT8     tsInfo_reserved;
+    A_UINT16    nominalMSDU;
+    A_UINT16    maxMSDU;
+    A_UINT32    minServiceInt;
+    A_UINT32    maxServiceInt;
+    A_UINT32    inactivityInt;
+    A_UINT32    suspensionInt;
+    A_UINT32    serviceStartTime;
+    A_UINT32    minDataRate;
+    A_UINT32    meanDataRate;
+    A_UINT32    peakDataRate;
+    A_UINT32    maxBurstSize;
+    A_UINT32    delayBound;
+    A_UINT32    minPhyRate;
+    A_UINT16    sba;
+    A_UINT16    mediumTime;
+} POSTPACK WMM_TSPEC_IE;
+
+
+/*
+ * BEACON management packets
+ *
+ *  octet timestamp[8]
+ *  octet beacon interval[2]
+ *  octet capability information[2]
+ *  information element
+ *      octet elemid
+ *      octet length
+ *      octet information[length]
+ */
+
+#define IEEE80211_BEACON_INTERVAL(beacon) \
+    ((beacon)[8] | ((beacon)[9] << 8))
+#define IEEE80211_BEACON_CAPABILITY(beacon) \
+    ((beacon)[10] | ((beacon)[11] << 8))
+
+#define IEEE80211_CAPINFO_ESS               0x0001
+#define IEEE80211_CAPINFO_IBSS              0x0002
+#define IEEE80211_CAPINFO_CF_POLLABLE       0x0004
+#define IEEE80211_CAPINFO_CF_POLLREQ        0x0008
+#define IEEE80211_CAPINFO_PRIVACY           0x0010
+#define IEEE80211_CAPINFO_SHORT_PREAMBLE    0x0020
+#define IEEE80211_CAPINFO_PBCC              0x0040
+#define IEEE80211_CAPINFO_CHNL_AGILITY      0x0080
+/* bits 8-9 are reserved */
+#define IEEE80211_CAPINFO_SHORT_SLOTTIME    0x0400
+#define IEEE80211_CAPINFO_APSD              0x0800
+/* bit 12 is reserved */
+#define IEEE80211_CAPINFO_DSSSOFDM          0x2000
+/* bits 14-15 are reserved */
+
+/*
+ * Authentication Modes
+ */
+
+enum ieee80211_authmode {
+    IEEE80211_AUTH_NONE     = 0,
+    IEEE80211_AUTH_OPEN     = 1,
+    IEEE80211_AUTH_SHARED   = 2,
+    IEEE80211_AUTH_8021X    = 3,
+    IEEE80211_AUTH_AUTO     = 4,   /* auto-select/accept */
+    /* NB: these are used only for ioctls */
+    IEEE80211_AUTH_WPA      = 5,  /* WPA/RSN  w/ 802.1x */
+    IEEE80211_AUTH_WPA_PSK  = 6,  /* WPA/RSN  w/ PSK */
+    IEEE80211_AUTH_WPA_CCKM = 7,  /* WPA/RSN IE  w/ CCKM */
+};
+
+#define IEEE80211_PS_MAX_QUEUE    50 /*Maximum no of buffers that can be queues for PS*/
+
+#include "athendpack.h"
+
+#endif /* _NET80211_IEEE80211_H_ */
diff --git a/drivers/net/ath6kl/wlan/include/ieee80211_node.h b/drivers/net/ath6kl/wlan/include/ieee80211_node.h
new file mode 100644
index 00000000000..683deec87b2
--- /dev/null
+++ b/drivers/net/ath6kl/wlan/include/ieee80211_node.h
@@ -0,0 +1,93 @@
+//------------------------------------------------------------------------------
+// <copyright file="ieee80211_node.h" company="Atheros">
+//    Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _IEEE80211_NODE_H_
+#define _IEEE80211_NODE_H_
+
+/*
+ * Node locking definitions.
+ */
+#define IEEE80211_NODE_LOCK_INIT(_nt)   A_MUTEX_INIT(&(_nt)->nt_nodelock)
+#define IEEE80211_NODE_LOCK_DESTROY(_nt) if (A_IS_MUTEX_VALID(&(_nt)->nt_nodelock)) { \
+                                               A_MUTEX_DELETE(&(_nt)->nt_nodelock); }
+       
+#define IEEE80211_NODE_LOCK(_nt)        A_MUTEX_LOCK(&(_nt)->nt_nodelock)
+#define IEEE80211_NODE_UNLOCK(_nt)      A_MUTEX_UNLOCK(&(_nt)->nt_nodelock)
+#define IEEE80211_NODE_LOCK_BH(_nt)     A_MUTEX_LOCK(&(_nt)->nt_nodelock)
+#define IEEE80211_NODE_UNLOCK_BH(_nt)   A_MUTEX_UNLOCK(&(_nt)->nt_nodelock)
+#define IEEE80211_NODE_LOCK_ASSERT(_nt)
+
+/*
+ * Node reference counting definitions.
+ *
+ * ieee80211_node_initref   initialize the reference count to 1
+ * ieee80211_node_incref    add a reference
+ * ieee80211_node_decref    remove a reference
+ * ieee80211_node_dectestref    remove a reference and return 1 if this
+ *              is the last reference, otherwise 0
+ * ieee80211_node_refcnt    reference count for printing (only)
+ */
+#define ieee80211_node_initref(_ni)     ((_ni)->ni_refcnt = 1)
+#define ieee80211_node_incref(_ni)      ((_ni)->ni_refcnt++)
+#define ieee80211_node_decref(_ni)      ((_ni)->ni_refcnt--)
+#define ieee80211_node_dectestref(_ni)  (((_ni)->ni_refcnt--) == 1)
+#define ieee80211_node_refcnt(_ni)      ((_ni)->ni_refcnt)
+
+#define IEEE80211_NODE_HASHSIZE 32
+/* simple hash is enough for variation of macaddr */
+#define IEEE80211_NODE_HASH(addr)   \
+    (((const A_UINT8 *)(addr))[IEEE80211_ADDR_LEN - 1] % \
+        IEEE80211_NODE_HASHSIZE)
+
+/*
+ * Table of ieee80211_node instances.  Each ieee80211com
+ * has at least one for holding the scan candidates.
+ * When operating as an access point or in ibss mode there
+ * is a second table for associated stations or neighbors.
+ */
+struct ieee80211_node_table {
+    void                   *nt_wmip;       /* back reference */
+    A_MUTEX_T               nt_nodelock;    /* on node table */
+    struct bss              *nt_node_first; /* information of all nodes */
+    struct bss              *nt_node_last;  /* information of all nodes */
+    struct bss              *nt_hash[IEEE80211_NODE_HASHSIZE];
+    const char              *nt_name;   /* for debugging */
+    A_UINT32                nt_scangen; /* gen# for timeout scan */
+#ifdef THREAD_X
+    A_TIMER                 nt_inact_timer;
+    A_UINT8                 isTimerArmed;   /* is the node timer armed */
+#endif
+    A_UINT32                nt_nodeAge; /* node aging time */
+#ifdef OS_ROAM_MANAGEMENT
+    A_UINT32                nt_si_gen; /* gen# for scan indication*/
+#endif
+};
+
+#ifdef THREAD_X
+#define WLAN_NODE_INACT_TIMEOUT_MSEC            20000
+#else
+#define WLAN_NODE_INACT_TIMEOUT_MSEC            120000
+#endif
+   
+#define WLAN_NODE_INACT_CNT            4
+
+#endif /* _IEEE80211_NODE_H_ */
diff --git a/drivers/net/ath6kl/wlan/src/wlan_node.c b/drivers/net/ath6kl/wlan/src/wlan_node.c
new file mode 100644
index 00000000000..6ec4e48eb2f
--- /dev/null
+++ b/drivers/net/ath6kl/wlan/src/wlan_node.c
@@ -0,0 +1,636 @@
+//------------------------------------------------------------------------------
+// <copyright file="wlan_node.c" company="Atheros">
+//    Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// IEEE 802.11 node handling support.
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#include <a_config.h>
+#include <athdefs.h>
+#include <a_types.h>
+#include <a_osapi.h>
+#define ATH_MODULE_NAME wlan
+#include <a_debug.h>
+#include "htc.h"
+#include "htc_api.h"
+#include <wmi.h>
+#include <ieee80211.h>
+#include <wlan_api.h>
+#include <wmi_api.h>
+#include <ieee80211_node.h>
+
+#define ATH_DEBUG_WLAN ATH_DEBUG_MAKE_MODULE_MASK(0)
+
+#ifdef ATH_DEBUG_MODULE
+
+static ATH_DEBUG_MASK_DESCRIPTION wlan_debug_desc[] = {
+    { ATH_DEBUG_WLAN , "General WLAN Node Tracing"},
+};
+
+ATH_DEBUG_INSTANTIATE_MODULE_VAR(wlan,
+                                 "wlan",
+                                 "WLAN Node Management",
+                                 ATH_DEBUG_MASK_DEFAULTS,
+                                 ATH_DEBUG_DESCRIPTION_COUNT(wlan_debug_desc),
+                                 wlan_debug_desc);
+                                 
+#endif
+
+#ifdef THREAD_X
+static void wlan_node_timeout(A_ATH_TIMER arg);
+#endif
+
+static bss_t * _ieee80211_find_node (struct ieee80211_node_table *nt,
+                                     const A_UINT8 *macaddr);
+
+bss_t *
+wlan_node_alloc(struct ieee80211_node_table *nt, int wh_size)
+{
+    bss_t *ni;
+
+    ni = A_MALLOC_NOWAIT(sizeof(bss_t));
+
+    if (ni != NULL) {
+        if (wh_size)
+        {
+        ni->ni_buf = A_MALLOC_NOWAIT(wh_size);
+        if (ni->ni_buf == NULL) {
+            A_FREE(ni);
+            ni = NULL;
+            return ni;
+        }
+        }
+    } else {
+        return ni;
+    }
+
+    /* Make sure our lists are clean */
+    ni->ni_list_next = NULL;
+    ni->ni_list_prev = NULL;
+    ni->ni_hash_next = NULL;
+    ni->ni_hash_prev = NULL;
+
+    //
+    // ni_scangen never initialized before and during suspend/resume of winmobile,
+    // that some junk has been stored in this, due to this scan list didn't properly updated
+    //
+    ni->ni_scangen   = 0;
+
+#ifdef OS_ROAM_MANAGEMENT
+    ni->ni_si_gen    = 0;
+#endif
+
+    return ni;
+}
+
+void
+wlan_node_free(bss_t *ni)
+{
+    if (ni->ni_buf != NULL) {
+        A_FREE(ni->ni_buf);
+    }
+    A_FREE(ni);
+}
+
+void
+wlan_setup_node(struct ieee80211_node_table *nt, bss_t *ni,
+                const A_UINT8 *macaddr)
+{
+    int hash;
+    A_UINT32 timeoutValue = 0;
+
+    A_MEMCPY(ni->ni_macaddr, macaddr, IEEE80211_ADDR_LEN);
+    hash = IEEE80211_NODE_HASH (macaddr);
+    ieee80211_node_initref (ni);     /* mark referenced */
+
+    timeoutValue = nt->nt_nodeAge;
+
+    ni->ni_tstamp = A_GET_MS (timeoutValue);
+    ni->ni_actcnt = WLAN_NODE_INACT_CNT;
+
+    IEEE80211_NODE_LOCK_BH(nt);
+
+    /* Insert at the end of the node list */
+    ni->ni_list_next = NULL;
+    ni->ni_list_prev = nt->nt_node_last;
+    if(nt->nt_node_last != NULL)
+    {
+        nt->nt_node_last->ni_list_next = ni;
+    }
+    nt->nt_node_last = ni;
+    if(nt->nt_node_first == NULL)
+    {
+        nt->nt_node_first = ni;
+    }
+
+    /* Insert into the hash list i.e. the bucket */
+    if((ni->ni_hash_next = nt->nt_hash[hash]) != NULL)
+    {
+        nt->nt_hash[hash]->ni_hash_prev = ni;
+    }
+    ni->ni_hash_prev = NULL;
+    nt->nt_hash[hash] = ni;
+
+#ifdef THREAD_X
+    if (!nt->isTimerArmed) {
+        A_TIMEOUT_MS(&nt->nt_inact_timer, timeoutValue, 0);
+        nt->isTimerArmed = TRUE;
+    }
+#endif
+
+    IEEE80211_NODE_UNLOCK_BH(nt);
+}
+
+static bss_t *
+_ieee80211_find_node(struct ieee80211_node_table *nt,
+    const A_UINT8 *macaddr)
+{
+    bss_t *ni;
+    int hash;
+
+    IEEE80211_NODE_LOCK_ASSERT(nt);
+
+    hash = IEEE80211_NODE_HASH(macaddr);
+    for(ni = nt->nt_hash[hash]; ni; ni = ni->ni_hash_next) {
+        if (IEEE80211_ADDR_EQ(ni->ni_macaddr, macaddr)) {
+            ieee80211_node_incref(ni);  /* mark referenced */
+            return ni;
+        }
+    }
+    return NULL;
+}
+
+bss_t *
+wlan_find_node(struct ieee80211_node_table *nt, const A_UINT8 *macaddr)
+{
+    bss_t *ni;
+
+    IEEE80211_NODE_LOCK(nt);
+    ni = _ieee80211_find_node(nt, macaddr);
+    IEEE80211_NODE_UNLOCK(nt);
+    return ni;
+}
+
+/*
+ * Reclaim a node.  If this is the last reference count then
+ * do the normal free work.  Otherwise remove it from the node
+ * table and mark it gone by clearing the back-reference.
+ */
+void
+wlan_node_reclaim(struct ieee80211_node_table *nt, bss_t *ni)
+{
+    IEEE80211_NODE_LOCK(nt);
+
+    if(ni->ni_list_prev == NULL)
+    {
+        /* First in list so fix the list head */
+        nt->nt_node_first = ni->ni_list_next;
+    }
+    else
+    {
+        ni->ni_list_prev->ni_list_next = ni->ni_list_next;
+    }
+
+    if(ni->ni_list_next == NULL)
+    {
+        /* Last in list so fix list tail */
+        nt->nt_node_last = ni->ni_list_prev;
+    }
+    else
+    {
+        ni->ni_list_next->ni_list_prev = ni->ni_list_prev;
+    }
+
+    if(ni->ni_hash_prev == NULL)
+    {
+        /* First in list so fix the list head */
+        int hash;
+        hash = IEEE80211_NODE_HASH(ni->ni_macaddr);
+        nt->nt_hash[hash] = ni->ni_hash_next;
+    }
+    else
+    {
+        ni->ni_hash_prev->ni_hash_next = ni->ni_hash_next;
+    }
+
+    if(ni->ni_hash_next != NULL)
+    {
+        ni->ni_hash_next->ni_hash_prev = ni->ni_hash_prev;
+    }
+    wlan_node_free(ni);
+
+    IEEE80211_NODE_UNLOCK(nt);
+}
+
+static void
+wlan_node_dec_free(bss_t *ni)
+{
+    if (ieee80211_node_dectestref(ni)) {
+        wlan_node_free(ni);
+    }
+}
+
+void
+wlan_free_allnodes(struct ieee80211_node_table *nt)
+{
+    bss_t *ni;
+
+    while ((ni = nt->nt_node_first) != NULL) {
+        wlan_node_reclaim(nt, ni);
+    }
+}
+
+void
+wlan_iterate_nodes(struct ieee80211_node_table *nt, wlan_node_iter_func *f,
+                   void *arg)
+{
+    bss_t *ni;
+    A_UINT32 gen;
+
+    gen = ++nt->nt_scangen;
+
+    IEEE80211_NODE_LOCK(nt);
+    for (ni = nt->nt_node_first; ni; ni = ni->ni_list_next) {
+        if (ni->ni_scangen != gen) {
+            ni->ni_scangen = gen;
+            (void) ieee80211_node_incref(ni);
+            (*f)(arg, ni);
+            wlan_node_dec_free(ni);
+        }
+    }
+    IEEE80211_NODE_UNLOCK(nt);
+}
+
+/*
+ * Node table support.
+ */
+void
+wlan_node_table_init(void *wmip, struct ieee80211_node_table *nt)
+{
+    int i;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_WLAN, ("node table = 0x%lx\n", (unsigned long)nt));
+    IEEE80211_NODE_LOCK_INIT(nt);
+
+    A_REGISTER_MODULE_DEBUG_INFO(wlan);
+    
+    nt->nt_node_first = nt->nt_node_last = NULL;
+    for(i = 0; i < IEEE80211_NODE_HASHSIZE; i++)
+    {
+        nt->nt_hash[i] = NULL;
+    }
+
+#ifdef THREAD_X
+    A_INIT_TIMER(&nt->nt_inact_timer, wlan_node_timeout, nt);
+    nt->isTimerArmed = FALSE;
+#endif
+    nt->nt_wmip = wmip;
+    nt->nt_nodeAge = WLAN_NODE_INACT_TIMEOUT_MSEC;
+
+    //
+    // nt_scangen never initialized before and during suspend/resume of winmobile, 
+    // that some junk has been stored in this, due to this scan list didn't properly updated
+    //
+    nt->nt_scangen   = 0;
+
+#ifdef OS_ROAM_MANAGEMENT
+    nt->nt_si_gen    = 0;
+#endif
+}
+
+void
+wlan_set_nodeage(struct ieee80211_node_table *nt, A_UINT32 nodeAge)
+{
+    nt->nt_nodeAge = nodeAge;
+    return;
+}
+void
+wlan_refresh_inactive_nodes (struct ieee80211_node_table *nt)
+{
+#ifdef THREAD_X
+    bss_t *bss, *nextBss;
+    A_UINT8 myBssid[IEEE80211_ADDR_LEN], reArmTimer = FALSE;
+
+    wmi_get_current_bssid(nt->nt_wmip, myBssid);
+
+    bss = nt->nt_node_first;
+    while (bss != NULL)
+    {
+        nextBss = bss->ni_list_next;
+        if (A_MEMCMP(myBssid, bss->ni_macaddr, sizeof(myBssid)) != 0)
+        {
+               /*
+                * free up all but the current bss - if set
+                */
+                wlan_node_reclaim(nt, bss);
+
+        }
+        bss = nextBss;
+    }
+#else
+    bss_t *bss, *nextBss;
+    A_UINT8 myBssid[IEEE80211_ADDR_LEN];
+    A_UINT32 timeoutValue = 0;
+    A_UINT32 now = A_GET_MS(0);
+    timeoutValue = nt->nt_nodeAge;
+
+    wmi_get_current_bssid(nt->nt_wmip, myBssid);
+
+    bss = nt->nt_node_first;
+    while (bss != NULL)
+    {
+        nextBss = bss->ni_list_next;
+        if (A_MEMCMP(myBssid, bss->ni_macaddr, sizeof(myBssid)) != 0)
+        {
+
+            if (bss->ni_tstamp <= now || --bss->ni_actcnt == 0)
+            {
+               /*
+                * free up all but the current bss - if set
+                */
+                wlan_node_reclaim(nt, bss);
+            }
+        }
+        bss = nextBss;
+    }
+#endif
+}
+
+#ifdef THREAD_X
+static void
+wlan_node_timeout (A_ATH_TIMER arg)
+{
+    struct ieee80211_node_table *nt = (struct ieee80211_node_table *)arg;
+    bss_t *bss, *nextBss;
+    A_UINT8 myBssid[IEEE80211_ADDR_LEN], reArmTimer = FALSE;
+    A_UINT32 timeoutValue = 0;
+
+    timeoutValue = nt->nt_nodeAge;
+
+    wmi_get_current_bssid(nt->nt_wmip, myBssid);
+
+    bss = nt->nt_node_first;
+    while (bss != NULL)
+    {
+        nextBss = bss->ni_list_next;
+        if (A_MEMCMP(myBssid, bss->ni_macaddr, sizeof(myBssid)) != 0)
+        {
+
+            if (bss->ni_tstamp <= A_GET_MS(0))
+            {
+               /*
+                * free up all but the current bss - if set
+                */
+                wlan_node_reclaim(nt, bss);
+            }
+            else
+            {
+                /*
+                 * Re-arm timer, only when we have a bss other than
+                 * current bss AND it is not aged-out.
+                 */
+                reArmTimer = TRUE;
+            }
+        }
+        bss = nextBss;
+    }
+
+    if (reArmTimer)
+        A_TIMEOUT_MS (&nt->nt_inact_timer, timeoutValue, 0);
+
+    nt->isTimerArmed = reArmTimer;
+}
+#endif
+
+void
+wlan_node_table_cleanup(struct ieee80211_node_table *nt)
+{
+#ifdef THREAD_X
+    A_UNTIMEOUT(&nt->nt_inact_timer);
+    A_DELETE_TIMER(&nt->nt_inact_timer);
+#endif
+    wlan_free_allnodes(nt);
+    IEEE80211_NODE_LOCK_DESTROY(nt);
+}
+
+bss_t *
+wlan_find_Ssidnode (struct ieee80211_node_table *nt, A_UCHAR *pSsid,
+                    A_UINT32 ssidLength, A_BOOL bIsWPA2, A_BOOL bMatchSSID)
+{
+    bss_t   *ni = NULL;
+    A_UCHAR *pIESsid = NULL;
+
+    IEEE80211_NODE_LOCK (nt);
+
+    for (ni = nt->nt_node_first; ni; ni = ni->ni_list_next) {
+        pIESsid = ni->ni_cie.ie_ssid;
+        if (pIESsid[1] <= 32) {
+
+            // Step 1 : Check SSID
+            if (0x00 == memcmp (pSsid, &pIESsid[2], ssidLength)) {
+
+                //
+                // Step 2.1 : Check MatchSSID is TRUE, if so, return Matched SSID
+                // Profile, otherwise check whether WPA2 or WPA
+                //
+                if (TRUE == bMatchSSID) {
+                    ieee80211_node_incref (ni);  /* mark referenced */
+                    IEEE80211_NODE_UNLOCK (nt);
+                    return ni;
+                }
+
+                // Step 2 : if SSID matches, check WPA or WPA2
+                if (TRUE == bIsWPA2 && NULL != ni->ni_cie.ie_rsn) {
+                    ieee80211_node_incref (ni);  /* mark referenced */
+                    IEEE80211_NODE_UNLOCK (nt);
+                    return ni;
+                }
+                if (FALSE == bIsWPA2 && NULL != ni->ni_cie.ie_wpa) {
+                    ieee80211_node_incref(ni);  /* mark referenced */
+                    IEEE80211_NODE_UNLOCK (nt);
+                    return ni;
+                }
+            }
+        }
+    }
+
+    IEEE80211_NODE_UNLOCK (nt);
+
+    return NULL;
+}
+
+void
+wlan_node_return (struct ieee80211_node_table *nt, bss_t *ni)
+{
+    IEEE80211_NODE_LOCK (nt);
+    wlan_node_dec_free (ni);
+    IEEE80211_NODE_UNLOCK (nt);
+}
+
+void
+wlan_node_remove_core (struct ieee80211_node_table *nt, bss_t *ni)
+{
+    if(ni->ni_list_prev == NULL)
+    {
+        /* First in list so fix the list head */
+        nt->nt_node_first = ni->ni_list_next;
+    }
+    else
+    {
+        ni->ni_list_prev->ni_list_next = ni->ni_list_next;
+    }
+
+    if(ni->ni_list_next == NULL)
+    {
+        /* Last in list so fix list tail */
+        nt->nt_node_last = ni->ni_list_prev;
+    }
+    else
+    {
+        ni->ni_list_next->ni_list_prev = ni->ni_list_prev;
+    }
+
+    if(ni->ni_hash_prev == NULL)
+    {
+        /* First in list so fix the list head */
+        int hash;
+        hash = IEEE80211_NODE_HASH(ni->ni_macaddr);
+        nt->nt_hash[hash] = ni->ni_hash_next;
+    }
+    else
+    {
+        ni->ni_hash_prev->ni_hash_next = ni->ni_hash_next;
+    }
+
+    if(ni->ni_hash_next != NULL)
+    {
+        ni->ni_hash_next->ni_hash_prev = ni->ni_hash_prev;
+    }
+}
+
+bss_t *
+wlan_node_remove(struct ieee80211_node_table *nt, A_UINT8 *bssid)
+{
+    bss_t *bss, *nextBss;
+
+    IEEE80211_NODE_LOCK(nt);
+
+    bss = nt->nt_node_first;
+
+    while (bss != NULL)
+    {
+        nextBss = bss->ni_list_next;
+
+        if (A_MEMCMP(bssid, bss->ni_macaddr, 6) == 0)
+        {
+            wlan_node_remove_core (nt, bss);
+            IEEE80211_NODE_UNLOCK(nt);
+            return bss;
+        }
+
+        bss = nextBss;
+    }
+
+    IEEE80211_NODE_UNLOCK(nt);
+    return NULL;
+}
+
+bss_t *
+wlan_find_matching_Ssidnode (struct ieee80211_node_table *nt, A_UCHAR *pSsid,
+                    A_UINT32 ssidLength, A_UINT32 dot11AuthMode, A_UINT32 authMode,
+                   A_UINT32 pairwiseCryptoType, A_UINT32 grpwiseCryptoTyp)
+{
+    bss_t   *ni = NULL;
+    bss_t   *best_ni = NULL;
+    A_UCHAR *pIESsid = NULL;
+
+    IEEE80211_NODE_LOCK (nt);
+
+    for (ni = nt->nt_node_first; ni; ni = ni->ni_list_next) {
+        pIESsid = ni->ni_cie.ie_ssid;
+        if (pIESsid[1] <= 32) {
+
+            // Step 1 : Check SSID
+            if (0x00 == memcmp (pSsid, &pIESsid[2], ssidLength)) {
+
+                if (ni->ni_cie.ie_capInfo & 0x10)
+                {
+
+                    if ((NULL != ni->ni_cie.ie_rsn) && (WPA2_PSK_AUTH == authMode))
+                    {
+                        /* WPA2 */
+                        if (NULL == best_ni)
+                        {
+                            best_ni = ni;
+                        }
+                        else if (ni->ni_rssi > best_ni->ni_rssi)
+                        {
+                            best_ni = ni;
+                        }
+                    }
+                    else if ((NULL != ni->ni_cie.ie_wpa) && (WPA_PSK_AUTH == authMode))
+                    {
+                        /* WPA */
+                        if (NULL == best_ni)
+                        {
+                            best_ni = ni;
+                        }
+                        else if (ni->ni_rssi > best_ni->ni_rssi)
+                        {
+                            best_ni = ni;
+                        }
+                    }
+                    else if (WEP_CRYPT == pairwiseCryptoType)
+                    {
+                        /* WEP */
+                        if (NULL == best_ni)
+                        {
+                            best_ni = ni;
+                        }
+                        else if (ni->ni_rssi > best_ni->ni_rssi)
+                        {
+                            best_ni = ni;
+                        }
+                    }
+                }
+                else
+                {
+                    /* open AP */
+                    if ((OPEN_AUTH == authMode) && (NONE_CRYPT == pairwiseCryptoType))
+                    {
+                        if (NULL == best_ni)
+                        {
+                            best_ni = ni;
+                        }
+                        else if (ni->ni_rssi > best_ni->ni_rssi)
+                        {
+                            best_ni = ni;
+                        }
+                    }
+                }
+            }
+        }
+    }
+
+    IEEE80211_NODE_UNLOCK (nt);
+
+    return best_ni;
+}
+
diff --git a/drivers/net/ath6kl/wlan/src/wlan_recv_beacon.c b/drivers/net/ath6kl/wlan/src/wlan_recv_beacon.c
new file mode 100644
index 00000000000..f4926f215bb
--- /dev/null
+++ b/drivers/net/ath6kl/wlan/src/wlan_recv_beacon.c
@@ -0,0 +1,200 @@
+//------------------------------------------------------------------------------
+// <copyright file="wlan_recv_beacon.c" company="Atheros">
+//    Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// IEEE 802.11 input handling.
+//
+// Author(s): ="Atheros"
+//==============================================================================
+
+#include "a_config.h"
+#include "athdefs.h"
+#include "a_types.h"
+#include "a_osapi.h"
+#include <wmi.h>
+#include <ieee80211.h>
+#include <wlan_api.h>
+
+#define IEEE80211_VERIFY_LENGTH(_len, _minlen) do {         \
+    if ((_len) < (_minlen)) {                   \
+        return A_EINVAL;                         \
+    }                               \
+} while (0)
+
+#define IEEE80211_VERIFY_ELEMENT(__elem, __maxlen) do {         \
+    if ((__elem) == NULL) {                     \
+        return A_EINVAL;                         \
+    }                               \
+    if ((__elem)[1] > (__maxlen)) {                 \
+        return A_EINVAL;                         \
+    }                               \
+} while (0)
+
+
+/* unaligned little endian access */
+#define LE_READ_2(p)                            \
+    ((A_UINT16)                            \
+     ((((A_UINT8 *)(p))[0]      ) | (((A_UINT8 *)(p))[1] <<  8)))
+
+#define LE_READ_4(p)                            \
+    ((A_UINT32)                            \
+     ((((A_UINT8 *)(p))[0]      ) | (((A_UINT8 *)(p))[1] <<  8) | \
+      (((A_UINT8 *)(p))[2] << 16) | (((A_UINT8 *)(p))[3] << 24)))
+
+
+static int __inline
+iswpaoui(const A_UINT8 *frm)
+{
+    return frm[1] > 3 && LE_READ_4(frm+2) == ((WPA_OUI_TYPE<<24)|WPA_OUI);
+}
+
+static int __inline
+iswmmoui(const A_UINT8 *frm)
+{
+    return frm[1] > 3 && LE_READ_4(frm+2) == ((WMM_OUI_TYPE<<24)|WMM_OUI);
+}
+
+/* unused functions for now */
+#if 0
+static int __inline
+iswmmparam(const A_UINT8 *frm)
+{
+    return frm[1] > 5 && frm[6] == WMM_PARAM_OUI_SUBTYPE;
+}
+
+static int __inline
+iswmminfo(const A_UINT8 *frm)
+{
+    return frm[1] > 5 && frm[6] == WMM_INFO_OUI_SUBTYPE;
+}
+#endif
+
+static int __inline
+isatherosoui(const A_UINT8 *frm)
+{
+    return frm[1] > 3 && LE_READ_4(frm+2) == ((ATH_OUI_TYPE<<24)|ATH_OUI);
+}
+
+static int __inline
+iswscoui(const A_UINT8 *frm)
+{
+    return frm[1] > 3 && LE_READ_4(frm+2) == ((0x04<<24)|WPA_OUI);
+}
+
+A_STATUS
+wlan_parse_beacon(A_UINT8 *buf, int framelen, struct ieee80211_common_ie *cie)
+{
+    A_UINT8 *frm, *efrm;
+    A_UINT8 elemid_ssid = FALSE;
+
+    frm = buf;
+    efrm = (A_UINT8 *) (frm + framelen);
+
+    /*
+     * beacon/probe response frame format
+     *  [8] time stamp
+     *  [2] beacon interval
+     *  [2] capability information
+     *  [tlv] ssid
+     *  [tlv] supported rates
+     *  [tlv] country information
+     *  [tlv] parameter set (FH/DS)
+     *  [tlv] erp information
+     *  [tlv] extended supported rates
+     *  [tlv] WMM
+     *  [tlv] WPA or RSN
+     *  [tlv] Atheros Advanced Capabilities
+     */
+    IEEE80211_VERIFY_LENGTH(efrm - frm, 12);
+    A_MEMZERO(cie, sizeof(*cie));
+
+    cie->ie_tstamp = frm; frm += 8;
+    cie->ie_beaconInt = A_LE2CPU16(*(A_UINT16 *)frm);  frm += 2;
+    cie->ie_capInfo = A_LE2CPU16(*(A_UINT16 *)frm);  frm += 2;
+    cie->ie_chan = 0;
+
+    while (frm < efrm) {
+        switch (*frm) {
+        case IEEE80211_ELEMID_SSID:
+            if (!elemid_ssid) {
+                cie->ie_ssid = frm;
+                elemid_ssid = TRUE;
+            }
+            break;
+        case IEEE80211_ELEMID_RATES:
+            cie->ie_rates = frm;
+            break;
+        case IEEE80211_ELEMID_COUNTRY:
+            cie->ie_country = frm;
+            break;
+        case IEEE80211_ELEMID_FHPARMS:
+            break;
+        case IEEE80211_ELEMID_DSPARMS:
+            cie->ie_chan = frm[2];
+            break;
+        case IEEE80211_ELEMID_TIM:
+            cie->ie_tim = frm;
+            break;
+        case IEEE80211_ELEMID_IBSSPARMS:
+            break;
+        case IEEE80211_ELEMID_XRATES:
+            cie->ie_xrates = frm;
+            break;
+        case IEEE80211_ELEMID_ERP:
+            if (frm[1] != 1) {
+                //A_PRINTF("Discarding ERP Element - Bad Len\n");
+                return A_EINVAL;
+            }
+            cie->ie_erp = frm[2];
+            break;
+        case IEEE80211_ELEMID_RSN:
+            cie->ie_rsn = frm;
+            break;
+        case IEEE80211_ELEMID_HTCAP_ANA:
+            cie->ie_htcap = frm;
+            break;
+        case IEEE80211_ELEMID_HTINFO_ANA:
+            cie->ie_htop = frm;
+            break;
+#ifdef WAPI_ENABLE
+		case IEEE80211_ELEMID_WAPI:
+            cie->ie_wapi = frm;
+            break;
+#endif
+        case IEEE80211_ELEMID_VENDOR:
+            if (iswpaoui(frm)) {
+                cie->ie_wpa = frm;
+            } else if (iswmmoui(frm)) {
+                cie->ie_wmm = frm;
+            } else if (isatherosoui(frm)) {
+                cie->ie_ath = frm;
+            } else if(iswscoui(frm)) {
+                cie->ie_wsc = frm;
+            }
+            break;
+        default:
+            break;
+        }
+        frm += frm[1] + 2;
+    }
+    IEEE80211_VERIFY_ELEMENT(cie->ie_rates, IEEE80211_RATE_MAXSIZE);
+    IEEE80211_VERIFY_ELEMENT(cie->ie_ssid, IEEE80211_NWID_LEN);
+
+    return A_OK;
+}
diff --git a/drivers/net/ath6kl/wlan/src/wlan_utils.c b/drivers/net/ath6kl/wlan/src/wlan_utils.c
new file mode 100644
index 00000000000..1eee7bab3e5
--- /dev/null
+++ b/drivers/net/ath6kl/wlan/src/wlan_utils.c
@@ -0,0 +1,61 @@
+//------------------------------------------------------------------------------
+// <copyright file="wlan_utils.c" company="Atheros">
+//    Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// This module implements frequently used wlan utilies
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#include <a_config.h>
+#include <athdefs.h>
+#include <a_types.h>
+#include <a_osapi.h>
+
+/*
+ * converts ieee channel number to frequency
+ */
+A_UINT16
+wlan_ieee2freq(int chan)
+{
+    if (chan == 14) {
+        return 2484;
+    }
+    if (chan < 14) {    /* 0-13 */
+        return (2407 + (chan*5));
+    }
+    if (chan < 27) {    /* 15-26 */
+        return (2512 + ((chan-15)*20));
+    }
+    return (5000 + (chan*5));
+}
+
+/*
+ * Converts MHz frequency to IEEE channel number.
+ */
+A_UINT32
+wlan_freq2ieee(A_UINT16 freq)
+{
+    if (freq == 2484)
+        return 14;
+    if (freq < 2484)
+        return (freq - 2407) / 5;
+    if (freq < 5000)
+        return 15 + ((freq - 2512) / 20);
+    return (freq - 5000) / 5;
+}
diff --git a/drivers/net/ath6kl/wmi/wmi.c b/drivers/net/ath6kl/wmi/wmi.c
new file mode 100644
index 00000000000..7800778099b
--- /dev/null
+++ b/drivers/net/ath6kl/wmi/wmi.c
@@ -0,0 +1,6670 @@
+//------------------------------------------------------------------------------
+// Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// This module implements the hardware independent layer of the
+// Wireless Module Interface (WMI) protocol.
+//
+// Author(s): ="Atheros"
+//==============================================================================
+
+#include <a_config.h>
+#include <athdefs.h>
+#include <a_types.h>
+#include <a_osapi.h>
+#include "htc.h"
+#include "htc_api.h"
+#include "wmi.h"
+#include <wlan_api.h>
+#include <wmi_api.h>
+#include <ieee80211.h>
+#include <ieee80211_node.h>
+#include "dset_api.h"
+#include "gpio_api.h"
+#include "wmi_host.h"
+#include "a_drv.h"
+#include "a_drv_api.h"
+#define ATH_MODULE_NAME wmi
+#include "a_debug.h"
+#include "dbglog_api.h"
+#include "roaming.h"
+
+#define ATH_DEBUG_WMI ATH_DEBUG_MAKE_MODULE_MASK(0)
+
+#ifdef ATH_DEBUG_MODULE
+
+static ATH_DEBUG_MASK_DESCRIPTION wmi_debug_desc[] = {
+    { ATH_DEBUG_WMI , "General WMI Tracing"},
+};
+
+ATH_DEBUG_INSTANTIATE_MODULE_VAR(wmi,
+                                 "wmi",
+                                 "Wireless Module Interface",
+                                 ATH_DEBUG_MASK_DEFAULTS,
+                                 ATH_DEBUG_DESCRIPTION_COUNT(wmi_debug_desc),
+                                 wmi_debug_desc);
+
+#endif
+
+#ifndef REXOS
+#define DBGARG      _A_FUNCNAME_
+#define DBGFMT      "%s() : "
+#define DBG_WMI     ATH_DEBUG_WMI
+#define DBG_ERROR   ATH_DEBUG_ERR
+#define DBG_WMI2    ATH_DEBUG_WMI
+#define A_DPRINTF   AR_DEBUG_PRINTF
+#endif
+
+static A_STATUS wmi_ready_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+
+static A_STATUS wmi_connect_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
+                                     int len);
+static A_STATUS wmi_disconnect_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
+                                        int len);
+
+static A_STATUS wmi_tkip_micerr_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
+                                        int len);
+static A_STATUS wmi_bssInfo_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
+                                     int len);
+static A_STATUS wmi_opt_frame_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
+                                       int len);
+static A_STATUS wmi_pstream_timeout_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
+                                     int len);
+static A_STATUS wmi_sync_point(struct wmi_t *wmip);
+
+static A_STATUS wmi_bitrate_reply_rx(struct wmi_t *wmip, A_UINT8 *datap,
+                                     int len);
+static A_STATUS wmi_ratemask_reply_rx(struct wmi_t *wmip, A_UINT8 *datap,
+                                     int len);
+static A_STATUS wmi_channelList_reply_rx(struct wmi_t *wmip, A_UINT8 *datap,
+                                         int len);
+static A_STATUS wmi_regDomain_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
+                                       int len);
+static A_STATUS wmi_txPwr_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+static A_STATUS wmi_neighborReport_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
+                                             int len);
+
+static A_STATUS wmi_dset_open_req_rx(struct wmi_t *wmip, A_UINT8 *datap,
+                                     int len);
+#ifdef CONFIG_HOST_DSET_SUPPORT
+static A_STATUS wmi_dset_close_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+static A_STATUS wmi_dset_data_req_rx(struct wmi_t *wmip, A_UINT8 *datap,
+                                     int len);
+#endif /* CONFIG_HOST_DSET_SUPPORT */
+
+
+static A_STATUS wmi_scanComplete_rx(struct wmi_t *wmip, A_UINT8 *datap,
+                                     int len);
+static A_STATUS wmi_errorEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+static A_STATUS wmi_statsEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+static A_STATUS wmi_rssiThresholdEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+static A_STATUS wmi_hbChallengeResp_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+static A_STATUS wmi_reportErrorEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+static A_STATUS wmi_cac_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+static A_STATUS wmi_channel_change_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+static A_STATUS wmi_roam_tbl_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
+                                      int len);
+static A_STATUS wmi_roam_data_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
+                                      int len);
+static A_STATUS wmi_get_wow_list_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
+                                      int len);
+static A_STATUS
+wmi_get_pmkid_list_event_rx(struct wmi_t *wmip, A_UINT8 *datap, A_UINT32 len);
+
+static A_STATUS
+wmi_set_params_event_rx(struct wmi_t *wmip, A_UINT8 *datap, A_UINT32 len);
+
+static A_STATUS
+wmi_acm_reject_event_rx(struct wmi_t *wmip, A_UINT8 *datap, A_UINT32 len);
+
+#ifdef CONFIG_HOST_GPIO_SUPPORT
+static A_STATUS wmi_gpio_intr_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+static A_STATUS wmi_gpio_data_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+static A_STATUS wmi_gpio_ack_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+#endif /* CONFIG_HOST_GPIO_SUPPORT */
+
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+static A_STATUS
+wmi_tcmd_test_report_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+#endif
+
+static A_STATUS
+wmi_txRetryErrEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+
+static A_STATUS
+wmi_snrThresholdEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+
+static A_STATUS
+wmi_lqThresholdEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+
+static A_BOOL
+wmi_is_bitrate_index_valid(struct wmi_t *wmip, A_INT32 rateIndex);
+
+static A_STATUS
+wmi_aplistEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+
+static A_STATUS
+wmi_dbglog_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+
+static A_STATUS wmi_keepalive_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+
+A_STATUS wmi_cmd_send_xtnd(struct wmi_t *wmip, void *osbuf, WMIX_COMMAND_ID cmdId,
+                  WMI_SYNC_FLAG syncflag);
+
+A_UINT8 ar6000_get_upper_threshold(A_INT16 rssi, SQ_THRESHOLD_PARAMS *sq_thresh, A_UINT32 size);
+A_UINT8 ar6000_get_lower_threshold(A_INT16 rssi, SQ_THRESHOLD_PARAMS *sq_thresh, A_UINT32 size);
+
+void wmi_cache_configure_rssithreshold(struct wmi_t *wmip, WMI_RSSI_THRESHOLD_PARAMS_CMD *rssiCmd);
+void wmi_cache_configure_snrthreshold(struct wmi_t *wmip, WMI_SNR_THRESHOLD_PARAMS_CMD *snrCmd);
+static A_STATUS wmi_send_rssi_threshold_params(struct wmi_t *wmip,
+                              WMI_RSSI_THRESHOLD_PARAMS_CMD *rssiCmd);
+static A_STATUS wmi_send_snr_threshold_params(struct wmi_t *wmip,
+                             WMI_SNR_THRESHOLD_PARAMS_CMD *snrCmd);
+#if defined(CONFIG_TARGET_PROFILE_SUPPORT)
+static A_STATUS
+wmi_prof_count_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+#endif /* CONFIG_TARGET_PROFILE_SUPPORT */
+
+static A_STATUS wmi_pspoll_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
+                                     int len);
+static A_STATUS wmi_dtimexpiry_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
+                                     int len);
+
+static A_STATUS wmi_peer_node_event_rx (struct wmi_t *wmip, A_UINT8 *datap,
+                                        int len);
+#ifdef ATH_AR6K_11N_SUPPORT
+static A_STATUS wmi_addba_req_event_rx(struct wmi_t *, A_UINT8 *, int);
+static A_STATUS wmi_addba_resp_event_rx(struct wmi_t *, A_UINT8 *, int);
+static A_STATUS wmi_delba_req_event_rx(struct wmi_t *, A_UINT8 *, int);
+static A_STATUS wmi_btcoex_config_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+static A_STATUS wmi_btcoex_stats_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+#endif
+static A_STATUS wmi_hci_event_rx(struct wmi_t *, A_UINT8 *, int);
+
+#ifdef WAPI_ENABLE
+static A_STATUS wmi_wapi_rekey_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
+                                     int len);
+#endif
+
+#if defined(UNDER_CE)
+#if defined(NDIS51_MINIPORT)
+unsigned int processDot11Hdr = 0;
+#else
+unsigned int processDot11Hdr = 1;
+#endif
+#else
+extern unsigned int processDot11Hdr;
+#endif
+
+int wps_enable;
+static const A_INT32 wmi_rateTable[][2] = {
+  //{W/O SGI, with SGI}
+    {1000, 1000},
+    {2000, 2000},
+    {5500, 5500},
+    {11000, 11000},
+    {6000, 6000},
+    {9000, 9000},
+    {12000, 12000},
+    {18000, 18000},
+    {24000, 24000},
+    {36000, 36000},
+    {48000, 48000},
+    {54000, 54000},
+    {6500, 7200},
+    {13000, 14400},
+    {19500, 21700},
+    {26000, 28900},
+    {39000, 43300},
+    {52000, 57800},
+    {58500, 65000},
+    {65000, 72200},
+    {13500, 15000},
+    {27000, 30000},
+    {40500, 45000},
+    {54000, 60000},
+    {81000, 90000},
+    {108000, 120000},
+    {121500, 135000},
+    {135000, 150000},
+    {0, 0}};
+
+#define MODE_A_SUPPORT_RATE_START       ((A_INT32) 4)
+#define MODE_A_SUPPORT_RATE_STOP        ((A_INT32) 11)
+
+#define MODE_GONLY_SUPPORT_RATE_START   MODE_A_SUPPORT_RATE_START
+#define MODE_GONLY_SUPPORT_RATE_STOP    MODE_A_SUPPORT_RATE_STOP
+
+#define MODE_B_SUPPORT_RATE_START       ((A_INT32) 0)
+#define MODE_B_SUPPORT_RATE_STOP        ((A_INT32) 3)
+
+#define MODE_G_SUPPORT_RATE_START       ((A_INT32) 0)
+#define MODE_G_SUPPORT_RATE_STOP        ((A_INT32) 11)
+
+#define MODE_GHT20_SUPPORT_RATE_START   ((A_INT32) 0)
+#define MODE_GHT20_SUPPORT_RATE_STOP    ((A_INT32) 19)
+
+#define MAX_NUMBER_OF_SUPPORT_RATES     (MODE_GHT20_SUPPORT_RATE_STOP + 1)
+
+/* 802.1d to AC mapping. Refer pg 57 of WMM-test-plan-v1.2 */
+const A_UINT8 up_to_ac[]= {
+                WMM_AC_BE,
+                WMM_AC_BK,
+                WMM_AC_BK,
+                WMM_AC_BE,
+                WMM_AC_VI,
+                WMM_AC_VI,
+                WMM_AC_VO,
+                WMM_AC_VO,
+            };
+
+#include "athstartpack.h"
+
+/* This stuff is used when we want a simple layer-3 visibility */
+typedef PREPACK struct _iphdr {
+    A_UINT8     ip_ver_hdrlen;          /* version and hdr length */
+    A_UINT8     ip_tos;                 /* type of service */
+    A_UINT16    ip_len;                 /* total length */
+    A_UINT16    ip_id;                  /* identification */
+    A_INT16     ip_off;                 /* fragment offset field */
+#define IP_DF 0x4000                    /* dont fragment flag */
+#define IP_MF 0x2000                    /* more fragments flag */
+#define IP_OFFMASK 0x1fff               /* mask for fragmenting bits */
+    A_UINT8     ip_ttl;                 /* time to live */
+    A_UINT8     ip_p;                   /* protocol */
+    A_UINT16    ip_sum;                 /* checksum */
+    A_UINT8     ip_src[4];              /* source and dest address */
+    A_UINT8     ip_dst[4];
+} POSTPACK iphdr;
+
+#include "athendpack.h"
+
+static A_INT16 rssi_event_value = 0;
+static A_INT16 snr_event_value = 0;
+
+A_BOOL is_probe_ssid = FALSE;
+
+void *
+wmi_init(void *devt)
+{
+    struct wmi_t *wmip;
+
+    A_REGISTER_MODULE_DEBUG_INFO(wmi);
+
+    wmip = A_MALLOC (sizeof(struct wmi_t));
+    if (wmip == NULL) {
+        return (NULL);
+    }
+    A_MEMZERO(wmip, sizeof(struct wmi_t ));
+#ifdef THREAD_X
+    INIT_WMI_LOCK(wmip);
+#else
+	A_MUTEX_INIT(&wmip->wmi_lock);
+#endif
+    wmip->wmi_devt = devt;
+    wlan_node_table_init(wmip, &wmip->wmi_scan_table);
+    wmi_qos_state_init(wmip);
+
+    wmip->wmi_powerMode = REC_POWER;
+    wmip->wmi_phyMode = WMI_11G_MODE;
+
+    wmip->wmi_pair_crypto_type  = NONE_CRYPT;
+    wmip->wmi_grp_crypto_type   = NONE_CRYPT;
+
+    wmip->wmi_ht_allowed[A_BAND_24GHZ] = 1;
+    wmip->wmi_ht_allowed[A_BAND_5GHZ] = 1;
+
+    return (wmip);
+}
+
+void
+wmi_qos_state_init(struct wmi_t *wmip)
+{
+    A_UINT8 i;
+
+    if (wmip == NULL) {
+        return;
+    }
+    LOCK_WMI(wmip);
+
+    /* Initialize QoS States */
+    wmip->wmi_numQoSStream = 0;
+
+    wmip->wmi_fatPipeExists = 0;
+
+    for (i=0; i < WMM_NUM_AC; i++) {
+        wmip->wmi_streamExistsForAC[i]=0;
+    }
+
+    UNLOCK_WMI(wmip);
+
+    A_WMI_SET_NUMDATAENDPTS(wmip->wmi_devt, 1);
+}
+
+void
+wmi_set_control_ep(struct wmi_t * wmip, HTC_ENDPOINT_ID eid)
+{
+    A_ASSERT( eid != ENDPOINT_UNUSED);
+    wmip->wmi_endpoint_id = eid;
+}
+
+HTC_ENDPOINT_ID
+wmi_get_control_ep(struct wmi_t * wmip)
+{
+    return(wmip->wmi_endpoint_id);
+}
+
+void
+wmi_shutdown(struct wmi_t *wmip)
+{
+    if (wmip != NULL) {
+        wlan_node_table_cleanup(&wmip->wmi_scan_table);
+        if (A_IS_MUTEX_VALID(&wmip->wmi_lock)) {
+#ifdef THREAD_X
+            DELETE_WMI_LOCK(&wmip);
+#else
+            A_MUTEX_DELETE(&wmip->wmi_lock);
+#endif
+        }
+        A_FREE(wmip);
+    }
+}
+
+/*
+ *  performs DIX to 802.3 encapsulation for transmit packets.
+ *  uses passed in buffer.  Returns buffer or NULL if failed.
+ *  Assumes the entire DIX header is contigous and that there is
+ *  enough room in the buffer for a 802.3 mac header and LLC+SNAP headers.
+ */
+A_STATUS
+wmi_dix_2_dot3(struct wmi_t *wmip, void *osbuf)
+{
+    A_UINT8          *datap;
+    A_UINT16         typeorlen;
+    ATH_MAC_HDR      macHdr;
+    ATH_LLC_SNAP_HDR *llcHdr;
+
+    A_ASSERT(osbuf != NULL);
+
+    if (A_NETBUF_HEADROOM(osbuf) <
+        (sizeof(ATH_LLC_SNAP_HDR) + sizeof(WMI_DATA_HDR)))
+    {
+        return A_NO_MEMORY;
+    }
+
+    datap = A_NETBUF_DATA(osbuf);
+
+    typeorlen = *(A_UINT16 *)(datap + ATH_MAC_LEN + ATH_MAC_LEN);
+
+    if (!IS_ETHERTYPE(A_BE2CPU16(typeorlen))) {
+        /*
+         * packet is already in 802.3 format - return success
+         */
+        A_DPRINTF(DBG_WMI, (DBGFMT "packet already 802.3\n", DBGARG));
+        return (A_OK);
+    }
+
+    /*
+     * Save mac fields and length to be inserted later
+     */
+    A_MEMCPY(macHdr.dstMac, datap, ATH_MAC_LEN);
+    A_MEMCPY(macHdr.srcMac, datap + ATH_MAC_LEN, ATH_MAC_LEN);
+    macHdr.typeOrLen = A_CPU2BE16(A_NETBUF_LEN(osbuf) - sizeof(ATH_MAC_HDR) +
+                                  sizeof(ATH_LLC_SNAP_HDR));
+
+    /*
+     * Make room for LLC+SNAP headers
+     */
+    if (A_NETBUF_PUSH(osbuf, sizeof(ATH_LLC_SNAP_HDR)) != A_OK) {
+        return A_NO_MEMORY;
+    }
+    datap = A_NETBUF_DATA(osbuf);
+
+    A_MEMCPY(datap, &macHdr, sizeof (ATH_MAC_HDR));
+
+    llcHdr = (ATH_LLC_SNAP_HDR *)(datap + sizeof(ATH_MAC_HDR));
+    llcHdr->dsap      = 0xAA;
+    llcHdr->ssap      = 0xAA;
+    llcHdr->cntl      = 0x03;
+    llcHdr->orgCode[0] = 0x0;
+    llcHdr->orgCode[1] = 0x0;
+    llcHdr->orgCode[2] = 0x0;
+    llcHdr->etherType = typeorlen;
+
+    return (A_OK);
+}
+
+A_STATUS wmi_meta_add(struct wmi_t *wmip, void *osbuf, A_UINT8 *pVersion,void *pTxMetaS)
+{
+    switch(*pVersion){
+	case 0:
+    		return (A_OK);
+    	case WMI_META_VERSION_1:
+	        {
+        	WMI_TX_META_V1     *pV1= NULL;
+        	A_ASSERT(osbuf != NULL);
+        	if (A_NETBUF_PUSH(osbuf, WMI_MAX_TX_META_SZ) != A_OK) {
+            		return A_NO_MEMORY;
+        	}
+
+        	pV1 = (WMI_TX_META_V1 *)A_NETBUF_DATA(osbuf);
+        	/* the pktID is used in conjunction with txComplete messages
+        	* allowing the target to notify which tx requests have been
+        	* completed and how. */
+        	pV1->pktID = 0;
+        	/* the ratePolicyID allows the host to specify which rate policy
+        	* to use for transmitting this packet. 0 means use default behavior. */
+        	pV1->ratePolicyID = 0;
+        	A_ASSERT(pVersion != NULL);
+        	/* the version must be used to populate the meta field of the WMI_DATA_HDR */
+        	*pVersion = WMI_META_VERSION_1;
+        	return (A_OK);
+    		}
+#ifdef CONFIG_CHECKSUM_OFFLOAD
+	case WMI_META_VERSION_2:
+		{
+     		WMI_TX_META_V2 *pV2 ;
+        	A_ASSERT(osbuf != NULL);
+        	if (A_NETBUF_PUSH(osbuf, WMI_MAX_TX_META_SZ) != A_OK) {
+            		return A_NO_MEMORY;
+        	}
+         	pV2 = (WMI_TX_META_V2 *)A_NETBUF_DATA(osbuf);
+         	A_MEMCPY(pV2,(WMI_TX_META_V2 *)pTxMetaS,sizeof(WMI_TX_META_V2));
+         	return (A_OK);
+    		}
+#endif
+	default:
+		return (A_OK);
+    }
+}
+
+/* Adds a WMI data header */
+A_STATUS
+wmi_data_hdr_add(struct wmi_t *wmip, void *osbuf, A_UINT8 msgType, A_BOOL bMoreData,
+                    WMI_DATA_HDR_DATA_TYPE data_type,A_UINT8 metaVersion, void *pTxMetaS)
+{
+    WMI_DATA_HDR     *dtHdr;
+//    A_UINT8 metaVersion = 0;
+    A_STATUS status;
+
+    A_ASSERT(osbuf != NULL);
+
+    /* adds the meta data field after the wmi data hdr. If metaVersion
+     * is returns 0 then no meta field was added. */
+    if ((status = wmi_meta_add(wmip, osbuf, &metaVersion,pTxMetaS)) != A_OK) {
+        return status;
+    }
+
+    if (A_NETBUF_PUSH(osbuf, sizeof(WMI_DATA_HDR)) != A_OK) {
+        return A_NO_MEMORY;
+    }
+
+    dtHdr = (WMI_DATA_HDR *)A_NETBUF_DATA(osbuf);
+    A_MEMZERO(dtHdr, sizeof(WMI_DATA_HDR));
+
+    WMI_DATA_HDR_SET_MSG_TYPE(dtHdr, msgType);
+    WMI_DATA_HDR_SET_DATA_TYPE(dtHdr, data_type);
+
+    if (bMoreData) {
+        WMI_DATA_HDR_SET_MORE_BIT(dtHdr);
+    }
+
+    WMI_DATA_HDR_SET_META(dtHdr, metaVersion);
+    //dtHdr->rssi = 0;
+
+    return (A_OK);
+}
+
+
+A_UINT8 wmi_implicit_create_pstream(struct wmi_t *wmip, void *osbuf, A_UINT32 layer2Priority, A_BOOL wmmEnabled)
+{
+    A_UINT8         *datap;
+    A_UINT8         trafficClass = WMM_AC_BE;
+    A_UINT16        ipType = IP_ETHERTYPE;
+    WMI_DATA_HDR    *dtHdr;
+    A_BOOL           streamExists = FALSE;
+    A_UINT8        userPriority;
+    A_UINT32            hdrsize, metasize;
+    ATH_LLC_SNAP_HDR    *llcHdr;
+
+    WMI_CREATE_PSTREAM_CMD  cmd;
+
+    A_ASSERT(osbuf != NULL);
+
+    //
+    // Initialize header size
+    //
+    hdrsize = 0;
+
+    datap = A_NETBUF_DATA(osbuf);
+    dtHdr = (WMI_DATA_HDR *)datap;
+    metasize = (WMI_DATA_HDR_GET_META(dtHdr))? WMI_MAX_TX_META_SZ : 0;
+
+    if (!wmmEnabled)
+    {
+            /* If WMM is disabled all traffic goes as BE traffic */
+        userPriority = 0;
+    }
+    else
+    {
+        if (processDot11Hdr)
+        {
+             hdrsize = A_ROUND_UP(sizeof(struct ieee80211_qosframe),sizeof(A_UINT32));
+             llcHdr = (ATH_LLC_SNAP_HDR *)(datap + sizeof(WMI_DATA_HDR) + metasize +
+                          hdrsize);
+
+
+        }
+        else
+        {
+            llcHdr = (ATH_LLC_SNAP_HDR *)(datap + sizeof(WMI_DATA_HDR) + metasize +
+                          sizeof(ATH_MAC_HDR));
+        }
+
+        if (llcHdr->etherType == A_CPU2BE16(ipType))
+        {
+            /* Extract the endpoint info from the TOS field in the IP header */
+
+            userPriority = wmi_determine_userPriority (((A_UINT8 *)llcHdr) + sizeof(ATH_LLC_SNAP_HDR),layer2Priority);
+        }
+        else
+        {
+            userPriority = layer2Priority & 0x7;
+        }
+    }
+
+
+    /* workaround for WMM S5 */
+    if ((WMM_AC_VI == wmip->wmi_traffic_class) && ((5 == userPriority) || (4 == userPriority)))
+    {
+        userPriority = 1;
+    }
+
+    trafficClass = convert_userPriority_to_trafficClass(userPriority);
+
+    WMI_DATA_HDR_SET_UP(dtHdr, userPriority);
+    /* lower 3-bits are 802.1d priority */
+    //dtHdr->info |= (userPriority & WMI_DATA_HDR_UP_MASK) << WMI_DATA_HDR_UP_SHIFT;
+
+    LOCK_WMI(wmip);
+    streamExists = wmip->wmi_fatPipeExists;
+    UNLOCK_WMI(wmip);
+
+    if (!(streamExists & (1 << trafficClass)))
+    {
+
+        A_MEMZERO(&cmd, sizeof(cmd));
+        cmd.trafficClass = trafficClass;
+        cmd.userPriority = userPriority;
+        cmd.inactivityInt = WMI_IMPLICIT_PSTREAM_INACTIVITY_INT;
+            /* Implicit streams are created with TSID 0xFF */
+
+        cmd.tsid = WMI_IMPLICIT_PSTREAM;
+        wmi_create_pstream_cmd(wmip, &cmd);
+    }
+
+    return trafficClass;
+}
+
+A_STATUS
+wmi_dot11_hdr_add (struct wmi_t *wmip, void *osbuf, NETWORK_TYPE mode)
+{
+    A_UINT8          *datap;
+    A_UINT16         typeorlen;
+    ATH_MAC_HDR      macHdr;
+    ATH_LLC_SNAP_HDR *llcHdr;
+    struct           ieee80211_frame *wh;
+    A_UINT32         hdrsize;
+
+    A_ASSERT(osbuf != NULL);
+
+    if (A_NETBUF_HEADROOM(osbuf) <
+        (sizeof(struct ieee80211_qosframe) +  sizeof(ATH_LLC_SNAP_HDR) + sizeof(WMI_DATA_HDR)))
+    {
+        return A_NO_MEMORY;
+    }
+
+    datap = A_NETBUF_DATA(osbuf);
+
+    typeorlen = *(A_UINT16 *)(datap + ATH_MAC_LEN + ATH_MAC_LEN);
+
+    if (!IS_ETHERTYPE(A_BE2CPU16(typeorlen))) {
+/*
+         * packet is already in 802.3 format - return success
+         */
+        A_DPRINTF(DBG_WMI, (DBGFMT "packet already 802.3\n", DBGARG));
+        goto AddDot11Hdr;
+    }
+
+    /*
+     * Save mac fields and length to be inserted later
+     */
+    A_MEMCPY(macHdr.dstMac, datap, ATH_MAC_LEN);
+    A_MEMCPY(macHdr.srcMac, datap + ATH_MAC_LEN, ATH_MAC_LEN);
+    macHdr.typeOrLen = A_CPU2BE16(A_NETBUF_LEN(osbuf) - sizeof(ATH_MAC_HDR) +
+                                  sizeof(ATH_LLC_SNAP_HDR));
+
+    // Remove the Ethernet hdr
+    A_NETBUF_PULL(osbuf, sizeof(ATH_MAC_HDR));
+    /*
+     * Make room for LLC+SNAP headers
+     */
+    if (A_NETBUF_PUSH(osbuf, sizeof(ATH_LLC_SNAP_HDR)) != A_OK) {
+        return A_NO_MEMORY;
+    }
+    datap = A_NETBUF_DATA(osbuf);
+
+    llcHdr = (ATH_LLC_SNAP_HDR *)(datap);
+    llcHdr->dsap       = 0xAA;
+    llcHdr->ssap       = 0xAA;
+    llcHdr->cntl       = 0x03;
+    llcHdr->orgCode[0] = 0x0;
+    llcHdr->orgCode[1] = 0x0;
+    llcHdr->orgCode[2] = 0x0;
+    llcHdr->etherType  = typeorlen;
+
+AddDot11Hdr:
+    /* Make room for 802.11 hdr */
+    if (wmip->wmi_is_wmm_enabled)
+    {
+        hdrsize = A_ROUND_UP(sizeof(struct ieee80211_qosframe),sizeof(A_UINT32));
+        if (A_NETBUF_PUSH(osbuf, hdrsize) != A_OK)
+        {
+            return A_NO_MEMORY;
+        }
+        wh = (struct ieee80211_frame *) A_NETBUF_DATA(osbuf);
+        wh->i_fc[0] = IEEE80211_FC0_SUBTYPE_QOS;
+    }
+    else
+    {
+        hdrsize = A_ROUND_UP(sizeof(struct ieee80211_frame),sizeof(A_UINT32));
+        if (A_NETBUF_PUSH(osbuf, hdrsize) != A_OK)
+        {
+            return A_NO_MEMORY;
+        }
+        wh = (struct ieee80211_frame *) A_NETBUF_DATA(osbuf);
+        wh->i_fc[0] = IEEE80211_FC0_SUBTYPE_DATA;
+    }
+    /* Setup the SA & DA */
+    IEEE80211_ADDR_COPY(wh->i_addr2, macHdr.srcMac);
+
+    if (mode == INFRA_NETWORK) {
+        IEEE80211_ADDR_COPY(wh->i_addr3, macHdr.dstMac);
+    }
+    else if (mode == ADHOC_NETWORK) {
+        IEEE80211_ADDR_COPY(wh->i_addr1, macHdr.dstMac);
+    }
+
+    return (A_OK);
+}
+
+A_STATUS
+wmi_dot11_hdr_remove(struct wmi_t *wmip, void *osbuf)
+{
+    A_UINT8          *datap;
+    struct           ieee80211_frame *pwh,wh;
+    A_UINT8          type,subtype;
+    ATH_LLC_SNAP_HDR *llcHdr;
+    ATH_MAC_HDR      macHdr;
+    A_UINT32         hdrsize;
+
+    A_ASSERT(osbuf != NULL);
+    datap = A_NETBUF_DATA(osbuf);
+
+    pwh = (struct ieee80211_frame *)datap;
+    type = pwh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
+    subtype = pwh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK;
+
+    A_MEMCPY((A_UINT8 *)&wh, datap, sizeof(struct ieee80211_frame));
+
+    /* strip off the 802.11 hdr*/
+    if (subtype == IEEE80211_FC0_SUBTYPE_QOS) {
+        hdrsize = A_ROUND_UP(sizeof(struct ieee80211_qosframe),sizeof(A_UINT32));
+        A_NETBUF_PULL(osbuf, hdrsize);
+    } else if (subtype == IEEE80211_FC0_SUBTYPE_DATA) {
+        A_NETBUF_PULL(osbuf, sizeof(struct ieee80211_frame));
+    }
+
+    datap = A_NETBUF_DATA(osbuf);
+    llcHdr = (ATH_LLC_SNAP_HDR *)(datap);
+
+    macHdr.typeOrLen = llcHdr->etherType;
+    A_MEMZERO(macHdr.dstMac, sizeof(macHdr.dstMac));
+    A_MEMZERO(macHdr.srcMac, sizeof(macHdr.srcMac));
+
+    switch (wh.i_fc[1] & IEEE80211_FC1_DIR_MASK) {
+    case IEEE80211_FC1_DIR_NODS:
+        IEEE80211_ADDR_COPY(macHdr.dstMac, wh.i_addr1);
+        IEEE80211_ADDR_COPY(macHdr.srcMac, wh.i_addr2);
+        break;
+    case IEEE80211_FC1_DIR_TODS:
+        IEEE80211_ADDR_COPY(macHdr.dstMac, wh.i_addr3);
+        IEEE80211_ADDR_COPY(macHdr.srcMac, wh.i_addr2);
+        break;
+    case IEEE80211_FC1_DIR_FROMDS:
+        IEEE80211_ADDR_COPY(macHdr.dstMac, wh.i_addr1);
+        IEEE80211_ADDR_COPY(macHdr.srcMac, wh.i_addr3);
+        break;
+    case IEEE80211_FC1_DIR_DSTODS:
+        break;
+    }
+
+    // Remove the LLC Hdr.
+    A_NETBUF_PULL(osbuf, sizeof(ATH_LLC_SNAP_HDR));
+
+    // Insert the ATH MAC hdr.
+
+    A_NETBUF_PUSH(osbuf, sizeof(ATH_MAC_HDR));
+    datap = A_NETBUF_DATA(osbuf);
+
+    A_MEMCPY (datap, &macHdr, sizeof(ATH_MAC_HDR));
+
+    return A_OK;
+}
+
+/*
+ *  performs 802.3 to DIX encapsulation for received packets.
+ *  Assumes the entire 802.3 header is contigous.
+ */
+A_STATUS
+wmi_dot3_2_dix(void *osbuf)
+{
+    A_UINT8          *datap;
+    ATH_MAC_HDR      macHdr;
+    ATH_LLC_SNAP_HDR *llcHdr;
+
+    A_ASSERT(osbuf != NULL);
+    datap = A_NETBUF_DATA(osbuf);
+
+    A_MEMCPY(&macHdr, datap, sizeof(ATH_MAC_HDR));
+    llcHdr = (ATH_LLC_SNAP_HDR *)(datap + sizeof(ATH_MAC_HDR));
+    macHdr.typeOrLen = llcHdr->etherType;
+
+    if (A_NETBUF_PULL(osbuf, sizeof(ATH_LLC_SNAP_HDR)) != A_OK) {
+        return A_NO_MEMORY;
+    }
+
+    datap = A_NETBUF_DATA(osbuf);
+
+    A_MEMCPY(datap, &macHdr, sizeof (ATH_MAC_HDR));
+
+    return (A_OK);
+}
+
+/*
+ * Removes a WMI data header
+ */
+A_STATUS
+wmi_data_hdr_remove(struct wmi_t *wmip, void *osbuf)
+{
+    A_ASSERT(osbuf != NULL);
+
+    return (A_NETBUF_PULL(osbuf, sizeof(WMI_DATA_HDR)));
+}
+
+void
+wmi_iterate_nodes(struct wmi_t *wmip, wlan_node_iter_func *f, void *arg)
+{
+    wlan_iterate_nodes(&wmip->wmi_scan_table, f, arg);
+}
+
+/*
+ * WMI Extended Event received from Target.
+ */
+A_STATUS
+wmi_control_rx_xtnd(struct wmi_t *wmip, void *osbuf)
+{
+    WMIX_CMD_HDR *cmd;
+    A_UINT16 id;
+    A_UINT8 *datap;
+    A_UINT32 len;
+    A_STATUS status = A_OK;
+
+    if (A_NETBUF_LEN(osbuf) < sizeof(WMIX_CMD_HDR)) {
+        A_DPRINTF(DBG_WMI, (DBGFMT "bad packet 1\n", DBGARG));
+        wmip->wmi_stats.cmd_len_err++;
+        return A_ERROR;
+    }
+
+    cmd = (WMIX_CMD_HDR *)A_NETBUF_DATA(osbuf);
+    id = cmd->commandId;
+
+    if (A_NETBUF_PULL(osbuf, sizeof(WMIX_CMD_HDR)) != A_OK) {
+        A_DPRINTF(DBG_WMI, (DBGFMT "bad packet 2\n", DBGARG));
+        wmip->wmi_stats.cmd_len_err++;
+        return A_ERROR;
+    }
+
+    datap = A_NETBUF_DATA(osbuf);
+    len = A_NETBUF_LEN(osbuf);
+
+    switch (id) {
+    case (WMIX_DSETOPENREQ_EVENTID):
+        status = wmi_dset_open_req_rx(wmip, datap, len);
+        break;
+#ifdef CONFIG_HOST_DSET_SUPPORT
+    case (WMIX_DSETCLOSE_EVENTID):
+        status = wmi_dset_close_rx(wmip, datap, len);
+        break;
+    case (WMIX_DSETDATAREQ_EVENTID):
+        status = wmi_dset_data_req_rx(wmip, datap, len);
+        break;
+#endif /* CONFIG_HOST_DSET_SUPPORT */
+#ifdef CONFIG_HOST_GPIO_SUPPORT
+    case (WMIX_GPIO_INTR_EVENTID):
+        wmi_gpio_intr_rx(wmip, datap, len);
+        break;
+    case (WMIX_GPIO_DATA_EVENTID):
+        wmi_gpio_data_rx(wmip, datap, len);
+        break;
+    case (WMIX_GPIO_ACK_EVENTID):
+        wmi_gpio_ack_rx(wmip, datap, len);
+        break;
+#endif /* CONFIG_HOST_GPIO_SUPPORT */
+    case (WMIX_HB_CHALLENGE_RESP_EVENTID):
+        wmi_hbChallengeResp_rx(wmip, datap, len);
+        break;
+    case (WMIX_DBGLOG_EVENTID):
+        wmi_dbglog_event_rx(wmip, datap, len);
+        break;
+#if defined(CONFIG_TARGET_PROFILE_SUPPORT)
+    case (WMIX_PROF_COUNT_EVENTID):
+        wmi_prof_count_rx(wmip, datap, len);
+        break;
+#endif /* CONFIG_TARGET_PROFILE_SUPPORT */
+    default:
+        A_DPRINTF(DBG_WMI|DBG_ERROR,
+            (DBGFMT "Unknown id 0x%x\n", DBGARG, id));
+        wmip->wmi_stats.cmd_id_err++;
+        status = A_ERROR;
+        break;
+    }
+
+    return status;
+}
+
+/*
+ * Control Path
+ */
+A_UINT32 cmdRecvNum;
+
+A_STATUS
+wmi_control_rx(struct wmi_t *wmip, void *osbuf)
+{
+    WMI_CMD_HDR *cmd;
+    A_UINT16 id;
+    A_UINT8 *datap;
+    A_UINT32 len, i, loggingReq;
+    A_STATUS status = A_OK;
+
+    A_ASSERT(osbuf != NULL);
+    if (A_NETBUF_LEN(osbuf) < sizeof(WMI_CMD_HDR)) {
+        A_NETBUF_FREE(osbuf);
+        A_DPRINTF(DBG_WMI, (DBGFMT "bad packet 1\n", DBGARG));
+        wmip->wmi_stats.cmd_len_err++;
+        return A_ERROR;
+    }
+
+    cmd = (WMI_CMD_HDR *)A_NETBUF_DATA(osbuf);
+    id = cmd->commandId;
+
+    if (A_NETBUF_PULL(osbuf, sizeof(WMI_CMD_HDR)) != A_OK) {
+        A_NETBUF_FREE(osbuf);
+        A_DPRINTF(DBG_WMI, (DBGFMT "bad packet 2\n", DBGARG));
+        wmip->wmi_stats.cmd_len_err++;
+        return A_ERROR;
+    }
+
+    datap = A_NETBUF_DATA(osbuf);
+    len = A_NETBUF_LEN(osbuf);
+
+    loggingReq = 0;
+
+    ar6000_get_driver_cfg(wmip->wmi_devt,
+                    AR6000_DRIVER_CFG_LOG_RAW_WMI_MSGS,
+                    &loggingReq);
+
+    if(loggingReq) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("WMI %d \n",id));
+        AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("WMI recv, MsgNo %d : ", cmdRecvNum));
+        for(i = 0; i < len; i++)
+            AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("%x ", datap[i]));
+        AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("\n"));
+    }
+
+    LOCK_WMI(wmip);
+    cmdRecvNum++;
+    UNLOCK_WMI(wmip);
+
+    switch (id) {
+    case (WMI_GET_BITRATE_CMDID):
+        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_GET_BITRATE_CMDID\n", DBGARG));
+        status = wmi_bitrate_reply_rx(wmip, datap, len);
+        break;
+    case (WMI_GET_CHANNEL_LIST_CMDID):
+        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_GET_CHANNEL_LIST_CMDID\n", DBGARG));
+        status = wmi_channelList_reply_rx(wmip, datap, len);
+        break;
+    case (WMI_GET_TX_PWR_CMDID):
+        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_GET_TX_PWR_CMDID\n", DBGARG));
+        status = wmi_txPwr_reply_rx(wmip, datap, len);
+        break;
+    case (WMI_READY_EVENTID):
+        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_READY_EVENTID\n", DBGARG));
+        status = wmi_ready_event_rx(wmip, datap, len);
+        A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len);
+        A_WMI_DBGLOG_INIT_DONE(wmip->wmi_devt);
+        break;
+    case (WMI_CONNECT_EVENTID):
+        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_CONNECT_EVENTID\n", DBGARG));
+        status = wmi_connect_event_rx(wmip, datap, len);
+        A_WMI_SEND_GENERIC_EVENT_TO_APP(wmip->wmi_devt, id, datap, len);
+        break;
+    case (WMI_DISCONNECT_EVENTID):
+        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_DISCONNECT_EVENTID\n", DBGARG));
+        status = wmi_disconnect_event_rx(wmip, datap, len);
+        A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len);
+        break;
+    case (WMI_PEER_NODE_EVENTID):
+        A_DPRINTF (DBG_WMI, (DBGFMT "WMI_PEER_NODE_EVENTID\n", DBGARG));
+        status = wmi_peer_node_event_rx(wmip, datap, len);
+        A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len);
+        break;
+    case (WMI_TKIP_MICERR_EVENTID):
+        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_TKIP_MICERR_EVENTID\n", DBGARG));
+        status = wmi_tkip_micerr_event_rx(wmip, datap, len);
+        break;
+    case (WMI_BSSINFO_EVENTID):
+        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_BSSINFO_EVENTID\n", DBGARG));
+        {
+            /*
+             * convert WMI_BSS_INFO_HDR2 to WMI_BSS_INFO_HDR
+             * Take a local copy of the WMI_BSS_INFO_HDR2 from the wmi buffer
+             * and reconstruct the WMI_BSS_INFO_HDR in its place
+            */
+            WMI_BSS_INFO_HDR2 bih2;
+            WMI_BSS_INFO_HDR *bih;
+            A_MEMCPY(&bih2, datap, sizeof(WMI_BSS_INFO_HDR2));
+
+            A_NETBUF_PUSH(osbuf, 4);
+            datap = A_NETBUF_DATA(osbuf);
+            len = A_NETBUF_LEN(osbuf);
+            bih = (WMI_BSS_INFO_HDR *)datap;
+
+            bih->channel = bih2.channel;
+            bih->frameType = bih2.frameType;
+            bih->snr = bih2.snr;
+            bih->rssi = bih2.snr - 95;
+            bih->ieMask = bih2.ieMask;
+            A_MEMCPY(bih->bssid, bih2.bssid, ATH_MAC_LEN);
+
+            status = wmi_bssInfo_event_rx(wmip, datap, len);
+            A_WMI_SEND_GENERIC_EVENT_TO_APP(wmip->wmi_devt, id, datap, len);
+        }
+        break;
+    case (WMI_REGDOMAIN_EVENTID):
+        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_REGDOMAIN_EVENTID\n", DBGARG));
+        status = wmi_regDomain_event_rx(wmip, datap, len);
+        break;
+    case (WMI_PSTREAM_TIMEOUT_EVENTID):
+        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_PSTREAM_TIMEOUT_EVENTID\n", DBGARG));
+        status = wmi_pstream_timeout_event_rx(wmip, datap, len);
+            /* pstreams are fatpipe abstractions that get implicitly created.
+             * User apps only deal with thinstreams. creation of a thinstream
+             * by the user or data traffic flow in an AC triggers implicit
+             * pstream creation. Do we need to send this event to App..?
+             * no harm in sending it.
+             */
+        A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len);
+        break;
+    case (WMI_NEIGHBOR_REPORT_EVENTID):
+        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_NEIGHBOR_REPORT_EVENTID\n", DBGARG));
+        status = wmi_neighborReport_event_rx(wmip, datap, len);
+        break;
+    case (WMI_SCAN_COMPLETE_EVENTID):
+        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_SCAN_COMPLETE_EVENTID\n", DBGARG));
+        status = wmi_scanComplete_rx(wmip, datap, len);
+        A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len);
+        break;
+    case (WMI_CMDERROR_EVENTID):
+        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_CMDERROR_EVENTID\n", DBGARG));
+        status = wmi_errorEvent_rx(wmip, datap, len);
+        break;
+    case (WMI_REPORT_STATISTICS_EVENTID):
+        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_REPORT_STATISTICS_EVENTID\n", DBGARG));
+        status = wmi_statsEvent_rx(wmip, datap, len);
+        break;
+    case (WMI_RSSI_THRESHOLD_EVENTID):
+        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_RSSI_THRESHOLD_EVENTID\n", DBGARG));
+        status = wmi_rssiThresholdEvent_rx(wmip, datap, len);
+        break;
+    case (WMI_ERROR_REPORT_EVENTID):
+        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_ERROR_REPORT_EVENTID\n", DBGARG));
+        status = wmi_reportErrorEvent_rx(wmip, datap, len);
+        A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len);
+        break;
+    case (WMI_OPT_RX_FRAME_EVENTID):
+        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_OPT_RX_FRAME_EVENTID\n", DBGARG));
+        status = wmi_opt_frame_event_rx(wmip, datap, len);
+        break;
+    case (WMI_REPORT_ROAM_TBL_EVENTID):
+        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_REPORT_ROAM_TBL_EVENTID\n", DBGARG));
+        status = wmi_roam_tbl_event_rx(wmip, datap, len);
+        break;
+    case (WMI_EXTENSION_EVENTID):
+        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_EXTENSION_EVENTID\n", DBGARG));
+        status = wmi_control_rx_xtnd(wmip, osbuf);
+        break;
+    case (WMI_CAC_EVENTID):
+        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_CAC_EVENTID\n", DBGARG));
+        status = wmi_cac_event_rx(wmip, datap, len);
+        break;
+    case (WMI_CHANNEL_CHANGE_EVENTID):
+        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_CHANNEL_CHANGE_EVENTID\n", DBGARG));
+        status = wmi_channel_change_event_rx(wmip, datap, len);
+        break;
+    case (WMI_REPORT_ROAM_DATA_EVENTID):
+        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_REPORT_ROAM_DATA_EVENTID\n", DBGARG));
+        status = wmi_roam_data_event_rx(wmip, datap, len);
+        break;
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+    case (WMI_TEST_EVENTID):
+        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_TEST_EVENTID\n", DBGARG));
+        status = wmi_tcmd_test_report_rx(wmip, datap, len);
+        break;
+#endif
+    case (WMI_GET_FIXRATES_CMDID):
+        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_GET_FIXRATES_CMDID\n", DBGARG));
+        status = wmi_ratemask_reply_rx(wmip, datap, len);
+        break;
+    case (WMI_TX_RETRY_ERR_EVENTID):
+        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_TX_RETRY_ERR_EVENTID\n", DBGARG));
+        status = wmi_txRetryErrEvent_rx(wmip, datap, len);
+        A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len);
+        break;
+    case (WMI_SNR_THRESHOLD_EVENTID):
+        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_SNR_THRESHOLD_EVENTID\n", DBGARG));
+        status = wmi_snrThresholdEvent_rx(wmip, datap, len);
+        break;
+    case (WMI_LQ_THRESHOLD_EVENTID):
+        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_LQ_THRESHOLD_EVENTID\n", DBGARG));
+        status = wmi_lqThresholdEvent_rx(wmip, datap, len);
+        A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len);
+        break;
+    case (WMI_APLIST_EVENTID):
+        AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("Received APLIST Event\n"));
+        status = wmi_aplistEvent_rx(wmip, datap, len);
+        break;
+    case (WMI_GET_KEEPALIVE_CMDID):
+        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_GET_KEEPALIVE_CMDID\n", DBGARG));
+        status = wmi_keepalive_reply_rx(wmip, datap, len);
+        break;
+    case (WMI_GET_WOW_LIST_EVENTID):
+        status = wmi_get_wow_list_event_rx(wmip, datap, len);
+        break;
+    case (WMI_GET_PMKID_LIST_EVENTID):
+        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_GET_PMKID_LIST Event\n", DBGARG));
+        status = wmi_get_pmkid_list_event_rx(wmip, datap, len);
+        break;
+    case (WMI_PSPOLL_EVENTID):
+        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_PSPOLL_EVENT\n", DBGARG));
+        status = wmi_pspoll_event_rx(wmip, datap, len);
+        break;
+    case (WMI_DTIMEXPIRY_EVENTID):
+        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_DTIMEXPIRY_EVENT\n", DBGARG));
+        status = wmi_dtimexpiry_event_rx(wmip, datap, len);
+        break;
+    case (WMI_SET_PARAMS_REPLY_EVENTID):
+        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_SET_PARAMS_REPLY Event\n", DBGARG));
+        status = wmi_set_params_event_rx(wmip, datap, len);
+        break;
+    case (WMI_ACM_REJECT_EVENTID):
+        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_SET_PARAMS_REPLY Event\n", DBGARG));
+        status = wmi_acm_reject_event_rx(wmip, datap, len);
+        break;		
+#ifdef ATH_AR6K_11N_SUPPORT
+    case (WMI_ADDBA_REQ_EVENTID):
+        status = wmi_addba_req_event_rx(wmip, datap, len);
+        break;
+    case (WMI_ADDBA_RESP_EVENTID):
+        status = wmi_addba_resp_event_rx(wmip, datap, len);
+        break;
+    case (WMI_DELBA_REQ_EVENTID):
+        status = wmi_delba_req_event_rx(wmip, datap, len);
+        break;
+	case (WMI_REPORT_BTCOEX_CONFIG_EVENTID):
+	    A_DPRINTF(DBG_WMI, (DBGFMT "WMI_BTCOEX_CONFIG_EVENTID", DBGARG));
+    	status = wmi_btcoex_config_event_rx(wmip, datap, len);
+	    break;
+	case (WMI_REPORT_BTCOEX_STATS_EVENTID):
+	    A_DPRINTF(DBG_WMI, (DBGFMT "WMI_BTCOEX_STATS_EVENTID", DBGARG));
+    	status = wmi_btcoex_stats_event_rx(wmip, datap, len);
+	    break;
+#endif
+    case (WMI_TX_COMPLETE_EVENTID):
+        {
+            int index;
+            TX_COMPLETE_MSG_V1 *pV1;
+            WMI_TX_COMPLETE_EVENT *pEv = (WMI_TX_COMPLETE_EVENT *)datap;
+            A_PRINTF("comp: %d %d %d\n", pEv->numMessages, pEv->msgLen, pEv->msgType);
+
+            for(index = 0 ; index < pEv->numMessages ; index++) {
+                pV1 = (TX_COMPLETE_MSG_V1 *)(datap + sizeof(WMI_TX_COMPLETE_EVENT) + index*sizeof(TX_COMPLETE_MSG_V1));
+                A_PRINTF("msg: %d %d %d %d\n", pV1->status, pV1->pktID, pV1->rateIdx, pV1->ackFailures);
+            }
+        }
+        break;
+    case (WMI_HCI_EVENT_EVENTID):
+        status = wmi_hci_event_rx(wmip, datap, len);
+        break;
+#ifdef WAPI_ENABLE
+    case (WMI_WAPI_REKEY_EVENTID):
+        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_WAPI_REKEY_EVENTID", DBGARG));
+        status = wmi_wapi_rekey_event_rx(wmip, datap, len);
+        break;
+#endif
+    default:
+        A_DPRINTF(DBG_WMI|DBG_ERROR,
+            (DBGFMT "Unknown id 0x%x\n", DBGARG, id));
+        wmip->wmi_stats.cmd_id_err++;
+        status = A_ERROR;
+        break;
+    }
+
+    A_NETBUF_FREE(osbuf);
+
+    return status;
+}
+
+/* Send a "simple" wmi command -- one with no arguments */
+static A_STATUS
+wmi_simple_cmd(struct wmi_t *wmip, WMI_COMMAND_ID cmdid)
+{
+    void *osbuf;
+
+    osbuf = A_NETBUF_ALLOC(0);
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    return (wmi_cmd_send(wmip, osbuf, cmdid, NO_SYNC_WMIFLAG));
+}
+
+/* Send a "simple" extended wmi command -- one with no arguments.
+   Enabling this command only if GPIO or profiling support is enabled.
+   This is to suppress warnings on some platforms */
+#if defined(CONFIG_HOST_GPIO_SUPPORT) || defined(CONFIG_TARGET_PROFILE_SUPPORT)
+static A_STATUS
+wmi_simple_cmd_xtnd(struct wmi_t *wmip, WMIX_COMMAND_ID cmdid)
+{
+    void *osbuf;
+
+    osbuf = A_NETBUF_ALLOC(0);
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    return (wmi_cmd_send_xtnd(wmip, osbuf, cmdid, NO_SYNC_WMIFLAG));
+}
+#endif
+
+static A_STATUS
+wmi_ready_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMI_READY_EVENT *ev = (WMI_READY_EVENT *)datap;
+
+    if (len < sizeof(WMI_READY_EVENT)) {
+        return A_EINVAL;
+    }
+    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+    wmip->wmi_ready = TRUE;
+    A_WMI_READY_EVENT(wmip->wmi_devt, ev->macaddr, ev->phyCapability,
+                      ev->sw_version, ev->abi_version);
+
+    return A_OK;
+}
+
+#define LE_READ_4(p)                            \
+    ((A_UINT32)                            \
+     ((((A_UINT8 *)(p))[0]      ) | (((A_UINT8 *)(p))[1] <<  8) | \
+      (((A_UINT8 *)(p))[2] << 16) | (((A_UINT8 *)(p))[3] << 24)))
+
+static int __inline
+iswmmoui(const A_UINT8 *frm)
+{
+    return frm[1] > 3 && LE_READ_4(frm+2) == ((WMM_OUI_TYPE<<24)|WMM_OUI);
+}
+
+static int __inline
+iswmmparam(const A_UINT8 *frm)
+{
+    return frm[1] > 5 && frm[6] == WMM_PARAM_OUI_SUBTYPE;
+}
+
+
+static A_STATUS
+wmi_connect_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMI_CONNECT_EVENT *ev;
+    A_UINT8 *pie,*peie;
+
+    if (len < sizeof(WMI_CONNECT_EVENT))
+    {
+        return A_EINVAL;
+    }
+    ev = (WMI_CONNECT_EVENT *)datap;
+
+    A_DPRINTF(DBG_WMI,
+        (DBGFMT "freq %d bssid %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n",
+        DBGARG, ev->channel,
+        ev->bssid[0], ev->bssid[1], ev->bssid[2],
+        ev->bssid[3], ev->bssid[4], ev->bssid[5]));
+
+    A_MEMCPY(wmip->wmi_bssid, ev->bssid, ATH_MAC_LEN);
+
+    /* initialize pointer to start of assoc rsp IEs */
+    pie = ev->assocInfo + ev->beaconIeLen + ev->assocReqLen +
+                            sizeof(A_UINT16)  +  /* capinfo*/
+                            sizeof(A_UINT16)  +  /* status Code */
+                            sizeof(A_UINT16)  ;  /* associd */
+
+    /* initialize pointer to end of assoc rsp IEs */
+    peie = ev->assocInfo + ev->beaconIeLen + ev->assocReqLen + ev->assocRespLen;
+
+    while (pie < peie)
+    {
+        switch (*pie)
+        {
+            case IEEE80211_ELEMID_VENDOR:
+                if (iswmmoui(pie))
+                {
+                    if(iswmmparam (pie))
+                    {
+                        wmip->wmi_is_wmm_enabled = TRUE;
+                    }
+                }
+            break;
+        }
+
+        if (wmip->wmi_is_wmm_enabled)
+        {
+            break;
+        }
+        pie += pie[1] + 2;
+    }
+
+    A_WMI_CONNECT_EVENT(wmip->wmi_devt, ev->channel, ev->bssid,
+                         ev->listenInterval, ev->beaconInterval,
+                         (NETWORK_TYPE) ev->networkType, ev->beaconIeLen,
+                         ev->assocReqLen, ev->assocRespLen,
+                         ev->assocInfo);
+
+    return A_OK;
+}
+
+static A_STATUS
+wmi_regDomain_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMI_REG_DOMAIN_EVENT *ev;
+
+    if (len < sizeof(*ev)) {
+        return A_EINVAL;
+    }
+    ev = (WMI_REG_DOMAIN_EVENT *)datap;
+
+    A_WMI_REGDOMAIN_EVENT(wmip->wmi_devt, ev->regDomain);
+
+    return A_OK;
+}
+
+static A_STATUS
+wmi_neighborReport_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMI_NEIGHBOR_REPORT_EVENT *ev;
+    int numAps;
+
+    if (len < sizeof(*ev)) {
+        return A_EINVAL;
+    }
+    ev = (WMI_NEIGHBOR_REPORT_EVENT *)datap;
+    numAps = ev->numberOfAps;
+
+    if (len < (int)(sizeof(*ev) + ((numAps - 1) * sizeof(WMI_NEIGHBOR_INFO)))) {
+        return A_EINVAL;
+    }
+
+    A_WMI_NEIGHBORREPORT_EVENT(wmip->wmi_devt, numAps, ev->neighbor);
+
+    return A_OK;
+}
+
+static A_STATUS
+wmi_disconnect_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMI_DISCONNECT_EVENT *ev;
+    wmip->wmi_traffic_class = 100;
+
+    if (len < sizeof(WMI_DISCONNECT_EVENT)) {
+        return A_EINVAL;
+    }
+    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+    ev = (WMI_DISCONNECT_EVENT *)datap;
+
+    A_MEMZERO(wmip->wmi_bssid, sizeof(wmip->wmi_bssid));
+
+    wmip->wmi_is_wmm_enabled = FALSE;
+    wmip->wmi_pair_crypto_type = NONE_CRYPT;
+    wmip->wmi_grp_crypto_type = NONE_CRYPT;
+
+    A_WMI_DISCONNECT_EVENT(wmip->wmi_devt, ev->disconnectReason, ev->bssid,
+                            ev->assocRespLen, ev->assocInfo, ev->protocolReasonStatus);
+
+    return A_OK;
+}
+
+static A_STATUS
+wmi_peer_node_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMI_PEER_NODE_EVENT *ev;
+
+    if (len < sizeof(WMI_PEER_NODE_EVENT)) {
+        return A_EINVAL;
+    }
+    ev = (WMI_PEER_NODE_EVENT *)datap;
+    if (ev->eventCode == PEER_NODE_JOIN_EVENT) {
+        A_DPRINTF (DBG_WMI, (DBGFMT "Joined node with Macaddr: ", DBGARG));
+    } else if(ev->eventCode == PEER_NODE_LEAVE_EVENT) {
+        A_DPRINTF (DBG_WMI, (DBGFMT "left node with Macaddr: ", DBGARG));
+    }
+
+    A_WMI_PEER_EVENT (wmip->wmi_devt, ev->eventCode, ev->peerMacAddr);
+
+    return A_OK;
+}
+
+static A_STATUS
+wmi_tkip_micerr_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMI_TKIP_MICERR_EVENT *ev;
+
+    if (len < sizeof(*ev)) {
+        return A_EINVAL;
+    }
+    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+    ev = (WMI_TKIP_MICERR_EVENT *)datap;
+    A_WMI_TKIP_MICERR_EVENT(wmip->wmi_devt, ev->keyid, ev->ismcast);
+
+    return A_OK;
+}
+
+static A_STATUS
+wmi_bssInfo_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    bss_t *bss = NULL;
+    WMI_BSS_INFO_HDR *bih;
+    A_UINT8 *buf;
+    A_UINT32 nodeCachingAllowed = 1;
+    A_UCHAR cached_ssid_len = 0;
+    A_UCHAR cached_ssid_buf[IEEE80211_NWID_LEN] = {0};
+    A_UINT8 beacon_ssid_len = 0;
+
+    if (len <= sizeof(WMI_BSS_INFO_HDR)) {
+        return A_EINVAL;
+    }
+
+    bih = (WMI_BSS_INFO_HDR *)datap;
+    bss = wlan_find_node(&wmip->wmi_scan_table, bih->bssid);
+
+    if (bih->rssi > 0) {
+        if (NULL == bss)
+            return A_OK;  //no node found in the table, just drop the node with incorrect RSSI
+        else
+            bih->rssi = bss->ni_rssi; //Adjust RSSI in datap in case it is used in A_WMI_BSSINFO_EVENT_RX
+    }
+
+    A_WMI_BSSINFO_EVENT_RX(wmip->wmi_devt, datap, len);
+    /* What is driver config for wlan node caching? */
+    if(ar6000_get_driver_cfg(wmip->wmi_devt,
+                    AR6000_DRIVER_CFG_GET_WLANNODECACHING,
+                    &nodeCachingAllowed) != A_OK) {
+        wmi_node_return(wmip, bss);
+        return A_EINVAL;
+    }
+
+    if(!nodeCachingAllowed) {
+        wmi_node_return(wmip, bss);
+        return A_OK;
+    }
+
+    buf = datap + sizeof(WMI_BSS_INFO_HDR);
+    len -= sizeof(WMI_BSS_INFO_HDR);
+
+	A_DPRINTF(DBG_WMI2, (DBGFMT "bssInfo event - ch %u, rssi %02x, "
+		"bssid \"%pM\"\n", DBGARG, bih->channel,
+		(unsigned char) bih->rssi, bih->bssid));
+
+    if(wps_enable && (bih->frameType == PROBERESP_FTYPE) ) {
+        wmi_node_return(wmip, bss);
+        return A_OK;
+    }
+
+    if (bss != NULL) {
+        /*
+         * Free up the node.  Not the most efficient process given
+         * we are about to allocate a new node but it is simple and should be
+         * adequate.
+         */
+
+        /* In case of hidden AP, beacon will not have ssid,
+         * but a directed probe response will have it,
+         * so cache the probe-resp-ssid if already present. */
+        if ((TRUE == is_probe_ssid) && (BEACON_FTYPE == bih->frameType))
+        {
+            A_UCHAR *ie_ssid;
+
+            ie_ssid = bss->ni_cie.ie_ssid;
+            if(ie_ssid && (ie_ssid[1] <= IEEE80211_NWID_LEN) && (ie_ssid[2] != 0))
+            {
+                cached_ssid_len = ie_ssid[1];
+                memcpy(cached_ssid_buf, ie_ssid + 2, cached_ssid_len);
+            }
+        }
+
+        /*
+         * Use the current average rssi of associated AP base on assumpiton
+         * 1. Most os with GUI will update RSSI by wmi_get_stats_cmd() periodically
+         * 2. wmi_get_stats_cmd(..) will be called when calling wmi_startscan_cmd(...)
+         * The average value of RSSI give end-user better feeling for instance value of scan result
+         * It also sync up RSSI info in GUI between scan result and RSSI signal icon
+         */
+        if (IEEE80211_ADDR_EQ(wmip->wmi_bssid, bih->bssid)) {
+            bih->rssi = bss->ni_rssi;
+            bih->snr  = bss->ni_snr;
+        }
+
+        wlan_node_reclaim(&wmip->wmi_scan_table, bss);
+    }
+
+    /*  beacon/probe response frame format
+     *  [8] time stamp
+     *  [2] beacon interval
+     *  [2] capability information
+     *  [tlv] ssid */
+    beacon_ssid_len = buf[SSID_IE_LEN_INDEX];
+
+    /* If ssid is cached for this hidden AP, then change buffer len accordingly. */
+    if ((TRUE == is_probe_ssid) && (BEACON_FTYPE == bih->frameType) &&
+        (0 != cached_ssid_len) &&
+        (0 == beacon_ssid_len || (cached_ssid_len > beacon_ssid_len && 0 == buf[SSID_IE_LEN_INDEX + 1])))
+    {
+        len += (cached_ssid_len - beacon_ssid_len);
+    }
+
+    bss = wlan_node_alloc(&wmip->wmi_scan_table, len);
+    if (bss == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    bss->ni_snr        = bih->snr;
+    bss->ni_rssi       = bih->rssi;
+    A_ASSERT(bss->ni_buf != NULL);
+
+    /* In case of hidden AP, beacon will not have ssid,
+     * but a directed probe response will have it,
+     * so place the cached-ssid(probe-resp) in the bssinfo. */
+    if ((TRUE == is_probe_ssid) && (BEACON_FTYPE == bih->frameType) &&
+         (0 != cached_ssid_len) &&
+         (0 == beacon_ssid_len || (beacon_ssid_len && 0 == buf[SSID_IE_LEN_INDEX + 1])))
+    {
+        A_UINT8 *ni_buf = bss->ni_buf;
+        int buf_len = len;
+
+        /* copy the first 14 bytes such as
+         * time-stamp(8), beacon-interval(2), cap-info(2), ssid-id(1), ssid-len(1). */
+        A_MEMCPY(ni_buf, buf, SSID_IE_LEN_INDEX + 1);
+
+        ni_buf[SSID_IE_LEN_INDEX] = cached_ssid_len;
+        ni_buf += (SSID_IE_LEN_INDEX + 1);
+
+        buf += (SSID_IE_LEN_INDEX + 1);
+        buf_len -= (SSID_IE_LEN_INDEX + 1);
+
+        /* copy the cached ssid */
+        A_MEMCPY(ni_buf, cached_ssid_buf, cached_ssid_len);
+        ni_buf += cached_ssid_len;
+
+        buf += beacon_ssid_len;
+        buf_len -= beacon_ssid_len;
+
+        if (cached_ssid_len > beacon_ssid_len)
+            buf_len -= (cached_ssid_len - beacon_ssid_len);
+
+        /* now copy the rest of bytes */
+        A_MEMCPY(ni_buf, buf, buf_len);
+    }
+    else
+        A_MEMCPY(bss->ni_buf, buf, len);
+
+    bss->ni_framelen = len;
+    if (wlan_parse_beacon(bss->ni_buf, len, &bss->ni_cie) != A_OK) {
+        wlan_node_free(bss);
+        return A_EINVAL;
+    }
+
+    /*
+     * Update the frequency in ie_chan, overwriting of channel number
+     * which is done in wlan_parse_beacon
+     */
+    bss->ni_cie.ie_chan = bih->channel;
+    wlan_setup_node(&wmip->wmi_scan_table, bss, bih->bssid);
+
+    return A_OK;
+}
+
+static A_STATUS
+wmi_opt_frame_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    bss_t *bss;
+    WMI_OPT_RX_INFO_HDR *bih;
+    A_UINT8 *buf;
+
+    if (len <= sizeof(WMI_OPT_RX_INFO_HDR)) {
+        return A_EINVAL;
+    }
+
+    bih = (WMI_OPT_RX_INFO_HDR *)datap;
+    buf = datap + sizeof(WMI_OPT_RX_INFO_HDR);
+    len -= sizeof(WMI_OPT_RX_INFO_HDR);
+
+    A_DPRINTF(DBG_WMI2, (DBGFMT "opt frame event %2.2x:%2.2x\n", DBGARG,
+        bih->bssid[4], bih->bssid[5]));
+
+    bss = wlan_find_node(&wmip->wmi_scan_table, bih->bssid);
+    if (bss != NULL) {
+        /*
+         * Free up the node.  Not the most efficient process given
+         * we are about to allocate a new node but it is simple and should be
+         * adequate.
+         */
+        wlan_node_reclaim(&wmip->wmi_scan_table, bss);
+    }
+
+    bss = wlan_node_alloc(&wmip->wmi_scan_table, len);
+    if (bss == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    bss->ni_snr        = bih->snr;
+    bss->ni_cie.ie_chan = bih->channel;
+    A_ASSERT(bss->ni_buf != NULL);
+    A_MEMCPY(bss->ni_buf, buf, len);
+    wlan_setup_node(&wmip->wmi_scan_table, bss, bih->bssid);
+
+    return A_OK;
+}
+
+    /* This event indicates inactivity timeout of a fatpipe(pstream)
+     * at the target
+     */
+static A_STATUS
+wmi_pstream_timeout_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMI_PSTREAM_TIMEOUT_EVENT *ev;
+
+    if (len < sizeof(WMI_PSTREAM_TIMEOUT_EVENT)) {
+        return A_EINVAL;
+    }
+
+    A_DPRINTF(DBG_WMI, (DBGFMT "wmi_pstream_timeout_event_rx\n", DBGARG));
+
+    ev = (WMI_PSTREAM_TIMEOUT_EVENT *)datap;
+
+        /* When the pstream (fat pipe == AC) timesout, it means there were no
+         * thinStreams within this pstream & it got implicitly created due to
+         * data flow on this AC. We start the inactivity timer only for
+         * implicitly created pstream. Just reset the host state.
+     */
+        /* Set the activeTsids for this AC to 0 */
+    LOCK_WMI(wmip);
+    wmip->wmi_streamExistsForAC[ev->trafficClass]=0;
+    wmip->wmi_fatPipeExists &= ~(1 << ev->trafficClass);
+    UNLOCK_WMI(wmip);
+
+        /*Indicate inactivity to driver layer for this fatpipe (pstream)*/
+    A_WMI_STREAM_TX_INACTIVE(wmip->wmi_devt, ev->trafficClass);
+
+    return A_OK;
+}
+
+static A_STATUS
+wmi_bitrate_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMI_BIT_RATE_REPLY *reply;
+    A_INT32 rate;
+    A_UINT32 sgi,index;
+    /* 54149:
+     * WMI_BIT_RATE_CMD structure is changed to WMI_BIT_RATE_REPLY.
+     * since there is difference in the length and to avoid returning
+     * error value.
+     */
+    if (len < sizeof(WMI_BIT_RATE_REPLY)) {
+        return A_EINVAL;
+    }
+    reply = (WMI_BIT_RATE_REPLY *)datap;
+    A_DPRINTF(DBG_WMI,
+        (DBGFMT "Enter - rateindex %d\n", DBGARG, reply->rateIndex));
+
+    if (reply->rateIndex == (A_INT8) RATE_AUTO) {
+        rate = RATE_AUTO;
+    } else {
+        // the SGI state is stored as the MSb of the rateIndex
+        index = reply->rateIndex & 0x7f;
+        sgi = (reply->rateIndex & 0x80)? 1:0;
+        rate = wmi_rateTable[index][sgi];
+    }
+
+    A_WMI_BITRATE_RX(wmip->wmi_devt, rate);
+    return A_OK;
+}
+
+static A_STATUS
+wmi_ratemask_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMI_FIX_RATES_REPLY *reply;
+
+    if (len < sizeof(WMI_FIX_RATES_REPLY)) {
+        return A_EINVAL;
+    }
+    reply = (WMI_FIX_RATES_REPLY *)datap;
+    A_DPRINTF(DBG_WMI,
+        (DBGFMT "Enter - fixed rate mask %x\n", DBGARG, reply->fixRateMask));
+
+    A_WMI_RATEMASK_RX(wmip->wmi_devt, reply->fixRateMask);
+
+    return A_OK;
+}
+
+static A_STATUS
+wmi_channelList_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMI_CHANNEL_LIST_REPLY *reply;
+
+    if (len < sizeof(WMI_CHANNEL_LIST_REPLY)) {
+        return A_EINVAL;
+    }
+    reply = (WMI_CHANNEL_LIST_REPLY *)datap;
+    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+    A_WMI_CHANNELLIST_RX(wmip->wmi_devt, reply->numChannels,
+                          reply->channelList);
+
+    return A_OK;
+}
+
+static A_STATUS
+wmi_txPwr_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMI_TX_PWR_REPLY *reply;
+
+    if (len < sizeof(*reply)) {
+        return A_EINVAL;
+    }
+    reply = (WMI_TX_PWR_REPLY *)datap;
+    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+    A_WMI_TXPWR_RX(wmip->wmi_devt, reply->dbM);
+
+    return A_OK;
+}
+static A_STATUS
+wmi_keepalive_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMI_GET_KEEPALIVE_CMD *reply;
+
+    if (len < sizeof(*reply)) {
+        return A_EINVAL;
+    }
+    reply = (WMI_GET_KEEPALIVE_CMD *)datap;
+    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+    A_WMI_KEEPALIVE_RX(wmip->wmi_devt, reply->configured);
+
+    return A_OK;
+}
+
+
+static A_STATUS
+wmi_dset_open_req_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMIX_DSETOPENREQ_EVENT *dsetopenreq;
+
+    if (len < sizeof(WMIX_DSETOPENREQ_EVENT)) {
+        return A_EINVAL;
+    }
+    dsetopenreq = (WMIX_DSETOPENREQ_EVENT *)datap;
+    A_DPRINTF(DBG_WMI,
+        (DBGFMT "Enter - dset_id=0x%x\n", DBGARG, dsetopenreq->dset_id));
+    A_WMI_DSET_OPEN_REQ(wmip->wmi_devt,
+                        dsetopenreq->dset_id,
+                        dsetopenreq->targ_dset_handle,
+                        dsetopenreq->targ_reply_fn,
+                        dsetopenreq->targ_reply_arg);
+
+    return A_OK;
+}
+
+#ifdef CONFIG_HOST_DSET_SUPPORT
+static A_STATUS
+wmi_dset_close_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMIX_DSETCLOSE_EVENT *dsetclose;
+
+    if (len < sizeof(WMIX_DSETCLOSE_EVENT)) {
+        return A_EINVAL;
+    }
+    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+    dsetclose = (WMIX_DSETCLOSE_EVENT *)datap;
+    A_WMI_DSET_CLOSE(wmip->wmi_devt, dsetclose->access_cookie);
+
+    return A_OK;
+}
+
+static A_STATUS
+wmi_dset_data_req_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMIX_DSETDATAREQ_EVENT *dsetdatareq;
+
+    if (len < sizeof(WMIX_DSETDATAREQ_EVENT)) {
+        return A_EINVAL;
+    }
+    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+    dsetdatareq = (WMIX_DSETDATAREQ_EVENT *)datap;
+    A_WMI_DSET_DATA_REQ(wmip->wmi_devt,
+                         dsetdatareq->access_cookie,
+                         dsetdatareq->offset,
+                         dsetdatareq->length,
+                         dsetdatareq->targ_buf,
+                         dsetdatareq->targ_reply_fn,
+                         dsetdatareq->targ_reply_arg);
+
+    return A_OK;
+}
+#endif /* CONFIG_HOST_DSET_SUPPORT */
+
+static A_STATUS
+wmi_scanComplete_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMI_SCAN_COMPLETE_EVENT *ev;
+
+    ev = (WMI_SCAN_COMPLETE_EVENT *)datap;
+    if ((A_STATUS)ev->status == A_OK) {
+        wlan_refresh_inactive_nodes(&wmip->wmi_scan_table);
+    }
+    A_WMI_SCANCOMPLETE_EVENT(wmip->wmi_devt, (A_STATUS) ev->status);
+    is_probe_ssid = FALSE;
+
+    return A_OK;
+}
+
+/*
+ * Target is reporting a programming error.  This is for
+ * developer aid only.  Target only checks a few common violations
+ * and it is responsibility of host to do all error checking.
+ * Behavior of target after wmi error event is undefined.
+ * A reset is recommended.
+ */
+static A_STATUS
+wmi_errorEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMI_CMD_ERROR_EVENT *ev;
+
+    ev = (WMI_CMD_ERROR_EVENT *)datap;
+    AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("Programming Error: cmd=%d ", ev->commandId));
+    switch (ev->errorCode) {
+    case (INVALID_PARAM):
+        AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("Illegal Parameter\n"));
+        break;
+    case (ILLEGAL_STATE):
+        AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("Illegal State\n"));
+        break;
+    case (INTERNAL_ERROR):
+        AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("Internal Error\n"));
+        break;
+    }
+
+    return A_OK;
+}
+
+
+static A_STATUS
+wmi_statsEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+    A_WMI_TARGETSTATS_EVENT(wmip->wmi_devt, datap, len);
+
+    return A_OK;
+}
+
+static A_STATUS
+wmi_rssiThresholdEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMI_RSSI_THRESHOLD_EVENT *reply;
+    WMI_RSSI_THRESHOLD_VAL newThreshold;
+    WMI_RSSI_THRESHOLD_PARAMS_CMD cmd;
+    SQ_THRESHOLD_PARAMS *sq_thresh =
+           &wmip->wmi_SqThresholdParams[SIGNAL_QUALITY_METRICS_RSSI];
+    A_UINT8 upper_rssi_threshold, lower_rssi_threshold;
+    A_INT16 rssi;
+
+    if (len < sizeof(*reply)) {
+        return A_EINVAL;
+    }
+    reply = (WMI_RSSI_THRESHOLD_EVENT *)datap;
+    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+    newThreshold = (WMI_RSSI_THRESHOLD_VAL) reply->range;
+    rssi = reply->rssi;
+
+    /*
+     * Identify the threshold breached and communicate that to the app. After
+     * that install a new set of thresholds based on the signal quality
+     * reported by the target
+     */
+    if (newThreshold) {
+        /* Upper threshold breached */
+        if (rssi < sq_thresh->upper_threshold[0]) {
+            A_DPRINTF(DBG_WMI, (DBGFMT "Spurious upper RSSI threshold event: "
+                      " %d\n", DBGARG, rssi));
+        } else if ((rssi < sq_thresh->upper_threshold[1]) &&
+                   (rssi >= sq_thresh->upper_threshold[0]))
+        {
+            newThreshold = WMI_RSSI_THRESHOLD1_ABOVE;
+        } else if ((rssi < sq_thresh->upper_threshold[2]) &&
+                   (rssi >= sq_thresh->upper_threshold[1]))
+        {
+            newThreshold = WMI_RSSI_THRESHOLD2_ABOVE;
+        } else if ((rssi < sq_thresh->upper_threshold[3]) &&
+                   (rssi >= sq_thresh->upper_threshold[2]))
+        {
+            newThreshold = WMI_RSSI_THRESHOLD3_ABOVE;
+        } else if ((rssi < sq_thresh->upper_threshold[4]) &&
+                   (rssi >= sq_thresh->upper_threshold[3]))
+        {
+            newThreshold = WMI_RSSI_THRESHOLD4_ABOVE;
+        } else if ((rssi < sq_thresh->upper_threshold[5]) &&
+                   (rssi >= sq_thresh->upper_threshold[4]))
+        {
+            newThreshold = WMI_RSSI_THRESHOLD5_ABOVE;
+        } else if (rssi >= sq_thresh->upper_threshold[5]) {
+            newThreshold = WMI_RSSI_THRESHOLD6_ABOVE;
+        }
+    } else {
+        /* Lower threshold breached */
+        if (rssi > sq_thresh->lower_threshold[0]) {
+            A_DPRINTF(DBG_WMI, (DBGFMT "Spurious lower RSSI threshold event: "
+                      "%d %d\n", DBGARG, rssi, sq_thresh->lower_threshold[0]));
+        } else if ((rssi > sq_thresh->lower_threshold[1]) &&
+                   (rssi <= sq_thresh->lower_threshold[0]))
+        {
+            newThreshold = WMI_RSSI_THRESHOLD6_BELOW;
+        } else if ((rssi > sq_thresh->lower_threshold[2]) &&
+                   (rssi <= sq_thresh->lower_threshold[1]))
+        {
+            newThreshold = WMI_RSSI_THRESHOLD5_BELOW;
+        } else if ((rssi > sq_thresh->lower_threshold[3]) &&
+                   (rssi <= sq_thresh->lower_threshold[2]))
+        {
+            newThreshold = WMI_RSSI_THRESHOLD4_BELOW;
+        } else if ((rssi > sq_thresh->lower_threshold[4]) &&
+                   (rssi <= sq_thresh->lower_threshold[3]))
+        {
+            newThreshold = WMI_RSSI_THRESHOLD3_BELOW;
+        } else if ((rssi > sq_thresh->lower_threshold[5]) &&
+                   (rssi <= sq_thresh->lower_threshold[4]))
+        {
+            newThreshold = WMI_RSSI_THRESHOLD2_BELOW;
+        } else if (rssi <= sq_thresh->lower_threshold[5]) {
+            newThreshold = WMI_RSSI_THRESHOLD1_BELOW;
+        }
+    }
+    /* Calculate and install the next set of thresholds */
+    lower_rssi_threshold = ar6000_get_lower_threshold(rssi, sq_thresh,
+                                      sq_thresh->lower_threshold_valid_count);
+    upper_rssi_threshold = ar6000_get_upper_threshold(rssi, sq_thresh,
+                                      sq_thresh->upper_threshold_valid_count);
+    /* Issue a wmi command to install the thresholds */
+    cmd.thresholdAbove1_Val = upper_rssi_threshold;
+    cmd.thresholdBelow1_Val = lower_rssi_threshold;
+    cmd.weight = sq_thresh->weight;
+    cmd.pollTime = sq_thresh->polling_interval;
+
+    rssi_event_value = rssi;
+
+    if (wmi_send_rssi_threshold_params(wmip, &cmd) != A_OK) {
+        A_DPRINTF(DBG_WMI, (DBGFMT "Unable to configure the RSSI thresholds\n",
+                  DBGARG));
+    }
+
+    A_WMI_RSSI_THRESHOLD_EVENT(wmip->wmi_devt, newThreshold, reply->rssi);
+
+    return A_OK;
+}
+
+
+static A_STATUS
+wmi_reportErrorEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMI_TARGET_ERROR_REPORT_EVENT *reply;
+
+    if (len < sizeof(*reply)) {
+        return A_EINVAL;
+    }
+    reply = (WMI_TARGET_ERROR_REPORT_EVENT *)datap;
+    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+    A_WMI_REPORT_ERROR_EVENT(wmip->wmi_devt, (WMI_TARGET_ERROR_VAL) reply->errorVal);
+
+    return A_OK;
+}
+
+static A_STATUS
+wmi_cac_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMI_CAC_EVENT *reply;
+    WMM_TSPEC_IE *tspec_ie;
+    A_UINT16 activeTsids;
+
+    if (len < sizeof(*reply)) {
+        return A_EINVAL;
+    }
+    reply = (WMI_CAC_EVENT *)datap;
+
+    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+    if ((reply->cac_indication == CAC_INDICATION_ADMISSION_RESP) &&
+        (reply->statusCode != TSPEC_STATUS_CODE_ADMISSION_ACCEPTED)) {
+        tspec_ie = (WMM_TSPEC_IE *) &(reply->tspecSuggestion);
+
+        wmi_delete_pstream_cmd(wmip, reply->ac,
+                (tspec_ie->tsInfo_info >> TSPEC_TSID_S) & TSPEC_TSID_MASK);
+    }
+    else if (reply->cac_indication == CAC_INDICATION_NO_RESP) {
+        A_UINT8 i;
+
+        /* following assumes that there is only one outstanding ADDTS request
+           when this event is received */
+        LOCK_WMI(wmip);
+        activeTsids = wmip->wmi_streamExistsForAC[reply->ac];
+        UNLOCK_WMI(wmip);
+
+        for (i = 0; i < sizeof(activeTsids) * 8; i++) {
+            if ((activeTsids >> i) & 1) {
+                break;
+            }
+        }
+        if (i < (sizeof(activeTsids) * 8)) {
+            wmi_delete_pstream_cmd(wmip, reply->ac, i);
+        }
+    }
+        /*
+         * Ev#72990: Clear active tsids and Add missing handling
+         * for delete qos stream from AP
+         */
+    else if (reply->cac_indication == CAC_INDICATION_DELETE) {
+        A_UINT8 tsid = 0;
+
+        tspec_ie = (WMM_TSPEC_IE *) &(reply->tspecSuggestion);
+        tsid= ((tspec_ie->tsInfo_info >> TSPEC_TSID_S) & TSPEC_TSID_MASK);
+        LOCK_WMI(wmip);
+        wmip->wmi_streamExistsForAC[reply->ac] &= ~(1<<tsid);
+        activeTsids = wmip->wmi_streamExistsForAC[reply->ac];
+        UNLOCK_WMI(wmip);
+
+
+        /* Indicate stream inactivity to driver layer only if all tsids
+         * within this AC are deleted.
+         */
+       if (!activeTsids) {
+           A_WMI_STREAM_TX_INACTIVE(wmip->wmi_devt, reply->ac);
+           wmip->wmi_fatPipeExists &= ~(1 << reply->ac);
+        }
+    }
+
+    A_WMI_CAC_EVENT(wmip->wmi_devt, reply->ac,
+                reply->cac_indication, reply->statusCode,
+                reply->tspecSuggestion);
+
+    return A_OK;
+}
+
+static A_STATUS
+wmi_channel_change_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMI_CHANNEL_CHANGE_EVENT *reply;
+
+    if (len < sizeof(*reply)) {
+        return A_EINVAL;
+    }
+    reply = (WMI_CHANNEL_CHANGE_EVENT *)datap;
+    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+    A_WMI_CHANNEL_CHANGE_EVENT(wmip->wmi_devt, reply->oldChannel,
+                               reply->newChannel);
+
+    return A_OK;
+}
+
+static A_STATUS
+wmi_hbChallengeResp_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMIX_HB_CHALLENGE_RESP_EVENT *reply;
+
+    if (len < sizeof(*reply)) {
+        return A_EINVAL;
+    }
+    reply = (WMIX_HB_CHALLENGE_RESP_EVENT *)datap;
+    A_DPRINTF(DBG_WMI, (DBGFMT "wmi: challenge response event\n", DBGARG));
+
+    A_WMI_HBCHALLENGERESP_EVENT(wmip->wmi_devt, reply->cookie, reply->source);
+
+    return A_OK;
+}
+
+static A_STATUS
+wmi_roam_tbl_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMI_TARGET_ROAM_TBL *reply;
+
+    if (len < sizeof(*reply)) {
+        return A_EINVAL;
+    }
+    reply = (WMI_TARGET_ROAM_TBL *)datap;
+    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+    A_WMI_ROAM_TABLE_EVENT(wmip->wmi_devt, reply);
+
+    return A_OK;
+}
+
+static A_STATUS
+wmi_roam_data_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMI_TARGET_ROAM_DATA *reply;
+
+    if (len < sizeof(*reply)) {
+        return A_EINVAL;
+    }
+    reply = (WMI_TARGET_ROAM_DATA *)datap;
+    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+    A_WMI_ROAM_DATA_EVENT(wmip->wmi_devt, reply);
+
+    return A_OK;
+}
+
+static A_STATUS
+wmi_txRetryErrEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    if (len < sizeof(WMI_TX_RETRY_ERR_EVENT)) {
+        return A_EINVAL;
+    }
+    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+    A_WMI_TX_RETRY_ERR_EVENT(wmip->wmi_devt);
+
+    return A_OK;
+}
+
+static A_STATUS
+wmi_snrThresholdEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMI_SNR_THRESHOLD_EVENT *reply;
+    SQ_THRESHOLD_PARAMS *sq_thresh =
+           &wmip->wmi_SqThresholdParams[SIGNAL_QUALITY_METRICS_SNR];
+    WMI_SNR_THRESHOLD_VAL newThreshold;
+    WMI_SNR_THRESHOLD_PARAMS_CMD cmd;
+    A_UINT8 upper_snr_threshold, lower_snr_threshold;
+    A_INT16 snr;
+
+    if (len < sizeof(*reply)) {
+        return A_EINVAL;
+    }
+    reply = (WMI_SNR_THRESHOLD_EVENT *)datap;
+    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+    newThreshold = (WMI_SNR_THRESHOLD_VAL) reply->range;
+    snr = reply->snr;
+    /*
+     * Identify the threshold breached and communicate that to the app. After
+     * that install a new set of thresholds based on the signal quality
+     * reported by the target
+     */
+    if (newThreshold) {
+        /* Upper threshold breached */
+        if (snr < sq_thresh->upper_threshold[0]) {
+            A_DPRINTF(DBG_WMI, (DBGFMT "Spurious upper SNR threshold event: "
+                     "%d\n", DBGARG, snr));
+        } else if ((snr < sq_thresh->upper_threshold[1]) &&
+                   (snr >= sq_thresh->upper_threshold[0]))
+        {
+            newThreshold = WMI_SNR_THRESHOLD1_ABOVE;
+        } else if ((snr < sq_thresh->upper_threshold[2]) &&
+                   (snr >= sq_thresh->upper_threshold[1]))
+        {
+            newThreshold = WMI_SNR_THRESHOLD2_ABOVE;
+        } else if ((snr < sq_thresh->upper_threshold[3]) &&
+                   (snr >= sq_thresh->upper_threshold[2]))
+        {
+            newThreshold = WMI_SNR_THRESHOLD3_ABOVE;
+        } else if (snr >= sq_thresh->upper_threshold[3]) {
+            newThreshold = WMI_SNR_THRESHOLD4_ABOVE;
+        }
+    } else {
+        /* Lower threshold breached */
+        if (snr > sq_thresh->lower_threshold[0]) {
+            A_DPRINTF(DBG_WMI, (DBGFMT "Spurious lower SNR threshold event: "
+                      "%d %d\n", DBGARG, snr, sq_thresh->lower_threshold[0]));
+        } else if ((snr > sq_thresh->lower_threshold[1]) &&
+                   (snr <= sq_thresh->lower_threshold[0]))
+        {
+            newThreshold = WMI_SNR_THRESHOLD4_BELOW;
+        } else if ((snr > sq_thresh->lower_threshold[2]) &&
+                   (snr <= sq_thresh->lower_threshold[1]))
+        {
+            newThreshold = WMI_SNR_THRESHOLD3_BELOW;
+        } else if ((snr > sq_thresh->lower_threshold[3]) &&
+                   (snr <= sq_thresh->lower_threshold[2]))
+        {
+            newThreshold = WMI_SNR_THRESHOLD2_BELOW;
+        } else if (snr <= sq_thresh->lower_threshold[3]) {
+            newThreshold = WMI_SNR_THRESHOLD1_BELOW;
+        }
+    }
+
+    /* Calculate and install the next set of thresholds */
+    lower_snr_threshold = ar6000_get_lower_threshold(snr, sq_thresh,
+                                      sq_thresh->lower_threshold_valid_count);
+    upper_snr_threshold = ar6000_get_upper_threshold(snr, sq_thresh,
+                                      sq_thresh->upper_threshold_valid_count);
+
+    /* Issue a wmi command to install the thresholds */
+    cmd.thresholdAbove1_Val = upper_snr_threshold;
+    cmd.thresholdBelow1_Val = lower_snr_threshold;
+    cmd.weight = sq_thresh->weight;
+    cmd.pollTime = sq_thresh->polling_interval;
+
+    A_DPRINTF(DBG_WMI, (DBGFMT "snr: %d, threshold: %d, lower: %d, upper: %d\n"
+              ,DBGARG, snr, newThreshold, lower_snr_threshold,
+              upper_snr_threshold));
+
+    snr_event_value = snr;
+
+    if (wmi_send_snr_threshold_params(wmip, &cmd) != A_OK) {
+        A_DPRINTF(DBG_WMI, (DBGFMT "Unable to configure the SNR thresholds\n",
+                  DBGARG));
+    }
+    A_WMI_SNR_THRESHOLD_EVENT_RX(wmip->wmi_devt, newThreshold, reply->snr);
+
+    return A_OK;
+}
+
+static A_STATUS
+wmi_lqThresholdEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMI_LQ_THRESHOLD_EVENT *reply;
+
+    if (len < sizeof(*reply)) {
+        return A_EINVAL;
+    }
+    reply = (WMI_LQ_THRESHOLD_EVENT *)datap;
+    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+    A_WMI_LQ_THRESHOLD_EVENT_RX(wmip->wmi_devt,
+                                (WMI_LQ_THRESHOLD_VAL) reply->range,
+                                reply->lq);
+
+    return A_OK;
+}
+
+static A_STATUS
+wmi_aplistEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    A_UINT16 ap_info_entry_size;
+    WMI_APLIST_EVENT *ev = (WMI_APLIST_EVENT *)datap;
+    WMI_AP_INFO_V1 *ap_info_v1;
+    A_UINT8 i;
+
+    if (len < sizeof(WMI_APLIST_EVENT)) {
+        return A_EINVAL;
+    }
+
+    if (ev->apListVer == APLIST_VER1) {
+        ap_info_entry_size = sizeof(WMI_AP_INFO_V1);
+        ap_info_v1 = (WMI_AP_INFO_V1 *)ev->apList;
+    } else {
+        return A_EINVAL;
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("Number of APs in APLIST Event is %d\n", ev->numAP));
+    if (len < (int)(sizeof(WMI_APLIST_EVENT) +
+              (ev->numAP - 1) * ap_info_entry_size))
+    {
+        return A_EINVAL;
+    }
+
+    /*
+     * AP List Ver1 Contents
+     */
+    for (i = 0; i < ev->numAP; i++) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("AP#%d BSSID %2.2x %2.2x %2.2x %2.2x %2.2x %2.2x "\
+                    "Channel %d\n", i,
+                   ap_info_v1->bssid[0], ap_info_v1->bssid[1],
+                   ap_info_v1->bssid[2], ap_info_v1->bssid[3],
+                   ap_info_v1->bssid[4], ap_info_v1->bssid[5],
+                   ap_info_v1->channel));
+        ap_info_v1++;
+    }
+    return A_OK;
+}
+
+static A_STATUS
+wmi_dbglog_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    A_UINT32 dropped;
+
+    dropped = *((A_UINT32 *)datap);
+    datap += sizeof(dropped);
+    len -= sizeof(dropped);
+    A_WMI_DBGLOG_EVENT(wmip->wmi_devt, dropped, (A_INT8*)datap, len);
+    return A_OK;
+}
+
+#ifdef CONFIG_HOST_GPIO_SUPPORT
+static A_STATUS
+wmi_gpio_intr_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMIX_GPIO_INTR_EVENT *gpio_intr = (WMIX_GPIO_INTR_EVENT *)datap;
+
+    A_DPRINTF(DBG_WMI,
+        (DBGFMT "Enter - intrmask=0x%x input=0x%x.\n", DBGARG,
+        gpio_intr->intr_mask, gpio_intr->input_values));
+
+    A_WMI_GPIO_INTR_RX(gpio_intr->intr_mask, gpio_intr->input_values);
+
+    return A_OK;
+}
+
+static A_STATUS
+wmi_gpio_data_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMIX_GPIO_DATA_EVENT *gpio_data = (WMIX_GPIO_DATA_EVENT *)datap;
+
+    A_DPRINTF(DBG_WMI,
+        (DBGFMT "Enter - reg=%d value=0x%x\n", DBGARG,
+        gpio_data->reg_id, gpio_data->value));
+
+    A_WMI_GPIO_DATA_RX(gpio_data->reg_id, gpio_data->value);
+
+    return A_OK;
+}
+
+static A_STATUS
+wmi_gpio_ack_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+    A_WMI_GPIO_ACK_RX();
+
+    return A_OK;
+}
+#endif /* CONFIG_HOST_GPIO_SUPPORT */
+
+/*
+ * Called to send a wmi command. Command specific data is already built
+ * on osbuf and current osbuf->data points to it.
+ */
+A_STATUS
+wmi_cmd_send(struct wmi_t *wmip, void *osbuf, WMI_COMMAND_ID cmdId,
+               WMI_SYNC_FLAG syncflag)
+{
+    A_STATUS status;
+#define IS_OPT_TX_CMD(cmdId) ((cmdId == WMI_OPT_TX_FRAME_CMDID))
+    WMI_CMD_HDR         *cHdr;
+    HTC_ENDPOINT_ID     eid  = wmip->wmi_endpoint_id;
+
+    A_ASSERT(osbuf != NULL);
+
+    if (syncflag >= END_WMIFLAG) {
+        A_NETBUF_FREE(osbuf);
+        return A_EINVAL;
+    }
+
+    if ((syncflag == SYNC_BEFORE_WMIFLAG) || (syncflag == SYNC_BOTH_WMIFLAG)) {
+        /*
+         * We want to make sure all data currently queued is transmitted before
+         * the cmd execution.  Establish a new sync point.
+         */
+        wmi_sync_point(wmip);
+    }
+
+    if (A_NETBUF_PUSH(osbuf, sizeof(WMI_CMD_HDR)) != A_OK) {
+        A_NETBUF_FREE(osbuf);
+        return A_NO_MEMORY;
+    }
+
+    cHdr = (WMI_CMD_HDR *)A_NETBUF_DATA(osbuf);
+    cHdr->commandId = (A_UINT16) cmdId;
+    cHdr->info1 = 0; // added for virtual interface
+
+    /*
+     * Only for OPT_TX_CMD, use BE endpoint.
+     */
+    if (IS_OPT_TX_CMD(cmdId)) {
+        if ((status=wmi_data_hdr_add(wmip, osbuf, OPT_MSGTYPE, FALSE, FALSE,0,NULL)) != A_OK) {
+            A_NETBUF_FREE(osbuf);
+            return status;
+        }
+        eid = A_WMI_Ac2EndpointID(wmip->wmi_devt, WMM_AC_BE);
+    }
+    A_WMI_CONTROL_TX(wmip->wmi_devt, osbuf, eid);
+
+    if ((syncflag == SYNC_AFTER_WMIFLAG) || (syncflag == SYNC_BOTH_WMIFLAG)) {
+        /*
+         * We want to make sure all new data queued waits for the command to
+         * execute. Establish a new sync point.
+         */
+        wmi_sync_point(wmip);
+    }
+    return (A_OK);
+#undef IS_OPT_TX_CMD
+}
+
+A_STATUS
+wmi_cmd_send_xtnd(struct wmi_t *wmip, void *osbuf, WMIX_COMMAND_ID cmdId,
+                  WMI_SYNC_FLAG syncflag)
+{
+    WMIX_CMD_HDR     *cHdr;
+
+    if (A_NETBUF_PUSH(osbuf, sizeof(WMIX_CMD_HDR)) != A_OK) {
+        A_NETBUF_FREE(osbuf);
+        return A_NO_MEMORY;
+    }
+
+    cHdr = (WMIX_CMD_HDR *)A_NETBUF_DATA(osbuf);
+    cHdr->commandId = (A_UINT32) cmdId;
+
+    return wmi_cmd_send(wmip, osbuf, WMI_EXTENSION_CMDID, syncflag);
+}
+
+A_STATUS
+wmi_connect_cmd(struct wmi_t *wmip, NETWORK_TYPE netType,
+                DOT11_AUTH_MODE dot11AuthMode, AUTH_MODE authMode,
+                CRYPTO_TYPE pairwiseCrypto, A_UINT8 pairwiseCryptoLen,
+                CRYPTO_TYPE groupCrypto, A_UINT8 groupCryptoLen,
+                int ssidLength, A_UCHAR *ssid,
+                A_UINT8 *bssid, A_UINT16 channel, A_UINT32 ctrl_flags)
+{
+    void *osbuf;
+    WMI_CONNECT_CMD *cc;
+    wmip->wmi_traffic_class = 100;
+
+    if ((pairwiseCrypto == NONE_CRYPT) && (groupCrypto != NONE_CRYPT)) {
+        return A_EINVAL;
+    }
+    if ((pairwiseCrypto != NONE_CRYPT) && (groupCrypto == NONE_CRYPT)) {
+        return A_EINVAL;
+    }
+
+    osbuf = A_NETBUF_ALLOC(sizeof(WMI_CONNECT_CMD));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(WMI_CONNECT_CMD));
+
+    cc = (WMI_CONNECT_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cc, sizeof(*cc));
+
+    if (ssidLength)
+    {
+        A_MEMCPY(cc->ssid, ssid, ssidLength);
+    }
+
+    cc->ssidLength          = ssidLength;
+    cc->networkType         = netType;
+    cc->dot11AuthMode       = dot11AuthMode;
+    cc->authMode            = authMode;
+    cc->pairwiseCryptoType  = pairwiseCrypto;
+    cc->pairwiseCryptoLen   = pairwiseCryptoLen;
+    cc->groupCryptoType     = groupCrypto;
+    cc->groupCryptoLen      = groupCryptoLen;
+    cc->channel             = channel;
+    cc->ctrl_flags          = ctrl_flags;
+
+    if (bssid != NULL) {
+        A_MEMCPY(cc->bssid, bssid, ATH_MAC_LEN);
+    }
+
+    wmip->wmi_pair_crypto_type  = pairwiseCrypto;
+    wmip->wmi_grp_crypto_type   = groupCrypto;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_CONNECT_CMDID, NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_reconnect_cmd(struct wmi_t *wmip, A_UINT8 *bssid, A_UINT16 channel)
+{
+    void *osbuf;
+    WMI_RECONNECT_CMD *cc;
+    wmip->wmi_traffic_class = 100;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(WMI_RECONNECT_CMD));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(WMI_RECONNECT_CMD));
+
+    cc = (WMI_RECONNECT_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cc, sizeof(*cc));
+
+    cc->channel = channel;
+
+    if (bssid != NULL) {
+        A_MEMCPY(cc->bssid, bssid, ATH_MAC_LEN);
+    }
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_RECONNECT_CMDID, NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_disconnect_cmd(struct wmi_t *wmip)
+{
+    A_STATUS status;
+    wmip->wmi_traffic_class = 100;
+
+    /* Bug fix for 24817(elevator bug) - the disconnect command does not
+       need to do a SYNC before.*/
+    status = wmi_simple_cmd(wmip, WMI_DISCONNECT_CMDID);
+
+    return status;
+}
+
+A_STATUS
+wmi_startscan_cmd(struct wmi_t *wmip, WMI_SCAN_TYPE scanType,
+                  A_BOOL forceFgScan, A_BOOL isLegacy,
+                  A_UINT32 homeDwellTime, A_UINT32 forceScanInterval,
+                  A_INT8 numChan, A_UINT16 *channelList)
+{
+    void *osbuf;
+    WMI_START_SCAN_CMD *sc;
+    A_INT8 size;
+
+    size = sizeof (*sc);
+
+    if ((scanType != WMI_LONG_SCAN) && (scanType != WMI_SHORT_SCAN)) {
+        return A_EINVAL;
+    }
+
+    if (numChan) {
+        if (numChan > WMI_MAX_CHANNELS) {
+            return A_EINVAL;
+        }
+        size += sizeof(A_UINT16) * (numChan - 1);
+    }
+
+    osbuf = A_NETBUF_ALLOC(size);
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, size);
+
+    sc = (WMI_START_SCAN_CMD *)(A_NETBUF_DATA(osbuf));
+    sc->scanType = scanType;
+    sc->forceFgScan = forceFgScan;
+    sc->isLegacy = isLegacy;
+    sc->homeDwellTime = homeDwellTime;
+    sc->forceScanInterval = forceScanInterval;
+    sc->numChannels = numChan;
+    if (numChan) {
+        A_MEMCPY(sc->channelList, channelList, numChan * sizeof(A_UINT16));
+    }
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_START_SCAN_CMDID, NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_scanparams_cmd(struct wmi_t *wmip, A_UINT16 fg_start_sec,
+                   A_UINT16 fg_end_sec, A_UINT16 bg_sec,
+                   A_UINT16 minact_chdw_msec, A_UINT16 maxact_chdw_msec,
+                   A_UINT16 pas_chdw_msec,
+                   A_UINT8 shScanRatio, A_UINT8 scanCtrlFlags,
+                   A_UINT32 max_dfsch_act_time, A_UINT16 maxact_scan_per_ssid)
+{
+    void *osbuf;
+    WMI_SCAN_PARAMS_CMD *sc;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*sc));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*sc));
+
+    sc = (WMI_SCAN_PARAMS_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(sc, sizeof(*sc));
+    sc->fg_start_period  = fg_start_sec;
+    sc->fg_end_period    = fg_end_sec;
+    sc->bg_period        = bg_sec;
+    sc->minact_chdwell_time = minact_chdw_msec;
+    sc->maxact_chdwell_time = maxact_chdw_msec;
+    sc->pas_chdwell_time = pas_chdw_msec;
+    sc->shortScanRatio   = shScanRatio;
+    sc->scanCtrlFlags    = scanCtrlFlags;
+    sc->max_dfsch_act_time = max_dfsch_act_time;
+    sc->maxact_scan_per_ssid = maxact_scan_per_ssid;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_SCAN_PARAMS_CMDID,
+                         NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_bssfilter_cmd(struct wmi_t *wmip, A_UINT8 filter, A_UINT32 ieMask)
+{
+    void *osbuf;
+    WMI_BSS_FILTER_CMD *cmd;
+
+    if (filter >= LAST_BSS_FILTER) {
+        return A_EINVAL;
+    }
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_BSS_FILTER_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+    cmd->bssFilter = filter;
+    cmd->ieMask = ieMask;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_BSS_FILTER_CMDID,
+                         NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_probedSsid_cmd(struct wmi_t *wmip, A_UINT8 index, A_UINT8 flag,
+                   A_UINT8 ssidLength, A_UCHAR *ssid)
+{
+    void *osbuf;
+    WMI_PROBED_SSID_CMD *cmd;
+
+    if (index > MAX_PROBED_SSID_INDEX) {
+        return A_EINVAL;
+    }
+    if (ssidLength > sizeof(cmd->ssid)) {
+        return A_EINVAL;
+    }
+    if ((flag & (DISABLE_SSID_FLAG | ANY_SSID_FLAG)) && (ssidLength > 0)) {
+        return A_EINVAL;
+    }
+    if ((flag & SPECIFIC_SSID_FLAG) && !ssidLength) {
+        return A_EINVAL;
+    }
+
+    if (flag & SPECIFIC_SSID_FLAG) {
+        is_probe_ssid = TRUE;
+    }
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_PROBED_SSID_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+    cmd->entryIndex = index;
+    cmd->flag       = flag;
+    cmd->ssidLength = ssidLength;
+    A_MEMCPY(cmd->ssid, ssid, ssidLength);
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_PROBED_SSID_CMDID,
+                         NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_listeninterval_cmd(struct wmi_t *wmip, A_UINT16 listenInterval, A_UINT16 listenBeacons)
+{
+    void *osbuf;
+    WMI_LISTEN_INT_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_LISTEN_INT_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+    cmd->listenInterval = listenInterval;
+    cmd->numBeacons = listenBeacons;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_LISTEN_INT_CMDID,
+                         NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_bmisstime_cmd(struct wmi_t *wmip, A_UINT16 bmissTime, A_UINT16 bmissBeacons)
+{
+    void *osbuf;
+    WMI_BMISS_TIME_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_BMISS_TIME_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+    cmd->bmissTime = bmissTime;
+    cmd->numBeacons =  bmissBeacons;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_BMISS_TIME_CMDID,
+                         NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_associnfo_cmd(struct wmi_t *wmip, A_UINT8 ieType,
+                     A_UINT8 ieLen, A_UINT8 *ieInfo)
+{
+    void *osbuf;
+    WMI_SET_ASSOC_INFO_CMD *cmd;
+    A_UINT16 cmdLen;
+
+    cmdLen = sizeof(*cmd) + ieLen - 1;
+    osbuf = A_NETBUF_ALLOC(cmdLen);
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, cmdLen);
+
+    cmd = (WMI_SET_ASSOC_INFO_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, cmdLen);
+    cmd->ieType = ieType;
+    cmd->bufferSize = ieLen;
+    A_MEMCPY(cmd->assocInfo, ieInfo, ieLen);
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_ASSOC_INFO_CMDID,
+                         NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_powermode_cmd(struct wmi_t *wmip, A_UINT8 powerMode)
+{
+    void *osbuf;
+    WMI_POWER_MODE_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_POWER_MODE_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+    cmd->powerMode = powerMode;
+    wmip->wmi_powerMode = powerMode;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_POWER_MODE_CMDID,
+                         NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_ibsspmcaps_cmd(struct wmi_t *wmip, A_UINT8 pmEnable, A_UINT8 ttl,
+                   A_UINT16 atim_windows, A_UINT16 timeout_value)
+{
+    void *osbuf;
+    WMI_IBSS_PM_CAPS_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_IBSS_PM_CAPS_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+    cmd->power_saving = pmEnable;
+    cmd->ttl = ttl;
+    cmd->atim_windows = atim_windows;
+    cmd->timeout_value = timeout_value;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_IBSS_PM_CAPS_CMDID,
+                         NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_apps_cmd(struct wmi_t *wmip, A_UINT8 psType, A_UINT32 idle_time,
+                   A_UINT32 ps_period, A_UINT8 sleep_period)
+{
+    void *osbuf;
+    WMI_AP_PS_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_AP_PS_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+    cmd->psType = psType;
+    cmd->idle_time = idle_time;
+    cmd->ps_period = ps_period;
+    cmd->sleep_period = sleep_period;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_AP_PS_CMDID,
+                         NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_pmparams_cmd(struct wmi_t *wmip, A_UINT16 idlePeriod,
+                 A_UINT16 psPollNum, A_UINT16 dtimPolicy,
+                 A_UINT16 tx_wakeup_policy, A_UINT16 num_tx_to_wakeup,
+                 A_UINT16 ps_fail_event_policy)
+{
+    void *osbuf;
+    WMI_POWER_PARAMS_CMD *pm;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*pm));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*pm));
+
+    pm = (WMI_POWER_PARAMS_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(pm, sizeof(*pm));
+    pm->idle_period   = idlePeriod;
+    pm->pspoll_number = psPollNum;
+    pm->dtim_policy   = dtimPolicy;
+    pm->tx_wakeup_policy = tx_wakeup_policy;
+    pm->num_tx_to_wakeup = num_tx_to_wakeup;
+    pm->ps_fail_event_policy = ps_fail_event_policy;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_POWER_PARAMS_CMDID,
+                         NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_disctimeout_cmd(struct wmi_t *wmip, A_UINT8 timeout)
+{
+    void *osbuf;
+    WMI_DISC_TIMEOUT_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_DISC_TIMEOUT_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+    cmd->disconnectTimeout = timeout;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_DISC_TIMEOUT_CMDID,
+                         NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_addKey_cmd(struct wmi_t *wmip, A_UINT8 keyIndex, CRYPTO_TYPE keyType,
+               A_UINT8 keyUsage, A_UINT8 keyLength, A_UINT8 *keyRSC,
+               A_UINT8 *keyMaterial, A_UINT8 key_op_ctrl, A_UINT8 *macAddr,
+               WMI_SYNC_FLAG sync_flag)
+{
+    void *osbuf;
+    WMI_ADD_CIPHER_KEY_CMD *cmd;
+
+    if ((keyIndex > WMI_MAX_KEY_INDEX) || (keyLength > WMI_MAX_KEY_LEN) ||
+        (keyMaterial == NULL))
+    {
+        return A_EINVAL;
+    }
+
+    if ((WEP_CRYPT != keyType) && (NULL == keyRSC)) {
+        return A_EINVAL;
+    }
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_ADD_CIPHER_KEY_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+    cmd->keyIndex = keyIndex;
+    cmd->keyType  = keyType;
+    cmd->keyUsage = keyUsage;
+    cmd->keyLength = keyLength;
+    A_MEMCPY(cmd->key, keyMaterial, keyLength);
+#ifdef WAPI_ENABLE
+    if (NULL != keyRSC && key_op_ctrl != KEY_OP_INIT_WAPIPN) {
+#else
+    if (NULL != keyRSC) {
+#endif // WAPI_ENABLE
+        A_MEMCPY(cmd->keyRSC, keyRSC, sizeof(cmd->keyRSC));
+    }
+    cmd->key_op_ctrl = key_op_ctrl;
+
+    if(macAddr) {
+        A_MEMCPY(cmd->key_macaddr,macAddr,IEEE80211_ADDR_LEN);
+    }
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_ADD_CIPHER_KEY_CMDID, sync_flag));
+}
+
+A_STATUS
+wmi_add_krk_cmd(struct wmi_t *wmip, A_UINT8 *krk)
+{
+    void *osbuf;
+    WMI_ADD_KRK_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_ADD_KRK_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+    A_MEMCPY(cmd->krk, krk, WMI_KRK_LEN);
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_ADD_KRK_CMDID, NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_delete_krk_cmd(struct wmi_t *wmip)
+{
+    return wmi_simple_cmd(wmip, WMI_DELETE_KRK_CMDID);
+}
+
+A_STATUS
+wmi_deleteKey_cmd(struct wmi_t *wmip, A_UINT8 keyIndex)
+{
+    void *osbuf;
+    WMI_DELETE_CIPHER_KEY_CMD *cmd;
+
+    if (keyIndex > WMI_MAX_KEY_INDEX) {
+        return A_EINVAL;
+    }
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_DELETE_CIPHER_KEY_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+    cmd->keyIndex = keyIndex;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_DELETE_CIPHER_KEY_CMDID,
+                         NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_setPmkid_cmd(struct wmi_t *wmip, A_UINT8 *bssid, A_UINT8 *pmkId,
+                 A_BOOL set)
+{
+    void *osbuf;
+    WMI_SET_PMKID_CMD *cmd;
+
+    if (bssid == NULL) {
+        return A_EINVAL;
+    }
+
+    if ((set == TRUE) && (pmkId == NULL)) {
+        return A_EINVAL;
+    }
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_SET_PMKID_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMCPY(cmd->bssid, bssid, sizeof(cmd->bssid));
+    if (set == TRUE) {
+        A_MEMCPY(cmd->pmkid, pmkId, sizeof(cmd->pmkid));
+        cmd->enable = PMKID_ENABLE;
+    } else {
+        A_MEMZERO(cmd->pmkid, sizeof(cmd->pmkid));
+        cmd->enable = PMKID_DISABLE;
+    }
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_PMKID_CMDID, NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_tkip_countermeasures_cmd(struct wmi_t *wmip, A_BOOL en)
+{
+    void *osbuf;
+    WMI_SET_TKIP_COUNTERMEASURES_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_SET_TKIP_COUNTERMEASURES_CMD *)(A_NETBUF_DATA(osbuf));
+    cmd->cm_en = (en == TRUE)? WMI_TKIP_CM_ENABLE : WMI_TKIP_CM_DISABLE;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_TKIP_COUNTERMEASURES_CMDID,
+            NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_akmp_params_cmd(struct wmi_t *wmip,
+                        WMI_SET_AKMP_PARAMS_CMD *akmpParams)
+{
+    void *osbuf;
+    WMI_SET_AKMP_PARAMS_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+    cmd = (WMI_SET_AKMP_PARAMS_CMD *)(A_NETBUF_DATA(osbuf));
+    cmd->akmpInfo = akmpParams->akmpInfo;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_AKMP_PARAMS_CMDID,
+            NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_pmkid_list_cmd(struct wmi_t *wmip,
+                       WMI_SET_PMKID_LIST_CMD *pmkInfo)
+{
+    void *osbuf;
+    WMI_SET_PMKID_LIST_CMD *cmd;
+    A_UINT16 cmdLen;
+    A_UINT8 i;
+
+    cmdLen = sizeof(pmkInfo->numPMKID) +
+             pmkInfo->numPMKID * sizeof(WMI_PMKID);
+
+    osbuf = A_NETBUF_ALLOC(cmdLen);
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, cmdLen);
+    cmd = (WMI_SET_PMKID_LIST_CMD *)(A_NETBUF_DATA(osbuf));
+    cmd->numPMKID = pmkInfo->numPMKID;
+
+    for (i = 0; i < cmd->numPMKID; i++) {
+        A_MEMCPY(&cmd->pmkidList[i], &pmkInfo->pmkidList[i],
+                 WMI_PMKID_LEN);
+    }
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_PMKID_LIST_CMDID,
+            NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_get_pmkid_list_cmd(struct wmi_t *wmip)
+{
+    return wmi_simple_cmd(wmip, WMI_GET_PMKID_LIST_CMDID);
+}
+
+A_STATUS
+wmi_dataSync_send(struct wmi_t *wmip, void *osbuf, HTC_ENDPOINT_ID eid)
+{
+    WMI_DATA_HDR     *dtHdr;
+
+    A_ASSERT( eid != wmip->wmi_endpoint_id);
+    A_ASSERT(osbuf != NULL);
+
+    if (A_NETBUF_PUSH(osbuf, sizeof(WMI_DATA_HDR)) != A_OK) {
+        return A_NO_MEMORY;
+    }
+
+    dtHdr = (WMI_DATA_HDR *)A_NETBUF_DATA(osbuf);
+    dtHdr->info =
+      (SYNC_MSGTYPE & WMI_DATA_HDR_MSG_TYPE_MASK) << WMI_DATA_HDR_MSG_TYPE_SHIFT;
+
+    A_DPRINTF(DBG_WMI, (DBGFMT "Enter - eid %d\n", DBGARG, eid));
+
+    return (A_WMI_CONTROL_TX(wmip->wmi_devt, osbuf, eid));
+}
+
+typedef struct _WMI_DATA_SYNC_BUFS {
+    A_UINT8            trafficClass;
+    void               *osbuf;
+}WMI_DATA_SYNC_BUFS;
+
+static A_STATUS
+wmi_sync_point(struct wmi_t *wmip)
+{
+    void *cmd_osbuf;
+    WMI_SYNC_CMD *cmd;
+    WMI_DATA_SYNC_BUFS dataSyncBufs[WMM_NUM_AC];
+    A_UINT8 i,numPriStreams=0;
+    A_STATUS status = A_OK;
+
+    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+    memset(dataSyncBufs,0,sizeof(dataSyncBufs));
+
+    /* lock out while we walk through the priority list and assemble our local array */
+    LOCK_WMI(wmip);
+
+    for (i=0; i < WMM_NUM_AC ; i++) {
+        if (wmip->wmi_fatPipeExists & (1 << i)) {
+            numPriStreams++;
+            dataSyncBufs[numPriStreams-1].trafficClass = i;
+        }
+    }
+
+    UNLOCK_WMI(wmip);
+
+    /* dataSyncBufs is now filled with entries (starting at index 0) containing valid streamIDs */
+
+    do {
+        /*
+         * We allocate all network buffers needed so we will be able to
+         * send all required frames.
+         */
+        cmd_osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+        if (cmd_osbuf == NULL) {
+            status = A_NO_MEMORY;
+            break;
+    }
+
+        A_NETBUF_PUT(cmd_osbuf, sizeof(*cmd));
+
+        cmd = (WMI_SYNC_CMD *)(A_NETBUF_DATA(cmd_osbuf));
+        A_MEMZERO(cmd, sizeof(*cmd));
+
+        /* In the SYNC cmd sent on the control Ep, send a bitmap of the data
+         * eps on which the Data Sync will be sent
+         */
+        cmd->dataSyncMap = wmip->wmi_fatPipeExists;
+
+        for (i=0; i < numPriStreams ; i++) {
+            dataSyncBufs[i].osbuf = A_NETBUF_ALLOC(0);
+            if (dataSyncBufs[i].osbuf == NULL) {
+                status = A_NO_MEMORY;
+                break;
+            }
+        } //end for
+
+        /* if Buffer allocation for any of the dataSync fails, then do not
+         * send the Synchronize cmd on the control ep
+         */
+        if (A_FAILED(status)) {
+            break;
+        }
+
+    /*
+     * Send sync cmd followed by sync data messages on all endpoints being
+     * used
+     */
+    status = wmi_cmd_send(wmip, cmd_osbuf, WMI_SYNCHRONIZE_CMDID,
+                          NO_SYNC_WMIFLAG);
+
+        if (A_FAILED(status)) {
+            break;
+    }
+            /* cmd buffer sent, we no longer own it */
+        cmd_osbuf = NULL;
+
+        for(i=0; i < numPriStreams; i++) {
+            A_ASSERT(dataSyncBufs[i].osbuf != NULL);
+            status = wmi_dataSync_send(wmip,
+                                       dataSyncBufs[i].osbuf,
+                                       A_WMI_Ac2EndpointID(wmip->wmi_devt,
+                                                            dataSyncBufs[i].
+                                                            trafficClass)
+                                      );
+
+            if (A_FAILED(status)) {
+                break;
+            }
+            /* we don't own this buffer anymore, NULL it out of the array so it
+             * won't get cleaned up */
+            dataSyncBufs[i].osbuf = NULL;
+        } //end for
+
+    } while(FALSE);
+
+    /* free up any resources left over (possibly due to an error) */
+
+    if (cmd_osbuf != NULL) {
+        A_NETBUF_FREE(cmd_osbuf);
+            }
+
+    for (i = 0; i < numPriStreams; i++) {
+        if (dataSyncBufs[i].osbuf != NULL) {
+            A_NETBUF_FREE(dataSyncBufs[i].osbuf);
+        }
+    }
+
+    return (status);
+}
+
+A_STATUS
+wmi_create_pstream_cmd(struct wmi_t *wmip, WMI_CREATE_PSTREAM_CMD *params)
+{
+    void *osbuf;
+    WMI_CREATE_PSTREAM_CMD *cmd;
+    A_UINT8 fatPipeExistsForAC=0;
+    A_INT32 minimalPHY = 0;
+    A_INT32 nominalPHY = 0;
+
+    /* Validate all the parameters. */
+    if( !((params->userPriority < 8) &&
+         (params->userPriority <= 0x7) &&
+         (convert_userPriority_to_trafficClass(params->userPriority) == params->trafficClass)  &&
+         (params->trafficDirection == UPLINK_TRAFFIC ||
+            params->trafficDirection == DNLINK_TRAFFIC ||
+            params->trafficDirection == BIDIR_TRAFFIC) &&
+         (params->trafficType == TRAFFIC_TYPE_APERIODIC ||
+            params->trafficType == TRAFFIC_TYPE_PERIODIC ) &&
+         (params->voicePSCapability == DISABLE_FOR_THIS_AC  ||
+            params->voicePSCapability == ENABLE_FOR_THIS_AC ||
+            params->voicePSCapability == ENABLE_FOR_ALL_AC) &&
+         (params->tsid == WMI_IMPLICIT_PSTREAM || params->tsid <= WMI_MAX_THINSTREAM)) )
+    {
+        return  A_EINVAL;
+    }
+
+    //
+    // check nominal PHY rate is >= minimalPHY, so that DUT
+    // can allow TSRS IE
+    //
+
+    // get the physical rate
+    minimalPHY = ((params->minPhyRate / 1000)/1000); // unit of bps
+
+    // check minimal phy < nominal phy rate
+    //
+    if (params->nominalPHY >= minimalPHY)
+    {
+        nominalPHY = (params->nominalPHY * 1000)/500; // unit of 500 kbps
+        A_DPRINTF(DBG_WMI,
+                  (DBGFMT "TSRS IE Enabled::MinPhy %x->NominalPhy ===> %x\n", DBGARG,
+                  minimalPHY, nominalPHY));
+
+        params->nominalPHY = nominalPHY;
+    }
+    else
+    {
+        params->nominalPHY = 0;
+    }
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    A_DPRINTF(DBG_WMI,
+        (DBGFMT "Sending create_pstream_cmd: ac=%d    tsid:%d\n", DBGARG,
+        params->trafficClass, params->tsid));
+
+    cmd = (WMI_CREATE_PSTREAM_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+    A_MEMCPY(cmd, params, sizeof(*cmd));
+
+        /* this is an implicitly created Fat pipe */
+    if ((A_UINT32)params->tsid == (A_UINT32)WMI_IMPLICIT_PSTREAM) {
+        LOCK_WMI(wmip);
+        fatPipeExistsForAC = (wmip->wmi_fatPipeExists & (1 << params->trafficClass));
+        wmip->wmi_fatPipeExists |= (1<<params->trafficClass);
+        UNLOCK_WMI(wmip);
+    } else {
+            /* this is an explicitly created thin stream within a fat pipe */
+    LOCK_WMI(wmip);
+        fatPipeExistsForAC = (wmip->wmi_fatPipeExists & (1 << params->trafficClass));
+    wmip->wmi_streamExistsForAC[params->trafficClass] |= (1<<params->tsid);
+            /* if a thinstream becomes active, the fat pipe automatically
+            * becomes active
+            */
+        wmip->wmi_fatPipeExists |= (1<<params->trafficClass);
+    UNLOCK_WMI(wmip);
+    }
+
+        /* Indicate activty change to driver layer only if this is the
+         * first TSID to get created in this AC explicitly or an implicit
+         * fat pipe is getting created.
+         */
+    if (!fatPipeExistsForAC) {
+        A_WMI_STREAM_TX_ACTIVE(wmip->wmi_devt, params->trafficClass);
+    }
+
+    /* mike: should be SYNC_BEFORE_WMIFLAG */
+    return (wmi_cmd_send(wmip, osbuf, WMI_CREATE_PSTREAM_CMDID,
+                         NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_delete_pstream_cmd(struct wmi_t *wmip, A_UINT8 trafficClass, A_UINT8 tsid)
+{
+    void *osbuf;
+    WMI_DELETE_PSTREAM_CMD *cmd;
+    A_STATUS status;
+    A_UINT16 activeTsids=0;
+
+    /* validate the parameters */
+    if (trafficClass > 3) {
+        A_DPRINTF(DBG_WMI, (DBGFMT "Invalid trafficClass: %d\n", DBGARG, trafficClass));
+        return A_EINVAL;
+    }
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_DELETE_PSTREAM_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+
+    cmd->trafficClass = trafficClass;
+    cmd->tsid = tsid;
+
+    LOCK_WMI(wmip);
+    activeTsids = wmip->wmi_streamExistsForAC[trafficClass];
+    UNLOCK_WMI(wmip);
+
+        /* Check if the tsid was created & exists */
+    if (!(activeTsids & (1<<tsid))) {
+
+        A_NETBUF_FREE(osbuf);
+        A_DPRINTF(DBG_WMI,
+        (DBGFMT "TSID %d does'nt exist for trafficClass: %d\n", DBGARG, tsid, trafficClass));
+            /* TODO: return a more appropriate err code */
+        return A_ERROR;
+    }
+
+    A_DPRINTF(DBG_WMI,
+        (DBGFMT "Sending delete_pstream_cmd: trafficClass: %d tsid=%d\n", DBGARG, trafficClass, tsid));
+
+    status = (wmi_cmd_send(wmip, osbuf, WMI_DELETE_PSTREAM_CMDID,
+                         SYNC_BEFORE_WMIFLAG));
+
+    LOCK_WMI(wmip);
+    wmip->wmi_streamExistsForAC[trafficClass] &= ~(1<<tsid);
+    activeTsids = wmip->wmi_streamExistsForAC[trafficClass];
+    UNLOCK_WMI(wmip);
+
+
+        /* Indicate stream inactivity to driver layer only if all tsids
+         * within this AC are deleted.
+         */
+    if(!activeTsids) {
+        A_WMI_STREAM_TX_INACTIVE(wmip->wmi_devt, trafficClass);
+        wmip->wmi_fatPipeExists &= ~(1<<trafficClass);
+    }
+
+    return status;
+}
+
+A_STATUS
+wmi_set_framerate_cmd(struct wmi_t *wmip, A_UINT8 bEnable, A_UINT8 type, A_UINT8 subType, A_UINT16 rateMask)
+{
+    void *osbuf;
+    WMI_FRAME_RATES_CMD *cmd;
+    A_UINT8 frameType;
+
+    A_DPRINTF(DBG_WMI,
+        (DBGFMT " type %02X, subType %02X, rateMask %04x\n", DBGARG, type, subType, rateMask));
+
+    if((type != IEEE80211_FRAME_TYPE_MGT && type != IEEE80211_FRAME_TYPE_CTL) ||
+        (subType > 15)){
+
+        return A_EINVAL;
+    }
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_FRAME_RATES_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+
+    frameType = (A_UINT8)((subType << 4) | type);
+
+    cmd->bEnableMask = bEnable;
+    cmd->frameType = frameType;
+    cmd->frameRateMask = rateMask;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_FRAMERATES_CMDID, NO_SYNC_WMIFLAG));
+}
+
+/*
+ * used to set the bit rate.  rate is in Kbps.  If rate == -1
+ * then auto selection is used.
+ */
+A_STATUS
+wmi_set_bitrate_cmd(struct wmi_t *wmip, A_INT32 dataRate, A_INT32 mgmtRate, A_INT32 ctlRate)
+{
+    void *osbuf;
+    WMI_BIT_RATE_CMD *cmd;
+    A_INT8 drix, mrix, crix, ret_val;
+
+    if (dataRate != -1) {
+        ret_val = wmi_validate_bitrate(wmip, dataRate, &drix);
+        if(ret_val == A_EINVAL){
+            return A_EINVAL;
+        }
+    } else {
+        drix = -1;
+    }
+
+    if (mgmtRate != -1) {
+        ret_val = wmi_validate_bitrate(wmip, mgmtRate, &mrix);
+        if(ret_val == A_EINVAL){
+            return A_EINVAL;
+        }
+    } else {
+        mrix = -1;
+    }
+    if (ctlRate != -1) {
+        ret_val = wmi_validate_bitrate(wmip, ctlRate, &crix);
+        if(ret_val == A_EINVAL){
+            return A_EINVAL;
+        }
+    } else {
+        crix = -1;
+    }
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_BIT_RATE_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+
+    cmd->rateIndex = drix;
+    cmd->mgmtRateIndex = mrix;
+    cmd->ctlRateIndex  = crix;
+
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_BITRATE_CMDID, NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_get_bitrate_cmd(struct wmi_t *wmip)
+{
+    return wmi_simple_cmd(wmip, WMI_GET_BITRATE_CMDID);
+}
+
+/*
+ * Returns TRUE iff the given rate index is legal in the current PHY mode.
+ */
+A_BOOL
+wmi_is_bitrate_index_valid(struct wmi_t *wmip, A_INT32 rateIndex)
+{
+    WMI_PHY_MODE phyMode = (WMI_PHY_MODE) wmip->wmi_phyMode;
+    A_BOOL isValid = TRUE;
+    switch(phyMode) {
+        case WMI_11A_MODE:
+            if (wmip->wmi_ht_allowed[A_BAND_5GHZ]){
+                if ((rateIndex < MODE_A_SUPPORT_RATE_START) || (rateIndex > MODE_GHT20_SUPPORT_RATE_STOP)) {
+                    isValid = FALSE;
+                }
+            } else {
+                if ((rateIndex < MODE_A_SUPPORT_RATE_START) || (rateIndex > MODE_A_SUPPORT_RATE_STOP)) {
+                    isValid = FALSE;
+                }
+            }
+            break;
+
+        case WMI_11B_MODE:
+            if ((rateIndex < MODE_B_SUPPORT_RATE_START) || (rateIndex > MODE_B_SUPPORT_RATE_STOP)) {
+                isValid = FALSE;
+            }
+            break;
+
+        case WMI_11GONLY_MODE:
+            if (wmip->wmi_ht_allowed[A_BAND_24GHZ]){
+                if ((rateIndex < MODE_GONLY_SUPPORT_RATE_START) || (rateIndex > MODE_GHT20_SUPPORT_RATE_STOP)) {
+                    isValid = FALSE;
+                }
+            } else {
+                if ((rateIndex < MODE_GONLY_SUPPORT_RATE_START) || (rateIndex > MODE_GONLY_SUPPORT_RATE_STOP)) {
+                    isValid = FALSE;
+                }
+            }
+            break;
+
+        case WMI_11G_MODE:
+        case WMI_11AG_MODE:
+            if (wmip->wmi_ht_allowed[A_BAND_24GHZ]){
+                if ((rateIndex < MODE_G_SUPPORT_RATE_START) || (rateIndex > MODE_GHT20_SUPPORT_RATE_STOP)) {
+                    isValid = FALSE;
+                }
+            } else {
+                if ((rateIndex < MODE_G_SUPPORT_RATE_START) || (rateIndex > MODE_G_SUPPORT_RATE_STOP)) {
+                    isValid = FALSE;
+                }
+            }
+            break;
+        default:
+            A_ASSERT(FALSE);
+            break;
+    }
+
+    return isValid;
+}
+
+A_INT8
+wmi_validate_bitrate(struct wmi_t *wmip, A_INT32 rate, A_INT8 *rate_idx)
+{
+    A_INT8 i;
+
+    for (i=0;;i++)
+    {
+        if (wmi_rateTable[(A_UINT32) i][0] == 0) {
+            return A_EINVAL;
+        }
+        if (wmi_rateTable[(A_UINT32) i][0] == rate) {
+            break;
+        }
+    }
+
+    if(wmi_is_bitrate_index_valid(wmip, (A_INT32) i) != TRUE) {
+        return A_EINVAL;
+    }
+
+    *rate_idx = i;
+    return A_OK;
+}
+
+A_STATUS
+wmi_set_fixrates_cmd(struct wmi_t *wmip, A_UINT32 fixRatesMask)
+{
+    void *osbuf;
+    WMI_FIX_RATES_CMD *cmd;
+#if 0
+    A_INT32 rateIndex;
+/* This check does not work for AR6003 as the HT modes are enabled only when
+ * the STA is connected to a HT_BSS and is not based only on channel. It is
+ * safe to skip this check however because rate control will only use rates
+ * that are permitted by the valid rate mask and the fix rate mask. Meaning
+ * the fix rate mask is not sufficient by itself to cause an invalid rate
+ * to be used. */
+    /* Make sure all rates in the mask are valid in the current PHY mode */
+    for(rateIndex = 0; rateIndex < MAX_NUMBER_OF_SUPPORT_RATES; rateIndex++) {
+       if((1 << rateIndex) & (A_UINT32)fixRatesMask) {
+            if(wmi_is_bitrate_index_valid(wmip, rateIndex) != TRUE) {
+                A_DPRINTF(DBG_WMI, (DBGFMT "Set Fix Rates command failed: Given rate is illegal in current PHY mode\n", DBGARG));
+                return A_EINVAL;
+            }
+       }
+    }
+#endif
+
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_FIX_RATES_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+
+    cmd->fixRateMask = fixRatesMask;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_FIXRATES_CMDID, NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_get_ratemask_cmd(struct wmi_t *wmip)
+{
+    return wmi_simple_cmd(wmip, WMI_GET_FIXRATES_CMDID);
+}
+
+A_STATUS
+wmi_get_channelList_cmd(struct wmi_t *wmip)
+{
+    return wmi_simple_cmd(wmip, WMI_GET_CHANNEL_LIST_CMDID);
+}
+
+/*
+ * used to generate a wmi sey channel Parameters cmd.
+ * mode should always be specified and corresponds to the phy mode of the
+ * wlan.
+ * numChan should alway sbe specified. If zero indicates that all available
+ * channels should be used.
+ * channelList is an array of channel frequencies (in Mhz) which the radio
+ * should limit its operation to.  It should be NULL if numChan == 0.  Size of
+ * array should correspond to numChan entries.
+ */
+A_STATUS
+wmi_set_channelParams_cmd(struct wmi_t *wmip, A_UINT8 scanParam,
+                          WMI_PHY_MODE mode, A_INT8 numChan,
+                          A_UINT16 *channelList)
+{
+    void *osbuf;
+    WMI_CHANNEL_PARAMS_CMD *cmd;
+    A_INT8 size;
+
+    size = sizeof (*cmd);
+
+    if (numChan) {
+        if (numChan > WMI_MAX_CHANNELS) {
+            return A_EINVAL;
+        }
+        size += sizeof(A_UINT16) * (numChan - 1);
+    }
+
+    osbuf = A_NETBUF_ALLOC(size);
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, size);
+
+    cmd = (WMI_CHANNEL_PARAMS_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, size);
+
+    wmip->wmi_phyMode = mode;
+    cmd->scanParam   = scanParam;
+    cmd->phyMode     = mode;
+    cmd->numChannels = numChan;
+    A_MEMCPY(cmd->channelList, channelList, numChan * sizeof(A_UINT16));
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_CHANNEL_PARAMS_CMDID,
+                         NO_SYNC_WMIFLAG));
+}
+
+void
+wmi_cache_configure_rssithreshold(struct wmi_t *wmip, WMI_RSSI_THRESHOLD_PARAMS_CMD *rssiCmd)
+{
+    SQ_THRESHOLD_PARAMS *sq_thresh =
+           &wmip->wmi_SqThresholdParams[SIGNAL_QUALITY_METRICS_RSSI];
+    /*
+     * Parse the command and store the threshold values here. The checks
+     * for valid values can be put here
+     */
+    sq_thresh->weight = rssiCmd->weight;
+    sq_thresh->polling_interval = rssiCmd->pollTime;
+
+    sq_thresh->upper_threshold[0] = rssiCmd->thresholdAbove1_Val - SIGNAL_QUALITY_NOISE_FLOOR;
+    sq_thresh->upper_threshold[1] = rssiCmd->thresholdAbove2_Val - SIGNAL_QUALITY_NOISE_FLOOR;
+    sq_thresh->upper_threshold[2] = rssiCmd->thresholdAbove3_Val - SIGNAL_QUALITY_NOISE_FLOOR;
+    sq_thresh->upper_threshold[3] = rssiCmd->thresholdAbove4_Val - SIGNAL_QUALITY_NOISE_FLOOR;
+    sq_thresh->upper_threshold[4] = rssiCmd->thresholdAbove5_Val - SIGNAL_QUALITY_NOISE_FLOOR;
+    sq_thresh->upper_threshold[5] = rssiCmd->thresholdAbove6_Val - SIGNAL_QUALITY_NOISE_FLOOR;
+    sq_thresh->upper_threshold_valid_count = 6;
+
+    /* List sorted in descending order */
+    sq_thresh->lower_threshold[0] = rssiCmd->thresholdBelow6_Val - SIGNAL_QUALITY_NOISE_FLOOR;
+    sq_thresh->lower_threshold[1] = rssiCmd->thresholdBelow5_Val - SIGNAL_QUALITY_NOISE_FLOOR;
+    sq_thresh->lower_threshold[2] = rssiCmd->thresholdBelow4_Val - SIGNAL_QUALITY_NOISE_FLOOR;
+    sq_thresh->lower_threshold[3] = rssiCmd->thresholdBelow3_Val - SIGNAL_QUALITY_NOISE_FLOOR;
+    sq_thresh->lower_threshold[4] = rssiCmd->thresholdBelow2_Val - SIGNAL_QUALITY_NOISE_FLOOR;
+    sq_thresh->lower_threshold[5] = rssiCmd->thresholdBelow1_Val - SIGNAL_QUALITY_NOISE_FLOOR;
+    sq_thresh->lower_threshold_valid_count = 6;
+
+    if (!rssi_event_value) {
+    /*
+     * Configuring the thresholds to their extremes allows the host to get an
+     * event from the target which is used for the configuring the correct
+     * thresholds
+     */
+    rssiCmd->thresholdAbove1_Val = sq_thresh->upper_threshold[0];
+    rssiCmd->thresholdBelow1_Val = sq_thresh->lower_threshold[0];
+    } else {
+        /*
+         * In case the user issues multiple times of rssi_threshold_setting,
+         * we should not use the extreames anymore, the target does not expect that.
+         */
+        rssiCmd->thresholdAbove1_Val = ar6000_get_upper_threshold(rssi_event_value, sq_thresh,
+                                              sq_thresh->upper_threshold_valid_count);
+        rssiCmd->thresholdBelow1_Val = ar6000_get_lower_threshold(rssi_event_value, sq_thresh,
+                                              sq_thresh->lower_threshold_valid_count);
+}
+}
+
+A_STATUS
+wmi_set_rssi_threshold_params(struct wmi_t *wmip,
+                              WMI_RSSI_THRESHOLD_PARAMS_CMD *rssiCmd)
+{
+
+     /* Check these values are in ascending order */
+    if( rssiCmd->thresholdAbove6_Val <= rssiCmd->thresholdAbove5_Val ||
+        rssiCmd->thresholdAbove5_Val <= rssiCmd->thresholdAbove4_Val ||
+        rssiCmd->thresholdAbove4_Val <= rssiCmd->thresholdAbove3_Val ||
+        rssiCmd->thresholdAbove3_Val <= rssiCmd->thresholdAbove2_Val ||
+        rssiCmd->thresholdAbove2_Val <= rssiCmd->thresholdAbove1_Val ||
+        rssiCmd->thresholdBelow6_Val <= rssiCmd->thresholdBelow5_Val ||
+        rssiCmd->thresholdBelow5_Val <= rssiCmd->thresholdBelow4_Val ||
+        rssiCmd->thresholdBelow4_Val <= rssiCmd->thresholdBelow3_Val ||
+        rssiCmd->thresholdBelow3_Val <= rssiCmd->thresholdBelow2_Val ||
+        rssiCmd->thresholdBelow2_Val <= rssiCmd->thresholdBelow1_Val)
+    {
+        return A_EINVAL;
+    }
+
+    wmi_cache_configure_rssithreshold(wmip, rssiCmd);
+
+    return (wmi_send_rssi_threshold_params(wmip, rssiCmd));
+}
+
+A_STATUS
+wmi_set_ip_cmd(struct wmi_t *wmip, WMI_SET_IP_CMD *ipCmd)
+{
+    void    *osbuf;
+    WMI_SET_IP_CMD *cmd;
+
+    /* Multicast address are not valid */
+    if((*((A_UINT8*)&ipCmd->ips[0]) >= 0xE0) ||
+       (*((A_UINT8*)&ipCmd->ips[1]) >= 0xE0)) {
+        return A_EINVAL;
+    }
+
+    osbuf = A_NETBUF_ALLOC(sizeof(WMI_SET_IP_CMD));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(WMI_SET_IP_CMD));
+    cmd = (WMI_SET_IP_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMCPY(cmd, ipCmd, sizeof(WMI_SET_IP_CMD));
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_IP_CMDID,
+                            NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_host_sleep_mode_cmd(struct wmi_t *wmip,
+                              WMI_SET_HOST_SLEEP_MODE_CMD *hostModeCmd)
+{
+    void    *osbuf;
+    A_INT8  size;
+    WMI_SET_HOST_SLEEP_MODE_CMD *cmd;
+    A_UINT16 activeTsids=0;
+    A_UINT8 streamExists=0;
+    A_UINT8 i;
+
+    if( hostModeCmd->awake == hostModeCmd->asleep) {
+        return A_EINVAL;
+    }
+
+    size = sizeof (*cmd);
+
+    osbuf = A_NETBUF_ALLOC(size);
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, size);
+
+    cmd = (WMI_SET_HOST_SLEEP_MODE_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, size);
+    A_MEMCPY(cmd, hostModeCmd, sizeof(WMI_SET_HOST_SLEEP_MODE_CMD));
+
+    if(hostModeCmd->asleep) {
+        /*
+         * Relinquish credits from all implicitly created pstreams since when we
+         * go to sleep. If user created explicit thinstreams exists with in a
+         * fatpipe leave them intact for the user to delete
+         */
+        LOCK_WMI(wmip);
+        streamExists = wmip->wmi_fatPipeExists;
+        UNLOCK_WMI(wmip);
+
+        for(i=0;i< WMM_NUM_AC;i++) {
+            if (streamExists & (1<<i)) {
+                LOCK_WMI(wmip);
+                activeTsids = wmip->wmi_streamExistsForAC[i];
+                UNLOCK_WMI(wmip);
+                /* If there are no user created thin streams delete the fatpipe */
+                if(!activeTsids) {
+                    streamExists &= ~(1<<i);
+                    /*Indicate inactivity to drv layer for this fatpipe(pstream)*/
+                    A_WMI_STREAM_TX_INACTIVE(wmip->wmi_devt,i);
+                }
+            }
+        }
+
+        /* Update the fatpipes that exists*/
+        LOCK_WMI(wmip);
+        wmip->wmi_fatPipeExists = streamExists;
+        UNLOCK_WMI(wmip);
+    }
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_HOST_SLEEP_MODE_CMDID,
+                            NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_wow_mode_cmd(struct wmi_t *wmip,
+                              WMI_SET_WOW_MODE_CMD *wowModeCmd)
+{
+    void    *osbuf;
+    A_INT8  size;
+    WMI_SET_WOW_MODE_CMD *cmd;
+
+    size = sizeof (*cmd);
+
+    osbuf = A_NETBUF_ALLOC(size);
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, size);
+
+    cmd = (WMI_SET_WOW_MODE_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, size);
+    A_MEMCPY(cmd, wowModeCmd, sizeof(WMI_SET_WOW_MODE_CMD));
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_WOW_MODE_CMDID,
+                            NO_SYNC_WMIFLAG));
+
+}
+
+A_STATUS
+wmi_get_wow_list_cmd(struct wmi_t *wmip,
+                              WMI_GET_WOW_LIST_CMD *wowListCmd)
+{
+    void    *osbuf;
+    A_INT8  size;
+    WMI_GET_WOW_LIST_CMD *cmd;
+
+    size = sizeof (*cmd);
+
+    osbuf = A_NETBUF_ALLOC(size);
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, size);
+
+    cmd = (WMI_GET_WOW_LIST_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, size);
+    A_MEMCPY(cmd, wowListCmd, sizeof(WMI_GET_WOW_LIST_CMD));
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_GET_WOW_LIST_CMDID,
+                            NO_SYNC_WMIFLAG));
+
+}
+
+static A_STATUS
+wmi_get_wow_list_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMI_GET_WOW_LIST_REPLY *reply;
+
+    if (len < sizeof(WMI_GET_WOW_LIST_REPLY)) {
+        return A_EINVAL;
+    }
+    reply = (WMI_GET_WOW_LIST_REPLY *)datap;
+
+    A_WMI_WOW_LIST_EVENT(wmip->wmi_devt, reply->num_filters,
+                          reply);
+
+    return A_OK;
+}
+
+A_STATUS wmi_add_wow_pattern_cmd(struct wmi_t *wmip,
+                                 WMI_ADD_WOW_PATTERN_CMD *addWowCmd,
+                                 A_UINT8* pattern, A_UINT8* mask,
+                                 A_UINT8 pattern_size)
+{
+    void    *osbuf;
+    A_INT8  size;
+    WMI_ADD_WOW_PATTERN_CMD *cmd;
+    A_UINT8 *filter_mask = NULL;
+
+    size = sizeof (*cmd);
+
+    size += ((2 * addWowCmd->filter_size)* sizeof(A_UINT8));
+    osbuf = A_NETBUF_ALLOC(size);
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, size);
+
+    cmd = (WMI_ADD_WOW_PATTERN_CMD *)(A_NETBUF_DATA(osbuf));
+    cmd->filter_list_id = addWowCmd->filter_list_id;
+    cmd->filter_offset = addWowCmd->filter_offset;
+    cmd->filter_size = addWowCmd->filter_size;
+
+    A_MEMCPY(cmd->filter, pattern, addWowCmd->filter_size);
+
+    filter_mask = (A_UINT8*)(cmd->filter + cmd->filter_size);
+    A_MEMCPY(filter_mask, mask, addWowCmd->filter_size);
+
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_ADD_WOW_PATTERN_CMDID,
+                            NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_del_wow_pattern_cmd(struct wmi_t *wmip,
+                              WMI_DEL_WOW_PATTERN_CMD *delWowCmd)
+{
+    void    *osbuf;
+    A_INT8  size;
+    WMI_DEL_WOW_PATTERN_CMD *cmd;
+
+    size = sizeof (*cmd);
+
+    osbuf = A_NETBUF_ALLOC(size);
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, size);
+
+    cmd = (WMI_DEL_WOW_PATTERN_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, size);
+    A_MEMCPY(cmd, delWowCmd, sizeof(WMI_DEL_WOW_PATTERN_CMD));
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_DEL_WOW_PATTERN_CMDID,
+                            NO_SYNC_WMIFLAG));
+
+}
+
+void
+wmi_cache_configure_snrthreshold(struct wmi_t *wmip, WMI_SNR_THRESHOLD_PARAMS_CMD *snrCmd)
+{
+    SQ_THRESHOLD_PARAMS *sq_thresh =
+           &wmip->wmi_SqThresholdParams[SIGNAL_QUALITY_METRICS_SNR];
+    /*
+     * Parse the command and store the threshold values here. The checks
+     * for valid values can be put here
+     */
+    sq_thresh->weight = snrCmd->weight;
+    sq_thresh->polling_interval = snrCmd->pollTime;
+
+    sq_thresh->upper_threshold[0] = snrCmd->thresholdAbove1_Val;
+    sq_thresh->upper_threshold[1] = snrCmd->thresholdAbove2_Val;
+    sq_thresh->upper_threshold[2] = snrCmd->thresholdAbove3_Val;
+    sq_thresh->upper_threshold[3] = snrCmd->thresholdAbove4_Val;
+    sq_thresh->upper_threshold_valid_count = 4;
+
+    /* List sorted in descending order */
+    sq_thresh->lower_threshold[0] = snrCmd->thresholdBelow4_Val;
+    sq_thresh->lower_threshold[1] = snrCmd->thresholdBelow3_Val;
+    sq_thresh->lower_threshold[2] = snrCmd->thresholdBelow2_Val;
+    sq_thresh->lower_threshold[3] = snrCmd->thresholdBelow1_Val;
+    sq_thresh->lower_threshold_valid_count = 4;
+
+    if (!snr_event_value) {
+    /*
+     * Configuring the thresholds to their extremes allows the host to get an
+     * event from the target which is used for the configuring the correct
+     * thresholds
+     */
+    snrCmd->thresholdAbove1_Val = (A_UINT8)sq_thresh->upper_threshold[0];
+    snrCmd->thresholdBelow1_Val = (A_UINT8)sq_thresh->lower_threshold[0];
+    } else {
+        /*
+         * In case the user issues multiple times of snr_threshold_setting,
+         * we should not use the extreames anymore, the target does not expect that.
+         */
+        snrCmd->thresholdAbove1_Val = ar6000_get_upper_threshold(snr_event_value, sq_thresh,
+                                              sq_thresh->upper_threshold_valid_count);
+        snrCmd->thresholdBelow1_Val = ar6000_get_lower_threshold(snr_event_value, sq_thresh,
+                                              sq_thresh->lower_threshold_valid_count);
+    }
+
+}
+A_STATUS
+wmi_set_snr_threshold_params(struct wmi_t *wmip,
+                             WMI_SNR_THRESHOLD_PARAMS_CMD *snrCmd)
+{
+    if( snrCmd->thresholdAbove4_Val <= snrCmd->thresholdAbove3_Val ||
+        snrCmd->thresholdAbove3_Val <= snrCmd->thresholdAbove2_Val ||
+        snrCmd->thresholdAbove2_Val <= snrCmd->thresholdAbove1_Val ||
+        snrCmd->thresholdBelow4_Val <= snrCmd->thresholdBelow3_Val ||
+        snrCmd->thresholdBelow3_Val <= snrCmd->thresholdBelow2_Val ||
+        snrCmd->thresholdBelow2_Val <= snrCmd->thresholdBelow1_Val)
+    {
+        return A_EINVAL;
+    }
+    wmi_cache_configure_snrthreshold(wmip, snrCmd);
+    return (wmi_send_snr_threshold_params(wmip, snrCmd));
+}
+
+A_STATUS
+wmi_clr_rssi_snr(struct wmi_t *wmip)
+{
+    void    *osbuf;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(int));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_CLR_RSSI_SNR_CMDID,
+                            NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_lq_threshold_params(struct wmi_t *wmip,
+                             WMI_LQ_THRESHOLD_PARAMS_CMD *lqCmd)
+{
+    void    *osbuf;
+    A_INT8  size;
+    WMI_LQ_THRESHOLD_PARAMS_CMD *cmd;
+    /* These values are in ascending order */
+    if( lqCmd->thresholdAbove4_Val <= lqCmd->thresholdAbove3_Val ||
+        lqCmd->thresholdAbove3_Val <= lqCmd->thresholdAbove2_Val ||
+        lqCmd->thresholdAbove2_Val <= lqCmd->thresholdAbove1_Val ||
+        lqCmd->thresholdBelow4_Val <= lqCmd->thresholdBelow3_Val ||
+        lqCmd->thresholdBelow3_Val <= lqCmd->thresholdBelow2_Val ||
+        lqCmd->thresholdBelow2_Val <= lqCmd->thresholdBelow1_Val ) {
+
+        return A_EINVAL;
+    }
+
+    size = sizeof (*cmd);
+
+    osbuf = A_NETBUF_ALLOC(size);
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, size);
+
+    cmd = (WMI_LQ_THRESHOLD_PARAMS_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, size);
+    A_MEMCPY(cmd, lqCmd, sizeof(WMI_LQ_THRESHOLD_PARAMS_CMD));
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_LQ_THRESHOLD_PARAMS_CMDID,
+                            NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_error_report_bitmask(struct wmi_t *wmip, A_UINT32 mask)
+{
+    void    *osbuf;
+    A_INT8  size;
+    WMI_TARGET_ERROR_REPORT_BITMASK *cmd;
+
+    size = sizeof (*cmd);
+
+    osbuf = A_NETBUF_ALLOC(size);
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, size);
+
+    cmd = (WMI_TARGET_ERROR_REPORT_BITMASK *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, size);
+
+    cmd->bitmask = mask;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_TARGET_ERROR_REPORT_BITMASK_CMDID,
+                            NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_get_challenge_resp_cmd(struct wmi_t *wmip, A_UINT32 cookie, A_UINT32 source)
+{
+    void *osbuf;
+    WMIX_HB_CHALLENGE_RESP_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMIX_HB_CHALLENGE_RESP_CMD *)(A_NETBUF_DATA(osbuf));
+    cmd->cookie = cookie;
+    cmd->source = source;
+
+    return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_HB_CHALLENGE_RESP_CMDID,
+                              NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_config_debug_module_cmd(struct wmi_t *wmip, A_UINT16 mmask,
+                            A_UINT16 tsr, A_BOOL rep, A_UINT16 size,
+                            A_UINT32 valid)
+{
+    void *osbuf;
+    WMIX_DBGLOG_CFG_MODULE_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMIX_DBGLOG_CFG_MODULE_CMD *)(A_NETBUF_DATA(osbuf));
+    cmd->config.cfgmmask = mmask;
+    cmd->config.cfgtsr = tsr;
+    cmd->config.cfgrep = rep;
+    cmd->config.cfgsize = size;
+    cmd->config.cfgvalid = valid;
+
+    return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_DBGLOG_CFG_MODULE_CMDID,
+                              NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_get_stats_cmd(struct wmi_t *wmip)
+{
+    return wmi_simple_cmd(wmip, WMI_GET_STATISTICS_CMDID);
+}
+
+A_STATUS
+wmi_addBadAp_cmd(struct wmi_t *wmip, A_UINT8 apIndex, A_UINT8 *bssid)
+{
+    void *osbuf;
+    WMI_ADD_BAD_AP_CMD *cmd;
+
+    if ((bssid == NULL) || (apIndex > WMI_MAX_BAD_AP_INDEX)) {
+        return A_EINVAL;
+    }
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_ADD_BAD_AP_CMD *)(A_NETBUF_DATA(osbuf));
+    cmd->badApIndex = apIndex;
+    A_MEMCPY(cmd->bssid, bssid, sizeof(cmd->bssid));
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_ADD_BAD_AP_CMDID, SYNC_BEFORE_WMIFLAG));
+}
+
+A_STATUS
+wmi_deleteBadAp_cmd(struct wmi_t *wmip, A_UINT8 apIndex)
+{
+    void *osbuf;
+    WMI_DELETE_BAD_AP_CMD *cmd;
+
+    if (apIndex > WMI_MAX_BAD_AP_INDEX) {
+        return A_EINVAL;
+    }
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_DELETE_BAD_AP_CMD *)(A_NETBUF_DATA(osbuf));
+    cmd->badApIndex = apIndex;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_DELETE_BAD_AP_CMDID,
+                         NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_abort_scan_cmd(struct wmi_t *wmip)
+{
+    return wmi_simple_cmd(wmip, WMI_ABORT_SCAN_CMDID);
+}
+
+A_STATUS
+wmi_set_txPwr_cmd(struct wmi_t *wmip, A_UINT8 dbM)
+{
+    void *osbuf;
+    WMI_SET_TX_PWR_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_SET_TX_PWR_CMD *)(A_NETBUF_DATA(osbuf));
+    cmd->dbM = dbM;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_TX_PWR_CMDID, NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_get_txPwr_cmd(struct wmi_t *wmip)
+{
+    return wmi_simple_cmd(wmip, WMI_GET_TX_PWR_CMDID);
+}
+
+A_UINT16
+wmi_get_mapped_qos_queue(struct wmi_t *wmip, A_UINT8 trafficClass)
+{
+    A_UINT16 activeTsids=0;
+
+    LOCK_WMI(wmip);
+    activeTsids = wmip->wmi_streamExistsForAC[trafficClass];
+    UNLOCK_WMI(wmip);
+
+    return activeTsids;
+}
+
+A_STATUS
+wmi_get_roam_tbl_cmd(struct wmi_t *wmip)
+{
+    return wmi_simple_cmd(wmip, WMI_GET_ROAM_TBL_CMDID);
+}
+
+A_STATUS
+wmi_get_roam_data_cmd(struct wmi_t *wmip, A_UINT8 roamDataType)
+{
+    void *osbuf;
+    A_UINT32 size = sizeof(A_UINT8);
+    WMI_TARGET_ROAM_DATA *cmd;
+
+    osbuf = A_NETBUF_ALLOC(size);      /* no payload */
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, size);
+
+    cmd = (WMI_TARGET_ROAM_DATA *)(A_NETBUF_DATA(osbuf));
+    cmd->roamDataType = roamDataType;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_GET_ROAM_DATA_CMDID,
+                         NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_roam_ctrl_cmd(struct wmi_t *wmip, WMI_SET_ROAM_CTRL_CMD *p,
+                      A_UINT8 size)
+{
+    void *osbuf;
+    WMI_SET_ROAM_CTRL_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(size);
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, size);
+
+    cmd = (WMI_SET_ROAM_CTRL_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, size);
+
+    A_MEMCPY(cmd, p, size);
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_ROAM_CTRL_CMDID,
+                         NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_powersave_timers_cmd(struct wmi_t *wmip,
+                            WMI_POWERSAVE_TIMERS_POLICY_CMD *pCmd,
+                            A_UINT8 size)
+{
+    void *osbuf;
+    WMI_POWERSAVE_TIMERS_POLICY_CMD *cmd;
+
+    /* These timers can't be zero */
+    if(!pCmd->psPollTimeout || !pCmd->triggerTimeout ||
+       !(pCmd->apsdTimPolicy == IGNORE_TIM_ALL_QUEUES_APSD ||
+         pCmd->apsdTimPolicy == PROCESS_TIM_ALL_QUEUES_APSD) ||
+       !(pCmd->simulatedAPSDTimPolicy == IGNORE_TIM_SIMULATED_APSD ||
+         pCmd->simulatedAPSDTimPolicy == PROCESS_TIM_SIMULATED_APSD))
+        return A_EINVAL;
+
+    osbuf = A_NETBUF_ALLOC(size);
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, size);
+
+    cmd = (WMI_POWERSAVE_TIMERS_POLICY_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, size);
+
+    A_MEMCPY(cmd, pCmd, size);
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_POWERSAVE_TIMERS_POLICY_CMDID,
+                         NO_SYNC_WMIFLAG));
+}
+
+#ifdef CONFIG_HOST_GPIO_SUPPORT
+/* Send a command to Target to change GPIO output pins. */
+A_STATUS
+wmi_gpio_output_set(struct wmi_t *wmip,
+                    A_UINT32 set_mask,
+                    A_UINT32 clear_mask,
+                    A_UINT32 enable_mask,
+                    A_UINT32 disable_mask)
+{
+    void *osbuf;
+    WMIX_GPIO_OUTPUT_SET_CMD *output_set;
+    int size;
+
+    size = sizeof(*output_set);
+
+    A_DPRINTF(DBG_WMI,
+        (DBGFMT "Enter - set=0x%x clear=0x%x enb=0x%x dis=0x%x\n", DBGARG,
+        set_mask, clear_mask, enable_mask, disable_mask));
+
+    osbuf = A_NETBUF_ALLOC(size);
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+    A_NETBUF_PUT(osbuf, size);
+    output_set = (WMIX_GPIO_OUTPUT_SET_CMD *)(A_NETBUF_DATA(osbuf));
+
+    output_set->set_mask                   = set_mask;
+    output_set->clear_mask                 = clear_mask;
+    output_set->enable_mask                = enable_mask;
+    output_set->disable_mask               = disable_mask;
+
+    return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_GPIO_OUTPUT_SET_CMDID,
+                             NO_SYNC_WMIFLAG));
+}
+
+/* Send a command to the Target requesting state of the GPIO input pins */
+A_STATUS
+wmi_gpio_input_get(struct wmi_t *wmip)
+{
+    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+    return wmi_simple_cmd_xtnd(wmip, WMIX_GPIO_INPUT_GET_CMDID);
+}
+
+/* Send a command to the Target that changes the value of a GPIO register. */
+A_STATUS
+wmi_gpio_register_set(struct wmi_t *wmip,
+                      A_UINT32 gpioreg_id,
+                      A_UINT32 value)
+{
+    void *osbuf;
+    WMIX_GPIO_REGISTER_SET_CMD *register_set;
+    int size;
+
+    size = sizeof(*register_set);
+
+    A_DPRINTF(DBG_WMI,
+        (DBGFMT "Enter - reg=%d value=0x%x\n", DBGARG, gpioreg_id, value));
+
+    osbuf = A_NETBUF_ALLOC(size);
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+    A_NETBUF_PUT(osbuf, size);
+    register_set = (WMIX_GPIO_REGISTER_SET_CMD *)(A_NETBUF_DATA(osbuf));
+
+    register_set->gpioreg_id               = gpioreg_id;
+    register_set->value                    = value;
+
+    return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_GPIO_REGISTER_SET_CMDID,
+                             NO_SYNC_WMIFLAG));
+}
+
+/* Send a command to the Target to fetch the value of a GPIO register. */
+A_STATUS
+wmi_gpio_register_get(struct wmi_t *wmip,
+                      A_UINT32 gpioreg_id)
+{
+    void *osbuf;
+    WMIX_GPIO_REGISTER_GET_CMD *register_get;
+    int size;
+
+    size = sizeof(*register_get);
+
+    A_DPRINTF(DBG_WMI, (DBGFMT "Enter - reg=%d\n", DBGARG, gpioreg_id));
+
+    osbuf = A_NETBUF_ALLOC(size);
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+    A_NETBUF_PUT(osbuf, size);
+    register_get = (WMIX_GPIO_REGISTER_GET_CMD *)(A_NETBUF_DATA(osbuf));
+
+    register_get->gpioreg_id               = gpioreg_id;
+
+    return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_GPIO_REGISTER_GET_CMDID,
+                             NO_SYNC_WMIFLAG));
+}
+
+/* Send a command to the Target acknowledging some GPIO interrupts. */
+A_STATUS
+wmi_gpio_intr_ack(struct wmi_t *wmip,
+                  A_UINT32 ack_mask)
+{
+    void *osbuf;
+    WMIX_GPIO_INTR_ACK_CMD *intr_ack;
+    int size;
+
+    size = sizeof(*intr_ack);
+
+    A_DPRINTF(DBG_WMI, (DBGFMT "Enter ack_mask=0x%x\n", DBGARG, ack_mask));
+
+    osbuf = A_NETBUF_ALLOC(size);
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+    A_NETBUF_PUT(osbuf, size);
+    intr_ack = (WMIX_GPIO_INTR_ACK_CMD *)(A_NETBUF_DATA(osbuf));
+
+    intr_ack->ack_mask               = ack_mask;
+
+    return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_GPIO_INTR_ACK_CMDID,
+                             NO_SYNC_WMIFLAG));
+}
+#endif /* CONFIG_HOST_GPIO_SUPPORT */
+
+A_STATUS
+wmi_set_access_params_cmd(struct wmi_t *wmip, A_UINT8 ac,  A_UINT16 txop, A_UINT8 eCWmin,
+                          A_UINT8 eCWmax, A_UINT8 aifsn)
+{
+    void *osbuf;
+    WMI_SET_ACCESS_PARAMS_CMD *cmd;
+
+    if ((eCWmin > WMI_MAX_CW_ACPARAM) || (eCWmax > WMI_MAX_CW_ACPARAM) ||
+        (aifsn > WMI_MAX_AIFSN_ACPARAM) || (ac >= WMM_NUM_AC))
+    {
+        return A_EINVAL;
+    }
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_SET_ACCESS_PARAMS_CMD *)(A_NETBUF_DATA(osbuf));
+    cmd->txop   = txop;
+    cmd->eCWmin = eCWmin;
+    cmd->eCWmax = eCWmax;
+    cmd->aifsn  = aifsn;
+    cmd->ac = ac;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_ACCESS_PARAMS_CMDID,
+                         NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_retry_limits_cmd(struct wmi_t *wmip, A_UINT8 frameType,
+                         A_UINT8 trafficClass, A_UINT8 maxRetries,
+                         A_UINT8 enableNotify)
+{
+    void *osbuf;
+    WMI_SET_RETRY_LIMITS_CMD *cmd;
+
+    if ((frameType != MGMT_FRAMETYPE) && (frameType != CONTROL_FRAMETYPE) &&
+        (frameType != DATA_FRAMETYPE))
+    {
+        return A_EINVAL;
+    }
+
+    if (maxRetries > WMI_MAX_RETRIES) {
+        return A_EINVAL;
+    }
+
+    if (frameType != DATA_FRAMETYPE) {
+        trafficClass = 0;
+    }
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_SET_RETRY_LIMITS_CMD *)(A_NETBUF_DATA(osbuf));
+    cmd->frameType    = frameType;
+    cmd->trafficClass = trafficClass;
+    cmd->maxRetries   = maxRetries;
+    cmd->enableNotify = enableNotify;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_RETRY_LIMITS_CMDID,
+                         NO_SYNC_WMIFLAG));
+}
+
+void
+wmi_get_current_bssid(struct wmi_t *wmip, A_UINT8 *bssid)
+{
+    if (bssid != NULL) {
+        A_MEMCPY(bssid, wmip->wmi_bssid, ATH_MAC_LEN);
+    }
+}
+
+A_STATUS
+wmi_set_opt_mode_cmd(struct wmi_t *wmip, A_UINT8 optMode)
+{
+    void *osbuf;
+    WMI_SET_OPT_MODE_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_SET_OPT_MODE_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+    cmd->optMode = optMode;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_OPT_MODE_CMDID,
+                         SYNC_BOTH_WMIFLAG));
+}
+
+A_STATUS
+wmi_opt_tx_frame_cmd(struct wmi_t *wmip,
+                      A_UINT8 frmType,
+                      A_UINT8 *dstMacAddr,
+                      A_UINT8 *bssid,
+                      A_UINT16 optIEDataLen,
+                      A_UINT8 *optIEData)
+{
+    void *osbuf;
+    WMI_OPT_TX_FRAME_CMD *cmd;
+    osbuf = A_NETBUF_ALLOC(optIEDataLen + sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, (optIEDataLen + sizeof(*cmd)));
+
+    cmd = (WMI_OPT_TX_FRAME_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, (optIEDataLen + sizeof(*cmd)-1));
+
+    cmd->frmType    = frmType;
+    cmd->optIEDataLen   = optIEDataLen;
+    //cmd->optIEData     = (A_UINT8 *)((int)cmd + sizeof(*cmd));
+    A_MEMCPY(cmd->bssid, bssid, sizeof(cmd->bssid));
+    A_MEMCPY(cmd->dstAddr, dstMacAddr, sizeof(cmd->dstAddr));
+    A_MEMCPY(&cmd->optIEData[0], optIEData, optIEDataLen);
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_OPT_TX_FRAME_CMDID,
+                         NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_adhoc_bconIntvl_cmd(struct wmi_t *wmip, A_UINT16 intvl)
+{
+    void *osbuf;
+    WMI_BEACON_INT_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_BEACON_INT_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+    cmd->beaconInterval = intvl;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_BEACON_INT_CMDID,
+            NO_SYNC_WMIFLAG));
+}
+
+
+A_STATUS
+wmi_set_voice_pkt_size_cmd(struct wmi_t *wmip, A_UINT16 voicePktSize)
+{
+    void *osbuf;
+    WMI_SET_VOICE_PKT_SIZE_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_SET_VOICE_PKT_SIZE_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+    cmd->voicePktSize = voicePktSize;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_VOICE_PKT_SIZE_CMDID,
+            NO_SYNC_WMIFLAG));
+}
+
+
+A_STATUS
+wmi_set_max_sp_len_cmd(struct wmi_t *wmip, A_UINT8 maxSPLen)
+{
+    void *osbuf;
+    WMI_SET_MAX_SP_LEN_CMD *cmd;
+
+    /* maxSPLen is a two-bit value. If user trys to set anything
+     * other than this, then its invalid
+     */
+    if(maxSPLen & ~0x03)
+        return  A_EINVAL;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_SET_MAX_SP_LEN_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+    cmd->maxSPLen = maxSPLen;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_MAX_SP_LEN_CMDID,
+            NO_SYNC_WMIFLAG));
+}
+
+A_UINT8
+wmi_determine_userPriority(
+    A_UINT8 *pkt,
+    A_UINT32 layer2Pri)
+{
+    A_UINT8 ipPri;
+    iphdr *ipHdr = (iphdr *)pkt;
+
+    /* Determine IPTOS priority */
+    /*
+     * IP Tos format :
+     *      (Refer Pg 57 WMM-test-plan-v1.2)
+     * IP-TOS - 8bits
+     *          : DSCP(6-bits) ECN(2-bits)
+     *          : DSCP - P2 P1 P0 X X X
+     *              where (P2 P1 P0) form 802.1D
+     */
+    ipPri = ipHdr->ip_tos >> 5;
+    ipPri &= 0x7;
+
+    if ((layer2Pri & 0x7) > ipPri)
+        return ((A_UINT8)layer2Pri & 0x7);
+    else
+        return ipPri;
+}
+
+A_UINT8
+convert_userPriority_to_trafficClass(A_UINT8 userPriority)
+{
+    return  (up_to_ac[userPriority & 0x7]);
+}
+
+A_UINT8
+wmi_get_power_mode_cmd(struct wmi_t *wmip)
+{
+    return wmip->wmi_powerMode;
+}
+
+A_STATUS
+wmi_verify_tspec_params(WMI_CREATE_PSTREAM_CMD *pCmd, A_BOOL tspecCompliance)
+{
+    A_STATUS ret = A_OK;
+
+#define TSPEC_SUSPENSION_INTERVAL_ATHEROS_DEF (~0)
+#define TSPEC_SERVICE_START_TIME_ATHEROS_DEF  0
+#define TSPEC_MAX_BURST_SIZE_ATHEROS_DEF      0
+#define TSPEC_DELAY_BOUND_ATHEROS_DEF         0
+#define TSPEC_MEDIUM_TIME_ATHEROS_DEF         0
+#define TSPEC_SBA_ATHEROS_DEF                 0x2000  /* factor is 1 */
+
+    /* Verify TSPEC params for ATHEROS compliance */
+    if(tspecCompliance == ATHEROS_COMPLIANCE) {
+        if ((pCmd->suspensionInt != TSPEC_SUSPENSION_INTERVAL_ATHEROS_DEF) ||
+            (pCmd->serviceStartTime != TSPEC_SERVICE_START_TIME_ATHEROS_DEF) ||
+            (pCmd->minDataRate != pCmd->meanDataRate) ||
+            (pCmd->minDataRate != pCmd->peakDataRate) ||
+            (pCmd->maxBurstSize != TSPEC_MAX_BURST_SIZE_ATHEROS_DEF) ||
+            (pCmd->delayBound != TSPEC_DELAY_BOUND_ATHEROS_DEF) ||
+            (pCmd->sba != TSPEC_SBA_ATHEROS_DEF) ||
+            (pCmd->mediumTime != TSPEC_MEDIUM_TIME_ATHEROS_DEF)) {
+
+            A_DPRINTF(DBG_WMI, (DBGFMT "Invalid TSPEC params\n", DBGARG));
+            //A_PRINTF("%s: Invalid TSPEC params\n", __func__);
+            ret = A_EINVAL;
+        }
+    }
+
+    return ret;
+}
+
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+static A_STATUS
+wmi_tcmd_test_report_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+
+   A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+   A_WMI_TCMD_RX_REPORT_EVENT(wmip->wmi_devt, datap, len);
+
+   return A_OK;
+}
+
+#endif /* CONFIG_HOST_TCMD_SUPPORT*/
+
+A_STATUS
+wmi_set_authmode_cmd(struct wmi_t *wmip, A_UINT8 mode)
+{
+    void *osbuf;
+    WMI_SET_AUTH_MODE_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_SET_AUTH_MODE_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+    cmd->mode = mode;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_AUTH_MODE_CMDID,
+            NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_reassocmode_cmd(struct wmi_t *wmip, A_UINT8 mode)
+{
+    void *osbuf;
+    WMI_SET_REASSOC_MODE_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_SET_REASSOC_MODE_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+    cmd->mode = mode;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_REASSOC_MODE_CMDID,
+            NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_lpreamble_cmd(struct wmi_t *wmip, A_UINT8 status, A_UINT8 preamblePolicy)
+{
+    void *osbuf;
+    WMI_SET_LPREAMBLE_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_SET_LPREAMBLE_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+    cmd->status = status;
+    cmd->preamblePolicy = preamblePolicy;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_LPREAMBLE_CMDID,
+            NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_rts_cmd(struct wmi_t *wmip, A_UINT16 threshold)
+{
+    void *osbuf;
+    WMI_SET_RTS_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_SET_RTS_CMD*)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+    cmd->threshold = threshold;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_RTS_CMDID,
+            NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_wmm_cmd(struct wmi_t *wmip, WMI_WMM_STATUS status)
+{
+    void *osbuf;
+    WMI_SET_WMM_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_SET_WMM_CMD*)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+    cmd->status = status;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_WMM_CMDID,
+            NO_SYNC_WMIFLAG));
+
+}
+
+A_STATUS
+wmi_set_qos_supp_cmd(struct wmi_t *wmip, A_UINT8 status)
+{
+    void *osbuf;
+    WMI_SET_QOS_SUPP_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_SET_QOS_SUPP_CMD*)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+    cmd->status = status;
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_QOS_SUPP_CMDID,
+            NO_SYNC_WMIFLAG));
+}
+
+
+A_STATUS
+wmi_set_wmm_txop(struct wmi_t *wmip, WMI_TXOP_CFG cfg)
+{
+    void *osbuf;
+    WMI_SET_WMM_TXOP_CMD *cmd;
+
+    if( !((cfg == WMI_TXOP_DISABLED) || (cfg == WMI_TXOP_ENABLED)) )
+        return A_EINVAL;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_SET_WMM_TXOP_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+    cmd->txopEnable = cfg;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_WMM_TXOP_CMDID,
+            NO_SYNC_WMIFLAG));
+
+}
+
+A_STATUS
+wmi_set_country(struct wmi_t *wmip, A_UCHAR *countryCode)
+{
+    void *osbuf;
+    WMI_AP_SET_COUNTRY_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_AP_SET_COUNTRY_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+    A_MEMCPY(cmd->countryCode,countryCode,3);
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_AP_SET_COUNTRY_CMDID,
+            NO_SYNC_WMIFLAG));
+}
+
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+/* WMI  layer doesn't need to know the data type of the test cmd.
+   This would be beneficial for customers like Qualcomm, who might
+   have different test command requirements from differnt manufacturers
+ */
+A_STATUS
+wmi_test_cmd(struct wmi_t *wmip, A_UINT8 *buf, A_UINT32  len)
+{
+    void *osbuf;
+    char *data;
+
+    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+    osbuf= A_NETBUF_ALLOC(len);
+    if(osbuf == NULL)
+    {
+        return A_NO_MEMORY;
+    }
+    A_NETBUF_PUT(osbuf, len);
+    data = A_NETBUF_DATA(osbuf);
+    A_MEMCPY(data, buf, len);
+
+    return(wmi_cmd_send(wmip, osbuf, WMI_TEST_CMDID,
+         NO_SYNC_WMIFLAG));
+}
+
+#endif
+
+A_STATUS
+wmi_set_bt_status_cmd(struct wmi_t *wmip, A_UINT8 streamType, A_UINT8 status)
+{
+    void *osbuf;
+    WMI_SET_BT_STATUS_CMD *cmd;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_WARN, ("Enter - streamType=%d, status=%d\n", streamType, status));
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_SET_BT_STATUS_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+    cmd->streamType = streamType;
+    cmd->status = status;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_BT_STATUS_CMDID,
+            NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_bt_params_cmd(struct wmi_t *wmip, WMI_SET_BT_PARAMS_CMD* cmd)
+{
+    void *osbuf;
+    WMI_SET_BT_PARAMS_CMD* alloc_cmd;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_WARN, ("cmd params is %d\n", cmd->paramType));
+
+    if (cmd->paramType == BT_PARAM_SCO) {
+      AR_DEBUG_PRINTF(ATH_DEBUG_WARN, ("sco params %d %d %d %d %d %d %d %d %d %d %d %d\n", cmd->info.scoParams.numScoCyclesForceTrigger,
+        cmd->info.scoParams.dataResponseTimeout,
+        cmd->info.scoParams.stompScoRules,
+        cmd->info.scoParams.scoOptFlags,
+        cmd->info.scoParams.stompDutyCyleVal,
+        cmd->info.scoParams.stompDutyCyleMaxVal,
+        cmd->info.scoParams.psPollLatencyFraction,
+        cmd->info.scoParams.noSCOSlots,
+        cmd->info.scoParams.noIdleSlots,
+        cmd->info.scoParams.scoOptOffRssi,
+        cmd->info.scoParams.scoOptOnRssi,
+        cmd->info.scoParams.scoOptRtsCount));
+    }
+    else if (cmd->paramType == BT_PARAM_A2DP) {
+      AR_DEBUG_PRINTF(ATH_DEBUG_WARN, ("A2DP params %d %d %d %d %d %d %d %d\n", cmd->info.a2dpParams.a2dpWlanUsageLimit,
+        cmd->info.a2dpParams.a2dpBurstCntMin,
+        cmd->info.a2dpParams.a2dpDataRespTimeout,
+        cmd->info.a2dpParams.a2dpOptFlags,
+        cmd->info.a2dpParams.isCoLocatedBtRoleMaster,
+        cmd->info.a2dpParams.a2dpOptOffRssi,
+        cmd->info.a2dpParams.a2dpOptOnRssi,
+        cmd->info.a2dpParams.a2dpOptRtsCount));
+    }
+    else if (cmd->paramType == BT_PARAM_ANTENNA_CONFIG) {
+      AR_DEBUG_PRINTF(ATH_DEBUG_WARN, ("Ant config %d\n", cmd->info.antType));
+    }
+    else if (cmd->paramType == BT_PARAM_COLOCATED_BT_DEVICE) {
+      AR_DEBUG_PRINTF(ATH_DEBUG_WARN, ("co-located BT %d\n", cmd->info.coLocatedBtDev));
+    }
+    else if (cmd->paramType == BT_PARAM_ACLCOEX) {
+      AR_DEBUG_PRINTF(ATH_DEBUG_WARN, ("ACL params %d %d %d\n", cmd->info.aclCoexParams.aclWlanMediumUsageTime,
+        cmd->info.aclCoexParams.aclBtMediumUsageTime,
+        cmd->info.aclCoexParams.aclDataRespTimeout));
+    }
+    else if (cmd->paramType == BT_PARAM_11A_SEPARATE_ANT) {
+      A_DPRINTF(DBG_WMI, (DBGFMT "11A ant\n", DBGARG));
+    }
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    alloc_cmd = (WMI_SET_BT_PARAMS_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(alloc_cmd, sizeof(*cmd));
+    A_MEMCPY(alloc_cmd, cmd, sizeof(*cmd));
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_BT_PARAMS_CMDID,
+            NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_btcoex_fe_ant_cmd(struct wmi_t *wmip, WMI_SET_BTCOEX_FE_ANT_CMD * cmd)
+{
+	void *osbuf;
+    WMI_SET_BTCOEX_FE_ANT_CMD *alloc_cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+    alloc_cmd = (WMI_SET_BTCOEX_FE_ANT_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(alloc_cmd, sizeof(*cmd));
+	A_MEMCPY(alloc_cmd,cmd,sizeof(WMI_SET_BTCOEX_FE_ANT_CMD));
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_BTCOEX_FE_ANT_CMDID,
+                         NO_SYNC_WMIFLAG));
+
+}
+
+
+A_STATUS
+wmi_set_btcoex_colocated_bt_dev_cmd(struct wmi_t *wmip,
+						WMI_SET_BTCOEX_COLOCATED_BT_DEV_CMD * cmd)
+{
+	void *osbuf;
+    WMI_SET_BTCOEX_COLOCATED_BT_DEV_CMD *alloc_cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+    alloc_cmd = (WMI_SET_BTCOEX_COLOCATED_BT_DEV_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(alloc_cmd, sizeof(*cmd));
+    A_MEMCPY(alloc_cmd,cmd,sizeof(WMI_SET_BTCOEX_COLOCATED_BT_DEV_CMD));
+    A_PRINTF("colocated bt = %d\n", alloc_cmd->btcoexCoLocatedBTdev);
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_BTCOEX_COLOCATED_BT_DEV_CMDID,
+                         NO_SYNC_WMIFLAG));
+
+}
+
+A_STATUS
+wmi_set_btcoex_btinquiry_page_config_cmd(struct wmi_t *wmip,
+						WMI_SET_BTCOEX_BTINQUIRY_PAGE_CONFIG_CMD* cmd)
+{
+	void *osbuf;
+    WMI_SET_BTCOEX_BTINQUIRY_PAGE_CONFIG_CMD *alloc_cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+    alloc_cmd = (WMI_SET_BTCOEX_BTINQUIRY_PAGE_CONFIG_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(alloc_cmd, sizeof(*cmd));
+	A_MEMCPY(alloc_cmd,cmd,sizeof(WMI_SET_BTCOEX_BTINQUIRY_PAGE_CONFIG_CMD));
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_BTCOEX_BTINQUIRY_PAGE_CONFIG_CMDID,
+                         NO_SYNC_WMIFLAG));
+
+}
+
+A_STATUS
+wmi_set_btcoex_sco_config_cmd(struct wmi_t *wmip,
+						WMI_SET_BTCOEX_SCO_CONFIG_CMD * cmd)
+{
+	void *osbuf;
+    WMI_SET_BTCOEX_SCO_CONFIG_CMD *alloc_cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+    alloc_cmd = (WMI_SET_BTCOEX_SCO_CONFIG_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(alloc_cmd, sizeof(*cmd));
+	A_MEMCPY(alloc_cmd,cmd,sizeof(WMI_SET_BTCOEX_SCO_CONFIG_CMD));
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_BTCOEX_SCO_CONFIG_CMDID ,
+                         NO_SYNC_WMIFLAG));
+
+}
+
+A_STATUS
+wmi_set_btcoex_a2dp_config_cmd(struct wmi_t *wmip,
+						WMI_SET_BTCOEX_A2DP_CONFIG_CMD * cmd)
+{
+	void *osbuf;
+    WMI_SET_BTCOEX_A2DP_CONFIG_CMD *alloc_cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+    alloc_cmd = (WMI_SET_BTCOEX_A2DP_CONFIG_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(alloc_cmd, sizeof(*cmd));
+	A_MEMCPY(alloc_cmd,cmd,sizeof(WMI_SET_BTCOEX_A2DP_CONFIG_CMD));
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_BTCOEX_A2DP_CONFIG_CMDID ,
+                         NO_SYNC_WMIFLAG));
+
+}
+
+A_STATUS
+wmi_set_btcoex_aclcoex_config_cmd(struct wmi_t *wmip,
+						WMI_SET_BTCOEX_ACLCOEX_CONFIG_CMD * cmd)
+{
+	void *osbuf;
+    WMI_SET_BTCOEX_ACLCOEX_CONFIG_CMD *alloc_cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+    alloc_cmd = (WMI_SET_BTCOEX_ACLCOEX_CONFIG_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(alloc_cmd, sizeof(*cmd));
+	A_MEMCPY(alloc_cmd,cmd,sizeof(WMI_SET_BTCOEX_ACLCOEX_CONFIG_CMD));
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_BTCOEX_ACLCOEX_CONFIG_CMDID ,
+                         NO_SYNC_WMIFLAG));
+
+}
+
+A_STATUS
+wmi_set_btcoex_debug_cmd(struct wmi_t *wmip, WMI_SET_BTCOEX_DEBUG_CMD * cmd)
+{
+	void *osbuf;
+	WMI_SET_BTCOEX_DEBUG_CMD *alloc_cmd;
+
+	osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+	if (osbuf == NULL) {
+			return A_NO_MEMORY;
+	}
+	A_NETBUF_PUT(osbuf, sizeof(*cmd));
+	alloc_cmd = (WMI_SET_BTCOEX_DEBUG_CMD *)(A_NETBUF_DATA(osbuf));
+	A_MEMZERO(alloc_cmd, sizeof(*cmd));
+	A_MEMCPY(alloc_cmd,cmd,sizeof(WMI_SET_BTCOEX_DEBUG_CMD));
+	return (wmi_cmd_send(wmip, osbuf, WMI_SET_BTCOEX_DEBUG_CMDID ,
+							 NO_SYNC_WMIFLAG));
+
+}
+
+A_STATUS
+wmi_set_btcoex_bt_operating_status_cmd(struct wmi_t * wmip,
+					WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMD * cmd)
+{
+	void *osbuf;
+	WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMD *alloc_cmd;
+
+	osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+	if (osbuf == NULL) {
+			return A_NO_MEMORY;
+	}
+	A_NETBUF_PUT(osbuf, sizeof(*cmd));
+	alloc_cmd = (WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMD *)(A_NETBUF_DATA(osbuf));
+	A_MEMZERO(alloc_cmd, sizeof(*cmd));
+	A_MEMCPY(alloc_cmd,cmd,sizeof(WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMD));
+	return (wmi_cmd_send(wmip, osbuf, WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMDID ,
+								 NO_SYNC_WMIFLAG));
+
+}
+
+A_STATUS
+wmi_get_btcoex_config_cmd(struct wmi_t * wmip, WMI_GET_BTCOEX_CONFIG_CMD * cmd)
+{
+	void *osbuf;
+	WMI_GET_BTCOEX_CONFIG_CMD *alloc_cmd;
+
+	osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+	if (osbuf == NULL) {
+			return A_NO_MEMORY;
+	}
+	A_NETBUF_PUT(osbuf, sizeof(*cmd));
+	alloc_cmd = (WMI_GET_BTCOEX_CONFIG_CMD *)(A_NETBUF_DATA(osbuf));
+	A_MEMZERO(alloc_cmd, sizeof(*cmd));
+	A_MEMCPY(alloc_cmd,cmd,sizeof(WMI_GET_BTCOEX_CONFIG_CMD));
+	return (wmi_cmd_send(wmip, osbuf, WMI_GET_BTCOEX_CONFIG_CMDID ,
+							 NO_SYNC_WMIFLAG));
+
+}
+
+A_STATUS
+wmi_get_btcoex_stats_cmd(struct wmi_t *wmip)
+{
+
+    return wmi_simple_cmd(wmip, WMI_GET_BTCOEX_STATS_CMDID);
+
+}
+
+A_STATUS
+wmi_get_keepalive_configured(struct wmi_t *wmip)
+{
+    void *osbuf;
+    WMI_GET_KEEPALIVE_CMD *cmd;
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+    cmd = (WMI_GET_KEEPALIVE_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+    return (wmi_cmd_send(wmip, osbuf, WMI_GET_KEEPALIVE_CMDID,
+                         NO_SYNC_WMIFLAG));
+}
+
+A_UINT8
+wmi_get_keepalive_cmd(struct wmi_t *wmip)
+{
+    return wmip->wmi_keepaliveInterval;
+}
+
+A_STATUS
+wmi_set_keepalive_cmd(struct wmi_t *wmip, A_UINT8 keepaliveInterval)
+{
+    void *osbuf;
+    WMI_SET_KEEPALIVE_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_SET_KEEPALIVE_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+    cmd->keepaliveInterval = keepaliveInterval;
+    wmip->wmi_keepaliveInterval = keepaliveInterval;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_KEEPALIVE_CMDID,
+                         NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_params_cmd(struct wmi_t *wmip, A_UINT32 opcode, A_UINT32 length, A_CHAR* buffer)
+{
+    void *osbuf;
+    WMI_SET_PARAMS_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd) + length);
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd) + length);
+
+    cmd = (WMI_SET_PARAMS_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+    cmd->opcode = opcode;
+    cmd->length = length;
+    A_MEMCPY(cmd->buffer, buffer, length);
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_PARAMS_CMDID,
+                         NO_SYNC_WMIFLAG));
+}
+
+
+A_STATUS
+wmi_set_mcast_filter_cmd(struct wmi_t *wmip, A_UINT8 dot1, A_UINT8 dot2, A_UINT8 dot3, A_UINT8 dot4)
+{
+    void *osbuf;
+    WMI_SET_MCAST_FILTER_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_SET_MCAST_FILTER_CMD *)(A_NETBUF_DATA(osbuf));
+    cmd->multicast_mac[0] = 0x01;
+    cmd->multicast_mac[1] = 0x00;
+    cmd->multicast_mac[2] = 0x5e;
+    cmd->multicast_mac[3] = dot2&0x7F;
+    cmd->multicast_mac[4] = dot3;
+    cmd->multicast_mac[5] = dot4;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_MCAST_FILTER_CMDID,
+                         NO_SYNC_WMIFLAG));
+}
+
+
+A_STATUS
+wmi_del_mcast_filter_cmd(struct wmi_t *wmip, A_UINT8 dot1, A_UINT8 dot2, A_UINT8 dot3, A_UINT8 dot4)
+{
+    void *osbuf;
+    WMI_SET_MCAST_FILTER_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_SET_MCAST_FILTER_CMD *)(A_NETBUF_DATA(osbuf));
+    cmd->multicast_mac[0] = 0x01;
+    cmd->multicast_mac[1] = 0x00;
+    cmd->multicast_mac[2] = 0x5e;
+    cmd->multicast_mac[3] = dot2&0x7F;
+    cmd->multicast_mac[4] = dot3;
+    cmd->multicast_mac[5] = dot4;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_DEL_MCAST_FILTER_CMDID,
+                         NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_mcast_filter_cmd(struct wmi_t *wmip, A_UINT8 enable)
+{
+    void *osbuf;
+    WMI_MCAST_FILTER_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_MCAST_FILTER_CMD *)(A_NETBUF_DATA(osbuf));
+    cmd->enable = enable;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_MCAST_FILTER_CMDID,
+                         NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_appie_cmd(struct wmi_t *wmip, A_UINT8 mgmtFrmType, A_UINT8 ieLen,
+                  A_UINT8 *ieInfo)
+{
+    void *osbuf;
+    WMI_SET_APPIE_CMD *cmd;
+    A_UINT16 cmdLen;
+
+    cmdLen = sizeof(*cmd) + ieLen - 1;
+    osbuf = A_NETBUF_ALLOC(cmdLen);
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, cmdLen);
+
+    cmd = (WMI_SET_APPIE_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, cmdLen);
+
+    cmd->mgmtFrmType = mgmtFrmType;
+    cmd->ieLen = ieLen;
+    A_MEMCPY(cmd->ieInfo, ieInfo, ieLen);
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_APPIE_CMDID, NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_halparam_cmd(struct wmi_t *wmip, A_UINT8 *cmd, A_UINT16 dataLen)
+{
+    void *osbuf;
+    A_UINT8 *data;
+
+    osbuf = A_NETBUF_ALLOC(dataLen);
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, dataLen);
+
+    data = A_NETBUF_DATA(osbuf);
+
+    A_MEMCPY(data, cmd, dataLen);
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_WHALPARAM_CMDID, NO_SYNC_WMIFLAG));
+}
+
+A_INT32
+wmi_get_rate(A_INT8 rateindex)
+{
+    if (rateindex == RATE_AUTO) {
+        return 0;
+    } else {
+        return(wmi_rateTable[(A_UINT32) rateindex][0]);
+    }
+}
+
+void
+wmi_node_return (struct wmi_t *wmip, bss_t *bss)
+{
+    if (NULL != bss)
+    {
+        wlan_node_return (&wmip->wmi_scan_table, bss);
+    }
+}
+
+void
+wmi_set_nodeage(struct wmi_t *wmip, A_UINT32 nodeAge)
+{
+    wlan_set_nodeage(&wmip->wmi_scan_table,nodeAge);
+}
+
+bss_t *
+wmi_find_Ssidnode (struct wmi_t *wmip, A_UCHAR *pSsid,
+                   A_UINT32 ssidLength, A_BOOL bIsWPA2, A_BOOL bMatchSSID)
+{
+    bss_t *node = NULL;
+    node = wlan_find_Ssidnode (&wmip->wmi_scan_table, pSsid,
+                               ssidLength, bIsWPA2, bMatchSSID);
+    return node;
+}
+
+
+#ifdef THREAD_X
+void
+wmi_refresh_scan_table (struct wmi_t *wmip)
+{
+	wlan_refresh_inactive_nodes (&wmip->wmi_scan_table);
+}
+#endif
+
+void
+wmi_free_allnodes(struct wmi_t *wmip)
+{
+    wlan_free_allnodes(&wmip->wmi_scan_table);
+}
+
+bss_t *
+wmi_find_node(struct wmi_t *wmip, const A_UINT8 *macaddr)
+{
+    bss_t *ni=NULL;
+    ni=wlan_find_node(&wmip->wmi_scan_table,macaddr);
+    return ni;
+}
+
+void
+wmi_free_node(struct wmi_t *wmip, const A_UINT8 *macaddr)
+{
+    bss_t *ni=NULL;
+
+    ni=wlan_find_node(&wmip->wmi_scan_table,macaddr);
+    if (ni != NULL) {
+        wlan_node_reclaim(&wmip->wmi_scan_table, ni);
+    }
+
+    return;
+}
+
+A_STATUS
+wmi_dset_open_reply(struct wmi_t *wmip,
+                    A_UINT32 status,
+                    A_UINT32 access_cookie,
+                    A_UINT32 dset_size,
+                    A_UINT32 dset_version,
+                    A_UINT32 targ_handle,
+                    A_UINT32 targ_reply_fn,
+                    A_UINT32 targ_reply_arg)
+{
+    void *osbuf;
+    WMIX_DSETOPEN_REPLY_CMD *open_reply;
+
+    A_DPRINTF(DBG_WMI, (DBGFMT "Enter - wmip=0x%lx\n", DBGARG, (unsigned long)wmip));
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*open_reply));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*open_reply));
+    open_reply = (WMIX_DSETOPEN_REPLY_CMD *)(A_NETBUF_DATA(osbuf));
+
+    open_reply->status                   = status;
+    open_reply->targ_dset_handle         = targ_handle;
+    open_reply->targ_reply_fn            = targ_reply_fn;
+    open_reply->targ_reply_arg           = targ_reply_arg;
+    open_reply->access_cookie            = access_cookie;
+    open_reply->size                     = dset_size;
+    open_reply->version                  = dset_version;
+
+    return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_DSETOPEN_REPLY_CMDID,
+                             NO_SYNC_WMIFLAG));
+}
+
+static A_STATUS
+wmi_get_pmkid_list_event_rx(struct wmi_t *wmip, A_UINT8 *datap, A_UINT32 len)
+{
+    WMI_PMKID_LIST_REPLY *reply;
+    A_UINT32 expected_len;
+
+    if (len < sizeof(WMI_PMKID_LIST_REPLY)) {
+        return A_EINVAL;
+    }
+    reply = (WMI_PMKID_LIST_REPLY *)datap;
+    expected_len = sizeof(reply->numPMKID) + reply->numPMKID * WMI_PMKID_LEN;
+
+    if (len < expected_len) {
+        return A_EINVAL;
+    }
+
+    A_WMI_PMKID_LIST_EVENT(wmip->wmi_devt, reply->numPMKID,
+                           reply->pmkidList, reply->bssidList[0]);
+
+    return A_OK;
+}
+
+
+static A_STATUS
+wmi_set_params_event_rx(struct wmi_t *wmip, A_UINT8 *datap, A_UINT32 len)
+{
+    WMI_SET_PARAMS_REPLY *reply;
+
+    if (len < sizeof(WMI_SET_PARAMS_REPLY)) {
+        return A_EINVAL;
+    }
+    reply = (WMI_SET_PARAMS_REPLY *)datap;
+
+    if (A_OK == reply->status)
+    {
+
+    }
+    else
+    {
+
+    }
+
+    return A_OK;
+}
+
+
+
+static A_STATUS
+wmi_acm_reject_event_rx(struct wmi_t *wmip, A_UINT8 *datap, A_UINT32 len)
+{
+    WMI_ACM_REJECT_EVENT *ev;
+
+    ev = (WMI_ACM_REJECT_EVENT *)datap;
+    wmip->wmi_traffic_class = ev->trafficClass;
+    printk("ACM REJECT %d\n",wmip->wmi_traffic_class);
+    return A_OK;
+}
+
+
+#ifdef CONFIG_HOST_DSET_SUPPORT
+A_STATUS
+wmi_dset_data_reply(struct wmi_t *wmip,
+                    A_UINT32 status,
+                    A_UINT8 *user_buf,
+                    A_UINT32 length,
+                    A_UINT32 targ_buf,
+                    A_UINT32 targ_reply_fn,
+                    A_UINT32 targ_reply_arg)
+{
+    void *osbuf;
+    WMIX_DSETDATA_REPLY_CMD *data_reply;
+    A_UINT32 size;
+
+    size = sizeof(*data_reply) + length;
+
+    if (size <= length) {
+        return A_ERROR;
+    }
+
+    A_DPRINTF(DBG_WMI,
+        (DBGFMT "Enter - length=%d status=%d\n", DBGARG, length, status));
+
+    osbuf = A_NETBUF_ALLOC(size);
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+    A_NETBUF_PUT(osbuf, size);
+    data_reply = (WMIX_DSETDATA_REPLY_CMD *)(A_NETBUF_DATA(osbuf));
+
+    data_reply->status                     = status;
+    data_reply->targ_buf                   = targ_buf;
+    data_reply->targ_reply_fn              = targ_reply_fn;
+    data_reply->targ_reply_arg             = targ_reply_arg;
+    data_reply->length                     = length;
+
+    if (status == A_OK) {
+        if (a_copy_from_user(data_reply->buf, user_buf, length)) {
+            A_NETBUF_FREE(osbuf);
+            return A_ERROR;
+        }
+    }
+
+    return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_DSETDATA_REPLY_CMDID,
+                             NO_SYNC_WMIFLAG));
+}
+#endif /* CONFIG_HOST_DSET_SUPPORT */
+
+A_STATUS
+wmi_set_wsc_status_cmd(struct wmi_t *wmip, A_UINT32 status)
+{
+    void *osbuf;
+    char *cmd;
+
+    wps_enable = status;
+
+    osbuf = a_netbuf_alloc(sizeof(1));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    a_netbuf_put(osbuf, sizeof(1));
+
+    cmd = (char *)(a_netbuf_to_data(osbuf));
+
+    A_MEMZERO(cmd, sizeof(*cmd));
+    cmd[0] = (status?1:0);
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_WSC_STATUS_CMDID,
+                         NO_SYNC_WMIFLAG));
+}
+
+#if defined(CONFIG_TARGET_PROFILE_SUPPORT)
+A_STATUS
+wmi_prof_cfg_cmd(struct wmi_t *wmip,
+                 A_UINT32 period,
+                 A_UINT32 nbins)
+{
+    void *osbuf;
+    WMIX_PROF_CFG_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMIX_PROF_CFG_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+    cmd->period = period;
+    cmd->nbins  = nbins;
+
+    return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_PROF_CFG_CMDID, NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_prof_addr_set_cmd(struct wmi_t *wmip, A_UINT32 addr)
+{
+    void *osbuf;
+    WMIX_PROF_ADDR_SET_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMIX_PROF_ADDR_SET_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+    cmd->addr = addr;
+
+    return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_PROF_ADDR_SET_CMDID, NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_prof_start_cmd(struct wmi_t *wmip)
+{
+    return wmi_simple_cmd_xtnd(wmip, WMIX_PROF_START_CMDID);
+}
+
+A_STATUS
+wmi_prof_stop_cmd(struct wmi_t *wmip)
+{
+    return wmi_simple_cmd_xtnd(wmip, WMIX_PROF_STOP_CMDID);
+}
+
+A_STATUS
+wmi_prof_count_get_cmd(struct wmi_t *wmip)
+{
+    return wmi_simple_cmd_xtnd(wmip, WMIX_PROF_COUNT_GET_CMDID);
+}
+
+/* Called to handle WMIX_PROF_CONT_EVENTID */
+static A_STATUS
+wmi_prof_count_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMIX_PROF_COUNT_EVENT *prof_data = (WMIX_PROF_COUNT_EVENT *)datap;
+
+    A_DPRINTF(DBG_WMI,
+        (DBGFMT "Enter - addr=0x%x count=%d\n", DBGARG,
+        prof_data->addr, prof_data->count));
+
+    A_WMI_PROF_COUNT_RX(prof_data->addr, prof_data->count);
+
+    return A_OK;
+}
+#endif /* CONFIG_TARGET_PROFILE_SUPPORT */
+
+#ifdef OS_ROAM_MANAGEMENT
+
+#define ETHERNET_MAC_ADDRESS_LENGTH    6
+
+void
+wmi_scan_indication (struct wmi_t *wmip)
+{
+    struct ieee80211_node_table *nt;
+    A_UINT32 gen;
+    A_UINT32 size;
+    A_UINT32 bsssize;
+    bss_t *bss;
+    A_UINT32 numbss;
+    PNDIS_802_11_BSSID_SCAN_INFO psi;
+    PBYTE  pie;
+    NDIS_802_11_FIXED_IEs *pFixed;
+    NDIS_802_11_VARIABLE_IEs *pVar;
+    A_UINT32  RateSize;
+
+    struct ar6kScanIndication
+    {
+        NDIS_802_11_STATUS_INDICATION     ind;
+        NDIS_802_11_BSSID_SCAN_INFO_LIST  slist;
+    } *pAr6kScanIndEvent;
+
+    nt = &wmip->wmi_scan_table;
+
+    ++nt->nt_si_gen;
+
+
+    gen = nt->nt_si_gen;
+
+    size = offsetof(struct ar6kScanIndication, slist) +
+           offsetof(NDIS_802_11_BSSID_SCAN_INFO_LIST, BssidScanInfo);
+
+    numbss = 0;
+
+    IEEE80211_NODE_LOCK(nt);
+
+    //calc size
+    for (bss = nt->nt_node_first; bss; bss = bss->ni_list_next) {
+        if (bss->ni_si_gen != gen) {
+            bsssize = offsetof(NDIS_802_11_BSSID_SCAN_INFO, Bssid) + offsetof(NDIS_WLAN_BSSID_EX, IEs);
+            bsssize = bsssize + sizeof(NDIS_802_11_FIXED_IEs);
+
+#ifdef SUPPORT_WPA2
+            if (bss->ni_cie.ie_rsn) {
+                bsssize = bsssize + bss->ni_cie.ie_rsn[1] + 2;
+            }
+#endif
+            if (bss->ni_cie.ie_wpa) {
+                bsssize = bsssize + bss->ni_cie.ie_wpa[1] + 2;
+            }
+
+            // bsssize must be a multiple of 4 to maintain alignment.
+            bsssize = (bsssize + 3) & ~3;
+
+            size += bsssize;
+
+            numbss++;
+        }
+    }
+
+    if (0 == numbss)
+    {
+//        RETAILMSG(1, (L"AR6K: scan indication: 0 bss\n"));
+        ar6000_scan_indication (wmip->wmi_devt, NULL, 0);
+        IEEE80211_NODE_UNLOCK (nt);
+        return;
+    }
+
+    pAr6kScanIndEvent = A_MALLOC(size);
+
+    if (NULL == pAr6kScanIndEvent)
+    {
+        IEEE80211_NODE_UNLOCK(nt);
+        return;
+    }
+
+    A_MEMZERO(pAr6kScanIndEvent, size);
+
+    //copy data
+    pAr6kScanIndEvent->ind.StatusType = Ndis802_11StatusType_BssidScanInfoList;
+    pAr6kScanIndEvent->slist.Version = 1;
+    pAr6kScanIndEvent->slist.NumItems = numbss;
+
+    psi = &pAr6kScanIndEvent->slist.BssidScanInfo[0];
+
+    for (bss = nt->nt_node_first; bss; bss = bss->ni_list_next) {
+        if (bss->ni_si_gen != gen) {
+
+            bss->ni_si_gen = gen;
+
+            //Set scan time
+            psi->ScanTime = bss->ni_tstamp - WLAN_NODE_INACT_TIMEOUT_MSEC;
+
+            // Copy data to bssid_ex
+            bsssize = offsetof(NDIS_WLAN_BSSID_EX, IEs);
+            bsssize = bsssize + sizeof(NDIS_802_11_FIXED_IEs);
+
+#ifdef SUPPORT_WPA2
+            if (bss->ni_cie.ie_rsn) {
+                bsssize = bsssize + bss->ni_cie.ie_rsn[1] + 2;
+            }
+#endif
+            if (bss->ni_cie.ie_wpa) {
+                bsssize = bsssize + bss->ni_cie.ie_wpa[1] + 2;
+            }
+
+            // bsssize must be a multiple of 4 to maintain alignment.
+            bsssize = (bsssize + 3) & ~3;
+
+            psi->Bssid.Length = bsssize;
+
+            memcpy (psi->Bssid.MacAddress, bss->ni_macaddr, ETHERNET_MAC_ADDRESS_LENGTH);
+
+
+//if (((bss->ni_macaddr[3] == 0xCE) && (bss->ni_macaddr[4] == 0xF0) && (bss->ni_macaddr[5] == 0xE7)) ||
+//  ((bss->ni_macaddr[3] == 0x03) && (bss->ni_macaddr[4] == 0xE2) && (bss->ni_macaddr[5] == 0x70)))
+//            RETAILMSG (1, (L"%x\n",bss->ni_macaddr[5]));
+
+            psi->Bssid.Ssid.SsidLength = 0;
+            pie = bss->ni_cie.ie_ssid;
+
+            if (pie) {
+                // Format of SSID IE is:
+                //  Type   (1 octet)
+                //  Length (1 octet)
+                //  SSID (Length octets)
+                //
+                //  Validation of the IE should have occurred within WMI.
+                //
+                if (pie[1] <= 32) {
+                    psi->Bssid.Ssid.SsidLength = pie[1];
+                    memcpy(psi->Bssid.Ssid.Ssid, &pie[2], psi->Bssid.Ssid.SsidLength);
+                }
+            }
+            psi->Bssid.Privacy = (bss->ni_cie.ie_capInfo & 0x10) ? 1 : 0;
+
+            //Post the RSSI value relative to the Standard Noise floor value.
+            psi->Bssid.Rssi = bss->ni_rssi;
+
+            if (bss->ni_cie.ie_chan >= 2412 && bss->ni_cie.ie_chan <= 2484) {
+
+                if (bss->ni_cie.ie_rates && bss->ni_cie.ie_xrates) {
+                    psi->Bssid.NetworkTypeInUse = Ndis802_11OFDM24;
+                }
+                else {
+                    psi->Bssid.NetworkTypeInUse = Ndis802_11DS;
+                }
+            }
+            else {
+                psi->Bssid.NetworkTypeInUse = Ndis802_11OFDM5;
+            }
+
+            psi->Bssid.Configuration.Length = sizeof(psi->Bssid.Configuration);
+            psi->Bssid.Configuration.BeaconPeriod = bss->ni_cie.ie_beaconInt; // Units are Kmicroseconds (1024 us)
+            psi->Bssid.Configuration.ATIMWindow =  0;
+            psi->Bssid.Configuration.DSConfig =  bss->ni_cie.ie_chan * 1000;
+            psi->Bssid.InfrastructureMode = ((bss->ni_cie.ie_capInfo & 0x03) == 0x01 ) ? Ndis802_11Infrastructure : Ndis802_11IBSS;
+
+            RateSize = 0;
+            pie = bss->ni_cie.ie_rates;
+            if (pie) {
+                RateSize = (pie[1] < NDIS_802_11_LENGTH_RATES_EX) ? pie[1] : NDIS_802_11_LENGTH_RATES_EX;
+                memcpy(psi->Bssid.SupportedRates, &pie[2], RateSize);
+            }
+            pie = bss->ni_cie.ie_xrates;
+            if (pie && RateSize < NDIS_802_11_LENGTH_RATES_EX) {
+                memcpy(psi->Bssid.SupportedRates + RateSize, &pie[2],
+                       (pie[1] < (NDIS_802_11_LENGTH_RATES_EX - RateSize)) ? pie[1] : (NDIS_802_11_LENGTH_RATES_EX - RateSize));
+            }
+
+            // Copy the fixed IEs
+            psi->Bssid.IELength = sizeof(NDIS_802_11_FIXED_IEs);
+
+            pFixed = (NDIS_802_11_FIXED_IEs *)psi->Bssid.IEs;
+            memcpy(pFixed->Timestamp, bss->ni_cie.ie_tstamp, sizeof(pFixed->Timestamp));
+            pFixed->BeaconInterval = bss->ni_cie.ie_beaconInt;
+            pFixed->Capabilities = bss->ni_cie.ie_capInfo;
+
+            // Copy selected variable IEs
+
+            pVar = (NDIS_802_11_VARIABLE_IEs *)((PBYTE)pFixed + sizeof(NDIS_802_11_FIXED_IEs));
+
+#ifdef SUPPORT_WPA2
+            // Copy the WPAv2 IE
+            if (bss->ni_cie.ie_rsn) {
+                pie = bss->ni_cie.ie_rsn;
+                psi->Bssid.IELength += pie[1] + 2;
+                memcpy(pVar, pie, pie[1] + 2);
+                pVar = (NDIS_802_11_VARIABLE_IEs *)((PBYTE)pVar + pie[1] + 2);
+            }
+#endif
+            // Copy the WPAv1 IE
+            if (bss->ni_cie.ie_wpa) {
+                pie = bss->ni_cie.ie_wpa;
+                psi->Bssid.IELength += pie[1] + 2;
+                memcpy(pVar, pie, pie[1] + 2);
+                pVar = (NDIS_802_11_VARIABLE_IEs *)((PBYTE)pVar + pie[1] + 2);
+            }
+
+            // Advance buffer pointer
+            psi = (PNDIS_802_11_BSSID_SCAN_INFO)((BYTE*)psi + bsssize + FIELD_OFFSET(NDIS_802_11_BSSID_SCAN_INFO, Bssid));
+        }
+    }
+
+    IEEE80211_NODE_UNLOCK(nt);
+
+//    wmi_free_allnodes(wmip);
+
+//    RETAILMSG(1, (L"AR6K: scan indication: %u bss\n", numbss));
+
+    ar6000_scan_indication (wmip->wmi_devt, pAr6kScanIndEvent, size);
+
+    A_FREE(pAr6kScanIndEvent);
+}
+#endif
+
+A_UINT8
+ar6000_get_upper_threshold(A_INT16 rssi, SQ_THRESHOLD_PARAMS *sq_thresh,
+                           A_UINT32 size)
+{
+    A_UINT32 index;
+    A_UINT8 threshold = (A_UINT8)sq_thresh->upper_threshold[size - 1];
+
+    /* The list is already in sorted order. Get the next lower value */
+    for (index = 0; index < size; index ++) {
+        if (rssi < sq_thresh->upper_threshold[index]) {
+            threshold = (A_UINT8)sq_thresh->upper_threshold[index];
+            break;
+        }
+    }
+
+    return threshold;
+}
+
+A_UINT8
+ar6000_get_lower_threshold(A_INT16 rssi, SQ_THRESHOLD_PARAMS *sq_thresh,
+                           A_UINT32 size)
+{
+    A_UINT32 index;
+    A_UINT8 threshold = (A_UINT8)sq_thresh->lower_threshold[size - 1];
+
+    /* The list is already in sorted order. Get the next lower value */
+    for (index = 0; index < size; index ++) {
+        if (rssi > sq_thresh->lower_threshold[index]) {
+            threshold = (A_UINT8)sq_thresh->lower_threshold[index];
+            break;
+        }
+    }
+
+    return threshold;
+}
+static A_STATUS
+wmi_send_rssi_threshold_params(struct wmi_t *wmip,
+                              WMI_RSSI_THRESHOLD_PARAMS_CMD *rssiCmd)
+{
+    void    *osbuf;
+    A_INT8  size;
+    WMI_RSSI_THRESHOLD_PARAMS_CMD *cmd;
+
+    size = sizeof (*cmd);
+
+    osbuf = A_NETBUF_ALLOC(size);
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, size);
+
+    cmd = (WMI_RSSI_THRESHOLD_PARAMS_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, size);
+    A_MEMCPY(cmd, rssiCmd, sizeof(WMI_RSSI_THRESHOLD_PARAMS_CMD));
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_RSSI_THRESHOLD_PARAMS_CMDID,
+                            NO_SYNC_WMIFLAG));
+}
+static A_STATUS
+wmi_send_snr_threshold_params(struct wmi_t *wmip,
+                             WMI_SNR_THRESHOLD_PARAMS_CMD *snrCmd)
+{
+    void    *osbuf;
+    A_INT8  size;
+    WMI_SNR_THRESHOLD_PARAMS_CMD *cmd;
+
+    size = sizeof (*cmd);
+
+    osbuf = A_NETBUF_ALLOC(size);
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, size);
+    cmd = (WMI_SNR_THRESHOLD_PARAMS_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, size);
+    A_MEMCPY(cmd, snrCmd, sizeof(WMI_SNR_THRESHOLD_PARAMS_CMD));
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SNR_THRESHOLD_PARAMS_CMDID,
+                            NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_target_event_report_cmd(struct wmi_t *wmip, WMI_SET_TARGET_EVENT_REPORT_CMD* cmd)
+{
+    void *osbuf;
+    WMI_SET_TARGET_EVENT_REPORT_CMD* alloc_cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    alloc_cmd = (WMI_SET_TARGET_EVENT_REPORT_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(alloc_cmd, sizeof(*cmd));
+    A_MEMCPY(alloc_cmd, cmd, sizeof(*cmd));
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_TARGET_EVENT_REPORT_CMDID,
+            NO_SYNC_WMIFLAG));
+}
+
+bss_t *wmi_rm_current_bss (struct wmi_t *wmip, A_UINT8 *id)
+{
+    wmi_get_current_bssid (wmip, id);
+    return wlan_node_remove (&wmip->wmi_scan_table, id);
+}
+
+A_STATUS wmi_add_current_bss (struct wmi_t *wmip, A_UINT8 *id, bss_t *bss)
+{
+    wlan_setup_node (&wmip->wmi_scan_table, bss, id);
+    return A_OK;
+}
+
+#ifdef ATH_AR6K_11N_SUPPORT
+static A_STATUS
+wmi_addba_req_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMI_ADDBA_REQ_EVENT *cmd = (WMI_ADDBA_REQ_EVENT *)datap;
+
+    A_WMI_AGGR_RECV_ADDBA_REQ_EVT(wmip->wmi_devt, cmd);
+
+    return A_OK;
+}
+
+
+static A_STATUS
+wmi_addba_resp_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMI_ADDBA_RESP_EVENT *cmd = (WMI_ADDBA_RESP_EVENT *)datap;
+
+    A_WMI_AGGR_RECV_ADDBA_RESP_EVT(wmip->wmi_devt, cmd);
+
+    return A_OK;
+}
+
+static A_STATUS
+wmi_delba_req_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMI_DELBA_EVENT *cmd = (WMI_DELBA_EVENT *)datap;
+
+    A_WMI_AGGR_RECV_DELBA_REQ_EVT(wmip->wmi_devt, cmd);
+
+    return A_OK;
+}
+
+A_STATUS
+wmi_btcoex_config_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+	A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+    A_WMI_BTCOEX_CONFIG_EVENT(wmip->wmi_devt, datap, len);
+
+     return A_OK;
+}
+
+
+A_STATUS
+wmi_btcoex_stats_event_rx(struct wmi_t * wmip,A_UINT8 * datap,int len)
+{
+	A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+    A_WMI_BTCOEX_STATS_EVENT(wmip->wmi_devt, datap, len);
+
+     return A_OK;
+
+}
+#endif
+
+static A_STATUS
+wmi_hci_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMI_HCI_EVENT *cmd = (WMI_HCI_EVENT *)datap;
+    A_WMI_HCI_EVENT_EVT(wmip->wmi_devt, cmd);
+
+    return A_OK;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+////                                                                        ////
+////                AP mode functions                                       ////
+////                                                                        ////
+////////////////////////////////////////////////////////////////////////////////
+/*
+ * IOCTL: AR6000_XIOCTL_AP_COMMIT_CONFIG
+ *
+ * When AR6K in AP mode, This command will be called after
+ * changing ssid, channel etc. It will pass the profile to
+ * target with a flag which will indicate which parameter changed,
+ * also if this flag is 0, there was no change in parametes, so
+ * commit cmd will not be sent to target. Without calling this IOCTL
+ * the changes will not take effect.
+ */
+A_STATUS
+wmi_ap_profile_commit(struct wmi_t *wmip, WMI_CONNECT_CMD *p)
+{
+    void *osbuf;
+    WMI_CONNECT_CMD *cm;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cm));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cm));
+    cm = (WMI_CONNECT_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cm, sizeof(*cm));
+
+    A_MEMCPY(cm,p,sizeof(*cm));
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_AP_CONFIG_COMMIT_CMDID, NO_SYNC_WMIFLAG));
+}
+
+/*
+ * IOCTL: AR6000_XIOCTL_AP_HIDDEN_SSID
+ *
+ * This command will be used to enable/disable hidden ssid functioanlity of
+ * beacon. If it is enabled, ssid will be NULL in beacon.
+ */
+A_STATUS
+wmi_ap_set_hidden_ssid(struct wmi_t *wmip, A_UINT8 hidden_ssid)
+{
+    void *osbuf;
+    WMI_AP_HIDDEN_SSID_CMD *hs;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(WMI_AP_HIDDEN_SSID_CMD));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(WMI_AP_HIDDEN_SSID_CMD));
+    hs = (WMI_AP_HIDDEN_SSID_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(hs, sizeof(*hs));
+
+    hs->hidden_ssid          = hidden_ssid;
+
+    A_DPRINTF(DBG_WMI, (DBGFMT "AR6000_XIOCTL_AP_HIDDEN_SSID %d\n", DBGARG , hidden_ssid));
+    return (wmi_cmd_send(wmip, osbuf, WMI_AP_HIDDEN_SSID_CMDID, NO_SYNC_WMIFLAG));
+}
+
+/*
+ * IOCTL: AR6000_XIOCTL_AP_SET_MAX_NUM_STA
+ *
+ * This command is used to limit max num of STA that can connect
+ * with this AP. This value should not exceed AP_MAX_NUM_STA (this
+ * is max num of STA supported by AP). Value was already validated
+ * in ioctl.c
+ */
+A_STATUS
+wmi_ap_set_num_sta(struct wmi_t *wmip, A_UINT8 num_sta)
+{
+    void *osbuf;
+    WMI_AP_SET_NUM_STA_CMD *ns;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(WMI_AP_SET_NUM_STA_CMD));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(WMI_AP_SET_NUM_STA_CMD));
+    ns = (WMI_AP_SET_NUM_STA_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(ns, sizeof(*ns));
+
+    ns->num_sta          = num_sta;
+
+    A_DPRINTF(DBG_WMI, (DBGFMT "AR6000_XIOCTL_AP_SET_MAX_NUM_STA %d\n", DBGARG , num_sta));
+    return (wmi_cmd_send(wmip, osbuf, WMI_AP_SET_NUM_STA_CMDID, NO_SYNC_WMIFLAG));
+}
+
+/*
+ * IOCTL: AR6000_XIOCTL_AP_SET_ACL_MAC
+ *
+ * This command is used to send list of mac of STAs which will
+ * be allowed to connect with this AP. When this list is empty
+ * firware will allow all STAs till the count reaches AP_MAX_NUM_STA.
+ */
+A_STATUS
+wmi_ap_acl_mac_list(struct wmi_t *wmip, WMI_AP_ACL_MAC_CMD *acl)
+{
+    void *osbuf;
+    WMI_AP_ACL_MAC_CMD *a;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(WMI_AP_ACL_MAC_CMD));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(WMI_AP_ACL_MAC_CMD));
+    a = (WMI_AP_ACL_MAC_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(a, sizeof(*a));
+    A_MEMCPY(a,acl,sizeof(*acl));
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_AP_ACL_MAC_LIST_CMDID, NO_SYNC_WMIFLAG));
+}
+
+/*
+ * IOCTL: AR6000_XIOCTL_AP_SET_MLME
+ *
+ * This command is used to send list of mac of STAs which will
+ * be allowed to connect with this AP. When this list is empty
+ * firware will allow all STAs till the count reaches AP_MAX_NUM_STA.
+ */
+A_STATUS
+wmi_ap_set_mlme(struct wmi_t *wmip, A_UINT8 cmd, A_UINT8 *mac, A_UINT16 reason)
+{
+    void *osbuf;
+    WMI_AP_SET_MLME_CMD *mlme;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(WMI_AP_SET_MLME_CMD));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(WMI_AP_SET_MLME_CMD));
+    mlme = (WMI_AP_SET_MLME_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(mlme, sizeof(*mlme));
+
+    mlme->cmd = cmd;
+    A_MEMCPY(mlme->mac, mac, ATH_MAC_LEN);
+    mlme->reason = reason;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_AP_SET_MLME_CMDID, NO_SYNC_WMIFLAG));
+}
+
+static A_STATUS
+wmi_pspoll_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMI_PSPOLL_EVENT *ev;
+
+    if (len < sizeof(WMI_PSPOLL_EVENT)) {
+        return A_EINVAL;
+    }
+    ev = (WMI_PSPOLL_EVENT *)datap;
+
+    A_WMI_PSPOLL_EVENT(wmip->wmi_devt, ev->aid);
+    return A_OK;
+}
+
+static A_STATUS
+wmi_dtimexpiry_event_rx(struct wmi_t *wmip, A_UINT8 *datap,int len)
+{
+    A_WMI_DTIMEXPIRY_EVENT(wmip->wmi_devt);
+    return A_OK;
+}
+
+#ifdef WAPI_ENABLE
+static A_STATUS
+wmi_wapi_rekey_event_rx(struct wmi_t *wmip, A_UINT8 *datap,int len)
+{
+    A_UINT8 *ev;
+
+    if (len < 7) {
+        return A_EINVAL;
+    }
+    ev = (A_UINT8 *)datap;
+
+    A_WMI_WAPI_REKEY_EVENT(wmip->wmi_devt, *ev, &ev[1]);
+    return A_OK;
+}
+#endif
+
+A_STATUS
+wmi_set_pvb_cmd(struct wmi_t *wmip, A_UINT16 aid, A_BOOL flag)
+{
+    WMI_AP_SET_PVB_CMD *cmd;
+    void *osbuf = NULL;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(WMI_AP_SET_PVB_CMD));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(WMI_AP_SET_PVB_CMD));
+    cmd = (WMI_AP_SET_PVB_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+
+    cmd->aid = aid;
+    cmd->flag = flag;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_AP_SET_PVB_CMDID, NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_ap_conn_inact_time(struct wmi_t *wmip, A_UINT32 period)
+{
+    WMI_AP_CONN_INACT_CMD *cmd;
+    void *osbuf = NULL;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(WMI_AP_CONN_INACT_CMD));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(WMI_AP_CONN_INACT_CMD));
+    cmd = (WMI_AP_CONN_INACT_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+
+    cmd->period = period;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_AP_CONN_INACT_CMDID, NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_ap_bgscan_time(struct wmi_t *wmip, A_UINT32 period, A_UINT32 dwell)
+{
+    WMI_AP_PROT_SCAN_TIME_CMD *cmd;
+    void *osbuf = NULL;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(WMI_AP_PROT_SCAN_TIME_CMD));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(WMI_AP_PROT_SCAN_TIME_CMD));
+    cmd = (WMI_AP_PROT_SCAN_TIME_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+
+    cmd->period_min = period;
+    cmd->dwell_ms   = dwell;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_AP_PROT_SCAN_TIME_CMDID, NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_ap_set_dtim(struct wmi_t *wmip, A_UINT8 dtim)
+{
+    WMI_AP_SET_DTIM_CMD *cmd;
+    void *osbuf = NULL;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(WMI_AP_SET_DTIM_CMD));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(WMI_AP_SET_DTIM_CMD));
+    cmd = (WMI_AP_SET_DTIM_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+
+    cmd->dtim = dtim;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_AP_SET_DTIM_CMDID, NO_SYNC_WMIFLAG));
+}
+
+/*
+ * IOCTL: AR6000_XIOCTL_AP_SET_ACL_POLICY
+ *
+ * This command is used to set ACL policay. While changing policy, if you
+ * want to retain the existing MAC addresses in the ACL list, policy should be
+ * OR with AP_ACL_RETAIN_LIST_MASK, else the existing list will be cleared.
+ * If there is no chage in policy, the list will be intact.
+ */
+A_STATUS
+wmi_ap_set_acl_policy(struct wmi_t *wmip, A_UINT8 policy)
+{
+    void *osbuf;
+    WMI_AP_ACL_POLICY_CMD *po;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(WMI_AP_ACL_POLICY_CMD));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+}
+
+    A_NETBUF_PUT(osbuf, sizeof(WMI_AP_ACL_POLICY_CMD));
+    po = (WMI_AP_ACL_POLICY_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(po, sizeof(*po));
+
+    po->policy = policy;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_AP_ACL_POLICY_CMDID, NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_ap_set_rateset(struct wmi_t *wmip, A_UINT8 rateset)
+{
+    void *osbuf;
+    WMI_AP_SET_11BG_RATESET_CMD *rs;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(WMI_AP_SET_11BG_RATESET_CMD));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(WMI_AP_SET_11BG_RATESET_CMD));
+    rs = (WMI_AP_SET_11BG_RATESET_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(rs, sizeof(*rs));
+
+    rs->rateset = rateset;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_AP_SET_11BG_RATESET_CMDID, NO_SYNC_WMIFLAG));
+}
+
+#ifdef ATH_AR6K_11N_SUPPORT
+A_STATUS
+wmi_set_ht_cap_cmd(struct wmi_t *wmip, WMI_SET_HT_CAP_CMD *cmd)
+{
+    void *osbuf;
+    WMI_SET_HT_CAP_CMD *htCap;
+    A_UINT8 band;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*htCap));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*htCap));
+
+    band = (cmd->band)? A_BAND_5GHZ : A_BAND_24GHZ;
+    wmip->wmi_ht_allowed[band] = (cmd->enable)? 1:0;
+
+    htCap = (WMI_SET_HT_CAP_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(htCap, sizeof(*htCap));
+    A_MEMCPY(htCap, cmd, sizeof(*htCap));
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_HT_CAP_CMDID,
+                         NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_ht_op_cmd(struct wmi_t *wmip, A_UINT8 sta_chan_width)
+{
+    void *osbuf;
+    WMI_SET_HT_OP_CMD *htInfo;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*htInfo));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*htInfo));
+
+    htInfo = (WMI_SET_HT_OP_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(htInfo, sizeof(*htInfo));
+    htInfo->sta_chan_width = sta_chan_width;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_HT_OP_CMDID,
+                         NO_SYNC_WMIFLAG));
+}
+#endif
+
+A_STATUS
+wmi_set_tx_select_rates_cmd(struct wmi_t *wmip, A_UINT32 *pMaskArray)
+{
+    void *osbuf;
+    WMI_SET_TX_SELECT_RATES_CMD *pData;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*pData));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*pData));
+
+    pData = (WMI_SET_TX_SELECT_RATES_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMCPY(pData, pMaskArray, sizeof(*pData));
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_TX_SELECT_RATES_CMDID,
+                         NO_SYNC_WMIFLAG));
+}
+
+
+A_STATUS
+wmi_send_hci_cmd(struct wmi_t *wmip, A_UINT8 *buf, A_UINT16 sz)
+{
+    void *osbuf;
+    WMI_HCI_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd) + sz);
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd) + sz);
+    cmd = (WMI_HCI_CMD *)(A_NETBUF_DATA(osbuf));
+
+    cmd->cmd_buf_sz = sz;
+    A_MEMCPY(cmd->buf, buf, sz);
+    return (wmi_cmd_send(wmip, osbuf, WMI_HCI_CMD_CMDID, NO_SYNC_WMIFLAG));
+}
+
+#ifdef ATH_AR6K_11N_SUPPORT
+A_STATUS
+wmi_allow_aggr_cmd(struct wmi_t *wmip, A_UINT16 tx_tidmask, A_UINT16 rx_tidmask)
+{
+    void *osbuf;
+    WMI_ALLOW_AGGR_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_ALLOW_AGGR_CMD *)(A_NETBUF_DATA(osbuf));
+    cmd->tx_allow_aggr = tx_tidmask;
+    cmd->rx_allow_aggr = rx_tidmask;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_ALLOW_AGGR_CMDID, NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_setup_aggr_cmd(struct wmi_t *wmip, A_UINT8 tid)
+{
+    void *osbuf;
+    WMI_ADDBA_REQ_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_ADDBA_REQ_CMD *)(A_NETBUF_DATA(osbuf));
+    cmd->tid = tid;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_ADDBA_REQ_CMDID, NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_delete_aggr_cmd(struct wmi_t *wmip, A_UINT8 tid, A_BOOL uplink)
+{
+    void *osbuf;
+    WMI_DELBA_REQ_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_DELBA_REQ_CMD *)(A_NETBUF_DATA(osbuf));
+    cmd->tid = tid;
+    cmd->is_sender_initiator = uplink;  /* uplink =1 - uplink direction, 0=downlink direction */
+
+    /* Delete the local aggr state, on host */
+    return (wmi_cmd_send(wmip, osbuf, WMI_DELBA_REQ_CMDID, NO_SYNC_WMIFLAG));
+}
+#endif
+
+A_STATUS
+wmi_set_rx_frame_format_cmd(struct wmi_t *wmip, A_UINT8 rxMetaVersion,
+                            A_BOOL rxDot11Hdr, A_BOOL defragOnHost)
+{
+    void *osbuf;
+    WMI_RX_FRAME_FORMAT_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_RX_FRAME_FORMAT_CMD *)(A_NETBUF_DATA(osbuf));
+    cmd->dot11Hdr = (rxDot11Hdr==TRUE)? 1:0;
+    cmd->defragOnHost = (defragOnHost==TRUE)? 1:0;
+    cmd->metaVersion = rxMetaVersion;  /*  */
+
+    /* Delete the local aggr state, on host */
+    return (wmi_cmd_send(wmip, osbuf, WMI_RX_FRAME_FORMAT_CMDID, NO_SYNC_WMIFLAG));
+}
+
+
+A_STATUS
+wmi_set_thin_mode_cmd(struct wmi_t *wmip, A_BOOL bThinMode)
+{
+    void *osbuf;
+    WMI_SET_THIN_MODE_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_SET_THIN_MODE_CMD *)(A_NETBUF_DATA(osbuf));
+    cmd->enable = (bThinMode==TRUE)? 1:0;
+
+    /* Delete the local aggr state, on host */
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_THIN_MODE_CMDID, NO_SYNC_WMIFLAG));
+}
+
+
+A_STATUS
+wmi_set_wlan_conn_precedence_cmd(struct wmi_t *wmip, BT_WLAN_CONN_PRECEDENCE precedence)
+{
+    void *osbuf;
+    WMI_SET_BT_WLAN_CONN_PRECEDENCE *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_SET_BT_WLAN_CONN_PRECEDENCE *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+    cmd->precedence = precedence;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_BT_WLAN_CONN_PRECEDENCE_CMDID,
+                         NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_pmk_cmd(struct wmi_t *wmip, A_UINT8 *pmk)
+{
+    void *osbuf;
+    WMI_SET_PMK_CMD *p;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(WMI_SET_PMK_CMD));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(WMI_SET_PMK_CMD));
+
+    p = (WMI_SET_PMK_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(p, sizeof(*p));
+
+    A_MEMCPY(p->pmk, pmk, WMI_PMK_LEN);
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_PMK_CMDID, NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_SGI_cmd(struct wmi_t *wmip, A_UINT32 sgiMask, A_UINT8 sgiPERThreshold)
+{
+    void *osbuf;
+    WMI_SET_TX_SGI_PARAM_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY ;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_SET_TX_SGI_PARAM_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+    cmd->sgiMask = sgiMask;
+    cmd->sgiPERThreshold = sgiPERThreshold;
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_TX_SGI_PARAM_CMDID,
+                         NO_SYNC_WMIFLAG));
+}
+
+bss_t *
+wmi_find_matching_Ssidnode (struct wmi_t *wmip, A_UCHAR *pSsid,
+                   A_UINT32 ssidLength,
+                   A_UINT32 dot11AuthMode, A_UINT32 authMode,
+                   A_UINT32 pairwiseCryptoType, A_UINT32 grpwiseCryptoTyp)
+{
+    bss_t *node = NULL;
+    node = wlan_find_matching_Ssidnode (&wmip->wmi_scan_table, pSsid,
+                               ssidLength, dot11AuthMode, authMode, pairwiseCryptoType, grpwiseCryptoTyp);
+
+    return node;
+}
+
+A_UINT16
+wmi_ieee2freq (int chan)
+{
+    A_UINT16 freq = 0;
+    freq = wlan_ieee2freq (chan);
+    return freq;
+
+}
+
+A_UINT32
+wmi_freq2ieee (A_UINT16 freq)
+{
+    A_UINT16 chan = 0;
+    chan = wlan_freq2ieee (freq);
+    return chan;
+}
diff --git a/drivers/net/ath6kl/wmi/wmi_host.h b/drivers/net/ath6kl/wmi/wmi_host.h
new file mode 100644
index 00000000000..5c7f7d3c3ce
--- /dev/null
+++ b/drivers/net/ath6kl/wmi/wmi_host.h
@@ -0,0 +1,102 @@
+//------------------------------------------------------------------------------
+// <copyright file="wmi_host.h" company="Atheros">
+//    Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// This file contains local definitios for the wmi host module.
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _WMI_HOST_H_
+#define _WMI_HOST_H_
+
+#include "roaming.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct wmi_stats {
+    A_UINT32    cmd_len_err;
+    A_UINT32    cmd_id_err;
+};
+
+#define SSID_IE_LEN_INDEX 13
+
+/* Host side link management data structures */
+#define SIGNAL_QUALITY_THRESHOLD_LEVELS 6
+#define SIGNAL_QUALITY_UPPER_THRESHOLD_LEVELS SIGNAL_QUALITY_THRESHOLD_LEVELS
+#define SIGNAL_QUALITY_LOWER_THRESHOLD_LEVELS SIGNAL_QUALITY_THRESHOLD_LEVELS
+typedef struct sq_threshold_params_s {
+    A_INT16 upper_threshold[SIGNAL_QUALITY_UPPER_THRESHOLD_LEVELS];
+    A_INT16 lower_threshold[SIGNAL_QUALITY_LOWER_THRESHOLD_LEVELS];
+    A_UINT32 upper_threshold_valid_count;
+    A_UINT32 lower_threshold_valid_count;
+    A_UINT32 polling_interval;
+    A_UINT8 weight;
+    A_UINT8  last_rssi; //normally you would expect this to be bss specific but we keep only one instance because its only valid when the device is in a connected state. Not sure if it belongs to host or target.
+    A_UINT8  last_rssi_poll_event; //Not sure if it belongs to host or target
+} SQ_THRESHOLD_PARAMS;
+
+/*
+ * These constants are used with A_WLAN_BAND_SET.
+ */ 
+#define A_BAND_24GHZ           0
+#define A_BAND_5GHZ            1
+#define A_NUM_BANDS            2
+
+struct wmi_t {
+    A_BOOL                          wmi_ready;
+    A_BOOL                          wmi_numQoSStream;
+    A_UINT16                        wmi_streamExistsForAC[WMM_NUM_AC];
+    A_UINT8                         wmi_fatPipeExists;
+    void                           *wmi_devt;
+    struct wmi_stats                wmi_stats;
+    struct ieee80211_node_table     wmi_scan_table;
+    A_UINT8                         wmi_bssid[ATH_MAC_LEN];
+    A_UINT8                         wmi_powerMode;
+    A_UINT8                         wmi_phyMode;
+    A_UINT8                         wmi_keepaliveInterval;
+#ifdef THREAD_X
+    A_CSECT_T                       wmi_lock;
+#else 
+    A_MUTEX_T                       wmi_lock;
+#endif
+    HTC_ENDPOINT_ID                 wmi_endpoint_id;
+    SQ_THRESHOLD_PARAMS             wmi_SqThresholdParams[SIGNAL_QUALITY_METRICS_NUM_MAX];
+    CRYPTO_TYPE                     wmi_pair_crypto_type;
+    CRYPTO_TYPE                     wmi_grp_crypto_type;
+    A_BOOL                          wmi_is_wmm_enabled;
+    A_UINT8                         wmi_ht_allowed[A_NUM_BANDS];
+    A_UINT8                         wmi_traffic_class;
+};
+
+#ifdef THREAD_X
+#define INIT_WMI_LOCK(w)    A_CSECT_INIT(&(w)->wmi_lock)
+#define LOCK_WMI(w)         A_CSECT_ENTER(&(w)->wmi_lock);
+#define UNLOCK_WMI(w)       A_CSECT_LEAVE(&(w)->wmi_lock);
+#define DELETE_WMI_LOCK(w)  A_CSECT_DELETE(&(w)->wmi_lock);
+#else
+#define LOCK_WMI(w)     A_MUTEX_LOCK(&(w)->wmi_lock);
+#define UNLOCK_WMI(w)   A_MUTEX_UNLOCK(&(w)->wmi_lock);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _WMI_HOST_H_ */
diff --git a/drivers/net/ax88796c/Makefile b/drivers/net/ax88796c/Makefile
new file mode 100644
index 00000000000..7a99e918098
--- /dev/null
+++ b/drivers/net/ax88796c/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_JZ_AX88796C)   += ax88796c.o ax88796c_dma.o
diff --git a/drivers/net/ax88796c/ax88796c.c b/drivers/net/ax88796c/ax88796c.c
new file mode 100644
index 00000000000..6f4e6c2b49a
--- /dev/null
+++ b/drivers/net/ax88796c/ax88796c.c
@@ -0,0 +1,2684 @@
+/*
+ * ASIX AX88796C based Fast Ethernet Devices
+ * Copyright (C) 2009 ASIX Electronics Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include "ax88796c.h"
+#include "ax88796c_ioctl.h"
+#include <linux/jiffies.h>
+#include <asm/jzsoc.h>
+
+/* Naming constant declarations */
+
+/* Local variables declarations */
+static char version[] =
+KERN_INFO AX88796C_ADP_NAME ":v" AX88796C_DRV_VERSION
+" " __TIME__ " " __DATE__ "\n"
+KERN_INFO "  http://www.asix.com.tw\n";
+#if (AX88796C_8BIT_MODE)
+static int bus_wide = 0;
+#else
+static int bus_wide = 1;
+#endif
+
+static int mem;
+static int irq;
+static int ps_level = AX_PS_D0;
+static int msg_enable = (NETIF_MSG_DRV |
+			 NETIF_MSG_PROBE |
+			 NETIF_MSG_LINK |
+			 NETIF_MSG_IFUP |
+			 NETIF_MSG_RX_ERR |
+			 NETIF_MSG_TX_ERR |
+			 NETIF_MSG_TX_QUEUED |
+//			 NETIF_MSG_INTR |
+//			 NETIF_MSG_RX_STATUS |
+//			 NETIF_MSG_PKTDATA |
+			 NETIF_MSG_HW |
+			 NETIF_MSG_WOL);
+
+module_param (mem, int, 0);
+module_param (irq, int, 0);
+module_param (msg_enable, int, 0);
+module_param (ps_level, int, 0);
+
+MODULE_PARM_DESC(mem, "MEMORY base address(es), required");
+MODULE_PARM_DESC(irq, "IRQ number(s)");
+MODULE_PARM_DESC(msg_enable, "Message level");
+MODULE_PARM_DESC(ps_level, "Power Saving Level (0:disable 1:level 1 2:level 2)");
+
+MODULE_DESCRIPTION ("ASIX AX88796C Fast Ethernet driver");
+MODULE_LICENSE ("GPL");
+
+/*
+ * ----------------------------------------------------------------------------
+ * Function Name: ax88796c_p2440_config_bank1
+ * Purpose: S3C2440A memory bank configuration
+ * ----------------------------------------------------------------------------
+ */
+static void ax88796c_jz4750_config_bank1 (int bus_type)
+{
+	u32 reg1;
+	int i;
+
+#ifdef CONFIG_SOC_JZ4740
+	__gpio_as_func0(60);             //CS4#
+	__gpio_as_func0(61);             //RD#
+	__gpio_as_func0(62);             //WR#
+	__gpio_as_irq_high_level(59);    //irq
+	__gpio_disable_pull(59);         //disable pull
+	REG_EMC_SMCR4 |= (1 << 6);       //16bit
+
+#elif defined(CONFIG_SOC_JZ4750)
+	__gpio_as_func0(32*2+23);             //CS3#
+	__gpio_as_func0(32*2+25);             //RD#
+	__gpio_as_func0(32*2+26);             //WR#
+
+#  ifdef CONFIG_JZ4750_FUWA
+	__gpio_as_irq_high_level(32*4+20);    //irq
+	__gpio_disable_pull(32*4+20);         //disable pull
+#  else
+	__gpio_as_irq_high_level(32*2 +6);    //irq
+	__gpio_disable_pull(32*2 +6);         //disable pull
+#  endif
+
+	REG_EMC_SMCR3 |= (1 << 6);            //16bit
+
+#elif defined(CONFIG_SOC_JZ4760) || defined(CONFIG_SOC_JZ4760B)
+#define RD_N_PIN (32*0 + 16)
+#define WE_N_PIN (32*0 + 17)
+#define CS6_PIN (32*0 + 26)
+	__gpio_as_func0(CS6_PIN);
+	__gpio_as_func0(RD_N_PIN);
+	__gpio_as_func0(WE_N_PIN);
+
+	__gpio_as_func0(32 * 1 + 0); /* SA0 */
+	__gpio_as_func0(32 * 1 + 1); /* SA1 */
+	__gpio_as_func0(32 * 1 + 2); /* SA2 */
+	__gpio_as_func0(32 * 1 + 3); /* SA3 */
+	__gpio_as_func0(32 * 1 + 4); /* SA4 */
+	__gpio_as_func0(32 * 1 + 5); /* SA5 */
+
+	__gpio_disable_pull(32 * 1 + 23);
+	__gpio_as_output(32 * 1 + 23);
+	__gpio_set_pin(32 * 1 + 23);
+	mdelay(10);
+	for (i = 0; i < 5280; i++)
+		__gpio_clear_pin(32 * 1 + 23);
+	mdelay(10);
+	__gpio_set_pin(32 * 1 + 23);
+	/* wait until AX88796c stable */
+	mdelay(10);
+
+	reg1 = REG_NEMC_SMCR6;
+	reg1 = (reg1 & (~NEMC_SMCR_BW_MASK)) | NEMC_SMCR_BW_16BIT;
+	REG_NEMC_SMCR6 = reg1;
+
+#if 0
+#  ifdef CONFIG_JZ4760_LEPUS
+	/* We use CS6 with 16-bit data width */
+	__gpio_as_func0(32 * 0 + 26);		/* GPA26 CS6# */
+	__gpio_as_func0(32 * 0 + 16);		/* GPA16 RD#  */
+	__gpio_as_func0(32 * 0 + 17);		/* GPA17 WE#  */
+
+	__gpio_as_func0(32 * 1 + 0); /* SA0 */
+	__gpio_as_func0(32 * 1 + 1); /* SA1 */
+	__gpio_as_func0(32 * 1 + 2); /* SA2 */
+	__gpio_as_func0(32 * 1 + 3); /* SA3 */
+	__gpio_as_func0(32 * 1 + 4); /* SA4 */
+	__gpio_as_func0(32 * 1 + 5); /* SA5 */
+
+	//REG_NEMC_SMCR6 &= ~EMC_SMCR_BW_MASK;
+	//REG_NEMC_SMCR6 |= EMC_SMCR_BW_16BIT;
+  //printk("**********REG_NEMC_SMCR6 = %08x\n", REG_NEMC_SMCR6);
+#  elif CONFIG_JZ4760_CYGNUS
+        /* We use CS5 with 16-bit data width */
+	__gpio_as_func0(32 * 0 + 25);		/* GPA25 CS5# */
+	__gpio_as_func0(32 * 0 + 16);		/* GPA16 RD#  */
+	__gpio_as_func0(32 * 0 + 17);		/* GPA17 WE#  */
+
+	REG_EMC_SMCR5 &= ~EMC_SMCR_BW_MASK;
+	REG_EMC_SMCR5 |= EMC_SMCR_BW_16BIT;
+#  endif
+#endif
+	__gpio_as_irq_high_level(GPIO_NET_INT);	/* irq */
+	__gpio_disable_pull(GPIO_NET_INT);	/* disable pull */
+#endif
+	udelay(1);
+}
+
+
+void ax88796c_platform_init (int bus_type)
+{
+	ax88796c_jz4750_config_bank1 (bus_type);
+}
+
+
+/* NAMING CONSTANT DECLARATIONS */
+
+
+/* LOCAL SUBPROGRAM DECLARATIONS */
+/*
+ * ----------------------------------------------------------------------------
+ * Function Name: ax88796c_check_power_state
+ * Purpose: Check AX88796C power saving status
+ * ----------------------------------------------------------------------------
+ */
+u8 ax88796c_check_power_state (struct net_device *ndev)
+{
+	struct ax88796c_device *ax_local = netdev_priv (ndev);
+	void __iomem *ax_base = ax_local->membase;
+	u16 power;
+
+	/* Check media link status first */
+	if (netif_carrier_ok (ndev) || (ax_local->ps_level == AX_PS_D0)
+	    || (ax_local->ps_level == AX_PS_D1))
+		return 0;
+
+	power = AX_READ (ax_base + P0_MACCR) & MACCR_PMM_MASK;
+	if (power != MACCR_PMM_READY) {
+		unsigned long start;
+		AX_WRITE (0xFF, ax_base + PG_HOST_WAKEUP);
+		start = jiffies;
+		while (power != MACCR_PMM_READY) {
+			if ((jiffies - start) > (2*HZ / 10)) {	/* 200ms */
+                        	printk (KERN_ERR
+                                	"%s: timeout waiting for waking\n",
+                                	ax_local->ndev->name);
+                        	break;
+			}
+			power = AX_READ (ax_base + P0_MACCR) & MACCR_PMM_MASK;
+		}
+		return 1;
+	}
+
+	return 0;
+}
+
+/*
+ * ----------------------------------------------------------------------------
+ * Function Name: ax88796c_set_power_saving
+ * Purpose: Set up AX88796C power saving
+ * ----------------------------------------------------------------------------
+ */
+void ax88796c_set_power_saving (struct net_device *ndev, u8 ps_level)
+{
+	struct ax88796c_device *ax_local = netdev_priv (ndev);
+	void __iomem *ax_base = ax_local->membase;
+	u16 pmm;
+
+	if (ps_level == AX_PS_D1) {
+		pmm = PSCR_PS_D1;
+	} else if (ps_level == AX_PS_D2) {
+		pmm = PSCR_PS_D2;
+	} else {
+		pmm = PSCR_PS_D0;
+	}
+
+        AX_WRITE ((AX_READ (ax_base + P0_PSCR) & PSCR_PS_MASK) |
+                        pmm, ax_base + P0_PSCR);
+}
+
+/*
+ * ----------------------------------------------------------------------------
+ * Function Name: ax88796c_mdio_read_phy
+ * Purpose: Read phy register via mdio interface
+ * ----------------------------------------------------------------------------
+ */
+int ax88796c_mdio_read_phy (struct net_device *ndev, int phy_id, int loc)
+{
+	struct ax88796c_device *ax_local = netdev_priv (ndev);
+	unsigned long start_time;
+	void __iomem *ax_base = ax_local->membase;
+	u16 val;
+
+	AX_SELECT_PAGE (PAGE2, ax_base + PG_PSR);
+
+	AX_WRITE (MDIOCR_RADDR (loc) | MDIOCR_FADDR (phy_id) | MDIOCR_READ,
+				P2_MDIOCR + ax_base);
+
+
+	start_time = jiffies;
+	while ((AX_READ (P2_MDIOCR + ax_base) & MDIOCR_VALID) == 0) {
+		printk("===>in %s\n", __func__);
+#if 0
+		if (time_after (jiffies, start_time + HZ/100)) {
+			return -EBUSY;
+		}
+#endif
+	}
+
+
+	val = AX_READ (P2_MDIODR + ax_base);
+
+	AX_SELECT_PAGE (PAGE0, ax_base + PG_PSR);
+
+	return val;
+}
+
+/*
+ * ----------------------------------------------------------------------------
+ * Function Name: ax88796c_mdio_read
+ * Purpose: Exported for upper layer to read PHY register
+ * ----------------------------------------------------------------------------
+ */
+int ax88796c_mdio_read (struct net_device *ndev, int phy_id, int loc)
+{
+	struct ax88796c_device *ax_local = netdev_priv (ndev);
+	u16 val;
+	unsigned long flags;
+	u8 power;
+
+	spin_lock_irqsave (&ax_local->isr_lock, flags);
+
+	power = ax88796c_check_power_state (ndev);
+
+	val = ax88796c_mdio_read_phy (ndev, phy_id, loc);
+
+	if (power)
+		ax88796c_set_power_saving (ndev, ax_local->ps_level);
+
+	spin_unlock_irqrestore (&ax_local->isr_lock, flags);
+
+	return val;
+}
+
+/*
+ * ----------------------------------------------------------------------------
+ * Function Name: ax88796c_mdio_write_phy
+ * Purpose: Write phy register via mdio interface
+ * ----------------------------------------------------------------------------
+ */
+void
+ax88796c_mdio_write_phy (struct net_device *ndev, int phy_id, int loc, int val)
+{
+	struct ax88796c_device *ax_local = netdev_priv (ndev);
+	void __iomem *ax_base = ax_local->membase;
+	unsigned long start_time;
+
+	AX_SELECT_PAGE(PAGE2, ax_base + PG_PSR);
+
+	AX_WRITE (val, P2_MDIODR + ax_base);
+
+	AX_WRITE (MDIOCR_RADDR (loc) | MDIOCR_FADDR (phy_id) | MDIOCR_WRITE,
+						 P2_MDIOCR + ax_base);
+
+	start_time = jiffies;
+	while ((AX_READ (P2_MDIOCR + ax_base) & MDIOCR_VALID) == 0) {
+		if (time_after (jiffies, start_time + HZ/100)) {
+			return;
+		}
+	}
+
+	if (loc == MII_ADVERTISE) {
+		AX_WRITE ((BMCR_FULLDPLX | BMCR_ANRESTART |
+			  BMCR_ANENABLE | BMCR_SPEED100), P2_MDIODR + ax_base);
+		AX_WRITE ((MDIOCR_RADDR (MII_BMCR) |
+			  MDIOCR_FADDR (phy_id) | MDIOCR_WRITE),
+			  P2_MDIOCR + ax_base);
+
+		start_time = jiffies;
+		while ((AX_READ (P2_MDIOCR + ax_base) & MDIOCR_VALID) == 0) {
+			printk("===>in %s:%d\n", __func__, __LINE__);
+#if 0
+			if (time_after (jiffies, start_time + HZ/100)) {
+				return;
+			}
+#endif
+		}
+	}
+
+	AX_SELECT_PAGE (PAGE0, ax_base + PG_PSR);
+}
+
+/*
+ * ----------------------------------------------------------------------------
+ * Function Name: ax88796c_mdio_write
+ * Purpose: Exported for upper layer to write PHY register
+ * ----------------------------------------------------------------------------
+ */
+void ax88796c_mdio_write (struct net_device *ndev, int phy_id, int loc, int val)
+{
+	struct ax88796c_device *ax_local = netdev_priv (ndev);
+	unsigned long flags;
+	u8 power;
+
+	spin_lock_irqsave (&ax_local->isr_lock, flags);
+
+	power = ax88796c_check_power_state (ndev);
+
+	ax88796c_mdio_write_phy (ndev, phy_id, loc, val);
+
+	if (power)
+		ax88796c_set_power_saving (ndev, ax_local->ps_level);
+
+	spin_unlock_irqrestore (&ax_local->isr_lock, flags);
+}
+
+/*
+ * ----------------------------------------------------------------------------
+ * Function Name: ax88796c_set_csums
+ * Purpose: Initialize hardware checksum.
+ * ----------------------------------------------------------------------------
+ */
+void ax88796c_set_csums (struct net_device *ndev)
+{
+	struct ax88796c_device *ax_local = netdev_priv (ndev);
+	void __iomem *ax_base = ax_local->membase;
+	unsigned long flags;
+	u8 power;
+
+	spin_lock_irqsave (&ax_local->isr_lock, flags);
+
+	power = ax88796c_check_power_state (ndev);
+
+	AX_SELECT_PAGE (PAGE4, ax_base + PG_PSR);
+
+	if (ax_local->checksum & AX_RX_CHECKSUM) {
+		AX_WRITE (COERCR0_DEFAULT, ax_base + P4_COERCR0);
+		AX_WRITE (COERCR1_DEFAULT, ax_base + P4_COERCR1);
+	} else {
+		AX_WRITE (0, ax_base + P4_COERCR0);
+		AX_WRITE (0, ax_base + P4_COERCR1);
+	}
+
+	if (ax_local->checksum & AX_TX_CHECKSUM) {
+		AX_WRITE (COETCR0_DEFAULT, ax_base + P4_COETCR0);
+	} else {
+		AX_WRITE (0, ax_base + P4_COETCR0);
+	}
+
+	AX_SELECT_PAGE (PAGE0, ax_base + PG_PSR);
+
+	if (power)
+		ax88796c_set_power_saving (ndev, ax_local->ps_level);
+
+	spin_unlock_irqrestore (&ax_local->isr_lock, flags);
+}
+
+/*
+ * ----------------------------------------------------------------------------
+ * Function Name: ax88796c_get_drvinfo
+ * Purpose: Exported for Ethtool to query the driver version
+ * ----------------------------------------------------------------------------
+ */
+static void ax88796c_get_drvinfo (struct net_device *ndev,
+				 struct ethtool_drvinfo *info)
+{
+	/* Inherit standard device info */
+	strncpy (info->driver, AX88796C_DRV_NAME, sizeof info->driver);
+	strncpy (info->version, AX88796C_DRV_VERSION, sizeof info->version);
+}
+
+/*
+ * ----------------------------------------------------------------------------
+ * Function Name: ax88796c_get_link
+ * Purpose: Exported for Ethtool to query the media link status
+ * ----------------------------------------------------------------------------
+ */
+static u32 ax88796c_get_link (struct net_device *ndev)
+{
+	struct ax88796c_device *ax_local = netdev_priv (ndev);
+	return mii_link_ok (&ax_local->mii);
+}
+
+/*
+ * ----------------------------------------------------------------------------
+ * Function Name: ax88796c_get_wol
+ * Purpose: Exported for Ethtool to query wake on lan setting
+ * ----------------------------------------------------------------------------
+ */
+static void
+ax88796c_get_wol (struct net_device *ndev, struct ethtool_wolinfo *wolinfo)
+{
+	struct ax88796c_device *ax_local = netdev_priv (ndev);
+
+	wolinfo->supported = WAKE_PHY | WAKE_MAGIC | WAKE_ARP;
+	wolinfo->wolopts = 0;
+
+	if (ax_local->wol & WFCR_LINKCH)
+		wolinfo->wolopts |= WAKE_PHY;
+	if (ax_local->wol & WFCR_MAGICP)
+		wolinfo->wolopts |= WAKE_MAGIC;
+	if (ax_local->wol & WFCR_WAKEF)
+		wolinfo->wolopts |= WAKE_ARP;
+}
+
+/*
+ * ----------------------------------------------------------------------------
+ * Function Name: ax88796c_set_wol
+ * Purpose: Exported for Ethtool to set the wake on lan setting
+ * ----------------------------------------------------------------------------
+ */
+static int
+ax88796c_set_wol (struct net_device *ndev, struct ethtool_wolinfo *wolinfo)
+{
+	struct ax88796c_device *ax_local = netdev_priv (ndev);
+
+	ax_local->wol = 0;
+
+	if (wolinfo->wolopts & WAKE_PHY)
+		ax_local->wol |= WFCR_LINKCH;
+	if (wolinfo->wolopts & WAKE_MAGIC)
+		ax_local->wol |= WFCR_MAGICP;
+	if (wolinfo->wolopts & WAKE_ARP) {
+		ax_local->wol |= WFCR_WAKEF;
+	}
+
+	return 0;
+}
+
+/*
+ * ----------------------------------------------------------------------------
+ * Function Name: ax88796c_get_settings
+ * Purpose: Exported for Ethtool to query PHY setting
+ * ----------------------------------------------------------------------------
+ */
+static int
+ax88796c_get_settings (struct net_device *ndev, struct ethtool_cmd *cmd)
+{
+	struct ax88796c_device *ax_local = netdev_priv (ndev);
+
+	return mii_ethtool_gset(&ax_local->mii, cmd);
+}
+
+/*
+ * ----------------------------------------------------------------------------
+ * Function Name: ax88796c_set_settings
+ * Purpose: Exported for Ethtool to set PHY setting
+ * ----------------------------------------------------------------------------
+ */
+static int
+ax88796c_set_settings (struct net_device *ndev, struct ethtool_cmd *cmd)
+{
+	struct ax88796c_device *ax_local = netdev_priv (ndev);
+	int retval;
+
+	retval = mii_ethtool_sset (&ax_local->mii, cmd);
+
+	return retval;
+
+}
+
+/*
+ * ----------------------------------------------------------------------------
+ * Function Name: ax88796c_nway_reset
+ * Purpose: Exported for Ethtool to restart PHY autonegotiation
+ * ----------------------------------------------------------------------------
+ */
+static int ax88796c_nway_reset (struct net_device *ndev)
+{
+	struct ax88796c_device *ax_local = netdev_priv (ndev);
+	return mii_nway_restart(&ax_local->mii);
+}
+
+/*
+ * ----------------------------------------------------------------------------
+ * Function Name: ax88796c_ethtool_getmsglevel
+ * Purpose: Exported for Ethtool to query driver message level
+ * ----------------------------------------------------------------------------
+ */
+static u32 ax88796c_ethtool_getmsglevel (struct net_device *ndev)
+{
+	struct ax88796c_device *ax_local = netdev_priv (ndev);
+	return ax_local->msg_enable;
+}
+
+/*
+ * ----------------------------------------------------------------------------
+ * Function Name: ax88796c_ethtool_setmsglevel
+ * Purpose: Exported for Ethtool to set driver message level
+ * ----------------------------------------------------------------------------
+ */
+static void ax88796c_ethtool_setmsglevel (struct net_device *ndev, u32 level)
+{
+	struct ax88796c_device *ax_local = netdev_priv (ndev);
+	ax_local->msg_enable = level;
+}
+
+/*
+ * ----------------------------------------------------------------------------
+ * Function Name: ax88796c_get_rx_csum
+ * Purpose: Exported for Ethtool to query receive checksum setting
+ * ----------------------------------------------------------------------------
+ */
+static u32 ax88796c_get_rx_csum (struct net_device *ndev)
+{
+	struct ax88796c_device *ax_local = netdev_priv (ndev);
+
+	return (ax_local->checksum & AX_RX_CHECKSUM);
+}
+
+/*
+ * ----------------------------------------------------------------------------
+ * Function Name: ax88796c_set_rx_csum
+ * Purpose: Exported for Ethtool to set receive checksum setting
+ * ----------------------------------------------------------------------------
+ */
+static int ax88796c_set_rx_csum (struct net_device *ndev, u32 val)
+{
+	struct ax88796c_device *ax_local = netdev_priv (ndev);
+
+	if (val)
+		ax_local->checksum |= AX_RX_CHECKSUM;
+	else
+		ax_local->checksum &= ~AX_RX_CHECKSUM;
+
+	ax88796c_set_csums (ndev);
+
+	return 0;
+}
+
+/*
+ * ----------------------------------------------------------------------------
+ * Function Name: ax88796c_get_tx_csum
+ * Purpose: Exported for Ethtool to query transmit checksum setting
+ * ----------------------------------------------------------------------------
+ */
+static u32 ax88796c_get_tx_csum (struct net_device *ndev)
+{
+	struct ax88796c_device *ax_local = netdev_priv (ndev);
+
+	return (ax_local->checksum & AX_TX_CHECKSUM);
+}
+
+/*
+ * ----------------------------------------------------------------------------
+ * Function Name: ax88796c_set_tx_csum
+ * Purpose: Exported for Ethtool to set transmit checksum setting
+ * ----------------------------------------------------------------------------
+ */
+static int ax88796c_set_tx_csum (struct net_device *ndev, u32 val)
+{
+	struct ax88796c_device *ax_local = netdev_priv (ndev);
+
+	if (val)
+		ax_local->checksum |= AX_TX_CHECKSUM;
+	else
+		ax_local->checksum &= ~AX_TX_CHECKSUM;
+
+	ethtool_op_set_tx_hw_csum (ndev, val);
+	ax88796c_set_csums (ndev);
+
+	return 0;
+}
+
+struct ethtool_ops ax88796c_ethtool_ops = {
+	.get_drvinfo		= ax88796c_get_drvinfo,
+	.get_link		= ax88796c_get_link,
+	.get_wol		= ax88796c_get_wol,
+	.set_wol		= ax88796c_set_wol,
+	.get_settings		= ax88796c_get_settings,
+	.set_settings		= ax88796c_set_settings,
+	.nway_reset		= ax88796c_nway_reset,
+	.get_msglevel		= ax88796c_ethtool_getmsglevel,
+	.set_msglevel		= ax88796c_ethtool_setmsglevel,
+	.get_tx_csum		= ax88796c_get_tx_csum,
+	.set_tx_csum		= ax88796c_set_tx_csum,
+	.get_rx_csum		= ax88796c_get_rx_csum,
+	.set_rx_csum		= ax88796c_set_rx_csum,
+};
+
+void ioctl_signature (struct ax88796c_device *ax_local, AX_IOCTL_COMMAND *info)
+{
+	strncpy (info->sig, AX88796C_DRV_NAME, strlen (AX88796C_DRV_NAME));
+}
+
+void ioctl_config_test_pkt (struct ax88796c_device *ax_local, AX_IOCTL_COMMAND *info)
+{
+	void __iomem *ax_base = ax_local->membase;
+	unsigned long flags;
+	unsigned short reg_data = 0x1500;
+	unsigned short phy_reg;
+
+	strncpy (info->sig, AX88796C_DRV_NAME, strlen (AX88796C_DRV_NAME));
+
+	spin_lock_irqsave (&ax_local->isr_lock, flags);
+
+
+	/* Disable force media link up at 10M first */
+	phy_reg = ax88796c_mdio_read_phy (ax_local->ndev,
+				ax_local->mii.phy_id, 0x10);
+	ax88796c_mdio_write_phy (ax_local->ndev, ax_local->mii.phy_id,
+				0x10, (phy_reg & 0xFFFE));
+	if (info->speed == 100) {
+
+		/* Force media link at speed 100 */
+		ax88796c_mdio_write_phy (ax_local->ndev, ax_local->mii.phy_id,
+				MII_BMCR, (BMCR_SPEED100 | BMCR_FULLDPLX));
+
+	} else if (info->speed == 10) {
+
+		/* Force media link at speed 10 */
+		ax88796c_mdio_write_phy (ax_local->ndev, ax_local->mii.phy_id,
+				MII_BMCR, 0);
+
+		/* Force media link up */
+		phy_reg = ax88796c_mdio_read_phy (ax_local->ndev,
+				ax_local->mii.phy_id, 0x10);
+		ax88796c_mdio_write_phy (ax_local->ndev, ax_local->mii.phy_id,
+				0x10, (phy_reg | 1));
+
+	} else {
+		/* Restart PHY autoneg */
+		ax88796c_mdio_write_phy (ax_local->ndev, ax_local->mii.phy_id,
+				MII_BMCR, (BMCR_ANENABLE | BMCR_ANRESTART));
+	}
+
+	AX_SELECT_PAGE(PAGE3, ax_base + PG_PSR);
+
+	/* Clear current setting */
+	AX_WRITE (reg_data, ax_base + P3_TPCR);
+
+	if (info->type == AX_PACKET_TYPE_FIX) {
+		reg_data |= TPCR_FIXED_PKT_EN | info->pattern;
+	} else if (info->type == AX_PACKET_TYPE_RAND) {
+		reg_data |= TPCR_RAND_PKT_EN;
+	}
+
+	AX_WRITE (info->length, ax_base + P3_TPLR);
+	AX_WRITE (reg_data, ax_base + P3_TPCR);
+
+	AX_SELECT_PAGE(PAGE0, ax_base + PG_PSR);
+	spin_unlock_irqrestore (&ax_local->isr_lock, flags);
+
+}
+
+typedef void (*IOCTRL_TABLE)(struct ax88796c_device *ax_local,
+						AX_IOCTL_COMMAND *info);
+
+IOCTRL_TABLE ioctl_tbl[] = {
+	ioctl_signature,	//AX_SIGNATURE
+	ioctl_config_test_pkt,	//AX_CFG_TEST_PKT
+};
+
+/*
+ * ----------------------------------------------------------------------------
+ * Function Name: ax_ioctl()
+ * Purpose:
+ * Params:
+ * Returns:
+ * Note:
+ * ----------------------------------------------------------------------------
+ */
+int ax88796c_ioctl(struct net_device *ndev, struct ifreq *ifr, int cmd)
+{
+	struct ax88796c_device *ax_local = netdev_priv (ndev);
+	AX_IOCTL_COMMAND info;
+	AX_IOCTL_COMMAND *uptr = (AX_IOCTL_COMMAND *)ifr->ifr_data;
+	int private_cmd;
+	u8 power;
+
+	switch(cmd) {
+
+	case AX_PRIVATE:
+		if ( copy_from_user(&info, uptr, sizeof(AX_IOCTL_COMMAND)) )
+			return -EFAULT;
+
+		private_cmd = info.ioctl_cmd;
+
+		power = ax88796c_check_power_state (ndev);
+
+		(*ioctl_tbl[private_cmd])(ax_local, &info);
+
+		if (power)
+			ax88796c_set_power_saving (ndev, ax_local->ps_level);
+
+		if( copy_to_user( uptr, &info, sizeof(AX_IOCTL_COMMAND) ) )
+				return -EFAULT;
+		break;
+	default:
+		return generic_mii_ioctl(&ax_local->mii, if_mii(ifr), cmd, NULL);
+	}
+
+	return 0;
+}
+
+
+
+
+
+
+
+
+/*
+ * ----------------------------------------------------------------------------
+ * Function Name: ax88796c_dump_regs
+ * Purpose: Dump all MAC registers
+ * ----------------------------------------------------------------------------
+ */
+static void ax88796c_dump_regs (struct ax88796c_device *ax_local)
+{
+	void __iomem *ax_base = ax_local->membase;
+	u8 i, j;
+
+	printk ("       Page0   Page1   Page2   Page3   "
+				"Page4   Page5   Page6   Page7\n");
+	for (i = 0; i < 0x20; i += 2) {
+
+		printk ("0x%02x   ", i);
+		for (j = 0; j < 8; j++) {
+			AX_SELECT_PAGE(j, ax_base + PG_PSR);
+			printk ("0x%04x  ", AX_READ (ax_base + AX_SHIFT (i)));
+		}
+		printk ("\n");
+	}
+	printk ("\n");
+
+}
+
+/*
+ * ----------------------------------------------------------------------------
+ * Function Name: ax88796c_dump_tx_pkt
+ * Purpose: Dump TX packets
+ * ----------------------------------------------------------------------------
+ */
+static void ax88796c_dump_tx_pkt (struct sk_buff *skb)
+{
+	struct skb_data *entry = (struct skb_data *) skb->cb;
+	u8 *buf = (u8 *)&entry->txhdr;
+	int i, total = 0;
+
+	printk ("Dump processed TX packet (len %d)\n",
+			(sizeof (struct tx_header) +
+			entry->dma_len +
+			sizeof (struct tx_eop_header)));
+	for (i = 0; i < sizeof (struct tx_header); i++) {
+		printk ("%02x ", *(buf + i));
+		total++;
+	}
+
+	for (i = 0; i < entry->dma_len; i++) {
+		if ((total % 16) == 0)
+			printk ("\n");
+		printk ("%02x ", *(skb->data + i));
+		total++;
+	}
+
+	buf = (u8 *)&entry->tx_eop;
+	for (i = 0; i < sizeof (struct tx_eop_header); i++) {
+		if ((total % 16) == 0)
+			printk ("\n");
+		printk ("%02x ", *(buf + i));
+		total++;
+	}
+
+	printk ("\n");
+
+}
+
+/*
+ * ----------------------------------------------------------------------------
+ * Function Name: ax88796c_dump_rx_pkt
+ * Purpose: Dump RX packets
+ * ----------------------------------------------------------------------------
+ */
+static void ax88796c_dump_rx_pkt (struct sk_buff *skb)
+{
+	int i;
+	for (i = 0; i < skb->len; i++) {
+		if ((i % 16) == 0)
+			printk ("\n");
+		printk ("%02x ", *(skb->data + i));
+	}
+	printk ("\n");
+}
+
+/*
+ * ----------------------------------------------------------------------------
+ * Function Name: ax88796c_dump_phy_regs
+ * Purpose: Dump PHY register from MR0 to MR5
+ * ----------------------------------------------------------------------------
+ */
+static void ax88796c_dump_phy_regs (struct ax88796c_device *ax_local)
+{
+	int i;
+
+	printk ("Dump PHY registers:\n");
+	for (i = 0; i < 6; i++) {
+		printk ("  MR%d = 0x%04x\n", i,
+			ax88796c_mdio_read_phy (ax_local->ndev,
+						ax_local->mii.phy_id, i));
+	}
+}
+
+/*
+ * ----------------------------------------------------------------------------
+ * Function Name: ax88796c_reset
+ * Purpose: Reset the whol chip
+ * ----------------------------------------------------------------------------
+ */
+static int ax88796c_reset (struct ax88796c_device *ax_local)
+{
+	void __iomem *ax_base = ax_local->membase;
+	unsigned long start;
+
+	AX_WRITE (PSR_RESET, ax_base + PG_PSR);
+	AX_WRITE (PSR_RESET_CLR, ax_base + PG_PSR);
+
+	start = jiffies;
+	while (!(AX_READ (ax_base + PG_PSR) & PSR_DEV_READY))
+	{
+		if ((jiffies - start) > (2*HZ / 100)) {		/* 20ms */
+			printk (KERN_ERR
+				"%s: timeout waiting for reset completion\n",
+				ax_local->ndev->name);
+			return -1;
+		}
+	}
+
+	return 0;
+}
+
+/*
+ * ----------------------------------------------------------------------------
+ * Function Name: ax88796c_reload_eeprom
+ * Purpose: Load eeprom data from eeprom
+ * ----------------------------------------------------------------------------
+ */
+static int ax88796c_reload_eeprom (struct ax88796c_device *ax_local)
+{
+	void __iomem *ax_base = ax_local->membase;
+	unsigned long start;
+
+	AX_SELECT_PAGE(PAGE3, ax_base + PG_PSR);
+	AX_WRITE (EECR_RELOAD , ax_base + P3_EECR);
+
+	start = jiffies;
+	while (!(AX_READ (ax_base + PG_PSR) & PSR_DEV_READY)) {
+		if ((jiffies - start) > (2*HZ / 100)) {		/* 20ms */
+			printk (KERN_ERR
+				"%s: timeout waiting for reload eeprom\n",
+				ax_local->ndev->name);
+			return -1;
+		}
+	}
+
+	AX_SELECT_PAGE(PAGE0, ax_base + PG_PSR);
+	return 0;
+}
+
+/*
+ * ----------------------------------------------------------------------------
+ * Function Name: ax88796c_set_multicast
+ * Purpose: Set receiving mode and multicast filter
+ * ----------------------------------------------------------------------------
+ */
+static void ax88796c_set_multicast (struct net_device *ndev)
+{
+	struct ax88796c_device *ax_local = netdev_priv (ndev);
+	void __iomem *ax_base = ax_local->membase;
+	unsigned long flags;
+	u16 rx_ctl = RXCR_AB;
+	u8 power;
+
+	spin_lock_irqsave (&ax_local->isr_lock, flags);
+
+	power = ax88796c_check_power_state (ndev);
+
+	AX_SELECT_PAGE(PAGE2, ax_base + PG_PSR);
+	if (ndev->flags & IFF_PROMISC) {
+		rx_ctl |= RXCR_PRO;
+	} else if (ndev->flags & IFF_ALLMULTI
+		   || ndev->mc_count > AX_MAX_MCAST) {
+		rx_ctl |= RXCR_AMALL;
+	} else if (ndev->mc_count == 0) {
+		/* just broadcast and directed */
+	} else {
+		/* We use the 20 byte dev->data
+		 * for our 8 byte filter buffer
+		 * to avoid allocating memory that
+		 * is tricky to free later */
+		struct dev_mc_list *mc_list = ndev->mc_list;
+		u32 crc_bits;
+		int i;
+
+		memset(ax_local->multi_filter, 0, AX_MCAST_FILTER_SIZE);
+		/* Build the multicast hash filter. */
+		for (i = 0; i < ndev->mc_count; i++) {
+			crc_bits =
+			    ether_crc (ETH_ALEN,
+				      mc_list->dmi_addr) >> 26;
+			ax_local->multi_filter[crc_bits >> 3] |=
+			    1 << (crc_bits & 7);
+			mc_list = mc_list->next;
+		}
+
+		AX_SELECT_PAGE (PAGE3, ax_base + PG_PSR);
+		for (i = 0; i < 4; i++) {
+			AX_WRITE (((ax_local->multi_filter[i*2+1] << 8) |
+					ax_local->multi_filter[i*2]),
+					ax_base + P3_MFAR(i));
+
+		}
+
+	}
+
+	AX_SELECT_PAGE(PAGE2, ax_base + PG_PSR);
+	AX_WRITE (rx_ctl ,ax_base + P2_RXCR);
+
+	AX_SELECT_PAGE(PAGE0, ax_base + PG_PSR);
+
+	if (power)
+		ax88796c_set_power_saving (ax_local->ndev, ax_local->ps_level);
+
+	spin_unlock_irqrestore (&ax_local->isr_lock, flags);
+}
+
+/*
+ * ----------------------------------------------------------------------------
+  * Function Name: ax88796c_handle_tx_hdr
+ * Purpose: TX headers processing
+ * ----------------------------------------------------------------------------
+ */
+static void inline
+ax88796c_handle_tx_hdr (struct tx_header *txhdr, u16 pkt_len, u16 seq_num,
+			u8 soffset, u8 eoffset)
+{
+	u16 len_bar = (~pkt_len & TX_HDR_SOP_PKTLENBAR );
+
+	/* Prepare SOP header */
+	txhdr->sop.flags_pktlen = pkt_len;
+	txhdr->sop.seqnum_pktlenbar = ((seq_num << 11) & TX_HDR_SOP_SEQNUM) |
+					(~pkt_len & TX_HDR_SOP_PKTLENBAR);
+
+	cpu_to_be16s (&txhdr->sop.flags_pktlen);
+	cpu_to_be16s (&txhdr->sop.seqnum_pktlenbar);
+
+#ifdef TX_MANUAL_DEQUEUE_CNT
+	if(ax_local->seq_num % TX_MANUAL_DEQUEUE_CNT == 0)
+		txhdr->sop.flags_pktlen |= TX_HDR_SOP_MDEQ;
+#endif
+
+	/* Prepare Segment header */
+	txhdr->seg.flags_seqnum_seglen = TX_HDR_SEG_FS |
+					TX_HDR_SEG_LS | pkt_len ;
+	txhdr->seg.eo_so_seglenbar = ((u16)eoffset << TX_HDR_SEG_EOFBITS) |
+					((u16)soffset << TX_HDR_SEG_SOFBITS) |
+					len_bar;
+
+	cpu_to_be16s (&txhdr->seg.flags_seqnum_seglen);
+	cpu_to_be16s (&txhdr->seg.eo_so_seglenbar);
+}
+
+/*
+ * ----------------------------------------------------------------------------
+ * Function Name: ax88796c_process_tx_eop
+ * Purpose: TX EOP header handling
+ * ----------------------------------------------------------------------------
+ */
+static void inline
+ax88796c_handle_tx_eop(struct tx_eop_header *tx_eop, u16 pkt_len, u16 seq_num)
+{
+	/* Prepare EOP header */
+	tx_eop->seqnum_pktlen = ((seq_num << 11) & TX_HDR_EOP_SEQNUM) | pkt_len;
+
+	tx_eop->seqnumbar_pktlenbar = ((~seq_num << 11) & TX_HDR_EOP_SEQNUMBAR)
+					| (~pkt_len & TX_HDR_EOP_PKTLENBAR);
+
+	cpu_to_be16s (&tx_eop->seqnum_pktlen);
+	cpu_to_be16s (&tx_eop->seqnumbar_pktlenbar);
+}
+
+/*
+ * ----------------------------------------------------------------------------
+ * Function Name: ax88796c_check_free_pages
+ * Purpose: Check free pages of TX buffer
+ * ----------------------------------------------------------------------------
+ */
+static int
+ax88796c_check_free_pages (struct ax88796c_device *ax_local, u8 need_pages)
+{
+	void __iomem *ax_base = ax_local->membase;
+	u8 free_pages;
+	u16 tmp;
+
+	free_pages = AX_READ (ax_base + P0_TFBFCR) & TX_FREEBUF_MASK;
+	if (free_pages < need_pages)
+	{
+		/* schedule free page interrupt */
+		tmp = AX_READ (ax_base + P0_TFBFCR) & TFBFCR_SCHE_FREE_PAGE;
+		AX_WRITE (tmp | TFBFCR_TX_PAGE_SET |
+				TFBFCR_SET_FREE_PAGE(need_pages),
+				ax_base + P0_TFBFCR);
+		return -ENOMEM;
+	}
+
+	return 0;
+}
+
+/*
+ * ----------------------------------------------------------------------------
+ * Function Name: ax88796c_xmit
+ * Purpose: Packet transmission handling
+ * ----------------------------------------------------------------------------
+ */
+static int ax88796c_xmit(struct sk_buff *skb, struct net_device *ndev)
+{
+	struct ax88796c_device *ax_local = netdev_priv (ndev);
+	struct skb_data *entry = (struct skb_data *) skb->cb;
+	unsigned long flags;
+	u8 offset;
+
+	entry->pages = ((skb->len + sizeof (struct tx_header) - 1) >>
+						AX88796C_PAGE_SHIFT ) + 1;
+	offset = (unsigned long)skb->data % 4;
+	entry->dma_len = ((skb->len + offset + 3) & DWORD_ALIGNMENT);
+	entry->offset = offset;
+	ax88796c_handle_tx_hdr (&entry->txhdr, skb->len,
+				ax_local->seq_num, offset,
+				ax_local->burst_len);
+
+	ax88796c_handle_tx_eop(&entry->tx_eop,
+			       skb->len, ax_local->seq_num);
+
+	/*Increase Sequence Number*/
+	ax_local->seq_num = (ax_local->seq_num + 1) & 0x1F;
+
+	if (netif_msg_pktdata (ax_local))
+	{
+		printk ("\n%s: TX packet, len %d\n",
+					__FUNCTION__, skb->len);
+		ax88796c_dump_tx_pkt (skb);
+	}
+
+	spin_lock_irqsave (&ax_local->tx_busy_q.lock, flags);
+
+	if (skb_queue_empty (&ax_local->tx_busy_q) &&
+	    skb_queue_empty (&ax_local->tx_q) &&
+	    (ax88796c_check_free_pages (ax_local, entry->pages) == 0)) {
+		ax_local->low_level_output(ndev, skb, entry);
+	} else {
+		skb_queue_tail(&ax_local->tx_q, skb);
+		if (skb_queue_len (&ax_local->tx_q) > TX_QUEUE_HIGH_WATER) {
+			if (netif_msg_tx_queued (ax_local))
+				printk ("%s: Too much TX packets in queue %d\n"
+					, __FUNCTION__
+					, skb_queue_len (&ax_local->tx_q));
+			netif_stop_queue (ndev);
+		}
+	}
+
+	spin_unlock_irqrestore (&ax_local->tx_busy_q.lock, flags);
+
+	return NET_XMIT_SUCCESS;
+}
+
+#if (TX_MANUAL_DEQUEUE)
+/*
+ * ----------------------------------------------------------------------------
+ * Function Name: ax88796c_handle_tx_manaul_dequeue
+ * Purpose: Tx manual dequeue handleing
+ * ----------------------------------------------------------------------------
+ */
+static void
+ax88796c_handle_tx_manaul_dequeue (struct ax88796c_device *ax_local)
+{
+	void __iomem *ax_base = ax_local->membase;
+	AX_WRITE (TFBFCR_MANU_ENTX | AX_READ (ax_base + P0_TFBFCR),
+		  ax_base + P0_TFBFCR);
+}
+#endif /* TX_MANUAL_DEQUEUE */
+
+/*
+ * ----------------------------------------------------------------------------
+ * Function Name: ax88796c_tx_pio_xmit
+ * Purpose: Packet transmitted to AX88796C by PIO mode
+ * ----------------------------------------------------------------------------
+ */
+static void  inline
+ax88796c_tx_pio_xmit (struct ax88796c_device *ax_local,
+		      const unsigned char *buf, int byte_count)
+{
+	void __iomem *ax_base = ax_local->membase;
+	unsigned int i, count;
+
+	count = ((byte_count + 3) & DWORD_ALIGNMENT);
+	for (i = 0; i < count; i += 2) {
+
+		AX_WRITE (*((u16 *)(buf + i)), ax_base + DATA_PORT_ADDR);
+		/*if(*((u16 *)(buf + i)) == 0x6363)
+		{
+		    printk(" ax_write = %x\n", *((u16 *)(buf + i)));
+		}*/
+	}
+
+}
+
+
+/*
+ * ----------------------------------------------------------------------------
+ * Function Name: ax88796c_tx_pio_start
+ * Purpose: Packet transmission handling by using PIO
+ * ----------------------------------------------------------------------------
+ */
+static int
+ax88796c_tx_pio_start (struct net_device *ndev,
+		struct sk_buff *skb, struct skb_data *entry)
+{
+	struct ax88796c_device *ax_local = netdev_priv (ndev);
+	void __iomem *ax_base = ax_local->membase;
+
+	/* Start tx transmission */
+	AX_WRITE (TSNR_TXB_START | TSNR_PKT_CNT(1), ax_base + P0_TSNR);
+
+
+	ax88796c_tx_pio_xmit (ax_local, (u8 *)&entry->txhdr,
+				sizeof(entry->txhdr));
+	ax88796c_tx_pio_xmit (ax_local, (skb->data - entry->offset),
+				entry->dma_len);
+	ax88796c_tx_pio_xmit (ax_local, (u8 *)&entry->tx_eop,
+				sizeof(entry->tx_eop));
+	/* If tx error interrupt is asserted */
+	if ((ISR_TXERR & AX_READ (ax_base + P0_ISR)) != 0)
+	{
+		ax_local->stat.tx_dropped++;
+		AX_WRITE ((TXNR_TXB_REINIT | AX_READ (ax_base+P0_TSNR)),
+				ax_base+P0_TSNR);
+		ax_local->seq_num = 0;
+	} else {
+		ax_local->stat.tx_bytes += entry->len;
+		ax_local->stat.tx_packets++;
+	}
+
+	dev_kfree_skb_any (skb);
+
+	return NET_XMIT_SUCCESS;
+}
+
+#if (TX_DMA_MODE)
+/*
+ * ----------------------------------------------------------------------------
+ * Function Name: ax88796c_tx_dma_start
+ * Purpose: Packet transmission handling by using DMA
+ * ----------------------------------------------------------------------------
+ */
+static int
+ax88796c_tx_dma_start (struct net_device *ndev,
+			struct sk_buff *skb, struct skb_data *entry)
+{
+	struct ax88796c_device *ax_local = netdev_priv (ndev);
+	void __iomem *ax_base = ax_local->membase;
+
+	__skb_queue_tail(&ax_local->tx_busy_q, skb);
+
+	entry->ndev = ndev;
+	entry->phy_addr = dma_map_single (NULL, (skb->data - entry->offset),
+						entry->dma_len, DMA_TO_DEVICE);
+
+	/* Start tx DMA */
+	AX_WRITE ((TSNR_TXB_START | TSNR_PKT_CNT(1)), ax_base + P0_TSNR);
+
+	ax88796c_tx_pio_xmit (ax_local, (u8 *)&entry->txhdr,
+				sizeof(entry->txhdr));
+
+	dma_start (entry->phy_addr, entry->dma_len / 2, 1);
+
+	return NET_XMIT_SUCCESS;
+}
+
+/*
+ * ----------------------------------------------------------------------------
+ * Function Name: ax88796c_tx_dma_complete
+ * Purpose: Tx DMA completion handling
+ * ----------------------------------------------------------------------------
+ */
+static void ax88796c_tx_dma_complete(void *priv)
+{
+	struct net_device *ndev = (struct net_device *)priv;
+	struct ax88796c_device *ax_local = netdev_priv (ndev);
+	void __iomem *ax_base = ax_local->membase;
+	struct sk_buff *skb;
+	struct skb_data *entry;
+	unsigned long flags;
+
+	spin_lock_irqsave (&ax_local->tx_busy_q.lock, flags);
+
+	skb = __skb_dequeue (&ax_local->tx_busy_q);
+	if (!skb) {
+		/* Should not happened */
+		if (netif_msg_tx_err (ax_local))
+			printk ("%s: No skb in tx_busy_q\n", __FUNCTION__);
+		spin_unlock_irqrestore (&ax_local->tx_busy_q.lock, flags);
+		return;
+	}
+	entry = (struct skb_data *) skb->cb;
+
+	/* PIO write eop hdr */
+	ax88796c_tx_pio_xmit (ax_local, (u8 *)&entry->tx_eop,
+				sizeof(entry->tx_eop));
+
+	/* If tx bridge is idle */
+	if (((AX_READ ( ax_base + P0_TSNR ) & TXNR_TXB_IDLE) == 0) ||
+	    ((ISR_TXERR & AX_READ (ax_base + P0_ISR) ) != 0)) {
+
+		AX_WRITE (ISR_TXERR, ax_base + P0_ISR);
+
+		ax_local->stat.tx_dropped++;
+
+		if (netif_msg_tx_err (ax_local))
+			printk ("%s: TX FIFO error, "
+				"re-initialize the TX bridge\n",
+				__FUNCTION__);
+
+		/* Reinitial tx bridge */
+		AX_WRITE (TXNR_TXB_REINIT | AX_READ (ax_base+P0_TSNR),
+				ax_base+P0_TSNR);
+		ax_local->seq_num = 0;
+	} else {
+		ax_local->stat.tx_bytes += entry->len;
+		ax_local->stat.tx_packets++;
+	}
+
+	/* Unmap DMA address */
+	dma_unmap_single (NULL, entry->phy_addr,
+				entry->dma_len, DMA_TO_DEVICE);
+	dev_kfree_skb_any (skb);
+
+	/* If there is any pending packet */
+	if (skb_queue_len (&ax_local->tx_q)) {
+		struct skb_data *entry;
+		skb = skb_peek(&ax_local->tx_q);
+
+		entry = (struct skb_data *) skb->cb;
+		if (ax88796c_check_free_pages (ax_local, entry->pages) == 0) {
+			skb_unlink(skb, &ax_local->tx_q);
+			ax_local->low_level_output(ndev, skb, entry);
+		}
+	}
+
+	if (netif_queue_stopped (ndev) &&
+	    skb_queue_len (&ax_local->tx_q) < TX_QUEUE_LOW_WATER) {
+		netif_wake_queue (ndev);
+	}
+
+	spin_unlock_irqrestore (&ax_local->tx_busy_q.lock, flags);
+
+	return;
+}
+#endif /* #if (TX_DMA_MODE) */
+
+/*
+ * ----------------------------------------------------------------------------
+ * Function Name: ax_skb_return
+ * Purpose: Send pkt to upper layer
+ * ----------------------------------------------------------------------------
+ */
+static void inline
+ax88796c_skb_return (struct ax88796c_device *ax_local,
+		     struct sk_buff *skb, struct rx_header *rxhdr)
+{
+	int	status;
+
+	do {
+		if (!(ax_local->checksum & AX_RX_CHECKSUM)) {
+			break;
+		}
+
+		/* checksum error bit is set */
+		if ((rxhdr->flags & RX_HDR3_L3_ERR)
+			|| (rxhdr->flags & RX_HDR3_L4_ERR)) {
+			break;
+		}
+
+		if ((RX_HDR3_L3_PKT_TYPE(rxhdr->flags))
+			|| (RX_HDR3_L4_PKT_TYPE(rxhdr->flags))) {
+			skb->ip_summed = CHECKSUM_UNNECESSARY;
+		}
+	} while (0);
+
+	skb->dev = ax_local->ndev;
+	ax_local->stat.rx_packets++;
+	ax_local->stat.rx_bytes += skb->len;
+
+	skb->truesize = skb->len + sizeof(struct sk_buff);
+	skb->protocol = eth_type_trans (skb, ax_local->ndev);
+
+	status = netif_rx (skb);
+	if (status != NET_RX_SUCCESS && netif_msg_rx_status (ax_local))
+		printk ("netif_rx status %d\n", status);
+}
+
+/*
+ * ----------------------------------------------------------------------------
+ * Function Name: ax_rx_fixup
+ * Purpose: Handle the received pkt buffer and send to kernel
+ * ----------------------------------------------------------------------------
+ */
+static void
+ax88696c_rx_fixup (struct ax88796c_device *ax_local,
+		   struct sk_buff *rx_skb)
+{
+	u16 len;
+	struct rx_header *rxhdr;
+
+	/*
+	 * Process first 6 bytes data as RX header
+	 * The rx_skb->data point to the RX header
+	 */
+	rxhdr = (struct rx_header *) rx_skb->data;
+
+	if (netif_msg_pktdata (ax_local)) {
+		int len = be16_to_cpu (rxhdr->flags_len) & RX_HDR1_PKT_LEN;
+		printk ("\n%s: Dump RX data, total len %d, packet len %d",
+			__FUNCTION__, rx_skb->len, len);
+		ax88796c_dump_rx_pkt (rx_skb);
+	}
+
+	/* Swap the RX header to the right order */
+	be16_to_cpus (&rxhdr->flags_len);
+	be16_to_cpus (&rxhdr->seq_lenbar);
+	be16_to_cpus (&rxhdr->flags);
+
+	/* Validate the RX header of this packet */
+	if ((((short)rxhdr->flags_len) & RX_HDR1_PKT_LEN) !=
+	    (~((short)rxhdr->seq_lenbar) & TX_HDR_SOP_PKTLEN)) {
+		ax_local->stat.rx_frame_errors++;
+		dev_kfree_skb_any (rx_skb);
+		printk("===>%s:%d: Something error!!!\n", __func__, __LINE__);
+		return;
+	}
+
+	/* Get packet length */
+	len = rxhdr->flags_len & RX_HDR1_PKT_LEN;
+
+	/* The packet lies after RX header */
+	skb_pull (rx_skb, sizeof (*rxhdr));
+	__pskb_trim (rx_skb, len);
+
+	return ax88796c_skb_return (ax_local, rx_skb, rxhdr);
+
+} /* End of ax_rx_fixup () */
+
+/*
+ * ----------------------------------------------------------------------------
+ * Function Name: ax88796c_rx_pio
+ * Purpose: Packet reception handling by using PIO
+ * ----------------------------------------------------------------------------
+ */
+static int ax88796c_rx_pio (struct net_device *ndev)
+{
+	struct ax88796c_device *ax_local = netdev_priv (ndev);
+	void __iomem *ax_base = ax_local->membase;
+	struct sk_buff *skb;
+	u8 pkt_cnt;
+	u16 w_count;
+	u16 header;
+	u16 len;
+	int i;
+	u8 loop_cnt = 20;
+
+	while (--loop_cnt) {
+
+		/* Read out the rx pkt counts and word counts */
+		AX_WRITE (RTWCR_RX_LATCH | AX_READ (ax_base + P0_RTWCR),
+				ax_base + P0_RTWCR);
+		pkt_cnt = AX_READ (ax_base + P0_RXBCR2) & RXBCR2_PKT_MASK;
+		if (!pkt_cnt)
+			break;
+
+		/* Read out the rx header1 */
+		header = AX_READ (ax_base + P0_RCPHR);
+		len = header & RX_HDR1_PKT_LEN;
+
+		if ((header & RX_HDR1_MII_ERR) ||
+			(header & RX_HDR1_CRC_ERR)) {
+			ax_local->stat.rx_crc_errors++;
+
+			/* skip this packet */
+			AX_WRITE (RXBCR1_RXB_DISCARD, ax_base + P0_RXBCR1);
+			continue;
+		}
+
+		w_count = ((len + sizeof (struct rx_header) + 3)
+						& DWORD_ALIGNMENT) >> 1;
+
+		skb = dev_alloc_skb (w_count * 2);
+		if (!skb) {
+			if (netif_msg_rx_err (ax_local))
+				printk ("%s: Couldn't allocate a sk_buff"
+					" of size %d\n",
+                                        ndev->name, w_count * 2);
+			/* skip this packet */
+			AX_WRITE (RXBCR1_RXB_DISCARD, ax_base + P0_RXBCR1);
+			continue;
+		}
+		skb_put (skb, w_count * 2);
+
+		/* Start rx PIO transmission */
+		AX_WRITE (RXBCR1_RXB_START | w_count, ax_base + P0_RXBCR1);
+		while(!(AX_READ(ax_base + P0_RXBCR2) & RXBCR2_RXB_READY));
+
+		//msleep(10);
+
+		//if (len == 155)
+			//printk("===>pkt_cnt = %d, len = %d w_count = %d skb->len = %d\n", pkt_cnt, len, w_count, skb->len);
+			//printk("===>pkt_cnt = %d, len = %d w_count = %d skb->len = %d\n", pkt_cnt, len, w_count, skb->len);
+		//printk("ax_base = 0x%08x\n", ax_base);
+		for (i = 0; i < skb->len; i += 2) {
+			*((u16 *)(skb->data + i)) = AX_READ (ax_base + DATA_PORT_ADDR);
+			//AX_READ (ax_base);
+			/*	if(*((u16 *)(skb->data + i)) == 0x6363)
+				printk(" skb->data = %x\n", *((u16 *)(skb->data + i)));*/
+		}
+
+		ax88696c_rx_fixup (ax_local, skb);
+	}
+
+	return 0;
+}
+
+#if (RX_DMA_MODE)
+/*
+ * ----------------------------------------------------------------------------
+ * Function Name: ax88796c_rx
+ * Purpose: Packet reception handling by using DMA
+ * ----------------------------------------------------------------------------
+ */
+static int ax88796c_rx_dma (struct net_device *ndev)
+{
+ 	struct ax88796c_device *ax_local = netdev_priv (ndev);
+	void __iomem *ax_base = ax_local->membase;
+	struct sk_buff *skb;
+	u16 w_count, header, len;
+	struct skb_data *entry;
+	u16 pkt_cnt;
+
+	AX_WRITE (RTWCR_RX_LATCH | AX_READ (ax_base + P0_RTWCR),
+				ax_base + P0_RTWCR);
+	pkt_cnt = AX_READ (ax_base + P0_RXBCR2) & RXBCR2_PKT_MASK;
+	if (!pkt_cnt) {
+		return 0;
+	}
+
+	/* Read out the rx header1 */
+	header = AX_READ (ax_base + P0_RCPHR);
+	len = header & RX_HDR1_PKT_LEN;
+
+	if ((header & RX_HDR1_MII_ERR) ||
+		(header & RX_HDR1_CRC_ERR)) {
+		ax_local->stat.rx_crc_errors++;
+
+		/* skip this packet */
+		AX_WRITE (RXBCR1_RXB_DISCARD, ax_base + P0_RXBCR1);
+		return 0;
+	}
+
+	w_count = ((len + sizeof (struct rx_header) + 3)
+					& DWORD_ALIGNMENT) >> 1;
+
+	skb = dev_alloc_skb (w_count * 2);
+	if (!skb) {
+		if (netif_msg_rx_err (ax_local))
+			printk ("%s: Couldn't allocate a sk_buff of size %d\n",
+					ndev->name, w_count * 2);
+		/* skip this packet */
+		AX_WRITE (RXBCR1_RXB_DISCARD, ax_base + P0_RXBCR1);
+		return 0;
+	}
+
+	skb_put (skb, w_count * 2);
+
+	/* Enable RX bridge */
+	AX_WRITE (RXBCR1_RXB_START | w_count, ax_base + P0_RXBCR1);
+	while(!(AX_READ(ax_base + P0_RXBCR2) & RXBCR2_RXB_READY));
+
+	entry = (struct skb_data *) skb->cb;
+	entry->phy_addr = dma_map_single (NULL, skb->data, skb->len,
+				DMA_FROM_DEVICE);
+	__skb_queue_tail (&ax_local->rx_busy_q, skb);
+
+	ax_local->rx_dmaing = 1;
+
+	/* Start rx DMA transmission */
+	dma_start (entry->phy_addr, w_count, 0);
+
+	return 1;
+}
+#endif
+
+#if (RX_DMA_MODE)
+/*
+ * ----------------------------------------------------------------------------
+ * Function Name: ax88796c_rx_dma_complete
+ * Purpose: Rx DMA completion handling
+ * ----------------------------------------------------------------------------
+ */
+static void ax88796c_rx_dma_complete(void *dev_temp)
+{
+	struct net_device *ndev = (struct net_device* ) dev_temp;
+	struct ax88796c_device *ax_local = netdev_priv (ndev);
+	void __iomem *ax_base = ax_local->membase;
+	struct sk_buff *skb;
+	struct skb_data *entry;
+	unsigned long flags;
+
+	spin_lock_irqsave (&ax_local->isr_lock, flags);
+	AX_WRITE (IMR_MASKALL, ax_base + P0_IMR);
+
+	skb = __skb_dequeue (&ax_local->rx_busy_q);
+	if (!skb) {
+		if (netif_msg_rx_err (ax_local)) {
+			/* Should not happened  */
+			printk ("%s: No RX SKB in queue\n", __FUNCTION__);
+		}
+	}
+	entry = (struct skb_data *) skb->cb;
+
+	/* Unmap DMA address */
+	dma_unmap_single(NULL, entry->phy_addr, skb->len, DMA_FROM_DEVICE);
+
+	/* Check if rx bridge is idle */
+	if ((AX_READ (ax_base + P0_RXBCR2) & RXBCR2_RXB_IDLE) == 0) {
+		if (netif_msg_rx_err (ax_local) )
+			printk("%s: Rx Bridge is not idle\n", ndev->name);
+		AX_WRITE (RXBCR2_RXB_REINIT, ax_base + P0_RXBCR2);
+		dev_kfree_skb_any (skb);
+	} else {
+		ax88696c_rx_fixup (ax_local, skb);
+	}
+
+	ax_local->rx_dmaing = 0;
+
+	/* If the rx pkt in RX RAM */
+	ax88796c_rx_dma (ndev);
+
+	/* Enable RX interrupt  */
+	if (ax_local->rx_dmaing) {
+		AX_WRITE((IMR_DEFAULT | IMR_RXPKT), ax_base + P0_IMR);
+	} else {
+		AX_WRITE (ISR_RXPKT, ax_base + P0_ISR);
+		AX_WRITE(IMR_DEFAULT, ax_base + P0_IMR);
+	}
+
+	spin_unlock_irqrestore (&ax_local->isr_lock, flags);
+}
+#endif
+
+/*
+ * ----------------------------------------------------------------------------
+ * Function Name: ax88796c_watchdog
+ * Purpose: Check media link status
+ * ----------------------------------------------------------------------------
+ */
+static void ax88796c_watchdog (unsigned long arg)
+{
+	struct net_device *ndev = (struct net_device *)(arg);
+    	struct ax88796c_device *ax_local = netdev_priv (ndev);
+	void __iomem *ax_base = ax_local->membase;
+	unsigned long time_to_chk = AX88796C_WATCHDOG_PERIOD;
+	unsigned long flags;
+	u16 phy_status;
+
+	spin_lock_irqsave (&ax_local->isr_lock, flags);
+
+	/*
+	 * Do a simple verification if AX88796C is in power saving mode.
+	 * If AX88796C is in power saving mode, then we cannot
+	 * switch to another page.
+	 */
+	if (ax_local->ps_level) {
+		AX_SELECT_PAGE (PAGE1, ax_base + PG_PSR);
+		if (AX_READ (ax_base + P0_BOR) == 0x1234) {
+			if (netif_msg_timer (ax_local))
+				printk ("%s: In power saving mode\n",
+					ax_local->ndev->name);
+			ax_local->w_state = chk_cable;
+			goto out;
+		}
+
+		/*
+		 * Be aware of AX88796C entering to power saving mode
+		 * during watchdog operations.
+		 */
+		AX_SELECT_PAGE (PAGE0, ax_base + PG_PSR);
+		ax88796c_set_power_saving (ndev, AX_PS_D0);
+	}
+
+	phy_status = AX_READ (ax_base + P0_PSCR);
+	if (phy_status & PSCR_PHYLINK) {
+
+		ax_local->w_state = ax_nop;
+		time_to_chk = 0;
+
+	} else if (!(phy_status & PSCR_PHYCOFF)) {
+	/* The ethernet cable has been plugged */
+
+		if (ax_local->w_state == chk_cable) {
+			if (netif_msg_timer (ax_local))
+				printk ("%s: Cable connected\n",
+					ax_local->ndev->name);
+			ax_local->w_state = chk_link;
+			ax_local->w_ticks = 0;
+		} else {
+			if (netif_msg_timer (ax_local))
+				printk ("%s: Check media status\n",
+					ax_local->ndev->name);
+			if (++ax_local->w_ticks == AX88796C_WATCHDOG_RESTART) {
+				if (netif_msg_timer (ax_local))
+					printk ("%s: Restart autoneg\n",
+						ax_local->ndev->name);
+				ax88796c_mdio_write_phy (ax_local->ndev,
+					ax_local->mii.phy_id, MII_BMCR,
+					BMCR_SPEED100 | BMCR_ANENABLE | BMCR_ANRESTART);
+				ax_local->w_ticks = 0;
+			}
+		}
+	} else {
+		if (netif_msg_timer (ax_local))
+			printk ("%s: Check cable status\n",
+				ax_local->ndev->name);
+		ax_local->w_state = chk_cable;
+	}
+
+	if (ax_local->ps_level)
+		ax88796c_set_power_saving (ndev, ax_local->ps_level);
+out:
+	spin_unlock_irqrestore (&ax_local->isr_lock, flags);
+
+	if (time_to_chk)
+		mod_timer (&ax_local->watchdog, jiffies + time_to_chk);
+}
+
+/*
+ * ----------------------------------------------------------------------------
+ * Function Name: ax88796c_check_media
+ * Purpose: Process media link status
+ * ----------------------------------------------------------------------------
+ */
+static void ax88796c_check_media (struct ax88796c_device *ax_local)
+{
+	u16 bmsr, bmcr;
+
+	if (netif_msg_hw (ax_local))
+		ax88796c_dump_phy_regs (ax_local);
+
+	bmsr = ax88796c_mdio_read_phy (ax_local->ndev,
+			ax_local->mii.phy_id, MII_BMSR);
+
+	if (!(bmsr & BMSR_LSTATUS) && netif_carrier_ok (ax_local->ndev)) {
+		struct sk_buff *skb;
+		unsigned long flags;
+
+		netif_carrier_off (ax_local->ndev);
+		if (netif_msg_link (ax_local))
+			printk(KERN_INFO "%s: link down\n",
+					ax_local->ndev->name);
+
+		spin_lock_irqsave (&ax_local->tx_busy_q.lock, flags);
+
+		/* If media link down, free all pending resource */
+		while (!skb_queue_empty (&ax_local->tx_q)) {
+			skb = skb_dequeue (&ax_local->tx_q);
+			dev_kfree_skb_any (skb);
+		}
+		spin_unlock_irqrestore (&ax_local->tx_busy_q.lock, flags);
+
+		ax_local->w_state = chk_cable;
+		mod_timer (&ax_local->watchdog,
+				jiffies + AX88796C_WATCHDOG_PERIOD);
+
+	} else if((bmsr & BMSR_LSTATUS) && !netif_carrier_ok (ax_local->ndev)) {
+		bmcr = ax88796c_mdio_read_phy (ax_local->ndev,
+				ax_local->mii.phy_id, MII_BMCR);
+		if (netif_msg_link (ax_local))
+			printk(KERN_INFO "%s: link up, %sMbps, %s-duplex\n",
+				ax_local->ndev->name,
+				(bmcr & BMCR_SPEED100) ? "100" : "10",
+				(bmcr & BMCR_FULLDPLX) ? "full" : "half");
+
+		netif_carrier_on (ax_local->ndev);
+	}
+
+	return;
+}
+
+/* ----------------------------------------------------------------------------
+ * Function Name: ax88796c_interrupt
+ * Purpose: Interrupt handling
+ * ----------------------------------------------------------------------------
+ */
+static irqreturn_t
+#if 1
+ax88796c_interrupt (int irq, void *dev_id)
+#else
+ax88796c_interrupt (int irq, void *dev_id, struct pt_regs * regs)
+#endif
+{
+	struct net_device *ndev = dev_id;
+    	struct ax88796c_device *ax_local = netdev_priv (ndev);
+	void __iomem *ax_base = ax_local->membase;
+	u16 interrupts;
+	unsigned long flags;
+
+	spin_lock_irqsave (&ax_local->isr_lock, flags);
+
+	/* Mask all interrupts */
+	AX_WRITE (IMR_MASKALL, ax_base + P0_IMR);
+
+	/* Check and handle each interrupt event */
+	interrupts = AX_READ (ax_base + P0_ISR);
+
+	if (netif_msg_intr (ax_local)) {
+		printk ("%s: Interrupt status 0x%x\n",
+			__FUNCTION__ , interrupts);
+	}
+
+	if (interrupts) {
+
+		/* RX interrupt */
+		if (interrupts & ISR_RXPKT) {
+
+			if (skb_queue_empty (&ax_local->rx_busy_q))
+				ax_local->low_level_input (ndev);
+		}
+
+		/* Tx interrupt */
+		if (interrupts & (ISR_TXPAGES)) {
+
+			spin_lock (&ax_local->tx_busy_q.lock);
+
+			/* If there is any pending packet */
+			if (!skb_queue_empty (&ax_local->tx_q) &&
+			    skb_queue_empty (&ax_local->tx_busy_q)) {
+				struct sk_buff *skb = skb_peek(&ax_local->tx_q);
+				struct skb_data *entry =
+						(struct skb_data *) skb->cb;
+
+				if (ax88796c_check_free_pages (ax_local,
+				    entry->pages) == 0) {
+					__skb_unlink (skb, &ax_local->tx_q);
+					ax_local->low_level_output (ndev,
+						skb, entry);
+				}
+			}
+
+			spin_unlock (&ax_local->tx_busy_q.lock);
+		}
+
+		if (interrupts & ISR_LINK) {
+			ax88796c_check_media (ax_local);
+		}
+
+		/* Acknowledge all interrupts */
+		AX_WRITE (interrupts, ax_base + P0_ISR);
+	}
+
+	/* If rx interrupt is asserted, do not unmake rx interrupt */
+	if (ax_local->rx_dmaing) {
+		AX_WRITE((IMR_DEFAULT | IMR_RXPKT), ax_base + P0_IMR);
+	} else {
+		AX_WRITE(IMR_DEFAULT, ax_base + P0_IMR);
+	}
+
+	spin_unlock_irqrestore (&ax_local->isr_lock, flags);
+
+	return IRQ_HANDLED;
+}
+
+/*
+ * ----------------------------------------------------------------------------
+ * Function Name: ax88796c_get_stats
+ * Purpose: Return statistics to the upper layer
+ * ----------------------------------------------------------------------------
+ */
+static struct net_device_stats *ax88796c_get_stats (struct net_device *ndev)
+{
+	struct ax88796c_device *ax_local = netdev_priv (ndev);
+	return &ax_local->stat;
+}
+
+/*
+ * ----------------------------------------------------------------------------
+ * Function Name: ax88796c_phy_init
+ * Purpose: Initialize phy.
+ * ----------------------------------------------------------------------------
+ */
+#ifndef ADVERTISE_PAUSE_CAP
+#  define ADVERTISE_PAUSE_CAP	0x400
+#endif
+static void ax88796c_phy_init (struct ax88796c_device *ax_local)
+{
+	u16 advertise = ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
+	unsigned long flags;
+	void __iomem *ax_base = ax_local->membase;
+
+	spin_lock_irqsave (&ax_local->isr_lock, flags);
+
+	AX_SELECT_PAGE (PAGE2, ax_base + PG_PSR);
+
+	/* Setup LED mode */
+	AX_WRITE ((LCR_LED0_EN | LCR_LED0_DUPLEX | LCR_LED1_EN |
+		   LCR_LED1_100MODE), ax_base + P2_LCR0);
+	AX_WRITE ((AX_READ (ax_base + P2_LCR1) & LCR_LED2_MASK) |
+		  LCR_LED2_EN | LCR_LED2_LINK, ax_base + P2_LCR1);
+
+	AX_WRITE (POOLCR_PHYID(ax_local->mii.phy_id) | POOLCR_POLL_EN |
+				POOLCR_POLL_FLOWCTRL | POOLCR_POLL_BMCR,
+				ax_base + P2_POOLCR);
+
+	AX_SELECT_PAGE(PAGE0, ax_base + PG_PSR);
+	spin_unlock_irqrestore (&ax_local->isr_lock, flags);
+
+	ax88796c_mdio_write (ax_local->ndev,
+			ax_local->mii.phy_id, MII_ADVERTISE, advertise);
+
+
+	ax88796c_mdio_write (ax_local->ndev, ax_local->mii.phy_id, MII_BMCR,
+			     BMCR_SPEED100 | BMCR_ANENABLE | BMCR_ANRESTART);
+
+
+	netif_carrier_off (ax_local->ndev);
+
+	if (netif_msg_hw (ax_local))
+		ax88796c_dump_phy_regs (ax_local);
+}
+
+/*
+ * ----------------------------------------------------------------------------
+ * Function Name: ax88796c_set_mac_addr
+ * Purpose: Set up AX88796C MAC address
+ * ----------------------------------------------------------------------------
+ */
+static void ax88796c_set_mac_addr (struct net_device *ndev)
+{
+	struct ax88796c_device *ax_local = netdev_priv (ndev);
+	unsigned long flags;
+	void __iomem *ax_base = ax_local->membase;
+
+	spin_lock_irqsave (&ax_local->isr_lock, flags);
+	/* Write deault MAC address into AX88796C */
+	AX_SELECT_PAGE(PAGE3, ax_local->membase + PG_PSR);
+
+	AX_WRITE(( (u16)(ndev->dev_addr[4] << MACASR_HIGH_BITS) |
+			(u16)ndev->dev_addr[5] ),
+			ax_local->membase + P3_MACASR0 );
+	AX_WRITE(( (u16)(ndev->dev_addr[2] << MACASR_HIGH_BITS) |
+			(u16)ndev->dev_addr[3] ),
+			ax_local->membase + P3_MACASR1 );
+	AX_WRITE(( (u16)(ndev->dev_addr[0] << MACASR_HIGH_BITS) |
+			(u16)ndev->dev_addr[1] ),
+			ax_local->membase + P3_MACASR2 );
+
+	AX_SELECT_PAGE(PAGE0, ax_base + PG_PSR);
+	spin_unlock_irqrestore (&ax_local->isr_lock, flags);
+}
+
+/*
+ * ----------------------------------------------------------------------------
+ * Function Name: ax88796c_set_mac_address
+ * Purpose: Reset the whol chip
+ * ----------------------------------------------------------------------------
+ */
+static int ax88796c_set_mac_address (struct net_device *ndev, void *p)
+{
+	struct ax88796c_device *ax_local = netdev_priv (ndev);
+	struct sockaddr *addr = p;
+	u8 power;
+
+	if (!is_valid_ether_addr(addr->sa_data))
+		return -EADDRNOTAVAIL;
+
+	power = ax88796c_check_power_state (ndev);
+
+	memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
+
+	ax88796c_set_mac_addr (ndev);
+
+	if (power)
+		ax88796c_set_power_saving (ndev, ax_local->ps_level);
+
+	return 0;
+}
+
+/*
+ * ----------------------------------------------------------------------------
+ * Function Name: ax88796c_load_mac_addr
+ * Purpose: Read MAC address from AX88796C
+ * ----------------------------------------------------------------------------
+ */
+static int ax88796c_load_mac_addr (struct net_device *ndev)
+{
+	struct ax88796c_device *ax_local = netdev_priv (ndev);
+	int i , j;
+	unsigned long flags;
+	void __iomem *ax_base = ax_local->membase;
+
+	spin_lock_irqsave (&ax_local->isr_lock, flags);
+	/* Read the MAC address from AX88796C */
+	AX_SELECT_PAGE(PAGE3, ax_local->membase + PG_PSR);
+	for(i = 2, j = 0 ; i >= 0 ; i-- , j++ ){
+		u16 temp;
+		temp = AX_READ ( ax_local->membase + P3_MACASR(i));
+		ndev->dev_addr[j*2+1]  = (u8)(temp & MACASR_LOWBYTE_MASK) ;
+		ndev->dev_addr[j*2]  = (u8)(temp >> MACASR_HIGH_BITS);
+	}
+	AX_SELECT_PAGE(PAGE0, ax_base + PG_PSR);
+	spin_unlock_irqrestore (&ax_local->isr_lock, flags);
+
+	/* Support for no EEPROM */
+	if ((ndev->dev_addr[0] & 0x01) ||
+		((ndev->dev_addr[0] == 0) && (ndev->dev_addr[1] == 0) &&
+		 (ndev->dev_addr[2] == 0) && (ndev->dev_addr[3] == 0) &&
+		 (ndev->dev_addr[4] == 0) && (ndev->dev_addr[5] == 0))) {
+
+		ndev->dev_addr[0] = 0x00;
+		ndev->dev_addr[1] = 0x12;
+		ndev->dev_addr[2] = 0x34;
+		ndev->dev_addr[3] = 0x56;
+		ndev->dev_addr[4] = 0x78;
+		ndev->dev_addr[5] = 0x9A;
+	}
+
+	if (netif_msg_probe (ax_local))
+		printk (KERN_INFO "%s: MAC Address "
+			"%2.2x-%2.2x-%2.2x-%2.2x-%2.2x-%2.2x\n",
+			AX88796C_DRV_NAME,
+			ndev->dev_addr[0], ndev->dev_addr[1],
+			ndev->dev_addr[2], ndev->dev_addr[3],
+			ndev->dev_addr[4], ndev->dev_addr[5]);
+	return 0;
+}
+
+/*
+ * ----------------------------------------------------------------------------
+ * Function Name: ax88796c_init
+ * Purpose: Initialize hardware and driver specific data.
+ * ----------------------------------------------------------------------------
+ */
+static int ax88796c_init (struct ax88796c_device *ax_local)
+{
+	u16 temp;
+	void __iomem *ax_base = ax_local->membase;
+//	printk("ax88796c init !\n");
+
+	/* Reset AX88796C */
+	ax88796c_reset (ax_local);
+
+	/*Reload EEPROM*/
+	//ax88796c_reload_eeprom (ax_local);
+
+	/* AX88796C Page1 registers initialization */
+	AX_SELECT_PAGE (PAGE1, ax_base + PG_PSR);
+
+	/* Enable RX packet process */
+	AX_WRITE (RPPER_RXEN, ax_base + P1_RPPER);
+
+	/* Disable stuffing */
+	AX_WRITE (AX_READ (ax_base + P1_RXBSPCR) & ~RXBSPCR_STUF_ENABLE,
+			ax_base + P1_RXBSPCR);
+
+	ax88796c_set_mac_addr (ax_local->ndev);
+
+	ax88796c_set_csums (ax_local->ndev);
+
+	/* AX88796C Page0 registers initialization */
+	AX_SELECT_PAGE (PAGE0, ax_base + PG_PSR);
+	temp = AX_READ (ax_base + P0_BOR);
+
+	if (temp == 0x1234){
+		AX_WRITE ((FER_IPALM | FER_DCRC | FER_BSWAP | FER_RXEN |
+				FER_TXEN | FER_INTHI| FER_IRQ_PULL),
+				ax_base + P0_FER);
+//		printk("LITTLE_ENDIAN\n");
+	} else {
+		AX_WRITE ((FER_IPALM | FER_DCRC | FER_RXEN | FER_TXEN |
+				FER_INTHI | FER_IRQ_PULL),                               //jarvis debug FER_INTLO -> FER_INTHI
+				ax_base + P0_FER);
+//		printk("BIG_ENDIAN\n");
+	}
+
+	ax88796c_set_power_saving (ax_local->ndev, ax_local->ps_level);
+
+	ax88796c_phy_init (ax_local);
+
+	return 0;
+}
+
+/*
+ * ----------------------------------------------------------------------------
+ * Function Name: ax88796c_free_skbuff
+ * Purpose: Free allocated skb buffer
+ * ----------------------------------------------------------------------------
+ */
+static void
+ax88796c_free_skbuff (struct sk_buff_head *q)
+{
+	struct sk_buff *skb;
+
+	/* Release skb_queue */
+	while (q->qlen) {
+		skb = skb_dequeue (q);
+		dev_kfree_skb (skb);
+	}
+}
+
+#if (TX_DMA_MODE) || (RX_DMA_MODE)
+extern int ax88796c_platform_dma_init (unsigned long base_addr,
+				void (*tx_dma_complete)(void *data),
+				void (*rx_dma_complete)(void *data),
+				void *priv);
+#endif
+/*
+ * ----------------------------------------------------------------------------
+ * Function Name: ax88796c_open
+ * Purpose: Device open and initialization
+ * ----------------------------------------------------------------------------
+ */
+static int
+ax88796c_open(struct net_device *ndev)
+{
+	struct ax88796c_device *ax_local = netdev_priv (ndev);
+	void __iomem *ax_base = ax_local->membase;
+	int ret = 0;
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)
+	unsigned long irq_flag = SA_SHIRQ;
+#else
+	unsigned long irq_flag = IRQF_SHARED;
+#endif
+	u8 power = ax88796c_check_power_state (ndev);
+
+	/* Mask interrupt first */
+	AX_WRITE (IMR_MASKALL, ax_base + P0_IMR);
+
+	/* Initialize all the local variables */
+	ax_local->seq_num = 0;
+
+	ax88796c_init (ax_local);
+	/* Request IRQ */
+	ret = request_irq (ndev->irq, &ax88796c_interrupt,
+				irq_flag, ndev->name, ndev);
+	if (ret) {
+		if (netif_msg_ifup (ax_local))
+			printk (KERN_ERR
+				"%s: unable to get IRQ %d (errno=%d)\n",
+				ndev->name, ndev->irq, ret);
+		return ret;
+	}
+#if (TX_DMA_MODE) || (RX_DMA_MODE)
+	ret = ax88796c_platform_dma_init (
+				ndev->base_addr,
+				ax_local->tx_dma_complete,
+				ax_local->rx_dma_complete,
+				ndev);
+	if (ret) {
+		free_irq (ndev->irq, ndev);
+		return ret;
+	}
+#endif
+
+	netif_start_queue(ndev);
+
+	AX_SELECT_PAGE(PAGE0, ax_local->membase + PG_PSR);
+	AX_WRITE (IMR_DEFAULT, ax_base + P0_IMR);
+
+	if (netif_msg_hw (ax_local)) {
+		printk ("Dump AX88796C registers (after initialaztion):\n");
+		ax88796c_dump_regs (ax_local);
+	}
+
+	if (power)
+		ax88796c_set_power_saving (ax_local->ndev, ax_local->ps_level);
+
+	init_timer (&ax_local->watchdog);
+	ax_local->watchdog.function = &ax88796c_watchdog;
+	ax_local->watchdog.expires = jiffies + AX88796C_WATCHDOG_PERIOD;
+	ax_local->watchdog.data = (unsigned long) ndev;
+	ax_local->w_state = chk_cable;
+	ax_local->w_ticks = 0;
+
+	add_timer (&ax_local->watchdog);
+
+	return 0;
+}
+
+/*
+ * ----------------------------------------------------------------------------
+ * Function Name: ax88796c_close
+ * Purpose: Device close
+ * ----------------------------------------------------------------------------
+ */
+static int
+ax88796c_close(struct net_device *ndev)
+{
+	struct ax88796c_device *ax_local = netdev_priv (ndev);
+	unsigned long flags;
+
+	(void) ax88796c_check_power_state (ndev);
+
+	netif_stop_queue (ndev);
+
+	del_timer_sync (&ax_local->watchdog);
+
+	/*Release IRQ*/
+ 	spin_lock_irqsave (&ax_local->isr_lock, flags);
+	free_irq (ndev->irq, ndev);
+	spin_unlock_irqrestore (&ax_local->isr_lock, flags);
+
+
+	ax88796c_free_skbuff (&ax_local->tx_q);
+	ax88796c_free_skbuff (&ax_local->tx_busy_q);
+	ax88796c_free_skbuff (&ax_local->rx_busy_q);
+
+	ax88796c_reset (ax_local);
+
+	ax88796c_set_power_saving (ax_local->ndev, ax_local->ps_level);
+
+	return 0;
+}
+/* Lutts@20101019 */
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
+const struct net_device_ops ax88796c_netdev_ops = {
+	.ndo_open		= ax88796c_open,
+	.ndo_stop		= ax88796c_close,
+	.ndo_start_xmit		= ax88796c_xmit,
+	.ndo_get_stats		= ax88796c_get_stats,
+	.ndo_set_multicast_list = ax88796c_set_multicast,
+	.ndo_do_ioctl		= ax88796c_ioctl,
+	.ndo_validate_addr	= eth_validate_addr,
+	.ndo_set_mac_address 	= ax88796c_set_mac_address,
+};
+#endif
+
+/*
+ * ----------------------------------------------------------------------------
+ * Function Name: ax88796c_probe
+ * Purpose: Device initialization.
+ * ----------------------------------------------------------------------------
+ */
+static int __devinit
+ax88796c_probe (struct ax88796c_device *ax_local)
+{
+	struct net_device *ndev = ax_local->ndev;
+	void __iomem *ax_base;
+	int retval;
+	int i = 0;
+  int i_temp = 0;
+
+	ax_base = ax_local->membase;
+
+
+
+	ax88796c_platform_init (bus_wide);
+
+#if 1
+	__gpio_disable_pull(32 * 1 + 23);
+	__gpio_as_output(32 * 1 + 23);
+	__gpio_set_pin(32 * 1 + 23);
+	msleep(10);
+	for (i = 0; i < 5280; i++)
+		__gpio_clear_pin(32 * 1 + 23);
+	msleep(10);
+	__gpio_set_pin(32 * 1 + 23);
+#endif
+
+	/* Wakeup AX88796C first */
+	AX_WRITE (0xFFFF, ax_base + PG_HOST_WAKEUP+1);
+	msleep (200);
+
+	//printk("PG_PSR = 0x%08x\n", AX_READ(ax_base + PG_PSR));
+	printk ( "PSR = 0X%04x \n",AX_READ (0xb4000000));
+	#if 0
+  AX_SELECT_PAGE(PAGE3,ax_base+PG_PSR);
+  for(i = 0; i < 0xffff; i++)
+  {
+  	AX_WRITE(i, ax_base + 0x02);
+  	i_temp = AX_READ(ax_base + 0x02);
+  	if(i != i_temp)
+  	{
+  		printk("AX_READ = %x != %x \n", i,i_temp);
+
+  	}
+
+  }
+  AX_SELECT_PAGE(PAGE0,ax_base+PG_PSR);
+  #endif
+
+	/* Reset AX88796C */
+	ax88796c_reset (ax_local);
+
+	/*Reload EEPROM*/
+	//ax88796c_reload_eeprom (ax_local);
+
+	if (netif_msg_hw (ax_local)) {
+		printk ("Dump AX88796C registers:\n");
+		ax88796c_dump_regs (ax_local);
+	}
+
+	if (netif_msg_probe (ax_local))
+		printk (version);
+
+	/* Set local arguments */
+	/* Lutts@20101019 */
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
+	ndev->netdev_ops = &ax88796c_netdev_ops;
+#else
+	ndev->hard_start_xmit = ax88796c_xmit;
+//	ndev->hard_start_xmit =ax88796c_tx_pio_start;
+	ndev->get_stats	= ax88796c_get_stats;
+	ndev->set_multicast_list = ax88796c_set_multicast;
+	ndev->open = ax88796c_open;
+	ndev->stop = ax88796c_close;
+	ndev->do_ioctl = ax88796c_ioctl;
+	ndev->set_mac_address 	= ax88796c_set_mac_address,
+#endif
+	ndev->ethtool_ops = &ax88796c_ethtool_ops;
+
+	/* Initialize MII structure */
+	ax_local->mii.dev = ndev;
+	ax_local->mii.mdio_read = ax88796c_mdio_read;
+	ax_local->mii.mdio_write = ax88796c_mdio_write;
+	ax_local->mii.phy_id_mask = PHY_ID_MASK;
+	ax_local->mii.reg_num_mask = REG_NUM_MASK;
+	ax_local->mii.phy_id = PHY_ID;
+
+	ax_local->checksum = AX_RX_CHECKSUM | AX_TX_CHECKSUM;
+
+	/* Hook TX and RX function */
+	ax_local->burst_len = DMA_BURST_LEN_2_WORD;	/* per access 16-bit */
+	ax_local->low_level_output = ax88796c_tx_pio_start;
+	ax_local->low_level_input = ax88796c_rx_pio;
+#if (TX_DMA_MODE)
+	//ax_local->burst_len = DMA_BURST_LEN;		/* per access 32-bit */
+	ax_local->low_level_output = ax88796c_tx_dma_start;
+	ax_local->tx_dma_complete = ax88796c_tx_dma_complete;
+#endif
+#if (RX_DMA_MODE)
+	ax_local->low_level_input = ax88796c_rx_dma;
+	ax_local->rx_dma_complete = ax88796c_rx_dma_complete;
+#endif
+
+	ether_setup (ndev);
+
+	/*Set Hardware check sum*/
+	ndev->features |= NETIF_F_HW_CSUM;
+
+	/* Initialize queue */
+	skb_queue_head_init (&ax_local->tx_q);
+	skb_queue_head_init (&ax_local->tx_busy_q);
+	skb_queue_head_init (&ax_local->rx_busy_q);
+
+	spin_lock_init (&ax_local->isr_lock);
+
+	ax88796c_load_mac_addr (ndev);
+
+	retval = register_netdev(ndev);
+	if (retval == 0) {
+		/* now, print out the card info, in a short format.. */
+		if (netif_msg_probe (ax_local))
+			printk("%s:  at %#lx IRQ %d",
+				ndev->name,
+				ndev->base_addr, ndev->irq);
+	}
+
+	return 0;
+}
+
+
+/*
+ * ----------------------------------------------------------------------------
+ * Function Name: ax88796c_drv_probe
+ * Purpose: Driver get resource and probe
+ * ----------------------------------------------------------------------------
+ */
+static int ax88796c_drv_probe(struct platform_device *pdev)
+{
+	struct ax88796c_device *ax_local;
+	struct resource *res = NULL;
+	void __iomem *addr;
+	int ret;
+	struct net_device *ndev;
+
+	printk ("AX88796C SRAM-like Linux driver v1.2.100)\n");
+	if (!mem){
+
+		res = platform_get_resource (pdev, IORESOURCE_MEM, 0);
+		if (!res) {
+			printk("%s: get no resource !\n", AX88796C_DRV_NAME);
+			return -ENODEV;
+		}
+
+		mem = res->start;
+	}
+
+	/* Get the IRQ resource from kernel */
+	if(!irq)
+		irq = platform_get_irq(pdev, 0);
+
+	/* Request the regions */
+	if (!request_mem_region (mem, AX88796C_IO_EXTENT, "ax88796c")) {
+		printk("%s: request_mem_region fail !", AX88796C_DRV_NAME);
+		return -EBUSY;
+	}
+
+	addr = ioremap (mem, AX88796C_IO_EXTENT);
+	if (!addr) {
+		ret = -EBUSY;
+		goto release_region;
+	}
+	ndev = alloc_etherdev (sizeof (struct ax88796c_device));
+	if (!ndev) {
+		printk("%s: could not allocate device.\n", AX88796C_DRV_NAME);
+		ret = -ENOMEM;
+		goto unmap_region;
+	}
+
+	SET_NETDEV_DEV(ndev, &pdev->dev);
+	platform_set_drvdata (pdev, ndev);
+
+	ndev->base_addr = mem;
+	ndev->irq = irq;
+
+	ax_local = netdev_priv (ndev);
+	ax_local->membase = addr;
+ 	ax_local->ndev = ndev;
+	ax_local->msg_enable =  msg_enable;
+
+	if (ps_level == AX_PS_D1) {
+		if (netif_msg_probe (ax_local))
+			printk ("AX88796C: Enable power saving level 1\n");
+	} else if (ps_level == AX_PS_D2) {
+		if (netif_msg_probe (ax_local))
+			printk ("AX88796C: Enable power saving level 2\n");
+	} else {
+		if (netif_msg_probe (ax_local))
+			printk ("AX88796C: Power saving disabled\n");
+		ps_level = 0;
+	}
+	ax_local->ps_level = ps_level;
+
+	/* Enable Link Change and Magic Packet wakeup */
+	ax_local->wol = WFCR_LINKCH | WFCR_MAGICP;
+
+	ret = ax88796c_probe (ax_local);
+	if (!ret)
+		return 0;
+
+	platform_set_drvdata (pdev, NULL);
+	free_netdev (ndev);
+unmap_region:
+	iounmap (addr);
+release_region:
+
+	printk("%s: not found (%d).\n", AX88796C_DRV_NAME, ret);
+	return ret;
+}
+
+/* Power management handling functions */
+/*
+ * ----------------------------------------------------------------------------
+ * Function Name: ax88796c_compute_crc16
+ * Purpose: Caculate crc for wakeup pattern
+ * ----------------------------------------------------------------------------
+ */
+static unsigned short ax88796c_compute_crc16 (unsigned char *Buffer, int Length)
+{
+	unsigned short i=0, j=0, k=0, crc=0;
+	unsigned char c[16]={0}, txpd[8]={0}, first_xor=0;
+	crc = 0xFFFF;
+	for(j = 0; j < Length; j++) {
+
+		for(i = 0; i < 16; i++) {
+			c[i] = (crc >> i) & 0x0001;
+		}
+		for(i = 0; i < 8; i++) {
+			txpd[i] = (Buffer[j] >> i) & 0x0001;
+		}
+		for(i = 0; i < 8; i++) {
+			first_xor = c[15]^txpd[i];
+			c[14] = c[14]^first_xor;
+			c[1] = c[1]^first_xor;
+			for(k = 15 ; k > 0; k--) {
+				c[k] = c[k-1];
+			}
+			c[0] = first_xor;
+		}
+
+		crc = (c[15] << 15) | (c[14] << 14) | (c[13] << 13) |
+		      (c[12] << 12) | (c[11] << 11) | (c[10] << 10) |
+		      (c[9] <<  9) |  (c[8] <<  8) | (c[7] <<  7) |
+		      (c[6] <<  6) |  (c[5] <<  5) | (c[4] <<  4) |
+		      (c[3] <<  3) |  (c[2] <<  2) | (c[1] <<  1) | c[0];
+	}
+
+	return crc;
+} /* End of ComputeCRC16() */
+
+/*
+ * ----------------------------------------------------------------------------
+ * Function Name: ax88796c_suspend
+ * Purpose: Device suspend handling function
+ * ----------------------------------------------------------------------------
+ */
+static int
+ax88796c_suspend(struct platform_device *p_dev, pm_message_t state)
+{
+	struct net_device *ndev = dev_get_drvdata(&(p_dev)->dev);
+	struct ax88796c_device *ax_local = netdev_priv (ndev);
+	void __iomem *ax_base = ax_local->membase;
+	unsigned long flags;
+
+	if (!ndev || !netif_running (ndev))
+		return 0;
+
+	netif_device_detach (ndev);
+	netif_stop_queue (ndev);
+
+	spin_lock_irqsave (&ax_local->isr_lock, flags);
+
+	ax88796c_check_power_state (ndev);
+
+	AX_WRITE (IMR_MASKALL, ax_base + P0_IMR);
+
+	ax88796c_free_skbuff (&ax_local->tx_q);
+	ax88796c_free_skbuff (&ax_local->rx_busy_q);
+
+	if (ax_local->wol) {
+
+		AX_SELECT_PAGE(PAGE5, ax_base + PG_PSR);
+		AX_WRITE (0, ax_base + P5_WFTR);
+
+		if (ax_local->wol & WFCR_LINKCH) {	/* Link change */
+
+			/* Disable wol power saving in link change mode */
+			AX_SELECT_PAGE(PAGE0, ax_base + PG_PSR);
+			AX_WRITE ((AX_READ (P0_PSCR + ax_base) & ~PSCR_WOLPS),
+					P0_PSCR + ax_base);
+			AX_SELECT_PAGE(PAGE5, ax_base + PG_PSR);
+
+			if (netif_msg_wol (ax_local))
+				printk ("Enable link change wakeup\n");
+			AX_WRITE (WFTR_8192MS, ax_base + P5_WFTR);
+		}
+		if (ax_local->wol & WFCR_MAGICP) {	/* Magic packet */
+			if (netif_msg_wol (ax_local))
+				printk ("Enable magic packet wakeup\n");
+		}
+		if (ax_local->wol & WFCR_WAKEF) {	/* ARP wakeup */
+			struct in_device *in_dev =
+				(struct in_device *) ndev->ip_ptr;
+
+			/* Get ip address from upper layer */
+			if (in_dev != NULL) {
+				struct in_ifaddr *ifa = in_dev->ifa_list;
+
+				/* caculate crc and mask */
+				if (ifa != NULL) {
+					u8 packet[6];
+
+					packet[0] = 0x08;
+					packet[1] = 0x06;
+					memcpy(&packet[2],
+						&ifa->ifa_address, 4);
+
+					/*
+					 * The CRC will be caculated from
+					 * 12. Last byte is the LSB of the
+					 * ip address.
+					 */
+					AX_WRITE (0x000c, ax_base + P5_WF0BMR0);
+					AX_WRITE (0xf000, ax_base + P5_WF0BMR1);
+					AX_WRITE (((u16)packet[5] << 8 |
+							(10 / 2)),
+							ax_base + P5_WF0OBR);
+					AX_WRITE (ax88796c_compute_crc16 (
+							&packet[0], 6),
+							ax_base + P5_WF0CR);
+					AX_WRITE (WFCR03_F0_EN,
+							ax_base + P5_WFCR03);
+
+					if (netif_msg_wol (ax_local))
+						printk ("Enable ARP wakeup\n");
+				}
+			}
+		}
+
+		AX_SELECT_PAGE(PAGE0, ax_base + PG_PSR);
+		AX_WRITE (ax_local->wol | WFCR_WAKEUP | WFCR_PMEEN,
+				ax_base + P0_WFCR);
+	}
+
+	spin_unlock_irqrestore (&ax_local->isr_lock, flags);
+
+	return 0;
+}
+
+/*
+ * ----------------------------------------------------------------------------
+ * Function Name: ax88796c_resume
+ * Purpose: Device resume handling function
+ * ----------------------------------------------------------------------------
+ */
+static int
+ax88796c_resume(struct platform_device *p_dev)
+{
+	struct net_device *ndev = dev_get_drvdata(&(p_dev)->dev);
+	struct ax88796c_device *ax_local = netdev_priv (ndev);
+	void __iomem *ax_base = ax_local->membase;
+	int ret;
+	u16 pme;
+
+	/* Wakeup AX88796C first */
+	AX_WRITE (0xFF, ax_base + PG_HOST_WAKEUP);
+	msleep (200);
+
+	pme = AX_READ (ax_base + P0_WFCR);
+	if (ax_local->wol && ~(pme & WFCR_WAITEVENT)) {
+
+		if (pme & WFCR_LINKCHS) {
+			if (netif_msg_wol (ax_local))
+				printk ("Wakeuped from link change.\n");
+		} else if (pme & WFCR_MAGICPS) {
+			if (netif_msg_wol (ax_local))
+				printk ("Wakeuped from magic packet.\n");
+		} else if (pme & WFCR_WAKEFS) {
+			if (netif_msg_wol (ax_local))
+				printk ("Wakeuped from wakeup frame.\n");
+		}
+
+		AX_WRITE (WFCR_CLRWAKE, ax_base + P0_WFCR);
+	}
+
+	netif_device_attach(ndev);
+
+	/* Initialize all the local variables*/
+	ax_local->seq_num = 0;
+
+	ax88796c_init (ax_local);
+
+	AX_SELECT_PAGE(PAGE0, ax_local->membase + PG_PSR);
+	netif_start_queue (ndev);
+
+	AX_SELECT_PAGE(PAGE0, ax_local->membase + PG_PSR);
+	AX_WRITE (IMR_DEFAULT, ax_base + P0_IMR);
+
+	ax88796c_set_power_saving (ax_local->ndev, ax_local->ps_level);
+
+	return 0;
+}
+
+/*
+ * ----------------------------------------------------------------------------
+ * Function Name: ax88796c_exit_module
+ * Purpose: Driver Driver clean and exit
+ * ----------------------------------------------------------------------------
+ */
+static int __devexit ax88796c_exit_module(struct platform_device *pdev)
+{
+	struct net_device *ndev = platform_get_drvdata(pdev);
+	struct ax88796c_device *ax_local = netdev_priv (ndev);
+	void __iomem *ax_base = ax_local->membase;
+	struct resource *res;
+
+	platform_set_drvdata (pdev, NULL);
+	unregister_netdev (ndev);
+	iounmap (ax_base);
+
+	if (mem) {
+		release_mem_region (mem, AX88796C_IO_EXTENT);
+	} else {
+		res = platform_get_resource (pdev, IORESOURCE_MEM, 0);
+		if (res)
+			release_mem_region (res->start, AX88796C_IO_EXTENT);
+	}
+	free_netdev (ndev);
+
+	return 1;
+}
+
+/*Fill platform driver information*/
+static struct platform_driver ax88796c_driver = {
+	.driver	= {
+		.name    = "ax88796c",
+		.owner	 = THIS_MODULE,
+	},
+	.probe   = ax88796c_drv_probe,
+	.remove  = __devexit_p(ax88796c_exit_module),
+	.suspend = ax88796c_suspend,
+	.resume  = ax88796c_resume,
+};
+
+/*
+ * ----------------------------------------------------------------------------
+ * Function Name: ax88796c_init_mod
+ * Purpose: Driver initialize
+ * ----------------------------------------------------------------------------
+ */
+static int __init
+ax88796c_init_mod(void)
+{
+	printk("enter ax88796c module\n");
+	return platform_driver_register (&ax88796c_driver);
+}
+
+/*
+ * ----------------------------------------------------------------------------
+ * Function Name: ax88796c_exit_module
+ * Purpose: Platform driver unregister
+ * ----------------------------------------------------------------------------
+ */
+static void __exit
+ax88796c_cleanup(void)
+{
+	/*Unregister platform driver*/
+	platform_driver_unregister (&ax88796c_driver);
+}
+
+
+module_init(ax88796c_init_mod);
+module_exit(ax88796c_cleanup);
+
diff --git a/drivers/net/ax88796c/ax88796c.h b/drivers/net/ax88796c/ax88796c.h
new file mode 100644
index 00000000000..3411c37ac76
--- /dev/null
+++ b/drivers/net/ax88796c/ax88796c.h
@@ -0,0 +1,693 @@
+/*
+ * ASIX AX88796C based Fast Ethernet Devices
+ * Copyright (C) 2009 ASIX Electronics Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef _AX796C_H_
+#define _AX796C_H_
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/version.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/types.h>
+#include <linux/string.h>
+#include <linux/delay.h>
+#include <linux/ioport.h>
+#include <linux/interrupt.h>
+#include <linux/crc32.h>
+#include <linux/mii.h>
+#include <linux/if_vlan.h>
+#include <linux/inetdevice.h>
+
+#include <asm/system.h>
+#include <asm/io.h>
+#include <asm/uaccess.h>
+#include <asm/irq.h>
+//#include <asm/dma.h>
+#include <linux/dma-mapping.h>
+//#include <asm/mach/arch.h>
+#include <linux/platform_device.h>
+
+#ifndef TRUE
+#define TRUE				1
+#endif
+
+#ifndef FALSE
+#define FALSE				0
+#endif
+
+/* AX88796C naming declarations */
+#define AX88796C_DRV_NAME	"AX88796C"
+#define AX88796C_ADP_NAME	"ASIX AX88796C Fast Ethernet Adapter"
+#define AX88796C_DRV_VERSION	"1.2.0"
+#define PFX			AX88796C_DRV_NAME ": "
+
+/* Configuration options */
+#if defined(CONFIG_SOC_JZ4760) || defined(CONFIG_SOC_JZ4760B) 
+#define DATA_PORT_ADDR		0x0020
+#else
+#define DATA_PORT_ADDR		0x4000
+#endif
+
+
+/* AX88796C specific feature settings */
+/* TRUE: enable, FALSE: disable */
+#define AX88796C_8BIT_MODE		FALSE
+#define AX88796C_WATCHDOG_PERIOD	(1 * HZ)
+#define AX88796C_WATCHDOG_RESTART	7
+
+#define TX_DMA_MODE			TRUE
+#define RX_DMA_MODE			TRUE
+
+/* Lutts@20101019 */
+#define AX88796B_PIN_COMPATIBLE		FALSE
+
+/* TX_DMA_MODE and TX_PIO_MODE are mutually exclusive */
+#if (TX_DMA_MODE)
+	#define TX_PIO_MODE		FALSE
+#else
+	#define TX_PIO_MODE		TRUE
+#endif
+
+/* RX_DMA_MODE and RX_PIO_MODE are mutually exclusive */
+#if (RX_DMA_MODE)
+	#define RX_PIO_MODE		FALSE
+#else
+	#define RX_PIO_MODE		TRUE
+#endif
+
+#define TX_QUEUE_HIGH_WATER		45		/* Tx queue high water mark */
+#define TX_QUEUE_LOW_WATER		20		/* Tx queue low water mark */
+
+
+#define TX_MANUAL_DEQUEUE		FALSE
+#if (TX_MANUAL_DEQUEUE)
+#define TX_MANUAL_DEQUEUE_CNT		0x30
+#endif
+
+#if (AX88796C_8BIT_MODE)
+static void inline AX_WRITE (u16 data, void __iomem *mem)
+{
+	writeb ((u8)data, mem);
+	writeb ((u8)(data >> 8), mem + 1);
+}
+
+static u16 inline AX_READ (void __iomem *mem)
+{
+        u16 data;
+        u8 *tmp = (u8 *)&data;
+        *tmp = readb (mem);
+        *(tmp+1) = readb (mem + 1);
+        return data;
+}
+#else
+static void inline AX_WRITE (u16 data, void __iomem *mem)
+{
+	writew (data, mem);
+}
+
+static u16 inline AX_READ (void __iomem *mem)
+{
+	return readw (mem);
+}
+#endif
+
+extern void dma_start (dma_addr_t mem_addr, int len, u8 tx);
+
+#define AX_SELECT_PAGE(a,b)		AX_WRITE (((AX_READ (b) & 0xFFF8) | a) , b)
+
+/* Tx header feilds mask */
+#define TX_HDR_SOP_DICF			0x8000
+#define TX_HDR_SOP_CPHI			0x4000
+#define TX_HDR_SOP_INT			0x2000
+#define TX_HDR_SOP_MDEQ			0x1000
+#define TX_HDR_SOP_PKTLEN		0x07FF
+#define TX_HDR_SOP_SEQNUM		0xF800
+#define TX_HDR_SOP_PKTLENBAR		0x07FF
+
+#define TX_HDR_SEG_FS			0x8000
+#define TX_HDR_SEG_LS			0x4000
+#define TX_HDR_SEG_SEGNUM		0x3800
+#define TX_HDR_SEG_SEGLEN		0x0700
+#define TX_HDR_SEG_EOFST		0xC000
+#define TX_HDR_SEG_EOFBITS		14
+#define TX_HDR_SEG_SOFST		0x3800
+#define TX_HDR_SEG_SOFBITS		11
+#define TX_HDR_SEG_SEGLENBAR		0x07FF
+
+
+#define TX_HDR_EOP_SEQNUM		0xF800
+#define TX_HDR_EOP_PKTLEN		0x07FF
+#define TX_HDR_EOP_SEQNUMBAR		0xF800
+#define TX_HDR_EOP_PKTLENBAR		0x07FF
+
+/* Rx header fields mask */
+#define RX_HDR1_MCBC			0x8000
+#define RX_HDR1_STUFF_PKT		0x4000
+#define RX_HDR1_MII_ERR			0x2000
+#define RX_HDR1_CRC_ERR			0x1000
+#define RX_HDR1_PKT_LEN			0x07FF
+#define RX_HDR2_SEQ_NUM			0xF800
+#define RX_HDR2_PKT_LEN_BAR		0x7FFF
+#define RX_HDR3_CE			(1 << 15)
+#define RX_HDR3_L3_PKT_TYPE(x)		(((x) >> 13) & 0x0003)
+#define RX_HDR3_L4_PKT_TYPE(x)		(((x) >> 10) & 0x0007)
+#define RX_HDR3_L3_ERR			(1 << 9)
+#define RX_HDR3_L4_ERR			(1 << 8)
+#define RX_HDR3_PRIORITY(x)		(((x) >> 4 ) & 0x0007 )
+#define RX_HDR3_STRIP			(1 << 3)
+#define RX_HDR3_VLAN_ID(x)		(x & 0x0007)
+
+/* Tx/Rx buffer offset */
+#define RX_PKT_DATA_OFFSET		6
+
+/* AX88796C Pages index */
+#define PAGE0				0x00
+#define PAGE1				0x01
+#define PAGE2				0x02
+#define PAGE3				0x03
+#define PAGE4				0x04
+#define PAGE5				0x05
+#define PAGE6				0x06
+#define PAGE7				0x07
+
+#define AX_MCAST_FILTER_SIZE		8
+#define AX_MAX_MCAST			64
+
+
+/* CIR bit */
+#define Chip_REV_ID			0xF0
+#define IRQ_POL_HIGH_ACTIVE		0x400
+
+/*PHY*/
+#define PHY_ID_MASK	0x3F
+#define REG_NUM_MASK	0x1F
+#define PHY_ID		0x10
+
+/* General packet handling feature settings */
+#define MAX_PKT_LEN			0x2000
+#define AX88796C_IO_EXTENT		0x6800
+#define ETHER_ADDR_LEN			6
+#define DWORD_ALIGNMENT			0xFFFC
+#define AX88796C_CHIP_ID                0x36
+#define AX88796C_PAGE_SIZE              128	/* 1 page has 128 bytes */
+#define AX88796C_TX_PAGES		32	/* Number of transmit packets */
+#define AX88796C_PAGE_SHIFT             0x07	/* 1 page has 128 bytes */
+/* Sturctures declaration */
+
+/* Tx headers structure */
+struct tx_sop_header {
+	/* bit 15-11: flags, bit 10-0: packet length */
+	u16 flags_pktlen;
+	/* bit 15-11: sequence number, bit 11-0: packet length bar */
+	u16 seqnum_pktlenbar;
+} __attribute__((packed));
+
+struct tx_segment_header {
+	/* bit 15-14: flags, bit 13-11: segment number,
+	   bit 10-0: segment length */
+	u16 flags_seqnum_seglen;
+	/* bit 15-14: end offset, bit 13-11: start offset */
+	/* bit 10-0: segment length bar */
+	u16 eo_so_seglenbar;
+} __attribute__((packed));
+
+struct tx_eop_header {
+	/* bit 15-11: sequence number, bit 10-0: packet length */
+	u16 seqnum_pktlen;
+	/* bit 15-11: sequence number bar, bit 10-0: packet length bar */
+	u16 seqnumbar_pktlenbar;
+} __attribute__((packed));
+
+struct tx_header {
+	struct tx_sop_header sop;
+	struct tx_segment_header seg;
+} __attribute__((packed));
+
+/* Rx headers structure */
+struct rx_header {
+	u16 flags_len;
+	u16 seq_lenbar;
+	u16 flags;
+} __attribute__((packed));
+
+struct skb_data {
+	struct net_device *ndev;
+	size_t len;
+	size_t pages;
+	size_t dma_len;
+	dma_addr_t phy_addr;
+	struct tx_header txhdr;
+	struct tx_eop_header tx_eop;
+	u8 offset;
+};
+
+enum watchdog_state {
+	chk_link = 0,
+	chk_cable,
+	ax_nop,
+};
+
+struct ax88796c_device {
+	struct net_device *ndev;
+	void __iomem *membase;
+	struct mii_if_info mii;
+	struct net_device_stats stat;	/* The new statistics table. */
+
+	spinlock_t isr_lock;
+	struct timer_list watchdog;
+	enum watchdog_state w_state;
+	size_t w_ticks;
+
+	/* Tx variables */
+	u16	seq_num;
+	struct sk_buff_head tx_q;
+	struct sk_buff_head tx_busy_q;
+
+	u8	burst_len;
+		#define DMA_BURST_LEN_2_WORD	0x00
+		#define DMA_BURST_LEN_4_WORD	0x01
+		#define DMA_BURST_LEN_8_WORD	0x10
+		#define DMA_BURST_LEN_16_WORD	0x11
+
+	/* Rx variables */
+	struct sk_buff_head rx_busy_q;
+	unsigned rx_dmaing;
+
+	/* Platform dependent variables */
+	int (*low_level_output) (struct net_device *dev,
+			struct sk_buff *skb, struct skb_data *entry);
+	void (*tx_dma_complete) (void *dev_temp);
+	int (*low_level_input) (struct net_device *dev);
+	void (*rx_dma_complete) (void *dev_temp);
+
+	u16	wol;
+
+	u8	plat_endian;
+		#define PLAT_LITTLE_ENDIAN	0
+		#define PLAT_BIG_ENDIAN		1
+
+	u8	multi_filter[AX_MCAST_FILTER_SIZE];
+
+	u8	checksum;
+		#define AX_RX_CHECKSUM		1
+		#define AX_TX_CHECKSUM		2
+
+	u8	ps_level;
+		#define AX_PS_D0		0
+		#define AX_PS_D1		1
+		#define AX_PS_D2		2
+
+	int	msg_enable;
+
+};
+
+/* A88796C register definition */
+#if (AX88796B_PIN_COMPATIBLE)
+#define AX_SHIFT(x)	((x) << 1)
+#else
+#define AX_SHIFT(x)	((x) << 0)
+#endif
+
+	/* Definition of PAGE0 */
+#define PG_PSR		AX_SHIFT(0x00)
+	#define PSR_BUS_TYPE(x)		((x >> 4) & 0x07)
+	#define BUS_TYPE_8BIT_SRAM	0x00
+	#define BUS_TYPE_8BIT_MULPLEX	0x01
+	#define BUS_TYPE_16BIT_SRAM	0x04
+	#define BUS_TYPE_16BIT_MULPLEX	0x05
+	#define BUS_TYPE_16BIT_LOCALBUS	0x07
+	#define PSR_DEV_READY		(1 << 7)
+	#define PSR_RESET		(0 << 15)
+	#define PSR_RESET_CLR		(1 << 15)
+#define P0_BOR		AX_SHIFT(0x02)
+#define P0_FER		AX_SHIFT(0x04)
+	#define FER_IPALM		(1 << 0)
+	#define FER_DCRC		(1 << 1)
+	#define FER_RH3M		(1 << 2)
+	#define FER_HEADERSWAP		(1 << 7)
+	#define FER_WSWAP		(1 << 8)
+	#define FER_BSWAP		(1 << 9)
+	#define FER_INTHI		(1 << 10)
+	#define FER_INTLO		(0 << 10)
+	#define FER_IRQ_PULL		(1 << 11)
+	#define FER_RXEN		(1 << 14)
+	#define FER_TXEN		(1 << 15)
+#define P0_ISR		AX_SHIFT(0x06)
+	#define ISR_RXPKT		(1 << 0)
+	#define ISR_MDQ			(1 << 4)
+	#define ISR_TXT			(1 << 5)
+	#define ISR_TXPAGES		(1 << 6)
+	#define ISR_TXERR		(1 << 8)
+	#define ISR_LINK		(1 << 9)
+#define P0_IMR		AX_SHIFT(0x08)
+	#define IMR_RXPKT		(1 << 0)
+	#define IMR_MDQ			(1 << 4)
+	#define IMR_TXT			(1 << 5)
+	#define IMR_TXPAGES		(1 << 6)
+	#define IMR_TXERR		(1 << 8)
+	#define IMR_LINK		(1 << 9)
+	#define IMR_MASKALL		(0xFFFF)
+	#define IMR_DEFAULT		(IMR_TXERR)
+#define P0_WFCR		AX_SHIFT(0x0A)
+	#define WFCR_PMEIND		(1 << 0) /* PME indication */
+	#define WFCR_PMETYPE		(1 << 1) /* PME I/O type */
+	#define WFCR_PMEPOL		(1 << 2) /* PME polarity */
+	#define WFCR_PMERST		(1 << 3) /* Reset PME */
+	#define WFCR_SLEEP		(1 << 4) /* Enable sleep mode */
+	#define WFCR_WAKEUP		(1 << 5) /* Enable wakeup mode */
+	#define WFCR_WAITEVENT		(1 << 6) /* Reserved */
+	#define WFCR_CLRWAKE		(1 << 7) /* Clear wakeup */
+	#define WFCR_LINKCH		(1 << 8) /* Enable link change */
+	#define WFCR_MAGICP		(1 << 9) /* Enable magic packet */
+	#define WFCR_WAKEF		(1 << 10) /* Enable wakeup frame */
+	#define WFCR_PMEEN		(1 << 11) /* Enable PME pin */
+	#define WFCR_LINKCHS		(1 << 12) /* Link change status */
+	#define WFCR_MAGICPS		(1 << 13) /* Magic packet status */
+	#define WFCR_WAKEFS		(1 << 14) /* Wakeup frame status */
+	#define WFCR_PMES		(1 << 15) /* PME pin status */
+#define P0_PSCR		AX_SHIFT(0x0C)
+	#define PSCR_PS_MASK		(0xFFF0)
+	#define PSCR_PS_D0		(0)
+	#define PSCR_PS_D1		(1 << 0)
+	#define PSCR_PS_D2		(1 << 1)
+	#define PSCR_FPS		(1 << 3) /* Enable fiber mode PS */
+	#define PSCR_SWPS		(1 << 4) /* Enable software PS control */
+	#define PSCR_WOLPS		(1 << 5) /* Enable WOL PS */
+	#define PSCR_SWWOL		(1 << 6) /* Enable software select WOL PS */
+	#define PSCR_PHYOSC		(1 << 7) /* Internal PHY OSC control */
+	#define PSCR_FOFEF		(1 << 8) /* Force PHY generate FEF */
+	#define PSCR_FOF		(1 << 9) /* Force PHY in fiber mode */
+	#define PSCR_PHYPD		(1 << 10) /* PHY power down. Active high */
+	#define PSCR_PHYRST		(1 << 11) /* PHY reset signal. Active low */
+	#define PSCR_PHYCSIL		(1 << 12) /* PHY cable energy detect */
+	#define PSCR_PHYCOFF		(1 << 13) /* PHY cable off */
+	#define PSCR_PHYLINK		(1 << 14) /* PHY link status */
+	#define PSCR_EEPOK		(1 << 15) /* EEPROM load complete */
+#define P0_MACCR	AX_SHIFT(0x0E)
+	#define MACCR_RXFC_ENABLE	(1 << 3)
+	#define MACCR_RXFC_MASK		0xFFF7
+	#define MACCR_TXFC_ENABLE	(1 << 4)
+	#define MACCR_TXFC_MASK		0xFFEF
+	#define MACCR_PF		(1 << 7)
+	#define MACCR_PMM_BITS		8
+	#define MACCR_PMM_MASK		(0x1F00)
+	#define MACCR_PMM_RESET		(1 << 8)
+	#define MACCR_PMM_WAIT		(2 << 8)
+	#define MACCR_PMM_READY		(3 << 8)
+	#define MACCR_PMM_D1		(4 << 8)
+	#define MACCR_PMM_D2		(5 << 8)
+	#define MACCR_PMM_WAKE		(7 << 8)
+	#define MACCR_PMM_D1_WAKE	(8 << 8)
+	#define MACCR_PMM_D2_WAKE	(9 << 8)
+	#define MACCR_PMM_SLEEP		(10 << 8)
+	#define MACCR_PMM_PHY_RESET	(11 << 8)
+	#define MACCR_PMM_SOFT_D1	(16 << 8)
+	#define MACCR_PMM_SOFT_D2	(17 << 8)
+#define P0_TFBFCR	AX_SHIFT(0x10)
+	#define TFBFCR_SCHE_FREE_PAGE 	0xE07F
+	#define TFBFCR_FREE_PAGE_BITS	0x07
+	#define TFBFCR_FREE_PAGE_LATCH	(1 << 6)
+	#define TFBFCR_SET_FREE_PAGE(x)	((x & 0x3F) << TFBFCR_FREE_PAGE_BITS)
+	#define TFBFCR_TX_PAGE_SET 	(1 << 13)
+	#define TFBFCR_MANU_ENTX	(1 << 15)
+	#define TX_FREEBUF_MASK		0x003F
+	#define TX_DPTSTART		0x4000
+
+#define P0_TSNR		AX_SHIFT(0x12)
+	#define TXNR_TXB_ERR		(1 << 5)
+	#define TXNR_TXB_IDLE		(1 << 6)
+	#define TSNR_PKT_CNT(x)		(((x) & 0x3F) << 8)
+	#define TXNR_TXB_REINIT		(1 << 14)
+	#define TSNR_TXB_START		(1 << 15)
+#define P0_RTDPR	AX_SHIFT(0x14)
+#define P0_RXBCR1	AX_SHIFT(0x16)
+	#define RXBCR1_RXB_DISCARD	(1 << 14)
+	#define RXBCR1_RXB_START	(1 << 15)
+#define P0_RXBCR2	AX_SHIFT(0x18)
+	#define RXBCR2_PKT_MASK		(0xFF)
+	#define RXBCR2_RXPC_MASK	(0x7F)
+	#define RXBCR2_RXB_READY	(1 << 13)
+	#define RXBCR2_RXB_IDLE		(1 << 14)
+	#define RXBCR2_RXB_REINIT	(1 << 15)
+#define P0_RTWCR	AX_SHIFT(0x1A)
+	#define RTWCR_RXWC_MASK		(0x3FFF)
+	#define RTWCR_RX_LATCH		(1 << 15)
+#define P0_RCPHR	AX_SHIFT(0x1C)
+#define PG_HOST_WAKEUP	AX_SHIFT(0x1F)
+
+	/* Definition of PAGE1 */
+#define P1_RPPER	AX_SHIFT(0x02)
+	#define RPPER_RXEN		(1 << 0)
+#define P1_MRCR		AX_SHIFT(0x08)
+#define P1_MDR		AX_SHIFT(0x0A)
+#define P1_RMPR		AX_SHIFT(0x0C)
+#define P1_TMPR		AX_SHIFT(0x0E)
+#define P1_RXBSPCR	AX_SHIFT(0x10)
+	#define RXBSPCR_STUF_WORD_CNT(x)	(((x) & 0x7000) >> 12)
+	#define RXBSPCR_STUF_ENABLE		(1 << 15)
+#define P1_MCR		AX_SHIFT(0x12)
+	#define MCR_SBP			(1 << 8)
+	#define MCR_SM			(1 << 9)
+	#define MCR_CRCENLAN		(1 << 11)
+	#define MCR_STP			(1 << 12)
+	/* Definition of PAGE2 */
+#define P2_CIR		AX_SHIFT(0x02)
+#define P2_POOLCR	AX_SHIFT(0x04)
+	#define POOLCR_POLL_EN		(1 << 0)
+	#define POOLCR_POLL_FLOWCTRL	(1 << 1)
+	#define POOLCR_POLL_BMCR	(1 << 2)
+	#define POOLCR_PHYID(x)		((x) << 8)
+#define P2_PHYSR	AX_SHIFT(0x06)
+#define P2_MDIODR	AX_SHIFT(0x08)
+#define P2_MDIOCR	AX_SHIFT(0x0A)
+	#define MDIOCR_RADDR(x)		((x) & 0x1F)
+	#define MDIOCR_FADDR(x)		(((x) & 0x1F) << 8)
+	#define MDIOCR_VALID		(1 << 13)
+	#define MDIOCR_READ		(1 << 14)
+	#define MDIOCR_WRITE		(1 << 15)
+#define P2_LCR0		AX_SHIFT(0x0C)
+	#define LCR_LED0_EN		(1 << 0)
+	#define LCR_LED0_100MODE	(1 << 1)
+	#define LCR_LED0_DUPLEX		(1 << 2)
+	#define LCR_LED0_LINK		(1 << 3)
+	#define LCR_LED0_ACT		(1 << 4)
+	#define LCR_LED0_COL		(1 << 5)
+	#define LCR_LED0_10MODE		(1 << 6)
+	#define LCR_LED0_DUPCOL		(1 << 7)
+	#define LCR_LED1_EN		(1 << 8)
+	#define LCR_LED1_100MODE	(1 << 9)
+	#define LCR_LED1_DUPLEX		(1 << 10)
+	#define LCR_LED1_LINK		(1 << 11)
+	#define LCR_LED1_ACT		(1 << 12)
+	#define LCR_LED1_COL		(1 << 13)
+	#define LCR_LED1_10MODE		(1 << 14)
+	#define LCR_LED1_DUPCOL		(1 << 15)
+#define P2_LCR1		AX_SHIFT(0x0E)
+	#define LCR_LED2_MASK		(0xFF00)
+	#define LCR_LED2_EN		(1 << 0)
+	#define LCR_LED2_100MODE	(1 << 1)
+	#define LCR_LED2_DUPLEX		(1 << 2)
+	#define LCR_LED2_LINK		(1 << 3)
+	#define LCR_LED2_ACT		(1 << 4)
+	#define LCR_LED2_COL		(1 << 5)
+	#define LCR_LED2_10MODE		(1 << 6)
+	#define LCR_LED2_DUPCOL		(1 << 7)
+#define P2_IPGCR	AX_SHIFT(0x10)
+#define P2_FLHWCR	AX_SHIFT(0x14)
+#define P2_RXCR		AX_SHIFT(0x16)
+	#define RXCR_PRO		(1 << 0)
+	#define RXCR_AMALL		(1 << 1)
+	#define RXCR_SEP		(1 << 2)
+	#define RXCR_AB			(1 << 3)
+	#define RXCR_AM			(1 << 4)
+	#define RXCR_AP			(1 << 5)
+	#define RXCR_ARP		(1 << 6)
+#define P2_JLCR		AX_SHIFT(0x18)
+#define P2_MPLR		AX_SHIFT(0x1C)
+
+	/* Definition of PAGE3 */
+#define P3_MACASR0	AX_SHIFT(0x02)
+	#define P3_MACASR(x)		(P3_MACASR0 + 2*x)
+	#define MACASR_LOWBYTE_MASK 	0x00FF
+	#define MACASR_HIGH_BITS	0x08
+#define P3_MACASR1	AX_SHIFT(0x04)
+#define P3_MACASR2	AX_SHIFT(0x06)
+#define P3_MFAR01	AX_SHIFT(0x08)
+#define P3_MFAR_BASE	AX_SHIFT(0x08)
+	#define P3_MFAR(x)		(P3_MFAR_BASE + 2*x)
+
+#define P3_MFAR23	AX_SHIFT(0x0A)
+#define P3_MFAR45	AX_SHIFT(0x0C)
+#define P3_MFAR67	AX_SHIFT(0x0E)
+#define P3_VID0FR	AX_SHIFT(0x10)
+#define P3_VID1FR	AX_SHIFT(0x12)
+#define P3_EECSR	AX_SHIFT(0x14)
+#define P3_EEDR		AX_SHIFT(0x16)
+#define P3_EECR		AX_SHIFT(0x18)
+	#define EECR_ADDR_MASK		(0x00FF)
+	#define EECR_READ_ACT		(1 << 8)
+	#define EECR_WRITE_ACT		(1 << 9)
+	#define EECR_WRITE_DISABLE	(1 << 10)
+	#define EECR_WRITE_ENABLE	(1 << 11)
+	#define EECR_EE_READY		(1 << 13)
+	#define EECR_RELOAD		(1 << 14)
+	#define EECR_RESET		(1 << 15)
+#define P3_TPCR		AX_SHIFT(0x1A)
+	#define TPCR_PATT_MASK		(0xFF)
+	#define TPCR_RAND_PKT_EN	(1 << 14)
+	#define TPCR_FIXED_PKT_EN	(1 << 15)
+#define P3_TPLR		AX_SHIFT(0x1C)
+	/* Definition of PAGE4 */
+#define P4_COERCR0	AX_SHIFT(0x12)
+	#define COERCR0_RXIPCE		(1 << 0)
+	#define COERCR0_RXIPVE		(1 << 1)
+	#define COERCR0_RXV6PE		(1 << 2)
+	#define COERCR0_RXTCPE		(1 << 3)
+	#define COERCR0_RXUDPE		(1 << 4)
+	#define COERCR0_RXICMP		(1 << 5)
+	#define COERCR0_RXIGMP		(1 << 6)
+	#define COERCR0_RXICV6		(1 << 7)
+
+	#define COERCR0_RXTCPV6		(1 << 8)
+	#define COERCR0_RXUDPV6		(1 << 9)
+	#define COERCR0_RXICMV6		(1 << 10)
+	#define COERCR0_RXIGMV6		(1 << 11)
+	#define COERCR0_RXICV6V6	(1 << 12)
+
+	#define COERCR0_DEFAULT		(COERCR0_RXIPCE | COERCR0_RXV6PE | \
+					 COERCR0_RXTCPE | COERCR0_RXUDPE | \
+					 COERCR0_RXTCPV6 | COERCR0_RXUDPV6)
+#define P4_COERCR1	AX_SHIFT(0x14)
+	#define COERCR1_IPCEDP		(1 << 0)
+	#define COERCR1_IPVEDP		(1 << 1)
+	#define COERCR1_V6VEDP		(1 << 2)
+	#define COERCR1_TCPEDP		(1 << 3)
+	#define COERCR1_UDPEDP		(1 << 4)
+	#define COERCR1_ICMPDP		(1 << 5)
+	#define COERCR1_IGMPDP		(1 << 6)
+	#define COERCR1_ICV6DP		(1 << 7)
+	#define COERCR1_RX64TE		(1 << 8)
+	#define COERCR1_RXPPPE		(1 << 9)
+	#define COERCR1_TCP6DP		(1 << 10)
+	#define COERCR1_UDP6DP		(1 << 11)
+	#define COERCR1_IC6DP		(1 << 12)
+	#define COERCR1_IG6DP		(1 << 13)
+	#define COERCR1_ICV66DP		(1 << 14)
+	#define COERCR1_RPCE		(1 << 15)
+
+	#define COERCR1_DEFAULT		(COERCR1_RXPPPE)
+#define P4_COETCR0	AX_SHIFT(0x16)
+	#define COETCR0_TXIP		(1 << 0)
+	#define COETCR0_TXTCP		(1 << 1)
+	#define COETCR0_TXUDP		(1 << 2)
+	#define COETCR0_TXICMP		(1 << 3)
+	#define COETCR0_TXIGMP		(1 << 4)
+	#define COETCR0_TXICV6		(1 << 5)
+	#define COETCR0_TXTCPV6		(1 << 8)
+	#define COETCR0_TXUDPV6		(1 << 9)
+	#define COETCR0_TXICMV6		(1 << 10)
+	#define COETCR0_TXIGMV6		(1 << 11)
+	#define COETCR0_TXICV6V6	(1 << 12)
+
+	#define COETCR0_DEFAULT		(COETCR0_TXIP | COETCR0_TXTCP | \
+					 COETCR0_TXUDP | COETCR0_TXTCPV6 | \
+					 COETCR0_TXUDPV6)
+#define P4_COETCR1	AX_SHIFT(0x18)
+	#define COETCR1_TX64TE		(1 << 0)
+	#define COETCR1_TXPPPE		(1 << 1)
+
+#define P4_COECEDR	AX_SHIFT(0x1A)
+#define P4_L2CECR	AX_SHIFT(0x1C)
+
+	/* Definition of PAGE5 */
+#define P5_WFTR		AX_SHIFT(0x02)
+	#define WFTR_2MS		(0x01)
+	#define WFTR_4MS		(0x02)
+	#define WFTR_8MS		(0x03)
+	#define WFTR_16MS		(0x04)
+	#define WFTR_32MS		(0x05)
+	#define WFTR_64MS		(0x06)
+	#define WFTR_128MS		(0x07)
+	#define WFTR_256MS		(0x08)
+	#define WFTR_512MS		(0x09)
+	#define WFTR_1024MS		(0x0A)
+	#define WFTR_2048MS		(0x0B)
+	#define WFTR_4096MS		(0x0C)
+	#define WFTR_8192MS		(0x0D)
+	#define WFTR_16384MS		(0x0E)
+	#define WFTR_32768MS		(0x0F)
+#define P5_WFCCR	AX_SHIFT(0x04)
+#define P5_WFCR03	AX_SHIFT(0x06)
+	#define WFCR03_F0_EN		(1 << 0)
+	#define WFCR03_F1_EN		(1 << 4)
+	#define WFCR03_F2_EN		(1 << 8)
+	#define WFCR03_F3_EN		(1 << 12)
+#define P5_WFCR47	AX_SHIFT(0x08)
+	#define WFCR47_F4_EN		(1 << 0)
+	#define WFCR47_F5_EN		(1 << 4)
+	#define WFCR47_F6_EN		(1 << 8)
+	#define WFCR47_F7_EN		(1 << 12)
+#define P5_WF0BMR0	AX_SHIFT(0x0A)
+#define P5_WF0BMR1	AX_SHIFT(0x0C)
+#define P5_WF0CR	AX_SHIFT(0x0E)
+#define P5_WF0OBR	AX_SHIFT(0x10)
+#define P5_WF1BMR0	AX_SHIFT(0x12)
+#define P5_WF1BMR1	AX_SHIFT(0x14)
+#define P5_WF1CR	AX_SHIFT(0x16)
+#define P5_WF1OBR	AX_SHIFT(0x18)
+#define P5_WF2BMR0	AX_SHIFT(0x1A)
+#define P5_WF2BMR1	AX_SHIFT(0x1C)
+
+	/* Definition of PAGE6 */
+#define P6_WF2CR	AX_SHIFT(0x02)
+#define P6_WF2OBR	AX_SHIFT(0x04)
+#define P6_WF3BMR0	AX_SHIFT(0x06)
+#define P6_WF3BMR1	AX_SHIFT(0x08)
+#define P6_WF3CR	AX_SHIFT(0x0A)
+#define P6_WF3OBR	AX_SHIFT(0x0C)
+#define P6_WF4BMR0	AX_SHIFT(0x0E)
+#define P6_WF4BMR1	AX_SHIFT(0x10)
+#define P6_WF4CR	AX_SHIFT(0x12)
+#define P6_WF4OBR	AX_SHIFT(0x14)
+#define P6_WF5BMR0	AX_SHIFT(0x16)
+#define P6_WF5BMR1	AX_SHIFT(0x18)
+#define P6_WF5CR	AX_SHIFT(0x1A)
+#define P6_WF5OBR	AX_SHIFT(0x1C)
+
+/* Definition of PAGE7 */
+#define P7_WF6BMR0	AX_SHIFT(0x02)
+#define P7_WF6BMR1	AX_SHIFT(0x04)
+#define P7_WF6CR	AX_SHIFT(0x06)
+#define P7_WF6OBR	AX_SHIFT(0x08)
+#define P7_WF7BMR0	AX_SHIFT(0x0A)
+#define P7_WF7BMR1	AX_SHIFT(0x0C)
+#define P7_WF7CR	AX_SHIFT(0x0E)
+#define P7_WF7OBR	AX_SHIFT(0x10)
+#define P7_WFR01	AX_SHIFT(0x12)
+#define P7_WFR23	AX_SHIFT(0x14)
+#define P7_WFR45	AX_SHIFT(0x16)
+#define P7_WFR67	AX_SHIFT(0x18)
+#define P7_WFPC0	AX_SHIFT(0x1A)
+#define P7_WFPC1	AX_SHIFT(0x1C)
+
+#endif /* _AX796C_H_ */
diff --git a/drivers/net/ax88796c/ax88796c_dma.c b/drivers/net/ax88796c/ax88796c_dma.c
new file mode 100644
index 00000000000..b15a7e88f1a
--- /dev/null
+++ b/drivers/net/ax88796c/ax88796c_dma.c
@@ -0,0 +1,132 @@
+#include <linux/version.h>
+#include <asm/jzsoc.h>
+#include "ax88796c.h"
+
+struct ax_dma_channel {
+	int		chan;
+	void		*priv;
+	dma_addr_t	dma_addr;
+	void (*dma_complete)(void *data);
+};
+
+static struct ax_dma_channel rx_chan;
+static struct ax_dma_channel tx_chan;
+
+static irqreturn_t ax88796c_dma_callback(int irq, void *devid)
+{
+	struct ax_dma_channel *dma_chan = (struct ax_dma_channel *)devid;
+
+	disable_dma(dma_chan->chan);
+	if (__dmac_channel_address_error_detected(dma_chan->chan)) {
+		printk("%s: DMAC address error.\n",
+		       __FUNCTION__);
+		__dmac_channel_clear_address_error(dma_chan->chan);
+	}
+	if (__dmac_channel_transmit_end_detected(dma_chan->chan)) {
+		__dmac_channel_clear_transmit_end(dma_chan->chan);
+		dma_chan->dma_complete(dma_chan->priv);
+	}
+
+	return IRQ_HANDLED;
+}
+
+static void jz_start_normal_dma(int chan, unsigned long mem_addr, unsigned long dev_addr,
+			     int count, int tx)
+{
+	unsigned long flags;
+	u32 dma_cmd = 0;
+	u32 src_addr = 0;
+	u32 dst_addr = 0;
+	u32 ds = 4;
+
+	BUG_ON(src_addr % 4);
+
+	if (count % 32 == 0)
+		ds = 32; /* 32 byte */
+	else if (count % 16 == 0)
+		ds = 16; /* 16 byte */
+	else
+		ds = 4; /* default to 4 byte */
+
+	flags = claim_dma_lock();
+	dma_cmd = DMAC_DCMD_RDIL_IGN | DMAC_DCMD_TIE;
+	if (tx)
+		dma_cmd |= DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_16;
+	else
+		dma_cmd |= DMAC_DCMD_SWDH_16 | DMAC_DCMD_DWDH_32;
+	switch (ds) {
+	case 32:
+		dma_cmd |= DMAC_DCMD_DS_32BYTE;
+		break;
+
+	case 16:
+		dma_cmd |= DMAC_DCMD_DS_16BYTE;
+		break;
+
+	case 4:
+		dma_cmd |= DMAC_DCMD_DS_32BIT;
+		break;
+
+	default:
+		;
+	}
+	if (tx) {
+		dma_cmd |= DMAC_DCMD_SAI;
+		src_addr = (unsigned int)mem_addr;      /* DMA source address */
+		dst_addr = dev_addr;      /* DMA target address */
+	} else {
+		dma_cmd |= DMAC_DCMD_DAI;
+		src_addr = dev_addr;
+		dst_addr = mem_addr;
+	}
+//	printk("dma_cmd =%08x\n",dma_cmd); //jarvis debug
+//	printk("source addr = %08x \n",src_addr);
+//	printk("target  addr = %08x \n",dst_addr);
+
+	REG_DMAC_DCCSR(chan) |= DMAC_DCCSR_NDES; /* No-descriptor transfer */
+	REG_DMAC_DSAR(chan) = src_addr;
+	REG_DMAC_DTAR(chan) = dst_addr;
+	REG_DMAC_DTCR(chan) = (count + ds - 1) / ds;
+	REG_DMAC_DCMD(chan) = dma_cmd;
+	REG_DMAC_DRSR(chan) = DMAC_DRSR_RS_AUTO;
+
+	REG_DMAC_DMACR(chan / HALF_DMA_NUM) |= DMAC_DMACR_DMAE;
+	REG_DMAC_DCCSR(chan) |= DMAC_DCCSR_EN;
+	release_dma_lock(flags);
+}
+
+void dma_start (dma_addr_t mem_addr, int len, u8 tx) {
+	if (tx) {
+		jz_start_normal_dma(tx_chan.chan, mem_addr, tx_chan.dma_addr, len * 2, tx);
+	} else {
+		jz_start_normal_dma(rx_chan.chan, mem_addr, rx_chan.dma_addr, len * 2, 0);
+	}
+}
+
+int ax88796c_platform_dma_init (unsigned long base_addr,
+				void (*tx_dma_complete)(void *data),
+				void (*rx_dma_complete)(void *data),
+				void *priv)
+{
+	if (rx_dma_complete) {
+		rx_chan.dma_complete = rx_dma_complete;
+		rx_chan.priv = priv;
+		rx_chan.dma_addr = CPHYSADDR(base_addr + DATA_PORT_ADDR);
+		rx_chan.chan = jz_request_dma(DMA_ID_AX88796C_RX,
+					       "ax88796c_rx",
+					       ax88796c_dma_callback,
+					       0, &rx_chan);
+	}
+
+	if (tx_dma_complete) {
+		tx_chan.dma_complete = tx_dma_complete;
+		tx_chan.priv = priv;
+		tx_chan.dma_addr = CPHYSADDR(base_addr + DATA_PORT_ADDR);
+		tx_chan.chan = jz_request_dma(DMA_ID_AX88796C_TX,
+					       "ax88796c_tx",
+					       ax88796c_dma_callback,
+					       0, &tx_chan);
+	}
+
+	return 0;
+}
diff --git a/drivers/net/ax88796c/ax88796c_ioctl.h b/drivers/net/ax88796c/ax88796c_ioctl.h
new file mode 100644
index 00000000000..b86eceb0e79
--- /dev/null
+++ b/drivers/net/ax88796c/ax88796c_ioctl.h
@@ -0,0 +1,52 @@
+
+ /*============================================================================
+ * Module Name: driver.h
+ * Purpose:
+ * Author:
+ * Date:
+ * Notes:
+ * $Log: driver.h,v $
+ * no message
+ *
+ *
+ *=============================================================================
+ */
+
+#ifndef _IOCTL_H
+#define _IOCTL_H
+
+#include <linux/module.h>
+#include <linux/version.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/ethtool.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/delay.h>
+#include <linux/random.h>
+#include <linux/mii.h>
+
+#include <linux/in.h>
+
+#include <asm/system.h>
+#include <asm/io.h>
+#include <asm/uaccess.h>
+
+#include "command.h"
+
+extern struct ethtool_ops ax88796c_ethtool_ops;
+
+u8 ax88796c_check_power_state (struct net_device *ndev);
+void ax88796c_set_power_saving (struct net_device *ndev, u8 ps_level);
+int ax88796c_mdio_read_phy (struct net_device *ndev, int phy_id, int loc);
+int ax88796c_mdio_read(struct net_device *ndev, int phy_id, int loc);
+void ax88796c_mdio_write_phy (struct net_device *ndev,
+			      int phy_id, int loc, int val);
+void ax88796c_mdio_write(struct net_device *ndev, int phy_id, int loc, int val);
+int ax88796c_ioctl(struct net_device *ndev, struct ifreq *ifr, int cmd);
+void ax88796c_set_csums (struct net_device *ndev);
+#endif
+
diff --git a/drivers/net/ax88796c/command.h b/drivers/net/ax88796c/command.h
new file mode 100644
index 00000000000..30026194a37
--- /dev/null
+++ b/drivers/net/ax88796c/command.h
@@ -0,0 +1,37 @@
+/*
+ *********************************************************************************
+ *     Copyright (c) 2005	ASIX Electronic Corporation      All rights reserved.
+ *
+ *     This is unpublished proprietary source code of ASIX Electronic Corporation
+ *
+ *     The copyright notice above does not evidence any actual or intended
+ *     publication of such source code.
+ *********************************************************************************
+ */
+ 
+#ifndef command_h
+#define command_h
+
+/* NAMING CONSTANT DECLARATIONS */
+#define AX88796C_SIGNATURE	"AX88796C"
+
+/* ioctl Command Definition */
+#define AX_PRIVATE		SIOCDEVPRIVATE
+
+/* private Command Definition */
+#define AX_SIGNATURE			0
+#define AX_CFG_TEST_PKT			1
+
+typedef struct _AX_IOCTL_COMMAND {
+
+	unsigned short	ioctl_cmd;
+	unsigned char	sig[16];
+	unsigned char	pattern;
+	unsigned char	type;
+		#define AX_PACKET_TYPE_RAND	1
+		#define AX_PACKET_TYPE_FIX	2
+	unsigned char	speed;
+	unsigned short	length;
+}AX_IOCTL_COMMAND;
+
+#endif /* end of command.h */
diff --git a/drivers/net/jz4760_eth.c b/drivers/net/jz4760_eth.c
index aced853a23f..3c1ee0441d6 100644
--- a/drivers/net/jz4760_eth.c
+++ b/drivers/net/jz4760_eth.c
@@ -1052,7 +1052,7 @@ static int jz_init_hw(struct net_device *dev)
 	struct ethtool_cmd ecmd;
 	int i;
 
-#ifdef CONFIG_SOC_JZ4810
+#if defined(CONFIG_SOC_JZ4770) || defined(CONFIG_SOC_JZ4810)
 	__gpio_as_eth();
 #endif
 
diff --git a/drivers/net/jzcs8900a.c b/drivers/net/jzcs8900a.c
index 0b45081b3a2..52c035902d8 100644
--- a/drivers/net/jzcs8900a.c
+++ b/drivers/net/jzcs8900a.c
@@ -2,7 +2,7 @@
 /*
  * linux/drivers/net/jzcs8900a.c
  *
- * Author: Lucifer  <yliu@ingenic> 
+ * Author: Lucifer  <yliu@ingenic>
  *
  * A Cirrus Logic CS8900A driver for Linux
  * based on the cs89x0 driver written by Russell Nelson,
@@ -55,14 +55,14 @@
 
 #include "jzcs8900a.h"
 
-#define FULL_DUPLEX 
+#define FULL_DUPLEX
 #define INT_PIN                 0
 
 #ifdef CONFIG_SOC_JZ4740
 #define CIRRUS_DEFAULT_IO	0xa8000000
 #define CIRRUS_DEFAULT_IRQ	107
 
-#elif CONFIG_SOC_JZ4750
+#elif defined(CONFIG_SOC_JZ4750)
 #define CIRRUS_DEFAULT_IO	0xac000000
 
 #ifdef CONFIG_JZ4750_FUWA
@@ -71,10 +71,10 @@
 #define CIRRUS_DEFAULT_IRQ	(32*2 +6+48)
 #endif
 
-#elif CONFIG_SOC_JZ4760
-#ifdef CONFIG_JZ4760_LEPUS
+#elif defined(CONFIG_SOC_JZ4760) || defined(CONFIG_SOC_JZ4760B)
+#if defined(CONFIG_JZ4760_LEPUS) || defined(CONFIG_JZ4760B_LEPUS)
 #define CIRRUS_DEFAULT_IO	0xb4000000
-#elif CONFIG_JZ4760_CYGNUS
+#elif defined(CONFIG_JZ4760_CYGNUS) || defined(CONFIG_JZ4760B_CYGNUS)
 #define CIRRUS_DEFAULT_IO	0xb5000000
 #endif
 #define CIRRUS_DEFAULT_IRQ	(GPIO_NET_INT + IRQ_GPIO_0)
@@ -91,20 +91,20 @@ static struct net_device *dev;
 
 /*
  * I/O routines
- */  
+ */
 static void gpio_init_cs8900(void)
 {
 #ifdef CONFIG_SOC_JZ4740
-	__gpio_as_func0(60);             //CS4# 
+	__gpio_as_func0(60);             //CS4#
 	__gpio_as_func0(61);             //RD#
-	__gpio_as_func0(62);             //WR# 
+	__gpio_as_func0(62);             //WR#
 	__gpio_as_irq_high_level(59);    //irq
 	__gpio_disable_pull(59);         //disable pull
 	REG_EMC_SMCR4 |= (1 << 6);       //16bit
-#elif CONFIG_SOC_JZ4750
+#elif defined(CONFIG_SOC_JZ4750)
 	__gpio_as_func0(32*2+23);             //CS3#
-	__gpio_as_func0(32*2+25);             //RD# 
-	__gpio_as_func0(32*2+26);             //WR# 
+	__gpio_as_func0(32*2+25);             //RD#
+	__gpio_as_func0(32*2+26);             //WR#
 
 #ifdef CONFIG_JZ4750_FUWA
 	__gpio_as_irq_high_level(32*4+20);    //irq
@@ -116,26 +116,50 @@ static void gpio_init_cs8900(void)
 
 	REG_EMC_SMCR3 |= (1 << 6);            //16bit
 
-#elif CONFIG_SOC_JZ4760
-
-#ifdef CONFIG_JZ4760_LEPUS
-	/* We use CS6 with 16-bit data width */
-	__gpio_as_func0(32 * 0 + 26);		/* GPA26 CS6# */
-	__gpio_as_func0(32 * 0 + 16);		/* GPA16 RD#  */
-	__gpio_as_func0(32 * 0 + 17);		/* GPA17 WE#  */
- 
-	REG_EMC_SMCR6 &= ~EMC_SMCR_BW_MASK;
-	REG_EMC_SMCR6 |= EMC_SMCR_BW_16BIT;
-
-#elif CONFIG_JZ4760_CYGNUS
-        /* We use CS5 with 16-bit data width */
-	__gpio_as_func0(32 * 0 + 25);		/* GPA25 CS5# */
-	__gpio_as_func0(32 * 0 + 16);		/* GPA16 RD#  */
-	__gpio_as_func0(32 * 0 + 17);		/* GPA17 WE#  */
- 
-	REG_EMC_SMCR5 &= ~EMC_SMCR_BW_MASK;
-	REG_EMC_SMCR5 |= EMC_SMCR_BW_16BIT;
+#elif defined(CONFIG_SOC_JZ4760) || defined(CONFIG_SOC_JZ4760B)
+
+#define RD_N_PIN (32*0 +16)  //gpa16
+#define WE_N_PIN (32*0 +17)  //gpa17
+
+#if defined(CONFIG_JZ4760_LEPUS) ||  defined(CONFIG_JZ4760B_LEPUS)
+#define WAIT_N (32*0 + 27)   //WAIT_N--->gpa27
+#define CS_PIN (32*0 + 26)   //CS6--->gpa26
+
+#elif defined(CONFIG_JZ4760_CYGNUS) || defined(CONFIG_JZ4760B_CYGNUS)
+#define CS_PIN (32*0 + 25)   //CS5--->gpa25
+#define WAIT_N (32*0 + 27)   //WAIT_N--->gpa27
+#define CS8900_RESET_PIN (32 * 1 +23)  //gpb23
+#endif
+	__gpio_as_func0(CS_PIN);
+	__gpio_as_func0(RD_N_PIN);
+	__gpio_as_func0(WE_N_PIN);
+
+	__gpio_as_func0(32 * 1 + 2);
+	__gpio_as_func0(32 * 1 + 3);
+
+
+#if defined(CONFIG_JZ4760_LEPUS) ||  defined(CONFIG_JZ4760B_LEPUS)
+	REG_GPIO_PXFUNS(0) = 0x0000ffff;
+	REG_GPIO_PXTRGC(0) = 0x0000ffff;
+	REG_GPIO_PXSELC(0) = 0x0000ffff;
+
+	__gpio_as_func0(WAIT_N);
+
+	REG_NEMC_SMCR6 &= ~EMC_SMCR_BW_MASK;
+	REG_NEMC_SMCR6 |= EMC_SMCR_BW_16BIT;
+
+#elif defined(CONFIG_JZ4760_CYGNUS)
+	__gpio_as_output(CS8900_RESET_PIN);
+	__gpio_set_pin(CS8900_RESET_PIN);
+	udelay(10000);
+	__gpio_clear_pin(CS8900_RESET_PIN);
+
+	__gpio_as_func0(WAIT_N);
+
+	REG_NEMC_SMCR5 &= ~EMC_SMCR_BW_MASK;
+	REG_NEMC_SMCR5 |= EMC_SMCR_BW_16BIT;
 #endif
+
 	__gpio_as_irq_high_level(GPIO_NET_INT);	/* irq */
 	__gpio_disable_pull(GPIO_NET_INT);	/* disable pull */
 #endif
@@ -590,8 +614,8 @@ int __init cirrus_probe(void)
 		printk(KERN_ERR " Cannot register net device\n");
 		free_netdev(dev);
 		return -ENOMEM;
-	}	
-	
+	}
+
 	return (0);
 }
 
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 81adbdbd504..f74d7e1cd7d 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -411,6 +411,7 @@ config RTC_DRV_DS1216
 	help
 	  If you say yes here you get support for the Dallas DS1216 RTC chips.
 
+
 config RTC_DRV_DS1286
 	tristate "Dallas DS1286"
 	help
@@ -759,4 +760,11 @@ config RTC_DRV_PS3
 	  This driver can also be built as a module. If so, the module
 	  will be called rtc-ps3.
 
+config RTC_DRV_JZ4760B
+	tristate "jz4760b rtc"
+	depends on SOC_JZ4760B
+	help
+	  If you say yes here you get support for the Dallas DS1216 RTC chips.
+
+
 endif # RTC_CLASS
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index 3c0f2b2ac92..b465de2cdbe 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -78,3 +78,4 @@ obj-$(CONFIG_RTC_DRV_WM8350)	+= rtc-wm8350.o
 obj-$(CONFIG_RTC_DRV_X1205)	+= rtc-x1205.o
 obj-$(CONFIG_RTC_DRV_PCF50633)	+= rtc-pcf50633.o
 obj-$(CONFIG_RTC_DRV_PS3)	+= rtc-ps3.o
+obj-$(CONFIG_RTC_DRV_JZ4760B)	+= rtc-jz4760b.o
diff --git a/drivers/rtc/rtc-jz4760b.c b/drivers/rtc/rtc-jz4760b.c
new file mode 100644
index 00000000000..15f537f1221
--- /dev/null
+++ b/drivers/rtc/rtc-jz4760b.c
@@ -0,0 +1,470 @@
+/*
+ * Real Time Clock interface for Jz4760.
+ *
+ * Copyright (C) 2005-2009, Ingenic Semiconductor Inc.
+ *
+ * Author: Richard Feng <cjfeng@ingenic.cn>
+ *         Regen Huang <lhhuang@ingenic.cn>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ */
+
+#include <linux/platform_device.h>
+#include <linux/module.h>
+#include <linux/rtc.h>
+#include <linux/init.h>
+#include <linux/fs.h>
+#include <linux/interrupt.h>
+#include <linux/string.h>
+#include <linux/pm.h>
+#include <linux/bitops.h>
+
+#include <asm/irq.h>
+#include <asm/jzsoc.h>
+
+#define TIMER_FREQ		CLOCK_TICK_RATE
+
+/* The divider is decided by the RTC clock frequency. */
+#define RTC_FREQ_DIVIDER	(32768 - 1)
+
+#define ms2clycle(x)  (((x) * RTC_FREQ_DIVIDER) / 1000)
+
+/* Default time for the first-time power on */
+static struct rtc_time default_tm = {
+	.tm_year = (2010 - 1900), // year 2010
+	.tm_mon = (10 - 1),       // month 10
+	.tm_mday = 1,             // day 1
+	.tm_hour = 12,
+	.tm_min = 0,
+	.tm_sec = 0
+};
+
+static unsigned long rtc_freq = 1024;
+static struct rtc_time rtc_alarm;
+static DEFINE_SPINLOCK(jz4760b_rtc_lock);
+
+static inline int rtc_periodic_alarm(struct rtc_time *tm)
+{
+	return  (tm->tm_year == -1) ||
+		((unsigned)tm->tm_mon >= 12) ||
+		((unsigned)(tm->tm_mday - 1) >= 31) ||
+		((unsigned)tm->tm_hour > 23) ||
+		((unsigned)tm->tm_min > 59) ||
+		((unsigned)tm->tm_sec > 59);
+}
+
+/*
+ * Calculate the next alarm time given the requested alarm time mask
+ * and the current time.
+ */
+static void rtc_next_alarm_time(struct rtc_time *next, struct rtc_time *now, struct rtc_time *alrm)
+{
+	unsigned long next_time;
+	unsigned long now_time;
+
+	next->tm_year = now->tm_year;
+	next->tm_mon = now->tm_mon;
+	next->tm_mday = now->tm_mday;
+	next->tm_hour = alrm->tm_hour;
+	next->tm_min = alrm->tm_min;
+	next->tm_sec = alrm->tm_sec;
+
+	rtc_tm_to_time(now, &now_time);
+	rtc_tm_to_time(next, &next_time);
+
+	if (next_time < now_time) {
+		/* Advance one day */
+		next_time += 60 * 60 * 24;
+		rtc_time_to_tm(next_time, next);
+	}
+}
+static int rtc_update_alarm(unsigned int now,struct rtc_time *alrm,unsigned long *time)
+{
+  struct rtc_time alarm_tm, now_tm;
+  rtc_time_to_tm(now, &now_tm);
+  rtc_next_alarm_time(&alarm_tm, &now_tm, alrm); //?
+  return rtc_tm_to_time(&alarm_tm, time);
+}
+
+#define IS_RTC_IRQ(x,y)  (((x) & (y)) == (y))
+
+static irqreturn_t jz4760b_rtc_interrupt(int irq, void *dev_id)
+{
+	struct platform_device *pdev = to_platform_device(dev_id);
+	struct rtc_device *rtc = platform_get_drvdata(pdev);
+	unsigned int rtsr,save_rtsr;
+	unsigned long events;
+
+	spin_lock(&jz4760b_rtc_lock);
+
+	rtsr = rtc_read_reg(RTC_RTCCR);
+	save_rtsr = rtsr;
+	//is rtc interrupt
+	events = 0;
+	if(IS_RTC_IRQ(rtsr,RTCCR_AF))
+	{
+	  events = RTC_AF | RTC_IRQF;
+	  rtsr &= ~RTCCR_AF;
+
+	  if(rtc_periodic_alarm(&rtc_alarm) == 0)
+	    rtsr &= ~(RTCCR_AIE | RTCCR_AE);
+	  else
+	  {
+	    unsigned int now = rtc_read_reg(RTC_RTCSR);
+	    unsigned long time;
+	    rtc_update_alarm(now,&rtc_alarm,&time);
+	    rtc_write_reg(RTC_RTCSAR,time);
+
+	  }
+	}
+	if(IS_RTC_IRQ(rtsr,RTCCR_1HZ))
+	{
+	  rtsr &= ~(RTCCR_1HZ);
+	  events = RTC_UF | RTC_IRQF;
+	}
+	if(events != 0)
+	  rtc_update_irq(rtc, 1, events);
+	if(rtsr != save_rtsr)
+	  rtc_write_reg(RTC_RTCCR,rtsr);
+	spin_unlock(&jz4760b_rtc_lock);
+	return IRQ_HANDLED;
+}
+
+#if 0
+static int rtc_timer1_count;
+static irqreturn_t timer1_interrupt(int irq, void *dev_id)
+{
+	struct platform_device *pdev = to_platform_device(dev_id);
+	struct rtc_device *rtc = platform_get_drvdata(pdev);
+
+	/*
+	 * If we match for the first time, rtc_timer1_count will be 1.
+	 * Otherwise, we wrapped around (very unlikely but
+	 * still possible) so compute the amount of missed periods.
+	 * The match reg is updated only when the data is actually retrieved
+	 * to avoid unnecessary interrupts.
+	 */
+	OSSR = OSSR_M1;	/* clear match on timer1 */
+
+	rtc_update_irq(rtc, rtc_timer1_count, RTC_PF | RTC_IRQF);
+
+	if (rtc_timer1_count == 1)
+		rtc_timer1_count = (rtc_freq * ((1<<30)/(TIMER_FREQ>>2)));
+
+	return IRQ_HANDLED;
+}
+#endif
+
+#if 0
+static int jz4760b_rtc_read_callback(struct device *dev, int data)
+{
+	if (data & RTC_PF) {
+		/* interpolate missed periods and set match for the next */
+		unsigned long period = TIMER_FREQ/rtc_freq;
+		unsigned long oscr = OSCR;
+		unsigned long osmr1 = OSMR1;
+		unsigned long missed = (oscr - osmr1)/period;
+		data += missed << 8;
+		OSSR = OSSR_M1;	/* clear match on timer 1 */
+		OSMR1 = osmr1 + (missed + 1)*period;
+		/* Ensure we didn't miss another match in the mean time.
+		 * Here we compare (match - OSCR) 8 instead of 0 --
+		 * see comment in pxa_timer_interrupt() for explanation.
+		 */
+		while( (signed long)((osmr1 = OSMR1) - OSCR) <= 8 ) {
+			data += 0x100;
+			OSSR = OSSR_M1;	/* clear match on timer 1 */
+			OSMR1 = osmr1 + period;
+		}
+	}
+	return data;
+}
+#endif
+
+static int jz4760b_rtc_open(struct device *dev)
+{
+	int ret;
+
+	ret = request_irq(IRQ_RTC, jz4760b_rtc_interrupt, IRQF_DISABLED,
+				"rtc 1Hz and alarm", dev);
+	if (ret) {
+		dev_err(dev, "IRQ %d already in use.\n", IRQ_RTC);
+		goto fail_ui;
+	}
+
+	/*ret = request_irq(IRQ_OST1, timer1_interrupt, IRQF_DISABLED,
+				"rtc timer", dev);
+	if (ret) {
+		dev_err(dev, "IRQ %d already in use.\n", IRQ_OST1);
+		goto fail_pi;
+		}*/
+
+	return 0;
+
+ fail_ui:
+	free_irq(IRQ_RTC, dev);
+	return ret;
+}
+
+static void jz4760b_rtc_release(struct device *dev)
+{
+	spin_lock_irq(&jz4760b_rtc_lock);
+
+	spin_unlock_irq(&jz4760b_rtc_lock);
+	//free_irq(IRQ_OST1, dev);
+	free_irq(IRQ_RTC, dev);
+}
+
+static int jz4760b_rtc_ioctl(struct device *dev, unsigned int cmd,
+		unsigned long arg)
+{
+  unsigned int tmp;
+  switch(cmd) {
+	case RTC_AIE_OFF:
+	        spin_lock_irq(&jz4760b_rtc_lock);
+		rtc_clr_reg(RTC_RTCCR, RTCCR_AIE | RTCCR_AE | RTCCR_AF);
+		spin_unlock_irq(&jz4760b_rtc_lock);
+		return 0;
+	case RTC_AIE_ON:
+		spin_lock_irq(&jz4760b_rtc_lock);
+		tmp = rtc_read_reg(RTC_RTCCR);
+		tmp &= ~RTCCR_AF;
+		tmp |= RTCCR_AIE | RTCCR_AE;
+		rtc_write_reg(RTC_RTCCR, tmp);
+		spin_unlock_irq(&jz4760b_rtc_lock);
+		return 0;
+	case RTC_UIE_OFF:
+		spin_lock_irq(&jz4760b_rtc_lock);
+		rtc_clr_reg(RTC_RTCCR, RTCCR_1HZ | RTCCR_1HZIE);
+		spin_unlock_irq(&jz4760b_rtc_lock);
+		return 0;
+	case RTC_UIE_ON:
+		spin_lock_irq(&jz4760b_rtc_lock);
+		tmp = rtc_read_reg(RTC_RTCCR);
+		tmp &= ~RTCCR_1HZ;
+		tmp |= RTCCR_1HZIE;
+		rtc_write_reg(RTC_RTCCR, tmp);
+		spin_unlock_irq(&jz4760b_rtc_lock);
+		return 0;
+	case RTC_PIE_OFF:
+		spin_lock_irq(&jz4760b_rtc_lock);
+		printk("no implement!\n");
+		spin_unlock_irq(&jz4760b_rtc_lock);
+		return 0;
+	case RTC_PIE_ON:
+		spin_lock_irq(&jz4760b_rtc_lock);
+		printk("no implement!\n");
+		spin_unlock_irq(&jz4760b_rtc_lock);
+		return 0;
+	case RTC_IRQP_READ:
+		return put_user(rtc_freq, (unsigned long *)arg);
+	case RTC_IRQP_SET:
+		if (arg < 1 || arg > TIMER_FREQ)
+			return -EINVAL;
+		rtc_freq = arg;
+		return 0;
+	}
+	return -ENOIOCTLCMD;
+}
+
+static int jz4760b_rtc_set_time(struct device *dev, struct rtc_time *tm)
+{
+	unsigned long time;
+	int ret;
+
+	ret = rtc_tm_to_time(tm, &time);
+	if (ret == 0) {
+	  rtc_write_reg(RTC_RTCSR, time);
+	}
+	return ret;
+}
+
+static int jz4760b_rtc_read_time(struct device *dev, struct rtc_time *tm)
+{
+  unsigned int tmp;
+  tmp = rtc_read_reg(RTC_RTCSR);
+  rtc_time_to_tm(tmp, tm);
+
+  if (rtc_valid_tm(tm) < 0) {
+    /* Set the default time */
+    jz4760b_rtc_set_time(dev, &default_tm);
+    tmp = rtc_read_reg(RTC_RTCSR);
+    rtc_time_to_tm(tmp, tm);
+  }
+  return 0;
+}
+
+static int jz4760b_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
+{
+  unsigned int rtc_rcr,tmp;
+  tmp = rtc_read_reg(RTC_RTCSAR);
+  rtc_time_to_tm(tmp, &rtc_alarm);
+  memcpy(&alrm->time, &rtc_alarm, sizeof(struct rtc_time));
+  rtc_rcr = rtc_read_reg(RTC_RTCCR);
+  alrm->enabled = (rtc_rcr & RTCCR_AIE) ? 1 : 0;
+  alrm->pending = (rtc_rcr & RTCCR_AF) ? 1 : 0;
+  return 0;
+}
+
+static int jz4760b_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
+{
+	int ret = 0;
+	unsigned int now;
+	unsigned long time;
+	unsigned int tmp;
+	spin_lock_irq(&jz4760b_rtc_lock);
+	now = rtc_read_reg(RTC_RTCSR);
+	rtc_update_alarm(now,&alrm->time,&time);
+	rtc_write_reg(RTC_RTCSAR, time);
+	if(alrm->enabled)
+	{
+	  tmp = rtc_read_reg(RTC_RTCCR);
+	  tmp &= ~RTCCR_AF;
+	  tmp |= RTCCR_AIE | RTCCR_AE;
+	  rtc_write_reg(RTC_RTCCR, tmp);
+	}else
+	{
+	  rtc_clr_reg(RTC_RTCCR, RTCCR_AIE | RTCCR_AE | RTCCR_AF);
+	}
+	spin_unlock_irq(&jz4760b_rtc_lock);
+
+	return ret;
+}
+
+static int jz4760b_rtc_proc(struct device *dev, struct seq_file *seq)
+{
+	seq_printf(seq, "RTC regulator\t: 0x%08x\n", rtc_read_reg(RTC_RTCGR));
+	seq_printf(seq, "update_IRQ\t: %s\n",
+			(rtc_read_reg(RTC_RTCCR) & RTCCR_1HZIE) ? "yes" : "no");
+	/*seq_printf(seq, "periodic_IRQ\t: %s\n",
+	  (OIER & OIER_E1) ? "yes" : "no");*/
+	seq_printf(seq, "periodic_freq\t: %ld\n", rtc_freq);
+
+	return 0;
+}
+
+static const struct rtc_class_ops jz4760b_rtc_ops = {
+	.open = jz4760b_rtc_open,
+	//.read_callback = jz4760b_rtc_read_callback,
+	.release = jz4760b_rtc_release,
+	.ioctl = jz4760b_rtc_ioctl,
+	.read_time = jz4760b_rtc_read_time,
+	.set_time = jz4760b_rtc_set_time,
+	.read_alarm = jz4760b_rtc_read_alarm,
+	.set_alarm = jz4760b_rtc_set_alarm,
+	.proc = jz4760b_rtc_proc,
+};
+
+static int jz4760b_rtc_probe(struct platform_device *pdev)
+{
+	struct rtc_device *rtc;
+	unsigned int cfc,hspr,rgr_1hz;
+	/*
+	 * When we are powered on for the first time, init the rtc and reset time.
+	 *
+	 * For other situations, we remain the rtc status unchanged.
+	 */
+	cpm_set_clock(CGU_RTCCLK, 32768);
+
+	//unsigned int ppr = IN_RTC_REG(REG_RTC_HWRSR);
+	cfc = HSPR_RTCV;
+	hspr = rtc_read_reg(RTC_HSPR);
+	rgr_1hz = rtc_read_reg(RTC_RTCGR) & RTCGR_NC1HZ_MASK;
+
+	if((hspr != cfc) || (rgr_1hz != RTC_FREQ_DIVIDER))
+	{
+	//if ((ppr >> RTC_HWRSR_PPR) & 0x1) {
+		/* We are powered on for the first time !!! */
+
+		printk("jz4760b-rtc: rtc status reset by power-on\n");
+
+		/* Set 32768 rtc clocks per seconds */
+		rtc_write_reg(RTC_RTCGR, RTC_FREQ_DIVIDER);
+
+		/* Set minimum wakeup_n pin low-level assertion time for wakeup: 100ms */
+		rtc_write_reg(RTC_HWFCR, HWFCR_WAIT_TIME(100));
+		rtc_write_reg(RTC_HRCR, HRCR_WAIT_TIME(60));
+
+                /* Reset to the default time */
+		jz4760b_rtc_set_time(NULL, &default_tm);
+
+		/* start rtc */
+		rtc_write_reg(RTC_RTCCR, RTCCR_RTCE);
+		rtc_write_reg(RTC_HSPR, cfc);
+	}
+
+	/* clear all rtc flags */
+	rtc_write_reg(RTC_HWRSR, 0);
+
+	device_init_wakeup(&pdev->dev, 1);
+	rtc = rtc_device_register(pdev->name, &pdev->dev, &jz4760b_rtc_ops,
+				THIS_MODULE);
+
+	if (IS_ERR(rtc))
+		return PTR_ERR(rtc);
+
+	platform_set_drvdata(pdev, rtc);
+
+	return 0;
+}
+
+static int jz4760b_rtc_remove(struct platform_device *pdev)
+{
+	struct rtc_device *rtc = platform_get_drvdata(pdev);
+
+	rtc_write_reg(RTC_RTCCR, 0);
+ 	if (rtc)
+		rtc_device_unregister(rtc);
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int jz4760b_rtc_suspend(struct platform_device *pdev, pm_message_t state)
+{
+//	if (device_may_wakeup(&pdev->dev))
+//		enable_irq_wake(IRQ_RTC);
+	return 0;
+}
+
+static int jz4760b_rtc_resume(struct platform_device *pdev)
+{
+//	if (device_may_wakeup(&pdev->dev))
+//		disable_irq_wake(IRQ_RTC);
+	return 0;
+}
+#else
+#define jz4760b_rtc_suspend	NULL
+#define jz4760b_rtc_resume	NULL
+#endif
+
+static struct platform_driver jz4760b_rtc_driver = {
+	.probe		= jz4760b_rtc_probe,
+	.remove		= jz4760b_rtc_remove,
+	.suspend	= jz4760b_rtc_suspend,
+	.resume		= jz4760b_rtc_resume,
+	.driver		= {
+		.name		= "jz4760b-rtc",
+	},
+};
+
+static int __init jz4760b_rtc_init(void)
+{
+	return platform_driver_register(&jz4760b_rtc_driver);
+}
+
+static void __exit jz4760b_rtc_exit(void)
+{
+	platform_driver_unregister(&jz4760b_rtc_driver);
+}
+
+module_init(jz4760b_rtc_init);
+module_exit(jz4760b_rtc_exit);
+
+MODULE_AUTHOR("James Jia <ljia@ingenic.cn>");
+MODULE_DESCRIPTION("JZ4760 Realtime Clock Driver (RTC)");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:jz4760b-rtc");
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 2c733c27db2..5cba10efd76 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -194,6 +194,7 @@ config SPI_S3C24XX
 	help
 	  SPI driver for Samsung S3C24XX series ARM SoCs
 
+
 config SPI_S3C24XX_GPIO
 	tristate "Samsung S3C24XX series SPI by GPIO"
 	depends on ARCH_S3C2410 && EXPERIMENTAL
@@ -227,6 +228,17 @@ config SPI_XILINX
 	  See the "OPB Serial Peripheral Interface (SPI) (v1.00e)"
 	  Product Specification document (DS464) for hardware details.
 
+config SPI_JZ47XX
+	tristate "Ingenic JZ47XX series SPI"
+	depends on JZSOC && EXPERIMENTAL
+	select SPI_BITBANG
+	help
+	  SPI driver for Ingenic JZ47XX series SoCs
+
+config JZ_SPI_BOARD_INFO_REGISTER
+    bool "Board info associated by spi master"
+    depends on SPI_JZ47XX
+    default y
 #
 # Add new SPI master controllers in alphabetical order above this line
 #
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 3de408d294b..1d6d452b986 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -16,24 +16,22 @@ obj-$(CONFIG_SPI_BFIN)			+= spi_bfin5xx.o
 obj-$(CONFIG_SPI_BITBANG)		+= spi_bitbang.o
 obj-$(CONFIG_SPI_AU1550)		+= au1550_spi.o
 obj-$(CONFIG_SPI_BUTTERFLY)		+= spi_butterfly.o
-obj-$(CONFIG_SPI_GPIO)			+= spi_gpio.o
 obj-$(CONFIG_SPI_IMX)			+= spi_imx.o
 obj-$(CONFIG_SPI_LM70_LLP)		+= spi_lm70llp.o
 obj-$(CONFIG_SPI_PXA2XX)		+= pxa2xx_spi.o
 obj-$(CONFIG_SPI_OMAP_UWIRE)		+= omap_uwire.o
 obj-$(CONFIG_SPI_OMAP24XX)		+= omap2_mcspi.o
-obj-$(CONFIG_SPI_ORION)			+= orion_spi.o
-obj-$(CONFIG_SPI_PL022)			+= amba-pl022.o
 obj-$(CONFIG_SPI_MPC52xx_PSC)		+= mpc52xx_psc_spi.o
-obj-$(CONFIG_SPI_MPC8xxx)		+= spi_mpc8xxx.o
+obj-$(CONFIG_SPI_MPC83xx)		+= spi_mpc83xx.o
 obj-$(CONFIG_SPI_S3C24XX_GPIO)		+= spi_s3c24xx_gpio.o
 obj-$(CONFIG_SPI_S3C24XX)		+= spi_s3c24xx.o
 obj-$(CONFIG_SPI_TXX9)			+= spi_txx9.o
 obj-$(CONFIG_SPI_XILINX)		+= xilinx_spi.o
-obj-$(CONFIG_SPI_SH_SCI)		+= spi_sh_sci.o
+obj-$(CONFIG_SPI_JZ47XX) 		+= spi_jz47xx.o
 # 	... add above this line ...
 
 # SPI protocol drivers (device/link on bus)
+obj-$(CONFIG_SPI_AT25)		+= at25.o
 obj-$(CONFIG_SPI_SPIDEV)	+= spidev.o
 obj-$(CONFIG_SPI_TLE62X0)	+= tle62x0.o
 # 	... add above this line ...
diff --git a/drivers/spi/spi_jz47xx.c b/drivers/spi/spi_jz47xx.c
new file mode 100644
index 00000000000..27fe5eb78d3
--- /dev/null
+++ b/drivers/spi/spi_jz47xx.c
@@ -0,0 +1,1392 @@
+/* linux/drivers/spi/spi_jz47xx.c

+ *

+ * SSI controller for SPI protocol,use FIFO and DMA;

+ * base-to: linux/drivers/spi/spi_bitbang.c

+ *

+ * Copyright (c) 2010 Ingenic

+ * Author:Shumb <sbhuang@ingenic.cn>

+ *

+ * This program is free software; you can redistribute it and/or modify

+ * it under the terms of the GNU General Public License version 2 as

+ * published by the Free Software Foundation.

+ *

+*/

+

+#include <linux/init.h>

+#include <linux/spinlock.h>

+#include <linux/workqueue.h>

+#include <linux/interrupt.h>

+#include <linux/delay.h>

+#include <linux/errno.h>

+#include <linux/err.h>

+#include <linux/clk.h>

+#include <linux/platform_device.h>

+#include <linux/spi/spi.h>

+#include <linux/spi/spi_bitbang.h>

+

+#include <asm/uaccess.h>

+#include <asm/irq.h>

+#include <asm/io.h>

+#include <asm/jzsoc.h> 

+

+

+//#define SSI_DEGUG

+#ifdef SSI_DEGUG

+#define SSI_KEY_DEGUG

+#define SSI_MSG

+#define  print_dbg(format,arg...)			\

+	printk(format,## arg)

+#else

+#define  print_dbg(format,arg...)	

+#endif

+

+//#define SSI_KEY_DEGUG

+#ifdef SSI_KEY_DEGUG

+#define print_kdbg(format,arg...)			\

+	printk(format,## arg)

+#else

+#define print_kdbg(format,arg...)	

+#endif

+

+//#define SSI_MSG

+#ifdef SSI_MSG

+#define print_msg(format,arg...)			\

+	printk(format,## arg)

+#else

+#define print_msg(format,arg...)	

+#endif

+

+

+/* tx rx threshold from 0x0 to 0xF */

+#define SSI_TX_FIFO_THRESHOLD		0x1

+#define SSI_RX_FIFO_THRESHOLD		(0xF - SSI_TX_FIFO_THRESHOLD)

+

+#define CPU_ONCE_BLOCK_ENTRIES 		((0xF-SSI_TX_FIFO_THRESHOLD)*8)

+

+#define MAX_SSI_INTR		10000

+

+#ifdef CONFIG_SOC_JZ4760  

+#define MAX_SSICDR	63

+#define MAX_CGV		255

+#else

+#define MAX_SSICDR	15

+#define MAX_CGV		255

+#endif

+

+#define GPIO_AS_SSI(n)	 	\

+do{								\

+	if(n) __gpio_as_ssi1();		\

+	else __gpio_as_ssi0();		\

+}while(0)

+#define GPIO_AS_SSI_EX(n)	 	\

+do{								\

+	if(n) __gpio_as_ssi1_x();		\

+	else __gpio_as_ssi0_x();		\

+}while(0)

+

+#if defined(CONFIG_SOC_JZ4760)

+extern unsigned int cpm_get_clock(cgu_clock); 	

+#define CPM_SSI_START(n) 	((n) ?cpm_start_clock(CGM_SSI1):cpm_start_clock(CGM_SSI0))

+#define CPM_SSI_STOP(n)		((n) ?cpm_stop_clock(CGM_SSI1):cpm_stop_clock(CGM_SSI0))

+

+#define SSI0_CE0_PIN	(32*1+29)

+#define SSI0_CE1_PIN	(32*1+31)

+#define SSI0_GPC_PIN	(32*1+30)

+#define SSI1_CE0_PIN	(32*3+29)

+#define SSI1_CE1_PIN	(32*3+30)

+

+#elif defined(CONFIG_SOC_JZ4750D) /* jz4755 */

+#define CPM_SSI_START(n) 	((n) ? :__cpm_start_ssi(0))

+#define CPM_SSI_STOP(n)		((n) ? :__cpm_stop_ssi(0))

+

+#define SSI0_CE0_PIN	(32*1+29)

+#define SSI0_CE1_PIN	(32*1+31)

+#define SSI0_GPC_PIN	(32*1+30)

+#define SSI1_CE0_PIN	(32*1+29)		/* same as SSI0, for avoiding compilation error and ... */

+#define SSI1_CE1_PIN	(32*1+31)

+#else

+#define CPM_SSI_START(n) 	((n) ? __cpm_start_ssi(1):__cpm_start_ssi(0))

+#define CPM_SSI_STOP(n)		((n) ? __cpm_stop_ssi(1):__cpm_stop_ssi(0))

+

+#define SSI0_CE0_PIN	(32*1+29)

+#define SSI0_CE1_PIN	(32*1+31)

+#define SSI0_GPC_PIN	(32*1+30)

+#define SSI1_CE0_PIN	(32*3+29)

+#define SSI1_CE1_PIN	(32*3+30)

+#endif

+

+struct jz47xx_spi {

+	/* bitbang has to be first */

+	struct spi_bitbang	 bitbang;

+	struct completion	 done;

+	

+	u8			 chnl;

+	u8			 rw_mode;

+

+	u8			 use_dma;

+	u8			 is_first;

+	

+	void __iomem		*regs;

+	int			 irq;

+	u32			 len;

+	u32			 rlen;	  /* receive len */

+	u32			 count;   /* sent count */

+

+	u8			 bits_per_word;		/*8 or 16 (or 32)*/

+	u8			 transfer_unit_size;	/* 1 or 2 (or 4) */

+	u8			 tx_trigger;					/* 0-128 */

+	u8			 rx_trigger;					/* 0-128 */

+	u8			 dma_tx_unit;			/* 1 or 2 or 4 or 16 or 32*/

+	u8			 dma_rx_unit;			/* 1 or 2 or 4 or 16 or 32*/

+	void			(*set_cs)(struct jz47xx_spi_info *spi, u8 cs, unsigned int pol);

+	

+	/* functions to deal with different size buffers */

+	void (*get_rx) (u16 rx_data, struct jz47xx_spi *);

+	u16 (*get_tx) (struct jz47xx_spi *);

+	

+	/* data buffers */

+	const u8	*tx;

+	u8			*rx;

+

+	int dma_tx_chnl;                 /* dma tx channel                  */

+	int dma_rx_chnl;                 /* dma rx channel                  */

+	

+	dma_addr_t	tx_dma;

+	dma_addr_t	rx_dma;

+	

+	unsigned long src_clk;

+	unsigned long spi_clk;

+	

+	struct jz_intr_cnt *g_jz_intr;

+

+	struct resource		*ioarea;

+	struct spi_master	*master;

+	struct device		*dev;

+	struct jz47xx_spi_info *pdata;

+};

+

+

+struct jz_intr_cnt{

+	int dma_tx_cnt;

+	int dma_rx_cnt;

+	int ssi_intr_cnt;

+	int ssi_txi;

+	int ssi_rxi;

+	int ssi_eti;

+	int ssi_eri;

+	int ssi_rlen;

+	int dma_tx_err;

+	int dma_tx_end;

+	int dma_rx_err;

+	int dma_rx_end;

+};

+

+static inline struct jz47xx_spi *to_hw(struct spi_device *sdev)

+{

+	return spi_master_get_devdata(sdev->master);

+}

+

+static void jz47xx_spi_cs(struct jz47xx_spi_info *spi, u8 cs, unsigned int pol)

+{

+	u32 pin_value = spi->pin_cs[cs];

+

+	__gpio_as_output(pin_value);

+	if(!pol)

+		__gpio_clear_pin(pin_value);

+	else

+		__gpio_set_pin(pin_value);

+	

+	print_msg("GPIO_PIN:0x%04X  LEVEL: %d:%d\n",

+		pin_value,pol,__gpio_get_pin(pin_value));

+

+}

+static void jz47xx_spi_chipsel(struct spi_device *spi, int value)

+{

+	struct jz47xx_spi *hw = to_hw(spi);

+	unsigned int cspol = spi->mode & SPI_CS_HIGH ? 1 : 0;

+

+	switch (value) {

+	case BITBANG_CS_INACTIVE:

+		if(hw->set_cs)

+			hw->set_cs(hw->pdata,spi->chip_select, cspol^1);

+		break;

+

+	case BITBANG_CS_ACTIVE:

+

+		if (spi->mode & SPI_CPHA)

+			__ssi_set_spi_clock_phase(hw->chnl,1);

+		else

+			__ssi_set_spi_clock_phase(hw->chnl,0);

+		

+		if (spi->mode & SPI_CPOL)

+			__ssi_set_spi_clock_polarity(hw->chnl,1);

+		else

+			__ssi_set_spi_clock_polarity(hw->chnl,0);

+

+		if (!(spi->mode & SPI_LSB_FIRST))

+			__ssi_set_msb(hw->chnl);

+		else

+			__ssi_set_lsb(hw->chnl);

+		

+		if(spi->mode & SPI_LOOP)

+			__ssi_enable_loopback(hw->chnl);

+		else

+			__ssi_disable_loopback(hw->chnl);

+

+		if(hw->set_cs)

+			hw->set_cs(hw->pdata,spi->chip_select, cspol);

+

+		break;

+	default:

+		break;

+	}

+}

+

+#define JZ47XX_SPI_RX_BUF(type) 			\

+void jz47xx_spi_rx_buf_##type(u16 data, struct jz47xx_spi *hw) \

+{									  		\

+	type * rx = (type *)hw->rx;				\

+	*rx++ = (type)(data);			  		\

+	hw->rx = (u8 *)rx;						\

+}

+

+#define JZ47XX_SPI_TX_BUF(type)				\

+u16 jz47xx_spi_tx_buf_##type(struct jz47xx_spi *hw)	\

+{										\

+	u16 data;							\

+	const type * tx = (type *)hw->tx;	\

+	data = *tx++;						\

+	hw->tx = (u8 *)tx;					\

+	return data;						\

+}

+

+JZ47XX_SPI_RX_BUF(u8)

+JZ47XX_SPI_RX_BUF(u16)

+JZ47XX_SPI_TX_BUF(u8)

+JZ47XX_SPI_TX_BUF(u16)

+

+static unsigned int jz_spi_get_clk(struct spi_device *spi)

+{

+	struct jz47xx_spi *hw = to_hw(spi);

+	int ssicdr,cgv;

+	unsigned long clk;

+	

+	ssicdr 	= __cpm_get_ssidiv();

+	cgv 	= __ssi_get_grdiv(hw->chnl);

+#ifdef CONFIG_SOC_JZ4760

+	if(!hw->pdata->is_pllclk)

+		ssicdr = 0;

+#endif

+	clk = hw->src_clk/(2*(cgv+1)*(ssicdr+1));

+	hw->spi_clk = clk;

+	return clk;

+}

+

+static unsigned int jz_spi_set_clk(struct spi_device *spi,u32 hz)

+{

+	struct jz47xx_spi *hw = to_hw(spi);

+	int div,ssicdr=0,cgv=0;

+	u32 ssiclk;

+

+	ssiclk = hw->src_clk;

+

+	div = ssiclk/ hz;

+

+	/* clk = (exclk or pllclk)/( (SSICDR +1) * (2*(CGV+1)) )    */

+	/* 4750: SSICDR (0-15)   CGV (0-255)   16*(2*256)     		*/

+	/* 4760: SSICDR (0-63)   CGV (0-255)   64*(2*256)	  		*/

+

+	if(hw->pdata->is_pllclk){  		/* source clock is PLLCLK */

+		if(div <= 2*(MAX_SSICDR+1)){

+			cgv    = 0;

+			ssicdr = div/2 -1;

+		}else if(div <= 2*(MAX_CGV+1)*(MAX_SSICDR+1)){	

+			ssicdr = MAX_SSICDR;

+			cgv    = (div/(MAX_SSICDR+1))/2 - 1;

+

+		}else{

+			ssicdr = MAX_SSICDR;

+			cgv	   = MAX_CGV;

+		}	

+	}else{  						/* source clock is EXCLK */

+		if(div <= 2*(MAX_CGV+1)){	

+			cgv    = div/2- 1;

+		}else

+			cgv	   = MAX_CGV;

+	}

+

+	if (cgv < 0)

+		cgv = 0;

+	if (ssicdr < 0)

+		ssicdr = 0;

+	

+	dev_dbg(&spi->dev,"SSICLK:%d setting pre-scaler to %d (hz %d) SSICDR:%d  CGV:%d\n",

+		ssiclk,div, hz,ssicdr,cgv);

+

+	__ssi_disable(0);

+	__ssi_disable(1);

+	__cpm_set_ssidiv(ssicdr);

+	__ssi_set_grdiv(hw->chnl,cgv);

+

+	return 0;

+}

+

+/* every spi_transfer could call this routine to setup itself */

+static int jz47xx_spi_setupxfer(struct spi_device *spi,struct spi_transfer *t)

+{

+	struct jz47xx_spi *hw = to_hw(spi);

+	u8 uintbits,bpw;

+	u32 hz;

+	

+	bpw = t ? t->bits_per_word : spi->bits_per_word;

+	hz  = t ? t->speed_hz : spi->max_speed_hz;

+

+	if(t){

+		if(!bpw)

+			bpw = spi->bits_per_word;

+		if(!hz) 

+			hz= spi->max_speed_hz;

+	}

+	

+	if (bpw < 2 || bpw > 17) {

+		dev_err(&spi->dev, "invalid bits-per-word (%d)\n", bpw);

+		return -EINVAL;

+	}

+

+	hw->bits_per_word = bpw;

+	if(bpw <= 8 ){

+		hw->transfer_unit_size = FIFO_8_BIT;

+		hw->get_rx = jz47xx_spi_rx_buf_u8;

+		hw->get_tx = jz47xx_spi_tx_buf_u8;

+	}else if(bpw <= 16){

+		hw->transfer_unit_size = FIFO_16_BIT;

+		hw->get_rx = jz47xx_spi_rx_buf_u16;

+		hw->get_tx = jz47xx_spi_tx_buf_u16;

+	}

+	uintbits = hw->transfer_unit_size*8;

+	

+	__ssi_set_frame_length(hw->chnl,uintbits);

+

+//	__ssi_set_frame_length(hw->chnl,bpw);

+

+	jz_spi_set_clk(spi,hz);

+

+	

+	dev_dbg(&spi->dev,"The real SPI CLK is %d Hz\n",jz_spi_get_clk(spi));

+	

+//	__ssi_set_clk(pdev->id,__cpm_get_extalclk(),hz);

+

+	spin_lock(&hw->bitbang.lock);

+	if (!hw->bitbang.busy) {

+		hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE);

+		/* need to ndelay for 0.5 clocktick ? */

+	}

+	spin_unlock(&hw->bitbang.lock);

+

+	return 0;

+}

+/* the spi->mode bits understood by this driver: */

+#define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST | SPI_LOOP)

+

+static int jz47xx_spi_setup(struct spi_device *spi)

+{

+	int ret;

+	

+	if (!spi->bits_per_word)

+		spi->bits_per_word = 8;

+

+	

+	if (spi->mode & ~MODEBITS) {

+		dev_info(&spi->dev, "Warning: unsupported mode bits %x\n",

+			spi->mode & ~MODEBITS);

+		return -EINVAL;

+	}

+	if (!spi->max_speed_hz)

+		return -EINVAL;

+	

+	ret = jz47xx_spi_setupxfer(spi, NULL);

+	if (ret < 0) {

+		dev_err(&spi->dev, "Warning:setupxfer returned %d\n", ret);

+		return ret;

+	}

+

+	return 0;

+}

+

+static inline int cpu_write_txfifo(struct jz47xx_spi *hw,unsigned int entries)

+{

+	unsigned int i;

+	u16 dat;

+		

+	if((!entries )|| (!(hw->rw_mode & RW_MODE)))

+	{

+		return -1;

+	}else if(hw->rw_mode & W_MODE)

+	{                           

+		for(i=0;i<entries;i++)

+		{

+			dat = hw->get_tx(hw);

+			__ssi_transmit_data(hw->chnl,dat);

+			print_dbg("0x%x,",dat);

+		}	

+	}else

+	{		 /* read, fill txfifo with 0 */

+		

+		for(i=0;i<entries;i++)

+			__ssi_transmit_data(hw->chnl,0);

+		print_dbg("0x0...,");

+	}

+	print_kdbg("+:%d ",entries);

+

+	return 0;	

+}

+static inline int spi_start_dma(struct jz47xx_spi *hw,unsigned int count, int mode)

+{

+	unsigned char dma_unit,src_bit,dest_bit;

+	unsigned char bpw = hw->transfer_unit_size * 8;

+	int chan;

+	unsigned int phyaddr;

+	unsigned long flags;

+

+	mode &= DMA_MODE_MASK;

+	if( mode == DMA_MODE_READ ){	/* dma read rxfifo */

+		chan = hw->dma_rx_chnl;

+		src_bit  = bpw;

+		dest_bit = 32;

+		phyaddr  = hw->rx_dma;	

+		dma_unit = hw->dma_tx_unit;

+	}else if( mode == DMA_MODE_WRITE ){  /* dma write txfifo */

+		chan = hw->dma_tx_chnl;

+		src_bit  = 32;

+		dest_bit = bpw;

+		phyaddr  = hw->tx_dma;

+		dma_unit = hw->dma_rx_unit;

+	}else{

+		dev_err(hw->dev,"SPI Start DMA Fail(Mode Error) !!!\n");

+		return -SPI_DMA_ERROR;

+	}

+

+	flags = claim_dma_lock();

+	disable_dma(chan);

+	clear_dma_ff(chan);	

+	jz_set_dma_src_width(chan, src_bit);

+	jz_set_dma_dest_width(chan, dest_bit);

+

+	jz_set_dma_block_size(chan, dma_unit);	 /* n byte burst */

+	set_dma_mode(chan, mode);

+	set_dma_addr(chan, phyaddr);

+	set_dma_count(chan, count + dma_unit -1); /* ensure dma count align */

+	enable_dma(chan);

+	release_dma_lock(flags);

+

+	return 0;

+}

+

+static inline int spi_dma_setup(struct jz47xx_spi *hw,unsigned int len)

+{

+	int status = 0;

+

+	if(hw->rx_trigger < hw->dma_rx_unit)

+		print_dbg("DMA  probable get invalid datas from SSI RxFIFO\n");

+	

+	if(hw->rw_mode & W_DMA){

+		

+		/* Start Rx to read if hw->rx_dma is not NULL */

+		if(hw->rx_dma)

+			status = spi_start_dma(hw,len,DMA_MODE_READ);

+

+		/* Start Tx for dummy write */

+		status = spi_start_dma(hw,len,DMA_MODE_WRITE);

+		if(status < 0)

+			return status;

+		print_kdbg("DMA Read and Write\n");

+		

+	}else{

+		if(!hw->tx_dma)

+			hw->tx_dma = hw->rx_dma;

+

+		/* Start Rx to read */

+		status = spi_start_dma(hw,len,DMA_MODE_READ);

+

+		/* Start Tx for dummy write */

+		status = spi_start_dma(hw,len,DMA_MODE_WRITE);

+

+		if(status < 0)

+			return status;

+		

+		print_kdbg("DMA Read sent\n");

+	}

+	

+	return status;

+}

+

+/* Fill SSI TxFIFO according to the data count,and decide whether DMA is used */

+static inline int fill_txfifo(struct jz47xx_spi *hw)

+{

+	unsigned char int_flag = 0,last_flag = 0;

+	unsigned int leave_len_bytes,unit_size,trigger,send_entries,entries=0;

+	int status = 0;

+	hw->use_dma = 0;

+

+	leave_len_bytes = hw->len - hw->count;

+	/* calculate the left entries */

+	unit_size = hw->transfer_unit_size;

+	if( unit_size == FIFO_8_BIT )

+		entries = leave_len_bytes;

+	else if(unit_size == FIFO_16_BIT )

+	{

+		entries = (leave_len_bytes + 1)/2;

+	}else{

+		dev_err(hw->dev,"transfer_unit_size error!\n");

+		return -1;

+	}

+	

+	if(leave_len_bytes == 0)								/* --- End or ??? --- */

+	{

+		int_flag = 0;

+		print_dbg("leave_len_bytes = 0\n");

+		

+	}else if(hw->rw_mode & R_DMA ||hw->rw_mode & W_DMA) 	/* --- DMA transfer --- */

+	{													

+		/* change SSI trigger for DMA transfer */

+		/* Important!!! it probable die in waitting for DMA_RX_END intr

+			if configure improper. */

+		hw->rx_trigger = hw->dma_rx_unit / unit_size;

+		

+		if(hw->rx_trigger < hw->dma_rx_unit)

+			print_dbg("DMA probable get invalid datas from SSI RxFIFO\n");

+		

+		__ssi_set_rx_trigger(hw->chnl,hw->rx_trigger);

+		

+		status = spi_dma_setup(hw,leave_len_bytes);

+		if(status < 0)

+			return status;

+

+		hw->use_dma = 1;

+	

+		hw->count += leave_len_bytes;

+		

+	}else{			 									 /* --- CPU transfer --- */	

+

+		trigger = JZ_SSI_MAX_FIFO_ENTRIES - hw->tx_trigger;

+		

+		/* calculate the entries which will be sent currently  */

+		if(hw->is_first){  /* distinguish between the first and interrupt */

+

+			/* CPU Mode should reset SSI triggers at first */

+			hw->tx_trigger = SSI_TX_FIFO_THRESHOLD*8;

+			hw->rx_trigger = SSI_RX_FIFO_THRESHOLD*8;

+			__ssi_set_tx_trigger(hw->chnl,hw->tx_trigger);

+			__ssi_set_rx_trigger(hw->chnl,hw->rx_trigger);

+			

+			if(entries <= JZ_SSI_MAX_FIFO_ENTRIES)	

+				send_entries = entries;

+			else{ 			

+			/* need enable half_intr, left entries will be sent in SSI interrupt 

+				and receive the datas*/

+				send_entries = JZ_SSI_MAX_FIFO_ENTRIES;

+				int_flag = 1;

+			}

+		}else{	/* happen in interrupts */

+			if(entries <= trigger){

+				send_entries = entries;

+				last_flag = 1;	/* the last part of data shouldn't disable RXI_intr at once !!! */

+			}

+			else{			

+			/* need enable half_intr, left entries will be sent in SSI interrupt 

+			and receive the datas*/

+				send_entries = CPU_ONCE_BLOCK_ENTRIES;

+				int_flag = 1;

+			}

+		}

+		/* fill the txfifo with CPU Mode */

+		cpu_write_txfifo(hw,send_entries);

+		hw->count += (send_entries*unit_size);

+	}

+	

+	/* every time should control the SSI half_intrs */

+	if(int_flag)

+	{	

+		__ssi_enable_txfifo_half_empty_intr(hw->chnl);

+		__ssi_enable_rxfifo_half_full_intr(hw->chnl);

+	}else

+	{

+		__ssi_disable_txfifo_half_empty_intr(hw->chnl);

+		__ssi_disable_rxfifo_half_full_intr(hw->chnl);

+	}

+	

+	/* to avoid RxFIFO overflow when CPU Mode at last time to fill */

+	if(last_flag)

+	{				

+		last_flag = 0;

+		__ssi_enable_rxfifo_half_full_intr(hw->chnl);

+	}

+

+	print_dbg("-----SSI%d half_int_flag= %d ,use_dma= %d\n",

+		hw->chnl,int_flag,hw->use_dma);

+	

+	return status;

+}

+void print_ssi_regs(u8 n)

+{

+	print_msg("\nSSI%d\n",n);

+//	print_msg("REG_SSI_DR ========0x%x  \n",REG_SSI_DR(n));

+	print_msg("REG_SSI_CR0========0x%x  \n",REG_SSI_CR0(n));

+	print_msg("REG_SSI_CR1========0x%x  \n",REG_SSI_CR1(n));

+	print_msg("REG_SSI_SR ========0x%x  \n",REG_SSI_SR(n));

+	print_msg("REG_SSI_ITR========0x%x  \n",REG_SSI_ITR(n));

+	print_msg("REG_SSI_ICR========0x%x  \n",REG_SSI_ICR(n));

+	print_msg("REG_SSI_GR ========0x%x  \n",REG_SSI_GR(n));

+

+}

+

+void save_ssi_regs(u32 *regs,u8 n)

+{

+	regs[0]=REG_SSI_CR0(n);

+	regs[1]=REG_SSI_CR1(n);

+	regs[2]=REG_SSI_SR(n);

+	regs[3]=REG_SSI_ITR(n);

+	regs[4]=REG_SSI_ICR(n);

+	regs[5]=REG_SSI_GR(n);

+

+//	return &regs[0];

+}

+

+void show_ssi_regs(u32 *regs)

+{

+	

+//	print_msg("REG_SSI_DR ========0x%x  \n",REG_SSI_DR(n));

+	print_msg("\nREG_SSI_CR0=====0x%x  \n",regs[0]);

+	print_msg("REG_SSI_CR1=====0x%x  \n",regs[1]);

+	print_msg("REG_SSI_SR =====0x%x  \n",regs[2]);

+	print_msg("REG_SSI_ITR=====0x%x  \n",regs[3]);

+	print_msg("REG_SSI_ICR=====0x%x  \n",regs[4]);

+	print_msg("REG_SSI_GR =====0x%x  \n",regs[5]);

+}

+

+static int jz47xx_spi_txrx(struct spi_device * spi, struct spi_transfer *t)

+{

+	int status;

+	struct jz47xx_spi * hw = to_hw(spi);

+	struct jz_intr_cnt *g_jz_intr = hw->g_jz_intr;

+

+	

+	print_dbg("in %s\n",__FUNCTION__);

+	

+	print_kdbg("mname: %s  txrx: tx %p, rx %p, len %d ,tx_dma 0x%08X ,rx_dma 0x%08X\n",

+		spi->modalias,t->tx_buf, t->rx_buf, t->len, t->tx_dma ,t->rx_dma);	

+

+	hw->tx = t->tx_buf;

+	hw->rx = t->rx_buf;

+	hw->tx_dma = t->tx_dma;

+	hw->rx_dma = t->rx_dma;

+	hw->len = t->len;

+	hw->count = 0;

+	hw->rlen = 0;

+

+//	dma_cache_wback_inv((unsigned long)t->tx_dma,t->len);

+//	dma_cache_wback_inv((unsigned long)t->rx_dma,t->len);

+	

+	if( REG_SSI_CR0(hw->chnl) & (1<<10) )

+		print_dbg("Loop Mode\n");

+	else

+		print_dbg("Normal Mode\n");

+	

+

+	hw->rw_mode = 0;

+	if(hw->tx)

+		hw->rw_mode |= W_MODE; 

+	if(hw->rx)

+		hw->rw_mode |= R_MODE; 

+

+	if(hw->tx_dma)

+		hw->rw_mode |= W_DMA;

+	if(hw->rx_dma)

+		hw->rw_mode |= R_DMA;

+

+	print_kdbg("hw->rw_mode = 0x%X\n",hw->rw_mode);

+	

+	__ssi_disable_tx_intr(hw->chnl);

+	__ssi_disable_rx_intr(hw->chnl);

+

+	__ssi_wait_transmit(hw->chnl);

+	/* flush TX FIFO and fill FIFO */

+	__ssi_flush_fifo(hw->chnl);

+	

+	__ssi_enable_receive(hw->chnl);

+	__ssi_clear_errors(hw->chnl);

+	

+	memset(g_jz_intr, 0, sizeof *g_jz_intr);

+	

+	hw->is_first = 1;

+	status = fill_txfifo(hw);

+

+	if(status == -SPI_DMA_ERROR){

+			hw->rw_mode &= ~RW_DMA;

+			dev_info(hw->dev,"Try CPU mode instead!\n");

+			status = fill_txfifo(hw);

+	}

+	if(status < 0)

+	{

+		__ssi_disable_tx_intr(hw->chnl);

+		__ssi_disable_tx_intr(hw->chnl);

+		dev_err(hw->dev,"CPU mode fail!\n");

+		return -1;

+	}

+	

+	if(hw->use_dma){

+		__ssi_disable_tx_error_intr(hw->chnl);

+		__ssi_disable_rx_error_intr(hw->chnl);

+

+	}else{

+		__ssi_enable_tx_error_intr(hw->chnl);

+		__ssi_enable_rx_error_intr(hw->chnl);

+	}

+	hw->is_first = 0;

+	

+	/* start SSI transfer, and start DMA transfer when DMA Mode */

+	__ssi_enable(hw->chnl);

+

+	/* wait the interrupt finish the transfer( one spi_transfer be sent ) */

+	wait_for_completion(&hw->done);

+	

+	__ssi_finish_transmit(hw->chnl);

+	__ssi_clear_errors(hw->chnl);

+

+	/* ------- for debug --------- */

+	print_msg("\ninterrupt Enable:\nTIE:%d RIE:%d \nTEIE:%d REIE:%d\n",

+		(regs[0]&1<<14)>>14,(regs[0]&1<<13)>>13,(regs[0]&1<<12)>>12,(regs[0]&1<<11)>>11);

+	print_msg("\nSSI interrupt cnts = %d\n",g_jz_intr->ssi_intr_cnt);

+	

+	print_msg("TXI:%d  RXI:%d\nunderrun:%d  overrun:%d\n\n",

+		g_jz_intr->ssi_txi,g_jz_intr->ssi_rxi,g_jz_intr->ssi_eti,g_jz_intr->ssi_eri);

+

+	print_msg("DMA TX interrupt cnts = %d\nDMA RX interrupt cnts = %d\n",

+		g_jz_intr->dma_tx_cnt,g_jz_intr->dma_rx_cnt);

+

+	print_msg("dma_tx_err:%d  dma_tx_end:%d\ndma_rx_err:%d  dma_rx_end:%d\n\n",

+		g_jz_intr->dma_tx_err,g_jz_intr->dma_tx_end,g_jz_intr->dma_rx_err,g_jz_intr->dma_rx_end);

+	/* ---------------------------- */

+

+	if(hw->rlen > hw->len)

+		hw->rlen = hw->len;

+

+	return hw->rlen;

+}

+

+static irqreturn_t jz47xx_spi_irq(int irq, void *dev)

+{

+	struct jz47xx_spi *hw = dev;

+	int left_count= hw->len - hw->count;

+	u8 flag = 0,fs;

+	u16 dat;

+	u32 cnt,unit_size = hw->transfer_unit_size;

+	int status;

+	struct jz_intr_cnt *g_jz_intr = hw->g_jz_intr;

+

+	g_jz_intr->ssi_intr_cnt++;

+	/* to avoid die in interrupt if some error occur */

+	if(g_jz_intr->ssi_intr_cnt >MAX_SSI_INTR)

+	{

+		__ssi_disable_tx_intr(hw->chnl);

+		__ssi_disable_rx_intr(hw->chnl);

+		dev_err(hw->dev,"\nERROR:SSI interrupts too many count(%d)!\n",

+			g_jz_intr->ssi_intr_cnt);

+		complete(&hw->done);

+

+		goto irq_done;

+	}

+	

+	if( __ssi_underrun(hw->chnl) &&

+		__ssi_tx_error_intr(hw->chnl)){

+		print_kdbg("UNDR:");

+		g_jz_intr->ssi_eti++;

+		__ssi_disable_tx_error_intr(hw->chnl);

+

+		cnt = g_jz_intr->ssi_rlen;

+		if((hw->rw_mode & RW_MODE) == W_MODE){

+			print_dbg("W_MODE\n");

+			hw->rlen += unit_size*__ssi_get_rxfifo_count(hw->chnl);

+			__ssi_flush_rxfifo(hw->chnl);

+		}else{		

+			while(!__ssi_rxfifo_empty(hw->chnl))

+			{

+				dat = __ssi_receive_data(hw->chnl);

+				hw->get_rx(dat,hw);

+				hw->rlen += unit_size;

+				

+				print_dbg("-%x,",dat);

+				g_jz_intr->ssi_rlen++;

+			}

+		}

+		print_kdbg("-:%d\n",g_jz_intr->ssi_rlen - cnt);

+		if( left_count == 0){

+			__ssi_disable_tx_intr(hw->chnl);

+			__ssi_disable_rx_intr(hw->chnl);

+

+			complete(&hw->done);

+		}else

+			__ssi_enable_tx_error_intr(hw->chnl);

+		

+		flag++;

+

+	}

+	

+	if ( __ssi_txfifo_half_empty_intr(hw->chnl) &&

+		 __ssi_txfifo_half_empty(hw->chnl)) {

+

+		print_kdbg("TXI:");

+		g_jz_intr->ssi_txi++;

+

+		status = fill_txfifo(hw);

+		if(status < 0)

+		{

+			__ssi_disable(hw->chnl);

+			__ssi_disable_tx_intr(hw->chnl);

+			__ssi_disable_rx_intr(hw->chnl);	

+			dev_err(hw->dev,"data filling error!\n");

+			complete(&hw->done);

+			

+			goto irq_done;

+		}

+		

+		fs = REG_SSI_SR(hw->chnl);

+		print_dbg("@VER-%d@UNDR-%d@RFHF-%d@TFHE-%d@\n",(fs>>0)&0x1,(fs>>1)&0x1,(fs>>2)&0x1,(fs>>3)&0x1);

+		

+		flag++;

+	}

+

+	if ( __ssi_rxfifo_half_full(hw->chnl) &&

+		__ssi_rxfifo_half_full_intr(hw->chnl)) {

+		__ssi_disable_rxfifo_half_full_intr(hw->chnl);

+		print_kdbg("RXI:");

+		g_jz_intr->ssi_rxi++;

+		

+		cnt = g_jz_intr->ssi_rlen;

+		if((hw->rw_mode & RW_MODE) == W_MODE){

+			print_dbg("W_MODE\n");

+			hw->rlen += unit_size*__ssi_get_rxfifo_count(hw->chnl);

+			__ssi_flush_rxfifo(hw->chnl);

+		}else{

+			

+			while(!__ssi_rxfifo_empty(hw->chnl))

+			{

+				dat = __ssi_receive_data(hw->chnl);

+				hw->get_rx(dat,hw);

+				hw->rlen += unit_size;

+				

+				print_dbg("-%x,",dat);

+				g_jz_intr->ssi_rlen++;

+			}

+		}

+		print_kdbg("-:%d ",g_jz_intr->ssi_rlen - cnt);

+		

+		flag++;

+	}

+

+	if( __ssi_overrun(hw->chnl) &&

+		__ssi_rx_error_intr(hw->chnl)){

+		print_kdbg(" overrun:");

+		g_jz_intr->ssi_eri++;

+

+		__ssi_disable(hw->chnl);

+

+		cnt = g_jz_intr->ssi_rlen;

+		while(!__ssi_rxfifo_empty(hw->chnl))

+		{

+			dat = __ssi_receive_data(hw->chnl);

+			hw->get_rx(dat,hw);

+			hw->rlen += unit_size;

+			

+			print_dbg("-%x,",dat);

+			g_jz_intr->ssi_rlen++;

+		}

+		print_kdbg("-:%d ",g_jz_intr->ssi_rlen - cnt);

+		__ssi_enable(hw->chnl);

+			

+		flag++;

+	}

+

+	if(!flag)

+	{

+		dev_info(hw->dev,"\nERROR:interrupt Type error\n");

+		complete(&hw->done);

+	}

+	

+ irq_done:

+ 	__ssi_clear_errors(hw->chnl);

+	return IRQ_HANDLED;

+}

+static irqreturn_t spi_dma_tx_irq(int irq, void *dev)

+{

+	struct jz47xx_spi *hw = dev;

+	struct jz_intr_cnt *g_jz_intr = hw->g_jz_intr;

+	int chan = hw->dma_tx_chnl;

+

+	g_jz_intr->dma_tx_cnt++;

+	disable_dma(chan);

+	if (__dmac_channel_address_error_detected(chan)) {

+		printk(KERN_DEBUG "%s: DMAC address error.\n", __FUNCTION__);

+		__dmac_channel_clear_address_error(chan);

+		g_jz_intr->dma_tx_err++;

+		

+		print_kdbg("DMA addr error\n");

+		complete(&hw->done);

+		

+		return IRQ_HANDLED;

+	}

+	if (__dmac_channel_transmit_end_detected(chan)) {

+		__dmac_channel_clear_transmit_end(chan);

+		__ssi_disable_tx_error_intr(hw->chnl); /* disable underrun irq here ??? */

+		g_jz_intr->dma_tx_end++;

+

+		print_kdbg("DMA Write End\n");

+	//	while(__ssi_get_txfifo_count(hw->chnl));

+

+		return IRQ_HANDLED;

+	}

+	

+	print_kdbg("DMA others tx int error\n");

+	

+	return IRQ_HANDLED;

+}

+static irqreturn_t spi_dma_rx_irq(int irq, void *dev)

+{

+	struct jz47xx_spi *hw = dev;

+	struct jz_intr_cnt *g_jz_intr = hw->g_jz_intr;

+	int chan = hw->dma_rx_chnl;

+	u16 dat;

+	

+	g_jz_intr->dma_rx_cnt++;

+	disable_dma(chan);

+	if (__dmac_channel_address_error_detected(chan)) {

+		printk(KERN_DEBUG "%s: DMAC address error.\n", __FUNCTION__);

+		g_jz_intr->dma_rx_err++;

+		__dmac_channel_clear_address_error(chan);

+	//	complete(&hw->done);

+		goto dma_rx_irq_done;

+	}

+	if (__dmac_channel_transmit_end_detected(chan)) {

+		g_jz_intr->dma_rx_end++;

+		__dmac_channel_clear_transmit_end(chan);

+

+		while(!__ssi_rxfifo_empty(hw->chnl))

+		{

+			dat = __ssi_receive_data(hw->chnl);

+			hw->get_rx(dat,hw);

+			

+			print_kdbg("-%x,",dat);

+			g_jz_intr->ssi_rlen++;

+		}

+		hw->rlen += hw->count;

+		print_kdbg("DMA Read End\n");

+		

+		goto dma_rx_irq_done;

+	}

+	print_kdbg("DMA others rx int error\n");

+dma_rx_irq_done:

+	complete(&hw->done);

+	return IRQ_HANDLED;

+}

+static int jz_spi_dma_init(struct jz47xx_spi *hw)

+{

+	

+	if ((hw->dma_tx_chnl= jz_request_dma(DMA_ID_SSI0_TX, "SSI0 Tx DMA", 

+		spi_dma_tx_irq,IRQ_DISABLED, hw)) < 0 ) {

+

+		printk(KERN_ERR "SSI0 Tx DMA request failed!\n");

+		return -EINVAL;

+	}

+	if ((hw->dma_rx_chnl = jz_request_dma(DMA_ID_SSI0_RX, "SSI0 Rx DMA", 

+		spi_dma_rx_irq,IRQ_DISABLED, hw)) < 0 ) {

+

+		printk(KERN_ERR "SSI0 Rx DMA request failed!\n");

+		return -EINVAL;

+	}

+	hw->dma_tx_unit = JZ_SSI_DMA_BURST_LENGTH;

+	hw->dma_rx_unit = JZ_SSI_DMA_BURST_LENGTH;

+

+	return 0;

+}

+int jz_spi_pinconfig(struct jz47xx_spi *hw)

+{

+	u8 f_gpiocs=0,f_spics0=0,f_spics1=0;

+	int i;

+	struct jz47xx_spi_info *pdata = hw->pdata;

+

+	if(pdata->board_size > MAX_SPI_DEVICES)

+	{

+		pdata->board_size = MAX_SPI_DEVICES;

+		dev_info(hw->dev,"SPI devices exceed defined max_num!!!\n");

+	}

+	

+	for(i=0; i< pdata->board_size; i++)

+	{

+		if(pdata->pin_cs[i] == PIN_SSI_CE0){ 

+			if(!hw->chnl)

+				pdata->pin_cs[i] = SSI0_CE0_PIN;

+			else

+				pdata->pin_cs[i] = SSI1_CE0_PIN;

+			f_spics0 = 1;

+		}else if(pdata->pin_cs[i] == PIN_SSI_CE1){ 	

+			if(!hw->chnl)

+				pdata->pin_cs[i] = SSI0_CE1_PIN;

+			else

+				pdata->pin_cs[i] = SSI1_CE1_PIN;

+			f_spics1 = 1;

+		}else									

+			f_gpiocs = 1;

+

+		__gpio_as_output(pdata->pin_cs[i]);

+		

+		print_msg("PIN:0x%04X\n",pdata->pin_cs[i]);

+	}

+	print_msg("f_spics0=%d\nf_spics1=%d\nf_gpiocs=%d\n",f_spics0,f_spics1,f_gpiocs);

+

+	

+	if(pdata->pins_config){			/* if user want to configure by himself */

+		pdata->pins_config();

+		return 0;

+	}

+	

+	if(f_spics0|| f_spics1){		/* spi chipselect for ssi controller internal */

+

+		/* one of two controllers in SOC 

+		 *

+		 * ??? pin_output function  instead of controller internal_chipselect, because ...

+		 *

+		 */

+		if(f_spics1)

+			__ssi_select_ce2(hw->chnl);

+		if(f_spics0)

+			__ssi_select_ce(hw->chnl);

+		

+		GPIO_AS_SSI(hw->chnl);

+

+	}

+	

+	if(f_gpiocs){					/* config SPI_PINs for spi function except for CE0 and CE1 

+	 *

+	 * SPI_PINs: SSI0_CLK, SSI0_DT, SSI0_DR

+	 */

+		

+		GPIO_AS_SSI_EX(hw->chnl);

+	}

+	

+	

+	return 0;

+}

+EXPORT_SYMBOL_GPL(jz_spi_pinconfig);

+	

+static int jz47xx_spi_init_setup(struct jz47xx_spi *hw)

+{

+		

+	/* for the moment,open the SSI clock gate */

+

+	/* disable the SSI controller */

+	__ssi_disable(hw->chnl);

+	

+	CPM_SSI_START(hw->chnl);

+	

+	/* set default half_intr trigger */

+	hw->tx_trigger = SSI_TX_FIFO_THRESHOLD*8;

+	hw->rx_trigger = SSI_RX_FIFO_THRESHOLD*8;

+	__ssi_set_tx_trigger(hw->chnl,hw->tx_trigger);

+	__ssi_set_rx_trigger(hw->chnl,hw->rx_trigger);

+

+	/* First,mask the interrupt, while verify the status ? */

+	__ssi_disable_tx_intr(hw->chnl);

+	__ssi_disable_rx_intr(hw->chnl);

+

+	__ssi_disable_receive(hw->chnl);

+

+	__ssi_set_spi_clock_phase(hw->chnl,0);

+	__ssi_set_spi_clock_polarity(hw->chnl,0);  

+	__ssi_set_msb(hw->chnl);

+	__ssi_spi_format(hw->chnl);

+	__ssi_set_frame_length(hw->chnl,8);

+	__ssi_disable_loopback(hw->chnl);   

+	__ssi_flush_fifo(hw->chnl);

+

+	__ssi_underrun_auto_clear(hw->chnl);

+ 	__ssi_clear_errors(hw->chnl);

+		

+	return 0;

+}

+

+

+static int jz_ssi_clk_setup(struct jz47xx_spi *hw)

+{

+#ifdef CONFIG_SOC_JZ4760

+

+	if(hw->pdata->is_pllclk){

+		__ssi_select_pllclk();

+	}else{

+		__ssi_select_exclk();

+	}

+	__cpm_set_ssidiv(0);

+	hw->src_clk = cpm_get_clock(CGU_SSICLK);

+#else

+	hw->src_clk = __cpm_get_pllout();

+	hw->pdata->is_pllclk = 1;

+#endif

+	

+	return 0;

+}

+

+static int __init jz47xx_spi_probe(struct platform_device *pdev)

+{

+	struct jz47xx_spi *hw;

+	struct spi_master *master;

+	

+	struct resource *res;

+	int err = 0;

+	

+#ifdef CONFIG_JZ_SPI_BOARD_INFO_REGISTER

+	int i;

+	struct spi_board_info *bi;

+#endif

+

+	print_msg("in %s\n",__FUNCTION__);

+	master = spi_alloc_master(&pdev->dev, sizeof(struct jz47xx_spi));

+	if (master == NULL) {

+		dev_err(&pdev->dev, "No memory for spi_master\n");

+		err = -ENOMEM;

+		goto err_nomem;

+	}

+	

+	hw = spi_master_get_devdata(master);

+	memset(hw, 0, sizeof(struct jz47xx_spi));

+

+	hw->g_jz_intr = kzalloc(sizeof(struct jz_intr_cnt),GFP_KERNEL);

+

+	if(hw->g_jz_intr == NULL)

+	{

+		dev_err(&pdev->dev, "No memory for jz_intr_cnt\n");

+		err = -ENOMEM;

+		goto err_nomem;

+	}

+	

+	hw->master = spi_master_get(master);

+	hw->dev = &pdev->dev;

+	

+	hw->pdata = pdev->dev.platform_data;

+	if (hw->pdata == NULL) {

+		dev_err(&pdev->dev, "No platform data supplied\n");

+		err = -ENOENT;

+		goto err_no_pdata;

+	}

+	hw->chnl= hw->pdata->chnl;

+	

+	if(hw->chnl != 0 && hw->chnl != 1){

+		dev_err(&pdev->dev, "No this channel\n");

+		err = -ENOENT;

+		goto err_no_pdata;

+	}

+	

+	platform_set_drvdata(pdev, hw);

+	init_completion(&hw->done);

+

+	/* setup the state for the bitbang driver */

+

+	hw->bitbang.master         = hw->master;

+	hw->bitbang.setup_transfer = jz47xx_spi_setupxfer;

+	hw->bitbang.chipselect     = jz47xx_spi_chipsel;

+	hw->bitbang.txrx_bufs      = jz47xx_spi_txrx;

+	hw->bitbang.master->setup  = jz47xx_spi_setup;

+

+	dev_dbg(hw->dev, "bitbang at %p\n", &hw->bitbang);

+

+	/* find and map our resources */

+

+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);

+	if (res == NULL) {

+		dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");

+		err = -ENOENT;

+		goto err_no_iores;

+	}

+	hw->ioarea = request_mem_region(res->start, (res->end - res->start)+1,

+					pdev->name);

+

+	if (hw->ioarea == NULL) {

+		dev_err(&pdev->dev, "Cannot reserve region\n");

+		err = -ENXIO;

+		goto err_no_iores;

+	}

+	hw->regs = ioremap(res->start, (res->end - res->start)+1);

+	if (hw->regs == NULL) {

+		dev_err(&pdev->dev, "Cannot map IO\n");

+		err = -ENXIO;

+		goto err_no_iomap;

+	}

+	hw->irq = platform_get_irq(pdev, 0);

+	if (hw->irq < 0) {

+		dev_err(&pdev->dev, "No IRQ specified\n");

+		err = -ENOENT;

+		goto err_no_irq;

+	}

+	

+	/* request DMA irq */

+	err =jz_spi_dma_init(hw);

+	if(err)

+		goto err_no_irq;

+	

+	/* request SSI irq */

+	err = request_irq(hw->irq, jz47xx_spi_irq, 0, pdev->name, hw);

+	if (err) {

+		dev_err(&pdev->dev, "Cannot claim IRQ\n");

+		goto err_no_irq;

+	}

+	

+	/* get controller associated params */

+	master->bus_num = hw->pdata->bus_num;

+	master->num_chipselect = hw->pdata->board_size;

+

+

+	/* setup chipselect */

+	if (hw->pdata->set_cs)

+		hw->set_cs = hw->pdata->set_cs; 

+	else

+		hw->set_cs = jz47xx_spi_cs;

+

+	/* SPI_PINs and chipselect configure */

+	jz_spi_pinconfig(hw);

+	/* SSI controller clock configure */

+	jz_ssi_clk_setup(hw);

+	/* SSI controller initializations for SPI */

+	jz47xx_spi_init_setup(hw);

+	

+	/* register our spi controller */

+	err = spi_bitbang_start(&hw->bitbang);

+	if (err) {

+		dev_err(&pdev->dev, "Failed to register SPI master ERR_NO:%d\n",err);

+		goto err_register;

+	}

+

+#ifdef CONFIG_JZ_SPI_BOARD_INFO_REGISTER	

+	/* register all the devices associated */

+	bi = &hw->pdata->board_info[0];

+	if(bi){

+		for (i = 0; i < hw->pdata->board_size; i++, bi++) {

+			dev_info(hw->dev, "registering %s\n", bi->modalias);

+

+			bi->controller_data = hw;

+			spi_new_device(master, bi);

+		}

+	}

+#endif

+

+	printk(KERN_INFO

+	       "JZ47xx SSI Controller for SPI channel %d driver\n",hw->chnl);

+	

+	return 0;

+

+ err_register:

+	CPM_SSI_STOP(hw->chnl);

+

+	free_irq(hw->irq, hw);

+

+ err_no_irq:

+	iounmap(hw->regs);

+

+ err_no_iomap:

+	release_resource(hw->ioarea);

+	kfree(hw->ioarea);

+

+ err_no_iores:

+ err_no_pdata:

+	spi_master_put(hw->master);;

+

+ err_nomem:

+	return err;

+}

+

+static int __exit jz47xx_spi_remove(struct platform_device *dev)

+{

+	struct jz47xx_spi *hw = platform_get_drvdata(dev);

+

+	CPM_SSI_STOP(hw->chnl);

+	__ssi_disable_tx_intr(hw->chnl);

+	__ssi_disable_rx_intr(hw->chnl);

+	__ssi_disable(hw->chnl);

+	

+	platform_set_drvdata(dev, NULL);

+

+	spi_unregister_master(hw->master);

+

+	

+

+	free_irq(hw->irq, hw);

+	iounmap(hw->regs);

+

+	release_resource(hw->ioarea);

+	kfree(hw->ioarea);

+

+	spi_master_put(hw->master);

+

+	/* release DMA channel */

+	if (hw->dma_rx_chnl >= 0) {

+		jz_free_dma(hw->dma_rx_chnl);

+		printk("dma_rx_chnl release\n");

+	}

+	if (hw->dma_tx_chnl >= 0) {

+		jz_free_dma(hw->dma_tx_chnl);

+		printk("dma_tx_chnl release\n");

+	}

+

+	kfree(hw->g_jz_intr);

+	kfree(hw);

+	

+	return 0;

+}

+#ifdef CONFIG_PM

+

+static int jz47xx_spi_suspend(struct platform_device *pdev, pm_message_t msg)

+{

+	struct jz47xx_spi *hw = platform_get_drvdata(pdev);

+

+	CPM_SSI_STOP(hw->chnl);

+

+	return 0;

+}

+

+static int jz47xx_spi_resume(struct platform_device *pdev)

+{

+	struct jz47xx_spi *hw = platform_get_drvdata(pdev);

+

+	CPM_SSI_START(hw->chnl);

+

+	return 0;

+}

+

+#else

+#define jz47xx_spi_suspend NULL

+#define jz47xx_spi_resume  NULL

+#endif

+

+MODULE_ALIAS("jz47xx_spi");			/* for platform bus hotplug */

+static struct platform_driver jz47xx_spidrv = {

+	.remove		= __exit_p(jz47xx_spi_remove),

+	.suspend	= jz47xx_spi_suspend,

+	.resume		= jz47xx_spi_resume,

+	.driver		= {

+		.name	= "jz47xx-spi0",

+		.owner	= THIS_MODULE,

+	},

+};

+static int __init jz47xx_spi_init(void)

+{

+        return platform_driver_probe(&jz47xx_spidrv, jz47xx_spi_probe);

+}

+

+static void __exit jz47xx_spi_exit(void)

+{

+        platform_driver_unregister(&jz47xx_spidrv);

+

+}

+module_init(jz47xx_spi_init);

+module_exit(jz47xx_spi_exit);

+

+MODULE_DESCRIPTION("JZ47XX SPI Driver");

+MODULE_LICENSE("GPL");

+

diff --git a/drivers/usb/core/hub.c b/drivers/usb/core/hub.c
index 01e5f04a422..747575f1585 100644
--- a/drivers/usb/core/hub.c
+++ b/drivers/usb/core/hub.c
@@ -102,7 +102,7 @@ static inline int jz_usb_hub_workaround(struct usb_hub *hub, int port1)
 	}
 #endif
 
-#if defined(CONFIG_SOC_JZ4740) || defined(CONFIG_SOC_JZ4750) || defined(CONFIG_SOC_JZ4750D)
+#if defined(CONFIG_SOC_JZ4740) || defined(CONFIG_SOC_JZ4750) || defined(CONFIG_SOC_JZ4750D) || defined(CONFIG_SOC_JZ4810)
 	/*
 	 * On Jz4740 and Jz4750, the second USB port was used as device.
 	 */
diff --git a/drivers/usb/gadget/jz4740_udc.c b/drivers/usb/gadget/jz4740_udc.c
index ccc989a6e90..887669a4610 100644
--- a/drivers/usb/gadget/jz4740_udc.c
+++ b/drivers/usb/gadget/jz4740_udc.c
@@ -29,6 +29,7 @@
 #include <linux/init.h>
 #include <linux/list.h>
 #include <linux/interrupt.h>
+#include <linux/timer.h>
 #include <linux/proc_fs.h>
 #include <linux/usb.h>
 #include <linux/usb/gadget.h>
@@ -66,6 +67,7 @@ static unsigned int use_dma = 1;   /* 1: use DMA, 0: use PIO */
 module_param(use_dma, int, 0);
 MODULE_PARM_DESC(use_dma, "DMA mode enable flag");
 
+
 /*
  *  Local definintions.
  */
@@ -91,6 +93,22 @@ static char *state_names[] = {
 };
 #endif
 
+//#define TEST_ON_WIN7
+#ifdef TEST_ON_WIN7
+/* used for WIN7 OR VISTA TEST */
+static unsigned int out_flag = 0;
+struct timer_list irq_timer;
+static void irq_timer_func(unsigned long data)
+{
+
+	if (out_flag) {
+		out_flag = 0;
+		printk(" PC removed???.\n");
+	}
+}
+#endif
+
+
 /*
  * Local declarations.
  */
@@ -141,6 +159,7 @@ static struct usb_ep_ops jz4740_ep_ops = {
 	.fifo_flush	= jz4740_fifo_flush,
 };
 
+
 /*-------------------------------------------------------------------------*/
 
 /* inline functions of register read/write/set/clear  */
@@ -248,6 +267,7 @@ static __inline__ int read_packet(struct jz4740_ep *ep,
 	u8 *buf;
 	int length, nlong, nbyte;
 	volatile u32 *fifo = (volatile u32 *)ep->fifo;
+	char *tmp = req->req.buf;
 
 	buf = req->req.buf + req->req.actual;
 	prefetchw(buf);
@@ -268,6 +288,10 @@ static __inline__ int read_packet(struct jz4740_ep *ep,
 		*buf++ = *((volatile u8 *)fifo);
 	}
 
+#ifdef  TEST_ON_WIN7
+	if (tmp[15] == 0x35)
+		out_flag = 1;
+#endif
 	return length;
 }
 
@@ -387,6 +411,8 @@ static void udc_enable(struct jz4740_udc *dev)
 	 * transistor on and pull the USBDP pin HIGH.
 	 */
 	usb_setb(USB_REG_POWER, USB_POWER_SOFTCONN);
+
+	
 }
 
 /*-------------------------------------------------------------------------*/
@@ -2075,6 +2101,10 @@ static irqreturn_t jz4740_udc_irq(int irq, void *_dev)
 	/* Check for Bulk-OUT DMA interrupt */
 	if (intr_dma & 0x2) {
 		int ep_num;
+#ifdef TEST_ON_WIN7
+		if (out_flag)
+			out_flag = 0;
+#endif
 		ep_num = (usb_readl(USB_REG_CNTL2) >> 4) & 0xf;
 		jz4740_out_epn(dev, ep_num, intr_out);
 	}
@@ -2110,6 +2140,11 @@ static irqreturn_t jz4740_udc_irq(int irq, void *_dev)
 #endif
 
 	spin_unlock(&dev->lock);
+
+#ifdef	TEST_ON_WIN7
+	if (out_flag == 1)
+		mod_timer(&irq_timer, 400+jiffies);
+#endif
 	return IRQ_HANDLED;
 }
 
@@ -2228,6 +2263,10 @@ static int jz4740_udc_probe(struct platform_device *pdev)
 
 	DEBUG("%s\n", __FUNCTION__);
 
+#ifdef 	TEST_ON_WIN7
+	setup_timer(&irq_timer, irq_timer_func, 0);
+#endif
+
 	spin_lock_init(&dev->lock);
 	the_controller = dev;
 
@@ -2316,6 +2355,9 @@ static void __exit udc_exit (void)
 {
 	platform_driver_unregister(&udc_driver);
 	platform_device_unregister(&the_udc_pdev);
+#ifdef TEST_ON_WIN7
+	del_timer(&irq_timer);
+#endif
 }
 
 module_init(udc_init);
diff --git a/drivers/usb/host/ohci-jz.c b/drivers/usb/host/ohci-jz.c
index 4391f7514b0..78708652820 100644
--- a/drivers/usb/host/ohci-jz.c
+++ b/drivers/usb/host/ohci-jz.c
@@ -29,7 +29,21 @@ extern int usb_disabled(void);
 
 /*-------------------------------------------------------------------------*/
 /* FIXME: when port 2.6.29's cpm to jz4750, remove me!!! */
-#ifdef CONFIG_SOC_JZ4760
+#ifdef CONFIG_SOC_JZ4810
+static void jz_start_ohc(struct platform_device *dev)
+{
+	/* the clock is support by the EXTRAL */
+
+	__cpm_enable_uhc_phy();
+}
+	
+static void jz_stop_ohc(struct platform_device *dev)
+{
+	__cpm_suspend_uhc_phy();
+}
+#else
+
+#if defined(CONFIG_SOC_JZ4760) || defined(CONFIG_SOC_JZ4760B)
 static void jz_start_ohc(struct platform_device *dev)
 {
 	printk(KERN_DEBUG __FILE__
@@ -88,6 +102,8 @@ static void jz_stop_ohc(struct platform_device *dev)
 }
 #endif	/* CONFIG_SOC_JZ4760 */
 
+#endif
+
 /*-------------------------------------------------------------------------*/
 
 /* configure so an HC device and id are always provided */
diff --git a/drivers/usb/musb/Kconfig b/drivers/usb/musb/Kconfig
index bfc1c06240c..1fcc0e49546 100644
--- a/drivers/usb/musb/Kconfig
+++ b/drivers/usb/musb/Kconfig
@@ -41,7 +41,7 @@ config USB_MUSB_SOC
 	default y if ARCH_OMAP34XX
 	default y if (BF54x && !BF544)
 	default y if (BF52x && !BF522 && !BF523)
-	default y if (SOC_JZ4760)
+	default y if (SOC_JZ4760 || SOC_JZ4760B)
 
 comment "DaVinci 35x and 644x USB support"
 	depends on USB_MUSB_HDRC && ARCH_DAVINCI
@@ -56,7 +56,7 @@ comment "Blackfin high speed USB Support"
 	depends on USB_MUSB_HDRC && ((BF54x && !BF544) || (BF52x && !BF522 && !BF523))
 
 comment "Ingenic OTG USB support"
-	depends on USB_MUSB_HDRC && SOC_JZ4760
+	depends on USB_MUSB_HDRC && (SOC_JZ4760 || SOC_JZ4760B)
 
 config USB_TUSB6010
 	boolean "TUSB 6010 support"
@@ -127,7 +127,7 @@ config USB_MUSB_OTG
 endchoice
 config USB_MUSB_PERIPHERAL_HOTPLUG
         bool "Support Ingenic USB Device Controller Hotplug"
-        depends on SOC_JZ4760 && USB_GADGET_MUSB_HDRC
+        depends on (SOC_JZ4760 || SOC_JZ4760B) && USB_GADGET_MUSB_HDRC
 
 # enable peripheral support (including with OTG)
 config USB_GADGET_MUSB_HDRC
@@ -161,7 +161,7 @@ config MUSB_PIO_ONLY
 config USB_INVENTRA_DMA
 	bool
 	depends on USB_MUSB_HDRC && !MUSB_PIO_ONLY
-	default ARCH_OMAP2430 || ARCH_OMAP34XX || BLACKFIN || SOC_JZ4760
+	default ARCH_OMAP2430 || ARCH_OMAP34XX || BLACKFIN || SOC_JZ4760 || SOC_JZ4760B
 	help
 	  Enable DMA transfers using Mentor's engine.
 
diff --git a/drivers/usb/musb/Makefile b/drivers/usb/musb/Makefile
index 30789ae9076..f16b9b3a20f 100644
--- a/drivers/usb/musb/Makefile
+++ b/drivers/usb/musb/Makefile
@@ -10,6 +10,10 @@ ifeq ($(CONFIG_SOC_JZ4760),y)
 	musb_hdrc-objs	+= jz4760.o
 endif
 
+ifeq ($(CONFIG_SOC_JZ4760B),y)
+	musb_hdrc-objs	+= jz4760.o
+endif
+
 ifeq ($(CONFIG_ARCH_DAVINCI),y)
 	musb_hdrc-objs	+= davinci.o
 endif
diff --git a/drivers/usb/musb/jz4760.c b/drivers/usb/musb/jz4760.c
index a45e873742c..01437599683 100644
--- a/drivers/usb/musb/jz4760.c
+++ b/drivers/usb/musb/jz4760.c
@@ -162,13 +162,17 @@ static void jz_musb_set_vbus(struct musb *musb, int is_on)
 
 #define __GPIO(p, n) (32 * (p - 'A') + n)
 
-#ifdef CONFIG_JZ4760_CYGNUS
+#if defined(CONFIG_JZ4760_CYGNUS) || defined(CONFIG_JZ4760B_CYGNUS)
 #define GPIO_OTG_ID_PIN		__GPIO('F', 3)
-#elif CONFIG_JZ4760_LEPUS
+#elif defined (CONFIG_JZ4760_LEPUS) || defined (CONFIG_JZ4760B_LEPUS)
 #define GPIO_OTG_ID_PIN		__GPIO('E', 2)
 #endif
 
+#ifndef CONFIG_JZ4760_HTB80
 #define OTG_HOTPLUG_PIN         __GPIO('E', 19)
+#else
+#define OTG_HOTPLUG_PIN         __GPIO('E', 0)
+#endif
 #define GPIO_OTG_ID_IRQ		(IRQ_GPIO_0 + GPIO_OTG_ID_PIN)
 #define GPIO_OTG_STABLE_JIFFIES 10
 
@@ -197,7 +201,11 @@ static unsigned int read_gpio_pin(unsigned int pin, unsigned int loop)
 static void do_otg_id_pin_state(struct musb *musb)
 {
 	unsigned int default_a;
+#ifndef CONFIG_JZ4760_HTB80
 	unsigned int pin = read_gpio_pin(GPIO_OTG_ID_PIN, 5000);
+#else
+	unsigned int pin = 1; /* always B */
+#endif
 
 	default_a = !pin;
 
@@ -210,14 +218,18 @@ static void do_otg_id_pin_state(struct musb *musb)
 #ifdef CONFIG_USB_MUSB_PERIPHERAL_HOTPLUG
 			__gpio_unmask_irq(OTG_HOTPLUG_PIN);
 #endif
+#ifndef CONFIG_JZ4760_HTB80
 			__gpio_as_irq_fall_edge(GPIO_OTG_ID_PIN);
+#endif
 	} else {
 		/* A */
 		if (is_otg_enabled(musb)) {
 #ifdef CONFIG_USB_MUSB_PERIPHERAL_HOTPLUG
 			__gpio_mask_irq(OTG_HOTPLUG_PIN); // otg's host mode not support hotplug
 #endif
+#ifndef CONFIG_JZ4760_HTB80
 			__gpio_as_irq_rise_edge(GPIO_OTG_ID_PIN);
+#endif
 		}
 	}
 
@@ -246,7 +258,7 @@ static int otg_id_pin_setup(struct musb *musb)
 
 	/* Update OTG ID PIN state. */
 	do_otg_id_pin_state(musb);
-
+#ifndef CONFIG_JZ4760_HTB80
 	setup_timer(&otg_id_pin_stable_timer, otg_id_pin_stable_func, (unsigned long)musb);
 
 	rv = request_irq(GPIO_OTG_ID_IRQ, jz_musb_otg_id_irq,
@@ -255,14 +267,17 @@ static int otg_id_pin_setup(struct musb *musb)
 		pr_err("Failed to request OTG_ID_IRQ.\n");
 		return rv;
 	}
+#endif
 
 	return rv;
 }
 
 static void otg_id_pin_cleanup(struct musb *musb)
 {
+#ifndef CONFIG_JZ4760_HTB80
 	free_irq(GPIO_OTG_ID_IRQ, "otg-id-irq");
 	del_timer(&otg_id_pin_stable_timer);
+#endif
 
 	return;
 }
diff --git a/drivers/usb/musb/musb_core.c b/drivers/usb/musb/musb_core.c
index 51c64ff157a..3cfe035e2cd 100644
--- a/drivers/usb/musb/musb_core.c
+++ b/drivers/usb/musb/musb_core.c
@@ -135,6 +135,18 @@ MODULE_LICENSE("GPL");
 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
 
 
+#ifdef TEST_ON_WIN7
+unsigned long out_flag = 0;
+struct timer_list monitor_remove_timer;
+static void monitor_timer_func(unsigned long data)
+{
+	if (out_flag) {
+		out_flag = 0;
+		printk("TO BE REMOVED???.\n");
+	}
+}
+#endif
+
 /*-------------------------------------------------------------------------*/
 
 static inline struct musb *dev_to_musb(struct device *dev)
@@ -149,6 +161,7 @@ static inline struct musb *dev_to_musb(struct device *dev)
 
 /*-------------------------------------------------------------------------*/
 
+
 #if !defined(CONFIG_USB_TUSB6010) && !defined(CONFIG_BLACKFIN)
 
 /*
@@ -191,6 +204,7 @@ void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
 	}
 }
 
+#if !defined(CONFIG_USB_MUSB_AM35X)
 /*
  * Unload an endpoint's FIFO
  */
@@ -228,6 +242,7 @@ void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
 		readsb(fifo, dst, len);
 	}
 }
+#endif
 
 #endif	/* normal PIO */
 
@@ -353,8 +368,7 @@ void musb_hnp_stop(struct musb *musb)
 	 * which cause occasional OPT A "Did not receive reset after connect"
 	 * errors.
 	 */
-	musb->port1_status &=
-		~(1 << USB_PORT_FEAT_C_CONNECTION);
+	musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
 }
 
 #endif
@@ -371,15 +385,10 @@ void musb_hnp_stop(struct musb *musb)
  * @param power
  */
 
-#define STAGE0_MASK (MUSB_INTR_RESUME | MUSB_INTR_SESSREQ \
-		| MUSB_INTR_VBUSERROR | MUSB_INTR_CONNECT \
-		| MUSB_INTR_RESET)
-
 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
 				u8 devctl, u8 power)
 {
 	irqreturn_t handled = IRQ_NONE;
-	void __iomem *mbase = musb->mregs;
 
 	DBG(3, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl,
 		int_usb);
@@ -394,6 +403,8 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
 
 		if (devctl & MUSB_DEVCTL_HM) {
 #ifdef CONFIG_USB_MUSB_HDRC_HCD
+			void __iomem *mbase = musb->mregs;
+
 			switch (musb->xceiv->state) {
 			case OTG_STATE_A_SUSPEND:
 				/* remote wakeup?  later, GetPortStatus
@@ -471,6 +482,14 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
 #ifdef CONFIG_USB_MUSB_HDRC_HCD
 	/* see manual for the order of the tests */
 	if (int_usb & MUSB_INTR_SESSREQ) {
+		void __iomem *mbase = musb->mregs;
+
+		if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
+				&& (devctl & MUSB_DEVCTL_BDEVICE)) {
+			DBG(3, "SessReq while on B state\n");
+			return IRQ_HANDLED;
+		}
+
 		DBG(1, "SESSION_REQUEST (%s)\n", otg_state_string(musb));
 
 		/* IRQ arrives from ID pin sense or (later, if VBUS power
@@ -519,14 +538,16 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
 		case OTG_STATE_A_WAIT_BCON:
 		case OTG_STATE_A_WAIT_VRISE:
 			if (musb->vbuserr_retry) {
+				void __iomem *mbase = musb->mregs;
+
 				musb->vbuserr_retry--;
 				ignore = 1;
 				devctl |= MUSB_DEVCTL_SESSION;
 				musb_writeb(mbase, MUSB_DEVCTL, devctl);
 			} else {
 				musb->port1_status |=
-					  (1 << USB_PORT_FEAT_OVER_CURRENT)
-					| (1 << USB_PORT_FEAT_C_OVER_CURRENT);
+					  USB_PORT_STAT_OVERCURRENT
+					| (USB_PORT_STAT_C_OVERCURRENT << 16);
 			}
 			break;
 		default:
@@ -557,6 +578,70 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
 		handled = IRQ_HANDLED;
 	}
 
+#endif
+	if (int_usb & MUSB_INTR_SUSPEND) {
+		DBG(1, "SUSPEND (%s) devctl %02x power %02x\n",
+				otg_state_string(musb), devctl, power);
+		handled = IRQ_HANDLED;
+
+		switch (musb->xceiv->state) {
+#ifdef	CONFIG_USB_MUSB_OTG
+		case OTG_STATE_A_PERIPHERAL:
+			/* We also come here if the cable is removed, since
+			 * this silicon doesn't report ID-no-longer-grounded.
+			 *
+			 * We depend on T(a_wait_bcon) to shut us down, and
+			 * hope users don't do anything dicey during this
+			 * undesired detour through A_WAIT_BCON.
+			 */
+			musb_hnp_stop(musb);
+			usb_hcd_resume_root_hub(musb_to_hcd(musb));
+			musb_root_disconnect(musb);
+			musb_platform_try_idle(musb, jiffies
+					+ msecs_to_jiffies(musb->a_wait_bcon
+						? : OTG_TIME_A_WAIT_BCON));
+
+			break;
+#endif
+		case OTG_STATE_B_IDLE:
+			if (!musb->is_active)
+				break;
+		case OTG_STATE_B_PERIPHERAL:
+			musb_g_suspend(musb);
+			musb->is_active = is_otg_enabled(musb)
+					&& musb->xceiv->gadget->b_hnp_enable;
+			if (musb->is_active) {
+#ifdef	CONFIG_USB_MUSB_OTG
+				musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
+				DBG(1, "HNP: Setting timer for b_ase0_brst\n");
+				mod_timer(&musb->otg_timer, jiffies
+					+ msecs_to_jiffies(
+							OTG_TIME_B_ASE0_BRST));
+#endif
+			}
+			break;
+		case OTG_STATE_A_WAIT_BCON:
+			if (musb->a_wait_bcon != 0)
+				musb_platform_try_idle(musb, jiffies
+					+ msecs_to_jiffies(musb->a_wait_bcon));
+			break;
+		case OTG_STATE_A_HOST:
+			musb->xceiv->state = OTG_STATE_A_SUSPEND;
+			musb->is_active = is_otg_enabled(musb)
+					&& musb->xceiv->host->b_hnp_enable;
+			break;
+		case OTG_STATE_B_HOST:
+			/* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
+			DBG(1, "REVISIT: SUSPEND as B_HOST\n");
+			break;
+		default:
+			/* "should not happen" */
+			musb->is_active = 0;
+			break;
+		}
+	}
+
+#ifdef CONFIG_USB_MUSB_HDRC_HCD
 	if (int_usb & MUSB_INTR_CONNECT) {
 		struct usb_hcd *hcd = musb_to_hcd(musb);
 
@@ -571,9 +656,9 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
 		if (is_peripheral_active(musb)) {
 			/* REVISIT HNP; just force disconnect */
 		}
-		musb_writew(mbase, MUSB_INTRTXE, musb->epmask);
-		musb_writew(mbase, MUSB_INTRRXE, musb->epmask & 0xfffe);
-		musb_writeb(mbase, MUSB_INTRUSBE, 0xf7);
+		musb_writew(musb->mregs, MUSB_INTRTXE, musb->epmask);
+		musb_writew(musb->mregs, MUSB_INTRRXE, musb->epmask & 0xfffe);
+		musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
 #endif
 		musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
 					|USB_PORT_STAT_HIGH_SPEED
@@ -625,10 +710,61 @@ b_host:
 	}
 #endif	/* CONFIG_USB_MUSB_HDRC_HCD */
 
+	if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) {
+		DBG(1, "DISCONNECT (%s) as %s, devctl %02x\n",
+				otg_state_string(musb),
+				MUSB_MODE(musb), devctl);
+		handled = IRQ_HANDLED;
+
+		switch (musb->xceiv->state) {
+#ifdef CONFIG_USB_MUSB_HDRC_HCD
+		case OTG_STATE_A_HOST:
+		case OTG_STATE_A_SUSPEND:
+			usb_hcd_resume_root_hub(musb_to_hcd(musb));
+			musb_root_disconnect(musb);
+			if (musb->a_wait_bcon != 0 && is_otg_enabled(musb))
+				musb_platform_try_idle(musb, jiffies
+					+ msecs_to_jiffies(musb->a_wait_bcon));
+			break;
+#endif	/* HOST */
+#ifdef CONFIG_USB_MUSB_OTG
+		case OTG_STATE_B_HOST:
+			/* REVISIT this behaves for "real disconnect"
+			 * cases; make sure the other transitions from
+			 * from B_HOST act right too.  The B_HOST code
+			 * in hnp_stop() is currently not used...
+			 */
+			musb_root_disconnect(musb);
+			musb_to_hcd(musb)->self.is_b_host = 0;
+			musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
+			MUSB_DEV_MODE(musb);
+			musb_g_disconnect(musb);
+			break;
+		case OTG_STATE_A_PERIPHERAL:
+			musb_hnp_stop(musb);
+			musb_root_disconnect(musb);
+			/* FALLTHROUGH */
+		case OTG_STATE_B_WAIT_ACON:
+			/* FALLTHROUGH */
+#endif	/* OTG */
+#ifdef CONFIG_USB_GADGET_MUSB_HDRC
+		case OTG_STATE_B_PERIPHERAL:
+		case OTG_STATE_B_IDLE:
+			musb_g_disconnect(musb);
+			break;
+#endif	/* GADGET */
+		default:
+			WARNING("unhandled DISCONNECT transition (%s)\n",
+				otg_state_string(musb));
+			break;
+		}
+	}
+
 	/* mentor saves a bit: bus reset and babble share the same irq.
 	 * only host sees babble; only peripheral sees bus reset.
 	 */
 	if (int_usb & MUSB_INTR_RESET) {
+		handled = IRQ_HANDLED;
 		if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) {
 			/*
 			 * Looks like non-HS BABBLE can be ignored, but
@@ -641,7 +777,7 @@ b_host:
 				DBG(1, "BABBLE devctl: %02x\n", devctl);
 			else {
 				ERR("Stopping host session -- babble\n");
-				musb_writeb(mbase, MUSB_DEVCTL, 0);
+				musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
 			}
 		} else if (is_peripheral_capable()) {
 			DBG(1, "BUS RESET as %s\n", otg_state_string(musb));
@@ -686,29 +822,7 @@ b_host:
 					otg_state_string(musb));
 			}
 		}
-
-		handled = IRQ_HANDLED;
 	}
-	schedule_work(&musb->irq_work);
-
-	return handled;
-}
-
-/*
- * Interrupt Service Routine to record USB "global" interrupts.
- * Since these do not happen often and signify things of
- * paramount importance, it seems OK to check them individually;
- * the order of the tests is specified in the manual
- *
- * @param musb instance pointer
- * @param int_usb register contents
- * @param devctl
- * @param power
- */
-static irqreturn_t musb_stage2_irq(struct musb *musb, u8 int_usb,
-				u8 devctl, u8 power)
-{
-	irqreturn_t handled = IRQ_NONE;
 
 #if 0
 /* REVISIT ... this would be for multiplexing periodic endpoints, or
@@ -755,117 +869,7 @@ static irqreturn_t musb_stage2_irq(struct musb *musb, u8 int_usb,
 	}
 #endif
 
-	if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) {
-		DBG(1, "DISCONNECT (%s) as %s, devctl %02x\n",
-				otg_state_string(musb),
-				MUSB_MODE(musb), devctl);
-		handled = IRQ_HANDLED;
-
-		switch (musb->xceiv->state) {
-#ifdef CONFIG_USB_MUSB_HDRC_HCD
-		case OTG_STATE_A_HOST:
-		case OTG_STATE_A_SUSPEND:
-			usb_hcd_resume_root_hub(musb_to_hcd(musb));
-			musb_root_disconnect(musb);
-			if (musb->a_wait_bcon != 0 && is_otg_enabled(musb))
-				musb_platform_try_idle(musb, jiffies
-					+ msecs_to_jiffies(musb->a_wait_bcon));
-			break;
-#endif	/* HOST */
-#ifdef CONFIG_USB_MUSB_OTG
-		case OTG_STATE_B_HOST:
-			/* REVISIT this behaves for "real disconnect"
-			 * cases; make sure the other transitions from
-			 * from B_HOST act right too.  The B_HOST code
-			 * in hnp_stop() is currently not used...
-			 */
-			musb_root_disconnect(musb);
-			musb_to_hcd(musb)->self.is_b_host = 0;
-			musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
-			MUSB_DEV_MODE(musb);
-			musb_g_disconnect(musb);
-			break;
-		case OTG_STATE_A_PERIPHERAL:
-			musb_hnp_stop(musb);
-			musb_root_disconnect(musb);
-			/* FALLTHROUGH */
-		case OTG_STATE_B_WAIT_ACON:
-			/* FALLTHROUGH */
-#endif	/* OTG */
-#ifdef CONFIG_USB_GADGET_MUSB_HDRC
-		case OTG_STATE_B_PERIPHERAL:
-		case OTG_STATE_B_IDLE:
-			musb_g_disconnect(musb);
-			break;
-#endif	/* GADGET */
-		default:
-			WARNING("unhandled DISCONNECT transition (%s)\n",
-				otg_state_string(musb));
-			break;
-		}
-
-		schedule_work(&musb->irq_work);
-	}
-
-	if (int_usb & MUSB_INTR_SUSPEND) {
-		DBG(1, "SUSPEND (%s) devctl %02x power %02x\n",
-				otg_state_string(musb), devctl, power);
-		handled = IRQ_HANDLED;
-
-		switch (musb->xceiv->state) {
-#ifdef	CONFIG_USB_MUSB_OTG
-		case OTG_STATE_A_PERIPHERAL:
-			/* We also come here if the cable is removed, since
-			 * this silicon doesn't report ID-no-longer-grounded.
-			 *
-			 * We depend on T(a_wait_bcon) to shut us down, and
-			 * hope users don't do anything dicey during this
-			 * undesired detour through A_WAIT_BCON.
-			 */
-			musb_hnp_stop(musb);
-			usb_hcd_resume_root_hub(musb_to_hcd(musb));
-			musb_root_disconnect(musb);
-			musb_platform_try_idle(musb, jiffies
-					+ msecs_to_jiffies(musb->a_wait_bcon
-						? : OTG_TIME_A_WAIT_BCON));
-			break;
-#endif
-		case OTG_STATE_B_PERIPHERAL:
-			musb_g_suspend(musb);
-			musb->is_active = is_otg_enabled(musb)
-					&& musb->xceiv->gadget->b_hnp_enable;
-			if (musb->is_active) {
-#ifdef	CONFIG_USB_MUSB_OTG
-				musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
-				DBG(1, "HNP: Setting timer for b_ase0_brst\n");
-				mod_timer(&musb->otg_timer, jiffies
-					+ msecs_to_jiffies(
-							OTG_TIME_B_ASE0_BRST));
-#endif
-			}
-			break;
-		case OTG_STATE_A_WAIT_BCON:
-			if (musb->a_wait_bcon != 0)
-				musb_platform_try_idle(musb, jiffies
-					+ msecs_to_jiffies(musb->a_wait_bcon));
-			break;
-		case OTG_STATE_A_HOST:
-			musb->xceiv->state = OTG_STATE_A_SUSPEND;
-			musb->is_active = is_otg_enabled(musb)
-					&& musb->xceiv->host->b_hnp_enable;
-			break;
-		case OTG_STATE_B_HOST:
-			/* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
-			DBG(1, "REVISIT: SUSPEND as B_HOST\n");
-			break;
-		default:
-			/* "should not happen" */
-			musb->is_active = 0;
-			break;
-		}
-		schedule_work(&musb->irq_work);
-	}
-
+	schedule_work(&musb->irq_work);
 
 	return handled;
 }
@@ -977,15 +981,13 @@ static void musb_shutdown(struct platform_device *pdev)
 	spin_lock_irqsave(&musb->lock, flags);
 	musb_platform_disable(musb);
 	musb_generic_disable(musb);
-
-#ifdef HAVE_CLK
-	if (musb->clock) {
+#ifndef CONFIG_JZSOC
+	if (musb->clock)
 		clk_put(musb->clock);
-		musb->clock = NULL;
-	}
 #endif
 	spin_unlock_irqrestore(&musb->lock, flags);
 
+
 	/* FIXME power down */
 }
 
@@ -1003,7 +1005,8 @@ static void musb_shutdown(struct platform_device *pdev)
  * more than selecting one of a bunch of predefined configurations.
  */
 #if defined(CONFIG_USB_TUSB6010) || \
-	defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX)
+	defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) \
+	|| defined(CONFIG_ARCH_OMAP4)
 static ushort __initdata fifo_mode = 4;
 #else
 static ushort __initdata fifo_mode = 2;
@@ -1013,7 +1016,6 @@ static ushort __initdata fifo_mode = 2;
 module_param(fifo_mode, ushort, 0);
 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
 
-
 enum fifo_style { FIFO_RXTX, FIFO_TX, FIFO_RX } __attribute__ ((packed));
 enum buf_mode { BUF_SINGLE, BUF_DOUBLE } __attribute__ ((packed));
 
@@ -1189,6 +1191,7 @@ static int __init ep_config_from_table(struct musb *musb)
 	int			offset;
 	struct musb_hw_ep	*hw_ep = musb->endpoints;
 
+
 	switch (fifo_mode) {
 	default:
 		fifo_mode = 0;
@@ -1317,13 +1320,9 @@ enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
  */
 static int __init musb_core_init(u16 musb_type, struct musb *musb)
 {
-#ifdef MUSB_AHB_ID
-	u32 data;
-#endif
 	u8 reg;
 	char *type;
-	u16 hwvers, rev_major, rev_minor;
-	char aInfo[78], aRevision[32], aDate[12];
+	char aInfo[90], aRevision[32], aDate[12];
 	void __iomem	*mbase = musb->mregs;
 	int		status = 0;
 	int		i;
@@ -1332,23 +1331,17 @@ static int __init musb_core_init(u16 musb_type, struct musb *musb)
 	reg = musb_read_configdata(mbase);
 
 	strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
-	if (reg & MUSB_CONFIGDATA_DYNFIFO)
+	if (reg & MUSB_CONFIGDATA_DYNFIFO) {
 		strcat(aInfo, ", dyn FIFOs");
+		musb->dyn_fifo = true;
+	}
 	if (reg & MUSB_CONFIGDATA_MPRXE) {
 		strcat(aInfo, ", bulk combine");
-#ifdef C_MP_RX
 		musb->bulk_combine = true;
-#else
-		strcat(aInfo, " (X)");		/* no driver support */
-#endif
 	}
 	if (reg & MUSB_CONFIGDATA_MPTXE) {
 		strcat(aInfo, ", bulk split");
-#ifdef C_MP_TX
 		musb->bulk_split = true;
-#else
-		strcat(aInfo, " (X)");		/* no driver support */
-#endif
 	}
 	if (reg & MUSB_CONFIGDATA_HBRXE) {
 		strcat(aInfo, ", HB-ISO Rx");
@@ -1364,20 +1357,7 @@ static int __init musb_core_init(u16 musb_type, struct musb *musb)
 	printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
 			musb_driver_name, reg, aInfo);
 
-#ifdef MUSB_AHB_ID
-	data = musb_readl(mbase, 0x404);
-	sprintf(aDate, "%04d-%02x-%02x", (data & 0xffff),
-		(data >> 16) & 0xff, (data >> 24) & 0xff);
-	/* FIXME ID2 and ID3 are unused */
-	data = musb_readl(mbase, 0x408);
-	printk(KERN_DEBUG "ID2=%lx\n", (long unsigned)data);
-	data = musb_readl(mbase, 0x40c);
-	printk(KERN_DEBUG "ID3=%lx\n", (long unsigned)data);
-	reg = musb_readb(mbase, 0x400);
-	musb_type = ('M' == reg) ? MUSB_CONTROLLER_MHDRC : MUSB_CONTROLLER_HDRC;
-#else
 	aDate[0] = 0;
-#endif
 	if (MUSB_CONTROLLER_MHDRC == musb_type) {
 		musb->is_multipoint = 1;
 		type = "M";
@@ -1394,11 +1374,10 @@ static int __init musb_core_init(u16 musb_type, struct musb *musb)
 	}
 
 	/* log release info */
-	hwvers = musb_read_hwvers(mbase);
-	rev_major = (hwvers >> 10) & 0x1f;
-	rev_minor = hwvers & 0x3ff;
-	snprintf(aRevision, 32, "%d.%d%s", rev_major,
-		rev_minor, (hwvers & 0x8000) ? "RC" : "");
+	musb->hwvers = musb_read_hwvers(mbase);
+	snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers),
+		MUSB_HWVERS_MINOR(musb->hwvers),
+		(musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
 	printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
 			musb_driver_name, type, aRevision, aDate);
 
@@ -1409,21 +1388,10 @@ static int __init musb_core_init(u16 musb_type, struct musb *musb)
 	musb->nr_endpoints = 1;
 	musb->epmask = 1;
 
-	if (reg & MUSB_CONFIGDATA_DYNFIFO) {
-		if (musb->config->dyn_fifo)
-			status = ep_config_from_table(musb);
-		else {
-			ERR("reconfigure software for Dynamic FIFOs\n");
-			status = -ENODEV;
-		}
-	} else {
-		if (!musb->config->dyn_fifo)
-			status = ep_config_from_hw(musb);
-		else {
-			ERR("reconfigure software for static FIFOs\n");
-			return -ENODEV;
-		}
-	}
+	if (musb->dyn_fifo)
+		status = ep_config_from_table(musb);
+	else
+		status = ep_config_from_hw(musb);
 
 	if (status < 0)
 		return status;
@@ -1453,7 +1421,7 @@ static int __init musb_core_init(u16 musb_type, struct musb *musb)
 #endif
 
 		if (hw_ep->max_packet_sz_tx) {
-			printk(KERN_DEBUG
+			DBG(1,
 				"%s: hw_ep %d%s, %smax %d\n",
 				musb_driver_name, i,
 				hw_ep->is_shared_fifo ? "shared" : "tx",
@@ -1462,7 +1430,7 @@ static int __init musb_core_init(u16 musb_type, struct musb *musb)
 				hw_ep->max_packet_sz_tx);
 		}
 		if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
-			printk(KERN_DEBUG
+			DBG(1,
 				"%s: hw_ep %d%s, %smax %d\n",
 				musb_driver_name, i,
 				"rx",
@@ -1479,7 +1447,8 @@ static int __init musb_core_init(u16 musb_type, struct musb *musb)
 
 /*-------------------------------------------------------------------------*/
 
-#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430) || defined (CONFIG_SOC_JZ4760)
+#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430) || \
+	defined(CONFIG_ARCH_OMAP4) || defined (CONFIG_SOC_JZ4760) || defined (CONFIG_SOC_JZ4760B)
 
 static irqreturn_t generic_interrupt(int irq, void *__hci)
 {
@@ -1487,7 +1456,6 @@ static irqreturn_t generic_interrupt(int irq, void *__hci)
 	struct musb	*musb = __hci;
 
 	irqreturn_t rv, rv_dma, rv_usb;
-
 	rv = rv_dma = rv_usb = IRQ_NONE;
 
 	spin_lock_irqsave(&musb->lock, flags);
@@ -1537,10 +1505,18 @@ irqreturn_t musb_interrupt(struct musb *musb)
 		(devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral",
 		musb->int_usb, musb->int_tx, musb->int_rx);
 
+#ifdef CONFIG_USB_GADGET_MUSB_HDRC
+	if (is_otg_enabled(musb) || is_peripheral_enabled(musb))
+		if (!musb->gadget_driver) {
+			DBG(5, "No gadget driver loaded\n");
+			return IRQ_HANDLED;
+		}
+#endif
+
 	/* the core can interrupt us for multiple reasons; docs have
 	 * a generic interrupt flowchart to follow
 	 */
-	if (musb->int_usb & STAGE0_MASK)
+	if (musb->int_usb)
 		retval |= musb_stage0_irq(musb, musb->int_usb,
 				devctl, power);
 
@@ -1595,10 +1571,10 @@ irqreturn_t musb_interrupt(struct musb *musb)
 		ep_num++;
 	}
 
-	/* finish handling "global" interrupts after handling fifos */
-	if (musb->int_usb)
-		retval |= musb_stage2_irq(musb,
-				musb->int_usb, devctl, power);
+#ifdef TEST_ON_WIN7
+	if (out_flag)
+	mod_timer(&monitor_remove_timer, 200+jiffies);
+#endif
 
 	return retval;
 }
@@ -1704,7 +1680,7 @@ musb_vbus_store(struct device *dev, struct device_attribute *attr,
 	unsigned long	val;
 
 	if (sscanf(buf, "%lu", &val) < 1) {
-		printk(KERN_ERR "Invalid VBUS timeout ms value\n");
+		dev_err(dev, "Invalid VBUS timeout ms value\n");
 		return -EINVAL;
 	}
 
@@ -1754,7 +1730,7 @@ musb_srp_store(struct device *dev, struct device_attribute *attr,
 
 	if (sscanf(buf, "%hu", &srp) != 1
 			|| (srp != 1)) {
-		printk(KERN_ERR "SRP: Value must be 1\n");
+		dev_err(dev, "SRP: Value must be 1\n");
 		return -EINVAL;
 	}
 
@@ -1767,6 +1743,19 @@ static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
 
 #endif /* CONFIG_USB_GADGET_MUSB_HDRC */
 
+static struct attribute *musb_attributes[] = {
+	&dev_attr_mode.attr,
+	&dev_attr_vbus.attr,
+#ifdef CONFIG_USB_GADGET_MUSB_HDRC
+	&dev_attr_srp.attr,
+#endif
+	NULL
+};
+
+static const struct attribute_group musb_attr_group = {
+	.attrs = musb_attributes,
+};
+
 #endif	/* sysfs */
 
 /* Only used to provide driver mode change events */
@@ -1841,11 +1830,7 @@ static void musb_free(struct musb *musb)
 	 */
 
 #ifdef CONFIG_SYSFS
-	device_remove_file(musb->controller, &dev_attr_mode);
-	device_remove_file(musb->controller, &dev_attr_vbus);
-#ifdef CONFIG_USB_GADGET_MUSB_HDRC
-	device_remove_file(musb->controller, &dev_attr_srp);
-#endif
+	sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
 #endif
 
 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
@@ -1864,21 +1849,6 @@ static void musb_free(struct musb *musb)
 		dma_controller_destroy(c);
 	}
 
-	musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
-	musb_platform_exit(musb);
-	musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
-
-#ifdef HAVE_CLK
-	if (musb->clock) {
-		clk_disable(musb->clock);
-		clk_put(musb->clock);
-	}
-#endif
-
-#ifdef CONFIG_USB_MUSB_OTG
-	put_device(musb->xceiv->dev);
-#endif
-
 #ifdef CONFIG_USB_MUSB_HDRC_HCD
 	usb_put_hcd(musb_to_hcd(musb));
 #else
@@ -1906,8 +1876,10 @@ musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
 	 */
 	if (!plat) {
 		dev_dbg(dev, "no platform_data?\n");
-		return -ENODEV;
+		status = -ENODEV;
+		goto fail0;
 	}
+
 	switch (plat->mode) {
 	case MUSB_HOST:
 #ifdef CONFIG_USB_MUSB_HDRC_HCD
@@ -1929,13 +1901,16 @@ bad_config:
 #endif
 	default:
 		dev_err(dev, "incompatible Kconfig role setting\n");
-		return -EINVAL;
+		status = -EINVAL;
+		goto fail0;
 	}
 
 	/* allocate */
 	musb = allocate_instance(dev, plat->config, ctrl);
-	if (!musb)
-		return -ENOMEM;
+	if (!musb) {
+		status = -ENOMEM;
+		goto fail0;
+	}
 
 	spin_lock_init(&musb->lock);
 	musb->board_mode = plat->mode;
@@ -1943,7 +1918,7 @@ bad_config:
 	musb->set_clock = plat->set_clock;
 	musb->min_power = plat->min_power;
 
-#ifdef HAVE_CLK
+#ifndef CONFIG_JZSOC
 	/* Clock usage is chip-specific ... functional clock (DaVinci,
 	 * OMAP2430), or PHY ref (some TUSB6010 boards).  All this core
 	 * code does is make sure a clock handle is available; platform
@@ -1954,7 +1929,7 @@ bad_config:
 		if (IS_ERR(musb->clock)) {
 			status = PTR_ERR(musb->clock);
 			musb->clock = NULL;
-			goto fail;
+			goto fail1;
 		}
 	}
 #endif
@@ -1974,14 +1949,15 @@ bad_config:
 	 */
 	musb->isr = generic_interrupt;
 	status = musb_platform_init(musb);
-
 	if (status < 0)
-		goto fail;
+		goto fail2;
+
 	if (!musb->isr) {
 		status = -ENODEV;
-		goto fail2;
+		goto fail3;
 	}
 
+
 #ifndef CONFIG_MUSB_PIO_ONLY
 	if (use_dma && dev->dma_mask) {
 		struct dma_controller	*c;
@@ -1999,14 +1975,13 @@ bad_config:
 	/* be sure interrupts are disabled before connecting ISR */
 	musb_platform_disable(musb);
 	musb_generic_disable(musb);
-	
+
 	/* setup musb parts of the core (especially endpoints) */
 	status = musb_core_init(plat->config->multipoint
 			? MUSB_CONTROLLER_MHDRC
 			: MUSB_CONTROLLER_HDRC, musb);
-	
 	if (status < 0)
-		goto fail2;
+		goto fail3;
 
 #ifdef CONFIG_USB_MUSB_OTG
 	setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
@@ -2019,7 +1994,7 @@ bad_config:
 	if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
 		dev_err(dev, "request_irq %d failed!\n", nIrq);
 		status = -ENODEV;
-		goto fail2;
+		goto fail3;
 	}
 	musb->nIrq = nIrq;
 /* FIXME this handles wakeup irqs wrong */
@@ -2030,19 +2005,6 @@ bad_config:
 		musb->irq_wake = 0;
 	}
 
-	pr_info("%s: USB %s mode controller at %p using %s, IRQ %d\n",
-			musb_driver_name,
-			({char *s;
-			switch (musb->board_mode) {
-			case MUSB_HOST:		s = "Host"; break;
-			case MUSB_PERIPHERAL:	s = "Peripheral"; break;
-			default:		s = "OTG"; break;
-			}; s; }),
-			ctrl,
-			(is_dma_capable() && musb->dma_controller)
-				? "DMA" : "PIO",
-			musb->nIrq);
-
 	/* host side needs more setup */
 	if (is_host_enabled(musb)) {
 		struct usb_hcd	*hcd = musb_to_hcd(musb);
@@ -2060,13 +2022,13 @@ bad_config:
 	 * Otherwise, wait till the gadget driver hooks up.
 	 */
 	if (!is_otg_enabled(musb) && is_host_enabled(musb)) {
+		struct usb_hcd	*hcd = musb_to_hcd(musb);
+
 		MUSB_HST_MODE(musb);
 		musb->xceiv->default_a = 1;
 		musb->xceiv->state = OTG_STATE_A_IDLE;
 
 		status = usb_add_hcd(musb_to_hcd(musb), -1, 0);
-		if (status)
-			goto fail;
 
 		DBG(1, "%s mode, status %d, devctl %02x %c\n",
 			"HOST", status,
@@ -2076,14 +2038,11 @@ bad_config:
 				? 'B' : 'A'));
 
 	} else /* peripheral is enabled */ {
-
 		MUSB_DEV_MODE(musb);
 		musb->xceiv->default_a = 0;
 		musb->xceiv->state = OTG_STATE_B_IDLE;
 
 		status = musb_gadget_setup(musb);
-		if (status)
-			goto fail;
 
 		DBG(1, "%s mode, status %d, dev%02x\n",
 			is_otg_enabled(musb) ? "OTG" : "PERIPHERAL",
@@ -2093,39 +2052,47 @@ bad_config:
 	}
 
 #ifdef CONFIG_SYSFS
-	status = device_create_file(dev, &dev_attr_mode);
-	status = device_create_file(dev, &dev_attr_vbus);
-#ifdef CONFIG_USB_GADGET_MUSB_HDRC
-	status = device_create_file(dev, &dev_attr_srp);
-#endif /* CONFIG_USB_GADGET_MUSB_HDRC */
-	status = 0;
-#endif
+	status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group);
 	if (status)
-		goto fail2;
+		goto fail5;
+#endif
+
+	dev_info(dev, "USB %s mode controller at %p using %s, IRQ %d\n",
+			({char *s;
+			 switch (musb->board_mode) {
+			 case MUSB_HOST:		s = "Host"; break;
+			 case MUSB_PERIPHERAL:	s = "Peripheral"; break;
+			 default:		s = "OTG"; break;
+			 }; s; }),
+			ctrl,
+			(is_dma_capable() && musb->dma_controller)
+			? "DMA" : "PIO",
+			musb->nIrq);
 
 	return 0;
 
-fail2:
-#ifdef CONFIG_SYSFS
-	device_remove_file(musb->controller, &dev_attr_mode);
-	device_remove_file(musb->controller, &dev_attr_vbus);
-#ifdef CONFIG_USB_GADGET_MUSB_HDRC
-	device_remove_file(musb->controller, &dev_attr_srp);
-#endif
-#endif
+fail5:
+	musb_exit_debugfs(musb);
+
+fail3:
+	if (musb->irq_wake)
+		device_init_wakeup(dev, 0);
 	musb_platform_exit(musb);
-fail:
-	dev_err(musb->controller,
-		"musb_init_controller failed with status %d\n", status);
 
-#ifdef HAVE_CLK
+fail2:
+#ifndef CONFIG_JZSOC
 	if (musb->clock)
 		clk_put(musb->clock);
 #endif
 
-	device_init_wakeup(dev, 0);
+fail1:
+	dev_err(musb->controller,
+		"musb_init_controller failed with status %d\n", status);
+
 	musb_free(musb);
 
+fail0:
+
 	return status;
 
 }
@@ -2144,6 +2111,7 @@ static int __init musb_probe(struct platform_device *pdev)
 {
 	struct device	*dev = &pdev->dev;
 	int		irq = platform_get_irq(pdev, 0);
+	int		status;
 	struct resource	*iomem;
 	void __iomem	*base;
 
@@ -2151,7 +2119,7 @@ static int __init musb_probe(struct platform_device *pdev)
 	if (!iomem || irq == 0)
 		return -ENODEV;
 
-	base = ioremap(iomem->start, iomem->end - iomem->start + 1);
+	base = ioremap(iomem->start, resource_size(iomem));
 	if (!base) {
 		dev_err(dev, "ioremap failed\n");
 		return -ENOMEM;
@@ -2161,10 +2129,14 @@ static int __init musb_probe(struct platform_device *pdev)
 	/* clobbered by use_dma=n */
 	orig_dma_mask = dev->dma_mask;
 #endif
-	return musb_init_controller(dev, irq, base);
+	status = musb_init_controller(dev, irq, base);
+	if (status < 0)
+		iounmap(base);
+
+	return status;
 }
 
-static int __devexit musb_remove(struct platform_device *pdev)
+static int __exit musb_remove(struct platform_device *pdev)
 {
 	struct musb	*musb = dev_to_musb(&pdev->dev);
 	void __iomem	*ctrl_base = musb->ctrl_base;
@@ -2174,11 +2146,9 @@ static int __devexit musb_remove(struct platform_device *pdev)
 	 *  - Peripheral mode: peripheral is deactivated (or never-activated)
 	 *  - OTG mode: both roles are deactivated (or never-activated)
 	 */
+	musb_exit_debugfs(musb);
 	musb_shutdown(pdev);
-#ifdef CONFIG_USB_MUSB_HDRC_HCD
-	if (musb->board_mode == MUSB_HOST)
-		usb_remove_hcd(musb_to_hcd(musb));
-#endif
+
 	musb_free(musb);
 	iounmap(ctrl_base);
 	device_init_wakeup(&pdev->dev, 0);
@@ -2190,14 +2160,154 @@ static int __devexit musb_remove(struct platform_device *pdev)
 
 #ifdef	CONFIG_PM
 
-static int musb_suspend(struct platform_device *pdev, pm_message_t message)
+static struct musb_context_registers musb_context;
+
+void musb_save_context(struct musb *musb)
+{
+	int i;
+	void __iomem *musb_base = musb->mregs;
+	void __iomem *epio;
+
+	if (is_host_enabled(musb)) {
+		musb_context.frame = musb_readw(musb_base, MUSB_FRAME);
+		musb_context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
+		musb_context.busctl = musb_read_ulpi_buscontrol(musb->mregs);
+	}
+	musb_context.power = musb_readb(musb_base, MUSB_POWER);
+	musb_context.intrtxe = musb_readw(musb_base, MUSB_INTRTXE);
+	musb_context.intrrxe = musb_readw(musb_base, MUSB_INTRRXE);
+	musb_context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
+	musb_context.index = musb_readb(musb_base, MUSB_INDEX);
+	musb_context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
+
+	for (i = 0; i < musb->config->num_eps; ++i) {
+		epio = musb->endpoints[i].regs;
+		musb_context.index_regs[i].txmaxp =
+			musb_readw(epio, MUSB_TXMAXP);
+		musb_context.index_regs[i].txcsr =
+			musb_readw(epio, MUSB_TXCSR);
+		musb_context.index_regs[i].rxmaxp =
+			musb_readw(epio, MUSB_RXMAXP);
+		musb_context.index_regs[i].rxcsr =
+			musb_readw(epio, MUSB_RXCSR);
+
+		if (musb->dyn_fifo) {
+			musb_context.index_regs[i].txfifoadd =
+					musb_read_txfifoadd(musb_base);
+			musb_context.index_regs[i].rxfifoadd =
+					musb_read_rxfifoadd(musb_base);
+			musb_context.index_regs[i].txfifosz =
+					musb_read_txfifosz(musb_base);
+			musb_context.index_regs[i].rxfifosz =
+					musb_read_rxfifosz(musb_base);
+		}
+		if (is_host_enabled(musb)) {
+			musb_context.index_regs[i].txtype =
+				musb_readb(epio, MUSB_TXTYPE);
+			musb_context.index_regs[i].txinterval =
+				musb_readb(epio, MUSB_TXINTERVAL);
+			musb_context.index_regs[i].rxtype =
+				musb_readb(epio, MUSB_RXTYPE);
+			musb_context.index_regs[i].rxinterval =
+				musb_readb(epio, MUSB_RXINTERVAL);
+
+			musb_context.index_regs[i].txfunaddr =
+				musb_read_txfunaddr(musb_base, i);
+			musb_context.index_regs[i].txhubaddr =
+				musb_read_txhubaddr(musb_base, i);
+			musb_context.index_regs[i].txhubport =
+				musb_read_txhubport(musb_base, i);
+
+			musb_context.index_regs[i].rxfunaddr =
+				musb_read_rxfunaddr(musb_base, i);
+			musb_context.index_regs[i].rxhubaddr =
+				musb_read_rxhubaddr(musb_base, i);
+			musb_context.index_regs[i].rxhubport =
+				musb_read_rxhubport(musb_base, i);
+		}
+	}
+
+	musb_platform_save_context(musb, &musb_context);
+}
+
+void musb_restore_context(struct musb *musb)
+{
+	int i;
+	void __iomem *musb_base = musb->mregs;
+	void __iomem *ep_target_regs;
+	void __iomem *epio;
+
+	musb_platform_restore_context(musb, &musb_context);
+
+	if (is_host_enabled(musb)) {
+		musb_writew(musb_base, MUSB_FRAME, musb_context.frame);
+		musb_writeb(musb_base, MUSB_TESTMODE, musb_context.testmode);
+		musb_write_ulpi_buscontrol(musb->mregs, musb_context.busctl);
+	}
+	musb_writeb(musb_base, MUSB_POWER, musb_context.power);
+	musb_writew(musb_base, MUSB_INTRTXE, musb_context.intrtxe);
+	musb_writew(musb_base, MUSB_INTRRXE, musb_context.intrrxe);
+	musb_writeb(musb_base, MUSB_INTRUSBE, musb_context.intrusbe);
+	musb_writeb(musb_base, MUSB_DEVCTL, musb_context.devctl);
+
+	for (i = 0; i < musb->config->num_eps; ++i) {
+		epio = musb->endpoints[i].regs;
+		musb_writew(epio, MUSB_TXMAXP,
+			musb_context.index_regs[i].txmaxp);
+		musb_writew(epio, MUSB_TXCSR,
+			musb_context.index_regs[i].txcsr);
+		musb_writew(epio, MUSB_RXMAXP,
+			musb_context.index_regs[i].rxmaxp);
+		musb_writew(epio, MUSB_RXCSR,
+			musb_context.index_regs[i].rxcsr);
+
+		if (musb->dyn_fifo) {
+			musb_write_txfifosz(musb_base,
+				musb_context.index_regs[i].txfifosz);
+			musb_write_rxfifosz(musb_base,
+				musb_context.index_regs[i].rxfifosz);
+			musb_write_txfifoadd(musb_base,
+				musb_context.index_regs[i].txfifoadd);
+			musb_write_rxfifoadd(musb_base,
+				musb_context.index_regs[i].rxfifoadd);
+		}
+
+		if (is_host_enabled(musb)) {
+			musb_writeb(epio, MUSB_TXTYPE,
+				musb_context.index_regs[i].txtype);
+			musb_writeb(epio, MUSB_TXINTERVAL,
+				musb_context.index_regs[i].txinterval);
+			musb_writeb(epio, MUSB_RXTYPE,
+				musb_context.index_regs[i].rxtype);
+			musb_writeb(epio, MUSB_RXINTERVAL,
+
+			musb_context.index_regs[i].rxinterval);
+			musb_write_txfunaddr(musb_base, i,
+				musb_context.index_regs[i].txfunaddr);
+			musb_write_txhubaddr(musb_base, i,
+				musb_context.index_regs[i].txhubaddr);
+			musb_write_txhubport(musb_base, i,
+				musb_context.index_regs[i].txhubport);
+
+			ep_target_regs =
+				musb_read_target_reg_base(i, musb_base);
+
+			musb_write_rxfunaddr(ep_target_regs,
+				musb_context.index_regs[i].rxfunaddr);
+			musb_write_rxhubaddr(ep_target_regs,
+				musb_context.index_regs[i].rxhubaddr);
+			musb_write_rxhubport(ep_target_regs,
+				musb_context.index_regs[i].rxhubport);
+		}
+	}
+}
+
+static int musb_suspend(struct device *dev)
 {
+	struct platform_device *pdev = to_platform_device(dev);
 	unsigned long	flags;
 	struct musb	*musb = dev_to_musb(&pdev->dev);
 
-	if (!musb->clock)
-		return 0;
-
 	spin_lock_irqsave(&musb->lock, flags);
 
 	if (is_peripheral_active(musb)) {
@@ -2210,30 +2320,35 @@ static int musb_suspend(struct platform_device *pdev, pm_message_t message)
 		 */
 	}
 
-#ifdef HAVE_CLK
-	if (musb->set_clock)
-		musb->set_clock(musb->clock, 0);
-	else
-		clk_disable(musb->clock);
+	musb_save_context(musb);
+#ifndef CONFIG_JZSOC
+	if (musb->clock) {
+		if (musb->set_clock)
+			musb->set_clock(musb->clock, 0);
+		else
+			clk_disable(musb->clock);
+	}
 #endif
-
 	spin_unlock_irqrestore(&musb->lock, flags);
 	return 0;
 }
 
-static int musb_resume_early(struct platform_device *pdev)
+static int musb_resume_noirq(struct device *dev)
 {
+	struct platform_device *pdev = to_platform_device(dev);
 	struct musb	*musb = dev_to_musb(&pdev->dev);
 
-	if (!musb->clock)
-		return 0;
-#ifdef HAVE_CLK
-	if (musb->set_clock)
-		musb->set_clock(musb->clock, 1);
-	else
-		clk_enable(musb->clock);
+#ifndef CONFIG_JZSOC
+	if (musb->clock) {
+		if (musb->set_clock)
+			musb->set_clock(musb->clock, 1);
+		else
+			clk_enable(musb->clock);
+	}
 #endif
 
+	musb_restore_context(musb);
+
 	/* for static cmos like DaVinci, register values were preserved
 	 * unless for some reason the whole soc powered down or the USB
 	 * module got reset through the PSC (vs just being disabled).
@@ -2241,9 +2356,14 @@ static int musb_resume_early(struct platform_device *pdev)
 	return 0;
 }
 
+static const struct dev_pm_ops musb_dev_pm_ops = {
+	.suspend	= musb_suspend,
+	.resume_noirq	= musb_resume_noirq,
+};
+
+#define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
 #else
-#define	musb_suspend	NULL
-#define	musb_resume_early	NULL
+#define	MUSB_DEV_PM_OPS	NULL
 #endif
 
 static struct platform_driver musb_driver = {
@@ -2251,17 +2371,19 @@ static struct platform_driver musb_driver = {
 		.name		= (char *)musb_driver_name,
 		.bus		= &platform_bus_type,
 		.owner		= THIS_MODULE,
+		.pm		= MUSB_DEV_PM_OPS,
 	},
-	.remove		= __devexit_p(musb_remove),
+	.remove		= __exit_p(musb_remove),
 	.shutdown	= musb_shutdown,
-	.suspend	= musb_suspend,
-	.resume_early	= musb_resume_early,
 };
 
 /*-------------------------------------------------------------------------*/
 
 static int __init musb_init(void)
 {
+#ifdef TEST_ON_WIN7
+	setup_timer(&monitor_remove_timer, monitor_timer_func, 0);
+#endif
 #ifdef CONFIG_USB_MUSB_HDRC_HCD
 	if (usb_disabled())
 		return 0;
@@ -2299,6 +2421,9 @@ fs_initcall(musb_init);
 
 static void __exit musb_cleanup(void)
 {
+#ifdef TEST_ON_WIN7
+	del_timer(&monitor_remove_timer);
+#endif
 	platform_driver_unregister(&musb_driver);
 }
 module_exit(musb_cleanup);
diff --git a/drivers/usb/musb/musb_core.h b/drivers/usb/musb/musb_core.h
index 2c9282199ac..7f324ef7ab6 100644
--- a/drivers/usb/musb/musb_core.h
+++ b/drivers/usb/musb/musb_core.h
@@ -52,6 +52,17 @@ struct musb;
 struct musb_hw_ep;
 struct musb_ep;
 
+//#define TEST_ON_WIN7
+
+/* Helper defines for struct musb->hwvers */
+#define MUSB_HWVERS_MAJOR(x)	((x >> 10) & 0x1f)
+#define MUSB_HWVERS_MINOR(x)	(x & 0x3ff)
+#define MUSB_HWVERS_RC		0x8000
+#define MUSB_HWVERS_1300	0x52C
+#define MUSB_HWVERS_1400	0x590
+#define MUSB_HWVERS_1800	0x720
+#define MUSB_HWVERS_1900	0x784
+#define MUSB_HWVERS_2000	0x800
 
 #include "musb_debug.h"
 #include "musb_dma.h"
@@ -95,6 +106,13 @@ struct musb_ep;
 #endif
 #endif	/* need MUSB gadget selection */
 
+#ifndef CONFIG_HAVE_CLK
+/* Dummy stub for clk framework */
+#define clk_get(dev, id)	NULL
+#define clk_put(clock)		do {} while (0)
+#define clk_enable(clock)	do {} while (0)
+#define clk_disable(clock)	do {} while (0)
+#endif
 
 #ifdef CONFIG_PROC_FS
 #include <linux/fs.h>
@@ -197,7 +215,8 @@ enum musb_g_ep0_state {
  */
 
 #if defined(CONFIG_ARCH_DAVINCI) || defined(CONFIG_ARCH_OMAP2430) \
-		|| defined(CONFIG_ARCH_OMAP3430) || defined(CONFIG_BLACKFIN)
+		|| defined(CONFIG_ARCH_OMAP3430) || defined(CONFIG_BLACKFIN) \
+		|| defined(CONFIG_ARCH_OMAP4)
 /* REVISIT indexed access seemed to
  * misbehave (on DaVinci) for at least peripheral IN ...
  */
@@ -313,8 +332,10 @@ struct musb {
 	/* device lock */
 	spinlock_t		lock;
 	struct clk		*clock;
+	struct clk		*phy_clock;
 	irqreturn_t		(*isr)(int, void *);
 	struct work_struct	irq_work;
+	u16			hwvers;
 
 /* this hub status bit is reserved by USB 2.0 and not seen by usbcore */
 #define MUSB_PORT_STAT_RESUME	(1 << 31)
@@ -396,22 +417,15 @@ struct musb {
 
 	unsigned		hb_iso_rx:1;	/* high bandwidth iso rx? */
 	unsigned		hb_iso_tx:1;	/* high bandwidth iso tx? */
+	unsigned		dyn_fifo:1;	/* dynamic FIFO supported? */
 
-#ifdef C_MP_TX
-	unsigned bulk_split:1;
+	unsigned		bulk_split:1;
 #define	can_bulk_split(musb,type) \
-		(((type) == USB_ENDPOINT_XFER_BULK) && (musb)->bulk_split)
-#else
-#define	can_bulk_split(musb, type)	0
-#endif
+	(((type) == USB_ENDPOINT_XFER_BULK) && (musb)->bulk_split)
 
-#ifdef C_MP_RX
-	unsigned bulk_combine:1;
+	unsigned		bulk_combine:1;
 #define	can_bulk_combine(musb,type) \
-		(((type) == USB_ENDPOINT_XFER_BULK) && (musb)->bulk_combine)
-#else
-#define	can_bulk_combine(musb, type)	0
-#endif
+	(((type) == USB_ENDPOINT_XFER_BULK) && (musb)->bulk_combine)
 
 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
 	/* is_suspended means USB B_PERIPHERAL suspend */
@@ -438,6 +452,7 @@ struct musb {
 	struct usb_gadget	g;			/* the gadget */
 	struct usb_gadget_driver *gadget_driver;	/* its driver */
 #endif
+
 	unsigned int b_dma_share_usb_irq;
 
 	struct musb_hdrc_config	*config;
@@ -447,6 +462,47 @@ struct musb {
 #endif
 };
 
+#ifdef CONFIG_PM
+struct musb_csr_regs {
+	/* FIFO registers */
+	u16 txmaxp, txcsr, rxmaxp, rxcsr;
+	u16 rxfifoadd, txfifoadd;
+	u8 txtype, txinterval, rxtype, rxinterval;
+	u8 rxfifosz, txfifosz;
+	u8 txfunaddr, txhubaddr, txhubport;
+	u8 rxfunaddr, rxhubaddr, rxhubport;
+};
+
+struct musb_context_registers {
+
+#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
+    defined(CONFIG_ARCH_OMAP4)
+	u32 otg_sysconfig, otg_forcestandby;
+#endif
+	u8 power;
+	u16 intrtxe, intrrxe;
+	u8 intrusbe;
+	u16 frame;
+	u8 index, testmode;
+
+	u8 devctl, busctl, misc;
+
+	struct musb_csr_regs index_regs[MUSB_C_NUM_EPS];
+};
+
+#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
+    defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_BLACKFIN)
+extern void musb_platform_save_context(struct musb *musb,
+		struct musb_context_registers *musb_context);
+extern void musb_platform_restore_context(struct musb *musb,
+		struct musb_context_registers *musb_context);
+#else
+#define musb_platform_save_context(m, x)	do {} while (0)
+#define musb_platform_restore_context(m, x)	do {} while (0)
+#endif
+
+#endif
+
 static inline void musb_set_vbus(struct musb *musb, int is_on)
 {
 	musb->board_set_vbus(musb, is_on);
@@ -548,7 +604,9 @@ extern void musb_hnp_stop(struct musb *musb);
 extern int musb_platform_set_mode(struct musb *musb, u8 musb_mode);
 
 #if defined(CONFIG_USB_TUSB6010) || defined(CONFIG_BLACKFIN) || \
-	defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX)
+	defined(CONFIG_ARCH_DAVINCI_DA8XX) || \
+	defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
+	defined(CONFIG_ARCH_OMAP4)
 extern void musb_platform_try_idle(struct musb *musb, unsigned long timeout);
 #else
 #define musb_platform_try_idle(x, y)		do {} while (0)
diff --git a/drivers/usb/musb/musb_debug.h b/drivers/usb/musb/musb_debug.h
index 9fc1db44c72..94f6973cf8f 100644
--- a/drivers/usb/musb/musb_debug.h
+++ b/drivers/usb/musb/musb_debug.h
@@ -42,11 +42,10 @@
 #define INFO(fmt, args...) yprintk(KERN_INFO, fmt, ## args)
 #define ERR(fmt, args...) yprintk(KERN_ERR, fmt, ## args)
 
-#define xprintk(level, facility, format, args...) do { \
-	if (_dbg_level(level)) { \
-		printk(facility "%s %d: " format , \
-				__func__, __LINE__ , ## args); \
-	} } while (0)
+#define DBG(level, format, args...) do { \
+	if (_dbg_level(level)) \
+		pr_debug("%s %d: " format, __func__, __LINE__, ## args); \
+	} while (0)
 
 extern unsigned musb_debug;
 
@@ -55,8 +54,19 @@ static inline int _dbg_level(unsigned l)
 	return musb_debug >= l;
 }
 
-#define DBG(level, fmt, args...) xprintk(level, KERN_DEBUG, fmt, ## args)
-
 extern const char *otg_state_string(struct musb *);
 
+#ifdef CONFIG_DEBUG_FS
+extern int musb_init_debugfs(struct musb *musb);
+extern void musb_exit_debugfs(struct musb *musb);
+#else
+static inline int musb_init_debugfs(struct musb *musb)
+{
+	return 0;
+}
+static inline void musb_exit_debugfs(struct musb *musb)
+{
+}
+#endif
+
 #endif				/*  __MUSB_LINUX_DEBUG_H__ */
diff --git a/drivers/usb/musb/musb_gadget.c b/drivers/usb/musb/musb_gadget.c
index 73b7b3818da..3aa17dec3d0 100644
--- a/drivers/usb/musb/musb_gadget.c
+++ b/drivers/usb/musb/musb_gadget.c
@@ -1,10 +1,10 @@
-
 /*
  * MUSB OTG driver peripheral support
  *
  * Copyright 2005 Mentor Graphics Corporation
  * Copyright (C) 2005-2006 by Texas Instruments
  * Copyright (C) 2006-2007 Nokia Corporation
+ * Copyright (C) 2009 MontaVista Software, Inc. <source@mvista.com>
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
@@ -43,6 +43,7 @@
 #include <linux/moduleparam.h>
 #include <linux/stat.h>
 #include <linux/dma-mapping.h>
+#include <linux/slab.h>
 
 #include "musb_core.h"
 
@@ -94,6 +95,59 @@
 
 /* ----------------------------------------------------------------------- */
 
+/* Maps the buffer to dma  */
+
+static inline void map_dma_buffer(struct musb_request *request,
+				struct musb *musb)
+{
+	if (request->request.dma == DMA_ADDR_INVALID) {
+		request->request.dma = dma_map_single(
+				musb->controller,
+				request->request.buf,
+				request->request.length,
+				request->tx
+					? DMA_TO_DEVICE
+					: DMA_FROM_DEVICE);
+		request->mapped = 1;
+	} else {
+		dma_sync_single_for_device(musb->controller,
+			request->request.dma,
+			request->request.length,
+			request->tx
+				? DMA_TO_DEVICE
+				: DMA_FROM_DEVICE);
+		request->mapped = 0;
+	}
+}
+
+/* Unmap the buffer from dma and maps it back to cpu */
+static inline void unmap_dma_buffer(struct musb_request *request,
+				struct musb *musb)
+{
+	if (request->request.dma == DMA_ADDR_INVALID) {
+		DBG(20, "not unmapping a never mapped buffer\n");
+		return;
+	}
+	if (request->mapped) {
+		dma_unmap_single(musb->controller,
+			request->request.dma,
+			request->request.length,
+			request->tx
+				? DMA_TO_DEVICE
+				: DMA_FROM_DEVICE);
+		request->request.dma = DMA_ADDR_INVALID;
+		request->mapped = 0;
+	} else {
+		dma_sync_single_for_cpu(musb->controller,
+			request->request.dma,
+			request->request.length,
+			request->tx
+				? DMA_TO_DEVICE
+				: DMA_FROM_DEVICE);
+
+	}
+}
+
 /*
  * Immediately complete a request.
  *
@@ -121,24 +175,8 @@ __acquires(ep->musb->lock)
 
 	ep->busy = 1;
 	spin_unlock(&musb->lock);
-	if (is_dma_capable()) {
-		if (req->mapped) {
-			dma_unmap_single(musb->controller,
-					req->request.dma,
-					req->request.length,
-					req->tx
-						? DMA_TO_DEVICE
-						: DMA_FROM_DEVICE);
-			req->request.dma = DMA_ADDR_INVALID;
-			req->mapped = 0;
-		} else if (req->request.dma != DMA_ADDR_INVALID)
-			dma_sync_single_for_cpu(musb->controller,
-					req->request.dma,
-					req->request.length,
-					req->tx
-						? DMA_TO_DEVICE
-						: DMA_FROM_DEVICE);
-	}
+	if (is_dma_capable() && ep->dma)
+		unmap_dma_buffer(req, musb);
 	if (request->status == 0)
 		DBG(5, "%s done request %p,  %d/%d\n",
 				ep->end_point.name, request,
@@ -300,8 +338,13 @@ static void txstate(struct musb *musb, struct musb_request *req)
 			csr);
 
 #ifndef	CONFIG_MUSB_PIO_ONLY
-	if (is_dma_capable() && musb_ep->dma && request->dma % 4 == 0) {
+	if (is_dma_capable() && musb_ep->dma) {
 		struct dma_controller	*c = musb->dma_controller;
+		size_t request_size;
+
+		/* setup DMA, then program endpoint CSR */
+		request_size = min_t(size_t, request->length - request->actual,
+					musb_ep->dma->max_len);
 
 		use_dma = (request->dma != DMA_ADDR_INVALID);
 
@@ -309,11 +352,6 @@ static void txstate(struct musb *musb, struct musb_request *req)
 
 #ifdef CONFIG_USB_INVENTRA_DMA
 		{
-			size_t request_size;
-
-			/* setup DMA, then program endpoint CSR */
-			request_size = min(request->length,
-						musb_ep->dma->max_len);
 			if (request_size < musb_ep->packet_sz)
 				musb_ep->dma->desired_mode = 0;
 			else
@@ -322,7 +360,7 @@ static void txstate(struct musb *musb, struct musb_request *req)
 			use_dma = use_dma && c->channel_program(
 					musb_ep->dma, musb_ep->packet_sz,
 					musb_ep->dma->desired_mode,
-					request->dma, request_size);
+					request->dma + request->actual, request_size);
 			if (use_dma) {
 				if (musb_ep->dma->desired_mode == 0) {
 					/*
@@ -339,13 +377,15 @@ static void txstate(struct musb *musb, struct musb_request *req)
 					csr |= (MUSB_TXCSR_DMAENAB |
 							MUSB_TXCSR_MODE);
 					/* against programming guide */
-				} else
-					csr |= (MUSB_TXCSR_AUTOSET
-							| MUSB_TXCSR_DMAENAB
+				} else {
+					csr |= (MUSB_TXCSR_DMAENAB
 							| MUSB_TXCSR_DMAMODE
 							| MUSB_TXCSR_MODE);
-
+					if (!musb_ep->hb_mult)
+						csr |= MUSB_TXCSR_AUTOSET;
+				}
 				csr &= ~MUSB_TXCSR_P_UNDERRUN;
+
 				musb_writew(epio, MUSB_TXCSR, csr);
 			}
 		}
@@ -375,8 +415,8 @@ static void txstate(struct musb *musb, struct musb_request *req)
 		use_dma = use_dma && c->channel_program(
 				musb_ep->dma, musb_ep->packet_sz,
 				0,
-				request->dma,
-				request->length);
+				request->dma + request->actual,
+				request_size);
 		if (!use_dma) {
 			c->channel_release(musb_ep->dma);
 			musb_ep->dma = NULL;
@@ -388,13 +428,20 @@ static void txstate(struct musb *musb, struct musb_request *req)
 		use_dma = use_dma && c->channel_program(
 				musb_ep->dma, musb_ep->packet_sz,
 				request->zero,
-				request->dma,
-				request->length);
+				request->dma + request->actual,
+				request_size);
 #endif
 	}
 #endif
 
 	if (!use_dma) {
+		/*
+		 * Unmap the dma buffer back to cpu if dma channel
+		 * programming fails
+		 */
+		if (is_dma_capable() && musb_ep->dma)
+			unmap_dma_buffer(req, musb);
+
 		musb_write_fifo(musb_ep->hw_ep, fifo_count,
 				(u8 *) (request->buf + request->actual));
 		request->actual += fifo_count;
@@ -432,120 +479,89 @@ void musb_g_tx(struct musb *musb, u8 epnum)
 	DBG(4, "<== %s, txcsr %04x\n", musb_ep->end_point.name, csr);
 
 	dma = is_dma_capable() ? musb_ep->dma : NULL;
-	do {
-		/* REVISIT for high bandwidth, MUSB_TXCSR_P_INCOMPTX
-		 * probably rates reporting as a host error
-		 */
-		if (csr & MUSB_TXCSR_P_SENTSTALL) {
-			csr |= MUSB_TXCSR_P_WZC_BITS;
-			csr &= ~MUSB_TXCSR_P_SENTSTALL;
-			musb_writew(epio, MUSB_TXCSR, csr);
-			if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
-				dma->status = MUSB_DMA_STATUS_CORE_ABORT;
-				musb->dma_controller->channel_abort(dma);
-			}
 
-			if (request)
-				musb_g_giveback(musb_ep, request, -EPIPE);
+	/*
+	 * REVISIT: for high bandwidth, MUSB_TXCSR_P_INCOMPTX
+	 * probably rates reporting as a host error.
+	 */
+	if (csr & MUSB_TXCSR_P_SENTSTALL) {
+		csr |=	MUSB_TXCSR_P_WZC_BITS;
+		csr &= ~MUSB_TXCSR_P_SENTSTALL;
+		musb_writew(epio, MUSB_TXCSR, csr);
+		return;
+	}
+
+	if (csr & MUSB_TXCSR_P_UNDERRUN) {
+		/* We NAKed, no big deal... little reason to care. */
+		csr |=	 MUSB_TXCSR_P_WZC_BITS;
+		csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
+		musb_writew(epio, MUSB_TXCSR, csr);
+		DBG(20, "underrun on ep%d, req %p\n", epnum, request);
+	}
 
-			break;
-		}
+	if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
+		/*
+		 * SHOULD NOT HAPPEN... has with CPPI though, after
+		 * changing SENDSTALL (and other cases); harmless?
+		 */
+		DBG(5, "%s dma still busy?\n", musb_ep->end_point.name);
+		return;
+	}
 
-		if (csr & MUSB_TXCSR_P_UNDERRUN) {
-			/* we NAKed, no big deal ... little reason to care */
+	if (request) {
+		u8	is_dma = 0;
+
+		if (dma && (csr & MUSB_TXCSR_DMAENAB)) {
+			is_dma = 1;
 			csr |= MUSB_TXCSR_P_WZC_BITS;
-			csr &= ~(MUSB_TXCSR_P_UNDERRUN
-					| MUSB_TXCSR_TXPKTRDY);
+			csr &= ~(MUSB_TXCSR_DMAENAB | MUSB_TXCSR_P_UNDERRUN |
+				 MUSB_TXCSR_TXPKTRDY);
 			musb_writew(epio, MUSB_TXCSR, csr);
-			DBG(20, "underrun on ep%d, req %p\n", epnum, request);
-		}
-
-		if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
-			/* SHOULD NOT HAPPEN ... has with cppi though, after
-			 * changing SENDSTALL (and other cases); harmless?
-			 */
-			DBG(5, "%s dma still busy?\n", musb_ep->end_point.name);
-			break;
+			/* Ensure writebuffer is empty. */
+			csr = musb_readw(epio, MUSB_TXCSR);
+			request->actual += musb_ep->dma->actual_len;
+			DBG(4, "TXCSR%d %04x, DMA off, len %zu, req %p\n",
+				epnum, csr, musb_ep->dma->actual_len, request);
 		}
 
-		if (request) {
-			u8	is_dma = 0;
-
-			if (dma && (csr & MUSB_TXCSR_DMAENAB)) {
-				is_dma = 1;
-				csr |= MUSB_TXCSR_P_WZC_BITS;
-				csr &= ~(MUSB_TXCSR_DMAENAB
-						| MUSB_TXCSR_P_UNDERRUN
-						| MUSB_TXCSR_TXPKTRDY);
-				musb_writew(epio, MUSB_TXCSR, csr);
-				/* ensure writebuffer is empty */
-				csr = musb_readw(epio, MUSB_TXCSR);
-				request->actual += musb_ep->dma->actual_len;
-				DBG(4, "TXCSR%d %04x, dma off, "
-						"len %zu, req %p\n",
-					epnum, csr,
-					musb_ep->dma->actual_len,
-					request);
-			}
-
-			if (is_dma || request->actual == request->length) {
-
-				/* First, maybe a terminating short packet.
-				 * Some DMA engines might handle this by
-				 * themselves.
-				 */
-				if ((request->zero
-						&& request->length
-						&& (request->length
-							% musb_ep->packet_sz)
-							== 0)
+		/*
+		 * First, maybe a terminating short packet. Some DMA
+		 * engines might handle this by themselves.
+		 */
+		if ((request->zero && request->length
+			&& (request->length % musb_ep->packet_sz == 0)
+			&& (request->actual == request->length))
 #ifdef CONFIG_USB_INVENTRA_DMA
-					|| (is_dma &&
-						((!dma->desired_mode) ||
-						    (request->actual &
-						    (musb_ep->packet_sz - 1))))
+			|| (is_dma && (!dma->desired_mode ||
+				(request->actual &
+					(musb_ep->packet_sz - 1))))
 #endif
-				) {
-					/* on dma completion, fifo may not
-					 * be available yet ...
-					 */
-					if (csr & MUSB_TXCSR_TXPKTRDY)
-						break;
-
-					DBG(4, "sending zero pkt\n");
-					musb_writew(epio, MUSB_TXCSR,
-							MUSB_TXCSR_MODE
-							| MUSB_TXCSR_TXPKTRDY);
-					request->zero = 0;
-				}
+		) {
+			/*
+			 * On DMA completion, FIFO may not be
+			 * available yet...
+			 */
+			if (csr & MUSB_TXCSR_TXPKTRDY)
+				return;
 
-				/* ... or if not, then complete it */
-				musb_g_giveback(musb_ep, request, 0);
+			DBG(4, "sending zero pkt\n");
+			musb_writew(epio, MUSB_TXCSR, MUSB_TXCSR_MODE
+					| MUSB_TXCSR_TXPKTRDY);
+			request->zero = 0;
+		}
 
-				/* kickstart next transfer if appropriate;
-				 * the packet that just completed might not
-				 * be transmitted for hours or days.
-				 * REVISIT for double buffering...
-				 * FIXME revisit for stalls too...
-				 */
-				musb_ep_select(mbase, epnum);
-				csr = musb_readw(epio, MUSB_TXCSR);
-				if (csr & MUSB_TXCSR_FIFONOTEMPTY)
-					break;
-				request = musb_ep->desc
-						? next_request(musb_ep)
-						: NULL;
-				if (!request) {
-					DBG(4, "%s idle now\n",
-						musb_ep->end_point.name);
-					break;
-				}
+		if (request->actual == request->length) {
+			musb_g_giveback(musb_ep, request, 0);
+			request = musb_ep->desc ? next_request(musb_ep) : NULL;
+			if (!request) {
+				DBG(4, "%s idle now\n",
+					musb_ep->end_point.name);
+				return;
 			}
-
-			txstate(musb, to_musb_request(request));
 		}
 
-	} while (0);
+		txstate(musb, to_musb_request(request));
+	}
 }
 
 /* ------------------------------------------------------------ */
@@ -586,15 +602,33 @@ void musb_g_tx(struct musb *musb, u8 epnum)
  */
 static void rxstate(struct musb *musb, struct musb_request *req)
 {
-	u16			csr = 0;
 	const u8		epnum = req->epnum;
 	struct usb_request	*request = &req->request;
-	struct musb_ep		*musb_ep = &musb->endpoints[epnum].ep_out;
+	struct musb_ep		*musb_ep;
 	void __iomem		*epio = musb->endpoints[epnum].regs;
 	unsigned		fifo_count = 0;
-	u16			len = musb_ep->packet_sz;
+	u16			len;
+	u16			csr = musb_readw(epio, MUSB_RXCSR);
+	struct musb_hw_ep	*hw_ep = &musb->endpoints[epnum];
 
-	csr = musb_readw(epio, MUSB_RXCSR);
+	if (hw_ep->is_shared_fifo)
+		musb_ep = &hw_ep->ep_in;
+	else
+		musb_ep = &hw_ep->ep_out;
+
+	len = musb_ep->packet_sz;
+
+	/* We shouldn't get here while DMA is active, but we do... */
+	if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) {
+		DBG(4, "DMA pending...\n");
+		return;
+	}
+
+	if (csr & MUSB_RXCSR_P_SENDSTALL) {
+		DBG(5, "%s stalling, RXCSR %04x\n",
+		    musb_ep->end_point.name, csr);
+		return;
+	}
 
 	if (is_cppi_enabled() && musb_ep->dma) {
 		struct dma_controller	*c = musb->dma_controller;
@@ -627,7 +661,7 @@ static void rxstate(struct musb *musb, struct musb_request *req)
 		len = musb_readw(epio, MUSB_RXCOUNT);
 		if (request->actual < request->length) {
 #ifdef CONFIG_USB_INVENTRA_DMA
-			if (is_dma_capable() && musb_ep->dma && request->dma % 4 == 0) {
+			if (is_dma_capable() && musb_ep->dma) {
 				struct dma_controller	*c;
 				struct dma_channel	*channel;
 				int			use_dma = 0;
@@ -667,16 +701,21 @@ static void rxstate(struct musb *musb, struct musb_request *req)
 				 */
 				musb_writew(epio, MUSB_RXCSR,
 					csr | MUSB_RXCSR_DMAMODE);
+#else
+				if (!musb_ep->hb_mult &&
+					musb_ep->hw_ep->rx_double_buffered)
+					csr |= MUSB_RXCSR_AUTOCLEAR;
 #endif
 				musb_writew(epio, MUSB_RXCSR, csr);
 
 				if (request->actual < request->length) {
 					int transfer_size = 0;
 #ifdef USE_MODE1
-					transfer_size = min(request->length,
+					transfer_size = min(request->length - request->actual,
 							channel->max_len);
 #else
-					transfer_size = len;
+					transfer_size = min(request->length - request->actual,
+							(unsigned)len);
 #endif
 					if (transfer_size <= musb_ep->packet_sz)
 						musb_ep->dma->desired_mode = 0;
@@ -721,6 +760,21 @@ static void rxstate(struct musb *musb, struct musb_request *req)
 					return;
 			}
 #endif
+			/*
+			 * Unmap the dma buffer back to cpu if dma channel
+			 * programming fails. This buffer is mapped if the
+			 * channel allocation is successful
+			 */
+			 if (is_dma_capable() && musb_ep->dma) {
+				unmap_dma_buffer(req, musb);
+
+				/*
+				 * Clear DMAENAB and AUTOCLEAR for the
+				 * PIO mode transfer
+				 */
+				csr &= ~(MUSB_RXCSR_DMAENAB | MUSB_RXCSR_AUTOCLEAR);
+				musb_writew(epio, MUSB_RXCSR, csr);
+			}
 
 			musb_read_fifo(musb_ep->hw_ep, fifo_count, (u8 *)
 					(request->buf + request->actual));
@@ -750,13 +804,21 @@ void musb_g_rx(struct musb *musb, u8 epnum)
 	u16			csr;
 	struct usb_request	*request;
 	void __iomem		*mbase = musb->mregs;
-	struct musb_ep		*musb_ep = &musb->endpoints[epnum].ep_out;
+	struct musb_ep		*musb_ep;
 	void __iomem		*epio = musb->endpoints[epnum].regs;
 	struct dma_channel	*dma;
+	struct musb_hw_ep	*hw_ep = &musb->endpoints[epnum];
+
+	if (hw_ep->is_shared_fifo)
+		musb_ep = &hw_ep->ep_in;
+	else
+		musb_ep = &hw_ep->ep_out;
 
 	musb_ep_select(mbase, epnum);
 
 	request = next_request(musb_ep);
+	if (!request)
+		return;
 
 	csr = musb_readw(epio, MUSB_RXCSR);
 	dma = is_dma_capable() ? musb_ep->dma : NULL;
@@ -765,19 +827,10 @@ void musb_g_rx(struct musb *musb, u8 epnum)
 			csr, dma ? " (dma)" : "", request);
 
 	if (csr & MUSB_RXCSR_P_SENTSTALL) {
-		if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
-			dma->status = MUSB_DMA_STATUS_CORE_ABORT;
-			(void) musb->dma_controller->channel_abort(dma);
-			request->actual += musb_ep->dma->actual_len;
-		}
-
 		csr |= MUSB_RXCSR_P_WZC_BITS;
 		csr &= ~MUSB_RXCSR_P_SENTSTALL;
 		musb_writew(epio, MUSB_RXCSR, csr);
-
-		if (request)
-			musb_g_giveback(musb_ep, request, -EPIPE);
-		goto done;
+		return;
 	}
 
 	if (csr & MUSB_RXCSR_P_OVERRUN) {
@@ -786,7 +839,7 @@ void musb_g_rx(struct musb *musb, u8 epnum)
 		musb_writew(epio, MUSB_RXCSR, csr);
 
 		DBG(3, "%s iso overrun on %p\n", musb_ep->name, request);
-		if (request && request->status == -EINPROGRESS)
+		if (request->status == -EINPROGRESS)
 			request->status = -EOVERFLOW;
 	}
 	if (csr & MUSB_RXCSR_INCOMPRX) {
@@ -799,7 +852,7 @@ void musb_g_rx(struct musb *musb, u8 epnum)
 		DBG((csr & MUSB_RXCSR_DMAENAB) ? 4 : 1,
 			"%s busy, csr %04x\n",
 			musb_ep->end_point.name, csr);
-		goto done;
+		return;
 	}
 
 	if (dma && (csr & MUSB_RXCSR_DMAENAB)) {
@@ -818,7 +871,7 @@ void musb_g_rx(struct musb *musb, u8 epnum)
 
 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA)
 		/* Autoclear doesn't clear RxPktRdy for short packets */
-		if ((dma->desired_mode == 0)
+		if ((dma->desired_mode == 0 && !hw_ep->rx_double_buffered)
 				|| (dma->actual_len
 					& (musb_ep->packet_sz - 1))) {
 			/* ack the read! */
@@ -829,33 +882,37 @@ void musb_g_rx(struct musb *musb, u8 epnum)
 		/* incomplete, and not short? wait for next IN packet */
 		if ((request->actual < request->length)
 				&& (musb_ep->dma->actual_len
-					== musb_ep->packet_sz))
-			goto done;
+					== musb_ep->packet_sz)) {
+			/* In double buffer case, continue to unload fifo if
+ 			 * there is Rx packet in FIFO.
+ 			 **/
+			csr = musb_readw(epio, MUSB_RXCSR);
+			if ((csr & MUSB_RXCSR_RXPKTRDY) &&
+				hw_ep->rx_double_buffered)
+				goto exit;
+			return;
+		}
+#endif
+#ifdef TEST_ON_WIN7
+		{
+			extern unsigned long out_flag;
+			char *tmp = request->buf;
+			if (tmp[15] == 0x35) {
+				out_flag = 1;
+			}
+		}
 #endif
 		musb_g_giveback(musb_ep, request, 0);
 
 		request = next_request(musb_ep);
 		if (!request)
-			goto done;
-
-		/* don't start more i/o till the stall clears */
-		musb_ep_select(mbase, epnum);
-		csr = musb_readw(epio, MUSB_RXCSR);
-		if (csr & MUSB_RXCSR_P_SENDSTALL)
-			goto done;
+			return;
 	}
-
-
-	/* analyze request if the ep is hot */
-	if (request)
-		rxstate(musb, to_musb_request(request));
-	else
-		DBG(3, "packet waiting for %s%s request\n",
-				musb_ep->desc ? "" : "inactive ",
-				musb_ep->end_point.name);
-
-done:
-	return;
+#if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA)
+exit:
+#endif
+	/* Analyze request */
+	rxstate(musb, to_musb_request(request));
 }
 
 /* ------------------------------------------------------------ */
@@ -898,9 +955,25 @@ static int musb_gadget_enable(struct usb_ep *ep,
 
 	/* REVISIT this rules out high bandwidth periodic transfers */
 	tmp = le16_to_cpu(desc->wMaxPacketSize);
-	if (tmp & ~0x07ff)
-		goto fail;
-	musb_ep->packet_sz = tmp;
+	if (tmp & ~0x07ff) {
+		int ok;
+
+		if (usb_endpoint_dir_in(desc))
+			ok = musb->hb_iso_tx;
+		else
+			ok = musb->hb_iso_rx;
+
+		if (!ok) {
+			DBG(4, "%s: not support ISO high bandwidth\n", __func__);
+			goto fail;
+		}
+		musb_ep->hb_mult = (tmp >> 11) & 3;
+	} else {
+		musb_ep->hb_mult = 0;
+	}
+
+	musb_ep->packet_sz = tmp & 0x7ff;
+	tmp = musb_ep->packet_sz * (musb_ep->hb_mult + 1);
 
 	/* enable the interrupts for the endpoint, set the endpoint
 	 * packet size (or fail), set the mode, clear the fifo
@@ -913,8 +986,11 @@ static int musb_gadget_enable(struct usb_ep *ep,
 			musb_ep->is_in = 1;
 		if (!musb_ep->is_in)
 			goto fail;
-		if (tmp > hw_ep->max_packet_sz_tx)
+
+		if (tmp > hw_ep->max_packet_sz_tx) {
+			DBG(4, "%s: packet size beyond hw fifo size\n", __func__);
 			goto fail;
+		}
 
 		int_txe |= (1 << epnum);
 		musb_writew(mbase, MUSB_INTRTXE, int_txe);
@@ -922,7 +998,10 @@ static int musb_gadget_enable(struct usb_ep *ep,
 		/* REVISIT if can_bulk_split(), use by updating "tmp";
 		 * likewise high bandwidth periodic tx
 		 */
-		musb_writew(regs, MUSB_TXMAXP, tmp);
+		/* Set TXMAXP with the FIFO size of the endpoint
+		 * to disable double buffering mode.
+		 */
+		musb_writew(regs, MUSB_TXMAXP, musb_ep->packet_sz | (musb_ep->hb_mult << 11));
 
 		csr = MUSB_TXCSR_MODE | MUSB_TXCSR_CLRDATATOG;
 		if (musb_readw(regs, MUSB_TXCSR)
@@ -943,8 +1022,11 @@ static int musb_gadget_enable(struct usb_ep *ep,
 			musb_ep->is_in = 0;
 		if (musb_ep->is_in)
 			goto fail;
-		if (tmp > hw_ep->max_packet_sz_rx)
+
+		if (tmp > hw_ep->max_packet_sz_rx) {
+			DBG(4, "%s: packet size beyond hw fifo size\n", __func__);
 			goto fail;
+		}
 
 		int_rxe |= (1 << epnum);
 		musb_writew(mbase, MUSB_INTRRXE, int_rxe);
@@ -952,7 +1034,10 @@ static int musb_gadget_enable(struct usb_ep *ep,
 		/* REVISIT if can_bulk_combine() use by updating "tmp"
 		 * likewise high bandwidth periodic rx
 		 */
-		musb_writew(regs, MUSB_RXMAXP, tmp);
+		/* Set RXMAXP with the FIFO size of the endpoint
+		 * to disable double buffering mode.
+		 */
+		musb_writew(regs, MUSB_RXMAXP, musb_ep->packet_sz | (musb_ep->hb_mult << 11));
 
 		/* force shared fifo to OUT-only mode */
 		if (hw_ep->is_shared_fifo) {
@@ -985,6 +1070,7 @@ static int musb_gadget_enable(struct usb_ep *ep,
 
 	musb_ep->desc = desc;
 	musb_ep->busy = 0;
+	musb_ep->wedged = 0;
 	status = 0;
 
 	pr_debug("%s periph: enabled %s for %s %s, %smaxpacket %d\n",
@@ -1093,7 +1179,7 @@ struct free_record {
 /*
  * Context: controller locked, IRQs blocked.
  */
-static void musb_ep_restart(struct musb *musb, struct musb_request *req)
+void musb_ep_restart(struct musb *musb, struct musb_request *req)
 {
 	DBG(3, "<== %s request %p len %u on hw_ep%d\n",
 		req->tx ? "TX/IN" : "RX/OUT",
@@ -1137,28 +1223,9 @@ static int musb_gadget_queue(struct usb_ep *ep, struct usb_request *req,
 	request->epnum = musb_ep->current_epnum;
 	request->tx = musb_ep->is_in;
 
-	if (is_dma_capable() && musb_ep->dma) {
-		if (request->request.dma == DMA_ADDR_INVALID) {
-			request->request.dma = dma_map_single(
-					musb->controller,
-					request->request.buf,
-					request->request.length,
-					request->tx
-						? DMA_TO_DEVICE
-						: DMA_FROM_DEVICE);
-			request->mapped = 1;
-		} else {
-			dma_sync_single_for_device(musb->controller,
-					request->request.dma,
-					request->request.length,
-					request->tx
-						? DMA_TO_DEVICE
-						: DMA_FROM_DEVICE);
-			request->mapped = 0;
-		}
-	} else if (!req->buf) {
-		return -ENODATA;
-	} else
+	if (is_dma_capable() && musb_ep->dma)
+		map_dma_buffer(request, musb);
+	else
 		request->mapped = 0;
 
 	spin_lock_irqsave(&musb->lock, lockflags);
@@ -1239,7 +1306,7 @@ done:
  *
  * exported to ep0 code
  */
-int musb_gadget_set_halt(struct usb_ep *ep, int value)
+static int musb_gadget_set_halt(struct usb_ep *ep, int value)
 {
 	struct musb_ep		*musb_ep = to_musb_ep(ep);
 	u8			epnum = musb_ep->current_epnum;
@@ -1248,7 +1315,7 @@ int musb_gadget_set_halt(struct usb_ep *ep, int value)
 	void __iomem		*mbase;
 	unsigned long		flags;
 	u16			csr;
-	struct musb_request	*request = NULL;
+	struct musb_request	*request;
 	int			status = 0;
 
 	if (!ep)
@@ -1264,24 +1331,30 @@ int musb_gadget_set_halt(struct usb_ep *ep, int value)
 
 	musb_ep_select(mbase, epnum);
 
-	/* cannot portably stall with non-empty FIFO */
 	request = to_musb_request(next_request(musb_ep));
-	if (value && musb_ep->is_in) {
-		csr = musb_readw(epio, MUSB_TXCSR);
-		if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
-			DBG(3, "%s fifo busy, cannot halt\n", ep->name);
-			spin_unlock_irqrestore(&musb->lock, flags);
-			return -EAGAIN;
+	if (value) {
+		if (request) {
+			DBG(3, "request in progress, cannot halt %s\n",
+			    ep->name);
+			status = -EAGAIN;
+			goto done;
 		}
-
-	}
+		/* Cannot portably stall with non-empty FIFO */
+		if (musb_ep->is_in) {
+			csr = musb_readw(epio, MUSB_TXCSR);
+			if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
+				DBG(3, "FIFO busy, cannot halt %s\n", ep->name);
+				status = -EAGAIN;
+				goto done;
+			}
+		}
+	} else
+		musb_ep->wedged = 0;
 
 	/* set/clear the stall and toggle bits */
 	DBG(2, "%s: %s stall\n", ep->name, value ? "set" : "clear");
 	if (musb_ep->is_in) {
 		csr = musb_readw(epio, MUSB_TXCSR);
-		if (csr & MUSB_TXCSR_FIFONOTEMPTY)
-			csr |= MUSB_TXCSR_FLUSHFIFO;
 		csr |= MUSB_TXCSR_P_WZC_BITS
 			| MUSB_TXCSR_CLRDATATOG;
 		if (value)
@@ -1304,18 +1377,32 @@ int musb_gadget_set_halt(struct usb_ep *ep, int value)
 		musb_writew(epio, MUSB_RXCSR, csr);
 	}
 
-done:
-
 	/* maybe start the first request in the queue */
 	if (!musb_ep->busy && !value && request) {
 		DBG(3, "restarting the request\n");
 		musb_ep_restart(musb, request);
 	}
 
+done:
 	spin_unlock_irqrestore(&musb->lock, flags);
 	return status;
 }
 
+/*
+ * Sets the halt feature with the clear requests ignored
+ */
+static int musb_gadget_set_wedge(struct usb_ep *ep)
+{
+	struct musb_ep		*musb_ep = to_musb_ep(ep);
+
+	if (!ep)
+		return -EINVAL;
+
+	musb_ep->wedged = 1;
+
+	return usb_ep_set_halt(ep);
+}
+
 static int musb_gadget_fifo_status(struct usb_ep *ep)
 {
 	struct musb_ep		*musb_ep = to_musb_ep(ep);
@@ -1386,6 +1473,7 @@ static const struct usb_ep_ops musb_ep_ops = {
 	.queue		= musb_gadget_queue,
 	.dequeue	= musb_gadget_dequeue,
 	.set_halt	= musb_gadget_set_halt,
+	.set_wedge	= musb_gadget_set_wedge,
 	.fifo_status	= musb_gadget_fifo_status,
 	.fifo_flush	= musb_gadget_fifo_flush
 };
@@ -1664,13 +1752,14 @@ int __init musb_gadget_setup(struct musb *musb)
 	musb_platform_try_idle(musb, 0);
 
 	status = device_register(&musb->g.dev);
-	if (status != 0)
+	if (status != 0) {
+		put_device(&musb->g.dev);
 		the_gadget = NULL;
-
+	}
 #ifdef CONFIG_USB_MUSB_PERIPHERAL_HOTPLUG
-	status = musb_gadget_hotplug_setup(musb);
-	if (status != 0)
-		the_gadget = NULL;
+        status = musb_gadget_hotplug_setup(musb);
+        if (status != 0)
+                the_gadget = NULL;
 #endif
 
 	return status;
@@ -1685,44 +1774,44 @@ void musb_gadget_cleanup(struct musb *musb)
 	the_gadget = NULL;
 }
 
-#ifdef CONFIG_USB_MUSB_PERIPHERAL_HOTPLUG 
-static void stop_activity(struct musb *musb,  
-                struct usb_gadget_driver *driver); 
-                                                   
-static int jz_musb_vbus_hotplug_event(struct notifier_block *n,  
-                unsigned long val, void *data)                 
-{                                                              
-        struct musb *musb = the_gadget;                        
-                                                               
-        unsigned long flags; 
-                             
-        int state = *((int *)data); 
-                                    
-        D("Called.\n"); 
-                        
-        if (!musb || !musb->gadget_driver) 
-                return 0;                 
-                                          
-        switch (val) {                    
-                case UH_NOTIFY_CABLE_STATE: 
-                        switch (state) {    
-                                case UH_CABLE_STATE_OFFLINE: 
-                                case UH_CABLE_STATE_POWER:   
-                                        D("OFFLINE.\n");     
-                                                             
-                                        spin_lock_irqsave(&musb->lock, flags); 
-                                                                               
-                                        musb_gadget_vbus_draw(&musb->g, 0);    
-                                        musb->xceiv->state = OTG_STATE_UNDEFINED; 
-                                        stop_activity(musb, musb->gadget_driver); 
-                                        musb->is_active = 0;                      
-                                                                                  
-                                        spin_unlock_irqrestore(&musb->lock, flags); 
-                                                                                    
-                                        break;                                      
-                                                                                    
-                                case UH_CABLE_STATE_USB:                            
-                                        D("ONLINE.\n");                             
+#ifdef CONFIG_USB_MUSB_PERIPHERAL_HOTPLUG
+static void stop_activity(struct musb *musb,
+                struct usb_gadget_driver *driver);
+
+static int jz_musb_vbus_hotplug_event(struct notifier_block *n,
+                unsigned long val, void *data)
+{
+        struct musb *musb = the_gadget;
+
+        unsigned long flags;
+
+        int state = *((int *)data);
+
+        D("Called.\n");
+
+        if (!musb || !musb->gadget_driver)
+                return 0;
+
+        switch (val) {
+                case UH_NOTIFY_CABLE_STATE:
+                        switch (state) {
+                                case UH_CABLE_STATE_OFFLINE:
+                                case UH_CABLE_STATE_POWER:
+                                        D("OFFLINE.\n");
+
+                                        spin_lock_irqsave(&musb->lock, flags);
+
+                                        musb_gadget_vbus_draw(&musb->g, 0);
+                                        musb->xceiv->state = OTG_STATE_UNDEFINED;
+                                        stop_activity(musb, musb->gadget_driver);
+                                        musb->is_active = 0;
+
+                                        spin_unlock_irqrestore(&musb->lock, flags);
+
+                                        break;
+
+                                case UH_CABLE_STATE_USB:
+                                        D("ONLINE.\n");
 
                                         spin_lock_irqsave(&musb->lock, flags);
 
@@ -1747,6 +1836,7 @@ static struct notifier_block jz_musb_vbus_hotplug_nb = {
 };
 #endif
 
+
 /*
  * Register the gadget driver. Used by gadget drivers when
  * registering themselves with the controller.
@@ -1756,6 +1846,7 @@ static struct notifier_block jz_musb_vbus_hotplug_nb = {
  * -ENOMEM no memeory to perform the operation
  *
  * @param driver the gadget driver
+ * @param bind the driver's bind function
  * @return <0 if error, 0 if everything is fine
  */
 int usb_gadget_register_driver(struct usb_gadget_driver *driver)
@@ -1809,8 +1900,8 @@ int usb_gadget_register_driver(struct usb_gadget_driver *driver)
 #ifdef CONFIG_USB_MUSB_PERIPHERAL_HOTPLUG
                 uh_register_notifier(&jz_musb_vbus_hotplug_nb);
 #else
-
 		otg_set_peripheral(musb->xceiv, &musb->g);
+		musb->xceiv->state = OTG_STATE_B_IDLE;
 		musb->is_active = 1;
 
 		/* FIXME this ignores the softconnect flag.  Drivers are
@@ -1828,6 +1919,7 @@ int usb_gadget_register_driver(struct usb_gadget_driver *driver)
 		spin_unlock_irqrestore(&musb->lock, flags);
 
 		if (is_otg_enabled(musb)) {
+
 			DBG(3, "OTG startup...\n");
 
 			/* REVISIT:  funcall to other code, which also
diff --git a/drivers/usb/musb/musb_gadget.h b/drivers/usb/musb/musb_gadget.h
index 59502da9f73..dec8dc00819 100644
--- a/drivers/usb/musb/musb_gadget.h
+++ b/drivers/usb/musb/musb_gadget.h
@@ -75,8 +75,12 @@ struct musb_ep {
 	/* later things are modified based on usage */
 	struct list_head		req_list;
 
+	u8				wedged;
+
 	/* true if lock must be dropped but req_list may not be advanced */
 	u8				busy;
+
+	u8				hb_mult;
 };
 
 static inline struct musb_ep *to_musb_ep(struct usb_ep *ep)
@@ -103,6 +107,6 @@ extern void musb_gadget_cleanup(struct musb *);
 
 extern void musb_g_giveback(struct musb_ep *, struct usb_request *, int);
 
-extern int musb_gadget_set_halt(struct usb_ep *ep, int value);
+extern void musb_ep_restart(struct musb *, struct musb_request *);
 
 #endif		/* __MUSB_GADGET_H */
diff --git a/drivers/usb/musb/musb_gadget_ep0.c b/drivers/usb/musb/musb_gadget_ep0.c
index 7a6778675ad..6dd03f4c5f4 100644
--- a/drivers/usb/musb/musb_gadget_ep0.c
+++ b/drivers/usb/musb/musb_gadget_ep0.c
@@ -199,7 +199,6 @@ service_in_request(struct musb *musb, const struct usb_ctrlrequest *ctrlrequest)
 static void musb_g_ep0_giveback(struct musb *musb, struct usb_request *req)
 {
 	musb_g_giveback(&musb->endpoints[0].ep_in, req, 0);
-	musb->ep0_state = MUSB_EP0_STAGE_SETUP;
 }
 
 /*
@@ -258,30 +257,62 @@ __acquires(musb->lock)
 			case USB_RECIP_INTERFACE:
 				break;
 			case USB_RECIP_ENDPOINT:{
-				const u8 num = ctrlrequest->wIndex & 0x0f;
-				struct musb_ep *musb_ep;
+				const u8		epnum =
+					ctrlrequest->wIndex & 0x0f;
+				struct musb_ep		*musb_ep;
+				struct musb_hw_ep	*ep;
+				struct musb_request	*request;
+				void __iomem		*regs;
+				int			is_in;
+				u16			csr;
 
-				if (num == 0
-						|| num >= MUSB_C_NUM_EPS
-						|| ctrlrequest->wValue
-							!= USB_ENDPOINT_HALT)
+				if (epnum == 0 || epnum >= MUSB_C_NUM_EPS ||
+				    ctrlrequest->wValue != USB_ENDPOINT_HALT)
 					break;
 
-				if (ctrlrequest->wIndex & USB_DIR_IN)
-					musb_ep = &musb->endpoints[num].ep_in;
+				ep = musb->endpoints + epnum;
+				regs = ep->regs;
+				is_in = ctrlrequest->wIndex & USB_DIR_IN;
+				if (is_in)
+					musb_ep = &ep->ep_in;
 				else
-					musb_ep = &musb->endpoints[num].ep_out;
+					musb_ep = &ep->ep_out;
 				if (!musb_ep->desc)
 					break;
 
-				/* REVISIT do it directly, no locking games */
-				spin_unlock(&musb->lock);
-				musb_gadget_set_halt(&musb_ep->end_point, 0);
-				spin_lock(&musb->lock);
+				handled = 1;
+				/* Ignore request if endpoint is wedged */
+				if (musb_ep->wedged)
+					break;
+
+				musb_ep_select(mbase, epnum);
+				if (is_in) {
+					csr  = musb_readw(regs, MUSB_TXCSR);
+					csr |= MUSB_TXCSR_CLRDATATOG |
+					       MUSB_TXCSR_P_WZC_BITS;
+					csr &= ~(MUSB_TXCSR_P_SENDSTALL |
+						 MUSB_TXCSR_P_SENTSTALL |
+						 MUSB_TXCSR_TXPKTRDY);
+					musb_writew(regs, MUSB_TXCSR, csr);
+				} else {
+					csr  = musb_readw(regs, MUSB_RXCSR);
+					csr |= MUSB_RXCSR_CLRDATATOG |
+					       MUSB_RXCSR_P_WZC_BITS;
+					csr &= ~(MUSB_RXCSR_P_SENDSTALL |
+						 MUSB_RXCSR_P_SENTSTALL);
+					musb_writew(regs, MUSB_RXCSR, csr);
+				}
+
+				/* Maybe start the first request in the queue */
+				request = to_musb_request(
+						next_request(musb_ep));
+				if (!musb_ep->busy && request) {
+					DBG(3, "restarting the request\n");
+					musb_ep_restart(musb, request);
+				}
 
 				/* select ep0 again */
 				musb_ep_select(mbase, 0);
-				handled = 1;
 				} break;
 			default:
 				/* class, vendor, etc ... delegate */
@@ -329,6 +360,31 @@ __acquires(musb->lock)
 						musb->test_mode_nr =
 							MUSB_TEST_PACKET;
 						break;
+
+					case 0xc0:
+						/* TEST_FORCE_HS */
+						pr_debug("TEST_FORCE_HS\n");
+						musb->test_mode_nr =
+							MUSB_TEST_FORCE_HS;
+						break;
+					case 0xc1:
+						/* TEST_FORCE_FS */
+						pr_debug("TEST_FORCE_FS\n");
+						musb->test_mode_nr =
+							MUSB_TEST_FORCE_FS;
+						break;
+					case 0xc2:
+						/* TEST_FIFO_ACCESS */
+						pr_debug("TEST_FIFO_ACCESS\n");
+						musb->test_mode_nr =
+							MUSB_TEST_FIFO_ACCESS;
+						break;
+					case 0xc3:
+						/* TEST_FORCE_HOST */
+						pr_debug("TEST_FORCE_HOST\n");
+						musb->test_mode_nr =
+							MUSB_TEST_FORCE_HOST;
+						break;
 					default:
 						goto stall;
 					}
@@ -355,6 +411,9 @@ __acquires(musb->lock)
 					musb->g.a_alt_hnp_support = 1;
 					break;
 #endif
+				case USB_DEVICE_DEBUG_MODE:
+					handled = 0;
+					break;
 stall:
 				default:
 					handled = -EINVAL;
@@ -374,10 +433,8 @@ stall:
 				int			is_in;
 				u16			csr;
 
-				if (epnum == 0
-						|| epnum >= MUSB_C_NUM_EPS
-						|| ctrlrequest->wValue
-							!= USB_ENDPOINT_HALT)
+				if (epnum == 0 || epnum >= MUSB_C_NUM_EPS ||
+				    ctrlrequest->wValue	!= USB_ENDPOINT_HALT)
 					break;
 
 				ep = musb->endpoints + epnum;
@@ -392,24 +449,20 @@ stall:
 
 				musb_ep_select(mbase, epnum);
 				if (is_in) {
-					csr = musb_readw(regs,
-							MUSB_TXCSR);
+					csr = musb_readw(regs, MUSB_TXCSR);
 					if (csr & MUSB_TXCSR_FIFONOTEMPTY)
 						csr |= MUSB_TXCSR_FLUSHFIFO;
 					csr |= MUSB_TXCSR_P_SENDSTALL
 						| MUSB_TXCSR_CLRDATATOG
 						| MUSB_TXCSR_P_WZC_BITS;
-					musb_writew(regs, MUSB_TXCSR,
-							csr);
+					musb_writew(regs, MUSB_TXCSR, csr);
 				} else {
-					csr = musb_readw(regs,
-							MUSB_RXCSR);
+					csr = musb_readw(regs, MUSB_RXCSR);
 					csr |= MUSB_RXCSR_P_SENDSTALL
 						| MUSB_RXCSR_FLUSHFIFO
 						| MUSB_RXCSR_CLRDATATOG
 						| MUSB_RXCSR_P_WZC_BITS;
-					musb_writew(regs, MUSB_RXCSR,
-							csr);
+					musb_writew(regs, MUSB_RXCSR, csr);
 				}
 
 				/* select ep0 again */
@@ -511,7 +564,8 @@ static void ep0_txstate(struct musb *musb)
 
 	/* update the flags */
 	if (fifo_count < MUSB_MAX_END0_PACKET
-			|| request->actual == request->length) {
+			|| (request->actual == request->length
+				&& !request->zero)) {
 		musb->ep0_state = MUSB_EP0_STAGE_STATUSOUT;
 		csr |= MUSB_CSR0_P_DATAEND;
 	} else
@@ -647,7 +701,7 @@ irqreturn_t musb_g_ep0_irq(struct musb *musb)
 			musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;
 			break;
 		default:
-			ERR("SetupEnd came in a wrong ep0stage %s",
+			ERR("SetupEnd came in a wrong ep0stage %s\n",
 			    decode_ep0stage(musb->ep0_state));
 		}
 		csr = musb_readw(regs, MUSB_CSR0);
@@ -770,12 +824,18 @@ setup:
 				handled = service_zero_data_request(
 						musb, &setup);
 
+				/*
+				 * We're expecting no data in any case, so
+				 * always set the DATAEND bit -- doing this
+				 * here helps avoid SetupEnd interrupt coming
+				 * in the idle stage when we're stalling...
+				 */
+				musb->ackpend |= MUSB_CSR0_P_DATAEND;
+
 				/* status stage might be immediate */
-				if (handled > 0) {
-					musb->ackpend |= MUSB_CSR0_P_DATAEND;
+				if (handled > 0)
 					musb->ep0_state =
 						MUSB_EP0_STAGE_STATUSIN;
-				}
 				break;
 
 			/* sequence #1 (IN to host), includes GET_STATUS
diff --git a/drivers/usb/musb/musb_io.h b/drivers/usb/musb/musb_io.h
index 108d7e07c3e..faef6504719 100644
--- a/drivers/usb/musb/musb_io.h
+++ b/drivers/usb/musb/musb_io.h
@@ -37,9 +37,10 @@
 
 #include <linux/io.h>
 
-#if !defined(CONFIG_ARM) && !defined(CONFIG_SUPERH) \
-	&& !defined(CONFIG_AVR32) && !defined(CONFIG_PPC32) \
-	&& !defined(CONFIG_PPC64) && !defined(CONFIG_BLACKFIN) && !defined(CONFIG_SOC_JZ4760)
+#if !defined(CONFIG_ARM) && !defined(CONFIG_SUPERH)			\
+	&& !defined(CONFIG_AVR32) && !defined(CONFIG_PPC32)		\
+	&& !defined(CONFIG_PPC64) && !defined(CONFIG_BLACKFIN)		\
+	&& !defined(CONFIG_SOC_JZ4760) && !defined(CONFIG_SOC_JZ4760B)
 static inline void readsl(const void __iomem *addr, void *buf, int len)
 	{ insl((unsigned long)addr, buf, len); }
 static inline void readsw(const void __iomem *addr, void *buf, int len)
diff --git a/drivers/usb/musb/musb_regs.h b/drivers/usb/musb/musb_regs.h
index fbfd3fd9ce1..5a727c5b867 100644
--- a/drivers/usb/musb/musb_regs.h
+++ b/drivers/usb/musb/musb_regs.h
@@ -72,6 +72,14 @@
 #define MUSB_DEVCTL_HR		0x02
 #define MUSB_DEVCTL_SESSION	0x01
 
+/* MUSB ULPI VBUSCONTROL */
+#define MUSB_ULPI_USE_EXTVBUS	0x01
+#define MUSB_ULPI_USE_EXTVBUSIND 0x02
+/* ULPI_REG_CONTROL */
+#define MUSB_ULPI_REG_REQ	(1 << 0)
+#define MUSB_ULPI_REG_CMPLT	(1 << 1)
+#define MUSB_ULPI_RDN_WR	(1 << 2)
+
 /* TESTMODE */
 #define MUSB_TEST_FORCE_HOST	0x80
 #define MUSB_TEST_FIFO_ACCESS	0x40
@@ -246,6 +254,13 @@
 
 /* REVISIT: vctrl/vstatus: optional vendor utmi+phy register at 0x68 */
 #define MUSB_HWVERS		0x6C	/* 8 bit */
+#define MUSB_ULPI_BUSCONTROL	0x70	/* 8 bit */
+#define MUSB_ULPI_INT_MASK	0x72	/* 8 bit */
+#define MUSB_ULPI_INT_SRC	0x73	/* 8 bit */
+#define MUSB_ULPI_REG_DATA	0x74	/* 8 bit */
+#define MUSB_ULPI_REG_ADDR	0x75	/* 8 bit */
+#define MUSB_ULPI_REG_CONTROL	0x76	/* 8 bit */
+#define MUSB_ULPI_RAW_DATA	0x77	/* 8 bit */
 
 #define MUSB_EPINFO		0x78	/* 8 bit */
 #define MUSB_RAMINFO		0x79	/* 8 bit */
@@ -321,6 +336,36 @@ static inline void  musb_write_rxfifoadd(void __iomem *mbase, u16 c_off)
 	musb_writew(mbase, MUSB_RXFIFOADD, c_off);
 }
 
+static inline void musb_write_ulpi_buscontrol(void __iomem *mbase, u8 val)
+{
+	musb_writeb(mbase, MUSB_ULPI_BUSCONTROL, val);
+}
+
+static inline u8 musb_read_txfifosz(void __iomem *mbase)
+{
+	return musb_readb(mbase, MUSB_TXFIFOSZ);
+}
+
+static inline u16 musb_read_txfifoadd(void __iomem *mbase)
+{
+	return musb_readw(mbase, MUSB_TXFIFOADD);
+}
+
+static inline u8 musb_read_rxfifosz(void __iomem *mbase)
+{
+	return musb_readb(mbase, MUSB_RXFIFOSZ);
+}
+
+static inline u16  musb_read_rxfifoadd(void __iomem *mbase)
+{
+	return musb_readw(mbase, MUSB_RXFIFOADD);
+}
+
+static inline u8 musb_read_ulpi_buscontrol(void __iomem *mbase)
+{
+	return musb_readb(mbase, MUSB_ULPI_BUSCONTROL);
+}
+
 static inline u8 musb_read_configdata(void __iomem *mbase)
 {
 	musb_writeb(mbase, MUSB_INDEX, 0);
@@ -376,6 +421,36 @@ static inline void  musb_write_txhubport(void __iomem *mbase, u8 epnum,
 			qh_h_port_reg);
 }
 
+static inline u8 musb_read_rxfunaddr(void __iomem *mbase, u8 epnum)
+{
+	return musb_readb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_RXFUNCADDR));
+}
+
+static inline u8 musb_read_rxhubaddr(void __iomem *mbase, u8 epnum)
+{
+	return musb_readb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_RXHUBADDR));
+}
+
+static inline u8 musb_read_rxhubport(void __iomem *mbase, u8 epnum)
+{
+	return musb_readb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_RXHUBPORT));
+}
+
+static inline u8  musb_read_txfunaddr(void __iomem *mbase, u8 epnum)
+{
+	return musb_readb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXFUNCADDR));
+}
+
+static inline u8  musb_read_txhubaddr(void __iomem *mbase, u8 epnum)
+{
+	return musb_readb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXHUBADDR));
+}
+
+static inline u8  musb_read_txhubport(void __iomem *mbase, u8 epnum)
+{
+	return musb_readb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXHUBPORT));
+}
+
 #else /* CONFIG_BLACKFIN */
 
 #define USB_BASE		USB_FADDR
@@ -436,18 +511,9 @@ static inline void  musb_write_txhubport(void __iomem *mbase, u8 epnum,
 #define MUSB_FLAT_OFFSET(_epnum, _offset)	\
 	(USB_OFFSET(USB_EP_NI0_TXMAXP) + (0x40 * (_epnum)) + (_offset))
 
-/* Not implemented - HW has seperate Tx/Rx FIFO */
+/* Not implemented - HW has separate Tx/Rx FIFO */
 #define MUSB_TXCSR_MODE			0x0000
 
-/*
- * Dummy stub for clk framework, it will be removed
- * until Blackfin supports clk framework
- */
-#define clk_get(dev, id)	NULL
-#define clk_put(clock)		do {} while (0)
-#define clk_enable(clock)	do {} while (0)
-#define clk_disable(clock)	do {} while (0)
-
 static inline void musb_write_txfifosz(void __iomem *mbase, u8 c_size)
 {
 }
@@ -464,21 +530,54 @@ static inline void  musb_write_rxfifoadd(void __iomem *mbase, u16 c_off)
 {
 }
 
-static inline u8 musb_read_configdata(void __iomem *mbase)
+static inline void musb_write_ulpi_buscontrol(void __iomem *mbase, u8 val)
+{
+}
+
+static inline u8 musb_read_txfifosz(void __iomem *mbase)
 {
 	return 0;
 }
 
-static inline u16 musb_read_hwvers(void __iomem *mbase)
+static inline u16 musb_read_txfifoadd(void __iomem *mbase)
 {
 	return 0;
 }
 
-static inline u16 musb_read_target_reg_base(u8 i, void __iomem *mbase)
+static inline u8 musb_read_rxfifosz(void __iomem *mbase)
 {
 	return 0;
 }
 
+static inline u16  musb_read_rxfifoadd(void __iomem *mbase)
+{
+	return 0;
+}
+
+static inline u8 musb_read_ulpi_buscontrol(void __iomem *mbase)
+{
+	return 0;
+}
+
+static inline u8 musb_read_configdata(void __iomem *mbase)
+{
+	return 0;
+}
+
+static inline u16 musb_read_hwvers(void __iomem *mbase)
+{
+	/*
+	 * This register is invisible on Blackfin, actually the MUSB
+	 * RTL version of Blackfin is 1.9, so just harcode its value.
+	 */
+	return MUSB_HWVERS_1900;
+}
+
+static inline void __iomem *musb_read_target_reg_base(u8 i, void __iomem *mbase)
+{
+	return NULL;
+}
+
 static inline void musb_write_rxfunaddr(void __iomem *ep_target_regs,
 		u8 qh_addr_req)
 {
@@ -509,6 +608,36 @@ static inline void  musb_write_txhubport(void __iomem *mbase, u8 epnum,
 {
 }
 
+static inline u8 musb_read_rxfunaddr(void __iomem *mbase, u8 epnum)
+{
+	return 0;
+}
+
+static inline u8 musb_read_rxhubaddr(void __iomem *mbase, u8 epnum)
+{
+	return 0;
+}
+
+static inline u8 musb_read_rxhubport(void __iomem *mbase, u8 epnum)
+{
+	return 0;
+}
+
+static inline u8  musb_read_txfunaddr(void __iomem *mbase, u8 epnum)
+{
+	return 0;
+}
+
+static inline u8  musb_read_txhubaddr(void __iomem *mbase, u8 epnum)
+{
+	return 0;
+}
+
+static inline u8 musb_read_txhubport(void __iomem *mbase, u8 epnum)
+{
+	return 0;
+}
+
 #endif /* CONFIG_BLACKFIN */
 
 #endif	/* __MUSB_REGS_H__ */
diff --git a/drivers/usb/musb/musbhsdma.c b/drivers/usb/musb/musbhsdma.c
index 5c597189942..e17c71682ba 100644
--- a/drivers/usb/musb/musbhsdma.c
+++ b/drivers/usb/musb/musbhsdma.c
@@ -33,9 +33,11 @@
 #include <linux/device.h>
 #include <linux/interrupt.h>
 #include <linux/platform_device.h>
+#include <linux/slab.h>
 #include "musb_core.h"
 #include "musbhsdma.h"
 
+
 static int dma_controller_start(struct dma_controller *c)
 {
 	/* nothing to do */
@@ -90,7 +92,7 @@ static struct dma_channel *dma_channel_allocate(struct dma_controller *c,
 			channel = &(musb_channel->channel);
 			channel->private_data = musb_channel;
 			channel->status = MUSB_DMA_STATUS_FREE;
-			channel->max_len = 0x10000;
+			channel->max_len = 0x100000;
 			/* Tx => mode 1; Rx => mode 0 */
 			channel->desired_mode = transmit;
 			channel->actual_len = 0;
@@ -131,18 +133,9 @@ static void configure_channel(struct dma_channel *channel,
 	if (mode) {
 		csr |= 1 << MUSB_HSDMA_MODE1_SHIFT;
 		BUG_ON(len < packet_sz);
-
-		if (packet_sz >= 64) {
-			csr |= MUSB_HSDMA_BURSTMODE_INCR16
-					<< MUSB_HSDMA_BURSTMODE_SHIFT;
-		} else if (packet_sz >= 32) {
-			csr |= MUSB_HSDMA_BURSTMODE_INCR8
-					<< MUSB_HSDMA_BURSTMODE_SHIFT;
-		} else if (packet_sz >= 16) {
-			csr |= MUSB_HSDMA_BURSTMODE_INCR4
-					<< MUSB_HSDMA_BURSTMODE_SHIFT;
-		}
 	}
+	csr |= MUSB_HSDMA_BURSTMODE_INCR16
+				<< MUSB_HSDMA_BURSTMODE_SHIFT;
 
 	csr |= (musb_channel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT)
 		| (1 << MUSB_HSDMA_ENABLE_SHIFT)
@@ -166,6 +159,8 @@ static int dma_channel_program(struct dma_channel *channel,
 				dma_addr_t dma_addr, u32 len)
 {
 	struct musb_dma_channel *musb_channel = channel->private_data;
+	struct musb_dma_controller *controller = musb_channel->controller;
+	struct musb *musb = controller->private_data;
 
 	DBG(2, "ep%d-%s pkt_sz %d, dma_addr 0x%x length %d, mode %d\n",
 		musb_channel->epnum,
@@ -175,16 +170,25 @@ static int dma_channel_program(struct dma_channel *channel,
 	BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN ||
 		channel->status == MUSB_DMA_STATUS_BUSY);
 
+	/*
+	 * The DMA engine in RTL1.8 and above cannot handle
+	 * DMA addresses that are not aligned to a 4 byte boundary.
+	 * It ends up masking the last two bits of the address
+	 * programmed in DMA_ADDR.
+	 *
+	 * Fail such DMA transfers, so that the backup PIO mode
+	 * can carry out the transfer
+	 */
+	if ((musb->hwvers >= MUSB_HWVERS_1800) && (dma_addr % 4))
+		return false;
+
 	channel->actual_len = 0;
 	musb_channel->start_addr = dma_addr;
 	musb_channel->len = len;
 	musb_channel->max_packet_sz = packet_sz;
 	channel->status = MUSB_DMA_STATUS_BUSY;
 
-	if ((mode == 1) && (len >= packet_sz))
-		configure_channel(channel, packet_sz, 1, dma_addr, len);
-	else
-		configure_channel(channel, packet_sz, 0, dma_addr, len);
+	configure_channel(channel, packet_sz, mode, dma_addr, len);
 
 	return true;
 }
@@ -234,7 +238,7 @@ static int dma_channel_abort(struct dma_channel *channel)
 	return 0;
 }
 
-irqreturn_t dma_controller_irq(int irq, void *private_data)
+static irqreturn_t dma_controller_irq(int irq, void *private_data)
 {
 	struct musb_dma_controller *controller = private_data;
 	struct musb *musb = controller->private_data;
@@ -250,25 +254,54 @@ irqreturn_t dma_controller_irq(int irq, void *private_data)
 	u8 bchannel;
 	u8 int_hsdma;
 
-	u32 addr;
+	u32 addr, count;
 	u16 csr;
 
+
 	if (!musb->b_dma_share_usb_irq) {
 		spin_lock_irqsave(&musb->lock, flags);
 
 		int_hsdma = musb_readb(mbase, MUSB_HSDMA_INTR);
-	}else{
+	} else
 		int_hsdma = controller->controller.int_hsdma;
-	}
 
-	if (!int_hsdma)
-		goto done;
+#ifdef CONFIG_BLACKFIN
+	/* Clear DMA interrupt flags */
+	musb_writeb(mbase, MUSB_HSDMA_INTR, int_hsdma);
+#endif
+
+	if (!int_hsdma) {
+		DBG(2, "spurious DMA irq\n");
+
+		for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
+			musb_channel = (struct musb_dma_channel *)
+					&(controller->channel[bchannel]);
+			channel = &musb_channel->channel;
+			if (channel->status == MUSB_DMA_STATUS_BUSY) {
+				count = musb_read_hsdma_count(mbase, bchannel);
+
+				if (count == 0)
+					int_hsdma |= (1 << bchannel);
+			}
+		}
+
+		DBG(2, "int_hsdma = 0x%x\n", int_hsdma);
+
+		if (!int_hsdma)
+			goto done;
+	}
 
 	for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
 		if (int_hsdma & (1 << bchannel)) {
 			musb_channel = (struct musb_dma_channel *)
 					&(controller->channel[bchannel]);
 			channel = &musb_channel->channel;
+#ifdef TEST_ON_WIN7
+	extern unsigned long out_flag;
+	if (out_flag && channel == 2)
+		out_flag = 0;
+#endif
+
 
 			csr = musb_readw(mbase,
 					MUSB_HSDMA_CHANNEL_OFFSET(bchannel,
@@ -285,7 +318,7 @@ irqreturn_t dma_controller_irq(int irq, void *private_data)
 				channel->actual_len = addr
 					- musb_channel->start_addr;
 
-				DBG(2, "ch %p, 0x%x -> 0x%x (%d / %d) %s\n",
+				DBG(2, "ch %p, 0x%x -> 0x%x (%zu / %d) %s\n",
 					channel, musb_channel->start_addr,
 					addr, channel->actual_len,
 					musb_channel->len,
@@ -329,16 +362,10 @@ irqreturn_t dma_controller_irq(int irq, void *private_data)
 		}
 	}
 
-#ifdef CONFIG_BLACKFIN
-	/* Clear DMA interrup flags */
-	musb_writeb(mbase, MUSB_HSDMA_INTR, int_hsdma);
-#endif
-
 	retval = IRQ_HANDLED;
 done:
-	if (!musb->b_dma_share_usb_irq) 
+	if (!musb->b_dma_share_usb_irq)
 		spin_unlock_irqrestore(&musb->lock, flags);
-
 	return retval;
 }
 
@@ -377,11 +404,11 @@ dma_controller_create(struct musb *musb, void __iomem *base)
 		dev_info(dev, "DMA IRQ: Shared. DMA Channels: %d.\n", nr_dma_channel);
 	}else{
 		irq = platform_get_irq(pdev, 1);
+
 		if (irq == 0) {
 			dev_err(dev, "No DMA interrupt line!\n");
 			return NULL;
 		}
-
 		dev_info(dev, "DMA IRQ: %d. DMA Channels: %d.\n", irq, nr_dma_channel);
 	}
 	/* End modified */
@@ -401,10 +428,9 @@ dma_controller_create(struct musb *musb, void __iomem *base)
 	controller->controller.channel_program = dma_channel_program;
 	controller->controller.channel_abort = dma_channel_abort;
 
-	/* Modified by River - DMA Share IRQ with USB. */
 	if (irq) {
 		if (request_irq(irq, dma_controller_irq, IRQF_DISABLED,
-					dev_name(musb->controller), &controller->controller)) {
+				dev_name(musb->controller), &controller->controller)) {
 			dev_err(dev, "request_irq %d failed!\n", irq);
 			dma_controller_destroy(&controller->controller);
 
diff --git a/drivers/usb/musb/musbhsdma.h b/drivers/usb/musb/musbhsdma.h
index 1299d92dc83..f763d62f151 100644
--- a/drivers/usb/musb/musbhsdma.h
+++ b/drivers/usb/musb/musbhsdma.h
@@ -55,6 +55,10 @@
 		    MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS), \
 		    addr)
 
+#define musb_read_hsdma_count(mbase, bchannel)	\
+	musb_readl(mbase,	\
+		   MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT))
+
 #define musb_write_hsdma_count(mbase, bchannel, len) \
 	musb_writel(mbase, \
 		    MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT), \
@@ -96,15 +100,18 @@ static inline void musb_write_hsdma_addr(void __iomem *mbase,
 		((u16)(((u32) dma_addr >> 16) & 0xFFFF)));
 }
 
+static inline u32 musb_read_hsdma_count(void __iomem *mbase, u8 bchannel)
+{
+	return musb_readl(mbase,
+		MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT_HIGH));
+}
+
 static inline void musb_write_hsdma_count(void __iomem *mbase,
 				u8 bchannel, u32 len)
 {
-	musb_writew(mbase,
-		MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT_LOW),
-		((u16)((u32) len & 0xFFFF)));
-	musb_writew(mbase,
+	musb_writel(mbase,
 		MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT_HIGH),
-		((u16)(((u32) len >> 16) & 0xFFFF)));
+		len);
 }
 
 #endif /* CONFIG_BLACKFIN */
diff --git a/drivers/usb/musb/vbus_hotplug.c b/drivers/usb/musb/vbus_hotplug.c
index eb7fe0ad9f5..20a17282c9c 100644
--- a/drivers/usb/musb/vbus_hotplug.c
+++ b/drivers/usb/musb/vbus_hotplug.c
@@ -196,7 +196,7 @@ static void cable_detect(struct uh_data *uh)
 /* USB is active ? */
 static int usb_is_active(void)
 {
-	unsigned long timeout = NR_UDC_WAIT_INTR_LOOP;	
+	unsigned volatile long timeout = NR_UDC_WAIT_INTR_LOOP;	
 	unsigned long frame_no = REG16(USB_REG_FRAME);
 
 	/* 
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 4d600b21503..8cd6b903e4e 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -502,7 +502,7 @@ endchoice
 
 config FB_JZ4760_LCD
 	tristate "JZ4760 LCD Controller support"
-	depends on FB_JZSOC && (SOC_JZ4760)
+	depends on FB_JZSOC && (SOC_JZ4760 || SOC_JZ4760B)
 	---help---
 	   JZ4760 LCD Controller driver.
 	   JZ4760 LCD Controller support OSD function(refer jz4760_lcdc_spec.pdf).JZ4760 LCD OSD implement 2 framebuffer layers: foreground0 and foreground1. JZ4760 LCD driver support only foreground0 default.
@@ -518,6 +518,11 @@ config FB_JZ4760_TVE
 	tristate "JZ4760 TV Encode support"
 	depends on FB_JZSOC && FB_JZ4760_LCD
 	default n
+	
+config JZ4760_HDMI_DISPLAY
+	tristate "HDMI display support"	
+	depends on FB_JZSOC && FB_JZ4760_LCD
+	default n
 
 config JZ4760_IPU_MM
 	tristate "JZ4760 IPU MM support"
@@ -571,14 +576,103 @@ config JZ4760_SLCD_KGM701A3_TFT_SPFD5420A
 	select FB_JZ4750_SLCD
 
 config JZ4760_VGA_DISPLAY
-	depends on SOC_JZ4760
+	depends on SOC_JZ4760 || SOC_JZ4760B
 	bool "Jz4760 VGA Display"
 endchoice
 
+config JZ4810_AOSD
+        bool "JZ4810 osd alpha blending support."
+	depends on FB_JZSOC && (SOC_JZ4810)
+	default n
+	---help---
+		JZ4810 ALPHA OSD driver,if you use compress founction,this should not be selected.
+
+config JZ4810_COMPRESS
+        bool "JZ4810 COMPRESS  support."
+	depends on FB_JZSOC && (SOC_JZ4810)
+	default n
+	---help---
+		JZ4810 compress driver,if you use alpha osd founction,this should not be selected.
+
+config FB_JZ4810_LCD
+	tristate "JZ4810 LCD Controller support"
+	depends on FB_JZSOC && (SOC_JZ4810)
+	---help---
+	   JZ4810 LCD Controller driver.
+	   JZ4810 LCD Controller support OSD function(refer jz4810_lcdc_spec.pdf).JZ4810 LCD OSD implement 2 framebuffer layers: foreground0 and foreground1. JZ4810 LCD driver support only foreground0 default.
+
+config FB_JZ4810_LCD_USE_2LAYER_FRAMEBUFFER
+	bool "JZ4810 LCD driver 2 layers framebuffer support."
+	depends on FB_JZ4810_LCD
+	---help---
+	   JZ4810 LCD driver support only foreground0 by default.
+	   If you need both foreground0 and foreground1, please select this.
+
+config FB_JZ4810_TVE
+	tristate "JZ4810 TV Encode support"
+	depends on FB_JZSOC && FB_JZ4810_LCD
+	default n
+
+config JZ4810_IPU_MM
+	tristate "JZ4810 IPU MM support"
+	depends on FB_JZSOC && FB_JZ4810_LCD
+	default y
+	---help---
+	   Enable IPU Memory Management system. 
+	   It will reserve 16MB / 16MB + 4MB as IPU Framebuffer on JZ4750 / JZ4755. 
+	   Enable this if you want to use IPU.
+
+config FB_JZ4810_SLCD
+	bool
+	depends on FB_JZ4810_LCD
+	default n
+choice
+	depends on FB_JZ4810_LCD
+	prompt "JZ4810 LCD Panels Support"
+	default JZ4810_LCD_SAMSUNG_LTP400WQF02
+	---help---
+	   Please select the lcd panel in you board
+
+config JZ4810_LCD_SAMSUNG_LTP400WQF01
+	bool "SAMSUNG LTP400WQF01 TFT panel (480x272)(16bits)"
+
+config JZ4810_LCD_SAMSUNG_LTP400WQF02
+	bool "SAMSUNG LTP400WQF02 TFT panel (480x272)(18bits)"
+
+config JZ4810_LCD_AUO_A043FL01V2
+	bool "AUO A043FL01V2 TFT panel (480x272)(24bits)"
+
+config JZ4810_LCD_FOXCONN_PT035TN01
+     	bool "FOXCONN PT035TN01 TFT panel (320x240,3.5in)(18bit-parallel mode)"
+
+config JZ4810_LCD_INNOLUX_PT035TN01_SERIAL
+     	bool "INNOLUX PT035TN01 TFT panel (320x240,3.5in)(8bit-serial mode)"
+
+config JZ4810_LCD_TOPPOLY_TD025THEA7_RGB_DELTA
+	bool "TOPPOLY_TD025THEA7 TFT panel(320x240)(serial RGB delta mode)"
+
+config JZ4810_LCD_TOPPOLY_TD043MGEB1
+	bool "TOPPOLY_TD043MGEB1 TFT panel(800x480)(24bit mode)"
+
+config JZ4810_LCD_TRULY_TFTG320240DTSW_18BIT
+	bool "TRULY_TFTG320240DTSW TFT panel (320x240) (Parallel 18bit mode)"
+
+config JZ4810_LCD_TRULY_TFT_GG1P0319LTSW_W
+	bool "TRULY_TFT_GG1P0319LTSW_W (240x320) (Smart LCD 16bit)"
+
+config JZ4810_SLCD_KGM701A3_TFT_SPFD5420A
+	bool "KGM701A3_TFT_SPFD5420A (400x240) (Smart LCD 18bit)"
+	select FB_JZ4750_SLCD
+
+config JZ4810_VGA_DISPLAY
+	depends on SOC_JZ4810
+	bool "Jz4810 VGA Display"
+endchoice
+
 
 config FB_JZ4760_EPD
 	tristate "JZ4760 EPD Controller support"
-	depends on FB_JZSOC && (SOC_JZ4760)
+	depends on FB_JZSOC && (SOC_JZ4760 || SOC_JZ4760B)
 	---help---
 	   JZ4760 EPD Controller driver.
 	   JZ4760 EPD Controller support OSD function(refer jz4760_epdc_spec.pdf).JZ4760 EPD OSD implement 2 framebuffer layers: foreground0 and foreground1. JZ4760 EPD driver support only foreground0 default.
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index e55a3d65272..cee7d67595b 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -29,6 +29,7 @@ obj-$(CONFIG_FB_DEFERRED_IO)   += fb_defio.o
 
 # Hardware specific drivers go first
 obj-$(CONFIG_FB_JZ475X)		+= jz475x/
+obj-$(CONFIG_JZ4760_HDMI_DISPLAY) += ep932/
 
 obj-$(CONFIG_FB_JZLCD_4730_4740)  += jzlcd.o
 obj-$(CONFIG_FB_JZ4740_SLCD)      += jz4740_slcd.o
@@ -36,8 +37,15 @@ obj-$(CONFIG_FB_JZ4750_LCD)       += jz4750_lcd.o
 obj-$(CONFIG_FB_JZ4750_TVE)       += jz4750_tve.o
 obj-$(CONFIG_FB_JZ4760_LCD)       += jz4760_lcd.o
 obj-$(CONFIG_FB_JZ4760_TVE)       += jz4760_tve.o
+obj-$(CONFIG_JZ4760_AOSD)         += jz4760_aosd.o 
+obj-$(CONFIG_JZ4760_COMPRESS)     += jz4760_aosd.o
 
-obj-$(CONFIG_FB_JZ4760_EPD)       += jz4760_epd.o
+obj-$(CONFIG_FB_JZ4810_LCD)       += jz4810_lcd.o
+obj-$(CONFIG_FB_JZ4810_TVE)       += jz4810_tve.o
+obj-$(CONFIG_JZ4810_AOSD)         += jz4810_aosd.o 
+obj-$(CONFIG_JZ4810_COMPRESS)     += jz4810_aosd.o
+
+#obj-$(CONFIG_FB_JZ4760_EPD)       += jz4760_epd.o
 obj-$(CONFIG_FB_AMIGA)            += amifb.o c2p_planar.o
 obj-$(CONFIG_FB_ARC)              += arcfb.o
 obj-$(CONFIG_FB_CLPS711X)         += clps711xfb.o
diff --git a/drivers/video/ep932/Makefile b/drivers/video/ep932/Makefile
new file mode 100644
index 00000000000..82ecdcc110f
--- /dev/null
+++ b/drivers/video/ep932/Makefile
@@ -0,0 +1,2 @@
+obj-$(CONFIG_JZ4760_HDMI_DISPLAY) += ep932api.o ep932_if.o ep932controller.o ep932settingsdata.o hdcp.o edid.o ddc_if.o i2c_drivers/
+
diff --git a/drivers/video/ep932/ddc_if.c b/drivers/video/ep932/ddc_if.c
new file mode 100644
index 00000000000..6533e00e505
--- /dev/null
+++ b/drivers/video/ep932/ddc_if.c
@@ -0,0 +1,247 @@
+#include <linux/kernel.h>

+#include <linux/delay.h>

+

+#include "ddc_if.h"

+

+

+#define HDCP_RX_ADDR            0x74     // HDCP RX address

+#define EDID_ADDR      		0xA0     // EDID address

+#define EDID_SEGMENT_PTR	0x60

+

+#define HDCP_RX_BKSV_ADDR       0x00     // HDCP RX, BKSV register address

+#define HDCP_RX_RI_ADDR         0x08     // HDCP RX, RI register address

+#define HDCP_RX_AKSV_ADDR       0x10     // HDCP RX, AKSV register address

+#define HDCP_RX_AINFO_ADDR      0x15     // HDCP RX, AINFO register address

+#define HDCP_RX_AN_ADDR         0x18     // HDCP RX, AN register address

+#define HDCP_RX_SHA1_HASH_ADDR  0x20     // HDCP RX, SHA-1 Hash Value Start address

+#define HDCP_RX_BCAPS_ADDR      0x40     // HDCP RX, BCAPS register address

+#define HDCP_RX_BSTATUS_ADDR    0x41     // HDCP RX, BSTATUS register address

+#define HDCP_RX_KSV_FIFO_ADDR   0x43     // HDCP RX, KSV FIFO Start address

+

+

+

+smbus_status status;

+

+unsigned char ddc_data[128];

+unsigned char tempbit;

+

+/* downstream HDCP control */

+

+unsigned char downstream_rx_read_bksv(unsigned char *pbksv)

+{

+	int i, j;

+	status = jz_i2c_hdcp_rx_read(HDCP_RX_BKSV_ADDR, pbksv, 5);

+	if(status != SMBUS_STATUS_SUCCESS) {

+		DBG_PRINTK(("ERROR: BKSV read - DN DDC %d\r\n", (int)status));

+		return 0;

+	}

+

+	i = 0;

+	j = 0;

+	while (i < 5) {

+		tempbit = 1;

+		while (tempbit) {

+			if (pbksv[i] & tempbit) j++;

+			tempbit <<= 1;

+		}

+

+		i++;

+	}

+	if(j != 20) {

+		DBG_PRINTK(("ERROR: BKSV read - Key Wrong\r\n"));

+		DBG_PRINTK(("ERROR: BKSV=0x%02X,0x%02X,0x%02X,0x%02X,0x%02X\r\n", (unsigned int)pbksv[0], (unsigned int)pbksv[1], (unsigned int)pbksv[2], (unsigned int)pbksv[3], (unsigned int)pbksv[4]));

+

+		return 0;

+	}

+

+	return 1;

+}

+

+unsigned char downstream_rx_bcaps(void)

+{

+ 	jz_i2c_hdcp_rx_read(HDCP_RX_BCAPS_ADDR, ddc_data, 1);

+	return ddc_data[0];

+}

+

+void downstream_rx_write_ainfo(char ainfo)

+{

+	jz_i2c_hdcp_rx_write(HDCP_RX_AINFO_ADDR, &ainfo, 1);

+}

+

+void downstream_rx_write_an(unsigned char *pan)

+{

+	jz_i2c_hdcp_rx_write(HDCP_RX_AN_ADDR, pan, 8);

+}

+

+void downstream_rx_write_aksv(unsigned char *paksv)

+{

+	jz_i2c_hdcp_rx_write(HDCP_RX_AKSV_ADDR, paksv, 5);

+}

+

+unsigned char downstream_rx_read_ri(unsigned char *pri)

+{

+	status = jz_i2c_hdcp_rx_read(HDCP_RX_RI_ADDR, pri, 2);

+	if(status != SMBUS_STATUS_SUCCESS) {

+		DBG_PRINTK(("ERROR: Rx Ri read - MCU IIC %d\r\n", (int)status));

+

+		return 0;

+	}

+

+	return 1;

+}

+

+void downstream_rx_read_bstatus(unsigned char *pbstatus)

+{

+	jz_i2c_hdcp_rx_read(HDCP_RX_BSTATUS_ADDR, pbstatus, 2);

+}

+

+void downstream_rx_read_sha1_hash(unsigned char *psha)

+{

+	jz_i2c_hdcp_rx_read(HDCP_RX_SHA1_HASH_ADDR, psha, 20);

+}

+

+// retrive a 5 byte KSV at "index" from FIFO

+unsigned char downstream_rx_read_ksv_fifo(unsigned char *pbksv, unsigned char index, unsigned char devcount)

+{

+	int i, j;

+

+	// try not to re-read the previous KSV

+	if(index == 0) { 

+		status = jz_i2c_hdcp_rx_read(HDCP_RX_KSV_FIFO_ADDR, ddc_data, min(devcount, 25));

+	}

+	memcpy(pbksv, ddc_data+(index*5), 5);

+

+	if(status != SMBUS_STATUS_SUCCESS) {

+		DBG_PRINTK(("ERROR: KSV FIFO read - DN DDC %d\r\n", (int)status));

+		return 0;

+	}

+

+	i = 0;

+	j = 0;

+	while (i < 5) {

+		tempbit = 1;

+		while (tempbit) {

+			if (pbksv[i] & tempbit) j++;

+			tempbit <<= 1;

+		}

+		i++;

+	}

+	if(j != 20) {

+		DBG_PRINTK(("ERROR: KSV FIFO read - Key Wrong\r\n"));

+

+		return 0;

+	}

+

+	return 1;

+}

+

+

+// downstream edid control

+unsigned char downstream_rx_poll_edid(void)

+{

+	status = jz_i2c_edid_read(0, ddc_data, 1);

+

+	if(status != SMBUS_STATUS_SUCCESS) // can't read EDID

+	{

+		return 2;

+	}

+	if(ddc_data[0] != 0x00)				// EDID header fail

+	{

+		return 2;

+	}

+	return 0;							// Read EDID success

+

+}

+

+edid_status downstream_rx_read_edid(unsigned char *pedid)

+{

+	int i;

+	unsigned char seg_ptr, blockcount, block1found, chksum;

+

+	

+	status = jz_i2c_edid_read(0, pedid, 128);

+	for(i=0; i<128; ++i) {

+		if(i%16 == 0) DBG_PRINTK(("\r\n"));

+		if(i%8 == 0) DBG_PRINTK((" "));

+		DBG_PRINTK(("0x%02X, ", (int)pedid[i] ));

+	}

+

+	if(status != SMBUS_STATUS_SUCCESS) {

+		DBG_PRINTK(("ERROR: EDID b0 read - DN DDC %d\r\n", (int)status));

+		return status;

+	}

+	DBG_PRINTK(("EDID b0 read:"));

+	for(i=0; i<128; ++i) {

+		if(i%16 == 0) DBG_PRINTK(("\r\n"));

+		if(i%8 == 0) DBG_PRINTK((" "));

+		DBG_PRINTK(("0x%02x, ", (int)pedid[i] ));

+	}

+	DBG_PRINTK(("\r\n"));

+

+	if( (pedid[0] != 0x00) ||

+	    (pedid[1] != 0xFF) ||

+	    (pedid[2] != 0xFF) ||

+	    (pedid[3] != 0xFF) ||

+	    (pedid[4] != 0xFF) ||

+	    (pedid[5] != 0xFF) ||

+	    (pedid[5] != 0xFF) ||

+	    (pedid[7] != 0x00))

+	{

+		return EDID_STATUS_NOACT;

+	}

+

+	// Check EDID

+	if(pedid[126] > 8) {

+		DBG_PRINTK(("ERROR: EDID Check failed, pedid[126]=0x%02X > 8\n\r", (int)pedid[126] ));

+		return EDID_STATUS_EXTENSIONOVERFLOW;

+	}

+

+	// =========================================================

+	// II. Read other blocks and find Timing Extension Block

+

+	blockcount = pedid[126];

+	block1found = 0;

+	for (seg_ptr = 1; seg_ptr <= blockcount; ++seg_ptr) {

+

+		status = jz_i2c_edid_read((seg_ptr & 0x01) << 7, ddc_data, 128);

+		if(status != SMBUS_STATUS_SUCCESS) {

+			DBG_PRINTK(("ERROR: EDID bi read - DN DDC %d\r\n", (int)status));

+			return status;

+		}

+

+		if(ddc_data[0] == 0x02 && block1found == 0) {

+			block1found = 1;

+			memcpy(&pedid[128], ddc_data, 128);

+		}

+

+		DBG_PRINTK (("EDID b%d read:", (int)seg_ptr));

+		for(i=0; i<128; ++i) {

+//			if(i%16 == 0) DBG_PRINTK(("\r\n"));

+//			if(i%8 == 0) DBG_PRINTK((" "));

+			if(i%16 == 0) printk(("\r\n"));

+			if(i%8 == 0)printk((" "));

+//			DBG_PRINTK(("0x%02X, ", (int)ddc_data[i] ));

+			printk("0x%02X, ", (int)ddc_data[i]);

+		}

+		DBG_PRINTK(("\r\n"));

+	}

+

+	// Check CheckSum

+	chksum = 0;

+	for(i=0; i<((block1found)?256:128); ++i) {

+		chksum += pedid[i];

+	}

+	if(chksum != 0) {

+		return EDID_STATUS_CHECKSUMERROR;

+	}

+	if(block1found) {

+		pedid[126] = 1;

+	}

+	else {

+		pedid[126] = 0;

+	}

+

+	return EDID_STATUS_SUCCESS;

+}

+

+

diff --git a/drivers/video/ep932/ddc_if.h b/drivers/video/ep932/ddc_if.h
new file mode 100644
index 00000000000..ba45cce41c2
--- /dev/null
+++ b/drivers/video/ep932/ddc_if.h
@@ -0,0 +1,48 @@
+

+#ifndef DDC_IF_H

+#define DDC_IF_H

+

+

+#include <linux/string.h>

+#include "ep932api.h"

+#include "./i2c_drivers/hdmi.h"

+

+

+extern smbus_status status;

+extern unsigned char ddc_data[128];	 // the ddc buffer

+

+// edid status error code

+typedef enum {

+	// master

+	EDID_STATUS_SUCCESS = 0x00,

+	EDID_STATUS_PENDING,		// SMBUS_STATUS_Abort,

+	EDID_STATUS_NOACT = 0x02,

+	EDID_STATUS_TIMEOUT,

+	EDID_STATUS_ARBITRATIONLOSS = 0x04,

+	EDID_STATUS_EXTENSIONOVERFLOW,

+	EDID_STATUS_CHECKSUMERROR

+} edid_status;

+

+

+/* downstream HDCP control interface */

+

+extern unsigned char downstream_rx_read_bksv(unsigned char *pbksv);

+extern unsigned char downstream_rx_bcaps(void);

+extern void downstream_rx_write_ainfo(char ainfo);

+extern void downstream_rx_write_an(unsigned char *pan);

+extern void downstream_rx_write_aksv(unsigned char *paksv);

+extern unsigned char downstream_rx_read_ri(unsigned char *pri);

+extern void downstream_rx_read_bstatus(unsigned char *pbstatus);

+extern void downstream_rx_read_sha1_hash(unsigned char *psha);

+extern unsigned char downstream_rx_read_ksv_fifo(unsigned char *pbksv, unsigned char index, unsigned char devcount);

+

+

+/* downstream EDID control interface */

+

+extern unsigned char downstream_rx_poll_edid(void);

+extern edid_status downstream_rx_read_edid(unsigned char *pedid);

+

+

+#endif // DDC_IF_H

+

+

diff --git a/drivers/video/ep932/edid.c b/drivers/video/ep932/edid.c
new file mode 100644
index 00000000000..0d63f18a337
--- /dev/null
+++ b/drivers/video/ep932/edid.c
@@ -0,0 +1,99 @@
+#include "edid.h"

+#include "ep932api.h"

+

+static int i, j;

+

+//--------------------------------------------------------------------------------------------------

+

+unsigned char edid_gethdmicap(unsigned char *ptarget)

+{

+	for(i = 0; i < 128; ++i) {

+                if(i%16 == 0) DBG_PRINTK(("\r\n"));

+                if(i%8 == 0) DBG_PRINTK((" "));

+                DBG_PRINTK(("0x%02X, ", (int)ptarget[i] ));

+        }

+

+	if(ptarget[126] == 0x01) {

+		for(i=4; i<ptarget[EDID_BLOCK_SIZE+2]; ++i) {

+			if((ptarget[EDID_BLOCK_SIZE+i] & 0xE0) == 0x60) { // find tag code - Vendor Specific Block

+				if( (ptarget[EDID_BLOCK_SIZE+1+i] == 0x03) && (ptarget[EDID_BLOCK_SIZE+2+i] == 0x0C) && (ptarget[EDID_BLOCK_SIZE+3+i] == 0x00) ) {

+

+					return 1;

+				}

+			}

+			else {

+				i += (ptarget[EDID_BLOCK_SIZE+i] & 0x1F);

+			}

+		}

+		if(i >= ptarget[EDID_BLOCK_SIZE+2]) { // Error, can not find the Vendor Specific Block

+

+			return 0;

+		}

+	}

+	return 0;

+}

+

+unsigned char edid_getpcmfreqcap(unsigned char *ptarget)

+{

+	if(ptarget[126] >= 0x01) {

+		for(i=4; i<ptarget[EDID_BLOCK_SIZE+2]; ++i) {

+			if((ptarget[EDID_BLOCK_SIZE+i] & 0xE0) == 0x20) { // find tag code - Audio Data Block

+				for(j=1; j<(ptarget[EDID_BLOCK_SIZE+i] & 0x1F); j+=3) {

+					if((ptarget[EDID_BLOCK_SIZE+i+j] >> 3) == 1) {

+						return ptarget[EDID_BLOCK_SIZE+i+j+1];

+					}

+				}

+			}

+			else {

+				i += (ptarget[EDID_BLOCK_SIZE+i] & 0x1F);

+			}

+		}

+		if(i>=ptarget[EDID_BLOCK_SIZE+2]) { // Error, can not find the Audio Data Block

+			return 0x07;

+		}

+	}

+

+	return 0x00;

+}

+

+unsigned char edid_getpcmchannelcap(unsigned char *ptarget)

+{

+	unsigned char max_pcm_channel = 1;

+	if(ptarget[126] >= 0x01) {

+		for(i=4; i<ptarget[EDID_BLOCK_SIZE+2]; ++i) {

+			if((ptarget[EDID_BLOCK_SIZE+i] & 0xE0) == 0x20) { // find tag code - Audio Data Block

+				for(j=1; j<(ptarget[EDID_BLOCK_SIZE+i] & 0x1F); j+=3) {

+					if((ptarget[EDID_BLOCK_SIZE+i+j] >> 3) == 1) {

+						//return ptarget[EDID_BLOCK_SIZE+i+j] & 0x07;

+						max_pcm_channel = max(max_pcm_channel, ptarget[EDID_BLOCK_SIZE+i+j] & 0x07);

+					}

+				}

+			}

+			else {

+				i += (ptarget[EDID_BLOCK_SIZE+i] & 0x1F);

+			}

+		}

+		return max_pcm_channel;

+	}

+

+	return 0;

+}

+

+unsigned char edid_getdatablockaddr(unsigned char *ptarget, unsigned char tag)

+{

+	if(ptarget[126] >= 0x01) {

+		for(i=4; i<ptarget[EDID_BLOCK_SIZE+2]; ++i) {

+			if((ptarget[EDID_BLOCK_SIZE+i] & 0xE0) == tag) { // find tag code 

+				return i+128;

+			}

+			else {

+				i += (ptarget[EDID_BLOCK_SIZE+i] & 0x1F);

+			}

+		}

+		if(i>=ptarget[EDID_BLOCK_SIZE+2]) { // Error, can not find

+			return 0;

+		}

+	}

+	return 0;

+}

+

diff --git a/drivers/video/ep932/edid.h b/drivers/video/ep932/edid.h
new file mode 100644
index 00000000000..5e5384066a9
--- /dev/null
+++ b/drivers/video/ep932/edid.h
@@ -0,0 +1,30 @@
+/******************************************************************************\

+

+          (c) Copyright Explore Semiconductor, Inc. Limited 2005

+                           ALL RIGHTS RESERVED 

+

+--------------------------------------------------------------------------------

+

+  File        :  Edid.h 

+

+  Description :  Head file of Edid IO Interface 

+

+\******************************************************************************/

+

+#ifndef EDID_H

+#define EDID_H

+

+#define EDID_BLOCK_SIZE  128

+

+

+

+// Structure Definitions

+

+extern unsigned char edid_gethdmicap(unsigned char *ptarget);

+extern unsigned char edid_getpcmfreqcap(unsigned char *ptarget);

+extern unsigned char edid_getpcmchannelcap(unsigned char *ptarget);

+extern unsigned char edid_getdatablockaddr(unsigned char *ptarget, unsigned char tag);

+

+#endif // EDID_H

+

+

diff --git a/drivers/video/ep932/ep932_if.c b/drivers/video/ep932/ep932_if.c
new file mode 100644
index 00000000000..1bde5fc0151
--- /dev/null
+++ b/drivers/video/ep932/ep932_if.c
@@ -0,0 +1,1105 @@
+#include <linux/kthread.h>

+#include <linux/delay.h>

+

+#include "ep932_if.h"

+#include "ddc_if.h"

+#include "ep932settingsdata.h"

+

+#define EP932_ADDR			0x70

+#define EP932_ADDR_2			0x72

+#define HEY_ADDR			0xA8

+

+

+extern struct task_struct *hdmi_kthread;

+extern int hdmi_init;

+

+// Private data

+unsigned char iic_ep932_addr,iic_key_addr;

+

+unsigned short tempushort;

+

+unsigned char temp_data[15];

+unsigned char w_data[2];

+

+// Global date for HDMI Transmiter

+unsigned char is_hdcp_avmute;

+unsigned char is_amute;

+unsigned char is_vmute;

+unsigned char is_hdmi;

+unsigned char is_rsen;

+unsigned char cache_ep932_de_control;

+

+// Private Functions

+smbus_status iic_write(unsigned char iic_addr, unsigned char byteaddr, unsigned char *data, unsigned int size);

+smbus_status iic_read(unsigned char iic_addr, unsigned char byteaddr, unsigned char *data, unsigned int size);

+

+

+void ep932_if_initial(void)	//customer setting

+{

+	//EP932_handle = E_handle;

+	//KEY_handle = K_handle;

+	iic_ep932_addr = 0x70;

+	iic_key_addr = 0xA8;

+

+#if 0

+// for test only

+	DBG_PRINTK(("IIC test write [0x63]0xAA, [0x64]0xA5, [0x65]0x5A\r\n"));

+

+//	while (i++ < 10)

+while(1) {

+		temp_data[0] = 0xAA;

+	printk("write data 0xAA.\n");

+	ep932_reg_write(0x10, temp_data, 1);

+	mdelay(200);

+	memset(temp_data, 0, 128);

+	ep932_reg_read(0x10, temp_data, 1);

+//	while (i--)

+	printk("maxueyue ======================= read data = %#x\n", temp_data[0]);

+	mdelay(5000);

+}

+

+	ep932_reg_write(0x63, temp_data, 1);

+	temp_data[0] = 0xA5;

+	ep932_reg_write(0x64, temp_data, 1);

+	temp_data[0] = 0x5A;

+	ep932_reg_write(0x65, temp_data, 1);

+

+	temp_data[0] = 0x55;

+	ep932_reg_write(0x60, temp_data, 1);

+	temp_data[0] = 0x99;

+	ep932_reg_write(0x61, temp_data, 1);

+	temp_data[0] = 0x88;

+	ep932_reg_write(0x62, temp_data, 1);

+

+// read for verify

+

+//	ep932_reg_read(EP932_cts, temp_data, 1);

+	i2c_read(0x38, temp_data, EP932.cts, 1);

+//	DBG_PRINTK(("EP932_cts_0(Reg addr 0x60) = 0x%02X\r\n",(int)temp_data[0]));

+	printk("EP932_cts_0(Reg addr 0x60) = 0x%02X\r\n",(int)temp_data[0]);

+	i2c_read(0x38, temp_data, 0x61, 1);

+//	ep932_reg_read(0x61, temp_data, 1);

+//	DBG_PRINTK(("EP932_cts_1(Reg addr 0x61) = 0x%02X\r\n",(int)temp_data[0]));

+	printk("EP932_cts_1(Reg addr 0x61) = 0x%02X\r\n",(int)temp_data[0]);

+	i2c_read(0x38, temp_data, 0x62, 1);

+//	ep932_reg_read(0x62, temp_data, 1);

+//	DBG_PRINTK(("EP932_cts_2(Reg addr 0x62) = 0x%02X\r\n",(int)temp_data[0]));

+	printk("EP932_cts_2(Reg addr 0x62) = 0x%02X\r\n",(int)temp_data[0]);

+

+	ep932_reg_read(EP932.n, temp_data, 1);

+//	DBG_PRINTK(("EP932.n_0(Reg addr 0x63) = 0x%02X\r\n",(int)temp_data[0]));

+	printk("EP932.n_0(Reg addr 0x63) = 0x%02X\r\n",(int)temp_data[0]);

+	ep932_reg_read(0x64, temp_data, 1);

+//	DBG_PRINTK(("EP932.n_1(Reg addr 0x64) = 0x%02X\r\n",(int)temp_data[0]));

+printk("EP932.n_1(Reg addr 0x64) = 0x%02X\r\n",(int)temp_data[0]);

+	ep932_reg_read(0x65, temp_data, 1);

+//	DBG_PRINTK(("EP932.n_2(Reg addr 0x65) = 0x%02X\r\n",(int)temp_data[0]));

+	printk("EP932.n_2(Reg addr 0x65) = 0x%02X\r\n",(int)temp_data[0]);

+

+#endif

+	

+}

+

+void ep932_if_reset(void)

+{

+	int i;

+

+	// Global date for HDMI Transmiter

+	is_hdcp_avmute = 0;

+	is_amute = 1;

+	is_vmute = 1;

+	is_hdmi = 0;

+	is_rsen = 0;

+	cache_ep932_de_control = 0x03;

+

+	// Initial Settings

+	ep932_reg_set_bit(EP932_GENERAL_CONTROL_1, EP932_GENERAL_CONTROL_1__VTX);

+	ep932_reg_set_bit(EP932_GENERAL_CONTROL_1, EP932_GENERAL_CONTROL_1__INT_OD);

+

+	// Default Audio Mute

+	ep932_reg_set_bit(EP932_COLOR_SPACE_CONTROL, EP932_COLOR_SPACE_CONTROL__AMUTE);

+	ep932_reg_set_bit(EP932_PIXEL_REPETITION_CONTROL, EP932_PIXEL_REPETITION_CONTROL__CTS_M);

+	// Default Video Mute

+	ep932_reg_set_bit(EP932_COLOR_SPACE_CONTROL, EP932_COLOR_SPACE_CONTROL__VMUTE);

+

+	//

+	// Set Default AVI Info Frame

+	//

+	memset(temp_data, 0x00, 14);

+

+	// Set AVI Info Frame to RGB

+	temp_data[1] &= 0x60;

+	temp_data[1] |= 0x00; // RGB

+

+	// Set AVI Info Frame to 601

+	temp_data[2] &= 0xC0;

+	temp_data[2] |= 0x40;

+

+	// Write AVI Info Frame

+	temp_data[0] = 0;

+	for(i=1; i<14; ++i) {

+		temp_data[0] += temp_data[i];

+	}

+	temp_data[0] = ~(temp_data[0] - 1);

+	ep932_reg_write(EP932_AVI_PACKET, temp_data, 14);

+

+

+	//

+	// Set Default ADO Info Frame

+	//

+	memset(temp_data, 0x00, 6);

+

+	// Write ADO Info Frame

+	temp_data[0] = 0;

+	for(i=1; i<6; ++i) {

+		temp_data[0] += temp_data[i];

+	}

+	temp_data[0] = ~(temp_data[0] - 1);

+	ep932_reg_write(EP932_ADO_PACKET, temp_data, 6);

+}

+

+//--------------------------------------------------------------------------------------------------

+//

+// HDMI Transmiter (EP932-Tx Implementation)

+//

+

+void hdmi_tx_power_down(void)

+{

+	// Software power down

+	ep932_reg_clear_bit(EP932_GENERAL_CONTROL_1, EP932_GENERAL_CONTROL_1__PU);

+}

+

+void hdmi_tx_power_up(void)

+{

+	// Software power up

+	ep932_reg_set_bit(EP932_GENERAL_CONTROL_1, EP932_GENERAL_CONTROL_1__PU);

+}

+

+unsigned char hdmi_tx_htplg(void)

+{

+	// Software HotPlug Detect

+//	return 1;

+	ep932_reg_read(EP932_GENERAL_CONTROL_2, temp_data, 1);

+	is_rsen = (temp_data[0] & EP932_GENERAL_CONTROL_2__RSEN)? 1:0;

+	if(temp_data[0] & EP932_GENERAL_CONTROL_2__HTPLG)

+	{

+		return 1;

+	}

+	else

+	{

+		//DBG_PRINTK(("hdmi_tx_htplg disconnect\r\n"));

+		return 0;

+	}

+	// This is for old DVI monitor compatibility. For HDMI TV, there is no need to poll the EDID.

+	return downstream_rx_poll_edid();

+}

+

+unsigned char hdmi_tx_rsen(void)

+{

+	return is_rsen;

+}

+

+void hdmi_tx_hdmi(void)

+{

+	if(!is_hdmi) {

+		is_hdmi = 1;

+		ep932_reg_set_bit(EP932_GENERAL_CONTROL_4, EP932_GENERAL_CONTROL_4__HDMI);

+		DBG_PRINTK(("Set to HDMI mode\r\n"));

+	}

+	if((is_vmute == 0)&&(is_amute == 0)&&(is_hdmi == 1))

+		hdmi_init = 0;

+}

+

+void hdmi_tx_dvi(void)

+{

+	if(is_hdmi) {

+		is_hdmi = 0;

+		ep932_reg_clear_bit(EP932_GENERAL_CONTROL_4, EP932_GENERAL_CONTROL_4__HDMI);

+		DBG_PRINTK(("Set to DVI mode\r\n"));

+	}

+}

+

+//------------------------------------

+// HDCP

+

+void hdmi_tx_mute_enable(void)

+{

+	is_hdcp_avmute = 1;

+	ep932_reg_set_bit(EP932_COLOR_SPACE_CONTROL, EP932_COLOR_SPACE_CONTROL__AMUTE | EP932_COLOR_SPACE_CONTROL__VMUTE);

+	ep932_reg_set_bit(EP932_PIXEL_REPETITION_CONTROL, EP932_PIXEL_REPETITION_CONTROL__CTS_M);

+}

+

+void hdmi_tx_mute_disable(void)

+{

+	is_hdcp_avmute = 0;

+

+	if(!is_amute) {

+		ep932_reg_clear_bit(EP932_PIXEL_REPETITION_CONTROL, EP932_PIXEL_REPETITION_CONTROL__CTS_M);

+		ep932_reg_clear_bit(EP932_COLOR_SPACE_CONTROL, EP932_COLOR_SPACE_CONTROL__AMUTE);

+	}

+	if(!is_vmute) {

+		ep932_reg_clear_bit(EP932_COLOR_SPACE_CONTROL, EP932_COLOR_SPACE_CONTROL__VMUTE);

+	}

+}

+

+void hdmi_tx_hdcp_enable(void)

+{

+	ep932_reg_set_bit(EP932_GENERAL_CONTROL_5, EP932_GENERAL_CONTROL_5__ENC_EN);

+}

+

+void hdmi_tx_hdcp_disable(void)

+{

+	ep932_reg_clear_bit(EP932_GENERAL_CONTROL_5, EP932_GENERAL_CONTROL_5__ENC_EN);

+}

+

+void hdmi_tx_rptr_set(void)

+{

+	ep932_reg_set_bit(EP932_GENERAL_CONTROL_5, EP932_GENERAL_CONTROL_5__RPTR);

+}

+

+void hdmi_tx_rptr_clear(void)

+{

+	ep932_reg_clear_bit(EP932_GENERAL_CONTROL_5, EP932_GENERAL_CONTROL_5__RPTR);

+}

+

+void hdmi_tx_write_an(unsigned char *pan)

+{

+	ep932_reg_write(EP932_AN, pan, 8);

+}

+

+unsigned char hdmi_tx_aksv_rdy(void)

+{

+	status = ep932_reg_read(EP932_GENERAL_CONTROL_5, temp_data, 1);

+	if(status != SMBUS_STATUS_SUCCESS) {

+		DBG_PRINTK(("ERROR: AKSV RDY - MCU IIC %d\r\n", (int)status));

+		return 0;

+	}

+	return (temp_data[0] & EP932_GENERAL_CONTROL_5__AKSV_RDY)? 1:0;

+}

+

+unsigned char hdmi_tx_read_aksv(unsigned char *paksv)

+{

+	int i, j;

+	unsigned char tmp[1];

+

+	status = ep932_reg_read(EP932_GENERAL_CONTROL_5, tmp, 1);

+

+	status = ep932_reg_read(EP932_AKSV, paksv, 5);

+	if(status != SMBUS_STATUS_SUCCESS) {

+		DBG_PRINTK(("ERROR: AKSV read - MCU IIC %d\r\n", (int)status));

+		return 0;

+	}

+

+printk("/************************************************************************************/\n");

+	for (i = 0; i < 5; i++)

+		printk("paksv[%d] = %#x\n", i, paksv[i]);

+printk("/************************************************************************************/\n");

+	i = 0;

+	j = 0;

+	while (i < 5) {

+		temp_data[0] = 1;

+		while (temp_data[0]) {

+			if (paksv[i] & temp_data[0]) j++;

+			temp_data[0] <<= 1;

+		}

+		i++;

+	}

+	if(j != 20) {

+		DBG_PRINTK(("ERROR: AKSV read - key Wrong\r\n"));

+		return 0;

+	}

+	return 1;

+}

+

+void hdmi_tx_write_bksv(unsigned char *pbksv)

+{

+	ep932_reg_write(EP932_BKSV, pbksv, 5);

+}

+

+unsigned char hdmi_tx_ri_rdy(void)

+{

+	ep932_reg_read(EP932_GENERAL_CONTROL_5, temp_data, 1);

+	printk("ri tmpdata = %#x\n", temp_data[0]);

+	return (temp_data[0] & EP932_GENERAL_CONTROL_5__RI_RDY)? 1:0;

+}

+

+unsigned char hdmi_tx_read_ri(unsigned char *pri)

+{

+	status = ep932_reg_read(EP932_RI, pri, 2);

+	if(status != SMBUS_STATUS_SUCCESS) {

+		DBG_PRINTK(("ERROR: Tx Ri read - MCU IIC %d\r\n", (int)status));

+		return 0;

+	}

+	return 1;

+}

+

+void hdmi_tx_read_m0(unsigned char *pm0)

+{

+	status = ep932_reg_read(EP932_M0, pm0, 8);

+}

+

+smbus_status hdmi_tx_get_key(unsigned char *key)

+{

+//	return iic_read(HEY_ADDR, 0, key, 512);

+	return jz_i2c_hey_read(0, key, 512);

+}

+

+//------------------------------------

+// Special for config

+

+void hdmi_tx_amute_enable(void)

+{

+	unsigned char temp_byte[2];

+	if(!is_amute) {

+		is_amute = 1;

+		ep932_reg_set_bit(EP932_COLOR_SPACE_CONTROL, EP932_COLOR_SPACE_CONTROL__AMUTE);

+		ep932_reg_set_bit(EP932_PIXEL_REPETITION_CONTROL, EP932_PIXEL_REPETITION_CONTROL__CTS_M);

+

+		DBG_PRINTK(("<<< AMute_enable >>>\r\n"));

+

+		//read for verify

+		ep932_reg_read(EP932_COLOR_SPACE_CONTROL, temp_byte, 1);

+		DBG_PRINTK(("EP932_COLOR_SPACE_CONTROL = 0x%02X\r\n",(int)temp_byte[0]));

+		ep932_reg_read(EP932_PIXEL_REPETITION_CONTROL, temp_byte, 1);

+		DBG_PRINTK(("EP932_PIXEL_REPETITION_CONTROL = 0x%02X\r\n",(int)temp_byte[0]));

+// add end

+	}

+}

+

+void hdmi_tx_amute_disable(void)

+{

+	unsigned char temp_byte[2];

+	if(is_amute) {

+		is_amute = 0;

+		if(!is_hdcp_avmute) {

+			ep932_reg_clear_bit(EP932_PIXEL_REPETITION_CONTROL, EP932_PIXEL_REPETITION_CONTROL__CTS_M);

+			ep932_reg_clear_bit(EP932_COLOR_SPACE_CONTROL, EP932_COLOR_SPACE_CONTROL__AMUTE);

+

+			DBG_PRINTK(("<<< AMute_disable >>>\r\n"));

+

+			//read for verify

+			ep932_reg_read(EP932_COLOR_SPACE_CONTROL, temp_byte, 1);

+			DBG_PRINTK(("EP932_COLOR_SPACE_CONTROL = 0x%02X\r\n",(int)temp_byte[0]));

+			ep932_reg_read(EP932_PIXEL_REPETITION_CONTROL, temp_byte, 1);

+			DBG_PRINTK(("EP932_PIXEL_REPETITION_CONTROL = 0x%02X\r\n",(int)temp_byte[0]));

+// add end

+		}

+	}

+	if((is_vmute == 0)&&(is_amute == 0)&&(is_hdmi == 1))

+		hdmi_init = 0;

+}

+

+void hdmi_tx_vmute_enable(void)

+{

+	if(!is_vmute) {

+		is_vmute = 1;

+		ep932_reg_set_bit(EP932_COLOR_SPACE_CONTROL, EP932_COLOR_SPACE_CONTROL__VMUTE);

+

+		DBG_PRINTK(("<<< VMute_enable >>>\r\n"));

+	}

+}

+

+void hdmi_tx_vmute_disable(void)

+{

+	if(is_vmute) {

+		is_vmute = 0;

+		if(!is_hdcp_avmute) {

+			ep932_reg_clear_bit(EP932_COLOR_SPACE_CONTROL, EP932_COLOR_SPACE_CONTROL__VMUTE);

+

+			DBG_PRINTK(("<<< VMute_disable >>>\r\n"));

+		}

+	}

+	if((is_vmute == 0)&&(is_amute == 0)&&(is_hdmi == 1))

+	hdmi_init = 0;

+	//kthread_stop(hdmi_kthread);

+}

+

+void hdmi_tx_video_config(pvdo_params params)

+{

+	int i;

+	DBG_PRINTK(("\r\nStart Tx Video Config\r\n"));

+

+	//

+	// Disable Video

+	//

+	ep932_reg_clear_bit(EP932_IIS_CONTROL, EP932_IIS_CONTROL__AVI_EN);

+

+	//

+	// Video Settings

+	//

+	// Interface

+	ep932_reg_read(EP932_GENERAL_CONTROL_3, temp_data, 1);

+	temp_data[0] &= ~0xF0;

+	temp_data[0] |= params->interface & 0xF0;

+	ep932_reg_write(EP932_GENERAL_CONTROL_3, temp_data, 1);

+

+	ep932_reg_read(EP932_GENERAL_CONTROL_1, temp_data, 1);

+	temp_data[0] &= ~0x0E;

+	temp_data[0] |= params->interface & 0x0E;

+	ep932_reg_write(EP932_GENERAL_CONTROL_1, temp_data, 1);

+

+	if(params->interface & 0x01) {

+		ep932_reg_set_bit(EP932_GENERAL_CONTROL_4, EP932_GENERAL_CONTROL_4__FMT12);

+	}

+	else {

+		ep932_reg_clear_bit(EP932_GENERAL_CONTROL_4, EP932_GENERAL_CONTROL_4__FMT12);

+	}

+

+	// Sync Mode

+	switch(params->syncmode) {

+		default:

+	 	case SYNCMODE_HVDE:

+			// Disable E_S.nC

+			ep932_reg_clear_bit(EP932_GENERAL_CONTROL_4, EP932_GENERAL_CONTROL_4__E_SYNC);

+			// Disable DE_G.n

+			cache_ep932_de_control &= ~EP932_DE_CONTROL__DE_GEN;

+			//ep932_reg_write(EP932_DE_CONTROL, &cache_ep932_de_control, 1);

+

+			// Regular VSO_POL, HSO_POL

+			if((params->hvpol & VNEGHPOS) != (ep932_vdo_settings[params->videosettingindex].hvres_type.hvpol & VNEGHPOS)) { // V

+				cache_ep932_de_control |= EP932_DE_CONTROL__VSO_POL; // Invert

+			}

+//	status = ep932_reg_read(EP932_AKSV, pAKSV, 5);

+			else {

+				cache_ep932_de_control &= ~EP932_DE_CONTROL__VSO_POL;

+			}

+			if((params->hvpol & VPOSHNEG) != (ep932_vdo_settings[params->videosettingindex].hvres_type.hvpol & VPOSHNEG)) { // H

+				cache_ep932_de_control |= EP932_DE_CONTROL__HSO_POL; // Invert

+			}

+			else {

+				cache_ep932_de_control &= ~EP932_DE_CONTROL__HSO_POL;

+			}

+			DBG_PRINTK(("Set Sync mode to DE mode\r\n"));

+			break;

+

+		case SYNCMODE_HV:

+			// Disable E_S.nC

+			ep932_reg_clear_bit(EP932_GENERAL_CONTROL_4, EP932_GENERAL_CONTROL_4__E_SYNC);

+			// Enable DE_G.n

+			cache_ep932_de_control |= EP932_DE_CONTROL__DE_GEN;

+			//ep932_reg_write(EP932_DE_CONTROL, &cache_ep932_de_control, 1);

+

+			// Regular VSO_POL, HSO_POL

+			if((params->hvpol & VNEGHPOS) != (ep932_vdo_settings[params->videosettingindex].hvres_type.hvpol & VNEGHPOS)) { // V

+				cache_ep932_de_control |= EP932_DE_CONTROL__VSO_POL; // Invert

+			}

+			else {

+				cache_ep932_de_control &= ~EP932_DE_CONTROL__VSO_POL;

+			}

+			if((params->hvpol & VPOSHNEG) != (ep932_vdo_settings[params->videosettingindex].hvres_type.hvpol & VPOSHNEG)) { // H

+				cache_ep932_de_control |= EP932_DE_CONTROL__HSO_POL; // Invert

+			}

+			else {

+				cache_ep932_de_control &= ~EP932_DE_CONTROL__HSO_POL;

+			}

+

+			// Set DE generation params

+			if(params->videosettingindex < ep932_vdo_settings_max) {

+				cache_ep932_de_control &= ~0x03;

+				cache_ep932_de_control |= ((unsigned char *)&ep932_vdo_settings[params->videosettingindex].de_gen.de_dly)[0];

+

+				temp_data[0] = ((unsigned char *)&ep932_vdo_settings[params->videosettingindex].de_gen.de_dly)[1];

+				ep932_reg_write(EP932_DE_DLY, temp_data, 1);

+

+				temp_data[0] = ((unsigned char *)&ep932_vdo_settings[params->videosettingindex].de_gen.de_top)[0];

+				ep932_reg_write(EP932_DE_TOP, temp_data, 1);

+

+				temp_data[0] = ((unsigned char *)&ep932_vdo_settings[params->videosettingindex].de_gen.de_cnt)[1];

+				temp_data[1] = ((unsigned char *)&ep932_vdo_settings[params->videosettingindex].de_gen.de_cnt)[0];

+				ep932_reg_write(EP932_DE_CNT, temp_data, 2);

+

+				temp_data[0] = ((unsigned char *)&ep932_vdo_settings[params->videosettingindex].de_gen.de_lin)[1];

+				temp_data[1] = ((unsigned char *)&ep932_vdo_settings[params->videosettingindex].de_gen.de_lin)[0];

+				ep932_reg_write(EP932_DE_LIN, temp_data, 2);

+

+				DBG_PRINTK(("Update DE_G.n params %u", (unsigned short)ep932_vdo_settings[params->videosettingindex].de_gen.de_dly));

+				DBG_PRINTK((", %u", (unsigned short)ep932_vdo_settings[params->videosettingindex].de_gen.de_cnt));

+				DBG_PRINTK((", %u", (unsigned short)ep932_vdo_settings[params->videosettingindex].de_gen.de_top));

+				DBG_PRINTK((", %u", (unsigned short)ep932_vdo_settings[params->videosettingindex].de_gen.de_lin));

+				DBG_PRINTK(("\r\n"));

+			}

+			else {

+				DBG_PRINTK(("ERROR:.videocode overflow DE_G.n table\r\n"));

+			}

+			break;

+

+		case SYNCMODE_EMBEDED:

+			// Disable DE_G.n

+			cache_ep932_de_control &= ~EP932_DE_CONTROL__DE_GEN;

+			//ep932_reg_write(EP932_DE_CONTROL, &cache_ep932_de_control, 1);

+			// Enable E_S.nC

+			ep932_reg_set_bit(EP932_GENERAL_CONTROL_4, EP932_GENERAL_CONTROL_4__E_SYNC);

+

+			// Set E_S.nC params

+			if(params->videosettingindex < ep932_vdo_settings_max) {

+

+				temp_data[0] = ep932_vdo_settings[params->videosettingindex].e_sync.ctl;

+				ep932_reg_write(EP932_EMBEDDED_SYNC, temp_data, 1);

+				//DBG_PRINTK(("[0x80]= 0x%02X\r\n",(int)temp_data[0]));

+

+

+				tempushort = ep932_vdo_settings[params->videosettingindex].e_sync.h_dly;

+				if(!(params->interface & 0x04)) { // Mux Mode

+					tempushort += 2;

+				}

+

+				/*	 // for Big Endean

+				temp_data[0] = ((BYTE *)&tempushort)[1];

+				temp_data[1] = ((BYTE *)&tempushort)[0];

+				ep932_reg_write(EP932_H_DELAY, temp_data, 2);

+				*/

+				temp_data[0] = ((unsigned char *)&tempushort)[0];		// for Little Endean

+				ep932_reg_write(EP932_H_DELAY, temp_data, 1);

+				//DBG_PRINTK(("[0x81]= 0x%02X\r\n",(int)temp_data[0]));

+				temp_data[0] = ((unsigned char *)&tempushort)[1];   	// for Little Endean

+				ep932_reg_write(0x82, temp_data, 1);

+				//DBG_PRINTK(("[0x82]= 0x%02X\r\n",(int)temp_data[0]));

+

+				/*	 // for Big Endean

+				temp_data[0] = ((BYTE *)&ep932_vdo_settings[params->videosettingindex].e_sync.h_width)[1];

+				temp_data[1] = ((BYTE *)&ep932_vdo_settings[params->videosettingindex].e_sync.h_width)[0];

+				ep932_reg_write(EP932_H_WIDTH, temp_data, 2);

+				*/

+				temp_data[0] = ((unsigned char *)&ep932_vdo_settings[params->videosettingindex].e_sync.h_width)[0];   // modify by Eric_Lu for Little Endean

+				ep932_reg_write(EP932_H_WIDTH, temp_data, 1);

+				//DBG_PRINTK(("[0x83]= 0x%02X\r\n",(int)temp_data[0]));

+				temp_data[0] = ((unsigned char *)&ep932_vdo_settings[params->videosettingindex].e_sync.h_width)[1];   // modify by Eric_Lu for Little Endean

+				ep932_reg_write(0x84, temp_data, 1);

+				//DBG_PRINTK(("[0x84]= 0x%02X\r\n",(int)temp_data[0]));

+

+				temp_data[0] = ep932_vdo_settings[params->videosettingindex].e_sync.v_dly;

+				ep932_reg_write(EP932_V_DELAY, temp_data, 1);

+				//DBG_PRINTK(("[0x85]= 0x%02X\r\n",(int)temp_data[0]));

+

+				temp_data[0] = ep932_vdo_settings[params->videosettingindex].e_sync.v_width;

+				ep932_reg_write(EP932_V_WIDTH, temp_data, 1);

+				//DBG_PRINTK(("[0x86]= 0x%02X\r\n",(int)temp_data[0]));

+

+				/*	 // for Big Endean

+				temp_data[0] = ((BYTE *)&ep932_vdo_settings[params->videosettingindex].e_sync.v_ofst)[1];

+				temp_data[1] = ((BYTE *)&ep932_vdo_settings[params->videosettingindex].e_sync.v_ofst)[0];

+				ep932_reg_write(EP932_V_OFF_SET, temp_data, 2);

+				*/

+				temp_data[0] = ((unsigned char *)&ep932_vdo_settings[params->videosettingindex].e_sync.v_ofst)[0];   // modify by Eric_Lu for Little Endean

+				ep932_reg_write(EP932_V_OFF_SET, temp_data, 1);

+				//DBG_PRINTK(("[0x87]= 0x%02X\r\n",(int)temp_data[0]));

+				temp_data[0] = ((unsigned char *)&ep932_vdo_settings[params->videosettingindex].e_sync.v_ofst)[1];   // modify by Eric_Lu for Little Endean

+				ep932_reg_write(0x88, temp_data, 1);

+				//DBG_PRINTK(("[0x88]= 0x%02X\r\n",(int)temp_data[0]));

+

+				DBG_PRINTK(("Update E_S.nC params 0x%02X", (unsigned short)ep932_vdo_settings[params->videosettingindex].e_sync.ctl));

+				DBG_PRINTK((", %u", (unsigned short)ep932_vdo_settings[params->videosettingindex].e_sync.h_dly));

+				DBG_PRINTK((", %u", (unsigned short)ep932_vdo_settings[params->videosettingindex].e_sync.h_width));

+				DBG_PRINTK((", %u", (unsigned short)ep932_vdo_settings[params->videosettingindex].e_sync.v_dly));

+				DBG_PRINTK((", %u", (unsigned short)ep932_vdo_settings[params->videosettingindex].e_sync.v_width));

+				DBG_PRINTK((", %u", (unsigned short)ep932_vdo_settings[params->videosettingindex].e_sync.v_ofst));

+				DBG_PRINTK(("\r\n"));

+

+

+				for(i=0x80; i<=0x88; i++)

+				{

+					ep932_reg_read(i, temp_data, 1);

+					DBG_PRINTK(("EP932_reg[0x%02X]=0x%02X\r\n",(int)i,(int)temp_data[0]));

+				}

+

+

+				// Regular VSO_POL, HSO_POL

+				if(ep932_vdo_settings[params->videosettingindex].hvres_type.hvpol & VNEGHPOS) { // VNeg?

+					cache_ep932_de_control |= EP932_DE_CONTROL__VSO_POL;

+				}

+				else {

+					cache_ep932_de_control &= ~EP932_DE_CONTROL__VSO_POL;

+				}

+				if(ep932_vdo_settings[params->videosettingindex].hvres_type.hvpol & VPOSHNEG) { // HNeg?

+					cache_ep932_de_control |= EP932_DE_CONTROL__HSO_POL;

+				}

+				else {

+					cache_ep932_de_control &= ~EP932_DE_CONTROL__HSO_POL;

+				}

+			}

+			else {

+				DBG_PRINTK(("ERROR:.videocode overflow E_S.nC table\r\n"));

+			}

+			break;

+	}

+	ep932_reg_write(EP932_DE_CONTROL, &cache_ep932_de_control, 1);

+

+	// Pixel Repetition

+	ep932_reg_read(EP932_PIXEL_REPETITION_CONTROL, temp_data, 1);

+	temp_data[0] &= ~EP932_PIXEL_REPETITION_CONTROL__PR;

+	if(params->videosettingindex < ep932_vdo_settings_max) {

+		temp_data[0] |= ep932_vdo_settings[params->videosettingindex].ar_pr & 0x03;

+	}

+	ep932_reg_write(EP932_PIXEL_REPETITION_CONTROL, temp_data, 1);

+

+	// Color Space

+	switch(params->formatin) {

+		default:

+	 	case COLORFORMAT_RGB:

+			ep932_reg_clear_bit(EP932_GENERAL_CONTROL_4, EP932_GENERAL_CONTROL_4__YCC_IN | EP932_GENERAL_CONTROL_4__422_IN);

+			DBG_PRINTK(("Set to RGB In\r\n"));

+			break;

+	 	case COLORFORMAT_YCC444:

+			ep932_reg_set_bit(EP932_GENERAL_CONTROL_4, EP932_GENERAL_CONTROL_4__YCC_IN);

+			ep932_reg_clear_bit(EP932_GENERAL_CONTROL_4, EP932_GENERAL_CONTROL_4__422_IN);

+			DBG_PRINTK(("Set to YCC444 In\r\n"));

+			break;

+	 	case COLORFORMAT_YCC422:

+			ep932_reg_set_bit(EP932_GENERAL_CONTROL_4, EP932_GENERAL_CONTROL_4__YCC_IN | EP932_GENERAL_CONTROL_4__422_IN);

+			DBG_PRINTK(("Set to YCC422 In\r\n"));

+			break;

+	}

+	switch(params->formatout) {

+		default:

+	 	case COLORFORMAT_RGB:

+			// Set to RGB

+			if(params->videosettingindex < EP932_VDO_SETTINGS_IT_START) { // CE Timing

+				ep932_reg_clear_bit(EP932_COLOR_SPACE_CONTROL, EP932_COLOR_SPACE_CONTROL__YCC_OUT | EP932_COLOR_SPACE_CONTROL__422_OUT);

+				ep932_reg_set_bit(EP932_COLOR_SPACE_CONTROL, EP932_COLOR_SPACE_CONTROL__YCC_RANGE); // Output limit range RGB

+			}

+			else { // IT Timing

+				ep932_reg_clear_bit(EP932_COLOR_SPACE_CONTROL, EP932_COLOR_SPACE_CONTROL__YCC_OUT | EP932_COLOR_SPACE_CONTROL__422_OUT | EP932_COLOR_SPACE_CONTROL__YCC_RANGE);

+			}

+			DBG_PRINTK(("Set to RGB Out\r\n"));

+			break;

+

+	 	case COLORFORMAT_YCC444:

+			// Set to YCC444

+			ep932_reg_set_bit(EP932_COLOR_SPACE_CONTROL, EP932_COLOR_SPACE_CONTROL__YCC_OUT);

+			ep932_reg_clear_bit(EP932_COLOR_SPACE_CONTROL, EP932_COLOR_SPACE_CONTROL__422_OUT);

+			DBG_PRINTK(("Set to YCC444 Out\r\n"));

+			break;

+	 	case COLORFORMAT_YCC422:

+			// Set to YCC422

+			ep932_reg_set_bit(EP932_COLOR_SPACE_CONTROL, EP932_COLOR_SPACE_CONTROL__YCC_OUT | EP932_COLOR_SPACE_CONTROL__422_OUT);

+			DBG_PRINTK(("Set to YCC422 Out\r\n"));

+			break;

+	}

+

+	// Color Space

+	switch(params->colorspace) {

+		default:

+	 	case COLORSPACE_601:

+			// Set to 601

+			ep932_reg_clear_bit(EP932_COLOR_SPACE_CONTROL, EP932_COLOR_SPACE_CONTROL__COLOR);

+			DBG_PRINTK(("Set to 601 color definition\r\n"));

+			break;

+

+	 	case COLORSPACE_709:

+			// Set to 709

+			ep932_reg_set_bit(EP932_COLOR_SPACE_CONTROL, EP932_COLOR_SPACE_CONTROL__COLOR);

+			DBG_PRINTK(("Set to 709 color definition\r\n"));

+			break;

+	}

+

+	//

+	// Update AVI Info Frame

+	//

+	// Read AVI Info Frame

+	memset(temp_data, 0x00, 14);

+	//temp_data[1] &= 0x60;

+	switch(params->formatout) {

+		default:

+	 	case COLORFORMAT_RGB:

+			// Set AVI Info Frame to RGB

+			temp_data[1] |= 0x00; // RGB

+			break;

+

+	 	case COLORFORMAT_YCC444:

+			// Set AVI Info Frame to RGB

+			temp_data[1] |= 0x40; // YCC 444

+			break;

+	 	case COLORFORMAT_YCC422:

+			// Set AVI Info Frame to RGB

+			temp_data[1] |= 0x20; // YCC 422

+			break;

+	}

+	temp_data[1] |= 0x10; // Active Format Information

+	//temp_data[2] &= 0xC0;

+

+//	temp_data[1] |= 0x02; // underscan

+//	temp_data[1] |= 0x01; // overderscan

+	

+	switch(params->colorspace) {

+		default:

+	 	case COLORSPACE_601:

+			// Set AVI Info Frame to 601

+			temp_data[2] |= 0x40;

+			break;

+

+	 	case COLORSPACE_709:

+			// Set AVI Info Frame to 709

+			temp_data[2] |= 0x80;

+			break;

+	}

+	//temp_data[2] &= 0x30;

+	if(params->videosettingindex < ep932_vdo_settings_max) {

+		temp_data[2] |= ep932_vdo_settings[params->videosettingindex].ar_pr & 0x30;

+	}

+	//temp_data[2] &= 0x0F;

+	temp_data[2] |= params->afarate & 0x0F;

+	if(params->videosettingindex < EP932_VDO_SETTINGS_IT_START) {

+		temp_data[4] |= ep932_vdo_settings[params->videosettingindex].videocode;

+	}

+	if(params->videosettingindex < ep932_vdo_settings_max) {

+		temp_data[5] |= (ep932_vdo_settings[params->videosettingindex].ar_pr & 0x0C) >> 2;

+	}

+

+	// Write AVI Info Frame

+	temp_data[0] = 0x91;

+	for(i=1; i<6; ++i) {

+		temp_data[0] += temp_data[i];

+	}

+	temp_data[0] = ~(temp_data[0] - 1);

+	ep932_reg_write(EP932_AVI_PACKET, temp_data, 14);

+

+	DBG_PRINTK(("AVI Info: "));

+	for(i=0; i<6; ++i) {

+		DBG_PRINTK(("0x%02x, ", (int)temp_data[i] ));

+	}

+	DBG_PRINTK(("\r\n"));

+

+	//

+	// Enable Video

+	//

+	ep932_reg_set_bit(EP932_IIS_CONTROL, EP932_IIS_CONTROL__AVI_EN);

+}

+

+void hdmi_tx_audio_config(pado_params params)

+{

+	int i;

+	unsigned char n_cts_index;

+	unsigned long n_value, cts_value;

+	adsfreq final_frequency;

+	unsigned char final_ads_rate;

+

+	DBG_PRINTK(("\r\nStart Tx Audio Config\r\n"));

+

+	//

+	// Audio Settings

+	//

+	// Update WS_M, WS_POL, SCK_POL

+	ep932_reg_read(EP932_IIS_CONTROL, temp_data, 1);

+	temp_data[0] &= ~0x07;

+	temp_data[0] |= params->interface & 0x07;

+	ep932_reg_write(EP932_IIS_CONTROL, temp_data, 1);

+

+	// Update Channel Status

+	if(params->interface & 0x08) { // IIS

+

+		temp_data[0] = 0;

+		// Update Flat | IIS

+		temp_data[0] |= ep932_ado_settings[params->channelnumber].flat;

+		// Update Channel.number

+		if(params->channelnumber > 1) {	// 3 - 8 channel

+			temp_data[0] |= EP932_PACKET_CONTROL__LAYOUT;

+		}

+		ep932_reg_write(EP932_PACKET_CONTROL, temp_data, 1); // Clear IIS

+		temp_data[0] |= EP932_PACKET_CONTROL__IIS;

+		ep932_reg_write(EP932_PACKET_CONTROL, temp_data, 1); // Set   IIS

+		

+

+		// Downsample Convert

+		final_ads_rate = params->adsrate;

+		switch(params->adsrate) {

+			default:

+			case 0: // Bypass

+				DBG_PRINTK(("Audio ADS = 0\r\n"));

+				final_ads_rate = 0;

+				final_frequency = params->inputfrequency;

+				break;

+			case 1: // 1/2

+				DBG_PRINTK(("Audio ADS = 1_2\r\n"));

+				switch(params->inputfrequency) {

+					default: // Bypass

+						//DBG_PRINTK(("Audio ADS = 0\r\n"));

+						final_ads_rate = 0;

+						final_frequency = params->inputfrequency;

+						break;

+					case ADSFREQ_88200HZ:

+						final_frequency = ADSFREQ_44100HZ;

+						break;

+					case ADSFREQ_96000HZ:

+						final_frequency = ADSFREQ_48000HZ;

+						break;

+					case ADSFREQ_176400HZ:

+						final_frequency = ADSFREQ_88200HZ;

+						break;

+					case ADSFREQ_192000HZ:

+						final_frequency = ADSFREQ_96000HZ;

+						break;

+				}

+				break;

+			case 2: // 1/3

+				//DBG_PRINTK(("Audio ADS = 1_3\r\n"));

+				switch(params->inputfrequency) {

+					default: // Bypass

+						//DBG_PRINTK(("Audio ADS = 0\r\n"));

+						final_ads_rate = 0;

+						final_frequency = params->inputfrequency;

+						break;

+					case ADSFREQ_96000HZ:

+						final_frequency = ADSFREQ_32000HZ;

+						break;

+				}

+				break;

+			case 3: // 1/4

+				//DBG_PRINTK(("Audio ADS = 1_4\r\n"));

+				switch(params->inputfrequency) {

+					default: // Bypass

+						//DBG_PRINTK(("Audio ADS = 0\r\n"));

+						final_ads_rate = 0;

+						final_frequency = params->inputfrequency;

+						break;

+					case ADSFREQ_176400HZ:

+						final_frequency = ADSFREQ_44100HZ;

+						break;

+					case ADSFREQ_192000HZ:

+						final_frequency = ADSFREQ_48000HZ;

+						break;

+				}

+				break;

+		}

+

+		// Update Down Sample ADSRate

+		ep932_reg_read(EP932_PIXEL_REPETITION_CONTROL, temp_data, 1);

+		temp_data[0] &= ~0x30;

+		temp_data[0] |= (final_ads_rate << 4) & 0x30;

+		ep932_reg_write(EP932_PIXEL_REPETITION_CONTROL, temp_data, 1);

+

+

+		// Set Channel Status

+		memset(temp_data, 0x00, 5);

+		temp_data[0] = (params->nocopyright)? 0x04:0x00;

+		temp_data[1] = 0x00; 			// Category code ??

+		temp_data[2] = 0x00; 			// Channel number ?? | Source number ??

+		temp_data[3] = final_frequency; 	// Clock accuracy ?? | Sampling frequency

+		temp_data[4] = 0x01; 			// Original sampling frequency ?? | Word length ??

+		ep932_reg_write(EP932_CHANNEL_STATUS, temp_data, 5);

+

+		DBG_PRINTK(("CS Info: "));

+		for(i=0; i<5; ++i) {

+			DBG_PRINTK(("0x%02X, ", (int)temp_data[i] ));

+		}

+		DBG_PRINTK(("\r\n"));

+

+		ep932_reg_set_bit(EP932_PIXEL_REPETITION_CONTROL, EP932_PIXEL_REPETITION_CONTROL__CS_M);

+	}

+	else { // SPIDIF

+

+		ep932_reg_set_bit(EP932_PACKET_CONTROL, EP932_PACKET_CONTROL__IIS);

+		ep932_reg_clear_bit(EP932_PACKET_CONTROL, EP932_PACKET_CONTROL__FLAT3 | EP932_PACKET_CONTROL__FLAT2 | EP932_PACKET_CONTROL__FLAT1 | EP932_PACKET_CONTROL__FLAT0 |

+			EP932_PACKET_CONTROL__IIS | EP932_PACKET_CONTROL__LAYOUT);

+

+		//.no Downsample

+		final_ads_rate = 0;

+		final_frequency = params->inputfrequency;

+

+		// Disable Down Sample and Bypass Channel Status

+		ep932_reg_clear_bit(EP932_PIXEL_REPETITION_CONTROL, EP932_PIXEL_REPETITION_CONTROL__ADSR | EP932_PIXEL_REPETITION_CONTROL__CS_M);

+

+		params->channelnumber = 0;

+	}

+

+	// Set.cts.n

+	if(params->videosettingindex < ep932_vdo_settings_max) {

+		n_cts_index = ep932_vdo_settings[params->videosettingindex].pix_freq_type;

+		if(ep932_vdo_settings[params->videosettingindex].hvres_type.vprd % 500) { // 59.94/60 HZ

+			n_cts_index += params->vfs;

+			DBG_PRINTK(("n_cts_index Shift %d\r\n", (int)params->vfs));

+		}

+	}

+	else {

+		DBG_PRINTK(("Use default n_cts_index\r\n"));

+		n_cts_index = PIX_FREQ_25200KHZ;

+	}

+	switch(final_frequency) {

+

+		default:

+		case ADSFREQ_32000HZ:

+			DBG_PRINTK(("Set to 32KHZ"));

+			n_value = n_cts_32k[n_cts_index].n;

+			cts_value = n_cts_32k[n_cts_index].cts;

+			break;

+		case ADSFREQ_44100HZ:

+			DBG_PRINTK(("Set to 44.1KHZ"));

+			n_value = n_cts_44k1[n_cts_index].n;

+			cts_value = n_cts_44k1[n_cts_index].cts;

+			break;

+		case ADSFREQ_48000HZ:

+			DBG_PRINTK(("Set to 48KHZ"));

+			n_value = n_cts_48k[n_cts_index].n;

+			cts_value = n_cts_48k[n_cts_index].cts;

+			break;

+		case ADSFREQ_88200HZ:

+			DBG_PRINTK(("Set to 88.2KHZ"));

+			n_value = n_cts_44k1[n_cts_index].n * 2;

+			cts_value = n_cts_44k1[n_cts_index].cts * 2;

+			break;

+		case ADSFREQ_96000HZ:

+			DBG_PRINTK(("Set to 96KHZ"));

+			n_value = n_cts_48k[n_cts_index].n * 2;

+			cts_value = n_cts_48k[n_cts_index].cts * 2;

+			break;

+		case ADSFREQ_176400HZ:

+			DBG_PRINTK(("Set to 176.4KHZ"));

+			n_value = n_cts_44k1[n_cts_index].n * 4;

+			cts_value = n_cts_44k1[n_cts_index].cts * 4;

+			break;

+		case ADSFREQ_192000HZ:

+			DBG_PRINTK(("Set to 192KHZ")); n_value = n_cts_48k[n_cts_index].n * 4;

+			cts_value = n_cts_48k[n_cts_index].cts * 4;

+			break;

+	}

+

+	DBG_PRINTK((",n[%d]=%lu(0x%lx)", n_cts_index, n_value, n_value));

+	DBG_PRINTK((",cts=%lu(0x%lx) \r\n", cts_value, cts_value));

+

+	temp_data[0] = cts_value>>16;

+	ep932_reg_write(EP932_CTS, temp_data, 1);

+	temp_data[0] = cts_value>>8;

+	ep932_reg_write(0x61, temp_data, 1);

+	temp_data[0] = cts_value;

+	ep932_reg_write(0x62, temp_data, 1);

+

+	temp_data[0] = n_value>>16;

+	ep932_reg_write(EP932_N, temp_data, 1);

+	temp_data[0] = n_value>>8;

+	ep932_reg_write(0x64, temp_data, 1);

+	temp_data[0] = n_value;

+	ep932_reg_write(0x65, temp_data, 1);

+

+// read for verify

+

+	ep932_reg_read(EP932_CTS, temp_data, 1);

+	DBG_PRINTK(("EP932_cts_0(Reg addr 0x60) = 0x%02X\r\n",(int)temp_data[0]));

+	ep932_reg_read(0x61, temp_data, 1);

+	DBG_PRINTK(("EP932_cts_1(Reg addr 0x61) = 0x%02X\r\n",(int)temp_data[0]));

+	ep932_reg_read(0x62, temp_data, 1);

+	DBG_PRINTK(("EP932_cts_2(Reg addr 0x62) = 0x%02X\r\n",(int)temp_data[0]));

+

+	ep932_reg_read(EP932_N, temp_data, 1);

+	DBG_PRINTK(("EP932_n_0(Reg addr 0x63) = 0x%02X\r\n",(int)temp_data[0]));

+	ep932_reg_read(0x64, temp_data, 1);

+	DBG_PRINTK(("EP932_n_1(Reg addr 0x64) = 0x%02X\r\n",(int)temp_data[0]));

+	ep932_reg_read(0x65, temp_data, 1);

+	DBG_PRINTK(("EP932_n_2(Reg addr 0x65) = 0x%02X\r\n",(int)temp_data[0]));

+

+	//

+	// Update ADO Info Frame

+	//

+	// Set Default ADO Info Frame

+	memset(temp_data, 0x00, 6);

+

+	// Overwrite ADO Info Frame

+	temp_data[1] = params->channelnumber;

+	temp_data[4] = ep932_ado_settings[params->channelnumber].speakermapping;

+

+	// Write ADO Info Frame back

+	temp_data[0] = 0x8F;

+	for(i=1; i<6; ++i) {

+		temp_data[0] += temp_data[i];

+	}

+	temp_data[0] = ~(temp_data[0] - 1);

+	ep932_reg_write(EP932_ADO_PACKET, temp_data, 6);

+

+	DBG_PRINTK(("ADO Info: "));

+	for(i=0; i<6; ++i) {

+		DBG_PRINTK(("0x%02x, ", (int)temp_data[i] ));

+	}

+	DBG_PRINTK(("\r\n"));

+

+	ep932_reg_set_bit(EP932_IIS_CONTROL, EP932_IIS_CONTROL__ACR_EN | EP932_IIS_CONTROL__ADO_EN | EP932_IIS_CONTROL__AUDIO_EN);

+	//DBG_PRINTK(("66666666666666666666666666666^^^^^^^^^^^^^^^\r\n"));

+}

+

+//--------------------------------------------------------------------------------------------------

+//

+// Hardware Interface

+//

+smbus_status key_read(unsigned char byteaddr, void *data, unsigned int size)

+{

+	return iic_read(iic_key_addr, byteaddr, data, size);

+}

+

+smbus_status key_write(unsigned char byteaddr, void *data, unsigned int size)

+{

+	return iic_write(iic_key_addr, byteaddr, data, size);

+}

+

+smbus_status ep932_reg_read(unsigned char byteaddr, unsigned char *data, unsigned int size)

+{

+	return iic_read(iic_ep932_addr, byteaddr, data, size);

+}

+

+smbus_status ep932_reg_write(unsigned char byteaddr, unsigned char *data, unsigned int size)

+{

+	//DBG_PRINTK(("ep932_reg_write 0x%02X, 0x%02X\r\n",(int)byteaddr,(int)data[0]));

+	return iic_write(iic_ep932_addr, byteaddr, data, size);

+}

+

+smbus_status ep932_reg_set_bit(unsigned char byteaddr, unsigned char bitmask)

+{

+	iic_read(iic_ep932_addr, byteaddr, temp_data, 1);

+

+	// Write back to Reg Reg_Addr

+	temp_data[0] |= bitmask;

+

+	return iic_write(iic_ep932_addr, byteaddr, temp_data, 1);

+}

+

+smbus_status ep932_reg_clear_bit(unsigned char byteaddr, unsigned char bitmask)

+{

+	iic_read(iic_ep932_addr, byteaddr, temp_data, 1);

+

+	// Write back to Reg Reg_Addr

+	temp_data[0] &= ~bitmask;

+

+	return iic_write(iic_ep932_addr, byteaddr, temp_data, 1);

+}

+

+

+

+smbus_status iic_write(unsigned char iic_addr, unsigned char byteaddr, unsigned char *data, unsigned int size)

+{

+	int result = 1;

+	int trytime=10;

+	int i;

+	//DBG_PRINTK(("iic_write 0x%02X, 0x%02X\r\n",(int)byteaddr,(int)data[0]));

+	do

+	{

+	result = jz_i2c_ep932_write(byteaddr, data, size);

+	trytime--;

+	if(trytime==0)

+		break;

+	}while(result);

+	if(result != 0)

+	{

+		DBG_PRINTK(("EP932M iic_write error : 0x%02X, 0x%02X, (%d):",(int)iic_addr,(int)byteaddr, (int)size));

+		printk("EP932M iic_write error : 0x%02X, 0x%02X, (%d):",(int)iic_addr,(int)byteaddr, (int)size);

+		for(i=0; i<size; i++)

+		{

+			DBG_PRINTK((" 0x%02X",(int)data[i]));

+		}

+		DBG_PRINTK(("\r\n"));

+	}

+	

+	return result;

+

+}

+

+smbus_status iic_read(unsigned char iic_addr, unsigned char byteaddr, unsigned char *data, unsigned int size)

+{

+	int result = 1;

+

+//	result = TLGI2C_ReadReg_EP932M(iic_addr, byteaddr, data, size);

+	result = jz_i2c_ep932_read(byteaddr, data, size);

+	if(result != 0)

+	{

+		DBG_PRINTK(("EP932M iic_read error : 0x%02X, 0x%02X, 0x%02X, %d\r\n",(int)iic_addr,(int)byteaddr,(int)data[0],size));

+		printk("EP932M iic_read error : 0x%02X, 0x%02X, 0x%02X, %d\r\n",(int)iic_addr,(int)byteaddr,(int)data[0],size);

+	}

+

+	return result;

+

+}

diff --git a/drivers/video/ep932/ep932_if.h b/drivers/video/ep932/ep932_if.h
new file mode 100644
index 00000000000..e2ce96a7300
--- /dev/null
+++ b/drivers/video/ep932/ep932_if.h
@@ -0,0 +1,124 @@
+#ifndef EP932_IF_H

+#define EP932_IF_H

+

+#include <linux/string.h>

+#include <linux/kernel.h>

+#include <linux/sched.h>

+

+#include "ep932api.h"

+#include "ep932regdef.h"

+

+

+typedef enum {

+	COLORSPACE_601 = 1,

+	COLORSPACE_709

+} colorspace_t;

+

+typedef enum {

+	SYNCMODE_HVDE = 0,

+	SYNCMODE_HV,

+	SYNCMODE_EMBEDED

+} syncmode_t;

+

+typedef enum {

+	COLORFORMAT_RGB = 0,

+	COLORFORMAT_YCC444,

+	COLORFORMAT_YCC422

+} colorformat_t;

+

+typedef enum {

+	AFAR_VIDEOCODE = 0,

+	AFAR_4_3,

+	AFAR_16_9,

+	AFAR_14_9

+} afar;

+

+// video output congif params

+typedef struct _vdo_params {

+	unsigned char 			interface;			// DK[3:1], DKEN, DSEL, BSEL, EDGE, FMT12

+	unsigned char 			videosettingindex;	// VIC

+	unsigned char 			hvpol;				// x, x, x, x, VSO_POL, HSO_POL, x, x

+	syncmode_t 		syncmode;			// 0 = HVDE, 1 = HV(DE Gen), 2 = Embedded Sync

+	colorformat_t 	formatin;			// 0 = RGB, 1 = YCC444, 2 = YCC422

+	colorformat_t 	formatout;			// 0 = RGB, 1 = YCC444, 2 = YCC422

+// Which don't cause Timing Chage Reset

+	colorspace_t 		colorspace;			// 0 = Auto, 1 = 601, 2 = 709

+	afar 			afarate;			// 0 = Auto, 1 = 4:3, 2 = 16:9, 3 = 14:9

+} vdo_params, *pvdo_params;

+

+typedef enum {

+	ADSFREQ_32000HZ = 0x03,

+	ADSFREQ_44100HZ = 0x00,

+	ADSFREQ_48000HZ = 0x02,

+	ADSFREQ_88200HZ = 0x08,

+	ADSFREQ_96000HZ = 0x0A,

+	ADSFREQ_176400HZ = 0x0C,

+	ADSFREQ_192000HZ = 0x0E

+} adsfreq;

+

+// Audio Output Congif Params

+typedef struct _ado_params {

+	unsigned char 		interface;				// x, x, x, x, IIS, WS_M, WS_POL, SCK_POL

+	unsigned char 		videosettingindex;		// VIC

+	unsigned char 		channelnumber;			// 1 = 2 ch, 2 = 3 ch, ... , 5 = 5.1 ch, 7 = 7.1 ch

+	unsigned char 		adsrate;				// 1 = SF/2, 2 = SF/3, 3 = SF/4 (Down Sample)

+	adsfreq			inputfrequency;			// ADSFREQ

+	unsigned char       	vfs; 					// 0 = 59.94Hz, 1 = 60Hz (Vertical Frequency Shift of Video)

+	unsigned char 		nocopyright;

+} ado_params, *pado_params;

+

+extern void ep932_if_initial(void);

+extern void ep932_if_reset(void);

+

+

+

+// Common

+extern void hdmi_tx_power_down(void);

+extern void hdmi_tx_power_up(void);

+extern void hdmi_tx_hdmi(void);

+extern void hdmi_tx_dvi(void);

+extern unsigned char hdmi_tx_htplg(void);

+extern unsigned char hdmi_tx_rsen(void);

+

+// HDCP

+extern void hdmi_tx_mute_enable(void);

+extern void hdmi_tx_mute_disable(void);

+extern void hdmi_tx_hdcp_enable(void);

+extern void hdmi_tx_hdcp_disable(void);

+extern void hdmi_tx_rptr_set(void);

+extern void hdmi_tx_rptr_clear(void);

+extern unsigned char hdmi_tx_ri_rdy(void);

+extern void hdmi_tx_write_an(unsigned char *pan);

+extern unsigned char hdmi_tx_aksv_rdy(void);

+extern unsigned char hdmi_tx_read_aksv(unsigned char *paksv);

+extern void hdmi_tx_write_bksv(unsigned char *pbksv);

+extern unsigned char hdmi_tx_read_ri(unsigned char *pri);

+extern void hdmi_tx_read_m0(unsigned char *pm0);

+smbus_status hdmi_tx_get_key(unsigned char *key);

+

+// special for EP932E

+extern void hdmi_tx_amute_enable(void);

+extern void hdmi_tx_amute_disable(void);

+extern void hdmi_tx_vmute_enable(void);

+extern void hdmi_tx_vmute_disable(void);

+extern void hdmi_tx_video_config(pvdo_params params);

+extern void hdmi_tx_audio_config(pado_params params);

+

+

+

+// hardware interface

+

+// EP932

+smbus_status key_read(unsigned char byteaddr, void *data, unsigned int size);

+

+smbus_status key_write(unsigned char byteaddr, void *data, unsigned int size);

+

+smbus_status ep932_reg_read(unsigned char byteaddr, unsigned char *data, unsigned int size);

+smbus_status ep932_reg_write(unsigned char byteaddr, unsigned char *data, unsigned int size);

+smbus_status ep932_reg_set_bit(unsigned char byteaddr, unsigned char bitmask);

+smbus_status ep932_reg_clear_bit(unsigned char byteaddr, unsigned char bitmask);

+

+

+#endif // EP932_IF_H

+

+

diff --git a/drivers/video/ep932/ep932api.c b/drivers/video/ep932/ep932api.c
new file mode 100644
index 00000000000..9d1c23ada28
--- /dev/null
+++ b/drivers/video/ep932/ep932api.c
@@ -0,0 +1,282 @@
+#include <linux/module.h>
+#include <linux/sched.h>
+
+#include <asm/jzsoc.h>
+#include <linux/timer.h>
+#include "ep932api.h"
+#include "ep932controller.h"  // HDMI Transmiter
+
+#define      IIC_EP932E 0x70
+#define      EP932M_RESET_PIN (32*4+11)
+#define      EP932M_5VEN_PIN (32*5+6)
+int hdmi_power_on= 0;
+int hdmi_init=1;
+int restart_system;
+int hdmi_terminate_flag=1;
+struct timer_list ep932_timer; 
+int hdmi_delay = 2;
+int hdmi_hg_out = 0;
+
+ep932c_register_map ep932c_registers;
+
+void ep_ep932m_reset(void)
+{
+	__gpio_as_output(EP932M_RESET_PIN);
+	__gpio_clear_pin(EP932M_RESET_PIN);	// set to output low
+
+	mdelay(400);		// Delay 10ms.
+
+	__gpio_set_pin(EP932M_RESET_PIN);
+	mdelay(400);		// Delay 10ms.
+}
+
+#undef printk
+
+void hdmi_main (void)
+{
+	   if(hdmi_power_on == 0){
+				//printk("EP932Controller ****************************\n");
+				if((hdmi_init == 0) || (hdmi_hg_out == 3 )){
+					mod_timer(&ep932_timer,jiffies+3*100);
+				}
+				else{
+					mod_timer(&ep932_timer,jiffies+hdmi_delay);
+				}
+				hdmi_hg_out = ep932controller_task();
+				ep932controller_timer();
+	   }
+	   else{
+	   	
+	   }
+   return;
+}
+
+
+void ep_hdmi_setaudfmt(hdmi_audfmt_t aud_fmt, hdmi_audfreq  aud_freq)
+{
+	if(aud_fmt == AUD_I2S)
+	{
+		ep932c_registers.audio_interface = 0x18;		// 2 channel IIS
+		//DBG_PRINTK(("Audio interface is IIS - 2.0 CH, "));
+	}
+	else
+	{
+		ep932c_registers.audio_interface = 0x10;		// SPDIF
+		//DBG_PRINTK(("Audio interface is SPDIF, "));
+	}
+
+	if(aud_freq == 0)
+	{
+		ep932c_registers.system_configuration = 0x02;
+		//DBG_PRINTK(("(AUDIO MUTE)"));
+	}
+	else
+	{
+		ep932c_registers.system_configuration = 0x00;
+	}
+	ep932c_registers.audio_input_format = aud_freq;	// set Audio frequency
+	DBG_PRINTK(("freq = "));
+	switch(aud_freq)
+	{
+		case AUD_SF_32000HZ:
+			DBG_PRINTK(("32K HZ\r\n"));
+			break;
+			
+		case AUD_SF_44100HZ:
+			DBG_PRINTK(("44.1K HZ\r\n"));
+			break;
+			
+		case AUD_SF_48000HZ:
+			DBG_PRINTK(("48K HZ\r\n"));
+			break;
+			
+		case AUD_SF_88200HZ:
+			DBG_PRINTK(("88.2K HZ\r\n"));
+			break;
+			
+		case AUD_SF_96000HZ:
+			DBG_PRINTK(("96K HZ\r\n"));
+			break;
+			
+		case AUD_SF_176400HZ:
+			DBG_PRINTK(("176.4K HZ\r\n"));
+			break;
+			
+		case AUD_SF_192000HZ:
+			DBG_PRINTK(("192K HZ\r\n"));
+			break;
+			
+	}
+}
+
+void ep_hdmi_set_video_timing(int timing)
+{
+
+	unsigned char temp_setting = 0;
+
+	DBG_PRINTK(("\r\n\r\n"));
+
+	switch (timing)
+	{
+/*
+		case 0: //TVOUT_MODE_576I:
+			DBG_PRINTK(("TVOUT_MODE_576I\r\n"));
+			ep932c_registers.video_input_format[0] = 0x15;
+			ep932c_registers.video_interface[0] = 0x8E;//0x81;
+			ep932c_registers.video_interface[1] = 0x00;//0x0a;
+
+			ep932c_registers.power_control = 0x00;
+			break;
+
+	   case 1: //TVOUT_MODE_480I:
+		    DBG_PRINTK(("TVOUT_MODE_480I\r\n"));
+			ep932c_registers.video_input_format[0] = 0x06;
+			ep932c_registers.video_interface[0] = 0x8E;//0x81;
+			ep932c_registers.video_interface[1] = 0x00;//0x0a;
+
+			ep932c_registers.power_control = 0x00;
+			break;
+
+*/
+		default:
+        case 3: //TVOUT_MODE_480P:
+			DBG_PRINTK(("EP932M_MODE H.V.DE mode - (480P output test)\r\n"));
+			ep932c_registers.video_input_format[0] = 0x00;	// video format timing
+			
+			temp_setting =EDGE_RISING | BSEL_24BIT /*| EDGE_RISING */ /*| FMT_12*/;
+			ep932c_registers.video_interface[0] = temp_setting;
+			
+			DBG_PRINTK(("video_interface_0 = 0x%02X \r\n",(int)ep932c_registers.video_interface[0] ));
+
+			ep932c_registers.video_interface[1] = 0x00; 	// DE,HS,VS, RGB444
+			
+			ep932c_registers.power_control = 0x00;
+			break;
+		case 4: //TVOUT_MODE_576P:
+		    DBG_PRINTK(("TVOUT_MODE_576P\r\n"));
+			ep932c_registers.video_input_format[0] = 0x11;
+			ep932c_registers.video_interface[0] = 0x8E;//0x84;
+			ep932c_registers.video_interface[1] = 0x00;//0x0a;
+
+			ep932c_registers.power_control = 0x00;
+		    break;
+		case 5: //TVOUT_MODE_720P50:
+			DBG_PRINTK(("TVOUT_MODE_720P50\r\n"));
+			ep932c_registers.video_input_format[0] = 0x13;
+			ep932c_registers.video_interface[0] = 0x86;
+			ep932c_registers.video_interface[1] = 0x00;//0x0a;
+
+			ep932c_registers.power_control = 0x00;
+			break;
+
+		 case 6: //TVOUT_MODE_720P60:
+			DBG_PRINTK(("TVOUT_MODE_720P60\r\n"));
+			ep932c_registers.video_input_format[0] = 0x04;
+			ep932c_registers.video_interface[0] = 0x86;
+			ep932c_registers.video_interface[1] = 0x00;//0x0a;
+
+			ep932c_registers.power_control = 0x00;
+			break;
+
+/*
+		case 6: //TVOUT_MODE_1080I25:
+		    DBG_PRINTK(("TVOUT_MODE_1080I25\r\n"));
+			ep932c_registers.video_input_format[0] = 0x14;
+			ep932c_registers.video_interface[0] = 0x84;
+			ep932c_registers.video_interface[1] = 0x00;//0x0a;
+
+			ep932c_registers.power_control = 0x00;
+			break;
+
+		case 7: //TVOUT_MODE_1080I30:
+		    DBG_PRINTK(("TVOUT_MODE_1080I30\r\n"));
+			ep932c_registers.video_input_format[0] = 0x05;
+			ep932c_registers.video_interface[0] = 0x84;
+			ep932c_registers.video_interface[1] = 0x00;//0x0a;
+
+			ep932c_registers.power_control = 0x00;
+			break;
+
+		case 8: //TVOUT_MODE_480P:
+			DBG_PRINTK(("TVOUT_MODE_480P\r\n"));
+			ep932c_registers.video_input_format[0] = 0x02;
+			ep932c_registers.video_interface[0] = 0x83;//0x84;
+			ep932c_registers.video_interface[1] = 0x00;//0x0a;
+
+			ep932c_registers.power_control = 0x00;
+			break;
+*/
+   	}
+
+	ep_hdmi_setaudfmt(AUD_I2S, AUD_SF_44100HZ);
+//	ep_hdmi_setaudfmt(AUD_I2S, 0);
+
+	DBG_PRINTK(("##############################################\r\n"));
+
+}
+unsigned char ep_hdmi_deinit(void)
+{
+   
+	ep_ep932m_reset();
+}
+unsigned char ep_hdmi_init(void)
+{
+
+//	int err;
+
+//	__gpio_as_output(EP932M_5VEN_PIN);
+//	__gpio_set_pin(EP932M_5VEN_PIN);
+
+	ep_ep932m_reset();
+	
+  
+	ep932controller_initial(&ep932c_registers, NULL);
+
+/*
+    err= pthread_create(&hdmi_tid, NULL, hdmi_main, NULL);	// for linux
+    if (err !=0){
+        printk("can't create hdmi thread: %s \n", strerror(err));
+        return 1; //HDMI_ERROR_INIT;
+    }
+	else
+	{
+        printk("create hdmi main thread ok\n");
+	}
+*/
+	return 0; //HDMI_SUCCESS;
+}
+
+void hdmi_test()
+{
+	add_timer(&ep932_timer);
+}
+
+void hdmi_start(int video_timing)
+{
+	ep_hdmi_init();				// Variables initial	
+	ep_hdmi_set_video_timing(video_timing);		// Video set to H.V.DE mode #
+	hdmi_init = 1; 
+	init_timer(&ep932_timer);
+	ep932_timer.function=&hdmi_main;
+	ep932_timer.expires=jiffies+hdmi_delay;
+	add_timer(&ep932_timer);
+}
+void hdmi_stop()
+{
+	del_timer(&ep932_timer);
+	mdelay(400);
+	ep_hdmi_deinit();
+}
+
+/*
+void hdmi_exit(void)
+{
+cleariisoutput();
+os_TaskDelete(PRIO_hdmi_TASK);
+deAlloc(TaskhdmiStk);
+lcd_reinit_lcd();
+}
+*/
+EXPORT_SYMBOL(hdmi_test);
+EXPORT_SYMBOL(hdmi_start);
+EXPORT_SYMBOL(hdmi_stop);
diff --git a/drivers/video/ep932/ep932api.h b/drivers/video/ep932/ep932api.h
new file mode 100644
index 00000000000..6a75028da3c
--- /dev/null
+++ b/drivers/video/ep932/ep932api.h
@@ -0,0 +1,59 @@
+#ifndef EP932_API_H

+#define EP932_API_H

+

+#include <linux/kernel.h>

+

+

+#define DBG_PRINTK(x) printk x

+//#define DBG_PRINTK(x) 

+

+#ifndef min

+#define min((a), (b))	((a) > (b)) ? (a) : (b)

+#endif

+

+typedef enum {

+	// Master

+	SMBUS_STATUS_SUCCESS = 0x00,

+	SMBUS_STATUS_PENDING,//	SMBUS_STATUS_Abort,

+	SMBUS_STATUS_NOACT = 0x02,

+	SMBUS_STATUS_TIMEOUT,

+	SMBUS_STATUS_ARBITRATIONLOSS = 0x04

+}smbus_status;

+

+

+typedef enum {

+	AUD_SF_32000HZ = 1,

+	AUD_SF_44100HZ,

+	AUD_SF_48000HZ,

+	AUD_SF_88200HZ,

+	AUD_SF_96000HZ,

+	AUD_SF_176400HZ,

+	AUD_SF_192000HZ

+} hdmi_audfreq;

+

+

+typedef enum{

+	AUDIOMUTE_DISABLE = 0,

+	AUDIOMUTE_ENALBE = 1

+} cstvout_audio_mode;

+	

+

+typedef enum {

+	AUD_I2S = 0,

+	AUD_SPDIF	

+}hdmi_audfmt_t;

+

+#define DSEL_DUAL_EDGE		0x08

+#define BSEL_24BIT		0x04

+#define EDGE_RISING		0x02

+#define FMT_12			0x01

+

+

+

+void ep_ep932m_reset(void);

+void hdmi_main (void);

+void ep_hdmi_setaudfmt(hdmi_audfmt_t  audfmt, hdmi_audfreq audfreq);

+void ep_hdmi_set_video_timing(int timing);

+unsigned char ep_hdmi_init(void); 

+

+#endif

diff --git a/drivers/video/ep932/ep932controller.c b/drivers/video/ep932/ep932controller.c
new file mode 100644
index 00000000000..583eb7a113f
--- /dev/null
+++ b/drivers/video/ep932/ep932controller.c
@@ -0,0 +1,1028 @@
+#include <linux/kernel.h>

+#include <linux/delay.h>

+

+#include "ep932api.h"

+#include "edid.h"

+#include "ddc_if.h"

+#include "ep932controller.h"

+#include "ep932settingsdata.h"

+

+#include "./i2c_drivers/hdmi.h"

+

+#define AV_STABLE_TIME            1000

+

+typedef enum {

+	TXS_SEARCH_EDID,

+	TXS_WAIT_UPSTREAM,

+	TXS_STREAM,

+	TXS_HDCP

+} tx_state_t;

+

+// HDCP Key  

+unsigned char hdcp_key[64][8];

+

+extern ep932c_register_map ep932c_registers;

+

+

+unsigned char is_cap_hdmi;

+unsigned char is_cap_ycc444;

+unsigned char is_cap_ycc422;

+unsigned char is_connected;

+unsigned char is_receiver_sense;

+

+unsigned char is_timing_changing;

+unsigned char is_video_changing;

+unsigned char is_audio_changing;

+unsigned char is_hdcp_info_bksv_rdy;

+unsigned char is_hot_plug;

+

+

+// temp data

+unsigned char chksum, vc_temp, connection_state;

+

+unsigned char htplg_now = 0, htplg_last = 0;

+

+

+// system data

+tx_state_t tx_state;

+unsigned int htp_time_count, videochg_time_count, audiochg_time_count, read_edid_time_count;

+unsigned char process_dispatch_id;

+

+unsigned char hp_change_count, rsen_change_count, backup_analog_test_control;

+

+vdo_params video_params;

+ado_params audio_params;

+unsigned char gamut_packet_header_backup[3];

+

+// Register

+pep932c_register_map pep932c_registers;

+

+// Private Functions

+void ep932controller_reset(void);

+

+void txs_rollback_wait_upstream(void);

+void txs_rollback_stream(void);

+void txs_rollback_hdcp(void);

+

+// Hardware

+void read_interruput_flags(void);

+//void On_HDMI_Int();

+void  ep_hdmi_dump_message(void);

+

+ep932c_callback ep932c_generateint;

+

+void ep932controller_initial(pep932c_register_map pep932c_regmap, ep932c_callback intcall)

+{

+	// Save the Logical Hardware Assignment

+	pep932c_registers = pep932c_regmap;

+	ep932c_generateint = intcall;

+

+	ep_ep932m_reset();

+	

+	ep932_if_initial();

+

+	is_cap_hdmi = 0;

+	is_cap_ycc444 = is_cap_ycc422 = 0;

+	is_connected = 0;

+	is_video_changing = 0;

+	is_audio_changing = 0;

+

+	tx_state = TXS_SEARCH_EDID;

+	htp_time_count = 0;

+	process_dispatch_id = 0;

+	videochg_time_count = 0;

+	audiochg_time_count = 0;

+	read_edid_time_count = 0;

+	hp_change_count = 0;

+	rsen_change_count = 0; 

+	memset(gamut_packet_header_backup, 0, 3);

+

+	// Reset all EP932C registers

+	memset(pep932c_registers, 0, sizeof(ep932c_register_map));

+	pep932c_registers->video_interface[0] = 0x80;

+	pep932c_registers->power_control = EP932E_POWER_CONTROL__PD_HDMI;

+	pep932c_registers->audio_interface = 0x10; // 2 Channel audio

+

+	// Update Version Registers

+	pep932c_registers->vendorid = 0x177A;

+	pep932c_registers->deviceid = 0x0932;

+	pep932c_registers->version_major = VERSION_MAJOR;

+	pep932c_registers->version_minor = VERSION_MINOR;

+	DBG_PRINTK(("Version %d.%d\r\n", (int)VERSION_MAJOR, (int)VERSION_MINOR ));

+	// Initial HDCP Info

+	memset(pep932c_registers->hdcp_aksv, 0x00, sizeof(pep932c_registers->hdcp_aksv));

+	memset(pep932c_registers->hdcp_bksv, 0x00, sizeof(pep932c_registers->hdcp_bksv));

+	

+	ep932_reg_read(EP932_CONFIGURATION, ddc_data, 1);

+

+	// Set Revocation List address

+	hdcp_extract_bksv_bcaps3(pep932c_registers->hdcp_bksv);

+	hdcp_extract_fifo((unsigned char*)pep932c_registers->hdcp_ksv_fifo, sizeof(pep932c_registers->hdcp_ksv_fifo));

+	hdcp_stop();

+

+	// Reset EP932 Control Program

+	ep932controller_reset();

+}

+

+void ep932controller_reset(void)

+{

+	smbus_status status = SMBUS_STATUS_SUCCESS;

+

+	// Reset Hardware

+	DBG_PRINTK(("Reset EP932\r\n"));

+

+	ep_ep932m_reset();

+	

+	// Initial Variables

+	ep932_reg_set_bit(EP932_PIXEL_REPETITION_CONTROL, EP932_PIXEL_REPETITION_CONTROL__OSCSEL);

+

+	// Read HDCP Key for EEPROM

+#if 0

+	    	if(!hdmi_tx_read_aksv(pep932c_registers->hdcp_aksv)) ;

+/*

+	while (1) {

+	status = hdmi_tx_get_key((unsigned char *)hdcp_key);

+	for (i = 0; i < 64; i++) {

+		int j;

+		for (j = 0; j < 8; j++)

+			printk("0x%08x,", hdcp_key[i][j]);

+		printk("\n");

+	}

+	DBG_PRINTK(("Read HDCP Key = %d\r\n",(int)status));

+	HDCP_Fake(0);

+	mdelay(10000);

+}

+*/

+#endif

+	pep932c_registers->system_status &= ~EP932E_SYSTEM_STATUS__KEY_FAIL;

+

+

+	pep932c_registers->system_configuration |= EP932E_SYSTEM_CONFIGURATION__HDCP_DIS;

+

+#if 0

+	// Check HDCP key and up load the key

+	if(status) {

+		// Do not upload the default Key!

+		pep932c_registers->system_configuration |= EP932E_SYSTEM_CONFIGURATION__HDCP_DIS;

+		pep932c_registers->system_status |= EP932E_SYSTEM_STATUS__KEY_FAIL;

+		DBG_PRINTK(("No HDCP Key\r\n"));

+	}

+	else {

+		// Check HDCP key and up load the key

+		chksum = 0;

+		for(i=0; i<328; ++i) {

+			chksum += *((unsigned char *)hdcp_key+i);

+		}	

+		DBG_PRINTK(("HDCP Key Check Sum 0x%02X\r\n", (int)chksum ));

+		if(hdcp_key[3][7] != 0x50 || hdcp_key[12][7] != 0x01 || chksum != 0x00) {// || hdcp_key[40][0] != 0xA5) {

+			HDCP_Fake(1);

+			pep932c_registers->system_status |= EP932E_SYSTEM_STATUS__KEY_FAIL;

+			DBG_PRINTK(("Check Key failed!\r\n"));

+			pep932c_registers->system_configuration |= EP932E_SYSTEM_CONFIGURATION__HDCP_DIS;

+			//DBG_PRINTK(("Disable HDCP \r\n"));

+		}

+		else {

+			// Upload the key 0-39

+			for(i=0; i<40; ++i) {

+				ddc_data[0] = (unsigned char)i;

+				status |= ep932_reg_write(EP932_Key_Add, ddc_data, 1);

+				memcpy(ddc_data,&hdcp_key[i][0],7);

+				status |= ep932_reg_write(EP932_Key_Data, ddc_data, 7);

+			}

+			// Read and check	

+			for(i=0; i<40; ++i) {

+				ddc_data[0] = (unsigned char)i;

+				status |= ep932_reg_write(EP932_Key_Add, ddc_data, 1);

+				status |= ep932_reg_read(EP932_Key_Data, ddc_data, 7);

+				if((memcmp(ddc_data,&hdcp_key[i][0],7) != 0) || status) {

+					// Test failed

+					HDCP_Fake(1);

+					pep932c_registers->system_status |= EP932E_SYSTEM_STATUS__KEY_FAIL;

+					DBG_PRINTK(("Check Key failed!\r\n"));

+					pep932c_registers->system_configuration |= EP932E_SYSTEM_CONFIGURATION__HDCP_DIS;

+					//DBG_PRINTK(("Disable HDCP \r\n"));

+					break;

+				}

+			}

+			// Upload final KSV 40

+			ddc_data[0] = 40;

+			status |= ep932_reg_write(EP932_Key_Add, ddc_data, 1);

+			memcpy(ddc_data,&hdcp_key[40][0],7);

+			status |= ep932_reg_write(EP932_Key_Data, ddc_data, 7);

+			// Read back and check

+	    	if(!hdmi_tx_read_aksv(pep932c_registers->hdcp_aksv)) {

+				// Test failed

+				HDCP_Fake(1);

+				pep932c_registers->system_status |= EP932E_SYSTEM_STATUS__KEY_FAIL;

+				DBG_PRINTK(("Check KSV failed!\r\n"));

+				pep932c_registers->system_configuration |= EP932E_SYSTEM_CONFIGURATION__HDCP_DIS;

+				//DBG_PRINTK(("Disable HDCP \r\n"));

+			}

+		}	

+	}

+#endif

+	ep932_if_reset();

+

+	is_receiver_sense = 0;

+

+	// data

+	backup_analog_test_control = 0;

+	if(tx_state > TXS_SEARCH_EDID) {

+		DBG_PRINTK(("\r\nState Transist: Reset -> [TXS_WAIT_UPSTREAM]\r\n"));

+		tx_state = TXS_WAIT_UPSTREAM;

+	}

+

+	DBG_PRINTK(("ep932controller_reset finish\r\n"));

+}

+

+void ep932controller_timer(void)

+{

+	++htp_time_count;

+	if(is_video_changing) ++videochg_time_count;

+	if(is_audio_changing) ++audiochg_time_count;

+	if(tx_state == TXS_HDCP) hdcp_timer();

+	++read_edid_time_count;

+}

+extern int hdmi_hg_out;

+extern int hdmi_init;

+unsigned char ep932controller_task(void)

+{

+

+	// Read Interrupt Flag and updat the internal information

+	read_interruput_flags();

+	// Polling Hot-Plug every 80ms

+	//if((htp_time_count > 800/EP932C_TIMER_PERIOD) || hdmi_init == 0) {

+	if(1) {

+		htp_time_count = 0;

+		

+		connection_state = hdmi_tx_htplg();

+

+		htplg_now = connection_state;

+		printk("HotPlug out htplg_now:%d###\r\n",htplg_now);	

+		if(htplg_last != htplg_now)

+		{

+			htplg_last = htplg_now;

+			if(htplg_now == 0)

+			{

+				printk(("HotPlug out ###\r\n"));	

+				ep_hdmi_dump_message();				

+			}

+			else

+			{

+			   	hdmi_hg_out = 0;

+				printk(("Detect HotPlug  ###\r\n"));

+#if 0				

+				is_video_changing  =1; //hycui

+				is_audio_changing =1;

+				ep_hdmi_init();									// Variables initial	

+       	//EP_HDMI_Set_Video_Timing(3);					// Video set to H.V.DE mode 

+       //	ep932c_registers.video_input_format[0] = 0x00;	// video format timing

+			

+			//int temp_setting = 0x80 | SEL_DUAL_EDGE | BSEL_24BIT /*| EDGE_RISING */ /*| FMT_12*/;

+			int temp_setting = EDGE_RISING | BSEL_24BIT /*| EDGE_RISING */ /*| FMT_12*/;

+			pep932c_registers->video_interface[0] = temp_setting;

+			

+			//DBG_PRINTK(("video_interface_0 = 0x%02X \r\n",(int)ep932c_registers.Video_interface[0] ));

+

+		   pep932c_registers->video_interface[1] = 0x00; 	// DE,HS,VS, RGB444

+			

+		  	pep932c_registers->power_control = 0x00;

+			EP_HDMI_SetAudFmt(AUD_I2S, 0);

+#endif			

+			}

+		}

+		

+		is_hot_plug = (connection_state == 1)? 1:0;

+		if(is_connected != ((connection_state)?1:0) ) {

+			if(hp_change_count++ >= 1) { // Accept continuous 1 error = 1*80 ms = 80 ms (Skip when low period < 80 ms)

+				hp_change_count = 0;

+

+				is_connected = ((connection_state)?1:0);

+			}

+		}

+		else {

+			hp_change_count = 0;

+		}

+		if(is_hot_plug) {

+			pep932c_registers->system_status |= EP932E_SYSTEM_STATUS__HTPLG;

+		}

+		else {

+			pep932c_registers->system_status &= ~EP932E_SYSTEM_STATUS__HTPLG;

+		}

+

+		is_receiver_sense = hdmi_tx_rsen(); // Only valid when TX is powered on

+

+		if(tx_state > TXS_WAIT_UPSTREAM) { // Powered Up and have Input

+			

+			// Update RSEN

+			if(is_receiver_sense) {

+				pep932c_registers->system_status |= EP932E_SYSTEM_STATUS__RSEN;

+			}

+			else {

+				pep932c_registers->system_status &= ~EP932E_SYSTEM_STATUS__RSEN;

+			}

+			rsen_change_count = 0;

+

+			// Read HSO VSO POL information

+			ep932_reg_read(EP932_GENERAL_CONTROL_4, ddc_data, 1);

+			video_params.hvpol = ddc_data[0] & (EP932_DE_CONTROL__VSO_POL | EP932_DE_CONTROL__HSO_POL);	

+//			video_params.hvpol = 0x0C;  // for test

+		}

+		else {

+			if(rsen_change_count++ >= 8) { // Accept continuous 8 error = 8*80 ms = 640 ms (Skip when low period < 640 ms)

+				rsen_change_count = 0;

+

+				pep932c_registers->system_status &= ~EP932E_SYSTEM_STATUS__RSEN;

+			}

+		}

+	}

+

+	if((htplg_now == 0)&&(hdmi_init == 1)){

+		return EP932C_TASK_PGOUT;//EP932C_TASK_IDLE;

+	}

+	//

+	// Update EP932 Registers according to the System Process

+	//

+//	printk("tx_state [%d] [%d]###\n", TX_State, is_connected);

+	switch(tx_state) {

+		case TXS_SEARCH_EDID:

+			if(is_connected ) {

+				if(1){//(read_edid_time_count > 200/EP932C_TIMER_PERIOD) {

+					unsigned char edid_ddc_status;

+

+					// Confirm Hot-Plug (time-out after 1s)

+					if(!is_hot_plug) {

+						if(read_edid_time_count <= 1000/EP932C_TIMER_PERIOD) break;

+						DBG_PRINTK(("WARNING: EDID detected without Hot-Plug for 1s\r\n"));

+					}

+

+					// Read EDID

+					DBG_PRINTK(("\r\nState Transist: Read EDID -> [TXS_WAIT_UPSTREAM]\r\n"));				

+					memset(pep932c_registers->readed_edid, 0xff, 256);

+					edid_ddc_status = downstream_rx_read_edid(pep932c_registers->readed_edid);

+					

+					if(edid_ddc_status) {

+						//if(edid_ddc_status == EDID_STATUS_NOACT) {

+						if(edid_ddc_status != EDID_STATUS_CHECKSUMERROR) {

+							DBG_PRINTK(("WARNING: EDID read failed 0x%02X\r\n", (int)edid_ddc_status));

+							if(read_edid_time_count <= 500/EP932C_TIMER_PERIOD) break;

+						}

+					}

+					read_edid_time_count = 0;

+ 

+					// Set Output

+					if(pep932c_registers->system_configuration & EP932E_SYSTEM_CONFIGURATION__FORCE_HDMI_CAP) {

+						is_cap_hdmi = 1;

+					}

+					else {

+						is_cap_hdmi = edid_gethdmicap(pep932c_registers->readed_edid);

+					}

+					if(is_cap_hdmi) {			

+						DBG_PRINTK(("Support HDMI"));

+

+						// Default Capability

+						is_cap_ycc444 =	is_cap_ycc422 = 0;

+						pep932c_registers->edid_asfreq = 0x07;

+						pep932c_registers->edid_achannel = 1;

+

+						pep932c_registers->edid_videodataaddr = 0x00;

+						pep932c_registers->edid_audiodataaddr = 0x00;

+						pep932c_registers->edid_speakerdataaddr = 0x00;

+						pep932c_registers->edid_vendordataaddr = 0x00;

+

+						if(!edid_ddc_status) {

+

+							if(pep932c_registers->readed_edid[131] & 0x20) {	// Support YCC444

+								is_cap_ycc444 = 1;

+								DBG_PRINTK((" YCC444"));

+							}

+							if(pep932c_registers->readed_edid[131] & 0x10) {	// Support YCC422

+								is_cap_ycc422 = 1;

+								DBG_PRINTK((" YCC422"));

+							}

+							DBG_PRINTK(("\r\n"));

+							pep932c_registers->edid_asfreq = edid_getpcmfreqcap(pep932c_registers->readed_edid);

+							DBG_PRINTK(("EDID ASFreq = 0x%02X\r\n",(int)pep932c_registers->edid_asfreq));

+

+							pep932c_registers->edid_achannel = edid_getpcmchannelcap(pep932c_registers->readed_edid);

+							DBG_PRINTK(("EDID AChannel = 0x%02X\r\n",(int)pep932c_registers->edid_achannel));

+

+							pep932c_registers->edid_videodataaddr = edid_getdatablockaddr(pep932c_registers->readed_edid, 0x40);

+							pep932c_registers->edid_audiodataaddr = edid_getdatablockaddr(pep932c_registers->readed_edid, 0x20);

+							pep932c_registers->edid_speakerdataaddr = edid_getdatablockaddr(pep932c_registers->readed_edid, 0x80);

+							pep932c_registers->edid_vendordataaddr = edid_getdatablockaddr(pep932c_registers->readed_edid, 0x60);

+						}

+					}

+					else {

+						DBG_PRINTK(("Support DVI RGB only\r\n"));

+						is_cap_ycc444 =	is_cap_ycc422 = 0;

+						pep932c_registers->edid_asfreq = pep932c_registers->edid_achannel = 0;

+					}

+

+					if(is_cap_hdmi)

+						pep932c_registers->edid_status = edid_ddc_status | EP932E_EDID_STATUS__HDMI;

+					else

+						pep932c_registers->edid_status = edid_ddc_status;

+					DBG_PRINTK(("Support Max Audio Channel %d\r\n", (int)pep932c_registers->edid_achannel+1));

+					DBG_PRINTK(("Support Audio Freq 0x%02X\r\n", (int)pep932c_registers->edid_asfreq));

+

+					// Report EDID Change

+					pep932c_registers->interrupt_flags |= EP932E_INTERRUPT_FLAGS__EDID_CHG;

+					if(ep932c_generateint && (pep932c_registers->interrupt_enable & EP932E_INTERRUPT_ENABLE__EDID_CHG) ) ep932c_generateint();

+	

+					tx_state = TXS_WAIT_UPSTREAM;

+				}

+			}

+			else {	

+				pep932c_registers->edid_status = EDID_STATUS_NOACT;

+				read_edid_time_count = 0;

+			}

+			break;

+			

+		case TXS_WAIT_UPSTREAM:

+

+			if(!is_connected) {

+

+				txs_rollback_wait_upstream();

+				tx_state = TXS_SEARCH_EDID;

+			}

+			else if(!(pep932c_registers->power_control & (EP932E_POWER_CONTROL__PD_HDMI | EP932E_POWER_CONTROL__PD_TOT)) ) {

+				DBG_PRINTK(("\r\nState Transist: Power Up -> [TXS_STREAM]\r\n"));							

+

+				// Power Up

+				hdmi_tx_power_up();

+

+				tx_state = TXS_STREAM;

+			}

+			else {

+				// Check Force HDMI bit

+				if(!is_cap_hdmi) {

+					if(pep932c_registers->system_configuration & EP932E_SYSTEM_CONFIGURATION__FORCE_HDMI_CAP) {

+						txs_rollback_wait_upstream();

+						tx_state = TXS_SEARCH_EDID;

+					}

+				}

+			}

+			break;

+

+		case TXS_STREAM:

+

+			/*

+			if(!is_hdcp_info_bksv_rdy && is_receiver_sense && is_hot_plug) {

+				// Get HDCP Info

+		    	if(!Downstream_Rx_read_BKSV(pep932c_registers->hdcp_bksv)) {

+					pep932c_registers->hdcp_status = EP932E_HDCP_Status__BKSV;

+				}

+				pep932c_registers->HDCP_BCAPS3[0] = Downstream_Rx_BCAPS();

+				is_hdcp_info_bksv_rdy = 1;

+			}

+			*/

+			if(!is_connected) {

+

+				txs_rollback_stream();

+				txs_rollback_wait_upstream();

+				tx_state = TXS_SEARCH_EDID;

+			}

+			else if(pep932c_registers->power_control & (EP932E_POWER_CONTROL__PD_HDMI | EP932E_POWER_CONTROL__PD_TOT) ) {

+				pep932c_registers->power_control |= EP932E_POWER_CONTROL__PD_HDMI;

+

+				txs_rollback_stream();

+				tx_state = TXS_WAIT_UPSTREAM;

+			}

+#if 0

+			else if(!((pep932c_registers->system_configuration & EP932E_SYSTEM_CONFIGURATION__HDCP_DIS) || is_video_changing) && is_receiver_sense) {

+				DBG_PRINTK(("\r\nState Transist: Start HDCP -> [TXS_HDCP]\r\n")); // Enable mute for transmiter video and audio 

+				hdmi_tx_mute_enable();

+				tx_state = TXS_HDCP; } 

+#endif

+			break;

+

+		case TXS_HDCP:

+		

+			if(!is_connected || !is_hot_plug) {

+

+				txs_rollback_hdcp();

+				txs_rollback_stream();

+				txs_rollback_wait_upstream();

+				tx_state = TXS_SEARCH_EDID;

+			}

+			else if(pep932c_registers->power_control & (EP932E_POWER_CONTROL__PD_HDMI | EP932E_POWER_CONTROL__PD_TOT) ) {

+				pep932c_registers->power_control |= EP932E_POWER_CONTROL__PD_HDMI;

+

+				txs_rollback_hdcp();

+				txs_rollback_stream();

+				tx_state = TXS_WAIT_UPSTREAM;

+			}

+			else if((pep932c_registers->system_configuration & EP932E_SYSTEM_CONFIGURATION__HDCP_DIS) || is_video_changing) {

+	

+				txs_rollback_hdcp();

+				tx_state = TXS_STREAM;

+			}

+			else {

+printk("^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^HDCP task .^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\n");

+				pep932c_registers->hdcp_state = hdcp_authentication_task(is_receiver_sense && is_hot_plug);

+				pep932c_registers->hdcp_status = hdcp_get_status();

+			}

+			break;

+	}

+

+	//

+	// Update EP932 Registers for any time

+	//

+

+	// Mute Control

+	if( (pep932c_registers->system_configuration & EP932E_SYSTEM_CONFIGURATION__AUDIO_DIS) || (tx_state < TXS_STREAM) || is_video_changing  || is_audio_changing ) {

+		hdmi_tx_amute_enable();	

+	}

+	else {

+		hdmi_tx_amute_disable();

+	}

+	

+	if( (pep932c_registers->system_configuration & EP932E_SYSTEM_CONFIGURATION__VIDEO_DIS) || (tx_state < TXS_STREAM) || is_video_changing ) {

+		hdmi_tx_vmute_enable();		

+	}

+	else {

+		hdmi_tx_vmute_disable();

+	}

+

+	// HDMI Mode

+	if(!is_cap_hdmi || (pep932c_registers->system_configuration & EP932E_SYSTEM_CONFIGURATION__HDMI_DIS) ) {

+		hdmi_tx_dvi();	// Set to DVI mode (The Info Frame and Audio Packets would not be send)

+	}

+	else {

+		hdmi_tx_hdmi();	// Set to HDMI mode

+	}

+

+

+	++process_dispatch_id;

+	if(process_dispatch_id > 2) process_dispatch_id = 0;

+

+	switch(process_dispatch_id) {

+

+		case 0:

+			//

+			// Update Video Params

+			//

+		

+			// Video interface

+			video_params.interface = pep932c_registers->video_interface[0];

+		

+			// Video Timing

+			if(pep932c_registers->video_input_format[0]) { 

+				// Manul set the Video Timing

+				if(pep932c_registers->video_input_format[0] < 128) {

+					video_params.videosettingindex = pep932c_registers->video_input_format[0];

+				}

+				else {

+					video_params.videosettingindex = pep932c_registers->video_input_format[0] - (128 - EP932_VDO_SETTINGS_IT_START);

+				}

+			} 

+		

+			// Select Sync Mode

+			video_params.syncmode = (pep932c_registers->video_interface[1] & EP932E_VIDEO_INTERFACE_SETTING_1__SYNC) >> 2;

+		

+			// Select Color Space

+			switch(pep932c_registers->video_interface[1] & EP932E_VIDEO_INTERFACE_SETTING_1__COLOR) {

+				default:

+				case EP932E_VIDEO_INTERFACE_SETTING_1__COLOR__AUTO:

+					switch(video_params.videosettingindex) {

+						case  4: case  5: case 16: case 19: case 20: case 31: case 32: 

+						case 33: case 34: case 39: case 40: case 41: case 46: case 47:		// HD Timing

+							video_params.colorspace = COLORSPACE_709;

+							break;

+		

+						default:

+							if(video_params.videosettingindex && video_params.videosettingindex < EP932_VDO_SETTINGS_IT_START) { // SD Timing

+								video_params.colorspace = COLORSPACE_601;

+							}

+							else {															// IT Timing

+								video_params.colorspace = COLORSPACE_709;

+							}

+					}

+					break;

+				case EP932E_VIDEO_INTERFACE_SETTING_1__COLOR__601:

+					video_params.colorspace = COLORSPACE_601;

+					break;

+				case EP932E_VIDEO_INTERFACE_SETTING_1__COLOR__709:

+					video_params.colorspace = COLORSPACE_709;

+					break;

+			}

+		

+			// Set Input Format

+			switch(pep932c_registers->video_interface[1] & EP932E_VIDEO_INTERFACE_SETTING_1__VIN_FMT) {

+				default:

+				case EP932E_VIDEO_INTERFACE_SETTING_1__VIN_FMT__RGB:

+					video_params.formatin = COLORFORMAT_RGB;

+					video_params.formatout = COLORFORMAT_RGB;

+					break;

+				case EP932E_VIDEO_INTERFACE_SETTING_1__VIN_FMT__YCC444:

+					video_params.formatin = COLORFORMAT_YCC444;

+					if(is_cap_ycc444) {

+						video_params.formatout = COLORFORMAT_YCC444;

+					}

+					else if(is_cap_ycc422) {

+						video_params.formatout = COLORFORMAT_YCC422;

+					}

+					else {

+						video_params.formatout = COLORFORMAT_RGB;

+					}

+					break;

+				case EP932E_VIDEO_INTERFACE_SETTING_1__VIN_FMT__YCC422:

+					video_params.formatin = COLORFORMAT_YCC422;

+					if(is_cap_ycc422) {

+						video_params.formatout = COLORFORMAT_YCC422;

+					}

+					else if(is_cap_ycc444) {

+						video_params.formatout = COLORFORMAT_YCC444;

+					}

+					else {

+						video_params.formatout = COLORFORMAT_RGB;

+					}

+					break;

+			}

+

+			// DVI mode settings overwrite

+			if(!is_cap_hdmi || (pep932c_registers->system_configuration & EP932E_SYSTEM_CONFIGURATION__HDMI_DIS) ) {

+				video_params.formatout = COLORFORMAT_RGB;

+			}

+		

+			// AFAR

+			video_params.afarate = ((pep932c_registers->video_input_format[1] & EP932E_VIDEO_INPUT_FORMAT_1__AFAR) >> 4) | 0x08;

+		

+			// Video Change

+			if(memcmp(&video_params, &pep932c_registers->video_params_backup, sizeof(vdo_params)) != 0) {

+				if(memcmp(&video_params, &pep932c_registers->video_params_backup, 6) != 0) {

+					is_timing_changing = 1;

+				}

+//				DBG_PRINTK(("video_params new: interface 0x%02X, Vindex 0x%02X, HV 0x%02X, mode 0x%02X, Fin 0x%02X, Fout 0x%02X, color 0x%02X, AFAR 0x%02X\r\n",(int)video_params.interface, (int)video_params.videosettingindex, (int)video_params.hvpol ,(int)video_params.syncmode, (int)video_params.formatin, (int)video_params.formatout, (int)video_params.colorspace, (int)video_params.afarate));

+//				DBG_PRINTK(("video_params old: interface 0x%02X, Vindex 0x%02X, HV 0x%02X, mode 0x%02X, Fin 0x%02X, Fout 0x%02X, color 0x%02X, AFAR 0x%02X\r\n",(int)pep932c_registers->video_params_backup.interface, (int)pep932c_registers->video_params_backup.videosettingindex, (int)pep932c_registers->video_params_backup.hvpol ,(int)pep932c_registers->video_params_backup.syncmode, (int)pEP932C_Registers->video_params_backup.formatin, (int)pEP932C_Registers->video_params_backup.formatout, (int)pEP932C_Registers->video_params_backup.colorspace, (int)pEP932C_Registers->video_params_backup.afarate));

+				

+				pep932c_registers->video_params_backup = video_params;

+				

+				videochg_time_count = 0;

+				is_video_changing = 1;

+			}

+		

+			// Video Change Debouncing

+			if(is_video_changing) {				

+				if(videochg_time_count > AV_STABLE_TIME/EP932C_TIMER_PERIOD) {

+				    DBG_PRINTK(("### VideoChanging \r\n"));

+					if(is_timing_changing) ep932controller_reset();

+					hdmi_tx_video_config(&video_params);

+					if(is_timing_changing) {

+						if(!is_audio_changing) hdmi_tx_audio_config(&audio_params);

+					}

+

+					is_timing_changing = 0;

+					is_video_changing = 0;

+					videochg_time_count = 0;

+					

+					// Report Video Change

+					pep932c_registers->interrupt_flags |= EP932E_INTERRUPT_FLAGS__VIDEO_CHG;

+					if(ep932c_generateint && (pep932c_registers->interrupt_enable & EP932E_INTERRUPT_ENABLE__VIDEO_CHG) ) ep932c_generateint();

+				}

+			DBG_PRINTK(("### VideoChanging end^^^^^^^^^\r\n"));

+			}

+			break;

+

+		case 1:

+			//

+			// Update Audio Params

+			//

+			audio_params.interface = pep932c_registers->audio_interface & 0x0F; // IIS, WS_M, WS_POL, SCK_POL

+			audio_params.videosettingindex = video_params.videosettingindex;

+

+			// Update Audio Channel Number

+			if(ep932_vdo_settings[video_params.videosettingindex].pix_freq_type <= PIX_FREQ_27027KHZ) {

+				audio_params.channelnumber = 1;

+			}

+			else {

+				audio_params.channelnumber = min(((pep932c_registers->audio_interface & 0x70) >> 4), pep932c_registers->edid_achannel);

+			}

+

+			// Update VFS

+			if(audio_params.videosettingindex < EP932_VDO_SETTINGS_IT_START) {

+				// Pixel Clock Type shift (59.94/60)

+				audio_params.vfs = (pep932c_registers->video_input_format[1] & EP932E_VIDEO_INPUT_FORMAT_1__VIF)? 1:0;

+			}

+			else {

+				audio_params.vfs = 0;

+			}

+			audio_params.nocopyright = (pep932c_registers->audio_input_format & EP932E_AUDIO_INPUT_FORMAT__NOCOPYRIGHT)?1:0;

+		

+			// Write Frequency info (Use ADO_FREQ or Auto)

+			switch( pep932c_registers->audio_input_format & EP932E_AUDIO_INPUT_FORMAT__ADO_FREQ ) {

+		

+				case EP932E_AUDIO_INPUT_FORMAT__ADO_FREQ__32000HZ:

+					audio_params.inputfrequency = ADSFREQ_32000HZ;

+					// Disable Down Sample

+					audio_params.adsrate = 0;

+					break;

+		

+				default:

+				case EP932E_AUDIO_INPUT_FORMAT__ADO_FREQ__44100HZ:

+					audio_params.inputfrequency = ADSFREQ_44100HZ;

+					// Disable Down Sample

+					audio_params.adsrate = 0;

+					break;

+		

+				case EP932E_AUDIO_INPUT_FORMAT__ADO_FREQ__48000HZ:

+					audio_params.inputfrequency = ADSFREQ_48000HZ;

+					// Disable Down Sample

+					audio_params.adsrate = 0;

+					break;

+		

+				case EP932E_AUDIO_INPUT_FORMAT__ADO_FREQ__88200HZ:

+					audio_params.inputfrequency = ADSFREQ_88200HZ;

+					if(pep932c_registers->edid_asfreq & 0x08) { // 88.2kHZ

+						// Disable Down Sample

+						audio_params.adsrate = 0;

+					}

+					else {

+						// Enable Down Sample 1/2

+						audio_params.adsrate = 1;

+					}

+					break;

+		

+				case EP932E_AUDIO_INPUT_FORMAT__ADO_FREQ__96000HZ:

+					audio_params.inputfrequency = ADSFREQ_96000HZ;

+					if(pep932c_registers->edid_asfreq & 0x10) { // 96kHZ

+						// Disable Down Sample

+						audio_params.adsrate = 0;

+					}

+					else {

+						if(pep932c_registers->edid_asfreq & 0x04) { // 48kHZ

+							// Enable Down Sample 1/2

+							audio_params.adsrate = 1;

+						}

+						else {

+							// Enable Down Sample 1/3

+							audio_params.adsrate = 2;

+						}

+					}

+					break;

+		

+				case EP932E_AUDIO_INPUT_FORMAT__ADO_FREQ__176400HZ:

+					audio_params.inputfrequency = ADSFREQ_176400HZ;

+					if(pep932c_registers->edid_asfreq & 0x20) { // 176kHZ

+						// Disable Down Sample

+						audio_params.adsrate = 0;

+					}

+					else {

+						if(pep932c_registers->edid_asfreq & 0x08) { // 88.2kHZ

+							// Enable Down Sample 1/2

+							audio_params.adsrate = 1;

+						}

+						else {

+							// Enable Down Sample 1/4

+							audio_params.adsrate = 3;

+						}

+					}

+					break;

+		

+				case EP932E_AUDIO_INPUT_FORMAT__ADO_FREQ__192000HZ:

+					audio_params.inputfrequency = ADSFREQ_192000HZ;

+					if(pep932c_registers->edid_asfreq & 0x40) { // 192kHZ

+						// Disable Down Sample

+						audio_params.adsrate = 0;

+					}

+					else {

+						if(pep932c_registers->edid_asfreq & 0x10) { // 96kHZ

+							// Enable Down Sample 1/2

+							audio_params.adsrate = 1;

+						}

+						else {

+							// Enable Down Sample 1/4

+							audio_params.adsrate = 3;

+						}

+					}

+					break;

+			}

+		

+			// Audio Change

+			if(memcmp(&audio_params, &pep932c_registers->audio_params_backup, sizeof(ado_params)) != 0) {

+				pep932c_registers->audio_params_backup = audio_params;

+		

+				audiochg_time_count = 0;

+				is_audio_changing = 1;

+			}

+

+			// Audio Change Debouncing

+			if(is_audio_changing) {

+				if(audiochg_time_count > AV_STABLE_TIME/EP932C_TIMER_PERIOD) {

+					hdmi_tx_audio_config(&audio_params);

+					is_audio_changing = 0;

+					audiochg_time_count = 0;

+					

+					// Report Audio Change

+					pep932c_registers->interrupt_flags |= EP932E_INTERRUPT_FLAGS__AUDIO_CHG;

+					if(ep932c_generateint && (pep932c_registers->interrupt_enable & EP932E_INTERRUPT_ENABLE__AUDIO_CHG) ) ep932c_generateint();

+				}

+			}

+			break;

+

+		case 2:

+

+			// Update TREG

+			if(pep932c_registers->analog_test_control != backup_analog_test_control) {

+				backup_analog_test_control = pep932c_registers->analog_test_control;

+		

+				if(pep932c_registers->analog_test_control & 0x01) {

+					ep932_reg_set_bit(EP932_COLOR_SPACE_CONTROL, 0x01);

+				}

+				else {

+					ep932_reg_clear_bit(EP932_COLOR_SPACE_CONTROL, 0x01);

+				}

+				if(pep932c_registers->analog_test_control & 0x02) {

+					ep932_reg_set_bit(EP932_COLOR_SPACE_CONTROL, 0x02);

+				}

+				else {

+					ep932_reg_clear_bit(EP932_COLOR_SPACE_CONTROL, 0x02);

+				}

+			}

+			break;

+	}

+

+	// Return the status

+	if(pep932c_registers->power_control & (EP932E_POWER_CONTROL__PD_HDMI | EP932E_POWER_CONTROL__PD_TOT)) {

+

+		return EP932C_TASK_IDLE;

+		

+	}

+	else {

+		return EP932C_TASK_PENDING;

+	}

+	

+}

+

+void txs_rollback_wait_upstream(void)

+{

+	DBG_PRINTK(("\r\nState Rollback: Reset EDID -> [TXS_SEARCH_EDID]\r\n"));

+

+	// Reset EDID

+	memset(pep932c_registers->readed_edid, 0xFF, 256);

+

+	// Report EDID Change

+	pep932c_registers->interrupt_flags |= EP932E_INTERRUPT_FLAGS__EDID_CHG;

+	if(ep932c_generateint && (pep932c_registers->interrupt_enable & EP932E_INTERRUPT_ENABLE__EDID_CHG) ) ep932c_generateint();

+	read_edid_time_count = 0;

+}

+

+void txs_rollback_stream(void)

+{

+	DBG_PRINTK(("\r\nState Rollback: Power Down -> [TXS_WAIT_UPSTREAM]\r\n"));

+

+	// Power Down

+	hdmi_tx_power_down();

+

+	// Reset HDCP Info

+	memset(pep932c_registers->hdcp_bksv, 0x00, sizeof(pep932c_registers->hdcp_bksv));

+	is_hdcp_info_bksv_rdy = 0;

+}

+

+void txs_rollback_hdcp(void)

+{

+	DBG_PRINTK(("\r\nState Rollback: Stop HDCP -> [TXS_STREAM]\r\n"));

+

+	hdcp_stop();

+	pep932c_registers->hdcp_status = 0;

+	pep932c_registers->hdcp_state = 0;

+}

+

+//----------------------------------------------------------------------------------------------------------------------

+

+void read_interruput_flags(void) 

+{

+	//DBG_PRINTK(("EP932 read_interruput_flags \r\n"));

+	ep932_reg_read(EP932_GENERAL_CONTROL_2, ddc_data, 1);

+

+	if(ddc_data[0] & EP932_GENERAL_CONTROL_2__RIF) {

+		hdcp_ext_ri_trigger();

+		// Clear the interrupt flag

+		ddc_data[0] = EP932_GENERAL_CONTROL_2__RIF;

+		ep932_reg_write(EP932_GENERAL_CONTROL_2, ddc_data, 1);

+	}

+/*

+	// Clear the interrupt flag

+	ddc_data[0] = EP932_GENERAL_CONTROL_2__RIF;

+	ep932_reg_write(EP932_GENERAL_CONTROL_2, ddc_data, 1);

+*/

+}

+

+//----------------------------------------------------------------------------------------------------------------------

+

+void  ep_hdmi_dump_message(void)

+{

+	unsigned short temp_ushort;

+	unsigned char temp_r[2];

+	unsigned char reg_addr;

+

+	// System Status

+	DBG_PRINTK(("\r\n\r\n======= Dump EP932E information =======\r\n"));

+

+	DBG_PRINTK(("\r\n[EDID Data]"));

+	for(temp_ushort = 0; temp_ushort < 256; ++temp_ushort) {

+		if(temp_ushort%16 == 0) DBG_PRINTK(("\r\n"));

+		if(temp_ushort%8 == 0) DBG_PRINTK((" "));

+		DBG_PRINTK(("0x%02X,", (int)ep932c_registers.readed_edid[temp_ushort] ));

+	}

+	DBG_PRINTK(("\r\n"));

+

+	DBG_PRINTK(("\r\n[Revision & Configuration]\r\n"));

+	DBG_PRINTK(("vendorid=0x%04X, ", ep932c_registers.vendorid ));

+	DBG_PRINTK(("deviceid=0x%04X, ", ep932c_registers.deviceid ));

+	DBG_PRINTK(("Version=%d.%d, CFG=0x%02X\r\n", (int)ep932c_registers.version_major, (int)ep932c_registers.version_minor, (int)ep932c_registers.configuration ));

+

+	DBG_PRINTK(("\r\n[Interrupt Flags]\r\n"));

+	DBG_PRINTK(("EDID_CHG=%d, ", (int)((ep932c_registers.interrupt_flags & EP932E_INTERRUPT_FLAGS__EDID_CHG)?1:0) ));

+	DBG_PRINTK(("VIDEO_CHG=%d, ", (int)((ep932c_registers.interrupt_flags & EP932E_INTERRUPT_FLAGS__VIDEO_CHG)?1:0) ));

+	DBG_PRINTK(("AUDIO_CHG=%d\r\n", (int)((ep932c_registers.interrupt_flags & EP932E_INTERRUPT_FLAGS__AUDIO_CHG)?1:0) ));

+

+	DBG_PRINTK(("\r\n[System Status]\r\n"));

+	DBG_PRINTK(("RSEN=%d, ", (int)((ep932c_registers.system_status & EP932E_SYSTEM_STATUS__RSEN)?1:0) ));

+	DBG_PRINTK(("HTPLG=%d, ", (int)((ep932c_registers.system_status & EP932E_SYSTEM_STATUS__HTPLG)?1:0) ));

+	DBG_PRINTK(("KEY_FAIL=%d, ", (int)((ep932c_registers.system_status & EP932E_SYSTEM_STATUS__KEY_FAIL)?1:0) ));

+	DBG_PRINTK(("DEF_KEY=%d\r\n", (int)((ep932c_registers.system_status & EP932E_SYSTEM_STATUS__DEF_KEY)?1:0) ));

+

+	DBG_PRINTK(("\r\n[EDID Status]\r\n"));

+	DBG_PRINTK(("EDID_HDMI=%d, ", (int)((ep932c_registers.edid_status & EP932E_EDID_STATUS__HDMI)?1:0) ));

+	DBG_PRINTK(("DDC_STATUS=%d\r\n", (int)(ep932c_registers.edid_status & 0x0F) ));

+	DBG_PRINTK(("VIDEO_DATA_ADDR=0x%02X, ", (int)ep932c_registers.edid_videodataaddr ));

+	DBG_PRINTK(("AUDIO_DATA_ADDR=0x%02X, ", (int)ep932c_registers.edid_audiodataaddr ));

+	DBG_PRINTK(("SPEAKER_DATA_ADDR=0x%02X, ", (int)ep932c_registers.edid_speakerdataaddr ));

+	DBG_PRINTK(("VENDOR_DATA_ADDR=0x%02X\r\n", (int)ep932c_registers.edid_vendordataaddr ));

+	DBG_PRINTK(("ASFREQ=0x%02X, ", (int)ep932c_registers.edid_asfreq ));

+	DBG_PRINTK(("ACHANNEL=%d\r\n", (int)ep932c_registers.edid_achannel ));

+

+	DBG_PRINTK(("\r\n[Video Status]\r\n"));

+	DBG_PRINTK(("interface=0x%02X, ", (int)ep932c_registers.video_params_backup.interface ));

+	DBG_PRINTK(("videosettingindex=%d, ", (int)ep932c_registers.video_params_backup.videosettingindex ));

+	DBG_PRINTK(("hvpol=%d, ", (int)ep932c_registers.video_params_backup.hvpol ));

+	DBG_PRINTK(("syncmode=%d, ", (int)ep932c_registers.video_params_backup.syncmode ));

+	DBG_PRINTK(("formatin=%d, ", (int)ep932c_registers.video_params_backup.formatin ));

+	DBG_PRINTK(("formatout=%d, ", (int)ep932c_registers.video_params_backup.formatout ));

+	DBG_PRINTK(("colorspace=%d, ", (int)ep932c_registers.video_params_backup.colorspace ));

+	DBG_PRINTK(("afarate=%d\r\n", (int)ep932c_registers.video_params_backup.afarate ));

+

+	DBG_PRINTK(("\r\n[Audio Status]\r\n"));

+	DBG_PRINTK(("interface=0x%02X, ", (int)ep932c_registers.audio_params_backup.interface ));

+	DBG_PRINTK(("videosettingindex=%d, ", (int)ep932c_registers.audio_params_backup.videosettingindex ));

+	DBG_PRINTK(("channelnumber=%d, ", (int)ep932c_registers.audio_params_backup.channelnumber ));

+	DBG_PRINTK(("adsrate=%d, ", (int)ep932c_registers.audio_params_backup.adsrate ));

+	DBG_PRINTK(("inputfrequency=%d, ", (int)ep932c_registers.audio_params_backup.inputfrequency ));

+	DBG_PRINTK(("VFS=%d, ", (int)ep932c_registers.audio_params_backup.vfs ));

+	DBG_PRINTK(("nocopyright=%d\r\n", (int)ep932c_registers.audio_params_backup.nocopyright ));

+

+	DBG_PRINTK(("\r\n[Power Control]\r\n"));

+	DBG_PRINTK(("PD_HDMI=%d, ", (int)((ep932c_registers.power_control & EP932E_POWER_CONTROL__PD_HDMI)?1:0) ));

+	DBG_PRINTK(("PD_TOT=%d\r\n", (int)((ep932c_registers.power_control & EP932E_POWER_CONTROL__PD_TOT)?1:0) ));

+

+	DBG_PRINTK(("\r\n[System Configuration]\r\n"));

+	DBG_PRINTK(("HDCP_DIS=%d, ", (int)((ep932c_registers.system_configuration & EP932E_SYSTEM_CONFIGURATION__HDCP_DIS)?1:0) ));

+	DBG_PRINTK(("HDMI_DIS=%d, ", (int)((ep932c_registers.system_configuration & EP932E_SYSTEM_CONFIGURATION__HDMI_DIS)?1:0) ));

+	DBG_PRINTK(("AUDIO_DIS=%d, ", (int)((ep932c_registers.system_configuration & EP932E_SYSTEM_CONFIGURATION__AUDIO_DIS)?1:0) ));

+	DBG_PRINTK(("VIDEO_DIS=%d\r\n", (int)((ep932c_registers.system_configuration & EP932E_SYSTEM_CONFIGURATION__VIDEO_DIS)?1:0) ));

+

+	DBG_PRINTK(("\r\n[Interrupt Enable]\r\n"));

+	DBG_PRINTK(("EDID_CHG=%d, ", (int)((ep932c_registers.interrupt_enable & EP932E_INTERRUPT_ENABLE__EDID_CHG)?1:0) ));

+	DBG_PRINTK(("VS_PERIOD_CHG=%d, ", (int)((ep932c_registers.interrupt_enable & EP932E_INTERRUPT_ENABLE__VIDEO_CHG)?1:0) ));

+	DBG_PRINTK(("AS_FREQ_CHG=%d\r\n", (int)((ep932c_registers.interrupt_enable & EP932E_INTERRUPT_ENABLE__AUDIO_CHG)?1:0) ));

+

+	DBG_PRINTK(("\r\n[Video interface 0]\r\n"));

+	DBG_PRINTK(("DK=%d, ", (int)((ep932c_registers.video_interface[0] & EP932E_VIDEO_INTERFACE_SETTING_0__DK)?1:0) ));

+	DBG_PRINTK(("DKEN=%d, ", (int)((ep932c_registers.video_interface[0] & EP932E_VIDEO_INTERFACE_SETTING_0__DKEN)?1:0) ));

+	DBG_PRINTK(("DSEL=%d, ", (int)((ep932c_registers.video_interface[0] & EP932E_VIDEO_INTERFACE_SETTING_0__DSEL)?1:0) ));

+	DBG_PRINTK(("BSEL=%d, ", (int)((ep932c_registers.video_interface[0] & EP932E_VIDEO_INTERFACE_SETTING_0__BSEL)?1:0) ));

+	DBG_PRINTK(("EDGE=%d, ", (int)((ep932c_registers.video_interface[0] & EP932E_VIDEO_INTERFACE_SETTING_0__EDGE)?1:0) ));

+	DBG_PRINTK(("FMT12=%d\r\n", (int)((ep932c_registers.video_interface[0] & EP932E_VIDEO_INTERFACE_SETTING_0__FMT12)?1:0) ));

+

+	DBG_PRINTK(("\r\n[Video interface 1]\r\n"));

+	DBG_PRINTK(("COLOR=%d, ", (int)((ep932c_registers.video_interface[1] & EP932E_VIDEO_INTERFACE_SETTING_1__COLOR)>>4) ));

+	DBG_PRINTK(("SYNC=%d, ", (int)((ep932c_registers.video_interface[1] & EP932E_VIDEO_INTERFACE_SETTING_1__SYNC)>>2) ));

+	DBG_PRINTK(("VIN_FMT=%d\r\n", (int)((ep932c_registers.video_interface[1] & EP932E_VIDEO_INTERFACE_SETTING_1__VIN_FMT)>>0) ));

+

+	DBG_PRINTK(("\r\n[Audio interface]\r\n"));

+	DBG_PRINTK(("CHANNEL=%d, ", (int) (ep932c_registers.audio_interface & EP932E_AUDIO_INTERFACE_SETTING__CHANNEL)>>4 ));

+	DBG_PRINTK(("IIS=%d, ", (int)((ep932c_registers.audio_interface & EP932E_AUDIO_INTERFACE_SETTING__IIS)?1:0) ));

+	DBG_PRINTK(("WS_M=%d, ", (int)((ep932c_registers.audio_interface & EP932E_AUDIO_INTERFACE_SETTING__WS_M)?1:0) ));

+	DBG_PRINTK(("WS_POL=%d, ", (int)((ep932c_registers.audio_interface & EP932E_AUDIO_INTERFACE_SETTING__WS_POL)?1:0) ));

+	DBG_PRINTK(("SCK_POL=%d\r\n", (int)((ep932c_registers.audio_interface & EP932E_AUDIO_INTERFACE_SETTING__SCK_POL)?1:0) ));	

+

+	DBG_PRINTK(("\r\n[Video Input Format 0]\r\n"));

+	DBG_PRINTK(("VIC=%d\r\n", (int)ep932c_registers.video_input_format[0] ));	

+

+	DBG_PRINTK(("\r\n[Video Input Format 1]\r\n"));

+	DBG_PRINTK(("AFAR_VIF=0x%02X\r\n", (int)ep932c_registers.video_input_format[1] ));	

+

+

+	DBG_PRINTK(("\r\n[EP932 Register value]"));

+	for(reg_addr = 0; reg_addr<=0x88; reg_addr++)

+	{

+		ep932_reg_read(reg_addr, temp_r, 1);

+		if(reg_addr%8 == 0)DBG_PRINTK(("\r\n"));

+		DBG_PRINTK(("[%02X]%02X, ",(int)reg_addr,(int)temp_r[0]));

+	}

+	DBG_PRINTK(("\r\n"));

+}

+

+

diff --git a/drivers/video/ep932/ep932controller.h b/drivers/video/ep932/ep932controller.h
new file mode 100644
index 00000000000..26c753b6291
--- /dev/null
+++ b/drivers/video/ep932/ep932controller.h
@@ -0,0 +1,97 @@
+#ifndef EP932CONTROLLER_H

+#define EP932CONTROLLER_H

+

+#include "ep932eregdef.h"

+#include "ep932_if.h"

+#include "hdcp.h"

+

+#define VERSION_MAJOR             0  // Beta

+#define VERSION_MINOR             36 //      36

+

+#define EP932C_TIMER_PERIOD       100		//     The EP932Controller.c must be re-compiled if user want to change this value.

+

+typedef enum {

+	EP932C_TASK_IDLE = 0,

+	EP932C_TASK_ERROR,

+	EP932C_TASK_PENDING,

+	EP932C_TASK_PGOUT

+} ep932c_task_status;

+

+typedef struct _ep932c_register_map {

+

+	// Read

+	unsigned short		vendorid;			// 0x00

+	unsigned short		deviceid;

+	unsigned char		version_major;

+	unsigned char		version_minor;

+	unsigned char		configuration;

+

+	unsigned char		interrupt_flags;		// 0x01

+

+	unsigned char		system_status;			// 0x02

+

+	unsigned char		hdcp_status;			// 0x03

+	unsigned char		hdcp_state;

+	unsigned char		hdcp_aksv[5];

+	unsigned char		hdcp_bksv[5];

+	unsigned char		hdcp_bcaps3[3];

+	unsigned char		hdcp_ksv_fifo[5*16];

+	unsigned char		hdcp_sha[20];

+	unsigned char		hdcp_m0[8];

+

+	unsigned char		edid_status;			// 0x04

+	unsigned char		edid_videodataaddr;

+	unsigned char		edid_audiodataaddr;

+	unsigned char		edid_speakerdataaddr;

+	unsigned char		edid_vendordataaddr;

+	unsigned char		edid_asfreq;

+	unsigned char		edid_achannel;

+						

+	//unsigned short		VS_Period;				// 0x05 (Video Status)

+	//unsigned short		H_Res;

+	//unsigned short		V_Res;

+	//unsigned short		Ratio_24;

+	vdo_params 			video_params_backup;

+

+	//unsigned short		AS_Freq;				// 0x06 (Audio Status)

+	//unsigned short		AS_Period;				// 

+	ado_params 			audio_params_backup;

+

+	unsigned char		readed_edid[256];		// 0x07 

+	// Read / Write

+	unsigned char		analog_test_control;	// 0X1C

+

+	unsigned char		power_control;			// 0x20

+	unsigned char		system_configuration;

+

+	unsigned char		interrupt_enable;		// 0x21

+

+	unsigned char		video_interface[2];		// 0x22

+

+	unsigned char		audio_interface;		// 0x23

+

+	unsigned char		video_input_format[2];	// 0x24

+

+	unsigned char		audio_input_format;		// 0x25

+

+	unsigned char		end;

+

+} ep932c_register_map, *pep932c_register_map;

+

+// -----------------------------------------------------------------------------

+// -----------------------------------------------------------------------------

+

+typedef void (*ep932c_callback)(void);

+

+void ep932controller_initial(pep932c_register_map pep932c_regmap, ep932c_callback intcall);

+

+unsigned char ep932controller_task(void);

+

+void ep932controller_timer(void);

+void ep_hdmi_dumpmessage(void);

+

+void ep932power_on();

+void ep932power_off();

+// -----------------------------------------------------------------------------

+#endif

+

diff --git a/drivers/video/ep932/ep932eregdef.h b/drivers/video/ep932/ep932eregdef.h
new file mode 100644
index 00000000000..81163a474f8
--- /dev/null
+++ b/drivers/video/ep932/ep932eregdef.h
@@ -0,0 +1,157 @@
+#ifndef EP932EREGDEF_H

+#define EP932EREGDEF_H

+

+#define EP932E_VENDOR_ID						0x0000

+#define EP932E_DEVICE_ID						0x0002

+#define EP932E_FIRMWARE_REVISION__MAJOR					0x0004

+#define EP932E_FIRMWARE_REVISION__MINOR					0x0005

+

+#define EP932E_INTERRUPT_FLAGS						0x0100

+#define EP932E_INTERRUPT_FLAGS__EDID_CHG				0x80

+#define EP932E_INTERRUPT_FLAGS__VIDEO_CHG				0x40

+#define EP932E_INTERRUPT_FLAGS__AUDIO_CHG				0x20

+#define EP932E_INTERRUPT_FLAGS__VS_ALIGN_FAILED				0x10

+#define EP932E_INTERRUPT_FLAGS__VS_ALIGN_DONE				0x08

+

+#define EP932E_SYSTEM_STATUS						0x0200

+#define EP932E_SYSTEM_STATUS__RSEN					0x80

+#define EP932E_SYSTEM_STATUS__HTPLG					0x40

+#define EP932E_SYSTEM_STATUS__KEY_FAIL					0x02

+#define EP932E_SYSTEM_STATUS__DEF_KEY					0x01

+

+#define EP932E_HDCP_STATUS						0x0300

+#define EP932E_HDCP_STATUS__BKSV					0x80

+#define EP932E_HDCP_STATUS__AKSV					0x40

+#define EP932E_HDCP_STATUS__R0						0x20

+#define EP932E_HDCP_STATUS__RI						0x10

+#define EP932E_HDCP_STATUS__REPEATERRDY					0x08

+#define EP932E_HDCP_STATUS__REPEATERSHA					0x04

+#define EP932E_HDCP_STATUS__RSEN					0x02

+#define EP932E_HDCP_STATUS__REVOKE					0x01

+

+#define EP932E_HDCP_STATE						0x0301

+

+#define EP932E_HDCP_AKSV						0x0302

+ 

+#define EP932E_HDCP_BKSV						0x0307 

+

+#define EP932E_HDCP_BCAPS						0x030C

+

+#define EP932E_HDCP_BSTATUS						0x030D

+

+#define EP932E_HDCP_KSV_FIFO						0x030F

+

+#define EP932E_EDID_STATUS						0x0400

+#define EP932E_EDID_STATUS__HDMI					0x10

+#define EP932E_EDID_STATUS__DDC_STATUS					0x0F

+

+typedef enum {

+	EDID_DDC_SUCCESS = 0x00,

+	EDID_DDC_PENDING,

+	EDID_DDC_NOACT = 0x02,

+	EDID_DDC_TIMEOUT,

+	EDID_DDC_ARBITRATIONLOSS = 0x04,

+	EDID_DDC_BLOCKNUMBER

+} edid_ddc_status;

+

+#define EP932E_EDID_STATUS_ASFREQ			0x0401

+#define EP932E_EDID_STATUS_ACHANNEL			0x0402

+

+#define EP932E_VIDEO_STATUS_VS_PERIOD			0x0500					// 2 Byte

+#define EP932E_VIDEO_STATUS_H_RES			0x0502					// 2 Byte

+#define EP932E_VIDEO_STATUS_V_RES			0x0504					// 2 Byte

+#define EP932E_VIDEO_STATUS_RATIO_24			0x0506					// 2 Byte

+#define EP932E_VIDEO_STATUS_PARAMS			0x0508					// 8 Byte

+

+#define EP932E_AUDIO_STATUS_AS_FREQ			0x0600					// 2 Byte

+#define EP932E_AUDIO_STATUS_AS_PERIOD			0x0602					// 2 Byte

+#define EP932E_AUDIO_STATUS_PARAMS			0x0604					// 7 Byte

+

+#define EP932E_EDID_DATA				0x0700					// 256 Byte

+

+#define EP932E_ANALOG_TEST_CONTROL				0x1C00

+#define EP932E_ANALOG_TEST_CONTROL__PREEMPHASIS			0x03

+

+#define EP932E_SIP_TEST_CONTROL					0x1D00

+#define EP932E_SIP_TEST_CONTROL__VS_ALIGN			0x08

+#define EP932E_SIP_TEST_CONTROL__BIST				0x04

+#define EP932E_SIP_TEST_CONTROL__ANA_TEST			0x02

+#define EP932E_SIP_TEST_CONTROL__IIC_STOP 			0x01

+

+#define EP932E_POWER_CONTROL					0x2000

+#define EP932E_POWER_CONTROL__PD_HDMI				0x02

+#define EP932E_POWER_CONTROL__PD_TOT				0x01

+

+#define EP932E_SYSTEM_CONFIGURATION				0x2001

+#define EP932E_SYSTEM_CONFIGURATION__PACKET_RDY			0x80

+#define EP932E_SYSTEM_CONFIGURATION__HDCP_DIS			0x20

+#define EP932E_SYSTEM_CONFIGURATION__HDMI_DIS			0x10

+#define EP932E_SYSTEM_CONFIGURATION__FORCE_HDMI_CAP		0x08

+#define EP932E_SYSTEM_CONFIGURATION__AUDIO_DIS			0x02

+#define EP932E_SYSTEM_CONFIGURATION__VIDEO_DIS			0x01

+

+#define EP932E_INTERRUPT_ENABLE					0x2100

+#define EP932E_INTERRUPT_ENABLE__EDID_CHG			0x80

+#define EP932E_INTERRUPT_ENABLE__VIDEO_CHG			0x40

+#define EP932E_INTERRUPT_ENABLE__AUDIO_CHG			0x20

+#define EP932E_INTERRUPT_ENABLE__VS_ALIGN_DONE			0x08

+

+#define EP932E_VIDEO_INTERFACE_SETTING_0				0x2200

+#define EP932E_VIDEO_INTERFACE_SETTING_0__DK				0xE0

+#define EP932E_VIDEO_INTERFACE_SETTING_0__DKEN				0x10

+#define EP932E_VIDEO_INTERFACE_SETTING_0__DSEL				0x08

+#define EP932E_VIDEO_INTERFACE_SETTING_0__BSEL				0x04

+#define EP932E_VIDEO_INTERFACE_SETTING_0__EDGE				0x02

+#define EP932E_VIDEO_INTERFACE_SETTING_0__FMT12				0x01

+

+#define EP932E_VIDEO_INTERFACE_SETTING_1				0x2201

+#define EP932E_VIDEO_INTERFACE_SETTING_1__COLOR				0x30

+#define EP932E_VIDEO_INTERFACE_SETTING_1__COLOR__AUTO			0x00

+#define EP932E_VIDEO_INTERFACE_SETTING_1__COLOR__601			0x10

+#define EP932E_VIDEO_INTERFACE_SETTING_1__COLOR__709			0x20

+#define EP932E_VIDEO_INTERFACE_SETTING_1__XVYCC_EN			0x80

+#define EP932E_VIDEO_INTERFACE_SETTING_1__SYNC				0x0C

+#define EP932E_VIDEO_INTERFACE_SETTING_1__SYNC__HVDE			0x00

+#define EP932E_VIDEO_INTERFACE_SETTING_1__SYNC__HV			0x04

+#define EP932E_VIDEO_INTERFACE_SETTING_1__SYNC__Embeded			0x08

+#define EP932E_VIDEO_INTERFACE_SETTING_1__VIN_FMT			0x03

+#define EP932E_VIDEO_INTERFACE_SETTING_1__VIN_FMT__RGB			0x00

+#define EP932E_VIDEO_INTERFACE_SETTING_1__VIN_FMT__YCC444		0x01

+#define EP932E_VIDEO_INTERFACE_SETTING_1__VIN_FMT__YCC422		0x02 

+

+#define EP932E_AUDIO_INTERFACE_SETTING					0x2300

+#define EP932E_AUDIO_INTERFACE_SETTING__CHANNEL				0xF0

+#define EP932E_AUDIO_INTERFACE_SETTING__IIS				0x08

+#define EP932E_AUDIO_INTERFACE_SETTING__WS_M				0x04

+#define EP932E_AUDIO_INTERFACE_SETTING__WS_POL				0x02

+#define EP932E_AUDIO_INTERFACE_SETTING__SCK_POL				0x01

+

+#define EP932E_VIDEO_INPUT_FORMAT_VIC					0x2400

+#define EP932E_VIDEO_INPUT_FORMAT_1					0x2401

+#define EP932E_VIDEO_INPUT_FORMAT_1__AFAR				0x30

+#define EP932E_VIDEO_INPUT_FORMAT_1__AFAR__AUTO				0x00

+#define EP932E_VIDEO_INPUT_FORMAT_1__AFAR__4_3				0x10

+#define EP932E_VIDEO_INPUT_FORMAT_1__AFAR__16_9				0x20

+#define EP932E_VIDEO_INPUT_FORMAT_1__AFAR__14_9				0x30

+#define EP932E_VIDEO_INPUT_FORMAT_1__VIF				0x01

+

+#define EP932E_AUDIO_INPUT_FORMAT					0x2500

+#define EP932E_AUDIO_INPUT_FORMAT__NOCOPYRIGHT				0x10

+#define EP932E_AUDIO_INPUT_FORMAT__ADO_FREQ				0x07

+#define EP932E_AUDIO_INPUT_FORMAT__ADO_FREQ__AUTO			0x00

+#define EP932E_AUDIO_INPUT_FORMAT__ADO_FREQ__32000HZ			0x01

+#define EP932E_AUDIO_INPUT_FORMAT__ADO_FREQ__44100HZ			0x02

+#define EP932E_AUDIO_INPUT_FORMAT__ADO_FREQ__48000HZ			0x03

+#define EP932E_AUDIO_INPUT_FORMAT__ADO_FREQ__88200HZ			0x04

+#define EP932E_AUDIO_INPUT_FORMAT__ADO_FREQ__96000HZ			0x05

+#define EP932E_AUDIO_INPUT_FORMAT__ADO_FREQ__176400HZ			0x06

+#define EP932E_AUDIO_INPUT_FORMAT__ADO_FREQ__192000HZ			0x07

+

+#define EP932E_KSV_REVOCATION_LIST				0x2600

+

+#define EP932E_GAMUT_PACKET_HEADER				0x2700

+#define EP932E_GAMUT_PACKET_DATA				0x2703

+

+#define EP932E_SELECT_PACKET_HEADER				0x2800

+#define EP932E_SELECT_PACKET_DATA				0x2803

+#endif

diff --git a/drivers/video/ep932/ep932regdef.h b/drivers/video/ep932/ep932regdef.h
new file mode 100644
index 00000000000..34023fa3131
--- /dev/null
+++ b/drivers/video/ep932/ep932regdef.h
@@ -0,0 +1,161 @@
+/******************************************************************************\

+

+          (c) Copyright Explore Semiconductor, Inc. Limited 2005

+                           ALL RIGHTS RESERVED 

+

+--------------------------------------------------------------------------------

+

+ Please review the terms of the license agreement before using this file.

+ If you are not an authorized user, please destroy this source code file  

+ and notify Explore Semiconductor Inc. immediately that you inadvertently 

+ received an unauthorized copy.  

+

+--------------------------------------------------------------------------------

+

+  File        :  EP932RegDef.h

+

+  Description :  Register Address definitions of EP932.

+

+\******************************************************************************/

+

+#ifndef EP932REGDEF_H

+#define EP932REGDEF_H

+

+#define EP932_SMPRD						0x06			// 2 Byte

+

+#define EP932_GENERAL_CONTROL_1					0x08

+#define EP932_GENERAL_CONTROL_1__TSEL_HTP			0x80

+#define EP932_GENERAL_CONTROL_1__INT_OD				0x40

+#define EP932_GENERAL_CONTROL_1__INT_POL			0x20

+#define EP932_GENERAL_CONTROL_1__VTX				0x10

+#define EP932_GENERAL_CONTROL_1__DSEL				0x08

+#define EP932_GENERAL_CONTROL_1__BSEL				0x04

+#define EP932_GENERAL_CONTROL_1__EDGE				0x02

+#define EP932_GENERAL_CONTROL_1__PU				0x01

+

+#define EP932_GENERAL_CONTROL_2					0x09

+#define EP932_GENERAL_CONTROL_2__RSEN				0x80

+#define EP932_GENERAL_CONTROL_2__HTPLG				0x40

+#define EP932_GENERAL_CONTROL_2__RIE				0x20

+#define EP932_GENERAL_CONTROL_2__VIE				0x10

+#define EP932_GENERAL_CONTROL_2__MIE				0x08

+#define EP932_GENERAL_CONTROL_2__RIF				0x04

+#define EP932_GENERAL_CONTROL_2__VIF				0x02

+#define EP932_GENERAL_CONTROL_2__MIF				0x01

+

+#define EP932_GENERAL_CONTROL_3					0x0A	

+

+#define EP932_CONFIGURATION					0x0B

+

+#define EP932_COLOR_SPACE_CONTROL				0x0C

+#define EP932_COLOR_SPACE_CONTROL__422_OUT			0x80

+#define EP932_COLOR_SPACE_CONTROL__YCC_OUT			0x40

+#define EP932_COLOR_SPACE_CONTROL__COLOR			0x20

+#define EP932_COLOR_SPACE_CONTROL__YCC_RANGE			0x10

+#define EP932_COLOR_SPACE_CONTROL__VMUTE			0x08

+#define EP932_COLOR_SPACE_CONTROL__AMUTE			0x04

+#define EP932_COLOR_SPACE_CONTROL__TREG				0x03

+		

+#define EP932_PIXEL_REPETITION_CONTROL				0x0D	

+#define EP932_PIXEL_REPETITION_CONTROL__CS_M			0x80

+#define EP932_PIXEL_REPETITION_CONTROL__CTS_M			0x40

+#define EP932_PIXEL_REPETITION_CONTROL__ADSR			0x30

+#define EP932_PIXEL_REPETITION_CONTROL__OSCSEL			0x08

+#define EP932_PIXEL_REPETITION_CONTROL__VSYNC			0x04	

+#define EP932_PIXEL_REPETITION_CONTROL__PR			0x03

+

+#define EP932_GENERAL_CONTROL_4					0x0E

+#define EP932_GENERAL_CONTROL_4__FMT12				0x80

+#define EP932_GENERAL_CONTROL_4__422_IN				0x40

+#define EP932_GENERAL_CONTROL_4__YCC_IN				0x20

+#define EP932_GENERAL_CONTROL_4__E_SYNC				0x10

+#define EP932_GENERAL_CONTROL_4__VPOL_DET			0x08

+#define EP932_GENERAL_CONTROL_4__HPOL_DET			0x04

+#define EP932_GENERAL_CONTROL_4__EESS				0x02

+#define EP932_GENERAL_CONTROL_4__HDMI				0x01

+

+#define EP932_GENERAL_CONTROL_5					0x0F

+#define EP932_GENERAL_CONTROL_5__AKSV_RDY			0x80

+#define EP932_GENERAL_CONTROL_5__RPTR				0x10

+#define EP932_GENERAL_CONTROL_5__RI_RDY				0x02

+#define EP932_GENERAL_CONTROL_5__ENC_EN				0x01

+

+#define EP932_BKSV					0x10			// BKSV1-BKSV5 0x10-0x14

+

+#define EP932_AN					0x15			// AN1-AN8 0x15-0x1C

+

+#define EP932_AKSV					0x1D			// AKSV1-AKSV5 0x1D-0x21

+

+#define EP932_RI					0x22			// RI1-RI2 0x22-0x23

+

+#define EP932_M0					0x25			// 0x25-0x32

+

+#define EP932_DE_DLY					0x32			// 10 bit

+

+#define EP932_DE_CONTROL				0x33			// 10 bit

+#define EP932_DE_CONTROL__DE_GEN					0x40

+#define EP932_DE_CONTROL__VSO_POL					0x08

+#define EP932_DE_CONTROL__HSO_POL					0x04

+

+#define EP932_DE_TOP					0x34			// 6 bit

+

+#define EP932_DE_CNT					0x36			// 10 bit

+

+#define EP932_DE_LIN					0x38			// 10 bit

+

+#define EP932_H_RES					0x3A			// 11 bit

+

+#define EP932_V_RES					0x3C			// 11 bit

+

+#define EP932_AUDIO_SUBPACKET_ALLOCATION		0x3E			// Default 0xE4

+

+#define EP932_IIS_CONTROL				0x3F			// Default 0x00

+#define EP932_IIS_CONTROL__ACR_EN					0x80

+#define EP932_IIS_CONTROL__AVI_EN					0x40

+#define EP932_IIS_CONTROL__ADO_EN					0x20

+#define EP932_IIS_CONTROL__AUDIO_EN					0x10

+#define EP932_IIS_CONTROL__WS_M						0x04

+#define EP932_IIS_CONTROL__WS_POL					0x02

+#define EP932_IIS_CONTROL__SCK_POL					0x01

+

+#define EP932_PACKET_CONTROL				0x40			// Default 0x00

+#define EP932_PACKET_CONTROL__FLAT3					0x80

+#define EP932_PACKET_CONTROL__FLAT2					0x40

+#define EP932_PACKET_CONTROL__FLAT1					0x20

+#define EP932_PACKET_CONTROL__FLAT0					0x10

+#define EP932_PACKET_CONTROL__LAYOUT					0x08

+#define EP932_PACKET_CONTROL__IIS					0x04

+#define EP932_PACKET_CONTROL__PKT_RDY					0x01

+

+#define EP932_DATA_PACKET_HEADER 			0x41			// HB0-HB2 0x41-0x43

+

+#define EP932_DATA_PACKET 				0x44			// PB0-PB27 0x44-0x5F

+

+#define EP932_CTS		 			0x60			// 20bit (3 Byte)

+

+#define EP932_N			 			0x63			// 20bit (3 Byte)

+

+#define EP932_AVI_PACKET 				0x66			// 14 Byte 0x66-0x73

+

+#define EP932_ADO_PACKET 				0x74			// 6 Byte 0x74-0x79

+

+#define EP932_SPDIF_SAMPLING_FREQUENCY 			0x7A			// 1 Byte

+

+#define EP932_CHANNEL_STATUS		 		0x7B			// 5 Byte 0x7B-0x7F

+

+#define EP932_EMBEDDED_SYNC		 		0x80			// Default 0x00

+

+#define EP932_H_DELAY					0x81			// 10 bit (2 Byte)

+

+#define EP932_H_WIDTH			 		0x83			// 10 bit (2 Byte)

+

+#define EP932_V_DELAY			 		0x85			// 6 bit

+

+#define EP932_V_WIDTH			 		0x86			// 6 bit 

+#define EP932_V_OFF_SET			 		0x87			// 12 bit (2 Byte)

+

+#define EP932_KEY_ADD			 		0xF0			// 1 Byte

+

+#define EP932_KEY_DATA			 		0xF1			// 7 Byte

+

+#endif

diff --git a/drivers/video/ep932/ep932settingsdata.c b/drivers/video/ep932/ep932settingsdata.c
new file mode 100644
index 00000000000..54a9df746ff
--- /dev/null
+++ b/drivers/video/ep932/ep932settingsdata.c
@@ -0,0 +1,294 @@
+

+#include "ep932settingsdata.h"

+

+vdo_settings ep932_vdo_settings[] = {

+	//                   HVRes_Type,             DE_Gen,                     E_Sync, AR_PR,       Pix_Freq_Type,

+	{  0,{       0,   0,   0,    0},{  0,   0,  0,   0},{0x00,  0,  0,  0,  0,   0},  0x00,                  1}, // 0:

+	// HDMI Mode

+	{  1,{VNEGHNEG, 800, 525,16666},{ 48, 640, 34, 480},{0x00, 12, 96, 10,  2,   0},  0x10,  PIX_FREQ_25175KHZ}, // 1:    640 x  480p

+	{  2,{VNEGHNEG, 858, 525,16666},{ 60, 720, 31, 480},{0x00, 12, 62,  9,  6,   0},  0x10,  PIX_FREQ_27000KHZ}, // 2:    720 x  480p  4:3

+	{  3,{VNEGHNEG, 858, 525,16666},{ 60, 720, 31, 480},{0x00, 12, 62,  9,  6,   0},  0x20,  PIX_FREQ_27000KHZ}, // 3:    720 x  480p 16:9

+	{  4,{VPOSHPOS,1650, 750,16666},{220,1280, 21, 720},{0x00,106, 40,  5,  5,   0},  0x20,  PIX_FREQ_74176KHZ}, // 4:   1280 x  720p

+	{  5,{VPOSHPOS,2200, 563,16666},{148,1920, 16, 540},{0x09, 84, 44,  2,  5,1100},  0x20,  PIX_FREQ_74176KHZ}, // 5:   1920 x 1080i

+	{  6,{VNEGHNEG, 858, 262,16666},{ 57, 720, 16, 240},{0x09, 15, 62,  4,  3, 429},  0x15,  PIX_FREQ_27000KHZ}, // 6:    720 x  480i, pix repl

+	{  7,{VNEGHNEG, 858, 262,16666},{ 57, 720, 16, 240},{0x09, 15, 62,  4,  3, 429},  0x25,  PIX_FREQ_27000KHZ}, // 7:    720 x  480i, pix repl

+	{  8,{VNEGHNEG, 858, 262,16666},{ 57, 720, 16, 240},{0x00, 15, 62,  4,  3,   0},  0x15,  PIX_FREQ_27000KHZ}, // 8:    720 x  240p, pix repl

+	{  9,{VNEGHNEG, 858, 262,16666},{ 57, 720, 16, 240},{0x00, 15, 62,  4,  3,   0},  0x25,  PIX_FREQ_27000KHZ}, // 9:    720 x  240p, pix repl

+	{ 10,{VNEGHNEG,3432, 262,16666},{228,2880, 16, 240},{0x09, 72,248,  4,  3,1716},  0x10,  PIX_FREQ_54000KHZ}, // 10:  2880 x  480i

+	{ 11,{VNEGHNEG,3432, 262,16666},{228,2880, 16, 240},{0x09, 72,248,  4,  3,1716},  0x20,  PIX_FREQ_54000KHZ}, // 11:  2880 x  480i

+	{ 12,{VNEGHNEG,3432, 262,16666},{228,2880, 16, 240},{0x00, 72,248,  4,  3,   0},  0x10,  PIX_FREQ_54000KHZ}, // 12:  2880 x  240p

+	{ 13,{VNEGHNEG,3432, 262,16666},{228,2880, 16, 240},{0x00, 72,248,  4,  3,   0},  0x20,  PIX_FREQ_54000KHZ}, // 13:  2880 x  240p

+	{ 14,{VNEGHNEG,1716, 525,16666},{120,1440, 31, 480},{0x00, 28,124,  9,  6,   0},  0x10,  PIX_FREQ_54000KHZ}, // 14:  1440 x  480p

+	{ 15,{VNEGHNEG,1716, 525,16666},{120,1440, 31, 480},{0x00, 28,124,  9,  6,   0},  0x20,  PIX_FREQ_54000KHZ}, // 15:  1440 x  480p

+	{ 16,{VPOSHPOS,2200,1125,16666},{148,1920, 37,1080},{0x00, 84, 44,  4,  5,   0},  0x20, PIX_FREQ_148352KHZ}, // 16:  1920 x 1080p

+	{ 17,{VNEGHNEG, 864, 625,20000},{ 68, 720, 40, 576},{0x00,  8, 64,  5,  5,   0},  0x10,  PIX_FREQ_27000KHZ}, // 17:   720 x  576p

+	{ 18,{VNEGHNEG, 864, 625,20000},{ 68, 720, 40, 576},{0x00,  8, 64,  5,  5,   0},  0x20,  PIX_FREQ_27000KHZ}, // 18:   720 x  576p

+	{ 19,{VPOSHPOS,1980, 750,20000},{220,1280, 21, 720},{0x00,436, 40,  5,  5,   0},  0x20,  PIX_FREQ_74250KHZ}, // 19:  1280 x  720p, 50 Hz

+	{ 20,{VPOSHPOS,2640, 563,20000},{148,1920, 16, 540},{0x09,524, 44,  2,  5,1320},  0x20,  PIX_FREQ_74250KHZ}, // 20:  1920 x 1080i, 50 Hz

+	{ 21,{VNEGHNEG, 864, 313,20000},{ 69, 720, 20, 288},{0x09,  8, 63,  2,  3, 432},  0x15,  PIX_FREQ_27000KHZ}, // 21:   720 x  576i, pix repl

+	{ 22,{VNEGHNEG, 864, 313,20000},{ 69, 720, 20, 288},{0x09,  8, 63,  2,  3, 432},  0x25,  PIX_FREQ_27000KHZ}, // 22:   720 x  576i, pix repl

+	{ 23,{VNEGHNEG, 864, 313,20000},{ 69, 720, 20, 288},{0x00,  8, 63,  3,  3,   0},  0x15,  PIX_FREQ_27000KHZ}, // 23:   720 x  288p, pix repl

+	{ 24,{VNEGHNEG, 864, 313,20000},{ 69, 720, 20, 288},{0x00,  8, 63,  3,  3,   0},  0x25,  PIX_FREQ_27000KHZ}, // 24:   720 x  288p, pix repl

+	{ 25,{VNEGHNEG,3456, 313,20000},{276,2880, 20, 288},{0x09, 44,252,  2,  3,1728},  0x10,  PIX_FREQ_54000KHZ}, // 25:  2880 x  576i

+	{ 26,{VNEGHNEG,3456, 313,20000},{276,2880, 20, 288},{0x09, 44,252,  2,  3,1728},  0x20,  PIX_FREQ_54000KHZ}, // 26:  2880 x  576i

+	{ 27,{VNEGHNEG,3456, 313,20000},{276,2880, 20, 288},{0x00, 44,252,  3,  3,   0},  0x10,  PIX_FREQ_54000KHZ}, // 27:  2880 x  288p

+	{ 28,{VNEGHNEG,3456, 313,20000},{276,2880, 20, 288},{0x00, 44,252,  3,  3,   0},  0x20,  PIX_FREQ_54000KHZ}, // 28:  2880 x  288p

+	{ 29,{VPOSHNEG,1728, 625,20000},{136,1440, 40, 576},{0x00, 20,128,  5,  5,   0},  0x10,  PIX_FREQ_54000KHZ}, // 29:  1440 x  576p

+	{ 30,{VPOSHNEG,1728, 625,20000},{136,1440, 40, 576},{0x00, 20,128,  5,  5,   0},  0x20,  PIX_FREQ_54000KHZ}, // 30:  1440 x  576p

+	{ 31,{VPOSHPOS,2640,1125,20000},{148,1920, 37,1080},{0x00,524, 44,  4,  5,   0},  0x20, PIX_FREQ_148500KHZ}, // 31:  1920 x 1080p, 50 Hz

+	{ 32,{VPOSHPOS,2750,1125,41666},{148,1920, 37,1080},{0x00,634, 44,  4,  5,   0},  0x20,  PIX_FREQ_74176KHZ}, // 32:  1920 x 1080p

+	{ 33,{VPOSHPOS,2640,1125,40000},{148,1920, 37,1080},{0x00,524, 44,  4,  5,   0},  0x20,  PIX_FREQ_74250KHZ}, // 33:  1920 x 1080p, 25 Hz

+	{ 34,{VPOSHPOS,2200,1125,33333},{148,1920, 37,1080},{0x00, 84, 44,  4,  5,   0},  0x20,  PIX_FREQ_74176KHZ}, // 34:  1920 x 1080p

+

+	{ 35,{VNEGHNEG,3432, 525,16666},{240,2880, 31, 480},{0x00, 92,248,  9,  6,   0},  0x10, PIX_FREQ_108000KHZ}, // 35:  2880 x  480p

+	{ 36,{VNEGHNEG,3432, 525,16666},{240,2880, 31, 480},{0x00, 92,248,  9,  6,   0},  0x20, PIX_FREQ_108000KHZ}, // 36:  2880 x  480p

+	{ 37,{VNEGHNEG,3456, 625,20000},{272,2880, 40, 576},{0x00, 44,256,  5,  5,   0},  0x10, PIX_FREQ_108000KHZ}, // 37:  2880 x  576p @ 50Hz

+	{ 38,{VNEGHNEG,3456, 625,20000},{272,2880, 40, 576},{0x00, 44,256,  5,  5,   0},  0x20, PIX_FREQ_108000KHZ}, // 38:  2880 x  576p @ 50Hz

+	{ 39,{VPOSHNEG,2304, 625,20000},{184,1920, 58, 540},{0x09, 28,168,  2,  5,1152},  0x20,  PIX_FREQ_72000KHZ}, // 39:  1920 x 1080i @ 50Hz

+	{ 40,{VPOSHPOS,2640, 563,10000},{148,1920, 16, 540},{0x09,524, 44,  2,  5,1320},  0x20, PIX_FREQ_148500KHZ}, // 40:  1920 x 1080i @ 100Hz

+	{ 41,{VPOSHPOS,1980, 750,10000},{220,1280, 21, 720},{0x00,436, 40,  5,  5,   0},  0x20, PIX_FREQ_148500KHZ}, // 41:  1280 x  720p @ 100Hz

+	{ 42,{VNEGHNEG, 864, 625,10000},{ 68, 720, 40, 576},{0x00,  8, 64,  5,  5,   0},  0x10,  PIX_FREQ_54000KHZ}, // 42:   720 x  576p @ 100Hz

+	{ 43,{VNEGHNEG, 864, 625,10000},{ 68, 720, 40, 576},{0x00,  8, 64,  5,  5,   0},  0x20,  PIX_FREQ_54000KHZ}, // 43:   720 x  576p @ 100Hz

+	{ 44,{VNEGHNEG, 864, 313,10000},{ 69, 720, 20, 288},{0x09,  8, 63,  2,  3, 432},  0x15,  PIX_FREQ_54000KHZ}, // 44:   720 x  576i @ 100Hz, pix repl

+	{ 45,{VNEGHNEG, 864, 313,10000},{ 69, 720, 20, 288},{0x09,  8, 63,  2,  3, 432},  0x25,  PIX_FREQ_54000KHZ}, // 45:   720 x  576i @ 100Hz, pix repl

+	{ 46,{VPOSHPOS,2200, 563, 8333},{148,1920, 16, 540},{0x09, 84, 44,  2,  5,2200},  0x20, PIX_FREQ_148352KHZ}, // 46:  1920 x 1080i @ 119.88/120Hz

+	{ 47,{VPOSHPOS,1650, 750, 8333},{220,1280, 21, 720},{0x00,106, 40,  5,  5,   0},  0x20, PIX_FREQ_148352KHZ}, // 47:  1280 x  720p @ 119.88/120Hz

+	{ 48,{VNEGHNEG, 858, 525, 8333},{ 60, 720, 31, 480},{0x00, 12, 62,  9,  6,   0},  0x10,  PIX_FREQ_54000KHZ}, // 48:   720 x  480p @ 119.88/120Hz

+	{ 49,{VNEGHNEG, 858, 525, 8333},{ 60, 720, 31, 480},{0x00, 12, 62,  9,  6,   0},  0x20,  PIX_FREQ_54000KHZ}, // 49:   720 x  480p @ 119.88/120Hz

+	{ 50,{VNEGHNEG, 858, 262, 8333},{ 57, 720, 16, 240},{0x09, 15, 62,  4,  3, 429},  0x15,  PIX_FREQ_54000KHZ}, // 50:   720 x  480i @ 119.88/120Hz, pix repl

+	{ 51,{VNEGHNEG, 858, 262, 8333},{ 57, 720, 16, 240},{0x09, 15, 62,  4,  3, 429},  0x25,  PIX_FREQ_54000KHZ}, // 51:   720 x  480i @ 119.88/120Hz, pix repl

+	{ 52,{VNEGHNEG, 864, 625, 5000},{ 68, 720, 40, 576},{0x00,  8, 64,  5,  5,   0},  0x10, PIX_FREQ_108000KHZ}, // 52:   720 x  576p @ 200Hz

+	{ 53,{VNEGHNEG, 864, 625, 5000},{ 68, 720, 40, 576},{0x00,  8, 64,  5,  5,   0},  0x20, PIX_FREQ_108000KHZ}, // 53:   720 x  576p @ 200Hz

+	{ 54,{VNEGHNEG, 864, 313, 5000},{ 69, 720, 20, 288},{0x09,  8, 63,  2,  3, 432},  0x15, PIX_FREQ_108000KHZ}, // 54:   720 x  576i @ 200Hz, pix repl

+	{ 55,{VNEGHNEG, 864, 313, 5000},{ 69, 720, 20, 288},{0x09,  8, 63,  2,  3, 432},  0x25, PIX_FREQ_108000KHZ}, // 55:   720 x  576i @ 200Hz, pix repl

+	{ 56,{VNEGHNEG, 858, 525, 4166},{ 60, 720, 31, 480},{0x00, 12, 62,  9,  6,   0},  0x10, PIX_FREQ_108000KHZ}, // 56:   720 x  480p @ 239.76/240Hz

+	{ 57,{VNEGHNEG, 858, 525, 4166},{ 60, 720, 31, 480},{0x00, 12, 62,  9,  6,   0},  0x20, PIX_FREQ_108000KHZ}, // 57:   720 x  480p @ 239.76/240Hz

+	{ 58,{VNEGHNEG, 858, 263, 4166},{ 57, 720, 16, 240},{0x09, 15, 62,  4,  3, 429},  0x15, PIX_FREQ_108000KHZ}, // 58:   720 x  480i @ 239.76/240Hz, pix repl

+	{ 59,{VNEGHNEG, 858, 263, 4166},{ 57, 720, 16, 240},{0x09, 15, 62,  4,  3, 429},  0x25, PIX_FREQ_108000KHZ}, // 59:   720 x  480i @ 239.76/240Hz, pix repl

+

+	// Special

+	{  6,{VNEGHNEG,1716, 262,16666},{114,1440, 16, 240},{0x09, 30,124,  4,  3, 858},  0x14,  PIX_FREQ_27000KHZ}, // 60:   720 x  480i, pix repl

+	{  7,{VNEGHNEG,1716, 262,16666},{114,1440, 16, 240},{0x09, 30,124,  4,  3, 858},  0x24,  PIX_FREQ_27000KHZ}, // 61:   720 x  480i, pix repl

+	{  8,{VNEGHNEG,1716, 262,16666},{114,1440, 16, 240},{0x00, 30,124,  4,  3,   0},  0x14,  PIX_FREQ_27000KHZ}, // 62:   720 x  240p, pix repl

+	{  9,{VNEGHNEG,1716, 262,16666},{114,1440, 16, 240},{0x00, 30,124,  4,  3,   0},  0x24,  PIX_FREQ_27000KHZ}, // 63:   720 x  240p, pix repl

+

+	{ 21,{VNEGHNEG,1728, 313,20000},{192,1440, 20, 288},{0x09, 20,128,  2,  3, 864},  0x14,  PIX_FREQ_27000KHZ}, // 64:   720 x  576i, pix repl

+	{ 22,{VNEGHNEG,1728, 313,20000},{192,1440, 20, 288},{0x09, 20,128,  2,  3, 864},  0x24,  PIX_FREQ_27000KHZ}, // 65:   720 x  576i, pix repl

+	{ 23,{VNEGHNEG,1728, 313,20000},{192,1440, 20, 288},{0x00, 20,128,  3,  3,   0},  0x14,  PIX_FREQ_27000KHZ}, // 66:   720 x  288p, pix repl

+	{ 24,{VNEGHNEG,1728, 313,20000},{192,1440, 20, 288},{0x00, 20,128,  3,  3,   0},  0x24,  PIX_FREQ_27000KHZ}, // 67:   720 x  288p, pix repl

+

+	{ 44,{VNEGHNEG,1728, 313,10000},{192,1440, 20, 288},{0x09, 20,128,  2,  3, 864},  0x14,  PIX_FREQ_54000KHZ}, // 68:   720 x  576i @ 100Hz, pix repl

+	{ 45,{VNEGHNEG,1728, 313,10000},{192,1440, 20, 288},{0x09, 20,128,  2,  3, 864},  0x24,  PIX_FREQ_54000KHZ}, // 69:   720 x  576i @ 100Hz, pix repl

+

+	{ 50,{VNEGHNEG,1716, 262, 8333},{114,1440, 16, 240},{0x09, 30,124,  4,  3, 858},  0x14,  PIX_FREQ_54000KHZ}, // 70:   720 x  480i @ 119.88/120Hz, pix repl

+	{ 51,{VNEGHNEG,1716, 262, 8333},{114,1440, 16, 240},{0x09, 30,124,  4,  3, 858},  0x24,  PIX_FREQ_54000KHZ}, // 71:   720 x  480i @ 119.88/120Hz, pix repl

+

+	{ 54,{VNEGHNEG,1728, 313, 5000},{192,1440, 20, 288},{0x09, 20,128,  2,  3, 864},  0x14, PIX_FREQ_108000KHZ}, // 72:   720 x  576i @ 200Hz, pix repl

+	{ 55,{VNEGHNEG,1728, 313, 5000},{192,1440, 20, 288},{0x09, 20,128,  2,  3, 864},  0x24, PIX_FREQ_108000KHZ}, // 73:   720 x  576i @ 200Hz, pix repl

+

+	{ 58,{VNEGHNEG,1716, 262, 4166},{114,1440, 16, 240},{0x09, 30,124,  4,  3, 858},  0x14, PIX_FREQ_108000KHZ}, // 74:   720 x  480i @ 239.76/240Hz, pix repl

+	{ 59,{VNEGHNEG,1716, 262, 4166},{114,1440, 16, 240},{0x09, 30,124,  4,  3, 858},  0x24, PIX_FREQ_108000KHZ}, // 75:   720 x  480i @ 239.76/240Hz, pix repl

+

+	// PC Mode (start form 76)

+	{128,{VNEGHPOS, 832, 445,16683},{ 96, 640, 61, 350},{0x00, 28, 64, 32,  3,   0},  0x00,        PIX_FREQ_PC}, // 128:  640 x  350p @ 60HZ d

+	{129,{VNEGHPOS, 832, 445,14285},{ 96, 640, 61, 350},{0x00, 28, 64, 32,  3,   0},  0x00,        PIX_FREQ_PC}, // 129:  640 x  350p @ 70HZ d

+	{130,{VNEGHPOS, 832, 445,13333},{ 96, 640, 61, 350},{0x00, 28, 64, 32,  3,   0},  0x00,        PIX_FREQ_PC}, // 130:  640 x  350p @ 75HZ d

+	{131,{VNEGHPOS, 832, 445,11753},{ 96, 640, 61, 350},{0x00, 28, 64, 32,  3,   0},  0x00,        PIX_FREQ_PC}, // 131:  640 x  350p @ 85HZ

+	

+	{132,{VPOSHNEG, 832, 445,16683},{ 96, 640, 42, 400},{0x00, 28, 64,  1,  3,   0},  0x00,        PIX_FREQ_PC}, // 132:  640 x  400p @ 60HZ d

+	{133,{VPOSHNEG, 832, 445,14285},{ 96, 640, 42, 400},{0x00, 28, 64,  1,  3,   0},  0x00,        PIX_FREQ_PC}, // 133:  640 x  400p @ 70HZ d

+	{134,{VPOSHNEG, 832, 445,13333},{ 96, 640, 42, 400},{0x00, 28, 64,  1,  3,   0},  0x00,        PIX_FREQ_PC}, // 134:  640 x  400p @ 75HZ d

+	{135,{VPOSHNEG, 832, 445,11753},{ 96, 640, 42, 400},{0x00, 28, 64,  1,  3,   0},  0x00,        PIX_FREQ_PC}, // 135:  640 x  400p @ 85HZ

+

+	{136,{VPOSHNEG, 900, 449,16683},{108, 720, 43, 400},{0x00, 14,108, 13,  2,   0},  0x00,        PIX_FREQ_PC}, // 136:  720 x  400p @ 60HZ d

+	{137,{VPOSHNEG, 900, 449,14285},{108, 720, 43, 400},{0x00, 14,108, 13,  2,   0},  0x00,        PIX_FREQ_PC}, // 137:  720 x  400p @ 70HZ d

+	{138,{VPOSHNEG, 900, 449,13333},{108, 720, 43, 400},{0x00, 14,108, 13,  2,   0},  0x00,        PIX_FREQ_PC}, // 138:  720 x  400p @ 75HZ d

+	{139,{VPOSHNEG, 936, 446,11759},{108, 720, 43, 400},{0x00, 32, 72,  1,  3,   0},  0x00,        PIX_FREQ_PC}, // 139:  720 x  400p @ 85HZ

+

+	// VGA

+	{140,{VNEGHNEG, 800, 525,16683},{ 48, 640, 34, 480},{0x00,  8,100,  8,  4,   0},  0x10,  PIX_FREQ_25175KHZ}, // 140:  640 x  480p @ 60Hz

+	{141,{VNEGHNEG, 832, 520,13734},{128, 640, 29, 480},{0x00, 20, 40,  9,  3,   0},  0x10,        PIX_FREQ_PC}, // 141:  640 x  480p @ 72HZ

+	{142,{VNEGHNEG, 840, 500,13333},{120, 640, 17, 480},{0x00, 12, 64,  1,  3,   0},  0x10,        PIX_FREQ_PC}, // 142:  640 x  480p @ 75HZ

+	{143,{VNEGHNEG, 832, 509,11763},{ 80, 640, 26, 480},{0x00, 52, 56,  1,  3,   0},  0x10,        PIX_FREQ_PC}, // 143:  640 x  480p @ 85HZ

+	

+	// SVGA

+	{144,{VPOSHPOS,1056, 628,16579},{ 88, 800, 24, 600},{0x00, 36,128,  1,  4,   0},  0x10,        PIX_FREQ_PC}, // 144:  800 x  600p @ 60HZ

+	{145,{VPOSHPOS,1040, 666,13852},{ 64, 800, 24, 600},{0x00, 52,120, 37,  6,   0},  0x10,        PIX_FREQ_PC}, // 145:  800 x  600p @ 72HZ

+	{146,{VPOSHPOS,1056, 625,13333},{160, 800, 22, 600},{0x00, 12, 80,  1,  3,   0},  0x10,        PIX_FREQ_PC}, // 146:  800 x  600p @ 75HZ

+	{147,{VPOSHPOS,1048, 631,11756},{152, 800, 28, 600},{0x00, 28, 64,  1,  3,   0},  0x10,        PIX_FREQ_PC}, // 147:  800 x  600p @ 85HZ

+

+	{148,{VPOSHPOS,1088, 517,16666},{112, 848, 24, 480},{0x00, 12,112,  6,  8,   0},  0x20,        PIX_FREQ_PC}, // 148:  848 x  480p @ 60HZ

+	{149,{VPOSHPOS,1088, 517,14285},{112, 848, 24, 480},{0x00, 12,112,  6,  8,   0},  0x20,        PIX_FREQ_PC}, // 149:  848 x  480p @ 70HZ d

+	{150,{VPOSHPOS,1088, 517,13333},{112, 848, 24, 480},{0x00, 12,112,  6,  8,   0},  0x20,        PIX_FREQ_PC}, // 150:  848 x  480p @ 75HZ d

+	{151,{VPOSHPOS,1088, 517,11764},{112, 848, 24, 480},{0x00, 12,112,  6,  8,   0},  0x20,        PIX_FREQ_PC}, // 151:  848 x  480p @ 85HZ d

+

+	// XGA

+	{152,{VNEGHNEG,1344, 806,16665},{160,1024, 30, 768},{0x00, 20,136,  3,  6,   0},  0x10,        PIX_FREQ_PC}, // 152: 1024 x  768p @ 60HZ

+	{153,{VNEGHNEG,1328, 806,14271},{144,1024, 30, 768},{0x00, 20,136,  3,  6,   0},  0x10,        PIX_FREQ_PC}, // 153: 1024 x  768p @ 70HZ

+	{154,{VPOSHPOS,1312, 800,13328},{176,1024, 29, 768},{0x00, 12, 96,  1,  3,   0},  0x10,        PIX_FREQ_PC}, // 154: 1024 x  768p @ 75HZ

+	{155,{VPOSHPOS,1376, 808,11765},{208,1024, 37, 768},{0x00, 44, 96,  1,  3,   0},  0x10,        PIX_FREQ_PC}, // 155: 1024 x  768p @ 85HZ

+

+	{156,{VPOSHPOS,1600, 900,16666},{256,1152, 33, 864},{0x00, 60,128,  1,  3,   0},  0x10,        PIX_FREQ_PC}, // 156: 1152 x  864p @ 60HZ d

+	{157,{VPOSHPOS,1600, 900,14285},{256,1152, 33, 864},{0x00, 60,128,  1,  3,   0},  0x10,        PIX_FREQ_PC}, // 157: 1152 x  864p @ 70HZ d

+	{158,{VPOSHPOS,1600, 900,13333},{256,1152, 33, 864},{0x00, 60,128,  1,  3,   0},  0x10, PIX_FREQ_108000KHZ}, // 158: 1152 x  864p @ 75Hz

+	{159,{VPOSHPOS,1600, 900,11764},{256,1152, 33, 864},{0x00, 60,128,  1,  3,   0},  0x10,        PIX_FREQ_PC}, // 159: 1152 x  864p @ 85HZ d

+

+	{160,{VPOSHNEG,1664, 798,16702},{192,1280, 21, 768},{0x00, 60,128,  3,  7,   0},  0x20,        PIX_FREQ_PC}, // 160: 1280 x  768p @ 60HZ

+	{161,{VPOSHNEG,1696, 805,14285},{208,1280, 28, 768},{0x00, 76,128,  3,  7,   0},  0x20,        PIX_FREQ_PC}, // 161: 1280 x  768p @ 70HZ d

+	{162,{VPOSHNEG,1696, 805,13352},{208,1280, 28, 768},{0x00, 76,128,  3,  7,   0},  0x20,        PIX_FREQ_PC}, // 162: 1280 x  768p @ 75HZ

+	{163,{VPOSHNEG,1712, 809,11787},{216,1280, 32, 768},{0x00, 76,136,  3,  7,   0},  0x20,        PIX_FREQ_PC}, // 163: 1280 x  768p @ 85HZ

+

+	{164,{VPOSHPOS,1800,1000,16666},{312,1280, 37, 960},{0x00, 92,112,  1,  3,   0},  0x10, PIX_FREQ_108000KHZ}, // 164: 1280 x  960p @ 60Hz

+	{165,{VPOSHPOS,1728,1011,14285},{224,1280, 48, 960},{0x00, 60,160,  1,  3,   0},  0x10,        PIX_FREQ_PC}, // 165: 1280 x  960p @ 70HZ d

+	{166,{VPOSHPOS,1728,1011,13333},{224,1280, 48, 960},{0x00, 60,160,  1,  3,   0},  0x10,        PIX_FREQ_PC}, // 166: 1280 x  960p @ 75HZ d

+	{167,{VPOSHPOS,1728,1011,11764},{224,1280, 48, 960},{0x00, 60,160,  1,  3,   0},  0x10, PIX_FREQ_148500KHZ}, // 167: 1280 x  960p @ 85Hz

+

+	// SXGA

+	{168,{VPOSHPOS,1688,1066,16661},{248,1280, 39,1024},{0x00, 44,112,  1,  3,   0},  0x10, PIX_FREQ_108000KHZ}, // 168: 1280 x 1024p @ 60Hz

+	{169,{VPOSHPOS,1688,1066,14285},{248,1280, 39,1024},{0x00, 12,144,  1,  3,   0},  0x10,        PIX_FREQ_PC}, // 169: 1280 x 1024p @ 70HZ d

+	{170,{VPOSHPOS,1688,1066,13328},{248,1280, 39,1024},{0x00, 12,144,  1,  3,   0},  0x10,        PIX_FREQ_PC}, // 170: 1280 x 1024p @ 75HZ

+	{171,{VPOSHPOS,1728,1072,11761},{224,1280, 45,1024},{0x00, 60,160,  1,  3,   0},  0x10,        PIX_FREQ_PC}, // 171: 1280 x 1024p @ 85HZ

+

+	{172,{VPOSHPOS,1792, 795,16662},{256,1360, 19, 768},{0x00, 60,112,  3,  6,   0},  0x20,        PIX_FREQ_PC}, // 172: 1360 x  768p @ 60HZ

+	{173,{VPOSHPOS,1792, 795,14285},{256,1360, 19, 768},{0x00, 60,112,  3,  6,   0},  0x20,        PIX_FREQ_PC}, // 173: 1360 x  768p @ 70HZ d

+	{174,{VPOSHPOS,1792, 795,13333},{256,1360, 19, 768},{0x00, 60,112,  3,  6,   0},  0x20,        PIX_FREQ_PC}, // 174: 1360 x  768p @ 75HZ d

+	{175,{VPOSHPOS,1792, 795,11764},{256,1360, 19, 768},{0x00, 60,112,  3,  6,   0},  0x20,        PIX_FREQ_PC}, // 175: 1360 x  768p @ 85HZ d

+

+	{176,{VPOSHNEG,1864,1089,16672},{232,1400, 33,1050},{0x00, 84,144,  3,  4,   0},  0x10,        PIX_FREQ_PC}, // 176: 1400 x 1050p @ 60HZ

+	{177,{VPOSHNEG,1896,1099,14285},{248,1400, 43,1050},{0x00,100,144,  3,  4,   0},  0x10,        PIX_FREQ_PC}, // 177: 1400 x 1050p @ 70HZ d

+	{178,{VPOSHNEG,1896,1099,13357},{248,1400, 43,1050},{0x00,100,144,  3,  4,   0},  0x10,        PIX_FREQ_PC}, // 178: 1400 x 1050p @ 75HZ

+	{179,{VPOSHNEG,1912,1105,11770},{256,1400, 49,1050},{0x00,100,152,  3,  4,   0},  0x10,        PIX_FREQ_PC}, // 179: 1400 x 1050p @ 85HZ

+

+	{180,{VPOSHNEG,1904, 934,16698},{232,1440, 26, 900},{0x00, 76,152,  3,  6,   0},  0x00,        PIX_FREQ_PC}, // 180: 1440 x  900p @ 60HZ

+	{181,{VPOSHNEG,1936, 942,14285},{248,1440, 34, 900},{0x00, 92,152,  3,  6,   0},  0x00,        PIX_FREQ_PC}, // 181: 1440 x  900p @ 70HZ d

+	{182,{VPOSHNEG,1936, 942,13336},{248,1440, 34, 900},{0x00, 92,152,  3,  6,   0},  0x00,        PIX_FREQ_PC}, // 182: 1440 x  900p @ 75HZ

+	{183,{VPOSHNEG,1952, 948,11786},{256,1440, 40, 900},{0x00,100,152,  3,  6,   0},  0x00,        PIX_FREQ_PC}, // 183: 1440 x  900p @ 85HZ

+

+	// UXGA

+	{184,{VPOSHPOS,2160,1250,16666},{304,1600, 47,1200},{0x00, 60,192,  1,  3,   0},  0x10,        PIX_FREQ_PC}, // 184: 1600 x 1200p @ 60HZ

+	{185,{VPOSHPOS,2160,1250,14285},{304,1600, 47,1200},{0x00, 60,192,  1,  3,   0},  0x10,        PIX_FREQ_PC}, // 185: 1600 x 1200p @ 70HZ

+	{186,{VPOSHPOS,2160,1250,13333},{304,1600, 47,1200},{0x00, 60,192,  1,  3,   0},  0x10,        PIX_FREQ_PC}, // 186: 1600 x 1200p @ 75HZ

+	{187,{VPOSHPOS,2160,1250,11764},{304,1600, 47,1200},{0x00, 60,192,  1,  3,   0},  0x10,        PIX_FREQ_PC}, // 186: 1600 x 1200p @ 85HZ

+	

+	{188,{VPOSHNEG,2240,1089,16679},{280,1680, 31,1050},{0x00,100,176,  3,  6,   0},  0x10,        PIX_FREQ_PC}, // 188: 1680 x 1050p @ 60HZ

+	{189,{VPOSHNEG,2272,1099,14285},{296,1680, 41,1050},{0x00,116,176,  3,  6,   0},  0x10,        PIX_FREQ_PC}, // 189: 1680 x 1050p @ 70HZ d

+	{190,{VPOSHNEG,2272,1099,13352},{296,1680, 41,1050},{0x00,116,176,  3,  6,   0},  0x10,        PIX_FREQ_PC}, // 190: 1680 x 1050p @ 75HZ

+	{191,{VPOSHNEG,2288,1105,11772},{304,1680, 47,1050},{0x00,124,176,  3,  6,   0},  0x10,        PIX_FREQ_PC}, // 191: 1680 x 1050p @ 85HZ

+

+	{192,{VPOSHNEG,2448,1394,16666},{328,1792, 47,1344},{0x00,124,200,  1,  3,   0},  0x10,        PIX_FREQ_PC}, // 192: 1792 x 1344p @ 60HZ

+	{193,{VPOSHNEG,2456,1417,14285},{352,1792, 70,1344},{0x00, 92,216,  1,  3,   0},  0x10,        PIX_FREQ_PC}, // 193: 1792 x 1344p @ 70HZ d

+	{194,{VPOSHNEG,2456,1417,13333},{352,1792, 70,1344},{0x00, 92,216,  1,  3,   0},  0x10,        PIX_FREQ_PC}, // 194: 1792 x 1344p @ 75HZ

+	{195,{VPOSHNEG,2456,1417,11764},{352,1792, 70,1344},{0x00, 92,216,  1,  3,   0},  0x10,        PIX_FREQ_PC}, // 195: 1792 x 1344p @ 85HZ d

+

+	{196,{VPOSHNEG,2528,1439,16668},{352,1856, 44,1392},{0x00, 92,224,  1,  3,   0},  0x10,        PIX_FREQ_PC}, // 196: 1856 x 1392p @ 60HZ

+	{197,{VPOSHNEG,2560,1500,14285},{352,1856,105,1392},{0x00,124,224,  1,  3,   0},  0x10,        PIX_FREQ_PC}, // 197: 1856 x 1392p @ 70HZ d

+	{198,{VPOSHNEG,2560,1500,13333},{352,1856,105,1392},{0x00,124,224,  1,  3,   0},  0x10,        PIX_FREQ_PC}, // 198: 1856 x 1392p @ 75HZ

+	{199,{VPOSHNEG,2560,1500,11764},{352,1856,105,1392},{0x00,124,224,  1,  3,   0},  0x10,        PIX_FREQ_PC}, // 199: 1856 x 1392p @ 85HZ d

+

+	{200,{VPOSHNEG,2592,1245,16698},{336,1920, 37,1200},{0x00,132,200,  3,  6,   0},  0x10,        PIX_FREQ_PC}, // 200: 1920 x 1200p @ 60HZ

+	{201,{VPOSHNEG,2608,1255,14285},{344,1920, 47,1200},{0x00,132,208,  3,  6,   0},  0x10,        PIX_FREQ_PC}, // 201: 1920 x 1200p @ 70HZ d

+	{202,{VPOSHNEG,2608,1255,13345},{344,1920, 47,1200},{0x00,132,208,  3,  6,   0},  0x10,        PIX_FREQ_PC}, // 202: 1920 x 1200p @ 75HZ

+	{203,{VPOSHNEG,2624,1262,11774},{352,1920, 54,1200},{0x00,140,208,  3,  6,   0},  0x10,        PIX_FREQ_PC}, // 203: 1920 x 1200p @ 85HZ

+

+	{204,{VPOSHNEG,2600,1500,16666},{344,1920, 57,1440},{0x00,124,208,  1,  3,   0},  0x10,        PIX_FREQ_PC}, // 204: 1920 x 1440p @ 60HZ

+	{205,{VPOSHNEG,2640,1500,14285},{352,1920, 57,1440},{0x00,140,224,  1,  3,   0},  0x10,        PIX_FREQ_PC}, // 205: 1920 x 1440p @ 70HZ d

+	{206,{VPOSHNEG,2640,1500,13333},{352,1920, 57,1440},{0x00,140,224,  1,  3,   0},  0x10,        PIX_FREQ_PC}, // 206: 1920 x 1440p @ 75HZ

+	{207,{VPOSHNEG,2640,1500,11774},{352,1920, 57,1440},{0x00,140,224,  1,  3,   0},  0x10,        PIX_FREQ_PC}, // 207: 1920 x 1440p @ 85HZ d

+

+	// Special

+	{144,{VPOSHPOS,1024, 625,17777},{128, 800, 23, 600},{0x00, 20, 72,  1,  2,   0},  0x10,        PIX_FREQ_PC}, // 144:  800 x  600p @ 56HZ *

+	{160,{VNEGHPOS,1440, 790,16668},{ 80,1280, 13, 768},{0x00, 44, 32,  3,  7,   0},  0x10,        PIX_FREQ_PC}, // 160: 1280 x  768p @ 60HZ * (Reduced Blanking)

+	{176,{VNEGHPOS,1560,1080,16681},{ 80,1400, 24,1050},{0x00, 44, 32,  3,  4,   0},  0x10,        PIX_FREQ_PC}, // 176: 1400 x 1050p @ 60HZ * (Reduced Blanking)

+	{180,{VNEGHPOS,1600, 926,16694},{ 80,1440, 18, 900},{0x00, 44, 32,  3,  6,   0},  0x10,        PIX_FREQ_PC}, // 180: 1440 x  900p @ 60HZ * (Reduced Blanking)

+	{184,{VPOSHPOS,2160,1250,15484},{304,1600, 47,1200},{0x00, 60,192,  1,  3,   0},  0x10,        PIX_FREQ_PC}, // 184: 1600 x 1200p @ 65HZ *

+	{188,{VNEGHPOS,1840,1080,16699},{ 80,1680, 22,1050},{0x00, 44, 32,  3,  6,   0},  0x10,        PIX_FREQ_PC}, // 188: 1680 x 1050p @ 60HZ * (Reduced Blanking)

+	{200,{VNEGHPOS,2080,1235,16680},{ 80,1920, 27,1200},{0x00, 44, 32,  3,  6,   0},  0x10,        PIX_FREQ_PC}, // 200: 1920 x 1200p @ 60HZ * (Reduced Blanking)

+};

+

+unsigned char ep932_vdo_settings_max = (sizeof(ep932_vdo_settings)/sizeof(ep932_vdo_settings[0]));

+

+// Index = [Channel Number]

+ado_settings ep932_ado_settings[] = {

+	// SpeakerMapping, Flat

+	{0x00, 0xF0}, // 0.0 - Flat All

+	{0x00, 0x00}, // 2.0 - SD0

+	{0x04, 0xA0}, // 3.0 - SD0 +SD2

+	{0x08, 0xA0}, // 4.0 - SD0 +SD1 +SD2 

+	{0x07, 0x80}, // 4.1 - SD0 +SD3

+	{0x0B, 0x80}, // 5.1 - SD0 +SD1 +SD3

+	{0x0F, 0x00}, // 6.1 - SD0 +SD2 +SD3

+	{0x13, 0x00}, // 7.1 - SD0 +SD1 +SD2 +SD3

+};

+

+// Index = [Pixel Freq Type]

+n_cts_settings n_cts_32k[] = {

+	{ 4576, 28125},        // ( 28125,  4576),  25.20 MHZ / 1.001

+	{ 4096, 25200},        // ( 25200,  4096),  25.20 MHZ

+

+	{ 4096, 27000},        // ( 27000,  4096),  27.00 MHZ

+	{ 4096, 27027},        // ( 27027,  4096),  27.00 MHZ * 1.001

+

+	{ 4096, 54000},        // ( 54000,  4096),  54.00 MHZ

+	{ 4096, 54054},        // ( 54054,  4096),  54.00 MHZ * 1.001

+

+	{ 4096, 72000},        // ( 72000,  4096),  72.00 MHZ

+

+	{11648,210937},        // (210937, 11648),  74.25 MHZ / 1.001

+	{ 4096, 74250},        // ( 74250,  4096),  74.25 MHZ

+

+	{ 4096,108000},        // (108000,  4096), 108.00 MHZ

+	{ 4096,108108},        // (108108,  4096), 108.00 MHZ * 1.001

+

+	{11648,421875},        // (421875, 11648), 148.50 MHZ / 1.001

+	{ 4096,148500},        // (148500,  4096), 148.50 MHZ

+

+	{ 4096,148500},        // PC

+};

+        

+n_cts_settings n_cts_44k1[] = {

+	{ 7007, 31250},        // ( 31250,  7007),  25.20 MHZ / 1.001

+	{ 6272, 28000},        // ( 28000,  6272),  25.20 MHZ

+

+	{ 6272, 30000},        // ( 30000,  6272),  27.00 MHZ

+	{ 6272, 30030},        // ( 30030,  6272),  27.00 MHZ * 1.001

+

+	{ 6272, 60000},        // ( 60000,  6272),  54.00 MHZ

+	{ 6272, 60060},        // ( 60060,  6272),  54.00 MHZ * 1.001

+

+	{ 6272, 80000},        // ( 80000,  6272),  72.00 MHZ

+

+	{17836,234375},        // (234375, 17836),  74.25 MHZ / 1.001

+	{ 6272, 82500},        // ( 82500,  6272),  74.25 MHZ

+

+	{ 6272,120000},        // (120000,  6272), 108.00 MHZ

+	{ 6272,120120},        // (120120,  6272), 108.00 MHZ * 1.001

+

+	{ 8918,234375},        // (234375,  8918), 148.50 MHZ / 1.001

+	{ 6272,165000},        // (165000,  6272), 148.50 MHZ

+

+	{ 6272,165000},        // PC

+};

+

+n_cts_settings n_cts_48k[] = {

+	{ 6864, 28125},        // ( 28125,  6864),  25.20 MHZ / 1.001

+	{ 6144, 25200},        // ( 25200,  6144),  25.20 MHZ

+

+	{ 6144, 27000},        // ( 27000,  6144),  27.00 MHZ

+	{ 6144, 27027},        // ( 27027,  6144),  27.00 MHZ * 1.001

+

+	{ 6144, 54000},        // ( 54000,  6144),  54.00 MHZ

+	{ 6144, 54054},        // ( 54054,  6144),  54.00 MHZ * 1.001

+

+	{ 6144, 72000},        // ( 72000,  6144),  72.00 MHZ

+

+	{11648,140625},        // (140625, 11648),  74.25 MHZ / 1.001

+	{ 6144, 74250},        // ( 74250,  6144),  74.25 MHZ

+

+	{ 6144, 108000},        // (108000,  6144), 108.00 MHZ

+	{ 6144, 108108},        // (108108,  6144), 108.00 MHZ * 1.001

+

+	{ 5824, 140625},        // (140625,  5824), 148.50 MHZ / 1.001

+	{ 6144, 148500},        // (148500,  6144), 148.50 MHZ

+

+	{ 6144, 148500},        // PC

+};

diff --git a/drivers/video/ep932/ep932settingsdata.h b/drivers/video/ep932/ep932settingsdata.h
new file mode 100644
index 00000000000..a3180c2626e
--- /dev/null
+++ b/drivers/video/ep932/ep932settingsdata.h
@@ -0,0 +1,130 @@
+/******************************************************************************\

+

+          (c) Copyright Explore Semiconductor, Inc. Limited 2005

+                           ALL RIGHTS RESERVED 

+

+--------------------------------------------------------------------------------

+

+ Please review the terms of the license agreement before using this file.

+ If you are not an authorized user, please destroy this source code file  

+ and notify Explore Semiconductor Inc. immediately that you inadvertently 

+ received an unauthorized copy.  

+

+--------------------------------------------------------------------------------

+

+  File        :  EP932SettingsData.h

+

+  Description :  Head file of EP932SettingsData.

+

+\******************************************************************************/

+

+#ifndef EP932SETTINGDATA_H

+#define EP932SETTINGDATA_H

+

+// -----------------------------------------------------------------------------

+

+#define EP932_VDO_SETTINGS_IT_START 76

+

+// Definition of H/V Polarity

+#define  VPOSHPOS               0x00

+#define  VPOSHNEG               0x04

+#define  VNEGHPOS               0x08

+#define  VNEGHNEG               0x0C

+

+// Pixel Freq Type

+typedef enum {

+	PIX_FREQ_25175KHZ = 0,

+	PIX_FREQ_25200KHZ,

+

+	PIX_FREQ_27000KHZ,

+	PIX_FREQ_27027KHZ,

+

+	PIX_FREQ_54000KHZ,

+	PIX_FREQ_54054KHZ,

+

+	PIX_FREQ_72000KHZ,

+

+	PIX_FREQ_74176KHZ,

+	PIX_FREQ_74250KHZ,

+

+	PIX_FREQ_108000KHZ,

+	PIX_FREQ_108108KHZ,

+

+	PIX_FREQ_148352KHZ,

+	PIX_FREQ_148500KHZ,

+

+	PIX_FREQ_PC

+

+} pix_freq_type;

+

+//

+// Index = [Video Code]

+//

+typedef struct _hvres_type {

+   unsigned char  hvpol;

+   unsigned short hres;

+   unsigned short vres;

+   unsigned short vprd;

+} hvres_type_t, *phvres_type;

+

+// DE Generation

+typedef struct _de_gen_settings { // VideoCode to

+	unsigned short de_dly;

+	unsigned short de_cnt;

+	unsigned char  de_top;

+	unsigned short de_lin;

+} de_gen_settings, *pde_gen_settings;

+

+// Embeded Sybc

+typedef struct _e_sync_settings { // VideoCode to

+	unsigned char  ctl;

+	unsigned short h_dly;

+	unsigned short h_width;

+	unsigned char  v_dly;

+	unsigned char  v_width;

+	unsigned short v_ofst;

+} e_sync_settings, *pe_sync_settings;

+

+// AVI Settings

+typedef struct _vdo_settings { 

+	unsigned char	videocode;

+	hvres_type_t    hvres_type;

+	de_gen_settings de_gen;

+	e_sync_settings e_sync; // (HV_Gen)

+	unsigned char   ar_pr;

+	pix_freq_type   pix_freq_type;

+} vdo_settings, *pvdo_settings;

+

+extern vdo_settings ep932_vdo_settings[];

+extern unsigned char ep932_vdo_settings_max; // = (sizeof(EP932_VDO_Settings)/sizeof(EP932_VDO_Settings[0]))

+

+// -----------------------------------------------------------------------------

+

+//

+// Index = [Channel Number]

+//

+// Audio Channel and Allocation

+typedef struct _ado_settings { // IIS ChannelNumber to

+	unsigned char speakermapping;

+	unsigned char flat;

+} ado_settings, *pado_settings;

+

+extern ado_settings ep932_ado_settings[];

+

+// -----------------------------------------------------------------------------

+

+//

+// Index = [Pixel Freq Type]

+//

+// N and CTS

+typedef struct _n_cts_setttings{ // IIS ChannelNumber to

+	unsigned long n;

+	unsigned long cts; // Use hardware to calculate the CTS

+} n_cts_settings, *pn_cts_settings;

+

+extern n_cts_settings n_cts_32k[];

+extern n_cts_settings n_cts_44k1[];

+extern n_cts_settings n_cts_48k[];

+

+

+#endif

diff --git a/drivers/video/ep932/hdcp.c b/drivers/video/ep932/hdcp.c
new file mode 100644
index 00000000000..ea2a9eedae9
--- /dev/null
+++ b/drivers/video/ep932/hdcp.c
@@ -0,0 +1,670 @@
+#include "hdcp.h"

+#include "ep932_if.h"

+#include "ddc_if.h"

+

+

+unsigned int hdcp_timecount = 0;

+hdcp_state_t hdcp_state = 0;

+unsigned char hdcp_status = 0;

+unsigned char ri_check = 0, fake_hdcp = 0;

+unsigned char *pksvlist = 0, *pbksv_bcaps3 = 0, *psha_m0 = 0;

+unsigned char ksvlistnumber = 0;

+

+

+//

+// Global Data

+//

+unsigned long temp_sha_h[5];

+unsigned char temp_hdcp[10];

+

+//int i, j;

+

+//

+// Private Functions

+//

+

+unsigned char hdcp_validate_ri(void);

+

+// Repeater

+unsigned char hdcp_compute_sha_message_digest(unsigned char hdcp_dev_count, unsigned char hdcp_depth);

+

+// SHA

+void sha_initial(void);

+void sha_push_data(unsigned char *pdata, unsigned char size);

+unsigned long *sha_get_sha_digest(void);

+void sha_calculation(unsigned long psha_h[5], unsigned long psha_w1[16]);

+

+//---------------------------------------------------------------------------------------------------------------------------

+

+void hdcp_extract_bksv_bcaps3(unsigned char *bksv_bcaps3)

+{

+	pbksv_bcaps3 = bksv_bcaps3;

+}

+

+void hdcp_extract_fifo(unsigned char *pfifolist, unsigned char listnumber)

+{

+	pksvlist = pfifolist;

+	ksvlistnumber = listnumber;

+}

+

+void hdcp_extract_sha_m0(unsigned char *sha_m0)

+{

+	psha_m0 = sha_m0;

+}

+

+void hdcp_stop()

+{

+	hdcp_timecount = 1000/HDCP_TIMER_PERIOD; // No delay for next startup

+	hdcp_status = 0;

+	hdcp_state = 0;

+	ri_check = 0;

+

+	// Disable the HDCP Engine

+	hdmi_tx_hdcp_disable();

+

+	// Disable mute for transmiter video and audio

+	hdmi_tx_mute_disable();

+}

+

+void hdcp_fake(unsigned char enable)

+{

+	fake_hdcp = enable;

+}

+

+unsigned char hdcp_get_status(void)

+{

+	return hdcp_status;

+}

+

+void hdcp_timer(void) 

+{

+	++hdcp_timecount;

+}

+

+void hdcp_ext_ri_trigger(void) 

+{

+	ri_check = 1;

+}

+

+hdcp_state_t hdcp_authentication_task(unsigned char receiverrdy)

+{

+	if( (hdcp_state > A0_WAIT_FOR_ACTIVE_RX) && !(receiverrdy) ) {

+		DBG_PRINTK(("WARNING: No RSEN or Hot-Plug in Authentication\r\n"));	

+			

+		// enable mute for transmiter video and audio

+		hdmi_tx_mute_enable();

+

+		// Confirm, Disable the HDCP Engine (actived from Downstream)

+		hdmi_tx_hdcp_disable();

+

+		// Restart HDCP authentication

+		hdcp_timecount = 0;

+		hdcp_state = A0_WAIT_FOR_ACTIVE_RX;

+		hdcp_status |= HDCP_ERROR_RSEN;

+		return hdcp_state;

+	}	   

+

+	switch(hdcp_state) {

+	// HDCP authentication

+

+		// A0 state -- Wait for Active RX

+		//          -- read and validate BKSV for every 1 second.

+		case A0_WAIT_FOR_ACTIVE_RX:

+ 		    

+printk("((((((((((((((((((((((((((((((((((((((((A0_WAIT_FOR_ACTIVE_RX:))))))))))))))))))))))))))))))))))))))))\n");

+ 	    	if(hdcp_timecount > 1000/HDCP_TIMER_PERIOD) {

+				hdcp_timecount = 0;

+   

+				if( downstream_rx_read_bksv(temp_hdcp) ) {		

+					int i;

+					for (i = 0; i < 10; i++)

+						printk("tmp[%d] = %#x\n", i, temp_hdcp[i]);

+					DBG_PRINTK(("Authentication start...\r\n"));

+		   			hdcp_state = A1_EXCHANGE_KSVS; }

+				else {	// HDCP not support

+					DBG_PRINTK(("HDCP might not be supported\r\n"));

+					downstream_rx_write_ainfo(0x00); // Make TE sense the retry to pass ATC HDCP test

+					hdcp_status |= HDCP_ERROR_BKSV;

+				}

+			}

+			break;

+

+		// A1 state -- Exchange KSVs

+		//          -- retrieve the random number

+		//          -- write AN to RX and TX

+		//          -- read and write AKSV, BKSV

+		case A1_EXCHANGE_KSVS:

+

+printk("((((((((((((((((((((((((((((((((((((((((A1:))))))))))))))))))))))))))))))))))))))))\n");

+			// Write AINFO

+			downstream_rx_write_ainfo(0x00);

+

+printk("((((((((((((((((((((((((((((((((((((((((A1:0))))))))))))))))))))))))))))))))))))))))\n");

+			// Check Repeater Bit

+			temp_hdcp[0] = downstream_rx_bcaps();

+			if(temp_hdcp[0] & 0x40) {		// REPEATER

+				hdmi_tx_rptr_set();

+				printk("repeater.\n");

+			}

+			else {						// NON-REPEATER

+				hdmi_tx_rptr_clear();

+				printk("not repeater.\n");

+			}

+

+printk("((((((((((((((((((((((((((((((((((((((((A1:1))))))))))))))))))))))))))))))))))))))))\n");

+			// Exange AN

+			for(temp_hdcp[8]=0; temp_hdcp[8]<8; ++temp_hdcp[8]) {		 	   

+			//	temp_hdcp[temp_hdcp[8]] = rand()%256;

+				temp_hdcp[temp_hdcp[8]] = jiffies%256;

+			}

+		    hdmi_tx_write_an(temp_hdcp);

+		    downstream_rx_write_an(temp_hdcp);

+

+printk("((((((((((((((((((((((((((((((((((((((((A1:2))))))))))))))))))))))))))))))))))))))))\n");

+			// Exange AKSV

+		    if(!hdmi_tx_read_aksv(temp_hdcp)) {

+			

+				if(!fake_hdcp) {

+					hdcp_state = A0_WAIT_FOR_ACTIVE_RX;

+					hdcp_status |= HDCP_ERROR_AKSV;

+					break;

+				}

+				else {

+					memset(temp_hdcp, 0x5A, 5);

+				}

+			}

+		    downstream_rx_write_aksv(temp_hdcp);

+printk("((((((((((((((((((((((((((((((((((((((((A1:3))))))))))))))))))))))))))))))))))))))))\n");

+

+			// Exange BKSV

+		    if(!downstream_rx_read_bksv(temp_hdcp)) {

+				hdcp_state = A0_WAIT_FOR_ACTIVE_RX;

+				hdcp_status |= HDCP_ERROR_BKSV;

+				break;

+			}

+		   	hdmi_tx_write_bksv(temp_hdcp);

+			if(pbksv_bcaps3) memcpy(&pbksv_bcaps3[0], temp_hdcp, 5);

+		

+printk("$$$$$$$$$$$$$$$$$$$$$$$$$state = A2.\n");

+		    hdcp_state = A2_COMPUTATIONS;

+			break;

+

+		// A2 state -- Computations

+		//          -- Wait 150ms for R0 update (min 100ms)

+		case A2_COMPUTATIONS:

+

+printk("((((((((((((((((((((((((((((((((((((((((A2:))))))))))))))))))))))))))))))))))))))))\n");

+		 	if(hdcp_timecount > 150/HDCP_TIMER_PERIOD) {

+				if(hdmi_tx_ri_rdy()) {

+					hdcp_timecount = 0;

+					hdcp_state = A3_VALIDATE_RECEIVER;

+				}

+			}

+			break;

+

+		// A3 state -- Validate Receiver

+		//          -- read and compare R0 from TX and RX

+  		//          -- allow IIC traffic or R0 compare error in 200ms

+		case A3_VALIDATE_RECEIVER: 

+printk("((((((((((((((((((((((((((((((((((((((((A3:))))))))))))))))))))))))))))))))))))))))\n");

+			if(!hdcp_validate_ri()) {

+	 	    	if(hdcp_timecount > 200/HDCP_TIMER_PERIOD) {

+					hdcp_timecount = 0;

+

+					DBG_PRINTK(("ERROR: R0 check failed\r\n"));

+

+					hdcp_state = A0_WAIT_FOR_ACTIVE_RX;	

+					hdcp_status |= HDCP_ERROR_R0;

+				}

+			}

+			else {

+				hdcp_timecount = 0;

+				hdcp_state = A6_TEST_FOR_REPEATER;

+			}

+			break;

+

+		// A4 state -- Authenticated

+		//          -- Disable mute

+		case A4_AUTHENTICATED:

+					

+printk("((((((((((((((((((((((((((((((((((((((((A4:))))))))))))))))))))))))))))))))))))))))\n");

+			// Start the HDCP Engine

+			if(!fake_hdcp) hdmi_tx_hdcp_enable(); 

+	

+			// Disable mute for transmiter video 

+			hdmi_tx_mute_disable();

+

+			DBG_PRINTK(("Authenticated\r\n"));			

+

+			hdcp_state = A5_LINK_INTEGRITY_CHECK;

+			break;

+

+		// A5 state -- Link Integrity Check every second

+		//          -- HDCP Engine must be started

+  		//          -- read and compare RI from RX and TX

+		case A5_LINK_INTEGRITY_CHECK:

+

+printk("((((((((((((((((((((((((((((((((((((((((A5:))))))))))))))))))))))))))))))))))))))))\n");

+			if(ri_check) {

+				ri_check = 0;

+

+				if(!hdcp_validate_ri()) {

+					if(!hdcp_validate_ri()) {

+

+						// enable mute for transmiter video and audio

+						hdmi_tx_mute_enable();

+

+						// Disable the HDCP Engine

+						hdmi_tx_hdcp_disable(); 

+

+						DBG_PRINTK(("ERROR: Ri check failed\r\n"));

+

+						hdcp_state = A0_WAIT_FOR_ACTIVE_RX;

+						hdcp_status |= HDCP_ERROR_RI;

+					}

+				}

+			}

+/*

+ 	    	if(hdcp_timecount > 2000/HDCP_TIMER_PERIOD) {	// Wait for 2 second

+				hdcp_timecount = 0;

+

+				if(!hdcp_validate_ri()) {

+

+					if(ri_check) { // RI_Failed_Two

+

+						// enable mute for transmiter video and audio

+						hdmi_tx_mute_enable();

+

+						// Disable the HDCP Engine

+						hdmi_tx_hdcp_disable(); 

+

+						DBG_PRINTK(("ERROR: Ri check failed\r\n"));

+

+						hdcp_state = A0_WAIT_FOR_ACTIVE_RX;

+						hdcp_status |= HDCP_ERROR_Ri;

+					}

+					else {

+						DBG_PRINTK(("WARNING: Ri check failed\r\n"));

+

+						ri_check = 1;

+						hdcp_timecount = 1500/HDCP_TIMER_PERIOD;

+					}

+				}

+				else {

+					ri_check = 0;

+				}

+			}

+*/

+			break;

+

+		// A6 state -- Test For Repeater

+		//          -- REPEATER     : Enter the WAIT_RX_RDY state;

+		//          -- NON-REPEATER : Enter the AUTHENTICATED state

+		case A6_TEST_FOR_REPEATER:   

+

+printk("((((((((((((((((((((((((((((((((((((((((A6:))))))))))))))))))))))))))))))))))))))))\n");

+			temp_hdcp[0] = downstream_rx_bcaps();

+			if(pbksv_bcaps3) pbksv_bcaps3[5] = temp_hdcp[0];

+

+			if (temp_hdcp[0] & 0x40) {	// REPEATER	

+				hdcp_state = A8_WAIT_FOR_READY;

+			}

+			else {						// NON-REPEATER

+				hdcp_state = A4_AUTHENTICATED;

+			}

+			break;

+

+		// A8 state -- Wait for READY

+		//          -- read BCAPS and check READY bit continuously

+		//          -- time out while 5-second period exceeds

+		case A8_WAIT_FOR_READY:   

+

+printk("((((((((((((((((((((((((((((((((((((((((A8: wait for ready))))))))))))))))))))))))))))))))))))))))\n");

+			temp_hdcp[0] = downstream_rx_bcaps();

+			if(pbksv_bcaps3) pbksv_bcaps3[5] = temp_hdcp[0];

+

+			if (temp_hdcp[0] & 0x20) {

+				hdcp_timecount = 0;

+				hdcp_state = A9_READ_KSV_LIST;

+			}

+			else {

+				if(hdcp_timecount > 5000/HDCP_TIMER_PERIOD) {

+					hdcp_timecount = 0;

+

+					DBG_PRINTK(("ERROR: Repeater check READY bit time-out\r\n"));

+

+					hdcp_state = A0_WAIT_FOR_ACTIVE_RX;	

+					hdcp_status |= HDCP_ERROR_REPEATERRDY;

+				}

+			}

+			break;

+

+		// A9 state -- Read KSV List

+		//          -- compute and validate SHA-1 values

+		case A9_READ_KSV_LIST:

+			

+printk("((((((((((((((((((((((((((((((((((((((((A9: read ksv list))))))))))))))))))))))))))))))))))))))))\n");

+			downstream_rx_read_bstatus(temp_hdcp);

+			if(pbksv_bcaps3) memcpy(&pbksv_bcaps3[6], temp_hdcp, 2);

+

+			if(!(temp_hdcp[0] & 0x80) && !(temp_hdcp[1] & 0x08)) {

+				if(hdcp_compute_sha_message_digest(temp_hdcp[0], temp_hdcp[1])) {

+					hdcp_state = A4_AUTHENTICATED;

+					break;

+				}

+				else {

+					hdcp_status |= HDCP_ERROR_REPEATERSHA;

+				}

+			}

+			else {

+				hdcp_status |= HDCP_ERROR_REPEATERMAX;

+			}

+

+			DBG_PRINTK(("ERROR: Repeater HDCP SHA check failed\r\n"));

+

+			hdcp_state = A0_WAIT_FOR_ACTIVE_RX;	

+			break;

+	}

+

+	return hdcp_state;

+}

+

+//----------------------------------------------------------------------------------------------------------------------

+

+unsigned char hdcp_validate_ri(void)

+{

+	unsigned short temp_ri_tx, temp_ri_rx;

+	if(!hdmi_tx_read_ri((unsigned char *)&temp_ri_tx)) return 0;		// Read form Tx is fast, do it first

+	if(!downstream_rx_read_ri((unsigned char *)&temp_ri_rx)) return 0;	// Read form Rx is slow, do it second

+//	if(temp_ri_tx != temp_ri_rx) DBG_PRINTK(("RI_Tx=0x%0.4X, RI_Rx=0x%0.4X\r\n", (int)Temp_RI_Tx, (int)temp_ri_rx));

+	if(fake_hdcp) return 1;

+	return (temp_ri_tx == temp_ri_rx);

+}

+

+//--------------------------------------------------------------------------------------------------

+

+//

+// NOTE : The following SHA calculation subroutine has not been verified in the

+//        real environment. It has been evaluated by some debugging procedure.

+//        The auther is not responsible to ensure the functionality.

+//

+unsigned char hdcp_compute_sha_message_digest(unsigned char hdcp_dev_count, unsigned char hdcp_depth) 

+{

+	int i;

+	unsigned long *sha_h;

+  

+	//////////////////////////////////////////////////////////////////////////////////////////////

+	// Calculate SHA Value

+	//

+

+	sha_initial();

+

+	//

+	// Step 1

+	// Push all KSV FIFO to SHA caculation

+	//

+

+	// Read KSV (5 byte) one by one and check the revocation list

+	for(i=0; i<hdcp_dev_count; ++i) {

+

+		// Get KSV from FIFO

+		if(!downstream_rx_read_ksv_fifo(temp_hdcp, i, hdcp_dev_count)) {

+			return 0;

+		}

+

+		// Save FIFO 

+		if(pksvlist && ksvlistnumber) {

+			if(i < ksvlistnumber) memcpy(pksvlist+(i*5), temp_hdcp, 5);

+		}

+

+		// Push KSV to the SHA block buffer (Total 5 bytes)

+		sha_push_data(temp_hdcp, 5);

+	}

+	if(hdcp_dev_count == 0) {

+		downstream_rx_read_ksv_fifo(temp_hdcp, 0, 1);

+	}

+

+	//

+	// Step 2

+	// Push BSTATUS, M0, and EOF to SHA caculation

+	//

+

+	// Get the BSTATUS, M0, and EOF

+	temp_hdcp[0] = hdcp_dev_count;	// temp_hdcp[0]   = BStatus, LSB

+	temp_hdcp[1] = hdcp_depth;		// temp_hdcp[1]   = BStatus, MSB

+	hdmi_tx_read_m0(temp_hdcp+2);	// temp_hdcp[2:9] = Read M0 from TX

+	if(psha_m0) memcpy(psha_m0+20, (unsigned char*)temp_hdcp+2, 8);

+

+	// Push the BSTATUS, and M0 to the SHA block buffer (Total 10 bytes)

+	sha_push_data(temp_hdcp, 10);

+

+	//

+	// Step 3

+	// Push the final block with length to SHA caculation

+	//

+

+	sha_h = sha_get_sha_digest();

+

+	//

+	// SHA complete

+	//////////////////////////////////////////////////////////////////////////////////////////////

+

+

+	//////////////////////////////////////////////////////////////////////////////////////////////

+	// Compare the SHA value

+	//

+

+	// read RX SHA value

+	downstream_rx_read_sha1_hash((unsigned char*)temp_sha_h); 

+	if(psha_m0) memcpy(psha_m0, (unsigned char*)temp_sha_h, 20);

+	DBG_PRINTK(("Rx_sha_h: "));  

+#ifdef DBG

+	for(i=0; i<20; i+=4) {		

+		DBG_PRINTK(("0x%0.2X%0.2X%0.2X%0.2X ", (int)(((PBYTE)temp_sha_h)[i+3]), (int)(((PBYTE)temp_sha_h)[i+2]), (int)(((PBYTE)temp_sha_h)[i+1]), (int)(((PBYTE)temp_sha_h)[i+0])));

+	}

+	DBG_PRINTK(("\r\n"));

+#endif

+	// compare the TX/RX SHA value

+	if( (hdcp_dev_count & 0x80) || (hdcp_depth & 0x08) ) {

+		DBG_PRINTK(("Max Cascade or Max Devs exceeded\r\n"));

+		return 0;

+	}

+	else if( (sha_h[0] != temp_sha_h[0]) || (sha_h[1] != temp_sha_h[1]) || (sha_h[2] != temp_sha_h[2]) || (sha_h[3] != temp_sha_h[3]) || (sha_h[4] != temp_sha_h[4]) ) {

+		DBG_PRINTK(("SHA Digit Unmatch\r\n"));

+  		return 0;

+	}

+	else {

+		DBG_PRINTK(("SHA Digit Match\r\n"));

+		return 1;

+	}

+

+	//

+	// Return the compared result

+	//////////////////////////////////////////////////////////////////////////////////////////////

+

+}

+

+//--------------------------------------------------------------------------------------------------

+// SHA Implementation

+//--------------------------------------------------------------------------------------------------

+

+unsigned long sha_h[5];

+unsigned char sha_block[64];	 	// 16*4

+unsigned char sha_block_index;

+unsigned char copysize;

+unsigned int sha_length;

+

+void sha_initial(void)

+{

+	//////////////////////////////////////////////////////////////////////////////////////////////

+	// Calculate SHA Value

+	//

+

+	// initial the SHA variables

+	sha_h[0] = 0x67452301;

+	sha_h[1] = 0xEFCDAB89;

+	sha_h[2] = 0x98BADCFE;

+	sha_h[3] = 0x10325476;

+	sha_h[4] = 0xC3D2E1F0;

+

+	// Clean the SHA Block buffer

+	memset(sha_block, 0, 64);

+	sha_block_index = 0;

+

+	sha_length = 0;

+}

+

+void sha_push_data(unsigned char *pdata, unsigned char size)

+{

+	int i;

+	sha_length += size;

+

+	while(size) {

+		// Push Data to the SHA block buffer

+		copysize = min((64-sha_block_index), size);

+		memcpy(sha_block+sha_block_index, pdata, copysize);

+		sha_block_index += copysize;

+		pdata += copysize;

+		size -= copysize;

+

+		if(sha_block_index >= 64) { // The SHA block buffer Full

+

+        // add by Eric_Lu

+

+			// Swap the sequence of SHA Block (The little-endian to big-endian)

+			unsigned char swap_temp;

+			for(i=0; i<64; i+=4) {

+			   

+				swap_temp = sha_block[i+0];

+				sha_block[i+0] = sha_block[i+3];

+				sha_block[i+3] = swap_temp;

+

+				swap_temp = sha_block[i+1];

+				sha_block[i+1] = sha_block[i+2];

+				sha_block[i+2] = swap_temp;

+			}

+         // add end

+			// Do SHA caculation for this SHA block buffer

+			sha_calculation(sha_h, (unsigned long*)sha_block);

+			memset(sha_block, 0, 64);				

+	

+			sha_block_index = 0; // Reset the Index

+		}

+	}

+}

+

+unsigned long *sha_get_sha_digest(void)

+{

+	int i;

+	unsigned char swap_temp;

+	sha_block[sha_block_index++] = 0x80;	// Set EOF

+

+	if((64 - sha_block_index) < 2) {

+		memset(sha_block, 0, 64);

+	}

+	sha_length *= 8; 

+	sha_block[62] = (sha_length >> 8) & 0xFF; 			// Pad with Length MSB

+	sha_block[63] = sha_length & 0xFF;  				// Pad with Length LSB

+

+        // add by Eric_Lu

+	// Swap the sequence of SHA Block (The little-endian to big-endian)

+	for(i=0; i<64; i+=4) {

+	   

+		swap_temp = sha_block[i+0];

+		sha_block[i+0] = sha_block[i+3];

+		sha_block[i+3] = swap_temp;

+

+		swap_temp = sha_block[i+1];

+		sha_block[i+1] = sha_block[i+2];

+		sha_block[i+2] = swap_temp;

+	}

+        // add end

+

+	// Do SHA caculation for final SHA block

+	sha_calculation(sha_h, (unsigned long*)sha_block);

+	

+	// Swap the sequence of sha_h (The big-endian to little-endian)

+	DBG_PRINTK(("sha_h:    ")); 

+	for(i=0; i<20; i+=4) {

+	   

+		temp_hdcp[0] = ((unsigned char*)sha_h)[i+0];

+		((unsigned char*)sha_h)[i+0] = ((unsigned char*)sha_h)[i+3];

+		((unsigned char*)sha_h)[i+3] = temp_hdcp[0];

+

+		temp_hdcp[0] = ((unsigned char*)sha_h)[i+1];

+		((unsigned char*)sha_h)[i+1] = ((unsigned char*)sha_h)[i+2];

+		((unsigned char*)sha_h)[i+2] = temp_hdcp[0];

+

+		DBG_PRINTK(("0x%02X%02X%02X%02X ", (int)(((unsigned char*)sha_h)[i+3]), (int)(((unsigned char*)sha_h)[i+2]), (int)(((unsigned char*)sha_h)[i+1]), (int)(((unsigned char*)sha_h)[i+0])));

+	}

+	DBG_PRINTK(("\r\n")); 

+

+	return sha_h;

+}

+

+void sha_calculation(unsigned long psha_h[5], unsigned long psha_w1[16])

+{

+	unsigned char i;

+	unsigned long temp;

+

+	// =========================================================

+	//

+	// STEP (c) : Let A = H0, B = H1, C = H2, D = H3, E = H4

+	//

+	temp_sha_h[0] = psha_h[0];

+	temp_sha_h[1] = psha_h[1];

+	temp_sha_h[2] = psha_h[2];

+	temp_sha_h[3] = psha_h[3];

+	temp_sha_h[4] = psha_h[4];

+	//

+	// =========================================================    

+													

+	// =========================================================

+	//

+	// STEP (d) : FOR t = 0 to 79 DO

+	//              1. temp = S5(A) + Ft(B,C,D) + E + Wt + Kt

+	//              2. E = D; D = C; C = S30(B); B = A; A = temp;

+	//

+	for (i = 0; i <= 79; i++) {

+		// Update the Message Word while loop time >= 16

+		if (i >= 16) {

+			// tword = psha_w1[tm03] ^ psha_w1[tm08] ^ psha_w1[tm14] ^ psha_w1[tm16];                   

+			temp = psha_w1[(i + 13) % 16] ^ psha_w1[(i + 8) % 16] ^ psha_w1[(i + 2) % 16] ^ psha_w1[i % 16];

+			psha_w1[i % 16] = (temp << 1) | (temp >> 31);

+		}

+

+		// Calculate first equation

+		temp = psha_w1[i % 16];

+

+	    temp += ((temp_sha_h[0] << 5) | (temp_sha_h[0] >> 27));

+	

+	    if (i <= 19)      temp += ((temp_sha_h[1] & temp_sha_h[2]) | (~temp_sha_h[1] & temp_sha_h[3])) + 0x5A827999;

+	    else if (i <= 39) temp += (temp_sha_h[1] ^ temp_sha_h[2] ^ temp_sha_h[3]) + 0x6ED9EBA1;

+	    else if (i <= 59) temp += ((temp_sha_h[1] & temp_sha_h[2]) | (temp_sha_h[1] & temp_sha_h[3]) | (temp_sha_h[2] & temp_sha_h[3])) + 0x8F1BBCDC;

+	    else              temp += (temp_sha_h[1] ^ temp_sha_h[2] ^ temp_sha_h[3]) + 0xCA62C1D6;

+

+	    temp += temp_sha_h[4];

+

+    	// Update the Value A/B/C/D/E

+    	temp_sha_h[4] = temp_sha_h[3];

+    	temp_sha_h[3] = temp_sha_h[2];

+    	temp_sha_h[2] = ((temp_sha_h[1] << 30) | (temp_sha_h[1] >> 2));

+    	temp_sha_h[1] = temp_sha_h[0];

+    	temp_sha_h[0] = temp;

+	}

+	//

+	// =========================================================

+

+	// =========================================================

+	//

+	// STEP (e) : H0 = H0 + A; H1 = H1 + B; H2 = H2 + C; H3 = H3 + D; H4 = H4 + E;

+	//

+	psha_h[0] += temp_sha_h[0];

+	psha_h[1] += temp_sha_h[1];

+	psha_h[2] += temp_sha_h[2];

+	psha_h[3] += temp_sha_h[3];

+	psha_h[4] += temp_sha_h[4];

+	//

+	// =========================================================

+}

+

diff --git a/drivers/video/ep932/hdcp.h b/drivers/video/ep932/hdcp.h
new file mode 100644
index 00000000000..b1c67b20ce3
--- /dev/null
+++ b/drivers/video/ep932/hdcp.h
@@ -0,0 +1,41 @@
+#ifndef HDCP_H

+#define HDCP_H

+

+#define HDCP_TIMER_PERIOD 					5		//   

+

+// HDCP Transmiter Link State

+typedef enum {

+	A0_WAIT_FOR_ACTIVE_RX,

+	A1_EXCHANGE_KSVS,

+	A2_COMPUTATIONS,

+	A3_VALIDATE_RECEIVER,

+	A4_AUTHENTICATED,

+	A5_LINK_INTEGRITY_CHECK,

+	A6_TEST_FOR_REPEATER,

+	A8_WAIT_FOR_READY,

+	A9_READ_KSV_LIST

+} hdcp_state_t;

+

+#define HDCP_ERROR_BKSV								0x80

+#define HDCP_ERROR_AKSV								0x40

+#define HDCP_ERROR_R0								0x20

+#define HDCP_ERROR_RI								0x10

+#define HDCP_ERROR_REPEATERRDY							0x08

+#define HDCP_ERROR_REPEATERSHA							0x04

+#define HDCP_ERROR_RSEN								0x02

+#define HDCP_ERROR_REPEATERMAX							0x01

+

+extern hdcp_state_t hdcp_authentication_task(unsigned char receiverrdy);

+extern void hdcp_stop(void);

+extern unsigned char hdcp_get_status(void);

+extern void hdcp_timer(void);

+extern void hdcp_ext_ri_trigger(void);

+

+// Special Functions

+extern void hdcp_assign_rksv_list(unsigned char *prevocationlist, unsigned char listnumber);

+extern void hdcp_fake(unsigned char enable);

+extern void hdcp_extract_bksv_bcaps3(unsigned char *bksv_bcaps3);

+extern void hdcp_extract_fifo(unsigned char *pfifo, unsigned char listnumber);

+extern void hdcp_extract_sha_m0(unsigned char *sha_m0);

+

+#endif // HDCP_H

diff --git a/drivers/video/ep932/i2c_drivers/Makefile b/drivers/video/ep932/i2c_drivers/Makefile
new file mode 100644
index 00000000000..1d0d70f1dc9
--- /dev/null
+++ b/drivers/video/ep932/i2c_drivers/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_JZ4760_HDMI_DISPLAY) 	+= ep932_i2c.o edid_i2c.o hdcp_rx_i2c.o hey_i2c.o
diff --git a/drivers/video/ep932/i2c_drivers/edid_i2c.c b/drivers/video/ep932/i2c_drivers/edid_i2c.c
new file mode 100644
index 00000000000..f5e7766b501
--- /dev/null
+++ b/drivers/video/ep932/i2c_drivers/edid_i2c.c
@@ -0,0 +1,139 @@
+#include <linux/kernel.h>

+#include <linux/i2c.h>

+#include <asm/jzsoc.h>

+

+static struct i2c_client *this_client;

+

+#define EDID_SPEED		100000

+extern void i2c_jz_setclk(struct i2c_client *client,unsigned long i2cclk);

+static int jz_edid_write(unsigned char *txData, int length)

+{

+        int retry;

+        struct i2c_msg msg[] = {

+                {

+                        .addr = this_client->addr,

+                        .flags = 0,

+                        .len = length,

+                        .buf = txData,

+                },

+        };

+

+        for (retry = 0; retry <= 100; retry++) {

+                if(i2c_transfer(this_client->adapter, msg, 1) > 0)

+                        break;

+                else

+                        mdelay(10);

+        }

+        if (retry > 100) {

+                printk(KERN_ERR "%s: retry over 100\n", __func__);

+                return -EIO;

+        }

+

+        return 0;

+}

+

+

+

+static int jz_edid_read(unsigned char *rxData, int length)

+{

+        int retry;

+

+        struct i2c_msg msgs[] = {

+                {

+                        .addr = this_client->addr,

+                        .flags = 0,

+                        .len = 1,

+                        .buf = rxData,

+                },

+                {

+                        .addr = this_client->addr,

+                        .flags = I2C_M_RD,

+                        .len = length,

+                        .buf = rxData,

+                },

+        };

+

+        for (retry = 0; retry <= 100; retry++) {

+                if (i2c_transfer(this_client->adapter, msgs, 2) > 0)

+                        break;

+                else

+                        mdelay(10);

+        }

+        if (retry > 100) {

+                printk(KERN_ERR "%s: retry over 100\n",__func__);

+                return -EIO;

+        }

+

+        return 0;

+}

+

+int jz_i2c_edid_write(unsigned char adress, unsigned char *txData, int length)

+{

+	int i;

+	

+	for (i = length; i >= 1; i--) {

+		txData[i] = txData[i-1];

+	}

+

+	txData[0] = adress;

+	return jz_edid_write(txData, length+1);

+}

+

+int jz_i2c_edid_read(unsigned char adress, unsigned char *txData, int length)

+{

+	txData[0] = adress;

+	return jz_edid_read(txData, length);

+}

+static int

+jz_edid_probe(struct i2c_client *client, const struct i2c_device_id *id)

+{

+	int err;

+

+	if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {

+		err = -ENODEV;

+		return err;

+	}

+	

+	this_client = client;

+	i2c_jz_setclk(client,EDID_SPEED);

+	return 0;

+}

+

+

+static int jz_edid_remove(struct i2c_client *client)

+{

+	return 0;

+}

+static const struct i2c_device_id jz_edid_id[] = {

+        { "jz_edid", 0 },

+        { }     /* Terminating entry */

+};

+MODULE_DEVICE_TABLE(i2c, jz_edid_id);

+

+

+static struct i2c_driver jz_edid_driver = {

+        .probe          = jz_edid_probe,

+        .remove         = jz_edid_remove,

+        .id_table       = jz_edid_id,

+        .driver = {

+                .name   = "jz_edid",

+        },

+};

+static int __init jz_edid_init(void)

+{

+        return i2c_add_driver(&jz_edid_driver);

+}

+

+static void __exit jz_edid_exit(void)

+{

+        i2c_del_driver(&jz_edid_driver);

+        printk(KERN_INFO "JZ_EP932 driver: exit\n");

+}

+

+module_init(jz_edid_init);

+module_exit(jz_edid_exit);

+

+EXPORT_SYMBOL(jz_i2c_edid_read);

+EXPORT_SYMBOL(jz_i2c_edid_write);

+

+MODULE_LICENSE("GPL");

diff --git a/drivers/video/ep932/i2c_drivers/ep932_i2c.c b/drivers/video/ep932/i2c_drivers/ep932_i2c.c
new file mode 100644
index 00000000000..c92bc49815d
--- /dev/null
+++ b/drivers/video/ep932/i2c_drivers/ep932_i2c.c
@@ -0,0 +1,244 @@
+#include <linux/kernel.h>

+#include <linux/module.h>

+#include <linux/fs.h>

+#include <linux/i2c.h>

+#include <linux/miscdevice.h>

+#include <linux/kthread.h>

+

+#include <asm/jzsoc.h>

+

+extern void hdmi_test(void);

+extern void hdmi_start();

+extern void hdmi_stop();

+

+

+struct task_struct *hdmi_kthread;

+static struct i2c_client *this_client;

+

+#define HDMI_INIT		1

+#define HDMI_EXIT		2

+#define HDMI_POWER_ON		3

+#define HDMI_POWER_OFF		4

+

+

+

+#define EP932_RESET_PIN		(32*4 + 11)

+#define EP932_SPEED		100000

+extern void i2c_jz_setclk(struct i2c_client *client,unsigned long i2cclk);

+

+static int jz_ep932_write(unsigned char *txData, int length)

+{

+        int retry;

+        struct i2c_msg msg[] = {

+                {

+                        .addr = this_client->addr,

+                        .flags = 0,

+                        .len = length,

+                        .buf = txData,

+                },

+        };

+

+        for (retry = 0; retry <= 100; retry++) {

+                if(i2c_transfer(this_client->adapter, msg, 1) > 0)

+                        break;

+                else

+                        mdelay(10);

+        }

+        if (retry > 100) {

+                printk(KERN_ERR "%s: retry over 100\n", __func__);

+                return -EIO;

+        }

+

+        return 0;

+}

+

+

+

+static int jz_ep932_read(unsigned char *rxData, int length)

+{

+        int retry;

+

+        struct i2c_msg msgs[] = {

+                {

+                        .addr = this_client->addr,

+                        .flags = I2C_M_NOSTART,

+                        .len = 1,

+                        .buf = rxData,

+                },

+                {

+                        .addr = this_client->addr,

+                        .flags = I2C_M_RD,

+                        .len = length,

+                        .buf = rxData,

+                },

+        };

+

+        for (retry = 0; retry <= 100; retry++) {

+                if (i2c_transfer(this_client->adapter, msgs, 2) > 0)

+                        break;

+                else

+                        mdelay(10);

+        }

+        if (retry > 100) {

+                printk(KERN_ERR "%s: retry over 100\n",__func__);

+                return -EIO;

+        }

+

+        return 0;

+}

+

+int jz_i2c_ep932_write(unsigned char adress, unsigned char *txData, int length)

+{

+	int i;

+	

+	for (i = length; i >= 1; i--) {

+		txData[i] = txData[i-1];

+	}

+

+	txData[0] = adress;

+	return jz_ep932_write(txData, length+1);

+}

+

+int jz_i2c_ep932_read(unsigned char adress, unsigned char *txData, int length)

+{

+	txData[0] = adress;

+	return jz_ep932_read(txData, length);

+}

+

+/************************************************************************/

+

+static int hdmi_thread(void *data)

+{

+	printk("called hdmi_test.\n");

+	hdmi_test();

+

+	return 0;

+}

+

+static int ep932_open(struct inode *inode, struct file *file)

+{

+        return 0;

+}

+

+static int ep932_release(struct inode *inode, struct file *file)

+{

+        return 0;

+}

+

+static int ep932_ioctl(struct inode *inode, struct file *file,

+                         unsigned int cmd, unsigned long arg)

+{

+	void __user *argp = (void __user *)arg;

+	int hdmi_type;

+	switch (cmd) {

+	case HDMI_INIT:

+		hdmi_kthread = kthread_run(hdmi_thread, NULL, "hdmi_run");

+		if (IS_ERR(hdmi_kthread)) {

+			printk(": Failed to create HDMI monitor thread.\n");

+			PTR_ERR(hdmi_kthread);

+		}

+		break;

+	case HDMI_EXIT:

+		if(hdmi_kthread)

+			kthread_stop(hdmi_kthread);

+

+		break;

+	case HDMI_POWER_ON:

+		if (copy_from_user(&hdmi_type, argp, sizeof(int)))

+			return -EFAULT;

+		printk(": HDMI type:%d\n",hdmi_type);

+		hdmi_start(hdmi_type);

+		break;

+	case HDMI_POWER_OFF:

+		printk(": HDMI stop:\n");

+		hdmi_stop();

+	break;

+	}

+	

+	return 0;

+

+}

+

+static struct file_operations ep932_fops = {

+        .owner  = THIS_MODULE,

+        .open   = ep932_open,

+        .ioctl  = ep932_ioctl,

+        .release = ep932_release,

+};

+

+static struct miscdevice ep932_device = {

+        .minor  = MISC_DYNAMIC_MINOR,

+        .name   = "hdmi_ep932",

+        .fops   = &ep932_fops,

+};

+

+

+static int jz_ep932_probe(struct i2c_client *client, const struct i2c_device_id *id)

+{

+	int err;

+	if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {

+		err = -ENODEV;

+		return err;

+	}

+	

+	this_client = client;

+	i2c_jz_setclk(client,EP932_SPEED);

+

+	err = misc_register(&ep932_device);

+        if (err) {

+                dev_err(&client->dev,

+                       "%s: ep932 device register failed\n", __func__);

+		return err;

+        }

+#if 0

+		hdmi_start(6);

+#if 0

+		hdmi_kthread = kthread_run(hdmi_thread, NULL, "hdmi_run");

+		if (IS_ERR(hdmi_kthread)) {

+			printk(": Failed to create HDMI monitor thread.\n");

+			PTR_ERR(hdmi_kthread);

+		}

+#endif

+#endif

+	return 0;

+}

+

+

+static int jz_ep932_remove(struct i2c_client *client)

+{

+	return 0;

+}

+static const struct i2c_device_id jz_ep932_id[] = {

+        { "jz_ep932", 0 },

+        { }     /* Terminating entry */

+};

+MODULE_DEVICE_TABLE(i2c, jz_ep932_id);

+

+

+static struct i2c_driver jz_ep932_driver = {

+        .probe          = jz_ep932_probe,

+        .remove         = jz_ep932_remove,

+        .id_table       = jz_ep932_id,

+        .driver = {

+                .name   = "jz_ep932",

+        },

+};

+static int __init jz_ep932_init(void)

+{

+        return i2c_add_driver(&jz_ep932_driver);

+}

+

+static void __exit jz_ep932_exit(void)

+{

+	kthread_stop(hdmi_kthread);

+        i2c_del_driver(&jz_ep932_driver);

+        printk(KERN_INFO "JZ_EP932 driver: exit\n");

+}

+late_initcall(jz_ep932_init);

+//module_init(jz_ep932_init);

+module_exit(jz_ep932_exit);

+

+EXPORT_SYMBOL(jz_i2c_ep932_read);

+EXPORT_SYMBOL(jz_i2c_ep932_write);

+

+MODULE_LICENSE("GPL");

diff --git a/drivers/video/ep932/i2c_drivers/hdcp_rx_i2c.c b/drivers/video/ep932/i2c_drivers/hdcp_rx_i2c.c
new file mode 100644
index 00000000000..86d295da503
--- /dev/null
+++ b/drivers/video/ep932/i2c_drivers/hdcp_rx_i2c.c
@@ -0,0 +1,136 @@
+#include <linux/kernel.h>

+#include <linux/i2c.h>

+#include <asm/jzsoc.h>

+

+static struct i2c_client *this_client;

+

+static int jz_hdcp_rx_write(unsigned char *txData, int length)

+{

+        int retry;

+        struct i2c_msg msg[] = {

+                {

+                        .addr = this_client->addr,

+                        .flags = 0,

+                        .len = length,

+                        .buf = txData,

+                },

+        };

+

+        for (retry = 0; retry <= 100; retry++) {

+                if(i2c_transfer(this_client->adapter, msg, 1) > 0)

+                        break;

+                else

+                        mdelay(10);

+        }

+        if (retry > 100) {

+                printk(KERN_ERR "%s: retry over 100\n", __func__);

+                return -EIO;

+        }

+

+        return 0;

+}

+

+

+

+static int jz_hdcp_rx_read(unsigned char *rxData, int length)

+{

+        int retry;

+

+        struct i2c_msg msgs[] = {

+                {

+                        .addr = this_client->addr,

+                        .flags = 0,

+                        .len = 1,

+                        .buf = rxData,

+                },

+                {

+                        .addr = this_client->addr,

+                        .flags = I2C_M_RD,

+                        .len = length,

+                        .buf = rxData,

+                },

+        };

+

+        for (retry = 0; retry <= 100; retry++) {

+                if (i2c_transfer(this_client->adapter, msgs, 2) > 0)

+                        break;

+                else

+                        mdelay(10);

+        }

+        if (retry > 100) {

+                printk(KERN_ERR "%s: retry over 100\n",__func__);

+                return -EIO;

+        }

+

+        return 0;

+}

+

+int jz_i2c_hdcp_rx_write(unsigned char adress, unsigned char *txData, int length)

+{

+	int i;

+	

+	for (i = length; i >= 1; i--) {

+		txData[i] = txData[i-1];

+	}

+

+	txData[0] = adress;

+	return jz_hdcp_rx_write(txData, length+1);

+}

+

+int jz_i2c_hdcp_rx_read(unsigned char adress, unsigned char *txData, int length)

+{

+	txData[0] = adress;

+	return jz_hdcp_rx_read(txData, length);

+}

+static int jz_hdcp_rx_probe(struct i2c_client *client, const struct i2c_device_id *id)

+{

+	int err;

+

+	if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {

+		err = -ENODEV;

+		return err;

+	}

+	

+	this_client = client;

+

+	return 0;

+}

+

+

+static int jz_hdcp_rx_remove(struct i2c_client *client)

+{

+	return 0;

+}

+static const struct i2c_device_id jz_hdcp_rx_id[] = {

+        { "jz_hdcp_rx", 0 },

+        { }     /* Terminating entry */

+};

+MODULE_DEVICE_TABLE(i2c, jz_hdcp_rx_id);

+

+

+static struct i2c_driver jz_hdcp_rx_driver = {

+        .probe          = jz_hdcp_rx_probe,

+        .remove         = jz_hdcp_rx_remove,

+        .id_table       = jz_hdcp_rx_id,

+        .driver = {

+                .name   = "jz_hdcp_rx",

+        },

+};

+static int __init jz_hdcp_rx_init(void)

+{

+        return i2c_add_driver(&jz_hdcp_rx_driver);

+}

+

+static void __exit jz_hdcp_rx_exit(void)

+{

+        i2c_del_driver(&jz_hdcp_rx_driver);

+        printk(KERN_INFO "JZ_EP932 driver: exit\n");

+}

+

+module_init(jz_hdcp_rx_init);

+module_exit(jz_hdcp_rx_exit);

+

+EXPORT_SYMBOL(jz_i2c_hdcp_rx_read);

+EXPORT_SYMBOL(jz_i2c_hdcp_rx_write);

+

+MODULE_LICENSE("GPL");

diff --git a/drivers/video/ep932/i2c_drivers/hdmi.h b/drivers/video/ep932/i2c_drivers/hdmi.h
new file mode 100644
index 00000000000..95cc2080bcb
--- /dev/null
+++ b/drivers/video/ep932/i2c_drivers/hdmi.h
@@ -0,0 +1,16 @@
+#ifndef __HDMI_H__
+#define __HDMI_H__
+	
+extern int jz_i2c_ep932_write(unsigned char adress, unsigned char *txData, int length);
+extern int jz_i2c_ep932_read(unsigned char adress, unsigned char *txData, int length);
+
+extern int jz_i2c_edid_write(unsigned char adress, unsigned char *txData, int length);
+extern int jz_i2c_edid_read(unsigned char adress, unsigned char *txData, int length);
+
+extern int jz_i2c_hdcp_rx_write(unsigned char adress, unsigned char *txData, int length);
+extern int jz_i2c_hdcp_rx_read(unsigned char adress, unsigned char *txData, int length);
+
+extern int jz_i2c_hey_write(unsigned char adress, unsigned char *txData, int length);
+extern int jz_i2c_hey_read(unsigned char adress, unsigned char *txData, int length);
+
+#endif
diff --git a/drivers/video/ep932/i2c_drivers/hey_i2c.c b/drivers/video/ep932/i2c_drivers/hey_i2c.c
new file mode 100644
index 00000000000..0f96f447933
--- /dev/null
+++ b/drivers/video/ep932/i2c_drivers/hey_i2c.c
@@ -0,0 +1,136 @@
+#include <linux/kernel.h>

+#include <linux/i2c.h>

+#include <asm/jzsoc.h>

+

+static struct i2c_client *this_client;

+

+static int jz_hey_write(unsigned char *txData, int length)

+{

+        int retry;

+        struct i2c_msg msg[] = {

+                {

+                        .addr = this_client->addr,

+                        .flags = 0,

+                        .len = length,

+                        .buf = txData,

+                },

+        };

+

+        for (retry = 0; retry <= 100; retry++) {

+                if(i2c_transfer(this_client->adapter, msg, 1) > 0)

+                        break;

+                else

+                        mdelay(10);

+        }

+        if (retry > 100) {

+                printk(KERN_ERR "%s: retry over 100\n", __func__);

+                return -EIO;

+        }

+

+        return 0;

+}

+

+

+

+static int jz_hey_read(unsigned char *rxData, int length)

+{

+        int retry;

+

+        struct i2c_msg msgs[] = {

+                {

+                        .addr = this_client->addr,

+                        .flags = 0,

+                        .len = 1,

+                        .buf = rxData,

+                },

+                {

+                        .addr = this_client->addr,

+                        .flags = I2C_M_RD,

+                        .len = length,

+                        .buf = rxData,

+                },

+        };

+

+        for (retry = 0; retry <= 100; retry++) {

+                if (i2c_transfer(this_client->adapter, msgs, 2) > 0)

+                        break;

+                else

+                        mdelay(10);

+        }

+        if (retry > 100) {

+                printk(KERN_ERR "%s: retry over 100\n",__func__);

+                return -EIO;

+        }

+

+        return 0;

+}

+

+int jz_i2c_hey_write(unsigned char adress, unsigned char *txData, int length)

+{

+	int i;

+	

+	for (i = length; i >= 1; i--) {

+		txData[i] = txData[i-1];

+	}

+

+	txData[0] = adress;

+	return jz_hey_write(txData, length+1);

+}

+

+int jz_i2c_hey_read(unsigned char adress, unsigned char *txData, int length)

+{

+	txData[0] = adress;

+	return jz_hey_read(txData, length);

+}

+static int jz_hey_probe(struct i2c_client *client, const struct i2c_device_id *id)

+{

+	int err;

+

+	if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {

+		err = -ENODEV;

+		return err;

+	}

+	

+	this_client = client;

+

+	return 0;

+}

+

+

+static int jz_hey_remove(struct i2c_client *client)

+{

+	return 0;

+}

+static const struct i2c_device_id jz_hey_id[] = {

+        { "jz_hey", 0 },

+        { }     /* Terminating entry */

+};

+MODULE_DEVICE_TABLE(i2c, jz_hey_id);

+

+

+static struct i2c_driver jz_hey_driver = {

+        .probe          = jz_hey_probe,

+        .remove         = jz_hey_remove,

+        .id_table       = jz_hey_id,

+        .driver = {

+                .name   = "jz_hey",

+        },

+};

+static int __init jz_hey_init(void)

+{

+        return i2c_add_driver(&jz_hey_driver);

+}

+

+static void __exit jz_hey_exit(void)

+{

+        i2c_del_driver(&jz_hey_driver);

+        printk(KERN_INFO "JZ_EP932 driver: exit\n");

+}

+

+module_init(jz_hey_init);

+module_exit(jz_hey_exit);

+

+EXPORT_SYMBOL(jz_i2c_hey_read);

+EXPORT_SYMBOL(jz_i2c_hey_write);

+

+MODULE_LICENSE("GPL");

diff --git a/drivers/video/ep932/type.h b/drivers/video/ep932/type.h
new file mode 100644
index 00000000000..5c7366abad8
--- /dev/null
+++ b/drivers/video/ep932/type.h
@@ -0,0 +1,109 @@
+/******************************************************************************\

+

+          (c) Copyright Explore Semiconductor, Inc. Limited 2006

+                           ALL RIGHTS RESERVED 

+

+--------------------------------------------------------------------------------

+

+ Please review the terms of the license agreement before using this file.

+ If you are not an authorized user, please destroy this source code file  

+ and notify Explore Semiconductor Inc. immediately that you inadvertently 

+ received an unauthorized copy.  

+

+--------------------------------------------------------------------------------

+

+  File        :  type.h   

+

+  Description :  Define the C-compiler variable syntax

+                  (modified from Gordon's ICP10 souce code) 

+

+\******************************************************************************/

+

+#ifndef _TYPE_H

+#define _TYPE_H

+

+

+// =============================================================================

+// =============================================================================

+

+//typedef unsigned char BYTE;

+//typedef BYTE *PBYTE;

+//typedef unsigned int WORD;

+//typedef unsigned int *PWORD;

+//typedef unsigned long DWORD;

+//typedef DWORD *PDWORD;

+

+//typedef unsigned long ULONG;

+//typedef unsigned long *PULONG;

+//typedef unsigned short USHORT;

+//typedef USHORT *PUSHORT;

+//typedef unsigned char UCHAR;

+//typedef UCHAR *PUCHAR;

+

+

+// =============================================================================

+// =============================================================================

+

+//typedef void (*FVN)(void);

+

+// =============================================================================

+// =============================================================================

+

+//#define FALSE               (0)

+//#define TRUE                (!FALSE)

+//#define OFF                 (0)

+//#define ON                  (!OFF)

+//#define ARRAYSIZE(ary)      (sizeof(ary)/sizeof(ary[0])) 

+

+// =============================================================================

+// =============================================================================

+

+//for big endian 

+//#define LOBYTE(x)           (BYTE)((x)>>8) 

+//#define HIBYTE(x)           (BYTE)((x) & 0x00FF) 

+//#define MKWORD(hi,lo)       (WORD)(((lo)<<8) | hi)                     

+

+// =============================================================================

+// =============================================================================

+

+#define setb0(x)                (x |= 0x01)

+#define setb1(x)                (x |= 0x02)

+#define setb2(x)                (x |= 0x04)

+#define setb3(x)                (x |= 0x08)

+#define setb4(x)                (x |= 0x10)

+#define setb5(x)                (x |= 0x20)

+#define setb6(x)                (x |= 0x40)

+#define setb7(x)                (x |= 0x80)

+

+#define clrb0(x)                (x &= 0xFE)

+#define clrb1(x)                (x &= 0xFD)

+#define clrb2(x)                (x &= 0xFB)

+#define clrb3(x)                (x &= 0xF7)

+#define clrb4(x)                (x &= 0xEF)

+#define clrb5(x)                (x &= 0xDF)

+#define clrb6(x)                (x &= 0xBF)

+#define clrb7(x)                (x &= 0x7F)

+

+#define getb0(x)                (x & 0x01)

+#define getb1(x)                ((x & 0x02)>>1)

+#define getb2(x)                ((x & 0x04)>>2)

+#define getb3(x)                ((x & 0x08)>>3)

+#define getb4(x)                ((x & 0x10)>>4)

+#define getb5(x)                ((x & 0x20)>>5)

+#define getb6(x)                ((x & 0x40)>>6)

+#define getb7(x)                ((x & 0x80)>>7)

+

+

+// =============================================================================

+// =============================================================================

+

+// math

+#ifndef min

+#define min(a,b) (((a)<(b))? (a):(b))

+#endif

+

+#ifndef max

+#define max(a,b) (((a)>(b))? (a):(b))

+#endif

+

+#endif

diff --git a/drivers/video/jz4750_lcd.c b/drivers/video/jz4750_lcd.c
index c5f06272b5d..41959160b96 100644
--- a/drivers/video/jz4750_lcd.c
+++ b/drivers/video/jz4750_lcd.c
@@ -323,8 +323,17 @@ struct jz4750lcd_info jz4750_info_tve = {
 };
 
 struct jz4750lcd_info *jz4750_lcd_info = &jz4750_lcd_panel; /* default output to lcd panel */
+static struct lcd_cfb_info *jz4750fb_info;
+static struct jz4750_lcd_dma_desc *dma_desc_base;
+static struct jz4750_lcd_dma_desc *dma0_desc_palette, *dma0_desc0, *dma0_desc1, *dma1_desc0, *dma1_desc1;
 
 #if JZ_FB_DEBUG
+static unsigned char *lcd_frame_test;
+static unsigned char *lcd_frame_test1;
+static int lcd_frame_size=0;
+
+static void display_h_color_bar(int w, int h, int bpp) ;
+
 static void print_lcdc_registers(void)	/* debug */
 {
 	/* LCD Controller Resgisters */
@@ -405,12 +414,12 @@ static void print_lcdc_registers(void)	/* debug */
 	if ( 1 ) {
 		unsigned int * pii = (unsigned int *)dma_desc_base;
 		int i, j;
-		for (j=0;j< DMA_DESC_NUM ; j++) {
+		/*for (j=0;j< DMA_DESC_NUM ; j++) {
 			printk("dma_desc%d(0x%08x):\n", j, (unsigned int)pii);
 			for (i =0; i<8; i++ ) {
 				printk("\t\t0x%08x\n", *pii++);
 			}
-		}
+		}*/
 	}
 }
 #else
@@ -428,10 +437,6 @@ struct lcd_cfb_info {
 	int backlight_level;
 };
 
-static struct lcd_cfb_info *jz4750fb_info;
-static struct jz4750_lcd_dma_desc *dma_desc_base;
-static struct jz4750_lcd_dma_desc *dma0_desc_palette, *dma0_desc0, *dma0_desc1, *dma1_desc0, *dma1_desc1;
-
 #define DMA_DESC_NUM 		6
 
 static unsigned char *lcd_palette;
@@ -1172,11 +1177,20 @@ static int jz4750fb_map_smem(struct lcd_cfb_info *cfb)
 			break;
 	lcd_palette = (unsigned char *)__get_free_pages(GFP_KERNEL, 0);
 	lcd_frame0 = (unsigned char *)__get_free_pages(GFP_KERNEL, page_shift);
+#if JZ_FB_DEBUG
+	lcd_frame_test = (unsigned char * )__get_free_pages(GFP_KERNEL,page_shift);
+	lcd_frame_test1 = (unsigned char * )__get_free_pages(GFP_KERNEL,page_shift);
+	lcd_frame_size = PAGE_SIZE<<page_shift;
+#endif
 
 	if ((!lcd_palette) || (!lcd_frame0))
 		return -ENOMEM;
 	memset((void *)lcd_palette, 0, PAGE_SIZE);
 	memset((void *)lcd_frame0, 0, PAGE_SIZE << page_shift);
+#if JZ_FB_DEBUG
+	memset((void *)lcd_frame_test,0,PAGE_SIZE<<page_shift);
+	memset((void *)lcd_frame_test1,0,PAGE_SIZE<<page_shift);
+#endif
 
 	dma_desc_base = (struct jz4750_lcd_dma_desc *)((void*)lcd_palette + ((PALETTE_SIZE+3)/4)*4);
 
@@ -1282,6 +1296,10 @@ static void jz4750fb_unmap_smem(struct lcd_cfb_info *cfb)
 			clear_bit(PG_reserved, &map->flags);
 		}
 		free_pages((int)lcd_frame0, page_shift);
+	#if JZ_FB_DEBUG
+		free_pages((int)lcd_frame_test,page_shift);
+		free_pages((int)lcd_frame_test1,page_shift);
+	#endif
 	}
 }
 
@@ -1903,14 +1921,13 @@ static int jz4750_fb_resume(struct platform_device *pdev)
 	printk("%s(): called.\n", __func__);
 
 	__cpm_start_lcd();
-
-	__gpio_set_pin(GPIO_DISP_OFF_N); 
-	__lcd_special_on();
-	__lcd_set_ena();
-	mdelay(200);
-
-	__lcd_set_backlight_level(cfb->backlight_level);
-
+	ctrl_enable();
+	screen_on();		
+	
+#if JZ_FB_DEBUG
+	display_h_color_bar(jz4750_lcd_info->osd.fg0.w, jz4750_lcd_info->osd.fg0.h, jz4750_lcd_info->osd.fg0.bpp);
+	mdelay(1000);
+#endif
 	return 0;
 }
 
@@ -2040,6 +2057,45 @@ static void display_v_color_bar(int w, int h, int bpp) {
 		}
 	}
 }
+#if 1
+extern void jz_flush_cache_all(void);
+static void display_h_color_bar(int w, int h, int bpp) 
+{
+	int i, j,data = 0;
+	unsigned int *ptr;
+	unsigned int *ptr1;
+	int wpl; //word_per_line
+	ptr = (unsigned int *)lcd_frame_test;
+	ptr1 = (unsigned int *)lcd_frame_test1;
+	
+	
+		
+	while(1)
+	{
+		for(i=0;i<272;i++)
+		for(j=0;j<480;j++)
+		{
+			*(ptr+i*480+j) =0xff0000; 		
+		}
+		//memcpy((void *)lcd_frame0,(void *)lcd_frame_test,lcd_frame_size);mdelay(1000);
+		dma0_desc0->databuf = (unsigned int)virt_to_phys((void *)lcd_frame_test);
+		dma_cache_wback((unsigned int)(dma0_desc0), sizeof(struct jz4750_lcd_dma_desc));
+		mdelay(1000);
+
+		for(i=0;i<272;i++)
+		for(j=0;j<480;j++)
+		{
+			*(ptr1+i*480+j) =0x00ff00; 		
+		}
+		//memcpy((void *)lcd_frame0,(void *)lcd_frame_test,lcd_frame_size);mdelay(1000);
+		dma0_desc0->databuf = (unsigned int)virt_to_phys((void *)lcd_frame_test1);
+		dma_cache_wback((unsigned int)(dma0_desc0), sizeof(struct jz4750_lcd_dma_desc));
+		mdelay(1000);
+		
+	}
+
+}
+#else
 static void display_h_color_bar(int w, int h, int bpp) {
 	int i, data = 0;
 	int *ptr;
@@ -2124,6 +2180,7 @@ static void display_h_color_bar(int w, int h, int bpp) {
 	}
 
 }
+#endif
 #endif	
 
 /* Backlight Control Interface via sysfs 
@@ -2160,7 +2217,7 @@ static int screen_on(void)
 	struct lcd_cfb_info *cfb = jz4750fb_info;
 	
 	__lcd_display_on();
-	
+	mdelay(200);//±ØÐëÑÓʱ£¬·ñÔò»á°×ÆÁ
 	/* Really restore LCD backlight when LCD backlight is turned on. */
 	if (cfb->backlight_level) {
 #ifdef HAVE_LCD_PWM_CONTROL
@@ -2168,8 +2225,9 @@ static int screen_on(void)
 			__lcd_pwm_start();
 			cfb->b_lcd_pwm = 1;
 		}
-#endif		
+#endif	
 		__lcd_set_backlight_level(cfb->backlight_level);
+		
 	}
 
 	cfb->b_lcd_display = 1;
@@ -2405,7 +2463,7 @@ static int __devinit jz4750_fb_probe(struct platform_device *dev)
 #if JZ_FB_DEBUG
 	display_h_color_bar(jz4750_lcd_info->osd.fg0.w, jz4750_lcd_info->osd.fg0.h, jz4750_lcd_info->osd.fg0.bpp);
 
-	print_lcdc_registers();
+	//print_lcdc_registers();
 #endif
 
 	return 0;
diff --git a/drivers/video/jz4760_epd.c b/drivers/video/jz4760_epd.c
deleted file mode 100644
index 8e0f1f8efb0..00000000000
--- a/drivers/video/jz4760_epd.c
+++ /dev/null
@@ -1,3079 +0,0 @@
-/*
- * linux/drivers/video/jz4760_lcd.c -- Ingenic Jz4760 LCD frame buffer device
- *
- * Copyright (C) 2005-2008, Ingenic Semiconductor Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-/*
- * --------------------------------
- * NOTE:
- * This LCD driver support TFT16 TFT32 LCD, not support STN and Special TFT LCD 
- * now.
- * 	It seems not necessory to support STN and Special TFT.
- * 	If it's necessary, update this driver in the future.
- * 	<Wolfgang Wang, Jun 10 2008>
- */
-/*
- * Added Electronic paper support <Cynthia zhao, Jun 2010>
- *
-*/
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/string.h>
-#include <linux/mm.h>
-#include <linux/tty.h>
-#include <linux/slab.h>
-#include <linux/delay.h>
-#include <linux/fb.h>
-#include <linux/init.h>
-#include <linux/dma-mapping.h>
-#include <linux/platform_device.h>
-#include <linux/suspend.h>
-#include <linux/pm.h>
-#include <linux/leds.h>
-
-#include <asm/irq.h>
-#include <asm/pgtable.h>
-#include <asm/system.h>
-#include <asm/uaccess.h>
-#include <asm/processor.h>
-#include <asm/jzsoc.h>
-
-#include "console/fbcon.h"
-
-#include "jz4760_epd.h"
-
-#include "jzepd.c"
-
-#define DRIVER_NAME	"jz-lcd"
-
-#ifdef CONFIG_JZ4760_SLCD_KGM701A3_TFT_SPFD5420A
-#include "jz_kgm_spfd5420a.h"
-#endif
-
-MODULE_DESCRIPTION("Jz4760 LCD Controller driver");
-MODULE_AUTHOR("Wolfgang Wang <lgwang@ingenic.cn>, Lemon Liu <zyliu@ingenic.cn>");
-MODULE_LICENSE("GPL");
-
-#define LCD_DEBUG
-//#undef LCD_DEBUG
-
-#ifdef LCD_DEBUG
-#define dprintk(x...)	printk(x)
-#define print_dbg(f, arg...) printk("dbg::" __FILE__ ",LINE(%d): " f "\n", __LINE__, ## arg)
-#else
-#define dprintk(x...)
-#define print_dbg(f, arg...) do {} while (0)
-#endif
-
-#define print_err(f, arg...) printk(KERN_ERR DRIVER_NAME ": " f "\n", ## arg)
-#define print_warn(f, arg...) printk(KERN_WARNING DRIVER_NAME ": " f "\n", ## arg)
-#define print_info(f, arg...) printk(KERN_INFO DRIVER_NAME ": " f "\n", ## arg)
-
-#define JZ_LCD_ID "jz-lcd"
-#define ANDROID_NUMBER_OF_BUFFERS 2
-
-struct lcd_cfb_info {
-	struct fb_info		fb0;	/* foreground 0 */
-	struct fb_info		fb;	/* foreground 1 */
-	struct display_switch	*dispsw;
-	signed int		currcon;
-	int			func_use_count;
-
-	struct {
-		u16 red, green, blue;
-	} palette[NR_PALETTE];
-#ifdef CONFIG_PM
-	struct pm_dev		*pm;
-#endif
-};
-
-static int lcd_backlight_level = 100;
-static struct lcd_cfb_info *jz4760fb_info;
-static int current_dma0_id, current_dma1_id;
-static struct jz4760_lcd_dma_desc *dma_desc_base;
-static struct jz4760_lcd_dma_desc *dma0_desc_palette, *dma0_desc0, *dma0_desc1, *dma1_desc0, *dma1_desc1;
-
-#define DMA_DESC_NUM 		9
-
-unsigned char *lcd_palette;
-static unsigned char *lcd_frame0;
-static unsigned char *lcd_frame;
-
-#define EPD_MODE_PAL 1
-
-/*because sdram can't support above 16 frames, so we should do sth. By Cynthia 2010*/
-#define NR_DMA1_DESC_EPD 1
-#define NR_DMA_DESC_EPD_PER_GROUP 17 //16 frames + 1 palette
-#define NR_EPD_PAL 12  // 12 paletteswe should surport 12 palette, 16 frame per palette, so we can support 12*16=192frames
-#define NR_DMA_DESC_EPD NR_DMA_DESC_EPD_PER_GROUP*NR_EPD_PAL
-static unsigned int palette_offset = 16*16*4; //(Bytes) per frame is 16 word, totally 16frame per palette
-static struct jz4760_lcd_dma_desc *dma_desc_epd[NR_DMA_DESC_EPD];
-static struct jz4760_lcd_dma_desc *dma0_desc_palette_epd[NR_EPD_PAL];
-
-
-int use_fg1_only = 0;
-int use_fg0_only = 0;
-int use_2layer_Fg = 1;
-
-
-/*Cynthia zhao add end*/
-
-
-/* APP */
-
-static void jz4760fb_deep_set_mode( struct jz4760lcd_info * lcd_info );
-static void print_lcdc_registers(void);
-#ifdef CONFIG_FB_JZ4760_TVE
-static void jz4760lcd_info_switch_to_TVE(int mode);
-static void jz4760lcd_info_switch_to_lcd(void);
-#endif
-
-static int jz4760fb0_foreground_resize(struct jz4760lcd_osd_t *lcd_osd_info);
-static int jz4760fb0_foreground_move(struct jz4760lcd_osd_t *lcd_osd_info);
-
-static int jz4760fb_foreground_resize(struct jz4760lcd_osd_t *lcd_osd_info);
-static int jz4760fb_foreground_move(struct jz4760lcd_osd_t *lcd_osd_info);
-
-
-struct jz4760lcd_info jz4760_lcd_panel = {
-#if defined(CONFIG_JZ4760_LCD_SAMSUNG_LTP400WQF02)
-	.panel = {
-		.cfg = LCD_CFG_LCDPIN_LCD | LCD_CFG_RECOVER | /* Underrun recover */ 
-		LCD_CFG_NEWDES | /* 8words descriptor */
-		LCD_CFG_MODE_GENERIC_TFT | /* General TFT panel */
-		LCD_CFG_MODE_TFT_18BIT | 	/* output 18bpp */
-		LCD_CFG_HSP | 	/* Hsync polarity: active low */
-		LCD_CFG_VSP,	/* Vsync polarity: leading edge is falling edge */
-		.slcd_cfg = 0,
-		.ctrl = LCD_CTRL_OFUM | LCD_CTRL_BST_16,	/* 16words burst, enable out FIFO underrun irq */
-		480, 272, 60, 41, 10, 2, 2, 2, 2,
-      	},
-	.osd = {
-		.osd_cfg = LCD_OSDC_OSDEN, /* Use OSD mode */
-		 .osd_ctrl = 0,		/* disable ipu,  */
-		 .rgb_ctrl = 0,
-		 .bgcolor = 0x000000, /* set background color Black */
-		 .colorkey0 = 0, /* disable colorkey */
-		 .colorkey1 = 0, /* disable colorkey */
-		 .alpha = 0xA0,	/* alpha value */
-		 .ipu_restart = 0x80001000, /* ipu restart */
-		 .fg_change = FG_CHANGE_ALL, /* change all initially */
-		 .fg0 = {32, 0, 0, 480, 272}, /* bpp, x, y, w, h */
-		 .fg1 = {32, 0, 0, 480, 272}, /* bpp, x, y, w, h */
-	 },
-#elif defined(CONFIG_JZ4760_LCD_AUO_A043FL01V2)
-	.panel = {
-		.cfg = LCD_CFG_LCDPIN_LCD | LCD_CFG_RECOVER | /* Underrun recover */ 
-		LCD_CFG_NEWDES | /* 8words descriptor */
-		LCD_CFG_MODE_GENERIC_TFT | /* General TFT panel */
-		LCD_CFG_MODE_TFT_24BIT | 	/* output 18bpp */
-		LCD_CFG_HSP | 	/* Hsync polarity: active low */
-		LCD_CFG_VSP,	/* Vsync polarity: leading edge is falling edge */
-		.slcd_cfg = 0,
-		.ctrl = LCD_CTRL_OFUM | LCD_CTRL_BST_16,	/* 16words burst, enable out FIFO underrun irq */
-		480, 272, 60, 41, 10, 8, 4, 4, 2,
-	},
-	.osd = {
-		.osd_cfg = LCD_OSDC_OSDEN | LCD_OSDC_ALPHAEN,// | /* Use OSD mode */
-		.osd_ctrl = 0,		/* disable ipu,  */
-		.rgb_ctrl = 0,
-		.bgcolor = 0x000000, /* set background color Black */
-		.colorkey0 = 0x80000000, /* disable colorkey */
-//		.colorkey0 = 0, /* disable colorkey */
-		.colorkey1 = 0, /* disable colorkey */
-		.alpha = 0xff,	/* alpha value */
-//		.alpha = 0xA0,	/* alpha value */
-		.ipu_restart = 0x80001000, /* ipu restart */
-		.fg_change = FG_CHANGE_ALL, /* change all initially */
-		.fg0 = {32, 0, 0, 480, 272}, /* bpp, x, y, w, h */
-		.fg1 = {32, 0, 0, 480, 272}, /* bpp, x, y, w, h */
-	},
-#elif defined(CONFIG_JZ4760_LCD_TRULY_TFT_GG1P0319LTSW_W)
-	.panel = {
-		 .cfg = LCD_CFG_LCDPIN_SLCD | /* Underrun recover*/ 
-		 LCD_CFG_NEWDES | /* 8words descriptor */
-		 LCD_CFG_MODE_SLCD, /* TFT Smart LCD panel */
-		 .slcd_cfg = SLCD_CFG_DWIDTH_16BIT | SLCD_CFG_CWIDTH_16BIT | SLCD_CFG_CS_ACTIVE_LOW | SLCD_CFG_RS_CMD_LOW | SLCD_CFG_CLK_ACTIVE_FALLING | SLCD_CFG_TYPE_PARALLEL,
-		 .ctrl = LCD_CTRL_OFUM | LCD_CTRL_BST_16,	/* 16words burst, enable out FIFO underrun irq */
-		 240, 320, 60, 0, 0, 0, 0, 0, 0,
-	 },
-	.osd = {
-		.osd_cfg = LCD_OSDC_OSDEN,/* Use OSD mode */
-		 .osd_ctrl = 0,		/* disable ipu,  */
-		 .rgb_ctrl = 0,
-		 .bgcolor = 0x000000, /* set background color Black */
-		 .colorkey0 = 0, /* disable colorkey */
-		 .colorkey1 = 0, /* disable colorkey */
-		 .alpha = 0xA0,	/* alpha value */
-		 .ipu_restart = 0x80001000, /* ipu restart */
-		 .fg_change = FG_CHANGE_ALL, /* change all initially */
-		 .fg0 = {32, 0, 0, 240, 320}, /* bpp, x, y, w, h */
-		 .fg1 = {32, 0, 0, 240, 320}, /* bpp, x, y, w, h */
-	 },
-
-#elif defined(CONFIG_JZ4760_LCD_FOXCONN_PT035TN01)
-	.panel = {
-		.cfg = LCD_CFG_LCDPIN_LCD | LCD_CFG_RECOVER | /* Underrun recover */ 
-		LCD_CFG_NEWDES | /* 8words descriptor */
-		LCD_CFG_MODE_GENERIC_TFT | /* General TFT panel */
-		LCD_CFG_MODE_TFT_24BIT | 	/* output 24bpp */
-		LCD_CFG_HSP | 	/* Hsync polarity: active low */
-		LCD_CFG_VSP |	/* Vsync polarity: leading edge is falling edge */
-		LCD_CFG_PCP,	/* Pix-CLK polarity: data translations at falling edge */
-		.slcd_cfg = 0,
-		.ctrl = LCD_CTRL_OFUM | LCD_CTRL_BST_16,	/* 16words burst, enable out FIFO underrun irq */
-		320, 240, 80, 1, 1, 10, 50, 10, 13
-	},
-	.osd = {
-		.osd_cfg = LCD_OSDC_OSDEN, /* Use OSD mode */
-		 .osd_ctrl = 0,		/* disable ipu,  */
-		 .rgb_ctrl = 0,
-		 .bgcolor = 0x000000, /* set background color Black */
-		 .colorkey0 = 0, /* disable colorkey */
-		 .colorkey1 = 0, /* disable colorkey */
-		 .alpha = 0xA0,	/* alpha value */
-		 .ipu_restart = 0x80001000, /* ipu restart */
-		 .fg_change = FG_CHANGE_ALL, /* change all initially */
-		 .fg0 = {32, 0, 0, 320, 240}, /* bpp, x, y, w, h */
-		 .fg1 = {32, 0, 0, 320, 240}, /* bpp, x, y, w, h */
-	 },
-#elif defined(CONFIG_JZ4760_LCD_INNOLUX_PT035TN01_SERIAL)
-	.panel = {
-		.cfg = LCD_CFG_LCDPIN_LCD | LCD_CFG_RECOVER | /* Underrun recover */ 
-		LCD_CFG_NEWDES | /* 8words descriptor */
-		LCD_CFG_MODE_SERIAL_TFT | /* Serial TFT panel */
-		LCD_CFG_MODE_TFT_18BIT | 	/* output 18bpp */
-		LCD_CFG_HSP | 	/* Hsync polarity: active low */
-		LCD_CFG_VSP |	/* Vsync polarity: leading edge is falling edge */
-		LCD_CFG_PCP,	/* Pix-CLK polarity: data translations at falling edge */
-		.slcd_cfg = 0,
-		.ctrl = LCD_CTRL_OFUM | LCD_CTRL_BST_16,	/* 16words burst, enable out FIFO underrun irq */
-		320, 240, 60, 1, 1, 10, 50, 10, 13
-	},
-	.osd = {
-		.osd_cfg = LCD_OSDC_OSDEN, /* Use OSD mode */
-		.osd_ctrl = 0,		/* disable ipu,  */
-		 .rgb_ctrl = 0,
-		.bgcolor = 0x000000, /* set background color Black */
-		.colorkey0 = 0, /* disable colorkey */
-		.colorkey1 = 0, /* disable colorkey */
-		.alpha = 0xA0,	/* alpha value */
-		.ipu_restart = 0x80001000, /* ipu restart */
-		.fg_change = FG_CHANGE_ALL, /* change all initially */
-		.fg0 = {32, 0, 0, 320, 240}, /* bpp, x, y, w, h */
-		.fg1 = {32, 0, 0, 320, 240}, /* bpp, x, y, w, h */
-	},
-#elif defined(CONFIG_JZ4760_SLCD_KGM701A3_TFT_SPFD5420A)
-	.panel = {
-		.cfg = LCD_CFG_LCDPIN_SLCD | /* Underrun recover*/ 
-//		 LCD_CFG_DITHER | /* dither */
-		LCD_CFG_NEWDES | /* 8words descriptor */
-		LCD_CFG_MODE_SLCD, /* TFT Smart LCD panel */
-		.slcd_cfg = SLCD_CFG_DWIDTH_18BIT | SLCD_CFG_CWIDTH_18BIT | SLCD_CFG_CS_ACTIVE_LOW | SLCD_CFG_RS_CMD_LOW | SLCD_CFG_CLK_ACTIVE_FALLING | SLCD_CFG_TYPE_PARALLEL,
-		 .ctrl = LCD_CTRL_OFUM | LCD_CTRL_BST_16,	/* 16words burst, enable out FIFO underrun irq */
-		 400, 240, 60, 0, 0, 0, 0, 0, 0,
-	 },
-	.osd = {
-		.osd_cfg = LCD_OSDC_OSDEN, /* Use OSD mode */
-		.osd_ctrl = 0,		/* disable ipu,  */
-		.rgb_ctrl = 0,
-		.bgcolor = 0x000000, /* set background color Black */
-		.colorkey0 = 0, /* disable colorkey */
-		.colorkey1 = 0, /* disable colorkey */
-		.alpha = 0xA0,	/* alpha value */
-		.ipu_restart = 0x80001000, /* ipu restart */
-		.fg_change = FG_CHANGE_ALL, /* change all initially */
-		.fg0 = {32, 0, 0, 400, 240}, /* bpp, x, y, w, h */
-		.fg1 = {32, 0, 0, 400, 240}, /* bpp, x, y, w, h */
-	},
-#elif defined(CONFIG_JZ4760_VGA_DISPLAY)
-	.panel = {
-		.cfg = LCD_CFG_LCDPIN_LCD | LCD_CFG_RECOVER |/* Underrun recover */ 
-		LCD_CFG_NEWDES | /* 8words descriptor */
-		LCD_CFG_MODE_GENERIC_TFT | /* General TFT panel */
-		LCD_CFG_MODE_TFT_24BIT | 	/* output 18bpp */
-		LCD_CFG_HSP | 	/* Hsync polarity: active low */
-		LCD_CFG_VSP,	/* Vsync polarity: leading edge is falling edge */
-		.slcd_cfg = 0,
-		.ctrl = LCD_CTRL_OFUM | LCD_CTRL_BST_16,	/* 16words burst, enable out FIFO underrun irq */
-//		800, 600, 60, 128, 4, 40, 88, 0, 23
-		640, 480, 54, 96, 2, 16, 48, 10, 33
-//		1280, 720, 50, 152, 15, 22, 200, 14, 1
-	},
-	.osd = {
-		 .osd_cfg = LCD_OSDC_OSDEN | /* Use OSD mode */
-//		 LCD_OSDC_ALPHAEN | /* enable alpha */
-//		 LCD_OSDC_F1EN | /* enable Foreground1 */
-		 LCD_OSDC_F0EN,	/* enable Foreground0 */
-		 .osd_ctrl = 0,		/* disable ipu,  */
-		 .rgb_ctrl = 0,
-		 .bgcolor = 0x000000, /* set background color Black */
-		 .colorkey0 = 0, /* disable colorkey */
-		 .colorkey1 = 0, /* disable colorkey */
-		 .alpha = 0xA0,	/* alpha value */
-		 .ipu_restart = 0x80001000, /* ipu restart */
-		 .fg_change = FG_CHANGE_ALL, /* change all initially */
-		 .fg0 = {32, 0, 0, 640, 480}, /* bpp, x, y, w, h */
-		 .fg1 = {32, 0, 0, 640, 480}, /* bpp, x, y, w, h */
-	 },
-#elif defined(CONFIG_JZ4760_EPSON_EPD_DISPLAY)
-	.panel = {
-		.cfg = LCD_CFG_LCDPIN_LCD | LCD_CFG_RECOVER |/* Underrun recover */ 
-		LCD_CFG_NEWDES | /* 8words descriptor */
-		LCD_CFG_MODE_GENERIC_TFT | /* General TFT panel */
-		LCD_CFG_MODE_TFT_24BIT | 	/* output 18bpp */
-		LCD_CFG_HSP | 	/* Hsync polarity: active low */
-		LCD_CFG_VSP,	/* Vsync polarity: leading edge is falling edge */
-		.slcd_cfg = 0,
-		.ctrl = LCD_CTRL_OFUM | LCD_CTRL_BST_32,	/* 16words burst, enable out FIFO underrun irq */
-		800, 600, 60, 128, 4, 40, 88, 0, 23
-
-//		1280, 720, 50, 152, 15, 22, 200, 14, 1
-	},
-	.osd = {
-		 .osd_cfg = LCD_OSDC_OSDEN | /* Use OSD mode */
-//		 LCD_OSDC_ALPHAEN | /* enable alpha */
-#if EPD_MODE_PAL
-		 LCD_OSDC_F1EN | /* enable Foreground1 */
-		 LCD_OSDC_F0EN,	/* enable Foreground0 */
-#else
-		 LCD_OSDC_F1EN,
-#endif
-		 .osd_ctrl = 0,		/* disable ipu,  */
-		 .rgb_ctrl = 0,
-		 .bgcolor = 0x000000, /* set background color Black */
-		 .colorkey0 = 0, /* disable colorkey */
-		 .colorkey1 = 0, /* disable colorkey */
-		 .alpha = 0x0,	/* alpha value */
-		 .ipu_restart = 0x80001000, /* ipu restart */
-		 .fg_change = FG_CHANGE_ALL, /* change all initially */
-#if EPD_MODE_PAL
- 
-		 .fg0 = {4, 0, 0, 800, 600}, /* bpp, x, y, w, h */
-//		 .fg0 = {4, 0, 0, 0, 0}, /* bpp, x, y, w, h */
-		 .fg1 = {4, 0, 0, 800, 600}, /* bpp, x, y, w, h */
-#else
- 
-		 .fg0 = {2, 0, 0, 800, 600}, /* bpp, x, y, w, h */
-//		 .fg0 = {4, 0, 0, 0, 0}, /* bpp, x, y, w, h */
-		 .fg1 = {2, 0, 0, 800, 600}, /* bpp, x, y, w, h */
-#endif
-	 },
-#else
-#error "Select LCD panel first!!!"
-#endif
-};
-
-#ifdef CONFIG_FB_JZ4760_TVE
-struct jz4760lcd_info jz4760_info_tve = {
-	.panel = {
-		.w = TVE_WIDTH_PAL, TVE_HEIGHT_PAL, TVE_FREQ_PAL, 0, 0, 0, 0, 0, 0,
-	},
-	.osd = {
-		.rgb_ctrl = LCD_RGBC_YCC, /* enable RGB => YUV */
-		.fg0 = {32,},	/*  */
-		.fg1 = {32,},
-	},
-};
-#endif
-
-struct jz4760lcd_info *jz4760_lcd_info = &jz4760_lcd_panel; /* default output to lcd panel */
-
-
-
-static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
-{
-        chan &= 0xffff;
-        chan >>= 16 - bf->length;
-        return chan << bf->offset;
-}
-
-#if defined(CONFIG_JZ4760_EPSON_EPD_DISPLAY)
-void print_epd_regs(void)
-{
-	printk("REG_EPD_CTRL1 \t= 0x%08x\n",REG_EPD_CTRL1);
-	printk("REG_EPD_CTRL2 \t= 0x%08x\n",REG_EPD_CTRL2);
-	printk("REG_EPD_CTRL3 \t= 0x%08x\n",REG_EPD_CTRL3);
-	printk("REG_EPD_CTRL4 \t= 0x%08x\n",REG_EPD_CTRL4);
-	printk("REG_EPD_CTRL5 \t= 0x%08x\n",REG_EPD_CTRL5);
-	printk("REG_EPD_CTRL6 \t= 0x%08x\n",REG_EPD_CTRL6);
-	printk("REG_EPD_CTRL7 \t= 0x%08x\n",REG_EPD_CTRL7);
-	printk("REG_EPD_CTRL8 \t= 0x%08x\n",REG_EPD_CTRL8);
-	printk("REG_EPD_CTRL9 \t= 0x%08x\n",REG_EPD_CTRL9);
-	printk("REG_LCD_VAT \t= 0x%08x\n",REG_LCD_VAT);
-	printk("REG_LCD_PS \t= 0x%08x\n",REG_LCD_PS);
-	printk("REG_LCD_CLS \t= 0x%08x\n",REG_LCD_CLS);
-	printk("REG_LCD_VSYNC \t= 0x%08x\n",REG_LCD_VSYNC);
-	printk("REG_LCD_HSYNC \t= 0x%08x\n",REG_LCD_HSYNC);
-	printk("\n");
-	printk("REG_EPD_CTRL1 \t= 0x%08x\n",(unsigned int)&REG_EPD_CTRL1);
-	printk("REG_EPD_CTRL2 \t= 0x%08x\n",(unsigned int)&REG_EPD_CTRL2);
-	printk("REG_EPD_CTRL3 \t= 0x%08x\n",(unsigned int)&REG_EPD_CTRL3);
-	printk("REG_EPD_CTRL4 \t= 0x%08x\n",(unsigned int)&REG_EPD_CTRL4);
-	printk("REG_EPD_CTRL5 \t= 0x%08x\n",(unsigned int)&REG_EPD_CTRL5);
-	printk("REG_EPD_CTRL6 \t= 0x%08x\n",(unsigned int)&REG_EPD_CTRL6);
-	printk("REG_EPD_CTRL7 \t= 0x%08x\n",(unsigned int)&REG_EPD_CTRL7);
-	printk("REG_EPD_CTRL8 \t= 0x%08x\n",(unsigned int)&REG_EPD_CTRL8);
-	printk("REG_EPD_CTRL9 \t= 0x%08x\n",(unsigned int)&REG_EPD_CTRL9);
-	printk("REG_LCD_VAT \t= 0x%08x\n",(unsigned int)&REG_LCD_VAT);
-	printk("REG_LCD_PS \t= 0x%08x\n",(unsigned int)&REG_LCD_PS);
-	printk("REG_LCD_CLS \t= 0x%08x\n",(unsigned int)&REG_LCD_CLS);
-	printk("REG_LCD_VSYNC \t= 0x%08x\n",(unsigned int)&REG_LCD_VSYNC);
-	printk("REG_LCD_HSYNC \t= 0x%08x\n",(unsigned int)&REG_LCD_HSYNC);
-
-	printk("REG_LCD_XYP0 \t= 0x%X\n",REG_LCD_XYP0);
-	printk("REG_LCD_XYP1 \t= 0x%X\n",REG_LCD_XYP1);
-	printk("REG_LCD_SIZE0 \t= 0x%X\n",REG_LCD_SIZE0);
-	printk("REG_LCD_SIZE1 \t= 0x%X\n",REG_LCD_SIZE1);
-	printk("REG_LCD_OSDCTRL \t= 0x%X\n",REG_LCD_OSDCTRL);
-	printk("REG_LCD_OSDC \t= 0x%X\n",REG_LCD_OSDC);
-
-
-	/* LCD Controller Resgisters */
-	printk("REG_LCD_CFG:\t0x%08x\n", REG_LCD_CFG);
-	printk("REG_LCD_CTRL:\t0x%08x\n", REG_LCD_CTRL);
-	printk("REG_LCD_STATE:\t0x%08x\n", REG_LCD_STATE);
-	printk("REG_LCD_OSDC:\t0x%08x\n", REG_LCD_OSDC);
-	printk("REG_LCD_OSDCTRL:\t0x%08x\n", REG_LCD_OSDCTRL);
-	printk("REG_LCD_OSDS:\t0x%08x\n", REG_LCD_OSDS);
-	printk("REG_LCD_BGC:\t0x%08x\n", REG_LCD_BGC);
-	printk("REG_LCD_KEK0:\t0x%08x\n", REG_LCD_KEY0);
-	printk("REG_LCD_KEY1:\t0x%08x\n", REG_LCD_KEY1);
-	printk("REG_LCD_ALPHA:\t0x%08x\n", REG_LCD_ALPHA);
-	printk("REG_LCD_IPUR:\t0x%08x\n", REG_LCD_IPUR);
-	printk("REG_LCD_VAT:\t0x%08x\n", REG_LCD_VAT);
-	printk("REG_LCD_DAH:\t0x%08x\n", REG_LCD_DAH);
-	printk("REG_LCD_DAV:\t0x%08x\n", REG_LCD_DAV);
-	printk("REG_LCD_XYP0:\t0x%08x\n", REG_LCD_XYP0);
-	printk("REG_LCD_XYP1:\t0x%08x\n", REG_LCD_XYP1);
-	printk("REG_LCD_SIZE0:\t0x%08x\n", REG_LCD_SIZE0);
-	printk("REG_LCD_SIZE1:\t0x%08x\n", REG_LCD_SIZE1);
-	printk("REG_LCD_RGBC\t0x%08x\n", REG_LCD_RGBC);
-	printk("REG_LCD_VSYNC:\t0x%08x\n", REG_LCD_VSYNC);
-	printk("REG_LCD_HSYNC:\t0x%08x\n", REG_LCD_HSYNC);
-	printk("REG_LCD_PS:\t0x%08x\n", REG_LCD_PS);
-	printk("REG_LCD_CLS:\t0x%08x\n", REG_LCD_CLS);
-	printk("REG_LCD_SPL:\t0x%08x\n", REG_LCD_SPL);
-	printk("REG_LCD_REV:\t0x%08x\n", REG_LCD_REV);
-	printk("REG_LCD_IID:\t0x%08x\n", REG_LCD_IID);
-	printk("REG_LCD_DA0:\t0x%08x\n", REG_LCD_DA0);
-	printk("REG_LCD_SA0:\t0x%08x\n", REG_LCD_SA0);
-	printk("REG_LCD_FID0:\t0x%08x\n", REG_LCD_FID0);
-	printk("REG_LCD_CMD0:\t0x%08x\n", REG_LCD_CMD0);
-	printk("REG_LCD_OFFS0:\t0x%08x\n", REG_LCD_OFFS0);
-	printk("REG_LCD_PW0:\t0x%08x\n", REG_LCD_PW0);
-	printk("REG_LCD_CNUM0:\t0x%08x\n", REG_LCD_CNUM0);
-	printk("REG_LCD_DESSIZE0:\t0x%08x\n", REG_LCD_DESSIZE0);
-	printk("REG_LCD_DA1:\t0x%08x\n", REG_LCD_DA1);
-	printk("REG_LCD_SA1:\t0x%08x\n", REG_LCD_SA1);
-	printk("REG_LCD_FID1:\t0x%08x\n", REG_LCD_FID1);
-	printk("REG_LCD_CMD1:\t0x%08x\n", REG_LCD_CMD1);
-	printk("REG_LCD_OFFS1:\t0x%08x\n", REG_LCD_OFFS1);
-	printk("REG_LCD_PW1:\t0x%08x\n", REG_LCD_PW1);
-	printk("REG_LCD_CNUM1:\t0x%08x\n", REG_LCD_CNUM1);
-	printk("REG_LCD_DESSIZE1:\t0x%08x\n", REG_LCD_DESSIZE1);
-	printk("==================================\n");
-	printk("REG_LCD_VSYNC:\t%d:%d\n", REG_LCD_VSYNC>>16, REG_LCD_VSYNC&0xfff);
-	printk("REG_LCD_HSYNC:\t%d:%d\n", REG_LCD_HSYNC>>16, REG_LCD_HSYNC&0xfff);
-	printk("REG_LCD_VAT:\t%d:%d\n", REG_LCD_VAT>>16, REG_LCD_VAT&0xfff);
-	printk("REG_LCD_DAH:\t%d:%d\n", REG_LCD_DAH>>16, REG_LCD_DAH&0xfff);
-	printk("REG_LCD_DAV:\t%d:%d\n", REG_LCD_DAV>>16, REG_LCD_DAV&0xfff);
-	printk("==================================\n");
-
-	/* Smart LCD Controller Resgisters */
-	printk("REG_SLCD_CFG:\t0x%08x\n", REG_SLCD_CFG);
-	printk("REG_SLCD_CTRL:\t0x%08x\n", REG_SLCD_CTRL);
-	printk("REG_SLCD_STATE:\t0x%08x\n", REG_SLCD_STATE);
-	printk("==================================\n");
-
-	/* TVE Controller Resgisters */
-	printk("REG_TVE_CTRL:\t0x%08x\n", REG_TVE_CTRL);
-	printk("REG_TVE_FRCFG:\t0x%08x\n", REG_TVE_FRCFG);
-	printk("REG_TVE_SLCFG1:\t0x%08x\n", REG_TVE_SLCFG1);
-	printk("REG_TVE_SLCFG2:\t0x%08x\n", REG_TVE_SLCFG2);
-	printk("REG_TVE_SLCFG3:\t0x%08x\n", REG_TVE_SLCFG3);
-	printk("REG_TVE_LTCFG1:\t0x%08x\n", REG_TVE_LTCFG1);
-	printk("REG_TVE_LTCFG2:\t0x%08x\n", REG_TVE_LTCFG2);
-	printk("REG_TVE_CFREQ:\t0x%08x\n", REG_TVE_CFREQ);
-	printk("REG_TVE_CPHASE:\t0x%08x\n", REG_TVE_CPHASE);
-	printk("REG_TVE_CBCRCFG:\t0x%08x\n", REG_TVE_CBCRCFG);
-	printk("REG_TVE_WSSCR:\t0x%08x\n", REG_TVE_WSSCR);
-	printk("REG_TVE_WSSCFG1:\t0x%08x\n", REG_TVE_WSSCFG1);
-	printk("REG_TVE_WSSCFG2:\t0x%08x\n", REG_TVE_WSSCFG2);
-	printk("REG_TVE_WSSCFG3:\t0x%08x\n", REG_TVE_WSSCFG3);
-
-	printk("==================================\n");
-
-	if ( 0 ) {
-		unsigned int * pii = (unsigned int *)dma_desc_base;
-		int i, j;
-		for (j=0;j< DMA_DESC_NUM ; j++) {
-			printk("dma_desc%d(0x%08x):\n", j, (unsigned int)pii);
-			for (i =0; i<8; i++ ) {
-				printk("\t\t0x%08x\n", *pii++);
-			}
-		}
-	}
-
-
-	if ( 0 ) {
-		unsigned int * pii = (unsigned int *)dma_desc_base;
-		int i, j;
-		for (j=0;j< NR_DMA_DESC_EPD ; j++) {
-			printk("zhihui::dma_desc%d(0x%08x):\n", j, (unsigned int)pii);
-			for (i =0; i<8; i++ ) {
-				printk("\t\t0x%08x\n", *pii++);
-			}
-		}
-	}
-
-
-}
-
-void init_epd_controller(void)
-{
-	
-	REG_EPD_CTRL1 = 0x04ea6600; /*c0*/ //for eink
-//	REG_EPD_CTRL1 = 0x04ea4600; /*c0*/ // for oed 20100607
-//	REG_EPD_CTRL1 = 0x04ea7600; /*c0*/
-	REG_EPD_CTRL2 = 0x0fa20c82; /*c0*/
-	REG_EPD_CTRL3 = 0x00320032; /*c0*/
-	REG_EPD_CTRL4 = 0xff01580e; /*cc*/
-
-	REG_EPD_CTRL4 = (0xff01580e); /*cc*/    //epd dma interrupt enable
-
-// 	REG_EPD_CTRL4 = 0xff01500e; /*cc*/ /* each frame irq enable */
-	REG_EPD_CTRL5 = 0x035a1024; /*d0*/ /* each update irq enable */
-//	REG_EPD_CTRL5 = 0x035a2525; /*d0*/ /* each update irq enable */
-	REG_EPD_CTRL6 = 0x01ad01ad; /*d4*/
-	REG_EPD_CTRL7 = 0x04e40034; /*d8*/
-	REG_EPD_CTRL8 = 0x00010001; /*dc*/
-	REG_EPD_CTRL9 = 0x00010001; /*e0*/
-	REG_LCD_VAT   = 0x04ea026a; /* 0c*/
-//	REG_LCD_PS    = 0x00380358; /*18*/
-//	REG_LCD_CLS   = 0x00080260; /*1c*/
-	REG_LCD_PS    = 0x00380358; /*18*/
-	REG_LCD_CLS   = 0x00080260; /*1c*/
-
-	REG_LCD_VSYNC = 0x00000004; /*04*/
-	REG_LCD_HSYNC = 0x04ea0028; /*08*/
-
-	REG_SLCD_CTRL |= SLCD_CTRL_DMA_MODE;
-
-	__lcd_set_ena();
-
-	print_epd_regs();
-
-	REG_EPD_CTRL5 |= 1<<0 ;//EPD_CTRL5_EPD_EN;
-
-}
-
-#endif
-
-/************************************
- *      Jz475X Framebuffer ops
- ************************************/
-
-static int jz4760fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
-			  u_int transp, struct fb_info *info)
-{
-
-	if (use_fg1_only || use_2layer_Fg){
-
-		struct fb_info *fb = info;
-		if (regno >= NR_PALETTE)
-			return 1;
-		if (fb->var.bits_per_pixel <= 16) {
-			red	>>= 8;
-			green	>>= 8;
-			blue	>>= 8;
-			
-			red	&= 0xff;
-			green	&= 0xff;
-			blue	&= 0xff;
-		}
-		
-		switch (fb->var.bits_per_pixel) {
-		case 15:
-			if (regno < 16)
-				((u32 *)fb->pseudo_palette)[regno] =
-					((red >> 3) << 10) | 
-					((green >> 3) << 5) |
-					(blue >> 3);
-			break;
-		case 16:
-			if (regno < 16) {
-				((u32 *)fb->pseudo_palette)[regno] =
-					((red >> 3) << 11) | 
-					((green >> 2) << 5) |
-					(blue >> 3); 
-			}
-			break;
-		case 30:
-			if (regno < 16)
-				((u32 *)fb->pseudo_palette)[regno] =
-					(red << 20) | 
-					(green << 10) |
-					(blue << 0); 
-		case 17 ... 29:
-		case 31 ... 32:
-			if (regno < 16)
-				((u32 *)fb->pseudo_palette)[regno] =
-					(red << 16) | 
-					(green << 8) |
-					(blue << 0); 
-			
-			break;
-		}
-	
-	}
-	if (use_fg0_only || use_2layer_Fg){
-		struct lcd_cfb_info *cfb = (struct lcd_cfb_info *)info;
-		unsigned short *ptr, ctmp;
-		
-		if (regno >= NR_PALETTE)
-			return 1;
-		
-		cfb->palette[regno].red		= red ;
-		cfb->palette[regno].green	= green;
-		cfb->palette[regno].blue	= blue;
-		if (cfb->fb0.var.bits_per_pixel <= 16) {
-			red	>>= 8;
-			green	>>= 8;
-			blue	>>= 8;
-			
-			red	&= 0xff;
-			green	&= 0xff;
-			blue	&= 0xff;
-		}
-		switch (cfb->fb0.var.bits_per_pixel) {
-		case 1:
-		case 2:
-		case 4:
-		case 8:
-			if (((jz4760_lcd_info->panel.cfg & LCD_CFG_MODE_MASK) == LCD_CFG_MODE_SINGLE_MSTN ) ||
-			    ((jz4760_lcd_info->panel.cfg & LCD_CFG_MODE_MASK) == LCD_CFG_MODE_DUAL_MSTN )) {
-				ctmp = (77L * red + 150L * green + 29L * blue) >> 8;
-				ctmp = ((ctmp >> 3) << 11) | ((ctmp >> 2) << 5) |
-					(ctmp >> 3);
-			} else {
-				/* RGB 565 */
-				if (((red >> 3) == 0) && ((red >> 2) != 0))
-					red = 1 << 3;
-				if (((blue >> 3) == 0) && ((blue >> 2) != 0))
-					blue = 1 << 3;
-				ctmp = ((red >> 3) << 11) 
-					| ((green >> 2) << 5) | (blue >> 3);
-			}
-			
-			ptr = (unsigned short *)lcd_palette;
-			ptr = (unsigned short *)(((u32)ptr)|0xa0000000);
-			ptr[regno] = ctmp;
-			
-			break;
-			
-		case 15:
-			if (regno < 16)
-				((u32 *)cfb->fb0.pseudo_palette)[regno] =
-					((red >> 3) << 10) | 
-					((green >> 3) << 5) |
-					(blue >> 3);
-			break;
-		case 16:
-			if (regno < 16) {
-				((u32 *)cfb->fb0.pseudo_palette)[regno] =
-					((red >> 3) << 11) | 
-					((green >> 2) << 5) |
-					(blue >> 3); 
-			}
-			break;
-		case 17 ... 29:
-		case 31 ... 32:
-			if (regno < 16)
-				((u32 *)cfb->fb0.pseudo_palette)[regno] =
-					(red << 16) | 
-					(green << 8) |
-					(blue << 0); 
-			
-			
-			break;
-		}
-		
-		
-		
-		
-	}
-
-	return 0;
-
-}
-static int jz4760fb_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg)
-{
-	int ret = 0;
-        void __user *argp = (void __user *)arg;
-
-
-	switch (cmd) {
-
-	case GET_EPD_INFO:
-	{
-
-		struct epd_info {
-			void * frame_index_buffer;
-			unsigned long frame_index_buffer_phys;
-			unsigned long frame_index_buffer_size;
-			void * frame_buffer_old;
-			unsigned long frame_buffer_old_phys;
-			unsigned long frame_buffer_old_size;
-			void * frame_buffer_new;
-			unsigned long frame_buffer_new_phys;
-			unsigned long frame_buffer_new_size;
-		}epd;
-		epd.frame_index_buffer = lcd_palette;
-		epd.frame_index_buffer_phys = virt_to_phys(lcd_palette);
-		epd.frame_index_buffer_size = 4096;
-		
-		epd.frame_buffer_old = lcd_frame;
-		epd.frame_buffer_old_phys = virt_to_phys(lcd_frame);
-		
-		epd.frame_buffer_old_size = 800*600/2;
-		epd.frame_buffer_new = lcd_frame0;
-		epd.frame_buffer_new_phys = virt_to_phys(lcd_frame0);
-		
-		epd.frame_buffer_new_size = 800*600/2;
-		copy_to_user(argp, &epd, sizeof(epd));
-		
-		
-		break;
-	}
-	case START_EPD_TRANS:
-	{
-		
-		REG_EPD_CTRL2 |= EPD_CTRL2_PWRON;
-		__lcd_clr_ena();
-		
-		break;
-	}
-	case SET_EPD_MOD:	
-	{
-		set_epd_mod(arg);		
-		break;
-	}
-	
-	case SET_GRAY_LEVEL:
-	{
-		epd_gray_level = *(unsigned long *)arg;
-		break;
-	}
-	case SET_HAND_WRITING:
-	{
-		handwriting_palette();
-		break;
-	}
-	case SET_HAND_WRITING_DMA:
-	{
-		REG_LCD_OSDCTRL &= ~0x7 ; 
-		REG_LCD_OSDCTRL |= 1 << 0 ;
-		REG_LCD_OSDC &= ~(1<<3);
-		REG_LCD_CMD1 = (800*600/2)/8;
-		use_fg1_only=1;
-		use_fg0_only=0;
-		use_2layer_Fg =0;
-		break;
-	}
-	case CANCEL_HANDWRITING_DMA: 
-	{
-		REG_LCD_OSDCTRL &= ~0x7 ; 
-		REG_LCD_OSDCTRL |= 1 << 1 ;
-		REG_LCD_OSDC |= (1<<3);
-		REG_LCD_CMD1 = (800*600/2)/4;
-		use_fg1_only=0;
-		use_2layer_Fg =1;
-		break;
-	}	
-		
-	default:
-		printk("%s, unknown command(0x%x)", __FILE__, cmd);
-		break;
-	}
-	
-	return ret;
-}
-
-
-/* Use mmap /dev/fb can only get a non-cacheable Virtual Address. */
-static int jz4760fb_mmap(struct fb_info *info, struct vm_area_struct *vma)
-{
-	if (use_fg1_only || use_2layer_Fg){
-		struct fb_info *fb = info;
-		unsigned long start;
-		unsigned long off;
-		u32 len;
-		off = vma->vm_pgoff << PAGE_SHIFT;
-		//fb->fb_get_fix(&fix, PROC_CONSOLE(info), info);
-		
-		/* frame buffer memory */
-		start = fb->fix.smem_start;
-		len = PAGE_ALIGN((start & ~PAGE_MASK) + fb->fix.smem_len);
-		start &= PAGE_MASK;
-		
-		if ((vma->vm_end - vma->vm_start + off) > len)
-			return -EINVAL;
-		off += start;
-		
-		vma->vm_pgoff = off >> PAGE_SHIFT;
-		vma->vm_flags |= VM_IO;
-		vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);	/* Uncacheable */
-		
-		
-		pgprot_val(vma->vm_page_prot) &= ~_CACHE_MASK;
-		pgprot_val(vma->vm_page_prot) |= _CACHE_UNCACHED;		/* Uncacheable */
-		
-		if (io_remap_pfn_range(vma, vma->vm_start, off >> PAGE_SHIFT,
-				       vma->vm_end - vma->vm_start,
-				       vma->vm_page_prot)) {
-			return -EAGAIN;
-		}
-	}
-	if (use_fg1_only || use_2layer_Fg){
-		struct lcd_cfb_info *cfb = (struct lcd_cfb_info *)info;
-		unsigned long start;
-		unsigned long off;
-		u32 len;
-		
-		off = vma->vm_pgoff << PAGE_SHIFT;
-		//fb->fb_get_fix(&fix, PROC_CONSOLE(info), info);
-		
-		/* frame buffer memory */
-		start = cfb->fb0.fix.smem_start;
-		len = PAGE_ALIGN((start & ~PAGE_MASK) + cfb->fb0.fix.smem_len);
-		start &= PAGE_MASK;
-		
-		if ((vma->vm_end - vma->vm_start + off) > len)
-			return -EINVAL;
-		off += start;
-		
-		vma->vm_pgoff = off >> PAGE_SHIFT;
-		vma->vm_flags |= VM_IO;
-		vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);	/* Uncacheable */
-		
-		
-		pgprot_val(vma->vm_page_prot) &= ~_CACHE_MASK;
-		pgprot_val(vma->vm_page_prot) |= _CACHE_UNCACHED;		/* Uncacheable */
-		
-		if (io_remap_pfn_range(vma, vma->vm_start, off >> PAGE_SHIFT,
-				       vma->vm_end - vma->vm_start,
-				       vma->vm_page_prot)) {
-			return -EAGAIN;
-		}
-	}
-	return 0;
-}
-
-
-/* checks var and eventually tweaks it to something supported,
- * DO NOT MODIFY PAR */
-static int jz4760fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
-{
-
-	if((var->rotate & 1) != (info->var.rotate & 1)) {
-		if((var->xres != info->var.yres) ||
-		   (var->yres != info->var.xres) ||
-		   (var->xres_virtual != info->var.yres) ||
-		   (var->yres_virtual > 
-		    info->var.xres * ANDROID_NUMBER_OF_BUFFERS) ||
-		   (var->yres_virtual < info->var.xres )) {
-			return -EINVAL;
-		}
-	}
-	else {
-		if((var->xres != info->var.xres) ||
-		   (var->yres != info->var.yres) ||
-		   (var->xres_virtual != info->var.xres) ||
-		   (var->yres_virtual > 
-		    info->var.yres * ANDROID_NUMBER_OF_BUFFERS) ||
-		   (var->yres_virtual < info->var.yres )) {
-			return -EINVAL;
-		}
-	}
-	if((var->xoffset != info->var.xoffset) ||
-	   (var->bits_per_pixel != info->var.bits_per_pixel)) {// ||
-//	   (var->grayscale != info->var.grayscale)) {
-		return -EINVAL;
-	}
-	return 0;
-}
-
-
-/* 
- * set the video mode according to info->var
- */
-static int jz4760fb_set_par(struct fb_info *info)
-{
-	dprintk("jz4760fb_set_par, not implemented\n");
-	return 0;
-}
-
-
-/*
- * (Un)Blank the display.
- * Fix me: should we use VESA value?
- */
-static int jz4760fb_blank(int blank_mode, struct fb_info *info)
-{
-	printk("jz4760 fb_blank %d %p", blank_mode, info);
-	switch (blank_mode) {
-	case FB_BLANK_UNBLANK:
-		//case FB_BLANK_NORMAL:
-			/* Turn on panel */
-		__lcd_set_ena();
-		__lcd_display_on();
-		break;
-
-	case FB_BLANK_NORMAL:
-	case FB_BLANK_VSYNC_SUSPEND:
-	case FB_BLANK_HSYNC_SUSPEND:
-	case FB_BLANK_POWERDOWN:
-	/* Turn off panel */
-		break;
-	default:
-		break;
-
-	}
-	return 0;
-}
-
-/* 
- * pan display
- */
-static int jz4760fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
-{
-	struct fb_info *fb = info;
-	int dy;
-	if (!var || !fb) {
-		return -EINVAL;
-	}
-
-	if (var->xoffset - fb->var.xoffset) {
-		/* No support for X panning for now! */
-		return -EINVAL;
-	}
-	/* TODO: Wait for current frame to finished */
-	dy = var->yoffset;// - fb->var.yoffset;
-	if(use_fg1_only){
-		if (dy) {
-			dma1_desc0->databuf = (unsigned int)virt_to_phys((void *)lcd_frame + (fb->fix.line_length * dy));
-			dma_cache_wback((unsigned int)(dma1_desc0), sizeof(struct jz4760_lcd_dma_desc));
-			
-		}
-		else {
-			dma1_desc0->databuf = (unsigned int)virt_to_phys((void *)lcd_frame);
-			dma_cache_wback((unsigned int)(dma1_desc0), sizeof(struct jz4760_lcd_dma_desc));
-		}
-	}
-	else{ 
-		if (dy) {
-			dma0_desc0->databuf = (unsigned int)virt_to_phys((void *)lcd_frame0 + (fb->fix.line_length * dy));
-			dma_cache_wback((unsigned int)(dma0_desc0), sizeof(struct jz4760_lcd_dma_desc));
-			
-		}
-		else {
-			dma0_desc0->databuf = (unsigned int)virt_to_phys((void *)lcd_frame0);
-			dma_cache_wback((unsigned int)(dma0_desc0), sizeof(struct jz4760_lcd_dma_desc));
-		}
-	}
-	return 0;
-}
-
-
-static struct fb_ops jz4760fb_ops = {
-	.owner			= THIS_MODULE,
-	.fb_setcolreg		= jz4760fb_setcolreg,
-	.fb_check_var 		= jz4760fb_check_var,
-	.fb_set_par 		= jz4760fb_set_par,
-	.fb_blank		= jz4760fb_blank,
-	.fb_pan_display		= jz4760fb_pan_display,
-	.fb_fillrect		= cfb_fillrect,
-	.fb_copyarea		= cfb_copyarea,
-	.fb_imageblit		= cfb_imageblit,
-	.fb_mmap		= jz4760fb_mmap,
-	.fb_ioctl		= jz4760fb_ioctl,
-};
-
-static int jz4760fb_set_var(struct fb_var_screeninfo *var, int con,
-			struct fb_info *info)
-{
-
-	struct fb_info *fb = info;
-	struct jz4760lcd_info *lcd_info = jz4760_lcd_info;
-	int chgvar = 0;
-
-	if (con == 0) {
-		var->height	            = lcd_info->osd.fg0.h;	/* tve mode */
-		var->width	            = lcd_info->osd.fg0.w;
-		var->bits_per_pixel	    = lcd_info->osd.fg0.bpp;
-	}
-	else {
-		var->height	            = lcd_info->osd.fg1.h;
-		var->width	            = lcd_info->osd.fg1.w;
-		var->bits_per_pixel	    = lcd_info->osd.fg1.bpp;
-	}
-
-	var->vmode                  = FB_VMODE_NONINTERLACED;
-//	var->vmode                  = FB_VMODE_DOUBLE
-	var->activate               = fb->var.activate;
-	var->xres                   = var->width;
-	var->yres                   = var->height;
-	var->xres_virtual           = var->width;
-	var->yres_virtual           = var->height * ANDROID_NUMBER_OF_BUFFERS;
-	var->xoffset                = 0;
-	var->yoffset                = 0;
-	var->pixclock               = KHZ2PICOS(jz_clocks.pixclk/1000);
-
-	var->left_margin            = lcd_info->panel.elw;
-	var->right_margin           = lcd_info->panel.blw;
-	var->upper_margin           = lcd_info->panel.efw;
-	var->lower_margin           = lcd_info->panel.bfw;
-	var->hsync_len              = lcd_info->panel.hsw;
-	var->vsync_len              = lcd_info->panel.vsw;
-	var->sync                   = 0;
-	var->activate               = FB_ACTIVATE_NOW;
-
-
-	/*
-	 * CONUPDATE and SMOOTH_XPAN are equal.  However,
-	 * SMOOTH_XPAN is only used internally by fbcon.
-	 */
-	if (var->vmode & FB_VMODE_CONUPDATE) {
-		var->vmode |= FB_VMODE_YWRAP;
-		var->xoffset = fb->var.xoffset;
-		var->yoffset = fb->var.yoffset;
-	}
-
-	if (var->activate & FB_ACTIVATE_TEST)
-		return 0;
-
-	if ((var->activate & FB_ACTIVATE_MASK) != FB_ACTIVATE_NOW)
-		return -EINVAL;
-
-	if (fb->var.xres != var->xres)
-		chgvar = 1;
-	if (fb->var.yres != var->yres)
-		chgvar = 1;
-	if (fb->var.xres_virtual != var->xres_virtual)
-		chgvar = 1;
-	if (fb->var.yres_virtual != var->yres_virtual)
-		chgvar = 1;
-	if (fb->var.bits_per_pixel != var->bits_per_pixel)
-		chgvar = 1;
-
-	//display = fb_display + con;
-
-	var->red.msb_right	= 0;
-	var->green.msb_right	= 0;
-	var->blue.msb_right	= 0;
-
-	switch(var->bits_per_pixel){
-	case 1:	/* Mono */
-		fb->fix.visual	= FB_VISUAL_MONO01;
-		fb->fix.line_length	= (var->xres * var->bits_per_pixel) / 8;
-		break;
-	case 2:	/* Mono */
-		var->red.offset		= 0;
-		var->red.length		= 2;
-		var->green.offset	= 0;
-		var->green.length	= 2;
-		var->blue.offset	= 0;
-		var->blue.length	= 2;
-
-		fb->fix.visual	= FB_VISUAL_PSEUDOCOLOR;
-		fb->fix.line_length	= (var->xres * var->bits_per_pixel) / 8;
-		break;
-	case 4:	/* PSEUDOCOLOUR*/
-		var->red.offset		= 0;
-		var->red.length		= 4;
-		var->green.offset	= 0;
-		var->green.length	= 4;
-		var->blue.offset	= 0;
-		var->blue.length	= 4;
-
-		fb->fix.visual	= FB_VISUAL_PSEUDOCOLOR;
-		fb->fix.line_length	= var->xres / 2;
-		break;
-	case 8:	/* PSEUDOCOLOUR, 256 */
-		var->red.offset		= 0;
-		var->red.length		= 8;
-		var->green.offset	= 0;
-		var->green.length	= 8;
-		var->blue.offset	= 0;
-		var->blue.length	= 8;
-
-		fb->fix.visual	= FB_VISUAL_PSEUDOCOLOR;
-		fb->fix.line_length	= var->xres ;
-		break;
-	case 15: /* DIRECTCOLOUR, 32k */
-		var->bits_per_pixel	= 15;
-		var->red.offset		= 10;
-		var->red.length		= 5;
-		var->green.offset	= 5;
-		var->green.length	= 5;
-		var->blue.offset	= 0;
-		var->blue.length	= 5;
-
-		fb->fix.visual	= FB_VISUAL_DIRECTCOLOR;
-		fb->fix.line_length	= var->xres_virtual * 2;
-		break;
-	case 16: /* DIRECTCOLOUR, 64k */
-		var->bits_per_pixel	= 16;
-		var->red.offset		= 11;
-		var->red.length		= 5;
-		var->green.offset	= 5;
-		var->green.length	= 6;
-		var->blue.offset	= 0;
-		var->blue.length	= 5;
-
-		fb->fix.visual	= FB_VISUAL_TRUECOLOR;
-		fb->fix.line_length	= var->xres_virtual * 2;
-		break;
-	case 30:
-		/* DIRECTCOLOUR, 256 */
-		var->bits_per_pixel	= 32;
-
-		var->red.offset		= 20;
-		var->red.length		= 10;
-		var->green.offset	= 10;
-		var->green.length	= 10;
-		var->blue.offset	= 0;
-		var->blue.length	= 10;
-		var->transp.offset  	= 30;
-		var->transp.length 	= 2;
-
-		fb->fix.visual	= FB_VISUAL_TRUECOLOR;
-		fb->fix.line_length	= var->xres_virtual * 4;
-		break;
-	case 17 ... 29:
-	case 31 ... 32:
-		/* DIRECTCOLOUR, 256 */
-		var->bits_per_pixel	= 32;
-
-		var->red.offset		= 16;
-		var->red.length		= 8;
-		var->green.offset	= 8;
-		var->green.length	= 8;
-		var->blue.offset	= 0;
-		var->blue.length	= 8;
-		var->transp.offset  	= 24;
-		var->transp.length 	= 8;
-
-		fb->fix.visual	= FB_VISUAL_TRUECOLOR;
-		fb->fix.line_length	= var->xres_virtual * 4;
-		break;
-
-	default: /* in theory this should never happen */
-		printk(KERN_WARNING "%s: don't support for %dbpp\n",
-		       fb->fix.id, var->bits_per_pixel);
-		break;
-	}
-
-	fb->var = *var;
-	fb->var.activate &= ~FB_ACTIVATE_ALL;
-
-	/*
-	 * Update the old var.  The fbcon drivers still use this.
-	 * Once they are using cfb->fb.var, this can be dropped.
-	 *					--rmk
-	 */
-	//display->var = cfb->fb.var;
-	/*
-	 * If we are setting all the virtual consoles, also set the
-	 * defaults used to create new consoles.
-	 */
-	fb_set_cmap(&fb->cmap, fb);
-	return 0;
-}
-
-static struct lcd_cfb_info * jz4760fb_alloc_fb_info(void)
-{
- 	struct lcd_cfb_info *cfb;
-	cfb = kmalloc(sizeof(struct lcd_cfb_info) + sizeof(u32) * 16, GFP_KERNEL);
-
-	if (!cfb)
-		return NULL;
-
-	jz4760fb_info = cfb;
-
-	memset(cfb, 0, sizeof(struct lcd_cfb_info) );
-
-	cfb->currcon		= -1;
-
-	if (use_fg1_only || use_2layer_Fg){
-	/* Foreground 1 -- fb */
-		strcpy(cfb->fb.fix.id, "jzlcd-fg1");
-		cfb->fb.flags		= FBINFO_FLAG_DEFAULT;
-		cfb->fb.fix.type	= FB_TYPE_PACKED_PIXELS;	
-		cfb->fb.fix.type_aux	= 0;
-		cfb->fb.fix.xpanstep	= 1;
-		cfb->fb.fix.ypanstep	= 1;
-		cfb->fb.fix.ywrapstep	= 0;
-		cfb->fb.fix.accel	= FB_ACCEL_NONE;
-		
-		cfb->fb.var.nonstd	= 0;
-		cfb->fb.var.activate	= FB_ACTIVATE_NOW;
-		cfb->fb.var.height	= -1;
-		cfb->fb.var.width	= -1;
-		cfb->fb.var.accel_flags	= FB_ACCELF_TEXT;
-		
-		cfb->fb.fbops		= &jz4760fb_ops;
-		cfb->fb.flags		= FBINFO_FLAG_DEFAULT;
-		
-		cfb->fb.pseudo_palette	= (void *)(cfb + 1);
-		
-		switch (jz4760_lcd_info->osd.fg1.bpp) {
-		case 1:
-			fb_alloc_cmap(&cfb->fb.cmap, 4, 0);
-			break;
-		case 2:
-			fb_alloc_cmap(&cfb->fb.cmap, 8, 0);
-			break;
-		case 4:
-			fb_alloc_cmap(&cfb->fb.cmap, 32, 0);
-			break;
-		case 8:
-			
-		default:
-			fb_alloc_cmap(&cfb->fb.cmap, 256, 0);
-			break;
-		}
-	}
-	
-	if (use_fg0_only || use_2layer_Fg){
-		/* Foreground 0 -- fb0 */
-		strcpy(cfb->fb0.fix.id, "jzlcd-fg0");
-		cfb->fb0.fix.type	= FB_TYPE_PACKED_PIXELS;	
-		cfb->fb0.fix.type_aux	= 0;
-		cfb->fb0.fix.xpanstep	= 1;
-		cfb->fb0.fix.ypanstep	= 1;
-		cfb->fb0.fix.ywrapstep	= 0;
-		cfb->fb0.fix.accel	= FB_ACCEL_NONE;
-		
-		cfb->fb0.var.nonstd	= 0;
-		cfb->fb0.var.activate	= FB_ACTIVATE_NOW;
-		cfb->fb0.var.height	= -1;
-		cfb->fb0.var.width	= -1;
-		cfb->fb0.var.accel_flags	= FB_ACCELF_TEXT;
-		
-		cfb->fb0.fbops		= &jz4760fb_ops;
-		cfb->fb0.flags		= FBINFO_FLAG_DEFAULT;
-		
-		cfb->fb0.pseudo_palette	= (void *)(cfb + 1);
-		
-		switch (jz4760_lcd_info->osd.fg0.bpp) {
-		case 1:
-			fb_alloc_cmap(&cfb->fb0.cmap, 4, 0);
-			break;
-		case 2:
-			fb_alloc_cmap(&cfb->fb0.cmap, 8, 0);
-			break;
-		case 4:
-			fb_alloc_cmap(&cfb->fb0.cmap, 32, 0);
-			break;
-		case 8:
-			
-		default:
-			fb_alloc_cmap(&cfb->fb0.cmap, 256, 0);
-			break;
-		}
-	}
-	dprintk("fb_alloc_cmap, fb.cmap.len:%d, fb0.cmap.len:%d....\n", cfb->fb.cmap.len, cfb->fb0.cmap.len);
-	return cfb;
-}
-static void fill_fb_newbuff(unsigned char *fb)
-{
-	int i,j;
-	unsigned char *c = (unsigned char *)fb;
-	unsigned char dat = 0;
-#if EPD_MODE_PAL
-	memset(c,0xff,800*600/4);
-	return;
-#endif 	
-	for(i = 0;i < 600;i++)
-		for(j = 0; j < 400;j++)
-		{
-				
-			*c = (dat & 0xf) | (((dat + 1) & 0xf) << 4);
-			c++;
-			dat += 2;
-				
-		}
-      
-
-}
-static void fill_fb_oldbuff(unsigned char *fb)
-{
-	int i,j,count = 1;
-	unsigned char *csave = (unsigned char *)fb;
-	unsigned char *c = csave;
-	unsigned char dat = 0;
-#if EPD_MODE_PAL
-	memset(c,0xff,800*600/4);
-	return;
-#endif
-	for(i = 0;i < 600;i++)
-		for(j = 0; j < 400;j++)
-		{
-			
-			*c = (dat & 0xf) | ((dat & 0xf) << 4); 
-			if((count & 0x7) == 0)
-				dat++;
-			count++;
-			c++;
-		}
-	
-}
-static void check_fb_new_old_buf(unsigned char *newfb,unsigned char *oldfb)
-{
-	unsigned char *new = newfb; 
-	unsigned char newc,oldc;
-	unsigned char *c = (unsigned char *)oldfb;
-	int i;
-	for(i = 0;i < 100;i++)
-	{
-				
-		newc = *new++; 
-		oldc = ((*c++ & 0xf) << 4);
-		if(((i+1) % 16) == 0)
-			c++;
-		//	printk("dat = 0x%X 0x%X\n",(oldc | (newc & 0xf)),(oldc | ((newc >> 4) & 0xf))); 
-	}
-
-}
-/*
- * Map screen memory
- */
-static int jz4760fb_map_smem(struct lcd_cfb_info *cfb)
-{
-	unsigned long page;
-	unsigned int page_shift, needroom = 0, needroom1=0, bpp, w, h;
-	unsigned char *fb_palette, *fb_frame;
-	
-	/* caculate the mem size of Foreground 0 */
-	if (use_fg0_only || use_2layer_Fg)
-	{
-		bpp = jz4760_lcd_info->osd.fg0.bpp;
-		if (bpp == 18 || bpp == 24)
-			bpp = 32;
-		if (bpp == 15)
-			bpp = 16;
-#ifndef CONFIG_FB_JZ4760_TVE
-		w = jz4760_lcd_info->osd.fg0.w;
-		h = jz4760_lcd_info->osd.fg0.h;
-#else
-		w = (jz4760_lcd_info->osd.fg0.w > TVE_WIDTH_PAL) ? jz4760_lcd_info->osd.fg0.w : TVE_WIDTH_PAL;
-		h = (jz4760_lcd_info->osd.fg0.h > TVE_HEIGHT_PAL) ? jz4760_lcd_info->osd.fg0.h : TVE_HEIGHT_PAL;
-#endif
-		
-		needroom1 = needroom = ((w * bpp + 7) >> 3) * h * ANDROID_NUMBER_OF_BUFFERS;
-	}
-	
-	/* caculate the mem size of Foreground 1 */
-	if (use_fg1_only || use_2layer_Fg){
-		bpp = jz4760_lcd_info->osd.fg1.bpp;
-		if (bpp == 18 || bpp == 24)
-			bpp = 32;
-		if (bpp == 15)
-			bpp = 16;
-#ifndef CONFIG_FB_JZ4760_TVE
-		w = jz4760_lcd_info->osd.fg1.w;
-		h = jz4760_lcd_info->osd.fg1.h;
-#else	/* CONFIG_FB_JZ4760_TVE */
-		w = (jz4760_lcd_info->osd.fg1.w > TVE_WIDTH_PAL) ? jz4760_lcd_info->osd.fg1.w : TVE_WIDTH_PAL;
-		h = (jz4760_lcd_info->osd.fg1.h > TVE_HEIGHT_PAL) ? jz4760_lcd_info->osd.fg1.h : TVE_HEIGHT_PAL;
-#endif
-		needroom += ((w * bpp + 7) >> 3) * h;
-
-	}
-/* end of alloc Foreground 1 mem */
-		needroom += PAGE_SIZE; // for
-	/* Alloc memory */
-		for (page_shift = 0; page_shift < 12; page_shift++)
-			if ((PAGE_SIZE << page_shift) >= needroom)
-				break;
-//	fb_palette = (unsigned char *)__get_free_pages(GFP_KERNEL, 0);
-		fb_palette = (unsigned char *)__get_free_pages(GFP_KERNEL, 1); // for init palette which need big room
-		
-		fb_frame = (unsigned char *)__get_free_pages(GFP_KERNEL, page_shift);
-		if ((!fb_palette) || (!fb_frame))
-			return -ENOMEM;
-		memset((void *)fb_palette, 0, PAGE_SIZE);
-		memset((void *)fb_frame, 0, PAGE_SIZE << page_shift);
-		
-//	memset((void *)fb_frame, 0xff, PAGE_SIZE << page_shift);
-		
-		lcd_palette = fb_palette;
-//	dma_desc_base = (struct jz4760_lcd_dma_desc *)__get_free_pages(GFP_KERNEL, 0);
-		dma_desc_base = (struct jz4760_lcd_dma_desc *)__get_free_pages(GFP_KERNEL, 1); 
-		
-		/*
-		 * Set page reserved so that mmap will work. This is necessary
-		 * since we'll be remapping normal memory.
-	 */
-		page = (unsigned long)lcd_palette;
-		SetPageReserved(virt_to_page((void*)page));
-		
-		page = (unsigned long)dma_desc_base;
-		SetPageReserved(virt_to_page((void*)page));
-
-		for (page = (unsigned long)fb_frame;
-		     page < PAGE_ALIGN((unsigned long)fb_frame + (PAGE_SIZE<<page_shift));
-		     page += PAGE_SIZE) {
-			SetPageReserved(virt_to_page((void*)page));
-		}
-
-		if (use_fg1_only || use_2layer_Fg){
-			
-			lcd_frame = (unsigned char *)(((unsigned int)fb_frame + needroom1 + PAGE_MASK) & PAGE_MASK);
-			cfb->fb.fix.smem_start = virt_to_phys((void *)lcd_frame);
-			cfb->fb.fix.smem_len = needroom - needroom1; /* page_shift/2 ??? */
-			cfb->fb.screen_base =
-				(unsigned char *)(((unsigned int)lcd_frame&0x1fffffff) | 0xa0000000);
-			if (!cfb->fb.screen_base) {
-				printk("jz4760fb, %s: unable to map screen memory\n", cfb->fb.fix.id);
-				return -ENOMEM;
-			}
-#if defined(CONFIG_JZ4760_EPSON_EPD_DISPLAY)
-			
-			memset((void *)lcd_frame, 0xff, cfb->fb.fix.smem_len);
-			
-			printk("%s %d set lcd frame 0xff\n",__FUNCTION__,__LINE__);
-#endif
-		}
-		
-		if (use_fg0_only || use_2layer_Fg){
-			lcd_frame0 = fb_frame;
-			cfb->fb0.fix.smem_start = virt_to_phys((void *)lcd_frame0);
-			cfb->fb0.fix.smem_len = needroom1; /* page_shift/2 ??? */
-			
-			cfb->fb0.screen_base =
-				(unsigned char *)(((unsigned int)lcd_frame0&0x1fffffff) | 0xa0000000);
-			if (!cfb->fb0.screen_base) {
-				printk("jz4760fb0, %s: unable to map screen memory\n", cfb->fb0.fix.id);
-				return -ENOMEM;
-			}
-#if defined(CONFIG_JZ4760_EPSON_EPD_DISPLAY)
-			
-			memset((void *)lcd_frame0, 0xff, cfb->fb0.fix.smem_len);
-			{
-				unsigned char * newfb = (unsigned char *)lcd_frame0;
-				unsigned char * oldfb = (unsigned char *)lcd_frame;
-				fill_fb_newbuff(newfb);
-				fill_fb_oldbuff(oldfb);
-				check_fb_new_old_buf(newfb,oldfb);
-			}
-			dma_cache_wback_inv((unsigned int)lcd_frame0,800*600/2);
-			dma_cache_wback_inv((unsigned int)lcd_frame,800*600/2);
-			
-#endif
-		}
-		
-		return 0;
-}
-
-static void jz4760fb_free_fb_info(struct lcd_cfb_info *cfb)
-{
-	if (cfb) {
-		fb_alloc_cmap(&cfb->fb.cmap, 0, 0);
-		kfree(cfb);
-	}
-}
-
-static void jz4760fb_unmap_smem(struct lcd_cfb_info *cfb)
-{
-	struct page * map = NULL;
-	unsigned char *tmp;
-	unsigned int page_shift, needroom, bpp, w, h;
-	bpp = jz4760_lcd_info->osd.fg0.bpp;
-	if ( bpp == 18 || bpp == 24)
-		bpp = 32;
-	if ( bpp == 15 )
-		bpp = 16;
-	w = jz4760_lcd_info->osd.fg0.w;
-	h = jz4760_lcd_info->osd.fg0.h;
-	needroom = ((w * bpp + 7) >> 3) * h;
-	if (use_2layer_Fg){
-		bpp = jz4760_lcd_info->osd.fg1.bpp;
-		if ( bpp == 18 || bpp == 24)
-			bpp = 32;
-		if ( bpp == 15 )
-			bpp = 16;
-		w = jz4760_lcd_info->osd.fg1.w;
-		h = jz4760_lcd_info->osd.fg1.h;
-		needroom += ((w * bpp + 7) >> 3) * h;
-	}
-
-	for (page_shift = 0; page_shift < 12; page_shift++)
-		if ((PAGE_SIZE << page_shift) >= needroom)
-			break;
-
-	if (cfb && cfb->fb.screen_base) {
-		iounmap(cfb->fb.screen_base);
-		cfb->fb.screen_base = NULL;
-		release_mem_region(cfb->fb.fix.smem_start,
-				   cfb->fb.fix.smem_len);
-	}
-
-	if (lcd_palette) {
-		map = virt_to_page(lcd_palette);
-		clear_bit(PG_reserved, &map->flags);
-		free_pages((int)lcd_palette, 0);
-	}
-
-	if (lcd_frame0) {
-		for (tmp=(unsigned char *)lcd_frame0; 
-		     tmp < lcd_frame0 + (PAGE_SIZE << page_shift); 
-		     tmp += PAGE_SIZE) {
-			map = virt_to_page(tmp);
-			clear_bit(PG_reserved, &map->flags);
-		}
-		free_pages((int)lcd_frame0, page_shift);
-	}
-}
-
-/************************************
- *      Jz475X Chipset OPS
- ************************************/
-
-/* 
- * switch to tve mode from lcd mode
- * mode:
- * 	PANEL_MODE_TVE_PAL: switch to TVE_PAL mode
- * 	PANEL_MODE_TVE_NTSC: switch to TVE_NTSC mode
- */
-static void print_lcdc_registers(void)	/* debug */
-{
-#ifdef  DEBUG
-	/* LCD Controller Resgisters */
-	printk("REG_LCD_CFG:\t0x%08x\n", REG_LCD_CFG);
-	printk("REG_LCD_CTRL:\t0x%08x\n", REG_LCD_CTRL);
-	printk("REG_LCD_STATE:\t0x%08x\n", REG_LCD_STATE);
-	printk("REG_LCD_OSDC:\t0x%08x\n", REG_LCD_OSDC);
-	printk("REG_LCD_OSDCTRL:\t0x%08x\n", REG_LCD_OSDCTRL);
-	printk("REG_LCD_OSDS:\t0x%08x\n", REG_LCD_OSDS);
-	printk("REG_LCD_BGC:\t0x%08x\n", REG_LCD_BGC);
-	printk("REG_LCD_KEK0:\t0x%08x\n", REG_LCD_KEY0);
-	printk("REG_LCD_KEY1:\t0x%08x\n", REG_LCD_KEY1);
-	printk("REG_LCD_ALPHA:\t0x%08x\n", REG_LCD_ALPHA);
-	printk("REG_LCD_IPUR:\t0x%08x\n", REG_LCD_IPUR);
-	printk("REG_LCD_VAT:\t0x%08x\n", REG_LCD_VAT);
-	printk("REG_LCD_DAH:\t0x%08x\n", REG_LCD_DAH);
-	printk("REG_LCD_DAV:\t0x%08x\n", REG_LCD_DAV);
-	printk("REG_LCD_XYP0:\t0x%08x\n", REG_LCD_XYP0);
-	printk("REG_LCD_XYP1:\t0x%08x\n", REG_LCD_XYP1);
-	printk("REG_LCD_SIZE0:\t0x%08x\n", REG_LCD_SIZE0);
-	printk("REG_LCD_SIZE1:\t0x%08x\n", REG_LCD_SIZE1);
-	printk("REG_LCD_RGBC\t0x%08x\n", REG_LCD_RGBC);
-	printk("REG_LCD_VSYNC:\t0x%08x\n", REG_LCD_VSYNC);
-	printk("REG_LCD_HSYNC:\t0x%08x\n", REG_LCD_HSYNC);
-	printk("REG_LCD_PS:\t0x%08x\n", REG_LCD_PS);
-	printk("REG_LCD_CLS:\t0x%08x\n", REG_LCD_CLS);
-	printk("REG_LCD_SPL:\t0x%08x\n", REG_LCD_SPL);
-	printk("REG_LCD_REV:\t0x%08x\n", REG_LCD_REV);
-	printk("REG_LCD_IID:\t0x%08x\n", REG_LCD_IID);
-	printk("REG_LCD_DA0:\t0x%08x\n", REG_LCD_DA0);
-	printk("REG_LCD_SA0:\t0x%08x\n", REG_LCD_SA0);
-	printk("REG_LCD_FID0:\t0x%08x\n", REG_LCD_FID0);
-	printk("REG_LCD_CMD0:\t0x%08x\n", REG_LCD_CMD0);
-	printk("REG_LCD_OFFS0:\t0x%08x\n", REG_LCD_OFFS0);
-	printk("REG_LCD_PW0:\t0x%08x\n", REG_LCD_PW0);
-	printk("REG_LCD_CNUM0:\t0x%08x\n", REG_LCD_CNUM0);
-	printk("REG_LCD_DESSIZE0:\t0x%08x\n", REG_LCD_DESSIZE0);
-	printk("REG_LCD_DA1:\t0x%08x\n", REG_LCD_DA1);
-	printk("REG_LCD_SA1:\t0x%08x\n", REG_LCD_SA1);
-	printk("REG_LCD_FID1:\t0x%08x\n", REG_LCD_FID1);
-	printk("REG_LCD_CMD1:\t0x%08x\n", REG_LCD_CMD1);
-	printk("REG_LCD_OFFS1:\t0x%08x\n", REG_LCD_OFFS1);
-	printk("REG_LCD_PW1:\t0x%08x\n", REG_LCD_PW1);
-	printk("REG_LCD_CNUM1:\t0x%08x\n", REG_LCD_CNUM1);
-	printk("REG_LCD_DESSIZE1:\t0x%08x\n", REG_LCD_DESSIZE1);
-	printk("==================================\n");
-	printk("REG_LCD_VSYNC:\t%d:%d\n", REG_LCD_VSYNC>>16, REG_LCD_VSYNC&0xfff);
-	printk("REG_LCD_HSYNC:\t%d:%d\n", REG_LCD_HSYNC>>16, REG_LCD_HSYNC&0xfff);
-	printk("REG_LCD_VAT:\t%d:%d\n", REG_LCD_VAT>>16, REG_LCD_VAT&0xfff);
-	printk("REG_LCD_DAH:\t%d:%d\n", REG_LCD_DAH>>16, REG_LCD_DAH&0xfff);
-	printk("REG_LCD_DAV:\t%d:%d\n", REG_LCD_DAV>>16, REG_LCD_DAV&0xfff);
-	printk("==================================\n");
-
-	/* Smart LCD Controller Resgisters */
-	printk("REG_SLCD_CFG:\t0x%08x\n", REG_SLCD_CFG);
-	printk("REG_SLCD_CTRL:\t0x%08x\n", REG_SLCD_CTRL);
-	printk("REG_SLCD_STATE:\t0x%08x\n", REG_SLCD_STATE);
-	printk("==================================\n");
-
-	/* TVE Controller Resgisters */
-	printk("REG_TVE_CTRL:\t0x%08x\n", REG_TVE_CTRL);
-	printk("REG_TVE_FRCFG:\t0x%08x\n", REG_TVE_FRCFG);
-	printk("REG_TVE_SLCFG1:\t0x%08x\n", REG_TVE_SLCFG1);
-	printk("REG_TVE_SLCFG2:\t0x%08x\n", REG_TVE_SLCFG2);
-	printk("REG_TVE_SLCFG3:\t0x%08x\n", REG_TVE_SLCFG3);
-	printk("REG_TVE_LTCFG1:\t0x%08x\n", REG_TVE_LTCFG1);
-	printk("REG_TVE_LTCFG2:\t0x%08x\n", REG_TVE_LTCFG2);
-	printk("REG_TVE_CFREQ:\t0x%08x\n", REG_TVE_CFREQ);
-	printk("REG_TVE_CPHASE:\t0x%08x\n", REG_TVE_CPHASE);
-	printk("REG_TVE_CBCRCFG:\t0x%08x\n", REG_TVE_CBCRCFG);
-	printk("REG_TVE_WSSCR:\t0x%08x\n", REG_TVE_WSSCR);
-	printk("REG_TVE_WSSCFG1:\t0x%08x\n", REG_TVE_WSSCFG1);
-	printk("REG_TVE_WSSCFG2:\t0x%08x\n", REG_TVE_WSSCFG2);
-	printk("REG_TVE_WSSCFG3:\t0x%08x\n", REG_TVE_WSSCFG3);
-
-	printk("==================================\n");
-
-	if ( 1 ) {
-		unsigned int * pii = (unsigned int *)dma_desc_base;
-		int i, j;
-		//for (j=0;j< DMA_DESC_NUM ; j++) {
-		for (j=0;j< NR_DMA_DESC_EPD ; j++) {
-			printk("dma_desc%d(0x%08x):\n", j, (unsigned int)pii);
-			for (i =0; i<8; i++ ) {
-				printk("\t\t0x%08x\n", *pii++);
-			}
-		}
-	}
-
-
-
-#endif
-}
-
-#ifdef CONFIG_FB_JZ4760_TVE
-static void jz4760lcd_info_switch_to_TVE(int mode)
-{
-	struct jz4760lcd_info *info;
-	struct jz4760lcd_osd_t *osd_lcd;
-	struct jz4760lcd_panel_t *panel_lcd;
-	int x, y, w, h;
-
-	info = &jz4760_info_tve;
-
-	/* Set to tve mode */
-	info->panel.cfg	= jz4760_lcd_panel.panel.cfg;
-	info->panel.cfg |= LCD_CFG_TVEN | LCD_CFG_MODE_INTER_CCIR656; /* Interlace CCIR656 mode */
-	info->panel.ctrl = jz4760_lcd_panel.panel.ctrl;
-	info->osd.rgb_ctrl = LCD_RGBC_YCC; /* enable RGB => YUV */
-
-	/* Copy current to keep the old style */
-	osd_lcd = &jz4760_lcd_panel.osd;
-	panel_lcd = &jz4760_lcd_panel.panel;
-
-	switch ( mode ) {
-	case PANEL_MODE_TVE_PAL:
-		info->panel.cfg |= LCD_CFG_TVEPEH; /* TVE PAL enable extra halfline signal */
-		info->panel.w = TVE_WIDTH_PAL;
-		info->panel.h = TVE_HEIGHT_PAL;
-		info->panel.fclk = TVE_FREQ_PAL;
-
-		/* set Foreground 0 */
-		w = osd_lcd->fg0.w / panel_lcd->w * TVE_WIDTH_PAL;
-		h = osd_lcd->fg0.h / panel_lcd->h * TVE_HEIGHT_PAL;
-		x = osd_lcd->fg0.x / panel_lcd->w * TVE_WIDTH_PAL;
-		y = osd_lcd->fg0.y / panel_lcd->h * TVE_HEIGHT_PAL;
-		info->osd.fg0.bpp = osd_lcd->fg0.bpp;
-		info->osd.fg0.x = x;
-		info->osd.fg0.y = y;
-		info->osd.fg0.w = w;
-		info->osd.fg0.h = h;
-
-		/* set Foreground 1 */
-		w = osd_lcd->fg1.w / panel_lcd->w * TVE_WIDTH_PAL;
-		h = osd_lcd->fg1.h / panel_lcd->h * TVE_HEIGHT_PAL;
-		x = osd_lcd->fg1.x / panel_lcd->w * TVE_WIDTH_PAL;
-		y = osd_lcd->fg1.y / panel_lcd->h * TVE_HEIGHT_PAL;
-		info->osd.fg1.bpp = 32;	/* use RGB888 in TVE mode*/
-		info->osd.fg1.x = x;
-		info->osd.fg1.y = y;
-		info->osd.fg1.w = w;
-		info->osd.fg1.h = h;
-		break;
-
-	case PANEL_MODE_TVE_NTSC:
-		info->panel.cfg &= ~LCD_CFG_TVEPEH; /* TVE NTSC disable extra halfline signal */
-		info->panel.w = TVE_WIDTH_NTSC;
-		info->panel.h = TVE_HEIGHT_NTSC;
-		info->panel.fclk = TVE_FREQ_NTSC;
-		w = osd_lcd->fg0.w / panel_lcd->w * TVE_WIDTH_PAL;
-		h = osd_lcd->fg0.h / panel_lcd->h * TVE_HEIGHT_NTSC;
-		x = osd_lcd->fg0.x / panel_lcd->w * TVE_WIDTH_NTSC;
-		y = osd_lcd->fg0.y / panel_lcd->h * TVE_HEIGHT_NTSC;
-		info->osd.fg0.bpp = osd_lcd->fg0.bpp;
-		info->osd.fg0.x = x;
-		info->osd.fg0.y = y;
-		info->osd.fg0.w = w;
-		info->osd.fg0.h = h;
-
-		w = osd_lcd->fg1.w / panel_lcd->w * TVE_WIDTH_PAL;
-		h = osd_lcd->fg1.h / panel_lcd->h * TVE_HEIGHT_NTSC;
-		x = osd_lcd->fg1.x / panel_lcd->w * TVE_WIDTH_NTSC;
-		y = osd_lcd->fg1.y / panel_lcd->h * TVE_HEIGHT_NTSC;
-		info->osd.fg1.bpp = 32;	/* use RGB888 int TVE mode */
-		info->osd.fg1.x = x;
-		info->osd.fg1.y = y;
-		info->osd.fg1.w = w;
-		info->osd.fg1.h = h;
-		break;
-	default:
-		printk("%s, %s: Unknown tve mode\n", __FILE__, __FUNCTION__);
-	}
-	jz4760_lcd_info = &jz4760_info_tve;
-}
-
-/* 
- * switch to lcd mode from TVE mode
- */
-
-static void jz4760lcd_info_switch_to_lcd(void)
-{
-	struct jz4760lcd_info *info;
-	struct jz4760lcd_osd_t *osd_lcd;
-	struct jz4760lcd_panel_t *panel_lcd;
-	int x, y, w, h;
-
-	info = &jz4760_lcd_panel;
-
-	/* set to tve mode */
-	info->panel.cfg	= jz4760_info_tve.panel.cfg;
-	info->panel.cfg &= ~(LCD_CFG_TVEN | LCD_CFG_MODE_INTER_CCIR656); /* Interlace CCIR656 mode */
-	info->panel.ctrl = jz4760_info_tve.panel.ctrl;
-	info->osd.rgb_ctrl &= ~LCD_RGBC_YCC; /* enable YUV => RGB*/
-
-	/*  */
-	osd_lcd = &jz4760_info_tve.osd;
-	panel_lcd = &jz4760_info_tve.panel;
-
-	/* set Foreground 0 */
-	w = osd_lcd->fg0.w / panel_lcd->w * info->panel.w;
-	h = osd_lcd->fg0.h / panel_lcd->h * info->panel.h;
-	x = osd_lcd->fg0.x / panel_lcd->w * info->panel.w;
-	y = osd_lcd->fg0.y / panel_lcd->h * info->panel.h;
-	info->osd.fg0.x = x;
-	info->osd.fg0.y = y;
-	info->osd.fg0.w = w;
-	info->osd.fg0.h = h;
-
-	/* set Foreground 1 */
-	w = osd_lcd->fg1.w / panel_lcd->w * info->panel.w;
-	h = osd_lcd->fg1.h / panel_lcd->h * info->panel.h;
-	x = osd_lcd->fg1.x / panel_lcd->w * info->panel.w;
-	y = osd_lcd->fg1.y / panel_lcd->h * info->panel.h;
-	info->osd.fg1.x = x;
-	info->osd.fg1.y = y;
-	info->osd.fg1.w = w;
-	info->osd.fg1.h = h;
-
-	jz4760_lcd_info = &jz4760_lcd_panel;
-}
-#endif
-/*for epd: we use 12 palettes, with 16 per palette, tatally 192 frames . BY Cynthia zhzhao 20100602*/
-
-static void jz4760fb_epd_descriptor_init( struct jz4760lcd_info * lcd_info )
-{
-	unsigned int pal_size;
-	int fg0_line_size, fg0_frm_size, fg1_line_size, fg1_frm_size;
-	int size0, size1;
-	int i;
-	unsigned int palette_id ;//which palette
-//	pal_size = palette_offset;
-	pal_size = 1024;
-	/* DMA Descriptor. */
-	for (i = 0; i < NR_DMA_DESC_EPD + NR_DMA1_DESC_EPD; i++)
-		dma_desc_epd[i] = dma_desc_base+i;
-
-	/* Foreground 0, caculate size */
-	if ( lcd_info->osd.fg0.x >= lcd_info->panel.w )
-		lcd_info->osd.fg0.x = lcd_info->panel.w - 1;
-	if ( lcd_info->osd.fg0.y >= lcd_info->panel.h )
-		lcd_info->osd.fg0.y = lcd_info->panel.h - 1;
-	if ( lcd_info->osd.fg0.x + lcd_info->osd.fg0.w > lcd_info->panel.w )
-		lcd_info->osd.fg0.w = lcd_info->panel.w - lcd_info->osd.fg0.x;
-	if ( lcd_info->osd.fg0.y + lcd_info->osd.fg0.h > lcd_info->panel.h ) 
-		lcd_info->osd.fg0.h = lcd_info->panel.h - lcd_info->osd.fg0.y;
-
-	size0 = lcd_info->osd.fg0.h << 16 | lcd_info->osd.fg0.w;
-	fg0_line_size = (lcd_info->osd.fg0.w * (lcd_info->osd.fg0.bpp) / 8);
-	fg0_line_size = ((fg0_line_size + 3) >> 2) << 2; /* word aligned */
-	fg0_frm_size = fg0_line_size * lcd_info->osd.fg0.h;
-	
-	dma0_desc_palette = dma_desc_epd[0];
-
-	/*The first Palette Descriptor */
-	palette_id=0;
-	dma0_desc_palette_epd[palette_id]= dma_desc_epd[0];
-	dma0_desc_palette_epd[palette_id]->next_desc 	= (unsigned int)virt_to_phys(dma_desc_epd[palette_id+1]);
-	dma0_desc_palette_epd[palette_id]->databuf 	= (unsigned int)virt_to_phys((void *)(lcd_palette + palette_offset*palette_id));
-	dma0_desc_palette_epd[palette_id]->frame_id 	= (unsigned int)0xaaaaaaaa;
-	dma0_desc_palette_epd[palette_id]->cmd 		= LCD_CMD_PAL | pal_size; /* Palette Descriptor */
-	dma0_desc_palette_epd[palette_id]->offsize	= 0x00000000; /* Palette Descriptor */
-
-//	printk("dma0_desc_palette_epd[%d]->databuf addr(%p) desc(%p) nex_Desc (%p) frame_id (0x%08x) cmd (0x%08x) \n",palette_id,(void*)dma0_desc_palette_epd[palette_id]->databuf,(void *)dma0_desc_palette_epd[palette_id],(void *)dma0_desc_palette_epd[palette_id]->next_desc,dma0_desc_palette_epd[palette_id]->frame_id ,dma0_desc_palette_epd[palette_id]->cmd);
-
-
-
-       /* next */
-	for(i=1;i<NR_DMA_DESC_EPD_PER_GROUP;i++){
-
-		dma0_desc0 = dma_desc_epd[i];
-		if (i != (NR_DMA_DESC_EPD_PER_GROUP*(palette_id+1) - 1))
-			dma0_desc0->next_desc = (unsigned int)virt_to_phys(dma0_desc0+1);
-		else{
-			dma0_desc_palette_epd[palette_id+1] = dma0_desc0+1;
-			dma0_desc0->next_desc = (unsigned int)virt_to_phys(dma0_desc_palette_epd[palette_id+1]);
-		}
-                /* frame phys addr */
-		dma0_desc0->databuf = virt_to_phys((void *)(lcd_frame0));
-		/* frame id */
-		dma0_desc0->frame_id = (unsigned int)0x0000da00; /* DMA0'0 */
-		/* others */
-		dma0_desc0->cmd = fg0_frm_size/4;
-		dma0_desc0->offsize =0;
-		dma0_desc0->page_width = 0;
-		dma0_desc0->desc_size = size0;
-
-//		printk("dma_desc_epd[%d](0x%08x)  databuf(0x%08x) nex_Desc(0x%08x) frame_id(0x%08x) cmd(0x%08x) \n",i,dma_desc_epd[i],dma0_desc0->databuf,dma0_desc0->next_desc,dma0_desc0->frame_id ,dma0_desc0->cmd);
-
-	}
-
-
-	/*The second Palette Descriptor */
-	palette_id=1;
-
-	dma0_desc_palette_epd[palette_id]->next_desc 	= (unsigned int)virt_to_phys(dma_desc_epd[NR_DMA_DESC_EPD_PER_GROUP*palette_id+1]);
-	dma0_desc_palette_epd[palette_id]->databuf 	= (unsigned int)virt_to_phys((void *)(lcd_palette + palette_offset*palette_id));
-	dma0_desc_palette_epd[palette_id]->frame_id 	= (unsigned int)0xaaaaaaaa;
-	dma0_desc_palette_epd[palette_id]->cmd 		= LCD_CMD_PAL | pal_size; /* Palette Descriptor */
-	dma0_desc_palette_epd[palette_id]->offsize	= 0x00000000; /* Palette Descriptor */
-
-	//printk("dma0_desc_palette_epd[%d]->databuf addr(%p) nex_Desc (%p) frame_id (0x%08x) cmd (0x%08x) \n",palette_id,(void*)dma0_desc_palette_epd[palette_id]->databuf,(void *)dma0_desc_palette_epd[palette_id]->next_desc,dma0_desc_palette_epd[palette_id]->frame_id ,dma0_desc_palette_epd[palette_id]->cmd);
-
-
-
-       /* next */
-	for(i=(NR_DMA_DESC_EPD_PER_GROUP*palette_id+1);i<(NR_DMA_DESC_EPD_PER_GROUP*(palette_id+1));i++){
-
-		dma0_desc0 = dma_desc_epd[i];
-		if (i != (NR_DMA_DESC_EPD_PER_GROUP*(palette_id+1) - 1))
-			dma0_desc0->next_desc = (unsigned int)virt_to_phys(dma0_desc0+1);
-		else{
-			dma0_desc_palette_epd[palette_id+1] = dma0_desc0+1;/* frame phys addr */
-			dma0_desc0->next_desc = (unsigned int)virt_to_phys(dma0_desc_palette_epd[palette_id+1]);
-		}
-		dma0_desc0->databuf = virt_to_phys((void *)lcd_frame0);
-		/* frame id */
-		dma0_desc0->frame_id = (unsigned int)0x0000da00; /* DMA0'0 */
-		/* others */
-		dma0_desc0->cmd = fg0_frm_size/4;
-		dma0_desc0->offsize =0;
-		dma0_desc0->page_width = 0;
-		dma0_desc0->desc_size = size0;
-
-		//printk("dma_desc_epd[%d](0x%08x)  databuf(0x%08x) nex_Desc(0x%08x) frame_id(0x%08x) cmd(0x%08x) \n",i,dma_desc_epd[i],dma0_desc0->databuf,dma0_desc0->next_desc,dma0_desc0->frame_id ,dma0_desc0->cmd);
-
-	}
- 
-	
-	/* The third Palette Descriptor */
-	palette_id=2;
-
-	dma0_desc_palette_epd[palette_id]->next_desc 	= (unsigned int)virt_to_phys(dma_desc_epd[NR_DMA_DESC_EPD_PER_GROUP*palette_id+1]);
-	dma0_desc_palette_epd[palette_id]->databuf 	= (unsigned int)virt_to_phys((void *)(lcd_palette + palette_offset*palette_id));
-	dma0_desc_palette_epd[palette_id]->frame_id 	= (unsigned int)0xaaaaaaaa;
-	dma0_desc_palette_epd[palette_id]->cmd 		= LCD_CMD_PAL | pal_size; /* Palette Descriptor */
-	dma0_desc_palette_epd[palette_id]->offsize	= 0x00000000; /* Palette Descriptor */
-
-	//printk("dma0_desc_palette_epd[%d]->databuf addr(%p) nex_Desc (%p) frame_id (0x%08x) cmd (0x%08x) \n",palette_id,(void*)dma0_desc_palette_epd[palette_id]->databuf,(void *)dma0_desc_palette_epd[palette_id]->next_desc,dma0_desc_palette_epd[palette_id]->frame_id ,dma0_desc_palette_epd[palette_id]->cmd);
-
-
-
-       /* next */
-	for(i=(NR_DMA_DESC_EPD_PER_GROUP*palette_id+1);i<(NR_DMA_DESC_EPD_PER_GROUP*(palette_id+1));i++){
-
-		dma0_desc0 = dma_desc_epd[i];
-		if (i != (NR_DMA_DESC_EPD_PER_GROUP*(palette_id+1) - 1))
-			dma0_desc0->next_desc = (unsigned int)virt_to_phys(dma0_desc0+1);
-		else{
-			dma0_desc_palette_epd[palette_id+1] = dma0_desc0+1;/* frame phys addr */
-			dma0_desc0->next_desc = (unsigned int)virt_to_phys(dma0_desc_palette_epd[palette_id+1]);
-		}
-		dma0_desc0->databuf = virt_to_phys((void *)lcd_frame0);
-		/* frame id */
-		dma0_desc0->frame_id = (unsigned int)0x0000da00; /* DMA0'0 */
-		/* others */
-		dma0_desc0->cmd = fg0_frm_size/4;
-		dma0_desc0->offsize =0;
-		dma0_desc0->page_width = 0;
-		dma0_desc0->desc_size = size0;
-		//printk("dma_desc_epd[%d](0x%08x)  databuf(0x%08x) nex_Desc(0x%08x) frame_id(0x%08x) cmd(0x%08x) \n",i,dma_desc_epd[i],dma0_desc0->databuf,dma0_desc0->next_desc,dma0_desc0->frame_id ,dma0_desc0->cmd);
-	
-
-	}
-	
-	/* The forth Palette Descriptor */
-	palette_id=3;
-
-	dma0_desc_palette_epd[palette_id]->next_desc 	= (unsigned int)virt_to_phys(dma_desc_epd[NR_DMA_DESC_EPD_PER_GROUP*palette_id+1]);
-	dma0_desc_palette_epd[palette_id]->databuf 	= (unsigned int)virt_to_phys((void *)(lcd_palette + palette_offset*palette_id));
-	dma0_desc_palette_epd[palette_id]->frame_id 	= (unsigned int)0xaaaaaaaa;
-	dma0_desc_palette_epd[palette_id]->cmd 		= LCD_CMD_PAL | pal_size; /* Palette Descriptor */
-	dma0_desc_palette_epd[palette_id]->offsize	= 0x00000000; /* Palette Descriptor */
-
-	//printk("dma0_desc_palette_epd[%d]->databuf addr(%p) nex_Desc (%p) frame_id (0x%08x) cmd (0x%08x) \n",palette_id,(void*)dma0_desc_palette_epd[palette_id]->databuf,(void *)dma0_desc_palette_epd[palette_id]->next_desc,dma0_desc_palette_epd[palette_id]->frame_id ,dma0_desc_palette_epd[palette_id]->cmd);
-
-
-
-       /* next */
-	for(i=(NR_DMA_DESC_EPD_PER_GROUP*palette_id+1);i<(NR_DMA_DESC_EPD_PER_GROUP*(palette_id+1));i++){
-
-		dma0_desc0 = dma_desc_epd[i];
-		if (i != (NR_DMA_DESC_EPD_PER_GROUP*(palette_id+1) - 1))
-			dma0_desc0->next_desc = (unsigned int)virt_to_phys(dma0_desc0+1);
-		else{
-			dma0_desc_palette_epd[palette_id+1] = dma0_desc0+1;/* frame phys addr */
-			dma0_desc0->next_desc = (unsigned int)virt_to_phys(dma0_desc_palette_epd[palette_id+1]);
-		}
-		dma0_desc0->databuf = virt_to_phys((void *)lcd_frame0);
-		/* frame id */
-		dma0_desc0->frame_id = (unsigned int)0x0000da00; /* DMA0'0 */
-		/* others */
-		dma0_desc0->cmd = fg0_frm_size/4;
-		dma0_desc0->offsize =0;
-		dma0_desc0->page_width = 0;
-		dma0_desc0->desc_size = size0;
-
-		//	printk("dma_desc_epd[%d](0x%08x)  databuf(0x%08x) nex_Desc(0x%08x) frame_id(0x%08x) cmd(0x%08x) \n",i,dma_desc_epd[i],dma0_desc0->databuf,dma0_desc0->next_desc,dma0_desc0->frame_id ,dma0_desc0->cmd);
-
-	}
-
-	/* The fifth Palette Descriptor */
-	palette_id=4;
-
-	dma0_desc_palette_epd[palette_id]->next_desc 	= (unsigned int)virt_to_phys(dma_desc_epd[NR_DMA_DESC_EPD_PER_GROUP*palette_id+1]);
-	dma0_desc_palette_epd[palette_id]->databuf 	= (unsigned int)virt_to_phys((void *)(lcd_palette + palette_offset*palette_id));
-	dma0_desc_palette_epd[palette_id]->frame_id 	= (unsigned int)0xaaaaaaaa;
-	dma0_desc_palette_epd[palette_id]->cmd 		= LCD_CMD_PAL | pal_size; /* Palette Descriptor */
-	dma0_desc_palette_epd[palette_id]->offsize	= 0x00000000; /* Palette Descriptor */
-
-	//printk("dma0_desc_palette_epd[%d]->databuf addr(%p) nex_Desc (%p) frame_id (0x%08x) cmd (0x%08x) \n",palette_id,(void*)dma0_desc_palette_epd[palette_id]->databuf,(void *)dma0_desc_palette_epd[palette_id]->next_desc,dma0_desc_palette_epd[palette_id]->frame_id ,dma0_desc_palette_epd[palette_id]->cmd);
-
-
-
-       /* next */
-	for(i=(NR_DMA_DESC_EPD_PER_GROUP*palette_id+1);i<(NR_DMA_DESC_EPD_PER_GROUP*(palette_id+1));i++){
-
-		dma0_desc0 = dma_desc_epd[i];
-		if (i != (NR_DMA_DESC_EPD_PER_GROUP*(palette_id+1) - 1))
-			dma0_desc0->next_desc = (unsigned int)virt_to_phys(dma0_desc0+1);
-		else{
-			dma0_desc_palette_epd[palette_id+1] = dma0_desc0+1;/* frame phys addr */
-			dma0_desc0->next_desc = (unsigned int)virt_to_phys(dma0_desc_palette_epd[palette_id+1]);
-		}
-		dma0_desc0->databuf = virt_to_phys((void *)lcd_frame0);
-		/* frame id */
-		dma0_desc0->frame_id = (unsigned int)0x0000da00; /* DMA0'0 */
-		/* others */
-		dma0_desc0->cmd = fg0_frm_size/4;
-		dma0_desc0->offsize =0;
-		dma0_desc0->page_width = 0;
-		dma0_desc0->desc_size = size0;
-		//printk("dma0_desc0->databuf 0x%08x nex_Desc (0x%08x) frame_id (0x%08x) cmd (0x%08x) \n",dma0_desc0->databuf,dma0_desc0->next_desc,dma0_desc0->frame_id ,dma0_desc0->cmd);
-
-
-
-	}
-	
-	/* The sixth Palette Descriptor */
-	palette_id=5;
-
-	dma0_desc_palette_epd[palette_id]->next_desc 	= (unsigned int)virt_to_phys(dma_desc_epd[NR_DMA_DESC_EPD_PER_GROUP*palette_id+1]);
-	dma0_desc_palette_epd[palette_id]->databuf 	= (unsigned int)virt_to_phys((void *)(lcd_palette + palette_offset*palette_id));
-	dma0_desc_palette_epd[palette_id]->frame_id 	= (unsigned int)0xaaaaaaaa;
-	dma0_desc_palette_epd[palette_id]->cmd 		= LCD_CMD_PAL | pal_size; /* Palette Descriptor */
-	dma0_desc_palette_epd[palette_id]->offsize	= 0x00000000; /* Palette Descriptor */
-
-	//printk("dma0_desc_palette_epd[%d]->databuf addr(%p) nex_Desc (%p) frame_id (0x%08x) cmd (0x%08x) \n",palette_id,(void*)dma0_desc_palette_epd[palette_id]->databuf,(void *)dma0_desc_palette_epd[palette_id]->next_desc,dma0_desc_palette_epd[palette_id]->frame_id ,dma0_desc_palette_epd[palette_id]->cmd);
-
-
-
-       /* next */
-	for(i=(NR_DMA_DESC_EPD_PER_GROUP*palette_id+1);i<(NR_DMA_DESC_EPD_PER_GROUP*(palette_id+1));i++){
-
-		dma0_desc0 = dma_desc_epd[i];
-		if (i != (NR_DMA_DESC_EPD_PER_GROUP*(palette_id+1) - 1))
-			dma0_desc0->next_desc = (unsigned int)virt_to_phys(dma0_desc0+1);
-		else{
-			dma0_desc_palette_epd[palette_id+1] = dma0_desc0+1;/* frame phys addr */
-			dma0_desc0->next_desc = (unsigned int)virt_to_phys(dma0_desc_palette_epd[palette_id+1]);
-		}
-		dma0_desc0->databuf = virt_to_phys((void *)lcd_frame0);
-		/* frame id */
-		dma0_desc0->frame_id = (unsigned int)0x0000da00; /* DMA0'0 */
-		/* others */
-		dma0_desc0->cmd = fg0_frm_size/4;
-		dma0_desc0->offsize =0;
-		dma0_desc0->page_width = 0;
-		dma0_desc0->desc_size = size0;
-		//printk("dma0_desc0->databuf 0x%08x nex_Desc (0x%08x) frame_id (0x%08x) cmd (0x%08x) \n",dma0_desc0->databuf,dma0_desc0->next_desc,dma0_desc0->frame_id ,dma0_desc0->cmd);
-
-
-	}
-
-
-	
-	/* The seventh Palette Descriptor */
-	palette_id=6;
-
-	dma0_desc_palette_epd[palette_id]->next_desc 	= (unsigned int)virt_to_phys(dma_desc_epd[NR_DMA_DESC_EPD_PER_GROUP*palette_id+1]);
-	dma0_desc_palette_epd[palette_id]->databuf 	= (unsigned int)virt_to_phys((void *)(lcd_palette + palette_offset*palette_id));
-	dma0_desc_palette_epd[palette_id]->frame_id 	= (unsigned int)0xaaaaaaaa;
-	dma0_desc_palette_epd[palette_id]->cmd 		= LCD_CMD_PAL | pal_size; /* Palette Descriptor */
-	dma0_desc_palette_epd[palette_id]->offsize	= 0x00000000; /* Palette Descriptor */
-
-	//printk("dma0_desc_palette_epd[%d]->databuf addr(%p) nex_Desc (%p) frame_id (0x%08x) cmd (0x%08x) \n",palette_id,(void*)dma0_desc_palette_epd[palette_id]->databuf,(void *)dma0_desc_palette_epd[palette_id]->next_desc,dma0_desc_palette_epd[palette_id]->frame_id ,dma0_desc_palette_epd[palette_id]->cmd);
-
-
-       /* next */
-	for(i=(NR_DMA_DESC_EPD_PER_GROUP*palette_id+1);i<(NR_DMA_DESC_EPD_PER_GROUP*(palette_id+1));i++){
-
-		dma0_desc0 = dma_desc_epd[i];
-		if (i != (NR_DMA_DESC_EPD_PER_GROUP*(palette_id+1) - 1))
-			dma0_desc0->next_desc = (unsigned int)virt_to_phys(dma0_desc0+1);
-		else{
-			dma0_desc_palette_epd[palette_id+1] = dma0_desc0+1;/* frame phys addr */
-			dma0_desc0->next_desc = (unsigned int)virt_to_phys(dma0_desc_palette_epd[palette_id+1]);
-			
-		}
-		dma0_desc0->databuf = virt_to_phys((void *)lcd_frame0);
-		/* frame id */
-		dma0_desc0->frame_id = (unsigned int)0x0000da00; /* DMA0'0 */
-		/* others */
-		dma0_desc0->cmd = fg0_frm_size/4;
-		dma0_desc0->offsize =0;
-		dma0_desc0->page_width = 0;
-		dma0_desc0->desc_size = size0;
-		//printk("dma0_desc0->databuf 0x%08x nex_Desc (0x%08x) frame_id (0x%08x) cmd (0x%08x) \n",dma0_desc0->databuf,dma0_desc0->next_desc,dma0_desc0->frame_id ,dma0_desc0->cmd);
-
-	}
-	
-
-
-       /* The eighth Palette Descriptor */
-	palette_id=7;
-
-	dma0_desc_palette_epd[palette_id]->next_desc 	= (unsigned int)virt_to_phys(dma_desc_epd[NR_DMA_DESC_EPD_PER_GROUP*palette_id+1]);
-	dma0_desc_palette_epd[palette_id]->databuf 	= (unsigned int)virt_to_phys((void *)(lcd_palette + palette_offset*palette_id));
-	dma0_desc_palette_epd[palette_id]->frame_id 	= (unsigned int)0xaaaaaaaa;
-	dma0_desc_palette_epd[palette_id]->cmd 		= LCD_CMD_PAL | pal_size; /* Palette Descriptor */
-	dma0_desc_palette_epd[palette_id]->offsize	= 0x00000000; /* Palette Descriptor */
-
-	//printk("dma0_desc_palette_epd[%d]->databuf addr(%p) nex_Desc (%p) frame_id (0x%08x) cmd (0x%08x) \n",palette_id,(void*)dma0_desc_palette_epd[palette_id]->databuf,(void *)dma0_desc_palette_epd[palette_id]->next_desc,dma0_desc_palette_epd[palette_id]->frame_id ,dma0_desc_palette_epd[palette_id]->cmd);
-
-
-       /* next */
-	for(i=(NR_DMA_DESC_EPD_PER_GROUP*palette_id+1);i<(NR_DMA_DESC_EPD_PER_GROUP*(palette_id+1));i++){
-
-		dma0_desc0 = dma_desc_epd[i];
-		if (i != (NR_DMA_DESC_EPD_PER_GROUP*(palette_id+1) - 1))
-			dma0_desc0->next_desc = (unsigned int)virt_to_phys(dma0_desc0+1);
-		else{
-			dma0_desc_palette_epd[palette_id+1] = dma0_desc0+1;/* frame phys addr */
-			dma0_desc0->next_desc = (unsigned int)virt_to_phys(dma0_desc_palette_epd[palette_id+1]);
-		
-		}
-		dma0_desc0->databuf = virt_to_phys((void *)lcd_frame0);
-		/* frame id */
-		dma0_desc0->frame_id = (unsigned int)0x0000da00; /* DMA0'0 */
-		/* others */
-		dma0_desc0->cmd = fg0_frm_size/4;
-		dma0_desc0->offsize =0;
-		dma0_desc0->page_width = 0;
-		dma0_desc0->desc_size = size0;
-		//printk("dma0_desc0->databuf 0x%08x nex_Desc (0x%08x) frame_id (0x%08x) cmd (0x%08x) \n",dma0_desc0->databuf,dma0_desc0->next_desc,dma0_desc0->frame_id ,dma0_desc0->cmd);
-
-
-	}
-
-	
-	/* The ninth Palette Descriptor */
-	palette_id=8;
-
-	dma0_desc_palette_epd[palette_id]->next_desc 	= (unsigned int)virt_to_phys(dma_desc_epd[NR_DMA_DESC_EPD_PER_GROUP*palette_id+1]);
-	dma0_desc_palette_epd[palette_id]->databuf 	= (unsigned int)virt_to_phys((void *)(lcd_palette + palette_offset*palette_id));
-	dma0_desc_palette_epd[palette_id]->frame_id 	= (unsigned int)0xaaaaaaaa;
-	dma0_desc_palette_epd[palette_id]->cmd 		= LCD_CMD_PAL | pal_size; /* Palette Descriptor */
-	dma0_desc_palette_epd[palette_id]->offsize	= 0x00000000; /* Palette Descriptor */
-
-	//printk("dma0_desc_palette_epd[%d]->databuf addr(%p) nex_Desc (%p) frame_id (0x%08x) cmd (0x%08x) \n",palette_id,(void*)dma0_desc_palette_epd[palette_id]->databuf,(void *)dma0_desc_palette_epd[palette_id]->next_desc,dma0_desc_palette_epd[palette_id]->frame_id ,dma0_desc_palette_epd[palette_id]->cmd);
-
-
-       /* next */
-	for(i=(NR_DMA_DESC_EPD_PER_GROUP*palette_id+1);i<(NR_DMA_DESC_EPD_PER_GROUP*(palette_id+1));i++){
-
-		dma0_desc0 = dma_desc_epd[i];
-		if (i != (NR_DMA_DESC_EPD_PER_GROUP*(palette_id+1) - 1))
-			dma0_desc0->next_desc = (unsigned int)virt_to_phys(dma0_desc0+1);
-		else{
-			dma0_desc_palette_epd[palette_id+1] = dma0_desc0+1;/* frame phys addr */
-			dma0_desc0->next_desc = (unsigned int)virt_to_phys(dma0_desc_palette_epd[palette_id+1]);
-			
-		}
-		dma0_desc0->databuf = virt_to_phys((void *)lcd_frame0);
-		/* frame id */
-		dma0_desc0->frame_id = (unsigned int)0x0000da00; /* DMA0'0 */
-		/* others */
-		dma0_desc0->cmd = fg0_frm_size/4;
-		dma0_desc0->offsize =0;
-		dma0_desc0->page_width = 0;
-		dma0_desc0->desc_size = size0;
-		//printk("dma0_desc0->databuf 0x%08x nex_Desc (0x%08x) frame_id (0x%08x) cmd (0x%08x) \n",dma0_desc0->databuf,dma0_desc0->next_desc,dma0_desc0->frame_id ,dma0_desc0->cmd);
-
-
-
-	}
-
-
-	/* The tenth Palette Descriptor */
-	palette_id=9;
-
-	dma0_desc_palette_epd[palette_id]->next_desc 	= (unsigned int)virt_to_phys(dma_desc_epd[NR_DMA_DESC_EPD_PER_GROUP*palette_id+1]);
-	dma0_desc_palette_epd[palette_id]->databuf 	= (unsigned int)virt_to_phys((void *)(lcd_palette + palette_offset*palette_id));
-	dma0_desc_palette_epd[palette_id]->frame_id 	= (unsigned int)0xaaaaaaaa;
-	dma0_desc_palette_epd[palette_id]->cmd 		= LCD_CMD_PAL | pal_size; /* Palette Descriptor */
-	dma0_desc_palette_epd[palette_id]->offsize	= 0x00000000; /* Palette Descriptor */
-
-	//printk("dma0_desc_palette_epd[%d]->databuf addr(%p) nex_Desc (%p) frame_id (0x%08x) cmd (0x%08x) \n",palette_id,(void*)dma0_desc_palette_epd[palette_id]->databuf,(void *)dma0_desc_palette_epd[palette_id]->next_desc,dma0_desc_palette_epd[palette_id]->frame_id ,dma0_desc_palette_epd[palette_id]->cmd);
-
-
-
-       /* next */
-	for(i=(NR_DMA_DESC_EPD_PER_GROUP*palette_id+1);i<(NR_DMA_DESC_EPD_PER_GROUP*(palette_id+1));i++){
-
-		dma0_desc0 = dma_desc_epd[i];
-		if (i != (NR_DMA_DESC_EPD_PER_GROUP*(palette_id+1) - 1))
-			dma0_desc0->next_desc = (unsigned int)virt_to_phys(dma0_desc0+1);
-		else{
-			dma0_desc_palette_epd[palette_id+1] = dma0_desc0+1;/* frame phys addr */
-			dma0_desc0->next_desc = (unsigned int)virt_to_phys(dma0_desc_palette_epd[palette_id+1]);
-			
-		}
-		dma0_desc0->databuf = virt_to_phys((void *)lcd_frame0);
-		/* frame id */
-		dma0_desc0->frame_id = (unsigned int)0x0000da00; /* DMA0'0 */
-		/* others */
-		dma0_desc0->cmd = fg0_frm_size/4;
-		dma0_desc0->offsize =0;
-		dma0_desc0->page_width = 0;
-		dma0_desc0->desc_size = size0;
-		//printk("dma0_desc0->databuf 0x%08x nex_Desc (0x%08x) frame_id (0x%08x) cmd (0x%08x) \n",dma0_desc0->databuf,dma0_desc0->next_desc,dma0_desc0->frame_id ,dma0_desc0->cmd);
-
-	
-	}
-
-
-	/* The eleventh Palette Descriptor */
-	palette_id=10;
-
-	dma0_desc_palette_epd[palette_id]->next_desc 	= (unsigned int)virt_to_phys(dma_desc_epd[NR_DMA_DESC_EPD_PER_GROUP*palette_id+1]);
-	dma0_desc_palette_epd[palette_id]->databuf 	= (unsigned int)virt_to_phys((void *)(lcd_palette + palette_offset*palette_id));
-	dma0_desc_palette_epd[palette_id]->frame_id 	= (unsigned int)0xaaaaaaaa;
-	dma0_desc_palette_epd[palette_id]->cmd 		= LCD_CMD_PAL | pal_size; /* Palette Descriptor */
-	dma0_desc_palette_epd[palette_id]->offsize	= 0x00000000; /* Palette Descriptor */
-
-	//printk("dma0_desc_palette_epd[%d]->databuf addr(%p) nex_Desc (%p) frame_id (0x%08x) cmd (0x%08x) \n",palette_id,(void*)dma0_desc_palette_epd[palette_id]->databuf,(void *)dma0_desc_palette_epd[palette_id]->next_desc,dma0_desc_palette_epd[palette_id]->frame_id ,dma0_desc_palette_epd[palette_id]->cmd);
-
-	
-
-       /* next */
-	for(i=(NR_DMA_DESC_EPD_PER_GROUP*palette_id+1);i<(NR_DMA_DESC_EPD_PER_GROUP*(palette_id+1));i++){
-
-		dma0_desc0 = dma_desc_epd[i];
-		if (i != (NR_DMA_DESC_EPD_PER_GROUP*(palette_id+1) - 1))
-			dma0_desc0->next_desc = (unsigned int)virt_to_phys(dma0_desc0+1);
-		else{
-			dma0_desc_palette_epd[palette_id+1] = dma0_desc0+1;/* frame phys addr */
-			dma0_desc0->next_desc = (unsigned int)virt_to_phys(dma0_desc_palette_epd[palette_id+1]);
-		}
-		dma0_desc0->databuf = virt_to_phys((void *)lcd_frame0);
-		/* frame id */
-		dma0_desc0->frame_id = (unsigned int)0x0000da00; /* DMA0'0 */
-		/* others */
-		dma0_desc0->cmd = fg0_frm_size/4;
-		dma0_desc0->offsize =0;
-		dma0_desc0->page_width = 0;
-		dma0_desc0->desc_size = size0;
-		//printk("dma0_desc0->databuf 0x%08x nex_Desc (0x%08x) frame_id (0x%08x) cmd (0x%08x) \n",dma0_desc0->databuf,dma0_desc0->next_desc,dma0_desc0->frame_id ,dma0_desc0->cmd);
-
-
-	}
-
-	
-	/* The tewlvth Palette Descriptor */
-	palette_id=11;
-
-	dma0_desc_palette_epd[palette_id]->next_desc 	= (unsigned int)virt_to_phys(dma_desc_epd[NR_DMA_DESC_EPD_PER_GROUP*palette_id+1]);
-	dma0_desc_palette_epd[palette_id]->databuf 	= (unsigned int)virt_to_phys((void *)((lcd_palette + palette_offset*palette_id)));
-	dma0_desc_palette_epd[palette_id]->frame_id 	= (unsigned int)0xaaaaaaaa;
-	dma0_desc_palette_epd[palette_id]->cmd 		= LCD_CMD_PAL | pal_size; /* Palette Descriptor */
-	dma0_desc_palette_epd[palette_id]->offsize	= 0x00000000; /* Palette Descriptor */
-
-	//printk("dma0_desc_palette_epd[%d]->databuf addr(%p) nex_Desc (%p) frame_id (0x%08x) cmd (0x%08x) \n",palette_id,(void*)dma0_desc_palette_epd[palette_id]->databuf,(void *)dma0_desc_palette_epd[palette_id]->next_desc,dma0_desc_palette_epd[palette_id]->frame_id ,dma0_desc_palette_epd[palette_id]->cmd);
-
-
-
-      /* next */
-	for(i=(NR_DMA_DESC_EPD_PER_GROUP*palette_id+1);i<(NR_DMA_DESC_EPD_PER_GROUP*(palette_id+1));i++){
-
-		dma0_desc0 = dma_desc_epd[i];
-		if (i != (NR_DMA_DESC_EPD_PER_GROUP*(palette_id+1) - 1))
-			dma0_desc0->next_desc = (unsigned int)virt_to_phys(dma0_desc0+1);
-
-		else{		
-			dma0_desc0->next_desc = (unsigned int)virt_to_phys(dma_desc_epd[0]);
-				
-		}
-		
-		dma0_desc0->databuf = virt_to_phys((void *)lcd_frame0);
-               /* frame id */
-		dma0_desc0->frame_id = (unsigned int)0x0000da00; /* DMA0'0 */
-		/* others */
-		dma0_desc0->cmd = fg0_frm_size/4;
-		dma0_desc0->offsize =0;
-		dma0_desc0->page_width = 0;
-		dma0_desc0->desc_size = size0;
-		//	printk("dma0_desc0->databuf 0x%08x nex_Desc (0x%08x) frame_id (0x%08x) cmd (0x%08x) \n",dma0_desc0->databuf,dma0_desc0->next_desc,dma0_desc0->frame_id ,dma0_desc0->cmd);
-
-	
-
-	}
-
-
-	REG_LCD_DA0 = virt_to_phys(dma0_desc_palette_epd[0]);
-
-#if EPD_MODE_PAL
-	REG_LCD_SIZE0 = size0;
-#else
-	dma0_desc0->cmd = 0;
-	dma0_desc0->desc_size = 0;
-	REG_LCD_DA0 = virt_to_phys(dma0_desc0); //tft
-	REG_LCD_SIZE0 = 0;
-
-#endif
-	current_dma0_id = 0;//dma0_desc0;
-
-        /*===========  fg1 descriptor ===========*/
-	dma1_desc0 = dma_desc_base + NR_DMA_DESC_EPD;
-	/* Foreground 1, caculate size */
-	if ( lcd_info->osd.fg1.x >= lcd_info->panel.w ) 
-		lcd_info->osd.fg1.x = lcd_info->panel.w - 1;
-	if ( lcd_info->osd.fg1.y >= lcd_info->panel.h ) 
-		lcd_info->osd.fg1.y = lcd_info->panel.h - 1;
-	if ( lcd_info->osd.fg1.x + lcd_info->osd.fg1.w > lcd_info->panel.w ) 
-		lcd_info->osd.fg1.w = lcd_info->panel.w - lcd_info->osd.fg1.x;
-	if ( lcd_info->osd.fg1.y + lcd_info->osd.fg1.h > lcd_info->panel.h ) 
-		lcd_info->osd.fg1.h = lcd_info->panel.h - lcd_info->osd.fg1.y;
-
-
-	size1 = lcd_info->osd.fg1.h << 16 | lcd_info->osd.fg1.w;
-	fg1_line_size = lcd_info->osd.fg1.w*lcd_info->osd.fg1.bpp/8;
-	fg1_line_size = ((fg1_line_size+3)>>2)<<2; /* word aligned */
-	fg1_frm_size = fg1_line_size * lcd_info->osd.fg1.h;
-	printk("%s: fg1_frm_size: %d \n",__func__,fg1_frm_size/4);
-	dma1_desc0->next_desc = (unsigned int)virt_to_phys(dma1_desc0);
-			/* frame phys addr */
-	dma1_desc0->databuf  = virt_to_phys((void *)lcd_frame);
-	
-		/* frame id */
-	dma1_desc0->frame_id = (unsigned int)0x0da10000; /* DMA1'0 */
-	
-	dma1_desc0->cmd = fg1_frm_size/4;
-	dma1_desc0->offsize = 0;
-	dma1_desc0->page_width = 0;
-	dma1_desc0->desc_size = size1;
-	
-	//printk("dma1_desc0(0x%08x) databuf(0x%08x) nex_Desc(0x%08x) frame_id(0x%08x) cmd(0x%08x) \n",dma1_desc0,dma1_desc0->databuf,dma1_desc0->next_desc,dma1_desc0->frame_id ,dma1_desc0->cmd);
-
-	REG_LCD_DA1 = virt_to_phys(dma1_desc0);	/* set Dma-chan1's Descripter Addrress */
-	REG_LCD_SIZE1 = size1;
-	current_dma1_id = 0;//dma1_desc0;
-
-
-	dma_cache_wback((unsigned int)(dma_desc_base), (NR_DMA_DESC_EPD + NR_DMA1_DESC_EPD)*sizeof(struct jz4760_lcd_dma_desc));
-}
-
-static void jz4760fb_set_panel_mode(struct jz4760lcd_info * lcd_info)
-{
-	struct jz4760lcd_panel_t *panel = &lcd_info->panel;
-
-	/* set bpp */
-	lcd_info->panel.ctrl &= ~LCD_CTRL_BPP_MASK;
-	if ( lcd_info->osd.fg0.bpp == 1 )
-		lcd_info->panel.ctrl |= LCD_CTRL_BPP_1;
-	else if ( lcd_info->osd.fg0.bpp == 2 )
-		lcd_info->panel.ctrl |= LCD_CTRL_BPP_2;
-	else if ( lcd_info->osd.fg0.bpp == 4 )
-		lcd_info->panel.ctrl |= LCD_CTRL_BPP_4;
-	else if ( lcd_info->osd.fg0.bpp == 8 )
-		lcd_info->panel.ctrl |= LCD_CTRL_BPP_8;
-	else if ( lcd_info->osd.fg0.bpp == 15 ) {
-		lcd_info->osd.fg0.bpp = 16;
-		lcd_info->panel.ctrl |= LCD_CTRL_BPP_16 | LCD_CTRL_RGB555;
-	}
-	else if ( lcd_info->osd.fg0.bpp == 16 ) {
-		lcd_info->panel.ctrl |= LCD_CTRL_BPP_16 | LCD_CTRL_RGB565;
-		lcd_info->panel.ctrl &= ~LCD_CTRL_RGB555;
-	}
-	else if ( lcd_info->osd.fg0.bpp == 30) {
-		lcd_info->osd.fg0.bpp = 32;
-		lcd_info->panel.ctrl |= LCD_CTRL_BPP_30;
-	}
-	else if ( lcd_info->osd.fg0.bpp > 16 && lcd_info->osd.fg0.bpp < 32+1 ) {
-		lcd_info->osd.fg0.bpp = 32;
-		lcd_info->panel.ctrl |= LCD_CTRL_BPP_18_24;
-	}
-	else {
-		printk("The BPP %d is not supported\n", lcd_info->osd.fg0.bpp);
-		lcd_info->osd.fg0.bpp = 32;
-		lcd_info->panel.ctrl |= LCD_CTRL_BPP_18_24;
-	}
-
-	lcd_info->panel.cfg |= LCD_CFG_NEWDES; /* use 8words descriptor always */
-	REG_LCD_CTRL = lcd_info->panel.ctrl; /* LCDC Controll Register */
-
-	REG_LCD_CFG = lcd_info->panel.cfg; /* LCDC Configure Register */
-	REG_SLCD_CFG = lcd_info->panel.slcd_cfg; /* Smart LCD Configure Register */
-	
-	if ( lcd_info->panel.cfg & LCD_CFG_LCDPIN_SLCD ) /* enable Smart LCD DMA */
-		REG_SLCD_CTRL = SLCD_CTRL_DMA_EN;
-
-	switch ( lcd_info->panel.cfg & LCD_CFG_MODE_MASK ) {
-	case LCD_CFG_MODE_GENERIC_TFT:
-	case LCD_CFG_MODE_INTER_CCIR656:
-	case LCD_CFG_MODE_NONINTER_CCIR656:
-	case LCD_CFG_MODE_SLCD:
-	default:		/* only support TFT16 TFT32, not support STN and Special TFT by now(10-06-2008)*/
-		REG_LCD_VAT = (((panel->blw + panel->w + panel->elw + panel->hsw)) << 16) | (panel->vsw + panel->bfw + panel->h + panel->efw);
-		REG_LCD_DAH = ((panel->hsw + panel->blw) << 16) | (panel->hsw + panel->blw + panel->w);
-		REG_LCD_DAV = ((panel->vsw + panel->bfw) << 16) | (panel->vsw + panel->bfw + panel->h);
-		REG_LCD_HSYNC = (0 << 16) | panel->hsw;
-		REG_LCD_VSYNC = (0 << 16) | panel->vsw;
-		break;
-	}
-}
-
-
-//static void jz4760fb_set_osd_mode( struct jz4760lcd_info * lcd_info )
-static void jz4760fb_set_osd_mode(struct jz4760lcd_osd_t *lcd_osd_info)
-{
-	lcd_osd_info->osd_ctrl &= ~(LCD_OSDCTRL_OSDBPP_MASK);
-	if(lcd_osd_info->fg1.bpp == 2)
-		lcd_osd_info->osd_ctrl |= LCD_OSDCTRL_OSDBPP_2;
-	else if(lcd_osd_info->fg1.bpp == 4)
-		lcd_osd_info->osd_ctrl |= LCD_OSDCTRL_OSDBPP_4;
-	else if ( lcd_osd_info->fg1.bpp == 15 )
-		lcd_osd_info->osd_ctrl |= LCD_OSDCTRL_OSDBPP_15_16|LCD_OSDCTRL_RGB555;
-	else if ( lcd_osd_info->fg1.bpp == 16 ) {
-		lcd_osd_info->osd_ctrl |= LCD_OSDCTRL_OSDBPP_15_16;
-		lcd_osd_info->osd_ctrl &= ~LCD_OSDCTRL_RGB555;
-	}
-	else if (lcd_osd_info->fg1.bpp == 30) {
-		lcd_osd_info->osd_ctrl |= LCD_OSDCTRL_OSDBPP_30;
-	}
-	else {
-		lcd_osd_info->fg1.bpp = 32;
-		lcd_osd_info->osd_ctrl |= LCD_OSDCTRL_OSDBPP_18_24;
-	}
-
-
-	REG_LCD_OSDC 	= lcd_osd_info->osd_cfg; /* F0, F1, alpha, */
-
-	REG_LCD_OSDCTRL = lcd_osd_info->osd_ctrl; /* IPUEN, bpp */
-	REG_LCD_RGBC  	= lcd_osd_info->rgb_ctrl;
-	REG_LCD_BGC  	= lcd_osd_info->bgcolor;
-	REG_LCD_KEY0 	= lcd_osd_info->colorkey0;
-	REG_LCD_KEY1 	= lcd_osd_info->colorkey1;
-	REG_LCD_ALPHA 	= lcd_osd_info->alpha;
-	REG_LCD_IPUR 	= lcd_osd_info->ipu_restart;
-}
-
-
-
-/* Change Position of Foreground 0 */
-static int jz4760fb0_foreground_move(struct jz4760lcd_osd_t *lcd_osd_info)
-{
-	int pos;
-	int j, count;
-	/* 
-	 * Foreground, only one of the following can be change at one time:
-	 * 	1. F0 size, 2. F0 position, 3. F1 size, 4. F1 position
-	 *
-	 * The rules of fg0 position:
-	 * 	fg0.x + fg0.w <= panel.w;
-	 * 	fg0.y + fg0.h <= panel.h;
-	 *
-	 * When output is LCD panel, fg.y can be odd number or even number.
-	 * When output is TVE, as the TVE has odd frame and even frame,
-	 * to simplified operation, fg.y should be even number always.
-	 *
-	 */
-
-	/* Foreground 0  */
-	if (lcd_osd_info->fg0.x + lcd_osd_info->fg0.w > jz4760_lcd_info->panel.w)
-		lcd_osd_info->fg0.x = jz4760_lcd_info->panel.w - lcd_osd_info->fg0.w;
-	if (lcd_osd_info->fg0.y + lcd_osd_info->fg0.h > jz4760_lcd_info->panel.h)
-		lcd_osd_info->fg0.y = jz4760_lcd_info->panel.h - lcd_osd_info->fg0.h;
-
-	if (lcd_osd_info->fg0.x >= jz4760_lcd_info->panel.w)
-		lcd_osd_info->fg0.x = jz4760_lcd_info->panel.w - 1;
-	if (lcd_osd_info->fg0.y >= jz4760_lcd_info->panel.h)
-		lcd_osd_info->fg0.y = jz4760_lcd_info->panel.h - 1;
-
-	pos = lcd_osd_info->fg0.y << 16 | lcd_osd_info->fg0.x;
-	if (REG_LCD_XYP0 == pos){
-		printk("FG0: same position\n");
-		return 0;
-	}
-
-	REG_LCD_XYP0 = pos;
-	REG_LCD_OSDCTRL |= LCD_OSDCTRL_CHANGES;
-	while(!(REG_LCD_OSDS & LCD_OSDS_READY));
-	j = count;
-	msleep(40);
-	while((REG_LCD_OSDCTRL & LCD_OSDCTRL_CHANGES) && j--);
-	if(j == 0) {
-		printk("Error FG0 Position: Wait change fail.\n");
-		return -EFAULT;
-	}
-
-	return 0;
-}
-/* Change Window size of Foreground 0 */
-static int jz4760fb0_foreground_resize(struct jz4760lcd_osd_t *lcd_osd_info)
-{
-	struct lcd_cfb_info *cfb = jz4760fb_info;
-	int size, fg0_line_size, fg0_frm_size;
-//	int desc_len = sizeof(struct jz4760_lcd_dma_desc);
-	/* 
-	 * NOTE: 
-	 * Foreground change sequence: 
-	 * 	1. Change Position Registers -> LCD_OSDCTL.Change;
-	 * 	2. LCD_OSDCTRL.Change -> descripter->Size
-	 * Foreground, only one of the following can be change at one time:
-	 * 	1. F0 size;
-	 *	2. F0 position
-	 * 	3. F1 size
-	 *	4. F1 position
-	 */
-	
-	/* 
-	 * The rules of f0, f1's position:
-	 * 	f0.x + f0.w <= panel.w;
-	 * 	f0.y + f0.h <= panel.h;
-	 *
-	 * When output is LCD panel, fg.y and fg.h can be odd number or even number.
-	 * When output is TVE, as the TVE has odd frame and even frame,
-	 * to simplified operation, fg.y and fg.h should be even number always.
-	 *
-	 */
-	/* Foreground 0  */
-	if (lcd_osd_info->fg0.x + lcd_osd_info->fg0.w > jz4760_lcd_info->panel.w)
-		lcd_osd_info->fg0.w = jz4760_lcd_info->panel.w - lcd_osd_info->fg0.x;
-	if (lcd_osd_info->fg0.y + lcd_osd_info->fg0.h > jz4760_lcd_info->panel.h)
-		lcd_osd_info->fg0.h = jz4760_lcd_info->panel.h - lcd_osd_info->fg0.y;
-
-	size = lcd_osd_info->fg0.h << 16 | lcd_osd_info->fg0.w;
-
-	if (REG_LCD_SIZE0 == size) {
-		printk("FG0: same size\n");
-		return 0;
-	}
-
-	fg0_line_size = lcd_osd_info->fg0.w * lcd_osd_info->fg0.bpp / 8;
-	fg0_line_size = ((fg0_line_size + 3) >> 2) << 2; /* word aligned */
-	fg0_frm_size = fg0_line_size * lcd_osd_info->fg0.h;
-
-	REG_LCD_OSDCTRL |= LCD_OSDCTRL_CHANGES;
-	/* set change bit */
-	REG_LCD_OSDCTRL |= LCD_OSDCTRL_CHANGES;
-
-	if (jz4760_lcd_info->panel.cfg & LCD_CFG_TVEN ) { /* output to TV */
-		dma0_desc0->cmd = dma0_desc1->cmd = (fg0_frm_size/4)/2;
-		dma0_desc0->offsize = dma0_desc1->offsize 
-			= fg0_line_size/4;
-		dma0_desc0->page_width = dma0_desc1->page_width 
-			= fg0_line_size/4;
-		dma0_desc1->databuf = virt_to_phys((void *)(lcd_frame0 + fg0_line_size));
-	}
-	else {
-		dma0_desc0->cmd = dma0_desc1->cmd = fg0_frm_size/4;
-		dma0_desc0->offsize = dma0_desc1->offsize =0;
-		dma0_desc0->page_width = dma0_desc1->page_width = 0;
-		}
-	
-	dma0_desc0->desc_size = dma0_desc1->desc_size = size;
-//			= lcd_osd_info->fg0.h << 16 | lcd_osd_info->fg0.w;
-	REG_LCD_SIZE0 = size;
-//	REG_LCD_SIZE0 = (lcd_osd_info->fg0.h << 16) | lcd_osd_info->fg0.w;
-
-	dma_cache_wback((unsigned int)(dma_desc_base), (DMA_DESC_NUM)*sizeof(struct jz4760_lcd_dma_desc));
-
-	jz4760fb_set_var(&cfb->fb0.var, 0, &cfb->fb0);
-	return 0;
-}
-
-/* Change Position of Foreground 1 */
-static int jz4760fb_foreground_move(struct jz4760lcd_osd_t *lcd_osd_info)
-{
-	int pos;
-	int j, count = 100000;
-	/* 
-	 * Foreground, only one of the following can be change at one time:
-	 * 	1. F0 size, 2. F0 position, 3. F1 size, 4. F1 position
-	 *
-	 * The rules of fg1 position:
-	 * 	fg1.x + fg1.w <= panel.w;
-	 * 	fg1.y + fg1.h <= panel.h;
-	 *
-	 * When output is LCD panel, fg.y can be odd number or even number.
-	 * When output is TVE, as the TVE has odd frame and even frame,
-	 * to simplified operation, fg.y should be even number always.
-	 *
-	 */
-
-	/* Foreground 0  */
-	if (lcd_osd_info->fg1.x + lcd_osd_info->fg1.w > jz4760_lcd_info->panel.w)
-		lcd_osd_info->fg1.x = jz4760_lcd_info->panel.w - lcd_osd_info->fg1.w;
-	if (lcd_osd_info->fg1.y + lcd_osd_info->fg1.h > jz4760_lcd_info->panel.h)
-		lcd_osd_info->fg1.y = jz4760_lcd_info->panel.h - lcd_osd_info->fg1.h;
-
-	if (lcd_osd_info->fg1.x >= jz4760_lcd_info->panel.w)
-		lcd_osd_info->fg1.x = jz4760_lcd_info->panel.w - 1;
-	if (lcd_osd_info->fg1.y >= jz4760_lcd_info->panel.h)
-		lcd_osd_info->fg1.y = jz4760_lcd_info->panel.h - 1;
-
-	pos = lcd_osd_info->fg1.y << 16 | lcd_osd_info->fg1.x;
-	if (REG_LCD_XYP1 == pos){
-		printk("FG1: same position\n");
-		return 0;
-	}
-
-	/*********************************************/
-	REG_LCD_XYP1 = pos;
-	REG_LCD_OSDCTRL |= LCD_OSDCTRL_CHANGES;
-	while(!(REG_LCD_OSDS & LCD_OSDS_READY));
-	j = count;
-	msleep(40);
-	while((REG_LCD_OSDCTRL & LCD_OSDCTRL_CHANGES) && j--);
-	if(j == 0) {
-		printk("Error FG1 Position: Wait change fail.\n");
-		return -EFAULT;
-
-	}
-	return 0;
-}
-
-/* Change window size of Foreground 1 */
-static int jz4760fb_foreground_resize(struct jz4760lcd_osd_t *lcd_osd_info)
-{
-	struct lcd_cfb_info *cfb = jz4760fb_info;
-	int size, fg1_line_size, fg1_frm_size;
-//	int desc_len = sizeof(struct jz4760_lcd_dma_desc);
-	/* 
-	 * NOTE: 
-	 * Foreground change sequence: 
-	 * 	1. Change Position Registers -> LCD_OSDCTL.Change;
-	 * 	2. LCD_OSDCTRL.Change -> descripter->Size
-	 * Foreground, only one of the following can be change at one time:
-	 * 	1. F0 size;
-	 *	2. F0 position
-	 * 	3. F1 size
-	 *	4. F1 position
-	 */
-	
-	/* 
-	 * The rules of f0, f1's position:
-	 * 	f0.x + f0.w <= panel.w;
-	 * 	f0.y + f0.h <= panel.h;
-	 *
-	 * When output is LCD panel, fg.y and fg.h can be odd number or even number.
-	 * When output is TVE, as the TVE has odd frame and even frame,
-	 * to simplified operation, fg.y and fg.h should be even number always.
-	 *
-	 */
-
-	/* Foreground 0  */
-	if (lcd_osd_info->fg1.x + lcd_osd_info->fg1.w > jz4760_lcd_info->panel.w)
-		lcd_osd_info->fg1.w = jz4760_lcd_info->panel.w - lcd_osd_info->fg1.x;
-	if (lcd_osd_info->fg1.y + lcd_osd_info->fg1.h > jz4760_lcd_info->panel.h)
-		lcd_osd_info->fg1.h = jz4760_lcd_info->panel.h - lcd_osd_info->fg1.y;
-//	size = lcd_info->osd.fg1.h << 16|lcd_info->osd.fg1.w;
-	size = lcd_osd_info->fg1.h << 16|lcd_osd_info->fg1.w;
-	if (REG_LCD_SIZE1 == size) {
-		printk("FG1: same size\n");
-		return 0;// -EFAULT;
-	}
-
-//	fg1_line_size = lcd_osd_info->fg1.w * ((lcd_osd_info->fg1.bpp + 7) / 8);
-	fg1_line_size = lcd_osd_info->fg1.w * lcd_osd_info->fg1.bpp / 8;
-	fg1_line_size = ((fg1_line_size + 3) >> 2) << 2; /* word aligned */
-	fg1_frm_size = fg1_line_size * lcd_osd_info->fg1.h;
-
-	/* set change bit */
-	REG_LCD_OSDCTRL |= LCD_OSDCTRL_CHANGES;
-	if ( jz4760_lcd_info->panel.cfg & LCD_CFG_TVEN ) { /* output to TV */
-		dma1_desc0->cmd = dma1_desc1->cmd = (fg1_frm_size/4)/2;
-		dma1_desc0->offsize = dma1_desc1->offsize = fg1_line_size/4;
-		dma1_desc0->page_width = dma1_desc1->page_width = fg1_line_size/4;
-		dma1_desc1->databuf = virt_to_phys((void *)(lcd_frame + fg1_line_size));
-	}
-	else {
-		dma1_desc0->cmd = dma1_desc1->cmd = fg1_frm_size/4;
-		dma1_desc0->offsize = dma1_desc1->offsize = 0;
-		dma1_desc0->page_width = dma1_desc1->page_width = 0;
-	}
-
-	dma1_desc0->desc_size = dma1_desc1->desc_size = size;
-	REG_LCD_SIZE1 = size;
-
-	dma_cache_wback((unsigned int)(dma_desc_base), (DMA_DESC_NUM)*sizeof(struct jz4760_lcd_dma_desc));
-
-	jz4760fb_set_var(&cfb->fb.var, 1, &cfb->fb);
-	return 0;
-}
-
-
-
-/*
- * Set lcd pixel clock 
- */
-static void jz4760fb_change_clock( struct jz4760lcd_info * lcd_info )
-{
-#if defined(CONFIG_FPGA)   /* FPGA test, pixdiv */
-//	REG_LCD_REV = 0x0000002;
-	REG_LCD_REV = 0x0000001;
-	printk("Fuwa test, pixclk divide REG_LCD_REV=0x%08x\n", REG_LCD_REV);
-	printk("Fuwa test, pixclk %d\n", JZ_EXTAL/(((REG_LCD_REV&0xFF)+1)*2));
-#else 
-	unsigned int val = 0;
-	unsigned int pclk;
-	/* Timing setting */
-	__cpm_stop_lcd();
-
-	val = lcd_info->panel.fclk; /* frame clk */
-
-	if ( (lcd_info->panel.cfg & LCD_CFG_MODE_MASK) != LCD_CFG_MODE_SERIAL_TFT) {
-		pclk = val * (lcd_info->panel.w + lcd_info->panel.hsw + lcd_info->panel.elw + lcd_info->panel.blw) * (lcd_info->panel.h + lcd_info->panel.vsw + lcd_info->panel.efw + lcd_info->panel.bfw); /* Pixclk */
-	}
-	else {
-		/* serial mode: Hsync period = 3*Width_Pixel */
-		pclk = val * (lcd_info->panel.w*3 + lcd_info->panel.hsw + lcd_info->panel.elw + lcd_info->panel.blw) * (lcd_info->panel.h + lcd_info->panel.vsw + lcd_info->panel.efw + lcd_info->panel.bfw); /* Pixclk */
-	}
-
-	/********* In TVE mode PCLK = 27MHz ***********/
-	if ( lcd_info->panel.cfg & LCD_CFG_TVEN ) { 		/* LCDC output to TVE */
-		pclk = 27000000;
-		__cpm_select_pixclk_tve();
-	}
-	else { 		/* LCDC output to  LCD panel */
-		__cpm_select_pixclk_lcd();
-	}
-
-#if defined(CONFIG_JZ4760_EPSON_EPD_DISPLAY)
-	pclk = 30000000;
-	val = __cpm_get_pllout2() / pclk; /* pclk */
-#else
-	val = __cpm_get_pllout2() / pclk; /* pclk */
-#endif	
-
-	val--;
-	dprintk("ratio: val = %d\n", val);
-	if ( val > 0x7ff ) {
-		printk("pixel clock divid is too large, set it to 0x7ff\n");
-		val = 0x7ff;
-	}
-
-
-	__cpm_set_pixdiv(val);
-//	REG_CPM_LPCDR = 0x0000000e;
-	dprintk("REG_CPM_LPCDR = 0x%08x\n", REG_CPM_LPCDR);
-	__cpm_enable_pll_change();
-
-	dprintk("REG_CPM_LPCDR=0x%08x\n", REG_CPM_LPCDR);
-	dprintk("REG_CPM_CPCCR=0x%08x\n", REG_CPM_CPCCR);
-
-	jz_clocks.pixclk = __cpm_get_pixclk();
-	printk("LCDC: PixClock:%d\n", jz_clocks.pixclk);
-	__cpm_start_lcd();
-	udelay(1000);
-
-	/* 
-	 * set lcd device clock and lcd pixel clock.
-	 * what about TVE mode???
-	 *
-	 */
-#endif
-
-}
-
-
-/* 
- * jz4760fb_deep_set_mode, 
- *
- */
-static void jz4760fb_deep_set_mode( struct jz4760lcd_info * lcd_info )
-{
-	/* configurate sequence:
-	 * 1. disable lcdc.
-	 * 2. init frame descriptor.
-	 * 3. set panel mode
-	 * 4. set osd mode
-	 * 5. start lcd clock in CPM
-	 * 6. enable lcdc.
-	 */
-	struct lcd_cfb_info *cfb = jz4760fb_info;
-
-//	__lcd_clr_ena();	/* Quick Disable */
-	lcd_info->osd.fg_change = FG_CHANGE_ALL; /* change FG0, FG1 size, postion??? */
-	jz4760fb_set_osd_mode(&lcd_info->osd);
-	jz4760fb_set_panel_mode(lcd_info);
-
-	jz4760fb_epd_descriptor_init(lcd_info);
-
-	jz4760fb_change_clock(lcd_info);
-if (use_fg0_only || use_2layer_Fg)
-	jz4760fb_set_var(&cfb->fb0.var, 0, &cfb->fb0);
-
-if (use_fg1_only || use_2layer_Fg)
-	jz4760fb_set_var(&cfb->fb.var, 1, &cfb->fb);
-
-//	__lcd_set_ena();	/* enable lcdc */
-}
-
-
-static irqreturn_t jz4760fb_interrupt_handler(int irq, void *dev_id)
-{
-	unsigned int state;
-	static int irqcnt=0;
-	static int framecnt = 0;
-
-	state = REG_LCD_STATE;
-//	printk("-------------In the lcd interrupt handler, state=0x%x--------\n", state);
-	if (state & EPD_STATE_PWRUP) {
-		REG_LCD_STATE = state & ~EPD_STATE_PWRUP;
-		mdelay(1);
-#if EPD_MODE_PAL
-		{
-			//	REG_LCD_DA0 = virt_to_phys(dma0_desc_palette);
-			REG_LCD_DA0 = virt_to_phys(dma0_desc_palette_epd[framecnt]);
-			REG_LCD_DA1 = virt_to_phys(dma1_desc0);     	
-		
-			//REG_SLCD_CTRL |= (1 << 1);
-			REG_SLCD_CTRL = 0;
-			__lcd_set_ena();	/* enalbe LCD Controller */
-		}
-#else
-		{
-			dma0_desc0->cmd = 0;
-			REG_SLCD_CTRL = 0;
-			__lcd_set_ena();	/* enalbe LCD Controller */
-		}
-
-#endif
-//		printk("power on!");
-		REG_LCD_CTRL |= LCD_CTRL_PEDN;		
-		REG_EPD_CTRL4 |= EPD_CTRL4_FEN;
-	}
-	if (state & EPD_STATE_PWRDN) {
-		REG_LCD_STATE = state & ~EPD_STATE_PWRDN;
-//		printk("EPD Power Down interrupt\n");
-	}
-
-	if (state & EPD_STATE_FEND) {
-		REG_LCD_STATE = state & ~EPD_STATE_FEND;
-		/* IC only support 16 frames, in this situation epd works well,
-		   but for more than 16 frames we should do sth
-		   Added by Cynthia */
-		
-                __lcd_clr_ena();
-
-		 if( totally_time > (++framecnt)){
-			 REG_LCD_DA0 = virt_to_phys(dma0_desc_palette_epd[framecnt]);
-			 REG_LCD_DA1 = virt_to_phys(dma1_desc0);     	
-			 REG_SLCD_CTRL |= SLCD_CTRL_DMA_START;
-			 REG_EPD_CTRL4 |= EPD_CTRL4_FEN;	
- //			printk("totally_time=%d , framecnt=%d \n",totally_time, framecnt);
-		 }
-		 else{
-
-			 framecnt =0;
-			 REG_EPD_CTRL4 &= ~EPD_CTRL4_FEN;
-			 REG_EPD_CTRL2 |= EPD_CTRL2_PWROFF; 
-		 }
-
-
-		 __lcd_set_ena();
-//		 printk("EPD Frame End interrupt state = 0x%x cnt= %d \n ", state,framecnt);
-
-/* ended by Cynthia */
-		
-
-	}
-	if (state & LCD_STATE_EOF) /* End of frame */
-	{	
-		REG_LCD_STATE = state & ~LCD_STATE_EOF;
-		//	irqcnt++;
-		printk("======== End of frame =  \n");
-	
-	}
-	if (state & LCD_STATE_IFU0) {
-		//	printk("%s, In FiFo0 underrun\n", __FUNCTION__);
-		REG_LCD_STATE = state & ~LCD_STATE_IFU0;
-	
-	}
-
-	if (state & LCD_STATE_IFU1) {
-		REG_LCD_STATE = state & ~LCD_STATE_IFU1;
-//		printk("%s, InFiFo1 underrun\n", __FUNCTION__);
-		
-	}
-
-	if (state & LCD_STATE_OFU) { /* Out fifo underrun */
-		REG_LCD_STATE = state & ~LCD_STATE_OFU;		
-		if ( irqcnt++ > 100 ) {
-			//__lcd_disable_ofu_intr();
-			//printk("disable Out FiFo underrun irq.\n");
-		}
-		printk("%s, Out FiFo underrun.\n", __FUNCTION__);
-		//
-//	printk("REG_LCD_CMD0:\t0x%08x, REG_LCD_CMD1:\t0x%08x\n", REG_LCD_CMD0,REG_LCD_CMD1);
-	}
-	return IRQ_HANDLED;
-}
-
-#ifdef CONFIG_PM
-
-/*
- * Suspend the LCDC.
- */
-static int jz4760fb_suspend(struct platform_device *pdev, pm_message_t state)
-{
-	__lcd_clr_ena(); /* Quick Disable */
-	__lcd_display_off();
-	__cpm_stop_lcd();
-
-	return 0;
-}
-
-/*
- * Resume the LCDC.
- */
-static int jz4760fb_resume(struct platform_device *pdev)
-{
-	__cpm_start_lcd();
-	REG_LCD_DA1 = virt_to_phys(dma1_desc0);
-	__lcd_set_ena();
-	__lcd_display_on();
-
-return 0;
-}
-#else
-static int jz4760fb_suspend(struct device *dev, pm_message_t state) {return 0;}
-static int jz4760fb_resume(struct device *dev) {return 0;}
-#endif /* CONFIG_PM */
-
-/* The following routine is only for test */
-
-static void jz4760_lcd_gpio_init(void)
-{
-	/* gpio init __gpio_as_lcd */
-	if (jz4760_lcd_info->panel.cfg & LCD_CFG_MODE_TFT_16BIT)
-		__gpio_as_lcd_16bit();
-	else if (jz4760_lcd_info->panel.cfg & LCD_CFG_MODE_TFT_24BIT)
-		__gpio_as_lcd_24bit();
-	else
- 		__gpio_as_lcd_18bit();
-
-	/* Configure SLCD module for setting smart lcd control registers */
-#if defined(CONFIG_FB_JZ4760_SLCD)
-	__lcd_as_smart_lcd();
-	__slcd_disable_dma();
-	__init_slcd_bus();	/* Note: modify this depend on you lcd */
-
-#endif	
-	__lcd_display_pin_init();
-}
-
-static void jz4760_lcd_init_cfg(void)
-{
-	if (use_fg0_only || use_2layer_Fg)
-		jz4760_lcd_info->osd.osd_cfg |= LCD_OSDC_F0EN; /* only open fg0 */
-	
-//	jz4760_lcd_info->osd.osd_cfg |= LCD_OSDC_F1EN; /* only open fg1 */
-
-	/* In special mode, we only need init special pin, 
-	 * as general lcd pin has init in uboot */
-#if defined(CONFIG_SOC_JZ4760)
-	switch (jz4760_lcd_info->panel.cfg & LCD_CFG_MODE_MASK) {
-	case LCD_CFG_MODE_SPECIAL_TFT_1:
-	case LCD_CFG_MODE_SPECIAL_TFT_2:
-	case LCD_CFG_MODE_SPECIAL_TFT_3:
-		__gpio_as_lcd_special();
-		break;
-	default:
-		break;
-	}
-#endif
-}
-#ifdef CONFIG_LEDS_CLASS
-static void lcd_set_backlight_level(struct led_classdev *led_cdev, enum led_brightness value) {
-	__lcd_set_backlight_level((int)value);
-}
-
-static struct led_classdev lcd_backlight_led = {
-	.name			= "lcd-backlight",
-	.brightness_set		= lcd_set_backlight_level,
-};
-#endif
-
-
-static int __init jz4760fb_probe(struct platform_device *pdev)
-{
-	struct lcd_cfb_info *cfb;
-	int err = 0;
-	__lcd_close_backlight();
-	if (!pdev)
-		return -EINVAL;
-	jz4760_lcd_gpio_init();		/* gpio init */
-	__gpio_as_epd();
-	jz4760_lcd_init_cfg();		/* first config of lcd */
-
-	__lcd_clr_dis();
-	__lcd_clr_ena();
-
-	/* init clock */
-	__lcd_slcd_special_on();
-
-	cfb = jz4760fb_alloc_fb_info();
-	if (!cfb)
-		goto failed;
-
-	err = jz4760fb_map_smem(cfb);
-	if (err)
-		goto failed;
-
-	jz4760fb_deep_set_mode( jz4760_lcd_info ); 
-
-	/* registers frame buffer devices */
-
-	if (use_fg0_only || use_2layer_Fg)
-	{	/* register fg0 */
-		err = register_framebuffer(&cfb->fb0);
-		if (err < 0) {
-			dprintk("jz4760fb_init(): register framebuffer err.\n");
-			goto failed;
-		}
-		printk("fb%d: %s frame buffer device, using %dK of video memory\n",
-		       cfb->fb0.node, cfb->fb0.fix.id, cfb->fb0.fix.smem_len>>10);
-		
-	}
-	
-	if (use_fg1_only || use_2layer_Fg)
-	{/* register fg1 */
-		err = register_framebuffer(&cfb->fb);
-		if (err < 0) {
-			dprintk("jz4760fb_init(): register framebuffer err.\n");
-			goto failed;
-		}
-		printk("fb%d: %s frame buffer device, using %dK of video memory\n",
-		       cfb->fb.node, cfb->fb.fix.id, cfb->fb.fix.smem_len>>10);
-	}
-
-
-	get_temp_sensor();
-	epd_gray_level = 8;
-	fill_init_palette();
-
-	if (request_irq(IRQ_LCD, jz4760fb_interrupt_handler, IRQF_DISABLED,
-			"lcd", 0)) {
-		err = -EBUSY;
-		goto failed;
-	}
-	 
-#ifdef CONFIG_LEDS_CLASS
-	err = led_classdev_register(&pdev->dev, &lcd_backlight_led);
-	if (err < 0)
-		goto failed;
-#endif
-#if defined(CONFIG_JZ4760_EPSON_EPD_DISPLAY)
-	init_epd_controller();
-	REG_SLCD_CTRL |= SLCD_CTRL_DMA_START;
-#endif
-
-#if defined(CONFIG_JZ4760_EPSON_EPD_DISPLAY)
-	REG_EPD_CTRL2 |= (EPD_CTRL2_PWRON);
-#else
-	__lcd_set_ena();	/* enalbe LCD Controller */
-	__lcd_display_on();
-#endif
-
-//	print_lcdc_registers();
-	pm_set_vt_switch(0); /*disable VT switch during suspend/resume*/
-	return 0;
-
-failed:
-	print_dbg();
-	jz4760fb_unmap_smem(cfb);
-	jz4760fb_free_fb_info(cfb);
-
-	return err;
-}
-
-static int jz4760fb_remove(struct platform_device *pdev)
-{
-	struct lcd_cfb_info *cfb = platform_get_drvdata(pdev);
-
-	jz4760fb_unmap_smem(cfb);
-	jz4760fb_free_fb_info(cfb);
-	return 0;
-}
-
-
-
-static struct platform_driver jz_lcd_driver = {
-	.probe = jz4760fb_probe,
-	.remove = jz4760fb_remove,
-#ifdef CONFIG_PM
-	.suspend = jz4760fb_suspend,
-	.resume = jz4760fb_resume,
-#endif
-	.driver = {
-		   .name = DRIVER_NAME,
-		   },
-};
-
-static int __init jz4760fb_init(void)
-{
-	return platform_driver_register(&jz_lcd_driver);
-}
-
-static void __exit jz4760fb_cleanup(void)
-{
-	platform_driver_unregister(&jz_lcd_driver);
-}
-
-module_init(jz4760fb_init);
-module_exit(jz4760fb_cleanup);
diff --git a/drivers/video/jz4760_lcd.c b/drivers/video/jz4760_lcd.c
index 9a1d1b99ad5..a227d022586 100644
--- a/drivers/video/jz4760_lcd.c
+++ b/drivers/video/jz4760_lcd.c
@@ -291,11 +291,180 @@ struct jz4760lcd_info jz4760_lcd_panel = {
 		 .fg0 = {32, 0, 0, 640, 480}, /* bpp, x, y, w, h */
 		 .fg1 = {32, 0, 0, 640, 480}, /* bpp, x, y, w, h */
 	 },
+
 #else
 #error "Select LCD panel first!!!"
 #endif
 };
 
+#if defined(CONFIG_JZ4760_HDMI_DISPLAY)  
+#define   AIC_FR_TFTH_BIT         16
+#define   AIC_FR_RFTH_BIT         24
+
+#define PANEL_MODE_HDMI_480P    3
+#define PANEL_MODE_HDMI_576P    4
+#define PANEL_MODE_HDMI_720P50  5
+#define PANEL_MODE_HDMI_720P60  6
+
+struct jz4760lcd_info jz4760_info_hdmi_480p = {                            
+        .panel = {                                                     
+                .cfg = LCD_CFG_MODE_GENERIC_TFT | LCD_CFG_MODE_TFT_24BIT |
+                       LCD_CFG_NEWDES | LCD_CFG_RECOVER |                 
+                       LCD_CFG_PCP | LCD_CFG_HSP | LCD_CFG_VSP,           
+                .slcd_cfg = 0,                                            
+		.ctrl = LCD_CTRL_BST_32,                                  
+		//  width,height,freq,hsync,vsync,elw,blw,efw,bfw         
+		640,480, 60, 96, 2,48,16,  33,10,       //HDMI-480P       
+		//800,600,58,128,4,88,40,23,1,i
+		//1024,768,60,136,6,160,24,29,3,
+	},                                      
+        .osd = {                                
+                .osd_cfg =  LCD_OSDC_OSDEN      |               // Use OSD mode
+                 LCD_OSDC_ALPHAEN                       |               // enable alpha
+                 LCD_OSDC_F0EN                          ,               // enable Foreground0    
+                // LCD_OSDC_F1EN,                                         // enable Foreground1    
+		
+                 .osd_ctrl = 0,                                         // disable ipu,          
+                 .rgb_ctrl = 0,                                                                  
+                 .bgcolor = 0x000000,                           // set background color Black    
+                 .colorkey0 = 0,                                        // disable colorkey
+                 .colorkey1 = 0,                                        // disable colorkey
+                 .alpha = 0xa0,                                         // alpha value
+                 .ipu_restart = 0x8000085d,                     // ipu restart
+                 .fg_change = FG_CHANGE_ALL,            // change all initially
+		 .fg0 = {32, 0, 0, 640, 480},   // bpp, x, y, w, h
+                 .fg1 = {32, 0, 0, 640, 480},       // bpp, x, y, w, h
+        },
+};
+struct jz4760lcd_info jz4760_info_hdmi_576p = {                            
+        .panel = {                                                     
+                .cfg = LCD_CFG_MODE_GENERIC_TFT | LCD_CFG_MODE_TFT_24BIT |
+                       LCD_CFG_NEWDES | LCD_CFG_RECOVER |                 
+                       LCD_CFG_PCP | LCD_CFG_HSP | LCD_CFG_VSP,           
+                .slcd_cfg = 0,                                            
+		.ctrl = LCD_CTRL_BST_32,                                  
+		//  width,height,freq,hsync,vsync,elw,blw,efw,bfw         
+		720,576,50,64,5,68,12,40,4,                               
+		//800,600,58,128,4,88,40,23,1,i
+		//1024,768,60,136,6,160,24,29,3,
+	},                                      
+        .osd = {                                
+                .osd_cfg =  LCD_OSDC_OSDEN      |               // Use OSD mode
+                 LCD_OSDC_ALPHAEN                       |               // enable alpha
+                 LCD_OSDC_F0EN                          ,               // enable Foreground0    
+                // LCD_OSDC_F1EN,                                         // enable Foreground1    
+		
+                 .osd_ctrl = 0,                                         // disable ipu,          
+                 .rgb_ctrl = 0,                                                                  
+                 .bgcolor = 0x000000,                           // set background color Black    
+                 .colorkey0 = 0,                                        // disable colorkey
+                 .colorkey1 = 0,                                        // disable colorkey
+                 .alpha = 0xa0,                                         // alpha value
+                 .ipu_restart = 0x8000085d,                     // ipu restart
+                 .fg_change = FG_CHANGE_ALL,            // change all initially
+				 .fg0 = {32, 0, 0, 720, 576},   // bpp, x, y, w, h
+                 .fg1 = {32, 0, 0, 720, 576},       // bpp, x, y, w, h
+        },
+};
+struct jz4760lcd_info jz4760_info_hdmi_720p50 = {                            
+        .panel = {                                                     
+                .cfg = LCD_CFG_MODE_GENERIC_TFT | LCD_CFG_MODE_TFT_24BIT |
+                       LCD_CFG_NEWDES | LCD_CFG_RECOVER |                 
+                       LCD_CFG_PCP | LCD_CFG_HSP | LCD_CFG_VSP,           
+                .slcd_cfg = 0,                                            
+		.ctrl = LCD_CTRL_BST_32,                                  
+		//  width,height,freq,hsync,vsync,elw,blw,efw,bfw         
+                1280,720,50,40,5,440,220,20,5,
+	//	1280, 720, 50, 152, 15, 22, 200, 14, 1
+	//	1280,720,46,1,1,121,259,6,19,                       
+		//800,600,58,128,4,88,40,23,1,i
+		//1024,768,60,136,6,160,24,29,3,
+	},                                      
+        .osd = {                                
+                .osd_cfg =  LCD_OSDC_OSDEN      |               // Use OSD mode
+                 LCD_OSDC_ALPHAEN                       |               // enable alpha
+                 LCD_OSDC_F0EN                          ,               // enable Foreground0    
+                // LCD_OSDC_F1EN,                                         // enable Foreground1    
+		
+                 .osd_ctrl = 0,                                         // disable ipu,          
+                 .rgb_ctrl = 0,                                                                  
+                 .bgcolor = 0x000000,                           // set background color Black    
+                 .colorkey0 = 0,                                        // disable colorkey
+                 .colorkey1 = 0,                                        // disable colorkey
+		.alpha = 0xa0,                                         // alpha value
+		.ipu_restart = 0x8000085d,                     // ipu restart
+		.fg_change = FG_CHANGE_ALL,            // change all initially
+		.fg0 = {32, 0, 0, 1280, 720},   // bpp, x, y, w, h
+                 .fg1 = {32, 0, 0, 1280, 720},       // bpp, x, y, w, h
+        },
+};
+struct jz4760lcd_info jz4760_info_hdmi_720p60 = {                            
+        .panel = {                                                     
+                .cfg = LCD_CFG_MODE_GENERIC_TFT | LCD_CFG_MODE_TFT_24BIT |
+                       LCD_CFG_NEWDES | LCD_CFG_RECOVER |                 
+                       LCD_CFG_PCP | LCD_CFG_HSP | LCD_CFG_VSP,           
+                .slcd_cfg = 0,                                            
+		.ctrl = LCD_CTRL_BST_32,                                  
+		//  width,height,freq,hsync,vsync,elw,blw,efw,bfw         
+		1280,720,60,40,5,110,220,20,5,//74250000                  
+		//800,600,58,128,4,88,40,23,1,i
+		//1024,768,60,136,6,160,24,29,3,
+	},                                      
+        .osd = {                                
+                .osd_cfg =  LCD_OSDC_OSDEN      |               // Use OSD mode
+                 LCD_OSDC_ALPHAEN                       |               // enable alpha
+                 LCD_OSDC_F0EN                          ,               // enable Foreground0    
+                // LCD_OSDC_F1EN,                                         // enable Foreground1    
+		
+                 .osd_ctrl = 0,                                         // disable ipu,          
+                 .rgb_ctrl = 0,                                                                  
+                 .bgcolor = 0x000000,                           // set background color Black    
+                 .colorkey0 = 0,                                        // disable colorkey
+                 .colorkey1 = 0,                                        // disable colorkey
+                 .alpha = 0xa0,                                         // alpha value
+                 .ipu_restart = 0x8000085d,                     // ipu restart
+                 .fg_change = FG_CHANGE_ALL,            // change all initially
+		 .fg0 = {32, 0, 0, 1280, 720},   // bpp, x, y, w, h
+                 .fg1 = {32, 0, 0, 1280, 720},       // bpp, x, y, w, h
+        },
+};
+
+static void set_i2s_external_codec(void)
+{
+#if	defined(CONFIG_JZ4760_CYGNUS) || defined(CONFIG_JZ4760B_CYGNUS)
+	/* gpio defined based on CYGNUS board */
+        __gpio_as_func1(3*32 + 12); //blck
+        __gpio_as_func0(3*32 + 13); //sync
+        __gpio_as_func0(4*32 + 7);  //sd0
+        __gpio_as_func0(4*32 + 11); //sd1
+        __gpio_as_func0(4*32 + 12); //sd2
+        __gpio_as_func0(4*32 + 13); //sd3
+#endif
+
+
+        __i2s_external_codec();
+
+        __aic_select_i2s();
+        __i2s_select_i2s();
+        __i2s_as_master();
+
+        REG_AIC_I2SCR |= AIC_I2SCR_ESCLK;
+
+        __i2s_disable_record();
+        __i2s_disable_replay();
+        __i2s_disable_loopback();
+
+        REG_AIC_FR &= ~AIC_FR_TFTH_MASK;
+        REG_AIC_FR |= ((8) << AIC_FR_TFTH_BIT);
+        REG_AIC_FR &= ~AIC_FR_RFTH_MASK;
+        REG_AIC_FR |= ((8) << AIC_FR_RFTH_BIT);
+
+        __i2s_enable();
+
+}
+#endif
+
+
 struct jz4760lcd_info jz4760_info_tve = {
 	.panel = {
 		.cfg = LCD_CFG_TVEN | /* output to tve */
@@ -597,10 +766,10 @@ static void jz4760lcd_info_switch_to_TVE(int mode)
 		info->panel.fclk = TVE_FREQ_PAL;
 		w = ( osd_lcd->fg0.w < TVE_WIDTH_PAL )? osd_lcd->fg0.w:TVE_WIDTH_PAL;
 		h = ( osd_lcd->fg0.h < TVE_HEIGHT_PAL )?osd_lcd->fg0.h:TVE_HEIGHT_PAL;
-//		x = ((TVE_WIDTH_PAL - w) >> 2) << 1;
-//		y = ((TVE_HEIGHT_PAL - h) >> 2) << 1;
-		x = 0;
-		y = 0;
+		x = ((TVE_WIDTH_PAL - w) >> 2) << 1;
+		y = ((TVE_HEIGHT_PAL - h) >> 2) << 1;
+//		x = 0;
+//		y = 0;
 
 		info->osd.fg0.bpp = osd_lcd->fg0.bpp;
 		info->osd.fg0.x = x;
@@ -609,10 +778,10 @@ static void jz4760lcd_info_switch_to_TVE(int mode)
 		info->osd.fg0.h = h;
 		w = ( osd_lcd->fg1.w < TVE_WIDTH_PAL )? osd_lcd->fg1.w:TVE_WIDTH_PAL;
 		h = ( osd_lcd->fg1.h < TVE_HEIGHT_PAL )?osd_lcd->fg1.h:TVE_HEIGHT_PAL;
-//		x = ((TVE_WIDTH_PAL-w) >> 2) << 1;
-//		y = ((TVE_HEIGHT_PAL-h) >> 2) << 1;
-		x = 0;
-		y = 0;
+		x = ((TVE_WIDTH_PAL-w) >> 2) << 1;
+		y = ((TVE_HEIGHT_PAL-h) >> 2) << 1;
+//		x = 0;
+//		y = 0;
 
 		info->osd.fg1.bpp = 32;	/* use RGB888 in TVE mode*/
 		info->osd.fg1.x = x;
@@ -709,33 +878,87 @@ static int jz4760fb_ioctl(struct fb_info *info, unsigned int cmd, unsigned long
 
 		break;
 
-#ifdef CONFIG_FB_JZ4760_TVE
 	case FBIO_MODE_SWITCH:
 		D("FBIO_MODE_SWITCH");
 		switch (arg) {
+#ifdef CONFIG_FB_JZ4760_TVE
 			case PANEL_MODE_TVE_PAL: 	/* switch to TVE_PAL mode */
 			case PANEL_MODE_TVE_NTSC: 	/* switch to TVE_NTSC mode */
 				jz4760lcd_info_switch_to_TVE(arg);
 				jz4760tve_init(arg); /* tve controller init */
 				udelay(100);
+				cpm_start_clock(CGM_TVE);
 				jz4760tve_enable_tve();
 				/* turn off lcd backlight */
 				screen_off();
 				break;
+#endif
+#if defined(CONFIG_JZ4760_HDMI_DISPLAY)  
+ 			case PANEL_MODE_HDMI_480P:
+   				set_i2s_external_codec();
+				/* turn off TVE, turn off DACn... */
+				//jz4760tve_disable_tve();
+				jz4760_lcd_info =&jz4760_info_hdmi_480p ;
+				/* turn on lcd backlight */
+				screen_off();
+				break;
+
+			case PANEL_MODE_HDMI_576P:
+   				set_i2s_external_codec();
+				/* turn off TVE, turn off DACn... */
+				//jz4760tve_disable_tve();
+				jz4760_lcd_info =&jz4760_info_hdmi_576p ;
+				/* turn on lcd backlight */
+				screen_off();
+				break;
+
+			case PANEL_MODE_HDMI_720P50:
+#if defined(CONFIG_SOC_JZ4760B)
+				REG_LCD_PCFG = 0xc0000888;
+                                REG_GPIO_PXSLC(2) = 0;
+                                REG_GPIO_PXDS1S(2) |= 1 << 8;
+                                REG_GPIO_PXDS0S(2) = 0x0fffffff;
+
+#endif
+				set_i2s_external_codec();
+				/* turn off TVE, turn off DACn... */
+				//jz4760tve_disable_tve();
+				jz4760_lcd_info =&jz4760_info_hdmi_720p50 ;
+				/* turn on lcd backlight */
+				screen_off();
+				break;
+
+			case PANEL_MODE_HDMI_720P60:
+#if defined(CONFIG_SOC_JZ4760B)
+				REG_LCD_PCFG = 0xc0000888;
+                                REG_GPIO_PXSLC(2) = 0;
+                                REG_GPIO_PXDS1S(2) |= 1 << 8;
+                                REG_GPIO_PXDS0S(2) = 0x0fffffff;
+#endif
+   				set_i2s_external_codec();
+				/* turn off TVE, turn off DACn... */
+				//jz4760tve_disable_tve();
+				jz4760_lcd_info =&jz4760_info_hdmi_720p60 ;
+				/* turn on lcd backlight */
+				screen_off();
+				break;
+#endif	//CONFIG_JZ4760_HDMI_DISPLAY
 			case PANEL_MODE_LCD_PANEL: 	/* switch to LCD mode */
 			default :
 				/* turn off TVE, turn off DACn... */
+#ifdef CONFIG_FB_JZ4760_TVE
 				jz4760tve_disable_tve();
+				cpm_stop_clock(CGM_TVE);
+#endif
 				jz4760_lcd_info = &jz4760_lcd_panel;
 				/* turn on lcd backlight */
 				screen_on();
 				break;
 		}
-
 		jz4760fb_deep_set_mode(jz4760_lcd_info);
-
 		break;
 
+#ifdef CONFIG_FB_JZ4760_TVE
 	case FBIO_GET_TVE_MODE:
 		D("fbio get TVE mode\n");
 		if (copy_to_user(argp, jz4760_tve_info, sizeof(struct jz4760tve_info)))
@@ -1169,9 +1392,12 @@ static int jz4760fb_map_smem(struct lcd_cfb_info *cfb)
 	needroom += ((w * bpp + 7) >> 3) * h;
 #endif // two layer
 
-	for (page_shift = 0; page_shift < 12; page_shift++)
+	for (page_shift = 0; page_shift < 13; page_shift++)
 		if ((PAGE_SIZE << page_shift) >= needroom)
 			break;
+#if defined(CONFIG_JZ4760_HDMI_DISPLAY)
+	page_shift = 11;
+#endif
 	lcd_palette = (unsigned char *)__get_free_pages(GFP_KERNEL, 0);
 	lcd_frame0 = (unsigned char *)__get_free_pages(GFP_KERNEL, page_shift);
 
@@ -1738,14 +1964,17 @@ static void jz4760fb_change_clock( struct jz4760lcd_info * lcd_info )
 		pclk = val * (lcd_info->panel.w*3 + lcd_info->panel.hsw + lcd_info->panel.elw + lcd_info->panel.blw) * (lcd_info->panel.h + lcd_info->panel.vsw + lcd_info->panel.efw + lcd_info->panel.bfw); /* Pixclk */
 	}
 
+#ifdef CONFIG_FB_JZ4760_TVE
 	/********* In TVE mode PCLK = 27MHz ***********/
 	if ( lcd_info->panel.cfg & LCD_CFG_TVEN ) { 		/* LCDC output to TVE */
+//	   	__cpm_stop_tve();
+		OUTREG32(CPM_CPPCR0,((90<< CPPCR0_PLLM_LSB)|(2<<CPPCR0_PLLN_LSB)|(1<<CPPCR0_PLLOD_LSB)|(0x20<<CPPCR0_PLLST_LSB)|CPPCR0_PLLEN));	
 		REG_CPM_LPCDR  |= LPCDR_LTCS;
 		pclk = 27000000;
 		val = __cpm_get_pllout2() / pclk; /* pclk */
 		val--;
 		__cpm_set_pixdiv(val);
-
+//		__cpm_start_tve();
 
 		D("REG_CPM_LPCDR = 0x%08x\n", REG_CPM_LPCDR);
 #if 0
@@ -1764,7 +1993,9 @@ static void jz4760fb_change_clock( struct jz4760lcd_info * lcd_info )
 
 		REG_CPM_CPCCR |= CPCCR_CE ; /* update divide */
 	}
-	else { 		/* LCDC output to  LCD panel */
+	else 
+#endif
+	{ 		/* LCDC output to  LCD panel */
 		val = __cpm_get_pllout2() / pclk; /* pclk */
 		val--;
 		D("ratio: val = %d\n", val);
@@ -1786,6 +2017,7 @@ static void jz4760fb_change_clock( struct jz4760lcd_info * lcd_info )
 		__cpm_set_ldiv( val );
 #endif
 #endif
+		__cpm_select_pixclk_lcd();
 		REG_CPM_CPCCR |= CPCCR_CE ; /* update divide */
 
 	}
diff --git a/drivers/video/jz4760_lcd.h b/drivers/video/jz4760_lcd.h
index 9ee7c1cc990..21be80cc76c 100644
--- a/drivers/video/jz4760_lcd.h
+++ b/drivers/video/jz4760_lcd.h
@@ -102,7 +102,7 @@ struct jz4760lcd_info {
  */
 /* AUO */
 #if defined(CONFIG_JZ4760_LCD_AUO_A043FL01V2)
-#if defined(CONFIG_JZ4760_LEPUS) /* board pavo */
+#if defined(CONFIG_JZ4760_LEPUS) || defined(CONFIG_JZ4760B_LEPUS)/* board pavo */
 	#define SPEN		(32*1+29)       /*LCD_CS*/
 	#define SPCK		(32*1+28)       /*LCD_SCL*/
 	#define SPDA		(32*1+21)       /*LCD_SDA*/
@@ -220,7 +220,7 @@ struct jz4760lcd_info {
 /* TRULY_TFTG320240DTSW */
 #if defined(CONFIG_JZ4760_LCD_TRULY_TFTG320240DTSW_16BIT) || defined(CONFIG_JZ4760_LCD_TRULY_TFTG320240DTSW_18BIT)
 
-#if defined(CONFIG_JZ4760_LEPUS)
+#if defined(CONFIG_JZ4760_LEPUS) || defined(CONFIG_JZ4760B_LEPUS)
 #define LCD_RESET_PIN	(32*5+10)// LCD_REV, GPF10
 #else
 #error "Define LCD_RESET_PIN on your board"
@@ -249,7 +249,7 @@ do { \
 #define PANEL_MODE 0x00		/* RGB Dummy */
 #endif
 
-#if defined(CONFIG_JZ4760_LEPUS) /* board LEPUS */
+#if defined(CONFIG_JZ4760_LEPUS) || defined(CONFIG_JZ4760B_LEPUS)/* board LEPUS */
 	#define SPEN	(32*2+29)       //GPB29
 	#define SPCK	(32*2+28)       //GPB28
 	#define SPDA	(32*2+21)       //GPB21
@@ -338,13 +338,19 @@ do { \
 #define MODE 0xc9		/* 8bit serial RGB */
 #endif
 
-#if defined(CONFIG_JZ4760_LEPUS) /* board FuWa */
+#if defined(CONFIG_JZ4760_LEPUS) || defined(CONFIG_JZ4760B_LEPUS)/* board FuWa */
 
 	#define SPEN		(32*2+29)       /*LCD_CS*/
 	#define SPCK		(32*2+28)       /*LCD_SCL*/
 	#define SPDA		(32*2+21)       /*LCD_SDA*/
 	#define LCD_RET 	(32*5+6)       /*LCD_DISP_N use for lcd reset*/
 
+#elif CONFIG_JZ4760_CYGNUS /* board cygnus */
+        #define SPEN            (32*3+13)       /*LCD_CS GPD13*/
+        #define SPCK            (32*4+13)       /*LCD_SCL GPE13*/
+        #define SPDA            (32*1+29)       /*LCD_SDA GPB29*/
+        #define LCD_DISP_N      (32*4+11)       /*LCD_DISP_N use for lcd reset*/
+        #define LCD_RET         (32*4+12)       /*LCD_RESET use for lcd reset*/
 #else
 #error "driver/video/Jzlcd.h, please define SPI pins on your board."
 #endif
@@ -443,7 +449,7 @@ do { \
 #endif	/* CONFIG_JZ4760_LCD_FOXCONN_PT035TN01 or CONFIG_JZ4760_LCD_INNOLUX_PT035TN01_SERIAL */
 
 #if defined(CONFIG_JZ4760_LCD_TOPPOLY_TD043MGEB1)
-#if defined(CONFIG_JZ4760_LEPUS) /* board pavo */
+#if defined(CONFIG_JZ4760_LEPUS) || defined(CONFIG_JZ4760B_LEPUS)/* board pavo */
 	#define SPEN		(32*1+29)       /*LCD_CS*/
 	#define SPCK		(32*1+28)       /*LCD_SCL*/
 	#define SPDA		(32*1+21)       /*LCD_SDA*/
@@ -790,7 +796,7 @@ static void SlcdInit(void)
 
 }
 
-#if defined(CONFIG_JZ4760_LEPUS)
+#if defined(CONFIG_JZ4760_LEPUS) || defined(CONFIG_JZ4760B_LEPUS)
 #define PIN_CS_N 	(32*1+29)	/* a low voltage */
 #define PIN_RD_N 	(32*2+9)	/* LCD_DE: GP C9, a high voltage */
 #define PIN_RESET_N 	(32*5+10)	/* LCD_REV GP F10 */
@@ -844,7 +850,7 @@ static void SlcdInit(void)
 #define __lcd_display_pin_init()
 #define __lcd_display_on()
 #define __lcd_display_off()
-#elif defined(CONFIG_JZ4760_LEPUS)/* board lepus */
+#elif defined(CONFIG_JZ4760_LEPUS) || defined(CONFIG_JZ4760B_LEPUS)/* board lepus */
 #define __lcd_display_pin_init() \
 do { \
 	__gpio_as_output(GPIO_LCD_VCC_EN_N);	 \
diff --git a/drivers/video/jz4760_tve.c b/drivers/video/jz4760_tve.c
index 07864fa8b58..e784efb8cd2 100644
--- a/drivers/video/jz4760_tve.c
+++ b/drivers/video/jz4760_tve.c
@@ -19,7 +19,7 @@
 #include "jz4760_tve.h"
 
 struct jz4760tve_info jz4760_tve_info_PAL = {
-	.ctrl = (4 << TVE_CTRL_YCDLY_BIT) | TVE_CTRL_SYNCT | TVE_CTRL_PAL | TVE_CTRL_SWRST,	/* PAL, SVIDEO */
+	.ctrl = TVE_CTRL_ECVBS | (4 << TVE_CTRL_YCDLY_BIT) | TVE_CTRL_SYNCT | TVE_CTRL_PAL | TVE_CTRL_SWRST,	/* PAL, SVIDEO */
 	.frcfg = (23 << TVE_FRCFG_L1ST_BIT) | (625 << TVE_FRCFG_NLINE_BIT),
 	.slcfg1 = (800<<TVE_SLCFG1_WHITEL_BIT) | (282<<TVE_SLCFG1_BLACKL_BIT),
 	.slcfg2 = (296<<TVE_SLCFG2_VBLANKL_BIT) | (240<<TVE_SLCFG2_BLANKL_BIT),
@@ -36,7 +36,7 @@ struct jz4760tve_info jz4760_tve_info_PAL = {
 };
 
 struct jz4760tve_info jz4760_tve_info_NTSC = {
-	.ctrl = (4 << TVE_CTRL_YCDLY_BIT) | TVE_CTRL_SWRST,	/* NTSC, SVIDEO */
+	.ctrl = TVE_CTRL_ECVBS | (4 << TVE_CTRL_YCDLY_BIT) | TVE_CTRL_SWRST,	/* NTSC, SVIDEO */
 	.frcfg = (21 << TVE_FRCFG_L1ST_BIT) | (525 << TVE_FRCFG_NLINE_BIT),
 	.slcfg1 = (800<<TVE_SLCFG1_WHITEL_BIT) | (282<<TVE_SLCFG1_BLACKL_BIT),
 	.slcfg2 = (296<<TVE_SLCFG2_VBLANKL_BIT) | (240<<TVE_SLCFG2_BLANKL_BIT),
diff --git a/drivers/video/jz4810_aosd.c b/drivers/video/jz4810_aosd.c
new file mode 100644
index 00000000000..708b2a1e06c
--- /dev/null
+++ b/drivers/video/jz4810_aosd.c
@@ -0,0 +1,603 @@
+/*
+ * linux/drivers/video/jz4810_lcd.c -- Ingenic Jz4810 LCD frame buffer device
+ *
+ * Copyright (C) 2005-2008, Ingenic Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/*
+ * --------------------------------
+ * NOTE:
+ * This LCD driver support TFT16 TFT32 LCD, not support STN and Special TFT LCD
+ * now.
+ * 	It seems not necessory to support STN and Special TFT.
+ * 	If it's necessary, update this driver in the future.
+ * 	<Wolfgang Wang, Jun 10 2008>
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/string.h>
+#include <linux/mm.h>
+#include <linux/tty.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/fb.h>
+#include <linux/init.h>
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+#include <linux/pm.h>
+
+#include <asm/irq.h>
+#include <asm/pgtable.h>
+#include <asm/system.h>
+#include <asm/uaccess.h>
+#include <asm/processor.h>
+#include <asm/jzsoc.h>
+
+#include "jz4810_aosd.h"
+
+MODULE_DESCRIPTION("Jz4810 ALPHA OSD driver");
+MODULE_AUTHOR("lltang, <lltang@ingenic.cn>");
+MODULE_LICENSE("GPL");
+
+#define D(fmt, args...) \
+//	printk(KERN_ERR "%s(): "fmt"\n", __func__, ##args)
+
+#define E(fmt, args...) \
+	printk(KERN_ERR "%s(): "fmt"\n", __func__, ##args)
+
+#define JZ_AOSD_DEBUG 1
+
+#define AOSD_MAJOR 241
+static int aosd_major = AOSD_MAJOR;
+struct aosd_dev{
+	struct cdev cdev;
+	struct jz4810_aosd_info *aosd_info;
+};
+
+struct aosd_dev *aosd_devp;
+int irq_flag = 0;
+static int jz4810_alloc_aosd_info(void)
+{
+	aosd_devp->aosd_info = kmalloc(sizeof(struct jz4810_aosd_info) , GFP_KERNEL);
+
+	if (!aosd_devp->aosd_info)
+		return -1;
+
+	memset(aosd_devp->aosd_info, 0, sizeof(struct jz4810_aosd_info) );
+	return 0;
+}
+
+int aosd_open(struct inode *inode,struct file *filp)
+{
+//	filp->private_data = aosd_devp;
+	return 0;
+}
+
+int aosd_release(struct inode *inode,struct file *filp)
+{
+	return 0;
+}
+
+/* The following routine is only for test */
+
+#if JZ_AOSD_DEBUG
+static void print_aosd_registers(void)	/* debug */
+{
+	/* LCD Controller Resgisters */
+	printk("REG_AOSD_ADDR0:\t0x%08x\n", REG_AOSD_ADDR0);
+	printk("REG_AOSD_ADDR1:\t0x%08x\n", REG_AOSD_ADDR1);
+	printk("REG_AOSD_ADDR2:\t0x%08x\n", REG_AOSD_ADDR2);
+	printk("REG_AOSD_ADDR3:\t0x%08x\n", REG_AOSD_ADDR3);
+	printk("REG_AOSD_WADDR:\t0x%08x\n", REG_AOSD_WADDR);
+	printk("REG_AOSD_ADDRLEN:\t0x%08x\n", REG_AOSD_ADDRLEN);
+	printk("REG_AOSD_ALPHA_VALUE:\t0x%08x\n", REG_AOSD_ALPHA_VALUE);
+	printk("REG_AOSD_CTRL:\t0x%08x\n",REG_AOSD_CTRL);
+	printk("REG_AOSD_INT:\t0x%08x\n", REG_AOSD_INT);
+	printk("REG_AOSD_CLK_GATE:\t0x%08x\n", REG_AOSD_CLK_GATE);	
+
+	printk("REG_COMPRESS_OFFSIZE:\t0x%08x\n", REG_COMPRESS_OFFSIZE);
+	printk("REG_COMPRESS_FRAME_SIZE:\t0x%08x\n", REG_COMPRESS_FRAME_SIZE);
+	printk("REG_COMPRESS_CTRL:\t0x%08x\n", REG_COMPRESS_CTRL);
+	printk("REG_COMPRESS_RATIO:\t0x%08x\n", REG_COMPRESS_RATIO);
+	printk("REG_COMPRESS_OFFSET:\t0x%08x\n", REG_COMPRESS_OFFSET);
+	printk("==================================\n");
+
+}
+#else
+#define print_aosd_registers()
+#endif
+
+static unsigned char *addr0,*addr1,*addr2,*addr3;
+
+static void jz4810_start_alpha_blending(void);
+static void jz4810_aosd_set_mode(struct jz4810_aosd_info *jz4810_oa_info);
+static void jz4810_compress_set_mode(struct jz4810_aosd_info *info);
+static void jz4810_start_compress(void);
+
+static int aosd_ioctl(struct inode *inodep, struct file *filep, unsigned int cmd, unsigned long arg)
+{
+	int ret = 0;
+	void __user *argp = (void __user *)arg;
+
+	switch (cmd) {
+	case ALPHA_OSD_PRINT:
+		print_aosd_registers();
+		break;
+
+
+	case ALPHA_OSD_START:
+		jz4810_start_alpha_blending();
+		break;
+
+	case ALPHA_OSD_GET_INFO:
+		if (copy_to_user(argp, aosd_devp->aosd_info, sizeof(struct jz4810_aosd_info)))
+			return -EFAULT;
+
+		break;
+
+	case ALPHA_OSD_SET_MODE:
+		D("osd alpha set mode\n");
+
+		if (copy_from_user(aosd_devp->aosd_info, argp, sizeof(struct jz4810_aosd_info)))
+			return -EFAULT;
+
+		jz4810_aosd_set_mode(aosd_devp->aosd_info);
+
+		break;
+
+	case COMPRESS_SET_MODE:
+		D("compress set mode\n");
+
+		if (copy_from_user(aosd_devp->aosd_info, argp, sizeof(struct jz4810_aosd_info)))
+			return -EFAULT;
+
+		jz4810_compress_set_mode(aosd_devp->aosd_info);
+
+		break;
+
+	case COMPRESS_START:
+		jz4810_start_compress();
+		break;
+
+
+	default:
+		printk("%s, unknown command(0x%x)", __FILE__, cmd);
+		break;
+	}
+
+	return ret;
+}
+
+static int aosd_mmap(struct file *filep, struct vm_area_struct *vma)
+{
+	struct jz4810_aosd_info *info = aosd_devp->aosd_info;
+	unsigned long start;
+	unsigned long off;
+	u32 len;
+
+//	printk("%s, %s, %d\n", __FILE__, __FUNCTION__, __LINE__);
+	off = vma->vm_pgoff << PAGE_SHIFT;
+	//fb->fb_get_fix(&fix, PROC_CONSOLE(info), info);
+
+	start = info->smem_start;
+	len = PAGE_ALIGN((start & ~PAGE_MASK) + info->addr_len);
+	start &= PAGE_MASK;
+
+	if ((vma->vm_end - vma->vm_start + off) > len)
+		return -EINVAL;
+	off += start;
+
+	vma->vm_pgoff = off >> PAGE_SHIFT;
+	vma->vm_flags |= VM_IO;
+	vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);	/* Uncacheable */
+
+#if 1
+ 	pgprot_val(vma->vm_page_prot) &= ~_CACHE_MASK;
+ 	pgprot_val(vma->vm_page_prot) |= _CACHE_UNCACHED;		/* Uncacheable */
+//	pgprot_val(vma->vm_page_prot) |= _CACHE_CACHABLE_NONCOHERENT;	/* Write-Back */
+#endif
+
+	if (io_remap_pfn_range(vma, vma->vm_start, off >> PAGE_SHIFT,
+			       vma->vm_end - vma->vm_start,
+			       vma->vm_page_prot)) {
+		return -EAGAIN;
+	}
+	return 0;
+}
+
+/*
+  Map 4 alpha osd memory ;added by lltang
+*/
+static int jz4810_map_osd_mem(struct jz4810_aosd_info *aosd_info)
+{
+	unsigned long page;
+	unsigned int page_shift,needroom_osd, needroom;
+
+	needroom = ((480*32) >> 3) * 272 ;
+#if defined(CONFIG_JZ4810_AOSD)
+	needroom_osd  = needroom * 4;
+#else
+	needroom_osd  = needroom * 2;
+#endif
+	page_shift = get_order(needroom_osd);
+	printk("the PAGE_SIZE -> %x,the page_shift -> %d\n",PAGE_SIZE, page_shift);
+
+	addr0 = (unsigned char *)__get_free_pages(GFP_KERNEL, page_shift);
+	if(!addr0)
+		return -ENOMEM;
+
+	memset((void *)addr0, 0, PAGE_SIZE << page_shift); 
+	addr1 = addr0 + needroom;
+
+	REG_AOSD_ADDR0 = virt_to_phys((void *)addr0); 
+	REG_AOSD_ADDR1 = virt_to_phys((void *)addr1); 
+#if defined(CONFIG_JZ4810_AOSD)
+	addr2 = addr0 + needroom * 2;
+	addr3 = addr0 + needroom * 3;
+
+	REG_AOSD_ADDR2 = virt_to_phys((void *)addr2); 
+	REG_AOSD_ADDR3 = virt_to_phys((void *)addr3); 
+#endif
+
+	for (page = (unsigned long)addr0;
+	     page < PAGE_ALIGN((unsigned long)addr0 + (PAGE_SIZE<<page_shift));
+	     page += PAGE_SIZE) {
+		SetPageReserved(virt_to_page((void*)page));
+	}
+
+	aosd_info->addr0 = virt_to_phys((void *)addr0);
+	aosd_info->smem_start = virt_to_phys((void *)addr0);
+//	aosd_info->addr_len = (PAGE_SIZE << page_shift); /* page_shift/2 ??? */
+	aosd_info->addr_len = needroom_osd; /* page_shift/2 ??? */
+	aosd_info->addr0_base =
+		(unsigned char *)(((unsigned int)addr0&0x1fffffff) | 0xa0000000);
+
+	if (!aosd_info->addr0_base) {
+		printk("%s: unable to map aosd memory\n",__func__);
+		return -ENOMEM;
+	}
+
+	printk("addr0 = %p addr1 = %p addr2 = %p, addr3 = %p\n", addr0, addr1, addr2, addr3);
+
+	return 0;
+}
+
+
+static void jz4810_unmap_osd_mem(struct jz4810_aosd_info *aosd_info)
+{
+
+	struct page * map = NULL;
+	unsigned char *tmp;
+	unsigned int page_shift, needroom, needroom_osd;
+
+
+	if (aosd_info && aosd_info->addr0_base) {
+		iounmap(aosd_info->addr0_base);
+		aosd_info->addr0_base = NULL;
+		release_mem_region(aosd_info->addr0,aosd_info->addr_len);
+	}
+
+	needroom = ((480*32) >> 3) * 272; 
+#if defined(CONFIG_JZ4810_AOSD)
+	needroom_osd  = needroom * 4;
+#else
+	needroom_osd  = needroom*2 ;
+#endif
+	page_shift = get_order(needroom_osd);
+
+
+	for (page_shift = 0; page_shift < 12; page_shift++)
+		if ((PAGE_SIZE << page_shift) >= needroom_osd)
+			break;
+
+	if (addr0) {
+		for (tmp=(unsigned char *)addr0;
+		     tmp < addr0 + (PAGE_SIZE << page_shift);
+		     tmp += PAGE_SIZE) {
+			map = virt_to_page(tmp);
+			clear_bit(PG_reserved, &map->flags);
+		}
+		free_pages((int)addr0, page_shift);
+	}
+
+}
+
+static void jz4810_start_alpha_blending(void)
+{
+//	print_aosd_registers();
+	while(!(REG_AOSD_CTRL & AOSD_CTRL_FRM_END)) ;
+	printk("all frames' alpha blending is finished\n");
+	__osd_alpha_start();
+}
+
+static void jz4810_start_compress(void)
+{
+#if 0
+	int i;
+	int *test=(int*)addr0;
+	for(i=0;i<480*32/32*272;i++){
+		if(i%10 == 0)
+			printk("\n");
+		printk("%x\t",*(test+i));
+	}
+#endif
+
+//	print_aosd_registers();
+
+	while(!(REG_COMPRESS_CTRL & COMPRESS_CTRL_COMP_END));
+	aosd_devp->aosd_info->compress_done = 0;
+	printk("frame compress is finished and send to frame buffer\n");
+	__compress_start();
+}
+
+static void jz4810_compress_set_mode(struct jz4810_aosd_info *info)
+{
+	int n;
+
+/*SET SCR AND DES ADDR*/
+	REG_AOSD_ADDR0 = info->addr0;//virt_to_phys((void *)addr0); //
+        REG_COMPRESS_DES_ADDR = info->waddr;
+
+/*SET DES OFFSIZE */
+	REG_COMPRESS_OFFSIZE = (info->width+1) * 4; //des byte
+
+/*SET SCR OFFSET*/
+	REG_COMPRESS_OFFSET = info->width * 4; //scr byte
+
+/*SET SIZE*/
+	REG_COMPRESS_FRAME_SIZE = (info->width & 0xffff) | ((info->height & 0xffff) << 16);
+
+/* SET CTRL*/
+	if(info->without_alpha)
+		REG_COMPRESS_CTRL = (COMPRESS_CTRL_WITHOUT_ALPHA | COMPRESS_CTRL_INT_MASK | COMPRESS_CTRL_COMP_ENABLE); 
+	else
+		REG_COMPRESS_CTRL = (COMPRESS_CTRL_WITH_ALPHA | COMPRESS_CTRL_INT_MASK | COMPRESS_CTRL_COMP_ENABLE); 		
+}
+
+static void jz4810_aosd_set_mode(struct jz4810_aosd_info *info)
+{
+#if 1
+	printk("%s,info->waddr \t%x,info->width %d\t,info->height %d\t,info->alpha_value %x\t,\n",__func__,info->waddr,info->width,info->height,info->alpha_value);
+
+#endif
+
+	REG_AOSD_WADDR = info->waddr;
+	REG_AOSD_ADDRLEN = info->width * info->height; 
+	REG_AOSD_ALPHA_VALUE = info->alpha_value;
+
+	printk("REG_AOSD_WADDR: %08x\n",REG_AOSD_WADDR);
+	if(info->frmlv == 4){
+		printk("info->frmlv == 4\n");
+		REG_AOSD_CTRL = (AOSD_ALPHA_ENABLE | AOSD_CTRL_INT_MAKS |  AOSD_CTRL_FRMLV_4);
+	}else if(info->frmlv == 3){
+		printk("info->frmlv == 3\n");
+		REG_AOSD_CTRL = (AOSD_ALPHA_ENABLE | AOSD_CTRL_INT_MAKS |  AOSD_CTRL_FRMLV_3);
+	}else if(info->frmlv == 2){
+		printk("info->frmlv == 2\n");
+		REG_AOSD_CTRL = (AOSD_ALPHA_ENABLE | AOSD_CTRL_INT_MAKS |  AOSD_CTRL_FRMLV_2);
+	}else{
+		printk("frmlv default value is 0b01,now the frmlv < 2\n");
+		return;
+	}
+
+	REG_AOSD_CTRL &= ~AOSD_CTRL_CHANNEL_LEVEL_MASK;
+	REG_AOSD_CTRL |= (info->order << AOSD_CTRL_CHANNEL_LEVEL_BIT);
+
+	REG_AOSD_CTRL &= ~AOSD_CTRL_ALPHA_MODE_MASK;
+	REG_AOSD_CTRL |= (info->alpha_mode << AOSD_CTRL_ALPHA_MODE_BIT) ;
+
+	REG_AOSD_CTRL &= ~AOSD_CTRL_FORMAT_MODE_MASK;
+	if(info->bpp == 15)
+		REG_AOSD_CTRL |= AOSD_CTRL_RGB555_FORMAT_MODE;
+	else if(info->bpp == 16)
+		REG_AOSD_CTRL |= AOSD_CTRL_RGB565_FORMAT_MODE;
+	else if(info->bpp == 24)
+		REG_AOSD_CTRL |= AOSD_CTRL_RGB8888_FORMAT_MODE;
+	else
+		printk("Sorry , we only support RGB555 RGB565 RGB8888!!!!!!\n");
+
+}
+
+static irqreturn_t jz4810_interrupt_handler(int irq, void *dev_id)
+{
+	unsigned int state;
+	int cnt = 0;
+	
+	state = REG_AOSD_INT;
+	D("In the lcd interrupt handler, state=0x%x\n", state);
+
+	if (state & AOSD_INT_COMPRESS_END){
+		printk("state & AOSD_INT_COMPRESS_END->OK!!!!!!!!!!!!!!!!!!!!\n");
+//		print_aosd_registers();
+		aosd_devp->aosd_info->compress_done = 1;
+		REG_AOSD_ADDR0 = virt_to_phys((void *)addr0);; 
+		REG_AOSD_INT = state & AOSD_INT_COMPRESS_END;
+	}
+
+	if (state & AOSD_INT_AOSD_END) {
+		printk("state & AOSD_INT_AOSD_END\n");
+
+		REG_AOSD_INT = state & AOSD_INT_AOSD_END;
+		REG_AOSD_ADDR0 = virt_to_phys((void *)
+addr0); 
+		REG_AOSD_ADDR1 = virt_to_phys((void *)addr1); 
+		REG_AOSD_ADDR2 = virt_to_phys((void *)addr2); 
+		REG_AOSD_ADDR3 = virt_to_phys((void *)addr3); 
+		aosd_devp->aosd_info->compress_done = 1;
+	}
+
+	return IRQ_HANDLED;
+}
+
+static const struct file_operations aosd_fops = {
+	.owner           =  THIS_MODULE,
+	.open            =  aosd_open,
+	.release         =  aosd_release,
+	.ioctl           =  aosd_ioctl,
+	.mmap            =  aosd_mmap,
+};
+
+static void aosd_setup_cdev(struct aosd_dev *dev,int index)
+{
+	int err,devno = MKDEV(aosd_major,index);
+
+	cdev_init(&dev->cdev, &aosd_fops);
+	dev->cdev.owner = THIS_MODULE;
+	dev->cdev.ops = &aosd_fops;
+	err = cdev_add(&dev->cdev,devno,1);
+	if(err)
+		printk(KERN_NOTICE "Error %d adding %d",err,index);
+}
+
+#ifdef CONFIG_PM
+/*
+ * Suspend the AOSD.
+ */
+static int jz4810_aosd_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	return 0;
+}
+
+/*
+ * Resume the AOSD.
+ */
+static int jz4810_aosd_resume(struct platform_device *pdev)
+{
+	return 0;
+}
+
+#else
+#define jz4810_aosd_suspend      NULL
+#define jz4810_aosd_resume       NULL
+#endif /* CONFIG_PM */
+
+static int __devinit jz4810_aosd_probe(struct platform_device *dev)
+{
+	struct jz4810_aosd_info *aosd_info;
+	struct resource *r;
+	int ret,irq;
+	dev_t devno = MKDEV(aosd_major,0);
+
+#if defined(CONFIG_JZ4810_AOSD) && defined(CONFIG_JZ4810_COMPRESS)
+	printk("you can not use aosd and compress at the  same time!!!!\n");
+	return -1;
+#endif
+	if(devno){
+		ret = register_chrdev_region(devno,1,"aosd");
+	}else{
+		ret = alloc_chrdev_region(&devno,0 ,1,"aosd");
+		aosd_major = MAJOR(devno);
+	}
+	if(ret < 0){
+		printk("register_chrdev_region failed\n");
+		return ret;
+	}
+
+	aosd_devp = kmalloc(sizeof(struct aosd_dev),GFP_KERNEL);
+	if(!aosd_devp){
+		printk("kmalloc aosd_dev failed\n");
+		ret = -ENOMEM;
+		goto failed1;
+	}
+
+	memset(aosd_devp,0,sizeof(struct aosd_dev));
+	aosd_setup_cdev(aosd_devp,0);
+
+	ret = jz4810_alloc_aosd_info();
+	if(-1 == ret)
+	{
+		printk("alloc aosd info failed\n");
+		ret = -ENOMEM;
+		goto failed2;
+	}
+
+	r = platform_get_resource(dev, IORESOURCE_MEM, 0);
+	irq = platform_get_irq(dev, 0);
+	if (!r || irq < 0){
+		printk("platform get resource or irq  failed\n");
+		ret = -ENXIO;
+		goto failed4;
+	}
+
+	r = request_mem_region(r->start, r->end - r->start + 1, "oasd_compress");
+	if (!r){
+		printk("request_mem_region failed\n");
+		ret = -EBUSY;
+		goto failed4;
+	}
+
+	/* aosd and compress use the same IRQ number */
+	if (request_irq(IRQ_AOSD, jz4810_interrupt_handler, IRQF_DISABLED,"oasd_compress", 0)) {
+		printk("Faield to request ALPHA OSD IRQ.\n");
+		ret = -EBUSY;
+		goto failed4;
+	}
+#if defined(CONFIG_JZ4810_COMPRESS)
+	REG_COMPRESS_CTRL = (COMPRESS_CTRL_INT_MASK | COMPRESS_CTRL_COMP_ENABLE); /* enable compress and enable finished interrupt */
+#elif defined(CONFIG_JZ4810_AOSD)
+	REG_AOSD_CTRL = (AOSD_ALPHA_ENABLE | AOSD_CTRL_INT_MAKS);
+#endif
+	REG_AOSD_CLK_GATE = AOSD_CLK_GATE_EN;
+	ret = jz4810_map_osd_mem(aosd_devp->aosd_info);
+	if (ret)
+		goto failed5;
+	printk("jz-aosd install!!! ######################################################\n");
+	return 0;
+
+failed5:
+	free_irq(IRQ_AOSD,0);
+failed4:
+
+failed3:
+	kfree(aosd_devp->aosd_info);
+failed2:
+	kfree(aosd_devp);
+	cdev_del(&aosd_devp->cdev);
+failed1:
+	unregister_chrdev_region(devno,1);
+
+	return ret;
+}
+
+static int __devexit jz4810_aosd_remove(struct platform_device *pdev)
+{
+	cdev_del(&aosd_devp->cdev);
+	kfree(aosd_devp);
+	kfree(aosd_devp->aosd_info);
+	unregister_chrdev_region(MKDEV(aosd_major,0),1);
+	return 0;
+}
+
+static struct platform_driver jz4810_aosd_driver = {
+	.probe	= jz4810_aosd_probe,
+	.remove = jz4810_aosd_remove,
+	.suspend = jz4810_aosd_suspend,
+	.resume = jz4810_aosd_resume,
+	.driver = {
+		.name = "jz-aosd",
+		.owner = THIS_MODULE,
+	},
+};
+
+static int __init jz4810_aosd_init(void)
+{
+	return platform_driver_register(&jz4810_aosd_driver);
+}
+
+static void __exit jz4810_aosd_cleanup(void)
+{
+	platform_driver_unregister(&jz4810_aosd_driver);
+}
+
+module_init(jz4810_aosd_init);
+module_exit(jz4810_aosd_cleanup);
diff --git a/drivers/video/jz4810_aosd.h b/drivers/video/jz4810_aosd.h
new file mode 100644
index 00000000000..8197b26feed
--- /dev/null
+++ b/drivers/video/jz4810_aosd.h
@@ -0,0 +1,48 @@
+/*
+ * linux/drivers/video/jz4810_lcd.h -- Ingenic Jz4810 On-Chip LCD frame buffer device
+ *
+ * Copyright (C) 2005-2008, Ingenic Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __JZ4810_AOSD_H__
+#define __JZ4810_AOSD_H__
+
+struct jz4810_aosd_info {
+	unsigned long addr0;
+	unsigned long addr1;
+	unsigned long addr2;
+	unsigned long addr3;
+	unsigned long waddr;
+
+	unsigned long smem_start;
+	char __iomem *addr0_base;
+	__u32         addr_len;
+
+	__u32         alpha_value;
+	__u32         frmlv;
+	__u32         order;
+	__u32         format_mode;
+	__u32         alpha_mode;
+	__u32         height;
+	__u32         width;
+	__u32         without_alpha;
+	__u32         compress_done;
+	__u32         bpp;
+	__u32         buf;
+}; 
+
+#define ALPHA_OSD_START         0x46a8
+#define ALPHA_OSD_GET_INFO      0x46a9
+#define ALPHA_OSD_SET_MODE      0x46aa
+#define COMPRESS_START          0x46ab
+#define COMPRESS_GET_INFO      0x46ac
+#define COMPRESS_SET_MODE      0x46ad
+#define ALPHA_OSD_PRINT      0x46ae
+ 
+
+#endif /* __JZ4810_AOSD_H__ */
diff --git a/drivers/video/jz4810_lcd.c b/drivers/video/jz4810_lcd.c
new file mode 100644
index 00000000000..a5b8d4ca0fb
--- /dev/null
+++ b/drivers/video/jz4810_lcd.c
@@ -0,0 +1,3009 @@
+/*
+ * linux/drivers/video/jz4810_lcd.c -- Ingenic Jz4810 LCD frame buffer device
+ *
+ * Copyright (C) 2005-2008, Ingenic Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/*
+ * --------------------------------
+ * NOTE:
+ * This LCD driver support TFT16 TFT32 LCD, not support STN and Special TFT LCD
+ * now.
+ * 	It seems not necessory to support STN and Special TFT.
+ * 	If it's necessary, update this driver in the future.
+ * 	<Wolfgang Wang, Jun 10 2008>
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/string.h>
+#include <linux/mm.h>
+#include <linux/tty.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/fb.h>
+#include <linux/init.h>
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+#include <linux/pm.h>
+
+#include <asm/cacheflush.h>
+#include <asm/irq.h>
+#include <asm/pgtable.h>
+#include <asm/system.h>
+#include <asm/uaccess.h>
+#include <asm/processor.h>
+#include <asm/jzsoc.h>
+
+#include "console/fbcon.h"
+
+#include "jz4810_lcd.h"
+#include "jz4810_tve.h"
+
+#ifdef CONFIG_JZ4810_SLCD_KGM701A3_TFT_SPFD5420A
+#include "jz_kgm_spfd5420a.h"
+#endif
+
+MODULE_DESCRIPTION("Jz4810 LCD Controller driver");
+MODULE_AUTHOR("Wolfgang Wang, <lgwang@ingenic.cn>");
+MODULE_LICENSE("GPL");
+
+#define D(fmt, args...) \
+//	printk(KERN_ERR "%s(): "fmt"\n", __func__, ##args)
+
+#define E(fmt, args...) \
+	printk(KERN_ERR "%s(): "fmt"\n", __func__, ##args)
+
+#define JZ_FB_DEBUG 0
+static int lcd_backlight_level = 102;
+struct jz4810lcd_info jz4810_lcd_panel = {
+#if defined(CONFIG_JZ4810_LCD_SAMSUNG_LTP400WQF02)
+	.panel = {
+		.cfg = LCD_CFG_LCDPIN_LCD | LCD_CFG_RECOVER | /* Underrun recover */
+		LCD_CFG_NEWDES | /* 8words descriptor */
+		LCD_CFG_MODE_GENERIC_TFT | /* General TFT panel */
+		LCD_CFG_MODE_TFT_18BIT | 	/* output 18bpp */
+		LCD_CFG_HSP | 	/* Hsync polarity: active low */
+		LCD_CFG_VSP,	/* Vsync polarity: leading edge is falling edge */
+		.slcd_cfg = 0,
+		.ctrl = LCD_CTRL_OFUM | LCD_CTRL_BST_16,	/* 16words burst, enable out FIFO underrun irq */
+		480, 272, 60, 41, 10, 2, 2, 2, 2,
+	},
+	.osd = {
+		 .osd_cfg = LCD_OSDC_OSDEN | /* Use OSD mode */
+//		 LCD_OSDC_ALPHAEN | /* enable alpha */
+		 LCD_OSDC_F0EN,	/* enable Foreground0 */
+		 .osd_ctrl = 0,		/* disable ipu,  */
+		 .rgb_ctrl = 0,
+		 .bgcolor = 0x000000, /* set background color Black */
+		 .colorkey0 = 0, /* disable colorkey */
+		 .colorkey1 = 0, /* disable colorkey */
+		 .alpha = 0xA0,	/* alpha value */
+		 .ipu_restart = 0x80001000, /* ipu restart */
+		 .fg_change = FG_CHANGE_ALL, /* change all initially */
+		 .fg0 = {32, 0, 0, 480, 272}, /* bpp, x, y, w, h */
+		 .fg1 = {32, 0, 0, 720, 573}, /* bpp, x, y, w, h */
+	 },
+#elif defined(CONFIG_JZ4810_LCD_AUO_A043FL01V2)
+	.panel = {
+		.cfg = LCD_CFG_LCDPIN_LCD | LCD_CFG_RECOVER | /* Underrun recover */
+		LCD_CFG_NEWDES | /* 8words descriptor */
+		LCD_CFG_MODE_GENERIC_TFT | /* General TFT panel */
+		LCD_CFG_MODE_TFT_24BIT | 	/* output 18bpp */
+		LCD_CFG_HSP | 	/* Hsync polarity: active low */
+		LCD_CFG_VSP,	/* Vsync polarity: leading edge is falling edge */
+		.slcd_cfg = 0,
+		.ctrl = LCD_CTRL_OFUM | LCD_CTRL_BST_16_CTN,	/* 16words burst, enable out FIFO underrun irq */
+		481, 272, 60, 41, 10, 8, 4, 4, 2,
+	},
+	.osd = {
+		 .osd_cfg = LCD_OSDC_OSDEN | /* Use OSD mode */
+//		 LCD_OSDC_ALPHAEN | /* enable alpha */
+//		 LCD_OSDC_F1EN | /* enable Foreground1 */
+		 LCD_OSDC_F0EN,	/* enable Foreground0 */
+		 .osd_ctrl = 0,		/* disable ipu,  */
+		 .rgb_ctrl = 0,
+		 .bgcolor = 0x000000, /* set background color Black */
+		 .colorkey0 = 0, /* disable colorkey */
+		 .colorkey1 = 0, /* disable colorkey */
+		 .alpha = 0xA0,	/* alpha value */
+		 .ipu_restart = 0x80001000, /* ipu restart */
+		 .fg_change = FG_CHANGE_ALL, /* change all initially */
+		 .fg0 = {24, 0, 0, 480, 272}, /* bpp, x, y, w, h */
+		 .fg1 = {24, 0, 0, 480, 272}, /* bpp, x, y, w, h */
+	 },
+#elif defined(CONFIG_JZ4810_LCD_TOPPOLY_TD043MGEB1)
+	.panel = {
+		.cfg = LCD_CFG_LCDPIN_LCD | LCD_CFG_RECOVER | /* Underrun recover */
+		LCD_CFG_NEWDES | /* 8words descriptor */
+		LCD_CFG_MODE_GENERIC_TFT | /* General TFT panel */
+		LCD_CFG_MODE_TFT_24BIT | 	/* output 18bpp */
+		LCD_CFG_HSP | 	/* Hsync polarity: active low */
+		LCD_CFG_VSP,	/* Vsync polarity: leading edge is falling edge */
+		.slcd_cfg = 0,
+		.ctrl = LCD_CTRL_OFUM | LCD_CTRL_IFUM0 | LCD_CTRL_BST_16,	/* 16words burst, enable out FIFO underrun irq */
+		800, 480, 60, 1, 1, 40, 215, 10, 34,
+	},
+	.osd = {
+		 .osd_cfg = LCD_OSDC_OSDEN | /* Use OSD mode */
+//		 LCD_OSDC_ALPHAEN | /* enable alpha */
+//		 LCD_OSDC_F1EN | /* enable Foreground1 */
+		 LCD_OSDC_F0EN,	/* enable Foreground0 */
+		 .osd_ctrl = 0,		/* disable ipu,  */
+		 .rgb_ctrl = 0,
+		 .bgcolor = 0xff, /* set background color Black */
+		 .colorkey0 = 0, /* disable colorkey */
+		 .colorkey1 = 0, /* disable colorkey */
+		 .alpha = 0xA0,	/* alpha value */
+		 .ipu_restart = 0x80001000, /* ipu restart */
+		 .fg_change = FG_CHANGE_ALL, /* change all initially */
+		 .fg0 = {32, 0, 0, 800, 480}, /* bpp, x, y, w, h */
+		 .fg1 = {32, 0, 0, 800, 480}, /* bpp, x, y, w, h */
+	 },
+#elif defined(CONFIG_JZ4810_LCD_TRULY_TFT_GG1P0319LTSW_W)
+	.panel = {
+		 .cfg = LCD_CFG_LCDPIN_SLCD | /* Underrun recover*/
+		 LCD_CFG_NEWDES | /* 8words descriptor */
+		 LCD_CFG_MODE_SLCD, /* TFT Smart LCD panel */
+		 .slcd_cfg = SLCD_CFG_DWIDTH_16BIT | SLCD_CFG_CWIDTH_16BIT | SLCD_CFG_CS_ACTIVE_LOW | SLCD_CFG_RS_CMD_LOW | SLCD_CFG_CLK_ACTIVE_FALLING | SLCD_CFG_TYPE_PARALLEL,
+		 .ctrl = LCD_CTRL_OFUM | LCD_CTRL_BST_16,	/* 16words burst, enable out FIFO underrun irq */
+		 240, 320, 60, 0, 0, 0, 0, 0, 0,
+	 },
+	.osd = {
+		 .osd_cfg = LCD_OSDC_OSDEN | /* Use OSD mode */
+//		 LCD_OSDC_ALPHAEN | /* enable alpha */
+//		 LCD_OSDC_F1EN | /* enable Foreground0 */
+		 LCD_OSDC_F0EN,	/* enable Foreground0 */
+		 .osd_ctrl = 0,		/* disable ipu,  */
+		 .rgb_ctrl = 0,
+		 .bgcolor = 0x000000, /* set background color Black */
+		 .colorkey0 = 0, /* disable colorkey */
+		 .colorkey1 = 0, /* disable colorkey */
+		 .alpha = 0xA0,	/* alpha value */
+		 .ipu_restart = 0x80001000, /* ipu restart */
+		 .fg_change = FG_CHANGE_ALL, /* change all initially */
+		 .fg0 = {32, 0, 0, 240, 320}, /* bpp, x, y, w, h */
+		 .fg1 = {32, 0, 0, 240, 320}, /* bpp, x, y, w, h */
+	 },
+
+#elif defined(CONFIG_JZ4810_LCD_FOXCONN_PT035TN01)
+	.panel = {
+		.cfg = LCD_CFG_LCDPIN_LCD | LCD_CFG_RECOVER | /* Underrun recover */
+		LCD_CFG_NEWDES | /* 8words descriptor */
+		LCD_CFG_MODE_GENERIC_TFT | /* General TFT panel */
+//		LCD_CFG_MODE_TFT_18BIT | 	/* output 18bpp */
+		LCD_CFG_MODE_TFT_24BIT | 	/* output 24bpp */
+		LCD_CFG_HSP | 	/* Hsync polarity: active low */
+		LCD_CFG_VSP |	/* Vsync polarity: leading edge is falling edge */
+		LCD_CFG_PCP,	/* Pix-CLK polarity: data translations at falling edge */
+		.slcd_cfg = 0,
+		.ctrl = LCD_CTRL_OFUM | LCD_CTRL_BST_16,	/* 16words burst, enable out FIFO underrun irq */
+		320, 240, 80, 1, 1, 10, 50, 10, 13
+	},
+	.osd = {
+		 .osd_cfg = LCD_OSDC_OSDEN | /* Use OSD mode */
+//		 LCD_OSDC_ALPHAEN | /* enable alpha */
+//		 LCD_OSDC_F1EN |	/* enable Foreground1 */
+		 LCD_OSDC_F0EN,	/* enable Foreground0 */
+		 .osd_ctrl = 0,		/* disable ipu,  */
+		 .rgb_ctrl = 0,
+		 .bgcolor = 0x000000, /* set background color Black */
+		 .colorkey0 = 0, /* disable colorkey */
+		 .colorkey1 = 0, /* disable colorkey */
+		 .alpha = 0xA0,	/* alpha value */
+		 .ipu_restart = 0x80001000, /* ipu restart */
+		 .fg_change = FG_CHANGE_ALL, /* change all initially */
+		 .fg0 = {32, 0, 0, 320, 240}, /* bpp, x, y, w, h */
+		 .fg1 = {32, 0, 0, 320, 240}, /* bpp, x, y, w, h */
+	 },
+#elif defined(CONFIG_JZ4810_LCD_INNOLUX_PT035TN01_SERIAL)
+	.panel = {
+		.cfg = LCD_CFG_LCDPIN_LCD | LCD_CFG_RECOVER | /* Underrun recover */
+		LCD_CFG_NEWDES | /* 8words descriptor */
+		LCD_CFG_MODE_SERIAL_TFT | /* Serial TFT panel */
+		LCD_CFG_MODE_TFT_18BIT | 	/* output 18bpp */
+		LCD_CFG_HSP | 	/* Hsync polarity: active low */
+		LCD_CFG_VSP |	/* Vsync polarity: leading edge is falling edge */
+		LCD_CFG_PCP,	/* Pix-CLK polarity: data translations at falling edge */
+		.slcd_cfg = 0,
+		.ctrl = LCD_CTRL_OFUM | LCD_CTRL_BST_16,	/* 16words burst, enable out FIFO underrun irq */
+		320, 240, 60, 1, 1, 10, 50, 10, 13
+	},
+	.osd = {
+		 .osd_cfg = LCD_OSDC_OSDEN | /* Use OSD mode */
+//		 LCD_OSDC_ALPHAEN | /* enable alpha */
+		 LCD_OSDC_F0EN,	/* enable Foreground0 */
+		 .osd_ctrl = 0,		/* disable ipu,  */
+		 .rgb_ctrl = 0,
+		 .bgcolor = 0x000000, /* set background color Black */
+		 .colorkey0 = 0, /* disable colorkey */
+		 .colorkey1 = 0, /* disable colorkey */
+		 .alpha = 0xA0,	/* alpha value */
+		 .ipu_restart = 0x80001000, /* ipu restart */
+		 .fg_change = FG_CHANGE_ALL, /* change all initially */
+		 .fg0 = {32, 0, 0, 320, 240}, /* bpp, x, y, w, h */
+		 .fg1 = {32, 0, 0, 320, 240}, /* bpp, x, y, w, h */
+	 },
+#elif defined(CONFIG_JZ4810_SLCD_KGM701A3_TFT_SPFD5420A)
+	.panel = {
+//		 .cfg = LCD_CFG_LCDPIN_SLCD | LCD_CFG_RECOVER | /* Underrun recover*/
+		 .cfg = LCD_CFG_LCDPIN_SLCD | /* Underrun recover*/
+//		 LCD_CFG_DITHER | /* dither */
+		 LCD_CFG_NEWDES | /* 8words descriptor */
+		 LCD_CFG_MODE_SLCD, /* TFT Smart LCD panel */
+		 .slcd_cfg = SLCD_CFG_DWIDTH_18BIT | SLCD_CFG_CWIDTH_18BIT | SLCD_CFG_CS_ACTIVE_LOW | SLCD_CFG_RS_CMD_LOW | SLCD_CFG_CLK_ACTIVE_FALLING | SLCD_CFG_TYPE_PARALLEL,
+		 .ctrl = LCD_CTRL_OFUM | LCD_CTRL_BST_16,	/* 16words burst, enable out FIFO underrun irq */
+		 400, 240, 60, 0, 0, 0, 0, 0, 0,
+	 },
+	.osd = {
+		 .osd_cfg = LCD_OSDC_OSDEN | /* Use OSD mode */
+//		 LCD_OSDC_ALPHAEN | /* enable alpha */
+//		 LCD_OSDC_ALPHAMD | /* alpha blending mode */
+//		 LCD_OSDC_F1EN | /* enable Foreground1 */
+		 LCD_OSDC_F0EN,	/* enable Foreground0 */
+		 .osd_ctrl = 0,		/* disable ipu,  */
+		 .rgb_ctrl = 0,
+		 .bgcolor = 0x000000, /* set background color Black */
+		 .colorkey0 = 0, /* disable colorkey */
+		 .colorkey1 = 0, /* disable colorkey */
+		 .alpha = 0xA0,	/* alpha value */
+		 .ipu_restart = 0x80001000, /* ipu restart */
+		 .fg_change = FG_CHANGE_ALL, /* change all initially */
+//		 .fg0 = {32, 0, 0, 400, 240}, /* bpp, x, y, w, h */
+		 .fg0 = {32, 0, 0, 320, 240}, /* bpp, x, y, w, h */
+		 .fg1 = {32, 0, 0, 400, 240}, /* bpp, x, y, w, h */
+	 },
+#elif defined(CONFIG_JZ4810_VGA_DISPLAY)
+	.panel = {
+		.cfg = LCD_CFG_LCDPIN_LCD | LCD_CFG_RECOVER |/* Underrun recover */
+		LCD_CFG_NEWDES | /* 8words descriptor */
+		LCD_CFG_MODE_GENERIC_TFT | /* General TFT panel */
+		LCD_CFG_MODE_TFT_24BIT | 	/* output 18bpp */
+		LCD_CFG_HSP | 	/* Hsync polarity: active low */
+		LCD_CFG_VSP,	/* Vsync polarity: leading edge is falling edge */
+		.slcd_cfg = 0,
+		.ctrl = LCD_CTRL_OFUM | LCD_CTRL_BST_16,	/* 16words burst, enable out FIFO underrun irq */
+//		800, 600, 60, 128, 4, 40, 88, 0, 23
+		640, 480, 54, 96, 2, 16, 48, 10, 33
+//		1280, 720, 50, 152, 15, 22, 200, 14, 1
+	},
+	.osd = {
+		 .osd_cfg = LCD_OSDC_OSDEN | /* Use OSD mode */
+//		 LCD_OSDC_ALPHAEN | /* enable alpha */
+//		 LCD_OSDC_F1EN | /* enable Foreground1 */
+		 LCD_OSDC_F0EN,	/* enable Foreground0 */
+		 .osd_ctrl = 0,		/* disable ipu,  */
+		 .rgb_ctrl = 0,
+		 .bgcolor = 0x000000, /* set background color Black */
+		 .colorkey0 = 0, /* disable colorkey */
+		 .colorkey1 = 0, /* disable colorkey */
+		 .alpha = 0xA0,	/* alpha value */
+		 .ipu_restart = 0x80001000, /* ipu restart */
+		 .fg_change = FG_CHANGE_ALL, /* change all initially */
+		 .fg0 = {32, 0, 0, 640, 480}, /* bpp, x, y, w, h */
+		 .fg1 = {32, 0, 0, 640, 480}, /* bpp, x, y, w, h */
+	 },
+#else
+#error "Select LCD panel first!!!"
+#endif
+};
+
+struct jz4810lcd_info jz4810_info_tve = {
+	.panel = {
+		.cfg = LCD_CFG_TVEN | /* output to tve */
+		LCD_CFG_NEWDES | /* 8words descriptor */
+		LCD_CFG_RECOVER | /* underrun protect */
+		LCD_CFG_MODE_INTER_CCIR656, /* Interlace CCIR656 mode */
+		.ctrl = LCD_CTRL_OFUM | LCD_CTRL_BST_16,	/* 16words burst */
+		TVE_WIDTH_PAL, TVE_HEIGHT_PAL, TVE_FREQ_PAL, 0, 0, 0, 0, 0, 0,
+	},
+	.osd = {
+		 .osd_cfg = LCD_OSDC_OSDEN | /* Use OSD mode */
+//		 LCD_OSDC_ALPHAEN | /* enable alpha */
+		 LCD_OSDC_F0EN,	/* enable Foreground0 */
+		 .osd_ctrl = 0,		/* disable ipu,  */
+		 .rgb_ctrl = LCD_RGBC_YCC, /* enable RGB => YUV */
+		 .bgcolor = 0x00000000, /* set background color Black */
+		 .colorkey0 = 0, /* disable colorkey */
+		 .colorkey1 = 0, /* disable colorkey */
+		 .alpha = 0xA0,	/* alpha value */
+		 .ipu_restart = 0x80000100, /* ipu restart */
+		 .fg_change = FG_CHANGE_ALL, /* change all initially */
+		 .fg0 = {32,},	/*  */
+		 .fg0 = {32,},
+	},
+};
+
+struct jz4810lcd_info *jz4810_lcd_info = &jz4810_lcd_panel; /* default output to lcd panel */
+
+struct lcd_cfb_info {
+	struct fb_info		fb;
+	struct {
+		u16 red, green, blue;
+	} palette[NR_PALETTE];
+
+	int b_lcd_display;
+	int b_lcd_pwm;
+	int backlight_level;
+};
+
+static struct lcd_cfb_info *jz4810fb_info;
+static struct jz4810_lcd_dma_desc *dma_desc_base;
+static struct jz4810_lcd_dma_desc *dma0_desc_palette, *dma0_desc0, *dma0_desc1, *dma1_desc0, *dma1_desc1;
+
+#define DMA_DESC_NUM 		6
+
+static unsigned char *lcd_palette;
+static unsigned char *lcd_frame0;
+static unsigned char *lcd_frame1;
+static unsigned char *lcd_frame2_0;
+static unsigned char *lcd_frame2_1;
+
+static struct jz4810_lcd_dma_desc *dma0_desc_cmd0, *dma0_desc_cmd;
+static unsigned char *lcd_cmdbuf;
+
+static void jz4810fb_set_mode( struct jz4810lcd_info * lcd_info );
+static void jz4810fb_deep_set_mode( struct jz4810lcd_info * lcd_info );
+
+static int jz4810fb_set_backlight_level(int n);
+
+static int screen_on(void);
+static int screen_off(void);
+
+
+#if 1//JZ_FB_DEBUG
+static void print_fb_buffer(void)
+{
+	int i;
+	int *buf0 = (int *)lcd_frame0;
+	int *buf1 = (int *)lcd_frame1;
+       
+	int *buf2_0 = (int *)lcd_frame2_0;
+	int *buf2_1 = (int *)lcd_frame2_1;
+
+	int *buf_pal = (int *)lcd_palette;
+
+	printk("\n------------lcd_frame0---------------\n");
+	for(i=0 ;i<50; i++)
+		printk("%08x \t",buf0[i]);
+#if 1
+	printk("\n------------lcd_frame2_0---------------\n");
+	for(i=0 ;i<10; i++)
+		printk("%08x \t",buf2_0[i]);
+	printk("\n");
+
+	printk("\n------------lcd_frame1---------------\n");
+	for(i=0 ;i<10; i++)
+		printk("%08x \t",buf1[i]);
+	printk("\n");
+	printk("\n------------lcd_frame2_1---------------\n");
+	for(i=0 ;i<10; i++)
+		printk("%08x \t",buf2_1[i]);
+	printk("\n");
+#endif
+	printk("\n------------lcd_palette---------------\n");
+	for(i=0 ;i<50; i++)
+		printk("%08x \t",buf_pal[i]);
+	printk("\n");
+
+}
+
+static void get_reg(struct reg *reg)
+{
+	reg->da0 = REG_LCD_DA0;
+	reg->da1 = REG_LCD_DA1;
+	return ;
+}
+
+static void print_lcdc_registers(void)	/* debug */
+{
+	/* LCD Controller Resgisters */
+	printk("REG_LCD_CFG:\t0x%08x\n", REG_LCD_CFG);
+	printk("REG_LCD_CTRL:\t0x%08x\n", REG_LCD_CTRL);
+	printk("REG_LCD_STATE:\t0x%08x\n", REG_LCD_STATE);
+	printk("REG_LCD_OSDC:\t0x%08x\n", REG_LCD_OSDC);
+	printk("REG_LCD_OSDCTRL:\t0x%08x\n", REG_LCD_OSDCTRL);
+	printk("REG_LCD_OSDS:\t0x%08x\n", REG_LCD_OSDS);
+	printk("REG_LCD_BGC:\t0x%08x\n", REG_LCD_BGC);
+	printk("REG_LCD_KEK0:\t0x%08x\n", REG_LCD_KEY0);
+	printk("REG_LCD_KEY1:\t0x%08x\n", REG_LCD_KEY1);
+	printk("REG_LCD_ALPHA:\t0x%08x\n", REG_LCD_ALPHA);
+	printk("REG_LCD_IPUR:\t0x%08x\n", REG_LCD_IPUR);
+	printk("REG_LCD_VAT:\t0x%08x\n", REG_LCD_VAT);
+	printk("REG_LCD_DAH:\t0x%08x\n", REG_LCD_DAH);
+	printk("REG_LCD_DAV:\t0x%08x\n", REG_LCD_DAV);
+	printk("REG_LCD_XYP0:\t0x%08x\n", REG_LCD_XYP0);
+	printk("REG_LCD_XYP0_PART2:\t0x%08x\n", REG_LCD_XYP0_PART2);
+	printk("REG_LCD_XYP1:\t0x%08x\n", REG_LCD_XYP1);
+	printk("REG_LCD_SIZE0:\t0x%08x\n", REG_LCD_SIZE0);
+	printk("REG_LCD_SIZE0_PART2:\t0x%08x\n", REG_LCD_SIZE0_PART2);
+	printk("REG_LCD_SIZE1:\t0x%08x\n", REG_LCD_SIZE1);
+	printk("REG_LCD_RGBC\t0x%08x\n", REG_LCD_RGBC);
+	printk("REG_LCD_VSYNC:\t0x%08x\n", REG_LCD_VSYNC);
+	printk("REG_LCD_HSYNC:\t0x%08x\n", REG_LCD_HSYNC);
+	printk("REG_LCD_PS:\t0x%08x\n", REG_LCD_PS);
+	printk("REG_LCD_CLS:\t0x%08x\n", REG_LCD_CLS);
+	printk("REG_LCD_SPL:\t0x%08x\n", REG_LCD_SPL);
+	printk("REG_LCD_REV:\t0x%08x\n", REG_LCD_REV);
+	printk("REG_LCD_IID:\t0x%08x\n", REG_LCD_IID);
+	printk("REG_LCD_DA0:\t0x%08x\n", REG_LCD_DA0);
+	printk("REG_LCD_SA0:\t0x%08x\n", REG_LCD_SA0);
+	printk("REG_LCD_FID0:\t0x%08x\n", REG_LCD_FID0);
+	printk("REG_LCD_CMD0:\t0x%08x\n", REG_LCD_CMD0);
+	printk("REG_LCD_OFFS0:\t0x%08x\n", REG_LCD_OFFS0);
+	printk("REG_LCD_PW0:\t0x%08x\n", REG_LCD_PW0);
+	printk("REG_LCD_CNUM0:\t0x%08x\n", REG_LCD_CNUM0);
+	printk("REG_LCD_DESSIZE0:\t0x%08x\n", REG_LCD_DESSIZE0);
+
+	printk("REG_LCD_DA0_PART2:\t0x%08x\n", REG_LCD_DA0_PART2);
+	printk("REG_LCD_SA0_PART2:\t0x%08x\n", REG_LCD_SA0_PART2);
+	printk("REG_LCD_FID0_PART2:\t0x%08x\n", REG_LCD_FID0_PART2);
+	printk("REG_LCD_CMD0_PART2:\t0x%08x\n", REG_LCD_CMD0_PART2);
+	printk("REG_LCD_OFFS0_PART2:\t0x%08x\n", REG_LCD_OFFS0_PART2);
+	printk("REG_LCD_PW0_PART2:\t0x%08x\n", REG_LCD_PW0_PART2);
+	printk("REG_LCD_CNUM0_PART2:\t0x%08x\n", REG_LCD_CNUM0_PART2);
+	printk("REG_LCD_DESSIZE0_PART2:\t0x%08x\n", REG_LCD_DESSIZE0_PART2);
+
+	printk("REG_LCD_DA1:\t0x%08x\n", REG_LCD_DA1);
+	printk("REG_LCD_SA1:\t0x%08x\n", REG_LCD_SA1);
+	printk("REG_LCD_FID1:\t0x%08x\n", REG_LCD_FID1);
+	printk("REG_LCD_CMD1:\t0x%08x\n", REG_LCD_CMD1);
+	printk("REG_LCD_OFFS1:\t0x%08x\n", REG_LCD_OFFS1);
+	printk("REG_LCD_PW1:\t0x%08x\n", REG_LCD_PW1);
+	printk("REG_LCD_CNUM1:\t0x%08x\n", REG_LCD_CNUM1);
+	printk("REG_LCD_DESSIZE1:\t0x%08x\n", REG_LCD_DESSIZE1);
+	printk("==================================\n");
+	printk("REG_LCD_VSYNC:\t%d:%d\n", REG_LCD_VSYNC>>16, REG_LCD_VSYNC&0xfff);
+	printk("REG_LCD_HSYNC:\t%d:%d\n", REG_LCD_HSYNC>>16, REG_LCD_HSYNC&0xfff);
+	printk("REG_LCD_VAT:\t%d:%d\n", REG_LCD_VAT>>16, REG_LCD_VAT&0xfff);
+	printk("REG_LCD_DAH:\t%d:%d\n", REG_LCD_DAH>>16, REG_LCD_DAH&0xfff);
+	printk("REG_LCD_DAV:\t%d:%d\n", REG_LCD_DAV>>16, REG_LCD_DAV&0xfff);
+	printk("==================================\n");
+
+	/* Smart LCD Controller Resgisters */
+	printk("REG_SLCD_CFG:\t0x%08x\n", REG_SLCD_CFG);
+	printk("REG_SLCD_CTRL:\t0x%08x\n", REG_SLCD_CTRL);
+	printk("REG_SLCD_STATE:\t0x%08x\n", REG_SLCD_STATE);
+	printk("==================================\n");
+
+	/* TVE Controller Resgisters */
+	printk("REG_TVE_CTRL:\t0x%08x\n", REG_TVE_CTRL);
+	printk("REG_TVE_FRCFG:\t0x%08x\n", REG_TVE_FRCFG);
+	printk("REG_TVE_SLCFG1:\t0x%08x\n", REG_TVE_SLCFG1);
+	printk("REG_TVE_SLCFG2:\t0x%08x\n", REG_TVE_SLCFG2);
+	printk("REG_TVE_SLCFG3:\t0x%08x\n", REG_TVE_SLCFG3);
+	printk("REG_TVE_LTCFG1:\t0x%08x\n", REG_TVE_LTCFG1);
+	printk("REG_TVE_LTCFG2:\t0x%08x\n", REG_TVE_LTCFG2);
+	printk("REG_TVE_CFREQ:\t0x%08x\n", REG_TVE_CFREQ);
+	printk("REG_TVE_CPHASE:\t0x%08x\n", REG_TVE_CPHASE);
+	printk("REG_TVE_CBCRCFG:\t0x%08x\n", REG_TVE_CBCRCFG);
+	printk("REG_TVE_WSSCR:\t0x%08x\n", REG_TVE_WSSCR);
+	printk("REG_TVE_WSSCFG1:\t0x%08x\n", REG_TVE_WSSCFG1);
+	printk("REG_TVE_WSSCFG2:\t0x%08x\n", REG_TVE_WSSCFG2);
+	printk("REG_TVE_WSSCFG3:\t0x%08x\n", REG_TVE_WSSCFG3);
+
+	printk("==================================\n");
+#if 0
+	if ( 0 ) {
+		unsigned int * pii = (unsigned int *)dma_desc_base;
+		int i, j;
+		for (j=0;j< DMA_DESC_NUM ; j++) {
+			printk("dma_desc%d(0x%08x):\n", j, (unsigned int)pii);
+			for (i =0; i<8; i++ ) {
+				printk("\t\t0x%08x\n", *pii++);
+			}
+		}
+	}
+#endif
+}
+#else
+#define print_lcdc_registers()
+#endif
+
+static void ctrl_enable(void)
+{
+	REG_LCD_STATE = 0; /* clear lcdc status */
+	__lcd_slcd_special_on();
+	__lcd_clr_dis();
+	__lcd_set_ena(); /* enable lcdc */
+
+	return;
+}
+
+static void ctrl_disable(void)
+{
+	if ( jz4810_lcd_info->panel.cfg & LCD_CFG_LCDPIN_SLCD ||
+			jz4810_lcd_info->panel.cfg & LCD_CFG_TVEN ) /*  */
+		__lcd_clr_ena(); /* Smart lcd and TVE mode only support quick disable */
+	else {
+		int cnt;
+		/* when CPU main freq is 336MHz,wait for 30ms */
+//		cnt = 528000 * 30;
+		cnt = 528000 ;
+		__lcd_set_dis(); /* regular disable */ 
+
+		while(!__lcd_disable_done() && cnt) {
+			cnt--;
+		}
+		if (cnt == 0)
+			printk("LCD disable timeout! REG_LCD_STATE=0x%08xx\n",REG_LCD_STATE);
+		REG_LCD_STATE &= ~LCD_STATE_LDD;
+	}
+	return;
+}
+
+static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
+{
+        chan &= 0xffff;
+        chan >>= 16 - bf->length;
+        return chan << bf->offset;
+}
+
+static int jz4810fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
+			  u_int transp, struct fb_info *info)
+{
+	struct lcd_cfb_info *cfb = (struct lcd_cfb_info *)info;
+	unsigned short *ptr, ctmp;
+
+//	D("regno:%d,RGBt:(%d,%d,%d,%d)\t", regno, red, green, blue, transp);
+	if (regno >= NR_PALETTE)
+		return 1;
+
+	cfb->palette[regno].red		= red ;
+	cfb->palette[regno].green	= green;
+	cfb->palette[regno].blue	= blue;
+	if (cfb->fb.var.bits_per_pixel <= 16) {
+		red	>>= 8;
+		green	>>= 8;
+		blue	>>= 8;
+
+		red	&= 0xff;
+		green	&= 0xff;
+		blue	&= 0xff;
+	}
+	switch (cfb->fb.var.bits_per_pixel) {
+	case 1:
+	case 2:
+	case 4:
+	case 8:
+		if (((jz4810_lcd_info->panel.cfg & LCD_CFG_MODE_MASK) == LCD_CFG_MODE_SINGLE_MSTN ) ||
+		    ((jz4810_lcd_info->panel.cfg & LCD_CFG_MODE_MASK) == LCD_CFG_MODE_DUAL_MSTN )) {
+			ctmp = (77L * red + 150L * green + 29L * blue) >> 8;
+			ctmp = ((ctmp >> 3) << 11) | ((ctmp >> 2) << 5) |
+				(ctmp >> 3);
+		} else {
+			/* RGB 565 */
+			if (((red >> 3) == 0) && ((red >> 2) != 0))
+			red = 1 << 3;
+			if (((blue >> 3) == 0) && ((blue >> 2) != 0))
+				blue = 1 << 3;
+			ctmp = ((red >> 3) << 11)
+				| ((green >> 2) << 5) | (blue >> 3);
+		}
+
+		ptr = (unsigned short *)lcd_palette;
+		ptr = (unsigned short *)(((u32)ptr)|0xa0000000);
+		ptr[regno] = ctmp;
+		break;
+
+	case 15:
+		if (regno < 16)
+			((u32 *)cfb->fb.pseudo_palette)[regno] =
+				((red >> 3) << 10) |
+				((green >> 3) << 5) |
+				(blue >> 3);
+		break;
+	case 16:
+		if (regno < 16) {
+			((u32 *)cfb->fb.pseudo_palette)[regno] =
+				((red >> 3) << 11) |
+				((green >> 2) << 5) |
+				(blue >> 3);
+		}
+		break;
+	case 17 ... 32:
+		if (regno < 16)
+			((u32 *)cfb->fb.pseudo_palette)[regno] =
+				(red << 16) |
+				(green << 8) |
+				(blue << 0);
+
+/*		if (regno < 16) {
+			unsigned val;
+                        val  = chan_to_field(red, &cfb->fb.var.red);
+                        val |= chan_to_field(green, &cfb->fb.var.green);
+                        val |= chan_to_field(blue, &cfb->fb.var.blue);
+			((u32 *)cfb->fb.pseudo_palette)[regno] = val;
+		}
+*/
+
+		break;
+	}
+	return 0;
+}
+
+
+/*
+ * switch to tve mode from lcd mode
+ * mode:
+ * 	PANEL_MODE_TVE_PAL: switch to TVE_PAL mode
+ * 	PANEL_MODE_TVE_NTSC: switch to TVE_NTSC mode
+ */
+static void jz4810lcd_info_switch_to_TVE(int mode)
+{
+	struct jz4810lcd_info *info;
+	struct jz4810lcd_osd_t *osd_lcd;
+	int x, y, w, h;
+
+	info = jz4810_lcd_info = &jz4810_info_tve;
+	osd_lcd = &jz4810_lcd_panel.osd;
+
+	switch ( mode ) {
+	case PANEL_MODE_TVE_PAL:
+		info->panel.cfg |= LCD_CFG_TVEPEH; /* TVE PAL enable extra halfline signal */
+		info->panel.w = TVE_WIDTH_PAL;
+		info->panel.h = TVE_HEIGHT_PAL;
+		info->panel.fclk = TVE_FREQ_PAL;
+		w = ( osd_lcd->fg0.w < TVE_WIDTH_PAL )? osd_lcd->fg0.w:TVE_WIDTH_PAL;
+		h = ( osd_lcd->fg0.h < TVE_HEIGHT_PAL )?osd_lcd->fg0.h:TVE_HEIGHT_PAL;
+//		x = ((TVE_WIDTH_PAL - w) >> 2) << 1;
+//		y = ((TVE_HEIGHT_PAL - h) >> 2) << 1;
+		x = 0;
+		y = 0;
+
+		info->osd.fg0.bpp = osd_lcd->fg0.bpp;
+		info->osd.fg0.x = x;
+		info->osd.fg0.y = y;
+		info->osd.fg0.w = w;
+		info->osd.fg0.h = h;
+		w = ( osd_lcd->fg1.w < TVE_WIDTH_PAL )? osd_lcd->fg1.w:TVE_WIDTH_PAL;
+		h = ( osd_lcd->fg1.h < TVE_HEIGHT_PAL )?osd_lcd->fg1.h:TVE_HEIGHT_PAL;
+//		x = ((TVE_WIDTH_PAL-w) >> 2) << 1;
+//		y = ((TVE_HEIGHT_PAL-h) >> 2) << 1;
+		x = 0;
+		y = 0;
+
+		info->osd.fg1.bpp = 32;	/* use RGB888 in TVE mode*/
+		info->osd.fg1.x = x;
+		info->osd.fg1.y = y;
+		info->osd.fg1.w = w;
+		info->osd.fg1.h = h;
+		break;
+	case PANEL_MODE_TVE_NTSC:
+		info->panel.cfg &= ~LCD_CFG_TVEPEH; /* TVE NTSC disable extra halfline signal */
+		info->panel.w = TVE_WIDTH_NTSC;
+		info->panel.h = TVE_HEIGHT_NTSC;
+		info->panel.fclk = TVE_FREQ_NTSC;
+		w = ( osd_lcd->fg0.w < TVE_WIDTH_NTSC )? osd_lcd->fg0.w:TVE_WIDTH_NTSC;
+		h = ( osd_lcd->fg0.h < TVE_HEIGHT_NTSC)?osd_lcd->fg0.h:TVE_HEIGHT_NTSC;
+		x = ((TVE_WIDTH_NTSC - w) >> 2) << 1;
+		y = ((TVE_HEIGHT_NTSC - h) >> 2) << 1;
+//		x = 0;
+//		y = 0;
+		info->osd.fg0.bpp = osd_lcd->fg0.bpp;
+		info->osd.fg0.x = x;
+		info->osd.fg0.y = y;
+		info->osd.fg0.w = w;
+		info->osd.fg0.h = h;
+		w = ( osd_lcd->fg1.w < TVE_WIDTH_NTSC )? osd_lcd->fg1.w:TVE_WIDTH_NTSC;
+		h = ( osd_lcd->fg1.h < TVE_HEIGHT_NTSC)?osd_lcd->fg1.h:TVE_HEIGHT_NTSC;
+		x = ((TVE_WIDTH_NTSC - w) >> 2) << 1;
+		y = ((TVE_HEIGHT_NTSC - h) >> 2) << 1;
+		info->osd.fg1.bpp = 32;	/* use RGB888 int TVE mode */
+		info->osd.fg1.x = x;
+		info->osd.fg1.y = y;
+		info->osd.fg1.w = w;
+		info->osd.fg1.h = h;
+		break;
+	default:
+		printk("%s, %s: Unknown tve mode\n", __FILE__, __FUNCTION__);
+	}
+}
+
+static int jz4810fb_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg)
+{
+	struct reg da_reg;
+	int ret = 0;
+        void __user *argp = (void __user *)arg;
+
+	switch (cmd) {
+	case FBIOSETBACKLIGHT:
+		jz4810fb_set_backlight_level(arg);
+
+		break;
+#if 0		
+	case FBIO_PRINT_BUF:
+		print_fb_buffer();
+		break;
+
+	case FBIO_SET_PAL:
+		set_palette();
+		break;
+#endif
+	case FBIODISPON:
+		ctrl_enable();
+		screen_on();
+		break;
+
+	case FBIODISPOFF:
+		screen_off();
+		ctrl_disable();
+		break;
+
+	case FBIOPRINT_REG:
+		print_lcdc_registers();
+
+		break;
+
+	case FBIO_GET_MODE:
+		D("fbio get mode\n");
+
+		if (copy_to_user(argp, jz4810_lcd_info, sizeof(struct jz4810lcd_info)))
+			return -EFAULT;
+
+		break;
+
+	case FBIO_SET_MODE:
+		D("fbio set mode\n");
+
+		if (copy_from_user(jz4810_lcd_info, argp, sizeof(struct jz4810lcd_info)))
+			return -EFAULT;
+
+		/* set mode */
+		jz4810fb_set_mode(jz4810_lcd_info);
+
+		break;
+
+	case FBIO_DEEP_SET_MODE:
+		D("fbio deep set mode\n");
+
+		if (copy_from_user(jz4810_lcd_info, argp, sizeof(struct jz4810lcd_info)))
+			return -EFAULT;
+
+		jz4810fb_deep_set_mode(jz4810_lcd_info);
+
+		break;
+
+#ifdef CONFIG_FB_JZ4810_TVE
+	case FBIO_MODE_SWITCH:
+		D("FBIO_MODE_SWITCH");
+		switch (arg) {
+			case PANEL_MODE_TVE_PAL: 	/* switch to TVE_PAL mode */
+			case PANEL_MODE_TVE_NTSC: 	/* switch to TVE_NTSC mode */
+				jz4810lcd_info_switch_to_TVE(arg);
+				jz4810tve_init(arg); /* tve controller init */
+				udelay(100);
+				jz4810tve_enable_tve();
+				/* turn off lcd backlight */
+				screen_off();
+				break;
+			case PANEL_MODE_LCD_PANEL: 	/* switch to LCD mode */
+			default :
+				/* turn off TVE, turn off DACn... */
+				jz4810tve_disable_tve();
+				jz4810_lcd_info = &jz4810_lcd_panel;
+				/* turn on lcd backlight */
+				screen_on();
+				break;
+		}
+
+		jz4810fb_deep_set_mode(jz4810_lcd_info);
+
+		break;
+
+	case FBIO_GET_TVE_MODE:
+		D("fbio get TVE mode\n");
+		if (copy_to_user(argp, jz4810_tve_info, sizeof(struct jz4810tve_info)))
+			return -EFAULT;
+		break;
+	case FBIO_SET_TVE_MODE:
+		D("fbio set TVE mode\n");
+		if (copy_from_user(jz4810_tve_info, argp, sizeof(struct jz4810tve_info)))
+			return -EFAULT;
+		/* set tve mode */
+		jz4810tve_set_tve_mode(jz4810_tve_info);
+		break;
+#endif
+	default:
+		printk("%s, unknown command(0x%x)", __FILE__, cmd);
+		break;
+	}
+
+	return ret;
+}
+
+/* Use mmap /dev/fb can only get a non-cacheable Virtual Address. */
+static int jz4810fb_mmap(struct fb_info *info, struct vm_area_struct *vma)
+{
+	struct lcd_cfb_info *cfb = (struct lcd_cfb_info *)info;
+	unsigned long start;
+	unsigned long off;
+	u32 len;
+	D("%s, %s, %d\n", __FILE__, __FUNCTION__, __LINE__);
+	off = vma->vm_pgoff << PAGE_SHIFT;
+	//fb->fb_get_fix(&fix, PROC_CONSOLE(info), info);
+
+	/* frame buffer memory */
+	start = cfb->fb.fix.smem_start;
+	len = PAGE_ALIGN((start & ~PAGE_MASK) + cfb->fb.fix.smem_len);
+	start &= PAGE_MASK;
+
+	if ((vma->vm_end - vma->vm_start + off) > len)
+		return -EINVAL;
+	off += start;
+
+	vma->vm_pgoff = off >> PAGE_SHIFT;
+	vma->vm_flags |= VM_IO;
+	vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);	/* Uncacheable */
+
+#if 1
+ 	pgprot_val(vma->vm_page_prot) &= ~_CACHE_MASK;
+// 	pgprot_val(vma->vm_page_prot) |= _CACHE_UNCACHED;		/* Uncacheable */
+	pgprot_val(vma->vm_page_prot) |= _CACHE_CACHABLE_NONCOHERENT;	/* Write-Back */
+#endif
+
+	if (io_remap_pfn_range(vma, vma->vm_start, off >> PAGE_SHIFT,
+			       vma->vm_end - vma->vm_start,
+			       vma->vm_page_prot)) {
+		return -EAGAIN;
+	}
+	return 0;
+}
+
+/* checks var and eventually tweaks it to something supported,
+ * DO NOT MODIFY PAR */
+static int jz4810fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
+{
+	printk("jz4810fb_check_var, not implement\n");
+	return 0;
+}
+
+
+/*
+ * set the video mode according to info->var
+ */
+static int jz4810fb_set_par(struct fb_info *info)
+{
+	printk("jz4810fb_set_par, not implemented\n");
+	return 0;
+}
+
+
+/*
+ * (Un)Blank the display.
+ * Fix me: should we use VESA value?
+ */
+static int jz4810fb_blank(int blank_mode, struct fb_info *info)
+{
+	D("jz4810 fb_blank %d %p", blank_mode, info);
+	switch (blank_mode) {
+	case FB_BLANK_UNBLANK:
+		//case FB_BLANK_NORMAL:
+			/* Turn on panel */
+		__lcd_set_ena();
+		screen_on();
+
+		break;
+
+	case FB_BLANK_NORMAL:
+	case FB_BLANK_VSYNC_SUSPEND:
+	case FB_BLANK_HSYNC_SUSPEND:
+	case FB_BLANK_POWERDOWN:
+#if 0
+		/* Turn off panel */
+		__lcd_display_off();
+		__lcd_set_dis();
+#endif
+		break;
+	default:
+		break;
+
+	}
+	return 0;
+}
+
+/*
+ * pan display
+ */
+static int jz4810fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
+{
+	struct lcd_cfb_info *cfb = (struct lcd_cfb_info *)info;
+	int dy;
+
+	if (!var || !cfb) {
+		return -EINVAL;
+	}
+
+	if (var->xoffset - cfb->fb.var.xoffset) {
+		/* No support for X panning for now! */
+		return -EINVAL;
+	}
+
+	dy = var->yoffset;
+	D("var.yoffset: %d", dy);
+	if (dy) {
+		dma0_desc0->databuf = (unsigned int)virt_to_phys((void *)lcd_frame0 + (cfb->fb.fix.line_length * dy));
+		dma_cache_wback((unsigned int)(dma0_desc0), sizeof(struct jz4810_lcd_dma_desc));
+
+	}
+	else {
+		dma0_desc0->databuf = (unsigned int)virt_to_phys((void *)lcd_frame0);
+		dma_cache_wback((unsigned int)(dma0_desc0), sizeof(struct jz4810_lcd_dma_desc));
+	}
+
+	return 0;
+}
+
+
+/* use default function cfb_fillrect, cfb_copyarea, cfb_imageblit */
+static struct fb_ops jz4810fb_ops = {
+	.owner			= THIS_MODULE,
+	.fb_setcolreg		= jz4810fb_setcolreg,
+	.fb_check_var 		= jz4810fb_check_var,
+	.fb_set_par 		= jz4810fb_set_par,
+	.fb_blank		= jz4810fb_blank,
+	.fb_pan_display		= jz4810fb_pan_display,
+	.fb_fillrect		= cfb_fillrect,
+	.fb_copyarea		= cfb_copyarea,
+	.fb_imageblit		= cfb_imageblit,
+	.fb_mmap		= jz4810fb_mmap,
+	.fb_ioctl		= jz4810fb_ioctl,
+};
+
+static int jz4810fb_set_var(struct fb_var_screeninfo *var, int con,
+			struct fb_info *info)
+{
+	struct lcd_cfb_info *cfb = (struct lcd_cfb_info *)info;
+	struct jz4810lcd_info *lcd_info = jz4810_lcd_info;
+	int chgvar = 0;
+
+	var->height	            = lcd_info->osd.fg0.h;	/* tve mode */
+	var->width	            = lcd_info->osd.fg0.w;
+	var->bits_per_pixel	    = lcd_info->osd.fg0.bpp;
+
+	var->vmode                  = FB_VMODE_NONINTERLACED;
+	var->activate               = cfb->fb.var.activate;
+	var->xres                   = var->width;
+	var->yres                   = var->height;
+	var->xres_virtual           = var->width;
+	var->yres_virtual           = var->height;
+	var->xoffset                = 0;
+	var->yoffset                = 0;
+	var->pixclock               = 0;
+	var->left_margin            = 0;
+	var->right_margin           = 0;
+	var->upper_margin           = 0;
+	var->lower_margin           = 0;
+	var->hsync_len              = 0;
+	var->vsync_len              = 0;
+	var->sync                   = 0;
+	var->activate              &= ~FB_ACTIVATE_TEST;
+
+	/*
+	 * CONUPDATE and SMOOTH_XPAN are equal.  However,
+	 * SMOOTH_XPAN is only used internally by fbcon.
+	 */
+	if (var->vmode & FB_VMODE_CONUPDATE) {
+		var->vmode |= FB_VMODE_YWRAP;
+		var->xoffset = cfb->fb.var.xoffset;
+		var->yoffset = cfb->fb.var.yoffset;
+	}
+
+	if (var->activate & FB_ACTIVATE_TEST)
+		return 0;
+
+	if ((var->activate & FB_ACTIVATE_MASK) != FB_ACTIVATE_NOW)
+		return -EINVAL;
+
+	if (cfb->fb.var.xres != var->xres)
+		chgvar = 1;
+	if (cfb->fb.var.yres != var->yres)
+		chgvar = 1;
+	if (cfb->fb.var.xres_virtual != var->xres_virtual)
+		chgvar = 1;
+	if (cfb->fb.var.yres_virtual != var->yres_virtual)
+		chgvar = 1;
+	if (cfb->fb.var.bits_per_pixel != var->bits_per_pixel)
+		chgvar = 1;
+
+	//display = fb_display + con;
+
+	var->red.msb_right	= 0;
+	var->green.msb_right	= 0;
+	var->blue.msb_right	= 0;
+
+	switch(var->bits_per_pixel){
+	case 1:	/* Mono */
+		cfb->fb.fix.visual	= FB_VISUAL_MONO01;
+		cfb->fb.fix.line_length	= (var->xres * var->bits_per_pixel) / 8;
+		break;
+	case 2:	/* Mono */
+		var->red.offset		= 0;
+		var->red.length		= 2;
+		var->green.offset	= 0;
+		var->green.length	= 2;
+		var->blue.offset	= 0;
+		var->blue.length	= 2;
+
+		cfb->fb.fix.visual	= FB_VISUAL_PSEUDOCOLOR;
+		cfb->fb.fix.line_length	= (var->xres * var->bits_per_pixel) / 8;
+		break;
+	case 4:	/* PSEUDOCOLOUR*/
+		var->red.offset		= 0;
+		var->red.length		= 4;
+		var->green.offset	= 0;
+		var->green.length	= 4;
+		var->blue.offset	= 0;
+		var->blue.length	= 4;
+
+		cfb->fb.fix.visual	= FB_VISUAL_PSEUDOCOLOR;
+		cfb->fb.fix.line_length	= var->xres / 2;
+		break;
+	case 8:	/* PSEUDOCOLOUR, 256 */
+		var->red.offset		= 0;
+		var->red.length		= 8;
+		var->green.offset	= 0;
+		var->green.length	= 8;
+		var->blue.offset	= 0;
+		var->blue.length	= 8;
+
+		cfb->fb.fix.visual	= FB_VISUAL_PSEUDOCOLOR;
+		cfb->fb.fix.line_length	= var->xres ;
+		break;
+	case 15: /* DIRECTCOLOUR, 32k */
+		var->bits_per_pixel	= 15;
+		var->red.offset		= 10;
+		var->red.length		= 5;
+		var->green.offset	= 5;
+		var->green.length	= 5;
+		var->blue.offset	= 0;
+		var->blue.length	= 5;
+
+		cfb->fb.fix.visual	= FB_VISUAL_DIRECTCOLOR;
+		cfb->fb.fix.line_length	= var->xres_virtual * 2;
+		break;
+	case 16: /* DIRECTCOLOUR, 64k */
+		var->bits_per_pixel	= 16;
+		var->red.offset		= 11;
+		var->red.length		= 5;
+		var->green.offset	= 5;
+		var->green.length	= 6;
+		var->blue.offset	= 0;
+		var->blue.length	= 5;
+
+		cfb->fb.fix.visual	= FB_VISUAL_TRUECOLOR;
+		cfb->fb.fix.line_length	= var->xres_virtual * 2;
+		break;
+	case 17 ... 32:
+		/* DIRECTCOLOUR, 256 */
+		var->bits_per_pixel	= 32;
+
+		var->red.offset		= 16;
+		var->red.length		= 8;
+		var->green.offset	= 8;
+		var->green.length	= 8;
+		var->blue.offset	= 0;
+		var->blue.length	= 8;
+		var->transp.offset  	= 24;
+		var->transp.length 	= 8;
+
+		cfb->fb.fix.visual	= FB_VISUAL_TRUECOLOR;
+		cfb->fb.fix.line_length	= var->xres_virtual * 4;
+		break;
+
+	default: /* in theory this should never happen */
+		printk(KERN_WARNING "%s: don't support for %dbpp\n",
+		       cfb->fb.fix.id, var->bits_per_pixel);
+		break;
+	}
+
+	cfb->fb.var = *var;
+	cfb->fb.var.activate &= ~FB_ACTIVATE_ALL;
+
+	/*
+	 * Update the old var.  The fbcon drivers still use this.
+	 * Once they are using cfb->fb.var, this can be dropped.
+	 *					--rmk
+	 */
+	//display->var = cfb->fb.var;
+	/*
+	 * If we are setting all the virtual consoles, also set the
+	 * defaults used to create new consoles.
+	 */
+	fb_set_cmap(&cfb->fb.cmap, &cfb->fb);
+
+	return 0;
+}
+
+static struct lcd_cfb_info * jz4810fb_alloc_fb_info(void)
+{
+ 	struct lcd_cfb_info *cfb;
+
+	cfb = kmalloc(sizeof(struct lcd_cfb_info) + sizeof(u32) * 16, GFP_KERNEL);
+
+	if (!cfb)
+		return NULL;
+
+	jz4810fb_info = cfb;
+
+	memset(cfb, 0, sizeof(struct lcd_cfb_info) );
+
+	cfb->backlight_level		= LCD_DEFAULT_BACKLIGHT;
+
+	strcpy(cfb->fb.fix.id, "jz-lcd");
+	cfb->fb.fix.type	= FB_TYPE_PACKED_PIXELS;
+	cfb->fb.fix.type_aux	= 0;
+	cfb->fb.fix.xpanstep	= 1;
+	cfb->fb.fix.ypanstep	= 1;
+	cfb->fb.fix.ywrapstep	= 0;
+	cfb->fb.fix.accel	= FB_ACCEL_NONE;
+
+	cfb->fb.var.nonstd	= 0;
+	cfb->fb.var.activate	= FB_ACTIVATE_NOW;
+	cfb->fb.var.height	= -1;
+	cfb->fb.var.width	= -1;
+	cfb->fb.var.accel_flags	= FB_ACCELF_TEXT;
+
+	cfb->fb.fbops		= &jz4810fb_ops;
+	cfb->fb.flags		= FBINFO_FLAG_DEFAULT;
+
+	cfb->fb.pseudo_palette	= (void *)(cfb + 1);
+
+	switch (jz4810_lcd_info->osd.fg0.bpp) {
+	case 1:
+		fb_alloc_cmap(&cfb->fb.cmap, 4, 0);
+		break;
+	case 2:
+		fb_alloc_cmap(&cfb->fb.cmap, 8, 0);
+		break;
+	case 4:
+		fb_alloc_cmap(&cfb->fb.cmap, 32, 0);
+		break;
+	case 8:
+	default:
+		fb_alloc_cmap(&cfb->fb.cmap, 256, 0);
+		break;
+	}
+	D("fb_alloc_cmap,fb.cmap.len:%d....\n", cfb->fb.cmap.len);
+
+	return cfb;
+}
+
+static int bpp_to_data_bpp(int bpp)
+{
+	switch (bpp) {
+		case 1:
+		case 2:
+		case 4:
+		case 8:
+		case 32:
+		case 16:
+			break;
+
+		case 15:
+			bpp = 16;
+			break;
+	        case 18:
+	        case 24:
+	        case 30:
+			bpp = 32;
+			break;
+		default:
+			bpp = -EINVAL;
+	}
+
+	return bpp;
+}
+
+/*
+ * Map screen memory
+ */
+
+static int jz4810fb_map_smem(struct lcd_cfb_info *cfb)
+{
+	unsigned long page;
+	unsigned int page_shift, needroom, needroom1, bpp, w, h;
+
+	bpp = bpp_to_data_bpp(jz4810_lcd_info->osd.fg0.bpp);
+
+	D("FG0 BPP: %d, Data BPP: %d.", jz4810_lcd_info->osd.fg0.bpp, bpp);
+
+#ifndef CONFIG_FB_JZ4810_TVE
+	w = jz4810_lcd_info->osd.fg0.w;
+	h = jz4810_lcd_info->osd.fg0.h;
+#else
+	w = ( jz4810_lcd_info->osd.fg0.w > TVE_WIDTH_PAL )?jz4810_lcd_info->osd.fg0.w:TVE_WIDTH_PAL;
+	h = ( jz4810_lcd_info->osd.fg0.h > TVE_HEIGHT_PAL )?jz4810_lcd_info->osd.fg0.h:TVE_HEIGHT_PAL;
+#endif
+/*lltang: we may be use the differ BPP, the buffer should be the largest one*/
+#if defined(CONFIG_JZ4810_COMPRESS)
+	needroom1 = needroom = ((481 * 32) >> 3) * 272 * 2;
+#else
+	needroom1 = needroom = ((480 * 32) >> 3) * 272 *2;
+#endif
+#if defined(CONFIG_FB_JZ4810_LCD_USE_2LAYER_FRAMEBUFFER)
+	bpp = bpp_to_data_bpp(jz4810_lcd_info->osd.fg1.bpp);
+
+	D("FG1 BPP: %d, Data BPP: %d.", jz4810_lcd_info->osd.fg1.bpp, bpp);
+
+#ifndef CONFIG_FB_JZ4810_TVE
+	w = jz4810_lcd_info->osd.fg1.w;
+	h = jz4810_lcd_info->osd.fg1.h;
+#else
+	w = ( jz4810_lcd_info->osd.fg1.w > TVE_WIDTH_PAL )?jz4810_lcd_info->osd.fg1.w:TVE_WIDTH_PAL;
+	h = ( jz4810_lcd_info->osd.fg1.h > TVE_HEIGHT_PAL )?jz4810_lcd_info->osd.fg1.h:TVE_HEIGHT_PAL;
+#endif
+#if defined(CONFIG_JZ4810_COMPRESS)
+	needroom += ((481 * 32 ) >> 3) * 272 *2;
+#else
+	needroom += ((480 * 32 ) >> 3) * 272 *2;
+#endif
+#endif // two layer
+
+//	page_shift = get_order(needroom);
+
+	for (page_shift = 0; page_shift < 12; page_shift++)
+		if ((PAGE_SIZE << page_shift) >= needroom)
+			break;
+
+	printk("page shift is %d\n",page_shift);
+	lcd_palette = (unsigned char *)__get_free_pages(GFP_KERNEL, 0);
+	lcd_frame0 = (unsigned char *)__get_free_pages(GFP_KERNEL, page_shift);
+
+	lcd_frame2_0 = lcd_frame0 + needroom1/2;
+
+	jz4810_lcd_info->frame0 = virt_to_phys((void *)lcd_frame0);
+	jz4810_lcd_info->frame2_0 = virt_to_phys((void *)lcd_frame2_0);
+
+	if ((!lcd_palette) || (!lcd_frame0))
+		return -ENOMEM;
+	memset((void *)lcd_palette, 0, PAGE_SIZE);
+	memset((void *)lcd_frame0, 0, PAGE_SIZE << page_shift);
+
+	dma_desc_base = (struct jz4810_lcd_dma_desc *)((void*)lcd_palette + ((PALETTE_SIZE+3)/4)*4);
+
+#if defined(CONFIG_FB_JZ4810_SLCD)
+	lcd_cmdbuf = (unsigned char *)__get_free_pages(GFP_KERNEL, 0);
+	memset((void *)lcd_cmdbuf, 0, PAGE_SIZE);
+
+	{	int data, i, *ptr;
+		ptr = (unsigned int *)lcd_cmdbuf;
+		data = WR_GRAM_CMD;
+		data = ((data & 0xff) << 1) | ((data & 0xff00) << 2);
+		for(i = 0; i < 3; i++){
+			ptr[i] = data;
+		}
+	}
+#endif
+
+#if defined(CONFIG_FB_JZ4810_LCD_USE_2LAYER_FRAMEBUFFER)
+	lcd_frame1 = lcd_frame0 + needroom1;
+	lcd_frame2_1 = lcd_frame1 + needroom1/2;
+
+	jz4810_lcd_info->frame1 = virt_to_phys((void *)lcd_frame1);
+	jz4810_lcd_info->frame2_1 = virt_to_phys((void *)lcd_frame2_1);
+#endif
+
+	printk("lcd_frame0 %p \t, lcd_frame1 %p\n",lcd_frame0,lcd_frame1);
+	printk("lcd_frame2_0 %p \t, lcd_frame2_1 %p\n",lcd_frame2_0,lcd_frame2_1);
+	/*
+	 * Set page reserved so that mmap will work. This is necessary
+	 * since we'll be remapping normal memory.
+	 */
+	page = (unsigned long)lcd_palette;
+	SetPageReserved(virt_to_page((void*)page));
+
+	for (page = (unsigned long)lcd_frame0;
+	     page < PAGE_ALIGN((unsigned long)lcd_frame0 + (PAGE_SIZE<<page_shift));
+	     page += PAGE_SIZE) {
+		SetPageReserved(virt_to_page((void*)page));
+	}
+
+	cfb->fb.fix.smem_start = virt_to_phys((void *)lcd_frame0);
+	cfb->fb.fix.smem_len = (PAGE_SIZE << page_shift); /* page_shift/2 ??? */
+	cfb->fb.screen_base =
+		(unsigned char *)(((unsigned int)lcd_frame0&0x1fffffff) | 0xa0000000);
+
+	if (!cfb->fb.screen_base) {
+		printk("jz4810fb, %s: unable to map screen memory\n", cfb->fb.fix.id);
+		return -ENOMEM;
+	}
+
+
+	return 0;
+}
+
+static void jz4810fb_free_fb_info(struct lcd_cfb_info *cfb)
+{
+	if (cfb) {
+		fb_alloc_cmap(&cfb->fb.cmap, 0, 0);
+		kfree(cfb);
+	}
+}
+
+static void jz4810fb_unmap_smem(struct lcd_cfb_info *cfb)
+{
+	struct page * map = NULL;
+	unsigned char *tmp;
+	unsigned int page_shift, needroom, bpp, w, h;
+
+	bpp = jz4810_lcd_info->osd.fg0.bpp;
+	if ( bpp == 18 || bpp == 24)
+		bpp = 32;
+	if ( bpp == 15 )
+		bpp = 16;
+	w = jz4810_lcd_info->osd.fg0.w;
+	h = jz4810_lcd_info->osd.fg0.h;
+	needroom = ((w * bpp + 7) >> 3) * h;
+#if defined(CONFIG_JZ4810_COMPRESS)
+	needroom = ((480 * 32 + 7) >> 3) * 272*2;
+#else
+	needroom = ((480 * 32 + 7) >> 3) * 272*2;
+#endif
+
+#if defined(CONFIG_FB_JZ4810_LCD_USE_2LAYER_FRAMEBUFFER)
+	bpp = jz4810_lcd_info->osd.fg1.bpp;
+	if ( bpp == 18 || bpp == 24)
+		bpp = 32;
+	if ( bpp == 15 )
+		bpp = 16;
+	w = jz4810_lcd_info->osd.fg1.w;
+	h = jz4810_lcd_info->osd.fg1.h;
+
+#if defined(CONFIG_JZ4810_COMPRESS)
+	needroom += ((480 * 32 + 7) >> 3) * 272*2;
+#else
+	needroom += ((480 * 32 + 7) >> 3) * 272*2;
+#endif
+
+#endif
+
+	for (page_shift = 0; page_shift < 12; page_shift++)
+		if ((PAGE_SIZE << page_shift) >= needroom)
+			break;
+
+	if (cfb && cfb->fb.screen_base) {
+		iounmap(cfb->fb.screen_base);
+		cfb->fb.screen_base = NULL;
+		release_mem_region(cfb->fb.fix.smem_start,
+				   cfb->fb.fix.smem_len);
+	}
+
+	if (lcd_palette) {
+		map = virt_to_page(lcd_palette);
+		clear_bit(PG_reserved, &map->flags);
+		free_pages((int)lcd_palette, 0);
+	}
+
+	if (lcd_frame0) {
+		for (tmp=(unsigned char *)lcd_frame0;
+		     tmp < lcd_frame0 + (PAGE_SIZE << page_shift);
+		     tmp += PAGE_SIZE) {
+			map = virt_to_page(tmp);
+			clear_bit(PG_reserved, &map->flags);
+		}
+		free_pages((int)lcd_frame0, page_shift);
+	}
+}
+
+static int calc_pal_size(struct jz4810lcd_info * lcd_info)
+{
+	unsigned int pal_size;
+
+	switch ( lcd_info->osd.fg0.bpp ) {
+	case 1:
+		pal_size = 4;
+		break;
+	case 2:
+		pal_size = 8;
+		break;
+	case 4:
+		pal_size = 32;
+		break;
+	case 8:
+	default:
+		pal_size = 512;
+	}
+
+	pal_size /= 4;
+
+	return pal_size;
+}
+/* initial dma descriptors */
+static void jz4810fb_descriptor_init( struct jz4810lcd_info * lcd_info )
+{
+
+	unsigned int pal_size;
+
+	pal_size = calc_pal_size(lcd_info);
+
+	dma0_desc_palette 	= dma_desc_base + 0;
+	dma0_desc0 		= dma_desc_base + 1;
+	dma0_desc1 		= dma_desc_base + 2;
+	dma0_desc_cmd0 		= dma_desc_base + 3; /* use only once */
+	dma0_desc_cmd 		= dma_desc_base + 4;
+	dma1_desc0 		= dma_desc_base + 5;
+	dma1_desc1 		= dma_desc_base + 6;
+
+	/*
+	 * Normal TFT panel's DMA Chan0:
+	 *	TO LCD Panel:
+	 * 		no palette:	dma0_desc0 <<==>> dma0_desc0
+	 * 		palette :	dma0_desc_palette <<==>> dma0_desc0
+	 *	TO TV Encoder:
+	 * 		no palette:	dma0_desc0 <<==>> dma0_desc1
+	 * 		palette:	dma0_desc_palette --> dma0_desc0
+	 * 				--> dma0_desc1 --> dma0_desc_palette --> ...
+	 *
+	 * SMART LCD TFT panel(dma0_desc_cmd)'s DMA Chan0:
+	 *	TO LCD Panel:
+	 * 		no palette:	dma0_desc_cmd <<==>> dma0_desc0
+	 * 		palette :	dma0_desc_palette --> dma0_desc_cmd
+	 * 				--> dma0_desc0 --> dma0_desc_palette --> ...
+	 *	TO TV Encoder:
+	 * 		no palette:	dma0_desc_cmd --> dma0_desc0
+	 * 				--> dma0_desc1 --> dma0_desc_cmd --> ...
+	 * 		palette:	dma0_desc_palette --> dma0_desc_cmd
+	 * 				--> dma0_desc0 --> dma0_desc1
+	 * 				--> dma0_desc_palette --> ...
+	 * DMA Chan1:
+	 *	TO LCD Panel:
+	 * 		dma1_desc0 <<==>> dma1_desc0
+	 *	TO TV Encoder:
+	 * 		dma1_desc0 <<==>> dma1_desc1
+	 */
+
+#if defined(CONFIG_FB_JZ4810_SLCD)
+	/* First CMD descriptors, use only once, cmd_num isn't 0 */
+	dma0_desc_cmd0->next_desc 	= (unsigned int)virt_to_phys(dma0_desc0);
+	dma0_desc_cmd0->databuf 	= (unsigned int)virt_to_phys((void *)lcd_cmdbuf);
+	dma0_desc_cmd0->frame_id 	= (unsigned int)0x0da0cad0; /* dma0's cmd0 */
+	dma0_desc_cmd0->cmd 		= LCD_CMD_CMD | 3; /* command */
+	dma0_desc_cmd0->offsize 	= 0;
+	dma0_desc_cmd0->page_width 	= 0;
+	dma0_desc_cmd0->cmd_num 	= 3;
+
+	/* Dummy Command Descriptor, cmd_num is 0 */
+	dma0_desc_cmd->next_desc 	= (unsigned int)virt_to_phys(dma0_desc0);
+	dma0_desc_cmd->databuf 		= 0;
+	dma0_desc_cmd->frame_id 	= (unsigned int)0x0da000cd; /* dma0's cmd0 */
+	dma0_desc_cmd->cmd 		= LCD_CMD_CMD | 0; /* dummy command */
+	dma0_desc_cmd->cmd_num 		= 0;
+	dma0_desc_cmd->offsize 		= 0;
+	dma0_desc_cmd->page_width 	= 0;
+
+	/* Palette Descriptor */
+	dma0_desc_palette->next_desc 	= (unsigned int)virt_to_phys(dma0_desc_cmd0);
+#else
+	/* Palette Descriptor */
+	dma0_desc_palette->next_desc 	= (unsigned int)virt_to_phys(dma0_desc0);
+#endif
+	dma0_desc_palette->databuf 	= (unsigned int)virt_to_phys((void *)lcd_palette);
+	dma0_desc_palette->frame_id 	= (unsigned int)0xaaaaaaaa;
+	dma0_desc_palette->cmd 		= LCD_CMD_PAL | pal_size; /* Palette Descriptor */
+
+	/* DMA0 Descriptor0 */
+	if ( lcd_info->panel.cfg & LCD_CFG_TVEN ) /* TVE mode */
+		dma0_desc0->next_desc 	= (unsigned int)virt_to_phys(dma0_desc1);
+	else{			/* Normal TFT LCD */
+#if defined(CONFIG_FB_JZ4810_SLCD)
+			dma0_desc0->next_desc = (unsigned int)virt_to_phys(dma0_desc_cmd);
+#else
+			dma0_desc0->next_desc = (unsigned int)virt_to_phys(dma0_desc0);
+#endif
+	}
+
+	dma0_desc0->databuf = virt_to_phys((void *)lcd_frame0);
+	dma0_desc0->frame_id = (unsigned int)0x0000da00; /* DMA0'0 */
+
+	/* DMA0 Descriptor1 */
+	if ( lcd_info->panel.cfg & LCD_CFG_TVEN ) { /* TVE mode */
+		if (lcd_info->osd.fg0.bpp <= 8) /* load palette only once at setup */
+			dma0_desc1->next_desc = (unsigned int)virt_to_phys(dma0_desc_palette);
+		else
+#if defined(CONFIG_FB_JZ4810_SLCD)  /* for smatlcd */
+			dma0_desc1->next_desc = (unsigned int)virt_to_phys(dma0_desc_cmd);
+#else
+			dma0_desc1->next_desc = (unsigned int)virt_to_phys(dma0_desc0);
+#endif
+		dma0_desc1->frame_id = (unsigned int)0x0000da01; /* DMA0'1 */
+	}else{  //lltang add here
+		dma0_desc1->next_desc = (unsigned int)virt_to_phys(dma0_desc1);
+		dma0_desc1->databuf = virt_to_phys((void *)lcd_frame2_0);
+		dma0_desc1->frame_id = (unsigned int)0x0000da01; /* DMA0'1 */		
+	}
+
+
+	if (lcd_info->osd.fg0.bpp <= 8){ /* load palette only once at setup */
+		REG_LCD_DA0 = virt_to_phys(dma0_desc_palette);
+	}else {
+#if defined(CONFIG_FB_JZ4810_SLCD)  /* for smartlcd */
+		REG_LCD_DA0 = virt_to_phys(dma0_desc_cmd0); //smart lcd
+#else
+		REG_LCD_DA0 = virt_to_phys(dma0_desc0); //tft
+#endif
+	}
+
+	/* DMA1 Descriptor0 */
+	if ( lcd_info->panel.cfg & LCD_CFG_TVEN ) /* TVE mode */
+		dma1_desc0->next_desc = (unsigned int)virt_to_phys(dma1_desc1);
+	else			/* Normal TFT LCD */
+		dma1_desc0->next_desc = (unsigned int)virt_to_phys(dma1_desc0);
+
+	dma1_desc0->databuf = virt_to_phys((void *)lcd_frame1);
+	dma1_desc0->frame_id = (unsigned int)0x0000da10; /* DMA1'0 */
+
+	/* DMA1 Descriptor1 */
+	if ( lcd_info->panel.cfg & LCD_CFG_TVEN ) { /* TVE mode */
+		dma1_desc1->next_desc = (unsigned int)virt_to_phys(dma1_desc0);
+		dma1_desc1->frame_id = (unsigned int)0x0000da11; /* DMA1'1 */
+	}else{
+		dma1_desc1->next_desc = (unsigned int)virt_to_phys(dma1_desc1);
+		dma1_desc1->databuf = virt_to_phys((void *)lcd_frame2_1);
+		dma1_desc1->frame_id = (unsigned int)0x0000da11; /* DMA1'1 */
+	}
+
+	REG_LCD_DA1 = virt_to_phys(dma1_desc0);	/* set Dma-chan1's Descripter Addrress */
+	printk("%s\t, %08x\n",__func__,REG_LCD_DA1);
+	dma_cache_wback_inv((unsigned int)(dma_desc_base), (DMA_DESC_NUM)*sizeof(struct jz4810_lcd_dma_desc));
+	
+#if 0
+	/* Palette Descriptor */
+	if ( lcd_info->panel.cfg & LCD_CFG_LCDPIN_SLCD )
+//		dma0_desc_palette->next_desc = (unsigned int)virt_to_phys(dma0_desc_cmd);
+		dma0_desc_palette->next_desc = (unsigned int)virt_to_phys(dma0_desc_cmd1);
+	else
+		dma0_desc_palette->next_desc = (unsigned int)virt_to_phys(dma0_desc0);
+	dma0_desc_palette->databuf = (unsigned int)virt_to_phys((void *)lcd_palette);
+	dma0_desc_palette->frame_id = (unsigned int)0xaaaaaaaa;
+	dma0_desc_palette->cmd 	= LCD_CMD_PAL | pal_size; /* Palette Descriptor */
+
+	/* Dummy Command Descriptor, cmd_num is 0 */
+	dma0_desc_cmd->next_desc = (unsigned int)virt_to_phys(dma0_desc0);
+	dma0_desc_cmd->databuf 	= (unsigned int)virt_to_phys((void *)lcd_cmdbuf);
+	dma0_desc_cmd->frame_id = (unsigned int)0x0da0cad0; /* dma0's cmd0 */
+	dma0_desc_cmd->cmd 	= LCD_CMD_CMD | 3; /* dummy command */
+	dma0_desc_cmd->offsize 	= 0; /* dummy command */
+	dma0_desc_cmd->page_width = 0; /* dummy command */
+	dma0_desc_cmd->cmd_num 	= 3;
+
+//---------------------------------
+	dma0_desc_cmd1->next_desc = (unsigned int)virt_to_phys(dma0_desc0);
+	dma0_desc_cmd1->databuf 	= 0;
+	dma0_desc_cmd1->frame_id = (unsigned int)0x0da0cad1; /* dma0's cmd0 */
+	dma0_desc_cmd1->cmd 	= LCD_CMD_CMD | 0; /* dummy command */
+	dma0_desc_cmd1->cmd_num 	= 0;
+	dma0_desc_cmd1->offsize 	= 0; /* dummy command */
+	dma0_desc_cmd1->page_width = 0; /* dummy command */
+//-----------------------------------
+	/* DMA0 Descriptor0 */
+	if ( lcd_info->panel.cfg & LCD_CFG_TVEN ) /* TVE mode */
+		dma0_desc0->next_desc = (unsigned int)virt_to_phys(dma0_desc1);
+	else{			/* Normal TFT LCD */
+		if (lcd_info->osd.fg0.bpp <= 8) /* load palette only once at setup?? */
+//			dma0_desc0->next_desc = (unsigned int)virt_to_phys(dma0_desc_palette); //tft
+			dma0_desc0->next_desc = (unsigned int)virt_to_phys(dma0_desc_cmd); // smart lcd
+		else if ( lcd_info->panel.cfg & LCD_CFG_LCDPIN_SLCD )
+			dma0_desc0->next_desc = (unsigned int)virt_to_phys(dma0_desc_cmd1);
+//			dma0_desc0->next_desc = (unsigned int)virt_to_phys(dma0_desc_cmd);
+		else
+			dma0_desc0->next_desc = (unsigned int)virt_to_phys(dma0_desc0);
+	}
+
+	dma0_desc0->databuf = virt_to_phys((void *)lcd_frame0);
+	dma0_desc0->frame_id = (unsigned int)0x0000da00; /* DMA0'0 */
+
+	/* DMA0 Descriptor1 */
+	if ( lcd_info->panel.cfg & LCD_CFG_TVEN ) { /* TVE mode */
+		if (lcd_info->osd.fg0.bpp <= 8) /* load palette only once at setup?? */
+			dma0_desc1->next_desc = (unsigned int)virt_to_phys(dma0_desc_palette);
+
+		else if ( lcd_info->panel.cfg & LCD_CFG_LCDPIN_SLCD )
+			dma0_desc1->next_desc = (unsigned int)virt_to_phys(dma0_desc_cmd);
+		else
+			dma0_desc1->next_desc = (unsigned int)virt_to_phys(dma0_desc0);
+		dma0_desc1->frame_id = (unsigned int)0x0000da01; /* DMA0'1 */
+	}
+
+	/* DMA1 Descriptor0 */
+	if ( lcd_info->panel.cfg & LCD_CFG_TVEN ) /* TVE mode */
+		dma1_desc0->next_desc = (unsigned int)virt_to_phys(dma1_desc1);
+	else			/* Normal TFT LCD */
+		dma1_desc0->next_desc = (unsigned int)virt_to_phys(dma1_desc0);
+
+	dma1_desc0->databuf = virt_to_phys((void *)lcd_frame1);
+	dma1_desc0->frame_id = (unsigned int)0x0000da10; /* DMA1'0 */
+
+	/* DMA1 Descriptor1 */
+	if ( lcd_info->panel.cfg & LCD_CFG_TVEN ) { /* TVE mode */
+		dma1_desc1->next_desc = (unsigned int)virt_to_phys(dma1_desc0);
+		dma1_desc1->frame_id = (unsigned int)0x0000da11; /* DMA1'1 */
+	}
+
+	if (lcd_info->osd.fg0.bpp <= 8) /* load palette only once at setup?? */
+		REG_LCD_DA0 = virt_to_phys(dma0_desc_palette);
+	else
+//		REG_LCD_DA0 = virt_to_phys(dma0_desc_cmd); //smart lcd
+		REG_LCD_DA0 = virt_to_phys(dma0_desc0); //tft
+	REG_LCD_DA1 = virt_to_phys(dma1_desc0);	/* set Dma-chan1's Descripter Addrress */
+	dma_cache_wback_inv((unsigned int)(dma_desc_base), (DMA_DESC_NUM)*sizeof(struct jz4810_lcd_dma_desc));
+#endif
+}
+
+static void jz4810fb_set_panel_mode( struct jz4810lcd_info * lcd_info )
+{
+	struct jz4810lcd_panel_t *panel = &lcd_info->panel;
+#ifdef CONFIG_JZ4810_VGA_DISPLAY
+	REG_TVE_CTRL |= TVE_CTRL_DAPD;
+	REG_TVE_CTRL &= ~( TVE_CTRL_DAPD1 | TVE_CTRL_DAPD2 | TVE_CTRL_DAPD3);
+#endif
+	/* set bpp */
+	lcd_info->panel.ctrl &= ~LCD_CTRL_BPP_MASK;
+	if ( lcd_info->osd.fg0.bpp == 1 )
+		lcd_info->panel.ctrl |= LCD_CTRL_BPP_1;
+	else if ( lcd_info->osd.fg0.bpp == 2 )
+		lcd_info->panel.ctrl |= LCD_CTRL_BPP_2;
+	else if ( lcd_info->osd.fg0.bpp == 4 )
+		lcd_info->panel.ctrl |= LCD_CTRL_BPP_4;
+	else if ( lcd_info->osd.fg0.bpp == 8 )
+		lcd_info->panel.ctrl |= LCD_CTRL_BPP_8;
+	else if ( lcd_info->osd.fg0.bpp == 15 ){
+		lcd_info->panel.ctrl |= LCD_CTRL_BPP_16 | LCD_CTRL_RGB555;
+	}
+	else if ( lcd_info->osd.fg0.bpp == 16 ){
+		lcd_info->panel.ctrl |= LCD_CTRL_BPP_16 ;
+		lcd_info->panel.ctrl &= ~(LCD_CTRL_RGB555);
+	}
+	else if ( lcd_info->osd.fg0.bpp > 16 && lcd_info->osd.fg0.bpp < 32+1 ) {
+		lcd_info->osd.fg0.bpp = 32;
+		lcd_info->panel.ctrl |= LCD_CTRL_BPP_18_24;
+	}
+	else {
+		printk("The BPP %d is not supported\n", lcd_info->osd.fg0.bpp);
+		lcd_info->osd.fg0.bpp = 32;
+		lcd_info->panel.ctrl |= LCD_CTRL_BPP_18_24;
+	}
+
+	lcd_info->panel.cfg |= LCD_CFG_NEWDES; /* use 8words descriptor always */
+
+	REG_LCD_CTRL = lcd_info->panel.ctrl; /* LCDC Controll Register */
+	REG_LCD_CFG = lcd_info->panel.cfg; /* LCDC Configure Register */
+	REG_SLCD_CFG = lcd_info->panel.slcd_cfg; /* Smart LCD Configure Register */
+
+	if ( lcd_info->panel.cfg & LCD_CFG_LCDPIN_SLCD ) /* enable Smart LCD DMA */
+		REG_SLCD_CTRL = SLCD_CTRL_DMA_EN;
+
+	switch ( lcd_info->panel.cfg & LCD_CFG_MODE_MASK ) {
+	case LCD_CFG_MODE_GENERIC_TFT:
+	case LCD_CFG_MODE_INTER_CCIR656:
+	case LCD_CFG_MODE_NONINTER_CCIR656:
+	case LCD_CFG_MODE_SLCD:
+	default:		/* only support TFT16 TFT32, not support STN and Special TFT by now(10-06-2008)*/
+		REG_LCD_VAT = (((panel->blw + panel->w + panel->elw + panel->hsw)) << 16) | (panel->vsw + panel->bfw + panel->h + panel->efw);
+		REG_LCD_DAH = ((panel->hsw + panel->blw) << 16) | (panel->hsw + panel->blw + panel->w);
+		REG_LCD_DAV = ((panel->vsw + panel->bfw) << 16) | (panel->vsw + panel->bfw + panel->h);
+		REG_LCD_HSYNC = (0 << 16) | panel->hsw;
+		REG_LCD_VSYNC = (0 << 16) | panel->vsw;
+		break;
+	}
+}
+
+
+static void jz4810fb_set_osd_mode( struct jz4810lcd_info * lcd_info )
+{
+	D("%s, %d\n", __FILE__, __LINE__ );
+	lcd_info->osd.osd_ctrl &= ~(LCD_OSDCTRL_OSDBPP_MASK);
+	if ( lcd_info->osd.fg1.bpp == 15 )
+		lcd_info->osd.osd_ctrl |= LCD_OSDCTRL_OSDBPP_15_16|LCD_OSDCTRL_RGB555;
+	else if ( lcd_info->osd.fg1.bpp == 16 )
+		lcd_info->osd.osd_ctrl |= LCD_OSDCTRL_OSDBPP_15_16|LCD_OSDCTRL_RGB565;
+	else {
+		lcd_info->osd.fg1.bpp = 32;
+		lcd_info->osd.osd_ctrl |= LCD_OSDCTRL_OSDBPP_18_24;
+	}
+
+	REG_LCD_OSDC 	= lcd_info->osd.osd_cfg; /* F0, F1, alpha, */
+
+	REG_LCD_OSDCTRL = lcd_info->osd.osd_ctrl; /* IPUEN, bpp */
+	REG_LCD_RGBC  	= lcd_info->osd.rgb_ctrl;
+	REG_LCD_BGC  	= lcd_info->osd.bgcolor;
+	REG_LCD_KEY0 	= lcd_info->osd.colorkey0;
+	REG_LCD_KEY1 	= lcd_info->osd.colorkey1;
+	REG_LCD_ALPHA 	= lcd_info->osd.alpha;
+	REG_LCD_IPUR 	= lcd_info->osd.ipu_restart;
+}
+
+
+unsigned int times0 = 1;
+static void jz4810fb_change_desc( struct jz4810lcd_info * lcd_info )
+{
+	int fg0_line_size, fg0_frm_size, fg1_line_size, fg1_frm_size,bpp0,bpp1;
+	int from00_to_desc01, from10_to_desc11;
+	unsigned int da0,da1 ,need_change=0;
+
+	/* Foreground 0  */
+	if ( lcd_info->osd.fg0.x >= lcd_info->panel.w )
+		lcd_info->osd.fg0.x = lcd_info->panel.w;
+	if ( lcd_info->osd.fg0.y >= lcd_info->panel.h )
+		lcd_info->osd.fg0.y = lcd_info->panel.h;
+	if ( lcd_info->osd.fg0.x + lcd_info->osd.fg0.w > lcd_info->panel.w )
+		lcd_info->osd.fg0.w = lcd_info->panel.w - lcd_info->osd.fg0.x;
+	if ( lcd_info->osd.fg0.y + lcd_info->osd.fg0.h > lcd_info->panel.h )
+		lcd_info->osd.fg0.h = lcd_info->panel.h - lcd_info->osd.fg0.y;
+
+#if 0
+	/* Foreground 1 */
+	/* Case TVE ??? TVE 720x573 or 720x480*/
+	if ( lcd_info->osd.fg1.x >= lcd_info->panel.w )
+		lcd_info->osd.fg1.x = lcd_info->panel.w;
+	if ( lcd_info->osd.fg1.y >= lcd_info->panel.h )
+		lcd_info->osd.fg1.y = lcd_info->panel.h;
+	if ( lcd_info->osd.fg1.x + lcd_info->osd.fg1.w > lcd_info->panel.w )
+		lcd_info->osd.fg1.w = lcd_info->panel.w - lcd_info->osd.fg1.x;
+	if ( lcd_info->osd.fg1.y + lcd_info->osd.fg1.h > lcd_info->panel.h )
+		lcd_info->osd.fg1.h = lcd_info->panel.h - lcd_info->osd.fg1.y;
+#endif
+
+	bpp0 = bpp_to_data_bpp(lcd_info->osd.fg0.bpp);
+	bpp1 = bpp_to_data_bpp(lcd_info->osd.fg1.bpp);
+
+	fg0_line_size = (lcd_info->osd.fg0.w*bpp0/8);
+	fg0_line_size = ((fg0_line_size+3)>>2)<<2; /* word aligned */
+	fg0_frm_size = fg0_line_size * lcd_info->osd.fg0.h;
+
+	fg1_line_size = lcd_info->osd.fg1.w*bpp1/8;
+	fg1_line_size = ((fg1_line_size+3)>>2)<<2; /* word aligned */
+	fg1_frm_size = fg1_line_size * lcd_info->osd.fg1.h;
+  
+	printk("lcd_info->osd.fg0.w ------> %d \n",lcd_info->osd.fg0.w);
+	printk("lcd_info->osd.fg0.h ------> %d \n",lcd_info->osd.fg0.h);
+	printk("lcd_info->osd.fg0.bpp ------> %d \n",lcd_info->osd.fg0.bpp);
+
+	printk("lcd_info->osd.fg_change -> %d\n",lcd_info->osd.fg_change );
+	
+	if ( lcd_info->osd.fg_change ) {
+		if ( lcd_info->osd.fg_change & FG0_CHANGE_POSITION ) { /* F1 change position */
+			if(REG_LCD_XYP0 != (lcd_info->osd.fg0.y << 16 | lcd_info->osd.fg0.x)){
+				need_change = 1;
+				printk("change xyp0\n");
+			}
+			REG_LCD_XYP0 = lcd_info->osd.fg0.y << 16 | lcd_info->osd.fg0.x;
+		}
+		if ( lcd_info->osd.fg_change & FG1_CHANGE_POSITION ) { /* F1 change position */
+			if(REG_LCD_XYP1 != (lcd_info->osd.fg1.y << 16 | lcd_info->osd.fg1.x)){
+				need_change = 1;
+				printk("change xyp1\n");
+			}
+			REG_LCD_XYP1 = lcd_info->osd.fg1.y << 16 | lcd_info->osd.fg1.x;
+		}
+		if ( !(lcd_info->osd.osd_ctrl & LCD_OSDCTRL_IPU) &&
+		     (lcd_info->osd.fg_change != FG_CHANGE_ALL) ){
+
+			if(lcd_info->osd.fg_change & FG0_CHANGE_SIZE){
+				if(REG_LCD_SIZE0 != ((lcd_info->osd.fg0.h<<16) | lcd_info->osd.fg0.w)){
+					printk("change size0\n");
+					need_change = 1;
+				}
+			}
+			
+			if(lcd_info->osd.fg_change & FG1_CHANGE_SIZE){
+				if(REG_LCD_SIZE1 != ((lcd_info->osd.fg1.h<<16) | lcd_info->osd.fg1.w)){
+					printk("change size1\n");
+					need_change = 1;
+				}
+			}
+		}else
+			need_change = 0;
+
+#if 1
+		if(need_change){
+			printk("\nset change\n");
+			REG_LCD_OSDCTRL |= LCD_OSDCTRL_CHANGES;
+		
+//			while(!(REG_LCD_OSDS & LCD_OSDS_READY));	/* fix in the future, Wolfgang, 06-20-2008 */
+
+		}
+#endif
+	/*judge the current desc,if dma0_desc0 is working ,change it to dma0_desc1*/
+		if(lcd_info->osd.fg_change & FG0_CHANGE_SIZE){
+			printk("FG0_CHANGE_SIZE\n");
+			if ( lcd_info->panel.cfg & LCD_CFG_TVEN ) { /* output to TV */
+				dma0_desc0->cmd = dma0_desc1->cmd = (fg0_frm_size/4)/2;
+				dma0_desc0->offsize = dma0_desc1->offsize = fg0_line_size/4;
+				dma0_desc0->page_width = dma0_desc1->page_width = fg0_line_size/4;
+				dma0_desc1->databuf = virt_to_phys((void *)(lcd_frame0 + fg0_line_size));
+				dma0_desc0->desc_size = dma0_desc1->desc_size = lcd_info->osd.fg0.h << 16 | lcd_info->osd.fg0.w;
+				REG_LCD_DA0 = (unsigned int)virt_to_phys(dma0_desc0); //tft
+			}else{
+				da0 = REG_LCD_DA0;
+				if(da0 == lcd_info->pdma00)
+					from00_to_desc01 = 1;
+				else
+					from00_to_desc01 = 0;
+
+				if(lcd_info->is0_compressed){
+					if(from00_to_desc01){
+						printk("\n----fg0-----compressed-----------from 00 to o01-\n");
+						dma0_desc1->cmd = lcd_info->osd.fg0.h;
+						dma0_desc1->cmd |= LCD_CMD_UNCOMPRESS_EN;
+						if(lcd_info->without_alpha)
+							dma0_desc1->cmd  |= LCD_CMD_UNCOMPRESS_WITHOUT_ALPHA;
+						
+						dma0_desc1->offsize =  (lcd_info->osd.fg0.w * bpp0 /32 )+ 1; //word
+						dma0_desc1->page_width = 0;
+						dma0_desc1->desc_size = lcd_info->osd.fg0.h << 16 | lcd_info->osd.fg0.w;//pixel
+						dma0_desc1->next_desc = (unsigned int)virt_to_phys(dma0_desc1);
+						dma_cache_wback((unsigned int)(dma_desc_base),
+								(DMA_DESC_NUM)*sizeof(struct jz4810_lcd_dma_desc));
+						dma0_desc0->next_desc = (unsigned int)virt_to_phys(dma0_desc1);
+						REG_LCD_DA0 = (unsigned int)virt_to_phys(dma0_desc1); //tft
+						REG_LCD_SIZE0 = (lcd_info->osd.fg0.h<<16)|lcd_info->osd.fg0.w;
+					}else{
+						printk("\n---fg0------compressed-----------from 01 to o00-\n");	
+						dma0_desc0->cmd = lcd_info->osd.fg0.h;
+						dma0_desc0->cmd |= LCD_CMD_UNCOMPRESS_EN;
+						if(lcd_info->without_alpha)
+							dma0_desc0->cmd  |= LCD_CMD_UNCOMPRESS_WITHOUT_ALPHA;
+						
+						dma0_desc0->offsize =  (lcd_info->osd.fg0.w * bpp0 /32 )+ 1; //word
+						dma0_desc0->page_width = 0;
+						dma0_desc0->desc_size = lcd_info->osd.fg0.h << 16 | lcd_info->osd.fg0.w;//pixel
+						dma0_desc0->next_desc = (unsigned int)virt_to_phys(dma0_desc0);
+						dma_cache_wback((unsigned int)(dma_desc_base),
+								(DMA_DESC_NUM)*sizeof(struct jz4810_lcd_dma_desc));
+						dma0_desc1->next_desc = (unsigned int)virt_to_phys(dma0_desc0);
+						REG_LCD_DA0 = (unsigned int)virt_to_phys(dma0_desc0);
+						REG_LCD_SIZE0 = (lcd_info->osd.fg0.h<<16)|lcd_info->osd.fg0.w;
+					}
+				}else{
+					if(times0--){
+						dma0_desc0->cmd = fg0_frm_size/4;
+						dma0_desc0->offsize = 0;
+						dma0_desc0->page_width = 0;
+						dma0_desc0->desc_size = lcd_info->osd.fg0.h << 16 | lcd_info->osd.fg0.w;
+						REG_LCD_DA0 = virt_to_phys(dma0_desc0);
+						REG_LCD_SIZE0 = (lcd_info->osd.fg0.h<<16)|lcd_info->osd.fg0.w; //must set at first fime!!
+					}else{
+						if(from00_to_desc01){
+							printk("\n----fg0-----no compress------------from 00 to 01-\n");
+							dma0_desc1->cmd = fg0_frm_size/4;
+							dma0_desc1->offsize =0;
+							dma0_desc1->page_width = 0;
+							dma0_desc1->desc_size = lcd_info->osd.fg0.h << 16 | lcd_info->osd.fg0.w;
+							dma0_desc1->next_desc = (unsigned int)virt_to_phys(dma0_desc1);
+							dma_cache_wback((unsigned int)(dma_desc_base), 
+									(DMA_DESC_NUM)*sizeof(struct jz4810_lcd_dma_desc));
+							dma0_desc0->next_desc = (unsigned int)virt_to_phys(dma0_desc1);
+							REG_LCD_DA0 = (unsigned int)virt_to_phys(dma0_desc1); //tft
+							REG_LCD_SIZE0 = (lcd_info->osd.fg0.h<<16)|lcd_info->osd.fg0.w;
+
+						}else{
+							printk("\n----fg0-----no compress------------from 01 to 00-\n");
+							dma0_desc0->cmd = fg0_frm_size/4;
+							dma0_desc0->offsize =0;
+							dma0_desc0->page_width = 0;
+							dma0_desc0->desc_size = lcd_info->osd.fg0.h << 16 | lcd_info->osd.fg0.w;
+							dma0_desc0->next_desc = (unsigned int)virt_to_phys(dma0_desc0);
+							dma_cache_wback((unsigned int)(dma_desc_base),
+									(DMA_DESC_NUM)*sizeof(struct jz4810_lcd_dma_desc));
+							dma0_desc1->next_desc = (unsigned int)virt_to_phys(dma0_desc0);
+							REG_LCD_DA0 = (unsigned int)virt_to_phys(dma0_desc0); //tft
+							REG_LCD_SIZE0 = (lcd_info->osd.fg0.h<<16)|lcd_info->osd.fg0.w;
+						}
+					}
+				}
+			}
+		}
+
+		if(lcd_info->osd.fg_change & FG1_CHANGE_SIZE){
+			if ( lcd_info->panel.cfg & LCD_CFG_TVEN ) { /* output to TV */
+				dma0_desc0->cmd = dma0_desc1->cmd = (fg0_frm_size/4)/2;
+				dma0_desc0->offsize = dma0_desc1->offsize = fg0_line_size/4;
+				dma0_desc0->page_width = dma0_desc1->page_width = fg0_line_size/4;
+				dma0_desc1->databuf = virt_to_phys((void *)(lcd_frame0 + fg0_line_size));
+				dma0_desc0->desc_size = dma0_desc1->desc_size = lcd_info->osd.fg0.h << 16 | lcd_info->osd.fg0.w;
+				REG_LCD_DA1 = virt_to_phys(dma0_desc1); //tft
+			}else{
+
+				da1 = REG_LCD_DA1;
+				if(REG_LCD_DA1 == lcd_info->pdma10)
+					from10_to_desc11 = 1;
+				else
+					from10_to_desc11 = 0;
+
+				if(lcd_info->is1_compressed){
+					if(from10_to_desc11){
+						printk("\n----fg1-----compressed------------from 10 to 11------------------\n");
+						dma1_desc1->cmd = lcd_info->osd.fg1.h;
+						dma1_desc1->cmd |= LCD_CMD_UNCOMPRESS_EN;
+						if(lcd_info->without_alpha)
+							dma1_desc1->cmd |= LCD_CMD_UNCOMPRESS_WITHOUT_ALPHA;
+						
+						dma1_desc1->offsize  = (lcd_info->osd.fg1.w * bpp1 /32 )+ 1; //word
+						dma1_desc1->page_width = 0;
+						dma1_desc1->desc_size = lcd_info->osd.fg1.h << 16 | lcd_info->osd.fg1.w;//pixel
+						dma1_desc1->next_desc = (unsigned int)virt_to_phys(dma1_desc1);
+						dma_cache_wback((unsigned int)(dma_desc_base),
+								(DMA_DESC_NUM)*sizeof(struct jz4810_lcd_dma_desc));
+						dma1_desc0->next_desc = (unsigned int)virt_to_phys(dma1_desc1);
+						REG_LCD_DA1 = virt_to_phys(dma1_desc1); //tft
+						REG_LCD_SIZE1 = lcd_info->osd.fg1.h << 16 | lcd_info->osd.fg1.w;//pixel
+					}else{
+						printk("\n----fg1-----compressed------------from 11 to 10------------------\n");
+						dma1_desc0->cmd = lcd_info->osd.fg1.h;
+						dma1_desc0->cmd |= LCD_CMD_UNCOMPRESS_EN;
+						if(lcd_info->without_alpha)
+							dma1_desc0->cmd |= LCD_CMD_UNCOMPRESS_WITHOUT_ALPHA;
+						
+						dma1_desc0->offsize  = (lcd_info->osd.fg1.w * bpp1 /32 )+ 1; //word
+						dma1_desc0->page_width = 0;
+						dma1_desc0->desc_size = lcd_info->osd.fg1.h << 16 | lcd_info->osd.fg1.w;//pixel
+						dma1_desc0->next_desc = (unsigned int)virt_to_phys(dma1_desc0);
+						dma_cache_wback((unsigned int)(dma_desc_base),
+								(DMA_DESC_NUM)*sizeof(struct jz4810_lcd_dma_desc));
+						dma1_desc1->next_desc = (unsigned int)virt_to_phys(dma1_desc0);
+						REG_LCD_DA1 = virt_to_phys(dma1_desc0); //tft
+						REG_LCD_SIZE1 = lcd_info->osd.fg1.h << 16 | lcd_info->osd.fg1.w;//pixel
+					}
+				}else{
+					if(from10_to_desc11){
+						printk("\n----fg1-- no ---compress------------from 10 to 11------------------\n");
+						dma1_desc1->cmd = fg1_frm_size/4;
+						dma1_desc1->offsize =  0;
+						dma1_desc1->page_width = 0;
+						dma1_desc1->desc_size= lcd_info->osd.fg1.h << 16 | lcd_info->osd.fg1.w;
+						dma1_desc1->next_desc = (unsigned int)virt_to_phys(dma1_desc1);
+						REG_LCD_SIZE1 = lcd_info->osd.fg1.h << 16|lcd_info->osd.fg1.w;
+						dma_cache_wback((unsigned int)(dma_desc_base),
+								(DMA_DESC_NUM)*sizeof(struct jz4810_lcd_dma_desc));
+						dma1_desc0->next_desc = (unsigned int)virt_to_phys(dma1_desc1);
+						REG_LCD_DA1 = virt_to_phys(dma1_desc1); //tft
+						REG_LCD_SIZE1 = lcd_info->osd.fg1.h << 16 | lcd_info->osd.fg1.w;//pixel			
+					}else{
+						printk("\n----fg1---no --compressed------------from 11 to 10------------------\n");
+						dma1_desc0->cmd = fg1_frm_size/4;
+						dma1_desc0->offsize = 0;
+						dma1_desc0->page_width = 0;
+						dma1_desc0->desc_size = lcd_info->osd.fg1.h << 16 | lcd_info->osd.fg1.w;
+						dma1_desc0->next_desc = (unsigned int)virt_to_phys(dma1_desc0);
+						REG_LCD_SIZE1 = lcd_info->osd.fg1.h << 16|lcd_info->osd.fg1.w;
+						dma_cache_wback((unsigned int)(dma_desc_base),
+									(DMA_DESC_NUM)*sizeof(struct jz4810_lcd_dma_desc));
+						dma1_desc1->next_desc =  (unsigned int)virt_to_phys(dma1_desc0);
+						REG_LCD_DA1 = virt_to_phys(dma1_desc0); //tft
+						REG_LCD_SIZE1 = lcd_info->osd.fg1.h << 16 | lcd_info->osd.fg1.w;//pixel
+					}
+				}//is compressed
+			}//config tve
+		}//fg1 change size
+
+		dma_cache_wback((unsigned int)(dma_desc_base), (DMA_DESC_NUM)*sizeof(struct jz4810_lcd_dma_desc));
+		lcd_info->osd.fg_change = FG_NOCHANGE; /* clear change flag */
+
+		if(need_change){
+//			while(REG_LCD_OSDCTRL & LCD_OSDCTRL_CHANGES);
+		}
+	}//change
+}
+
+static void jz4810fb_foreground_resize( struct jz4810lcd_info * lcd_info )
+{
+	int fg0_line_size, fg0_frm_size, fg1_line_size, fg1_frm_size;
+	int bpp0, bpp1;
+	unsigned int pal_size;
+
+	/*
+	 * NOTE:
+	 * Foreground change sequence:
+	 * 	1. Change Position Registers -> LCD_OSDCTL.Change;
+	 * 	2. LCD_OSDCTRL.Change -> descripter->Size
+	 * Foreground, only one of the following can be change at one time:
+	 * 	1. F0 size;
+	 *	2. F0 position
+	 * 	3. F1 size
+	 *	4. F1 position
+	 */
+
+	/*
+	 * The rules of f0, f1's position:
+	 * 	f0.x + f0.w <= panel.w;
+	 * 	f0.y + f0.h <= panel.h;
+	 *
+	 * When output is LCD panel, fg.y and fg.h can be odd number or even number.
+	 * When output is TVE, as the TVE has odd frame and even frame,
+	 * to simplified operation, fg.y and fg.h should be even number always.
+	 *
+	 */
+
+	printk("lcd_info->osd.fg0.bpp : -> %d\n",lcd_info->osd.fg0.bpp);
+	printk("lcd_info->osd.fg1.bpp : -> %d\n",lcd_info->osd.fg1.bpp);
+	
+	/* Foreground 0  */
+	if ( lcd_info->osd.fg0.x >= lcd_info->panel.w )
+		lcd_info->osd.fg0.x = lcd_info->panel.w;
+	if ( lcd_info->osd.fg0.y >= lcd_info->panel.h )
+		lcd_info->osd.fg0.y = lcd_info->panel.h;
+	if ( lcd_info->osd.fg0.x + lcd_info->osd.fg0.w > lcd_info->panel.w )
+		lcd_info->osd.fg0.w = lcd_info->panel.w - lcd_info->osd.fg0.x;
+	if ( lcd_info->osd.fg0.y + lcd_info->osd.fg0.h > lcd_info->panel.h )
+		lcd_info->osd.fg0.h = lcd_info->panel.h - lcd_info->osd.fg0.y;
+
+#if 0
+	/* Foreground 1 */
+	/* Case TVE ??? TVE 720x573 or 720x480*/
+	if ( lcd_info->osd.fg1.x >= lcd_info->panel.w )
+		lcd_info->osd.fg1.x = lcd_info->panel.w;
+	if ( lcd_info->osd.fg1.y >= lcd_info->panel.h )
+		lcd_info->osd.fg1.y = lcd_info->panel.h;
+	if ( lcd_info->osd.fg1.x + lcd_info->osd.fg1.w > lcd_info->panel.w )
+		lcd_info->osd.fg1.w = lcd_info->panel.w - lcd_info->osd.fg1.x;
+	if ( lcd_info->osd.fg1.y + lcd_info->osd.fg1.h > lcd_info->panel.h )
+		lcd_info->osd.fg1.h = lcd_info->panel.h - lcd_info->osd.fg1.y;
+#endif
+//	fg0_line_size = lcd_info->osd.fg0.w*((lcd_info->osd.fg0.bpp+7)/8);
+	bpp0 = bpp_to_data_bpp(lcd_info->osd.fg0.bpp);
+	bpp1 = bpp_to_data_bpp(lcd_info->osd.fg1.bpp);
+	
+	printk("bpp0 : -> %d\n",bpp0);
+	printk("bpp1 : -> %d\n",bpp1);
+	
+	
+	fg0_line_size = (lcd_info->osd.fg0.w * bpp0/8);
+	fg0_line_size = ((fg0_line_size+3)>>2)<<2; /* word aligned */
+	fg0_frm_size = fg0_line_size * lcd_info->osd.fg0.h;
+	
+	fg1_line_size = lcd_info->osd.fg1.w * bpp1/8;
+	fg1_line_size = ((fg1_line_size+3)>>2)<<2; /* word aligned */
+	fg1_frm_size = fg1_line_size * lcd_info->osd.fg1.h;
+
+	printk("lcd_info->osd.fg0.bpp : -> %d\n",lcd_info->osd.fg0.bpp);
+	printk("lcd_info->osd.fg1.bpp : -> %d\n",lcd_info->osd.fg1.bpp);
+	if ( lcd_info->osd.fg_change ) {
+		if ( lcd_info->osd.fg_change & FG0_CHANGE_POSITION ) { /* F1 change position */
+			REG_LCD_XYP0 = lcd_info->osd.fg0.y << 16 | lcd_info->osd.fg0.x;
+		}
+		if ( lcd_info->osd.fg_change & FG1_CHANGE_POSITION ) { /* F1 change position */
+			REG_LCD_XYP1 = lcd_info->osd.fg1.y << 16 | lcd_info->osd.fg1.x;
+		}
+		
+		/* set change */
+		if ( !(lcd_info->osd.osd_ctrl & LCD_OSDCTRL_IPU) &&
+		     (lcd_info->osd.fg_change != FG_CHANGE_ALL) ){
+//			REG_LCD_OSDCTRL |= LCD_OSDCTRL_CHANGES;
+
+			/* wait change ready??? */
+//			while ( !(REG_LCD_OSDS & LCD_OSDS_READY ))	/* fix in the future, Wolfgang, 06-20-2008 */
+				D("wait LCD_OSDS_READY\n");
+		}
+		printk("lcd_info->osd.fg_change -> %d\n",lcd_info->osd.fg_change);
+		if ( lcd_info->osd.fg_change & FG0_CHANGE_SIZE ) { /* change FG0 size */
+			printk("********FG0_CHANGE_SIZE************\n");
+			if ( lcd_info->panel.cfg & LCD_CFG_TVEN ) { /* output to TV */
+				dma0_desc0->cmd = dma0_desc1->cmd = (fg0_frm_size/4)/2;
+				dma0_desc0->offsize = dma0_desc1->offsize
+					= fg0_line_size/4;
+				dma0_desc0->page_width = dma0_desc1->page_width
+					= fg0_line_size/4;
+				dma0_desc1->databuf = virt_to_phys((void *)(lcd_frame0 + fg0_line_size));
+				REG_LCD_DA0 = virt_to_phys(dma0_desc0); //tft
+			}else{
+				if(lcd_info->is0_compressed){
+					printk("***********is0_compressed***********\n");
+					dma0_desc0->cmd = lcd_info->osd.fg0.h;
+					dma0_desc0->cmd |= LCD_CMD_UNCOMPRESS_EN;
+					if(lcd_info->without_alpha)
+						dma0_desc0->cmd  |= LCD_CMD_UNCOMPRESS_WITHOUT_ALPHA;
+					
+					dma0_desc0->offsize =  (lcd_info->osd.fg0.w * bpp0 /32 )+ 1; //word
+					dma0_desc0->page_width = 0;
+				}else{
+					dma0_desc0->cmd = fg0_frm_size/4;
+					if(lcd_info->is0_disPart)
+					{
+						printk("*******is0_disPart*******\n");
+						dma0_desc0->offsize  =fg0_line_size/4;
+						dma0_desc0->page_width  = fg0_line_size/4;   //wrod
+					}
+					else{
+						dma0_desc0->offsize  =0;
+						dma0_desc0->page_width  = 0;
+					}
+				}
+			} //fg0_change_size
+			if(lcd_info->osd.fg_change & FG0_CHANGE_BUF){
+				printk("change buf to 2-0\n");
+				dma0_desc0->databuf = virt_to_phys((void *)(lcd_frame2_0));
+				REG_LCD_SA0 = virt_to_phys((void *)(lcd_frame2_0));
+			}else{
+				printk("change buf to 0\n");
+				dma0_desc0->databuf = virt_to_phys((void *)(lcd_frame0));
+				REG_LCD_SA0 = virt_to_phys((void *)(lcd_frame0));
+			}
+
+			dma0_desc0->desc_size = dma0_desc1->desc_size = lcd_info->osd.fg0.h << 16 | lcd_info->osd.fg0.w;
+			REG_LCD_SIZE0 = (lcd_info->osd.fg0.h<<16)|lcd_info->osd.fg0.w;
+			REG_LCD_DA0 = virt_to_phys(dma0_desc0); //tft
+			printk("REG_LCD_DA0 : %08x\n",REG_LCD_DA0);
+		}
+		
+		if ( lcd_info->osd.fg_change & FG1_CHANGE_SIZE ) { /* change FG1 size*/
+			printk("********FG1_CHANGE_SIZE************\n");
+			if ( lcd_info->panel.cfg & LCD_CFG_TVEN ) { /* output to TV */
+				printk("********LCD_CFG_TVEN************\n");				
+				dma1_desc0->cmd = dma1_desc1->cmd = (fg1_frm_size/4)/2;
+				dma1_desc0->offsize = dma1_desc1->offsize = fg1_line_size/4;
+				dma1_desc0->page_width = dma1_desc1->page_width = fg1_line_size/4;
+				dma1_desc1->databuf = virt_to_phys((void *)(lcd_frame1 + fg1_line_size));
+				REG_LCD_DA1 = virt_to_phys(dma0_desc1); //tft
+				
+			}else {
+				if(lcd_info->is1_compressed){
+					printk("---------is1 compressed---------------\n");
+					dma1_desc0->cmd = lcd_info->osd.fg1.h;
+					dma1_desc0->cmd |= LCD_CMD_UNCOMPRESS_EN;
+					if(lcd_info->without_alpha)
+						dma1_desc0->cmd  |= LCD_CMD_UNCOMPRESS_WITHOUT_ALPHA;
+					
+					dma1_desc0->offsize =  (lcd_info->osd.fg1.w * bpp1 /32 )+ 1; //word
+					dma1_desc0->page_width = 0;
+				}else{
+					dma1_desc0->cmd = fg1_frm_size/4;
+					if(lcd_info->is1_disPart)
+					{
+						printk("-------------is 1 dispart--------------------\n");
+						dma1_desc0->offsize     = fg1_line_size/4;
+						dma1_desc0->page_width  = fg1_line_size/4;   //wrod
+					}
+					else{
+						dma1_desc0->offsize     = 0;
+						dma1_desc0->page_width  = 0;
+					}
+					
+				}
+			}//not tve
+			if(lcd_info->osd.fg_change & FG1_CHANGE_BUF){
+				printk("change buf to 2-1\n");
+				dma1_desc0->databuf = virt_to_phys((void *)(lcd_frame2_1));
+				REG_LCD_SA1 = virt_to_phys((void *)(lcd_frame2_1));
+			}else{
+				printk("change buf to 1\n");
+				dma1_desc0->databuf = virt_to_phys((void *)(lcd_frame1));
+				REG_LCD_SA1 = virt_to_phys((void *)(lcd_frame1));
+			}
+			
+			dma1_desc0->desc_size = dma1_desc1->desc_size= lcd_info->osd.fg1.h << 16 | lcd_info->osd.fg1.w;
+			REG_LCD_SIZE1 = (lcd_info->osd.fg1.h << 16) |lcd_info->osd.fg1.w;
+			REG_LCD_DA1 = virt_to_phys(dma1_desc0); //tft
+		}//fg1 change size
+		
+		if (lcd_info->osd.fg_change & FG0_CHANGE_PALETTE){
+			if(lcd_info->osd.fg0.bpp <= 8){
+				printk("------change_palette---------\n");
+				switch (lcd_info->osd.fg0.bpp) {
+				case 1:
+					fb_alloc_cmap(&jz4810fb_info->fb.cmap, 4, 0);
+					break;
+				case 2:
+					fb_alloc_cmap(&jz4810fb_info->fb.cmap, 8, 0);
+					break;
+				case 4:
+					fb_alloc_cmap(&jz4810fb_info->fb.cmap, 32, 0);
+					break;
+				case 8:
+					fb_alloc_cmap(&jz4810fb_info->fb.cmap, 256, 0);
+					break;
+					
+				}
+				
+				pal_size = calc_pal_size(lcd_info);
+				dma0_desc_palette->cmd 		= LCD_CMD_PAL | pal_size; /* Palette Descriptor */
+				
+				dma0_desc_palette->next_desc 	= (unsigned int)virt_to_phys(dma0_desc0);
+				REG_LCD_DA0 = virt_to_phys(dma0_desc_palette); //tft
+				
+				printk("dma0_desc_palette->databuf : %08x\n",dma0_desc_palette->databuf);
+				printk("dma0_desc_palette->frame_id : %08x\n",dma0_desc_palette->frame_id);
+				printk("dma0_desc_palette->next_desc : %08x\n",dma0_desc_palette->next_desc);
+				printk("dma0_desc0->next_desc : %08x\n",dma0_desc0->next_desc);
+				
+			}
+			
+		}
+		
+		
+		if(lcd_info->test_part2){
+			printk("---------test part2-------------\n");
+			int fg0p2_line_size, fg0p2_frm_size;
+			int bpp0p2 = bpp_to_data_bpp(lcd_info->osd.fg0p2.bpp);
+			
+			fg0p2_line_size = (lcd_info->osd.fg0p2.w * bpp0p2/8);
+			fg0p2_line_size = ((fg0p2_line_size+3)>>2)<<2; /* word aligned */
+			fg0p2_frm_size  = fg0p2_line_size * lcd_info->osd.fg0p2.h;
+			
+			dma0_desc1->next_desc = (unsigned int)virt_to_phys(dma0_desc1);
+			dma0_desc1->databuf   = virt_to_phys((void *)lcd_frame2_0);
+			dma0_desc1->frame_id  = (unsigned int)0x0000da01; /* DMA0'1 */		
+			
+			if(lcd_info->is0_compressed){
+				dma1_desc0->cmd = lcd_info->osd.fg0p2.h;
+				dma1_desc0->cmd |= LCD_CMD_UNCOMPRESS_EN;
+				if(lcd_info->without_alpha)
+					dma1_desc0->cmd  |= LCD_CMD_UNCOMPRESS_WITHOUT_ALPHA;
+				
+				dma1_desc0->offsize =  (lcd_info->osd.fg0p2.w * bpp0p2 /32 )+ 1; //word
+				dma1_desc0->page_width = 0;
+
+			}else{
+				dma0_desc1->cmd         = fg0p2_frm_size/4;
+				dma0_desc1->offsize     =0;
+				dma0_desc1->page_width  = 0;
+			}
+			dma0_desc1->desc_size   = lcd_info->osd.fg0p2.h << 16 | lcd_info->osd.fg0p2.w;
+
+			REG_LCD_SIZE0_PART2 = lcd_info->osd.fg0p2.h << 16 | lcd_info->osd.fg0p2.w;
+			REG_LCD_XYP0_PART2  = lcd_info->osd.fg0p2.y << 16 | lcd_info->osd.fg0p2.x;
+			REG_LCD_DA0_PART2   = (unsigned int)virt_to_phys(dma0_desc1);
+ 		}
+		
+		dma_cache_wback((unsigned int)(dma_desc_base), (DMA_DESC_NUM)*sizeof(struct jz4810_lcd_dma_desc));
+		lcd_info->osd.fg_change = FG_NOCHANGE; /* clear change flag */
+//		while(REG_LCD_OSDCTRL & LCD_OSDCTRL_CHANGES);
+	}//is change
+}
+
+
+static void jz4810fb_change_clock( struct jz4810lcd_info * lcd_info )
+{
+
+#if defined(CONFIG_FPGA)
+	REG_LCD_REV = 0x00000002;
+#define JZ_LCD 	 48000000
+	printk("Falcon test , pixclk divide REG_LCD_REV=0x%08x\n", REG_LCD_REV);
+	printk("Falcon test, pixclk %d\n", JZ_LCD/(((REG_LCD_REV&0xFF)+1)*2));
+#else
+	unsigned int val = 0;
+	unsigned int pclk;
+	/* Timing setting */
+	__cpm_stop_lcd();
+
+	val = lcd_info->panel.fclk; /* frame clk */
+
+	if ( (lcd_info->panel.cfg & LCD_CFG_MODE_MASK) != LCD_CFG_MODE_SERIAL_TFT) {
+		pclk = val * (lcd_info->panel.w + lcd_info->panel.hsw + lcd_info->panel.elw + lcd_info->panel.blw) * (lcd_info->panel.h + lcd_info->panel.vsw + lcd_info->panel.efw + lcd_info->panel.bfw); /* Pixclk */
+	}
+	else {
+		/* serial mode: Hsync period = 3*Width_Pixel */
+		pclk = val * (lcd_info->panel.w*3 + lcd_info->panel.hsw + lcd_info->panel.elw + lcd_info->panel.blw) * (lcd_info->panel.h + lcd_info->panel.vsw + lcd_info->panel.efw + lcd_info->panel.bfw); /* Pixclk */
+	}
+
+	/********* In TVE mode PCLK = 27MHz ***********/
+	if ( lcd_info->panel.cfg & LCD_CFG_TVEN ) { 		/* LCDC output to TVE */
+		REG_CPM_LPCDR  |= LPCDR_LTCS;
+		pclk = 27000000;
+		val = __cpm_get_pllout2() / pclk; /* pclk */
+		val--;
+		__cpm_set_pixdiv(val);
+
+
+		D("REG_CPM_LPCDR = 0x%08x\n", REG_CPM_LPCDR);
+#if 0
+#if defined(CONFIG_SOC_JZ4810) /* Jz4810D don't use LCLK */
+		val = pclk * 3 ;	/* LCDClock > 2.5*Pixclock */
+
+		val =(__cpm_get_pllout()) / val;
+		if ( val > 0x1f ) {
+			printk("lcd clock divide is too large, set it to 0x1f\n");
+			val = 0x1f;
+		}
+		__cpm_set_ldiv( val );
+#endif
+#endif
+		__cpm_select_pixclk_tve();
+
+		REG_CPM_CPCCR |= CPCCR_CE ; /* update divide */
+	}
+	else { 		/* LCDC output to  LCD panel */
+		val = __cpm_get_pllout2() / pclk; /* pclk */
+		val--;
+		D("ratio: val = %d\n", val);
+		if ( val > 0x7ff ) {
+			printk("pixel clock divid is too large, set it to 0x7ff\n");
+			val = 0x7ff;
+		}
+
+		__cpm_set_pixdiv(val);
+		D("REG_CPM_LPCDR = 0x%08x\n", REG_CPM_LPCDR);
+#if 0
+#if defined(CONFIG_SOC_JZ4810) /* Jz4810D don't use LCLK */
+		val = pclk * 3 ;	/* LCDClock > 2.5*Pixclock */
+		val =__cpm_get_pllout2() / val;
+		if ( val > 0x1f ) {
+			printk("lcd clock divide is too large, set it to 0x1f\n");
+			val = 0x1f;
+		}
+		__cpm_set_ldiv( val );
+#endif
+#endif
+		REG_CPM_CPCCR |= CPCCR_CE ; /* update divide */
+
+	}
+
+	D("REG_CPM_LPCDR=0x%08x\n", REG_CPM_LPCDR);
+	D("REG_CPM_CPCCR=0x%08x\n", REG_CPM_CPCCR);
+
+	jz_clocks.pixclk = __cpm_get_pixclk();
+	printk("LCDC: PixClock:%d\n", jz_clocks.pixclk);
+#if 0
+#if defined(CONFIG_SOC_JZ4810) /* Jz4810D don't use LCLK */
+	jz_clocks.lcdclk = __cpm_get_lcdclk();
+	printk("LCDC: LcdClock:%d\n", jz_clocks.lcdclk);
+#endif
+#endif
+	__cpm_start_lcd();
+	udelay(1000);
+	/*
+	 * set lcd device clock and lcd pixel clock.
+	 * what about TVE mode???
+	 *
+	 */
+#endif
+
+}
+
+/*
+ * jz4810fb_set_mode(), set osd configure, resize foreground
+ *
+ */
+static void jz4810fb_set_mode( struct jz4810lcd_info * lcd_info )
+{
+	struct lcd_cfb_info *cfb = jz4810fb_info;
+
+	jz4810fb_set_panel_mode(lcd_info);
+	jz4810fb_set_osd_mode(lcd_info);
+//	jz4810fb_change_desc(lcd_info);
+	jz4810fb_foreground_resize(lcd_info);
+	jz4810fb_set_var(&cfb->fb.var, -1, &cfb->fb);
+}
+
+/*
+ * jz4810fb_deep_set_mode,
+ *
+ */
+static void jz4810fb_deep_set_mode( struct jz4810lcd_info * lcd_info )
+{
+	struct lcd_cfb_info *cfb = jz4810fb_info;
+	/* configurate sequence:
+	 * 1. disable lcdc.
+	 * 2. init frame descriptor.
+	 * 3. set panel mode
+	 * 4. set osd mode
+	 * 5. start lcd clock in CPM
+	 * 6. enable lcdc.
+	 */
+
+	__lcd_clr_ena();	/* Quick Disable */
+	lcd_info->osd.fg_change = FG_CHANGE_ALL; /* change FG0, FG1 size, postion??? */
+	jz4810fb_descriptor_init(lcd_info);
+	jz4810fb_set_mode(lcd_info);
+	jz4810fb_change_clock(lcd_info);
+	__lcd_set_ena();	/* enable lcdc */
+}
+
+
+static irqreturn_t jz4810fb_interrupt_handler(int irq, void *dev_id)
+{
+	unsigned int state;
+	static int irqcnt=0;
+
+	state = REG_LCD_STATE;
+	D("In the lcd interrupt handler, state=0x%x\n", state);
+
+	if (state & LCD_STATE_EOF) /* End of frame */
+		REG_LCD_STATE = state & ~LCD_STATE_EOF;
+
+	if (state & LCD_STATE_IFU0) {
+		printk("%s, InFiFo0 underrun\n", __FUNCTION__);
+		REG_LCD_STATE = state & ~LCD_STATE_IFU0;
+	}
+
+	if (state & LCD_STATE_IFU1) {
+		printk("%s, InFiFo1 underrun\n", __FUNCTION__);
+		REG_LCD_STATE = state & ~LCD_STATE_IFU1;
+	}
+
+	if (state & LCD_STATE_OFU) { /* Out fifo underrun */
+		REG_LCD_STATE = state & ~LCD_STATE_OFU;
+		if ( irqcnt++ > 100 ) {
+			__lcd_disable_ofu_intr();
+			printk("disable Out FiFo underrun irq.\n");
+		}
+		printk("%s, Out FiFo underrun.\n", __FUNCTION__);
+	}
+
+	return IRQ_HANDLED;
+}
+
+#ifdef CONFIG_PM
+
+/*
+ * Suspend the LCDC.
+ */
+static int jz4810_fb_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	printk("%s(): called.\n", __func__);
+
+	screen_off();
+	//ctrl_disable();
+	__lcd_clr_ena();
+
+	__cpm_stop_lcd();
+
+	return 0;
+}
+
+/*
+ * Resume the LCDC.
+ */
+static int jz4810_fb_resume(struct platform_device *pdev)
+{
+	struct lcd_cfb_info *cfb = jz4810fb_info;
+
+	printk("%s(): called.\n", __func__);
+
+	__cpm_start_lcd();
+	screen_on();
+	__lcd_set_ena();
+
+	return 0;
+}
+
+#else
+#define jzfb_suspend      NULL
+#define jzfb_resume       NULL
+#endif /* CONFIG_PM */
+
+/* The following routine is only for test */
+
+#if 1 //JZ_FB_DEBUG
+static void test_gpio(int gpio_num, int delay)	{
+	while(1) {
+		__gpio_as_output1(gpio_num);
+		udelay(delay);
+		__gpio_as_output0(gpio_num);
+		udelay(delay);
+	}
+}
+static void display_v_color_bar(int w, int h, int bpp) {
+	int i, j, wpl, data = 0;
+	int *ptr;
+//	ptr = (int *)lcd_frame0;
+	ptr = (int *)lcd_frame1;
+	wpl = w*bpp/32;
+	if (!(bpp > 8))
+		switch(bpp){
+		case 1:
+			for (j = 0;j < h; j++)
+				for (i = 0;i < wpl; i++) {
+					*ptr++ = 0x00ff00ff;
+				}
+			break;
+		case 2:
+			for (j = 0;j < h; j++)
+				for (i = 0;i < wpl; i++) {
+					data = (i%4)*0x55555555;
+					*ptr++ = data;
+				}
+			break;
+		case 4:
+			for (j = 0;j < h; j++)
+				for (i = 0;i < wpl; i++) {
+					data = (i%16)*0x11111111;
+					*ptr++ = data;
+				}
+			break;
+		case 8:
+			for (j = 0;j < h; j++)
+				for (i = 0;i < wpl; i+=2) {
+					data = (i%(256))*0x01010101;
+					*ptr++ = data;
+					*ptr++ = data;
+				}
+			break;
+		}
+	else {
+		switch(bpp) {
+		case 16:
+			for (j = 0;j < h; j++)
+				for (i = 0;i < wpl; i++) {
+					if((i/4)%8==0)
+						*ptr++ = 0xffffffff;
+					else if ((i/4)%8==1)
+						*ptr++ = 0xf800f800;
+					else if ((i/4)%8==2)
+						*ptr++ = 0xffe0ffe0;
+					else if ((i/4)%8==3)
+						*ptr++ = 0x07e007e0;
+					else if ((i/4)%8==4)
+						*ptr++ = 0x07ff07ff;
+					else if ((i/4)%8==5)
+						*ptr++ = 0x001f001f;
+					else if ((i/4)%8==6)
+						*ptr++ = 0xf81ff81f;
+					else if ((i/4)%8==7)
+						*ptr++ = 0x00000000;
+				}
+			break;
+		case 18:
+		case 24:
+		case 32:
+		default:
+#if 1
+			for (j = 0;j < h; j++)
+				for (i = 0;i < wpl; i++) {
+					if((i/8)%8==7)
+						*ptr++ = 0xffffff;
+					else if ((i/8)%8==1)
+						*ptr++ = 0xff0000;
+					else if ((i/8)%8==2)
+						*ptr++ = 0xffff00;
+					else if ((i/8)%8==3)
+						*ptr++ = 0x00ff00;
+					else if ((i/8)%8==4)
+						*ptr++ = 0x00ffff;
+					else if ((i/8)%8==5)
+						*ptr++ = 0x0000ff;
+					else if ((i/8)%8==6)
+						*ptr++ = 0xff00ff;
+					else if ((i/8)%8==0)
+						*ptr++ = 0x000000;
+				}
+#else
+			for (j = 0;j < h; j++)
+				for (i = 0;i < wpl; i++) {
+					if((i/8)%8==7)
+						*ptr++ = 0x00ff0000;
+					else if ((i/8)%8==1)
+						*ptr++ = 0xffff0000;
+					else if ((i/8)%8==2)
+						*ptr++ = 0x20ff0000;
+					else if ((i/8)%8==3)
+						*ptr++ = 0x40ff0000;
+					else if ((i/8)%8==4)
+						*ptr++ = 0x60ff0000;
+					else if ((i/8)%8==5)
+						*ptr++ = 0x80ff0000;
+					else if ((i/8)%8==6)
+						*ptr++ = 0xa0ff0000;
+					else if ((i/8)%8==0)
+						*ptr++ = 0xc0ff0000;
+				}
+#endif
+			break;
+		}
+	}
+}
+static void display_h_color_bar(int w, int h, int bpp) {
+	int i, data = 0;
+	int *ptr;
+	int wpl; //word_per_line
+	ptr = (int *)lcd_frame0;
+
+	wpl = w*bpp/32;
+	if (!(bpp > 8))
+		for (i = 0;i < wpl*h;i++) {
+			switch(bpp){
+			case 1:
+				if(i%(wpl*8)==0)
+					data = ((i/(wpl*8))%2)*0xffffffff;
+					*ptr++ = data;
+				break;
+			case 2:
+				if(i%(wpl*8)==0)
+					data = ((i/(wpl*8))%4)*0x55555555;
+					*ptr++ = data;
+				break;
+			case 4:
+				if(i%(wpl*8)==0)
+					data = ((i/(wpl*8))%16)*0x11111111;
+				*ptr++ = data;
+				break;
+			case 8:
+				if(i%(wpl*8)==0)
+					data = ((i/(wpl*8))%256)*0x01010101;
+				*ptr++ = data;
+				break;
+			}
+		}
+	else {
+
+		switch(bpp) {
+		case 15:
+		case 16:
+			for (i = 0;i < wpl*h;i++) {
+				if (((i/(wpl*8)) % 8) == 0)
+					*ptr++ = 0xffffffff;
+				else if (((i/(wpl*8)) % 8) == 1)
+					*ptr++ = 0xf800f800;
+				else if (((i/(wpl*8)) % 8) == 2)
+					*ptr++ = 0xffe0ffe0;
+				else if (((i/(wpl*8)) % 8) == 3)
+					*ptr++ = 0x07e007e0;
+				else if (((i/(wpl*8)) % 8) == 4)
+					*ptr++ = 0x07ff07ff;
+				else if (((i/(wpl*8)) % 8) == 5)
+					*ptr++ = 0x001f001f;
+				else if (((i/(wpl*8)) % 8) == 6)
+					*ptr++ = 0xf81ff81f;
+				else if (((i/(wpl*8)) % 8) == 7)
+					*ptr++ = 0x00000000;
+			}
+				break;
+		case 18:
+		case 24:
+		case 32:
+		default:
+			for (i = 0;i < wpl*h;i++) {
+				if (((i/(wpl*8)) % 8) == 7)
+					*ptr++ = 0xffffff;
+				else if (((i/(wpl*8)) % 8) == 2)
+					*ptr++ = 0xff0000;
+				else if (((i/(wpl*8)) % 8) == 4)
+					*ptr++ = 0xffff00;
+				else if (((i/(wpl*8)) % 8) == 6)
+					*ptr++ = 0x00ff00;
+				else if (((i/(wpl*8)) % 8) == 1)
+					*ptr++ = 0x00ffff;
+				else if (((i/(wpl*8)) % 8) == 3)
+					*ptr++ = 0x0000ff;
+				else if (((i/(wpl*8)) % 8) == 5)
+					*ptr++ = 0x000000;
+				else if (((i/(wpl*8)) % 8) == 0)
+					*ptr++ = 0xff00ff;
+			}
+			break;
+		}
+
+	}
+
+}
+#endif
+
+/* Backlight Control Interface via sysfs
+ *
+ * LCDC:
+ * Enabling LCDC when LCD backlight is off will only affects cfb->display.
+ *
+ * Backlight:
+ * Changing the value of LCD backlight when LCDC is off will only affect the cfb->backlight_level.
+ *
+ * - River.
+ */
+static int screen_off(void)
+{
+	struct lcd_cfb_info *cfb = jz4810fb_info;
+
+//	__lcd_close_backlight();
+	__lcd_display_off();
+
+#ifdef HAVE_LCD_PWM_CONTROL
+	if (cfb->b_lcd_pwm) {
+		__lcd_pwm_stop();
+		cfb->b_lcd_pwm = 0;
+	}
+#endif
+
+	cfb->b_lcd_display = 0;
+
+	return 0;
+}
+
+static int screen_on(void)
+{
+	struct lcd_cfb_info *cfb = jz4810fb_info;
+
+	__lcd_display_on();
+
+	/* Really restore LCD backlight when LCD backlight is turned on. */
+	if (cfb->backlight_level) {
+#ifdef HAVE_LCD_PWM_CONTROL
+		if (!cfb->b_lcd_pwm) {
+			__lcd_pwm_start();
+			cfb->b_lcd_pwm = 1;
+		}
+#endif
+		__lcd_set_backlight_level(cfb->backlight_level);
+	}
+	cfb->b_lcd_display = 1;
+
+	return 0;
+}
+
+static int jz4810fb_set_backlight_level(int n)
+{
+	struct lcd_cfb_info *cfb = jz4810fb_info;
+
+	if (n) {
+		if (n > LCD_MAX_BACKLIGHT)
+			n = LCD_MAX_BACKLIGHT;
+
+		if (n < LCD_MIN_BACKLIGHT)
+			n = LCD_MIN_BACKLIGHT;
+
+		/* Really change the value of backlight when LCDC is enabled. */
+		if (cfb->b_lcd_display) {
+#ifdef HAVE_LCD_PWM_CONTROL
+			if (!cfb->b_lcd_pwm) {
+				__lcd_pwm_start();
+				cfb->b_lcd_pwm = 1;
+			}
+#endif
+			__lcd_set_backlight_level(n);
+		}
+	}else{
+		/* Turn off LCD backlight. */
+		__lcd_close_backlight();
+
+#ifdef HAVE_LCD_PWM_CONTROL
+		if (cfb->b_lcd_pwm) {
+			__lcd_pwm_stop();
+			cfb->b_lcd_pwm = 0;
+		}
+#endif
+	}
+
+	cfb->backlight_level = n;
+
+	return 0;
+}
+
+static ssize_t show_bl_level(struct device *device,
+			     struct device_attribute *attr, char *buf)
+{
+	struct lcd_cfb_info *cfb = jz4810fb_info;
+
+	return snprintf(buf, PAGE_SIZE, "%d\n", cfb->backlight_level);
+}
+
+static ssize_t store_bl_level(struct device *device,
+		struct device_attribute *attr,
+		const char *buf, size_t count)
+{
+	int n;
+	char *ep;
+
+	n = simple_strtoul(buf, &ep, 0);
+	if (*ep && *ep != '\n')
+		return -EINVAL;
+
+	jz4810fb_set_backlight_level(n);
+
+	return count;
+}
+
+static struct device_attribute device_attrs[] = {
+	__ATTR(backlight_level, S_IRUGO | S_IWUSR, show_bl_level, store_bl_level),
+};
+
+static int jz4810fb_device_attr_register(struct fb_info *fb_info)
+{
+	int error = 0;
+	unsigned int i;
+
+	for (i = 0; i < ARRAY_SIZE(device_attrs); i++) {
+		error = device_create_file(fb_info->dev, &device_attrs[i]);
+
+		if (error)
+			break;
+	}
+
+	if (error) {
+		while (--i >= 0)
+			device_remove_file(fb_info->dev, &device_attrs[i]);
+	}
+
+	return 0;
+}
+
+static int jz4810fb_device_attr_unregister(struct fb_info *fb_info)
+{
+	unsigned int i;
+
+	for (i = 0; i < ARRAY_SIZE(device_attrs); i++)
+		device_remove_file(fb_info->dev, &device_attrs[i]);
+
+	return 0;
+}
+/* End */
+
+static void gpio_init(void)
+{
+//	__lcd_display_pin_init(); /*lltang: new gpio operation put as gpio and set/clear together*/
+
+	/* gpio init __gpio_as_lcd */
+	if (jz4810_lcd_info->panel.cfg & LCD_CFG_MODE_TFT_16BIT)
+		__gpio_as_lcd_16bit();
+	else if (jz4810_lcd_info->panel.cfg & LCD_CFG_MODE_TFT_24BIT){
+		__gpio_as_lcd_24bit();
+	}
+	else
+ 		__gpio_as_lcd_18bit();
+
+	/* In special mode, we only need init special pin,
+	 * as general lcd pin has init in uboot */
+#if defined(CONFIG_SOC_JZ4810)
+	switch (jz4810_lcd_info->panel.cfg & LCD_CFG_MODE_MASK) {
+	case LCD_CFG_MODE_SPECIAL_TFT_1:
+	case LCD_CFG_MODE_SPECIAL_TFT_2:
+	case LCD_CFG_MODE_SPECIAL_TFT_3:
+		__gpio_as_lcd_special();
+		break;
+	default:
+		;
+	}
+#endif
+
+	return;
+}
+
+static void set_bpp_to_ctrl_bpp(void)
+{
+	switch (jz4810_lcd_info->osd.fg0.bpp) {
+		case 1:
+		case 2:
+		case 4:
+		case 8:
+		case 15:
+		case 16:
+	        case 18:
+  	        case 24:
+	        case 30:
+			break;
+
+	        case 17:
+		case 19 ... 23:
+		case 25 ... 29:
+		case 31 ... 32:
+			jz4810_lcd_info->osd.fg0.bpp = 32;
+			break;
+
+		default:
+			E("FG0: BPP (%d) not support, Set BPP 32.\n",
+					jz4810_lcd_info->osd.fg0.bpp);
+
+			jz4810_lcd_info->osd.fg0.bpp = 32;
+			break;
+	}
+
+	switch (jz4810_lcd_info->osd.fg1.bpp) {
+		case 15:
+		case 16:
+			break;
+
+		case 17 ... 32:
+			jz4810_lcd_info->osd.fg1.bpp = 32;
+			break;
+
+		default:
+			E("FG1: BPP (%d) not support, Set BPP 32.\n",
+					jz4810_lcd_info->osd.fg1.bpp);
+
+			jz4810_lcd_info->osd.fg1.bpp = 32;
+			break;
+	}
+
+	return;
+}
+
+static void slcd_init(void)
+{
+	/* Configure SLCD module for setting smart lcd control registers */
+#if defined(CONFIG_FB_JZ4810_SLCD)
+	__lcd_as_smart_lcd();
+	__slcd_disable_dma();
+	__init_slcd_bus();	/* Note: modify this depend on you lcd */
+
+#endif
+	return;
+}
+
+static int __devinit jz4810_fb_probe(struct platform_device *dev)
+{
+	struct lcd_cfb_info *cfb;
+
+	int rv = 0;
+
+	cfb = jz4810fb_alloc_fb_info();
+	if (!cfb)
+		goto failed;
+
+	screen_off();
+	ctrl_disable();
+
+	gpio_init();
+	slcd_init();
+
+	set_bpp_to_ctrl_bpp();
+
+	printk("lcd_info->osd.fg0.bpp : %d\n",jz4810_lcd_info->osd.fg0.bpp);
+	/* init clk */
+	jz4810fb_change_clock(jz4810_lcd_info);
+
+	rv = jz4810fb_map_smem(cfb);
+	if (rv)
+		goto failed;
+
+	jz4810fb_deep_set_mode(jz4810_lcd_info);
+
+	rv = register_framebuffer(&cfb->fb);
+	if (rv < 0) {
+		D("Failed to register framebuffer device.");
+		goto failed;
+	}
+
+	printk("fb%d: %s frame buffer device, using %dK of video memory\n",
+	       cfb->fb.node, cfb->fb.fix.id, cfb->fb.fix.smem_len>>10);
+
+	jz4810fb_device_attr_register(&cfb->fb);
+
+	if (request_irq(IRQ_LCD, jz4810fb_interrupt_handler, IRQF_DISABLED,
+				"lcd", 0)) {
+		D("Faield to request LCD IRQ.\n");
+		rv = -EBUSY;
+		goto failed;
+	}
+//	REG_LCD_PCFG = 0x37fffeff;
+	REG_LCD_PCFG = 0x47fffeff;
+
+	ctrl_enable();
+	screen_on();
+#if JZ_FB_DEBUG
+	display_h_color_bar(jz4810_lcd_info->osd.fg0.w, jz4810_lcd_info->osd.fg0.h, jz4810_lcd_info->osd.fg0.bpp);
+	print_lcdc_registers();
+#endif
+
+	return 0;
+
+failed:
+	jz4810fb_unmap_smem(cfb);
+	jz4810fb_free_fb_info(cfb);
+
+	return rv;
+}
+
+static int __devexit jz4810_fb_remove(struct platform_device *pdev)
+{
+	return 0;
+}
+
+static struct platform_driver jz4810_fb_driver = {
+	.probe	= jz4810_fb_probe,
+	.remove = jz4810_fb_remove,
+	.suspend = jz4810_fb_suspend,
+	.resume = jz4810_fb_resume,
+	.driver = {
+		.name = "jz-lcd",
+		.owner = THIS_MODULE,
+	},
+};
+
+static int __init jz4810_fb_init(void)
+{
+	return platform_driver_register(&jz4810_fb_driver);
+}
+
+static void __exit jz4810_fb_cleanup(void)
+{
+	platform_driver_unregister(&jz4810_fb_driver);
+}
+
+module_init(jz4810_fb_init);
+module_exit(jz4810_fb_cleanup);
diff --git a/drivers/video/jz4760_epd.h b/drivers/video/jz4810_lcd.h
index 0e8527ef4f7..64fa43f2aa0 100644
--- a/drivers/video/jz4760_epd.h
+++ b/drivers/video/jz4810_lcd.h
@@ -1,5 +1,5 @@
 /*
- * linux/drivers/video/jz4760_lcd.h -- Ingenic Jz4760 On-Chip LCD frame buffer device
+ * linux/drivers/video/jz4810_lcd.h -- Ingenic Jz4810 On-Chip LCD frame buffer device
  *
  * Copyright (C) 2005-2008, Ingenic Semiconductor Inc.
  *
@@ -9,8 +9,8 @@
  *
  */
 
-#ifndef __JZ4760_LCD_H__
-#define __JZ4760_LCD_H__
+#ifndef __JZ4810_LCD_H__
+#define __JZ4810_LCD_H__
 
 //#include <asm/io.h>
 
@@ -18,11 +18,16 @@
 #define NR_PALETTE	256
 #define PALETTE_SIZE	(NR_PALETTE*2)
 
+struct reg{
+	unsigned long da0;
+	unsigned long da1;
+}da_reg;
+
 /* use new descriptor(8 words) */
-struct jz4760_lcd_dma_desc {
+struct jz4810_lcd_dma_desc {
 	unsigned int next_desc; 	/* LCDDAx */
 	unsigned int databuf;   	/* LCDSAx */
-	unsigned int frame_id;  	/* LCDFIDx */ 
+	unsigned int frame_id;  	/* LCDFIDx */
 	unsigned int cmd; 		/* LCDCMDx */
 	unsigned int offsize;       	/* Stride Offsize(in word) */
 	unsigned int page_width; 	/* Stride Pagewidth(in word) */
@@ -30,14 +35,7 @@ struct jz4760_lcd_dma_desc {
 	unsigned int desc_size; 	/* Foreground Size */
 };
 
-struct jz4760_epd_dma_desc {
-	unsigned int next_desc; 	/* LCDDAx */
-	unsigned int databuf;   	/* LCDSAx */
-
-};
-
-
-struct jz4760lcd_panel_t {
+struct jz4810lcd_panel_t {
 	unsigned int cfg;	/* panel mode and pin usage etc. */
 	unsigned int slcd_cfg;	/* Smart lcd configurations */
 	unsigned int ctrl;	/* lcd controll register */
@@ -53,7 +51,7 @@ struct jz4760lcd_panel_t {
 };
 
 
-struct jz4760lcd_fg_t {
+struct jz4810lcd_fg_t {
 	int bpp;	/* foreground bpp */
 	int x;		/* foreground start position x */
 	int y;		/* foreground start position y */
@@ -61,7 +59,7 @@ struct jz4760lcd_fg_t {
 	int h;		/* foreground height */
 };
 
-struct jz4760lcd_osd_t {
+struct jz4810lcd_osd_t {
 	unsigned int osd_cfg;	/* OSDEN, ALHPAEN, F0EN, F1EN, etc */
 	unsigned int osd_ctrl;	/* IPUEN, OSDBPP, etc */
 	unsigned int rgb_ctrl;	/* RGB Dummy, RGB sequence, RGB to YUV */
@@ -73,22 +71,37 @@ struct jz4760lcd_osd_t {
 
 #define FG_NOCHANGE 		0x0000
 #define FG0_CHANGE_SIZE 	0x0001
-#define FG0_CHANGE_POSITION 	0x0002
-#define FG1_CHANGE_SIZE 	0x0010
+#define FG0_CHANGE_POSITION 	0x0010
+#define FG0_CHANGE_BUF  	0x0100
+#define FG0_CHANGE_PALETTE 	0x1000
+#define FG1_CHANGE_SIZE 	0x0002
 #define FG1_CHANGE_POSITION 	0x0020
-#define FG_CHANGE_ALL 		( FG0_CHANGE_SIZE | FG0_CHANGE_POSITION | \
+#define FG1_CHANGE_BUF  	0x0200
+#define FG_CHANGE_ALL 		( FG0_CHANGE_SIZE | FG0_CHANGE_POSITION |\
 				  FG1_CHANGE_SIZE | FG1_CHANGE_POSITION )
 	int fg_change;
-	struct jz4760lcd_fg_t fg0;	/* foreground 0 */
-	struct jz4760lcd_fg_t fg1;	/* foreground 1 */
+	struct jz4810lcd_fg_t fg0;	/* foreground 0 */
+	struct jz4810lcd_fg_t fg0p2;	/* foreground 0p2 */
+	struct jz4810lcd_fg_t fg1;	/* foreground 1 */
 };
 
-struct jz4760lcd_info {
-	struct jz4760lcd_panel_t panel;
-	struct jz4760lcd_osd_t osd;
+struct jz4810lcd_info {
+	struct jz4810lcd_panel_t panel;
+	struct jz4810lcd_osd_t osd;
+	unsigned long frame0;
+	unsigned long frame1;
+	unsigned long frame2_0;
+	unsigned long frame2_1;
+	int without_alpha;
+	int is0_compressed;
+	int is1_compressed;
+	int is0_disPart;
+	int is1_disPart;
+	int test_part2;
+	unsigned long pdma00;
+	unsigned long pdma10;
 };
 
-
 /* Jz LCDFB supported I/O controls. */
 #define FBIOSETBACKLIGHT	0x4688 /* set back light level */
 #define FBIODISPON		0x4689 /* display on */
@@ -103,52 +116,120 @@ struct jz4760lcd_info {
 #define FBIO_MODE_SWITCH	0x46a5 /* switch mode between LCD and TVE */
 #define FBIO_GET_TVE_MODE	0x46a6 /* get tve info */
 #define FBIO_SET_TVE_MODE	0x46a7 /* set tve mode */
-#define FBIODISON_FG		0x46a8 /* FG display on */
-#define FBIODISOFF_FG		0x46a9 /* FG display on */
-#define FBIO_SET_LCD_TO_TVE	0x46b0 /* set lcd to tve mode */
-#define FBIO_SET_FRM_TO_LCD	0x46b1 /* set framebuffer to lcd */
-#define FBIO_SET_IPU_TO_LCD	0x46b2 /* set ipu to lcd directly */
-#define FBIO_CHANGE_SIZE	0x46b3 /* change FG size */
-#define FBIO_CHANGE_POSITION	0x46b4 /* change FG starts position */
-#define FBIO_SET_BG_COLOR	0x46b5 /* set background color */
-#define FBIO_SET_IPU_RESTART_VAL	0x46b6 /* set ipu restart value */
-#define FBIO_SET_IPU_RESTART_ON	0x46b7 /* set ipu restart on */
-#define FBIO_SET_IPU_RESTART_OFF	0x46b8 /* set ipu restart off */
-#define FBIO_ALPHA_ON		0x46b9 /* enable alpha */
-#define FBIO_ALPHA_OFF		0x46c0 /* disable alpha */
-#define FBIO_SET_ALPHA_VAL	0x46c1 /* set alpha value */
-
-
-#define GET_EPD_INFO             0x46d0
-#define START_EPD_TRANS          0x46d1
-
 
 /*
  * LCD panel specific definition
  */
 /* AUO */
-#if defined(CONFIG_JZ4760_LCD_AUO_A043FL01V2)
-#if defined(CONFIG_JZ4760_F4760) /* Jz4760 FPGA board */
-	#define LCD_RET 	(32*3+27)       /*GPD29 LCD_DISP_N use for lcd reset*/
+#if defined(CONFIG_JZ4810_LCD_AUO_A043FL01V2)
+#if defined(CONFIG_JZ4810_F4810) 
+	#define SPEN		(32*1+29)       /*LCD_CS*/
+	#define SPCK		(32*1+28)       /*LCD_SCL*/
+	#define SPDA		(32*1+21)       /*LCD_SDA*/
+        #define LCD_RET 	(32*3+9)       /*GPD9 LCD_DISP_N use for lcd reset*/
 #else
 #error "driver/video/Jzlcd.h, please define SPI pins on your board."
 #endif
+
+#define __spi_write_reg(reg, val)		\
+	do {					\
+		unsigned char no;		\
+		unsigned short value;		\
+		unsigned char a=0;		\
+		unsigned char b=0;		\
+		__gpio_as_output(SPEN); /* use SPDA */	\
+		__gpio_as_output(SPCK); /* use SPCK */	\
+		__gpio_as_output(SPDA); /* use SPDA */	\
+		a=reg;				\
+		b=val;				\
+		__gpio_set_pin(SPEN);		\
+		__gpio_clear_pin(SPCK);		\
+		udelay(50);			\
+		__gpio_clear_pin(SPDA);		\
+		__gpio_clear_pin(SPEN);		\
+		udelay(50);			\
+		value=((a<<8)|(b&0xFF));	\
+		for(no=0;no<16;no++)		\
+		{				\
+			if((value&0x8000)==0x8000){	      \
+				__gpio_set_pin(SPDA);}	      \
+			else{				      \
+				__gpio_clear_pin(SPDA); }     \
+			udelay(50);			\
+			__gpio_set_pin(SPCK);		\
+			value=(value<<1);		\
+			udelay(50);			\
+			__gpio_clear_pin(SPCK);		\
+		}					\
+		__gpio_set_pin(SPEN);			\
+		udelay(400);				\
+	} while (0)
+#define __spi_read_reg(reg,val)			\
+	do{					\
+		unsigned char no;		\
+		unsigned short value;			\
+		__gpio_as_output(SPEN); /* use SPDA */	\
+		__gpio_as_output(SPCK); /* use SPCK */	\
+		__gpio_as_output(SPDA); /* use SPDA */	\
+		value = ((reg << 0) | (1 << 7));	\
+		val = 0;				\
+		__gpio_as_output(SPDA);			\
+		__gpio_set_pin(SPEN);			\
+		__gpio_clear_pin(SPCK);			\
+		udelay(50);				\
+		__gpio_clear_pin(SPDA);			\
+		__gpio_clear_pin(SPEN);			\
+		udelay(50);				\
+		for (no = 0; no < 16; no++ ) {		\
+			udelay(50);			\
+			if(no < 8)			\
+			{						\
+				if (value & 0x80) /* send data */	\
+					__gpio_set_pin(SPDA);		\
+				else					\
+					__gpio_clear_pin(SPDA);		\
+				udelay(50);				\
+				__gpio_set_pin(SPCK);			\
+				value = (value << 1);			\
+				udelay(50);				\
+				__gpio_clear_pin(SPCK);			\
+				if(no == 7)				\
+					__gpio_as_input(SPDA);		\
+			}						\
+			else						\
+			{						\
+				udelay(100);				\
+				__gpio_set_pin(SPCK);			\
+				udelay(50);				\
+				val = (val << 1);			\
+				val |= __gpio_get_pin(SPDA);		\
+				__gpio_clear_pin(SPCK);			\
+			}						\
+		}							\
+		__gpio_as_output(SPDA);					\
+		__gpio_set_pin(SPEN);					\
+		udelay(400);						\
+	} while(0)
+
 #define __lcd_special_pin_init()		\
 	do {						\
-		__gpio_as_output(LCD_RET);		\
+		__gpio_as_output0(LCD_RET);		\
+		udelay(100);				\
+		__gpio_as_output1(LCD_RET);		\
 	} while (0)
+
 #define __lcd_special_on()			     \
-	do {					     \
+do {					     \
 		udelay(50);			     \
-		__gpio_clear_pin(LCD_RET);	     \
+		__gpio_as_output0(LCD_RET);	     \
 		udelay(100);			     \
-		__gpio_set_pin(LCD_RET);	     \
+		__gpio_as_output1(LCD_RET);	     \
 } while (0)
 
-	#define __lcd_special_off() \
-	do { \
-		__gpio_clear_pin(LCD_RET);		\
-	} while (0)
+#define __lcd_special_off() \
+do { \
+	    __gpio_as_output0(LCD_RET);		\
+} while (0)
 
 #endif	/* CONFIG_JZLCD_AUO_A030FL01_V1 */
 
@@ -166,46 +247,27 @@ struct jz4760lcd_info {
 /*
  * Platform specific definition
  */
-#if defined(CONFIG_SOC_JZ4760) || defined(CONFIG_SOC_JZ4760D)
-
-#if defined(CONFIG_JZ4760_APUS) /* board apus */
+#if defined(CONFIG_JZ4810_VGA_DISPLAY)
+#define __lcd_display_pin_init()
+#define __lcd_display_on()
+#define __lcd_display_off()
+#elif defined(CONFIG_JZ4810_XXXX) 
 #define __lcd_display_pin_init() \
 do { \
-	__gpio_as_output(GPIO_LCD_VCC_EN_N);	 \
+	__gpio_as_output0(GPIO_LCD_VCC_EN_N);	\
 	__lcd_special_pin_init();	   \
 } while (0)
-#define __lcd_display_on() \
-do { \
-	__gpio_clear_pin(GPIO_LCD_VCC_EN_N);	\
-	__lcd_special_on();			\
-	mdelay(200);				\
-	__lcd_set_backlight_level(80);		\
-} while (0)
-
-#define __lcd_display_off() \
-do { \
-	__lcd_close_backlight();	   \
-	__lcd_special_off();	 \
-} while (0)
 
-#elif defined(CONFIG_JZ4760D_CETUS)/* board apus */
-
-#define __lcd_display_pin_init() \
-do { \
-	__gpio_as_output(GPIO_LCD_VCC_EN_N);	 \
-	__lcd_special_pin_init();	   \
-} while (0)
 #define __lcd_display_on() \
 do { \
-	__gpio_set_pin(GPIO_LCD_VCC_EN_N);	\
+	__gpio_as_output1(GPIO_LCD_VCC_EN_N);	 \
 	__lcd_special_on();			\
-	__lcd_set_backlight_level(80);		\
 } while (0)
 
 #define __lcd_display_off() \
 do { \
-	__lcd_close_backlight();	   \
-	__lcd_special_off();	 \
+	__lcd_special_off(); \
+	__gpio_as_output0(GPIO_LCD_VCC_EN_N);	 \
 } while (0)
 
 #else /* other boards */
@@ -214,6 +276,7 @@ do { \
 do { \
 	__lcd_special_pin_init();	   \
 } while (0)
+
 #define __lcd_display_on() \
 do { \
 	__lcd_special_on();			\
@@ -225,8 +288,8 @@ do { \
 	__lcd_close_backlight();	   \
 	__lcd_special_off();	 \
 } while (0)
-#endif /* APUS */
-#endif /* CONFIG_SOC_JZ4760 */
+
+#endif /* LEPUS */
 
 
 /*****************************************************************************
@@ -249,4 +312,4 @@ do { \
 #define __lcd_set_backlight_level(n)
 #endif
 
-#endif /* __JZ4760_LCD_H__ */
+#endif /* __JZ4810_LCD_H__ */
diff --git a/drivers/video/jz4810_tve.c b/drivers/video/jz4810_tve.c
new file mode 100644
index 00000000000..60fe8f94f7e
--- /dev/null
+++ b/drivers/video/jz4810_tve.c
@@ -0,0 +1,104 @@
+
+/*
+ * linux/drivers/video/jz4810_tve.c -- Ingenic Jz4810 TVE Controller operation
+ * interface.
+ * Copyright (C) 2005-2008, Ingenic Semiconductor Inc.
+ * Author: Wolfgang Wang, <lgwang@ingenic.cn>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * You should have received a copy of the  GNU General Public License along
+ * with this program; if not, write  to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+
+#include <asm/jzsoc.h>
+#include "jz4810_tve.h"
+
+struct jz4810tve_info jz4810_tve_info_PAL = {
+	.ctrl = (4 << TVE_CTRL_YCDLY_BIT) | TVE_CTRL_SYNCT | TVE_CTRL_PAL | TVE_CTRL_SWRST,	/* PAL, SVIDEO */
+	.frcfg = (23 << TVE_FRCFG_L1ST_BIT) | (625 << TVE_FRCFG_NLINE_BIT),
+	.slcfg1 = (800<<TVE_SLCFG1_WHITEL_BIT) | (282<<TVE_SLCFG1_BLACKL_BIT),
+	.slcfg2 = (296<<TVE_SLCFG2_VBLANKL_BIT) | (240<<TVE_SLCFG2_BLANKL_BIT),
+	.slcfg3 = (72 <<TVE_SLCFG3_SYNCL_BIT),
+	.ltcfg1 = (20<<TVE_LTCFG1_FRONTP_BIT) | (63<<TVE_LTCFG1_HSYNCW_BIT) | (78<<TVE_LTCFG1_BACKP_BIT),
+	.ltcfg2 = (1440 << TVE_LTCFG2_ACTLIN_BIT) | (24 << TVE_LTCFG2_PREBW_BIT) | (68 << TVE_LTCFG2_BURSTW_BIT),
+	.cfreq = 0x2a098acb,
+	.cphase = (0 << TVE_CPHASE_INITPH_BIT) | (0 << TVE_CPHASE_ACTPH_BIT) | (1 << TVE_CPHASE_CCRSTP_BIT),
+	.cbcrcfg = (32<<TVE_CBCRCFG_CBBA_BIT) | (59<<TVE_CBCRCFG_CRBA_BIT) | (137<<TVE_CBCRCFG_CBGAIN_BIT) | (137<<TVE_CBCRCFG_CRGAIN_BIT), /* CBGAIN CRGAIN??? */
+	.wsscr = 0x00000070,	/* default value */
+	.wsscfg1 = 0x0,
+	.wsscfg2 = 0x0,
+	.wsscfg3 = 0x0,
+};
+
+struct jz4810tve_info jz4810_tve_info_NTSC = {
+	.ctrl = (4 << TVE_CTRL_YCDLY_BIT) | TVE_CTRL_SWRST,	/* NTSC, SVIDEO */
+	.frcfg = (21 << TVE_FRCFG_L1ST_BIT) | (525 << TVE_FRCFG_NLINE_BIT),
+	.slcfg1 = (800<<TVE_SLCFG1_WHITEL_BIT) | (282<<TVE_SLCFG1_BLACKL_BIT),
+	.slcfg2 = (296<<TVE_SLCFG2_VBLANKL_BIT) | (240<<TVE_SLCFG2_BLANKL_BIT),
+	.slcfg3 = (72 <<TVE_SLCFG3_SYNCL_BIT),
+	.ltcfg1 = (16<<TVE_LTCFG1_FRONTP_BIT) | (63<<TVE_LTCFG1_HSYNCW_BIT) | (59<<TVE_LTCFG1_BACKP_BIT),
+	.ltcfg2 = (1440 << TVE_LTCFG2_ACTLIN_BIT) | (22 << TVE_LTCFG2_PREBW_BIT) | (68 << TVE_LTCFG2_BURSTW_BIT),
+	.cfreq = 0x21f07c1f,
+	.cphase = (0x17 << TVE_CPHASE_INITPH_BIT) | (0 << TVE_CPHASE_ACTPH_BIT) | (1 << TVE_CPHASE_CCRSTP_BIT),
+	.cbcrcfg = (59<<TVE_CBCRCFG_CBBA_BIT) | (0<<TVE_CBCRCFG_CRBA_BIT) | (137<<TVE_CBCRCFG_CBGAIN_BIT) | (137<<TVE_CBCRCFG_CRGAIN_BIT),
+	.wsscr = 0x00000070,	/* default value */
+	.wsscfg1 = 0x0,
+	.wsscfg2 = 0x0,
+	.wsscfg3 = 0x0,
+};
+
+struct jz4810tve_info *jz4810_tve_info = &jz4810_tve_info_PAL; /* default as PAL mode */
+
+void jz4810tve_enable_tve(void)
+{
+	/* enable tve controller, enable DACn??? */
+	jz4810_tve_info->ctrl = (jz4810_tve_info->ctrl | TVE_CTRL_DAPD) & ( ~( TVE_CTRL_DAPD1 | TVE_CTRL_DAPD2));
+	jz4810_tve_info->ctrl &= ~TVE_CTRL_SWRST;
+	REG_TVE_CTRL = jz4810_tve_info->ctrl;
+}
+
+/* turn off TVE, turn off DACn... */
+void jz4810tve_disable_tve(void)
+{
+	jz4810_tve_info->ctrl &= ~TVE_CTRL_DAPD;/* DACn disabled??? */
+	jz4810_tve_info->ctrl |= TVE_CTRL_SWRST;/* DACn disabled??? */
+	REG_TVE_CTRL = jz4810_tve_info->ctrl;
+}
+
+void jz4810tve_set_tve_mode( struct jz4810tve_info *tve )
+{
+	REG_TVE_CTRL 		= tve->ctrl;
+	REG_TVE_FRCFG 		= tve->frcfg;
+	REG_TVE_SLCFG1 		= tve->slcfg1;
+	REG_TVE_SLCFG2 		= tve->slcfg2;
+	REG_TVE_SLCFG3 		= tve->slcfg3;
+	REG_TVE_LTCFG1 		= tve->ltcfg1;
+	REG_TVE_LTCFG2 		= tve->ltcfg2;
+	REG_TVE_CFREQ 		= tve->cfreq;
+	REG_TVE_CPHASE 		= tve->cphase;
+	REG_TVE_CBCRCFG 	= tve->cbcrcfg;
+	REG_TVE_WSSCR 		= tve->wsscr;
+	REG_TVE_WSSCFG1 	= tve->wsscfg1;
+	REG_TVE_WSSCFG2 	= tve->wsscfg2;
+	REG_TVE_WSSCFG3 	= tve->wsscfg3;
+}
+
+void jz4810tve_init( int tve_mode )
+{
+	switch ( tve_mode ) {
+	case PANEL_MODE_TVE_PAL:
+		jz4810_tve_info = &jz4810_tve_info_PAL;
+		break;
+	case PANEL_MODE_TVE_NTSC:
+		jz4810_tve_info = &jz4810_tve_info_NTSC;
+		break;
+	}
+
+	jz4810tve_set_tve_mode( jz4810_tve_info );
+//	jz4810tve_enable_tve();
+}
diff --git a/drivers/video/jz4810_tve.h b/drivers/video/jz4810_tve.h
new file mode 100644
index 00000000000..526351db1b5
--- /dev/null
+++ b/drivers/video/jz4810_tve.h
@@ -0,0 +1,45 @@
+#ifndef __JZ4810_TVE_H__
+#define __JZ4810_TVE_H__
+
+
+#define PANEL_MODE_LCD_PANEL	0
+#define PANEL_MODE_TVE_PAL	1
+#define PANEL_MODE_TVE_NTSC	2
+
+/* TV parameter */
+#define TVE_WIDTH_PAL 		720
+#define TVE_HEIGHT_PAL 		573
+#define TVE_FREQ_PAL 		50
+#define TVE_WIDTH_NTSC 		720
+#define TVE_HEIGHT_NTSC 	482
+#define TVE_FREQ_NTSC 		60
+
+
+/* Structure for TVE */
+struct jz4810tve_info {
+	unsigned int ctrl;
+	unsigned int frcfg;
+	unsigned int slcfg1;
+	unsigned int slcfg2;
+	unsigned int slcfg3;
+	unsigned int ltcfg1;
+	unsigned int ltcfg2;
+	unsigned int cfreq;
+	unsigned int cphase;
+	unsigned int cbcrcfg;
+	unsigned int wsscr;
+	unsigned int wsscfg1;
+	unsigned int wsscfg2;
+	unsigned int wsscfg3;
+};
+
+extern struct jz4810tve_info *jz4810_tve_info;
+
+extern void jz4810tve_enable_tve(void);
+extern void jz4810tve_disable_tve(void);
+
+extern void jz4810tve_set_tve_mode( struct jz4810tve_info *tve );
+extern void jz4810tve_init( int tve_mode );
+
+
+#endif	/* __JZ4810_TVE_H__ */
diff --git a/drivers/video/jzepd.c b/drivers/video/jzepd.c
deleted file mode 100644
index 79ce8f31412..00000000000
--- a/drivers/video/jzepd.c
+++ /dev/null
@@ -1,2155 +0,0 @@
-/*
- * linux/drivers/video/jzepd.c -- Ingenic AUO-EPD frame buffer device
- *
- * This program is used to support Electronic Paper Display;
- * you can redistribute it and/or modify it according to your own needs.
- *
- * This driver supports 4/8level waveform.
- * The first writen by Cynthia <zhzhao@ingenic.cn>
- */
-
-#include "jz4760_epd.h"
-
-//#define EPD_DEBUG
-
-#ifdef EPD_DEBUG
-#define D(fmt, arg...)			printk(fmt, ##arg)
-#else
-#define D(fmt, arg...)
-#endif
-
-#define INVALID_TEMP -1
-#define VALID_TEMP    1
-
-#define MOD_INVALID  -2
-#define MOD_VALID     2
-
-#define EPD_SUCCESS   0
-
-#define TEMP_NUM  4
-#define MOD_NUM   4
-
-int  totally_time; // this is used to record multiple of 16 frames
-
-extern unsigned char *lcd_palette;
-
-enum epd_temperature_level
-{
-    	TEMP_LOW_LEVEL = 0,  //temp0
-	TEMP_HIGH_LEVEL ,    //temp1
-	TEMP_HIGHER_LEVEL ,  //temp2
-	TEMP_HIGHEST_LEVEL   //temp3
-};
-enum epd_temperature_level epd_temp_level;
-
-
-enum epd_mod_level
-{
-    	EPD_MOD_INIT = 0,  
- 	EPD_MOD_DU, // white/black level
- 	EPD_MOD_GU, //gray level
- 	EPD_MOD_GC  //update all display with gray level
-};
-enum epd_mod_level epd_mod_level;
-
-enum epd_gray_level
-{
-    	GRAY_LEVEL_4 = 4,
-	GRAY_LEVEL_8 = 8,
-	GRAY_LEVEL_16 = 16
-};
-enum epd_gray_level epd_gray_level;
-
-
-// waveform when temp = low level
-unsigned int waveform_temp0_init[]={
-};
-
-unsigned int waveform_temp0_du[]={
-};
-
-unsigned int waveform_temp0_gu[]={
-};
-
-unsigned int waveform_temp0_gc[]={
-};
-// waveform when temp = high level
-unsigned int waveform_temp1_init[]={
-};
-
-unsigned int waveform_temp1_du[]={
-};
-
-unsigned int waveform_temp1_gu[]={
-};
-
-unsigned int waveform_temp1_gc[]={
-};
-// waveform when temp = higher level
-unsigned int waveform_temp2_init[]={
-	0x55555554, 0xAAAAAAA8, 0x01555555, 0x500AAAAA, 0xAA801555, 0x555500AA, 0xAAAAA855, 0x55555402, 
-	0xAAAAAAA0,
-};
-
-unsigned int waveform_temp2_du[]={
-	0x01000080, 0x01000080, 0x05000080, 0x05000080, 0x05000080, 0x05000080, 0x15000080, 0x15000080, 
-	0x15000080, 0x150000A0, 0x150000A0, 0x150000A0, 0x150000A0, 0x150000A8, 0x150000A8, 0x00000000,
-};
-
-unsigned int waveform_temp2_gu[]={
-	0x01010100, 0x01010100, 0x05050104, 0x05050104, 0x05050104, 0x05050104, 0x15051114, 0x15051114,
-	0x15051114, 0x15051114, 0x15051114, 0x15051114, 0x15051114, 0x15051114, 0x15051114, 0, 
-        0x2A8AA2A8, 0x2A8AA2A8, 0x2A8AA2A8, 0x2A8AA2A8, 0x2A8AA2A8, 0x2A8AA2A8, 0x2A8AA2A8, 0x2A8AA2A8, 
-	0x2A8AA2A8, 0x2A8AA2A8, 0x2A8AA2A8, 0x2A8AA2A8, 0x2A8AA2A8, 0x2A8AA2A8, 0x2A8AA2A8, 0,
-	0x15455100, 0x15455100, 0x15450000, 0x15450000, 0x15450000, 0x15450000, 0x15000000, 0x15000000,
-	0x15000000, 0x15000000, 0x15000000, 0x15000000, 0x15000000, 0x15000000, 0x15000000, 0,
-};
-
-unsigned int waveform_temp2_gc[]={
-};
-
-// waveform when temp = highest level
-unsigned int waveform_temp3_init[]={
-	0x5555554A, 0xAAAAA855, 0x5555402A, 0xAAAAA005, 0x555554AA, 0xAAAA8555, 0x555402AA, 0xAAAA0000,
-};
-
-unsigned int waveform_temp3_du[]={
-	0x01000080,0x01000080,0x05000080,0x05000080,0x05000080,0x15000080,0x15000080,0x15000080,
-	0x150000A0,0x150000A0,0x150000A0,0x150000A8,0x150000A8,0x0,
-
-};
-
-unsigned int waveform_temp3_gu[]={
-	0x01010100, 0x01010100, 0x05050104, 0x05050104, 0x05050104, 0x15051114, 0x15051114, 0x15051114, 
-	0x15051114, 0x15051114, 0x15051114, 0x15051114, 0x15051114, 0,          0x2A8AA2A8, 0x2A8AA2A8,
-	0x2A8AA2A8, 0x2A8AA2A8, 0x2A8AA2A8, 0x2A8AA2A8, 0x2A8AA2A8, 0x2A8AA2A8, 0x2A8AA2A8, 0x2A8AA2A8,
-	0x2A8AA2A8, 0x2A8AA2A8, 0x2A8AA2A8, 0,        	0x15455100, 0x15455100, 0x15450000, 0x15450000,
-	0x15450000, 0x15000000, 0x15000000, 0x15000000, 0x15000000, 0x15000000, 0x15000000, 0x15000000, 
-	0x15000000, 0,
-
-};
-
-unsigned int waveform_temp3_gc[]={
-	0x01010101,0x01010101,0x05050505,0x05050505,0x05050505,0x15151515,0x15151515,0x15151515,
-	0x15151515,0x15151515,0x15151515,0x15151515,0x15151515,0x00000000,0xAAAAAAAA,0xAAAAAAAA,
-	0xAAAAAAAA,0xAAAAAAAA,0xAAAAAAAA,0xAAAAAAAA,0xAAAAAAAA,0xAAAAAAAA,0xAAAAAAAA,0xAAAAAAAA,
-	0xAAAAAAAA,0xAAAAAAAA,0xAAAAAAAA,0x00000000,0x55555500,0x55555500,0x55550000,0x55550000,
-	0x55550000,0x55000000,0x55000000,0x55000000,0x55000000,0x55000000,0x55000000,0x55000000,
-	0x55000000,0x00000000,
-};
-
-
-unsigned int waveform_handwriting[]={
-	0x01000080,0x01000080,
-};
-
-
-/*========8 gray level waveform =======*/
-
-unsigned int waveform8_temp0_init[]={
-};
-
-unsigned int waveform8_temp0_du[]={
-};
-
-unsigned int waveform8_temp0_gu[]={
-};
-
-unsigned int waveform8_temp0_gc[]={
-};
-// waveform when temp = high level
-unsigned int waveform8_temp1_init[]={
-};
-
-unsigned int waveform8_temp1_du[]={
-};
-
-unsigned int waveform8_temp1_gu[]={
-};
-
-unsigned int waveform8_temp1_gc[]={
-};
-// waveform when temp = higher level
-unsigned int waveform8_temp2_init[]={
-};
-
-unsigned int waveform8_temp2_du[]={
-};
-
-unsigned int waveform8_temp2_gu[]={
-};
-
-unsigned int waveform8_temp2_gc[]={
-};
-// waveform when temp = highest level
-unsigned int waveform8_temp3_init[]={
-	0x5555554A, 0xAAAAA955, 0x5555002A, 0xAAAAA001, 0x5555552A, 0xAAAAA555, 0x555400AA, 0xAAAA8000,
-};
-
-unsigned int waveform8_temp3_du[]={
-	0x00100000,0x00000000,0x00000000,0x00008000,0x00050000,0x00000000,0x00000000,0x0000A000,
-	0x00050000,0x00000000,0x00000000,0x0000A000,0x00150000,0x00000000,0x00000000,0x0000A800,
-	0x00150000,0x00000000,0x00000000,0x0000A800,0x00550000,0x00000000,0x00000000,0x0000AA00,
-	0x00550000,0x00000000,0x00000000,0x0000AA00,0x01550000,0x00000000,0x00000000,0x0000AA00,
-	0x01550000,0x00000000,0x00000000,0x0000AA80,0x05550000,0x00000000,0x00000000,0x0000AAA0,
-	0x05550000,0x00000000,0x00000000,0x0000AAA0,0x15550000,0x00000000,0x00000000,0x0000AAA8,
-	0x15550000,0x00000000,0x00000000,0x0000AAA8,0,         0,         0,         0,         
-
-};
-
-unsigned int waveform8_temp3_gu[]={
-
-	0x00010001, 0x00010001, 0x00010001, 0x00010000, 0x00050005, 0x00050005, 0x00050005, 0x00010004,
-	0x00050005, 0x00050005, 0x00050005, 0x00010004, 0x00150015, 0x00150015, 0x00150005, 0x00110014,
-	0x00150015, 0x00150015, 0x00150005, 0x00110014, 0x00550055, 0x00550055, 0x00150045, 0x00510054,
-	0x00550055, 0x00550055, 0x00150045, 0x00510054, 0x01550155, 0x01550055, 0x01150145, 0x01510154, 
-	0x01550155, 0x01550055, 0x01150145, 0x01510154, 0x05550555, 0x01550455, 0x05150545, 0x05510554, 
-	0x05550555, 0x01550455, 0x05150545, 0x05510554, 0x15550555, 0x11551455, 0x15151545, 0x15511554, 
-	0x15550555, 0x11551455, 0x15151545, 0x15511554, 0,          0,          0,          0,         
-	0x2AAA8AAA, 0xa2aaa8aa, 0xaa2a2a8a, 0xaaa2aaa8,  0x2AAA8AAA, 0xa2aaa8aa, 0xaa2a2a8a, 0xaaa2aaa8, 
-	0x2AAA8AAA, 0xa2aaa8aa, 0xaa2a2a8a, 0xaaa2aaa8, 0x2AAA8AAA, 0xa2aaa8aa, 0xaa2a2a8a, 0xaaa2aaa8, 
-	0x2AAA8AAA, 0xa2aaa8aa, 0xaa2a2a8a, 0xaaa2aaa8, 0x2AAA8AAA, 0xa2aaa8aa, 0xaa2a2a8a, 0xaaa2aaa8, 
-	0x2AAA8AAA, 0xa2aaa8aa, 0xaa2a2a8a, 0xaaa2aaa8, 0x2AAA8AAA, 0xa2aaa8aa, 0xaa2a2a8a, 0xaaa2aaa8, 
-	0x2AAA8AAA, 0xa2aaa8aa, 0xaa2a2a8a, 0xaaa2aaa8, 0x2AAA8AAA, 0xa2aaa8aa, 0xaa2a2a8a, 0xaaa2aaa8, 
-	0x2AAA8AAA, 0xa2aaa8aa, 0xaa2a2a8a, 0xaaa2aaa8, 0x2AAA8AAA, 0xa2aaa8aa, 0xaa2a2a8a, 0xaaa2aaa8, 
- 	0x2AAA8AAA, 0xa2aaa8aa, 0xaa2a2a8a, 0xaaa2aaa8, 0x15550000, 0,          0,          0,          
-	0x15554555, 0x51555455, 0x55155545, 0x55510000, 0x15554555, 0x51555455, 0x55155545, 0,         
-	0x15554555, 0x51555455, 0x55155545, 0,          0x15554555, 0x51555455, 0x55150000, 0,          
-	0x15554555, 0x51555455, 0x55150000, 0,          0x15554555, 0x51555455, 0,          0,          
-	0x15554555, 0x51555455, 0x00000000, 0,          0x15554555, 0x51550000, 0,          0,          
-	0x15554555, 0x51550000, 0x00000000, 0,          0x15554555, 0,          0,          0,          
-	0x15554555, 0,          0,          0,          0x15550000, 0,          0,          0,          
-	0,          0,          0,          0,          0,          0,          0,          0,
-};
-
-unsigned int waveform8_temp3_gc[]={
-
-	0x00010001, 0x00010001, 0x00010001, 0x00010001, 0x00050005, 0x00050005, 0x00050005, 0x00050005,
-	0x00050005, 0x00050005, 0x00050005, 0x00050005, 0x00150015, 0x00150015, 0x00150015, 0x00150015,
-	0x00150015, 0x00150015, 0x00150015, 0x00150015, 0x00550055, 0x00550055, 0x00550055, 0x00550055,
-	0x00550055, 0x00550055, 0x00550055, 0x00550055, 0x01550155, 0x01550155, 0x01550155, 0x01550155,  
-	0x01550155, 0x01550155, 0x01550155, 0x01550155, 0x05550555, 0x05550555, 0x05550555, 0x05550555, 
-	0x05550555, 0x05550555, 0x05550555, 0x05550555, 0x15551555, 0x15551555, 0x15551555, 0x15551555, 
-	0x15551555, 0x15551555, 0x15551555, 0x15551555, 0,          0,          0,          0,          
-	0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 
-	0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 
-	0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 
-	0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 
-	0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 
-	0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 
-	0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0x55550000, 0,          0,          0,         
-	0x55555555, 0x55555555, 0x55555555, 0x55550000,	0x55555555, 0x55555555, 0x55555555, 0,
-	0x55555555, 0x55555555, 0x55555555, 0,          0x55555555, 0x55555555, 0x55550000, 0,          
-	0x55555555, 0x55555555, 0x55550000, 0,          0x55555555, 0x55555555, 0,          0,          
-	0x55555555, 0x55555555, 0x00000000, 0,          0x55555555, 0x55550000, 0x00000000, 0,          
-	0x55555555, 0x55550000, 0x00000000, 0,          0x55555555, 0,          0,          0,          
-	0x55555555, 0,          0,          0,          0x55550000, 0,          0,          0,          
-	0,          0,          0,          0,          0,          0,          0,          0,
-	
-};
-
-/*========16 gray level waveform =======*/
-unsigned int waveform16_temp0_init[]={
-};
-
-unsigned int waveform16_temp0_du[]={
-};
-
-unsigned int waveform16_temp0_gu[]={
-};
-
-unsigned int waveform16_temp0_gc[]={
-};
-// waveform when temp = high level
-unsigned int waveform16_temp1_init[]={
-};
-
-unsigned int waveform16_temp1_du[]={
-};
-
-unsigned int waveform16_temp1_gu[]={
-};
-
-unsigned int waveform16_temp1_gc[]={
-};
-// waveform when temp = higher level
-unsigned int waveform16_temp2_init[]={
-};
-
-unsigned int waveform16_temp2_du[]={
-};
-
-unsigned int waveform16_temp2_gu[]={
-};
-
-unsigned int waveform16_temp2_gc[]={
-};
-
-// waveform when temp = highest level
-unsigned int waveform16_temp3_init[]={
-};
-
-unsigned int waveform16_temp3_du[]={
-};
-
-unsigned int waveform16_temp3_gu[]={
-};
-
-unsigned int waveform16_temp3_gc[]={
-};
-
-
-
-void printpalette(void *palette, int len)
-{
-	unsigned short *pal = (unsigned short *)palette;
-	int i;
-	printk("palette:\n");
-	for (i = 0; i < len; i++) {
-		if ((i*8)%256 == 0)
-			printk("\nfrm%d:\t", i*8/256);
-		if (i % 16 == 0)
-			printk("\n\t");
-		printk("%04x ", pal[i]);
-	}
-	printk("\n");
-}
-
-
-int get_temp_sensor(void)
-{
-	return 20;
-}
-
-/*identify different temperature zone*/
-int get_temp(void) 
-{
-	int temp =0 ;
-
-	temp = get_temp_sensor(); 
-
-	if (temp <=5 && temp >= 0)
-	{
-		epd_temp_level = TEMP_LOW_LEVEL;
-	}
-	else if (temp <=12 && temp >= 6)
-		epd_temp_level = TEMP_HIGH_LEVEL;
-
-	else if (temp <=17 && temp >= 13)
-		epd_temp_level = TEMP_HIGHER_LEVEL;
-
-	else if (temp <=50 && temp >= 18)
-		epd_temp_level = TEMP_HIGHEST_LEVEL;
-	
-	else 
-		return INVALID_TEMP;
-
-	return VALID_TEMP;
-}
-
-
-void fill_init_palette(void)
-{
-	int i, j, offset, bit2;
-	int max_frm ;
-	int index_per_frame = (1 << 8);
-	unsigned int *ptr = (unsigned int *)lcd_palette; 
-	int count=0, shift=0;
-	unsigned int *p;
-
-	memset(lcd_palette, 0x0, 4096*2);
-
-	get_temp();
-	D("%s:  temp(%d) gray level=%d. \n",__func__,epd_temp_level,epd_gray_level);
-
-	if(epd_gray_level == GRAY_LEVEL_4){
-		
-		if (epd_temp_level ==  TEMP_LOW_LEVEL)
-		{
-		
-			max_frm = 179;
-			// record the totally multiple of 16frames
-			if( max_frm%16 != 0)
-				totally_time = (1+max_frm/16); 
-			else
-				totally_time = max_frm/16;
-			
-			p = (unsigned int *)&waveform_temp0_init; // give waveform_temp2_init to p
-			for (j = 0; j < max_frm; j++) {	
-				
-				for(i=0;i<index_per_frame;i++){
-					/*
-					  (j * index_per_frame + i)*2(bit) = offset
-					  but it alligned by word, so offset = offset/32; 
-					*/
-					offset = (j * index_per_frame + i)*2/32; 
-					/*
-					  store by word so shif 2 bit per 2 bit voltage until 32bit(a word)
-					  from Lsb to Msb bit2 = 0,2,4,6,8,10...30
-					*/
-					bit2 = ((j * index_per_frame + i)%16)*2;
-
-					ptr[offset] |= ((*(p+count) >> (30-shift*2)) & 0x3) << bit2; 
-					
-				}
-				if (shift <15 )
-					shift ++;
-				else {
-					shift = 0;
-					count ++;
-				}
-			
-			}
-		}
-		else if (epd_temp_level ==  TEMP_HIGH_LEVEL)
-		{
-		
-			max_frm = 143;
-			
-			// record the totally multiple of 16frames
-			if( max_frm%16 != 0)
-				totally_time = (1+max_frm/16);
-			else
-				totally_time = max_frm/16;
-			
-			p = (unsigned int *)&waveform_temp1_init; // give waveform_temp2_init to p
-			for (j = 0; j < max_frm; j++) {	
-		
-				for(i=0;i<index_per_frame;i++){
-					offset = (j * index_per_frame + i)*2/32; 
-					bit2 = ((j * index_per_frame + i)%16)*2;
-					
-					ptr[offset] |= ((*(p+count) >> (30-shift*2)) & 0x3) << bit2; 
-					
-				}
-				if (shift <15 )
-					shift ++;
-				else {
-					count ++; 
-					shift = 0;
-					
-				}
-				
-			}
-
-		}
-		else if (epd_temp_level ==  TEMP_HIGHER_LEVEL)
-		{	
-	
-			max_frm = 143;
-			// record the totally multiple of 16frames
-			if( max_frm%16 != 0)
-				totally_time = (1+max_frm/16);
-			else
-				totally_time = max_frm/16;
-			
-			p =  (unsigned int *)&waveform_temp2_init; // give waveform_temp2_init to p
-			for (j = 0; j < max_frm; j++) {	
-				
-				for(i=0;i<index_per_frame;i++){
-					offset = (j * index_per_frame + i)*2/32; 
-				bit2 = ((j * index_per_frame + i)%16)*2;
-				
-				ptr[offset] |= ((*(p+count) >> (30-shift*2)) & 0x3) << bit2; 
-				
-				}
-				if (shift <15 ) // when shift(0~14),shift++, so shift tatally is 16
-					shift ++;
-				else {
-				count ++;  
-				shift = 0;
-				}
-				
-			}
-		}
-		else if (epd_temp_level ==  TEMP_HIGHEST_LEVEL)
-		{
-		
-			max_frm = 121;
-			// record the totally multiple of 16frames
-			if( max_frm%16 != 0)
-				totally_time = (1+max_frm/16);
-			else
-				totally_time = max_frm/16;
-			
-			p =  (unsigned int *)&waveform_temp3_init; // give waveform_temp2_init to p
-			for (j = 0; j < max_frm; j++) {	
-				
-				for(i=0;i<index_per_frame;i++){
-					
-					offset = (j * index_per_frame + i)*2/32; 
-					bit2 = ((j * index_per_frame + i)%16)*2;
-					
-					ptr[offset] |= ((*(p+count) >> (30-shift*2)) & 0x3) << bit2; 
-					
-				}
-				
-				if (shift < 15 )
-					shift ++;// when shift(0~14),shift++, so shift tatally is 16
-				else {
-					count ++;  
-					shift = 0;
-				}
-				
-			}
-		}
-		else{
-			printk("Invalid temperature level. \n");
-			return;	
-		}
-	}
-	if(epd_gray_level == GRAY_LEVEL_8){
-		if (epd_temp_level ==  TEMP_LOW_LEVEL)
-		{
-					
-			max_frm = 179;
-			// record the totally multiple of 16frames
-			if( max_frm%16 != 0)
-				totally_time = (1+max_frm/16); 
-			else
-				totally_time = max_frm/16;
-			
-			p = (unsigned int *)&waveform8_temp0_init; // give waveform_temp2_init to p
-			for (j = 0; j < max_frm; j++) {	
-				
-				for(i=0;i<index_per_frame;i++){
-					/*
-					  (j * index_per_frame + i)*2(bit) = offset
-					  but it alligned by word, so offset = offset/32; 
-					*/
-					offset = (j * index_per_frame + i)*2/32; 
-					/*
-					  store by word so shif 2 bit per 2 bit voltage until 32bit(a word)
-					  from Lsb to Msb bit2 = 0,2,4,6,8,10...30
-					*/
-					bit2 = ((j * index_per_frame + i)%16)*2;
-					
-					ptr[offset] |= ((*(p+count) >> (30-shift*2)) & 0x3) << bit2; 
-					
-				}
-				if (shift <15 )
-					shift ++;
-				else {
-					shift = 0;
-					count ++;
-			}
-				
-			}
-		}
-		else if (epd_temp_level ==  TEMP_HIGH_LEVEL)
-		{
-	
-			max_frm = 143;
-			
-			// record the totally multiple of 16frames
-			if( max_frm%16 != 0)
-				totally_time = (1+max_frm/16);
-			else
-				totally_time = max_frm/16;
-			
-			p = (unsigned int *)&waveform8_temp1_init; // give waveform_temp2_init to p
-			for (j = 0; j < max_frm; j++) {	
-				
-				for(i=0;i<index_per_frame;i++){
-					offset = (j * index_per_frame + i)*2/32; 
-					bit2 = ((j * index_per_frame + i)%16)*2;
-					
-					ptr[offset] |= ((*(p+count) >> (30-shift*2)) & 0x3) << bit2; 
-					
-				}
-				if (shift <15 )
-					shift ++;
-				else {
-					count ++; 
-					shift = 0;
-					
-				}
-				
-			}
-			
-		}
-		else if (epd_temp_level ==  TEMP_HIGHER_LEVEL)
-		{	
-	
-			max_frm = 143;
-			// record the totally multiple of 16frames
-			if( max_frm%16 != 0)
-				totally_time = (1+max_frm/16);
-			else
-				totally_time = max_frm/16;
-			
-			p =  (unsigned int *)&waveform8_temp2_init; // give waveform_temp2_init to p
-			for (j = 0; j < max_frm; j++) {	
-				
-				for(i=0;i<index_per_frame;i++){
-					offset = (j * index_per_frame + i)*2/32; 
-					bit2 = ((j * index_per_frame + i)%16)*2;
-					
-					ptr[offset] |= ((*(p+count) >> (30-shift*2)) & 0x3) << bit2; 
-					
-				}
-				if (shift <15 ) // when shift(0~14),shift++, so shift tatally is 16
-					shift ++;
-				else {
-					count ++;  
-					shift = 0;
-				}
-				
-			}
-		}
-		else if (epd_temp_level ==  TEMP_HIGHEST_LEVEL)
-		{
-		
-			max_frm = 122;
-			// record the totally multiple of 16frames
-			if( max_frm%16 != 0)
-				totally_time = (1+max_frm/16);
-			else
-				totally_time = max_frm/16;
-			
-			p =  (unsigned int *)&waveform8_temp3_init; // give waveform_temp2_init to p
-			for (j = 0; j < max_frm; j++) {	
-				
-				for(i=0;i<index_per_frame;i++){
-					
-					offset = (j * index_per_frame + i)*2/32; 
-					bit2 = ((j * index_per_frame + i)%16)*2;
-					
-					ptr[offset] |= ((*(p+count) >> (30-shift*2)) & 0x3) << bit2; 
-					
-				}
-				
-				if (shift < 15 )
-					shift ++;// when shift(0~14),shift++, so shift tatally is 16
-				else {
-					count ++;  
-					shift = 0;
-				}
-				
-			}
-		}
-		else{
-			printk("Invalid temperature level. \n");
-			return;	
-		}
-		
-	
-		
-		
-	}
-	if(epd_gray_level == GRAY_LEVEL_16){
-		if (epd_temp_level ==  TEMP_LOW_LEVEL)
-		{
-					
-			max_frm = 179;
-			// record the totally multiple of 16frames
-			if( max_frm%16 != 0)
-				totally_time = (1+max_frm/16); 
-			else
-				totally_time = max_frm/16;
-			
-			p = (unsigned int *)&waveform16_temp0_init; // give waveform_temp2_init to p
-			for (j = 0; j < max_frm; j++) {	
-				
-				for(i=0;i<index_per_frame;i++){
-					/*
-					  (j * index_per_frame + i)*2(bit) = offset
-					  but it alligned by word, so offset = offset/32; 
-					*/
-					offset = (j * index_per_frame + i)*2/32; 
-					/*
-					  store by word so shif 2 bit per 2 bit voltage until 32bit(a word)
-					  from Lsb to Msb bit2 = 0,2,4,6,8,10...30
-					*/
-					bit2 = ((j * index_per_frame + i)%16)*2;
-					
-					ptr[offset] |= ((*(p+count) >> (30-shift*2)) & 0x3) << bit2; 
-					
-				}
-				if (shift <15 )
-					shift ++;
-				else {
-					shift = 0;
-					count ++;
-			}
-				
-			}
-		}
-		else if (epd_temp_level ==  TEMP_HIGH_LEVEL)
-		{
-	
-			max_frm = 143;
-			
-			// record the totally multiple of 16frames
-			if( max_frm%16 != 0)
-				totally_time = (1+max_frm/16);
-			else
-				totally_time = max_frm/16;
-			
-			p = (unsigned int *)&waveform16_temp1_init; // give waveform_temp2_init to p
-			for (j = 0; j < max_frm; j++) {	
-				
-				for(i=0;i<index_per_frame;i++){
-					offset = (j * index_per_frame + i)*2/32; 
-					bit2 = ((j * index_per_frame + i)%16)*2;
-					
-					ptr[offset] |= ((*(p+count) >> (30-shift*2)) & 0x3) << bit2; 
-					
-				}
-				if (shift <15 )
-					shift ++;
-				else {
-					count ++; 
-					shift = 0;
-					
-				}
-				
-			}
-			
-		}
-		else if (epd_temp_level ==  TEMP_HIGHER_LEVEL)
-		{	
-	
-			max_frm = 143;
-			// record the totally multiple of 16frames
-			if( max_frm%16 != 0)
-				totally_time = (1+max_frm/16);
-			else
-				totally_time = max_frm/16;
-			
-			p =  (unsigned int *)&waveform16_temp2_init; // give waveform_temp2_init to p
-			for (j = 0; j < max_frm; j++) {	
-				
-				for(i=0;i<index_per_frame;i++){
-					offset = (j * index_per_frame + i)*2/32; 
-					bit2 = ((j * index_per_frame + i)%16)*2;
-					
-					ptr[offset] |= ((*(p+count) >> (30-shift*2)) & 0x3) << bit2; 
-					
-				}
-				if (shift <15 ) // when shift(0~14),shift++, so shift tatally is 16
-					shift ++;
-				else {
-					count ++;  
-					shift = 0;
-				}
-				
-			}
-		}
-		else if (epd_temp_level ==  TEMP_HIGHEST_LEVEL)
-		{
-		
-			max_frm = 122;
-			// record the totally multiple of 16frames
-			if( max_frm%16 != 0)
-				totally_time = (1+max_frm/16);
-			else
-				totally_time = max_frm/16;
-			
-			p =  (unsigned int *)&waveform16_temp3_init; // give waveform_temp2_init to p
-			for (j = 0; j < max_frm; j++) {	
-				
-				for(i=0;i<index_per_frame;i++){
-					
-					offset = (j * index_per_frame + i)*2/32; 
-					bit2 = ((j * index_per_frame + i)%16)*2;
-					
-					ptr[offset] |= ((*(p+count) >> (30-shift*2)) & 0x3) << bit2; 
-					
-				}
-				
-				if (shift < 15 )
-					shift ++;// when shift(0~14),shift++, so shift tatally is 16
-				else {
-					count ++;  
-					shift = 0;
-				}
-				
-			}
-		}
-		else{
-			printk("Invalid temperature level. \n");
-			return;	
-		}
-		
-	
-		
-		
-	}
-	
-	dma_cache_wback((unsigned int)(lcd_palette), 4096);
-//	printpalette((unsigned short *)((unsigned int)lcd_palette | 0xa0000000), 4096);
-}
-
-void fill_du_4level_gray(int max_frm,unsigned int *p)
-{
-
-	int i,j,old,new,offset, bit2;
-	int count; // count is offset of array
-	unsigned int *ptr = (unsigned int *)lcd_palette; 
-	int index_per_frame = (1 << 8);
-	memset(lcd_palette, 0x0, 4096);
-	// record the totally multiple of 16frames
-
-	if( max_frm%16 != 0)
-		totally_time = (1+max_frm/16);
-	else
-		totally_time = max_frm/16;
-	
-
-	for (j = 0; j < max_frm; j++) {
-		count = j;	
-		for(i=0;i<index_per_frame;i++){
-			
-			old = (i >> 4) & 0xf;
-			new = i & 0xf;
-			offset = (j * index_per_frame + i)*2/32; 
-			bit2 = ((j * index_per_frame + i)%16)*2;
-			
-			if(old == 0 && new == 0x0)
-				ptr[offset] |= ((*(p+count) >> (30-0*2)) & 0x3)<< bit2; 
-			if(old == 0xf && new == 0x0)
-				ptr[offset] |= ((*(p+count) >> (30-3*2)) & 0x3)<< bit2; 
-			
-			if(old == 0 && new == 0xf)
-				ptr[offset] |= ((*(p+count) >> (30-2*12)) & 0x3)<< bit2; 
-			if(old == 0xf && new == 0xf)
-				ptr[offset] |= ((*(p+count) >> (30-2*15)) & 0x3)<< bit2; 
-			
-		}
-		
-		
-	}
-			
-}
-
-void fill_du_8level_gray(int max_frm,unsigned int *p)
-{
-
-	int i,j,old,new,offset, bit2;
-	int count; // count is offset of array
-	unsigned int *ptr = (unsigned int *)lcd_palette; 
-	int index_per_frame = (1 << 8);
-	memset(lcd_palette, 0x0, 4096);
-	// record the totally multiple of 16frames
-
-	if( max_frm%16 != 0)
-		totally_time = (1+max_frm/16);
-	else
-		totally_time = max_frm/16;
-	
-
-	for (j = 0; j < max_frm; j++) {
-		count = 4*j;
-	
-		for(i=0;i<index_per_frame;i++){
-			
-			old = (i >> 4) & 0xf;
-			new = i & 0xf;
-			offset = (j * index_per_frame + i)*2/32; 
-			bit2 = ((j * index_per_frame + i)%16)*2;
-			
-			if(old == 0 && new == 0x0)
-				ptr[offset] |= ((*(p+count) >> (30-0*2)) & 0x3)<< bit2; 
-			if(old == 0xf && new == 0x0)
-				ptr[offset] |= ((*(p+count) >> (30-7*2)) & 0x3)<< bit2; 
-
-		
-		
-			if(old == 0 && new == 0xf)
-				ptr[offset] |= ((*(p+count+3) >> (30-8*2)) & 0x3)<< bit2; 
-			if(old == 0xf && new == 0xf)
-				ptr[offset] |= ((*(p+count+3) >> (30-2*15)) & 0x3)<< bit2; 
-			
-						
-		}
-		
-	       	
-	}
-
-}
-void fill_du_16level_gray(int max_frm,unsigned int *p)
-{
-
-	int i,j,old,new,offset, bit2;
-	int count; // count is offset of array
-	unsigned int *ptr = (unsigned int *)lcd_palette; 
-	int index_per_frame = (1 << 8);
-	memset(lcd_palette, 0x0, 4096);
-	// record the totally multiple of 16frames
-
-	if( max_frm%16 != 0)
-		totally_time = (1+max_frm/16);
-	else
-		totally_time = max_frm/16;
-	
-
-	for (j = 0; j < max_frm; j++) {
-		count = 16*j;
-	
-		for(i=0;i<index_per_frame;i++){
-			
-			old = (i >> 4) & 0xf;
-			new = i & 0xf;
-			offset = (j * index_per_frame + i)*2/32; 
-			bit2 = ((j * index_per_frame + i)%16)*2;
-			
-			if(old == 0 && new == 0x0)
-				ptr[offset] |= ((*(p+count) >> (30-0*2)) & 0x3)<< bit2; 
-			if(old == 0xf && new == 0x0)
-				ptr[offset] |= ((*(p+count) >> (30-15*2)) & 0x3)<< bit2; 
-
-		
-		
-			if(old == 0 && new == 0xf)
-				ptr[offset] |= ((*(p+count+15) >> (30-0*2)) & 0x3)<< bit2; 
-			if(old == 0xf && new == 0xf)
-				ptr[offset] |= ((*(p+count+15) >> (30-2*15)) & 0x3)<< bit2; 
-			
-						
-		}
-		
-	       	
-	}
-
-}
-
-void fill_du_palette(void)
-{
-
-	int max_frm ;
-	unsigned int *p;
-
-	get_temp();
-	D("%s:  temp(%d) gray level=%d. \n",__func__,epd_temp_level,epd_gray_level);
-
-	if(epd_gray_level == GRAY_LEVEL_4)
-	{
-		if (epd_temp_level ==  TEMP_LOW_LEVEL)
-		{
-		
-			max_frm = 16;
-			p =  (unsigned int *)&waveform_temp0_du; // give waveform_temp2_Du to p
-		
-			
-		}
-		else if (epd_temp_level ==  TEMP_HIGH_LEVEL)
-		{
-		
-			max_frm = 16;
-			p =  (unsigned int *)&waveform_temp1_du; // give waveform_temp2_Du to p	
-		
-		}
-		else if (epd_temp_level ==  TEMP_HIGHER_LEVEL)
-		{	
-		
-			max_frm = 14;
-			p =  (unsigned int *)&waveform_temp2_du; // give waveform_temp2_Du to p	
-		
-		}
-		
-		else if (epd_temp_level ==  TEMP_HIGHEST_LEVEL)
-		{
-		
-			max_frm = 14;
-			p =  (unsigned int *)&waveform_temp3_du; 
-		
-
-		}
-		else{
-			printk("Invalid temperature level. \n");
-			return;	
-		}
-	
-		fill_du_4level_gray(max_frm,p);
-	}
-
-	if(epd_gray_level == GRAY_LEVEL_8)
-	{
-	
-
-		if (epd_temp_level ==  TEMP_LOW_LEVEL)
-		{
-		
-			max_frm = 16;
-			p =  (unsigned int *)&waveform8_temp0_du; // give waveform_temp2_Du to p
-		
-			
-		}
-		else if (epd_temp_level ==  TEMP_HIGH_LEVEL)
-		{
-		
-			max_frm = 16;
-			p =  (unsigned int *)&waveform8_temp1_du; // give waveform_temp2_Du to p
-			
-		}
-		else if (epd_temp_level ==  TEMP_HIGHER_LEVEL)
-		{	
-		
-			max_frm = 14;
-			p =  (unsigned int *)&waveform8_temp2_du; // give waveform_temp2_Du to p			
-			
-		}
-		
-		else if (epd_temp_level ==  TEMP_HIGHEST_LEVEL)
-		{
-			max_frm = 14;
-			p =  (unsigned int *)&waveform8_temp3_du; 
-		}
-		else{
-			printk("Invalid temperature level. \n");
-			return;	
-		}
-		
-		fill_du_8level_gray(max_frm,p);
-	}
-	if(epd_gray_level == GRAY_LEVEL_16)
-	{
-		// add 16level gray support
-	
-
-		if (epd_temp_level ==  TEMP_LOW_LEVEL)
-		{
-		
-			max_frm = 16;
-			p =  (unsigned int *)&waveform16_temp0_du; // give waveform_temp2_Du to p
-		
-			
-		}
-		else if (epd_temp_level ==  TEMP_HIGH_LEVEL)
-		{
-		
-			max_frm = 16;
-			p =  (unsigned int *)&waveform16_temp1_du; // give waveform_temp2_Du to p
-			
-		}
-		else if (epd_temp_level ==  TEMP_HIGHER_LEVEL)
-		{	
-		
-			max_frm = 14;
-			p =  (unsigned int *)&waveform16_temp2_du; // give waveform_temp2_Du to p			
-			
-		}
-		
-		else if (epd_temp_level ==  TEMP_HIGHEST_LEVEL)
-		{
-			max_frm = 14;
-			p =  (unsigned int *)&waveform16_temp3_du; 
-		}
-		else{
-			printk("Invalid temperature level. \n");
-			return;	
-		}
-		
-		fill_du_8level_gray(max_frm,p);
-
-
-
-	}
-	dma_cache_wback((unsigned int)(lcd_palette), 4096);
-//	printpalette((unsigned short *)((unsigned int)lcd_palette | 0xa0000000), 2048);
-		
-}
-
-
-void fill_16level_gray(int max_frm,unsigned int *p)
-{
-	int i,j,old,new,offset, bit2;
-	int index_per_frame = (1 << 8);
-	int count; // count is offset of array
-	unsigned int *ptr = (unsigned int *)lcd_palette; 
-	memset(lcd_palette, 0x0, 4096);
-
-	// record the totally multiple of 16frames
-	if( max_frm%16 != 0)
-		totally_time = (1+max_frm/16);
-	else
-		totally_time = max_frm/16;
-	
-	for (j = 0; j < max_frm; j++) {	
-		count = 16*j;
-		for(i=0;i<index_per_frame;i++){
-			old = (i >> 4) & 0xf;
-			new = i & 0xf;
-			offset = (j * index_per_frame + i)*2/32; 
-			bit2 = ((j * index_per_frame + i)%16)*2;
-			
-			if(new == 0 && old == 0)
-				ptr[offset] |= ((*(p+count) >> (30-0*2)) & 0x3) << bit2; 
-			if(new == 0 && old == 0x1)
-				ptr[offset] |= ((*(p+count) >> (30-1*2)) & 0x3) << bit2; 
-			if(new == 0 && old == 0x2)
-				ptr[offset] |= ((*(p+count) >> (30-2*2)) & 0x3) << bit2; 
-			if(new == 0 && old == 0x3)
-				ptr[offset] |= ((*(p+count) >> (30-3*2)) & 0x3) << bit2; 
-			if(new == 0 && old == 0x4)
-				ptr[offset] |= ((*(p+count) >> (30-4*2)) & 0x3) << bit2; 
-			if(new == 0 && old == 0x5)
-				ptr[offset] |= ((*(p+count) >> (30-5*2)) & 0x3) << bit2; 
-			if(new == 0 && old == 0x6)
-				ptr[offset] |= ((*(p+count) >> (30-6*2)) & 0x3) << bit2; 
-			if(new == 0 && old == 0x7)
-				ptr[offset] |= ((*(p+count) >> (30-7*2)) & 0x3) << bit2; 
-			if(new == 0x0 && old == 0x8)
-				ptr[offset] |= ((*(p+count) >> (30-8*2)) & 0x3) << bit2; 
-			if(new == 0x0 && old == 0x9)
-				ptr[offset] |= ((*(p+count) >> (30-9*2)) & 0x3) << bit2; 
-			if(new == 0x0 && old == 0xa)
-				ptr[offset] |= ((*(p+count) >> (30-10*2)) & 0x3) << bit2; 
-			if(new == 0x0 && old == 0xb)
-				ptr[offset] |= ((*(p+count) >> (30-11*2)) & 0x3) << bit2; 
-			if(new == 0x0 && old == 0xc)
-				ptr[offset] |= ((*(p+count) >> (30-12*2)) & 0x3) << bit2; 
-			if(new == 0x0 && old == 0xd)
-				ptr[offset] |= ((*(p+count) >> (30-13*2)) & 0x3) << bit2; 
-			if(new == 0x0 && old == 0xe)
-				ptr[offset] |= ((*(p+count) >> (30-14*2)) & 0x3) << bit2; 
-			if(new == 0x0 && old == 0xf)
-				ptr[offset] |= ((*(p+count) >> (30-15*2)) & 0x3) << bit2; 
-
-
-			if(new == 0x1 && old == 0)
-				ptr[offset] |= ((*(p+count+1) >> (30-0*2)) & 0x3) << bit2; 
-			if(new == 0x1 && old == 0x1)
-				ptr[offset] |= ((*(p+count+1) >> (30-1*2)) & 0x3) << bit2; 
-			if(new == 0x1 && old == 0x2)
-				ptr[offset] |= ((*(p+count+1) >> (30-2*2)) & 0x3) << bit2; 
-			if(new == 0x1 && old == 0x3)
-				ptr[offset] |= ((*(p+count+1) >> (30-3*2)) & 0x3) << bit2; 
-			if(new == 0x1 && old == 0x4)
-				ptr[offset] |= ((*(p+count+1) >> (30-4*2)) & 0x3) << bit2; 
-			if(new == 0x1 && old == 0x5)
-				ptr[offset] |= ((*(p+count+1) >> (30-5*2)) & 0x3) << bit2; 
-			if(new == 0x1 && old == 0x6)
-				ptr[offset] |= ((*(p+count+1) >> (30-6*2)) & 0x3) << bit2; 
-			if(new == 0x1 && old == 0x7)
-				ptr[offset] |= ((*(p+count+1) >> (30-7*2)) & 0x3) << bit2; 
-			if(new == 0x1 && old == 0x8)
-				ptr[offset] |= ((*(p+count+1) >> (30-8*2)) & 0x3) << bit2; 
-			if(new == 0x1 && old == 0x9)
-				ptr[offset] |= ((*(p+count+1) >> (30-9*2)) & 0x3) << bit2; 
-			if(new == 0x1 && old == 0xa)
-				ptr[offset] |= ((*(p+count+1) >> (30-10*2)) & 0x3) << bit2; 
-			if(new == 0x1 && old == 0xb)
-				ptr[offset] |= ((*(p+count+1) >> (30-11*2)) & 0x3) << bit2; 
-			if(new == 0x1 && old == 0xc)
-				ptr[offset] |= ((*(p+count+1) >> (30-12*2)) & 0x3) << bit2; 
-			if(new == 0x1 && old == 0xd)
-				ptr[offset] |= ((*(p+count+1) >> (30-13*2)) & 0x3) << bit2; 
-			if(new == 0x1 && old == 0xe)
-				ptr[offset] |= ((*(p+count+1) >> (30-14*2)) & 0x3) << bit2; 
-			if(new == 0x1 && old == 0xf)
-				ptr[offset] |= ((*(p+count+1) >> (30-15*2)) & 0x3) << bit2; 
-
-
-			if(new == 0x2 && old == 0)
-				ptr[offset] |= ((*(p+count+2) >> (30-0*2)) & 0x3) << bit2; 
-			if(new == 0x2 && old == 0x1)
-				ptr[offset] |= ((*(p+count+2) >> (30-1*2)) & 0x3) << bit2; 
-			if(new == 0x2 && old == 0x2)
-				ptr[offset] |= ((*(p+count+2) >> (30-2*2)) & 0x3) << bit2; 
-			if(new == 0x2 && old == 0x3)
-				ptr[offset] |= ((*(p+count+2) >> (30-3*2)) & 0x3) << bit2; 
-			if(new == 0x2 && old == 0x4)
-				ptr[offset] |= ((*(p+count+2) >> (30-4*2)) & 0x3) << bit2; 
-			if(new == 0x2 && old == 0x5)
-				ptr[offset] |= ((*(p+count+2) >> (30-5*2)) & 0x3) << bit2; 
-			if(new == 0x2 && old == 0x6)
-				ptr[offset] |= ((*(p+count+2) >> (30-6*2)) & 0x3) << bit2; 
-			if(new == 0x2 && old == 0x7)
-				ptr[offset] |= ((*(p+count+2) >> (30-7*2)) & 0x3) << bit2; 
-			if(new == 0x2 && old == 0x8)
-				ptr[offset] |= ((*(p+count+2) >> (30-8*2)) & 0x3) << bit2; 
-			if(new == 0x2 && old == 0x9)
-				ptr[offset] |= ((*(p+count+2) >> (30-9*2)) & 0x3) << bit2; 
-			if(new == 0x2 && old == 0xa)
-				ptr[offset] |= ((*(p+count+2) >> (30-10*2)) & 0x3) << bit2; 
-			if(new == 0x2 && old == 0xb)
-				ptr[offset] |= ((*(p+count+2) >> (30-11*2)) & 0x3) << bit2; 
-			if(new == 0x2 && old == 0xc)
-				ptr[offset] |= ((*(p+count+2) >> (30-12*2)) & 0x3) << bit2; 
-			if(new == 0x2 && old == 0xd)
-				ptr[offset] |= ((*(p+count+2) >> (30-13*2)) & 0x3) << bit2; 
-			if(new == 0x2 && old == 0xe)
-				ptr[offset] |= ((*(p+count+2) >> (30-14*2)) & 0x3) << bit2; 
-			if(new == 0x2 && old == 0xf)
-				ptr[offset] |= ((*(p+count+2) >> (30-15*2)) & 0x3) << bit2; 
-
-			if(new == 0x3 && old == 0)
-				ptr[offset] |= ((*(p+count+3) >> (30-0*2)) & 0x3) << bit2; 
-			if(new == 0x3 && old == 0x1)
-				ptr[offset] |= ((*(p+count+3) >> (30-1*2)) & 0x3) << bit2; 
-			if(new == 0x3 && old == 0x2)
-				ptr[offset] |= ((*(p+count+3) >> (30-2*2)) & 0x3) << bit2; 
-			if(new == 0x3 && old == 0x3)
-				ptr[offset] |= ((*(p+count+3) >> (30-3*2)) & 0x3) << bit2; 
-			if(new == 0x3 && old == 0x4)
-				ptr[offset] |= ((*(p+count+3) >> (30-4*2)) & 0x3) << bit2; 
-			if(new == 0x3 && old == 0x5)
-				ptr[offset] |= ((*(p+count+3) >> (30-5*2)) & 0x3) << bit2; 
-			if(new == 0x3 && old == 0x6)
-				ptr[offset] |= ((*(p+count+3) >> (30-6*2)) & 0x3) << bit2; 
-			if(new == 0x3 && old == 0x7)
-				ptr[offset] |= ((*(p+count+3) >> (30-7*2)) & 0x3) << bit2; 
-			if(new == 0x3 && old == 0x8)
-				ptr[offset] |= ((*(p+count+3) >> (30-8*2)) & 0x3) << bit2; 
-			if(new == 0x3 && old == 0x9)
-				ptr[offset] |= ((*(p+count+3) >> (30-9*2)) & 0x3) << bit2; 
-			if(new == 0x3 && old == 0xa)
-				ptr[offset] |= ((*(p+count+3) >> (30-10*2)) & 0x3) << bit2; 
-			if(new == 0x3 && old == 0xb)
-				ptr[offset] |= ((*(p+count+3) >> (30-11*2)) & 0x3) << bit2; 
-			if(new == 0x3 && old == 0xc)
-				ptr[offset] |= ((*(p+count+3) >> (30-12*2)) & 0x3) << bit2; 
-			if(new == 0x3 && old == 0xd)
-				ptr[offset] |= ((*(p+count+3) >> (30-13*2)) & 0x3) << bit2; 
-			if(new == 0x3 && old == 0xe)
-				ptr[offset] |= ((*(p+count+3) >> (30-14*2)) & 0x3) << bit2; 
-			if(new == 0x3 && old == 0xf)
-				ptr[offset] |= ((*(p+count+3) >> (30-15*2)) & 0x3) << bit2; 
-			
-			
-			if(new == 0x4 && old == 0)
-				ptr[offset] |= ((*(p+count+4) >> (30-0*2)) & 0x3) << bit2; 
-			if(new == 0x4 && old == 0x1)
-				ptr[offset] |= ((*(p+count+4) >> (30-1*2)) & 0x3) << bit2; 
-			if(new == 0x4 && old == 0x2)
-				ptr[offset] |= ((*(p+count+4) >> (30-2*2)) & 0x3) << bit2; 
-			if(new == 0x4 && old == 0x3)
-				ptr[offset] |= ((*(p+count+4) >> (30-3*2)) & 0x3) << bit2; 
-			if(new == 0x4 && old == 0x4)
-				ptr[offset] |= ((*(p+count+4) >> (30-4*2)) & 0x3) << bit2; 
-			if(new == 0x4 && old == 0x5)
-				ptr[offset] |= ((*(p+count+4) >> (30-5*2)) & 0x3) << bit2; 
-			if(new == 0x4 && old == 0x6)
-				ptr[offset] |= ((*(p+count+4) >> (30-6*2)) & 0x3) << bit2; 
-			if(new == 0x4 && old == 0x7)
-				ptr[offset] |= ((*(p+count+4) >> (30-7*2)) & 0x3) << bit2; 
-			if(new == 0x4 && old == 0x8)
-				ptr[offset] |= ((*(p+count+4) >> (30-8*2)) & 0x3) << bit2; 
-			if(new == 0x4 && old == 0x9)
-				ptr[offset] |= ((*(p+count+4) >> (30-9*2)) & 0x3) << bit2; 
-			if(new == 0x4 && old == 0xa)
-				ptr[offset] |= ((*(p+count+4) >> (30-10*2)) & 0x3) << bit2; 
-			if(new == 0x4 && old == 0xb)
-				ptr[offset] |= ((*(p+count+4) >> (30-11*2)) & 0x3) << bit2; 
-			if(new == 0x4 && old == 0xc)
-				ptr[offset] |= ((*(p+count+4) >> (30-12*2)) & 0x3) << bit2; 
-			if(new == 0x4 && old == 0xd)
-				ptr[offset] |= ((*(p+count+4) >> (30-13*2)) & 0x3) << bit2; 
-			if(new == 0x4 && old == 0xe)
-				ptr[offset] |= ((*(p+count+4) >> (30-14*2)) & 0x3) << bit2; 
-			if(new == 0x4 && old == 0xf)
-				ptr[offset] |= ((*(p+count+4) >> (30-15*2)) & 0x3) << bit2; 
-
-
-			if(new == 0x5 && old == 0)
-				ptr[offset] |= ((*(p+count+5) >> (30-0*2)) & 0x3) << bit2; 
-			if(new == 0x5 && old == 0x1)
-				ptr[offset] |= ((*(p+count+5) >> (30-1*2)) & 0x3) << bit2; 
-			if(new == 0x5 && old == 0x2)
-				ptr[offset] |= ((*(p+count+5) >> (30-2*2)) & 0x3) << bit2; 
-			if(new == 0x5 && old == 0x3)
-				ptr[offset] |= ((*(p+count+5) >> (30-3*2)) & 0x3) << bit2; 
-			if(new == 0x5 && old == 0x4)
-				ptr[offset] |= ((*(p+count+5) >> (30-4*2)) & 0x3) << bit2; 
-			if(new == 0x5 && old == 0x5)
-				ptr[offset] |= ((*(p+count+5) >> (30-5*2)) & 0x3) << bit2; 
-			if(new == 0x5 && old == 0x6)
-				ptr[offset] |= ((*(p+count+5) >> (30-6*2)) & 0x3) << bit2; 
-			if(new == 0x5 && old == 0x7)
-				ptr[offset] |= ((*(p+count+5) >> (30-7*2)) & 0x3) << bit2; 
-			if(new == 0x5 && old == 0x8)
-				ptr[offset] |= ((*(p+count+5) >> (30-8*2)) & 0x3) << bit2; 
-			if(new == 0x5 && old == 0x9)
-				ptr[offset] |= ((*(p+count+5) >> (30-9*2)) & 0x3) << bit2; 
-			if(new == 0x5 && old == 0xa)
-				ptr[offset] |= ((*(p+count+5) >> (30-10*2)) & 0x3) << bit2; 
-			if(new == 0x5 && old == 0xb)
-				ptr[offset] |= ((*(p+count+5) >> (30-11*2)) & 0x3) << bit2; 
-			if(new == 0x5 && old == 0xc)
-				ptr[offset] |= ((*(p+count+5) >> (30-12*2)) & 0x3) << bit2; 
-			if(new == 0x5 && old == 0xd)
-				ptr[offset] |= ((*(p+count+5) >> (30-13*2)) & 0x3) << bit2; 
-			if(new == 0x5 && old == 0xe)
-				ptr[offset] |= ((*(p+count+5) >> (30-14*2)) & 0x3) << bit2; 
-			if(new == 0x5 && old == 0xf)
-				ptr[offset] |= ((*(p+count+5) >> (30-15*2)) & 0x3) << bit2; 
-
-			if(new == 0x6 && old == 0)
-				ptr[offset] |= ((*(p+count+6) >> (30-0*2)) & 0x3) << bit2; 
-			if(new == 0x6 && old == 0x1)
-				ptr[offset] |= ((*(p+count+6) >> (30-1*2)) & 0x3) << bit2; 
-			if(new == 0x6 && old == 0x2)
-				ptr[offset] |= ((*(p+count+6) >> (30-2*2)) & 0x3) << bit2; 
-			if(new == 0x6 && old == 0x3)
-				ptr[offset] |= ((*(p+count+6) >> (30-3*2)) & 0x3) << bit2; 
-			if(new == 0x6 && old == 0x4)
-				ptr[offset] |= ((*(p+count+6) >> (30-4*2)) & 0x3) << bit2; 
-			if(new == 0x6 && old == 0x5)
-				ptr[offset] |= ((*(p+count+6) >> (30-5*2)) & 0x3) << bit2; 
-			if(new == 0x6 && old == 0x6)
-				ptr[offset] |= ((*(p+count+6) >> (30-6*2)) & 0x3) << bit2; 
-			if(new == 0x6 && old == 0x7)
-				ptr[offset] |= ((*(p+count+6) >> (30-7*2)) & 0x3) << bit2; 
-			if(new == 0x6 && old == 0x8)
-				ptr[offset] |= ((*(p+count+6) >> (30-8*2)) & 0x3) << bit2; 
-			if(new == 0x6 && old == 0x9)
-				ptr[offset] |= ((*(p+count+6) >> (30-9*2)) & 0x3) << bit2; 
-			if(new == 0x6 && old == 0xa)
-				ptr[offset] |= ((*(p+count+6) >> (30-10*2)) & 0x3) << bit2; 
-			if(new == 0x6 && old == 0xb)
-				ptr[offset] |= ((*(p+count+6) >> (30-11*2)) & 0x3) << bit2; 
-			if(new == 0x6 && old == 0xc)
-				ptr[offset] |= ((*(p+count+6) >> (30-12*2)) & 0x3) << bit2; 
-			if(new == 0x6 && old == 0xd)
-				ptr[offset] |= ((*(p+count+6) >> (30-13*2)) & 0x3) << bit2; 
-			if(new == 0x6 && old == 0xe)
-				ptr[offset] |= ((*(p+count+6) >> (30-14*2)) & 0x3) << bit2; 
-			if(new == 0x6 && old == 0xf)
-				ptr[offset] |= ((*(p+count+6) >> (30-15*2)) & 0x3) << bit2; 
-
-			if(new == 0x7 && old == 0)
-				ptr[offset] |= ((*(p+count+7) >> (30-0*2)) & 0x3) << bit2; 
-			if(new == 0x7 && old == 0x1)
-				ptr[offset] |= ((*(p+count+7) >> (30-1*2)) & 0x3) << bit2; 
-			if(new == 0x7 && old == 0x2)
-				ptr[offset] |= ((*(p+count+7) >> (30-2*2)) & 0x3) << bit2; 
-			if(new == 0x7 && old == 0x3)
-				ptr[offset] |= ((*(p+count+7) >> (30-3*2)) & 0x3) << bit2; 
-			if(new == 0x7 && old == 0x4)
-				ptr[offset] |= ((*(p+count+7) >> (30-4*2)) & 0x3) << bit2; 
-			if(new == 0x7 && old == 0x5)
-				ptr[offset] |= ((*(p+count+7) >> (30-5*2)) & 0x3) << bit2; 
-			if(new == 0x7 && old == 0x6)
-				ptr[offset] |= ((*(p+count+7) >> (30-6*2)) & 0x3) << bit2; 
-			if(new == 0x7 && old == 0x7)
-				ptr[offset] |= ((*(p+count+7) >> (30-7*2)) & 0x3) << bit2; 
-			if(new == 0x7 && old == 0x8)
-				ptr[offset] |= ((*(p+count+7) >> (30-8*2)) & 0x3) << bit2; 
-			if(new == 0x7 && old == 0x9)
-				ptr[offset] |= ((*(p+count+7) >> (30-9*2)) & 0x3) << bit2; 
-			if(new == 0x7 && old == 0xa)
-				ptr[offset] |= ((*(p+count+7) >> (30-10*2)) & 0x3) << bit2; 
-			if(new == 0x7 && old == 0xb)
-				ptr[offset] |= ((*(p+count+7) >> (30-11*2)) & 0x3) << bit2; 
-			if(new == 0x7 && old == 0xc)
-				ptr[offset] |= ((*(p+count+7) >> (30-12*2)) & 0x3) << bit2; 
-			if(new == 0x7 && old == 0xd)
-				ptr[offset] |= ((*(p+count+7) >> (30-13*2)) & 0x3) << bit2; 
-			if(new == 0x7 && old == 0xe)
-				ptr[offset] |= ((*(p+count+7) >> (30-14*2)) & 0x3) << bit2; 
-			if(new == 0x7 && old == 0xf)
-				ptr[offset] |= ((*(p+count+7) >> (30-15*2)) & 0x3) << bit2; 
-
-			if(new == 0x8 && old == 0)
-				ptr[offset] |= ((*(p+count+8) >> (30-0*2)) & 0x3) << bit2; 
-			if(new == 0x8 && old == 0x1)
-				ptr[offset] |= ((*(p+count+8) >> (30-1*2)) & 0x3) << bit2; 
-			if(new == 0x8 && old == 0x2)
-				ptr[offset] |= ((*(p+count+8) >> (30-2*2)) & 0x3) << bit2; 
-			if(new == 0x8 && old == 0x3)
-				ptr[offset] |= ((*(p+count+8) >> (30-3*2)) & 0x3) << bit2; 
-			if(new == 0x8 && old == 0x4)
-				ptr[offset] |= ((*(p+count+8) >> (30-4*2)) & 0x3) << bit2; 
-			if(new == 0x8 && old == 0x5)
-				ptr[offset] |= ((*(p+count+8) >> (30-5*2)) & 0x3) << bit2; 
-			if(new == 0x8 && old == 0x6)
-				ptr[offset] |= ((*(p+count+8) >> (30-6*2)) & 0x3) << bit2; 
-			if(new == 0x8 && old == 0x7)
-				ptr[offset] |= ((*(p+count+8) >> (30-7*2)) & 0x3) << bit2; 
-			if(new == 0x8 && old == 0x8)
-				ptr[offset] |= ((*(p+count+8) >> (30-8*2)) & 0x3) << bit2; 
-			if(new == 0x8 && old == 0x9)
-				ptr[offset] |= ((*(p+count+8) >> (30-9*2)) & 0x3) << bit2; 
-			if(new == 0x8 && old == 0xa)
-				ptr[offset] |= ((*(p+count+8) >> (30-10*2)) & 0x3) << bit2; 
-			if(new == 0x8 && old == 0xb)
-				ptr[offset] |= ((*(p+count+8) >> (30-11*2)) & 0x3) << bit2; 
-			if(new == 0x8 && old == 0xc)
-				ptr[offset] |= ((*(p+count+8) >> (30-12*2)) & 0x3) << bit2; 
-			if(new == 0x8 && old == 0xd)
-				ptr[offset] |= ((*(p+count+8) >> (30-13*2)) & 0x3) << bit2; 
-			if(new == 0x8 && old == 0xe)
-				ptr[offset] |= ((*(p+count+8) >> (30-14*2)) & 0x3) << bit2; 
-			if(new == 0x8 && old == 0xf)
-				ptr[offset] |= ((*(p+count+8) >> (30-15*2)) & 0x3) << bit2; 
-
-			if(new == 0x9 && old == 0)
-				ptr[offset] |= ((*(p+count+9) >> (30-0*2)) & 0x3) << bit2; 
-			if(new == 0x9 && old == 0x1)
-				ptr[offset] |= ((*(p+count+9) >> (30-1*2)) & 0x3) << bit2; 
-			if(new == 0x9 && old == 0x2)
-				ptr[offset] |= ((*(p+count+9) >> (30-2*2)) & 0x3) << bit2; 
-			if(new == 0x9 && old == 0x3)
-				ptr[offset] |= ((*(p+count+9) >> (30-3*2)) & 0x3) << bit2; 
-			if(new == 0x9 && old == 0x4)
-				ptr[offset] |= ((*(p+count+9) >> (30-4*2)) & 0x3) << bit2; 
-			if(new == 0x9 && old == 0x5)
-				ptr[offset] |= ((*(p+count+9) >> (30-5*2)) & 0x3) << bit2; 
-			if(new == 0x9 && old == 0x6)
-				ptr[offset] |= ((*(p+count+9) >> (30-6*2)) & 0x3) << bit2; 
-			if(new == 0x9 && old == 0x7)
-				ptr[offset] |= ((*(p+count+9) >> (30-7*2)) & 0x3) << bit2; 
-			if(new == 0x9 && old == 0x8)
-				ptr[offset] |= ((*(p+count+9) >> (30-8*2)) & 0x3) << bit2; 
-			if(new == 0x9 && old == 0x9)
-				ptr[offset] |= ((*(p+count+9) >> (30-9*2)) & 0x3) << bit2; 
-			if(new == 0x9 && old == 0xa)
-				ptr[offset] |= ((*(p+count+9) >> (30-10*2)) & 0x3) << bit2; 
-			if(new == 0x9 && old == 0xb)
-				ptr[offset] |= ((*(p+count+9) >> (30-11*2)) & 0x3) << bit2; 
-			if(new == 0x9 && old == 0xc)
-				ptr[offset] |= ((*(p+count+9) >> (30-12*2)) & 0x3) << bit2; 
-			if(new == 0x9 && old == 0xd)
-				ptr[offset] |= ((*(p+count+9) >> (30-13*2)) & 0x3) << bit2; 
-			if(new == 0x9 && old == 0xe)
-				ptr[offset] |= ((*(p+count+9) >> (30-14*2)) & 0x3) << bit2; 
-			if(new == 0x9 && old == 0xf)
-				ptr[offset] |= ((*(p+count+9) >> (30-15*2)) & 0x3) << bit2; 
-
-			if(new == 0xa && old == 0)
-				ptr[offset] |= ((*(p+count+10) >> (30-0*2)) & 0x3) << bit2; 
-			if(new == 0xa && old == 0x1)
-				ptr[offset] |= ((*(p+count+10) >> (30-1*2)) & 0x3) << bit2; 
-			if(new == 0xa && old == 0x2)
-				ptr[offset] |= ((*(p+count+10) >> (30-2*2)) & 0x3) << bit2; 
-			if(new == 0xa && old == 0x3)
-				ptr[offset] |= ((*(p+count+10) >> (30-3*2)) & 0x3) << bit2; 
-			if(new == 0xa && old == 0x4)
-				ptr[offset] |= ((*(p+count+10) >> (30-4*2)) & 0x3) << bit2; 
-			if(new == 0xa && old == 0x5)
-				ptr[offset] |= ((*(p+count+10) >> (30-5*2)) & 0x3) << bit2; 
-			if(new == 0xa && old == 0x6)
-				ptr[offset] |= ((*(p+count+10) >> (30-6*2)) & 0x3) << bit2; 
-			if(new == 0xa && old == 0x7)
-				ptr[offset] |= ((*(p+count+10) >> (30-7*2)) & 0x3) << bit2; 
-			if(new == 0xa && old == 0x8)
-				ptr[offset] |= ((*(p+count+10) >> (30-8*2)) & 0x3) << bit2; 
-			if(new == 0xa && old == 0x9)
-				ptr[offset] |= ((*(p+count+10) >> (30-9*2)) & 0x3) << bit2; 
-			if(new == 0xa && old == 0xa)
-				ptr[offset] |= ((*(p+count+10) >> (30-10*2)) & 0x3) << bit2; 
-			if(new == 0xa && old == 0xb)
-				ptr[offset] |= ((*(p+count+10) >> (30-11*2)) & 0x3) << bit2; 
-			if(new == 0xa && old == 0xc)
-				ptr[offset] |= ((*(p+count+10) >> (30-12*2)) & 0x3) << bit2; 
-			if(new == 0xa && old == 0xd)
-				ptr[offset] |= ((*(p+count+10) >> (30-13*2)) & 0x3) << bit2; 
-			if(new == 0xa && old == 0xe)
-				ptr[offset] |= ((*(p+count+10) >> (30-14*2)) & 0x3) << bit2; 
-			if(new == 0xa && old == 0xf)
-				ptr[offset] |= ((*(p+count+10) >> (30-15*2)) & 0x3) << bit2; 
-
-			if(new == 0xb && old == 0)
-				ptr[offset] |= ((*(p+count+11) >> (30-0*2)) & 0x3) << bit2; 
-			if(new == 0xb && old == 0x1)
-				ptr[offset] |= ((*(p+count+11) >> (30-1*2)) & 0x3) << bit2; 
-			if(new == 0xb && old == 0x2)
-				ptr[offset] |= ((*(p+count+11) >> (30-2*2)) & 0x3) << bit2; 
-			if(new == 0xb && old == 0x3)
-				ptr[offset] |= ((*(p+count+11) >> (30-3*2)) & 0x3) << bit2; 
-			if(new == 0xb && old == 0x4)
-				ptr[offset] |= ((*(p+count+11) >> (30-4*2)) & 0x3) << bit2; 
-			if(new == 0xb && old == 0x5)
-				ptr[offset] |= ((*(p+count+11) >> (30-5*2)) & 0x3) << bit2; 
-			if(new == 0xb && old == 0x6)
-				ptr[offset] |= ((*(p+count+11) >> (30-6*2)) & 0x3) << bit2; 
-			if(new == 0xb && old == 0x7)
-				ptr[offset] |= ((*(p+count+11) >> (30-7*2)) & 0x3) << bit2; 
-			if(new == 0xb && old == 0x8)
-				ptr[offset] |= ((*(p+count+11) >> (30-8*2)) & 0x3) << bit2; 
-			if(new == 0xb && old == 0x9)
-				ptr[offset] |= ((*(p+count+11) >> (30-9*2)) & 0x3) << bit2; 
-			if(new == 0xb && old == 0xa)
-				ptr[offset] |= ((*(p+count+11) >> (30-10*2)) & 0x3) << bit2; 
-			if(new == 0xb && old == 0xb)
-				ptr[offset] |= ((*(p+count+11) >> (30-11*2)) & 0x3) << bit2; 
-			if(new == 0xb && old == 0xc)
-				ptr[offset] |= ((*(p+count+11) >> (30-12*2)) & 0x3) << bit2; 
-			if(new == 0xb && old == 0xd)
-				ptr[offset] |= ((*(p+count+11) >> (30-13*2)) & 0x3) << bit2; 
-			if(new == 0xb && old == 0xe)
-				ptr[offset] |= ((*(p+count+11) >> (30-14*2)) & 0x3) << bit2; 
-			if(new == 0xb && old == 0xf)
-				ptr[offset] |= ((*(p+count+11) >> (30-15*2)) & 0x3) << bit2; 
-
-			if(new == 0xc && old == 0)
-				ptr[offset] |= ((*(p+count+12) >> (30-0*2)) & 0x3) << bit2; 
-			if(new == 0xc && old == 0x1)
-				ptr[offset] |= ((*(p+count+12) >> (30-1*2)) & 0x3) << bit2; 
-			if(new == 0xc && old == 0x2)
-				ptr[offset] |= ((*(p+count+12) >> (30-2*2)) & 0x3) << bit2; 
-			if(new == 0xc && old == 0x3)
-				ptr[offset] |= ((*(p+count+12) >> (30-3*2)) & 0x3) << bit2; 
-			if(new == 0xc && old == 0x4)
-				ptr[offset] |= ((*(p+count+12) >> (30-4*2)) & 0x3) << bit2; 
-			if(new == 0xc && old == 0x5)
-				ptr[offset] |= ((*(p+count+12) >> (30-5*2)) & 0x3) << bit2; 
-			if(new == 0xc && old == 0x6)
-				ptr[offset] |= ((*(p+count+12) >> (30-6*2)) & 0x3) << bit2; 
-			if(new == 0xc && old == 0x7)
-				ptr[offset] |= ((*(p+count+12) >> (30-7*2)) & 0x3) << bit2; 
-			if(new == 0xc && old == 0x8)
-				ptr[offset] |= ((*(p+count+12) >> (30-8*2)) & 0x3) << bit2; 
-			if(new == 0xc && old == 0x9)
-				ptr[offset] |= ((*(p+count+12) >> (30-9*2)) & 0x3) << bit2; 
-			if(new == 0xc && old == 0xa)
-				ptr[offset] |= ((*(p+count+12) >> (30-10*2)) & 0x3) << bit2; 
-			if(new == 0xc && old == 0xb)
-				ptr[offset] |= ((*(p+count+12) >> (30-11*2)) & 0x3) << bit2; 
-			if(new == 0xc && old == 0xc)
-				ptr[offset] |= ((*(p+count+12) >> (30-12*2)) & 0x3) << bit2; 
-			if(new == 0xc && old == 0xd)
-				ptr[offset] |= ((*(p+count+12) >> (30-13*2)) & 0x3) << bit2; 
-			if(new == 0xc && old == 0xe)
-				ptr[offset] |= ((*(p+count+12) >> (30-14*2)) & 0x3) << bit2; 
-			if(new == 0xc && old == 0xf)
-				ptr[offset] |= ((*(p+count+12) >> (30-15*2)) & 0x3) << bit2; 
-
-			if(new == 0xd && old == 0)
-				ptr[offset] |= ((*(p+count+13) >> (30-0*2)) & 0x3) << bit2; 
-			if(new == 0xd && old == 0x1)
-				ptr[offset] |= ((*(p+count+13) >> (30-1*2)) & 0x3) << bit2; 
-			if(new == 0xd && old == 0x2)
-				ptr[offset] |= ((*(p+count+13) >> (30-2*2)) & 0x3) << bit2; 
-			if(new == 0xd && old == 0x3)
-				ptr[offset] |= ((*(p+count+13) >> (30-3*2)) & 0x3) << bit2; 
-			if(new == 0xd && old == 0x4)
-				ptr[offset] |= ((*(p+count+13) >> (30-4*2)) & 0x3) << bit2; 
-			if(new == 0xd && old == 0x5)
-				ptr[offset] |= ((*(p+count+13) >> (30-5*2)) & 0x3) << bit2; 
-			if(new == 0xd && old == 0x6)
-				ptr[offset] |= ((*(p+count+13) >> (30-6*2)) & 0x3) << bit2; 
-			if(new == 0xd && old == 0x7)
-				ptr[offset] |= ((*(p+count+13) >> (30-7*2)) & 0x3) << bit2; 
-			if(new == 0xd && old == 0x8)
-				ptr[offset] |= ((*(p+count+13) >> (30-8*2)) & 0x3) << bit2; 
-			if(new == 0xd && old == 0x9)
-				ptr[offset] |= ((*(p+count+13) >> (30-9*2)) & 0x3) << bit2; 
-			if(new == 0xd && old == 0xa)
-				ptr[offset] |= ((*(p+count+13) >> (30-10*2)) & 0x3) << bit2; 
-			if(new == 0xd && old == 0xb)
-				ptr[offset] |= ((*(p+count+13) >> (30-11*2)) & 0x3) << bit2; 
-			if(new == 0xd && old == 0xc)
-				ptr[offset] |= ((*(p+count+13) >> (30-12*2)) & 0x3) << bit2; 
-			if(new == 0xd && old == 0xd)
-				ptr[offset] |= ((*(p+count+13) >> (30-13*2)) & 0x3) << bit2; 
-			if(new == 0xd && old == 0xe)
-				ptr[offset] |= ((*(p+count+13) >> (30-14*2)) & 0x3) << bit2; 
-			if(new == 0xd && old == 0xf)
-				ptr[offset] |= ((*(p+count+13) >> (30-15*2)) & 0x3) << bit2; 
-
-			if(new == 0xe && old == 0)
-				ptr[offset] |= ((*(p+count+14) >> (30-0*2)) & 0x3) << bit2; 
-			if(new == 0xe && old == 0x1)
-				ptr[offset] |= ((*(p+count+14) >> (30-1*2)) & 0x3) << bit2; 
-			if(new == 0xe && old == 0x2)
-				ptr[offset] |= ((*(p+count+14) >> (30-2*2)) & 0x3) << bit2; 
-			if(new == 0xe && old == 0x3)
-				ptr[offset] |= ((*(p+count+14) >> (30-3*2)) & 0x3) << bit2; 
-			if(new == 0xe && old == 0x4)
-				ptr[offset] |= ((*(p+count+14) >> (30-4*2)) & 0x3) << bit2; 
-			if(new == 0xe && old == 0x5)
-				ptr[offset] |= ((*(p+count+14) >> (30-5*2)) & 0x3) << bit2; 
-			if(new == 0xe && old == 0x6)
-				ptr[offset] |= ((*(p+count+14) >> (30-6*2)) & 0x3) << bit2; 
-			if(new == 0xe && old == 0x7)
-				ptr[offset] |= ((*(p+count+14) >> (30-7*2)) & 0x3) << bit2; 
-			if(new == 0xe && old == 0x8)
-				ptr[offset] |= ((*(p+count+14) >> (30-8*2)) & 0x3) << bit2; 
-			if(new == 0xe && old == 0x9)
-				ptr[offset] |= ((*(p+count+14) >> (30-9*2)) & 0x3) << bit2; 
-			if(new == 0xe && old == 0xa)
-				ptr[offset] |= ((*(p+count+14) >> (30-10*2)) & 0x3) << bit2; 
-			if(new == 0xe && old == 0xb)
-				ptr[offset] |= ((*(p+count+14) >> (30-11*2)) & 0x3) << bit2; 
-			if(new == 0xe && old == 0xc)
-				ptr[offset] |= ((*(p+count+14) >> (30-12*2)) & 0x3) << bit2; 
-			if(new == 0xe && old == 0xd)
-				ptr[offset] |= ((*(p+count+14) >> (30-13*2)) & 0x3) << bit2; 
-			if(new == 0xe && old == 0xe)
-				ptr[offset] |= ((*(p+count+14) >> (30-14*2)) & 0x3) << bit2; 
-			if(new == 0xe && old == 0xf)
-				ptr[offset] |= ((*(p+count+14) >> (30-15*2)) & 0x3) << bit2; 
-
-			if(new == 0xf && old == 0)
-				ptr[offset] |= ((*(p+count+15) >> (30-0*2)) & 0x3) << bit2; 
-			if(new == 0xf && old == 0x1)
-				ptr[offset] |= ((*(p+count+15) >> (30-1*2)) & 0x3) << bit2; 
-			if(new == 0xf && old == 0x2)
-				ptr[offset] |= ((*(p+count+15) >> (30-2*2)) & 0x3) << bit2; 
-			if(new == 0xf && old == 0x3)
-				ptr[offset] |= ((*(p+count+15) >> (30-3*2)) & 0x3) << bit2; 
-			if(new == 0xf && old == 0x4)
-				ptr[offset] |= ((*(p+count+15) >> (30-4*2)) & 0x3) << bit2; 
-			if(new == 0xf && old == 0x5)
-				ptr[offset] |= ((*(p+count+15) >> (30-5*2)) & 0x3) << bit2; 
-			if(new == 0xf && old == 0x6)
-				ptr[offset] |= ((*(p+count+15) >> (30-6*2)) & 0x3) << bit2; 
-			if(new == 0xf && old == 0x7)
-				ptr[offset] |= ((*(p+count+15) >> (30-7*2)) & 0x3) << bit2; 
-			if(new == 0xf && old == 0x8)
-				ptr[offset] |= ((*(p+count+15) >> (30-8*2)) & 0x3) << bit2; 
-			if(new == 0xf && old == 0x9)
-				ptr[offset] |= ((*(p+count+15) >> (30-9*2)) & 0x3) << bit2; 
-			if(new == 0xf && old == 0xa)
-				ptr[offset] |= ((*(p+count+15) >> (30-10*2)) & 0x3) << bit2; 
-			if(new == 0xf && old == 0xb)
-				ptr[offset] |= ((*(p+count+15) >> (30-11*2)) & 0x3) << bit2; 
-			if(new == 0xf && old == 0xc)
-				ptr[offset] |= ((*(p+count+15) >> (30-12*2)) & 0x3) << bit2; 
-			if(new == 0xf && old == 0xd)
-				ptr[offset] |= ((*(p+count+15) >> (30-13*2)) & 0x3) << bit2; 
-			if(new == 0xf && old == 0xe)
-				ptr[offset] |= ((*(p+count+15) >> (30-14*2)) & 0x3) << bit2; 
-			if(new == 0xf && old == 0xf)
-				ptr[offset] |= ((*(p+count+15) >> (30-15*2)) & 0x3) << bit2; 
-
-		}
-	}
-
-
-}
-
-
-void fill_8level_gray(int max_frm,unsigned int *p)
-{
-	int i,j,old,new,offset, bit2;
-	int index_per_frame = (1 << 8);
-	int count; // count is offset of array
-	unsigned int *ptr = (unsigned int *)lcd_palette; 
-	memset(lcd_palette, 0x0, 4096);
-
-	// record the totally multiple of 16frames
-	if( max_frm%16 != 0)
-		totally_time = (1+max_frm/16);
-	else
-		totally_time = max_frm/16;
-	
-	for (j = 0; j < max_frm; j++) {	
-		count = 4*j;
-		for(i=0;i<index_per_frame;i++){
-			old = (i >> 4) & 0xf;
-			new = i & 0xf;
-			offset = (j * index_per_frame + i)*2/32; 
-			bit2 = ((j * index_per_frame + i)%16)*2;
-			
-			if(new == 0 && old == 0)
-				ptr[offset] |= ((*(p+count) >> (30-0*2)) & 0x3) << bit2; 
-			if(new == 0 && old == 0x2)
-				ptr[offset] |= ((*(p+count) >> (30-1*2)) & 0x3) << bit2; 
-			if(new == 0 && old == 0x5)
-				ptr[offset] |= ((*(p+count) >> (30-2*2)) & 0x3) << bit2; 
-			if(new == 0 && old == 0x7)
-				ptr[offset] |= ((*(p+count) >> (30-3*2)) & 0x3) << bit2; 
-			if(new == 0 && old == 0x8)
-				ptr[offset] |= ((*(p+count) >> (30-4*2)) & 0x3) << bit2; 
-			if(new == 0 && old == 0xa)
-				ptr[offset] |= ((*(p+count) >> (30-5*2)) & 0x3) << bit2; 
-			if(new == 0 && old == 0xc)
-				ptr[offset] |= ((*(p+count) >> (30-6*2)) & 0x3) << bit2; 
-			if(new == 0 && old == 0xf)
-				ptr[offset] |= ((*(p+count) >> (30-7*2)) & 0x3) << bit2; 
-			
-			if(new == 0x2 && old == 0)
-				ptr[offset] |= ((*(p+count) >> (30-8*2)) & 0x3) << bit2; 
-			if(new == 0x2 && old == 0x2)
-				ptr[offset] |= ((*(p+count) >> (30-9*2)) & 0x3) << bit2; 
-			if(new == 0x2 && old == 0x5)
-				ptr[offset] |= ((*(p+count) >> (30-10*2)) & 0x3) << bit2; 
-			if(new == 0x2 && old == 0x7)
-				ptr[offset] |= ((*(p+count) >> (30-11*2)) & 0x3) << bit2; 
-			if(new == 0x2 && old == 0x8)
-				ptr[offset] |= ((*(p+count) >> (30-12*2)) & 0x3) << bit2; 
-			if(new == 0x2 && old == 0xa)
-				ptr[offset] |= ((*(p+count) >> (30-13*2)) & 0x3) << bit2; 
-			if(new == 0x2 && old == 0xc)
-				ptr[offset] |= ((*(p+count) >> (30-14*2)) & 0x3) << bit2; 
-			if(new == 0x2 && old == 0xf)
-				ptr[offset] |= ((*(p+count) >> (30-15*2)) & 0x3) << bit2; 
-			
-		
-			if(new == 0x5 && old == 0)
-				ptr[offset] |= ((*(p+count+1) >> (30-0*2)) & 0x3) << bit2; 
-			if(new == 0x5 && old == 0x2)
-				ptr[offset] |= ((*(p+count+1) >> (30-1*2)) & 0x3) << bit2; 
-			if(new == 0x5 && old == 0x5)
-				ptr[offset] |= ((*(p+count+1) >> (30-2*2)) & 0x3) << bit2; 
-			if(new == 0x5 && old == 0x7)
-				ptr[offset] |= ((*(p+count+1) >> (30-3*2)) & 0x3) << bit2; 
-			if(new == 0x5 && old == 0x8)
-				ptr[offset] |= ((*(p+count+1) >> (30-4*2)) & 0x3) << bit2; 
-			if(new == 0x5 && old == 0xa)
-				ptr[offset] |= ((*(p+count+1) >> (30-5*2)) & 0x3) << bit2; 
-			if(new == 0x5 && old == 0xc)
-				ptr[offset] |= ((*(p+count+1) >> (30-6*2)) & 0x3) << bit2; 
-			if(new == 0x5 && old == 0xf)
-				ptr[offset] |= ((*(p+count+1) >> (30-7*2)) & 0x3) << bit2; 
-					
-			if(new == 0x7 && old == 0)
-				ptr[offset] |= ((*(p+count+1) >> (30-8*2)) & 0x3) << bit2; 
-			if(new == 0x7 && old == 0x2)
-				ptr[offset] |= ((*(p+count+1) >> (30-9*2)) & 0x3) << bit2; 
-			if(new == 0x7 && old == 0x5)
-				ptr[offset] |= ((*(p+count+1) >> (30-10*2)) & 0x3) << bit2; 
-			if(new == 0x7 && old == 0x7)
-				ptr[offset] |= ((*(p+count+1) >> (30-11*2)) & 0x3) << bit2; 
-			if(new == 0x7 && old == 0x8)
-				ptr[offset] |= ((*(p+count+1) >> (30-12*2)) & 0x3) << bit2; 
-			if(new == 0x7 && old == 0xa)
-				ptr[offset] |= ((*(p+count+1) >> (30-13*2)) & 0x3) << bit2; 
-			if(new == 0x7 && old == 0xc)
-				ptr[offset] |= ((*(p+count+1) >> (30-14*2)) & 0x3) << bit2; 
-			if(new == 0x7 && old == 0xf)
-				ptr[offset] |= ((*(p+count+1) >> (30-15*2)) & 0x3) << bit2; 
-			
-			
-			if(new == 0x8 && old == 0)
-				ptr[offset] |= ((*(p+count+2) >> (30-0*2)) & 0x3) << bit2; 
-			if(new == 0x8 && old == 0x2)
-				ptr[offset] |= ((*(p+count+2) >> (30-1*2)) & 0x3) << bit2; 
-			if(new == 0x8 && old == 0x5)
-				ptr[offset] |= ((*(p+count+2) >> (30-2*2)) & 0x3) << bit2; 
-			if(new == 0x8 && old == 0x7)
-				ptr[offset] |= ((*(p+count+2) >> (30-3*2)) & 0x3) << bit2; 
-			if(new == 0x8 && old == 0x8)
-				ptr[offset] |= ((*(p+count+2) >> (30-4*2)) & 0x3) << bit2; 
-			if(new == 0x8 && old == 0xa)
-				ptr[offset] |= ((*(p+count+2) >> (30-5*2)) & 0x3) << bit2; 
-			if(new == 0x8 && old == 0xc)
-				ptr[offset] |= ((*(p+count+2) >> (30-6*2)) & 0x3) << bit2; 
-			if(new == 0x8 && old == 0xf)
-				ptr[offset] |= ((*(p+count+2) >> (30-7*2)) & 0x3) << bit2; 
-			
-			if(new == 0xa && old == 0)
-				ptr[offset] |= ((*(p+count+2) >> (30-8*2)) & 0x3) << bit2; 
-			if(new == 0xa && old == 0x2)
-				ptr[offset] |= ((*(p+count+2) >> (30-9*2)) & 0x3) << bit2; 
-			if(new == 0xa && old == 0x5)
-				ptr[offset] |= ((*(p+count+2) >> (30-10*2)) & 0x3) << bit2; 
-			if(new == 0xa && old == 0x7)
-				ptr[offset] |= ((*(p+count+2) >> (30-11*2)) & 0x3) << bit2; 
-			if(new == 0xa && old == 0x8)
-				ptr[offset] |= ((*(p+count+2) >> (30-12*2)) & 0x3) << bit2; 
-			if(new == 0xa && old == 0xa)
-				ptr[offset] |= ((*(p+count+2) >> (30-13*2)) & 0x3) << bit2; 
-			if(new == 0xa && old == 0xc)
-				ptr[offset] |= ((*(p+count+2) >> (30-14*2)) & 0x3) << bit2; 
-			if(new == 0xa && old == 0xf)
-				ptr[offset] |= ((*(p+count+2) >> (30-15*2)) & 0x3) << bit2; 
-			
-		
-			if(new == 0xc && old == 0)
-				ptr[offset] |= ((*(p+count+3) >> (30-0*2)) & 0x3) << bit2; 
-			if(new == 0xc && old == 0x2)
-				ptr[offset] |= ((*(p+count+3) >> (30-1*2)) & 0x3) << bit2; 
-			if(new == 0xc && old == 0x5)
-				ptr[offset] |= ((*(p+count+3) >> (30-2*2)) & 0x3) << bit2; 
-			if(new == 0xc && old == 0x7)
-				ptr[offset] |= ((*(p+count+3) >> (30-3*2)) & 0x3) << bit2; 
-			if(new == 0xc && old == 0x8)
-				ptr[offset] |= ((*(p+count+3) >> (30-4*2)) & 0x3) << bit2; 
-			if(new == 0xc && old == 0xa)
-				ptr[offset] |= ((*(p+count+3) >> (30-5*2)) & 0x3) << bit2; 
-			if(new == 0xc && old == 0xc)
-				ptr[offset] |= ((*(p+count+3) >> (30-6*2)) & 0x3) << bit2; 
-			if(new == 0xc && old == 0xf)
-				ptr[offset] |= ((*(p+count+3) >> (30-7*2)) & 0x3) << bit2; 
-			
-			if(new == 0xf && old == 0)
-				ptr[offset] |= ((*(p+count+3) >> (30-8*2)) & 0x3) << bit2; 
-			if(new == 0xf && old == 0x2)
-				ptr[offset] |= ((*(p+count+3) >> (30-9*2)) & 0x3) << bit2; 
-			if(new == 0xf && old == 0x5)
-				ptr[offset] |= ((*(p+count+3) >> (30-10*2)) & 0x3) << bit2; 
-			if(new == 0xf && old == 0x7)
-				ptr[offset] |= ((*(p+count+3) >> (30-11*2)) & 0x3) << bit2; 
-			if(new == 0xf && old == 0x8)
-				ptr[offset] |= ((*(p+count+3) >> (30-12*2)) & 0x3) << bit2; 
-			if(new == 0xf && old == 0xa)
-				ptr[offset] |= ((*(p+count+3) >> (30-13*2)) & 0x3) << bit2; 
-			if(new == 0xf && old == 0xc)
-				ptr[offset] |= ((*(p+count+3) >> (30-14*2)) & 0x3) << bit2; 
-			if(new == 0xf && old == 0xf)
-				ptr[offset] |= ((*(p+count+3) >> (30-15*2)) & 0x3) << bit2; 
-
-		
-			
-		}
-	}
-
-
-}
-
-void fill_4level_gray(int max_frm,unsigned int *p)
-{
-
-	int i,j,old,new,offset, bit2;
-	int index_per_frame = (1 << 8);
-	int count; // count is offset of array
-	unsigned int *ptr = (unsigned int *)lcd_palette; 
-	memset(lcd_palette, 0x0, 4096);
-	// record the totally multiple of 16frames
-
-	if( max_frm%16 != 0)
-		totally_time = (1+max_frm/16);
-	else
-		totally_time = max_frm/16;
-
-
-	for (j = 0; j < max_frm; j++) {	
-		count = j;
-		for(i=0;i<index_per_frame;i++){
-			old = (i >> 4) & 0xf;
-			new = i & 0xf;
-			offset = (j * index_per_frame + i)*2/32; 
-			bit2 = ((j * index_per_frame + i)%16)*2;
-			
-			if(new == 0 && old == 0)
-				ptr[offset] |= ((*(p+count) >> (30-0*2)) & 0x3) << bit2; 
-			if(new == 0 && old == 0x5)
-				ptr[offset] |= ((*(p+count) >> (30-1*2)) & 0x3) << bit2; 
-			if(new == 0 && old == 0xa)
-				ptr[offset] |= ((*(p+count) >> (30-2*2)) & 0x3) << bit2; 
-			if(new == 0 && old == 0xf)
-				ptr[offset] |= ((*(p+count) >> (30-3*2)) & 0x3) << bit2; 
-			
-			if(new == 0x5 && old == 0x0)
-				ptr[offset] |= ((*(p+count) >> (30-4*2)) & 0x3) << bit2; 
-			if(new == 0x5 && old == 0x5)
-				ptr[offset] |= ((*(p+count) >> (30-5*2)) & 0x3) << bit2; 
-			if(new == 0x5 && old == 0xa)
-				ptr[offset] |= ((*(p+count) >> (30-6*2)) & 0x3) << bit2; 
-			if(new == 0x5 && old == 0xf)
-				ptr[offset] |= ((*(p+count) >> (30-7*2)) & 0x3) << bit2; 
-			
-			
-			if(new == 0xa && old == 0x0)
-				ptr[offset] |= ((*(p+count) >> (30-8*2)) & 0x3) << bit2; 
-			if(new == 0xa && old == 0x5)
-				ptr[offset] |= ((*(p+count) >> (30-9*2)) & 0x3) << bit2; 
-			if(new == 0xa && old == 0xa)
-				ptr[offset] |= ((*(p+count) >> (30-10*2)) & 0x3) << bit2; 
-			if(new == 0xa && old == 0xf)
-				ptr[offset] |= ((*(p+count) >> (30-11*2)) & 0x3) << bit2; 
-			
-			
-			if(new == 0xf && old == 0x0)
-				ptr[offset] |= ((*(p+count) >> (30-12*2)) & 0x3) << bit2; 
-			if(new == 0xf && old == 0x5)
-				ptr[offset] |= ((*(p+count) >> (30-13*2)) & 0x3) << bit2; 
-			if(new == 0xf && old == 0xa)
-				ptr[offset] |= ((*(p+count) >> (30-14*2)) & 0x3) << bit2; 
-			if(new == 0xf && old == 0xf)
-				ptr[offset] |= ((*(p+count) >> (30-15*2)) & 0x3) << bit2; 
-		}
-	}
-
-}
-
-
-
-void fill_gu_palette(void)
-{
-
-	int max_frm ;
-	unsigned int *p;
-
-	get_temp();
-	D("%s:  temp(%d) gray level=%d. \n",__func__,epd_temp_level,epd_gray_level);
-
-	if(epd_gray_level == GRAY_LEVEL_4)
-	{
-		if (epd_temp_level ==  TEMP_LOW_LEVEL)
-		{
-		
-			max_frm = 48;
-			p =  (unsigned int *)&waveform_temp0_gu; // give waveform_temp2_Du to p
-		
-			
-		}
-		else if (epd_temp_level ==  TEMP_HIGH_LEVEL)
-		{
-		
-			max_frm = 48;
-			p =  (unsigned int *)&waveform_temp1_gu; // give waveform_temp2_Du to p	
-		
-		}
-		else if (epd_temp_level ==  TEMP_HIGHER_LEVEL)
-		{	
-		
-			max_frm = 48;
-			p =  (unsigned int *)&waveform_temp2_gu; // give waveform_temp2_Du to p	
-		
-		}
-		
-		else if (epd_temp_level ==  TEMP_HIGHEST_LEVEL)
-		{
-		
-			max_frm = 42;
-			p =  (unsigned int *)&waveform_temp3_gu; 
-			
-		}
-		else{
-			printk("Invalid temperature level. \n");
-			return;	
-		}
-	
-		fill_4level_gray(max_frm,p);
-	}
-
-	if(epd_gray_level == GRAY_LEVEL_8)
-	{
-	
-
-		if (epd_temp_level ==  TEMP_LOW_LEVEL)
-		{
-		
-			max_frm = 48;
-			p =  (unsigned int *)&waveform8_temp0_gu; // give waveform_temp2_Du to p
-		
-			
-		}
-		else if (epd_temp_level ==  TEMP_HIGH_LEVEL)
-		{
-		
-			max_frm = 48;
-			p =  (unsigned int *)&waveform8_temp1_gu; // give waveform_temp2_Du to p
-			
-		}
-		else if (epd_temp_level ==  TEMP_HIGHER_LEVEL)
-		{	
-		
-			max_frm = 48;
-			p =  (unsigned int *)&waveform8_temp2_gu; // give waveform_temp2_Du to p			
-			
-		}
-		
-		else if (epd_temp_level ==  TEMP_HIGHEST_LEVEL)
-		{
-		
-			max_frm = 42;
-			p =  (unsigned int *)&waveform8_temp3_gu; 
-		}
-		else{
-			printk("Invalid temperature level. \n");
-			return;	
-		}
-		
-		fill_8level_gray(max_frm,p);
-	}
-	if(epd_gray_level == GRAY_LEVEL_16)
-       	{
-		// add 16level gray support
-
-		if (epd_temp_level ==  TEMP_LOW_LEVEL)
-		{
-		
-			max_frm = 48;
-			p =  (unsigned int *)&waveform16_temp0_gu; // give waveform_temp2_Du to p
-		
-			
-		}
-		else if (epd_temp_level ==  TEMP_HIGH_LEVEL)
-		{
-		
-			max_frm = 48;
-			p =  (unsigned int *)&waveform16_temp1_gu; // give waveform_temp2_Du to p
-			
-		}
-		else if (epd_temp_level ==  TEMP_HIGHER_LEVEL)
-		{	
-		
-			max_frm = 48;
-			p =  (unsigned int *)&waveform16_temp2_gu; // give waveform_temp2_Du to p			
-			
-		}
-		
-		else if (epd_temp_level ==  TEMP_HIGHEST_LEVEL)
-		{
-		
-			max_frm = 42;
-			p =  (unsigned int *)&waveform16_temp3_gu; 
-		}
-		else{
-			printk("Invalid temperature level. \n");
-			return;	
-		}
-		
-		fill_16level_gray(max_frm,p);
-
-	}
-	dma_cache_wback((unsigned int)(lcd_palette), 4096);
-//	printpalette((unsigned short *)((unsigned int)lcd_palette | 0xa0000000), 2048);
-		
-}
-void fill_gc_palette(void)
-{
-
-	int max_frm ;
-	unsigned int *p;
-
-	get_temp();
-	D("%s:  temp%d gray level=%d. \n",__func__,epd_temp_level,epd_gray_level);
-
-	if(epd_gray_level == GRAY_LEVEL_4)
-	{
-		if (epd_temp_level ==  TEMP_LOW_LEVEL)
-		{
-		
-			max_frm = 48;
-			p =  (unsigned int *)&waveform_temp0_gc; // give waveform_temp2_Du to p
-		
-			
-		}
-		else if (epd_temp_level ==  TEMP_HIGH_LEVEL)
-		{
-		
-			max_frm = 48;
-			p =  (unsigned int *)&waveform_temp1_gc; // give waveform_temp2_Du to p	
-		
-		}
-		else if (epd_temp_level ==  TEMP_HIGHER_LEVEL)
-		{	
-		
-			max_frm = 48;
-			p =  (unsigned int *)&waveform_temp2_gc; // give waveform_temp2_Du to p	
-		
-		}
-		
-		else if (epd_temp_level ==  TEMP_HIGHEST_LEVEL)
-		{
-		
-			max_frm = 42;
-			p =  (unsigned int *)&waveform_temp3_gc; 
-			
-
-		}
-		else{
-			printk("Invalid temperature level. \n");
-			return;	
-		}
-	
-		fill_4level_gray(max_frm,p);
-	}
-
-	if(epd_gray_level == GRAY_LEVEL_8)
-	{
-	
-		if (epd_temp_level ==  TEMP_LOW_LEVEL)
-		{
-		
-			max_frm = 48;
-			p =  (unsigned int *)&waveform8_temp0_gc; // give waveform_temp2_Du to p
-		
-			
-		}
-		else if (epd_temp_level ==  TEMP_HIGH_LEVEL)
-		{
-		
-			max_frm = 48;
-			p =  (unsigned int *)&waveform8_temp1_gc; // give waveform_temp2_Du to p
-			
-		}
-		else if (epd_temp_level ==  TEMP_HIGHER_LEVEL)
-		{	
-		
-			max_frm = 48;
-			p =  (unsigned int *)&waveform8_temp2_gc; // give waveform_temp2_Du to p			
-			
-		}
-		
-		else if (epd_temp_level ==  TEMP_HIGHEST_LEVEL)
-		{
-		
-			max_frm = 42;
-			p =  (unsigned int *)&waveform8_temp3_gc; 
-		}
-		else{
-			printk("Invalid temperature level. \n");
-			return;	
-		}
-		
-		fill_8level_gray(max_frm,p);
-	}
-	if(epd_gray_level == GRAY_LEVEL_16)
-	{
-		// add 16level gray support
-
-		if (epd_temp_level ==  TEMP_LOW_LEVEL)
-		{
-		
-			max_frm = 48;
-			p =  (unsigned int *)&waveform16_temp0_gc; // give waveform_temp2_Du to p
-		
-			
-		}
-		else if (epd_temp_level ==  TEMP_HIGH_LEVEL)
-		{
-		
-			max_frm = 48;
-			p =  (unsigned int *)&waveform16_temp1_gc; // give waveform_temp2_Du to p
-			
-		}
-		else if (epd_temp_level ==  TEMP_HIGHER_LEVEL)
-		{	
-		
-			max_frm = 48;
-			p =  (unsigned int *)&waveform16_temp2_gc; // give waveform_temp2_Du to p			
-			
-		}
-		
-		else if (epd_temp_level ==  TEMP_HIGHEST_LEVEL)
-		{
-		
-			max_frm = 42;
-			p =  (unsigned int *)&waveform16_temp3_gc; 
-		}
-		else{
-			printk("Invalid temperature level. \n");
-			return;	
-		}
-		
-		fill_16level_gray(max_frm,p);
-
-	}
-	dma_cache_wback((unsigned int)(lcd_palette), 4096);
-//	printpalette((unsigned short *)((unsigned int)lcd_palette | 0xa0000000), 2048);
-	
-	
-}
-
-void handwriting_palette(void)
-{
-
-	int max_frm ;
-	unsigned int *p;
-	D("%s:  temp(%d) gray level=%d. \n",__func__,epd_temp_level,epd_gray_level);
-	max_frm = 2;
-	p =  (unsigned int *)&waveform_handwriting; 
-	fill_du_4level_gray(max_frm,p);
-	dma_cache_wback((unsigned int)(lcd_palette), 4096);
-//	printpalette((unsigned short *)((unsigned int)lcd_palette | 0xa0000000), 64);
-
-}
-
-int set_epd_mod(unsigned long arg)
-{
-
-	epd_mod_level  = *(unsigned long *)arg;
-	
-	if (epd_mod_level == EPD_MOD_INIT )
-		fill_init_palette();
-	else if (epd_mod_level == EPD_MOD_DU )
-		fill_du_palette();
-	else if (epd_mod_level == EPD_MOD_GU )
-		fill_gu_palette();
-	else if (epd_mod_level == EPD_MOD_GC )
-		fill_gc_palette();
-	else 
-		return MOD_INVALID;
-	return EPD_SUCCESS;
-
-	
-}
diff --git a/fs/sync.c b/fs/sync.c
index 86dc6378876..c894aba807b 100644
--- a/fs/sync.c
+++ b/fs/sync.c
@@ -17,11 +17,11 @@
 
 #define VALID_FLAGS (SYNC_FILE_RANGE_WAIT_BEFORE|SYNC_FILE_RANGE_WRITE| \
 			SYNC_FILE_RANGE_WAIT_AFTER)
-
+#if defined(CONFIG_MTD_BLOCK)
 static struct mtdblk_dev *g_udc_mtdblk;
 extern struct mtdblk_dev *udc_get_mtdblk(void);
 extern void udc_flush_cache(struct mtdblk_dev *mtdblk);
-
+#endif
 /*
  * Do the filesystem syncing work. For simple filesystems sync_inodes_sb(sb, 0)
  * just dirties buffers with inodes so we have to submit IO for these buffers
@@ -116,9 +116,11 @@ restart:
 	}
 	spin_unlock(&sb_lock);
 	mutex_unlock(&mutex);
-	
+#if defined(CONFIG_MTD_BLOCK)	
 	g_udc_mtdblk = udc_get_mtdblk();
-	udc_flush_cache(g_udc_mtdblk);
+	if(g_udc_mtdblk)
+		udc_flush_cache(g_udc_mtdblk);
+#endif
 }
 
 /*
diff --git a/fs/yaffs2/utils/Makefile b/fs/yaffs2/utils/Makefile
index ba8c0e55009..3bbe7831a92 100644
--- a/fs/yaffs2/utils/Makefile
+++ b/fs/yaffs2/utils/Makefile
@@ -51,15 +51,17 @@ MKYAFFSSOURCES = mkyaffsimage.c
 MKYAFFSIMAGEOBJS = $(MKYAFFSSOURCES:.c=.o)
 
 MKYAFFS2SOURCES = mkyaffs2image.c
+MKYAFFS2SOURCES4760x = mkyaffs2image4760x.c
 MKYAFFS2LINKS = yaffs_packedtags2.c yaffs_tagsvalidity.c
 MKYAFFS2IMAGEOBJS = $(MKYAFFS2SOURCES:.c=.o) $(MKYAFFS2LINKS:.c=.o)
+MKYAFFS2IMAGEOBJS4760x = $(MKYAFFS2SOURCES4760x:.c=.o) $(MKYAFFS2LINKS:.c=.o)
 
-all: mkyaffsimage mkyaffs2image
+all: mkyaffsimage mkyaffs2image mkyaffs2image4760x
 
 $(COMMONLINKS) $(MKYAFFSLINKS) $(MKYAFFS2LINKS):
 	ln -s ../$@ $@
 
-$(COMMONOBJS) $(MKYAFFSIMAGEOBJS) $(MKYAFFS2IMAGEOBJS) : %.o: %.c
+$(COMMONOBJS) $(MKYAFFSIMAGEOBJS) $(MKYAFFS2IMAGEOBJS) $(MKYAFFS2IMAGEOBJS4760x): %.o: %.c
 	$(CC) -c $(CFLAGS) $< -o $@
 
 mkyaffsimage: $(COMMONOBJS) $(MKYAFFSIMAGEOBJS)
@@ -68,6 +70,8 @@ mkyaffsimage: $(COMMONOBJS) $(MKYAFFSIMAGEOBJS)
 mkyaffs2image: $(COMMONOBJS) $(MKYAFFS2IMAGEOBJS)
 	$(CC) -o $@ $(COMMONOBJS) $(MKYAFFS2IMAGEOBJS)
 
+mkyaffs2image4760x: $(COMMONOBJS) $(MKYAFFS2IMAGEOBJS4760x)
+	$(CC) -o $@ $(COMMONOBJS) $(MKYAFFS2IMAGEOBJS4760x)
 
 clean:
-	rm -f $(COMMONOBJS) $(MKYAFFSIMAGEOBJS) $(MKYAFFS2IMAGEOBJS) $(COMMONLINKS) $(MKYAFFSLINKS) $(MKYAFFS2LINKS) mkyaffsimage mkyaffs2image core
+	rm -f $(COMMONOBJS) $(MKYAFFSIMAGEOBJS) $(MKYAFFS2IMAGEOBJS) $(MKYAFFS2IMAGEOBJS4760x) $(COMMONLINKS) $(MKYAFFSLINKS) $(MKYAFFS2LINKS) mkyaffsimage mkyaffs2image mkyaffs2image4760x core
diff --git a/fs/yaffs2/utils/mkyaffs2image.c b/fs/yaffs2/utils/mkyaffs2image.c
index d59845eaf23..4b3d9cbb015 100644
--- a/fs/yaffs2/utils/mkyaffs2image.c
+++ b/fs/yaffs2/utils/mkyaffs2image.c
@@ -344,16 +344,17 @@ static int write_chunk(__u8 *data, __u32 objId, __u32 chunkId, __u32 nBytes)
         } else {
                 nandmtd2_pt2buf(spare_buf, &pt);
         }
-
 	/* In oob area, bad block status: 2 Bytes, yaffs info: 16 Bytes. 
 	   We use software 4-bit bch algorithm to encode yaffs info, and 
 	   put the 4-Bytes parity data in (spare_buf + 2 + 16) area.  */
-	memset(spare_buf + 18, 0xff, spareSize - 18);
-	do_bch_encode(spare_buf + 2, spare_buf + 2 + 16, 16);
 
 #ifdef CONFIG_MTD_HW_BCH_ECC
 	/* When programming using usb boot, the data in oob after eccpos should be
 	   0xff to make programming check easy. And eccpos = 24 when using BCH. */
+	memset(spare_buf + 18, 0xff, spareSize - 18);
+	do_bch_encode(spare_buf + 2, spare_buf + 2 + 16, 16);
+
+
 	memset(spare_buf + 24, 0xff, spareSize - 24);
 #endif
 	return write(outFile,spare_buf,spareSize);
@@ -686,7 +687,8 @@ void usage(void)
 	       "                    0 - nand_oob_raw, no used, \n"
                "                    1 - nand_oob_64, for 2KB pagesize, \n"
                "                    2 - nand_oob_128, for 2KB pagesize using multiple planes or 4KB pagesize,\n"
-	       "                    3 - nand_oob_256, for 4KB pagesize using multiple planes\n");
+               "                    3 - nand_oob_218, for 2KB pagesize using multiple planes or 4KB pagesize,\n"
+	       "                    4 - nand_oob_256, for 4KB pagesize using multiple planes\n");
 	printf("	source      the directory tree or file to be converted\n");
 	printf("	image_file  the output file to hold the image\n");
 	printf("	'convert'   make a big-endian img on a little-endian machine. BROKEN !\n");
@@ -723,6 +725,10 @@ int main(int argc, char *argv[])
 		spareSize = 128;
 		break;
 	case 3:
+		chunkSize = 4096;
+		spareSize = 218;
+		break;
+	case 4:
 		chunkSize = 8192;
 		spareSize = 256;
 		break;
diff --git a/fs/yaffs2/utils/mkyaffs2image4760x.c b/fs/yaffs2/utils/mkyaffs2image4760x.c
new file mode 100644
index 00000000000..2d51dfc85a1
--- /dev/null
+++ b/fs/yaffs2/utils/mkyaffs2image4760x.c
@@ -0,0 +1,897 @@
+/*
+ * YAFFS: Yet another FFS. A NAND-flash specific file system.
+ *
+ * makeyaffsimage.c
+ *
+ * Makes a YAFFS file system image that can be used to load up a file system.
+ *
+ * Copyright (C) 2002 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *
+ * Nick Bane modifications flagged NCB
+ *
+ * Endian handling patches by James Ng.
+ *
+ * mkyaffs2image hacks by NCB
+ *
+ * Changes by Sergey Kubushin flagged KSI
+ *
+ * Modified by <hpyang@ingenic.cn> base on mkyaffs2image.c
+ *
+ */
+
+/* KSI:
+ * All this nightmare should be rewritten from ground up. Why save return
+ * values if nobody checks them? The read/write function returns only one
+ * error, -1. Positive return value does NOT mean read/write operation has
+ * been completed successfully. If somebody opens files, he MUST close them
+ * when they are not longer needed. Only those brave enough can write 64
+ * bytes from a yaffs_PackedTags2 structure. The list is too long, there is
+ * enough bugs here to write a couple of thick books on how NOT to write
+ * programs...
+ *
+ * And BTW, what was one supposed to do with that file that this horror
+ * occasionally managed to generate?
+ */
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <fcntl.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <dirent.h>
+#include <string.h>
+#include <unistd.h>
+#include <mtd/mtd-user.h>
+#include "yaffs_ecc.h"
+#include "yaffs_guts.h"
+
+#include "yaffs_packedtags2.h"
+//#include "mtd/mtd_bch4bit_n8.h"
+
+unsigned yaffs_traceMask=0;
+
+#define MAX_OBJECTS 100000
+#define MAX_CHUNKSIZE 8192
+//#define MAX_SPARESIZE 256
+#define MAX_SPARESIZE 640
+#define BYTES_PER_ECC 512
+#define ECC_POS 24
+#define PT2_BYTES 25
+
+const char * mkyaffsimage_c_version = "$Id: mkyaffs2image4760x.c,v 1.1.1.1 2008-12-01 14:29:21 lhhuang Exp $";
+
+static int	pageSize = 2048;
+static int	freeSize = 0;
+static int	chunkSize = 2048;
+static int	spareSize = 64;
+static int	eccBit = 4;
+static int	layout_no = 0;
+
+static struct nand_oobinfo oob_layout[] = {
+	{
+		.oobfree = {{2,26}}
+	}
+};
+
+#if 0
+static struct nand_oobinfo oob_layout[] = {
+        /* KSI:
+         * Dummy "raw" layout - no ECC, all the bytes are free. Does NOT
+         * really work, only used for compatibility with CVS YAFFS2 that
+         * never ever worked with any stock MTD.
+         */
+        {
+        	.useecc = MTD_NANDECC_AUTOPLACE,
+        	.eccbytes = 0,
+        	.eccpos = {},
+        	.oobfree = { {0, 64} }
+        },
+        /* KSI:
+         * Regular MTD AUTOPLACED ECC for large page NAND devices, the
+         * only one existing in stock MTD so far. It corresponds to layout# 1
+         * in command line arguments. Any other layouts could be added to
+         * the list when they made their way in kernel's MTD. The structure
+         * is simply copied from kernel's drivers/mtd/nand/nand_base.c as-is.
+         */
+        /* For 2KB pagesize NAND devices */
+        {
+        	.useecc = MTD_NANDECC_AUTOPLACE,
+        	.eccbytes = 36,
+        	.eccpos = {
+			28, 29, 30, 31,
+			32, 33, 34, 35, 36, 37, 38, 39,
+			40, 41, 42, 43, 44, 45, 46, 47,
+			48, 49, 50, 51, 52, 53, 54, 55,
+			56, 57, 58, 59, 60, 61, 62, 63},
+		.oobfree = {{2, 26}}
+        },
+        /* For 4KB pagesize NAND devices */
+        {
+        	.useecc = MTD_NANDECC_AUTOPLACE,
+		.eccbytes = 72,
+		.eccpos = {
+			28, 29, 30, 31,	32, 33, 34, 35,
+			36, 37, 38, 39, 40, 41, 42, 43,
+			44, 45, 46, 47, 48, 49, 50, 51,
+			52, 53, 54, 55, 56, 57, 58, 59,
+			60, 61, 62, 63, 64, 65, 66, 67,
+			68, 69, 70, 71, 72, 73, 74, 75,
+			76, 77, 78, 79, 80, 81, 82, 83,
+			84, 85, 86, 87, 88, 89, 90, 91,
+			92, 93, 94, 95,	96, 97, 98, 99},
+		.oobfree = {
+			{2, 26},
+			{100, 28}}
+        },
+        /* For 4KB pagesize with 2 planes NAND devices */
+        {
+        	.useecc = MTD_NANDECC_AUTOPLACE,
+		.eccbytes = 72,
+		.eccpos = {
+			28, 29, 30, 31,	32, 33, 34, 35,
+			36, 37, 38, 39, 40, 41, 42, 43,
+			44, 45, 46, 47, 48, 49, 50, 51,
+			52, 53, 54, 55, 56, 57, 58, 59,
+			60, 61, 62, 63, 64, 65, 66, 67,
+			68, 69, 70, 71, 72, 73, 74, 75,
+			76, 77, 78, 79, 80, 81, 82, 83,
+			84, 85, 86, 87, 88, 89, 90, 91,
+			92, 93, 94, 95,	96, 97, 98, 99},
+		.oobfree = {
+			{2, 26},
+			{100, 28}}
+        },
+        /* For 8KB pagesize with NAND devices */
+	{
+        	.useecc = MTD_NANDECC_AUTOPLACE,
+		.eccbytes = 72,
+		.eccpos = {
+			28, 29, 30, 31,	32, 33, 34, 35,
+			36, 37, 38, 39, 40, 41, 42, 43,
+			44, 45, 46, 47, 48, 49, 50, 51,
+			52, 53, 54, 55, 56, 57, 58, 59,
+			60, 61, 62, 63, 64, 65, 66, 67,
+			68, 69, 70, 71, 72, 73, 74, 75,
+			76, 77, 78, 79, 80, 81, 82, 83,
+			84, 85, 86, 87, 88, 89, 90, 91,
+			92, 93, 94, 95,	96, 97, 98, 99},
+		.oobfree = {
+			{2, 26},
+			{100, 28}}
+        },
+        /* End-of-list marker */
+        {
+                .useecc = -1,
+        }
+};
+#endif
+
+typedef struct
+{
+	dev_t dev;
+	ino_t ino;
+	int   obj;
+} objItem;
+
+
+static objItem obj_list[MAX_OBJECTS];
+static int n_obj = 0;
+static int obj_id = YAFFS_NOBJECT_BUCKETS + 1;
+
+static int nObjects = 0, nDirectories = 0, nPages = 0;
+
+static int outFile;
+
+static int error;
+
+static int convert_endian = 0;
+
+void nandmtd2_pt2buf(unsigned char *buf, yaffs_PackedTags2 *pt);
+void usage(void);
+void process_file(char *file_name);
+
+static int obj_compare(const void *a, const void * b)
+{
+  objItem *oa, *ob;
+
+  oa = (objItem *)a;
+  ob = (objItem *)b;
+
+  if(oa->dev < ob->dev) return -1;
+  if(oa->dev > ob->dev) return 1;
+  if(oa->ino < ob->ino) return -1;
+  if(oa->ino > ob->ino) return 1;
+
+  return 0;
+}
+
+
+static void add_obj_to_list(dev_t dev, ino_t ino, int obj)
+{
+	if(n_obj < MAX_OBJECTS)
+	{
+		obj_list[n_obj].dev = dev;
+		obj_list[n_obj].ino = ino;
+		obj_list[n_obj].obj = obj;
+		n_obj++;
+		qsort(obj_list,n_obj,sizeof(objItem),obj_compare);
+
+	}
+	else
+	{
+		// oops! not enough space in the object array
+		fprintf(stderr,"Not enough space in object array\n");
+		exit(2);
+	}
+}
+
+
+static int find_obj_in_list(dev_t dev, ino_t ino)
+{
+	objItem *i = NULL;
+	objItem test;
+
+	test.dev = dev;
+	test.ino = ino;
+
+	if(n_obj > 0)
+	{
+		i = bsearch(&test,obj_list,n_obj,sizeof(objItem),obj_compare);
+	}
+
+	if(i)
+	{
+		return i->obj;
+	}
+	return -1;
+}
+
+/* KSI:
+ * No big endian for now. This is left for a later time. The existing code
+ * is FUBAR.
+ */
+#if 0
+/* This little function converts a little endian tag to a big endian tag.
+ * NOTE: The tag is not usable after this other than calculating the CRC
+ * with.
+ */
+static void little_to_big_endian(yaffs_Tags *tagsPtr)
+{
+#if 0 // FIXME NCB
+    yaffs_TagsUnion * tags = (yaffs_TagsUnion* )tagsPtr; // Work in bytes.
+    yaffs_TagsUnion   temp;
+
+    memset(&temp, 0, sizeof(temp));
+    // Ick, I hate magic numbers.
+    temp.asBytes[0] = ((tags->asBytes[2] & 0x0F) << 4) | ((tags->asBytes[1] & 0xF0) >> 4);
+    temp.asBytes[1] = ((tags->asBytes[1] & 0x0F) << 4) | ((tags->asBytes[0] & 0xF0) >> 4);
+    temp.asBytes[2] = ((tags->asBytes[0] & 0x0F) << 4) | ((tags->asBytes[2] & 0x30) >> 2) | ((tags->asBytes[3] & 0xC0) >> 6);
+    temp.asBytes[3] = ((tags->asBytes[3] & 0x3F) << 2) | ((tags->asBytes[2] & 0xC0) >> 6);
+    temp.asBytes[4] = ((tags->asBytes[6] & 0x03) << 6) | ((tags->asBytes[5] & 0xFC) >> 2);
+    temp.asBytes[5] = ((tags->asBytes[5] & 0x03) << 6) | ((tags->asBytes[4] & 0xFC) >> 2);
+    temp.asBytes[6] = ((tags->asBytes[4] & 0x03) << 6) | (tags->asBytes[7] & 0x3F);
+    temp.asBytes[7] = (tags->asBytes[6] & 0xFC) | ((tags->asBytes[7] & 0xC0) >> 6);
+
+    // Now copy it back.
+    tags->asBytes[0] = temp.asBytes[0];
+    tags->asBytes[1] = temp.asBytes[1];
+    tags->asBytes[2] = temp.asBytes[2];
+    tags->asBytes[3] = temp.asBytes[3];
+    tags->asBytes[4] = temp.asBytes[4];
+    tags->asBytes[5] = temp.asBytes[5];
+    tags->asBytes[6] = temp.asBytes[6];
+    tags->asBytes[7] = temp.asBytes[7];
+#endif
+}
+#endif
+
+void nandmtd2_pt2buf(unsigned char *buf, yaffs_PackedTags2 *pt)
+{
+	int		i, j = 0, k, n;
+	unsigned char	pt2_byte_buf[PT2_BYTES];
+
+	*((unsigned int *) &pt2_byte_buf[0]) = pt->t.sequenceNumber;
+	*((unsigned int *) &pt2_byte_buf[4]) = pt->t.objectId;
+	*((unsigned int *) &pt2_byte_buf[8]) = pt->t.chunkId;
+	*((unsigned int *) &pt2_byte_buf[12]) = pt->t.byteCount;
+	pt2_byte_buf[16] = pt->ecc.colParity;
+	pt2_byte_buf[17] = pt->ecc.lineParity & 0xff;
+	pt2_byte_buf[18] = (pt->ecc.lineParity >> 8) & 0xff;
+	pt2_byte_buf[19] = (pt->ecc.lineParity >> 16) & 0xff;
+	pt2_byte_buf[20] = (pt->ecc.lineParity >> 24) & 0xff;
+	pt2_byte_buf[21] = pt->ecc.lineParityPrime & 0xff;
+	pt2_byte_buf[22] = (pt->ecc.lineParityPrime >> 8) & 0xff;
+	pt2_byte_buf[23] = (pt->ecc.lineParityPrime >> 16) & 0xff;
+	pt2_byte_buf[24] = (pt->ecc.lineParityPrime >> 24) & 0xff;
+
+	k = oob_layout[layout_no].oobfree[j][0];
+	n = oob_layout[layout_no].oobfree[j][1];
+
+	if (n == 0) {
+		fprintf(stderr, "No OOB space for tags");
+		exit(-1);
+	}
+
+	for (i = 0; i < PT2_BYTES; i++) {
+		if (n == 0) {
+			j++;
+			k = oob_layout[layout_no].oobfree[j][0];
+			n = oob_layout[layout_no].oobfree[j][1];
+			if (n == 0) {
+				fprintf(stderr, "No OOB space for tags");
+				exit(-1);
+			}
+		}
+		buf[k++] = pt2_byte_buf[i];
+		n--;
+	}
+}
+
+static int write_chunk(__u8 *data, __u32 objId, __u32 chunkId, __u32 nBytes)
+{
+	yaffs_ExtendedTags t;
+	yaffs_PackedTags2 pt;
+	unsigned char	spare_buf[MAX_SPARESIZE];
+
+
+	error = write(outFile,data,chunkSize);
+	if(error < 0) return error;
+
+	yaffs_InitialiseTags(&t);
+
+	t.chunkId = chunkId;
+//	t.serialNumber = 0;
+	t.serialNumber = 1;	// **CHECK**
+	t.byteCount = nBytes;
+	t.objectId = objId;
+
+	t.sequenceNumber = YAFFS_LOWEST_SEQUENCE_NUMBER;
+
+// added NCB **CHECK**
+	t.chunkUsed = 1;
+
+/* KSI: Broken anyway -- e.g. &t is pointer to a wrong type... */
+#if 0
+	if (convert_endian)
+	{
+    	    little_to_big_endian(&t);
+	}
+#endif
+
+	nPages++;
+
+	yaffs_PackTags2(&pt,&t);
+
+        memset(spare_buf, 0xff, spareSize);
+
+//        if (layout_no == 0) {
+//                memcpy(spare_buf, &pt, sizeof(yaffs_PackedTags2));
+//        } else {
+                nandmtd2_pt2buf(spare_buf, &pt);
+//        }
+
+#if 0
+	/* In oob area, bad block status: 2 Bytes, yaffs info: 16 Bytes. 
+	   We use software 4-bit bch algorithm to encode yaffs info, and 
+	   put the 4-Bytes parity data in (spare_buf + 2 + 16) area.  */
+	memset(spare_buf + 18, 0xff, spareSize - 18);
+	do_bch_encode(spare_buf + 2, spare_buf + 2 + 16, 16);
+#ifdef CONFIG_MTD_HW_BCH_ECC
+	/* When programming using usb boot, the data in oob after eccpos should be
+	   0xff to make programming check easy. And eccpos = 24 when using BCH. */
+	memset(spare_buf + 24, 0xff, spareSize - 24);
+#endif
+#endif
+	memset(spare_buf + 18, 0xff, spareSize - 18);
+	return write(outFile,spare_buf,spareSize);
+}
+
+#define SWAP32(x)   ((((x) & 0x000000FF) << 24) | \
+                     (((x) & 0x0000FF00) << 8 ) | \
+                     (((x) & 0x00FF0000) >> 8 ) | \
+                     (((x) & 0xFF000000) >> 24))
+
+#define SWAP16(x)   ((((x) & 0x00FF) << 8) | \
+                     (((x) & 0xFF00) >> 8))
+
+/* KSI: Removed for now. TBD later when the proper util (from scratch) is written */
+#if 0
+// This one is easier, since the types are more standard. No funky shifts here.
+static void object_header_little_to_big_endian(yaffs_ObjectHeader* oh)
+{
+    oh->type = SWAP32(oh->type); // GCC makes enums 32 bits.
+    oh->parentObjectId = SWAP32(oh->parentObjectId); // int
+    oh->sum__NoLongerUsed = SWAP16(oh->sum__NoLongerUsed); // __u16 - Not used, but done for completeness.
+    // name = skip. Char array. Not swapped.
+    oh->yst_mode = SWAP32(oh->yst_mode);
+#ifdef CONFIG_YAFFS_WINCE // WinCE doesn't implement this, but we need to just in case.
+    // In fact, WinCE would be *THE* place where this would be an issue!
+    oh->notForWinCE[0] = SWAP32(oh->notForWinCE[0]);
+    oh->notForWinCE[1] = SWAP32(oh->notForWinCE[1]);
+    oh->notForWinCE[2] = SWAP32(oh->notForWinCE[2]);
+    oh->notForWinCE[3] = SWAP32(oh->notForWinCE[3]);
+    oh->notForWinCE[4] = SWAP32(oh->notForWinCE[4]);
+#else
+    // Regular POSIX.
+    oh->yst_uid = SWAP32(oh->yst_uid);
+    oh->yst_gid = SWAP32(oh->yst_gid);
+    oh->yst_atime = SWAP32(oh->yst_atime);
+    oh->yst_mtime = SWAP32(oh->yst_mtime);
+    oh->yst_ctime = SWAP32(oh->yst_ctime);
+#endif
+
+    oh->fileSize = SWAP32(oh->fileSize); // Aiee. An int... signed, at that!
+    oh->equivalentObjectId = SWAP32(oh->equivalentObjectId);
+    // alias  - char array.
+    oh->yst_rdev = SWAP32(oh->yst_rdev);
+
+#ifdef CONFIG_YAFFS_WINCE
+    oh->win_ctime[0] = SWAP32(oh->win_ctime[0]);
+    oh->win_ctime[1] = SWAP32(oh->win_ctime[1]);
+    oh->win_atime[0] = SWAP32(oh->win_atime[0]);
+    oh->win_atime[1] = SWAP32(oh->win_atime[1]);
+    oh->win_mtime[0] = SWAP32(oh->win_mtime[0]);
+    oh->win_mtime[1] = SWAP32(oh->win_mtime[1]);
+    oh->roomToGrow[0] = SWAP32(oh->roomToGrow[0]);
+    oh->roomToGrow[1] = SWAP32(oh->roomToGrow[1]);
+    oh->roomToGrow[2] = SWAP32(oh->roomToGrow[2]);
+    oh->roomToGrow[3] = SWAP32(oh->roomToGrow[3]);
+    oh->roomToGrow[4] = SWAP32(oh->roomToGrow[4]);
+    oh->roomToGrow[5] = SWAP32(oh->roomToGrow[5]);
+#else
+    oh->roomToGrow[0] = SWAP32(oh->roomToGrow[0]);
+    oh->roomToGrow[1] = SWAP32(oh->roomToGrow[1]);
+    oh->roomToGrow[2] = SWAP32(oh->roomToGrow[2]);
+    oh->roomToGrow[3] = SWAP32(oh->roomToGrow[3]);
+    oh->roomToGrow[4] = SWAP32(oh->roomToGrow[4]);
+    oh->roomToGrow[5] = SWAP32(oh->roomToGrow[5]);
+    oh->roomToGrow[6] = SWAP32(oh->roomToGrow[6]);
+    oh->roomToGrow[7] = SWAP32(oh->roomToGrow[7]);
+    oh->roomToGrow[8] = SWAP32(oh->roomToGrow[8]);
+    oh->roomToGrow[9] = SWAP32(oh->roomToGrow[9]);
+    oh->roomToGrow[10] = SWAP32(oh->roomToGrow[10]);
+    oh->roomToGrow[11] = SWAP32(oh->roomToGrow[11]);
+#endif
+}
+#endif
+
+static int write_object_header(int objId, yaffs_ObjectType t, struct stat *s, int parent, const char *name, int equivalentObj, const char * alias)
+{
+	__u8 bytes[MAX_CHUNKSIZE];
+
+
+	yaffs_ObjectHeader *oh = (yaffs_ObjectHeader *)bytes;
+
+	memset(bytes,0xff,chunkSize);
+
+	oh->type = t;
+
+	oh->parentObjectId = parent;
+
+	strncpy(oh->name,name,YAFFS_MAX_NAME_LENGTH);
+
+
+	if(t != YAFFS_OBJECT_TYPE_HARDLINK)
+	{
+		oh->yst_mode = s->st_mode;
+		oh->yst_uid = s->st_uid;
+// NCB 12/9/02		oh->yst_gid = s->yst_uid;
+		oh->yst_gid = s->st_gid;
+		oh->yst_atime = s->st_atime;
+		oh->yst_mtime = s->st_mtime;
+		oh->yst_ctime = s->st_ctime;
+		oh->yst_rdev  = s->st_rdev;
+	}
+
+	if(t == YAFFS_OBJECT_TYPE_FILE)
+	{
+		oh->fileSize = s->st_size;
+	}
+
+	if(t == YAFFS_OBJECT_TYPE_HARDLINK)
+	{
+		oh->equivalentObjectId = equivalentObj;
+	}
+
+	if(t == YAFFS_OBJECT_TYPE_SYMLINK)
+	{
+		strncpy(oh->alias,alias,YAFFS_MAX_ALIAS_LENGTH);
+	}
+
+/* KSI: FUBAR. Left for a leter time. */
+#if 0
+	if (convert_endian)
+	{
+    		object_header_little_to_big_endian(oh);
+	}
+#endif
+
+	return write_chunk(bytes,objId,0,0xffff);
+
+}
+
+
+static int process_directory(int parent, const char *path)
+{
+
+	DIR *dir;
+	struct dirent *entry;
+
+	nDirectories++;
+
+	dir = opendir(path);
+
+	if(dir)
+	{
+		while((entry = readdir(dir)) != NULL)
+		{
+
+			/* Ignore . and .. */
+			if(strcmp(entry->d_name,".") &&
+			   strcmp(entry->d_name,".."))
+ 			{
+ 				char full_name[500];
+				struct stat stats;
+				int equivalentObj;
+				int newObj;
+
+				sprintf(full_name,"%s/%s",path,entry->d_name);
+
+				lstat(full_name,&stats);
+
+				if(S_ISLNK(stats.st_mode) ||
+				    S_ISREG(stats.st_mode) ||
+				    S_ISDIR(stats.st_mode) ||
+				    S_ISFIFO(stats.st_mode) ||
+				    S_ISBLK(stats.st_mode) ||
+				    S_ISCHR(stats.st_mode) ||
+				    S_ISSOCK(stats.st_mode))
+				{
+
+					newObj = obj_id++;
+					nObjects++;
+
+					printf("Object %d, %s is a ",newObj,full_name);
+
+					/* We're going to create an object for it */
+					if((equivalentObj = find_obj_in_list(stats.st_dev, stats.st_ino)) > 0)
+					{
+					 	/* we need to make a hard link */
+					 	printf("hard link to object %d\n",equivalentObj);
+						error =  write_object_header(newObj, YAFFS_OBJECT_TYPE_HARDLINK, &stats, parent, entry->d_name, equivalentObj, NULL);
+					}
+					else
+					{
+
+						add_obj_to_list(stats.st_dev,stats.st_ino,newObj);
+
+						if(S_ISLNK(stats.st_mode))
+						{
+
+							char symname[500];
+
+							memset(symname,0, sizeof(symname));
+
+							readlink(full_name,symname,sizeof(symname) -1);
+
+							printf("symlink to \"%s\"\n",symname);
+							error =  write_object_header(newObj, YAFFS_OBJECT_TYPE_SYMLINK, &stats, parent, entry->d_name, -1, symname);
+
+						}
+						else if(S_ISREG(stats.st_mode))
+						{
+							printf("file, ");
+							error =  write_object_header(newObj, YAFFS_OBJECT_TYPE_FILE, &stats, parent, entry->d_name, -1, NULL);
+
+							if(error >= 0)
+							{
+								int h;
+								__u8 bytes[MAX_CHUNKSIZE];
+								int nBytes;
+								int chunk = 0;
+
+								h = open(full_name,O_RDONLY);
+								if(h >= 0)
+								{
+									memset(bytes,0xff,chunkSize);
+									while((nBytes = read(h,bytes,chunkSize)) > 0)
+									{
+										chunk++;
+										write_chunk(bytes,newObj,chunk,nBytes);
+										memset(bytes,0xff,chunkSize);
+									}
+									if(nBytes < 0)
+									   error = nBytes;
+
+									printf("%d data chunks written\n",chunk);
+        								close(h);
+								}
+								else
+								{
+									perror("Error opening file");
+								}
+
+							}
+
+						}
+						else if(S_ISSOCK(stats.st_mode))
+						{
+							printf("socket\n");
+							error =  write_object_header(newObj, YAFFS_OBJECT_TYPE_SPECIAL, &stats, parent, entry->d_name, -1, NULL);
+						}
+						else if(S_ISFIFO(stats.st_mode))
+						{
+							printf("fifo\n");
+							error =  write_object_header(newObj, YAFFS_OBJECT_TYPE_SPECIAL, &stats, parent, entry->d_name, -1, NULL);
+						}
+						else if(S_ISCHR(stats.st_mode))
+						{
+							printf("character device\n");
+							error =  write_object_header(newObj, YAFFS_OBJECT_TYPE_SPECIAL, &stats, parent, entry->d_name, -1, NULL);
+						}
+						else if(S_ISBLK(stats.st_mode))
+						{
+							printf("block device\n");
+							error =  write_object_header(newObj, YAFFS_OBJECT_TYPE_SPECIAL, &stats, parent, entry->d_name, -1, NULL);
+						}
+						else if(S_ISDIR(stats.st_mode))
+						{
+							printf("directory\n");
+							error =  write_object_header(newObj, YAFFS_OBJECT_TYPE_DIRECTORY, &stats, parent, entry->d_name, -1, NULL);
+// NCB modified 10/9/2001				process_directory(1,full_name);
+							process_directory(newObj,full_name);
+						}
+					}
+				}
+				else
+				{
+					printf(" we don't handle this type\n");
+				}
+			}
+		}
+		/* KSI:
+		 * Who is supposed to close those open directories in this
+		 * recursive function, lord Byron? Stock "ulimit -n" is 1024
+		 * and e.g. stock Fedora /etc directory has more that 1024
+		 * directories...
+		 */
+		closedir(dir);
+	}
+
+	return 0;
+
+}
+
+void process_file(char *file_name)
+{
+	printf("file, ");
+
+	int h;
+	__u8 bytes[MAX_CHUNKSIZE];
+	int nBytes;
+	int chunk = 0;
+
+	h = open(file_name,O_RDONLY);
+	if(h >= 0)
+	{
+		memset(bytes,0xff,chunkSize);
+		while((nBytes = read(h,bytes,chunkSize)) > 0)
+		{
+			chunk++;
+			write_chunk(bytes,0,chunk,nBytes);
+			memset(bytes,0xff,chunkSize);
+		}
+		if(nBytes < 0) {
+			printf("error occured!\n");
+		}
+		printf("%d data chunks written\n",chunk);
+		close(h);
+	}
+	else
+	{
+		perror("Error opening file");
+	}
+}
+
+
+void usage(void)
+{
+        /* ECC for oob should conform with CONFIG_YAFFS_ECC_XX when building linux kernel, but ecc
+	   for oob isn't required when using BCH ECC, as oob will be corrected together with data
+	   when using BCH ECC. */
+#if defined(CONFIG_YAFFS_ECC_RS)
+	printf("Reed-solomn ECC will be used for checking 16 bytes for yaffs2 information in oob area.\n"
+	       "so, CONFIG_YAFFS_ECC_RS should be selected when building linux kernel.\n");
+#elif defined(CONFIG_YAFFS_ECC_HAMMING)
+	printf("Hamming ECC will be used for checking 16 bytes for yaffs2 information in oob area.\n"
+	       "so, CONFIG_YAFFS_ECC_HAMMING should be selected when building linux kernel.\n");
+#endif
+
+	printf("\nusage: mkyaffs2image4760x PageSize SpareSize EccBit source image_file [convert]\n");
+	printf("	PageSize    the page size of the nand chip\n");
+	printf("	SpareSize   the spare(OOB) size of the nand chip\n");
+	printf("	EccBit	    the ecc bits per 512 Bytes. Maybe 4|8|12|16|20|24\n");
+	printf("	source      the directory tree or file to be converted\n");
+	printf("	image_file  the output file to hold the image\n");
+	printf("	'convert'   make a big-endian img on a little-endian machine. BROKEN !\n");
+	printf("\n Example:\n"
+	       "        mkyaffs2image4760x 2048 64 4 /nfsroot/root26 root26.yaffs2 \n"
+	       "        mkyaffs2image4760x 8192 436 24 uImage uImage.oob \n\n");
+	printf("or: mkyaffs2image4760x list\n");
+	printf("	list	    list the nand info.\n");
+	printf("\n Example:\n"
+	       "        mkyaffs2image4760x list\n\n");
+	exit(1);
+}
+
+void DumpList(void)
+{
+	printf("\nNand Info:\n");
+	printf("Type			PageSize	SpareSize\n");
+
+	printf("SAMSUNG_K9G8G08U0M	2048 Bytes	64 Bytes\n");
+	printf("SAMSUNG_K9F1G08U0M	2048 Bytes	64 Bytes\n");
+	printf("SAMSUNG_K9HBG08U1M	2048 Bytes	64 Bytes\n");
+	printf("SAMSUNG_K9G8G08U0B	2048 Bytes	64 Bytes\n");
+	printf("SAMSUNG_K9LBG08U0M	4096 Bytes	64 Bytes\n");
+	printf("SAMSUNG_K9GAG08U0M	4096 Bytes	128 Bytes\n");
+	printf("SAMSUNG_K9GAG08U0D	4096 Bytes	218 Bytes\n");
+	printf("SAMSUNG_K9GAG08U0E	8192 Bytes	436 Bytes\n");
+	printf("SAMSUNG_K9GBG08U0M	8192 Bytes	436 Bytes\n");
+
+	exit(0);	
+}
+
+static int calc_free_size(int pagesize, int sparesize, int eccbit)
+{
+	int freesize;
+	int eccbytes;
+
+	switch(eccbit)
+	{
+		case 4:
+			eccbytes = 7;
+			break;
+		case 8:
+			eccbytes = 13;
+			break;
+		case 12:
+			eccbytes = 20;
+			break;
+		case 16:
+			eccbytes = 26;
+			break;
+		case 20:
+			eccbytes = 33;
+			break;
+		case 24:
+			eccbytes = 39;
+			break;
+		default:
+			break;
+	}
+
+	if ((pagesize / BYTES_PER_ECC + 1) * eccbytes + ECC_POS > sparesize)
+		freesize = 512;
+	else
+		freesize = 0;
+
+	return freesize;
+} 
+
+int main(int argc, char *argv[])
+{
+	struct stat stats;
+	int	i;
+
+	printf("\nmkyaffs2image: image building tool for YAFFS2 built "__DATE__"\n");
+
+	if (argc < 6)
+	{
+		if(argc == 2 && !strncmp(argv[1],"list",4)) {
+			DumpList();
+		} else {
+			usage();
+		}
+	}
+
+	sscanf(argv[1], "%u", &pageSize);
+	sscanf(argv[2], "%u", &spareSize);
+	sscanf(argv[3], "%u", &eccBit);
+	
+	if ((eccBit != 4) && (eccBit != 8) && (eccBit != 12) && (eccBit != 16) && (eccBit != 20) && (eccBit != 24)) 
+	{
+		printf("\nError: the value of EccBit invalid.\n");
+		usage();
+	}
+
+	freeSize = calc_free_size(pageSize, spareSize, eccBit);
+	
+	chunkSize = pageSize - freeSize;
+
+	if (chunkSize < 512 || chunkSize % BYTES_PER_ECC != 0)
+	{
+		printf("\nError: pagesize or freesize is invalid.\n");
+		usage();
+	}
+
+	printf("\nInfo: pagesize:%d sparesize:%d eccbit:%d freesize:%d chunksize:%d\n\n", \
+			pageSize, spareSize, eccBit, freeSize, chunkSize);
+
+//	i = 0;
+
+//	while (oob_layout[i].useecc != -1)
+//	        i++;
+
+//        if (layout_no >= i)
+//                usage();
+
+	if ((argc == 7) && (!strncmp(argv[6], "convert", strlen("convert"))))
+	{
+	        /* KSI: Broken as of now. TBD. Fail. */
+	        usage();
+                convert_endian = 1;
+        }
+
+	if(stat(argv[4],&stats) < 0)
+	{
+		printf("Could not stat %s\n",argv[4]);
+		exit(1);
+	}
+
+	if(!S_ISDIR(stats.st_mode))
+	{
+		printf(" %s is not a directory. For a file, just pad oob to data area.\n",argv[4]);
+//		exit(1);
+	}
+
+	outFile = open(argv[5],O_CREAT | O_TRUNC | O_WRONLY, S_IREAD | S_IWRITE);
+
+
+	if(outFile < 0)
+	{
+		printf("Could not open output file %s\n",argv[5]);
+		exit(1);
+	}
+
+        /* for a file, just pad oob to data area */
+	if(S_ISREG(stats.st_mode))
+	{
+		process_file(argv[4]);
+		close(outFile);
+		exit(0);
+	}
+
+	printf("Processing directory %s into image file %s\n\n",argv[4],argv[5]);
+	error =  write_object_header(1, YAFFS_OBJECT_TYPE_DIRECTORY, &stats, 1,"", -1, NULL);
+
+	if(error)
+	error = process_directory(YAFFS_OBJECTID_ROOT,argv[4]);
+
+	close(outFile);
+
+	if(error < 0)
+	{
+		perror("operation incomplete");
+		exit(1);
+	}
+	else
+	{
+		printf("Operation complete.\n"
+		       "%d objects in %d directories\n"
+		       "%d NAND pages\n",nObjects, nDirectories, nPages);
+	}
+
+	close(outFile);
+
+	exit(0);
+}
+
diff --git a/fs/yaffs2/yaffs_fs.c b/fs/yaffs2/yaffs_fs.c
index bebe61ace00..db28ddeaa77 100644
--- a/fs/yaffs2/yaffs_fs.c
+++ b/fs/yaffs2/yaffs_fs.c
@@ -113,10 +113,14 @@ static uint32_t YCALCBLOCKS(uint64_t partition_size, uint32_t block_size)
 #include "yportenv.h"
 #include "yaffs_guts.h"
 
-unsigned yaffs_traceMask = YAFFS_TRACE_ALWAYS | 
-			   YAFFS_TRACE_BAD_BLOCKS/* | 
-			    YAFFS_TRACE_CHECKPOINT*/
-			   /* | 0xFFFFFFFF */; 
+#if 1
+	unsigned yaffs_traceMask = 0x0; 
+#else
+	unsigned yaffs_traceMask = YAFFS_TRACE_ALWAYS | 
+				   YAFFS_TRACE_BAD_BLOCKS | 
+			    	   YAFFS_TRACE_CHECKPOINT |
+				   0xFFFFFFFF ; 
+#endif
 
 #include <linux/mtd/mtd.h>
 #include "yaffs_mtdif.h"
@@ -1923,6 +1927,8 @@ static struct super_block *yaffs_internal_read_super(int yaffsVersion,
 	T(YAFFS_TRACE_OS, (" oobblock %d\n", mtd->oobblock));
 #endif
 	T(YAFFS_TRACE_OS, (" oobsize %d\n", mtd->oobsize));
+	T(YAFFS_TRACE_OS, (" validsize %d\n", mtd->validsize));
+	T(YAFFS_TRACE_OS, (" freesize %d\n", mtd->freesize));
 	T(YAFFS_TRACE_OS, (" erasesize %d\n", mtd->erasesize));
 	T(YAFFS_TRACE_OS, (" size %lld\n", mtd->size));
 	
@@ -2051,7 +2057,11 @@ static struct super_block *yaffs_internal_read_super(int yaffsVersion,
 		dev->spareBuffer = YMALLOC(mtd->oobsize);
 		dev->isYaffs2 = 1;
 #if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,17))
+#if !defined(CONFIG_SOC_JZ4760B)
 		dev->nDataBytesPerChunk = mtd->writesize;
+#else
+		dev->nDataBytesPerChunk = mtd->validsize;
+#endif
 		dev->nChunksPerBlock = mtd->erasesize / mtd->writesize;
 #else
 		dev->nDataBytesPerChunk = mtd->oobblock;
diff --git a/fs/yaffs2/yaffs_mtdif.c b/fs/yaffs2/yaffs_mtdif.c
index 9b50e109efc..09d39eebf79 100644
--- a/fs/yaffs2/yaffs_mtdif.c
+++ b/fs/yaffs2/yaffs_mtdif.c
@@ -84,7 +84,11 @@ int nandmtd_WriteChunkToNAND(yaffs_Device * dev, int chunkInNAND,
 	size_mtd_t dummy;
 	int retval = 0;
 
+#if !defined(CONFIG_SOC_JZ4760B)
 	loff_mtd_t addr = ((loff_mtd_t) chunkInNAND) * dev->nDataBytesPerChunk;
+#else
+	loff_mtd_t addr = ((loff_mtd_t) chunkInNAND) * mtd->writesize;
+#endif
 
 #if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,17))
 	__u8 spareAsBytes[8]; /* OOB */
@@ -94,8 +98,10 @@ int nandmtd_WriteChunkToNAND(yaffs_Device * dev, int chunkInNAND,
 				&dummy, data);
 	else if (spare) {
 		if (dev->useNANDECC) {
+	//		printk("YAFFS2:%s %s %d\n",__FILE__,__func__,__LINE__);
 			translate_spare2oob(spare, spareAsBytes);
 			ops.mode = MTD_OOB_AUTO;
+	//		ops.mode = MTD_OOB_PLACE;
 			ops.ooblen = 8; /* temp hack */
 			ops.oobbuf = spareAsBytes;
 		} else {
@@ -150,7 +156,11 @@ int nandmtd_ReadChunkFromNAND(yaffs_Device * dev, int chunkInNAND, __u8 * data,
 	size_mtd_t dummy;
 	int retval = 0;
 
+#if !defined(CONFIG_SOC_JZ4760B)
 	loff_mtd_t addr = ((loff_mtd_t) chunkInNAND) * dev->nDataBytesPerChunk;
+#else
+	loff_mtd_t addr = ((loff_mtd_t) chunkInNAND) * mtd->writesize;
+#endif
 
 #if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,17))
 	__u8 spareAsBytes[8]; /* OOB */
@@ -160,7 +170,9 @@ int nandmtd_ReadChunkFromNAND(yaffs_Device * dev, int chunkInNAND, __u8 * data,
 				&dummy, data);
 	else if (spare) {
 		if (dev->useNANDECC) {
+//			printk("YAFFS2:%s %s %d\n",__FILE__,__func__,__LINE__);
 			ops.mode = MTD_OOB_AUTO;
+//			ops.mode = MTD_OOB_PLACE;
 			ops.ooblen = 8; /* temp hack */
 			ops.oobbuf = spareAsBytes;
 		} else {
@@ -215,15 +227,27 @@ int nandmtd_ReadChunkFromNAND(yaffs_Device * dev, int chunkInNAND, __u8 * data,
 int nandmtd_EraseBlockInNAND(yaffs_Device * dev, int blockNumber)
 {
 	struct mtd_info *mtd = (struct mtd_info *)(dev->genericDevice);
+
+#if !defined(CONFIG_SOC_JZ4760B)
 	__u64 addr =
 	    ((loff_mtd_t) blockNumber) * dev->nDataBytesPerChunk
 		* dev->nChunksPerBlock;
+#else
+	__u64 addr =
+	    ((loff_mtd_t) blockNumber) * mtd->writesize 
+		* dev->nChunksPerBlock;
+#endif
+
 	struct erase_info ei;
 	int retval = 0;
 
 	ei.mtd = mtd;
 	ei.addr = addr;
+#if !defined(CONFIG_SOC_JZ4760B)
 	ei.len = dev->nDataBytesPerChunk * dev->nChunksPerBlock;
+#else
+	ei.len = mtd->writesize * dev->nChunksPerBlock;
+#endif
 	ei.time = 1000;
 	ei.retries = 2;
 	ei.callback = NULL;
diff --git a/fs/yaffs2/yaffs_mtdif2.c b/fs/yaffs2/yaffs_mtdif2.c
index f3a8263dbd7..11659d05cca 100644
--- a/fs/yaffs2/yaffs_mtdif2.c
+++ b/fs/yaffs2/yaffs_mtdif2.c
@@ -171,7 +171,11 @@ int nandmtd2_WriteChunkWithTagsToNAND(yaffs_Device * dev, int chunkInNAND,
 	size_t dummy;
 #endif
 	int retval = 0;
+#if !defined(CONFIG_SOC_JZ4760B)
 	loff_mtd_t addr = ((loff_mtd_t) chunkInNAND) * dev->nDataBytesPerChunk;
+#else
+	loff_mtd_t addr = ((loff_mtd_t) chunkInNAND) * mtd->writesize;
+#endif
 	yaffs_PackedTags2 pt;
 
 	T(YAFFS_TRACE_MTD,
@@ -188,6 +192,7 @@ int nandmtd2_WriteChunkWithTagsToNAND(yaffs_Device * dev, int chunkInNAND,
 	if (data) {
      		nandmtd2_pt2buf(dev, &pt, 0);         //modify
 		ops.mode = MTD_OOB_AUTO;
+//		ops.mode = MTD_OOB_PLACE;
 		ops.ooblen = sizeof(pt);
 		ops.len = dev->nDataBytesPerChunk;
 		ops.ooboffs = 0;
@@ -195,6 +200,7 @@ int nandmtd2_WriteChunkWithTagsToNAND(yaffs_Device * dev, int chunkInNAND,
 //		ops.oobbuf = (void *)&pt;              //modify
 		ops.oobbuf = (void *)dev->spareBuffer; //modify
 		retval = mtd->write_oob(mtd, addr, &ops);
+//		printk("YAFFS2:%s %s %d addr:0x%08p retval:%d\n",__FILE__,__func__,__LINE__,addr,retval);
 	} else
 		BUG(); /* both tags and data should always be present */
 #else
@@ -240,9 +246,14 @@ int nandmtd2_ReadChunkWithTagsFromNAND(yaffs_Device * dev, int chunkInNAND,
 #if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,17))
 	struct mtd_oob_ops ops;
 #endif
+//	dump_stack();
 	size_mtd_t dummy;
 	int retval = 0;
+#if !defined(CONFIG_SOC_JZ4760B)
 	loff_mtd_t addr = ((loff_mtd_t) chunkInNAND) * dev->nDataBytesPerChunk;
+#else
+	loff_mtd_t addr = ((loff_mtd_t) chunkInNAND) * mtd->writesize;
+#endif
 	yaffs_PackedTags2 pt;
 
 	T(YAFFS_TRACE_MTD,
@@ -255,7 +266,9 @@ int nandmtd2_ReadChunkWithTagsFromNAND(yaffs_Device * dev, int chunkInNAND,
 		retval = mtd->read(mtd, addr, dev->nDataBytesPerChunk,
 				&dummy, data);
 	else if (tags) {
+//		printk("YAFFS2:%s %s %d\n",__FILE__,__func__,__LINE__);
 		ops.mode = MTD_OOB_AUTO;
+//		ops.mode = MTD_OOB_PLACE;
 		ops.ooblen = sizeof(pt);
 		ops.len = data ? dev->nDataBytesPerChunk : sizeof(pt);
 		ops.ooboffs = 0;
@@ -298,6 +311,8 @@ int nandmtd2_ReadChunkWithTagsFromNAND(yaffs_Device * dev, int chunkInNAND,
 	
 	if(tags && retval == -EBADMSG && tags->eccResult == YAFFS_ECC_RESULT_NO_ERROR)
 		tags->eccResult = YAFFS_ECC_RESULT_UNFIXED;
+		
+//	printk("retval:%d tags.eccResult:%d\n",retval,tags->eccResult);
 
 	if (retval == 0)
 		return YAFFS_OK;
diff --git a/include/linux/i2c.h b/include/linux/i2c.h
index 8c2102d1720..f4784c0fe97 100644
--- a/include/linux/i2c.h
+++ b/include/linux/i2c.h
@@ -47,11 +47,7 @@ struct i2c_driver;
 union i2c_smbus_data;
 struct i2c_board_info;
 
-#define EEPROM_DEVICE_NUMBER   0x50   /*eeprom device number.20091027*/
-
 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
-
-extern void i2c_jz_setclk(struct i2c_client *client,unsigned long i2cclk);
 /*
  * The master routines are the ones normally used to transmit data to devices
  * on a bus (or read from them). Apart from two basic transfer functions to
diff --git a/include/linux/miscdevice.h b/include/linux/miscdevice.h
index 413510d6a4d..05211774462 100644
--- a/include/linux/miscdevice.h
+++ b/include/linux/miscdevice.h
@@ -30,7 +30,6 @@
 #define HPET_MINOR		228
 #define FUSE_MINOR		229
 #define KVM_MINOR		232
-#define CIM_MINOR		234        /* JZ CIM for multimedia */
 #define MISC_DYNAMIC_MINOR	255
 
 struct device;
diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h
index 3b126666e00..09b2fe1ddc8 100644
--- a/include/linux/mtd/mtd.h
+++ b/include/linux/mtd/mtd.h
@@ -119,6 +119,8 @@ struct mtd_info {
 	 * 1 or larger.
 	 */
 	uint32_t writesize;
+	uint32_t freesize;
+	uint32_t validsize;
 
 	uint32_t oobsize;   // Amount of OOB data per block (e.g. 16)
 	uint32_t oobavail;  // Available OOB bytes per block
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index fc2619d06cf..386c1d24723 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -37,14 +37,30 @@ extern void nand_release (struct mtd_info *mtd);
 extern void nand_wait_ready(struct mtd_info *mtd);
 
 /* The maximum number of NAND chips in an array */
-#define NAND_MAX_CHIPS		8
+#if defined(CONFIG_MTD_NAND_CS6)
+#define NAND_MAX_CHIPS		6
+#elif defined(CONFIG_MTD_NAND_CS5)
+#define NAND_MAX_CHIPS		5
+#elif defined(CONFIG_MTD_NAND_CS4)
+#define NAND_MAX_CHIPS		4
+#elif defined(CONFIG_MTD_NAND_CS3)
+#define NAND_MAX_CHIPS		3
+#elif defined(CONFIG_MTD_NAND_CS2)
+#define NAND_MAX_CHIPS		2
+#elif defined(CONFIG_MTD_NAND_JZ4760B)
+#define NAND_MAX_CHIPS		1
+#else
+#define NAND_MAX_CHIPS		0
+#endif
+
 
 /* This constant declares the max. oobsize / page, which
  * is supported now. If you add a chip with bigger oobsize/page
  * adjust this accordingly.
  */
-#define NAND_MAX_OOBSIZE	256
+#define NAND_MAX_OOBSIZE	512
 #define NAND_MAX_PAGESIZE	8192
+#define NAND_MAX_ERRSIZE	60
 
 /*
  * Constants for hardware specific CLE/ALE/NCE function
@@ -128,6 +144,11 @@ typedef enum {
 	NAND_ECC_HW_SYNDROME,
 } nand_ecc_modes_t;
 
+typedef enum {
+	NAND_DATA_HW_BCH,
+	NAND_OOB_HW_BCH,
+} hw_bch_obj;
+
 /*
  * Constants for Hardware ECC
  */
@@ -458,9 +479,25 @@ struct nand_chip {
 struct nand_flash_dev {
 	char *name;
 	int id;
+	uint32_t extid;
+	int realplanenum;
+	int dienum;
+	int tals;
+	int talh;
+	int trp;
+	int twp;
+	int trhw;
+	int trhr;
 	unsigned long pagesize;
-	u64 chipsize;
 	unsigned long erasesize;
+	uint32_t oobsize;
+	int rowcycle;
+	int maxbadblocks;
+	int maxvalidblocks;
+	int eccblock;
+	int eccbit;
+	int buswidth;
+	int badblockpos;	
 	unsigned long options;
 };
 
diff --git a/include/linux/mtd/partitions.h b/include/linux/mtd/partitions.h
index 4ab9190165f..6fe6a50c6b3 100644
--- a/include/linux/mtd/partitions.h
+++ b/include/linux/mtd/partitions.h
@@ -36,7 +36,8 @@
 
 struct mtd_partition {
 	char *name;			/* identifier string */
-	uint64_t size;			/* partition size */
+	uint64_t real_size;		/* partition real size */
+	uint64_t size;			/* partition valid size */
 	uint64_t offset;		/* offset within the master MTD space */
 	uint32_t mask_flags;		/* master MTD flags to mask out for this partition */
 	struct nand_ecclayout *ecclayout;	/* out of band layout for this partition (NAND only)*/
diff --git a/sound/oss/Kconfig b/sound/oss/Kconfig
index 324e0321846..1a5b1589adf 100644
--- a/sound/oss/Kconfig
+++ b/sound/oss/Kconfig
@@ -50,7 +50,13 @@ config I2S_DLV_4750
 
 config I2S_DLV_4760
 	bool "Internal On-Chip codec on Jz4760"
-	depends on SOC_JZ4760
+	depends on SOC_JZ4760 || SOC_JZ4760B
+	help
+	  Answer Y if you have an internal I2S codec on Jz4760.
+
+config I2S_DLV_4810
+	bool "Internal On-Chip codec on Jz4810"
+	depends on SOC_JZ4810
 	help
 	  Answer Y if you have an internal I2S codec on Jz4760.
 
diff --git a/sound/oss/Makefile b/sound/oss/Makefile
index 43dbf3037e4..ed2941e7bf8 100644
--- a/sound/oss/Makefile
+++ b/sound/oss/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_I2S_AK4642EN)	+= ak4642en.o
 obj-$(CONFIG_I2S_ICODEC)	+= jzcodec.o jz4740_i2s.o
 obj-$(CONFIG_I2S_DLV_4750)      += jzdlv.o jz_i2s.o
 obj-$(CONFIG_I2S_DLV_4760)	+= jz4760_dlv.o jz4760_i2s.o
+obj-$(CONFIG_I2S_DLV_4810)	+= jztest_dlv.o jztest_i2s.o
 obj-$(CONFIG_SOUND_JZ_PCM)	+= jz_pcm_tlv320aic1106_dma.o
 
 obj-$(CONFIG_SOUND_SH_DAC_AUDIO)	+= sh_dac_audio.o
diff --git a/sound/oss/jz4760_dlv.c b/sound/oss/jz4760_dlv.c
index 69610f20c60..d0d68d8dc77 100644
--- a/sound/oss/jz4760_dlv.c
+++ b/sound/oss/jz4760_dlv.c
@@ -35,6 +35,8 @@
 #include "jz4760_dlv.h"

 #include "jz_i2s_dbg.h"

 

+// Hanvon

+//static int spk_state;//add by wll

 

 //#define ANTI_POP_TIMER

 #define ANTI_POP_WORK_STRUCT

@@ -51,6 +53,26 @@
   #endif

 #endif

 

+#define switch_SB_LINE_IN(pwrstat)                                      \

+do {                                                            \

+        dlv_write_reg_bit(DLV_REG_PMR1, pwrstat, PMR1_SB_LINE); \

+                                                                \

+} while (0)

+

+#define switch_SB_ADC(pwrstat)                                  \

+do {                                                            \

+        dlv_write_reg_bit(DLV_REG_PMR2, pwrstat, PMR2_SB_ADC);  \

+} while (0)

+

+#define switch_SB_MIC1(pwrstat)                                 \

+do {                                                            \

+        dlv_write_reg_bit(DLV_REG_PMR1, pwrstat, PMR1_SB_MIC1); \

+        dlv_write_reg_bit(DLV_REG_PMR1, pwrstat, PMR1_SB_MIC2); \

+        dlv_write_reg_bit(DLV_REG_PMR1, pwrstat, PMR1_SB_MICBIAS);\

+                                                                \

+} while (0)

+

+

 enum device_t {

 	SND_DEVICE_DEFAULT = 0,

 	SND_DEVICE_CURRENT,

@@ -85,40 +107,40 @@ extern int gstate_dock;
 

 #define DLV_LOCK()								\

 	do{											\

-		spin_lock(g_dlv_sem_lock);				\

+		spin_lock(&g_dlv_sem_lock);				\

 		if(g_dlv_sem)							\

 			down(g_dlv_sem);					\

-		spin_unlock(g_dlv_sem_lock);			\

+		spin_unlock(&g_dlv_sem_lock);			\

 		DLV_DEBUG_SEM("dlvsemlock lock\n");		\

 	}while(0)

 

 #define DLV_UNLOCK()							\

 	do{											\

-		spin_lock(g_dlv_sem_lock);				\

+		spin_lock(&g_dlv_sem_lock);				\

 		if(g_dlv_sem)							\

 			up(g_dlv_sem);						\

-		spin_unlock(g_dlv_sem_lock);			\

+		spin_unlock(&g_dlv_sem_lock);			\

 		DLV_DEBUG_SEM("dlvsemlock unlock\n");		\

 	}while(0)

 

 #define DLV_LOCKINIT()							\

 	do{											\

-		spin_lock(g_dlv_sem_lock);										\

+		spin_lock(&g_dlv_sem_lock);										\

 		if(g_dlv_sem == NULL)											\

 			g_dlv_sem = (struct semaphore *)vmalloc(sizeof(struct semaphore)); \

 		if(g_dlv_sem)													\

 			init_MUTEX_LOCKED(g_dlv_sem);								\

-		spin_unlock(g_dlv_sem_lock);									\

+		spin_unlock(&g_dlv_sem_lock);									\

 		DLV_DEBUG_SEM("dlvsemlock init\n");									\

 	}while(0)

 

 #define DLV_LOCKDEINIT()						\

 	do{											\

-		spin_lock(g_dlv_sem_lock);				\

+		spin_lock(&g_dlv_sem_lock);				\

 		if(g_dlv_sem)							\

 			vfree(g_dlv_sem);					\

 		g_dlv_sem = NULL;						\

-		spin_unlock(g_dlv_sem_lock);			\

+		spin_unlock(&g_dlv_sem_lock);			\

 		DLV_DEBUG_SEM("dlvsemlock deinit\n");		\

 	}while(0)

 

@@ -137,6 +159,7 @@ static unsigned int g_volumes[SND_DEVICE_COUNT];
 */

 

 /* Audio route ops */

+static void dlv_anti_pop_part(void);

 static void dlv_enable_hp_out(void);

 static void dlv_disable_hp_out(void);

 static void dlv_enable_btl(void);

@@ -148,6 +171,7 @@ static void dlv_disable_receiver(void);
 static void dlv_enable_line_out(void);

 static void dlv_disable_line_out(void);

 static void dlv_enable_line_in_record(int insel);

+static void dlv_set_line_in(void);

 static void dlv_disable_line_in_record(void);

 static void dlv_enable_line_in_bypass_hp(void);

 static void dlv_disable_line_in_bypass_hp(void);

@@ -244,7 +268,6 @@ void dlv_write_reg(int addr, int val)
 static inline void dlv_sleep_wait_bitset(int reg, unsigned bit, int stime, int line)

 {

 	while(!(dlv_read_reg(reg) & (1 << bit))) {

-		printk("DLV waiting reg(%2x) bit(%2x) set %d \n",reg, bit, line);

 		msleep(stime);

 	}

 }

@@ -252,7 +275,7 @@ static inline void dlv_sleep_wait_bitset(int reg, unsigned bit, int stime, int l
 static inline void dlv_sleep_wait_bitclear(int reg, unsigned bit, int stime)

 {

 	while((dlv_read_reg(reg) & (1 << bit)))

-	      msleep(stime);

+		msleep(stime);

 }

 

 /**

@@ -279,7 +302,7 @@ static int dlv_write_reg_bit(int addr, int bitval, int mask_bit)
  * DLV CODEC operations routines

  */

 

-static inline void turn_on_dac(void)

+static inline void turn_on_dac(int timeout)

 {

 	if(__dlv_get_dac_mute()){

 		/* clear IFR_GUP */

@@ -287,11 +310,11 @@ static inline void turn_on_dac(void)
 		/* turn on dac */

 		__dlv_disable_dac_mute();

 		/* wait IFR_GUP set */

-		dlv_sleep_wait_bitset(0xb, IFR_GUP, 100,__LINE__);

+		dlv_sleep_wait_bitset(0xb, IFR_GUP, timeout,__LINE__);

 	}

 }

 

-static inline void turn_off_dac(void)

+static inline void turn_off_dac(int timeout)

 {

  	if (!(__dlv_get_dac_mute())){

 		/* clear IFR_GDO */

@@ -299,7 +322,7 @@ static inline void turn_off_dac(void)
 		/* turn off dac */

 		__dlv_enable_dac_mute();

 		/* wait IFR_GDO set */

-		dlv_sleep_wait_bitset(0xb, IFR_GUP, 100,__LINE__);

+		dlv_sleep_wait_bitset(0xb, IFR_GDO, timeout,__LINE__);

 	}

 }

 

@@ -326,14 +349,38 @@ static inline void turn_off_sb_hp(void)
         	dlv_sleep_wait_bitset(0xb, IFR_RDO, 100,__LINE__);

 	}

 }

+void dump_aic_regs2(const char *str)

+{

+	char *regname[] = {"aicfr","aiccr","aiccr1","aiccr2","i2scr","aicsr","acsr","i2ssr"};

+	int i;

+	unsigned int addr;

+

+	printk("AIC regs dump, %s\n", str);

+	for (i = 0; i < 0x1c; i += 4) {

+		addr = 0xb0020000 + i;

+		printk("%s\t0x%08x -> 0x%08x\n", regname[i/4], addr, *(unsigned int *)addr);

+	}

+}

+

 

 static void dlv_shutdown(void) {

 	unsigned long start_time = jiffies;

-

-	__dlv_enable_hp_mute();

-	udelay(500);

-	turn_off_dac();

+#if 0			      /* Hanvon */

+	spk_state=__gpio_get_pin(GPIO_SPK_SHUD);

+	__gpio_clear_pin(GPIO_SPK_SHUD);

+#endif

+	turn_off_dac(5);

+	// wll@20101020

+	//dump_dlv_regs(__FUNCTION__);

+	//dump_aic_regs2(__FUNCTION__);

+        __aic_write_tfifo(0x0);

+        __aic_write_tfifo(0x0);

+	__i2s_enable_replay();

+	msleep(1);

+	//__i2s_disable_replay();

 	turn_off_sb_hp();

+	mdelay(1);

+	__dlv_enable_hp_mute();

  	mdelay(1);

 	__dlv_switch_sb_dac(POWER_OFF);

 

@@ -370,6 +417,10 @@ static void dlv_init(void)
 	__dlv_set_irq_flag(0x3f);

 

 	__dlv_set_12m_crystal();

+	//__dlv_set_10kohm_load(); //1uF

+	__dlv_set_16ohm_load(); // 220uF

+

+        dlv_anti_pop_part();

 

 	g_current_out_dev = SND_DEVICE_SPEAKER;

 

@@ -484,6 +535,9 @@ static void dlv_get_mixer_info(mixer_info *old_info)
 	strncpy(old_info->name, "Jz internal codec dlv on jz4760", sizeof(old_info->name));

 }

 

+

+//static void dlv_set_replay_volume(int val);

+

 static void dlv_turn_off(int mode)

 {

 	ENTER();

@@ -503,9 +557,12 @@ static void dlv_turn_off(int mode)
 		printk("JZ DLV: Close REPLAY\n");

 		//dlv_disable_receiver();

 		//dlv_shutdown();

+		//dlv_set_replay_volume(0);

 		__dlv_enable_hp_mute();

 		udelay(500);

-		turn_off_dac();

+		turn_off_dac(5);

+		__aic_write_tfifo(0x0);

+		__aic_write_tfifo(0x0);

 		//nothing

 	} else if (mode & RECORD) {

 		printk("JZ DLV: Close RECORD\n");

@@ -582,7 +639,11 @@ static int dlv_set_data_width(unsigned int mode, unsigned int width)
 

 static int dlv_mute(int val)

 {

-	return dlv_write_reg_bit(DLV_REG_CR2, val ? 1 : 0, CR2_DAC_MUTE);

+	if (val)

+		turn_off_dac(10);

+	else

+		turn_on_dac(10);

+	return 0;

 }

 

 void dump_dlv_regs(const char * str)

@@ -621,15 +682,20 @@ void board_set_record(void)
 static struct work_struct dlv_anti_pop_work;

 #endif

 

+static int first_start = 1;

+

 static void dlv_anti_pop_part(void)

 {

 	unsigned start_time = jiffies;

 

-	__dlv_switch_sb(POWER_ON);

-	msleep(10);

+	if (first_start) {

+		first_start = 0;

+		__dlv_switch_sb(POWER_ON);

+		mdelay(300);

 

-	__dlv_switch_sb_sleep(POWER_ON);

-	msleep(10);

+		__dlv_switch_sb_sleep(POWER_ON);

+		mdelay(400);

+	}

 

 	__dlv_switch_sb_dac(POWER_ON);

 	udelay(500);

@@ -646,12 +712,18 @@ static void dlv_anti_pop_part(void)
  *

  * Perform an anti-pop startup sequence with msleep (block operation).

  */

+

 static void dlv_anti_pop_work_handler(struct work_struct *work)

 {

 	dlv_anti_pop_part();

-	turn_on_dac();

+	turn_on_dac(10);

 	__dlv_disable_hp_mute();

 

+#if 0

+	if(spk_state==1)

+		__gpio_set_pin(GPIO_SPK_SHUD);

+#endif

+

 #ifdef CONFIG_JZ4760_PT701

 	/* if headphone not attached */

 	if (!gstate_hp) {

@@ -847,7 +919,6 @@ static void dlv_anti_pop(int mode)
 	case CODEC_RMODE:

 		break;

 	case CODEC_WMODE:

-		printk(">>>>>>>>>>>>>>>>1: dlv_anti_pop\n");

 		/* Call work handler directly to anti-pop at system start.

 		 * Notice that this is block operation...

 		 * We use this way to ensure the operation of device openning

@@ -855,7 +926,6 @@ static void dlv_anti_pop(int mode)
 		 */

 		if (__dlv_get_sb_hp() != POWER_ON){

 			should_up = 1;

-			printk(">>>>>>>>>>>>>>>>2: dlv_anti_pop\n");

 			dlv_anti_pop_part();

 		}

 		break;

@@ -881,9 +951,21 @@ static void dlv_set_replay_volume(int val)
 	 * val = 95;

 	 */

 

-	fixed_vol = 30 * (100 - val) / 100;

+	fixed_vol = 6 +  (25 * (100 - val) / 100);

+#ifdef SNR_TEST

+	dlv_write_reg(0x10, 2);

+	dlv_write_reg(0x11, 2);

+#endif

 	__dlv_set_hp_volume(fixed_vol);

 

+	if (val == 0) {

+		__dlv_set_godr(0x1f | 0x80);

+		dlv_mute(1);

+	} else {

+		__dlv_set_godr(0x0 | 0x80);

+		dlv_mute(0);

+	}

+

 	DPRINT_CODEC("$$$$$ val = %d, DLV_REG_CGR1 = 0x%02x\n",

 		     val, dlv_read_reg(DLV_REG_GCR1));

 

@@ -896,9 +978,14 @@ static void dlv_set_mic_volume(int val)
 

 	ENTER();

 

+#ifdef JZDLV_USE_AGC

+	fixed_vol = 15 * (100 - val) / 100;

+	dlv_write_reg(0x15, (1 << 7) | (val << 2)); /* target: 0x0~0x3c */

+#else

 	fixed_vol = 31 * val / 100;

 	__dlv_set_gidr(fixed_vol | 0x80);

 	//__dlv_set_mic_1_volume(fixed_vol);

+#endif

 

 	LEAVE();

 }

@@ -913,7 +1000,6 @@ static void dlv_set_mic_volume(int val)
  */

 static void dlv_enable_hp_out(void)

 {

-	printk("[-- dlv route --] %s\n", __FUNCTION__);

 	__dlv_enable_nomad();

 	__dlv_disable_dac_right_only();

 	__dlv_set_outsel(DAC_OUTPUT);

@@ -923,6 +1009,7 @@ static void dlv_enable_hp_out(void)
 

 	__dlv_switch_sb_aip(POWER_ON);

 	mdelay(1);

+#if 0

 	__dlv_switch_sb(POWER_ON);

 	// reference up time

 	mdelay(300);

@@ -935,6 +1022,7 @@ static void dlv_enable_hp_out(void)
 	__dlv_disable_hp_mute();

 	mdelay(1);

 	turn_on_sb_hp();

+#endif

 

 //	mdelay(300);

 //	__dlv_disable_dac_mute();

@@ -946,10 +1034,9 @@ static void dlv_enable_hp_out(void)
  */

 static void dlv_disable_hp_out(void)

 {

-	printk("[-- dlv route --] %s\n", __FUNCTION__);

 	turn_off_sb_hp();

 	__dlv_enable_hp_mute();

-	turn_off_dac();

+	turn_off_dac(5);

 	//__dlv_switch_sb_dac(POWER_ON);

 	mdelay(10);

 }

@@ -960,7 +1047,6 @@ static void dlv_disable_hp_out(void)
  */

 static void dlv_enable_btl(void)

 {

-	printk("[-- dlv route --] %s\n", __FUNCTION__);

 	if (__dlv_get_sb_hp() != POWER_ON) {

 		__dlv_switch_sb_hp(POWER_ON);

 		dlv_sleep_wait_bitset(0xb, IFR_RUP, 100,__LINE__);

@@ -986,7 +1072,6 @@ static void dlv_enable_btl(void)
  */

 static void dlv_disable_btl(void)

 {

-	printk("[-- dlv route --] %s\n", __FUNCTION__);

 

 	__dlv_switch_sb_btl(POWER_OFF);

 	__dlv_switch_sb_line_out(POWER_OFF);

@@ -1000,7 +1085,6 @@ static void dlv_disable_btl(void)
  */

 static void dlv_enable_speaker(void)

 {

-	printk("[-- dlv route --] %s\n", __FUNCTION__);

 	dlv_enable_btl();

 }

 

@@ -1010,7 +1094,6 @@ static void dlv_enable_speaker(void)
  */

 static void dlv_disable_speaker(void)

 {

-	printk("[-- dlv route --] %s\n", __FUNCTION__);

 	dlv_disable_btl();

 

 }

@@ -1021,7 +1104,6 @@ static void dlv_disable_speaker(void)
  */

 static void dlv_enable_receiver(void)

 {

-	printk("[-- dlv route --] %s\n", __FUNCTION__);

 //	__dlv_set_16ohm_load();

 //	__dlv_set_10kohm_load();

 

@@ -1034,7 +1116,6 @@ static void dlv_enable_receiver(void)
  */

 static void dlv_disable_receiver(void)

 {

-	printk("[-- dlv route --] %s\n", __FUNCTION__);

 

 	dlv_disable_hp_out();

 }

@@ -1045,7 +1126,6 @@ static void dlv_disable_receiver(void)
  */

 static void dlv_enable_line_out(void)

 {

-	printk("[-- dlv route --] %s\n", __FUNCTION__);

 

 	__dlv_switch_sb_dac(POWER_ON);

 	if (__dlv_get_sb_hp() != POWER_ON) {

@@ -1072,20 +1152,62 @@ static void dlv_enable_line_out(void)
  */

 static void dlv_disable_line_out(void)

 {

-	printk("[-- dlv route --] %s\n", __FUNCTION__);

 	//DUMP_CODEC_REGS("after dlv_disable_line_out\n");

 }

 

 /**

  * Enable LINE IN record mode

+

  *

  * insel:	1	line in left channel

  * insel:	2	line in right channel

  * insel:	3	line in left & right channels

  */

+static void dlv_set_line(int val)

+{

+        int cur_vol;

+

+        ENTER();

+        /* set gain */

+        cur_vol = 31 * val / 100;

+        cur_vol &= 0x1f;

+        /* ???

+        dlv_write_reg(11, cur_vol);//GO1L

+        dlv_write_reg(12, cur_vol);//GO1R

+        */

+

+        dlv_write_reg(DLV_REG_GCR3, val);//GIL,GIR

+        dlv_write_reg(DLV_REG_GCR4, val);//GIL,GIR

+        LEAVE();

+}

+

+static void dlv_set_line_in(void)

+{

+        printk("[-- route --] %s\n", __FUNCTION__);

+

+        dlv_write_reg_bit(DLV_REG_CR2, 0, CR2_NOMAD);

+        dlv_write_reg_bit(DLV_REG_AGC1, 0, AGC1_AGCEN);//AGC1.AGC_EN->0

+        dlv_write_reg_bit(DLV_REG_CR3, 0, CR3_MICDIFF);

+        dlv_write_reg_bit(DLV_REG_PMR1, 0, PMR1_SB_AIP);

+

+        schedule_timeout(2);

+

+        dlv_write_reg_bit(DLV_REG_CR1, 1, CR1_BTL_MUTE);

+        dlv_write_reg_bit(DLV_REG_CR1, 1, CR1_LINEOUT_MUTE);

+        dlv_write_reg_bit(DLV_REG_PMR2, 1, PMR2_SB_LOUT);

+        dlv_write_reg_bit(DLV_REG_PMR2, 1, PMR2_SB_BTL);

+

+        switch_SB_LINE_IN(POWER_ON);

+        __dlv_set_insel(LINE_INPUT);

+

+        switch_SB_MIC1(POWER_OFF);

+        switch_SB_ADC(POWER_ON);

+}

+

+

+

 static void dlv_enable_line_in_record(int insel)

 {

-	printk("[-- dlv route --] %s\n", __FUNCTION__);

 

 	dlv_write_reg_bit(DLV_REG_AGC1, 0, AGC1_AGCEN);//AGC1.AGC_EN->0

 

@@ -1110,7 +1232,6 @@ static void dlv_enable_line_in_record(int insel)
  */

 static void dlv_disable_line_in_record(void)

 {

-	printk("[-- dlv route --] %s\n", __FUNCTION__);

 	//DUMP_CODEC_REGS("after dlv_disable_line_in\n");

 }

 

@@ -1121,7 +1242,6 @@ static void dlv_disable_line_in_record(void)
  */

 static void dlv_enable_line_in_bypass_hp(void)

 {

-	printk("[-- dlv route --] %s\n", __FUNCTION__);

 

 	// Yunfeng@Jul27'10 added for FM's audio path

 	__dlv_switch_sb(POWER_ON);

@@ -1154,7 +1274,6 @@ static void dlv_enable_line_in_bypass_hp(void)
  */

 static void dlv_disable_line_in_bypass_hp(void)

 {

-	printk("[-- dlv route --] %s\n", __FUNCTION__);

 }

 

 /**

@@ -1164,7 +1283,6 @@ static void dlv_disable_line_in_bypass_hp(void)
  */

 static void dlv_enable_line_in_bypass_btl(void)

 {

-	printk("[-- dlv route --] %s\n", __FUNCTION__);

 

 	__dlv_switch_sb(POWER_ON);

 	__dlv_switch_sb_sleep(POWER_ON);

@@ -1199,7 +1317,6 @@ static void dlv_enable_line_in_bypass_btl(void)
  */

 static void dlv_disable_line_in_bypass_btl(void)

 {

-	printk("[-- dlv route --] %s\n", __FUNCTION__);

 

 	__dlv_set_outsel(DAC_OUTPUT);

 	__dlv_switch_sb_bypass(POWER_OFF);

@@ -1231,9 +1348,9 @@ static void dlv_disable_rec_2_dac(void)
  */

 static void dlv_enable_mic_2(void)

 {

+	static int first = 1;

 	ENTER();

 

-	printk("[-- dlv route --] %s\n", __FUNCTION__);

 

 	dlv_write_reg(DLV_REG_CCR2, 0x29);

 

@@ -1262,22 +1379,51 @@ static void dlv_enable_mic_2(void)
 	__dlv_enable_mic_diff();

 #endif

 

+	__dlv_enable_mic_diff();

+

 	/* For z800, main MIC is connected to MIC2 of JZ4760 */

 	__dlv_set_insel(MIC2_TO_LR);

 

 	__dlv_set_mic_mono();

 

 	__dlv_enable_adc_right_only();

-

+#if 0

 	/* Depend on board situation. For z800, we set max. */

+#if 0

+	/* max */

 	__dlv_set_gim(0x3f);

 	__dlv_set_gidr(0x9f);

+#endif

+

+#if 1

+	/* for record test */

+	__dlv_set_gim(0x3f);

+	__dlv_set_gidr(0x80);

+#endif

+

+#if 0

+	/* min */

+	__dlv_set_gim(0x0);

+	__dlv_set_gidr(0x8f);

+	//__dlv_set_gidr(0x80);

+	//__dlv_set_gidl(0x0);

+#endif

+#endif

 

 	__dlv_switch_sb_mic2(POWER_ON);

 

-	__dlv_disable_agc();

+	if (first) {

+		dlv_write_reg(0x15, 0x0); /* target: 0x0~0x3c */

+		dlv_write_reg(0x16, (1 << 7) | (0x2<< 4) | dlv_read_reg(0x16));  /* noise gate[7 6:4] & hold[3:0] */

+		dlv_write_reg(0x17, 0x0);			   /* ATK[7:4] and DCY[3:0] */

+		dlv_write_reg(0x18, 0x1f);			   /* AGC_MAX */

+		dlv_write_reg(0x19, 0x0);			   /* AGC_MIN */

+		first = 0;

+	}

+	//__dlv_disable_agc();

+	__dlv_enable_agc();

 

-	dump_dlv_regs("enable mic2");

+//	dump_dlv_regs("enable mic2");

 

 	//DUMP_CODEC_REGS("leave dlv_enable_mic_2\n");

 	//dump_dlv_regs("leave dlv_enable_mic_2\n");

@@ -1290,7 +1436,6 @@ static void dlv_enable_mic_2(void)
  */

 static void dlv_disable_mic_2(void)

 {

-	printk("[-- dlv route --] %s\n", __FUNCTION__);

 	__dlv_switch_sb_mic2(POWER_OFF);

 	//DUMP_CODEC_REGS("leave dlv_disable_mic_2\n");

 }

@@ -1303,7 +1448,6 @@ static void dlv_enable_mic_1(void)
 {

 	ENTER();

 

-	printk("[-- dlv route --] %s\n", __FUNCTION__);

 

 	dlv_write_reg(DLV_REG_CCR2, 0x29);

 

@@ -1350,6 +1494,12 @@ static void dlv_enable_mic_1(void)
 	__dlv_set_gidr(0x9f);

 #endif

 

+#if 0

+	/* for record test */

+	__dlv_set_gim(0x3f);

+	__dlv_set_gidr(0x80);

+#endif

+

 #if 1

 	/* min */

 	__dlv_set_gim(0x0);

@@ -1362,7 +1512,7 @@ static void dlv_enable_mic_1(void)
 

 	__dlv_disable_agc();

 

-	dump_dlv_regs("enable mic1");

+//	dump_dlv_regs("enable mic1");

 

 	//DUMP_CODEC_REGS("leave dlv_enable_mic_2\n");

 	//dump_dlv_regs("leave dlv_enable_mic_2\n");

@@ -1375,7 +1525,6 @@ static void dlv_enable_mic_1(void)
  */

 static void dlv_disable_mic_1(void)

 {

-	printk("[-- dlv route --] %s\n", __FUNCTION__);

 	__dlv_switch_sb_mic1(POWER_OFF);

 	//DUMP_CODEC_REGS("leave dlv_disable_mic_1\n");

 }

@@ -1389,7 +1538,6 @@ static void dlv_disable_mic_1(void)
  */

 static void dlv_set_device(struct snd_device_config *snd_dev_cfg)

 {

-	printk("[-- dlv route --] %s\n", __FUNCTION__);

 

 	dlv_enable_hp_out();

 //	__dlv_disable_hp_mute();

@@ -1449,8 +1597,6 @@ static void dlv_set_device(struct snd_device_config *snd_dev_cfg)
 #if 0

 static void dlv_set_device(struct snd_device_config *snd_dev_cfg)

 {

-	printk("[-- dlv route --] %s\n", __FUNCTION__);

-

 	switch (snd_dev_cfg->device) {

 	case SND_DEVICE_HANDSET:

 		dlv_enable_receiver();

@@ -1572,6 +1718,8 @@ static void dlv_resume(void)
 static int jzdlv_ioctl(void *context, unsigned int cmd, unsigned long arg)

 {

 	int ret = 0;

+	int start_jiffies = 0;

+	int end_jiffies = 0;

 	ENTER();

 	DUMP_CODEC_REGS(__FUNCTION__);

 	DPRINT_CODEC("[dlv IOCTL]++++++++++++++++++++++++++++\n");

@@ -1584,8 +1732,12 @@ static int jzdlv_ioctl(void *context, unsigned int cmd, unsigned long arg)
 	switch (cmd) {

 	case CODEC_FIRST_OUTPUT:

 //		dlv_set_replay_volume(greplay_volume);

-		__dlv_disable_dac_mute();

+		//__dlv_disable_dac_mute();

+		start_jiffies = jiffies;

+		turn_on_dac(5);

 		__dlv_disable_hp_mute();

+		end_jiffies = jiffies;

+		printk("turn on DAC_MUTE duration: %d\n", end_jiffies - start_jiffies);

 		break;

 

 	case CODEC_INIT:

@@ -1646,6 +1798,12 @@ static int jzdlv_ioctl(void *context, unsigned int cmd, unsigned long arg)
 		break;

 

 	case CODEC_SET_RECORD:

+#if 0

+		if (arg == USE_LINEIN)

+			dlv_set_line_in();

+		else if (arg == USE_MIC)

+			board_set_record();

+#endif

 		board_set_record();

 		break;

 

@@ -1678,9 +1836,7 @@ static int jzdlv_ioctl(void *context, unsigned int cmd, unsigned long arg)
 		break;

 

 	case CODEC_SET_LINE:

-		//dlv_set_line(arg);

-		printk("JZ DLV: should not run here -- CODEC_SET_LINE\n");

-		BUG_ON(1);

+		dlv_set_line(arg);

 		break;

 

 	case CODEC_EACH_TIME_INIT:

@@ -1897,7 +2053,7 @@ _ensure_stable:
 		}

 	}

 

-	spin_lock_irqsave(dlv_irq_lock, flags);

+	spin_lock_irqsave(&dlv_irq_lock, flags);

 

 	/* Clear current irq flag */

 	__dlv_set_irq_flag(dlv_ifr);

@@ -1905,7 +2061,7 @@ _ensure_stable:
 	/* Unmask SCMC & JACK (ifdef HP_SENSE_DETECT) */

 	__dlv_set_irq_mask(ICR_COMMON_MASK);

 

-	spin_unlock_irqrestore(dlv_irq_lock, flags);

+	spin_unlock_irqrestore(&dlv_irq_lock, flags);

 

 	/* If the jack status has changed, we have to redo the process. */

 	if (dlv_ifr & (1 << IFR_JACKE)) {

@@ -1934,7 +2090,7 @@ static irqreturn_t dlv_codec_irq(int irq, void *dev_id)
 	unsigned int aic_reg;

 	unsigned long flags;

 

-	spin_lock_irqsave(dlv_irq_lock, flags);

+	spin_lock_irqsave(&dlv_irq_lock, flags);

 

 	dlv_ifr = __dlv_get_irq_flag();

 	dlv_icr = __dlv_get_irq_mask();

@@ -1957,12 +2113,12 @@ static irqreturn_t dlv_codec_irq(int irq, void *dev_id)
 		/* Unmask SCMC & JACK (ifdef HP_SENSE_DETECT) */

 //		__dlv_set_irq_mask(ICR_COMMON_MASK);

 

-		spin_unlock_irqrestore(dlv_irq_lock, flags);

+		spin_unlock_irqrestore(&dlv_irq_lock, flags);

 		return IRQ_HANDLED;

 

 	} else {

 

-		spin_unlock_irqrestore(dlv_irq_lock, flags);

+		spin_unlock_irqrestore(&dlv_irq_lock, flags);

 

 		if (handling_scmc == 0) {

 			handling_scmc = 1;

@@ -2023,7 +2179,7 @@ static irqreturn_t dlv_codec_irq(int irq, void *dev_id)
 	unsigned int aic_reg;

 	unsigned long flags;

 

-	spin_lock_irqsave(dlv_irq_lock, flags);

+	spin_lock_irqsave(&dlv_irq_lock, flags);

 

 	dlv_ifr = __dlv_get_irq_flag();

 	dlv_icr = __dlv_get_irq_mask();

@@ -2046,11 +2202,11 @@ static irqreturn_t dlv_codec_irq(int irq, void *dev_id)
 		/* Unmask SCMC & JACK (ifdef HP_SENSE_DETECT) */

 		__dlv_set_irq_mask(ICR_COMMON_MASK);

 

-		spin_unlock_irqrestore(dlv_irq_lock, flags);

+		spin_unlock_irqrestore(&dlv_irq_lock, flags);

 		return IRQ_HANDLED;

 

 	} else {

-		spin_unlock_irqrestore(dlv_irq_lock, flags);

+		spin_unlock_irqrestore(&dlv_irq_lock, flags);

 

 		/* Handle SCMC and JACK in work queue. */

 		schedule_work(&dlv_irq_work);

@@ -2140,6 +2296,8 @@ static int __init init_dlv(void)
 {

 	int retval;

 

+	printk("=====>enter %s\n", __func__);

+

 

 	cpm_start_clock(CGM_AIC);

 

diff --git a/sound/oss/jz4760_i2s.c b/sound/oss/jz4760_i2s.c
index 4da5607915e..15d75e684c8 100644
--- a/sound/oss/jz4760_i2s.c
+++ b/sound/oss/jz4760_i2s.c
@@ -1,3050 +1,3123 @@
-/*

- * Linux/sound/oss/jz_i2s.c

- *

- * Sound driver for Ingenic Jz4750 MIPS processor

- *

- * 2009-12-xx	Steven <dsqiu@ingenic.cn>

- * 2010-01-xx	Jason <xwang@ingenic.cn>

- *

- * Copyright (c) Ingenic Semiconductor Co., Ltd.

- */

-

-#include <linux/init.h>

-#include <linux/interrupt.h>

-#include <linux/pm.h>

-#include <linux/sched.h>

-#include <linux/delay.h>

-#include <linux/sound.h>

-#include <linux/slab.h>

-#include <sound/core.h>

-#include <sound/initval.h>

-#include <linux/proc_fs.h>

-#include <linux/soundcard.h>

-#include <linux/dma-mapping.h>

-#include <linux/mutex.h>

-#include <linux/mm.h>

-#include <asm/hardirq.h>

-#include <asm/jzsoc.h>

-#include "sound_config.h"

-

-#include <linux/miscdevice.h>

-#include <linux/platform_device.h>

-//#include <linux/msm_audio.h>

-#include "jz_codec.h"

-#include "jz_i2s_dbg.h"

-

-//#if defined CONFIG_PM

-//#undef CONFIG_PM

-//#endif

-

-#define DMA_ID_I2S_TX			DMA_ID_AIC_TX

-#define DMA_ID_I2S_RX			DMA_ID_AIC_RX

-

-// reference to dma.c

-#define DMA_TX_CHAN			6

-#define DMA_RX_CHAN			7

-

-#define NR_I2S				2

-

-#define JZCODEC_RW_BUFFER_SIZE		1

-#define JZCODEC_RW_BUFFER_TOTAL		4

-

-#define AUDIOBUF_STATE_FREE		0

-

-#define NOMAL_STOP			0

-#define FORCE_STOP			1

-#define PIPE_TRANS			1

-

-#define AUDIO_LOCK(lock, flags)		spin_lock_irqsave(lock, flags)

-#define AUDIO_UNLOCK(lock, flags)	spin_unlock_irqrestore(lock, flags)

-

-#define THIS_AUDIO_NODE(p)		list_entry(p, audio_node, list)

-#define ALIGN_PAGE_SIZE(x)		(((x) + PAGE_SIZE) / PAGE_SIZE * PAGE_SIZE)

-

-typedef struct {

-	struct list_head list;

-	unsigned int pBuf;

-#ifdef Q_DEBUG

-	unsigned int pBufID;

-#endif

-	unsigned int start;

-	unsigned int end;

-	unsigned int phyaddr;

-} audio_node;

-

-typedef struct {

-	unsigned int fact;

-	unsigned int datasize;

-	unsigned int listsize;

-	struct list_head free;

-	struct list_head use;

-} audio_head;

-

-typedef struct

-{

-	int ch;

-	int onetrans_bit;

-	int rw;

-	unsigned int *trans_addr;

-	unsigned int *trans_count;

-	unsigned int *trans_mode;

-	unsigned int *data_addr;

-} audio_dma_type;

-

-typedef struct __audio_pipe

-{

-	spinlock_t	lock;

-	audio_dma_type	dma;

-	unsigned int	*mem;

-	audio_node	*savenode;

-

-	int	fragsize;

-	int 	fragstotal;

-	int	is_non_block;

-	volatile int	trans_state;

-

-	wait_queue_head_t	q_full;

-	int			avialable_couter;

-

-#ifdef WORK_QUEUE_MODE

-	struct work_struct	work;

-#endif

-	void (*handle)(struct __audio_pipe *endpoint);

-	int (*filter)(void *buff, int cnt);

-} audio_pipe;

-

-struct i2s_codec

-{

-	/* I2S controller connected with */

-	void	*private_data;

-	char	*name;

-	int	id;

-	int	dev_mixer;

-

-	int	use_mic_line_flag;

-	int	audio_volume;

-	int	mic_gain;

-	int	bass_gain;

-

-	unsigned short	record_audio_rate;

-	unsigned short	replay_audio_rate;

-

-	short	replay_codec_channel;

-	short	record_codec_channel;

-

-	short	replay_format;

-	short	record_format;

-

-	int	audiomute;

-	int	user_need_mono;

-

-	struct semaphore i2s_sem;

-	int (*codecs_ioctrl)(void *context, unsigned int cmd, unsigned long arg);

-};

-

-struct jz_i2s_controller_info

-{

-	char		*name;

-	audio_pipe	*pout_endpoint;

-	audio_pipe	*pin_endpoint;

-	int		dev_audio;

-	unsigned int	error;	/* over / underrun */

-

-	struct i2s_codec *i2s_codec;

-

-#ifdef CONFIG_PM

-	struct pm_dev	*pm;

-#endif

-};

-

-

-/*

- * Global variates

- */

-static audio_pipe out_endpoint = {

-	.mem		= 0,

-	.savenode	= 0,

-	.fragsize	= 0,

-	.fragstotal	= 0,

-	.trans_state	= 0,

-};

-

-static audio_pipe in_endpoint= {

-	.mem		= 0,

-	.savenode	= 0,

-	.fragsize	= 0,

-	.fragstotal	= 0,

-	.trans_state	= 0,

-};

-

-static struct i2s_codec the_codecs[NR_I2S];

-static struct jz_i2s_controller_info *the_i2s_controller = NULL;

-static int audio_mix_modcnt = 0;

-static audio_node *last_read_node = NULL;

-static int g_play_first = 0;

-

-/*

- * Debug functions

- */

-#ifdef DMA_DEBUG

-void dump_dma(unsigned int dmanr, const char *str)

-{

-	printk("DMA%d Registers, %s:\n", dmanr, str);

-	printk("\tDMACR	= 0x%08x\n", REG_DMAC_DMACR(dmanr/HALF_DMA_NUM));

-	printk("\tDSAR	= 0x%08x\n", REG_DMAC_DSAR(dmanr));

-	printk("\tDTAR	= 0x%08x\n", REG_DMAC_DTAR(dmanr));

-	printk("\tDTCR	= 0x%08x\n", REG_DMAC_DTCR(dmanr));

-

-	*(unsigned int *)0xb342010c = 0x18;

-

-	printk("\tDRSR	= 0x%08x, addr = 0x%08x\n", REG_DMAC_DRSR(dmanr), DMAC_DRSR(dmanr));

-	printk("\tDCCSR	= 0x%08x\n", REG_DMAC_DCCSR(dmanr));

-	printk("\tDCMD	= 0x%08x\n", REG_DMAC_DCMD(dmanr));

-	printk("\tDDA	= 0x%08x\n", REG_DMAC_DDA(dmanr));

-	printk("\tDMADBR= 0x%08x\n", REG_DMAC_DMADBR(dmanr/HALF_DMA_NUM));

-	printk("\tCPCCR = 0x%08x\n", REG_CPM_CPCCR);

-	printk("\tCPPCR = 0x%08x\n", REG_CPM_CPPCR0);

-	printk("\tREG_CPM_CLKGR0 = 0x%08x\n", REG_CPM_CLKGR0);

-	printk("\tREG_CPM_CLKGR1 = 0x%08x\n", REG_CPM_CLKGR1);

-}

-#endif

-

-#ifdef IOC_DEBUG

-void dsp_print_ioc_cmd(int cmd)

-{

-	int i;

-	int cmd_arr[] = {

-		OSS_GETVERSION,		SNDCTL_DSP_RESET,	SNDCTL_DSP_SYNC,

-		SNDCTL_DSP_SPEED,	SNDCTL_DSP_STEREO,	SNDCTL_DSP_GETBLKSIZE,

-		SNDCTL_DSP_GETFMTS,	SNDCTL_DSP_SETFMT,	SNDCTL_DSP_CHANNELS,

-		SNDCTL_DSP_POST,	SNDCTL_DSP_SUBDIVIDE,	SNDCTL_DSP_SETFRAGMENT,

-		SNDCTL_DSP_GETCAPS,	SNDCTL_DSP_NONBLOCK,	SNDCTL_DSP_SETDUPLEX,

-		SNDCTL_DSP_GETOSPACE,	SNDCTL_DSP_GETISPACE,	SNDCTL_DSP_GETTRIGGER,

-		SNDCTL_DSP_SETTRIGGER,	SNDCTL_DSP_GETIPTR,	SNDCTL_DSP_GETOPTR,

-		SNDCTL_DSP_GETODELAY,	SOUND_PCM_READ_RATE,	SOUND_PCM_READ_CHANNELS,

-		SOUND_PCM_READ_BITS,	SNDCTL_DSP_MAPINBUF,	SNDCTL_DSP_MAPOUTBUF,

-		SNDCTL_DSP_SETSYNCRO,	SOUND_PCM_READ_FILTER,	SOUND_PCM_WRITE_FILTER,

-//		AUDIO_GET_CONFIG,	AUDIO_SET_CONFIG

-	};

-	char *cmd_str[] = {

-		"OSS_GETVERSION",	"SNDCTL_DSP_RESET",	"SNDCTL_DSP_SYNC",

-		"SNDCTL_DSP_SPEED",	"SNDCTL_DSP_STEREO",	"SNDCTL_DSP_GETBLKSIZE",

-		"SNDCTL_DSP_GETFMTS",	"SNDCTL_DSP_SETFMT",	"SNDCTL_DSP_CHANNELS",

-		"SNDCTL_DSP_POST",	"SNDCTL_DSP_SUBDIVIDE",	"SNDCTL_DSP_SETFRAGMENT",

-		"SNDCTL_DSP_GETCAPS",	"SNDCTL_DSP_NONBLOCK",	"SNDCTL_DSP_SETDUPLEX",

-		"SNDCTL_DSP_GETOSPACE",	"SNDCTL_DSP_GETISPACE",	"SNDCTL_DSP_GETTRIGGER",

-		"SNDCTL_DSP_SETTRIGGER","SNDCTL_DSP_GETIPTR",	"SNDCTL_DSP_GETOPTR",

-		"SNDCTL_DSP_GETODELAY",	"SOUND_PCM_READ_RATE",	"SOUND_PCM_READ_CHANNELS",

-		"SOUND_PCM_READ_BITS",	"SNDCTL_DSP_MAPINBUF",	"SNDCTL_DSP_MAPOUTBUF",

-		"SNDCTL_DSP_SETSYNCRO",	"SOUND_PCM_READ_FILTER","SOUND_PCM_WRITE_FILTER",

-//		"AUDIO_GET_CONFIG",	"AUDIO_SET_CONFIG"

-	};

-

-	for ( i = 0; i < sizeof(cmd_arr) / sizeof(int); i++) {

-		if (cmd_arr[i] == cmd) {

-			printk("Command name : %s\n", cmd_str[i]);

-			return;

-		}

-	}

-

-	if (i == sizeof(cmd_arr) / sizeof(int)) {

-		printk("Unknown command\n");

-	}

-}

-

-void mixer_print_ioc_cmd(int cmd)

-{

-	int i;

-	int cmd_arr[] = {

-		SOUND_MIXER_INFO,	SOUND_OLD_MIXER_INFO,		SOUND_MIXER_READ_STEREODEVS,

-		SOUND_MIXER_READ_CAPS,	SOUND_MIXER_READ_DEVMASK,	SOUND_MIXER_READ_RECMASK,

-		SOUND_MIXER_READ_RECSRC,SOUND_MIXER_WRITE_SPEAKER,	SOUND_MIXER_WRITE_BASS,

-		SOUND_MIXER_READ_BASS,	SOUND_MIXER_WRITE_VOLUME,	SOUND_MIXER_READ_VOLUME,

-		SOUND_MIXER_WRITE_MIC,	SOUND_MIXER_READ_MIC,		SOUND_MIXER_WRITE_LINE,

-		SOUND_MIXER_READ_LINE,	SOUND_MIXER_WRITE_MUTE,		SOUND_MIXER_READ_MUTE,

-//		SND_SET_DEVICE,		SND_SET_VOLUME,

-//		SND_GET_NUM_ENDPOINTS,	SND_GET_ENDPOINT

-	};

-

-	char *cmd_str[] = {

-		"SOUND_MIXER_INFO",		"SOUND_OLD_MIXER_INFO",		"SOUND_MIXER_READ_STEREODEVS",

-		"SOUND_MIXER_READ_CAPS",	"SOUND_MIXER_READ_DEVMASK",	"SOUND_MIXER_READ_RECMASK",

-		"SOUND_MIXER_READ_RECSRC",	"SOUND_MIXER_WRITE_SPEAKER",	"SOUND_MIXER_WRITE_BASS",

-		"SOUND_MIXER_READ_BASS",	"SOUND_MIXER_WRITE_VOLUME",	"SOUND_MIXER_READ_VOLUME",

-		"SOUND_MIXER_WRITE_MIC",	"SOUND_MIXER_READ_MIC",		"SOUND_MIXER_WRITE_LINE",

-		"SOUND_MIXER_READ_LINE",	"SOUND_MIXER_WRITE_MUTE",	"SOUND_MIXER_READ_MUTE",

-//		"SND_SET_DEVICE",		"SND_SET_VOLUME",

-//		"SND_GET_NUM_ENDPOINTS",	"SND_GET_ENDPOINT"

-	};

-

-	for (i = 0; i < sizeof(cmd_arr) / sizeof(int); i++) {

-		if (cmd_arr[i] == cmd) {

-			printk("Command name : %s\n", cmd_str[i]);

-			return;

-		}

-	}

-

-	printk("Unknown command\n");

-}

-#endif

-

-//#ifdef REG_DEBUG

-void dump_aic_regs(const char *str)

-{

-	char *regname[] = {"aicfr","aiccr","aiccr1","aiccr2","i2scr","aicsr","acsr","i2ssr"};

-	int i;

-	unsigned int addr;

-

-	printk("AIC regs dump, %s\n", str);

-	for (i = 0; i < 0x1c; i += 4) {

-		addr = 0xb0020000 + i;

-		printk("%s\t0x%08x -> 0x%08x\n", regname[i/4], addr, *(unsigned int *)addr);

-	}

-}

-//#endif

-

-#ifdef BUF_DEBUG

-void dump_buf(char *buf, int dump_len, int bytes_in_line)

-{

-	int i;

-	printk("Buffer 0x%p:\n", buf);

-	for (i = 0; i < dump_len; i++) {

-		printk("%02x ", (unsigned char)buf[i]);

-		if ((i+1) % bytes_in_line == 0) {

-			printk("\n");

-		}

-	}

-	printk("\n");

-}

-#endif

-

-#ifdef Q_DEBUG

-void dump_node(audio_node *node, const char *str)

-{

-	if (!node || !str) {

-		printk("DUMP_NODE: detected argument is NULL\n");

-		return;

-	}

-

-	printk("%s: addr(0x%08x) id=%d, pBuf=0x%08x, start=0x%08x, end=0x%08x, phyaddr=0x%08x\n",

-	       str, (unsigned int)node, node->pBufID, node->pBuf, node->start, node->end, node->phyaddr);

-}

-

-void dump_list(audio_head *head)

-{

-	audio_node *tmp;

-	struct list_head *p, *n;

-

-	BUG_ON(!head);

-

-	printk("--------\nAudio head info: fact = %d, datasize = %d, listsize = %d\n",

-	       head->fact, head->datasize, head->listsize);

-

-	printk("free q:\n");

-	list_for_each_safe(p, n, &head->free) {

-		tmp = list_entry(p, audio_node, list);

-		DUMP_NODE(tmp, "fQ");

-	}

-	printk("use q:\n");

-	list_for_each_safe(p, n, &head->use) {

-		tmp = list_entry(p, audio_node, list);

-		DUMP_NODE(tmp, "uQ");

-	}

-	printk("--------\n");

-}

-#endif

-

-//----------------------------------------------------------------

-// audio node operater

-// int init_audio_node(unsigned int **memory, unsigned int pagesize, unsigned int count)

-// void deinit_audio_node(unsigned int **memory)

-// static inline audio_node *get_audio_freenode(unsigned int *mem)

-// static inline void put_audio_usenode(unsigned int *mem, audio_node *node)

-// static inline audio_node *get_audio_usenode(unsigned int *mem)

-// static inline void put_audio_freenode(unsigned int *mem, audio_node *node)

-// static inline int get_audio_freenodecount(unsigned int *mem)

-//

-//----------------------------------------------------------------

-

-void deinit_audio_node(unsigned int **memory)

-{

-	audio_head	*phead;

-	unsigned int	fact;

-

-	phead = (audio_head *)*memory;

-	fact = phead->fact;

-	free_pages((unsigned long)*memory, fact);

-	*memory = NULL;

-}

-

-int init_audio_node(unsigned int **memory, unsigned int pagesize, unsigned int count)

-{

-	unsigned int	fact;

-	audio_node	*pbuff;

-	audio_head	*phead;

-	unsigned int	*mem;

-	struct list_head *audio_wfree;

-	struct list_head *audio_wuse;

-	int	memsize;

-	int	datasize;

-	int	headlistsize;

-	int	i;

-

-	ENTER();

-

-	// Alloc memory first, to avail fail

-	datasize	= ALIGN_PAGE_SIZE(pagesize * count);

-	headlistsize	= ALIGN_PAGE_SIZE(count * sizeof(audio_node) + sizeof(audio_head));

-	memsize		= headlistsize + datasize;

-	fact		= get_order(memsize);

-

-	mem = (unsigned int *)__get_free_pages(GFP_KERNEL | GFP_DMA, fact);

-	if (mem == NULL) {

-		printk("JZ I2S: Memory allocation failed in function init_audio_node!\n");

-		return 0;

-	}

-

-	DPRINT("Mem alloc finish! memsize = %x, fact = %d, mem = 0x%08x\n",

-	       memsize, fact, (unsigned int)mem);

-

-	// Free old buffer

-	if (*memory) {

-		phead	= (audio_head *)*memory;

-		fact	= phead->fact;

-		free_pages((unsigned long)*memory, fact);

-		*memory	= NULL;

-	}

-	*memory = mem;

-

-/*

-	datasize	= ALIGN_PAGE_SIZE(pagesize * count);

-	headlistsize	= ALIGN_PAGE_SIZE(count * sizeof(audio_node) + sizeof(audio_head)); //8byte is save head data

-	memsize		= headlistsize + datasize;

-

-	fact = get_order(memsize);

-*/

-

-	// Update list head

-	phead		= (audio_head *)*memory;

-	phead->fact	= fact;

-	phead->listsize	= headlistsize;

-	phead->datasize	= datasize;

-

-	audio_wuse	= &(phead->use);

-	audio_wfree	= &(phead->free);

-	INIT_LIST_HEAD(audio_wuse);

-	INIT_LIST_HEAD(audio_wfree);

-

-	pbuff = (audio_node *)((unsigned int)*memory + sizeof(audio_head));

-	for (i = 0; i < count; i++) {

-		pbuff->pBuf	= (unsigned int)*memory + headlistsize + pagesize * i;

-		pbuff->phyaddr	= (unsigned int)virt_to_phys((void *)pbuff->pBuf);

-		pbuff->start	= 0;

-		pbuff->end	= 0;

-#ifdef Q_DEBUG

-		pbuff->pBufID	= i;

-#endif

-		DPRINT_Q("audio_note buffer[%d] = %x\n", i, (unsigned int)pbuff->pBuf);

-		list_add(&pbuff->list, audio_wfree);

-		pbuff++;

-	}

-

-	DUMP_LIST(phead);

-

-	LEAVE();

-	return 1;

-}

-

-#define is_null_free_audio_node(mem)				\

-({								\

-	audio_head *phead = (audio_head *)(mem);		\

-	struct list_head *pfree = &(phead->pfree);		\

-	(pfree->next == pfree);					\

-})

-

-#define is_null_use_audio_node(mem)				\

-({								\

-	audio_head *phead = (audio_head *)mem;			\

-	struct list_head *puse = &(phead->use);			\

-	(puse->next == puse);					\

-})

-

-//static unsigned int putid = 0, getid = 0;

-

-static inline audio_node *get_audio_freenode(unsigned int *mem)

-{

-	audio_head	 *phead;

-	audio_node	 *node = NULL;

-	struct list_head *pfree;

-	struct list_head *curnode;

-

-	phead	= (audio_head *)mem;

-	pfree	= &(phead->free);

-	curnode	= pfree->next;

-

-	if (curnode != pfree) {

-		node = THIS_AUDIO_NODE(curnode);

-		node->start = 0;

-		node->end = 0;

-		list_del(curnode);

-	}

-	return node;

-}

-

-static inline void put_audio_usenode(unsigned int *mem, audio_node *node)

-{

-	audio_head *phead = (audio_head *)mem;

-	struct list_head *puse = &(phead->use);

-	struct list_head *curnode = &(node->list);

-

-	list_add_tail(curnode, puse);

-}

-

-static inline audio_node *get_audio_usenode(unsigned int *mem)

-{

-	audio_head	 *phead;

-	audio_node	 *node = NULL;

-	struct list_head *curnode;

-	struct list_head *puse;

-

-	phead	= (audio_head *)mem;

-	puse	=  &(phead->use);

-	curnode	= puse->next;

-

-	if (curnode != puse) {

-		node = THIS_AUDIO_NODE(curnode);

-		list_del(curnode);

-	}

-	return node;

-}

-

-static inline void put_audio_freenode(unsigned int *mem, audio_node *node)

-{

-	audio_head *phead = (audio_head *)mem;

-	struct list_head *pfree = &(phead->free);

-	struct list_head *curnode = &(node->list);

-

-	list_add_tail(curnode, pfree);

-}

-

-static inline int get_audio_freenodecount(unsigned int *mem)

-{

-	struct list_head *pfree;

-	struct list_head *plist;

-	audio_head *phead;

-	int count = 0;

-

-	phead = (audio_head *)mem;

-	pfree =  &(phead->free);

-	plist = pfree;

-	while (plist->next != pfree) {

-		count++;

-		plist = plist->next;

-	}

-	return count;

-}

-

-//--------------------------------------------------------------------

-// end audio node operater

-//--------------------------------------------------------------------

-

-//--------------------------------------------------------------------

-// static irqreturn_t jz_i2s_dma_irq (int irq, void *dev_id)

-// int init_audio_recorddma(audio_pipe *endpoint)

-// int init_audio_replaydma(audio_pipe *endpoint)

-// int init_audio_audiodma(audio_pipe *endpoint, int mode)

-// void config_dma_trans_mode(spinlock_t lock, audio_dma_type* dma, int mode)

-// static inline int audio_trystart_dma_node(audio_dma_type* dma, audio_node *node)

-// static inline int audio_trystart_dma_node(audio_dma_type* dma, audio_node *node)

-// static inline void audio_stop_dma_node(audio_dma_type* dma)

-

-static irqreturn_t jz_i2s_dma_irq (int irq, void *dev_id)

-{

-	audio_pipe * endpoint = (audio_pipe *) dev_id;

-	int dma_chan = endpoint->dma.ch;

-	int dma_state = REG_DMAC_DCCSR(dma_chan);

-	int err = 0;

-

-	ENTER();

-

-	REG_DMAC_DCCSR(dma_chan) = 0;

-

-	DPRINT_IRQ("!!!! endpoint direct = %s \n",(endpoint == &out_endpoint) ? "out" : "in");

-

-	if (dma_state & DMAC_DCCSR_HLT) {

-		err = 0;

-		DPRINT_IRQ("!!!! DMA HALT\n");

-	}

-	if (dma_state & DMAC_DCCSR_AR) {

-		err = 1;

-		DPRINT_IRQ("!!!! DMA ADDR ERROR\n");

-	}

-	if (dma_state & DMAC_DCCSR_CT) {

-		DPRINT_IRQ("!!!! DMA descriptor finish\n");

-	}

-	/*

-	if (dma_state & DMA_DCCSR_TT) {

-

-	}

-	*/

-	if (err == 0) {

-		//printk("schedule_work++++ %x %x\n", endpoint,&(endpoint->work));

-		//schedule_work(&(endpoint->work));

-		//printk("schedule_work----\n");

-		endpoint->handle(endpoint);

-	} else {

-		DPRINT_IRQ("!!!! ??? unknown !!!\n");

-	}

-

-	LEAVE();

-

-	return IRQ_HANDLED;

-}

-

-static int jz_request_aic_dma(int dev_id, const char *dev_str,

-			      irqreturn_t (*irqhandler)(int, void *),

-			      unsigned long irqflags, void *irq_dev_id)

-{

-	struct jz_dma_chan *chan;

-	int i, ret;

-

-	if (dev_id == DMA_ID_AIC_TX) {

-		i = DMA_TX_CHAN;

-		if (jz_dma_table[i].dev_id != DMA_ID_AIC_TX) {

-			BUG_ON(1);

-		}

-	} else if (dev_id == DMA_ID_AIC_RX) {

-		i = DMA_RX_CHAN;

-		if (jz_dma_table[i].dev_id != DMA_ID_AIC_RX) {

-			BUG_ON(1);

-		}

-	} else {

-		BUG_ON(1);

-	}

-

-	/* we got channel */

-	chan = &jz_dma_table[i];

-

-	if (irqhandler) {

-		chan->irq = IRQ_DMA_0 + i;

-		chan->irq_dev = irq_dev_id;

-		if ((ret = request_irq(chan->irq, irqhandler, irqflags,

-				       dev_str, chan->irq_dev))) {

-			chan->irq = -1;

-			chan->irq_dev = NULL;

-			return ret;

-		}

-	} else {

-		chan->irq = -1;

-		chan->irq_dev = NULL;

-	}

-/*

-	printk("\n@@@@ %s:%d chan index = %d, chan.irq = %d\n\n",

-	       __FUNCTION__, __LINE__, i, chan->irq);

-*/

-	chan->io	= i;

-	chan->dev_id	= dev_id;

-	chan->dev_str	= dev_str;

-	chan->fifo_addr	= CPHYSADDR(AIC_DR);

-

-	switch (dev_id) {

-	case DMA_ID_AIC_TX:

-		chan->mode	= DMA_AIC_TX_CMD_UNPACK | DMA_MODE_WRITE;

-		chan->source	= DMAC_DRSR_RS_AICOUT;

-		break;

-	case DMA_ID_AIC_RX:

-		chan->mode	= DMA_32BIT_RX_CMD | DMA_MODE_READ;

-		chan->source	= DMAC_DRSR_RS_AICIN;

-		break;

-	default:

-		printk("JZ AIC: %s:%d, need fix !!!\n", __FUNCTION__, __LINE__);

-		BUG_ON(1);

-	}

-

-	// Open AIC_TX and AIC_RX

-	REG_DMAC_DMACKE(1) = 1 << (DMA_RX_CHAN - HALF_DMA_NUM) | 1 << (DMA_TX_CHAN - HALF_DMA_NUM);

-

-	return i;

-}

-

-static int init_audio_recorddma(audio_pipe *endpoint)

-{

-	int ch = 0;

-

-	ENTER();

-	if ((ch = jz_request_aic_dma(DMA_ID_I2S_RX, "audio adc", jz_i2s_dma_irq, IRQF_DISABLED, endpoint)) < 0) {

-		printk(KERN_ERR "%s: can't reqeust DMA DAC channel.\n", __FUNCTION__);

-		return -1;

-	}

-	REG_DMAC_DMACR(ch / HALF_DMA_NUM) |= 1;

-	REG_DMAC_DCMD(ch) =  DMAC_DCMD_DAI | DMAC_DCMD_SWDH_32 | DMAC_DCMD_TIE;

-	REG_DMAC_DRSR(ch) =  DMAC_DRSR_RS_AICIN;

-	REG_DMAC_DSAR(ch) =  (unsigned int)CPHYSADDR(AIC_DR);

-

-	endpoint->dma.ch = ch;

-	endpoint->dma.trans_addr = (unsigned int *)DMAC_DTAR(ch);

-	endpoint->dma.trans_count = (unsigned int *)DMAC_DTCR(ch);

-	endpoint->dma.trans_mode = (unsigned int *)DMAC_DCMD(ch);

-	endpoint->dma.data_addr = (unsigned int *)DMAC_DSAR(ch);

-

-	endpoint->dma.rw = 0;

-

-	LEAVE();

-	return ch;

-}

-

-static int init_audio_replaydma(audio_pipe *endpoint)

-{

-	int ch = 0;

-	if ((ch = jz_request_aic_dma(DMA_ID_I2S_TX,"audio dac", jz_i2s_dma_irq, IRQF_DISABLED, endpoint)) < 0) {

-		printk(KERN_ERR "%s: can't reqeust DMA DAC channel.\n", __FUNCTION__);

-		return -1;

-	}

-

-	REG_DMAC_DMACR(ch / HALF_DMA_NUM) |= 1;

-	REG_DMAC_DCMD(ch) =  DMAC_DCMD_SAI | DMAC_DCMD_DWDH_32 | DMAC_DCMD_TIE;

-

-	//printk("$$$$ before set --- REG_DMAC_DRSR(ch) = 0x%08x\n", REG_DMAC_DRSR(ch));

-	REG_DMAC_DRSR(ch) =  DMAC_DRSR_RS_AICOUT;

-

-	//printk("$$$$ ch = %d, DMAC_DRSR = 0x%08x, set 0x%08x, after set -- 0x%08x\n",

-	//       ch, DMAC_DRSR(ch), DMAC_DRSR_RS_AICOUT, REG_DMAC_DRSR(ch));

-

-	*(unsigned int *)0xb342010c = 0x18;

-

-	//printk("$$$$ after force set --- REG_DMAC_DRSR(ch) = 0x%08x\n", REG_DMAC_DRSR(ch));

-

-	REG_DMAC_DTAR(ch) =  (unsigned int)CPHYSADDR(AIC_DR);

-

-	endpoint->dma.ch = ch;

-	endpoint->dma.trans_addr = (unsigned int *)DMAC_DSAR(ch);

-	endpoint->dma.trans_count = (unsigned int *)DMAC_DTCR(ch);

-	endpoint->dma.trans_mode = (unsigned int *)DMAC_DCMD(ch);

-	endpoint->dma.data_addr = (unsigned int *)DMAC_DTAR(ch);

-	endpoint->dma.rw = 1;

-	return ch;

-}

-

-static int init_audio_audiodma(audio_pipe *endpoint, int mode)

-{

-	if (mode == CODEC_RMODE) {

-		return init_audio_recorddma(endpoint);

-	}

-

-	if (mode == CODEC_WMODE) {

-		return init_audio_replaydma(endpoint);

-	}

-

-	return -1;

-}

-

-static void config_dma_trans_mode(spinlock_t lock, audio_dma_type* dma, int sound_data_width)

-{

-	unsigned int	curmode;

-	unsigned long	flags;

-

-	ENTER();

-	AUDIO_LOCK(lock, flags);

-	curmode = *dma->trans_mode;

-

-	if (dma->rw) {

-		curmode &= ~(DMAC_DCMD_DWDH_MASK | DMAC_DCMD_DS_MASK);

-		switch(sound_data_width) {

-		case 8:

-			*dma->trans_mode = (curmode | DMAC_DCMD_DWDH_8 | DMAC_DCMD_DS_16BYTE);

-			dma->onetrans_bit = 16 * 8;

-			break;

-		case 16:

-			*dma->trans_mode = (curmode | DMAC_DCMD_DWDH_16 | DMAC_DCMD_DS_16BYTE);

-			dma->onetrans_bit = 16 * 8;

-			break;

-		case 17 ... 32:

-			*dma->trans_mode = (curmode | DMAC_DCMD_DWDH_32 | DMAC_DCMD_DS_32BYTE);

-			dma->onetrans_bit = 32 * 8;

-			break;

-		default:

-			printk("JZ I2S: Unkown DMA mode(sound data width) %d\n", sound_data_width);

-			break;

-		}

-	} else {

-		curmode &= ~(DMAC_DCMD_SWDH_MASK | DMAC_DCMD_DS_MASK);

-		switch(sound_data_width) {

-		case 8:

-			*dma->trans_mode = (curmode | DMAC_DCMD_SWDH_8 | DMAC_DCMD_DS_16BYTE);

-			dma->onetrans_bit = 16 * 8;

-			break;

-		case 16:

-			*dma->trans_mode = (curmode | DMAC_DCMD_SWDH_16 | DMAC_DCMD_DS_16BYTE);

-			dma->onetrans_bit = 16 * 8;

-			break;

-		case 17 ... 32:

-			*dma->trans_mode = (curmode | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DS_32BYTE);

-			dma->onetrans_bit = 32 * 8;

-			break;

-		default:

-			printk("JZ I2S: Unkown DMA mode(sound data width) %d\n", sound_data_width);

-			break;

-		}

-	}

-

-	AUDIO_UNLOCK(lock, flags);

-	DUMP_DMA(dma->ch, __FUNCTION__);

-	DPRINT_DMA("dma_trans = %d\n", dma->onetrans_bit);

-	LEAVE();

-}

-

-#define aic_enable_transmit()					\

-do {								\

-	int dat = REG_AIC_CR;					\

-	dat |= (AIC_CR_TDMS | AIC_CR_ERPL);			\

-	REG_AIC_CR = dat;					\

-} while (0)

-

-#define aic_disable_transmit()					\

-do {								\

-	int dat = REG_AIC_CR;					\

-	dat &= ~(AIC_CR_TDMS | AIC_CR_ERPL);			\

-	REG_AIC_CR = dat;					\

-} while (0)

-

-static inline int audio_trystart_dma_node(audio_dma_type* dma, audio_node *node)

-{

-	int start = 0;

-

-	ENTER();

-

-	if ((REG_DMAC_DCCSR(dma->ch) & DMAC_DCCSR_EN) == 0) {

-		int count = node->end - node->start;

-		*(dma->trans_addr) = node->phyaddr;

-		*(dma->data_addr) =  (unsigned int)CPHYSADDR(AIC_DR);

-		*(dma->trans_count) = count * 8 / dma->onetrans_bit;

-		REG_DMAC_DCCSR(dma->ch) = DMAC_DCCSR_NDES | DMAC_DCCSR_EN;

-		DPRINT_DMA("virt = 0x%08x phy = 0x%08x, dma->onetrans_bit = 0x%x\n",

-			   node->pBuf, node->phyaddr, dma->onetrans_bit);

-

-		DUMP_CODEC_REGS(__FUNCTION__);

-		DUMP_AIC_REGS(__FUNCTION__);

-		start = 1;

-	}

-

-	DUMP_DMA(dma->ch, "audio_trystart_dma_node -----------");

-

-	LEAVE();

-	return start;

-}

-

-static inline void audio_stop_dma_node(audio_dma_type* dma)

-{

-	REG_DMAC_DCCSR(dma->ch) = 0;

-}

-

-/* Never be used, fix me ???

-static inline int recalculate_fifowidth(short channels, short fmt)

-{

-	int bit = 16;

-

-	if (fmt <= 8) {

-		bit = 8;

-	} else if (fmt > 16) {

-		bit = 32;

-	} else {

-		bit = 16;

-	}

-

-	return 	bit *= channels;

-}

-*/

-#define I2S_FIFO_DEPTH 32

-

-static inline void set_controller_triger(struct jz_i2s_controller_info *controller,

-					 audio_pipe *endpoint, short channels, short format)

-{

-	int sound_data_width = 0;

-

-	ENTER();

-

-//	printk("%%%% format = %d\n", format);

-

-	switch (format) {

-	case AFMT_U8:

-	case AFMT_S8:

-		sound_data_width = 8;

-		break;

-	case AFMT_S16_LE:

-	case AFMT_S16_BE:

-		sound_data_width = 16;

-		break;

-	default:

-		printk("JZ I2S: Unkown sound format %d\n", format);

-		return ;

-	}

-

-	config_dma_trans_mode(endpoint->lock,&(endpoint->dma), sound_data_width);

-	if (endpoint == &out_endpoint) {

-		if ((I2S_FIFO_DEPTH - endpoint->dma.onetrans_bit / sound_data_width) >= 30) {

-			__i2s_set_transmit_trigger(14);

-		} else {

-			__i2s_set_transmit_trigger((I2S_FIFO_DEPTH - endpoint->dma.onetrans_bit / sound_data_width) / 2);

-		}

-	}

-	if (endpoint == &in_endpoint) {

-		__i2s_set_receive_trigger((endpoint->dma.onetrans_bit / sound_data_width) / 2);

-	}

-

-	LEAVE();

-}

-

-//-------------------------------------------------------------------

-/*

-  int trystart_endpoint_out(audio_pipe *endpoint, audio_node *node);

-  int trystart_endpoint_in(audio_pipe *endpoint, audio_node *node);

-  note: this two function isn't protected;

- */

-static inline int trystart_endpoint_out(struct jz_i2s_controller_info *controller, audio_node *node)

-{

-	audio_pipe *endpoint = controller->pout_endpoint;

-	int start = 0;

-

-	ENTER();

-

-	start = audio_trystart_dma_node(&(endpoint->dma), node);

-	if (start) {

-		endpoint->trans_state |= PIPE_TRANS;

-		endpoint->savenode = node;

-		aic_enable_transmit();

-		DUMP_AIC_REGS(__FUNCTION__);

-		DUMP_CODEC_REGS(__FUNCTION__);

-	}

-

-	LEAVE();

-	return start;

-}

-

-static inline int trystart_endpoint_in(struct jz_i2s_controller_info *controller, audio_node *node)

-{

-	audio_pipe *endpoint = controller->pin_endpoint;

-	int start = 0;

-

-	ENTER();

-	dma_cache_wback_inv((unsigned long)node->pBuf, endpoint->fragsize);

-	start = audio_trystart_dma_node(&(endpoint->dma), node);

-	if (start) {

-		endpoint->trans_state |= PIPE_TRANS;

-		endpoint->savenode = node;

-		__i2s_enable_receive_dma();

-		__i2s_enable_record();

-		DUMP_AIC_REGS(__FUNCTION__);

-		DUMP_CODEC_REGS(__FUNCTION__);

-	}

-	LEAVE();

-	return start;

-}

-

-int audio_get_endpoint_freesize(audio_pipe *endpoint, audio_buf_info *info)

-{

-	int count;

-	unsigned long flags;

-

-	AUDIO_LOCK(endpoint->lock, flags);

-	count = get_audio_freenodecount(endpoint->mem);

-	AUDIO_UNLOCK(endpoint->lock, flags);

-	info->fragments = count;

-	info->fragstotal = endpoint->fragstotal;

-	info->fragsize = endpoint->fragsize;

-	info->bytes = count * endpoint->fragsize;

-	return info->bytes;

-}

-

-void audio_clear_endpoint(audio_pipe *endpoint)

-{

-	audio_node *pusenode;

-	unsigned long flags;

-

-	ENTER();

-	AUDIO_LOCK(endpoint->lock, flags);

-	while (!is_null_use_audio_node(endpoint->mem)) {

-		pusenode = get_audio_usenode(endpoint->mem);

-		if (pusenode) {

-			put_audio_freenode(endpoint->mem, pusenode);

-		}

-	}

-	AUDIO_UNLOCK(endpoint->lock, flags);

-	LEAVE();

-}

-

-void audio_sync_endpoint(audio_pipe *endpoint)

-{

-	int isnull = 1;

-	unsigned long flags;

-

-	ENTER();

-

-	do {

-		AUDIO_LOCK(endpoint->lock, flags);

-		isnull = is_null_use_audio_node(endpoint->mem);

-		AUDIO_UNLOCK(endpoint->lock, flags);

-		if (!isnull) {

-			//printk("&&&& audio_sync_endpoint\n");

-			schedule_timeout(1);

-		}

-	} while (!isnull);

-

-	LEAVE();

-}

-

-void audio_close_endpoint(audio_pipe *endpoint, int mode)

-{

-	int is_use_list_null = 1, trans = 0;

-	unsigned long flags;

-

-	ENTER();

-

-	AUDIO_LOCK(endpoint->lock, flags);

-	is_use_list_null = is_null_use_audio_node(endpoint->mem);

-	trans = endpoint->trans_state & PIPE_TRANS;

-	AUDIO_UNLOCK(endpoint->lock, flags);

-

-	if (is_use_list_null) {

-		// Wait savenode trans complete

-		while (trans) {

-			AUDIO_LOCK(endpoint->lock, flags);

-			trans = endpoint->trans_state & PIPE_TRANS;

-			AUDIO_UNLOCK(endpoint->lock, flags);

-			DPRINT("waiting savenode\n");

-			if (trans) {

-				schedule_timeout(10);

-			}

-		}

-

-		/* In replay mode, savenode must been put into free list after trans completed,

-		 * so we don't care it in this condition.

-		 * But in record mode, savenode must been put into use list after trans completed,

-		 * so we have to ignore the incomming data and move it to free list forcely.

-		 */

-		if (endpoint == &out_endpoint) {

-			goto _L_AUDIO_CLOSE_EP_RET;

-		}

-	}

-

-	// NOMAL_STOP routine of replay mode

-	if (mode == NOMAL_STOP) {

-		BUG_ON(endpoint != &out_endpoint);

-

-		// Wait use list free

-		audio_sync_endpoint(endpoint);

-		// wait savenode trans finish

-		while (trans) {

-			AUDIO_LOCK(endpoint->lock, flags);

-			trans = endpoint->trans_state & PIPE_TRANS;

-			AUDIO_UNLOCK(endpoint->lock, flags);

-			//printk("waiting savenode\n");

-			if (trans) {

-				schedule_timeout(10);

-			}

-		}

-

-		AUDIO_LOCK(endpoint->lock, flags);

-		DUMP_LIST((audio_head *)endpoint->mem);

-		DUMP_NODE(endpoint->savenode, "SN");

-		AUDIO_UNLOCK(endpoint->lock, flags);

-	} else {

-		// FORCE_STOP routine, both replay and record mode could run

-		audio_node *pusenode;

-

-		// Shutdown DMA immediately and clear lists forcely.

-		AUDIO_LOCK(endpoint->lock, flags);

-

-		endpoint->trans_state &= ~PIPE_TRANS;

-		audio_stop_dma_node(&endpoint->dma);

-

-		DUMP_LIST((audio_head *)endpoint->mem);

-		DUMP_NODE(endpoint->savenode, "SN");

-		DPRINT_Q("---------------------------------\n");

-

-		while (!is_null_use_audio_node(endpoint->mem)) {

-			pusenode = get_audio_usenode(endpoint->mem);

-			if (pusenode) {

-				put_audio_freenode(endpoint->mem, pusenode);

-			}

-		}

-

-		DUMP_LIST((audio_head *)endpoint->mem);

-		DUMP_NODE(endpoint->savenode, "SN");

-		DPRINT_Q("---------------------------------\n");

-

-		if (endpoint->savenode) {

-			DPRINT_Q("handle savenode : 0x%08x\n", (unsigned int)endpoint->savenode);

-			DUMP_NODE(endpoint->savenode, "SN");

-			put_audio_freenode(endpoint->mem, endpoint->savenode);

-

-			DPRINT_Q("savenode->list->next = 0x%08x, savenode->list->prev = 0x%08x\n",

-			       (unsigned int)endpoint->savenode->list.next,

-			       (unsigned int)endpoint->savenode->list.prev);

-

-			endpoint->savenode = NULL;

-		}

-

-		DUMP_LIST((audio_head *)endpoint->mem);

-		DUMP_NODE(endpoint->savenode, "SN");

-

-		AUDIO_UNLOCK(endpoint->lock, flags);

-	}

-

-_L_AUDIO_CLOSE_EP_RET:

-	LEAVE();

-}

-

-int audio_resizemem_endpoint(audio_pipe *endpoint, unsigned int pagesize, unsigned int count)

-{

-	int ret = init_audio_node(&endpoint->mem, pagesize, count);

-	if (ret) {

-		endpoint->fragsize = pagesize;

-		endpoint->fragstotal = count;

-	}

-	return ret;

-}

-

-static void handle_in_endpoint_work(audio_pipe *endpoint)

-{

-	audio_node	*node;

-	unsigned long	flags;

-

-	ENTER();

-

-	AUDIO_LOCK(endpoint->lock, flags);

-	if (endpoint->savenode) {

-		DPRINT_Q("\nIIII RRRR QQQQ >>>>\n");

-		DUMP_LIST((audio_head *)endpoint->mem);

-		DUMP_NODE(endpoint->savenode, "IRQSN");

-		DPRINT_Q("IIII RRRR QQQQ <<<<\n\n");

-

-		DPRINT_IRQ("%s endpoint->savenode = 0x%p\n", __FUNCTION__, endpoint->savenode);

-		put_audio_usenode(endpoint->mem, endpoint->savenode);

-

-		endpoint->savenode = NULL;

-		DUMP_BUF((char *)(endpoint->savenode->pBuf + endpoint->savenode->start), 64, 32);

-

-		if (!(endpoint->is_non_block)) {

-			endpoint->avialable_couter++;

-			wake_up_interruptible(&endpoint->q_full);

-		}

-	}

-

-	node = get_audio_freenode(endpoint->mem);

-	if (node) {

-		int start;

-		node->end = endpoint->fragsize;

-		dma_cache_wback_inv((unsigned long)node->pBuf, endpoint->fragsize);

-		start = audio_trystart_dma_node(&(endpoint->dma), node);

-		if (start == 0) {

-			put_audio_freenode(endpoint->mem, node);

-		} else {

-			endpoint->savenode = node;

-		}

-	} else {

-		endpoint->trans_state &= ~PIPE_TRANS;

-		__i2s_disable_receive_dma();

-		__i2s_disable_record();

-		DPRINT_IRQ("!!!! Stop AIC record !\n");

-	}

-

-	DPRINT_Q("\nIIII RRRR QQQQ >>>>\n");

-	DUMP_LIST((audio_head *)endpoint->mem);

-	DUMP_NODE(endpoint->savenode, "SN");

-	DPRINT_Q("IIII RRRR QQQQ <<<<\n\n");

-

-	AUDIO_UNLOCK(endpoint->lock, flags);

-

-	LEAVE();

-}

-

-/*

-static void audio_in_endpoint_work(struct work_struct *work)

-{

-	audio_pipe *endpoint = &in_endpoint;

-	handle_in_endpoint_work(endpoint);

-}

-*/

-

-static void handle_out_endpoint_work(audio_pipe *endpoint)

-{

-	audio_node *node;

-	unsigned long flags;

-

-	ENTER();

-

-	AUDIO_LOCK(endpoint->lock, flags);

-	DPRINT_IRQ("%s endpoint->savenode = 0x%08x\n", __FUNCTION__, (unsigned int)endpoint->savenode);

-

-	if (endpoint->savenode) {

-		put_audio_freenode(endpoint->mem, endpoint->savenode);

-		DPRINT_IRQ("put_audio_freenode\n");

-		endpoint->savenode = NULL;

-

-		if (!(endpoint->is_non_block)) {

-			wake_up_interruptible(&endpoint->q_full);

-			endpoint->avialable_couter++;

-		}

-	}

-

-	node = get_audio_usenode(endpoint->mem);

-	if (node) {

-		int start;

-		start = audio_trystart_dma_node(&(endpoint->dma), node);

-		if (start == 0) {

-			printk("audio_out_endpoint_work audio_trystart_dma_node error!\n");

-		} else {

-			endpoint->savenode = node;

-			DPRINT_DMA("restart dma!\n");

-		}

-	} else {

-		endpoint->trans_state &= ~PIPE_TRANS;

-		aic_disable_transmit();

-		DPRINT_IRQ("!!!! Stop AIC !\n");

-	}

-

-	AUDIO_UNLOCK(endpoint->lock, flags);

-	LEAVE();

-}

-

-/*

-static void audio_out_endpoint_work(struct work_struct *work)

-{

-	audio_pipe *endpoint = &out_endpoint;

-	handle_out_endpoint_work(endpoint);

-}

-*/

-

-void audio_init_endpoint(audio_pipe *endpoint, unsigned int pagesize, unsigned int count)

-{

-	audio_resizemem_endpoint(endpoint, pagesize, count);

-	spin_lock_init(&endpoint->lock);

-	init_waitqueue_head(&endpoint->q_full);

-	endpoint->avialable_couter = 0;

-	endpoint->filter = NULL;

-

-	if (endpoint == &in_endpoint) {

-		init_audio_audiodma(endpoint, CODEC_RMODE);

-		// INIT_WORK(&endpoint->work, audio_in_endpoint_work);

-		endpoint->handle = handle_in_endpoint_work;

-	}

-	if (endpoint == &out_endpoint) {

-		init_audio_audiodma(endpoint, CODEC_WMODE);

-		// INIT_WORK(&endpoint->work, audio_out_endpoint_work);

-		endpoint->handle = handle_out_endpoint_work;

-	}

-}

-

-void audio_deinit_endpoint(audio_pipe *endpoint)

-{

-	audio_close_endpoint(endpoint, FORCE_STOP);

-	deinit_audio_node(&endpoint->mem);

-}

-

-void register_jz_codecs(void *func)

-{

-	int i;

-

-	ENTER();

-

-	for (i = 0; i < NR_I2S; i++) {

-		if (the_codecs[i].codecs_ioctrl == 0) {

-			printk("register codec %x\n",(unsigned int)func);

-			the_codecs[i].id = i;

-			the_codecs[i].codecs_ioctrl = func;

-			init_MUTEX(&(the_codecs[i].i2s_sem));

-			break;

-		}

-	}

-

-	LEAVE();

-}

-

-#define codec_ioctrl(codec, cmd, args) ({			\

-	int result;						\

-	down(&(codec)->i2s_sem);				\

-	result = (codec)->codecs_ioctrl((codec), (cmd), (args));\

-	up(&(codec)->i2s_sem);					\

-	result;							\

-})

-

-static int jz_i2s_open_mixdev(struct inode *inode, struct file *file)

-{

-	int i;

-	int minor = MINOR(inode->i_rdev);

-

-	ENTER();

-

-	for (i = 0; i < NR_I2S; i++) {

-		if (the_codecs[i].dev_mixer == minor) {

-			goto match;

-		}

-	}

-match:

-	file->private_data = &the_codecs[i];

-

-	LEAVE();

-	return 0;

-}

-

-/*

- * Debug entry for Android

- */

-static int jz_i2s_write_mixdev(struct file *file, const char __user *buffer, size_t count, loff_t *ppos)

-{

-	struct i2s_codec *codec = (struct i2s_codec *)file->private_data;

-	char	buf_byte = 0;

-	char	argument[16];

-	int	val;

-

-	if (copy_from_user((void *)&buf_byte, buffer, 1)) {

-		printk("JZ MIX: copy_from_user failed !\n");

-		return -EFAULT;

-	}

-

-	switch (buf_byte) {

-	case '1':

-		dump_dlv_regs("jz_i2s_write_mixdev --- debug routine");

-		dump_aic_regs("");

-		break;

-	case '2':

-		printk("dlv_set_replay\n");

-		codec_ioctrl(codec, CODEC_SET_REPLAY, 0);

-		break;

-	case '3':

-		printk("dlv_set_record\n");

-		codec_ioctrl(codec, CODEC_SET_RECORD, 0);

-		break;

-	case '4':

-		if (codec_ioctrl(codec, CODEC_SET_RECORD_DATA_WIDTH, 16) >= 0) {

-			printk("Set data width : 16\n");

-		} else {

-			printk("Could not set data width\n");

-		}

-		break;

-	case '5':

-		if (copy_from_user((void *)&argument, buffer + 1, 3)) {

-			printk("JZ MIX: copy_from_user failed !\n");

-			return -EFAULT;

-		}

-		if (argument[0] >= '0' && argument[0] <= '9'

-		    && argument [1] >= '0' && argument[1] <= '9'

-		    && argument [2] >= '0' && argument[2] <= '9') {

-

-			val = (argument[0] - '0') * 100 + (argument[1] - '0') * 10 + argument[2] - '0';

-

-			printk("JZ MIX: set volume (%d)\n", val);

-			codec_ioctrl(codec, CODEC_SET_VOLUME, val);

-		} else {

-			printk("JZ MIX: invalid argument for set volume\n");

-		}

-		break;

-	}

-

-	return count;

-}

-

-/*

- * Handle IOCTL request on /dev/mixer

- *

- * Support OSS IOCTL interfaces for /dev/mixer

- * Support IOCTL interfaces for /dev/mixer defined in include/msm_audio.h

- */

-static int jz_i2s_ioctl_mixdev(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)

-{

-	struct i2s_codec *codec = (struct i2s_codec *)file->private_data;

-	long	val = 0;

-	int	ret, rc = 0;

-

-	ENTER();

-

-	DPRINT_IOC("[mixer IOCTL]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n");

-	DPRINT_IOC(" mixer IOCTL %s cmd = 0x%08x, arg = %lu\n", __FUNCTION__, cmd, arg);

-	DPRINT_MIXER_IOC_CMD(cmd);

-	DPRINT_IOC("[mixer IOCTL]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n");

-

-	// struct jz_i2s_controller_info *controller = (struct jz_i2s_controller_info *) file->private_data;

-

-	switch (cmd) {

-

-	/*

-	 * OSS IOCTL commands for /dev/mixer

-	 */

-	case SOUND_MIXER_INFO:

-	{

-		mixer_info info;

-		codec_ioctrl(codec, CODEC_GET_MIXER_INFO, (unsigned int)&info);

-		info.modify_counter = audio_mix_modcnt;

-		return copy_to_user((void *)arg, &info, sizeof(info));

-	}

-	case SOUND_OLD_MIXER_INFO:

-	{

-		_old_mixer_info info;

-		codec_ioctrl(codec, CODEC_GET_MIXER_OLD_INFO, (unsigned int)&info);

-		return copy_to_user((void *)arg, &info, sizeof(info));

-	}

-

-	case SOUND_MIXER_READ_STEREODEVS:

-		return put_user(0, (long *) arg);

-	case SOUND_MIXER_READ_CAPS:

-		return put_user(SOUND_CAP_EXCL_INPUT, (long *) arg);

-

-	case SOUND_MIXER_READ_DEVMASK:

-		break;

-	case SOUND_MIXER_READ_RECMASK:

-		break;

-	case SOUND_MIXER_READ_RECSRC:

-		break;

-

-	case SOUND_MIXER_WRITE_SPEAKER:

-		ret = get_user(val, (long *) arg);

-		if ((val &= 0xff) >= 100) {

-			val = 100;

-		}

-		codec_ioctrl(codec, CODEC_SET_DIRECT_MODE, val);

-		break;

-

-	case SOUND_MIXER_WRITE_BASS:

-		ret = get_user(val, (long *) arg);

-		if ((val &= 0xff) >= 100) {

-			val = 100;

-		}

-		codec->bass_gain = val;

-		codec_ioctrl(codec, CODEC_SET_BASS, val);

-		return 0;

-

-	case SOUND_MIXER_READ_BASS:

-		val = codec->bass_gain;

-		ret = val << 8;

-		val = val | ret;

-		return put_user(val, (long *) arg);

-

-	case SOUND_MIXER_WRITE_VOLUME:

-		ret = get_user(val, (long *) arg);

-		if ((val &= 0xff) >= 100) {

-			val = 100;

-		}

-

-		DPRINT_IOC("SOUND_MIXER_WRITE_VOLUME <- %lu\n", val);

-

-		codec->audio_volume = val;

-		codec_ioctrl(codec, CODEC_SET_REPLAY_VOLUME, val);

-		return 0;

-

-	case SOUND_MIXER_READ_VOLUME:

-		val = codec->audio_volume;

-		ret = val << 8;

-		val = val | ret;

-		return put_user(val, (long *) arg);

-

-	case SOUND_MIXER_WRITE_MIC:

-

-		printk(">>>>>>>>>>>>>>>>>>>>>>>>>>>>>write mic\n");

-		ret = get_user(val, (long *) arg);

-		if ((val &= 0xff) >= 100) {

-			val = 100;

-		}

-		codec->mic_gain = val;

-		codec->use_mic_line_flag = USE_MIC;

-		codec_ioctrl(codec, CODEC_SET_MIC_VOLUME, val);

-		return 0;

-

-	case SOUND_MIXER_READ_MIC:

-		val = codec->mic_gain;

-		ret = val << 8;

-		val = val | ret;

-		return put_user(val, (long *) arg);

-

-	case SOUND_MIXER_WRITE_LINE:

-		ret = get_user(val, (long *) arg);

-		if (ret) {

-			return ret;

-		}

-		if ((val &= 0xff) >= 100) {

-			val = 100;

-		}

-		codec->use_mic_line_flag = USE_LINEIN;

-		codec->mic_gain = val;

-		codec_ioctrl(codec, CODEC_SET_LINE, val);

-		return 0;

-

-	case SOUND_MIXER_READ_LINE:

-		val = codec->mic_gain;

-		ret = val << 8;

-		val = val | ret;

-		return put_user(val, (long *) arg);

-

-	case SOUND_MIXER_WRITE_MUTE:

-		get_user(codec->audiomute, (long *)arg);

-		//codec_ioctrl(codec, CODEC_DAC_MUTE, codec->audiomute);

-		break;

-

-	case SOUND_MIXER_READ_MUTE:

-		put_user(codec->audiomute, (long *) arg);

-		break;

-

-#if 0

-	/*

-	 * MSM IOCTL commands for /dev/mixer

-	 */

-	case SND_SET_DEVICE:

-	{

-		struct snd_device_config dev;

-		if (copy_from_user(&dev, (void *) arg, sizeof(dev))) {

-			rc = -EFAULT;

-			break;

-		}

-		break;

-	}

-

-	case SND_SET_VOLUME:

-	{

-		struct snd_volume_config vol;

-		if (copy_from_user(&vol, (void *) arg, sizeof(vol))) {

-			return -EFAULT;

-		}

-		val =  vol.volume;

-		if ((val &= 0xff) >= 100) {

-			val = 100;

-		}

-		DPRINT_IOC("snd_set_volume %d %d %d\n", vol.device, vol.method, vol.volume);

-		codec->audio_volume = val;

-		codec_ioctrl(codec, CODEC_SET_MIC, (unsigned int)&val); ///??????????????????????????

-		//error

-		break;

-	}

-

-	case SND_GET_NUM_ENDPOINTS:

-		if (copy_to_user((void __user*) arg, &snd->snd_epts->num, sizeof(unsigned))) {

-			printk("%s: error get endpoint\n",__FUNCTION__);

-			rc = -EFAULT;

-		}

-		val = 2;

-		if (copy_to_user((void __user*) arg, &val, sizeof(unsigned))) {

-			printk("%s: error get endpoint\n",__FUNCTION__);

-			rc = -EFAULT;

-		}

-

-		break;

-	case SND_GET_ENDPOINT:

-		//rc = get_endpoint(snd, arg);

-		break;

-#endif

-

-	default:

-		printk("Mixer IOCTL error: %s:%d: known command: 0x%08x\n", __FUNCTION__, __LINE__, cmd);

-		return -ENOSYS;

-	}

-	audio_mix_modcnt++;

-

-	LEAVE();

-	return rc;

-}

-

-static struct file_operations jz_i2s_mixer_fops =

-{

-	owner:		THIS_MODULE,

-	ioctl:		jz_i2s_ioctl_mixdev,

-	open:		jz_i2s_open_mixdev,

-	write:		jz_i2s_write_mixdev,

-};

-

-int i2s_probe_codec(struct i2s_codec *codec)

-{

-	/* generic OSS to I2S wrapper */

-	return (codec->codecs_ioctrl) ? 1 : 0;

-}

-

-/* I2S codec initialisation. */

-static int __init jz_i2s_codec_init(struct jz_i2s_controller_info *controller)

-{

-	int i;

-

-	ENTER();

-

-	for (i = 0; i < NR_I2S; i++) {

-		the_codecs[i].private_data = controller;

-		if (i2s_probe_codec(&the_codecs[i]) == 0) {

-			break;

-		}

-		if ((the_codecs[i].dev_mixer = register_sound_mixer(&jz_i2s_mixer_fops, the_codecs[i].id)) < 0) {

-			printk(KERN_ERR "JZ I2S: couldn't register mixer!\n");

-			break;

-		}

-

-	}

-	controller->i2s_codec = &the_codecs[0];

-

-	LEAVE();

-	return i;

-}

-

-static void jz_i2s_reinit_hw(struct i2s_codec *codec, int mode)

-{

-	ENTER();

-

-   	__i2s_disable();

-	schedule_timeout(5);

-	codec_ioctrl(codec, CODEC_EACH_TIME_INIT, 0);

-	__i2s_disable_record();

-	__i2s_disable_replay();

-	__i2s_disable_loopback();

-	__i2s_set_transmit_trigger(4);

-	__i2s_set_receive_trigger(3);

-

-	LEAVE();

-}

-

-static int jz_codec_set_speed(struct i2s_codec *codec, int rate, int mode)

-{

-	ENTER();

-

-	/* 8000, 11025, 16000, 22050, 24000, 32000, 44100, 48000, 99999999 ? */

-	if (mode & CODEC_RMODE) {

-		rate = codec_ioctrl(codec, CODEC_SET_RECORD_RATE, rate);

-		if (rate > 0) {

-			codec->record_audio_rate = rate;

-		} else {

-			rate = codec->record_audio_rate;

-		}

-	}

-	if (mode & CODEC_WMODE) {

-		rate = codec_ioctrl(codec, CODEC_SET_REPLAY_RATE, rate);

-		if (rate > 0) {

-			codec->replay_audio_rate = rate;

-		} else {

-			rate = codec->replay_audio_rate;

-		}

-	}

-

-	LEAVE();

-	return rate;

-}

-

-static short jz_codec_set_channels(struct i2s_codec *codec, short channels, int mode)

-{

-	ENTER();

-

-	DPRINT_IOC("%s mode = %x channels = %d\n", __FUNCTION__, mode, channels);

-	DPRINT_IOC("mode & CODEC_RMODE == %x", mode & CODEC_RMODE);

-

-	if (mode & CODEC_RMODE) {

-		channels = codec_ioctrl(codec, CODEC_SET_RECORD_CHANNEL, channels);

-		codec->record_codec_channel = channels;

-	}

-	if (mode & CODEC_WMODE) {

-		channels = codec_ioctrl(codec, CODEC_SET_REPLAY_CHANNEL, channels);

-		codec->replay_codec_channel = channels;

-		if (channels == 1) {

-			__aic_enable_mono2stereo();

-			__aic_out_channel_select(0);

-		} else {

-			__aic_disable_mono2stereo();

-			__aic_out_channel_select(1);

-		}

-	}

-

-	LEAVE();

-

-	return channels;

-}

-

-static void jz_codec_select_mode(struct i2s_codec *codec, int mode)

-{

-	ENTER();

-

-	switch (mode) {

-	case CODEC_WRMODE:

-		if (codec->use_mic_line_flag == USE_NONE) {

-			codec->use_mic_line_flag = USE_MIC;

-		}

-		codec_ioctrl(codec, CODEC_SET_REPLAY_RECORD, codec->use_mic_line_flag);

-		break;

-	case CODEC_RMODE:

-		if (codec->use_mic_line_flag == USE_NONE) {

-			codec->use_mic_line_flag = USE_MIC;

-		}

-		codec_ioctrl(codec, CODEC_SET_RECORD, codec->use_mic_line_flag);

-		break;

-	case CODEC_WMODE:

-		codec_ioctrl(codec, CODEC_SET_REPLAY, mode);

-		break;

-	}

-

-	LEAVE();

-}

-

-void jz_codec_anti_pop(struct i2s_codec *codec, int mode)

-{

-	ENTER();

-	codec_ioctrl(codec, CODEC_ANTI_POP, mode);

-	LEAVE();

-}

-

-void jz_codec_close(struct i2s_codec *codec, int mode)

-{

-	ENTER();

-	down(&codec->i2s_sem);

-	codec->codecs_ioctrl(codec, CODEC_TURN_OFF, mode);

-	up(&codec->i2s_sem);

-	LEAVE();

-}

-

-/***************************************************************

-			filter functions

- ***************************************************************/

-

-/*

- * Convert signed byte to unsiged byte

- *

- * Mapping:

- * 	signed		unsigned

- *	0x00 (0)	0x80 (128)

- *	0x01 (1)	0x81 (129)

- *	......		......

- *	0x7f (127)	0xff (255)

- *	0x80 (-128)	0x00 (0)

- *	0x81 (-127)	0x01 (1)

- *	......		......

- *	0xff (-1)	0x7f (127)

- */

-static int convert_8bits_signed2unsigned(void *buffer, int counter)

-{

-	int i;

-	int counter_8align	= counter & ~0x7;

-	unsigned char *ucsrc	= buffer;

-	unsigned char *ucdst	= buffer;

-

-	ENTER();

-

-	for (i = 0; i < counter_8align; i+=8) {

-		*(ucdst + i + 0) = *(ucsrc + i + 0) + 0x80;

-		*(ucdst + i + 1) = *(ucsrc + i + 1) + 0x80;

-		*(ucdst + i + 2) = *(ucsrc + i + 2) + 0x80;

-		*(ucdst + i + 3) = *(ucsrc + i + 3) + 0x80;

-		*(ucdst + i + 4) = *(ucsrc + i + 4) + 0x80;

-		*(ucdst + i + 5) = *(ucsrc + i + 5) + 0x80;

-		*(ucdst + i + 6) = *(ucsrc + i + 6) + 0x80;

-		*(ucdst + i + 7) = *(ucsrc + i + 7) + 0x80;

-		//printk("csrc + %d + 7 = %d,  ucdst + %d + 7 = %d\n",

-		//       i, *(csrc + i + 7), i, *(ucdst + i + 7));

-	}

-

-	BUG_ON(i != counter_8align);

-

-	for (i = counter_8align; i < counter; i++) {

-		*(ucdst + i) = *(ucsrc + i) + 0x80;

-	}

-

-	//printk("[dbg] src = 0x%02x (%d) --- dst = 0x%02x (%d), cnt = %d, cnt8a = %d\n",

-	//       *csrc, *csrc, *ucdst, *ucdst, counter, counter_8align);

-	LEAVE();

-	return counter;

-}

-

-/*

- * Convert stereo data to mono data, data width: 8 bits/channel

- *

- * buff:	buffer address

- * data_len:	data length in kernel space, the length of stereo data

- *		calculated by "node->end - node->start"

- */

-int convert_8bits_stereo2mono(void *buff, int data_len)

-{

-	/* stride = 16 bytes = 2 channels * 1 byte * 8 pipelines */

-	int data_len_16aligned = data_len & ~0xf;

-	int mono_cur, stereo_cur;

-	unsigned char *uc_buff = buff;

-

-	/* copy 8 times each loop */

-	for (stereo_cur = mono_cur = 0;

-	     stereo_cur < data_len_16aligned;

-	     stereo_cur += 16, mono_cur += 8) {

-

-		uc_buff[mono_cur + 0] = uc_buff[stereo_cur + 0];

-		uc_buff[mono_cur + 1] = uc_buff[stereo_cur + 2];

-		uc_buff[mono_cur + 2] = uc_buff[stereo_cur + 4];

-		uc_buff[mono_cur + 3] = uc_buff[stereo_cur + 6];

-		uc_buff[mono_cur + 4] = uc_buff[stereo_cur + 8];

-		uc_buff[mono_cur + 5] = uc_buff[stereo_cur + 10];

-		uc_buff[mono_cur + 6] = uc_buff[stereo_cur + 12];

-		uc_buff[mono_cur + 7] = uc_buff[stereo_cur + 14];

-	}

-

-	BUG_ON(stereo_cur != data_len_16aligned);

-

-	/* remaining data */

-	for (; stereo_cur < data_len; stereo_cur += 2, mono_cur++) {

-		uc_buff[mono_cur] = uc_buff[stereo_cur];

-	}

-

-	LEAVE();

-	return (data_len / 2);

-}

-

-/*

- * Convert stereo data to mono data, and convert signed byte to unsigned byte.

- *

- * data width: 8 bits/channel

- *

- * buff:	buffer address

- * data_len:	data length in kernel space, the length of stereo data

- *		calculated by "node->end - node->start"

- */

-int convert_8bits_stereo2mono_signed2unsigned(void *buff, int data_len)

-{

-	/* stride = 16 bytes = 2 channels * 1 byte * 8 pipelines */

-	int data_len_16aligned = data_len & ~0xf;

-	int mono_cur, stereo_cur;

-	unsigned char *uc_buff = buff;

-

-	/* copy 8 times each loop */

-	for (stereo_cur = mono_cur = 0;

-	     stereo_cur < data_len_16aligned;

-	     stereo_cur += 16, mono_cur += 8) {

-

-		uc_buff[mono_cur + 0] = uc_buff[stereo_cur + 0] + 0x80;

-		uc_buff[mono_cur + 1] = uc_buff[stereo_cur + 2] + 0x80;

-		uc_buff[mono_cur + 2] = uc_buff[stereo_cur + 4] + 0x80;

-		uc_buff[mono_cur + 3] = uc_buff[stereo_cur + 6] + 0x80;

-		uc_buff[mono_cur + 4] = uc_buff[stereo_cur + 8] + 0x80;

-		uc_buff[mono_cur + 5] = uc_buff[stereo_cur + 10] + 0x80;

-		uc_buff[mono_cur + 6] = uc_buff[stereo_cur + 12] + 0x80;

-		uc_buff[mono_cur + 7] = uc_buff[stereo_cur + 14] + 0x80;

-	}

-

-	BUG_ON(stereo_cur != data_len_16aligned);

-

-	/* remaining data */

-	for (; stereo_cur < data_len; stereo_cur += 2, mono_cur++) {

-		uc_buff[mono_cur] = uc_buff[stereo_cur] + 0x80;

-	}

-

-	LEAVE();

-	return (data_len / 2);

-}

-

-/*

- * Convert stereo data to mono data, data width: 16 bits/channel

- *

- * buff:	buffer address

- * data_len:	data length in kernel space, the length of stereo data

- *		calculated by "node->end - node->start"

- */

-int convert_16bits_stereo2mono(void *buff, int data_len)

-{

-	/* stride = 32 bytes = 2 channels * 2 byte * 8 pipelines */

-	int data_len_32aligned = data_len & ~0x1f;

-	int data_cnt_ushort = data_len_32aligned / 2;

-	int mono_cur, stereo_cur;

-	unsigned short *ushort_buff = (unsigned short *)buff;

-

-	/* copy 8 times each loop */

-	for (stereo_cur = mono_cur = 0;

-	     stereo_cur < data_cnt_ushort;

-	     stereo_cur += 16, mono_cur += 8) {

-

-		ushort_buff[mono_cur + 0] = ushort_buff[stereo_cur + 0];

-		ushort_buff[mono_cur + 1] = ushort_buff[stereo_cur + 2];

-		ushort_buff[mono_cur + 2] = ushort_buff[stereo_cur + 4];

-		ushort_buff[mono_cur + 3] = ushort_buff[stereo_cur + 6];

-		ushort_buff[mono_cur + 4] = ushort_buff[stereo_cur + 8];

-		ushort_buff[mono_cur + 5] = ushort_buff[stereo_cur + 10];

-		ushort_buff[mono_cur + 6] = ushort_buff[stereo_cur + 12];

-		ushort_buff[mono_cur + 7] = ushort_buff[stereo_cur + 14];

-	}

-

-	BUG_ON(stereo_cur != data_cnt_ushort);

-

-	/* remaining data */

-	for (; stereo_cur < data_cnt_ushort; stereo_cur += 2, mono_cur++) {

-		ushort_buff[mono_cur] = ushort_buff[stereo_cur];

-	}

-

-	LEAVE();

-	return (data_len / 2);

-}

-

-/*

- * Set convert function for audio_pipe

- *

- * In AIC, we just use signed data for all ops as it is shared by

- * replay and record. So, converting data for every non-compatible

- * format is neccessary.

- */

-static inline int endpoint_set_filter(audio_pipe *endpoint, int format, int channels)

-{

-	ENTER();

-

-	DPRINT("%s %d, endpoint = 0x%08x, format = %d, channels = %d\n",

-	       __FUNCTION__, __LINE__, (unsigned int)endpoint, format, channels);

-

-	endpoint->filter = NULL;

-

-	switch (format) {

-	case AFMT_U8:

-		if (endpoint == &in_endpoint) {

-			if (channels == 2) {

-				endpoint->filter = convert_8bits_stereo2mono_signed2unsigned;

-				DPRINT("$$$$ set pin_endpoint->filter = convert_8bits_stereo_2_mono\n");

-			} else {

-				endpoint->filter = convert_8bits_signed2unsigned;

-				DPRINT("$$$$ set pin_endpoint->filter = convert_8bits_signed2unsigned\n");

-			}

-		}

-		break;

-	case AFMT_S16_LE:

-		if (endpoint == &in_endpoint) {

-			if (channels == 1) {

-				endpoint->filter = convert_16bits_stereo2mono;

-				DPRINT("$$$$ set pin_endpoint->filter = convert_16bits_stereo2mono\n");

-			} else {

-				endpoint->filter = NULL;

-				DPRINT("$$$$ set pin_endpoint->filter = NULL\n");

-			}

-		}

-		break;

-	default:

-		printk("JZ I2S endpoint_set_filter: unknown format\n");

-		endpoint->filter = NULL;

-	}

-

-	LEAVE();

-	return 0;

-}

-

-/*

- * The "format" contains data width, signed/unsigned and LE/BE

- *

- * The AIC registers will not be modified !

- *

- * For CODEC	set	data_width

- */

-static int jz_codec_set_format(struct i2s_codec *codec, unsigned int format, int mode)

-{

-	/* The value of format reference to soundcard.h:

-	 *

-	 * AFMT_MU_LAW		0x00000001

-	 * AFMT_A_LAW		0x00000002

-	 * AFMT_IMA_ADPCM	0x00000004

-	 * AFMT_U8		0x00000008

-	 * AFMT_S16_LE		0x00000010

-	 * AFMT_S16_BE		0x00000020

-	 * AFMT_S8		0x00000040

-	 */

-	int data_width = 0;

-

-	ENTER();

-

-	DPRINT("$$$$ %s %d, format = %u, mode = %d\n", __FUNCTION__, __LINE__, format, mode);

-

-	down(&codec->i2s_sem);

-

-	/*

-	 * It is dangerous to modify settings about signed bit, endian and M2S

-	 * as record and replay shared the settings.

-	 *

-	 * Now we don't support unsigned format (AFMT_U8) and BE format (AFMT_S16_BE)

-	 * To support such format, corresponding filter function must be implemented.

-	 */

-	switch (format) {

-	case AFMT_U8:

-		data_width = 8;

-		if (mode & CODEC_RMODE) {

-			__i2s_set_iss_sample_size(8);

-		}

-		if (mode & CODEC_WMODE) {

-			__i2s_set_oss_sample_size(8);

-		}

-		break;

-	case AFMT_S8:

-		data_width = 8;

-		if (mode & CODEC_RMODE) {

-			__i2s_set_iss_sample_size(8);

-		}

-		if (mode & CODEC_WMODE) {

-			__i2s_set_oss_sample_size(8);

-		}

-		break;

-	case AFMT_S16_LE:

-		data_width = 16;

-		if (mode & CODEC_RMODE) {

-			__i2s_set_iss_sample_size(16);

-		}

-		if (mode & CODEC_WMODE) {

-			__i2s_set_oss_sample_size(16);

-		}

-		break;

-	case AFMT_S16_BE:

-		data_width = 16;

-		if (mode & CODEC_RMODE) {

-			__i2s_set_iss_sample_size(16);

-		}

-		if (mode & CODEC_WMODE) {

-			__i2s_set_oss_sample_size(16);

-		}

-		break;

-	default:

-		printk("JZ I2S: Unkown sound format %d\n", format);

-		goto _ERROR_SET_FORMAT;

-	}

-

-	if (mode & CODEC_RMODE) {

-		if (codec->codecs_ioctrl(codec, CODEC_SET_RECORD_DATA_WIDTH, data_width) < 0) {

-			printk("JZ I2S: CODEC ioctl error, command: CODEC_SET_RECORD_FORMAT");

-			goto _ERROR_SET_FORMAT;

-		}

-		codec->record_format = format;

-	}

-

-	if (mode & CODEC_WMODE) {

-		if (codec->codecs_ioctrl(codec, CODEC_SET_REPLAY_DATA_WIDTH, data_width) < 0) {

-			printk("JZ I2S: CODEC ioctl error, command: CODEC_SET_REPLAY_FORMAT");

-			goto _ERROR_SET_FORMAT;

-		}

-		codec->replay_format = format;

-	}

-

-	up(&codec->i2s_sem);

-	LEAVE();

-	return format;

-

-_ERROR_SET_FORMAT:

-	up(&codec->i2s_sem);

-	LEAVE();

-	return -1;

-}

-

-static int jz_audio_release(struct inode *inode, struct file *file)

-{

-	struct jz_i2s_controller_info *controller = (struct jz_i2s_controller_info *) file->private_data;

-	int mode = 0;

-

-	ENTER();

-

-	if (controller == NULL) {

-		printk("\nAudio device not ready!\n");

-		return -ENODEV;

-	}

-	if ((controller->pin_endpoint == NULL) && (controller->pout_endpoint == NULL) ) {

-		printk("\nAudio endpoint not open!\n");

-		return -ENODEV;

-	}

-	if ((file->f_mode & FMODE_READ) && controller->pin_endpoint) {

-		printk("Read mode, %s\n", __FUNCTION__);

-		mode |= CODEC_RMODE;

-		audio_close_endpoint(controller->pin_endpoint, FORCE_STOP);

-		controller->pin_endpoint = NULL;

-

-		__i2s_disable_receive_dma();

-		__i2s_disable_record();

-	}

-

-	if ((file->f_mode & FMODE_WRITE) && controller->pout_endpoint) {

-		printk("Write mode, %s\n", __FUNCTION__);

-		mode |= CODEC_WMODE;

-		audio_close_endpoint(controller->pout_endpoint, NOMAL_STOP);

-		controller->pout_endpoint = NULL;

-

-		__i2s_disable_transmit_dma();

-		__i2s_disable_replay();

-	}

-

-

-	if ((controller->pin_endpoint == NULL) && (controller->pout_endpoint == NULL) ) {

-		__i2s_disable();

-	}

-

-	last_read_node = NULL;

-

-	jz_codec_close(controller->i2s_codec, mode);

-

-	LEAVE();

-	return 0;

-}

-

-static int jz_audio_open(struct inode *inode, struct file *file)

-{

-	struct jz_i2s_controller_info *controller = the_i2s_controller;

-	struct i2s_codec *codec = controller->i2s_codec;

-	int mode = 0;

-	int reset = 1;

-

-	ENTER();

-

-	if (controller == NULL) {

-		return -ENODEV;

-	}

-

-	if (controller->pin_endpoint || controller->pout_endpoint) {

-		reset = 0;

-	}

-

-	if ((file->f_mode & FMODE_READ) && (controller->pin_endpoint)) {

-		printk("\nAudio read device is busy!\n");

-		return -EBUSY;

-	}

-	if ((file->f_mode & FMODE_WRITE) && (controller->pout_endpoint)) {

-		printk("\nAudio write device is busy!\n");

-		return -EBUSY;

-	}

-

-	if (file->f_mode & FMODE_WRITE) {

-		controller->pout_endpoint = &out_endpoint;

-		controller->pout_endpoint->is_non_block = file->f_flags & O_NONBLOCK;

-		mode |= CODEC_WMODE;

-	}

-	if (file->f_mode & FMODE_READ) {

-		controller->pin_endpoint = &in_endpoint;

-		controller->pin_endpoint->is_non_block = file->f_flags & O_NONBLOCK;

-		mode |= CODEC_RMODE;

-	}

-   	file->private_data = controller;

-

-	/* we should turn codec and anti-pop first */

-	jz_codec_anti_pop(controller->i2s_codec, mode);

-

-	if (mode & CODEC_RMODE){

-/*

-		jz_codec_set_channels(codec, 2, CODEC_RMODE);

-		jz_codec_set_format(codec, 8, CODEC_RMODE);

-		jz_codec_set_speed(codec, 8000, CODEC_RMODE);

-*/

-		jz_codec_set_channels(codec, 2, CODEC_RMODE);

-		jz_codec_set_format(codec, 16, CODEC_RMODE);

-		jz_codec_set_speed(codec, 44100, CODEC_RMODE);

-		codec->user_need_mono = 0;

-

-		set_controller_triger(controller, &in_endpoint, codec->record_codec_channel, codec->record_format);

-	}

-	if (mode & CODEC_WMODE) {

-		jz_codec_set_channels(codec, 2, CODEC_WMODE);

-		jz_codec_set_format(codec, 16, CODEC_WMODE);

-		jz_codec_set_speed(codec, 44100, CODEC_WMODE);

-		set_controller_triger(controller, &out_endpoint, codec->replay_codec_channel, codec->replay_format);

-	}

-

-	DPRINT_IOC("============ default_codec record ===============\n"

-		   "format	= %d\n"

-		   "channels	= %d\n"

-		   "rate	= %d\n"

-		   "dma one tran bit = %d\n",

-		   codec->record_format, codec->record_codec_channel,

-		   codec->record_audio_rate, in_endpoint.dma.onetrans_bit);

-

-	DPRINT_IOC("============ default_codec replay ===============\n"

-		   "format	= %d\n"

-		   "channels	= %d\n"

-		   "rate	= %d\n"

-		   "dma one tran bit = %d\n",

-		   codec->replay_format, codec->replay_codec_channel,

-		   codec->replay_audio_rate, out_endpoint.dma.onetrans_bit);

-

-	jz_codec_select_mode(controller->i2s_codec, mode);

-

-	/* note: reset AIC  protected REG_AIC_I2SCR.ECCLK is setting */

-	if (reset) {

-		down(&controller->i2s_codec->i2s_sem);

-		//__i2s_enable_transmit_dma();

-		//__i2s_enable_receive_dma();

-		//__i2s_enable_replay();

-		__i2s_enable();

-		up(&controller->i2s_codec->i2s_sem);

-	}

-	//reinit codec option

-

-	//DUMP_AIC_REGS();

-	DPRINT_TRC(".... jz_audio_open\n");

-

-	g_play_first = 0;

-

-	LEAVE();

-	return 0;

-}

-

-static int jz_audio_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)

-{

-	long	rc = -EINVAL;

-	int	val = 0;

-	int	mode = 0;

-

-	struct jz_i2s_controller_info *controller = (struct jz_i2s_controller_info *) file->private_data;

-	struct i2s_codec *codec = controller->i2s_codec;

-	audio_pipe	*pin_endpoint = controller->pin_endpoint;

-	audio_pipe	*pout_endpoint = controller->pout_endpoint;

-

-	ENTER();

-

-	DPRINT_IOC("[dsp IOCTL] --------------------------------\n");

-	DPRINT_IOC(" dsp IOCTL %s cmd = (0x%08x), arg = %lu\n", __FUNCTION__, cmd, arg);

-	DPRINT_DSP_IOC_CMD(cmd);

-	DPRINT_IOC("[dsp IOCTL] --------------------------------\n");

-

-	if (file->f_mode & FMODE_READ) {

-		mode |= CODEC_RMODE;

-	}

-	if (file->f_mode & FMODE_WRITE) {

-		mode |= CODEC_WMODE;

-	}

-

-	switch (cmd) {

-

-	case OSS_GETVERSION:

-		rc = put_user(SOUND_VERSION, (int *)arg);

-		break;

-	case SNDCTL_DSP_RESET:

-		break;

-

-	case SNDCTL_DSP_SYNC:

-		if (mode & CODEC_WMODE) {

-			if (pout_endpoint) {

-				audio_sync_endpoint(pout_endpoint);

-			}

-		}

-		rc = 1;

-		break;

-

-	case SNDCTL_DSP_SPEED:

-		/* set smaple rate */

-		if (get_user(val, (int *)arg)) {

-			rc = -EFAULT;

-		}

-		//printk("SNDCTL_DSP_SPEED ... set to %d\n", val);

-		val = jz_codec_set_speed(codec, val, mode);

-		rc = put_user(val, (int *)arg);

-		break;

-

-	case SNDCTL_DSP_STEREO:

-		/* set stereo or mono channel */

-		if (get_user(val, (int *)arg)) {

-		    rc = -EFAULT;

-		}

-

-		jz_codec_set_channels(controller->i2s_codec, val ? 2 : 1, mode);

-

-		if (mode & CODEC_RMODE) {

-			set_controller_triger(controller, pin_endpoint,

-					      codec->record_codec_channel, codec->record_format);

-		}

-

-		if (mode & CODEC_WMODE) {

-			set_controller_triger(controller, pout_endpoint,

-					      codec->replay_codec_channel, codec->replay_format);

-		}

-

-		rc = 1;

-		break;

-

-	case SNDCTL_DSP_GETBLKSIZE:

-	{

-		// It seems that device could only be open with one mode (R or W)

-		int fragsize = 0;

-		if (mode & CODEC_RMODE) {

-			fragsize = pin_endpoint->fragsize;

-		}

-		if (mode & CODEC_WMODE) {

-			fragsize = pout_endpoint->fragsize;

-		}

-		rc = put_user(fragsize, (int *)arg);

-		break;

-	}

-

-	case SNDCTL_DSP_GETFMTS:

-		/* Returns a mask of supported sample format*/

-		rc = put_user(AFMT_U8 | AFMT_S16_LE, (int *)arg);

-		break;

-

-	case SNDCTL_DSP_SETFMT:

-		/* Select sample format */

-		if (get_user(val, (int *)arg)) {

-			rc = -EFAULT;

-		}

-

-		printk("\nSNDCTL_DSP_SETFMT ... set to %d\n", val);

-

-		if (val == AFMT_QUERY) {

-			if (mode & CODEC_RMODE) {

-				val = codec->record_format;

-			} else {

-				val = codec->replay_format;

-			}

-		} else {

-			val = jz_codec_set_format(codec, val, mode);

-			if (mode & CODEC_RMODE) {

-				if (codec->user_need_mono) {

-					endpoint_set_filter(pin_endpoint, val, 1);

-				} else {

-					endpoint_set_filter(pin_endpoint, val, 2);

-				}

-

-				set_controller_triger(controller, pin_endpoint,

-						      codec->record_codec_channel, codec->record_format);

-			}

-			if (mode & CODEC_WMODE) {

-				set_controller_triger(controller, pout_endpoint,

-						      codec->replay_codec_channel, codec->replay_format);

-			}

-		}

-

-		rc = put_user(val, (int *)arg);

-		break;

-

-	case SNDCTL_DSP_CHANNELS:

-		if (get_user(val, (int *)arg)) {

-			rc = -EFAULT;

-		}

-		//printk("\nSNDCTL_DSP_CHANNELS ... set to %d\n", val);

-

-		/* if mono, change to 2, and set 1 to codec->user_need_mono */

-		if (mode & CODEC_RMODE) {

-			if (val == 1) {

-				val = 2;

-				codec->user_need_mono = 1;

-

-			} else {

-				codec->user_need_mono = 0;

-			}

-		}

-

-		/* Following lines could be marked as nothing will be changed */

-		jz_codec_set_channels(codec, val, mode);

-

-		if (mode & CODEC_RMODE) {

-			/* Set filter according to channel count */

-			if (codec->user_need_mono) {

-				endpoint_set_filter(pin_endpoint, codec->record_format, 1);

-			} else {

-				endpoint_set_filter(pin_endpoint, codec->record_format, 2);

-			}

-

-			set_controller_triger(controller, pin_endpoint,

-					      codec->record_codec_channel, codec->record_format);

-		}

-		if (mode & CODEC_WMODE) {

-			set_controller_triger(controller, pout_endpoint,

-					      codec->replay_codec_channel, codec->replay_format);

-		}

-

-		/* Restore for return value */

-		if (codec->user_need_mono) {

-			val = 1;

-		}

-

-		rc = put_user(val, (int *)arg);

-		break;

-

-	case SNDCTL_DSP_POST:

-		/* FIXME: the same as RESET ?? */

-		break;

-

-	case SNDCTL_DSP_SUBDIVIDE:

-		break;

-

-	case SNDCTL_DSP_SETFRAGMENT:

-		rc = get_user(val, (long *) arg);

-		if (rc != -EINVAL) {

-			int newfragsize, newfragstotal;

-			newfragsize = 1 << (val & 0xFFFF);

-			if (newfragsize < 4 * PAGE_SIZE) {

-				newfragsize = 4 * PAGE_SIZE;

-			}

-			if (newfragsize > (16 * PAGE_SIZE)) {

-				newfragsize = 16 * PAGE_SIZE;

-			}

-

-			newfragstotal = (val >> 16) & 0x7FFF;

-			if (newfragstotal < 2) {

-				newfragstotal = 2;

-			}

-			if (newfragstotal > 32) {

-				newfragstotal = 32;

-			}

-

-			if (mode & CODEC_RMODE) {

-				rc = audio_resizemem_endpoint(controller->pin_endpoint, newfragsize, newfragstotal);

-				if (!rc) {

-					rc = -EINVAL;

-				}

-			}

-			if (mode & CODEC_WMODE) {

-				rc = audio_resizemem_endpoint(controller->pout_endpoint, newfragsize, newfragstotal);

-				if (!rc) {

-					rc = -EINVAL;

-				}

-			}

-		}

-		break;

-

-	case SNDCTL_DSP_GETCAPS:

-		rc = put_user(DSP_CAP_REALTIME | DSP_CAP_BATCH, (int *)arg);

-		break;

-

-	case SNDCTL_DSP_NONBLOCK:

-		file->f_flags |= O_NONBLOCK;

-		rc = 0;

-		break;

-

-	case SNDCTL_DSP_SETDUPLEX:

-		rc = -EINVAL;

-		break;

-

-	case SNDCTL_DSP_GETOSPACE:

-	{

-		audio_buf_info abinfo;

-		if (!(mode & CODEC_WMODE)) {

-			return -EINVAL;

-		}

-		audio_get_endpoint_freesize(pout_endpoint, &abinfo);

-		rc = copy_to_user((void *)arg, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;

-		break;

-	}

-

-	case SNDCTL_DSP_GETISPACE:

-	{

-		audio_buf_info abinfo;

-		if (!(mode & CODEC_RMODE)) {

-			return -EINVAL;

-		}

-		audio_get_endpoint_freesize(controller->pin_endpoint, &abinfo);

-		rc = copy_to_user((void *)arg, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;

-		break;

-	}

-

-	case SNDCTL_DSP_GETTRIGGER:

-		val = 0;

-		if ((mode & CODEC_RMODE) && controller->pin_endpoint) {

-			val |= PCM_ENABLE_INPUT;

-		}

-		if ((mode & CODEC_WMODE) && controller->pout_endpoint) {

-			val |= PCM_ENABLE_OUTPUT;

-		}

-		rc = put_user(val, (int *)arg);

-

-		break;

-

-	case SNDCTL_DSP_SETTRIGGER:

-		if (get_user(val, (int *)arg)) {

-			rc = -EFAULT;

-		}

-		break;

-

-	case SNDCTL_DSP_GETIPTR:

-	{

-		count_info cinfo;

-		if (!(mode & CODEC_RMODE)) {

-			rc = -EINVAL;

-		}

-		rc = copy_to_user((void *)arg, &cinfo, sizeof(cinfo));

-		break;

-	}

-

-	case SNDCTL_DSP_GETOPTR:

-	{

-		count_info cinfo;

-		if (!(mode & CODEC_WMODE)) {

-			rc = -EINVAL;

-		}

-		rc = copy_to_user((void *) arg, &cinfo, sizeof(cinfo));

-		break;

-	}

-

-	case SNDCTL_DSP_GETODELAY:

-	{

-		// fix me !!!

-		int unfinish = 0;

-		if (!(mode & CODEC_WMODE)) {

-			rc = -EINVAL;

-		}

-		rc = put_user(unfinish, (int *) arg);

-		break;

-	}

-

-	case SOUND_PCM_READ_RATE:

-		if (mode  & CODEC_RMODE) {

-			//printk("\nSOUND_PCM_READ_RATE = %d\n", codec->record_audio_rate);

-			rc = put_user(codec->record_audio_rate, (int *)arg);

-		}

-		if (mode & CODEC_WMODE) {

-			//printk("\nSOUND_PCM_READ_RATE = %d\n", codec->replay_audio_rate);

-			rc = put_user(codec->replay_audio_rate, (int *)arg);

-		}

-		break;

-

-	case SOUND_PCM_READ_CHANNELS:

-		if (mode & CODEC_RMODE) {

-			//printk("\nSOUND_PCM_READ_RATE = %d\n", codec->record_codec_channel);

-			rc = put_user(codec->record_codec_channel, (int *)arg);

-		}

-		if (mode & CODEC_WMODE) {

-			//printk("\nSOUND_PCM_READ_RATE = %d\n", codec->replay_codec_channel);

-			rc = put_user(codec->replay_codec_channel, (int *)arg);

-		}

-		break;

-

-	case SOUND_PCM_READ_BITS:

-		if (mode & CODEC_RMODE) {

-			rc = put_user((codec->record_format & (AFMT_S8 | AFMT_U8)) ? 8 : 16, (int *)arg);

-		}

-		if (mode & CODEC_WMODE) {

-			rc = put_user((codec->record_format & (AFMT_S8 | AFMT_U8)) ? 8 : 16, (int *)arg);

-		}

-		break;

-

-	case SNDCTL_DSP_MAPINBUF:

-	case SNDCTL_DSP_MAPOUTBUF:

-	case SNDCTL_DSP_SETSYNCRO:

-	case SOUND_PCM_WRITE_FILTER:

-	case SOUND_PCM_READ_FILTER:

-		rc = -EINVAL;

-		break;

-#if 0

-	/* may be for msm only */

-	case AUDIO_GET_CONFIG:

- 		break;

-

-	case AUDIO_SET_CONFIG:

-		break;

-#endif

-	default:

-		printk("%s[%s]:%d---no cmd\n",__FILE__,__FUNCTION__,__LINE__);

-		break;

-	}

-

-	LEAVE();

-

-	return rc;

-}

-

-static inline int endpoint_put_userdata(audio_pipe *endpoint, const char __user *buffer, size_t count)

-{

-	unsigned long	flags;

-	audio_node	*node;

-

-	ENTER();

-	DPRINT("<<<< put_userdata\n");

-

-	AUDIO_LOCK(endpoint->lock, flags);

-	node = get_audio_freenode(endpoint->mem);

-	AUDIO_UNLOCK(endpoint->lock, flags);

-

-	// For non-block mode

-	if (endpoint->is_non_block && !node) {

-		LEAVE();

-		return 0;

-	}

-

-	// For block mode, wait free node

-	while (!node) {

-		DPRINT("wait ----------\n");

-

-		AUDIO_LOCK(endpoint->lock, flags);

-		DUMP_LIST((audio_head *)endpoint->mem);

-		DUMP_NODE(endpoint->savenode, "SN");

-		AUDIO_UNLOCK(endpoint->lock, flags);

-

-		// wait available node

-		wait_event_interruptible(endpoint->q_full, (endpoint->avialable_couter >= 1));

-

-		AUDIO_LOCK(endpoint->lock, flags);

-		node = get_audio_freenode(endpoint->mem);

-		endpoint->avialable_couter = 0;

-		AUDIO_UNLOCK(endpoint->lock, flags);

-	}

-

-	if (copy_from_user((void *)node->pBuf, buffer, count)) {

-		printk("JZ I2S: copy_from_user failed !\n");

-		return -EFAULT;

-	}

-	dma_cache_wback_inv((unsigned long)node->pBuf,(unsigned long)count);

-	node->start = 0;

-	node->end = count;

-	AUDIO_LOCK(endpoint->lock, flags);

-	put_audio_usenode(endpoint->mem, node);

-	AUDIO_UNLOCK(endpoint->lock, flags);

-

-	LEAVE();

-

-	return count;

-}

-

-static ssize_t jz_audio_write(struct file *file, const char __user *buffer, size_t count, loff_t *ppos)

-{

-	struct jz_i2s_controller_info *controller = (struct jz_i2s_controller_info *)file->private_data;

-	audio_pipe *pout_endpoint = controller->pout_endpoint;

-	struct i2s_codec *codec = (struct i2s_codec *)controller->i2s_codec;

-	size_t	usecount = 0;

-	int	bat_cnt = -1;

-	int	rem_cnt = 0;

-

-	if (!g_play_first) {

-		// first play, trun on dac mute

-		codec_ioctrl(codec, CODEC_FIRST_OUTPUT, 0);

-		g_play_first = 1;

-	}

-

-	ENTER();

-

-//	dump_dlv_regs(__FUNCTION__);

-//	dump_aic_regs(__FUNCTION__);

-

-	DPRINT("write data count = %d\n", count);

-

-	while (count >= pout_endpoint->fragsize) {

-

-		bat_cnt = endpoint_put_userdata(pout_endpoint,

-						&(buffer[usecount]),

-						pout_endpoint->fragsize);

-		// Prepare data success.

-		if (bat_cnt > 0) {

-			usecount += bat_cnt;

-			count -= bat_cnt;

-			DPRINT("bat_cnt = %d\n", bat_cnt);

-		}

-		// Perhaps non node is avialable.

-		else if (bat_cnt == 0) {

-			DPRINT("bat_cnt == 0\n");

-			break;

-		}

-		// Error occured.

-		else {

-			// break and handle prepared data.

-			if (usecount > 0) {

-				DPRINT("bat_cnt < 0, usecount > 0\n");

-				break;

-			}

-			// Has not prepared any data and return error when prepared data.

-			else {

-				DPRINT("bat_cnt < 0, usecount == 0\n");

-				return bat_cnt;

-			}

-		}

-	}

-

-	DPRINT("count = %d\n", count);

-

-	// Prepare few data or remain data after below code.

-	if (bat_cnt != 0 && count >= 32) {

-		DPRINT("check point 2 ... count = %d\n", count);

-		rem_cnt = endpoint_put_userdata(pout_endpoint, &buffer[usecount], count);

-		if (rem_cnt > 0) {

-			usecount += rem_cnt;

-			count -= rem_cnt;

-			DPRINT("check point 3 ... rem_cnt = %d\n", rem_cnt);

-		} else if (rem_cnt <= 0) {

-			// Not success... return Error.

-			if (usecount == 0) {

-				DPRINT("rem_cnt <= 0, usecount == 0\n");

-				return rem_cnt;

-			}

-			// Go on handle prepared data, ignore the error.

-			else {

-				DPRINT("rem_cnt <= 0, usecount != 0, usecount = %d\n", usecount);

-			}

-		}

-	}

-

-	// Handle prepared data.

-	if (usecount > 0) {

-		unsigned long	flags;

-		audio_node	*node;

-		AUDIO_LOCK(pout_endpoint->lock, flags);

-		if ((pout_endpoint->trans_state & PIPE_TRANS) == 0) {

-			node = get_audio_usenode(pout_endpoint->mem);

-			if (node) {

-				unsigned int start;

-				start = trystart_endpoint_out(controller, node);

-				if (start == 0) {

-					printk("JZ I2S: trystart_endpoint_out error\n");

-				}

-			}

-		}

-		AUDIO_UNLOCK(pout_endpoint->lock, flags);

-	}

-

-	DPRINT("----write data usecount = %d, count = %d\n", usecount, count);

-	BUG_ON(count < 0);

-	LEAVE();

-

-	return usecount + (count < 32 ? count : 0);

-}

-

-/**

- *  Copy recorded sound data from 'use' link list to userspace

- */

-static inline int endpoint_get_userdata(audio_pipe *endpoint, const char __user *buffer, size_t count)

-{

-	unsigned long	flags;

-	audio_node	*node = last_read_node;

-	int	ret;

-

-	/* counter for node buffer, raw data */

-	int	node_buff_cnt = 0;

-

-	ENTER();

-

-	if (!node) {

-		AUDIO_LOCK(endpoint->lock, flags);

-		node = get_audio_usenode(endpoint->mem);

-		AUDIO_UNLOCK(endpoint->lock, flags);

-

-		if (node && endpoint->filter) {

-			node_buff_cnt = node->end - node->start;

-			node_buff_cnt = endpoint->filter((void *)(node->pBuf + node->start), node_buff_cnt);

-			node->end = node->start + node_buff_cnt;

-		}

-	}

-

-	DPRINT(">>>> %s mode\n", endpoint->is_non_block ? "non block" : "block");

-

-	// For non-block mode

-	if (endpoint->is_non_block && !node) {

-		return 0;

-	}

-

-	// For block mode, wait node which full filled data

-	while (!node) {

-		if ((endpoint->trans_state & PIPE_TRANS) == 0 ) {

-			DPRINT("DMA trans has not been started !\n");

-			return -1;

-		}

-

-		AUDIO_LOCK(endpoint->lock, flags);

-		DUMP_LIST((audio_head *)endpoint->mem);

-		DUMP_NODE(endpoint->savenode, "SN");

-		AUDIO_UNLOCK(endpoint->lock, flags);

-

-		DPRINT("record stereo ... wait pipe_sem ----------\n");

-

-		// wait available node

-//		interruptible_sleep_on(&endpoint->q_full);

-		wait_event_interruptible(endpoint->q_full, endpoint->avialable_couter >= 1);

-

-		AUDIO_LOCK(endpoint->lock, flags);

-		node = get_audio_usenode(endpoint->mem);

-		endpoint->avialable_couter = 0;

-		AUDIO_UNLOCK(endpoint->lock, flags);

-

-		if (node && endpoint->filter) {

-			node_buff_cnt = node->end - node->start;

-			node_buff_cnt = endpoint->filter((void *)(node->pBuf + node->start), node_buff_cnt);

-			node->end = node->start + node_buff_cnt;

-		}

-	}

-

-	if (node && (node_buff_cnt = node->end - node->start)) {

-		DPRINT("node_buff_cnt = %d, count = %d\n", node_buff_cnt, count);

-

-		if (count >= (size_t)node_buff_cnt) {

-			DPRINT(">>>> count >= fixed_buff_cnt, copy_to_user count = %d\n", node_buff_cnt);

-			ret = copy_to_user((void *)buffer, (void *)(node->pBuf + node->start), node_buff_cnt);

-			if (ret) {

-				printk("JZ I2S: copy_to_user failed, return %d\n", ret);

-				return -EFAULT;

-			}

-			put_audio_freenode(endpoint->mem, node);

-			last_read_node = NULL;

-		} else {

-			DPRINT(">>>> count < fixed_buff_cnt, copy_to_user count = %d\n", count);

-			ret = copy_to_user((void *)buffer,(void *)(node->pBuf + node->start), count);

-			if (ret) {

-				printk("JZ I2S: copy_to_user failed, return %d\n", ret);

-				return -EFAULT;

-			}

-			node->start += count;

-			last_read_node = node;

-		}

-	}

-

-	LEAVE();

-	return (node_buff_cnt < count ? node_buff_cnt : count);

-}

-

-static ssize_t jz_audio_read(struct file *file, char __user *buffer, size_t count, loff_t *ppos)

-{

-	struct jz_i2s_controller_info *controller = (struct jz_i2s_controller_info *)file->private_data;

-	audio_pipe	*pin_endpoint = controller->pin_endpoint;

-	audio_node	*node;

-	unsigned long	flags;

-	int		mcount, usecount = 0;

-

-	ENTER();

-

-//	dump_dlv_regs(__FUNCTION__);

-//	dump_aic_regs(__FUNCTION__);

-

-	if (count == 0) {

-		DPRINT("@@@@ jz_audio_read count == 0\n");

-		return 0;

-	}

-

-	AUDIO_LOCK(pin_endpoint->lock, flags);

-

-	DUMP_LIST((audio_head *)pin_endpoint->mem);

-	DUMP_NODE(pin_endpoint->savenode, "SN");

-

-	DPRINT("@@@@ jz_audio_read, pin_endpoint->trans_state = 0x%08x\n",

-	       pin_endpoint->trans_state);

-

-	if ((pin_endpoint->trans_state & PIPE_TRANS) == 0) {

-		DPRINT("@@@@ jz_audio_read, PIPE_TRANS\n");

-		node = get_audio_freenode(pin_endpoint->mem);

-		if (node) {

-			unsigned int start;

-			DPRINT("@@@@ jz_audio_read, trystart_endpoint_in\n");

-//			pin_endpoint->fragsize = count;

-			node->end = pin_endpoint->fragsize;

-

-			start = trystart_endpoint_in(controller, node);

-			if (start == 0) {

-				DPRINT("@@@@ Error ! jz_audio_read, start == 0\n");

-				put_audio_freenode(pin_endpoint->mem, node);

-			}

-		}

-	}

-	AUDIO_UNLOCK(pin_endpoint->lock, flags);

-

-	DUMP_AIC_REGS(__FUNCTION__);

-	DUMP_CODEC_REGS(__FUNCTION__);

-	//dump_dlv_regs(__FUNCTION__);

-	DPRINT("@@@@ count = %d\n", count);

-

-	do{

-		mcount = endpoint_get_userdata(pin_endpoint, &buffer[usecount], count);

-

-		DPRINT("@@@@ jz_audio_read, mcount = %d, usecount = %d\n", mcount, usecount);

-

-		if (mcount < 0) {

-			DPRINT("@@@@ jz_audio_read, mcount < 0, %d\n", mcount);

-			if (usecount > 0) {

-				break;

-			} else {

-				return mcount;

-			}

-		} else if (mcount == 0) {

-			DPRINT("@@@@ jz_audio_read, mcount == 0\n");

-			break;

-		} else {

-			usecount += mcount;

-			count -= mcount;

-			DPRINT("@@@@ jz_audio_read, mcount > 0, %d\n", mcount);

-		}

-	} while (count > 0);

-

-	DPRINT("@@@@ jz_audio_read, usecount = %d\n", usecount);

-

-	LEAVE();

-	return usecount;

-}

-

-/* static struct file_operations jz_i2s_audio_fops */

-static struct file_operations jz_i2s_audio_fops = {

-	owner:		THIS_MODULE,

-	open:		jz_audio_open,

-	release:	jz_audio_release,

-	write:		jz_audio_write,

-	read:		jz_audio_read,

-	ioctl:		jz_audio_ioctl

-};

-

-static void __init attach_jz_i2s(struct jz_i2s_controller_info *controller)

-{

-	char	*name = NULL;

-	int	adev = 0; /* No of Audio device. */

-

-	ENTER();

-

-	name = controller->name;

-

-	/* Initialize I2S CODEC and register /dev/mixer. */

-	if (jz_i2s_codec_init(controller) <= 0) {

-		goto mixer_failed;

-	}

-

-	/* Initialize AIC controller and reset it. */

-	jz_i2s_reinit_hw(controller->i2s_codec,1);

-	adev = register_sound_dsp(&jz_i2s_audio_fops, -1);

-	if (adev < 0) {

-		goto audio_failed;

-	}

-

-	controller->dev_audio = adev;

-

-	LEAVE();

-

-	return;

-mixer_failed:

-

-audio_failed:

-	unregister_sound_dsp(adev);

-

-	LEAVE();

-	return;

-}

-

-static void __exit unload_jz_i2s(struct jz_i2s_controller_info *controller)

-{

-	jz_i2s_reinit_hw(controller->i2s_codec,0);

-}

-

-//--------------------------------------------------------------------

-#ifdef CONFIG_PM

-static int jz_i2s_suspend(struct platform_device *pdev, pm_message_t state)

-{

-	int i;

-	struct i2s_codec *codec;

-	for(i = 0;i < NR_I2S; i++){

-		codec = &the_codecs[i];

-		if (codec && codec->codecs_ioctrl) {

-			codec->codecs_ioctrl(codec, CODEC_I2S_SUSPEND, 0);

-		}

-	}

-

-#if 0

-	__i2s_disable();

-	mdelay(5);

-	__i2s_disable_record();

-	__i2s_disable_replay();

-	__i2s_disable_loopback();

-#endif

-	printk("Aic and codec are suspended!\n");

-	return 0;

-}

-

-static int jz_i2s_resume(struct platform_device *pdev)

-{

-	int i;

-	struct i2s_codec *codec;

-	for(i = 0;i < NR_I2S; i++){

-		codec = &the_codecs[i];

-		if (codec && codec->codecs_ioctrl) {

-			codec->codecs_ioctrl(codec, CODEC_I2S_RESUME, 0);

-		}

-	}

-	return 0;

-}

-#endif /* CONFIG_PM */

-

-static int __init probe_jz_i2s(struct jz_i2s_controller_info **controller)

-{

-	struct jz_i2s_controller_info *ctrl;

-

-	ENTER();

-	ctrl = kmalloc(sizeof(struct jz_i2s_controller_info), GFP_KERNEL);

-	if (ctrl == NULL) {

-		printk(KERN_ERR "Jz I2S Controller: out of memory.\n");

-		return -ENOMEM;

-	}

-	ctrl->name = "Jz I2S controller";

-	ctrl->pout_endpoint = 0;

-	ctrl->pin_endpoint = 0;

-	ctrl->error = 0;

-	//ctrl->i2s_codec->use_mic_line_flag = USE_NONE;

-

-	*controller = ctrl;

-

-	LEAVE();

-

-	return 0;

-}

-

-void i2s_controller_init(void)

-{

-	unsigned int aicfr;

-	unsigned int aiccr;

-	//init cpm clock, use ext clock;

-

-	ENTER();

-

-	/* Select exclk as i2s clock */

-	cpm_set_clock(CGU_I2SCLK, JZ_EXTAL);

-

-	aicfr = (8 << 12) | (8 << 8) | (AIC_FR_ICDC | AIC_FR_LSMP | AIC_FR_AUSEL);

-	REG_AIC_FR = aicfr;

-

-	aiccr = REG_AIC_CR;

-	aiccr &= (~(AIC_CR_EREC | AIC_CR_ERPL | AIC_CR_TDMS | AIC_CR_RDMS));

-	REG_AIC_CR = aiccr;

-

-	LEAVE();

-}

-

-static int __init init_jz_i2s(struct platform_device *pdev)

-{

-	struct i2s_codec *default_codec = &(the_codecs[0]);

-	int errno;

-	int fragsize;

-	int fragstotal;

-

-	cpm_start_clock(CGM_AIC);

-

-	REG_AIC_I2SCR |= AIC_I2SCR_ESCLK;

-

-	i2s_controller_init();

-	if (default_codec->codecs_ioctrl == NULL) {

-		printk("default_codec: not ready!");

-		return -1;

-	}

-

-	//default_codec->codecs_ioctrl(default_codec, CODEC_SET_MODE, 0);

-	default_codec->codecs_ioctrl(default_codec, CODEC_INIT, 0);

-

-	if ((errno = probe_jz_i2s(&the_i2s_controller)) < 0) {

-		return errno;

-	}

-

-	/* May be external CODEC need it ...

-	 * default_codec->codecs_ioctrl(default_codec, CODEC_SET_GPIO_PIN, 0);

-	 */

-	attach_jz_i2s(the_i2s_controller);

-

-	/* Actually, the handler function of the command do nothing ...

-	 * default_codec->codecs_ioctrl(default_codec, CODEC_SET_STARTUP_PARAM, 0);

-	 * default_codec->codecs_ioctrl(default_codec, CODEC_SET_STARTUP_PARAM, 0);

-	 */

-

-	/* Now the command is not supported by DLV CODEC ...

-	 * default_codec->codecs_ioctrl(default_codec, CODEC_SET_VOLUME_TABLE, 0);

-	 */

-	fragsize = JZCODEC_RW_BUFFER_SIZE * PAGE_SIZE;

-	fragstotal = JZCODEC_RW_BUFFER_TOTAL;

-

-	audio_init_endpoint(&out_endpoint, fragsize, fragstotal);

-	audio_init_endpoint(&in_endpoint, fragsize, fragstotal);

-

-	printk("JZ I2S OSS audio driver initialized\n");

-

-	LEAVE();

-

-	return 0;

-}

-

-static void __exit cleanup_jz_i2s(void)

-{

-#ifdef CONFIG_PM

-	/* pm_unregister(i2s_controller->pm); */

-#endif

-	struct i2s_codec *default_codec = &the_codecs[0];

-	unload_jz_i2s(the_i2s_controller);

-	the_i2s_controller = NULL;

-	audio_deinit_endpoint(&out_endpoint);

-	audio_deinit_endpoint(&in_endpoint);

-	default_codec->codecs_ioctrl(default_codec, CODEC_CLEAR_MODE, 0);

-}

-

-static struct platform_driver snd_plat_driver = {

-	.probe	=  init_jz_i2s,

-	.driver	= {

-		.name	= "mixer",

-		.owner	= THIS_MODULE,

-	},

-	.suspend	= jz_i2s_suspend,

-	.resume		= jz_i2s_resume,

-};

-

-static int __init snd_init(void)

-{

-	return platform_driver_register(&snd_plat_driver);

-}

-

-module_init(snd_init);

-module_exit(cleanup_jz_i2s);

+/*
+ * Linux/sound/oss/jz_i2s.c
+ *
+ * Sound driver for Ingenic Jz4750 MIPS processor
+ *
+ * 2009-12-xx	Steven <dsqiu@ingenic.cn>
+ * 2010-01-xx	Jason <xwang@ingenic.cn>
+ *
+ * Copyright (c) Ingenic Semiconductor Co., Ltd.
+ */
+
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/pm.h>
+#include <linux/sched.h>
+#include <linux/delay.h>
+#include <linux/sound.h>
+#include <linux/slab.h>
+#include <sound/core.h>
+#include <sound/initval.h>
+#include <linux/proc_fs.h>
+#include <linux/soundcard.h>
+#include <linux/dma-mapping.h>
+#include <linux/mutex.h>
+#include <linux/mm.h>
+#include <asm/hardirq.h>
+#include <asm/jzsoc.h>
+#include "sound_config.h"
+
+#include <linux/miscdevice.h>
+#include <linux/platform_device.h>
+//#include <linux/msm_audio.h>
+#include "jz_codec.h"
+#include "jz_i2s_dbg.h"
+
+//#if defined CONFIG_PM
+//#undef CONFIG_PM
+//#endif
+
+#define DMA_ID_I2S_TX			DMA_ID_AIC_TX
+#define DMA_ID_I2S_RX			DMA_ID_AIC_RX
+
+// reference to dma.c
+#define DMA_TX_CHAN			6
+#define DMA_RX_CHAN			7
+
+#define NR_I2S				2
+
+#define JZCODEC_RW_BUFFER_SIZE		1
+#define JZCODEC_RW_BUFFER_TOTAL		4
+
+#define AUDIOBUF_STATE_FREE		0
+
+#define NOMAL_STOP			0
+#define FORCE_STOP			1
+#define PIPE_TRANS			1
+
+#define AUDIO_LOCK(lock, flags)		spin_lock_irqsave(&lock, flags)
+#define AUDIO_UNLOCK(lock, flags)	spin_unlock_irqrestore(&lock, flags)
+
+#define THIS_AUDIO_NODE(p)		list_entry(p, audio_node, list)
+#define ALIGN_PAGE_SIZE(x)		(((x) + PAGE_SIZE) / PAGE_SIZE * PAGE_SIZE)
+
+typedef struct {
+	struct list_head list;
+	unsigned int pBuf;
+#ifdef Q_DEBUG
+	unsigned int pBufID;
+#endif
+	unsigned int start;
+	unsigned int end;
+	unsigned int phyaddr;
+} audio_node;
+
+typedef struct {
+	unsigned int fact;
+	unsigned int datasize;
+	unsigned int listsize;
+	struct list_head free;
+	struct list_head use;
+} audio_head;
+
+typedef struct
+{
+	int ch;
+	int onetrans_bit;
+	int rw;
+	unsigned int *trans_addr;
+	unsigned int *trans_count;
+	unsigned int *trans_mode;
+	unsigned int *data_addr;
+} audio_dma_type;
+
+typedef struct __audio_pipe
+{
+	spinlock_t	lock;
+	audio_dma_type	dma;
+	unsigned int	*mem;
+	audio_node	*savenode;
+
+	int	fragsize;
+	int 	fragstotal;
+	int	is_non_block;
+	volatile int	trans_state;
+
+	wait_queue_head_t	q_full;
+	int			avialable_couter;
+
+#ifdef WORK_QUEUE_MODE
+	struct work_struct	work;
+#endif
+	void (*handle)(struct __audio_pipe *endpoint);
+	int (*filter)(void *buff, int cnt);
+} audio_pipe;
+
+struct i2s_codec
+{
+	/* I2S controller connected with */
+	void	*private_data;
+	char	*name;
+	int	id;
+	int	dev_mixer;
+
+	int	use_mic_line_flag;
+	int	audio_volume;
+	int	mic_gain;
+	int	bass_gain;
+
+	unsigned short	record_audio_rate;
+	unsigned short	replay_audio_rate;
+
+	short	replay_codec_channel;
+	short	record_codec_channel;
+
+	short	replay_format;
+	short	record_format;
+
+	int	audiomute;
+	int	user_need_mono;
+
+	struct semaphore i2s_sem;
+	int (*codecs_ioctrl)(void *context, unsigned int cmd, unsigned long arg);
+};
+
+struct jz_i2s_controller_info
+{
+	char		*name;
+	audio_pipe	*pout_endpoint;
+	audio_pipe	*pin_endpoint;
+	int		dev_audio;
+	unsigned int	error;	/* over / underrun */
+
+	struct i2s_codec *i2s_codec;
+
+#ifdef CONFIG_PM
+	struct pm_dev	*pm;
+#endif
+};
+
+
+/*
+ * Global variates
+ */
+static audio_pipe out_endpoint = {
+	.mem		= 0,
+	.savenode	= 0,
+	.fragsize	= 0,
+	.fragstotal	= 0,
+	.trans_state	= 0,
+};
+
+static audio_pipe in_endpoint= {
+	.mem		= 0,
+	.savenode	= 0,
+	.fragsize	= 0,
+	.fragstotal	= 0,
+	.trans_state	= 0,
+};
+
+static struct i2s_codec the_codecs[NR_I2S];
+static struct jz_i2s_controller_info *the_i2s_controller = NULL;
+static int audio_mix_modcnt = 0;
+static audio_node *last_read_node = NULL;
+static int g_play_first = 0;
+
+#ifdef CONFIG_JZ_EBOOK_HARD
+int audio_device_open = 0;
+volatile int audio_device_pm_state = 0;
+#endif
+
+/*
+ * Debug functions
+ */
+#ifdef DMA_DEBUG
+void dump_dma(unsigned int dmanr, const char *str)
+{
+	printk("DMA%d Registers, %s:\n", dmanr, str);
+	printk("\tDMACR	= 0x%08x\n", REG_DMAC_DMACR(dmanr/HALF_DMA_NUM));
+	printk("\tDSAR	= 0x%08x\n", REG_DMAC_DSAR(dmanr));
+	printk("\tDTAR	= 0x%08x\n", REG_DMAC_DTAR(dmanr));
+	printk("\tDTCR	= 0x%08x\n", REG_DMAC_DTCR(dmanr));
+
+	*(unsigned int *)0xb342010c = 0x18;
+
+	printk("\tDRSR	= 0x%08x, addr = 0x%08x\n", REG_DMAC_DRSR(dmanr), DMAC_DRSR(dmanr));
+	printk("\tDCCSR	= 0x%08x\n", REG_DMAC_DCCSR(dmanr));
+	printk("\tDCMD	= 0x%08x\n", REG_DMAC_DCMD(dmanr));
+	printk("\tDDA	= 0x%08x\n", REG_DMAC_DDA(dmanr));
+	printk("\tDMADBR= 0x%08x\n", REG_DMAC_DMADBR(dmanr/HALF_DMA_NUM));
+	printk("\tCPCCR = 0x%08x\n", REG_CPM_CPCCR);
+	printk("\tCPPCR = 0x%08x\n", REG_CPM_CPPCR0);
+	printk("\tREG_CPM_CLKGR0 = 0x%08x\n", REG_CPM_CLKGR0);
+	printk("\tREG_CPM_CLKGR1 = 0x%08x\n", REG_CPM_CLKGR1);
+}
+#endif
+
+#ifdef IOC_DEBUG
+void dsp_print_ioc_cmd(int cmd)
+{
+	int i;
+	int cmd_arr[] = {
+		OSS_GETVERSION,		SNDCTL_DSP_RESET,	SNDCTL_DSP_SYNC,
+		SNDCTL_DSP_SPEED,	SNDCTL_DSP_STEREO,	SNDCTL_DSP_GETBLKSIZE,
+		SNDCTL_DSP_GETFMTS,	SNDCTL_DSP_SETFMT,	SNDCTL_DSP_CHANNELS,
+		SNDCTL_DSP_POST,	SNDCTL_DSP_SUBDIVIDE,	SNDCTL_DSP_SETFRAGMENT,
+		SNDCTL_DSP_GETCAPS,	SNDCTL_DSP_NONBLOCK,	SNDCTL_DSP_SETDUPLEX,
+		SNDCTL_DSP_GETOSPACE,	SNDCTL_DSP_GETISPACE,	SNDCTL_DSP_GETTRIGGER,
+		SNDCTL_DSP_SETTRIGGER,	SNDCTL_DSP_GETIPTR,	SNDCTL_DSP_GETOPTR,
+		SNDCTL_DSP_GETODELAY,	SOUND_PCM_READ_RATE,	SOUND_PCM_READ_CHANNELS,
+		SOUND_PCM_READ_BITS,	SNDCTL_DSP_MAPINBUF,	SNDCTL_DSP_MAPOUTBUF,
+		SNDCTL_DSP_SETSYNCRO,	SOUND_PCM_READ_FILTER,	SOUND_PCM_WRITE_FILTER,
+//		AUDIO_GET_CONFIG,	AUDIO_SET_CONFIG
+	};
+	char *cmd_str[] = {
+		"OSS_GETVERSION",	"SNDCTL_DSP_RESET",	"SNDCTL_DSP_SYNC",
+		"SNDCTL_DSP_SPEED",	"SNDCTL_DSP_STEREO",	"SNDCTL_DSP_GETBLKSIZE",
+		"SNDCTL_DSP_GETFMTS",	"SNDCTL_DSP_SETFMT",	"SNDCTL_DSP_CHANNELS",
+		"SNDCTL_DSP_POST",	"SNDCTL_DSP_SUBDIVIDE",	"SNDCTL_DSP_SETFRAGMENT",
+		"SNDCTL_DSP_GETCAPS",	"SNDCTL_DSP_NONBLOCK",	"SNDCTL_DSP_SETDUPLEX",
+		"SNDCTL_DSP_GETOSPACE",	"SNDCTL_DSP_GETISPACE",	"SNDCTL_DSP_GETTRIGGER",
+		"SNDCTL_DSP_SETTRIGGER","SNDCTL_DSP_GETIPTR",	"SNDCTL_DSP_GETOPTR",
+		"SNDCTL_DSP_GETODELAY",	"SOUND_PCM_READ_RATE",	"SOUND_PCM_READ_CHANNELS",
+		"SOUND_PCM_READ_BITS",	"SNDCTL_DSP_MAPINBUF",	"SNDCTL_DSP_MAPOUTBUF",
+		"SNDCTL_DSP_SETSYNCRO",	"SOUND_PCM_READ_FILTER","SOUND_PCM_WRITE_FILTER",
+//		"AUDIO_GET_CONFIG",	"AUDIO_SET_CONFIG"
+	};
+
+	for ( i = 0; i < sizeof(cmd_arr) / sizeof(int); i++) {
+		if (cmd_arr[i] == cmd) {
+			printk("Command name : %s\n", cmd_str[i]);
+			return;
+		}
+	}
+
+	if (i == sizeof(cmd_arr) / sizeof(int)) {
+		printk("Unknown command\n");
+	}
+}
+
+void mixer_print_ioc_cmd(int cmd)
+{
+	int i;
+	int cmd_arr[] = {
+		SOUND_MIXER_INFO,	SOUND_OLD_MIXER_INFO,		SOUND_MIXER_READ_STEREODEVS,
+		SOUND_MIXER_READ_CAPS,	SOUND_MIXER_READ_DEVMASK,	SOUND_MIXER_READ_RECMASK,
+		SOUND_MIXER_READ_RECSRC,SOUND_MIXER_WRITE_SPEAKER,	SOUND_MIXER_WRITE_BASS,
+		SOUND_MIXER_READ_BASS,	SOUND_MIXER_WRITE_VOLUME,	SOUND_MIXER_READ_VOLUME,
+		SOUND_MIXER_WRITE_MIC,	SOUND_MIXER_READ_MIC,		SOUND_MIXER_WRITE_LINE,
+		SOUND_MIXER_READ_LINE,	SOUND_MIXER_WRITE_MUTE,		SOUND_MIXER_READ_MUTE,
+//		SND_SET_DEVICE,		SND_SET_VOLUME,
+//		SND_GET_NUM_ENDPOINTS,	SND_GET_ENDPOINT
+	};
+
+	char *cmd_str[] = {
+		"SOUND_MIXER_INFO",		"SOUND_OLD_MIXER_INFO",		"SOUND_MIXER_READ_STEREODEVS",
+		"SOUND_MIXER_READ_CAPS",	"SOUND_MIXER_READ_DEVMASK",	"SOUND_MIXER_READ_RECMASK",
+		"SOUND_MIXER_READ_RECSRC",	"SOUND_MIXER_WRITE_SPEAKER",	"SOUND_MIXER_WRITE_BASS",
+		"SOUND_MIXER_READ_BASS",	"SOUND_MIXER_WRITE_VOLUME",	"SOUND_MIXER_READ_VOLUME",
+		"SOUND_MIXER_WRITE_MIC",	"SOUND_MIXER_READ_MIC",		"SOUND_MIXER_WRITE_LINE",
+		"SOUND_MIXER_READ_LINE",	"SOUND_MIXER_WRITE_MUTE",	"SOUND_MIXER_READ_MUTE",
+//		"SND_SET_DEVICE",		"SND_SET_VOLUME",
+//		"SND_GET_NUM_ENDPOINTS",	"SND_GET_ENDPOINT"
+	};
+
+	for (i = 0; i < sizeof(cmd_arr) / sizeof(int); i++) {
+		if (cmd_arr[i] == cmd) {
+			printk("Command name : %s\n", cmd_str[i]);
+			return;
+		}
+	}
+
+	printk("Unknown command\n");
+}
+#endif
+
+//#ifdef REG_DEBUG
+void dump_aic_regs(const char *str)
+{
+	char *regname[] = {"aicfr","aiccr","aiccr1","aiccr2","i2scr","aicsr","acsr","i2ssr",
+			   "accar", "accdr", "acsar", "acsdr", "i2sdiv", "aicdr"};
+	int i;
+	unsigned int addr;
+
+	printk("AIC regs dump, %s\n", str);
+	for (i = 0; i <= 0x34; i += 4) {
+		addr = 0xb0020000 + i;
+		printk("%s\t0x%08x -> 0x%08x\n", regname[i/4], addr, *(unsigned int *)addr);
+	}
+}
+//#endif
+
+#ifdef BUF_DEBUG
+void dump_buf(char *buf, int dump_len, int bytes_in_line)
+{
+	int i;
+	printk("Buffer 0x%p:\n", buf);
+	for (i = 0; i < dump_len; i++) {
+		printk("%02x ", (unsigned char)buf[i]);
+		if ((i+1) % bytes_in_line == 0) {
+			printk("\n");
+		}
+	}
+	printk("\n");
+}
+#endif
+
+#ifdef Q_DEBUG
+void dump_node(audio_node *node, const char *str)
+{
+	if (!node || !str) {
+		printk("DUMP_NODE: detected argument is NULL\n");
+		return;
+	}
+
+	printk("%s: addr(0x%08x) id=%d, pBuf=0x%08x, start=0x%08x, end=0x%08x, phyaddr=0x%08x\n",
+	       str, (unsigned int)node, node->pBufID, node->pBuf, node->start, node->end, node->phyaddr);
+}
+
+void dump_list(audio_head *head)
+{
+	audio_node *tmp;
+	struct list_head *p, *n;
+
+	BUG_ON(!head);
+
+	printk("--------\nAudio head info: fact = %d, datasize = %d, listsize = %d\n",
+	       head->fact, head->datasize, head->listsize);
+
+	printk("free q:\n");
+	list_for_each_safe(p, n, &head->free) {
+		tmp = list_entry(p, audio_node, list);
+		DUMP_NODE(tmp, "fQ");
+	}
+	printk("use q:\n");
+	list_for_each_safe(p, n, &head->use) {
+		tmp = list_entry(p, audio_node, list);
+		DUMP_NODE(tmp, "uQ");
+	}
+	printk("--------\n");
+}
+#endif
+
+//----------------------------------------------------------------
+// audio node operater
+// int init_audio_node(unsigned int **memory, unsigned int pagesize, unsigned int count)
+// void deinit_audio_node(unsigned int **memory)
+// static inline audio_node *get_audio_freenode(unsigned int *mem)
+// static inline void put_audio_usenode(unsigned int *mem, audio_node *node)
+// static inline audio_node *get_audio_usenode(unsigned int *mem)
+// static inline void put_audio_freenode(unsigned int *mem, audio_node *node)
+// static inline int get_audio_freenodecount(unsigned int *mem)
+//
+//----------------------------------------------------------------
+
+void deinit_audio_node(unsigned int **memory)
+{
+	audio_head	*phead;
+	unsigned int	fact;
+
+	phead = (audio_head *)*memory;
+	fact = phead->fact;
+	free_pages((unsigned long)*memory, fact);
+	*memory = NULL;
+}
+
+int init_audio_node(unsigned int **memory, unsigned int pagesize, unsigned int count)
+{
+	unsigned int	fact;
+	audio_node	*pbuff;
+	audio_head	*phead;
+	unsigned int	*mem;
+	struct list_head *audio_wfree;
+	struct list_head *audio_wuse;
+	int	memsize;
+	int	datasize;
+	int	headlistsize;
+	int	i;
+
+	ENTER();
+
+	// Alloc memory first, to avail fail
+	datasize	= ALIGN_PAGE_SIZE(pagesize * count);
+	headlistsize	= ALIGN_PAGE_SIZE(count * sizeof(audio_node) + sizeof(audio_head));
+	memsize		= headlistsize + datasize;
+	fact		= get_order(memsize);
+
+	mem = (unsigned int *)__get_free_pages(GFP_KERNEL | GFP_DMA, fact);
+	if (mem == NULL) {
+		printk("JZ I2S: Memory allocation failed in function init_audio_node!\n");
+		return 0;
+	}
+
+	DPRINT("Mem alloc finish! memsize = %x, fact = %d, mem = 0x%08x\n",
+	       memsize, fact, (unsigned int)mem);
+
+	// Free old buffer
+	if (*memory) {
+		phead	= (audio_head *)*memory;
+		fact	= phead->fact;
+		free_pages((unsigned long)*memory, fact);
+		*memory	= NULL;
+	}
+	*memory = mem;
+
+/*
+	datasize	= ALIGN_PAGE_SIZE(pagesize * count);
+	headlistsize	= ALIGN_PAGE_SIZE(count * sizeof(audio_node) + sizeof(audio_head)); //8byte is save head data
+	memsize		= headlistsize + datasize;
+
+	fact = get_order(memsize);
+*/
+
+	// Update list head
+	phead		= (audio_head *)*memory;
+	phead->fact	= fact;
+	phead->listsize	= headlistsize;
+	phead->datasize	= datasize;
+
+	audio_wuse	= &(phead->use);
+	audio_wfree	= &(phead->free);
+	INIT_LIST_HEAD(audio_wuse);
+	INIT_LIST_HEAD(audio_wfree);
+
+	pbuff = (audio_node *)((unsigned int)*memory + sizeof(audio_head));
+	for (i = 0; i < count; i++) {
+		pbuff->pBuf	= (unsigned int)*memory + headlistsize + pagesize * i;
+		pbuff->phyaddr	= (unsigned int)virt_to_phys((void *)pbuff->pBuf);
+		pbuff->start	= 0;
+		pbuff->end	= 0;
+#ifdef Q_DEBUG
+		pbuff->pBufID	= i;
+#endif
+		DPRINT_Q("audio_note buffer[%d] = %x\n", i, (unsigned int)pbuff->pBuf);
+		list_add(&pbuff->list, audio_wfree);
+		pbuff++;
+	}
+
+	DUMP_LIST(phead);
+
+	LEAVE();
+	return 1;
+}
+
+#define is_null_free_audio_node(mem)				\
+({								\
+	audio_head *phead = (audio_head *)(mem);		\
+	struct list_head *pfree = &(phead->pfree);		\
+	(pfree->next == pfree);					\
+})
+
+#define is_null_use_audio_node(mem)				\
+({								\
+	audio_head *phead = (audio_head *)mem;			\
+	struct list_head *puse = &(phead->use);			\
+	(puse->next == puse);					\
+})
+
+//static unsigned int putid = 0, getid = 0;
+
+static inline audio_node *get_audio_freenode(unsigned int *mem)
+{
+	audio_head	 *phead;
+	audio_node	 *node = NULL;
+	struct list_head *pfree;
+	struct list_head *curnode;
+
+	phead	= (audio_head *)mem;
+	pfree	= &(phead->free);
+	curnode	= pfree->next;
+
+	if (curnode != pfree) {
+		node = THIS_AUDIO_NODE(curnode);
+		node->start = 0;
+		node->end = 0;
+		list_del(curnode);
+	}
+	return node;
+}
+
+static inline void put_audio_usenode(unsigned int *mem, audio_node *node)
+{
+	audio_head *phead = (audio_head *)mem;
+	struct list_head *puse = &(phead->use);
+	struct list_head *curnode = &(node->list);
+
+	list_add_tail(curnode, puse);
+}
+
+static inline audio_node *get_audio_usenode(unsigned int *mem)
+{
+	audio_head	 *phead;
+	audio_node	 *node = NULL;
+	struct list_head *curnode;
+	struct list_head *puse;
+
+	phead	= (audio_head *)mem;
+	puse	=  &(phead->use);
+	curnode	= puse->next;
+
+	if (curnode != puse) {
+		node = THIS_AUDIO_NODE(curnode);
+		list_del(curnode);
+	}
+	return node;
+}
+
+static inline void put_audio_freenode(unsigned int *mem, audio_node *node)
+{
+	audio_head *phead = (audio_head *)mem;
+	struct list_head *pfree = &(phead->free);
+	struct list_head *curnode = &(node->list);
+
+	list_add_tail(curnode, pfree);
+}
+
+static inline int get_audio_freenodecount(unsigned int *mem)
+{
+	struct list_head *pfree;
+	struct list_head *plist;
+	audio_head *phead;
+	int count = 0;
+
+	phead = (audio_head *)mem;
+	pfree =  &(phead->free);
+	plist = pfree;
+	while (plist->next != pfree) {
+		count++;
+		plist = plist->next;
+	}
+	return count;
+}
+
+//--------------------------------------------------------------------
+// end audio node operater
+//--------------------------------------------------------------------
+
+//--------------------------------------------------------------------
+// static irqreturn_t jz_i2s_dma_irq (int irq, void *dev_id)
+// int init_audio_recorddma(audio_pipe *endpoint)
+// int init_audio_replaydma(audio_pipe *endpoint)
+// int init_audio_audiodma(audio_pipe *endpoint, int mode)
+// void config_dma_trans_mode(spinlock_t lock, audio_dma_type* dma, int mode)
+// static inline int audio_trystart_dma_node(audio_dma_type* dma, audio_node *node)
+// static inline int audio_trystart_dma_node(audio_dma_type* dma, audio_node *node)
+// static inline void audio_stop_dma_node(audio_dma_type* dma)
+
+static irqreturn_t jz_i2s_dma_irq (int irq, void *dev_id)
+{
+	audio_pipe * endpoint = (audio_pipe *) dev_id;
+	int dma_chan = endpoint->dma.ch;
+	int dma_state = REG_DMAC_DCCSR(dma_chan);
+	int err = 0;
+
+	ENTER();
+
+	REG_DMAC_DCCSR(dma_chan) = 0;
+
+	DPRINT_IRQ("!!!! endpoint direct = %s \n",(endpoint == &out_endpoint) ? "out" : "in");
+
+	if (dma_state & DMAC_DCCSR_HLT) {
+		err = 0;
+		DPRINT_IRQ("!!!! DMA HALT\n");
+	}
+	if (dma_state & DMAC_DCCSR_AR) {
+		err = 1;
+		DPRINT_IRQ("!!!! DMA ADDR ERROR\n");
+	}
+	if (dma_state & DMAC_DCCSR_CT) {
+		DPRINT_IRQ("!!!! DMA descriptor finish\n");
+	}
+	/*
+	if (dma_state & DMA_DCCSR_TT) {
+
+	}
+	*/
+	if (err == 0) {
+		//printk("schedule_work++++ %x %x\n", endpoint,&(endpoint->work));
+		//schedule_work(&(endpoint->work));
+		//printk("schedule_work----\n");
+		endpoint->handle(endpoint);
+	} else {
+		DPRINT_IRQ("!!!! ??? unknown !!!\n");
+	}
+
+	LEAVE();
+
+	return IRQ_HANDLED;
+}
+
+static int jz_request_aic_dma(int dev_id, const char *dev_str,
+			      irqreturn_t (*irqhandler)(int, void *),
+			      unsigned long irqflags, void *irq_dev_id)
+{
+	struct jz_dma_chan *chan;
+	int i, ret;
+
+	if (dev_id == DMA_ID_AIC_TX) {
+		i = DMA_TX_CHAN;
+		if (jz_dma_table[i].dev_id != DMA_ID_AIC_TX) {
+			BUG_ON(1);
+		}
+	} else if (dev_id == DMA_ID_AIC_RX) {
+		i = DMA_RX_CHAN;
+		if (jz_dma_table[i].dev_id != DMA_ID_AIC_RX) {
+			BUG_ON(1);
+		}
+	} else {
+		BUG_ON(1);
+	}
+
+	/* we got channel */
+	chan = &jz_dma_table[i];
+
+	if (irqhandler) {
+		chan->irq = IRQ_DMA_0 + i;
+		chan->irq_dev = irq_dev_id;
+		if ((ret = request_irq(chan->irq, irqhandler, irqflags,
+				       dev_str, chan->irq_dev))) {
+			chan->irq = -1;
+			chan->irq_dev = NULL;
+			return ret;
+		}
+	} else {
+		chan->irq = -1;
+		chan->irq_dev = NULL;
+	}
+/*
+	printk("\n@@@@ %s:%d chan index = %d, chan.irq = %d\n\n",
+	       __FUNCTION__, __LINE__, i, chan->irq);
+*/
+	chan->io	= i;
+	chan->dev_id	= dev_id;
+	chan->dev_str	= dev_str;
+	chan->fifo_addr	= CPHYSADDR(AIC_DR);
+
+	switch (dev_id) {
+	case DMA_ID_AIC_TX:
+		chan->mode	= DMA_AIC_TX_CMD_UNPACK | DMA_MODE_WRITE;
+		chan->source	= DMAC_DRSR_RS_AICOUT;
+		break;
+	case DMA_ID_AIC_RX:
+		chan->mode	= DMA_32BIT_RX_CMD | DMA_MODE_READ;
+		chan->source	= DMAC_DRSR_RS_AICIN;
+		break;
+	default:
+		printk("JZ AIC: %s:%d, need fix !!!\n", __FUNCTION__, __LINE__);
+		BUG_ON(1);
+	}
+
+	// Open AIC_TX and AIC_RX
+#ifdef CONFIG_SOC_JZ4760
+	REG_DMAC_DMACKE(1) = 1 << (DMA_RX_CHAN - HALF_DMA_NUM) | 1 << (DMA_TX_CHAN - HALF_DMA_NUM);
+#else
+	REG_DMAC_DMACKS(1) = 1 << (DMA_RX_CHAN - HALF_DMA_NUM) | 1 << (DMA_TX_CHAN - HALF_DMA_NUM);
+#endif
+	return i;
+}
+
+static int init_audio_recorddma(audio_pipe *endpoint)
+{
+	int ch = 0;
+
+	ENTER();
+	if ((ch = jz_request_aic_dma(DMA_ID_I2S_RX, "audio adc", jz_i2s_dma_irq, IRQF_DISABLED, endpoint)) < 0) {
+		printk(KERN_ERR "%s: can't reqeust DMA DAC channel.\n", __FUNCTION__);
+		return -1;
+	}
+	REG_DMAC_DMACR(ch / HALF_DMA_NUM) |= 1;
+	REG_DMAC_DCMD(ch) =  DMAC_DCMD_DAI | DMAC_DCMD_SWDH_32 | DMAC_DCMD_TIE;
+	REG_DMAC_DRSR(ch) =  DMAC_DRSR_RS_AICIN;
+	REG_DMAC_DSAR(ch) =  (unsigned int)CPHYSADDR(AIC_DR);
+
+	endpoint->dma.ch = ch;
+	endpoint->dma.trans_addr = (unsigned int *)DMAC_DTAR(ch);
+	endpoint->dma.trans_count = (unsigned int *)DMAC_DTCR(ch);
+	endpoint->dma.trans_mode = (unsigned int *)DMAC_DCMD(ch);
+	endpoint->dma.data_addr = (unsigned int *)DMAC_DSAR(ch);
+
+	endpoint->dma.rw = 0;
+
+	LEAVE();
+	return ch;
+}
+
+static int init_audio_replaydma(audio_pipe *endpoint)
+{
+	int ch = 0;
+	if ((ch = jz_request_aic_dma(DMA_ID_I2S_TX,"audio dac", jz_i2s_dma_irq, IRQF_DISABLED, endpoint)) < 0) {
+		printk(KERN_ERR "%s: can't reqeust DMA DAC channel.\n", __FUNCTION__);
+		return -1;
+	}
+
+	REG_DMAC_DMACR(ch / HALF_DMA_NUM) |= 1;
+	REG_DMAC_DCMD(ch) =  DMAC_DCMD_SAI | DMAC_DCMD_DWDH_32 | DMAC_DCMD_TIE;
+
+	//printk("$$$$ before set --- REG_DMAC_DRSR(ch) = 0x%08x\n", REG_DMAC_DRSR(ch));
+	REG_DMAC_DRSR(ch) =  DMAC_DRSR_RS_AICOUT;
+
+	//printk("$$$$ ch = %d, DMAC_DRSR = 0x%08x, set 0x%08x, after set -- 0x%08x\n",
+	//       ch, DMAC_DRSR(ch), DMAC_DRSR_RS_AICOUT, REG_DMAC_DRSR(ch));
+
+	*(unsigned int *)0xb342010c = 0x18;
+
+	//printk("$$$$ after force set --- REG_DMAC_DRSR(ch) = 0x%08x\n", REG_DMAC_DRSR(ch));
+
+	REG_DMAC_DTAR(ch) =  (unsigned int)CPHYSADDR(AIC_DR);
+
+	endpoint->dma.ch = ch;
+	endpoint->dma.trans_addr = (unsigned int *)DMAC_DSAR(ch);
+	endpoint->dma.trans_count = (unsigned int *)DMAC_DTCR(ch);
+	endpoint->dma.trans_mode = (unsigned int *)DMAC_DCMD(ch);
+	endpoint->dma.data_addr = (unsigned int *)DMAC_DTAR(ch);
+	endpoint->dma.rw = 1;
+	return ch;
+}
+
+static int init_audio_audiodma(audio_pipe *endpoint, int mode)
+{
+	if (mode == CODEC_RMODE) {
+		return init_audio_recorddma(endpoint);
+	}
+
+	if (mode == CODEC_WMODE) {
+		return init_audio_replaydma(endpoint);
+	}
+
+	return -1;
+}
+
+static void config_dma_trans_mode(spinlock_t lock, audio_dma_type* dma, int sound_data_width)
+{
+	unsigned int	curmode;
+	unsigned long	flags;
+
+	ENTER();
+	AUDIO_LOCK(lock, flags);
+	curmode = *dma->trans_mode;
+
+	if (dma->rw) {
+		curmode &= ~(DMAC_DCMD_DWDH_MASK | DMAC_DCMD_DS_MASK);
+		switch(sound_data_width) {
+		case 8:
+			*dma->trans_mode = (curmode | DMAC_DCMD_DWDH_8 | DMAC_DCMD_DS_16BYTE);
+			dma->onetrans_bit = 16 * 8;
+			break;
+		case 16:
+			*dma->trans_mode = (curmode | DMAC_DCMD_DWDH_16 | DMAC_DCMD_DS_16BYTE);
+			dma->onetrans_bit = 16 * 8;
+			break;
+		case 17 ... 32:
+			*dma->trans_mode = (curmode | DMAC_DCMD_DWDH_32 | DMAC_DCMD_DS_32BYTE);
+			dma->onetrans_bit = 32 * 8;
+			break;
+		default:
+			printk("JZ I2S: Unkown DMA mode(sound data width) %d\n", sound_data_width);
+			break;
+		}
+	} else {
+		curmode &= ~(DMAC_DCMD_SWDH_MASK | DMAC_DCMD_DS_MASK);
+		switch(sound_data_width) {
+		case 8:
+			*dma->trans_mode = (curmode | DMAC_DCMD_SWDH_8 | DMAC_DCMD_DS_16BYTE);
+			dma->onetrans_bit = 16 * 8;
+			break;
+		case 16:
+			*dma->trans_mode = (curmode | DMAC_DCMD_SWDH_16 | DMAC_DCMD_DS_16BYTE);
+			dma->onetrans_bit = 16 * 8;
+			break;
+		case 17 ... 32:
+			*dma->trans_mode = (curmode | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DS_32BYTE);
+			dma->onetrans_bit = 32 * 8;
+			break;
+		default:
+			printk("JZ I2S: Unkown DMA mode(sound data width) %d\n", sound_data_width);
+			break;
+		}
+	}
+
+	AUDIO_UNLOCK(lock, flags);
+	DUMP_DMA(dma->ch, __FUNCTION__);
+	DPRINT_DMA("dma_trans = %d\n", dma->onetrans_bit);
+	LEAVE();
+}
+
+#define aic_enable_transmit()					\
+do {								\
+	int dat = REG_AIC_CR;					\
+	dat |= (AIC_CR_TDMS | AIC_CR_ERPL);			\
+	REG_AIC_CR = dat;					\
+} while (0)
+
+#define aic_disable_transmit()					\
+do {								\
+	int dat = REG_AIC_CR;					\
+	dat &= ~(AIC_CR_TDMS | AIC_CR_ERPL);			\
+	REG_AIC_CR = dat;					\
+} while (0)
+
+static inline int audio_trystart_dma_node(audio_dma_type* dma, audio_node *node)
+{
+	int start = 0;
+
+	ENTER();
+
+	if ((REG_DMAC_DCCSR(dma->ch) & DMAC_DCCSR_EN) == 0) {
+		int count = node->end - node->start;
+		*(dma->trans_addr) = node->phyaddr;
+		*(dma->data_addr) =  (unsigned int)CPHYSADDR(AIC_DR);
+		*(dma->trans_count) = count * 8 / dma->onetrans_bit;
+		REG_DMAC_DCCSR(dma->ch) = DMAC_DCCSR_NDES | DMAC_DCCSR_EN;
+		DPRINT_DMA("virt = 0x%08x phy = 0x%08x, dma->onetrans_bit = 0x%x\n",
+			   node->pBuf, node->phyaddr, dma->onetrans_bit);
+
+		DUMP_CODEC_REGS(__FUNCTION__);
+		DUMP_AIC_REGS(__FUNCTION__);
+		start = 1;
+	}
+
+	DUMP_DMA(dma->ch, "audio_trystart_dma_node -----------");
+
+	LEAVE();
+	return start;
+}
+
+static inline void audio_stop_dma_node(audio_dma_type* dma)
+{
+	REG_DMAC_DCCSR(dma->ch) = 0;
+}
+
+/* Never be used, fix me ???
+static inline int recalculate_fifowidth(short channels, short fmt)
+{
+	int bit = 16;
+
+	if (fmt <= 8) {
+		bit = 8;
+	} else if (fmt > 16) {
+		bit = 32;
+	} else {
+		bit = 16;
+	}
+
+	return 	bit *= channels;
+}
+*/
+#define I2S_FIFO_DEPTH 32
+
+static inline void set_controller_triger(struct jz_i2s_controller_info *controller,
+					 audio_pipe *endpoint, short channels, short format)
+{
+	int sound_data_width = 0;
+
+	ENTER();
+
+//	printk("%%%% format = %d\n", format);
+
+	switch (format) {
+	case AFMT_U8:
+	case AFMT_S8:
+		sound_data_width = 8;
+		break;
+	case AFMT_S16_LE:
+	case AFMT_S16_BE:
+		sound_data_width = 16;
+		break;
+	default:
+		printk("JZ I2S: Unkown sound format %d\n", format);
+		return ;
+	}
+
+	config_dma_trans_mode(endpoint->lock,&(endpoint->dma), sound_data_width);
+	if (endpoint == &out_endpoint) {
+		if ((I2S_FIFO_DEPTH - endpoint->dma.onetrans_bit / sound_data_width) >= 30) {
+			__i2s_set_transmit_trigger(14);
+		} else {
+			__i2s_set_transmit_trigger((I2S_FIFO_DEPTH - endpoint->dma.onetrans_bit / sound_data_width) / 2);
+		}
+	}
+	if (endpoint == &in_endpoint) {
+		__i2s_set_receive_trigger((endpoint->dma.onetrans_bit / sound_data_width) / 2);
+	}
+
+	LEAVE();
+}
+
+//-------------------------------------------------------------------
+/*
+  int trystart_endpoint_out(audio_pipe *endpoint, audio_node *node);
+  int trystart_endpoint_in(audio_pipe *endpoint, audio_node *node);
+  note: this two function isn't protected;
+ */
+static inline int trystart_endpoint_out(struct jz_i2s_controller_info *controller, audio_node *node)
+{
+	audio_pipe *endpoint = controller->pout_endpoint;
+	int start = 0;
+
+	ENTER();
+
+	start = audio_trystart_dma_node(&(endpoint->dma), node);
+	if (start) {
+		endpoint->trans_state |= PIPE_TRANS;
+		endpoint->savenode = node;
+		aic_enable_transmit();
+		DUMP_AIC_REGS(__FUNCTION__);
+		DUMP_CODEC_REGS(__FUNCTION__);
+	}
+
+	LEAVE();
+	return start;
+}
+
+static inline int trystart_endpoint_in(struct jz_i2s_controller_info *controller, audio_node *node)
+{
+	audio_pipe *endpoint = controller->pin_endpoint;
+	int start = 0;
+
+	ENTER();
+	dma_cache_wback_inv((unsigned long)node->pBuf, endpoint->fragsize);
+	start = audio_trystart_dma_node(&(endpoint->dma), node);
+	if (start) {
+		endpoint->trans_state |= PIPE_TRANS;
+		endpoint->savenode = node;
+		__i2s_enable_receive_dma();
+		__i2s_enable_record();
+		DUMP_AIC_REGS(__FUNCTION__);
+		DUMP_CODEC_REGS(__FUNCTION__);
+	}
+	LEAVE();
+	return start;
+}
+
+int audio_get_endpoint_freesize(audio_pipe *endpoint, audio_buf_info *info)
+{
+	int count;
+	unsigned long flags;
+
+	AUDIO_LOCK(endpoint->lock, flags);
+	count = get_audio_freenodecount(endpoint->mem);
+	AUDIO_UNLOCK(endpoint->lock, flags);
+	info->fragments = count;
+	info->fragstotal = endpoint->fragstotal;
+	info->fragsize = endpoint->fragsize;
+	info->bytes = count * endpoint->fragsize;
+	return info->bytes;
+}
+
+void audio_clear_endpoint(audio_pipe *endpoint)
+{
+	audio_node *pusenode;
+	unsigned long flags;
+
+	ENTER();
+	AUDIO_LOCK(endpoint->lock, flags);
+	while (!is_null_use_audio_node(endpoint->mem)) {
+		pusenode = get_audio_usenode(endpoint->mem);
+		if (pusenode) {
+			put_audio_freenode(endpoint->mem, pusenode);
+		}
+	}
+	AUDIO_UNLOCK(endpoint->lock, flags);
+	LEAVE();
+}
+
+void audio_sync_endpoint(audio_pipe *endpoint)
+{
+	int isnull = 1;
+	unsigned long flags;
+
+	ENTER();
+
+	do {
+		AUDIO_LOCK(endpoint->lock, flags);
+		isnull = is_null_use_audio_node(endpoint->mem);
+		AUDIO_UNLOCK(endpoint->lock, flags);
+		if (!isnull) {
+			//printk("&&&& audio_sync_endpoint\n");
+			schedule_timeout(1);
+		}
+	} while (!isnull);
+
+	LEAVE();
+}
+
+void audio_close_endpoint(audio_pipe *endpoint, int mode)
+{
+	int is_use_list_null = 1, trans = 0;
+	unsigned long flags;
+
+	ENTER();
+
+	AUDIO_LOCK(endpoint->lock, flags);
+	is_use_list_null = is_null_use_audio_node(endpoint->mem);
+	trans = endpoint->trans_state & PIPE_TRANS;
+	AUDIO_UNLOCK(endpoint->lock, flags);
+
+	if (is_use_list_null) {
+		// Wait savenode trans complete
+		while (trans) {
+			AUDIO_LOCK(endpoint->lock, flags);
+			trans = endpoint->trans_state & PIPE_TRANS;
+			AUDIO_UNLOCK(endpoint->lock, flags);
+			DPRINT("waiting savenode\n");
+			if (trans) {
+				schedule_timeout(10);
+			}
+		}
+
+		/* In replay mode, savenode must been put into free list after trans completed,
+		 * so we don't care it in this condition.
+		 * But in record mode, savenode must been put into use list after trans completed,
+		 * so we have to ignore the incomming data and move it to free list forcely.
+		 */
+		if (endpoint == &out_endpoint) {
+			goto _L_AUDIO_CLOSE_EP_RET;
+		}
+	}
+
+	// NOMAL_STOP routine of replay mode
+	if (mode == NOMAL_STOP) {
+		BUG_ON(endpoint != &out_endpoint);
+
+		// Wait use list free
+		audio_sync_endpoint(endpoint);
+		// wait savenode trans finish
+		while (trans) {
+			AUDIO_LOCK(endpoint->lock, flags);
+			trans = endpoint->trans_state & PIPE_TRANS;
+			AUDIO_UNLOCK(endpoint->lock, flags);
+			//printk("waiting savenode\n");
+			if (trans) {
+				schedule_timeout(10);
+			}
+		}
+
+		AUDIO_LOCK(endpoint->lock, flags);
+		DUMP_LIST((audio_head *)endpoint->mem);
+		DUMP_NODE(endpoint->savenode, "SN");
+		AUDIO_UNLOCK(endpoint->lock, flags);
+	} else {
+		// FORCE_STOP routine, both replay and record mode could run
+		audio_node *pusenode;
+
+		// Shutdown DMA immediately and clear lists forcely.
+		AUDIO_LOCK(endpoint->lock, flags);
+
+		endpoint->trans_state &= ~PIPE_TRANS;
+		audio_stop_dma_node(&endpoint->dma);
+
+		DUMP_LIST((audio_head *)endpoint->mem);
+		DUMP_NODE(endpoint->savenode, "SN");
+		DPRINT_Q("---------------------------------\n");
+
+		while (!is_null_use_audio_node(endpoint->mem)) {
+			pusenode = get_audio_usenode(endpoint->mem);
+			if (pusenode) {
+				put_audio_freenode(endpoint->mem, pusenode);
+			}
+		}
+
+		DUMP_LIST((audio_head *)endpoint->mem);
+		DUMP_NODE(endpoint->savenode, "SN");
+		DPRINT_Q("---------------------------------\n");
+
+		if (endpoint->savenode) {
+			DPRINT_Q("handle savenode : 0x%08x\n", (unsigned int)endpoint->savenode);
+			DUMP_NODE(endpoint->savenode, "SN");
+			put_audio_freenode(endpoint->mem, endpoint->savenode);
+
+			DPRINT_Q("savenode->list->next = 0x%08x, savenode->list->prev = 0x%08x\n",
+			       (unsigned int)endpoint->savenode->list.next,
+			       (unsigned int)endpoint->savenode->list.prev);
+
+			endpoint->savenode = NULL;
+		}
+
+		DUMP_LIST((audio_head *)endpoint->mem);
+		DUMP_NODE(endpoint->savenode, "SN");
+
+		AUDIO_UNLOCK(endpoint->lock, flags);
+	}
+
+_L_AUDIO_CLOSE_EP_RET:
+	LEAVE();
+}
+
+int audio_resizemem_endpoint(audio_pipe *endpoint, unsigned int pagesize, unsigned int count)
+{
+	int ret;
+	if((endpoint->fragsize == pagesize)&&(endpoint->fragstotal == count))
+	return 1;//debug by wll
+	ret = init_audio_node(&endpoint->mem, pagesize, count);
+	if (ret) {
+		endpoint->fragsize = pagesize;
+		endpoint->fragstotal = count;
+	}
+	return ret;
+}
+
+static void handle_in_endpoint_work(audio_pipe *endpoint)
+{
+	audio_node	*node;
+	unsigned long	flags;
+
+	ENTER();
+
+	AUDIO_LOCK(endpoint->lock, flags);
+	if (endpoint->savenode) {
+		DPRINT_Q("\nIIII RRRR QQQQ >>>>\n");
+		DUMP_LIST((audio_head *)endpoint->mem);
+		DUMP_NODE(endpoint->savenode, "IRQSN");
+		DPRINT_Q("IIII RRRR QQQQ <<<<\n\n");
+
+		DPRINT_IRQ("%s endpoint->savenode = 0x%p\n", __FUNCTION__, endpoint->savenode);
+		put_audio_usenode(endpoint->mem, endpoint->savenode);
+
+		endpoint->savenode = NULL;
+		DUMP_BUF((char *)(endpoint->savenode->pBuf + endpoint->savenode->start), 64, 32);
+
+		if (!(endpoint->is_non_block)) {
+			endpoint->avialable_couter++;
+			wake_up_interruptible(&endpoint->q_full);
+		}
+	}
+
+	node = get_audio_freenode(endpoint->mem);
+	if (node) {
+		int start;
+		node->end = endpoint->fragsize;
+		dma_cache_wback_inv((unsigned long)node->pBuf, endpoint->fragsize);
+		start = audio_trystart_dma_node(&(endpoint->dma), node);
+		if (start == 0) {
+			put_audio_freenode(endpoint->mem, node);
+		} else {
+			endpoint->savenode = node;
+		}
+	} else {
+		endpoint->trans_state &= ~PIPE_TRANS;
+		__i2s_disable_receive_dma();
+		__i2s_disable_record();
+		DPRINT_IRQ("!!!! Stop AIC record !\n");
+	}
+
+	DPRINT_Q("\nIIII RRRR QQQQ >>>>\n");
+	DUMP_LIST((audio_head *)endpoint->mem);
+	DUMP_NODE(endpoint->savenode, "SN");
+	DPRINT_Q("IIII RRRR QQQQ <<<<\n\n");
+
+	AUDIO_UNLOCK(endpoint->lock, flags);
+
+	LEAVE();
+}
+
+/*
+static void audio_in_endpoint_work(struct work_struct *work)
+{
+	audio_pipe *endpoint = &in_endpoint;
+	handle_in_endpoint_work(endpoint);
+}
+*/
+
+static void handle_out_endpoint_work(audio_pipe *endpoint)
+{
+	audio_node *node;
+	unsigned long flags;
+
+	ENTER();
+
+	AUDIO_LOCK(endpoint->lock, flags);
+	DPRINT_IRQ("%s endpoint->savenode = 0x%08x\n", __FUNCTION__, (unsigned int)endpoint->savenode);
+
+	if (endpoint->savenode) {
+		put_audio_freenode(endpoint->mem, endpoint->savenode);
+		DPRINT_IRQ("put_audio_freenode\n");
+		endpoint->savenode = NULL;
+
+		if (!(endpoint->is_non_block)) {
+			wake_up_interruptible(&endpoint->q_full);
+			endpoint->avialable_couter++;
+		}
+	}
+
+	node = get_audio_usenode(endpoint->mem);
+	if (node) {
+		int start;
+		start = audio_trystart_dma_node(&(endpoint->dma), node);
+		if (start == 0) {
+			printk("audio_out_endpoint_work audio_trystart_dma_node error!\n");
+		} else {
+			endpoint->savenode = node;
+			DPRINT_DMA("restart dma!\n");
+		}
+	} else {
+		endpoint->trans_state &= ~PIPE_TRANS;
+		aic_disable_transmit();
+		DPRINT_IRQ("!!!! Stop AIC !\n");
+	}
+
+	AUDIO_UNLOCK(endpoint->lock, flags);
+	LEAVE();
+}
+
+/*
+static void audio_out_endpoint_work(struct work_struct *work)
+{
+	audio_pipe *endpoint = &out_endpoint;
+	handle_out_endpoint_work(endpoint);
+}
+*/
+
+void audio_init_endpoint(audio_pipe *endpoint, unsigned int pagesize, unsigned int count)
+{
+	audio_resizemem_endpoint(endpoint, pagesize, count);
+	spin_lock_init(&endpoint->lock);
+	init_waitqueue_head(&endpoint->q_full);
+	endpoint->avialable_couter = 0;
+	endpoint->filter = NULL;
+
+	if (endpoint == &in_endpoint) {
+		init_audio_audiodma(endpoint, CODEC_RMODE);
+		// INIT_WORK(&endpoint->work, audio_in_endpoint_work);
+		endpoint->handle = handle_in_endpoint_work;
+	}
+	if (endpoint == &out_endpoint) {
+		init_audio_audiodma(endpoint, CODEC_WMODE);
+		// INIT_WORK(&endpoint->work, audio_out_endpoint_work);
+		endpoint->handle = handle_out_endpoint_work;
+	}
+}
+
+void audio_deinit_endpoint(audio_pipe *endpoint)
+{
+	audio_close_endpoint(endpoint, FORCE_STOP);
+	deinit_audio_node(&endpoint->mem);
+}
+
+void register_jz_codecs(void *func)
+{
+	int i;
+
+	ENTER();
+
+	for (i = 0; i < NR_I2S; i++) {
+		if (the_codecs[i].codecs_ioctrl == 0) {
+			printk("register codec %x\n",(unsigned int)func);
+			the_codecs[i].id = i;
+			the_codecs[i].codecs_ioctrl = func;
+			init_MUTEX(&(the_codecs[i].i2s_sem));
+			break;
+		}
+	}
+
+	LEAVE();
+}
+
+#define codec_ioctrl(codec, cmd, args) ({			\
+	int result;						\
+	down(&(codec)->i2s_sem);				\
+	result = (codec)->codecs_ioctrl((codec), (cmd), (args));\
+	up(&(codec)->i2s_sem);					\
+	result;							\
+})
+
+static int jz_i2s_open_mixdev(struct inode *inode, struct file *file)
+{
+	int i;
+	int minor = MINOR(inode->i_rdev);
+
+	ENTER();
+
+	for (i = 0; i < NR_I2S; i++) {
+		if (the_codecs[i].dev_mixer == minor) {
+			goto match;
+		}
+	}
+match:
+	file->private_data = &the_codecs[i];
+
+	LEAVE();
+	return 0;
+}
+
+/*
+ * Debug entry for Android
+ */
+static int jz_i2s_write_mixdev(struct file *file, const char __user *buffer, size_t count, loff_t *ppos)
+{
+	struct i2s_codec *codec = (struct i2s_codec *)file->private_data;
+	char	buf_byte = 0;
+	char	argument[16];
+	int	val;
+
+	if (copy_from_user((void *)&buf_byte, buffer, 1)) {
+		printk("JZ MIX: copy_from_user failed !\n");
+		return -EFAULT;
+	}
+
+	switch (buf_byte) {
+	case '1':
+		dump_dlv_regs("jz_i2s_write_mixdev --- debug routine");
+		dump_aic_regs("");
+		break;
+	case '2':
+		printk("dlv_set_replay\n");
+		codec_ioctrl(codec, CODEC_SET_REPLAY, 0);
+		break;
+	case '3':
+		printk("dlv_set_record\n");
+		codec_ioctrl(codec, CODEC_SET_RECORD, 0);
+		break;
+	case '4':
+		if (codec_ioctrl(codec, CODEC_SET_RECORD_DATA_WIDTH, 16) >= 0) {
+			printk("Set data width : 16\n");
+		} else {
+			printk("Could not set data width\n");
+		}
+		break;
+	case '5':
+		if (copy_from_user((void *)&argument, buffer + 1, 3)) {
+			printk("JZ MIX: copy_from_user failed !\n");
+			return -EFAULT;
+		}
+		if (argument[0] >= '0' && argument[0] <= '9'
+		    && argument [1] >= '0' && argument[1] <= '9'
+		    && argument [2] >= '0' && argument[2] <= '9') {
+
+			val = (argument[0] - '0') * 100 + (argument[1] - '0') * 10 + argument[2] - '0';
+
+			printk("JZ MIX: set volume (%d)\n", val);
+			codec_ioctrl(codec, CODEC_SET_VOLUME, val);
+		} else {
+			printk("JZ MIX: invalid argument for set volume\n");
+		}
+		break;
+	}
+
+	return count;
+}
+
+/*
+ * Handle IOCTL request on /dev/mixer
+ *
+ * Support OSS IOCTL interfaces for /dev/mixer
+ * Support IOCTL interfaces for /dev/mixer defined in include/msm_audio.h
+ */
+static int jz_i2s_ioctl_mixdev(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
+{
+	struct i2s_codec *codec = (struct i2s_codec *)file->private_data;
+	long	val = 0;
+	int	ret, rc = 0;
+
+#ifdef CONFIG_JZ_EBOOK_HARD
+//	printk("DEBUG: %s, %d\n", __FUNCTION__, __LINE__);
+	/* add by qinbh, control the aic clock */
+	int reg = REG_CPM_CLKGR;
+//	__cpm_start_aic1();
+#endif
+
+
+	ENTER();
+
+	DPRINT_IOC("[mixer IOCTL]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n");
+	DPRINT_IOC(" mixer IOCTL %s cmd = 0x%08x, arg = %lu\n", __FUNCTION__, cmd, arg);
+	DPRINT_MIXER_IOC_CMD(cmd);
+	DPRINT_IOC("[mixer IOCTL]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n");
+
+	// struct jz_i2s_controller_info *controller = (struct jz_i2s_controller_info *) file->private_data;
+
+	switch (cmd) {
+
+	/*
+	 * OSS IOCTL commands for /dev/mixer
+	 */
+	case SOUND_MIXER_INFO:
+	{
+		mixer_info info;
+		codec_ioctrl(codec, CODEC_GET_MIXER_INFO, (unsigned int)&info);
+		info.modify_counter = audio_mix_modcnt;
+		return copy_to_user((void *)arg, &info, sizeof(info));
+	}
+	case SOUND_OLD_MIXER_INFO:
+	{
+		_old_mixer_info info;
+		codec_ioctrl(codec, CODEC_GET_MIXER_OLD_INFO, (unsigned int)&info);
+		return copy_to_user((void *)arg, &info, sizeof(info));
+	}
+
+	case SOUND_MIXER_READ_STEREODEVS:
+		return put_user(0, (long *) arg);
+	case SOUND_MIXER_READ_CAPS:
+		return put_user(SOUND_CAP_EXCL_INPUT, (long *) arg);
+
+	case SOUND_MIXER_READ_DEVMASK:
+		break;
+	case SOUND_MIXER_READ_RECMASK:
+		break;
+	case SOUND_MIXER_READ_RECSRC:
+		break;
+
+	case SOUND_MIXER_WRITE_SPEAKER:
+		ret = get_user(val, (long *) arg);
+		if ((val &= 0xff) >= 100) {
+			val = 100;
+		}
+		codec_ioctrl(codec, CODEC_SET_DIRECT_MODE, val);
+		break;
+
+	case SOUND_MIXER_WRITE_BASS:
+		ret = get_user(val, (long *) arg);
+		if ((val &= 0xff) >= 100) {
+			val = 100;
+		}
+		codec->bass_gain = val;
+		codec_ioctrl(codec, CODEC_SET_BASS, val);
+		return 0;
+
+	case SOUND_MIXER_READ_BASS:
+		val = codec->bass_gain;
+		ret = val << 8;
+		val = val | ret;
+		return put_user(val, (long *) arg);
+
+	case SOUND_MIXER_WRITE_VOLUME:
+		ret = get_user(val, (long *) arg);
+		if ((val &= 0xff) >= 100) {
+			val = 100;
+		}
+
+		DPRINT_IOC("SOUND_MIXER_WRITE_VOLUME <- %lu\n", val);
+
+		codec->audio_volume = val;
+		codec_ioctrl(codec, CODEC_SET_REPLAY_VOLUME, val);
+		return 0;
+
+	case SOUND_MIXER_READ_VOLUME:
+		val = codec->audio_volume;
+		ret = val << 8;
+		val = val | ret;
+		return put_user(val, (long *) arg);
+
+	case SOUND_MIXER_WRITE_MIC:
+		ret = get_user(val, (long *) arg);
+		if ((val &= 0xff) >= 100) {
+			val = 100;
+		}
+		codec->mic_gain = val;
+		codec->use_mic_line_flag = USE_MIC;
+		codec_ioctrl(codec, CODEC_SET_MIC_VOLUME, val);
+		return 0;
+
+	case SOUND_MIXER_READ_MIC:
+		val = codec->mic_gain;
+		ret = val << 8;
+		val = val | ret;
+		return put_user(val, (long *) arg);
+
+	case SOUND_MIXER_WRITE_LINE:
+		ret = get_user(val, (long *) arg);
+		if (ret) {
+			return ret;
+		}
+		if ((val &= 0xff) >= 100) {
+			val = 100;
+		}
+		codec->use_mic_line_flag = USE_LINEIN;
+		codec->mic_gain = val;
+		codec_ioctrl(codec, CODEC_SET_LINE, val);
+		return 0;
+
+	case SOUND_MIXER_READ_LINE:
+		val = codec->mic_gain;
+		ret = val << 8;
+		val = val | ret;
+		return put_user(val, (long *) arg);
+
+	case SOUND_MIXER_WRITE_MUTE:
+		get_user(codec->audiomute, (long *)arg);
+		//codec_ioctrl(codec, CODEC_DAC_MUTE, codec->audiomute);
+		break;
+
+	case SOUND_MIXER_READ_MUTE:
+		put_user(codec->audiomute, (long *) arg);
+		break;
+
+#if 0
+	/*
+	 * MSM IOCTL commands for /dev/mixer
+	 */
+	case SND_SET_DEVICE:
+	{
+		struct snd_device_config dev;
+		if (copy_from_user(&dev, (void *) arg, sizeof(dev))) {
+			rc = -EFAULT;
+			break;
+		}
+		break;
+	}
+
+	case SND_SET_VOLUME:
+	{
+		struct snd_volume_config vol;
+		if (copy_from_user(&vol, (void *) arg, sizeof(vol))) {
+			return -EFAULT;
+		}
+		val =  vol.volume;
+		if ((val &= 0xff) >= 100) {
+			val = 100;
+		}
+		DPRINT_IOC("snd_set_volume %d %d %d\n", vol.device, vol.method, vol.volume);
+		codec->audio_volume = val;
+		codec_ioctrl(codec, CODEC_SET_MIC, (unsigned int)&val); ///??????????????????????????
+		//error
+		break;
+	}
+
+	case SND_GET_NUM_ENDPOINTS:
+		if (copy_to_user((void __user*) arg, &snd->snd_epts->num, sizeof(unsigned))) {
+			printk("%s: error get endpoint\n",__FUNCTION__);
+			rc = -EFAULT;
+		}
+		val = 2;
+		if (copy_to_user((void __user*) arg, &val, sizeof(unsigned))) {
+			printk("%s: error get endpoint\n",__FUNCTION__);
+			rc = -EFAULT;
+		}
+
+		break;
+	case SND_GET_ENDPOINT:
+		//rc = get_endpoint(snd, arg);
+		break;
+#endif
+
+	default:
+		printk("Mixer IOCTL error: %s:%d: known command: 0x%08x\n", __FUNCTION__, __LINE__, cmd);
+		return -ENOSYS;
+	}
+	audio_mix_modcnt++;
+
+#ifdef CONFIG_JZ_EBOOK_HARD
+//	printk("DEBUG: %s, %d\n", __FUNCTION__, __LINE__);
+	/* add by qinbh */
+	REG_CPM_CLKGR = reg;
+#endif
+
+	LEAVE();
+	return rc;
+}
+
+static struct file_operations jz_i2s_mixer_fops =
+{
+	owner:		THIS_MODULE,
+	ioctl:		jz_i2s_ioctl_mixdev,
+	open:		jz_i2s_open_mixdev,
+	write:		jz_i2s_write_mixdev,
+};
+
+int i2s_probe_codec(struct i2s_codec *codec)
+{
+	/* generic OSS to I2S wrapper */
+	return (codec->codecs_ioctrl) ? 1 : 0;
+}
+
+/* I2S codec initialisation. */
+static int __init jz_i2s_codec_init(struct jz_i2s_controller_info *controller)
+{
+	int i;
+
+	ENTER();
+
+	for (i = 0; i < NR_I2S; i++) {
+		the_codecs[i].private_data = controller;
+		if (i2s_probe_codec(&the_codecs[i]) == 0) {
+			break;
+		}
+		if ((the_codecs[i].dev_mixer = register_sound_mixer(&jz_i2s_mixer_fops, the_codecs[i].id)) < 0) {
+			printk(KERN_ERR "JZ I2S: couldn't register mixer!\n");
+			break;
+		}
+
+	}
+	controller->i2s_codec = &the_codecs[0];
+
+	LEAVE();
+	return i;
+}
+
+static void jz_i2s_reinit_hw(struct i2s_codec *codec, int mode)
+{
+	ENTER();
+
+   	__i2s_disable();
+	schedule_timeout(5);
+	codec_ioctrl(codec, CODEC_EACH_TIME_INIT, 0);
+	__i2s_disable_record();
+	__i2s_disable_replay();
+	__i2s_disable_loopback();
+	__i2s_set_transmit_trigger(4);
+	__i2s_set_receive_trigger(3);
+	__i2s_send_rfirst();
+
+	LEAVE();
+}
+
+static int jz_codec_set_speed(struct i2s_codec *codec, int rate, int mode)
+{
+	ENTER();
+
+	/* 8000, 11025, 16000, 22050, 24000, 32000, 44100, 48000, 99999999 ? */
+	if (mode & CODEC_RMODE) {
+		rate = codec_ioctrl(codec, CODEC_SET_RECORD_RATE, rate);
+		if (rate > 0) {
+			codec->record_audio_rate = rate;
+		} else {
+			rate = codec->record_audio_rate;
+		}
+	}
+	if (mode & CODEC_WMODE) {
+		rate = codec_ioctrl(codec, CODEC_SET_REPLAY_RATE, rate);
+		if (rate > 0) {
+			codec->replay_audio_rate = rate;
+		} else {
+			rate = codec->replay_audio_rate;
+		}
+	}
+
+	LEAVE();
+	return rate;
+}
+
+static short jz_codec_set_channels(struct i2s_codec *codec, short channels, int mode)
+{
+	ENTER();
+
+	DPRINT_IOC("%s mode = %x channels = %d\n", __FUNCTION__, mode, channels);
+	DPRINT_IOC("mode & CODEC_RMODE == %x", mode & CODEC_RMODE);
+
+	if (mode & CODEC_RMODE) {
+		channels = codec_ioctrl(codec, CODEC_SET_RECORD_CHANNEL, channels);
+		codec->record_codec_channel = channels;
+	}
+	if (mode & CODEC_WMODE) {
+		channels = codec_ioctrl(codec, CODEC_SET_REPLAY_CHANNEL, channels);
+		codec->replay_codec_channel = channels;
+		if (channels == 1) {
+			__aic_enable_mono2stereo();
+			__aic_out_channel_select(0);
+		} else {
+			__aic_disable_mono2stereo();
+			__aic_out_channel_select(1);
+		}
+	}
+
+	LEAVE();
+
+	return channels;
+}
+
+static void jz_codec_select_mode(struct i2s_codec *codec, int mode)
+{
+	ENTER();
+
+	switch (mode) {
+	case CODEC_WRMODE:
+		if (codec->use_mic_line_flag == USE_NONE) {
+			codec->use_mic_line_flag = USE_MIC;
+		}
+		codec_ioctrl(codec, CODEC_SET_REPLAY_RECORD, codec->use_mic_line_flag);
+		break;
+	case CODEC_RMODE:
+		if (codec->use_mic_line_flag == USE_NONE) {
+			codec->use_mic_line_flag = USE_MIC;
+		}
+		codec_ioctrl(codec, CODEC_SET_RECORD, codec->use_mic_line_flag);
+		break;
+	case CODEC_WMODE:
+		codec_ioctrl(codec, CODEC_SET_REPLAY, mode);
+		break;
+	}
+
+	LEAVE();
+}
+
+void jz_codec_anti_pop(struct i2s_codec *codec, int mode)
+{
+	ENTER();
+	codec_ioctrl(codec, CODEC_ANTI_POP, mode);
+	LEAVE();
+}
+
+void jz_codec_close(struct i2s_codec *codec, int mode)
+{
+	ENTER();
+	down(&codec->i2s_sem);
+	codec->codecs_ioctrl(codec, CODEC_TURN_OFF, mode);
+	up(&codec->i2s_sem);
+	LEAVE();
+}
+
+/***************************************************************
+			filter functions
+ ***************************************************************/
+
+/*
+ * Convert signed byte to unsiged byte
+ *
+ * Mapping:
+ * 	signed		unsigned
+ *	0x00 (0)	0x80 (128)
+ *	0x01 (1)	0x81 (129)
+ *	......		......
+ *	0x7f (127)	0xff (255)
+ *	0x80 (-128)	0x00 (0)
+ *	0x81 (-127)	0x01 (1)
+ *	......		......
+ *	0xff (-1)	0x7f (127)
+ */
+static int convert_8bits_signed2unsigned(void *buffer, int counter)
+{
+	int i;
+	int counter_8align	= counter & ~0x7;
+	unsigned char *ucsrc	= buffer;
+	unsigned char *ucdst	= buffer;
+
+	ENTER();
+
+	for (i = 0; i < counter_8align; i+=8) {
+		*(ucdst + i + 0) = *(ucsrc + i + 0) + 0x80;
+		*(ucdst + i + 1) = *(ucsrc + i + 1) + 0x80;
+		*(ucdst + i + 2) = *(ucsrc + i + 2) + 0x80;
+		*(ucdst + i + 3) = *(ucsrc + i + 3) + 0x80;
+		*(ucdst + i + 4) = *(ucsrc + i + 4) + 0x80;
+		*(ucdst + i + 5) = *(ucsrc + i + 5) + 0x80;
+		*(ucdst + i + 6) = *(ucsrc + i + 6) + 0x80;
+		*(ucdst + i + 7) = *(ucsrc + i + 7) + 0x80;
+		//printk("csrc + %d + 7 = %d,  ucdst + %d + 7 = %d\n",
+		//       i, *(csrc + i + 7), i, *(ucdst + i + 7));
+	}
+
+	BUG_ON(i != counter_8align);
+
+	for (i = counter_8align; i < counter; i++) {
+		*(ucdst + i) = *(ucsrc + i) + 0x80;
+	}
+
+	//printk("[dbg] src = 0x%02x (%d) --- dst = 0x%02x (%d), cnt = %d, cnt8a = %d\n",
+	//       *csrc, *csrc, *ucdst, *ucdst, counter, counter_8align);
+	LEAVE();
+	return counter;
+}
+
+/*
+ * Convert stereo data to mono data, data width: 8 bits/channel
+ *
+ * buff:	buffer address
+ * data_len:	data length in kernel space, the length of stereo data
+ *		calculated by "node->end - node->start"
+ */
+int convert_8bits_stereo2mono(void *buff, int data_len)
+{
+	/* stride = 16 bytes = 2 channels * 1 byte * 8 pipelines */
+	int data_len_16aligned = data_len & ~0xf;
+	int mono_cur, stereo_cur;
+	unsigned char *uc_buff = buff;
+
+	/* copy 8 times each loop */
+	for (stereo_cur = mono_cur = 0;
+	     stereo_cur < data_len_16aligned;
+	     stereo_cur += 16, mono_cur += 8) {
+
+		uc_buff[mono_cur + 0] = uc_buff[stereo_cur + 0];
+		uc_buff[mono_cur + 1] = uc_buff[stereo_cur + 2];
+		uc_buff[mono_cur + 2] = uc_buff[stereo_cur + 4];
+		uc_buff[mono_cur + 3] = uc_buff[stereo_cur + 6];
+		uc_buff[mono_cur + 4] = uc_buff[stereo_cur + 8];
+		uc_buff[mono_cur + 5] = uc_buff[stereo_cur + 10];
+		uc_buff[mono_cur + 6] = uc_buff[stereo_cur + 12];
+		uc_buff[mono_cur + 7] = uc_buff[stereo_cur + 14];
+	}
+
+	BUG_ON(stereo_cur != data_len_16aligned);
+
+	/* remaining data */
+	for (; stereo_cur < data_len; stereo_cur += 2, mono_cur++) {
+		uc_buff[mono_cur] = uc_buff[stereo_cur];
+	}
+
+	LEAVE();
+	return (data_len / 2);
+}
+
+/*
+ * Convert stereo data to mono data, and convert signed byte to unsigned byte.
+ *
+ * data width: 8 bits/channel
+ *
+ * buff:	buffer address
+ * data_len:	data length in kernel space, the length of stereo data
+ *		calculated by "node->end - node->start"
+ */
+int convert_8bits_stereo2mono_signed2unsigned(void *buff, int data_len)
+{
+	/* stride = 16 bytes = 2 channels * 1 byte * 8 pipelines */
+	int data_len_16aligned = data_len & ~0xf;
+	int mono_cur, stereo_cur;
+	unsigned char *uc_buff = buff;
+
+	/* copy 8 times each loop */
+	for (stereo_cur = mono_cur = 0;
+	     stereo_cur < data_len_16aligned;
+	     stereo_cur += 16, mono_cur += 8) {
+
+		uc_buff[mono_cur + 0] = uc_buff[stereo_cur + 0] + 0x80;
+		uc_buff[mono_cur + 1] = uc_buff[stereo_cur + 2] + 0x80;
+		uc_buff[mono_cur + 2] = uc_buff[stereo_cur + 4] + 0x80;
+		uc_buff[mono_cur + 3] = uc_buff[stereo_cur + 6] + 0x80;
+		uc_buff[mono_cur + 4] = uc_buff[stereo_cur + 8] + 0x80;
+		uc_buff[mono_cur + 5] = uc_buff[stereo_cur + 10] + 0x80;
+		uc_buff[mono_cur + 6] = uc_buff[stereo_cur + 12] + 0x80;
+		uc_buff[mono_cur + 7] = uc_buff[stereo_cur + 14] + 0x80;
+	}
+
+	BUG_ON(stereo_cur != data_len_16aligned);
+
+	/* remaining data */
+	for (; stereo_cur < data_len; stereo_cur += 2, mono_cur++) {
+		uc_buff[mono_cur] = uc_buff[stereo_cur] + 0x80;
+	}
+
+	LEAVE();
+	return (data_len / 2);
+}
+
+/*
+ * Convert stereo data to mono data, data width: 16 bits/channel
+ *
+ * buff:	buffer address
+ * data_len:	data length in kernel space, the length of stereo data
+ *		calculated by "node->end - node->start"
+ */
+int convert_16bits_stereo2mono(void *buff, int data_len)
+{
+	/* stride = 32 bytes = 2 channels * 2 byte * 8 pipelines */
+	int data_len_32aligned = data_len & ~0x1f;
+	int data_cnt_ushort = data_len_32aligned / 2;
+	int mono_cur, stereo_cur;
+	unsigned short *ushort_buff = (unsigned short *)buff;
+
+	/* copy 8 times each loop */
+	for (stereo_cur = mono_cur = 0;
+	     stereo_cur < data_cnt_ushort;
+	     stereo_cur += 16, mono_cur += 8) {
+
+		ushort_buff[mono_cur + 0] = ushort_buff[stereo_cur + 0];
+		ushort_buff[mono_cur + 1] = ushort_buff[stereo_cur + 2];
+		ushort_buff[mono_cur + 2] = ushort_buff[stereo_cur + 4];
+		ushort_buff[mono_cur + 3] = ushort_buff[stereo_cur + 6];
+		ushort_buff[mono_cur + 4] = ushort_buff[stereo_cur + 8];
+		ushort_buff[mono_cur + 5] = ushort_buff[stereo_cur + 10];
+		ushort_buff[mono_cur + 6] = ushort_buff[stereo_cur + 12];
+		ushort_buff[mono_cur + 7] = ushort_buff[stereo_cur + 14];
+	}
+
+	BUG_ON(stereo_cur != data_cnt_ushort);
+
+	/* remaining data */
+	for (; stereo_cur < data_cnt_ushort; stereo_cur += 2, mono_cur++) {
+		ushort_buff[mono_cur] = ushort_buff[stereo_cur];
+	}
+
+	LEAVE();
+	return (data_len / 2);
+}
+
+/*
+ * Set convert function for audio_pipe
+ *
+ * In AIC, we just use signed data for all ops as it is shared by
+ * replay and record. So, converting data for every non-compatible
+ * format is neccessary.
+ */
+static inline int endpoint_set_filter(audio_pipe *endpoint, int format, int channels)
+{
+	ENTER();
+
+	DPRINT("%s %d, endpoint = 0x%08x, format = %d, channels = %d\n",
+	       __FUNCTION__, __LINE__, (unsigned int)endpoint, format, channels);
+
+	endpoint->filter = NULL;
+
+	switch (format) {
+	case AFMT_U8:
+		if (endpoint == &in_endpoint) {
+			if (channels == 2) {
+				endpoint->filter = convert_8bits_stereo2mono_signed2unsigned;
+				DPRINT("$$$$ set pin_endpoint->filter = convert_8bits_stereo_2_mono\n");
+			} else {
+				endpoint->filter = convert_8bits_signed2unsigned;
+				DPRINT("$$$$ set pin_endpoint->filter = convert_8bits_signed2unsigned\n");
+			}
+		}
+		break;
+	case AFMT_S16_LE:
+		if (endpoint == &in_endpoint) {
+			if (channels == 1) {
+				endpoint->filter = convert_16bits_stereo2mono;
+				DPRINT("$$$$ set pin_endpoint->filter = convert_16bits_stereo2mono\n");
+			} else {
+				endpoint->filter = NULL;
+				DPRINT("$$$$ set pin_endpoint->filter = NULL\n");
+			}
+		}
+		break;
+	default:
+		printk("JZ I2S endpoint_set_filter: unknown format\n");
+		endpoint->filter = NULL;
+	}
+
+	LEAVE();
+	return 0;
+}
+
+/*
+ * The "format" contains data width, signed/unsigned and LE/BE
+ *
+ * The AIC registers will not be modified !
+ *
+ * For CODEC	set	data_width
+ */
+static int jz_codec_set_format(struct i2s_codec *codec, unsigned int format, int mode)
+{
+	/* The value of format reference to soundcard.h:
+	 *
+	 * AFMT_MU_LAW		0x00000001
+	 * AFMT_A_LAW		0x00000002
+	 * AFMT_IMA_ADPCM	0x00000004
+	 * AFMT_U8		0x00000008
+	 * AFMT_S16_LE		0x00000010
+	 * AFMT_S16_BE		0x00000020
+	 * AFMT_S8		0x00000040
+	 */
+	int data_width = 0;
+
+	ENTER();
+
+	DPRINT("$$$$ %s %d, format = %u, mode = %d\n", __FUNCTION__, __LINE__, format, mode);
+
+	down(&codec->i2s_sem);
+
+	/*
+	 * It is dangerous to modify settings about signed bit, endian and M2S
+	 * as record and replay shared the settings.
+	 *
+	 * Now we don't support unsigned format (AFMT_U8) and BE format (AFMT_S16_BE)
+	 * To support such format, corresponding filter function must be implemented.
+	 */
+	switch (format) {
+	case AFMT_U8:
+		data_width = 8;
+		if (mode & CODEC_RMODE) {
+			__i2s_set_iss_sample_size(8);
+		}
+		if (mode & CODEC_WMODE) {
+			__i2s_set_oss_sample_size(8);
+		}
+		break;
+	case AFMT_S8:
+		data_width = 8;
+		if (mode & CODEC_RMODE) {
+			__i2s_set_iss_sample_size(8);
+		}
+		if (mode & CODEC_WMODE) {
+			__i2s_set_oss_sample_size(8);
+		}
+		break;
+	case AFMT_S16_LE:
+		data_width = 16;
+		if (mode & CODEC_RMODE) {
+			__i2s_set_iss_sample_size(16);
+		}
+		if (mode & CODEC_WMODE) {
+			__i2s_set_oss_sample_size(16);
+		}
+		break;
+	case AFMT_S16_BE:
+		data_width = 16;
+		if (mode & CODEC_RMODE) {
+			__i2s_set_iss_sample_size(16);
+		}
+		if (mode & CODEC_WMODE) {
+			__i2s_set_oss_sample_size(16);
+		}
+		break;
+	default:
+		printk("JZ I2S: Unkown sound format %d\n", format);
+		goto _ERROR_SET_FORMAT;
+	}
+
+	if (mode & CODEC_RMODE) {
+		if (codec->codecs_ioctrl(codec, CODEC_SET_RECORD_DATA_WIDTH, data_width) < 0) {
+			printk("JZ I2S: CODEC ioctl error, command: CODEC_SET_RECORD_FORMAT");
+			goto _ERROR_SET_FORMAT;
+		}
+		codec->record_format = format;
+	}
+
+	if (mode & CODEC_WMODE) {
+		if (codec->codecs_ioctrl(codec, CODEC_SET_REPLAY_DATA_WIDTH, data_width) < 0) {
+			printk("JZ I2S: CODEC ioctl error, command: CODEC_SET_REPLAY_FORMAT");
+			goto _ERROR_SET_FORMAT;
+		}
+		codec->replay_format = format;
+	}
+
+	up(&codec->i2s_sem);
+	LEAVE();
+	return format;
+
+_ERROR_SET_FORMAT:
+	up(&codec->i2s_sem);
+	LEAVE();
+	return -1;
+}
+
+static int jz_audio_release(struct inode *inode, struct file *file)
+{
+	struct jz_i2s_controller_info *controller = (struct jz_i2s_controller_info *) file->private_data;
+	int mode = 0;
+	int codec_closed = 0;
+
+
+	ENTER();
+
+	if (controller == NULL) {
+		printk("\nAudio device not ready!\n");
+		return -ENODEV;
+	}
+	if ((controller->pin_endpoint == NULL) && (controller->pout_endpoint == NULL) ) {
+		printk("\nAudio endpoint not open!\n");
+		return -ENODEV;
+	}
+	if ((file->f_mode & FMODE_READ) && controller->pin_endpoint) {
+//		printk("Read mode, %s\n", __FUNCTION__);
+		mode |= CODEC_RMODE;
+		audio_close_endpoint(controller->pin_endpoint, FORCE_STOP);
+		controller->pin_endpoint = NULL;
+
+		__i2s_disable_receive_dma();
+		jz_codec_close(controller->i2s_codec, mode);
+		__i2s_disable_record();
+	}
+
+	if ((file->f_mode & FMODE_WRITE) && controller->pout_endpoint) {
+//		printk("Write mode, %s\n", __FUNCTION__);
+		mode |= CODEC_WMODE;
+		audio_close_endpoint(controller->pout_endpoint, NOMAL_STOP);
+		controller->pout_endpoint = NULL;
+
+		__i2s_disable_transmit_dma();
+
+		jz_codec_close(controller->i2s_codec, mode);
+		__i2s_enable_replay();
+		msleep(1);
+
+		__i2s_disable_replay();
+		codec_closed = 1;
+
+
+#ifdef CONFIG_JZ_EBOOK_HARD
+//		printk("DEBUG: %s, %d\n", __FUNCTION__, __LINE__);
+		__gpio_clear_pin(GPIO_SPK_SHUD);
+#endif
+	}
+
+
+	if ((controller->pin_endpoint == NULL) && (controller->pout_endpoint == NULL) ) {
+		__i2s_disable();
+	}
+
+	last_read_node = NULL;
+
+//	jz_codec_close(controller->i2s_codec, mode);
+
+#ifdef CONFIG_JZ_EBOOK_HARD
+//	printk("DEBUG: %s, %d\n", __FUNCTION__, __LINE__);
+//	__cpm_stop_aic1();
+	audio_device_open = 0;
+#endif
+
+	LEAVE();
+	return 0;
+}
+
+static int jz_audio_open(struct inode *inode, struct file *file)
+{
+	struct jz_i2s_controller_info *controller = the_i2s_controller;
+	struct i2s_codec *codec = controller->i2s_codec;
+	int mode = 0;
+	int reset = 1;
+
+	ENTER();
+
+	if (controller == NULL) {
+		return -ENODEV;
+	}
+#ifdef CONFIG_JZ_EBOOK_HARD
+//	printk("DEBUG: %s, %d\n", __FUNCTION__, __LINE__);
+//	__cpm_start_aic1();
+#endif
+
+	if (controller->pin_endpoint || controller->pout_endpoint) {
+		reset = 0;
+	}
+
+	if ((file->f_mode & FMODE_READ) && (controller->pin_endpoint)) {
+		printk("\nAudio read device is busy!\n");
+		return -EBUSY;
+	}
+	if ((file->f_mode & FMODE_WRITE) && (controller->pout_endpoint)) {
+		printk("\nAudio write device is busy!\n");
+		return -EBUSY;
+	}
+
+	if (file->f_mode & FMODE_WRITE) {
+		controller->pout_endpoint = &out_endpoint;
+		controller->pout_endpoint->is_non_block = file->f_flags & O_NONBLOCK;
+		mode |= CODEC_WMODE;
+	}
+	if (file->f_mode & FMODE_READ) {
+		controller->pin_endpoint = &in_endpoint;
+		controller->pin_endpoint->is_non_block = file->f_flags & O_NONBLOCK;
+		mode |= CODEC_RMODE;
+	}
+   	file->private_data = controller;
+
+	/* we should turn codec and anti-pop first */
+	jz_codec_anti_pop(controller->i2s_codec, mode);
+
+	if (mode & CODEC_RMODE){
+/*
+		jz_codec_set_channels(codec, 2, CODEC_RMODE);
+		jz_codec_set_format(codec, 8, CODEC_RMODE);
+		jz_codec_set_speed(codec, 8000, CODEC_RMODE);
+*/
+		jz_codec_set_channels(codec, 2, CODEC_RMODE);
+		jz_codec_set_format(codec, 16, CODEC_RMODE);
+		jz_codec_set_speed(codec, 44100, CODEC_RMODE);
+		codec->user_need_mono = 0;
+
+		set_controller_triger(controller, &in_endpoint, codec->record_codec_channel, codec->record_format);
+
+
+	}
+	if (mode & CODEC_WMODE) {
+		jz_codec_set_channels(codec, 2, CODEC_WMODE);
+		jz_codec_set_format(codec, 16, CODEC_WMODE);
+		jz_codec_set_speed(codec, 44100, CODEC_WMODE);
+		set_controller_triger(controller, &out_endpoint, codec->replay_codec_channel, codec->replay_format);
+#ifdef CONFIG_JZ_EBOOK_HARD
+//		printk("DEBUG: %s, %d\n", __FUNCTION__, __LINE__);
+		while (audio_device_pm_state == 1) schedule();
+		audio_device_open = 1;
+		if ((__gpio_get_pin(GPIO_HPONE_PLUG))) /* opposite logic with D21 */
+		{
+			__gpio_set_pin(GPIO_SPK_SHUD);
+		}
+#endif
+	}
+
+	DPRINT_IOC("============ default_codec record ===============\n"
+		   "format	= %d\n"
+		   "channels	= %d\n"
+		   "rate	= %d\n"
+		   "dma one tran bit = %d\n",
+		   codec->record_format, codec->record_codec_channel,
+		   codec->record_audio_rate, in_endpoint.dma.onetrans_bit);
+
+	DPRINT_IOC("============ default_codec replay ===============\n"
+		   "format	= %d\n"
+		   "channels	= %d\n"
+		   "rate	= %d\n"
+		   "dma one tran bit = %d\n",
+		   codec->replay_format, codec->replay_codec_channel,
+		   codec->replay_audio_rate, out_endpoint.dma.onetrans_bit);
+
+	jz_codec_select_mode(controller->i2s_codec, mode);
+
+	/* note: reset AIC  protected REG_AIC_I2SCR.ECCLK is setting */
+	if (reset) {
+		down(&controller->i2s_codec->i2s_sem);
+		//__i2s_enable_transmit_dma();
+		//__i2s_enable_receive_dma();
+		//__i2s_enable_replay();
+		__i2s_enable();
+		up(&controller->i2s_codec->i2s_sem);
+	}
+	//reinit codec option
+
+	//DUMP_AIC_REGS();
+	DPRINT_TRC(".... jz_audio_open\n");
+
+	g_play_first = 0;
+
+	LEAVE();
+	return 0;
+}
+
+static int jz_audio_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
+{
+	long	rc = -EINVAL;
+	int	val = 0;
+	int	mode = 0;
+
+	struct jz_i2s_controller_info *controller = (struct jz_i2s_controller_info *) file->private_data;
+	struct i2s_codec *codec = controller->i2s_codec;
+	audio_pipe	*pin_endpoint = controller->pin_endpoint;
+	audio_pipe	*pout_endpoint = controller->pout_endpoint;
+
+	ENTER();
+
+	DPRINT_IOC("[dsp IOCTL] --------------------------------\n");
+	DPRINT_IOC(" dsp IOCTL %s cmd = (0x%08x), arg = %lu\n", __FUNCTION__, cmd, arg);
+	DPRINT_DSP_IOC_CMD(cmd);
+	DPRINT_IOC("[dsp IOCTL] --------------------------------\n");
+
+	if (file->f_mode & FMODE_READ) {
+		mode |= CODEC_RMODE;
+	}
+	if (file->f_mode & FMODE_WRITE) {
+		mode |= CODEC_WMODE;
+	}
+
+	switch (cmd) {
+
+	case OSS_GETVERSION:
+		rc = put_user(SOUND_VERSION, (int *)arg);
+		break;
+	case SNDCTL_DSP_RESET:
+		break;
+
+	case SNDCTL_DSP_SYNC:
+		if (mode & CODEC_WMODE) {
+			if (pout_endpoint) {
+				audio_sync_endpoint(pout_endpoint);
+			}
+		}
+		rc = 1;
+		break;
+
+	case SNDCTL_DSP_SPEED:
+		/* set smaple rate */
+		if (get_user(val, (int *)arg)) {
+			rc = -EFAULT;
+		}
+		//printk("SNDCTL_DSP_SPEED ... set to %d\n", val);
+		val = jz_codec_set_speed(codec, val, mode);
+		rc = put_user(val, (int *)arg);
+		break;
+
+	case SNDCTL_DSP_STEREO:
+		/* set stereo or mono channel */
+		if (get_user(val, (int *)arg)) {
+		    rc = -EFAULT;
+		}
+
+		jz_codec_set_channels(controller->i2s_codec, val ? 2 : 1, mode);
+
+		if (mode & CODEC_RMODE) {
+			set_controller_triger(controller, pin_endpoint,
+					      codec->record_codec_channel, codec->record_format);
+		}
+
+		if (mode & CODEC_WMODE) {
+			set_controller_triger(controller, pout_endpoint,
+					      codec->replay_codec_channel, codec->replay_format);
+		}
+
+		rc = 1;
+		break;
+
+	case SNDCTL_DSP_GETBLKSIZE:
+	{
+		// It seems that device could only be open with one mode (R or W)
+		int fragsize = 0;
+		if (mode & CODEC_RMODE) {
+			fragsize = pin_endpoint->fragsize;
+		}
+		if (mode & CODEC_WMODE) {
+			fragsize = pout_endpoint->fragsize;
+		}
+		rc = put_user(fragsize, (int *)arg);
+		break;
+	}
+
+	case SNDCTL_DSP_GETFMTS:
+		/* Returns a mask of supported sample format*/
+		rc = put_user(AFMT_U8 | AFMT_S16_LE, (int *)arg);
+		break;
+
+	case SNDCTL_DSP_SETFMT:
+		/* Select sample format */
+		if (get_user(val, (int *)arg)) {
+			rc = -EFAULT;
+		}
+
+//		printk("\nSNDCTL_DSP_SETFMT ... set to %d\n", val);
+
+		if (val == AFMT_QUERY) {
+			if (mode & CODEC_RMODE) {
+				val = codec->record_format;
+			} else {
+				val = codec->replay_format;
+			}
+		} else {
+			val = jz_codec_set_format(codec, val, mode);
+			if (mode & CODEC_RMODE) {
+				if (codec->user_need_mono) {
+					endpoint_set_filter(pin_endpoint, val, 1);
+				} else {
+					endpoint_set_filter(pin_endpoint, val, 2);
+				}
+
+				set_controller_triger(controller, pin_endpoint,
+						      codec->record_codec_channel, codec->record_format);
+			}
+			if (mode & CODEC_WMODE) {
+				set_controller_triger(controller, pout_endpoint,
+						      codec->replay_codec_channel, codec->replay_format);
+			}
+		}
+
+		rc = put_user(val, (int *)arg);
+		break;
+
+	case SNDCTL_DSP_CHANNELS:
+		if (get_user(val, (int *)arg)) {
+			rc = -EFAULT;
+		}
+		//printk("\nSNDCTL_DSP_CHANNELS ... set to %d\n", val);
+
+		/* if mono, change to 2, and set 1 to codec->user_need_mono */
+		if (mode & CODEC_RMODE) {
+			if (val == 1) {
+				val = 2;
+				codec->user_need_mono = 1;
+
+			} else {
+				codec->user_need_mono = 0;
+			}
+		}
+
+		/* Following lines could be marked as nothing will be changed */
+		jz_codec_set_channels(codec, val, mode);
+
+		if (mode & CODEC_RMODE) {
+			/* Set filter according to channel count */
+			if (codec->user_need_mono) {
+				endpoint_set_filter(pin_endpoint, codec->record_format, 1);
+			} else {
+				endpoint_set_filter(pin_endpoint, codec->record_format, 2);
+			}
+
+			set_controller_triger(controller, pin_endpoint,
+					      codec->record_codec_channel, codec->record_format);
+		}
+		if (mode & CODEC_WMODE) {
+			set_controller_triger(controller, pout_endpoint,
+					      codec->replay_codec_channel, codec->replay_format);
+		}
+
+		/* Restore for return value */
+		if (codec->user_need_mono) {
+			val = 1;
+		}
+
+		rc = put_user(val, (int *)arg);
+		break;
+
+	case SNDCTL_DSP_POST:
+		/* FIXME: the same as RESET ?? */
+		break;
+
+	case SNDCTL_DSP_SUBDIVIDE:
+		break;
+
+	case SNDCTL_DSP_SETFRAGMENT:
+		rc = get_user(val, (long *) arg);
+		if (rc != -EINVAL) {
+			int newfragsize, newfragstotal;
+			newfragsize = 1 << (val & 0xFFFF);
+			if (newfragsize < 4 * PAGE_SIZE) {
+				newfragsize = 4 * PAGE_SIZE;
+			}
+			if (newfragsize > (16 * PAGE_SIZE)) {
+				newfragsize = 16 * PAGE_SIZE;
+			}
+
+			newfragstotal = (val >> 16) & 0x7FFF;
+			if (newfragstotal < 2) {
+				newfragstotal = 2;
+			}
+			if (newfragstotal > 32) {
+				newfragstotal = 32;
+			}
+
+			if (mode & CODEC_RMODE) {
+				rc = audio_resizemem_endpoint(controller->pin_endpoint, newfragsize, newfragstotal);
+				if (!rc) {
+					rc = -EINVAL;
+				}
+			}
+			if (mode & CODEC_WMODE) {
+				rc = audio_resizemem_endpoint(controller->pout_endpoint, newfragsize, newfragstotal);
+				if (!rc) {
+					rc = -EINVAL;
+				}
+			}
+		}
+		break;
+
+	case SNDCTL_DSP_GETCAPS:
+		rc = put_user(DSP_CAP_REALTIME | DSP_CAP_BATCH, (int *)arg);
+		break;
+
+	case SNDCTL_DSP_NONBLOCK:
+		file->f_flags |= O_NONBLOCK;
+		rc = 0;
+		break;
+
+	case SNDCTL_DSP_SETDUPLEX:
+		rc = -EINVAL;
+		break;
+
+	case SNDCTL_DSP_GETOSPACE:
+	{
+		audio_buf_info abinfo;
+		if (!(mode & CODEC_WMODE)) {
+			return -EINVAL;
+		}
+		audio_get_endpoint_freesize(pout_endpoint, &abinfo);
+		rc = copy_to_user((void *)arg, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
+		break;
+	}
+
+	case SNDCTL_DSP_GETISPACE:
+	{
+		audio_buf_info abinfo;
+		if (!(mode & CODEC_RMODE)) {
+			return -EINVAL;
+		}
+		audio_get_endpoint_freesize(controller->pin_endpoint, &abinfo);
+		rc = copy_to_user((void *)arg, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
+		break;
+	}
+
+	case SNDCTL_DSP_GETTRIGGER:
+		val = 0;
+		if ((mode & CODEC_RMODE) && controller->pin_endpoint) {
+			val |= PCM_ENABLE_INPUT;
+		}
+		if ((mode & CODEC_WMODE) && controller->pout_endpoint) {
+			val |= PCM_ENABLE_OUTPUT;
+		}
+		rc = put_user(val, (int *)arg);
+
+		break;
+
+	case SNDCTL_DSP_SETTRIGGER:
+		if (get_user(val, (int *)arg)) {
+			rc = -EFAULT;
+		}
+		break;
+
+	case SNDCTL_DSP_GETIPTR:
+	{
+		count_info cinfo;
+		if (!(mode & CODEC_RMODE)) {
+			rc = -EINVAL;
+		}
+		rc = copy_to_user((void *)arg, &cinfo, sizeof(cinfo));
+		break;
+	}
+
+	case SNDCTL_DSP_GETOPTR:
+	{
+		count_info cinfo;
+		if (!(mode & CODEC_WMODE)) {
+			rc = -EINVAL;
+		}
+		rc = copy_to_user((void *) arg, &cinfo, sizeof(cinfo));
+		break;
+	}
+
+	case SNDCTL_DSP_GETODELAY:
+	{
+		// fix me !!!
+		int unfinish = 0;
+		if (!(mode & CODEC_WMODE)) {
+			rc = -EINVAL;
+		}
+		rc = put_user(unfinish, (int *) arg);
+		break;
+	}
+
+	case SOUND_PCM_READ_RATE:
+		if (mode  & CODEC_RMODE) {
+			//printk("\nSOUND_PCM_READ_RATE = %d\n", codec->record_audio_rate);
+			rc = put_user(codec->record_audio_rate, (int *)arg);
+		}
+		if (mode & CODEC_WMODE) {
+			//printk("\nSOUND_PCM_READ_RATE = %d\n", codec->replay_audio_rate);
+			rc = put_user(codec->replay_audio_rate, (int *)arg);
+		}
+		break;
+
+	case SOUND_PCM_READ_CHANNELS:
+		if (mode & CODEC_RMODE) {
+			//printk("\nSOUND_PCM_READ_RATE = %d\n", codec->record_codec_channel);
+			rc = put_user(codec->record_codec_channel, (int *)arg);
+		}
+		if (mode & CODEC_WMODE) {
+			//printk("\nSOUND_PCM_READ_RATE = %d\n", codec->replay_codec_channel);
+			rc = put_user(codec->replay_codec_channel, (int *)arg);
+		}
+		break;
+
+	case SOUND_PCM_READ_BITS:
+		if (mode & CODEC_RMODE) {
+			rc = put_user((codec->record_format & (AFMT_S8 | AFMT_U8)) ? 8 : 16, (int *)arg);
+		}
+		if (mode & CODEC_WMODE) {
+			rc = put_user((codec->record_format & (AFMT_S8 | AFMT_U8)) ? 8 : 16, (int *)arg);
+		}
+		break;
+
+	case SNDCTL_DSP_MAPINBUF:
+	case SNDCTL_DSP_MAPOUTBUF:
+	case SNDCTL_DSP_SETSYNCRO:
+	case SOUND_PCM_WRITE_FILTER:
+	case SOUND_PCM_READ_FILTER:
+		rc = -EINVAL;
+		break;
+#if 0
+	/* may be for msm only */
+	case AUDIO_GET_CONFIG:
+ 		break;
+
+	case AUDIO_SET_CONFIG:
+		break;
+#endif
+	default:
+		printk("%s[%s]:%d---no cmd\n",__FILE__,__FUNCTION__,__LINE__);
+		break;
+	}
+
+	LEAVE();
+
+	return rc;
+}
+
+static inline int endpoint_put_userdata(audio_pipe *endpoint, const char __user *buffer, size_t count)
+{
+	unsigned long	flags;
+	audio_node	*node;
+
+	ENTER();
+	DPRINT("<<<< put_userdata\n");
+
+	AUDIO_LOCK(endpoint->lock, flags);
+	node = get_audio_freenode(endpoint->mem);
+	AUDIO_UNLOCK(endpoint->lock, flags);
+
+	// For non-block mode
+	if (endpoint->is_non_block && !node) {
+		LEAVE();
+		return 0;
+	}
+
+	// For block mode, wait free node
+	while (!node) {
+		DPRINT("wait ----------\n");
+
+		AUDIO_LOCK(endpoint->lock, flags);
+		DUMP_LIST((audio_head *)endpoint->mem);
+		DUMP_NODE(endpoint->savenode, "SN");
+		AUDIO_UNLOCK(endpoint->lock, flags);
+
+		// wait available node
+		wait_event_interruptible(endpoint->q_full, (endpoint->avialable_couter >= 1));
+
+		AUDIO_LOCK(endpoint->lock, flags);
+		node = get_audio_freenode(endpoint->mem);
+		endpoint->avialable_couter = 0;
+		AUDIO_UNLOCK(endpoint->lock, flags);
+	}
+
+	if (copy_from_user((void *)node->pBuf, buffer, count)) {
+		printk("JZ I2S: copy_from_user failed !\n");
+		return -EFAULT;
+	}
+	dma_cache_wback_inv((unsigned long)node->pBuf,(unsigned long)count);
+	node->start = 0;
+	node->end = count;
+	AUDIO_LOCK(endpoint->lock, flags);
+	put_audio_usenode(endpoint->mem, node);
+	AUDIO_UNLOCK(endpoint->lock, flags);
+
+	LEAVE();
+
+	return count;
+}
+
+static ssize_t jz_audio_write(struct file *file, const char __user *buffer, size_t count, loff_t *ppos)
+{
+	struct jz_i2s_controller_info *controller = (struct jz_i2s_controller_info *)file->private_data;
+	audio_pipe *pout_endpoint = controller->pout_endpoint;
+	struct i2s_codec *codec = (struct i2s_codec *)controller->i2s_codec;
+	size_t	usecount = 0;
+	int	bat_cnt = -1;
+	int	rem_cnt = 0;
+
+	if (!g_play_first) {
+		// first play, trun on dac mute
+		codec_ioctrl(codec, CODEC_FIRST_OUTPUT, 0);
+		g_play_first = 1;
+		if (codec->audio_volume == 0)
+			codec_ioctrl(codec, CODEC_DAC_MUTE, 1);
+	}
+
+	ENTER();
+
+	//dump_dlv_regs(__FUNCTION__);
+	//dump_aic_regs(__FUNCTION__);
+
+	// wll@20101020
+//	printk("===>enter %s: \n", __FUNCTION__);
+//	printk("write data count = %d\n", count);
+
+	while (count >= pout_endpoint->fragsize) {
+
+		bat_cnt = endpoint_put_userdata(pout_endpoint,
+						&(buffer[usecount]),
+						pout_endpoint->fragsize);
+		// Prepare data success.
+		if (bat_cnt > 0) {
+			usecount += bat_cnt;
+			count -= bat_cnt;
+			DPRINT("bat_cnt = %d\n", bat_cnt);
+		}
+		// Perhaps non node is avialable.
+		else if (bat_cnt == 0) {
+			DPRINT("bat_cnt == 0\n");
+			break;
+		}
+		// Error occured.
+		else {
+			// break and handle prepared data.
+			if (usecount > 0) {
+				DPRINT("bat_cnt < 0, usecount > 0\n");
+				break;
+			}
+			// Has not prepared any data and return error when prepared data.
+			else {
+				DPRINT("bat_cnt < 0, usecount == 0\n");
+				return bat_cnt;
+			}
+		}
+	}
+
+	DPRINT("count = %d\n", count);
+
+	// Prepare few data or remain data after below code.
+	if (bat_cnt != 0 && count >= 32) {
+		DPRINT("check point 2 ... count = %d\n", count);
+		rem_cnt = endpoint_put_userdata(pout_endpoint, &buffer[usecount], count);
+		if (rem_cnt > 0) {
+			usecount += rem_cnt;
+			count -= rem_cnt;
+			DPRINT("check point 3 ... rem_cnt = %d\n", rem_cnt);
+		} else if (rem_cnt <= 0) {
+			// Not success... return Error.
+			if (usecount == 0) {
+				DPRINT("rem_cnt <= 0, usecount == 0\n");
+				return rem_cnt;
+			}
+			// Go on handle prepared data, ignore the error.
+			else {
+				DPRINT("rem_cnt <= 0, usecount != 0, usecount = %d\n", usecount);
+			}
+		}
+	}
+
+	// Handle prepared data.
+	if (usecount > 0) {
+		unsigned long	flags;
+		audio_node	*node;
+		AUDIO_LOCK(pout_endpoint->lock, flags);
+		if ((pout_endpoint->trans_state & PIPE_TRANS) == 0) {
+			node = get_audio_usenode(pout_endpoint->mem);
+			if (node) {
+				unsigned int start;
+				start = trystart_endpoint_out(controller, node);
+				if (start == 0) {
+					printk("JZ I2S: trystart_endpoint_out error\n");
+				}
+			}
+		}
+		AUDIO_UNLOCK(pout_endpoint->lock, flags);
+	}
+
+	DPRINT("----write data usecount = %d, count = %d\n", usecount, count);
+	BUG_ON(count < 0);
+	LEAVE();
+
+	return usecount + (count < 32 ? count : 0);
+}
+
+/**
+ *  Copy recorded sound data from 'use' link list to userspace
+ */
+static inline int endpoint_get_userdata(audio_pipe *endpoint, const char __user *buffer, size_t count)
+{
+	unsigned long	flags;
+	audio_node	*node = last_read_node;
+	int	ret;
+
+	/* counter for node buffer, raw data */
+	int	node_buff_cnt = 0;
+
+	ENTER();
+
+	if (!node) {
+		AUDIO_LOCK(endpoint->lock, flags);
+		node = get_audio_usenode(endpoint->mem);
+		AUDIO_UNLOCK(endpoint->lock, flags);
+
+		if (node && endpoint->filter) {
+			node_buff_cnt = node->end - node->start;
+			node_buff_cnt = endpoint->filter((void *)(node->pBuf + node->start), node_buff_cnt);
+			node->end = node->start + node_buff_cnt;
+		}
+	}
+
+	DPRINT(">>>> %s mode\n", endpoint->is_non_block ? "non block" : "block");
+
+	// For non-block mode
+	if (endpoint->is_non_block && !node) {
+		return 0;
+	}
+
+	// For block mode, wait node which full filled data
+	while (!node) {
+		if ((endpoint->trans_state & PIPE_TRANS) == 0 ) {
+			DPRINT("DMA trans has not been started !\n");
+			return -1;
+		}
+
+		AUDIO_LOCK(endpoint->lock, flags);
+		DUMP_LIST((audio_head *)endpoint->mem);
+		DUMP_NODE(endpoint->savenode, "SN");
+		AUDIO_UNLOCK(endpoint->lock, flags);
+
+		DPRINT("record stereo ... wait pipe_sem ----------\n");
+
+		// wait available node
+//		interruptible_sleep_on(&endpoint->q_full);
+		wait_event_interruptible(endpoint->q_full, endpoint->avialable_couter >= 1);
+
+		AUDIO_LOCK(endpoint->lock, flags);
+		node = get_audio_usenode(endpoint->mem);
+		endpoint->avialable_couter = 0;
+		AUDIO_UNLOCK(endpoint->lock, flags);
+
+		if (node && endpoint->filter) {
+			node_buff_cnt = node->end - node->start;
+			node_buff_cnt = endpoint->filter((void *)(node->pBuf + node->start), node_buff_cnt);
+			node->end = node->start + node_buff_cnt;
+		}
+	}
+
+	if (node && (node_buff_cnt = node->end - node->start)) {
+		DPRINT("node_buff_cnt = %d, count = %d\n", node_buff_cnt, count);
+
+		if (count >= (size_t)node_buff_cnt) {
+			DPRINT(">>>> count >= fixed_buff_cnt, copy_to_user count = %d\n", node_buff_cnt);
+			ret = copy_to_user((void *)buffer, (void *)(node->pBuf + node->start), node_buff_cnt);
+			if (ret) {
+				printk("JZ I2S: copy_to_user failed, return %d\n", ret);
+				return -EFAULT;
+			}
+			put_audio_freenode(endpoint->mem, node);
+			last_read_node = NULL;
+		} else {
+			DPRINT(">>>> count < fixed_buff_cnt, copy_to_user count = %d\n", count);
+			ret = copy_to_user((void *)buffer,(void *)(node->pBuf + node->start), count);
+			if (ret) {
+				printk("JZ I2S: copy_to_user failed, return %d\n", ret);
+				return -EFAULT;
+			}
+			node->start += count;
+			last_read_node = node;
+		}
+	}
+
+	LEAVE();
+	return (node_buff_cnt < count ? node_buff_cnt : count);
+}
+
+static ssize_t jz_audio_read(struct file *file, char __user *buffer, size_t count, loff_t *ppos)
+{
+	struct jz_i2s_controller_info *controller = (struct jz_i2s_controller_info *)file->private_data;
+	audio_pipe	*pin_endpoint = controller->pin_endpoint;
+	audio_node	*node;
+	unsigned long	flags;
+	int		mcount, usecount = 0;
+
+	ENTER();
+
+//	dump_dlv_regs(__FUNCTION__);
+//	dump_aic_regs(__FUNCTION__);
+
+	if (count == 0) {
+		DPRINT("@@@@ jz_audio_read count == 0\n");
+		return 0;
+	}
+
+	AUDIO_LOCK(pin_endpoint->lock, flags);
+
+	DUMP_LIST((audio_head *)pin_endpoint->mem);
+	DUMP_NODE(pin_endpoint->savenode, "SN");
+
+	DPRINT("@@@@ jz_audio_read, pin_endpoint->trans_state = 0x%08x\n",
+	       pin_endpoint->trans_state);
+
+	if ((pin_endpoint->trans_state & PIPE_TRANS) == 0) {
+		DPRINT("@@@@ jz_audio_read, PIPE_TRANS\n");
+		node = get_audio_freenode(pin_endpoint->mem);
+		if (node) {
+			unsigned int start;
+			DPRINT("@@@@ jz_audio_read, trystart_endpoint_in\n");
+//			pin_endpoint->fragsize = count;
+			node->end = pin_endpoint->fragsize;
+
+			start = trystart_endpoint_in(controller, node);
+			if (start == 0) {
+				DPRINT("@@@@ Error ! jz_audio_read, start == 0\n");
+				put_audio_freenode(pin_endpoint->mem, node);
+			}
+		}
+	}
+	AUDIO_UNLOCK(pin_endpoint->lock, flags);
+
+	DUMP_AIC_REGS(__FUNCTION__);
+	DUMP_CODEC_REGS(__FUNCTION__);
+	//dump_dlv_regs(__FUNCTION__);
+	DPRINT("@@@@ count = %d\n", count);
+
+	do{
+		mcount = endpoint_get_userdata(pin_endpoint, &buffer[usecount], count);
+
+		DPRINT("@@@@ jz_audio_read, mcount = %d, usecount = %d\n", mcount, usecount);
+
+		if (mcount < 0) {
+			DPRINT("@@@@ jz_audio_read, mcount < 0, %d\n", mcount);
+			if (usecount > 0) {
+				break;
+			} else {
+				return mcount;
+			}
+		} else if (mcount == 0) {
+			DPRINT("@@@@ jz_audio_read, mcount == 0\n");
+			break;
+		} else {
+			usecount += mcount;
+			count -= mcount;
+			DPRINT("@@@@ jz_audio_read, mcount > 0, %d\n", mcount);
+		}
+	} while (count > 0);
+
+	DPRINT("@@@@ jz_audio_read, usecount = %d\n", usecount);
+
+	LEAVE();
+	return usecount;
+}
+
+/* static struct file_operations jz_i2s_audio_fops */
+static struct file_operations jz_i2s_audio_fops = {
+	owner:		THIS_MODULE,
+	open:		jz_audio_open,
+	release:	jz_audio_release,
+	write:		jz_audio_write,
+	read:		jz_audio_read,
+	ioctl:		jz_audio_ioctl
+};
+
+static void __init attach_jz_i2s(struct jz_i2s_controller_info *controller)
+{
+	char	*name = NULL;
+	int	adev = 0; /* No of Audio device. */
+
+	ENTER();
+
+	name = controller->name;
+
+	/* Initialize I2S CODEC and register /dev/mixer. */
+	if (jz_i2s_codec_init(controller) <= 0) {
+		goto mixer_failed;
+	}
+
+	/* Initialize AIC controller and reset it. */
+	jz_i2s_reinit_hw(controller->i2s_codec,1);
+	adev = register_sound_dsp(&jz_i2s_audio_fops, -1);
+	if (adev < 0) {
+		goto audio_failed;
+	}
+
+	controller->dev_audio = adev;
+
+	LEAVE();
+
+	return;
+mixer_failed:
+
+audio_failed:
+	unregister_sound_dsp(adev);
+
+	LEAVE();
+	return;
+}
+
+static void __exit unload_jz_i2s(struct jz_i2s_controller_info *controller)
+{
+	jz_i2s_reinit_hw(controller->i2s_codec,0);
+}
+
+//--------------------------------------------------------------------
+#ifdef CONFIG_PM
+static int jz_i2s_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	int i;
+	struct i2s_codec *codec;
+	//audio_sync_endpoint(&out_endpoint);
+	//msleep(30);
+	for(i = 0;i < NR_I2S; i++){
+		codec = &the_codecs[i];
+		if (codec && codec->codecs_ioctrl) {
+			codec->codecs_ioctrl(codec, CODEC_I2S_SUSPEND, 0);
+		}
+	}
+
+//	printk("Aic and codec are suspended!\n");
+	return 0;
+}
+
+static int jz_i2s_resume(struct platform_device *pdev)
+{
+	int i;
+	struct i2s_codec *codec;
+	for(i = 0;i < NR_I2S; i++){
+		codec = &the_codecs[i];
+		if (codec && codec->codecs_ioctrl) {
+			codec->codecs_ioctrl(codec, CODEC_I2S_RESUME, 0);
+		}
+	}
+	return 0;
+}
+#endif /* CONFIG_PM */
+
+static int __init probe_jz_i2s(struct jz_i2s_controller_info **controller)
+{
+	struct jz_i2s_controller_info *ctrl;
+
+	ENTER();
+	ctrl = kmalloc(sizeof(struct jz_i2s_controller_info), GFP_KERNEL);
+	if (ctrl == NULL) {
+		printk(KERN_ERR "Jz I2S Controller: out of memory.\n");
+		return -ENOMEM;
+	}
+	ctrl->name = "Jz I2S controller";
+	ctrl->pout_endpoint = 0;
+	ctrl->pin_endpoint = 0;
+	ctrl->error = 0;
+	//ctrl->i2s_codec->use_mic_line_flag = USE_NONE;
+
+	*controller = ctrl;
+
+	LEAVE();
+
+	return 0;
+}
+
+void i2s_controller_init(void)
+{
+	unsigned int aicfr;
+	unsigned int aiccr;
+	//init cpm clock, use ext clock;
+
+	ENTER();
+
+	/* Select exclk as i2s clock */
+	cpm_set_clock(CGU_I2SCLK, JZ_EXTAL);
+
+	aicfr = (8 << 12) | (8 << 8) | (AIC_FR_ICDC | AIC_FR_LSMP | AIC_FR_AUSEL);
+	REG_AIC_FR = aicfr;
+
+	aiccr = REG_AIC_CR;
+	aiccr &= (~(AIC_CR_EREC | AIC_CR_ERPL | AIC_CR_TDMS | AIC_CR_RDMS));
+	REG_AIC_CR = aiccr;
+
+	LEAVE();
+}
+
+static int __init init_jz_i2s(struct platform_device *pdev)
+{
+	struct i2s_codec *default_codec = &(the_codecs[0]);
+	int errno;
+	int fragsize;
+	int fragstotal;
+
+	printk("===>enter %s\n", __func__);
+
+#ifdef CONFIG_JZ_EBOOK_HARD
+//	printk("DEBUG: %s, %d\n", __FUNCTION__, __LINE__);
+//	__cpm_start_aic1();
+#endif
+
+	cpm_start_clock(CGM_AIC);
+
+	REG_AIC_I2SCR |= AIC_I2SCR_ESCLK;
+
+	i2s_controller_init();
+	if (default_codec->codecs_ioctrl == NULL) {
+		printk("default_codec: not ready!");
+		return -1;
+	}
+
+	//default_codec->codecs_ioctrl(default_codec, CODEC_SET_MODE, 0);
+	default_codec->codecs_ioctrl(default_codec, CODEC_INIT, 0);
+
+	if ((errno = probe_jz_i2s(&the_i2s_controller)) < 0) {
+		return errno;
+	}
+
+	/* May be external CODEC need it ...
+	 * default_codec->codecs_ioctrl(default_codec, CODEC_SET_GPIO_PIN, 0);
+	 */
+	attach_jz_i2s(the_i2s_controller);
+
+	/* Actually, the handler function of the command do nothing ...
+	 * default_codec->codecs_ioctrl(default_codec, CODEC_SET_STARTUP_PARAM, 0);
+	 * default_codec->codecs_ioctrl(default_codec, CODEC_SET_STARTUP_PARAM, 0);
+	 */
+
+	/* Now the command is not supported by DLV CODEC ...
+	 * default_codec->codecs_ioctrl(default_codec, CODEC_SET_VOLUME_TABLE, 0);
+	 */
+	fragsize = JZCODEC_RW_BUFFER_SIZE * PAGE_SIZE;
+	fragstotal = JZCODEC_RW_BUFFER_TOTAL;
+
+	audio_init_endpoint(&out_endpoint, fragsize, fragstotal);
+	audio_init_endpoint(&in_endpoint, fragsize, fragstotal);
+
+#ifdef CONFIG_JZ_EBOOK_HARD
+//	printk("DEBUG: %s, %d\n", __FUNCTION__, __LINE__);
+//	__cpm_stop_aic1();
+	audio_device_open = 0;
+#endif
+
+	printk("JZ I2S OSS audio driver initialized\n");
+
+	LEAVE();
+
+	return 0;
+}
+
+static void __exit cleanup_jz_i2s(void)
+{
+#ifdef CONFIG_PM
+	/* pm_unregister(i2s_controller->pm); */
+#endif
+	struct i2s_codec *default_codec = &the_codecs[0];
+	unload_jz_i2s(the_i2s_controller);
+	the_i2s_controller = NULL;
+	audio_deinit_endpoint(&out_endpoint);
+	audio_deinit_endpoint(&in_endpoint);
+	default_codec->codecs_ioctrl(default_codec, CODEC_CLEAR_MODE, 0);
+}
+
+static struct platform_driver snd_plat_driver = {
+	.probe	=  init_jz_i2s,
+	.driver	= {
+		.name	= "mixer",
+		.owner	= THIS_MODULE,
+	},
+	.suspend	= jz_i2s_suspend,
+	.resume		= jz_i2s_resume,
+};
+
+static int __init snd_init(void)
+{
+	return platform_driver_register(&snd_plat_driver);
+}
+
+module_init(snd_init);
+module_exit(cleanup_jz_i2s);
diff --git a/sound/oss/jz_codec.h b/sound/oss/jz_codec.h
index 680d8dac76c..607bfe36304 100644
--- a/sound/oss/jz_codec.h
+++ b/sound/oss/jz_codec.h
@@ -77,7 +77,7 @@
 

 //-------------------------------------------------

 

-#define CODEC_DEBUG			100

+//#define CODEC_DEBUG			100

 

 //-------------------------------------------------

 

diff --git a/sound/oss/jz_i2s_dbg.h b/sound/oss/jz_i2s_dbg.h
index a2088d2e6b3..8cac3a7b830 100644
--- a/sound/oss/jz_i2s_dbg.h
+++ b/sound/oss/jz_i2s_dbg.h
@@ -33,31 +33,32 @@
 #endif
 
 #ifdef AIC_DEBUG_LEVEL2
-  #define REG_DEBUG			1
-  #define DMA_DEBUG			1
-  #define BUF_DEBUG			1
-  #define Q_DEBUG			1
-  #define TRACE_DEBUG			1
-  #define IRQ_DEBUG			1
-  #define IOC_DEBUG			1
-  #define CODEC_DEBUG			1
-  #define OTHER_DEBUG			1
+  #define REG_DEBUG			0
+  #define DMA_DEBUG			0
+  #define BUF_DEBUG			0
+  #define Q_DEBUG			0
+  #define TRACE_DEBUG			0
+  #define IRQ_DEBUG			0
+  #define IOC_DEBUG			0
+  #define CODEC_DEBUG			0
+  #define OTHER_DEBUG			0
 #endif
 
 #ifdef AIC_DEBUG_LEVEL1
-  #define OTHER_DEBUG			1
-  #define IRQ_DEBUG			1
-  #define DMA_DEBUG			1
-  #define REG_DEBUG			1
-//  #define IOC_DEBUG			1
+  #define OTHER_DEBUG			0
+  #define IRQ_DEBUG			0
+  #define DMA_DEBUG			0
+  #define REG_DEBUG			0
+//  #define IOC_DEBUG			0
 #endif
 
 #ifdef AIC_DEBUG_LEVEL0
-  #define IRQ_DEBUG			1
-  #define TRACE_DEBUG			1
+  #define IRQ_DEBUG			0
+  #define TRACE_DEBUG			0
 #endif
 
-#ifdef CODEC_DEBUG
+//#ifdef CODEC_DEBUG
+#if 0
   #define DPRINT_CODEC(msg...)		printk(msg)
 #else
   #define DPRINT_CODEC(msg...)		do{} while (0)
diff --git a/sound/oss/jztest_dlv.c b/sound/oss/jztest_dlv.c
new file mode 100644
index 00000000000..eabce17eb84
--- /dev/null
+++ b/sound/oss/jztest_dlv.c
@@ -0,0 +1,1290 @@
+/*

+ * Linux/sound/oss/jz_dlv.c

+ *

+ * DLV CODEC driver for Ingenic Jz4750 MIPS processor

+ *

+ * 2009-12-xx	Steven <dsqiu@ingenic.cn>

+ * 2010-01-xx	Jason <xwang@ingenic.cn>

+ *

+ * Copyright (c) Ingenic Semiconductor Co., Ltd.

+ */

+

+#include <linux/init.h>

+#include <linux/interrupt.h>

+#include <linux/sched.h>

+#include <linux/delay.h>

+#include <linux/workqueue.h>

+#include <linux/sound.h>

+#include <linux/slab.h>

+#include <sound/core.h>

+#include <sound/initval.h>

+#include <linux/proc_fs.h>

+#include <linux/soundcard.h>

+#include <linux/dma-mapping.h>

+#include <linux/mutex.h>

+#include <linux/mm.h>

+#include <asm/hardirq.h>

+#include <asm/jzsoc.h>

+

+#include "sound_config.h"

+

+#include "jz_audio.h"

+#include "jz_codec.h"

+#include "jz4750_dlv.h"

+#include "jz_i2s_dbg.h"

+

+#define REPLAY		1

+#define RECORD		2

+

+#define POWER_ON	0

+#define POWER_OFF	1

+

+#define switch_SB_DAC(pwrstat)			\

+do {						\

+	dlv_write_reg_bit(5, pwrstat, 7);	\

+} while (0)					\

+

+#define switch_SB_OUT(pwrstat)			\

+do {						\

+	dlv_write_reg_bit(5, pwrstat, 6);	\

+} while (0)					\

+

+#define switch_SB_MIX(pwrstat)			\

+do {						\

+	dlv_write_reg_bit(5, pwrstat, 5);	\

+} while (0)					\

+

+#define switch_SB_ADC(pwrstat)			\

+do {						\

+	dlv_write_reg_bit(5, pwrstat, 4);	\

+} while (0)					\

+

+/*

+#define ENTER()			printk("Enter: %s, %s:%i\n", __FUNCTION__, __FILE__, __LINE__)

+#define LEAVE()			printk("Leave: %s, %s:%i\n", __FUNCTION__, __FILE__, __LINE__)

+*/

+

+#ifdef IOC_DEBUG

+static dlv_print_ioc_cmd(int cmd)

+{

+	char *dlv_ioc_cmd[] = {

+		"CODEC_SET_MODE",		"CODEC_CLEAR_MODE",		"CODEC_SET_GPIO_PIN",

+		"CODEC_EACH_TIME_INIT",		"CODEC_SET_STARTUP_PARAM",	"CODEC_SET_VOLUME_TABLE",

+		"CODEC_SET_RECORD",		"CODEC_SET_REPLAY",		"CODEC_SET_REPLAY_RECORD",

+		"CODEC_TURN_ON",		"CODEC_TURN_OFF",		"CODEC_SET_REPLAY_SPEED",

+		"CODEC_RESET",			"CODEC_GET_MIXER_OLD_INFO",	"CODEC_GET_MIXER_INFO",

+		"CODEC_SET_BASS",		"CODEC_SET_VOLUME",		"CODEC_SET_MIC",

+		"CODEC_SET_LINE",		"CODEC_I2S_RESUME",		"CODEC_I2S_SUSPEND",

+		"CODEC_PIN_INIT",		"CODEC_SET_SOME_FUNC",		"CODEC_CLEAR_RECORD",

+		"CODEC_CLEAR_REPLAY",		"CODEC_SET_REPLAY_HP_OR_SPKR",	"CODEC_SET_DIRECT_MODE",

+		"CODEC_CLEAR_DIRECT_MODE",	"CODEC_SET_LINEIN2HP",		"CODEC_CLEAR_LINEIN2HP",

+		"CODEC_ANTI_POP",		"CODEC_TURN_REPLAY",		"CODEC_SET_REPLAY_CHANNEL",

+		"CODEC_SET_REPLAY_FORMAT",	"CODEC_SET_RECORD_CHANNEL",	"CODEC_SET_RECORD_FORMAT",

+		"CODEC_SET_RECORD_SPEED",	"CODEC_DAC_MUTE"

+	};

+

+	if (cmd >= (sizeof(dlv_ioc_cmd) / sizeof(dlv_ioc_cmd[0]))) {

+		printk("%s: Unkown command !\n", __FUNCTION__);

+	} else {

+		printk("IOC CMD NAME = %s\n", dlv_ioc_cmd[cmd - 1]);

+	}

+}

+#endif

+

+#if 1

+/*

+ * CODEC registers access routines

+ */

+

+/**

+ * CODEC read register

+ *

+ * addr:        address of register

+ * return:      value of register

+ */

+static inline int dlv_read_reg(int addr)

+{

+        volatile int reg;

+        while (__icdc_rgwr_ready()) {

+                ;//nothing...

+        }

+        __icdc_set_addr(addr);

+        reg = __icdc_get_value();

+        reg = __icdc_get_value();

+        reg = __icdc_get_value();

+        reg = __icdc_get_value();

+        reg = __icdc_get_value();

+        return __icdc_get_value();

+}

+

+/**

+ * CODEC write register

+ *

+ * addr:        address of register

+ * val:         value to set

+ */

+void dlv_write_reg(int addr, int val)

+{

+        volatile int reg;

+        while (__icdc_rgwr_ready()) {

+                ;//nothing...

+        }

+        REG_ICDC_RGADW = ((addr << ICDC_RGADW_RGADDR_LSB) | val);

+        __icdc_set_rgwr();

+        reg = __icdc_rgwr_ready();

+        reg = __icdc_rgwr_ready();

+        reg = __icdc_rgwr_ready();

+        reg = __icdc_rgwr_ready();

+        reg = __icdc_rgwr_ready();

+        reg = __icdc_rgwr_ready();

+        while (__icdc_rgwr_ready()) {

+                ;//nothing...

+        }

+}

+

+/**

+ * CODEC write a bit of a register

+ *

+ * addr:        address of register

+ * bitval:      bit value to modifiy

+ * mask_bit:    indicate which bit will be modifiy

+ */

+static int dlv_write_reg_bit(int addr, int bitval, int mask_bit)

+{

+        int val = dlv_read_reg(addr);

+

+        if (bitval)

+                val |= (1 << mask_bit);

+        else

+                val &= ~(1 << mask_bit);

+        dlv_write_reg(addr, val);

+

+        return 1;

+}

+

+#else

+static inline int dlv_read_reg(int addr)

+{

+	while (__icdc_rgwr_ready()) {

+		;//nothing...

+	}

+	__icdc_set_addr(addr);

+	return __icdc_get_value();

+}

+

+void dlv_write_reg(int addr, int val)

+{

+#if 0

+	while (__icdc_rgwr_ready()) {

+		;//nothing...

+	}

+	REG_ICDC_RGADW = ((addr << ICDC_RGADW_RGADDR_LSB) | val);

+	__icdc_set_rgwr();

+	while (__icdc_rgwr_ready()) {

+		;//nothing...

+	}

+#else

+	volatile int reg;

+	while (__idc_rgwr_ready()) {

+		; // nothing

+	}

+	REG_ICDC_RGADW = ((addr << ICDC_RGADW_RGADDR_LSB) | val);

+	__icdc_set_rgwr();

+	reg = __icdc_rgwr_ready();

+	reg = __icdc_rgwr_ready();

+	reg = __icdc_rgwr_ready();

+	reg = __icdc_rgwr_ready();

+	reg = __icdc_rgwr_ready();

+	reg = __icdc_rgwr_ready();

+	while (__icdc_rgwr_ready()) {

+		; //nothing...

+	}

+#endif

+}

+

+static int dlv_write_reg_bit(int addr, int bitval, int mask_bit)

+{

+	int val;

+	while (__icdc_rgwr_ready()) {

+		;//nothing...

+	}

+	__icdc_set_addr(addr);

+	mdelay(1);

+	/* read */

+	val = __icdc_get_value();

+	while (__icdc_rgwr_ready()) {

+		;//nothing...

+	}

+

+	__icdc_set_addr(addr);

+	val &= ~(1 << mask_bit);

+	if (bitval == 1) {

+		val |= 1 << mask_bit;

+	}

+

+	__icdc_set_cmd(val); /* write */

+	mdelay(1);

+	__icdc_set_rgwr();

+	mdelay(1);

+

+	while (__icdc_rgwr_ready()) {

+		;//nothing...

+	}

+	__icdc_set_addr(addr);

+	val = __icdc_get_value(); /* read */	

+	

+	if (((val >> mask_bit) & bitval) == bitval) {

+		return 1;

+	} else {

+		return 0;

+	}

+}

+#endif

+

+/*

+ * DLV CODEC operations routines

+ */

+

+static void dlv_each_time_init(void)

+{

+	ENTER();

+	__i2s_disable();

+	__i2s_as_slave();

+#if AIC_BASE == 0xb0020000

+	__aic_internal_codec();

+#else

+	__aic0_external_codec();

+	__aic_internal_codec();

+#endif

+	//__i2s_set_oss_sample_size(16);

+	//__i2s_set_iss_sample_size(16);

+	LEAVE();

+}

+

+static void dlv_set_mode(void)

+{

+	ENTER();

+	/*REG_CPM_CPCCR &= ~(1 << 31);

+	  REG_CPM_CPCCR &= ~(1 << 30);*/

+	dlv_write_reg(0, 0xf);

+	dlv_write_reg(8, 0x2f);

+	dlv_write_reg(9, 0xff);

+	schedule_timeout(2);

+

+	dlv_write_reg_bit(6, 0, 1);//PMR2.SB->0

+	msleep(10);

+	dlv_write_reg_bit(6, 0, 0);//PMR2.SB->0

+	msleep(10);

+	DPRINT_CODEC("##### cleared codec reg6\n");

+	dlv_write_reg_bit(1, 0, 3);//PMR2.SB->0

+

+	dlv_write_reg_bit(5, 0, 4);//SB_ADC->1

+//	set_record_mic_input_audio_with_audio_data_replay();

+//	reset_dlv_codec();

+	LEAVE();

+}

+

+static void dlv_reset(void)

+{

+	int i = 0;

+	int reg = 0;

+	ENTER();

+	/* reset DLV codec. from hibernate mode to sleep mode */

+#if 0

+	for (i = 0; i < 27; i++) {

+		dlv_write_reg(i, 0x5a);

+	} 

+

+	for (i = 0; i < 27; i++) {

+		reg = dlv_read_reg(i);

+		if (reg != 0x5a)  {

+			printk("reg%d error: 0x%02x\n", i, reg);

+		}

+	}

+#endif

+	dlv_write_reg(0, 0xf);

+	dlv_write_reg_bit(6, 0, 0);

+	dlv_write_reg_bit(6, 0, 1);

+

+	//2010-01-31 Jason add

+	dlv_write_reg(22, 0x40);//mic 1

+

+	schedule_timeout(20);

+	//dlv_write_reg(0, 0xf);

+	dlv_write_reg_bit(5, 0, 7);//PMR1.SB_DAC->0

+	dlv_write_reg_bit(5, 0, 4);//PMR1.SB_ADC->0

+	schedule_timeout(2); ;//wait for stability

+	LEAVE();

+}

+

+static int dlv_set_startup_param(void)

+{

+	ENTER();

+	LEAVE();

+//	__i2s_disable_transmit_intr();

+//	__i2s_disable_receive_intr();

+	return 1;

+}

+

+//@@@@@@@@@@@@@@@@@@@@

+/* set Audio data replay */

+static void dlv_set_replay(void)

+{

+	ENTER();

+

+	//dump_dlv_regs("enter dlv_set_replay");

+	//printk("===>enter %s:%d, REG[0x9] = 0x%02x\n", __func__, __LINE__, dlv_read_reg(0x9));

+	//msleep(5000);

+

+	/* DAC path */

+	dlv_write_reg(9, 0xff);

+	//dlv_write_reg(8, 0x30);

+	//dlv_write_reg(8, 0x20);

+

+	schedule_timeout(2);

+	//printk("===>enter %s:%d\n", __func__, __LINE__);

+	//msleep(5000);

+	dlv_write_reg_bit(1, 0, 4);//CR1.HP_DIS->0

+	//printk("===>enter %s:%d\n", __func__, __LINE__);

+	//msleep(5000);

+

+	dlv_write_reg_bit(5, 1, 3);//PMR1.SB_LIN->1

+	//printk("===>enter %s:%d\n", __func__, __LINE__);

+	//msleep(5000);

+	dlv_write_reg_bit(5, 1, 0);//PMR1.SB_IND->1

+	//printk("===>enter %s:%d\n", __func__, __LINE__);

+	//msleep(5000);

+

+	//2010-01-31 Jason marked

+	dlv_write_reg_bit(1, 0, 2);//CR1.BYPASS->0

+	//printk("===>enter %s:%d\n", __func__, __LINE__);

+	//msleep(5000);

+	dlv_write_reg_bit(1, 1, 3);//CR1.DACSEL->1

+	//printk("===>enter %s:%d\n", __func__, __LINE__);

+	//msleep(5000);

+

+	dlv_write_reg_bit(1, 0, 5);//MUTE

+	//printk("===>enter %s:%d\n", __func__, __LINE__);

+	//msleep(5000);

+

+	dlv_write_reg_bit(5, 0, 5);//PMR1.SB_MIX->0

+	//printk("===>enter %s:%d\n", __func__, __LINE__);

+	//msleep(5000);

+	//mdelay(100);

+	//dlv_write_reg_bit(5, 0, 6);//PMR1.SB_OUT->0

+

+	//2010-01-31 Jason marked

+	//dlv_write_reg_bit(1, 1, 7);//CR1.SB_MICBIAS->1

+

+	//mdelay(300);

+	//dump_dlv_regs("leave dlv_set_replay");

+	LEAVE();

+}

+

+#if 0

+// @@@@@@@@@@@@@@@@@@@@@@@@

+/* set Record MIC input audio without playback */

+static void set_record_mic_input_audio_without_playback(void)

+{

+	ENTER();

+	// 2010-01-20 Jason added

+/*

+	dlv_write_reg_bit(6, 0, 0);//SB_SLEEP->0

+	dlv_write_reg_bit(6, 0, 1);//SB->0

+	dlv_write_reg_bit(5, 0, 4);//SB_ADC->0

+*/

+	/* ADC path for MIC IN */

+	dlv_write_reg(9, 0xff);

+	dlv_write_reg(8, 0x3f);

+	dlv_write_reg_bit(23, 0, 7);//AGC1.AGC_EN->0

+	schedule_timeout(2);

+	dlv_write_reg_bit(1, 1, 2);

+	//dlv_write_reg_bit(1, 1, 6);//CR1.MONO->1

+	

+	dlv_write_reg(22, 0x40);//mic 1

+	dlv_write_reg_bit(3, 1, 7);//CR1.HP_DIS->1

+	dlv_write_reg_bit(5, 1, 3);//PMR1.SB_LIN->1

+	dlv_write_reg_bit(5, 1, 0);//PMR1.SB_IND->1

+	

+	dlv_write_reg_bit(1, 0, 2);//CR1.BYPASS->0

+	dlv_write_reg_bit(1, 0, 3);//CR1.DACSEL->0

+	//dlv_write_reg_bit(6, 1, 3);// gain set

+

+	dlv_write_reg_bit(5, 0, 5);//PMR1.SB_MIX->0

+	schedule_timeout(10);

+	dlv_write_reg_bit(5, 0, 6);//PMR1.SB_OUT->0

+	dlv_write_reg(1, 0x4);

+

+	dlv_write_reg(19, (80 * 32 / 100) | ((80 * 32 / 100) << 4));

+

+	// 2010-01-19 Jason added

+

+	dlv_write_reg_bit(6, 0, 0);//SB_SLEEP->0

+	dlv_write_reg_bit(6, 0, 1);//SB->0

+	dlv_write_reg_bit(5, 0, 4);//SB_ADC->0

+

+	LEAVE();

+}

+

+/* unset Record MIC input audio without playback */

+static void unset_record_mic_input_audio_without_playback(void)

+{

+	ENTER();

+	/* ADC path for MIC IN */

+	// 2010-01-20 Jason modified

+//	dlv_write_reg_bit(5, 1, 4);//SB_ADC->1

+	dlv_write_reg_bit(1, 1, 7);//CR1.SB_MICBIAS->1

+	dlv_write_reg(22, 0xc0);//CR3.SB_MIC1

+	dlv_write_reg_bit(5, 1, 6);//PMR1.SB_OUT->1

+	dlv_write_reg_bit(1, 1, 5);//DAC_MUTE->1

+//	dlv_write_reg_bit(6, 1, 0);//SB_SLEEP->1

+//	dlv_write_reg_bit(6, 1, 1);//SB->1

+	LEAVE();

+}

+#endif

+

+#if 0

+/* set Record LINE input audio without playback */

+static void set_record_line_input_audio_without_playback(void)

+{

+	ENTER();

+	/* ADC path for LINE IN */	

+	dlv_write_reg(9, 0xff);

+	dlv_write_reg(8, 0x3f);

+	mdelay(10);

+	dlv_write_reg(22, 0xf6);//line in 1

+	dlv_write_reg_bit(23, 0, 7);//AGC1.AGC_EN->0

+	dlv_write_reg_bit(3, 1, 7);//CR1.HP_DIS->1

+	dlv_write_reg_bit(5, 0, 3);//PMR1.SB_LIN->0

+	dlv_write_reg_bit(5, 1, 0);//PMR1.SB_IND->1

+	

+	dlv_write_reg_bit(1, 0, 2);//CR1.BYPASS->0

+	dlv_write_reg_bit(1, 0, 3);//CR1.DACSEL->0

+	mdelay(10);

+	dlv_write_reg_bit(5, 0, 5);//PMR1.SB_MIX->0

+	mdelay(100);

+	dlv_write_reg_bit(5, 0, 6);//PMR1.SB_OUT->0

+	dlv_write_reg(1, 0x4);

+	LEAVE();

+}

+#endif

+

+#if 0

+/* unset Record LINE input audio without playback */

+static void unset_record_line_input_audio_without_playback(void)

+{

+	ENTER();

+	/* ADC path for LINE IN */

+	dlv_write_reg_bit(5, 1, 4);//SB_ADC->1

+	dlv_write_reg_bit(5, 1, 3);//ONR1.SB_LIN->1

+

+	dlv_write_reg(22, 0xc0);//CR3.SB_MIC1

+	dlv_write_reg_bit(5, 1, 6);//PMR1.SB_OUT->1

+	dlv_write_reg_bit(1, 1, 5);//DAC_MUTE->1

+	dlv_write_reg_bit(6, 1, 0);//SB_SLEEP->1

+	dlv_write_reg_bit(6, 1, 1);//SB->1

+	LEAVE();

+}

+#endif

+

+#if 0

+/* set Playback LINE input audio direct only */

+static void set_playback_line_input_audio_direct_only(void)

+{

+	ENTER();

+// need fix !!!

+//	jz_audio_reset();//or init_codec()

+	REG_AIC_I2SCR = 0x10;

+	dlv_write_reg(9, 0xff);

+	dlv_write_reg(8, 0x3f);

+	mdelay(10);

+	dlv_write_reg(22, 0xf6);//line in 1

+	dlv_write_reg_bit(23, 0, 7);//AGC1.AGC_EN->0

+	mdelay(10);

+	dlv_write_reg_bit(1, 1, 2);//CR1.HP_BYPASS->1

+	dlv_write_reg_bit(1, 0, 4);//CR1.HP_DIS->0

+	dlv_write_reg_bit(1, 0, 3);//CR1.DACSEL->0

+	dlv_write_reg_bit(5, 1, 0);//PMR1.SB_IND->1

+	dlv_write_reg_bit(5, 0, 3);//PMR1.SB_LIN->0

+

+	dlv_write_reg_bit(5, 0, 5);//PMR1.SB_MIX->0

+	mdelay(100);

+	dlv_write_reg_bit(5, 0, 6);//PMR1.SB_OUT->0

+	//dlv_write_reg_bit(5, 1, 7);//PMR1.SB_DAC->1

+	//dlv_write_reg_bit(5, 1, 4);//PMR1.SB_ADC->1

+	LEAVE();

+}

+#endif

+

+#if 0

+/* unset Playback LINE input audio direct only */

+static void unset_playback_line_input_audio_direct_only(void)

+{

+	ENTER();

+	dlv_write_reg_bit(6, 0, 3);//GIM->0

+	dlv_write_reg_bit(1, 0, 2);//PMR1.BYPASS->0

+	dlv_write_reg_bit(5, 1, 3);//PMR1.SB_LINE->1

+	dlv_write_reg_bit(5, 1, 6);//PMR1.SB_OUT->1

+	mdelay(100);

+	dlv_write_reg_bit(5, 1, 5);//PMR1.SB_MIX->1

+	dlv_write_reg_bit(6, 1, 0);//SB_SLEEP->1

+	dlv_write_reg_bit(6, 1, 1);//SB->1

+	LEAVE();

+}

+#endif

+

+#if 0

+/* set Record MIC input audio with direct playback */

+static void set_record_mic_input_audio_with_direct_playback(void)

+{

+	ENTER();

+	dlv_write_reg_bit(23, 0, 7);//AGC1.AGC_EN->0

+	dlv_write_reg(9, 0xff);

+	dlv_write_reg(8, 0x3f);

+	mdelay(10);

+	

+	dlv_write_reg(22, 0x60);//mic 1

+	dlv_write_reg_bit(23, 0, 7);//AGC1.AGC_EN->0

+	dlv_write_reg_bit(5, 1, 3);//PMR1.SB_LIN->1

+	dlv_write_reg_bit(5, 1, 0);//PMR1.SB_IND->1

+	dlv_write_reg_bit(1, 0, 7);//CR1.SB_MICBIAS->0

+	dlv_write_reg_bit(1, 0, 4);//CR1.HP_DIS->0

+	

+	dlv_write_reg_bit(1, 0, 2);//CR1.BYPASS->0

+	dlv_write_reg_bit(1, 0, 3);//CR1.DACSEL->0

+	dlv_write_reg_bit(6, 1, 3);// gain set

+	

+	dlv_write_reg_bit(5, 0, 5);//PMR1.SB_MIX->0

+	mdelay(100);

+	dlv_write_reg_bit(5, 0, 6);//PMR1.SB_OUT->0

+	//dlv_write_reg(1, 0x4);

+	LEAVE();

+}

+#endif

+

+#if 0

+/* unset Record MIC input audio with direct playback */

+static void unset_record_mic_input_audio_with_direct_playback(void)

+{

+	ENTER();

+	/* ADC path for MIC IN */

+	dlv_write_reg_bit(5, 1, 4);//SB_ADC->1

+	dlv_write_reg_bit(1, 1, 7);//CR1.SB_MICBIAS->1

+	dlv_write_reg(22, 0xc0);//CR3.SB_MIC1

+	dlv_write_reg_bit(5, 1, 6);//PMR1.SB_OUT->1

+	dlv_write_reg_bit(1, 1, 5);//DAC_MUTE->1

+	dlv_write_reg_bit(6, 1, 0);//SB_SLEEP->1

+	dlv_write_reg_bit(6, 1, 1);//SB->1

+	LEAVE();

+}

+#endif

+

+#if 0

+/* set Record playing audio mixed with MIC input audio */

+static void set_record_playing_audio_mixed_with_mic_input_audio(void)

+{

+	ENTER();

+	dlv_write_reg_bit(23, 0, 7);//AGC1.AGC_EN->0

+	dlv_write_reg(9, 0xff);

+	//dlv_write_reg(8, 0x30);

+	dlv_write_reg(8, 0x20);

+	

+	schedule_timeout(2);

+	dlv_write_reg(22, 0x63);//mic 1

+	

+	dlv_write_reg_bit(1, 0, 2);//CR1.BYPASS->0

+	dlv_write_reg_bit(6, 1, 3);// gain set

+

+	dlv_write_reg_bit(1, 0, 4);//CR1.HP_DIS->0	

+	dlv_write_reg_bit(5, 1, 3);//PMR1.SB_LIN->1

+	dlv_write_reg_bit(5, 1, 0);//PMR1.SB_IND->1

+	dlv_write_reg_bit(1, 0, 7);//CR1.SB_MICBIAS->0

+	dlv_write_reg_bit(22, 0, 7);//CR3.SB_MIC->0

+	dlv_write_reg_bit(1, 1, 3);//CR1.DACSEL->1

+	dlv_write_reg_bit(5, 0, 5);//PMR1.SB_MIX->0

+	dlv_write_reg_bit(5, 0, 4);//PMR1.SB_MIX->0

+	LEAVE();

+}

+#endif

+

+#if 0

+/* unset Record playing audio mixed with MIC input audio */

+static void unset_record_playing_audio_mixed_with_mic_input_audio(void)

+{

+	ENTER();

+	/* ADC path */

+	dlv_write_reg_bit(5, 1, 4);//SB_ADC->1

+	dlv_write_reg_bit(1, 1, 7);//CR1.SB_MICBIAS->1

+	//dlv_write_reg_bit(1, 1, 6);//CR1.MONO->1

+	dlv_write_reg(22, 0xc0);//CR3.SB_MIC1->1

+	//dlv_write_reg_bit(1, 1, 5);//DAC_MUTE->1

+	//dlv_write_reg_bit(5, 1, 6);//SB_OUT->1

+//	dlv_write_reg_bit(5, 1, 7);//SB_DAC->1

+	dlv_write_reg_bit(5, 1, 5);//SB_MIX->1

+	dlv_write_reg_bit(6, 1, 0);//SB_SLEEP->1

+	dlv_write_reg_bit(6, 1, 1);//SB->1

+	LEAVE();

+}

+#endif

+

+

+//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@

+/* set Record MIC input audio with Audio data replay (full duplex) */

+static void set_record_mic_input_audio_with_audio_data_replay(void)

+{

+	ENTER();

+	printk("when run here ?????\n");

+	dlv_write_reg_bit(23, 0, 7);//AGC1.AGC_EN->0

+	dlv_write_reg(9, 0xff);

+	//dlv_write_reg(8, 0x30);

+	dlv_write_reg(8, 0x20);

+	dlv_write_reg_bit(1, 0, 4);//CR1.HP_DIS->0	

+	dlv_write_reg_bit(5, 1, 3);//PMR1.SB_LIN->1

+	dlv_write_reg_bit(5, 1, 0);//PMR1.SB_IND->1

+

+	dlv_write_reg_bit(22, 0, 7);//CR3.SB_MIC->0

+

+	dlv_write_reg_bit(1, 0, 7);//CR1.SB_MICBIAS->0

+

+	dlv_write_reg_bit(1, 1, 3);//CR1.DACSEL->1

+	dlv_write_reg_bit(5, 0, 5);//PMR1.SB_MIX->0

+	LEAVE();

+}

+

+/* unset Record MIC input audio with Audio data replay (full duplex) */

+static void unset_record_mic_input_audio_with_audio_data_replay(void)

+{

+	ENTER();

+	/* ADC path */

+	printk("@@@ %s", __FUNCTION__);

+	dlv_write_reg_bit(5, 1, 4);//SB_ADC->1

+	dlv_write_reg_bit(1, 1, 7);//CR1.SB_MICBIAS->1

+	//dlv_write_reg_bit(1, 1, 6);//CR1.MONO->1

+	dlv_write_reg(22, 0xc0);//CR3.SB_MIC1->1

+//	dlv_write_reg_bit(5, 1, 7);//SB_DAC->1

+	dlv_write_reg_bit(5, 1, 5);//SB_MIX->1

+

+	// 2009-01-20 Jason marked

+//	dlv_write_reg_bit(6, 1, 0);//SB_SLEEP->1

+//	dlv_write_reg_bit(6, 1, 1);//SB->1

+	LEAVE();

+}

+

+//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@

+/* set Record LINE input audio with Audio data replay (full duplex for linein) */

+static void set_record_line_input_audio_with_audio_data_replay(void)

+{

+	ENTER();

+	dlv_write_reg(9, 0xff);

+	//dlv_write_reg(8, 0x30);

+	dlv_write_reg(8, 0x20);

+	dlv_write_reg_bit(1, 0, 4);//CR1.HP_DIS->0	

+	dlv_write_reg_bit(5, 0, 3);//PMR1.SB_LIN->0

+	dlv_write_reg_bit(5, 1, 0);//PMR1.SB_IND->1

+	dlv_write_reg_bit(1, 1, 7);//CR1.SB_MICBIAS->1

+	//dlv_write_reg_bit(22, 1, 7);//CR3.SB_MIC->1

+	dlv_write_reg_bit(1, 1, 3);//CR1.DACSEL->1

+	dlv_write_reg_bit(5, 0, 5);//PMR1.SB_MIX->0

+

+	dlv_write_reg(22, 0xc6);//line in 1

+	dlv_write_reg_bit(23, 0, 7);//AGC1.AGC_EN->0

+	dlv_write_reg_bit(1, 0, 2);//CR1.BYPASS->0

+	dlv_write_reg_bit(5, 0, 5);//PMR1.SB_MIX->0

+	LEAVE();

+}

+

+//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@

+/* unset Record LINE input audio with Audio data replay (full duplex for linein) */

+static void unset_record_line_input_audio_with_audio_data_replay(void)

+{

+	ENTER();

+	/* ADC path */

+	printk("@@@ %s", __FUNCTION__);

+

+	dlv_write_reg_bit(5, 1, 4);//SB_ADC->1

+	dlv_write_reg_bit(1, 1, 7);//CR1.SB_MICBIAS->1

+	//dlv_write_reg_bit(1, 1, 6);//CR1.MONO->1

+	dlv_write_reg(22, 0xc0);//CR3.SB_MIC1->1

+//	dlv_write_reg_bit(5, 1, 7);//SB_DAC->1

+	dlv_write_reg_bit(5, 1, 5);//SB_MIX->1

+

+	// 2010-01-20 Jason masked

+//	dlv_write_reg_bit(6, 1, 0);//SB_SLEEP->1

+//	dlv_write_reg_bit(6, 1, 1);//SB->1

+	LEAVE();

+}

+

+#if 0

+/* unset Audio data replay */

+static void unset_audio_data_replay(void)

+{

+	ENTER();

+	//dlv_write_reg_bit(1, 1, 5);//DAC_MUTE->1

+	//mdelay(800);

+	//dlv_write_reg_bit(5, 1, 6);//SB_OUT->1

+	//mdelay(800);

+//	dlv_write_reg_bit(5, 1, 7);//SB_DAC->1

+	dlv_write_reg_bit(5, 1, 4);//SB_MIX->1

+	dlv_write_reg_bit(6, 1, 0);//SB_SLEEP->1

+	dlv_write_reg_bit(6, 1, 1);//SB->1

+	LEAVE();

+}

+#endif

+

+static int dlv_set_replay_speed(int rate)

+{

+	int speed = 0, val;

+#define MAX_RATE_COUNT 11

+	int mrate[MAX_RATE_COUNT] = { 

+		96000, 48000, 44100, 32000,

+		24000, 22050, 16000, 12000,

+		11025, 9600 , 8000};

+

+	for (val = 0; val < MAX_RATE_COUNT; val++) {

+		if (rate >= mrate[val]) {

+			speed = val;

+			break;

+		}

+	}

+	if (rate < mrate[MAX_RATE_COUNT - 1]) {

+		speed = MAX_RATE_COUNT - 1;

+	}

+	val = dlv_read_reg(4);

+	val &= 0xf;

+	val = (speed << 4) | val;

+	dlv_write_reg(4, val);	

+	return mrate[speed];

+}

+

+static int dlv_set_record_speed(int rate)

+{

+	int speed = 0, val;

+#define MAX_RATE_COUNT 11

+	int mrate[MAX_RATE_COUNT] = { 

+		96000, 48000, 44100, 32000,

+		24000, 22050, 16000, 12000,

+		11025, 9600 , 8000};

+	for (val = 0; val < MAX_RATE_COUNT; val++) {

+		if (rate >= mrate[val]) {

+			speed = val;

+			break;

+		}

+	}

+	if (rate < mrate[MAX_RATE_COUNT - 1]) {

+		speed = MAX_RATE_COUNT - 1;

+	}

+	val = dlv_read_reg(4);

+	val &= 0xf0;

+	val = (speed) | val;

+	dlv_write_reg(4, val);	

+	return mrate[speed];	

+}

+

+static void dlv_get_mixer_old_info(mixer_info *info)

+{

+	strncpy(info->id, "JZDLV", sizeof(info->id));

+	strncpy(info->name, "Jz internal codec dlv on jz4750", sizeof(info->name));

+}

+

+static void dlv_get_mixer_info(mixer_info *old_info)

+{

+	strncpy(old_info->id, "JZDLV", sizeof(old_info->id));

+	strncpy(old_info->name, "Jz internal codec dlv on jz4750", sizeof(old_info->name));

+}

+

+static void dlv_set_mic(int val)

+{

+	int cur_vol;

+

+	ENTER();

+

+	/* set gain */

+	dlv_write_reg_bit(6, 1, 3);//GIM

+	cur_vol = 31 * val / 100;

+	cur_vol |= cur_vol << 4;

+	dlv_write_reg(19, cur_vol);//GIL,GIR

+

+	LEAVE();

+}

+

+static void dlv_set_line(int val)

+{

+	int cur_vol;

+

+	ENTER();

+	/* set gain */

+	cur_vol = 31 * val / 100;

+	cur_vol &= 0x1f;

+	dlv_write_reg(11, cur_vol);//GO1L

+	dlv_write_reg(12, cur_vol);//GO1R

+

+	LEAVE();

+}

+

+static void dlv_set_volume(int val)

+{

+	unsigned long cur_vol;

+

+	ENTER();

+

+	/* To protect circut and to avoid shutting down CODEC,

+	 * valume must less then 60% of the max

+	 */

+	if (val > 60) {

+		val = 60;

+	}

+	cur_vol = 31 * (100 - val) / 100;

+

+	dlv_write_reg(17, cur_vol | 0x80);

+

+	DPRINT_CODEC("$$$$$ val = %d, REG_17 = 0x%02x, REG_18 = 0x%02x\n",

+		     val, dlv_read_reg(17), dlv_read_reg(18));

+

+	LEAVE();

+}

+

+/*

+ * Base on set_record_mic_input_audio_without_playback()

+ */

+static void dlv_set_record(void)

+{

+	ENTER();

+

+	//dump_dlv_regs("enter dlv_set_record");

+

+	/* ADC path for MIC IN */

+	dlv_write_reg(9, 0xff);

+	dlv_write_reg(8, 0x2f);

+	dlv_write_reg_bit(23, 0, 7);//AGC1.AGC_EN->0

+	schedule_timeout(2);

+	dlv_write_reg_bit(1, 1, 2);

+	//dlv_write_reg_bit(1, 1, 6);//CR1.MONO->1

+	

+	dlv_write_reg(22, 0x40);//mic 1

+	dlv_write_reg_bit(3, 1, 7);//CR1.HP_DIS->1

+	dlv_write_reg_bit(5, 1, 3);//PMR1.SB_LIN->1

+	dlv_write_reg_bit(5, 1, 0);//PMR1.SB_IND->1

+

+	dlv_write_reg_bit(1, 0, 2);//CR1.BYPASS->0

+

+	//2010-02-01 Jason marked

+	//dlv_write_reg_bit(1, 0, 3);//CR1.DACSEL->0

+

+	// 2010-01-31 Jason added

+	//dlv_write_reg_bit(1, 0, 7);

+	

+	dlv_write_reg_bit(5, 0, 5);//PMR1.SB_MIX->0

+	schedule_timeout(10);

+	dlv_write_reg_bit(5, 0, 6);//PMR1.SB_OUT->0

+	dlv_write_reg(1, 0x8);

+

+	//2010-02-01 Jason masked

+	//dlv_write_reg(19, (80 * 32 / 100) | ((80 * 32 / 100) << 4));

+

+	// 2010-01-19 Jason added

+	dlv_write_reg_bit(6, 0, 0);//SB_SLEEP->0

+	dlv_write_reg_bit(6, 0, 1);//SB->0

+	dlv_write_reg_bit(5, 0, 4);//SB_ADC->0

+

+	//dump_dlv_regs("leave dlv_set_record");

+

+	LEAVE();

+}

+

+static void dlv_set_replay_recode(int val)

+{

+	ENTER();

+	if (val == USE_LINEIN) {

+		/* Record LINE input audio with Audio data replay (full duplex for linein) */

+		/* codec_test_line */

+		printk("use line in ???\n");

+		set_record_line_input_audio_with_audio_data_replay();

+	}

+	if (val == USE_MIC) {

+		/* Record MIC input audio with Audio data replay (full duplex) */

+		/* codec_test_mic */

+		set_record_mic_input_audio_with_audio_data_replay();

+	}

+	LEAVE();

+}

+

+static void dlv_anti_pop(int mode)

+{

+	switch(mode) {

+	case CODEC_WRMODE:

+		//set SB_ADC or SB_DAC

+		dlv_write_reg_bit(5, 0, 6);//PMR1.SB_OUT->0

+

+		//2010-01-31 Jason add

+		dlv_write_reg(22, 0x40);//mic 1

+

+		//2010-01-31 Jason add

+		//dlv_write_reg(1, 0x04);

+

+		schedule_timeout(28); //280 ms 

+		break;

+	case CODEC_RMODE:

+		// 2010-01-31 Jason marked

+		//dlv_write_reg_bit(5, 1, 7);//SB_DAC->1

+

+		//2010-01-31 Jason add

+		dlv_write_reg(22, 0x40);//mic 1

+

+		break;

+	case CODEC_WMODE:

+		printk("===>dlv_anti_pop!!!\n");

+		dlv_write_reg_bit(6, 0, 2);     //codec_reg_clear(A_CODEC_PMR2, SB_MC);

+		mdelay(5);

+		dlv_write_reg_bit(6, 0, 1);     //codec_reg_clear(A_CODEC_PMR2, SB);

+		mdelay(30);

+		dlv_write_reg_bit(6, 0, 0);     //codec_reg_clear(A_CODEC_PMR2, SB_SLEEP);

+		mdelay(1);

+		dlv_write_reg_bit(5, 0, 7);     //codec_reg_clear(A_CODEC_PMR1, SB_DAC);

+		mdelay(1);

+		dlv_write_reg_bit(5, 0, 6);     //codec_reg_clear(A_CODEC_PMR1, SB_OUT);

+		mdelay(1);

+		dlv_write_reg_bit(5, 0, 5);     //codec_reg_clear(A_CODEC_PMR1, SB_MIX);

+		

+		msleep(350);

+		break;

+	}

+}

+

+static void dlv_turn_replay(int mode)

+{

+	ENTER();

+	if (mode == USE_LINEIN) {

+		unset_record_line_input_audio_with_audio_data_replay();

+	}

+	if (mode == USE_MIC) {

+		unset_record_mic_input_audio_with_audio_data_replay();

+	}

+	LEAVE();

+}

+

+static void dlv_turn_off(int mode)

+{

+	ENTER();

+

+	if ((mode & REPLAY) && (mode & RECORD)) {

+		printk("Close DLV !!!\n");

+		dlv_write_reg_bit(1, 1, 5);//DAC_MUTE->1

+		schedule_timeout(20);

+

+		// 2010-01-31 Jason marked

+		//dlv_write_reg_bit(5, 1, 6);//SB_OUT->1

+

+		dlv_write_reg(9, 0xff);

+		dlv_write_reg(8, 0x2f);

+	} else if (mode & REPLAY) {

+		//nothing

+	} else if (mode & RECORD) {

+		printk("Close RECORD\n");

+		dlv_write_reg(4, 0x20);

+	}

+

+	LEAVE();

+}

+

+static int dlv_set_channel(int ch)

+{

+	if(ch > 2) ch = 2;

+	if(ch < 1) ch = 1;

+	switch (ch) {

+	case 1:

+		dlv_write_reg_bit(1, 1, 6);//CR1.MONO->1 for Mono

+		break;

+	case 2:

+		dlv_write_reg_bit(1, 0, 6);//CR1.MONO->0 for Stereo

+		break;

+	}

+	return ch;

+}

+

+static int dlv_set_data_width(unsigned int mode, unsigned int width)

+{

+	unsigned char cr2 = dlv_read_reg(2);

+	unsigned char savecr2 = cr2;

+	int supported_width[4] = {16, 18, 20, 24};

+	int i;

+

+	for (i = 0; i < (sizeof(supported_width) / sizeof(supported_width[0])); i++) {

+		if (supported_width[i] <= width) {

+			break;

+		}

+	}

+

+	if (i == (sizeof(supported_width) / sizeof(supported_width[0]))) {

+		// For 8 bit width mode, handle it as 16 bit

+		if (width == 8) {

+			i = 0;

+		} else {

+			return -1;

+		}

+	}

+

+	//printk("mode = %d, width = %d, selected %d\n", mode, width, i);

+

+	switch (mode) {

+	case RECORD:

+		cr2 &= ~(3 << 3);

+		cr2 |= (i << 3);

+		break;

+	case REPLAY:

+		cr2 &= ~(3 << 5);

+		cr2 |= (i << 5);

+		break;

+	}

+

+	if (cr2 != savecr2) {

+		dlv_write_reg(2, cr2);

+	}

+

+	//printk("set cr2 = %x, %x\n", cr2, savecr2);

+

+	if (width == 8) {

+		return 8;

+	} else {

+		return supported_width[i];

+	}

+}

+

+static int dlv_mute(int val)

+{

+	return dlv_write_reg_bit(1, val ? 1 : 0, 5);

+}

+static void dlv_suspend(void)

+{    

+	printk("suspend\n");

+	dlv_write_reg_bit(5, 1, 6);     //codec_reg_set(A_CODEC_PMR1, SB_OUT);

+	mdelay(40);

+	dlv_write_reg_bit(6, 1, 1);     //codec_reg_set(A_CODEC_PMR2, SB);

+	dlv_write_reg_bit(6, 1, 0);     //codec_reg_set(A_CODEC_PMR2, SB_SLEEP);

+	mdelay(30);

+	dlv_write_reg_bit(5, 1, 5);     //codec_reg_set(A_CODEC_PMR1, SB_MIX);

+	dlv_write_reg_bit(5, 1, 7);     //codec_reg_set(A_CODEC_PMR1, SB_DAC);

+	dlv_write_reg_bit(5, 1, 4);     //codec_reg_set(A_CODEC_PMR1, SB_ADC);

+}

+

+static void dlv_resume(void)

+{     

+	dlv_write_reg_bit(6, 0, 2);     //codec_reg_clear(A_CODEC_PMR2, SB_MC);

+	mdelay(5);

+	dlv_write_reg_bit(6, 0, 1);     //codec_reg_clear(A_CODEC_PMR2, SB);

+	mdelay(30);

+	dlv_write_reg_bit(6, 0, 0);     //codec_reg_clear(A_CODEC_PMR2, SB_SLEEP);

+	mdelay(1);

+	dlv_write_reg_bit(5, 0, 7);     //codec_reg_clear(A_CODEC_PMR1, SB_DAC);	p380

+	mdelay(1);

+	dlv_write_reg_bit(5, 0, 6);     //codec_reg_clear(A_CODEC_PMR1, SB_OUT);

+	mdelay(1);

+	dlv_write_reg_bit(5, 0, 5);     //codec_reg_clear(A_CODEC_PMR1, SB_MIX);

+	msleep(350);

+ }

+

+

+void dump_dlv_regs(const char * str)

+{

+	unsigned int i;

+	unsigned char dat;

+	printk("codec register, %s:\n", str);

+	for (i = 0; i < 27; i++) {

+		dat = dlv_read_reg(i);

+		printk("addr = %2d data = 0x%02x\n", i, dat);

+	}

+}

+

+static int jzdlv_ioctl(void *context, unsigned int cmd, unsigned long arg)

+{

+	ENTER();

+	DUMP_CODEC_REGS(__FUNCTION__);

+	DPRINT_CODEC("[dlv IOCTL]++++++++++++++++++++++++++++\n");

+	DPRINT_CODEC("%s  cmd = %d, arg = %lu\n", __FUNCTION__, cmd, arg);

+	DPRINT_DLV_IOC_CMD(cmd);

+	DPRINT_CODEC("[dlv IOCTL]----------------------------\n");

+

+	switch (cmd) {

+	case CODEC_SET_MODE:

+		dlv_set_mode();

+		break;

+

+	case CODEC_SET_STARTUP_PARAM:

+		dlv_set_startup_param();

+		break;

+

+	case CODEC_SET_REPLAY:

+		dlv_set_replay();

+		break;

+

+	case CODEC_SET_RECORD:

+		dlv_set_record();

+		break;

+

+	case CODEC_SET_REPLAY_RECORD:

+		dlv_set_replay_recode(arg);

+		break;

+

+	case CODEC_SET_VOLUME:

+		dlv_set_volume(arg);

+		break;

+

+	case CODEC_SET_MIC:

+		dlv_set_mic(arg);

+		break;

+

+	case CODEC_SET_LINE:

+		dlv_set_line(arg);

+		break;

+

+	case CODEC_EACH_TIME_INIT:

+		dlv_each_time_init();

+		break;

+

+	case CODEC_RESET:

+		dlv_reset();

+		break;

+

+	case CODEC_ANTI_POP:

+		dlv_anti_pop(arg);

+		break;

+

+	case CODEC_TURN_REPLAY:

+		dlv_turn_replay(arg);

+		break;

+

+	case CODEC_TURN_OFF:

+		dlv_turn_off(arg);

+		break;

+

+	case CODEC_GET_MIXER_INFO:

+		dlv_get_mixer_info((mixer_info *)arg);

+		break;

+

+	case CODEC_GET_MIXER_OLD_INFO:

+		dlv_get_mixer_old_info((mixer_info *)arg);

+		break;

+

+	case CODEC_SET_REPLAY_SPEED:

+		return dlv_set_replay_speed(arg);

+

+	case CODEC_SET_RECORD_SPEED:

+		return dlv_set_record_speed(arg);

+

+	case CODEC_SET_RECORD_CHANNEL:

+		return arg;

+

+	case CODEC_SET_REPLAY_CHANNEL:

+		return dlv_set_channel(arg);

+

+	case CODEC_SET_RECORD_DATA_WIDTH:

+		return dlv_set_data_width(RECORD, arg);

+

+	case CODEC_SET_REPLAY_DATA_WIDTH:

+		return dlv_set_data_width(REPLAY, arg);

+

+	case CODEC_DAC_MUTE:

+		return dlv_mute(arg);

+

+	case CODEC_I2S_SUSPEND:

+		dlv_suspend();

+		break;

+	case CODEC_I2S_RESUME:

+		dlv_resume();

+		break;

+

+	default:

+		printk("%s:%d no support\n", __FUNCTION__, __LINE__);

+		return -1;

+	}

+

+	LEAVE();

+	return 0;

+}

+

+static struct work_struct dlv_work;

+

+/*

+ * work handler

+ *

+ * Mission:

+ *	Restart CODEC after shut down by short circurt protection

+ */

+static void dlv_work_handle(struct work_struct *work)

+{

+	printk("CODEC: short circurt detected!\n");

+

+	/* Renable SB OUT */

+	switch_SB_OUT(POWER_OFF);

+	mdelay(300);

+	while ((dlv_read_reg(9) & 0x4) != 0x4) {

+		;/* nothing */

+	}

+	while ((dlv_read_reg(9) & 0x10) == 0x10) {

+		dlv_write_reg(9, 0x10);

+	}

+	switch_SB_OUT(POWER_ON);

+	mdelay(300);

+	while ((dlv_read_reg(9) & 0x8) != 0x8) {

+		;/* nothing */

+	}

+

+	/* Enable CCMC interrupt ... clear bit 4*/

+	dlv_write_reg(8, 0x2f);

+}

+

+static spinlock_t dlv_irq_lock;

+

+static irqreturn_t dlv_codec_irq(int irq, void *dev_id)

+{

+	unsigned char reg_9;

+

+	spin_lock(dlv_irq_lock);

+

+	/* Clear interrupt flag */

+	reg_9 = dlv_read_reg(9);

+	dlv_write_reg(9, reg_9);

+

+	/* Mask CCMC temporarily */

+	dlv_write_reg(8, 0x3f);

+

+	REG_AIC_SR = 0x78; //???

+

+	/* Start work when output short circuit has been detected */

+	if ((reg_9 & 0x10) == 0x10) {

+		schedule_work(&dlv_work);

+	}

+

+/*

+	reg_9 = dlv_read_reg(9);

+	reg_8 = dlv_read_reg(8);

+	printk("reg_8 = %x, reg_9 = %x\n", reg_8, reg_9);

+*/

+	spin_unlock(dlv_irq_lock);

+	return IRQ_HANDLED;

+}

+

+static int __init init_dlv(void)

+{

+	int retval;

+

+	spin_lock_init(&dlv_irq_lock);

+	INIT_WORK(&dlv_work, dlv_work_handle);

+	register_jz_codecs((void *)jzdlv_ioctl);

+	dlv_reset();

+

+	retval = request_irq(IRQ_AIC, dlv_codec_irq, IRQF_DISABLED, "dlv_codec_irq", NULL);

+	if (retval) {

+		printk("Could not get aic codec irq %d\n", IRQ_AIC);

+		return retval;

+	}

+

+	return 0;

+}

+

+static void __exit cleanup_dlv(void)

+{

+	free_irq(IRQ_AIC, NULL);

+}

+

+module_init(init_dlv);

+module_exit(cleanup_dlv);

diff --git a/sound/oss/jztest_i2s.c b/sound/oss/jztest_i2s.c
new file mode 100644
index 00000000000..07448ef8f12
--- /dev/null
+++ b/sound/oss/jztest_i2s.c
@@ -0,0 +1,3188 @@
+/*
+ * Linux/sound/oss/jz_i2s.c
+ *
+ * Sound driver for Ingenic Jz4750 MIPS processor
+ *
+ * 2009-12-xx	Steven <dsqiu@ingenic.cn>
+ * 2010-01-xx	Jason <xwang@ingenic.cn>
+ *
+ * Copyright (c) Ingenic Semiconductor Co., Ltd.
+ */
+
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/pm.h>
+#include <linux/sched.h>
+#include <linux/delay.h>
+#include <linux/sound.h>
+#include <linux/slab.h>
+#include <sound/core.h>
+#include <sound/initval.h>
+#include <linux/proc_fs.h>
+#include <linux/soundcard.h>
+#include <linux/dma-mapping.h>
+#include <linux/mutex.h>
+#include <linux/mm.h>
+#include <asm/hardirq.h>
+#include <asm/jzsoc.h>
+#include "sound_config.h"
+
+#include <linux/miscdevice.h>
+#include <linux/platform_device.h>
+//#include <linux/msm_audio.h>
+#include "jz_codec.h"
+#include "jz_i2s_dbg.h"
+
+//#if defined CONFIG_PM
+//#undef CONFIG_PM
+//#endif
+
+#define DMA_ID_I2S_TX			DMA_ID_AIC_TX
+#define DMA_ID_I2S_RX			DMA_ID_AIC_RX
+
+// reference to dma.c
+#define DMA_TX_CHAN			6
+#define DMA_RX_CHAN			7
+
+#define NR_I2S				2
+
+#define JZCODEC_RW_BUFFER_SIZE		1
+#define JZCODEC_RW_BUFFER_TOTAL		4
+
+#define AUDIOBUF_STATE_FREE		0
+
+#define NOMAL_STOP			0
+#define FORCE_STOP			1
+#define PIPE_TRANS			1
+
+#define AUDIO_LOCK(lock, flags)		spin_lock_irqsave(&lock, flags)
+#define AUDIO_UNLOCK(lock, flags)	spin_unlock_irqrestore(&lock, flags)
+
+#define THIS_AUDIO_NODE(p)		list_entry(p, audio_node, list)
+#define ALIGN_PAGE_SIZE(x)		(((x) + PAGE_SIZE) / PAGE_SIZE * PAGE_SIZE)
+
+typedef struct {
+	struct list_head list;
+	unsigned int pBuf;
+#ifdef Q_DEBUG
+	unsigned int pBufID;
+#endif
+	unsigned int start;
+	unsigned int end;
+	unsigned int phyaddr;
+} audio_node;
+
+typedef struct {
+	unsigned int fact;
+	unsigned int datasize;
+	unsigned int listsize;
+	struct list_head free;
+	struct list_head use;
+} audio_head;
+
+typedef struct
+{
+	int ch;
+	int onetrans_bit;
+	int rw;
+	unsigned int *trans_addr;
+	unsigned int *trans_count;
+	unsigned int *trans_mode;
+	unsigned int *data_addr;
+} audio_dma_type;
+
+typedef struct __audio_pipe
+{
+	spinlock_t	lock;
+	audio_dma_type	dma;
+	unsigned int	*mem;
+	audio_node	*savenode;
+
+	int	fragsize;
+	int 	fragstotal;
+	int	is_non_block;
+	volatile int	trans_state;
+
+	wait_queue_head_t	q_full;
+	int			avialable_couter;
+
+#ifdef WORK_QUEUE_MODE
+	struct work_struct	work;
+#endif
+	void (*handle)(struct __audio_pipe *endpoint);
+	int (*filter)(void *buff, int cnt);
+} audio_pipe;
+
+struct i2s_codec
+{
+	/* I2S controller connected with */
+	void	*private_data;
+	char	*name;
+	int	id;
+	int	dev_mixer;
+
+	int	use_mic_line_flag;
+	int	audio_volume;
+	int	mic_gain;
+	int	bass_gain;
+
+	unsigned short	record_audio_rate;
+	unsigned short	replay_audio_rate;
+
+	short	replay_codec_channel;
+	short	record_codec_channel;
+
+	short	replay_format;
+	short	record_format;
+
+	int	audiomute;
+	int	user_need_mono;
+
+	struct semaphore i2s_sem;
+	int (*codecs_ioctrl)(void *context, unsigned int cmd, unsigned long arg);
+};
+
+struct jz_i2s_controller_info
+{
+	char		*name;
+	audio_pipe	*pout_endpoint;
+	audio_pipe	*pin_endpoint;
+	int		dev_audio;
+	unsigned int	error;	/* over / underrun */
+
+	struct i2s_codec *i2s_codec;
+
+#ifdef CONFIG_PM
+	struct pm_dev	*pm;
+#endif
+};
+
+
+/*
+ * Global variates
+ */
+static audio_pipe out_endpoint = {
+	.mem		= 0,
+	.savenode	= 0,
+	.fragsize	= 0,
+	.fragstotal	= 0,
+	.trans_state	= 0,
+};
+
+static audio_pipe in_endpoint= {
+	.mem		= 0,
+	.savenode	= 0,
+	.fragsize	= 0,
+	.fragstotal	= 0,
+	.trans_state	= 0,
+};
+
+static struct i2s_codec the_codecs[NR_I2S];
+static struct jz_i2s_controller_info *the_i2s_controller = NULL;
+static int audio_mix_modcnt = 0;
+static audio_node *last_read_node = NULL;
+static int g_play_first = 0;
+
+#ifdef CONFIG_JZ_EBOOK_HARD
+int audio_device_open = 0;
+volatile int audio_device_pm_state = 0;
+#endif
+
+/*
+ * Debug functions
+ */
+#ifdef DMA_DEBUG
+void dump_dma(unsigned int dmanr, const char *str)
+{
+	printk("DMA%d Registers, %s:\n", dmanr, str);
+	printk("\tDMACR	= 0x%08x\n", REG_DMAC_DMACR(dmanr/HALF_DMA_NUM));
+	printk("\tDSAR	= 0x%08x\n", REG_DMAC_DSAR(dmanr));
+	printk("\tDTAR	= 0x%08x\n", REG_DMAC_DTAR(dmanr));
+	printk("\tDTCR	= 0x%08x\n", REG_DMAC_DTCR(dmanr));
+
+	*(unsigned int *)0xb342010c = 0x18;
+
+	printk("\tDRSR	= 0x%08x, addr = 0x%08x\n", REG_DMAC_DRSR(dmanr), DMAC_DRSR(dmanr));
+	printk("\tDCCSR	= 0x%08x\n", REG_DMAC_DCCSR(dmanr));
+	printk("\tDCMD	= 0x%08x\n", REG_DMAC_DCMD(dmanr));
+	printk("\tDDA	= 0x%08x\n", REG_DMAC_DDA(dmanr));
+	printk("\tDMADBR= 0x%08x\n", REG_DMAC_DMADBR(dmanr/HALF_DMA_NUM));
+	printk("\tCPCCR = 0x%08x\n", REG_CPM_CPCCR);
+	printk("\tCPPCR = 0x%08x\n", REG_CPM_CPPCR0);
+	printk("\tREG_CPM_CLKGR0 = 0x%08x\n", REG_CPM_CLKGR0);
+	printk("\tREG_CPM_CLKGR1 = 0x%08x\n", REG_CPM_CLKGR1);
+}
+#endif
+
+#ifdef IOC_DEBUG
+void dsp_print_ioc_cmd(int cmd)
+{
+	int i;
+	int cmd_arr[] = {
+		OSS_GETVERSION,		SNDCTL_DSP_RESET,	SNDCTL_DSP_SYNC,
+		SNDCTL_DSP_SPEED,	SNDCTL_DSP_STEREO,	SNDCTL_DSP_GETBLKSIZE,
+		SNDCTL_DSP_GETFMTS,	SNDCTL_DSP_SETFMT,	SNDCTL_DSP_CHANNELS,
+		SNDCTL_DSP_POST,	SNDCTL_DSP_SUBDIVIDE,	SNDCTL_DSP_SETFRAGMENT,
+		SNDCTL_DSP_GETCAPS,	SNDCTL_DSP_NONBLOCK,	SNDCTL_DSP_SETDUPLEX,
+		SNDCTL_DSP_GETOSPACE,	SNDCTL_DSP_GETISPACE,	SNDCTL_DSP_GETTRIGGER,
+		SNDCTL_DSP_SETTRIGGER,	SNDCTL_DSP_GETIPTR,	SNDCTL_DSP_GETOPTR,
+		SNDCTL_DSP_GETODELAY,	SOUND_PCM_READ_RATE,	SOUND_PCM_READ_CHANNELS,
+		SOUND_PCM_READ_BITS,	SNDCTL_DSP_MAPINBUF,	SNDCTL_DSP_MAPOUTBUF,
+		SNDCTL_DSP_SETSYNCRO,	SOUND_PCM_READ_FILTER,	SOUND_PCM_WRITE_FILTER,
+//		AUDIO_GET_CONFIG,	AUDIO_SET_CONFIG
+	};
+	char *cmd_str[] = {
+		"OSS_GETVERSION",	"SNDCTL_DSP_RESET",	"SNDCTL_DSP_SYNC",
+		"SNDCTL_DSP_SPEED",	"SNDCTL_DSP_STEREO",	"SNDCTL_DSP_GETBLKSIZE",
+		"SNDCTL_DSP_GETFMTS",	"SNDCTL_DSP_SETFMT",	"SNDCTL_DSP_CHANNELS",
+		"SNDCTL_DSP_POST",	"SNDCTL_DSP_SUBDIVIDE",	"SNDCTL_DSP_SETFRAGMENT",
+		"SNDCTL_DSP_GETCAPS",	"SNDCTL_DSP_NONBLOCK",	"SNDCTL_DSP_SETDUPLEX",
+		"SNDCTL_DSP_GETOSPACE",	"SNDCTL_DSP_GETISPACE",	"SNDCTL_DSP_GETTRIGGER",
+		"SNDCTL_DSP_SETTRIGGER","SNDCTL_DSP_GETIPTR",	"SNDCTL_DSP_GETOPTR",
+		"SNDCTL_DSP_GETODELAY",	"SOUND_PCM_READ_RATE",	"SOUND_PCM_READ_CHANNELS",
+		"SOUND_PCM_READ_BITS",	"SNDCTL_DSP_MAPINBUF",	"SNDCTL_DSP_MAPOUTBUF",
+		"SNDCTL_DSP_SETSYNCRO",	"SOUND_PCM_READ_FILTER","SOUND_PCM_WRITE_FILTER",
+//		"AUDIO_GET_CONFIG",	"AUDIO_SET_CONFIG"
+	};
+
+	for ( i = 0; i < sizeof(cmd_arr) / sizeof(int); i++) {
+		if (cmd_arr[i] == cmd) {
+			printk("Command name : %s\n", cmd_str[i]);
+			return;
+		}
+	}
+
+	if (i == sizeof(cmd_arr) / sizeof(int)) {
+		printk("Unknown command\n");
+	}
+}
+
+void mixer_print_ioc_cmd(int cmd)
+{
+	int i;
+	int cmd_arr[] = {
+		SOUND_MIXER_INFO,	SOUND_OLD_MIXER_INFO,		SOUND_MIXER_READ_STEREODEVS,
+		SOUND_MIXER_READ_CAPS,	SOUND_MIXER_READ_DEVMASK,	SOUND_MIXER_READ_RECMASK,
+		SOUND_MIXER_READ_RECSRC,SOUND_MIXER_WRITE_SPEAKER,	SOUND_MIXER_WRITE_BASS,
+		SOUND_MIXER_READ_BASS,	SOUND_MIXER_WRITE_VOLUME,	SOUND_MIXER_READ_VOLUME,
+		SOUND_MIXER_WRITE_MIC,	SOUND_MIXER_READ_MIC,		SOUND_MIXER_WRITE_LINE,
+		SOUND_MIXER_READ_LINE,	SOUND_MIXER_WRITE_MUTE,		SOUND_MIXER_READ_MUTE,
+//		SND_SET_DEVICE,		SND_SET_VOLUME,
+//		SND_GET_NUM_ENDPOINTS,	SND_GET_ENDPOINT
+	};
+
+	char *cmd_str[] = {
+		"SOUND_MIXER_INFO",		"SOUND_OLD_MIXER_INFO",		"SOUND_MIXER_READ_STEREODEVS",
+		"SOUND_MIXER_READ_CAPS",	"SOUND_MIXER_READ_DEVMASK",	"SOUND_MIXER_READ_RECMASK",
+		"SOUND_MIXER_READ_RECSRC",	"SOUND_MIXER_WRITE_SPEAKER",	"SOUND_MIXER_WRITE_BASS",
+		"SOUND_MIXER_READ_BASS",	"SOUND_MIXER_WRITE_VOLUME",	"SOUND_MIXER_READ_VOLUME",
+		"SOUND_MIXER_WRITE_MIC",	"SOUND_MIXER_READ_MIC",		"SOUND_MIXER_WRITE_LINE",
+		"SOUND_MIXER_READ_LINE",	"SOUND_MIXER_WRITE_MUTE",	"SOUND_MIXER_READ_MUTE",
+//		"SND_SET_DEVICE",		"SND_SET_VOLUME",
+//		"SND_GET_NUM_ENDPOINTS",	"SND_GET_ENDPOINT"
+	};
+
+	for (i = 0; i < sizeof(cmd_arr) / sizeof(int); i++) {
+		if (cmd_arr[i] == cmd) {
+			printk("Command name : %s\n", cmd_str[i]);
+			return;
+		}
+	}
+
+	printk("Unknown command\n");
+}
+#endif
+
+//#ifdef REG_DEBUG
+void dump_aic_regs(const char *str)
+{
+	char *regname[] = {"aicfr","aiccr","aiccr1","aiccr2","i2scr","aicsr","acsr","i2ssr",
+			   "accar", "accdr", "acsar", "acsdr", "i2sdiv", "aicdr"};
+	int i;
+	unsigned int addr;
+
+	printk("AIC regs dump, %s\n", str);
+	for (i = 0; i <= 0x34; i += 4) {
+		addr = AIC_BASE + i;
+		printk("%s\t0x%08x -> 0x%08x\n", regname[i/4], addr, *(unsigned int *)addr);
+	}
+}
+//#endif
+
+#ifdef BUF_DEBUG
+void dump_buf(char *buf, int dump_len, int bytes_in_line)
+{
+	int i;
+	printk("Buffer 0x%p:\n", buf);
+	for (i = 0; i < dump_len; i++) {
+		printk("%02x ", (unsigned char)buf[i]);
+		if ((i+1) % bytes_in_line == 0) {
+			printk("\n");
+		}
+	}
+	printk("\n");
+}
+#endif
+
+#ifdef Q_DEBUG
+void dump_node(audio_node *node, const char *str)
+{
+	if (!node || !str) {
+		printk("DUMP_NODE: detected argument is NULL\n");
+		return;
+	}
+
+	printk("%s: addr(0x%08x) id=%d, pBuf=0x%08x, start=0x%08x, end=0x%08x, phyaddr=0x%08x\n",
+	       str, (unsigned int)node, node->pBufID, node->pBuf, node->start, node->end, node->phyaddr);
+}
+
+void dump_list(audio_head *head)
+{
+	audio_node *tmp;
+	struct list_head *p, *n;
+
+	BUG_ON(!head);
+
+	printk("--------\nAudio head info: fact = %d, datasize = %d, listsize = %d\n",
+	       head->fact, head->datasize, head->listsize);
+
+	printk("free q:\n");
+	list_for_each_safe(p, n, &head->free) {
+		tmp = list_entry(p, audio_node, list);
+		DUMP_NODE(tmp, "fQ");
+	}
+	printk("use q:\n");
+	list_for_each_safe(p, n, &head->use) {
+		tmp = list_entry(p, audio_node, list);
+		DUMP_NODE(tmp, "uQ");
+	}
+	printk("--------\n");
+}
+#endif
+
+//----------------------------------------------------------------
+// audio node operater
+// int init_audio_node(unsigned int **memory, unsigned int pagesize, unsigned int count)
+// void deinit_audio_node(unsigned int **memory)
+// static inline audio_node *get_audio_freenode(unsigned int *mem)
+// static inline void put_audio_usenode(unsigned int *mem, audio_node *node)
+// static inline audio_node *get_audio_usenode(unsigned int *mem)
+// static inline void put_audio_freenode(unsigned int *mem, audio_node *node)
+// static inline int get_audio_freenodecount(unsigned int *mem)
+//
+//----------------------------------------------------------------
+
+void deinit_audio_node(unsigned int **memory)
+{
+	audio_head	*phead;
+	unsigned int	fact;
+
+	phead = (audio_head *)*memory;
+	fact = phead->fact;
+	free_pages((unsigned long)*memory, fact);
+	*memory = NULL;
+}
+
+int init_audio_node(unsigned int **memory, unsigned int pagesize, unsigned int count)
+{
+	unsigned int	fact;
+	audio_node	*pbuff;
+	audio_head	*phead;
+	unsigned int	*mem;
+	struct list_head *audio_wfree;
+	struct list_head *audio_wuse;
+	int	memsize;
+	int	datasize;
+	int	headlistsize;
+	int	i;
+
+	ENTER();
+
+	// Alloc memory first, to avail fail
+	datasize	= ALIGN_PAGE_SIZE(pagesize * count);
+	headlistsize	= ALIGN_PAGE_SIZE(count * sizeof(audio_node) + sizeof(audio_head));
+	memsize		= headlistsize + datasize;
+	fact		= get_order(memsize);
+
+	mem = (unsigned int *)__get_free_pages(GFP_KERNEL | GFP_DMA, fact);
+	if (mem == NULL) {
+		printk("JZ I2S: Memory allocation failed in function init_audio_node!\n");
+		return 0;
+	}
+
+	DPRINT("Mem alloc finish! memsize = %x, fact = %d, mem = 0x%08x\n",
+	       memsize, fact, (unsigned int)mem);
+
+	// Free old buffer
+	if (*memory) {
+		phead	= (audio_head *)*memory;
+		fact	= phead->fact;
+		free_pages((unsigned long)*memory, fact);
+		*memory	= NULL;
+	}
+	*memory = mem;
+
+/*
+	datasize	= ALIGN_PAGE_SIZE(pagesize * count);
+	headlistsize	= ALIGN_PAGE_SIZE(count * sizeof(audio_node) + sizeof(audio_head)); //8byte is save head data
+	memsize		= headlistsize + datasize;
+
+	fact = get_order(memsize);
+*/
+
+	// Update list head
+	phead		= (audio_head *)*memory;
+	phead->fact	= fact;
+	phead->listsize	= headlistsize;
+	phead->datasize	= datasize;
+
+	audio_wuse	= &(phead->use);
+	audio_wfree	= &(phead->free);
+	INIT_LIST_HEAD(audio_wuse);
+	INIT_LIST_HEAD(audio_wfree);
+
+	pbuff = (audio_node *)((unsigned int)*memory + sizeof(audio_head));
+	for (i = 0; i < count; i++) {
+		pbuff->pBuf	= (unsigned int)*memory + headlistsize + pagesize * i;
+		pbuff->phyaddr	= (unsigned int)virt_to_phys((void *)pbuff->pBuf);
+		pbuff->start	= 0;
+		pbuff->end	= 0;
+#ifdef Q_DEBUG
+		pbuff->pBufID	= i;
+#endif
+		DPRINT_Q("audio_note buffer[%d] = %x\n", i, (unsigned int)pbuff->pBuf);
+		list_add(&pbuff->list, audio_wfree);
+		pbuff++;
+	}
+
+	DUMP_LIST(phead);
+
+	LEAVE();
+	return 1;
+}
+
+#define is_null_free_audio_node(mem)				\
+({								\
+	audio_head *phead = (audio_head *)(mem);		\
+	struct list_head *pfree = &(phead->pfree);		\
+	(pfree->next == pfree);					\
+})
+
+#define is_null_use_audio_node(mem)				\
+({								\
+	audio_head *phead = (audio_head *)mem;			\
+	struct list_head *puse = &(phead->use);			\
+	(puse->next == puse);					\
+})
+
+//static unsigned int putid = 0, getid = 0;
+
+static inline audio_node *get_audio_freenode(unsigned int *mem)
+{
+	audio_head	 *phead;
+	audio_node	 *node = NULL;
+	struct list_head *pfree;
+	struct list_head *curnode;
+
+	phead	= (audio_head *)mem;
+	pfree	= &(phead->free);
+	curnode	= pfree->next;
+
+	if (curnode != pfree) {
+		node = THIS_AUDIO_NODE(curnode);
+		node->start = 0;
+		node->end = 0;
+		list_del(curnode);
+	}
+	return node;
+}
+
+static inline void put_audio_usenode(unsigned int *mem, audio_node *node)
+{
+	audio_head *phead = (audio_head *)mem;
+	struct list_head *puse = &(phead->use);
+	struct list_head *curnode = &(node->list);
+
+	list_add_tail(curnode, puse);
+}
+
+static inline audio_node *get_audio_usenode(unsigned int *mem)
+{
+	audio_head	 *phead;
+	audio_node	 *node = NULL;
+	struct list_head *curnode;
+	struct list_head *puse;
+
+	phead	= (audio_head *)mem;
+	puse	=  &(phead->use);
+	curnode	= puse->next;
+
+	if (curnode != puse) {
+		node = THIS_AUDIO_NODE(curnode);
+		list_del(curnode);
+	}
+	return node;
+}
+
+static inline void put_audio_freenode(unsigned int *mem, audio_node *node)
+{
+	audio_head *phead = (audio_head *)mem;
+	struct list_head *pfree = &(phead->free);
+	struct list_head *curnode = &(node->list);
+
+	list_add_tail(curnode, pfree);
+}
+
+static inline int get_audio_freenodecount(unsigned int *mem)
+{
+	struct list_head *pfree;
+	struct list_head *plist;
+	audio_head *phead;
+	int count = 0;
+
+	phead = (audio_head *)mem;
+	pfree =  &(phead->free);
+	plist = pfree;
+	while (plist->next != pfree) {
+		count++;
+		plist = plist->next;
+	}
+	return count;
+}
+
+#if 1
+static struct timer_list debug_timer;
+static int dbg_timer_should_stop = 0;
+
+static void debug_func(unsigned long arg) {
+	dump_dlv_regs(__func__);	
+	dump_aic_regs(__func__);
+	dump_jz_dma_channel(6);
+	dump_jz_dma_channel(6);
+
+	if (!dbg_timer_should_stop) {
+		debug_timer.expires = jiffies + HZ;
+		add_timer(&debug_timer);
+	}
+}
+
+static void start_debug_timer() {
+	static audio_timer_inited = 0;
+
+	if (!audio_timer_inited) {
+		init_timer(&debug_timer);		
+		debug_timer.function = debug_func;
+		debug_timer.data = 0x0;
+	}
+
+	debug_timer.expires = jiffies + HZ;
+
+	dbg_timer_should_stop = 0;
+	add_timer(&debug_timer);
+}
+
+static void stop_debug_timer() {
+	dbg_timer_should_stop = 1;
+	del_timer_sync(&debug_timer);
+}
+#endif
+
+//--------------------------------------------------------------------
+// end audio node operater
+//--------------------------------------------------------------------
+
+//--------------------------------------------------------------------
+// static irqreturn_t jz_i2s_dma_irq (int irq, void *dev_id)
+// int init_audio_recorddma(audio_pipe *endpoint)
+// int init_audio_replaydma(audio_pipe *endpoint)
+// int init_audio_audiodma(audio_pipe *endpoint, int mode)
+// void config_dma_trans_mode(spinlock_t lock, audio_dma_type* dma, int mode)
+// static inline int audio_trystart_dma_node(audio_dma_type* dma, audio_node *node)
+// static inline int audio_trystart_dma_node(audio_dma_type* dma, audio_node *node)
+// static inline void audio_stop_dma_node(audio_dma_type* dma)
+
+static irqreturn_t jz_i2s_dma_irq (int irq, void *dev_id)
+{
+	audio_pipe * endpoint = (audio_pipe *) dev_id;
+	int dma_chan = endpoint->dma.ch;
+	int dma_state = REG_DMAC_DCCSR(dma_chan);
+	int err = 0;
+
+	ENTER();
+
+	//printk("===>enter %s:%d\n", __func__, __LINE__);
+	stop_debug_timer();
+
+	REG_DMAC_DCCSR(dma_chan) = 0;
+
+	DPRINT_IRQ("!!!! endpoint direct = %s \n",(endpoint == &out_endpoint) ? "out" : "in");
+
+	if (dma_state & DMAC_DCCSR_HLT) {
+		err = 0;
+		DPRINT_IRQ("!!!! DMA HALT\n");
+	}
+	if (dma_state & DMAC_DCCSR_AR) {
+		err = 1;
+		DPRINT_IRQ("!!!! DMA ADDR ERROR\n");
+	}
+	if (dma_state & DMAC_DCCSR_CT) {
+		DPRINT_IRQ("!!!! DMA descriptor finish\n");
+	}
+	/*
+	if (dma_state & DMA_DCCSR_TT) {
+
+	}
+	*/
+	if (err == 0) {
+		//printk("schedule_work++++ %x %x\n", endpoint,&(endpoint->work));
+		//schedule_work(&(endpoint->work));
+		//printk("schedule_work----\n");
+		endpoint->handle(endpoint);
+	} else {
+		DPRINT_IRQ("!!!! ??? unknown !!!\n");
+	}
+
+	LEAVE();
+
+	return IRQ_HANDLED;
+}
+
+static int jz_request_aic_dma(int dev_id, const char *dev_str,
+			      irqreturn_t (*irqhandler)(int, void *),
+			      unsigned long irqflags, void *irq_dev_id)
+{
+	struct jz_dma_chan *chan;
+	int i, ret;
+
+	if (dev_id == DMA_ID_AIC_TX) {
+		i = DMA_TX_CHAN;
+		if (jz_dma_table[i].dev_id != DMA_ID_AIC_TX) {
+			BUG_ON(1);
+		}
+	} else if (dev_id == DMA_ID_AIC_RX) {
+		i = DMA_RX_CHAN;
+		if (jz_dma_table[i].dev_id != DMA_ID_AIC_RX) {
+			BUG_ON(1);
+		}
+	} else {
+		BUG_ON(1);
+	}
+
+	/* we got channel */
+	chan = &jz_dma_table[i];
+
+	if (irqhandler) {
+		chan->irq = IRQ_DMA_0 + i;
+		chan->irq_dev = irq_dev_id;
+		if ((ret = request_irq(chan->irq, irqhandler, irqflags,
+				       dev_str, chan->irq_dev))) {
+			chan->irq = -1;
+			chan->irq_dev = NULL;
+			return ret;
+		}
+	} else {
+		chan->irq = -1;
+		chan->irq_dev = NULL;
+	}
+/*
+	printk("\n@@@@ %s:%d chan index = %d, chan.irq = %d\n\n",
+	       __FUNCTION__, __LINE__, i, chan->irq);
+*/
+	chan->io	= i;
+	chan->dev_id	= dev_id;
+	chan->dev_str	= dev_str;
+	chan->fifo_addr	= CPHYSADDR(AIC_DR);
+
+	switch (dev_id) {
+	case DMA_ID_AIC_TX:
+		chan->mode	= DMA_AIC_TX_CMD_UNPACK | DMA_MODE_WRITE;
+		chan->source	= DMAC_DRSR_RS_AICOUT;
+		break;
+	case DMA_ID_AIC_RX:
+		chan->mode	= DMA_32BIT_RX_CMD | DMA_MODE_READ;
+		chan->source	= DMAC_DRSR_RS_AICIN;
+		break;
+	default:
+		printk("JZ AIC: %s:%d, need fix !!!\n", __FUNCTION__, __LINE__);
+		BUG_ON(1);
+	}
+
+	// Open AIC_TX and AIC_RX
+#ifdef CONFIG_SOC_JZ4760B
+	REG_DMAC_DMACKS(1) = 1 << (DMA_RX_CHAN - HALF_DMA_NUM) | 1 << (DMA_TX_CHAN - HALF_DMA_NUM);
+#else
+	REG_DMAC_DMACKE(1) = 1 << (DMA_RX_CHAN - HALF_DMA_NUM) | 1 << (DMA_TX_CHAN - HALF_DMA_NUM);
+#endif
+	return i;
+}
+
+static int init_audio_recorddma(audio_pipe *endpoint)
+{
+	int ch = 0;
+
+	ENTER();
+	if ((ch = jz_request_aic_dma(DMA_ID_I2S_RX, "audio adc", jz_i2s_dma_irq, IRQF_DISABLED, endpoint)) < 0) {
+		printk(KERN_ERR "%s: can't reqeust DMA DAC channel.\n", __FUNCTION__);
+		return -1;
+	}
+	REG_DMAC_DMACR(ch / HALF_DMA_NUM) |= 1;
+	REG_DMAC_DCMD(ch) =  DMAC_DCMD_DAI | DMAC_DCMD_SWDH_32 | DMAC_DCMD_TIE;
+	REG_DMAC_DRSR(ch) =  DMAC_DRSR_RS_AICIN;
+	REG_DMAC_DSAR(ch) =  (unsigned int)CPHYSADDR(AIC_DR);
+
+	endpoint->dma.ch = ch;
+	endpoint->dma.trans_addr = (unsigned int *)DMAC_DTAR(ch);
+	endpoint->dma.trans_count = (unsigned int *)DMAC_DTCR(ch);
+	endpoint->dma.trans_mode = (unsigned int *)DMAC_DCMD(ch);
+	endpoint->dma.data_addr = (unsigned int *)DMAC_DSAR(ch);
+
+	endpoint->dma.rw = 0;
+
+	LEAVE();
+	return ch;
+}
+
+static int init_audio_replaydma(audio_pipe *endpoint)
+{
+	int ch = 0;
+	if ((ch = jz_request_aic_dma(DMA_ID_I2S_TX,"audio dac", jz_i2s_dma_irq, IRQF_DISABLED, endpoint)) < 0) {
+		printk(KERN_ERR "%s: can't reqeust DMA DAC channel.\n", __FUNCTION__);
+		return -1;
+	}
+
+	REG_DMAC_DMACR(ch / HALF_DMA_NUM) |= 1;
+	REG_DMAC_DCMD(ch) =  DMAC_DCMD_SAI | DMAC_DCMD_DWDH_32 | DMAC_DCMD_TIE;
+
+	//printk("$$$$ before set --- REG_DMAC_DRSR(ch) = 0x%08x\n", REG_DMAC_DRSR(ch));
+	REG_DMAC_DRSR(ch) =  DMAC_DRSR_RS_AICOUT;
+
+	//printk("$$$$ ch = %d, DMAC_DRSR = 0x%08x, set 0x%08x, after set -- 0x%08x\n",
+	//       ch, DMAC_DRSR(ch), DMAC_DRSR_RS_AICOUT, REG_DMAC_DRSR(ch));
+
+	*(unsigned int *)0xb342010c = 0x18;
+
+	//printk("$$$$ after force set --- REG_DMAC_DRSR(ch) = 0x%08x\n", REG_DMAC_DRSR(ch));
+
+	REG_DMAC_DTAR(ch) =  (unsigned int)CPHYSADDR(AIC_DR);
+
+	endpoint->dma.ch = ch;
+	endpoint->dma.trans_addr = (unsigned int *)DMAC_DSAR(ch);
+	endpoint->dma.trans_count = (unsigned int *)DMAC_DTCR(ch);
+	endpoint->dma.trans_mode = (unsigned int *)DMAC_DCMD(ch);
+	endpoint->dma.data_addr = (unsigned int *)DMAC_DTAR(ch);
+	endpoint->dma.rw = 1;
+	return ch;
+}
+
+static int init_audio_audiodma(audio_pipe *endpoint, int mode)
+{
+	if (mode == CODEC_RMODE) {
+		return init_audio_recorddma(endpoint);
+	}
+
+	if (mode == CODEC_WMODE) {
+		return init_audio_replaydma(endpoint);
+	}
+
+	return -1;
+}
+
+static void config_dma_trans_mode(spinlock_t lock, audio_dma_type* dma, int sound_data_width)
+{
+	unsigned int	curmode;
+	unsigned long	flags;
+
+	ENTER();
+	AUDIO_LOCK(lock, flags);
+	curmode = *dma->trans_mode;
+
+	if (dma->rw) {
+		curmode &= ~(DMAC_DCMD_DWDH_MASK | DMAC_DCMD_DS_MASK);
+		switch(sound_data_width) {
+		case 8:
+			*dma->trans_mode = (curmode | DMAC_DCMD_DWDH_8 | DMAC_DCMD_DS_16BYTE);
+			dma->onetrans_bit = 16 * 8;
+			break;
+		case 16:
+			*dma->trans_mode = (curmode | DMAC_DCMD_DWDH_16 | DMAC_DCMD_DS_16BYTE);
+			dma->onetrans_bit = 16 * 8;
+			break;
+		case 17 ... 32:
+			*dma->trans_mode = (curmode | DMAC_DCMD_DWDH_32 | DMAC_DCMD_DS_32BYTE);
+			dma->onetrans_bit = 32 * 8;
+			break;
+		default:
+			printk("JZ I2S: Unkown DMA mode(sound data width) %d\n", sound_data_width);
+			break;
+		}
+	} else {
+		curmode &= ~(DMAC_DCMD_SWDH_MASK | DMAC_DCMD_DS_MASK);
+		switch(sound_data_width) {
+		case 8:
+			*dma->trans_mode = (curmode | DMAC_DCMD_SWDH_8 | DMAC_DCMD_DS_16BYTE);
+			dma->onetrans_bit = 16 * 8;
+			break;
+		case 16:
+			*dma->trans_mode = (curmode | DMAC_DCMD_SWDH_16 | DMAC_DCMD_DS_16BYTE);
+			dma->onetrans_bit = 16 * 8;
+			break;
+		case 17 ... 32:
+			*dma->trans_mode = (curmode | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DS_32BYTE);
+			dma->onetrans_bit = 32 * 8;
+			break;
+		default:
+			printk("JZ I2S: Unkown DMA mode(sound data width) %d\n", sound_data_width);
+			break;
+		}
+	}
+
+	AUDIO_UNLOCK(lock, flags);
+	DUMP_DMA(dma->ch, __FUNCTION__);
+	DPRINT_DMA("dma_trans = %d\n", dma->onetrans_bit);
+	LEAVE();
+}
+
+#define aic_enable_transmit()					\
+do {								\
+	int dat = REG_AIC_CR;					\
+	dat |= (AIC_CR_TDMS | AIC_CR_ERPL);			\
+	REG_AIC_CR = dat;					\
+} while (0)
+
+#define aic_disable_transmit()					\
+do {								\
+	int dat = REG_AIC_CR;					\
+	dat &= ~(AIC_CR_TDMS | AIC_CR_ERPL);			\
+	REG_AIC_CR = dat;					\
+} while (0)
+
+static inline int audio_trystart_dma_node(audio_dma_type* dma, audio_node *node)
+{
+	int start = 0;
+
+	ENTER();
+	//printk("===>enter %s:%d\n", __func__, __LINE__);
+
+	if ((REG_DMAC_DCCSR(dma->ch) & DMAC_DCCSR_EN) == 0) {
+		int count = node->end - node->start;
+		*(dma->trans_addr) = node->phyaddr;
+		*(dma->data_addr) =  (unsigned int)CPHYSADDR(AIC_DR);
+		*(dma->trans_count) = count * 8 / dma->onetrans_bit;
+		REG_DMAC_DCCSR(dma->ch) = DMAC_DCCSR_NDES | DMAC_DCCSR_EN;
+		//printk("virt = 0x%08x phy = 0x%08x, dma->onetrans_bit = 0x%x\n",
+			   //node->pBuf, node->phyaddr, dma->onetrans_bit);
+
+		DUMP_CODEC_REGS(__FUNCTION__);
+		DUMP_AIC_REGS(__FUNCTION__);
+		start = 1;
+		start_debug_timer();
+	}
+
+	DUMP_DMA(dma->ch, "audio_trystart_dma_node -----------");
+
+	LEAVE();
+	return start;
+}
+
+static inline void audio_stop_dma_node(audio_dma_type* dma)
+{
+	REG_DMAC_DCCSR(dma->ch) = 0;
+}
+
+/* Never be used, fix me ???
+static inline int recalculate_fifowidth(short channels, short fmt)
+{
+	int bit = 16;
+
+	if (fmt <= 8) {
+		bit = 8;
+	} else if (fmt > 16) {
+		bit = 32;
+	} else {
+		bit = 16;
+	}
+
+	return 	bit *= channels;
+}
+*/
+#define I2S_FIFO_DEPTH 32
+
+static inline void set_controller_triger(struct jz_i2s_controller_info *controller,
+					 audio_pipe *endpoint, short channels, short format)
+{
+	int sound_data_width = 0;
+
+	ENTER();
+
+//	printk("%%%% format = %d\n", format);
+
+	switch (format) {
+	case AFMT_U8:
+	case AFMT_S8:
+		sound_data_width = 8;
+		break;
+	case AFMT_S16_LE:
+	case AFMT_S16_BE:
+		sound_data_width = 16;
+		break;
+	default:
+		printk("JZ I2S: Unkown sound format %d\n", format);
+		return ;
+	}
+
+	config_dma_trans_mode(endpoint->lock,&(endpoint->dma), sound_data_width);
+	if (endpoint == &out_endpoint) {
+		if ((I2S_FIFO_DEPTH - endpoint->dma.onetrans_bit / sound_data_width) >= 30) {
+			__i2s_set_transmit_trigger(14);
+		} else {
+			__i2s_set_transmit_trigger((I2S_FIFO_DEPTH - endpoint->dma.onetrans_bit / sound_data_width) / 2);
+		}
+	}
+	if (endpoint == &in_endpoint) {
+		__i2s_set_receive_trigger((endpoint->dma.onetrans_bit / sound_data_width) / 2);
+	}
+
+	LEAVE();
+}
+
+//-------------------------------------------------------------------
+/*
+  int trystart_endpoint_out(audio_pipe *endpoint, audio_node *node);
+  int trystart_endpoint_in(audio_pipe *endpoint, audio_node *node);
+  note: this two function isn't protected;
+ */
+static inline int trystart_endpoint_out(struct jz_i2s_controller_info *controller, audio_node *node)
+{
+	audio_pipe *endpoint = controller->pout_endpoint;
+	int start = 0;
+
+	ENTER();
+
+	start = audio_trystart_dma_node(&(endpoint->dma), node);
+	if (start) {
+		endpoint->trans_state |= PIPE_TRANS;
+		endpoint->savenode = node;
+		aic_enable_transmit();
+		DUMP_AIC_REGS(__FUNCTION__);
+		DUMP_CODEC_REGS(__FUNCTION__);
+	}
+
+	LEAVE();
+	return start;
+}
+
+static inline int trystart_endpoint_in(struct jz_i2s_controller_info *controller, audio_node *node)
+{
+	audio_pipe *endpoint = controller->pin_endpoint;
+	int start = 0;
+
+	ENTER();
+	dma_cache_wback_inv((unsigned long)node->pBuf, endpoint->fragsize);
+	start = audio_trystart_dma_node(&(endpoint->dma), node);
+	if (start) {
+		endpoint->trans_state |= PIPE_TRANS;
+		endpoint->savenode = node;
+		__i2s_enable_receive_dma();
+		__i2s_enable_record();
+		DUMP_AIC_REGS(__FUNCTION__);
+		DUMP_CODEC_REGS(__FUNCTION__);
+	}
+	LEAVE();
+	return start;
+}
+
+int audio_get_endpoint_freesize(audio_pipe *endpoint, audio_buf_info *info)
+{
+	int count;
+	unsigned long flags;
+
+	AUDIO_LOCK(endpoint->lock, flags);
+	count = get_audio_freenodecount(endpoint->mem);
+	AUDIO_UNLOCK(endpoint->lock, flags);
+	info->fragments = count;
+	info->fragstotal = endpoint->fragstotal;
+	info->fragsize = endpoint->fragsize;
+	info->bytes = count * endpoint->fragsize;
+	return info->bytes;
+}
+
+void audio_clear_endpoint(audio_pipe *endpoint)
+{
+	audio_node *pusenode;
+	unsigned long flags;
+
+	ENTER();
+	AUDIO_LOCK(endpoint->lock, flags);
+	while (!is_null_use_audio_node(endpoint->mem)) {
+		pusenode = get_audio_usenode(endpoint->mem);
+		if (pusenode) {
+			put_audio_freenode(endpoint->mem, pusenode);
+		}
+	}
+	AUDIO_UNLOCK(endpoint->lock, flags);
+	LEAVE();
+}
+
+void audio_sync_endpoint(audio_pipe *endpoint)
+{
+	int isnull = 1;
+	unsigned long flags;
+
+	ENTER();
+
+	do {
+		AUDIO_LOCK(endpoint->lock, flags);
+		isnull = is_null_use_audio_node(endpoint->mem);
+		AUDIO_UNLOCK(endpoint->lock, flags);
+		if (!isnull) {
+			//printk("&&&& audio_sync_endpoint\n");
+			schedule_timeout(1);
+		}
+	} while (!isnull);
+
+	LEAVE();
+}
+
+void audio_close_endpoint(audio_pipe *endpoint, int mode)
+{
+	int is_use_list_null = 1, trans = 0;
+	unsigned long flags;
+
+	ENTER();
+
+	AUDIO_LOCK(endpoint->lock, flags);
+	is_use_list_null = is_null_use_audio_node(endpoint->mem);
+	trans = endpoint->trans_state & PIPE_TRANS;
+	AUDIO_UNLOCK(endpoint->lock, flags);
+
+	if (is_use_list_null) {
+		// Wait savenode trans complete
+		while (trans) {
+			AUDIO_LOCK(endpoint->lock, flags);
+			trans = endpoint->trans_state & PIPE_TRANS;
+			AUDIO_UNLOCK(endpoint->lock, flags);
+			DPRINT("waiting savenode\n");
+			if (trans) {
+				schedule_timeout(10);
+			}
+		}
+
+		/* In replay mode, savenode must been put into free list after trans completed,
+		 * so we don't care it in this condition.
+		 * But in record mode, savenode must been put into use list after trans completed,
+		 * so we have to ignore the incomming data and move it to free list forcely.
+		 */
+		if (endpoint == &out_endpoint) {
+			goto _L_AUDIO_CLOSE_EP_RET;
+		}
+	}
+
+	// NOMAL_STOP routine of replay mode
+	if (mode == NOMAL_STOP) {
+		BUG_ON(endpoint != &out_endpoint);
+
+		// Wait use list free
+		audio_sync_endpoint(endpoint);
+		// wait savenode trans finish
+		while (trans) {
+			AUDIO_LOCK(endpoint->lock, flags);
+			trans = endpoint->trans_state & PIPE_TRANS;
+			AUDIO_UNLOCK(endpoint->lock, flags);
+			//printk("waiting savenode\n");
+			if (trans) {
+				schedule_timeout(10);
+			}
+		}
+
+		AUDIO_LOCK(endpoint->lock, flags);
+		DUMP_LIST((audio_head *)endpoint->mem);
+		DUMP_NODE(endpoint->savenode, "SN");
+		AUDIO_UNLOCK(endpoint->lock, flags);
+	} else {
+		// FORCE_STOP routine, both replay and record mode could run
+		audio_node *pusenode;
+
+		// Shutdown DMA immediately and clear lists forcely.
+		AUDIO_LOCK(endpoint->lock, flags);
+
+		endpoint->trans_state &= ~PIPE_TRANS;
+		audio_stop_dma_node(&endpoint->dma);
+
+		DUMP_LIST((audio_head *)endpoint->mem);
+		DUMP_NODE(endpoint->savenode, "SN");
+		DPRINT_Q("---------------------------------\n");
+
+		while (!is_null_use_audio_node(endpoint->mem)) {
+			pusenode = get_audio_usenode(endpoint->mem);
+			if (pusenode) {
+				put_audio_freenode(endpoint->mem, pusenode);
+			}
+		}
+
+		DUMP_LIST((audio_head *)endpoint->mem);
+		DUMP_NODE(endpoint->savenode, "SN");
+		DPRINT_Q("---------------------------------\n");
+
+		if (endpoint->savenode) {
+			DPRINT_Q("handle savenode : 0x%08x\n", (unsigned int)endpoint->savenode);
+			DUMP_NODE(endpoint->savenode, "SN");
+			put_audio_freenode(endpoint->mem, endpoint->savenode);
+
+			DPRINT_Q("savenode->list->next = 0x%08x, savenode->list->prev = 0x%08x\n",
+			       (unsigned int)endpoint->savenode->list.next,
+			       (unsigned int)endpoint->savenode->list.prev);
+
+			endpoint->savenode = NULL;
+		}
+
+		DUMP_LIST((audio_head *)endpoint->mem);
+		DUMP_NODE(endpoint->savenode, "SN");
+
+		AUDIO_UNLOCK(endpoint->lock, flags);
+	}
+
+_L_AUDIO_CLOSE_EP_RET:
+	LEAVE();
+}
+
+int audio_resizemem_endpoint(audio_pipe *endpoint, unsigned int pagesize, unsigned int count)
+{
+	int ret;
+	if((endpoint->fragsize == pagesize)&&(endpoint->fragstotal == count))
+	return 1;//debug by wll
+	ret = init_audio_node(&endpoint->mem, pagesize, count);
+	if (ret) {
+		endpoint->fragsize = pagesize;
+		endpoint->fragstotal = count;
+	}
+	return ret;
+}
+
+static void handle_in_endpoint_work(audio_pipe *endpoint)
+{
+	audio_node	*node;
+	unsigned long	flags;
+
+	ENTER();
+
+	AUDIO_LOCK(endpoint->lock, flags);
+	if (endpoint->savenode) {
+		DPRINT_Q("\nIIII RRRR QQQQ >>>>\n");
+		DUMP_LIST((audio_head *)endpoint->mem);
+		DUMP_NODE(endpoint->savenode, "IRQSN");
+		DPRINT_Q("IIII RRRR QQQQ <<<<\n\n");
+
+		DPRINT_IRQ("%s endpoint->savenode = 0x%p\n", __FUNCTION__, endpoint->savenode);
+		put_audio_usenode(endpoint->mem, endpoint->savenode);
+
+		endpoint->savenode = NULL;
+		DUMP_BUF((char *)(endpoint->savenode->pBuf + endpoint->savenode->start), 64, 32);
+
+		if (!(endpoint->is_non_block)) {
+			endpoint->avialable_couter++;
+			wake_up_interruptible(&endpoint->q_full);
+		}
+	}
+
+	node = get_audio_freenode(endpoint->mem);
+	if (node) {
+		int start;
+		node->end = endpoint->fragsize;
+		dma_cache_wback_inv((unsigned long)node->pBuf, endpoint->fragsize);
+		start = audio_trystart_dma_node(&(endpoint->dma), node);
+		if (start == 0) {
+			put_audio_freenode(endpoint->mem, node);
+		} else {
+			endpoint->savenode = node;
+		}
+	} else {
+		endpoint->trans_state &= ~PIPE_TRANS;
+		__i2s_disable_receive_dma();
+		__i2s_disable_record();
+		DPRINT_IRQ("!!!! Stop AIC record !\n");
+	}
+
+	DPRINT_Q("\nIIII RRRR QQQQ >>>>\n");
+	DUMP_LIST((audio_head *)endpoint->mem);
+	DUMP_NODE(endpoint->savenode, "SN");
+	DPRINT_Q("IIII RRRR QQQQ <<<<\n\n");
+
+	AUDIO_UNLOCK(endpoint->lock, flags);
+
+	LEAVE();
+}
+
+/*
+static void audio_in_endpoint_work(struct work_struct *work)
+{
+	audio_pipe *endpoint = &in_endpoint;
+	handle_in_endpoint_work(endpoint);
+}
+*/
+
+static void handle_out_endpoint_work(audio_pipe *endpoint)
+{
+	audio_node *node;
+	unsigned long flags;
+
+	ENTER();
+
+	AUDIO_LOCK(endpoint->lock, flags);
+	DPRINT_IRQ("%s endpoint->savenode = 0x%08x\n", __FUNCTION__, (unsigned int)endpoint->savenode);
+
+	if (endpoint->savenode) {
+		put_audio_freenode(endpoint->mem, endpoint->savenode);
+		DPRINT_IRQ("put_audio_freenode\n");
+		endpoint->savenode = NULL;
+
+		if (!(endpoint->is_non_block)) {
+			wake_up_interruptible(&endpoint->q_full);
+			endpoint->avialable_couter++;
+		}
+	}
+
+	node = get_audio_usenode(endpoint->mem);
+	if (node) {
+		int start;
+		start = audio_trystart_dma_node(&(endpoint->dma), node);
+		if (start == 0) {
+			printk("audio_out_endpoint_work audio_trystart_dma_node error!\n");
+		} else {
+			endpoint->savenode = node;
+			DPRINT_DMA("restart dma!\n");
+		}
+	} else {
+		endpoint->trans_state &= ~PIPE_TRANS;
+		aic_disable_transmit();
+		DPRINT_IRQ("!!!! Stop AIC !\n");
+	}
+
+	AUDIO_UNLOCK(endpoint->lock, flags);
+	LEAVE();
+}
+
+/*
+static void audio_out_endpoint_work(struct work_struct *work)
+{
+	audio_pipe *endpoint = &out_endpoint;
+	handle_out_endpoint_work(endpoint);
+}
+*/
+
+void audio_init_endpoint(audio_pipe *endpoint, unsigned int pagesize, unsigned int count)
+{
+	audio_resizemem_endpoint(endpoint, pagesize, count);
+	spin_lock_init(&endpoint->lock);
+	init_waitqueue_head(&endpoint->q_full);
+	endpoint->avialable_couter = 0;
+	endpoint->filter = NULL;
+
+	if (endpoint == &in_endpoint) {
+		init_audio_audiodma(endpoint, CODEC_RMODE);
+		// INIT_WORK(&endpoint->work, audio_in_endpoint_work);
+		endpoint->handle = handle_in_endpoint_work;
+	}
+	if (endpoint == &out_endpoint) {
+		init_audio_audiodma(endpoint, CODEC_WMODE);
+		// INIT_WORK(&endpoint->work, audio_out_endpoint_work);
+		endpoint->handle = handle_out_endpoint_work;
+	}
+}
+
+void audio_deinit_endpoint(audio_pipe *endpoint)
+{
+	audio_close_endpoint(endpoint, FORCE_STOP);
+	deinit_audio_node(&endpoint->mem);
+}
+
+void register_jz_codecs(void *func)
+{
+	int i;
+
+	ENTER();
+
+	for (i = 0; i < NR_I2S; i++) {
+		if (the_codecs[i].codecs_ioctrl == 0) {
+			printk("register codec %x\n",(unsigned int)func);
+			the_codecs[i].id = i;
+			the_codecs[i].codecs_ioctrl = func;
+			init_MUTEX(&(the_codecs[i].i2s_sem));
+			break;
+		}
+	}
+
+	LEAVE();
+}
+
+#define codec_ioctrl(codec, cmd, args) ({			\
+	int result;						\
+	down(&(codec)->i2s_sem);				\
+	result = (codec)->codecs_ioctrl((codec), (cmd), (args));\
+	up(&(codec)->i2s_sem);					\
+	result;							\
+})
+
+static int jz_i2s_open_mixdev(struct inode *inode, struct file *file)
+{
+	int i;
+	int minor = MINOR(inode->i_rdev);
+
+	ENTER();
+
+	for (i = 0; i < NR_I2S; i++) {
+		if (the_codecs[i].dev_mixer == minor) {
+			goto match;
+		}
+	}
+match:
+	file->private_data = &the_codecs[i];
+
+	LEAVE();
+	return 0;
+}
+
+/*
+ * Debug entry for Android
+ */
+static int jz_i2s_write_mixdev(struct file *file, const char __user *buffer, size_t count, loff_t *ppos)
+{
+	struct i2s_codec *codec = (struct i2s_codec *)file->private_data;
+	char	buf_byte = 0;
+	char	argument[16];
+	int	val;
+
+	if (copy_from_user((void *)&buf_byte, buffer, 1)) {
+		printk("JZ MIX: copy_from_user failed !\n");
+		return -EFAULT;
+	}
+
+	switch (buf_byte) {
+	case '1':
+		dump_dlv_regs("jz_i2s_write_mixdev --- debug routine");
+		dump_aic_regs("");
+		break;
+	case '2':
+		printk("dlv_set_replay\n");
+		codec_ioctrl(codec, CODEC_SET_REPLAY, 0);
+		break;
+	case '3':
+		printk("dlv_set_record\n");
+		codec_ioctrl(codec, CODEC_SET_RECORD, 0);
+		break;
+	case '4':
+		if (codec_ioctrl(codec, CODEC_SET_RECORD_DATA_WIDTH, 16) >= 0) {
+			printk("Set data width : 16\n");
+		} else {
+			printk("Could not set data width\n");
+		}
+		break;
+	case '5':
+		if (copy_from_user((void *)&argument, buffer + 1, 3)) {
+			printk("JZ MIX: copy_from_user failed !\n");
+			return -EFAULT;
+		}
+		if (argument[0] >= '0' && argument[0] <= '9'
+		    && argument [1] >= '0' && argument[1] <= '9'
+		    && argument [2] >= '0' && argument[2] <= '9') {
+
+			val = (argument[0] - '0') * 100 + (argument[1] - '0') * 10 + argument[2] - '0';
+
+			printk("JZ MIX: set volume (%d)\n", val);
+			codec_ioctrl(codec, CODEC_SET_VOLUME, val);
+		} else {
+			printk("JZ MIX: invalid argument for set volume\n");
+		}
+		break;
+	}
+
+	return count;
+}
+
+/*
+ * Handle IOCTL request on /dev/mixer
+ *
+ * Support OSS IOCTL interfaces for /dev/mixer
+ * Support IOCTL interfaces for /dev/mixer defined in include/msm_audio.h
+ */
+static int jz_i2s_ioctl_mixdev(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
+{
+	struct i2s_codec *codec = (struct i2s_codec *)file->private_data;
+	long	val = 0;
+	int	ret, rc = 0;
+
+#ifdef CONFIG_JZ_EBOOK_HARD
+//	printk("DEBUG: %s, %d\n", __FUNCTION__, __LINE__);
+	/* add by qinbh, control the aic clock */
+	int reg = REG_CPM_CLKGR;
+//	__cpm_start_aic1();
+#endif
+
+
+	ENTER();
+
+	DPRINT_IOC("[mixer IOCTL]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n");
+	DPRINT_IOC(" mixer IOCTL %s cmd = 0x%08x, arg = %lu\n", __FUNCTION__, cmd, arg);
+	DPRINT_MIXER_IOC_CMD(cmd);
+	DPRINT_IOC("[mixer IOCTL]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n");
+
+	// struct jz_i2s_controller_info *controller = (struct jz_i2s_controller_info *) file->private_data;
+
+	switch (cmd) {
+
+	/*
+	 * OSS IOCTL commands for /dev/mixer
+	 */
+	case SOUND_MIXER_INFO:
+	{
+		mixer_info info;
+		codec_ioctrl(codec, CODEC_GET_MIXER_INFO, (unsigned int)&info);
+		info.modify_counter = audio_mix_modcnt;
+		return copy_to_user((void *)arg, &info, sizeof(info));
+	}
+	case SOUND_OLD_MIXER_INFO:
+	{
+		_old_mixer_info info;
+		codec_ioctrl(codec, CODEC_GET_MIXER_OLD_INFO, (unsigned int)&info);
+		return copy_to_user((void *)arg, &info, sizeof(info));
+	}
+
+	case SOUND_MIXER_READ_STEREODEVS:
+		return put_user(0, (long *) arg);
+	case SOUND_MIXER_READ_CAPS:
+		return put_user(SOUND_CAP_EXCL_INPUT, (long *) arg);
+
+	case SOUND_MIXER_READ_DEVMASK:
+		break;
+	case SOUND_MIXER_READ_RECMASK:
+		break;
+	case SOUND_MIXER_READ_RECSRC:
+		break;
+
+	case SOUND_MIXER_WRITE_SPEAKER:
+		ret = get_user(val, (long *) arg);
+		if ((val &= 0xff) >= 100) {
+			val = 100;
+		}
+		codec_ioctrl(codec, CODEC_SET_DIRECT_MODE, val);
+		break;
+
+	case SOUND_MIXER_WRITE_BASS:
+		ret = get_user(val, (long *) arg);
+		if ((val &= 0xff) >= 100) {
+			val = 100;
+		}
+		codec->bass_gain = val;
+		codec_ioctrl(codec, CODEC_SET_BASS, val);
+		return 0;
+
+	case SOUND_MIXER_READ_BASS:
+		val = codec->bass_gain;
+		ret = val << 8;
+		val = val | ret;
+		return put_user(val, (long *) arg);
+
+	case SOUND_MIXER_WRITE_VOLUME:
+		ret = get_user(val, (long *) arg);
+		if ((val &= 0xff) >= 100) {
+			val = 100;
+		}
+
+		DPRINT_IOC("SOUND_MIXER_WRITE_VOLUME <- %lu\n", val);
+
+		codec->audio_volume = val;
+		codec_ioctrl(codec, CODEC_SET_VOLUME, val);
+		return 0;
+
+	case SOUND_MIXER_READ_VOLUME:
+		val = codec->audio_volume;
+		ret = val << 8;
+		val = val | ret;
+		return put_user(val, (long *) arg);
+
+	case SOUND_MIXER_WRITE_MIC:
+		ret = get_user(val, (long *) arg);
+		if ((val &= 0xff) >= 100) {
+			val = 100;
+		}
+		codec->mic_gain = val;
+		codec->use_mic_line_flag = USE_MIC;
+		codec_ioctrl(codec, CODEC_SET_MIC, val);
+		return 0;
+
+	case SOUND_MIXER_READ_MIC:
+		val = codec->mic_gain;
+		ret = val << 8;
+		val = val | ret;
+		return put_user(val, (long *) arg);
+
+	case SOUND_MIXER_WRITE_LINE:
+		ret = get_user(val, (long *) arg);
+		if (ret) {
+			return ret;
+		}
+		if ((val &= 0xff) >= 100) {
+			val = 100;
+		}
+		codec->use_mic_line_flag = USE_LINEIN;
+		codec->mic_gain = val;
+		codec_ioctrl(codec, CODEC_SET_LINE, val);
+		return 0;
+
+	case SOUND_MIXER_READ_LINE:
+		val = codec->mic_gain;
+		ret = val << 8;
+		val = val | ret;
+		return put_user(val, (long *) arg);
+
+	case SOUND_MIXER_WRITE_MUTE:
+		get_user(codec->audiomute, (long *)arg);
+		//codec_ioctrl(codec, CODEC_DAC_MUTE, codec->audiomute);
+		break;
+
+	case SOUND_MIXER_READ_MUTE:
+		put_user(codec->audiomute, (long *) arg);
+		break;
+
+#if 0
+	/*
+	 * MSM IOCTL commands for /dev/mixer
+	 */
+	case SND_SET_DEVICE:
+	{
+		struct snd_device_config dev;
+		if (copy_from_user(&dev, (void *) arg, sizeof(dev))) {
+			rc = -EFAULT;
+			break;
+		}
+		break;
+	}
+
+	case SND_SET_VOLUME:
+	{
+		struct snd_volume_config vol;
+		if (copy_from_user(&vol, (void *) arg, sizeof(vol))) {
+			return -EFAULT;
+		}
+		val =  vol.volume;
+		if ((val &= 0xff) >= 100) {
+			val = 100;
+		}
+		DPRINT_IOC("snd_set_volume %d %d %d\n", vol.device, vol.method, vol.volume);
+		codec->audio_volume = val;
+		codec_ioctrl(codec, CODEC_SET_MIC, (unsigned int)&val); ///??????????????????????????
+		//error
+		break;
+	}
+
+	case SND_GET_NUM_ENDPOINTS:
+		if (copy_to_user((void __user*) arg, &snd->snd_epts->num, sizeof(unsigned))) {
+			printk("%s: error get endpoint\n",__FUNCTION__);
+			rc = -EFAULT;
+		}
+		val = 2;
+		if (copy_to_user((void __user*) arg, &val, sizeof(unsigned))) {
+			printk("%s: error get endpoint\n",__FUNCTION__);
+			rc = -EFAULT;
+		}
+
+		break;
+	case SND_GET_ENDPOINT:
+		//rc = get_endpoint(snd, arg);
+		break;
+#endif
+
+	default:
+		printk("Mixer IOCTL error: %s:%d: known command: 0x%08x\n", __FUNCTION__, __LINE__, cmd);
+		return -ENOSYS;
+	}
+	audio_mix_modcnt++;
+
+#ifdef CONFIG_JZ_EBOOK_HARD
+//	printk("DEBUG: %s, %d\n", __FUNCTION__, __LINE__);
+	/* add by qinbh */
+	REG_CPM_CLKGR = reg;
+#endif
+
+	LEAVE();
+	return rc;
+}
+
+static struct file_operations jz_i2s_mixer_fops =
+{
+	owner:		THIS_MODULE,
+	ioctl:		jz_i2s_ioctl_mixdev,
+	open:		jz_i2s_open_mixdev,
+	write:		jz_i2s_write_mixdev,
+};
+
+int i2s_probe_codec(struct i2s_codec *codec)
+{
+	/* generic OSS to I2S wrapper */
+	return (codec->codecs_ioctrl) ? 1 : 0;
+}
+
+/* I2S codec initialisation. */
+static int __init jz_i2s_codec_init(struct jz_i2s_controller_info *controller)
+{
+	int i;
+
+	ENTER();
+
+	for (i = 0; i < NR_I2S; i++) {
+		the_codecs[i].private_data = controller;
+		if (i2s_probe_codec(&the_codecs[i]) == 0) {
+			break;
+		}
+		if ((the_codecs[i].dev_mixer = register_sound_mixer(&jz_i2s_mixer_fops, the_codecs[i].id)) < 0) {
+			printk(KERN_ERR "JZ I2S: couldn't register mixer!\n");
+			break;
+		}
+
+	}
+	controller->i2s_codec = &the_codecs[0];
+
+	LEAVE();
+	return i;
+}
+
+static void jz_i2s_reinit_hw(struct i2s_codec *codec, int mode)
+{
+	ENTER();
+
+   	__i2s_disable();
+	schedule_timeout(5);
+	codec_ioctrl(codec, CODEC_EACH_TIME_INIT, 0);
+	__i2s_disable_record();
+	__i2s_disable_replay();
+	__i2s_disable_loopback();
+	__i2s_set_transmit_trigger(4);
+	__i2s_set_receive_trigger(3);
+	__i2s_send_rfirst();
+
+	LEAVE();
+}
+
+static int jz_codec_set_speed(struct i2s_codec *codec, int rate, int mode)
+{
+	ENTER();
+
+	/* 8000, 11025, 16000, 22050, 24000, 32000, 44100, 48000, 99999999 ? */
+	if (mode & CODEC_RMODE) {
+		rate = codec_ioctrl(codec, CODEC_SET_RECORD_SPEED, rate);
+		if (rate > 0) {
+			codec->record_audio_rate = rate;
+		} else {
+			rate = codec->record_audio_rate;
+		}
+	}
+	if (mode & CODEC_WMODE) {
+		rate = codec_ioctrl(codec, CODEC_SET_REPLAY_SPEED, rate);
+		if (rate > 0) {
+			codec->replay_audio_rate = rate;
+		} else {
+			rate = codec->replay_audio_rate;
+		}
+	}
+
+	LEAVE();
+	return rate;
+}
+
+static short jz_codec_set_channels(struct i2s_codec *codec, short channels, int mode)
+{
+	ENTER();
+
+	DPRINT_IOC("%s mode = %x channels = %d\n", __FUNCTION__, mode, channels);
+	DPRINT_IOC("mode & CODEC_RMODE == %x", mode & CODEC_RMODE);
+
+	if (mode & CODEC_RMODE) {
+		channels = codec_ioctrl(codec, CODEC_SET_RECORD_CHANNEL, channels);
+		codec->record_codec_channel = channels;
+	}
+	if (mode & CODEC_WMODE) {
+		channels = codec_ioctrl(codec, CODEC_SET_REPLAY_CHANNEL, channels);
+		codec->replay_codec_channel = channels;
+		if (channels == 1) {
+			__aic_enable_mono2stereo();
+			__aic_out_channel_select(0);
+		} else {
+			__aic_disable_mono2stereo();
+			__aic_out_channel_select(1);
+		}
+	}
+
+	LEAVE();
+
+	return channels;
+}
+
+static void jz_codec_select_mode(struct i2s_codec *codec, int mode)
+{
+	ENTER();
+
+	switch (mode) {
+	case CODEC_WRMODE:
+		if (codec->use_mic_line_flag == USE_NONE) {
+			codec->use_mic_line_flag = USE_MIC;
+		}
+		codec_ioctrl(codec, CODEC_SET_REPLAY_RECORD, codec->use_mic_line_flag);
+		break;
+	case CODEC_RMODE:
+		if (codec->use_mic_line_flag == USE_NONE) {
+			codec->use_mic_line_flag = USE_MIC;
+		}
+		codec_ioctrl(codec, CODEC_SET_RECORD, codec->use_mic_line_flag);
+		break;
+	case CODEC_WMODE:
+		printk("===>wmode!!!\n");
+		codec_ioctrl(codec, CODEC_SET_REPLAY, mode);
+		break;
+	}
+
+	LEAVE();
+}
+
+void jz_codec_anti_pop(struct i2s_codec *codec, int mode)
+{
+	ENTER();
+	codec_ioctrl(codec, CODEC_ANTI_POP, mode);
+	LEAVE();
+}
+
+void jz_codec_close(struct i2s_codec *codec, int mode)
+{
+	ENTER();
+	down(&codec->i2s_sem);
+	codec->codecs_ioctrl(codec, CODEC_TURN_OFF, mode);
+	up(&codec->i2s_sem);
+	LEAVE();
+}
+
+/***************************************************************
+			filter functions
+ ***************************************************************/
+
+/*
+ * Convert signed byte to unsiged byte
+ *
+ * Mapping:
+ * 	signed		unsigned
+ *	0x00 (0)	0x80 (128)
+ *	0x01 (1)	0x81 (129)
+ *	......		......
+ *	0x7f (127)	0xff (255)
+ *	0x80 (-128)	0x00 (0)
+ *	0x81 (-127)	0x01 (1)
+ *	......		......
+ *	0xff (-1)	0x7f (127)
+ */
+static int convert_8bits_signed2unsigned(void *buffer, int counter)
+{
+	int i;
+	int counter_8align	= counter & ~0x7;
+	unsigned char *ucsrc	= buffer;
+	unsigned char *ucdst	= buffer;
+
+	ENTER();
+
+	for (i = 0; i < counter_8align; i+=8) {
+		*(ucdst + i + 0) = *(ucsrc + i + 0) + 0x80;
+		*(ucdst + i + 1) = *(ucsrc + i + 1) + 0x80;
+		*(ucdst + i + 2) = *(ucsrc + i + 2) + 0x80;
+		*(ucdst + i + 3) = *(ucsrc + i + 3) + 0x80;
+		*(ucdst + i + 4) = *(ucsrc + i + 4) + 0x80;
+		*(ucdst + i + 5) = *(ucsrc + i + 5) + 0x80;
+		*(ucdst + i + 6) = *(ucsrc + i + 6) + 0x80;
+		*(ucdst + i + 7) = *(ucsrc + i + 7) + 0x80;
+		//printk("csrc + %d + 7 = %d,  ucdst + %d + 7 = %d\n",
+		//       i, *(csrc + i + 7), i, *(ucdst + i + 7));
+	}
+
+	BUG_ON(i != counter_8align);
+
+	for (i = counter_8align; i < counter; i++) {
+		*(ucdst + i) = *(ucsrc + i) + 0x80;
+	}
+
+	//printk("[dbg] src = 0x%02x (%d) --- dst = 0x%02x (%d), cnt = %d, cnt8a = %d\n",
+	//       *csrc, *csrc, *ucdst, *ucdst, counter, counter_8align);
+	LEAVE();
+	return counter;
+}
+
+/*
+ * Convert stereo data to mono data, data width: 8 bits/channel
+ *
+ * buff:	buffer address
+ * data_len:	data length in kernel space, the length of stereo data
+ *		calculated by "node->end - node->start"
+ */
+int convert_8bits_stereo2mono(void *buff, int data_len)
+{
+	/* stride = 16 bytes = 2 channels * 1 byte * 8 pipelines */
+	int data_len_16aligned = data_len & ~0xf;
+	int mono_cur, stereo_cur;
+	unsigned char *uc_buff = buff;
+
+	/* copy 8 times each loop */
+	for (stereo_cur = mono_cur = 0;
+	     stereo_cur < data_len_16aligned;
+	     stereo_cur += 16, mono_cur += 8) {
+
+		uc_buff[mono_cur + 0] = uc_buff[stereo_cur + 0];
+		uc_buff[mono_cur + 1] = uc_buff[stereo_cur + 2];
+		uc_buff[mono_cur + 2] = uc_buff[stereo_cur + 4];
+		uc_buff[mono_cur + 3] = uc_buff[stereo_cur + 6];
+		uc_buff[mono_cur + 4] = uc_buff[stereo_cur + 8];
+		uc_buff[mono_cur + 5] = uc_buff[stereo_cur + 10];
+		uc_buff[mono_cur + 6] = uc_buff[stereo_cur + 12];
+		uc_buff[mono_cur + 7] = uc_buff[stereo_cur + 14];
+	}
+
+	BUG_ON(stereo_cur != data_len_16aligned);
+
+	/* remaining data */
+	for (; stereo_cur < data_len; stereo_cur += 2, mono_cur++) {
+		uc_buff[mono_cur] = uc_buff[stereo_cur];
+	}
+
+	LEAVE();
+	return (data_len / 2);
+}
+
+/*
+ * Convert stereo data to mono data, and convert signed byte to unsigned byte.
+ *
+ * data width: 8 bits/channel
+ *
+ * buff:	buffer address
+ * data_len:	data length in kernel space, the length of stereo data
+ *		calculated by "node->end - node->start"
+ */
+int convert_8bits_stereo2mono_signed2unsigned(void *buff, int data_len)
+{
+	/* stride = 16 bytes = 2 channels * 1 byte * 8 pipelines */
+	int data_len_16aligned = data_len & ~0xf;
+	int mono_cur, stereo_cur;
+	unsigned char *uc_buff = buff;
+
+	/* copy 8 times each loop */
+	for (stereo_cur = mono_cur = 0;
+	     stereo_cur < data_len_16aligned;
+	     stereo_cur += 16, mono_cur += 8) {
+
+		uc_buff[mono_cur + 0] = uc_buff[stereo_cur + 0] + 0x80;
+		uc_buff[mono_cur + 1] = uc_buff[stereo_cur + 2] + 0x80;
+		uc_buff[mono_cur + 2] = uc_buff[stereo_cur + 4] + 0x80;
+		uc_buff[mono_cur + 3] = uc_buff[stereo_cur + 6] + 0x80;
+		uc_buff[mono_cur + 4] = uc_buff[stereo_cur + 8] + 0x80;
+		uc_buff[mono_cur + 5] = uc_buff[stereo_cur + 10] + 0x80;
+		uc_buff[mono_cur + 6] = uc_buff[stereo_cur + 12] + 0x80;
+		uc_buff[mono_cur + 7] = uc_buff[stereo_cur + 14] + 0x80;
+	}
+
+	BUG_ON(stereo_cur != data_len_16aligned);
+
+	/* remaining data */
+	for (; stereo_cur < data_len; stereo_cur += 2, mono_cur++) {
+		uc_buff[mono_cur] = uc_buff[stereo_cur] + 0x80;
+	}
+
+	LEAVE();
+	return (data_len / 2);
+}
+
+/*
+ * Convert stereo data to mono data, data width: 16 bits/channel
+ *
+ * buff:	buffer address
+ * data_len:	data length in kernel space, the length of stereo data
+ *		calculated by "node->end - node->start"
+ */
+int convert_16bits_stereo2mono(void *buff, int data_len)
+{
+	/* stride = 32 bytes = 2 channels * 2 byte * 8 pipelines */
+	int data_len_32aligned = data_len & ~0x1f;
+	int data_cnt_ushort = data_len_32aligned / 2;
+	int mono_cur, stereo_cur;
+	unsigned short *ushort_buff = (unsigned short *)buff;
+
+	/* copy 8 times each loop */
+	for (stereo_cur = mono_cur = 0;
+	     stereo_cur < data_cnt_ushort;
+	     stereo_cur += 16, mono_cur += 8) {
+
+		ushort_buff[mono_cur + 0] = ushort_buff[stereo_cur + 0];
+		ushort_buff[mono_cur + 1] = ushort_buff[stereo_cur + 2];
+		ushort_buff[mono_cur + 2] = ushort_buff[stereo_cur + 4];
+		ushort_buff[mono_cur + 3] = ushort_buff[stereo_cur + 6];
+		ushort_buff[mono_cur + 4] = ushort_buff[stereo_cur + 8];
+		ushort_buff[mono_cur + 5] = ushort_buff[stereo_cur + 10];
+		ushort_buff[mono_cur + 6] = ushort_buff[stereo_cur + 12];
+		ushort_buff[mono_cur + 7] = ushort_buff[stereo_cur + 14];
+	}
+
+	BUG_ON(stereo_cur != data_cnt_ushort);
+
+	/* remaining data */
+	for (; stereo_cur < data_cnt_ushort; stereo_cur += 2, mono_cur++) {
+		ushort_buff[mono_cur] = ushort_buff[stereo_cur];
+	}
+
+	LEAVE();
+	return (data_len / 2);
+}
+
+/*
+ * Set convert function for audio_pipe
+ *
+ * In AIC, we just use signed data for all ops as it is shared by
+ * replay and record. So, converting data for every non-compatible
+ * format is neccessary.
+ */
+static inline int endpoint_set_filter(audio_pipe *endpoint, int format, int channels)
+{
+	ENTER();
+
+	DPRINT("%s %d, endpoint = 0x%08x, format = %d, channels = %d\n",
+	       __FUNCTION__, __LINE__, (unsigned int)endpoint, format, channels);
+
+	endpoint->filter = NULL;
+
+	switch (format) {
+	case AFMT_U8:
+		if (endpoint == &in_endpoint) {
+			if (channels == 2) {
+				endpoint->filter = convert_8bits_stereo2mono_signed2unsigned;
+				DPRINT("$$$$ set pin_endpoint->filter = convert_8bits_stereo_2_mono\n");
+			} else {
+				endpoint->filter = convert_8bits_signed2unsigned;
+				DPRINT("$$$$ set pin_endpoint->filter = convert_8bits_signed2unsigned\n");
+			}
+		}
+		break;
+	case AFMT_S16_LE:
+		if (endpoint == &in_endpoint) {
+			if (channels == 1) {
+				endpoint->filter = convert_16bits_stereo2mono;
+				DPRINT("$$$$ set pin_endpoint->filter = convert_16bits_stereo2mono\n");
+			} else {
+				endpoint->filter = NULL;
+				DPRINT("$$$$ set pin_endpoint->filter = NULL\n");
+			}
+		}
+		break;
+	default:
+		printk("JZ I2S endpoint_set_filter: unknown format\n");
+		endpoint->filter = NULL;
+	}
+
+	LEAVE();
+	return 0;
+}
+
+/*
+ * The "format" contains data width, signed/unsigned and LE/BE
+ *
+ * The AIC registers will not be modified !
+ *
+ * For CODEC	set	data_width
+ */
+static int jz_codec_set_format(struct i2s_codec *codec, unsigned int format, int mode)
+{
+	/* The value of format reference to soundcard.h:
+	 *
+	 * AFMT_MU_LAW		0x00000001
+	 * AFMT_A_LAW		0x00000002
+	 * AFMT_IMA_ADPCM	0x00000004
+	 * AFMT_U8		0x00000008
+	 * AFMT_S16_LE		0x00000010
+	 * AFMT_S16_BE		0x00000020
+	 * AFMT_S8		0x00000040
+	 */
+	int data_width = 0;
+
+	ENTER();
+
+	DPRINT("$$$$ %s %d, format = %u, mode = %d\n", __FUNCTION__, __LINE__, format, mode);
+
+	down(&codec->i2s_sem);
+
+	/*
+	 * It is dangerous to modify settings about signed bit, endian and M2S
+	 * as record and replay shared the settings.
+	 *
+	 * Now we don't support unsigned format (AFMT_U8) and BE format (AFMT_S16_BE)
+	 * To support such format, corresponding filter function must be implemented.
+	 */
+	switch (format) {
+	case AFMT_U8:
+		data_width = 8;
+		if (mode & CODEC_RMODE) {
+			__i2s_set_iss_sample_size(8);
+		}
+		if (mode & CODEC_WMODE) {
+			__i2s_set_oss_sample_size(8);
+		}
+		break;
+	case AFMT_S8:
+		data_width = 8;
+		if (mode & CODEC_RMODE) {
+			__i2s_set_iss_sample_size(8);
+		}
+		if (mode & CODEC_WMODE) {
+			__i2s_set_oss_sample_size(8);
+		}
+		break;
+	case AFMT_S16_LE:
+		data_width = 16;
+		if (mode & CODEC_RMODE) {
+			__i2s_set_iss_sample_size(16);
+		}
+		if (mode & CODEC_WMODE) {
+			__i2s_set_oss_sample_size(16);
+		}
+		break;
+	case AFMT_S16_BE:
+		data_width = 16;
+		if (mode & CODEC_RMODE) {
+			__i2s_set_iss_sample_size(16);
+		}
+		if (mode & CODEC_WMODE) {
+			__i2s_set_oss_sample_size(16);
+		}
+		break;
+	default:
+		printk("JZ I2S: Unkown sound format %d\n", format);
+		goto _ERROR_SET_FORMAT;
+	}
+
+	if (mode & CODEC_RMODE) {
+		if (codec->codecs_ioctrl(codec, CODEC_SET_RECORD_DATA_WIDTH, data_width) < 0) {
+			printk("JZ I2S: CODEC ioctl error, command: CODEC_SET_RECORD_FORMAT");
+			goto _ERROR_SET_FORMAT;
+		}
+		codec->record_format = format;
+	}
+
+	if (mode & CODEC_WMODE) {
+		if (codec->codecs_ioctrl(codec, CODEC_SET_REPLAY_DATA_WIDTH, data_width) < 0) {
+			printk("JZ I2S: CODEC ioctl error, command: CODEC_SET_REPLAY_FORMAT");
+			goto _ERROR_SET_FORMAT;
+		}
+		codec->replay_format = format;
+	}
+
+	up(&codec->i2s_sem);
+	LEAVE();
+	return format;
+
+_ERROR_SET_FORMAT:
+	up(&codec->i2s_sem);
+	LEAVE();
+	return -1;
+}
+
+static int jz_audio_release(struct inode *inode, struct file *file)
+{
+	struct jz_i2s_controller_info *controller = (struct jz_i2s_controller_info *) file->private_data;
+	int mode = 0;
+	int codec_closed = 0;
+
+
+	ENTER();
+
+	if (controller == NULL) {
+		printk("\nAudio device not ready!\n");
+		return -ENODEV;
+	}
+	if ((controller->pin_endpoint == NULL) && (controller->pout_endpoint == NULL) ) {
+		printk("\nAudio endpoint not open!\n");
+		return -ENODEV;
+	}
+	if ((file->f_mode & FMODE_READ) && controller->pin_endpoint) {
+//		printk("Read mode, %s\n", __FUNCTION__);
+		mode |= CODEC_RMODE;
+		audio_close_endpoint(controller->pin_endpoint, FORCE_STOP);
+		controller->pin_endpoint = NULL;
+
+		__i2s_disable_receive_dma();
+		jz_codec_close(controller->i2s_codec, mode);
+		__i2s_disable_record();
+	}
+
+	if ((file->f_mode & FMODE_WRITE) && controller->pout_endpoint) {
+//		printk("Write mode, %s\n", __FUNCTION__);
+		mode |= CODEC_WMODE;
+		audio_close_endpoint(controller->pout_endpoint, NOMAL_STOP);
+		controller->pout_endpoint = NULL;
+
+		__i2s_disable_transmit_dma();
+
+		jz_codec_close(controller->i2s_codec, mode);
+		__i2s_enable_replay();
+		msleep(1);
+
+		__i2s_disable_replay();
+		codec_closed = 1;
+
+
+#ifdef CONFIG_JZ_EBOOK_HARD
+//		printk("DEBUG: %s, %d\n", __FUNCTION__, __LINE__);
+		__gpio_clear_pin(GPIO_SPK_SHUD);
+#endif
+	}
+
+
+	if ((controller->pin_endpoint == NULL) && (controller->pout_endpoint == NULL) ) {
+		__i2s_disable();
+	}
+
+	last_read_node = NULL;
+
+//	jz_codec_close(controller->i2s_codec, mode);
+
+#ifdef CONFIG_JZ_EBOOK_HARD
+//	printk("DEBUG: %s, %d\n", __FUNCTION__, __LINE__);
+//	__cpm_stop_aic1();
+	audio_device_open = 0;
+#endif
+
+	LEAVE();
+	return 0;
+}
+
+static int jz_audio_open(struct inode *inode, struct file *file)
+{
+	struct jz_i2s_controller_info *controller = the_i2s_controller;
+	struct i2s_codec *codec = controller->i2s_codec;
+	int mode = 0;
+	int reset = 1;
+
+	ENTER();
+
+	printk("===>enter %s:%d\n", __func__, __LINE__);
+
+	if (controller == NULL) {
+		return -ENODEV;
+	}
+#ifdef CONFIG_JZ_EBOOK_HARD
+//	printk("DEBUG: %s, %d\n", __FUNCTION__, __LINE__);
+//	__cpm_start_aic1();
+#endif
+
+	if (controller->pin_endpoint || controller->pout_endpoint) {
+		reset = 0;
+	}
+
+	if ((file->f_mode & FMODE_READ) && (controller->pin_endpoint)) {
+		printk("\nAudio read device is busy!\n");
+		return -EBUSY;
+	}
+	if ((file->f_mode & FMODE_WRITE) && (controller->pout_endpoint)) {
+		printk("\nAudio write device is busy!\n");
+		return -EBUSY;
+	}
+
+	if (file->f_mode & FMODE_WRITE) {
+		controller->pout_endpoint = &out_endpoint;
+		controller->pout_endpoint->is_non_block = file->f_flags & O_NONBLOCK;
+		mode |= CODEC_WMODE;
+	}
+	if (file->f_mode & FMODE_READ) {
+		controller->pin_endpoint = &in_endpoint;
+		controller->pin_endpoint->is_non_block = file->f_flags & O_NONBLOCK;
+		mode |= CODEC_RMODE;
+	}
+   	file->private_data = controller;
+
+	/* we should turn codec and anti-pop first */
+	//jz_codec_anti_pop(controller->i2s_codec, mode);
+	//printk("===>check point1\n");
+	//mdelay(5000);
+
+	if (mode & CODEC_RMODE){
+/*
+		jz_codec_set_channels(codec, 2, CODEC_RMODE);
+		jz_codec_set_format(codec, 8, CODEC_RMODE);
+		jz_codec_set_speed(codec, 8000, CODEC_RMODE);
+*/
+		jz_codec_set_channels(codec, 2, CODEC_RMODE);
+		jz_codec_set_format(codec, 16, CODEC_RMODE);
+		jz_codec_set_speed(codec, 44100, CODEC_RMODE);
+		codec->user_need_mono = 0;
+
+		set_controller_triger(controller, &in_endpoint, codec->record_codec_channel, codec->record_format);
+
+
+	}
+	if (mode & CODEC_WMODE) {
+		jz_codec_set_channels(codec, 2, CODEC_WMODE);
+		jz_codec_set_format(codec, 16, CODEC_WMODE);
+		jz_codec_set_speed(codec, 44100, CODEC_WMODE);
+		set_controller_triger(controller, &out_endpoint, codec->replay_codec_channel, codec->replay_format);
+#ifdef CONFIG_JZ_EBOOK_HARD
+//		printk("DEBUG: %s, %d\n", __FUNCTION__, __LINE__);
+		while (audio_device_pm_state == 1) schedule();
+		audio_device_open = 1;
+		if ((__gpio_get_pin(GPIO_HPONE_PLUG))) /* opposite logic with D21 */
+		{
+			__gpio_set_pin(GPIO_SPK_SHUD);
+		}
+#endif
+	}
+
+	//printk("===>check point2\n");
+	//mdelay(5000);
+
+	DPRINT_IOC("============ default_codec record ===============\n"
+		   "format	= %d\n"
+		   "channels	= %d\n"
+		   "rate	= %d\n"
+		   "dma one tran bit = %d\n",
+		   codec->record_format, codec->record_codec_channel,
+		   codec->record_audio_rate, in_endpoint.dma.onetrans_bit);
+
+	DPRINT_IOC("============ default_codec replay ===============\n"
+		   "format	= %d\n"
+		   "channels	= %d\n"
+		   "rate	= %d\n"
+		   "dma one tran bit = %d\n",
+		   codec->replay_format, codec->replay_codec_channel,
+		   codec->replay_audio_rate, out_endpoint.dma.onetrans_bit);
+
+	jz_codec_select_mode(controller->i2s_codec, mode);
+
+	//printk("===>check point3\n");
+	//mdelay(5000);
+
+	/* note: reset AIC  protected REG_AIC_I2SCR.ECCLK is setting */
+	if (reset) {
+		down(&controller->i2s_codec->i2s_sem);
+		//__i2s_enable_transmit_dma();
+		//__i2s_enable_receive_dma();
+		//__i2s_enable_replay();
+		__i2s_enable();
+		up(&controller->i2s_codec->i2s_sem);
+	}
+	//reinit codec option
+
+	//DUMP_AIC_REGS();
+	DPRINT_TRC(".... jz_audio_open\n");
+
+	g_play_first = 0;
+	jz_codec_anti_pop(controller->i2s_codec, mode);
+
+	//printk("===>check point4\n");
+	//mdelay(5000);
+
+	LEAVE();
+	return 0;
+}
+
+static int jz_audio_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
+{
+	long	rc = -EINVAL;
+	int	val = 0;
+	int	mode = 0;
+
+	struct jz_i2s_controller_info *controller = (struct jz_i2s_controller_info *) file->private_data;
+	struct i2s_codec *codec = controller->i2s_codec;
+	audio_pipe	*pin_endpoint = controller->pin_endpoint;
+	audio_pipe	*pout_endpoint = controller->pout_endpoint;
+
+	ENTER();
+
+	DPRINT_IOC("[dsp IOCTL] --------------------------------\n");
+	DPRINT_IOC(" dsp IOCTL %s cmd = (0x%08x), arg = %lu\n", __FUNCTION__, cmd, arg);
+	DPRINT_DSP_IOC_CMD(cmd);
+	DPRINT_IOC("[dsp IOCTL] --------------------------------\n");
+
+	if (file->f_mode & FMODE_READ) {
+		mode |= CODEC_RMODE;
+	}
+	if (file->f_mode & FMODE_WRITE) {
+		mode |= CODEC_WMODE;
+	}
+
+	switch (cmd) {
+
+	case OSS_GETVERSION:
+		rc = put_user(SOUND_VERSION, (int *)arg);
+		break;
+	case SNDCTL_DSP_RESET:
+		break;
+
+	case SNDCTL_DSP_SYNC:
+		if (mode & CODEC_WMODE) {
+			if (pout_endpoint) {
+				audio_sync_endpoint(pout_endpoint);
+			}
+		}
+		rc = 1;
+		break;
+
+	case SNDCTL_DSP_SPEED:
+		/* set smaple rate */
+		if (get_user(val, (int *)arg)) {
+			rc = -EFAULT;
+		}
+		//printk("SNDCTL_DSP_SPEED ... set to %d\n", val);
+		val = jz_codec_set_speed(codec, val, mode);
+		rc = put_user(val, (int *)arg);
+		break;
+
+	case SNDCTL_DSP_STEREO:
+		/* set stereo or mono channel */
+		if (get_user(val, (int *)arg)) {
+		    rc = -EFAULT;
+		}
+
+		jz_codec_set_channels(controller->i2s_codec, val ? 2 : 1, mode);
+
+		if (mode & CODEC_RMODE) {
+			set_controller_triger(controller, pin_endpoint,
+					      codec->record_codec_channel, codec->record_format);
+		}
+
+		if (mode & CODEC_WMODE) {
+			set_controller_triger(controller, pout_endpoint,
+					      codec->replay_codec_channel, codec->replay_format);
+		}
+
+		rc = 1;
+		break;
+
+	case SNDCTL_DSP_GETBLKSIZE:
+	{
+		// It seems that device could only be open with one mode (R or W)
+		int fragsize = 0;
+		if (mode & CODEC_RMODE) {
+			fragsize = pin_endpoint->fragsize;
+		}
+		if (mode & CODEC_WMODE) {
+			fragsize = pout_endpoint->fragsize;
+		}
+		rc = put_user(fragsize, (int *)arg);
+		break;
+	}
+
+	case SNDCTL_DSP_GETFMTS:
+		/* Returns a mask of supported sample format*/
+		rc = put_user(AFMT_U8 | AFMT_S16_LE, (int *)arg);
+		break;
+
+	case SNDCTL_DSP_SETFMT:
+		/* Select sample format */
+		if (get_user(val, (int *)arg)) {
+			rc = -EFAULT;
+		}
+
+//		printk("\nSNDCTL_DSP_SETFMT ... set to %d\n", val);
+
+		if (val == AFMT_QUERY) {
+			if (mode & CODEC_RMODE) {
+				val = codec->record_format;
+			} else {
+				val = codec->replay_format;
+			}
+		} else {
+			val = jz_codec_set_format(codec, val, mode);
+			if (mode & CODEC_RMODE) {
+				if (codec->user_need_mono) {
+					endpoint_set_filter(pin_endpoint, val, 1);
+				} else {
+					endpoint_set_filter(pin_endpoint, val, 2);
+				}
+
+				set_controller_triger(controller, pin_endpoint,
+						      codec->record_codec_channel, codec->record_format);
+			}
+			if (mode & CODEC_WMODE) {
+				set_controller_triger(controller, pout_endpoint,
+						      codec->replay_codec_channel, codec->replay_format);
+			}
+		}
+
+		rc = put_user(val, (int *)arg);
+		break;
+
+	case SNDCTL_DSP_CHANNELS:
+		if (get_user(val, (int *)arg)) {
+			rc = -EFAULT;
+		}
+		//printk("\nSNDCTL_DSP_CHANNELS ... set to %d\n", val);
+
+		/* if mono, change to 2, and set 1 to codec->user_need_mono */
+		if (mode & CODEC_RMODE) {
+			if (val == 1) {
+				val = 2;
+				codec->user_need_mono = 1;
+
+			} else {
+				codec->user_need_mono = 0;
+			}
+		}
+
+		/* Following lines could be marked as nothing will be changed */
+		jz_codec_set_channels(codec, val, mode);
+
+		if (mode & CODEC_RMODE) {
+			/* Set filter according to channel count */
+			if (codec->user_need_mono) {
+				endpoint_set_filter(pin_endpoint, codec->record_format, 1);
+			} else {
+				endpoint_set_filter(pin_endpoint, codec->record_format, 2);
+			}
+
+			set_controller_triger(controller, pin_endpoint,
+					      codec->record_codec_channel, codec->record_format);
+		}
+		if (mode & CODEC_WMODE) {
+			set_controller_triger(controller, pout_endpoint,
+					      codec->replay_codec_channel, codec->replay_format);
+		}
+
+		/* Restore for return value */
+		if (codec->user_need_mono) {
+			val = 1;
+		}
+
+		rc = put_user(val, (int *)arg);
+		break;
+
+	case SNDCTL_DSP_POST:
+		/* FIXME: the same as RESET ?? */
+		break;
+
+	case SNDCTL_DSP_SUBDIVIDE:
+		break;
+
+	case SNDCTL_DSP_SETFRAGMENT:
+		rc = get_user(val, (long *) arg);
+		if (rc != -EINVAL) {
+			int newfragsize, newfragstotal;
+			newfragsize = 1 << (val & 0xFFFF);
+			if (newfragsize < 4 * PAGE_SIZE) {
+				newfragsize = 4 * PAGE_SIZE;
+			}
+			if (newfragsize > (16 * PAGE_SIZE)) {
+				newfragsize = 16 * PAGE_SIZE;
+			}
+
+			newfragstotal = (val >> 16) & 0x7FFF;
+			if (newfragstotal < 2) {
+				newfragstotal = 2;
+			}
+			if (newfragstotal > 32) {
+				newfragstotal = 32;
+			}
+
+			if (mode & CODEC_RMODE) {
+				rc = audio_resizemem_endpoint(controller->pin_endpoint, newfragsize, newfragstotal);
+				if (!rc) {
+					rc = -EINVAL;
+				}
+			}
+			if (mode & CODEC_WMODE) {
+				rc = audio_resizemem_endpoint(controller->pout_endpoint, newfragsize, newfragstotal);
+				if (!rc) {
+					rc = -EINVAL;
+				}
+			}
+		}
+		break;
+
+	case SNDCTL_DSP_GETCAPS:
+		rc = put_user(DSP_CAP_REALTIME | DSP_CAP_BATCH, (int *)arg);
+		break;
+
+	case SNDCTL_DSP_NONBLOCK:
+		file->f_flags |= O_NONBLOCK;
+		rc = 0;
+		break;
+
+	case SNDCTL_DSP_SETDUPLEX:
+		rc = -EINVAL;
+		break;
+
+	case SNDCTL_DSP_GETOSPACE:
+	{
+		audio_buf_info abinfo;
+		if (!(mode & CODEC_WMODE)) {
+			return -EINVAL;
+		}
+		audio_get_endpoint_freesize(pout_endpoint, &abinfo);
+		rc = copy_to_user((void *)arg, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
+		break;
+	}
+
+	case SNDCTL_DSP_GETISPACE:
+	{
+		audio_buf_info abinfo;
+		if (!(mode & CODEC_RMODE)) {
+			return -EINVAL;
+		}
+		audio_get_endpoint_freesize(controller->pin_endpoint, &abinfo);
+		rc = copy_to_user((void *)arg, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
+		break;
+	}
+
+	case SNDCTL_DSP_GETTRIGGER:
+		val = 0;
+		if ((mode & CODEC_RMODE) && controller->pin_endpoint) {
+			val |= PCM_ENABLE_INPUT;
+		}
+		if ((mode & CODEC_WMODE) && controller->pout_endpoint) {
+			val |= PCM_ENABLE_OUTPUT;
+		}
+		rc = put_user(val, (int *)arg);
+
+		break;
+
+	case SNDCTL_DSP_SETTRIGGER:
+		if (get_user(val, (int *)arg)) {
+			rc = -EFAULT;
+		}
+		break;
+
+	case SNDCTL_DSP_GETIPTR:
+	{
+		count_info cinfo;
+		if (!(mode & CODEC_RMODE)) {
+			rc = -EINVAL;
+		}
+		rc = copy_to_user((void *)arg, &cinfo, sizeof(cinfo));
+		break;
+	}
+
+	case SNDCTL_DSP_GETOPTR:
+	{
+		count_info cinfo;
+		if (!(mode & CODEC_WMODE)) {
+			rc = -EINVAL;
+		}
+		rc = copy_to_user((void *) arg, &cinfo, sizeof(cinfo));
+		break;
+	}
+
+	case SNDCTL_DSP_GETODELAY:
+	{
+		// fix me !!!
+		int unfinish = 0;
+		if (!(mode & CODEC_WMODE)) {
+			rc = -EINVAL;
+		}
+		rc = put_user(unfinish, (int *) arg);
+		break;
+	}
+
+	case SOUND_PCM_READ_RATE:
+		if (mode  & CODEC_RMODE) {
+			//printk("\nSOUND_PCM_READ_RATE = %d\n", codec->record_audio_rate);
+			rc = put_user(codec->record_audio_rate, (int *)arg);
+		}
+		if (mode & CODEC_WMODE) {
+			//printk("\nSOUND_PCM_READ_RATE = %d\n", codec->replay_audio_rate);
+			rc = put_user(codec->replay_audio_rate, (int *)arg);
+		}
+		break;
+
+	case SOUND_PCM_READ_CHANNELS:
+		if (mode & CODEC_RMODE) {
+			//printk("\nSOUND_PCM_READ_RATE = %d\n", codec->record_codec_channel);
+			rc = put_user(codec->record_codec_channel, (int *)arg);
+		}
+		if (mode & CODEC_WMODE) {
+			//printk("\nSOUND_PCM_READ_RATE = %d\n", codec->replay_codec_channel);
+			rc = put_user(codec->replay_codec_channel, (int *)arg);
+		}
+		break;
+
+	case SOUND_PCM_READ_BITS:
+		if (mode & CODEC_RMODE) {
+			rc = put_user((codec->record_format & (AFMT_S8 | AFMT_U8)) ? 8 : 16, (int *)arg);
+		}
+		if (mode & CODEC_WMODE) {
+			rc = put_user((codec->record_format & (AFMT_S8 | AFMT_U8)) ? 8 : 16, (int *)arg);
+		}
+		break;
+
+	case SNDCTL_DSP_MAPINBUF:
+	case SNDCTL_DSP_MAPOUTBUF:
+	case SNDCTL_DSP_SETSYNCRO:
+	case SOUND_PCM_WRITE_FILTER:
+	case SOUND_PCM_READ_FILTER:
+		rc = -EINVAL;
+		break;
+#if 0
+	/* may be for msm only */
+	case AUDIO_GET_CONFIG:
+ 		break;
+
+	case AUDIO_SET_CONFIG:
+		break;
+#endif
+	default:
+		printk("%s[%s]:%d---no cmd\n",__FILE__,__FUNCTION__,__LINE__);
+		break;
+	}
+
+	LEAVE();
+
+	return rc;
+}
+
+static inline int endpoint_put_userdata(audio_pipe *endpoint, const char __user *buffer, size_t count)
+{
+	unsigned long	flags;
+	audio_node	*node;
+
+	ENTER();
+	DPRINT("<<<< put_userdata\n");
+
+	AUDIO_LOCK(endpoint->lock, flags);
+	node = get_audio_freenode(endpoint->mem);
+	AUDIO_UNLOCK(endpoint->lock, flags);
+
+	// For non-block mode
+	if (endpoint->is_non_block && !node) {
+		LEAVE();
+		return 0;
+	}
+
+	// For block mode, wait free node
+	while (!node) {
+		DPRINT("wait ----------\n");
+
+		AUDIO_LOCK(endpoint->lock, flags);
+		DUMP_LIST((audio_head *)endpoint->mem);
+		DUMP_NODE(endpoint->savenode, "SN");
+		AUDIO_UNLOCK(endpoint->lock, flags);
+
+		// wait available node
+		wait_event_interruptible(endpoint->q_full, (endpoint->avialable_couter >= 1));
+
+		AUDIO_LOCK(endpoint->lock, flags);
+		node = get_audio_freenode(endpoint->mem);
+		endpoint->avialable_couter = 0;
+		AUDIO_UNLOCK(endpoint->lock, flags);
+	}
+
+	if (copy_from_user((void *)node->pBuf, buffer, count)) {
+		printk("JZ I2S: copy_from_user failed !\n");
+		return -EFAULT;
+	}
+	dma_cache_wback_inv((unsigned long)node->pBuf,(unsigned long)count);
+	node->start = 0;
+	node->end = count;
+	AUDIO_LOCK(endpoint->lock, flags);
+	put_audio_usenode(endpoint->mem, node);
+	AUDIO_UNLOCK(endpoint->lock, flags);
+
+	LEAVE();
+
+	return count;
+}
+
+static ssize_t jz_audio_write(struct file *file, const char __user *buffer, size_t count, loff_t *ppos)
+{
+	struct jz_i2s_controller_info *controller = (struct jz_i2s_controller_info *)file->private_data;
+	audio_pipe *pout_endpoint = controller->pout_endpoint;
+	struct i2s_codec *codec = (struct i2s_codec *)controller->i2s_codec;
+	size_t	usecount = 0;
+	int	bat_cnt = -1;
+	int	rem_cnt = 0;
+
+	if (!g_play_first) {
+		// first play, trun on dac mute
+		//codec_ioctrl(codec, CODEC_FIRST_OUTPUT, 0);
+		g_play_first = 1;
+	}
+
+	//printk("===>enter %s:%d\n", __func__, __LINE__);
+
+	ENTER();
+
+	//dump_dlv_regs(__FUNCTION__);
+	//dump_aic_regs(__FUNCTION__);
+
+	// wll@20101020
+//	printk("===>enter %s: \n", __FUNCTION__);
+//	printk("write data count = %d\n", count);
+
+	while (count >= pout_endpoint->fragsize) {
+
+		bat_cnt = endpoint_put_userdata(pout_endpoint,
+						&(buffer[usecount]),
+						pout_endpoint->fragsize);
+		// Prepare data success.
+		if (bat_cnt > 0) {
+			usecount += bat_cnt;
+			count -= bat_cnt;
+			DPRINT("bat_cnt = %d\n", bat_cnt);
+		}
+		// Perhaps non node is avialable.
+		else if (bat_cnt == 0) {
+			DPRINT("bat_cnt == 0\n");
+			break;
+		}
+		// Error occured.
+		else {
+			// break and handle prepared data.
+			if (usecount > 0) {
+				DPRINT("bat_cnt < 0, usecount > 0\n");
+				break;
+			}
+			// Has not prepared any data and return error when prepared data.
+			else {
+				DPRINT("bat_cnt < 0, usecount == 0\n");
+				return bat_cnt;
+			}
+		}
+	}
+
+	DPRINT("count = %d\n", count);
+
+	// Prepare few data or remain data after below code.
+	if (bat_cnt != 0 && count >= 32) {
+		DPRINT("check point 2 ... count = %d\n", count);
+		rem_cnt = endpoint_put_userdata(pout_endpoint, &buffer[usecount], count);
+		if (rem_cnt > 0) {
+			usecount += rem_cnt;
+			count -= rem_cnt;
+			DPRINT("check point 3 ... rem_cnt = %d\n", rem_cnt);
+		} else if (rem_cnt <= 0) {
+			// Not success... return Error.
+			if (usecount == 0) {
+				DPRINT("rem_cnt <= 0, usecount == 0\n");
+				return rem_cnt;
+			}
+			// Go on handle prepared data, ignore the error.
+			else {
+				DPRINT("rem_cnt <= 0, usecount != 0, usecount = %d\n", usecount);
+			}
+		}
+	}
+
+	// Handle prepared data.
+	if (usecount > 0) {
+		unsigned long	flags;
+		audio_node	*node;
+		AUDIO_LOCK(pout_endpoint->lock, flags);
+		if ((pout_endpoint->trans_state & PIPE_TRANS) == 0) {
+			node = get_audio_usenode(pout_endpoint->mem);
+			if (node) {
+				unsigned int start;
+				start = trystart_endpoint_out(controller, node);
+				if (start == 0) {
+					printk("JZ I2S: trystart_endpoint_out error\n");
+				}
+			}
+		}
+		AUDIO_UNLOCK(pout_endpoint->lock, flags);
+	}
+
+	DPRINT("----write data usecount = %d, count = %d\n", usecount, count);
+	BUG_ON(count < 0);
+	LEAVE();
+
+	return usecount + (count < 32 ? count : 0);
+}
+
+/**
+ *  Copy recorded sound data from 'use' link list to userspace
+ */
+static inline int endpoint_get_userdata(audio_pipe *endpoint, const char __user *buffer, size_t count)
+{
+	unsigned long	flags;
+	audio_node	*node = last_read_node;
+	int	ret;
+
+	/* counter for node buffer, raw data */
+	int	node_buff_cnt = 0;
+
+	ENTER();
+
+	if (!node) {
+		AUDIO_LOCK(endpoint->lock, flags);
+		node = get_audio_usenode(endpoint->mem);
+		AUDIO_UNLOCK(endpoint->lock, flags);
+
+		if (node && endpoint->filter) {
+			node_buff_cnt = node->end - node->start;
+			node_buff_cnt = endpoint->filter((void *)(node->pBuf + node->start), node_buff_cnt);
+			node->end = node->start + node_buff_cnt;
+		}
+	}
+
+	DPRINT(">>>> %s mode\n", endpoint->is_non_block ? "non block" : "block");
+
+	// For non-block mode
+	if (endpoint->is_non_block && !node) {
+		return 0;
+	}
+
+	// For block mode, wait node which full filled data
+	while (!node) {
+		if ((endpoint->trans_state & PIPE_TRANS) == 0 ) {
+			DPRINT("DMA trans has not been started !\n");
+			return -1;
+		}
+
+		AUDIO_LOCK(endpoint->lock, flags);
+		DUMP_LIST((audio_head *)endpoint->mem);
+		DUMP_NODE(endpoint->savenode, "SN");
+		AUDIO_UNLOCK(endpoint->lock, flags);
+
+		DPRINT("record stereo ... wait pipe_sem ----------\n");
+
+		// wait available node
+//		interruptible_sleep_on(&endpoint->q_full);
+		wait_event_interruptible(endpoint->q_full, endpoint->avialable_couter >= 1);
+
+		AUDIO_LOCK(endpoint->lock, flags);
+		node = get_audio_usenode(endpoint->mem);
+		endpoint->avialable_couter = 0;
+		AUDIO_UNLOCK(endpoint->lock, flags);
+
+		if (node && endpoint->filter) {
+			node_buff_cnt = node->end - node->start;
+			node_buff_cnt = endpoint->filter((void *)(node->pBuf + node->start), node_buff_cnt);
+			node->end = node->start + node_buff_cnt;
+		}
+	}
+
+	if (node && (node_buff_cnt = node->end - node->start)) {
+		DPRINT("node_buff_cnt = %d, count = %d\n", node_buff_cnt, count);
+
+		if (count >= (size_t)node_buff_cnt) {
+			DPRINT(">>>> count >= fixed_buff_cnt, copy_to_user count = %d\n", node_buff_cnt);
+			ret = copy_to_user((void *)buffer, (void *)(node->pBuf + node->start), node_buff_cnt);
+			if (ret) {
+				printk("JZ I2S: copy_to_user failed, return %d\n", ret);
+				return -EFAULT;
+			}
+			put_audio_freenode(endpoint->mem, node);
+			last_read_node = NULL;
+		} else {
+			DPRINT(">>>> count < fixed_buff_cnt, copy_to_user count = %d\n", count);
+			ret = copy_to_user((void *)buffer,(void *)(node->pBuf + node->start), count);
+			if (ret) {
+				printk("JZ I2S: copy_to_user failed, return %d\n", ret);
+				return -EFAULT;
+			}
+			node->start += count;
+			last_read_node = node;
+		}
+	}
+
+	LEAVE();
+	return (node_buff_cnt < count ? node_buff_cnt : count);
+}
+
+static ssize_t jz_audio_read(struct file *file, char __user *buffer, size_t count, loff_t *ppos)
+{
+	struct jz_i2s_controller_info *controller = (struct jz_i2s_controller_info *)file->private_data;
+	audio_pipe	*pin_endpoint = controller->pin_endpoint;
+	audio_node	*node;
+	unsigned long	flags;
+	int		mcount, usecount = 0;
+
+	ENTER();
+
+//	dump_dlv_regs(__FUNCTION__);
+//	dump_aic_regs(__FUNCTION__);
+
+	if (count == 0) {
+		DPRINT("@@@@ jz_audio_read count == 0\n");
+		return 0;
+	}
+
+	AUDIO_LOCK(pin_endpoint->lock, flags);
+
+	DUMP_LIST((audio_head *)pin_endpoint->mem);
+	DUMP_NODE(pin_endpoint->savenode, "SN");
+
+	DPRINT("@@@@ jz_audio_read, pin_endpoint->trans_state = 0x%08x\n",
+	       pin_endpoint->trans_state);
+
+	if ((pin_endpoint->trans_state & PIPE_TRANS) == 0) {
+		DPRINT("@@@@ jz_audio_read, PIPE_TRANS\n");
+		node = get_audio_freenode(pin_endpoint->mem);
+		if (node) {
+			unsigned int start;
+			DPRINT("@@@@ jz_audio_read, trystart_endpoint_in\n");
+//			pin_endpoint->fragsize = count;
+			node->end = pin_endpoint->fragsize;
+
+			start = trystart_endpoint_in(controller, node);
+			if (start == 0) {
+				DPRINT("@@@@ Error ! jz_audio_read, start == 0\n");
+				put_audio_freenode(pin_endpoint->mem, node);
+			}
+		}
+	}
+	AUDIO_UNLOCK(pin_endpoint->lock, flags);
+
+	DUMP_AIC_REGS(__FUNCTION__);
+	DUMP_CODEC_REGS(__FUNCTION__);
+	//dump_dlv_regs(__FUNCTION__);
+	DPRINT("@@@@ count = %d\n", count);
+
+	do{
+		mcount = endpoint_get_userdata(pin_endpoint, &buffer[usecount], count);
+
+		DPRINT("@@@@ jz_audio_read, mcount = %d, usecount = %d\n", mcount, usecount);
+
+		if (mcount < 0) {
+			DPRINT("@@@@ jz_audio_read, mcount < 0, %d\n", mcount);
+			if (usecount > 0) {
+				break;
+			} else {
+				return mcount;
+			}
+		} else if (mcount == 0) {
+			DPRINT("@@@@ jz_audio_read, mcount == 0\n");
+			break;
+		} else {
+			usecount += mcount;
+			count -= mcount;
+			DPRINT("@@@@ jz_audio_read, mcount > 0, %d\n", mcount);
+		}
+	} while (count > 0);
+
+	DPRINT("@@@@ jz_audio_read, usecount = %d\n", usecount);
+
+	LEAVE();
+	return usecount;
+}
+
+/* static struct file_operations jz_i2s_audio_fops */
+static struct file_operations jz_i2s_audio_fops = {
+	owner:		THIS_MODULE,
+	open:		jz_audio_open,
+	release:	jz_audio_release,
+	write:		jz_audio_write,
+	read:		jz_audio_read,
+	ioctl:		jz_audio_ioctl
+};
+
+static void __init attach_jz_i2s(struct jz_i2s_controller_info *controller)
+{
+	char	*name = NULL;
+	int	adev = 0; /* No of Audio device. */
+
+	ENTER();
+
+	name = controller->name;
+
+	/* Initialize I2S CODEC and register /dev/mixer. */
+	if (jz_i2s_codec_init(controller) <= 0) {
+		goto mixer_failed;
+	}
+
+	/* Initialize AIC controller and reset it. */
+	jz_i2s_reinit_hw(controller->i2s_codec,1);
+	adev = register_sound_dsp(&jz_i2s_audio_fops, -1);
+	if (adev < 0) {
+		goto audio_failed;
+	}
+
+	controller->dev_audio = adev;
+	jz_codec_anti_pop(controller->i2s_codec, 1);    //CODEC_WMODE
+
+	LEAVE();
+
+	return;
+mixer_failed:
+
+audio_failed:
+	unregister_sound_dsp(adev);
+
+	LEAVE();
+	return;
+}
+
+static void __exit unload_jz_i2s(struct jz_i2s_controller_info *controller)
+{
+	jz_i2s_reinit_hw(controller->i2s_codec,0);
+}
+
+//--------------------------------------------------------------------
+#ifdef CONFIG_PM
+static int jz_i2s_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	int i;
+	struct i2s_codec *codec;
+	//audio_sync_endpoint(&out_endpoint);
+	//msleep(30);
+	for(i = 0;i < NR_I2S; i++){
+		codec = &the_codecs[i];
+		if (codec && codec->codecs_ioctrl) {
+			codec->codecs_ioctrl(codec, CODEC_I2S_SUSPEND, 0);
+		}
+	}
+
+//	printk("Aic and codec are suspended!\n");
+	return 0;
+}
+
+static int jz_i2s_resume(struct platform_device *pdev)
+{
+	int i;
+	struct i2s_codec *codec;
+	for(i = 0;i < NR_I2S; i++){
+		codec = &the_codecs[i];
+		if (codec && codec->codecs_ioctrl) {
+			codec->codecs_ioctrl(codec, CODEC_I2S_RESUME, 0);
+		}
+	}
+	return 0;
+}
+#endif /* CONFIG_PM */
+
+static int __init probe_jz_i2s(struct jz_i2s_controller_info **controller)
+{
+	struct jz_i2s_controller_info *ctrl;
+
+	ENTER();
+	ctrl = kmalloc(sizeof(struct jz_i2s_controller_info), GFP_KERNEL);
+	if (ctrl == NULL) {
+		printk(KERN_ERR "Jz I2S Controller: out of memory.\n");
+		return -ENOMEM;
+	}
+	ctrl->name = "Jz I2S controller";
+	ctrl->pout_endpoint = 0;
+	ctrl->pin_endpoint = 0;
+	ctrl->error = 0;
+	//ctrl->i2s_codec->use_mic_line_flag = USE_NONE;
+
+	*controller = ctrl;
+
+	LEAVE();
+
+	return 0;
+}
+
+void i2s_controller_init(void)
+{
+	unsigned int aicfr;
+	unsigned int aiccr;
+	//init cpm clock, use ext clock;
+
+	ENTER();
+
+	/* Select exclk as i2s clock */
+	cpm_set_clock(CGU_I2SCLK, JZ_EXTAL);
+
+	aicfr = (8 << 12) | (8 << 8) | (AIC_FR_ICDC | AIC_FR_LSMP | AIC_FR_AUSEL);
+	REG_AIC_FR = aicfr;
+
+	aiccr = REG_AIC_CR;
+	aiccr &= (~(AIC_CR_EREC | AIC_CR_ERPL | AIC_CR_TDMS | AIC_CR_RDMS));
+	REG_AIC_CR = aiccr;
+
+	LEAVE();
+}
+
+static int __init init_jz_i2s(struct platform_device *pdev)
+{
+	struct i2s_codec *default_codec = &(the_codecs[0]);
+	int errno;
+	int fragsize;
+	int fragstotal;
+
+	printk("===>enter %s\n", __func__);
+
+#ifdef CONFIG_JZ_EBOOK_HARD
+//	printk("DEBUG: %s, %d\n", __FUNCTION__, __LINE__);
+//	__cpm_start_aic1();
+#endif
+
+	cpm_start_clock(CGM_AIC);
+
+	REG_AIC_I2SCR |= AIC_I2SCR_ESCLK;
+	REG_AIC_I2SCR = 0x5a5a5a5a;
+	printk("===>REG_AIC_I2SCR = 0x%0x\n", REG_AIC_I2SCR);
+
+	i2s_controller_init();
+	if (default_codec->codecs_ioctrl == NULL) {
+		printk("default_codec: not ready!");
+		return -1;
+	}
+
+	default_codec->codecs_ioctrl(default_codec, CODEC_SET_MODE, 0);
+	//default_codec->codecs_ioctrl(default_codec, CODEC_INIT, 0);
+
+	if ((errno = probe_jz_i2s(&the_i2s_controller)) < 0) {
+		return errno;
+	}
+
+	//printk("===>enter %s:%d\n", __func__, __LINE__);
+	//mdelay(5000);
+
+	/* May be external CODEC need it ...
+	 * default_codec->codecs_ioctrl(default_codec, CODEC_SET_GPIO_PIN, 0);
+	 */
+	attach_jz_i2s(the_i2s_controller);
+	//printk("===>enter %s:%d\n", __func__, __LINE__);
+	//mdelay(5000);
+
+	/* Actually, the handler function of the command do nothing ...
+	 * default_codec->codecs_ioctrl(default_codec, CODEC_SET_STARTUP_PARAM, 0);
+	 * default_codec->codecs_ioctrl(default_codec, CODEC_SET_STARTUP_PARAM, 0);
+	 */
+
+	/* Now the command is not supported by DLV CODEC ...
+	 * default_codec->codecs_ioctrl(default_codec, CODEC_SET_VOLUME_TABLE, 0);
+	 */
+	fragsize = JZCODEC_RW_BUFFER_SIZE * PAGE_SIZE;
+	fragstotal = JZCODEC_RW_BUFFER_TOTAL;
+
+	audio_init_endpoint(&out_endpoint, fragsize, fragstotal);
+	audio_init_endpoint(&in_endpoint, fragsize, fragstotal);
+
+#ifdef CONFIG_JZ_EBOOK_HARD
+//	printk("DEBUG: %s, %d\n", __FUNCTION__, __LINE__);
+//	__cpm_stop_aic1();
+	audio_device_open = 0;
+#endif
+
+	printk("JZ I2S OSS audio driver initialized\n");
+
+	LEAVE();
+
+	return 0;
+}
+
+static void __exit cleanup_jz_i2s(void)
+{
+#ifdef CONFIG_PM
+	/* pm_unregister(i2s_controller->pm); */
+#endif
+	struct i2s_codec *default_codec = &the_codecs[0];
+	unload_jz_i2s(the_i2s_controller);
+	the_i2s_controller = NULL;
+	audio_deinit_endpoint(&out_endpoint);
+	audio_deinit_endpoint(&in_endpoint);
+	default_codec->codecs_ioctrl(default_codec, CODEC_CLEAR_MODE, 0);
+}
+
+static struct platform_driver snd_plat_driver = {
+	.probe	=  init_jz_i2s,
+	.driver	= {
+		.name	= "mixer",
+		.owner	= THIS_MODULE,
+	},
+	.suspend	= jz_i2s_suspend,
+	.resume		= jz_i2s_resume,
+};
+
+static int __init snd_init(void)
+{
+	return platform_driver_register(&snd_plat_driver);
+}
+
+module_init(snd_init);
+module_exit(cleanup_jz_i2s);