diff options
| author | Lubomir Rintel <lkundrak@v3.sk> | 2019-11-08 14:01:58 +0100 |
|---|---|---|
| committer | Mitch Bradley <wmb@firmworks.com> | 2019-11-08 07:30:53 -1000 |
| commit | 2e7caf333e9c4ba2c01f4d36257c6ff88922dc01 (patch) | |
| tree | 23cdf0b882717fc856fca76b744edd422271f0b2 | |
| parent | 5127d532cab4b0779aa249c966a32ad61b3f0721 (diff) | |
| download | cforth-2e7caf333e9c4ba2c01f4d36257c6ff88922dc01.tar.gz | |
arm-xo-1.75: drop initio.c
It is not used.
| -rw-r--r-- | src/platform/arm-xo-1.75/initio.c | 22 |
1 files changed, 0 insertions, 22 deletions
diff --git a/src/platform/arm-xo-1.75/initio.c b/src/platform/arm-xo-1.75/initio.c deleted file mode 100644 index 36414fc..0000000 --- a/src/platform/arm-xo-1.75/initio.c +++ /dev/null @@ -1,22 +0,0 @@ -void init_io() -{ - *(int *)0xd4051024 = 0xffffffff; // PMUM_CGR_PJ - everything on - *(int *)0xD4015064 = 0x7; // APBC_AIB_CLK_RST - reset, functional and APB clock on - *(int *)0xD4015064 = 0x3; // APBC_AIB_CLK_RST - release reset, functional and APB clock on - *(int *)0xD401502c = 0x13; // APBC_UART1_CLK_RST - VCTCXO, functional and APB clock on (26 mhz) - *(int *)0xD4015034 = 0x13; // APBC_UART3_CLK_RST - VCTCXO, functional and APB clock on (26 mhz) - -// *(int *)0xd401e120 = 0xc1; // GPIO51 = af1 for UART3 RXD -// *(int *)0xd401e124 = 0xc1; // GPIO52 = af1 for UART3 TXD - *(int *)0xd401e260 = 0xc4; // GPIO115 = af4 for UART3 RXD - *(int *)0xd401e264 = 0xc4; // GPIO116 = af4 for UART3 TXD - *(int *)0xd401e0c8 = 0xc1; // GPIO29 = af1 for UART1 RXD - *(int *)0xd401e0cc = 0xc1; // GPIO30 = af1 for UART1 TXD - - UARTREG[1] = 0x40; // Marvell-specific UART Enable bit - UARTREG[3] = 0x83; // Divisor Latch Access bit - UARTREG[0] = 42; // 38400 baud - UARTREG[1] = 00; // 38400 baud - UARTREG[3] = 0x03; // 8n1 - UARTREG[2] = 0x07; // FIFOs and stuff -} |