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| author | Jacopo Mondi <jacopo@jmondi.org> | 2022-06-16 16:31:58 +0200 |
|---|---|---|
| committer | Jacopo Mondi <jacopo.mondi@ideasonboard.com> | 2023-02-23 12:13:50 +0100 |
| commit | d20adc5b4362a3fece406d4ce668eb924cb1f1dc (patch) | |
| tree | a0b508a0aa9f4c3424c7e62519af5175c5234b1f | |
| parent | 40e0fba1f0a7a82aed594390c678645363ddce64 (diff) | |
| download | linux-jmondi/imx8mp/v6.2/icore-ar0521.tar.gz | |
arm64: dts: freescale: icore: edimm2.2: Add AR0521jmondi/imx8mp/v6.2/icore-ar0521
Maintain the CSI-2 timings commented out in DTS (they do not take effect
in mainline but do on the CSI-2 downstream driver) for reference.
Signed-off-by: Jacopo Mondi <jacopo@jmondi.org>
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp-edimm2.2.dts | 124 |
1 files changed, 124 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp-edimm2.2.dts b/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp-edimm2.2.dts index a02b31c42db487..f64a6756a9a3ab 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp-edimm2.2.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp-edimm2.2.dts @@ -10,6 +10,7 @@ #include "imx8mp.dtsi" #include "imx8mp-icore-mx8mp.dtsi" #include <dt-bindings/usb/pd.h> +#include <dt-bindings/media/video-interfaces.h> / { model = "Engicam i.Core MX8M Plus EDIMM2.2 Starter Kit"; @@ -64,6 +65,110 @@ }; }; +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + ar0521: ar0521_mipi@36 { + compatible = "onn,ar0521"; + reg = <0x36>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi0_pwn>, <&pinctrl_csi0_rst>; + powerdown-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; + + clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; + clock-names = "extclk"; + assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; + assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + + /* Does this work for real ?? */ + assigned-clock-rates = <27000000>; + + status = "okay"; + + port { + ar0521_out: endpoint { + remote-endpoint = <&mipi_csi0_ep>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&mipi_csi_0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ports { + port@0 { + reg = <0>; + + mipi_csi0_ep: endpoint { + remote-endpoint = <&ar0521_out>; + data-lanes = <1 2 3 4>; + +#if 0 + /* According to calculations in the mainline imx8mm + * CSI-2 driver this should be 7 for pixelclock + * of 168MHz. + * + * clock_freq = 168 * 8 (bpp) / 4 (lanes) / 2 (DDR) + * = 168 Mhz + * lane_rate = clock_freq * 2 = 336 Mbps + * ths_settle = (lane_rate - 5000000) / 45000000 + * = 7 + * + * This indeed has to be confirmed, specifically where + * the 5000000 and 45000000 values come from. + */ + csis-hs-settle = <7>; + + /* + * 0 = 110ns to 280ns (v0.87 to v1.00) + * 2 = 150 ns to 430ns (v0.83 to v0.86) + * + * BSP has this set to 2 (set here) + * mainline CSI-2 driver uses 0 (set in the driver) + */ + csis-clk-settle = <2>; + csis-wclk; +#endif + }; + }; + + port@1 { + reg = <1>; + mipi_csi_0_out: endpoint { + remote-endpoint = <&isp0_in>; + }; + }; + }; +}; + +&isp_0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + isp0_in: endpoint { + remote-endpoint = <&mipi_csi_0_out>; + bus-type = <MEDIA_BUS_TYPE_PARALLEL>; + }; + }; + + }; +}; + /* console */ &uart2 { pinctrl-names = "default"; @@ -108,6 +213,18 @@ }; &iomuxc { + pinctrl_csi0_pwn: csi0_pwn_grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x19 + >; + }; + + pinctrl_csi0_rst: csi0_rst_grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x19 + >; + }; + pinctrl_eqos: eqosgrp { fsl,pins = < MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 @@ -128,6 +245,13 @@ >; }; + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3 + >; + }; + pinctrl_uart2: uart2grp { fsl,pins = < MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x40 |