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authorStephen Boyd <sboyd@kernel.org>2022-10-04 10:54:14 -0700
committerStephen Boyd <sboyd@kernel.org>2022-10-04 10:54:14 -0700
commitb7f257ceb3c88ee3e2c6b0d1db703c818d3971f1 (patch)
treec64cbd2b28d920758c3582763b8c787a0e0e9fbb
parent26bebbfed5bd06fd7202fd1befa6c2c935a593e8 (diff)
parent1d7d20658534c7d36fe6f4252f6f1a27d9631a99 (diff)
parentaf3bd36573e3686a82ebb79114cd9c9ccbd5374f (diff)
parent117a1542c0bc9bcce0c5b9bc63ff54dc967acdf5 (diff)
parent3475c885480817c9e340fb75b9f6e31b19331ba9 (diff)
downloadstaging-b7f257ceb3c88ee3e2c6b0d1db703c818d3971f1.tar.gz
Merge branches 'clk-fixed-rate', 'clk-spreadtrum', 'clk-pxa' and 'clk-ti' into clk-next
- More devm helpers for fixed rate registration - Add Spreadtrum UMS512 SoC clk support - Various PXA168 clk driver fixes * clk-fixed-rate: clk: fixed-rate: add devm_clk_hw_register_fixed_rate clk: asm9260: use parent index to link the reference clock * clk-spreadtrum: clk: sprd: Add clocks support for UMS512 * clk-pxa: clk: pxa: add a check for the return value of kzalloc() clk: mmp: pxa168: control shared SDH bits with separate clock dt-bindings: marvell,pxa168: add clock ids for SDH AXI clocks clk: mmp: pxa168: add clocks for SDH2 and SDH3 dt-bindings: marvell,pxa168: add clock id for SDH3 clk: mmp: pxa168: fix GPIO clock enable bits clk: mmp: pxa168: add muxes for more peripherals clk: mmp: pxa168: fix incorrect parent clocks clk: mmp: pxa168: fix const-correctness clk: mmp: pxa168: add new clocks for peripherals dt-bindings: marvell,pxa168: add clock ids for additional dividers clk: mmp: pxa168: fix incorrect dividers clk: mmp: pxa168: add additional register defines * clk-ti: clk: davinci: cfgchip: Use dev_err_probe() helper clk: davinci: pll: fix spelling typo in comment MAINTAINERS: add header file to TI DAVINCI SERIES CLOCK DRIVER