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| author | Jesse Barnes <jbarnes@virtuousgeek.org> | 2012-10-18 10:28:51 -0500 |
|---|---|---|
| committer | Jesse Barnes <jbarnes@virtuousgeek.org> | 2012-10-25 13:24:07 -0500 |
| commit | 060dc19db758784490f38f902d144fac4f1e9585 (patch) | |
| tree | e2d3c2929eba2da96b80e69d4571c20020a7863e | |
| parent | 3c89730359c702ca0c67ddc179f125d13af3ea9a (diff) | |
| download | drm-intel-workarounds.tar.gz | |
drm/i915: add clock gating regs to VLV offset check functionworkarounds
So we can write them properly.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
| -rw-r--r-- | drivers/gpu/drm/i915/i915_drv.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 6f03b2656bf83a..39c53ad1d8edce 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -1130,8 +1130,17 @@ static bool IS_DISPLAYREG(u32 reg) return false; switch (reg) { + case _3D_CHICKEN3: + case IVB_CHICKEN3: + case GEN7_COMMON_SLICE_CHICKEN1: + case GEN7_L3CNTLREG1: + case GEN7_L3_CHICKEN_MODE_REGISTER: case GEN7_ROW_CHICKEN2: + case GEN7_L3SQCREG4: + case GEN7_SQ_CHICKEN_MBCUNIT_CONFIG: case GEN7_HALF_SLICE_CHICKEN1: + case GEN6_MBCTL: + case GEN6_UCGCTL2: return false; default: break; |