diff options
| author | Takeshi Kihara <takeshi.kihara.df@renesas.com> | 2019-01-28 18:49:34 +0900 |
|---|---|---|
| committer | Ryo Kataoka <ryo.kataoka.wt@renesas.com> | 2019-03-22 20:50:38 +0900 |
| commit | c922c328f1383099b600690844ed029c167e8520 (patch) | |
| tree | 68f2fc33054fc7e04f89af6872e98c169c2b537a | |
| parent | c3cbd3684e52686f65a24baa9ea5803c557c4d67 (diff) | |
| download | renesas-bsp-c922c328f1383099b600690844ed029c167e8520.tar.gz | |
arm64: dts: r8a7795: Fix clock, reset and power domain for iVDP1C
According to the R-Car Gen3 Hardware Manual Rev 1.50, the module clock
status, module clock control, and reset control bit of the iVDP1C module
on R-Car H3 ES2.0 or later was changed from bit28 to bit30. And the power
domain of the iVDP1C module was changed from A2VC0 to A2VC1.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi | 8 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r8a7795.dtsi | 8 |
2 files changed, 11 insertions, 5 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi index 600f56c1be324..9e2e5b56f2cd4 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi @@ -2,7 +2,7 @@ /* * Device Tree Source for the R-Car H3 (R8A77950) ES1.x SoC * - * Copyright (C) 2015 Renesas Electronics Corp. + * Copyright (C) 2015-2019 Renesas Electronics Corp. */ #include "r8a7795.dtsi" @@ -50,6 +50,12 @@ /delete-node/ dma-controller@e6460000; /delete-node/ dma-controller@e6470000; + ivdp1c: vcp4@fe8d0000 { + clocks = <&cpg CPG_MOD 128>; + power-domains = <&sysc R8A7795_PD_A2VC0>; + resets = <&cpg 128>; + }; + vcp4@fe8f0000 { compatible = "renesas,vcp4-vcpl4"; reg = <0 0xfe8f0000 0 0x200>, <0 0xfe8f0200 0 0x200>; diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index 1896e5250dffc..81d0f1d786404 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -2,7 +2,7 @@ /* * Device Tree Source for the R-Car H3 (R8A77950) SoC * - * Copyright (C) 2015-2017 Renesas Electronics Corp. + * Copyright (C) 2015-2019 Renesas Electronics Corp. */ #include <dt-bindings/clock/r8a7795-cpg-mssr.h> @@ -3032,9 +3032,9 @@ interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 128>; - power-domains = <&sysc R8A7795_PD_A2VC0>; - resets = <&cpg 128>; + clocks = <&cpg CPG_MOD 130>; + power-domains = <&sysc R8A7795_PD_A2VC1>; + resets = <&cpg 130>; renesas,#ch = <2>; renesas,#fcp_ch = <0>; }; |