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| author | Oleksandr Tyshchenko <oleksandr_tyshchenko@epam.com> | 2018-08-29 18:00:19 +0900 |
|---|---|---|
| committer | Ryo Kataoka <ryo.kataoka.wt@renesas.com> | 2018-12-07 19:57:03 +0900 |
| commit | 97887e97ec88b6feff413ef99977f87ed8c8b08d (patch) | |
| tree | bdfe1b0d27f00c810c0b98f84dacd8d7e3926604 | |
| parent | 1e95dd6dd2e5dbed0112b3ac77862b063ef5b73f (diff) | |
| download | renesas-bsp-97887e97ec88b6feff413ef99977f87ed8c8b08d.tar.gz | |
arm64: dts: r8a7795-h3ulcb: Fix source clock for DU2
This patch changes the clock for DU2, supply the initial value of
versaclock directly to the DU2.
The initial value of versaclock out4 is 33 MHz.
Signed-off-by: Oleksandr Tyshchenko <oleksandr_tyshchenko@epam.com>
Signed-off-by: Yusuke Goda <yusuke.goda.sx@renesas.com>
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts index 7ed91ed02a287..87132c0fe4b41 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts @@ -81,6 +81,13 @@ /* Initial value of versaclock out3 */ clock-frequency = <33000000>; }; + + versaclock5_out4: versaclk-4 { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* Initial value of versaclock out4 */ + clock-frequency = <33000000>; + }; }; &du { @@ -90,7 +97,7 @@ <&cpg CPG_MOD 721>, <&versaclock5 1>, <&versaclock5_out3>, - <&versaclock5 4>, + <&versaclock5_out4>, <&versaclock5 2>; clock-names = "du.0", "du.1", "du.2", "du.3", "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3"; |