diff options
| author | Yusuke Goda <yusuke.goda.sx@renesas.com> | 2019-01-17 06:04:21 +0000 |
|---|---|---|
| committer | Ryo Kataoka <ryo.kataoka.wt@renesas.com> | 2019-03-22 20:50:40 +0900 |
| commit | 44145606a843a196841d9b4d4b3669f7feae38a8 (patch) | |
| tree | 21ba49aa1188d7e8c349b2e8f18b1c01a25bf189 | |
| parent | b8d5de71addccb19c14f077625fdd562c52dd389 (diff) | |
| download | renesas-bsp-44145606a843a196841d9b4d4b3669f7feae38a8.tar.gz | |
arm64: dts: r8a77965-m3nulcb: Fix source clock for DU
ULCB Versaclock default output clock is based on its ROM code,
and ULCB case is 33HMz.
But current DT is missing such information, and Versaclock driver
can't handle it today.
We need to update Versaclock driver to handle it correctly.
But as Quick-Hack, this patch indicates it via versaclock5_out3
temporally.
Signed-off-by: Yusuke Goda <yusuke.goda.sx@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r8a77965-m3nulcb.dts | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a77965-m3nulcb.dts b/arch/arm64/boot/dts/renesas/r8a77965-m3nulcb.dts index 5158094feaad1..0d3a6e65a77e4 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965-m3nulcb.dts +++ b/arch/arm64/boot/dts/renesas/r8a77965-m3nulcb.dts @@ -59,6 +59,13 @@ vspm_if { compatible = "renesas,vspm_if"; }; + + versaclock5_out3: versaclk-3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* Initial value of versaclock out3 */ + clock-frequency = <33000000>; + }; }; &du { @@ -66,7 +73,7 @@ <&cpg CPG_MOD 723>, <&cpg CPG_MOD 721>, <&versaclock5 1>, - <&versaclock5 3>, + <&versaclock5_out3>, <&versaclock5 2>; clock-names = "du.0", "du.1", "du.3", "dclkin.0", "dclkin.1", "dclkin.3"; |