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| author | Koji Matsuoka <koji.matsuoka.xm@renesas.com> | 2018-03-14 10:01:24 +0900 |
|---|---|---|
| committer | Ryo Kataoka <ryo.kataoka.wt@renesas.com> | 2018-12-07 19:57:02 +0900 |
| commit | 392e61f1bf6029b8a160260b7b96b60fd16bee97 (patch) | |
| tree | dd265c0485c29c4b31de3060aca67ab71d43dd36 | |
| parent | c2ac6e5c33685bba77844db3f5322102db7242d4 (diff) | |
| download | renesas-bsp-392e61f1bf6029b8a160260b7b96b60fd16bee97.tar.gz | |
arm64: dts: r8a7796-m3ulcb: Fix souce clock for DU
This patch changes the clock for DU, supply the initial value of
versaclock directly to the DU.
The initial value of versaclock out3 is 33 MHz.
Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts index 3e6a4e111b38d..c962301b5f340 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts +++ b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts @@ -70,6 +70,13 @@ vspm_if { compatible = "renesas,vspm_if"; }; + + versaclock5_out3: versaclk-3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* Initial value of versaclock out3 */ + clock-frequency = <33000000>; + }; }; &a53_0 { @@ -93,7 +100,7 @@ <&cpg CPG_MOD 723>, <&cpg CPG_MOD 722>, <&versaclock5 1>, - <&versaclock5 3>, + <&versaclock5_out3>, <&versaclock5 2>; clock-names = "du.0", "du.1", "du.2", "dclkin.0", "dclkin.1", "dclkin.2"; |