diff options
| author | Mauro Carvalho Chehab <mchehab+huawei@kernel.org> | 2020-06-01 09:02:46 +0200 |
|---|---|---|
| committer | Mauro Carvalho Chehab <mchehab+huawei@kernel.org> | 2020-06-11 19:10:56 +0200 |
| commit | 17c3827b4c5744abed8cfc6bf86fdbedf0ed61d2 (patch) | |
| tree | 5e0a036989795da33380ee7cb53076fd74641303 | |
| parent | c371af686972ee2a7946b56f6b6b42bcb80d2091 (diff) | |
| download | tty-17c3827b4c5744abed8cfc6bf86fdbedf0ed61d2.tar.gz | |
media: atomisp: don't set hpll_freq twice with different values
The logic which sets the hpll_freq for BYT sets hpll_freq
to 1600MHz, but ignores it, and sets it again after reading
from-device-specific EFI vars (this time, using a default
of 2000MHz).
Remove the first set, as this will be overriden anyway.
While here, do minor adjustments on comments and on a
printk message.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
| -rw-r--r-- | drivers/staging/media/atomisp/pci/atomisp_v4l2.c | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/drivers/staging/media/atomisp/pci/atomisp_v4l2.c b/drivers/staging/media/atomisp/pci/atomisp_v4l2.c index d31e88d04d555f..03c0c5e91f6fb4 100644 --- a/drivers/staging/media/atomisp/pci/atomisp_v4l2.c +++ b/drivers/staging/media/atomisp/pci/atomisp_v4l2.c @@ -1653,10 +1653,12 @@ static int atomisp_pci_probe(struct pci_dev *dev, * resolution accordingly. */ isp->dfs = &dfs_config_byt; - isp->hpll_freq = HPLL_FREQ_1600MHZ; - /* HPLL frequency is known to be device-specific, but we don't + + /* + * HPLL frequency is known to be device-specific, but we don't * have specs yet for exactly how it varies. Default to - * BYT-CR but let provisioning set it via EFI variable */ + * BYT-CR but let provisioning set it via EFI variable + */ isp->hpll_freq = gmin_get_var_int(&dev->dev, false, "HpllFreq", HPLL_FREQ_2000MHZ); @@ -1708,7 +1710,7 @@ static int atomisp_pci_probe(struct pci_dev *dev, default: isp->hpll_freq = HPLL_FREQ_1600MHZ; dev_warn(isp->dev, - "read HPLL from cck failed.default 1600MHz.\n"); + "read HPLL from cck failed. Default to 1600 MHz.\n"); } break; default: |