more patches added

4 files changed, 252 insertions, 0 deletions

diff --git a/pci/pci-allow-msi-to-work-on-kexec-kernel.patch b/pci/pci-allow-msi-to-work-on-kexec-kernel.patch
new file mode 100644
index 0000000000000..922c97596c255
--- /dev/null
+++ b/pci/pci-allow-msi-to-work-on-kexec-kernel.patch
@@ -0,0 +1,45 @@
+From owner-linux-pci@atrey.karlin.mff.cuni.cz Tue May 23 10:16:46 2006
+Date: Tue, 23 May 2006 10:14:36 -0700
+From: Rajesh Shah <rajesh.shah@intel.com>
+To: gregkh@suse.de, <ak@suse.de>
+Subject: PCI: Allow MSI to work on kexec kernel
+Message-ID: <20060523101436.A25249@unix-os.sc.intel.com>
+Content-Disposition: inline
+
+We recently ran into a problem where the e1000 device failed to
+work properly on the kexec kernel. MSI was enabled for the
+device in the main kernel when it crashed. The e1000 driver
+tried to enable MSI on the kexec kernel, but the code bailed
+early when it found that MSI was already enabled in the hardware,
+even though the software state was not properly set up in the
+kexec'd kernel. This patch fixes the problem by moving the
+early return to after making sure that the software state
+is properly initialized.
+
+Signed-off-by: Rajesh Shah <rajesh.shah@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
+
+---
+ drivers/pci/msi.c |    7 +++----
+ 1 file changed, 3 insertions(+), 4 deletions(-)
+
+--- gregkh-2.6.orig/drivers/pci/msi.c
++++ gregkh-2.6/drivers/pci/msi.c
+@@ -940,14 +940,13 @@ int pci_enable_msi(struct pci_dev* dev)
+ 	if (!pos)
+ 		return -EINVAL;
+ 
+-	pci_read_config_word(dev, msi_control_reg(pos), &control);
+-	if (control & PCI_MSI_FLAGS_ENABLE)
+-		return 0;			/* Already in MSI mode */
+-
+ 	if (!msi_lookup_vector(dev, PCI_CAP_ID_MSI)) {
+ 		/* Lookup Sucess */
+ 		unsigned long flags;
+ 
++		pci_read_config_word(dev, msi_control_reg(pos), &control);
++		if (control & PCI_MSI_FLAGS_ENABLE)
++			return 0;	/* Already in MSI mode */
+ 		spin_lock_irqsave(&msi_lock, flags);
+ 		if (!vector_irq[dev->irq]) {
+ 			msi_desc[dev->irq]->msi_attrib.state = 0;
diff --git a/pci/pci-amd-8131-msi-quirk-called-too-late-bus_flags-not-inherited.patch b/pci/pci-amd-8131-msi-quirk-called-too-late-bus_flags-not-inherited.patch
new file mode 100644
index 0000000000000..9c62a81e1b19e
--- /dev/null
+++ b/pci/pci-amd-8131-msi-quirk-called-too-late-bus_flags-not-inherited.patch
@@ -0,0 +1,69 @@
+From bgoglin@myri.com Tue May 23 00:05:51 2006
+Date: Tue, 23 May 2006 03:05:27 -0400
+From: Brice Goglin <brice@myri.com>
+To: Greg KH <gregkh@suse.de>
+Cc: "Michael S. Tsirkin" <mst@mellanox.co.il>
+Subject: PCI: AMD 8131 MSI quirk called too late, bus_flags not inherited ?
+Message-ID: <20060523070526.GA30499@myri.com>
+Content-Disposition: inline
+
+The PCI_BUS_FLAGS_NO_MSI bus flags does not appear do be inherited
+correctly from the amd8131 MSI quirk to its parent busses. It makes
+devices behind a bridge behind amd8131 try to enable MSI while the
+amd8131 does not support it.
+We fix this by looking at flags of all parent busses in
+pci_enable_msi() and pci_enable_msix().
+
+By the way, also add the missing dev->no_msi check in pci_enable_msix()
+
+Signed-off-by: Brice Goglin <brice@myri.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
+
+---
+ drivers/pci/msi.c |   14 ++++++++++++--
+ 1 file changed, 12 insertions(+), 2 deletions(-)
+
+--- gregkh-2.6.orig/drivers/pci/msi.c
++++ gregkh-2.6/drivers/pci/msi.c
+@@ -916,6 +916,7 @@ static int msix_capability_init(struct p
+  **/
+ int pci_enable_msi(struct pci_dev* dev)
+ {
++	struct pci_bus *bus;
+ 	int pos, temp, status = -EINVAL;
+ 	u16 control;
+ 
+@@ -925,8 +926,9 @@ int pci_enable_msi(struct pci_dev* dev)
+ 	if (dev->no_msi)
+ 		return status;
+ 
+-	if (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MSI)
+-		return -EINVAL;
++	for (bus = dev->bus; bus; bus = bus->parent)
++		if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI)
++			return -EINVAL;
+ 
+ 	temp = dev->irq;
+ 
+@@ -1162,6 +1164,7 @@ static int reroute_msix_table(int head, 
+  **/
+ int pci_enable_msix(struct pci_dev* dev, struct msix_entry *entries, int nvec)
+ {
++	struct pci_bus *bus;
+ 	int status, pos, nr_entries, free_vectors;
+ 	int i, j, temp;
+ 	u16 control;
+@@ -1170,6 +1173,13 @@ int pci_enable_msix(struct pci_dev* dev,
+ 	if (!pci_msi_enable || !dev || !entries)
+  		return -EINVAL;
+ 
++	if (dev->no_msi)
++		return -EINVAL;
++
++	for (bus = dev->bus; bus; bus = bus->parent)
++		if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI)
++			return -EINVAL;
++
+ 	status = msi_init();
+ 	if (status < 0)
+ 		return status;
diff --git a/pci/pci-disable-msi-mode-in-pci_disable_device.patch b/pci/pci-disable-msi-mode-in-pci_disable_device.patch
new file mode 100644
index 0000000000000..c8139b83af2e9
--- /dev/null
+++ b/pci/pci-disable-msi-mode-in-pci_disable_device.patch
@@ -0,0 +1,97 @@
+From shaohua.li@intel.com Thu May 25 20:00:07 2006
+Subject: PCI: disable msi mode in pci_disable_device
+From: Shaohua Li <shaohua.li@intel.com>
+Cc: Andrew Morton <akpm@osdl.org>, Greg <greg@kroah.com>, tom long <tom.l.nguyen@intel.com>, Brice Goglin <brice@myri.com>, Rajesh Shah <rajesh.shah@intel.com>
+Date: Fri, 26 May 2006 10:58:27 +0800
+Message-Id: <1148612307.32046.132.camel@sli10-desk.sh.intel.com>
+
+Brice said the pci_save_msi_state breaks his driver in his special usage
+(not in suspend/resume), as pci_save_msi_state will disable msi mode. In
+his usage, pci_save_state will be called at runtime, and later (after
+the device operates for some time and has an error) pci_restore_state
+will be called.
+In another hand, suspend/resume needs disable msi mode, as device should
+stop working completely. This patch try to workaround this issue.
+Drivers are expected call pci_disable_device in suspend time after
+pci_save_state.
+
+Signed-off-by: Shaohua Li <shaohua.li@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
+
+---
+ drivers/pci/msi.c   |    6 ++++--
+ drivers/pci/pci.c   |    9 ++++++++-
+ include/linux/pci.h |    2 ++
+ 3 files changed, 14 insertions(+), 3 deletions(-)
+
+--- gregkh-2.6.orig/drivers/pci/msi.c
++++ gregkh-2.6/drivers/pci/msi.c
+@@ -453,9 +453,11 @@ static void enable_msi_mode(struct pci_d
+ 		/* Set enabled bits to single MSI & enable MSI_enable bit */
+ 		msi_enable(control, 1);
+ 		pci_write_config_word(dev, msi_control_reg(pos), control);
++		dev->msi_enabled = 1;
+ 	} else {
+ 		msix_enable(control);
+ 		pci_write_config_word(dev, msi_control_reg(pos), control);
++		dev->msix_enabled = 1;
+ 	}
+     	if (pci_find_capability(dev, PCI_CAP_ID_EXP)) {
+ 		/* PCI Express Endpoint device detected */
+@@ -472,9 +474,11 @@ void disable_msi_mode(struct pci_dev *de
+ 		/* Set enabled bits to single MSI & enable MSI_enable bit */
+ 		msi_disable(control);
+ 		pci_write_config_word(dev, msi_control_reg(pos), control);
++		dev->msi_enabled = 0;
+ 	} else {
+ 		msix_disable(control);
+ 		pci_write_config_word(dev, msi_control_reg(pos), control);
++		dev->msix_enabled = 0;
+ 	}
+     	if (pci_find_capability(dev, PCI_CAP_ID_EXP)) {
+ 		/* PCI Express Endpoint device detected */
+@@ -549,7 +553,6 @@ int pci_save_msi_state(struct pci_dev *d
+ 		pci_read_config_dword(dev, pos + PCI_MSI_DATA_32, &cap[i++]);
+ 	if (control & PCI_MSI_FLAGS_MASKBIT)
+ 		pci_read_config_dword(dev, pos + PCI_MSI_MASK_BIT, &cap[i++]);
+-	disable_msi_mode(dev, pos, PCI_CAP_ID_MSI);
+ 	save_state->cap_nr = PCI_CAP_ID_MSI;
+ 	pci_add_saved_cap(dev, save_state);
+ 	return 0;
+@@ -639,7 +642,6 @@ int pci_save_msix_state(struct pci_dev *
+ 	}
+ 	dev->irq = temp;
+ 
+-	disable_msi_mode(dev, pos, PCI_CAP_ID_MSIX);
+ 	save_state->cap_nr = PCI_CAP_ID_MSIX;
+ 	pci_add_saved_cap(dev, save_state);
+ 	return 0;
+--- gregkh-2.6.orig/drivers/pci/pci.c
++++ gregkh-2.6/drivers/pci/pci.c
+@@ -549,7 +549,14 @@ void
+ pci_disable_device(struct pci_dev *dev)
+ {
+ 	u16 pci_command;
+-	
++
++	if (dev->msi_enabled)
++		disable_msi_mode(dev, pci_find_capability(dev, PCI_CAP_ID_MSI),
++			PCI_CAP_ID_MSI);
++	if (dev->msix_enabled)
++		disable_msi_mode(dev, pci_find_capability(dev, PCI_CAP_ID_MSI),
++			PCI_CAP_ID_MSIX);
++
+ 	pci_read_config_word(dev, PCI_COMMAND, &pci_command);
+ 	if (pci_command & PCI_COMMAND_MASTER) {
+ 		pci_command &= ~PCI_COMMAND_MASTER;
+--- gregkh-2.6.orig/include/linux/pci.h
++++ gregkh-2.6/include/linux/pci.h
+@@ -164,6 +164,8 @@ struct pci_dev {
+ 	unsigned int	no_msi:1;	/* device may not use msi */
+ 	unsigned int	block_ucfg_access:1;	/* userspace config space access is blocked */
+ 	unsigned int	broken_parity_status:1;	/* Device generates false positive parity */
++	unsigned int 	msi_enabled:1;
++	unsigned int	msix_enabled:1;
+ 
+ 	u32		saved_config_space[16]; /* config space saved at suspend time */
+ 	struct hlist_head saved_cap_space;
diff --git a/pci/pci-pci_ids-add-new-device-ids.patch b/pci/pci-pci_ids-add-new-device-ids.patch
new file mode 100644
index 0000000000000..2047c53a2af39
--- /dev/null
+++ b/pci/pci-pci_ids-add-new-device-ids.patch
@@ -0,0 +1,41 @@
+From akpm@osdl.org Thu May 25 14:43:24 2006
+Message-Id: <200605252143.k4PLh9oT011089@shell0.pdx.osdl.net>
+From: Ayaz Abdulla <aabdulla@nvidia.com>
+Subject: PCI: pci_ids: add new device ids
+To: aabdulla@nvidia.com, greg@kroah.com, jeff@garzik.org
+Date: Thu, 25 May 2006 14:42:40 -0700
+
+From: Ayaz Abdulla <aabdulla@nvidia.com>
+
+Add new device ids for MCP61 and MCP65 chips.
+
+Signed-off-by: Ayaz Abdulla <aabdulla@nvidia.com>
+Cc: Jeff Garzik <jeff@garzik.org>
+Signed-off-by: Andrew Morton <akpm@osdl.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
+
+---
+ include/linux/pci_ids.h |   12 ++++++++++--
+ 1 file changed, 10 insertions(+), 2 deletions(-)
+
+--- gregkh-2.6.orig/include/linux/pci_ids.h
++++ gregkh-2.6/include/linux/pci_ids.h
+@@ -1190,8 +1190,16 @@
+ #define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5700_2    0x0348
+ #define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_GO1000       0x034C
+ #define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_1100         0x034E
+-#define PCI_DEVICE_ID_NVIDIA_NVENET_14              0x0372
+-#define PCI_DEVICE_ID_NVIDIA_NVENET_15              0x0373
++#define PCI_DEVICE_ID_NVIDIA_NVENET_14		0x0372
++#define PCI_DEVICE_ID_NVIDIA_NVENET_15		0x0373
++#define PCI_DEVICE_ID_NVIDIA_NVENET_16		0x03E5
++#define PCI_DEVICE_ID_NVIDIA_NVENET_17		0x03E6
++#define PCI_DEVICE_ID_NVIDIA_NVENET_18		0x03EE
++#define PCI_DEVICE_ID_NVIDIA_NVENET_19		0x03EF
++#define PCI_DEVICE_ID_NVIDIA_NVENET_20		0x0450
++#define PCI_DEVICE_ID_NVIDIA_NVENET_21		0x0451
++#define PCI_DEVICE_ID_NVIDIA_NVENET_22		0x0452
++#define PCI_DEVICE_ID_NVIDIA_NVENET_23		0x0453
+ 
+ #define PCI_VENDOR_ID_IMS		0x10e0
+ #define PCI_DEVICE_ID_IMS_TT128		0x9128