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path: root/patches.at91/0145-media-at91sam9x5-video-align-DMA-descriptors-on-64-b.patch
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From d97e93bccbd81a88c5c60553b1dca5d59f23aa08 Mon Sep 17 00:00:00 2001
From: Nicolas Ferre <nicolas.ferre@atmel.com>
Date: Tue, 16 Oct 2012 18:29:45 +0200
Subject: media/at91sam9x5-video: align DMA descriptors on 64 bits

Needed for future revisions of the LCD ip

Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
---
 drivers/media/video/at91sam9x5-video.c | 46 ++++++++++++++++++++--------------
 1 file changed, 27 insertions(+), 19 deletions(-)

diff --git a/drivers/media/video/at91sam9x5-video.c b/drivers/media/video/at91sam9x5-video.c
index c83dad1..9d7e6c5 100644
--- a/drivers/media/video/at91sam9x5-video.c
+++ b/drivers/media/video/at91sam9x5-video.c
@@ -375,7 +375,7 @@ static void at91sam9x5_video_show_buf(struct at91sam9x5_video_priv *priv,
 	struct v4l2_pix_format *pix = &priv->fmt_vid_out_cur;
 	/* XXX: format dependant */
 	size_t offset_dmadesc = ALIGN(pix->width * pix->height +
-			ALIGN(pix->width, 2) * ALIGN(pix->height, 2) / 2, 32);
+			ALIGN(pix->width, 2) * ALIGN(pix->height, 2) / 2, 64);
 	u32 *dmadesc = vaddr + offset_dmadesc;
 	u32 heocher;
 
@@ -388,23 +388,30 @@ static void at91sam9x5_video_show_buf(struct at91sam9x5_video_priv *priv,
 	}
 
 	debug("vout=%ux%u, heocher=%08x\n", pix->width, pix->height, heocher);
+	debug("dmadesc @ 0x%08x\n", dmadesc);
+	debug("dmadesc u @ 0x%08x\n", &dmadesc[4]);
+	debug("dmadesc v @ 0x%08x\n", &dmadesc[8]);
 
 	dmadesc[0] = buffer + priv->y_offset;
 	dmadesc[1] = REG_HEOxCTRL_DFETCH;
 	dmadesc[2] = buffer + offset_dmadesc;
+	/* dmadesc[3] not used to align U plane descriptor */
 
 	if (priv->u_planeno >= 0) {
-		dmadesc[3] = vb2_dma_contig_plane_dma_addr(vb, priv->u_planeno) +
+		dmadesc[4] = vb2_dma_contig_plane_dma_addr(vb, priv->u_planeno) +
 			priv->u_offset;
-		dmadesc[4] = REG_HEOxCTRL_DFETCH;
-		dmadesc[5] = buffer + offset_dmadesc + 3 * 4;
+		dmadesc[5] = REG_HEOxCTRL_DFETCH;
+		/* link to physical address of this U descriptor */
+		dmadesc[6] = buffer + offset_dmadesc + 4 * 4;
 	}
+	/* dmadesc[7] not used to align V plane descriptor */
 
 	if (priv->v_planeno >= 0) {
-		dmadesc[6] = vb2_dma_contig_plane_dma_addr(vb, priv->v_planeno) +
+		dmadesc[8] = vb2_dma_contig_plane_dma_addr(vb, priv->v_planeno) +
 			priv->v_offset;
-		dmadesc[7] = REG_HEOxCTRL_DFETCH;
-		dmadesc[8] = buffer + offset_dmadesc + 6 * 4;
+		dmadesc[9] = REG_HEOxCTRL_DFETCH;
+		/* link to physical address of this V descriptor */
+		dmadesc[10] = buffer + offset_dmadesc + 8 * 4;
 	}
 
 
@@ -415,11 +422,11 @@ static void at91sam9x5_video_show_buf(struct at91sam9x5_video_priv *priv,
 
 		if (priv->u_planeno >= 0)
 			at91sam9x5_video_write32(priv,
-					REG_HEOUHEAD, dmadesc[5]);
+					REG_HEOUHEAD, dmadesc[6]);
 
 		if (priv->v_planeno >= 0)
 			at91sam9x5_video_write32(priv,
-					REG_HEOVHEAD, dmadesc[8]);
+					REG_HEOVHEAD, dmadesc[10]);
 
 		at91sam9x5_video_write32(priv,
 				REG_HEOCHER, heocher | REG_HEOCHER_A2QEN);
@@ -432,20 +439,20 @@ static void at91sam9x5_video_show_buf(struct at91sam9x5_video_priv *priv,
 
 		if (priv->u_planeno >= 0) {
 			at91sam9x5_video_write32(priv,
-					REG_HEOUADDR, dmadesc[3]);
+					REG_HEOUADDR, dmadesc[4]);
 			at91sam9x5_video_write32(priv,
-					REG_HEOUCTRL, dmadesc[4]);
+					REG_HEOUCTRL, dmadesc[5]);
 			at91sam9x5_video_write32(priv,
-					REG_HEOUNEXT, dmadesc[5]);
+					REG_HEOUNEXT, dmadesc[6]);
 		}
 
 		if (priv->v_planeno >= 0) {
 			at91sam9x5_video_write32(priv,
-					REG_HEOVADDR, dmadesc[6]);
+					REG_HEOVADDR, dmadesc[8]);
 			at91sam9x5_video_write32(priv,
-					REG_HEOVCTRL, dmadesc[7]);
+					REG_HEOVCTRL, dmadesc[9]);
 			at91sam9x5_video_write32(priv,
-					REG_HEOVNEXT, dmadesc[8]);
+					REG_HEOVNEXT, dmadesc[10]);
 		}
 
 		at91sam9x5_video_write32(priv, REG_HEOCHER,
@@ -713,14 +720,15 @@ static int at91sam9x5_video_vb_queue_setup(struct vb2_queue *q,
 	*num_planes = 1;
 
 	/*
-	 * The last 9 (aligned) words are used for the 3 dma descriptors (3
-	 * 32-bit words each). The additional 32 bits are for alignment.
+	 * The last 9 (64 bits aligned) words are used for the 3 dma
+	 * descriptors (3 * 32-bit words each).
+	 * The additional 64 + 2 * 32 bits are for alignment.
 	 * XXX: is that allowed and done right?
 	 * XXX: format-dependant
 	 */
 	sizes[0] = pix->width * pix->height +
 		ALIGN(pix->width, 2) * ALIGN(pix->height, 2) / 2 +
-		10 * 32;
+		9 * 32 + 128;
 	priv->plane_size[0] = sizes[0];
 
 	alloc_ctxs[0] = priv->alloc_ctx;
@@ -787,7 +795,7 @@ static int at91sam9x5_video_vb_buf_prepare(struct vb2_buffer *vb)
 	/* XXX: format-dependant */
 	if (vb->v4l2_planes[0].length < pix->width * pix->height +
 			ALIGN(pix->width, 2) * ALIGN(pix->height, 2) / 2 +
-			10 * 32)
+			9 * 32 + 128)
 		return -EINVAL;
 
 	return 0;
-- 
1.8.0.197.g5a90748